commit 3511d68eb9101ca8cb68c5b87d5392a46e62b6fd Author: cfif Date: Mon Aug 24 15:40:37 2026 +0300 Init Mono diff --git a/APP/Clock.c b/APP/Clock.c new file mode 100644 index 0000000..120ea47 --- /dev/null +++ b/APP/Clock.c @@ -0,0 +1,299 @@ +#include "Clock.h" + + +/* ################################################################################## */ +/* ################################### Type define ################################## */ + +/* PCBA external oscillator value, these macro is user defined. */ +/* FOSC/SOSC clock need to manually configuration according to PCBA XTAL value + * in SOSC/FOSc configuration. + * Current default value is the XTAL value on EVB board. */ + + +/* ################################################################################## */ +/* ########################### Local Prototype Functions ############################ */ +static void Bsp_SCG_Init(void); + +static void Bsp_PCC_Init(void); + +/* ################################################################################## */ +/* ################################ Local Functions ################################# */ + + +/** + * @brief Local SCG initial + * + */ + +// Ядро процессора: 240 МГц +// Системная шина: 120 МГц +// Медленная периферия: 120 МГц +// PLL0/PLL1: 240 МГц +// FOSC: 24 МГц +// SIRC: 12 МГц + +static void Bsp_SCG_Init(void) { + + SCG_Deinit(); + + /* Enable FOSC, frequency is 24M, DIVH=DIV1(24M), DIVM=DIV1(24M), DIVL=DIV2(12M)*/ + // FOSC - Внешний кварцевый генератор (Базовый источник 24 МГц) + SCG_FoscType tFoscStruct = + { + .bLock = false, + .bCm = false, + .bCmre = false, + .bSten = false, + .bBypass = false, + .eDivH = SCG_ASYNCCLOCKDIV_BY1, + .eDivM = SCG_ASYNCCLOCKDIV_BY1, + .eDivL = SCG_ASYNCCLOCKDIV_BY2, + }; + SCG_EnableFOSC(&tFoscStruct); + + /* Enable PLL0, frequency is 240M, DIVH=DIV2(120M), DIVM=DIV2(120M), DIVL=DIV4(60M), src=FOSC*/ + /* The value of multiplier factor(FOSC/u8Prediv) between 2 ~ 4 is better*/ + + // FOSC = 24 МГц + // После предделителя: 24 МГц / (11 + 1) = 24 МГц / 12 = 2 МГц + // После умножения: 2 МГц × (239 + 1) = 2 МГц × 240 = 480 МГц + // После постделителя: 480 МГц / 2 = 240 МГц + + SCG_PllType tPll0Struct = + { + .bLock = false, + .bCm = false, + .bCmre = false, + .bSten = false, + .eDivH = SCG_ASYNCCLOCKDIV_BY2, + .eDivM = SCG_ASYNCCLOCKDIV_BY2, + .eDivL = SCG_ASYNCCLOCKDIV_BY4, + .u8Prediv = 11U, + .ePstDiv = SCG_PLLPSTDIV_BY2, + .u16Mult = 239U, + .eSrc = SCG_PLLSOURCE_FOSC + }; + SCG_EnablePLL(SCG_PLL0, &tPll0Struct); + + /* Enable PLL1, frequency is 240M, DIVH=DIV2(120M), DIVM=DIV2(120M), DIVL=DIV4(60M), src=FOSC*/ + /* The value of multiplier factor(FOSC/u8Prediv) between 2 ~ 4 is better*/ + + // Аналогична PLL0, также 240 МГц + // Обычно используется для периферии + + SCG_PllType tPll1Struct = + { + .bLock = false, + .bCm = false, + .bCmre = false, + .bSten = false, + .eDivH = SCG_ASYNCCLOCKDIV_BY2, + .eDivM = SCG_ASYNCCLOCKDIV_BY2, + .eDivL = SCG_ASYNCCLOCKDIV_BY4, + .u8Prediv = 11U, + .ePstDiv = SCG_PLLPSTDIV_BY2, + .u16Mult = 239U, + .eSrc = SCG_PLLSOURCE_FOSC + }; + SCG_EnablePLL(SCG_PLL1, &tPll1Struct); + + /* Enable SIRC DIV, DIVH=DIV1(12M), DIVM=DIV1(12M), DIVL=DIV2(6M) */ + // Резервный источник тактирования + // Меньшая точность, но быстрый запуск + + SCG_SircType tSircStruct = + { + .bLock = false, + .bCm = false, + .bTrEn = false, + .bLpen = false, + .bSten = false, + .eDivH = SCG_ASYNCCLOCKDIV_BY1, + .eDivM = SCG_ASYNCCLOCKDIV_BY1, + .eDivL = SCG_ASYNCCLOCKDIV_BY2, + .u8TrimSrc = 0U + }; + SCG_SetSIRC(&tSircStruct); + + /* Set core clock source from PLL0, DIV_CORE=DIV1(240M), DIV_BUS=DIV2(120M), DIV_SLOW=DIV4(60M)*/ + // Системное тактирование + + //.eSrc = PLL0, // Источник - PLL0 (240 МГц) + //.eDivCore = DIV1, // Ядро: 240 МГц + //.eDivBus = DIV2, // Шина: 120 МГц + //.eDivSlow = DIV2 // Медленная периферия: 120 МГц + + SCG_ClockCtrlType tClockStruct = + { + .bSysClkMonitor = false, + .eSrc = SCG_CLOCK_SRC_PLL0, + .eDivSlow = SCG_CLOCK_DIV_BY2, + .eDivBus = SCG_CLOCK_DIV_BY2, + .eDivCore = SCG_CLOCK_DIV_BY1 + }; + SCG_SetClkCtrl(&tClockStruct); + +} + +/** + * @brief Local PCC Initial + * + */ +static void Bsp_PCC_Init(void) { + PCC_CtrlType bSP_PCC_Config; + + // UART 0 (LIN) + bSP_PCC_Config.eClockName = PCC_CLK_FCUART0; + bSP_PCC_Config.bEn = true; + bSP_PCC_Config.eClkSrc = PCC_CLKGATE_SRC_FOSCDIV; + bSP_PCC_Config.eDivider = PCC_CLK_UNINVOLVED; + + PCC_SetPcc(&bSP_PCC_Config); + + // UART 1 (DBG) + bSP_PCC_Config.eClockName = PCC_CLK_FCUART1; + bSP_PCC_Config.bEn = true; + bSP_PCC_Config.eClkSrc = PCC_CLKGATE_SRC_FOSCDIV; + bSP_PCC_Config.eDivider = PCC_CLK_UNINVOLVED; + + PCC_SetPcc(&bSP_PCC_Config); + + // UART 2 (LIN) + bSP_PCC_Config.eClockName = PCC_CLK_FCUART2; + bSP_PCC_Config.bEn = true; + bSP_PCC_Config.eClkSrc = PCC_CLKGATE_SRC_FOSCDIV; + bSP_PCC_Config.eDivider = PCC_CLK_UNINVOLVED; + + PCC_SetPcc(&bSP_PCC_Config); + + // UART 3 (LIN) + bSP_PCC_Config.eClockName = PCC_CLK_FCUART3; + bSP_PCC_Config.bEn = true; + bSP_PCC_Config.eClkSrc = PCC_CLKGATE_SRC_FOSCDIV; + bSP_PCC_Config.eDivider = PCC_CLK_UNINVOLVED; + + PCC_SetPcc(&bSP_PCC_Config); + + // UART 4 (LIN) + bSP_PCC_Config.eClockName = PCC_CLK_FCUART4; + bSP_PCC_Config.bEn = true; + bSP_PCC_Config.eClkSrc = PCC_CLKGATE_SRC_FOSCDIV; + bSP_PCC_Config.eDivider = PCC_CLK_UNINVOLVED; + + PCC_SetPcc(&bSP_PCC_Config); + + // UART 5 (LIN) + bSP_PCC_Config.eClockName = PCC_CLK_FCUART5; + bSP_PCC_Config.bEn = true; + bSP_PCC_Config.eClkSrc = PCC_CLKGATE_SRC_FOSCDIV; + bSP_PCC_Config.eDivider = PCC_CLK_UNINVOLVED; + + PCC_SetPcc(&bSP_PCC_Config); + + // CAN 0 + bSP_PCC_Config.eClockName = PCC_CLK_FLEXCAN0; + bSP_PCC_Config.bEn = TRUE; + bSP_PCC_Config.eClkSrc = PCC_CLKGATE_SRC_FOSCDIV; + bSP_PCC_Config.eDivider = PCC_CLK_DIV_BY1; + + PCC_SetPcc(&bSP_PCC_Config); + + // CAN 1 + bSP_PCC_Config.eClockName = PCC_CLK_FLEXCAN1; + bSP_PCC_Config.bEn = TRUE; + bSP_PCC_Config.eClkSrc = PCC_CLKGATE_SRC_FOSCDIV; + bSP_PCC_Config.eDivider = PCC_CLK_DIV_BY1; + + PCC_SetPcc(&bSP_PCC_Config); + + // ADC 0 + bSP_PCC_Config.eClockName = PCC_CLK_ADC0; + bSP_PCC_Config.bEn = TRUE; + bSP_PCC_Config.eClkSrc = PCC_CLKGATE_SRC_FOSCDIV; + bSP_PCC_Config.eDivider = PCC_CLK_DIV_BY1; + + PCC_SetPcc(&bSP_PCC_Config); + + // ADC 1 + bSP_PCC_Config.eClockName = PCC_CLK_ADC1; + bSP_PCC_Config.bEn = TRUE; + bSP_PCC_Config.eClkSrc = PCC_CLKGATE_SRC_FOSCDIV; + bSP_PCC_Config.eDivider = PCC_CLK_DIV_BY1; + + PCC_SetPcc(&bSP_PCC_Config); + + // DMA 0 + bSP_PCC_Config.eClockName = PCC_CLK_DMA0; + bSP_PCC_Config.bEn = true; + bSP_PCC_Config.eClkSrc = PCC_CLKGATE_SRC_FOSCDIV; + bSP_PCC_Config.eDivider = PCC_CLK_UNINVOLVED; + + PCC_SetPcc(&bSP_PCC_Config); + + // DMAMUX 0 + bSP_PCC_Config.eClockName = PCC_CLK_DMAMUX0; + bSP_PCC_Config.bEn = true; + bSP_PCC_Config.eClkSrc = PCC_CLKGATE_SRC_FOSCDIV; + bSP_PCC_Config.eDivider = PCC_CLK_UNINVOLVED; + + PCC_SetPcc(&bSP_PCC_Config); + + // CRC + bSP_PCC_Config.eClockName = PCC_CLK_CRC0; + bSP_PCC_Config.bEn = true; + bSP_PCC_Config.eClkSrc = PCC_CLKGATE_SRC_PLL0DIV; + bSP_PCC_Config.eDivider = PCC_CLK_UNINVOLVED; + PCC_SetPcc(&bSP_PCC_Config); + + + // PCC_CLK_WKU0 + bSP_PCC_Config.eClockName = PCC_CLK_WKU0; + bSP_PCC_Config.bEn = true; + bSP_PCC_Config.eClkSrc = PCC_CLKGATE_UNINVOLVED; + bSP_PCC_Config.eDivider = PCC_CLK_UNINVOLVED; + + PCC_SetPcc(&bSP_PCC_Config); + +} + +void Bsp_Systick_Init(void) +{ + uint32_t u32ReloadVal; + uint32_t SystemCoreClock; + + SystemCoreClock = SCG_GetScgClockFreq(SCG_CORE_CLK); + while(SystemCoreClock == 0){}; + u32ReloadVal = SystemCoreClock / 1000; + Core_SysTick_Config(u32ReloadVal); + NVIC_SetPriority(SysTick_IRQn, 0); + Core_SysTick_Enable(); +} + + +/* ################################################################################## */ +/* ################################# Global Functions ############################### */ + + +/** + * @brief General Clock Initial + * + */ +void Bsp_CLOCK_Init(void) { + CSC0_ClkoutType tCSCClkOutCfg = {0}; + + /* Configure CSC(clock out configuration) */ + tCSCClkOutCfg.bEnable = true; + tCSCClkOutCfg.eClkOutSrc = CSC0_CLKOUT_BUS_CLK; + tCSCClkOutCfg.eDivider = CSC0_CLKOUT_DIV_BY4; + + + SCG_Deinit(); + Bsp_SCG_Init(); + Bsp_PCC_Init(); + + /* Set clock out */ + SCG_SetClkOut(SCG_CLOCKOUT_SRC_FOSC); + CSC0_SetClockOut(&tCSCClkOutCfg, false); + + Bsp_Systick_Init(); +} diff --git a/APP/Clock.h b/APP/Clock.h new file mode 100644 index 0000000..fad051f --- /dev/null +++ b/APP/Clock.h @@ -0,0 +1,20 @@ +#ifndef INCLUDE_BSP_CLOCK_H_ +#define INCLUDE_BSP_CLOCK_H_ + +#include "fc7xxx_driver_fcuart.h" +#include "fc7xxx_driver_pcc.h" +#include "fc7xxx_driver_port.h" +#include "fc7xxx_driver_scg.h" +#include "fc7xxx_driver_gpio.h" +#include "fc7xxx_driver_dma.h" +#include "fc7xxx_driver_csc.h" +#include "interrupt_manager.h" +#include "fc7xxx_driver_systick.h" + +/** + * @brief General Clock Initial + * + */ +void Bsp_CLOCK_Init(void); + +#endif /* INCLUDE_BSP_CLOCK_H_ */ diff --git a/APP/FC7240_flash.ld b/APP/FC7240_flash.ld new file mode 100644 index 0000000..3dd9ef8 --- /dev/null +++ b/APP/FC7240_flash.ld @@ -0,0 +1,253 @@ +/* Entry Point */ +ENTRY(Reset_Handler) + + +M_VECTOR_RAM_SIZE = 0x0400; + +_BootloaderSize = 64K; +_BootloaderBegin = 0x01000000; /* BANK1 */ + +_FirmwareSize = 704K; +_MetadataSize = 256; +_FirmwareSize_CALIB = 256K; + +_FirmwareMainBegin = _BootloaderBegin + _BootloaderSize; +_FirmwareMetaBegin = _FirmwareMainBegin + _FirmwareSize - _MetadataSize; +_FirmwareCalibBegin = _FirmwareMainBegin + _FirmwareSize; +_FirmwareMetaCalibBegin = _FirmwareCalibBegin + _FirmwareSize_CALIB - _MetadataSize; + +_FirmwareRecoveryBegin = 0x01100000; /* BANK2 */ +_FirmwareRecoveryMetaBegin = _FirmwareRecoveryBegin + _FirmwareSize - _MetadataSize; +_FirmwareRecoveryCalibBegin = _FirmwareRecoveryBegin + _FirmwareSize; +_FirmwareRecoveryMetaCalibBegin = _FirmwareRecoveryCalibBegin + _FirmwareSize_CALIB - _MetadataSize; + +/* Specify the memory areas */ +MEMORY +{ + + ITCM (RW) : ORIGIN = 0x00000000, LENGTH = 0x00008000 /* 32KB */ + + SRAM0 (RW) : ORIGIN = 0x21000000, LENGTH = 0x00010000 /* 64KB */ + SRAM1 (RW) : ORIGIN = 0x21010000, LENGTH = 0x00008000 /* 32KB */ + + PFLASH_BOOT (RW) : ORIGIN = _BootloaderBegin, LENGTH = _BootloaderSize /* 64K */ + PFLASH_MAIN (RW) : ORIGIN = _FirmwareMainBegin, LENGTH = _FirmwareSize /* 704K */ + PFLASH_MAIN_META (RW) : ORIGIN = _FirmwareMetaBegin, LENGTH = _MetadataSize /* 256 */ + PFLASH_CALIB (RW) : ORIGIN = _FirmwareCalibBegin, LENGTH = _FirmwareSize_CALIB /* 256K */ + PFLASH_CALIB_META (RW) : ORIGIN = _FirmwareMetaCalibBegin, LENGTH = _MetadataSize /* 256 */ + + PFLASH_R_MAIN (RW) : ORIGIN = _FirmwareRecoveryBegin, LENGTH = _FirmwareSize /* 704K */ + PFLASH_R_MAIN_META (RW) : ORIGIN = _FirmwareRecoveryMetaBegin, LENGTH = _MetadataSize /* 256 */ + PFLASH_R_CALIB (RW) : ORIGIN = _FirmwareRecoveryCalibBegin, LENGTH = _FirmwareSize_CALIB /* 192K */ + PFLASH_R_CALIB_META (RW) : ORIGIN = _FirmwareRecoveryMetaCalibBegin, LENGTH = _FirmwareSize_CALIB /* 256 */ + + DFLASH (RW) : ORIGIN = 0x04000000, LENGTH = 0x00020000 /* 128KB */ + + NVR0 (RW) : ORIGIN = 0x04400000, LENGTH = 0x00004000 /* 16KB */ + NVR1 (RW) : ORIGIN = 0x04408000, LENGTH = 0x00004000 /* 16KB */ + NVR2 (RW) : ORIGIN = 0x04410000, LENGTH = 0x00002000 /* 8KB */ + + /* DTCM */ + DTCM (RW) : ORIGIN = 0x20000000, LENGTH = 0x0001FA00 /* 128K - 0x600 */ + DTCM_STACK (RW) : ORIGIN = 0x2001FA00, LENGTH = 0x00000600 /* 0x600 */ + +} + +/* Define output sections */ +SECTIONS +{ + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(1024); /* VTOR must be align to 1K */ + __vector_table = .; + __interrupts_start__ = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) + __interrupts_end__ = .; + . = ALIGN(4); + + KEEP(*(.version_section)) + . = ALIGN(4); + + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.init) /* section used in crti.o files */ + *(.fini) /* section used in crti.o files */ + *(.eh_frame) /* section used in crtbegin.o files */ + . = ALIGN(4); + } > PFLASH_MAIN + + .meta_main : SUBALIGN(1) + { +/* LONG(_FirmwareSize - 4) ;*/ /* word with firmware_size */ + + KEEP(*(.meta_fw_name_size)) + KEEP(*(.meta_fw_name)) + + KEEP(*(.meta_internal_hw_year)) + KEEP(*(.meta_internal_hw_month)) + KEEP(*(.meta_internal_hw_day)) + KEEP(*(.meta_internal_hw_rev)) + + KEEP(*(.meta_internal_sw_year)) + KEEP(*(.meta_internal_sw_month)) + KEEP(*(.meta_internal_sw_day)) + KEEP(*(.meta_internal_sw_rev)) + + KEEP(*(.meta_internal_mdb_year)) + KEEP(*(.meta_internal_mdb_month)) + KEEP(*(.meta_internal_mdb_day)) + KEEP(*(.meta_internal_mdb_rev)) + + KEEP(*(.meta_finger_module)) + KEEP(*(.meta_finger_tester_serial)) + KEEP(*(.meta_finger_year)) + KEEP(*(.meta_finger_month)) + KEEP(*(.meta_finger_day)) + + . = ALIGN(256); + } > PFLASH_MAIN_META + + + .caltext : SUBALIGN(2) + { + __caltext_start = .; + KEEP(*(.caltext)) + __caltext_end = .; + . = ALIGN(4); + } > PFLASH_CALIB + + .meta_main : SUBALIGN(3) + { + LONG(0) ; /* word with firmware_size */ + + . = ALIGN(256); + } > PFLASH_CALIB_META + + + .data : + { + __ram_data_start = .; + . = ALIGN(4); + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + . = ALIGN(4); + /* All data end */ + __ram_data_end = .; + + } > DTCM AT > PFLASH_MAIN + + /* Non-cache RAM section with data initialization */ + .ncache_data : + { + . = ALIGN(4); + __ram_ncache_data_start = .; + *(.nocacheable_data*) + __ram_ncache_data_end = .; + . = ALIGN(4); + } > SRAM1 AT > PFLASH_MAIN + + +.cals_data(NOLOAD) : +{ + __itcm_start = .; + + /* Начало .caldata */ + __caldata_start = .; + KEEP(*(.caldata)) + . = ALIGN(4); + + /* Проверяем и резервируем 20K */ + __caldata_actual_size = . - __caldata_start; + ASSERT(__caldata_actual_size <= 20K, "Ошибка: .caldata превышает 20K!"); + + /* Если данные меньше 20K, резервируем оставшееся пространство */ + . = __caldata_start + 20K; + + KEEP(*(.nvmdata)) + + __itcm_end = .; + . = ALIGN(4); +} > ITCM + + .xcp_data(NOLOAD) : + { + + . = ALIGN(4); + KEEP(*(.save_data)) + . = ALIGN(4); + + __xcp_start = .; + KEEP(*(.xcpdata)) + __xcp_end = .; + . = ALIGN(4); + } > SRAM0 + + + + .bss(NOLOAD) : + { + . = ALIGN(4); + __bss_start = .; + + + *HVAC_model.c.obj(.bss .bss*) + . = ALIGN(4); + + *(.bss*) + *(COMMON) + __bss_end = .; + . = ALIGN(4); + } > DTCM + + /* Non-cache RAM section with no initialization */ + .ncache_bss(NOLOAD) : + { + . = ALIGN(4); + __ncache_bss_start = .; + + . = ALIGN(4); + KEEP(*(.stack_data)) + . = ALIGN(4); + + *(.nocacheable_bss*) + __ncache_bss_end = .; + . = ALIGN(4); + } > SRAM1 + + __HeapBegin = ORIGIN(DTCM_STACK); + __HeapLimit = ORIGIN(DTCM_STACK) + 0x200 - 8; + + __StackLimit = ORIGIN(DTCM_STACK)+0x200; + __StackTop = ORIGIN(DTCM_STACK) + LENGTH(DTCM_STACK) - 8; + + __rom_data_start = LOADADDR(.data); + __rom_ncache_data_start = LOADADDR(.ncache_data); +} + + diff --git a/APP/FreeRTOSConfig.h b/APP/FreeRTOSConfig.h new file mode 100644 index 0000000..d2046c2 --- /dev/null +++ b/APP/FreeRTOSConfig.h @@ -0,0 +1,177 @@ +/* USER CODE BEGIN Header */ +/* + * FreeRTOS Kernel V10.3.1 + * Portion Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * Portion Copyright (C) 2019 StMicroelectronics, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ +/* USER CODE END Header */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * These parameters and more are described within the 'configuration' section of the + * FreeRTOS API documentation available on the FreeRTOS.org web site. + * + * See http://www.freertos.org/a00110.html + *----------------------------------------------------------*/ + +/* USER CODE BEGIN Includes */ +/* Section where include file can be added */ +/* USER CODE END Includes */ + +/* Ensure definitions are only used by the compiler, and not by the assembler. */ +#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__) + +#include + +extern uint32_t SystemCoreClock; +#endif + +//#ifndef CMSIS_device_header +//#define CMSIS_device_header "niietcm4.h" +//#define CMSIS_device_header "at32f435_437.h" +//#endif /* CMSIS_device_header */ +//#include "niietcm4.h" +//#include "at32f435_437.h" + +#define configCHECK_FOR_STACK_OVERFLOW 1 + +#define configENABLE_FPU 1 +#define configENABLE_MPU 0 + +#define configUSE_PREEMPTION 1 +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( 240000000 ) +#define configTICK_RATE_HZ ((TickType_t)1000) +#define configMAX_PRIORITIES ( 56 ) +#define configMINIMAL_STACK_SIZE ((uint16_t)64) +#define configTOTAL_HEAP_SIZE ((size_t)20 * 1024) +#define configMAX_TASK_NAME_LEN ( 16 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configUSE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 8 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +/* USER CODE BEGIN MESSAGE_BUFFER_LENGTH_TYPE */ +/* Defaults to size_t for backward compatibility, but can be changed + if lengths will always be less than the number of bytes in a size_t. */ +#define configMESSAGE_BUFFER_LENGTH_TYPE size_t +/* USER CODE END MESSAGE_BUFFER_LENGTH_TYPE */ + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( 2 ) +#define configTIMER_QUEUE_LENGTH 10 +#define configTIMER_TASK_STACK_DEPTH 128 + +/* CMSIS-RTOS V2 flags */ +#define configUSE_OS2_THREAD_SUSPEND_RESUME 1 +#define configUSE_OS2_THREAD_ENUMERATE 1 +#define configUSE_OS2_EVENTFLAGS_FROM_ISR 1 +#define configUSE_OS2_THREAD_FLAGS 1 +#define configUSE_OS2_TIMER 1 +#define configUSE_OS2_MUTEX 1 + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xQueueGetMutexHolder 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_eTaskGetState 1 + +/* + * The CMSIS-RTOS V2 FreeRTOS wrapper is dependent on the heap implementation used + * by the application thus the correct define need to be enabled below + */ +#define USE_FreeRTOS_HEAP_4 + +/* Cortex-M specific definitions. */ +#ifdef __NVIC_PRIO_BITS +/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ +#define configPRIO_BITS __NVIC_PRIO_BITS +#else +#define configPRIO_BITS 3U +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 7 // 15 + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 1 // 5 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) + +/* Normal assert() semantics without relying on the provision of an assert.h +header file. */ +/* USER CODE BEGIN 1 */ + +//#define configASSERT(x) if ((x) == 0) {nvic_system_reset();} +#define configASSERT(x) if ((x) == 0) {taskDISABLE_INTERRUPTS(); for( ;; );} +/* USER CODE END 1 */ + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler + +/* IMPORTANT: After 10.3.1 update, Systick_Handler comes from NVIC (if SYS timebase = systick), otherwise from cmsis_os2.c */ + +#define USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION 0 + + +#endif /* FREERTOS_CONFIG_H */ diff --git a/APP/main.c b/APP/main.c new file mode 100644 index 0000000..f889caa --- /dev/null +++ b/APP/main.c @@ -0,0 +1,90 @@ +// +// Created by cfif on 22.09.2025. +// +#include "Clock.h" +#include "cmsis_os.h" +#include "MainModesArbiter.h" +#include "LoggerInterface.h" +#include "PeripheralInterfaces.h" + +//#define BOOT_AREA_LENGTH (256 * 1024) +//#define FIRMWARE_MAIN_ADDR (0x01000000 + BOOT_AREA_LENGTH) +//#define FIRMWARE_MAIN_RECOVERY_ADDR (FIRMWARE_MAIN_ADDR + FIRMWARE_MAIN_AREA_LENGTH) + +tMma MAIN_ENV; + +//deep sleep 98 116 197 264 + + +//int _write(int fd, char* ptr, int len) { + +// MAIN_ENV.serialPorts->cliVirtualPortOut_Io.transmit(MAIN_ENV.serialPorts->cliVirtualPortOut_Io.env, (uint8_t *)ptr, len, 0); + +// return len; +//return 0; +//} + +#define LOGGER &MAIN_ENV.slog.logger +#define LOG_SIGN "Model" + +char buffer_printf[1024]; + +int printf(const char *format, ...) { + + return 0; + + va_list args; + va_start(args, format); + int ret = vsnprintf(buffer_printf, sizeof(buffer_printf), format, args); + va_end(args); + + if (ret > 0) { + +// if (buffer_printf[ret - 1] == '\n') { +// buffer_printf[ret - 1] = ' '; +// } + + LoggerCnInfo(LOGGER, LOG_SIGN, buffer_printf, ret) + } + + return ret; +} + +_Noreturn void stop() { + while (1) { + asm("nop"); + } +} + +#define STOP stop(); + +#if (configCHECK_FOR_STACK_OVERFLOW > 0) + +void vApplicationStackOverflowHook(TaskHandle_t xTask, const char *pcTaskName) { + PROCESS_UNUSED_VAR(xTask); + PROCESS_UNUSED_VAR(pcTaskName); + STOP +} + +#endif + +void FirmwareStopThread() { + ModelTask_StopThread(&MAIN_ENV.ModelTask); +} + +int main(void) { + + Bsp_CLOCK_Init(); + + NVIC_SetPriorityGrouping(NVIC_PRIORITY_GROUP_4); + + osKernelInitialize(); + + Mma_Init(&MAIN_ENV, &GPIOS, &ADCS, &SERIAL_PORTS, &LIN_PORTS, &CAN_PORTS, &NVM_STORAGE, &PWMS, &RTCS); + + Mma_StartThread(&MAIN_ENV); + + osKernelStart(); + + STOP +} \ No newline at end of file diff --git a/APP/modular.json b/APP/modular.json new file mode 100644 index 0000000..7eef019 --- /dev/null +++ b/APP/modular.json @@ -0,0 +1,15 @@ +{ + "cmake": { + "inc_dirs": [ + "./", + "./clock", + "./int" + ], + "srcs": [ + "./**.c", + "./clock/**.c", + "./int/**.c", + "./**.s" + ] + } +} \ No newline at end of file diff --git a/APP/startup_FC7240.s b/APP/startup_FC7240.s new file mode 100644 index 0000000..8de644a --- /dev/null +++ b/APP/startup_FC7240.s @@ -0,0 +1,480 @@ +/* ================================================================================================== */ +/* BRIEF : Startup - Startup file for FC7240 */ +/* PERIPHERAL : N/A */ +/* PLATFORM : Flagchip FC7240 */ +/* SOFTWARE VERSION : 0.1.0 */ +/* VENDOR : Flagchip */ +/* Copyright 2024 Flagchip Semiconductors Co., Ltd. */ +/* All Rights Reserved. */ +/* ================================================================================================== */ +/* ================================================================================================== */ +/* Revision History */ +/* Version Date Initials CR# Descriptions */ +/* --------- ---------- ------------- ---------- --------------- */ +/* 0.1.0 2024-01-12 qxw0030 N/A Initial version */ +/* ================================================================================================== */ + + .syntax unified + .arch armv7-m + + .extern __StackTop + .extern __StackLimit + +/* ================================================================================================== */ +/* Set vector table */ +/* ================================================================================================== */ + .section .isr_vector + .align 2 + .globl __isr_vector + + /* vector table */ +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External Interrupts*/ + .long DMA0_IRQHandler /* DMA channel 0 transfer complete */ + .long DMA1_IRQHandler /* DMA channel 1 transfer complete */ + .long DMA2_IRQHandler /* DMA channel 2 transfer complete */ + .long DMA3_IRQHandler /* DMA channel 3 transfer complete */ + .long DMA4_IRQHandler /* DMA channel 4 transfer complete */ + .long DMA5_IRQHandler /* DMA channel 5 transfer complete */ + .long DMA6_IRQHandler /* DMA channel 6 transfer complete */ + .long DMA7_IRQHandler /* DMA channel 7 transfer complete */ + .long DMA8_IRQHandler /* DMA channel 8 transfer complete */ + .long DMA9_IRQHandler /* DMA channel 9 transfer complete */ + .long DMA10_IRQHandler /* DMA channel 10 transfer complete */ + .long DMA11_IRQHandler /* DMA channel 11 transfer complete */ + .long DMA12_IRQHandler /* DMA channel 12 transfer complete */ + .long DMA13_IRQHandler /* DMA channel 13 transfer complete */ + .long DMA14_IRQHandler /* DMA channel 14 transfer complete */ + .long DMA15_IRQHandler /* DMA channel 15 transfer complete */ + .long DMA_Error_IRQHandler /* DMA error interrupt channels 0-31 */ + .long CPM_IRQHandler /* FPU etc. interrupt */ + .long FC_IRQHandler /* FC Command complete */ + .long PMC_IRQHandler /* HVD/LVD etc. interrupt */ + .long TMU_IRQHandler /* Temperature Monitor Unit interrupt */ + .long WDOG0_IRQHandler /* interrupt request out before wdg reset out */ + .long WDOG1_IRQHandler /* interrupt request out before wdg reset out */ + .long FCSMU0_IRQHandler /* Fault Control and Safety Manage Unit */ + .long STCU0_IRQHandler /* Safety Control Unit interrupt */ + .long ERM_fault_IRQHandler /* ERM single/double bit error correction */ + .long MAM0_IRQHandler /* Matrix Access Monitor interrupt */ + .long RGM_Pre_IRQHandler /* RGM pre-reset Interrupt */ + .long INTM0_IRQHandler /* INTM alarm interrupt */ + .long ISM0_IRQHandler /* ISM0 interrupt */ + .long MB_IRQHandler /* Mail Box interrupt */ + .long SCG_IRQHandler /* SCG bus interrupt request */ + .long CMU0_IRQHandler /* CMU0 interrupt */ + .long CMU1_IRQHandler /* CMU1 interrupt */ + .long CMU2_IRQHandler /* CMU2 interrupt */ + .long CMU3_IRQHandler /* CMU3 interrupt */ + .long CMU4_IRQHandler /* CMU4 interrupt */ + .long TSTMP0_IRQHandler /* TimerStamp0 interrupt */ + .long TSTMP1_IRQHandler /* TimerStamp1 interrupt */ + .long CORDIC_IRQHandler /* CORDIC Accelerator interrupt */ + .long HSM0_IRQHandler /* HSM error interrupt */ + .long FCPIT0_IRQHandler /* FCPIT0 interrupt */ + .long RTC_IRQHandler /* RTC alarm or seconds interrupt */ + .long AONTIMER_IRQHandler /* AONTIMER interrupt request */ + .long SWI_IRQHandler /* Software interrupt */ + .long FREQM_IRQHandler /* FREQM interrupt */ + .long ADC0_IRQHandler /* ADC0 interrupt request. */ + .long ADC1_IRQHandler /* ADC1 interrupt request. */ + .long PTIMER0_IRQHandler /* PTIMER0 interrupt */ + .long PTIMER1_IRQHandler /* PTIMER1 interrupt */ + .long CAN0_IRQHandler /* CAN0 Interrupt */ + .long CAN1_IRQHandler /* CAN1 Interrupt */ + .long CAN2_IRQHandler /* CAN2 Interrupt */ + .long CAN3_IRQHandler /* CAN3 Interrupt */ + .long FCIIC0_IRQHandler /* FCIIC0 Interrupt */ + .long FCIIC1_IRQHandler /* FCIIC1 Interrupt */ + .long FCSPI0_IRQHandler /* FCSPI0 Interrupt */ + .long FCSPI1_IRQHandler /* FCSPI1 Interrupt */ + .long FCSPI2_IRQHandler /* FCSPI2 Interrupt */ + .long FCSPI3_IRQHandler /* FCSPI3 Interrupt */ + .long FCSPI4_IRQHandler /* FCSPI4 Interrupt */ + .long FCSPI5_IRQHandler /* FCSPI5 Interrupt */ + .long FCUART0_RxTx_IRQHandler /* FCUART0 Transmit / Receive Interrupt */ + .long FCUART1_RxTx_IRQHandler /* FCUART1 Transmit / Receive Interrupt */ + .long FCUART2_RxTx_IRQHandler /* FCUART2 Transmit / Receive Interrupt */ + .long FCUART3_RxTx_IRQHandler /* FCUART3 Transmit / Receive Interrupt */ + .long FCUART4_RxTx_IRQHandler /* FCUART4 Transmit / Receive Interrupt */ + .long FCUART5_RxTx_IRQHandler /* FCUART5 Transmit / Receive Interrupt */ + .long FCUART6_RxTx_IRQHandler /* FCUART6 Transmit / Receive Interrupt */ + .long FCUART7_RxTx_IRQHandler /* FCUART7 Transmit / Receive Interrupt */ + .long FTU0_IRQHandler /* FTU0 all source interrupt */ + .long FTU1_IRQHandler /* FTU1 all source interrupt */ + .long FTU2_IRQHandler /* FTU2 all source interrupt */ + .long FTU3_IRQHandler /* FTU3 all source interrupt */ + .long FTU4_IRQHandler /* FTU4 all source interrupt */ + .long FTU5_IRQHandler /* FTU5 all source interrupt */ + .long FTU6_IRQHandler /* FTU6 all source interrupt */ + .long FTU7_IRQHandler /* FTU7 all source interrupt */ + .long CMP0_IRQHandler /* CMP0 interrupt request */ + .long CMP1_IRQHandler /* CMP1 interrupt request */ + .long PORTA_IRQHandler /* Port A pin detect interrupt */ + .long PORTB_IRQHandler /* Port B pin detect interrupt */ + .long PORTC_IRQHandler /* Port C pin detect interrupt */ + .long PORTD_IRQHandler /* Port D pin detect interrupt */ + .long PORTE_IRQHandler /* Port E pin detect interrupt */ + .long MSC0_IRQHandler /* MSC interrupt */ + .long SENT0_IRQHandler /* SENT all interrupt (fast or slow) */ + .long TPU0_CH0_7_IRQHandler /* TPU0 CH0-7 interrupt */ + .long TPU0_CH8_15_IRQHandler /* TPU0 CH8-15 interrupt */ + .long TPU0_CH16_23_IRQHandler /* TPU0 CH16-23 interrupt */ + .long TPU0_CH24_31_IRQHandler /* TPU0 CH24-31 interrupt */ + .long HSM0_CRYPTO_IRQHandler /* HSM crypto interrupt */ + .long DefaultISR /* 108 */ + .long DefaultISR /* 109 */ + .long DefaultISR /* 110 */ + .long DefaultISR /* 111 */ + .long DefaultISR /* 112 */ + .long DefaultISR /* 113 */ + .long DefaultISR /* 114 */ + .long DefaultISR /* 115 */ + .long DefaultISR /* 116 */ + .long DefaultISR /* 117 */ + .long DefaultISR /* 118 */ + .long DefaultISR /* 119 */ + .long DefaultISR /* 120 */ + .long DefaultISR /* 121 */ + .long DefaultISR /* 122 */ + .long DefaultISR /* 123 */ + .long DefaultISR /* 124 */ + .long DefaultISR /* 125 */ + .long DefaultISR /* 126 */ + .long DefaultISR /* 127 */ + .long DefaultISR /* 128 */ + .long DefaultISR /* 129 */ + .long DefaultISR /* 130 */ + .long DefaultISR /* 131 */ + .long DefaultISR /* 132 */ + .long DefaultISR /* 133 */ + .long DefaultISR /* 134 */ + .long DefaultISR /* 135 */ + .long DefaultISR /* 136 */ + .long DefaultISR /* 137 */ + .long DefaultISR /* 138 */ + .long DefaultISR /* 139 */ + .long DefaultISR /* 140 */ + .long DefaultISR /* 141 */ + .long DefaultISR /* 142 */ + .long DefaultISR /* 143 */ + .long DefaultISR /* 144 */ + .long DefaultISR /* 145 */ + .long DefaultISR /* 146 */ + .long DefaultISR /* 147 */ + .long DefaultISR /* 148 */ + .long DefaultISR /* 149 */ + .long DefaultISR /* 150 */ + .long DefaultISR /* 151 */ + .long DefaultISR /* 152 */ + .long DefaultISR /* 153 */ + .long DefaultISR /* 154 */ + .long DefaultISR /* 155 */ + .long DefaultISR /* 156 */ + .long DefaultISR /* 157 */ + .long DefaultISR /* 158 */ + .long DefaultISR /* 159 */ + .long DefaultISR /* 160 */ + .long DefaultISR /* 161 */ + .long DefaultISR /* 162 */ + .long DefaultISR /* 163 */ + .long DefaultISR /* 164 */ + .long DefaultISR /* 165 */ + .long DefaultISR /* 166 */ + .long DefaultISR /* 167 */ + .long DefaultISR /* 168 */ + .long DefaultISR /* 169 */ + .long DefaultISR /* 170 */ + .long DefaultISR /* 171 */ + .long DefaultISR /* 172 */ + .long DefaultISR /* 173 */ + .long DefaultISR /* 174 */ + .long DefaultISR /* 175 */ + .long DefaultISR /* 176 */ + .long DefaultISR /* 177 */ + .long DefaultISR /* 178 */ + .long DefaultISR /* 179 */ + .long DefaultISR /* 180 */ + .long DefaultISR /* 181 */ + .long DefaultISR /* 182 */ + .long DefaultISR /* 183 */ + .long DefaultISR /* 184 */ + .long DefaultISR /* 185 */ + .long DefaultISR /* 186 */ + .long DefaultISR /* 187 */ + .long DefaultISR /* 188 */ + .long DefaultISR /* 189 */ + .long DefaultISR /* 190 */ + .long DefaultISR /* 191 */ + .long DefaultISR /* 192 */ + .long DefaultISR /* 193 */ + .long DefaultISR /* 194 */ + .long DefaultISR /* 195 */ + .long DefaultISR /* 196 */ + .long DefaultISR /* 197 */ + .long DefaultISR /* 198 */ + .long DefaultISR /* 199 */ + .long DefaultISR /* 200 */ + .long DefaultISR /* 201 */ + .long DefaultISR /* 202 */ + .long DefaultISR /* 203 */ + .long DefaultISR /* 204 */ + .long DefaultISR /* 205 */ + .long DefaultISR /* 206 */ + .long DefaultISR /* 207 */ + .long DefaultISR /* 208 */ + .long DefaultISR /* 209 */ + .long DefaultISR /* 210 */ + .long DefaultISR /* 211 */ + .long DefaultISR /* 212 */ + .long DefaultISR /* 213 */ + .long DefaultISR /* 214 */ + .long DefaultISR /* 215 */ + .long DefaultISR /* 216 */ + .long DefaultISR /* 217 */ + .long DefaultISR /* 218 */ + .long DefaultISR /* 219 */ + .long DefaultISR /* 220 */ + .long DefaultISR /* 221 */ + .long DefaultISR /* 222 */ + .long DefaultISR /* 223 */ + .long DefaultISR /* 224 */ + .long DefaultISR /* 225 */ + .long DefaultISR /* 226 */ + .long DefaultISR /* 227 */ + .long DefaultISR /* 228 */ + .long DefaultISR /* 229 */ + .long DefaultISR /* 230 */ + .long DefaultISR /* 231 */ + .long DefaultISR /* 232 */ + .long DefaultISR /* 233 */ + .long DefaultISR /* 234 */ + .long DefaultISR /* 235 */ + .long DefaultISR /* 236 */ + .long DefaultISR /* 237 */ + .long DefaultISR /* 238 */ + .long DefaultISR /* 239 */ + .long DefaultISR /* 240 */ + .long DefaultISR /* 241 */ + .long DefaultISR /* 242 */ + .long DefaultISR /* 243 */ + .long DefaultISR /* 244 */ + .long DefaultISR /* 245 */ + .long DefaultISR /* 246 */ + .long DefaultISR /* 247 */ + .long DefaultISR /* 248 */ + .long DefaultISR /* 249 */ + .long DefaultISR /* 250 */ + .long DefaultISR /* 251 */ + .long DefaultISR /* 252 */ + .long DefaultISR /* 253 */ + .long DefaultISR /* 254 */ + .long 0xFFFFFFFF /* Reserved for user TRIM value */ + + .size __isr_vector, . - __isr_vector + + +/**************************************************************/ +/************************ set other ***************************/ + .text + .thumb + +/* Reset Handler */ + + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + cpsid i /* Mask interrupts */ + + /* Init the rest of the registers */ + ldr r1,=0 + ldr r2,=0 + ldr r3,=0 + ldr r4,=0 + ldr r5,=0 + ldr r6,=0 + ldr r7,=0 + mov r8,r7 + mov r9,r7 + mov r10,r7 + mov r11,r7 + mov r12,r7 + + ldr r0, =0xE000ED08 + ldr r1, =__vector_table + str r1, [r0] + + /* Initialize the stack pointer */ + ldr r0,=__StackTop + mov sp,r0 ; sp=r13 + + /* Clear Stack */ + ldr r2, =__StackLimit + ldr r4, =__StackTop + movs r3, #0 + b LoopFillZero_STACK + +FillZero_STACK: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZero_STACK: + cmp r2, r4 + bcc FillZero_STACK + + /* System Initialization */ + ldr r0,=System_Init + blx r0 + + /* Initialize .data and .bss sections */ + ldr r0,=Data_Init + blx r0 + + cpsie i /* Unmask interrupts */ + bl main +JumpToSelf: + b JumpToSelf + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm + +/* Exception Handlers */ + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + def_irq_handler DMA0_IRQHandler + def_irq_handler DMA1_IRQHandler + def_irq_handler DMA2_IRQHandler + def_irq_handler DMA3_IRQHandler + def_irq_handler DMA4_IRQHandler + def_irq_handler DMA5_IRQHandler + def_irq_handler DMA6_IRQHandler + def_irq_handler DMA7_IRQHandler + def_irq_handler DMA8_IRQHandler + def_irq_handler DMA9_IRQHandler + def_irq_handler DMA10_IRQHandler + def_irq_handler DMA11_IRQHandler + def_irq_handler DMA12_IRQHandler + def_irq_handler DMA13_IRQHandler + def_irq_handler DMA14_IRQHandler + def_irq_handler DMA15_IRQHandler + def_irq_handler DMA_Error_IRQHandler + def_irq_handler CPM_IRQHandler + def_irq_handler FC_IRQHandler + def_irq_handler PMC_IRQHandler + def_irq_handler TMU_IRQHandler + def_irq_handler WDOG0_IRQHandler + def_irq_handler WDOG1_IRQHandler + def_irq_handler FCSMU0_IRQHandler + def_irq_handler STCU0_IRQHandler + def_irq_handler ERM_fault_IRQHandler + def_irq_handler MAM0_IRQHandler + def_irq_handler RGM_Pre_IRQHandler + def_irq_handler INTM0_IRQHandler + def_irq_handler ISM0_IRQHandler + def_irq_handler MB_IRQHandler + def_irq_handler SCG_IRQHandler + def_irq_handler CMU0_IRQHandler + def_irq_handler CMU1_IRQHandler + def_irq_handler CMU2_IRQHandler + def_irq_handler CMU3_IRQHandler + def_irq_handler CMU4_IRQHandler + def_irq_handler TSTMP0_IRQHandler + def_irq_handler TSTMP1_IRQHandler + def_irq_handler CORDIC_IRQHandler + def_irq_handler HSM0_IRQHandler + def_irq_handler FCPIT0_IRQHandler + def_irq_handler RTC_IRQHandler + def_irq_handler AONTIMER_IRQHandler + def_irq_handler SWI_IRQHandler + def_irq_handler FREQM_IRQHandler + def_irq_handler ADC0_IRQHandler + def_irq_handler ADC1_IRQHandler + def_irq_handler PTIMER0_IRQHandler + def_irq_handler PTIMER1_IRQHandler + def_irq_handler CAN0_IRQHandler + def_irq_handler CAN1_IRQHandler + def_irq_handler CAN2_IRQHandler + def_irq_handler CAN3_IRQHandler + def_irq_handler FCIIC0_IRQHandler + def_irq_handler FCIIC1_IRQHandler + def_irq_handler FCSPI0_IRQHandler + def_irq_handler FCSPI1_IRQHandler + def_irq_handler FCSPI2_IRQHandler + def_irq_handler FCSPI3_IRQHandler + def_irq_handler FCSPI4_IRQHandler + def_irq_handler FCSPI5_IRQHandler + def_irq_handler FCUART0_RxTx_IRQHandler + def_irq_handler FCUART1_RxTx_IRQHandler + def_irq_handler FCUART2_RxTx_IRQHandler + def_irq_handler FCUART3_RxTx_IRQHandler + def_irq_handler FCUART4_RxTx_IRQHandler + def_irq_handler FCUART5_RxTx_IRQHandler + def_irq_handler FCUART6_RxTx_IRQHandler + def_irq_handler FCUART7_RxTx_IRQHandler + def_irq_handler FTU0_IRQHandler + def_irq_handler FTU1_IRQHandler + def_irq_handler FTU2_IRQHandler + def_irq_handler FTU3_IRQHandler + def_irq_handler FTU4_IRQHandler + def_irq_handler FTU5_IRQHandler + def_irq_handler FTU6_IRQHandler + def_irq_handler FTU7_IRQHandler + def_irq_handler CMP0_IRQHandler + def_irq_handler CMP1_IRQHandler + def_irq_handler PORTA_IRQHandler + def_irq_handler PORTB_IRQHandler + def_irq_handler PORTC_IRQHandler + def_irq_handler PORTD_IRQHandler + def_irq_handler PORTE_IRQHandler + def_irq_handler MSC0_IRQHandler + def_irq_handler SENT0_IRQHandler + def_irq_handler TPU0_CH0_7_IRQHandler + def_irq_handler TPU0_CH8_15_IRQHandler + def_irq_handler TPU0_CH16_23_IRQHandler + def_irq_handler TPU0_CH24_31_IRQHandler + def_irq_handler HSM0_CRYPTO_IRQHandler + .end diff --git a/APP/syscalls.c b/APP/syscalls.c new file mode 100644 index 0000000..931a5b1 --- /dev/null +++ b/APP/syscalls.c @@ -0,0 +1,75 @@ +#if (defined(__ICCARM__)) + +#elif defined(__ARMCC_VERSION) + +#elif defined __GNUC__ + #include "sys/types.h" + #include "sys/stat.h" +#endif + +static uint32_t s_u32Current_heap_end; + +#if (defined(__ICCARM__)) +extern uint32_t __HeapBegin[1]; // Defined by the linker. +extern uint32_t __HeapLimit[1]; // Defined by the linker. +#elif defined __GNUC__ +extern uint32_t __HeapBegin[1]; // Defined by the linker. +extern uint32_t __HeapLimit[1]; // Defined by the linker. +#endif + + +#if (defined(__ICCARM__)) +/** + * TODO: something can be done to make sure the start address used in heap is defined heap start +*/ +#elif defined(__ARMCC_VERSION) + +#elif defined __GNUC__ +extern caddr_t _sbrk(int incr); + +/** + * \brief Replacement of C library of _sbrk + */ +caddr_t _sbrk(int incr) +{ + if (s_u32Current_heap_end == 0U) + { + #if (defined(__ICCARM__)) + s_u32Current_heap_end = (uint32_t)__HeapBegin; + #elif defined __GNUC__ + s_u32Current_heap_end = (uint32_t)__HeapBegin; + #endif + } + + // Need to align heap to word boundary, else will get + // hard faults on Cortex-M0. So we assume that heap starts on + // word boundary, hence make sure we always add a multiple of + // 4 to it. + incr = (incr + 3) & (~3); // align value to 4 + #if (defined(__ICCARM__)) + if ( (s_u32Current_heap_end + incr) > (uint32_t)__HeapLimit ) + #elif defined __GNUC__ + if ( (s_u32Current_heap_end + incr) > (uint32_t)__HeapLimit ) + #endif + { + // Some of the libstdc++-v3 tests rely upon detecting + // out of memory errors, so do not abort here. + #if 0 + extern void abort(void); + + _write(1, "_sbrk: Heap and stack collision\n", 32); + + abort(); + #else + return (caddr_t) - 1; + #endif + } + else + { + s_u32Current_heap_end+= incr; + } + + return (caddr_t) s_u32Current_heap_end; +} + +#endif diff --git a/APP/system_init.c b/APP/system_init.c new file mode 100644 index 0000000..4221dc3 --- /dev/null +++ b/APP/system_init.c @@ -0,0 +1,163 @@ +/** + * @file system_init.c + * @author Flagchip + * @brief interrupt configuration + * @version 0.1.0 + * @date 2024-01-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ + +/* ******************************************************************************** + * Revision History: + * + * Version Date Author Descriptions + * --------- ---------- ------------ --------------- + * 0.1.0 2024-01-12 Flagchip038 First version for gcc, iar, keil, ghs data init + ******************************************************************************** */ + + +#include "system_init.h" +#include "fc7xxx_driver_fpu.h" + +static void data_clear(uint32_t u32StartAddr, uint32_t u32EndAddr); +static void data_copy(uint32_t u32SourceAddr, uint32_t u32DestAddr, uint32_t u32DestEndAddr); + +/** + * \brief System Initialization + * + */ +void System_Init(void) +{ + /* disable wdog 0 */ + *(volatile uint32 *)0x40022004 = 0x08181982; + while (0U == (0x800u & *(volatile uint32 *)0x40022000)); + *(volatile uint32 *)0x40022000 = 0x2920; + *(volatile uint32 *)0x40022008 = 0xF000; + while (0U == (0x400u & *(volatile uint32 *)0x40022000)); + + /* disable wdog 1 */ + *(volatile uint32 *)0x40433004 = 0x08181982; + while (0U == (0x800u & *(volatile uint32 *)0x40433000)); + *(volatile uint32 *)0x40433000 = 0x2920; + *(volatile uint32 *)0x40433008 = 0xF000; + while (0U == (0x400u & *(volatile uint32 *)0x40433000)); + +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + FPU_Enable(); /* Enable FPU */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + +} + +void Data_Init(void) +{ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + extern uint32_t Load$$RW_m_dtcm$$Base; + extern uint32_t Image$$RW_m_dtcm$$Base; + extern uint32_t Image$$RW_m_dtcm$$Limit; + + extern uint32_t Image$$RW_m_dtcm$$ZI$$Limit; + extern uint32_t Image$$RW_m_dtcm$$ZI$$Base; + + extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Base; + extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Limit; + + /* data/bss/heap clear */ + data_clear((uint32_t)&Image$$RW_m_dtcm$$Base, (uint32_t)&Image$$RW_m_dtcm$$Limit); + data_clear((uint32_t)&Image$$RW_m_dtcm$$ZI$$Base, (uint32_t)&Image$$RW_m_dtcm$$ZI$$Limit); + data_clear((uint32_t)&Image$$ARM_LIB_HEAP$$ZI$$Base, (uint32_t)&Image$$ARM_LIB_HEAP$$ZI$$Limit); + + /* data */ + data_copy((uint32_t)&Load$$RW_m_dtcm$$Base, (uint32_t)&Image$$RW_m_dtcm$$Base, (uint32_t)&Image$$RW_m_dtcm$$Limit); + +#elif defined(__GNUC__) || defined(__ghs__) + extern uint32 __rom_data_start[]; + extern uint32 __ram_data_start[]; + extern uint32 __ram_data_end[]; + extern uint32 __bss_start[]; + extern uint32 __bss_end[]; + extern uint32 __rom_ncache_data_start[]; + extern uint32 __ram_ncache_data_start[]; + extern uint32 __ram_ncache_data_end[]; + extern uint32 __ncache_bss_start[]; + extern uint32 __ncache_bss_end[]; + + extern uint32_t __itcm_start[]; + extern uint32_t __itcm_end[]; + + + extern uint32_t __xcp_start[]; + extern uint32_t __xcp_end[]; + + + /* data clear */ + data_clear((uint32_t)__ram_data_start, (uint32_t)__ram_data_end); + data_clear((uint32_t)__bss_start, (uint32_t)__bss_end); + data_clear((uint32_t)__ram_ncache_data_start, (uint32_t)__ram_ncache_data_end); + data_clear((uint32_t)__ncache_bss_start, (uint32_t)__ncache_bss_end); + + data_clear((uint32_t)__itcm_start, (uint32_t)__itcm_end); + data_clear((uint32_t)__xcp_start, (uint32_t)__xcp_end); + + /* data copy */ + data_copy((uint32_t)__rom_data_start, (uint32_t)__ram_data_start, (uint32_t)__ram_data_end); + data_copy((uint32_t)__rom_ncache_data_start, (uint32_t)__ram_ncache_data_start, (uint32_t)__ram_ncache_data_end); + +#elif defined(__ICCARM__) + #pragma section=".data" + #pragma section=".data_init" + #pragma section=".ncsram" + #pragma section=".ncsram_init" + #pragma section=".bss" + #pragma section="RAM_VECTOR" + #pragma section=".intvec" + + data_clear((uint32_t)__section_begin(".bss"), (uint32_t)__section_end(".bss")); + + data_copy((uint32_t)__section_begin(".data_init"), (uint32_t)__section_begin(".data"), (uint32_t)__section_end(".data")); + + data_copy((uint32_t)__section_begin(".ncsram_init"), (uint32_t)__section_begin(".ncsram"), (uint32_t)__section_end(".ncsram")); + +#endif +} + +/* to avoid ecc issue, FC7240 clear ram with 64bits once after power on reset */ +static void data_clear(uint32_t u32StartAddr, uint32_t u32EndAddr) +{ + /* 64 bits align */ + uint32_t u32AlignStart = u32StartAddr & 0xFFFFFFF8; + uint32_t u32AlignEnd = (u32EndAddr - u32AlignStart); + volatile uint64_t *pData = (uint64_t *)u32AlignStart; + + /* 32 word Align */ + uint32_t u32LeftCount = u32AlignEnd & 0x1Fu; + u32AlignEnd = u32EndAddr - u32LeftCount; + + while ((uint32_t)pData < u32AlignEnd) + { + *pData++ = 0u; + *pData++ = 0u; + *pData++ = 0u; + *pData++ = 0u; + } + + while ((uint32_t)pData < u32EndAddr) + { + *pData++ = 0u; + } +} + +static void data_copy(uint32_t u32SourceAddr, uint32_t u32DestAddr, uint32_t u32DestEndAddr) +{ + uint32_t *pSource = (uint32_t *)u32SourceAddr; + uint32_t *pDest = (uint32_t *)u32DestAddr; + + while ((uint32_t)pDest < u32DestEndAddr) + { + *pDest = *pSource; + pDest++; + pSource++; + } +} + diff --git a/APP/system_init.h b/APP/system_init.h new file mode 100644 index 0000000..8057dbe --- /dev/null +++ b/APP/system_init.h @@ -0,0 +1,32 @@ +/** + * @file system_init.h + * @author Flagchip + * @brief interrupt configuration + * @version 0.1.0 + * @date 2024-01-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +#if !defined(SYSTEM_INIT_H) +#define SYSTEM_INIT_H + + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + + +#include "device_header.h" + +void System_Init(void); + +void Data_Init(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + + + +#endif /* SYSTEM_INIT_H */ diff --git a/APP/text b/APP/text new file mode 100644 index 0000000..df5be91 --- /dev/null +++ b/APP/text @@ -0,0 +1,28 @@ +.cals_data(NOLOAD) : +{ + __itcm_start = .; + + /* Резервируем ровно 20K для .caldata */ + .caldata : { + KEEP(*(.caldata)) + . = ALIGN(4); + } > ITCM + + /* Проверяем размер и заполняем до 20K */ + __caldata_end = .; + __caldata_start = ADDR(.caldata); + __caldata_size = SIZEOF(.caldata); + + /* Если .caldata меньше 20K, добавляем пустое пространство */ + . = __caldata_start + 20K; + + /* Проверяем, что не превысили размер */ + ASSERT((. - __caldata_start) >= 20K, "Зарезервировано менее 20K для .caldata"); + ASSERT(__caldata_size <= 20K, "Раздел .caldata превышает 20K!"); + + KEEP(*(.nvmdata)) + . = ALIGN(4); + *Model_actuator.c.obj(.bss .bss*) + __itcm_end = .; + . = ALIGN(4); +} > ITCM \ No newline at end of file diff --git a/CMakeLists.txt b/CMakeLists.txt new file mode 100644 index 0000000..ec84136 --- /dev/null +++ b/CMakeLists.txt @@ -0,0 +1,144 @@ +#-- Service -------------------------------------------------------------------- +SET(CMAKE_TOOLCHAIN_FILE ${CMAKE_SOURCE_DIR}/MODULES/CmakeConfig_GCC_CortexM7/gcc_cm7f.cmake) +ENABLE_LANGUAGE(ASM) +CMAKE_MINIMUM_REQUIRED(VERSION 3.8.0) + +set(CMAKE_CXX_FLAGS_DEBUG "${CMAKE_CXX_FLAGS_DEBUG} -O0") +set(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -O0") + +IF (${CMAKE_SOURCE_DIR} STREQUAL ${CMAKE_BINARY_DIR}) + MESSAGE( + FATAL_ERROR + "In-source builds not allowed. + Please make a new directory (called a build directory) and run CMake from there. + You may need to remove CMakeCache.txt." + ) +ENDIF () + +SET(CMAKE_EXPORT_COMPILE_COMMANDS ON) +#-- Project config ------------------------------------------------------------- +PROJECT(HVAC_M7) # Project name + + +SET(INTERNAL_HW_YEAR 26) +SET(INTERNAL_HW_MONTH 8) +SET(INTERNAL_HW_DAY 19) +SET(INTERNAL_HW_REV 1) + +SET(INTERNAL_SW_YEAR 26) +SET(INTERNAL_SW_MONTH 8) +SET(INTERNAL_SW_DAY 18) +SET(INTERNAL_SW_REV 3) + +SET(INTERNAL_MDB_YEAR 26) +SET(INTERNAL_MDB_MONTH 8) +SET(INTERNAL_MDB_DAY 21) +SET(INTERNAL_MDB_REV 6) + +SET(FINGER_MODULE 0x01) +SET(FINGER_YEAR 0x26) +SET(FINGER_MONTH 0x08) +SET(FINGER_DAY 0x16) +SET(FINGER_TESTER_SERIAL \"M\") + + +SET(VECT_TAB_OFFSET "0x00000") + + + +#-- Defines -------------------------------------------------------------------- + + +ADD_DEFINITIONS(-DINTERNAL_HW_YEAR=${INTERNAL_HW_YEAR}) +ADD_DEFINITIONS(-DINTERNAL_HW_MONTH=${INTERNAL_HW_MONTH}) +ADD_DEFINITIONS(-DINTERNAL_HW_DAY=${INTERNAL_HW_DAY}) +ADD_DEFINITIONS(-DINTERNAL_HW_REV=${INTERNAL_HW_REV}) + +ADD_DEFINITIONS(-DINTERNAL_SW_YEAR=${INTERNAL_SW_YEAR}) +ADD_DEFINITIONS(-DINTERNAL_SW_MONTH=${INTERNAL_SW_MONTH}) +ADD_DEFINITIONS(-DINTERNAL_SW_DAY=${INTERNAL_SW_DAY}) +ADD_DEFINITIONS(-DINTERNAL_SW_REV=${INTERNAL_SW_REV}) + +ADD_DEFINITIONS(-DINTERNAL_MDB_YEAR=${INTERNAL_MDB_YEAR}) +ADD_DEFINITIONS(-DINTERNAL_MDB_MONTH=${INTERNAL_MDB_MONTH}) +ADD_DEFINITIONS(-DINTERNAL_MDB_DAY=${INTERNAL_MDB_DAY}) +ADD_DEFINITIONS(-DINTERNAL_MDB_REV=${INTERNAL_MDB_REV}) + +ADD_DEFINITIONS(-DFINGER_MODULE=${FINGER_MODULE}) +ADD_DEFINITIONS(-DFINGER_YEAR=${FINGER_YEAR}) +ADD_DEFINITIONS(-DFINGER_MONTH=${FINGER_MONTH}) +ADD_DEFINITIONS(-DFINGER_DAY=${FINGER_DAY}) +ADD_DEFINITIONS(-DFINGER_TESTER_SERIAL=${FINGER_TESTER_SERIAL}) + +ADD_DEFINITIONS(-DUSING_OS_FREERTOS) + +ADD_DEFINITIONS(-DVERSION_SEDANL_Y=25) +ADD_DEFINITIONS(-DVERSION_SEDANL_M=10) +ADD_DEFINITIONS(-DVERSION_SEDANL_D=29) + +ADD_DEFINITIONS(-DVERSION_SEDANH_Y=25) +ADD_DEFINITIONS(-DVERSION_SEDANH_M=10) +ADD_DEFINITIONS(-DVERSION_SEDANH_D=29) + +ADD_DEFINITIONS(-DVERSION_LIMO_Y=25) +ADD_DEFINITIONS(-DVERSION_LIMO_M=10) +ADD_DEFINITIONS(-DVERSION_LIMO_D=29) + +ADD_DEFINITIONS(-DVERSION_SUV_Y=25) +ADD_DEFINITIONS(-DVERSION_SUV_M=10) +ADD_DEFINITIONS(-DVERSION_SUV_D=29) + +ADD_DEFINITIONS(-DVERSION_MPV_Y=25) +ADD_DEFINITIONS(-DVERSION_MPV_M=10) +ADD_DEFINITIONS(-DVERSION_MPV_D=29) + +ADD_DEFINITIONS(-DVECT_TAB_OFFSET=${VECT_TAB_OFFSET}) +ADD_DEFINITIONS(-DHEXT_VALUE=${HEXT_VALUE}) +ADD_DEFINITIONS(-DCMSIS_device_header="interrupt_manager.h") + +ADD_DEFINITIONS(-DFLASH_PAGE_D_SIZE=2048) +ADD_DEFINITIONS(-DFLASH_PAGE_P_SIZE=4096) +ADD_DEFINITIONS(-DCOM_INT_BIG_BUFFERS) +ADD_DEFINITIONS(-DVARIABLE_TABLE_WITH_ID) +ADD_DEFINITIONS(-DLFS_THREADSAFE=1) +ADD_DEFINITIONS(-DHALF_DUPLEX_NO_DELAY=1) +ADD_DEFINITIONS(-DACCESS_ADC=1) +ADD_DEFINITIONS(-DACCESS_RTC=1) +ADD_DEFINITIONS(-DSTORAGE_ARTERY_CHECK_CLEAR=1) + +#ADD_DEFINITIONS(-DSTORAGE_ARTERY_CHECK_WRITE_SECTORS=1) # Включение записи по секторам (Тестово, закоментированно) + +#-- Project paths, Include dirs, Sources list --------------------------------- +#ADD_FILES(SOURCES "MODULES/DeviceStartup_ARTERY_AT32F437ZMT7/ld/startup_at32f435_437.s") +include(modular.cmake) + + +#-- Options -------------------------------------------------------------------- +#IF (PRINTF_FLOAT STREQUAL "1") +SET(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -u_printf_float") +#ENDIF () +IF (SCANF_FLOAT STREQUAL "1") + SET(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -u_scanf_float") +ENDIF () + +#-- Linker script -------------------------------------------------------------- +SET(LDSCRIPT ${CMAKE_SOURCE_DIR}/APP/FC7240_flash.ld) +SET(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -T ${LDSCRIPT} -Wl,-Map=${CMAKE_BINARY_DIR}/${PROJECT_NAME}.map -Wl,--print-memory-usage") + +#-- Random BuildId Generation ------------------------------------------------------------ +SET(RANDOM_BUILD_ID_GEN_FILE ${CMAKE_SOURCE_DIR}/MODULES/CmakeConfig_RandomBuildIdGenerator/version.cmake) +add_custom_target(GEN_RANDOM_BUILD_ID) +ADD_CUSTOM_COMMAND(TARGET GEN_RANDOM_BUILD_ID POST_BUILD + COMMAND ${CMAKE_COMMAND} -P ${RANDOM_BUILD_ID_GEN_FILE}) + +#-- Project linking ------------------------------------------------------------ +ADD_EXECUTABLE(${PROJECT_NAME}.elf ${SOURCES}) +TARGET_LINK_LIBRARIES(${PROJECT_NAME}.elf m) +add_dependencies(${PROJECT_NAME}.elf GEN_RANDOM_BUILD_ID) + +#-- Custom commands ------------------------------------------------------------ +ADD_CUSTOM_COMMAND(TARGET ${PROJECT_NAME}.elf POST_BUILD + COMMAND ${CMAKE_OBJCOPY} "-Oihex" ${PROJECT_NAME}.elf ${CMAKE_BINARY_DIR}/${PROJECT_NAME}.hex + COMMAND ${CMAKE_OBJCOPY} "-Obinary" ${PROJECT_NAME}.elf ${CMAKE_BINARY_DIR}/${PROJECT_NAME}.bin + # COMMAND ${CMAKE_OBJDUMP} "-DS" ${PROJECT_NAME}.elf > ${CMAKE_BINARY_DIR}/${PROJECT_NAME}.dasm + COMMAND ${CMAKE_SIZE} ${PROJECT_NAME}.elf) \ No newline at end of file diff --git a/MODULES/Adc/Inc/Adc.h b/MODULES/Adc/Inc/Adc.h new file mode 100644 index 0000000..6d838bb --- /dev/null +++ b/MODULES/Adc/Inc/Adc.h @@ -0,0 +1,12 @@ +// +// Created by cfif on 11.09.22. +// + +#ifndef ADC_H +#define ADC_H + +#include "AdcIO.h" + +uint8_t AdcGet(tAdcIO *io, uint32_t *buf, uint32_t timeout); + +#endif //ADC_H diff --git a/MODULES/Adc/Src/Adc.c b/MODULES/Adc/Src/Adc.c new file mode 100644 index 0000000..34bd83b --- /dev/null +++ b/MODULES/Adc/Src/Adc.c @@ -0,0 +1,10 @@ +// +// Created by cfif on 17.11.22. +// + +#include "Adc.h" +#include "SystemDelayInterface.h" + +uint8_t AdcGet(tAdcIO *io, uint32_t *buf, uint32_t timeout) { + return io->get(io->env, buf, timeout); +} diff --git a/MODULES/Adc/modular.json b/MODULES/Adc/modular.json new file mode 100644 index 0000000..7039047 --- /dev/null +++ b/MODULES/Adc/modular.json @@ -0,0 +1,17 @@ +{ + "dep": [ + { + "type": "local", + + "dir": "./MODULES/AdcInterface" + } + ], + "cmake": { + "inc_dirs": [ + "Inc" + ], + "srcs": [ + "Src/**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/AdcInterface/Inc/AdcIO.h b/MODULES/AdcInterface/Inc/AdcIO.h new file mode 100644 index 0000000..6e39803 --- /dev/null +++ b/MODULES/AdcInterface/Inc/AdcIO.h @@ -0,0 +1,18 @@ +// +// Created by cfif on 17.11.22. +// + +#ifndef MODULE_ADCIO_H +#define MODULE_ADCIO_H + +#include "stdint.h" + +typedef uint32_t (*AdcIOTransaction )(void *env, uint32_t *buf, uint32_t timeout); + +typedef struct { + void *env; + AdcIOTransaction get; +} tAdcIO; + + +#endif //MODULE_ADCIO_H diff --git a/MODULES/AdcInterface/modular.json b/MODULES/AdcInterface/modular.json new file mode 100644 index 0000000..9bdd478 --- /dev/null +++ b/MODULES/AdcInterface/modular.json @@ -0,0 +1,7 @@ +{ + "cmake": { + "inc_dirs": [ + "Inc" + ] + } +} \ No newline at end of file diff --git a/MODULES/Adc_Flagchip_FC7240/Inc/AdcFlagchip.h b/MODULES/Adc_Flagchip_FC7240/Inc/AdcFlagchip.h new file mode 100644 index 0000000..c939743 --- /dev/null +++ b/MODULES/Adc_Flagchip_FC7240/Inc/AdcFlagchip.h @@ -0,0 +1,58 @@ +// +// Created by cfif on 17.11.22. +// + +#ifndef ADC_FLAGCHIP_H +#define ADC_FLAGCHIP_H + +#include "Adc.h" +#include "cmsis_os2.h" +#include "fc7xxx_driver_adc.h" +#include "fc7xxx_driver_pcc.h" +#include "interrupt_manager.h" + +typedef struct { + ADC_InstanceType ADCx; + uint8_t num_aChannels; + uint32_t *DMA_BUF; + + int32_t offset; + double mux; + double div; + + osMessageQueueId_t txAccessQueue; + + ADC_InitType s_tAdcInitCfg; + ADC_DmaType s_tAdcDmaCfg; + + float pVoltageBuffer[32]; + +} tAdcFlagchip; + +void ADC_Initial( + tAdcFlagchip *env, + + ADC_InstanceType ADCx, // ADC_INSTANCE_0, ADC_INSTANCE_1 + + DMA_ChannelType ADC_DMA_CHANNEL, // DMA_CHANNEL_0 .. DMA_CHANNEL_15 + + IRQn_Type IRQ_DMA, + uint8_t IRQ_DMA_PRIORITY, + uint8_t IRQ_DMA_CHANNEL_PRIORITY, + + const uint32_t *DMA_BUF, + + uint8_t num_aChannels, + ADC_ChannelCfgType *s_aChannels, + + int32_t offset, + double mux, + double div, + + ADC_ConvCompleteCallbackType Bsp_ADC_HandleResult +); + +tAdcIO vAdcGetIo(tAdcFlagchip *env); +void Get_ADC_Result(tAdcFlagchip *env); + +#endif //ADC_FLAGCHIP_H diff --git a/MODULES/Adc_Flagchip_FC7240/Src/AdcFlagchip.c b/MODULES/Adc_Flagchip_FC7240/Src/AdcFlagchip.c new file mode 100644 index 0000000..802bcb5 --- /dev/null +++ b/MODULES/Adc_Flagchip_FC7240/Src/AdcFlagchip.c @@ -0,0 +1,131 @@ +// +// Created by cfif on 07.09.22. +// +#include +#include "AdcFlagchip.h" + +#define VREF 5.0F + +static const uint8_t DUMMY_BYTE = 0xFF; + +void Get_ADC_Result(tAdcFlagchip *env) { + osMessageQueuePut(env->txAccessQueue, &DUMMY_BYTE, 0, 0); +} + +void ADC_Initial( + tAdcFlagchip *env, + ADC_InstanceType ADCx, // ADC_INSTANCE_0, ADC_INSTANCE_1 + + DMA_ChannelType ADC_DMA_CHANNEL, // DMA_CHANNEL_0 .. DMA_CHANNEL_15 + + IRQn_Type IRQ_DMA, + uint8_t IRQ_DMA_PRIORITY, + uint8_t IRQ_DMA_CHANNEL_PRIORITY, + + const uint32_t *DMA_BUF, + + uint8_t num_aChannels, + ADC_ChannelCfgType *s_aChannels, + + int32_t offset, + double mux, + double div, + + ADC_ConvCompleteCallbackType Bsp_ADC_HandleResult +) { + + + env->ADCx = ADCx; + env->DMA_BUF = (uint32_t *) DMA_BUF; + env->offset = offset; + env->div = div; + env->mux = mux; + env->num_aChannels = num_aChannels; + env->txAccessQueue = osMessageQueueNew(1, 1, NULL); + + env->s_tAdcInitCfg.eResolution = ADC_RESOLUTION_12_BIT, //!< 12 bit resolution + env->s_tAdcInitCfg.eAlign = ADC_ALIGN_RIGHT, //!< Align right + env->s_tAdcInitCfg.eTriggerMode = ADC_TRIGMODE_SW, //!< Software trigger + env->s_tAdcInitCfg.bWaitEnable = false; //!< Disable wait conversion mode + env->s_tAdcInitCfg.bCalEnable = false; + env->s_tAdcInitCfg.s32CalOffset = 0U; + env->s_tAdcInitCfg.s32CalGain = 0U; + env->s_tAdcInitCfg.bSequenceGroupModeEnable = false; //!< Disable sequence group mode + env->s_tAdcInitCfg.eTrgLatchUnitPri = TRG_LATCH_UNIT_PRI_ROUND_ROBIN; //!< Round robin priority + env->s_tAdcInitCfg.eClockDivider = ADC_CLOCK_DIV_1; //!< Adc clock divided by 1 + env->s_tAdcInitCfg.eSequenceMode = ADC_SEQMODE_SINGLE; //!< Single sequence mode + env->s_tAdcInitCfg.eOverrunMode = ADC_OVERRUN_MODE_PRESERVE; //!< When overrun occurred, the old conversion data are preserved + env->s_tAdcInitCfg.eVoltageRef = ADC_REF_INTERNAL; //!< Use internal reference + env->s_tAdcInitCfg.bHwAvgEnable = true; //!< Disable averaging functionality + env->s_tAdcInitCfg.eHwAverage = ADC_AVERAGE_32; //!< Selection for number of samples used for averaging + env->s_tAdcInitCfg.aSampleTimes[0] = 4U; + env->s_tAdcInitCfg.aSampleTimes[1] = 10U; + env->s_tAdcInitCfg.aSampleTimes[2] = 40U; + env->s_tAdcInitCfg.aSampleTimes[3] = 80U; + + ADC_Init(ADCx, &env->s_tAdcInitCfg); + ADC_InitChannel(ADCx, s_aChannels, num_aChannels); + + //начало-----------------------------------DMA-RX------------------------------------------------------------------- + //начало-----------------------------------DMA-RX------------------------------------------------------------------- + //начало-----------------------------------DMA-RX------------------------------------------------------------------- + + env->s_tAdcDmaCfg.bDmaEnable = true; + env->s_tAdcDmaCfg.eSeqGroupIndex = ADC_SEQUENCE_GROUP_0; + env->s_tAdcDmaCfg.eDmaInstance = DMA_INSTANCE_0; + env->s_tAdcDmaCfg.eDmaChannel = ADC_DMA_CHANNEL; + env->s_tAdcDmaCfg.u8ChannelPriority = IRQ_DMA_CHANNEL_PRIORITY; + env->s_tAdcDmaCfg.pResultBuffer = (void *) ((uint32_t) DMA_BUF); + env->s_tAdcDmaCfg.pConvCompleteNotify = Bsp_ADC_HandleResult; + + ADC_InitDmaChannel(ADCx, &env->s_tAdcDmaCfg); + ADC_Enable(ADCx); + + NVIC_SetPriority(IRQ_DMA, IRQ_DMA_PRIORITY); + NVIC_EnableIRQ(IRQ_DMA); + + DMA_StartChannel(DMA_INSTANCE_0, ADC_DMA_CHANNEL); + + //конец-----------------------------------DMA-RX------------------------------------------------------------------- + //конец-----------------------------------DMA-RX------------------------------------------------------------------- + //конец-----------------------------------DMA-RX------------------------------------------------------------------- + +} + + + +//static void vAdcStart(tAdcFlagchip *env) { +// ADC_Start(env->ADCx); +//} + +static uint32_t vAdcGet(tAdcFlagchip *env, uint32_t *buf, uint32_t timeout) { + + ADC_Start(env->ADCx); + + uint8_t res; + + uint16_t sent = osMessageQueueGet(env->txAccessQueue, &res, 0, timeout); + +// if (sent == osOK) { +// for (uint8_t i = 0; i < env->num_aChannels; ++i) { +// env->pVoltageBuffer[i] = (float) env->DMA_BUF[i] / ((1U << 12U) - 1U) * VREF; +// } +// } + + // return env->pVoltageBuffer; + *buf = (uint32_t) env->DMA_BUF; + + if (sent == osOK) { + return env->num_aChannels; + } + + return 0; +} + +tAdcIO vAdcGetIo(tAdcFlagchip *env) { + tAdcIO io = { + .env = env, + .get = (AdcIOTransaction) vAdcGet, + }; + return io; +} \ No newline at end of file diff --git a/MODULES/Adc_Flagchip_FC7240/modular.json b/MODULES/Adc_Flagchip_FC7240/modular.json new file mode 100644 index 0000000..2123643 --- /dev/null +++ b/MODULES/Adc_Flagchip_FC7240/modular.json @@ -0,0 +1,17 @@ +{ + "dep": [ + { + "type": "local", + + "dir": "./MODULES/Adc" + } + ], + "cmake": { + "inc_dirs": [ + "Inc" + ], + "srcs": [ + "Src/**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/AsciiStringAssemblingUtils/Inc/AsciiStringAssmeblingUtils.h b/MODULES/AsciiStringAssemblingUtils/Inc/AsciiStringAssmeblingUtils.h new file mode 100644 index 0000000..9cf2132 --- /dev/null +++ b/MODULES/AsciiStringAssemblingUtils/Inc/AsciiStringAssmeblingUtils.h @@ -0,0 +1,42 @@ +// +// Created by CFIF on 06.09.22. +// + +#ifndef ASCIISTRINGASSMEBLINGUTILS_ASCIISTRINGASSMEBLINGUTILS_H +#define ASCIISTRINGASSMEBLINGUTILS_ASCIISTRINGASSMEBLINGUTILS_H + +#include "stdint.h" +#include "stddef.h" + +void vAsciiStringAdd(char *string, size_t *stringLen, char *addString, size_t addStringLen); + +uint8_t vAsciiStringDecimalIntToChar(uint8_t number_0_9); + +void vAsciiStringAddChar(char *string, size_t *stringLen, uint8_t singleChar); + +#define vAsciiStringAddStatic(string, stringLen, staticString)\ + vAsciiStringAdd(string, stringLen, staticString, sizeof(staticString)-1) + +void vAsciiStringClean(char *string, size_t *stringLen); + +void vAsciiStringInit(char *string, size_t *stringLen, size_t fullLen); + +void vAsciiStringAddDecimalInt(char *string, size_t *stringLen, uint8_t number, uint8_t digits); + +void vAsciiStringAddDecimalInt64(char *string, size_t *stringLen, uint64_t number, uint8_t digits); + +void vAsciiStringAddDecimalIntWithLimit(char *string, size_t *stringLen, int64_t number, uint8_t digitsLimit); + +void vAsciiStringAddByteAsHex(char *str, size_t *stringLen, uint8_t number); + +void vAsciiStringAddBytesAsHex(char *str, size_t *stringLen, uint8_t *bytesData, size_t bytesCount); + +void vAsciiStringAddDecimalFloatWithLimit( + char *string, + size_t *stringLen, + double number, + uint8_t intDigits, + uint8_t fractionalDigits +); + +#endif //ASCIISTRINGASSMEBLINGUTILS_ASCIISTRINGASSMEBLINGUTILS_H diff --git a/MODULES/AsciiStringAssemblingUtils/Src/AsciiStringAssemblingUtils.c b/MODULES/AsciiStringAssemblingUtils/Src/AsciiStringAssemblingUtils.c new file mode 100644 index 0000000..916123b --- /dev/null +++ b/MODULES/AsciiStringAssemblingUtils/Src/AsciiStringAssemblingUtils.c @@ -0,0 +1,149 @@ +// +// Created by CFIF on 06.09.22. +// + +#include +#include +#include "AsciiStringAssmeblingUtils.h" + +static const char ASCII_STRING_HEX_CHAR[] = "0123456789ABCDEF"; + +static const uint64_t ASCII_STRING_DEC_POW[] = { + 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000, 100000000, 1000000000, 10000000000, 100000000000 +}; +static const uint8_t ASCII_STRING_DEC_POW_LEN = (sizeof(ASCII_STRING_DEC_POW) / sizeof(uint64_t)); + +uint8_t vAsciiStringDecimalIntToChar(uint8_t number_0_9) { + number_0_9 = number_0_9 % 10; //cutoff digits more 1 (numbers between 0 and 9) + return ('0' + number_0_9); //return char of number('0' is base number in ascii) +} + +void vAsciiStringAdd(char *string, size_t *stringLen, char *addString, size_t addStringLen) { + memcpy(string + (*stringLen), addString, addStringLen); + *stringLen += addStringLen; +} + +void vAsciiStringAddChar(char *string, size_t *stringLen, uint8_t singleChar) { + string[*stringLen] = singleChar; + ++(*stringLen); +} + +void vAsciiStringInit(char *string, size_t *stringLen, size_t fullLen) { + memset(string, 0, fullLen); + *stringLen = 0; +} + +void vAsciiStringClean(char *string, size_t *stringLen) { + if (*stringLen == 0)return; + memset(string, 0, *stringLen); + *stringLen = 0; +} + +void vAsciiStringAddDecimalInt(char *string, size_t *stringLen, uint8_t number, uint8_t digits) { + for (uint8_t reverse_digit = 1; reverse_digit <= digits; ++reverse_digit) { + string[*stringLen + digits - reverse_digit] = vAsciiStringDecimalIntToChar(number); + number /= 10; + } + *stringLen += digits; +} + +void vAsciiStringAddDecimalInt64(char *string, size_t *stringLen, uint64_t number, uint8_t digits) { + for (uint8_t reverse_digit = 1; reverse_digit <= digits; ++reverse_digit) { + string[*stringLen + digits - reverse_digit] = vAsciiStringDecimalIntToChar(number % 10); + number /= 10; + } + *stringLen += digits; +} + +void vAsciiStringSpitChars(char *one, char *two) { + char tmp; + tmp = *one; + *one = *two; + *two = tmp; +} + +void vAsciiStringAddDecimalIntWithLimit(char *string, size_t *stringLen, int64_t number, uint8_t digitsLimit) { + + if (number < 0) { + *(string + (*stringLen)) = '-'; + ++(*stringLen); + number = -number; + } + + uint32_t cutoffNumber = 1; + + for (uint8_t scale = 0; scale < digitsLimit; ++scale) { + cutoffNumber *= 10; + } + number = number % cutoffNumber; + + if (number == 0) { + string[*stringLen] = '0'; + (*stringLen) += 1; + } + + uint8_t digits = 0; + + for (; (digits < digitsLimit) && (number != 0); ++digits) { + string[(*stringLen) + digits] = vAsciiStringDecimalIntToChar(number % 10); + number /= 10; + } + + uint8_t reverses = digits / 2; + + for (uint8_t reverse_digit = 0; reverse_digit < reverses; ++reverse_digit) { + vAsciiStringSpitChars(string + *stringLen + reverse_digit, string + *stringLen + digits - 1 - reverse_digit); + } + + *stringLen += digits; +} + +void vAsciiStringAddByteAsHex(char *str, size_t *stringLen, uint8_t number) { + str[*stringLen + 0] = ASCII_STRING_HEX_CHAR[(number >> 4) & 0xF]; + str[*stringLen + 1] = ASCII_STRING_HEX_CHAR[(number & 0xF)]; + *stringLen += 2; +} + +void vAsciiStringAddBytesAsHex(char *str, size_t *stringLen, uint8_t *bytesData, size_t bytesCount) { + uint8_t *end = bytesData + bytesCount; + while (end > bytesData) { + vAsciiStringAddByteAsHex(str, stringLen, *bytesData); + ++bytesData; + } +} + +static inline uint64_t get_dec_pow(uint8_t value) { + if (value < ASCII_STRING_DEC_POW_LEN) { + return ASCII_STRING_DEC_POW[value]; + } + + uint64_t mux = ASCII_STRING_DEC_POW[ASCII_STRING_DEC_POW_LEN - 1]; + + for (uint8_t scale = ASCII_STRING_DEC_POW_LEN; scale < value; ++scale) { + mux *= 10; + } + + return mux; +} + + +void vAsciiStringAddDecimalFloatWithLimit( + char *string, + size_t *stringLen, + double number, + uint8_t intDigits, + uint8_t fractionalDigits +) { + uint64_t dec_mux = get_dec_pow(fractionalDigits); + + uint64_t intPart = (uint64_t) number; + double fractional = round(number * dec_mux) / dec_mux - intPart; + uint64_t fractionalPartInInteger = (uint64_t) (fractional * dec_mux); + + + vAsciiStringAddDecimalIntWithLimit(string, stringLen, intPart, intDigits); + vAsciiStringAddChar(string, stringLen, '.'); + vAsciiStringAddDecimalInt64(string, stringLen, fractionalPartInInteger, fractionalDigits); + + +} \ No newline at end of file diff --git a/MODULES/AsciiStringAssemblingUtils/modular.json b/MODULES/AsciiStringAssemblingUtils/modular.json new file mode 100644 index 0000000..d4d574e --- /dev/null +++ b/MODULES/AsciiStringAssemblingUtils/modular.json @@ -0,0 +1,12 @@ +{ + "dep": [ + ], + "cmake": { + "inc_dirs": [ + "Inc" + ], + "srcs": [ + "Src/**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/AsciiStringParsingUtils/Inc/AsciiStringParsingUtils.h b/MODULES/AsciiStringParsingUtils/Inc/AsciiStringParsingUtils.h new file mode 100644 index 0000000..db64603 --- /dev/null +++ b/MODULES/AsciiStringParsingUtils/Inc/AsciiStringParsingUtils.h @@ -0,0 +1,33 @@ +// +// Created by CFIF on 10.09.22. +// + +#ifndef ASCIISTRINGPARSINGUTILS_ASCIISTRINGPARSINGUTILS_H +#define ASCIISTRINGPARSINGUTILS_ASCIISTRINGPARSINGUTILS_H + +#include +#include "stdint.h" + +int64_t iAsciiStringParseSignedLongDecimalNumber(char *str, const char *strEnd); + +uint64_t iAsciiStringParseUnsignedLongDecimalNumber(char *str, const char *strEnd); + +double dAsciiStringParseDouble(char *str, const char *strEnd); + +char *xAsciiStringSkipChar(char *str, char const *strEnd, char symbol); + +#define xAsciiStringSkipSpace(STR, STR_END) xAsciiStringSkipChar(STR,STR_END,' ') + +char *xAsciiStringSeekChar(char *str, char const *strEnd, char symbol); + +uint8_t iAsciiStringMoveToNextParsingBlock(char **blockBeginPos, char **blockDividerPos, char *strEnd, char divider); + +uint8_t iAsciiStringParseHexByte(const char *str); + +size_t iAsciiStringParseHexBytes(uint8_t *bytesData, char *str, size_t stringLen); + +#define BIN_FROM_HEX(DATA,LEN,HEX_STRING) \ +uint8_t DATA[(sizeof(HEX_STRING)-1)/2]; \ +size_t LEN = iAsciiStringParseHexBytes(DATA, HEX_STRING, sizeof(HEX_STRING) - 1); + +#endif //ASCIISTRINGPARSINGUTILS_ASCIISTRINGPARSINGUTILS_H diff --git a/MODULES/AsciiStringParsingUtils/Src/AsciiStringParsingUtils.c b/MODULES/AsciiStringParsingUtils/Src/AsciiStringParsingUtils.c new file mode 100644 index 0000000..dbf51b6 --- /dev/null +++ b/MODULES/AsciiStringParsingUtils/Src/AsciiStringParsingUtils.c @@ -0,0 +1,123 @@ +// +// Created by CFIF on 10.09.22. +// + +#include "AsciiStringParsingUtils.h" +#include +#include + +uint8_t iAsciiStringParseCharToDecimalInt(char symbol) { + return (symbol - '0'); // return overvalue if not a decimal number +} + +uint8_t iAsciiStringParseHexCharToInt(char symbol) { + if (symbol >= '0' && symbol <= '9') { + return iAsciiStringParseCharToDecimalInt(symbol); + } else if (symbol >= 'a' && symbol <= 'f') { + return 0xA + symbol - 'a'; + } else if (symbol >= 'A' && symbol <= 'F') { + return 0xA + (symbol - 'A'); + } else { + return 0x10; //not a hex number, return overvalue + } +} + + +uint8_t iAsciiStringParseHexByte(const char *str) { + return iAsciiStringParseHexCharToInt(*str) * 0x10 + iAsciiStringParseHexCharToInt(*(str + 1)); +} + +size_t iAsciiStringParseHexBytes(uint8_t *bytesData, char *str, size_t stringLen) { + char *end = str + stringLen; + + size_t dataLen = stringLen / 2; + + while (end > str) { + + *bytesData = iAsciiStringParseHexByte(str); + + str += 2; + ++bytesData; + } + + return dataLen; +} + +uint64_t iAsciiStringParseUIntDecimalNumberWhitEnd(char **str, const char *strEnd) { + + + uint32_t value = 0; + uint8_t digit; + + while ((*str) < strEnd) { + digit = iAsciiStringParseCharToDecimalInt(**str); + if (digit > 9) { + return value; + } else { + value = (value * 10) + digit; + } + ++(*str); + } + + return value; +} + +int64_t iAsciiStringParseSignedLongDecimalNumber(char *str, const char *strEnd) { + int8_t sign = 1; + if (*str == '-') { + sign = -1; + ++str; + } + + return iAsciiStringParseUIntDecimalNumberWhitEnd(&str, strEnd) * sign; +} + +uint64_t iAsciiStringParseUnsignedLongDecimalNumber(char *str, const char *strEnd) { + return iAsciiStringParseUIntDecimalNumberWhitEnd(&str, strEnd); +} + + +char *xAsciiStringSkipChar(char *utcString, char const *utcStringEnd, char symbol) { + while ((utcString < utcStringEnd) && (*utcString == symbol)) { + ++utcString; + } + return utcString; +} + +char *xAsciiStringSeekChar(char *utcString, char const *utcStringEnd, char symbol) { + while ((utcString < utcStringEnd) && (*utcString != symbol)) { + ++utcString; + } + return utcString; +} + +double dAsciiStringParseDouble(char *str, const char *strEnd) { + double sign = 1; + if (str[0] == '-') { + sign = -1; + ++str; + } + char *dividerSymbol = xAsciiStringSeekChar(str, strEnd, '.'); + + double result = iAsciiStringParseUnsignedLongDecimalNumber(str, dividerSymbol); + + if (dividerSymbol < (strEnd - 1)) { + ++dividerSymbol; + char *fractionalStr = dividerSymbol; + double fractional = iAsciiStringParseUIntDecimalNumberWhitEnd(&fractionalStr, strEnd); + + for (; dividerSymbol < fractionalStr; ++dividerSymbol) { + fractional /= 10; + } + result += fractional; + } + + + return result * sign; +} + +uint8_t iAsciiStringMoveToNextParsingBlock(char **blockBeginPos, char **blockDividerPos, char *strEnd, char divider) { + *blockBeginPos = xAsciiStringSkipSpace((*blockDividerPos + 1), strEnd); + *blockDividerPos = xAsciiStringSeekChar(*blockBeginPos, strEnd, divider); + return *blockDividerPos - *blockBeginPos; //return block length +} \ No newline at end of file diff --git a/MODULES/AsciiStringParsingUtils/Tst/CMakeLists.txt b/MODULES/AsciiStringParsingUtils/Tst/CMakeLists.txt new file mode 100644 index 0000000..72c5078 --- /dev/null +++ b/MODULES/AsciiStringParsingUtils/Tst/CMakeLists.txt @@ -0,0 +1,8 @@ +cmake_minimum_required(VERSION 3.17) +PROJECT(test) + +set(CMAKE_CXX_STANDARD 17) + +include(modular.cmake) + +add_executable(test ${SOURCES}) \ No newline at end of file diff --git a/MODULES/AsciiStringParsingUtils/Tst/Src/test.c b/MODULES/AsciiStringParsingUtils/Tst/Src/test.c new file mode 100644 index 0000000..23d9e47 --- /dev/null +++ b/MODULES/AsciiStringParsingUtils/Tst/Src/test.c @@ -0,0 +1,17 @@ +// +// Created by CFIF on 10.09.22. +// +#include "AsciiStringParsingUtils.h" +#include "printf.h" + +int main() { + char srt[] = "22341.233adfa"; + + + int32_t si = iAsciiStringParseSignedLongDecimalNumber(srt, srt + 10); + double dbl = dAsciiStringParseDouble(srt, srt + 10); + + printf("short unsigned %i %f\n", si, dbl); + + return 0; +} \ No newline at end of file diff --git a/MODULES/AsciiStringParsingUtils/Tst/modular.json b/MODULES/AsciiStringParsingUtils/Tst/modular.json new file mode 100644 index 0000000..236f353 --- /dev/null +++ b/MODULES/AsciiStringParsingUtils/Tst/modular.json @@ -0,0 +1,16 @@ +{ + "dep": [ + { + "type": "local", + "dir": "../" + } + ], + "cmake": { + "inc_dirs": [ + "Inc" + ], + "srcs": [ + "Src/**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/AsciiStringParsingUtils/modular.json b/MODULES/AsciiStringParsingUtils/modular.json new file mode 100644 index 0000000..d4d574e --- /dev/null +++ b/MODULES/AsciiStringParsingUtils/modular.json @@ -0,0 +1,12 @@ +{ + "dep": [ + ], + "cmake": { + "inc_dirs": [ + "Inc" + ], + "srcs": [ + "Src/**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/BaseTypes/Inc/BaseTypes.h b/MODULES/BaseTypes/Inc/BaseTypes.h new file mode 100644 index 0000000..5522bb5 --- /dev/null +++ b/MODULES/BaseTypes/Inc/BaseTypes.h @@ -0,0 +1,11 @@ +// +// Created by cfif on 13.10.22. +// + +#ifndef BASETYPES_H +#define BASETYPES_H + +#include "BaseTypes/String.h" +#include "BaseTypes/Strings.h" + +#endif //BASETYPES_H diff --git a/MODULES/BaseTypes/Inc/BaseTypes/String.h b/MODULES/BaseTypes/Inc/BaseTypes/String.h new file mode 100644 index 0000000..734b195 --- /dev/null +++ b/MODULES/BaseTypes/Inc/BaseTypes/String.h @@ -0,0 +1,24 @@ +// +// Created by CFIF on 10.11.22. +// + +#ifndef UVEOS_ON_NATION_STRING_H +#define UVEOS_ON_NATION_STRING_H + +#include "stdint.h" + +typedef struct { + uint8_t length; + uint8_t max_length; + uint8_t readonly; + char str[32]; +} tString; + + +uint8_t getStrLen(char *str); + +void vInitStringOnlyLength(tString *tstr, uint8_t length); + +void vInitString(tString *tstr, void *str, uint8_t length, uint8_t max_length, uint8_t readonly); + +#endif //UVEOS_ON_NATION_STRING_H diff --git a/MODULES/BaseTypes/Inc/BaseTypes/Strings.h b/MODULES/BaseTypes/Inc/BaseTypes/Strings.h new file mode 100644 index 0000000..557f895 --- /dev/null +++ b/MODULES/BaseTypes/Inc/BaseTypes/Strings.h @@ -0,0 +1,81 @@ +// +// Created by CFIF on 10.11.22. +// + +#ifndef UVEOS_ON_NATION_STRINGS_H +#define UVEOS_ON_NATION_STRINGS_H + +#include "stdint.h" + +#define tString(T) \ +typedef struct { \ + uint8_t length; \ + char data[T]; \ +} tString##T; + +tString(8) +tString(16) +tString(32) +tString(64) +tString(128) +tString(255) + +typedef struct { + uint8_t length; + char *data; +} tStringStatic; + +typedef struct { + uint8_t *length; + char *data; +} tStringLink; + + +#define StringGetLinkTemplateD(T) \ +tStringLink String##T##GetLink(tString##T *string); + +StringGetLinkTemplateD(8) + +StringGetLinkTemplateD(16) + +StringGetLinkTemplateD(32) + +StringGetLinkTemplateD(64) + +StringGetLinkTemplateD(128) + +StringGetLinkTemplateD(255) + +StringGetLinkTemplateD(Static) + + +#define StringStaticInit(STR) (tStringStatic){.data = (char*)(STR), .length = sizeof(STR)-1} +#define StringArrInit(STR) (tStringStatic){.data = (char*)(STR), .length = sizeof(STR)} + + +#define StringCopyTD(T) \ +void String##T##Copy(tString##T *dest, char *source, uint8_t sourceLen); + +StringCopyTD(8) + +StringCopyTD(16) + +StringCopyTD(32) + +StringCopyTD(64) + +StringCopyTD(128) + +StringCopyTD(255) + +#define StringCopyStaticTemplate(T) \ + String##T##Copy(DEST,STR,sizeof(STR)-1) + +#define String8CopyStatic(DEST, STR) String8Copy(DEST,STR,sizeof(STR)-1) +#define String16CopyStatic(DEST, STR) String16Copy(DEST,STR,sizeof(STR)-1) +#define String32CopyStatic(DEST, STR) String32Copy(DEST,STR,sizeof(STR)-1) +#define String64CopyStatic(DEST, STR) String64Copy(DEST,STR,sizeof(STR)-1) +#define String128CopyStatic(DEST, STR) String128Copy(DEST,STR,sizeof(STR)-1) +#define String255CopyStatic(DEST, STR) String128Copy(DEST,STR,sizeof(STR)-1) + +#endif //UVEOS_ON_NATION_STRINGS_H diff --git a/MODULES/BaseTypes/Src/BaseTypes.c b/MODULES/BaseTypes/Src/BaseTypes.c new file mode 100644 index 0000000..edb4717 --- /dev/null +++ b/MODULES/BaseTypes/Src/BaseTypes.c @@ -0,0 +1,27 @@ +// +// Created by cfif on 13.10.22. +// + +#include +#include "BaseTypes.h" + +uint8_t getStrLen(char *str) { + uint8_t len = 0; + while (str[len]) { + ++len; + } + return len; +} + +void vInitString(tString *tstr, void *str, uint8_t length, uint8_t max_length, uint8_t readonly) { + + tstr->length = length; + tstr->max_length = max_length; + tstr->readonly = readonly; + memcpy(tstr->str, str, length); + +} + +void vInitStringOnlyLength(tString *tstr, uint8_t length) { + tstr->length = length; +} \ No newline at end of file diff --git a/MODULES/BaseTypes/Src/Strings.c b/MODULES/BaseTypes/Src/Strings.c new file mode 100644 index 0000000..5f155c3 --- /dev/null +++ b/MODULES/BaseTypes/Src/Strings.c @@ -0,0 +1,43 @@ +// +// Created by CFIF on 11.11.22. +// + +#include "BaseTypes/Strings.h" +#include "memory.h" + +#define StringGetLinkTemplate(T) \ +tStringLink String##T##GetLink(tString##T *string) { \ + return (tStringLink) {.length = &string->length, .data = string->data}; \ +} + +StringGetLinkTemplate(8) + +StringGetLinkTemplate(16) + +StringGetLinkTemplate(32) + +StringGetLinkTemplate(64) + +StringGetLinkTemplate(128) + +StringGetLinkTemplate(Static) + + +//#define StringStaticInit(STR) (tStringStatic){.data = STR, .length = sizeof(STR)-1} + + +#define StringCopyT(T) \ +void String##T##Copy(tString##T *dest, char *source, uint8_t sourceLen) { \ + dest->length = sourceLen > T ? T : sourceLen; \ + memcpy(dest->data, source, dest->length); \ +} + +StringCopyT(8) + +StringCopyT(16) + +StringCopyT(32) + +StringCopyT(64) + +StringCopyT(128) diff --git a/MODULES/BaseTypes/modular.json b/MODULES/BaseTypes/modular.json new file mode 100644 index 0000000..71971cd --- /dev/null +++ b/MODULES/BaseTypes/modular.json @@ -0,0 +1,10 @@ +{ + "cmake": { + "inc_dirs": [ + "Inc" + ], + "srcs": [ + "Src/**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/BootJump_Flagchip_FC7240/Inc/BootJump.h b/MODULES/BootJump_Flagchip_FC7240/Inc/BootJump.h new file mode 100644 index 0000000..059a109 --- /dev/null +++ b/MODULES/BootJump_Flagchip_FC7240/Inc/BootJump.h @@ -0,0 +1,14 @@ +// +// Created by cfif on 02.11.22. +// + +#ifndef HVAC_ON_CHIP_BOOTLOADER_JUMP_H +#define HVAC_ON_CHIP_BOOTLOADER_JUMP_H + +#include "stdint.h" + +void BootFastJumpToAddress(const uint32_t address); +void BootJumpToAddress(const uint32_t address); +void Reset(); + +#endif //HVAC_ON_CHIP_BOOTLOADER_JUMP_H diff --git a/MODULES/BootJump_Flagchip_FC7240/Src/BootJump.c b/MODULES/BootJump_Flagchip_FC7240/Src/BootJump.c new file mode 100644 index 0000000..9a301a0 --- /dev/null +++ b/MODULES/BootJump_Flagchip_FC7240/Src/BootJump.c @@ -0,0 +1,193 @@ +// +// Created by cfif on 02.11.22. +// +#include CMSIS_device_header +#include "fc7xxx_driver_dma.h" +#include "fc7xxx_driver_fcuart.h" +#include "fc7240_fcuart_regs.h" +#include "fc7xxx_driver_pcc.h" +#include "fc7xxx_driver_adc.h" +#include "fc7xxx_driver_flexcan.h" +#include "fc7xxx_driver_tpu.h" + + + +typedef void (*pFunction)(void); + +#define EnablePrivilegedMode() __asm("SVC #0") + + +void DeInitAll() { + // 1. ГЛОБАЛЬНО отключаем прерывания (первое, что делаем) + __disable_irq(); + + // 2. Отключаем ВСЕ прерывания в NVIC + for (int i = 0; i < 8; i++) { // Обычно достаточно 8 банков для всех прерываний + NVIC->ICER[i] = 0xFFFFFFFF; + NVIC->ICPR[i] = 0xFFFFFFFF; + } + + // 3. Останавливаем SysTick и сбрасываем + SysTick->CTRL = 0; + SysTick->LOAD = 0; + SysTick->VAL = 0; + + // 4. Сбрасываем все pending-флаги + SCB->ICSR |= SCB_ICSR_PENDSVCLR_Msk | SCB_ICSR_PENDSTCLR_Msk; + + // 5. Отключаем периферию, которая может генерировать прерывания + + // 5.1. DMA + DMA_DeInit(DMA_INSTANCE_0); + + // 5.2. UART + for (uint8_t i = 0; i < FCUART_INSTANCE_COUNT; ++i) { + FCUART_DeInit(i); + } + + // 5.3. CAN + for (uint8_t i = 0; i < FLEXCAN_INSTANCE_COUNT; ++i) { + FLEXCAN_DeInit(i); + } + + // 5.4. ADC + for (uint8_t i = 0; i < ADC_INSTANCE_COUNT; ++i) { + ADC_DeInit(i); + } + + // 5.5. TPU + TPU_DeInit(); + + + // 5.6 RESET CLK + PCC_GenPeripheralReset(PCC_CLK_DMA0); + PCC_GenPeripheralReset(PCC_CLK_DMAMUX0); + PCC_GenPeripheralReset(PCC_CLK_FLEXCAN0); + PCC_GenPeripheralReset(PCC_CLK_FLEXCAN1); + PCC_GenPeripheralReset(PCC_CLK_FLEXCAN2); + PCC_GenPeripheralReset(PCC_CLK_FLEXCAN3); + PCC_GenPeripheralReset(PCC_CLK_ADC0); + PCC_GenPeripheralReset(PCC_CLK_ADC1); + PCC_GenPeripheralReset(PCC_CLK_FCUART0); + PCC_GenPeripheralReset(PCC_CLK_FCUART1); + PCC_GenPeripheralReset(PCC_CLK_FCUART2); + PCC_GenPeripheralReset(PCC_CLK_FCUART3); + PCC_GenPeripheralReset(PCC_CLK_FCUART4); + PCC_GenPeripheralReset(PCC_CLK_FCUART5); + PCC_GenPeripheralReset(PCC_CLK_FCUART6); + PCC_GenPeripheralReset(PCC_CLK_FCUART7); + +} + +void BootJumpToAddress(const uint32_t address) { + + // 1. ГЛОБАЛЬНО отключаем прерывания (первое, что делаем) + __disable_irq(); + + // 2. Отключаем ВСЕ прерывания в NVIC + for (int i = 0; i < 8; i++) { // Обычно достаточно 8 банков для всех прерываний + NVIC->ICER[i] = 0xFFFFFFFF; + NVIC->ICPR[i] = 0xFFFFFFFF; + } + + // 3. Останавливаем SysTick и сбрасываем + SysTick->CTRL = 0; + SysTick->LOAD = 0; + SysTick->VAL = 0; + + // 4. Сбрасываем все pending-флаги + SCB->ICSR |= SCB_ICSR_PENDSVCLR_Msk | SCB_ICSR_PENDSTCLR_Msk; + + // 5. Отключаем периферию, которая может генерировать прерывания + + // 5.1. DMA + DMA_DeInit(DMA_INSTANCE_0); + + // 5.2. UART + for (uint8_t i = 0; i < FCUART_INSTANCE_COUNT; ++i) { + FCUART_DeInit(i); + } + + // 5.3 RESET CLK + PCC_GenPeripheralReset(PCC_CLK_DMA0); + PCC_GenPeripheralReset(PCC_CLK_DMAMUX0); + PCC_GenPeripheralReset(PCC_CLK_FCUART0); + PCC_GenPeripheralReset(PCC_CLK_FCUART1); + PCC_GenPeripheralReset(PCC_CLK_FCUART2); + PCC_GenPeripheralReset(PCC_CLK_FCUART3); + PCC_GenPeripheralReset(PCC_CLK_FCUART4); + PCC_GenPeripheralReset(PCC_CLK_FCUART5); + PCC_GenPeripheralReset(PCC_CLK_FCUART6); + PCC_GenPeripheralReset(PCC_CLK_FCUART7); + + + // 6. Подготовка процессора + if (CONTROL_nPRIV_Msk & __get_CONTROL()) { + EnablePrivilegedMode(); + } + + if (CONTROL_SPSEL_Msk & __get_CONTROL()) { + __set_MSP(__get_PSP()); + __set_CONTROL(__get_CONTROL() & ~CONTROL_SPSEL_Msk); + } + + // 7. Получаем стек и точку входа приложения + uint32_t appStack = *((__IO uint32_t *) address); + pFunction appEntry = (pFunction) *((__IO uint32_t *) (address + 4)); + + // 8. Устанавливаем VTOR и стек + SCB->VTOR = address; + __set_MSP(appStack); + + // 9. Очищаем регистры, которые могут содержать данные загрузчика + __ISB(); // Instruction Synchronization Barrier + __DSB(); // Data Synchronization Barrier + + // 10. Переход БЕЗ включения прерываний! + // Приложение само должно включить прерывания после инициализации + appEntry(); + + while (1); +} + + +void BootFastJumpToAddress(const uint32_t address) { + + + // 1. Подготовка процессора + if (CONTROL_nPRIV_Msk & __get_CONTROL()) { + EnablePrivilegedMode(); + } + + if (CONTROL_SPSEL_Msk & __get_CONTROL()) { + __set_MSP(__get_PSP()); + __set_CONTROL(__get_CONTROL() & ~CONTROL_SPSEL_Msk); + } + + // 2. Получаем стек и точку входа приложения + uint32_t appStack = *((__IO uint32_t *) address); + pFunction appEntry = (pFunction) *((__IO uint32_t *) (address + 4)); + + // 3. Устанавливаем VTOR и стек + SCB->VTOR = address; + __set_MSP(appStack); + + // 4. Очищаем регистры, которые могут содержать данные загрузчика + __ISB(); // Instruction Synchronization Barrier + __DSB(); // Data Synchronization Barrier + + // 5. Переход БЕЗ включения прерываний! + // Приложение само должно включить прерывания после инициализации + appEntry(); + + while (1); +} + + +void Reset() { + +// DeInitAll(); + + NVIC_SystemReset(); + +} \ No newline at end of file diff --git a/MODULES/BootJump_Flagchip_FC7240/modular.json b/MODULES/BootJump_Flagchip_FC7240/modular.json new file mode 100644 index 0000000..71971cd --- /dev/null +++ b/MODULES/BootJump_Flagchip_FC7240/modular.json @@ -0,0 +1,10 @@ +{ + "cmake": { + "inc_dirs": [ + "Inc" + ], + "srcs": [ + "Src/**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/CanSerialPortFrame_Flagchip_FC7240/Inc/CanSerialPortFrame.h b/MODULES/CanSerialPortFrame_Flagchip_FC7240/Inc/CanSerialPortFrame.h new file mode 100644 index 0000000..f22974c --- /dev/null +++ b/MODULES/CanSerialPortFrame_Flagchip_FC7240/Inc/CanSerialPortFrame.h @@ -0,0 +1,177 @@ +// +// Created by cfif on 16.03.2024. +// + +#ifndef FLAGCHIP_CAN_MODULE_CAN_FRAME_H +#define FLAGCHIP_CAN_MODULE_CAN_FRAME_H + +#include "SerialPortFrameIO.h" +#include "cmsis_os2.h" +#include "stdbool.h" + + +#include "device_header.h" +#include "interrupt_manager.h" + +#include "fc7xxx_driver_flexcan.h" +#include "fc7xxx_driver_pcc.h" +#include "fc7xxx_driver_dma.h" + + +typedef struct { + uint32_t standard_id; /*!< specifies the 11 bits standard identifier + this parameter can be a value between 0 to 0x7FF. */ + + uint32_t extended_id; /*!< specifies the 29 bits extended identifier. + this parameter can be a value between 0 to 0x1FFFFFFF. */ + + FLEXCAN_IdType id_type; /*!< specifies identifier type for the receive message.*/ + + FLEXCAN_DataType frame_type; /*!< specifies frame type for the receive message.*/ + + uint8_t dlc; /*!< specifies the frame data length that will be received. + this parameter can be a value between 0 to 8 */ + + uint8_t data[8]; /*!< contains the receive data. it ranges from 0 to 0xFF.*/ + + uint8_t filter_index; /*!< specifies the message stored in which filter + this parameter can be a value between 0 to 0xFF */ +} can_rx_message_type; + +#define COUNT_TX_CAN0_HANDLER 8 +#define COUNT_TX_CAN1_HANDLER 16 + +#define COUNT_QUEUE 4 + +typedef struct { + FLEXCAN_IdType eRxFrameType; /**< FLEXCAN ID type, 0 STD, 1 EXT */ + uint32_t u32RxCanId; /**< FLEXCAN received ID */ + uint32_t u32RxCanIdMask; + uint8_t filter; +} FilterTo_FLEXCAN_RxMbFilterType; + +typedef struct { + + FLEXCAN_Type *can; + + uint8_t CAN_INDEX; + + uint32_t id; + uint32_t id1; + FLEXCAN_IdType canTypeFrame; + bool canFilterEnable; + + bool reInitOne; + + uint8_t CountHardSoftFilter_RX; + + FLEXCAN_BaudType canBaudRate; + + uint32_t g_u32RxDataIndex; + + FLEXCAN_RxMbFilterType pRxMbFilterList[32]; + FLEXCAN_RxMbFilterType pRxFilterFifoList[32]; + + osMessageQueueId_t rxDataQueue[COUNT_QUEUE]; + osMessageQueueId_t rxDataSnifferQueue[COUNT_QUEUE]; + + osMutexId_t access; + + DMA_InitType dmaInitCfg_RX; + DMA_ChannelCfgType chnCfg_RX; + DMA_InterruptCfgType interruptCfg_RX; + + FLEXCAN_InitType tInitCfg; + FLEXCAN_MBConfigType tMbCfg; + FLEXCAN_InterruptType tIntCfg; + + uint8_t DMA_BUF_LEN_RX; + uint8_t pBufCounter; + + FilterTo_FLEXCAN_RxMbFilterType *IdHardSoftFilter_RX; + + can_rx_message_type rx_message_struct; + + IRQn_Type IRQ_CAN; + + FLEXCAN_ErrorInterruptCallBackType CAN_ErrorInterrupt_CallBack; + FLEXCAN_RxInterruptCallBackType CAN_RxInterrupt_CallBack; + FLEXCAN_RxInterruptCallBackType CAN_RxFifoInterrupt_CallBack; + FLEXCAN_TxInterruptCallBackType CAN_TxInterrupt_CallBack; + DMA_TransferCompleteCallbackType DMA_TransferCompleteCallback; + DMA_TransferErrorCallbackType DMA_ErrorCallback; + +} tCanSerialPortFrameFlagchip; + +bool vCanSerialPortFrameDMAInit( + tCanSerialPortFrameFlagchip *env, + FLEXCAN_Type *CANx, // FLEXCAN0 + uint8 CAN_INDEX, // CAN0 = 0 ... CAN3 = 3 + IRQn_Type IRQ_CAN, // FlexCAN0_IRQn ... FlexCAN3_IRQn + uint8 CAN_PRIORITY, + + DMA_ChannelType DMA_CHANNEL_RX, + DMA_RequestSourceType DMA_CHANNEL_REQ_RX, // DMA_REQ_FLEXCAN0 + const uint8_t *DMA_BUF_RX, + uint8_t DMA_BUF_LEN_RX, + + const FilterTo_FLEXCAN_RxMbFilterType *IdHardSoftFilter_RX, + uint8_t CountHardSoftFilter_RX, + + const FLEXCAN_RxMbFilterType *IdFilterFifo_RX, + uint8_t CountFilterFifo_RX, + + IRQn_Type IRQ_DMA_RX, + uint8_t IRQ_DMA_PRIORITY_RX, + uint8_t IRQ_DMA_CHANNEL_PRIORITY_RX, + + FLEXCAN_BaudType canBaudRate, + FLEXCAN_IdType canTypeFrame, + uint32_t canId, + FLEXCAN_ErrorInterruptCallBackType CAN_ErrorInterrupt_CallBack, + FLEXCAN_RxInterruptCallBackType CAN_RxInterrupt_CallBack, + FLEXCAN_RxInterruptCallBackType CAN_RxFifoInterrupt_CallBack, + FLEXCAN_TxInterruptCallBackType CAN_TxInterrupt_CallBack, + + DMA_TransferCompleteCallbackType DMA_TransferCompleteCallback, + DMA_TransferErrorCallbackType DMA_ErrorCallback +); + +bool vCanSerialPortFrameMbInit( + tCanSerialPortFrameFlagchip *env, + FLEXCAN_Type *CANx, // FLEXCAN0 + uint8 CAN_INDEX, // CAN0 = 0 ... CAN3 = 3 + IRQn_Type IRQ_CAN, // FlexCAN0_IRQn ... FlexCAN3_IRQn + uint8 CAN_PRIORITY, + + const FilterTo_FLEXCAN_RxMbFilterType *IdHardSoftFilter_RX, + uint8_t CountHardSoftFilter_RX, + + FLEXCAN_BaudType canBaudRate, + FLEXCAN_IdType canTypeFrame, + uint32_t canId, + FLEXCAN_ErrorInterruptCallBackType CAN_ErrorInterrupt_CallBack, + FLEXCAN_RxInterruptCallBackType CAN_RxInterrupt_CallBack, + FLEXCAN_RxInterruptCallBackType CAN_RxFifoInterrupt_CallBack, + FLEXCAN_TxInterruptCallBackType CAN_TxInterrupt_CallBack + +); + + + void CAN_RxInterrupt_CallBack_Handler(tCanSerialPortFrameFlagchip *env, uint8_t u8CanIndex, FLEXCAN_RxMsgType *pRxCfg); + +void CanSerialPortFrameIrqRxProcessing(tCanSerialPortFrameFlagchip *env, uint32_t *pBuf); + +void CanSerialPortFrameIrqRxProcessingNO_DMA(tCanSerialPortFrameFlagchip *env, FLEXCAN_RxMsgType *pRxCfg); + +void CanSerialPortFrameSetId(tCanSerialPortFrameFlagchip *env, uint32_t id); + +void CanSerialPortFrameSetType(tCanSerialPortFrameFlagchip *env, FLEXCAN_IdType canTypeFrame); + +tSerialPortFrameIO CanPortFrame_GetIo(tCanSerialPortFrameFlagchip *env); + +tSerialPortFrameIO CanPortFrame_GetSnifferIo(tCanSerialPortFrameFlagchip *env); + +bool vCanSerialPortSetMaskCount(tCanSerialPortFrameFlagchip *env, uint8_t maskCount); + +#endif //FLAGCHIP_CAN_MODULE_CAN_FRAME_H diff --git a/MODULES/CanSerialPortFrame_Flagchip_FC7240/Src/CanSerialPortFrame.c b/MODULES/CanSerialPortFrame_Flagchip_FC7240/Src/CanSerialPortFrame.c new file mode 100644 index 0000000..d7195cc --- /dev/null +++ b/MODULES/CanSerialPortFrame_Flagchip_FC7240/Src/CanSerialPortFrame.c @@ -0,0 +1,920 @@ +// +// Created by cfif on 16.03.2024. +// +#include +#include "CanSerialPortFrame.h" +#include "memory.h" +#include "candb.h" +#include "CanPorts.h" + +#define CAN_USED_NUM 2U // Количество CAN +#define CAN_RECEIVE_MB_NUM 128 // Количество mailbox на один CAN + +static FLEXCAN_RxMsgType s_aaRxDataBuf[CAN_USED_NUM][CAN_RECEIVE_MB_NUM]; + +#define CAN_GET_BUFFER(index) (FLEXCAN_RxMsgType*)s_aaRxDataBuf[index] + +static const PCC_ClkSrcType s_ePccCanTable[] = + { + PCC_CLK_FLEXCAN0, + PCC_CLK_FLEXCAN1, + PCC_CLK_FLEXCAN2, + PCC_CLK_FLEXCAN3 + }; + +static void BSP_CAN_INIT_CFG(FLEXCAN_InitType *pCfg) { + pCfg->bListenOnly = 0U; + pCfg->bEnBrs = 0; + pCfg->bEnDma = 0; + pCfg->bEnFd = 0; + pCfg->bEnRxFifo = 0; + pCfg->eBaudrate = FLEXCAN_BAUD_100K; + pCfg->eClkSrcHz = FLEXCAN_BAUDCLK_HZ_8M; + pCfg->eClkSrcSel = FLEXCAN_CLOCK_FUNCTION; + pCfg->eDataBaud = FLEXCAN_BAUD_100K; + pCfg->eMbDataWidth = FLEXCAN_DATAWIDTH_8; + pCfg->u8EnhancedFifoDmaWM = 0; + pCfg->eDirect = FLEXCAN_DIR_DISABLE; +} + +static void BSP_CAN_INIT_MBConfig(FLEXCAN_MBConfigType *pMbCfg) { + pMbCfg->pRxFilterFifoList = NULL; + pMbCfg->u8RxFilterFifoCnt = 0; + pMbCfg->pRxFilterMBList = NULL; + pMbCfg->u8RxFilterMBCnt = 0; + pMbCfg->u8TxMsgCnt = 0; + pMbCfg->pRxBuf = NULL; +} + +void CanSerialPortFrameSetId(tCanSerialPortFrameFlagchip *env, uint32_t id) { + env->id = id; +} + +void CanSerialPortFrameSetType(tCanSerialPortFrameFlagchip *env, FLEXCAN_IdType canTypeFrame) { + env->canTypeFrame = canTypeFrame; +} + +static void +vCanSerialPortFrameInitStructure(tCanSerialPortFrameFlagchip *env, uint16_t rxDataLength, uint16_t rxSnifferLength) { + + for (uint8_t i = 0; i < COUNT_QUEUE; ++i) { + env->rxDataQueue[i] = osMessageQueueNew(rxDataLength, sizeof(can_rx_message_type), NULL); + if (rxSnifferLength) { + env->rxDataSnifferQueue[i] = osMessageQueueNew(rxSnifferLength, sizeof(can_rx_message_type), NULL); + } else { + env->rxDataSnifferQueue[i] = NULL; + } + } + +} + +bool vCanSerialPortFrameDMAInit( + tCanSerialPortFrameFlagchip *env, + FLEXCAN_Type *CANx, // FLEXCAN0 + uint8 CAN_INDEX, // CAN0 = 0 ... CAN3 = 3 + IRQn_Type IRQ_CAN, // FlexCAN0_IRQn ... FlexCAN3_IRQn + uint8 CAN_PRIORITY, + + DMA_ChannelType DMA_CHANNEL_RX, + DMA_RequestSourceType DMA_CHANNEL_REQ_RX, // DMA_REQ_FLEXCAN0 + const uint8_t *DMA_BUF_RX, + uint8_t DMA_BUF_LEN_RX, + + const FilterTo_FLEXCAN_RxMbFilterType *IdHardSoftFilter_RX, + uint8_t CountHardSoftFilter_RX, + + const FLEXCAN_RxMbFilterType *IdFilterFifo_RX, + uint8_t CountFilterFifo_RX, + + IRQn_Type IRQ_DMA_RX, + uint8_t IRQ_DMA_PRIORITY_RX, + uint8_t IRQ_DMA_CHANNEL_PRIORITY_RX, + + FLEXCAN_BaudType canBaudRate, + FLEXCAN_IdType canTypeFrame, + uint32_t canId, + FLEXCAN_ErrorInterruptCallBackType CAN_ErrorInterrupt_CallBack, + FLEXCAN_RxInterruptCallBackType CAN_RxInterrupt_CallBack, + FLEXCAN_RxInterruptCallBackType CAN_RxFifoInterrupt_CallBack, + FLEXCAN_TxInterruptCallBackType CAN_TxInterrupt_CallBack, + + DMA_TransferCompleteCallbackType DMA_TransferCompleteCallback, + DMA_TransferErrorCallbackType DMA_ErrorCallback +) { + env->g_u32RxDataIndex = 0; + env->can = CANx; + env->CAN_INDEX = CAN_INDEX; + env->DMA_BUF_LEN_RX = DMA_BUF_LEN_RX; + env->IdHardSoftFilter_RX = (FilterTo_FLEXCAN_RxMbFilterType *) IdHardSoftFilter_RX; + env->CountHardSoftFilter_RX = CountHardSoftFilter_RX; + env->canBaudRate = canBaudRate; + env->IRQ_CAN = IRQ_CAN; + + env->CAN_ErrorInterrupt_CallBack = CAN_ErrorInterrupt_CallBack; + env->CAN_RxInterrupt_CallBack = CAN_RxInterrupt_CallBack; + env->CAN_RxFifoInterrupt_CallBack = CAN_RxFifoInterrupt_CallBack; + env->CAN_TxInterrupt_CallBack = CAN_TxInterrupt_CallBack; + env->DMA_TransferCompleteCallback = DMA_TransferCompleteCallback; + env->DMA_ErrorCallback = DMA_ErrorCallback; + + //начало-----------------------------------DMA-RX------------------------------------------------------------------- + //начало-----------------------------------DMA-RX------------------------------------------------------------------- + //начало-----------------------------------DMA-RX------------------------------------------------------------------- + + uint32_t u32TargetAddr = (uint32_t)(DMA_BUF_RX); + + env->chnCfg_RX.pSrcBuffer = &(CANx->RAM[0]); + env->chnCfg_RX.pDestBuffer = (void *) (u32TargetAddr); + env->chnCfg_RX.u32BlockSize = DMA_BUF_LEN_RX; + env->chnCfg_RX.u16BlockCount = 1U; + env->chnCfg_RX.u8ChannelPriority = IRQ_DMA_CHANNEL_PRIORITY_RX; + env->chnCfg_RX.eSrcDataSize = DMA_TRANSFER_SIZE_4B; + env->chnCfg_RX.eDestDataSize = DMA_TRANSFER_SIZE_4B; + env->chnCfg_RX.eSrcIncMode = DMA_INCREMENT_DATA_SIZE; + env->chnCfg_RX.eDestIncMode = DMA_INCREMENT_DATA_SIZE; + env->chnCfg_RX.bSrcBlockOffsetEn = 0U; + env->chnCfg_RX.bDestBlockOffsetEn = 0U; + env->chnCfg_RX.s32BlockOffset = 0; + env->chnCfg_RX.bSrcAddrLoopbackEn = 1U; + env->chnCfg_RX.bDestAddrLoopbackEn = false; + env->chnCfg_RX.bAutoStop = 0U; + env->chnCfg_RX.bSrcCircularBufferEn = false; + env->chnCfg_RX.u32SrcCircBufferSize = DMA_CIRCULAR_BUFFER_SIZE_1B; + env->chnCfg_RX.bDestCircularBufferEn = true; + env->chnCfg_RX.u32DestCircBufferSize = 256U; + env->chnCfg_RX.eTriggerSrc = DMA_CHANNEL_REQ_RX; + DMA_InitChannel(DMA_INSTANCE_0, (DMA_ChannelType) DMA_CHANNEL_RX, &env->chnCfg_RX); + + env->interruptCfg_RX.bTransferCompleteIntEn = 1; + env->interruptCfg_RX.pTransferCompleteNotify = DMA_TransferCompleteCallback; + env->interruptCfg_RX.bTransferErrorIntEn = 1; + env->interruptCfg_RX.pTransferErrorNotify = DMA_ErrorCallback; + + DMA_InitChannelInterrupt(DMA_INSTANCE_0, (DMA_ChannelType) DMA_CHANNEL_RX, &env->interruptCfg_RX); + + NVIC_SetPriority(IRQ_DMA_RX, IRQ_DMA_PRIORITY_RX); + NVIC_EnableIRQ(IRQ_DMA_RX); + + DMA_StartChannel(DMA_INSTANCE_0, (DMA_ChannelType) DMA_CHANNEL_RX); + + + //конец-----------------------------------DMA-RX-------------------------------------------------------------------- + //конец-----------------------------------DMA-RX-------------------------------------------------------------------- + //конец-----------------------------------DMA-RX-------------------------------------------------------------------- + + + //начало------------------------------------CAN--------------------------------------------------------------------- + //начало------------------------------------CAN--------------------------------------------------------------------- + //начало------------------------------------CAN--------------------------------------------------------------------- + + FLEXCAN_ErrorType tRetVal; + uint32_t u32FuncClk; + + tRetVal = FLEXCAN_DeInit(CAN_INDEX); + + BSP_CAN_INIT_CFG(&env->tInitCfg); + BSP_CAN_INIT_MBConfig(&env->tMbCfg); + + env->tInitCfg.eBaudrate = canBaudRate; + env->tInitCfg.eDataBaud = canBaudRate; + env->tInitCfg.bEnRxFifo = TRUE; +// env->tInitCfg.bEnRxFifo = FALSE; + + env->tInitCfg.bEnDma = TRUE; +// env->tInitCfg.bEnDma = FALSE; + + env->tInitCfg.bEnFd = FALSE; + env->tInitCfg.bEnBrs = FALSE; + env->tInitCfg.eMbDataWidth = FLEXCAN_DATAWIDTH_8; + + u32FuncClk = PCC_GetPccFunctionClock(s_ePccCanTable[CAN_INDEX]); + + env->tInitCfg.eClkSrcSel = FLEXCAN_CLOCK_FUNCTION; // functional clock + env->tInitCfg.eClkSrcHz = (FLEXCAN_BaudClkType) u32FuncClk; // function clock frequency + + env->tInitCfg.eDirect = FLEXCAN_DIR_ENABLE_WITHOUT_TRIG; + + tRetVal = FLEXCAN_Init(CAN_INDEX, &env->tInitCfg); + + if (tRetVal == FLEXCAN_ERROR_OK) { + + + env->tMbCfg.pRxFilterMBList = NULL; + env->tMbCfg.u8RxFilterMBCnt = 0; + + for (uint8_t i = 0; i < CountFilterFifo_RX; ++i) { + env->pRxFilterFifoList[i].eRxFrameType = IdFilterFifo_RX[i].eRxFrameType; + env->pRxFilterFifoList[i].u32RxCanId = IdFilterFifo_RX[i].u32RxCanId; + env->pRxFilterFifoList[i].u32RxCanIdMask = IdFilterFifo_RX[i].u32RxCanIdMask; + } + + env->tMbCfg.pRxFilterFifoList = env->pRxFilterFifoList; + env->tMbCfg.u8RxFilterFifoCnt = CountFilterFifo_RX; + + env->tMbCfg.pRxBuf = CAN_GET_BUFFER(CAN_INDEX); + + // tx config + if (CAN_INDEX == 0) { + env->tMbCfg.u8TxMsgCnt = COUNT_TX_CAN0_HANDLER; // tx occupy 3 mb + } + + if (CAN_INDEX == 1) { + env->tMbCfg.u8TxMsgCnt = COUNT_TX_CAN1_HANDLER; // tx occupy 3 mb + } + + tRetVal = FLEXCAN_RxFilterConfig(CAN_INDEX, &env->tMbCfg); + + if (CAN_ErrorInterrupt_CallBack == NULL) { + env->tIntCfg.bEnErrorInterrupt = 0U; + env->tIntCfg.pErrorNotify = NULL; + } else { + env->tIntCfg.bEnErrorInterrupt = 1U; + env->tIntCfg.pErrorNotify = CAN_ErrorInterrupt_CallBack; + } + + if (CAN_TxInterrupt_CallBack == NULL) { + env->tIntCfg.bEnTxMBInterrupt = 0U; + env->tIntCfg.pTxMBNotify = NULL; + } else { + env->tIntCfg.bEnTxMBInterrupt = 1U; + env->tIntCfg.pTxMBNotify = CAN_TxInterrupt_CallBack; + } + + if (CAN_RxInterrupt_CallBack == NULL) { + env->tIntCfg.bEnRxMBInterrupt = 0U; + env->tIntCfg.pRxMBNotify = NULL; + } else { + env->tIntCfg.bEnRxMBInterrupt = 1U; + env->tIntCfg.pRxMBNotify = CAN_RxInterrupt_CallBack; + } + + if (CAN_RxFifoInterrupt_CallBack == NULL) { + env->tIntCfg.bEnRxFifoInterrupt = 0U; + env->tIntCfg.pRxFifoNotify = NULL; + } else { + env->tIntCfg.bEnRxFifoInterrupt = 1U; + env->tIntCfg.pRxFifoNotify = CAN_RxFifoInterrupt_CallBack; + } + + if ((env->tIntCfg.bEnErrorInterrupt) || + (env->tIntCfg.bEnTxMBInterrupt) || + (env->tIntCfg.bEnRxMBInterrupt) || + (env->tIntCfg.bEnRxFifoInterrupt)) { + + NVIC_SetPriority(IRQ_CAN, CAN_PRIORITY); + NVIC_EnableIRQ(IRQ_CAN); + + FLEXCAN_SetInterrupt(CAN_INDEX, &env->tIntCfg); + + } + + if (!env->reInitOne) { + + env->reInitOne = true; + +// for (uint8_t i = 0; i < COUNT_TX_HANDLER; ++i) { +// env->access[i] = osMutexNew(NULL); +// env->txDataQueueCan[i] = osMessageQueueNew(1, 1, NULL); +// } + env->access = osMutexNew(NULL); + vCanSerialPortFrameInitStructure(env, 10, 0); + + CanSerialPortFrameSetType(env, canTypeFrame); + CanSerialPortFrameSetId(env, canId); + + env->canBaudRate = canBaudRate; + } + + FLEXCAN_Start(CAN_INDEX); // Start CAN + + } else { + return false; + } + + + return true; + //конец------------------------------------CAN---------------------------------------------------------------------- + //конец------------------------------------CAN---------------------------------------------------------------------- + //конец------------------------------------CAN---------------------------------------------------------------------- +} + + +bool vCanSerialPortFrameMbInit( + tCanSerialPortFrameFlagchip *env, + FLEXCAN_Type *CANx, // FLEXCAN0 + uint8 CAN_INDEX, // CAN0 = 0 ... CAN3 = 3 + IRQn_Type IRQ_CAN, // FlexCAN0_IRQn ... FlexCAN3_IRQn + uint8 CAN_PRIORITY, + + const FilterTo_FLEXCAN_RxMbFilterType *IdHardSoftFilter_RX, + uint8_t CountHardSoftFilter_RX, + + FLEXCAN_BaudType canBaudRate, + FLEXCAN_IdType canTypeFrame, + uint32_t canId, + FLEXCAN_ErrorInterruptCallBackType CAN_ErrorInterrupt_CallBack, + FLEXCAN_RxInterruptCallBackType CAN_RxInterrupt_CallBack, + FLEXCAN_RxInterruptCallBackType CAN_RxFifoInterrupt_CallBack, + FLEXCAN_TxInterruptCallBackType CAN_TxInterrupt_CallBack + +) { + + env->g_u32RxDataIndex = 0; + env->can = CANx; + env->CAN_INDEX = CAN_INDEX; +// env->DMA_BUF_LEN_RX = DMA_BUF_LEN_RX; + env->IdHardSoftFilter_RX = (FilterTo_FLEXCAN_RxMbFilterType *) IdHardSoftFilter_RX; + env->CountHardSoftFilter_RX = CountHardSoftFilter_RX; + env->canBaudRate = canBaudRate; + env->IRQ_CAN = IRQ_CAN; + + env->CAN_ErrorInterrupt_CallBack = CAN_ErrorInterrupt_CallBack; + env->CAN_RxInterrupt_CallBack = CAN_RxInterrupt_CallBack; + env->CAN_RxFifoInterrupt_CallBack = CAN_RxFifoInterrupt_CallBack; + env->CAN_TxInterrupt_CallBack = CAN_TxInterrupt_CallBack; +// env->DMA_TransferCompleteCallback = DMA_TransferCompleteCallback; +// env->DMA_ErrorCallback = DMA_ErrorCallback; + + + //начало------------------------------------CAN--------------------------------------------------------------------- + //начало------------------------------------CAN--------------------------------------------------------------------- + //начало------------------------------------CAN--------------------------------------------------------------------- + + FLEXCAN_ErrorType tRetVal; + uint32_t u32FuncClk; + + tRetVal = FLEXCAN_DeInit(CAN_INDEX); + + BSP_CAN_INIT_CFG(&env->tInitCfg); + BSP_CAN_INIT_MBConfig(&env->tMbCfg); + + env->tInitCfg.eBaudrate = canBaudRate; + env->tInitCfg.eDataBaud = canBaudRate; +// env->tInitCfg.bEnRxFifo = TRUE; + env->tInitCfg.bEnRxFifo = FALSE; + +// env->tInitCfg.bEnDma = TRUE; + env->tInitCfg.bEnDma = FALSE; + + env->tInitCfg.bEnFd = FALSE; + env->tInitCfg.bEnBrs = FALSE; + env->tInitCfg.eMbDataWidth = FLEXCAN_DATAWIDTH_8; + + u32FuncClk = PCC_GetPccFunctionClock(s_ePccCanTable[CAN_INDEX]); + + env->tInitCfg.eClkSrcSel = FLEXCAN_CLOCK_FUNCTION; // functional clock + env->tInitCfg.eClkSrcHz = (FLEXCAN_BaudClkType) u32FuncClk; // function clock frequency + + tRetVal = FLEXCAN_Init(CAN_INDEX, &env->tInitCfg); + + if (tRetVal == FLEXCAN_ERROR_OK) { + + for (uint8_t i = 0; i < CountHardSoftFilter_RX; ++i) { + env->pRxMbFilterList[i].eRxFrameType = IdHardSoftFilter_RX[i].eRxFrameType; + env->pRxMbFilterList[i].u32RxCanId = IdHardSoftFilter_RX[i].u32RxCanId; + env->pRxMbFilterList[i].u32RxCanIdMask = IdHardSoftFilter_RX[i].u32RxCanIdMask; + } + + env->tMbCfg.pRxFilterMBList = env->pRxMbFilterList; + env->tMbCfg.u8RxFilterMBCnt = CountHardSoftFilter_RX; + + env->tMbCfg.pRxFilterFifoList = NULL; + env->tMbCfg.u8RxFilterFifoCnt = 0; + + env->tMbCfg.pRxBuf = CAN_GET_BUFFER(CAN_INDEX); + + // tx config + if (CAN_INDEX == 0) { + env->tMbCfg.u8TxMsgCnt = COUNT_TX_CAN0_HANDLER; // tx occupy 3 mb + } + + if (CAN_INDEX == 1) { + env->tMbCfg.u8TxMsgCnt = COUNT_TX_CAN1_HANDLER; // tx occupy 3 mb + } + + tRetVal = FLEXCAN_RxFilterConfig(CAN_INDEX, &env->tMbCfg); + + if (CAN_ErrorInterrupt_CallBack == NULL) { + env->tIntCfg.bEnErrorInterrupt = 0U; + env->tIntCfg.pErrorNotify = NULL; + } else { + env->tIntCfg.bEnErrorInterrupt = 1U; + env->tIntCfg.pErrorNotify = CAN_ErrorInterrupt_CallBack; + } + + if (CAN_TxInterrupt_CallBack == NULL) { + env->tIntCfg.bEnTxMBInterrupt = 0U; + env->tIntCfg.pTxMBNotify = NULL; + } else { + env->tIntCfg.bEnTxMBInterrupt = 1U; + env->tIntCfg.pTxMBNotify = CAN_TxInterrupt_CallBack; + } + + if (CAN_RxInterrupt_CallBack == NULL) { + env->tIntCfg.bEnRxMBInterrupt = 0U; + env->tIntCfg.pRxMBNotify = NULL; + } else { + env->tIntCfg.bEnRxMBInterrupt = 1U; + env->tIntCfg.pRxMBNotify = CAN_RxInterrupt_CallBack; + } + + if (CAN_RxFifoInterrupt_CallBack == NULL) { + env->tIntCfg.bEnRxFifoInterrupt = 0U; + env->tIntCfg.pRxFifoNotify = NULL; + } else { + env->tIntCfg.bEnRxFifoInterrupt = 1U; + env->tIntCfg.pRxFifoNotify = CAN_RxFifoInterrupt_CallBack; + } + + + if ((env->tIntCfg.bEnErrorInterrupt) || + (env->tIntCfg.bEnTxMBInterrupt) || + (env->tIntCfg.bEnRxMBInterrupt) || + (env->tIntCfg.bEnRxFifoInterrupt)) { + + NVIC_SetPriority(IRQ_CAN, CAN_PRIORITY); + NVIC_EnableIRQ(IRQ_CAN); + + FLEXCAN_SetInterrupt(CAN_INDEX, &env->tIntCfg); + + } + + if (!env->reInitOne) { + env->reInitOne = true; + +// for (uint8_t i = 0; i < COUNT_TX_HANDLER; ++i) { +// env->access[i] = osMutexNew(NULL); +// env->txDataQueueCan[i] = osMessageQueueNew(1, 1, NULL); +// } + + env->access = osMutexNew(NULL); + vCanSerialPortFrameInitStructure(env, 10, 0); + + CanSerialPortFrameSetType(env, canTypeFrame); + CanSerialPortFrameSetId(env, canId); + + env->canBaudRate = canBaudRate; + } + + FLEXCAN_Start(CAN_INDEX); // Start CAN + + } else { + return false; + } + + + return true; + //конец------------------------------------CAN---------------------------------------------------------------------- + //конец------------------------------------CAN---------------------------------------------------------------------- + //конец------------------------------------CAN---------------------------------------------------------------------- +} + + +bool vCanSerialPortSetMaskCount(tCanSerialPortFrameFlagchip *env, uint8_t maskCount) { + FLEXCAN_ErrorType tRetVal; + uint8_t i; + + + // Отключаем прерывания CAN + NVIC_DisableIRQ(env->IRQ_CAN); + + // Останавливаем CAN модуль (переводим в режим заморозки) + tRetVal = FLEXCAN_Stop(env->CAN_INDEX); + if (tRetVal != FLEXCAN_ERROR_OK) { + NVIC_EnableIRQ(env->IRQ_CAN); + return false; + } + + // Обновляем список фильтров в рабочем буфере (первые maskCount элементов) + for (i = 0; i < maskCount; i++) { + env->pRxMbFilterList[i].eRxFrameType = env->IdHardSoftFilter_RX[i].eRxFrameType; + env->pRxMbFilterList[i].u32RxCanId = env->IdHardSoftFilter_RX[i].u32RxCanId; + env->pRxMbFilterList[i].u32RxCanIdMask = env->IdHardSoftFilter_RX[i].u32RxCanIdMask; + } + + for (i = maskCount; i < 32; i++) { + env->pRxMbFilterList[i].eRxFrameType = env->IdHardSoftFilter_RX[0].eRxFrameType; + env->pRxMbFilterList[i].u32RxCanId = env->IdHardSoftFilter_RX[0].u32RxCanId; + env->pRxMbFilterList[i].u32RxCanIdMask = env->IdHardSoftFilter_RX[0].u32RxCanIdMask; + } + + + // Обновляем конфигурационную структуру для драйвера +// env->CountHardSoftFilter_RX = maskCount; + env->tMbCfg.pRxFilterMBList = env->pRxMbFilterList; +// env->tMbCfg.u8RxFilterMBCnt = maskCount; + + // Убеждаемся, что в tMbCfg сохранены правильные настройки TX + // (они были установлены при инициализации и не должны измениться) + // Если нужно, можно перечитать их из глобальной таблицы драйвера + // но обычно они уже корректны. + + // Переконфигурируем фильтры (без полной деинициализации CAN) + tRetVal = FLEXCAN_RxFilterConfig(env->CAN_INDEX, &env->tMbCfg); + + if (tRetVal != FLEXCAN_ERROR_OK) { + // В случае ошибки пытаемся восстановить предыдущее состояние + // (можно также попробовать перечитать старые фильтры) + FLEXCAN_Start(env->CAN_INDEX); + NVIC_EnableIRQ(env->IRQ_CAN); + return false; + } + + // Запускаем CAN снова (выход из режима заморозки) + tRetVal = FLEXCAN_Start(env->CAN_INDEX); + if (tRetVal != FLEXCAN_ERROR_OK) { + NVIC_EnableIRQ(env->IRQ_CAN); + return false; + } + + // Включаем прерывания обратно + NVIC_EnableIRQ(env->IRQ_CAN); + + return true; +} + + +static void CanSerialPortFrameAddDataQueue(tCanSerialPortFrameFlagchip *env, can_rx_message_type *rx_message_struct, + uint8_t filter) { + osStatus_t status = osMessageQueuePut(env->rxDataQueue[filter], rx_message_struct, 0x0, 0U); + + if (status != osOK) { + asm("nop"); + } + + if (env->rxDataSnifferQueue[filter]) { + status = osMessageQueuePut(env->rxDataSnifferQueue[filter], rx_message_struct, 0x0, 0U); + } +} + + +void CanSerialPortFrameIrqRxProcessingNO_DMA(tCanSerialPortFrameFlagchip *env, FLEXCAN_RxMsgType *pRxCfg) { + if (pRxCfg->eDataType != FLEXCAN_FRAME_DATA) { + return; // Ранний выход + } + + // Копируем основные данные один раз + const uint32_t rx_id = pRxCfg->u32CanId; + const uint8_t dlc = pRxCfg->u32DataLen; + const FLEXCAN_IdType id_type = pRxCfg->eFrameType; + + // Заполняем структуру + can_rx_message_type *pMsg = &env->rx_message_struct; + pMsg->dlc = dlc; + pMsg->id_type = id_type; + + if (id_type == FLEXCAN_ID_STD) { + pMsg->standard_id = rx_id; + } else { + pMsg->extended_id = rx_id; + } + + // Быстрый поиск по ID (можно использовать switch или бинарный поиск) + uint8_t filter_index = 0xFF; + const uint8_t count = env->CountHardSoftFilter_RX; + + // Линейный поиск ID + for (uint8_t i = 0; i < count; i++) { + if (rx_id == env->IdHardSoftFilter_RX[i].u32RxCanId) { + filter_index = env->IdHardSoftFilter_RX[i].filter; + pMsg->filter_index = filter_index; + + if (i > 2) { + asm("nop"); + } + + break; + } + } + + // Если ID найден или фильтров нет + if (filter_index != 0xFF || count == 0) { + + memcpy(pMsg->data, pRxCfg->aData, dlc); + CanSerialPortFrameAddDataQueue(env, pMsg, filter_index != 0xFF ? filter_index : 0); + } +} + + +void CanSerialPortFrameIrqRxProcessing(tCanSerialPortFrameFlagchip *env, uint32_t *pBuf) { + + // message buffer 1th word + uint32_t u32TempAddr = (uint32_t)FLEXCAN_MB_WORDN_ADDR(&pBuf[env->pBufCounter << 2], 0U, 8U, 0U); + + uint32_t dlc = FLEXCAN_MB_DLC_GET(u32TempAddr); + env->rx_message_struct.dlc = FLEXCAN_DlcToDataLen(dlc); + + env->rx_message_struct.id_type = FLEXCAN_MB_IDE_GET(u32TempAddr); + + // message buffer 2th word + u32TempAddr = (uint32_t)FLEXCAN_MB_WORDN_ADDR(&pBuf[env->pBufCounter << 2], 0U, 8U, 4U); + + if (env->rx_message_struct.id_type == FLEXCAN_ID_STD) { + env->rx_message_struct.standard_id = FLEXCAN_MB_STDID_GET(u32TempAddr); + } else { + env->rx_message_struct.extended_id = FLEXCAN_MB_EXTID_GET(u32TempAddr); + } + + uint8_t index = 0xFF; + + for (uint8_t i = 0; i < env->CountHardSoftFilter_RX; ++i) { + + if ((env->rx_message_struct.id_type == FLEXCAN_ID_STD) && + (env->IdHardSoftFilter_RX[i].eRxFrameType == FLEXCAN_ID_STD)) { + + if (env->rx_message_struct.standard_id == env->IdHardSoftFilter_RX[i].u32RxCanId) { + env->rx_message_struct.filter_index = env->IdHardSoftFilter_RX[i].filter; + index = i; + break; + } + + } else { + + if (env->rx_message_struct.extended_id == env->IdHardSoftFilter_RX[i].u32RxCanId) { + + if (env->rx_message_struct.extended_id == env->IdHardSoftFilter_RX[i].u32RxCanId) { + env->rx_message_struct.filter_index = env->IdHardSoftFilter_RX[i].filter; + index = i; + break; + } + + } + + } + + + } + + if (index != 0xFF) { + + // message buffer 3th word + uint32_t *pSrc = (uint32_t * )FLEXCAN_MB_WORDN_ADDR(&pBuf[env->pBufCounter << 2], 0U, 8U, 8U); + uint32_t *pDest = (uint32_t * ) & env->rx_message_struct.data[0]; + + uint32_t u32WordLen = env->rx_message_struct.dlc / 4U + (env->rx_message_struct.dlc % 4U > 0U ? 1U : 0U); + + for (uint32_t u8Index = 0U; u8Index < u32WordLen; ++u8Index) { + REV_BYTES_32(pSrc[u8Index], pDest[u8Index]); + } + + CanSerialPortFrameAddDataQueue(env, &env->rx_message_struct, env->IdHardSoftFilter_RX[index].filter); + + } + + if (env->CountHardSoftFilter_RX == 0) { + // message buffer 3th word + uint32_t *pSrc = (uint32_t * )FLEXCAN_MB_WORDN_ADDR(&pBuf[env->pBufCounter << 2], 0U, 8U, 8U); + uint32_t *pDest = (uint32_t * ) & env->rx_message_struct.data[0]; + + uint32_t u32WordLen = env->rx_message_struct.dlc / 4U + (env->rx_message_struct.dlc % 4U > 0U ? 1U : 0U); + + for (uint32_t u8Index = 0U; u8Index < u32WordLen; ++u8Index) { + REV_BYTES_32(pSrc[u8Index], pDest[u8Index]); + } + + CanSerialPortFrameAddDataQueue(env, &env->rx_message_struct, 0); + } + + ++env->pBufCounter; + + if (env->pBufCounter >= env->DMA_BUF_LEN_RX) { + env->pBufCounter = 0; + } + +} + +static uint16_t vSerialPortFrameReceiveQueue( + tCanSerialPortFrameFlagchip *env, uint8_t *data, uint16_t size, uint32_t timeout, osMessageQueueId_t queueId +) { + uint16_t received = 0; + + if (timeout) { + uint32_t endMs = SystemGetMs() + timeout; + uint32_t leftMs; + + while (size && ((timeout == SystemWaitForever) || (endMs > SystemGetMs()))) { + leftMs = endMs - SystemGetMs(); + if (osMessageQueueGet(queueId, data, NULL, leftMs) == osOK) { + --size; + ++received; + ++data; + } + } + } else { + while (size) { + if (osMessageQueueGet(queueId, data, NULL, 0) == osOK) { + --size; + ++received; + ++data; + } else { + return received; + } + } + } + + return received; +} + +static uint16_t +vCanSerialPortFrameReceive(tCanSerialPortFrameFlagchip *env, uint8_t idFilter, uint8_t *data, uint16_t size, + uint32_t timeout) { + return vSerialPortFrameReceiveQueue(env, data, size, timeout, env->rxDataQueue[idFilter]); +} + +//static uint16_t +//vCanSerialPortFrameReceiveSniffer(tCanSerialPortFrameFlagchip *env, uint8_t idFilter, uint8_t *data, uint16_t size, +// uint32_t timeout) { + +// return env->rxDataSnifferQueue +// ? vSerialPortFrameReceiveQueue(env, data, size, timeout, env->rxDataSnifferQueue[idFilter]) +// : 0; +//} + +#define TRANSMIT_MULTI_FRAME_TX 1 + +//#define TRANSMIT_MULTI_FRAME_DBG_TX 1 + +#ifdef TRANSMIT_MULTI_FRAME_DBG_TX +uint8_t max0_i =0; +uint8_t max1_i =0; + +uint8_t handler_0[1000]; +uint16_t handler_0_cnt = 0; + +uint8_t handler_1[1000]; +uint16_t handler_1_cnt = 0; + +#endif + +static FLEXCAN_ErrorType SendToCan(tCanSerialPortFrameFlagchip *env, FLEXCAN_TxMsgType *const pTxMsg, uint32_t timeout) { + FLEXCAN_ErrorType tRetval = FLEXCAN_ERROR_TIMEOUT; + +#ifdef TRANSMIT_MULTI_FRAME_TX + uint8_t ready = 0; + + uint32_t endMs = SystemGetMs() + timeout; + + while ((ready == 0) && (endMs > SystemGetMs())) { + + if (env->CAN_INDEX == 0) { + for (uint8_t i = 0; i < COUNT_TX_CAN0_HANDLER; ++i) { + ready = IsTxBufferFree_ByCode(env->CAN_INDEX, i); + + if (ready) { + pTxMsg->u8TxHandler = i; + break; + } else { +#ifdef TRANSMIT_MULTI_FRAME_DBG_TX + handler_0[handler_0_cnt] = i; + handler_0_cnt++; + if (handler_0_cnt >= 1000) { + handler_0_cnt = 0; + } + + if (i > max0_i) { + max0_i = i; + } + + if (max0_i >= COUNT_TX_CAN0_HANDLER) { + asm("nop"); + } +#endif + } + } + + } + + + + if (env->CAN_INDEX == 1) { + for (uint8_t i = 0; i < COUNT_TX_CAN1_HANDLER; ++i) { + ready = IsTxBufferFree_ByCode(env->CAN_INDEX, i); + + if (ready) { + pTxMsg->u8TxHandler = i; + break; + } else { +#ifdef TRANSMIT_MULTI_FRAME_DBG_TX + handler_1[handler_1_cnt] = i; + handler_1_cnt++; + if (handler_1_cnt >= 1000) { + handler_1_cnt = 0; + } + + if (i > max1_i) { + max1_i = i; + } + + if (max1_i >= COUNT_TX_CAN1_HANDLER) { + asm("nop"); + } +#endif + } + } + + + } + + } + + + pTxMsg->bWaitTxCompleted = 0; + + tRetval = FLEXCAN_TransmitData(env->CAN_INDEX, pTxMsg); + +#endif + + + +#ifndef TRANSMIT_MULTI_FRAME_TX + tRetval = FLEXCAN_TransmitData(env->CAN_INDEX, pTxMsg); + if (tRetval != FLEXCAN_ERROR_OK) { + FLEXCAN_TransmitAbort(env->CAN_INDEX, pTxMsg->u8TxHandler); + } else { + FLEXCAN_TransmitProcess(env->CAN_INDEX, pTxMsg->u8TxHandler); + } +#endif + + return tRetval; +} + + +uint16_t vCanSerialPortFrameTransmit(tCanSerialPortFrameFlagchip *env, uint8_t *data, uint16_t size, uint32_t adr, + uint8_t canType, uint32_t timeout) { + + + timeout = 5; + + uint16_t sent = 0; + + if (osMutexAcquire(env->access, 1000) == osOK) { + + env->id = adr; + env->canTypeFrame = canType; + + uint16_t fullSize = size / 8; + uint8_t tailSize = size % 8; + + FLEXCAN_TxMsgType tTxMsg = {0}; + FLEXCAN_ErrorType tRetval; + + tTxMsg.u32CanId = env->id; + tTxMsg.u8TxHandler = 0U; + + tTxMsg.bEnFd = FALSE; + tTxMsg.bEnBrs = FALSE; + tTxMsg.u32DataLen = 8; + + tTxMsg.eDataType = FLEXCAN_FRAME_DATA; + tTxMsg.eFrameType = (FLEXCAN_IdType) env->canTypeFrame; + tTxMsg.bWaitTxCompleted = 1U; + tTxMsg.u16WaitTxTimeout = 500000U; + + + uint16_t len = 0; + for (uint16_t i = 0; i < fullSize; ++i) { + + FCFUNC_FcOwnMemcpy(tTxMsg.aData, &data[len], 8, NULL); + len += 8; + + tRetval = SendToCan(env, &tTxMsg, timeout); + + sent += 8; + size -= 8; + } + + if (tailSize) { + tTxMsg.u32DataLen = tailSize; + + FCFUNC_FcOwnMemcpy(tTxMsg.aData, &data[len], tailSize, NULL); + + tRetval = SendToCan(env, &tTxMsg, timeout); + + sent += tailSize; + size -= tailSize; + } + + osMutexRelease(env->access); + } + + return sent; +} + + +tSerialPortFrameIO CanPortFrame_GetIo(tCanSerialPortFrameFlagchip *env) { + tSerialPortFrameIO io = { + .env = env, + .receive = (SerialPortFrameReceivedTransaction) vCanSerialPortFrameReceive, + .transmit = (SerialPortFrameTransmitTransaction) vCanSerialPortFrameTransmit + }; + return io; +} + +tSerialPortFrameIO CanPort_GetSnifferIo(tCanSerialPortFrameFlagchip *env) { + tSerialPortFrameIO io = { + .env = env, + .receive = (SerialPortFrameReceivedTransaction) vCanSerialPortFrameReceive, + .transmit = (SerialPortFrameTransmitTransaction) vCanSerialPortFrameTransmit + }; + return io; +} \ No newline at end of file diff --git a/MODULES/CanSerialPortFrame_Flagchip_FC7240/modular.json b/MODULES/CanSerialPortFrame_Flagchip_FC7240/modular.json new file mode 100644 index 0000000..631f702 --- /dev/null +++ b/MODULES/CanSerialPortFrame_Flagchip_FC7240/modular.json @@ -0,0 +1,24 @@ +{ + "dep": [ + { + "type": "local", + + "dir": "./MODULES/SerialPort" + }, + { + "type": "local", + + "dir": "./MODULES/SerialPortFrameInterface" + } + ], + "cmake": { + "inc_dirs": [ + "Inc" + ], + "srcs": [ + "Src/**.c" + ] + } +} + + diff --git a/MODULES/CanSerialPortFrame_TP/Inc/CanSerialPortFrameTP.h b/MODULES/CanSerialPortFrame_TP/Inc/CanSerialPortFrameTP.h new file mode 100644 index 0000000..bc210ae --- /dev/null +++ b/MODULES/CanSerialPortFrame_TP/Inc/CanSerialPortFrameTP.h @@ -0,0 +1,155 @@ +// +// Created by cfif on 16.03.2024. +// + +#ifndef CAN_MODULE_CAN_FRAME_UDS_H +#define CAN_MODULE_CAN_FRAME_UDS_H + +#include "SerialPortFrameIO.h" +#include "CanSerialPortFrame.h" +#include "LoggerToSerialPort.h" +#include "CmsisRtosThreadUtils.h" +#include "SystemMutexCmsis.h" + +#define LOG_UDS_TP 0 + +#define TP_FRAME_PADDING 0xAA + +#define WAIT_FC_FRAME_TIMEOUT 2000 +#define WAIT_FF_FRAME_TIMEOUT 2000 + +#define WAIT_FRAME_WRITE 100 + +#define LEN_DEBUG_TP_BUFF 128 + +#define timeout_StMin 50 // Сепаратор между многокадровыми сообщениями +#define timeout_Br 10 // Перед отправкой FlowControl (для получения остальных данных) + +typedef enum { + TP_TYPE_FRAME_SF = 0, + TP_TYPE_FRAME_FF = 1, + TP_TYPE_FRAME_CF = 2, + TP_TYPE_FRAME_FC = 3 +} eTpTypeFrame; + +typedef enum { + TP_RECEIVED_DATA = 0, + TP_RECEIVED_FC_DATA = 1, + TP_ERROR_FS_ERROR_SIZE = 2, + TP_ERROR_FC_TIMEOUT = 3, + TP_ERROR_FC_ERROR = 4, + TP_ERROR_FF_ERROR = 5, + TP_ERROR_FF_ERROR_SIZE = 6, + TP_ERROR_FF_ERROR_TIMEOUT = 7, + TP_ERROR_CF_ERROR = 8, + TP_ERROR_CF_ERROR_SIZE = 9, + TP_ERROR_CF_ERROR_SN = 10, + TP_ERROR_WRONG_ADDRESS= 11, + TP_STANDBY = 12, + TP_ERROR_SF_ERROR = 13 + +} eTpResult; + +typedef struct __attribute__ ((packed)) { + eTpTypeFrame typeFrame: 4; +} eTpFrameHead; + +typedef struct __attribute__ ((packed)) { + uint8_t dl: 4; + eTpTypeFrame typeFrame: 4; + uint8_t data[7]; +} eTpFrameSF; + +typedef struct __attribute__ ((packed)) { + uint8_t dlM: 4; + eTpTypeFrame typeFrame: 4; + uint8_t dlL; + uint8_t data[6]; +} eTpFrameFF; + +typedef struct __attribute__ ((packed)) { + uint8_t sn: 4; + eTpTypeFrame typeFrame: 4; + uint8_t data[7]; +} eTpFrameCF; + +typedef struct __attribute__ ((packed)) { + uint8_t status: 4; + eTpTypeFrame typeFrame: 4; + uint8_t blockSize; + uint8_t timeST; +} eTpFrameFC; + +typedef struct { + uint32_t adrCan; + uint16_t len; + uint8_t data[4096]; +} tCanTP_data; + +typedef void (*tReceivedTP_func)(void *arg, tCanTP_data *data); +typedef bool (*tReceivedCan_func)(void *arg, can_rx_message_type *data); + +typedef struct { + tSerialPortFrameIO *ioCanFrame; + tLoggerInterface *logger; + char hexString[LEN_DEBUG_TP_BUFF]; + bool isFlowControl; + + uint32_t timeoutFF; + + tCanTP_data *dataBuf; + uint16_t dataBufMaxSize; + uint16_t dataBufWorkLen; + uint16_t dataBufLen; + + uint16_t dataReceivedConsecutiveFrameLen; + uint8_t sn; + + tReceivedCan_func ReceivedCan_func; + void *callback_argCan; + + tReceivedTP_func receivedTP_func; + void *callback_argTp; + + uint8_t filterIdCount; + uint32_t *filterReqId; + uint32_t *filterRespId; + uint8_t *filterDirReq; + + struct { + osThreadId_t id; + uint32_t stack[384]; + StaticTask_t controlBlock; + osThreadAttr_t attr; + } threadCanListener; + +// tStaticThreadBlock(384) T_can_Listener; +} tCanSerialPortFrameTp; + +void CanSerialPortFrameTpInit( + tCanSerialPortFrameTp *env, + + + tReceivedCan_func receivedCan_func, + void *callback_argCan, + + tReceivedTP_func receivedTP_func, + void *callback_argTp, + + tSerialPortFrameIO *ioCanFrame, + tCanTP_data *dataBuf, + uint16_t dataBufMaxSize, + tLoggerInterface *logger, + + uint8_t filterIdCount, + uint32_t *filterReqId, + uint32_t *filterRespId, + uint8_t *filterDirReq +); + +void CanSerialPortFrameTp_Start(tCanSerialPortFrameTp *env); + +bool +CanSerialPortFrameTpTransmit(tCanSerialPortFrameTp *env, uint8_t *data, uint16_t size, uint32_t id, uint32_t timeout); + +#endif //CAN_MODULE_CAN_FRAME_UDS_H diff --git a/MODULES/CanSerialPortFrame_TP/Src/CanSerialPortFrameTP.c b/MODULES/CanSerialPortFrame_TP/Src/CanSerialPortFrameTP.c new file mode 100644 index 0000000..256e2e3 --- /dev/null +++ b/MODULES/CanSerialPortFrame_TP/Src/CanSerialPortFrameTP.c @@ -0,0 +1,535 @@ +// +// Created by cfif on 16.03.2024. +// +#include +#include "CanSerialPortFrameTP.h" +#include "memory.h" +#include "AsciiStringAssmeblingUtils.h" +#include "SystemMutexCmsis.h" +#include "CanPorts.h" +#include + +#define LOG_SIGN "CAN_TP" +#define LOGGER env->logger + + +static char strPrintfDebug_TP[80]; + +static void PrintfDebug(uint8_t *data, uint8_t dlc) { + + switch (dlc) { + + case 0: + sprintf(strPrintfDebug_TP, " "); + break; + case 1: + sprintf(strPrintfDebug_TP, "%02X", data[0]); + break; + case 2: + sprintf(strPrintfDebug_TP, "%02X:%02X", data[0], data[1]); + break; + case 3: + sprintf(strPrintfDebug_TP, "%02X:%02X:%02X", data[0], data[1], data[2]); + break; + case 4: + sprintf(strPrintfDebug_TP, "%02X:%02X:%02X:%02X", data[0], data[1], data[2], data[3]); + break; + case 5: + sprintf(strPrintfDebug_TP, "%02X:%02X:%02X:%02X:%02X", data[0], data[1], data[2], data[3], + data[4]); + break; + case 6: + sprintf(strPrintfDebug_TP, "%02X:%02X:%02X:%02X:%02X:%02X", data[0], data[1], data[2], data[3], + data[4], data[5]); + break; + case 7: + sprintf(strPrintfDebug_TP, "%02X:%02X:%02X:%02X:%02X:%02X:%02X", data[0], data[1], data[2], + data[3], data[4], + data[5], data[6]); + break; + case 8: + sprintf(strPrintfDebug_TP, "%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X ", data[0], data[1], + data[2], data[3], data[4], + data[5], data[6], data[7]); + break; + default: + sprintf(strPrintfDebug_TP, " "); + } + +} + + +char *sendLogCanTpHex(tCanSerialPortFrameTp *env, uint8_t *data, size_t size) { + memset(env->hexString, 0, sizeof(env->hexString)); + size_t len = 0; + + + uint8_t full = size / 8; + uint8_t tail = size % 8; + + for (uint8_t i = 0; i < full; ++i) { + PrintfDebug(&data[i * 8], 8); + + if ((len + strlen(strPrintfDebug_TP)) < LEN_DEBUG_TP_BUFF) { + memcpy(&env->hexString[len], strPrintfDebug_TP, strlen(strPrintfDebug_TP)); + len += strlen(strPrintfDebug_TP); + } else { + return env->hexString; + } + + } + + if (tail > 0) { + PrintfDebug(&data[full * 8], tail); + + if ((len + strlen(strPrintfDebug_TP)) < LEN_DEBUG_TP_BUFF) { + memcpy(&env->hexString[len], strPrintfDebug_TP, strlen(strPrintfDebug_TP)); + len += strlen(strPrintfDebug_TP); + } else { + return env->hexString; + } + + } + + return env->hexString; +} + +uint16_t sendFlowFrame(tCanSerialPortFrameTp *env, uint32_t id, uint32_t timeout) { + uint8_t dataTpFrame[8]; + + memset(dataTpFrame, TP_FRAME_PADDING, sizeof(dataTpFrame)); + + eTpFrameFC *frame = (eTpFrameFC *) dataTpFrame; + frame->typeFrame = TP_TYPE_FRAME_FC; + frame->status = 0; + frame->blockSize = 0; + frame->timeST = 0; + +// SystemDelayMs(timeout_Br); + uint16_t sent = env->ioCanFrame->transmit(env->ioCanFrame->env, (uint8_t *) frame, 8, id, + PROTOCOL_CAN_TYPE_UDS, timeout); + + return sent; +} + + +uint16_t sendSingleFrame(tCanSerialPortFrameTp *env, uint8_t *data, uint16_t size, uint32_t id, uint32_t timeout) { + uint8_t dataTpFrame[8]; + + memset(dataTpFrame, TP_FRAME_PADDING, sizeof(dataTpFrame)); + + eTpFrameSF *frame = (eTpFrameSF *) dataTpFrame; + frame->typeFrame = TP_TYPE_FRAME_SF; + frame->dl = size; + + memcpy(&frame->data[0], data, size); + +// SystemDelayMs(timeout_Br); // ?? + uint16_t sent = env->ioCanFrame->transmit(env->ioCanFrame->env, (uint8_t *) frame, 8, id, + PROTOCOL_CAN_TYPE_UDS, timeout); + + return sent; +} + +uint16_t sendConsecutiveFrame(tCanSerialPortFrameTp *env, uint8_t *data, uint16_t size, uint32_t id, uint8_t sn, + uint32_t timeout) { + + uint8_t dataTpFrame[8]; + memset(dataTpFrame, TP_FRAME_PADDING, sizeof(dataTpFrame)); + + eTpFrameCF *frame = (eTpFrameCF *) dataTpFrame; + frame->typeFrame = TP_TYPE_FRAME_CF; + frame->sn = sn; + + memcpy(&frame->data[0], data, size); + + SystemDelayMs(timeout_StMin); + + uint16_t sent = env->ioCanFrame->transmit(env->ioCanFrame->env, (uint8_t *) frame, 8, id, + PROTOCOL_CAN_TYPE_UDS, timeout); + + + return sent; + +} + +eTpResult vCanSerialPortFrameTpReceive(tCanSerialPortFrameTp *env, uint32_t timeout) { + can_rx_message_type canFrame; + + if ((env->timeoutFF > 0) && (env->timeoutFF < SystemGetMs())) { + env->timeoutFF = 0; + env->dataReceivedConsecutiveFrameLen = 0; + env->dataBufLen = 0; + env->dataBufWorkLen = 0; + + return TP_ERROR_FF_ERROR_TIMEOUT; + } + + uint16_t recv = 0; + + recv = env->ioCanFrame->receive(env->ioCanFrame->env, PROTOCOL_CAN_UDS, (uint8_t *) &canFrame, 1, timeout); + + if (recv == 0) + return TP_STANDBY; + + bool isTesterPresent = env->ReceivedCan_func(env->callback_argCan, &canFrame); + + if (isTesterPresent) { + return TP_STANDBY; + } + + bool isFilterFind = false; + uint32_t reqId = 0; + for (uint8_t i = 0; i < env->filterIdCount; ++i) { + if (canFrame.standard_id == env->filterReqId[i]) { + + reqId = env->filterRespId[i]; + + isFilterFind = true; + break; + } + } + + if (!isFilterFind) { + return TP_ERROR_WRONG_ADDRESS; + } + + + if ((recv > 0) && (canFrame.dlc == 8)) { + + // Flow control Frame – FC – фрейм управления потоком + if ((canFrame.data[0] >> 4) == TP_TYPE_FRAME_FC) { + eTpFrameFC *frame = (eTpFrameFC *) canFrame.data; + + if (frame->status == 0) + return TP_RECEIVED_FC_DATA; + + return TP_ERROR_FC_ERROR; + } + + // Single Frame SF – Однократный фрейм + if ((canFrame.data[0] >> 4) == TP_TYPE_FRAME_SF) { + + if (env->dataReceivedConsecutiveFrameLen) { + return TP_ERROR_SF_ERROR; + } + + eTpFrameSF *frame = (eTpFrameSF *) canFrame.data; + + if (frame->dl < env->dataBufMaxSize) { + //memcpy(env->dataBuf, &canFrame.data[1], frame->dl); + env->dataBufLen = frame->dl; + + memcpy(env->dataBuf->data, &canFrame.data[1], frame->dl); + env->dataBuf->len = env->dataBufLen; + env->dataBuf->adrCan = canFrame.standard_id; + + env->dataBufWorkLen = 0; + return TP_RECEIVED_DATA; + } else { + env->dataBufWorkLen = 0; + return TP_ERROR_FS_ERROR_SIZE; + } + } + + // First Frame FF – Первый фрейм из серии фреймов + if ((canFrame.data[0] >> 4) == TP_TYPE_FRAME_FF) { + if (env->dataReceivedConsecutiveFrameLen) { + return TP_ERROR_FF_ERROR; + } + + eTpFrameFF *frame = (eTpFrameFF *) canFrame.data; + + if (env->dataBufWorkLen + (frame->dlL | (frame->dlM << 8)) > env->dataBufMaxSize) { + return TP_ERROR_FF_ERROR_SIZE; + } + + uint16_t dll = frame->dlL | (frame->dlM << 8); + if (dll > 100) { + asm("nop"); + } + + env->timeoutFF = SystemGetMs() + WAIT_FF_FRAME_TIMEOUT; + + env->sn = 1; + env->dataBufWorkLen = 0; + env->dataReceivedConsecutiveFrameLen = (frame->dlL | (frame->dlM << 8)); + + for (uint8_t j = 2; j < 8; ++j) { + //env->dataBuf[env->dataBufWorkLen] = canFrame.data[j]; + env->dataBuf->data[env->dataBufWorkLen] = canFrame.data[j]; + + ++env->dataBufWorkLen; + if (env->dataBufWorkLen > env->dataBufMaxSize) { + env->timeoutFF = 0; + env->dataReceivedConsecutiveFrameLen = 0; + env->dataBufWorkLen = 0; + return TP_ERROR_CF_ERROR_SIZE; + } + + --env->dataReceivedConsecutiveFrameLen; + } + + sendFlowFrame(env, reqId, WAIT_FRAME_WRITE); + } + + // Consecutive Frame CF – последующий фрейм. + if ((canFrame.data[0] >> 4) == TP_TYPE_FRAME_CF) { + + if (env->dataReceivedConsecutiveFrameLen == 0) { + return TP_ERROR_CF_ERROR; + } + + eTpFrameCF *frame = (eTpFrameCF *) canFrame.data; + + if (frame->sn != env->sn) { + env->timeoutFF = 0; + env->dataReceivedConsecutiveFrameLen = 0; + env->dataBufWorkLen = 0; + return TP_ERROR_CF_ERROR_SN; + } + + ++env->sn; + if (env->sn > 15) + env->sn = 0; + + for (uint8_t j = 1; j < 8; ++j) { + //env->dataBuf[env->dataBufWorkLen] = canFrame.data[j]; + env->dataBuf->data[env->dataBufWorkLen] = canFrame.data[j]; + + ++env->dataBufWorkLen; + if (env->dataBufWorkLen > env->dataBufMaxSize) { + env->timeoutFF = 0; + env->dataReceivedConsecutiveFrameLen = 0; + env->dataBufWorkLen = 0; + return TP_ERROR_CF_ERROR_SIZE; + } + + --env->dataReceivedConsecutiveFrameLen; + if (env->dataReceivedConsecutiveFrameLen == 0) { + env->timeoutFF = 0; + env->dataBufLen = env->dataBufWorkLen; + + env->dataBuf->len = env->dataBufLen; + env->dataBuf->adrCan = canFrame.standard_id; + + env->dataBufWorkLen = 0; + return TP_RECEIVED_DATA; + } + } + + } + + } + + return TP_ERROR_FC_TIMEOUT; +} + + +bool waitFlowControl(tCanSerialPortFrameTp *env) { + + env->isFlowControl = true; + + eTpResult result = vCanSerialPortFrameTpReceive(env, WAIT_FC_FRAME_TIMEOUT); + + if (result == TP_RECEIVED_FC_DATA) { + if (env->isFlowControl) { + env->isFlowControl = false; +// LoggerStrInfoStatic(LOGGER, LOG_SIGN, "Flow control frame accepted"); + } else { + LoggerErrorStatic(LOGGER, LOG_SIGN, "Error: An unexpected Flow Control Frame was received"); + } + } + + if (env->isFlowControl) { + LoggerStrInfoStatic(LOGGER, LOG_SIGN, "Flow control frame timeout"); + return false; + } + + return true; +} + +bool sendFirstFrame(tCanSerialPortFrameTp *env, uint8_t *data, uint16_t size, uint32_t id, uint32_t timeout) { + uint8_t dataTpFrame[8]; + uint16_t pDataLen = 0; + + memset(dataTpFrame, TP_FRAME_PADDING, sizeof(dataTpFrame)); + + eTpFrameFF *frame = (eTpFrameFF *) dataTpFrame; + frame->typeFrame = TP_TYPE_FRAME_FF; + frame->dlL = size; + frame->dlM = (size >> 8); + + memcpy(&frame->data[0], &data[pDataLen], 6); + pDataLen += 6; + +// SystemDelayMs(timeout_Br); // ?? + env->ioCanFrame->transmit(env->ioCanFrame->env, (uint8_t *) frame, 8, id, + PROTOCOL_CAN_TYPE_UDS, timeout); + + bool result = waitFlowControl(env); + if (!result) + return false; + + uint16_t countPacketFull = (size - 6) / 7; + uint16_t sizePacketTail = (size - 6) % 7; + + uint8_t sn = 1; + + for (uint16_t i = 0; i < countPacketFull; ++i) { + + sendConsecutiveFrame(env, &data[pDataLen], 7, id, sn, timeout); + pDataLen += 7; + + ++sn; + if (sn > 15) { + sn = 0; + } + } + + if (sizePacketTail) { + sendConsecutiveFrame(env, &data[pDataLen], sizePacketTail, id, sn, timeout); + pDataLen += sizePacketTail; + } + + return true; + +} + +bool +CanSerialPortFrameTpTransmit(tCanSerialPortFrameTp *env, uint8_t *data, uint16_t size, uint32_t id, uint32_t timeout) { + bool result; + + // Single Frame SF + if (size <= 7) { + result = sendSingleFrame(env, data, size, id, timeout); + } else { + result = sendFirstFrame(env, data, size, id, timeout); + } + + return result; +} + + +_Noreturn void CanTpProcessing_ListenerTask(tCanSerialPortFrameTp *env) { + while (1) { + eTpResult result = vCanSerialPortFrameTpReceive(env, 1000); + + if (result == TP_RECEIVED_FC_DATA) { + LoggerErrorStatic(LOGGER, LOG_SIGN, "Error: An unexpected Flow Control Frame was received (listener)"); + } + + if (result == TP_RECEIVED_DATA) { + +#if (LOG_UDS_TP == 1) + sendLogCanTpHex(env, env->dataBuf->data, env->dataBuf->len); + LoggerFormatInfo(LOGGER, LOG_SIGN, "Data received: %s", env->hexString) +#endif + env->receivedTP_func(env->callback_argTp, env->dataBuf); + + } + + if (result == TP_ERROR_FS_ERROR_SIZE) { + LoggerErrorStatic(LOGGER, LOG_SIGN, "Error: Receive buffer overflow (1)"); + } + + if (result == TP_ERROR_FC_ERROR) { + LoggerErrorStatic(LOGGER, LOG_SIGN, "Error: An error status was set in the Flow Control Frame"); + } + + if (result == TP_ERROR_FF_ERROR) { + LoggerErrorStatic(LOGGER, LOG_SIGN, + "Error: First Frame FF received, but Consecutive Frame reception is not yet complete"); + } + + + if (result == TP_ERROR_FF_ERROR_SIZE) { + LoggerErrorStatic(LOGGER, LOG_SIGN, "Error: Receive buffer overflow (2)"); + } + + if (result == TP_ERROR_CF_ERROR) { + LoggerErrorStatic(LOGGER, LOG_SIGN, "Error: Unexpected Consecutive Frame received"); + } + + if (result == TP_ERROR_CF_ERROR_SIZE) { + LoggerErrorStatic(LOGGER, LOG_SIGN, "Error: Receive buffer overflow (3)"); + } + + if (result == TP_ERROR_CF_ERROR_SN) { + LoggerErrorStatic(LOGGER, LOG_SIGN, "Error: SN counter mismatch in Consecutive Frame"); + } + + if (result == TP_ERROR_FF_ERROR_TIMEOUT) { + LoggerErrorStatic(LOGGER, LOG_SIGN, "Error: The Consecutive Frame timed out"); + } + + if (result == TP_ERROR_SF_ERROR) { + // LoggerErrorStatic(LOGGER, LOG_SIGN, "Error: Single Frame SF received, but Consecutive Frame reception is not yet complete"); + } + + } +} + +void CanSerialPortFrameTp_Start(tCanSerialPortFrameTp *env) { +// ThreadBlock_Start(env->T_can_Listener, env, CanTpProcessing_ListenerTask); + + if (!env->threadCanListener.id) { + env->threadCanListener.id = osThreadNew((osThreadFunc_t) (CanTpProcessing_ListenerTask), (void *) (env), &env->threadCanListener.attr); + SystemDelayMs(10); + } +} + +void CanSerialPortFrameTpInit( + tCanSerialPortFrameTp *env, + + tReceivedCan_func receivedCan_func, + void *callback_argCan, + + tReceivedTP_func receivedTP_func, + void *callback_arg, + + tSerialPortFrameIO *ioCanFrame, + tCanTP_data *dataBuf, + uint16_t dataBufMaxSize, + tLoggerInterface *logger, + + uint8_t filterIdCount, + uint32_t *filterReqId, + uint32_t *filterRespId, + uint8_t *filterDirReq + +) { + env->ioCanFrame = ioCanFrame; + + env->dataBuf = dataBuf; + env->dataBufMaxSize = dataBufMaxSize; + env->dataBufLen = 0; + env->dataBufWorkLen = 0; + env->isFlowControl = false; + + env->filterIdCount = filterIdCount; + env->filterReqId = filterReqId; + env->filterRespId = filterRespId; + env->filterDirReq = filterDirReq; + + env->dataReceivedConsecutiveFrameLen = 0; + + + env->ReceivedCan_func = receivedCan_func; + env->callback_argCan = callback_argCan; + + + env->receivedTP_func = receivedTP_func; + env->callback_argTp = callback_arg; + + env->timeoutFF = 0; + + env->logger = logger; + +// InitThreadBlock(env->T_can_Listener, "CanTpUds", osPriorityNormal); + InitThreadAtrStatic(&env->threadCanListener.attr, "CanTpUds", env->threadCanListener.controlBlock, env->threadCanListener.stack, + osPriorityNormal); + +} + + diff --git a/MODULES/CanSerialPortFrame_TP/modular.json b/MODULES/CanSerialPortFrame_TP/modular.json new file mode 100644 index 0000000..71971cd --- /dev/null +++ b/MODULES/CanSerialPortFrame_TP/modular.json @@ -0,0 +1,10 @@ +{ + "cmake": { + "inc_dirs": [ + "Inc" + ], + "srcs": [ + "Src/**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/CanSerialPortFrame_XCP/Inc/CanSerialPortFrameXCP.h b/MODULES/CanSerialPortFrame_XCP/Inc/CanSerialPortFrameXCP.h new file mode 100644 index 0000000..f242901 --- /dev/null +++ b/MODULES/CanSerialPortFrame_XCP/Inc/CanSerialPortFrameXCP.h @@ -0,0 +1,693 @@ +// +// Created by cfif on 16.03.2024. +// + +#ifndef CAN_MODULE_CAN_FRAME_XCP_H +#define CAN_MODULE_CAN_FRAME_XCP_H20 + +#include "SerialPortFrameIO.h" +#include "CanSerialPortFrame.h" +#include "LoggerToSerialPort.h" +#include "CmsisRtosThreadUtils.h" +#include "SystemMutexCmsis.h" +#include "VarsTabDumpObserver.h" + + +typedef enum { + XCP_ERR_CMD_SYNCH = 0x00, + XCP_ERR_CMD_BUSY = 0x10, + XCP_ERR_DAQ_ACTIVE = 0x11, + XCP_ERR_PGM_ACTIVE = 0x12, + XCP_ERR_CMD_UNKNOWN = 0x20, + XCP_ERR_CMD_SYNTAX = 0x21, + XCP_ERR_OUT_OF_RANGE = 0x22, + XCP_ERR_WRITE_PROTECTED = 0x23, + XCP_ERR_ACCESS_DENIED = 0x24, + XCP_ERR_ACCESS_LOCKED = 0x25, + XCP_ERR_PAGE_NOT_VALID = 0x26, + XCP_ERR_MODE_NOT_VALID = 0x27, + XCP_ERR_SEGMENT_NOT_VALID = 0x28, + XCP_ERR_SEQUENCE = 0x29, + XCP_ERR_DAQ_CONFIG = 0x2A, + XCP_ERR_MEMORY_OVERFLOW = 0x30, + XCP_ERR_GENERIC = 0x31, + XCP_ERR_VERIFY = 0x32, + XCP_ERR_RESOURCE_TEMPORARY_NOT_ACCESSIBLE = 0x33, + XCP_ERR_SUBCMD_UNKNOWN = 0x34 +} eXcpError; + +typedef enum { + XCP_COMMAND_CONNECT = 0xFF, + XCP_COMMAND_DISCONNECT = 0xFE, + XCP_COMMAND_GET_STATUS = 0xFD, + XCP_COMMAND_SYNCH = 0xFC, + XCP_GET_COMM_MODE_INFO = 0xFB, + + XCP_GET_SEED = 0xF8, + XCP_UNLOCK = 0xF7, + + XCP_COMMAND_SET_MTA = 0xF6, + + XCP_COMMAND_UPLOAD = 0xF5, + XCP_COMMAND_SHORT_UPLOAD = 0xF4, + + XCP_COMMAND_DOWNLOAD = 0xF0, + XCP_COMMAND_DOWNLOAD_NEXT = 0xEF, + XCP_COMMAND_DOWNLOAD_MAX = 0xEE, + + XCP_CLEAR_DAQ_LIST = 0xE3, + XCP_GET_DAQ_LIST_INFO = 0xD8, + + XCP_FREE_DAQ = 0xD6, + XCP_ALLOC_DAQ = 0xD5, + XCP_ALLOC_ODT = 0xD4, + XCP_ALLOC_ODT_ENTRY = 0xD3, + + XCP_SET_DAQ_PTR = 0xE2, + XCP_WRITE_DAQ = 0xE1, + XCP_SET_DAQ_LIST_MODE = 0xE0, + XCP_START_STOP_DAQ_LIST = 0xDE, + XCP_START_STOP_SYNCH = 0xDD, + +} eXcpTypeCommand; + +typedef enum { + XCP_PROTECT_CAL_PAG = 0x01, + XCP_PROTECT_DAQ = 0x04, + XCP_PROTECT_STM = 0x08, + XCP_PROTECT_PGM = 0x10 +} eTypeProtect; + +typedef enum { + XCP_STOP = 0, + XCP_START = 1, + XCP_SELECT = 2 + +} eXcpDAQ_Mode; + +typedef enum { + XCP_SYNC_STOP_ALL = 0, + XCP_SYNC_START_SEL = 1, + XCP_SYNC_STOP_SEL = 2 + +} eXcpDAQ_Sync_Mode; + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + + uint8_t CAL_PAG: 1; // CALibration and PAGing + uint8_t reserve1: 1; + uint8_t DAQ: 1; // DAQ lists supported + uint8_t STIM: 1; // STIMulation + uint8_t PGM: 1; // Flash programming + uint8_t reserve2: 1; + uint8_t reserve3: 1; + uint8_t reserve4: 1; + + uint8_t BYTE__ORDER: 1; // 0 - Intel + uint8_t ADDRESS_GRANULARITY_0: 1; + uint8_t ADDRESS_GRANULARITY_1: 1; + uint8_t reserve5: 1; + uint8_t reserve6: 1; + uint8_t reserve7: 1; + uint8_t _SLAVE_BLOCK_MODE: 1; + uint8_t OPTIONAL: 1; + + uint8_t MAX_CTO_; + uint16_t MAX_DTO_; + + uint8_t XCP_PROTOCOL_VER; + uint8_t XCP_TRANSPORT_VER; + +} eXcpCommand_CONNECT; + + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + + uint8_t STORE_CAL_REQ: 1; + uint8_t reserve1: 1; + uint8_t STORE_DAQ_REQ: 1; + uint8_t CLEAR_DAQ_REQ: 1; + uint8_t reserve2: 1; + uint8_t reserve3: 1; + uint8_t DAQ_RUNNING: 1; + uint8_t RESUME: 1; + + uint8_t CAL_PAG: 1; + uint8_t reserve5: 1; + uint8_t DAQ: 1; + uint8_t STIM: 1; + uint8_t PGM: 1; + uint8_t reserve6: 1; + uint8_t reserve7: 1; + uint8_t reserve8: 1; + + uint8_t STATE_NUMBER; + + uint16_t SESSION_CONFIGURATION_ID; + + +} eXcpCommand_GET_STATUS; + + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + + uint8_t RESERVED1; + + uint8_t _MASTER_BLOCK_MODE: 1; + uint8_t INTERLEAVED_MODE: 1; + uint8_t RESERVED2: 6; + + uint8_t RESERVED3; + uint8_t MAX_BS; + uint8_t MIN_ST; + uint8_t QUEUE_SIZE; + uint8_t VERSION; +} eXcpCommand_GET_COMM_MODE_INFO; + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + uint8_t COUNT; +} eXcpCommand_Upload; + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + uint8_t COUNT; + uint8_t RESERVED; + uint8_t ADR_EX; + uint32_t ADR; +} eXcpCommand_SHORT_UPLOAD; + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + uint8_t MODE; + uint8_t RESOURCE; +} eXcpCommand_REQ_GET_SEED; + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + uint8_t LEN; + uint32_t KEY; +} eXcpCommand_GET_SEED; + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + uint8_t LEN; + uint32_t KEY; +} eXcpCommand_REQ_UNLOCK; + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + uint16_t RESERVED; + uint8_t ADR_EX; + uint32_t ADR; +} eXcpCommand_SET_MTA; + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + uint8_t COUNT; +} eXcpCommand_Download; + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + uint16_t DAQ_LIST_NUMBER; +} eXcpCommand_Get_DAQ_List_Info_Request; + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + uint8_t RESERVED; + uint16_t DAQ_LIST_NUMBER; + uint8_t ODT_NUMBER; + uint8_t ODT_ENTRY_NUMBER; +} eXcpCommand_SET_DAQ_PTR; + +#define LOG_XCP 0 + +#define PROTECT_CAL_PAG 0 +#define PROTECT_DAQ 0 +#define PROTECT_STIM 0 +#define PROTECT_PGM 0 + +#define SECT_SRAM_XCP __attribute__((section (".xcpdata"))) + +#define MASTER_BLOCK_MODE 0 +#define SLAVE_BLOCK_MODE 0 + +#define PROGRAM_MASTER_BLOCK_MODE 1 +#define PROGRAM_MAX_SECTOR 8 +#define PROGRAM_MAX_BUF 256 + +#define MAX_CTO 8 +#define MAX_DTO 8 + +#define BODY_MAX_LEN (MAX_DTO - 2) + +#define MAX_DAO 10 +#define MAX_ODT 255 +#define MAX_ODT_ENTRIES_SIZE_DAQ 1 +#define MAX_EVENT_CHANNEL 4 + +typedef struct { + uint8_t DATA[BODY_MAX_LEN]; +} tXCP_DATA_STIM; + +typedef struct { + uint8_t ODT_ENTRIES_COUNT; + + uint8_t DATA_STM_COUNTER; + tXCP_DATA_STIM DATA_STM[MAX_ODT_ENTRIES_SIZE_DAQ]; + + uint8_t BIT_OFFSET[MAX_ODT_ENTRIES_SIZE_DAQ]; + uint8_t ADR_EXT[MAX_ODT_ENTRIES_SIZE_DAQ]; + uint8_t ODT_ENTRIES_SIZE[MAX_ODT_ENTRIES_SIZE_DAQ]; + uint32_t ODT_ENTRIES_ADR[MAX_ODT_ENTRIES_SIZE_DAQ]; +} tXCP_ODT_ENTRIES; + +//typedef struct { +// uint8_t ALTERNATING; +// uint8_t DIRECTION; +// uint8_t DTO_CTR; +// uint8_t TIMESTAMP; +// uint8_t PID_OFF; +// uint8_t TRANSMISSION_RATE_PRESCALER; +// uint8_t DAQ_LIST_PRIORITY; + +// uint8_t COUNTER; + +//} tXCP_EVENT_CHANNEL; + +typedef struct { + uint8_t SELECTED; + uint8_t RUNNING; + uint8_t ODT_COUNT; + uint16_t EVENT_CHANNEL; + + uint8_t ALTERNATING; + uint8_t DIRECTION; + uint8_t DTO_CTR; + uint8_t TIMESTAMP; + uint8_t PID_OFF; + uint8_t TRANSMISSION_RATE_PRESCALER; + uint8_t DAQ_LIST_PRIORITY; + + uint8_t PRESCALER_COUNTER; + + uint8_t IS_STIM_RECEIVED; + tXCP_ODT_ENTRIES ODT_NUMBER[MAX_ODT]; +} tXCP_DAQ; + + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + + uint8_t PREDEFINED: 1; + uint8_t EVENT_FIXED: 1; + uint8_t DAQ: 1; + uint8_t STIM: 1; + uint8_t RESERVER: 4; + + uint8_t MAX_ODT_; + uint8_t MAX_ODT_ENTRIES_; + uint16_t FIXED_EVENT; + +} eXcpCommand_Get_DAQ_List_Info; + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + uint8_t RESERVED; + uint16_t DAQ_LIST_NUMBER; + uint8_t ODT_NUMBER; + uint8_t ODT_ENTRIES_COUNT; +} eXcpCommand_DAQ_Alloc_ODR_Entry; + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + uint8_t BIT_OFFSET; + uint8_t ODT_ENTRY_SIZE; + uint8_t ADR_EXT; + uint32_t ADR; +} eXcpCommand_WRITE_DAQ; + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + + uint8_t ALTERNATING: 1; + uint8_t DIRECTION: 1; + uint8_t RESERVED1: 1; + uint8_t DTO_CTR: 1; + uint8_t TIMESTAMP: 1; + uint8_t PID_OFF: 1; + uint8_t RESERVED2: 1; + uint8_t RESERVED3: 1; + + uint16_t DAQ_LIST_NUMBER; + uint16_t EVENT_CHANNEL_NUMBER; + uint8_t TRANSMISSION_RATE_PRESCALER; + uint8_t DAQ_LIST_PRIORITY; +} eXcpCommand_SET_DAQ_LIST_MODE; + + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + eXcpDAQ_Mode MODE; + uint16_t DAQ_LIST_NUMBER; +} eXcpCommand_START_STOP_DAQ_LIST; + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + eXcpDAQ_Sync_Mode MODE; +} eXcpCommand_START_STOP_SYNCH; + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + uint8_t RESERVED; + uint16_t DAQ_COUNT; +} eXcpCommand_ALLOC_DAQ; + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + uint8_t RESERVED; + uint16_t DAQ_LIST_NUMBER; + uint8_t ODT_COUNT; +} eXcpCommand_ALLOC_ODT; + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + uint8_t RESERVED; + uint16_t DAQ_LIST_NUMBER; + uint8_t ODT_NUMBER; + uint8_t ODT_ENTRIES_COUNT; +} eXcpCommand_ALLOC_ODT_ENTRY; + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + + uint8_t DAQ_CONFIG_TYPE: 1; + uint8_t PRESCALER_SUPPORTED: 1; + uint8_t RESUME_SUPPORTED: 1; + uint8_t BIT_STIM_SUPPORTED: 1; + uint8_t TIMESTAMP_SUPPORTED: 1; + uint8_t PID_OFF_SUPPORTED: 1; + uint8_t OVERLOAD_MSB: 1; + uint8_t OVERLOAD_EVENT: 1; + + uint16_t MAX_DAQ; + uint16_t MAX_EVENT_CHANNEL_; + uint8_t MIN_DAQ; + + uint8_t Optimisation_Type_0: 1; + uint8_t Optimisation_Type_1: 1; + uint8_t Optimisation_Type_2: 1; + uint8_t Optimisation_Type_3: 1; + uint8_t Address_Extension_ODT: 1; + uint8_t Address_Extension_DAQ: 1; + uint8_t Identification_Field_Type_0: 1; + uint8_t Identification_Field_Type_1: 1; + +} eXcpCommand_GET_DAQ_PROCESSOR_INFO; + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + uint8_t GRANULARITY_ODT_ENTRY_SIZE_DAQ; + uint8_t MAX_ODT_ENTRY_SIZE_DAQ; + uint8_t GRANULARITY_ODT_ENTRY_SIZE_STIM; + uint8_t MAX_ODT_ENTRY_SIZE_STIM; + uint8_t TIMESTAMP_MODE; + uint16_t TIMESTAMP_TICKS; +} eXcpCommand_GET_DAQ_RESOLUTION_INFO; + + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + uint8_t RESERVED; + uint16_t DAQ_LIST_NUMBER; +} eXcpCommand_GET_DAQ_LIST_MODE_GET; + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + + uint8_t SELECTED: 1; + uint8_t DIRECTION: 1; + uint8_t RESERVED1: 1; + uint8_t DTO_CTR: 1; + uint8_t TIMESTAMP: 1; + uint8_t PID_OFF: 1; + uint8_t RUNNING: 1; + uint8_t RESUME: 1; + + uint16_t RESERVED2; + uint16_t CURRENT_EVENT_CHANNEL_NUMBER; + uint8_t CURRENT_PRESCALER; + uint8_t CURRENT_DAQ_LIST_PRIORITY; + +} eXcpCommand_GET_DAQ_LIST_MODE; + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + uint8_t RESERVED; + uint16_t EVENT_CHANNEL_NUMBER; +} eXcpCommand_GET_DAQ_EVENT_INFO_GET; + +typedef struct __attribute__ ((packed)) { + uint8_t ODT; + uint8_t DAQ; +} eXcpCommand_GET_DAQ_STM; + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + + uint8_t RESERVED1: 1; + uint8_t RESERVED2: 1; + uint8_t DAQ: 1; + uint8_t STM: 1; + uint8_t RESERVED3: 1; + uint8_t RESERVED4: 1; + uint8_t CONSISTENCY_DAQ: 1; + uint8_t CONSISTENCY_EVENT: 1; + + uint8_t MAX_DAQ_LIST; + uint8_t EVENT_CHANNEL_NAME_LENGTH; + uint8_t EVENT_CHANNEL_TIME_CYCLE; + uint8_t EVENT_CHANNEL_TIME_UNIT; + uint8_t EVENT_CHANNEL_PRIORITY; + +} eXcpCommand_GET_DAQ_EVENT_INFO; + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + uint8_t RESERVED1; + + uint8_t _MASTER_BLOCK_MODE: 1; + uint8_t INTERLEAVED_MODE: 1; + uint8_t RESERVED2: 1; + uint8_t RESERVED3: 1; + uint8_t RESERVED4: 1; + uint8_t RESERVED5: 1; + uint8_t _SLAVE_BLOCK_MODE: 1; + uint8_t RESERVED6: 1; + + uint8_t MAX_CTO_PGM; + uint8_t MAX_BS_PGM; + uint8_t MIN_ST_PGM; + uint8_t QUEUE_SIZE_PGM; +} eXcpCommand_PROGRAM_START; + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + uint8_t MODE; + uint16_t RESERVED; + uint32_t CLEAR_RANGE; +} eXcpCommand_XCP_PROGRAM_CLEAR_D1; + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + uint8_t COUNT; +} eXcpCommand_Program_ProgramNext_D0_CA; + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + uint8_t RESERVED; + uint16_t CODESIZE; +} eXcpCommand_Program_Prepare_CC; + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + uint8_t COMPRESSION_METHOD; + uint8_t ENCRYPTION_METHOD; + uint8_t PROGRAM_METHOD; + uint8_t ACCESS_METHOD; +} eXcpCommand_Program_Format_CB; + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + + uint8_t ABSOLUTE_MODE: 1; + uint8_t FUNCTIONAL_MODE: 1; + uint8_t COMPRESSION_SUPPORTED: 1; + uint8_t COMPRESSION_REQUIRED: 1; + uint8_t ENCRYPTION_SUPPORTED: 1; + uint8_t ENCRYPTION_REQUIRED: 1; + uint8_t NON_SEQ_PGM_SUPPORTED: 1; + uint8_t NON_SEQ_PGM_REQUIRED: 1; + + uint8_t MAX_SECTOR; + +} eXcpCommand_PGM_PROCESSOR_INFO_CE; + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + uint8_t MODE; + uint8_t SECTOR_NUMBER; +} eXcpCommand_REQ_GET_SECTOR_INFO_CD; + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + uint8_t CLEAR_SEQUENCE_NUMBER; + uint8_t PROGRAM_SEQUENCE_NUMBER; + + uint8_t ABSOLUTE_MODE: 1; + uint8_t FUNCTIONAL_MODE: 1; + uint8_t PAGED_MODE: 1; + uint8_t SEQUENTIAL_ONLY: 1; + uint8_t ERASE_BEFORE_WRITE: 1; + uint8_t VERIFY_AFTER_WRITE: 1; + uint8_t RESERVED1: 1; + uint8_t RESERVED2: 1; + + uint32_t SECTOR_INFO; +} eXcpCommand_RESP_GET_SECTOR_INFO_CD; + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + + uint8_t ECU: 1; + uint8_t XCP: 1; + uint8_t RESERVED1: 1; + uint8_t RESERVED2: 1; + uint8_t RESERVED3: 1; + uint8_t RESERVED4: 1; + uint8_t RESERVED5: 1; + uint8_t ALL: 1; + + uint8_t SEGMENT; + uint8_t PAGE; + +} eXcpCommand_SET_CALIBRATION_PAGE_EB; + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + uint8_t VERIFICATION_MODE; + uint16_t VERIFICATION_TYPE; + uint32_t VERIFICATION_VALUE; +} eXcpCommand_Program_Verify_C8; + +typedef struct __attribute__ ((packed)) { + eXcpTypeCommand COM; + uint8_t ACCESS_MODE; + uint8_t LOGICAL_DATA_SEGMENT_NUMBER; +} eXcpCommand_XCP_GET_CAL_PAGE_EA; + + +typedef bool (xcp_clear_flash_func)(uint32_t firstPageAddr, uint32_t totalSize, void *wdTriggerFct, +void *wdTriggerFct_env); + +typedef bool (xcp_write_flash_func)(uint32_t beginPageAddr, void *sourceRamAddr, uint32_t size); + + +typedef struct { + tSerialPortFrameIO *ioCanFrame; + tLoggerInterface *logger; + tVarsTabDumpObserver *varsTabDumpObserver; + + eTypeProtect RESOURCE; + uint8_t ADR_EXT; + uint32_t ADR_MTA; + uint8_t PAGE_ID; + + bool PROTECT[4]; + + can_rx_message_type canFrame; + uint8_t downloadRemaining; + uint8_t response[8]; + + uint8_t DATA[MAX_ODT_ENTRIES_SIZE_DAQ * BODY_MAX_LEN]; + + //tXCP_DAQ DAQ[MAX_DAO]; + + struct { + uint8_t STORE_CAL_REQ; // ожидает сохранения в энергонезависимую память + uint8_t STORE_DAQ_REQ; // требуется сохранить DAQ-листы + uint8_t CLEAR_DAQ_REQ; // требуется очистить все DAQ-листы + uint8_t DAQ_RUNNING; // минимум один DAQ-лист запущен и работает + uint8_t RESUME; // устройство в режиме RESUME + } STATE; + + struct { + uint16_t DAQ_LIST_NUMBER; + uint8_t ODT_NUMBER; + uint8_t ODT_ENTRY_NUMBER; + uint16_t DAQ_COUNT; + } SETUP; + + tXCP_DAQ *DAQ; + + + tRtcIO *rtcIO; + + osMutexId_t access; + + uint32_t startRamAdr; + uint32_t endRamAdr; + + uint32_t startFlashAdr; + uint32_t endFlashAdr; + xcp_clear_flash_func *clear_flash_func; + + xcp_write_flash_func *write_flash_func; + + uint8_t bufWriteFlash[PROGRAM_MAX_BUF]; + uint16_t bufWriteFlashCount; + uint32_t bufWriteFlashAdr; + + struct { + osThreadId_t id; + uint32_t stack[384]; + StaticTask_t controlBlock; + osThreadAttr_t attr; + } thread_Listener_XCP; + +// tStaticThreadBlock(384) T_can_Listener_XCP; +// tStaticThreadBlock(512) T_can_Listener_Dto_Stim_XCP; +// tStaticThreadBlock(512) T_can_Listener_Dto_Daq_10_XCP; +// tStaticThreadBlock(512) T_can_Listener_Dto_Daq_100_XCP; +// tStaticThreadBlock(512) T_can_Listener_Dto_Daq_1000_XCP; + +} tCanSerialPortFrameXCP; + + +typedef uint8_t (*xcp_func_ptr)(tCanSerialPortFrameXCP *env); + +typedef struct { + xcp_func_ptr func; + char *desc; +} eXcp_com; + +void CanSerialPortFrameXcpInit( + tCanSerialPortFrameXCP *env, + tSerialPortFrameIO *ioCanFrame, + tRtcIO *rtcIO, + uint32_t startRamAddr, + uint32_t endRamAdr, + uint32_t startFlashAdr, + uint32_t endFlashAdr, + xcp_clear_flash_func *clear_flash_func, + xcp_write_flash_func *write_flash_func, + tVarsTabDumpObserver *varsTabDumpObserver, + tLoggerInterface *logger +); + +void CanXcpProcessing_Listener_Start(tCanSerialPortFrameXCP *env); + +#endif //CAN_MODULE_CAN_FRAME_XCP_H diff --git a/MODULES/CanSerialPortFrame_XCP/Src/CanSerialPortFrameXCP.c b/MODULES/CanSerialPortFrame_XCP/Src/CanSerialPortFrameXCP.c new file mode 100644 index 0000000..fea907a --- /dev/null +++ b/MODULES/CanSerialPortFrame_XCP/Src/CanSerialPortFrameXCP.c @@ -0,0 +1,1915 @@ +// +// Created by cfif on 16.03.2024. +// +#include +#include "CanSerialPortFrameXCP.h" +#include "memory.h" +#include "AsciiStringAssmeblingUtils.h" +#include "SystemMutexCmsis.h" +#include "CanPorts.h" +#include + +#define LOG_SIGN "CAN_XCP" +#define LOGGER env->logger + +SECT_SRAM_XCP tXCP_DAQ DAQ[MAX_DAO]; + +static char strPrintfDebug_XCP[80]; + +static void PrintfDebug(uint8_t *data, uint8_t dlc) { + + switch (dlc) { + + case 0: + sprintf(strPrintfDebug_XCP, " "); + break; + case 1: + sprintf(strPrintfDebug_XCP, "0x%02X", data[0]); + break; + case 2: + sprintf(strPrintfDebug_XCP, "0x%02X:0x%02X", data[0], data[1]); + break; + case 3: + sprintf(strPrintfDebug_XCP, "0x%02X:0x%02X:0x%02X", data[0], data[1], data[2]); + break; + case 4: + sprintf(strPrintfDebug_XCP, "0x%02X:0x%02X:0x%02X:0x%02X", data[0], data[1], data[2], data[3]); + break; + case 5: + sprintf(strPrintfDebug_XCP, "0x%02X:0x%02X:0x%02X:0x%02X:0x%02X", data[0], data[1], data[2], data[3], + data[4]); + break; + case 6: + sprintf(strPrintfDebug_XCP, "0x%02X:0x%02X:0x%02X:0x%02X:0x%02X:0x%02X", data[0], data[1], data[2], data[3], + data[4], data[5]); + break; + case 7: + sprintf(strPrintfDebug_XCP, "0x%02X:0x%02X:0x%02X:0x%02X:0x%02X:0x%02X:0x%02X", data[0], data[1], data[2], + data[3], data[4], + data[5], data[6]); + break; + case 8: + sprintf(strPrintfDebug_XCP, "0x%02X:0x%02X:0x%02X:0x%02X:0x%02X:0x%02X:0x%02X:0x%02X", data[0], data[1], + data[2], data[3], data[4], + data[5], data[6], data[7]); + break; + default: + sprintf(strPrintfDebug_XCP, " "); + } + +} + +static bool isUNLOCK(tCanSerialPortFrameXCP *env, eTypeProtect RESOURCE) { + + if ((RESOURCE == XCP_PROTECT_CAL_PAG) && (env->PROTECT[0])) { + return true; + } + + if ((RESOURCE == XCP_PROTECT_DAQ) && (env->PROTECT[1])) { + return true; + } + + if ((RESOURCE == XCP_PROTECT_STM) && (env->PROTECT[2])) { + return true; + } + + if ((RESOURCE == XCP_PROTECT_PGM) && (env->PROTECT[3])) { + return true; + } + + return false; +} + +/* +static unsigned long SeedToKeyHVAC_NAMI(unsigned char rnd, unsigned long dwSeedInfo) { +#define Mask 0x55F388A6UL + + unsigned char i; + unsigned long key = dwSeedInfo; + + rnd += 35; + if (rnd < 35) rnd = 255; + + for (i = 0; i < rnd; i++) { + if (key & 0x80000000UL) + key = (key << 1) ^ Mask; + else + key <<= 1; + } + + return key; +} +*/ +extern uint32_t generate_key(uint32_t seed); + +void CanSerialPortFrameXcpInit( + tCanSerialPortFrameXCP *env, + tSerialPortFrameIO *ioCanFrame, + tRtcIO *rtcIO, + uint32_t startRamAdr, + uint32_t endRamAdr, + uint32_t startFlashAdr, + uint32_t endFlashAdr, + xcp_clear_flash_func *clear_flash_func, + xcp_write_flash_func *write_flash_func, + tVarsTabDumpObserver *varsTabDumpObserver, + tLoggerInterface *logger +) { + env->DAQ = DAQ; + + env->varsTabDumpObserver = varsTabDumpObserver; + + env->ioCanFrame = ioCanFrame; + + env->rtcIO = rtcIO; + env->logger = logger; + + env->startRamAdr = startRamAdr; + env->endRamAdr = endRamAdr; + + env->startFlashAdr = startFlashAdr; + env->endFlashAdr = endFlashAdr; + env->clear_flash_func = clear_flash_func; + env->write_flash_func = write_flash_func; + + env->access = osMutexNew(NULL); + +// InitThreadBlock(env->T_can_Listener_XCP, "CanListenerXCP", osPriorityNormal); + InitThreadAtrStatic(&env->thread_Listener_XCP.attr, "CanListenerXCP", env->thread_Listener_XCP.controlBlock, env->thread_Listener_XCP.stack, + osPriorityNormal); +} + +static void FREE_DAQ(tCanSerialPortFrameXCP *env) { + memset(&env->STATE, 0, sizeof(env->STATE)); + memset(&env->SETUP, 0, sizeof(env->SETUP)); + memset(env->DAQ, 0, sizeof(DAQ)); +} + +static uint8_t XCP_COMMAND_CONNECT_FF(tCanSerialPortFrameXCP *env) { + + FREE_DAQ(env); + + eXcpCommand_CONNECT *xcpCommand_CONNECT = (eXcpCommand_CONNECT *) env->response; + + xcpCommand_CONNECT->COM = XCP_COMMAND_CONNECT; + + xcpCommand_CONNECT->CAL_PAG = 1; // Калибровка и пагинация + xcpCommand_CONNECT->reserve1 = 0; + xcpCommand_CONNECT->DAQ = 1; // Поддержка DAQ + xcpCommand_CONNECT->STIM = 1; // Стимуляция (формирование инициативных запросов) + xcpCommand_CONNECT->PGM = 1; // Программирование FLASH + xcpCommand_CONNECT->reserve2 = 0; + xcpCommand_CONNECT->reserve3 = 0; + xcpCommand_CONNECT->reserve4 = 0; + + xcpCommand_CONNECT->BYTE__ORDER = 0; // 0 - Intel 1 - Motorola + xcpCommand_CONNECT->ADDRESS_GRANULARITY_0 = 0; + xcpCommand_CONNECT->ADDRESS_GRANULARITY_1 = 0; + xcpCommand_CONNECT->reserve5 = 0; + xcpCommand_CONNECT->reserve6 = 0; + xcpCommand_CONNECT->reserve7 = 0; + xcpCommand_CONNECT->_SLAVE_BLOCK_MODE = SLAVE_BLOCK_MODE; // Блочный режим не поддерживается + xcpCommand_CONNECT->OPTIONAL = 1; // Поддержка команды XCP_COMMAND_GET_STATUS + + xcpCommand_CONNECT->MAX_CTO_ = MAX_CTO; + xcpCommand_CONNECT->MAX_DTO_ = MAX_DTO; + + xcpCommand_CONNECT->XCP_PROTOCOL_VER = 1; + xcpCommand_CONNECT->XCP_TRANSPORT_VER = 1; + + return 8; +} + +static uint8_t XCP_COMMAND_DISCONNECT_FE(tCanSerialPortFrameXCP *env) { + + FREE_DAQ(env); + + env->response[0] = XCP_COMMAND_CONNECT; + + return 1; +} + +static void update_STATE(tCanSerialPortFrameXCP *env) { + + env->STATE.STORE_CAL_REQ = 0; // ожидает сохранения в энергонезависимую память + env->STATE.STORE_DAQ_REQ = 0; // требуется сохранить DAQ-листы (не загрузить, а сохранить) + env->STATE.CLEAR_DAQ_REQ = 0; // требуется очистить все DAQ-листы + + env->STATE.DAQ_RUNNING = 0; // минимум один DAQ-лист запущен и работает + + for (uint16 i = 0; i < env->SETUP.DAQ_COUNT; ++i) { + if (env->DAQ[i].RUNNING) { + env->STATE.DAQ_RUNNING = 1; // минимум один DAQ-лист запущен и работает + break; + } + } + + env->STATE.RESUME = 0; // устройство в режиме RESUME +} + +static uint8_t XCP_COMMAND_GET_STATUS_FD(tCanSerialPortFrameXCP *env) { + + update_STATE(env); + + eXcpCommand_GET_STATUS *xcpCommand_GET_STATUS = (eXcpCommand_GET_STATUS *) env->response; + + xcpCommand_GET_STATUS->COM = XCP_COMMAND_CONNECT; + + // Статус состояний + xcpCommand_GET_STATUS->STORE_CAL_REQ = env->STATE.STORE_CAL_REQ; + xcpCommand_GET_STATUS->reserve1 = 0; + xcpCommand_GET_STATUS->STORE_DAQ_REQ = env->STATE.STORE_DAQ_REQ; + xcpCommand_GET_STATUS->CLEAR_DAQ_REQ = env->STATE.CLEAR_DAQ_REQ; + xcpCommand_GET_STATUS->reserve2 = 0; + xcpCommand_GET_STATUS->reserve3 = 0; + xcpCommand_GET_STATUS->DAQ_RUNNING = env->STATE.DAQ_RUNNING; + xcpCommand_GET_STATUS->RESUME = env->STATE.RESUME; // устройство не в режиме RESUME + + // Статус защиты ресурсов + xcpCommand_GET_STATUS->CAL_PAG = PROTECT_CAL_PAG; // защита команд калибровки/пагинации + xcpCommand_GET_STATUS->reserve5 = 0; + xcpCommand_GET_STATUS->DAQ = PROTECT_DAQ; // защита DAQ-команд + xcpCommand_GET_STATUS->STIM = PROTECT_STIM; // защита STIM-команд + xcpCommand_GET_STATUS->PGM = PROTECT_PGM; // защита команд программирования + xcpCommand_GET_STATUS->reserve6 = 0; + xcpCommand_GET_STATUS->reserve7 = 0; + xcpCommand_GET_STATUS->reserve8 = 0; + + xcpCommand_GET_STATUS->STATE_NUMBER = 2; // номер состояния ECU + + xcpCommand_GET_STATUS->SESSION_CONFIGURATION_ID = 0; // ID конфигурации сессии + + return 6; +} + +static uint8_t XCP_COMMAND_SYNCH_FC(tCanSerialPortFrameXCP *env) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_CMD_SYNCH; + + return 2; +} + +static uint8_t XCP_GET_COMM_MODE_INFO_FB(tCanSerialPortFrameXCP *env) { + + eXcpCommand_GET_COMM_MODE_INFO *xcpCommand_GET_COMM_MODE_INFO = (eXcpCommand_GET_COMM_MODE_INFO *) env->response; + + xcpCommand_GET_COMM_MODE_INFO->RESERVED1 = 0; + + xcpCommand_GET_COMM_MODE_INFO->_MASTER_BLOCK_MODE = MASTER_BLOCK_MODE; + xcpCommand_GET_COMM_MODE_INFO->INTERLEAVED_MODE = 0; + xcpCommand_GET_COMM_MODE_INFO->RESERVED2 = 0; + + xcpCommand_GET_COMM_MODE_INFO->RESERVED3 = 0; + xcpCommand_GET_COMM_MODE_INFO->MAX_BS = 255; + xcpCommand_GET_COMM_MODE_INFO->MIN_ST = 0; + xcpCommand_GET_COMM_MODE_INFO->QUEUE_SIZE = 0; + xcpCommand_GET_COMM_MODE_INFO->VERSION = 1; + + return 8; +} + +static uint8_t XCP_GET_SEED_F8(tCanSerialPortFrameXCP *env) { + eXcpCommand_REQ_GET_SEED *request = (eXcpCommand_REQ_GET_SEED *) env->canFrame.data; + + eXcpCommand_GET_SEED *xcpCommand_GET_SEED = (eXcpCommand_GET_SEED *) env->response; + xcpCommand_GET_SEED->COM = XCP_COMMAND_CONNECT; + xcpCommand_GET_SEED->LEN = 4; + xcpCommand_GET_SEED->KEY = 0x853A08FB; + env->RESOURCE = request->RESOURCE; + + return 6; +} + +static uint8_t XCP_UNLOCK_F7(tCanSerialPortFrameXCP *env) { + eXcpCommand_REQ_UNLOCK *request = (eXcpCommand_REQ_UNLOCK *) env->canFrame.data; + + uint32_t securitySeedMy = generate_key(0x853A08FB);//SeedToKeyHVAC_NAMI(0, 0x11223344); + + if (securitySeedMy != request->KEY) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_ACCESS_LOCKED; + + if (env->RESOURCE == XCP_PROTECT_CAL_PAG) { + env->PROTECT[0] = false; + } + + if (env->RESOURCE == XCP_PROTECT_DAQ) { + env->PROTECT[1] = false; + } + + if (env->RESOURCE == XCP_PROTECT_STM) { + env->PROTECT[2] = false; + } + + if (env->RESOURCE == XCP_PROTECT_PGM) { + env->PROTECT[3] = false; + } + + + } else { + env->response[0] = XCP_COMMAND_CONNECT; + env->response[1] = 0; + + if (env->RESOURCE == XCP_PROTECT_CAL_PAG) { + env->PROTECT[0] = true; + } + + if (env->RESOURCE == XCP_PROTECT_DAQ) { + env->PROTECT[1] = true; + } + + if (env->RESOURCE == XCP_PROTECT_STM) { + env->PROTECT[2] = true; + } + + if (env->RESOURCE == XCP_PROTECT_PGM) { + env->PROTECT[3] = true; + } + + } + + return 2; +} + +static uint8_t XCP_COMMAND_SET_MTA_F6(tCanSerialPortFrameXCP *env) { + eXcpCommand_SET_MTA *request = (eXcpCommand_SET_MTA *) env->canFrame.data; + + + if (((request->ADR < env->startRamAdr) || (request->ADR > env->endRamAdr)) && + ((request->ADR < env->startFlashAdr) || (request->ADR > env->endFlashAdr))) { + + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_ACCESS_DENIED; + + + env->bufWriteFlashCount = 0; + + return 2; + } + + env->ADR_EXT = request->ADR_EX; + env->ADR_MTA = request->ADR; + + env->response[0] = XCP_COMMAND_CONNECT; + env->bufWriteFlashAdr = env->ADR_MTA; + + return 1; +} + +static uint8_t XCP_COMMAND_UPLOAD_F5(tCanSerialPortFrameXCP *env) { + eXcpCommand_Upload *request = (eXcpCommand_Upload *) env->canFrame.data; + + env->response[0] = XCP_COMMAND_CONNECT; + + + if (SLAVE_BLOCK_MODE) { + + if (request->COUNT == 0) { + +#if (LOG_XCP == 1) + PrintfDebug(env->response, 1); + LoggerFormatInfo(LOGGER, LOG_SIGN, "< [%d] %s", 1, strPrintfDebug_XCP) +#endif + env->ioCanFrame->transmit(env->ioCanFrame->env, env->response, 1, PROTOCOL_CAN_ADR_XCP, + PROTOCOL_CAN_TYPE_XCP, + 100); + + return 0; + } + + + uint8_t fullBlock = request->COUNT / 7; + uint8_t tailBlock = request->COUNT % 7; + + for (uint8_t i = 0; i < fullBlock; ++i) { + memcpy(&env->response[1], (uint8_t * )(env->ADR_MTA), request->COUNT); + env->ADR_MTA += 7; +#if (LOG_XCP == 1) + PrintfDebug(env->response, 7 + 1); + LoggerFormatInfo(LOGGER, LOG_SIGN, "< [%d] %s", 7 + 1, strPrintfDebug_XCP) +#endif + env->ioCanFrame->transmit(env->ioCanFrame->env, env->response, 7 + 1, PROTOCOL_CAN_ADR_XCP, + PROTOCOL_CAN_TYPE_XCP, + 100); + } + + if (tailBlock > 0) { + memcpy(&env->response[1], (uint8_t * )(env->ADR_MTA), tailBlock); + env->ADR_MTA += tailBlock; + +#if (LOG_XCP == 1) + PrintfDebug(env->response, tailBlock + 1); + LoggerFormatInfo(LOGGER, LOG_SIGN, "< [%d] %s", tailBlock + 1, strPrintfDebug_XCP) +#endif + env->ioCanFrame->transmit(env->ioCanFrame->env, env->response, tailBlock + 1, PROTOCOL_CAN_ADR_XCP, + PROTOCOL_CAN_TYPE_XCP, 100); + } + + return 0; + } else { + memcpy(&env->response[1], (uint8_t * )(env->ADR_MTA), request->COUNT); + env->ADR_MTA += request->COUNT; + return request->COUNT + 1; + } +} + +static uint8_t XCP_COMMAND_SHORT_UPLOAD_F4(tCanSerialPortFrameXCP *env) { + eXcpCommand_SHORT_UPLOAD *request = (eXcpCommand_SHORT_UPLOAD *) env->canFrame.data; + + if (request->COUNT > (MAX_CTO - 1)) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_OUT_OF_RANGE; + + return 2; + } + + + env->response[0] = XCP_COMMAND_CONNECT; + + memcpy(&env->response[1], (uint8_t *) request->ADR, request->COUNT); + + return request->COUNT + 1; +} + +static uint8_t XCP_COMMAND_DOWNLOAD_F0(tCanSerialPortFrameXCP *env) { + + eXcpCommand_Download *request = (eXcpCommand_Download *) env->canFrame.data; + +#if (PROTECT_CAL_PAG == 1) + if (isUNLOCK(env, XCP_PROTECT_CAL_PAG) == false) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_ACCESS_LOCKED; + + return 2; + } +#endif + +// uint8_t COUNT = env->canFrame.dlc - 2; + uint8_t COUNT; + if (request->COUNT <= 6) { + COUNT = request->COUNT; + } else { + COUNT = 6; + } + + +// memcpy((uint8_t *) (env->ADR_MTA), &env->response[2], COUNT); + memcpy((uint8_t * )(env->ADR_MTA), &env->canFrame.data[2], COUNT); + env->ADR_MTA += COUNT; + + env->downloadRemaining = request->COUNT - COUNT; + + if (request->COUNT <= 6) { + env->response[0] = XCP_COMMAND_CONNECT; + return 1; + } else { + return 0; + } +} + +static uint8_t XCP_COMMAND_DOWNLOAD_NEXT_EF(tCanSerialPortFrameXCP *env) { + + eXcpCommand_Download *request = (eXcpCommand_Download *) env->canFrame.data; + +#if (PROTECT_CAL_PAG == 1) + if (isUNLOCK(env, XCP_PROTECT_CAL_PAG) == false) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_ACCESS_LOCKED; + + return 2; + } +#endif + + //uint8_t COUNT = env->canFrame.dlc - 2; + uint8_t COUNT = request->COUNT; + + memcpy((uint8_t * )(env->ADR_MTA), &env->canFrame.data[2], COUNT); + env->ADR_MTA += COUNT; + + if (request->COUNT > env->downloadRemaining) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_SEQUENCE; + env->response[2] = env->downloadRemaining; + + return 3; + } + + env->downloadRemaining -= COUNT; + + if (env->downloadRemaining == 0) { + env->response[0] = XCP_COMMAND_CONNECT; + return 1; + } + + return 0; +} + +static uint8_t XCP_COMMAND_DOWNLOAD_MAX_EE(tCanSerialPortFrameXCP *env) { + +#if (PROTECT_CAL_PAG == 1) + if (isUNLOCK(env, XCP_PROTECT_CAL_PAG) == false) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_ACCESS_LOCKED; + + return 2; + } +#endif + + uint8_t COUNT = env->canFrame.dlc - 1; + + memcpy((uint8_t * )(env->ADR_MTA), &env->response[1], COUNT); + env->ADR_MTA += COUNT; + + env->response[0] = XCP_COMMAND_CONNECT; + + return 1; +} + + +static uint8_t XCP_CLEAR_DAQ_LIST_E3(tCanSerialPortFrameXCP *env) { + +#if (PROTECT_DAQ == 1) + if (isUNLOCK(env, XCP_PROTECT_DAQ) == false) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_ACCESS_LOCKED; + + return 2; + } +#endif + + env->response[0] = XCP_COMMAND_CONNECT; + + return 1; +} + + +static uint8_t XCP_GET_DAQ_LIST_INFO_D8(tCanSerialPortFrameXCP *env) { + eXcpCommand_Get_DAQ_List_Info_Request *request = (eXcpCommand_Get_DAQ_List_Info_Request *) env->canFrame.data; + +#if (PROTECT_DAQ == 1) + if (isUNLOCK(env, XCP_PROTECT_DAQ) == false) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_ACCESS_LOCKED; + + return 2; + } +#endif + + + if (request->DAQ_LIST_NUMBER > MAX_DAO) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_OUT_OF_RANGE; + + return 2; + } + + eXcpCommand_Get_DAQ_List_Info *xcpCommand_Get_DAQ_List_Info = (eXcpCommand_Get_DAQ_List_Info *) env->response; + + xcpCommand_Get_DAQ_List_Info->COM = XCP_COMMAND_CONNECT; + + xcpCommand_Get_DAQ_List_Info->PREDEFINED = 0; + xcpCommand_Get_DAQ_List_Info->EVENT_FIXED = 0; + xcpCommand_Get_DAQ_List_Info->DAQ = 1; + xcpCommand_Get_DAQ_List_Info->STIM = 1; + xcpCommand_Get_DAQ_List_Info->RESERVER = 0; + + xcpCommand_Get_DAQ_List_Info->MAX_ODT_ = MAX_ODT; + xcpCommand_Get_DAQ_List_Info->MAX_ODT_ENTRIES_ = MAX_ODT_ENTRIES_SIZE_DAQ; + xcpCommand_Get_DAQ_List_Info->FIXED_EVENT = 0; + + return 6; +} + +static uint8_t XCP_ALLOC_DAQ_D5(tCanSerialPortFrameXCP *env) { + eXcpCommand_ALLOC_DAQ *request = (eXcpCommand_ALLOC_DAQ *) env->canFrame.data; + +#if (PROTECT_DAQ == 1) + if (isUNLOCK(env, XCP_PROTECT_DAQ) == false) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_ACCESS_LOCKED; + + return 2; + } +#endif + + + env->SETUP.DAQ_COUNT = request->DAQ_COUNT; + + env->response[0] = XCP_COMMAND_CONNECT; + return 1; +} + +static uint8_t XCP_FREE_DAQ_D6(tCanSerialPortFrameXCP *env) { + +#if (PROTECT_DAQ == 1) + if (isUNLOCK(env, XCP_PROTECT_DAQ) == false) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_ACCESS_LOCKED; + + return 2; + } +#endif + + + FREE_DAQ(env); + + env->response[0] = XCP_COMMAND_CONNECT; + return 1; +} + +static uint8_t XCP_ALLOC_ODT_D4(tCanSerialPortFrameXCP *env) { + eXcpCommand_ALLOC_ODT *request = (eXcpCommand_ALLOC_ODT *) env->canFrame.data; + +#if (PROTECT_DAQ == 1) + if (isUNLOCK(env, XCP_PROTECT_DAQ) == false) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_ACCESS_LOCKED; + + return 2; + } +#endif + + + env->DAQ[request->DAQ_LIST_NUMBER].ODT_COUNT = request->ODT_COUNT; + + env->response[0] = XCP_COMMAND_CONNECT; + return 1; +} + + +static uint8_t XCP_ALLOC_ODT_ENTRY_D3(tCanSerialPortFrameXCP *env) { + eXcpCommand_ALLOC_ODT_ENTRY *request = (eXcpCommand_ALLOC_ODT_ENTRY *) env->canFrame.data; + +#if (PROTECT_DAQ == 1) + if (isUNLOCK(env, XCP_PROTECT_DAQ) == false) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_ACCESS_LOCKED; + + return 2; + } +#endif + + + env->DAQ[request->DAQ_LIST_NUMBER].ODT_NUMBER[request->ODT_NUMBER].ODT_ENTRIES_COUNT = request->ODT_ENTRIES_COUNT; + + env->response[0] = XCP_COMMAND_CONNECT; + return 1; +} + + +static uint8_t XCP_SET_DAQ_PTR_E2(tCanSerialPortFrameXCP *env) { + eXcpCommand_SET_DAQ_PTR *request = (eXcpCommand_SET_DAQ_PTR *) env->canFrame.data; + +#if (PROTECT_DAQ == 1) + if (isUNLOCK(env, XCP_PROTECT_DAQ) == false) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_ACCESS_LOCKED; + + return 2; + } +#endif + + + if ((request->DAQ_LIST_NUMBER > MAX_DAO) || + (request->ODT_NUMBER > MAX_ODT) || + (request->ODT_ENTRY_NUMBER > MAX_ODT_ENTRIES_SIZE_DAQ)) { + + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_OUT_OF_RANGE; + + return 2; + } + + env->SETUP.DAQ_LIST_NUMBER = request->DAQ_LIST_NUMBER; + env->SETUP.ODT_NUMBER = request->ODT_NUMBER; + env->SETUP.ODT_ENTRY_NUMBER = request->ODT_ENTRY_NUMBER; + + + env->response[0] = XCP_COMMAND_CONNECT; + return 1; +} + +static uint8_t XCP_WRITE_DAQ_E1(tCanSerialPortFrameXCP *env) { + eXcpCommand_WRITE_DAQ *request = (eXcpCommand_WRITE_DAQ *) env->canFrame.data; + +#if (PROTECT_DAQ == 1) + if (isUNLOCK(env, XCP_PROTECT_DAQ) == false) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_ACCESS_LOCKED; + + return 2; + } +#endif + + + if (env->SETUP.ODT_ENTRY_NUMBER > MAX_ODT_ENTRIES_SIZE_DAQ) { + + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_OUT_OF_RANGE; + + return 2; + } + + env->DAQ[env->SETUP.DAQ_LIST_NUMBER].ODT_NUMBER[env->SETUP.ODT_NUMBER].BIT_OFFSET[env->SETUP.ODT_ENTRY_NUMBER] = request->BIT_OFFSET; + env->DAQ[env->SETUP.DAQ_LIST_NUMBER].ODT_NUMBER[env->SETUP.ODT_NUMBER].ADR_EXT[env->SETUP.ODT_ENTRY_NUMBER] = request->ADR_EXT; + env->DAQ[env->SETUP.DAQ_LIST_NUMBER].ODT_NUMBER[env->SETUP.ODT_NUMBER].ODT_ENTRIES_ADR[env->SETUP.ODT_ENTRY_NUMBER] = request->ADR; + env->DAQ[env->SETUP.DAQ_LIST_NUMBER].ODT_NUMBER[env->SETUP.ODT_NUMBER].ODT_ENTRIES_SIZE[env->SETUP.ODT_ENTRY_NUMBER] = request->ODT_ENTRY_SIZE; + + ++env->SETUP.ODT_ENTRY_NUMBER; + + env->response[0] = XCP_COMMAND_CONNECT; + return 1; +} + +static uint8_t XCP_SET_DAQ_LIST_MODE_E0(tCanSerialPortFrameXCP *env) { + eXcpCommand_SET_DAQ_LIST_MODE *request = (eXcpCommand_SET_DAQ_LIST_MODE *) env->canFrame.data; + +#if (PROTECT_DAQ == 1) + if (isUNLOCK(env, XCP_PROTECT_DAQ) == false) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_ACCESS_LOCKED; + + return 2; + } +#endif + + + if ((request->DAQ_LIST_NUMBER > MAX_DAO) || (request->EVENT_CHANNEL_NUMBER > MAX_EVENT_CHANNEL)) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_OUT_OF_RANGE; + + return 2; + } + + env->DAQ[request->DAQ_LIST_NUMBER].EVENT_CHANNEL = request->EVENT_CHANNEL_NUMBER; + + env->DAQ[request->DAQ_LIST_NUMBER].ALTERNATING = request->ALTERNATING; + env->DAQ[request->DAQ_LIST_NUMBER].DIRECTION = request->DIRECTION; + env->DAQ[request->DAQ_LIST_NUMBER].DTO_CTR = request->DTO_CTR; + env->DAQ[request->DAQ_LIST_NUMBER].TIMESTAMP = request->TIMESTAMP; + env->DAQ[request->DAQ_LIST_NUMBER].PID_OFF = request->PID_OFF; + + env->DAQ[request->DAQ_LIST_NUMBER].TRANSMISSION_RATE_PRESCALER = request->TRANSMISSION_RATE_PRESCALER - 1; + env->DAQ[request->DAQ_LIST_NUMBER].DAQ_LIST_PRIORITY = request->DAQ_LIST_PRIORITY; + + env->DAQ[request->DAQ_LIST_NUMBER].PRESCALER_COUNTER = request->TRANSMISSION_RATE_PRESCALER - 1; + + env->response[0] = XCP_COMMAND_CONNECT; + return 1; +} + +static uint8_t XCP_START_STOP_DAQ_LIST_DE(tCanSerialPortFrameXCP *env) { + eXcpCommand_START_STOP_DAQ_LIST *request = (eXcpCommand_START_STOP_DAQ_LIST *) env->canFrame.data; + +#if (PROTECT_DAQ == 1) + if (isUNLOCK(env, XCP_PROTECT_DAQ) == false) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_ACCESS_LOCKED; + + return 2; + } +#endif + + + if (request->DAQ_LIST_NUMBER > MAX_DAO) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_OUT_OF_RANGE; + + return 2; + } + + if (request->MODE == XCP_STOP) { + env->DAQ[request->DAQ_LIST_NUMBER].RUNNING = 0; + } + + if (request->MODE == XCP_START) { + env->DAQ[request->DAQ_LIST_NUMBER].RUNNING = 1; + } + + if (request->MODE == XCP_SELECT) { + env->DAQ[request->DAQ_LIST_NUMBER].SELECTED = 1; + } + + env->response[0] = XCP_COMMAND_CONNECT; + return 1; +} + +static uint8_t XCP_START_STOP_SYNCH_DD(tCanSerialPortFrameXCP *env) { + eXcpCommand_START_STOP_SYNCH *request = (eXcpCommand_START_STOP_SYNCH *) env->canFrame.data; + +#if (PROTECT_DAQ == 1) + if (isUNLOCK(env, XCP_PROTECT_DAQ) == false) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_ACCESS_LOCKED; + + return 2; + } +#endif + + + if (request->MODE == XCP_SYNC_START_SEL) { + for (uint16 i = 0; i < MAX_DAO; ++i) { + if (env->DAQ[i].SELECTED) { + env->DAQ[i].RUNNING = 1; + } + } + } + + if (request->MODE == XCP_SYNC_STOP_ALL) { + + for (uint16 i = 0; i < MAX_DAO; ++i) { + env->DAQ[i].RUNNING = 0; + } + + FREE_DAQ(env); + } + + if (request->MODE == XCP_SYNC_STOP_SEL) { + for (uint16 i = 0; i < MAX_DAO; ++i) { + if (env->DAQ[i].SELECTED) { + env->DAQ[i].RUNNING = 1; + } + } + } + + env->response[0] = XCP_COMMAND_CONNECT; + return 2; +} + +static uint8_t XCP_READ_DAQ_DB(tCanSerialPortFrameXCP *env) { + eXcpCommand_WRITE_DAQ *response = (eXcpCommand_WRITE_DAQ *) env->response; + +#if (PROTECT_DAQ == 1) + if (isUNLOCK(env, XCP_PROTECT_DAQ) == false) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_ACCESS_LOCKED; + + return 2; + } +#endif + + + response->COM = XCP_COMMAND_CONNECT; + response->BIT_OFFSET = env->DAQ[env->SETUP.DAQ_LIST_NUMBER].ODT_NUMBER[env->SETUP.ODT_NUMBER].BIT_OFFSET[env->SETUP.ODT_ENTRY_NUMBER]; + response->ADR_EXT = env->DAQ[env->SETUP.DAQ_LIST_NUMBER].ODT_NUMBER[env->SETUP.ODT_NUMBER].ADR_EXT[env->SETUP.ODT_ENTRY_NUMBER]; + response->ADR = env->DAQ[env->SETUP.DAQ_LIST_NUMBER].ODT_NUMBER[env->SETUP.ODT_NUMBER].ODT_ENTRIES_ADR[env->SETUP.ODT_ENTRY_NUMBER]; + response->ODT_ENTRY_SIZE = env->DAQ[env->SETUP.DAQ_LIST_NUMBER].ODT_NUMBER[env->SETUP.ODT_NUMBER].ODT_ENTRIES_SIZE[env->SETUP.ODT_ENTRY_NUMBER]; + + ++env->SETUP.ODT_ENTRY_NUMBER; + + return 8; +} + +static uint8_t XCP_GET_DAQ_PROCESSOR_INFO_DA(tCanSerialPortFrameXCP *env) { + + eXcpCommand_GET_DAQ_PROCESSOR_INFO *response = (eXcpCommand_GET_DAQ_PROCESSOR_INFO *) env->response; + +#if (PROTECT_DAQ == 1) + if (isUNLOCK(env, XCP_PROTECT_DAQ) == false) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_ACCESS_LOCKED; + + return 2; + } +#endif + + + response->COM = XCP_COMMAND_CONNECT; + + response->DAQ_CONFIG_TYPE = 1; // dynamic DAQ list configuration + response->PRESCALER_SUPPORTED = 1; // prescaler supported + response->RESUME_SUPPORTED = 0; // DAQ lists can not be set to RESUME mode + response->BIT_STIM_SUPPORTED = 0; // bitwise data stimulation not supported + response->TIMESTAMP_SUPPORTED = 0; // time-stamped mode not supported + response->PID_OFF_SUPPORTED = 0; // Identification field can not be switched off + response->OVERLOAD_MSB = 0; // No overload indication + response->OVERLOAD_EVENT = 0; // No overload indication + + response->MAX_DAQ = MAX_DAO; + response->MAX_EVENT_CHANNEL_ = MAX_EVENT_CHANNEL; + response->MIN_DAQ = 0; + + response->Optimisation_Type_0 = 0; + response->Optimisation_Type_1 = 1; + response->Optimisation_Type_2 = 0; + response->Optimisation_Type_3 = 1; + response->Address_Extension_ODT = 0; + response->Address_Extension_DAQ = 0; + response->Identification_Field_Type_0 = 1; // Relative ODT number, absolute DAQ list number (BYTE) + response->Identification_Field_Type_1 = 0; // Relative ODT number, absolute DAQ list number (BYTE) + + + return 8; +} + +static uint8_t XCP_GET_DAQ_RESOLUTION_INFO_D9(tCanSerialPortFrameXCP *env) { + eXcpCommand_GET_DAQ_RESOLUTION_INFO *response = (eXcpCommand_GET_DAQ_RESOLUTION_INFO *) env->response; + +#if (PROTECT_DAQ == 1) + if (isUNLOCK(env, XCP_PROTECT_DAQ) == false) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_ACCESS_LOCKED; + + return 2; + } +#endif + + + response->COM = XCP_COMMAND_CONNECT; + + response->GRANULARITY_ODT_ENTRY_SIZE_DAQ = 1; + response->MAX_ODT_ENTRY_SIZE_DAQ = MAX_ODT_ENTRIES_SIZE_DAQ; + response->GRANULARITY_ODT_ENTRY_SIZE_STIM = 1; + response->MAX_ODT_ENTRY_SIZE_STIM = MAX_ODT_ENTRIES_SIZE_DAQ; + response->TIMESTAMP_MODE = 0; + response->TIMESTAMP_TICKS = 0; + + return 8; +} + + +static uint8_t XCP_GET_DAQ_LIST_MODE_DF(tCanSerialPortFrameXCP *env) { + + eXcpCommand_GET_DAQ_LIST_MODE_GET *request = (eXcpCommand_GET_DAQ_LIST_MODE_GET *) env->canFrame.data; + +#if (PROTECT_DAQ == 1) + if (isUNLOCK(env, XCP_PROTECT_DAQ) == false) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_ACCESS_LOCKED; + + return 2; + } +#endif + + + if (request->DAQ_LIST_NUMBER > MAX_DAO) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_OUT_OF_RANGE; + + return 2; + } + + eXcpCommand_GET_DAQ_LIST_MODE *response = (eXcpCommand_GET_DAQ_LIST_MODE *) env->response; + + response->COM = XCP_COMMAND_CONNECT; + + response->SELECTED = env->DAQ[request->DAQ_LIST_NUMBER].SELECTED; + response->DIRECTION = env->DAQ[request->DAQ_LIST_NUMBER].DIRECTION; + response->RESERVED1 = 0; + response->DTO_CTR = env->DAQ[request->DAQ_LIST_NUMBER].DTO_CTR; + response->TIMESTAMP = env->DAQ[request->DAQ_LIST_NUMBER].TIMESTAMP; + response->PID_OFF = env->DAQ[request->DAQ_LIST_NUMBER].PID_OFF; + response->RUNNING = env->DAQ[request->DAQ_LIST_NUMBER].RUNNING; + response->RESUME = 0; + + response->RESERVED2 = 0; + response->CURRENT_EVENT_CHANNEL_NUMBER = env->DAQ[request->DAQ_LIST_NUMBER].EVENT_CHANNEL; + response->CURRENT_PRESCALER = env->DAQ[request->DAQ_LIST_NUMBER].TRANSMISSION_RATE_PRESCALER; + response->CURRENT_DAQ_LIST_PRIORITY = env->DAQ[request->DAQ_LIST_NUMBER].DAQ_LIST_PRIORITY; + + return 8; +} + + +static uint8_t XCP_GET_DAQ_EVENT_INFO_D7(tCanSerialPortFrameXCP *env) { + + eXcpCommand_GET_DAQ_EVENT_INFO_GET *request = (eXcpCommand_GET_DAQ_EVENT_INFO_GET *) env->canFrame.data; + +#if (PROTECT_DAQ == 1) + if (isUNLOCK(env, XCP_PROTECT_DAQ) == false) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_ACCESS_LOCKED; + + return 2; + } +#endif + + + if (request->EVENT_CHANNEL_NUMBER > MAX_EVENT_CHANNEL) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_OUT_OF_RANGE; + + return 2; + } + + eXcpCommand_GET_DAQ_EVENT_INFO *response = (eXcpCommand_GET_DAQ_EVENT_INFO *) env->response; + + response->COM = XCP_COMMAND_CONNECT; + + response->RESERVED1 = 0; + response->RESERVED2 = 0; + + if (request->EVENT_CHANNEL_NUMBER == 0) { // DTO-STIM + response->DAQ = 1; + response->STM = 0; + } else { // DTO-DAQ + response->DAQ = 0; + response->STM = 1; + } + + response->RESERVED3 = 0; + response->RESERVED4 = 0; + response->CONSISTENCY_DAQ = 0; + response->CONSISTENCY_EVENT = 0; + + response->MAX_DAQ_LIST = 255; + response->EVENT_CHANNEL_NAME_LENGTH = 0; + response->EVENT_CHANNEL_TIME_CYCLE = 1; + response->EVENT_CHANNEL_TIME_UNIT = 7; // EVENT_CHANNEL _TIME_UNIT_10MS + response->EVENT_CHANNEL_PRIORITY = 255; + + return 7; +} + +static uint8_t XCP_GET_DAQ_STM(tCanSerialPortFrameXCP *env) { + eXcpCommand_GET_DAQ_STM *response = (eXcpCommand_GET_DAQ_STM *) env->canFrame.data; + + uint8_t *COUNTER = &env->DAQ[response->DAQ].ODT_NUMBER[response->ODT].DATA_STM_COUNTER; + + memcpy(env->DAQ[response->DAQ].ODT_NUMBER[response->ODT].DATA_STM[*COUNTER].DATA, &env->canFrame.data[3], + env->canFrame.dlc - 2); + + ++env->DAQ[response->DAQ].ODT_NUMBER[response->ODT].DATA_STM_COUNTER; + + if (*COUNTER == env->DAQ[response->DAQ].ODT_COUNT) { + *COUNTER = 0; + env->DAQ[response->DAQ].IS_STIM_RECEIVED = 1; + } + + return 0; +} + +static uint8_t XCP_PROGRAM_START_D2(tCanSerialPortFrameXCP *env) { + eXcpCommand_PROGRAM_START *response = (eXcpCommand_PROGRAM_START *) env->response; + +#if (PROTECT_PGM == 1) + if (isUNLOCK(env, XCP_PROTECT_PGM) == false) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_ACCESS_LOCKED; + + return 2; + } +#endif + + response->COM = XCP_COMMAND_CONNECT; + response->RESERVED1 = 0; + + response->_MASTER_BLOCK_MODE = PROGRAM_MASTER_BLOCK_MODE; + response->INTERLEAVED_MODE = 0; + response->RESERVED2 = 0; + response->RESERVED3 = 0; + response->RESERVED4 = 0; + response->RESERVED5 = 0; + response->_SLAVE_BLOCK_MODE = SLAVE_BLOCK_MODE; + response->RESERVED6 = 0; + + response->MAX_CTO_PGM = 8; + response->MAX_BS_PGM = 255; // Максимальный размер блока в режиме программирования. Определяет, сколько пакетов можно отправить подряд в блочном режиме + response->MIN_ST_PGM = 1; // Минимальное время шага (Minimum Separation Time). Определяет минимальную паузу (в миллисекундах) + response->QUEUE_SIZE_PGM = 10; // Размер очереди. Указывает, сколько пакетов типа CTO мастер может отправить "подряд" + + return 8; +} + +static uint8_t XCP_PROGRAM_CLEAR_D1(tCanSerialPortFrameXCP *env) { + eXcpCommand_XCP_PROGRAM_CLEAR_D1 *request = (eXcpCommand_XCP_PROGRAM_CLEAR_D1 *) env->canFrame.data; + +#if (PROTECT_PGM == 1) + if (isUNLOCK(env, XCP_PROTECT_PGM) == false) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_ACCESS_LOCKED; + + return 2; + } +#endif + + + if (request->MODE == 0) { + + if ((env->ADR_MTA < env->startFlashAdr) || ((env->ADR_MTA + request->CLEAR_RANGE) > env->endFlashAdr)) { + + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_ACCESS_DENIED; + + return 2; + } + + env->clear_flash_func(env->ADR_MTA, request->CLEAR_RANGE, NULL, NULL); + } else { + + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_OUT_OF_RANGE; + + return 2; + } + + env->response[0] = XCP_COMMAND_CONNECT; + return 1; +} + +static uint8_t XCP_PROGRAM_D0(tCanSerialPortFrameXCP *env) { + eXcpCommand_Program_ProgramNext_D0_CA *request = (eXcpCommand_Program_ProgramNext_D0_CA *) env->canFrame.data; + +#if (PROTECT_PGM == 1) + if (isUNLOCK(env, XCP_PROTECT_PGM) == false) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_ACCESS_LOCKED; + + return 2; + } +#endif + + + uint8_t COUNT = env->canFrame.dlc - 2; + + for (uint8_t i = 0; i < COUNT; ++i) { + + env->bufWriteFlash[env->bufWriteFlashCount] = env->canFrame.data[2 + i]; + + ++env->bufWriteFlashCount; + + if (env->bufWriteFlashCount >= PROGRAM_MAX_BUF) { + bool result = env->write_flash_func(env->bufWriteFlashAdr, env->bufWriteFlash, PROGRAM_MAX_BUF); + env->bufWriteFlashAdr += PROGRAM_MAX_BUF; + env->bufWriteFlashCount = 0; + } + + + } + + env->ADR_MTA += request->COUNT; + + env->response[0] = XCP_COMMAND_CONNECT; + return 1; +} + + +static uint8_t PROGRAM_VERIFY_C8(tCanSerialPortFrameXCP *env) { + eXcpCommand_Program_Verify_C8 *request = (eXcpCommand_Program_Verify_C8 *) env->canFrame.data; + +#if (PROTECT_PGM == 1) + if (isUNLOCK(env, XCP_PROTECT_PGM) == false) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_ACCESS_LOCKED; + + return 2; + } +#endif + + + if (env->bufWriteFlashCount > 0) { + bool result = env->write_flash_func(env->bufWriteFlashAdr, env->bufWriteFlash, env->bufWriteFlashCount); + env->bufWriteFlashCount = 0; + } + + VarsTabDumpObserverCalib_Load(env->varsTabDumpObserver); + + env->response[0] = XCP_COMMAND_CONNECT; + return 1; +} + +static uint8_t XCP_PROGRAM_NEXT_CA(tCanSerialPortFrameXCP *env) { + eXcpCommand_Program_ProgramNext_D0_CA *request = (eXcpCommand_Program_ProgramNext_D0_CA *) env->canFrame.data; + +#if (PROTECT_PGM == 1) + if (isUNLOCK(env, XCP_PROTECT_PGM) == false) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_ACCESS_LOCKED; + + return 2; + } +#endif + + + uint8_t COUNT = env->canFrame.dlc - 2; + + env->write_flash_func(env->ADR_MTA, &env->canFrame.data[2], request->COUNT); + + env->ADR_MTA += request->COUNT; + + return 0; +} + + +static uint8_t XCP_PROGRAM_PREPARE_CC(tCanSerialPortFrameXCP *env) { + eXcpCommand_Program_Prepare_CC *request = (eXcpCommand_Program_Prepare_CC *) env->canFrame.data; + +#if (PROTECT_PGM == 1) + if (isUNLOCK(env, XCP_PROTECT_PGM) == false) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_ACCESS_LOCKED; + + return 2; + } +#endif + + + if ((env->ADR_MTA < env->startFlashAdr) || ((env->ADR_MTA + request->CODESIZE) > env->endFlashAdr)) { + + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_GENERIC; + + return 2; + } + + env->response[0] = XCP_COMMAND_CONNECT; + return 1; + +} + + +static uint8_t XCP_PROGRAM_FORMAT_CB(tCanSerialPortFrameXCP *env) { + eXcpCommand_Program_Format_CB *request = (eXcpCommand_Program_Format_CB *) env->canFrame.data; + +#if (PROTECT_PGM == 1) + if (isUNLOCK(env, XCP_PROTECT_PGM) == false) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_ACCESS_LOCKED; + + return 2; + } +#endif + + + env->response[0] = XCP_COMMAND_CONNECT; + return 1; + +} + +static uint8_t XCP_PROGRAM_RESET_CF(tCanSerialPortFrameXCP *env) { + env->response[0] = XCP_COMMAND_CONNECT; + +#if (PROTECT_PGM == 1) + if (isUNLOCK(env, XCP_PROTECT_PGM) == false) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_ACCESS_LOCKED; + + return 2; + } +#endif + + + if (env->bufWriteFlashCount > 0) { + bool result = env->write_flash_func(env->bufWriteFlashAdr, env->bufWriteFlash, env->bufWriteFlashCount); + env->bufWriteFlashCount = 0; + } + + return 1; +} + +static uint8_t XCP_GET_PGM_PROCESSOR_INFO_CE(tCanSerialPortFrameXCP *env) { + eXcpCommand_PGM_PROCESSOR_INFO_CE *response = (eXcpCommand_PGM_PROCESSOR_INFO_CE *) env->response; + +#if (PROTECT_PGM == 1) + if (isUNLOCK(env, XCP_PROTECT_PGM) == false) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_ACCESS_LOCKED; + + return 2; + } +#endif + + + response->COM = XCP_COMMAND_CONNECT; + + response->ABSOLUTE_MODE = 1; + response->FUNCTIONAL_MODE = 0; + response->COMPRESSION_SUPPORTED = 0; + response->COMPRESSION_REQUIRED = 0; + response->ENCRYPTION_SUPPORTED = 0; + response->ENCRYPTION_REQUIRED = 0; + response->NON_SEQ_PGM_SUPPORTED = 0; + response->NON_SEQ_PGM_REQUIRED = 0; + + response->MAX_SECTOR = PROGRAM_MAX_SECTOR; + + return 3; +} + +static uint8_t XCP_GET_SECTOR_INFO_CD(tCanSerialPortFrameXCP *env) { + eXcpCommand_REQ_GET_SECTOR_INFO_CD *request = (eXcpCommand_REQ_GET_SECTOR_INFO_CD *) env->canFrame.data; + +#if (PROTECT_PGM == 1) + if (isUNLOCK(env, XCP_PROTECT_PGM) == false) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_ACCESS_LOCKED; + + return 2; + } +#endif + + + if (request->SECTOR_NUMBER > PROGRAM_MAX_SECTOR) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_OUT_OF_RANGE; + + return 2; + } + + eXcpCommand_RESP_GET_SECTOR_INFO_CD *response = (eXcpCommand_RESP_GET_SECTOR_INFO_CD *) env->response; + response->COM = XCP_COMMAND_CONNECT; + response->CLEAR_SEQUENCE_NUMBER = request->SECTOR_NUMBER; + response->PROGRAM_SEQUENCE_NUMBER = request->SECTOR_NUMBER; + + response->ABSOLUTE_MODE = 1; + response->FUNCTIONAL_MODE = 0; + response->PAGED_MODE = 0; + response->SEQUENTIAL_ONLY = 1; + response->ERASE_BEFORE_WRITE = 1; + response->VERIFY_AFTER_WRITE = 0; + response->RESERVED1 = 0; + response->RESERVED2 = 0; + + if (request->MODE == 0) { + response->SECTOR_INFO = request->SECTOR_NUMBER * FLASH_PAGE_D_SIZE + env->startFlashAdr; + } else if (request->MODE == 1) { + response->SECTOR_INFO = FLASH_PAGE_D_SIZE; + } else if (request->MODE == 2) { + env->response[1] = 0; + return 2; + } else { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_CMD_SYNTAX; + return 2; + } + + return 8; +} + +static uint8_t XCP_SET_CALIBRATION_PAGE_EB(tCanSerialPortFrameXCP *env) { + eXcpCommand_SET_CALIBRATION_PAGE_EB *request = (eXcpCommand_SET_CALIBRATION_PAGE_EB *) env->canFrame.data; + + env->PAGE_ID = request->PAGE; + + env->response[0] = XCP_COMMAND_CONNECT; + return 1; +} + +static uint8_t XCP_GET_CAL_PAGE_EA(tCanSerialPortFrameXCP *env) { + eXcpCommand_XCP_GET_CAL_PAGE_EA *request = (eXcpCommand_XCP_GET_CAL_PAGE_EA *) env->canFrame.data; + +#if (PROTECT_CAL_PAG == 1) + if (isUNLOCK(env, XCP_PROTECT_CAL_PAG) == false) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_ACCESS_LOCKED; + + return 2; + } +#endif + + env->response[0] = XCP_COMMAND_CONNECT; + env->response[1] = env->PAGE_ID; + + return 2; +} + +const eXcp_com xcp_com[256] = { + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, + {NULL, ""}, // 0xC5 DTO_CTR_PROPERTIES + {NULL, ""}, // 0xC6 TIME_CORRELATION_PROPERTIES + {NULL, ""}, // 0xC7 WRITE_DAQ_MULTIPLE + {PROGRAM_VERIFY_C8, "PROGRAM_VERIFY_C8"}, + {NULL, ""}, // 0xC9 PROGRAM_MAX (This command does not support block transfer) + {XCP_PROGRAM_NEXT_CA, "XCP_PROGRAM_NEXT_CA"}, + {XCP_PROGRAM_FORMAT_CB, "XCP_PROGRAM_FORMAT_CB"}, // 0xCB PROGRAM_FORMAT + {XCP_PROGRAM_PREPARE_CC, "XCP_PROGRAM_PREPARE_CC"}, // 0xCC PROGRAM_PREPARE + {XCP_GET_SECTOR_INFO_CD, "XCP_GET_SECTOR_INFO_CD"}, + {XCP_GET_PGM_PROCESSOR_INFO_CE, "XCP_GET_PGM_PROCESSOR_INFO_CE"}, + {XCP_PROGRAM_RESET_CF, "XCP_PROGRAM_RESET_CF"}, + {XCP_PROGRAM_D0, "XCP_PROGRAM_D0"}, // This command does not support block transfer + {XCP_PROGRAM_CLEAR_D1, "XCP_PROGRAM_CLEAR_D1"}, + {XCP_PROGRAM_START_D2, "XCP_PROGRAM_START_D2"}, + {XCP_ALLOC_ODT_ENTRY_D3, "XCP_ALLOC_ODT_ENTRY_D3"}, + {XCP_ALLOC_ODT_D4, "XCP_ALLOC_ODT_D4"}, + {XCP_ALLOC_DAQ_D5, "XCP_ALLOC_DAQ_D5"}, + {XCP_FREE_DAQ_D6, "XCP_FREE_DAQ_D6"}, + {XCP_GET_DAQ_EVENT_INFO_D7, "XCP_GET_DAQ_EVENT_INFO_D7"}, + {XCP_GET_DAQ_LIST_INFO_D8, "XCP_GET_DAQ_LIST_INFO_D8"}, + {XCP_GET_DAQ_RESOLUTION_INFO_D9, "XCP_GET_DAQ_RESOLUTION_INFO_D9"}, + {XCP_GET_DAQ_PROCESSOR_INFO_DA, "XCP_GET_DAQ_PROCESSOR_INFO_DA"}, + {XCP_READ_DAQ_DB, "XCP_READ_DAQ_DB"}, + {NULL, ""}, //0xDC GET_DAQ_CLOCK + {XCP_START_STOP_SYNCH_DD, "XCP_START_STOP_SYNCH_DD"}, + {XCP_START_STOP_DAQ_LIST_DE, "XCP_START_STOP_DAQ_LIST_DE"}, + {XCP_GET_DAQ_LIST_MODE_DF, "XCP_GET_DAQ_LIST_MODE_DF"}, + {XCP_SET_DAQ_LIST_MODE_E0, "XCP_SET_DAQ_LIST_MODE_E0"}, + {XCP_WRITE_DAQ_E1, "XCP_WRITE_DAQ_E1"}, + {XCP_SET_DAQ_PTR_E2, "XCP_SET_DAQ_PTR_E2"}, + {XCP_CLEAR_DAQ_LIST_E3, "XCP_CLEAR_DAQ_LIST_E3"}, + {NULL, ""}, // 0xE4 COPY_CAL_PAGE + {NULL, ""}, // 0xE5 GET_SEGMENT_MODE + {NULL, ""}, // 0xE6 SET_SEGMENT_MODE + {NULL, ""}, // 0xE7 GET_PAGE_INFO + {NULL, ""}, // 0xE8 GET_SEGMENT_INFO + {NULL, ""}, // 0xE9 GET_PAG_PROCESSOR_INFO + {XCP_GET_CAL_PAGE_EA, "XCP_GET_CAL_PAGE_EA"}, // 0xEA GET_CAL_PAGE + {XCP_SET_CALIBRATION_PAGE_EB, "XCP_SET_CALIBRATION_PAGE_EB"}, + {NULL, ""}, // 0xEC MODIFY_BITS + {NULL, ""}, // 0xEB SHORT_DOWNLOAD (This command does not support block transfer) + {XCP_COMMAND_DOWNLOAD_MAX_EE, "XCP_COMMAND_DOWNLOAD_MAX_EE"}, // This command does not support block transfer + {XCP_COMMAND_DOWNLOAD_NEXT_EF, "XCP_COMMAND_DOWNLOAD_NEXT_EF"}, + {XCP_COMMAND_DOWNLOAD_F0, "XCP_COMMAND_DOWNLOAD_F0"}, + {NULL, ""}, // 0XF1 USER_CMD + {NULL, ""}, // 0xF2 DOWNLOAD + {NULL, ""}, // 0xF3 DOWNLOAD_NEXT + {XCP_COMMAND_SHORT_UPLOAD_F4, "XCP_COMMAND_SHORT_UPLOAD_F4"}, // This command does not support block transfer + {XCP_COMMAND_UPLOAD_F5, "XCP_COMMAND_UPLOAD_F5"}, + {XCP_COMMAND_SET_MTA_F6, "XCP_COMMAND_SET_MTA_F6"}, + {XCP_UNLOCK_F7, "XCP_UNLOCK_F7"}, + {XCP_GET_SEED_F8, "XCP_GET_SEED_F8"}, + {NULL, ""}, // 0xF9 SET_REQUEST + {NULL, ""}, // 0xFA GET_ID + {XCP_GET_COMM_MODE_INFO_FB, "XCP_GET_COMM_MODE_INFO_FB"}, + {XCP_COMMAND_SYNCH_FC, "XCP_COMMAND_SYNCH_FC"}, + {XCP_COMMAND_GET_STATUS_FD, "XCP_COMMAND_GET_STATUS_FD"}, + {XCP_COMMAND_DISCONNECT_FE, "XCP_COMMAND_DISCONNECT_FE"}, + {XCP_COMMAND_CONNECT_FF, "XCP_COMMAND_CONNECT_FF"} +}; + +uint8_t vCanSerialPortFrameXcpReceive(tCanSerialPortFrameXCP *env, uint32 timeout) { + uint8_t response_size = 0; + + uint16_t recv = env->ioCanFrame->receive(env->ioCanFrame->env, PROTOCOL_CAN_XCP, (uint8_t * ) & env->canFrame, + 1, + timeout); + + if (recv == 0) + return 0; + + if (osMutexAcquire(env->access, 100) == osOK) { + + eXcpTypeCommand com = env->canFrame.data[0]; + + if (com > 0xBF) { // CMD + +#if (LOG_XCP == 1) + if ((com != 0xD0) && (com != 0xF5)) { + PrintfDebug(env->canFrame.data, env->canFrame.dlc); + LoggerFormatInfo(LOGGER, LOG_SIGN, "> %s [%d] %s", xcp_com[com].desc, env->canFrame.dlc, strPrintfDebug_XCP) + } +#endif + if (xcp_com[com].func != NULL) { + + response_size = xcp_com[com].func(env); + + if (response_size) { + +#if (LOG_XCP == 1) + if ((com != 0xD0) && (com != 0xF5)) { + PrintfDebug(env->response, response_size); + LoggerFormatInfo(LOGGER, LOG_SIGN, "< [%d] %s", response_size, strPrintfDebug_XCP) + } +#endif + + env->ioCanFrame->transmit(env->ioCanFrame->env, env->response, response_size, + PROTOCOL_CAN_ADR_XCP, + PROTOCOL_CAN_TYPE_XCP, 100); + } + + } else { + asm("nop"); + } + + } else { // ODT + +#if (PROTECT_STIM == 1) + if (isUNLOCK(env, XCP_PROTECT_STM) == false) { + env->response[0] = XCP_COMMAND_DISCONNECT; + env->response[1] = XCP_ERR_ACCESS_LOCKED; + + env->ioCanFrame->transmit(env->ioCanFrame->env, env->response, 2, + PROTOCOL_CAN_ADR_XCP, + PROTOCOL_CAN_TYPE_XCP, 100); + } else { + XCP_GET_DAQ_STM(env); + } +#endif + +#if (PROTECT_STIM == 0) + XCP_GET_DAQ_STM(env); +#endif + } + + osMutexRelease(env->access); + } + + return response_size; +} + +/* +_Noreturn void CanXcpProcessing_Service_Dto_Stim_Task(tCanSerialPortFrameXCP *env) { + uint8_t size; + + while (1) { + + if (osMutexAcquire(env->access, 1000) == osOK) { + + for (uint16 i = 0; i < env->SETUP.DAQ_COUNT; ++i) { + + if ((env->DAQ[i].DIRECTION == 1) && + (env->DAQ[i].EVENT_CHANNEL == 0) && + (env->DAQ[i].RUNNING)) { // STIM - DTO + + if (env->DAQ[i].PRESCALER_COUNTER == 0) { + + env->DAQ[i].PRESCALER_COUNTER = env->DAQ[i].TRANSMISSION_RATE_PRESCALER; + + if (env->DAQ[i].IS_STIM_RECEIVED) { + + for (uint8_t j = 0; j < env->DAQ[i].ODT_COUNT; ++j) { + + size = 0; + + for (uint8_t k = 0; k < MAX_ODT_ENTRIES_SIZE_DAQ; ++k) { + + uint8_t ODT_ENTRIES_SIZE = env->DAQ[i].ODT_NUMBER[j].ODT_ENTRIES_SIZE[k]; + + if (ODT_ENTRIES_SIZE) { + + memcpy(&env->DATA[size], + env->DAQ[i].ODT_NUMBER[j].DATA_STM[k].DATA, + ODT_ENTRIES_SIZE); + + size += ODT_ENTRIES_SIZE; + + } + + } + + uint8_t size_stim = 0; + + for (uint8_t k = 0; k < MAX_ODT_ENTRIES_SIZE_DAQ; ++k) { + + + uint8_t ODT_ENTRIES_SIZE = env->DAQ[i].ODT_NUMBER[j].ODT_ENTRIES_SIZE[k]; + + if (ODT_ENTRIES_SIZE) { + + if ((size_stim + ODT_ENTRIES_SIZE) <= size) { + memcpy((uint8_t *) env->DAQ[i].ODT_NUMBER[j].ODT_ENTRIES_ADR[k], + &env->DAQ[i].ODT_NUMBER[j].DATA_STM[k].DATA[size_stim], + ODT_ENTRIES_SIZE); + + size_stim += ODT_ENTRIES_SIZE; + } else { + asm("nop"); + } + + } + + + } + + + } + + env->DAQ[i].IS_STIM_RECEIVED = 0; + + } else { + asm("nop"); + } + + + } else { + --env->DAQ[i].PRESCALER_COUNTER; + } + + + } + + + } + + osMutexRelease(env->access); + } + + SystemDelayMs(10); + } + + +} + + +void Dto_Daq(tCanSerialPortFrameXCP *env, uint16_t channel, uint32_t timeout) { + + uint8_t size; + + if (osMutexAcquire(env->access, 1000) == osOK) { + + for (uint16 i = 0; i < env->SETUP.DAQ_COUNT; ++i) { + + if ((env->DAQ[i].DIRECTION == 0) && + (env->DAQ[i].EVENT_CHANNEL == channel) && + (env->DAQ[i].RUNNING)) { // DAQ - DTO + + if (env->DAQ[i].PRESCALER_COUNTER == 0) { + + env->DAQ[i].PRESCALER_COUNTER = env->DAQ[i].TRANSMISSION_RATE_PRESCALER; + + for (uint8_t j = 0; j < env->DAQ[i].ODT_COUNT; ++j) { + + env->response[0] = j; // ODT + env->response[1] = i; // DAQ + size = 0; + + for (uint8_t k = 0; k < MAX_ODT_ENTRIES_SIZE_DAQ; ++k) { + + uint8_t ODT_ENTRIES_SIZE = env->DAQ[i].ODT_NUMBER[j].ODT_ENTRIES_SIZE[k]; + + if (ODT_ENTRIES_SIZE) { + + memcpy(&env->DATA[size], + (uint8_t *) env->DAQ[i].ODT_NUMBER[j].ODT_ENTRIES_ADR[k], + ODT_ENTRIES_SIZE); + + size += ODT_ENTRIES_SIZE; + + } + + } + + uint8_t count_size = size / BODY_MAX_LEN; + uint8_t count_size_tail = size % BODY_MAX_LEN; + + size = 0; + + for (uint8_t k = 0; k < count_size; ++k) { + memcpy(&env->response[2], &env->DATA[size], BODY_MAX_LEN); + env->ioCanFrame->transmit(env->ioCanFrame->env, env->response, MAX_DTO, + PROTOCOL_CAN_ADR_XCP, PROTOCOL_CAN_TYPE_XCP, + 100); + size += BODY_MAX_LEN; + } + + if (count_size_tail) { + memcpy(&env->response[2], &env->DATA[size], count_size_tail); + env->ioCanFrame->transmit(env->ioCanFrame->env, env->response, + count_size_tail + 2, + PROTOCOL_CAN_ADR_XCP, PROTOCOL_CAN_TYPE_XCP, + 100); + } + + + } + + + } else { + --env->DAQ[i].PRESCALER_COUNTER; + } + + + } + + + } + + osMutexRelease(env->access); + } + + SystemDelayMs(timeout); +} + + +_Noreturn void CanXcpProcessing_Service_Dto_Daq_10_Task(tCanSerialPortFrameXCP *env) { + while (1) { + Dto_Daq(env, 1, 10); + } +} + +_Noreturn void CanXcpProcessing_Service_Dto_Daq_100_Task(tCanSerialPortFrameXCP *env) { + while (1) { + Dto_Daq(env, 2, 100); + } +} + +_Noreturn void CanXcpProcessing_Service_Dto_Daq_1000_Task(tCanSerialPortFrameXCP *env) { + while (1) { + Dto_Daq(env, 3, 1000); + } +} + +void CanXcpProcessing_Service_Start(tCanSerialPortFrameXCP *env) { + InitThreadBlock(env->T_can_Listener_Dto_Stim_XCP, "DtoStim_XCP", osPriorityNormal); + ThreadBlock_Start(env->T_can_Listener_Dto_Stim_XCP, env, CanXcpProcessing_Service_Dto_Stim_Task); + + InitThreadBlock(env->T_can_Listener_Dto_Daq_10_XCP, "DtoDaq_10_XCP", osPriorityNormal); + ThreadBlock_Start(env->T_can_Listener_Dto_Daq_10_XCP, env, CanXcpProcessing_Service_Dto_Daq_10_Task); + + InitThreadBlock(env->T_can_Listener_Dto_Daq_100_XCP, "DtoDaq_100_XCP", osPriorityNormal); + ThreadBlock_Start(env->T_can_Listener_Dto_Daq_100_XCP, env, CanXcpProcessing_Service_Dto_Daq_100_Task); + + InitThreadBlock(env->T_can_Listener_Dto_Daq_1000_XCP, "DtoDaq_1000_XCP", osPriorityNormal); + ThreadBlock_Start(env->T_can_Listener_Dto_Daq_1000_XCP, env, CanXcpProcessing_Service_Dto_Daq_1000_Task); + +} +*/ +_Noreturn void CanXcpProcessing_ListenerTask(tCanSerialPortFrameXCP *env) { + while (1) { + vCanSerialPortFrameXcpReceive(env, 1000); + } +} + +void CanXcpProcessing_Listener_Start(tCanSerialPortFrameXCP *env) { +// ThreadBlock_Start(env->T_can_Listener_XCP, env, CanXcpProcessing_ListenerTask); + if (!env->thread_Listener_XCP.id) { + env->thread_Listener_XCP.id = osThreadNew((osThreadFunc_t) (CanXcpProcessing_ListenerTask), (void *) (env), &env->thread_Listener_XCP.attr); + } + +// CanXcpProcessing_Service_Start(env); +} diff --git a/MODULES/CanSerialPortFrame_XCP/modular.json b/MODULES/CanSerialPortFrame_XCP/modular.json new file mode 100644 index 0000000..71971cd --- /dev/null +++ b/MODULES/CanSerialPortFrame_XCP/modular.json @@ -0,0 +1,10 @@ +{ + "cmake": { + "inc_dirs": [ + "Inc" + ], + "srcs": [ + "Src/**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/CliCmd/Inc/CliCmd.h b/MODULES/CliCmd/Inc/CliCmd.h new file mode 100644 index 0000000..8229bfb --- /dev/null +++ b/MODULES/CliCmd/Inc/CliCmd.h @@ -0,0 +1,63 @@ +// +// Created by CFIF on 14.11.22. +// + +#ifndef UVEOS_ON_NATION_CLICMD_H +#define UVEOS_ON_NATION_CLICMD_H + +#include "SerialPort.h" +#include "stdbool.h" +#include "stddef.h" +#include "LoggerToSerialPort.h" + +typedef struct { + struct { + char *data; + size_t limit; + char *begin; + size_t length; + } rxLine; + + tSerialPortIO *serialCommandPortIn; + tSerialPortIO *serialCommandPortOut; + tLoggerToSerialPort *loggerToSerialPort; + +} tCliCmd; + +void CliCmd_Init(tCliCmd *env, tLoggerToSerialPort *loggerToSerialPort, tSerialPortIO *io_in, tSerialPortIO *io_out, + uint8_t *data, size_t dataLen); + +#define CliCmd_InitStatic(ENV, LOGGER, IO_IN, IO_OUT, DATA) CliCmd_Init(ENV, LOGGER, IO_IN,IO_OUT,DATA,sizeof(DATA)); + +void CliCmd_WaitLine(tCliCmd *env); + +void CliCmd_Print(tCliCmd *cli, char *text, uint16_t len); + +void CliCmd_PrintHex(tCliCmd *cli, uint8_t *data, uint16_t byteLen); + +char *CliCmd_RxLineBegin(tCliCmd *cli); + +char *CliCmd_RxLineEnd(tCliCmd *cli); + +size_t CliCmd_RxLineLength(tCliCmd *cli); + +char *CliCmd_RxStartsWith(tCliCmd *cli, char *text, uint16_t len); + +void CliCmd_RxSkipSpace(tCliCmd *cli); + +void CliCmd_RxSkipTo(tCliCmd *cli, char *next); + +void CliCmd_WaitLineDelay(tCliCmd *env, uint32_t delay); + +void CliCmd_RxSkip(tCliCmd *cli, size_t len); + +#define CliCmd_PrintStatic(CLI, STR) CliCmd_Print(CLI,STR,sizeof(STR)-1) + +#define CliCmd_PrintLnStatic(CLI, STR) CliCmd_PrintStatic(CLI,(STR "\r\n")) + +#define CliCmd_PrintSpStatic(CLI, STR) CliCmd_PrintStatic(CLI,(STR " ")) + +// 1 если STR присутствует первым блоком в cli->data +#define CliCmd_RxStartsWithStatic(CLI, STR) CliCmd_RxStartsWith(CLI,(STR),sizeof(STR) - 1) + +#endif //UVEOS_ON_NATION_CLICMD_H diff --git a/MODULES/CliCmd/Src/CliCmd.c b/MODULES/CliCmd/Src/CliCmd.c new file mode 100644 index 0000000..5790d50 --- /dev/null +++ b/MODULES/CliCmd/Src/CliCmd.c @@ -0,0 +1,136 @@ +// +// Created by CFIF on 14.11.22. +// +#include +#include "CliCmd.h" +#include "AsciiStringParsingUtils.h" +#include "AsciiStringAssmeblingUtils.h" +#include "SystemDelayInterface.h" +#include "LoggerToSerialPort.h" + +void CliCmd_Init(tCliCmd *env, tLoggerToSerialPort *loggerToSerialPort, tSerialPortIO *io_in, tSerialPortIO *io_out, + uint8_t *data, size_t dataLen) { + env->loggerToSerialPort = loggerToSerialPort; + env->serialCommandPortIn = io_in; + env->serialCommandPortOut = io_out; + env->rxLine.limit = dataLen; + env->rxLine.data = (char *) data; + vAsciiStringInit(env->rxLine.data, &env->rxLine.length, env->rxLine.limit); + env->rxLine.begin = env->rxLine.data; +} + +void CliCmd_WaitLine(tCliCmd *env) { + //чистим буфер + //получаем строку + //печатаем ее в ответ + + SerialPortClearRxBuffer(env->serialCommandPortIn); + vAsciiStringClean(env->rxLine.data, &env->rxLine.length); + + env->rxLine.length = SerialPortReceiveTo( + env->serialCommandPortIn, + (uint8_t *) env->rxLine.data, + env->rxLine.limit, + '\n', + SystemWaitForever + ); + + env->rxLine.begin = env->rxLine.data; + if (env->rxLine.length && (*(CliCmd_RxLineEnd(env) - 2) == '\n')) { + --env->rxLine.length; + } + CliCmd_Print(env, CliCmd_RxLineBegin(env), CliCmd_RxLineLength(env)); +} + +void CliCmd_WaitLineDelay(tCliCmd *env, uint32_t delay) { + //чистим буфер + //получаем строку + //печатаем ее в ответ + + SerialPortClearRxBuffer(env->serialCommandPortIn); + vAsciiStringClean(env->rxLine.data, &env->rxLine.length); + + env->rxLine.length = SerialPortReceiveTo( + env->serialCommandPortIn, + (uint8_t *) env->rxLine.data, + env->rxLine.limit, + '\n', + delay + ); + + env->rxLine.begin = env->rxLine.data; + if (env->rxLine.length && (*(CliCmd_RxLineEnd(env) - 2) == '\n')) { + --env->rxLine.length; + } + CliCmd_Print(env, CliCmd_RxLineBegin(env), CliCmd_RxLineLength(env)); +} + +void CliCmd_ClearRx(tCliCmd *env) { + SerialPortClearRxBuffer(env->serialCommandPortIn); + vAsciiStringClean(env->rxLine.data, &env->rxLine.length); +} + +bool CliCmd_HasCompleteLine(tCliCmd *env) { + + env->rxLine.length = SerialPortReceiveTo( + env->serialCommandPortIn, + (uint8_t *) env->rxLine.begin, + env->rxLine.limit, + '\n', + 0 + ); + + env->rxLine.begin = env->rxLine.data; + if (env->rxLine.length && (*(CliCmd_RxLineEnd(env) - 2) == '\n')) { + --env->rxLine.length; + } + CliCmd_Print(env, CliCmd_RxLineBegin(env), CliCmd_RxLineLength(env)); + + return true; +} + +void CliCmd_Print(tCliCmd *cli, char *text, uint16_t len) { + +// SerialPortTransmit(cli->serialCommandPortOut, (uint8_t *) text, len, SystemWaitForever); + LoggerToSerialPort_Cmd(cli->loggerToSerialPort, text, len); + +} + +void CliCmd_PrintHex(tCliCmd *cli, uint8_t *data, uint16_t byteLen) { + char hexString[byteLen * 2]; + size_t len = 0; + vAsciiStringAddBytesAsHex(hexString, &len, data, byteLen); + CliCmd_Print(cli, hexString, len); +} + +char *CliCmd_RxLineBegin(tCliCmd *cli) { + return cli->rxLine.begin; +} + +char *CliCmd_RxLineEnd(tCliCmd *cli) { + return cli->rxLine.data + cli->rxLine.length; +} + +size_t CliCmd_RxLineLength(tCliCmd *cli) { + return CliCmd_RxLineEnd(cli) - CliCmd_RxLineBegin(cli); +} + +char *CliCmd_RxStartsWith(tCliCmd *cli, char *text, uint16_t len) { + //смотрим что у нас в начале буфера + return strnstr(CliCmd_RxLineBegin(cli), text, len); +} + +void CliCmd_RxSkipTo(tCliCmd *cli, char *next) { + if ((next < CliCmd_RxLineEnd(cli)) && (next > CliCmd_RxLineBegin(cli))) { + cli->rxLine.begin = next; + } +} + +void CliCmd_RxSkip(tCliCmd *cli, size_t len) { + cli->rxLine.begin += len; +} + +void CliCmd_RxSkipSpace(tCliCmd *cli) { + char *end = CliCmd_RxLineEnd(cli); + for (; cli->rxLine.begin < end && *cli->rxLine.begin == ' '; ++cli->rxLine.begin) {} +} diff --git a/MODULES/CliCmd/modular.json b/MODULES/CliCmd/modular.json new file mode 100644 index 0000000..cc313cc --- /dev/null +++ b/MODULES/CliCmd/modular.json @@ -0,0 +1,27 @@ +{ + "dep": [ + { + "type": "local", + + "dir": "./MODULES/SerialPort" + }, + { + "type": "local", + + "dir": "./MODULES/AsciiStringParsingUtils" + }, + { + "type": "local", + + "dir": "./MODULES/AsciiStringAssemblingUtils" + } + ], + "cmake": { + "inc_dirs": [ + "Inc" + ], + "srcs": [ + "Src/**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/CliCmd_RedirectTable/CliRedirectTable.c b/MODULES/CliCmd_RedirectTable/CliRedirectTable.c new file mode 100644 index 0000000..8e801ab --- /dev/null +++ b/MODULES/CliCmd_RedirectTable/CliRedirectTable.c @@ -0,0 +1,51 @@ +// +// Created by cfif on 15.11.22. +// +#include "CliRedirectTable.h" + + +bool CliRedirectionTable_RecAdd(tCliRedirectTable *baseTable, char *cmdStatic, uint8_t cmdLen, cliCall mtd, void *env) { + if (baseTable->count >= baseTable->itemsLimit) { + return false; + } + + baseTable->items[baseTable->count].cmd.data = cmdStatic; + baseTable->items[baseTable->count].cmd.length = cmdLen; + baseTable->items[baseTable->count].method = mtd; + baseTable->items[baseTable->count].env = env; + + ++baseTable->count; + return true; +} + + +void CliRedirectionTable_Init(tCliRedirectTable *baseTable, tCliRedirectItem *mem, uint16_t itemsLimit) { + baseTable->count = 0; + baseTable->itemsLimit = itemsLimit; + baseTable->items = mem; +} + +int32_t CliRedirectionTable_ProcessCmd(tCliRedirectTable *env, tCliCmd *cmd) { + for (uint16_t id = 0; id < env->count; ++id) { + tCliRedirectItem *item = env->items + id; + char *cmdName = CliCmd_RxStartsWith(cmd, item->cmd.data, item->cmd.length); + if (cmdName) { + CliCmd_RxSkip(cmd, item->cmd.length); + CliCmd_RxSkipSpace(cmd); + return item->method(item->env, cmd); + } + } + return -1; +} + +int32_t CliRedirectionTable_ListCmd(tCliRedirectTable *env, tCliCmd *cmd, char divider) { + for (uint16_t id = 0; id < env->count; ++id) { + tCliRedirectItem *item = env->items + id; + CliCmd_Print(cmd, item->cmd.data, item->cmd.length); + if (divider) { + CliCmd_Print(cmd, ÷r, 1); + } + } + return -1; +} + diff --git a/MODULES/CliCmd_RedirectTable/CliRedirectTable.h b/MODULES/CliCmd_RedirectTable/CliRedirectTable.h new file mode 100644 index 0000000..80379f4 --- /dev/null +++ b/MODULES/CliCmd_RedirectTable/CliRedirectTable.h @@ -0,0 +1,40 @@ +// +// Created by cfif on 11.11.22. +// + +#ifndef UVEOS_ON_NATION_CLIREDIRECTTABLE_H +#define UVEOS_ON_NATION_CLIREDIRECTTABLE_H + +#include +#include +#include "CliCmd.h" +#include "BaseTypes.h" + +typedef int32_t (*cliCall)(void *env, tCliCmd *cli); + +typedef struct { + tStringStatic cmd; + cliCall method; + void *env; +} tCliRedirectItem; + +typedef struct { + tCliRedirectItem *items; + uint16_t count; + uint16_t itemsLimit; +} tCliRedirectTable; + +void CliRedirectionTable_Init(tCliRedirectTable *baseTable, tCliRedirectItem *mem, uint16_t itemsLimit); + +#define CliRedirectionTable_InitStatic(TAB, MEM) CliRedirectionTable_Init(TAB,MEM,sizeof(MEM)/sizeof(tCliRedirectItem)) + +bool CliRedirectionTable_RecAdd(tCliRedirectTable *baseTable, char *cmdStatic, uint8_t cmdLen, cliCall mtd, void *env); + +#define CliRedirectionTable_RecAddStatic(TAB, CMD, CALL, ENV) CliRedirectionTable_RecAdd(TAB,CMD,sizeof (CMD)-1,CALL,ENV) + +int32_t CliRedirectionTable_ProcessCmd(tCliRedirectTable *env, tCliCmd *cmd); + +int32_t CliRedirectionTable_ListCmd(tCliRedirectTable *env, tCliCmd *cmd, char divider); + +#endif //UVEOS_ON_NATION_CLIREDIRECTTABLE_H + diff --git a/MODULES/CliCmd_RedirectTable/modular.json b/MODULES/CliCmd_RedirectTable/modular.json new file mode 100644 index 0000000..1520fc5 --- /dev/null +++ b/MODULES/CliCmd_RedirectTable/modular.json @@ -0,0 +1,23 @@ +{ + "dep": [ + { + "type": "local", + + "dir": "./MODULES/BaseTypes" + }, + { + "type": "local", + + "dir": "./MODULES/CliCmd" + } + ], + "cmake": { + "inc_dirs": [ + "./" + ], + "srcs": [ + "./**.c" + ] + } +} + diff --git a/MODULES/CmakeConfig_GCC_CortexM7/gcc_cm7.cmake b/MODULES/CmakeConfig_GCC_CortexM7/gcc_cm7.cmake new file mode 100644 index 0000000..6817c6f --- /dev/null +++ b/MODULES/CmakeConfig_GCC_CortexM7/gcc_cm7.cmake @@ -0,0 +1,50 @@ +#-- System --------------------------------------------------------------------- +SET(CMAKE_SYSTEM_NAME Generic) +SET(CMAKE_SYSTEM_PROCESSOR arm) + +#-- Toolchain ------------------------------------------------------------------ +SET(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) +IF(WIN32) + SET(TOOL_EXECUTABLE_SUFFIX ".exe") +ELSE() + SET(TOOL_EXECUTABLE_SUFFIX "") +ENDIF() +SET(CMAKE_C_COMPILER "arm-none-eabi-gcc${TOOL_EXECUTABLE_SUFFIX}") +SET(CMAKE_CXX_COMPILER "arm-none-eabi-g++${TOOL_EXECUTABLE_SUFFIX}") +SET(CMAKE_ASM_COMPILER "arm-none-eabi-gcc${TOOL_EXECUTABLE_SUFFIX}") +SET(CMAKE_OBJCOPY "arm-none-eabi-objcopy${TOOL_EXECUTABLE_SUFFIX}" CACHE STRING "objcopy tool") +SET(CMAKE_OBJDUMP "arm-none-eabi-objdump${TOOL_EXECUTABLE_SUFFIX}" CACHE STRING "objdump tool") +SET(CMAKE_SIZE "arm-none-eabi-size${TOOL_EXECUTABLE_SUFFIX}" CACHE STRING "size tool") + +#-- Common flags --------------------------------------------------------------- +SET(COMPILER_COMMON_FLAGS "-mthumb -mcpu=cortex-m7 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+SET(CMAKE_CXX_FLAGS_DEBUG "-g -Og -DDEBUG" CACHE STRING "c++ compiler flags debug") +SET(CMAKE_ASM_FLAGS_DEBUG "-g" CACHE STRING "assembler compiler flags debug") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG "" CACHE STRING "linker flags debug") + +#-- Release flags ---------------------------------------------------------------- +SET(CMAKE_C_FLAGS_RELEASE "-O2 " CACHE STRING "c compiler flags release") +SET(CMAKE_CXX_FLAGS_RELEASE "-O2" CACHE STRING "c++ compiler flags release") +SET(CMAKE_ASM_FLAGS_RELEASE "" CACHE STRING "assembler compiler flags release") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE "" CACHE STRING "linker flags release") + +#-- Release with debug info flags ---------------------------------------------------------------- +SET(CMAKE_C_FLAGS_RELWITHDEBINFO "-g -O2" CACHE STRING "c compiler flags release with debug info") +SET(CMAKE_CXX_FLAGS_RELWITHDEBINFO "-g -O2" CACHE STRING "c++ compiler flags release with debug info") +SET(CMAKE_ASM_FLAGS_RELWITHDEBINFO "" CACHE STRING "assembler compiler flags release with debug info") +SET(CMAKE_EXE_LINKER_FLAGS_RELWITHDEBINFO "" CACHE STRING "linker flags release with debug info") + +#-- Minimum size release flags ---------------------------------------------------------------- +SET(CMAKE_C_FLAGS_MINSIZEREL "-Os -flto -ffat-lto-objects" CACHE STRING "c compiler flags minimum size release") +SET(CMAKE_CXX_FLAGS_MINSIZEREL "-Os -flto -ffat-lto-objects" CACHE STRING "c++ compiler flags minimum size release") +SET(CMAKE_ASM_FLAGS_MINSIZEREL "" CACHE STRING "assembler compiler flags minimum size release") +SET(CMAKE_EXE_LINKER_FLAGS_MINSIZEREL "-flto" CACHE STRING "linker flags minimum size release") diff --git a/MODULES/CmakeConfig_GCC_CortexM7/gcc_cm7f.cmake b/MODULES/CmakeConfig_GCC_CortexM7/gcc_cm7f.cmake new file mode 100644 index 0000000..d4853b0 --- /dev/null +++ b/MODULES/CmakeConfig_GCC_CortexM7/gcc_cm7f.cmake @@ -0,0 +1,50 @@ +#-- System --------------------------------------------------------------------- +SET(CMAKE_SYSTEM_NAME Generic) +SET(CMAKE_SYSTEM_PROCESSOR arm) + +#-- Toolchain ------------------------------------------------------------------ +SET(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) +IF(WIN32) + SET(TOOL_EXECUTABLE_SUFFIX ".exe") +ELSE() + SET(TOOL_EXECUTABLE_SUFFIX "") +ENDIF() +SET(CMAKE_C_COMPILER "arm-none-eabi-gcc${TOOL_EXECUTABLE_SUFFIX}") +SET(CMAKE_CXX_COMPILER "arm-none-eabi-g++${TOOL_EXECUTABLE_SUFFIX}") +SET(CMAKE_ASM_COMPILER "arm-none-eabi-gcc${TOOL_EXECUTABLE_SUFFIX}") +SET(CMAKE_OBJCOPY "arm-none-eabi-objcopy${TOOL_EXECUTABLE_SUFFIX}" CACHE STRING "objcopy tool") +SET(CMAKE_OBJDUMP "arm-none-eabi-objdump${TOOL_EXECUTABLE_SUFFIX}" CACHE STRING "objdump tool") +SET(CMAKE_SIZE "arm-none-eabi-size${TOOL_EXECUTABLE_SUFFIX}" CACHE STRING "size tool") + +#-- Common flags --------------------------------------------------------------- +SET(COMPILER_COMMON_FLAGS "-mcpu=cortex-m7 -march=armv7e-m+fp -mthumb -mfloat-abi=hard -mfpu=fpv5-sp-d16 -Wall -Wextra -ffunction-sections -fdata-sections -mlong-calls -Wno-unused-function -Wno-unused-variable -Wno-unused-parameter -fno-builtin -fno-builtin-printf") +SET(CMAKE_C_FLAGS "${COMPILER_COMMON_FLAGS} -std=gnu99" CACHE STRING "c compiler flags") +SET(CMAKE_CXX_FLAGS "${COMPILER_COMMON_FLAGS} -std=c++11" CACHE STRING "c++ compiler flags") +SET(CMAKE_ASM_FLAGS "-mthumb -mcpu=cortex-m7" CACHE STRING "assembler compiler flags") +SET(CMAKE_EXE_LINKER_FLAGS "-mcpu=cortex-m7 -march=armv7e-m+fp -mthumb -mfloat-abi=hard -mfpu=fpv5-sp-d16 -mlong-calls -Wl,--gc-sections -specs=nosys.specs -specs=nano.specs -lgcc -lc" CACHE STRING "executable linker flags") +SET(CMAKE_MODULE_LINKER_FLAGS "-mcpu=cortex-m7 -march=armv7e-m+fp -mthumb -mfloat-abi=soft -mfpu=fpv5-sp-d16" CACHE STRING "module linker flags") +SET(CMAKE_SHARED_LINKER_FLAGS "-mcpu=cortex-m7 -march=armv7e-m+fp -mthumb -mfloat-abi=hard -mfpu=fpv5-sp-d16" CACHE STRING "shared linker flags") + +#-- Debug flags ---------------------------------------------------------------- +SET(CMAKE_C_FLAGS_DEBUG "-g -Og -DDEBUG" CACHE STRING "c compiler flags debug") +SET(CMAKE_CXX_FLAGS_DEBUG "-g -Og -DDEBUG" CACHE STRING "c++ compiler flags debug") +SET(CMAKE_ASM_FLAGS_DEBUG "-g" CACHE STRING "assembler compiler flags debug") +SET(CMAKE_EXE_LINKER_FLAGS_DEBUG "" CACHE STRING "linker flags debug") + +#-- Release flags ---------------------------------------------------------------- +SET(CMAKE_C_FLAGS_RELEASE "-O2 " CACHE STRING "c compiler flags release") +SET(CMAKE_CXX_FLAGS_RELEASE "-O2" CACHE STRING "c++ compiler flags release") +SET(CMAKE_ASM_FLAGS_RELEASE "" CACHE STRING "assembler compiler flags release") +SET(CMAKE_EXE_LINKER_FLAGS_RELEASE "" CACHE STRING "linker flags release") + +#-- Release with debug info flags ---------------------------------------------------------------- +SET(CMAKE_C_FLAGS_RELWITHDEBINFO "-g -O2" CACHE STRING "c compiler flags release with debug info") +SET(CMAKE_CXX_FLAGS_RELWITHDEBINFO "-g -O2" CACHE STRING "c++ compiler flags release with debug info") +SET(CMAKE_ASM_FLAGS_RELWITHDEBINFO "" CACHE STRING "assembler compiler flags release with debug info") +SET(CMAKE_EXE_LINKER_FLAGS_RELWITHDEBINFO "" CACHE STRING "linker flags release with debug info") + +#-- Minimum size release flags ---------------------------------------------------------------- +SET(CMAKE_C_FLAGS_MINSIZEREL "-Os -flto -ffat-lto-objects" CACHE STRING "c compiler flags minimum size release") +SET(CMAKE_CXX_FLAGS_MINSIZEREL "-Os -flto -ffat-lto-objects" CACHE STRING "c++ compiler flags minimum size release") +SET(CMAKE_ASM_FLAGS_MINSIZEREL "" CACHE STRING "assembler compiler flags minimum size release") +SET(CMAKE_EXE_LINKER_FLAGS_MINSIZEREL "-flto" CACHE STRING "linker flags minimum size release") diff --git a/MODULES/CmakeConfig_GCC_CortexM7/modular.json b/MODULES/CmakeConfig_GCC_CortexM7/modular.json new file mode 100644 index 0000000..28b6c64 --- /dev/null +++ b/MODULES/CmakeConfig_GCC_CortexM7/modular.json @@ -0,0 +1,8 @@ +{ + "cmake": { + "inc_dirs": [ + ], + "srcs": [ + ] + } +} \ No newline at end of file diff --git a/MODULES/CmakeConfig_RandomBuildIdGenerator/VersionRandID.h b/MODULES/CmakeConfig_RandomBuildIdGenerator/VersionRandID.h new file mode 100644 index 0000000..0b1f802 --- /dev/null +++ b/MODULES/CmakeConfig_RandomBuildIdGenerator/VersionRandID.h @@ -0,0 +1 @@ +#define VERSION_RANDOM_BUILD_IDENTIFIER "RPcyf" diff --git a/MODULES/CmakeConfig_RandomBuildIdGenerator/VersionRandID.h.in b/MODULES/CmakeConfig_RandomBuildIdGenerator/VersionRandID.h.in new file mode 100644 index 0000000..cf7f03a --- /dev/null +++ b/MODULES/CmakeConfig_RandomBuildIdGenerator/VersionRandID.h.in @@ -0,0 +1 @@ +#define VERSION_RANDOM_BUILD_IDENTIFIER "${VRS_BUILD_RND}" diff --git a/MODULES/CmakeConfig_RandomBuildIdGenerator/modular.json b/MODULES/CmakeConfig_RandomBuildIdGenerator/modular.json new file mode 100644 index 0000000..8802620 --- /dev/null +++ b/MODULES/CmakeConfig_RandomBuildIdGenerator/modular.json @@ -0,0 +1,10 @@ +{ + "cmake": { + "inc_dirs": [ + "./" + ], + "srcs": [ + + ] + } +} \ No newline at end of file diff --git a/MODULES/CmakeConfig_RandomBuildIdGenerator/version.cmake b/MODULES/CmakeConfig_RandomBuildIdGenerator/version.cmake new file mode 100755 index 0000000..649bd15 --- /dev/null +++ b/MODULES/CmakeConfig_RandomBuildIdGenerator/version.cmake @@ -0,0 +1,6 @@ +set(WORKING_DIRECTORY ${CMAKE_CURRENT_LIST_DIR}) + +string(RANDOM VRS_BUILD_RND) +configure_file(${WORKING_DIRECTORY}/VersionRandID.h.in ${WORKING_DIRECTORY}/VersionRandID.h) + +message(STATUS "New build identifier: " \"${VRS_BUILD_RND}\") \ No newline at end of file diff --git a/MODULES/CmsisRtosInterface/Inc/cmsis_os.h b/MODULES/CmsisRtosInterface/Inc/cmsis_os.h new file mode 100644 index 0000000..711408a --- /dev/null +++ b/MODULES/CmsisRtosInterface/Inc/cmsis_os.h @@ -0,0 +1,846 @@ +/* + * Copyright (c) 2013-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 10. January 2017 + * $Revision: V2.1.0 + * + * Project: CMSIS-RTOS API + * Title: cmsis_os.h FreeRTOS header file + * + * Version 0.02 + * Initial Proposal Phase + * Version 0.03 + * osKernelStart added, optional feature: main started as thread + * osSemaphores have standard behavior + * osTimerCreate does not start the timer, added osTimerStart + * osThreadPass is renamed to osThreadYield + * Version 1.01 + * Support for C++ interface + * - const attribute removed from the osXxxxDef_t typedefs + * - const attribute added to the osXxxxDef macros + * Added: osTimerDelete, osMutexDelete, osSemaphoreDelete + * Added: osKernelInitialize + * Version 1.02 + * Control functions for short timeouts in microsecond resolution: + * Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec + * Removed: osSignalGet + * Version 2.0.0 + * OS objects creation without macros (dynamic creation and resource allocation): + * - added: osXxxxNew functions which replace osXxxxCreate + * - added: osXxxxAttr_t structures + * - deprecated: osXxxxCreate functions, osXxxxDef_t structures + * - deprecated: osXxxxDef and osXxxx macros + * osStatus codes simplified and renamed to osStatus_t + * osEvent return structure deprecated + * Kernel: + * - added: osKernelInfo_t and osKernelGetInfo + * - added: osKernelState_t and osKernelGetState (replaces osKernelRunning) + * - added: osKernelLock, osKernelUnlock + * - added: osKernelSuspend, osKernelResume + * - added: osKernelGetTickCount, osKernelGetTickFreq + * - renamed osKernelSysTick to osKernelGetSysTimerCount + * - replaced osKernelSysTickFrequency with osKernelGetSysTimerFreq + * - deprecated osKernelSysTickMicroSec + * Thread: + * - extended number of thread priorities + * - renamed osPrioriry to osPrioriry_t + * - replaced osThreadCreate with osThreadNew + * - added: osThreadGetName + * - added: osThreadState_t and osThreadGetState + * - added: osThreadGetStackSize, osThreadGetStackSpace + * - added: osThreadSuspend, osThreadResume + * - added: osThreadJoin, osThreadDetach, osThreadExit + * - added: osThreadGetCount, osThreadEnumerate + * - added: Thread Flags (moved from Signals) + * Signals: + * - renamed osSignals to osThreadFlags (moved to Thread Flags) + * - changed return value of Set/Clear/Wait functions + * - Clear function limited to current running thread + * - extended Wait function (options) + * - added: osThreadFlagsGet + * Event Flags: + * - added new independent object for handling Event Flags + * Delay and Wait functions: + * - added: osDelayUntil + * - deprecated: osWait + * Timer: + * - replaced osTimerCreate with osTimerNew + * - added: osTimerGetName, osTimerIsRunning + * Mutex: + * - extended: attributes (Recursive, Priority Inherit, Robust) + * - replaced osMutexCreate with osMutexNew + * - renamed osMutexWait to osMutexAcquire + * - added: osMutexGetName, osMutexGetOwner + * Semaphore: + * - extended: maximum and initial token count + * - replaced osSemaphoreCreate with osSemaphoreNew + * - renamed osSemaphoreWait to osSemaphoreAcquire (changed return value) + * - added: osSemaphoreGetName, osSemaphoreGetCount + * Memory Pool: + * - using osMemoryPool prefix instead of osPool + * - replaced osPoolCreate with osMemoryPoolNew + * - extended osMemoryPoolAlloc (timeout) + * - added: osMemoryPoolGetName + * - added: osMemoryPoolGetCapacity, osMemoryPoolGetBlockSize + * - added: osMemoryPoolGetCount, osMemoryPoolGetSpace + * - added: osMemoryPoolDelete + * - deprecated: osPoolCAlloc + * Message Queue: + * - extended: fixed size message instead of a single 32-bit value + * - using osMessageQueue prefix instead of osMessage + * - replaced osMessageCreate with osMessageQueueNew + * - updated: osMessageQueuePut, osMessageQueueGet + * - added: osMessageQueueGetName + * - added: osMessageQueueGetCapacity, osMessageQueueGetMsgSize + * - added: osMessageQueueGetCount, osMessageQueueGetSpace + * - added: osMessageQueueReset, osMessageQueueDelete + * Mail Queue: + * - deprecated (superseded by extended Message Queue functionality) + * Version 2.1.0 + * Support for critical and uncritical sections (nesting safe): + * - updated: osKernelLock, osKernelUnlock + * - added: osKernelRestoreLock + * Updated Thread and Event Flags: + * - changed flags parameter and return type from int32_t to uint32_t + *---------------------------------------------------------------------------*/ + +#ifndef CMSIS_OS_H_ +#define CMSIS_OS_H_ + +#include "FreeRTOS.h" +#include "task.h" + +#define RTOS_ID_n ((tskKERNEL_VERSION_MAJOR << 16) | (tskKERNEL_VERSION_MINOR)) +#define RTOS_ID_s ("FreeRTOS " tskKERNEL_VERSION_NUMBER) + +#define osCMSIS 0x20001U ///< API version (main[31:16].sub[15:0]) + +#define osCMSIS_FreeRTOS RTOS_ID_n ///< RTOS identification and version (main[31:16].sub[15:0]) + +#define osKernelSystemId RTOS_ID_s ///< RTOS identification string + +#define osFeature_MainThread 0 ///< main thread 1=main can be thread, 0=not available +#define osFeature_Signals 24U ///< maximum number of Signal Flags available per thread +#define osFeature_Semaphore 65535U ///< maximum count for \ref osSemaphoreCreate function +#define osFeature_Wait 0 ///< osWait function: 1=available, 0=not available +#define osFeature_SysTick 1 ///< osKernelSysTick functions: 1=available, 0=not available +#define osFeature_Pool 0 ///< Memory Pools: 1=available, 0=not available +#define osFeature_MessageQ 1 ///< Message Queues: 1=available, 0=not available +#define osFeature_MailQ 0 ///< Mail Queues: 1=available, 0=not available + +#if defined(__CC_ARM) +#define os_InRegs __value_in_regs +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#define os_InRegs __attribute__((value_in_regs)) +#else +#define os_InRegs +#endif + +#include "cmsis_os2.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + +// ==== Enumerations, structures, defines ==== + +/// Priority values. +#if (osCMSIS < 0x20000U) +typedef enum { + osPriorityIdle = -3, ///< Priority: idle (lowest) + osPriorityLow = -2, ///< Priority: low + osPriorityBelowNormal = -1, ///< Priority: below normal + osPriorityNormal = 0, ///< Priority: normal (default) + osPriorityAboveNormal = +1, ///< Priority: above normal + osPriorityHigh = +2, ///< Priority: high + osPriorityRealtime = +3, ///< Priority: realtime (highest) + osPriorityError = 0x84, ///< System cannot determine priority or illegal priority. + osPriorityReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osPriority; +#else +#define osPriority osPriority_t +#endif + +/// Entry point of a thread. +typedef void (*os_pthread) (void const *argument); + +/// Entry point of a timer call back function. +typedef void (*os_ptimer) (void const *argument); + +/// Timer type. +#if (osCMSIS < 0x20000U) +typedef enum { + osTimerOnce = 0, ///< One-shot timer. + osTimerPeriodic = 1 ///< Repeating timer. +} os_timer_type; +#else +#define os_timer_type osTimerType_t +#endif + +/// Timeout value. +#define osWaitForever 0xFFFFFFFFU ///< Wait forever timeout value. + +/// Status code values returned by CMSIS-RTOS functions. +#if (osCMSIS < 0x20000U) +typedef enum { + osOK = 0, ///< Function completed; no error or event occurred. + osEventSignal = 0x08, ///< Function completed; signal event occurred. + osEventMessage = 0x10, ///< Function completed; message event occurred. + osEventMail = 0x20, ///< Function completed; mail event occurred. + osEventTimeout = 0x40, ///< Function completed; timeout occurred. + osErrorParameter = 0x80, ///< Parameter error: a mandatory parameter was missing or specified an incorrect object. + osErrorResource = 0x81, ///< Resource not available: a specified resource was not available. + osErrorTimeoutResource = 0xC1, ///< Resource not available within given time: a specified resource was not available within the timeout period. + osErrorISR = 0x82, ///< Not allowed in ISR context: the function cannot be called from interrupt service routines. + osErrorISRRecursive = 0x83, ///< Function called multiple times from ISR with same object. + osErrorPriority = 0x84, ///< System cannot determine priority or thread has illegal priority. + osErrorNoMemory = 0x85, ///< System is out of memory: it was impossible to allocate or reserve memory for the operation. + osErrorValue = 0x86, ///< Value of a parameter is out of range. + osErrorOS = 0xFF, ///< Unspecified RTOS error: run-time error but no other error message fits. + osStatusReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osStatus; +#else +typedef int32_t osStatus; +#define osEventSignal (0x08) +#define osEventMessage (0x10) +#define osEventMail (0x20) +#define osEventTimeout (0x40) +#define osErrorOS osError +#define osErrorTimeoutResource osErrorTimeout +#define osErrorISRRecursive (-126) +#define osErrorValue (-127) +#define osErrorPriority (-128) +#endif + + +// >>> the following data type definitions may be adapted towards a specific RTOS + +/// Thread ID identifies the thread. +#if (osCMSIS < 0x20000U) +typedef void *osThreadId; +#else +#define osThreadId osThreadId_t +#endif + +/// Timer ID identifies the timer. +#if (osCMSIS < 0x20000U) +typedef void *osTimerId; +#else +#define osTimerId osTimerId_t +#endif + +/// Mutex ID identifies the mutex. +#if (osCMSIS < 0x20000U) +typedef void *osMutexId; +#else +#define osMutexId osMutexId_t +#endif + +/// Semaphore ID identifies the semaphore. +#if (osCMSIS < 0x20000U) +typedef void *osSemaphoreId; +#else +#define osSemaphoreId osSemaphoreId_t +#endif + +/// Pool ID identifies the memory pool. +typedef void *osPoolId; + +/// Message ID identifies the message queue. +typedef void *osMessageQId; + +/// Mail ID identifies the mail queue. +typedef void *osMailQId; + + +/// Thread Definition structure contains startup information of a thread. +#if (osCMSIS < 0x20000U) +typedef struct os_thread_def { + os_pthread pthread; ///< start address of thread function + osPriority tpriority; ///< initial thread priority + uint32_t instances; ///< maximum number of instances of that thread function + uint32_t stacksize; ///< stack size requirements in bytes; 0 is default stack size +} osThreadDef_t; +#else +typedef struct os_thread_def { + os_pthread pthread; ///< start address of thread function + osThreadAttr_t attr; ///< thread attributes +} osThreadDef_t; +#endif + +/// Timer Definition structure contains timer parameters. +#if (osCMSIS < 0x20000U) +typedef struct os_timer_def { + os_ptimer ptimer; ///< start address of a timer function +} osTimerDef_t; +#else +typedef struct os_timer_def { + os_ptimer ptimer; ///< start address of a timer function + osTimerAttr_t attr; ///< timer attributes +} osTimerDef_t; +#endif + +/// Mutex Definition structure contains setup information for a mutex. +#if (osCMSIS < 0x20000U) +typedef struct os_mutex_def { + uint32_t dummy; ///< dummy value +} osMutexDef_t; +#else +#define osMutexDef_t osMutexAttr_t +#endif + +/// Semaphore Definition structure contains setup information for a semaphore. +#if (osCMSIS < 0x20000U) +typedef struct os_semaphore_def { + uint32_t dummy; ///< dummy value +} osSemaphoreDef_t; +#else +#define osSemaphoreDef_t osSemaphoreAttr_t +#endif + +/// Definition structure for memory block allocation. +#if (osCMSIS < 0x20000U) +typedef struct os_pool_def { + uint32_t pool_sz; ///< number of items (elements) in the pool + uint32_t item_sz; ///< size of an item + void *pool; ///< pointer to memory for pool +} osPoolDef_t; +#else +typedef struct os_pool_def { + uint32_t pool_sz; ///< number of items (elements) in the pool + uint32_t item_sz; ///< size of an item + osMemoryPoolAttr_t attr; ///< memory pool attributes +} osPoolDef_t; +#endif + +/// Definition structure for message queue. +#if (osCMSIS < 0x20000U) +typedef struct os_messageQ_def { + uint32_t queue_sz; ///< number of elements in the queue + void *pool; ///< memory array for messages +} osMessageQDef_t; +#else +typedef struct os_messageQ_def { + uint32_t queue_sz; ///< number of elements in the queue + osMessageQueueAttr_t attr; ///< message queue attributes +} osMessageQDef_t; +#endif + +/// Definition structure for mail queue. +#if (osCMSIS < 0x20000U) +typedef struct os_mailQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item + void *pool; ///< memory array for mail +} osMailQDef_t; +#else +typedef struct os_mailQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item + void *mail; ///< pointer to mail + osMemoryPoolAttr_t mp_attr; ///< memory pool attributes + osMessageQueueAttr_t mq_attr; ///< message queue attributes +} osMailQDef_t; +#endif + + +/// Event structure contains detailed information about an event. +typedef struct { + osStatus status; ///< status code: event or error information + union { + uint32_t v; ///< message as 32-bit value + void *p; ///< message or mail as void pointer + int32_t signals; ///< signal flags + } value; ///< event value + union { + osMailQId mail_id; ///< mail id obtained by \ref osMailCreate + osMessageQId message_id; ///< message id obtained by \ref osMessageCreate + } def; ///< event definition +} osEvent; + + +// ==== Kernel Management Functions ==== + +/// Initialize the RTOS Kernel for creating objects. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osKernelInitialize (void); +#endif + +/// Start the RTOS Kernel scheduler. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osKernelStart (void); +#endif + +/// Check if the RTOS kernel is already started. +/// \return 0 RTOS is not started, 1 RTOS is started. +#if (osCMSIS < 0x20000U) +int32_t osKernelRunning(void); +#endif + +#if (defined(osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available + +/// Get the RTOS kernel system timer counter. +/// \return RTOS kernel system timer as 32-bit value +#if (osCMSIS < 0x20000U) +uint32_t osKernelSysTick (void); +#else +#define osKernelSysTick osKernelGetSysTimerCount +#endif + +/// The RTOS kernel system timer frequency in Hz. +/// \note Reflects the system timer setting and is typically defined in a configuration file. +#if (osCMSIS < 0x20000U) +#define osKernelSysTickFrequency 100000000 +#endif + +/// Convert a microseconds value to a RTOS kernel system timer value. +/// \param microsec time value in microseconds. +/// \return time value normalized to the \ref osKernelSysTickFrequency +#if (osCMSIS < 0x20000U) +#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000) +#else +#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * osKernelGetSysTimerFreq()) / 1000000) +#endif + +#endif // System Timer available + + +// ==== Thread Management Functions ==== + +/// Create a Thread Definition with function, priority, and stack requirements. +/// \param name name of the thread function. +/// \param priority initial priority of the thread function. +/// \param instances number of possible thread instances. +/// \param stacksz stack size (in bytes) requirements for the thread function. +#if defined (osObjectsExternal) // object is external +#define osThreadDef(name, priority, instances, stacksz) \ +extern const osThreadDef_t os_thread_def_##name +#else // define the object +#define osThreadDef(name, priority, instances, stacksz) \ +static uint64_t os_thread_stack##name[(stacksz)?(((stacksz+7)/8)):1]; \ +static StaticTask_t os_thread_cb_##name; \ +const osThreadDef_t os_thread_def_##name = \ +{ (name), \ + { NULL, osThreadDetached, \ + (instances == 1) ? (&os_thread_cb_##name) : NULL,\ + (instances == 1) ? sizeof(StaticTask_t) : 0U, \ + ((stacksz) && (instances == 1)) ? (&os_thread_stack##name) : NULL, \ + 8*((stacksz+7)/8), \ + (priority), 0U, 0U } } +#endif + +/// Access a Thread definition. +/// \param name name of the thread definition object. +#define osThread(name) \ +&os_thread_def_##name + +/// Create a thread and add it to Active Threads and set it to state READY. +/// \param[in] thread_def thread definition referenced with \ref osThread. +/// \param[in] argument pointer that is passed to the thread function as start argument. +/// \return thread ID for reference by other functions or NULL in case of error. +osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument); + +/// Return the thread ID of the current running thread. +/// \return thread ID for reference by other functions or NULL in case of error. +#if (osCMSIS < 0x20000U) +osThreadId osThreadGetId (void); +#endif + +/// Change priority of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] priority new priority value for the thread function. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority); +#endif + +/// Get current priority of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return current priority value of the specified thread. +#if (osCMSIS < 0x20000U) +osPriority osThreadGetPriority (osThreadId thread_id); +#endif + +/// Pass control to next thread that is in state \b READY. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osThreadYield (void); +#endif + +/// Terminate execution of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osThreadTerminate (osThreadId thread_id); +#endif + + +// ==== Signal Management ==== + +/// Set the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that should be set. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. +int32_t osSignalSet (osThreadId thread_id, int32_t signals); + +/// Clear the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that shall be cleared. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR. +int32_t osSignalClear (osThreadId thread_id, int32_t signals); + +/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread. +/// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event flag information or error code. +os_InRegs osEvent osSignalWait (int32_t signals, uint32_t millisec); + + +// ==== Generic Wait Functions ==== + +/// Wait for Timeout (Time Delay). +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osDelay (uint32_t millisec); +#endif + +#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available + +/// Wait for Signal, Message, Mail, or Timeout. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out +/// \return event that contains signal, message, or mail information or error code. +os_InRegs osEvent osWait (uint32_t millisec); + +#endif // Generic Wait available + + +// ==== Timer Management Functions ==== + +/// Define a Timer object. +/// \param name name of the timer object. +/// \param function name of the timer call back function. +#if defined (osObjectsExternal) // object is external +#define osTimerDef(name, function) \ +extern const osTimerDef_t os_timer_def_##name +#else // define the object +#define osTimerDef(name, function) \ +static StaticTimer_t os_timer_cb_##name; \ +const osTimerDef_t os_timer_def_##name = \ +{ (function), { NULL, 0U, (&os_timer_cb_##name), sizeof(StaticTimer_t) } } +#endif + +/// Access a Timer definition. +/// \param name name of the timer object. +#define osTimer(name) \ +&os_timer_def_##name + +/// Create and Initialize a timer. +/// \param[in] timer_def timer object referenced with \ref osTimer. +/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior. +/// \param[in] argument argument to the timer call back function. +/// \return timer ID for reference by other functions or NULL in case of error. +osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument); + +/// Start or restart a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "time delay" value of the timer. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osTimerStart (osTimerId timer_id, uint32_t millisec); +#endif + +/// Stop a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osTimerStop (osTimerId timer_id); +#endif + +/// Delete a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osTimerDelete (osTimerId timer_id); +#endif + + +// ==== Mutex Management Functions ==== + +/// Define a Mutex. +/// \param name name of the mutex object. +#if defined (osObjectsExternal) // object is external +#define osMutexDef(name) \ +extern const osMutexDef_t os_mutex_def_##name +#else // define the object +#define osMutexDef(name) \ +static StaticSemaphore_t os_mutex_cb_##name; \ +const osMutexDef_t os_mutex_def_##name = \ +{ NULL, osMutexRecursive | osMutexPrioInherit, (&os_mutex_cb_##name), sizeof(StaticSemaphore_t) } +#endif + +/// Access a Mutex definition. +/// \param name name of the mutex object. +#define osMutex(name) \ +&os_mutex_def_##name + +/// Create and Initialize a Mutex object. +/// \param[in] mutex_def mutex definition referenced with \ref osMutex. +/// \return mutex ID for reference by other functions or NULL in case of error. +osMutexId osMutexCreate (const osMutexDef_t *mutex_def); + +/// Wait until a Mutex becomes available. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec); +#else +#define osMutexWait osMutexAcquire +#endif + +/// Release a Mutex that was obtained by \ref osMutexWait. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osMutexRelease (osMutexId mutex_id); +#endif + +/// Delete a Mutex object. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osMutexDelete (osMutexId mutex_id); +#endif + + +// ==== Semaphore Management Functions ==== + +#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0U)) // Semaphore available + +/// Define a Semaphore object. +/// \param name name of the semaphore object. +#if defined (osObjectsExternal) // object is external +#define osSemaphoreDef(name) \ +extern const osSemaphoreDef_t os_semaphore_def_##name +#else // define the object +#define osSemaphoreDef(name) \ +static StaticSemaphore_t os_semaphore_cb_##name; \ +const osSemaphoreDef_t os_semaphore_def_##name = \ +{ NULL, 0U, (&os_semaphore_cb_##name), sizeof(StaticSemaphore_t) } +#endif + +/// Access a Semaphore definition. +/// \param name name of the semaphore object. +#define osSemaphore(name) \ +&os_semaphore_def_##name + +/// Create and Initialize a Semaphore object. +/// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore. +/// \param[in] count maximum and initial number of available tokens. +/// \return semaphore ID for reference by other functions or NULL in case of error. +osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count); + +/// Wait until a Semaphore token becomes available. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return number of available tokens, or -1 in case of incorrect parameters. +int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); + +/// Release a Semaphore token. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osSemaphoreRelease (osSemaphoreId semaphore_id); +#endif + +/// Delete a Semaphore object. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \return status code that indicates the execution status of the function. +#if (osCMSIS < 0x20000U) +osStatus osSemaphoreDelete (osSemaphoreId semaphore_id); +#endif + +#endif // Semaphore available + + +// ==== Memory Pool Management Functions ==== + +#if (defined(osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool available + +/// \brief Define a Memory Pool. +/// \param name name of the memory pool. +/// \param no maximum number of blocks (objects) in the memory pool. +/// \param type data type of a single block (object). +#if defined (osObjectsExternal) // object is external +#define osPoolDef(name, no, type) \ +extern const osPoolDef_t os_pool_def_##name +#else // define the object +#define osPoolDef(name, no, type) \ +const osPoolDef_t os_pool_def_##name = \ +{ (no), sizeof(type), {NULL} } +#endif + +/// \brief Access a Memory Pool definition. +/// \param name name of the memory pool +#define osPool(name) \ +&os_pool_def_##name + +/// Create and Initialize a Memory Pool object. +/// \param[in] pool_def memory pool definition referenced with \ref osPool. +/// \return memory pool ID for reference by other functions or NULL in case of error. +osPoolId osPoolCreate (const osPoolDef_t *pool_def); + +/// Allocate a memory block from a Memory Pool. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +void *osPoolAlloc (osPoolId pool_id); + +/// Allocate a memory block from a Memory Pool and set memory block to zero. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +void *osPoolCAlloc (osPoolId pool_id); + +/// Return an allocated memory block back to a Memory Pool. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \param[in] block address of the allocated memory block to be returned to the memory pool. +/// \return status code that indicates the execution status of the function. +osStatus osPoolFree (osPoolId pool_id, void *block); + +#endif // Memory Pool available + + +// ==== Message Queue Management Functions ==== + +#if (defined(osFeature_MessageQ) && (osFeature_MessageQ != 0)) // Message Queue available + +/// \brief Create a Message Queue Definition. +/// \param name name of the queue. +/// \param queue_sz maximum number of messages in the queue. +/// \param type data type of a single message element (for debugger). +#if defined (osObjectsExternal) // object is external +#define osMessageQDef(name, queue_sz, type) \ +extern const osMessageQDef_t os_messageQ_def_##name +#else // define the object +#define osMessageQDef(name, queue_sz, type) \ +static StaticQueue_t os_mq_cb_##name; \ +static uint32_t os_mq_data_##name[(queue_sz) * sizeof(type)]; \ +const osMessageQDef_t os_messageQ_def_##name = \ +{ (queue_sz), \ + { NULL, 0U, (&os_mq_cb_##name), sizeof(StaticQueue_t), \ + (&os_mq_data_##name), sizeof(os_mq_data_##name) } } +#endif + +/// \brief Access a Message Queue Definition. +/// \param name name of the queue +#define osMessageQ(name) \ +&os_messageQ_def_##name + +/// Create and Initialize a Message Queue object. +/// \param[in] queue_def message queue definition referenced with \ref osMessageQ. +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return message queue ID for reference by other functions or NULL in case of error. +osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id); + +/// Put a Message to a Queue. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] info message information. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec); + +/// Get a Message from a Queue or timeout if Queue is empty. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event information that includes status code. +os_InRegs osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec); + +#endif // Message Queue available + + +// ==== Mail Queue Management Functions ==== + +#if (defined(osFeature_MailQ) && (osFeature_MailQ != 0)) // Mail Queue available + +/// \brief Create a Mail Queue Definition. +/// \param name name of the queue. +/// \param queue_sz maximum number of mails in the queue. +/// \param type data type of a single mail element. +#if defined (osObjectsExternal) // object is external +#define osMailQDef(name, queue_sz, type) \ +extern const osMailQDef_t os_mailQ_def_##name +#else // define the object +#define osMailQDef(name, queue_sz, type) \ +const osMailQDef_t os_mailQ_def_##name = \ +{ (queue_sz), sizeof(type), NULL } +#endif + +/// \brief Access a Mail Queue Definition. +/// \param name name of the queue +#define osMailQ(name) \ +&os_mailQ_def_##name + +/// Create and Initialize a Mail Queue object. +/// \param[in] queue_def mail queue definition referenced with \ref osMailQ. +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return mail queue ID for reference by other functions or NULL in case of error. +osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id); + +/// Allocate a memory block for mail from a mail memory pool. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case of error. +void *osMailAlloc (osMailQId queue_id, uint32_t millisec); + +/// Allocate a memory block for mail from a mail memory pool and set memory block to zero. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case of error. +void *osMailCAlloc (osMailQId queue_id, uint32_t millisec); + +/// Put a Mail into a Queue. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail pointer to memory with mail to put into a queue. +/// \return status code that indicates the execution status of the function. +osStatus osMailPut (osMailQId queue_id, const void *mail); + +/// Get a Mail from a Queue or timeout if Queue is empty. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event information that includes status code. +os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec); + +/// Free a memory block by returning it to a mail memory pool. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail pointer to memory block that was obtained with \ref osMailGet. +/// \return status code that indicates the execution status of the function. +osStatus osMailFree (osMailQId queue_id, void *mail); + +#endif // Mail Queue available + + +#ifdef __cplusplus +} +#endif + +#endif // CMSIS_OS_H_ diff --git a/MODULES/CmsisRtosInterface/Inc/cmsis_os2.h b/MODULES/CmsisRtosInterface/Inc/cmsis_os2.h new file mode 100644 index 0000000..61d1b1f --- /dev/null +++ b/MODULES/CmsisRtosInterface/Inc/cmsis_os2.h @@ -0,0 +1,736 @@ +/* -------------------------------------------------------------------------- + * Portions Copyright © 2017 STMicroelectronics International N.V. All rights reserved. + * Portions Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * -------------------------------------------------------------------------- + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: cmsis_os2.h + * Purpose: CMSIS RTOS2 wrapper for FreeRTOS + * + *---------------------------------------------------------------------------*/ + +#ifndef CMSIS_OS2_H_ +#define CMSIS_OS2_H_ + +#ifndef __NO_RETURN +#if defined(__CC_ARM) +#define __NO_RETURN __declspec(noreturn) +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#define __NO_RETURN __attribute__((__noreturn__)) +#elif defined(__GNUC__) +#define __NO_RETURN __attribute__((__noreturn__)) +#elif defined(__ICCARM__) +#define __NO_RETURN __noreturn +#else +#define __NO_RETURN +#endif +#endif + +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + + +// ==== Enumerations, structures, defines ==== + +/// Version information. +typedef struct { + uint32_t api; ///< API version (major.minor.rev: mmnnnrrrr dec). + uint32_t kernel; ///< Kernel version (major.minor.rev: mmnnnrrrr dec). +} osVersion_t; + +/// Kernel state. +typedef enum { + osKernelInactive = 0, ///< Inactive. + osKernelReady = 1, ///< Ready. + osKernelRunning = 2, ///< Running. + osKernelLocked = 3, ///< Locked. + osKernelSuspended = 4, ///< Suspended. + osKernelError = -1, ///< Error. + osKernelReserved = 0x7FFFFFFFU ///< Prevents enum down-size compiler optimization. +} osKernelState_t; + +/// Thread state. +typedef enum { + osThreadInactive = 0, ///< Inactive. + osThreadReady = 1, ///< Ready. + osThreadRunning = 2, ///< Running. + osThreadBlocked = 3, ///< Blocked. + osThreadTerminated = 4, ///< Terminated. + osThreadError = -1, ///< Error. + osThreadReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osThreadState_t; + +/// Priority values. +typedef enum { + osPriorityNone = 0, ///< No priority (not initialized). + osPriorityIdle = 1, ///< Reserved for Idle thread. + osPriorityLow = 8, ///< Priority: low + osPriorityLow1 = 8+1, ///< Priority: low + 1 + osPriorityLow2 = 8+2, ///< Priority: low + 2 + osPriorityLow3 = 8+3, ///< Priority: low + 3 + osPriorityLow4 = 8+4, ///< Priority: low + 4 + osPriorityLow5 = 8+5, ///< Priority: low + 5 + osPriorityLow6 = 8+6, ///< Priority: low + 6 + osPriorityLow7 = 8+7, ///< Priority: low + 7 + osPriorityBelowNormal = 16, ///< Priority: below normal + osPriorityBelowNormal1 = 16+1, ///< Priority: below normal + 1 + osPriorityBelowNormal2 = 16+2, ///< Priority: below normal + 2 + osPriorityBelowNormal3 = 16+3, ///< Priority: below normal + 3 + osPriorityBelowNormal4 = 16+4, ///< Priority: below normal + 4 + osPriorityBelowNormal5 = 16+5, ///< Priority: below normal + 5 + osPriorityBelowNormal6 = 16+6, ///< Priority: below normal + 6 + osPriorityBelowNormal7 = 16+7, ///< Priority: below normal + 7 + osPriorityNormal = 24, ///< Priority: normal + osPriorityNormal1 = 24+1, ///< Priority: normal + 1 + osPriorityNormal2 = 24+2, ///< Priority: normal + 2 + osPriorityNormal3 = 24+3, ///< Priority: normal + 3 + osPriorityNormal4 = 24+4, ///< Priority: normal + 4 + osPriorityNormal5 = 24+5, ///< Priority: normal + 5 + osPriorityNormal6 = 24+6, ///< Priority: normal + 6 + osPriorityNormal7 = 24+7, ///< Priority: normal + 7 + osPriorityAboveNormal = 32, ///< Priority: above normal + osPriorityAboveNormal1 = 32+1, ///< Priority: above normal + 1 + osPriorityAboveNormal2 = 32+2, ///< Priority: above normal + 2 + osPriorityAboveNormal3 = 32+3, ///< Priority: above normal + 3 + osPriorityAboveNormal4 = 32+4, ///< Priority: above normal + 4 + osPriorityAboveNormal5 = 32+5, ///< Priority: above normal + 5 + osPriorityAboveNormal6 = 32+6, ///< Priority: above normal + 6 + osPriorityAboveNormal7 = 32+7, ///< Priority: above normal + 7 + osPriorityHigh = 40, ///< Priority: high + osPriorityHigh1 = 40+1, ///< Priority: high + 1 + osPriorityHigh2 = 40+2, ///< Priority: high + 2 + osPriorityHigh3 = 40+3, ///< Priority: high + 3 + osPriorityHigh4 = 40+4, ///< Priority: high + 4 + osPriorityHigh5 = 40+5, ///< Priority: high + 5 + osPriorityHigh6 = 40+6, ///< Priority: high + 6 + osPriorityHigh7 = 40+7, ///< Priority: high + 7 + osPriorityRealtime = 48, ///< Priority: realtime + osPriorityRealtime1 = 48+1, ///< Priority: realtime + 1 + osPriorityRealtime2 = 48+2, ///< Priority: realtime + 2 + osPriorityRealtime3 = 48+3, ///< Priority: realtime + 3 + osPriorityRealtime4 = 48+4, ///< Priority: realtime + 4 + osPriorityRealtime5 = 48+5, ///< Priority: realtime + 5 + osPriorityRealtime6 = 48+6, ///< Priority: realtime + 6 + osPriorityRealtime7 = 48+7, ///< Priority: realtime + 7 + osPriorityISR = 56, ///< Reserved for ISR deferred thread. + osPriorityError = -1, ///< System cannot determine priority or illegal priority. + osPriorityReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osPriority_t; + +/// Entry point of a thread. +typedef void (*osThreadFunc_t) (void *argument); + +/// Timer callback function. +typedef void (*osTimerFunc_t) (void *argument); + +/// Timer type. +typedef enum { + osTimerOnce = 0, ///< One-shot timer. + osTimerPeriodic = 1 ///< Repeating timer. +} osTimerType_t; + +// Timeout value. +#define osWaitForever 0xFFFFFFFFU ///< Wait forever timeout value. + +// Flags options (\ref osThreadFlagsWait and \ref osEventFlagsWait). +#define osFlagsWaitAny 0x00000000U ///< Wait for any flag (default). +#define osFlagsWaitAll 0x00000001U ///< Wait for all flags. +#define osFlagsNoClear 0x00000002U ///< Do not clear flags which have been specified to wait for. + +// Flags errors (returned by osThreadFlagsXxxx and osEventFlagsXxxx). +#define osFlagsError 0x80000000U ///< Error indicator. +#define osFlagsErrorUnknown 0xFFFFFFFFU ///< osError (-1). +#define osFlagsErrorTimeout 0xFFFFFFFEU ///< osErrorTimeout (-2). +#define osFlagsErrorResource 0xFFFFFFFDU ///< osErrorResource (-3). +#define osFlagsErrorParameter 0xFFFFFFFCU ///< osErrorParameter (-4). +#define osFlagsErrorISR 0xFFFFFFFAU ///< osErrorISR (-6). + +// Thread attributes (attr_bits in \ref osThreadAttr_t). +#define osThreadDetached 0x00000000U ///< Thread created in detached mode (default) +#define osThreadJoinable 0x00000001U ///< Thread created in joinable mode + +// Mutex attributes (attr_bits in \ref osMutexAttr_t). +#define osMutexRecursive 0x00000001U ///< Recursive mutex. +#define osMutexPrioInherit 0x00000002U ///< Priority inherit protocol. +#define osMutexRobust 0x00000008U ///< Robust mutex. + +/// Status code values returned by CMSIS-RTOS functions. +typedef enum { + osOK = 0, ///< Operation completed successfully. + osError = -1, ///< Unspecified RTOS error: run-time error but no other error message fits. + osErrorTimeout = -2, ///< Operation not completed within the timeout period. + osErrorResource = -3, ///< Resource not available. + osErrorParameter = -4, ///< Parameter error. + osErrorNoMemory = -5, ///< System is out of memory: it was impossible to allocate or reserve memory for the operation. + osErrorISR = -6, ///< Not allowed in ISR context: the function cannot be called from interrupt service routines. + osStatusReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osStatus_t; + + +/// \details Thread ID identifies the thread. +typedef void *osThreadId_t; + +/// \details Timer ID identifies the timer. +typedef void *osTimerId_t; + +/// \details Event Flags ID identifies the event flags. +typedef void *osEventFlagsId_t; + +/// \details Mutex ID identifies the mutex. +typedef void *osMutexId_t; + +/// \details Semaphore ID identifies the semaphore. +typedef void *osSemaphoreId_t; + +/// \details Memory Pool ID identifies the memory pool. +typedef void *osMemoryPoolId_t; + +/// \details Message Queue ID identifies the message queue. +typedef void *osMessageQueueId_t; + + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + + +/// Attributes structure for thread. +typedef struct { + const char *name; ///< name of the thread + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block + void *stack_mem; ///< memory for stack + uint32_t stack_size; ///< size of stack + osPriority_t priority; ///< initial thread priority (default: osPriorityNormal) + TZ_ModuleId_t tz_module; ///< TrustZone module identifier + uint32_t reserved; ///< reserved (must be 0) + uint8_t pinToCore; + uint8_t core; +} osThreadAttr_t; + +/// Attributes structure for timer. +typedef struct { + const char *name; ///< name of the timer + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osTimerAttr_t; + +/// Attributes structure for event flags. +typedef struct { + const char *name; ///< name of the event flags + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osEventFlagsAttr_t; + +/// Attributes structure for mutex. +typedef struct { + const char *name; ///< name of the mutex + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osMutexAttr_t; + +/// Attributes structure for semaphore. +typedef struct { + const char *name; ///< name of the semaphore + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block +} osSemaphoreAttr_t; + +/// Attributes structure for memory pool. +typedef struct { + const char *name; ///< name of the memory pool + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block + void *mp_mem; ///< memory for data storage + uint32_t mp_size; ///< size of provided memory for data storage +} osMemoryPoolAttr_t; + +/// Attributes structure for message queue. +typedef struct { + const char *name; ///< name of the message queue + uint32_t attr_bits; ///< attribute bits + void *cb_mem; ///< memory for control block + uint32_t cb_size; ///< size of provided memory for control block + void *mq_mem; ///< memory for data storage + uint32_t mq_size; ///< size of provided memory for data storage +} osMessageQueueAttr_t; + + +// ==== Kernel Management Functions ==== + +/// Initialize the RTOS Kernel. +/// \return status code that indicates the execution status of the function. +osStatus_t osKernelInitialize (void); + +/// Get RTOS Kernel Information. +/// \param[out] version pointer to buffer for retrieving version information. +/// \param[out] id_buf pointer to buffer for retrieving kernel identification string. +/// \param[in] id_size size of buffer for kernel identification string. +/// \return status code that indicates the execution status of the function. +osStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size); + +/// Get the current RTOS Kernel state. +/// \return current RTOS Kernel state. +osKernelState_t osKernelGetState (void); + +/// Start the RTOS Kernel scheduler. +/// \return status code that indicates the execution status of the function. +osStatus_t osKernelStart (void); + +/// Lock the RTOS Kernel scheduler. +/// \return previous lock state (1 - locked, 0 - not locked, error code if negative). +int32_t osKernelLock (void); + +/// Unlock the RTOS Kernel scheduler. +/// \return previous lock state (1 - locked, 0 - not locked, error code if negative). +int32_t osKernelUnlock (void); + +/// Restore the RTOS Kernel scheduler lock state. +/// \param[in] lock lock state obtained by \ref osKernelLock or \ref osKernelUnlock. +/// \return new lock state (1 - locked, 0 - not locked, error code if negative). +int32_t osKernelRestoreLock (int32_t lock); + +/// Suspend the RTOS Kernel scheduler. +/// \return time in ticks, for how long the system can sleep or power-down. +uint32_t osKernelSuspend (void); + +/// Resume the RTOS Kernel scheduler. +/// \param[in] sleep_ticks time in ticks for how long the system was in sleep or power-down mode. +void osKernelResume (uint32_t sleep_ticks); + +/// Get the RTOS kernel tick count. +/// \return RTOS kernel current tick count. +uint32_t osKernelGetTickCount (void); + +/// Get the RTOS kernel tick frequency. +/// \return frequency of the kernel tick in hertz, i.e. kernel ticks per second. +uint32_t osKernelGetTickFreq (void); + +/// Get the RTOS kernel system timer count. +/// \return RTOS kernel current system timer count as 32-bit value. +uint32_t osKernelGetSysTimerCount (void); + +/// Get the RTOS kernel system timer frequency. +/// \return frequency of the system timer in hertz, i.e. timer ticks per second. +uint32_t osKernelGetSysTimerFreq (void); + + +// ==== Thread Management Functions ==== + +/// Create a thread and add it to Active Threads. +/// \param[in] func thread function. +/// \param[in] argument pointer that is passed to the thread function as start argument. +/// \param[in] attr thread attributes; NULL: default values. +/// \return thread ID for reference by other functions or NULL in case of error. +osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr); + +/// Get name of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return name as NULL terminated string. +const char *osThreadGetName (osThreadId_t thread_id); + +/// Return the thread ID of the current running thread. +/// \return thread ID for reference by other functions or NULL in case of error. +osThreadId_t osThreadGetId (void); + +/// Get current thread state of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return current thread state of the specified thread. +osThreadState_t osThreadGetState (osThreadId_t thread_id); + +/// Get stack size of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return stack size in bytes. +uint32_t osThreadGetStackSize (osThreadId_t thread_id); + +/// Get available stack space of a thread based on stack watermark recording during execution. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return remaining stack space in bytes. +uint32_t osThreadGetStackSpace (osThreadId_t thread_id); + +/// Change priority of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \param[in] priority new priority value for the thread function. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority); + +/// Get current priority of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return current priority value of the specified thread. +osPriority_t osThreadGetPriority (osThreadId_t thread_id); + +/// Pass control to next thread that is in state \b READY. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadYield (void); + +/// Suspend execution of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadSuspend (osThreadId_t thread_id); + +/// Resume execution of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadResume (osThreadId_t thread_id); + +/// Detach a thread (thread storage can be reclaimed when thread terminates). +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadDetach (osThreadId_t thread_id); + +/// Wait for specified thread to terminate. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadJoin (osThreadId_t thread_id); + +/// Terminate execution of current running thread. +__NO_RETURN void osThreadExit (void); + +/// Terminate execution of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +osStatus_t osThreadTerminate (osThreadId_t thread_id); + +/// Get number of active threads. +/// \return number of active threads. +uint32_t osThreadGetCount (void); + +/// Enumerate active threads. +/// \param[out] thread_array pointer to array for retrieving thread IDs. +/// \param[in] array_items maximum number of items in array for retrieving thread IDs. +/// \return number of enumerated threads. +uint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items); + + +// ==== Thread Flags Functions ==== + +/// Set the specified Thread Flags of a thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadNew or \ref osThreadGetId. +/// \param[in] flags specifies the flags of the thread that shall be set. +/// \return thread flags after setting or error code if highest bit set. +uint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags); + +/// Clear the specified Thread Flags of current running thread. +/// \param[in] flags specifies the flags of the thread that shall be cleared. +/// \return thread flags before clearing or error code if highest bit set. +uint32_t osThreadFlagsClear (uint32_t flags); + +/// Get the current Thread Flags of current running thread. +/// \return current thread flags. +uint32_t osThreadFlagsGet (void); + +/// Wait for one or more Thread Flags of the current running thread to become signaled. +/// \param[in] flags specifies the flags to wait for. +/// \param[in] options specifies flags options (osFlagsXxxx). +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return thread flags before clearing or error code if highest bit set. +uint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout); + + +// ==== Generic Wait Functions ==== + +/// Wait for Timeout (Time Delay). +/// \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value +/// \return status code that indicates the execution status of the function. +osStatus_t osDelay (uint32_t ticks); + +/// Wait until specified time. +/// \param[in] ticks absolute time in ticks +/// \return status code that indicates the execution status of the function. +osStatus_t osDelayUntil (uint32_t ticks); + + +// ==== Timer Management Functions ==== + +/// Create and Initialize a timer. +/// \param[in] func function pointer to callback function. +/// \param[in] type \ref osTimerOnce for one-shot or \ref osTimerPeriodic for periodic behavior. +/// \param[in] argument argument to the timer callback function. +/// \param[in] attr timer attributes; NULL: default values. +/// \return timer ID for reference by other functions or NULL in case of error. +osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr); + +/// Get name of a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return name as NULL terminated string. +const char *osTimerGetName (osTimerId_t timer_id); + +/// Start or restart a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \param[in] ticks \ref CMSIS_RTOS_TimeOutValue "time ticks" value of the timer. +/// \return status code that indicates the execution status of the function. +osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks); + +/// Stop a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osTimerStop (osTimerId_t timer_id); + +/// Check if a timer is running. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return 0 not running, 1 running. +uint32_t osTimerIsRunning (osTimerId_t timer_id); + +/// Delete a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osTimerDelete (osTimerId_t timer_id); + + +// ==== Event Flags Management Functions ==== + +/// Create and Initialize an Event Flags object. +/// \param[in] attr event flags attributes; NULL: default values. +/// \return event flags ID for reference by other functions or NULL in case of error. +osEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr); + +/// Get name of an Event Flags object. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \return name as NULL terminated string. +const char *osEventFlagsGetName (osEventFlagsId_t ef_id); + +/// Set the specified Event Flags. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \param[in] flags specifies the flags that shall be set. +/// \return event flags after setting or error code if highest bit set. +uint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags); + +/// Clear the specified Event Flags. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \param[in] flags specifies the flags that shall be cleared. +/// \return event flags before clearing or error code if highest bit set. +uint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags); + +/// Get the current Event Flags. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \return current event flags. +uint32_t osEventFlagsGet (osEventFlagsId_t ef_id); + +/// Wait for one or more Event Flags to become signaled. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \param[in] flags specifies the flags to wait for. +/// \param[in] options specifies flags options (osFlagsXxxx). +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return event flags before clearing or error code if highest bit set. +uint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout); + +/// Delete an Event Flags object. +/// \param[in] ef_id event flags ID obtained by \ref osEventFlagsNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id); + + +// ==== Mutex Management Functions ==== + +/// Create and Initialize a Mutex object. +/// \param[in] attr mutex attributes; NULL: default values. +/// \return mutex ID for reference by other functions or NULL in case of error. +osMutexId_t osMutexNew (const osMutexAttr_t *attr); + +/// Get name of a Mutex object. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return name as NULL terminated string. +const char *osMutexGetName (osMutexId_t mutex_id); + +/// Acquire a Mutex or timeout if it is locked. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout); + +/// Release a Mutex that was acquired by \ref osMutexAcquire. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMutexRelease (osMutexId_t mutex_id); + +/// Get Thread which owns a Mutex object. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return thread ID of owner thread or NULL when mutex was not acquired. +osThreadId_t osMutexGetOwner (osMutexId_t mutex_id); + +/// Delete a Mutex object. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMutexDelete (osMutexId_t mutex_id); + + +// ==== Semaphore Management Functions ==== + +/// Create and Initialize a Semaphore object. +/// \param[in] max_count maximum number of available tokens. +/// \param[in] initial_count initial number of available tokens. +/// \param[in] attr semaphore attributes; NULL: default values. +/// \return semaphore ID for reference by other functions or NULL in case of error. +osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr); + +/// Get name of a Semaphore object. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return name as NULL terminated string. +const char *osSemaphoreGetName (osSemaphoreId_t semaphore_id); + +/// Acquire a Semaphore token or timeout if no tokens are available. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout); + +/// Release a Semaphore token up to the initial maximum count. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id); + +/// Get current Semaphore token count. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return number of tokens available. +uint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id); + +/// Delete a Semaphore object. +/// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id); + + +// ==== Memory Pool Management Functions ==== + +/// Create and Initialize a Memory Pool object. +/// \param[in] block_count maximum number of memory blocks in memory pool. +/// \param[in] block_size memory block size in bytes. +/// \param[in] attr memory pool attributes; NULL: default values. +/// \return memory pool ID for reference by other functions or NULL in case of error. +osMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr); + +/// Get name of a Memory Pool object. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return name as NULL terminated string. +const char *osMemoryPoolGetName (osMemoryPoolId_t mp_id); + +/// Allocate a memory block from a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return address of the allocated memory block or NULL in case of no memory is available. +void *osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout); + +/// Return an allocated memory block back to a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \param[in] block address of the allocated memory block to be returned to the memory pool. +/// \return status code that indicates the execution status of the function. +osStatus_t osMemoryPoolFree (osMemoryPoolId_t mp_id, void *block); + +/// Get maximum number of memory blocks in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return maximum number of memory blocks. +uint32_t osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id); + +/// Get memory block size in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return memory block size in bytes. +uint32_t osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id); + +/// Get number of memory blocks used in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return number of memory blocks used. +uint32_t osMemoryPoolGetCount (osMemoryPoolId_t mp_id); + +/// Get number of memory blocks available in a Memory Pool. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return number of memory blocks available. +uint32_t osMemoryPoolGetSpace (osMemoryPoolId_t mp_id); + +/// Delete a Memory Pool object. +/// \param[in] mp_id memory pool ID obtained by \ref osMemoryPoolNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMemoryPoolDelete (osMemoryPoolId_t mp_id); + + +// ==== Message Queue Management Functions ==== + +/// Create and Initialize a Message Queue object. +/// \param[in] msg_count maximum number of messages in queue. +/// \param[in] msg_size maximum message size in bytes. +/// \param[in] attr message queue attributes; NULL: default values. +/// \return message queue ID for reference by other functions or NULL in case of error. +osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr); + +/// Get name of a Message Queue object. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return name as NULL terminated string. +const char *osMessageQueueGetName (osMessageQueueId_t mq_id); + +/// Put a Message into a Queue or timeout if Queue is full. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \param[in] msg_ptr pointer to buffer with message to put into a queue. +/// \param[in] msg_prio message priority. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout); + +/// Get a Message from a Queue or timeout if Queue is empty. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \param[out] msg_ptr pointer to buffer for message to get from a queue. +/// \param[out] msg_prio pointer to buffer for message priority or NULL. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout); + +/// Get maximum number of messages in a Message Queue. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return maximum number of messages. +uint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id); + +/// Get maximum message size in a Memory Pool. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return maximum message size in bytes. +uint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id); + +/// Get number of queued messages in a Message Queue. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return number of queued messages. +uint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id); + +/// Get number of available slots for messages in a Message Queue. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return number of available slots for messages. +uint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id); + +/// Reset a Message Queue to initial empty state. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueueReset (osMessageQueueId_t mq_id); + +/// Delete a Message Queue object. +/// \param[in] mq_id message queue ID obtained by \ref osMessageQueueNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id); + + +#ifdef __cplusplus +} +#endif + +#endif // CMSIS_OS2_H_ diff --git a/MODULES/CmsisRtosInterface/modular.json b/MODULES/CmsisRtosInterface/modular.json new file mode 100644 index 0000000..9bdd478 --- /dev/null +++ b/MODULES/CmsisRtosInterface/modular.json @@ -0,0 +1,7 @@ +{ + "cmake": { + "inc_dirs": [ + "Inc" + ] + } +} \ No newline at end of file diff --git a/MODULES/CmsisRtosThreadUtils/CmsisRtosThreadUtils.c b/MODULES/CmsisRtosThreadUtils/CmsisRtosThreadUtils.c new file mode 100644 index 0000000..a9d6192 --- /dev/null +++ b/MODULES/CmsisRtosThreadUtils/CmsisRtosThreadUtils.c @@ -0,0 +1,74 @@ +// +// Created by CFIF on 23.11.22. +// + +#include "CmsisRtosThreadUtils.h" + +void InitThreadAtr( + osThreadAttr_t *attr, + const char *name, ///< name of the thread + + void *cb_mem, ///< memory for control block + uint32_t cb_size, ///< size of provided memory for control block + + void *stack_mem, ///< memory for stack + uint32_t stack_size, ///< size of stack + + osPriority_t priority ///< initial thread priority (default: osPriorityNormal) +) { + + attr->name = name; + + attr->cb_mem = cb_mem; + attr->cb_size = cb_size; + + attr->stack_mem = stack_mem; + attr->stack_size = stack_size; + + attr->priority = priority; + + attr->tz_module = 0; + attr->reserved = 0; +} + +void InitQueueAtr( + osMessageQueueAttr_t *attr, + const char *name, ///< name of the thread + + void *cb_mem, ///< memory for control block + uint32_t cb_size, ///< size of provided memory for control block + + void *mem, ///< memory for data + uint32_t mem_size ///< size of mem +) { + + attr->name = name; + + attr->cb_mem = cb_mem; + attr->cb_size = cb_size; + + attr->mq_mem = mem; + attr->mq_size = mem_size; +} + +void utils_thread_block_start(void *env, osThreadId_t *id, osThreadAttr_t *attr, osThreadFunc_t func) { + if (!*id) { + *id = osThreadNew((osThreadFunc_t) func, (void *) (env), attr); + } else { + osThreadResume(*id); + } +} + +void utils_thread_block_pause(osThreadId_t id) { + if (id) { + osThreadSuspend(id); + } +} + +void utils_thread_block_stop(osThreadId_t *id) { + if (*id) { + if (osThreadTerminate(*id) == osOK) { + *id = NULL; + } + } +} \ No newline at end of file diff --git a/MODULES/CmsisRtosThreadUtils/CmsisRtosThreadUtils.h b/MODULES/CmsisRtosThreadUtils/CmsisRtosThreadUtils.h new file mode 100644 index 0000000..167243d --- /dev/null +++ b/MODULES/CmsisRtosThreadUtils/CmsisRtosThreadUtils.h @@ -0,0 +1,75 @@ +// +// Created by CFIF on 08.09.22. +// + +#ifndef CMSISRTOSTHREADSUTILS_CMSISRTOSTHREADSUTILS_H +#define CMSISRTOSTHREADSUTILS_CMSISRTOSTHREADSUTILS_H + +#include "cmsis_os.h" + +typedef struct { + osThreadId_t id; + StaticTask_t controlBlock; +} tThreadData; + +#define tStaticThreadBlock(WORDS_LEN) struct { osThreadId_t id; osThreadAttr_t attr; StaticTask_t controlBlock; uint32_t stack[WORDS_LEN]; } +#define tStaticThreadDynBlock struct { osThreadId_t id; osThreadAttr_t attr; } + +#define THREAD_ATTR_CREATE(PRIORITY, TASK_NAME) osThreadAttr_t TASK_NAME##TaskAttr ={ \ + .name = #TASK_NAME, \ + .cb_mem = &threads.TASK_NAME.controlBlock, \ + .cb_size = sizeof(threads.TASK_NAME.controlBlock), \ + \ + .stack_mem = &threadsBuffers.TASK_NAME[0], \ + .stack_size = sizeof(threadsBuffers.TASK_NAME), \ + \ + .priority = (osPriority_t) (PRIORITY) \ +} + +#define THREAD_ADD(THREAD_NAME, ENV, FUNC) threads.THREAD_NAME.id = osThreadNew((osThreadFunc_t)(FUNC), (void *) (ENV), &THREAD_NAME##TaskAttr) + + +void InitThreadAtr( + osThreadAttr_t *attr, + const char *name, ///< name of the thread + + void *cb_mem, ///< memory for control block + uint32_t cb_size, ///< size of provided memory for control block + + void *stack_mem, ///< memory for stack + uint32_t stack_size, ///< size of stack + + osPriority_t priority ///< initial thread priority (default: osPriorityNormal) +); + +void InitQueueAtr( + osMessageQueueAttr_t *attr, + const char *name, ///< name of the thread + + void *cb_mem, ///< memory for control block + uint32_t cb_size, ///< size of provided memory for control block + + void *mem, ///< memory for data + uint32_t mem_size ///< size of mem +); + +#define InitThreadAtrStatic(ATTR, NAME, CB, STACK, PRIOR) InitThreadAtr(ATTR,NAME,&CB,sizeof(CB),STACK,sizeof(STACK),PRIOR) +#define InitQueueAtrStatic(ATTR, NAME, CB, MEM) InitQueueAtr(ATTR,NAME,&CB,sizeof(CB),MEM,sizeof(MEM)) + +#define InitThreadBlock(BLOCK, NAME, PRIOR) (BLOCK).id = 0; InitThreadAtr(&(BLOCK).attr,NAME,&(BLOCK).controlBlock,sizeof((BLOCK).controlBlock),(BLOCK).stack,sizeof((BLOCK).stack),PRIOR) +#define InitThreadDynBlock(BLOCK, NAME, STACK, PRIOR) (BLOCK).id = 0; InitThreadAtr(&(BLOCK).attr,NAME,NULL,0,NULL,STACK,PRIOR) + + +void utils_thread_block_start(void *env, osThreadId_t *id, osThreadAttr_t *attr, osThreadFunc_t func); + +void utils_thread_block_pause(osThreadId_t id); + +void utils_thread_block_stop(osThreadId_t *id); + +#define ThreadBlock_Start(THREAD, ENV, FUNC) utils_thread_block_start(ENV,&(THREAD).id,&(THREAD).attr, (osThreadFunc_t)(FUNC)) +#define ThreadBlock_Pause(THREAD) utils_thread_block_pause((THREAD).id) +#define ThreadBlock_Stop(THREAD) utils_thread_block_stop(&(THREAD).id) + + +#define PinThreadToCore(BLOCK, CORE) (BLOCK).attr.pinToCore = 1; (BLOCK).attr.core = CORE +#endif //CMSISRTOSTHREADSUTILS_CMSISRTOSTHREADSUTILS_H diff --git a/MODULES/CmsisRtosThreadUtils/modular.json b/MODULES/CmsisRtosThreadUtils/modular.json new file mode 100644 index 0000000..2b84119 --- /dev/null +++ b/MODULES/CmsisRtosThreadUtils/modular.json @@ -0,0 +1,17 @@ +{ + "dep": [ + { + "type": "local", + + "dir": "./MODULES/CmsisRtosInterface" + } + ], + "cmake": { + "inc_dirs": [ + "./" + ], + "srcs": [ + "./*.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/Device_Flagchip_FC7240/cm7/arm_cortex_m7_asm.h b/MODULES/Device_Flagchip_FC7240/cm7/arm_cortex_m7_asm.h new file mode 100644 index 0000000..a18c907 --- /dev/null +++ b/MODULES/Device_Flagchip_FC7240/cm7/arm_cortex_m7_asm.h @@ -0,0 +1,23 @@ +#ifndef _DEVICE_CM7_ARM_CORTEXM7_ASM_H_ +#define _DEVICE_CM7_ARM_CORTEXM7_ASM_H_ + + +/** \brief Reverse byte order in a word. + */ +#if defined (__GNUC__) || defined (__ICCARM__) || defined (__ghs__) || defined (__ARMCC_VERSION) +#define REV_BYTES_32(a, b) __asm volatile ("rev %0, %1" : "=r" (b) : "r" (a)) +#else +#define REV_BYTES_32(a, b) (b = ((a & 0xFF000000U) >> 24U) | ((a & 0xFF0000U) >> 8U) \ + | ((a & 0xFF00U) << 8U) | ((a & 0xFFU) << 24U)) +#endif + +/** \brief Enter low-power standby state + * WFI (Wait For Interrupt) makes the processor suspend execution (Clock is stopped) until an IRQ interrupts. + */ +#if defined (__GNUC__) +#define STANDBY() __asm volatile ("wfi") +#else +#define STANDBY() __asm("wfi") +#endif + +#endif diff --git a/MODULES/Device_Flagchip_FC7240/cm7/cmsis_armcc.h b/MODULES/Device_Flagchip_FC7240/cm7/cmsis_armcc.h new file mode 100644 index 0000000..4d9d064 --- /dev/null +++ b/MODULES/Device_Flagchip_FC7240/cm7/cmsis_armcc.h @@ -0,0 +1,865 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/MODULES/Device_Flagchip_FC7240/cm7/cmsis_armcc_V6.h b/MODULES/Device_Flagchip_FC7240/cm7/cmsis_armcc_V6.h new file mode 100644 index 0000000..cd13240 --- /dev/null +++ b/MODULES/Device_Flagchip_FC7240/cm7/cmsis_armcc_V6.h @@ -0,0 +1,1800 @@ +/**************************************************************************//** + * @file cmsis_armcc_V6.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_ARMCC_V6_H +#define __CMSIS_ARMCC_V6_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get IPSR Register (non-secure) + \details Returns the content of the non-secure IPSR Register when in secure state. + \return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get APSR Register (non-secure) + \details Returns the content of the non-secure APSR Register when in secure state. + \return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get xPSR Register (non-secure) + \details Returns the content of the non-secure xPSR Register when in secure state. + \return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : "sp"); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : "sp"); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (value) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Base Priority with condition (non_secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value) +{ + __ASM volatile ("MSR basepri_max_ns, %0" : : "r" (value) : "memory"); +} +#endif + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + + +#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + +#if (__ARM_ARCH_8M__ == 1U) + +/** + \brief Get Process Stack Pointer Limit + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Get Process Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + + return(result); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Get Main Stack Pointer Limit (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +} + + +#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */ +/** + \brief Set Main Stack Pointer Limit (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +} +#endif + +#endif /* (__ARM_ARCH_8M__ == 1U) */ + + +#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=4 */ + +/** + \brief Get FPSCR + \details eturns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#define __get_FPSCR __builtin_arm_get_fpscr +#if 0 +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} +#endif + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get FPSCR (non-secure) + \details Returns the current value of the non-secure Floating Point Status/Control register when in secure state. + \return Floating Point Status/Control register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMRS %0, fpscr_ns" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} +#endif + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#define __set_FPSCR __builtin_arm_set_fpscr +#if 0 +__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} +#endif + +#if (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set FPSCR (non-secure) + \details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */ + __ASM volatile ("VMSR fpscr_ns, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} +#endif + +#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __builtin_bswap32 + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16 __builtin_bswap16 /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ +#if 0 +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} +#endif + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ + /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ + /* ToDo: ARMCC_V6: check if __builtin_arm_rbit is supported */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */ + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +/*#define __SSAT __builtin_arm_ssat*/ +#define __SSAT(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat +#if 0 +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) +#endif + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */ + + +#if (__ARM_ARCH_8M__ == 1U) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* (__ARM_ARCH_8M__ == 1U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__ARM_FEATURE_DSP == 1U) /* ToDo: ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */ + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1U) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_V6_H */ diff --git a/MODULES/Device_Flagchip_FC7240/cm7/cmsis_armclang.h b/MODULES/Device_Flagchip_FC7240/cm7/cmsis_armclang.h new file mode 100644 index 0000000..162a400 --- /dev/null +++ b/MODULES/Device_Flagchip_FC7240/cm7/cmsis_armclang.h @@ -0,0 +1,1869 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/MODULES/Device_Flagchip_FC7240/cm7/cmsis_compiler.h b/MODULES/Device_Flagchip_FC7240/cm7/cmsis_compiler.h new file mode 100644 index 0000000..9664d6c --- /dev/null +++ b/MODULES/Device_Flagchip_FC7240/cm7/cmsis_compiler.h @@ -0,0 +1,271 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include "cmsis_iccarm.h" + +/* + * GHS Compiler + */ +#elif defined ( __ghs__ ) + #include "cmsis_ghs.h" + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/MODULES/Device_Flagchip_FC7240/cm7/cmsis_gcc.h b/MODULES/Device_Flagchip_FC7240/cm7/cmsis_gcc.h new file mode 100644 index 0000000..2d9db15 --- /dev/null +++ b/MODULES/Device_Flagchip_FC7240/cm7/cmsis_gcc.h @@ -0,0 +1,2085 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.4 + * @date 09. April 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/MODULES/Device_Flagchip_FC7240/cm7/cmsis_ghs.h b/MODULES/Device_Flagchip_FC7240/cm7/cmsis_ghs.h new file mode 100644 index 0000000..390d532 --- /dev/null +++ b/MODULES/Device_Flagchip_FC7240/cm7/cmsis_ghs.h @@ -0,0 +1,104 @@ +/**************************************************************************//** + * @file cmsis_ghs.h + * @brief CMSIS compiler GHS header file + * @version V5.0.4 + * @date 09. April 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GHS_H +#define __CMSIS_GHS_H +/* GHS MULTI intrinsic functions (e.g. __enable_interrupt()) */ +#include + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __RESTRICT + #define __RESTRICT restrict +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __UNALIGNED_UINT32 + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __DMB + #define __DMB() __ASM("dmb") +#endif +#ifndef __DSB + #define __DSB() __ASM("dsb") +#endif +#ifndef __ISB + #define __ISB() __ASM("isb") +#endif +#ifndef __WFI + #define __WFI() __ASM("wfi") +#endif +#ifndef __WFE + #define __WFE() __ASM("wfe") +#endif +#ifndef __enable_irq + #define __enable_irq() __ASM("cpsie i") +#endif +#ifndef __disable_irq + #define __disable_irq() __ASM("cpsid i") +#endif +#ifndef __get_FPSCR + /** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ + __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) + { + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + return __VMRS(__VFP_FPSCR);; + #else + return(0U); + #endif + } +#endif + + +#endif /* __CMSIS_GHS_H */ diff --git a/MODULES/Device_Flagchip_FC7240/cm7/cmsis_iccarm.h b/MODULES/Device_Flagchip_FC7240/cm7/cmsis_iccarm.h new file mode 100644 index 0000000..11c4af0 --- /dev/null +++ b/MODULES/Device_Flagchip_FC7240/cm7/cmsis_iccarm.h @@ -0,0 +1,935 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.0.7 + * @date 19. June 2018 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2018 IAR Systems +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/MODULES/Device_Flagchip_FC7240/cm7/cmsis_version.h b/MODULES/Device_Flagchip_FC7240/cm7/cmsis_version.h new file mode 100644 index 0000000..660f612 --- /dev/null +++ b/MODULES/Device_Flagchip_FC7240/cm7/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/MODULES/Device_Flagchip_FC7240/cm7/core_cm7_regs.h b/MODULES/Device_Flagchip_FC7240/cm7/core_cm7_regs.h new file mode 100644 index 0000000..7ee1cd6 --- /dev/null +++ b/MODULES/Device_Flagchip_FC7240/cm7/core_cm7_regs.h @@ -0,0 +1,2417 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 04. June 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +/*@} end of group CMSIS_FPU */ + +/** + \ingroup MCM_register + \brief Type definitions for the MCM_register Registers + @{ + */ +/** + \brief Structure type to access the MCM Register (CoreDebug). + */ +typedef struct +{ + __IM uint32_t RESERVE; /*!< Offset: 0x000 */ + __IM uint32_t MICR; /*!< Offset: 0x004 ( / ) Core ID Register */ +} MCM_Type; + +#define MCM_MICR_COREID_Pos 16U /*!< MCM MICR: COREID Position */ +#define MCM_MICR_COREID_Msk 0x000F0000UL /*!< MCM MICR: COREID Mask */ + +/*@} end of group MCM */ + + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ +#define MCM_BASE (0xE0080000UL) /*!< MICR Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ +#define MCM ((MCM_Type *) MCM_BASE) /*!< MCM configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping IntMgr_SetGroupPriority//__NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ IntMgr_EnableInterrupt//__NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ IntMgr_DisableInterrupt + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority IntMgr_SetPriority//__NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); +#else + (void)addr; + (void)dsize; + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); +#else + (void)addr; + (void)dsize; + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); +#else + (void)addr; + (void)dsize; + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/MODULES/Device_Flagchip_FC7240/cm7/mpu_armv7.h b/MODULES/Device_Flagchip_FC7240/cm7/mpu_armv7.h new file mode 100644 index 0000000..d9eedf8 --- /dev/null +++ b/MODULES/Device_Flagchip_FC7240/cm7/mpu_armv7.h @@ -0,0 +1,275 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.2 + * @date 25. May 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/MODULES/Device_Flagchip_FC7240/compiler.h b/MODULES/Device_Flagchip_FC7240/compiler.h new file mode 100644 index 0000000..353a060 --- /dev/null +++ b/MODULES/Device_Flagchip_FC7240/compiler.h @@ -0,0 +1,54 @@ +/** + * @file compiler.h + * @author Flagchip + * @brief compiler define + * @version 0.1.1 + * @date 2024-01-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +#ifndef DEVICE_COMPILER_H_ +#define DEVICE_COMPILER_H_ + + +#ifndef __IO + #ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ + #else + #define __I volatile const /*!< Defines 'read only' permissions */ + #endif + #define __O volatile /*!< Defines 'write only' permissions */ + #define __IO volatile /*!< Defines 'read / write' permissions */ +#endif + + +#if defined (__GNUC__) + #define INLINE __attribute__((always_inline)) inline + #define LOCAL_INLINE __attribute__((always_inline)) static inline + +#else + #define INLINE inline + #define LOCAL_INLINE static inline + +#endif + +#if (defined(__ICCARM__)) +#define STRINGIZE(x) #x +#define ALIGN(n) _Pragma(STRINGIZE(data_alignment=(n))) +#define PACKED __packed +#endif + +#if (defined(__GNUC__)) +#define ALIGN(n) __attribute__ ((aligned (n))) +#define PACKED __packed +#endif + +#if (defined(__ghs__)) +#define INLINE inline +#define LOCAL_INLINE static inline +#define ALIGN(n) __attribute__((aligned(n))) +#define PCAKED __attribute__((packed)) +#endif + +#endif /* DEVICE_COMPILER_H_ */ diff --git a/MODULES/Device_Flagchip_FC7240/device_header.h b/MODULES/Device_Flagchip_FC7240/device_header.h new file mode 100644 index 0000000..7958f8a --- /dev/null +++ b/MODULES/Device_Flagchip_FC7240/device_header.h @@ -0,0 +1,121 @@ +/** + * @file device_header.h + * @author Flagchip + * @brief include all peripheral register files + * @version 0.1.0 + * @date 2024-01-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +#ifndef DEVICE_HEADER_H +#define DEVICE_HEADER_H + +#define __FPU_PRESENT 1 +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __ICACHE_PRESENT 1U +#define __DCACHE_PRESENT 1U + +#include + +#include "typedef.h" +#include "v_def.h" + +#include "fcmath.h" +#include "fcfunc.h" +#include "cmsis_compiler.h" +#include "core_cm7_regs.h" +#include "arm_cortex_m7_asm.h" +#include "mpu_armv7.h" + +#include "fc7240_acc_regs.h" +#include "fc7240_adc_regs.h" +#include "fc7240_aontimer_regs.h" +#include "fc7240_cmp_regs.h" +#include "fc7240_cmu_regs.h" +#include "fc7240_cordic_regs.h" +#include "fc7240_cpm_regs.h" +#include "fc7240_crc_regs.h" +#include "fc7240_csc0_regs.h" +#include "fc7240_dmamux_regs.h" +#include "fc7240_dma_regs.h" +#include "fc7240_eim_regs.h" +#include "fc7240_erm_regs.h" +#include "fc7240_fciic_regs.h" +#include "fc7240_fcpit_regs.h" +#include "fc7240_fcsmu_regs.h" +#include "fc7240_fcspi_regs.h" +#include "fc7240_fcuart_regs.h" +#include "fc7240_flexcan_regs.h" +#include "fc7240_fmc_regs.h" +#include "fc7240_freqm_regs.h" +#include "fc7240_ftu_regs.h" +#include "fc7240_gpio_regs.h" +#include "fc7240_intm_regs.h" +#include "fc7240_ism_regs.h" +#include "fc7240_lu_regs.h" +#include "fc7240_mam_regs.h" +#include "fc7240_mb_regs.h" +#include "fc7240_msc_regs.h" +#include "fc7240_ahb_overlay_regs.h" +#include "fc7240_pcc_regs.h" +#include "fc7240_pmc_regs.h" +#include "fc7240_port_regs.h" +#include "fc7240_ptimer_regs.h" +#include "fc7240_rgm_regs.h" +#include "fc7240_rtc_regs.h" +#include "fc7240_scg_regs.h" +#include "fc7240_scm_regs.h" +#include "fc7240_stcu_regs.h" +#include "fc7240_sec_regs.h" +#include "fc7240_sent_regs.h" +#include "fc7240_smc_regs.h" +#include "fc7240_stcu_regs.h" +#include "fc7240_tmu_regs.h" +#include "fc7240_tpu_e_regs.h" +#include "fc7240_tpu_h_regs.h" +#include "fc7240_trgsel_regs.h" +#include "fc7240_tstmp_regs.h" +#include "fc7240_wdog_regs.h" +#include "fc7240_wku_regs.h" + + +#define PFLASH_START 0x01000000U +#define PFLASH_END 0x011FFFFFU + +#define SRAM_START 0x21000000U +#define SRAM_END 0x21017FFFU + + +#define INLINE_FLASHDRIVER_RAM STD_OFF + +#define WDOG0_RECONF_LOCK_DELAY_US 100U /* 100us */ + + + +#if (defined(__ICCARM__)) + +#define PROCESS_UNUSED_VAR(var) (var) = (var); + +#elif defined __GNUC__ +#define PROCESS_UNUSED_VAR(var) (void)(var); + +#elif defined __ghs__ + +#define PROCESS_UNUSED_VAR(var) (void)(var); +#endif + + +#define FC4150F512 0x01U +#define FC4150F2M 0x02U +#define FC7300HSM 0x03U +#define FC7300CM7 0x04U +#define FC7240HOST 0x05U +#define FC7240FLEXCORE 0x06U +#define DEVICE_TYPE FC7240HOST + +#endif /* DEVICE_HEADER_H */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/MODULES/Device_Flagchip_FC7240/fc/Z_AddInclude.py b/MODULES/Device_Flagchip_FC7240/fc/Z_AddInclude.py new file mode 100644 index 0000000..dd4f6cd --- /dev/null +++ b/MODULES/Device_Flagchip_FC7240/fc/Z_AddInclude.py @@ -0,0 +1,44 @@ +import os +import re +import time + +def Add_Include(filePath,name): + fp = open(filePath) + lines = [] + for line in fp: + lines.append(line) + fp.close() + fp.close() + + del lines[:2] #delete previous define DRIVER_xxx_H + lines.insert(0, r'#ifndef _'+name.upper()+'_H_') #add in LINE+1 + lines.insert(1, r'#define _'+name.upper()+'_H_') #add in LINE+1 + lines.insert(2, r'#ifdef __cplusplus') #add in LINE+1 + lines.insert(3, r' extern "C" {') #add in LINE+1 + lines.insert(4, r'#endif') #add in LINE+1 + + lines.insert(len(lines)-1, r'#ifdef __cplusplus') #add in LINE+1 + lines.insert(len(lines)-1, r'}') #add in LINE+1 + lines.insert(len(lines)-1, r'#endif') #add in LINE+1 + + s = '\n'.join(lines) + fp = open(filePath, 'w') + fp.write(s) + fp.close() + + +if __name__=='__main__': + path = os.getcwd() + for filename in os.listdir(path): + result1 = os.path.splitext(filename) + #print(filename+', '+result1[0]+'\n') + + if result1[1] == '.h' : + oldname=filename + print(filename[7:-9]) + #time.sleep() + newname='fc7240_'+filename[7:-9].lower()+'_regs.h' + os.rename(oldname,newname); + result1 = os.path.splitext(newname) + Add_Include(newname,result1[0]) + #print(newname+'\n') diff --git a/MODULES/Device_Flagchip_FC7240/fc/fc7240_acc_regs.h b/MODULES/Device_Flagchip_FC7240/fc/fc7240_acc_regs.h new file mode 100644 index 0000000..625f7b6 --- /dev/null +++ b/MODULES/Device_Flagchip_FC7240/fc/fc7240_acc_regs.h @@ -0,0 +1,719 @@ +#ifndef _FC7240_ACC_NU_Tztufn3_REGS_H_ +#define _FC7240_ACC_NU_Tztufn3_REGS_H_ +#ifdef __cplusplus + extern "C" { +#endif + + +/* ---------------------------------------------------------------------------- + + -- ACC Peripheral Access Layer + + ---------------------------------------------------------------------------- */ + + + +/*! + + * @addtogroup ACC_Peripheral_Access_Layer ACC Peripheral Access Layer + + * @{ + + */ + + + +/** ACC - Size of Registers Arrays */ + + + +/** ACC - Register Layout Typedef */ + +#define ACC_IEBR_COUNT 2 + +#define ACC_DEBR_COUNT 2 + + + +typedef struct { + + + + uint8_t RESERVED_0[20]; + + __IO uint32_t CCR ; /* Configuration and Control Register, offset: 0x14 */ + + uint8_t RESERVED_1[96]; + + __I uint32_t CLIDR ; /* Cache Level ID Register, offset: 0x78 */ + + __I uint32_t CTR ; /* Cache Type Register, offset: 0x7C */ + + __I uint32_t CCSIDR ; /* Cache Size ID Register, offset: 0x80 */ + + __IO uint32_t CSSELR ; /* Cache Size Selection Register, offset: 0x84 */ + + uint8_t RESERVED_2[456]; + + __O uint32_t ICIALLU ; /* I-cache Invalidate All to PoU Register, offset: 0x250 */ + + uint8_t RESERVED_3[4]; + + __O uint32_t ICIMVAU ; /* I-cache Invalidate by MVA to PoU Register, offset: 0x258 */ + + __O uint32_t DCIMVAC ; /* D-cache Invalidate by MVA to PoC Register, offset: 0x25C */ + + __O uint32_t DCISW ; /* D-cache Invalidate by Set-way Register, offset: 0x260 */ + + __O uint32_t DCCMVAU ; /* D-cache Clean by MVA to PoU Register, offset: 0x264 */ + + __O uint32_t DCCMVAC ; /* D-cache Clean by MVA to PoC Register, offset: 0x268 */ + + __O uint32_t DCCSW ; /* D-cache Clean by Set-way Register, offset: 0x26C */ + + __O uint32_t DCCIMVAC ; /* D-cache Clean and Invalidate by MVA to PoC Register, offset: 0x270 */ + + __O uint32_t DCCISW ; /* D-cache Clean and Invalidate by Set-way Register, offset: 0x274 */ + + uint8_t RESERVED_4[36]; + + __IO uint32_t CACR ; /* L1 Cache Control Register, offset: 0x29C */ + + uint8_t RESERVED_5[16]; + + __IO uint32_t IEBR[ACC_IEBR_COUNT] ; /* Instruction Error Bank Register, offset: 0x2b0 */ + + __IO uint32_t DEBR[ACC_DEBR_COUNT] ; /* Data Error Bank Register, offset: 0x2b8 */ + + + +} ACC_Type, *ACC_MemMapPtr; + + + +/** Number of instances of the ACC module. */ + +#define ACC_INSTANCE_COUNT (1u) + + + +/* ACC - Peripheral instance base addresses */ + +/** Peripheral ACC base address */ + +#define ACC_BASE (0xE000ED00u) + +/** Peripheral ACC base pointer */ + +#define ACC ((ACC_Type *)ACC_BASE) + +/** Array initializer of ACC peripheral base addresses */ + +#define ACC_BASE_ADDRS {ACC_BASE} + +/** Array initializer of ACC peripheral base pointers */ + +#define ACC_BASE_PTRS {ACC} + +// need fill by yourself + +///** Number of interrupt vector arrays for the ACC module. */ + +//#define ACC_IRQS_ARR_COUNT (1u) + +///** Number of interrupt channels for the ACC module. */ + +//#define ACC_IRQS_CH_COUNT (1u) + +///** Interrupt vectors for the ACC peripheral type */ + +//#define ACC_IRQS {ACC_IRQn} + + + + + +/* ---------------------------------------------------------------------------- + + -- ACC Register Masks + + ---------------------------------------------------------------------------- */ + + + +/*! + + * @addtogroup ACC_Register_Masks ACC Register Masks + + * @{ + + */ + + + +/* CCR Bit Fields */ + +#define ACC_CCR_BP_MASK 0x40000u + +#define ACC_CCR_BP_SHIFT 18u + +#define ACC_CCR_BP_WIDTH 1u + +#define ACC_CCR_BP(x) (((uint32_t)(((uint32_t)(x))<--memcpy() + * + * \param pDest pSource u32Count wdogTriggerFunc + */ +void* FCFUNC_FcOwnMemcpy(uint8_t *pDest, const uint8_t *pSource, uint32_t u32Count, void_functype wdogTriggerFunc ) +{ + uint8_t* plocalDest; + const uint8_t* plocalSource; + uint32_t u32Index; + + /* Initialize variables */ + plocalDest = (uint8_t*)pDest; + plocalSource = (uint8_t const *)pSource; + + for (u32Index = 0u; u32Index < u32Count; u32Index++) + { + if ((u32Index & 0x3Fu) == 0u) + { + if(wdogTriggerFunc!=NULL) + { + (void)wdogTriggerFunc(); + } + } + plocalDest[u32Index] = plocalSource[u32Index]; + } + + return pDest; +} + + +void* FC_OwnMemcpy(void *pDest, const void *pSource, uint32_t u32Count) +{ + uint8_t* plocalDest; + const uint8_t* plocalSource; + uint32_t u32Index; + + /* Initialize variables */ + plocalDest = (uint8_t*)pDest; + plocalSource = (const uint8_t*)pSource; + + for (u32Index = 0u; u32Index < u32Count; u32Index++) + { + plocalDest[u32Index] = plocalSource[u32Index]; + } + + return pDest; +} + + + +void* FC_OwnMemcpyWithWdg(void *pDest, const void *pSource, uint32_t u32Count, void_functype wdogTriggerFunc, uint32_t u32CallBackCnt) +{ + uint8_t* plocalDest; + const uint8_t* plocalSource; + uint32_t u32Index; + + /* Initialize variables */ + plocalDest = (uint8_t*)pDest; + plocalSource = (const uint8_t*)pSource; + + for (u32Index = 0u; u32Index < u32Count; u32Index++) + { + if ((u32Index % u32CallBackCnt) == 0u) + { + if(wdogTriggerFunc!=NULL) + { + (void)wdogTriggerFunc(); + } + } + plocalDest[u32Index] = plocalSource[u32Index]; + } + + return pDest; +} + diff --git a/MODULES/Device_Flagchip_FC7240/fclib/fcfunc.h b/MODULES/Device_Flagchip_FC7240/fclib/fcfunc.h new file mode 100644 index 0000000..27e3590 --- /dev/null +++ b/MODULES/Device_Flagchip_FC7240/fclib/fcfunc.h @@ -0,0 +1,32 @@ +/** + * @file fc7xxx_fclib.h + * @author Flagchip + * @brief include fclib file + * @version 0.2.1 + * @date 2022-02-20 + * + * @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. + * + */ +#ifndef _DEVICE_FCLIB_FCFUNC_H_ +#define _DEVICE_FCLIB_FCFUNC_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "typedef.h" +#include "v_def.h" + + void* FCFUNC_FcOwnMemcpy(uint8_t *pDest, const uint8_t *pSource, uint32_t u32Count, void_functype wdogTriggerFunc ); + +void* FC_OwnMemcpy(void *pDest, const void *pSource, uint32_t u32Count); + +void* FC_OwnMemcpyWithWdg(void *pDest, const void *pSource, uint32_t u32Count, void_functype wdogTriggerFunc, uint32_t u32CallBackCnt ); + +#ifdef __cplusplus +} +#endif + + +#endif diff --git a/MODULES/Device_Flagchip_FC7240/fclib/fcmath.c b/MODULES/Device_Flagchip_FC7240/fclib/fcmath.c new file mode 100644 index 0000000..9d9d725 --- /dev/null +++ b/MODULES/Device_Flagchip_FC7240/fclib/fcmath.c @@ -0,0 +1,45 @@ +/** + * @file fc7xxx_fcmath.h + * @author Flagchip + * @brief include fcmath file + * @version 0.2.1 + * @date 2022-02-20 + * + * @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. + * + */ +#include "fcmath.h" + + +uint32_t Fc_Power(uint32_t num, uint32_t u8Power) +{ + uint8_t u8Index; + uint32_t u32RetVal; + + u32RetVal = 1; + for(u8Index=0;u8Indexu32Val2) + return u32Val1; + else + return u32Val2; +} + + +uint32_t Fc_Min(uint32_t u32Val1, uint32_t u32Val2) +{ + if(u32Val1>u32Val2) + return u32Val2; + else + return u32Val1; +} diff --git a/MODULES/Device_Flagchip_FC7240/fclib/fcmath.h b/MODULES/Device_Flagchip_FC7240/fclib/fcmath.h new file mode 100644 index 0000000..c51d32e --- /dev/null +++ b/MODULES/Device_Flagchip_FC7240/fclib/fcmath.h @@ -0,0 +1,32 @@ +/** + * @file fc7xxx_fclib.h + * @author Flagchip + * @brief include fclib file + * @version 0.2.1 + * @date 2022-02-20 + * + * @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. + * + */ +#ifndef _DEVICE_FCLIB_FCMATH_H_ +#define _DEVICE_FCLIB_FCMATH_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "typedef.h" + +uint32_t Fc_Power(uint32_t num, uint32_t u8Power); + +uint32_t Fc_Max(uint32_t u32Val1, uint32_t u32Val2); + +uint32_t Fc_Min(uint32_t u32Val1, uint32_t u32Val2); + + +#ifdef __cplusplus +} +#endif + + +#endif diff --git a/MODULES/Device_Flagchip_FC7240/interrupt_manager.c b/MODULES/Device_Flagchip_FC7240/interrupt_manager.c new file mode 100644 index 0000000..a261dc8 --- /dev/null +++ b/MODULES/Device_Flagchip_FC7240/interrupt_manager.c @@ -0,0 +1,159 @@ +/** + * @file interrupt_manager.c + * @author Flagchip + * @brief interrupt configuration + * @version 0.1.0 + * @date 2024-01-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +#include "interrupt_manager.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + + +#define FC7300_PERI_VECTOR_START 16U + +#define FC7300_NVIC_PRIO_BITS 3U + + +#define __NVIC_PRIO_BITS 2U + + + +/******************************************************************************* + * Code + ******************************************************************************/ + +#if 0 +/** + * \brief Initial the interrupt table and data and bss + * + */ +void IntMgr_Init(void) +{ +#if defined ( __GNUC__ ) + extern uint32 __isr0_vector[1]; + SCB->VTOR = (uint32_t)__isr0_vector; +#elif defined (__ICCARM__) + extern uint32 __vector_table[1]; + SCB->VTOR = (uint32_t)__vector_table; +#endif +} +#endif + + +/** + * \brief enable interrupt via interrupt number + * + * \param eIrqNumber is interrupt number + */ +void IntMgr_EnableInterrupt(IRQn_Type eIrqNumber) +{ + if ((int32_t)(eIrqNumber) >= 0) + { + NVIC->ISER[(((uint32_t)eIrqNumber) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)eIrqNumber) & 0x1FUL)); + } +} + + +/** + * \brief disable interrupt via interrupt number + * + * \param eIrqNumber is interrupt number + */ +void IntMgr_DisableInterrupt(IRQn_Type eIrqNumber) +{ + if ((int32_t)(eIrqNumber) >= 0) + { + NVIC->ICER[(((uint32_t)eIrqNumber) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)eIrqNumber) & 0x1FUL)); + __DSB(); + __ISB(); + } + +} + +/** + * \brief enable global interrupt + * + */ +void IntMgr_EnableGlobalInterrupt(void) +{ + /* Enable the global interrupt*/ + __enable_irq(); + +} + +/** + * \brief disable global interrupt + * + */ +void IntMgr_DisableGlobalInterrupt(void) +{ + /* Disable the global interrupt */ + __disable_irq(); + +} + +/** + * \brief Set Priority group + * + * \param u32PriorityGroup is the group bits + */ +void IntMgr_SetGroupPriority(uint32_t u32PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (u32PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + +/** + * \brief set the interrupt service Priority + * + * \param eIrqNumber is interrupt number + * \param u8Priority is u8Priority number + */ +void IntMgr_SetPriority(IRQn_Type eIrqNumber, uint8_t u8Priority) +{ + + if ((int32_t)(eIrqNumber) >= 0) + { + NVIC->IP[((uint32_t)eIrqNumber)] = (uint8_t)(((uint32_t)u8Priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFU); + } + else + { + SCB->SHPR[(((uint32_t)eIrqNumber) & 0xFUL) - 4UL] = (uint8_t)(((uint32_t)u8Priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFU); + } +} + + +/** + * \brief get the interrupt service Priority + * + * \param eIrqNumber is interrupt number + * \return the Priority + */ +uint8_t IntMgr_GetPriority(IRQn_Type eIrqNumber) +{ + if ((int32_t)(eIrqNumber) >= 0) + { + return (((uint32_t)NVIC->IP[((uint32_t)eIrqNumber)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return (((uint32_t)SCB->SHPR[(((uint32_t)eIrqNumber) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/MODULES/Device_Flagchip_FC7240/interrupt_manager.h b/MODULES/Device_Flagchip_FC7240/interrupt_manager.h new file mode 100644 index 0000000..112f323 --- /dev/null +++ b/MODULES/Device_Flagchip_FC7240/interrupt_manager.h @@ -0,0 +1,207 @@ +/** + * @file interrupt_manager.h + * @author Flagchip + * @brief interrupt configuration + * @version 0.1.0 + * @date 2024-01-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +#if !defined(INTERRUPT_MANAGER_H) +#define INTERRUPT_MANAGER_H + + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + + +#include "device_header.h" + +typedef enum +{ + NVIC_PRIORITY_GROUP_0 = ((uint32_t)0x7), /*!< 0 bits for preemption priority, 4 bits for subpriority */ + NVIC_PRIORITY_GROUP_1 = ((uint32_t)0x6), /*!< 1 bits for preemption priority, 3 bits for subpriority */ + NVIC_PRIORITY_GROUP_2 = ((uint32_t)0x5), /*!< 2 bits for preemption priority, 2 bits for subpriority */ + NVIC_PRIORITY_GROUP_3 = ((uint32_t)0x4), /*!< 3 bits for preemption priority, 1 bits for subpriority */ + NVIC_PRIORITY_GROUP_4 = ((uint32_t)0x3) /*!< 4 bits for preemption priority, 0 bits for subpriority */ +} nvic_priority_group_type; + +typedef enum +{ + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ + + /* FC100 Device specific interrupts */ + DMA0_IRQn = 0U, /**< DMA channel 0 transfer complete */ + DMA1_IRQn = 1U, /**< DMA channel 1 transfer complete */ + DMA2_IRQn = 2U, /**< DMA channel 2 transfer complete */ + DMA3_IRQn = 3U, /**< DMA channel 3 transfer complete */ + DMA4_IRQn = 4U, /**< DMA channel 4 transfer complete */ + DMA5_IRQn = 5U, /**< DMA channel 5 transfer complete */ + DMA6_IRQn = 6U, /**< DMA channel 6 transfer complete */ + DMA7_IRQn = 7U, /**< DMA channel 7 transfer complete */ + DMA8_IRQn = 8U, /**< DMA channel 8 transfer complete */ + DMA9_IRQn = 9U, /**< DMA channel 9 transfer complete */ + DMA10_IRQn = 10U, /**< DMA channel 10 transfer complete */ + DMA11_IRQn = 11U, /**< DMA channel 11 transfer complete */ + DMA12_IRQn = 12U, /**< DMA channel 12 transfer complete */ + DMA13_IRQn = 13U, /**< DMA channel 13 transfer complete */ + DMA14_IRQn = 14U, /**< DMA channel 14 transfer complete */ + DMA15_IRQn = 15U, /**< DMA channel 15 transfer complete */ + DMA_Error_IRQn = 16U, /**< DMA error interrupt channels 0-63 */ + CPM_IRQn = 17U, /**< FPU etc. interrupt */ + FC_IRQn = 18U, /**< Flash Controller Command complete, time out etc. interrupt */ + LVD_LVW_IRQn = 19U, /**< HVD/LVD etc. interrupt */ + TMU_IRQn = 20U, /**< Temperature Monitor Unit interrupt */ + WDOG0_IRQn = 21U, /**< Interrupt request out before wdg0 reset out */ + WDOG1_IRQn = 22U, /**< Interrupt request out before wdg1 reset out */ + FCSMU0_IRQn = 23U, /**< Fault Control and Safety Manage Unit */ + STCU0_IRQn = 24U, /**< Safety Control Unit interrupt */ + ERM_fault_IRQn = 25U, /**< ERM single- or double-bit error interrupt */ + MAM0_IRQn = 26U, /**< Matrix Access Monitor interrupt */ + RGM_Pre_IRQn = 27U, /**< RGM pre-reset Interrupt */ + INTM0_IRQn = 28U, /**< INTM0 timeout interrupt */ + ISM0_IRQn = 29U, /**< ISM0 interrupt */ + MB_IRQn = 30U, /**< Mail Box interrupt */ + SCG_IRQn = 31U, /**< SCG bus interrupt request */ + CMU0_IRQn = 32U, /**< CMU0 interrupt */ + CMU1_IRQn = 33U, /**< CMU1 interrupt */ + CMU2_IRQn = 34U, /**< CMU2 interrupt */ + CMU3_IRQn = 35U, /**< CMU3 interrupt */ + CMU4_IRQn = 36U, /**< CMU4 interrupt */ + TSTMP0_IRQn = 37U, /**< TimerStamp0 interrupt */ + TSTMP1_IRQn = 38U, /**< TimerStamp1 interrupt */ + CORDIC_IRQn = 39U, /**< CORDIC Accelerator interrupt */ + HSM0_ERR_IRQn = 40U, /**< HSM error interrupt */ + FCPIT0_IRQn = 41U, /**< FCPIT interrupt */ + RTC_IRQn = 42U, /**< RTC alarm or seconds interrupt */ + AONTIMER_IRQn = 43U, /**< AONTIMER interrupt request */ + SWI_IRQn = 44U, /**< Software interrupt */ + FREQM_IRQn = 45U, /**< FREQM interrupt */ + ADC0_IRQn = 46U, /**< ADC0 interrupt request */ + ADC1_IRQn = 47U, /**< ADC1 interrupt request */ + PTIMER0_IRQn = 48U, /**< PTIMER0 interrupt */ + PTIMER1_IRQn = 49U, /**< PTIMER1 interrupt */ + FlexCAN0_IRQn = 50U, /**< FLEXCAN0 interrupt */ + FlexCAN1_IRQn = 51U, /**< FLEXCAN1 interrupt */ + FlexCAN2_IRQn = 52U, /**< FLEXCAN2 interrupt */ + FlexCAN3_IRQn = 53U, /**< FLEXCAN3 interrupt */ + FCIIC0_IRQn = 54U, /**< FCIIC0 Interrupt */ + FCIIC1_IRQn = 55U, /**< FCIIC1 Interrupt */ + FCSPI0_IRQn = 56U, /**< FCSPI0 Interrupt */ + FCSPI1_IRQn = 57U, /**< FCSPI1 Interrupt */ + FCSPI2_IRQn = 58U, /**< FCSPI2 Interrupt */ + FCSPI3_IRQn = 59U, /**< FCSPI3 Interrupt */ + FCSPI4_IRQn = 60U, /**< FCSPI4 Interrupt */ + FCSPI5_IRQn = 61U, /**< FCSPI5 Interrupt */ + FCUART0_IRQn = 62U, /**< FCUART0 Interrupt */ + FCUART1_IRQn = 63U, /**< FCUART1 Interrupt */ + FCUART2_IRQn = 64U, /**< FCUART2 Interrupt */ + FCUART3_IRQn = 65U, /**< FCUART3 Interrupt */ + FCUART4_IRQn = 66U, /**< FCUART4 Interrupt */ + FCUART5_IRQn = 67U, /**< FCUART5 Interrupt */ + FCUART6_IRQn = 68U, /**< FCUART6 Interrupt */ + FCUART7_IRQn = 69U, /**< FCUART7 Interrupt */ + FTU0_IRQn = 70U, /**< FTU0 all source interrupt */ + FTU1_IRQn = 71U, /**< FTU1 all source interrupt */ + FTU2_IRQn = 72U, /**< FTU2 all source interrupt */ + FTU3_IRQn = 73U, /**< FTU3 all source interrupt */ + FTU4_IRQn = 74U, /**< FTU4 all source interrupt */ + FTU5_IRQn = 75U, /**< FTU5 all source interrupt */ + FTU6_IRQn = 76U, /**< FTU6 all source interrupt */ + FTU7_IRQn = 77U, /**< FTU7 all source interrupt */ + CMP0_IRQn = 78U, /**< CMP0 all source interrupt */ + CMP1_IRQn = 79U, /**< CMP1 all source interrupt */ + PORTA_IRQn = 80U, /**< Port A pin detect interrupt */ + PORTB_IRQn = 81U, /**< Port B pin detect interrupt */ + PORTC_IRQn = 82U, /**< Port C pin detect interrupt */ + PORTD_IRQn = 83U, /**< Port D pin detect interrupt */ + PORTE_IRQn = 84U, /**< Port E pin detect interrupt */ + MSC0_IRQn = 85U, /**< MSC Interrupt */ + SENT0_IRQn = 86U, /**< SENT all interrupt (fast or slow) */ + TPU0_CH0_7_IRQn = 87U, /**< TPU0 CH0-7 interrupt */ + TPU0_CH8_15_IRQn = 88U, /**< TPU0 CH8-15 interrupt */ + TPU0_CH16_23_IRQn = 89U, /**< TPU0 CH16-23 interrupt */ + TPU0_CH24_31_IRQn = 90U, /**< TPU0 CH24-31 interrupt */ + HSM0_IRQn = 91U, /**< HSM crypto interrupt */ + IRQn_MAX = 92U +} IRQn_Type; + + + + + +/** + * \brief enable interrupt via interrupt number + * + * \param eIrqNumber is interrupt number + */ +void IntMgr_EnableInterrupt(IRQn_Type eIrqNumber); + +/** + * \brief disable interrupt via interrupt number + * + * \param eIrqNumber is interrupt number + */ +void IntMgr_DisableInterrupt(IRQn_Type eIrqNumber); + +/** + * \brief enable global interrupt + * + */ +void IntMgr_EnableGlobalInterrupt(void); + +/** + * \brief disable global interrupt + * + */ +void IntMgr_DisableGlobalInterrupt(void); + +/** + * \brief Set Priority group + * + * \param u32PriorityGroup is the group bits + */ +void IntMgr_SetGroupPriority(uint32_t u32PriorityGroup); + +/** + * \brief set the interrupt service priority + * + * \param eIrqNumber is interrupt number + * \param u8Priority is priority number + */ +void IntMgr_SetPriority(IRQn_Type eIrqNumber, uint8_t u8Priority); + +/** + * \brief get the interrupt service priority + * + * \param eIrqNumber is interrupt number + * \return the priority + */ +uint8_t IntMgr_GetPriority(IRQn_Type eIrqNumber); + + + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + + + +#endif /* INTERRUPT_MANAGER_H */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/MODULES/Device_Flagchip_FC7240/modular.json b/MODULES/Device_Flagchip_FC7240/modular.json new file mode 100644 index 0000000..d398fbb --- /dev/null +++ b/MODULES/Device_Flagchip_FC7240/modular.json @@ -0,0 +1,16 @@ +{ + "cmake": { + "inc_dirs": [ + "./", + "./cm7", + "./fc", + "./fclib" + ], + "srcs": [ + "./**.c", + "./cm7/**.c", + "./fc/**.c", + "./fclib/**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/Device_Flagchip_FC7240/typedef.h b/MODULES/Device_Flagchip_FC7240/typedef.h new file mode 100644 index 0000000..ead96ba --- /dev/null +++ b/MODULES/Device_Flagchip_FC7240/typedef.h @@ -0,0 +1,37 @@ +/** + * @file typedef.h + * @author Flagchip + * @brief type defines + * @version 0.1.0 + * @date 2024-01-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +#ifndef DEVICE_TYPEDEF_H_ +#define DEVICE_TYPEDEF_H_ + + +#include +#include +#include +#include "compiler.h" + +#define STD_ON 1 +#define STD_OFF 0 + +#ifdef NDEBUG + #define DEV_ASSERT(x) ((void)0) +#else + #define DEV_ASSERT(x) do{}while((x) != 1) +#endif + +#ifndef __IO +#define __IO volatile +#endif + +#ifndef __I +#define __I const +#endif + +#endif /* DEVICE_TYPEDEF_H_ */ diff --git a/MODULES/Device_Flagchip_FC7240/v_def.h b/MODULES/Device_Flagchip_FC7240/v_def.h new file mode 100644 index 0000000..7053b98 --- /dev/null +++ b/MODULES/Device_Flagchip_FC7240/v_def.h @@ -0,0 +1,60 @@ +/** + * @file v_def.h + * @author Flagchip + * @brief variables type define + * @version 0.1.0 + * @date 2024-01-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +#ifndef DEVICE_V_DEF_H_ +#define DEVICE_V_DEF_H_ + +#ifndef TRUE + #define TRUE 1U +#endif + +#ifndef FALSE + #define FALSE 0U +#endif + +#ifndef NULL_PTR + #define NULL_PTR ((void*)0) +#endif + +#ifndef int8 + typedef signed char int8; +#endif + +#ifndef int16 + typedef signed short int16; +#endif + +#ifndef int32 + typedef signed int int32; +#endif + +#ifndef uint8 + typedef unsigned char uint8; +#endif + +#ifndef uint16 + typedef unsigned short uint16; +#endif + +#ifndef uint32 + typedef unsigned int uint32; +#endif + +#ifndef boolean + typedef uint8_t boolean; +#endif + +typedef void (*void_functype)(void); + +#ifdef __GUNC__ + +#endif + +#endif /* DEVICE_V_DEF_H_ */ diff --git a/MODULES/FirmwareMetadataSection/FirmwareMetadataSection.c b/MODULES/FirmwareMetadataSection/FirmwareMetadataSection.c new file mode 100644 index 0000000..f78dce8 --- /dev/null +++ b/MODULES/FirmwareMetadataSection/FirmwareMetadataSection.c @@ -0,0 +1,54 @@ +// +// Created by CFIF on 10.10.25. +// + + +#include "FirmwareMetadataSection.h" +#include "VersionRandID.h" + +#define DEF_INTERNAL_HW_YEAR INTERNAL_HW_YEAR +#define DEF_INTERNAL_HW_MONTH INTERNAL_HW_MONTH +#define DEF_INTERNAL_HW_DAY INTERNAL_HW_DAY +#define DEF_INTERNAL_HW_REV INTERNAL_HW_REV + +#define DEF_INTERNAL_SW_YEAR INTERNAL_SW_YEAR +#define DEF_INTERNAL_SW_MONTH INTERNAL_SW_MONTH +#define DEF_INTERNAL_SW_DAY INTERNAL_SW_DAY +#define DEF_INTERNAL_SW_REV INTERNAL_SW_REV + +#define DEF_INTERNAL_MDB_YEAR INTERNAL_MDB_YEAR +#define DEF_INTERNAL_MDB_MONTH INTERNAL_MDB_MONTH +#define DEF_INTERNAL_MDB_DAY INTERNAL_MDB_DAY +#define DEF_INTERNAL_MDB_REV INTERNAL_MDB_REV + +#define DEF_FINGER_MODULE FINGER_MODULE +#define DEF_FINGER_YEAR FINGER_YEAR +#define DEF_FINGER_MONTH FINGER_MONTH +#define DEF_FINGER_DAY FINGER_DAY +#define DEF_FINGER_TESTER_SERIAL FINGER_TESTER_SERIAL "_(" VERSION_RANDOM_BUILD_IDENTIFIER ")" + +volatile const uint8_t META_FW_NAME_SIZE __attribute__((section (".meta_fw_name_size"))) = sizeof(DEF_FINGER_TESTER_SERIAL) - 1; +volatile const char META_FW_NAME[sizeof(DEF_FINGER_TESTER_SERIAL) - 1] __attribute__((section (".meta_fw_name"))) = DEF_FINGER_TESTER_SERIAL; + +volatile const char META_INTERNAL_HW_YEAR __attribute__((section (".meta_internal_hw_year"))) = DEF_INTERNAL_HW_YEAR; +volatile const char META_INTERNAL_HW_MONTH __attribute__((section (".meta_internal_hw_month"))) = DEF_INTERNAL_HW_MONTH; +volatile const char META_INTERNAL_HW_DAY __attribute__((section (".meta_internal_hw_day"))) = DEF_INTERNAL_HW_DAY; +volatile const char META_INTERNAL_HW_REV __attribute__((section (".meta_internal_hw_rev"))) = DEF_INTERNAL_HW_REV; + +volatile const char META_INTERNAL_SW_YEAR __attribute__((section (".meta_internal_sw_year"))) = DEF_INTERNAL_SW_YEAR; +volatile const char META_INTERNAL_SW_MONTH __attribute__((section (".meta_internal_sw_month"))) = DEF_INTERNAL_SW_MONTH; +volatile const char META_INTERNAL_SW_DAY __attribute__((section (".meta_internal_sw_day"))) = DEF_INTERNAL_SW_DAY; +volatile const char META_INTERNAL_SW_REV __attribute__((section (".meta_internal_sw_rev"))) = DEF_INTERNAL_SW_REV; + +volatile const char META_INTERNAL_MDB_YEAR __attribute__((section (".meta_internal_mdb_year"))) = DEF_INTERNAL_MDB_YEAR; +volatile const char META_INTERNAL_MDB_MONTH __attribute__((section (".meta_internal_mdb_month"))) = DEF_INTERNAL_MDB_MONTH; +volatile const char META_INTERNAL_MDB_DAY __attribute__((section (".meta_internal_mdb_day"))) = DEF_INTERNAL_MDB_DAY; +volatile const char META_INTERNAL_MDB_REV __attribute__((section (".meta_internal_mdb_rev"))) = DEF_INTERNAL_MDB_REV; + +volatile const char META_FINGER_MODULE __attribute__((section (".meta_finger_module"))) = DEF_FINGER_MODULE; +volatile const char META_FINGER[sizeof(DEF_FINGER_TESTER_SERIAL) - 1] __attribute__((section (".meta_finger_tester_serial"))) = DEF_FINGER_TESTER_SERIAL; +volatile const char META_FINGER_YEAR __attribute__((section (".meta_finger_year"))) = DEF_FINGER_YEAR; +volatile const char META_FINGER_MONTH __attribute__((section (".meta_finger_month"))) = DEF_FINGER_MONTH; +volatile const char META_FINGER_DAY __attribute__((section (".meta_finger_day"))) = DEF_FINGER_DAY; + + diff --git a/MODULES/FirmwareMetadataSection/FirmwareMetadataSection.h b/MODULES/FirmwareMetadataSection/FirmwareMetadataSection.h new file mode 100644 index 0000000..5dda523 --- /dev/null +++ b/MODULES/FirmwareMetadataSection/FirmwareMetadataSection.h @@ -0,0 +1,24 @@ +// +// Created by CFIF on 07.12.22. +// + +#ifndef UVEOS_ON_NATION_FIRMWAREMETADATASECTION_H +#define UVEOS_ON_NATION_FIRMWAREMETADATASECTION_H + +#include "stdint.h" + +#define ADR_META_BOOT (0x01000000 + (64 * 1024) - 256) +#define ADR_META_MAIN (0x01000000 + ((64 + 704) * 1024) - 256) + +#define ADR_META_MAPPED_BOOT (0x01100000 + (64 * 1024) - 256) +#define ADR_META_MAPPED_MAIN (0x01100000 + ((64 + 704) * 1024) - 256) + +extern volatile const uint32_t META_FW_CRC; + +extern volatile const uint8_t META_FW_NAME_SIZE; +extern volatile const char META_FW_NAME[]; + +extern volatile const uint8_t META_HW_NAME_SIZE; +extern volatile const char META_HW_NAME[]; + +#endif //UVEOS_ON_NATION_FIRMWAREMETADATASECTION_H diff --git a/MODULES/FirmwareMetadataSection/modular.json b/MODULES/FirmwareMetadataSection/modular.json new file mode 100644 index 0000000..404c009 --- /dev/null +++ b/MODULES/FirmwareMetadataSection/modular.json @@ -0,0 +1,17 @@ +{ + "dep": [ + { + "type": "local", + + "dir": "./MODULES/CmakeConfig_RandomBuildIdGenerator" + } + ], + "cmake": { + "inc_dirs": [ + "./" + ], + "srcs": [ + "./*.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/FreeRTOS/doc/GitHub-FreeRTOS-Kernel-Home.url b/MODULES/FreeRTOS/doc/GitHub-FreeRTOS-Kernel-Home.url new file mode 100644 index 0000000..ee675d6 --- /dev/null +++ b/MODULES/FreeRTOS/doc/GitHub-FreeRTOS-Kernel-Home.url @@ -0,0 +1,8 @@ +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,2 +[InternetShortcut] +URL=https://github.com/FreeRTOS/FreeRTOS-Kernel +IconIndex=0 +IDList= +HotKey=0 + diff --git a/MODULES/FreeRTOS/doc/History.txt b/MODULES/FreeRTOS/doc/History.txt new file mode 100644 index 0000000..389dcd9 --- /dev/null +++ b/MODULES/FreeRTOS/doc/History.txt @@ -0,0 +1,2855 @@ +Documentation and download available at https://www.FreeRTOS.org/ + +Changes between FreeRTOS V10.4.3 LTS Patch 1 and FreeRTOS V10.4.3 LTS Patch 2 released November 12 2021 + + + ARMv7-M and ARMv8-M MPU ports – prevent non-kernel code from calling the + internal functions xPortRaisePrivilege and vPortResetPrivilege by changing + them to macros. + +Changes between FreeRTOS V10.4.3 and FreeRTOS V10.4.3 LTS Patch 1 released September 10 2021 + + See https://www.FreeRTOS.org/FreeRTOS-V10.4.5.html + + + ARMv8-M secure-side port: Tasks that call secure functions from the + non-secure side of an ARMv8-M MCU (ARM Cortex-M23 and Cortex-M33) have two + contexts – one on the non-secure side and one on the secure-side. Previous + versions of the FreeRTOS ARMv8-M secure-side ports allocated the structures + that reference secure-side contexts at run time. Now the structures are + allocated statically at compile time. The change necessitates the + introduction of the secureconfigMAX_SECURE_CONTEXTS configuration constant, + which sets the number of statically allocated secure contexts. + secureconfigMAX_SECURE_CONTEXTS defaults to 8 if left undefined. + Applications that only use FreeRTOS code on the non-secure side, such as + those running third-party code on the secure side, are not affected by + this change. + + +Changes between FreeRTOS V10.4.2 and FreeRTOS V10.4.3 released December 14 2020 + + V10.4.3 is included in the 202012.00 LTS release. Learn more at https:/freertos.org/lts-libraries.html + + See https://www.FreeRTOS.org/FreeRTOS-V10.4.x.html + + + Changes to improve robustness and consistency for buffer allocation in + the heap, queue and stream buffer. + + The following functions can no longer be called from unprivileged code. + - xTaskCreateRestricted + - xTaskCreateRestrictedStatic + - vTaskAllocateMPURegions + + +Changes between FreeRTOS V10.4.1 and FreeRTOS V10.4.2 released November 10 2020 + + See https://www.FreeRTOS.org/FreeRTOS-V10.4.x.html + + + Fix an issue in the ARMv8-M ports that caused BASEPRI to be masked + between the first task starting to execute and that task making + a FreeRTOS API call. + + Introduced xTaskDelayUntil(), which is functionally equivalent to + vTaskDelayUntil(), with the addition of returning a value to + indicating whether or not the function placed the calling task into + the Blocked state or not. + + Update WolfSSL to 4.5.0 and add the FIPS ready demo. + + Add support for ESP IDF 4.2 to ThirdParty Xtensa port. + + Re-introduce uxTopUsedPriority to support OpenOCD debugging. + + Convert most dependent libraries in FreeRTOS/FreeRTOS to submodules. + + Various general maintenance and improvements to MISRA compliance. + + +Changes between FreeRTOS V10.4.0 and FreeRTOS V10.4.1 released September 17 2020 + + See https://www.FreeRTOS.org/FreeRTOS-V10.4.x.html + + + Fixed an incorrectly named parameter that prevented the + ulTaskNotifyTakeIndexed macro compiling, and the name space clash in the + test code that prevented this error causing test failures. + + +Changes between FreeRTOS V10.3.1 and FreeRTOS V10.4.0 released September 10 2020 + + See https://www.FreeRTOS.org/FreeRTOS-V10.4.x.html + + Major enhancements: + + + Task notifications: Prior to FreeRTOS V10.4.0 each created task had a + single direct to task notification. From FreeRTOS V10.4.0 each task has + an array of notifications. The direct to task notification API has been + extended with API functions postfixed with "Indexed" to enable the API to + operate on a task notification at any array index. See + https://www.freertos.org/RTOS-task-notifications.html for more information. + + Kernel ports that support memory protection units (MPUs): The ARMv7-M and + ARMv8-M MPU ports now support a privilege access only heap. The ARMv7-M + MPU ports now support devices that have 16 MPU regions, have the ability + to override default memory attributes for privileged code and data + regions, and have the ability to place the FreeRTOS kernel code outside of + the Flash memory. The ARMv8-M MPU ports now support tickless idle mode. + See https://www.freertos.org/FreeRTOS-MPU-memory-protection-unit.html + for more information. + + Additional noteworthy updates: + + + Code formatting is now automated to facilitate the increase in + collaborative development in Git. The auto-formated code is not identical + to the original formatting conventions. Most notably spaces are now used + in place of tabs. + + The prototypes for callback functions (those that start with "Application", + such as vApplicationStackOverflowHook()) are now in the FreeRTOS header + files, removing the need for application writers to add prototypes into + the C files in which they define the functions. + + New Renesas RXv3 port layer. + + Updates to the Synopsys ARC code, including support for EM and HS cores, + and updated BSP. + + Added new POSIX port layer that allows FreeRTOS to run on Linux hosts in + the same way the Windows port layer enables FreeRTOS to run on Windows + hosts. + + Many other minor optimisations and enhancements. For full details + see https://github.com/FreeRTOS/FreeRTOS-Kernel/commits/master + + +Changes between FreeRTOS V10.3.0 and FreeRTOS V10.3.1 released February 18 2020 + + See https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html + + + ./FreeRTOS-Labs directory was removed from this file. The libraries it + contained are now available as a separate download. + +Changes between FreeRTOS V10.2.1 and FreeRTOS V10.3.0 released February 7 2020 + + See https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html + + New and updated kernel ports: + + + Added RISC-V port for the IAR compiler. + + Update the Windows simulator port to use a synchronous object to prevent + a user reported error whereby a task continues to run for a short time + after being moved to the Blocked state. Note we were not able to + replicate the reported issue and it likely depends on your CPU model. + + Correct alignment of stack top in RISC-V port when + configISR_STACK_SIZE_WORDS is defined to a non zero value, which causes + the interrupt stack to be statically allocated. + + The RISC-V machine timer compare register can now be for any HART, whereas + previously it was always assumed FreeRTOS was running on HART 0. + + Update the sequence used to update the 64-bit machine timer + compare register on 32-bit cores to match that suggested in RISC-V + documentation. + + Added tickless low power modes into the ARM, IAR and GCC Cortex-M0 compiler + ports. + + Updated the behaviour of the ARMv7-M MPU (Memory Protection Unit) ports to + match that of the ARMv8-M ports whereby privilege escalations can only + originate from within the kernel's own memory segment. Added + configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY configuration constant. + + Update existing MPU ports to correctly disable the MPU before it is + updated. + + Added contributed port and demo application for a T-Head (formally C-SKY) + microcontroller. + + New API functions: + + + Added the vPortGetHeapStats() API function which returns information on + the heap_4 and heap_5 state. + + Added xTaskCatchUpTicks(), which corrects the tick count value after the + application code has held interrupts disabled for an extended period. + + Added xTaskNotifyValueClear() API function. + + Added uxTimerGetReloadMode() API function. + + Other miscellaneous changes: + + Change type of uxPendedTicks from UBaseType_t to TickType_t to ensure it + has the same type as variables with which it is compared to, and therefore + also renamed the variable xPendingTicks. + + Update Keil projects that use the MPU so memory regions come from linker + script (scatter file) variables instead of being hard coded. + + Added LPC51U68 Cortex-M0+ demos for GCC (MCUXpresso), Keil and IAR + compilers. + + Added CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube demo. + + Added LPC54018 MPU demo. + + Rename xTaskGetIdleRunTimeCounter() to ulTaskGetIdleRunTimeCounter(). + + +Changes between FreeRTOS V10.2.1 and FreeRTOS V10.2.0 released May 13 2019: + + + Added ARM Cortex-M23 port layer to complement the pre-existing ARM + Cortex-M33 port layer. + + The RISC-V port now automatically switches between 32-bit and 64-bit + cores. + + Introduced the portMEMORY_BARRIER macro to prevent instruction re-ordering + when GCC link time optimisation is used. + + Introduced the portDONT_DISCARD macro to the ARMv8-M ports to try and + prevent the secure side builds from removing symbols required by the + non secure side build. + + Introduced the portARCH_NAME to provide additional data to select semi- + automated build environments. + + Cortex-M33 and Cortex-M23 ports now correctly disable the MPU before + updating the MPU registers. + + + Added Nuvoton NuMaker-PFM-M2351 ARM Cortex-M23 demo. + + Added LPC55S69 ARM Cortex-M33 demo. + + Added an STM32 dual core AMP stress test demo. + + +Changes between FreeRTOS V10.1.1 and FreeRTOS V10.2.0 released February 25 2019: + + + Added GCC RISC-V MCU port with three separate demo applications. + + Included pre-existing ARM Cortex-M33 (ARMv8-M) GCC/ARMclang and IAR ports + with Keil simulator demo. + + Update the method used to detect if a timer is active. Previously the + timer was deemed to be inactive if it was not referenced from a list. + However, when a timer is updated it is temporarily removed from, then + re-added to a list, so now the timer's active status is stored separately. + + Add vTimerSetReloadMode(), xTaskGetIdleRunTimeCounter(), and + xTaskGetApplicationTaskTagFromISR() API functions. + + Updated third party Xtensa port so it is MIT licensed. + + Added configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H to the Renesas + compiler RX600v2 port to enable switching between platform.h and + iodefine.h includes within that port's port.c file. + + Removed the 'FromISR' functions from the MPU ports as ISRs run privileged + anyway. + + Added uxTaskGetStackHighWaterMark2() function to enable the return type to + be changed without breaking backward compatibility. + uxTaskGetStackHighWaterMark() returns a UBaseType_t as always, + uxTaskGetStackHighWaterMark2() returns configSTACK_DEPTH_TYPE to allow the + user to determine the return type. + + Fixed issues in memory protected ports related to different combinations + of static memory only and dynamic memory only builds. As a result the + definition of tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE became more + complex and was moved to FreeRTOS.h with a table explaining its definition. + + Added a 'get task tag from ISR' function. + + Change the method used to determine if a timer is active or not from just + seeing if it is referenced from the active timer list to storing its + active state explicitly. The change prevents the timer reporting that it + is inactive while it is being moved from one list to another. + + The pcName parameter passed into the task create functions can be NULL, + previously a name had to be provided. + + When using tickless idle, prvResetNextTaskUnblockTime() is now only called + in xTaskRemoveFromEventList() if the scheduler is not suspended. + + Introduced portHAS_STACK_OVERFLOW_CHECKING, which should be set to 1 for + FreeRTOS ports that run on architectures that have stack limit registers. + + +Changes between FreeRTOS V10.1.0 and FreeRTOS V10.1.1 released 7 September 2018 + + + Reverted a few structure name changes that broke several kernel aware + debugger plug-ins. + + Updated to the latest trace recorder code. + + Fixed some formatting in the FreeRTOS+TCP TCP/IP stack code. + + Reverted moving some variables from file to function scope as doing so + broke debug scenarios that require the static qualifier to be removed. + +Changes between FreeRTOS V10.0.1 and FreeRTOS V10.1.0 released 22 August 2018 + + FreeRTOS Kernel Changes: + + + Update lint checked MISRA compliance to use the latest MISRA standard, was + previously using the original MISRA standard. + + Updated all object handles (TaskHandle_t, QueueHandle_t, etc.) to be + unique types instead of void pointers, improving type safety. (this was + attempted some years back but had to be backed out due to bugs in some + debuggers). Note this required the pvContainer member of a ListItem_t + struct to be renamed - set configENABLE_BACKWARD_COMPATIBILITY to 1 if + this causes an issue. + + Added configUSE_POSIX_ERRNO to enable per task POSIX style errno + functionality in a more user friendly way - previously the generic thread + local storage feature was used for this purpose. + + Added Xtensa port and demo application for the XCC compiler. + + Changed the implementation of vPortEndScheduler() for the Win32 port to + simply call exit( 0 ). + + Bug fix in vPortEnableInterrupt() for the GCC Microblaze port to protect + the read modify write access to an internal Microblaze register. + + Fix minor niggles when the MPU is used with regards to prototype + differences, static struct size differences, etc. + + The usStackHighWaterMark member of the TaskStatus_t structure now has type + configSTACK_DEPTH_TYPE in place of uint16_t - that change should have been + made when the configSTACK_DEPTH_TYPE type (which gets around the previous + 16-bit limit on stack size specifications) was introduced. + + Added the xMessageBufferNextLengthBytes() API function and likewise stream + buffer equivalent. + + Introduce configMESSAGE_BUFFER_LENGTH_TYPE to allow the number of bytes + used to hold the length of a message in the message buffer to be reduced. + configMESSAGE_BUFFER_LENGTH_TYPE default to size_t, but if, for example, + messages can never be more than 255 bytes it could be set to uint8_t, + saving 3 bytes each time a message is written into the message buffer + (assuming sizeof( size_t ) is 4). + + Updated the StaticTimer_t structure to ensure it matches the size of the + Timer_t structure when the size of TaskFunction_t does not equal the size + of void *. + + Update various Xilinx demos to use 2018.1 version of the SDK tools. + + Various updates to demo threads to maintain test coverage. + + FreeRTOS+UDP was removed in FreeRTOS V10.1.0 as it was replaced by + FreeRTOS+TCP, which was brought into the main download in FreeRTOS + V10.0.0. FreeRTOS+TCP can be configured as a UDP only stack, and + FreeRTOS+UDP does not contain the patches applied to FreeRTOS+TCP. + + FreeRTOS+TCP Changes: + + + Multiple security improvements and fixes in packet parsing routines, DNS + caching, and TCP sequence number and ID generation. + + Disable NBNS and LLMNR by default. + + Add TCP hang protection by default. + + We thank Ori Karliner of Zimperium zLabs Team for reporting these issues. + + +Changes between FreeRTOS V10.0.0 and FreeRTOS V10.0.1, released December 20 2017 + + + Fix position of "#if defined( __cplusplus )" in stream_buffer.h. + + Correct declarations of MPU_xQueuePeek() and MPU_xQueueSemaphoreTake() in + mpu_prototypes.h. + + Correct formatting in vTaskList() helper function when it prints the state + of the currently executing task. + + Introduce #error if stream_buffer.c is built without + configUSE_TASK_NOTIFICATIONS set to 1. + + Update FreeRTOS+TCP to V2.0.0 + - Improve the formatting of text that displays the available netword + interfaces when FreeRTOS+TCP is used on Windows with WinPCap. + - Introduce ipconfigSOCKET_HAS_USER_WAKE_CALLBACK option to enable a user + definable callback to execute when data arrives on a socket. + +Changes between FreeRTOS V9.0.1 and FreeRTOS V10.0.0: + + The FreeRTOS kernel is now MIT licensed: https://www.FreeRTOS.org/license + + New Features and components: + + + Stream Buffers - see https://www.FreeRTOS.org/RTOS-stream-buffer-example.html + + Message Buffers - see https://www.FreeRTOS.org//RTOS-message-buffer-example.html + + Move FreeRTOS+TCP into the main repository, along with the basic Win32 + TCP demo FreeRTOS_Plus_TCP_Minimal_Windows_Simulator. + + New ports or demos: + + + Added demo for TI SimpleLink CC3220 MCU. + + Added MPU and non MPU projects for Microchip CEC and MEC 17xx and 51xx + MCUs. + + Added CORTEX_MPU_Static_Simulator_Keil_GCC demo to test static allocation + in the MPU port. + + Fixes or enhancements: + + + Cortex-M ports push additional register prior to calling + vTaskSwitchContext to ensure 8-byte alignment is maintained. Only + important if a user defined tick hook function performs an operation that + requires 8-byte alignment. + + Optimisations to the implementation of the standard tickless idle mode on + Cortex-M devices. + + Improvements to the Win32 port including using higher priority threads. + + Ensure interrupt stack alignment on PIC32 ports. + + Updated GCC TriCore port to build with later compiler versions. + + Update mpu_wrappers.c to support static allocation. + + The uxNumberOfItems member of List_t is now volatile - solving an issue + when the IAR compiler was used with maximum optimization. + + Introduced configRECORD_STACK_HIGH_ADDRESS. When set to 1 the stack start + address is saved into each task's TCB (assuming stack grows down). + + Introduced configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H to allow user defined + functionality, and user defined initialisation, to be added to FreeRTOS's + threads.c source file. When configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H is + set to 1 a user provided header file called freertos_task_c_additions.h + will be included at the bottom of threads.c. Functions defined in that + header file can call freertos_tasks_c_additions_init(), which in turn + calls a macro called FREERTOS_TASKS_C_ADDITIONS_INIT(), if it is defined. + FREERTOS_TASKS_C_ADDITIONS_INIT() can be defined in FreeRTOSConfig.h. + + Introduced configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( x ) which can be + defined by a user in FreeRTOSConfig.h. The macro is called before + assessing whether to enter tickless idle mode or not. If the macro sets + x to zero then tickless idle mode will not be entered. This allows users + to abort tickless idle mode entry before the tickless idle function is + even called - previously it was only possible to abort from within the + tickless idle function itself. + + Added configPRINTF(), which can be defined by users to allow all libraries + to use the same print formatter. + + Introduced configMAX() and configMIN() macros which default to standard + max( x, y ) and min( x, y ) macro behaviour, but can be overridden if the + application writer defines the same macros in FreeRTOSConfig.h. + + Corrected the definition of StaticTask_t in the case where + INCLUDE_xTaskAbortDelay is set to 1. + + Introduced configTIMER_SERVICE_TASK_NAME and configIDLE_TASK_NAME, both of + which can be defined to strings in FreeRTOSConfig.h to change the default + names of the timer service and idle threads respectively. + + Only fill the stack of a newly created task with a known value if stack + checking, or high water mark checking/viewing, is in use - removing the + dependency on memset() in other cases. + + Introduced xTaskCreateRestrictedStatic() so static allocation can be used + with the MPU. + + Ensure suspended threads cannot be unsuspended by a received task + notification. + + Fix race condition in vTaskSetTimeOutState(). + + Updated trace recorder files to the latest version. + +Changes since FreeRTOS V9.0.0: + + + Priority dis-inheritance behaviour has been enhanced in the case where a + task that attempted to take a mutex that was held by a lower priority task + timed out before it was able to obtain the mutex (causing the task that + holds the mutex to have its priority raised, then lowered again, in + accordance with the priority inheritance protocol). + + Split the overloaded xQueueGenericReceive() function into three separate + dedicated functions. + + Allow the default human readable text names given to the Idle and Timer + threads to be overridden by defining the configIDLE_TASK_NAME and + configTIMER_SERVICE_TASK_NAME definitions respectively in FreeRTOSConfig.h. + + Introduced configINITIAL_TICK_COUNT to allow the tick count to take a + value of than than 0 when the system boots. This can be useful for + testing purposes - although setting configUSE_16_BIT_TICKS to 1 can also + be used to test frequent tick overflows. + + Ensure the Cortex-M SysTick count is cleared to zero before starting the + first task. + + Add configASSERT() into ARM Cortex-M ports to check the number of priority + bit settings. + + Clear the 'control' register before starting ARM Cortex-M4F ports in case + the FPU is used before the scheduler is started. This just saves a few + bytes on the main stack as it prevents space being left for a later save + of FPU registers. + + Added xSemaphoreGetMutexHolderFromISR(). + + Corrected use of portNVIC_PENDSVSET to portNVIC_PENDSVSET_BIT in MPU ports. + + Introduced configSTACK_DEPTH_TYPE to allow users to change the type used + to specify the stack size when using xTaskCreate(). For historic reasons, + when FreeRTOS was only used on small MCUs, the type was set to uint16_t, + but that can be too restrictive when FreeRTOS is used on larger + processors. configSTACK_DEPTH_TYPE defaults to uint16_t. + xTaskCreateStatic(), being a newer function, used a uint32_t. + + Increase the priority of the Windows threads used by the Win32 port. As + all the threads run on the same core, and the threads run with very high + priority, there is a risk that the host will become unresponsive, so also + prevent the Windows port executing on single core hosts. + +Changes between FreeRTOS V9.0.0 and FreeRTOS V9.0.0rc2 released May 25 2016: + + See https://www.FreeRTOS.org/FreeRTOS-V9.html + + RTOS kernel updates: + + + The prototype of the new xTaskCreateStatic() API function was modified to + remove a parameter and improve compatibility with other new + "CreateStatic()" API functions. The stack size parameter in + xTaskCreateStatic() is now uint32_t, which changes the prototype of the + callback functions. See the following URL: + https://www.FreeRTOS.org/xTaskCreateStatic.html + + GCC ARM Cortex-A port: Introduced the configUSE_TASK_FPU_SUPPORT + constant. When configUSE_TASK_FPU_SUPPORT is set to 2 every task is + automatically given a floating point (FPU) context. + + GCC ARM Cortex-A port: It is now possible to automatically save and + restore all floating point (FPU) registers on entry to each potentially + nested interrupt by defining vApplicationFPUSafeIRQHandler() instead of + vApplicationIRQHandler(). + + All ARM Cortex-M3/4F/7 ports: Clear the least significant bit of the task + entry address placed onto the stack of a task when the task is created for + strict compliance with the ARM Cortex-M3/4/7 architecture documentation + (no noticeable effect unless using the QMEU emulator). + + Added GCC and Keil ARM Cortex-M4F MPU ports - previously the MPU was only + supported on ARM Cortex-M3. + + ARM Cortex-M3/4F MPU ports: Update to fully support the FreeRTOS V9.0.0 + API (other than static object creation) and added the + FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC demo application to + demonstrate how to use the updated MPU port. + + All ARM Cortex-M3/4F/7 ports: Add additional barrier instructions to the + default low power tickless implementation. + + All ARM Cortex-M0 ports: Prevent an item being left on the stack of the + first task that executes. + + Win32 ports: Reduce the amount of stack used and change the way Windows + threads are deleted to increase the maximum execution time. + + Add an ARM Cortex-M4F port for the MikroC compiler. Ensure to read the + documentation page for this port before use. + + MPS430X IAR port: Update to be compatible with the latest EW430 tools + release. + + IAR32 GCC port: Correct vPortExitCritical() when + configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY. + + For consistency vTaskGetTaskInfo() now has the alias vTaskGetInfo(), + xTaskGetTaskHandle() now has the alias xTaskGetHandle() and + pcQueueGetQueueName() now has an alias pcQueueGetName(). + + Fix various errors in comments and compiler warnings. + + Demo application updates: + + + Update Atmel Studio projects to use Atmel Studio 7. + + Update Xilinx SDK projects to use the 2016.1 version of the SDK. + + Remove dependency on legacy IO libraries from the PIC32 demos. + + Move the Xilinx UltraScale Cortex-R5 demo into the main distribution. + + Update the MSP432 libraries to the latest version. + + Add Microchip CEC1302 (ARM Cortex-M4F) demos for GCC, Keil and MikroC + compilers. + + Move the Atmel SAMA5D2 demo into the main distribution. + +Changes between FreeRTOS V9.0.0rc1 and FreeRTOS V9.0.0rc2 (release candidate 2) +released March 30 2016: + + NOTE - See https://www.FreeRTOS.org/FreeRTOS-V9.html for details + + + The functions that create RTOS objects using static memory allocation have + been simplified and will not revert to using dynamic allocation if a + buffer is passed into a function as NULL. + + Introduced the configSUPPORT_DYNAMIC_ALLOCATION configuration constant to + allow a FreeRTOS application to be built without a heap even being being + defined. The Win32 example located in the + /FreeRTOS/demo/WIN32-MSVC-Static-Allocation-Only directory is provided as + a reference for projects that do not include a FreeRTOS heap. + + Minor run-time optimisations. + + Two new low power tickless implementations that target Silicon Labs EFM32 + microcontrollers. + + Addition of the xTimerGetPeriod() and xTimerGetExpireTime() API functions. + +Changes between FreeRTOS V8.2.3 and FreeRTOS V9.0.0rc1 (release candidate 1) +released February 19 2016: + + RTOS Kernel Updates: + + + Major new feature - threads, semaphores, queues, timers and event groups can + now be created using statically allocated memory, so without any calls to + pvPortMalloc(). + + Major new features - Added the xTaskAbortDelay() API function which allows + one task to force another task to immediately leave the Blocked state, + even if the event the blocked task is waiting for has not occurred, or the + blocked task's timeout has not expired. + + Updates necessary to allow FreeRTOS to run on 64-bit architectures. + + Added vApplicationDaemonTaskStartupHook() which executes when the RTOS + daemon task (which used to be called the timer service task) starts + running. This is useful if the application includes initialisation code + that would benefit from executing after the scheduler has been started. + + Added the xTaskGetTaskHandle() API function, which obtains a task handle + from the task's name. xTaskGetTaskHandle() uses multiple string compare + operations, so it is recommended that it is called only once per task. + The handle returned by xTaskGetTaskHandle() can then be stored locally for + later re-use. + + Added the pcQueueGetQueueName() API function, which obtains the name of + a queue from the queue's handle. + + Tickless idling (for low power applications) can now also be used when + configUSE_PREEMPTION is 0. + + If one task deletes another task, then the stack and TCB of the deleted + task is now freed immediately. If a task deletes itself, then the stack + and TCB of the deleted task are freed by the Idle task as before. + + If a task notification is used to unblock a task from an ISR, but the + xHigherPriorityTaskWoken parameter is not used, then pend a context switch + that will then occur during the next tick interrupt. + + Heap_1.c and Heap_2.c now use the configAPPLICATION_ALLOCATED_HEAP + settings, which previously was only used by heap_4.c. + configAPPLICATION_ALLOCATED_HEAP allows the application writer to declare + the array that will be used as the FreeRTOS heap, and in-so-doing, place + the heap at a specific memory location. + + TaskStatus_t structures are used to obtain details of a task. + TaskStatus_t now includes the bae address of the task's stack. + + Added the vTaskGetTaskInfo() API function, which returns a TaskStatus_t + structure that contains information about a single task. Previously this + information could only be obtained for all the threads at once, as an array + of TaskStatus_t structures. + + Added the uxSemaphoreGetCount() API function. + + Replicate previous Cortex-M4F and Cortex-M7 optimisations in some + Cortex-M3 port layers. + + Demo Application Updates: + + Further demo applications will be added prior to the final FreeRTOS V9 + release. + + + Updated SAM4L Atmel Studio project to use Atmel Studio 7. + + Added ARM Cortex-A53 64-bit port. + + Added a port and demo for the ARM Cortex-A53 64-bit cores on the Xilinx + Ultrascale MPSoC. + + Added Cortex-M7 SAME70 GCC demo. + + Added EFM32 Giant and Wonder Gecko demos. + + +Changes between V8.2.2 and V8.2.3 released October 16, 2015 + + RTOS kernel updates: + + + Fix bug identified in a modification made in V8.2.2 to the software timer + code that allows tickless low power applications to sleep indefinitely + when software timers are used. + + Simplify and improve efficiency of stack overflow checking. + + Add xTaskNotifyStateClear() API function. + + New IAR and GCC Cortex-R ports for microprocessors that do not use an ARM + generic interrupt controller (GIC). + + New PIC32MEC14xx port. + + Add support for PIC32MZ EF parts (with floating point) into the PIC32MZ + port. + + Zynq7000 port layer now declares the functions that setup and clear the + tick interrupt as weak symbols so they can be overridden by the + application, and uses a global XScuGic object so the same object can be + used by the application code. + + Introduced configUSE_TASK_FPU_SUPPORT, although the PIC32MZ EF port is + currently the only port that uses it. + + Updates to RL78 and 78K0 IAR port layers to improve support for + combinations of memory models. + + Minor updates to heap_5.c to remove compiler warnings generated by some + compilers. + + License simplifications. See /FreeRTOS/License/license.txt in the + official distribution. + + FreeRTOS+ updates: + + + Update directory names to use WolfSSL instead of CyaSSL, inline with + WolfSSL's re-branding. + + Update to latest WolfSSL code. + + Update to latest FreeRTOS+Trace recorder code. + + Add in the FreeRTOS+Trace recorder library required for streaming trace. + + Demo application changes: + + + Add demo applications for Renesas RZ/T (Cortex-R), PIC32MZ EF (PIC32 with + floating point hardware), PIC32MEC14xx, RX71M, RX113 and RX231. + + General tidy up of spelling and compiler warnings. + + +Changes between V8.2.1 and V8.2.2 released August 12, 2015 + + RTOS kernel updates: + + + Added Intel IA32/x86 32-bit port. + + General maintenance. + + PRIVILEGED_FUNCTION and PRIVILEGED_DATA macros, which are used in memory + protected systems, have been added to the newer event group and software + timer functions. + + Add the errno definitions used by FreeRTOS+ components into projdefs.h. + + Remove the restriction that prevented tick-less idle implementations + waiting indefinitely when software timers were used in the same + application. + + Introduce xTaskNotifyAndQueryFromISR() as the interrupt safe version of + xTaskNotifyAndQuery(). + + Add additional NOPs to the MSP430X port layers to ensure strict compliance + with the hardware documentation. + + Microblaze port: Added option for port optimised task selection. + + Microblaze port: Previously threads inherited the exception enable state + at the time the task was created. Now all threads are created with + exceptions enabled if the Microblaze design supports exceptions. + + Windows port: Add additional safe guards to ensure the correct start up + sequence and thread switching timing. + + Windows port: Improve the implementation of the port optimised task + selection assembly code. + + Update heap_4 and heap_5 to allow use on 64-bit processors. + + Simplify the code that creates a queue. + + General improved tick-less idle behaviour. + + Ensure none of the variables in the common kernel files are initialised to + anything other than zero. + + Correct calculation of xHeapStructSize in heap_4 and heap_5. + + Demo application updates: + + + Added demo project for the new IA32/x86 port that targets the Galileo + hardware. + + Added MSP430FR5969 demos (previously provided as a separate download). + + Added FreeRTOS BSP repository for automatic creation of FreeRTOS + applications in the Xilinx SDK. + + Added Atmel Studio / GCC project for the SAMV71 (ARM Cortex-M7) + + Update Xilinx SDK projects to use version 2015.2 of the SDK. + + Remove Microblaze demos that were using obsolete tools. + + Add MSP43FR5969 IAR and CCS demos. + + FreeRTOS+ Updates: + + + Updated FreeRTOS+Trace recorder library, which requires an update to the + FreeRTOS+Trace application. + + Added Reliance Edge source code and demo application. Reliance edge is + a fail safe transactional file system ideal for applications that require + file storage, and especially when high reliability is essential. + + Introduce configAPPLICATION_PROVIDES_cOutputBuffer to allow FreeRTOS+CLI + users to place the output buffer at a fixed memory address. + + Improve the NetworkInterface.c file provided for the Windows port of + FreeRTOS+UDP. + +Changes between V8.2.0 and V8.2.1 released 24th March 2015. + + RTOS kernel updates: + + + Added user definable and flexible thread local storage facility. + + Added vTimerSetTimerID() API function to complement the pvTimerGetTimerID() + function to allow the timer's ID to be used as timer local storage. + + Fixed a potential issue related to the use of queue sets from an ISR. + + Some updates to the Xilinx Microblaze GCC port. + + Added ARM Cortex-M4F port for Texas Instruments Code Composer Studio. + + Added ARM Cortex-M7 r0p1 port layer for IAR, GCC and Keil which contains a + minor errata work around. All other ARM Cortex-M7 core revisions should + use the ARM Cortex-M4F port. + + Exclude the whole of croutine.c if configUSE_CO_ROUTINES is set to 0. + + Change some data types from uint32_t to size_t in preparation for 64-bit + Windows port. + + Update the PIC32 port to remove deprecation warnings output by the latest + XC32 compilers. + + Fix bug when xQueueOverwrite() and xQueueOverwrite() from ISR are used to + overwrite items in two queues that are part of the same set. + + Demo application updates: + + + Added demo application for TI's ARM Cortex-M4F based MSP432 + microcontroller using IAR, Keil and CCS compilers. + + Added demo application for STM32F ARM Cortex-M7 based microcontroller + using IAR and Keil. + + Added demo application for Atmel SAMV71 ARM Cortex-M7 based + microcontroller using IAR and Keil. + + Added Microblaze demo that uses the 2014.4 version of the Xilinx SDK and + runs on the KC705 evaluation board (Kintex FPGA). + +Changes between V8.1.2 and V8.2.0 released 16th January 2015 + + Changes between release candidate 1 and the official release are restricted + to maintenance only. + + Significant RTOS kernel updates: + + + MAJOR NEW FEATURE! Task notifications. Please see the following URL for + details: https://www.FreeRTOS.org/RTOS-task-notifications.html + + NEW HEADER FILE REQUIRED! Obsolete definitions have been separated into + a new header file called FreeRTOS/Source/include/deprecated_definitions.h. + This header file must be present to build. Note some of the obsolete + definitions are still used by very old demo application projects. + + Other RTOS kernel updates: + + + Made xSemaphoreGiveFromISR() a function rather than a macro that calls + xQueueGenericSendFromISR(). This allows for major performance + enhancements at the expense of some additional code size if both functions + are used in the same application. NOTE: In most uses cases such use of + a semaphore can now be replaced with a task notification which is smaller + and faster still. + + The TCB is now always allocated such that the task's stack grows away from + the TCB (improves debugging of stack overflows as the overflow will not + overwrite the task's name). + + GCC, IAR and Keil Cortex-M4F ports now use more inlining (performance + enhancements at the cost of a little additional code space). + + Queues are now allocated with a single call to pvPortMalloc() which + allocates both the queue structure and the queue storage area. + + Introduced a new critical section macro for reading the tick count that + defines away to nothing in cases where the width of the tick allows the + tick count to be read atomically (performance benefits - especially when + optimisation is on). + + Introduced configAPPLICATION_ALLOCATED_HEAP in heap_4.c to allow the + application writer to provide their own heap array - and in so doing + control the location of the heap. + + Introduced configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES which, when set, will + include known values in both list and list item structures. The values + are intended to assist debugging. If the values get overwritten then it + is likely application code has written over RAM used by the kernel. + + configASSERT()s in all Cortex-M ports used to test the lowest 5 bits of + the interrupt control register to detect taskENTER_CRITICAL() being called + from an interrupt. This has been changed to test all 8 bits. + + Introduced uxTaskPriorityGetFromISR(). + + Microblze V8 port now tests XPAR_MICROBLAZE_0_USE_FPU for inequality to 0 + rather than equality to 1, and 2 and 3 are also valid values. + + Cortex-A5 GIC-less port no longer passes the address of the interrupting + peripheral into the interrupt handler. + + Fix an issue in FreeRTOS-MPU where an attempt was made to free the stack + belonging to a task when the task was deleted, even when the stack was + allocated statically. + + Utility (helper) functions that format task statistic information into + human readable tables now pad task names with spaces to ensure columns + line up correctly even where task name lengths vary greatly. + + Update FreeRTOS+Trace recorder library to version 2.7.0. + + Demo application updates: + + + Added two new standard demo task sets: IntSemTest and TaskNotify. + + Added port and demo application for Atmel SAMA5D4 Cortex-A5 MPU. + + Added demo application for Altera Cyclone V Cortex-A9 MPU. + + Updated Zynq demo to use version 2014.4 of Xilinx's SDK and added in + demo threads for new RTOS features. + + Updated Atmel SAM4E and SAM4S demos to include a lot of additional test + and demo threads. + + Fixed a corner case issue in Atmel SAM4L low power tickless + implementation, and added button interrupt handling. + + Make the interrupt queue tests more tolerant to heave CPU loads. + + Updated MSVC FreeRTOS simulator demo to include the latest standard test + and demo threads. + + Updated MingW/Eclipse FreeRTOS simulator demo to match the FreeRTOS MSVC + simulator demo. + + Updated all demos that use FreeRTOS+Trace to work with the latest trace + recorder code. + + +Changes between V8.1.1 and V8.1.2 released September 2nd 2014 + + Move the defaulting of configUSE_PORT_OPTIMISED_TASK_SELECTION into the + individual port layers where necessary so it does not affect ports that do + not support the definition. + +Changes between V8.1.0 and V8.1.1 released August 29th 2014 + + By popular requests - a minor patch to V8.1.0 to re-instate the ability to + give a mutex type semaphore (with priority inheritance) from an interrupt + handler. + +Changes between V8.0.1 and V8.1.0 released August 26th 2014 + + FreeRTOS scheduler, kernel, demo and test updates: + + + Improved the priority inheritance algorithms to assist integration with + off the shelf middleware that may hold multiple mutexes simultaneously. + + Introduce heap_5.c, which is similar to heap_4.c but allows the heap to + span multiple non-contiguous memory regions. + + Updated all Cortex-A9 ports to help trap a couple of common usage errors - + the first being when a task incorrectly attempts to exit its implementing + function and the second being when a non interrupt safe API function is + called from an interrupt. + + Update all Cortex-A9 ports to remove obsolete mode switches prior to + restoring a task context. + + configUSE_PORT_OPTIMISED_TASK_SELECTION now defaults to 1 instead of 0. + + Update all Cortex-M3/4F ports to trap a non interrupt safe API function + being called from an interrupt handler. + + Simplify the alignment checks in heap_4.c. + + Update the MSVC Windows simulator demo to use heap_5.c in place of + heap_4.c to ensure end users have an example to refer to. + + Updated standard demo test code to test the new priority inheritance + algorithms. + + Updated the standard demo threads to make use of stdint and the FreeRTOS + specific typedefs that were introduced in FreeRTOS V8.0.0. + + Introduce the pdMS_TO_TICKS() macro as a more user friendly and intuitive + alternative to pdTICKS_PER_MS - both of which can be used to convert a + time specified in milliseconds to a time specified in RTOS ticks. + + Fix a bug in the Tasking compiler's Cortex-M port that resulted in an + incorrect value being written to the basepri register. This only effects + users of the Tasking compiler. + + Update the Zynq demo to use version 2014.2 of the SDK and add in an lwIP + example that demonstrates lwIP being used with both its raw and sockets + interfaces. + + Updated the CCS Cortex-R4 port to enable it to be built with the latest + CCS compiler. + + New ports and demo applications: + + + Two Renesas RX64M ports (RXv2 core) and demos introduced, one for the GCC + compiler and one for the Renesas compiler. Both demos use e2 studio. + + Generic IAR Cortex-A5 port (without any reliance on a GIC) introduced. + The new port is demonstrated on an Atmel SAMA5D3 XPlained board. + + FreeRTOS+ component updates: + + + Update CyaSSL to the latest version. + + Updated the FreeRTOS+ components supplied directly by Real Time Engineers + Ltd. to make use of stdint and the FreeRTOS specific typedefs that were + introduced in FreeRTOS V8.0.0. + + Rework and simplify the FreeRTOS+FAT SL RAM disk driver. + + Miscellaneous updates and maintenance: + + + Update the IAR and DS-5/ARM RZ demos to target the official RZ RSK + hardware in place of the previously targeted Renesas internal (not + publicly available) hardware. + + Various other maintenance threads. + + +Changes between V8.0.0 and V8.0.1 released 2nd May 2014 + + + Minor fixes to the event group functionality that was released in V8.0.0. + The 'clear bits from ISR' functionality is now implemented using a + deferred interrupt callback instead of a function, and the 'wait bits' and + 'task sync' functions now correctly clear internal control bits before + returning a value in every possible path through the respective functions. + + Ensure the updating of internal control data is protected by a critical + section after a task is deleted or suspended. + + Minor fixes to FreeRTOS+FAT SL - namely seeking beyond the end of a file + when the offset was not a multiple of the sector size. + + Ensure Cortex-A9 system registers are only ever accessed as 32-bit values, + even when only the lest significant byte of the register is implemented. + + Other updates: + + + Updated the XMC4200 IAR project so it links with version 7.x of the IAR + tools. + + Add RL78L1C demo. + + Add pcTimerGetName() API function. + + Call _reclaim_reent() when a task is deleted if configUSE_NEWLIB_REENTRANT + is defined. + +Changes between V7.6.0 and V8.0.0 released 19th Feb 2014 + + https://www.FreeRTOS.org/upgrading-to-FreeRTOS-V8.html + + FreeRTOS V8.x.x is a drop-in compatible replacement for FreeRTOS V7.x.x, + although a change to the type used to reference character strings may result + in application code generating a few (easily clearable) compiler warnings + after the upgrade, and an updated typedef naming convention means use of the + old typedef names is now discouraged. + See https://www.FreeRTOS.org/upgrading-to-FreeRTOS-V8.html for full + information. + + New features and functionality: + + + Event groups - see https://www.FreeRTOS.org/FreeRTOS-Event-Groups.html + + Centralised deferred interrupt processing - see + https://www.FreeRTOS.org/xTimerPendFunctionCallFromISR.html + + Other updates: + + + Previously, when a task left the Blocked state, a context switch was + performed if the priority of the unblocked task was greater than or equal + to the priority of the Running task. Now a context switch is only + performed if the priority of the unblocked task is greater than the + priority of the Running task. + + New low power tickless demonstration project that targets the ST STM32L + microcontroller - see + https://www.FreeRTOS.org/STM32L-discovery-low-power-tickless-RTOS-demo.html + + Add xPortGetMinimumEverFreeHeapSize() to heap_4.c. + + Small change to the tickless low power implementation on the SAM4L to + ensure the alarm value (compare match value) cannot be set to zero when a + tickless period is exited due to an interrupt originating from a source + other than the RTOS tick. + + Update the GCC/Eclipse Win32 simulator demo to make better use of Eclipse + resource filters and match the functionality of the MSVC equivalent. + + xTaskIsTaskSuspended() is no longer a public function. Use + eTaskGetState() in its place. + + Improved trace macros, including tracing of heap usage. + + Remove one level of indirection when accepting interrupts on the PIC32MZ. + + Add Cortex-A9 GCC port layer. + + Add Xilinx Zynq demo application. + + +Changes between V7.5.3 and V7.6.0 released 18th November 2013 + + V7.6.0 changes some behaviour when the co-operative scheduler is used (when + configUSE_PREEMPTION is set to 0). It is important to note that the + behaviour of the pre-emptive scheduler is unchanged - the following + description only applies when configUSE_PREEMPTION is set to 0: + + WHEN configUSE_PREEMPTION IS SET TO 0 (which is in a small minority of + cases) a context switch will now only occur when a task places itself into + the Blocked state, or explicitly calls taskYIELD(). This differs from + previous versions, where a context switch would also occur when implicitly + moving a higher priority task out of the Blocked state. For example, + previously, WHEN PREEMPTION WAS TURNED OFF, if task A unblocks task B by + writing to a queue, then the scheduler would switch to the higher priority + task. Now, WHEN PREEMPTION IS TURNED OFF, if task A unblocks task B by + writing to a queue, task B will not start running until task A enters the + Blocked state or task A calls taskYIELD(). [If configUSE_PREEMPTION is not + set to 0, so the normal pre-emptive scheduler is being used, then task B + will start running immediately that it is moved out of the Blocked state]. + + Other changes: + + + Added a port layer and a demo project for the new PIC32MZ architecture. + + Update the PIC32MX port layer to re-introduce some ehb instructions that + were previously removed, add the ability to catch interrupt stack + overflows (previously only task stack overflows were trapped), and also + add the ability to catch an application task incorrectly attempting to + return from its implementing function. + + Make dramatic improvements to the performance of the Win32 simulator port + layer. + + Ensure threads that are blocked indefinitely report their state as Blocked + instead of Suspended. + + Slight improvement to the Cortex-M4F port layers where previously one + register was inadvertently being saved twice. + + Introduce the xSemaphoreCreateBinary() API function to ensure consistency + in the semantics of how each semaphore type is created. It is no longer + recommended to use vSemaphoreCreateBinary() (the version prefixed with a + 'v'), although it will remain in the code for backward compatibility. + + Update the Cortex-M0 port layers to allow the scheduler to be started + without using the SVC handler. + + Added a build configuration to the PIC32MX MPLAB X demo project that + targets the PIC32 USB II starter kit. Previously all the build + configurations required the Explorer 16 hardware. + + Some of the standard demo threads have been updated to ensure they execute + correctly with the updated co-operative scheduling behaviour. + + Added comprehensive demo for the Atmel SAM4E, including use of + FreeRTOS+UDP, FreeRTOS+FAT SL and FreeRTOS+CLI. + + FreeRTOS+ Changes: + + + Minor maintenance on FreeRTOS+UDP. + +Changes between V7.5.2 and V7.5.3 released October 14 2013 + + Kernel changes: + + + Prior to V7.5.x yields requested from the tick hook would occur in the + same tick interrupt - revert to that original behaviour. + + New API function uxQueueSpacesAvailable(). + + Introduced the prvTaskExitError() function to Cortex-M0, Cortex-M3/4 + and Cortex-M4F ports. prvTaskExitError() is used to trap threads that + attempt to return from their implementing functions (threads should call + vTaskDelete( NULL ); if they want to exit). + + The Cortex-M0 version of portSET_INTERRUPT_MASK_FROM_ISR and + portCLEAR_INTERRUPT_MASK_FROM_ISR are now fully nestable. + + Improved behaviour and robustness of the default Cortex-M tickless idle + behaviour. + + Add workaround for silicon errata PMU_CM001 in Infineon XMC4000 devices to + all Cortex-M4F ports. + + Add Cortex-M0 port for Keil. + + Updated Cortus port. + + Ensure _impure_ptr is initialised before the scheduler is started. + Previously it was not set until the first context switch. + + FreeRTOS+ changes: + + + Update FreeRTOS+UDP to V1.0.1 - including direct integration of the + FreeRTOS+Nabto task, improvements to the DHCP behaviour, and a correction + to the test that prevents the network event hook being called on the first + network down event. The FreeRTOS+UDP change history is maintained + separately. + + Correct the __NVIC_PRIO_BITS setting in the LPC18xx.h header files + provided in the NXP CMSIS library, then update the interrupts used by the + LPC18xx demos accordingly. + + Replace double quotes (") with single quotes (') in FreeRTOS+CLI help + strings to ensure the strings can be used with the JSON descriptions used + in the FreeRTOS+Nabto demos. + + Demo and miscellaneous changes: + + + Added demo for the Atmel SAMD20 Cortex-M0+. The demo includes + FreeRTOS+CLI + + Added a demo for the Infineon Cortex-M0 that can be built with the IAR + Keil and GCC tools. + + Updated the Infineon XMC4000 demos for IAR, Keil, GCC and Tasking tools, + with additional build configurations to directly support the XMC4200 and + XMC4400 devices, in addition to the previously supported XMC4500. + + Updated the demo application. + + Added additional trace macros traceMALLOC and traceFREE to track heap + usage. + +Changes between V7.5.0 and V7.5.2 released July 24 2013 + + V7.5.2 makes the new Cortex-M vPortCheckInterruptPriority() function + compatible with the STM32 standard peripheral driver library, and adds + an extra critical section to the default low power tickless mode + implementation. Only users of the STM32 peripheral library or the default + tickless implementation need update from version 7.5.0. + +Changes between V7.4.2 and V7.5.0 released July 19 2013 + + V7.5.0 is a major upgrade that includes multiple scheduling and efficiency + improvements, and some new API functions. + + Compatibility information for FreeRTOS users: + FreeRTOS V7.5.0 is backward compatible with FreeRTOS V7.4.0 with one + exception; the vTaskList() and vTaskGetRunTimeStats() functions are now + considered legacy, having been replaced by the single uxTaskGetSystemState() + function. configUSE_STATS_FORMATTING_FUNCTIONS must be set to 1 in + FreeRTOSConfig.h for vTaskList() and vTaskGetRunTimeStats() to be + available. + + Compatibility information for FreeRTOS port writers: + vTaskIncrementTick() is now called xTaskIncrementTick() (because it now + returns a value). + + Headline changes: + + + Multiple scheduling and efficiency improvements. + + Core kernel files now pass PC-Lint V8 static checking without outputting + any warnings (information on the test conditions will follow). + + New API functions: + + + uxTaskGetSystemState() https://www.FreeRTOS.org/uxTaskGetSystemState.html + + xQueueOverwrite() https://www.FreeRTOS.org/xQueueOverwrite.html + + xQueueOverwriteFromISR() + + xQueuePeekFromISR() + + The following ports and demos, which were previously available separately, + are now incorporated into the main FreeRTOS zip file download: + + + ARM Cortex-A9 IAR + + ARM Cortex-A9 ARM compiler + + Renesas RZ + + Microsemi SmartFusion2 + + New FreeRTOSConfig.h settings + https://freertos.org/a00110.html + + + configUSE_TIME_SLICING + + configUSE_NEWLIB_REENTRANT + + configUSE_STATS_FORMATTING_FUNCTIONS + + configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS + + Other changes: + + + (MPU port only) The configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS + options provides a mechanism that allows application writers to execute + certain functions in privileged mode even when a task is running in user + mode. + + Ports that support interrupt nesting now include a configASSERT() that + will trigger if an interrupt safe FreeRTOS function is called from an + interrupt that has a priority designated as above the maximum system/API + call interrupt priority. + + The included FreeRTOS+Trace recorder code has been updated to the latest + version, and the demo applications that use the trace recorder code have + been updated accordingly. + + The FreeRTOS Windows Simulator (MSVC version only) has been updated to + include a new basic 'blinky' build option in addition to the original + comprehensive build option. + + Improve RAM usage efficiency of heap_4.c and heap_2.c. + + Prevent heap_4.c from attempting to free memory blocks that were not + allocated by heap_4.c, or have already been freed. + + As FreeRTOS now comes with FreeRTOS+FAT SL (donated by HCC) the Chan FATfs + files have been removed from FreeRTOS/Demo/Common. + + Fix build error when R4 port is build in co-operative mode. + + Multiple port and demo application maintenance activities. + +Changes between V7.4.1 and V7.4.2 released May 1 2013 + + NOTE: There are no changes in the FreeRTOS kernel between V7.4.1 and V7.4.2 + + + Added FreeRTOS+FAT SL source code and demo project. The demo project + runs in the FreeRTOS Windows simulator for easy and hardware independent + experimentation and evaluation. See https://www.FreeRTOS.org/fat_sl + +Changes between V7.4.0 and V7.4.1 released April 18 2013 + + + To ensure strict conformance with the spec and ensure compatibility with + future chips data and instruction barrier instructions have been added to + the yield macros of Cortex-M and Cortex-R port layers. For efficiency + the Cortex-M port layer "yield" and "yield" from ISR are now implemented + separately as the barrier instructions are not required in the ISR case. + + Added FreeRTOS+UDP into main download. + + Reorganised the FreeRTOS+ directory so it now matches the FreeRTOS + directory with Source and Demo subdirectories. + + Implemented the Berkeley sockets select() function in FreeRTOS+UDP. + + Changed (unsigned) casting in calls to standard library functions with + (size_t) casting. + + Added the Atmel SAM4L and Renesas RX100 demos that demonstrates the + tickless (tick suppression) low power FreeRTOS features. + + Add a new RL78 IAR demo that targets numerous new RL78 chips and + evaluation boards. + + Adjusted stack alignment on RX200 ports to ensure an assert was not + falsely triggered when configASSERT() is defined. + + Updated the Cortex_M4F_Infineon_XMC4500_IAR demo to build with the latest + version of EWARM. + + Corrected header comments in the het.c and het.h files (RM48/TMS570 demo). + + +Changes between V7.3.0 and V7.4.0 released February 20 2013 + + + New feature: Queue sets. See: + https://www.FreeRTOS.org/Pend-on-multiple-rtos-objects.html + + Overhauled the default tickless idle mode implementation provided with the + ARM Cortex-M3 port layers. + + Enhanced tickless support in the core kernel code with the introduction of + the configEXPECTED_IDLE_TIME_BEFORE_SLEEP macro and the + eTaskConfirmSleepModeStatus() function. + + Added the QueueSet.c common demo/test file. Several demo applications + have been updated to use the new demo/test threads. + + Removed reliance on the PLIB libraries from the MPLAB PIC32 port layer and + demo applications. + + Added the FreeRTOS+Trace recorder code to the MSVC Win32 demo. + + Renamed eTaskStateGet() to eTaskGetState() for consistency, and added a + pre-processor macro for backward compatibility with the previous name. + + Updated functions implemented in the core queue.c source file to allow + queue.h to be included from the .c file directly (this prevents compiler + warnings that were generated by some compilers). + + Updated the CCS Cortex-R4 port layer to replace the CLZ assembler function + with the CLZ compiler intrinsic that is provided by the latest versions of + the CCS ARM compiler. + + Updated all heap_x.c implementations to replace the structure that was + used to ensure the start of the heap was aligned with a more portable + direct C code implementation. + + Added support for PIC24 devices that include EDS. + + Minor optimisations to the PIC32 port layer. + + Minor changes to threads.c that allow the state viewer plug-ins to display + additional information. + + Bug fix: Update prvProcessReceivedCommands() in timers.c to remove an + issue that could occur if the priority of the timer daemon task was set + below the priority of threads that used timer services. + + Update the FreeRTOS+Trace recorder code to the latest version. + +Changes between V7.2.0 and V7.3.0 released October 31 2012 + + + Added ability to override the default scheduler task selection mechanism + with implementations that make use of architecture specific instructions. + + Added ability to suppress tick interrupts during idle time, and in so + doing, provide the ability to make use of architecture specific low power + functionality. + + Added the portSUPPRESS_TICKS_AND_SLEEP() macro and vTaskStepTick() helper + function. + + Added the configSYSTICK_CLOCK_HZ configuration constant. + + Reworked the Cortex-M3 and Cortex-M4F port layers for GCC, Keil and IAR to + directly support basic power saving functionality. + + Added hooks to allow basic power saving to be augmented in the application + by making use of chip specific functionality. + + Minor change to allow mutex type semaphores to be used from interrupts + (which would not be a normal usage model for a mutex). + + Change the behaviour of the interrupt safe interrupt mask save and restore + macros in the Cortex-M ports. The save macro now returns the previous + mask value. The restore macro now uses the previous mask value. These + changes are not necessary for the kernel's own implementation, and are + made purely because the macros were being used by application writers. + + Added eTaskStateGet() API function. + + Added port specific optimisations to the PIC32 port layer, and updated the + PIC32 demo applications to make use of this new feature. + + Added port specific optimisations to the Win32 simulator port. + + Added new ports and demo applications for the TI Hercules RM48 and TMS570 + safety microcontrollers. + + Added SAM3 demos targeting the ATSAM3S-EK2 and ATSAM3X-EK evaluation + boards. + + Updated the PIC32 MPLAB X project to manually set the compiler include + paths instead of using the IDE entry box following reports that the + include paths were somehow being deleted. + + Improved character handling in FreeRTOS+CLI. + +Changes between V7.1.1 and V7.2.0 released 14 August 2012 + + FreeRTOS V7.2.0 is backward compatible with FreeRTOS V7.1.2. + + + Added a FreeRTOS+ sub-directory. The directory contains some FreeRTOS+ + source code, and example projects that use the FreeRTOS Win32 simulator. + + Added a new example heap allocation implementation (heap_4.c) that + includes memory block coalescence. + + Added a demo that targets the Atmel SAM4S Cortex-M4 based microcontroller. + The demo is preconfigured to build using the free Atmel Studio 6 IDE and + GCC compiler. + + Added xSemaphoreTakeFromISR() implementation. + + The last parameter in ISR safe FreeRTOS queue and semaphore functions + (xHigherPriorityTaskWoken) is now optional and can be set to NULL if it + is not required. + + Update the IAR and MSP430X ports to clear all lower power mode bits before + exiting the tick interrupt [bug fix]. + + Allow xQueueReset() to be used, even when the queues event lists are not + empty. + + Added a vQueueDelete() handler for the FreeRTOS MPU port (this was + previously missing). + + Updated the vPortSVCHandler() functions in the FreeRTOS MPU port layer to + ensure it compiles with the latest ARM GCC compilers from Linaro. + + Updated the prvReadGP() function in the NIOS II port to ensure the compiler + can choose any register for the functions parameter (required at high + compiler optimisation levels). + + Add #error macros into the Keil and IAR Cortex-M ports to ensure they + cannot be built if the user has set configMAX_SYSCALL_INTERRUPT_PRIORITY + to 0. + + Added comments in the FreeRTOSConfig.h files associated with Cortex-M3 and + Cortex-M4 demos stating that the configMAX_SYSCALL_INTERRUPT_PRIORITY + parameter must not be set to 0. + + Introduce new INCLUDE_xQueueGetMutexHolder configuration constant + (defaulted to 0). + + Added two new list handling macros - for internal use only in upcoming new + products. + + Removed all mention of the legacy vTaskStartTrace and ulTaskEndTrace + macros. FreeRTOS+Trace supersedes the legacy trace. + + Added a configASSERT() into the vPortFree() function in heap_1.c as it is + invalid for the function to be called. + + Made the xRxLock and xTxLock members of the queue structure volatile. + This is probably not necessary, and is included as a precautionary + measure. + + Modify the assert() that checks to see if the priority passed into an + xTaskCreate() function is within valid bounds to permit the assert to be + used in the FreeRTOS MPU port. + + The software timer service (daemon) task is now created in a way that + to ensure compatibility with FreeRTOS MPU. + +Changes between V7.1.0 and V7.1.1 released May 1 2012 + + New ports: + + The following ports are brand new: + + Cortex-M3 Tasking + + The following ports have been available as separate downloads for a number + of months, but are now included in the main FreeRTOS download. + + Cortex-M0 IAR + + Cortex-M0 GCC + + Cortex-M4F GCC (with full floating point support) + + + New demos: + + The following demos are brand new: + + Renesas RX63N RDK (Renesas compiler) + + The following demos have been available as separate downloads for a number + of months, but are now included in the main FreeRTOS download. + + NXP LPC1114 GCC/LPCXpresso + + ST STM32F0518 IAR + + Infineon XMC4500 GCC/Atollic + + Infineon XMC4500 IAR + + Infineon XMC4500 Keil + + Infineon XMC4500 Tasking + + + Kernel miscellaneous / maintenance: + + + Introduced the portSETUP_TCB() macro to remove the requirement for the + Windows simulator to use the traceTASK_CREATE() macro, leaving the trace + macro available for use by FreeRTOS+Trace (https://www.FreeRTOS.org/trace). + + Added a new trace macro, traceMOVE_TASK_TO_READY_STATE(), to allow future + FreeRTOS+Trace versions to provide even more information to users. + + Updated the FreeRTOS MPU port to be correct for changes that were + introduced in FreeRTOS V7.1.0. + + Introduced the xQueueReset() API function. + + Introduced the xSemaphoreGetMutexHolder() API function. + + Tidy up various port implementations to add the static key word where + appropriate, and remove obsolete code. + + Slight change to the initial stack frame given to the RX600 ports to allow + them to be used in the Eclipse based E2Studio IDE without confusing GDB. + + Correct the alignment given to the initial stack of Cortex-M4F threads. + + Added a NOP following each DINT instruction on MSP430 devices for strict + conformance with the instructions on using DINT. + + Changed the implementation of thread deletes in the Win32 port to prevent + the port making use of the traceTASK_DELETE() trace macros - leaving this + macro free for use by FreeRTOS+Trace. + + Made some benign changes to the RX600 Renesas compiler port layer to + ensure the code can be built to a library without essential code being + removed by the linker. + + Reverted the change in the name of the uxTaskNumber variable made in + V7.1.0 as it broke the IAR plug-in. + + + Demo miscellaneous / maintenance: + + + The command interpreter has now been formally released as FreeRTOS+CLI, + and been moved out of the main FreeRTOS download, to instead be available + from the FreeRTOS+ Ecosystem site https://www.FreeRTOS.org/plus. + + flash_timer.c/h has been added to the list of standard demo threads. This + performs the same functionality as the flash.c threads, but using software + timers in place of threads. + + Upgraded the PIC32 demo as follows: Changes to how the library functions + are called necessitated by the new compiler version, addition of MPLAB X + project with PIC32MX360, PIC32MX460 and PIC32MX795 configurations, + addition of simply blinky demo, updated FreeRTOSConfig.h to include more + parameters, addition of hook function stubs. + + The MSP430X IAR and CCS demos have been updated to ensure the power + settings are correct for the configured CPU frequency. + + Rowley CrossWorks projects have been updated to correct the "multiple + definition of ..." warnings introduced when the toolchain was updated. + + Updated various FreeRTOSConfig.h header files associated with projects + that build with Eclipse to include a #error statement informing the user + that the CreateProjectDirectoryStructure.bat batch file needs to be + executed before the projects can be opened. + + Renamed directories that included "CCS4" in their name to remove the '4' + and instead just be "CCS". This is because the demo was updated and + tested to also work with later Code Composer Studio versions. + + Updated the TCP/IP periodic timer frequency in numerous uIP demos to be + 50ms instead of 500ms. + +Changes between V7.0.2 and V7.1.0 released December 13 2011 + + New ports: + + + Cortex-M4F IAR port. + + Cortex-M4F Keil/RVDS port. + + TriCore GCC port. + + New demos: + + + NXP LPC4350 using the Keil MDK, and demonstrated on a Hitex development + board. + + ST STM32F407 using the IAR Embedded Workbench for ARM, and demonstrated on + the IAR STM32F407ZG-SK starter kit. + + Infineon TriCore TC1782, using the GCC compiler, demonstrated on the + TriBoard TC1782 evaluation board. + + Renesas RX630, using the Renesas compiler and HEW, demonstrated on an + RX630 RSK (Renesas Starter Kit). + + Miscellaneous / maintenance: + + + Removed all calls to printf() from the K60/IAR Kinetis demo so the project + can execute stand alone - without being connected to the debugger. + + Completed the command interpreter framework. Command handlers now receive + the entire command string, giving them direct access to parameters. + Utility functions are provided to check the number of parameters, and + return parameter sub-strings. + + The previously documented fix for the bug in xTaskResumeFromISR() that + effected (only) ports supporting interrupt nesting has now been + incorporated into the main release. + + The portALIGNMENT_ASSERT_pxCurrentTCB() definition has been added to allow + specific ports to skip the second stack alignment check when a task is + created. This is because the second check is not appropriate for some + ports - including the new TriCore port where the checked pointer does not + actually point to a stack. + + The portCLEAN_UP_TCB() macro has been added to allow port specific clean + up when a task is deleted - again this is required by the TriCore port. + + Various other minor changes to ensure warning free builds on a growing + number of microcontroller and toolchain platforms. This includes a + (benign) correction to the prototype of the + vApplicationStackOverflowHook() definition found in lots of recent demos. + + Trace system: + + + The legacy trace mechanism has been completely removed - it has been + obsolete for the years since the trace macros were introduced. The + configuration constant configUSE_TRACE_FACILITY is now used to optionally + include additional queue and task information. The additional information + is intended to make the trace mechanism more generic, and allow the trace + output to provide more information. When configUSE_TRACE_FACILITY is set + to 1: + - the queue structure includes an additional member to hold the queue + type, which can be base, mutex, counting semaphore, binary semaphore + or recursive mutex. + - the queue structure includes an additional member to hold a queue + number. A trace tool can set and query the queue number for its own + purposes. The kernel does not use the queue number itself. + - the TCB structure includes an additional member to hold a task number + number. A trace tool can set and query the task number for its own + purposes. The kernel does not use the task number itself. + + Queues and all types of semaphores are now automatically allocated their + type as they are created. + + Added two new trace macros - traceTASK_PRIORITY_INHERIT() and + traskTASK_PRIORITY_DISINHERIT(). + + Updated the traceQUEUE_CREATE_FAILED() macro to take a parameter that + indicates the type of queue, mutex, or semaphore that failed to be + created. + + The position from which traceCREATE_MUTEX() is called has been moved from + after the call to xQueueGenericSend() [within the same function] to before + the call. This ensures the trace events occur in the correct order. + + The value passed into tracePRIORITY_SET() has been corrected for the case + where vTaskPrioritySet() is called with a null parameter. + +Changes between V7.0.1 and V7.0.2 released September 20 2011 + + New ports: + + + The official FreeRTOS Renesas RX200 port and demo application have been + incorporated into the main FreeRTOS zip file download. + + The official FreeRTOS Renesas RL78 port and demo application have been + incorporated into the main FreeRTOS zip file download. + + The official FreeRTOS Freescale Kinetis K60 tower demo application has + been incorporated into the main FreeRTOS zip file download. This includes + an embedded web server example. + + A new Microblaze V8 port layer has been created to replace the older, now + deprecated, port layer. The V8 port supports V8.x of the Microblaze IP, + including exceptions, caches, and the floating point unit. A new + Microblaze demo has also been added to demonstrate the new Microblaze V8 + port layer. The demo application was created using V13.1 of the Xilinx + EDK, and includes a basic embedded web server that uses lwIP V1.4.0. + + The official FreeRTOS Fujitsu FM3 MB9A310 demo application has been + incorporated into the main FreeRTOS zip file download. Projects are + provided for both the IAR and Keil toolchains. + + + API additions: + + + xTaskGetIdleTaskHandle() has been added. + + xTaskGetTimerDaemonTaskHandle() has been added. + + pcTaskGetTaskName() has been added. + + vSemaphoreDelete() macro has been added to make it obvious how to delete + a semaphore. In previous versions vQueueDelete() had to be used. + + vTaskCleanUpResources() has been removed. It has been obsolete for a + while. + + portPOINTER_SIZE_TYPE has been introduced to prevent compiler warnings + being generated when the size of a pointer does not match the size of + the stack type. This will (has already) be used in new ports, but will + not be retrofitted to existing ports until the existing port itself is + updated. + + Other updates and news: + + + The core files have all been modified to tighten the coding standard even + further. These are style, not functional changes. + + All ARM7 port layers have been slightly modified to prevent erroneous + assert() failures when threads are created and configASSERT() is defined. + + All ARM IAR projects have been updated to build with the latest V6.2.x + versions of the IAR Embedded Workbench for ARM tools (EWARM). This was + necessary due to a change in the way EWARM uses the CMSIS libraries. + + The PIC32 port layer has been updated in preparation for V2 of the C32 + compiler. + + The old Virtex-4 Microblaze demo has been marked as deprecated. Please + use the brand new Spartan-6 port and demo in its place. + + The bones of a new generic command interpreter is located in + FreeRTOS/Demo/Common/Utils/CommandInterpreter.c. This is still a work in + progress, and not documented. It is however already in use. It will be + documented in full when the projects that are already using it are + completed. + + A couple of new standard demos have been included. First, a version of + flop.c called sp_flop.c. This is similar to flop.c, but uses single + precision floats in place of double precision doubles. This allows the + for testing ports to processors that have only single precision floating + point units, and revert to using emulated calculations whenever a double + is used. Second, comtest_strings.c has been included to allow the test + of UART drivers when an entire string is transmitted at once. The + previous comtest.c only used single character transmission and reception. + + lwIP V1.4.0 is now included in the FreeRTOS/Demo/Common directory, and + used by a couple of new demos. + +Changes between V7.0.0 and V7.0.1 released May 13 2011 + + + Added a Fujitsu FM3 demo application for both the IAR and Keil tool + chains. + + Added a SmartFusion demo application for all of the IAR, Keil and + SoftConsole (GCC/Eclipse) tool chains. + + Updated the RX600 port and demo applications to take into account the + different semantics required when using the latest (V1.0.2.0) version of + the Renesas compiler. + + Modified the RX600 Ethernet driver slightly to make it more robust under + heavy load, and updated the uIP handling task to make use of the FreeRTOS + software timers. + + Slightly changed the PIC32 port layer to move an ehb instruction in line + with the recommendations of the MIPS core manual, and ensure 8 byte stack + alignment is truly always obtained. + + Changed the behaviour when threads are suspended before the scheduler has + been started. Before, there needed to be at least one task that was not + in the suspended state. This is no longer the case. + +Changes between V6.1.1 and V7.0.0 released April 8 2011 + + FreeRTOS V7.0.0 is backward compatible with FreeRTOS V6.x.x + + Main changes: + + + Introduced a new software timer implementation. + + Introduced a new common demo application file to exercise the new timer + implementation. + + Updated the Win32/MSVC simulator project to include the new software timer + demo threads and software timer tick hook test. Much simpler software timer + demonstrations are included in the demo projects for both of the new ports + (MSP430X with CCS4 and STM32 with TrueStudio). + + Various enhancements to the kernel implementation in threads.c. These are + transparent to users and do not effect the pre-existing API. + + Added calls to configASSERT() within the kernel code. configASSERT() is + functionally equivalent to the standard C assert() macro, but does not + rely on the compiler providing assert.h. + + Other changes: + + + Updated the MSP430X IAR port and demo project to include support for the + medium memory model. + + Added a demo project for the MSP430X that targets the MSP430X Discovery + board and uses the Code Composer Studio 4 tools. This demo includes use + of the new software timer implementation. + + Added an STM32F100RB demo project that targets the STM32 Discovery Board + and uses the TrueStudio Eclipse based IDE from Atollic. + + Removed some compiler warnings from the PSoC demo application. + + Updated the PIC32 port layer to ensure the + configMAX_SYSCALL_INTERRUPT_PRIORITY constant works as expected no matter + what its value is (within the valid range set by the microcontroller + kernel). + + Updated the PIC24, dsPIC and PIC32 projects so they work with the latest + MPLAB compiler versions from Microchip. + + Various cosmetic changes to prepare for a standards compliance statement + that will be published after the software release. + + +Changes between V6.1.0 and V6.1.1 released January 14 2011 + + + Added two new Windows simulator ports. One uses the free Microsoft Visual + Studio 2010 express edition, and the other the free MingW/Eclipse + environment. Demo projects are provided for both. + + Added three demo projects for the PSoC 5 (CYAC5588). These are for the + GCC, Keil, and RVDS build tools, and all use the PSoC Creator IDE. + + Added a demo for the low power STM32L152 microcontroller using the IAR + Embedded Workbench. + + Added a new port for the MSP430X core using the IAR Embedded Workbench. + + Updated all the RX62N demo projects that target the Renesas Demonstration + Kit (RDK) to take into account the revered LED wiring on later hardware + revisions, and the new J-Link debug interface DLL. + + Updated all the RX62N demo projects so the IO page served by the example + embedded web server works with all web browsers. + + Updated the Red Suite projects to work with the up coming Red Suite + release, and to use a more recent version of the CMSIS libraries. + + Added the traceTAKE_MUTEX_RECURSIVE_FAILED() trace macro. + + Removed the (pointless) parameter from the traceTASK_CREATE_FAILED() + trace macro. + + Introduced the portALT_GET_RUN_TIME_COUNTER_VALUE() macro to compliment + the already existing portGET_RUN_TIME_COUNTER_VALUE(). This allows for + more flexibility in how the time base for the run time statistics feature + can be implemented. + + Added a "cpsie i" instruction before the "svc 0" instruction used to start + the scheduler in each of the Cortex M3 ports. This is to ensure that + interrupts are globally enabled prior to the "svc 0" instruction being + executed in cases where interrupts are left disabled by the C start up + code. + + Slight optimisation in the run time stats calculation. + +Changes between V6.0.5 and V6.1.0 released October 6 2010 + + + Added xTaskGetTickCountFromISR() function. + + Modified vTaskSuspend() to allow threads that have just been created to be + immediately suspended even when the kernel has not been started. This + allows them to effectively start in the Suspended state - a feature that + has been asked for on numerous occasions to assist with initialisation + procedures. + + Added ports for the Renesas RX62N using IAR, GCC and Renesas tool suites. + + Added a STM32F103 demo application that uses the Rowley tools. + + Under specific conditions xFreeBytesRemaining within heap_2.c could end up + with an incorrect value. This has been fixed. + + xTaskCreateGeneric() has a parameter that can be used to pass the handle + of the task just created out to the calling task. The assignment to this + parameter has been moved to ensure it is assigned prior to the newly + created having any possibility of executing. This takes into account the + case where the assignment is made to a global variable that is accessed by + the newly created task. + + Fixed some build time compiler warnings in various FreeTCPIP (based on + uIP) files. + + Fixed some build time compiler warnings in Demo/Common/Minimal/IntQueue.c. + +Changes between V6.0.4 and V6.0.5 released May 17 2010 + + + Added port and demo application for the Cortus APS3 processor. + +Changes between V6.0.3 and V6.0.4 released March 14 2010 + + + All the contributed files that were located in the Demo/Unsupported_Demos + directory have been removed. These files are instead now available in the + new Community Contributions section of the FreeRTOS website. See + https://www.FreeRTOS.org/RTOS-contributed-ports.html + + The project file located in the Demo/CORTEX_STM32F107_GCC_Rowley directory + has been upgraded to use V2.x of the Rowley Crossworks STM32 support + package. + + An initial Energy Micro EFM32 demo has been included. This will be + updated over the coming months to make better use of the low power modes + the EFM32 provides. + +Changes between V6.0.2 and V6.0.3 released February 26 2010 + + + SuperH SH7216 (SH2A-FPU) port and demo application added. + + Slight modification made to the default implementation of + pvPortMallocAligned() and vPortFreeAligned() macros so by default they + just call pvPortMalloc() and vPortFree(). The macros are only needed to + be defined when a memory protection unit (MPU) is being used - and then + only depending on other configuration settings. + +Changes between V6.0.1 and V6.0.2 released January 9th 2010 + + + Changed all GCC ARM 7 ports to use 0 as the SWI instruction parameter. + Previously the parameter was blank and therefore only an implicit 0 but + newer GCC releases do not permit this. + + Updated IAR SAM7S and SAM7X ports to work with IAR V5.40. + + Changed the stack alignment requirement for PIC32 from 4 bytes to 8 bytes. + + Updated prvListTaskWithinSingleList() is it works on processors where the + stack grows up from low memory. + + Corrected some comments. + + Updated the startup file for the RVDS LPC21xx demo. + +Changes between V6.0.0 and V6.0.1 released November 15th 2009 + + + Altered pxPortInitialiseStack() for all Cortex-M3 ports to ensure the + stack pointer is where the compiler expects it to be when a task first + starts executing. + + The following minor changes only effect the Cortex-M3 MPU port: + + + portRESET_PRIVILEGE() assembly macro updated to include a clobber list. + + Added prototypes for all the privileged function wrappers to ensure no + compile time warnings are generated no matter what the warning level + setting. + + Corrected the name of portSVC_prvRaisePrivilege to + portSVC_RAISE_PRIVILEGE. + + Added conditional compilation into xTaskGenericCreate() to prevent some + compilers issuing warnings when portPRIVILEGE_BIT is defined as zero. + + +Changes between V5.4.2 and V6.0.0 released October 16th 2009 + + FreeRTOS V6 is backward compatible with FreeRTOS V5.x. + + Main changes: + + + FreeRTOS V6 is the first version to include memory protection unit (MPU) + support. Two ports now exist for the Cortex M3, the standard FreeRTOS + which does not include MPU support, and FreeRTOS-MPU which does. + + xTaskCreateRestricted() and vTaskAllocateMPURegions() API functions added + in support of FreeRTOS-MPU. + + Wording for the GPL exception has been (hopefully) clarified. Also the + license.txt file included in the download has been fixed (the previous + version contained some corruption). + + Other changes: + + + New API function xPortGetFreeHeapSize() added to heap_1.c and heap_2.c. + + ARM7 GCC demo interrupt service routines wrappers have been modified to + call the C portion using an __asm statement. This prevents the function + call being inlined at higher optimisation levels. + + ARM7 ports now automatically set the THUMB bit if necessary when + setting up the initial stack of a task - removing the need for + THUMB_INTERWORK to be defined. This also allows THUMB mode and ARM mode + threads to be mixed more easily. + + All ARM7/9 ports now have portBYTE_ALIGNMENT set to 8 by default. + + Various demo application project files have been updated to be up to date + with the latest IDE versions. + + The linker scripts used with command line GCC demos have been updated to + include an eh_frame section to allow their use with the latest Yagarto + release. Likewise the demo makefiles have been updated to include + command line options to reduce or eliminate the eh_frame section all + together. + + The definition of portBYTE_ALIGNMENT_MASK has been moved out of the + various memory allocation files and into the common portable.h header + file. + + Removed unnecessary use of portLONG, portSHORT and portCHAR. + + Added LM3Sxxxx demo for Rowley CrossWorks. + + Posix simulator has been upgraded - see the corresponding WEB page on the + FreeRTOS.org site. + + +Changes between V5.4.1 and V5.4.2 released August 9th 2009 + + + Added a new port and demo app for the Altera Nios2 soft core. + + Added LPC1768 demo for IAR. + + Added a USB CDC demo to all LPC1768 demos (Code Red, CrossWorks and IAR). + + Changed clock frequency of LPC1768 demos to 99MHz. + +Changes between V5.4.0 and V5.4.1 released July 25th 2009 + + + New hook function added. vApplicationMallocFailedHook() is (optionally) + called if pvPortMalloc() returns NULL. + + Additional casting added to xTaskCheckForTimeOut(). This prevents + problems that can arise should configUSE_16_BIT_TICKS be set to 1 on a + 32 bit architecture (which would probably be a mistake, anyway). + + Corrected the parameter passed to NVIC_SetPriority() to set the MAC + interrupt priority in both LPC1768 demos. + + Decreased the default setting of configMINIMAL_STACK_SIZE in the PIC32 + demo application to ensure the heap space was not completely consumed + before the scheduler was started. + +Changes between V5.3.1 and V5.4.0 released July 13th 2009 + + + Added Virtex5 / PPC440 port and demos. + + Replaced the LPC1766 Red Suite demo with an LPC1768 Red Suite demo. The + original demo was configured to use engineering samples of the CPU. The + new demo has an improved Ethernet driver. + + Added LPC1768 Rowley demo with zero copy Ethernet driver. + + Reworked byte alignment code to ensure 8 byte alignment works correctly. + + Set configUSE_16_BIT_TICKS to 0 in the PPC405 demo projects. + + Changed the initial stack setup for the PPC405 to ensure the small data + area pointers are setup correctly. + +Changes between V5.3.0 and V5.3.1 released June 21st 2009 + + + Added ColdFire V1 MCF51CN128 port and WEB server demo. + + Added STM32 Connectivity Line STM32107 Cortex M3 WEB server demo. + + Changed the Cortex M3 port.c asm statements to __asm so it can be + compiled using Rowley CrossWorks V2 in its default configuration. + + Updated the Posix/Linux simulator contributed port. + +Changes between V5.2.0 and V5.3.0 released June 1st 2009 + + Main changes: + + + Added new (optional) feature that gathers statistics on the amount of CPU + time used by each task. + + Added a new demo application for the Atmel AT91SAM3U Cortex-M3 based + microcontroller. + + Added a new demo application for the NXP LPC1766 Cortex-M3 based + microcontroller. + + Added a contributed port/demo that allows FreeRTOS to be 'simulated' in a + Linux environment. + + Minor changes: + + Updated the Stellaris uIP WEB server demos to include the new run time + statistics gathering feature - and include a served WEB page that + presents the information in a tabular format. + + Added in the lwIP port layer for the Coldfire MCF52259. + + Updated the CrossWorks LPC2368 WEB server to include an image in the + served content. + + Changed some of the timing in the initialisation of the LPC2368 MAC to + permit its use on all part revisions. + + Minor modifications to the core uIP code to remove some compiler warnings. + + Added xTaskGetApplicationTaskTag() function and updated the OpenWatcom + demo to make use of the new function. + + Added contributed demos for AVR32 AP7000, STM32 Primer 2 and STM32 using + Rowley Crossworks. + + Heap_1.c and Heap_2.c used to define structures for the purpose of data + alignment. These have been converted to unions to save a few bytes of + RAM that would otherwise be wasted. + + Remove the call to strncpy() used to copy the task name into the TCB when + the maximum task name is configured to be 1 byte long. + +Changes between V5.1.2 and V5.2.0 released March 14th 2009 + + + Optimised the queue send and receive functions (also used by semaphores). + + Replaced the standard critical sections used to protect BIOS calls in the + PC port to instead use scheduler locks. This is because the BIOS calls + always return with interrupts enabled. + + Corrected unclosed comments in boot.s. + +Changes between V5.1.1 and V5.1.2 released February 9th 2009 + + + Added NEC V850ES port and demo. + + Added NEC 78K0R port and demo. + + Added MCF52259 port and demo. + + Added the AT91SAM9XE port and demo. + + Updated the MCF52233 FEC driver to work around a silicon bug that + prevents the part auto negotiating some network parameters. + + Minor modifications to the MCF52233 makefile to permit it to be used + on Linux hosts. + + Updated the STM32 primer files to allow them to be built with the latest + version of the RIDE tools. + + Updated the threads.js Java script used for kernel aware debugging in + the Rowley CrossWorks IDE. + + +Changes between V5.1.0 and V5.1.1 released November 20, 2008 + + + Added Coldfire MCF52233 WEB server demo using GCC and Eclipse. + + Added IAR MSP430 port and demo. + + Corrected several compiler time issues that had crept in as tool versions + change. + + Included FreeRTOS-uIP - a faster uIP. This is not yet complete. + +Changes between V5.0.4 and V5.1.0 released October 24, 2008 + + + Added a new port and demo application for the ColdFire V2 core using the + CodeWarrior development tools. + + Replaced the ARM7 demo that used the old (and now no longer supported) + Keil compiler with a new port that uses the new Keil/RVDS combo. + + Stack overflow checking now works for stacks that grow up from low + memory (PIC24 and dsPIC). + + BUG FIX - set the PIC32 definition of portSTACK_GROWTH to the correct + value of -1. + + MSP430 port layers have been updated to permit threads to place the + microcontroller into power down modes 1 to 3. The demo applications have + likewise been updated to demonstrate the new feature. + + Replaced the two separate MSP430/Rowley port layers with a single and more + flexible version. + + Added more contributed ports, including ports for NEC and SAM9 + microcontrollers. + + Changed the linker script used in the LPC2368 Eclipse demo. + +Changes between V5.0.3 and V5.0.4 released September 22, 2008 + + + Completely re-written port for ColdFire GCC. + + Bug fix: All Cortex M3 ports have a minor change to the code that sets + the pending interrupt. + + Some header files require that FreeRTOS.h be included prior to their + inclusion. #error message have been added to all such header file + informing users to the cause of the compilation error should the headers + not be included in the correct order. + +Changes between V5.0.2 and V5.0.3 released July 31, 2008 + + Changes relating to the Cortex M3: + + + Added configMAX_SYSCALL_INTERRUPT_PRIORITY usage to all the Cortex M3 + ports and demos. See the port documentation pages on the FreeRTOS.org + WEB site for full usage information. + + Improved efficiency of Cortex M3 port even further. + + Ensure the Cortex M3 port works no matter where the vector table is + located. + + Added the IntQTimer demo/test threads to a demo project for each CM3 port + (Keil, GCC and IAR) to test the new configMAX_SYSCALL_INTERRUPT_PRIORITY + functionality. + + Added the mainINCLUDE_WEB_SERVER definition to the LM3SXXXX IAR and Keil + projects to allow the WEB server to be conditionally excluded from the + build and therefore allow use of the KickStart (code size limited) + compiler version. + + Other changes: + + + Moved the PIC24 and dsPIC versions of vPortYield() from the C file to + an assembly file to allow use with all MPLAB compiler versions. This also + allows the omit-frame-pointer optimisation to be turned off. + +Changes between V5.0.0 and V5.0.2 released May 30, 2008 + + + Updated the PIC32 port to allow queue API calls to be used from + interrupts above the kernel interrupt priority, and to allow full + interrupt nesting. Task stack usages has also been reduced. + + Added a new PowerPC port that demonstrates how the trace macros can be + used to allow the use of a floating point co-processor. The + traceTASK_SWITCHED_OUT() and traceTASK_SWITCHED_INT() macros are used to + save and restore the floating point context respectively for those threads + that actually use floating point operations. + + BUG FIX: The first PPC405 port contained a bug in that it did not leave + adequate space above the stack for the backchain to be saved when a task + started to execute for the first time. + + Updated queue.c to add in the means to allow interrupt nesting and for + queue API functions to be called from interrupts that have a priority + above the kernel priority. This is only supported on PIC32 ports thus + far. + + Fixed the compiler warnings that were generated when the latest version + of WinAVR was used. + + Remove all inline usage of 'inline' from the core kernel code. + + Added the queue registry feature. The queue registry is provided as a + means for kernel aware debuggers to locate queue definitions. It has no + purpose unless you are using a kernel aware debugger. The queue registry + will only be used when configQUEUE_REGISTRY_SIZE is greater than zero. + + Added the ST Cortex-M3 drivers into the Demo/Common/Drivers directory to + prevent them from having to be included in multiple demos. + + Added a Keil STM32 demo application. + + Changed the blocktim.c test files as it is no longer legitimate for all + ports to call queue API functions from within a critical section. + + Added the IntQueue.c test file to test the calling of queue API functions + from different interrupt priority levels, and test interrupt nesting. + +Changes between V5.0.0 and V5.0.1 + + + V5.0.1 was a customer specific release. + +Changes between V4.8.0 and V5.0.0 released April 15, 2008 + + *** VERY IMPORTANT INFORMATION ON UPGRADING TO FREERTOS.ORG V5.0.0 *** + + The parameters to the functions xQueueSendFromISR(), xQueueSendToFrontFromISR(), + xQueueSendToBackFromISR() and xSemaphoreGiveFromISR() have changed. You must + update all calls to these functions to use the new calling convention! Your + compiler might not issue any type mismatch warnings! + + + Other changes: + + + Support added for the new Luminary Micro LM3S3768 and LM3S3748 Cortex-M3 + microcontrollers. + + New task hook feature added. + + PowerPC demo updated to use version 10.1 of the Xilinx EDK. + + Efficiency gains within the PIC32 port layer. + +Changes between V4.7.2 and V4.8.0 released March 26 2008 + + + Added a Virtex4 PowerPC 405 port and demo application. + + Added optional stack overflow checking and new + uxTaskGetStackHighWaterMark() function. + + Added new xQueueIsQueueEmptyFromISR(), xQueueIsQueueFullFromISR() and + uxQueueMessagesWaitingFromISR() API functions. + + Efficiency improvements to the Cortex-M3 port layer. NOTE: This + requires that an SVC handler be installed in the application. + + Efficiency improvements to the queue send and receive functions. + + Added new trace macros. These are application definable to provide + a flexible trace facility. + + Implemented the configKERNEL_INTERRUPT_PRIORITY within the Keil Cortex + M3 port layer (bringing it up to the same standard as the IAR and GCC + versions). + + Ports that used the arm-stellaris-eabi-gcc tools have been converted to + use the arm-non-eabi-gcc tools. + +Changes between V4.7.1 and V4.7.2 released February 21, 2008 + + + Added Fujitsu MB91460 port and demo. + + Added Fujitsu MB96340 port and demo. + + Tidied up the capitalisation of include files to facilitate builds on + Linux hosts. + + Removed some redundant casting that was generating warnings - but was + included to remove warnings on other compilers. + +Changes between V4.7.0 and V4.7.1 released February 3, 2008 + + + Updated all IAR ARM projects to use V5.11 of the IAR Embedded Workbench + for ARM. + + Introduced recursive semaphore feature. + + Updated LPC2368 demos to take into account silicon bugs in old chip + revisions. + + Updated STR9 uIP port to manually set the net mask and gateway addresses. + + Updating demos to allow more to run with the co-operative scheduler. + + Fixed co-operative scheduler behaviour upon the occurrence of a tick + interrupt while the scheduler was suspended. + + Updated documentation contained within semphr.h. + + ARM7 GCC ports no longer use the IRQ attribute. + +Changes between V4.6.1 and V4.7.0 released December 6, 2007 + + + Introduced the counting semaphore macros and demo source files. The + Open Watcom PC project has been updated to include the new demo. See + the online documentation for more information. + + Introduced the 'alternative' queue handling API and demo source files. + The Open Watcom PC project has been updated to include the new demo + source files. See the online documentation for more information. + + Added AT91SAM7X Eclipse demo project. + + Added the STM32 primer demo project for the GCC compiler and Ride IDE. + + Removed the .lock files that were mistakenly included in the V4.6.1 + eclipse workspaces. + +Changes between V4.6.0 and V4.6.1 released November 5 2007 + + + Added support for the MIPS M4K based PIC32. + + Added 'extern "C"' to all the header files to facilitate use with C++. + +Changes between V4.5.0 and V4.6.0 released October 28 2007 + + + Changed the method used to force a context switch within an ISR for the + ARM7/9 GCC ports only. The portENTER_SWITCHING_ISR() and + portEXIT_SWITCHING_ISR() macros are no longer supported. This is to + ensure correct behaviour no matter which GCC version is used, with or + without the -fomit-frame-pointer option, and at all optimisation levels. + + Corrected the prototype for xQueueGenericSend() within queue.h. + +Changes between V4.4.0 and V4.5.0 released September 17 2007 + + + Added the xQueueSendToFront(), xQueueSendToBack() and xQueuePeek() + functionality. These should now be used in preference to the old + xQueueSend() function - which is maintained for backward compatibility. + + Added Mutex functionality. The behaviour of mutexes is subtly different + to the already existing binary semaphores as mutexes automatically + include a priority inheritance mechanism. + + Added the GenQTest.c and QPeek.c to test and demonstrate the behaviour + of the new functionality. + + Updated the LM3Sxxxx and PC ports to include the new GenQTest.c and + QPeek.c files. + + Updated the GCC port for the Cortex M3 to include the + configKERNEL_INTERRUPT_PRIORITY functionality. This was previously only + included in the IAR port. + + Optimised the GCC and IAR port layer code - specifically the context + switch code. + + Consolidated the LM3Sxxxx EK demos for all development tools into a + single project that automatically detects which version of the EK the + application is executing on. + + Added Eclipse support for LM3Sxxxx evaluation kits. + + Added Eclipse support for the Keil LPC2368 evaluation kit. + + Added the Demo/Drivers directory to hold code that is common to multiple + demo application projects. + + Included some minor bug fixes in the uIP 1.0 code. + + Added an lwIP demo for the STR9 - thanks ST for assistance. + + Updated the AVR32 port to ensure correct behaviour with full compiler + optimisation. + + Included binaries for OpenOCD FTDI and parallel port interfaces. + +Changes between V4.4.0 and V4.3.1 released July 31, 2007 + + + Added AVR32 UC3B demo application. + + Updated AVR32 UC3A port and demo applications. + + Added IAR lwIP demo for AVR32 UC3A. + + Updated listGET_OWNER_OF_NEXT_ENTRY() to assist compiler optimisation + (thanks Niu Yong for making the suggestion). + + Added xTaskGetSchedulerState() API function. + + BUG FIX: Corrected behaviour when threads that are blocked indefinitely + have their block time adjusted (within xQueueSend() and xQueueReceive()), + and are the subject of a call the vTaskResume() when they are not + actually in the Suspended state (thanks Dan Searles for reporting the + issues). + + +Changes between V4.3.0 and V4.3.1 released June 11, 2007 + + + Added STMicroelectronics STM32 Cortex-M3 demo application. + + Updated ustdlib.c for the GCC LM3S6965 demo. + +Changes between V4.2.1 and V4.3.0 released June 5, 2007 + + + Introduced configKERNEL_INTERRUPT_PRIORITY to the IAR Cortex-M3, PIC24 + and dsPIC ports. See the LM3S6965 and PIC24 demo application + documentation pages for more information. + + Updated the PIC24 and dsPIC demos to build with V3.0 of the PIC30 GCC + tools, and changed the demo applications. + + Added demos for the new Ethernet and CAN enabled Luminary Micro Stellaris + microcontrollers. + + Corrected bug in uIP the demos that prevented frames of approximately 1480 + bytes and over from being transmitted. + + Included the LPC2368/uIP/Rowley demo into the main FreeRTOS.org + download. + + Update to WizC PIC18 port to permit its use with version 14 of the + compiler. Thanks Marcel! + +Changes between V4.2.1 and V4.2.0 released April 2, 2007 + + + Added AVR32 AT32UC3A ports for GCC and IAR. + + Added -fomit-frame-pointer option to lwIP SAM7X demo makefile. + + Moved location of call to LCD_Init() in STR9 demo to ensure it is only + called after the scheduler has been started. + +Changes between V4.1.3 and V4.2.0 released February 8, 2007 + + + Changes to both task.c and queue.c as a result of testing performed on + the SafeRTOS code base. + + Added Cortex-M3 LM3S811 demos for GCC and IAR tools. + +Changes between V4.1.2 and V4.1.3 released November 19, 2006 + + + Added STR750 ARM7 port using the Raisonance RIDE/GCC tools. + + Added -fomit-frame-pointer option to Rowley ARM7 demos as work around + to GCC bug at some optimisation levels. + + Altered the way the heap is defined in the LM3S811 Keil demo to prevent + the RAM usage from counting toward the code size limit calculation. + + CO-ROUTINE BUG FIX: Removed the call to prvIsQueueEmpty from within + xQueueCRReceive as it exited with interrupts enabled. Thanks Paul Katz. + + Tasks that block on events with a timeout of portMAX_DELAY are now + blocked indefinitely if configINCLUDE_vTaskSuspend is defined. + Previously portMAX_DELAY was just the longest block time possible. This + is still the case if configINCLUDE_vTaskSuspend is not defined. + + Minor changes to some demo application files. + +Changes between V4.1.1 and V4.1.2 released October 21, 2006 + + + Added 16bit PIC ports and demos. + + Added STR750 port and demo. + + +Changes between V4.1.0 and V4.1.1 released September 24, 2006 + + + Added the Luminary Micro Stellaris LM3S811 demo application. + +Changes between V4.0.5 and V4.1.0 released August 28, 2006 + + + Prior to V4.1.0, under certain documented circumstances, it was possible + for xQueueSend() and xQueueReceive() to return without having completed + and without their block time expiring. The block time effectively + stated a maximum block time, and the return value of the function needed + to be checked to determine the reason for returning. This is no longer + the case as the functions will only return once the block time has + expired or they are able to complete their operation. It is therefore no + longer necessary to wrap calls within loops. + + Changed the critical section handling in the IAR AVR port to correct the + behaviour when used with later compiler versions. + + Added the LPC2138 CrossWorks demo into the zip file. Previously this was + only available as a separate download. + + Modified the AVR demo applications to demonstrate the use of co-routines. + +Changes between V4.0.4 and V4.0.5 released August 13, 2006 + + + Introduced API function xTaskResumeFromISR(). Same functionality as + xTaskResume(), but can be called from within an interrupt service routine. + + Optimised vListInsert() in the case when the wake time is the maximum + tick count value. + + Bug fix: The 'value' of the event list item is updated when the priority + of a task is changed. Previously only the priority of the TCB itself was + changed. + + vTaskPrioritySet() and vTaskResume() no longer use the event list item. + This has not been necessary since V4.0.1 when the xMissedYield handling + was added. + + Lowered the PCLK setting on the ARM9 STR9 demo from 96MHz to 48MHz. + + When ending the scheduler - do not try to attempt a context switch when + deleting the current task. + + SAM7X EMAC drivers: Corrected the Rx frame length mask when obtaining + the length from the rx descriptor. + + +Changes between V4.0.3 and V4.0.4 released June 22, 2006 + + + Added a port and demo application for the STR9 ARM9 based processors from + ST. + + Slight optimisation to the vTaskPrioritySet() function. + + Included the latest uIP version (1.0) in the demo/common/ethernet + directory. + +Changes between V4.0.2 and V4.0.3 released June 7, 2006 + + + Added a port and demo application for the Cortex-M3 target using the IAR + development tools. + + The ARM Cortex-m3 Rowley projects have been updated to use V1.6 of the + CrossStudio tools. + + The heap size defined for the lwIP Rowley demo has been reduced so that + the project will link correctly when using the command line GCC tools + also. The makefile has also been modified to allow debugging. + + The lwIP Rowley demo not includes a 'kernel aware' debug window. + + The uIP Rowley project has been updated to build with V1.6 of CrossWorks. + + The second set of threads in the blockQ demo were created the wrong way + around (inconsistent to the description in the file). This has been + corrected. + +Changes between V4.0.1 and V4.0.2 released May 28, 2006 + + + Port and demo application added for the Tern Ethernet Engine controller. + + Port and demo application added for MC9S12 using GCC, thanks to + Jefferson "imajeff" Smith. + + The function vTaskList() now suspends the scheduler rather than disabling + interrupts during the creation of the task list. + + Allow a task to delete itself by passing in its own handle. Previously + this could only be done by passing in NULL. + + Corrected the value passed to the WDG_PeriodValueConfig() library + function in the STR71x demo. + + The tick hook function is now called only within a tick isr. Previously + it was also called when the tick function was called during the scheduler + unlocking process. + + The EMAC driver in the SAM7X lwIP demo has been made more robust as per + the thread: https://sourceforge.net/forum/message.php?msg_id=3714405 + + In the PC ports: Add function prvSetTickFrequencyDefault() to set the + DOS tick back to its proper value when the scheduler exits. Thanks + Raynald! + + In the Borland x86 ports there was a mistake in the portFIRST_CONTEXT + macro where the BP register was not popped from the stack correctly. The + BP value would never get used so this did not cause a problem, but it has + been corrected all the same. + + +Changes between V4.0.0 and V4.0.1 released April 7 2006 + + + Improved the ARM CORTEX M3 ports so they now only have to service + pendSV interrupts. + + Added a Luminary Micro port and demo for use with Rowley CrossWorks. + + Added the xMissedYield handling to threads.c. + +Changes between V3.2.4 and V4.0.0 + + Major changes: + + + Added new RTOS port for Luminary Micros ARM CORTEX M3 microcontrollers. + + Added new co-routine functionality. + + Other kernel changes: + + + An optional tick hook call is now included in the tick function. + + Introduced the xMiniListItem structure and removed the list pxHead + member in order to reduce RAM usage. + + Added the following definitions to the FreeRTOSConfig.h file included + with every port: + configUSE_TICK_HOOK + configUSE_CO_ROUTINES + configMAX_CO_ROUTINE_PRIORITIES + + The volatile qualification has been changed on the list members to allow + the task.c code to be tidied up a bit. + + The scheduler can now be started even if no threads have been created! + This is to allow co-routines to run when there are no threads. + + A task being woken by an event will now preempt the currently running task + even if its priority is only equal to the currently running task. + + Port and demo application changes: + + + Updated the WinAVR demo to compile with the latest version of WinAVR + with no warnings generated. + + Changed the WinAVR makefile to make chars signed - needed for the + co-routine code if BaseType_t is set to char. + + Added new demo application file crflash.c. This demonstrates co-routine + functionality including passing data between co-routines. + + Added new demo application file crhook.c. This demonstrates co-routine + and tick hook functionality including passing data between and ISR and + a co-routine. + + Some NOP's were missing following stmdb{}^ instructions in various ARM7 + ports. These have been added. + + Updated the Open Watcom PC demo project to include the crflash and crhook + demo co-routines as an example of their use. + + Updated the H8S demo to compile with the latest version of GCC. + + Updated the SAM7X EMAC drivers to take into account the hardware errata + regarding lost packets. + + Changed the default MAC address used by some WEB server demos as the + original addresses used was not liked by some routers. + + Modified the SAM7X/IAR startup code slightly to prevent it hanging on + some systems when the code is executed using a j-link debugger. The + j-link macro file configures the PLL before the code executes so + attempting to configure it again in the startup code was causing a + problem for some user. Now a check is performed first to see if the + PLL is already set up. + + GCC port now contain all assembler code in a single asm block rather than + individual blocks as before. + + GCC LPC2000 code now explicitly uses R0 rather than letting the assembler + choose the register to use as a temporary register during the context + switch. + + Added portNOP() macro. + + The compare match load value on LPC2000 ports now has 1 added to correct + the value used. + + The minimal stack depth has been increased slightly on the WIZC PIC18 + port. + +Changes between V3.2.3 and V3.2.4 + + + Modified the GCC ARM7 port layer to allow use with GCC V4.0.0 and above. + Many thanks to Glen Biagioni for the provided update. + + Added a new Microblaze port and demo application. + + Modified the SAM7X EMAC demo to default to use the MII interface rather + than the RMII interface. + + Modified the startup sequence of the SAM7X demo slightly to allow the + EMAC longer to auto negotiate. + +Changes between V3.2.2 and V3.2.3 + + + Added MII interface support to the SAM7X EMAC peripheral driver. + Previously versions worked with the RMII interface only. + + Added command line GCC support to the SAM7X lwIP demo. Previously the + project could only be built using the CrossWorks IDE. Modifications to + this end include the addition of a standard makefile and linker script to + the download, and some adjustments to the stacks allocated to each task. + + Changed the page returned by the lwIP WEB server demo to display the + task status table rather than the TCP/IP statistics. + + Corrected the capitalisation of some header file includes and makefile + dependencies to facilitate use on Linux host computers. + + The various LPC2000 ports had a mistake in the timer setup where the + prescale value was written to T0_PC instead of T0_PR. This would have + no effect unless a prescale value was actually required. This has been + corrected. + +Changes between V3.2.1 and V3.2.2 - Released 23 September, 2005 + + + Added an IAR port for the Philips LPC2129 + + The Atmel ARM7 IAR demo project files are now saved in the IAR Embedded + Workbench V4.30a format. + + Updated the J-Link macro file included with the SAM7X uIP demo project + to allow the demo board to be reset over the J-Link. + +Changes between V3.2.0 and V3.2.1 - Released 1 September, 2005 + + + Added lwIP demo for AT91SAM7X using Rowley tools. + + Added uIP demo for AT91SAM7X using IAR tools. + + Added function xTaskGetCurrentTaskHandle(). + + Renamed events.h to mevents.h to prevent it conflicting with the events.h + generated automatically by the HCS12 processor expert utility. events.h + is only used by the PC demo application. + + Both PIC18 ports now initialise the TBLPTRU to 0 as this is the value + expected by the compiler, and the compilers do not write to this + register. + + The HCS12 banked model demo now creates the 'suicide' threads immediately + prior to starting the scheduler. These threads should be the last threads to + get started in order for the test to function correctly. + +Changes between V3.1.1 and V3.2.0 - Released 29 June, 2005 + + V3.2.0 introduces two new MSP430 ports and corrects a minor kernel + issues. Thanks to Ares.qi for his input. + + + Added two MSP430 ports that use the Rowley CrossWorks development tools. + One port just mirrors the existing GCC port. The other port was provided + by Milos Prokic. Thanks! + + V3.2.0 corrects the behavior when vTaskPrioritySet() or vTaskResume() + are called while the scheduler is locked (by a call to + vTaskSuspendAll()). When this is done the subject task now starts to + execute immediately when the scheduler is unlocked if it has the highest + priority that is ready to run. Previously there was a possibility that + the task would not run until the next RTOS tick or call to portYIELD(). + + Another similar small correction ensures that in the case where more than + one task is blocked on a semaphore or queue, the task with the highest + priority is guaranteed to be unblocked first. + + Added a couple of more test threads to the PC demo which cover the points + above. + +Changes between V3.1.0 and V3.1.1 - Released 21st June, 2005 + + This release updates the HCS12 port. The common kernel code + remains unchanged. + + + Updated the HCS12 port to support banking and introduced a demo + application for the MC9S12DP256. The new demo application is + located in the Demo/HCS12_CodeWarrior_banked directory. + + The name of the directory containing the MC9S12F32 demo application + has been changed to Demo/HCS12_CodeWarrior_small (as in 'small' + memory model). + + MC9S12F32 demo updated slightly to use the PLL. The CPU speed for the + demo application is now 24MHz. Previously it was 8MHz. + + The demo application file Demo/Common/Minimal/death.c has a slight + alteration to prevent it using floating point variables. + + +Changes between V3.0.0 and V3.1.0 - Released 11th June, 2005 + + + Added new ports for ST Microsystems STR71x, and Freescale HCS12 + microcontrollers. Currently the HCS12 port is limited to the small + memory model. Large memory models will be supported in the next + release. + + PIC18 wizC port updated. Thanks to Marcel van Lieshout for his + continuing contribution. + + The accuracy of the AVR port timer setup has been improved. Thanks to + Thomas Krutmann for this contribution. + + Added a new conditional compilation macro configIDLE_SHOULD_YIELD. + See the WEB documentation for details. + + Updated the CrossWorks uIP demo to build with V1.4 of CrossWorks. + + Slight modification to the SAM7 release build configuration to correct + an include path definition. + + Updated the MPLAB PIC18 documentation to provide extra details on linker + file configuration. + +Changes between V3.0.0 and V2.6.1 - Released 23rd April, 2005 + + V3.0.0 includes many enhancements, so this history list is broken into + subsections as follows: + + API changes + New ports + Directory name changes + Kernel and miscellaneous changes changes + + - API changes + + + Each port now defines BaseType_t as the data type that is most + efficient for that architecture. The type BaseType_t is used + extensively in API calls necessitating the following changes to the + FreeRTOS API function prototypes. + + See the "New for V3.0.0" section of the FreeRTOS online + documentation for full details of API changes. + + - New ports + + + The AT91FR40008 ARM7 port contributed by John Feller is now included + in the download (thanks John!). + + The PIC18 port for the wizC/fedC compiler contributed by Marcel van + Lieshout is now included in the download (thanks Marcel!). + + The IAR port for the AVR microcontroller has been upgraded to V3.0.0 + and is now a supported port. + + - Directory name changes + + For consistency, and to allow integration of the new ports, the + following directory names have been changed. + + + The source/portable/GCC/ARM7 directory has been renamed + source/portable/GCC/ARM7_LPC2000 so it is compatible with the naming + of other GCC ARM7 ports. + + The Demo/PIC directory has been renamed Demo/PIC18_MPLAB to + accommodate the wizC/fedC PIC port. + + The demo applications for the two AVR ports no longer share the same + directory. The WinAVR demo is in the Demo/AVR_ATMega323_WinAVR + directory and the IAR port in the Demo/AVR_ATMega323_IAR directory. + + + - Kernel and miscellaneous changes changes + + See the "New for V3.0.0" section of the FreeRTOS online + documentation for more information. + + + Previously 'portmacro.h' contained some user editable definitions + relating to the user application, and some fixed definitions relating + specifically to the port being used. The application specific + definitions have been removed from 'portmacro.h' and placed inside a + new header file called 'FreeRTOSConfig.h'. 'portmacro.h' should now + never be modified by the user. A 'FreeRTOSConfig.h' is now included + in each of FreeRTOS/Demo subdirectories - as it's settings relate to + the demo application rather than being specific to the port. + + Introduced configUSE_IDLE_HOOK in idle task. + + The idle task will yield when another idle priority task is ready to + run. Previously the idle task would run to the end of its time slice + regardless. + + The idle task is now created when the scheduler is started. This + requires less stack than the previous scheme where it was created upon + creation of the first application task. + + The function usPortCheckFreeStackSpace() has been renamed + usTaskCheckFreeStackSpace() and moved from the portable layer to + threads.c. + + Corrected spelling of portMINMAL_STACK_SIZE to portMINIMAL_STACK_SIZE. + + The portheap.c file included with the AVR port has been deleted. The + AVR demo now uses the standard heap1 sample memory allocator. + + The GCC AVR port is now build using the standard make utility. The + batch files used previously have been deleted. This means a recent + version of WinAVR is required in order to create a binary suitable for + source level debugging. + + vTaskStartScheduler() no longer takes the configUSE_PREEMPTION + constant as a parameter. Instead the constant is used directly within + threads.c and no parameter is required. + + The header file 'FreeRTOS.h' has been created and is used to include + 'projdefs.h', 'FreeRTOSConfig.h' and 'portable.h' in the necessary + order. FreeRTOS.h can now be included in place of these other + headers. + + The header file 'errors.h' has been deleted. The definitions it + contained are now located within 'projdefs.h'. + + pvPortMalloc() now takes a size_t parameter as per the ANSI malloc(). + Previously an unsigned short was used. + + When resuming the scheduler a yield is performed if either a tick has + been missed, or a task is moved from the pending ready list into a + ready list. Previously a yield was not performed on this second + condition. + + In heap1.c an overflow check has been added to ensure the next free + byte variable does not wrap around. + + Introduced the portTASK_FUNCTION() and portTASK_FUNCTION_PROTO() + macros. + + The MPLAB PIC port now saved the TABLAT register in interrupt service + routines. + +Changes between V2.6.0 and V2.6.1 - Released Feb 22, 2005 + + This version adds support for the H8 processor. + + Other changes: + + + tskMAX_TASK_NAME_LEN removed from the task.h header and added to each + individual portmacro.h file as portMAX_TASK_NAME_LEN. This allows RAM + limited ports to allocate fewer characters to the task name. + + AVR port - Replaced the inb() and outb() functions with direct memory + access. This allows the port to be built with the 20050414 build of + WinAVR. + + GCC LPC2106 port - removed the 'static' from the definition of + vNonPreemptiveTick() to allow the demo to link when using the cooperative + scheduler. + + GCC LPC2106 port - Corrected the optimisation options in the batch files + ROM_THUMB.bat, RAM_THUMB.bat, ROM_ARM.bat and RAM_ARM.bat. The lower case + -o is replaced by an uppercase -O. + + Tasks.c - The strcpy call has been removed when copying across the task + name into the TCB. + + Updated the trace visualisation to always be 4 byte aligned so it can be + used on ARM architectures. + + There are now two tracecon executables (that convert the trace file binary + into an ASCII file). One for big endian targets and one for little endian + targets. + + Added ucTasksDeleted variable to prevent vTaskSuspendAll() being called + too often in the idle task. + + SAM7 USB driver - Replaced the duplicated RX_DATA_BK0 in the interrupt + mask with the RX_DATA_BK1. + + +Changes between V2.5.5 and V2.6.0 - Released January 16, 2005 + + + Added the API function vTaskDelayUntil(). The demo app file + Demo/Common/Minimal/flash.c has been updated to demonstrate its use. + + Added INCLUDE_vTaskDelay conditional compilation. + + Changed the name of the Demo/ARM7_AtmelSAM7S64_IAR directory to + Demo/ARM7_AT91SAM7S64_IAR for consistency. + + Modified the AT91SAM7S USB driver to allow descriptors that have + a length that is an exact multiple of the FIFO to be transmitted. + +Changes between V2.5.4 and V2.5.5 - Released January 3, 2005 + + This version adds support for the Atmel SAM7 ARM7 microcontrollers + along with the IAR development tools. + + Other changes: + + + Renamed the Demo/ARM7 directory to Demo/ARM7_LPC2106_GCC. + + Renamed the Demo/ARM7_Keil directory to Demo/ARM7_LPC2129_Keil. + + Modified the Philips ARM7 serial interrupt service routines to only + process one interrupt per call. This seems to enable the ISR to + operate more quickly. + + Removed the 'far' keyword from the Open Watcom portable layer source + files. This allows their use with V1.3 of Open Watcom. + + Minor modifications to the SDCC build files to allow their use under + Linux. Thanks to Frieder Ferlemann for this contribution. + + Small change to sTaskCreate() to allow a context switch even when + pxCreatedTask is NULL. Thanks to Kamil for this contribution. + + inline keyword removed from vTaskSwitchContext() and VTaskIncrementTick() + definitions. + +Changes between V2.5.3 and V2.5.4 - Released Dec 1, 2004 + + This is an important maintenance release. + + The function cTaskResumeAll() has been modified so it can be used safely + prior to the kernel being initialised. This was an issue as + cTaskResumeAll() is called from pvPortMalloc(). Thanks to Daniel Braun + for highlighting this issue. + +Changes between V2.5.2 and V2.5.3 - Released Nov 2, 2004 + + The critical section handling functions have been changed for the GCC ARM7 + port. Some optimisation levels use the stack differently to others. This + means the interrupt flags cannot always be stored on the stack and are + instead now stored in a variable, which is then saved as part of the + threads context. This allows the GCC ARM7 port to be used at all + optimisation levels - including -Os. + + Other minor changes: + + + MSP430 definition of usCriticalNesting now uses the volatile qualifier. + This is probably not required but added just in case. + +Changes between V2.5.1 and V2.5.2 - Released Oct 26, 2004 + + + Added the Keil ARM7 port. + + Slight modification to comtest.c to make the delay periods more random. + This creates a better test condition. + +Changes between V2.5.0 and V2.5.1 - Released Oct 9, 2004 + + + Added the MSP430 port. + + Extra comments added to the GCC ARM7 port.c and portISR.c files. + + The memory pool allocated within heap_1.c has been placed within a + structure to ensure correct memory alignment on 32bit systems. + + Within the GCC ARM7 serial drivers an extra check is made to ensure + the post to the queue was successful if then attempting immediately + retrieve the posted character. + + Changed the name of the constant portTICKS_PER_MS to portTICK_PERIOD_MS + as the old name was misleading. + + +Changes between V2.4.2 and V2.5.0 - Released Aug 12, 2004 + + The RTOS source code download now includes three separate memory allocation + schemes - so you can choose the most appropriate for your application. + These are found in the Source/Portable/MemMang directory. The demo + application projects have also been updated to demonstrate the new schemes. + See the "Memory Management" page of the API documentation for more details. + + + Added heap_1.c, heap_2.c and heap_3.c in the Source/Portable/MemMang + directory. + + Replaced the portheap.c files for each demo application with one of the + new memory allocation files. + + Updated the portmacro.h file for each demo application to include the + constants required for the new memory allocators: portTOTAL_HEAP_SIZE and + portBYTE_ALIGNMENT. + + Added a new test to the ARM7 demo application that tests the operation + of the heap_2 memory allocator. + + +Changes between V2.4.1 and V2.4.2 - Released July 14, 2004 + + + The ARM7 port now supports THUMB mode. + + Modification to the ARM7 demo application serial port driver. + +Changes between V2.4.0 and V2.4.1 - Released July 2, 2004 + + + Rationalised the ARM7 port version of portEXIT_CRITICAL() - + improvements provided by Bill Knight. + + Made demo serial driver more complete and robust. + + +Changes between V2.4.0 and V2.3.1 - Released June 30, 2004 + + + Added the first ARM7 port - thanks to Bill Knight for the assistance + provided. + + Added extra files to the Demo/Common/Minimal directory. These are + equivalent to their Demo/Common/Full counterparts but with the + calls to the functions defined in print.c removed. + + Added TABLAT to the list of registers saved as part of a PIC18 context. + +Changes between V2.3.0 and V2.3.1 - Released June 25, 2004 + + + Changed the way the vector table is defined to be more portable. + + Corrected the definitions of SPH and SPL in portmacro.s90. + The previous definitions prevented V2.3.0 operating if the iom323.h + header file was included in portmacro.s90. + +Changes between V2.2.0 and V2.3.0 - Released June 19, 2004 + + + Added an AVR port that uses the IAR compiler. + + Explicit use of 'signed' qualifier on plain char types. + + Modified the Open Watcom project files to use 'signed' as the + default char type. + + Changed odd calculation of initial pxTopOfStack value when + portSTACK_GROWTH < 0. + + Added inline qualifier to context switch functions within task.c. + Ports that do not support the (non ANSI) inline keyword have the + inline #define'd away in their respective portmacro.h files. + +Changes between V2.1.1 and V2.2.0 - Released May 18, 2004 + + + Added Cygnal 8051 port. + + PCLATU and PCLATH are now saved as part of the PIC18 context. This + allows function pointers to be used within threads. Thanks to Javier + Espeche for the enhancement. + + Minor changes to demo application files to reduce stack usage. + + Minor changes to prevent compiler warnings when compiling the new port. + +Changes between V2.1.0 and V2.1.1 - Released March 12, 2004 + + + Bug fix - pxCurrentTCB is now initialised before the call to + prvInitialiseTaskLists(). Previously pxCurrentTCB could be accessed + while null during the initialisation sequence. Thanks to Giuseppe + Franco for the correction. + +Changes between V2.0.0 and V2.1.0 - Released Feb 29, 2004 + + V2.1.0 has significant reworks that greatly reduce the amount of time + the kernel has interrupts disabled. The first section of modifications + listed here must be taken into account by users. The second section + are related to the kernel implementation and as such are transparent. + + Section1 : + + + The typedef TickType_t has been introduced. All delay times should + now use a variable of type TickType_t in place of the unsigned long's + used previously. API function prototypes have been updated + appropriately. + + The configuration macro USE_16_BIT_TICKS has been introduced. If set + to 1 TickType_t is defined as an unsigned short. If set to 0 + TickType_t is defined as an unsigned long. See the configuration + section of the API documentation for more details. + + The configuration macro INCLUDE_vTaskSuspendAll is now obsolete. + + vTaskResumeAll() has been renamed cTaskResumeAll() as it now returns a + value (see the API documentation). + + ulTaskGetTickCount() has been renamed xTaskGetTickCount() as the type + it returns now depends on the USE_16_BIT_TICKS definition. + + cQueueReceive() must now >never< be used from within an ISR. Use the new + cQueueReceiveFromISR() function instead. + + Section 2: + + + A mechanism has been introduced that allows a queue to be accessed by + a task and ISR simultaneously. + + A "pending ready" queue has been introduced that enables interrupts to + be processed when the scheduler is suspended. + + The list implementation has been improved to provide faster item + removal. + + The scheduler now makes use of the scheduler suspend mechanism in places + where previously interrupts were disabled. + +Changes between V1.2.6 and V2.0.0 - Released Jan 31, 2004 + + + Introduced new API functions: + vTaskPriorityGet () + vTaskPrioritySet () + vTaskSuspend () + vTaskResume () + vTaskSuspendAll () + vTaskResumeAll () + + Added conditional compilation options that allow the components of the + kernel that are unused by an application to be excluded from the build. + See the Configuration section on the WEB site for more information (on + the API pages). The macros have been added to each portmacro.h file ( + sometimes called prtmacro.h). + + Rearranged threads.c. + + Added demo application file dynamic.c. + + Updated the PC demo application to make use of dynamic.c. + + Updated the documentation contained in the kernel header files. + + Creating a task now causes a context switch if the task being created + has a higher priority than the calling task - assuming the kernel is + running. + + vTaskDelete() now only causes a context switch if the calling task is + the task being deleted. + +Changes between V1.2.5 and V1.2.6 - Released December 31, 2003 + + Barring the change to the interrupt vector (PIC port) these are minor + enhancements. + + + The interrupt vector used for the PIC master ISR has been changed from + 0x18 to 0x08 - where it should have always been. The incorrect address + still works but probably executes a number of NOP's before getting to the + ISR. + + Changed the baud rate used by the AVR demo application to 38400. This + has an error percentage of less than one percent with an 8MHz clock. + + Raised the priority of the Rx task in demo\full\comtest.c. This only + affects the Flashlite and PC ports. This was done to prevent the Rx + buffer becoming full. + + Reverted the Flashlite COM port driver back so it does not use the DMA. + The DMA appears to miss characters under stress. The Borland Flashlite + port was also calculating a register value incorrectly resulting in the + wrong DMA source address being used. The same code worked fine when + compiling with Open Watcom. Other minor enhancements were made to the + interrupt handling. + + Modified the PIC serial Rx ISR to check for and clear overrun errors. + Overrun errors seem to prevent any further characters being received. + + The PIC demo projects now have some optimisation switched on. + + +Changes between V1.2.4 and V1.2.5 + + Small fix made to the PIC specific port.c file described below. + + + Introduced portGLOBAL_INTERRUPT_FLAG definition to test the global + interrupt flag setting. Using the two bits defined within + portINITAL_INTERRUPT_STATE was causing the w register to get clobbered + before the test was performed. + +Changes between V1.2.3 and V1.2.4 + + V1.2.4 contains a release version of the PIC18 port. + An optional exception has been included with the GPL. See the licensing + section of www.FreeRTOS.org for details. + + + The function xPortInitMinimal() has been renamed to + xSerialPortInitMinimal() and the function xPortInit() has been renamed + to xSerialPortInit(). + + The function sSerialPutChar() has been renamed cSerialPutChar() and + the function return type chaned to portCHAR. + + The integer and flop threads now include calls to tskYIELD(), allowing + them to be used with the cooperative scheduler. + + All the demo applications now use the integer and comtest threads when the + cooperative scheduler is being used. Previously they were only used with + the preemptive scheduler. + + Minor changes made to operation of minimal versions of comtest.c and + integer.c. + + The ATMega port definition of portCPU_CLOSK_HZ definition changed to + 8MHz base 10, previously it base 16. + + + +Changes between V1.2.2a and V1.2.3 + + The only change of any significance is to the license, which has changed + from the Open Software License to the GNU GPL. + + The zip file also contains a pre-release version of the PIC18 port. This + has not yet completed testing and as such does not constitute part of the + V1.2.3 release. It is still however covered by the GNU GPL. + + There are minor source code changes to accommodate the PIC C compiler. + These mainly involve more explicit casting. + + + sTaskCreate() has been modified slightly to make use of the + portSTACK_GROWTH macro. This is required for the PIC port where the + stack grows in the opposite direction to the other existing ports. + + prvCheckTasksWaitingTermination() has been modified slightly to bring + the decrementing of usCurrentNumberOfTasks within the critical section, + where it should have been since the creation of an eight bit port. + +Changes between V1.2.2 and V1.2.2a + + The makefile and buildcoff.bat files included with the AVR demo application + have been modified for use with the September 2003 build of WinAVR. No + source files have changed. + +Changes between V1.2.1 and V1.2.2 + + There are only minor changes here to allow the PC and Flashlite 186 ports + to use the Borland V4.52 compiler, as supplied with the Flashlite 186 + development kit. + + + Introduced a BCC directory under source\portable. This contains all the + files specific to the Borland compiler port. + + Corrected the macro naming of portMS_PER_TICK to portTICKS_PER_MS. + + Modified comtest.c to increase the rate at which the string is + transmitted and received on the serial port. The Flashlite 186 demo + app baud rate has also been increased. + + The values of the constants used in both integer.c files have been + increased to force the Borland compiler to use 32 bit values. The + Borland optimiser placed the previous values in 16 bit registers, and in + So doing invalidated the test. + +Changes between V1.2.0 and V1.2.1 + + This version includes some minor changes to the list implementation aimed + at improving the context switch time - with is now approximately 10% faster. + Changes include the removal of some null pointer assignment checks. These + were redundant where the scheduler uses the list functions, but means any + user application choosing to use the same list functions must now check + that no NULL pointers are passed as a parameter. + + The Flashlite 186 serial port driver has also been modified to use a DMA + channel for transmissions. The serial driver is fully functional but still + under development. Flashlite users may prefer to use V1.2.0 for now. + + Details: + + + Changed the baud rate for the ATMega323 serial test from 19200 to 57600. + + Use vSerialPutString() instead of single character puts in + Demo\Full\Comtest.c. This allows the use of the flashlite DMA serial + driver. Also the check variable only stops incrementing after two + consecutive failures. + + semtest.c creates four threads, two of which operate at the idle priority. + The threads that operate at the idle priority now use a lower expected + count than those running at a higher priority. This prevents the low + priority threads from signalling an error because they have not been + scheduled enough time for each of them to count the shared variable to + the higher original value. + + The flashlite 186 serial driver now uses a DMA channel for transmissions. + + Removed the volatile modifier from the list function parameters. This was + only ever included to prevent compiler warnings. Now warnings are + removed by casting parameters where the calls are made. + + prvListGetOwnerOfNextEntry() and prvListGetOwnerOfHeadEntry() have been + removed from list.c and added as macros in list.h. + + usNumberOfItems has been added to the list structure. This removes the + need for a pointer comparison when checking if a list is empty, and so + is slightly faster. + + Removed the NULL check in vListRemove(). This makes the call faster but + necessitates any application code utilising the list implementation to + ensure NULL pointers are not passed. + + Renamed portTICKS_PER_MS definition to portMS_PER_TICK (milli seconds + per tick). This is what it always should have been. + +Changes between V1.01 and V1.2.0 + + The majority of these changes were made to accommodate the 8bit AVR port. + The scheduler workings have not changed, but some of the data types used + have been made more friendly to an eight bit environment. + + Details: + + + Changed the version numbering format. + + Added AVR port. + + Split the directory demo\common into demo\common\minimal and + demo\common\full. The files in the full directory are for systems with + a display (currently PC and Flashlite 186 demo's). The files in the + minimal directory are for systems with limited RAM and no display + (currently MegaAVR). + + Minor changes to demo application function prototypes to make more use + of 8bit data types. + + Within the scheduler itself the following functions have slightly + modified declarations to make use of 8bit data types where possible: + xQueueCreate(), + sQueueReceive(), + sQUeueReceive(), + usQueueMessageWaiting(), + sQueueSendFromISR(), + sSemaphoreTake(), + sSemaphoreGive(), + sSemaphoreGiveFromISR(), + sTaskCreate(), + sTaskMoveFromEventList(). + + Where the return type has changed the function name has also changed in + accordance with the naming convention. For example + usQueueMessageWaiting() has become ucQueueMessageWaiting(). + + The definition tskMAX_PRIORITIES has been moved from task.h to + portmacro.h and renamed portMAX_PRIORITIES. This allows different + ports to allocate a different maximum number of priorities. + + By default the trace facility is off, previously USE_TRACE_FACILITY + was defined. + + comtest.c now uses a psuedo random delay between sends. This allows for + better testing as the interrupts do not arrive at regular intervals. + + Minor change to the Flashlite serial port driver. The driver is written + to demonstrate the scheduler and is not written to be efficient. + + + +Changes between V1.00 and V1.01 + + These changes improve the ports. The scheduler itself has not changed. + + Improved context switch mechanism used when performing a context + switch from an ISR (both the tick ISR and the serial comms ISR's within + the demo application). The new mechanism is faster and uses less stack. + + The assembler file portasm.asm has been replaced by a header file + portasm.h. This includes a few assembler macro definitions. + + All saving and restoring of registers onto/off of the stack is now handled + by the compiler. This means the initial stack setup for a task has to + mimic the stack used by the compiler, which is different for debug and + release builds. + + Slightly changed the operation of the demo application, details below. + + Details: + + + portSWITCH_CONTEXT() replaced by vPortFirstContext(). + + pxPortInitialiseStack() modified to replicate the stack used by the + compiler. + + portasm.asm file removed. + + portasm.h introduced. This contains macro definitions for + portSWITCH_CONTEXT() and portFIRST_CONTEXT(). + + Context switch from ISR now uses the compiler generated interrupt + mechanism. This is done simply by calling portSWITCH_CONTEXT and leaving + the save/restore to compiler generated code. + + Calls to taskYIELD() during ISR's have been replaced by calling the + simpler and faster portSWITCH_CONTEXT(). + + The Flashlite 186 port now uses 186 instruction set (used to use 80x86 + instructions only). + + The blocking queue threads within the demo application did not operate + quite as described. This has been corrected. + + The priority of the comtest Rx task within the demo application has been + lowered. Received characters are now processed (read from the queue) at + the idle priority, allowing low priority threads to run evenly at times of + a high communications overhead. + + Prevent the call to kbhit() in main.c for debug builds as the debugger + seems to have problems stepping over the call. This if for the PC port + only. + + + diff --git a/MODULES/FreeRTOS/doc/LICENSE.md b/MODULES/FreeRTOS/doc/LICENSE.md new file mode 100644 index 0000000..9cf1062 --- /dev/null +++ b/MODULES/FreeRTOS/doc/LICENSE.md @@ -0,0 +1,19 @@ +MIT License + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. diff --git a/MODULES/FreeRTOS/doc/Quick_Start_Guide.url b/MODULES/FreeRTOS/doc/Quick_Start_Guide.url new file mode 100644 index 0000000..ebefebd --- /dev/null +++ b/MODULES/FreeRTOS/doc/Quick_Start_Guide.url @@ -0,0 +1,5 @@ +[InternetShortcut] +URL=https://www.FreeRTOS.org/FreeRTOS-quick-start-guide.html +IDList= +[{000214A0-0000-0000-C000-000000000046}] +Prop3=19,2 diff --git a/MODULES/FreeRTOS/doc/README.md b/MODULES/FreeRTOS/doc/README.md new file mode 100644 index 0000000..3359253 --- /dev/null +++ b/MODULES/FreeRTOS/doc/README.md @@ -0,0 +1,39 @@ +## Getting started +This repository contains FreeRTOS kernel source/header files and kernel ports only. This repository is referenced as a submodule in [FreeRTOS/FreeRTOS](https://github.com/FreeRTOS/FreeRTOS) repository, which contains pre-configured demo application projects under ```FreeRTOS/Demo``` directory. + +The easiest way to use FreeRTOS is to start with one of the pre-configured demo application projects. That way you will have the correct FreeRTOS source files included, and the correct include paths configured. Once a demo application is building and executing you can remove the demo application files, and start to add in your own application source files. See the [FreeRTOS Kernel Quick Start Guide](https://www.FreeRTOS.org/FreeRTOS-quick-start-guide.html) for detailed instructions and other useful links. + +Additionally, for FreeRTOS kernel feature information refer to the [Developer Documentation](https://www.FreeRTOS.org/features.html), and [API Reference](https://www.FreeRTOS.org/a00106.html). + +### Getting help +If you have any questions or need assistance troubleshooting your FreeRTOS project, we have an active community that can help on the [FreeRTOS Community Support Forum](https://forums.freertos.org). + +## Cloning this repository + +To clone using HTTPS: +``` +git clone https://github.com/FreeRTOS/FreeRTOS-Kernel.git +``` +Using SSH: +``` +git clone git@github.com:FreeRTOS/FreeRTOS-Kernel.git +``` + +## Repository structure +- The root of this repository contains the three files that are common to +every port - list.c, queue.c and threads.c. The kernel is contained within these +three files. croutine.c implements the optional co-routine functionality - which +is normally only used on very memory limited systems. + +- The ```./portable``` directory contains the files that are specific to a particular microcontroller and/or compiler. +See the readme file in the ```./portable``` directory for more information. + +- The ```./include``` directory contains the real time kernel header files. + +### Code Formatting +FreeRTOS files are formatted using the "uncrustify" tool. The configuration file used by uncrustify can be found in the [FreeRTOS/FreeRTOS repository](https://github.com/FreeRTOS/FreeRTOS/blob/master/tools/uncrustify.cfg). + +### Spelling +*lexicon.txt* contains words that are not traditionally found in an English dictionary. It is used by the spellchecker to verify the various jargon, variable names, and other odd words used in the FreeRTOS code base. If your pull request fails to pass the spelling and you believe this is a mistake, then add the word to *lexicon.txt*. +Note that only the FreeRTOS Kernel source files are checked for proper spelling, the portable section is ignored. + diff --git a/MODULES/FreeRTOS/inc/FreeRTOS.h b/MODULES/FreeRTOS/inc/FreeRTOS.h new file mode 100644 index 0000000..68931ff --- /dev/null +++ b/MODULES/FreeRTOS/inc/FreeRTOS.h @@ -0,0 +1,1345 @@ +/* + * FreeRTOS Kernel V10.4.3 LTS Patch 2 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef INC_FREERTOS_H +#define INC_FREERTOS_H + +/* + * Include the generic headers required for the FreeRTOS port being used. + */ +#include + +/* + * If stdint.h cannot be located then: + * + If using GCC ensure the -nostdint options is *not* being used. + * + Ensure the project's include path includes the directory in which your + * compiler stores stdint.h. + * + Set any compiler options necessary for it to support C99, as technically + * stdint.h is only mandatory with C99 (FreeRTOS does not require C99 in any + * other way). + * + The FreeRTOS download includes a simple stdint.h definition that can be + * used in cases where none is provided by the compiler. The files only + * contains the typedefs required to build FreeRTOS. Read the instructions + * in FreeRTOS/source/stdint.readme for more information. + */ +#include /* READ COMMENT ABOVE. */ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* Application specific configuration options. */ +#include "FreeRTOSConfig.h" + +/* Basic FreeRTOS definitions. */ +#include "projdefs.h" + +/* Definitions specific to the port being used. */ +#include "portable.h" + +/* Must be defaulted before configUSE_NEWLIB_REENTRANT is used below. */ +#ifndef configUSE_NEWLIB_REENTRANT + #define configUSE_NEWLIB_REENTRANT 0 +#endif + +/* Required if struct _reent is used. */ +#if ( configUSE_NEWLIB_REENTRANT == 1 ) + #include +#endif + +/* + * Check all the required application specific macros have been defined. + * These macros are application specific and (as downloaded) are defined + * within FreeRTOSConfig.h. + */ + +#ifndef configMINIMAL_STACK_SIZE + #error Missing definition: configMINIMAL_STACK_SIZE must be defined in FreeRTOSConfig.h. configMINIMAL_STACK_SIZE defines the size (in words) of the stack allocated to the idle task. Refer to the demo project provided for your port for a suitable value. +#endif + +#ifndef configMAX_PRIORITIES + #error Missing definition: configMAX_PRIORITIES must be defined in FreeRTOSConfig.h. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#if configMAX_PRIORITIES < 1 + #error configMAX_PRIORITIES must be defined to be greater than or equal to 1. +#endif + +#ifndef configUSE_PREEMPTION + #error Missing definition: configUSE_PREEMPTION must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_IDLE_HOOK + #error Missing definition: configUSE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_TICK_HOOK + #error Missing definition: configUSE_TICK_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_16_BIT_TICKS + #error Missing definition: configUSE_16_BIT_TICKS must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. +#endif + +#ifndef configUSE_CO_ROUTINES + #define configUSE_CO_ROUTINES 0 +#endif + +#ifndef INCLUDE_vTaskPrioritySet + #define INCLUDE_vTaskPrioritySet 0 +#endif + +#ifndef INCLUDE_uxTaskPriorityGet + #define INCLUDE_uxTaskPriorityGet 0 +#endif + +#ifndef INCLUDE_vTaskDelete + #define INCLUDE_vTaskDelete 0 +#endif + +#ifndef INCLUDE_vTaskSuspend + #define INCLUDE_vTaskSuspend 0 +#endif + +#ifdef INCLUDE_xTaskDelayUntil + #ifdef INCLUDE_vTaskDelayUntil + /* INCLUDE_vTaskDelayUntil was replaced by INCLUDE_xTaskDelayUntil. Backward + * compatibility is maintained if only one or the other is defined, but + * there is a conflict if both are defined. */ + #error INCLUDE_vTaskDelayUntil and INCLUDE_xTaskDelayUntil are both defined. INCLUDE_vTaskDelayUntil is no longer required and should be removed + #endif +#endif + +#ifndef INCLUDE_xTaskDelayUntil + #ifdef INCLUDE_vTaskDelayUntil + /* If INCLUDE_vTaskDelayUntil is set but INCLUDE_xTaskDelayUntil is not then + * the project's FreeRTOSConfig.h probably pre-dates the introduction of + * xTaskDelayUntil and setting INCLUDE_xTaskDelayUntil to whatever + * INCLUDE_vTaskDelayUntil is set to will ensure backward compatibility. + */ + #define INCLUDE_xTaskDelayUntil INCLUDE_vTaskDelayUntil + #endif +#endif + +#ifndef INCLUDE_xTaskDelayUntil + #define INCLUDE_xTaskDelayUntil 0 +#endif + +#ifndef INCLUDE_vTaskDelay + #define INCLUDE_vTaskDelay 0 +#endif + +#ifndef INCLUDE_xTaskGetIdleTaskHandle + #define INCLUDE_xTaskGetIdleTaskHandle 0 +#endif + +#ifndef INCLUDE_xTaskAbortDelay + #define INCLUDE_xTaskAbortDelay 0 +#endif + +#ifndef INCLUDE_xQueueGetMutexHolder + #define INCLUDE_xQueueGetMutexHolder 0 +#endif + +#ifndef INCLUDE_xSemaphoreGetMutexHolder + #define INCLUDE_xSemaphoreGetMutexHolder INCLUDE_xQueueGetMutexHolder +#endif + +#ifndef INCLUDE_xTaskGetHandle + #define INCLUDE_xTaskGetHandle 0 +#endif + +#ifndef INCLUDE_uxTaskGetStackHighWaterMark + #define INCLUDE_uxTaskGetStackHighWaterMark 0 +#endif + +#ifndef INCLUDE_uxTaskGetStackHighWaterMark2 + #define INCLUDE_uxTaskGetStackHighWaterMark2 0 +#endif + +#ifndef INCLUDE_eTaskGetState + #define INCLUDE_eTaskGetState 0 +#endif + +#ifndef INCLUDE_xTaskResumeFromISR + #define INCLUDE_xTaskResumeFromISR 1 +#endif + +#ifndef INCLUDE_xTimerPendFunctionCall + #define INCLUDE_xTimerPendFunctionCall 0 +#endif + +#ifndef INCLUDE_xTaskGetSchedulerState + #define INCLUDE_xTaskGetSchedulerState 0 +#endif + +#ifndef INCLUDE_xTaskGetCurrentTaskHandle + #define INCLUDE_xTaskGetCurrentTaskHandle 0 +#endif + +#if configUSE_CO_ROUTINES != 0 + #ifndef configMAX_CO_ROUTINE_PRIORITIES + #error configMAX_CO_ROUTINE_PRIORITIES must be greater than or equal to 1. + #endif +#endif + +#ifndef configUSE_DAEMON_TASK_STARTUP_HOOK + #define configUSE_DAEMON_TASK_STARTUP_HOOK 0 +#endif + +#ifndef configUSE_APPLICATION_TASK_TAG + #define configUSE_APPLICATION_TASK_TAG 0 +#endif + +#ifndef configNUM_THREAD_LOCAL_STORAGE_POINTERS + #define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0 +#endif + +#ifndef configUSE_RECURSIVE_MUTEXES + #define configUSE_RECURSIVE_MUTEXES 0 +#endif + +#ifndef configUSE_MUTEXES + #define configUSE_MUTEXES 0 +#endif + +#ifndef configUSE_TIMERS + #define configUSE_TIMERS 0 +#endif + +#ifndef configUSE_COUNTING_SEMAPHORES + #define configUSE_COUNTING_SEMAPHORES 0 +#endif + +#ifndef configUSE_ALTERNATIVE_API + #define configUSE_ALTERNATIVE_API 0 +#endif + +#ifndef portCRITICAL_NESTING_IN_TCB + #define portCRITICAL_NESTING_IN_TCB 0 +#endif + +#ifndef configMAX_TASK_NAME_LEN + #define configMAX_TASK_NAME_LEN 16 +#endif + +#ifndef configIDLE_SHOULD_YIELD + #define configIDLE_SHOULD_YIELD 1 +#endif + +#if configMAX_TASK_NAME_LEN < 1 + #error configMAX_TASK_NAME_LEN must be set to a minimum of 1 in FreeRTOSConfig.h +#endif + +#ifndef configASSERT + #define configASSERT( x ) + #define configASSERT_DEFINED 0 +#else + #define configASSERT_DEFINED 1 +#endif + +/* configPRECONDITION should be defined as configASSERT. + * The CBMC proofs need a way to track assumptions and assertions. + * A configPRECONDITION statement should express an implicit invariant or + * assumption made. A configASSERT statement should express an invariant that must + * hold explicit before calling the code. */ +#ifndef configPRECONDITION + #define configPRECONDITION( X ) configASSERT( X ) + #define configPRECONDITION_DEFINED 0 +#else + #define configPRECONDITION_DEFINED 1 +#endif + +#ifndef portMEMORY_BARRIER + #define portMEMORY_BARRIER() +#endif + +#ifndef portSOFTWARE_BARRIER + #define portSOFTWARE_BARRIER() +#endif + +/* The timers module relies on xTaskGetSchedulerState(). */ +#if configUSE_TIMERS == 1 + + #ifndef configTIMER_TASK_PRIORITY + #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_PRIORITY must also be defined. + #endif /* configTIMER_TASK_PRIORITY */ + + #ifndef configTIMER_QUEUE_LENGTH + #error If configUSE_TIMERS is set to 1 then configTIMER_QUEUE_LENGTH must also be defined. + #endif /* configTIMER_QUEUE_LENGTH */ + + #ifndef configTIMER_TASK_STACK_DEPTH + #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined. + #endif /* configTIMER_TASK_STACK_DEPTH */ + +#endif /* configUSE_TIMERS */ + +#ifndef portSET_INTERRUPT_MASK_FROM_ISR + #define portSET_INTERRUPT_MASK_FROM_ISR() 0 +#endif + +#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR + #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue +#endif + +#ifndef portCLEAN_UP_TCB + #define portCLEAN_UP_TCB( pxTCB ) ( void ) pxTCB +#endif + +#ifndef portPRE_TASK_DELETE_HOOK + #define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxYieldPending ) +#endif + +#ifndef portSETUP_TCB + #define portSETUP_TCB( pxTCB ) ( void ) pxTCB +#endif + +#ifndef configQUEUE_REGISTRY_SIZE + #define configQUEUE_REGISTRY_SIZE 0U +#endif + +#if ( configQUEUE_REGISTRY_SIZE < 1 ) + #define vQueueAddToRegistry( xQueue, pcName ) + #define vQueueUnregisterQueue( xQueue ) + #define pcQueueGetName( xQueue ) +#endif + +#ifndef portPOINTER_SIZE_TYPE + #define portPOINTER_SIZE_TYPE uint32_t +#endif + +/* Remove any unused trace macros. */ +#ifndef traceSTART + +/* Used to perform any necessary initialisation - for example, open a file + * into which trace is to be written. */ + #define traceSTART() +#endif + +#ifndef traceEND + +/* Use to close a trace, for example close a file into which trace has been + * written. */ + #define traceEND() +#endif + +#ifndef traceTASK_SWITCHED_IN + +/* Called after a task has been selected to run. pxCurrentTCB holds a pointer + * to the task control block of the selected task. */ + #define traceTASK_SWITCHED_IN() +#endif + +#ifndef traceINCREASE_TICK_COUNT + +/* Called before stepping the tick count after waking from tickless idle + * sleep. */ + #define traceINCREASE_TICK_COUNT( x ) +#endif + +#ifndef traceLOW_POWER_IDLE_BEGIN + /* Called immediately before entering tickless idle. */ + #define traceLOW_POWER_IDLE_BEGIN() +#endif + +#ifndef traceLOW_POWER_IDLE_END + /* Called when returning to the Idle task after a tickless idle. */ + #define traceLOW_POWER_IDLE_END() +#endif + +#ifndef traceTASK_SWITCHED_OUT + +/* Called before a task has been selected to run. pxCurrentTCB holds a pointer + * to the task control block of the task being switched out. */ + #define traceTASK_SWITCHED_OUT() +#endif + +#ifndef traceTASK_PRIORITY_INHERIT + +/* Called when a task attempts to take a mutex that is already held by a + * lower priority task. pxTCBOfMutexHolder is a pointer to the TCB of the task + * that holds the mutex. uxInheritedPriority is the priority the mutex holder + * will inherit (the priority of the task that is attempting to obtain the + * muted. */ + #define traceTASK_PRIORITY_INHERIT( pxTCBOfMutexHolder, uxInheritedPriority ) +#endif + +#ifndef traceTASK_PRIORITY_DISINHERIT + +/* Called when a task releases a mutex, the holding of which had resulted in + * the task inheriting the priority of a higher priority task. + * pxTCBOfMutexHolder is a pointer to the TCB of the task that is releasing the + * mutex. uxOriginalPriority is the task's configured (base) priority. */ + #define traceTASK_PRIORITY_DISINHERIT( pxTCBOfMutexHolder, uxOriginalPriority ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_RECEIVE + +/* Task is about to block because it cannot read from a + * queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + * upon which the read was attempted. pxCurrentTCB points to the TCB of the + * task that attempted the read. */ + #define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_PEEK + +/* Task is about to block because it cannot read from a + * queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + * upon which the read was attempted. pxCurrentTCB points to the TCB of the + * task that attempted the read. */ + #define traceBLOCKING_ON_QUEUE_PEEK( pxQueue ) +#endif + +#ifndef traceBLOCKING_ON_QUEUE_SEND + +/* Task is about to block because it cannot write to a + * queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore + * upon which the write was attempted. pxCurrentTCB points to the TCB of the + * task that attempted the write. */ + #define traceBLOCKING_ON_QUEUE_SEND( pxQueue ) +#endif + +#ifndef configCHECK_FOR_STACK_OVERFLOW + #define configCHECK_FOR_STACK_OVERFLOW 0 +#endif + +#ifndef configRECORD_STACK_HIGH_ADDRESS + #define configRECORD_STACK_HIGH_ADDRESS 1 +#endif + +#ifndef configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H + #define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 0 +#endif + +/* The following event macros are embedded in the kernel API calls. */ + +#ifndef traceMOVED_TASK_TO_READY_STATE + #define traceMOVED_TASK_TO_READY_STATE( pxTCB ) +#endif + +#ifndef tracePOST_MOVED_TASK_TO_READY_STATE + #define tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB ) +#endif + +#ifndef traceQUEUE_CREATE + #define traceQUEUE_CREATE( pxNewQueue ) +#endif + +#ifndef traceQUEUE_CREATE_FAILED + #define traceQUEUE_CREATE_FAILED( ucQueueType ) +#endif + +#ifndef traceCREATE_MUTEX + #define traceCREATE_MUTEX( pxNewQueue ) +#endif + +#ifndef traceCREATE_MUTEX_FAILED + #define traceCREATE_MUTEX_FAILED() +#endif + +#ifndef traceGIVE_MUTEX_RECURSIVE + #define traceGIVE_MUTEX_RECURSIVE( pxMutex ) +#endif + +#ifndef traceGIVE_MUTEX_RECURSIVE_FAILED + #define traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex ) +#endif + +#ifndef traceTAKE_MUTEX_RECURSIVE + #define traceTAKE_MUTEX_RECURSIVE( pxMutex ) +#endif + +#ifndef traceTAKE_MUTEX_RECURSIVE_FAILED + #define traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex ) +#endif + +#ifndef traceCREATE_COUNTING_SEMAPHORE + #define traceCREATE_COUNTING_SEMAPHORE() +#endif + +#ifndef traceCREATE_COUNTING_SEMAPHORE_FAILED + #define traceCREATE_COUNTING_SEMAPHORE_FAILED() +#endif + +#ifndef traceQUEUE_SET_SEND + #define traceQUEUE_SET_SEND traceQUEUE_SEND +#endif + +#ifndef traceQUEUE_SEND + #define traceQUEUE_SEND( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FAILED + #define traceQUEUE_SEND_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE + #define traceQUEUE_RECEIVE( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK + #define traceQUEUE_PEEK( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FAILED + #define traceQUEUE_PEEK_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FROM_ISR + #define traceQUEUE_PEEK_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FAILED + #define traceQUEUE_RECEIVE_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FROM_ISR + #define traceQUEUE_SEND_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_SEND_FROM_ISR_FAILED + #define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FROM_ISR + #define traceQUEUE_RECEIVE_FROM_ISR( pxQueue ) +#endif + +#ifndef traceQUEUE_RECEIVE_FROM_ISR_FAILED + #define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_PEEK_FROM_ISR_FAILED + #define traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue ) +#endif + +#ifndef traceQUEUE_DELETE + #define traceQUEUE_DELETE( pxQueue ) +#endif + +#ifndef traceTASK_CREATE + #define traceTASK_CREATE( pxNewTCB ) +#endif + +#ifndef traceTASK_CREATE_FAILED + #define traceTASK_CREATE_FAILED() +#endif + +#ifndef traceTASK_DELETE + #define traceTASK_DELETE( pxTaskToDelete ) +#endif + +#ifndef traceTASK_DELAY_UNTIL + #define traceTASK_DELAY_UNTIL( x ) +#endif + +#ifndef traceTASK_DELAY + #define traceTASK_DELAY() +#endif + +#ifndef traceTASK_PRIORITY_SET + #define traceTASK_PRIORITY_SET( pxTask, uxNewPriority ) +#endif + +#ifndef traceTASK_SUSPEND + #define traceTASK_SUSPEND( pxTaskToSuspend ) +#endif + +#ifndef traceTASK_RESUME + #define traceTASK_RESUME( pxTaskToResume ) +#endif + +#ifndef traceTASK_RESUME_FROM_ISR + #define traceTASK_RESUME_FROM_ISR( pxTaskToResume ) +#endif + +#ifndef traceTASK_INCREMENT_TICK + #define traceTASK_INCREMENT_TICK( xTickCount ) +#endif + +#ifndef traceTIMER_CREATE + #define traceTIMER_CREATE( pxNewTimer ) +#endif + +#ifndef traceTIMER_CREATE_FAILED + #define traceTIMER_CREATE_FAILED() +#endif + +#ifndef traceTIMER_COMMAND_SEND + #define traceTIMER_COMMAND_SEND( xTimer, xMessageID, xMessageValueValue, xReturn ) +#endif + +#ifndef traceTIMER_EXPIRED + #define traceTIMER_EXPIRED( pxTimer ) +#endif + +#ifndef traceTIMER_COMMAND_RECEIVED + #define traceTIMER_COMMAND_RECEIVED( pxTimer, xMessageID, xMessageValue ) +#endif + +#ifndef traceMALLOC + #define traceMALLOC( pvAddress, uiSize ) +#endif + +#ifndef traceFREE + #define traceFREE( pvAddress, uiSize ) +#endif + +#ifndef traceEVENT_GROUP_CREATE + #define traceEVENT_GROUP_CREATE( xEventGroup ) +#endif + +#ifndef traceEVENT_GROUP_CREATE_FAILED + #define traceEVENT_GROUP_CREATE_FAILED() +#endif + +#ifndef traceEVENT_GROUP_SYNC_BLOCK + #define traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor ) +#endif + +#ifndef traceEVENT_GROUP_SYNC_END + #define traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred +#endif + +#ifndef traceEVENT_GROUP_WAIT_BITS_BLOCK + #define traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor ) +#endif + +#ifndef traceEVENT_GROUP_WAIT_BITS_END + #define traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred +#endif + +#ifndef traceEVENT_GROUP_CLEAR_BITS + #define traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear ) +#endif + +#ifndef traceEVENT_GROUP_CLEAR_BITS_FROM_ISR + #define traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear ) +#endif + +#ifndef traceEVENT_GROUP_SET_BITS + #define traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet ) +#endif + +#ifndef traceEVENT_GROUP_SET_BITS_FROM_ISR + #define traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet ) +#endif + +#ifndef traceEVENT_GROUP_DELETE + #define traceEVENT_GROUP_DELETE( xEventGroup ) +#endif + +#ifndef tracePEND_FUNC_CALL + #define tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, ret ) +#endif + +#ifndef tracePEND_FUNC_CALL_FROM_ISR + #define tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, ret ) +#endif + +#ifndef traceQUEUE_REGISTRY_ADD + #define traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName ) +#endif + +#ifndef traceTASK_NOTIFY_TAKE_BLOCK + #define traceTASK_NOTIFY_TAKE_BLOCK( uxIndexToWait ) +#endif + +#ifndef traceTASK_NOTIFY_TAKE + #define traceTASK_NOTIFY_TAKE( uxIndexToWait ) +#endif + +#ifndef traceTASK_NOTIFY_WAIT_BLOCK + #define traceTASK_NOTIFY_WAIT_BLOCK( uxIndexToWait ) +#endif + +#ifndef traceTASK_NOTIFY_WAIT + #define traceTASK_NOTIFY_WAIT( uxIndexToWait ) +#endif + +#ifndef traceTASK_NOTIFY + #define traceTASK_NOTIFY( uxIndexToNotify ) +#endif + +#ifndef traceTASK_NOTIFY_FROM_ISR + #define traceTASK_NOTIFY_FROM_ISR( uxIndexToNotify ) +#endif + +#ifndef traceTASK_NOTIFY_GIVE_FROM_ISR + #define traceTASK_NOTIFY_GIVE_FROM_ISR( uxIndexToNotify ) +#endif + +#ifndef traceSTREAM_BUFFER_CREATE_FAILED + #define traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_CREATE_STATIC_FAILED + #define traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_CREATE + #define traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_DELETE + #define traceSTREAM_BUFFER_DELETE( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RESET + #define traceSTREAM_BUFFER_RESET( xStreamBuffer ) +#endif + +#ifndef traceBLOCKING_ON_STREAM_BUFFER_SEND + #define traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND + #define traceSTREAM_BUFFER_SEND( xStreamBuffer, xBytesSent ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND_FAILED + #define traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_SEND_FROM_ISR + #define traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xBytesSent ) +#endif + +#ifndef traceBLOCKING_ON_STREAM_BUFFER_RECEIVE + #define traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE + #define traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE_FAILED + #define traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer ) +#endif + +#ifndef traceSTREAM_BUFFER_RECEIVE_FROM_ISR + #define traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength ) +#endif + +#ifndef configGENERATE_RUN_TIME_STATS + #define configGENERATE_RUN_TIME_STATS 0 +#endif + +#if ( configGENERATE_RUN_TIME_STATS == 1 ) + + #ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS + #error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined. portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base. + #endif /* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS */ + + #ifndef portGET_RUN_TIME_COUNTER_VALUE + #ifndef portALT_GET_RUN_TIME_COUNTER_VALUE + #error If configGENERATE_RUN_TIME_STATS is defined then either portGET_RUN_TIME_COUNTER_VALUE or portALT_GET_RUN_TIME_COUNTER_VALUE must also be defined. See the examples provided and the FreeRTOS web site for more information. + #endif /* portALT_GET_RUN_TIME_COUNTER_VALUE */ + #endif /* portGET_RUN_TIME_COUNTER_VALUE */ + +#endif /* configGENERATE_RUN_TIME_STATS */ + +#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS + #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() +#endif + +#ifndef configUSE_MALLOC_FAILED_HOOK + #define configUSE_MALLOC_FAILED_HOOK 0 +#endif + +#ifndef portPRIVILEGE_BIT + #define portPRIVILEGE_BIT ( ( UBaseType_t ) 0x00 ) +#endif + +#ifndef portYIELD_WITHIN_API + #define portYIELD_WITHIN_API portYIELD +#endif + +#ifndef portSUPPRESS_TICKS_AND_SLEEP + #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) +#endif + +#ifndef configEXPECTED_IDLE_TIME_BEFORE_SLEEP + #define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 2 +#endif + +#if configEXPECTED_IDLE_TIME_BEFORE_SLEEP < 2 + #error configEXPECTED_IDLE_TIME_BEFORE_SLEEP must not be less than 2 +#endif + +#ifndef configUSE_TICKLESS_IDLE + #define configUSE_TICKLESS_IDLE 0 +#endif + +#ifndef configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING + #define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( x ) +#endif + +#ifndef configPRE_SLEEP_PROCESSING + #define configPRE_SLEEP_PROCESSING( x ) +#endif + +#ifndef configPOST_SLEEP_PROCESSING + #define configPOST_SLEEP_PROCESSING( x ) +#endif + +#ifndef configUSE_QUEUE_SETS + #define configUSE_QUEUE_SETS 0 +#endif + +#ifndef portTASK_USES_FLOATING_POINT + #define portTASK_USES_FLOATING_POINT() +#endif + +#ifndef portALLOCATE_SECURE_CONTEXT + #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) +#endif + +#ifndef portDONT_DISCARD + #define portDONT_DISCARD +#endif + +#ifndef configUSE_TIME_SLICING + #define configUSE_TIME_SLICING 1 +#endif + +#ifndef configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS + #define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0 +#endif + +#ifndef configUSE_STATS_FORMATTING_FUNCTIONS + #define configUSE_STATS_FORMATTING_FUNCTIONS 0 +#endif + +#ifndef portASSERT_IF_INTERRUPT_PRIORITY_INVALID + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() +#endif + +#ifndef configUSE_TRACE_FACILITY + #define configUSE_TRACE_FACILITY 0 +#endif + +#ifndef mtCOVERAGE_TEST_MARKER + #define mtCOVERAGE_TEST_MARKER() +#endif + +#ifndef mtCOVERAGE_TEST_DELAY + #define mtCOVERAGE_TEST_DELAY() +#endif + +#ifndef portASSERT_IF_IN_ISR + #define portASSERT_IF_IN_ISR() +#endif + +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#endif + +#ifndef configAPPLICATION_ALLOCATED_HEAP + #define configAPPLICATION_ALLOCATED_HEAP 0 +#endif + +#ifndef configUSE_TASK_NOTIFICATIONS + #define configUSE_TASK_NOTIFICATIONS 1 +#endif + +#ifndef configTASK_NOTIFICATION_ARRAY_ENTRIES + #define configTASK_NOTIFICATION_ARRAY_ENTRIES 1 +#endif + +#if configTASK_NOTIFICATION_ARRAY_ENTRIES < 1 + #error configTASK_NOTIFICATION_ARRAY_ENTRIES must be at least 1 +#endif + +#ifndef configUSE_POSIX_ERRNO + #define configUSE_POSIX_ERRNO 0 +#endif + +#ifndef portTICK_TYPE_IS_ATOMIC + #define portTICK_TYPE_IS_ATOMIC 0 +#endif + +#ifndef configSUPPORT_STATIC_ALLOCATION + /* Defaults to 0 for backward compatibility. */ + #define configSUPPORT_STATIC_ALLOCATION 0 +#endif + +#ifndef configSUPPORT_DYNAMIC_ALLOCATION + /* Defaults to 1 for backward compatibility. */ + #define configSUPPORT_DYNAMIC_ALLOCATION 1 +#endif + +#ifndef configSTACK_DEPTH_TYPE + +/* Defaults to uint16_t for backward compatibility, but can be overridden + * in FreeRTOSConfig.h if uint16_t is too restrictive. */ + #define configSTACK_DEPTH_TYPE uint16_t +#endif + +#ifndef configMESSAGE_BUFFER_LENGTH_TYPE + +/* Defaults to size_t for backward compatibility, but can be overridden + * in FreeRTOSConfig.h if lengths will always be less than the number of bytes + * in a size_t. */ + #define configMESSAGE_BUFFER_LENGTH_TYPE size_t +#endif + +/* Sanity check the configuration. */ +#if ( configUSE_TICKLESS_IDLE != 0 ) + #if ( INCLUDE_vTaskSuspend != 1 ) + #error INCLUDE_vTaskSuspend must be set to 1 if configUSE_TICKLESS_IDLE is not set to 0 + #endif /* INCLUDE_vTaskSuspend */ +#endif /* configUSE_TICKLESS_IDLE */ + +#if ( ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) ) + #error configSUPPORT_STATIC_ALLOCATION and configSUPPORT_DYNAMIC_ALLOCATION cannot both be 0, but can both be 1. +#endif + +#if ( ( configUSE_RECURSIVE_MUTEXES == 1 ) && ( configUSE_MUTEXES != 1 ) ) + #error configUSE_MUTEXES must be set to 1 to use recursive mutexes +#endif + +#ifndef configINITIAL_TICK_COUNT + #define configINITIAL_TICK_COUNT 0 +#endif + +#if ( portTICK_TYPE_IS_ATOMIC == 0 ) + +/* Either variables of tick type cannot be read atomically, or + * portTICK_TYPE_IS_ATOMIC was not set - map the critical sections used when + * the tick count is returned to the standard critical section macros. */ + #define portTICK_TYPE_ENTER_CRITICAL() portENTER_CRITICAL() + #define portTICK_TYPE_EXIT_CRITICAL() portEXIT_CRITICAL() + #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR() + #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( ( x ) ) +#else + +/* The tick type can be read atomically, so critical sections used when the + * tick count is returned can be defined away. */ + #define portTICK_TYPE_ENTER_CRITICAL() + #define portTICK_TYPE_EXIT_CRITICAL() + #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() 0 + #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) ( void ) x +#endif /* if ( portTICK_TYPE_IS_ATOMIC == 0 ) */ + +/* Definitions to allow backward compatibility with FreeRTOS versions prior to + * V8 if desired. */ +#ifndef configENABLE_BACKWARD_COMPATIBILITY + #define configENABLE_BACKWARD_COMPATIBILITY 1 +#endif + +#ifndef configPRINTF + +/* configPRINTF() was not defined, so define it away to nothing. To use + * configPRINTF() then define it as follows (where MyPrintFunction() is + * provided by the application writer): + * + * void MyPrintFunction(const char *pcFormat, ... ); + #define configPRINTF( X ) MyPrintFunction X + * + * Then call like a standard printf() function, but placing brackets around + * all parameters so they are passed as a single parameter. For example: + * configPRINTF( ("Value = %d", MyVariable) ); */ + #define configPRINTF( X ) +#endif + +#ifndef configMAX + +/* The application writer has not provided their own MAX macro, so define + * the following generic implementation. */ + #define configMAX( a, b ) ( ( ( a ) > ( b ) ) ? ( a ) : ( b ) ) +#endif + +#ifndef configMIN + +/* The application writer has not provided their own MAX macro, so define + * the following generic implementation. */ + #define configMIN( a, b ) ( ( ( a ) < ( b ) ) ? ( a ) : ( b ) ) +#endif + +#if configENABLE_BACKWARD_COMPATIBILITY == 1 + #define eTaskStateGet eTaskGetState + #define portTickType TickType_t + #define xTaskHandle TaskHandle_t + #define xQueueHandle QueueHandle_t + #define xSemaphoreHandle SemaphoreHandle_t + #define xQueueSetHandle QueueSetHandle_t + #define xQueueSetMemberHandle QueueSetMemberHandle_t + #define xTimeOutType TimeOut_t + #define xMemoryRegion MemoryRegion_t + #define xTaskParameters TaskParameters_t + #define xTaskStatusType TaskStatus_t + #define xTimerHandle TimerHandle_t + #define xCoRoutineHandle CoRoutineHandle_t + #define pdTASK_HOOK_CODE TaskHookFunction_t + #define portTICK_RATE_MS portTICK_PERIOD_MS + #define pcTaskGetTaskName pcTaskGetName + #define pcTimerGetTimerName pcTimerGetName + #define pcQueueGetQueueName pcQueueGetName + #define vTaskGetTaskInfo vTaskGetInfo + #define xTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounter + +/* Backward compatibility within the scheduler code only - these definitions + * are not really required but are included for completeness. */ + #define tmrTIMER_CALLBACK TimerCallbackFunction_t + #define pdTASK_CODE TaskFunction_t + #define xListItem ListItem_t + #define xList List_t + +/* For libraries that break the list data hiding, and access list structure + * members directly (which is not supposed to be done). */ + #define pxContainer pvContainer +#endif /* configENABLE_BACKWARD_COMPATIBILITY */ + +#if ( configUSE_ALTERNATIVE_API != 0 ) + #error The alternative API was deprecated some time ago, and was removed in FreeRTOS V9.0 0 +#endif + +/* Set configUSE_TASK_FPU_SUPPORT to 0 to omit floating point support even + * if floating point hardware is otherwise supported by the FreeRTOS port in use. + * This constant is not supported by all FreeRTOS ports that include floating + * point support. */ +#ifndef configUSE_TASK_FPU_SUPPORT + #define configUSE_TASK_FPU_SUPPORT 1 +#endif + +/* Set configENABLE_MPU to 1 to enable MPU support and 0 to disable it. This is + * currently used in ARMv8M ports. */ +#ifndef configENABLE_MPU + #define configENABLE_MPU 0 +#endif + +/* Set configENABLE_FPU to 1 to enable FPU support and 0 to disable it. This is + * currently used in ARMv8M ports. */ +#ifndef configENABLE_FPU + #define configENABLE_FPU 1 +#endif + +/* Set configENABLE_TRUSTZONE to 1 enable TrustZone support and 0 to disable it. + * This is currently used in ARMv8M ports. */ +#ifndef configENABLE_TRUSTZONE + #define configENABLE_TRUSTZONE 1 +#endif + +/* Set configRUN_FREERTOS_SECURE_ONLY to 1 to run the FreeRTOS ARMv8M port on + * the Secure Side only. */ +#ifndef configRUN_FREERTOS_SECURE_ONLY + #define configRUN_FREERTOS_SECURE_ONLY 0 +#endif + +/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using + * dynamically allocated RAM, in which case when any task is deleted it is known + * that both the task's stack and TCB need to be freed. Sometimes the + * FreeRTOSConfig.h settings only allow a task to be created using statically + * allocated RAM, in which case when any task is deleted it is known that neither + * the task's stack or TCB should be freed. Sometimes the FreeRTOSConfig.h + * settings allow a task to be created using either statically or dynamically + * allocated RAM, in which case a member of the TCB is used to record whether the + * stack and/or TCB were allocated statically or dynamically, so when a task is + * deleted the RAM that was allocated dynamically is freed again and no attempt is + * made to free the RAM that was allocated statically. + * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is only true if it is possible for a + * task to be created using either statically or dynamically allocated RAM. Note + * that if portUSING_MPU_WRAPPERS is 1 then a protected task can be created with + * a statically allocated stack and a dynamically allocated TCB. + * + * The following table lists various combinations of portUSING_MPU_WRAPPERS, + * configSUPPORT_DYNAMIC_ALLOCATION and configSUPPORT_STATIC_ALLOCATION and + * when it is possible to have both static and dynamic allocation: + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + * | MPU | Dynamic | Static | Available Functions | Possible Allocations | Both Dynamic and | Need Free | + * | | | | | | Static Possible | | + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + * | 0 | 0 | 1 | xTaskCreateStatic | TCB - Static, Stack - Static | No | No | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 0 | 1 | 0 | xTaskCreate | TCB - Dynamic, Stack - Dynamic | No | Yes | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 0 | 1 | 1 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateStatic | 2. TCB - Static, Stack - Static | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 0 | 1 | xTaskCreateStatic, | TCB - Static, Stack - Static | No | No | + * | | | | xTaskCreateRestrictedStatic | | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 1 | 0 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateRestricted | 2. TCB - Dynamic, Stack - Static | | | + * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| + * | 1 | 1 | 1 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | + * | | | | xTaskCreateStatic, | 2. TCB - Dynamic, Stack - Static | | | + * | | | | xTaskCreateRestricted, | 3. TCB - Static, Stack - Static | | | + * | | | | xTaskCreateRestrictedStatic | | | | + * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ + */ +#define tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE \ + ( ( ( portUSING_MPU_WRAPPERS == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) || \ + ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) ) + +/* + * In line with software engineering best practice, FreeRTOS implements a strict + * data hiding policy, so the real structures used by FreeRTOS to maintain the + * state of tasks, queues, semaphores, etc. are not accessible to the application + * code. However, if the application writer wants to statically allocate such + * an object then the size of the object needs to be know. Dummy structures + * that are guaranteed to have the same size and alignment requirements of the + * real objects are used for this purpose. The dummy list and list item + * structures below are used for inclusion in such a dummy structure. + */ +struct xSTATIC_LIST_ITEM +{ + #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + TickType_t xDummy2; + void * pvDummy3[ 4 ]; + #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy4; + #endif +}; +typedef struct xSTATIC_LIST_ITEM StaticListItem_t; + +/* See the comments above the struct xSTATIC_LIST_ITEM definition. */ +struct xSTATIC_MINI_LIST_ITEM +{ + #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + TickType_t xDummy2; + void * pvDummy3[ 2 ]; +}; +typedef struct xSTATIC_MINI_LIST_ITEM StaticMiniListItem_t; + +/* See the comments above the struct xSTATIC_LIST_ITEM definition. */ +typedef struct xSTATIC_LIST +{ + #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy1; + #endif + UBaseType_t uxDummy2; + void * pvDummy3; + StaticMiniListItem_t xDummy4; + #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) + TickType_t xDummy5; + #endif +} StaticList_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the Task structure used internally by + * FreeRTOS is not accessible to application code. However, if the application + * writer wants to statically allocate the memory required to create a task then + * the size of the task object needs to be know. The StaticTask_t structure + * below is provided for this purpose. Its sizes and alignment requirements are + * guaranteed to match those of the genuine structure, no matter which + * architecture is being used, and no matter how the values in FreeRTOSConfig.h + * are set. Its contents are somewhat obfuscated in the hope users will + * recognise that it would be unwise to make direct use of the structure members. + */ +typedef struct xSTATIC_TCB +{ + void * pxDummy1; + #if ( portUSING_MPU_WRAPPERS == 1 ) + xMPU_SETTINGS xDummy2; + #endif + StaticListItem_t xDummy3[ 2 ]; + UBaseType_t uxDummy5; + void * pxDummy6; + uint8_t ucDummy7[ configMAX_TASK_NAME_LEN ]; + #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) + void * pxDummy8; + #endif + #if ( portCRITICAL_NESTING_IN_TCB == 1 ) + UBaseType_t uxDummy9; + #endif + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy10[ 2 ]; + #endif + #if ( configUSE_MUTEXES == 1 ) + UBaseType_t uxDummy12[ 2 ]; + #endif + #if ( configUSE_APPLICATION_TASK_TAG == 1 ) + void * pxDummy14; + #endif + #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 ) + void * pvDummy15[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ]; + #endif + #if ( configGENERATE_RUN_TIME_STATS == 1 ) + uint32_t ulDummy16; + #endif + #if ( configUSE_NEWLIB_REENTRANT == 1 ) + struct _reent xDummy17; + #endif + #if ( configUSE_TASK_NOTIFICATIONS == 1 ) + uint32_t ulDummy18[ configTASK_NOTIFICATION_ARRAY_ENTRIES ]; + uint8_t ucDummy19[ configTASK_NOTIFICATION_ARRAY_ENTRIES ]; + #endif + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) + uint8_t uxDummy20; + #endif + + #if ( INCLUDE_xTaskAbortDelay == 1 ) + uint8_t ucDummy21; + #endif + #if ( configUSE_POSIX_ERRNO == 1 ) + int iDummy22; + #endif +} StaticTask_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the Queue structure used internally by + * FreeRTOS is not accessible to application code. However, if the application + * writer wants to statically allocate the memory required to create a queue + * then the size of the queue object needs to be know. The StaticQueue_t + * structure below is provided for this purpose. Its sizes and alignment + * requirements are guaranteed to match those of the genuine structure, no + * matter which architecture is being used, and no matter how the values in + * FreeRTOSConfig.h are set. Its contents are somewhat obfuscated in the hope + * users will recognise that it would be unwise to make direct use of the + * structure members. + */ +typedef struct xSTATIC_QUEUE +{ + void * pvDummy1[ 3 ]; + + union + { + void * pvDummy2; + UBaseType_t uxDummy2; + } u; + + StaticList_t xDummy3[ 2 ]; + UBaseType_t uxDummy4[ 3 ]; + uint16_t ucDummy5[ 2 ]; + + #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucDummy6; + #endif + + #if ( configUSE_QUEUE_SETS == 1 ) + void * pvDummy7; + #endif + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy8; + uint8_t ucDummy9; + #endif +} StaticQueue_t; +typedef StaticQueue_t StaticSemaphore_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the event group structure used + * internally by FreeRTOS is not accessible to application code. However, if + * the application writer wants to statically allocate the memory required to + * create an event group then the size of the event group object needs to be + * know. The StaticEventGroup_t structure below is provided for this purpose. + * Its sizes and alignment requirements are guaranteed to match those of the + * genuine structure, no matter which architecture is being used, and no matter + * how the values in FreeRTOSConfig.h are set. Its contents are somewhat + * obfuscated in the hope users will recognise that it would be unwise to make + * direct use of the structure members. + */ +typedef struct xSTATIC_EVENT_GROUP +{ + TickType_t xDummy1; + StaticList_t xDummy2; + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy3; + #endif + + #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucDummy4; + #endif +} StaticEventGroup_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the software timer structure used + * internally by FreeRTOS is not accessible to application code. However, if + * the application writer wants to statically allocate the memory required to + * create a software timer then the size of the queue object needs to be know. + * The StaticTimer_t structure below is provided for this purpose. Its sizes + * and alignment requirements are guaranteed to match those of the genuine + * structure, no matter which architecture is being used, and no matter how the + * values in FreeRTOSConfig.h are set. Its contents are somewhat obfuscated in + * the hope users will recognise that it would be unwise to make direct use of + * the structure members. + */ +typedef struct xSTATIC_TIMER +{ + void * pvDummy1; + StaticListItem_t xDummy2; + TickType_t xDummy3; + void * pvDummy5; + TaskFunction_t pvDummy6; + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy7; + #endif + uint8_t ucDummy8; +} StaticTimer_t; + +/* + * In line with software engineering best practice, especially when supplying a + * library that is likely to change in future versions, FreeRTOS implements a + * strict data hiding policy. This means the stream buffer structure used + * internally by FreeRTOS is not accessible to application code. However, if + * the application writer wants to statically allocate the memory required to + * create a stream buffer then the size of the stream buffer object needs to be + * know. The StaticStreamBuffer_t structure below is provided for this purpose. + * Its size and alignment requirements are guaranteed to match those of the + * genuine structure, no matter which architecture is being used, and no matter + * how the values in FreeRTOSConfig.h are set. Its contents are somewhat + * obfuscated in the hope users will recognise that it would be unwise to make + * direct use of the structure members. + */ +typedef struct xSTATIC_STREAM_BUFFER +{ + size_t uxDummy1[ 4 ]; + void * pvDummy2[ 3 ]; + uint8_t ucDummy3; + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxDummy4; + #endif +} StaticStreamBuffer_t; + +/* Message buffers are built on stream buffers. */ +typedef StaticStreamBuffer_t StaticMessageBuffer_t; + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* INC_FREERTOS_H */ diff --git a/MODULES/FreeRTOS/inc/StackMacros.h b/MODULES/FreeRTOS/inc/StackMacros.h new file mode 100644 index 0000000..0f37c4d --- /dev/null +++ b/MODULES/FreeRTOS/inc/StackMacros.h @@ -0,0 +1,32 @@ +/* + * FreeRTOS Kernel V10.4.3 LTS Patch 2 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef _MSC_VER /* Visual Studio doesn't support #warning. */ + #warning The name of this file has changed to stack_macros.h. Please update your code accordingly. This source file (which has the original name) will be removed in future released. +#endif + +#include "stack_macros.h" diff --git a/MODULES/FreeRTOS/inc/atomic.h b/MODULES/FreeRTOS/inc/atomic.h new file mode 100644 index 0000000..74abbe0 --- /dev/null +++ b/MODULES/FreeRTOS/inc/atomic.h @@ -0,0 +1,417 @@ +/* + * FreeRTOS Kernel V10.4.3 LTS Patch 2 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/** + * @file atomic.h + * @brief FreeRTOS atomic operation support. + * + * This file implements atomic functions by disabling interrupts globally. + * Implementations with architecture specific atomic instructions can be + * provided under each compiler directory. + */ + +#ifndef ATOMIC_H +#define ATOMIC_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include atomic.h" +#endif + +/* Standard includes. */ +#include + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* + * Port specific definitions -- entering/exiting critical section. + * Refer template -- ./lib/FreeRTOS/portable/Compiler/Arch/portmacro.h + * + * Every call to ATOMIC_EXIT_CRITICAL() must be closely paired with + * ATOMIC_ENTER_CRITICAL(). + * + */ +#if defined( portSET_INTERRUPT_MASK_FROM_ISR ) + +/* Nested interrupt scheme is supported in this port. */ + #define ATOMIC_ENTER_CRITICAL() \ + UBaseType_t uxCriticalSectionType = portSET_INTERRUPT_MASK_FROM_ISR() + + #define ATOMIC_EXIT_CRITICAL() \ + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxCriticalSectionType ) + +#else + +/* Nested interrupt scheme is NOT supported in this port. */ + #define ATOMIC_ENTER_CRITICAL() portENTER_CRITICAL() + #define ATOMIC_EXIT_CRITICAL() portEXIT_CRITICAL() + +#endif /* portSET_INTERRUPT_MASK_FROM_ISR() */ + +/* + * Port specific definition -- "always inline". + * Inline is compiler specific, and may not always get inlined depending on your + * optimization level. Also, inline is considered as performance optimization + * for atomic. Thus, if portFORCE_INLINE is not provided by portmacro.h, + * instead of resulting error, simply define it away. + */ +#ifndef portFORCE_INLINE + #define portFORCE_INLINE +#endif + +#define ATOMIC_COMPARE_AND_SWAP_SUCCESS 0x1U /**< Compare and swap succeeded, swapped. */ +#define ATOMIC_COMPARE_AND_SWAP_FAILURE 0x0U /**< Compare and swap failed, did not swap. */ + +/*----------------------------- Swap && CAS ------------------------------*/ + +/** + * Atomic compare-and-swap + * + * @brief Performs an atomic compare-and-swap operation on the specified values. + * + * @param[in, out] pulDestination Pointer to memory location from where value is + * to be loaded and checked. + * @param[in] ulExchange If condition meets, write this value to memory. + * @param[in] ulComparand Swap condition. + * + * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped. + * + * @note This function only swaps *pulDestination with ulExchange, if previous + * *pulDestination value equals ulComparand. + */ +static portFORCE_INLINE uint32_t Atomic_CompareAndSwap_u32( uint32_t volatile * pulDestination, + uint32_t ulExchange, + uint32_t ulComparand ) +{ + uint32_t ulReturnValue; + + ATOMIC_ENTER_CRITICAL(); + { + if( *pulDestination == ulComparand ) + { + *pulDestination = ulExchange; + ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS; + } + else + { + ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE; + } + } + ATOMIC_EXIT_CRITICAL(); + + return ulReturnValue; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic swap (pointers) + * + * @brief Atomically sets the address pointed to by *ppvDestination to the value + * of *pvExchange. + * + * @param[in, out] ppvDestination Pointer to memory location from where a pointer + * value is to be loaded and written back to. + * @param[in] pvExchange Pointer value to be written to *ppvDestination. + * + * @return The initial value of *ppvDestination. + */ +static portFORCE_INLINE void * Atomic_SwapPointers_p32( void * volatile * ppvDestination, + void * pvExchange ) +{ + void * pReturnValue; + + ATOMIC_ENTER_CRITICAL(); + { + pReturnValue = *ppvDestination; + *ppvDestination = pvExchange; + } + ATOMIC_EXIT_CRITICAL(); + + return pReturnValue; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic compare-and-swap (pointers) + * + * @brief Performs an atomic compare-and-swap operation on the specified pointer + * values. + * + * @param[in, out] ppvDestination Pointer to memory location from where a pointer + * value is to be loaded and checked. + * @param[in] pvExchange If condition meets, write this value to memory. + * @param[in] pvComparand Swap condition. + * + * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped. + * + * @note This function only swaps *ppvDestination with pvExchange, if previous + * *ppvDestination value equals pvComparand. + */ +static portFORCE_INLINE uint32_t Atomic_CompareAndSwapPointers_p32( void * volatile * ppvDestination, + void * pvExchange, + void * pvComparand ) +{ + uint32_t ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE; + + ATOMIC_ENTER_CRITICAL(); + { + if( *ppvDestination == pvComparand ) + { + *ppvDestination = pvExchange; + ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS; + } + } + ATOMIC_EXIT_CRITICAL(); + + return ulReturnValue; +} + + +/*----------------------------- Arithmetic ------------------------------*/ + +/** + * Atomic add + * + * @brief Atomically adds count to the value of the specified pointer points to. + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * @param[in] ulCount Value to be added to *pulAddend. + * + * @return previous *pulAddend value. + */ +static portFORCE_INLINE uint32_t Atomic_Add_u32( uint32_t volatile * pulAddend, + uint32_t ulCount ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend += ulCount; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic subtract + * + * @brief Atomically subtracts count from the value of the specified pointer + * pointers to. + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * @param[in] ulCount Value to be subtract from *pulAddend. + * + * @return previous *pulAddend value. + */ +static portFORCE_INLINE uint32_t Atomic_Subtract_u32( uint32_t volatile * pulAddend, + uint32_t ulCount ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend -= ulCount; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic increment + * + * @brief Atomically increments the value of the specified pointer points to. + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * + * @return *pulAddend value before increment. + */ +static portFORCE_INLINE uint32_t Atomic_Increment_u32( uint32_t volatile * pulAddend ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend += 1; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic decrement + * + * @brief Atomically decrements the value of the specified pointer points to + * + * @param[in,out] pulAddend Pointer to memory location from where value is to be + * loaded and written back to. + * + * @return *pulAddend value before decrement. + */ +static portFORCE_INLINE uint32_t Atomic_Decrement_u32( uint32_t volatile * pulAddend ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulAddend; + *pulAddend -= 1; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} + +/*----------------------------- Bitwise Logical ------------------------------*/ + +/** + * Atomic OR + * + * @brief Performs an atomic OR operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be ORed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_OR_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination |= ulValue; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic AND + * + * @brief Performs an atomic AND operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be ANDed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_AND_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination &= ulValue; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic NAND + * + * @brief Performs an atomic NAND operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be NANDed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_NAND_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination = ~( ulCurrent & ulValue ); + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} +/*-----------------------------------------------------------*/ + +/** + * Atomic XOR + * + * @brief Performs an atomic XOR operation on the specified values. + * + * @param [in, out] pulDestination Pointer to memory location from where value is + * to be loaded and written back to. + * @param [in] ulValue Value to be XORed with *pulDestination. + * + * @return The original value of *pulDestination. + */ +static portFORCE_INLINE uint32_t Atomic_XOR_u32( uint32_t volatile * pulDestination, + uint32_t ulValue ) +{ + uint32_t ulCurrent; + + ATOMIC_ENTER_CRITICAL(); + { + ulCurrent = *pulDestination; + *pulDestination ^= ulValue; + } + ATOMIC_EXIT_CRITICAL(); + + return ulCurrent; +} + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* ATOMIC_H */ diff --git a/MODULES/FreeRTOS/inc/croutine.h b/MODULES/FreeRTOS/inc/croutine.h new file mode 100644 index 0000000..4d30a83 --- /dev/null +++ b/MODULES/FreeRTOS/inc/croutine.h @@ -0,0 +1,751 @@ +/* + * FreeRTOS Kernel V10.4.3 LTS Patch 2 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef CO_ROUTINE_H +#define CO_ROUTINE_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include croutine.h" +#endif + +#include "list.h" + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* Used to hide the implementation of the co-routine control block. The + * control block structure however has to be included in the header due to + * the macro implementation of the co-routine functionality. */ +typedef void * CoRoutineHandle_t; + +/* Defines the prototype to which co-routine functions must conform. */ +typedef void (* crCOROUTINE_CODE)( CoRoutineHandle_t, + UBaseType_t ); + +typedef struct corCoRoutineControlBlock +{ + crCOROUTINE_CODE pxCoRoutineFunction; + ListItem_t xGenericListItem; /*< List item used to place the CRCB in ready and blocked queues. */ + ListItem_t xEventListItem; /*< List item used to place the CRCB in event lists. */ + UBaseType_t uxPriority; /*< The priority of the co-routine in relation to other co-routines. */ + UBaseType_t uxIndex; /*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */ + uint16_t uxState; /*< Used internally by the co-routine implementation. */ +} CRCB_t; /* Co-routine control block. Note must be identical in size down to uxPriority with TCB_t. */ + +/** + * croutine. h + * 
+ * BaseType_t xCoRoutineCreate(
+ *                               crCOROUTINE_CODE pxCoRoutineCode,
+ *                               UBaseType_t uxPriority,
+ *                               UBaseType_t uxIndex
+ *                             ); 
+ *
+ * + * Create a new co-routine and add it to the list of co-routines that are + * ready to run. + * + * @param pxCoRoutineCode Pointer to the co-routine function. Co-routine + * functions require special syntax - see the co-routine section of the WEB + * documentation for more information. + * + * @param uxPriority The priority with respect to other co-routines at which + * the co-routine will run. + * + * @param uxIndex Used to distinguish between different co-routines that + * execute the same function. See the example below and the co-routine section + * of the WEB documentation for further information. + * + * @return pdPASS if the co-routine was successfully created and added to a ready + * list, otherwise an error code defined with ProjDefs.h. + * + * Example usage: + * 
+ * // Co-routine to be created.
+ * void vFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ * // This may not be necessary for const variables.
+ * static const char cLedToFlash[ 2 ] = { 5, 6 };
+ * static const TickType_t uxFlashRates[ 2 ] = { 200, 400 };
+ *
+ *   // Must start every co-routine with a call to crSTART();
+ *   crSTART( xHandle );
+ *
+ *   for( ;; )
+ *   {
+ *       // This co-routine just delays for a fixed period, then toggles
+ *       // an LED.  Two co-routines are created using this function, so
+ *       // the uxIndex parameter is used to tell the co-routine which
+ *       // LED to flash and how int32_t to delay.  This assumes xQueue has
+ *       // already been created.
+ *       vParTestToggleLED( cLedToFlash[ uxIndex ] );
+ *       crDELAY( xHandle, uxFlashRates[ uxIndex ] );
+ *   }
+ *
+ *   // Must end every co-routine with a call to crEND();
+ *   crEND();
+ * }
+ *
+ * // Function that creates two co-routines.
+ * void vOtherFunction( void )
+ * {
+ * uint8_t ucParameterToPass;
+ * TaskHandle_t xHandle;
+ *
+ *   // Create two co-routines at priority 0.  The first is given index 0
+ *   // so (from the code above) toggles LED 5 every 200 ticks.  The second
+ *   // is given index 1 so toggles LED 6 every 400 ticks.
+ *   for( uxIndex = 0; uxIndex < 2; uxIndex++ )
+ *   {
+ *       xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );
+ *   }
+ * }
+ *
+ * \defgroup xCoRoutineCreate xCoRoutineCreate + * \ingroup Tasks + */ +BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, + UBaseType_t uxPriority, + UBaseType_t uxIndex ); + + +/** + * croutine. h + * 
+ * void vCoRoutineSchedule( void );
+ *
+ * + * Run a co-routine. + * + * vCoRoutineSchedule() executes the highest priority co-routine that is able + * to run. The co-routine will execute until it either blocks, yields or is + * preempted by a task. Co-routines execute cooperatively so one + * co-routine cannot be preempted by another, but can be preempted by a task. + * + * If an application comprises of both tasks and co-routines then + * vCoRoutineSchedule should be called from the idle task (in an idle task + * hook). + * + * Example usage: + * 
+ * // This idle task hook will schedule a co-routine each time it is called.
+ * // The rest of the idle task will execute between co-routine calls.
+ * void vApplicationIdleHook( void )
+ * {
+ *  vCoRoutineSchedule();
+ * }
+ *
+ * // Alternatively, if you do not require any other part of the idle task to
+ * // execute, the idle task hook can call vCoRoutineSchedule() within an
+ * // infinite loop.
+ * void vApplicationIdleHook( void )
+ * {
+ *  for( ;; )
+ *  {
+ *      vCoRoutineSchedule();
+ *  }
+ * }
+ *
+ * \defgroup vCoRoutineSchedule vCoRoutineSchedule + * \ingroup Tasks + */ +void vCoRoutineSchedule( void ); + +/** + * croutine. h + * 
+ * crSTART( CoRoutineHandle_t xHandle );
+ *
+ * + * This macro MUST always be called at the start of a co-routine function. + * + * Example usage: + * 
+ * // Co-routine to be created.
+ * void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ * static int32_t ulAVariable;
+ *
+ *   // Must start every co-routine with a call to crSTART();
+ *   crSTART( xHandle );
+ *
+ *   for( ;; )
+ *   {
+ *        // Co-routine functionality goes here.
+ *   }
+ *
+ *   // Must end every co-routine with a call to crEND();
+ *   crEND();
+ * }
+ *
+ * \defgroup crSTART crSTART + * \ingroup Tasks + */ +#define crSTART( pxCRCB ) \ + switch( ( ( CRCB_t * ) ( pxCRCB ) )->uxState ) { \ + case 0: + +/** + * croutine. h + * 
+ * crEND();
+ *
+ * + * This macro MUST always be called at the end of a co-routine function. + * + * Example usage: + * 
+ * // Co-routine to be created.
+ * void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ * static int32_t ulAVariable;
+ *
+ *   // Must start every co-routine with a call to crSTART();
+ *   crSTART( xHandle );
+ *
+ *   for( ;; )
+ *   {
+ *        // Co-routine functionality goes here.
+ *   }
+ *
+ *   // Must end every co-routine with a call to crEND();
+ *   crEND();
+ * }
+ *
+ * \defgroup crSTART crSTART + * \ingroup Tasks + */ +#define crEND() } + +/* + * These macros are intended for internal use by the co-routine implementation + * only. The macros should not be used directly by application writers. + */ +#define crSET_STATE0( xHandle ) \ + ( ( CRCB_t * ) ( xHandle ) )->uxState = ( __LINE__ * 2 ); return; \ + case ( __LINE__ * 2 ): +#define crSET_STATE1( xHandle ) \ + ( ( CRCB_t * ) ( xHandle ) )->uxState = ( ( __LINE__ * 2 ) + 1 ); return; \ + case ( ( __LINE__ * 2 ) + 1 ): + +/** + * croutine. h + * 
+ * crDELAY( CoRoutineHandle_t xHandle, TickType_t xTicksToDelay );
+ *
+ * + * Delay a co-routine for a fixed period of time. + * + * crDELAY can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * @param xHandle The handle of the co-routine to delay. This is the xHandle + * parameter of the co-routine function. + * + * @param xTickToDelay The number of ticks that the co-routine should delay + * for. The actual amount of time this equates to is defined by + * configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant portTICK_PERIOD_MS + * can be used to convert ticks to milliseconds. + * + * Example usage: + * 
+ * // Co-routine to be created.
+ * void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ * // This may not be necessary for const variables.
+ * // We are to delay for 200ms.
+ * static const xTickType xDelayTime = 200 / portTICK_PERIOD_MS;
+ *
+ *   // Must start every co-routine with a call to crSTART();
+ *   crSTART( xHandle );
+ *
+ *   for( ;; )
+ *   {
+ *      // Delay for 200ms.
+ *      crDELAY( xHandle, xDelayTime );
+ *
+ *      // Do something here.
+ *   }
+ *
+ *   // Must end every co-routine with a call to crEND();
+ *   crEND();
+ * }
+ *
+ * \defgroup crDELAY crDELAY + * \ingroup Tasks + */ +#define crDELAY( xHandle, xTicksToDelay ) \ + if( ( xTicksToDelay ) > 0 ) \ + { \ + vCoRoutineAddToDelayedList( ( xTicksToDelay ), NULL ); \ + } \ + crSET_STATE0( ( xHandle ) ); + +/** + * 
+ * crQUEUE_SEND(
+ *                CoRoutineHandle_t xHandle,
+ *                QueueHandle_t pxQueue,
+ *                void *pvItemToQueue,
+ *                TickType_t xTicksToWait,
+ *                BaseType_t *pxResult
+ *           )
+ *
+ * + * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine + * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. + * + * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas + * xQueueSend() and xQueueReceive() can only be used from tasks. + * + * crQUEUE_SEND can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xHandle The handle of the calling co-routine. This is the xHandle + * parameter of the co-routine function. + * + * @param pxQueue The handle of the queue on which the data will be posted. + * The handle is obtained as the return value when the queue is created using + * the xQueueCreate() API function. + * + * @param pvItemToQueue A pointer to the data being posted onto the queue. + * The number of bytes of each queued item is specified when the queue is + * created. This number of bytes is copied from pvItemToQueue into the queue + * itself. + * + * @param xTickToDelay The number of ticks that the co-routine should block + * to wait for space to become available on the queue, should space not be + * available immediately. The actual amount of time this equates to is defined + * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant + * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see example + * below). + * + * @param pxResult The variable pointed to by pxResult will be set to pdPASS if + * data was successfully posted onto the queue, otherwise it will be set to an + * error defined within ProjDefs.h. + * + * Example usage: + * 
+ * // Co-routine function that blocks for a fixed period then posts a number onto
+ * // a queue.
+ * static void prvCoRoutineFlashTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ * static BaseType_t xNumberToPost = 0;
+ * static BaseType_t xResult;
+ *
+ *  // Co-routines must begin with a call to crSTART().
+ *  crSTART( xHandle );
+ *
+ *  for( ;; )
+ *  {
+ *      // This assumes the queue has already been created.
+ *      crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );
+ *
+ *      if( xResult != pdPASS )
+ *      {
+ *          // The message was not posted!
+ *      }
+ *
+ *      // Increment the number to be posted onto the queue.
+ *      xNumberToPost++;
+ *
+ *      // Delay for 100 ticks.
+ *      crDELAY( xHandle, 100 );
+ *  }
+ *
+ *  // Co-routines must end with a call to crEND().
+ *  crEND();
+ * }
+ *
+ * \defgroup crQUEUE_SEND crQUEUE_SEND + * \ingroup Tasks + */ +#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult ) \ + { \ + *( pxResult ) = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), ( xTicksToWait ) ); \ + if( *( pxResult ) == errQUEUE_BLOCKED ) \ + { \ + crSET_STATE0( ( xHandle ) ); \ + *pxResult = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), 0 ); \ + } \ + if( *pxResult == errQUEUE_YIELD ) \ + { \ + crSET_STATE1( ( xHandle ) ); \ + *pxResult = pdPASS; \ + } \ + } + +/** + * croutine. h + * 
+ * crQUEUE_RECEIVE(
+ *                   CoRoutineHandle_t xHandle,
+ *                   QueueHandle_t pxQueue,
+ *                   void *pvBuffer,
+ *                   TickType_t xTicksToWait,
+ *                   BaseType_t *pxResult
+ *               )
+ *
+ * + * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine + * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks. + * + * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas + * xQueueSend() and xQueueReceive() can only be used from tasks. + * + * crQUEUE_RECEIVE can only be called from the co-routine function itself - not + * from within a function called by the co-routine function. This is because + * co-routines do not maintain their own stack. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xHandle The handle of the calling co-routine. This is the xHandle + * parameter of the co-routine function. + * + * @param pxQueue The handle of the queue from which the data will be received. + * The handle is obtained as the return value when the queue is created using + * the xQueueCreate() API function. + * + * @param pvBuffer The buffer into which the received item is to be copied. + * The number of bytes of each queued item is specified when the queue is + * created. This number of bytes is copied into pvBuffer. + * + * @param xTickToDelay The number of ticks that the co-routine should block + * to wait for data to become available from the queue, should data not be + * available immediately. The actual amount of time this equates to is defined + * by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant + * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see the + * crQUEUE_SEND example). + * + * @param pxResult The variable pointed to by pxResult will be set to pdPASS if + * data was successfully retrieved from the queue, otherwise it will be set to + * an error code as defined within ProjDefs.h. + * + * Example usage: + * 
+ * // A co-routine receives the number of an LED to flash from a queue.  It
+ * // blocks on the queue until the number is received.
+ * static void prvCoRoutineFlashWorkTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ * static BaseType_t xResult;
+ * static UBaseType_t uxLEDToFlash;
+ *
+ *  // All co-routines must start with a call to crSTART().
+ *  crSTART( xHandle );
+ *
+ *  for( ;; )
+ *  {
+ *      // Wait for data to become available on the queue.
+ *      crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+ *
+ *      if( xResult == pdPASS )
+ *      {
+ *          // We received the LED to flash - flash it!
+ *          vParTestToggleLED( uxLEDToFlash );
+ *      }
+ *  }
+ *
+ *  crEND();
+ * }
+ *
+ * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE + * \ingroup Tasks + */ +#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult ) \ + { \ + *( pxResult ) = xQueueCRReceive( ( pxQueue ), ( pvBuffer ), ( xTicksToWait ) ); \ + if( *( pxResult ) == errQUEUE_BLOCKED ) \ + { \ + crSET_STATE0( ( xHandle ) ); \ + *( pxResult ) = xQueueCRReceive( ( pxQueue ), ( pvBuffer ), 0 ); \ + } \ + if( *( pxResult ) == errQUEUE_YIELD ) \ + { \ + crSET_STATE1( ( xHandle ) ); \ + *( pxResult ) = pdPASS; \ + } \ + } + +/** + * croutine. h + * 
+ * crQUEUE_SEND_FROM_ISR(
+ *                          QueueHandle_t pxQueue,
+ *                          void *pvItemToQueue,
+ *                          BaseType_t xCoRoutinePreviouslyWoken
+ *                     )
+ *
+ * + * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the + * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() + * functions used by tasks. + * + * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to + * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and + * xQueueReceiveFromISR() can only be used to pass data between a task and and + * ISR. + * + * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue + * that is being used from within a co-routine. + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto + * the same queue multiple times from a single interrupt. The first call + * should always pass in pdFALSE. Subsequent calls should pass in + * the value returned from the previous call. + * + * @return pdTRUE if a co-routine was woken by posting onto the queue. This is + * used by the ISR to determine if a context switch may be required following + * the ISR. + * + * Example usage: + * 
+ * // A co-routine that blocks on a queue waiting for characters to be received.
+ * static void vReceivingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * char cRxedChar;
+ * BaseType_t xResult;
+ *
+ *   // All co-routines must start with a call to crSTART().
+ *   crSTART( xHandle );
+ *
+ *   for( ;; )
+ *   {
+ *       // Wait for data to become available on the queue.  This assumes the
+ *       // queue xCommsRxQueue has already been created!
+ *       crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+ *
+ *       // Was a character received?
+ *       if( xResult == pdPASS )
+ *       {
+ *           // Process the character here.
+ *       }
+ *   }
+ *
+ *   // All co-routines must end with a call to crEND().
+ *   crEND();
+ * }
+ *
+ * // An ISR that uses a queue to send characters received on a serial port to
+ * // a co-routine.
+ * void vUART_ISR( void )
+ * {
+ * char cRxedChar;
+ * BaseType_t xCRWokenByPost = pdFALSE;
+ *
+ *   // We loop around reading characters until there are none left in the UART.
+ *   while( UART_RX_REG_NOT_EMPTY() )
+ *   {
+ *       // Obtain the character from the UART.
+ *       cRxedChar = UART_RX_REG;
+ *
+ *       // Post the character onto a queue.  xCRWokenByPost will be pdFALSE
+ *       // the first time around the loop.  If the post causes a co-routine
+ *       // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.
+ *       // In this manner we can ensure that if more than one co-routine is
+ *       // blocked on the queue only one is woken by this ISR no matter how
+ *       // many characters are posted to the queue.
+ *       xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );
+ *   }
+ * }
+ *
+ * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR + * \ingroup Tasks + */ +#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) \ + xQueueCRSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( xCoRoutinePreviouslyWoken ) ) + + +/** + * croutine. h + * 
+ * crQUEUE_SEND_FROM_ISR(
+ *                          QueueHandle_t pxQueue,
+ *                          void *pvBuffer,
+ *                          BaseType_t * pxCoRoutineWoken
+ *                     )
+ *
+ * + * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the + * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR() + * functions used by tasks. + * + * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to + * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and + * xQueueReceiveFromISR() can only be used to pass data between a task and and + * ISR. + * + * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data + * from a queue that is being used from within a co-routine (a co-routine + * posted to the queue). + * + * See the co-routine section of the WEB documentation for information on + * passing data between tasks and co-routines and between ISR's and + * co-routines. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvBuffer A pointer to a buffer into which the received item will be + * placed. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from the queue into + * pvBuffer. + * + * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become + * available on the queue. If crQUEUE_RECEIVE_FROM_ISR causes such a + * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise + * *pxCoRoutineWoken will remain unchanged. + * + * @return pdTRUE an item was successfully received from the queue, otherwise + * pdFALSE. + * + * Example usage: + * 
+ * // A co-routine that posts a character to a queue then blocks for a fixed
+ * // period.  The character is incremented each time.
+ * static void vSendingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * // cChar holds its value while this co-routine is blocked and must therefore
+ * // be declared static.
+ * static char cCharToTx = 'a';
+ * BaseType_t xResult;
+ *
+ *   // All co-routines must start with a call to crSTART().
+ *   crSTART( xHandle );
+ *
+ *   for( ;; )
+ *   {
+ *       // Send the next character to the queue.
+ *       crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );
+ *
+ *       if( xResult == pdPASS )
+ *       {
+ *           // The character was successfully posted to the queue.
+ *       }
+ *       else
+ *       {
+ *          // Could not post the character to the queue.
+ *       }
+ *
+ *       // Enable the UART Tx interrupt to cause an interrupt in this
+ *       // hypothetical UART.  The interrupt will obtain the character
+ *       // from the queue and send it.
+ *       ENABLE_RX_INTERRUPT();
+ *
+ *       // Increment to the next character then block for a fixed period.
+ *       // cCharToTx will maintain its value across the delay as it is
+ *       // declared static.
+ *       cCharToTx++;
+ *       if( cCharToTx > 'x' )
+ *       {
+ *          cCharToTx = 'a';
+ *       }
+ *       crDELAY( 100 );
+ *   }
+ *
+ *   // All co-routines must end with a call to crEND().
+ *   crEND();
+ * }
+ *
+ * // An ISR that uses a queue to receive characters to send on a UART.
+ * void vUART_ISR( void )
+ * {
+ * char cCharToTx;
+ * BaseType_t xCRWokenByPost = pdFALSE;
+ *
+ *   while( UART_TX_REG_EMPTY() )
+ *   {
+ *       // Are there any characters in the queue waiting to be sent?
+ *       // xCRWokenByPost will automatically be set to pdTRUE if a co-routine
+ *       // is woken by the post - ensuring that only a single co-routine is
+ *       // woken no matter how many times we go around this loop.
+ *       if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )
+ *       {
+ *           SEND_CHARACTER( cCharToTx );
+ *       }
+ *   }
+ * }
+ *
+ * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR + * \ingroup Tasks + */ +#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) \ + xQueueCRReceiveFromISR( ( pxQueue ), ( pvBuffer ), ( pxCoRoutineWoken ) ) + +/* + * This function is intended for internal use by the co-routine macros only. + * The macro nature of the co-routine implementation requires that the + * prototype appears here. The function should not be used by application + * writers. + * + * Removes the current co-routine from its ready list and places it in the + * appropriate delayed list. + */ +void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, + List_t * pxEventList ); + +/* + * This function is intended for internal use by the queue implementation only. + * The function should not be used by application writers. + * + * Removes the highest priority co-routine from the event list and places it in + * the pending ready list. + */ +BaseType_t xCoRoutineRemoveFromEventList( const List_t * pxEventList ); + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* CO_ROUTINE_H */ diff --git a/MODULES/FreeRTOS/inc/deprecated_definitions.h b/MODULES/FreeRTOS/inc/deprecated_definitions.h new file mode 100644 index 0000000..6adc5d0 --- /dev/null +++ b/MODULES/FreeRTOS/inc/deprecated_definitions.h @@ -0,0 +1,279 @@ +/* + * FreeRTOS Kernel V10.4.3 LTS Patch 2 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef DEPRECATED_DEFINITIONS_H +#define DEPRECATED_DEFINITIONS_H + + +/* Each FreeRTOS port has a unique portmacro.h header file. Originally a + * pre-processor definition was used to ensure the pre-processor found the correct + * portmacro.h file for the port being used. That scheme was deprecated in favour + * of setting the compiler's include path such that it found the correct + * portmacro.h file - removing the need for the constant and allowing the + * portmacro.h file to be located anywhere in relation to the port being used. The + * definitions below remain in the code for backward compatibility only. New + * projects should not use them. */ + +#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT + #include "..\..\Source\portable\owatcom\16bitdos\pc\portmacro.h" + typedef void ( __interrupt __far * pxISR )(); +#endif + +#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT + #include "..\..\Source\portable\owatcom\16bitdos\flsh186\portmacro.h" + typedef void ( __interrupt __far * pxISR )(); +#endif + +#ifdef GCC_MEGA_AVR + #include "../portable/GCC/ATMega323/portmacro.h" +#endif + +#ifdef IAR_MEGA_AVR + #include "../portable/IAR/ATMega323/portmacro.h" +#endif + +#ifdef MPLAB_PIC24_PORT + #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h" +#endif + +#ifdef MPLAB_DSPIC_PORT + #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h" +#endif + +#ifdef MPLAB_PIC18F_PORT + #include "../../Source/portable/MPLAB/PIC18F/portmacro.h" +#endif + +#ifdef MPLAB_PIC32MX_PORT + #include "../../Source/portable/MPLAB/PIC32MX/portmacro.h" +#endif + +#ifdef _FEDPICC + #include "libFreeRTOS/Include/portmacro.h" +#endif + +#ifdef SDCC_CYGNAL + #include "../../Source/portable/SDCC/Cygnal/portmacro.h" +#endif + +#ifdef GCC_ARM7 + #include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h" +#endif + +#ifdef GCC_ARM7_ECLIPSE + #include "portmacro.h" +#endif + +#ifdef ROWLEY_LPC23xx + #include "../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h" +#endif + +#ifdef IAR_MSP430 + #include "..\..\Source\portable\IAR\MSP430\portmacro.h" +#endif + +#ifdef GCC_MSP430 + #include "../../Source/portable/GCC/MSP430F449/portmacro.h" +#endif + +#ifdef ROWLEY_MSP430 + #include "../../Source/portable/Rowley/MSP430F449/portmacro.h" +#endif + +#ifdef ARM7_LPC21xx_KEIL_RVDS + #include "..\..\Source\portable\RVDS\ARM7_LPC21xx\portmacro.h" +#endif + +#ifdef SAM7_GCC + #include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h" +#endif + +#ifdef SAM7_IAR + #include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h" +#endif + +#ifdef SAM9XE_IAR + #include "..\..\Source\portable\IAR\AtmelSAM9XE\portmacro.h" +#endif + +#ifdef LPC2000_IAR + #include "..\..\Source\portable\IAR\LPC2000\portmacro.h" +#endif + +#ifdef STR71X_IAR + #include "..\..\Source\portable\IAR\STR71x\portmacro.h" +#endif + +#ifdef STR75X_IAR + #include "..\..\Source\portable\IAR\STR75x\portmacro.h" +#endif + +#ifdef STR75X_GCC + #include "..\..\Source\portable\GCC\STR75x\portmacro.h" +#endif + +#ifdef STR91X_IAR + #include "..\..\Source\portable\IAR\STR91x\portmacro.h" +#endif + +#ifdef GCC_H8S + #include "../../Source/portable/GCC/H8S2329/portmacro.h" +#endif + +#ifdef GCC_AT91FR40008 + #include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h" +#endif + +#ifdef RVDS_ARMCM3_LM3S102 + #include "../../Source/portable/RVDS/ARM_CM3/portmacro.h" +#endif + +#ifdef GCC_ARMCM3_LM3S102 + #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" +#endif + +#ifdef GCC_ARMCM3 + #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" +#endif + +#ifdef IAR_ARM_CM3 + #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" +#endif + +#ifdef IAR_ARMCM3_LM + #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" +#endif + +#ifdef HCS12_CODE_WARRIOR + #include "../../Source/portable/CodeWarrior/HCS12/portmacro.h" +#endif + +#ifdef MICROBLAZE_GCC + #include "../../Source/portable/GCC/MicroBlaze/portmacro.h" +#endif + +#ifdef TERN_EE + #include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h" +#endif + +#ifdef GCC_HCS12 + #include "../../Source/portable/GCC/HCS12/portmacro.h" +#endif + +#ifdef GCC_MCF5235 + #include "../../Source/portable/GCC/MCF5235/portmacro.h" +#endif + +#ifdef COLDFIRE_V2_GCC + #include "../../../Source/portable/GCC/ColdFire_V2/portmacro.h" +#endif + +#ifdef COLDFIRE_V2_CODEWARRIOR + #include "../../Source/portable/CodeWarrior/ColdFire_V2/portmacro.h" +#endif + +#ifdef GCC_PPC405 + #include "../../Source/portable/GCC/PPC405_Xilinx/portmacro.h" +#endif + +#ifdef GCC_PPC440 + #include "../../Source/portable/GCC/PPC440_Xilinx/portmacro.h" +#endif + +#ifdef _16FX_SOFTUNE + #include "..\..\Source\portable\Softune\MB96340\portmacro.h" +#endif + +#ifdef BCC_INDUSTRIAL_PC_PORT + +/* A short file name has to be used in place of the normal + * FreeRTOSConfig.h when using the Borland compiler. */ + #include "frconfig.h" + #include "..\portable\BCC\16BitDOS\PC\prtmacro.h" + typedef void ( __interrupt __far * pxISR )(); +#endif + +#ifdef BCC_FLASH_LITE_186_PORT + +/* A short file name has to be used in place of the normal + * FreeRTOSConfig.h when using the Borland compiler. */ + #include "frconfig.h" + #include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h" + typedef void ( __interrupt __far * pxISR )(); +#endif + +#ifdef __GNUC__ + #ifdef __AVR32_AVR32A__ + #include "portmacro.h" + #endif +#endif + +#ifdef __ICCAVR32__ + #ifdef __CORE__ + #if __CORE__ == __AVR32A__ + #include "portmacro.h" + #endif + #endif +#endif + +#ifdef __91467D + #include "portmacro.h" +#endif + +#ifdef __96340 + #include "portmacro.h" +#endif + + +#ifdef __IAR_V850ES_Fx3__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx3__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx3_L__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Jx2__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_V850ES_Hx2__ + #include "../../Source/portable/IAR/V850ES/portmacro.h" +#endif + +#ifdef __IAR_78K0R_Kx3__ + #include "../../Source/portable/IAR/78K0R/portmacro.h" +#endif + +#ifdef __IAR_78K0R_Kx3L__ + #include "../../Source/portable/IAR/78K0R/portmacro.h" +#endif + +#endif /* DEPRECATED_DEFINITIONS_H */ diff --git a/MODULES/FreeRTOS/inc/event_groups.h b/MODULES/FreeRTOS/inc/event_groups.h new file mode 100644 index 0000000..036ef8e --- /dev/null +++ b/MODULES/FreeRTOS/inc/event_groups.h @@ -0,0 +1,775 @@ +/* + * FreeRTOS Kernel V10.4.3 LTS Patch 2 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef EVENT_GROUPS_H +#define EVENT_GROUPS_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h" must appear in source files before "include event_groups.h" +#endif + +/* FreeRTOS includes. */ +#include "timers.h" + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/** + * An event group is a collection of bits to which an application can assign a + * meaning. For example, an application may create an event group to convey + * the status of various CAN bus related events in which bit 0 might mean "A CAN + * message has been received and is ready for processing", bit 1 might mean "The + * application has queued a message that is ready for sending onto the CAN + * network", and bit 2 might mean "It is time to send a SYNC message onto the + * CAN network" etc. A task can then test the bit values to see which events + * are active, and optionally enter the Blocked state to wait for a specified + * bit or a group of specified bits to be active. To continue the CAN bus + * example, a CAN controlling task can enter the Blocked state (and therefore + * not consume any processing time) until either bit 0, bit 1 or bit 2 are + * active, at which time the bit that was actually active would inform the task + * which action it had to take (process a received message, send a message, or + * send a SYNC). + * + * The event groups implementation contains intelligence to avoid race + * conditions that would otherwise occur were an application to use a simple + * variable for the same purpose. This is particularly important with respect + * to when a bit within an event group is to be cleared, and when bits have to + * be set and then tested atomically - as is the case where event groups are + * used to create a synchronisation point between multiple tasks (a + * 'rendezvous'). + * + * \defgroup EventGroup + */ + + + +/** + * event_groups.h + * + * Type by which event groups are referenced. For example, a call to + * xEventGroupCreate() returns an EventGroupHandle_t variable that can then + * be used as a parameter to other event group functions. + * + * \defgroup EventGroupHandle_t EventGroupHandle_t + * \ingroup EventGroup + */ +struct EventGroupDef_t; +typedef struct EventGroupDef_t * EventGroupHandle_t; + +/* + * The type that holds event bits always matches TickType_t - therefore the + * number of bits it holds is set by configUSE_16_BIT_TICKS (16 bits if set to 1, + * 32 bits if set to 0. + * + * \defgroup EventBits_t EventBits_t + * \ingroup EventGroup + */ +typedef TickType_t EventBits_t; + +/** + * event_groups.h + * 
+ * EventGroupHandle_t xEventGroupCreate( void );
+ *
+ * + * Create a new event group. + * + * Internally, within the FreeRTOS implementation, event groups use a [small] + * block of memory, in which the event group's structure is stored. If an event + * groups is created using xEventGropuCreate() then the required memory is + * automatically dynamically allocated inside the xEventGroupCreate() function. + * (see https://www.FreeRTOS.org/a00111.html). If an event group is created + * using xEventGropuCreateStatic() then the application writer must instead + * provide the memory that will get used by the event group. + * xEventGroupCreateStatic() therefore allows an event group to be created + * without using any dynamic memory allocation. + * + * Although event groups are not related to ticks, for internal implementation + * reasons the number of bits available for use in an event group is dependent + * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h. If + * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit + * 0 to bit 7). If configUSE_16_BIT_TICKS is set to 0 then each event group has + * 24 usable bits (bit 0 to bit 23). The EventBits_t type is used to store + * event bits within an event group. + * + * @return If the event group was created then a handle to the event group is + * returned. If there was insufficient FreeRTOS heap available to create the + * event group then NULL is returned. See https://www.FreeRTOS.org/a00111.html + * + * Example usage: + * 
+ *  // Declare a variable to hold the created event group.
+ *  EventGroupHandle_t xCreatedEventGroup;
+ *
+ *  // Attempt to create the event group.
+ *  xCreatedEventGroup = xEventGroupCreate();
+ *
+ *  // Was the event group created successfully?
+ *  if( xCreatedEventGroup == NULL )
+ *  {
+ *      // The event group was not created because there was insufficient
+ *      // FreeRTOS heap available.
+ *  }
+ *  else
+ *  {
+ *      // The event group was created.
+ *  }
+ *
+ * \defgroup xEventGroupCreate xEventGroupCreate + * \ingroup EventGroup + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + EventGroupHandle_t xEventGroupCreate( void ) PRIVILEGED_FUNCTION; +#endif + +/** + * event_groups.h + * 
+ * EventGroupHandle_t xEventGroupCreateStatic( EventGroupHandle_t * pxEventGroupBuffer );
+ *
+ * + * Create a new event group. + * + * Internally, within the FreeRTOS implementation, event groups use a [small] + * block of memory, in which the event group's structure is stored. If an event + * groups is created using xEventGropuCreate() then the required memory is + * automatically dynamically allocated inside the xEventGroupCreate() function. + * (see https://www.FreeRTOS.org/a00111.html). If an event group is created + * using xEventGropuCreateStatic() then the application writer must instead + * provide the memory that will get used by the event group. + * xEventGroupCreateStatic() therefore allows an event group to be created + * without using any dynamic memory allocation. + * + * Although event groups are not related to ticks, for internal implementation + * reasons the number of bits available for use in an event group is dependent + * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h. If + * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit + * 0 to bit 7). If configUSE_16_BIT_TICKS is set to 0 then each event group has + * 24 usable bits (bit 0 to bit 23). The EventBits_t type is used to store + * event bits within an event group. + * + * @param pxEventGroupBuffer pxEventGroupBuffer must point to a variable of type + * StaticEventGroup_t, which will be then be used to hold the event group's data + * structures, removing the need for the memory to be allocated dynamically. + * + * @return If the event group was created then a handle to the event group is + * returned. If pxEventGroupBuffer was NULL then NULL is returned. + * + * Example usage: + * 
+ *  // StaticEventGroup_t is a publicly accessible structure that has the same
+ *  // size and alignment requirements as the real event group structure.  It is
+ *  // provided as a mechanism for applications to know the size of the event
+ *  // group (which is dependent on the architecture and configuration file
+ *  // settings) without breaking the strict data hiding policy by exposing the
+ *  // real event group internals.  This StaticEventGroup_t variable is passed
+ *  // into the xSemaphoreCreateEventGroupStatic() function and is used to store
+ *  // the event group's data structures
+ *  StaticEventGroup_t xEventGroupBuffer;
+ *
+ *  // Create the event group without dynamically allocating any memory.
+ *  xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer );
+ *
+ */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) PRIVILEGED_FUNCTION; +#endif + +/** + * event_groups.h + * 
+ *  EventBits_t xEventGroupWaitBits(    EventGroupHandle_t xEventGroup,
+ *                                      const EventBits_t uxBitsToWaitFor,
+ *                                      const BaseType_t xClearOnExit,
+ *                                      const BaseType_t xWaitForAllBits,
+ *                                      const TickType_t xTicksToWait );
+ *
+ * + * [Potentially] block to wait for one or more bits to be set within a + * previously created event group. + * + * This function cannot be called from an interrupt. + * + * @param xEventGroup The event group in which the bits are being tested. The + * event group must have previously been created using a call to + * xEventGroupCreate(). + * + * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test + * inside the event group. For example, to wait for bit 0 and/or bit 2 set + * uxBitsToWaitFor to 0x05. To wait for bits 0 and/or bit 1 and/or bit 2 set + * uxBitsToWaitFor to 0x07. Etc. + * + * @param xClearOnExit If xClearOnExit is set to pdTRUE then any bits within + * uxBitsToWaitFor that are set within the event group will be cleared before + * xEventGroupWaitBits() returns if the wait condition was met (if the function + * returns for a reason other than a timeout). If xClearOnExit is set to + * pdFALSE then the bits set in the event group are not altered when the call to + * xEventGroupWaitBits() returns. + * + * @param xWaitForAllBits If xWaitForAllBits is set to pdTRUE then + * xEventGroupWaitBits() will return when either all the bits in uxBitsToWaitFor + * are set or the specified block time expires. If xWaitForAllBits is set to + * pdFALSE then xEventGroupWaitBits() will return when any one of the bits set + * in uxBitsToWaitFor is set or the specified block time expires. The block + * time is specified by the xTicksToWait parameter. + * + * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait + * for one/all (depending on the xWaitForAllBits value) of the bits specified by + * uxBitsToWaitFor to become set. + * + * @return The value of the event group at the time either the bits being waited + * for became set, or the block time expired. Test the return value to know + * which bits were set. If xEventGroupWaitBits() returned because its timeout + * expired then not all the bits being waited for will be set. If + * xEventGroupWaitBits() returned because the bits it was waiting for were set + * then the returned value is the event group value before any bits were + * automatically cleared in the case that xClearOnExit parameter was set to + * pdTRUE. + * + * Example usage: + * 
+ #define BIT_0 ( 1 << 0 )
+ #define BIT_4 ( 1 << 4 )
+ *
+ * void aFunction( EventGroupHandle_t xEventGroup )
+ * {
+ * EventBits_t uxBits;
+ * const TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+ *
+ *      // Wait a maximum of 100ms for either bit 0 or bit 4 to be set within
+ *      // the event group.  Clear the bits before exiting.
+ *      uxBits = xEventGroupWaitBits(
+ *                  xEventGroup,    // The event group being tested.
+ *                  BIT_0 | BIT_4,  // The bits within the event group to wait for.
+ *                  pdTRUE,         // BIT_0 and BIT_4 should be cleared before returning.
+ *                  pdFALSE,        // Don't wait for both bits, either bit will do.
+ *                  xTicksToWait ); // Wait a maximum of 100ms for either bit to be set.
+ *
+ *      if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+ *      {
+ *          // xEventGroupWaitBits() returned because both bits were set.
+ *      }
+ *      else if( ( uxBits & BIT_0 ) != 0 )
+ *      {
+ *          // xEventGroupWaitBits() returned because just BIT_0 was set.
+ *      }
+ *      else if( ( uxBits & BIT_4 ) != 0 )
+ *      {
+ *          // xEventGroupWaitBits() returned because just BIT_4 was set.
+ *      }
+ *      else
+ *      {
+ *          // xEventGroupWaitBits() returned because xTicksToWait ticks passed
+ *          // without either BIT_0 or BIT_4 becoming set.
+ *      }
+ * }
+ *
+ * \defgroup xEventGroupWaitBits xEventGroupWaitBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToWaitFor, + const BaseType_t xClearOnExit, + const BaseType_t xWaitForAllBits, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + * 
+ *  EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );
+ *
+ * + * Clear bits within an event group. This function cannot be called from an + * interrupt. + * + * @param xEventGroup The event group in which the bits are to be cleared. + * + * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear + * in the event group. For example, to clear bit 3 only, set uxBitsToClear to + * 0x08. To clear bit 3 and bit 0 set uxBitsToClear to 0x09. + * + * @return The value of the event group before the specified bits were cleared. + * + * Example usage: + * 
+ #define BIT_0 ( 1 << 0 )
+ #define BIT_4 ( 1 << 4 )
+ *
+ * void aFunction( EventGroupHandle_t xEventGroup )
+ * {
+ * EventBits_t uxBits;
+ *
+ *      // Clear bit 0 and bit 4 in xEventGroup.
+ *      uxBits = xEventGroupClearBits(
+ *                              xEventGroup,    // The event group being updated.
+ *                              BIT_0 | BIT_4 );// The bits being cleared.
+ *
+ *      if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+ *      {
+ *          // Both bit 0 and bit 4 were set before xEventGroupClearBits() was
+ *          // called.  Both will now be clear (not set).
+ *      }
+ *      else if( ( uxBits & BIT_0 ) != 0 )
+ *      {
+ *          // Bit 0 was set before xEventGroupClearBits() was called.  It will
+ *          // now be clear.
+ *      }
+ *      else if( ( uxBits & BIT_4 ) != 0 )
+ *      {
+ *          // Bit 4 was set before xEventGroupClearBits() was called.  It will
+ *          // now be clear.
+ *      }
+ *      else
+ *      {
+ *          // Neither bit 0 nor bit 4 were set in the first place.
+ *      }
+ * }
+ *
+ * \defgroup xEventGroupClearBits xEventGroupClearBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + * 
+ *  BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+ *
+ * + * A version of xEventGroupClearBits() that can be called from an interrupt. + * + * Setting bits in an event group is not a deterministic operation because there + * are an unknown number of tasks that may be waiting for the bit or bits being + * set. FreeRTOS does not allow nondeterministic operations to be performed + * while interrupts are disabled, so protects event groups that are accessed + * from tasks by suspending the scheduler rather than disabling interrupts. As + * a result event groups cannot be accessed directly from an interrupt service + * routine. Therefore xEventGroupClearBitsFromISR() sends a message to the + * timer task to have the clear operation performed in the context of the timer + * task. + * + * @param xEventGroup The event group in which the bits are to be cleared. + * + * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear. + * For example, to clear bit 3 only, set uxBitsToClear to 0x08. To clear bit 3 + * and bit 0 set uxBitsToClear to 0x09. + * + * @return If the request to execute the function was posted successfully then + * pdPASS is returned, otherwise pdFALSE is returned. pdFALSE will be returned + * if the timer service queue was full. + * + * Example usage: + * 
+ #define BIT_0 ( 1 << 0 )
+ #define BIT_4 ( 1 << 4 )
+ *
+ * // An event group which it is assumed has already been created by a call to
+ * // xEventGroupCreate().
+ * EventGroupHandle_t xEventGroup;
+ *
+ * void anInterruptHandler( void )
+ * {
+ *      // Clear bit 0 and bit 4 in xEventGroup.
+ *      xResult = xEventGroupClearBitsFromISR(
+ *                          xEventGroup,     // The event group being updated.
+ *                          BIT_0 | BIT_4 ); // The bits being set.
+ *
+ *      if( xResult == pdPASS )
+ *      {
+ *          // The message was posted successfully.
+ *      }
+ * }
+ *
+ * \defgroup xEventGroupClearBitsFromISR xEventGroupClearBitsFromISR + * \ingroup EventGroup + */ +#if ( configUSE_TRACE_FACILITY == 1 ) + BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION; +#else + #define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) \ + xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ) +#endif + +/** + * event_groups.h + * 
+ *  EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+ *
+ * + * Set bits within an event group. + * This function cannot be called from an interrupt. xEventGroupSetBitsFromISR() + * is a version that can be called from an interrupt. + * + * Setting bits in an event group will automatically unblock tasks that are + * blocked waiting for the bits. + * + * @param xEventGroup The event group in which the bits are to be set. + * + * @param uxBitsToSet A bitwise value that indicates the bit or bits to set. + * For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3 + * and bit 0 set uxBitsToSet to 0x09. + * + * @return The value of the event group at the time the call to + * xEventGroupSetBits() returns. There are two reasons why the returned value + * might have the bits specified by the uxBitsToSet parameter cleared. First, + * if setting a bit results in a task that was waiting for the bit leaving the + * blocked state then it is possible the bit will be cleared automatically + * (see the xClearBitOnExit parameter of xEventGroupWaitBits()). Second, any + * unblocked (or otherwise Ready state) task that has a priority above that of + * the task that called xEventGroupSetBits() will execute and may change the + * event group value before the call to xEventGroupSetBits() returns. + * + * Example usage: + * 
+ #define BIT_0 ( 1 << 0 )
+ #define BIT_4 ( 1 << 4 )
+ *
+ * void aFunction( EventGroupHandle_t xEventGroup )
+ * {
+ * EventBits_t uxBits;
+ *
+ *      // Set bit 0 and bit 4 in xEventGroup.
+ *      uxBits = xEventGroupSetBits(
+ *                          xEventGroup,    // The event group being updated.
+ *                          BIT_0 | BIT_4 );// The bits being set.
+ *
+ *      if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+ *      {
+ *          // Both bit 0 and bit 4 remained set when the function returned.
+ *      }
+ *      else if( ( uxBits & BIT_0 ) != 0 )
+ *      {
+ *          // Bit 0 remained set when the function returned, but bit 4 was
+ *          // cleared.  It might be that bit 4 was cleared automatically as a
+ *          // task that was waiting for bit 4 was removed from the Blocked
+ *          // state.
+ *      }
+ *      else if( ( uxBits & BIT_4 ) != 0 )
+ *      {
+ *          // Bit 4 remained set when the function returned, but bit 0 was
+ *          // cleared.  It might be that bit 0 was cleared automatically as a
+ *          // task that was waiting for bit 0 was removed from the Blocked
+ *          // state.
+ *      }
+ *      else
+ *      {
+ *          // Neither bit 0 nor bit 4 remained set.  It might be that a task
+ *          // was waiting for both of the bits to be set, and the bits were
+ *          // cleared as the task left the Blocked state.
+ *      }
+ * }
+ *
+ * \defgroup xEventGroupSetBits xEventGroupSetBits + * \ingroup EventGroup + */ +EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + * 
+ *  BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * + * A version of xEventGroupSetBits() that can be called from an interrupt. + * + * Setting bits in an event group is not a deterministic operation because there + * are an unknown number of tasks that may be waiting for the bit or bits being + * set. FreeRTOS does not allow nondeterministic operations to be performed in + * interrupts or from critical sections. Therefore xEventGroupSetBitsFromISR() + * sends a message to the timer task to have the set operation performed in the + * context of the timer task - where a scheduler lock is used in place of a + * critical section. + * + * @param xEventGroup The event group in which the bits are to be set. + * + * @param uxBitsToSet A bitwise value that indicates the bit or bits to set. + * For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3 + * and bit 0 set uxBitsToSet to 0x09. + * + * @param pxHigherPriorityTaskWoken As mentioned above, calling this function + * will result in a message being sent to the timer daemon task. If the + * priority of the timer daemon task is higher than the priority of the + * currently running task (the task the interrupt interrupted) then + * *pxHigherPriorityTaskWoken will be set to pdTRUE by + * xEventGroupSetBitsFromISR(), indicating that a context switch should be + * requested before the interrupt exits. For that reason + * *pxHigherPriorityTaskWoken must be initialised to pdFALSE. See the + * example code below. + * + * @return If the request to execute the function was posted successfully then + * pdPASS is returned, otherwise pdFALSE is returned. pdFALSE will be returned + * if the timer service queue was full. + * + * Example usage: + * 
+ #define BIT_0 ( 1 << 0 )
+ #define BIT_4 ( 1 << 4 )
+ *
+ * // An event group which it is assumed has already been created by a call to
+ * // xEventGroupCreate().
+ * EventGroupHandle_t xEventGroup;
+ *
+ * void anInterruptHandler( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken, xResult;
+ *
+ *      // xHigherPriorityTaskWoken must be initialised to pdFALSE.
+ *      xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *      // Set bit 0 and bit 4 in xEventGroup.
+ *      xResult = xEventGroupSetBitsFromISR(
+ *                          xEventGroup,    // The event group being updated.
+ *                          BIT_0 | BIT_4   // The bits being set.
+ *                          &xHigherPriorityTaskWoken );
+ *
+ *      // Was the message posted successfully?
+ *      if( xResult == pdPASS )
+ *      {
+ *          // If xHigherPriorityTaskWoken is now set to pdTRUE then a context
+ *          // switch should be requested.  The macro used is port specific and
+ *          // will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
+ *          // refer to the documentation page for the port being used.
+ *          portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ *      }
+ * }
+ *
+ * \defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR + * \ingroup EventGroup + */ +#if ( configUSE_TRACE_FACILITY == 1 ) + BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; +#else + #define xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) \ + xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ) +#endif + +/** + * event_groups.h + * 
+ *  EventBits_t xEventGroupSync(    EventGroupHandle_t xEventGroup,
+ *                                  const EventBits_t uxBitsToSet,
+ *                                  const EventBits_t uxBitsToWaitFor,
+ *                                  TickType_t xTicksToWait );
+ *
+ * + * Atomically set bits within an event group, then wait for a combination of + * bits to be set within the same event group. This functionality is typically + * used to synchronise multiple tasks, where each task has to wait for the other + * tasks to reach a synchronisation point before proceeding. + * + * This function cannot be used from an interrupt. + * + * The function will return before its block time expires if the bits specified + * by the uxBitsToWait parameter are set, or become set within that time. In + * this case all the bits specified by uxBitsToWait will be automatically + * cleared before the function returns. + * + * @param xEventGroup The event group in which the bits are being tested. The + * event group must have previously been created using a call to + * xEventGroupCreate(). + * + * @param uxBitsToSet The bits to set in the event group before determining + * if, and possibly waiting for, all the bits specified by the uxBitsToWait + * parameter are set. + * + * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test + * inside the event group. For example, to wait for bit 0 and bit 2 set + * uxBitsToWaitFor to 0x05. To wait for bits 0 and bit 1 and bit 2 set + * uxBitsToWaitFor to 0x07. Etc. + * + * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait + * for all of the bits specified by uxBitsToWaitFor to become set. + * + * @return The value of the event group at the time either the bits being waited + * for became set, or the block time expired. Test the return value to know + * which bits were set. If xEventGroupSync() returned because its timeout + * expired then not all the bits being waited for will be set. If + * xEventGroupSync() returned because all the bits it was waiting for were + * set then the returned value is the event group value before any bits were + * automatically cleared. + * + * Example usage: + * 
+ * // Bits used by the three tasks.
+ #define TASK_0_BIT     ( 1 << 0 )
+ #define TASK_1_BIT     ( 1 << 1 )
+ #define TASK_2_BIT     ( 1 << 2 )
+ *
+ #define ALL_SYNC_BITS ( TASK_0_BIT | TASK_1_BIT | TASK_2_BIT )
+ *
+ * // Use an event group to synchronise three tasks.  It is assumed this event
+ * // group has already been created elsewhere.
+ * EventGroupHandle_t xEventBits;
+ *
+ * void vTask0( void *pvParameters )
+ * {
+ * EventBits_t uxReturn;
+ * TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+ *
+ *   for( ;; )
+ *   {
+ *      // Perform task functionality here.
+ *
+ *      // Set bit 0 in the event flag to note this task has reached the
+ *      // sync point.  The other two tasks will set the other two bits defined
+ *      // by ALL_SYNC_BITS.  All three tasks have reached the synchronisation
+ *      // point when all the ALL_SYNC_BITS are set.  Wait a maximum of 100ms
+ *      // for this to happen.
+ *      uxReturn = xEventGroupSync( xEventBits, TASK_0_BIT, ALL_SYNC_BITS, xTicksToWait );
+ *
+ *      if( ( uxReturn & ALL_SYNC_BITS ) == ALL_SYNC_BITS )
+ *      {
+ *          // All three tasks reached the synchronisation point before the call
+ *          // to xEventGroupSync() timed out.
+ *      }
+ *  }
+ * }
+ *
+ * void vTask1( void *pvParameters )
+ * {
+ *   for( ;; )
+ *   {
+ *      // Perform task functionality here.
+ *
+ *      // Set bit 1 in the event flag to note this task has reached the
+ *      // synchronisation point.  The other two tasks will set the other two
+ *      // bits defined by ALL_SYNC_BITS.  All three tasks have reached the
+ *      // synchronisation point when all the ALL_SYNC_BITS are set.  Wait
+ *      // indefinitely for this to happen.
+ *      xEventGroupSync( xEventBits, TASK_1_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+ *
+ *      // xEventGroupSync() was called with an indefinite block time, so
+ *      // this task will only reach here if the synchronisation was made by all
+ *      // three tasks, so there is no need to test the return value.
+ *   }
+ * }
+ *
+ * void vTask2( void *pvParameters )
+ * {
+ *   for( ;; )
+ *   {
+ *      // Perform task functionality here.
+ *
+ *      // Set bit 2 in the event flag to note this task has reached the
+ *      // synchronisation point.  The other two tasks will set the other two
+ *      // bits defined by ALL_SYNC_BITS.  All three tasks have reached the
+ *      // synchronisation point when all the ALL_SYNC_BITS are set.  Wait
+ *      // indefinitely for this to happen.
+ *      xEventGroupSync( xEventBits, TASK_2_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+ *
+ *      // xEventGroupSync() was called with an indefinite block time, so
+ *      // this task will only reach here if the synchronisation was made by all
+ *      // three tasks, so there is no need to test the return value.
+ *  }
+ * }
+ *
+ *
+ * \defgroup xEventGroupSync xEventGroupSync + * \ingroup EventGroup + */ +EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + + +/** + * event_groups.h + * 
+ *  EventBits_t xEventGroupGetBits( EventGroupHandle_t xEventGroup );
+ *
+ * + * Returns the current value of the bits in an event group. This function + * cannot be used from an interrupt. + * + * @param xEventGroup The event group being queried. + * + * @return The event group bits at the time xEventGroupGetBits() was called. + * + * \defgroup xEventGroupGetBits xEventGroupGetBits + * \ingroup EventGroup + */ +#define xEventGroupGetBits( xEventGroup ) xEventGroupClearBits( xEventGroup, 0 ) + +/** + * event_groups.h + * 
+ *  EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup );
+ *
+ * + * A version of xEventGroupGetBits() that can be called from an ISR. + * + * @param xEventGroup The event group being queried. + * + * @return The event group bits at the time xEventGroupGetBitsFromISR() was called. + * + * \defgroup xEventGroupGetBitsFromISR xEventGroupGetBitsFromISR + * \ingroup EventGroup + */ +EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION; + +/** + * event_groups.h + * 
+ *  void xEventGroupDelete( EventGroupHandle_t xEventGroup );
+ *
+ * + * Delete an event group that was previously created by a call to + * xEventGroupCreate(). Tasks that are blocked on the event group will be + * unblocked and obtain 0 as the event group's value. + * + * @param xEventGroup The event group being deleted. + */ +void vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION; + +/* For internal use only. */ +void vEventGroupSetBitsCallback( void * pvEventGroup, + const uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION; +void vEventGroupClearBitsCallback( void * pvEventGroup, + const uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION; + + +#if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxEventGroupGetNumber( void * xEventGroup ) PRIVILEGED_FUNCTION; + void vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) PRIVILEGED_FUNCTION; +#endif + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* EVENT_GROUPS_H */ diff --git a/MODULES/FreeRTOS/inc/list.h b/MODULES/FreeRTOS/inc/list.h new file mode 100644 index 0000000..f1e0f3c --- /dev/null +++ b/MODULES/FreeRTOS/inc/list.h @@ -0,0 +1,417 @@ +/* + * FreeRTOS Kernel V10.4.3 LTS Patch 2 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * This is the list implementation used by the scheduler. While it is tailored + * heavily for the schedulers needs, it is also available for use by + * application code. + * + * list_ts can only store pointers to list_item_ts. Each ListItem_t contains a + * numeric value (xItemValue). Most of the time the lists are sorted in + * descending item value order. + * + * Lists are created already containing one list item. The value of this + * item is the maximum possible that can be stored, it is therefore always at + * the end of the list and acts as a marker. The list member pxHead always + * points to this marker - even though it is at the tail of the list. This + * is because the tail contains a wrap back pointer to the true head of + * the list. + * + * In addition to it's value, each list item contains a pointer to the next + * item in the list (pxNext), a pointer to the list it is in (pxContainer) + * and a pointer to back to the object that contains it. These later two + * pointers are included for efficiency of list manipulation. There is + * effectively a two way link between the object containing the list item and + * the list item itself. + * + * + * \page ListIntroduction List Implementation + * \ingroup FreeRTOSIntro + */ + + +#ifndef LIST_H +#define LIST_H + +#ifndef INC_FREERTOS_H + #error "FreeRTOS.h must be included before list.h" +#endif + +/* + * The list structure members are modified from within interrupts, and therefore + * by rights should be declared volatile. However, they are only modified in a + * functionally atomic way (within critical sections of with the scheduler + * suspended) and are either passed by reference into a function or indexed via + * a volatile variable. Therefore, in all use cases tested so far, the volatile + * qualifier can be omitted in order to provide a moderate performance + * improvement without adversely affecting functional behaviour. The assembly + * instructions generated by the IAR, ARM and GCC compilers when the respective + * compiler's options were set for maximum optimisation has been inspected and + * deemed to be as intended. That said, as compiler technology advances, and + * especially if aggressive cross module optimisation is used (a use case that + * has not been exercised to any great extend) then it is feasible that the + * volatile qualifier will be needed for correct optimisation. It is expected + * that a compiler removing essential code because, without the volatile + * qualifier on the list structure members and with aggressive cross module + * optimisation, the compiler deemed the code unnecessary will result in + * complete and obvious failure of the scheduler. If this is ever experienced + * then the volatile qualifier can be inserted in the relevant places within the + * list structures by simply defining configLIST_VOLATILE to volatile in + * FreeRTOSConfig.h (as per the example at the bottom of this comment block). + * If configLIST_VOLATILE is not defined then the preprocessor directives below + * will simply #define configLIST_VOLATILE away completely. + * + * To use volatile list structure members then add the following line to + * FreeRTOSConfig.h (without the quotes): + * "#define configLIST_VOLATILE volatile" + */ +#ifndef configLIST_VOLATILE + #define configLIST_VOLATILE +#endif /* configSUPPORT_CROSS_MODULE_OPTIMISATION */ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/* Macros that can be used to place known values within the list structures, + * then check that the known values do not get corrupted during the execution of + * the application. These may catch the list data structures being overwritten in + * memory. They will not catch data errors caused by incorrect configuration or + * use of FreeRTOS.*/ +#if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 ) + /* Define the macros to do nothing. */ + #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE + #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE + #define listFIRST_LIST_INTEGRITY_CHECK_VALUE + #define listSECOND_LIST_INTEGRITY_CHECK_VALUE + #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) + #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) + #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ) + #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ) + #define listTEST_LIST_ITEM_INTEGRITY( pxItem ) + #define listTEST_LIST_INTEGRITY( pxList ) +#else /* if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 ) */ + /* Define macros that add new members into the list structures. */ + #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue1; + #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue2; + #define listFIRST_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue1; + #define listSECOND_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue2; + +/* Define macros that set the new structure members to known values. */ + #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue1 = pdINTEGRITY_CHECK_VALUE + #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue2 = pdINTEGRITY_CHECK_VALUE + #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ) ( pxList )->xListIntegrityValue1 = pdINTEGRITY_CHECK_VALUE + #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ) ( pxList )->xListIntegrityValue2 = pdINTEGRITY_CHECK_VALUE + +/* Define macros that will assert if one of the structure members does not + * contain its expected value. */ + #define listTEST_LIST_ITEM_INTEGRITY( pxItem ) configASSERT( ( ( pxItem )->xListItemIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxItem )->xListItemIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) ) + #define listTEST_LIST_INTEGRITY( pxList ) configASSERT( ( ( pxList )->xListIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxList )->xListIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) ) +#endif /* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES */ + + +/* + * Definition of the only type of object that a list can contain. + */ +struct xLIST; +struct xLIST_ITEM +{ + listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + configLIST_VOLATILE TickType_t xItemValue; /*< The value being listed. In most cases this is used to sort the list in descending order. */ + struct xLIST_ITEM * configLIST_VOLATILE pxNext; /*< Pointer to the next ListItem_t in the list. */ + struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; /*< Pointer to the previous ListItem_t in the list. */ + void * pvOwner; /*< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. */ + struct xLIST * configLIST_VOLATILE pxContainer; /*< Pointer to the list in which this list item is placed (if any). */ + listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ +}; +typedef struct xLIST_ITEM ListItem_t; /* For some reason lint wants this as two separate definitions. */ + +struct xMINI_LIST_ITEM +{ + listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + configLIST_VOLATILE TickType_t xItemValue; + struct xLIST_ITEM * configLIST_VOLATILE pxNext; + struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; +}; +typedef struct xMINI_LIST_ITEM MiniListItem_t; + +/* + * Definition of the type of queue used by the scheduler. + */ +typedef struct xLIST +{ + listFIRST_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + volatile UBaseType_t uxNumberOfItems; + ListItem_t * configLIST_VOLATILE pxIndex; /*< Used to walk through the list. Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */ + MiniListItem_t xListEnd; /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */ + listSECOND_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ +} List_t; + +/* + * Access macro to set the owner of a list item. The owner of a list item + * is the object (usually a TCB) that contains the list item. + * + * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER + * \ingroup LinkedList + */ +#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner ) ( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) ) + +/* + * Access macro to get the owner of a list item. The owner of a list item + * is the object (usually a TCB) that contains the list item. + * + * \page listGET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER + * \ingroup LinkedList + */ +#define listGET_LIST_ITEM_OWNER( pxListItem ) ( ( pxListItem )->pvOwner ) + +/* + * Access macro to set the value of the list item. In most cases the value is + * used to sort the list in descending order. + * + * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listSET_LIST_ITEM_VALUE( pxListItem, xValue ) ( ( pxListItem )->xItemValue = ( xValue ) ) + +/* + * Access macro to retrieve the value of the list item. The value can + * represent anything - for example the priority of a task, or the time at + * which a task should be unblocked. + * + * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listGET_LIST_ITEM_VALUE( pxListItem ) ( ( pxListItem )->xItemValue ) + +/* + * Access macro to retrieve the value of the list item at the head of a given + * list. + * + * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE + * \ingroup LinkedList + */ +#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext->xItemValue ) + +/* + * Return the list item at the head of the list. + * + * \page listGET_HEAD_ENTRY listGET_HEAD_ENTRY + * \ingroup LinkedList + */ +#define listGET_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext ) + +/* + * Return the next list item. + * + * \page listGET_NEXT listGET_NEXT + * \ingroup LinkedList + */ +#define listGET_NEXT( pxListItem ) ( ( pxListItem )->pxNext ) + +/* + * Return the list item that marks the end of the list + * + * \page listGET_END_MARKER listGET_END_MARKER + * \ingroup LinkedList + */ +#define listGET_END_MARKER( pxList ) ( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) ) + +/* + * Access macro to determine if a list contains any items. The macro will + * only have the value true if the list is empty. + * + * \page listLIST_IS_EMPTY listLIST_IS_EMPTY + * \ingroup LinkedList + */ +#define listLIST_IS_EMPTY( pxList ) ( ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ? pdTRUE : pdFALSE ) + +/* + * Access macro to return the number of items in the list. + */ +#define listCURRENT_LIST_LENGTH( pxList ) ( ( pxList )->uxNumberOfItems ) + +/* + * Access function to obtain the owner of the next entry in a list. + * + * The list member pxIndex is used to walk through a list. Calling + * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list + * and returns that entry's pxOwner parameter. Using multiple calls to this + * function it is therefore possible to move through every item contained in + * a list. + * + * The pxOwner parameter of a list item is a pointer to the object that owns + * the list item. In the scheduler this is normally a task control block. + * The pxOwner parameter effectively creates a two way link between the list + * item and its owner. + * + * @param pxTCB pxTCB is set to the address of the owner of the next list item. + * @param pxList The list from which the next item owner is to be returned. + * + * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY + * \ingroup LinkedList + */ +#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList ) \ + { \ + List_t * const pxConstList = ( pxList ); \ + /* Increment the index to the next item and return the item, ensuring */ \ + /* we don't return the marker used at the end of the list. */ \ + ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ + if( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) ) \ + { \ + ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ + } \ + ( pxTCB ) = ( pxConstList )->pxIndex->pvOwner; \ + } + + +/* + * Access function to obtain the owner of the first entry in a list. Lists + * are normally sorted in ascending item value order. + * + * This function returns the pxOwner member of the first item in the list. + * The pxOwner parameter of a list item is a pointer to the object that owns + * the list item. In the scheduler this is normally a task control block. + * The pxOwner parameter effectively creates a two way link between the list + * item and its owner. + * + * @param pxList The list from which the owner of the head item is to be + * returned. + * + * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY + * \ingroup LinkedList + */ +#define listGET_OWNER_OF_HEAD_ENTRY( pxList ) ( ( &( ( pxList )->xListEnd ) )->pxNext->pvOwner ) + +/* + * Check to see if a list item is within a list. The list item maintains a + * "container" pointer that points to the list it is in. All this macro does + * is check to see if the container and the list match. + * + * @param pxList The list we want to know if the list item is within. + * @param pxListItem The list item we want to know if is in the list. + * @return pdTRUE if the list item is in the list, otherwise pdFALSE. + */ +#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( ( pxListItem )->pxContainer == ( pxList ) ) ? ( pdTRUE ) : ( pdFALSE ) ) + +/* + * Return the list a list item is contained within (referenced from). + * + * @param pxListItem The list item being queried. + * @return A pointer to the List_t object that references the pxListItem + */ +#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pxContainer ) + +/* + * This provides a crude means of knowing if a list has been initialised, as + * pxList->xListEnd.xItemValue is set to portMAX_DELAY by the vListInitialise() + * function. + */ +#define listLIST_IS_INITIALISED( pxList ) ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY ) + +/* + * Must be called before a list is used! This initialises all the members + * of the list structure and inserts the xListEnd item into the list as a + * marker to the back of the list. + * + * @param pxList Pointer to the list being initialised. + * + * \page vListInitialise vListInitialise + * \ingroup LinkedList + */ +void vListInitialise( List_t * const pxList ) PRIVILEGED_FUNCTION; + +/* + * Must be called before a list item is used. This sets the list container to + * null so the item does not think that it is already contained in a list. + * + * @param pxItem Pointer to the list item being initialised. + * + * \page vListInitialiseItem vListInitialiseItem + * \ingroup LinkedList + */ +void vListInitialiseItem( ListItem_t * const pxItem ) PRIVILEGED_FUNCTION; + +/* + * Insert a list item into a list. The item will be inserted into the list in + * a position determined by its item value (descending item value order). + * + * @param pxList The list into which the item is to be inserted. + * + * @param pxNewListItem The item that is to be placed in the list. + * + * \page vListInsert vListInsert + * \ingroup LinkedList + */ +void vListInsert( List_t * const pxList, + ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION; + +/* + * Insert a list item into a list. The item will be inserted in a position + * such that it will be the last item within the list returned by multiple + * calls to listGET_OWNER_OF_NEXT_ENTRY. + * + * The list member pxIndex is used to walk through a list. Calling + * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list. + * Placing an item in a list using vListInsertEnd effectively places the item + * in the list position pointed to by pxIndex. This means that every other + * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before + * the pxIndex parameter again points to the item being inserted. + * + * @param pxList The list into which the item is to be inserted. + * + * @param pxNewListItem The list item to be inserted into the list. + * + * \page vListInsertEnd vListInsertEnd + * \ingroup LinkedList + */ +void vListInsertEnd( List_t * const pxList, + ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION; + +/* + * Remove an item from a list. The list item has a pointer to the list that + * it is in, so only the list item need be passed into the function. + * + * @param uxListRemove The item to be removed. The item will remove itself from + * the list pointed to by it's pxContainer parameter. + * + * @return The number of items that remain in the list after the list item has + * been removed. + * + * \page uxListRemove uxListRemove + * \ingroup LinkedList + */ +UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) PRIVILEGED_FUNCTION; + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* ifndef LIST_H */ diff --git a/MODULES/FreeRTOS/inc/message_buffer.h b/MODULES/FreeRTOS/inc/message_buffer.h new file mode 100644 index 0000000..10762e6 --- /dev/null +++ b/MODULES/FreeRTOS/inc/message_buffer.h @@ -0,0 +1,821 @@ +/* + * FreeRTOS Kernel V10.4.3 LTS Patch 2 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/* + * Message buffers build functionality on top of FreeRTOS stream buffers. + * Whereas stream buffers are used to send a continuous stream of data from one + * task or interrupt to another, message buffers are used to send variable + * length discrete messages from one task or interrupt to another. Their + * implementation is light weight, making them particularly suited for interrupt + * to task and core to core communication scenarios. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xMessageBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xMessageBufferRead()) inside a critical section and set the receive + * timeout to 0. + * + * Message buffers hold variable length messages. To enable that, when a + * message is written to the message buffer an additional sizeof( size_t ) bytes + * are also written to store the message's length (that happens internally, with + * the API function). sizeof( size_t ) is typically 4 bytes on a 32-bit + * architecture, so writing a 10 byte message to a message buffer on a 32-bit + * architecture will actually reduce the available space in the message buffer + * by 14 bytes (10 byte are used by the message, and 4 bytes to hold the length + * of the message). + */ + +#ifndef FREERTOS_MESSAGE_BUFFER_H +#define FREERTOS_MESSAGE_BUFFER_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include message_buffer.h" +#endif + +/* Message buffers are built onto of stream buffers. */ +#include "stream_buffer.h" + +/* *INDENT-OFF* */ +#if defined( __cplusplus ) + extern "C" { +#endif +/* *INDENT-ON* */ + +/** + * Type by which message buffers are referenced. For example, a call to + * xMessageBufferCreate() returns an MessageBufferHandle_t variable that can + * then be used as a parameter to xMessageBufferSend(), xMessageBufferReceive(), + * etc. + */ +typedef void * MessageBufferHandle_t; + +/*-----------------------------------------------------------*/ + +/** + * message_buffer.h + * + * 
+ * MessageBufferHandle_t xMessageBufferCreate( size_t xBufferSizeBytes );
+ *
+ * + * Creates a new message buffer using dynamically allocated memory. See + * xMessageBufferCreateStatic() for a version that uses statically allocated + * memory (memory that is allocated at compile time). + * + * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in + * FreeRTOSConfig.h for xMessageBufferCreate() to be available. + * + * @param xBufferSizeBytes The total number of bytes (not messages) the message + * buffer will be able to hold at any one time. When a message is written to + * the message buffer an additional sizeof( size_t ) bytes are also written to + * store the message's length. sizeof( size_t ) is typically 4 bytes on a + * 32-bit architecture, so on most 32-bit architectures a 10 byte message will + * take up 14 bytes of message buffer space. + * + * @return If NULL is returned, then the message buffer cannot be created + * because there is insufficient heap memory available for FreeRTOS to allocate + * the message buffer data structures and storage area. A non-NULL value being + * returned indicates that the message buffer has been created successfully - + * the returned value should be stored as the handle to the created message + * buffer. + * + * Example use: + * 
+ *
+ * void vAFunction( void )
+ * {
+ * MessageBufferHandle_t xMessageBuffer;
+ * const size_t xMessageBufferSizeBytes = 100;
+ *
+ *  // Create a message buffer that can hold 100 bytes.  The memory used to hold
+ *  // both the message buffer structure and the messages themselves is allocated
+ *  // dynamically.  Each message added to the buffer consumes an additional 4
+ *  // bytes which are used to hold the lengh of the message.
+ *  xMessageBuffer = xMessageBufferCreate( xMessageBufferSizeBytes );
+ *
+ *  if( xMessageBuffer == NULL )
+ *  {
+ *      // There was not enough heap memory space available to create the
+ *      // message buffer.
+ *  }
+ *  else
+ *  {
+ *      // The message buffer was created successfully and can now be used.
+ *  }
+ *
+ *
+ * \defgroup xMessageBufferCreate xMessageBufferCreate + * \ingroup MessageBufferManagement + */ +#define xMessageBufferCreate( xBufferSizeBytes ) \ + ( MessageBufferHandle_t ) xStreamBufferGenericCreate( xBufferSizeBytes, ( size_t ) 0, pdTRUE ) + +/** + * message_buffer.h + * + * 
+ * MessageBufferHandle_t xMessageBufferCreateStatic( size_t xBufferSizeBytes,
+ *                                                uint8_t *pucMessageBufferStorageArea,
+ *                                                StaticMessageBuffer_t *pxStaticMessageBuffer );
+ *
+ * Creates a new message buffer using statically allocated memory. See + * xMessageBufferCreate() for a version that uses dynamically allocated memory. + * + * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the + * pucMessageBufferStorageArea parameter. When a message is written to the + * message buffer an additional sizeof( size_t ) bytes are also written to store + * the message's length. sizeof( size_t ) is typically 4 bytes on a 32-bit + * architecture, so on most 32-bit architecture a 10 byte message will take up + * 14 bytes of message buffer space. The maximum number of bytes that can be + * stored in the message buffer is actually (xBufferSizeBytes - 1). + * + * @param pucMessageBufferStorageArea Must point to a uint8_t array that is at + * least xBufferSizeBytes + 1 big. This is the array to which messages are + * copied when they are written to the message buffer. + * + * @param pxStaticMessageBuffer Must point to a variable of type + * StaticMessageBuffer_t, which will be used to hold the message buffer's data + * structure. + * + * @return If the message buffer is created successfully then a handle to the + * created message buffer is returned. If either pucMessageBufferStorageArea or + * pxStaticmessageBuffer are NULL then NULL is returned. + * + * Example use: + * 
+ *
+ * // Used to dimension the array used to hold the messages.  The available space
+ * // will actually be one less than this, so 999.
+ #define STORAGE_SIZE_BYTES 1000
+ *
+ * // Defines the memory that will actually hold the messages within the message
+ * // buffer.
+ * static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
+ *
+ * // The variable used to hold the message buffer structure.
+ * StaticMessageBuffer_t xMessageBufferStruct;
+ *
+ * void MyFunction( void )
+ * {
+ * MessageBufferHandle_t xMessageBuffer;
+ *
+ *  xMessageBuffer = xMessageBufferCreateStatic( sizeof( ucBufferStorage ),
+ *                                               ucBufferStorage,
+ *                                               &xMessageBufferStruct );
+ *
+ *  // As neither the pucMessageBufferStorageArea or pxStaticMessageBuffer
+ *  // parameters were NULL, xMessageBuffer will not be NULL, and can be used to
+ *  // reference the created message buffer in other message buffer API calls.
+ *
+ *  // Other code that uses the message buffer can go here.
+ * }
+ *
+ *
+ * \defgroup xMessageBufferCreateStatic xMessageBufferCreateStatic + * \ingroup MessageBufferManagement + */ +#define xMessageBufferCreateStatic( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer ) \ + ( MessageBufferHandle_t ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, 0, pdTRUE, pucMessageBufferStorageArea, pxStaticMessageBuffer ) + +/** + * message_buffer.h + * + * 
+ * size_t xMessageBufferSend( MessageBufferHandle_t xMessageBuffer,
+ *                         const void *pvTxData,
+ *                         size_t xDataLengthBytes,
+ *                         TickType_t xTicksToWait );
+ *
+ * + * Sends a discrete message to the message buffer. The message can be any + * length that fits within the buffer's free space, and is copied into the + * buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xMessageBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xMessageBufferRead()) inside a critical section and set the receive + * block time to 0. + * + * Use xMessageBufferSend() to write to a message buffer from a task. Use + * xMessageBufferSendFromISR() to write to a message buffer from an interrupt + * service routine (ISR). + * + * @param xMessageBuffer The handle of the message buffer to which a message is + * being sent. + * + * @param pvTxData A pointer to the message that is to be copied into the + * message buffer. + * + * @param xDataLengthBytes The length of the message. That is, the number of + * bytes to copy from pvTxData into the message buffer. When a message is + * written to the message buffer an additional sizeof( size_t ) bytes are also + * written to store the message's length. sizeof( size_t ) is typically 4 bytes + * on a 32-bit architecture, so on most 32-bit architecture setting + * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24 + * bytes (20 bytes of message data and 4 bytes to hold the message length). + * + * @param xTicksToWait The maximum amount of time the calling task should remain + * in the Blocked state to wait for enough space to become available in the + * message buffer, should the message buffer have insufficient space when + * xMessageBufferSend() is called. The calling task will never block if + * xTicksToWait is zero. The block time is specified in tick periods, so the + * absolute time it represents is dependent on the tick frequency. The macro + * pdMS_TO_TICKS() can be used to convert a time specified in milliseconds into + * a time specified in ticks. Setting xTicksToWait to portMAX_DELAY will cause + * the task to wait indefinitely (without timing out), provided + * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h. Tasks do not use any + * CPU time when they are in the Blocked state. + * + * @return The number of bytes written to the message buffer. If the call to + * xMessageBufferSend() times out before there was enough space to write the + * message into the message buffer then zero is returned. If the call did not + * time out then xDataLengthBytes is returned. + * + * Example use: + * 
+ * void vAFunction( MessageBufferHandle_t xMessageBuffer )
+ * {
+ * size_t xBytesSent;
+ * uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
+ * char *pcStringToSend = "String to send";
+ * const TickType_t x100ms = pdMS_TO_TICKS( 100 );
+ *
+ *  // Send an array to the message buffer, blocking for a maximum of 100ms to
+ *  // wait for enough space to be available in the message buffer.
+ *  xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
+ *
+ *  if( xBytesSent != sizeof( ucArrayToSend ) )
+ *  {
+ *      // The call to xMessageBufferSend() times out before there was enough
+ *      // space in the buffer for the data to be written.
+ *  }
+ *
+ *  // Send the string to the message buffer.  Return immediately if there is
+ *  // not enough space in the buffer.
+ *  xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
+ *
+ *  if( xBytesSent != strlen( pcStringToSend ) )
+ *  {
+ *      // The string could not be added to the message buffer because there was
+ *      // not enough free space in the buffer.
+ *  }
+ * }
+ *
+ * \defgroup xMessageBufferSend xMessageBufferSend + * \ingroup MessageBufferManagement + */ +#define xMessageBufferSend( xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait ) \ + xStreamBufferSend( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait ) + +/** + * message_buffer.h + * + * 
+ * size_t xMessageBufferSendFromISR( MessageBufferHandle_t xMessageBuffer,
+ *                                const void *pvTxData,
+ *                                size_t xDataLengthBytes,
+ *                                BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * + * Interrupt safe version of the API function that sends a discrete message to + * the message buffer. The message can be any length that fits within the + * buffer's free space, and is copied into the buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xMessageBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xMessageBufferRead()) inside a critical section and set the receive + * block time to 0. + * + * Use xMessageBufferSend() to write to a message buffer from a task. Use + * xMessageBufferSendFromISR() to write to a message buffer from an interrupt + * service routine (ISR). + * + * @param xMessageBuffer The handle of the message buffer to which a message is + * being sent. + * + * @param pvTxData A pointer to the message that is to be copied into the + * message buffer. + * + * @param xDataLengthBytes The length of the message. That is, the number of + * bytes to copy from pvTxData into the message buffer. When a message is + * written to the message buffer an additional sizeof( size_t ) bytes are also + * written to store the message's length. sizeof( size_t ) is typically 4 bytes + * on a 32-bit architecture, so on most 32-bit architecture setting + * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24 + * bytes (20 bytes of message data and 4 bytes to hold the message length). + * + * @param pxHigherPriorityTaskWoken It is possible that a message buffer will + * have a task blocked on it waiting for data. Calling + * xMessageBufferSendFromISR() can make data available, and so cause a task that + * was waiting for data to leave the Blocked state. If calling + * xMessageBufferSendFromISR() causes a task to leave the Blocked state, and the + * unblocked task has a priority higher than the currently executing task (the + * task that was interrupted), then, internally, xMessageBufferSendFromISR() + * will set *pxHigherPriorityTaskWoken to pdTRUE. If + * xMessageBufferSendFromISR() sets this value to pdTRUE, then normally a + * context switch should be performed before the interrupt is exited. This will + * ensure that the interrupt returns directly to the highest priority Ready + * state task. *pxHigherPriorityTaskWoken should be set to pdFALSE before it + * is passed into the function. See the code example below for an example. + * + * @return The number of bytes actually written to the message buffer. If the + * message buffer didn't have enough free space for the message to be stored + * then 0 is returned, otherwise xDataLengthBytes is returned. + * + * Example use: + * 
+ * // A message buffer that has already been created.
+ * MessageBufferHandle_t xMessageBuffer;
+ *
+ * void vAnInterruptServiceRoutine( void )
+ * {
+ * size_t xBytesSent;
+ * char *pcStringToSend = "String to send";
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
+ *
+ *  // Attempt to send the string to the message buffer.
+ *  xBytesSent = xMessageBufferSendFromISR( xMessageBuffer,
+ *                                          ( void * ) pcStringToSend,
+ *                                          strlen( pcStringToSend ),
+ *                                          &xHigherPriorityTaskWoken );
+ *
+ *  if( xBytesSent != strlen( pcStringToSend ) )
+ *  {
+ *      // The string could not be added to the message buffer because there was
+ *      // not enough free space in the buffer.
+ *  }
+ *
+ *  // If xHigherPriorityTaskWoken was set to pdTRUE inside
+ *  // xMessageBufferSendFromISR() then a task that has a priority above the
+ *  // priority of the currently executing task was unblocked and a context
+ *  // switch should be performed to ensure the ISR returns to the unblocked
+ *  // task.  In most FreeRTOS ports this is done by simply passing
+ *  // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
+ *  // variables value, and perform the context switch if necessary.  Check the
+ *  // documentation for the port in use for port specific instructions.
+ *  portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ * }
+ *
+ * \defgroup xMessageBufferSendFromISR xMessageBufferSendFromISR + * \ingroup MessageBufferManagement + */ +#define xMessageBufferSendFromISR( xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ) \ + xStreamBufferSendFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ) + +/** + * message_buffer.h + * + * 
+ * size_t xMessageBufferReceive( MessageBufferHandle_t xMessageBuffer,
+ *                            void *pvRxData,
+ *                            size_t xBufferLengthBytes,
+ *                            TickType_t xTicksToWait );
+ *
+ * + * Receives a discrete message from a message buffer. Messages can be of + * variable length and are copied out of the buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xMessageBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xMessageBufferRead()) inside a critical section and set the receive + * block time to 0. + * + * Use xMessageBufferReceive() to read from a message buffer from a task. Use + * xMessageBufferReceiveFromISR() to read from a message buffer from an + * interrupt service routine (ISR). + * + * @param xMessageBuffer The handle of the message buffer from which a message + * is being received. + * + * @param pvRxData A pointer to the buffer into which the received message is + * to be copied. + * + * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData + * parameter. This sets the maximum length of the message that can be received. + * If xBufferLengthBytes is too small to hold the next message then the message + * will be left in the message buffer and 0 will be returned. + * + * @param xTicksToWait The maximum amount of time the task should remain in the + * Blocked state to wait for a message, should the message buffer be empty. + * xMessageBufferReceive() will return immediately if xTicksToWait is zero and + * the message buffer is empty. The block time is specified in tick periods, so + * the absolute time it represents is dependent on the tick frequency. The + * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds + * into a time specified in ticks. Setting xTicksToWait to portMAX_DELAY will + * cause the task to wait indefinitely (without timing out), provided + * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h. Tasks do not use any + * CPU time when they are in the Blocked state. + * + * @return The length, in bytes, of the message read from the message buffer, if + * any. If xMessageBufferReceive() times out before a message became available + * then zero is returned. If the length of the message is greater than + * xBufferLengthBytes then the message will be left in the message buffer and + * zero is returned. + * + * Example use: + * 
+ * void vAFunction( MessageBuffer_t xMessageBuffer )
+ * {
+ * uint8_t ucRxData[ 20 ];
+ * size_t xReceivedBytes;
+ * const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
+ *
+ *  // Receive the next message from the message buffer.  Wait in the Blocked
+ *  // state (so not using any CPU processing time) for a maximum of 100ms for
+ *  // a message to become available.
+ *  xReceivedBytes = xMessageBufferReceive( xMessageBuffer,
+ *                                          ( void * ) ucRxData,
+ *                                          sizeof( ucRxData ),
+ *                                          xBlockTime );
+ *
+ *  if( xReceivedBytes > 0 )
+ *  {
+ *      // A ucRxData contains a message that is xReceivedBytes long.  Process
+ *      // the message here....
+ *  }
+ * }
+ *
+ * \defgroup xMessageBufferReceive xMessageBufferReceive + * \ingroup MessageBufferManagement + */ +#define xMessageBufferReceive( xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ) \ + xStreamBufferReceive( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ) + + +/** + * message_buffer.h + * + * 
+ * size_t xMessageBufferReceiveFromISR( MessageBufferHandle_t xMessageBuffer,
+ *                                   void *pvRxData,
+ *                                   size_t xBufferLengthBytes,
+ *                                   BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * + * An interrupt safe version of the API function that receives a discrete + * message from a message buffer. Messages can be of variable length and are + * copied out of the buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xMessageBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xMessageBufferRead()) inside a critical section and set the receive + * block time to 0. + * + * Use xMessageBufferReceive() to read from a message buffer from a task. Use + * xMessageBufferReceiveFromISR() to read from a message buffer from an + * interrupt service routine (ISR). + * + * @param xMessageBuffer The handle of the message buffer from which a message + * is being received. + * + * @param pvRxData A pointer to the buffer into which the received message is + * to be copied. + * + * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData + * parameter. This sets the maximum length of the message that can be received. + * If xBufferLengthBytes is too small to hold the next message then the message + * will be left in the message buffer and 0 will be returned. + * + * @param pxHigherPriorityTaskWoken It is possible that a message buffer will + * have a task blocked on it waiting for space to become available. Calling + * xMessageBufferReceiveFromISR() can make space available, and so cause a task + * that is waiting for space to leave the Blocked state. If calling + * xMessageBufferReceiveFromISR() causes a task to leave the Blocked state, and + * the unblocked task has a priority higher than the currently executing task + * (the task that was interrupted), then, internally, + * xMessageBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE. + * If xMessageBufferReceiveFromISR() sets this value to pdTRUE, then normally a + * context switch should be performed before the interrupt is exited. That will + * ensure the interrupt returns directly to the highest priority Ready state + * task. *pxHigherPriorityTaskWoken should be set to pdFALSE before it is + * passed into the function. See the code example below for an example. + * + * @return The length, in bytes, of the message read from the message buffer, if + * any. + * + * Example use: + * 
+ * // A message buffer that has already been created.
+ * MessageBuffer_t xMessageBuffer;
+ *
+ * void vAnInterruptServiceRoutine( void )
+ * {
+ * uint8_t ucRxData[ 20 ];
+ * size_t xReceivedBytes;
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
+ *
+ *  // Receive the next message from the message buffer.
+ *  xReceivedBytes = xMessageBufferReceiveFromISR( xMessageBuffer,
+ *                                                ( void * ) ucRxData,
+ *                                                sizeof( ucRxData ),
+ *                                                &xHigherPriorityTaskWoken );
+ *
+ *  if( xReceivedBytes > 0 )
+ *  {
+ *      // A ucRxData contains a message that is xReceivedBytes long.  Process
+ *      // the message here....
+ *  }
+ *
+ *  // If xHigherPriorityTaskWoken was set to pdTRUE inside
+ *  // xMessageBufferReceiveFromISR() then a task that has a priority above the
+ *  // priority of the currently executing task was unblocked and a context
+ *  // switch should be performed to ensure the ISR returns to the unblocked
+ *  // task.  In most FreeRTOS ports this is done by simply passing
+ *  // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
+ *  // variables value, and perform the context switch if necessary.  Check the
+ *  // documentation for the port in use for port specific instructions.
+ *  portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ * }
+ *
+ * \defgroup xMessageBufferReceiveFromISR xMessageBufferReceiveFromISR + * \ingroup MessageBufferManagement + */ +#define xMessageBufferReceiveFromISR( xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ) \ + xStreamBufferReceiveFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ) + +/** + * message_buffer.h + * + * 
+ * void vMessageBufferDelete( MessageBufferHandle_t xMessageBuffer );
+ *
+ * + * Deletes a message buffer that was previously created using a call to + * xMessageBufferCreate() or xMessageBufferCreateStatic(). If the message + * buffer was created using dynamic memory (that is, by xMessageBufferCreate()), + * then the allocated memory is freed. + * + * A message buffer handle must not be used after the message buffer has been + * deleted. + * + * @param xMessageBuffer The handle of the message buffer to be deleted. + * + */ +#define vMessageBufferDelete( xMessageBuffer ) \ + vStreamBufferDelete( ( StreamBufferHandle_t ) xMessageBuffer ) + +/** + * message_buffer.h + * 
+ * BaseType_t xMessageBufferIsFull( MessageBufferHandle_t xMessageBuffer ) );
+ *
+ * + * Tests to see if a message buffer is full. A message buffer is full if it + * cannot accept any more messages, of any size, until space is made available + * by a message being removed from the message buffer. + * + * @param xMessageBuffer The handle of the message buffer being queried. + * + * @return If the message buffer referenced by xMessageBuffer is full then + * pdTRUE is returned. Otherwise pdFALSE is returned. + */ +#define xMessageBufferIsFull( xMessageBuffer ) \ + xStreamBufferIsFull( ( StreamBufferHandle_t ) xMessageBuffer ) + +/** + * message_buffer.h + * 
+ * BaseType_t xMessageBufferIsEmpty( MessageBufferHandle_t xMessageBuffer ) );
+ *
+ * + * Tests to see if a message buffer is empty (does not contain any messages). + * + * @param xMessageBuffer The handle of the message buffer being queried. + * + * @return If the message buffer referenced by xMessageBuffer is empty then + * pdTRUE is returned. Otherwise pdFALSE is returned. + * + */ +#define xMessageBufferIsEmpty( xMessageBuffer ) \ + xStreamBufferIsEmpty( ( StreamBufferHandle_t ) xMessageBuffer ) + +/** + * message_buffer.h + * 
+ * BaseType_t xMessageBufferReset( MessageBufferHandle_t xMessageBuffer );
+ *
+ * + * Resets a message buffer to its initial empty state, discarding any message it + * contained. + * + * A message buffer can only be reset if there are no tasks blocked on it. + * + * @param xMessageBuffer The handle of the message buffer being reset. + * + * @return If the message buffer was reset then pdPASS is returned. If the + * message buffer could not be reset because either there was a task blocked on + * the message queue to wait for space to become available, or to wait for a + * a message to be available, then pdFAIL is returned. + * + * \defgroup xMessageBufferReset xMessageBufferReset + * \ingroup MessageBufferManagement + */ +#define xMessageBufferReset( xMessageBuffer ) \ + xStreamBufferReset( ( StreamBufferHandle_t ) xMessageBuffer ) + + +/** + * message_buffer.h + * 
+ * size_t xMessageBufferSpaceAvailable( MessageBufferHandle_t xMessageBuffer ) );
+ *
+ * Returns the number of bytes of free space in the message buffer. + * + * @param xMessageBuffer The handle of the message buffer being queried. + * + * @return The number of bytes that can be written to the message buffer before + * the message buffer would be full. When a message is written to the message + * buffer an additional sizeof( size_t ) bytes are also written to store the + * message's length. sizeof( size_t ) is typically 4 bytes on a 32-bit + * architecture, so if xMessageBufferSpacesAvailable() returns 10, then the size + * of the largest message that can be written to the message buffer is 6 bytes. + * + * \defgroup xMessageBufferSpaceAvailable xMessageBufferSpaceAvailable + * \ingroup MessageBufferManagement + */ +#define xMessageBufferSpaceAvailable( xMessageBuffer ) \ + xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer ) +#define xMessageBufferSpacesAvailable( xMessageBuffer ) \ + xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer ) /* Corrects typo in original macro name. */ + +/** + * message_buffer.h + * 
+ * size_t xMessageBufferNextLengthBytes( MessageBufferHandle_t xMessageBuffer ) );
+ *
+ * Returns the length (in bytes) of the next message in a message buffer. + * Useful if xMessageBufferReceive() returned 0 because the size of the buffer + * passed into xMessageBufferReceive() was too small to hold the next message. + * + * @param xMessageBuffer The handle of the message buffer being queried. + * + * @return The length (in bytes) of the next message in the message buffer, or 0 + * if the message buffer is empty. + * + * \defgroup xMessageBufferNextLengthBytes xMessageBufferNextLengthBytes + * \ingroup MessageBufferManagement + */ +#define xMessageBufferNextLengthBytes( xMessageBuffer ) \ + xStreamBufferNextMessageLengthBytes( ( StreamBufferHandle_t ) xMessageBuffer ) PRIVILEGED_FUNCTION; + +/** + * message_buffer.h + * + * 
+ * BaseType_t xMessageBufferSendCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * + * For advanced users only. + * + * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when + * data is sent to a message buffer or stream buffer. If there was a task that + * was blocked on the message or stream buffer waiting for data to arrive then + * the sbSEND_COMPLETED() macro sends a notification to the task to remove it + * from the Blocked state. xMessageBufferSendCompletedFromISR() does the same + * thing. It is provided to enable application writers to implement their own + * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME. + * + * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for + * additional information. + * + * @param xStreamBuffer The handle of the stream buffer to which data was + * written. + * + * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be + * initialised to pdFALSE before it is passed into + * xMessageBufferSendCompletedFromISR(). If calling + * xMessageBufferSendCompletedFromISR() removes a task from the Blocked state, + * and the task has a priority above the priority of the currently running task, + * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a + * context switch should be performed before exiting the ISR. + * + * @return If a task was removed from the Blocked state then pdTRUE is returned. + * Otherwise pdFALSE is returned. + * + * \defgroup xMessageBufferSendCompletedFromISR xMessageBufferSendCompletedFromISR + * \ingroup StreamBufferManagement + */ +#define xMessageBufferSendCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) \ + xStreamBufferSendCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken ) + +/** + * message_buffer.h + * + * 
+ * BaseType_t xMessageBufferReceiveCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * + * For advanced users only. + * + * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when + * data is read out of a message buffer or stream buffer. If there was a task + * that was blocked on the message or stream buffer waiting for data to arrive + * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to + * remove it from the Blocked state. xMessageBufferReceiveCompletedFromISR() + * does the same thing. It is provided to enable application writers to + * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT + * ANY OTHER TIME. + * + * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for + * additional information. + * + * @param xStreamBuffer The handle of the stream buffer from which data was + * read. + * + * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be + * initialised to pdFALSE before it is passed into + * xMessageBufferReceiveCompletedFromISR(). If calling + * xMessageBufferReceiveCompletedFromISR() removes a task from the Blocked state, + * and the task has a priority above the priority of the currently running task, + * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a + * context switch should be performed before exiting the ISR. + * + * @return If a task was removed from the Blocked state then pdTRUE is returned. + * Otherwise pdFALSE is returned. + * + * \defgroup xMessageBufferReceiveCompletedFromISR xMessageBufferReceiveCompletedFromISR + * \ingroup StreamBufferManagement + */ +#define xMessageBufferReceiveCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) \ + xStreamBufferReceiveCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken ) + +/* *INDENT-OFF* */ +#if defined( __cplusplus ) + } /* extern "C" */ +#endif +/* *INDENT-ON* */ + +#endif /* !defined( FREERTOS_MESSAGE_BUFFER_H ) */ diff --git a/MODULES/FreeRTOS/inc/mpu_prototypes.h b/MODULES/FreeRTOS/inc/mpu_prototypes.h new file mode 100644 index 0000000..7667953 --- /dev/null +++ b/MODULES/FreeRTOS/inc/mpu_prototypes.h @@ -0,0 +1,257 @@ +/* + * FreeRTOS Kernel V10.4.3 LTS Patch 2 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * When the MPU is used the standard (non MPU) API functions are mapped to + * equivalents that start "MPU_", the prototypes for which are defined in this + * header files. This will cause the application code to call the MPU_ version + * which wraps the non-MPU version with privilege promoting then demoting code, + * so the kernel code always runs will full privileges. + */ + + +#ifndef MPU_PROTOTYPES_H +#define MPU_PROTOTYPES_H + +/* MPU versions of tasks.h API functions. */ +BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, + const char * const pcName, + const uint16_t usStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, + const char * const pcName, + const uint32_t ulStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + StackType_t * const puxStackBuffer, + StaticTask_t * const pxTaskBuffer ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskPrioritySet( TaskHandle_t xTask, + UBaseType_t uxNewPriority ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskStartScheduler( void ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSuspendAll( void ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskResumeAll( void ) FREERTOS_SYSTEM_CALL; +TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL; +char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTaskGetHandle( const char * pcNameToQuery ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL; +TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) FREERTOS_SYSTEM_CALL; +void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, + void * pvParameter ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + uint32_t * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL; +uint32_t MPU_ulTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskList( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskGetRunTimeStats( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + uint32_t ulValue, + eNotifyAction eAction, + uint32_t * pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn, + uint32_t ulBitsToClearOnEntry, + uint32_t ulBitsToClearOnExit, + uint32_t * pulNotificationValue, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) FREERTOS_SYSTEM_CALL; +uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskIncrementTick( void ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL; +void MPU_vTaskMissedYield( void ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) FREERTOS_SYSTEM_CALL; + +/* MPU versions of queue.h API functions. */ +BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +void MPU_vQueueDelete( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, + StaticQueue_t * pxStaticQueue ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, + const UBaseType_t uxInitialCount ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, + const UBaseType_t uxInitialCount, + StaticQueue_t * pxStaticQueue ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) FREERTOS_SYSTEM_CALL; +void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcName ) FREERTOS_SYSTEM_CALL; +void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL; +QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + uint8_t * pucQueueStorage, + StaticQueue_t * pxStaticQueue, + const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL; +QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL; +QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, + BaseType_t xNewQueue ) FREERTOS_SYSTEM_CALL; +void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue, + UBaseType_t uxQueueNumber ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; +uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL; + +/* MPU versions of timers.h API functions. */ +TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, + const TickType_t xTimerPeriodInTicks, + const UBaseType_t uxAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction ) FREERTOS_SYSTEM_CALL; +TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, + const TickType_t xTimerPeriodInTicks, + const UBaseType_t uxAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction, + StaticTimer_t * pxTimerBuffer ) FREERTOS_SYSTEM_CALL; +void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +void MPU_vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, + void * pvParameter1, + uint32_t ulParameter2, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, + const UBaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTimerCreateTimerTask( void ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, + const BaseType_t xCommandID, + const TickType_t xOptionalValue, + BaseType_t * const pxHigherPriorityTaskWoken, + const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; + +/* MPU versions of event_group.h API functions. */ +EventGroupHandle_t MPU_xEventGroupCreate( void ) FREERTOS_SYSTEM_CALL; +EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) FREERTOS_SYSTEM_CALL; +EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToWaitFor, + const BaseType_t xClearOnExit, + const BaseType_t xWaitForAllBits, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL; +EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL; +EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) FREERTOS_SYSTEM_CALL; +UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) FREERTOS_SYSTEM_CALL; + +/* MPU versions of message/stream_buffer.h API functions. */ +size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL; +size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL; +BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL; +StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xIsMessageBuffer ) FREERTOS_SYSTEM_CALL; +StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xIsMessageBuffer, + uint8_t * const pucStreamBufferStorageArea, + StaticStreamBuffer_t * const pxStaticStreamBuffer ) FREERTOS_SYSTEM_CALL; + + + +#endif /* MPU_PROTOTYPES_H */ diff --git a/MODULES/FreeRTOS/inc/mpu_wrappers.h b/MODULES/FreeRTOS/inc/mpu_wrappers.h new file mode 100644 index 0000000..ba63846 --- /dev/null +++ b/MODULES/FreeRTOS/inc/mpu_wrappers.h @@ -0,0 +1,215 @@ +/* + * FreeRTOS Kernel V10.4.3 LTS Patch 2 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef MPU_WRAPPERS_H +#define MPU_WRAPPERS_H + +/* This file redefines API functions to be called through a wrapper macro, but + * only for ports that are using the MPU. */ +#ifdef portUSING_MPU_WRAPPERS + +/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is + * included from queue.c or task.c to prevent it from having an effect within + * those files. */ + #ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* + * Map standard (non MPU) API functions to equivalents that start + * "MPU_". This will cause the application code to call the MPU_ + * version, which wraps the non-MPU version with privilege promoting + * then demoting code, so the kernel code always runs will full + * privileges. + */ + +/* Map standard tasks.h API functions to the MPU equivalents. */ + #define xTaskCreate MPU_xTaskCreate + #define xTaskCreateStatic MPU_xTaskCreateStatic + #define vTaskDelete MPU_vTaskDelete + #define vTaskDelay MPU_vTaskDelay + #define xTaskDelayUntil MPU_xTaskDelayUntil + #define xTaskAbortDelay MPU_xTaskAbortDelay + #define uxTaskPriorityGet MPU_uxTaskPriorityGet + #define eTaskGetState MPU_eTaskGetState + #define vTaskGetInfo MPU_vTaskGetInfo + #define vTaskPrioritySet MPU_vTaskPrioritySet + #define vTaskSuspend MPU_vTaskSuspend + #define vTaskResume MPU_vTaskResume + #define vTaskSuspendAll MPU_vTaskSuspendAll + #define xTaskResumeAll MPU_xTaskResumeAll + #define xTaskGetTickCount MPU_xTaskGetTickCount + #define uxTaskGetNumberOfTasks MPU_uxTaskGetNumberOfTasks + #define pcTaskGetName MPU_pcTaskGetName + #define xTaskGetHandle MPU_xTaskGetHandle + #define uxTaskGetStackHighWaterMark MPU_uxTaskGetStackHighWaterMark + #define uxTaskGetStackHighWaterMark2 MPU_uxTaskGetStackHighWaterMark2 + #define vTaskSetApplicationTaskTag MPU_vTaskSetApplicationTaskTag + #define xTaskGetApplicationTaskTag MPU_xTaskGetApplicationTaskTag + #define vTaskSetThreadLocalStoragePointer MPU_vTaskSetThreadLocalStoragePointer + #define pvTaskGetThreadLocalStoragePointer MPU_pvTaskGetThreadLocalStoragePointer + #define xTaskCallApplicationTaskHook MPU_xTaskCallApplicationTaskHook + #define xTaskGetIdleTaskHandle MPU_xTaskGetIdleTaskHandle + #define uxTaskGetSystemState MPU_uxTaskGetSystemState + #define vTaskList MPU_vTaskList + #define vTaskGetRunTimeStats MPU_vTaskGetRunTimeStats + #define ulTaskGetIdleRunTimeCounter MPU_ulTaskGetIdleRunTimeCounter + #define xTaskGenericNotify MPU_xTaskGenericNotify + #define xTaskGenericNotifyWait MPU_xTaskGenericNotifyWait + #define ulTaskGenericNotifyTake MPU_ulTaskGenericNotifyTake + #define xTaskGenericNotifyStateClear MPU_xTaskGenericNotifyStateClear + #define ulTaskGenericNotifyValueClear MPU_ulTaskGenericNotifyValueClear + #define xTaskCatchUpTicks MPU_xTaskCatchUpTicks + + #define xTaskGetCurrentTaskHandle MPU_xTaskGetCurrentTaskHandle + #define vTaskSetTimeOutState MPU_vTaskSetTimeOutState + #define xTaskCheckForTimeOut MPU_xTaskCheckForTimeOut + #define xTaskGetSchedulerState MPU_xTaskGetSchedulerState + +/* Map standard queue.h API functions to the MPU equivalents. */ + #define xQueueGenericSend MPU_xQueueGenericSend + #define xQueueReceive MPU_xQueueReceive + #define xQueuePeek MPU_xQueuePeek + #define xQueueSemaphoreTake MPU_xQueueSemaphoreTake + #define uxQueueMessagesWaiting MPU_uxQueueMessagesWaiting + #define uxQueueSpacesAvailable MPU_uxQueueSpacesAvailable + #define vQueueDelete MPU_vQueueDelete + #define xQueueCreateMutex MPU_xQueueCreateMutex + #define xQueueCreateMutexStatic MPU_xQueueCreateMutexStatic + #define xQueueCreateCountingSemaphore MPU_xQueueCreateCountingSemaphore + #define xQueueCreateCountingSemaphoreStatic MPU_xQueueCreateCountingSemaphoreStatic + #define xQueueGetMutexHolder MPU_xQueueGetMutexHolder + #define xQueueTakeMutexRecursive MPU_xQueueTakeMutexRecursive + #define xQueueGiveMutexRecursive MPU_xQueueGiveMutexRecursive + #define xQueueGenericCreate MPU_xQueueGenericCreate + #define xQueueGenericCreateStatic MPU_xQueueGenericCreateStatic + #define xQueueCreateSet MPU_xQueueCreateSet + #define xQueueAddToSet MPU_xQueueAddToSet + #define xQueueRemoveFromSet MPU_xQueueRemoveFromSet + #define xQueueSelectFromSet MPU_xQueueSelectFromSet + #define xQueueGenericReset MPU_xQueueGenericReset + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + #define vQueueAddToRegistry MPU_vQueueAddToRegistry + #define vQueueUnregisterQueue MPU_vQueueUnregisterQueue + #define pcQueueGetName MPU_pcQueueGetName + #endif + +/* Map standard timer.h API functions to the MPU equivalents. */ + #define xTimerCreate MPU_xTimerCreate + #define xTimerCreateStatic MPU_xTimerCreateStatic + #define pvTimerGetTimerID MPU_pvTimerGetTimerID + #define vTimerSetTimerID MPU_vTimerSetTimerID + #define xTimerIsTimerActive MPU_xTimerIsTimerActive + #define xTimerGetTimerDaemonTaskHandle MPU_xTimerGetTimerDaemonTaskHandle + #define xTimerPendFunctionCall MPU_xTimerPendFunctionCall + #define pcTimerGetName MPU_pcTimerGetName + #define vTimerSetReloadMode MPU_vTimerSetReloadMode + #define uxTimerGetReloadMode MPU_uxTimerGetReloadMode + #define xTimerGetPeriod MPU_xTimerGetPeriod + #define xTimerGetExpiryTime MPU_xTimerGetExpiryTime + #define xTimerGenericCommand MPU_xTimerGenericCommand + +/* Map standard event_group.h API functions to the MPU equivalents. */ + #define xEventGroupCreate MPU_xEventGroupCreate + #define xEventGroupCreateStatic MPU_xEventGroupCreateStatic + #define xEventGroupWaitBits MPU_xEventGroupWaitBits + #define xEventGroupClearBits MPU_xEventGroupClearBits + #define xEventGroupSetBits MPU_xEventGroupSetBits + #define xEventGroupSync MPU_xEventGroupSync + #define vEventGroupDelete MPU_vEventGroupDelete + +/* Map standard message/stream_buffer.h API functions to the MPU + * equivalents. */ + #define xStreamBufferSend MPU_xStreamBufferSend + #define xStreamBufferReceive MPU_xStreamBufferReceive + #define xStreamBufferNextMessageLengthBytes MPU_xStreamBufferNextMessageLengthBytes + #define vStreamBufferDelete MPU_vStreamBufferDelete + #define xStreamBufferIsFull MPU_xStreamBufferIsFull + #define xStreamBufferIsEmpty MPU_xStreamBufferIsEmpty + #define xStreamBufferReset MPU_xStreamBufferReset + #define xStreamBufferSpacesAvailable MPU_xStreamBufferSpacesAvailable + #define xStreamBufferBytesAvailable MPU_xStreamBufferBytesAvailable + #define xStreamBufferSetTriggerLevel MPU_xStreamBufferSetTriggerLevel + #define xStreamBufferGenericCreate MPU_xStreamBufferGenericCreate + #define xStreamBufferGenericCreateStatic MPU_xStreamBufferGenericCreateStatic + + +/* Remove the privileged function macro, but keep the PRIVILEGED_DATA + * macro so applications can place data in privileged access sections + * (useful when using statically allocated objects). */ + #define PRIVILEGED_FUNCTION + #define PRIVILEGED_DATA __attribute__( ( section( "privileged_data" ) ) ) + #define FREERTOS_SYSTEM_CALL + + #else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */ + + /* Ensure API functions go in the privileged execution section. */ + #define PRIVILEGED_FUNCTION __attribute__( ( section( "privileged_functions" ) ) ) + #define PRIVILEGED_DATA __attribute__( ( section( "privileged_data" ) ) ) + #define FREERTOS_SYSTEM_CALL __attribute__( ( section( "freertos_system_calls" ) ) ) + + /** + * @brief Calls the port specific code to raise the privilege. + * + * Sets xRunningPrivileged to pdFALSE if privilege was raised, else sets + * it to pdTRUE. + */ + #define xPortRaisePrivilege( xRunningPrivileged ) \ + { \ + /* Check whether the processor is already privileged. */ \ + xRunningPrivileged = portIS_PRIVILEGED(); \ + \ + /* If the processor is not already privileged, raise privilege. */ \ + if( xRunningPrivileged == pdFALSE ) \ + { \ + portRAISE_PRIVILEGE(); \ + } \ + } + + /** + * @brief If xRunningPrivileged is not pdTRUE, calls the port specific + * code to reset the privilege, otherwise does nothing. + */ + #define vPortResetPrivilege( xRunningPrivileged ) \ + { \ + if( xRunningPrivileged == pdFALSE ) \ + { \ + portRESET_PRIVILEGE(); \ + } \ + } + + #endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */ + +#else /* portUSING_MPU_WRAPPERS */ + + #define PRIVILEGED_FUNCTION + #define PRIVILEGED_DATA + #define FREERTOS_SYSTEM_CALL + #define portUSING_MPU_WRAPPERS 0 + +#endif /* portUSING_MPU_WRAPPERS */ + + +#endif /* MPU_WRAPPERS_H */ diff --git a/MODULES/FreeRTOS/inc/portable.h b/MODULES/FreeRTOS/inc/portable.h new file mode 100644 index 0000000..2d52cf2 --- /dev/null +++ b/MODULES/FreeRTOS/inc/portable.h @@ -0,0 +1,216 @@ +/* + * FreeRTOS Kernel V10.4.3 LTS Patch 2 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Portable layer API. Each function must be defined for each port. +*----------------------------------------------------------*/ + +#ifndef PORTABLE_H +#define PORTABLE_H + +/* Each FreeRTOS port has a unique portmacro.h header file. Originally a + * pre-processor definition was used to ensure the pre-processor found the correct + * portmacro.h file for the port being used. That scheme was deprecated in favour + * of setting the compiler's include path such that it found the correct + * portmacro.h file - removing the need for the constant and allowing the + * portmacro.h file to be located anywhere in relation to the port being used. + * Purely for reasons of backward compatibility the old method is still valid, but + * to make it clear that new projects should not use it, support for the port + * specific constants has been moved into the deprecated_definitions.h header + * file. */ +#include "deprecated_definitions.h" + +/* If portENTER_CRITICAL is not defined then including deprecated_definitions.h + * did not result in a portmacro.h header file being included - and it should be + * included here. In this case the path to the correct portmacro.h header file + * must be set in the compiler's include path. */ +#ifndef portENTER_CRITICAL + #include "portmacro.h" +#endif + +#if portBYTE_ALIGNMENT == 32 + #define portBYTE_ALIGNMENT_MASK ( 0x001f ) +#endif + +#if portBYTE_ALIGNMENT == 16 + #define portBYTE_ALIGNMENT_MASK ( 0x000f ) +#endif + +#if portBYTE_ALIGNMENT == 8 + #define portBYTE_ALIGNMENT_MASK ( 0x0007 ) +#endif + +#if portBYTE_ALIGNMENT == 4 + #define portBYTE_ALIGNMENT_MASK ( 0x0003 ) +#endif + +#if portBYTE_ALIGNMENT == 2 + #define portBYTE_ALIGNMENT_MASK ( 0x0001 ) +#endif + +#if portBYTE_ALIGNMENT == 1 + #define portBYTE_ALIGNMENT_MASK ( 0x0000 ) +#endif + +#ifndef portBYTE_ALIGNMENT_MASK + #error "Invalid portBYTE_ALIGNMENT definition" +#endif + +#ifndef portNUM_CONFIGURABLE_REGIONS + #define portNUM_CONFIGURABLE_REGIONS 1 +#endif + +#ifndef portHAS_STACK_OVERFLOW_CHECKING + #define portHAS_STACK_OVERFLOW_CHECKING 0 +#endif + +#ifndef portARCH_NAME + #define portARCH_NAME NULL +#endif + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +#include "mpu_wrappers.h" + +/* + * Setup the stack of a new task so it is ready to be placed under the + * scheduler control. The registers have to be placed on the stack in + * the order that the port expects to find them. + * + */ +#if ( portUSING_MPU_WRAPPERS == 1 ) + #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 ) + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION; + #else + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters, + BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION; + #endif +#else /* if ( portUSING_MPU_WRAPPERS == 1 ) */ + #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 ) + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + StackType_t * pxEndOfStack, + TaskFunction_t pxCode, + void * pvParameters ) PRIVILEGED_FUNCTION; + #else + StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, + TaskFunction_t pxCode, + void * pvParameters ) PRIVILEGED_FUNCTION; + #endif +#endif /* if ( portUSING_MPU_WRAPPERS == 1 ) */ + +/* Used by heap_5.c to define the start address and size of each memory region + * that together comprise the total FreeRTOS heap space. */ +typedef struct HeapRegion +{ + uint8_t * pucStartAddress; + size_t xSizeInBytes; +} HeapRegion_t; + +/* Used to pass information about the heap out of vPortGetHeapStats(). */ +typedef struct xHeapStats +{ + size_t xAvailableHeapSpaceInBytes; /* The total heap size currently available - this is the sum of all the free blocks, not the largest block that can be allocated. */ + size_t xSizeOfLargestFreeBlockInBytes; /* The maximum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */ + size_t xSizeOfSmallestFreeBlockInBytes; /* The minimum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */ + size_t xNumberOfFreeBlocks; /* The number of free memory blocks within the heap at the time vPortGetHeapStats() is called. */ + size_t xMinimumEverFreeBytesRemaining; /* The minimum amount of total free memory (sum of all free blocks) there has been in the heap since the system booted. */ + size_t xNumberOfSuccessfulAllocations; /* The number of calls to pvPortMalloc() that have returned a valid memory block. */ + size_t xNumberOfSuccessfulFrees; /* The number of calls to vPortFree() that has successfully freed a block of memory. */ +} HeapStats_t; + +/* + * Used to define multiple heap regions for use by heap_5.c. This function + * must be called before any calls to pvPortMalloc() - not creating a task, + * queue, semaphore, mutex, software timer, event group, etc. will result in + * pvPortMalloc being called. + * + * pxHeapRegions passes in an array of HeapRegion_t structures - each of which + * defines a region of memory that can be used as the heap. The array is + * terminated by a HeapRegions_t structure that has a size of 0. The region + * with the lowest start address must appear first in the array. + */ +void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION; + +/* + * Returns a HeapStats_t structure filled with information about the current + * heap state. + */ +void vPortGetHeapStats( HeapStats_t * pxHeapStats ); + +/* + * Map to the memory management routines required for the port. + */ +void * pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION; +void vPortFree( void * pv ) PRIVILEGED_FUNCTION; +void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION; +size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION; +size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION; + +/* + * Setup the hardware ready for the scheduler to take control. This generally + * sets up a tick interrupt and sets timers for the correct tick frequency. + */ +BaseType_t xPortStartScheduler( void ) PRIVILEGED_FUNCTION; + +/* + * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so + * the hardware is left in its original condition after the scheduler stops + * executing. + */ +void vPortEndScheduler( void ) PRIVILEGED_FUNCTION; + +/* + * The structures and methods of manipulating the MPU are contained within the + * port layer. + * + * Fills the xMPUSettings structure with the memory region information + * contained in xRegions. + */ +#if ( portUSING_MPU_WRAPPERS == 1 ) + struct xMEMORY_REGION; + void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings, + const struct xMEMORY_REGION * const xRegions, + StackType_t * pxBottomOfStack, + uint32_t ulStackDepth ) PRIVILEGED_FUNCTION; +#endif + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* PORTABLE_H */ diff --git a/MODULES/FreeRTOS/inc/projdefs.h b/MODULES/FreeRTOS/inc/projdefs.h new file mode 100644 index 0000000..878d5e2 --- /dev/null +++ b/MODULES/FreeRTOS/inc/projdefs.h @@ -0,0 +1,120 @@ +/* + * FreeRTOS Kernel V10.4.3 LTS Patch 2 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef PROJDEFS_H +#define PROJDEFS_H + +/* + * Defines the prototype to which task functions must conform. Defined in this + * file to ensure the type is known before portable.h is included. + */ +typedef void (* TaskFunction_t)( void * ); + +/* Converts a time in milliseconds to a time in ticks. This macro can be + * overridden by a macro of the same name defined in FreeRTOSConfig.h in case the + * definition here is not suitable for your application. */ +#ifndef pdMS_TO_TICKS + #define pdMS_TO_TICKS( xTimeInMs ) ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000U ) ) +#endif + +#define pdFALSE ( ( BaseType_t ) 0 ) +#define pdTRUE ( ( BaseType_t ) 1 ) + +#define pdPASS ( pdTRUE ) +#define pdFAIL ( pdFALSE ) +#define errQUEUE_EMPTY ( ( BaseType_t ) 0 ) +#define errQUEUE_FULL ( ( BaseType_t ) 0 ) + +/* FreeRTOS error definitions. */ +#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ( -1 ) +#define errQUEUE_BLOCKED ( -4 ) +#define errQUEUE_YIELD ( -5 ) + +/* Macros used for basic data corruption checks. */ +#ifndef configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES + #define configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES 0 +#endif + +#if ( configUSE_16_BIT_TICKS == 1 ) + #define pdINTEGRITY_CHECK_VALUE 0x5a5a +#else + #define pdINTEGRITY_CHECK_VALUE 0x5a5a5a5aUL +#endif + +/* The following errno values are used by FreeRTOS+ components, not FreeRTOS + * itself. */ +#define pdFREERTOS_ERRNO_NONE 0 /* No errors */ +#define pdFREERTOS_ERRNO_ENOENT 2 /* No such file or directory */ +#define pdFREERTOS_ERRNO_EINTR 4 /* Interrupted system call */ +#define pdFREERTOS_ERRNO_EIO 5 /* I/O error */ +#define pdFREERTOS_ERRNO_ENXIO 6 /* No such device or address */ +#define pdFREERTOS_ERRNO_EBADF 9 /* Bad file number */ +#define pdFREERTOS_ERRNO_EAGAIN 11 /* No more processes */ +#define pdFREERTOS_ERRNO_EWOULDBLOCK 11 /* Operation would block */ +#define pdFREERTOS_ERRNO_ENOMEM 12 /* Not enough memory */ +#define pdFREERTOS_ERRNO_EACCES 13 /* Permission denied */ +#define pdFREERTOS_ERRNO_EFAULT 14 /* Bad address */ +#define pdFREERTOS_ERRNO_EBUSY 16 /* Mount device busy */ +#define pdFREERTOS_ERRNO_EEXIST 17 /* File exists */ +#define pdFREERTOS_ERRNO_EXDEV 18 /* Cross-device link */ +#define pdFREERTOS_ERRNO_ENODEV 19 /* No such device */ +#define pdFREERTOS_ERRNO_ENOTDIR 20 /* Not a directory */ +#define pdFREERTOS_ERRNO_EISDIR 21 /* Is a directory */ +#define pdFREERTOS_ERRNO_EINVAL 22 /* Invalid argument */ +#define pdFREERTOS_ERRNO_ENOSPC 28 /* No space left on device */ +#define pdFREERTOS_ERRNO_ESPIPE 29 /* Illegal seek */ +#define pdFREERTOS_ERRNO_EROFS 30 /* Read only file system */ +#define pdFREERTOS_ERRNO_EUNATCH 42 /* Protocol driver not attached */ +#define pdFREERTOS_ERRNO_EBADE 50 /* Invalid exchange */ +#define pdFREERTOS_ERRNO_EFTYPE 79 /* Inappropriate file type or format */ +#define pdFREERTOS_ERRNO_ENMFILE 89 /* No more files */ +#define pdFREERTOS_ERRNO_ENOTEMPTY 90 /* Directory not empty */ +#define pdFREERTOS_ERRNO_ENAMETOOLONG 91 /* File or path name too long */ +#define pdFREERTOS_ERRNO_EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ +#define pdFREERTOS_ERRNO_ENOBUFS 105 /* No buffer space available */ +#define pdFREERTOS_ERRNO_ENOPROTOOPT 109 /* Protocol not available */ +#define pdFREERTOS_ERRNO_EADDRINUSE 112 /* Address already in use */ +#define pdFREERTOS_ERRNO_ETIMEDOUT 116 /* Connection timed out */ +#define pdFREERTOS_ERRNO_EINPROGRESS 119 /* Connection already in progress */ +#define pdFREERTOS_ERRNO_EALREADY 120 /* Socket already connected */ +#define pdFREERTOS_ERRNO_EADDRNOTAVAIL 125 /* Address not available */ +#define pdFREERTOS_ERRNO_EISCONN 127 /* Socket is already connected */ +#define pdFREERTOS_ERRNO_ENOTCONN 128 /* Socket is not connected */ +#define pdFREERTOS_ERRNO_ENOMEDIUM 135 /* No medium inserted */ +#define pdFREERTOS_ERRNO_EILSEQ 138 /* An invalid UTF-16 sequence was encountered. */ +#define pdFREERTOS_ERRNO_ECANCELED 140 /* Operation canceled. */ + +/* The following endian values are used by FreeRTOS+ components, not FreeRTOS + * itself. */ +#define pdFREERTOS_LITTLE_ENDIAN 0 +#define pdFREERTOS_BIG_ENDIAN 1 + +/* Re-defining endian values for generic naming. */ +#define pdLITTLE_ENDIAN pdFREERTOS_LITTLE_ENDIAN +#define pdBIG_ENDIAN pdFREERTOS_BIG_ENDIAN + + +#endif /* PROJDEFS_H */ diff --git a/MODULES/FreeRTOS/inc/queue.h b/MODULES/FreeRTOS/inc/queue.h new file mode 100644 index 0000000..bc0f6f0 --- /dev/null +++ b/MODULES/FreeRTOS/inc/queue.h @@ -0,0 +1,1716 @@ +/* + * FreeRTOS Kernel V10.4.3 LTS Patch 2 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef QUEUE_H +#define QUEUE_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h" must appear in source files before "include queue.h" +#endif + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +#include "task.h" + +/** + * Type by which queues are referenced. For example, a call to xQueueCreate() + * returns an QueueHandle_t variable that can then be used as a parameter to + * xQueueSend(), xQueueReceive(), etc. + */ +struct QueueDefinition; /* Using old naming convention so as not to break kernel aware debuggers. */ +typedef struct QueueDefinition * QueueHandle_t; + +/** + * Type by which queue sets are referenced. For example, a call to + * xQueueCreateSet() returns an xQueueSet variable that can then be used as a + * parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc. + */ +typedef struct QueueDefinition * QueueSetHandle_t; + +/** + * Queue sets can contain both queues and semaphores, so the + * QueueSetMemberHandle_t is defined as a type to be used where a parameter or + * return value can be either an QueueHandle_t or an SemaphoreHandle_t. + */ +typedef struct QueueDefinition * QueueSetMemberHandle_t; + +/* For internal use only. */ +#define queueSEND_TO_BACK ( ( BaseType_t ) 0 ) +#define queueSEND_TO_FRONT ( ( BaseType_t ) 1 ) +#define queueOVERWRITE ( ( BaseType_t ) 2 ) + +/* For internal use only. These definitions *must* match those in queue.c. */ +#define queueQUEUE_TYPE_BASE ( ( uint8_t ) 0U ) +#define queueQUEUE_TYPE_SET ( ( uint8_t ) 0U ) +#define queueQUEUE_TYPE_MUTEX ( ( uint8_t ) 1U ) +#define queueQUEUE_TYPE_COUNTING_SEMAPHORE ( ( uint8_t ) 2U ) +#define queueQUEUE_TYPE_BINARY_SEMAPHORE ( ( uint8_t ) 3U ) +#define queueQUEUE_TYPE_RECURSIVE_MUTEX ( ( uint8_t ) 4U ) + +/** + * queue. h + * 
+ * QueueHandle_t xQueueCreate(
+ *                            UBaseType_t uxQueueLength,
+ *                            UBaseType_t uxItemSize
+ *                        );
+ *
+ * + * Creates a new queue instance, and returns a handle by which the new queue + * can be referenced. + * + * Internally, within the FreeRTOS implementation, queues use two blocks of + * memory. The first block is used to hold the queue's data structures. The + * second block is used to hold items placed into the queue. If a queue is + * created using xQueueCreate() then both blocks of memory are automatically + * dynamically allocated inside the xQueueCreate() function. (see + * https://www.FreeRTOS.org/a00111.html). If a queue is created using + * xQueueCreateStatic() then the application writer must provide the memory that + * will get used by the queue. xQueueCreateStatic() therefore allows a queue to + * be created without using any dynamic memory allocation. + * + * https://www.FreeRTOS.org/Embedded-RTOS-Queues.html + * + * @param uxQueueLength The maximum number of items that the queue can contain. + * + * @param uxItemSize The number of bytes each item in the queue will require. + * Items are queued by copy, not by reference, so this is the number of bytes + * that will be copied for each posted item. Each item on the queue must be + * the same size. + * + * @return If the queue is successfully create then a handle to the newly + * created queue is returned. If the queue cannot be created then 0 is + * returned. + * + * Example usage: + * 
+ * struct AMessage
+ * {
+ *  char ucMessageID;
+ *  char ucData[ 20 ];
+ * };
+ *
+ * void vATask( void *pvParameters )
+ * {
+ * QueueHandle_t xQueue1, xQueue2;
+ *
+ *  // Create a queue capable of containing 10 uint32_t values.
+ *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+ *  if( xQueue1 == 0 )
+ *  {
+ *      // Queue was not created and must not be used.
+ *  }
+ *
+ *  // Create a queue capable of containing 10 pointers to AMessage structures.
+ *  // These should be passed by pointer as they contain a lot of data.
+ *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+ *  if( xQueue2 == 0 )
+ *  {
+ *      // Queue was not created and must not be used.
+ *  }
+ *
+ *  // ... Rest of task code.
+ * }
+ *
+ * \defgroup xQueueCreate xQueueCreate + * \ingroup QueueManagement + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + #define xQueueCreate( uxQueueLength, uxItemSize ) xQueueGenericCreate( ( uxQueueLength ), ( uxItemSize ), ( queueQUEUE_TYPE_BASE ) ) +#endif + +/** + * queue. h + * 
+ * QueueHandle_t xQueueCreateStatic(
+ *                            UBaseType_t uxQueueLength,
+ *                            UBaseType_t uxItemSize,
+ *                            uint8_t *pucQueueStorageBuffer,
+ *                            StaticQueue_t *pxQueueBuffer
+ *                        );
+ *
+ * + * Creates a new queue instance, and returns a handle by which the new queue + * can be referenced. + * + * Internally, within the FreeRTOS implementation, queues use two blocks of + * memory. The first block is used to hold the queue's data structures. The + * second block is used to hold items placed into the queue. If a queue is + * created using xQueueCreate() then both blocks of memory are automatically + * dynamically allocated inside the xQueueCreate() function. (see + * https://www.FreeRTOS.org/a00111.html). If a queue is created using + * xQueueCreateStatic() then the application writer must provide the memory that + * will get used by the queue. xQueueCreateStatic() therefore allows a queue to + * be created without using any dynamic memory allocation. + * + * https://www.FreeRTOS.org/Embedded-RTOS-Queues.html + * + * @param uxQueueLength The maximum number of items that the queue can contain. + * + * @param uxItemSize The number of bytes each item in the queue will require. + * Items are queued by copy, not by reference, so this is the number of bytes + * that will be copied for each posted item. Each item on the queue must be + * the same size. + * + * @param pucQueueStorageBuffer If uxItemSize is not zero then + * pucQueueStorageBuffer must point to a uint8_t array that is at least large + * enough to hold the maximum number of items that can be in the queue at any + * one time - which is ( uxQueueLength * uxItemsSize ) bytes. If uxItemSize is + * zero then pucQueueStorageBuffer can be NULL. + * + * @param pxQueueBuffer Must point to a variable of type StaticQueue_t, which + * will be used to hold the queue's data structure. + * + * @return If the queue is created then a handle to the created queue is + * returned. If pxQueueBuffer is NULL then NULL is returned. + * + * Example usage: + * 
+ * struct AMessage
+ * {
+ *  char ucMessageID;
+ *  char ucData[ 20 ];
+ * };
+ *
+ #define QUEUE_LENGTH 10
+ #define ITEM_SIZE sizeof( uint32_t )
+ *
+ * // xQueueBuffer will hold the queue structure.
+ * StaticQueue_t xQueueBuffer;
+ *
+ * // ucQueueStorage will hold the items posted to the queue.  Must be at least
+ * // [(queue length) * ( queue item size)] bytes long.
+ * uint8_t ucQueueStorage[ QUEUE_LENGTH * ITEM_SIZE ];
+ *
+ * void vATask( void *pvParameters )
+ * {
+ * QueueHandle_t xQueue1;
+ *
+ *  // Create a queue capable of containing 10 uint32_t values.
+ *  xQueue1 = xQueueCreate( QUEUE_LENGTH, // The number of items the queue can hold.
+ *                          ITEM_SIZE     // The size of each item in the queue
+ *                          &( ucQueueStorage[ 0 ] ), // The buffer that will hold the items in the queue.
+ *                          &xQueueBuffer ); // The buffer that will hold the queue structure.
+ *
+ *  // The queue is guaranteed to be created successfully as no dynamic memory
+ *  // allocation is used.  Therefore xQueue1 is now a handle to a valid queue.
+ *
+ *  // ... Rest of task code.
+ * }
+ *
+ * \defgroup xQueueCreateStatic xQueueCreateStatic + * \ingroup QueueManagement + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + #define xQueueCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxQueueBuffer ) xQueueGenericCreateStatic( ( uxQueueLength ), ( uxItemSize ), ( pucQueueStorage ), ( pxQueueBuffer ), ( queueQUEUE_TYPE_BASE ) ) +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/** + * queue. h + * 
+ * BaseType_t xQueueSendToToFront(
+ *                                 QueueHandle_t    xQueue,
+ *                                 const void       *pvItemToQueue,
+ *                                 TickType_t       xTicksToWait
+ *                             );
+ *
+ * + * Post an item to the front of a queue. The item is queued by copy, not by + * reference. This function must not be called from an interrupt service + * routine. See xQueueSendFromISR () for an alternative which may be used + * in an ISR. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for space to become available on the queue, should it already + * be full. The call will return immediately if this is set to 0 and the + * queue is full. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * + * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. + * + * Example usage: + * 
+ * struct AMessage
+ * {
+ *  char ucMessageID;
+ *  char ucData[ 20 ];
+ * } xMessage;
+ *
+ * uint32_t ulVar = 10UL;
+ *
+ * void vATask( void *pvParameters )
+ * {
+ * QueueHandle_t xQueue1, xQueue2;
+ * struct AMessage *pxMessage;
+ *
+ *  // Create a queue capable of containing 10 uint32_t values.
+ *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+ *
+ *  // Create a queue capable of containing 10 pointers to AMessage structures.
+ *  // These should be passed by pointer as they contain a lot of data.
+ *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+ *
+ *  // ...
+ *
+ *  if( xQueue1 != 0 )
+ *  {
+ *      // Send an uint32_t.  Wait for 10 ticks for space to become
+ *      // available if necessary.
+ *      if( xQueueSendToFront( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+ *      {
+ *          // Failed to post the message, even after 10 ticks.
+ *      }
+ *  }
+ *
+ *  if( xQueue2 != 0 )
+ *  {
+ *      // Send a pointer to a struct AMessage object.  Don't block if the
+ *      // queue is already full.
+ *      pxMessage = & xMessage;
+ *      xQueueSendToFront( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+ *  }
+ *
+ *  // ... Rest of task code.
+ * }
+ *
+ * \defgroup xQueueSend xQueueSend + * \ingroup QueueManagement + */ +#define xQueueSendToFront( xQueue, pvItemToQueue, xTicksToWait ) \ + xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT ) + +/** + * queue. h + * 
+ * BaseType_t xQueueSendToBack(
+ *                                 QueueHandle_t    xQueue,
+ *                                 const void       *pvItemToQueue,
+ *                                 TickType_t       xTicksToWait
+ *                             );
+ *
+ * + * This is a macro that calls xQueueGenericSend(). + * + * Post an item to the back of a queue. The item is queued by copy, not by + * reference. This function must not be called from an interrupt service + * routine. See xQueueSendFromISR () for an alternative which may be used + * in an ISR. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for space to become available on the queue, should it already + * be full. The call will return immediately if this is set to 0 and the queue + * is full. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * + * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. + * + * Example usage: + * 
+ * struct AMessage
+ * {
+ *  char ucMessageID;
+ *  char ucData[ 20 ];
+ * } xMessage;
+ *
+ * uint32_t ulVar = 10UL;
+ *
+ * void vATask( void *pvParameters )
+ * {
+ * QueueHandle_t xQueue1, xQueue2;
+ * struct AMessage *pxMessage;
+ *
+ *  // Create a queue capable of containing 10 uint32_t values.
+ *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+ *
+ *  // Create a queue capable of containing 10 pointers to AMessage structures.
+ *  // These should be passed by pointer as they contain a lot of data.
+ *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+ *
+ *  // ...
+ *
+ *  if( xQueue1 != 0 )
+ *  {
+ *      // Send an uint32_t.  Wait for 10 ticks for space to become
+ *      // available if necessary.
+ *      if( xQueueSendToBack( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+ *      {
+ *          // Failed to post the message, even after 10 ticks.
+ *      }
+ *  }
+ *
+ *  if( xQueue2 != 0 )
+ *  {
+ *      // Send a pointer to a struct AMessage object.  Don't block if the
+ *      // queue is already full.
+ *      pxMessage = & xMessage;
+ *      xQueueSendToBack( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+ *  }
+ *
+ *  // ... Rest of task code.
+ * }
+ *
+ * \defgroup xQueueSend xQueueSend + * \ingroup QueueManagement + */ +#define xQueueSendToBack( xQueue, pvItemToQueue, xTicksToWait ) \ + xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK ) + +/** + * queue. h + * 
+ * BaseType_t xQueueSend(
+ *                            QueueHandle_t xQueue,
+ *                            const void * pvItemToQueue,
+ *                            TickType_t xTicksToWait
+ *                       );
+ *
+ * + * This is a macro that calls xQueueGenericSend(). It is included for + * backward compatibility with versions of FreeRTOS.org that did not + * include the xQueueSendToFront() and xQueueSendToBack() macros. It is + * equivalent to xQueueSendToBack(). + * + * Post an item on a queue. The item is queued by copy, not by reference. + * This function must not be called from an interrupt service routine. + * See xQueueSendFromISR () for an alternative which may be used in an ISR. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for space to become available on the queue, should it already + * be full. The call will return immediately if this is set to 0 and the + * queue is full. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * + * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. + * + * Example usage: + * 
+ * struct AMessage
+ * {
+ *  char ucMessageID;
+ *  char ucData[ 20 ];
+ * } xMessage;
+ *
+ * uint32_t ulVar = 10UL;
+ *
+ * void vATask( void *pvParameters )
+ * {
+ * QueueHandle_t xQueue1, xQueue2;
+ * struct AMessage *pxMessage;
+ *
+ *  // Create a queue capable of containing 10 uint32_t values.
+ *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+ *
+ *  // Create a queue capable of containing 10 pointers to AMessage structures.
+ *  // These should be passed by pointer as they contain a lot of data.
+ *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+ *
+ *  // ...
+ *
+ *  if( xQueue1 != 0 )
+ *  {
+ *      // Send an uint32_t.  Wait for 10 ticks for space to become
+ *      // available if necessary.
+ *      if( xQueueSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+ *      {
+ *          // Failed to post the message, even after 10 ticks.
+ *      }
+ *  }
+ *
+ *  if( xQueue2 != 0 )
+ *  {
+ *      // Send a pointer to a struct AMessage object.  Don't block if the
+ *      // queue is already full.
+ *      pxMessage = & xMessage;
+ *      xQueueSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+ *  }
+ *
+ *  // ... Rest of task code.
+ * }
+ *
+ * \defgroup xQueueSend xQueueSend + * \ingroup QueueManagement + */ +#define xQueueSend( xQueue, pvItemToQueue, xTicksToWait ) \ + xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK ) + +/** + * queue. h + * 
+ * BaseType_t xQueueOverwrite(
+ *                            QueueHandle_t xQueue,
+ *                            const void * pvItemToQueue
+ *                       );
+ *
+ * + * Only for use with queues that have a length of one - so the queue is either + * empty or full. + * + * Post an item on a queue. If the queue is already full then overwrite the + * value held in the queue. The item is queued by copy, not by reference. + * + * This function must not be called from an interrupt service routine. + * See xQueueOverwriteFromISR () for an alternative which may be used in an ISR. + * + * @param xQueue The handle of the queue to which the data is being sent. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @return xQueueOverwrite() is a macro that calls xQueueGenericSend(), and + * therefore has the same return values as xQueueSendToFront(). However, pdPASS + * is the only value that can be returned because xQueueOverwrite() will write + * to the queue even when the queue is already full. + * + * Example usage: + * 
+ *
+ * void vFunction( void *pvParameters )
+ * {
+ * QueueHandle_t xQueue;
+ * uint32_t ulVarToSend, ulValReceived;
+ *
+ *  // Create a queue to hold one uint32_t value.  It is strongly
+ *  // recommended *not* to use xQueueOverwrite() on queues that can
+ *  // contain more than one value, and doing so will trigger an assertion
+ *  // if configASSERT() is defined.
+ *  xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+ *
+ *  // Write the value 10 to the queue using xQueueOverwrite().
+ *  ulVarToSend = 10;
+ *  xQueueOverwrite( xQueue, &ulVarToSend );
+ *
+ *  // Peeking the queue should now return 10, but leave the value 10 in
+ *  // the queue.  A block time of zero is used as it is known that the
+ *  // queue holds a value.
+ *  ulValReceived = 0;
+ *  xQueuePeek( xQueue, &ulValReceived, 0 );
+ *
+ *  if( ulValReceived != 10 )
+ *  {
+ *      // Error unless the item was removed by a different task.
+ *  }
+ *
+ *  // The queue is still full.  Use xQueueOverwrite() to overwrite the
+ *  // value held in the queue with 100.
+ *  ulVarToSend = 100;
+ *  xQueueOverwrite( xQueue, &ulVarToSend );
+ *
+ *  // This time read from the queue, leaving the queue empty once more.
+ *  // A block time of 0 is used again.
+ *  xQueueReceive( xQueue, &ulValReceived, 0 );
+ *
+ *  // The value read should be the last value written, even though the
+ *  // queue was already full when the value was written.
+ *  if( ulValReceived != 100 )
+ *  {
+ *      // Error!
+ *  }
+ *
+ *  // ...
+ * }
+ *
+ * \defgroup xQueueOverwrite xQueueOverwrite + * \ingroup QueueManagement + */ +#define xQueueOverwrite( xQueue, pvItemToQueue ) \ + xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), 0, queueOVERWRITE ) + + +/** + * queue. h + * 
+ * BaseType_t xQueueGenericSend(
+ *                                  QueueHandle_t xQueue,
+ *                                  const void * pvItemToQueue,
+ *                                  TickType_t xTicksToWait
+ *                                  BaseType_t xCopyPosition
+ *                              );
+ *
+ * + * It is preferred that the macros xQueueSend(), xQueueSendToFront() and + * xQueueSendToBack() are used in place of calling this function directly. + * + * Post an item on a queue. The item is queued by copy, not by reference. + * This function must not be called from an interrupt service routine. + * See xQueueSendFromISR () for an alternative which may be used in an ISR. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for space to become available on the queue, should it already + * be full. The call will return immediately if this is set to 0 and the + * queue is full. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * + * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the + * item at the back of the queue, or queueSEND_TO_FRONT to place the item + * at the front of the queue (for high priority messages). + * + * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL. + * + * Example usage: + * 
+ * struct AMessage
+ * {
+ *  char ucMessageID;
+ *  char ucData[ 20 ];
+ * } xMessage;
+ *
+ * uint32_t ulVar = 10UL;
+ *
+ * void vATask( void *pvParameters )
+ * {
+ * QueueHandle_t xQueue1, xQueue2;
+ * struct AMessage *pxMessage;
+ *
+ *  // Create a queue capable of containing 10 uint32_t values.
+ *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+ *
+ *  // Create a queue capable of containing 10 pointers to AMessage structures.
+ *  // These should be passed by pointer as they contain a lot of data.
+ *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+ *
+ *  // ...
+ *
+ *  if( xQueue1 != 0 )
+ *  {
+ *      // Send an uint32_t.  Wait for 10 ticks for space to become
+ *      // available if necessary.
+ *      if( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10, queueSEND_TO_BACK ) != pdPASS )
+ *      {
+ *          // Failed to post the message, even after 10 ticks.
+ *      }
+ *  }
+ *
+ *  if( xQueue2 != 0 )
+ *  {
+ *      // Send a pointer to a struct AMessage object.  Don't block if the
+ *      // queue is already full.
+ *      pxMessage = & xMessage;
+ *      xQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0, queueSEND_TO_BACK );
+ *  }
+ *
+ *  // ... Rest of task code.
+ * }
+ *
+ * \defgroup xQueueSend xQueueSend + * \ingroup QueueManagement + */ +BaseType_t xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * 
+ * BaseType_t xQueuePeek(
+ *                           QueueHandle_t xQueue,
+ *                           void * const pvBuffer,
+ *                           TickType_t xTicksToWait
+ *                       );
+ *
+ * + * Receive an item from a queue without removing the item from the queue. + * The item is received by copy so a buffer of adequate size must be + * provided. The number of bytes copied into the buffer was defined when + * the queue was created. + * + * Successfully received items remain on the queue so will be returned again + * by the next call, or a call to xQueueReceive(). + * + * This macro must not be used in an interrupt service routine. See + * xQueuePeekFromISR() for an alternative that can be called from an interrupt + * service routine. + * + * @param xQueue The handle to the queue from which the item is to be + * received. + * + * @param pvBuffer Pointer to the buffer into which the received item will + * be copied. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for an item to receive should the queue be empty at the time + * of the call. The time is defined in tick periods so the constant + * portTICK_PERIOD_MS should be used to convert to real time if this is required. + * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue + * is empty. + * + * @return pdTRUE if an item was successfully received from the queue, + * otherwise pdFALSE. + * + * Example usage: + * 
+ * struct AMessage
+ * {
+ *  char ucMessageID;
+ *  char ucData[ 20 ];
+ * } xMessage;
+ *
+ * QueueHandle_t xQueue;
+ *
+ * // Task to create a queue and post a value.
+ * void vATask( void *pvParameters )
+ * {
+ * struct AMessage *pxMessage;
+ *
+ *  // Create a queue capable of containing 10 pointers to AMessage structures.
+ *  // These should be passed by pointer as they contain a lot of data.
+ *  xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+ *  if( xQueue == 0 )
+ *  {
+ *      // Failed to create the queue.
+ *  }
+ *
+ *  // ...
+ *
+ *  // Send a pointer to a struct AMessage object.  Don't block if the
+ *  // queue is already full.
+ *  pxMessage = & xMessage;
+ *  xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+ *
+ *  // ... Rest of task code.
+ * }
+ *
+ * // Task to peek the data from the queue.
+ * void vADifferentTask( void *pvParameters )
+ * {
+ * struct AMessage *pxRxedMessage;
+ *
+ *  if( xQueue != 0 )
+ *  {
+ *      // Peek a message on the created queue.  Block for 10 ticks if a
+ *      // message is not immediately available.
+ *      if( xQueuePeek( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+ *      {
+ *          // pcRxedMessage now points to the struct AMessage variable posted
+ *          // by vATask, but the item still remains on the queue.
+ *      }
+ *  }
+ *
+ *  // ... Rest of task code.
+ * }
+ *
+ * \defgroup xQueuePeek xQueuePeek + * \ingroup QueueManagement + */ +BaseType_t xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * 
+ * BaseType_t xQueuePeekFromISR(
+ *                                  QueueHandle_t xQueue,
+ *                                  void *pvBuffer,
+ *                              );
+ *
+ * + * A version of xQueuePeek() that can be called from an interrupt service + * routine (ISR). + * + * Receive an item from a queue without removing the item from the queue. + * The item is received by copy so a buffer of adequate size must be + * provided. The number of bytes copied into the buffer was defined when + * the queue was created. + * + * Successfully received items remain on the queue so will be returned again + * by the next call, or a call to xQueueReceive(). + * + * @param xQueue The handle to the queue from which the item is to be + * received. + * + * @param pvBuffer Pointer to the buffer into which the received item will + * be copied. + * + * @return pdTRUE if an item was successfully received from the queue, + * otherwise pdFALSE. + * + * \defgroup xQueuePeekFromISR xQueuePeekFromISR + * \ingroup QueueManagement + */ +BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, + void * const pvBuffer ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * 
+ * BaseType_t xQueueReceive(
+ *                               QueueHandle_t xQueue,
+ *                               void *pvBuffer,
+ *                               TickType_t xTicksToWait
+ *                          );
+ *
+ * + * Receive an item from a queue. The item is received by copy so a buffer of + * adequate size must be provided. The number of bytes copied into the buffer + * was defined when the queue was created. + * + * Successfully received items are removed from the queue. + * + * This function must not be used in an interrupt service routine. See + * xQueueReceiveFromISR for an alternative that can. + * + * @param xQueue The handle to the queue from which the item is to be + * received. + * + * @param pvBuffer Pointer to the buffer into which the received item will + * be copied. + * + * @param xTicksToWait The maximum amount of time the task should block + * waiting for an item to receive should the queue be empty at the time + * of the call. xQueueReceive() will return immediately if xTicksToWait + * is zero and the queue is empty. The time is defined in tick periods so the + * constant portTICK_PERIOD_MS should be used to convert to real time if this is + * required. + * + * @return pdTRUE if an item was successfully received from the queue, + * otherwise pdFALSE. + * + * Example usage: + * 
+ * struct AMessage
+ * {
+ *  char ucMessageID;
+ *  char ucData[ 20 ];
+ * } xMessage;
+ *
+ * QueueHandle_t xQueue;
+ *
+ * // Task to create a queue and post a value.
+ * void vATask( void *pvParameters )
+ * {
+ * struct AMessage *pxMessage;
+ *
+ *  // Create a queue capable of containing 10 pointers to AMessage structures.
+ *  // These should be passed by pointer as they contain a lot of data.
+ *  xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+ *  if( xQueue == 0 )
+ *  {
+ *      // Failed to create the queue.
+ *  }
+ *
+ *  // ...
+ *
+ *  // Send a pointer to a struct AMessage object.  Don't block if the
+ *  // queue is already full.
+ *  pxMessage = & xMessage;
+ *  xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+ *
+ *  // ... Rest of task code.
+ * }
+ *
+ * // Task to receive from the queue.
+ * void vADifferentTask( void *pvParameters )
+ * {
+ * struct AMessage *pxRxedMessage;
+ *
+ *  if( xQueue != 0 )
+ *  {
+ *      // Receive a message on the created queue.  Block for 10 ticks if a
+ *      // message is not immediately available.
+ *      if( xQueueReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+ *      {
+ *          // pcRxedMessage now points to the struct AMessage variable posted
+ *          // by vATask.
+ *      }
+ *  }
+ *
+ *  // ... Rest of task code.
+ * }
+ *
+ * \defgroup xQueueReceive xQueueReceive + * \ingroup QueueManagement + */ +BaseType_t xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * 
+ * UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue );
+ *
+ * + * Return the number of messages stored in a queue. + * + * @param xQueue A handle to the queue being queried. + * + * @return The number of messages available in the queue. + * + * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting + * \ingroup QueueManagement + */ +UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * 
+ * UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue );
+ *
+ * + * Return the number of free spaces available in a queue. This is equal to the + * number of items that can be sent to the queue before the queue becomes full + * if no items are removed. + * + * @param xQueue A handle to the queue being queried. + * + * @return The number of spaces available in the queue. + * + * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting + * \ingroup QueueManagement + */ +UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * 
+ * void vQueueDelete( QueueHandle_t xQueue );
+ *
+ * + * Delete a queue - freeing all the memory allocated for storing of items + * placed on the queue. + * + * @param xQueue A handle to the queue to be deleted. + * + * \defgroup vQueueDelete vQueueDelete + * \ingroup QueueManagement + */ +void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * 
+ * BaseType_t xQueueSendToFrontFromISR(
+ *                                       QueueHandle_t xQueue,
+ *                                       const void *pvItemToQueue,
+ *                                       BaseType_t *pxHigherPriorityTaskWoken
+ *                                    );
+ *
+ * + * This is a macro that calls xQueueGenericSendFromISR(). + * + * Post an item to the front of a queue. It is safe to use this macro from + * within an interrupt service routine. + * + * Items are queued by copy not reference so it is preferable to only + * queue small items, especially when called from an ISR. In most cases + * it would be preferable to store a pointer to the item being queued. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xQueueSendToFromFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return pdTRUE if the data was successfully sent to the queue, otherwise + * errQUEUE_FULL. + * + * Example usage for buffered IO (where the ISR can obtain more than one value + * per call): + * 
+ * void vBufferISR( void )
+ * {
+ * char cIn;
+ * BaseType_t xHigherPrioritTaskWoken;
+ *
+ *  // We have not woken a task at the start of the ISR.
+ *  xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *  // Loop until the buffer is empty.
+ *  do
+ *  {
+ *      // Obtain a byte from the buffer.
+ *      cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+ *
+ *      // Post the byte.
+ *      xQueueSendToFrontFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+ *
+ *  } while( portINPUT_BYTE( BUFFER_COUNT ) );
+ *
+ *  // Now the buffer is empty we can switch context if necessary.
+ *  if( xHigherPriorityTaskWoken )
+ *  {
+ *      taskYIELD ();
+ *  }
+ * }
+ *
+ * + * \defgroup xQueueSendFromISR xQueueSendFromISR + * \ingroup QueueManagement + */ +#define xQueueSendToFrontFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \ + xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_FRONT ) + + +/** + * queue. h + * 
+ * BaseType_t xQueueSendToBackFromISR(
+ *                                       QueueHandle_t xQueue,
+ *                                       const void *pvItemToQueue,
+ *                                       BaseType_t *pxHigherPriorityTaskWoken
+ *                                    );
+ *
+ * + * This is a macro that calls xQueueGenericSendFromISR(). + * + * Post an item to the back of a queue. It is safe to use this macro from + * within an interrupt service routine. + * + * Items are queued by copy not reference so it is preferable to only + * queue small items, especially when called from an ISR. In most cases + * it would be preferable to store a pointer to the item being queued. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param pxHigherPriorityTaskWoken xQueueSendToBackFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xQueueSendToBackFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return pdTRUE if the data was successfully sent to the queue, otherwise + * errQUEUE_FULL. + * + * Example usage for buffered IO (where the ISR can obtain more than one value + * per call): + * 
+ * void vBufferISR( void )
+ * {
+ * char cIn;
+ * BaseType_t xHigherPriorityTaskWoken;
+ *
+ *  // We have not woken a task at the start of the ISR.
+ *  xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *  // Loop until the buffer is empty.
+ *  do
+ *  {
+ *      // Obtain a byte from the buffer.
+ *      cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+ *
+ *      // Post the byte.
+ *      xQueueSendToBackFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+ *
+ *  } while( portINPUT_BYTE( BUFFER_COUNT ) );
+ *
+ *  // Now the buffer is empty we can switch context if necessary.
+ *  if( xHigherPriorityTaskWoken )
+ *  {
+ *      taskYIELD ();
+ *  }
+ * }
+ *
+ * + * \defgroup xQueueSendFromISR xQueueSendFromISR + * \ingroup QueueManagement + */ +#define xQueueSendToBackFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \ + xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK ) + +/** + * queue. h + * 
+ * BaseType_t xQueueOverwriteFromISR(
+ *                            QueueHandle_t xQueue,
+ *                            const void * pvItemToQueue,
+ *                            BaseType_t *pxHigherPriorityTaskWoken
+ *                       );
+ *
+ * + * A version of xQueueOverwrite() that can be used in an interrupt service + * routine (ISR). + * + * Only for use with queues that can hold a single item - so the queue is either + * empty or full. + * + * Post an item on a queue. If the queue is already full then overwrite the + * value held in the queue. The item is queued by copy, not by reference. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param pxHigherPriorityTaskWoken xQueueOverwriteFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xQueueOverwriteFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return xQueueOverwriteFromISR() is a macro that calls + * xQueueGenericSendFromISR(), and therefore has the same return values as + * xQueueSendToFrontFromISR(). However, pdPASS is the only value that can be + * returned because xQueueOverwriteFromISR() will write to the queue even when + * the queue is already full. + * + * Example usage: + * 
+ *
+ * QueueHandle_t xQueue;
+ *
+ * void vFunction( void *pvParameters )
+ * {
+ *  // Create a queue to hold one uint32_t value.  It is strongly
+ *  // recommended *not* to use xQueueOverwriteFromISR() on queues that can
+ *  // contain more than one value, and doing so will trigger an assertion
+ *  // if configASSERT() is defined.
+ *  xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+ * }
+ *
+ * void vAnInterruptHandler( void )
+ * {
+ * // xHigherPriorityTaskWoken must be set to pdFALSE before it is used.
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ * uint32_t ulVarToSend, ulValReceived;
+ *
+ *  // Write the value 10 to the queue using xQueueOverwriteFromISR().
+ *  ulVarToSend = 10;
+ *  xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+ *
+ *  // The queue is full, but calling xQueueOverwriteFromISR() again will still
+ *  // pass because the value held in the queue will be overwritten with the
+ *  // new value.
+ *  ulVarToSend = 100;
+ *  xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+ *
+ *  // Reading from the queue will now return 100.
+ *
+ *  // ...
+ *
+ *  if( xHigherPrioritytaskWoken == pdTRUE )
+ *  {
+ *      // Writing to the queue caused a task to unblock and the unblocked task
+ *      // has a priority higher than or equal to the priority of the currently
+ *      // executing task (the task this interrupt interrupted).  Perform a context
+ *      // switch so this interrupt returns directly to the unblocked task.
+ *      portYIELD_FROM_ISR(); // or portEND_SWITCHING_ISR() depending on the port.
+ *  }
+ * }
+ *
+ * \defgroup xQueueOverwriteFromISR xQueueOverwriteFromISR + * \ingroup QueueManagement + */ +#define xQueueOverwriteFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \ + xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueOVERWRITE ) + +/** + * queue. h + * 
+ * BaseType_t xQueueSendFromISR(
+ *                                   QueueHandle_t xQueue,
+ *                                   const void *pvItemToQueue,
+ *                                   BaseType_t *pxHigherPriorityTaskWoken
+ *                              );
+ *
+ * + * This is a macro that calls xQueueGenericSendFromISR(). It is included + * for backward compatibility with versions of FreeRTOS.org that did not + * include the xQueueSendToBackFromISR() and xQueueSendToFrontFromISR() + * macros. + * + * Post an item to the back of a queue. It is safe to use this function from + * within an interrupt service routine. + * + * Items are queued by copy not reference so it is preferable to only + * queue small items, especially when called from an ISR. In most cases + * it would be preferable to store a pointer to the item being queued. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param pxHigherPriorityTaskWoken xQueueSendFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xQueueSendFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return pdTRUE if the data was successfully sent to the queue, otherwise + * errQUEUE_FULL. + * + * Example usage for buffered IO (where the ISR can obtain more than one value + * per call): + * 
+ * void vBufferISR( void )
+ * {
+ * char cIn;
+ * BaseType_t xHigherPriorityTaskWoken;
+ *
+ *  // We have not woken a task at the start of the ISR.
+ *  xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *  // Loop until the buffer is empty.
+ *  do
+ *  {
+ *      // Obtain a byte from the buffer.
+ *      cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+ *
+ *      // Post the byte.
+ *      xQueueSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+ *
+ *  } while( portINPUT_BYTE( BUFFER_COUNT ) );
+ *
+ *  // Now the buffer is empty we can switch context if necessary.
+ *  if( xHigherPriorityTaskWoken )
+ *  {
+ *      // Actual macro used here is port specific.
+ *      portYIELD_FROM_ISR ();
+ *  }
+ * }
+ *
+ * + * \defgroup xQueueSendFromISR xQueueSendFromISR + * \ingroup QueueManagement + */ +#define xQueueSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \ + xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK ) + +/** + * queue. h + * 
+ * BaseType_t xQueueGenericSendFromISR(
+ *                                         QueueHandle_t    xQueue,
+ *                                         const    void    *pvItemToQueue,
+ *                                         BaseType_t  *pxHigherPriorityTaskWoken,
+ *                                         BaseType_t  xCopyPosition
+ *                                     );
+ *
+ * + * It is preferred that the macros xQueueSendFromISR(), + * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place + * of calling this function directly. xQueueGiveFromISR() is an + * equivalent for use by semaphores that don't actually copy any data. + * + * Post an item on a queue. It is safe to use this function from within an + * interrupt service routine. + * + * Items are queued by copy not reference so it is preferable to only + * queue small items, especially when called from an ISR. In most cases + * it would be preferable to store a pointer to the item being queued. + * + * @param xQueue The handle to the queue on which the item is to be posted. + * + * @param pvItemToQueue A pointer to the item that is to be placed on the + * queue. The size of the items the queue will hold was defined when the + * queue was created, so this many bytes will be copied from pvItemToQueue + * into the queue storage area. + * + * @param pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xQueueGenericSendFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the + * item at the back of the queue, or queueSEND_TO_FRONT to place the item + * at the front of the queue (for high priority messages). + * + * @return pdTRUE if the data was successfully sent to the queue, otherwise + * errQUEUE_FULL. + * + * Example usage for buffered IO (where the ISR can obtain more than one value + * per call): + * 
+ * void vBufferISR( void )
+ * {
+ * char cIn;
+ * BaseType_t xHigherPriorityTaskWokenByPost;
+ *
+ *  // We have not woken a task at the start of the ISR.
+ *  xHigherPriorityTaskWokenByPost = pdFALSE;
+ *
+ *  // Loop until the buffer is empty.
+ *  do
+ *  {
+ *      // Obtain a byte from the buffer.
+ *      cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+ *
+ *      // Post each byte.
+ *      xQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK );
+ *
+ *  } while( portINPUT_BYTE( BUFFER_COUNT ) );
+ *
+ *  // Now the buffer is empty we can switch context if necessary.  Note that the
+ *  // name of the yield function required is port specific.
+ *  if( xHigherPriorityTaskWokenByPost )
+ *  {
+ *      portYIELD_FROM_ISR();
+ *  }
+ * }
+ *
+ * + * \defgroup xQueueSendFromISR xQueueSendFromISR + * \ingroup QueueManagement + */ +BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, + const void * const pvItemToQueue, + BaseType_t * const pxHigherPriorityTaskWoken, + const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION; +BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, + BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/** + * queue. h + * 
+ * BaseType_t xQueueReceiveFromISR(
+ *                                     QueueHandle_t    xQueue,
+ *                                     void             *pvBuffer,
+ *                                     BaseType_t       *pxTaskWoken
+ *                                 );
+ *
+ * + * Receive an item from a queue. It is safe to use this function from within an + * interrupt service routine. + * + * @param xQueue The handle to the queue from which the item is to be + * received. + * + * @param pvBuffer Pointer to the buffer into which the received item will + * be copied. + * + * @param pxTaskWoken A task may be blocked waiting for space to become + * available on the queue. If xQueueReceiveFromISR causes such a task to + * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will + * remain unchanged. + * + * @return pdTRUE if an item was successfully received from the queue, + * otherwise pdFALSE. + * + * Example usage: + * 
+ *
+ * QueueHandle_t xQueue;
+ *
+ * // Function to create a queue and post some values.
+ * void vAFunction( void *pvParameters )
+ * {
+ * char cValueToPost;
+ * const TickType_t xTicksToWait = ( TickType_t )0xff;
+ *
+ *  // Create a queue capable of containing 10 characters.
+ *  xQueue = xQueueCreate( 10, sizeof( char ) );
+ *  if( xQueue == 0 )
+ *  {
+ *      // Failed to create the queue.
+ *  }
+ *
+ *  // ...
+ *
+ *  // Post some characters that will be used within an ISR.  If the queue
+ *  // is full then this task will block for xTicksToWait ticks.
+ *  cValueToPost = 'a';
+ *  xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+ *  cValueToPost = 'b';
+ *  xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+ *
+ *  // ... keep posting characters ... this task may block when the queue
+ *  // becomes full.
+ *
+ *  cValueToPost = 'c';
+ *  xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+ * }
+ *
+ * // ISR that outputs all the characters received on the queue.
+ * void vISR_Routine( void )
+ * {
+ * BaseType_t xTaskWokenByReceive = pdFALSE;
+ * char cRxedChar;
+ *
+ *  while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )
+ *  {
+ *      // A character was received.  Output the character now.
+ *      vOutputCharacter( cRxedChar );
+ *
+ *      // If removing the character from the queue woke the task that was
+ *      // posting onto the queue cTaskWokenByReceive will have been set to
+ *      // pdTRUE.  No matter how many times this loop iterates only one
+ *      // task will be woken.
+ *  }
+ *
+ *  if( cTaskWokenByPost != ( char ) pdFALSE;
+ *  {
+ *      taskYIELD ();
+ *  }
+ * }
+ *
+ * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR + * \ingroup QueueManagement + */ +BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, + void * const pvBuffer, + BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/* + * Utilities to query queues that are safe to use from an ISR. These utilities + * should be used only from witin an ISR, or within a critical section. + */ +BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + +/* + * The functions defined above are for passing data to and from tasks. The + * functions below are the equivalents for passing data to and from + * co-routines. + * + * These functions are called from the co-routine macro implementation and + * should not be called directly from application code. Instead use the macro + * wrappers defined within croutine.h. + */ +BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, + const void * pvItemToQueue, + BaseType_t xCoRoutinePreviouslyWoken ); +BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, + void * pvBuffer, + BaseType_t * pxTaskWoken ); +BaseType_t xQueueCRSend( QueueHandle_t xQueue, + const void * pvItemToQueue, + TickType_t xTicksToWait ); +BaseType_t xQueueCRReceive( QueueHandle_t xQueue, + void * pvBuffer, + TickType_t xTicksToWait ); + +/* + * For internal use only. Use xSemaphoreCreateMutex(), + * xSemaphoreCreateCounting() or xSemaphoreGetMutexHolder() instead of calling + * these functions directly. + */ +QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION; +QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, + StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION; +QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, + const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION; +QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, + const UBaseType_t uxInitialCount, + StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION; +BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION; +TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION; + +/* + * For internal use only. Use xSemaphoreTakeMutexRecursive() or + * xSemaphoreGiveMutexRecursive() instead of calling these functions directly. + */ +BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION; + +/* + * Reset a queue back to its original empty state. The return value is now + * obsolete and is always set to pdPASS. + */ +#define xQueueReset( xQueue ) xQueueGenericReset( xQueue, pdFALSE ) + +/* + * The registry is provided as a means for kernel aware debuggers to + * locate queues, semaphores and mutexes. Call vQueueAddToRegistry() add + * a queue, semaphore or mutex handle to the registry if you want the handle + * to be available to a kernel aware debugger. If you are not using a kernel + * aware debugger then this function can be ignored. + * + * configQUEUE_REGISTRY_SIZE defines the maximum number of handles the + * registry can hold. configQUEUE_REGISTRY_SIZE must be greater than 0 + * within FreeRTOSConfig.h for the registry to be available. Its value + * does not effect the number of queues, semaphores and mutexes that can be + * created - just the number that the registry can hold. + * + * @param xQueue The handle of the queue being added to the registry. This + * is the handle returned by a call to xQueueCreate(). Semaphore and mutex + * handles can also be passed in here. + * + * @param pcName The name to be associated with the handle. This is the + * name that the kernel aware debugger will display. The queue registry only + * stores a pointer to the string - so the string must be persistent (global or + * preferably in ROM/Flash), not on the stack. + */ +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + void vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcQueueName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ +#endif + +/* + * The registry is provided as a means for kernel aware debuggers to + * locate queues, semaphores and mutexes. Call vQueueAddToRegistry() add + * a queue, semaphore or mutex handle to the registry if you want the handle + * to be available to a kernel aware debugger, and vQueueUnregisterQueue() to + * remove the queue, semaphore or mutex from the register. If you are not using + * a kernel aware debugger then this function can be ignored. + * + * @param xQueue The handle of the queue being removed from the registry. + */ +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + void vQueueUnregisterQueue( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +#endif + +/* + * The queue registry is provided as a means for kernel aware debuggers to + * locate queues, semaphores and mutexes. Call pcQueueGetName() to look + * up and return the name of a queue in the queue registry from the queue's + * handle. + * + * @param xQueue The handle of the queue the name of which will be returned. + * @return If the queue is in the registry then a pointer to the name of the + * queue is returned. If the queue is not in the registry then NULL is + * returned. + */ +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + const char * pcQueueGetName( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ +#endif + +/* + * Generic version of the function used to create a queue using dynamic memory + * allocation. This is called by other functions and macros that create other + * RTOS objects that use the queue structure as their base. + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + const uint8_t ucQueueType ) PRIVILEGED_FUNCTION; +#endif + +/* + * Generic version of the function used to create a queue using dynamic memory + * allocation. This is called by other functions and macros that create other + * RTOS objects that use the queue structure as their base. + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + uint8_t * pucQueueStorage, + StaticQueue_t * pxStaticQueue, + const uint8_t ucQueueType ) PRIVILEGED_FUNCTION; +#endif + +/* + * Queue sets provide a mechanism to allow a task to block (pend) on a read + * operation from multiple queues or semaphores simultaneously. + * + * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this + * function. + * + * A queue set must be explicitly created using a call to xQueueCreateSet() + * before it can be used. Once created, standard FreeRTOS queues and semaphores + * can be added to the set using calls to xQueueAddToSet(). + * xQueueSelectFromSet() is then used to determine which, if any, of the queues + * or semaphores contained in the set is in a state where a queue read or + * semaphore take operation would be successful. + * + * Note 1: See the documentation on https://www.FreeRTOS.org/RTOS-queue-sets.html + * for reasons why queue sets are very rarely needed in practice as there are + * simpler methods of blocking on multiple objects. + * + * Note 2: Blocking on a queue set that contains a mutex will not cause the + * mutex holder to inherit the priority of the blocked task. + * + * Note 3: An additional 4 bytes of RAM is required for each space in a every + * queue added to a queue set. Therefore counting semaphores that have a high + * maximum count value should not be added to a queue set. + * + * Note 4: A receive (in the case of a queue) or take (in the case of a + * semaphore) operation must not be performed on a member of a queue set unless + * a call to xQueueSelectFromSet() has first returned a handle to that set member. + * + * @param uxEventQueueLength Queue sets store events that occur on + * the queues and semaphores contained in the set. uxEventQueueLength specifies + * the maximum number of events that can be queued at once. To be absolutely + * certain that events are not lost uxEventQueueLength should be set to the + * total sum of the length of the queues added to the set, where binary + * semaphores and mutexes have a length of 1, and counting semaphores have a + * length set by their maximum count value. Examples: + * + If a queue set is to hold a queue of length 5, another queue of length 12, + * and a binary semaphore, then uxEventQueueLength should be set to + * (5 + 12 + 1), or 18. + * + If a queue set is to hold three binary semaphores then uxEventQueueLength + * should be set to (1 + 1 + 1 ), or 3. + * + If a queue set is to hold a counting semaphore that has a maximum count of + * 5, and a counting semaphore that has a maximum count of 3, then + * uxEventQueueLength should be set to (5 + 3), or 8. + * + * @return If the queue set is created successfully then a handle to the created + * queue set is returned. Otherwise NULL is returned. + */ +QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION; + +/* + * Adds a queue or semaphore to a queue set that was previously created by a + * call to xQueueCreateSet(). + * + * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this + * function. + * + * Note 1: A receive (in the case of a queue) or take (in the case of a + * semaphore) operation must not be performed on a member of a queue set unless + * a call to xQueueSelectFromSet() has first returned a handle to that set member. + * + * @param xQueueOrSemaphore The handle of the queue or semaphore being added to + * the queue set (cast to an QueueSetMemberHandle_t type). + * + * @param xQueueSet The handle of the queue set to which the queue or semaphore + * is being added. + * + * @return If the queue or semaphore was successfully added to the queue set + * then pdPASS is returned. If the queue could not be successfully added to the + * queue set because it is already a member of a different queue set then pdFAIL + * is returned. + */ +BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION; + +/* + * Removes a queue or semaphore from a queue set. A queue or semaphore can only + * be removed from a set if the queue or semaphore is empty. + * + * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this + * function. + * + * @param xQueueOrSemaphore The handle of the queue or semaphore being removed + * from the queue set (cast to an QueueSetMemberHandle_t type). + * + * @param xQueueSet The handle of the queue set in which the queue or semaphore + * is included. + * + * @return If the queue or semaphore was successfully removed from the queue set + * then pdPASS is returned. If the queue was not in the queue set, or the + * queue (or semaphore) was not empty, then pdFAIL is returned. + */ +BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION; + +/* + * xQueueSelectFromSet() selects from the members of a queue set a queue or + * semaphore that either contains data (in the case of a queue) or is available + * to take (in the case of a semaphore). xQueueSelectFromSet() effectively + * allows a task to block (pend) on a read operation on all the queues and + * semaphores in a queue set simultaneously. + * + * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this + * function. + * + * Note 1: See the documentation on https://www.FreeRTOS.org/RTOS-queue-sets.html + * for reasons why queue sets are very rarely needed in practice as there are + * simpler methods of blocking on multiple objects. + * + * Note 2: Blocking on a queue set that contains a mutex will not cause the + * mutex holder to inherit the priority of the blocked task. + * + * Note 3: A receive (in the case of a queue) or take (in the case of a + * semaphore) operation must not be performed on a member of a queue set unless + * a call to xQueueSelectFromSet() has first returned a handle to that set member. + * + * @param xQueueSet The queue set on which the task will (potentially) block. + * + * @param xTicksToWait The maximum time, in ticks, that the calling task will + * remain in the Blocked state (with other tasks executing) to wait for a member + * of the queue set to be ready for a successful queue read or semaphore take + * operation. + * + * @return xQueueSelectFromSet() will return the handle of a queue (cast to + * a QueueSetMemberHandle_t type) contained in the queue set that contains data, + * or the handle of a semaphore (cast to a QueueSetMemberHandle_t type) contained + * in the queue set that is available, or NULL if no such queue or semaphore + * exists before before the specified block time expires. + */ +QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/* + * A version of xQueueSelectFromSet() that can be used from an ISR. + */ +QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION; + +/* Not public API functions. */ +void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, + TickType_t xTicksToWait, + const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION; +BaseType_t xQueueGenericReset( QueueHandle_t xQueue, + BaseType_t xNewQueue ) PRIVILEGED_FUNCTION; +void vQueueSetQueueNumber( QueueHandle_t xQueue, + UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION; +UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; +uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; + + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ + +#endif /* QUEUE_H */ diff --git a/MODULES/FreeRTOS/inc/semphr.h b/MODULES/FreeRTOS/inc/semphr.h new file mode 100644 index 0000000..a3b1ab4 --- /dev/null +++ b/MODULES/FreeRTOS/inc/semphr.h @@ -0,0 +1,1173 @@ +/* + * FreeRTOS Kernel V10.4.3 LTS Patch 2 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef SEMAPHORE_H +#define SEMAPHORE_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h" must appear in source files before "include semphr.h" +#endif + +#include "queue.h" + +typedef QueueHandle_t SemaphoreHandle_t; + +#define semBINARY_SEMAPHORE_QUEUE_LENGTH ( ( uint8_t ) 1U ) +#define semSEMAPHORE_QUEUE_ITEM_LENGTH ( ( uint8_t ) 0U ) +#define semGIVE_BLOCK_TIME ( ( TickType_t ) 0U ) + + +/** + * semphr. h + * 
+ * vSemaphoreCreateBinary( SemaphoreHandle_t xSemaphore );
+ *
+ * + * In many usage scenarios it is faster and more memory efficient to use a + * direct to task notification in place of a binary semaphore! + * https://www.FreeRTOS.org/RTOS-task-notifications.html + * + * This old vSemaphoreCreateBinary() macro is now deprecated in favour of the + * xSemaphoreCreateBinary() function. Note that binary semaphores created using + * the vSemaphoreCreateBinary() macro are created in a state such that the + * first call to 'take' the semaphore would pass, whereas binary semaphores + * created using xSemaphoreCreateBinary() are created in a state such that the + * the semaphore must first be 'given' before it can be 'taken'. + * + * Macro that implements a semaphore by using the existing queue mechanism. + * The queue length is 1 as this is a binary semaphore. The data size is 0 + * as we don't want to actually store any data - we just want to know if the + * queue is empty or full. + * + * This type of semaphore can be used for pure synchronisation between tasks or + * between an interrupt and a task. The semaphore need not be given back once + * obtained, so one task/interrupt can continuously 'give' the semaphore while + * another continuously 'takes' the semaphore. For this reason this type of + * semaphore does not use a priority inheritance mechanism. For an alternative + * that does use priority inheritance see xSemaphoreCreateMutex(). + * + * @param xSemaphore Handle to the created semaphore. Should be of type SemaphoreHandle_t. + * + * Example usage: + * 
+ * SemaphoreHandle_t xSemaphore = NULL;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ *  // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().
+ *  // This is a macro so pass the variable in directly.
+ *  vSemaphoreCreateBinary( xSemaphore );
+ *
+ *  if( xSemaphore != NULL )
+ *  {
+ *      // The semaphore was created successfully.
+ *      // The semaphore can now be used.
+ *  }
+ * }
+ *
+ * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary + * \ingroup Semaphores + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + #define vSemaphoreCreateBinary( xSemaphore ) \ + { \ + ( xSemaphore ) = xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE ); \ + if( ( xSemaphore ) != NULL ) \ + { \ + ( void ) xSemaphoreGive( ( xSemaphore ) ); \ + } \ + } +#endif + +/** + * semphr. h + * 
+ * SemaphoreHandle_t xSemaphoreCreateBinary( void );
+ *
+ * + * Creates a new binary semaphore instance, and returns a handle by which the + * new semaphore can be referenced. + * + * In many usage scenarios it is faster and more memory efficient to use a + * direct to task notification in place of a binary semaphore! + * https://www.FreeRTOS.org/RTOS-task-notifications.html + * + * Internally, within the FreeRTOS implementation, binary semaphores use a block + * of memory, in which the semaphore structure is stored. If a binary semaphore + * is created using xSemaphoreCreateBinary() then the required memory is + * automatically dynamically allocated inside the xSemaphoreCreateBinary() + * function. (see https://www.FreeRTOS.org/a00111.html). If a binary semaphore + * is created using xSemaphoreCreateBinaryStatic() then the application writer + * must provide the memory. xSemaphoreCreateBinaryStatic() therefore allows a + * binary semaphore to be created without using any dynamic memory allocation. + * + * The old vSemaphoreCreateBinary() macro is now deprecated in favour of this + * xSemaphoreCreateBinary() function. Note that binary semaphores created using + * the vSemaphoreCreateBinary() macro are created in a state such that the + * first call to 'take' the semaphore would pass, whereas binary semaphores + * created using xSemaphoreCreateBinary() are created in a state such that the + * the semaphore must first be 'given' before it can be 'taken'. + * + * This type of semaphore can be used for pure synchronisation between tasks or + * between an interrupt and a task. The semaphore need not be given back once + * obtained, so one task/interrupt can continuously 'give' the semaphore while + * another continuously 'takes' the semaphore. For this reason this type of + * semaphore does not use a priority inheritance mechanism. For an alternative + * that does use priority inheritance see xSemaphoreCreateMutex(). + * + * @return Handle to the created semaphore, or NULL if the memory required to + * hold the semaphore's data structures could not be allocated. + * + * Example usage: + * 
+ * SemaphoreHandle_t xSemaphore = NULL;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ *  // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
+ *  // This is a macro so pass the variable in directly.
+ *  xSemaphore = xSemaphoreCreateBinary();
+ *
+ *  if( xSemaphore != NULL )
+ *  {
+ *      // The semaphore was created successfully.
+ *      // The semaphore can now be used.
+ *  }
+ * }
+ *
+ * \defgroup xSemaphoreCreateBinary xSemaphoreCreateBinary + * \ingroup Semaphores + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + #define xSemaphoreCreateBinary() xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE ) +#endif + +/** + * semphr. h + * 
+ * SemaphoreHandle_t xSemaphoreCreateBinaryStatic( StaticSemaphore_t *pxSemaphoreBuffer );
+ *
+ * + * Creates a new binary semaphore instance, and returns a handle by which the + * new semaphore can be referenced. + * + * NOTE: In many usage scenarios it is faster and more memory efficient to use a + * direct to task notification in place of a binary semaphore! + * https://www.FreeRTOS.org/RTOS-task-notifications.html + * + * Internally, within the FreeRTOS implementation, binary semaphores use a block + * of memory, in which the semaphore structure is stored. If a binary semaphore + * is created using xSemaphoreCreateBinary() then the required memory is + * automatically dynamically allocated inside the xSemaphoreCreateBinary() + * function. (see https://www.FreeRTOS.org/a00111.html). If a binary semaphore + * is created using xSemaphoreCreateBinaryStatic() then the application writer + * must provide the memory. xSemaphoreCreateBinaryStatic() therefore allows a + * binary semaphore to be created without using any dynamic memory allocation. + * + * This type of semaphore can be used for pure synchronisation between tasks or + * between an interrupt and a task. The semaphore need not be given back once + * obtained, so one task/interrupt can continuously 'give' the semaphore while + * another continuously 'takes' the semaphore. For this reason this type of + * semaphore does not use a priority inheritance mechanism. For an alternative + * that does use priority inheritance see xSemaphoreCreateMutex(). + * + * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t, + * which will then be used to hold the semaphore's data structure, removing the + * need for the memory to be allocated dynamically. + * + * @return If the semaphore is created then a handle to the created semaphore is + * returned. If pxSemaphoreBuffer is NULL then NULL is returned. + * + * Example usage: + * 
+ * SemaphoreHandle_t xSemaphore = NULL;
+ * StaticSemaphore_t xSemaphoreBuffer;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ *  // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
+ *  // The semaphore's data structures will be placed in the xSemaphoreBuffer
+ *  // variable, the address of which is passed into the function.  The
+ *  // function's parameter is not NULL, so the function will not attempt any
+ *  // dynamic memory allocation, and therefore the function will not return
+ *  // return NULL.
+ *  xSemaphore = xSemaphoreCreateBinary( &xSemaphoreBuffer );
+ *
+ *  // Rest of task code goes here.
+ * }
+ *
+ * \defgroup xSemaphoreCreateBinaryStatic xSemaphoreCreateBinaryStatic + * \ingroup Semaphores + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + #define xSemaphoreCreateBinaryStatic( pxStaticSemaphore ) xQueueGenericCreateStatic( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticSemaphore, queueQUEUE_TYPE_BINARY_SEMAPHORE ) +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/** + * semphr. h + * 
+ * xSemaphoreTake(
+ *                   SemaphoreHandle_t xSemaphore,
+ *                   TickType_t xBlockTime
+ *               );
+ *
+ * + * Macro to obtain a semaphore. The semaphore must have previously been + * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or + * xSemaphoreCreateCounting(). + * + * @param xSemaphore A handle to the semaphore being taken - obtained when + * the semaphore was created. + * + * @param xBlockTime The time in ticks to wait for the semaphore to become + * available. The macro portTICK_PERIOD_MS can be used to convert this to a + * real time. A block time of zero can be used to poll the semaphore. A block + * time of portMAX_DELAY can be used to block indefinitely (provided + * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h). + * + * @return pdTRUE if the semaphore was obtained. pdFALSE + * if xBlockTime expired without the semaphore becoming available. + * + * Example usage: + * 
+ * SemaphoreHandle_t xSemaphore = NULL;
+ *
+ * // A task that creates a semaphore.
+ * void vATask( void * pvParameters )
+ * {
+ *  // Create the semaphore to guard a shared resource.
+ *  xSemaphore = xSemaphoreCreateBinary();
+ * }
+ *
+ * // A task that uses the semaphore.
+ * void vAnotherTask( void * pvParameters )
+ * {
+ *  // ... Do other things.
+ *
+ *  if( xSemaphore != NULL )
+ *  {
+ *      // See if we can obtain the semaphore.  If the semaphore is not available
+ *      // wait 10 ticks to see if it becomes free.
+ *      if( xSemaphoreTake( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+ *      {
+ *          // We were able to obtain the semaphore and can now access the
+ *          // shared resource.
+ *
+ *          // ...
+ *
+ *          // We have finished accessing the shared resource.  Release the
+ *          // semaphore.
+ *          xSemaphoreGive( xSemaphore );
+ *      }
+ *      else
+ *      {
+ *          // We could not obtain the semaphore and can therefore not access
+ *          // the shared resource safely.
+ *      }
+ *  }
+ * }
+ *
+ * \defgroup xSemaphoreTake xSemaphoreTake + * \ingroup Semaphores + */ +#define xSemaphoreTake( xSemaphore, xBlockTime ) xQueueSemaphoreTake( ( xSemaphore ), ( xBlockTime ) ) + +/** + * semphr. h + * 
+ * xSemaphoreTakeRecursive(
+ *                          SemaphoreHandle_t xMutex,
+ *                          TickType_t xBlockTime
+ *                        );
+ *
+ * + * Macro to recursively obtain, or 'take', a mutex type semaphore. + * The mutex must have previously been created using a call to + * xSemaphoreCreateRecursiveMutex(); + * + * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this + * macro to be available. + * + * This macro must not be used on mutexes created using xSemaphoreCreateMutex(). + * + * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex + * doesn't become available again until the owner has called + * xSemaphoreGiveRecursive() for each successful 'take' request. For example, + * if a task successfully 'takes' the same mutex 5 times then the mutex will + * not be available to any other task until it has also 'given' the mutex back + * exactly five times. + * + * @param xMutex A handle to the mutex being obtained. This is the + * handle returned by xSemaphoreCreateRecursiveMutex(); + * + * @param xBlockTime The time in ticks to wait for the semaphore to become + * available. The macro portTICK_PERIOD_MS can be used to convert this to a + * real time. A block time of zero can be used to poll the semaphore. If + * the task already owns the semaphore then xSemaphoreTakeRecursive() will + * return immediately no matter what the value of xBlockTime. + * + * @return pdTRUE if the semaphore was obtained. pdFALSE if xBlockTime + * expired without the semaphore becoming available. + * + * Example usage: + * 
+ * SemaphoreHandle_t xMutex = NULL;
+ *
+ * // A task that creates a mutex.
+ * void vATask( void * pvParameters )
+ * {
+ *  // Create the mutex to guard a shared resource.
+ *  xMutex = xSemaphoreCreateRecursiveMutex();
+ * }
+ *
+ * // A task that uses the mutex.
+ * void vAnotherTask( void * pvParameters )
+ * {
+ *  // ... Do other things.
+ *
+ *  if( xMutex != NULL )
+ *  {
+ *      // See if we can obtain the mutex.  If the mutex is not available
+ *      // wait 10 ticks to see if it becomes free.
+ *      if( xSemaphoreTakeRecursive( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+ *      {
+ *          // We were able to obtain the mutex and can now access the
+ *          // shared resource.
+ *
+ *          // ...
+ *          // For some reason due to the nature of the code further calls to
+ *          // xSemaphoreTakeRecursive() are made on the same mutex.  In real
+ *          // code these would not be just sequential calls as this would make
+ *          // no sense.  Instead the calls are likely to be buried inside
+ *          // a more complex call structure.
+ *          xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+ *          xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+ *
+ *          // The mutex has now been 'taken' three times, so will not be
+ *          // available to another task until it has also been given back
+ *          // three times.  Again it is unlikely that real code would have
+ *          // these calls sequentially, but instead buried in a more complex
+ *          // call structure.  This is just for illustrative purposes.
+ *          xSemaphoreGiveRecursive( xMutex );
+ *          xSemaphoreGiveRecursive( xMutex );
+ *          xSemaphoreGiveRecursive( xMutex );
+ *
+ *          // Now the mutex can be taken by other tasks.
+ *      }
+ *      else
+ *      {
+ *          // We could not obtain the mutex and can therefore not access
+ *          // the shared resource safely.
+ *      }
+ *  }
+ * }
+ *
+ * \defgroup xSemaphoreTakeRecursive xSemaphoreTakeRecursive + * \ingroup Semaphores + */ +#if ( configUSE_RECURSIVE_MUTEXES == 1 ) + #define xSemaphoreTakeRecursive( xMutex, xBlockTime ) xQueueTakeMutexRecursive( ( xMutex ), ( xBlockTime ) ) +#endif + +/** + * semphr. h + * 
+ * xSemaphoreGive( SemaphoreHandle_t xSemaphore );
+ *
+ * + * Macro to release a semaphore. The semaphore must have previously been + * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or + * xSemaphoreCreateCounting(). and obtained using sSemaphoreTake(). + * + * This macro must not be used from an ISR. See xSemaphoreGiveFromISR () for + * an alternative which can be used from an ISR. + * + * This macro must also not be used on semaphores created using + * xSemaphoreCreateRecursiveMutex(). + * + * @param xSemaphore A handle to the semaphore being released. This is the + * handle returned when the semaphore was created. + * + * @return pdTRUE if the semaphore was released. pdFALSE if an error occurred. + * Semaphores are implemented using queues. An error can occur if there is + * no space on the queue to post a message - indicating that the + * semaphore was not first obtained correctly. + * + * Example usage: + * 
+ * SemaphoreHandle_t xSemaphore = NULL;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ *  // Create the semaphore to guard a shared resource.
+ *  xSemaphore = vSemaphoreCreateBinary();
+ *
+ *  if( xSemaphore != NULL )
+ *  {
+ *      if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+ *      {
+ *          // We would expect this call to fail because we cannot give
+ *          // a semaphore without first "taking" it!
+ *      }
+ *
+ *      // Obtain the semaphore - don't block if the semaphore is not
+ *      // immediately available.
+ *      if( xSemaphoreTake( xSemaphore, ( TickType_t ) 0 ) )
+ *      {
+ *          // We now have the semaphore and can access the shared resource.
+ *
+ *          // ...
+ *
+ *          // We have finished accessing the shared resource so can free the
+ *          // semaphore.
+ *          if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+ *          {
+ *              // We would not expect this call to fail because we must have
+ *              // obtained the semaphore to get here.
+ *          }
+ *      }
+ *  }
+ * }
+ *
+ * \defgroup xSemaphoreGive xSemaphoreGive + * \ingroup Semaphores + */ +#define xSemaphoreGive( xSemaphore ) xQueueGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK ) + +/** + * semphr. h + * 
+ * xSemaphoreGiveRecursive( SemaphoreHandle_t xMutex );
+ *
+ * + * Macro to recursively release, or 'give', a mutex type semaphore. + * The mutex must have previously been created using a call to + * xSemaphoreCreateRecursiveMutex(); + * + * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this + * macro to be available. + * + * This macro must not be used on mutexes created using xSemaphoreCreateMutex(). + * + * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex + * doesn't become available again until the owner has called + * xSemaphoreGiveRecursive() for each successful 'take' request. For example, + * if a task successfully 'takes' the same mutex 5 times then the mutex will + * not be available to any other task until it has also 'given' the mutex back + * exactly five times. + * + * @param xMutex A handle to the mutex being released, or 'given'. This is the + * handle returned by xSemaphoreCreateMutex(); + * + * @return pdTRUE if the semaphore was given. + * + * Example usage: + * 
+ * SemaphoreHandle_t xMutex = NULL;
+ *
+ * // A task that creates a mutex.
+ * void vATask( void * pvParameters )
+ * {
+ *  // Create the mutex to guard a shared resource.
+ *  xMutex = xSemaphoreCreateRecursiveMutex();
+ * }
+ *
+ * // A task that uses the mutex.
+ * void vAnotherTask( void * pvParameters )
+ * {
+ *  // ... Do other things.
+ *
+ *  if( xMutex != NULL )
+ *  {
+ *      // See if we can obtain the mutex.  If the mutex is not available
+ *      // wait 10 ticks to see if it becomes free.
+ *      if( xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ) == pdTRUE )
+ *      {
+ *          // We were able to obtain the mutex and can now access the
+ *          // shared resource.
+ *
+ *          // ...
+ *          // For some reason due to the nature of the code further calls to
+ *          // xSemaphoreTakeRecursive() are made on the same mutex.  In real
+ *          // code these would not be just sequential calls as this would make
+ *          // no sense.  Instead the calls are likely to be buried inside
+ *          // a more complex call structure.
+ *          xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+ *          xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+ *
+ *          // The mutex has now been 'taken' three times, so will not be
+ *          // available to another task until it has also been given back
+ *          // three times.  Again it is unlikely that real code would have
+ *          // these calls sequentially, it would be more likely that the calls
+ *          // to xSemaphoreGiveRecursive() would be called as a call stack
+ *          // unwound.  This is just for demonstrative purposes.
+ *          xSemaphoreGiveRecursive( xMutex );
+ *          xSemaphoreGiveRecursive( xMutex );
+ *          xSemaphoreGiveRecursive( xMutex );
+ *
+ *          // Now the mutex can be taken by other tasks.
+ *      }
+ *      else
+ *      {
+ *          // We could not obtain the mutex and can therefore not access
+ *          // the shared resource safely.
+ *      }
+ *  }
+ * }
+ *
+ * \defgroup xSemaphoreGiveRecursive xSemaphoreGiveRecursive + * \ingroup Semaphores + */ +#if ( configUSE_RECURSIVE_MUTEXES == 1 ) + #define xSemaphoreGiveRecursive( xMutex ) xQueueGiveMutexRecursive( ( xMutex ) ) +#endif + +/** + * semphr. h + * 
+ * xSemaphoreGiveFromISR(
+ *                        SemaphoreHandle_t xSemaphore,
+ *                        BaseType_t *pxHigherPriorityTaskWoken
+ *                    );
+ *
+ * + * Macro to release a semaphore. The semaphore must have previously been + * created with a call to xSemaphoreCreateBinary() or xSemaphoreCreateCounting(). + * + * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex()) + * must not be used with this macro. + * + * This macro can be used from an ISR. + * + * @param xSemaphore A handle to the semaphore being released. This is the + * handle returned when the semaphore was created. + * + * @param pxHigherPriorityTaskWoken xSemaphoreGiveFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if giving the semaphore caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xSemaphoreGiveFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return pdTRUE if the semaphore was successfully given, otherwise errQUEUE_FULL. + * + * Example usage: + * 
+ \#define LONG_TIME 0xffff
+ \#define TICKS_TO_WAIT 10
+ * SemaphoreHandle_t xSemaphore = NULL;
+ *
+ * // Repetitive task.
+ * void vATask( void * pvParameters )
+ * {
+ *  for( ;; )
+ *  {
+ *      // We want this task to run every 10 ticks of a timer.  The semaphore
+ *      // was created before this task was started.
+ *
+ *      // Block waiting for the semaphore to become available.
+ *      if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )
+ *      {
+ *          // It is time to execute.
+ *
+ *          // ...
+ *
+ *          // We have finished our task.  Return to the top of the loop where
+ *          // we will block on the semaphore until it is time to execute
+ *          // again.  Note when using the semaphore for synchronisation with an
+ *          // ISR in this manner there is no need to 'give' the semaphore back.
+ *      }
+ *  }
+ * }
+ *
+ * // Timer ISR
+ * void vTimerISR( void * pvParameters )
+ * {
+ * static uint8_t ucLocalTickCount = 0;
+ * static BaseType_t xHigherPriorityTaskWoken;
+ *
+ *  // A timer tick has occurred.
+ *
+ *  // ... Do other time functions.
+ *
+ *  // Is it time for vATask () to run?
+ *  xHigherPriorityTaskWoken = pdFALSE;
+ *  ucLocalTickCount++;
+ *  if( ucLocalTickCount >= TICKS_TO_WAIT )
+ *  {
+ *      // Unblock the task by releasing the semaphore.
+ *      xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken );
+ *
+ *      // Reset the count so we release the semaphore again in 10 ticks time.
+ *      ucLocalTickCount = 0;
+ *  }
+ *
+ *  if( xHigherPriorityTaskWoken != pdFALSE )
+ *  {
+ *      // We can force a context switch here.  Context switching from an
+ *      // ISR uses port specific syntax.  Check the demo task for your port
+ *      // to find the syntax required.
+ *  }
+ * }
+ *
+ * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR + * \ingroup Semaphores + */ +#define xSemaphoreGiveFromISR( xSemaphore, pxHigherPriorityTaskWoken ) xQueueGiveFromISR( ( QueueHandle_t ) ( xSemaphore ), ( pxHigherPriorityTaskWoken ) ) + +/** + * semphr. h + * 
+ * xSemaphoreTakeFromISR(
+ *                        SemaphoreHandle_t xSemaphore,
+ *                        BaseType_t *pxHigherPriorityTaskWoken
+ *                    );
+ *
+ * + * Macro to take a semaphore from an ISR. The semaphore must have + * previously been created with a call to xSemaphoreCreateBinary() or + * xSemaphoreCreateCounting(). + * + * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex()) + * must not be used with this macro. + * + * This macro can be used from an ISR, however taking a semaphore from an ISR + * is not a common operation. It is likely to only be useful when taking a + * counting semaphore when an interrupt is obtaining an object from a resource + * pool (when the semaphore count indicates the number of resources available). + * + * @param xSemaphore A handle to the semaphore being taken. This is the + * handle returned when the semaphore was created. + * + * @param pxHigherPriorityTaskWoken xSemaphoreTakeFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if taking the semaphore caused a task + * to unblock, and the unblocked task has a priority higher than the currently + * running task. If xSemaphoreTakeFromISR() sets this value to pdTRUE then + * a context switch should be requested before the interrupt is exited. + * + * @return pdTRUE if the semaphore was successfully taken, otherwise + * pdFALSE + */ +#define xSemaphoreTakeFromISR( xSemaphore, pxHigherPriorityTaskWoken ) xQueueReceiveFromISR( ( QueueHandle_t ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ) ) + +/** + * semphr. h + * 
+ * SemaphoreHandle_t xSemaphoreCreateMutex( void );
+ *
+ * + * Creates a new mutex type semaphore instance, and returns a handle by which + * the new mutex can be referenced. + * + * Internally, within the FreeRTOS implementation, mutex semaphores use a block + * of memory, in which the mutex structure is stored. If a mutex is created + * using xSemaphoreCreateMutex() then the required memory is automatically + * dynamically allocated inside the xSemaphoreCreateMutex() function. (see + * https://www.FreeRTOS.org/a00111.html). If a mutex is created using + * xSemaphoreCreateMutexStatic() then the application writer must provided the + * memory. xSemaphoreCreateMutexStatic() therefore allows a mutex to be created + * without using any dynamic memory allocation. + * + * Mutexes created using this function can be accessed using the xSemaphoreTake() + * and xSemaphoreGive() macros. The xSemaphoreTakeRecursive() and + * xSemaphoreGiveRecursive() macros must not be used. + * + * This type of semaphore uses a priority inheritance mechanism so a task + * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the + * semaphore it is no longer required. + * + * Mutex type semaphores cannot be used from within interrupt service routines. + * + * See xSemaphoreCreateBinary() for an alternative implementation that can be + * used for pure synchronisation (where one task or interrupt always 'gives' the + * semaphore and another always 'takes' the semaphore) and from within interrupt + * service routines. + * + * @return If the mutex was successfully created then a handle to the created + * semaphore is returned. If there was not enough heap to allocate the mutex + * data structures then NULL is returned. + * + * Example usage: + * 
+ * SemaphoreHandle_t xSemaphore;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ *  // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+ *  // This is a macro so pass the variable in directly.
+ *  xSemaphore = xSemaphoreCreateMutex();
+ *
+ *  if( xSemaphore != NULL )
+ *  {
+ *      // The semaphore was created successfully.
+ *      // The semaphore can now be used.
+ *  }
+ * }
+ *
+ * \defgroup xSemaphoreCreateMutex xSemaphoreCreateMutex + * \ingroup Semaphores + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + #define xSemaphoreCreateMutex() xQueueCreateMutex( queueQUEUE_TYPE_MUTEX ) +#endif + +/** + * semphr. h + * 
+ * SemaphoreHandle_t xSemaphoreCreateMutexStatic( StaticSemaphore_t *pxMutexBuffer );
+ *
+ * + * Creates a new mutex type semaphore instance, and returns a handle by which + * the new mutex can be referenced. + * + * Internally, within the FreeRTOS implementation, mutex semaphores use a block + * of memory, in which the mutex structure is stored. If a mutex is created + * using xSemaphoreCreateMutex() then the required memory is automatically + * dynamically allocated inside the xSemaphoreCreateMutex() function. (see + * https://www.FreeRTOS.org/a00111.html). If a mutex is created using + * xSemaphoreCreateMutexStatic() then the application writer must provided the + * memory. xSemaphoreCreateMutexStatic() therefore allows a mutex to be created + * without using any dynamic memory allocation. + * + * Mutexes created using this function can be accessed using the xSemaphoreTake() + * and xSemaphoreGive() macros. The xSemaphoreTakeRecursive() and + * xSemaphoreGiveRecursive() macros must not be used. + * + * This type of semaphore uses a priority inheritance mechanism so a task + * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the + * semaphore it is no longer required. + * + * Mutex type semaphores cannot be used from within interrupt service routines. + * + * See xSemaphoreCreateBinary() for an alternative implementation that can be + * used for pure synchronisation (where one task or interrupt always 'gives' the + * semaphore and another always 'takes' the semaphore) and from within interrupt + * service routines. + * + * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t, + * which will be used to hold the mutex's data structure, removing the need for + * the memory to be allocated dynamically. + * + * @return If the mutex was successfully created then a handle to the created + * mutex is returned. If pxMutexBuffer was NULL then NULL is returned. + * + * Example usage: + * 
+ * SemaphoreHandle_t xSemaphore;
+ * StaticSemaphore_t xMutexBuffer;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ *  // A mutex cannot be used before it has been created.  xMutexBuffer is
+ *  // into xSemaphoreCreateMutexStatic() so no dynamic memory allocation is
+ *  // attempted.
+ *  xSemaphore = xSemaphoreCreateMutexStatic( &xMutexBuffer );
+ *
+ *  // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
+ *  // so there is no need to check it.
+ * }
+ *
+ * \defgroup xSemaphoreCreateMutexStatic xSemaphoreCreateMutexStatic + * \ingroup Semaphores + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + #define xSemaphoreCreateMutexStatic( pxMutexBuffer ) xQueueCreateMutexStatic( queueQUEUE_TYPE_MUTEX, ( pxMutexBuffer ) ) +#endif /* configSUPPORT_STATIC_ALLOCATION */ + + +/** + * semphr. h + * 
+ * SemaphoreHandle_t xSemaphoreCreateRecursiveMutex( void );
+ *
+ * + * Creates a new recursive mutex type semaphore instance, and returns a handle + * by which the new recursive mutex can be referenced. + * + * Internally, within the FreeRTOS implementation, recursive mutexs use a block + * of memory, in which the mutex structure is stored. If a recursive mutex is + * created using xSemaphoreCreateRecursiveMutex() then the required memory is + * automatically dynamically allocated inside the + * xSemaphoreCreateRecursiveMutex() function. (see + * https://www.FreeRTOS.org/a00111.html). If a recursive mutex is created using + * xSemaphoreCreateRecursiveMutexStatic() then the application writer must + * provide the memory that will get used by the mutex. + * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to + * be created without using any dynamic memory allocation. + * + * Mutexes created using this macro can be accessed using the + * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros. The + * xSemaphoreTake() and xSemaphoreGive() macros must not be used. + * + * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex + * doesn't become available again until the owner has called + * xSemaphoreGiveRecursive() for each successful 'take' request. For example, + * if a task successfully 'takes' the same mutex 5 times then the mutex will + * not be available to any other task until it has also 'given' the mutex back + * exactly five times. + * + * This type of semaphore uses a priority inheritance mechanism so a task + * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the + * semaphore it is no longer required. + * + * Mutex type semaphores cannot be used from within interrupt service routines. + * + * See xSemaphoreCreateBinary() for an alternative implementation that can be + * used for pure synchronisation (where one task or interrupt always 'gives' the + * semaphore and another always 'takes' the semaphore) and from within interrupt + * service routines. + * + * @return xSemaphore Handle to the created mutex semaphore. Should be of type + * SemaphoreHandle_t. + * + * Example usage: + * 
+ * SemaphoreHandle_t xSemaphore;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ *  // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+ *  // This is a macro so pass the variable in directly.
+ *  xSemaphore = xSemaphoreCreateRecursiveMutex();
+ *
+ *  if( xSemaphore != NULL )
+ *  {
+ *      // The semaphore was created successfully.
+ *      // The semaphore can now be used.
+ *  }
+ * }
+ *
+ * \defgroup xSemaphoreCreateRecursiveMutex xSemaphoreCreateRecursiveMutex + * \ingroup Semaphores + */ +#if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) ) + #define xSemaphoreCreateRecursiveMutex() xQueueCreateMutex( queueQUEUE_TYPE_RECURSIVE_MUTEX ) +#endif + +/** + * semphr. h + * 
+ * SemaphoreHandle_t xSemaphoreCreateRecursiveMutexStatic( StaticSemaphore_t *pxMutexBuffer );
+ *
+ * + * Creates a new recursive mutex type semaphore instance, and returns a handle + * by which the new recursive mutex can be referenced. + * + * Internally, within the FreeRTOS implementation, recursive mutexs use a block + * of memory, in which the mutex structure is stored. If a recursive mutex is + * created using xSemaphoreCreateRecursiveMutex() then the required memory is + * automatically dynamically allocated inside the + * xSemaphoreCreateRecursiveMutex() function. (see + * https://www.FreeRTOS.org/a00111.html). If a recursive mutex is created using + * xSemaphoreCreateRecursiveMutexStatic() then the application writer must + * provide the memory that will get used by the mutex. + * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to + * be created without using any dynamic memory allocation. + * + * Mutexes created using this macro can be accessed using the + * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros. The + * xSemaphoreTake() and xSemaphoreGive() macros must not be used. + * + * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex + * doesn't become available again until the owner has called + * xSemaphoreGiveRecursive() for each successful 'take' request. For example, + * if a task successfully 'takes' the same mutex 5 times then the mutex will + * not be available to any other task until it has also 'given' the mutex back + * exactly five times. + * + * This type of semaphore uses a priority inheritance mechanism so a task + * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the + * semaphore it is no longer required. + * + * Mutex type semaphores cannot be used from within interrupt service routines. + * + * See xSemaphoreCreateBinary() for an alternative implementation that can be + * used for pure synchronisation (where one task or interrupt always 'gives' the + * semaphore and another always 'takes' the semaphore) and from within interrupt + * service routines. + * + * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t, + * which will then be used to hold the recursive mutex's data structure, + * removing the need for the memory to be allocated dynamically. + * + * @return If the recursive mutex was successfully created then a handle to the + * created recursive mutex is returned. If pxMutexBuffer was NULL then NULL is + * returned. + * + * Example usage: + * 
+ * SemaphoreHandle_t xSemaphore;
+ * StaticSemaphore_t xMutexBuffer;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ *  // A recursive semaphore cannot be used before it is created.  Here a
+ *  // recursive mutex is created using xSemaphoreCreateRecursiveMutexStatic().
+ *  // The address of xMutexBuffer is passed into the function, and will hold
+ *  // the mutexes data structures - so no dynamic memory allocation will be
+ *  // attempted.
+ *  xSemaphore = xSemaphoreCreateRecursiveMutexStatic( &xMutexBuffer );
+ *
+ *  // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
+ *  // so there is no need to check it.
+ * }
+ *
+ * \defgroup xSemaphoreCreateRecursiveMutexStatic xSemaphoreCreateRecursiveMutexStatic + * \ingroup Semaphores + */ +#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) ) + #define xSemaphoreCreateRecursiveMutexStatic( pxStaticSemaphore ) xQueueCreateMutexStatic( queueQUEUE_TYPE_RECURSIVE_MUTEX, pxStaticSemaphore ) +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/** + * semphr. h + * 
+ * SemaphoreHandle_t xSemaphoreCreateCounting( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount );
+ *
+ * + * Creates a new counting semaphore instance, and returns a handle by which the + * new counting semaphore can be referenced. + * + * In many usage scenarios it is faster and more memory efficient to use a + * direct to task notification in place of a counting semaphore! + * https://www.FreeRTOS.org/RTOS-task-notifications.html + * + * Internally, within the FreeRTOS implementation, counting semaphores use a + * block of memory, in which the counting semaphore structure is stored. If a + * counting semaphore is created using xSemaphoreCreateCounting() then the + * required memory is automatically dynamically allocated inside the + * xSemaphoreCreateCounting() function. (see + * https://www.FreeRTOS.org/a00111.html). If a counting semaphore is created + * using xSemaphoreCreateCountingStatic() then the application writer can + * instead optionally provide the memory that will get used by the counting + * semaphore. xSemaphoreCreateCountingStatic() therefore allows a counting + * semaphore to be created without using any dynamic memory allocation. + * + * Counting semaphores are typically used for two things: + * + * 1) Counting events. + * + * In this usage scenario an event handler will 'give' a semaphore each time + * an event occurs (incrementing the semaphore count value), and a handler + * task will 'take' a semaphore each time it processes an event + * (decrementing the semaphore count value). The count value is therefore + * the difference between the number of events that have occurred and the + * number that have been processed. In this case it is desirable for the + * initial count value to be zero. + * + * 2) Resource management. + * + * In this usage scenario the count value indicates the number of resources + * available. To obtain control of a resource a task must first obtain a + * semaphore - decrementing the semaphore count value. When the count value + * reaches zero there are no free resources. When a task finishes with the + * resource it 'gives' the semaphore back - incrementing the semaphore count + * value. In this case it is desirable for the initial count value to be + * equal to the maximum count value, indicating that all resources are free. + * + * @param uxMaxCount The maximum count value that can be reached. When the + * semaphore reaches this value it can no longer be 'given'. + * + * @param uxInitialCount The count value assigned to the semaphore when it is + * created. + * + * @return Handle to the created semaphore. Null if the semaphore could not be + * created. + * + * Example usage: + * 
+ * SemaphoreHandle_t xSemaphore;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ * SemaphoreHandle_t xSemaphore = NULL;
+ *
+ *  // Semaphore cannot be used before a call to xSemaphoreCreateCounting().
+ *  // The max value to which the semaphore can count should be 10, and the
+ *  // initial value assigned to the count should be 0.
+ *  xSemaphore = xSemaphoreCreateCounting( 10, 0 );
+ *
+ *  if( xSemaphore != NULL )
+ *  {
+ *      // The semaphore was created successfully.
+ *      // The semaphore can now be used.
+ *  }
+ * }
+ *
+ * \defgroup xSemaphoreCreateCounting xSemaphoreCreateCounting + * \ingroup Semaphores + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + #define xSemaphoreCreateCounting( uxMaxCount, uxInitialCount ) xQueueCreateCountingSemaphore( ( uxMaxCount ), ( uxInitialCount ) ) +#endif + +/** + * semphr. h + * 
+ * SemaphoreHandle_t xSemaphoreCreateCountingStatic( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount, StaticSemaphore_t *pxSemaphoreBuffer );
+ *
+ * + * Creates a new counting semaphore instance, and returns a handle by which the + * new counting semaphore can be referenced. + * + * In many usage scenarios it is faster and more memory efficient to use a + * direct to task notification in place of a counting semaphore! + * https://www.FreeRTOS.org/RTOS-task-notifications.html + * + * Internally, within the FreeRTOS implementation, counting semaphores use a + * block of memory, in which the counting semaphore structure is stored. If a + * counting semaphore is created using xSemaphoreCreateCounting() then the + * required memory is automatically dynamically allocated inside the + * xSemaphoreCreateCounting() function. (see + * https://www.FreeRTOS.org/a00111.html). If a counting semaphore is created + * using xSemaphoreCreateCountingStatic() then the application writer must + * provide the memory. xSemaphoreCreateCountingStatic() therefore allows a + * counting semaphore to be created without using any dynamic memory allocation. + * + * Counting semaphores are typically used for two things: + * + * 1) Counting events. + * + * In this usage scenario an event handler will 'give' a semaphore each time + * an event occurs (incrementing the semaphore count value), and a handler + * task will 'take' a semaphore each time it processes an event + * (decrementing the semaphore count value). The count value is therefore + * the difference between the number of events that have occurred and the + * number that have been processed. In this case it is desirable for the + * initial count value to be zero. + * + * 2) Resource management. + * + * In this usage scenario the count value indicates the number of resources + * available. To obtain control of a resource a task must first obtain a + * semaphore - decrementing the semaphore count value. When the count value + * reaches zero there are no free resources. When a task finishes with the + * resource it 'gives' the semaphore back - incrementing the semaphore count + * value. In this case it is desirable for the initial count value to be + * equal to the maximum count value, indicating that all resources are free. + * + * @param uxMaxCount The maximum count value that can be reached. When the + * semaphore reaches this value it can no longer be 'given'. + * + * @param uxInitialCount The count value assigned to the semaphore when it is + * created. + * + * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t, + * which will then be used to hold the semaphore's data structure, removing the + * need for the memory to be allocated dynamically. + * + * @return If the counting semaphore was successfully created then a handle to + * the created counting semaphore is returned. If pxSemaphoreBuffer was NULL + * then NULL is returned. + * + * Example usage: + * 
+ * SemaphoreHandle_t xSemaphore;
+ * StaticSemaphore_t xSemaphoreBuffer;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ * SemaphoreHandle_t xSemaphore = NULL;
+ *
+ *  // Counting semaphore cannot be used before they have been created.  Create
+ *  // a counting semaphore using xSemaphoreCreateCountingStatic().  The max
+ *  // value to which the semaphore can count is 10, and the initial value
+ *  // assigned to the count will be 0.  The address of xSemaphoreBuffer is
+ *  // passed in and will be used to hold the semaphore structure, so no dynamic
+ *  // memory allocation will be used.
+ *  xSemaphore = xSemaphoreCreateCounting( 10, 0, &xSemaphoreBuffer );
+ *
+ *  // No memory allocation was attempted so xSemaphore cannot be NULL, so there
+ *  // is no need to check its value.
+ * }
+ *
+ * \defgroup xSemaphoreCreateCountingStatic xSemaphoreCreateCountingStatic + * \ingroup Semaphores + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + #define xSemaphoreCreateCountingStatic( uxMaxCount, uxInitialCount, pxSemaphoreBuffer ) xQueueCreateCountingSemaphoreStatic( ( uxMaxCount ), ( uxInitialCount ), ( pxSemaphoreBuffer ) ) +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/** + * semphr. h + * 
+ * void vSemaphoreDelete( SemaphoreHandle_t xSemaphore );
+ *
+ * + * Delete a semaphore. This function must be used with care. For example, + * do not delete a mutex type semaphore if the mutex is held by a task. + * + * @param xSemaphore A handle to the semaphore to be deleted. + * + * \defgroup vSemaphoreDelete vSemaphoreDelete + * \ingroup Semaphores + */ +#define vSemaphoreDelete( xSemaphore ) vQueueDelete( ( QueueHandle_t ) ( xSemaphore ) ) + +/** + * semphr.h + * 
+ * TaskHandle_t xSemaphoreGetMutexHolder( SemaphoreHandle_t xMutex );
+ *
+ * + * If xMutex is indeed a mutex type semaphore, return the current mutex holder. + * If xMutex is not a mutex type semaphore, or the mutex is available (not held + * by a task), return NULL. + * + * Note: This is a good way of determining if the calling task is the mutex + * holder, but not a good way of determining the identity of the mutex holder as + * the holder may change between the function exiting and the returned value + * being tested. + */ +#define xSemaphoreGetMutexHolder( xSemaphore ) xQueueGetMutexHolder( ( xSemaphore ) ) + +/** + * semphr.h + * 
+ * TaskHandle_t xSemaphoreGetMutexHolderFromISR( SemaphoreHandle_t xMutex );
+ *
+ * + * If xMutex is indeed a mutex type semaphore, return the current mutex holder. + * If xMutex is not a mutex type semaphore, or the mutex is available (not held + * by a task), return NULL. + * + */ +#define xSemaphoreGetMutexHolderFromISR( xSemaphore ) xQueueGetMutexHolderFromISR( ( xSemaphore ) ) + +/** + * semphr.h + * 
+ * UBaseType_t uxSemaphoreGetCount( SemaphoreHandle_t xSemaphore );
+ *
+ * + * If the semaphore is a counting semaphore then uxSemaphoreGetCount() returns + * its current count value. If the semaphore is a binary semaphore then + * uxSemaphoreGetCount() returns 1 if the semaphore is available, and 0 if the + * semaphore is not available. + * + */ +#define uxSemaphoreGetCount( xSemaphore ) uxQueueMessagesWaiting( ( QueueHandle_t ) ( xSemaphore ) ) + +#endif /* SEMAPHORE_H */ diff --git a/MODULES/FreeRTOS/inc/stack_macros.h b/MODULES/FreeRTOS/inc/stack_macros.h new file mode 100644 index 0000000..3eabe21 --- /dev/null +++ b/MODULES/FreeRTOS/inc/stack_macros.h @@ -0,0 +1,127 @@ +/* + * FreeRTOS Kernel V10.4.3 LTS Patch 2 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef STACK_MACROS_H +#define STACK_MACROS_H + +/* + * Call the stack overflow hook function if the stack of the task being swapped + * out is currently overflowed, or looks like it might have overflowed in the + * past. + * + * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check + * the current stack state only - comparing the current top of stack value to + * the stack limit. Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1 + * will also cause the last few stack bytes to be checked to ensure the value + * to which the bytes were set when the task was created have not been + * overwritten. Note this second test does not guarantee that an overflowed + * stack will always be recognised. + */ + +/*-----------------------------------------------------------*/ + +#if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) ) + +/* Only the current stack state is to be checked. */ + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + /* Is the currently saved stack pointer within the stack limit? */ \ + if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) ) + +/* Only the current stack state is to be checked. */ + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + \ + /* Is the currently saved stack pointer within the stack limit? */ \ + if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */ +/*-----------------------------------------------------------*/ + +#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) ) + + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack; \ + const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5; \ + \ + if( ( pulStack[ 0 ] != ulCheckValue ) || \ + ( pulStack[ 1 ] != ulCheckValue ) || \ + ( pulStack[ 2 ] != ulCheckValue ) || \ + ( pulStack[ 3 ] != ulCheckValue ) ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) ) + + #define taskCHECK_FOR_STACK_OVERFLOW() \ + { \ + int8_t * pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack; \ + static const uint8_t ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \ + tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \ + \ + \ + pcEndOfStack -= sizeof( ucExpectedStackBytes ); \ + \ + /* Has the extremity of the task stack ever been written over? */ \ + if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) \ + { \ + vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \ + } \ + } + +#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */ +/*-----------------------------------------------------------*/ + +/* Remove stack overflow macro if not being used. */ +#ifndef taskCHECK_FOR_STACK_OVERFLOW + #define taskCHECK_FOR_STACK_OVERFLOW() +#endif + + + +#endif /* STACK_MACROS_H */ diff --git a/MODULES/FreeRTOS/inc/stdint.readme b/MODULES/FreeRTOS/inc/stdint.readme new file mode 100644 index 0000000..629ae4b --- /dev/null +++ b/MODULES/FreeRTOS/inc/stdint.readme @@ -0,0 +1,52 @@ +/* + * FreeRTOS Kernel V10.4.3 LTS Patch 2 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef FREERTOS_STDINT +#define FREERTOS_STDINT + +/******************************************************************************* + * THIS IS NOT A FULL stdint.h IMPLEMENTATION - It only contains the definitions + * necessary to build the FreeRTOS code. It is provided to allow FreeRTOS to be + * built using compilers that do not provide their own stdint.h definition. + * + * To use this file: + * + * 1) Copy this file into the directory that contains your FreeRTOSConfig.h + * header file, as that directory will already be in the compiler's include + * path. + * + * 2) Rename the copied file stdint.h. + * + */ + +typedef signed char int8_t; +typedef unsigned char uint8_t; +typedef short int16_t; +typedef unsigned short uint16_t; +typedef long int32_t; +typedef unsigned long uint32_t; + +#endif /* FREERTOS_STDINT */ diff --git a/MODULES/FreeRTOS/inc/stream_buffer.h b/MODULES/FreeRTOS/inc/stream_buffer.h new file mode 100644 index 0000000..282f4db --- /dev/null +++ b/MODULES/FreeRTOS/inc/stream_buffer.h @@ -0,0 +1,867 @@ +/* + * FreeRTOS Kernel V10.4.3 LTS Patch 2 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * Stream buffers are used to send a continuous stream of data from one task or + * interrupt to another. Their implementation is light weight, making them + * particularly suited for interrupt to task and core to core communication + * scenarios. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xStreamBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xStreamBufferReceive()) inside a critical section section and set the + * receive block time to 0. + * + */ + +#ifndef STREAM_BUFFER_H +#define STREAM_BUFFER_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include stream_buffer.h" +#endif + +/* *INDENT-OFF* */ +#if defined( __cplusplus ) + extern "C" { +#endif +/* *INDENT-ON* */ + +/** + * Type by which stream buffers are referenced. For example, a call to + * xStreamBufferCreate() returns an StreamBufferHandle_t variable that can + * then be used as a parameter to xStreamBufferSend(), xStreamBufferReceive(), + * etc. + */ +struct StreamBufferDef_t; +typedef struct StreamBufferDef_t * StreamBufferHandle_t; + + +/** + * message_buffer.h + * + * 
+ * StreamBufferHandle_t xStreamBufferCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes );
+ *
+ * + * Creates a new stream buffer using dynamically allocated memory. See + * xStreamBufferCreateStatic() for a version that uses statically allocated + * memory (memory that is allocated at compile time). + * + * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in + * FreeRTOSConfig.h for xStreamBufferCreate() to be available. + * + * @param xBufferSizeBytes The total number of bytes the stream buffer will be + * able to hold at any one time. + * + * @param xTriggerLevelBytes The number of bytes that must be in the stream + * buffer before a task that is blocked on the stream buffer to wait for data is + * moved out of the blocked state. For example, if a task is blocked on a read + * of an empty stream buffer that has a trigger level of 1 then the task will be + * unblocked when a single byte is written to the buffer or the task's block + * time expires. As another example, if a task is blocked on a read of an empty + * stream buffer that has a trigger level of 10 then the task will not be + * unblocked until the stream buffer contains at least 10 bytes or the task's + * block time expires. If a reading task's block time expires before the + * trigger level is reached then the task will still receive however many bytes + * are actually available. Setting a trigger level of 0 will result in a + * trigger level of 1 being used. It is not valid to specify a trigger level + * that is greater than the buffer size. + * + * @return If NULL is returned, then the stream buffer cannot be created + * because there is insufficient heap memory available for FreeRTOS to allocate + * the stream buffer data structures and storage area. A non-NULL value being + * returned indicates that the stream buffer has been created successfully - + * the returned value should be stored as the handle to the created stream + * buffer. + * + * Example use: + * 
+ *
+ * void vAFunction( void )
+ * {
+ * StreamBufferHandle_t xStreamBuffer;
+ * const size_t xStreamBufferSizeBytes = 100, xTriggerLevel = 10;
+ *
+ *  // Create a stream buffer that can hold 100 bytes.  The memory used to hold
+ *  // both the stream buffer structure and the data in the stream buffer is
+ *  // allocated dynamically.
+ *  xStreamBuffer = xStreamBufferCreate( xStreamBufferSizeBytes, xTriggerLevel );
+ *
+ *  if( xStreamBuffer == NULL )
+ *  {
+ *      // There was not enough heap memory space available to create the
+ *      // stream buffer.
+ *  }
+ *  else
+ *  {
+ *      // The stream buffer was created successfully and can now be used.
+ *  }
+ * }
+ *
+ * \defgroup xStreamBufferCreate xStreamBufferCreate + * \ingroup StreamBufferManagement + */ +#define xStreamBufferCreate( xBufferSizeBytes, xTriggerLevelBytes ) xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE ) + +/** + * stream_buffer.h + * + * 
+ * StreamBufferHandle_t xStreamBufferCreateStatic( size_t xBufferSizeBytes,
+ *                                              size_t xTriggerLevelBytes,
+ *                                              uint8_t *pucStreamBufferStorageArea,
+ *                                              StaticStreamBuffer_t *pxStaticStreamBuffer );
+ *
+ * Creates a new stream buffer using statically allocated memory. See + * xStreamBufferCreate() for a version that uses dynamically allocated memory. + * + * configSUPPORT_STATIC_ALLOCATION must be set to 1 in FreeRTOSConfig.h for + * xStreamBufferCreateStatic() to be available. + * + * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the + * pucStreamBufferStorageArea parameter. + * + * @param xTriggerLevelBytes The number of bytes that must be in the stream + * buffer before a task that is blocked on the stream buffer to wait for data is + * moved out of the blocked state. For example, if a task is blocked on a read + * of an empty stream buffer that has a trigger level of 1 then the task will be + * unblocked when a single byte is written to the buffer or the task's block + * time expires. As another example, if a task is blocked on a read of an empty + * stream buffer that has a trigger level of 10 then the task will not be + * unblocked until the stream buffer contains at least 10 bytes or the task's + * block time expires. If a reading task's block time expires before the + * trigger level is reached then the task will still receive however many bytes + * are actually available. Setting a trigger level of 0 will result in a + * trigger level of 1 being used. It is not valid to specify a trigger level + * that is greater than the buffer size. + * + * @param pucStreamBufferStorageArea Must point to a uint8_t array that is at + * least xBufferSizeBytes + 1 big. This is the array to which streams are + * copied when they are written to the stream buffer. + * + * @param pxStaticStreamBuffer Must point to a variable of type + * StaticStreamBuffer_t, which will be used to hold the stream buffer's data + * structure. + * + * @return If the stream buffer is created successfully then a handle to the + * created stream buffer is returned. If either pucStreamBufferStorageArea or + * pxStaticstreamBuffer are NULL then NULL is returned. + * + * Example use: + * 
+ *
+ * // Used to dimension the array used to hold the streams.  The available space
+ * // will actually be one less than this, so 999.
+ #define STORAGE_SIZE_BYTES 1000
+ *
+ * // Defines the memory that will actually hold the streams within the stream
+ * // buffer.
+ * static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
+ *
+ * // The variable used to hold the stream buffer structure.
+ * StaticStreamBuffer_t xStreamBufferStruct;
+ *
+ * void MyFunction( void )
+ * {
+ * StreamBufferHandle_t xStreamBuffer;
+ * const size_t xTriggerLevel = 1;
+ *
+ *  xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucBufferStorage ),
+ *                                             xTriggerLevel,
+ *                                             ucBufferStorage,
+ *                                             &xStreamBufferStruct );
+ *
+ *  // As neither the pucStreamBufferStorageArea or pxStaticStreamBuffer
+ *  // parameters were NULL, xStreamBuffer will not be NULL, and can be used to
+ *  // reference the created stream buffer in other stream buffer API calls.
+ *
+ *  // Other code that uses the stream buffer can go here.
+ * }
+ *
+ *
+ * \defgroup xStreamBufferCreateStatic xStreamBufferCreateStatic + * \ingroup StreamBufferManagement + */ +#define xStreamBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) \ + xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE, pucStreamBufferStorageArea, pxStaticStreamBuffer ) + +/** + * stream_buffer.h + * + * 
+ * size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+ *                        const void *pvTxData,
+ *                        size_t xDataLengthBytes,
+ *                        TickType_t xTicksToWait );
+ *
+ * + * Sends bytes to a stream buffer. The bytes are copied into the stream buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xStreamBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xStreamBufferReceive()) inside a critical section and set the receive + * block time to 0. + * + * Use xStreamBufferSend() to write to a stream buffer from a task. Use + * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt + * service routine (ISR). + * + * @param xStreamBuffer The handle of the stream buffer to which a stream is + * being sent. + * + * @param pvTxData A pointer to the buffer that holds the bytes to be copied + * into the stream buffer. + * + * @param xDataLengthBytes The maximum number of bytes to copy from pvTxData + * into the stream buffer. + * + * @param xTicksToWait The maximum amount of time the task should remain in the + * Blocked state to wait for enough space to become available in the stream + * buffer, should the stream buffer contain too little space to hold the + * another xDataLengthBytes bytes. The block time is specified in tick periods, + * so the absolute time it represents is dependent on the tick frequency. The + * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds + * into a time specified in ticks. Setting xTicksToWait to portMAX_DELAY will + * cause the task to wait indefinitely (without timing out), provided + * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h. If a task times out + * before it can write all xDataLengthBytes into the buffer it will still write + * as many bytes as possible. A task does not use any CPU time when it is in + * the blocked state. + * + * @return The number of bytes written to the stream buffer. If a task times + * out before it can write all xDataLengthBytes into the buffer it will still + * write as many bytes as possible. + * + * Example use: + * 
+ * void vAFunction( StreamBufferHandle_t xStreamBuffer )
+ * {
+ * size_t xBytesSent;
+ * uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
+ * char *pcStringToSend = "String to send";
+ * const TickType_t x100ms = pdMS_TO_TICKS( 100 );
+ *
+ *  // Send an array to the stream buffer, blocking for a maximum of 100ms to
+ *  // wait for enough space to be available in the stream buffer.
+ *  xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
+ *
+ *  if( xBytesSent != sizeof( ucArrayToSend ) )
+ *  {
+ *      // The call to xStreamBufferSend() times out before there was enough
+ *      // space in the buffer for the data to be written, but it did
+ *      // successfully write xBytesSent bytes.
+ *  }
+ *
+ *  // Send the string to the stream buffer.  Return immediately if there is not
+ *  // enough space in the buffer.
+ *  xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
+ *
+ *  if( xBytesSent != strlen( pcStringToSend ) )
+ *  {
+ *      // The entire string could not be added to the stream buffer because
+ *      // there was not enough free space in the buffer, but xBytesSent bytes
+ *      // were sent.  Could try again to send the remaining bytes.
+ *  }
+ * }
+ *
+ * \defgroup xStreamBufferSend xStreamBufferSend + * \ingroup StreamBufferManagement + */ +size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * 
+ * size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+ *                               const void *pvTxData,
+ *                               size_t xDataLengthBytes,
+ *                               BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * + * Interrupt safe version of the API function that sends a stream of bytes to + * the stream buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xStreamBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xStreamBufferReceive()) inside a critical section and set the receive + * block time to 0. + * + * Use xStreamBufferSend() to write to a stream buffer from a task. Use + * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt + * service routine (ISR). + * + * @param xStreamBuffer The handle of the stream buffer to which a stream is + * being sent. + * + * @param pvTxData A pointer to the data that is to be copied into the stream + * buffer. + * + * @param xDataLengthBytes The maximum number of bytes to copy from pvTxData + * into the stream buffer. + * + * @param pxHigherPriorityTaskWoken It is possible that a stream buffer will + * have a task blocked on it waiting for data. Calling + * xStreamBufferSendFromISR() can make data available, and so cause a task that + * was waiting for data to leave the Blocked state. If calling + * xStreamBufferSendFromISR() causes a task to leave the Blocked state, and the + * unblocked task has a priority higher than the currently executing task (the + * task that was interrupted), then, internally, xStreamBufferSendFromISR() + * will set *pxHigherPriorityTaskWoken to pdTRUE. If + * xStreamBufferSendFromISR() sets this value to pdTRUE, then normally a + * context switch should be performed before the interrupt is exited. This will + * ensure that the interrupt returns directly to the highest priority Ready + * state task. *pxHigherPriorityTaskWoken should be set to pdFALSE before it + * is passed into the function. See the example code below for an example. + * + * @return The number of bytes actually written to the stream buffer, which will + * be less than xDataLengthBytes if the stream buffer didn't have enough free + * space for all the bytes to be written. + * + * Example use: + * 
+ * // A stream buffer that has already been created.
+ * StreamBufferHandle_t xStreamBuffer;
+ *
+ * void vAnInterruptServiceRoutine( void )
+ * {
+ * size_t xBytesSent;
+ * char *pcStringToSend = "String to send";
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
+ *
+ *  // Attempt to send the string to the stream buffer.
+ *  xBytesSent = xStreamBufferSendFromISR( xStreamBuffer,
+ *                                         ( void * ) pcStringToSend,
+ *                                         strlen( pcStringToSend ),
+ *                                         &xHigherPriorityTaskWoken );
+ *
+ *  if( xBytesSent != strlen( pcStringToSend ) )
+ *  {
+ *      // There was not enough free space in the stream buffer for the entire
+ *      // string to be written, ut xBytesSent bytes were written.
+ *  }
+ *
+ *  // If xHigherPriorityTaskWoken was set to pdTRUE inside
+ *  // xStreamBufferSendFromISR() then a task that has a priority above the
+ *  // priority of the currently executing task was unblocked and a context
+ *  // switch should be performed to ensure the ISR returns to the unblocked
+ *  // task.  In most FreeRTOS ports this is done by simply passing
+ *  // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+ *  // variables value, and perform the context switch if necessary.  Check the
+ *  // documentation for the port in use for port specific instructions.
+ *  taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ * }
+ *
+ * \defgroup xStreamBufferSendFromISR xStreamBufferSendFromISR + * \ingroup StreamBufferManagement + */ +size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * 
+ * size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+ *                           void *pvRxData,
+ *                           size_t xBufferLengthBytes,
+ *                           TickType_t xTicksToWait );
+ *
+ * + * Receives bytes from a stream buffer. + * + * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer + * implementation (so also the message buffer implementation, as message buffers + * are built on top of stream buffers) assumes there is only one task or + * interrupt that will write to the buffer (the writer), and only one task or + * interrupt that will read from the buffer (the reader). It is safe for the + * writer and reader to be different tasks or interrupts, but, unlike other + * FreeRTOS objects, it is not safe to have multiple different writers or + * multiple different readers. If there are to be multiple different writers + * then the application writer must place each call to a writing API function + * (such as xStreamBufferSend()) inside a critical section and set the send + * block time to 0. Likewise, if there are to be multiple different readers + * then the application writer must place each call to a reading API function + * (such as xStreamBufferReceive()) inside a critical section and set the receive + * block time to 0. + * + * Use xStreamBufferReceive() to read from a stream buffer from a task. Use + * xStreamBufferReceiveFromISR() to read from a stream buffer from an + * interrupt service routine (ISR). + * + * @param xStreamBuffer The handle of the stream buffer from which bytes are to + * be received. + * + * @param pvRxData A pointer to the buffer into which the received bytes will be + * copied. + * + * @param xBufferLengthBytes The length of the buffer pointed to by the + * pvRxData parameter. This sets the maximum number of bytes to receive in one + * call. xStreamBufferReceive will return as many bytes as possible up to a + * maximum set by xBufferLengthBytes. + * + * @param xTicksToWait The maximum amount of time the task should remain in the + * Blocked state to wait for data to become available if the stream buffer is + * empty. xStreamBufferReceive() will return immediately if xTicksToWait is + * zero. The block time is specified in tick periods, so the absolute time it + * represents is dependent on the tick frequency. The macro pdMS_TO_TICKS() can + * be used to convert a time specified in milliseconds into a time specified in + * ticks. Setting xTicksToWait to portMAX_DELAY will cause the task to wait + * indefinitely (without timing out), provided INCLUDE_vTaskSuspend is set to 1 + * in FreeRTOSConfig.h. A task does not use any CPU time when it is in the + * Blocked state. + * + * @return The number of bytes actually read from the stream buffer, which will + * be less than xBufferLengthBytes if the call to xStreamBufferReceive() timed + * out before xBufferLengthBytes were available. + * + * Example use: + * 
+ * void vAFunction( StreamBuffer_t xStreamBuffer )
+ * {
+ * uint8_t ucRxData[ 20 ];
+ * size_t xReceivedBytes;
+ * const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
+ *
+ *  // Receive up to another sizeof( ucRxData ) bytes from the stream buffer.
+ *  // Wait in the Blocked state (so not using any CPU processing time) for a
+ *  // maximum of 100ms for the full sizeof( ucRxData ) number of bytes to be
+ *  // available.
+ *  xReceivedBytes = xStreamBufferReceive( xStreamBuffer,
+ *                                         ( void * ) ucRxData,
+ *                                         sizeof( ucRxData ),
+ *                                         xBlockTime );
+ *
+ *  if( xReceivedBytes > 0 )
+ *  {
+ *      // A ucRxData contains another xRecievedBytes bytes of data, which can
+ *      // be processed here....
+ *  }
+ * }
+ *
+ * \defgroup xStreamBufferReceive xStreamBufferReceive + * \ingroup StreamBufferManagement + */ +size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * 
+ * size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+ *                                  void *pvRxData,
+ *                                  size_t xBufferLengthBytes,
+ *                                  BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * + * An interrupt safe version of the API function that receives bytes from a + * stream buffer. + * + * Use xStreamBufferReceive() to read bytes from a stream buffer from a task. + * Use xStreamBufferReceiveFromISR() to read bytes from a stream buffer from an + * interrupt service routine (ISR). + * + * @param xStreamBuffer The handle of the stream buffer from which a stream + * is being received. + * + * @param pvRxData A pointer to the buffer into which the received bytes are + * copied. + * + * @param xBufferLengthBytes The length of the buffer pointed to by the + * pvRxData parameter. This sets the maximum number of bytes to receive in one + * call. xStreamBufferReceive will return as many bytes as possible up to a + * maximum set by xBufferLengthBytes. + * + * @param pxHigherPriorityTaskWoken It is possible that a stream buffer will + * have a task blocked on it waiting for space to become available. Calling + * xStreamBufferReceiveFromISR() can make space available, and so cause a task + * that is waiting for space to leave the Blocked state. If calling + * xStreamBufferReceiveFromISR() causes a task to leave the Blocked state, and + * the unblocked task has a priority higher than the currently executing task + * (the task that was interrupted), then, internally, + * xStreamBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE. + * If xStreamBufferReceiveFromISR() sets this value to pdTRUE, then normally a + * context switch should be performed before the interrupt is exited. That will + * ensure the interrupt returns directly to the highest priority Ready state + * task. *pxHigherPriorityTaskWoken should be set to pdFALSE before it is + * passed into the function. See the code example below for an example. + * + * @return The number of bytes read from the stream buffer, if any. + * + * Example use: + * 
+ * // A stream buffer that has already been created.
+ * StreamBuffer_t xStreamBuffer;
+ *
+ * void vAnInterruptServiceRoutine( void )
+ * {
+ * uint8_t ucRxData[ 20 ];
+ * size_t xReceivedBytes;
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
+ *
+ *  // Receive the next stream from the stream buffer.
+ *  xReceivedBytes = xStreamBufferReceiveFromISR( xStreamBuffer,
+ *                                                ( void * ) ucRxData,
+ *                                                sizeof( ucRxData ),
+ *                                                &xHigherPriorityTaskWoken );
+ *
+ *  if( xReceivedBytes > 0 )
+ *  {
+ *      // ucRxData contains xReceivedBytes read from the stream buffer.
+ *      // Process the stream here....
+ *  }
+ *
+ *  // If xHigherPriorityTaskWoken was set to pdTRUE inside
+ *  // xStreamBufferReceiveFromISR() then a task that has a priority above the
+ *  // priority of the currently executing task was unblocked and a context
+ *  // switch should be performed to ensure the ISR returns to the unblocked
+ *  // task.  In most FreeRTOS ports this is done by simply passing
+ *  // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+ *  // variables value, and perform the context switch if necessary.  Check the
+ *  // documentation for the port in use for port specific instructions.
+ *  taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ * }
+ *
+ * \defgroup xStreamBufferReceiveFromISR xStreamBufferReceiveFromISR + * \ingroup StreamBufferManagement + */ +size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * 
+ * void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer );
+ *
+ * + * Deletes a stream buffer that was previously created using a call to + * xStreamBufferCreate() or xStreamBufferCreateStatic(). If the stream + * buffer was created using dynamic memory (that is, by xStreamBufferCreate()), + * then the allocated memory is freed. + * + * A stream buffer handle must not be used after the stream buffer has been + * deleted. + * + * @param xStreamBuffer The handle of the stream buffer to be deleted. + * + * \defgroup vStreamBufferDelete vStreamBufferDelete + * \ingroup StreamBufferManagement + */ +void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * 
+ * BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer );
+ *
+ * + * Queries a stream buffer to see if it is full. A stream buffer is full if it + * does not have any free space, and therefore cannot accept any more data. + * + * @param xStreamBuffer The handle of the stream buffer being queried. + * + * @return If the stream buffer is full then pdTRUE is returned. Otherwise + * pdFALSE is returned. + * + * \defgroup xStreamBufferIsFull xStreamBufferIsFull + * \ingroup StreamBufferManagement + */ +BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * 
+ * BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer );
+ *
+ * + * Queries a stream buffer to see if it is empty. A stream buffer is empty if + * it does not contain any data. + * + * @param xStreamBuffer The handle of the stream buffer being queried. + * + * @return If the stream buffer is empty then pdTRUE is returned. Otherwise + * pdFALSE is returned. + * + * \defgroup xStreamBufferIsEmpty xStreamBufferIsEmpty + * \ingroup StreamBufferManagement + */ +BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * 
+ * BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer );
+ *
+ * + * Resets a stream buffer to its initial, empty, state. Any data that was in + * the stream buffer is discarded. A stream buffer can only be reset if there + * are no tasks blocked waiting to either send to or receive from the stream + * buffer. + * + * @param xStreamBuffer The handle of the stream buffer being reset. + * + * @return If the stream buffer is reset then pdPASS is returned. If there was + * a task blocked waiting to send to or read from the stream buffer then the + * stream buffer is not reset and pdFAIL is returned. + * + * \defgroup xStreamBufferReset xStreamBufferReset + * \ingroup StreamBufferManagement + */ +BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * 
+ * size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer );
+ *
+ * + * Queries a stream buffer to see how much free space it contains, which is + * equal to the amount of data that can be sent to the stream buffer before it + * is full. + * + * @param xStreamBuffer The handle of the stream buffer being queried. + * + * @return The number of bytes that can be written to the stream buffer before + * the stream buffer would be full. + * + * \defgroup xStreamBufferSpacesAvailable xStreamBufferSpacesAvailable + * \ingroup StreamBufferManagement + */ +size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * 
+ * size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer );
+ *
+ * + * Queries a stream buffer to see how much data it contains, which is equal to + * the number of bytes that can be read from the stream buffer before the stream + * buffer would be empty. + * + * @param xStreamBuffer The handle of the stream buffer being queried. + * + * @return The number of bytes that can be read from the stream buffer before + * the stream buffer would be empty. + * + * \defgroup xStreamBufferBytesAvailable xStreamBufferBytesAvailable + * \ingroup StreamBufferManagement + */ +size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * 
+ * BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel );
+ *
+ * + * A stream buffer's trigger level is the number of bytes that must be in the + * stream buffer before a task that is blocked on the stream buffer to + * wait for data is moved out of the blocked state. For example, if a task is + * blocked on a read of an empty stream buffer that has a trigger level of 1 + * then the task will be unblocked when a single byte is written to the buffer + * or the task's block time expires. As another example, if a task is blocked + * on a read of an empty stream buffer that has a trigger level of 10 then the + * task will not be unblocked until the stream buffer contains at least 10 bytes + * or the task's block time expires. If a reading task's block time expires + * before the trigger level is reached then the task will still receive however + * many bytes are actually available. Setting a trigger level of 0 will result + * in a trigger level of 1 being used. It is not valid to specify a trigger + * level that is greater than the buffer size. + * + * A trigger level is set when the stream buffer is created, and can be modified + * using xStreamBufferSetTriggerLevel(). + * + * @param xStreamBuffer The handle of the stream buffer being updated. + * + * @param xTriggerLevel The new trigger level for the stream buffer. + * + * @return If xTriggerLevel was less than or equal to the stream buffer's length + * then the trigger level will be updated and pdTRUE is returned. Otherwise + * pdFALSE is returned. + * + * \defgroup xStreamBufferSetTriggerLevel xStreamBufferSetTriggerLevel + * \ingroup StreamBufferManagement + */ +BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * 
+ * BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * + * For advanced users only. + * + * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when + * data is sent to a message buffer or stream buffer. If there was a task that + * was blocked on the message or stream buffer waiting for data to arrive then + * the sbSEND_COMPLETED() macro sends a notification to the task to remove it + * from the Blocked state. xStreamBufferSendCompletedFromISR() does the same + * thing. It is provided to enable application writers to implement their own + * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME. + * + * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for + * additional information. + * + * @param xStreamBuffer The handle of the stream buffer to which data was + * written. + * + * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be + * initialised to pdFALSE before it is passed into + * xStreamBufferSendCompletedFromISR(). If calling + * xStreamBufferSendCompletedFromISR() removes a task from the Blocked state, + * and the task has a priority above the priority of the currently running task, + * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a + * context switch should be performed before exiting the ISR. + * + * @return If a task was removed from the Blocked state then pdTRUE is returned. + * Otherwise pdFALSE is returned. + * + * \defgroup xStreamBufferSendCompletedFromISR xStreamBufferSendCompletedFromISR + * \ingroup StreamBufferManagement + */ +BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, + BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/** + * stream_buffer.h + * + * 
+ * BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * + * For advanced users only. + * + * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when + * data is read out of a message buffer or stream buffer. If there was a task + * that was blocked on the message or stream buffer waiting for data to arrive + * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to + * remove it from the Blocked state. xStreamBufferReceiveCompletedFromISR() + * does the same thing. It is provided to enable application writers to + * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT + * ANY OTHER TIME. + * + * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for + * additional information. + * + * @param xStreamBuffer The handle of the stream buffer from which data was + * read. + * + * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be + * initialised to pdFALSE before it is passed into + * xStreamBufferReceiveCompletedFromISR(). If calling + * xStreamBufferReceiveCompletedFromISR() removes a task from the Blocked state, + * and the task has a priority above the priority of the currently running task, + * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a + * context switch should be performed before exiting the ISR. + * + * @return If a task was removed from the Blocked state then pdTRUE is returned. + * Otherwise pdFALSE is returned. + * + * \defgroup xStreamBufferReceiveCompletedFromISR xStreamBufferReceiveCompletedFromISR + * \ingroup StreamBufferManagement + */ +BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, + BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/* Functions below here are not part of the public API. */ +StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xIsMessageBuffer ) PRIVILEGED_FUNCTION; + +StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xIsMessageBuffer, + uint8_t * const pucStreamBufferStorageArea, + StaticStreamBuffer_t * const pxStaticStreamBuffer ) PRIVILEGED_FUNCTION; + +size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + +#if ( configUSE_TRACE_FACILITY == 1 ) + void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, + UBaseType_t uxStreamBufferNumber ) PRIVILEGED_FUNCTION; + UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; + uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION; +#endif + +/* *INDENT-OFF* */ +#if defined( __cplusplus ) + } +#endif +/* *INDENT-ON* */ + +#endif /* !defined( STREAM_BUFFER_H ) */ diff --git a/MODULES/FreeRTOS/inc/task.h b/MODULES/FreeRTOS/inc/task.h new file mode 100644 index 0000000..3aed608 --- /dev/null +++ b/MODULES/FreeRTOS/inc/task.h @@ -0,0 +1,3053 @@ +/* + * FreeRTOS Kernel V10.4.3 LTS Patch 2 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef INC_TASK_H +#define INC_TASK_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include task.h" +#endif + +#include "list.h" + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- +* MACROS AND DEFINITIONS +*----------------------------------------------------------*/ + +#define tskKERNEL_VERSION_NUMBER "V10.4.3 LTS Patch 2" +#define tskKERNEL_VERSION_MAJOR 10 +#define tskKERNEL_VERSION_MINOR 4 +#define tskKERNEL_VERSION_BUILD 3 + +/* MPU region parameters passed in ulParameters + * of MemoryRegion_t struct. */ +#define tskMPU_REGION_READ_ONLY ( 1UL << 0UL ) +#define tskMPU_REGION_READ_WRITE ( 1UL << 1UL ) +#define tskMPU_REGION_EXECUTE_NEVER ( 1UL << 2UL ) +#define tskMPU_REGION_NORMAL_MEMORY ( 1UL << 3UL ) +#define tskMPU_REGION_DEVICE_MEMORY ( 1UL << 4UL ) + +/* The direct to task notification feature used to have only a single notification + * per task. Now there is an array of notifications per task that is dimensioned by + * configTASK_NOTIFICATION_ARRAY_ENTRIES. For backward compatibility, any use of the + * original direct to task notification defaults to using the first index in the + * array. */ +#define tskDEFAULT_INDEX_TO_NOTIFY ( 0 ) + +/** + * task. h + * + * Type by which tasks are referenced. For example, a call to xTaskCreate + * returns (via a pointer parameter) an TaskHandle_t variable that can then + * be used as a parameter to vTaskDelete to delete the task. + * + * \defgroup TaskHandle_t TaskHandle_t + * \ingroup Tasks + */ +struct tskTaskControlBlock; /* The old naming convention is used to prevent breaking kernel aware debuggers. */ +typedef struct tskTaskControlBlock * TaskHandle_t; + +/* + * Defines the prototype to which the application task hook function must + * conform. + */ +typedef BaseType_t (* TaskHookFunction_t)( void * ); + +/* Task states returned by eTaskGetState. */ +typedef enum +{ + eRunning = 0, /* A task is querying the state of itself, so must be running. */ + eReady, /* The task being queried is in a read or pending ready list. */ + eBlocked, /* The task being queried is in the Blocked state. */ + eSuspended, /* The task being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */ + eDeleted, /* The task being queried has been deleted, but its TCB has not yet been freed. */ + eInvalid /* Used as an 'invalid state' value. */ +} eTaskState; + +/* Actions that can be performed when vTaskNotify() is called. */ +typedef enum +{ + eNoAction = 0, /* Notify the task without updating its notify value. */ + eSetBits, /* Set bits in the task's notification value. */ + eIncrement, /* Increment the task's notification value. */ + eSetValueWithOverwrite, /* Set the task's notification value to a specific value even if the previous value has not yet been read by the task. */ + eSetValueWithoutOverwrite /* Set the task's notification value if the previous value has been read by the task. */ +} eNotifyAction; + +/* + * Used internally only. + */ +typedef struct xTIME_OUT +{ + BaseType_t xOverflowCount; + TickType_t xTimeOnEntering; +} TimeOut_t; + +/* + * Defines the memory ranges allocated to the task when an MPU is used. + */ +typedef struct xMEMORY_REGION +{ + void * pvBaseAddress; + uint32_t ulLengthInBytes; + uint32_t ulParameters; +} MemoryRegion_t; + +/* + * Parameters required to create an MPU protected task. + */ +typedef struct xTASK_PARAMETERS +{ + TaskFunction_t pvTaskCode; + const char * pcName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + configSTACK_DEPTH_TYPE usStackDepth; + void * pvParameters; + UBaseType_t uxPriority; + StackType_t * puxStackBuffer; + MemoryRegion_t xRegions[ portNUM_CONFIGURABLE_REGIONS ]; + #if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + StaticTask_t * const pxTaskBuffer; + #endif +} TaskParameters_t; + +/* Used with the uxTaskGetSystemState() function to return the state of each task + * in the system. */ +typedef struct xTASK_STATUS +{ + TaskHandle_t xHandle; /* The handle of the task to which the rest of the information in the structure relates. */ + const char * pcTaskName; /* A pointer to the task's name. This value will be invalid if the task was deleted since the structure was populated! */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + UBaseType_t xTaskNumber; /* A number unique to the task. */ + eTaskState eCurrentState; /* The state in which the task existed when the structure was populated. */ + UBaseType_t uxCurrentPriority; /* The priority at which the task was running (may be inherited) when the structure was populated. */ + UBaseType_t uxBasePriority; /* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex. Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */ + uint32_t ulRunTimeCounter; /* The total run time allocated to the task so far, as defined by the run time stats clock. See https://www.FreeRTOS.org/rtos-run-time-stats.html. Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */ + StackType_t * pxStackBase; /* Points to the lowest address of the task's stack area. */ + configSTACK_DEPTH_TYPE usStackHighWaterMark; /* The minimum amount of stack space that has remained for the task since the task was created. The closer this value is to zero the closer the task has come to overflowing its stack. */ +} TaskStatus_t; + +/* Possible return values for eTaskConfirmSleepModeStatus(). */ +typedef enum +{ + eAbortSleep = 0, /* A task has been made ready or a context switch pended since portSUPPORESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode. */ + eStandardSleep, /* Enter a sleep mode that will not last any longer than the expected idle time. */ + eNoTasksWaitingTimeout /* No tasks are waiting for a timeout so it is safe to enter a sleep mode that can only be exited by an external interrupt. */ +} eSleepModeStatus; + +/** + * Defines the priority used by the idle task. This must not be modified. + * + * \ingroup TaskUtils + */ +#define tskIDLE_PRIORITY ( ( UBaseType_t ) 0U ) + +/** + * task. h + * + * Macro for forcing a context switch. + * + * \defgroup taskYIELD taskYIELD + * \ingroup SchedulerControl + */ +#define taskYIELD() portYIELD() + +/** + * task. h + * + * Macro to mark the start of a critical code region. Preemptive context + * switches cannot occur when in a critical region. + * + * NOTE: This may alter the stack (depending on the portable implementation) + * so must be used with care! + * + * \defgroup taskENTER_CRITICAL taskENTER_CRITICAL + * \ingroup SchedulerControl + */ +#define taskENTER_CRITICAL() portENTER_CRITICAL() +#define taskENTER_CRITICAL_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR() + +/** + * task. h + * + * Macro to mark the end of a critical code region. Preemptive context + * switches cannot occur when in a critical region. + * + * NOTE: This may alter the stack (depending on the portable implementation) + * so must be used with care! + * + * \defgroup taskEXIT_CRITICAL taskEXIT_CRITICAL + * \ingroup SchedulerControl + */ +#define taskEXIT_CRITICAL() portEXIT_CRITICAL() +#define taskEXIT_CRITICAL_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) + +/** + * task. h + * + * Macro to disable all maskable interrupts. + * + * \defgroup taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS + * \ingroup SchedulerControl + */ +#define taskDISABLE_INTERRUPTS() portDISABLE_INTERRUPTS() + +/** + * task. h + * + * Macro to enable microcontroller interrupts. + * + * \defgroup taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS + * \ingroup SchedulerControl + */ +#define taskENABLE_INTERRUPTS() portENABLE_INTERRUPTS() + +/* Definitions returned by xTaskGetSchedulerState(). taskSCHEDULER_SUSPENDED is + * 0 to generate more optimal code when configASSERT() is defined as the constant + * is used in assert() statements. */ +#define taskSCHEDULER_SUSPENDED ( ( BaseType_t ) 0 ) +#define taskSCHEDULER_NOT_STARTED ( ( BaseType_t ) 1 ) +#define taskSCHEDULER_RUNNING ( ( BaseType_t ) 2 ) + + +/*----------------------------------------------------------- +* TASK CREATION API +*----------------------------------------------------------*/ + +/** + * task. h + * 
+ * BaseType_t xTaskCreate(
+ *                            TaskFunction_t pvTaskCode,
+ *                            const char * const pcName,
+ *                            configSTACK_DEPTH_TYPE usStackDepth,
+ *                            void *pvParameters,
+ *                            UBaseType_t uxPriority,
+ *                            TaskHandle_t *pvCreatedTask
+ *                        );
+ *
+ * + * Create a new task and add it to the list of tasks that are ready to run. + * + * Internally, within the FreeRTOS implementation, tasks use two blocks of + * memory. The first block is used to hold the task's data structures. The + * second block is used by the task as its stack. If a task is created using + * xTaskCreate() then both blocks of memory are automatically dynamically + * allocated inside the xTaskCreate() function. (see + * https://www.FreeRTOS.org/a00111.html). If a task is created using + * xTaskCreateStatic() then the application writer must provide the required + * memory. xTaskCreateStatic() therefore allows a task to be created without + * using any dynamic memory allocation. + * + * See xTaskCreateStatic() for a version that does not use any dynamic memory + * allocation. + * + * xTaskCreate() can only be used to create a task that has unrestricted + * access to the entire microcontroller memory map. Systems that include MPU + * support can alternatively create an MPU constrained task using + * xTaskCreateRestricted(). + * + * @param pvTaskCode Pointer to the task entry function. Tasks + * must be implemented to never return (i.e. continuous loop). + * + * @param pcName A descriptive name for the task. This is mainly used to + * facilitate debugging. Max length defined by configMAX_TASK_NAME_LEN - default + * is 16. + * + * @param usStackDepth The size of the task stack specified as the number of + * variables the stack can hold - not the number of bytes. For example, if + * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes + * will be allocated for stack storage. + * + * @param pvParameters Pointer that will be used as the parameter for the task + * being created. + * + * @param uxPriority The priority at which the task should run. Systems that + * include MPU support can optionally create tasks in a privileged (system) + * mode by setting bit portPRIVILEGE_BIT of the priority parameter. For + * example, to create a privileged task at priority 2 the uxPriority parameter + * should be set to ( 2 | portPRIVILEGE_BIT ). + * + * @param pvCreatedTask Used to pass back a handle by which the created task + * can be referenced. + * + * @return pdPASS if the task was successfully created and added to a ready + * list, otherwise an error code defined in the file projdefs.h + * + * Example usage: + * 
+ * // Task to be created.
+ * void vTaskCode( void * pvParameters )
+ * {
+ *   for( ;; )
+ *   {
+ *       // Task code goes here.
+ *   }
+ * }
+ *
+ * // Function that creates a task.
+ * void vOtherFunction( void )
+ * {
+ * static uint8_t ucParameterToPass;
+ * TaskHandle_t xHandle = NULL;
+ *
+ *   // Create the task, storing the handle.  Note that the passed parameter ucParameterToPass
+ *   // must exist for the lifetime of the task, so in this case is declared static.  If it was just an
+ *   // an automatic stack variable it might no longer exist, or at least have been corrupted, by the time
+ *   // the new task attempts to access it.
+ *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );
+ *   configASSERT( xHandle );
+ *
+ *   // Use the handle to delete the task.
+ *   if( xHandle != NULL )
+ *   {
+ *      vTaskDelete( xHandle );
+ *   }
+ * }
+ *
+ * \defgroup xTaskCreate xTaskCreate + * \ingroup Tasks + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + BaseType_t xTaskCreate( TaskFunction_t pxTaskCode, + const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const configSTACK_DEPTH_TYPE usStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION; +#endif + +/** + * task. h + * 
+ * TaskHandle_t xTaskCreateStatic( TaskFunction_t pvTaskCode,
+ *                               const char * const pcName,
+ *                               uint32_t ulStackDepth,
+ *                               void *pvParameters,
+ *                               UBaseType_t uxPriority,
+ *                               StackType_t *pxStackBuffer,
+ *                               StaticTask_t *pxTaskBuffer );
+ *
+ * + * Create a new task and add it to the list of tasks that are ready to run. + * + * Internally, within the FreeRTOS implementation, tasks use two blocks of + * memory. The first block is used to hold the task's data structures. The + * second block is used by the task as its stack. If a task is created using + * xTaskCreate() then both blocks of memory are automatically dynamically + * allocated inside the xTaskCreate() function. (see + * https://www.FreeRTOS.org/a00111.html). If a task is created using + * xTaskCreateStatic() then the application writer must provide the required + * memory. xTaskCreateStatic() therefore allows a task to be created without + * using any dynamic memory allocation. + * + * @param pvTaskCode Pointer to the task entry function. Tasks + * must be implemented to never return (i.e. continuous loop). + * + * @param pcName A descriptive name for the task. This is mainly used to + * facilitate debugging. The maximum length of the string is defined by + * configMAX_TASK_NAME_LEN in FreeRTOSConfig.h. + * + * @param ulStackDepth The size of the task stack specified as the number of + * variables the stack can hold - not the number of bytes. For example, if + * the stack is 32-bits wide and ulStackDepth is defined as 100 then 400 bytes + * will be allocated for stack storage. + * + * @param pvParameters Pointer that will be used as the parameter for the task + * being created. + * + * @param uxPriority The priority at which the task will run. + * + * @param pxStackBuffer Must point to a StackType_t array that has at least + * ulStackDepth indexes - the array will then be used as the task's stack, + * removing the need for the stack to be allocated dynamically. + * + * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will + * then be used to hold the task's data structures, removing the need for the + * memory to be allocated dynamically. + * + * @return If neither pxStackBuffer or pxTaskBuffer are NULL, then the task will + * be created and a handle to the created task is returned. If either + * pxStackBuffer or pxTaskBuffer are NULL then the task will not be created and + * NULL is returned. + * + * Example usage: + * 
+ *
+ *  // Dimensions the buffer that the task being created will use as its stack.
+ *  // NOTE:  This is the number of words the stack will hold, not the number of
+ *  // bytes.  For example, if each stack item is 32-bits, and this is set to 100,
+ *  // then 400 bytes (100 * 32-bits) will be allocated.
+ #define STACK_SIZE 200
+ *
+ *  // Structure that will hold the TCB of the task being created.
+ *  StaticTask_t xTaskBuffer;
+ *
+ *  // Buffer that the task being created will use as its stack.  Note this is
+ *  // an array of StackType_t variables.  The size of StackType_t is dependent on
+ *  // the RTOS port.
+ *  StackType_t xStack[ STACK_SIZE ];
+ *
+ *  // Function that implements the task being created.
+ *  void vTaskCode( void * pvParameters )
+ *  {
+ *      // The parameter value is expected to be 1 as 1 is passed in the
+ *      // pvParameters value in the call to xTaskCreateStatic().
+ *      configASSERT( ( uint32_t ) pvParameters == 1UL );
+ *
+ *      for( ;; )
+ *      {
+ *          // Task code goes here.
+ *      }
+ *  }
+ *
+ *  // Function that creates a task.
+ *  void vOtherFunction( void )
+ *  {
+ *      TaskHandle_t xHandle = NULL;
+ *
+ *      // Create the task without using any dynamic memory allocation.
+ *      xHandle = xTaskCreateStatic(
+ *                    vTaskCode,       // Function that implements the task.
+ *                    "NAME",          // Text name for the task.
+ *                    STACK_SIZE,      // Stack size in words, not bytes.
+ *                    ( void * ) 1,    // Parameter passed into the task.
+ *                    tskIDLE_PRIORITY,// Priority at which the task is created.
+ *                    xStack,          // Array to use as the task's stack.
+ *                    &xTaskBuffer );  // Variable to hold the task's data structure.
+ *
+ *      // puxStackBuffer and pxTaskBuffer were not NULL, so the task will have
+ *      // been created, and xHandle will be the task's handle.  Use the handle
+ *      // to suspend the task.
+ *      vTaskSuspend( xHandle );
+ *  }
+ *
+ * \defgroup xTaskCreateStatic xTaskCreateStatic + * \ingroup Tasks + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode, + const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const uint32_t ulStackDepth, + void * const pvParameters, + UBaseType_t uxPriority, + StackType_t * const puxStackBuffer, + StaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION; +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/** + * task. h + * 
+ * BaseType_t xTaskCreateRestricted( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );
+ *
+ * + * Only available when configSUPPORT_DYNAMIC_ALLOCATION is set to 1. + * + * xTaskCreateRestricted() should only be used in systems that include an MPU + * implementation. + * + * Create a new task and add it to the list of tasks that are ready to run. + * The function parameters define the memory regions and associated access + * permissions allocated to the task. + * + * See xTaskCreateRestrictedStatic() for a version that does not use any + * dynamic memory allocation. + * + * @param pxTaskDefinition Pointer to a structure that contains a member + * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API + * documentation) plus an optional stack buffer and the memory region + * definitions. + * + * @param pxCreatedTask Used to pass back a handle by which the created task + * can be referenced. + * + * @return pdPASS if the task was successfully created and added to a ready + * list, otherwise an error code defined in the file projdefs.h + * + * Example usage: + * 
+ * // Create an TaskParameters_t structure that defines the task to be created.
+ * static const TaskParameters_t xCheckTaskParameters =
+ * {
+ *  vATask,     // pvTaskCode - the function that implements the task.
+ *  "ATask",    // pcName - just a text name for the task to assist debugging.
+ *  100,        // usStackDepth - the stack size DEFINED IN WORDS.
+ *  NULL,       // pvParameters - passed into the task function as the function parameters.
+ *  ( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+ *  cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
+ *
+ *  // xRegions - Allocate up to three separate memory regions for access by
+ *  // the task, with appropriate access permissions.  Different processors have
+ *  // different memory alignment requirements - refer to the FreeRTOS documentation
+ *  // for full information.
+ *  {
+ *      // Base address                 Length  Parameters
+ *      { cReadWriteArray,              32,     portMPU_REGION_READ_WRITE },
+ *      { cReadOnlyArray,               32,     portMPU_REGION_READ_ONLY },
+ *      { cPrivilegedOnlyAccessArray,   128,    portMPU_REGION_PRIVILEGED_READ_WRITE }
+ *  }
+ * };
+ *
+ * int main( void )
+ * {
+ * TaskHandle_t xHandle;
+ *
+ *  // Create a task from the const structure defined above.  The task handle
+ *  // is requested (the second parameter is not NULL) but in this case just for
+ *  // demonstration purposes as its not actually used.
+ *  xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
+ *
+ *  // Start the scheduler.
+ *  vTaskStartScheduler();
+ *
+ *  // Will only get here if there was insufficient memory to create the idle
+ *  // and/or timer task.
+ *  for( ;; );
+ * }
+ *
+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted + * \ingroup Tasks + */ +#if ( portUSING_MPU_WRAPPERS == 1 ) + BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, + TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION; +#endif + +/** + * task. h + * 
+ * BaseType_t xTaskCreateRestrictedStatic( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );
+ *
+ * + * Only available when configSUPPORT_STATIC_ALLOCATION is set to 1. + * + * xTaskCreateRestrictedStatic() should only be used in systems that include an + * MPU implementation. + * + * Internally, within the FreeRTOS implementation, tasks use two blocks of + * memory. The first block is used to hold the task's data structures. The + * second block is used by the task as its stack. If a task is created using + * xTaskCreateRestricted() then the stack is provided by the application writer, + * and the memory used to hold the task's data structure is automatically + * dynamically allocated inside the xTaskCreateRestricted() function. If a task + * is created using xTaskCreateRestrictedStatic() then the application writer + * must provide the memory used to hold the task's data structures too. + * xTaskCreateRestrictedStatic() therefore allows a memory protected task to be + * created without using any dynamic memory allocation. + * + * @param pxTaskDefinition Pointer to a structure that contains a member + * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API + * documentation) plus an optional stack buffer and the memory region + * definitions. If configSUPPORT_STATIC_ALLOCATION is set to 1 the structure + * contains an additional member, which is used to point to a variable of type + * StaticTask_t - which is then used to hold the task's data structure. + * + * @param pxCreatedTask Used to pass back a handle by which the created task + * can be referenced. + * + * @return pdPASS if the task was successfully created and added to a ready + * list, otherwise an error code defined in the file projdefs.h + * + * Example usage: + * 
+ * // Create an TaskParameters_t structure that defines the task to be created.
+ * // The StaticTask_t variable is only included in the structure when
+ * // configSUPPORT_STATIC_ALLOCATION is set to 1.  The PRIVILEGED_DATA macro can
+ * // be used to force the variable into the RTOS kernel's privileged data area.
+ * static PRIVILEGED_DATA StaticTask_t xTaskBuffer;
+ * static const TaskParameters_t xCheckTaskParameters =
+ * {
+ *  vATask,     // pvTaskCode - the function that implements the task.
+ *  "ATask",    // pcName - just a text name for the task to assist debugging.
+ *  100,        // usStackDepth - the stack size DEFINED IN WORDS.
+ *  NULL,       // pvParameters - passed into the task function as the function parameters.
+ *  ( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+ *  cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
+ *
+ *  // xRegions - Allocate up to three separate memory regions for access by
+ *  // the task, with appropriate access permissions.  Different processors have
+ *  // different memory alignment requirements - refer to the FreeRTOS documentation
+ *  // for full information.
+ *  {
+ *      // Base address                 Length  Parameters
+ *      { cReadWriteArray,              32,     portMPU_REGION_READ_WRITE },
+ *      { cReadOnlyArray,               32,     portMPU_REGION_READ_ONLY },
+ *      { cPrivilegedOnlyAccessArray,   128,    portMPU_REGION_PRIVILEGED_READ_WRITE }
+ *  }
+ *
+ *  &xTaskBuffer; // Holds the task's data structure.
+ * };
+ *
+ * int main( void )
+ * {
+ * TaskHandle_t xHandle;
+ *
+ *  // Create a task from the const structure defined above.  The task handle
+ *  // is requested (the second parameter is not NULL) but in this case just for
+ *  // demonstration purposes as its not actually used.
+ *  xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
+ *
+ *  // Start the scheduler.
+ *  vTaskStartScheduler();
+ *
+ *  // Will only get here if there was insufficient memory to create the idle
+ *  // and/or timer task.
+ *  for( ;; );
+ * }
+ *
+ * \defgroup xTaskCreateRestrictedStatic xTaskCreateRestrictedStatic + * \ingroup Tasks + */ +#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, + TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION; +#endif + +/** + * task. h + * 
+ * void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions );
+ *
+ * + * Memory regions are assigned to a restricted task when the task is created by + * a call to xTaskCreateRestricted(). These regions can be redefined using + * vTaskAllocateMPURegions(). + * + * @param xTask The handle of the task being updated. + * + * @param xRegions A pointer to an MemoryRegion_t structure that contains the + * new memory region definitions. + * + * Example usage: + * 
+ * // Define an array of MemoryRegion_t structures that configures an MPU region
+ * // allowing read/write access for 1024 bytes starting at the beginning of the
+ * // ucOneKByte array.  The other two of the maximum 3 definable regions are
+ * // unused so set to zero.
+ * static const MemoryRegion_t xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] =
+ * {
+ *  // Base address     Length      Parameters
+ *  { ucOneKByte,       1024,       portMPU_REGION_READ_WRITE },
+ *  { 0,                0,          0 },
+ *  { 0,                0,          0 }
+ * };
+ *
+ * void vATask( void *pvParameters )
+ * {
+ *  // This task was created such that it has access to certain regions of
+ *  // memory as defined by the MPU configuration.  At some point it is
+ *  // desired that these MPU regions are replaced with that defined in the
+ *  // xAltRegions const struct above.  Use a call to vTaskAllocateMPURegions()
+ *  // for this purpose.  NULL is used as the task handle to indicate that this
+ *  // function should modify the MPU regions of the calling task.
+ *  vTaskAllocateMPURegions( NULL, xAltRegions );
+ *
+ *  // Now the task can continue its function, but from this point on can only
+ *  // access its stack and the ucOneKByte array (unless any other statically
+ *  // defined or shared regions have been declared elsewhere).
+ * }
+ *
+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted + * \ingroup Tasks + */ +void vTaskAllocateMPURegions( TaskHandle_t xTask, + const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
+ * void vTaskDelete( TaskHandle_t xTask );
+ *
+ * + * INCLUDE_vTaskDelete must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Remove a task from the RTOS real time kernel's management. The task being + * deleted will be removed from all ready, blocked, suspended and event lists. + * + * NOTE: The idle task is responsible for freeing the kernel allocated + * memory from tasks that have been deleted. It is therefore important that + * the idle task is not starved of microcontroller processing time if your + * application makes any calls to vTaskDelete (). Memory allocated by the + * task code is not automatically freed, and should be freed before the task + * is deleted. + * + * See the demo application file death.c for sample code that utilises + * vTaskDelete (). + * + * @param xTask The handle of the task to be deleted. Passing NULL will + * cause the calling task to be deleted. + * + * Example usage: + * 
+ * void vOtherFunction( void )
+ * {
+ * TaskHandle_t xHandle;
+ *
+ *   // Create the task, storing the handle.
+ *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+ *
+ *   // Use the handle to delete the task.
+ *   vTaskDelete( xHandle );
+ * }
+ *
+ * \defgroup vTaskDelete vTaskDelete + * \ingroup Tasks + */ +void vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION; + +/*----------------------------------------------------------- +* TASK CONTROL API +*----------------------------------------------------------*/ + +/** + * task. h + * 
+ * void vTaskDelay( const TickType_t xTicksToDelay );
+ *
+ * + * Delay a task for a given number of ticks. The actual time that the + * task remains blocked depends on the tick rate. The constant + * portTICK_PERIOD_MS can be used to calculate real time from the tick + * rate - with the resolution of one tick period. + * + * INCLUDE_vTaskDelay must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * + * vTaskDelay() specifies a time at which the task wishes to unblock relative to + * the time at which vTaskDelay() is called. For example, specifying a block + * period of 100 ticks will cause the task to unblock 100 ticks after + * vTaskDelay() is called. vTaskDelay() does not therefore provide a good method + * of controlling the frequency of a periodic task as the path taken through the + * code, as well as other task and interrupt activity, will effect the frequency + * at which vTaskDelay() gets called and therefore the time at which the task + * next executes. See xTaskDelayUntil() for an alternative API function designed + * to facilitate fixed frequency execution. It does this by specifying an + * absolute time (rather than a relative time) at which the calling task should + * unblock. + * + * @param xTicksToDelay The amount of time, in tick periods, that + * the calling task should block. + * + * Example usage: + * + * void vTaskFunction( void * pvParameters ) + * { + * // Block for 500ms. + * const TickType_t xDelay = 500 / portTICK_PERIOD_MS; + * + * for( ;; ) + * { + * // Simply toggle the LED every 500ms, blocking between each toggle. + * vToggleLED(); + * vTaskDelay( xDelay ); + * } + * } + * + * \defgroup vTaskDelay vTaskDelay + * \ingroup TaskCtrl + */ +void vTaskDelay( const TickType_t xTicksToDelay ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
+ * BaseType_t xTaskDelayUntil( TickType_t *pxPreviousWakeTime, const TickType_t xTimeIncrement );
+ *
+ * + * INCLUDE_xTaskDelayUntil must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Delay a task until a specified time. This function can be used by periodic + * tasks to ensure a constant execution frequency. + * + * This function differs from vTaskDelay () in one important aspect: vTaskDelay () will + * cause a task to block for the specified number of ticks from the time vTaskDelay () is + * called. It is therefore difficult to use vTaskDelay () by itself to generate a fixed + * execution frequency as the time between a task starting to execute and that task + * calling vTaskDelay () may not be fixed [the task may take a different path though the + * code between calls, or may get interrupted or preempted a different number of times + * each time it executes]. + * + * Whereas vTaskDelay () specifies a wake time relative to the time at which the function + * is called, xTaskDelayUntil () specifies the absolute (exact) time at which it wishes to + * unblock. + * + * The macro pdMS_TO_TICKS() can be used to calculate the number of ticks from a + * time specified in milliseconds with a resolution of one tick period. + * + * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the + * task was last unblocked. The variable must be initialised with the current time + * prior to its first use (see the example below). Following this the variable is + * automatically updated within xTaskDelayUntil (). + * + * @param xTimeIncrement The cycle time period. The task will be unblocked at + * time *pxPreviousWakeTime + xTimeIncrement. Calling xTaskDelayUntil with the + * same xTimeIncrement parameter value will cause the task to execute with + * a fixed interface period. + * + * @return Value which can be used to check whether the task was actually delayed. + * Will be pdTRUE if the task way delayed and pdFALSE otherwise. A task will not + * be delayed if the next expected wake time is in the past. + * + * Example usage: + * 
+ * // Perform an action every 10 ticks.
+ * void vTaskFunction( void * pvParameters )
+ * {
+ * TickType_t xLastWakeTime;
+ * const TickType_t xFrequency = 10;
+ * BaseType_t xWasDelayed;
+ *
+ *     // Initialise the xLastWakeTime variable with the current time.
+ *     xLastWakeTime = xTaskGetTickCount ();
+ *     for( ;; )
+ *     {
+ *         // Wait for the next cycle.
+ *         xWasDelayed = xTaskDelayUntil( &xLastWakeTime, xFrequency );
+ *
+ *         // Perform action here. xWasDelayed value can be used to determine
+ *         // whether a deadline was missed if the code here took too long.
+ *     }
+ * }
+ *
+ * \defgroup xTaskDelayUntil xTaskDelayUntil + * \ingroup TaskCtrl + */ +BaseType_t xTaskDelayUntil( TickType_t * const pxPreviousWakeTime, + const TickType_t xTimeIncrement ) PRIVILEGED_FUNCTION; + +/* + * vTaskDelayUntil() is the older version of xTaskDelayUntil() and does not + * return a value. + */ +#define vTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement ) \ +{ \ + ( void ) xTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement ); \ +} + + +/** + * task. h + * 
+ * BaseType_t xTaskAbortDelay( TaskHandle_t xTask );
+ *
+ * + * INCLUDE_xTaskAbortDelay must be defined as 1 in FreeRTOSConfig.h for this + * function to be available. + * + * A task will enter the Blocked state when it is waiting for an event. The + * event it is waiting for can be a temporal event (waiting for a time), such + * as when vTaskDelay() is called, or an event on an object, such as when + * xQueueReceive() or ulTaskNotifyTake() is called. If the handle of a task + * that is in the Blocked state is used in a call to xTaskAbortDelay() then the + * task will leave the Blocked state, and return from whichever function call + * placed the task into the Blocked state. + * + * There is no 'FromISR' version of this function as an interrupt would need to + * know which object a task was blocked on in order to know which actions to + * take. For example, if the task was blocked on a queue the interrupt handler + * would then need to know if the queue was locked. + * + * @param xTask The handle of the task to remove from the Blocked state. + * + * @return If the task referenced by xTask was not in the Blocked state then + * pdFAIL is returned. Otherwise pdPASS is returned. + * + * \defgroup xTaskAbortDelay xTaskAbortDelay + * \ingroup TaskCtrl + */ +BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
+ * UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask );
+ *
+ * + * INCLUDE_uxTaskPriorityGet must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Obtain the priority of any task. + * + * @param xTask Handle of the task to be queried. Passing a NULL + * handle results in the priority of the calling task being returned. + * + * @return The priority of xTask. + * + * Example usage: + * 
+ * void vAFunction( void )
+ * {
+ * TaskHandle_t xHandle;
+ *
+ *   // Create a task, storing the handle.
+ *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+ *
+ *   // ...
+ *
+ *   // Use the handle to obtain the priority of the created task.
+ *   // It was created with tskIDLE_PRIORITY, but may have changed
+ *   // it itself.
+ *   if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )
+ *   {
+ *       // The task has changed it's priority.
+ *   }
+ *
+ *   // ...
+ *
+ *   // Is our priority higher than the created task?
+ *   if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )
+ *   {
+ *       // Our priority (obtained using NULL handle) is higher.
+ *   }
+ * }
+ *
+ * \defgroup uxTaskPriorityGet uxTaskPriorityGet + * \ingroup TaskCtrl + */ +UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
+ * UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask );
+ *
+ * + * A version of uxTaskPriorityGet() that can be used from an ISR. + */ +UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
+ * eTaskState eTaskGetState( TaskHandle_t xTask );
+ *
+ * + * INCLUDE_eTaskGetState must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Obtain the state of any task. States are encoded by the eTaskState + * enumerated type. + * + * @param xTask Handle of the task to be queried. + * + * @return The state of xTask at the time the function was called. Note the + * state of the task might change between the function being called, and the + * functions return value being tested by the calling task. + */ +eTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
+ * void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState );
+ *
+ * + * configUSE_TRACE_FACILITY must be defined as 1 for this function to be + * available. See the configuration section for more information. + * + * Populates a TaskStatus_t structure with information about a task. + * + * @param xTask Handle of the task being queried. If xTask is NULL then + * information will be returned about the calling task. + * + * @param pxTaskStatus A pointer to the TaskStatus_t structure that will be + * filled with information about the task referenced by the handle passed using + * the xTask parameter. + * + * @xGetFreeStackSpace The TaskStatus_t structure contains a member to report + * the stack high water mark of the task being queried. Calculating the stack + * high water mark takes a relatively long time, and can make the system + * temporarily unresponsive - so the xGetFreeStackSpace parameter is provided to + * allow the high water mark checking to be skipped. The high watermark value + * will only be written to the TaskStatus_t structure if xGetFreeStackSpace is + * not set to pdFALSE; + * + * @param eState The TaskStatus_t structure contains a member to report the + * state of the task being queried. Obtaining the task state is not as fast as + * a simple assignment - so the eState parameter is provided to allow the state + * information to be omitted from the TaskStatus_t structure. To obtain state + * information then set eState to eInvalid - otherwise the value passed in + * eState will be reported as the task state in the TaskStatus_t structure. + * + * Example usage: + * 
+ * void vAFunction( void )
+ * {
+ * TaskHandle_t xHandle;
+ * TaskStatus_t xTaskDetails;
+ *
+ *  // Obtain the handle of a task from its name.
+ *  xHandle = xTaskGetHandle( "Task_Name" );
+ *
+ *  // Check the handle is not NULL.
+ *  configASSERT( xHandle );
+ *
+ *  // Use the handle to obtain further information about the task.
+ *  vTaskGetInfo( xHandle,
+ *                &xTaskDetails,
+ *                pdTRUE, // Include the high water mark in xTaskDetails.
+ *                eInvalid ); // Include the task state in xTaskDetails.
+ * }
+ *
+ * \defgroup vTaskGetInfo vTaskGetInfo + * \ingroup TaskCtrl + */ +void vTaskGetInfo( TaskHandle_t xTask, + TaskStatus_t * pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
+ * void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority );
+ *
+ * + * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Set the priority of any task. + * + * A context switch will occur before the function returns if the priority + * being set is higher than the currently executing task. + * + * @param xTask Handle to the task for which the priority is being set. + * Passing a NULL handle results in the priority of the calling task being set. + * + * @param uxNewPriority The priority to which the task will be set. + * + * Example usage: + * 
+ * void vAFunction( void )
+ * {
+ * TaskHandle_t xHandle;
+ *
+ *   // Create a task, storing the handle.
+ *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+ *
+ *   // ...
+ *
+ *   // Use the handle to raise the priority of the created task.
+ *   vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );
+ *
+ *   // ...
+ *
+ *   // Use a NULL handle to raise our priority to the same value.
+ *   vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );
+ * }
+ *
+ * \defgroup vTaskPrioritySet vTaskPrioritySet + * \ingroup TaskCtrl + */ +void vTaskPrioritySet( TaskHandle_t xTask, + UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
+ * void vTaskSuspend( TaskHandle_t xTaskToSuspend );
+ *
+ * + * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Suspend any task. When suspended a task will never get any microcontroller + * processing time, no matter what its priority. + * + * Calls to vTaskSuspend are not accumulative - + * i.e. calling vTaskSuspend () twice on the same task still only requires one + * call to vTaskResume () to ready the suspended task. + * + * @param xTaskToSuspend Handle to the task being suspended. Passing a NULL + * handle will cause the calling task to be suspended. + * + * Example usage: + * 
+ * void vAFunction( void )
+ * {
+ * TaskHandle_t xHandle;
+ *
+ *   // Create a task, storing the handle.
+ *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+ *
+ *   // ...
+ *
+ *   // Use the handle to suspend the created task.
+ *   vTaskSuspend( xHandle );
+ *
+ *   // ...
+ *
+ *   // The created task will not run during this period, unless
+ *   // another task calls vTaskResume( xHandle ).
+ *
+ *   //...
+ *
+ *
+ *   // Suspend ourselves.
+ *   vTaskSuspend( NULL );
+ *
+ *   // We cannot get here unless another task calls vTaskResume
+ *   // with our handle as the parameter.
+ * }
+ *
+ * \defgroup vTaskSuspend vTaskSuspend + * \ingroup TaskCtrl + */ +void vTaskSuspend( TaskHandle_t xTaskToSuspend ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
+ * void vTaskResume( TaskHandle_t xTaskToResume );
+ *
+ * + * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available. + * See the configuration section for more information. + * + * Resumes a suspended task. + * + * A task that has been suspended by one or more calls to vTaskSuspend () + * will be made available for running again by a single call to + * vTaskResume (). + * + * @param xTaskToResume Handle to the task being readied. + * + * Example usage: + * 
+ * void vAFunction( void )
+ * {
+ * TaskHandle_t xHandle;
+ *
+ *   // Create a task, storing the handle.
+ *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+ *
+ *   // ...
+ *
+ *   // Use the handle to suspend the created task.
+ *   vTaskSuspend( xHandle );
+ *
+ *   // ...
+ *
+ *   // The created task will not run during this period, unless
+ *   // another task calls vTaskResume( xHandle ).
+ *
+ *   //...
+ *
+ *
+ *   // Resume the suspended task ourselves.
+ *   vTaskResume( xHandle );
+ *
+ *   // The created task will once again get microcontroller processing
+ *   // time in accordance with its priority within the system.
+ * }
+ *
+ * \defgroup vTaskResume vTaskResume + * \ingroup TaskCtrl + */ +void vTaskResume( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
+ * void xTaskResumeFromISR( TaskHandle_t xTaskToResume );
+ *
+ * + * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be + * available. See the configuration section for more information. + * + * An implementation of vTaskResume() that can be called from within an ISR. + * + * A task that has been suspended by one or more calls to vTaskSuspend () + * will be made available for running again by a single call to + * xTaskResumeFromISR (). + * + * xTaskResumeFromISR() should not be used to synchronise a task with an + * interrupt if there is a chance that the interrupt could arrive prior to the + * task being suspended - as this can lead to interrupts being missed. Use of a + * semaphore as a synchronisation mechanism would avoid this eventuality. + * + * @param xTaskToResume Handle to the task being readied. + * + * @return pdTRUE if resuming the task should result in a context switch, + * otherwise pdFALSE. This is used by the ISR to determine if a context switch + * may be required following the ISR. + * + * \defgroup vTaskResumeFromISR vTaskResumeFromISR + * \ingroup TaskCtrl + */ +BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION; + +/*----------------------------------------------------------- +* SCHEDULER CONTROL +*----------------------------------------------------------*/ + +/** + * task. h + * 
+ * void vTaskStartScheduler( void );
+ *
+ * + * Starts the real time kernel tick processing. After calling the kernel + * has control over which tasks are executed and when. + * + * See the demo application file main.c for an example of creating + * tasks and starting the kernel. + * + * Example usage: + * 
+ * void vAFunction( void )
+ * {
+ *   // Create at least one task before starting the kernel.
+ *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+ *
+ *   // Start the real time kernel with preemption.
+ *   vTaskStartScheduler ();
+ *
+ *   // Will not get here unless a task calls vTaskEndScheduler ()
+ * }
+ *
+ * + * \defgroup vTaskStartScheduler vTaskStartScheduler + * \ingroup SchedulerControl + */ +void vTaskStartScheduler( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
+ * void vTaskEndScheduler( void );
+ *
+ * + * NOTE: At the time of writing only the x86 real mode port, which runs on a PC + * in place of DOS, implements this function. + * + * Stops the real time kernel tick. All created tasks will be automatically + * deleted and multitasking (either preemptive or cooperative) will + * stop. Execution then resumes from the point where vTaskStartScheduler () + * was called, as if vTaskStartScheduler () had just returned. + * + * See the demo application file main. c in the demo/PC directory for an + * example that uses vTaskEndScheduler (). + * + * vTaskEndScheduler () requires an exit function to be defined within the + * portable layer (see vPortEndScheduler () in port. c for the PC port). This + * performs hardware specific operations such as stopping the kernel tick. + * + * vTaskEndScheduler () will cause all of the resources allocated by the + * kernel to be freed - but will not free resources allocated by application + * tasks. + * + * Example usage: + * 
+ * void vTaskCode( void * pvParameters )
+ * {
+ *   for( ;; )
+ *   {
+ *       // Task code goes here.
+ *
+ *       // At some point we want to end the real time kernel processing
+ *       // so call ...
+ *       vTaskEndScheduler ();
+ *   }
+ * }
+ *
+ * void vAFunction( void )
+ * {
+ *   // Create at least one task before starting the kernel.
+ *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+ *
+ *   // Start the real time kernel with preemption.
+ *   vTaskStartScheduler ();
+ *
+ *   // Will only get here when the vTaskCode () task has called
+ *   // vTaskEndScheduler ().  When we get here we are back to single task
+ *   // execution.
+ * }
+ *
+ * + * \defgroup vTaskEndScheduler vTaskEndScheduler + * \ingroup SchedulerControl + */ +void vTaskEndScheduler( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
+ * void vTaskSuspendAll( void );
+ *
+ * + * Suspends the scheduler without disabling interrupts. Context switches will + * not occur while the scheduler is suspended. + * + * After calling vTaskSuspendAll () the calling task will continue to execute + * without risk of being swapped out until a call to xTaskResumeAll () has been + * made. + * + * API functions that have the potential to cause a context switch (for example, + * xTaskDelayUntil(), xQueueSend(), etc.) must not be called while the scheduler + * is suspended. + * + * Example usage: + * 
+ * void vTask1( void * pvParameters )
+ * {
+ *   for( ;; )
+ *   {
+ *       // Task code goes here.
+ *
+ *       // ...
+ *
+ *       // At some point the task wants to perform a long operation during
+ *       // which it does not want to get swapped out.  It cannot use
+ *       // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+ *       // operation may cause interrupts to be missed - including the
+ *       // ticks.
+ *
+ *       // Prevent the real time kernel swapping out the task.
+ *       vTaskSuspendAll ();
+ *
+ *       // Perform the operation here.  There is no need to use critical
+ *       // sections as we have all the microcontroller processing time.
+ *       // During this time interrupts will still operate and the kernel
+ *       // tick count will be maintained.
+ *
+ *       // ...
+ *
+ *       // The operation is complete.  Restart the kernel.
+ *       xTaskResumeAll ();
+ *   }
+ * }
+ *
+ * \defgroup vTaskSuspendAll vTaskSuspendAll + * \ingroup SchedulerControl + */ +void vTaskSuspendAll( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
+ * BaseType_t xTaskResumeAll( void );
+ *
+ * + * Resumes scheduler activity after it was suspended by a call to + * vTaskSuspendAll(). + * + * xTaskResumeAll() only resumes the scheduler. It does not unsuspend tasks + * that were previously suspended by a call to vTaskSuspend(). + * + * @return If resuming the scheduler caused a context switch then pdTRUE is + * returned, otherwise pdFALSE is returned. + * + * Example usage: + * 
+ * void vTask1( void * pvParameters )
+ * {
+ *   for( ;; )
+ *   {
+ *       // Task code goes here.
+ *
+ *       // ...
+ *
+ *       // At some point the task wants to perform a long operation during
+ *       // which it does not want to get swapped out.  It cannot use
+ *       // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+ *       // operation may cause interrupts to be missed - including the
+ *       // ticks.
+ *
+ *       // Prevent the real time kernel swapping out the task.
+ *       vTaskSuspendAll ();
+ *
+ *       // Perform the operation here.  There is no need to use critical
+ *       // sections as we have all the microcontroller processing time.
+ *       // During this time interrupts will still operate and the real
+ *       // time kernel tick count will be maintained.
+ *
+ *       // ...
+ *
+ *       // The operation is complete.  Restart the kernel.  We want to force
+ *       // a context switch - but there is no point if resuming the scheduler
+ *       // caused a context switch already.
+ *       if( !xTaskResumeAll () )
+ *       {
+ *            taskYIELD ();
+ *       }
+ *   }
+ * }
+ *
+ * \defgroup xTaskResumeAll xTaskResumeAll + * \ingroup SchedulerControl + */ +BaseType_t xTaskResumeAll( void ) PRIVILEGED_FUNCTION; + +/*----------------------------------------------------------- +* TASK UTILITIES +*----------------------------------------------------------*/ + +/** + * task. h + * 
TickType_t xTaskGetTickCount( void );
+ * + * @return The count of ticks since vTaskStartScheduler was called. + * + * \defgroup xTaskGetTickCount xTaskGetTickCount + * \ingroup TaskUtils + */ +TickType_t xTaskGetTickCount( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
TickType_t xTaskGetTickCountFromISR( void );
+ * + * @return The count of ticks since vTaskStartScheduler was called. + * + * This is a version of xTaskGetTickCount() that is safe to be called from an + * ISR - provided that TickType_t is the natural word size of the + * microcontroller being used or interrupt nesting is either not supported or + * not being used. + * + * \defgroup xTaskGetTickCountFromISR xTaskGetTickCountFromISR + * \ingroup TaskUtils + */ +TickType_t xTaskGetTickCountFromISR( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
uint16_t uxTaskGetNumberOfTasks( void );
+ * + * @return The number of tasks that the real time kernel is currently managing. + * This includes all ready, blocked and suspended tasks. A task that + * has been deleted but not yet freed by the idle task will also be + * included in the count. + * + * \defgroup uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks + * \ingroup TaskUtils + */ +UBaseType_t uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
char *pcTaskGetName( TaskHandle_t xTaskToQuery );
+ * + * @return The text (human readable) name of the task referenced by the handle + * xTaskToQuery. A task can query its own name by either passing in its own + * handle, or by setting xTaskToQuery to NULL. + * + * \defgroup pcTaskGetName pcTaskGetName + * \ingroup TaskUtils + */ +char * pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + +/** + * task. h + * 
TaskHandle_t xTaskGetHandle( const char *pcNameToQuery );
+ * + * NOTE: This function takes a relatively long time to complete and should be + * used sparingly. + * + * @return The handle of the task that has the human readable name pcNameToQuery. + * NULL is returned if no matching name is found. INCLUDE_xTaskGetHandle + * must be set to 1 in FreeRTOSConfig.h for pcTaskGetHandle() to be available. + * + * \defgroup pcTaskGetHandle pcTaskGetHandle + * \ingroup TaskUtils + */ +TaskHandle_t xTaskGetHandle( const char * pcNameToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + +/** + * task.h + * 
UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask );
+ * + * INCLUDE_uxTaskGetStackHighWaterMark must be set to 1 in FreeRTOSConfig.h for + * this function to be available. + * + * Returns the high water mark of the stack associated with xTask. That is, + * the minimum free stack space there has been (in words, so on a 32 bit machine + * a value of 1 means 4 bytes) since the task started. The smaller the returned + * number the closer the task has come to overflowing its stack. + * + * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the + * same except for their return type. Using configSTACK_DEPTH_TYPE allows the + * user to determine the return type. It gets around the problem of the value + * overflowing on 8-bit types without breaking backward compatibility for + * applications that expect an 8-bit return type. + * + * @param xTask Handle of the task associated with the stack to be checked. + * Set xTask to NULL to check the stack of the calling task. + * + * @return The smallest amount of free stack space there has been (in words, so + * actual spaces on the stack rather than bytes) since the task referenced by + * xTask was created. + */ +UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/** + * task.h + * 
configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask );
+ * + * INCLUDE_uxTaskGetStackHighWaterMark2 must be set to 1 in FreeRTOSConfig.h for + * this function to be available. + * + * Returns the high water mark of the stack associated with xTask. That is, + * the minimum free stack space there has been (in words, so on a 32 bit machine + * a value of 1 means 4 bytes) since the task started. The smaller the returned + * number the closer the task has come to overflowing its stack. + * + * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the + * same except for their return type. Using configSTACK_DEPTH_TYPE allows the + * user to determine the return type. It gets around the problem of the value + * overflowing on 8-bit types without breaking backward compatibility for + * applications that expect an 8-bit return type. + * + * @param xTask Handle of the task associated with the stack to be checked. + * Set xTask to NULL to check the stack of the calling task. + * + * @return The smallest amount of free stack space there has been (in words, so + * actual spaces on the stack rather than bytes) since the task referenced by + * xTask was created. + */ +configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/* When using trace macros it is sometimes necessary to include task.h before + * FreeRTOS.h. When this is done TaskHookFunction_t will not yet have been defined, + * so the following two prototypes will cause a compilation error. This can be + * fixed by simply guarding against the inclusion of these two prototypes unless + * they are explicitly required by the configUSE_APPLICATION_TASK_TAG configuration + * constant. */ +#ifdef configUSE_APPLICATION_TASK_TAG + #if configUSE_APPLICATION_TASK_TAG == 1 + +/** + * task.h + * 
+ * void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction );
+ *
+ * + * Sets pxHookFunction to be the task hook function used by the task xTask. + * Passing xTask as NULL has the effect of setting the calling tasks hook + * function. + */ + void vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) PRIVILEGED_FUNCTION; + +/** + * task.h + * 
+ * void xTaskGetApplicationTaskTag( TaskHandle_t xTask );
+ *
+ * + * Returns the pxHookFunction value assigned to the task xTask. Do not + * call from an interrupt service routine - call + * xTaskGetApplicationTaskTagFromISR() instead. + */ + TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/** + * task.h + * 
+ * void xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask );
+ *
+ * + * Returns the pxHookFunction value assigned to the task xTask. Can + * be called from an interrupt service routine. + */ + TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + #endif /* configUSE_APPLICATION_TASK_TAG ==1 */ +#endif /* ifdef configUSE_APPLICATION_TASK_TAG */ + +#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 ) + +/* Each task contains an array of pointers that is dimensioned by the + * configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h. The + * kernel does not use the pointers itself, so the application writer can use + * the pointers for any purpose they wish. The following two functions are + * used to set and query a pointer respectively. */ + void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) PRIVILEGED_FUNCTION; + void * pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) PRIVILEGED_FUNCTION; + +#endif + +#if ( configCHECK_FOR_STACK_OVERFLOW > 0 ) + + /** + * task.h + * 
void vApplicationStackOverflowHook( TaskHandle_t xTask char *pcTaskName);
+ * + * The application stack overflow hook is called when a stack overflow is detected for a task. + * + * Details on stack overflow detection can be found here: https://www.FreeRTOS.org/Stacks-and-stack-overflow-checking.html + * + * @param xTask the task that just exceeded its stack boundaries. + * @param pcTaskName A character string containing the name of the offending task. + */ + void vApplicationStackOverflowHook( TaskHandle_t xTask, + const char * pcTaskName ); + +#endif + +#if ( configUSE_TICK_HOOK > 0 ) + /** + * task.h + * 
void vApplicationTickHook( void );
+ * + * This hook function is called in the system tick handler after any OS work is completed. + */ + void vApplicationTickHook( void ); /*lint !e526 Symbol not defined as it is an application callback. */ + +#endif + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + /** + * task.h + * 
void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, StackType_t ** ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize )
+ * + * This function is used to provide a statically allocated block of memory to FreeRTOS to hold the Idle Task TCB. This function is required when + * configSUPPORT_STATIC_ALLOCATION is set. For more information see this URI: https://www.FreeRTOS.org/a00110.html#configSUPPORT_STATIC_ALLOCATION + * + * @param ppxIdleTaskTCBBuffer A handle to a statically allocated TCB buffer + * @param ppxIdleTaskStackBuffer A handle to a statically allocated Stack buffer for thie idle task + * @param pulIdleTaskStackSize A pointer to the number of elements that will fit in the allocated stack buffer + */ + void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, + StackType_t ** ppxIdleTaskStackBuffer, + uint32_t * pulIdleTaskStackSize ); /*lint !e526 Symbol not defined as it is an application callback. */ +#endif + +/** + * task.h + * 
+ * BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );
+ *
+ * + * Calls the hook function associated with xTask. Passing xTask as NULL has + * the effect of calling the Running tasks (the calling task) hook function. + * + * pvParameter is passed to the hook function for the task to interpret as it + * wants. The return value is the value returned by the task hook function + * registered by the user. + */ +BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, + void * pvParameter ) PRIVILEGED_FUNCTION; + +/** + * xTaskGetIdleTaskHandle() is only available if + * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h. + * + * Simply returns the handle of the idle task. It is not valid to call + * xTaskGetIdleTaskHandle() before the scheduler has been started. + */ +TaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION; + +/** + * configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for + * uxTaskGetSystemState() to be available. + * + * uxTaskGetSystemState() populates an TaskStatus_t structure for each task in + * the system. TaskStatus_t structures contain, among other things, members + * for the task handle, task name, task priority, task state, and total amount + * of run time consumed by the task. See the TaskStatus_t structure + * definition in this file for the full member list. + * + * NOTE: This function is intended for debugging use only as its use results in + * the scheduler remaining suspended for an extended period. + * + * @param pxTaskStatusArray A pointer to an array of TaskStatus_t structures. + * The array must contain at least one TaskStatus_t structure for each task + * that is under the control of the RTOS. The number of tasks under the control + * of the RTOS can be determined using the uxTaskGetNumberOfTasks() API function. + * + * @param uxArraySize The size of the array pointed to by the pxTaskStatusArray + * parameter. The size is specified as the number of indexes in the array, or + * the number of TaskStatus_t structures contained in the array, not by the + * number of bytes in the array. + * + * @param pulTotalRunTime If configGENERATE_RUN_TIME_STATS is set to 1 in + * FreeRTOSConfig.h then *pulTotalRunTime is set by uxTaskGetSystemState() to the + * total run time (as defined by the run time stats clock, see + * https://www.FreeRTOS.org/rtos-run-time-stats.html) since the target booted. + * pulTotalRunTime can be set to NULL to omit the total run time information. + * + * @return The number of TaskStatus_t structures that were populated by + * uxTaskGetSystemState(). This should equal the number returned by the + * uxTaskGetNumberOfTasks() API function, but will be zero if the value passed + * in the uxArraySize parameter was too small. + * + * Example usage: + * 
+ *  // This example demonstrates how a human readable table of run time stats
+ *  // information is generated from raw data provided by uxTaskGetSystemState().
+ *  // The human readable table is written to pcWriteBuffer
+ *  void vTaskGetRunTimeStats( char *pcWriteBuffer )
+ *  {
+ *  TaskStatus_t *pxTaskStatusArray;
+ *  volatile UBaseType_t uxArraySize, x;
+ *  uint32_t ulTotalRunTime, ulStatsAsPercentage;
+ *
+ *      // Make sure the write buffer does not contain a string.
+ * pcWriteBuffer = 0x00;
+ *
+ *      // Take a snapshot of the number of tasks in case it changes while this
+ *      // function is executing.
+ *      uxArraySize = uxTaskGetNumberOfTasks();
+ *
+ *      // Allocate a TaskStatus_t structure for each task.  An array could be
+ *      // allocated statically at compile time.
+ *      pxTaskStatusArray = pvPortMalloc( uxArraySize * sizeof( TaskStatus_t ) );
+ *
+ *      if( pxTaskStatusArray != NULL )
+ *      {
+ *          // Generate raw status information about each task.
+ *          uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalRunTime );
+ *
+ *          // For percentage calculations.
+ *          ulTotalRunTime /= 100UL;
+ *
+ *          // Avoid divide by zero errors.
+ *          if( ulTotalRunTime > 0 )
+ *          {
+ *              // For each populated position in the pxTaskStatusArray array,
+ *              // format the raw data as human readable ASCII data
+ *              for( x = 0; x < uxArraySize; x++ )
+ *              {
+ *                  // What percentage of the total run time has the task used?
+ *                  // This will always be rounded down to the nearest integer.
+ *                  // ulTotalRunTimeDiv100 has already been divided by 100.
+ *                  ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalRunTime;
+ *
+ *                  if( ulStatsAsPercentage > 0UL )
+ *                  {
+ *                      sprintf( pcWriteBuffer, "%s\t\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
+ *                  }
+ *                  else
+ *                  {
+ *                      // If the percentage is zero here then the task has
+ *                      // consumed less than 1% of the total run time.
+ *                      sprintf( pcWriteBuffer, "%s\t\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter );
+ *                  }
+ *
+ *                  pcWriteBuffer += strlen( ( char * ) pcWriteBuffer );
+ *              }
+ *          }
+ *
+ *          // The array is no longer needed, free the memory it consumes.
+ *          vPortFree( pxTaskStatusArray );
+ *      }
+ *  }
+ *
+ */ +UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, + const UBaseType_t uxArraySize, + uint32_t * const pulTotalRunTime ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
void vTaskList( char *pcWriteBuffer );
+ * + * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must + * both be defined as 1 for this function to be available. See the + * configuration section of the FreeRTOS.org website for more information. + * + * NOTE 1: This function will disable interrupts for its duration. It is + * not intended for normal application runtime use but as a debug aid. + * + * Lists all the current tasks, along with their current state and stack + * usage high water mark. + * + * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or + * suspended ('S'). + * + * PLEASE NOTE: + * + * This function is provided for convenience only, and is used by many of the + * demo applications. Do not consider it to be part of the scheduler. + * + * vTaskList() calls uxTaskGetSystemState(), then formats part of the + * uxTaskGetSystemState() output into a human readable table that displays task + * names, states and stack usage. + * + * vTaskList() has a dependency on the sprintf() C library function that might + * bloat the code size, use a lot of stack, and provide different results on + * different platforms. An alternative, tiny, third party, and limited + * functionality implementation of sprintf() is provided in many of the + * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note + * printf-stdarg.c does not provide a full snprintf() implementation!). + * + * It is recommended that production systems call uxTaskGetSystemState() + * directly to get access to raw stats data, rather than indirectly through a + * call to vTaskList(). + * + * @param pcWriteBuffer A buffer into which the above mentioned details + * will be written, in ASCII form. This buffer is assumed to be large + * enough to contain the generated report. Approximately 40 bytes per + * task should be sufficient. + * + * \defgroup vTaskList vTaskList + * \ingroup TaskUtils + */ +void vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + +/** + * task. h + * 
void vTaskGetRunTimeStats( char *pcWriteBuffer );
+ * + * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS + * must both be defined as 1 for this function to be available. The application + * must also then provide definitions for + * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE() + * to configure a peripheral timer/counter and return the timers current count + * value respectively. The counter should be at least 10 times the frequency of + * the tick count. + * + * NOTE 1: This function will disable interrupts for its duration. It is + * not intended for normal application runtime use but as a debug aid. + * + * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total + * accumulated execution time being stored for each task. The resolution + * of the accumulated time value depends on the frequency of the timer + * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro. + * Calling vTaskGetRunTimeStats() writes the total execution time of each + * task into a buffer, both as an absolute count value and as a percentage + * of the total system execution time. + * + * NOTE 2: + * + * This function is provided for convenience only, and is used by many of the + * demo applications. Do not consider it to be part of the scheduler. + * + * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part of the + * uxTaskGetSystemState() output into a human readable table that displays the + * amount of time each task has spent in the Running state in both absolute and + * percentage terms. + * + * vTaskGetRunTimeStats() has a dependency on the sprintf() C library function + * that might bloat the code size, use a lot of stack, and provide different + * results on different platforms. An alternative, tiny, third party, and + * limited functionality implementation of sprintf() is provided in many of the + * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note + * printf-stdarg.c does not provide a full snprintf() implementation!). + * + * It is recommended that production systems call uxTaskGetSystemState() directly + * to get access to raw stats data, rather than indirectly through a call to + * vTaskGetRunTimeStats(). + * + * @param pcWriteBuffer A buffer into which the execution times will be + * written, in ASCII form. This buffer is assumed to be large enough to + * contain the generated report. Approximately 40 bytes per task should + * be sufficient. + * + * \defgroup vTaskGetRunTimeStats vTaskGetRunTimeStats + * \ingroup TaskUtils + */ +void vTaskGetRunTimeStats( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + +/** + * task. h + * 
uint32_t ulTaskGetIdleRunTimeCounter( void );
+ * + * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS + * must both be defined as 1 for this function to be available. The application + * must also then provide definitions for + * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE() + * to configure a peripheral timer/counter and return the timers current count + * value respectively. The counter should be at least 10 times the frequency of + * the tick count. + * + * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total + * accumulated execution time being stored for each task. The resolution + * of the accumulated time value depends on the frequency of the timer + * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro. + * While uxTaskGetSystemState() and vTaskGetRunTimeStats() writes the total + * execution time of each task into a buffer, ulTaskGetIdleRunTimeCounter() + * returns the total execution time of just the idle task. + * + * @return The total run time of the idle task. This is the amount of time the + * idle task has actually been executing. The unit of time is dependent on the + * frequency configured using the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and + * portGET_RUN_TIME_COUNTER_VALUE() macros. + * + * \defgroup ulTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounter + * \ingroup TaskUtils + */ +uint32_t ulTaskGetIdleRunTimeCounter( void ) PRIVILEGED_FUNCTION; + +/** + * task. h + * 
BaseType_t xTaskNotifyIndexed( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction );
+ * 
BaseType_t xTaskNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction );
+ * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these + * functions to be available. + * + * Sends a direct to task notification to a task, with an optional value and + * action. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment one of the task's notification values. In + * that way task notifications can be used to send data to a task, or be used as + * light weight and fast binary or counting semaphores. + * + * A task can use xTaskNotifyWaitIndexed() to [optionally] block to wait for a + * notification to be pending, or ulTaskNotifyTakeIndexed() to [optionally] block + * to wait for a notification value to have a non-zero value. The task does + * not consume any CPU time while it is in the Blocked state. + * + * A notification sent to a task will remain pending until it is cleared by the + * task calling xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() (or their + * un-indexed equivalents). If the task was already in the Blocked state to + * wait for a notification when the notification arrives then the task will + * automatically be removed from the Blocked state (unblocked) and the + * notification cleared. + * + * **NOTE** Each notification within the array operates independently - a task + * can only block on one notification within the array at a time and will not be + * unblocked by a notification sent to any other array index. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. xTaskNotify() is the original API function, and remains backward + * compatible by always operating on the notification value at index 0 in the + * array. Calling xTaskNotify() is equivalent to calling xTaskNotifyIndexed() + * with the uxIndexToNotify parameter set to 0. + * + * @param xTaskToNotify The handle of the task being notified. The handle to a + * task can be returned from the xTaskCreate() API function used to create the + * task, and the handle of the currently running task can be obtained by calling + * xTaskGetCurrentTaskHandle(). + * + * @param uxIndexToNotify The index within the target task's array of + * notification values to which the notification is to be sent. uxIndexToNotify + * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES. xTaskNotify() does + * not have this parameter and always sends notifications to index 0. + * + * @param ulValue Data that can be sent with the notification. How the data is + * used depends on the value of the eAction parameter. + * + * @param eAction Specifies how the notification updates the task's notification + * value, if at all. Valid values for eAction are as follows: + * + * eSetBits - + * The target notification value is bitwise ORed with ulValue. + * xTaskNofifyIndexed() always returns pdPASS in this case. + * + * eIncrement - + * The target notification value is incremented. ulValue is not used and + * xTaskNotifyIndexed() always returns pdPASS in this case. + * + * eSetValueWithOverwrite - + * The target notification value is set to the value of ulValue, even if the + * task being notified had not yet processed the previous notification at the + * same array index (the task already had a notification pending at that index). + * xTaskNotifyIndexed() always returns pdPASS in this case. + * + * eSetValueWithoutOverwrite - + * If the task being notified did not already have a notification pending at the + * same array index then the target notification value is set to ulValue and + * xTaskNotifyIndexed() will return pdPASS. If the task being notified already + * had a notification pending at the same array index then no action is + * performed and pdFAIL is returned. + * + * eNoAction - + * The task receives a notification at the specified array index without the + * notification value at that index being updated. ulValue is not used and + * xTaskNotifyIndexed() always returns pdPASS in this case. + * + * pulPreviousNotificationValue - + * Can be used to pass out the subject task's notification value before any + * bits are modified by the notify function. + * + * @return Dependent on the value of eAction. See the description of the + * eAction parameter. + * + * \defgroup xTaskNotifyIndexed xTaskNotifyIndexed + * \ingroup TaskNotifications + */ +BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + uint32_t ulValue, + eNotifyAction eAction, + uint32_t * pulPreviousNotificationValue ) PRIVILEGED_FUNCTION; +#define xTaskNotify( xTaskToNotify, ulValue, eAction ) \ + xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), NULL ) +#define xTaskNotifyIndexed( xTaskToNotify, uxIndexToNotify, ulValue, eAction ) \ + xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), NULL ) + +/** + * task. h + * 
BaseType_t xTaskNotifyAndQueryIndexed( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotifyValue );
+ * 
BaseType_t xTaskNotifyAndQuery( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotifyValue );
+ * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * xTaskNotifyAndQueryIndexed() performs the same operation as + * xTaskNotifyIndexed() with the addition that it also returns the subject + * task's prior notification value (the notification value at the time the + * function is called rather than when the function returns) in the additional + * pulPreviousNotifyValue parameter. + * + * xTaskNotifyAndQuery() performs the same operation as xTaskNotify() with the + * addition that it also returns the subject task's prior notification value + * (the notification value as it was at the time the function is called, rather + * than when the function returns) in the additional pulPreviousNotifyValue + * parameter. + * + * \defgroup xTaskNotifyAndQueryIndexed xTaskNotifyAndQueryIndexed + * \ingroup TaskNotifications + */ +#define xTaskNotifyAndQuery( xTaskToNotify, ulValue, eAction, pulPreviousNotifyValue ) \ + xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) ) +#define xTaskNotifyAndQueryIndexed( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotifyValue ) \ + xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) ) + +/** + * task. h + * 
BaseType_t xTaskNotifyIndexedFromISR( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken );
+ * 
BaseType_t xTaskNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken );
+ * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these + * functions to be available. + * + * A version of xTaskNotifyIndexed() that can be used from an interrupt service + * routine (ISR). + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment one of the task's notification values. In + * that way task notifications can be used to send data to a task, or be used as + * light weight and fast binary or counting semaphores. + * + * A task can use xTaskNotifyWaitIndexed() to [optionally] block to wait for a + * notification to be pending, or ulTaskNotifyTakeIndexed() to [optionally] block + * to wait for a notification value to have a non-zero value. The task does + * not consume any CPU time while it is in the Blocked state. + * + * A notification sent to a task will remain pending until it is cleared by the + * task calling xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() (or their + * un-indexed equivalents). If the task was already in the Blocked state to + * wait for a notification when the notification arrives then the task will + * automatically be removed from the Blocked state (unblocked) and the + * notification cleared. + * + * **NOTE** Each notification within the array operates independently - a task + * can only block on one notification within the array at a time and will not be + * unblocked by a notification sent to any other array index. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. xTaskNotifyFromISR() is the original API function, and remains + * backward compatible by always operating on the notification value at index 0 + * within the array. Calling xTaskNotifyFromISR() is equivalent to calling + * xTaskNotifyIndexedFromISR() with the uxIndexToNotify parameter set to 0. + * + * @param uxIndexToNotify The index within the target task's array of + * notification values to which the notification is to be sent. uxIndexToNotify + * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES. xTaskNotifyFromISR() + * does not have this parameter and always sends notifications to index 0. + * + * @param xTaskToNotify The handle of the task being notified. The handle to a + * task can be returned from the xTaskCreate() API function used to create the + * task, and the handle of the currently running task can be obtained by calling + * xTaskGetCurrentTaskHandle(). + * + * @param ulValue Data that can be sent with the notification. How the data is + * used depends on the value of the eAction parameter. + * + * @param eAction Specifies how the notification updates the task's notification + * value, if at all. Valid values for eAction are as follows: + * + * eSetBits - + * The task's notification value is bitwise ORed with ulValue. xTaskNofify() + * always returns pdPASS in this case. + * + * eIncrement - + * The task's notification value is incremented. ulValue is not used and + * xTaskNotify() always returns pdPASS in this case. + * + * eSetValueWithOverwrite - + * The task's notification value is set to the value of ulValue, even if the + * task being notified had not yet processed the previous notification (the + * task already had a notification pending). xTaskNotify() always returns + * pdPASS in this case. + * + * eSetValueWithoutOverwrite - + * If the task being notified did not already have a notification pending then + * the task's notification value is set to ulValue and xTaskNotify() will + * return pdPASS. If the task being notified already had a notification + * pending then no action is performed and pdFAIL is returned. + * + * eNoAction - + * The task receives a notification without its notification value being + * updated. ulValue is not used and xTaskNotify() always returns pdPASS in + * this case. + * + * @param pxHigherPriorityTaskWoken xTaskNotifyFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the + * task to which the notification was sent to leave the Blocked state, and the + * unblocked task has a priority higher than the currently running task. If + * xTaskNotifyFromISR() sets this value to pdTRUE then a context switch should + * be requested before the interrupt is exited. How a context switch is + * requested from an ISR is dependent on the port - see the documentation page + * for the port in use. + * + * @return Dependent on the value of eAction. See the description of the + * eAction parameter. + * + * \defgroup xTaskNotifyIndexedFromISR xTaskNotifyIndexedFromISR + * \ingroup TaskNotifications + */ +BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + uint32_t ulValue, + eNotifyAction eAction, + uint32_t * pulPreviousNotificationValue, + BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; +#define xTaskNotifyFromISR( xTaskToNotify, ulValue, eAction, pxHigherPriorityTaskWoken ) \ + xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) ) +#define xTaskNotifyIndexedFromISR( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pxHigherPriorityTaskWoken ) \ + xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) ) + +/** + * task. h + * 
BaseType_t xTaskNotifyAndQueryIndexedFromISR( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken );
+ * 
BaseType_t xTaskNotifyAndQueryFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken );
+ * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * xTaskNotifyAndQueryIndexedFromISR() performs the same operation as + * xTaskNotifyIndexedFromISR() with the addition that it also returns the + * subject task's prior notification value (the notification value at the time + * the function is called rather than at the time the function returns) in the + * additional pulPreviousNotifyValue parameter. + * + * xTaskNotifyAndQueryFromISR() performs the same operation as + * xTaskNotifyFromISR() with the addition that it also returns the subject + * task's prior notification value (the notification value at the time the + * function is called rather than at the time the function returns) in the + * additional pulPreviousNotifyValue parameter. + * + * \defgroup xTaskNotifyAndQueryIndexedFromISR xTaskNotifyAndQueryIndexedFromISR + * \ingroup TaskNotifications + */ +#define xTaskNotifyAndQueryIndexedFromISR( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) \ + xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) ) +#define xTaskNotifyAndQueryFromISR( xTaskToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) \ + xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) ) + +/** + * task. h + * 
+ * BaseType_t xTaskNotifyWaitIndexed( UBaseType_t uxIndexToWaitOn, uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );
+ *
+ * BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );
+ *
+ * + * Waits for a direct to task notification to be pending at a given index within + * an array of direct to task notifications. + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this + * function to be available. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment one of the task's notification values. In + * that way task notifications can be used to send data to a task, or be used as + * light weight and fast binary or counting semaphores. + * + * A notification sent to a task will remain pending until it is cleared by the + * task calling xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() (or their + * un-indexed equivalents). If the task was already in the Blocked state to + * wait for a notification when the notification arrives then the task will + * automatically be removed from the Blocked state (unblocked) and the + * notification cleared. + * + * A task can use xTaskNotifyWaitIndexed() to [optionally] block to wait for a + * notification to be pending, or ulTaskNotifyTakeIndexed() to [optionally] block + * to wait for a notification value to have a non-zero value. The task does + * not consume any CPU time while it is in the Blocked state. + * + * **NOTE** Each notification within the array operates independently - a task + * can only block on one notification within the array at a time and will not be + * unblocked by a notification sent to any other array index. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. xTaskNotifyWait() is the original API function, and remains backward + * compatible by always operating on the notification value at index 0 in the + * array. Calling xTaskNotifyWait() is equivalent to calling + * xTaskNotifyWaitIndexed() with the uxIndexToWaitOn parameter set to 0. + * + * @param uxIndexToWaitOn The index within the calling task's array of + * notification values on which the calling task will wait for a notification to + * be received. uxIndexToWaitOn must be less than + * configTASK_NOTIFICATION_ARRAY_ENTRIES. xTaskNotifyWait() does + * not have this parameter and always waits for notifications on index 0. + * + * @param ulBitsToClearOnEntry Bits that are set in ulBitsToClearOnEntry value + * will be cleared in the calling task's notification value before the task + * checks to see if any notifications are pending, and optionally blocks if no + * notifications are pending. Setting ulBitsToClearOnEntry to ULONG_MAX (if + * limits.h is included) or 0xffffffffUL (if limits.h is not included) will have + * the effect of resetting the task's notification value to 0. Setting + * ulBitsToClearOnEntry to 0 will leave the task's notification value unchanged. + * + * @param ulBitsToClearOnExit If a notification is pending or received before + * the calling task exits the xTaskNotifyWait() function then the task's + * notification value (see the xTaskNotify() API function) is passed out using + * the pulNotificationValue parameter. Then any bits that are set in + * ulBitsToClearOnExit will be cleared in the task's notification value (note + * *pulNotificationValue is set before any bits are cleared). Setting + * ulBitsToClearOnExit to ULONG_MAX (if limits.h is included) or 0xffffffffUL + * (if limits.h is not included) will have the effect of resetting the task's + * notification value to 0 before the function exits. Setting + * ulBitsToClearOnExit to 0 will leave the task's notification value unchanged + * when the function exits (in which case the value passed out in + * pulNotificationValue will match the task's notification value). + * + * @param pulNotificationValue Used to pass the task's notification value out + * of the function. Note the value passed out will not be effected by the + * clearing of any bits caused by ulBitsToClearOnExit being non-zero. + * + * @param xTicksToWait The maximum amount of time that the task should wait in + * the Blocked state for a notification to be received, should a notification + * not already be pending when xTaskNotifyWait() was called. The task + * will not consume any processing time while it is in the Blocked state. This + * is specified in kernel ticks, the macro pdMS_TO_TICSK( value_in_ms ) can be + * used to convert a time specified in milliseconds to a time specified in + * ticks. + * + * @return If a notification was received (including notifications that were + * already pending when xTaskNotifyWait was called) then pdPASS is + * returned. Otherwise pdFAIL is returned. + * + * \defgroup xTaskNotifyWaitIndexed xTaskNotifyWaitIndexed + * \ingroup TaskNotifications + */ +BaseType_t xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn, + uint32_t ulBitsToClearOnEntry, + uint32_t ulBitsToClearOnExit, + uint32_t * pulNotificationValue, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +#define xTaskNotifyWait( ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait ) \ + xTaskGenericNotifyWait( tskDEFAULT_INDEX_TO_NOTIFY, ( ulBitsToClearOnEntry ), ( ulBitsToClearOnExit ), ( pulNotificationValue ), ( xTicksToWait ) ) +#define xTaskNotifyWaitIndexed( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait ) \ + xTaskGenericNotifyWait( ( uxIndexToWaitOn ), ( ulBitsToClearOnEntry ), ( ulBitsToClearOnExit ), ( pulNotificationValue ), ( xTicksToWait ) ) + +/** + * task. h + * 
BaseType_t xTaskNotifyGiveIndexed( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify );
+ * 
BaseType_t xTaskNotifyGive( TaskHandle_t xTaskToNotify );
+ * + * Sends a direct to task notification to a particular index in the target + * task's notification array in a manner similar to giving a counting semaphore. + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for more details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these + * macros to be available. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment one of the task's notification values. In + * that way task notifications can be used to send data to a task, or be used as + * light weight and fast binary or counting semaphores. + * + * xTaskNotifyGiveIndexed() is a helper macro intended for use when task + * notifications are used as light weight and faster binary or counting + * semaphore equivalents. Actual FreeRTOS semaphores are given using the + * xSemaphoreGive() API function, the equivalent action that instead uses a task + * notification is xTaskNotifyGiveIndexed(). + * + * When task notifications are being used as a binary or counting semaphore + * equivalent then the task being notified should wait for the notification + * using the ulTaskNotificationTakeIndexed() API function rather than the + * xTaskNotifyWaitIndexed() API function. + * + * **NOTE** Each notification within the array operates independently - a task + * can only block on one notification within the array at a time and will not be + * unblocked by a notification sent to any other array index. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. xTaskNotifyGive() is the original API function, and remains backward + * compatible by always operating on the notification value at index 0 in the + * array. Calling xTaskNotifyGive() is equivalent to calling + * xTaskNotifyGiveIndexed() with the uxIndexToNotify parameter set to 0. + * + * @param xTaskToNotify The handle of the task being notified. The handle to a + * task can be returned from the xTaskCreate() API function used to create the + * task, and the handle of the currently running task can be obtained by calling + * xTaskGetCurrentTaskHandle(). + * + * @param uxIndexToNotify The index within the target task's array of + * notification values to which the notification is to be sent. uxIndexToNotify + * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES. xTaskNotifyGive() + * does not have this parameter and always sends notifications to index 0. + * + * @return xTaskNotifyGive() is a macro that calls xTaskNotify() with the + * eAction parameter set to eIncrement - so pdPASS is always returned. + * + * \defgroup xTaskNotifyGiveIndexed xTaskNotifyGiveIndexed + * \ingroup TaskNotifications + */ +#define xTaskNotifyGive( xTaskToNotify ) \ + xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( 0 ), eIncrement, NULL ) +#define xTaskNotifyGiveIndexed( xTaskToNotify, uxIndexToNotify ) \ + xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( 0 ), eIncrement, NULL ) + +/** + * task. h + * 
void vTaskNotifyGiveIndexedFromISR( TaskHandle_t xTaskHandle, UBaseType_t uxIndexToNotify, BaseType_t *pxHigherPriorityTaskWoken );
+ * 
void vTaskNotifyGiveFromISR( TaskHandle_t xTaskHandle, BaseType_t *pxHigherPriorityTaskWoken );
+ * + * A version of xTaskNotifyGiveIndexed() that can be called from an interrupt + * service routine (ISR). + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for more details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro + * to be available. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment one of the task's notification values. In + * that way task notifications can be used to send data to a task, or be used as + * light weight and fast binary or counting semaphores. + * + * vTaskNotifyGiveIndexedFromISR() is intended for use when task notifications + * are used as light weight and faster binary or counting semaphore equivalents. + * Actual FreeRTOS semaphores are given from an ISR using the + * xSemaphoreGiveFromISR() API function, the equivalent action that instead uses + * a task notification is vTaskNotifyGiveIndexedFromISR(). + * + * When task notifications are being used as a binary or counting semaphore + * equivalent then the task being notified should wait for the notification + * using the ulTaskNotificationTakeIndexed() API function rather than the + * xTaskNotifyWaitIndexed() API function. + * + * **NOTE** Each notification within the array operates independently - a task + * can only block on one notification within the array at a time and will not be + * unblocked by a notification sent to any other array index. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. xTaskNotifyFromISR() is the original API function, and remains + * backward compatible by always operating on the notification value at index 0 + * within the array. Calling xTaskNotifyGiveFromISR() is equivalent to calling + * xTaskNotifyGiveIndexedFromISR() with the uxIndexToNotify parameter set to 0. + * + * @param xTaskToNotify The handle of the task being notified. The handle to a + * task can be returned from the xTaskCreate() API function used to create the + * task, and the handle of the currently running task can be obtained by calling + * xTaskGetCurrentTaskHandle(). + * + * @param uxIndexToNotify The index within the target task's array of + * notification values to which the notification is to be sent. uxIndexToNotify + * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES. + * xTaskNotifyGiveFromISR() does not have this parameter and always sends + * notifications to index 0. + * + * @param pxHigherPriorityTaskWoken vTaskNotifyGiveFromISR() will set + * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the + * task to which the notification was sent to leave the Blocked state, and the + * unblocked task has a priority higher than the currently running task. If + * vTaskNotifyGiveFromISR() sets this value to pdTRUE then a context switch + * should be requested before the interrupt is exited. How a context switch is + * requested from an ISR is dependent on the port - see the documentation page + * for the port in use. + * + * \defgroup vTaskNotifyGiveIndexedFromISR vTaskNotifyGiveIndexedFromISR + * \ingroup TaskNotifications + */ +void vTaskGenericNotifyGiveFromISR( TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; +#define vTaskNotifyGiveFromISR( xTaskToNotify, pxHigherPriorityTaskWoken ) \ + vTaskGenericNotifyGiveFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( pxHigherPriorityTaskWoken ) ); +#define vTaskNotifyGiveIndexedFromISR( xTaskToNotify, uxIndexToNotify, pxHigherPriorityTaskWoken ) \ + vTaskGenericNotifyGiveFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( pxHigherPriorityTaskWoken ) ); + +/** + * task. h + * 
+ * uint32_t ulTaskNotifyTakeIndexed( UBaseType_t uxIndexToWaitOn, BaseType_t xClearCountOnExit, TickType_t xTicksToWait );
+ *
+ * uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait );
+ *
+ * + * Waits for a direct to task notification on a particular index in the calling + * task's notification array in a manner similar to taking a counting semaphore. + * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this + * function to be available. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * Events can be sent to a task using an intermediary object. Examples of such + * objects are queues, semaphores, mutexes and event groups. Task notifications + * are a method of sending an event directly to a task without the need for such + * an intermediary object. + * + * A notification sent to a task can optionally perform an action, such as + * update, overwrite or increment one of the task's notification values. In + * that way task notifications can be used to send data to a task, or be used as + * light weight and fast binary or counting semaphores. + * + * ulTaskNotifyTakeIndexed() is intended for use when a task notification is + * used as a faster and lighter weight binary or counting semaphore alternative. + * Actual FreeRTOS semaphores are taken using the xSemaphoreTake() API function, + * the equivalent action that instead uses a task notification is + * ulTaskNotifyTakeIndexed(). + * + * When a task is using its notification value as a binary or counting semaphore + * other tasks should send notifications to it using the xTaskNotifyGiveIndexed() + * macro, or xTaskNotifyIndex() function with the eAction parameter set to + * eIncrement. + * + * ulTaskNotifyTakeIndexed() can either clear the task's notification value at + * the array index specified by the uxIndexToWaitOn parameter to zero on exit, + * in which case the notification value acts like a binary semaphore, or + * decrement the notification value on exit, in which case the notification + * value acts like a counting semaphore. + * + * A task can use ulTaskNotifyTakeIndexed() to [optionally] block to wait for + * the task's notification value to be non-zero. The task does not consume any + * CPU time while it is in the Blocked state. + * + * Where as xTaskNotifyWaitIndexed() will return when a notification is pending, + * ulTaskNotifyTakeIndexed() will return when the task's notification value is + * not zero. + * + * **NOTE** Each notification within the array operates independently - a task + * can only block on one notification within the array at a time and will not be + * unblocked by a notification sent to any other array index. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. ulTaskNotifyTake() is the original API function, and remains backward + * compatible by always operating on the notification value at index 0 in the + * array. Calling ulTaskNotifyTake() is equivalent to calling + * ulTaskNotifyTakeIndexed() with the uxIndexToWaitOn parameter set to 0. + * + * @param uxIndexToWaitOn The index within the calling task's array of + * notification values on which the calling task will wait for a notification to + * be non-zero. uxIndexToWaitOn must be less than + * configTASK_NOTIFICATION_ARRAY_ENTRIES. xTaskNotifyTake() does + * not have this parameter and always waits for notifications on index 0. + * + * @param xClearCountOnExit if xClearCountOnExit is pdFALSE then the task's + * notification value is decremented when the function exits. In this way the + * notification value acts like a counting semaphore. If xClearCountOnExit is + * not pdFALSE then the task's notification value is cleared to zero when the + * function exits. In this way the notification value acts like a binary + * semaphore. + * + * @param xTicksToWait The maximum amount of time that the task should wait in + * the Blocked state for the task's notification value to be greater than zero, + * should the count not already be greater than zero when + * ulTaskNotifyTake() was called. The task will not consume any processing + * time while it is in the Blocked state. This is specified in kernel ticks, + * the macro pdMS_TO_TICSK( value_in_ms ) can be used to convert a time + * specified in milliseconds to a time specified in ticks. + * + * @return The task's notification count before it is either cleared to zero or + * decremented (see the xClearCountOnExit parameter). + * + * \defgroup ulTaskNotifyTakeIndexed ulTaskNotifyTakeIndexed + * \ingroup TaskNotifications + */ +uint32_t ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +#define ulTaskNotifyTake( xClearCountOnExit, xTicksToWait ) \ + ulTaskGenericNotifyTake( ( tskDEFAULT_INDEX_TO_NOTIFY ), ( xClearCountOnExit ), ( xTicksToWait ) ) +#define ulTaskNotifyTakeIndexed( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait ) \ + ulTaskGenericNotifyTake( ( uxIndexToWaitOn ), ( xClearCountOnExit ), ( xTicksToWait ) ) + +/** + * task. h + * 
+ * BaseType_t xTaskNotifyStateClearIndexed( TaskHandle_t xTask, UBaseType_t uxIndexToCLear );
+ *
+ * BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );
+ *
+ * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these + * functions to be available. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * If a notification is sent to an index within the array of notifications then + * the notification at that index is said to be 'pending' until it is read or + * explicitly cleared by the receiving task. xTaskNotifyStateClearIndexed() + * is the function that clears a pending notification without reading the + * notification value. The notification value at the same array index is not + * altered. Set xTask to NULL to clear the notification state of the calling + * task. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. xTaskNotifyStateClear() is the original API function, and remains + * backward compatible by always operating on the notification value at index 0 + * within the array. Calling xTaskNotifyStateClear() is equivalent to calling + * xTaskNotifyStateClearIndexed() with the uxIndexToNotify parameter set to 0. + * + * @param xTask The handle of the RTOS task that will have a notification state + * cleared. Set xTask to NULL to clear a notification state in the calling + * task. To obtain a task's handle create the task using xTaskCreate() and + * make use of the pxCreatedTask parameter, or create the task using + * xTaskCreateStatic() and store the returned value, or use the task's name in + * a call to xTaskGetHandle(). + * + * @param uxIndexToClear The index within the target task's array of + * notification values to act upon. For example, setting uxIndexToClear to 1 + * will clear the state of the notification at index 1 within the array. + * uxIndexToClear must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES. + * ulTaskNotifyStateClear() does not have this parameter and always acts on the + * notification at index 0. + * + * @return pdTRUE if the task's notification state was set to + * eNotWaitingNotification, otherwise pdFALSE. + * + * \defgroup xTaskNotifyStateClearIndexed xTaskNotifyStateClearIndexed + * \ingroup TaskNotifications + */ +BaseType_t xTaskGenericNotifyStateClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear ) PRIVILEGED_FUNCTION; +#define xTaskNotifyStateClear( xTask ) \ + xTaskGenericNotifyStateClear( ( xTask ), ( tskDEFAULT_INDEX_TO_NOTIFY ) ) +#define xTaskNotifyStateClearIndexed( xTask, uxIndexToClear ) \ + xTaskGenericNotifyStateClear( ( xTask ), ( uxIndexToClear ) ) + +/** + * task. h + * 
+ * uint32_t ulTaskNotifyValueClearIndexed( TaskHandle_t xTask, UBaseType_t uxIndexToClear, uint32_t ulBitsToClear );
+ *
+ * uint32_t ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear );
+ *
+ * + * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details. + * + * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these + * functions to be available. + * + * Each task has a private array of "notification values" (or 'notifications'), + * each of which is a 32-bit unsigned integer (uint32_t). The constant + * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the + * array, and (for backward compatibility) defaults to 1 if left undefined. + * Prior to FreeRTOS V10.4.0 there was only one notification value per task. + * + * ulTaskNotifyValueClearIndexed() clears the bits specified by the + * ulBitsToClear bit mask in the notification value at array index uxIndexToClear + * of the task referenced by xTask. + * + * Backward compatibility information: + * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and + * all task notification API functions operated on that value. Replacing the + * single notification value with an array of notification values necessitated a + * new set of API functions that could address specific notifications within the + * array. ulTaskNotifyValueClear() is the original API function, and remains + * backward compatible by always operating on the notification value at index 0 + * within the array. Calling ulTaskNotifyValueClear() is equivalent to calling + * ulTaskNotifyValueClearIndexed() with the uxIndexToClear parameter set to 0. + * + * @param xTask The handle of the RTOS task that will have bits in one of its + * notification values cleared. Set xTask to NULL to clear bits in a + * notification value of the calling task. To obtain a task's handle create the + * task using xTaskCreate() and make use of the pxCreatedTask parameter, or + * create the task using xTaskCreateStatic() and store the returned value, or + * use the task's name in a call to xTaskGetHandle(). + * + * @param uxIndexToClear The index within the target task's array of + * notification values in which to clear the bits. uxIndexToClear + * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES. + * ulTaskNotifyValueClear() does not have this parameter and always clears bits + * in the notification value at index 0. + * + * @param ulBitsToClear Bit mask of the bits to clear in the notification value of + * xTask. Set a bit to 1 to clear the corresponding bits in the task's notification + * value. Set ulBitsToClear to 0xffffffff (UINT_MAX on 32-bit architectures) to clear + * the notification value to 0. Set ulBitsToClear to 0 to query the task's + * notification value without clearing any bits. + * + * + * @return The value of the target task's notification value before the bits + * specified by ulBitsToClear were cleared. + * \defgroup ulTaskNotifyValueClear ulTaskNotifyValueClear + * \ingroup TaskNotifications + */ +uint32_t ulTaskGenericNotifyValueClear( TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION; +#define ulTaskNotifyValueClear( xTask, ulBitsToClear ) \ + ulTaskGenericNotifyValueClear( ( xTask ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulBitsToClear ) ) +#define ulTaskNotifyValueClearIndexed( xTask, uxIndexToClear, ulBitsToClear ) \ + ulTaskGenericNotifyValueClear( ( xTask ), ( uxIndexToClear ), ( ulBitsToClear ) ) + +/** + * task.h + * 
+ * void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut );
+ *
+ * + * Capture the current time for future use with xTaskCheckForTimeOut(). + * + * @param pxTimeOut Pointer to a timeout object into which the current time + * is to be captured. The captured time includes the tick count and the number + * of times the tick count has overflowed since the system first booted. + * \defgroup vTaskSetTimeOutState vTaskSetTimeOutState + * \ingroup TaskCtrl + */ +void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION; + +/** + * task.h + * 
+ * BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait );
+ *
+ * + * Determines if pxTicksToWait ticks has passed since a time was captured + * using a call to vTaskSetTimeOutState(). The captured time includes the tick + * count and the number of times the tick count has overflowed. + * + * @param pxTimeOut The time status as captured previously using + * vTaskSetTimeOutState. If the timeout has not yet occurred, it is updated + * to reflect the current time status. + * @param pxTicksToWait The number of ticks to check for timeout i.e. if + * pxTicksToWait ticks have passed since pxTimeOut was last updated (either by + * vTaskSetTimeOutState() or xTaskCheckForTimeOut()), the timeout has occurred. + * If the timeout has not occurred, pxTIcksToWait is updated to reflect the + * number of remaining ticks. + * + * @return If timeout has occurred, pdTRUE is returned. Otherwise pdFALSE is + * returned and pxTicksToWait is updated to reflect the number of remaining + * ticks. + * + * @see https://www.FreeRTOS.org/xTaskCheckForTimeOut.html + * + * Example Usage: + * 
+ *  // Driver library function used to receive uxWantedBytes from an Rx buffer
+ *  // that is filled by a UART interrupt. If there are not enough bytes in the
+ *  // Rx buffer then the task enters the Blocked state until it is notified that
+ *  // more data has been placed into the buffer. If there is still not enough
+ *  // data then the task re-enters the Blocked state, and xTaskCheckForTimeOut()
+ *  // is used to re-calculate the Block time to ensure the total amount of time
+ *  // spent in the Blocked state does not exceed MAX_TIME_TO_WAIT. This
+ *  // continues until either the buffer contains at least uxWantedBytes bytes,
+ *  // or the total amount of time spent in the Blocked state reaches
+ *  // MAX_TIME_TO_WAIT - at which point the task reads however many bytes are
+ *  // available up to a maximum of uxWantedBytes.
+ *
+ *  size_t xUART_Receive( uint8_t *pucBuffer, size_t uxWantedBytes )
+ *  {
+ *  size_t uxReceived = 0;
+ *  TickType_t xTicksToWait = MAX_TIME_TO_WAIT;
+ *  TimeOut_t xTimeOut;
+ *
+ *      // Initialize xTimeOut.  This records the time at which this function
+ *      // was entered.
+ *      vTaskSetTimeOutState( &xTimeOut );
+ *
+ *      // Loop until the buffer contains the wanted number of bytes, or a
+ *      // timeout occurs.
+ *      while( UART_bytes_in_rx_buffer( pxUARTInstance ) < uxWantedBytes )
+ *      {
+ *          // The buffer didn't contain enough data so this task is going to
+ *          // enter the Blocked state. Adjusting xTicksToWait to account for
+ *          // any time that has been spent in the Blocked state within this
+ *          // function so far to ensure the total amount of time spent in the
+ *          // Blocked state does not exceed MAX_TIME_TO_WAIT.
+ *          if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) != pdFALSE )
+ *          {
+ *              //Timed out before the wanted number of bytes were available,
+ *              // exit the loop.
+ *              break;
+ *          }
+ *
+ *          // Wait for a maximum of xTicksToWait ticks to be notified that the
+ *          // receive interrupt has placed more data into the buffer.
+ *          ulTaskNotifyTake( pdTRUE, xTicksToWait );
+ *      }
+ *
+ *      // Attempt to read uxWantedBytes from the receive buffer into pucBuffer.
+ *      // The actual number of bytes read (which might be less than
+ *      // uxWantedBytes) is returned.
+ *      uxReceived = UART_read_from_receive_buffer( pxUARTInstance,
+ *                                                  pucBuffer,
+ *                                                  uxWantedBytes );
+ *
+ *      return uxReceived;
+ *  }
+ *
+ * \defgroup xTaskCheckForTimeOut xTaskCheckForTimeOut + * \ingroup TaskCtrl + */ +BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, + TickType_t * const pxTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * task.h + * 
+ * BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp );
+ *
+ * + * This function corrects the tick count value after the application code has held + * interrupts disabled for an extended period resulting in tick interrupts having + * been missed. + * + * This function is similar to vTaskStepTick(), however, unlike + * vTaskStepTick(), xTaskCatchUpTicks() may move the tick count forward past a + * time at which a task should be removed from the blocked state. That means + * tasks may have to be removed from the blocked state as the tick count is + * moved. + * + * @param xTicksToCatchUp The number of tick interrupts that have been missed due to + * interrupts being disabled. Its value is not computed automatically, so must be + * computed by the application writer. + * + * @return pdTRUE if moving the tick count forward resulted in a task leaving the + * blocked state and a context switch being performed. Otherwise pdFALSE. + * + * \defgroup xTaskCatchUpTicks xTaskCatchUpTicks + * \ingroup TaskCtrl + */ +BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) PRIVILEGED_FUNCTION; + + +/*----------------------------------------------------------- +* SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES +*----------------------------------------------------------*/ + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY + * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS + * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * Called from the real time kernel tick (either preemptive or cooperative), + * this increments the tick count and checks if any tasks that are blocked + * for a finite period required removing from a blocked list and placing on + * a ready list. If a non-zero value is returned then a context switch is + * required because either: + * + A task was removed from a blocked list because its timeout had expired, + * or + * + Time slicing is in use and there is a task of equal priority to the + * currently running task. + */ +BaseType_t xTaskIncrementTick( void ) PRIVILEGED_FUNCTION; + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN + * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. + * + * Removes the calling task from the ready list and places it both + * on the list of tasks waiting for a particular event, and the + * list of delayed tasks. The task will be removed from both lists + * and replaced on the ready list should either the event occur (and + * there be no higher priority tasks waiting on the same event) or + * the delay period expires. + * + * The 'unordered' version replaces the event list item value with the + * xItemValue value, and inserts the list item at the end of the list. + * + * The 'ordered' version uses the existing event list item value (which is the + * owning tasks priority) to insert the list item into the event list is task + * priority order. + * + * @param pxEventList The list containing tasks that are blocked waiting + * for the event to occur. + * + * @param xItemValue The item value to use for the event list item when the + * event list is not ordered by task priority. + * + * @param xTicksToWait The maximum amount of time that the task should wait + * for the event to occur. This is specified in kernel ticks,the constant + * portTICK_PERIOD_MS can be used to convert kernel ticks into a real time + * period. + */ +void vTaskPlaceOnEventList( List_t * const pxEventList, + const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; +void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, + const TickType_t xItemValue, + const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN + * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. + * + * This function performs nearly the same function as vTaskPlaceOnEventList(). + * The difference being that this function does not permit tasks to block + * indefinitely, whereas vTaskPlaceOnEventList() does. + * + */ +void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, + TickType_t xTicksToWait, + const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION; + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS AN + * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED. + * + * Removes a task from both the specified event list and the list of blocked + * tasks, and places it on a ready queue. + * + * xTaskRemoveFromEventList()/vTaskRemoveFromUnorderedEventList() will be called + * if either an event occurs to unblock a task, or the block timeout period + * expires. + * + * xTaskRemoveFromEventList() is used when the event list is in task priority + * order. It removes the list item from the head of the event list as that will + * have the highest priority owning task of all the tasks on the event list. + * vTaskRemoveFromUnorderedEventList() is used when the event list is not + * ordered and the event list items hold something other than the owning tasks + * priority. In this case the event list item value is updated to the value + * passed in the xItemValue parameter. + * + * @return pdTRUE if the task being removed has a higher priority than the task + * making the call, otherwise pdFALSE. + */ +BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) PRIVILEGED_FUNCTION; +void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, + const TickType_t xItemValue ) PRIVILEGED_FUNCTION; + +/* + * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE. IT IS ONLY + * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS + * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER. + * + * Sets the pointer to the current TCB to the TCB of the highest priority task + * that is ready to run. + */ +portDONT_DISCARD void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION; + +/* + * THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE. THEY ARE USED BY + * THE EVENT BITS MODULE. + */ +TickType_t uxTaskResetEventItemValue( void ) PRIVILEGED_FUNCTION; + +/* + * Return the handle of the calling task. + */ +TaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION; + +/* + * Shortcut used by the queue implementation to prevent unnecessary call to + * taskYIELD(); + */ +void vTaskMissedYield( void ) PRIVILEGED_FUNCTION; + +/* + * Returns the scheduler state as taskSCHEDULER_RUNNING, + * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED. + */ +BaseType_t xTaskGetSchedulerState( void ) PRIVILEGED_FUNCTION; + +/* + * Raises the priority of the mutex holder to that of the calling task should + * the mutex holder have a priority less than the calling task. + */ +BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION; + +/* + * Set the priority of a task back to its proper priority in the case that it + * inherited a higher priority while it was holding a semaphore. + */ +BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION; + +/* + * If a higher priority task attempting to obtain a mutex caused a lower + * priority task to inherit the higher priority task's priority - but the higher + * priority task then timed out without obtaining the mutex, then the lower + * priority task will disinherit the priority again - but only down as far as + * the highest priority task that is still waiting for the mutex (if there were + * more than one task waiting for the mutex). + */ +void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, + UBaseType_t uxHighestPriorityWaitingTask ) PRIVILEGED_FUNCTION; + +/* + * Get the uxTCBNumber assigned to the task referenced by the xTask parameter. + */ +UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION; + +/* + * Set the uxTaskNumber of the task referenced by the xTask parameter to + * uxHandle. + */ +void vTaskSetTaskNumber( TaskHandle_t xTask, + const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION; + +/* + * Only available when configUSE_TICKLESS_IDLE is set to 1. + * If tickless mode is being used, or a low power mode is implemented, then + * the tick interrupt will not execute during idle periods. When this is the + * case, the tick count value maintained by the scheduler needs to be kept up + * to date with the actual execution time by being skipped forward by a time + * equal to the idle period. + */ +void vTaskStepTick( const TickType_t xTicksToJump ) PRIVILEGED_FUNCTION; + +/* + * Only available when configUSE_TICKLESS_IDLE is set to 1. + * Provided for use within portSUPPRESS_TICKS_AND_SLEEP() to allow the port + * specific sleep function to determine if it is ok to proceed with the sleep, + * and if it is ok to proceed, if it is ok to sleep indefinitely. + * + * This function is necessary because portSUPPRESS_TICKS_AND_SLEEP() is only + * called with the scheduler suspended, not from within a critical section. It + * is therefore possible for an interrupt to request a context switch between + * portSUPPRESS_TICKS_AND_SLEEP() and the low power mode actually being + * entered. eTaskConfirmSleepModeStatus() should be called from a short + * critical section between the timer being stopped and the sleep mode being + * entered to ensure it is ok to proceed into the sleep mode. + */ +eSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION; + +/* + * For internal use only. Increment the mutex held count when a mutex is + * taken and return the handle of the task that has taken the mutex. + */ +TaskHandle_t pvTaskIncrementMutexHeldCount( void ) PRIVILEGED_FUNCTION; + +/* + * For internal use only. Same as vTaskSetTimeOutState(), but without a critical + * section. + */ +void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION; + + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ +#endif /* INC_TASK_H */ diff --git a/MODULES/FreeRTOS/inc/timers.h b/MODULES/FreeRTOS/inc/timers.h new file mode 100644 index 0000000..9a19c83 --- /dev/null +++ b/MODULES/FreeRTOS/inc/timers.h @@ -0,0 +1,1351 @@ +/* + * FreeRTOS Kernel V10.4.3 LTS Patch 2 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#ifndef TIMERS_H +#define TIMERS_H + +#ifndef INC_FREERTOS_H + #error "include FreeRTOS.h must appear in source files before include timers.h" +#endif + +/*lint -save -e537 This headers are only multiply included if the application code + * happens to also be including task.h. */ +#include "task.h" +/*lint -restore */ + +/* *INDENT-OFF* */ +#ifdef __cplusplus + extern "C" { +#endif +/* *INDENT-ON* */ + +/*----------------------------------------------------------- +* MACROS AND DEFINITIONS +*----------------------------------------------------------*/ + +/* IDs for commands that can be sent/received on the timer queue. These are to + * be used solely through the macros that make up the public software timer API, + * as defined below. The commands that are sent from interrupts must use the + * highest numbers as tmrFIRST_FROM_ISR_COMMAND is used to determine if the task + * or interrupt version of the queue send function should be used. */ +#define tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR ( ( BaseType_t ) -2 ) +#define tmrCOMMAND_EXECUTE_CALLBACK ( ( BaseType_t ) -1 ) +#define tmrCOMMAND_START_DONT_TRACE ( ( BaseType_t ) 0 ) +#define tmrCOMMAND_START ( ( BaseType_t ) 1 ) +#define tmrCOMMAND_RESET ( ( BaseType_t ) 2 ) +#define tmrCOMMAND_STOP ( ( BaseType_t ) 3 ) +#define tmrCOMMAND_CHANGE_PERIOD ( ( BaseType_t ) 4 ) +#define tmrCOMMAND_DELETE ( ( BaseType_t ) 5 ) + +#define tmrFIRST_FROM_ISR_COMMAND ( ( BaseType_t ) 6 ) +#define tmrCOMMAND_START_FROM_ISR ( ( BaseType_t ) 6 ) +#define tmrCOMMAND_RESET_FROM_ISR ( ( BaseType_t ) 7 ) +#define tmrCOMMAND_STOP_FROM_ISR ( ( BaseType_t ) 8 ) +#define tmrCOMMAND_CHANGE_PERIOD_FROM_ISR ( ( BaseType_t ) 9 ) + + +/** + * Type by which software timers are referenced. For example, a call to + * xTimerCreate() returns an TimerHandle_t variable that can then be used to + * reference the subject timer in calls to other software timer API functions + * (for example, xTimerStart(), xTimerReset(), etc.). + */ +struct tmrTimerControl; /* The old naming convention is used to prevent breaking kernel aware debuggers. */ +typedef struct tmrTimerControl * TimerHandle_t; + +/* + * Defines the prototype to which timer callback functions must conform. + */ +typedef void (* TimerCallbackFunction_t)( TimerHandle_t xTimer ); + +/* + * Defines the prototype to which functions used with the + * xTimerPendFunctionCallFromISR() function must conform. + */ +typedef void (* PendedFunction_t)( void *, + uint32_t ); + +/** + * TimerHandle_t xTimerCreate( const char * const pcTimerName, + * TickType_t xTimerPeriodInTicks, + * UBaseType_t uxAutoReload, + * void * pvTimerID, + * TimerCallbackFunction_t pxCallbackFunction ); + * + * Creates a new software timer instance, and returns a handle by which the + * created software timer can be referenced. + * + * Internally, within the FreeRTOS implementation, software timers use a block + * of memory, in which the timer data structure is stored. If a software timer + * is created using xTimerCreate() then the required memory is automatically + * dynamically allocated inside the xTimerCreate() function. (see + * https://www.FreeRTOS.org/a00111.html). If a software timer is created using + * xTimerCreateStatic() then the application writer must provide the memory that + * will get used by the software timer. xTimerCreateStatic() therefore allows a + * software timer to be created without using any dynamic memory allocation. + * + * Timers are created in the dormant state. The xTimerStart(), xTimerReset(), + * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and + * xTimerChangePeriodFromISR() API functions can all be used to transition a + * timer into the active state. + * + * @param pcTimerName A text name that is assigned to the timer. This is done + * purely to assist debugging. The kernel itself only ever references a timer + * by its handle, and never by its name. + * + * @param xTimerPeriodInTicks The timer period. The time is defined in tick + * periods so the constant portTICK_PERIOD_MS can be used to convert a time that + * has been specified in milliseconds. For example, if the timer must expire + * after 100 ticks, then xTimerPeriodInTicks should be set to 100. + * Alternatively, if the timer must expire after 500ms, then xPeriod can be set + * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or + * equal to 1000. Time timer period must be greater than 0. + * + * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will + * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter. + * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and + * enter the dormant state after it expires. + * + * @param pvTimerID An identifier that is assigned to the timer being created. + * Typically this would be used in the timer callback function to identify which + * timer expired when the same callback function is assigned to more than one + * timer. + * + * @param pxCallbackFunction The function to call when the timer expires. + * Callback functions must have the prototype defined by TimerCallbackFunction_t, + * which is "void vCallbackFunction( TimerHandle_t xTimer );". + * + * @return If the timer is successfully created then a handle to the newly + * created timer is returned. If the timer cannot be created because there is + * insufficient FreeRTOS heap remaining to allocate the timer + * structures then NULL is returned. + * + * Example usage: + * @verbatim + * #define NUM_TIMERS 5 + * + * // An array to hold handles to the created timers. + * TimerHandle_t xTimers[ NUM_TIMERS ]; + * + * // An array to hold a count of the number of times each timer expires. + * int32_t lExpireCounters[ NUM_TIMERS ] = { 0 }; + * + * // Define a callback function that will be used by multiple timer instances. + * // The callback function does nothing but count the number of times the + * // associated timer expires, and stop the timer once the timer has expired + * // 10 times. + * void vTimerCallback( TimerHandle_t pxTimer ) + * { + * int32_t lArrayIndex; + * const int32_t xMaxExpiryCountBeforeStopping = 10; + * + * // Optionally do something if the pxTimer parameter is NULL. + * configASSERT( pxTimer ); + * + * // Which timer expired? + * lArrayIndex = ( int32_t ) pvTimerGetTimerID( pxTimer ); + * + * // Increment the number of times that pxTimer has expired. + * lExpireCounters[ lArrayIndex ] += 1; + * + * // If the timer has expired 10 times then stop it from running. + * if( lExpireCounters[ lArrayIndex ] == xMaxExpiryCountBeforeStopping ) + * { + * // Do not use a block time if calling a timer API function from a + * // timer callback function, as doing so could cause a deadlock! + * xTimerStop( pxTimer, 0 ); + * } + * } + * + * void main( void ) + * { + * int32_t x; + * + * // Create then start some timers. Starting the timers before the scheduler + * // has been started means the timers will start running immediately that + * // the scheduler starts. + * for( x = 0; x < NUM_TIMERS; x++ ) + * { + * xTimers[ x ] = xTimerCreate( "Timer", // Just a text name, not used by the kernel. + * ( 100 * x ), // The timer period in ticks. + * pdTRUE, // The timers will auto-reload themselves when they expire. + * ( void * ) x, // Assign each timer a unique id equal to its array index. + * vTimerCallback // Each timer calls the same callback when it expires. + * ); + * + * if( xTimers[ x ] == NULL ) + * { + * // The timer was not created. + * } + * else + * { + * // Start the timer. No block time is specified, and even if one was + * // it would be ignored because the scheduler has not yet been + * // started. + * if( xTimerStart( xTimers[ x ], 0 ) != pdPASS ) + * { + * // The timer could not be set into the Active state. + * } + * } + * } + * + * // ... + * // Create tasks here. + * // ... + * + * // Starting the scheduler will start the timers running as they have already + * // been set into the active state. + * vTaskStartScheduler(); + * + * // Should not reach here. + * for( ;; ); + * } + * @endverbatim + */ +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const TickType_t xTimerPeriodInTicks, + const UBaseType_t uxAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION; +#endif + +/** + * TimerHandle_t xTimerCreateStatic(const char * const pcTimerName, + * TickType_t xTimerPeriodInTicks, + * UBaseType_t uxAutoReload, + * void * pvTimerID, + * TimerCallbackFunction_t pxCallbackFunction, + * StaticTimer_t *pxTimerBuffer ); + * + * Creates a new software timer instance, and returns a handle by which the + * created software timer can be referenced. + * + * Internally, within the FreeRTOS implementation, software timers use a block + * of memory, in which the timer data structure is stored. If a software timer + * is created using xTimerCreate() then the required memory is automatically + * dynamically allocated inside the xTimerCreate() function. (see + * https://www.FreeRTOS.org/a00111.html). If a software timer is created using + * xTimerCreateStatic() then the application writer must provide the memory that + * will get used by the software timer. xTimerCreateStatic() therefore allows a + * software timer to be created without using any dynamic memory allocation. + * + * Timers are created in the dormant state. The xTimerStart(), xTimerReset(), + * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and + * xTimerChangePeriodFromISR() API functions can all be used to transition a + * timer into the active state. + * + * @param pcTimerName A text name that is assigned to the timer. This is done + * purely to assist debugging. The kernel itself only ever references a timer + * by its handle, and never by its name. + * + * @param xTimerPeriodInTicks The timer period. The time is defined in tick + * periods so the constant portTICK_PERIOD_MS can be used to convert a time that + * has been specified in milliseconds. For example, if the timer must expire + * after 100 ticks, then xTimerPeriodInTicks should be set to 100. + * Alternatively, if the timer must expire after 500ms, then xPeriod can be set + * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or + * equal to 1000. The timer period must be greater than 0. + * + * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will + * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter. + * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and + * enter the dormant state after it expires. + * + * @param pvTimerID An identifier that is assigned to the timer being created. + * Typically this would be used in the timer callback function to identify which + * timer expired when the same callback function is assigned to more than one + * timer. + * + * @param pxCallbackFunction The function to call when the timer expires. + * Callback functions must have the prototype defined by TimerCallbackFunction_t, + * which is "void vCallbackFunction( TimerHandle_t xTimer );". + * + * @param pxTimerBuffer Must point to a variable of type StaticTimer_t, which + * will be then be used to hold the software timer's data structures, removing + * the need for the memory to be allocated dynamically. + * + * @return If the timer is created then a handle to the created timer is + * returned. If pxTimerBuffer was NULL then NULL is returned. + * + * Example usage: + * @verbatim + * + * // The buffer used to hold the software timer's data structure. + * static StaticTimer_t xTimerBuffer; + * + * // A variable that will be incremented by the software timer's callback + * // function. + * UBaseType_t uxVariableToIncrement = 0; + * + * // A software timer callback function that increments a variable passed to + * // it when the software timer was created. After the 5th increment the + * // callback function stops the software timer. + * static void prvTimerCallback( TimerHandle_t xExpiredTimer ) + * { + * UBaseType_t *puxVariableToIncrement; + * BaseType_t xReturned; + * + * // Obtain the address of the variable to increment from the timer ID. + * puxVariableToIncrement = ( UBaseType_t * ) pvTimerGetTimerID( xExpiredTimer ); + * + * // Increment the variable to show the timer callback has executed. + * ( *puxVariableToIncrement )++; + * + * // If this callback has executed the required number of times, stop the + * // timer. + * if( *puxVariableToIncrement == 5 ) + * { + * // This is called from a timer callback so must not block. + * xTimerStop( xExpiredTimer, staticDONT_BLOCK ); + * } + * } + * + * + * void main( void ) + * { + * // Create the software time. xTimerCreateStatic() has an extra parameter + * // than the normal xTimerCreate() API function. The parameter is a pointer + * // to the StaticTimer_t structure that will hold the software timer + * // structure. If the parameter is passed as NULL then the structure will be + * // allocated dynamically, just as if xTimerCreate() had been called. + * xTimer = xTimerCreateStatic( "T1", // Text name for the task. Helps debugging only. Not used by FreeRTOS. + * xTimerPeriod, // The period of the timer in ticks. + * pdTRUE, // This is an auto-reload timer. + * ( void * ) &uxVariableToIncrement, // A variable incremented by the software timer's callback function + * prvTimerCallback, // The function to execute when the timer expires. + * &xTimerBuffer ); // The buffer that will hold the software timer structure. + * + * // The scheduler has not started yet so a block time is not used. + * xReturned = xTimerStart( xTimer, 0 ); + * + * // ... + * // Create tasks here. + * // ... + * + * // Starting the scheduler will start the timers running as they have already + * // been set into the active state. + * vTaskStartScheduler(); + * + * // Should not reach here. + * for( ;; ); + * } + * @endverbatim + */ +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + TimerHandle_t xTimerCreateStatic( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const TickType_t xTimerPeriodInTicks, + const UBaseType_t uxAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction, + StaticTimer_t * pxTimerBuffer ) PRIVILEGED_FUNCTION; +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +/** + * void *pvTimerGetTimerID( TimerHandle_t xTimer ); + * + * Returns the ID assigned to the timer. + * + * IDs are assigned to timers using the pvTimerID parameter of the call to + * xTimerCreated() that was used to create the timer, and by calling the + * vTimerSetTimerID() API function. + * + * If the same callback function is assigned to multiple timers then the timer + * ID can be used as time specific (timer local) storage. + * + * @param xTimer The timer being queried. + * + * @return The ID assigned to the timer being queried. + * + * Example usage: + * + * See the xTimerCreate() API function example usage scenario. + */ +void * pvTimerGetTimerID( const TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; + +/** + * void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ); + * + * Sets the ID assigned to the timer. + * + * IDs are assigned to timers using the pvTimerID parameter of the call to + * xTimerCreated() that was used to create the timer. + * + * If the same callback function is assigned to multiple timers then the timer + * ID can be used as time specific (timer local) storage. + * + * @param xTimer The timer being updated. + * + * @param pvNewID The ID to assign to the timer. + * + * Example usage: + * + * See the xTimerCreate() API function example usage scenario. + */ +void vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) PRIVILEGED_FUNCTION; + +/** + * BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ); + * + * Queries a timer to see if it is active or dormant. + * + * A timer will be dormant if: + * 1) It has been created but not started, or + * 2) It is an expired one-shot timer that has not been restarted. + * + * Timers are created in the dormant state. The xTimerStart(), xTimerReset(), + * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and + * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the + * active state. + * + * @param xTimer The timer being queried. + * + * @return pdFALSE will be returned if the timer is dormant. A value other than + * pdFALSE will be returned if the timer is active. + * + * Example usage: + * @verbatim + * // This function assumes xTimer has already been created. + * void vAFunction( TimerHandle_t xTimer ) + * { + * if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )" + * { + * // xTimer is active, do something. + * } + * else + * { + * // xTimer is not active, do something else. + * } + * } + * @endverbatim + */ +BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; + +/** + * TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ); + * + * Simply returns the handle of the timer service/daemon task. It it not valid + * to call xTimerGetTimerDaemonTaskHandle() before the scheduler has been started. + */ +TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) PRIVILEGED_FUNCTION; + +/** + * BaseType_t xTimerStart( TimerHandle_t xTimer, TickType_t xTicksToWait ); + * + * Timer functionality is provided by a timer service/daemon task. Many of the + * public FreeRTOS timer API functions send commands to the timer service task + * through a queue called the timer command queue. The timer command queue is + * private to the kernel itself and is not directly accessible to application + * code. The length of the timer command queue is set by the + * configTIMER_QUEUE_LENGTH configuration constant. + * + * xTimerStart() starts a timer that was previously created using the + * xTimerCreate() API function. If the timer had already been started and was + * already in the active state, then xTimerStart() has equivalent functionality + * to the xTimerReset() API function. + * + * Starting a timer ensures the timer is in the active state. If the timer + * is not stopped, deleted, or reset in the mean time, the callback function + * associated with the timer will get called 'n' ticks after xTimerStart() was + * called, where 'n' is the timers defined period. + * + * It is valid to call xTimerStart() before the scheduler has been started, but + * when this is done the timer will not actually start until the scheduler is + * started, and the timers expiry time will be relative to when the scheduler is + * started, not relative to when xTimerStart() was called. + * + * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStart() + * to be available. + * + * @param xTimer The handle of the timer being started/restarted. + * + * @param xTicksToWait Specifies the time, in ticks, that the calling task should + * be held in the Blocked state to wait for the start command to be successfully + * sent to the timer command queue, should the queue already be full when + * xTimerStart() was called. xTicksToWait is ignored if xTimerStart() is called + * before the scheduler is started. + * + * @return pdFAIL will be returned if the start command could not be sent to + * the timer command queue even after xTicksToWait ticks had passed. pdPASS will + * be returned if the command was successfully sent to the timer command queue. + * When the command is actually processed will depend on the priority of the + * timer service/daemon task relative to other tasks in the system, although the + * timers expiry time is relative to when xTimerStart() is actually called. The + * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY + * configuration constant. + * + * Example usage: + * + * See the xTimerCreate() API function example usage scenario. + * + */ +#define xTimerStart( xTimer, xTicksToWait ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) ) + +/** + * BaseType_t xTimerStop( TimerHandle_t xTimer, TickType_t xTicksToWait ); + * + * Timer functionality is provided by a timer service/daemon task. Many of the + * public FreeRTOS timer API functions send commands to the timer service task + * through a queue called the timer command queue. The timer command queue is + * private to the kernel itself and is not directly accessible to application + * code. The length of the timer command queue is set by the + * configTIMER_QUEUE_LENGTH configuration constant. + * + * xTimerStop() stops a timer that was previously started using either of the + * The xTimerStart(), xTimerReset(), xTimerStartFromISR(), xTimerResetFromISR(), + * xTimerChangePeriod() or xTimerChangePeriodFromISR() API functions. + * + * Stopping a timer ensures the timer is not in the active state. + * + * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStop() + * to be available. + * + * @param xTimer The handle of the timer being stopped. + * + * @param xTicksToWait Specifies the time, in ticks, that the calling task should + * be held in the Blocked state to wait for the stop command to be successfully + * sent to the timer command queue, should the queue already be full when + * xTimerStop() was called. xTicksToWait is ignored if xTimerStop() is called + * before the scheduler is started. + * + * @return pdFAIL will be returned if the stop command could not be sent to + * the timer command queue even after xTicksToWait ticks had passed. pdPASS will + * be returned if the command was successfully sent to the timer command queue. + * When the command is actually processed will depend on the priority of the + * timer service/daemon task relative to other tasks in the system. The timer + * service/daemon task priority is set by the configTIMER_TASK_PRIORITY + * configuration constant. + * + * Example usage: + * + * See the xTimerCreate() API function example usage scenario. + * + */ +#define xTimerStop( xTimer, xTicksToWait ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0U, NULL, ( xTicksToWait ) ) + +/** + * BaseType_t xTimerChangePeriod( TimerHandle_t xTimer, + * TickType_t xNewPeriod, + * TickType_t xTicksToWait ); + * + * Timer functionality is provided by a timer service/daemon task. Many of the + * public FreeRTOS timer API functions send commands to the timer service task + * through a queue called the timer command queue. The timer command queue is + * private to the kernel itself and is not directly accessible to application + * code. The length of the timer command queue is set by the + * configTIMER_QUEUE_LENGTH configuration constant. + * + * xTimerChangePeriod() changes the period of a timer that was previously + * created using the xTimerCreate() API function. + * + * xTimerChangePeriod() can be called to change the period of an active or + * dormant state timer. + * + * The configUSE_TIMERS configuration constant must be set to 1 for + * xTimerChangePeriod() to be available. + * + * @param xTimer The handle of the timer that is having its period changed. + * + * @param xNewPeriod The new period for xTimer. Timer periods are specified in + * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time + * that has been specified in milliseconds. For example, if the timer must + * expire after 100 ticks, then xNewPeriod should be set to 100. Alternatively, + * if the timer must expire after 500ms, then xNewPeriod can be set to + * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than + * or equal to 1000. + * + * @param xTicksToWait Specifies the time, in ticks, that the calling task should + * be held in the Blocked state to wait for the change period command to be + * successfully sent to the timer command queue, should the queue already be + * full when xTimerChangePeriod() was called. xTicksToWait is ignored if + * xTimerChangePeriod() is called before the scheduler is started. + * + * @return pdFAIL will be returned if the change period command could not be + * sent to the timer command queue even after xTicksToWait ticks had passed. + * pdPASS will be returned if the command was successfully sent to the timer + * command queue. When the command is actually processed will depend on the + * priority of the timer service/daemon task relative to other tasks in the + * system. The timer service/daemon task priority is set by the + * configTIMER_TASK_PRIORITY configuration constant. + * + * Example usage: + * @verbatim + * // This function assumes xTimer has already been created. If the timer + * // referenced by xTimer is already active when it is called, then the timer + * // is deleted. If the timer referenced by xTimer is not active when it is + * // called, then the period of the timer is set to 500ms and the timer is + * // started. + * void vAFunction( TimerHandle_t xTimer ) + * { + * if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )" + * { + * // xTimer is already active - delete it. + * xTimerDelete( xTimer ); + * } + * else + * { + * // xTimer is not active, change its period to 500ms. This will also + * // cause the timer to start. Block for a maximum of 100 ticks if the + * // change period command cannot immediately be sent to the timer + * // command queue. + * if( xTimerChangePeriod( xTimer, 500 / portTICK_PERIOD_MS, 100 ) == pdPASS ) + * { + * // The command was successfully sent. + * } + * else + * { + * // The command could not be sent, even after waiting for 100 ticks + * // to pass. Take appropriate action here. + * } + * } + * } + * @endverbatim + */ +#define xTimerChangePeriod( xTimer, xNewPeriod, xTicksToWait ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), NULL, ( xTicksToWait ) ) + +/** + * BaseType_t xTimerDelete( TimerHandle_t xTimer, TickType_t xTicksToWait ); + * + * Timer functionality is provided by a timer service/daemon task. Many of the + * public FreeRTOS timer API functions send commands to the timer service task + * through a queue called the timer command queue. The timer command queue is + * private to the kernel itself and is not directly accessible to application + * code. The length of the timer command queue is set by the + * configTIMER_QUEUE_LENGTH configuration constant. + * + * xTimerDelete() deletes a timer that was previously created using the + * xTimerCreate() API function. + * + * The configUSE_TIMERS configuration constant must be set to 1 for + * xTimerDelete() to be available. + * + * @param xTimer The handle of the timer being deleted. + * + * @param xTicksToWait Specifies the time, in ticks, that the calling task should + * be held in the Blocked state to wait for the delete command to be + * successfully sent to the timer command queue, should the queue already be + * full when xTimerDelete() was called. xTicksToWait is ignored if xTimerDelete() + * is called before the scheduler is started. + * + * @return pdFAIL will be returned if the delete command could not be sent to + * the timer command queue even after xTicksToWait ticks had passed. pdPASS will + * be returned if the command was successfully sent to the timer command queue. + * When the command is actually processed will depend on the priority of the + * timer service/daemon task relative to other tasks in the system. The timer + * service/daemon task priority is set by the configTIMER_TASK_PRIORITY + * configuration constant. + * + * Example usage: + * + * See the xTimerChangePeriod() API function example usage scenario. + */ +#define xTimerDelete( xTimer, xTicksToWait ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_DELETE, 0U, NULL, ( xTicksToWait ) ) + +/** + * BaseType_t xTimerReset( TimerHandle_t xTimer, TickType_t xTicksToWait ); + * + * Timer functionality is provided by a timer service/daemon task. Many of the + * public FreeRTOS timer API functions send commands to the timer service task + * through a queue called the timer command queue. The timer command queue is + * private to the kernel itself and is not directly accessible to application + * code. The length of the timer command queue is set by the + * configTIMER_QUEUE_LENGTH configuration constant. + * + * xTimerReset() re-starts a timer that was previously created using the + * xTimerCreate() API function. If the timer had already been started and was + * already in the active state, then xTimerReset() will cause the timer to + * re-evaluate its expiry time so that it is relative to when xTimerReset() was + * called. If the timer was in the dormant state then xTimerReset() has + * equivalent functionality to the xTimerStart() API function. + * + * Resetting a timer ensures the timer is in the active state. If the timer + * is not stopped, deleted, or reset in the mean time, the callback function + * associated with the timer will get called 'n' ticks after xTimerReset() was + * called, where 'n' is the timers defined period. + * + * It is valid to call xTimerReset() before the scheduler has been started, but + * when this is done the timer will not actually start until the scheduler is + * started, and the timers expiry time will be relative to when the scheduler is + * started, not relative to when xTimerReset() was called. + * + * The configUSE_TIMERS configuration constant must be set to 1 for xTimerReset() + * to be available. + * + * @param xTimer The handle of the timer being reset/started/restarted. + * + * @param xTicksToWait Specifies the time, in ticks, that the calling task should + * be held in the Blocked state to wait for the reset command to be successfully + * sent to the timer command queue, should the queue already be full when + * xTimerReset() was called. xTicksToWait is ignored if xTimerReset() is called + * before the scheduler is started. + * + * @return pdFAIL will be returned if the reset command could not be sent to + * the timer command queue even after xTicksToWait ticks had passed. pdPASS will + * be returned if the command was successfully sent to the timer command queue. + * When the command is actually processed will depend on the priority of the + * timer service/daemon task relative to other tasks in the system, although the + * timers expiry time is relative to when xTimerStart() is actually called. The + * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY + * configuration constant. + * + * Example usage: + * @verbatim + * // When a key is pressed, an LCD back-light is switched on. If 5 seconds pass + * // without a key being pressed, then the LCD back-light is switched off. In + * // this case, the timer is a one-shot timer. + * + * TimerHandle_t xBacklightTimer = NULL; + * + * // The callback function assigned to the one-shot timer. In this case the + * // parameter is not used. + * void vBacklightTimerCallback( TimerHandle_t pxTimer ) + * { + * // The timer expired, therefore 5 seconds must have passed since a key + * // was pressed. Switch off the LCD back-light. + * vSetBacklightState( BACKLIGHT_OFF ); + * } + * + * // The key press event handler. + * void vKeyPressEventHandler( char cKey ) + * { + * // Ensure the LCD back-light is on, then reset the timer that is + * // responsible for turning the back-light off after 5 seconds of + * // key inactivity. Wait 10 ticks for the command to be successfully sent + * // if it cannot be sent immediately. + * vSetBacklightState( BACKLIGHT_ON ); + * if( xTimerReset( xBacklightTimer, 100 ) != pdPASS ) + * { + * // The reset command was not executed successfully. Take appropriate + * // action here. + * } + * + * // Perform the rest of the key processing here. + * } + * + * void main( void ) + * { + * int32_t x; + * + * // Create then start the one-shot timer that is responsible for turning + * // the back-light off if no keys are pressed within a 5 second period. + * xBacklightTimer = xTimerCreate( "BacklightTimer", // Just a text name, not used by the kernel. + * ( 5000 / portTICK_PERIOD_MS), // The timer period in ticks. + * pdFALSE, // The timer is a one-shot timer. + * 0, // The id is not used by the callback so can take any value. + * vBacklightTimerCallback // The callback function that switches the LCD back-light off. + * ); + * + * if( xBacklightTimer == NULL ) + * { + * // The timer was not created. + * } + * else + * { + * // Start the timer. No block time is specified, and even if one was + * // it would be ignored because the scheduler has not yet been + * // started. + * if( xTimerStart( xBacklightTimer, 0 ) != pdPASS ) + * { + * // The timer could not be set into the Active state. + * } + * } + * + * // ... + * // Create tasks here. + * // ... + * + * // Starting the scheduler will start the timer running as it has already + * // been set into the active state. + * vTaskStartScheduler(); + * + * // Should not reach here. + * for( ;; ); + * } + * @endverbatim + */ +#define xTimerReset( xTimer, xTicksToWait ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) ) + +/** + * BaseType_t xTimerStartFromISR( TimerHandle_t xTimer, + * BaseType_t *pxHigherPriorityTaskWoken ); + * + * A version of xTimerStart() that can be called from an interrupt service + * routine. + * + * @param xTimer The handle of the timer being started/restarted. + * + * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most + * of its time in the Blocked state, waiting for messages to arrive on the timer + * command queue. Calling xTimerStartFromISR() writes a message to the timer + * command queue, so has the potential to transition the timer service/daemon + * task out of the Blocked state. If calling xTimerStartFromISR() causes the + * timer service/daemon task to leave the Blocked state, and the timer service/ + * daemon task has a priority equal to or greater than the currently executing + * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will + * get set to pdTRUE internally within the xTimerStartFromISR() function. If + * xTimerStartFromISR() sets this value to pdTRUE then a context switch should + * be performed before the interrupt exits. + * + * @return pdFAIL will be returned if the start command could not be sent to + * the timer command queue. pdPASS will be returned if the command was + * successfully sent to the timer command queue. When the command is actually + * processed will depend on the priority of the timer service/daemon task + * relative to other tasks in the system, although the timers expiry time is + * relative to when xTimerStartFromISR() is actually called. The timer + * service/daemon task priority is set by the configTIMER_TASK_PRIORITY + * configuration constant. + * + * Example usage: + * @verbatim + * // This scenario assumes xBacklightTimer has already been created. When a + * // key is pressed, an LCD back-light is switched on. If 5 seconds pass + * // without a key being pressed, then the LCD back-light is switched off. In + * // this case, the timer is a one-shot timer, and unlike the example given for + * // the xTimerReset() function, the key press event handler is an interrupt + * // service routine. + * + * // The callback function assigned to the one-shot timer. In this case the + * // parameter is not used. + * void vBacklightTimerCallback( TimerHandle_t pxTimer ) + * { + * // The timer expired, therefore 5 seconds must have passed since a key + * // was pressed. Switch off the LCD back-light. + * vSetBacklightState( BACKLIGHT_OFF ); + * } + * + * // The key press interrupt service routine. + * void vKeyPressEventInterruptHandler( void ) + * { + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; + * + * // Ensure the LCD back-light is on, then restart the timer that is + * // responsible for turning the back-light off after 5 seconds of + * // key inactivity. This is an interrupt service routine so can only + * // call FreeRTOS API functions that end in "FromISR". + * vSetBacklightState( BACKLIGHT_ON ); + * + * // xTimerStartFromISR() or xTimerResetFromISR() could be called here + * // as both cause the timer to re-calculate its expiry time. + * // xHigherPriorityTaskWoken was initialised to pdFALSE when it was + * // declared (in this function). + * if( xTimerStartFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS ) + * { + * // The start command was not executed successfully. Take appropriate + * // action here. + * } + * + * // Perform the rest of the key processing here. + * + * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch + * // should be performed. The syntax required to perform a context switch + * // from inside an ISR varies from port to port, and from compiler to + * // compiler. Inspect the demos for the port you are using to find the + * // actual syntax required. + * if( xHigherPriorityTaskWoken != pdFALSE ) + * { + * // Call the interrupt safe yield function here (actual function + * // depends on the FreeRTOS port being used). + * } + * } + * @endverbatim + */ +#define xTimerStartFromISR( xTimer, pxHigherPriorityTaskWoken ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U ) + +/** + * BaseType_t xTimerStopFromISR( TimerHandle_t xTimer, + * BaseType_t *pxHigherPriorityTaskWoken ); + * + * A version of xTimerStop() that can be called from an interrupt service + * routine. + * + * @param xTimer The handle of the timer being stopped. + * + * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most + * of its time in the Blocked state, waiting for messages to arrive on the timer + * command queue. Calling xTimerStopFromISR() writes a message to the timer + * command queue, so has the potential to transition the timer service/daemon + * task out of the Blocked state. If calling xTimerStopFromISR() causes the + * timer service/daemon task to leave the Blocked state, and the timer service/ + * daemon task has a priority equal to or greater than the currently executing + * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will + * get set to pdTRUE internally within the xTimerStopFromISR() function. If + * xTimerStopFromISR() sets this value to pdTRUE then a context switch should + * be performed before the interrupt exits. + * + * @return pdFAIL will be returned if the stop command could not be sent to + * the timer command queue. pdPASS will be returned if the command was + * successfully sent to the timer command queue. When the command is actually + * processed will depend on the priority of the timer service/daemon task + * relative to other tasks in the system. The timer service/daemon task + * priority is set by the configTIMER_TASK_PRIORITY configuration constant. + * + * Example usage: + * @verbatim + * // This scenario assumes xTimer has already been created and started. When + * // an interrupt occurs, the timer should be simply stopped. + * + * // The interrupt service routine that stops the timer. + * void vAnExampleInterruptServiceRoutine( void ) + * { + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; + * + * // The interrupt has occurred - simply stop the timer. + * // xHigherPriorityTaskWoken was set to pdFALSE where it was defined + * // (within this function). As this is an interrupt service routine, only + * // FreeRTOS API functions that end in "FromISR" can be used. + * if( xTimerStopFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS ) + * { + * // The stop command was not executed successfully. Take appropriate + * // action here. + * } + * + * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch + * // should be performed. The syntax required to perform a context switch + * // from inside an ISR varies from port to port, and from compiler to + * // compiler. Inspect the demos for the port you are using to find the + * // actual syntax required. + * if( xHigherPriorityTaskWoken != pdFALSE ) + * { + * // Call the interrupt safe yield function here (actual function + * // depends on the FreeRTOS port being used). + * } + * } + * @endverbatim + */ +#define xTimerStopFromISR( xTimer, pxHigherPriorityTaskWoken ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP_FROM_ISR, 0, ( pxHigherPriorityTaskWoken ), 0U ) + +/** + * BaseType_t xTimerChangePeriodFromISR( TimerHandle_t xTimer, + * TickType_t xNewPeriod, + * BaseType_t *pxHigherPriorityTaskWoken ); + * + * A version of xTimerChangePeriod() that can be called from an interrupt + * service routine. + * + * @param xTimer The handle of the timer that is having its period changed. + * + * @param xNewPeriod The new period for xTimer. Timer periods are specified in + * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time + * that has been specified in milliseconds. For example, if the timer must + * expire after 100 ticks, then xNewPeriod should be set to 100. Alternatively, + * if the timer must expire after 500ms, then xNewPeriod can be set to + * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than + * or equal to 1000. + * + * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most + * of its time in the Blocked state, waiting for messages to arrive on the timer + * command queue. Calling xTimerChangePeriodFromISR() writes a message to the + * timer command queue, so has the potential to transition the timer service/ + * daemon task out of the Blocked state. If calling xTimerChangePeriodFromISR() + * causes the timer service/daemon task to leave the Blocked state, and the + * timer service/daemon task has a priority equal to or greater than the + * currently executing task (the task that was interrupted), then + * *pxHigherPriorityTaskWoken will get set to pdTRUE internally within the + * xTimerChangePeriodFromISR() function. If xTimerChangePeriodFromISR() sets + * this value to pdTRUE then a context switch should be performed before the + * interrupt exits. + * + * @return pdFAIL will be returned if the command to change the timers period + * could not be sent to the timer command queue. pdPASS will be returned if the + * command was successfully sent to the timer command queue. When the command + * is actually processed will depend on the priority of the timer service/daemon + * task relative to other tasks in the system. The timer service/daemon task + * priority is set by the configTIMER_TASK_PRIORITY configuration constant. + * + * Example usage: + * @verbatim + * // This scenario assumes xTimer has already been created and started. When + * // an interrupt occurs, the period of xTimer should be changed to 500ms. + * + * // The interrupt service routine that changes the period of xTimer. + * void vAnExampleInterruptServiceRoutine( void ) + * { + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; + * + * // The interrupt has occurred - change the period of xTimer to 500ms. + * // xHigherPriorityTaskWoken was set to pdFALSE where it was defined + * // (within this function). As this is an interrupt service routine, only + * // FreeRTOS API functions that end in "FromISR" can be used. + * if( xTimerChangePeriodFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS ) + * { + * // The command to change the timers period was not executed + * // successfully. Take appropriate action here. + * } + * + * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch + * // should be performed. The syntax required to perform a context switch + * // from inside an ISR varies from port to port, and from compiler to + * // compiler. Inspect the demos for the port you are using to find the + * // actual syntax required. + * if( xHigherPriorityTaskWoken != pdFALSE ) + * { + * // Call the interrupt safe yield function here (actual function + * // depends on the FreeRTOS port being used). + * } + * } + * @endverbatim + */ +#define xTimerChangePeriodFromISR( xTimer, xNewPeriod, pxHigherPriorityTaskWoken ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD_FROM_ISR, ( xNewPeriod ), ( pxHigherPriorityTaskWoken ), 0U ) + +/** + * BaseType_t xTimerResetFromISR( TimerHandle_t xTimer, + * BaseType_t *pxHigherPriorityTaskWoken ); + * + * A version of xTimerReset() that can be called from an interrupt service + * routine. + * + * @param xTimer The handle of the timer that is to be started, reset, or + * restarted. + * + * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most + * of its time in the Blocked state, waiting for messages to arrive on the timer + * command queue. Calling xTimerResetFromISR() writes a message to the timer + * command queue, so has the potential to transition the timer service/daemon + * task out of the Blocked state. If calling xTimerResetFromISR() causes the + * timer service/daemon task to leave the Blocked state, and the timer service/ + * daemon task has a priority equal to or greater than the currently executing + * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will + * get set to pdTRUE internally within the xTimerResetFromISR() function. If + * xTimerResetFromISR() sets this value to pdTRUE then a context switch should + * be performed before the interrupt exits. + * + * @return pdFAIL will be returned if the reset command could not be sent to + * the timer command queue. pdPASS will be returned if the command was + * successfully sent to the timer command queue. When the command is actually + * processed will depend on the priority of the timer service/daemon task + * relative to other tasks in the system, although the timers expiry time is + * relative to when xTimerResetFromISR() is actually called. The timer service/daemon + * task priority is set by the configTIMER_TASK_PRIORITY configuration constant. + * + * Example usage: + * @verbatim + * // This scenario assumes xBacklightTimer has already been created. When a + * // key is pressed, an LCD back-light is switched on. If 5 seconds pass + * // without a key being pressed, then the LCD back-light is switched off. In + * // this case, the timer is a one-shot timer, and unlike the example given for + * // the xTimerReset() function, the key press event handler is an interrupt + * // service routine. + * + * // The callback function assigned to the one-shot timer. In this case the + * // parameter is not used. + * void vBacklightTimerCallback( TimerHandle_t pxTimer ) + * { + * // The timer expired, therefore 5 seconds must have passed since a key + * // was pressed. Switch off the LCD back-light. + * vSetBacklightState( BACKLIGHT_OFF ); + * } + * + * // The key press interrupt service routine. + * void vKeyPressEventInterruptHandler( void ) + * { + * BaseType_t xHigherPriorityTaskWoken = pdFALSE; + * + * // Ensure the LCD back-light is on, then reset the timer that is + * // responsible for turning the back-light off after 5 seconds of + * // key inactivity. This is an interrupt service routine so can only + * // call FreeRTOS API functions that end in "FromISR". + * vSetBacklightState( BACKLIGHT_ON ); + * + * // xTimerStartFromISR() or xTimerResetFromISR() could be called here + * // as both cause the timer to re-calculate its expiry time. + * // xHigherPriorityTaskWoken was initialised to pdFALSE when it was + * // declared (in this function). + * if( xTimerResetFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS ) + * { + * // The reset command was not executed successfully. Take appropriate + * // action here. + * } + * + * // Perform the rest of the key processing here. + * + * // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch + * // should be performed. The syntax required to perform a context switch + * // from inside an ISR varies from port to port, and from compiler to + * // compiler. Inspect the demos for the port you are using to find the + * // actual syntax required. + * if( xHigherPriorityTaskWoken != pdFALSE ) + * { + * // Call the interrupt safe yield function here (actual function + * // depends on the FreeRTOS port being used). + * } + * } + * @endverbatim + */ +#define xTimerResetFromISR( xTimer, pxHigherPriorityTaskWoken ) \ + xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U ) + + +/** + * BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, + * void *pvParameter1, + * uint32_t ulParameter2, + * BaseType_t *pxHigherPriorityTaskWoken ); + * + * + * Used from application interrupt service routines to defer the execution of a + * function to the RTOS daemon task (the timer service task, hence this function + * is implemented in timers.c and is prefixed with 'Timer'). + * + * Ideally an interrupt service routine (ISR) is kept as short as possible, but + * sometimes an ISR either has a lot of processing to do, or needs to perform + * processing that is not deterministic. In these cases + * xTimerPendFunctionCallFromISR() can be used to defer processing of a function + * to the RTOS daemon task. + * + * A mechanism is provided that allows the interrupt to return directly to the + * task that will subsequently execute the pended callback function. This + * allows the callback function to execute contiguously in time with the + * interrupt - just as if the callback had executed in the interrupt itself. + * + * @param xFunctionToPend The function to execute from the timer service/ + * daemon task. The function must conform to the PendedFunction_t + * prototype. + * + * @param pvParameter1 The value of the callback function's first parameter. + * The parameter has a void * type to allow it to be used to pass any type. + * For example, unsigned longs can be cast to a void *, or the void * can be + * used to point to a structure. + * + * @param ulParameter2 The value of the callback function's second parameter. + * + * @param pxHigherPriorityTaskWoken As mentioned above, calling this function + * will result in a message being sent to the timer daemon task. If the + * priority of the timer daemon task (which is set using + * configTIMER_TASK_PRIORITY in FreeRTOSConfig.h) is higher than the priority of + * the currently running task (the task the interrupt interrupted) then + * *pxHigherPriorityTaskWoken will be set to pdTRUE within + * xTimerPendFunctionCallFromISR(), indicating that a context switch should be + * requested before the interrupt exits. For that reason + * *pxHigherPriorityTaskWoken must be initialised to pdFALSE. See the + * example code below. + * + * @return pdPASS is returned if the message was successfully sent to the + * timer daemon task, otherwise pdFALSE is returned. + * + * Example usage: + * @verbatim + * + * // The callback function that will execute in the context of the daemon task. + * // Note callback functions must all use this same prototype. + * void vProcessInterface( void *pvParameter1, uint32_t ulParameter2 ) + * { + * BaseType_t xInterfaceToService; + * + * // The interface that requires servicing is passed in the second + * // parameter. The first parameter is not used in this case. + * xInterfaceToService = ( BaseType_t ) ulParameter2; + * + * // ...Perform the processing here... + * } + * + * // An ISR that receives data packets from multiple interfaces + * void vAnISR( void ) + * { + * BaseType_t xInterfaceToService, xHigherPriorityTaskWoken; + * + * // Query the hardware to determine which interface needs processing. + * xInterfaceToService = prvCheckInterfaces(); + * + * // The actual processing is to be deferred to a task. Request the + * // vProcessInterface() callback function is executed, passing in the + * // number of the interface that needs processing. The interface to + * // service is passed in the second parameter. The first parameter is + * // not used in this case. + * xHigherPriorityTaskWoken = pdFALSE; + * xTimerPendFunctionCallFromISR( vProcessInterface, NULL, ( uint32_t ) xInterfaceToService, &xHigherPriorityTaskWoken ); + * + * // If xHigherPriorityTaskWoken is now set to pdTRUE then a context + * // switch should be requested. The macro used is port specific and will + * // be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to + * // the documentation page for the port being used. + * portYIELD_FROM_ISR( xHigherPriorityTaskWoken ); + * + * } + * @endverbatim + */ +BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, + void * pvParameter1, + uint32_t ulParameter2, + BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; + +/** + * BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, + * void *pvParameter1, + * uint32_t ulParameter2, + * TickType_t xTicksToWait ); + * + * + * Used to defer the execution of a function to the RTOS daemon task (the timer + * service task, hence this function is implemented in timers.c and is prefixed + * with 'Timer'). + * + * @param xFunctionToPend The function to execute from the timer service/ + * daemon task. The function must conform to the PendedFunction_t + * prototype. + * + * @param pvParameter1 The value of the callback function's first parameter. + * The parameter has a void * type to allow it to be used to pass any type. + * For example, unsigned longs can be cast to a void *, or the void * can be + * used to point to a structure. + * + * @param ulParameter2 The value of the callback function's second parameter. + * + * @param xTicksToWait Calling this function will result in a message being + * sent to the timer daemon task on a queue. xTicksToWait is the amount of + * time the calling task should remain in the Blocked state (so not using any + * processing time) for space to become available on the timer queue if the + * queue is found to be full. + * + * @return pdPASS is returned if the message was successfully sent to the + * timer daemon task, otherwise pdFALSE is returned. + * + */ +BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, + void * pvParameter1, + uint32_t ulParameter2, + TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +/** + * const char * const pcTimerGetName( TimerHandle_t xTimer ); + * + * Returns the name that was assigned to a timer when the timer was created. + * + * @param xTimer The handle of the timer being queried. + * + * @return The name assigned to the timer specified by the xTimer parameter. + */ +const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + +/** + * void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ); + * + * Updates a timer to be either an auto-reload timer, in which case the timer + * automatically resets itself each time it expires, or a one-shot timer, in + * which case the timer will only expire once unless it is manually restarted. + * + * @param xTimer The handle of the timer being updated. + * + * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will + * expire repeatedly with a frequency set by the timer's period (see the + * xTimerPeriodInTicks parameter of the xTimerCreate() API function). If + * uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and + * enter the dormant state after it expires. + */ +void vTimerSetReloadMode( TimerHandle_t xTimer, + const UBaseType_t uxAutoReload ) PRIVILEGED_FUNCTION; + +/** + * UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer ); + * + * Queries a timer to determine if it is an auto-reload timer, in which case the timer + * automatically resets itself each time it expires, or a one-shot timer, in + * which case the timer will only expire once unless it is manually restarted. + * + * @param xTimer The handle of the timer being queried. + * + * @return If the timer is an auto-reload timer then pdTRUE is returned, otherwise + * pdFALSE is returned. + */ +UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; + +/** + * TickType_t xTimerGetPeriod( TimerHandle_t xTimer ); + * + * Returns the period of a timer. + * + * @param xTimer The handle of the timer being queried. + * + * @return The period of the timer in ticks. + */ +TickType_t xTimerGetPeriod( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; + +/** + * TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ); + * + * Returns the time in ticks at which the timer will expire. If this is less + * than the current tick count then the expiry time has overflowed from the + * current time. + * + * @param xTimer The handle of the timer being queried. + * + * @return If the timer is running then the time in ticks at which the timer + * will next expire is returned. If the timer is not running then the return + * value is undefined. + */ +TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; + +/* + * Functions beyond this part are not part of the public API and are intended + * for use by the kernel only. + */ +BaseType_t xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION; +BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, + const BaseType_t xCommandID, + const TickType_t xOptionalValue, + BaseType_t * const pxHigherPriorityTaskWoken, + const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; + +#if ( configUSE_TRACE_FACILITY == 1 ) + void vTimerSetTimerNumber( TimerHandle_t xTimer, + UBaseType_t uxTimerNumber ) PRIVILEGED_FUNCTION; + UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; +#endif + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + /** + * task.h + * 
void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, StackType_t ** ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize )
+ * + * This function is used to provide a statically allocated block of memory to FreeRTOS to hold the Timer Task TCB. This function is required when + * configSUPPORT_STATIC_ALLOCATION is set. For more information see this URI: https://www.FreeRTOS.org/a00110.html#configSUPPORT_STATIC_ALLOCATION + * + * @param ppxTimerTaskTCBBuffer A handle to a statically allocated TCB buffer + * @param ppxTimerTaskStackBuffer A handle to a statically allocated Stack buffer for thie idle task + * @param pulTimerTaskStackSize A pointer to the number of elements that will fit in the allocated stack buffer + */ + void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, + StackType_t ** ppxTimerTaskStackBuffer, + uint32_t * pulTimerTaskStackSize ); + +#endif + +/* *INDENT-OFF* */ +#ifdef __cplusplus + } +#endif +/* *INDENT-ON* */ +#endif /* TIMERS_H */ diff --git a/MODULES/FreeRTOS/modular.json b/MODULES/FreeRTOS/modular.json new file mode 100644 index 0000000..94181f5 --- /dev/null +++ b/MODULES/FreeRTOS/modular.json @@ -0,0 +1,10 @@ +{ + "cmake": { + "inc_dirs": [ + "inc" + ], + "srcs": [ + "src/**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/FreeRTOS/src/croutine.c b/MODULES/FreeRTOS/src/croutine.c new file mode 100644 index 0000000..271f4b8 --- /dev/null +++ b/MODULES/FreeRTOS/src/croutine.c @@ -0,0 +1,361 @@ +/* + * FreeRTOS Kernel V10.4.3 LTS Patch 2 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include "FreeRTOS.h" +#include "task.h" +#include "croutine.h" + +/* Remove the whole file is co-routines are not being used. */ +#if ( configUSE_CO_ROUTINES != 0 ) + +/* + * Some kernel aware debuggers require data to be viewed to be global, rather + * than file scope. + */ + #ifdef portREMOVE_STATIC_QUALIFIER + #define static + #endif + + +/* Lists for ready and blocked co-routines. --------------------*/ + static List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /*< Prioritised ready co-routines. */ + static List_t xDelayedCoRoutineList1; /*< Delayed co-routines. */ + static List_t xDelayedCoRoutineList2; /*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */ + static List_t * pxDelayedCoRoutineList = NULL; /*< Points to the delayed co-routine list currently being used. */ + static List_t * pxOverflowDelayedCoRoutineList = NULL; /*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */ + static List_t xPendingReadyCoRoutineList; /*< Holds co-routines that have been readied by an external event. They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */ + +/* Other file private variables. --------------------------------*/ + CRCB_t * pxCurrentCoRoutine = NULL; + static UBaseType_t uxTopCoRoutineReadyPriority = 0; + static TickType_t xCoRoutineTickCount = 0, xLastTickCount = 0, xPassedTicks = 0; + +/* The initial state of the co-routine when it is created. */ + #define corINITIAL_STATE ( 0 ) + +/* + * Place the co-routine represented by pxCRCB into the appropriate ready queue + * for the priority. It is inserted at the end of the list. + * + * This macro accesses the co-routine ready lists and therefore must not be + * used from within an ISR. + */ + #define prvAddCoRoutineToReadyQueue( pxCRCB ) \ + { \ + if( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority ) \ + { \ + uxTopCoRoutineReadyPriority = pxCRCB->uxPriority; \ + } \ + vListInsertEnd( ( List_t * ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) ); \ + } + +/* + * Utility to ready all the lists used by the scheduler. This is called + * automatically upon the creation of the first co-routine. + */ + static void prvInitialiseCoRoutineLists( void ); + +/* + * Co-routines that are readied by an interrupt cannot be placed directly into + * the ready lists (there is no mutual exclusion). Instead they are placed in + * in the pending ready list in order that they can later be moved to the ready + * list by the co-routine scheduler. + */ + static void prvCheckPendingReadyList( void ); + +/* + * Macro that looks at the list of co-routines that are currently delayed to + * see if any require waking. + * + * Co-routines are stored in the queue in the order of their wake time - + * meaning once one co-routine has been found whose timer has not expired + * we need not look any further down the list. + */ + static void prvCheckDelayedList( void ); + +/*-----------------------------------------------------------*/ + + BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, + UBaseType_t uxPriority, + UBaseType_t uxIndex ) + { + BaseType_t xReturn; + CRCB_t * pxCoRoutine; + + /* Allocate the memory that will store the co-routine control block. */ + pxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) ); + + if( pxCoRoutine ) + { + /* If pxCurrentCoRoutine is NULL then this is the first co-routine to + * be created and the co-routine data structures need initialising. */ + if( pxCurrentCoRoutine == NULL ) + { + pxCurrentCoRoutine = pxCoRoutine; + prvInitialiseCoRoutineLists(); + } + + /* Check the priority is within limits. */ + if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES ) + { + uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1; + } + + /* Fill out the co-routine control block from the function parameters. */ + pxCoRoutine->uxState = corINITIAL_STATE; + pxCoRoutine->uxPriority = uxPriority; + pxCoRoutine->uxIndex = uxIndex; + pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode; + + /* Initialise all the other co-routine control block parameters. */ + vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) ); + vListInitialiseItem( &( pxCoRoutine->xEventListItem ) ); + + /* Set the co-routine control block as a link back from the ListItem_t. + * This is so we can get back to the containing CRCB from a generic item + * in a list. */ + listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine ); + listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine ); + + /* Event lists are always in priority order. */ + listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), ( ( TickType_t ) configMAX_CO_ROUTINE_PRIORITIES - ( TickType_t ) uxPriority ) ); + + /* Now the co-routine has been initialised it can be added to the ready + * list at the correct priority. */ + prvAddCoRoutineToReadyQueue( pxCoRoutine ); + + xReturn = pdPASS; + } + else + { + xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, + List_t * pxEventList ) + { + TickType_t xTimeToWake; + + /* Calculate the time to wake - this may overflow but this is + * not a problem. */ + xTimeToWake = xCoRoutineTickCount + xTicksToDelay; + + /* We must remove ourselves from the ready list before adding + * ourselves to the blocked list as the same list item is used for + * both lists. */ + ( void ) uxListRemove( ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) ); + + /* The list item will be inserted in wake time order. */ + listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake ); + + if( xTimeToWake < xCoRoutineTickCount ) + { + /* Wake time has overflowed. Place this item in the + * overflow list. */ + vListInsert( ( List_t * ) pxOverflowDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) ); + } + else + { + /* The wake time has not overflowed, so we can use the + * current block list. */ + vListInsert( ( List_t * ) pxDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) ); + } + + if( pxEventList ) + { + /* Also add the co-routine to an event list. If this is done then the + * function must be called with interrupts disabled. */ + vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) ); + } + } +/*-----------------------------------------------------------*/ + + static void prvCheckPendingReadyList( void ) + { + /* Are there any co-routines waiting to get moved to the ready list? These + * are co-routines that have been readied by an ISR. The ISR cannot access + * the ready lists itself. */ + while( listLIST_IS_EMPTY( &xPendingReadyCoRoutineList ) == pdFALSE ) + { + CRCB_t * pxUnblockedCRCB; + + /* The pending ready list can be accessed by an ISR. */ + portDISABLE_INTERRUPTS(); + { + pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyCoRoutineList ) ); + ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) ); + } + portENABLE_INTERRUPTS(); + + ( void ) uxListRemove( &( pxUnblockedCRCB->xGenericListItem ) ); + prvAddCoRoutineToReadyQueue( pxUnblockedCRCB ); + } + } +/*-----------------------------------------------------------*/ + + static void prvCheckDelayedList( void ) + { + CRCB_t * pxCRCB; + + xPassedTicks = xTaskGetTickCount() - xLastTickCount; + + while( xPassedTicks ) + { + xCoRoutineTickCount++; + xPassedTicks--; + + /* If the tick count has overflowed we need to swap the ready lists. */ + if( xCoRoutineTickCount == 0 ) + { + List_t * pxTemp; + + /* Tick count has overflowed so we need to swap the delay lists. If there are + * any items in pxDelayedCoRoutineList here then there is an error! */ + pxTemp = pxDelayedCoRoutineList; + pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList; + pxOverflowDelayedCoRoutineList = pxTemp; + } + + /* See if this tick has made a timeout expire. */ + while( listLIST_IS_EMPTY( pxDelayedCoRoutineList ) == pdFALSE ) + { + pxCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList ); + + if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) ) + { + /* Timeout not yet expired. */ + break; + } + + portDISABLE_INTERRUPTS(); + { + /* The event could have occurred just before this critical + * section. If this is the case then the generic list item will + * have been moved to the pending ready list and the following + * line is still valid. Also the pvContainer parameter will have + * been set to NULL so the following lines are also valid. */ + ( void ) uxListRemove( &( pxCRCB->xGenericListItem ) ); + + /* Is the co-routine waiting on an event also? */ + if( pxCRCB->xEventListItem.pxContainer ) + { + ( void ) uxListRemove( &( pxCRCB->xEventListItem ) ); + } + } + portENABLE_INTERRUPTS(); + + prvAddCoRoutineToReadyQueue( pxCRCB ); + } + } + + xLastTickCount = xCoRoutineTickCount; + } +/*-----------------------------------------------------------*/ + + void vCoRoutineSchedule( void ) + { + /* Only run a co-routine after prvInitialiseCoRoutineLists() has been + * called. prvInitialiseCoRoutineLists() is called automatically when a + * co-routine is created. */ + if( pxDelayedCoRoutineList != NULL ) + { + /* See if any co-routines readied by events need moving to the ready lists. */ + prvCheckPendingReadyList(); + + /* See if any delayed co-routines have timed out. */ + prvCheckDelayedList(); + + /* Find the highest priority queue that contains ready co-routines. */ + while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) ) + { + if( uxTopCoRoutineReadyPriority == 0 ) + { + /* No more co-routines to check. */ + return; + } + + --uxTopCoRoutineReadyPriority; + } + + /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines + * of the same priority get an equal share of the processor time. */ + listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ); + + /* Call the co-routine. */ + ( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex ); + } + } +/*-----------------------------------------------------------*/ + + static void prvInitialiseCoRoutineLists( void ) + { + UBaseType_t uxPriority; + + for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ ) + { + vListInitialise( ( List_t * ) &( pxReadyCoRoutineLists[ uxPriority ] ) ); + } + + vListInitialise( ( List_t * ) &xDelayedCoRoutineList1 ); + vListInitialise( ( List_t * ) &xDelayedCoRoutineList2 ); + vListInitialise( ( List_t * ) &xPendingReadyCoRoutineList ); + + /* Start with pxDelayedCoRoutineList using list1 and the + * pxOverflowDelayedCoRoutineList using list2. */ + pxDelayedCoRoutineList = &xDelayedCoRoutineList1; + pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2; + } +/*-----------------------------------------------------------*/ + + BaseType_t xCoRoutineRemoveFromEventList( const List_t * pxEventList ) + { + CRCB_t * pxUnblockedCRCB; + BaseType_t xReturn; + + /* This function is called from within an interrupt. It can only access + * event lists and the pending ready list. This function assumes that a + * check has already been made to ensure pxEventList is not empty. */ + pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); + ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) ); + vListInsertEnd( ( List_t * ) &( xPendingReadyCoRoutineList ), &( pxUnblockedCRCB->xEventListItem ) ); + + if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; + } + +#endif /* configUSE_CO_ROUTINES == 0 */ diff --git a/MODULES/FreeRTOS/src/event_groups.c b/MODULES/FreeRTOS/src/event_groups.c new file mode 100644 index 0000000..31e2e3f --- /dev/null +++ b/MODULES/FreeRTOS/src/event_groups.c @@ -0,0 +1,771 @@ +/* + * FreeRTOS Kernel V10.4.3 LTS Patch 2 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "event_groups.h" + +/* Lint e961, e750 and e9021 are suppressed as a MISRA exception justified + * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined + * for the header files above, but not in this file, in order to generate the + * correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021 See comment above. */ + +/* The following bit fields convey control information in a task's event list + * item value. It is important they don't clash with the + * taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */ +#if configUSE_16_BIT_TICKS == 1 + #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x0100U + #define eventUNBLOCKED_DUE_TO_BIT_SET 0x0200U + #define eventWAIT_FOR_ALL_BITS 0x0400U + #define eventEVENT_BITS_CONTROL_BYTES 0xff00U +#else + #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x01000000UL + #define eventUNBLOCKED_DUE_TO_BIT_SET 0x02000000UL + #define eventWAIT_FOR_ALL_BITS 0x04000000UL + #define eventEVENT_BITS_CONTROL_BYTES 0xff000000UL +#endif + +typedef struct EventGroupDef_t +{ + EventBits_t uxEventBits; + List_t xTasksWaitingForBits; /*< List of tasks waiting for a bit to be set. */ + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxEventGroupNumber; + #endif + + #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the event group is statically allocated to ensure no attempt is made to free the memory. */ + #endif +} EventGroup_t; + +/*-----------------------------------------------------------*/ + +/* + * Test the bits set in uxCurrentEventBits to see if the wait condition is met. + * The wait condition is defined by xWaitForAllBits. If xWaitForAllBits is + * pdTRUE then the wait condition is met if all the bits set in uxBitsToWaitFor + * are also set in uxCurrentEventBits. If xWaitForAllBits is pdFALSE then the + * wait condition is met if any of the bits set in uxBitsToWait for are also set + * in uxCurrentEventBits. + */ +static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, + const EventBits_t uxBitsToWaitFor, + const BaseType_t xWaitForAllBits ) PRIVILEGED_FUNCTION; + +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) + { + EventGroup_t * pxEventBits; + + /* A StaticEventGroup_t object must be provided. */ + configASSERT( pxEventGroupBuffer ); + + #if ( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + * variable of type StaticEventGroup_t equals the size of the real + * event group structure. */ + volatile size_t xSize = sizeof( StaticEventGroup_t ); + configASSERT( xSize == sizeof( EventGroup_t ) ); + } /*lint !e529 xSize is referenced if configASSERT() is defined. */ + #endif /* configASSERT_DEFINED */ + + /* The user has provided a statically allocated event group - use it. */ + pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; /*lint !e740 !e9087 EventGroup_t and StaticEventGroup_t are deliberately aliased for data hiding purposes and guaranteed to have the same size and alignment requirement - checked by configASSERT(). */ + + if( pxEventBits != NULL ) + { + pxEventBits->uxEventBits = 0; + vListInitialise( &( pxEventBits->xTasksWaitingForBits ) ); + + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + /* Both static and dynamic allocation can be used, so note that + * this event group was created statically in case the event group + * is later deleted. */ + pxEventBits->ucStaticallyAllocated = pdTRUE; + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + + traceEVENT_GROUP_CREATE( pxEventBits ); + } + else + { + /* xEventGroupCreateStatic should only ever be called with + * pxEventGroupBuffer pointing to a pre-allocated (compile time + * allocated) StaticEventGroup_t variable. */ + traceEVENT_GROUP_CREATE_FAILED(); + } + + return pxEventBits; + } + +#endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + EventGroupHandle_t xEventGroupCreate( void ) + { + EventGroup_t * pxEventBits; + + /* Allocate the event group. Justification for MISRA deviation as + * follows: pvPortMalloc() always ensures returned memory blocks are + * aligned per the requirements of the MCU stack. In this case + * pvPortMalloc() must return a pointer that is guaranteed to meet the + * alignment requirements of the EventGroup_t structure - which (if you + * follow it through) is the alignment requirements of the TickType_t type + * (EventBits_t being of TickType_t itself). Therefore, whenever the + * stack alignment requirements are greater than or equal to the + * TickType_t alignment requirements the cast is safe. In other cases, + * where the natural word size of the architecture is less than + * sizeof( TickType_t ), the TickType_t variables will be accessed in two + * or more reads operations, and the alignment requirements is only that + * of each individual read. */ + pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) ); /*lint !e9087 !e9079 see comment above. */ + + if( pxEventBits != NULL ) + { + pxEventBits->uxEventBits = 0; + vListInitialise( &( pxEventBits->xTasksWaitingForBits ) ); + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + /* Both static and dynamic allocation can be used, so note this + * event group was allocated statically in case the event group is + * later deleted. */ + pxEventBits->ucStaticallyAllocated = pdFALSE; + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + + traceEVENT_GROUP_CREATE( pxEventBits ); + } + else + { + traceEVENT_GROUP_CREATE_FAILED(); /*lint !e9063 Else branch only exists to allow tracing and does not generate code if trace macros are not defined. */ + } + + return pxEventBits; + } + +#endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + const EventBits_t uxBitsToWaitFor, + TickType_t xTicksToWait ) +{ + EventBits_t uxOriginalBitValue, uxReturn; + EventGroup_t * pxEventBits = xEventGroup; + BaseType_t xAlreadyYielded; + BaseType_t xTimeoutOccurred = pdFALSE; + + configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + configASSERT( uxBitsToWaitFor != 0 ); + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + vTaskSuspendAll(); + { + uxOriginalBitValue = pxEventBits->uxEventBits; + + ( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet ); + + if( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor ) + { + /* All the rendezvous bits are now set - no need to block. */ + uxReturn = ( uxOriginalBitValue | uxBitsToSet ); + + /* Rendezvous always clear the bits. They will have been cleared + * already unless this is the only task in the rendezvous. */ + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + + xTicksToWait = 0; + } + else + { + if( xTicksToWait != ( TickType_t ) 0 ) + { + traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor ); + + /* Store the bits that the calling task is waiting for in the + * task's event list item so the kernel knows when a match is + * found. Then enter the blocked state. */ + vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait ); + + /* This assignment is obsolete as uxReturn will get set after + * the task unblocks, but some compilers mistakenly generate a + * warning about uxReturn being returned without being set if the + * assignment is omitted. */ + uxReturn = 0; + } + else + { + /* The rendezvous bits were not set, but no block time was + * specified - just return the current event bit value. */ + uxReturn = pxEventBits->uxEventBits; + xTimeoutOccurred = pdTRUE; + } + } + } + xAlreadyYielded = xTaskResumeAll(); + + if( xTicksToWait != ( TickType_t ) 0 ) + { + if( xAlreadyYielded == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The task blocked to wait for its required bits to be set - at this + * point either the required bits were set or the block time expired. If + * the required bits were set they will have been stored in the task's + * event list item, and they should now be retrieved then cleared. */ + uxReturn = uxTaskResetEventItemValue(); + + if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 ) + { + /* The task timed out, just return the current event bit value. */ + taskENTER_CRITICAL(); + { + uxReturn = pxEventBits->uxEventBits; + + /* Although the task got here because it timed out before the + * bits it was waiting for were set, it is possible that since it + * unblocked another task has set the bits. If this is the case + * then it needs to clear the bits before exiting. */ + if( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor ) + { + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + xTimeoutOccurred = pdTRUE; + } + else + { + /* The task unblocked because the bits were set. */ + } + + /* Control bits might be set as the task had blocked should not be + * returned. */ + uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES; + } + + traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xTimeoutOccurred; + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToWaitFor, + const BaseType_t xClearOnExit, + const BaseType_t xWaitForAllBits, + TickType_t xTicksToWait ) +{ + EventGroup_t * pxEventBits = xEventGroup; + EventBits_t uxReturn, uxControlBits = 0; + BaseType_t xWaitConditionMet, xAlreadyYielded; + BaseType_t xTimeoutOccurred = pdFALSE; + + /* Check the user is not attempting to wait on the bits used by the kernel + * itself, and that at least one bit is being requested. */ + configASSERT( xEventGroup ); + configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + configASSERT( uxBitsToWaitFor != 0 ); + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + vTaskSuspendAll(); + { + const EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits; + + /* Check to see if the wait condition is already met or not. */ + xWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits ); + + if( xWaitConditionMet != pdFALSE ) + { + /* The wait condition has already been met so there is no need to + * block. */ + uxReturn = uxCurrentEventBits; + xTicksToWait = ( TickType_t ) 0; + + /* Clear the wait bits if requested to do so. */ + if( xClearOnExit != pdFALSE ) + { + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else if( xTicksToWait == ( TickType_t ) 0 ) + { + /* The wait condition has not been met, but no block time was + * specified, so just return the current value. */ + uxReturn = uxCurrentEventBits; + xTimeoutOccurred = pdTRUE; + } + else + { + /* The task is going to block to wait for its required bits to be + * set. uxControlBits are used to remember the specified behaviour of + * this call to xEventGroupWaitBits() - for use when the event bits + * unblock the task. */ + if( xClearOnExit != pdFALSE ) + { + uxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xWaitForAllBits != pdFALSE ) + { + uxControlBits |= eventWAIT_FOR_ALL_BITS; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Store the bits that the calling task is waiting for in the + * task's event list item so the kernel knows when a match is + * found. Then enter the blocked state. */ + vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait ); + + /* This is obsolete as it will get set after the task unblocks, but + * some compilers mistakenly generate a warning about the variable + * being returned without being set if it is not done. */ + uxReturn = 0; + + traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor ); + } + } + xAlreadyYielded = xTaskResumeAll(); + + if( xTicksToWait != ( TickType_t ) 0 ) + { + if( xAlreadyYielded == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The task blocked to wait for its required bits to be set - at this + * point either the required bits were set or the block time expired. If + * the required bits were set they will have been stored in the task's + * event list item, and they should now be retrieved then cleared. */ + uxReturn = uxTaskResetEventItemValue(); + + if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 ) + { + taskENTER_CRITICAL(); + { + /* The task timed out, just return the current event bit value. */ + uxReturn = pxEventBits->uxEventBits; + + /* It is possible that the event bits were updated between this + * task leaving the Blocked state and running again. */ + if( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pdFALSE ) + { + if( xClearOnExit != pdFALSE ) + { + pxEventBits->uxEventBits &= ~uxBitsToWaitFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xTimeoutOccurred = pdTRUE; + } + taskEXIT_CRITICAL(); + } + else + { + /* The task unblocked because the bits were set. */ + } + + /* The task blocked so control bits may have been set. */ + uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES; + } + + traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ); + + /* Prevent compiler warnings when trace macros are not used. */ + ( void ) xTimeoutOccurred; + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) +{ + EventGroup_t * pxEventBits = xEventGroup; + EventBits_t uxReturn; + + /* Check the user is not attempting to clear the bits used by the kernel + * itself. */ + configASSERT( xEventGroup ); + configASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + + taskENTER_CRITICAL(); + { + traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear ); + + /* The value returned is the event group value prior to the bits being + * cleared. */ + uxReturn = pxEventBits->uxEventBits; + + /* Clear the bits. */ + pxEventBits->uxEventBits &= ~uxBitsToClear; + } + taskEXIT_CRITICAL(); + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) + + BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToClear ) + { + BaseType_t xReturn; + + traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear ); + xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */ + + return xReturn; + } + +#endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */ +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) +{ + UBaseType_t uxSavedInterruptStatus; + EventGroup_t const * const pxEventBits = xEventGroup; + EventBits_t uxReturn; + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + uxReturn = pxEventBits->uxEventBits; + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return uxReturn; +} /*lint !e818 EventGroupHandle_t is a typedef used in other functions to so can't be pointer to const. */ +/*-----------------------------------------------------------*/ + +EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet ) +{ + ListItem_t * pxListItem, * pxNext; + ListItem_t const * pxListEnd; + List_t const * pxList; + EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits; + EventGroup_t * pxEventBits = xEventGroup; + BaseType_t xMatchFound = pdFALSE; + + /* Check the user is not attempting to set the bits used by the kernel + * itself. */ + configASSERT( xEventGroup ); + configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); + + pxList = &( pxEventBits->xTasksWaitingForBits ); + pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + vTaskSuspendAll(); + { + traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet ); + + pxListItem = listGET_HEAD_ENTRY( pxList ); + + /* Set the bits. */ + pxEventBits->uxEventBits |= uxBitsToSet; + + /* See if the new bit value should unblock any tasks. */ + while( pxListItem != pxListEnd ) + { + pxNext = listGET_NEXT( pxListItem ); + uxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem ); + xMatchFound = pdFALSE; + + /* Split the bits waited for from the control bits. */ + uxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES; + uxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES; + + if( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 ) + { + /* Just looking for single bit being set. */ + if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 ) + { + xMatchFound = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor ) + { + /* All bits are set. */ + xMatchFound = pdTRUE; + } + else + { + /* Need all bits to be set, but not all the bits were set. */ + } + + if( xMatchFound != pdFALSE ) + { + /* The bits match. Should the bits be cleared on exit? */ + if( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 ) + { + uxBitsToClear |= uxBitsWaitedFor; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Store the actual event flag value in the task's event list + * item before removing the task from the event list. The + * eventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows + * that is was unblocked due to its required bits matching, rather + * than because it timed out. */ + vTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET ); + } + + /* Move onto the next list item. Note pxListItem->pxNext is not + * used here as the list item may have been removed from the event list + * and inserted into the ready/pending reading list. */ + pxListItem = pxNext; + } + + /* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT + * bit was set in the control word. */ + pxEventBits->uxEventBits &= ~uxBitsToClear; + } + ( void ) xTaskResumeAll(); + + return pxEventBits->uxEventBits; +} +/*-----------------------------------------------------------*/ + +void vEventGroupDelete( EventGroupHandle_t xEventGroup ) +{ + EventGroup_t * pxEventBits = xEventGroup; + const List_t * pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits ); + + vTaskSuspendAll(); + { + traceEVENT_GROUP_DELETE( xEventGroup ); + + while( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 ) + { + /* Unblock the task, returning 0 as the event list is being deleted + * and cannot therefore have any bits set. */ + configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( const ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) ); + vTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET ); + } + + #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) ) + { + /* The event group can only have been allocated dynamically - free + * it again. */ + vPortFree( pxEventBits ); + } + #elif ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + { + /* The event group could have been allocated statically or + * dynamically, so check before attempting to free the memory. */ + if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdFALSE ) + { + vPortFree( pxEventBits ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + } + ( void ) xTaskResumeAll(); +} +/*-----------------------------------------------------------*/ + +/* For internal use only - execute a 'set bits' command that was pended from + * an interrupt. */ +void vEventGroupSetBitsCallback( void * pvEventGroup, + const uint32_t ulBitsToSet ) +{ + ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */ +} +/*-----------------------------------------------------------*/ + +/* For internal use only - execute a 'clear bits' command that was pended from + * an interrupt. */ +void vEventGroupClearBitsCallback( void * pvEventGroup, + const uint32_t ulBitsToClear ) +{ + ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */ +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, + const EventBits_t uxBitsToWaitFor, + const BaseType_t xWaitForAllBits ) +{ + BaseType_t xWaitConditionMet = pdFALSE; + + if( xWaitForAllBits == pdFALSE ) + { + /* Task only has to wait for one bit within uxBitsToWaitFor to be + * set. Is one already set? */ + if( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 ) + { + xWaitConditionMet = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* Task has to wait for all the bits in uxBitsToWaitFor to be set. + * Are they set already? */ + if( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor ) + { + xWaitConditionMet = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + return xWaitConditionMet; +} +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) + + BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, + const EventBits_t uxBitsToSet, + BaseType_t * pxHigherPriorityTaskWoken ) + { + BaseType_t xReturn; + + traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet ); + xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */ + + return xReturn; + } + +#endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t uxEventGroupGetNumber( void * xEventGroup ) + { + UBaseType_t xReturn; + EventGroup_t const * pxEventBits = ( EventGroup_t * ) xEventGroup; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */ + + if( xEventGroup == NULL ) + { + xReturn = 0; + } + else + { + xReturn = pxEventBits->uxEventGroupNumber; + } + + return xReturn; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + void vEventGroupSetNumber( void * xEventGroup, + UBaseType_t uxEventGroupNumber ) + { + ( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */ + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ diff --git a/MODULES/FreeRTOS/src/list.c b/MODULES/FreeRTOS/src/list.c new file mode 100644 index 0000000..a84b1f3 --- /dev/null +++ b/MODULES/FreeRTOS/src/list.c @@ -0,0 +1,210 @@ +/* + * FreeRTOS Kernel V10.4.3 LTS Patch 2 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#include "FreeRTOS.h" +#include "list.h" + +/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified + * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be + * defined for the header files above, but not in this file, in order to + * generate the correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */ + +/*----------------------------------------------------------- +* PUBLIC LIST API documented in list.h +*----------------------------------------------------------*/ + +void vListInitialise( List_t * const pxList ) +{ + /* The list structure contains a list item which is used to mark the + * end of the list. To initialise the list the list end is inserted + * as the only list entry. */ + pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + + /* The list end value is the highest possible value in the list to + * ensure it remains at the end of the list. */ + pxList->xListEnd.xItemValue = portMAX_DELAY; + + /* The list end next and previous pointers point to itself so we know + * when the list is empty. */ + pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ + + pxList->uxNumberOfItems = ( UBaseType_t ) 0U; + + /* Write known values into the list if + * configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ); + listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ); +} +/*-----------------------------------------------------------*/ + +void vListInitialiseItem( ListItem_t * const pxItem ) +{ + /* Make sure the list item is not recorded as being on a list. */ + pxItem->pxContainer = NULL; + + /* Write known values into the list item if + * configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ + listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); + listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); +} +/*-----------------------------------------------------------*/ + +void vListInsertEnd( List_t * const pxList, + ListItem_t * const pxNewListItem ) +{ + ListItem_t * const pxIndex = pxList->pxIndex; + + /* Only effective when configASSERT() is also defined, these tests may catch + * the list data structures being overwritten in memory. They will not catch + * data errors caused by incorrect configuration or use of FreeRTOS. */ + listTEST_LIST_INTEGRITY( pxList ); + listTEST_LIST_ITEM_INTEGRITY( pxNewListItem ); + + /* Insert a new list item into pxList, but rather than sort the list, + * makes the new list item the last item to be removed by a call to + * listGET_OWNER_OF_NEXT_ENTRY(). */ + pxNewListItem->pxNext = pxIndex; + pxNewListItem->pxPrevious = pxIndex->pxPrevious; + + /* Only used during decision coverage testing. */ + mtCOVERAGE_TEST_DELAY(); + + pxIndex->pxPrevious->pxNext = pxNewListItem; + pxIndex->pxPrevious = pxNewListItem; + + /* Remember which list the item is in. */ + pxNewListItem->pxContainer = pxList; + + ( pxList->uxNumberOfItems )++; +} +/*-----------------------------------------------------------*/ + +void vListInsert( List_t * const pxList, + ListItem_t * const pxNewListItem ) +{ + ListItem_t * pxIterator; + const TickType_t xValueOfInsertion = pxNewListItem->xItemValue; + + /* Only effective when configASSERT() is also defined, these tests may catch + * the list data structures being overwritten in memory. They will not catch + * data errors caused by incorrect configuration or use of FreeRTOS. */ + listTEST_LIST_INTEGRITY( pxList ); + listTEST_LIST_ITEM_INTEGRITY( pxNewListItem ); + + /* Insert the new list item into the list, sorted in xItemValue order. + * + * If the list already contains a list item with the same item value then the + * new list item should be placed after it. This ensures that TCBs which are + * stored in ready lists (all of which have the same xItemValue value) get a + * share of the CPU. However, if the xItemValue is the same as the back marker + * the iteration loop below will not end. Therefore the value is checked + * first, and the algorithm slightly modified if necessary. */ + if( xValueOfInsertion == portMAX_DELAY ) + { + pxIterator = pxList->xListEnd.pxPrevious; + } + else + { + /* *** NOTE *********************************************************** + * If you find your application is crashing here then likely causes are + * listed below. In addition see https://www.FreeRTOS.org/FAQHelp.html for + * more tips, and ensure configASSERT() is defined! + * https://www.FreeRTOS.org/a00110.html#configASSERT + * + * 1) Stack overflow - + * see https://www.FreeRTOS.org/Stacks-and-stack-overflow-checking.html + * 2) Incorrect interrupt priority assignment, especially on Cortex-M + * parts where numerically high priority values denote low actual + * interrupt priorities, which can seem counter intuitive. See + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html and the definition + * of configMAX_SYSCALL_INTERRUPT_PRIORITY on + * https://www.FreeRTOS.org/a00110.html + * 3) Calling an API function from within a critical section or when + * the scheduler is suspended, or calling an API function that does + * not end in "FromISR" from an interrupt. + * 4) Using a queue or semaphore before it has been initialised or + * before the scheduler has been started (are interrupts firing + * before vTaskStartScheduler() has been called?). + **********************************************************************/ + + for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */ + { + /* There is nothing to do here, just iterating to the wanted + * insertion position. */ + } + } + + pxNewListItem->pxNext = pxIterator->pxNext; + pxNewListItem->pxNext->pxPrevious = pxNewListItem; + pxNewListItem->pxPrevious = pxIterator; + pxIterator->pxNext = pxNewListItem; + + /* Remember which list the item is in. This allows fast removal of the + * item later. */ + pxNewListItem->pxContainer = pxList; + + ( pxList->uxNumberOfItems )++; +} +/*-----------------------------------------------------------*/ + +UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) +{ +/* The list item knows which list it is in. Obtain the list from the list + * item. */ + List_t * const pxList = pxItemToRemove->pxContainer; + + pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; + pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; + + /* Only used during decision coverage testing. */ + mtCOVERAGE_TEST_DELAY(); + + /* Make sure the index is left pointing to a valid item. */ + if( pxList->pxIndex == pxItemToRemove ) + { + pxList->pxIndex = pxItemToRemove->pxPrevious; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + pxItemToRemove->pxContainer = NULL; + ( pxList->uxNumberOfItems )--; + + return pxList->uxNumberOfItems; +} +/*-----------------------------------------------------------*/ diff --git a/MODULES/FreeRTOS/src/queue.c b/MODULES/FreeRTOS/src/queue.c new file mode 100644 index 0000000..3103212 --- /dev/null +++ b/MODULES/FreeRTOS/src/queue.c @@ -0,0 +1,3016 @@ +/* + * FreeRTOS Kernel V10.4.3 LTS Patch 2 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +#if ( configUSE_CO_ROUTINES == 1 ) + #include "croutine.h" +#endif + +/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified + * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined + * for the header files above, but not in this file, in order to generate the + * correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */ + + +/* Constants used with the cRxLock and cTxLock structure members. */ +#define queueUNLOCKED ( ( int16_t ) -1 ) +#define queueLOCKED_UNMODIFIED ( ( int16_t ) 0 ) +#define queueINT16_MAX ( ( int16_t ) 0x7fff ) + +/* When the Queue_t structure is used to represent a base queue its pcHead and + * pcTail members are used as pointers into the queue storage area. When the + * Queue_t structure is used to represent a mutex pcHead and pcTail pointers are + * not necessary, and the pcHead pointer is set to NULL to indicate that the + * structure instead holds a pointer to the mutex holder (if any). Map alternative + * names to the pcHead and structure member to ensure the readability of the code + * is maintained. The QueuePointers_t and SemaphoreData_t types are used to form + * a union as their usage is mutually exclusive dependent on what the queue is + * being used for. */ +#define uxQueueType pcHead +#define queueQUEUE_IS_MUTEX NULL + +typedef struct QueuePointers +{ + int8_t * pcTail; /*< Points to the byte at the end of the queue storage area. Once more byte is allocated than necessary to store the queue items, this is used as a marker. */ + int8_t * pcReadFrom; /*< Points to the last place that a queued item was read from when the structure is used as a queue. */ +} QueuePointers_t; + +typedef struct SemaphoreData +{ + TaskHandle_t xMutexHolder; /*< The handle of the task that holds the mutex. */ + UBaseType_t uxRecursiveCallCount; /*< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */ +} SemaphoreData_t; + +/* Semaphores do not actually store or copy data, so have an item size of + * zero. */ +#define queueSEMAPHORE_QUEUE_ITEM_LENGTH ( ( UBaseType_t ) 0 ) +#define queueMUTEX_GIVE_BLOCK_TIME ( ( TickType_t ) 0U ) + +#if ( configUSE_PREEMPTION == 0 ) + +/* If the cooperative scheduler is being used then a yield should not be + * performed just because a higher priority task has been woken. */ + #define queueYIELD_IF_USING_PREEMPTION() +#else + #define queueYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API() +#endif + +/* + * Definition of the queue used by the scheduler. + * Items are queued by copy, not reference. See the following link for the + * rationale: https://www.FreeRTOS.org/Embedded-RTOS-Queues.html + */ +typedef struct QueueDefinition /* The old naming convention is used to prevent breaking kernel aware debuggers. */ +{ + int8_t * pcHead; /*< Points to the beginning of the queue storage area. */ + int8_t * pcWriteTo; /*< Points to the free next place in the storage area. */ + + union + { + QueuePointers_t xQueue; /*< Data required exclusively when this structure is used as a queue. */ + SemaphoreData_t xSemaphore; /*< Data required exclusively when this structure is used as a semaphore. */ + } u; + + List_t xTasksWaitingToSend; /*< List of tasks that are blocked waiting to post onto this queue. Stored in priority order. */ + List_t xTasksWaitingToReceive; /*< List of tasks that are blocked waiting to read from this queue. Stored in priority order. */ + + volatile UBaseType_t uxMessagesWaiting; /*< The number of items currently in the queue. */ + UBaseType_t uxLength; /*< The length of the queue defined as the number of items it will hold, not the number of bytes. */ + UBaseType_t uxItemSize; /*< The size of each items that the queue will hold. */ + + volatile int16_t cRxLock; /*< Stores the number of items received from the queue (removed from the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */ + volatile int16_t cTxLock; /*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked. Set to queueUNLOCKED when the queue is not locked. */ + + #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the memory used by the queue was statically allocated to ensure no attempt is made to free the memory. */ + #endif + + #if ( configUSE_QUEUE_SETS == 1 ) + struct QueueDefinition * pxQueueSetContainer; + #endif + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxQueueNumber; + uint8_t ucQueueType; + #endif +} xQUEUE; + +/* The old xQUEUE name is maintained above then typedefed to the new Queue_t + * name below to enable the use of older kernel aware debuggers. */ +typedef xQUEUE Queue_t; + +/*-----------------------------------------------------------*/ + +/* + * The queue registry is just a means for kernel aware debuggers to locate + * queue structures. It has no other purpose so is an optional component. + */ +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + +/* The type stored within the queue registry array. This allows a name + * to be assigned to each queue making kernel aware debugging a little + * more user friendly. */ + typedef struct QUEUE_REGISTRY_ITEM + { + const char * pcQueueName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + QueueHandle_t xHandle; + } xQueueRegistryItem; + +/* The old xQueueRegistryItem name is maintained above then typedefed to the + * new xQueueRegistryItem name below to enable the use of older kernel aware + * debuggers. */ + typedef xQueueRegistryItem QueueRegistryItem_t; + +/* The queue registry is simply an array of QueueRegistryItem_t structures. + * The pcQueueName member of a structure being NULL is indicative of the + * array position being vacant. */ + PRIVILEGED_DATA QueueRegistryItem_t xQueueRegistry[ configQUEUE_REGISTRY_SIZE ]; + +#endif /* configQUEUE_REGISTRY_SIZE */ + +/* + * Unlocks a queue locked by a call to prvLockQueue. Locking a queue does not + * prevent an ISR from adding or removing items to the queue, but does prevent + * an ISR from removing tasks from the queue event lists. If an ISR finds a + * queue is locked it will instead increment the appropriate queue lock count + * to indicate that a task may require unblocking. When the queue in unlocked + * these lock counts are inspected, and the appropriate action taken. + */ +static void prvUnlockQueue( Queue_t * const pxQueue ) PRIVILEGED_FUNCTION; + +/* + * Uses a critical section to determine if there is any data in a queue. + * + * @return pdTRUE if the queue contains no items, otherwise pdFALSE. + */ +static BaseType_t prvIsQueueEmpty( const Queue_t * pxQueue ) PRIVILEGED_FUNCTION; + +/* + * Uses a critical section to determine if there is any space in a queue. + * + * @return pdTRUE if there is no space, otherwise pdFALSE; + */ +static BaseType_t prvIsQueueFull( const Queue_t * pxQueue ) PRIVILEGED_FUNCTION; + +/* + * Copies an item into the queue, either at the front of the queue or the + * back of the queue. + */ +static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, + const void * pvItemToQueue, + const BaseType_t xPosition ) PRIVILEGED_FUNCTION; + +/* + * Copies an item out of a queue. + */ +static void prvCopyDataFromQueue( Queue_t * const pxQueue, + void * const pvBuffer ) PRIVILEGED_FUNCTION; + +#if ( configUSE_QUEUE_SETS == 1 ) + +/* + * Checks to see if a queue is a member of a queue set, and if so, notifies + * the queue set that the queue contains data. + */ + static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION; +#endif + +/* + * Called after a Queue_t structure has been allocated either statically or + * dynamically to fill in the structure's members. + */ +static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + uint8_t * pucQueueStorage, + const uint8_t ucQueueType, + Queue_t * pxNewQueue ) PRIVILEGED_FUNCTION; + +/* + * Mutexes are a special type of queue. When a mutex is created, first the + * queue is created, then prvInitialiseMutex() is called to configure the queue + * as a mutex. + */ +#if ( configUSE_MUTEXES == 1 ) + static void prvInitialiseMutex( Queue_t * pxNewQueue ) PRIVILEGED_FUNCTION; +#endif + +#if ( configUSE_MUTEXES == 1 ) + +/* + * If a task waiting for a mutex causes the mutex holder to inherit a + * priority, but the waiting task times out, then the holder should + * disinherit the priority - but only down to the highest priority of any + * other tasks that are waiting for the same mutex. This function returns + * that priority. + */ + static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION; +#endif +/*-----------------------------------------------------------*/ + +/* + * Macro to mark a queue as locked. Locking a queue prevents an ISR from + * accessing the queue event lists. + */ +#define prvLockQueue( pxQueue ) \ + taskENTER_CRITICAL(); \ + { \ + if( ( pxQueue )->cRxLock == queueUNLOCKED ) \ + { \ + ( pxQueue )->cRxLock = queueLOCKED_UNMODIFIED; \ + } \ + if( ( pxQueue )->cTxLock == queueUNLOCKED ) \ + { \ + ( pxQueue )->cTxLock = queueLOCKED_UNMODIFIED; \ + } \ + } \ + taskEXIT_CRITICAL() +/*-----------------------------------------------------------*/ + +BaseType_t xQueueGenericReset( QueueHandle_t xQueue, + BaseType_t xNewQueue ) +{ + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + + taskENTER_CRITICAL(); + { + pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ + pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U; + pxQueue->pcWriteTo = pxQueue->pcHead; + pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ + pxQueue->cRxLock = queueUNLOCKED; + pxQueue->cTxLock = queueUNLOCKED; + + if( xNewQueue == pdFALSE ) + { + /* If there are tasks blocked waiting to read from the queue, then + * the tasks will remain blocked as after this function exits the queue + * will still be empty. If there are tasks blocked waiting to write to + * the queue, then one should be unblocked as after this function exits + * it will be possible to write to it. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* Ensure the event queues start in the correct state. */ + vListInitialise( &( pxQueue->xTasksWaitingToSend ) ); + vListInitialise( &( pxQueue->xTasksWaitingToReceive ) ); + } + } + taskEXIT_CRITICAL(); + + /* A value is returned for calling semantic consistency with previous + * versions. */ + return pdPASS; +} +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + uint8_t * pucQueueStorage, + StaticQueue_t * pxStaticQueue, + const uint8_t ucQueueType ) + { + Queue_t * pxNewQueue; + + configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); + + /* The StaticQueue_t structure and the queue storage area must be + * supplied. */ + configASSERT( pxStaticQueue != NULL ); + + /* A queue storage area should be provided if the item size is not 0, and + * should not be provided if the item size is 0. */ + configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) ); + configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) ); + + #if ( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + * variable of type StaticQueue_t or StaticSemaphore_t equals the size of + * the real queue and semaphore structures. */ + volatile size_t xSize = sizeof( StaticQueue_t ); + configASSERT( xSize == sizeof( Queue_t ) ); + ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ + } + #endif /* configASSERT_DEFINED */ + + /* The address of a statically allocated queue was passed in, use it. + * The address of a statically allocated storage area was also passed in + * but is already set. */ + pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ + + if( pxNewQueue != NULL ) + { + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + /* Queues can be allocated wither statically or dynamically, so + * note this queue was allocated statically in case the queue is + * later deleted. */ + pxNewQueue->ucStaticallyAllocated = pdTRUE; + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + + prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); + } + else + { + traceQUEUE_CREATE_FAILED( ucQueueType ); + mtCOVERAGE_TEST_MARKER(); + } + + return pxNewQueue; + } + +#endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + const uint8_t ucQueueType ) + { + Queue_t * pxNewQueue; + size_t xQueueSizeInBytes; + uint8_t * pucQueueStorage; + + configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); + + /* Allocate enough space to hold the maximum number of items that + * can be in the queue at any time. It is valid for uxItemSize to be + * zero in the case the queue is used as a semaphore. */ + xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + + /* Check for multiplication overflow. */ + configASSERT( ( uxItemSize == 0 ) || ( uxQueueLength == ( xQueueSizeInBytes / uxItemSize ) ) ); + + /* Check for addition overflow. */ + configASSERT( ( sizeof( Queue_t ) + xQueueSizeInBytes ) > xQueueSizeInBytes ); + + /* Allocate the queue and storage area. Justification for MISRA + * deviation as follows: pvPortMalloc() always ensures returned memory + * blocks are aligned per the requirements of the MCU stack. In this case + * pvPortMalloc() must return a pointer that is guaranteed to meet the + * alignment requirements of the Queue_t structure - which in this case + * is an int8_t *. Therefore, whenever the stack alignment requirements + * are greater than or equal to the pointer to char requirements the cast + * is safe. In other cases alignment requirements are not strict (one or + * two bytes). */ + pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */ + + if( pxNewQueue != NULL ) + { + /* Jump past the queue structure to find the location of the queue + * storage area. */ + pucQueueStorage = ( uint8_t * ) pxNewQueue; + pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + /* Queues can be created either statically or dynamically, so + * note this task was created dynamically in case it is later + * deleted. */ + pxNewQueue->ucStaticallyAllocated = pdFALSE; + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + + prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); + } + else + { + traceQUEUE_CREATE_FAILED( ucQueueType ); + mtCOVERAGE_TEST_MARKER(); + } + + return pxNewQueue; + } + +#endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, + const UBaseType_t uxItemSize, + uint8_t * pucQueueStorage, + const uint8_t ucQueueType, + Queue_t * pxNewQueue ) +{ + /* Remove compiler warnings about unused parameters should + * configUSE_TRACE_FACILITY not be set to 1. */ + ( void ) ucQueueType; + + if( uxItemSize == ( UBaseType_t ) 0 ) + { + /* No RAM was allocated for the queue storage area, but PC head cannot + * be set to NULL because NULL is used as a key to say the queue is used as + * a mutex. Therefore just set pcHead to point to the queue as a benign + * value that is known to be within the memory map. */ + pxNewQueue->pcHead = ( int8_t * ) pxNewQueue; + } + else + { + /* Set the head to the start of the queue storage area. */ + pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage; + } + + /* Initialise the queue members as described where the queue type is + * defined. */ + pxNewQueue->uxLength = uxQueueLength; + pxNewQueue->uxItemSize = uxItemSize; + ( void ) xQueueGenericReset( pxNewQueue, pdTRUE ); + + #if ( configUSE_TRACE_FACILITY == 1 ) + { + pxNewQueue->ucQueueType = ucQueueType; + } + #endif /* configUSE_TRACE_FACILITY */ + + #if ( configUSE_QUEUE_SETS == 1 ) + { + pxNewQueue->pxQueueSetContainer = NULL; + } + #endif /* configUSE_QUEUE_SETS */ + + traceQUEUE_CREATE( pxNewQueue ); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_MUTEXES == 1 ) + + static void prvInitialiseMutex( Queue_t * pxNewQueue ) + { + if( pxNewQueue != NULL ) + { + /* The queue create function will set all the queue structure members + * correctly for a generic queue, but this function is creating a + * mutex. Overwrite those members that need to be set differently - + * in particular the information required for priority inheritance. */ + pxNewQueue->u.xSemaphore.xMutexHolder = NULL; + pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX; + + /* In case this is a recursive mutex. */ + pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0; + + traceCREATE_MUTEX( pxNewQueue ); + + /* Start with the semaphore in the expected state. */ + ( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK ); + } + else + { + traceCREATE_MUTEX_FAILED(); + } + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + + QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) + { + QueueHandle_t xNewQueue; + const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; + + xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType ); + prvInitialiseMutex( ( Queue_t * ) xNewQueue ); + + return xNewQueue; + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + + QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, + StaticQueue_t * pxStaticQueue ) + { + QueueHandle_t xNewQueue; + const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0; + + /* Prevent compiler warnings about unused parameters if + * configUSE_TRACE_FACILITY does not equal 1. */ + ( void ) ucQueueType; + + xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType ); + prvInitialiseMutex( ( Queue_t * ) xNewQueue ); + + return xNewQueue; + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + + TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) + { + TaskHandle_t pxReturn; + Queue_t * const pxSemaphore = ( Queue_t * ) xSemaphore; + + /* This function is called by xSemaphoreGetMutexHolder(), and should not + * be called directly. Note: This is a good way of determining if the + * calling task is the mutex holder, but not a good way of determining the + * identity of the mutex holder, as the holder may change between the + * following critical section exiting and the function returning. */ + taskENTER_CRITICAL(); + { + if( pxSemaphore->uxQueueType == queueQUEUE_IS_MUTEX ) + { + pxReturn = pxSemaphore->u.xSemaphore.xMutexHolder; + } + else + { + pxReturn = NULL; + } + } + taskEXIT_CRITICAL(); + + return pxReturn; + } /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */ + +#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) + + TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) + { + TaskHandle_t pxReturn; + + configASSERT( xSemaphore ); + + /* Mutexes cannot be used in interrupt service routines, so the mutex + * holder should not change in an ISR, and therefore a critical section is + * not required here. */ + if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX ) + { + pxReturn = ( ( Queue_t * ) xSemaphore )->u.xSemaphore.xMutexHolder; + } + else + { + pxReturn = NULL; + } + + return pxReturn; + } /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */ + +#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) + { + BaseType_t xReturn; + Queue_t * const pxMutex = ( Queue_t * ) xMutex; + + configASSERT( pxMutex ); + + /* If this is the task that holds the mutex then xMutexHolder will not + * change outside of this task. If this task does not hold the mutex then + * pxMutexHolder can never coincidentally equal the tasks handle, and as + * this is the only condition we are interested in it does not matter if + * pxMutexHolder is accessed simultaneously by another task. Therefore no + * mutual exclusion is required to test the pxMutexHolder variable. */ + if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() ) + { + traceGIVE_MUTEX_RECURSIVE( pxMutex ); + + /* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to + * the task handle, therefore no underflow check is required. Also, + * uxRecursiveCallCount is only modified by the mutex holder, and as + * there can only be one, no mutual exclusion is required to modify the + * uxRecursiveCallCount member. */ + ( pxMutex->u.xSemaphore.uxRecursiveCallCount )--; + + /* Has the recursive call count unwound to 0? */ + if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 ) + { + /* Return the mutex. This will automatically unblock any other + * task that might be waiting to access the mutex. */ + ( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xReturn = pdPASS; + } + else + { + /* The mutex cannot be given because the calling task is not the + * holder. */ + xReturn = pdFAIL; + + traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex ); + } + + return xReturn; + } + +#endif /* configUSE_RECURSIVE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_RECURSIVE_MUTEXES == 1 ) + + BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, + TickType_t xTicksToWait ) + { + BaseType_t xReturn; + Queue_t * const pxMutex = ( Queue_t * ) xMutex; + + configASSERT( pxMutex ); + + /* Comments regarding mutual exclusion as per those within + * xQueueGiveMutexRecursive(). */ + + traceTAKE_MUTEX_RECURSIVE( pxMutex ); + + if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() ) + { + ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++; + xReturn = pdPASS; + } + else + { + xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait ); + + /* pdPASS will only be returned if the mutex was successfully + * obtained. The calling task may have entered the Blocked state + * before reaching here. */ + if( xReturn != pdFAIL ) + { + ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++; + } + else + { + traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex ); + } + } + + return xReturn; + } + +#endif /* configUSE_RECURSIVE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + + QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, + const UBaseType_t uxInitialCount, + StaticQueue_t * pxStaticQueue ) + { + QueueHandle_t xHandle; + + configASSERT( uxMaxCount != 0 ); + configASSERT( uxInitialCount <= uxMaxCount ); + + xHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE ); + + if( xHandle != NULL ) + { + ( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount; + + traceCREATE_COUNTING_SEMAPHORE(); + } + else + { + traceCREATE_COUNTING_SEMAPHORE_FAILED(); + } + + return xHandle; + } + +#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + + QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, + const UBaseType_t uxInitialCount ) + { + QueueHandle_t xHandle; + + configASSERT( uxMaxCount != 0 ); + configASSERT( uxInitialCount <= uxMaxCount ); + + xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE ); + + if( xHandle != NULL ) + { + ( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount; + + traceCREATE_COUNTING_SEMAPHORE(); + } + else + { + traceCREATE_COUNTING_SEMAPHORE_FAILED(); + } + + return xHandle; + } + +#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ +/*-----------------------------------------------------------*/ + +BaseType_t xQueueGenericSend( QueueHandle_t xQueue, + const void * const pvItemToQueue, + TickType_t xTicksToWait, + const BaseType_t xCopyPosition ) +{ + BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired; + TimeOut_t xTimeOut; + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); + configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + /*lint -save -e904 This function relaxes the coding standard somewhat to + * allow return statements within the function itself. This is done in the + * interest of execution time efficiency. */ + for( ; ; ) + { + taskENTER_CRITICAL(); + { + /* Is there room on the queue now? The running task must be the + * highest priority task wanting to access the queue. If the head item + * in the queue is to be overwritten then it does not matter if the + * queue is full. */ + if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) + { + traceQUEUE_SEND( pxQueue ); + + #if ( configUSE_QUEUE_SETS == 1 ) + { + const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting; + + xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); + + if( pxQueue->pxQueueSetContainer != NULL ) + { + if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) ) + { + /* Do not notify the queue set as an existing item + * was overwritten in the queue so the number of items + * in the queue has not changed. */ + mtCOVERAGE_TEST_MARKER(); + } + else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE ) + { + /* The queue is a member of a queue set, and posting + * to the queue set caused a higher priority task to + * unblock. A context switch is required. */ + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* If there was a task waiting for data to arrive on the + * queue then unblock it now. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The unblocked task has a priority higher than + * our own so yield immediately. Yes it is ok to + * do this from within the critical section - the + * kernel takes care of that. */ + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else if( xYieldRequired != pdFALSE ) + { + /* This path is a special case that will only get + * executed if the task was holding multiple mutexes + * and the mutexes were given back in an order that is + * different to that in which they were taken. */ + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + #else /* configUSE_QUEUE_SETS */ + { + xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); + + /* If there was a task waiting for data to arrive on the + * queue then unblock it now. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The unblocked task has a priority higher than + * our own so yield immediately. Yes it is ok to do + * this from within the critical section - the kernel + * takes care of that. */ + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else if( xYieldRequired != pdFALSE ) + { + /* This path is a special case that will only get + * executed if the task was holding multiple mutexes and + * the mutexes were given back in an order that is + * different to that in which they were taken. */ + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_QUEUE_SETS */ + + taskEXIT_CRITICAL(); + return pdPASS; + } + else + { + if( xTicksToWait == ( TickType_t ) 0 ) + { + /* The queue was full and no block time is specified (or + * the block time has expired) so leave now. */ + taskEXIT_CRITICAL(); + + /* Return to the original privilege level before exiting + * the function. */ + traceQUEUE_SEND_FAILED( pxQueue ); + return errQUEUE_FULL; + } + else if( xEntryTimeSet == pdFALSE ) + { + /* The queue was full and a block time was specified so + * configure the timeout structure. */ + vTaskInternalSetTimeOutState( &xTimeOut ); + xEntryTimeSet = pdTRUE; + } + else + { + /* Entry time was already set. */ + mtCOVERAGE_TEST_MARKER(); + } + } + } + taskEXIT_CRITICAL(); + + /* Interrupts and other tasks can send to and receive from the queue + * now the critical section has been exited. */ + + vTaskSuspendAll(); + prvLockQueue( pxQueue ); + + /* Update the timeout state to see if it has expired yet. */ + if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) + { + if( prvIsQueueFull( pxQueue ) != pdFALSE ) + { + traceBLOCKING_ON_QUEUE_SEND( pxQueue ); + vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); + + /* Unlocking the queue means queue events can effect the + * event list. It is possible that interrupts occurring now + * remove this task from the event list again - but as the + * scheduler is suspended the task will go onto the pending + * ready last instead of the actual ready list. */ + prvUnlockQueue( pxQueue ); + + /* Resuming the scheduler will move tasks from the pending + * ready list into the ready list - so it is feasible that this + * task is already in a ready list before it yields - in which + * case the yield will not cause a context switch unless there + * is also a higher priority task in the pending ready list. */ + if( xTaskResumeAll() == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + } + else + { + /* Try again. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + } + } + else + { + /* The timeout has expired. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + + traceQUEUE_SEND_FAILED( pxQueue ); + return errQUEUE_FULL; + } + } /*lint -restore */ +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, + const void * const pvItemToQueue, + BaseType_t * const pxHigherPriorityTaskWoken, + const BaseType_t xCopyPosition ) +{ + BaseType_t xReturn; + UBaseType_t uxSavedInterruptStatus; + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); + configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); + + /* RTOS ports that support interrupt nesting have the concept of a maximum + * system call (or maximum API call) interrupt priority. Interrupts that are + * above the maximum system call priority are kept permanently enabled, even + * when the RTOS kernel is in a critical section, but cannot make any calls to + * FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h + * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has been + * assigned a priority above the configured maximum system call priority. + * Only FreeRTOS functions that end in FromISR can be called from interrupts + * that have been assigned a priority at or (logically) below the maximum + * system call interrupt priority. FreeRTOS maintains a separate interrupt + * safe API to ensure interrupt entry is as fast and as simple as possible. + * More information (albeit Cortex-M specific) is provided on the following + * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + /* Similar to xQueueGenericSend, except without blocking if there is no room + * in the queue. Also don't directly wake a task that was blocked on a queue + * read, instead return a flag to say whether a context switch is required or + * not (i.e. has a task with a higher priority than us been woken by this + * post). */ + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) + { + const int16_t cTxLock = pxQueue->cTxLock; + const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting; + + traceQUEUE_SEND_FROM_ISR( pxQueue ); + + /* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a + * semaphore or mutex. That means prvCopyDataToQueue() cannot result + * in a task disinheriting a priority and prvCopyDataToQueue() can be + * called here even though the disinherit function does not check if + * the scheduler is suspended before accessing the ready lists. */ + ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); + + /* The event list is not altered if the queue is locked. This will + * be done when the queue is unlocked later. */ + if( cTxLock == queueUNLOCKED ) + { + #if ( configUSE_QUEUE_SETS == 1 ) + { + if( pxQueue->pxQueueSetContainer != NULL ) + { + if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) ) + { + /* Do not notify the queue set as an existing item + * was overwritten in the queue so the number of items + * in the queue has not changed. */ + mtCOVERAGE_TEST_MARKER(); + } + else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE ) + { + /* The queue is a member of a queue set, and posting + * to the queue set caused a higher priority task to + * unblock. A context switch is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority so + * record that a context switch is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + #else /* configUSE_QUEUE_SETS */ + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority so record that a + * context switch is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Not used in this path. */ + ( void ) uxPreviousMessagesWaiting; + } + #endif /* configUSE_QUEUE_SETS */ + } + else + { + /* Increment the lock count so the task that unlocks the queue + * knows that data was posted while it was locked. */ + configASSERT( cTxLock != queueINT16_MAX ); + + pxQueue->cTxLock = ( int16_t ) ( cTxLock + 1 ); + } + + xReturn = pdPASS; + } + else + { + traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ); + xReturn = errQUEUE_FULL; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, + BaseType_t * const pxHigherPriorityTaskWoken ) +{ + BaseType_t xReturn; + UBaseType_t uxSavedInterruptStatus; + Queue_t * const pxQueue = xQueue; + + /* Similar to xQueueGenericSendFromISR() but used with semaphores where the + * item size is 0. Don't directly wake a task that was blocked on a queue + * read, instead return a flag to say whether a context switch is required or + * not (i.e. has a task with a higher priority than us been woken by this + * post). */ + + configASSERT( pxQueue ); + + /* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR() + * if the item size is not 0. */ + configASSERT( pxQueue->uxItemSize == 0 ); + + /* Normally a mutex would not be given from an interrupt, especially if + * there is a mutex holder, as priority inheritance makes no sense for an + * interrupts, only tasks. */ + configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) ); + + /* RTOS ports that support interrupt nesting have the concept of a maximum + * system call (or maximum API call) interrupt priority. Interrupts that are + * above the maximum system call priority are kept permanently enabled, even + * when the RTOS kernel is in a critical section, but cannot make any calls to + * FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h + * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has been + * assigned a priority above the configured maximum system call priority. + * Only FreeRTOS functions that end in FromISR can be called from interrupts + * that have been assigned a priority at or (logically) below the maximum + * system call interrupt priority. FreeRTOS maintains a separate interrupt + * safe API to ensure interrupt entry is as fast and as simple as possible. + * More information (albeit Cortex-M specific) is provided on the following + * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; + + /* When the queue is used to implement a semaphore no data is ever + * moved through the queue but it is still valid to see if the queue 'has + * space'. */ + if( uxMessagesWaiting < pxQueue->uxLength ) + { + const int16_t cTxLock = pxQueue->cTxLock; + + traceQUEUE_SEND_FROM_ISR( pxQueue ); + + /* A task can only have an inherited priority if it is a mutex + * holder - and if there is a mutex holder then the mutex cannot be + * given from an ISR. As this is the ISR version of the function it + * can be assumed there is no mutex holder and no need to determine if + * priority disinheritance is needed. Simply increase the count of + * messages (semaphores) available. */ + pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; + + /* The event list is not altered if the queue is locked. This will + * be done when the queue is unlocked later. */ + if( cTxLock == queueUNLOCKED ) + { + #if ( configUSE_QUEUE_SETS == 1 ) + { + if( pxQueue->pxQueueSetContainer != NULL ) + { + if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE ) + { + /* The semaphore is a member of a queue set, and + * posting to the queue set caused a higher priority + * task to unblock. A context switch is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority so + * record that a context switch is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + #else /* configUSE_QUEUE_SETS */ + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority so record that a + * context switch is required. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_QUEUE_SETS */ + } + else + { + /* Increment the lock count so the task that unlocks the queue + * knows that data was posted while it was locked. */ + configASSERT( cTxLock != queueINT16_MAX ); + + pxQueue->cTxLock = ( int16_t ) ( cTxLock + 1 ); + } + + xReturn = pdPASS; + } + else + { + traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ); + xReturn = errQUEUE_FULL; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueReceive( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) +{ + BaseType_t xEntryTimeSet = pdFALSE; + TimeOut_t xTimeOut; + Queue_t * const pxQueue = xQueue; + + /* Check the pointer is not NULL. */ + configASSERT( ( pxQueue ) ); + + /* The buffer into which data is received can only be NULL if the data size + * is zero (so no data is copied into the buffer). */ + configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) ); + + /* Cannot block if the scheduler is suspended. */ + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + /*lint -save -e904 This function relaxes the coding standard somewhat to + * allow return statements within the function itself. This is done in the + * interest of execution time efficiency. */ + for( ; ; ) + { + taskENTER_CRITICAL(); + { + const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; + + /* Is there data in the queue now? To be running the calling task + * must be the highest priority task wanting to access the queue. */ + if( uxMessagesWaiting > ( UBaseType_t ) 0 ) + { + /* Data available, remove one item. */ + prvCopyDataFromQueue( pxQueue, pvBuffer ); + traceQUEUE_RECEIVE( pxQueue ); + pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; + + /* There is now space in the queue, were any tasks waiting to + * post to the queue? If so, unblock the highest priority waiting + * task. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + taskEXIT_CRITICAL(); + return pdPASS; + } + else + { + if( xTicksToWait == ( TickType_t ) 0 ) + { + /* The queue was empty and no block time is specified (or + * the block time has expired) so leave now. */ + taskEXIT_CRITICAL(); + traceQUEUE_RECEIVE_FAILED( pxQueue ); + return errQUEUE_EMPTY; + } + else if( xEntryTimeSet == pdFALSE ) + { + /* The queue was empty and a block time was specified so + * configure the timeout structure. */ + vTaskInternalSetTimeOutState( &xTimeOut ); + xEntryTimeSet = pdTRUE; + } + else + { + /* Entry time was already set. */ + mtCOVERAGE_TEST_MARKER(); + } + } + } + taskEXIT_CRITICAL(); + + /* Interrupts and other tasks can send to and receive from the queue + * now the critical section has been exited. */ + + vTaskSuspendAll(); + prvLockQueue( pxQueue ); + + /* Update the timeout state to see if it has expired yet. */ + if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) + { + /* The timeout has not expired. If the queue is still empty place + * the task on the list of tasks waiting to receive from the queue. */ + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + { + traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); + vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); + prvUnlockQueue( pxQueue ); + + if( xTaskResumeAll() == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* The queue contains data again. Loop back to try and read the + * data. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + } + } + else + { + /* Timed out. If there is no data in the queue exit, otherwise loop + * back and attempt to read the data. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + { + traceQUEUE_RECEIVE_FAILED( pxQueue ); + return errQUEUE_EMPTY; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } /*lint -restore */ +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, + TickType_t xTicksToWait ) +{ + BaseType_t xEntryTimeSet = pdFALSE; + TimeOut_t xTimeOut; + Queue_t * const pxQueue = xQueue; + + #if ( configUSE_MUTEXES == 1 ) + BaseType_t xInheritanceOccurred = pdFALSE; + #endif + + /* Check the queue pointer is not NULL. */ + configASSERT( ( pxQueue ) ); + + /* Check this really is a semaphore, in which case the item size will be + * 0. */ + configASSERT( pxQueue->uxItemSize == 0 ); + + /* Cannot block if the scheduler is suspended. */ + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + /*lint -save -e904 This function relaxes the coding standard somewhat to allow return + * statements within the function itself. This is done in the interest + * of execution time efficiency. */ + for( ; ; ) + { + taskENTER_CRITICAL(); + { + /* Semaphores are queues with an item size of 0, and where the + * number of messages in the queue is the semaphore's count value. */ + const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting; + + /* Is there data in the queue now? To be running the calling task + * must be the highest priority task wanting to access the queue. */ + if( uxSemaphoreCount > ( UBaseType_t ) 0 ) + { + traceQUEUE_RECEIVE( pxQueue ); + + /* Semaphores are queues with a data size of zero and where the + * messages waiting is the semaphore's count. Reduce the count. */ + pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1; + + #if ( configUSE_MUTEXES == 1 ) + { + if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) + { + /* Record the information required to implement + * priority inheritance should it become necessary. */ + pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_MUTEXES */ + + /* Check to see if other tasks are blocked waiting to give the + * semaphore, and if so, unblock the highest priority such task. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + taskEXIT_CRITICAL(); + return pdPASS; + } + else + { + if( xTicksToWait == ( TickType_t ) 0 ) + { + /* For inheritance to have occurred there must have been an + * initial timeout, and an adjusted timeout cannot become 0, as + * if it were 0 the function would have exited. */ + #if ( configUSE_MUTEXES == 1 ) + { + configASSERT( xInheritanceOccurred == pdFALSE ); + } + #endif /* configUSE_MUTEXES */ + + /* The semaphore count was 0 and no block time is specified + * (or the block time has expired) so exit now. */ + taskEXIT_CRITICAL(); + traceQUEUE_RECEIVE_FAILED( pxQueue ); + return errQUEUE_EMPTY; + } + else if( xEntryTimeSet == pdFALSE ) + { + /* The semaphore count was 0 and a block time was specified + * so configure the timeout structure ready to block. */ + vTaskInternalSetTimeOutState( &xTimeOut ); + xEntryTimeSet = pdTRUE; + } + else + { + /* Entry time was already set. */ + mtCOVERAGE_TEST_MARKER(); + } + } + } + taskEXIT_CRITICAL(); + + /* Interrupts and other tasks can give to and take from the semaphore + * now the critical section has been exited. */ + + vTaskSuspendAll(); + prvLockQueue( pxQueue ); + + /* Update the timeout state to see if it has expired yet. */ + if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) + { + /* A block time is specified and not expired. If the semaphore + * count is 0 then enter the Blocked state to wait for a semaphore to + * become available. As semaphores are implemented with queues the + * queue being empty is equivalent to the semaphore count being 0. */ + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + { + traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); + + #if ( configUSE_MUTEXES == 1 ) + { + if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) + { + taskENTER_CRITICAL(); + { + xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder ); + } + taskEXIT_CRITICAL(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* if ( configUSE_MUTEXES == 1 ) */ + + vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); + prvUnlockQueue( pxQueue ); + + if( xTaskResumeAll() == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* There was no timeout and the semaphore count was not 0, so + * attempt to take the semaphore again. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + } + } + else + { + /* Timed out. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + + /* If the semaphore count is 0 exit now as the timeout has + * expired. Otherwise return to attempt to take the semaphore that is + * known to be available. As semaphores are implemented by queues the + * queue being empty is equivalent to the semaphore count being 0. */ + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + { + #if ( configUSE_MUTEXES == 1 ) + { + /* xInheritanceOccurred could only have be set if + * pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to + * test the mutex type again to check it is actually a mutex. */ + if( xInheritanceOccurred != pdFALSE ) + { + taskENTER_CRITICAL(); + { + UBaseType_t uxHighestWaitingPriority; + + /* This task blocking on the mutex caused another + * task to inherit this task's priority. Now this task + * has timed out the priority should be disinherited + * again, but only as low as the next highest priority + * task that is waiting for the same mutex. */ + uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue ); + vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority ); + } + taskEXIT_CRITICAL(); + } + } + #endif /* configUSE_MUTEXES */ + + traceQUEUE_RECEIVE_FAILED( pxQueue ); + return errQUEUE_EMPTY; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } /*lint -restore */ +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueuePeek( QueueHandle_t xQueue, + void * const pvBuffer, + TickType_t xTicksToWait ) +{ + BaseType_t xEntryTimeSet = pdFALSE; + TimeOut_t xTimeOut; + int8_t * pcOriginalReadPosition; + Queue_t * const pxQueue = xQueue; + + /* Check the pointer is not NULL. */ + configASSERT( ( pxQueue ) ); + + /* The buffer into which data is received can only be NULL if the data size + * is zero (so no data is copied into the buffer. */ + configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) ); + + /* Cannot block if the scheduler is suspended. */ + #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) + { + configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); + } + #endif + + /*lint -save -e904 This function relaxes the coding standard somewhat to + * allow return statements within the function itself. This is done in the + * interest of execution time efficiency. */ + for( ; ; ) + { + taskENTER_CRITICAL(); + { + const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; + + /* Is there data in the queue now? To be running the calling task + * must be the highest priority task wanting to access the queue. */ + if( uxMessagesWaiting > ( UBaseType_t ) 0 ) + { + /* Remember the read position so it can be reset after the data + * is read from the queue as this function is only peeking the + * data, not removing it. */ + pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom; + + prvCopyDataFromQueue( pxQueue, pvBuffer ); + traceQUEUE_PEEK( pxQueue ); + + /* The data is not being removed, so reset the read pointer. */ + pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition; + + /* The data is being left in the queue, so see if there are + * any other tasks waiting for the data. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority than this task. */ + queueYIELD_IF_USING_PREEMPTION(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + taskEXIT_CRITICAL(); + return pdPASS; + } + else + { + if( xTicksToWait == ( TickType_t ) 0 ) + { + /* The queue was empty and no block time is specified (or + * the block time has expired) so leave now. */ + taskEXIT_CRITICAL(); + traceQUEUE_PEEK_FAILED( pxQueue ); + return errQUEUE_EMPTY; + } + else if( xEntryTimeSet == pdFALSE ) + { + /* The queue was empty and a block time was specified so + * configure the timeout structure ready to enter the blocked + * state. */ + vTaskInternalSetTimeOutState( &xTimeOut ); + xEntryTimeSet = pdTRUE; + } + else + { + /* Entry time was already set. */ + mtCOVERAGE_TEST_MARKER(); + } + } + } + taskEXIT_CRITICAL(); + + /* Interrupts and other tasks can send to and receive from the queue + * now the critical section has been exited. */ + + vTaskSuspendAll(); + prvLockQueue( pxQueue ); + + /* Update the timeout state to see if it has expired yet. */ + if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) + { + /* Timeout has not expired yet, check to see if there is data in the + * queue now, and if not enter the Blocked state to wait for data. */ + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + { + traceBLOCKING_ON_QUEUE_PEEK( pxQueue ); + vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); + prvUnlockQueue( pxQueue ); + + if( xTaskResumeAll() == pdFALSE ) + { + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* There is data in the queue now, so don't enter the blocked + * state, instead return to try and obtain the data. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + } + } + else + { + /* The timeout has expired. If there is still no data in the queue + * exit, otherwise go back and try to read the data again. */ + prvUnlockQueue( pxQueue ); + ( void ) xTaskResumeAll(); + + if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) + { + traceQUEUE_PEEK_FAILED( pxQueue ); + return errQUEUE_EMPTY; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } /*lint -restore */ +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, + void * const pvBuffer, + BaseType_t * const pxHigherPriorityTaskWoken ) +{ + BaseType_t xReturn; + UBaseType_t uxSavedInterruptStatus; + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); + + /* RTOS ports that support interrupt nesting have the concept of a maximum + * system call (or maximum API call) interrupt priority. Interrupts that are + * above the maximum system call priority are kept permanently enabled, even + * when the RTOS kernel is in a critical section, but cannot make any calls to + * FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h + * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has been + * assigned a priority above the configured maximum system call priority. + * Only FreeRTOS functions that end in FromISR can be called from interrupts + * that have been assigned a priority at or (logically) below the maximum + * system call interrupt priority. FreeRTOS maintains a separate interrupt + * safe API to ensure interrupt entry is as fast and as simple as possible. + * More information (albeit Cortex-M specific) is provided on the following + * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; + + /* Cannot block in an ISR, so check there is data available. */ + if( uxMessagesWaiting > ( UBaseType_t ) 0 ) + { + const int16_t cRxLock = pxQueue->cRxLock; + + traceQUEUE_RECEIVE_FROM_ISR( pxQueue ); + + prvCopyDataFromQueue( pxQueue, pvBuffer ); + pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; + + /* If the queue is locked the event list will not be modified. + * Instead update the lock count so the task that unlocks the queue + * will know that an ISR has removed data while the queue was + * locked. */ + if( cRxLock == queueUNLOCKED ) + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + /* The task waiting has a higher priority than us so + * force a context switch. */ + if( pxHigherPriorityTaskWoken != NULL ) + { + *pxHigherPriorityTaskWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* Increment the lock count so the task that unlocks the queue + * knows that data was removed while it was locked. */ + configASSERT( cRxLock != queueINT16_MAX ); + + pxQueue->cRxLock = ( int16_t ) ( cRxLock + 1 ); + } + + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, + void * const pvBuffer ) +{ + BaseType_t xReturn; + UBaseType_t uxSavedInterruptStatus; + int8_t * pcOriginalReadPosition; + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); + configASSERT( pxQueue->uxItemSize != 0 ); /* Can't peek a semaphore. */ + + /* RTOS ports that support interrupt nesting have the concept of a maximum + * system call (or maximum API call) interrupt priority. Interrupts that are + * above the maximum system call priority are kept permanently enabled, even + * when the RTOS kernel is in a critical section, but cannot make any calls to + * FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h + * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has been + * assigned a priority above the configured maximum system call priority. + * Only FreeRTOS functions that end in FromISR can be called from interrupts + * that have been assigned a priority at or (logically) below the maximum + * system call interrupt priority. FreeRTOS maintains a separate interrupt + * safe API to ensure interrupt entry is as fast and as simple as possible. + * More information (albeit Cortex-M specific) is provided on the following + * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* Cannot block in an ISR, so check there is data available. */ + if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 ) + { + traceQUEUE_PEEK_FROM_ISR( pxQueue ); + + /* Remember the read position so it can be reset as nothing is + * actually being removed from the queue. */ + pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom; + prvCopyDataFromQueue( pxQueue, pvBuffer ); + pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition; + + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue ); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) +{ + UBaseType_t uxReturn; + + configASSERT( xQueue ); + + taskENTER_CRITICAL(); + { + uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting; + } + taskEXIT_CRITICAL(); + + return uxReturn; +} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */ +/*-----------------------------------------------------------*/ + +UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) +{ + UBaseType_t uxReturn; + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + + taskENTER_CRITICAL(); + { + uxReturn = pxQueue->uxLength - pxQueue->uxMessagesWaiting; + } + taskEXIT_CRITICAL(); + + return uxReturn; +} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */ +/*-----------------------------------------------------------*/ + +UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) +{ + UBaseType_t uxReturn; + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + uxReturn = pxQueue->uxMessagesWaiting; + + return uxReturn; +} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */ +/*-----------------------------------------------------------*/ + +void vQueueDelete( QueueHandle_t xQueue ) +{ + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + traceQUEUE_DELETE( pxQueue ); + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + { + vQueueUnregisterQueue( pxQueue ); + } + #endif + + #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) ) + { + /* The queue can only have been allocated dynamically - free it + * again. */ + vPortFree( pxQueue ); + } + #elif ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) + { + /* The queue could have been allocated statically or dynamically, so + * check before attempting to free the memory. */ + if( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdFALSE ) + { + vPortFree( pxQueue ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #else /* if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) ) */ + { + /* The queue must have been statically allocated, so is not going to be + * deleted. Avoid compiler warnings about the unused parameter. */ + ( void ) pxQueue; + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) + { + return ( ( Queue_t * ) xQueue )->uxQueueNumber; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + void vQueueSetQueueNumber( QueueHandle_t xQueue, + UBaseType_t uxQueueNumber ) + { + ( ( Queue_t * ) xQueue )->uxQueueNumber = uxQueueNumber; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) + { + return ( ( Queue_t * ) xQueue )->ucQueueType; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_MUTEXES == 1 ) + + static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) + { + UBaseType_t uxHighestPriorityOfWaitingTasks; + + /* If a task waiting for a mutex causes the mutex holder to inherit a + * priority, but the waiting task times out, then the holder should + * disinherit the priority - but only down to the highest priority of any + * other tasks that are waiting for the same mutex. For this purpose, + * return the priority of the highest priority task that is waiting for the + * mutex. */ + if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U ) + { + uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) ); + } + else + { + uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY; + } + + return uxHighestPriorityOfWaitingTasks; + } + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, + const void * pvItemToQueue, + const BaseType_t xPosition ) +{ + BaseType_t xReturn = pdFALSE; + UBaseType_t uxMessagesWaiting; + + /* This function is called from a critical section. */ + + uxMessagesWaiting = pxQueue->uxMessagesWaiting; + + if( pxQueue->uxItemSize == ( UBaseType_t ) 0 ) + { + #if ( configUSE_MUTEXES == 1 ) + { + if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) + { + /* The mutex is no longer being held. */ + xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder ); + pxQueue->u.xSemaphore.xMutexHolder = NULL; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_MUTEXES */ + } + else if( xPosition == queueSEND_TO_BACK ) + { + ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ + pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ + + if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ + { + pxQueue->pcWriteTo = pxQueue->pcHead; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */ + pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize; + + if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ + { + pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xPosition == queueOVERWRITE ) + { + if( uxMessagesWaiting > ( UBaseType_t ) 0 ) + { + /* An item is not being added but overwritten, so subtract + * one from the recorded number of items in the queue so when + * one is added again below the number of recorded items remains + * correct. */ + --uxMessagesWaiting; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static void prvCopyDataFromQueue( Queue_t * const pxQueue, + void * const pvBuffer ) +{ + if( pxQueue->uxItemSize != ( UBaseType_t ) 0 ) + { + pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ + + if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */ + { + pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ + } +} +/*-----------------------------------------------------------*/ + +static void prvUnlockQueue( Queue_t * const pxQueue ) +{ + /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */ + + /* The lock counts contains the number of extra data items placed or + * removed from the queue while the queue was locked. When a queue is + * locked items can be added or removed, but the event lists cannot be + * updated. */ + taskENTER_CRITICAL(); + { + int16_t cTxLock = pxQueue->cTxLock; + + /* See if data was added to the queue while it was locked. */ + while( cTxLock > queueLOCKED_UNMODIFIED ) + { + /* Data was posted while the queue was locked. Are any tasks + * blocked waiting for data to become available? */ + #if ( configUSE_QUEUE_SETS == 1 ) + { + if( pxQueue->pxQueueSetContainer != NULL ) + { + if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE ) + { + /* The queue is a member of a queue set, and posting to + * the queue set caused a higher priority task to unblock. + * A context switch is required. */ + vTaskMissedYield(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* Tasks that are removed from the event list will get + * added to the pending ready list as the scheduler is still + * suspended. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority so record that a + * context switch is required. */ + vTaskMissedYield(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + break; + } + } + } + #else /* configUSE_QUEUE_SETS */ + { + /* Tasks that are removed from the event list will get added to + * the pending ready list as the scheduler is still suspended. */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority so record that + * a context switch is required. */ + vTaskMissedYield(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + break; + } + } + #endif /* configUSE_QUEUE_SETS */ + + --cTxLock; + } + + pxQueue->cTxLock = queueUNLOCKED; + } + taskEXIT_CRITICAL(); + + /* Do the same for the Rx lock. */ + taskENTER_CRITICAL(); + { + int16_t cRxLock = pxQueue->cRxLock; + + while( cRxLock > queueLOCKED_UNMODIFIED ) + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + vTaskMissedYield(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + --cRxLock; + } + else + { + break; + } + } + + pxQueue->cRxLock = queueUNLOCKED; + } + taskEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +static BaseType_t prvIsQueueEmpty( const Queue_t * pxQueue ) +{ + BaseType_t xReturn; + + taskENTER_CRITICAL(); + { + if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + } + taskEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) +{ + BaseType_t xReturn; + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + + if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; +} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ +/*-----------------------------------------------------------*/ + +static BaseType_t prvIsQueueFull( const Queue_t * pxQueue ) +{ + BaseType_t xReturn; + + taskENTER_CRITICAL(); + { + if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + } + taskEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) +{ + BaseType_t xReturn; + Queue_t * const pxQueue = xQueue; + + configASSERT( pxQueue ); + + if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; +} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_CO_ROUTINES == 1 ) + + BaseType_t xQueueCRSend( QueueHandle_t xQueue, + const void * pvItemToQueue, + TickType_t xTicksToWait ) + { + BaseType_t xReturn; + Queue_t * const pxQueue = xQueue; + + /* If the queue is already full we may have to block. A critical section + * is required to prevent an interrupt removing something from the queue + * between the check to see if the queue is full and blocking on the queue. */ + portDISABLE_INTERRUPTS(); + { + if( prvIsQueueFull( pxQueue ) != pdFALSE ) + { + /* The queue is full - do we want to block or just leave without + * posting? */ + if( xTicksToWait > ( TickType_t ) 0 ) + { + /* As this is called from a coroutine we cannot block directly, but + * return indicating that we need to block. */ + vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) ); + portENABLE_INTERRUPTS(); + return errQUEUE_BLOCKED; + } + else + { + portENABLE_INTERRUPTS(); + return errQUEUE_FULL; + } + } + } + portENABLE_INTERRUPTS(); + + portDISABLE_INTERRUPTS(); + { + if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) + { + /* There is room in the queue, copy the data into the queue. */ + prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK ); + xReturn = pdPASS; + + /* Were any co-routines waiting for data to become available? */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + /* In this instance the co-routine could be placed directly + * into the ready list as we are within a critical section. + * Instead the same pending ready list mechanism is used as if + * the event were caused from within an interrupt. */ + if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The co-routine waiting has a higher priority so record + * that a yield might be appropriate. */ + xReturn = errQUEUE_YIELD; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xReturn = errQUEUE_FULL; + } + } + portENABLE_INTERRUPTS(); + + return xReturn; + } + +#endif /* configUSE_CO_ROUTINES */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_CO_ROUTINES == 1 ) + + BaseType_t xQueueCRReceive( QueueHandle_t xQueue, + void * pvBuffer, + TickType_t xTicksToWait ) + { + BaseType_t xReturn; + Queue_t * const pxQueue = xQueue; + + /* If the queue is already empty we may have to block. A critical section + * is required to prevent an interrupt adding something to the queue + * between the check to see if the queue is empty and blocking on the queue. */ + portDISABLE_INTERRUPTS(); + { + if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) + { + /* There are no messages in the queue, do we want to block or just + * leave with nothing? */ + if( xTicksToWait > ( TickType_t ) 0 ) + { + /* As this is a co-routine we cannot block directly, but return + * indicating that we need to block. */ + vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) ); + portENABLE_INTERRUPTS(); + return errQUEUE_BLOCKED; + } + else + { + portENABLE_INTERRUPTS(); + return errQUEUE_FULL; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + portENABLE_INTERRUPTS(); + + portDISABLE_INTERRUPTS(); + { + if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 ) + { + /* Data is available from the queue. */ + pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; + + if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) + { + pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + --( pxQueue->uxMessagesWaiting ); + ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); + + xReturn = pdPASS; + + /* Were any co-routines waiting for space to become available? */ + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + { + /* In this instance the co-routine could be placed directly + * into the ready list as we are within a critical section. + * Instead the same pending ready list mechanism is used as if + * the event were caused from within an interrupt. */ + if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + xReturn = errQUEUE_YIELD; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xReturn = pdFAIL; + } + } + portENABLE_INTERRUPTS(); + + return xReturn; + } + +#endif /* configUSE_CO_ROUTINES */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_CO_ROUTINES == 1 ) + + BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, + const void * pvItemToQueue, + BaseType_t xCoRoutinePreviouslyWoken ) + { + Queue_t * const pxQueue = xQueue; + + /* Cannot block within an ISR so if there is no space on the queue then + * exit without doing anything. */ + if( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) + { + prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK ); + + /* We only want to wake one co-routine per ISR, so check that a + * co-routine has not already been woken. */ + if( xCoRoutinePreviouslyWoken == pdFALSE ) + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) + { + return pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xCoRoutinePreviouslyWoken; + } + +#endif /* configUSE_CO_ROUTINES */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_CO_ROUTINES == 1 ) + + BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, + void * pvBuffer, + BaseType_t * pxCoRoutineWoken ) + { + BaseType_t xReturn; + Queue_t * const pxQueue = xQueue; + + /* We cannot block from an ISR, so check there is data available. If + * not then just leave without doing anything. */ + if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 ) + { + /* Copy the data from the queue. */ + pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; + + if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) + { + pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + --( pxQueue->uxMessagesWaiting ); + ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize ); + + if( ( *pxCoRoutineWoken ) == pdFALSE ) + { + if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) + { + if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) + { + *pxCoRoutineWoken = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xReturn = pdPASS; + } + else + { + xReturn = pdFAIL; + } + + return xReturn; + } + +#endif /* configUSE_CO_ROUTINES */ +/*-----------------------------------------------------------*/ + +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void vQueueAddToRegistry( QueueHandle_t xQueue, + const char * pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + { + UBaseType_t ux; + + /* See if there is an empty space in the registry. A NULL name denotes + * a free slot. */ + for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) + { + if( xQueueRegistry[ ux ].pcQueueName == NULL ) + { + /* Store the information on this queue. */ + xQueueRegistry[ ux ].pcQueueName = pcQueueName; + xQueueRegistry[ ux ].xHandle = xQueue; + + traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName ); + break; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + +#endif /* configQUEUE_REGISTRY_SIZE */ +/*-----------------------------------------------------------*/ + +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + + const char * pcQueueGetName( QueueHandle_t xQueue ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + { + UBaseType_t ux; + const char * pcReturn = NULL; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + + /* Note there is nothing here to protect against another task adding or + * removing entries from the registry while it is being searched. */ + + for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) + { + if( xQueueRegistry[ ux ].xHandle == xQueue ) + { + pcReturn = xQueueRegistry[ ux ].pcQueueName; + break; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + return pcReturn; + } /*lint !e818 xQueue cannot be a pointer to const because it is a typedef. */ + +#endif /* configQUEUE_REGISTRY_SIZE */ +/*-----------------------------------------------------------*/ + +#if ( configQUEUE_REGISTRY_SIZE > 0 ) + + void vQueueUnregisterQueue( QueueHandle_t xQueue ) + { + UBaseType_t ux; + + /* See if the handle of the queue being unregistered in actually in the + * registry. */ + for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) + { + if( xQueueRegistry[ ux ].xHandle == xQueue ) + { + /* Set the name to NULL to show that this slot if free again. */ + xQueueRegistry[ ux ].pcQueueName = NULL; + + /* Set the handle to NULL to ensure the same queue handle cannot + * appear in the registry twice if it is added, removed, then + * added again. */ + xQueueRegistry[ ux ].xHandle = ( QueueHandle_t ) 0; + break; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ + +#endif /* configQUEUE_REGISTRY_SIZE */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TIMERS == 1 ) + + void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, + TickType_t xTicksToWait, + const BaseType_t xWaitIndefinitely ) + { + Queue_t * const pxQueue = xQueue; + + /* This function should not be called by application code hence the + * 'Restricted' in its name. It is not part of the public API. It is + * designed for use by kernel code, and has special calling requirements. + * It can result in vListInsert() being called on a list that can only + * possibly ever have one item in it, so the list will be fast, but even + * so it should be called with the scheduler locked and not from a critical + * section. */ + + /* Only do anything if there are no messages in the queue. This function + * will not actually cause the task to block, just place it on a blocked + * list. It will not block until the scheduler is unlocked - at which + * time a yield will be performed. If an item is added to the queue while + * the queue is locked, and the calling task blocks on the queue, then the + * calling task will be immediately unblocked when the queue is unlocked. */ + prvLockQueue( pxQueue ); + + if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U ) + { + /* There is nothing in the queue, block for the specified period. */ + vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + prvUnlockQueue( pxQueue ); + } + +#endif /* configUSE_TIMERS */ +/*-----------------------------------------------------------*/ + +#if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) + + QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) + { + QueueSetHandle_t pxQueue; + + pxQueue = xQueueGenericCreate( uxEventQueueLength, ( UBaseType_t ) sizeof( Queue_t * ), queueQUEUE_TYPE_SET ); + + return pxQueue; + } + +#endif /* configUSE_QUEUE_SETS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_QUEUE_SETS == 1 ) + + BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) + { + BaseType_t xReturn; + + taskENTER_CRITICAL(); + { + if( ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer != NULL ) + { + /* Cannot add a queue/semaphore to more than one queue set. */ + xReturn = pdFAIL; + } + else if( ( ( Queue_t * ) xQueueOrSemaphore )->uxMessagesWaiting != ( UBaseType_t ) 0 ) + { + /* Cannot add a queue/semaphore to a queue set if there are already + * items in the queue/semaphore. */ + xReturn = pdFAIL; + } + else + { + ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer = xQueueSet; + xReturn = pdPASS; + } + } + taskEXIT_CRITICAL(); + + return xReturn; + } + +#endif /* configUSE_QUEUE_SETS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_QUEUE_SETS == 1 ) + + BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, + QueueSetHandle_t xQueueSet ) + { + BaseType_t xReturn; + Queue_t * const pxQueueOrSemaphore = ( Queue_t * ) xQueueOrSemaphore; + + if( pxQueueOrSemaphore->pxQueueSetContainer != xQueueSet ) + { + /* The queue was not a member of the set. */ + xReturn = pdFAIL; + } + else if( pxQueueOrSemaphore->uxMessagesWaiting != ( UBaseType_t ) 0 ) + { + /* It is dangerous to remove a queue from a set when the queue is + * not empty because the queue set will still hold pending events for + * the queue. */ + xReturn = pdFAIL; + } + else + { + taskENTER_CRITICAL(); + { + /* The queue is no longer contained in the set. */ + pxQueueOrSemaphore->pxQueueSetContainer = NULL; + } + taskEXIT_CRITICAL(); + xReturn = pdPASS; + } + + return xReturn; + } /*lint !e818 xQueueSet could not be declared as pointing to const as it is a typedef. */ + +#endif /* configUSE_QUEUE_SETS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_QUEUE_SETS == 1 ) + + QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, + TickType_t const xTicksToWait ) + { + QueueSetMemberHandle_t xReturn = NULL; + + ( void ) xQueueReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait ); /*lint !e961 Casting from one typedef to another is not redundant. */ + return xReturn; + } + +#endif /* configUSE_QUEUE_SETS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_QUEUE_SETS == 1 ) + + QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) + { + QueueSetMemberHandle_t xReturn = NULL; + + ( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL ); /*lint !e961 Casting from one typedef to another is not redundant. */ + return xReturn; + } + +#endif /* configUSE_QUEUE_SETS */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_QUEUE_SETS == 1 ) + + static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue ) + { + Queue_t * pxQueueSetContainer = pxQueue->pxQueueSetContainer; + BaseType_t xReturn = pdFALSE; + + /* This function must be called form a critical section. */ + + configASSERT( pxQueueSetContainer ); + configASSERT( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength ); + + if( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength ) + { + const int16_t cTxLock = pxQueueSetContainer->cTxLock; + + traceQUEUE_SET_SEND( pxQueueSetContainer ); + + /* The data copied is the handle of the queue that contains data. */ + xReturn = prvCopyDataToQueue( pxQueueSetContainer, &pxQueue, queueSEND_TO_BACK ); + + if( cTxLock == queueUNLOCKED ) + { + if( listLIST_IS_EMPTY( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) == pdFALSE ) + { + if( xTaskRemoveFromEventList( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) != pdFALSE ) + { + /* The task waiting has a higher priority. */ + xReturn = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + configASSERT( cTxLock != queueINT16_MAX ); + + pxQueueSetContainer->cTxLock = ( int16_t ) ( cTxLock + 1 ); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xReturn; + } + +#endif /* configUSE_QUEUE_SETS */ diff --git a/MODULES/FreeRTOS/src/stream_buffer.c b/MODULES/FreeRTOS/src/stream_buffer.c new file mode 100644 index 0000000..f2f43d8 --- /dev/null +++ b/MODULES/FreeRTOS/src/stream_buffer.c @@ -0,0 +1,1314 @@ +/* + * FreeRTOS Kernel V10.4.3 LTS Patch 2 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "stream_buffer.h" + +#if ( configUSE_TASK_NOTIFICATIONS != 1 ) + #error configUSE_TASK_NOTIFICATIONS must be set to 1 to build stream_buffer.c +#endif + +/* Lint e961, e9021 and e750 are suppressed as a MISRA exception justified + * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined + * for the header files above, but not in this file, in order to generate the + * correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */ + +/* If the user has not provided application specific Rx notification macros, + * or #defined the notification macros away, them provide default implementations + * that uses task notifications. */ +/*lint -save -e9026 Function like macros allowed and needed here so they can be overridden. */ +#ifndef sbRECEIVE_COMPLETED + #define sbRECEIVE_COMPLETED( pxStreamBuffer ) \ + vTaskSuspendAll(); \ + { \ + if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL ) \ + { \ + ( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToSend, \ + ( uint32_t ) 0, \ + eNoAction ); \ + ( pxStreamBuffer )->xTaskWaitingToSend = NULL; \ + } \ + } \ + ( void ) xTaskResumeAll(); +#endif /* sbRECEIVE_COMPLETED */ + +#ifndef sbRECEIVE_COMPLETED_FROM_ISR + #define sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, \ + pxHigherPriorityTaskWoken ) \ + { \ + UBaseType_t uxSavedInterruptStatus; \ + \ + uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR(); \ + { \ + if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL ) \ + { \ + ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend, \ + ( uint32_t ) 0, \ + eNoAction, \ + pxHigherPriorityTaskWoken ); \ + ( pxStreamBuffer )->xTaskWaitingToSend = NULL; \ + } \ + } \ + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); \ + } +#endif /* sbRECEIVE_COMPLETED_FROM_ISR */ + +/* If the user has not provided an application specific Tx notification macro, + * or #defined the notification macro away, them provide a default implementation + * that uses task notifications. */ +#ifndef sbSEND_COMPLETED + #define sbSEND_COMPLETED( pxStreamBuffer ) \ + vTaskSuspendAll(); \ + { \ + if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL ) \ + { \ + ( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToReceive, \ + ( uint32_t ) 0, \ + eNoAction ); \ + ( pxStreamBuffer )->xTaskWaitingToReceive = NULL; \ + } \ + } \ + ( void ) xTaskResumeAll(); +#endif /* sbSEND_COMPLETED */ + +#ifndef sbSEND_COMPLETE_FROM_ISR + #define sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ) \ + { \ + UBaseType_t uxSavedInterruptStatus; \ + \ + uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR(); \ + { \ + if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL ) \ + { \ + ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive, \ + ( uint32_t ) 0, \ + eNoAction, \ + pxHigherPriorityTaskWoken ); \ + ( pxStreamBuffer )->xTaskWaitingToReceive = NULL; \ + } \ + } \ + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); \ + } +#endif /* sbSEND_COMPLETE_FROM_ISR */ +/*lint -restore (9026) */ + +/* The number of bytes used to hold the length of a message in the buffer. */ +#define sbBYTES_TO_STORE_MESSAGE_LENGTH ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) ) + +/* Bits stored in the ucFlags field of the stream buffer. */ +#define sbFLAGS_IS_MESSAGE_BUFFER ( ( uint8_t ) 1 ) /* Set if the stream buffer was created as a message buffer, in which case it holds discrete messages rather than a stream. */ +#define sbFLAGS_IS_STATICALLY_ALLOCATED ( ( uint8_t ) 2 ) /* Set if the stream buffer was created using statically allocated memory. */ + +/*-----------------------------------------------------------*/ + +/* Structure that hold state information on the buffer. */ +typedef struct StreamBufferDef_t /*lint !e9058 Style convention uses tag. */ +{ + volatile size_t xTail; /* Index to the next item to read within the buffer. */ + volatile size_t xHead; /* Index to the next item to write within the buffer. */ + size_t xLength; /* The length of the buffer pointed to by pucBuffer. */ + size_t xTriggerLevelBytes; /* The number of bytes that must be in the stream buffer before a task that is waiting for data is unblocked. */ + volatile TaskHandle_t xTaskWaitingToReceive; /* Holds the handle of a task waiting for data, or NULL if no tasks are waiting. */ + volatile TaskHandle_t xTaskWaitingToSend; /* Holds the handle of a task waiting to send data to a message buffer that is full. */ + uint8_t * pucBuffer; /* Points to the buffer itself - that is - the RAM that stores the data passed through the buffer. */ + uint8_t ucFlags; + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxStreamBufferNumber; /* Used for tracing purposes. */ + #endif +} StreamBuffer_t; + +/* + * The number of bytes available to be read from the buffer. + */ +static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) PRIVILEGED_FUNCTION; + +/* + * Add xCount bytes from pucData into the pxStreamBuffer message buffer. + * Returns the number of bytes written, which will either equal xCount in the + * success case, or 0 if there was not enough space in the buffer (in which case + * no data is written into the buffer). + */ +static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, + const uint8_t * pucData, + size_t xCount ) PRIVILEGED_FUNCTION; + +/* + * If the stream buffer is being used as a message buffer, then reads an entire + * message out of the buffer. If the stream buffer is being used as a stream + * buffer then read as many bytes as possible from the buffer. + * prvReadBytesFromBuffer() is called to actually extract the bytes from the + * buffer's data storage area. + */ +static size_t prvReadMessageFromBuffer( StreamBuffer_t * pxStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + size_t xBytesAvailable, + size_t xBytesToStoreMessageLength ) PRIVILEGED_FUNCTION; + +/* + * If the stream buffer is being used as a message buffer, then writes an entire + * message to the buffer. If the stream buffer is being used as a stream + * buffer then write as many bytes as possible to the buffer. + * prvWriteBytestoBuffer() is called to actually send the bytes to the buffer's + * data storage area. + */ +static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + size_t xSpace, + size_t xRequiredSpace ) PRIVILEGED_FUNCTION; + +/* + * Read xMaxCount bytes from the pxStreamBuffer message buffer and write them + * to pucData. + */ +static size_t prvReadBytesFromBuffer( StreamBuffer_t * pxStreamBuffer, + uint8_t * pucData, + size_t xMaxCount, + size_t xBytesAvailable ) PRIVILEGED_FUNCTION; + +/* + * Called by both pxStreamBufferCreate() and pxStreamBufferCreateStatic() to + * initialise the members of the newly created stream buffer structure. + */ +static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, + uint8_t * const pucBuffer, + size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + uint8_t ucFlags ) PRIVILEGED_FUNCTION; + +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xIsMessageBuffer ) + { + uint8_t * pucAllocatedMemory; + uint8_t ucFlags; + + /* In case the stream buffer is going to be used as a message buffer + * (that is, it will hold discrete messages with a little meta data that + * says how big the next message is) check the buffer will be large enough + * to hold at least one message. */ + if( xIsMessageBuffer == pdTRUE ) + { + /* Is a message buffer but not statically allocated. */ + ucFlags = sbFLAGS_IS_MESSAGE_BUFFER; + configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH ); + } + else + { + /* Not a message buffer and not statically allocated. */ + ucFlags = 0; + configASSERT( xBufferSizeBytes > 0 ); + } + + configASSERT( xTriggerLevelBytes <= xBufferSizeBytes ); + + /* A trigger level of 0 would cause a waiting task to unblock even when + * the buffer was empty. */ + if( xTriggerLevelBytes == ( size_t ) 0 ) + { + xTriggerLevelBytes = ( size_t ) 1; + } + + /* A stream buffer requires a StreamBuffer_t structure and a buffer. + * Both are allocated in a single call to pvPortMalloc(). The + * StreamBuffer_t structure is placed at the start of the allocated memory + * and the buffer follows immediately after. The requested size is + * incremented so the free space is returned as the user would expect - + * this is a quirk of the implementation that means otherwise the free + * space would be reported as one byte smaller than would be logically + * expected. */ + if( xBufferSizeBytes < ( xBufferSizeBytes + 1 + sizeof( StreamBuffer_t ) ) ) + { + xBufferSizeBytes++; + pucAllocatedMemory = ( uint8_t * ) pvPortMalloc( xBufferSizeBytes + sizeof( StreamBuffer_t ) ); /*lint !e9079 malloc() only returns void*. */ + } + else + { + pucAllocatedMemory = NULL; + } + + + if( pucAllocatedMemory != NULL ) + { + prvInitialiseNewStreamBuffer( ( StreamBuffer_t * ) pucAllocatedMemory, /* Structure at the start of the allocated memory. */ /*lint !e9087 Safe cast as allocated memory is aligned. */ /*lint !e826 Area is not too small and alignment is guaranteed provided malloc() behaves as expected and returns aligned buffer. */ + pucAllocatedMemory + sizeof( StreamBuffer_t ), /* Storage area follows. */ /*lint !e9016 Indexing past structure valid for uint8_t pointer, also storage area has no alignment requirement. */ + xBufferSizeBytes, + xTriggerLevelBytes, + ucFlags ); + + traceSTREAM_BUFFER_CREATE( ( ( StreamBuffer_t * ) pucAllocatedMemory ), xIsMessageBuffer ); + } + else + { + traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer ); + } + + return ( StreamBufferHandle_t ) pucAllocatedMemory; /*lint !e9087 !e826 Safe cast as allocated memory is aligned. */ + } + +#endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +#if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + BaseType_t xIsMessageBuffer, + uint8_t * const pucStreamBufferStorageArea, + StaticStreamBuffer_t * const pxStaticStreamBuffer ) + { + StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) pxStaticStreamBuffer; /*lint !e740 !e9087 Safe cast as StaticStreamBuffer_t is opaque Streambuffer_t. */ + StreamBufferHandle_t xReturn; + uint8_t ucFlags; + + configASSERT( pucStreamBufferStorageArea ); + configASSERT( pxStaticStreamBuffer ); + configASSERT( xTriggerLevelBytes <= xBufferSizeBytes ); + + /* A trigger level of 0 would cause a waiting task to unblock even when + * the buffer was empty. */ + if( xTriggerLevelBytes == ( size_t ) 0 ) + { + xTriggerLevelBytes = ( size_t ) 1; + } + + if( xIsMessageBuffer != pdFALSE ) + { + /* Statically allocated message buffer. */ + ucFlags = sbFLAGS_IS_MESSAGE_BUFFER | sbFLAGS_IS_STATICALLY_ALLOCATED; + } + else + { + /* Statically allocated stream buffer. */ + ucFlags = sbFLAGS_IS_STATICALLY_ALLOCATED; + } + + /* In case the stream buffer is going to be used as a message buffer + * (that is, it will hold discrete messages with a little meta data that + * says how big the next message is) check the buffer will be large enough + * to hold at least one message. */ + configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH ); + + #if ( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + * variable of type StaticStreamBuffer_t equals the size of the real + * message buffer structure. */ + volatile size_t xSize = sizeof( StaticStreamBuffer_t ); + configASSERT( xSize == sizeof( StreamBuffer_t ) ); + } /*lint !e529 xSize is referenced is configASSERT() is defined. */ + #endif /* configASSERT_DEFINED */ + + if( ( pucStreamBufferStorageArea != NULL ) && ( pxStaticStreamBuffer != NULL ) ) + { + prvInitialiseNewStreamBuffer( pxStreamBuffer, + pucStreamBufferStorageArea, + xBufferSizeBytes, + xTriggerLevelBytes, + ucFlags ); + + /* Remember this was statically allocated in case it is ever deleted + * again. */ + pxStreamBuffer->ucFlags |= sbFLAGS_IS_STATICALLY_ALLOCATED; + + traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer ); + + xReturn = ( StreamBufferHandle_t ) pxStaticStreamBuffer; /*lint !e9087 Data hiding requires cast to opaque type. */ + } + else + { + xReturn = NULL; + traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer ); + } + + return xReturn; + } + +#endif /* ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ +/*-----------------------------------------------------------*/ + +void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) +{ + StreamBuffer_t * pxStreamBuffer = xStreamBuffer; + + configASSERT( pxStreamBuffer ); + + traceSTREAM_BUFFER_DELETE( xStreamBuffer ); + + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) pdFALSE ) + { + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + /* Both the structure and the buffer were allocated using a single call + * to pvPortMalloc(), hence only one call to vPortFree() is required. */ + vPortFree( ( void * ) pxStreamBuffer ); /*lint !e9087 Standard free() semantics require void *, plus pxStreamBuffer was allocated by pvPortMalloc(). */ + } + #else + { + /* Should not be possible to get here, ucFlags must be corrupt. + * Force an assert. */ + configASSERT( xStreamBuffer == ( StreamBufferHandle_t ) ~0 ); + } + #endif + } + else + { + /* The structure and buffer were not allocated dynamically and cannot be + * freed - just scrub the structure so future use will assert. */ + ( void ) memset( pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); + } +} +/*-----------------------------------------------------------*/ + +BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + BaseType_t xReturn = pdFAIL; + + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxStreamBufferNumber; + #endif + + configASSERT( pxStreamBuffer ); + + #if ( configUSE_TRACE_FACILITY == 1 ) + { + /* Store the stream buffer number so it can be restored after the + * reset. */ + uxStreamBufferNumber = pxStreamBuffer->uxStreamBufferNumber; + } + #endif + + /* Can only reset a message buffer if there are no tasks blocked on it. */ + taskENTER_CRITICAL(); + { + if( pxStreamBuffer->xTaskWaitingToReceive == NULL ) + { + if( pxStreamBuffer->xTaskWaitingToSend == NULL ) + { + prvInitialiseNewStreamBuffer( pxStreamBuffer, + pxStreamBuffer->pucBuffer, + pxStreamBuffer->xLength, + pxStreamBuffer->xTriggerLevelBytes, + pxStreamBuffer->ucFlags ); + xReturn = pdPASS; + + #if ( configUSE_TRACE_FACILITY == 1 ) + { + pxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber; + } + #endif + + traceSTREAM_BUFFER_RESET( xStreamBuffer ); + } + } + } + taskEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, + size_t xTriggerLevel ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + BaseType_t xReturn; + + configASSERT( pxStreamBuffer ); + + /* It is not valid for the trigger level to be 0. */ + if( xTriggerLevel == ( size_t ) 0 ) + { + xTriggerLevel = ( size_t ) 1; + } + + /* The trigger level is the number of bytes that must be in the stream + * buffer before a task that is waiting for data is unblocked. */ + if( xTriggerLevel <= pxStreamBuffer->xLength ) + { + pxStreamBuffer->xTriggerLevelBytes = xTriggerLevel; + xReturn = pdPASS; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) +{ + const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + size_t xSpace; + + configASSERT( pxStreamBuffer ); + + xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail; + xSpace -= pxStreamBuffer->xHead; + xSpace -= ( size_t ) 1; + + if( xSpace >= pxStreamBuffer->xLength ) + { + xSpace -= pxStreamBuffer->xLength; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xSpace; +} +/*-----------------------------------------------------------*/ + +size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) +{ + const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + size_t xReturn; + + configASSERT( pxStreamBuffer ); + + xReturn = prvBytesInBuffer( pxStreamBuffer ); + return xReturn; +} +/*-----------------------------------------------------------*/ + +size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + TickType_t xTicksToWait ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + size_t xReturn, xSpace = 0; + size_t xRequiredSpace = xDataLengthBytes; + TimeOut_t xTimeOut; + + /* The maximum amount of space a stream buffer will ever report is its length + * minus 1. */ + const size_t xMaxReportedSpace = pxStreamBuffer->xLength - ( size_t ) 1; + + configASSERT( pvTxData ); + configASSERT( pxStreamBuffer ); + + /* This send function is used to write to both message buffers and stream + * buffers. If this is a message buffer then the space needed must be + * increased by the amount of bytes needed to store the length of the + * message. */ + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + { + xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH; + + /* Overflow? */ + configASSERT( xRequiredSpace > xDataLengthBytes ); + + /* If this is a message buffer then it must be possible to write the + * whole message. */ + if( xRequiredSpace > xMaxReportedSpace ) + { + /* The message would not fit even if the entire buffer was empty, + * so don't wait for space. */ + xTicksToWait = ( TickType_t ) 0; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* If this is a stream buffer then it is acceptable to write only part + * of the message to the buffer. Cap the length to the total length of + * the buffer. */ + if( xRequiredSpace > xMaxReportedSpace ) + { + xRequiredSpace = xMaxReportedSpace; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + if( xTicksToWait != ( TickType_t ) 0 ) + { + vTaskSetTimeOutState( &xTimeOut ); + + do + { + /* Wait until the required number of bytes are free in the message + * buffer. */ + taskENTER_CRITICAL(); + { + xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer ); + + if( xSpace < xRequiredSpace ) + { + /* Clear notification state as going to wait for space. */ + ( void ) xTaskNotifyStateClear( NULL ); + + /* Should only be one writer. */ + configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL ); + pxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle(); + } + else + { + taskEXIT_CRITICAL(); + break; + } + } + taskEXIT_CRITICAL(); + + traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer ); + ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait ); + pxStreamBuffer->xTaskWaitingToSend = NULL; + } while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xSpace == ( size_t ) 0 ) + { + xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace ); + + if( xReturn > ( size_t ) 0 ) + { + traceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn ); + + /* Was a task waiting for the data? */ + if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes ) + { + sbSEND_COMPLETED( pxStreamBuffer ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer ); + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + BaseType_t * const pxHigherPriorityTaskWoken ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + size_t xReturn, xSpace; + size_t xRequiredSpace = xDataLengthBytes; + + configASSERT( pvTxData ); + configASSERT( pxStreamBuffer ); + + /* This send function is used to write to both message buffers and stream + * buffers. If this is a message buffer then the space needed must be + * increased by the amount of bytes needed to store the length of the + * message. */ + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + { + xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer ); + xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace ); + + if( xReturn > ( size_t ) 0 ) + { + /* Was a task waiting for the data? */ + if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes ) + { + sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xReturn ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer, + const void * pvTxData, + size_t xDataLengthBytes, + size_t xSpace, + size_t xRequiredSpace ) +{ + BaseType_t xShouldWrite; + size_t xReturn; + + if( xSpace == ( size_t ) 0 ) + { + /* Doesn't matter if this is a stream buffer or a message buffer, there + * is no space to write. */ + xShouldWrite = pdFALSE; + } + else if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) == ( uint8_t ) 0 ) + { + /* This is a stream buffer, as opposed to a message buffer, so writing a + * stream of bytes rather than discrete messages. Write as many bytes as + * possible. */ + xShouldWrite = pdTRUE; + xDataLengthBytes = configMIN( xDataLengthBytes, xSpace ); + } + else if( xSpace >= xRequiredSpace ) + { + /* This is a message buffer, as opposed to a stream buffer, and there + * is enough space to write both the message length and the message itself + * into the buffer. Start by writing the length of the data, the data + * itself will be written later in this function. */ + xShouldWrite = pdTRUE; + ( void ) prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xDataLengthBytes ), sbBYTES_TO_STORE_MESSAGE_LENGTH ); + } + else + { + /* There is space available, but not enough space. */ + xShouldWrite = pdFALSE; + } + + if( xShouldWrite != pdFALSE ) + { + /* Writes the data itself. */ + xReturn = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alignment and access. */ + } + else + { + xReturn = 0; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength; + + configASSERT( pvRxData ); + configASSERT( pxStreamBuffer ); + + /* This receive function is used by both message buffers, which store + * discrete messages, and stream buffers, which store a continuous stream of + * bytes. Discrete messages include an additional + * sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the + * message. */ + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + { + xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH; + } + else + { + xBytesToStoreMessageLength = 0; + } + + if( xTicksToWait != ( TickType_t ) 0 ) + { + /* Checking if there is data and clearing the notification state must be + * performed atomically. */ + taskENTER_CRITICAL(); + { + xBytesAvailable = prvBytesInBuffer( pxStreamBuffer ); + + /* If this function was invoked by a message buffer read then + * xBytesToStoreMessageLength holds the number of bytes used to hold + * the length of the next discrete message. If this function was + * invoked by a stream buffer read then xBytesToStoreMessageLength will + * be 0. */ + if( xBytesAvailable <= xBytesToStoreMessageLength ) + { + /* Clear notification state as going to wait for data. */ + ( void ) xTaskNotifyStateClear( NULL ); + + /* Should only be one reader. */ + configASSERT( pxStreamBuffer->xTaskWaitingToReceive == NULL ); + pxStreamBuffer->xTaskWaitingToReceive = xTaskGetCurrentTaskHandle(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + if( xBytesAvailable <= xBytesToStoreMessageLength ) + { + /* Wait for data to be available. */ + traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer ); + ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait ); + pxStreamBuffer->xTaskWaitingToReceive = NULL; + + /* Recheck the data available after blocking. */ + xBytesAvailable = prvBytesInBuffer( pxStreamBuffer ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xBytesAvailable = prvBytesInBuffer( pxStreamBuffer ); + } + + /* Whether receiving a discrete message (where xBytesToStoreMessageLength + * holds the number of bytes used to store the message length) or a stream of + * bytes (where xBytesToStoreMessageLength is zero), the number of bytes + * available must be greater than xBytesToStoreMessageLength to be able to + * read bytes from the buffer. */ + if( xBytesAvailable > xBytesToStoreMessageLength ) + { + xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength ); + + /* Was a task waiting for space in the buffer? */ + if( xReceivedLength != ( size_t ) 0 ) + { + traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength ); + sbRECEIVE_COMPLETED( pxStreamBuffer ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer ); + mtCOVERAGE_TEST_MARKER(); + } + + return xReceivedLength; +} +/*-----------------------------------------------------------*/ + +size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + size_t xReturn, xBytesAvailable, xOriginalTail; + configMESSAGE_BUFFER_LENGTH_TYPE xTempReturn; + + configASSERT( pxStreamBuffer ); + + /* Ensure the stream buffer is being used as a message buffer. */ + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + { + xBytesAvailable = prvBytesInBuffer( pxStreamBuffer ); + + if( xBytesAvailable > sbBYTES_TO_STORE_MESSAGE_LENGTH ) + { + /* The number of bytes available is greater than the number of bytes + * required to hold the length of the next message, so another message + * is available. Return its length without removing the length bytes + * from the buffer. A copy of the tail is stored so the buffer can be + * returned to its prior state as the message is not actually being + * removed from the buffer. */ + xOriginalTail = pxStreamBuffer->xTail; + ( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempReturn, sbBYTES_TO_STORE_MESSAGE_LENGTH, xBytesAvailable ); + xReturn = ( size_t ) xTempReturn; + pxStreamBuffer->xTail = xOriginalTail; + } + else + { + /* The minimum amount of bytes in a message buffer is + * ( sbBYTES_TO_STORE_MESSAGE_LENGTH + 1 ), so if xBytesAvailable is + * less than sbBYTES_TO_STORE_MESSAGE_LENGTH the only other valid + * value is 0. */ + configASSERT( xBytesAvailable == 0 ); + xReturn = 0; + } + } + else + { + xReturn = 0; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + BaseType_t * const pxHigherPriorityTaskWoken ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength; + + configASSERT( pvRxData ); + configASSERT( pxStreamBuffer ); + + /* This receive function is used by both message buffers, which store + * discrete messages, and stream buffers, which store a continuous stream of + * bytes. Discrete messages include an additional + * sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the + * message. */ + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + { + xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH; + } + else + { + xBytesToStoreMessageLength = 0; + } + + xBytesAvailable = prvBytesInBuffer( pxStreamBuffer ); + + /* Whether receiving a discrete message (where xBytesToStoreMessageLength + * holds the number of bytes used to store the message length) or a stream of + * bytes (where xBytesToStoreMessageLength is zero), the number of bytes + * available must be greater than xBytesToStoreMessageLength to be able to + * read bytes from the buffer. */ + if( xBytesAvailable > xBytesToStoreMessageLength ) + { + xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength ); + + /* Was a task waiting for space in the buffer? */ + if( xReceivedLength != ( size_t ) 0 ) + { + sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength ); + + return xReceivedLength; +} +/*-----------------------------------------------------------*/ + +static size_t prvReadMessageFromBuffer( StreamBuffer_t * pxStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + size_t xBytesAvailable, + size_t xBytesToStoreMessageLength ) +{ + size_t xOriginalTail, xReceivedLength, xNextMessageLength; + configMESSAGE_BUFFER_LENGTH_TYPE xTempNextMessageLength; + + if( xBytesToStoreMessageLength != ( size_t ) 0 ) + { + /* A discrete message is being received. First receive the length + * of the message. A copy of the tail is stored so the buffer can be + * returned to its prior state if the length of the message is too + * large for the provided buffer. */ + xOriginalTail = pxStreamBuffer->xTail; + ( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempNextMessageLength, xBytesToStoreMessageLength, xBytesAvailable ); + xNextMessageLength = ( size_t ) xTempNextMessageLength; + + /* Reduce the number of bytes available by the number of bytes just + * read out. */ + xBytesAvailable -= xBytesToStoreMessageLength; + + /* Check there is enough space in the buffer provided by the + * user. */ + if( xNextMessageLength > xBufferLengthBytes ) + { + /* The user has provided insufficient space to read the message + * so return the buffer to its previous state (so the length of + * the message is in the buffer again). */ + pxStreamBuffer->xTail = xOriginalTail; + xNextMessageLength = 0; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* A stream of bytes is being received (as opposed to a discrete + * message), so read as many bytes as possible. */ + xNextMessageLength = xBufferLengthBytes; + } + + /* Read the actual data. */ + xReceivedLength = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) pvRxData, xNextMessageLength, xBytesAvailable ); /*lint !e9079 Data storage area is implemented as uint8_t array for ease of sizing, indexing and alignment. */ + + return xReceivedLength; +} +/*-----------------------------------------------------------*/ + +BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) +{ + const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + BaseType_t xReturn; + size_t xTail; + + configASSERT( pxStreamBuffer ); + + /* True if no bytes are available. */ + xTail = pxStreamBuffer->xTail; + + if( pxStreamBuffer->xHead == xTail ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) +{ + BaseType_t xReturn; + size_t xBytesToStoreMessageLength; + const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + + configASSERT( pxStreamBuffer ); + + /* This generic version of the receive function is used by both message + * buffers, which store discrete messages, and stream buffers, which store a + * continuous stream of bytes. Discrete messages include an additional + * sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the message. */ + if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 ) + { + xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH; + } + else + { + xBytesToStoreMessageLength = 0; + } + + /* True if the available space equals zero. */ + if( xStreamBufferSpacesAvailable( xStreamBuffer ) <= xBytesToStoreMessageLength ) + { + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, + BaseType_t * pxHigherPriorityTaskWoken ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + BaseType_t xReturn; + UBaseType_t uxSavedInterruptStatus; + + configASSERT( pxStreamBuffer ); + + uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR(); + { + if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL ) + { + ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive, + ( uint32_t ) 0, + eNoAction, + pxHigherPriorityTaskWoken ); + ( pxStreamBuffer )->xTaskWaitingToReceive = NULL; + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, + BaseType_t * pxHigherPriorityTaskWoken ) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + BaseType_t xReturn; + UBaseType_t uxSavedInterruptStatus; + + configASSERT( pxStreamBuffer ); + + uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR(); + { + if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL ) + { + ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend, + ( uint32_t ) 0, + eNoAction, + pxHigherPriorityTaskWoken ); + ( pxStreamBuffer )->xTaskWaitingToSend = NULL; + xReturn = pdTRUE; + } + else + { + xReturn = pdFALSE; + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, + const uint8_t * pucData, + size_t xCount ) +{ + size_t xNextHead, xFirstLength; + + configASSERT( xCount > ( size_t ) 0 ); + + xNextHead = pxStreamBuffer->xHead; + + /* Calculate the number of bytes that can be added in the first write - + * which may be less than the total number of bytes that need to be added if + * the buffer will wrap back to the beginning. */ + xFirstLength = configMIN( pxStreamBuffer->xLength - xNextHead, xCount ); + + /* Write as many bytes as can be written in the first write. */ + configASSERT( ( xNextHead + xFirstLength ) <= pxStreamBuffer->xLength ); + ( void ) memcpy( ( void * ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */ + + /* If the number of bytes written was less than the number that could be + * written in the first write... */ + if( xCount > xFirstLength ) + { + /* ...then write the remaining bytes to the start of the buffer. */ + configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength ); + ( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xNextHead += xCount; + + if( xNextHead >= pxStreamBuffer->xLength ) + { + xNextHead -= pxStreamBuffer->xLength; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + pxStreamBuffer->xHead = xNextHead; + + return xCount; +} +/*-----------------------------------------------------------*/ + +static size_t prvReadBytesFromBuffer( StreamBuffer_t * pxStreamBuffer, + uint8_t * pucData, + size_t xMaxCount, + size_t xBytesAvailable ) +{ + size_t xCount, xFirstLength, xNextTail; + + /* Use the minimum of the wanted bytes and the available bytes. */ + xCount = configMIN( xBytesAvailable, xMaxCount ); + + if( xCount > ( size_t ) 0 ) + { + xNextTail = pxStreamBuffer->xTail; + + /* Calculate the number of bytes that can be read - which may be + * less than the number wanted if the data wraps around to the start of + * the buffer. */ + xFirstLength = configMIN( pxStreamBuffer->xLength - xNextTail, xCount ); + + /* Obtain the number of bytes it is possible to obtain in the first + * read. Asserts check bounds of read and write. */ + configASSERT( xFirstLength <= xMaxCount ); + configASSERT( ( xNextTail + xFirstLength ) <= pxStreamBuffer->xLength ); + ( void ) memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xNextTail ] ), xFirstLength ); /*lint !e9087 memcpy() requires void *. */ + + /* If the total number of wanted bytes is greater than the number + * that could be read in the first read... */ + if( xCount > xFirstLength ) + { + /*...then read the remaining bytes from the start of the buffer. */ + configASSERT( xCount <= xMaxCount ); + ( void ) memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Move the tail pointer to effectively remove the data read from + * the buffer. */ + xNextTail += xCount; + + if( xNextTail >= pxStreamBuffer->xLength ) + { + xNextTail -= pxStreamBuffer->xLength; + } + + pxStreamBuffer->xTail = xNextTail; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xCount; +} +/*-----------------------------------------------------------*/ + +static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) +{ +/* Returns the distance between xTail and xHead. */ + size_t xCount; + + xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead; + xCount -= pxStreamBuffer->xTail; + + if( xCount >= pxStreamBuffer->xLength ) + { + xCount -= pxStreamBuffer->xLength; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xCount; +} +/*-----------------------------------------------------------*/ + +static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer, + uint8_t * const pucBuffer, + size_t xBufferSizeBytes, + size_t xTriggerLevelBytes, + uint8_t ucFlags ) +{ + /* Assert here is deliberately writing to the entire buffer to ensure it can + * be written to without generating exceptions, and is setting the buffer to a + * known value to assist in development/debugging. */ + #if ( configASSERT_DEFINED == 1 ) + { + /* The value written just has to be identifiable when looking at the + * memory. Don't use 0xA5 as that is the stack fill value and could + * result in confusion as to what is actually being observed. */ + const BaseType_t xWriteValue = 0x55; + configASSERT( memset( pucBuffer, ( int ) xWriteValue, xBufferSizeBytes ) == pucBuffer ); + } /*lint !e529 !e438 xWriteValue is only used if configASSERT() is defined. */ + #endif + + ( void ) memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); /*lint !e9087 memset() requires void *. */ + pxStreamBuffer->pucBuffer = pucBuffer; + pxStreamBuffer->xLength = xBufferSizeBytes; + pxStreamBuffer->xTriggerLevelBytes = xTriggerLevelBytes; + pxStreamBuffer->ucFlags = ucFlags; +} + +#if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) + { + return xStreamBuffer->uxStreamBufferNumber; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, + UBaseType_t uxStreamBufferNumber ) + { + xStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber; + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ( configUSE_TRACE_FACILITY == 1 ) + + uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer ) + { + return( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ); + } + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ diff --git a/MODULES/FreeRTOS/src/tasks.c b/MODULES/FreeRTOS/src/tasks.c new file mode 100644 index 0000000..4d2f000 --- /dev/null +++ b/MODULES/FreeRTOS/src/tasks.c @@ -0,0 +1,5027 @@ +/* + * FreeRTOS Kernel V10.4.3 LTS Patch 2 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "stack_macros.h" + +/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified + * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined + * for the header files above, but not in this file, in order to generate the + * correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */ + +/* Set configUSE_STATS_FORMATTING_FUNCTIONS to 2 to include the stats formatting + * functions but without including stdio.h here. */ +#if (configUSE_STATS_FORMATTING_FUNCTIONS == 1) + + /* At the bottom of this file are two optional functions that can be used + * to generate human readable text from the raw data generated by the + * uxTaskGetSystemState() function. Note the formatting functions are provided + * for convenience only, and are NOT considered part of the kernel. */ + #include +#endif /* configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) */ + +#if (configUSE_PREEMPTION == 0) + + /* If the cooperative scheduler is being used then a yield should not be + * performed just because a higher priority task has been woken. */ + #define taskYIELD_IF_USING_PREEMPTION() +#else +#define taskYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API() +#endif + +/* Values that can be assigned to the ucNotifyState member of the TCB. */ +#define taskNOT_WAITING_NOTIFICATION ( ( uint8_t ) 0 ) /* Must be zero as it is the initialised value. */ +#define taskWAITING_NOTIFICATION ( ( uint8_t ) 1 ) +#define taskNOTIFICATION_RECEIVED ( ( uint8_t ) 2 ) + +/* + * The value used to fill the stack of a task when the task is created. This + * is used purely for checking the high water mark for tasks. + */ +#define tskSTACK_FILL_BYTE ( 0xa5U ) + +/* Bits used to recored how a task's stack and TCB were allocated. */ +#define tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB ( ( uint8_t ) 0 ) +#define tskSTATICALLY_ALLOCATED_STACK_ONLY ( ( uint8_t ) 1 ) +#define tskSTATICALLY_ALLOCATED_STACK_AND_TCB ( ( uint8_t ) 2 ) + +/* If any of the following are set then task stacks are filled with a known + * value so the high water mark can be determined. If none of the following are + * set then don't fill the stack so there is no unnecessary dependency on memset. */ +#if ((configCHECK_FOR_STACK_OVERFLOW > 1) || (configUSE_TRACE_FACILITY == 1) || (INCLUDE_uxTaskGetStackHighWaterMark == 1) || (INCLUDE_uxTaskGetStackHighWaterMark2 == 1)) +#define tskSET_NEW_STACKS_TO_KNOWN_VALUE 1 +#else +#define tskSET_NEW_STACKS_TO_KNOWN_VALUE 0 +#endif + +/* + * Macros used by vListTask to indicate which state a task is in. + */ +#define tskRUNNING_CHAR ( 'X' ) +#define tskBLOCKED_CHAR ( 'B' ) +#define tskREADY_CHAR ( 'R' ) +#define tskDELETED_CHAR ( 'D' ) +#define tskSUSPENDED_CHAR ( 'S' ) + +/* + * Some kernel aware debuggers require the data the debugger needs access to be + * global, rather than file scope. + */ +#ifdef portREMOVE_STATIC_QUALIFIER +#define static +#endif + +/* The name allocated to the Idle task. This can be overridden by defining + * configIDLE_TASK_NAME in FreeRTOSConfig.h. */ +#ifndef configIDLE_TASK_NAME +#define configIDLE_TASK_NAME "IDLE" +#endif + +#if (configUSE_PORT_OPTIMISED_TASK_SELECTION == 0) + +/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 0 then task selection is + * performed in a generic way that is not optimised to any particular + * microcontroller architecture. */ + +/* uxTopReadyPriority holds the priority of the highest priority ready + * state task. */ +#define taskRECORD_READY_PRIORITY(uxPriority) \ + { \ + if( ( uxPriority ) > uxTopReadyPriority ) \ + { \ + uxTopReadyPriority = ( uxPriority ); \ + } \ + } /* taskRECORD_READY_PRIORITY */ + +/*-----------------------------------------------------------*/ + +#define taskSELECT_HIGHEST_PRIORITY_TASK() \ + { \ + UBaseType_t uxTopPriority = uxTopReadyPriority; \ + \ + /* Find the highest priority queue that contains ready tasks. */ \ + while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopPriority ] ) ) ) \ + { \ + configASSERT( uxTopPriority ); \ + --uxTopPriority; \ + } \ + \ + /* listGET_OWNER_OF_NEXT_ENTRY indexes through the list, so the tasks of \ + * the same priority get an equal share of the processor time. */ \ + listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) ); \ + uxTopReadyPriority = uxTopPriority; \ + } /* taskSELECT_HIGHEST_PRIORITY_TASK */ + +/*-----------------------------------------------------------*/ + +/* Define away taskRESET_READY_PRIORITY() and portRESET_READY_PRIORITY() as + * they are only required when a port optimised method of task selection is + * being used. */ +#define taskRESET_READY_PRIORITY(uxPriority) +#define portRESET_READY_PRIORITY(uxPriority, uxTopReadyPriority) + +#else /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + + /* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 1 then task selection is + * performed in a way that is tailored to the particular microcontroller + * architecture being used. */ + +/* A port optimised version is provided. Call the port defined macros. */ + #define taskRECORD_READY_PRIORITY( uxPriority ) portRECORD_READY_PRIORITY( uxPriority, uxTopReadyPriority ) + +/*-----------------------------------------------------------*/ + + #define taskSELECT_HIGHEST_PRIORITY_TASK() \ + { \ + UBaseType_t uxTopPriority; \ + \ + /* Find the highest priority list that contains ready tasks. */ \ + portGET_HIGHEST_PRIORITY( uxTopPriority, uxTopReadyPriority ); \ + configASSERT( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ uxTopPriority ] ) ) > 0 ); \ + listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) ); \ + } /* taskSELECT_HIGHEST_PRIORITY_TASK() */ + +/*-----------------------------------------------------------*/ + +/* A port optimised version is provided, call it only if the TCB being reset + * is being referenced from a ready list. If it is referenced from a delayed + * or suspended list then it won't be in a ready list. */ + #define taskRESET_READY_PRIORITY( uxPriority ) \ + { \ + if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ ( uxPriority ) ] ) ) == ( UBaseType_t ) 0 ) \ + { \ + portRESET_READY_PRIORITY( ( uxPriority ), ( uxTopReadyPriority ) ); \ + } \ + } + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/*-----------------------------------------------------------*/ + +/* pxDelayedTaskList and pxOverflowDelayedTaskList are switched when the tick + * count overflows. */ +#define taskSWITCH_DELAYED_LISTS() \ + { \ + List_t * pxTemp; \ + \ + /* The delayed tasks list should be empty when the lists are switched. */ \ + configASSERT( ( listLIST_IS_EMPTY( pxDelayedTaskList ) ) ); \ + \ + pxTemp = pxDelayedTaskList; \ + pxDelayedTaskList = pxOverflowDelayedTaskList; \ + pxOverflowDelayedTaskList = pxTemp; \ + xNumOfOverflows++; \ + prvResetNextTaskUnblockTime(); \ + } + +/*-----------------------------------------------------------*/ + +/* + * Place the task represented by pxTCB into the appropriate ready list for + * the task. It is inserted at the end of the list. + */ +#define prvAddTaskToReadyList(pxTCB) \ + traceMOVED_TASK_TO_READY_STATE( pxTCB ); \ + taskRECORD_READY_PRIORITY( ( pxTCB )->uxPriority ); \ + vListInsertEnd( &( pxReadyTasksLists[ ( pxTCB )->uxPriority ] ), &( ( pxTCB )->xStateListItem ) ); \ + tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB ) +/*-----------------------------------------------------------*/ + +/* + * Several functions take an TaskHandle_t parameter that can optionally be NULL, + * where NULL is used to indicate that the handle of the currently executing + * task should be used in place of the parameter. This macro simply checks to + * see if the parameter is NULL and returns a pointer to the appropriate TCB. + */ +#define prvGetTCBFromHandle(pxHandle) ( ( ( pxHandle ) == NULL ) ? pxCurrentTCB : ( pxHandle ) ) + +/* The item value of the event list item is normally used to hold the priority + * of the task to which it belongs (coded to allow it to be held in reverse + * priority order). However, it is occasionally borrowed for other purposes. It + * is important its value is not updated due to a task priority change while it is + * being used for another purpose. The following bit definition is used to inform + * the scheduler that the value should not be changed - in which case it is the + * responsibility of whichever module is using the value to ensure it gets set back + * to its original value when it is released. */ +#if (configUSE_16_BIT_TICKS == 1) +#define taskEVENT_LIST_ITEM_VALUE_IN_USE 0x8000U +#else +#define taskEVENT_LIST_ITEM_VALUE_IN_USE 0x80000000UL +#endif + +/* + * Task control block. A task control block (TCB) is allocated for each task, + * and stores task state information, including a pointer to the task's context + * (the task's run time environment, including register values) + */ +typedef struct tskTaskControlBlock /* The old naming convention is used to prevent breaking kernel aware debuggers. */ +{ + volatile StackType_t *pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack. THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */ + +#if (portUSING_MPU_WRAPPERS == 1) + xMPU_SETTINGS xMPUSettings; /*< The MPU settings are defined as part of the port layer. THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */ +#endif + + ListItem_t xStateListItem; /*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */ + ListItem_t xEventListItem; /*< Used to reference a task from an event list. */ + UBaseType_t uxPriority; /*< The priority of the task. 0 is the lowest priority. */ + StackType_t *pxStack; /*< Points to the start of the stack. */ + char pcTaskName[configMAX_TASK_NAME_LEN]; /*< Descriptive name given to the task when created. Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + +#if ((portSTACK_GROWTH > 0) || (configRECORD_STACK_HIGH_ADDRESS == 1)) + StackType_t * pxEndOfStack; /*< Points to the highest valid address for the stack. */ +#endif + +#if (portCRITICAL_NESTING_IN_TCB == 1) + UBaseType_t uxCriticalNesting; /*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */ +#endif + +#if (configUSE_TRACE_FACILITY == 1) + UBaseType_t uxTCBNumber; /*< Stores a number that increments each time a TCB is created. It allows debuggers to determine when a task has been deleted and then recreated. */ + UBaseType_t uxTaskNumber; /*< Stores a number specifically for use by third party trace code. */ +#endif + +#if (configUSE_MUTEXES == 1) + UBaseType_t uxBasePriority; /*< The priority last assigned to the task - used by the priority inheritance mechanism. */ + UBaseType_t uxMutexesHeld; +#endif + +#if (configUSE_APPLICATION_TASK_TAG == 1) + TaskHookFunction_t pxTaskTag; +#endif + +#if (configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0) + void * pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ]; +#endif + +#if (configGENERATE_RUN_TIME_STATS == 1) + uint32_t ulRunTimeCounter; /*< Stores the amount of time the task has spent in the Running state. */ +#endif + +#if (configUSE_NEWLIB_REENTRANT == 1) + + /* Allocate a Newlib reent structure that is specific to this task. + * Note Newlib support has been included by popular demand, but is not + * used by the FreeRTOS maintainers themselves. FreeRTOS is not + * responsible for resulting newlib operation. User must be familiar with + * newlib and must provide system-wide implementations of the necessary + * stubs. Be warned that (at the time of writing) the current newlib design + * implements a system-wide malloc() that must be provided with locks. + * + * See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html + * for additional information. */ + struct _reent xNewLib_reent; +#endif + +#if (configUSE_TASK_NOTIFICATIONS == 1) + volatile uint32_t ulNotifiedValue[configTASK_NOTIFICATION_ARRAY_ENTRIES]; + volatile uint8_t ucNotifyState[configTASK_NOTIFICATION_ARRAY_ENTRIES]; +#endif + + /* See the comments in FreeRTOS.h with the definition of + * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */ +#if (tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ + uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */ +#endif + +#if (INCLUDE_xTaskAbortDelay == 1) + uint8_t ucDelayAborted; +#endif + +#if (configUSE_POSIX_ERRNO == 1) + int iTaskErrno; +#endif +} tskTCB; + +/* The old tskTCB name is maintained above then typedefed to the new TCB_t name + * below to enable the use of older kernel aware debuggers. */ +typedef tskTCB TCB_t; + +/*lint -save -e956 A manual analysis and inspection has been used to determine + * which static variables must be declared volatile. */ +PRIVILEGED_DATA TCB_t *volatile pxCurrentTCB = NULL; + +/* Lists for ready and blocked tasks. -------------------- + * xDelayedTaskList1 and xDelayedTaskList2 could be move to function scople but + * doing so breaks some kernel aware debuggers and debuggers that rely on removing + * the static qualifier. */ +PRIVILEGED_DATA static List_t pxReadyTasksLists[configMAX_PRIORITIES]; /*< Prioritised ready tasks. */ +PRIVILEGED_DATA static List_t xDelayedTaskList1; /*< Delayed tasks. */ +PRIVILEGED_DATA static List_t xDelayedTaskList2; /*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */ +PRIVILEGED_DATA static List_t *volatile pxDelayedTaskList; /*< Points to the delayed task list currently being used. */ +PRIVILEGED_DATA static List_t *volatile pxOverflowDelayedTaskList; /*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */ +PRIVILEGED_DATA static List_t xPendingReadyList; /*< Tasks that have been readied while the scheduler was suspended. They will be moved to the ready list when the scheduler is resumed. */ + +#if (INCLUDE_vTaskDelete == 1) + +PRIVILEGED_DATA static List_t xTasksWaitingTermination; /*< Tasks that have been deleted - but their memory not yet freed. */ +PRIVILEGED_DATA static volatile UBaseType_t uxDeletedTasksWaitingCleanUp = (UBaseType_t) 0U; + +#endif + +#if (INCLUDE_vTaskSuspend == 1) + +PRIVILEGED_DATA static List_t xSuspendedTaskList; /*< Tasks that are currently suspended. */ + +#endif + +/* Global POSIX errno. Its value is changed upon context switching to match + * the errno of the currently running task. */ +#if (configUSE_POSIX_ERRNO == 1) +int FreeRTOS_errno = 0; +#endif + +/* Other file private variables. --------------------------------*/ +PRIVILEGED_DATA static volatile UBaseType_t uxCurrentNumberOfTasks = (UBaseType_t) 0U; +PRIVILEGED_DATA static volatile TickType_t xTickCount = (TickType_t) configINITIAL_TICK_COUNT; +PRIVILEGED_DATA static volatile UBaseType_t uxTopReadyPriority = tskIDLE_PRIORITY; +PRIVILEGED_DATA static volatile BaseType_t xSchedulerRunning = pdFALSE; +PRIVILEGED_DATA static volatile TickType_t xPendedTicks = (TickType_t) 0U; +PRIVILEGED_DATA static volatile BaseType_t xYieldPending = pdFALSE; +PRIVILEGED_DATA static volatile BaseType_t xNumOfOverflows = (BaseType_t) 0; +PRIVILEGED_DATA static UBaseType_t uxTaskNumber = (UBaseType_t) 0U; +PRIVILEGED_DATA static volatile TickType_t xNextTaskUnblockTime = (TickType_t) 0U; /* Initialised to portMAX_DELAY before the scheduler starts. */ +PRIVILEGED_DATA static TaskHandle_t xIdleTaskHandle = NULL; /*< Holds the handle of the idle task. The idle task is created automatically when the scheduler is started. */ + +/* Improve support for OpenOCD. The kernel tracks Ready tasks via priority lists. + * For tracking the state of remote threads, OpenOCD uses uxTopUsedPriority + * to determine the number of priority lists to read back from the remote target. */ +const volatile UBaseType_t uxTopUsedPriority = configMAX_PRIORITIES - 1U; + +/* Context switches are held pending while the scheduler is suspended. Also, + * interrupts must not manipulate the xStateListItem of a TCB, or any of the + * lists the xStateListItem can be referenced from, if the scheduler is suspended. + * If an interrupt needs to unblock a task while the scheduler is suspended then it + * moves the task's event list item into the xPendingReadyList, ready for the + * kernel to move the task from the pending ready list into the real ready list + * when the scheduler is unsuspended. The pending ready list itself can only be + * accessed from a critical section. */ +PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended = (UBaseType_t) pdFALSE; + +#if (configGENERATE_RUN_TIME_STATS == 1) + + /* Do not move these variables to function scope as doing so prevents the + * code working with debuggers that need to remove the static qualifier. */ + PRIVILEGED_DATA static uint32_t ulTaskSwitchedInTime = 0UL; /*< Holds the value of a timer/counter the last time a task was switched in. */ + PRIVILEGED_DATA static volatile uint32_t ulTotalRunTime = 0UL; /*< Holds the total amount of execution time as defined by the run time counter clock. */ + +#endif + +/*lint -restore */ + +/*-----------------------------------------------------------*/ + +/* File private functions. --------------------------------*/ + +/** + * Utility task that simply returns pdTRUE if the task referenced by xTask is + * currently in the Suspended state, or pdFALSE if the task referenced by xTask + * is in any other state. + */ +#if (INCLUDE_vTaskSuspend == 1) + +static BaseType_t prvTaskIsTaskSuspended(const TaskHandle_t xTask) PRIVILEGED_FUNCTION; + +#endif /* INCLUDE_vTaskSuspend */ + +/* + * Utility to ready all the lists used by the scheduler. This is called + * automatically upon the creation of the first task. + */ +static void prvInitialiseTaskLists(void) PRIVILEGED_FUNCTION; + +/* + * The idle task, which as all tasks is implemented as a never ending loop. + * The idle task is automatically created and added to the ready lists upon + * creation of the first user task. + * + * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific + * language extensions. The equivalent prototype for this function is: + * + * void prvIdleTask( void *pvParameters ); + * + */ +static portTASK_FUNCTION_PROTO(prvIdleTask, pvParameters) PRIVILEGED_FUNCTION; + +/* + * Utility to free all memory allocated by the scheduler to hold a TCB, + * including the stack pointed to by the TCB. + * + * This does not free memory allocated by the task itself (i.e. memory + * allocated by calls to pvPortMalloc from within the tasks application code). + */ +#if (INCLUDE_vTaskDelete == 1) + +static void prvDeleteTCB(TCB_t *pxTCB) PRIVILEGED_FUNCTION; + +#endif + +/* + * Used only by the idle task. This checks to see if anything has been placed + * in the list of tasks waiting to be deleted. If so the task is cleaned up + * and its TCB deleted. + */ +static void prvCheckTasksWaitingTermination(void) PRIVILEGED_FUNCTION; + +/* + * The currently executing task is entering the Blocked state. Add the task to + * either the current or the overflow delayed task list. + */ +static void prvAddCurrentTaskToDelayedList(TickType_t xTicksToWait, + const BaseType_t xCanBlockIndefinitely) PRIVILEGED_FUNCTION; + +/* + * Fills an TaskStatus_t structure with information on each task that is + * referenced from the pxList list (which may be a ready list, a delayed list, + * a suspended list, etc.). + * + * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM + * NORMAL APPLICATION CODE. + */ +#if (configUSE_TRACE_FACILITY == 1) + +static UBaseType_t prvListTasksWithinSingleList(TaskStatus_t *pxTaskStatusArray, + List_t *pxList, + eTaskState eState) PRIVILEGED_FUNCTION; + +#endif + +/* + * Searches pxList for a task with name pcNameToQuery - returning a handle to + * the task if it is found, or NULL if the task is not found. + */ +#if (INCLUDE_xTaskGetHandle == 1) + + static TCB_t * prvSearchForNameWithinSingleList( List_t * pxList, + const char pcNameToQuery[] ) PRIVILEGED_FUNCTION; + +#endif + +/* + * When a task is created, the stack of the task is filled with a known value. + * This function determines the 'high water mark' of the task stack by + * determining how much of the stack remains at the original preset value. + */ +#if ((configUSE_TRACE_FACILITY == 1) || (INCLUDE_uxTaskGetStackHighWaterMark == 1) || (INCLUDE_uxTaskGetStackHighWaterMark2 == 1)) + +static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace(const uint8_t *pucStackByte) PRIVILEGED_FUNCTION; + +#endif + +/* + * Return the amount of time, in ticks, that will pass before the kernel will + * next move a task from the Blocked state to the Running state. + * + * This conditional compilation should use inequality to 0, not equality to 1. + * This is to ensure portSUPPRESS_TICKS_AND_SLEEP() can be called when user + * defined low power mode implementations require configUSE_TICKLESS_IDLE to be + * set to a value other than 1. + */ +#if (configUSE_TICKLESS_IDLE != 0) + +static TickType_t prvGetExpectedIdleTime( void ) PRIVILEGED_FUNCTION; + +#endif + +/* + * Set xNextTaskUnblockTime to the time at which the next Blocked state task + * will exit the Blocked state. + */ +static void prvResetNextTaskUnblockTime(void) PRIVILEGED_FUNCTION; + +#if ((configUSE_TRACE_FACILITY == 1) && (configUSE_STATS_FORMATTING_FUNCTIONS > 0)) + + /* + * Helper function used to pad task names with spaces when printing out + * human readable tables of task information. + */ + static char * prvWriteNameToBuffer( char * pcBuffer, + const char * pcTaskName ) PRIVILEGED_FUNCTION; + +#endif + +/* + * Called after a Task_t structure has been allocated either statically or + * dynamically to fill in the structure's members. + */ +static void prvInitialiseNewTask(TaskFunction_t pxTaskCode, + const char *const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const uint32_t ulStackDepth, + void *const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t *const pxCreatedTask, + TCB_t *pxNewTCB, + const MemoryRegion_t *const xRegions) PRIVILEGED_FUNCTION; + +/* + * Called after a new task has been created and initialised to place the task + * under the control of the scheduler. + */ +static void prvAddNewTaskToReadyList(TCB_t *pxNewTCB) PRIVILEGED_FUNCTION; + +/* + * freertos_tasks_c_additions_init() should only be called if the user definable + * macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is the only macro + * called by the function. + */ +#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT + +static void freertos_tasks_c_additions_init( void ) PRIVILEGED_FUNCTION; + +#endif + +/*-----------------------------------------------------------*/ + +#if (configSUPPORT_STATIC_ALLOCATION == 1) + +TaskHandle_t xTaskCreateStatic(TaskFunction_t pxTaskCode, + const char *const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const uint32_t ulStackDepth, + void *const pvParameters, + UBaseType_t uxPriority, + StackType_t *const puxStackBuffer, + StaticTask_t *const pxTaskBuffer) { + TCB_t *pxNewTCB; + TaskHandle_t xReturn; + + configASSERT(puxStackBuffer != NULL); + configASSERT(pxTaskBuffer != NULL); + +#if (configASSERT_DEFINED == 1) + { + /* Sanity check that the size of the structure used to declare a + * variable of type StaticTask_t equals the size of the real task + * structure. */ + volatile size_t xSize = sizeof(StaticTask_t); + configASSERT(xSize == sizeof(TCB_t)); + (void) xSize; /* Prevent lint warning when configASSERT() is not used. */ + } +#endif /* configASSERT_DEFINED */ + + if ((pxTaskBuffer != NULL) && (puxStackBuffer != NULL)) { + /* The memory used for the task's TCB and stack are passed into this + * function - use them. */ + pxNewTCB = (TCB_t *) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ + pxNewTCB->pxStack = (StackType_t *) puxStackBuffer; + +#if (tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ + { + /* Tasks can be created statically or dynamically, so note this + * task was created statically in case the task is later deleted. */ + pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; + } +#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ + + prvInitialiseNewTask(pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL); + prvAddNewTaskToReadyList(pxNewTCB); + } else { + xReturn = NULL; + } + + return xReturn; +} + +#endif /* SUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + +#if ((portUSING_MPU_WRAPPERS == 1) && (configSUPPORT_STATIC_ALLOCATION == 1)) + + BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, + TaskHandle_t * pxCreatedTask ) + { + TCB_t * pxNewTCB; + BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + + configASSERT( pxTaskDefinition->puxStackBuffer != NULL ); + configASSERT( pxTaskDefinition->pxTaskBuffer != NULL ); + + if( ( pxTaskDefinition->puxStackBuffer != NULL ) && ( pxTaskDefinition->pxTaskBuffer != NULL ) ) + { + /* Allocate space for the TCB. Where the memory comes from depends + * on the implementation of the port malloc function and whether or + * not static allocation is being used. */ + pxNewTCB = ( TCB_t * ) pxTaskDefinition->pxTaskBuffer; + + /* Store the stack location in the TCB. */ + pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer; + + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) + { + /* Tasks can be created statically or dynamically, so note this + * task was created statically in case the task is later deleted. */ + pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; + } + #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ + + prvInitialiseNewTask( pxTaskDefinition->pvTaskCode, + pxTaskDefinition->pcName, + ( uint32_t ) pxTaskDefinition->usStackDepth, + pxTaskDefinition->pvParameters, + pxTaskDefinition->uxPriority, + pxCreatedTask, pxNewTCB, + pxTaskDefinition->xRegions ); + + prvAddNewTaskToReadyList( pxNewTCB ); + xReturn = pdPASS; + } + + return xReturn; + } + +#endif /* ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ +/*-----------------------------------------------------------*/ + +#if ((portUSING_MPU_WRAPPERS == 1) && (configSUPPORT_DYNAMIC_ALLOCATION == 1)) + + BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, + TaskHandle_t * pxCreatedTask ) + { + TCB_t * pxNewTCB; + BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + + configASSERT( pxTaskDefinition->puxStackBuffer ); + + if( pxTaskDefinition->puxStackBuffer != NULL ) + { + /* Allocate space for the TCB. Where the memory comes from depends + * on the implementation of the port malloc function and whether or + * not static allocation is being used. */ + pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); + + if( pxNewTCB != NULL ) + { + /* Store the stack location in the TCB. */ + pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer; + + #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) + { + /* Tasks can be created statically or dynamically, so note + * this task had a statically allocated stack in case it is + * later deleted. The TCB was allocated dynamically. */ + pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_ONLY; + } + #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ + + prvInitialiseNewTask( pxTaskDefinition->pvTaskCode, + pxTaskDefinition->pcName, + ( uint32_t ) pxTaskDefinition->usStackDepth, + pxTaskDefinition->pvParameters, + pxTaskDefinition->uxPriority, + pxCreatedTask, pxNewTCB, + pxTaskDefinition->xRegions ); + + prvAddNewTaskToReadyList( pxNewTCB ); + xReturn = pdPASS; + } + } + + return xReturn; + } + +#endif /* portUSING_MPU_WRAPPERS */ +/*-----------------------------------------------------------*/ + +#if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + +BaseType_t xTaskCreate(TaskFunction_t pxTaskCode, + const char *const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const configSTACK_DEPTH_TYPE usStackDepth, + void *const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t *const pxCreatedTask) { + TCB_t *pxNewTCB; + BaseType_t xReturn; + + /* If the stack grows down then allocate the stack then the TCB so the stack + * does not grow into the TCB. Likewise if the stack grows up then allocate + * the TCB then the stack. */ +#if (portSTACK_GROWTH > 0) + { + /* Allocate space for the TCB. Where the memory comes from depends on + * the implementation of the port malloc function and whether or not static + * allocation is being used. */ + pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); + + if( pxNewTCB != NULL ) + { + /* Allocate space for the stack used by the task being created. + * The base of the stack memory stored in the TCB so the task can + * be deleted later if required. */ + pxNewTCB->pxStack = ( StackType_t * ) pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + + if( pxNewTCB->pxStack == NULL ) + { + /* Could not allocate the stack. Delete the allocated TCB. */ + vPortFree( pxNewTCB ); + pxNewTCB = NULL; + } + } + } +#else /* portSTACK_GROWTH */ + { + StackType_t *pxStack; + + /* Allocate space for the stack used by the task being created. */ + pxStack = pvPortMalloc((((size_t) usStackDepth) * + sizeof(StackType_t))); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */ + + if (pxStack != NULL) { + /* Allocate space for the TCB. */ + pxNewTCB = (TCB_t *) pvPortMalloc( + sizeof(TCB_t)); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */ + + if (pxNewTCB != NULL) { + /* Store the stack location in the TCB. */ + pxNewTCB->pxStack = pxStack; + } else { + /* The stack cannot be used as the TCB was not created. Free + * it again. */ + vPortFree(pxStack); + } + } else { + pxNewTCB = NULL; + } + } +#endif /* portSTACK_GROWTH */ + + if (pxNewTCB != NULL) { +#if (tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */ + { + /* Tasks can be created statically or dynamically, so note this + * task was created dynamically in case it is later deleted. */ + pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB; + } +#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ + + prvInitialiseNewTask(pxTaskCode, pcName, (uint32_t) usStackDepth, pvParameters, uxPriority, pxCreatedTask, + pxNewTCB, NULL); + prvAddNewTaskToReadyList(pxNewTCB); + xReturn = pdPASS; + } else { + xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; + } + + return xReturn; +} + +#endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + +/*-----------------------------------------------------------*/ + +static void prvInitialiseNewTask(TaskFunction_t pxTaskCode, + const char *const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const uint32_t ulStackDepth, + void *const pvParameters, + UBaseType_t uxPriority, + TaskHandle_t *const pxCreatedTask, + TCB_t *pxNewTCB, + const MemoryRegion_t *const xRegions) { + StackType_t *pxTopOfStack; + UBaseType_t x; + +#if (portUSING_MPU_WRAPPERS == 1) + /* Should the task be created in privileged mode? */ + BaseType_t xRunPrivileged; + + if( ( uxPriority & portPRIVILEGE_BIT ) != 0U ) + { + xRunPrivileged = pdTRUE; + } + else + { + xRunPrivileged = pdFALSE; + } + uxPriority &= ~portPRIVILEGE_BIT; +#endif /* portUSING_MPU_WRAPPERS == 1 */ + + /* Avoid dependency on memset() if it is not required. */ +#if (tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1) + { + /* Fill the stack with a known value to assist debugging. */ + ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) ); +/* + size_t k = 0; + while (k < (size_t) ulStackDepth) { + ((uint8_t *) pxNewTCB->pxStack)[0] = tskSTACK_FILL_BYTE; + ((uint8_t *) pxNewTCB->pxStack)[1] = tskSTACK_FILL_BYTE; + ((uint8_t *) pxNewTCB->pxStack)[2] = tskSTACK_FILL_BYTE; + ((uint8_t *) pxNewTCB->pxStack)[3] = tskSTACK_FILL_BYTE; + ++k; + } +*/ + + } +#endif /* tskSET_NEW_STACKS_TO_KNOWN_VALUE */ + + /* Calculate the top of stack address. This depends on whether the stack + * grows from high memory to low (as per the 80x86) or vice versa. + * portSTACK_GROWTH is used to make the result positive or negative as required + * by the port. */ +#if (portSTACK_GROWTH < 0) + { + pxTopOfStack = &(pxNewTCB->pxStack[ulStackDepth - (uint32_t) 1]); + pxTopOfStack = (StackType_t *) (((portPOINTER_SIZE_TYPE) pxTopOfStack) & + (~((portPOINTER_SIZE_TYPE) portBYTE_ALIGNMENT_MASK))); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */ + + /* Check the alignment of the calculated top of stack is correct. */ + configASSERT((((portPOINTER_SIZE_TYPE) pxTopOfStack & (portPOINTER_SIZE_TYPE) portBYTE_ALIGNMENT_MASK) == 0UL)); + +#if (configRECORD_STACK_HIGH_ADDRESS == 1) + { + /* Also record the stack's high address, which may assist + * debugging. */ + pxNewTCB->pxEndOfStack = pxTopOfStack; + } +#endif /* configRECORD_STACK_HIGH_ADDRESS */ + } +#else /* portSTACK_GROWTH */ + { + pxTopOfStack = pxNewTCB->pxStack; + + /* Check the alignment of the stack buffer is correct. */ + configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxNewTCB->pxStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) ); + + /* The other extreme of the stack space is required if stack checking is + * performed. */ + pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 ); + } +#endif /* portSTACK_GROWTH */ + + /* Store the task name in the TCB. */ + if (pcName != NULL) { + for (x = (UBaseType_t) 0; x < (UBaseType_t) configMAX_TASK_NAME_LEN; x++) { + pxNewTCB->pcTaskName[x] = pcName[x]; + + /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than + * configMAX_TASK_NAME_LEN characters just in case the memory after the + * string is not accessible (extremely unlikely). */ + if (pcName[x] == (char) 0x00) { + break; + } else { + mtCOVERAGE_TEST_MARKER(); + } + } + + /* Ensure the name string is terminated in the case that the string length + * was greater or equal to configMAX_TASK_NAME_LEN. */ + pxNewTCB->pcTaskName[configMAX_TASK_NAME_LEN - 1] = '\0'; + } else { + /* The task has not been given a name, so just ensure there is a NULL + * terminator when it is read out. */ + pxNewTCB->pcTaskName[0] = 0x00; + } + + /* This is used as an array index so must ensure it's not too large. First + * remove the privilege bit if one is present. */ + if (uxPriority >= (UBaseType_t) configMAX_PRIORITIES) { + uxPriority = (UBaseType_t) configMAX_PRIORITIES - (UBaseType_t) 1U; + } else { + mtCOVERAGE_TEST_MARKER(); + } + + pxNewTCB->uxPriority = uxPriority; +#if (configUSE_MUTEXES == 1) + { + pxNewTCB->uxBasePriority = uxPriority; + pxNewTCB->uxMutexesHeld = 0; + } +#endif /* configUSE_MUTEXES */ + + vListInitialiseItem(&(pxNewTCB->xStateListItem)); + vListInitialiseItem(&(pxNewTCB->xEventListItem)); + + /* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get + * back to the containing TCB from a generic item in a list. */ + listSET_LIST_ITEM_OWNER(&(pxNewTCB->xStateListItem), pxNewTCB); + + /* Event lists are always in priority order. */ + listSET_LIST_ITEM_VALUE(&(pxNewTCB->xEventListItem), (TickType_t) configMAX_PRIORITIES - + (TickType_t) uxPriority); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + listSET_LIST_ITEM_OWNER(&(pxNewTCB->xEventListItem), pxNewTCB); + +#if (portCRITICAL_NESTING_IN_TCB == 1) + { + pxNewTCB->uxCriticalNesting = ( UBaseType_t ) 0U; + } +#endif /* portCRITICAL_NESTING_IN_TCB */ + +#if (configUSE_APPLICATION_TASK_TAG == 1) + { + pxNewTCB->pxTaskTag = NULL; + } +#endif /* configUSE_APPLICATION_TASK_TAG */ + +#if (configGENERATE_RUN_TIME_STATS == 1) + { + pxNewTCB->ulRunTimeCounter = 0UL; + } +#endif /* configGENERATE_RUN_TIME_STATS */ + +#if (portUSING_MPU_WRAPPERS == 1) + { + vPortStoreTaskMPUSettings( &( pxNewTCB->xMPUSettings ), xRegions, pxNewTCB->pxStack, ulStackDepth ); + } +#else + { + /* Avoid compiler warning about unreferenced parameter. */ + (void) xRegions; + } +#endif + +#if (configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0) + { + memset( ( void * ) &( pxNewTCB->pvThreadLocalStoragePointers[ 0 ] ), 0x00, sizeof( pxNewTCB->pvThreadLocalStoragePointers ) ); + } +#endif + +#if (configUSE_TASK_NOTIFICATIONS == 1) + { + memset((void *) &(pxNewTCB->ulNotifiedValue[0]), 0x00, sizeof(pxNewTCB->ulNotifiedValue)); + memset((void *) &(pxNewTCB->ucNotifyState[0]), 0x00, sizeof(pxNewTCB->ucNotifyState)); + } +#endif + +#if (configUSE_NEWLIB_REENTRANT == 1) + { + /* Initialise this task's Newlib reent structure. + * See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html + * for additional information. */ + _REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) ); + } +#endif + +#if (INCLUDE_xTaskAbortDelay == 1) + { + pxNewTCB->ucDelayAborted = pdFALSE; + } +#endif + + /* Initialize the TCB stack to look as if the task was already running, + * but had been interrupted by the scheduler. The return address is set + * to the start of the task function. Once the stack has been initialised + * the top of stack variable is updated. */ +#if (portUSING_MPU_WRAPPERS == 1) + { + /* If the port has capability to detect stack overflow, + * pass the stack end address to the stack initialization + * function as well. */ + #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 ) + { + #if ( portSTACK_GROWTH < 0 ) + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters, xRunPrivileged ); + } + #else /* portSTACK_GROWTH */ + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters, xRunPrivileged ); + } + #endif /* portSTACK_GROWTH */ + } + #else /* portHAS_STACK_OVERFLOW_CHECKING */ + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged ); + } + #endif /* portHAS_STACK_OVERFLOW_CHECKING */ + } +#else /* portUSING_MPU_WRAPPERS */ + { + /* If the port has capability to detect stack overflow, + * pass the stack end address to the stack initialization + * function as well. */ +#if (portHAS_STACK_OVERFLOW_CHECKING == 1) + { + #if ( portSTACK_GROWTH < 0 ) + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters ); + } + #else /* portSTACK_GROWTH */ + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters ); + } + #endif /* portSTACK_GROWTH */ + } +#else /* portHAS_STACK_OVERFLOW_CHECKING */ + { + pxNewTCB->pxTopOfStack = pxPortInitialiseStack(pxTopOfStack, pxTaskCode, pvParameters); + } +#endif /* portHAS_STACK_OVERFLOW_CHECKING */ + } +#endif /* portUSING_MPU_WRAPPERS */ + + if (pxCreatedTask != NULL) { + /* Pass the handle out in an anonymous way. The handle can be used to + * change the created task's priority, delete the created task, etc.*/ + *pxCreatedTask = (TaskHandle_t) pxNewTCB; + } else { + mtCOVERAGE_TEST_MARKER(); + } +} + +/*-----------------------------------------------------------*/ + +static void prvAddNewTaskToReadyList(TCB_t *pxNewTCB) { + /* Ensure interrupts don't access the task lists while the lists are being + * updated. */ + taskENTER_CRITICAL(); + { + uxCurrentNumberOfTasks++; + + if (pxCurrentTCB == NULL) { + /* There are no other tasks, or all the other tasks are in + * the suspended state - make this the current task. */ + pxCurrentTCB = pxNewTCB; + + if (uxCurrentNumberOfTasks == (UBaseType_t) 1) { + /* This is the first task to be created so do the preliminary + * initialisation required. We will not recover if this call + * fails, but we will report the failure. */ + prvInitialiseTaskLists(); + } else { + mtCOVERAGE_TEST_MARKER(); + } + } else { + /* If the scheduler is not already running, make this task the + * current task if it is the highest priority task to be created + * so far. */ + if (xSchedulerRunning == pdFALSE) { + if (pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority) { + pxCurrentTCB = pxNewTCB; + } else { + mtCOVERAGE_TEST_MARKER(); + } + } else { + mtCOVERAGE_TEST_MARKER(); + } + } + + uxTaskNumber++; + +#if (configUSE_TRACE_FACILITY == 1) + { + /* Add a counter into the TCB for tracing only. */ + pxNewTCB->uxTCBNumber = uxTaskNumber; + } +#endif /* configUSE_TRACE_FACILITY */ + traceTASK_CREATE(pxNewTCB); + + prvAddTaskToReadyList(pxNewTCB); + + portSETUP_TCB(pxNewTCB); + } + taskEXIT_CRITICAL(); + + if (xSchedulerRunning != pdFALSE) { + /* If the created task is of a higher priority than the current task + * then it should run now. */ + if (pxCurrentTCB->uxPriority < pxNewTCB->uxPriority) { + taskYIELD_IF_USING_PREEMPTION(); + } else { + mtCOVERAGE_TEST_MARKER(); + } + } else { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +#if (INCLUDE_vTaskDelete == 1) + +void vTaskDelete(TaskHandle_t xTaskToDelete) { + TCB_t *pxTCB; + + taskENTER_CRITICAL(); + { + /* If null is passed in here then it is the calling task that is + * being deleted. */ + pxTCB = prvGetTCBFromHandle(xTaskToDelete); + + /* Remove task from the ready/delayed list. */ + if (uxListRemove(&(pxTCB->xStateListItem)) == (UBaseType_t) 0) { + taskRESET_READY_PRIORITY(pxTCB->uxPriority); + } else { + mtCOVERAGE_TEST_MARKER(); + } + + /* Is the task waiting on an event also? */ + if (listLIST_ITEM_CONTAINER(&(pxTCB->xEventListItem)) != NULL) { + (void) uxListRemove(&(pxTCB->xEventListItem)); + } else { + mtCOVERAGE_TEST_MARKER(); + } + + /* Increment the uxTaskNumber also so kernel aware debuggers can + * detect that the task lists need re-generating. This is done before + * portPRE_TASK_DELETE_HOOK() as in the Windows port that macro will + * not return. */ + uxTaskNumber++; + + if (pxTCB == pxCurrentTCB) { + /* A task is deleting itself. This cannot complete within the + * task itself, as a context switch to another task is required. + * Place the task in the termination list. The idle task will + * check the termination list and free up any memory allocated by + * the scheduler for the TCB and stack of the deleted task. */ + vListInsertEnd(&xTasksWaitingTermination, &(pxTCB->xStateListItem)); + + /* Increment the ucTasksDeleted variable so the idle task knows + * there is a task that has been deleted and that it should therefore + * check the xTasksWaitingTermination list. */ + ++uxDeletedTasksWaitingCleanUp; + + /* Call the delete hook before portPRE_TASK_DELETE_HOOK() as + * portPRE_TASK_DELETE_HOOK() does not return in the Win32 port. */ + traceTASK_DELETE(pxTCB); + + /* The pre-delete hook is primarily for the Windows simulator, + * in which Windows specific clean up operations are performed, + * after which it is not possible to yield away from this task - + * hence xYieldPending is used to latch that a context switch is + * required. */ + portPRE_TASK_DELETE_HOOK(pxTCB, &xYieldPending); + } else { + --uxCurrentNumberOfTasks; + traceTASK_DELETE(pxTCB); + + /* Reset the next expected unblock time in case it referred to + * the task that has just been deleted. */ + prvResetNextTaskUnblockTime(); + } + } + taskEXIT_CRITICAL(); + + /* If the task is not deleting itself, call prvDeleteTCB from outside of + * critical section. If a task deletes itself, prvDeleteTCB is called + * from prvCheckTasksWaitingTermination which is called from Idle task. */ + if (pxTCB != pxCurrentTCB) { + prvDeleteTCB(pxTCB); + } + + /* Force a reschedule if it is the currently running task that has just + * been deleted. */ + if (xSchedulerRunning != pdFALSE) { + if (pxTCB == pxCurrentTCB) { + configASSERT(uxSchedulerSuspended == 0); + portYIELD_WITHIN_API(); + } else { + mtCOVERAGE_TEST_MARKER(); + } + } +} + +#endif /* INCLUDE_vTaskDelete */ +/*-----------------------------------------------------------*/ + +#if (INCLUDE_xTaskDelayUntil == 1) + +BaseType_t xTaskDelayUntil(TickType_t *const pxPreviousWakeTime, + const TickType_t xTimeIncrement) { + TickType_t xTimeToWake; + BaseType_t xAlreadyYielded, xShouldDelay = pdFALSE; + + configASSERT(pxPreviousWakeTime); + configASSERT((xTimeIncrement > 0U)); + configASSERT(uxSchedulerSuspended == 0); + + vTaskSuspendAll(); + { + /* Minor optimisation. The tick count cannot change in this + * block. */ + const TickType_t xConstTickCount = xTickCount; + + /* Generate the tick time at which the task wants to wake. */ + xTimeToWake = *pxPreviousWakeTime + xTimeIncrement; + + if (xConstTickCount < *pxPreviousWakeTime) { + /* The tick count has overflowed since this function was + * lasted called. In this case the only time we should ever + * actually delay is if the wake time has also overflowed, + * and the wake time is greater than the tick time. When this + * is the case it is as if neither time had overflowed. */ + if ((xTimeToWake < *pxPreviousWakeTime) && (xTimeToWake > xConstTickCount)) { + xShouldDelay = pdTRUE; + } else { + mtCOVERAGE_TEST_MARKER(); + } + } else { + /* The tick time has not overflowed. In this case we will + * delay if either the wake time has overflowed, and/or the + * tick time is less than the wake time. */ + if ((xTimeToWake < *pxPreviousWakeTime) || (xTimeToWake > xConstTickCount)) { + xShouldDelay = pdTRUE; + } else { + mtCOVERAGE_TEST_MARKER(); + } + } + + /* Update the wake time ready for the next call. */ + *pxPreviousWakeTime = xTimeToWake; + + if (xShouldDelay != pdFALSE) { + traceTASK_DELAY_UNTIL(xTimeToWake); + + /* prvAddCurrentTaskToDelayedList() needs the block time, not + * the time to wake, so subtract the current tick count. */ + prvAddCurrentTaskToDelayedList(xTimeToWake - xConstTickCount, pdFALSE); + } else { + mtCOVERAGE_TEST_MARKER(); + } + } + xAlreadyYielded = xTaskResumeAll(); + + /* Force a reschedule if xTaskResumeAll has not already done so, we may + * have put ourselves to sleep. */ + if (xAlreadyYielded == pdFALSE) { + portYIELD_WITHIN_API(); + } else { + mtCOVERAGE_TEST_MARKER(); + } + + return xShouldDelay; +} + +#endif /* INCLUDE_xTaskDelayUntil */ +/*-----------------------------------------------------------*/ + +#if (INCLUDE_vTaskDelay == 1) + +void vTaskDelay(const TickType_t xTicksToDelay) { + BaseType_t xAlreadyYielded = pdFALSE; + + /* A delay time of zero just forces a reschedule. */ + if (xTicksToDelay > (TickType_t) 0U) { + configASSERT(uxSchedulerSuspended == 0); + vTaskSuspendAll(); + { + traceTASK_DELAY(); + + /* A task that is removed from the event list while the + * scheduler is suspended will not get placed in the ready + * list or removed from the blocked list until the scheduler + * is resumed. + * + * This task cannot be in an event list as it is the currently + * executing task. */ + prvAddCurrentTaskToDelayedList(xTicksToDelay, pdFALSE); + } + xAlreadyYielded = xTaskResumeAll(); + } else { + mtCOVERAGE_TEST_MARKER(); + } + + /* Force a reschedule if xTaskResumeAll has not already done so, we may + * have put ourselves to sleep. */ + if (xAlreadyYielded == pdFALSE) { + portYIELD_WITHIN_API(); + } else { + mtCOVERAGE_TEST_MARKER(); + } +} + +#endif /* INCLUDE_vTaskDelay */ +/*-----------------------------------------------------------*/ + +#if ((INCLUDE_eTaskGetState == 1) || (configUSE_TRACE_FACILITY == 1) || (INCLUDE_xTaskAbortDelay == 1)) + +eTaskState eTaskGetState(TaskHandle_t xTask) { + eTaskState eReturn; + List_t const *pxStateList, *pxDelayedList, *pxOverflowedDelayedList; + const TCB_t *const pxTCB = xTask; + + configASSERT(pxTCB); + + if (pxTCB == pxCurrentTCB) { + /* The task calling this function is querying its own state. */ + eReturn = eRunning; + } else { + taskENTER_CRITICAL(); + { + pxStateList = listLIST_ITEM_CONTAINER(&(pxTCB->xStateListItem)); + pxDelayedList = pxDelayedTaskList; + pxOverflowedDelayedList = pxOverflowDelayedTaskList; + } + taskEXIT_CRITICAL(); + + if ((pxStateList == pxDelayedList) || (pxStateList == pxOverflowedDelayedList)) { + /* The task being queried is referenced from one of the Blocked + * lists. */ + eReturn = eBlocked; + } + +#if (INCLUDE_vTaskSuspend == 1) + else if (pxStateList == &xSuspendedTaskList) { + /* The task being queried is referenced from the suspended + * list. Is it genuinely suspended or is it blocked + * indefinitely? */ + if (listLIST_ITEM_CONTAINER(&(pxTCB->xEventListItem)) == NULL) { +#if (configUSE_TASK_NOTIFICATIONS == 1) + { + BaseType_t x; + + /* The task does not appear on the event list item of + * and of the RTOS objects, but could still be in the + * blocked state if it is waiting on its notification + * rather than waiting on an object. If not, is + * suspended. */ + eReturn = eSuspended; + + for (x = 0; x < configTASK_NOTIFICATION_ARRAY_ENTRIES; x++) { + if (pxTCB->ucNotifyState[x] == taskWAITING_NOTIFICATION) { + eReturn = eBlocked; + break; + } + } + } +#else /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ + { + eReturn = eSuspended; + } +#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ + } else { + eReturn = eBlocked; + } + } +#endif /* if ( INCLUDE_vTaskSuspend == 1 ) */ + +#if (INCLUDE_vTaskDelete == 1) + else if ((pxStateList == &xTasksWaitingTermination) || (pxStateList == NULL)) { + /* The task being queried is referenced from the deleted + * tasks list, or it is not referenced from any lists at + * all. */ + eReturn = eDeleted; + } +#endif + + else /*lint !e525 Negative indentation is intended to make use of pre-processor clearer. */ + { + /* If the task is not in any other state, it must be in the + * Ready (including pending ready) state. */ + eReturn = eReady; + } + } + + return eReturn; +} /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */ + +#endif /* INCLUDE_eTaskGetState */ +/*-----------------------------------------------------------*/ + +#if (INCLUDE_uxTaskPriorityGet == 1) + +UBaseType_t uxTaskPriorityGet(const TaskHandle_t xTask) { + TCB_t const *pxTCB; + UBaseType_t uxReturn; + + taskENTER_CRITICAL(); + { + /* If null is passed in here then it is the priority of the task + * that called uxTaskPriorityGet() that is being queried. */ + pxTCB = prvGetTCBFromHandle(xTask); + uxReturn = pxTCB->uxPriority; + } + taskEXIT_CRITICAL(); + + return uxReturn; +} + +#endif /* INCLUDE_uxTaskPriorityGet */ +/*-----------------------------------------------------------*/ + +#if (INCLUDE_uxTaskPriorityGet == 1) + +UBaseType_t uxTaskPriorityGetFromISR(const TaskHandle_t xTask) { + TCB_t const *pxTCB; + UBaseType_t uxReturn, uxSavedInterruptState; + + /* RTOS ports that support interrupt nesting have the concept of a + * maximum system call (or maximum API call) interrupt priority. + * Interrupts that are above the maximum system call priority are keep + * permanently enabled, even when the RTOS kernel is in a critical section, + * but cannot make any calls to FreeRTOS API functions. If configASSERT() + * is defined in FreeRTOSConfig.h then + * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has + * been assigned a priority above the configured maximum system call + * priority. Only FreeRTOS functions that end in FromISR can be called + * from interrupts that have been assigned a priority at or (logically) + * below the maximum system call interrupt priority. FreeRTOS maintains a + * separate interrupt safe API to ensure interrupt entry is as fast and as + * simple as possible. More information (albeit Cortex-M specific) is + * provided on the following link: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + uxSavedInterruptState = portSET_INTERRUPT_MASK_FROM_ISR(); + { + /* If null is passed in here then it is the priority of the calling + * task that is being queried. */ + pxTCB = prvGetTCBFromHandle(xTask); + uxReturn = pxTCB->uxPriority; + } + portCLEAR_INTERRUPT_MASK_FROM_ISR(uxSavedInterruptState); + + return uxReturn; +} + +#endif /* INCLUDE_uxTaskPriorityGet */ +/*-----------------------------------------------------------*/ + +#if (INCLUDE_vTaskPrioritySet == 1) + +void vTaskPrioritySet(TaskHandle_t xTask, + UBaseType_t uxNewPriority) { + TCB_t *pxTCB; + UBaseType_t uxCurrentBasePriority, uxPriorityUsedOnEntry; + BaseType_t xYieldRequired = pdFALSE; + + configASSERT((uxNewPriority < configMAX_PRIORITIES)); + + /* Ensure the new priority is valid. */ + if (uxNewPriority >= (UBaseType_t) configMAX_PRIORITIES) { + uxNewPriority = (UBaseType_t) configMAX_PRIORITIES - (UBaseType_t) 1U; + } else { + mtCOVERAGE_TEST_MARKER(); + } + + taskENTER_CRITICAL(); + { + /* If null is passed in here then it is the priority of the calling + * task that is being changed. */ + pxTCB = prvGetTCBFromHandle(xTask); + + traceTASK_PRIORITY_SET(pxTCB, uxNewPriority); + +#if (configUSE_MUTEXES == 1) + { + uxCurrentBasePriority = pxTCB->uxBasePriority; + } +#else + { + uxCurrentBasePriority = pxTCB->uxPriority; + } +#endif + + if (uxCurrentBasePriority != uxNewPriority) { + /* The priority change may have readied a task of higher + * priority than the calling task. */ + if (uxNewPriority > uxCurrentBasePriority) { + if (pxTCB != pxCurrentTCB) { + /* The priority of a task other than the currently + * running task is being raised. Is the priority being + * raised above that of the running task? */ + if (uxNewPriority >= pxCurrentTCB->uxPriority) { + xYieldRequired = pdTRUE; + } else { + mtCOVERAGE_TEST_MARKER(); + } + } else { + /* The priority of the running task is being raised, + * but the running task must already be the highest + * priority task able to run so no yield is required. */ + } + } else if (pxTCB == pxCurrentTCB) { + /* Setting the priority of the running task down means + * there may now be another task of higher priority that + * is ready to execute. */ + xYieldRequired = pdTRUE; + } else { + /* Setting the priority of any other task down does not + * require a yield as the running task must be above the + * new priority of the task being modified. */ + } + + /* Remember the ready list the task might be referenced from + * before its uxPriority member is changed so the + * taskRESET_READY_PRIORITY() macro can function correctly. */ + uxPriorityUsedOnEntry = pxTCB->uxPriority; + +#if (configUSE_MUTEXES == 1) + { + /* Only change the priority being used if the task is not + * currently using an inherited priority. */ + if (pxTCB->uxBasePriority == pxTCB->uxPriority) { + pxTCB->uxPriority = uxNewPriority; + } else { + mtCOVERAGE_TEST_MARKER(); + } + + /* The base priority gets set whatever. */ + pxTCB->uxBasePriority = uxNewPriority; + } +#else /* if ( configUSE_MUTEXES == 1 ) */ + { + pxTCB->uxPriority = uxNewPriority; + } +#endif /* if ( configUSE_MUTEXES == 1 ) */ + + /* Only reset the event list item value if the value is not + * being used for anything else. */ + if ((listGET_LIST_ITEM_VALUE(&(pxTCB->xEventListItem)) & taskEVENT_LIST_ITEM_VALUE_IN_USE) == 0UL) { + listSET_LIST_ITEM_VALUE(&(pxTCB->xEventListItem), ((TickType_t) configMAX_PRIORITIES - + (TickType_t) uxNewPriority)); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + } else { + mtCOVERAGE_TEST_MARKER(); + } + + /* If the task is in the blocked or suspended list we need do + * nothing more than change its priority variable. However, if + * the task is in a ready list it needs to be removed and placed + * in the list appropriate to its new priority. */ + if (listIS_CONTAINED_WITHIN(&(pxReadyTasksLists[uxPriorityUsedOnEntry]), &(pxTCB->xStateListItem)) != + pdFALSE) { + /* The task is currently in its ready list - remove before + * adding it to it's new ready list. As we are in a critical + * section we can do this even if the scheduler is suspended. */ + if (uxListRemove(&(pxTCB->xStateListItem)) == (UBaseType_t) 0) { + /* It is known that the task is in its ready list so + * there is no need to check again and the port level + * reset macro can be called directly. */ + portRESET_READY_PRIORITY(uxPriorityUsedOnEntry, uxTopReadyPriority); + } else { + mtCOVERAGE_TEST_MARKER(); + } + + prvAddTaskToReadyList(pxTCB); + } else { + mtCOVERAGE_TEST_MARKER(); + } + + if (xYieldRequired != pdFALSE) { + taskYIELD_IF_USING_PREEMPTION(); + } else { + mtCOVERAGE_TEST_MARKER(); + } + + /* Remove compiler warning about unused variables when the port + * optimised task selection is not being used. */ + (void) uxPriorityUsedOnEntry; + } + } + taskEXIT_CRITICAL(); +} + +#endif /* INCLUDE_vTaskPrioritySet */ +/*-----------------------------------------------------------*/ + +#if (INCLUDE_vTaskSuspend == 1) + +void vTaskSuspend(TaskHandle_t xTaskToSuspend) { + TCB_t *pxTCB; + + taskENTER_CRITICAL(); + { + /* If null is passed in here then it is the running task that is + * being suspended. */ + pxTCB = prvGetTCBFromHandle(xTaskToSuspend); + + traceTASK_SUSPEND(pxTCB); + + /* Remove task from the ready/delayed list and place in the + * suspended list. */ + if (uxListRemove(&(pxTCB->xStateListItem)) == (UBaseType_t) 0) { + taskRESET_READY_PRIORITY(pxTCB->uxPriority); + } else { + mtCOVERAGE_TEST_MARKER(); + } + + /* Is the task waiting on an event also? */ + if (listLIST_ITEM_CONTAINER(&(pxTCB->xEventListItem)) != NULL) { + (void) uxListRemove(&(pxTCB->xEventListItem)); + } else { + mtCOVERAGE_TEST_MARKER(); + } + + vListInsertEnd(&xSuspendedTaskList, &(pxTCB->xStateListItem)); + +#if (configUSE_TASK_NOTIFICATIONS == 1) + { + BaseType_t x; + + for (x = 0; x < configTASK_NOTIFICATION_ARRAY_ENTRIES; x++) { + if (pxTCB->ucNotifyState[x] == taskWAITING_NOTIFICATION) { + /* The task was blocked to wait for a notification, but is + * now suspended, so no notification was received. */ + pxTCB->ucNotifyState[x] = taskNOT_WAITING_NOTIFICATION; + } + } + } +#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */ + } + taskEXIT_CRITICAL(); + + if (xSchedulerRunning != pdFALSE) { + /* Reset the next expected unblock time in case it referred to the + * task that is now in the Suspended state. */ + taskENTER_CRITICAL(); + { + prvResetNextTaskUnblockTime(); + } + taskEXIT_CRITICAL(); + } else { + mtCOVERAGE_TEST_MARKER(); + } + + if (pxTCB == pxCurrentTCB) { + if (xSchedulerRunning != pdFALSE) { + /* The current task has just been suspended. */ + configASSERT(uxSchedulerSuspended == 0); + portYIELD_WITHIN_API(); + } else { + /* The scheduler is not running, but the task that was pointed + * to by pxCurrentTCB has just been suspended and pxCurrentTCB + * must be adjusted to point to a different task. */ + if (listCURRENT_LIST_LENGTH(&xSuspendedTaskList) == + uxCurrentNumberOfTasks) /*lint !e931 Right has no side effect, just volatile. */ + { + /* No other tasks are ready, so set pxCurrentTCB back to + * NULL so when the next task is created pxCurrentTCB will + * be set to point to it no matter what its relative priority + * is. */ + pxCurrentTCB = NULL; + } else { + vTaskSwitchContext(); + } + } + } else { + mtCOVERAGE_TEST_MARKER(); + } +} + +#endif /* INCLUDE_vTaskSuspend */ +/*-----------------------------------------------------------*/ + +#if (INCLUDE_vTaskSuspend == 1) + +static BaseType_t prvTaskIsTaskSuspended(const TaskHandle_t xTask) { + BaseType_t xReturn = pdFALSE; + const TCB_t *const pxTCB = xTask; + + /* Accesses xPendingReadyList so must be called from a critical + * section. */ + + /* It does not make sense to check if the calling task is suspended. */ + configASSERT(xTask); + + /* Is the task being resumed actually in the suspended list? */ + if (listIS_CONTAINED_WITHIN(&xSuspendedTaskList, &(pxTCB->xStateListItem)) != pdFALSE) { + /* Has the task already been resumed from within an ISR? */ + if (listIS_CONTAINED_WITHIN(&xPendingReadyList, &(pxTCB->xEventListItem)) == pdFALSE) { + /* Is it in the suspended list because it is in the Suspended + * state, or because is is blocked with no timeout? */ + if (listIS_CONTAINED_WITHIN(NULL, &(pxTCB->xEventListItem)) != + pdFALSE) /*lint !e961. The cast is only redundant when NULL is used. */ + { + xReturn = pdTRUE; + } else { + mtCOVERAGE_TEST_MARKER(); + } + } else { + mtCOVERAGE_TEST_MARKER(); + } + } else { + mtCOVERAGE_TEST_MARKER(); + } + + return xReturn; +} /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */ + +#endif /* INCLUDE_vTaskSuspend */ +/*-----------------------------------------------------------*/ + +#if (INCLUDE_vTaskSuspend == 1) + +void vTaskResume(TaskHandle_t xTaskToResume) { + TCB_t *const pxTCB = xTaskToResume; + + /* It does not make sense to resume the calling task. */ + configASSERT(xTaskToResume); + + /* The parameter cannot be NULL as it is impossible to resume the + * currently executing task. */ + if ((pxTCB != pxCurrentTCB) && (pxTCB != NULL)) { + taskENTER_CRITICAL(); + { + if (prvTaskIsTaskSuspended(pxTCB) != pdFALSE) { + traceTASK_RESUME(pxTCB); + + /* The ready list can be accessed even if the scheduler is + * suspended because this is inside a critical section. */ + (void) uxListRemove(&(pxTCB->xStateListItem));prvAddTaskToReadyList(pxTCB); + + /* A higher priority task may have just been resumed. */ + if (pxTCB->uxPriority >= pxCurrentTCB->uxPriority) { + /* This yield may not cause the task just resumed to run, + * but will leave the lists in the correct state for the + * next yield. */ + taskYIELD_IF_USING_PREEMPTION(); + } else { + mtCOVERAGE_TEST_MARKER(); + } + } else { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + } else { + mtCOVERAGE_TEST_MARKER(); + } +} + +#endif /* INCLUDE_vTaskSuspend */ + +/*-----------------------------------------------------------*/ + +#if ((INCLUDE_xTaskResumeFromISR == 1) && (INCLUDE_vTaskSuspend == 1)) + +BaseType_t xTaskResumeFromISR(TaskHandle_t xTaskToResume) { + BaseType_t xYieldRequired = pdFALSE; + TCB_t *const pxTCB = xTaskToResume; + UBaseType_t uxSavedInterruptStatus; + + configASSERT(xTaskToResume); + + /* RTOS ports that support interrupt nesting have the concept of a + * maximum system call (or maximum API call) interrupt priority. + * Interrupts that are above the maximum system call priority are keep + * permanently enabled, even when the RTOS kernel is in a critical section, + * but cannot make any calls to FreeRTOS API functions. If configASSERT() + * is defined in FreeRTOSConfig.h then + * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has + * been assigned a priority above the configured maximum system call + * priority. Only FreeRTOS functions that end in FromISR can be called + * from interrupts that have been assigned a priority at or (logically) + * below the maximum system call interrupt priority. FreeRTOS maintains a + * separate interrupt safe API to ensure interrupt entry is as fast and as + * simple as possible. More information (albeit Cortex-M specific) is + * provided on the following link: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + if (prvTaskIsTaskSuspended(pxTCB) != pdFALSE) { + traceTASK_RESUME_FROM_ISR(pxTCB); + + /* Check the ready lists can be accessed. */ + if (uxSchedulerSuspended == (UBaseType_t) pdFALSE) { + /* Ready lists can be accessed so move the task from the + * suspended list to the ready list directly. */ + if (pxTCB->uxPriority >= pxCurrentTCB->uxPriority) { + xYieldRequired = pdTRUE; + + /* Mark that a yield is pending in case the user is not + * using the return value to initiate a context switch + * from the ISR using portYIELD_FROM_ISR. */ + xYieldPending = pdTRUE; + } else { + mtCOVERAGE_TEST_MARKER(); + } + + (void) uxListRemove(&(pxTCB->xStateListItem));prvAddTaskToReadyList(pxTCB); + } else { + /* The delayed or ready lists cannot be accessed so the task + * is held in the pending ready list until the scheduler is + * unsuspended. */ + vListInsertEnd(&(xPendingReadyList), &(pxTCB->xEventListItem)); + } + } else { + mtCOVERAGE_TEST_MARKER(); + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR(uxSavedInterruptStatus); + + return xYieldRequired; +} + +#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */ + +/*-----------------------------------------------------------*/ + +void vTaskStartScheduler(void) { + BaseType_t xReturn; + + /* Add the idle task at the lowest priority. */ +#if (configSUPPORT_STATIC_ALLOCATION == 1) + { + StaticTask_t *pxIdleTaskTCBBuffer = NULL; + StackType_t *pxIdleTaskStackBuffer = NULL; + uint32_t ulIdleTaskStackSize; + + /* The Idle task is created using user provided RAM - obtain the + * address of the RAM then create the idle task. */ + vApplicationGetIdleTaskMemory(&pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize); + xIdleTaskHandle = xTaskCreateStatic(prvIdleTask, + configIDLE_TASK_NAME, + ulIdleTaskStackSize, + (void *) NULL, /*lint !e961. The cast is not redundant for all compilers. */ + portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */ + pxIdleTaskStackBuffer, + pxIdleTaskTCBBuffer); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */ + + if (xIdleTaskHandle != NULL) { + xReturn = pdPASS; + } else { + xReturn = pdFAIL; + } + } +#else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ + { + /* The Idle task is being created using dynamically allocated RAM. */ + xReturn = xTaskCreate( prvIdleTask, + configIDLE_TASK_NAME, + configMINIMAL_STACK_SIZE, + ( void * ) NULL, + portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */ + &xIdleTaskHandle ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */ + } +#endif /* configSUPPORT_STATIC_ALLOCATION */ + +#if (configUSE_TIMERS == 1) + { + if (xReturn == pdPASS) { + xReturn = xTimerCreateTimerTask(); + } else { + mtCOVERAGE_TEST_MARKER(); + } + } +#endif /* configUSE_TIMERS */ + + if (xReturn == pdPASS) { + /* freertos_tasks_c_additions_init() should only be called if the user + * definable macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is + * the only macro called by the function. */ +#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT + { + freertos_tasks_c_additions_init(); + } +#endif + + /* Interrupts are turned off here, to ensure a tick does not occur + * before or during the call to xPortStartScheduler(). The stacks of + * the created tasks contain a status word with interrupts switched on + * so interrupts will automatically get re-enabled when the first task + * starts to run. */ + portDISABLE_INTERRUPTS(); + +#if (configUSE_NEWLIB_REENTRANT == 1) + { + /* Switch Newlib's _impure_ptr variable to point to the _reent + * structure specific to the task that will run first. + * See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html + * for additional information. */ + _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); + } +#endif /* configUSE_NEWLIB_REENTRANT */ + + xNextTaskUnblockTime = portMAX_DELAY; + xSchedulerRunning = pdTRUE; + xTickCount = (TickType_t) configINITIAL_TICK_COUNT; + + /* If configGENERATE_RUN_TIME_STATS is defined then the following + * macro must be defined to configure the timer/counter used to generate + * the run time counter time base. NOTE: If configGENERATE_RUN_TIME_STATS + * is set to 0 and the following line fails to build then ensure you do not + * have portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() defined in your + * FreeRTOSConfig.h file. */ + portCONFIGURE_TIMER_FOR_RUN_TIME_STATS(); + + traceTASK_SWITCHED_IN(); + + /* Setting up the timer tick is hardware specific and thus in the + * portable interface. */ + if (xPortStartScheduler() != pdFALSE) { + /* Should not reach here as if the scheduler is running the + * function will not return. */ + } else { + /* Should only reach here if a task calls xTaskEndScheduler(). */ + } + } else { + /* This line will only be reached if the kernel could not be started, + * because there was not enough FreeRTOS heap to create the idle task + * or the timer task. */ + configASSERT(xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY); + } + + /* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0, + * meaning xIdleTaskHandle is not used anywhere else. */ + (void) xIdleTaskHandle; + + /* OpenOCD makes use of uxTopUsedPriority for thread debugging. Prevent uxTopUsedPriority + * from getting optimized out as it is no longer used by the kernel. */ + (void) uxTopUsedPriority; +} + +/*-----------------------------------------------------------*/ + +void vTaskEndScheduler(void) { + /* Stop the scheduler interrupts and call the portable scheduler end + * routine so the original ISRs can be restored if necessary. The port + * layer must ensure interrupts enable bit is left in the correct state. */ + portDISABLE_INTERRUPTS(); + xSchedulerRunning = pdFALSE; + vPortEndScheduler(); +} + +/*----------------------------------------------------------*/ + +void vTaskSuspendAll(void) { + /* A critical section is not required as the variable is of type + * BaseType_t. Please read Richard Barry's reply in the following link to a + * post in the FreeRTOS support forum before reporting this as a bug! - + * https://goo.gl/wu4acr */ + + /* portSOFRWARE_BARRIER() is only implemented for emulated/simulated ports that + * do not otherwise exhibit real time behaviour. */ + portSOFTWARE_BARRIER(); + + /* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment + * is used to allow calls to vTaskSuspendAll() to nest. */ + ++uxSchedulerSuspended; + + /* Enforces ordering for ports and optimised compilers that may otherwise place + * the above increment elsewhere. */ + portMEMORY_BARRIER(); +} +/*----------------------------------------------------------*/ + +#if (configUSE_TICKLESS_IDLE != 0) + + static TickType_t prvGetExpectedIdleTime( void ) + { + TickType_t xReturn; + UBaseType_t uxHigherPriorityReadyTasks = pdFALSE; + + /* uxHigherPriorityReadyTasks takes care of the case where + * configUSE_PREEMPTION is 0, so there may be tasks above the idle priority + * task that are in the Ready state, even though the idle task is + * running. */ + #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 ) + { + if( uxTopReadyPriority > tskIDLE_PRIORITY ) + { + uxHigherPriorityReadyTasks = pdTRUE; + } + } + #else + { + const UBaseType_t uxLeastSignificantBit = ( UBaseType_t ) 0x01; + + /* When port optimised task selection is used the uxTopReadyPriority + * variable is used as a bit map. If bits other than the least + * significant bit are set then there are tasks that have a priority + * above the idle priority that are in the Ready state. This takes + * care of the case where the co-operative scheduler is in use. */ + if( uxTopReadyPriority > uxLeastSignificantBit ) + { + uxHigherPriorityReadyTasks = pdTRUE; + } + } + #endif /* if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 ) */ + + if( pxCurrentTCB->uxPriority > tskIDLE_PRIORITY ) + { + xReturn = 0; + } + else if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1 ) + { + /* There are other idle priority tasks in the ready state. If + * time slicing is used then the very next tick interrupt must be + * processed. */ + xReturn = 0; + } + else if( uxHigherPriorityReadyTasks != pdFALSE ) + { + /* There are tasks in the Ready state that have a priority above the + * idle priority. This path can only be reached if + * configUSE_PREEMPTION is 0. */ + xReturn = 0; + } + else + { + xReturn = xNextTaskUnblockTime - xTickCount; + } + + return xReturn; + } + +#endif /* configUSE_TICKLESS_IDLE */ + +/*----------------------------------------------------------*/ + +BaseType_t xTaskResumeAll(void) { + TCB_t *pxTCB = NULL; + BaseType_t xAlreadyYielded = pdFALSE; + + /* If uxSchedulerSuspended is zero then this function does not match a + * previous call to vTaskSuspendAll(). */ + configASSERT(uxSchedulerSuspended); + + /* It is possible that an ISR caused a task to be removed from an event + * list while the scheduler was suspended. If this was the case then the + * removed task will have been added to the xPendingReadyList. Once the + * scheduler has been resumed it is safe to move all the pending ready + * tasks from this list into their appropriate ready list. */ + taskENTER_CRITICAL(); + { + --uxSchedulerSuspended; + + if (uxSchedulerSuspended == (UBaseType_t) pdFALSE) { + if (uxCurrentNumberOfTasks > (UBaseType_t) 0U) { + /* Move any readied tasks from the pending list into the + * appropriate ready list. */ + while (listLIST_IS_EMPTY(&xPendingReadyList) == pdFALSE) { + pxTCB = listGET_OWNER_OF_HEAD_ENTRY( + (&xPendingReadyList)); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + (void) uxListRemove(&(pxTCB->xEventListItem)); + (void) uxListRemove(&(pxTCB->xStateListItem));prvAddTaskToReadyList(pxTCB); + + /* If the moved task has a priority higher than the current + * task then a yield must be performed. */ + if (pxTCB->uxPriority >= pxCurrentTCB->uxPriority) { + xYieldPending = pdTRUE; + } else { + mtCOVERAGE_TEST_MARKER(); + } + } + + if (pxTCB != NULL) { + /* A task was unblocked while the scheduler was suspended, + * which may have prevented the next unblock time from being + * re-calculated, in which case re-calculate it now. Mainly + * important for low power tickless implementations, where + * this can prevent an unnecessary exit from low power + * state. */ + prvResetNextTaskUnblockTime(); + } + + /* If any ticks occurred while the scheduler was suspended then + * they should be processed now. This ensures the tick count does + * not slip, and that any delayed tasks are resumed at the correct + * time. */ + { + TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */ + + if (xPendedCounts > (TickType_t) 0U) { + do { + if (xTaskIncrementTick() != pdFALSE) { + xYieldPending = pdTRUE; + } else { + mtCOVERAGE_TEST_MARKER(); + } + + --xPendedCounts; + } while (xPendedCounts > (TickType_t) 0U); + + xPendedTicks = 0; + } else { + mtCOVERAGE_TEST_MARKER(); + } + } + + if (xYieldPending != pdFALSE) { +#if (configUSE_PREEMPTION != 0) + { + xAlreadyYielded = pdTRUE; + } +#endif + taskYIELD_IF_USING_PREEMPTION(); + } else { + mtCOVERAGE_TEST_MARKER(); + } + } + } else { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + return xAlreadyYielded; +} + +/*-----------------------------------------------------------*/ + +TickType_t xTaskGetTickCount(void) { + TickType_t xTicks; + + /* Critical section required if running on a 16 bit processor. */ + portTICK_TYPE_ENTER_CRITICAL(); + { + xTicks = xTickCount; + } + portTICK_TYPE_EXIT_CRITICAL(); + + return xTicks; +} + +/*-----------------------------------------------------------*/ + +TickType_t xTaskGetTickCountFromISR(void) { + TickType_t xReturn; + UBaseType_t uxSavedInterruptStatus; + + /* RTOS ports that support interrupt nesting have the concept of a maximum + * system call (or maximum API call) interrupt priority. Interrupts that are + * above the maximum system call priority are kept permanently enabled, even + * when the RTOS kernel is in a critical section, but cannot make any calls to + * FreeRTOS API functions. If configASSERT() is defined in FreeRTOSConfig.h + * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has been + * assigned a priority above the configured maximum system call priority. + * Only FreeRTOS functions that end in FromISR can be called from interrupts + * that have been assigned a priority at or (logically) below the maximum + * system call interrupt priority. FreeRTOS maintains a separate interrupt + * safe API to ensure interrupt entry is as fast and as simple as possible. + * More information (albeit Cortex-M specific) is provided on the following + * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR(); + { + xReturn = xTickCount; + } + portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR(uxSavedInterruptStatus); + + return xReturn; +} + +/*-----------------------------------------------------------*/ + +UBaseType_t uxTaskGetNumberOfTasks(void) { + /* A critical section is not required because the variables are of type + * BaseType_t. */ + return uxCurrentNumberOfTasks; +} + +/*-----------------------------------------------------------*/ + +char *pcTaskGetName( + TaskHandle_t xTaskToQuery) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ +{ + TCB_t *pxTCB; + + /* If null is passed in here then the name of the calling task is being + * queried. */ + pxTCB = prvGetTCBFromHandle(xTaskToQuery); + configASSERT(pxTCB); + return &(pxTCB->pcTaskName[0]); +} +/*-----------------------------------------------------------*/ + +#if (INCLUDE_xTaskGetHandle == 1) + + static TCB_t * prvSearchForNameWithinSingleList( List_t * pxList, + const char pcNameToQuery[] ) + { + TCB_t * pxNextTCB, * pxFirstTCB, * pxReturn = NULL; + UBaseType_t x; + char cNextChar; + BaseType_t xBreakLoop; + + /* This function is called with the scheduler suspended. */ + + if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 ) + { + listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + + do + { + listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + + /* Check each character in the name looking for a match or + * mismatch. */ + xBreakLoop = pdFALSE; + + for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) + { + cNextChar = pxNextTCB->pcTaskName[ x ]; + + if( cNextChar != pcNameToQuery[ x ] ) + { + /* Characters didn't match. */ + xBreakLoop = pdTRUE; + } + else if( cNextChar == ( char ) 0x00 ) + { + /* Both strings terminated, a match must have been + * found. */ + pxReturn = pxNextTCB; + xBreakLoop = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + if( xBreakLoop != pdFALSE ) + { + break; + } + } + + if( pxReturn != NULL ) + { + /* The handle has been found. */ + break; + } + } while( pxNextTCB != pxFirstTCB ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return pxReturn; + } + +#endif /* INCLUDE_xTaskGetHandle */ +/*-----------------------------------------------------------*/ + +#if (INCLUDE_xTaskGetHandle == 1) + + TaskHandle_t xTaskGetHandle( const char * pcNameToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + { + UBaseType_t uxQueue = configMAX_PRIORITIES; + TCB_t * pxTCB; + + /* Task names will be truncated to configMAX_TASK_NAME_LEN - 1 bytes. */ + configASSERT( strlen( pcNameToQuery ) < configMAX_TASK_NAME_LEN ); + + vTaskSuspendAll(); + { + /* Search the ready lists. */ + do + { + uxQueue--; + pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) &( pxReadyTasksLists[ uxQueue ] ), pcNameToQuery ); + + if( pxTCB != NULL ) + { + /* Found the handle. */ + break; + } + } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + + /* Search the delayed lists. */ + if( pxTCB == NULL ) + { + pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxDelayedTaskList, pcNameToQuery ); + } + + if( pxTCB == NULL ) + { + pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxOverflowDelayedTaskList, pcNameToQuery ); + } + + #if ( INCLUDE_vTaskSuspend == 1 ) + { + if( pxTCB == NULL ) + { + /* Search the suspended list. */ + pxTCB = prvSearchForNameWithinSingleList( &xSuspendedTaskList, pcNameToQuery ); + } + } + #endif + + #if ( INCLUDE_vTaskDelete == 1 ) + { + if( pxTCB == NULL ) + { + /* Search the deleted list. */ + pxTCB = prvSearchForNameWithinSingleList( &xTasksWaitingTermination, pcNameToQuery ); + } + } + #endif + } + ( void ) xTaskResumeAll(); + + return pxTCB; + } + +#endif /* INCLUDE_xTaskGetHandle */ +/*-----------------------------------------------------------*/ + +#if (configUSE_TRACE_FACILITY == 1) + +UBaseType_t uxTaskGetSystemState(TaskStatus_t *const pxTaskStatusArray, + const UBaseType_t uxArraySize, + uint32_t *const pulTotalRunTime) { + UBaseType_t uxTask = 0, uxQueue = configMAX_PRIORITIES; + + vTaskSuspendAll(); + { + /* Is there a space in the array for each task in the system? */ + if (uxArraySize >= uxCurrentNumberOfTasks) { + /* Fill in an TaskStatus_t structure with information on each + * task in the Ready state. */ + do { + uxQueue--; + uxTask += prvListTasksWithinSingleList(&(pxTaskStatusArray[uxTask]), &(pxReadyTasksLists[uxQueue]), + eReady); + } while (uxQueue > + (UBaseType_t) tskIDLE_PRIORITY); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + + /* Fill in an TaskStatus_t structure with information on each + * task in the Blocked state. */ + uxTask += prvListTasksWithinSingleList(&(pxTaskStatusArray[uxTask]), (List_t *) pxDelayedTaskList, + eBlocked); + uxTask += prvListTasksWithinSingleList(&(pxTaskStatusArray[uxTask]), (List_t *) pxOverflowDelayedTaskList, + eBlocked); + +#if (INCLUDE_vTaskDelete == 1) + { + /* Fill in an TaskStatus_t structure with information on + * each task that has been deleted but not yet cleaned up. */ + uxTask += prvListTasksWithinSingleList(&(pxTaskStatusArray[uxTask]), &xTasksWaitingTermination, + eDeleted); + } +#endif + +#if (INCLUDE_vTaskSuspend == 1) + { + /* Fill in an TaskStatus_t structure with information on + * each task in the Suspended state. */ + uxTask += prvListTasksWithinSingleList(&(pxTaskStatusArray[uxTask]), &xSuspendedTaskList, eSuspended); + } +#endif + +#if (configGENERATE_RUN_TIME_STATS == 1) + { + if( pulTotalRunTime != NULL ) + { + #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE + portALT_GET_RUN_TIME_COUNTER_VALUE( ( *pulTotalRunTime ) ); + #else + *pulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE(); + #endif + } + } +#else /* if ( configGENERATE_RUN_TIME_STATS == 1 ) */ + { + if (pulTotalRunTime != NULL) { + *pulTotalRunTime = 0; + } + } +#endif /* if ( configGENERATE_RUN_TIME_STATS == 1 ) */ + } else { + mtCOVERAGE_TEST_MARKER(); + } + } + (void) xTaskResumeAll(); + + return uxTask; +} + +#endif /* configUSE_TRACE_FACILITY */ +/*----------------------------------------------------------*/ + +#if (INCLUDE_xTaskGetIdleTaskHandle == 1) + + TaskHandle_t xTaskGetIdleTaskHandle( void ) + { + /* If xTaskGetIdleTaskHandle() is called before the scheduler has been + * started, then xIdleTaskHandle will be NULL. */ + configASSERT( ( xIdleTaskHandle != NULL ) ); + return xIdleTaskHandle; + } + +#endif /* INCLUDE_xTaskGetIdleTaskHandle */ +/*----------------------------------------------------------*/ + +/* This conditional compilation should use inequality to 0, not equality to 1. + * This is to ensure vTaskStepTick() is available when user defined low power mode + * implementations require configUSE_TICKLESS_IDLE to be set to a value other than + * 1. */ +#if (configUSE_TICKLESS_IDLE != 0) + + void vTaskStepTick( const TickType_t xTicksToJump ) + { + /* Correct the tick count value after a period during which the tick + * was suppressed. Note this does *not* call the tick hook function for + * each stepped tick. */ + configASSERT( ( xTickCount + xTicksToJump ) <= xNextTaskUnblockTime ); + xTickCount += xTicksToJump; + traceINCREASE_TICK_COUNT( xTicksToJump ); + } + +#endif /* configUSE_TICKLESS_IDLE */ + +/*----------------------------------------------------------*/ + +BaseType_t xTaskCatchUpTicks(TickType_t xTicksToCatchUp) { + BaseType_t xYieldOccurred; + + /* Must not be called with the scheduler suspended as the implementation + * relies on xPendedTicks being wound down to 0 in xTaskResumeAll(). */ + configASSERT(uxSchedulerSuspended == 0); + + /* Use xPendedTicks to mimic xTicksToCatchUp number of ticks occurring when + * the scheduler is suspended so the ticks are executed in xTaskResumeAll(). */ + vTaskSuspendAll(); + xPendedTicks += xTicksToCatchUp; + xYieldOccurred = xTaskResumeAll(); + + return xYieldOccurred; +} +/*----------------------------------------------------------*/ + +#if (INCLUDE_xTaskAbortDelay == 1) + + BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) + { + TCB_t * pxTCB = xTask; + BaseType_t xReturn; + + configASSERT( pxTCB ); + + vTaskSuspendAll(); + { + /* A task can only be prematurely removed from the Blocked state if + * it is actually in the Blocked state. */ + if( eTaskGetState( xTask ) == eBlocked ) + { + xReturn = pdPASS; + + /* Remove the reference to the task from the blocked list. An + * interrupt won't touch the xStateListItem because the + * scheduler is suspended. */ + ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); + + /* Is the task waiting on an event also? If so remove it from + * the event list too. Interrupts can touch the event list item, + * even though the scheduler is suspended, so a critical section + * is used. */ + taskENTER_CRITICAL(); + { + if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) + { + ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); + + /* This lets the task know it was forcibly removed from the + * blocked state so it should not re-evaluate its block time and + * then block again. */ + pxTCB->ucDelayAborted = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + /* Place the unblocked task into the appropriate ready list. */ + prvAddTaskToReadyList( pxTCB ); + + /* A task being unblocked cannot cause an immediate context + * switch if preemption is turned off. */ + #if ( configUSE_PREEMPTION == 1 ) + { + /* Preemption is on, but a context switch should only be + * performed if the unblocked task has a priority that is + * equal to or higher than the currently executing task. */ + if( pxTCB->uxPriority > pxCurrentTCB->uxPriority ) + { + /* Pend the yield to be performed when the scheduler + * is unsuspended. */ + xYieldPending = pdTRUE; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configUSE_PREEMPTION */ + } + else + { + xReturn = pdFAIL; + } + } + ( void ) xTaskResumeAll(); + + return xReturn; + } + +#endif /* INCLUDE_xTaskAbortDelay */ + +/*----------------------------------------------------------*/ + +BaseType_t xTaskIncrementTick(void) { + TCB_t *pxTCB; + TickType_t xItemValue; + BaseType_t xSwitchRequired = pdFALSE; + + /* Called by the portable layer each time a tick interrupt occurs. + * Increments the tick then checks to see if the new tick value will cause any + * tasks to be unblocked. */ + traceTASK_INCREMENT_TICK(xTickCount); + + if (uxSchedulerSuspended == (UBaseType_t) pdFALSE) { + /* Minor optimisation. The tick count cannot change in this + * block. */ + const TickType_t xConstTickCount = xTickCount + (TickType_t) 1; + + /* Increment the RTOS tick, switching the delayed and overflowed + * delayed lists if it wraps to 0. */ + xTickCount = xConstTickCount; + + if (xConstTickCount == + (TickType_t) 0U) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */ + { + taskSWITCH_DELAYED_LISTS(); + } else { + mtCOVERAGE_TEST_MARKER(); + } + + /* See if this tick has made a timeout expire. Tasks are stored in + * the queue in the order of their wake time - meaning once one task + * has been found whose block time has not expired there is no need to + * look any further down the list. */ + if (xConstTickCount >= xNextTaskUnblockTime) { + for (;;) { + if (listLIST_IS_EMPTY(pxDelayedTaskList) != pdFALSE) { + /* The delayed list is empty. Set xNextTaskUnblockTime + * to the maximum possible value so it is extremely + * unlikely that the + * if( xTickCount >= xNextTaskUnblockTime ) test will pass + * next time through. */ + xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + break; + } else { + /* The delayed list is not empty, get the value of the + * item at the head of the delayed list. This is the time + * at which the task at the head of the delayed list must + * be removed from the Blocked state. */ + pxTCB = listGET_OWNER_OF_HEAD_ENTRY( + pxDelayedTaskList); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + xItemValue = listGET_LIST_ITEM_VALUE(&(pxTCB->xStateListItem)); + + if (xConstTickCount < xItemValue) { + /* It is not time to unblock this item yet, but the + * item value is the time at which the task at the head + * of the blocked list must be removed from the Blocked + * state - so record the item value in + * xNextTaskUnblockTime. */ + xNextTaskUnblockTime = xItemValue; + break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */ + } else { + mtCOVERAGE_TEST_MARKER(); + } + + /* It is time to remove the item from the Blocked state. */ + (void) uxListRemove(&(pxTCB->xStateListItem)); + + /* Is the task waiting on an event also? If so remove + * it from the event list. */ + if (listLIST_ITEM_CONTAINER(&(pxTCB->xEventListItem)) != NULL) { + (void) uxListRemove(&(pxTCB->xEventListItem)); + } else { + mtCOVERAGE_TEST_MARKER(); + } + + /* Place the unblocked task into the appropriate ready + * list. */ + prvAddTaskToReadyList(pxTCB); + + /* A task being unblocked cannot cause an immediate + * context switch if preemption is turned off. */ +#if (configUSE_PREEMPTION == 1) + { + /* Preemption is on, but a context switch should + * only be performed if the unblocked task has a + * priority that is equal to or higher than the + * currently executing task. */ + if (pxTCB->uxPriority >= pxCurrentTCB->uxPriority) { + xSwitchRequired = pdTRUE; + } else { + mtCOVERAGE_TEST_MARKER(); + } + } +#endif /* configUSE_PREEMPTION */ + } + } + } + + /* Tasks of equal priority to the currently running task will share + * processing time (time slice) if preemption is on, and the application + * writer has not explicitly turned time slicing off. */ +#if ((configUSE_PREEMPTION == 1) && (configUSE_TIME_SLICING == 1)) + { + if (listCURRENT_LIST_LENGTH(&(pxReadyTasksLists[pxCurrentTCB->uxPriority])) > (UBaseType_t) 1) { + xSwitchRequired = pdTRUE; + } else { + mtCOVERAGE_TEST_MARKER(); + } + } +#endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */ + +#if (configUSE_TICK_HOOK == 1) + { + /* Guard against the tick hook being called when the pended tick + * count is being unwound (when the scheduler is being unlocked). */ + if( xPendedTicks == ( TickType_t ) 0 ) + { + vApplicationTickHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +#endif /* configUSE_TICK_HOOK */ + +#if (configUSE_PREEMPTION == 1) + { + if (xYieldPending != pdFALSE) { + xSwitchRequired = pdTRUE; + } else { + mtCOVERAGE_TEST_MARKER(); + } + } +#endif /* configUSE_PREEMPTION */ + } else { + ++xPendedTicks; + + /* The tick hook gets called at regular intervals, even if the + * scheduler is locked. */ +#if (configUSE_TICK_HOOK == 1) + { + vApplicationTickHook(); + } +#endif + } + + return xSwitchRequired; +} +/*-----------------------------------------------------------*/ + +#if (configUSE_APPLICATION_TASK_TAG == 1) + + void vTaskSetApplicationTaskTag( TaskHandle_t xTask, + TaskHookFunction_t pxHookFunction ) + { + TCB_t * xTCB; + + /* If xTask is NULL then it is the task hook of the calling task that is + * getting set. */ + if( xTask == NULL ) + { + xTCB = ( TCB_t * ) pxCurrentTCB; + } + else + { + xTCB = xTask; + } + + /* Save the hook function in the TCB. A critical section is required as + * the value can be accessed from an interrupt. */ + taskENTER_CRITICAL(); + { + xTCB->pxTaskTag = pxHookFunction; + } + taskEXIT_CRITICAL(); + } + +#endif /* configUSE_APPLICATION_TASK_TAG */ +/*-----------------------------------------------------------*/ + +#if (configUSE_APPLICATION_TASK_TAG == 1) + + TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) + { + TCB_t * pxTCB; + TaskHookFunction_t xReturn; + + /* If xTask is NULL then set the calling task's hook. */ + pxTCB = prvGetTCBFromHandle( xTask ); + + /* Save the hook function in the TCB. A critical section is required as + * the value can be accessed from an interrupt. */ + taskENTER_CRITICAL(); + { + xReturn = pxTCB->pxTaskTag; + } + taskEXIT_CRITICAL(); + + return xReturn; + } + +#endif /* configUSE_APPLICATION_TASK_TAG */ +/*-----------------------------------------------------------*/ + +#if (configUSE_APPLICATION_TASK_TAG == 1) + + TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) + { + TCB_t * pxTCB; + TaskHookFunction_t xReturn; + UBaseType_t uxSavedInterruptStatus; + + /* If xTask is NULL then set the calling task's hook. */ + pxTCB = prvGetTCBFromHandle( xTask ); + + /* Save the hook function in the TCB. A critical section is required as + * the value can be accessed from an interrupt. */ + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + xReturn = pxTCB->pxTaskTag; + } + portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); + + return xReturn; + } + +#endif /* configUSE_APPLICATION_TASK_TAG */ +/*-----------------------------------------------------------*/ + +#if (configUSE_APPLICATION_TASK_TAG == 1) + + BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, + void * pvParameter ) + { + TCB_t * xTCB; + BaseType_t xReturn; + + /* If xTask is NULL then we are calling our own task hook. */ + if( xTask == NULL ) + { + xTCB = pxCurrentTCB; + } + else + { + xTCB = xTask; + } + + if( xTCB->pxTaskTag != NULL ) + { + xReturn = xTCB->pxTaskTag( pvParameter ); + } + else + { + xReturn = pdFAIL; + } + + return xReturn; + } + +#endif /* configUSE_APPLICATION_TASK_TAG */ + +/*-----------------------------------------------------------*/ + +void vTaskSwitchContext(void) { + if (uxSchedulerSuspended != (UBaseType_t) pdFALSE) { + /* The scheduler is currently suspended - do not allow a context + * switch. */ + xYieldPending = pdTRUE; + } else { + xYieldPending = pdFALSE; + traceTASK_SWITCHED_OUT(); + +#if (configGENERATE_RUN_TIME_STATS == 1) + { + #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE + portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime ); + #else + ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE(); + #endif + + /* Add the amount of time the task has been running to the + * accumulated time so far. The time the task started running was + * stored in ulTaskSwitchedInTime. Note that there is no overflow + * protection here so count values are only valid until the timer + * overflows. The guard against negative values is to protect + * against suspect run time stat counter implementations - which + * are provided by the application, not the kernel. */ + if( ulTotalRunTime > ulTaskSwitchedInTime ) + { + pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + ulTaskSwitchedInTime = ulTotalRunTime; + } +#endif /* configGENERATE_RUN_TIME_STATS */ + + /* Check for stack overflow, if configured. */ + taskCHECK_FOR_STACK_OVERFLOW(); + + /* Before the currently running task is switched out, save its errno. */ +#if (configUSE_POSIX_ERRNO == 1) + { + pxCurrentTCB->iTaskErrno = FreeRTOS_errno; + } +#endif + + /* Select a new task to run using either the generic C or port + * optimised asm code. */ + taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + traceTASK_SWITCHED_IN(); + + /* After the new task is switched in, update the global errno. */ +#if (configUSE_POSIX_ERRNO == 1) + { + FreeRTOS_errno = pxCurrentTCB->iTaskErrno; + } +#endif + +#if (configUSE_NEWLIB_REENTRANT == 1) + { + /* Switch Newlib's _impure_ptr variable to point to the _reent + * structure specific to this task. + * See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html + * for additional information. */ + _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); + } +#endif /* configUSE_NEWLIB_REENTRANT */ + } +} + +/*-----------------------------------------------------------*/ + +void vTaskPlaceOnEventList(List_t *const pxEventList, + const TickType_t xTicksToWait) { + configASSERT(pxEventList); + + /* THIS FUNCTION MUST BE CALLED WITH EITHER INTERRUPTS DISABLED OR THE + * SCHEDULER SUSPENDED AND THE QUEUE BEING ACCESSED LOCKED. */ + + /* Place the event list item of the TCB in the appropriate event list. + * This is placed in the list in priority order so the highest priority task + * is the first to be woken by the event. The queue that contains the event + * list is locked, preventing simultaneous access from interrupts. */ + vListInsert(pxEventList, &(pxCurrentTCB->xEventListItem)); + + prvAddCurrentTaskToDelayedList(xTicksToWait, pdTRUE); +} + +/*-----------------------------------------------------------*/ + +void vTaskPlaceOnUnorderedEventList(List_t *pxEventList, + const TickType_t xItemValue, + const TickType_t xTicksToWait) { + configASSERT(pxEventList); + + /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. It is used by + * the event groups implementation. */ + configASSERT(uxSchedulerSuspended != 0); + + /* Store the item value in the event list item. It is safe to access the + * event list item here as interrupts won't access the event list item of a + * task that is not in the Blocked state. */ + listSET_LIST_ITEM_VALUE(&(pxCurrentTCB->xEventListItem), xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE); + + /* Place the event list item of the TCB at the end of the appropriate event + * list. It is safe to access the event list here because it is part of an + * event group implementation - and interrupts don't access event groups + * directly (instead they access them indirectly by pending function calls to + * the task level). */ + vListInsertEnd(pxEventList, &(pxCurrentTCB->xEventListItem)); + + prvAddCurrentTaskToDelayedList(xTicksToWait, pdTRUE); +} +/*-----------------------------------------------------------*/ + +#if (configUSE_TIMERS == 1) + +void vTaskPlaceOnEventListRestricted(List_t *const pxEventList, + TickType_t xTicksToWait, + const BaseType_t xWaitIndefinitely) { + configASSERT(pxEventList); + + /* This function should not be called by application code hence the + * 'Restricted' in its name. It is not part of the public API. It is + * designed for use by kernel code, and has special calling requirements - + * it should be called with the scheduler suspended. */ + + + /* Place the event list item of the TCB in the appropriate event list. + * In this case it is assume that this is the only task that is going to + * be waiting on this event list, so the faster vListInsertEnd() function + * can be used in place of vListInsert. */ + vListInsertEnd(pxEventList, &(pxCurrentTCB->xEventListItem)); + + /* If the task should block indefinitely then set the block time to a + * value that will be recognised as an indefinite delay inside the + * prvAddCurrentTaskToDelayedList() function. */ + if (xWaitIndefinitely != pdFALSE) { + xTicksToWait = portMAX_DELAY; + } + + traceTASK_DELAY_UNTIL((xTickCount + xTicksToWait)); + prvAddCurrentTaskToDelayedList(xTicksToWait, xWaitIndefinitely); +} + +#endif /* configUSE_TIMERS */ + +/*-----------------------------------------------------------*/ + +BaseType_t xTaskRemoveFromEventList(const List_t *const pxEventList) { + TCB_t *pxUnblockedTCB; + BaseType_t xReturn; + + /* THIS FUNCTION MUST BE CALLED FROM A CRITICAL SECTION. It can also be + * called from a critical section within an ISR. */ + + /* The event list is sorted in priority order, so the first in the list can + * be removed as it is known to be the highest priority. Remove the TCB from + * the delayed list, and add it to the ready list. + * + * If an event is for a queue that is locked then this function will never + * get called - the lock count on the queue will get modified instead. This + * means exclusive access to the event list is guaranteed here. + * + * This function assumes that a check has already been made to ensure that + * pxEventList is not empty. */ + pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( + pxEventList); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + configASSERT(pxUnblockedTCB); + (void) uxListRemove(&(pxUnblockedTCB->xEventListItem)); + + if (uxSchedulerSuspended == (UBaseType_t) pdFALSE) { + (void) uxListRemove(&(pxUnblockedTCB->xStateListItem));prvAddTaskToReadyList(pxUnblockedTCB); + +#if (configUSE_TICKLESS_IDLE != 0) + { + /* If a task is blocked on a kernel object then xNextTaskUnblockTime + * might be set to the blocked task's time out time. If the task is + * unblocked for a reason other than a timeout xNextTaskUnblockTime is + * normally left unchanged, because it is automatically reset to a new + * value when the tick count equals xNextTaskUnblockTime. However if + * tickless idling is used it might be more important to enter sleep mode + * at the earliest possible time - so reset xNextTaskUnblockTime here to + * ensure it is updated at the earliest possible time. */ + prvResetNextTaskUnblockTime(); + } +#endif + } else { + /* The delayed and ready lists cannot be accessed, so hold this task + * pending until the scheduler is resumed. */ + vListInsertEnd(&(xPendingReadyList), &(pxUnblockedTCB->xEventListItem)); + } + + if (pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority) { + /* Return true if the task removed from the event list has a higher + * priority than the calling task. This allows the calling task to know if + * it should force a context switch now. */ + xReturn = pdTRUE; + + /* Mark that a yield is pending in case the user is not using the + * "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ + xYieldPending = pdTRUE; + } else { + xReturn = pdFALSE; + } + + return xReturn; +} + +/*-----------------------------------------------------------*/ + +void vTaskRemoveFromUnorderedEventList(ListItem_t *pxEventListItem, + const TickType_t xItemValue) { + TCB_t *pxUnblockedTCB; + + /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. It is used by + * the event flags implementation. */ + configASSERT(uxSchedulerSuspended != pdFALSE); + + /* Store the new item value in the event list. */ + listSET_LIST_ITEM_VALUE(pxEventListItem, xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE); + + /* Remove the event list form the event flag. Interrupts do not access + * event flags. */ + pxUnblockedTCB = listGET_LIST_ITEM_OWNER( + pxEventListItem); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + configASSERT(pxUnblockedTCB); + (void) uxListRemove(pxEventListItem); + +#if (configUSE_TICKLESS_IDLE != 0) + { + /* If a task is blocked on a kernel object then xNextTaskUnblockTime + * might be set to the blocked task's time out time. If the task is + * unblocked for a reason other than a timeout xNextTaskUnblockTime is + * normally left unchanged, because it is automatically reset to a new + * value when the tick count equals xNextTaskUnblockTime. However if + * tickless idling is used it might be more important to enter sleep mode + * at the earliest possible time - so reset xNextTaskUnblockTime here to + * ensure it is updated at the earliest possible time. */ + prvResetNextTaskUnblockTime(); + } +#endif + + /* Remove the task from the delayed list and add it to the ready list. The + * scheduler is suspended so interrupts will not be accessing the ready + * lists. */ + (void) uxListRemove(&(pxUnblockedTCB->xStateListItem));prvAddTaskToReadyList(pxUnblockedTCB); + + if (pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority) { + /* The unblocked task has a priority above that of the calling task, so + * a context switch is required. This function is called with the + * scheduler suspended so xYieldPending is set so the context switch + * occurs immediately that the scheduler is resumed (unsuspended). */ + xYieldPending = pdTRUE; + } +} + +/*-----------------------------------------------------------*/ + +void vTaskSetTimeOutState(TimeOut_t *const pxTimeOut) { + configASSERT(pxTimeOut); + taskENTER_CRITICAL(); + { + pxTimeOut->xOverflowCount = xNumOfOverflows; + pxTimeOut->xTimeOnEntering = xTickCount; + } + taskEXIT_CRITICAL(); +} + +/*-----------------------------------------------------------*/ + +void vTaskInternalSetTimeOutState(TimeOut_t *const pxTimeOut) { + /* For internal use only as it does not use a critical section. */ + pxTimeOut->xOverflowCount = xNumOfOverflows; + pxTimeOut->xTimeOnEntering = xTickCount; +} + +/*-----------------------------------------------------------*/ + +BaseType_t xTaskCheckForTimeOut(TimeOut_t *const pxTimeOut, + TickType_t *const pxTicksToWait) { + BaseType_t xReturn; + + configASSERT(pxTimeOut); + configASSERT(pxTicksToWait); + + taskENTER_CRITICAL(); + { + /* Minor optimisation. The tick count cannot change in this block. */ + const TickType_t xConstTickCount = xTickCount; + const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering; + +#if (INCLUDE_xTaskAbortDelay == 1) + if( pxCurrentTCB->ucDelayAborted != ( uint8_t ) pdFALSE ) + { + /* The delay was aborted, which is not the same as a time out, + * but has the same result. */ + pxCurrentTCB->ucDelayAborted = pdFALSE; + xReturn = pdTRUE; + } + else +#endif + +#if (INCLUDE_vTaskSuspend == 1) + if (*pxTicksToWait == portMAX_DELAY) { + /* If INCLUDE_vTaskSuspend is set to 1 and the block time + * specified is the maximum block time then the task should block + * indefinitely, and therefore never time out. */ + xReturn = pdFALSE; + } else +#endif + + if ((xNumOfOverflows != pxTimeOut->xOverflowCount) && (xConstTickCount >= + pxTimeOut->xTimeOnEntering)) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */ + { + /* The tick count is greater than the time at which + * vTaskSetTimeout() was called, but has also overflowed since + * vTaskSetTimeOut() was called. It must have wrapped all the way + * around and gone past again. This passed since vTaskSetTimeout() + * was called. */ + xReturn = pdTRUE; + *pxTicksToWait = (TickType_t) 0; + } else if (xElapsedTime < + *pxTicksToWait) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */ + { + /* Not a genuine timeout. Adjust parameters for time remaining. */ + *pxTicksToWait -= xElapsedTime; + vTaskInternalSetTimeOutState(pxTimeOut); + xReturn = pdFALSE; + } else { + *pxTicksToWait = (TickType_t) 0; + xReturn = pdTRUE; + } + } + taskEXIT_CRITICAL(); + + return xReturn; +} + +/*-----------------------------------------------------------*/ + +void vTaskMissedYield(void) { + xYieldPending = pdTRUE; +} +/*-----------------------------------------------------------*/ + +#if (configUSE_TRACE_FACILITY == 1) + +UBaseType_t uxTaskGetTaskNumber(TaskHandle_t xTask) { + UBaseType_t uxReturn; + TCB_t const *pxTCB; + + if (xTask != NULL) { + pxTCB = xTask; + uxReturn = pxTCB->uxTaskNumber; + } else { + uxReturn = 0U; + } + + return uxReturn; +} + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if (configUSE_TRACE_FACILITY == 1) + +void vTaskSetTaskNumber(TaskHandle_t xTask, + const UBaseType_t uxHandle) { + TCB_t *pxTCB; + + if (xTask != NULL) { + pxTCB = xTask; + pxTCB->uxTaskNumber = uxHandle; + } +} + +#endif /* configUSE_TRACE_FACILITY */ + +/* + * ----------------------------------------------------------- + * The Idle task. + * ---------------------------------------------------------- + * + * The portTASK_FUNCTION() macro is used to allow port/compiler specific + * language extensions. The equivalent prototype for this function is: + * + * void prvIdleTask( void *pvParameters ); + * + */ +static portTASK_FUNCTION(prvIdleTask, pvParameters) { + /* Stop warnings. */ + (void) pvParameters; + + /** THIS IS THE RTOS IDLE TASK - WHICH IS CREATED AUTOMATICALLY WHEN THE + * SCHEDULER IS STARTED. **/ + + /* In case a task that has a secure context deletes itself, in which case + * the idle task is responsible for deleting the task's secure context, if + * any. */ + portALLOCATE_SECURE_CONTEXT(configMINIMAL_SECURE_STACK_SIZE); + + for (;;) { + /* See if any tasks have deleted themselves - if so then the idle task + * is responsible for freeing the deleted task's TCB and stack. */ + + prvCheckTasksWaitingTermination(); + +#if (configUSE_PREEMPTION == 0) + { + /* If we are not using preemption we keep forcing a task switch to + * see if any other task has become available. If we are using + * preemption we don't need to do this as any task becoming available + * will automatically get the processor anyway. */ + taskYIELD(); + } +#endif /* configUSE_PREEMPTION */ + +#if ((configUSE_PREEMPTION == 1) && (configIDLE_SHOULD_YIELD == 1)) + { + /* When using preemption tasks of equal priority will be + * timesliced. If a task that is sharing the idle priority is ready + * to run then the idle task should yield before the end of the + * timeslice. + * + * A critical region is not required here as we are just reading from + * the list, and an occasional incorrect value will not matter. If + * the ready list at the idle priority contains more than one task + * then a task other than the idle task is ready to execute. */ + if (listCURRENT_LIST_LENGTH(&(pxReadyTasksLists[tskIDLE_PRIORITY])) > (UBaseType_t) 1) { + taskYIELD(); + } else { + mtCOVERAGE_TEST_MARKER(); + } + } +#endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */ + +#if (configUSE_IDLE_HOOK == 1) + { + extern void vApplicationIdleHook( void ); + + /* Call the user defined function from within the idle task. This + * allows the application designer to add background functionality + * without the overhead of a separate task. + * NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES, + * CALL A FUNCTION THAT MIGHT BLOCK. */ + vApplicationIdleHook(); + } +#endif /* configUSE_IDLE_HOOK */ + + /* This conditional compilation should use inequality to 0, not equality + * to 1. This is to ensure portSUPPRESS_TICKS_AND_SLEEP() is called when + * user defined low power mode implementations require + * configUSE_TICKLESS_IDLE to be set to a value other than 1. */ +#if (configUSE_TICKLESS_IDLE != 0) + { + TickType_t xExpectedIdleTime; + + /* It is not desirable to suspend then resume the scheduler on + * each iteration of the idle task. Therefore, a preliminary + * test of the expected idle time is performed without the + * scheduler suspended. The result here is not necessarily + * valid. */ + xExpectedIdleTime = prvGetExpectedIdleTime(); + + if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP ) + { + vTaskSuspendAll(); + { + /* Now the scheduler is suspended, the expected idle + * time can be sampled again, and this time its value can + * be used. */ + configASSERT( xNextTaskUnblockTime >= xTickCount ); + xExpectedIdleTime = prvGetExpectedIdleTime(); + + /* Define the following macro to set xExpectedIdleTime to 0 + * if the application does not want + * portSUPPRESS_TICKS_AND_SLEEP() to be called. */ + configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( xExpectedIdleTime ); + + if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP ) + { + traceLOW_POWER_IDLE_BEGIN(); + portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ); + traceLOW_POWER_IDLE_END(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + ( void ) xTaskResumeAll(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +#endif /* configUSE_TICKLESS_IDLE */ + } +} +/*-----------------------------------------------------------*/ + +#if (configUSE_TICKLESS_IDLE != 0) + + eSleepModeStatus eTaskConfirmSleepModeStatus( void ) + { + /* The idle task exists in addition to the application tasks. */ + const UBaseType_t uxNonApplicationTasks = 1; + eSleepModeStatus eReturn = eStandardSleep; + + /* This function must be called from a critical section. */ + + if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0 ) + { + /* A task was made ready while the scheduler was suspended. */ + eReturn = eAbortSleep; + } + else if( xYieldPending != pdFALSE ) + { + /* A yield was pended while the scheduler was suspended. */ + eReturn = eAbortSleep; + } + else if( xPendedTicks != 0 ) + { + /* A tick interrupt has already occurred but was held pending + * because the scheduler is suspended. */ + eReturn = eAbortSleep; + } + else + { + /* If all the tasks are in the suspended list (which might mean they + * have an infinite block time rather than actually being suspended) + * then it is safe to turn all clocks off and just wait for external + * interrupts. */ + if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == ( uxCurrentNumberOfTasks - uxNonApplicationTasks ) ) + { + eReturn = eNoTasksWaitingTimeout; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + return eReturn; + } + +#endif /* configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +#if (configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0) + + void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, + BaseType_t xIndex, + void * pvValue ) + { + TCB_t * pxTCB; + + if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS ) + { + pxTCB = prvGetTCBFromHandle( xTaskToSet ); + configASSERT( pxTCB != NULL ); + pxTCB->pvThreadLocalStoragePointers[ xIndex ] = pvValue; + } + } + +#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */ +/*-----------------------------------------------------------*/ + +#if (configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0) + + void * pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, + BaseType_t xIndex ) + { + void * pvReturn = NULL; + TCB_t * pxTCB; + + if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS ) + { + pxTCB = prvGetTCBFromHandle( xTaskToQuery ); + pvReturn = pxTCB->pvThreadLocalStoragePointers[ xIndex ]; + } + else + { + pvReturn = NULL; + } + + return pvReturn; + } + +#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */ +/*-----------------------------------------------------------*/ + +#if (portUSING_MPU_WRAPPERS == 1) + + void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify, + const MemoryRegion_t * const xRegions ) + { + TCB_t * pxTCB; + + /* If null is passed in here then we are modifying the MPU settings of + * the calling task. */ + pxTCB = prvGetTCBFromHandle( xTaskToModify ); + + vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, NULL, 0 ); + } + +#endif /* portUSING_MPU_WRAPPERS */ + +/*-----------------------------------------------------------*/ + +static void prvInitialiseTaskLists(void) { + UBaseType_t uxPriority; + + for (uxPriority = (UBaseType_t) 0U; uxPriority < (UBaseType_t) configMAX_PRIORITIES; uxPriority++) { + vListInitialise(&(pxReadyTasksLists[uxPriority])); + } + + vListInitialise(&xDelayedTaskList1); + vListInitialise(&xDelayedTaskList2); + vListInitialise(&xPendingReadyList); + +#if (INCLUDE_vTaskDelete == 1) + { + vListInitialise(&xTasksWaitingTermination); + } +#endif /* INCLUDE_vTaskDelete */ + +#if (INCLUDE_vTaskSuspend == 1) + { + vListInitialise(&xSuspendedTaskList); + } +#endif /* INCLUDE_vTaskSuspend */ + + /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList + * using list2. */ + pxDelayedTaskList = &xDelayedTaskList1; + pxOverflowDelayedTaskList = &xDelayedTaskList2; +} + +/*-----------------------------------------------------------*/ + +static void prvCheckTasksWaitingTermination(void) { + /** THIS FUNCTION IS CALLED FROM THE RTOS IDLE TASK **/ + + +#if (INCLUDE_vTaskDelete == 1) + { + TCB_t *pxTCB; + + /* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL() + * being called too often in the idle task. */ + while (uxDeletedTasksWaitingCleanUp > (UBaseType_t) 0U) { + taskENTER_CRITICAL(); + { + pxTCB = listGET_OWNER_OF_HEAD_ENTRY( + (&xTasksWaitingTermination)); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + (void) uxListRemove(&(pxTCB->xStateListItem)); + --uxCurrentNumberOfTasks; + --uxDeletedTasksWaitingCleanUp; + } + taskEXIT_CRITICAL(); + + prvDeleteTCB(pxTCB); + } + } +#endif /* INCLUDE_vTaskDelete */ +} +/*-----------------------------------------------------------*/ + +#if (configUSE_TRACE_FACILITY == 1) + +void vTaskGetInfo(TaskHandle_t xTask, + TaskStatus_t *pxTaskStatus, + BaseType_t xGetFreeStackSpace, + eTaskState eState) { + TCB_t *pxTCB; + + /* xTask is NULL then get the state of the calling task. */ + pxTCB = prvGetTCBFromHandle(xTask); + + pxTaskStatus->xHandle = (TaskHandle_t) pxTCB; + pxTaskStatus->pcTaskName = (const char *) &(pxTCB->pcTaskName[0]); + pxTaskStatus->uxCurrentPriority = pxTCB->uxPriority; + pxTaskStatus->pxStackBase = pxTCB->pxStack; + pxTaskStatus->xTaskNumber = pxTCB->uxTCBNumber; + +#if (configUSE_MUTEXES == 1) + { + pxTaskStatus->uxBasePriority = pxTCB->uxBasePriority; + } +#else + { + pxTaskStatus->uxBasePriority = 0; + } +#endif + +#if (configGENERATE_RUN_TIME_STATS == 1) + { + pxTaskStatus->ulRunTimeCounter = pxTCB->ulRunTimeCounter; + } +#else + { + pxTaskStatus->ulRunTimeCounter = 0; + } +#endif + + /* Obtaining the task state is a little fiddly, so is only done if the + * value of eState passed into this function is eInvalid - otherwise the + * state is just set to whatever is passed in. */ + if (eState != eInvalid) { + if (pxTCB == pxCurrentTCB) { + pxTaskStatus->eCurrentState = eRunning; + } else { + pxTaskStatus->eCurrentState = eState; + +#if (INCLUDE_vTaskSuspend == 1) + { + /* If the task is in the suspended list then there is a + * chance it is actually just blocked indefinitely - so really + * it should be reported as being in the Blocked state. */ + if (eState == eSuspended) { + vTaskSuspendAll(); + { + if (listLIST_ITEM_CONTAINER(&(pxTCB->xEventListItem)) != NULL) { + pxTaskStatus->eCurrentState = eBlocked; + } + } + (void) xTaskResumeAll(); + } + } +#endif /* INCLUDE_vTaskSuspend */ + } + } else { + pxTaskStatus->eCurrentState = eTaskGetState(pxTCB); + } + + /* Obtaining the stack space takes some time, so the xGetFreeStackSpace + * parameter is provided to allow it to be skipped. */ + if (xGetFreeStackSpace != pdFALSE) { +#if (portSTACK_GROWTH > 0) + { + pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxEndOfStack ); + } +#else + { + pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace((uint8_t *) pxTCB->pxStack); + } +#endif + } else { + pxTaskStatus->usStackHighWaterMark = 0; + } +} + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if (configUSE_TRACE_FACILITY == 1) + +static UBaseType_t prvListTasksWithinSingleList(TaskStatus_t *pxTaskStatusArray, + List_t *pxList, + eTaskState eState) { + configLIST_VOLATILE TCB_t *pxNextTCB, *pxFirstTCB; + UBaseType_t uxTask = 0; + + if (listCURRENT_LIST_LENGTH(pxList) > (UBaseType_t) 0) { + listGET_OWNER_OF_NEXT_ENTRY(pxFirstTCB, + pxList); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + + /* Populate an TaskStatus_t structure within the + * pxTaskStatusArray array for each task that is referenced from + * pxList. See the definition of TaskStatus_t in task.h for the + * meaning of each TaskStatus_t structure member. */ + do { + listGET_OWNER_OF_NEXT_ENTRY(pxNextTCB, + pxList); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + vTaskGetInfo((TaskHandle_t) pxNextTCB, &(pxTaskStatusArray[uxTask]), pdTRUE, eState); + uxTask++; + } while (pxNextTCB != pxFirstTCB); + } else { + mtCOVERAGE_TEST_MARKER(); + } + + return uxTask; +} + +#endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +#if ((configUSE_TRACE_FACILITY == 1) || (INCLUDE_uxTaskGetStackHighWaterMark == 1) || (INCLUDE_uxTaskGetStackHighWaterMark2 == 1)) + +static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace(const uint8_t *pucStackByte) { + uint32_t ulCount = 0U; + + while (*pucStackByte == (uint8_t) tskSTACK_FILL_BYTE) { + pucStackByte -= portSTACK_GROWTH; + ulCount++; + } + + ulCount /= (uint32_t) sizeof(StackType_t); /*lint !e961 Casting is not redundant on smaller architectures. */ + + return (configSTACK_DEPTH_TYPE) ulCount; +} + +#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if (INCLUDE_uxTaskGetStackHighWaterMark2 == 1) + + /* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the + * same except for their return type. Using configSTACK_DEPTH_TYPE allows the + * user to determine the return type. It gets around the problem of the value + * overflowing on 8-bit types without breaking backward compatibility for + * applications that expect an 8-bit return type. */ + configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) + { + TCB_t * pxTCB; + uint8_t * pucEndOfStack; + configSTACK_DEPTH_TYPE uxReturn; + + /* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are + * the same except for their return type. Using configSTACK_DEPTH_TYPE + * allows the user to determine the return type. It gets around the + * problem of the value overflowing on 8-bit types without breaking + * backward compatibility for applications that expect an 8-bit return + * type. */ + + pxTCB = prvGetTCBFromHandle( xTask ); + + #if portSTACK_GROWTH < 0 + { + pucEndOfStack = ( uint8_t * ) pxTCB->pxStack; + } + #else + { + pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack; + } + #endif + + uxReturn = prvTaskCheckFreeStackSpace( pucEndOfStack ); + + return uxReturn; + } + +#endif /* INCLUDE_uxTaskGetStackHighWaterMark2 */ +/*-----------------------------------------------------------*/ + +#if (INCLUDE_uxTaskGetStackHighWaterMark == 1) + +UBaseType_t uxTaskGetStackHighWaterMark(TaskHandle_t xTask) { + TCB_t *pxTCB; + uint8_t *pucEndOfStack; + UBaseType_t uxReturn; + + pxTCB = prvGetTCBFromHandle(xTask); + +#if portSTACK_GROWTH < 0 + { + pucEndOfStack = (uint8_t *) pxTCB->pxStack; + } +#else + { + pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack; + } +#endif + + uxReturn = (UBaseType_t) prvTaskCheckFreeStackSpace(pucEndOfStack); + + return uxReturn; +} + +#endif /* INCLUDE_uxTaskGetStackHighWaterMark */ +/*-----------------------------------------------------------*/ + +#if (INCLUDE_vTaskDelete == 1) + +static void prvDeleteTCB(TCB_t *pxTCB) { + /* This call is required specifically for the TriCore port. It must be + * above the vPortFree() calls. The call is also used by ports/demos that + * want to allocate and clean RAM statically. */ + portCLEAN_UP_TCB(pxTCB); + + /* Free up the memory allocated by the scheduler for the task. It is up + * to the task to free any memory allocated at the application level. + * See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html + * for additional information. */ +#if (configUSE_NEWLIB_REENTRANT == 1) + { + _reclaim_reent( &( pxTCB->xNewLib_reent ) ); + } +#endif /* configUSE_NEWLIB_REENTRANT */ + +#if ((configSUPPORT_DYNAMIC_ALLOCATION == 1) && (configSUPPORT_STATIC_ALLOCATION == 0) && (portUSING_MPU_WRAPPERS == 0)) + { + /* The task can only have been allocated dynamically - free both + * the stack and TCB. */ + vPortFree( pxTCB->pxStack ); + vPortFree( pxTCB ); + } +#elif (tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ + { + /* The task could have been allocated statically or dynamically, so + * check what was statically allocated before trying to free the + * memory. */ + if (pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB) { + /* Both the stack and TCB were allocated dynamically, so both + * must be freed. */ + vPortFree(pxTCB->pxStack); + vPortFree(pxTCB); + } else if (pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY) { + /* Only the stack was statically allocated, so the TCB is the + * only memory that must be freed. */ + vPortFree(pxTCB); + } else { + /* Neither the stack nor the TCB were allocated dynamically, so + * nothing needs to be freed. */ + configASSERT(pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB); + mtCOVERAGE_TEST_MARKER(); + } + } +#endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +} + +#endif /* INCLUDE_vTaskDelete */ + +/*-----------------------------------------------------------*/ + +static void prvResetNextTaskUnblockTime(void) { + if (listLIST_IS_EMPTY(pxDelayedTaskList) != pdFALSE) { + /* The new current delayed list is empty. Set xNextTaskUnblockTime to + * the maximum possible value so it is extremely unlikely that the + * if( xTickCount >= xNextTaskUnblockTime ) test will pass until + * there is an item in the delayed list. */ + xNextTaskUnblockTime = portMAX_DELAY; + } else { + /* The new current delayed list is not empty, get the value of + * the item at the head of the delayed list. This is the time at + * which the task at the head of the delayed list should be removed + * from the Blocked state. */ + xNextTaskUnblockTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY(pxDelayedTaskList); + } +} +/*-----------------------------------------------------------*/ + +#if ((INCLUDE_xTaskGetCurrentTaskHandle == 1) || (configUSE_MUTEXES == 1)) + +TaskHandle_t xTaskGetCurrentTaskHandle(void) { + TaskHandle_t xReturn; + + /* A critical section is not required as this is not called from + * an interrupt and the current TCB will always be the same for any + * individual execution thread. */ + xReturn = pxCurrentTCB; + + return xReturn; +} + +#endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if ((INCLUDE_xTaskGetSchedulerState == 1) || (configUSE_TIMERS == 1)) + +BaseType_t xTaskGetSchedulerState(void) { + BaseType_t xReturn; + + if (xSchedulerRunning == pdFALSE) { + xReturn = taskSCHEDULER_NOT_STARTED; + } else { + if (uxSchedulerSuspended == (UBaseType_t) pdFALSE) { + xReturn = taskSCHEDULER_RUNNING; + } else { + xReturn = taskSCHEDULER_SUSPENDED; + } + } + + return xReturn; +} + +#endif /* ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) */ +/*-----------------------------------------------------------*/ + +#if (configUSE_MUTEXES == 1) + +BaseType_t xTaskPriorityInherit(TaskHandle_t const pxMutexHolder) { + TCB_t *const pxMutexHolderTCB = pxMutexHolder; + BaseType_t xReturn = pdFALSE; + + /* If the mutex was given back by an interrupt while the queue was + * locked then the mutex holder might now be NULL. _RB_ Is this still + * needed as interrupts can no longer use mutexes? */ + if (pxMutexHolder != NULL) { + /* If the holder of the mutex has a priority below the priority of + * the task attempting to obtain the mutex then it will temporarily + * inherit the priority of the task attempting to obtain the mutex. */ + if (pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority) { + /* Adjust the mutex holder state to account for its new + * priority. Only reset the event list item value if the value is + * not being used for anything else. */ + if ((listGET_LIST_ITEM_VALUE(&(pxMutexHolderTCB->xEventListItem)) & taskEVENT_LIST_ITEM_VALUE_IN_USE) == + 0UL) { + listSET_LIST_ITEM_VALUE(&(pxMutexHolderTCB->xEventListItem), (TickType_t) configMAX_PRIORITIES - + (TickType_t) pxCurrentTCB->uxPriority); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + } else { + mtCOVERAGE_TEST_MARKER(); + } + + /* If the task being modified is in the ready state it will need + * to be moved into a new list. */ + if (listIS_CONTAINED_WITHIN(&(pxReadyTasksLists[pxMutexHolderTCB->uxPriority]), + &(pxMutexHolderTCB->xStateListItem)) != pdFALSE) { + if (uxListRemove(&(pxMutexHolderTCB->xStateListItem)) == (UBaseType_t) 0) { + /* It is known that the task is in its ready list so + * there is no need to check again and the port level + * reset macro can be called directly. */ + portRESET_READY_PRIORITY(pxMutexHolderTCB->uxPriority, uxTopReadyPriority); + } else { + mtCOVERAGE_TEST_MARKER(); + } + + /* Inherit the priority before being moved into the new list. */ + pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;prvAddTaskToReadyList(pxMutexHolderTCB); + } else { + /* Just inherit the priority. */ + pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority; + } + + traceTASK_PRIORITY_INHERIT(pxMutexHolderTCB, pxCurrentTCB->uxPriority); + + /* Inheritance occurred. */ + xReturn = pdTRUE; + } else { + if (pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority) { + /* The base priority of the mutex holder is lower than the + * priority of the task attempting to take the mutex, but the + * current priority of the mutex holder is not lower than the + * priority of the task attempting to take the mutex. + * Therefore the mutex holder must have already inherited a + * priority, but inheritance would have occurred if that had + * not been the case. */ + xReturn = pdTRUE; + } else { + mtCOVERAGE_TEST_MARKER(); + } + } + } else { + mtCOVERAGE_TEST_MARKER(); + } + + return xReturn; +} + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if (configUSE_MUTEXES == 1) + +BaseType_t xTaskPriorityDisinherit(TaskHandle_t const pxMutexHolder) { + TCB_t *const pxTCB = pxMutexHolder; + BaseType_t xReturn = pdFALSE; + + if (pxMutexHolder != NULL) { + /* A task can only have an inherited priority if it holds the mutex. + * If the mutex is held by a task then it cannot be given from an + * interrupt, and if a mutex is given by the holding task then it must + * be the running state task. */ + configASSERT(pxTCB == pxCurrentTCB); + configASSERT(pxTCB->uxMutexesHeld); + (pxTCB->uxMutexesHeld)--; + + /* Has the holder of the mutex inherited the priority of another + * task? */ + if (pxTCB->uxPriority != pxTCB->uxBasePriority) { + /* Only disinherit if no other mutexes are held. */ + if (pxTCB->uxMutexesHeld == (UBaseType_t) 0) { + /* A task can only have an inherited priority if it holds + * the mutex. If the mutex is held by a task then it cannot be + * given from an interrupt, and if a mutex is given by the + * holding task then it must be the running state task. Remove + * the holding task from the ready list. */ + if (uxListRemove(&(pxTCB->xStateListItem)) == (UBaseType_t) 0) { + portRESET_READY_PRIORITY(pxTCB->uxPriority, uxTopReadyPriority); + } else { + mtCOVERAGE_TEST_MARKER(); + } + + /* Disinherit the priority before adding the task into the + * new ready list. */ + traceTASK_PRIORITY_DISINHERIT(pxTCB, pxTCB->uxBasePriority); + pxTCB->uxPriority = pxTCB->uxBasePriority; + + /* Reset the event list item value. It cannot be in use for + * any other purpose if this task is running, and it must be + * running to give back the mutex. */ + listSET_LIST_ITEM_VALUE(&(pxTCB->xEventListItem), (TickType_t) configMAX_PRIORITIES - + (TickType_t) pxTCB->uxPriority); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + prvAddTaskToReadyList(pxTCB); + + /* Return true to indicate that a context switch is required. + * This is only actually required in the corner case whereby + * multiple mutexes were held and the mutexes were given back + * in an order different to that in which they were taken. + * If a context switch did not occur when the first mutex was + * returned, even if a task was waiting on it, then a context + * switch should occur when the last mutex is returned whether + * a task is waiting on it or not. */ + xReturn = pdTRUE; + } else { + mtCOVERAGE_TEST_MARKER(); + } + } else { + mtCOVERAGE_TEST_MARKER(); + } + } else { + mtCOVERAGE_TEST_MARKER(); + } + + return xReturn; +} + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if (configUSE_MUTEXES == 1) + +void vTaskPriorityDisinheritAfterTimeout(TaskHandle_t const pxMutexHolder, + UBaseType_t uxHighestPriorityWaitingTask) { + TCB_t *const pxTCB = pxMutexHolder; + UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse; + const UBaseType_t uxOnlyOneMutexHeld = (UBaseType_t) 1; + + if (pxMutexHolder != NULL) { + /* If pxMutexHolder is not NULL then the holder must hold at least + * one mutex. */ + configASSERT(pxTCB->uxMutexesHeld); + + /* Determine the priority to which the priority of the task that + * holds the mutex should be set. This will be the greater of the + * holding task's base priority and the priority of the highest + * priority task that is waiting to obtain the mutex. */ + if (pxTCB->uxBasePriority < uxHighestPriorityWaitingTask) { + uxPriorityToUse = uxHighestPriorityWaitingTask; + } else { + uxPriorityToUse = pxTCB->uxBasePriority; + } + + /* Does the priority need to change? */ + if (pxTCB->uxPriority != uxPriorityToUse) { + /* Only disinherit if no other mutexes are held. This is a + * simplification in the priority inheritance implementation. If + * the task that holds the mutex is also holding other mutexes then + * the other mutexes may have caused the priority inheritance. */ + if (pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld) { + /* If a task has timed out because it already holds the + * mutex it was trying to obtain then it cannot of inherited + * its own priority. */ + configASSERT(pxTCB != pxCurrentTCB); + + /* Disinherit the priority, remembering the previous + * priority to facilitate determining the subject task's + * state. */ + traceTASK_PRIORITY_DISINHERIT(pxTCB, uxPriorityToUse); + uxPriorityUsedOnEntry = pxTCB->uxPriority; + pxTCB->uxPriority = uxPriorityToUse; + + /* Only reset the event list item value if the value is not + * being used for anything else. */ + if ((listGET_LIST_ITEM_VALUE(&(pxTCB->xEventListItem)) & taskEVENT_LIST_ITEM_VALUE_IN_USE) == 0UL) { + listSET_LIST_ITEM_VALUE(&(pxTCB->xEventListItem), (TickType_t) configMAX_PRIORITIES - + (TickType_t) uxPriorityToUse); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + } else { + mtCOVERAGE_TEST_MARKER(); + } + + /* If the running task is not the task that holds the mutex + * then the task that holds the mutex could be in either the + * Ready, Blocked or Suspended states. Only remove the task + * from its current state list if it is in the Ready state as + * the task's priority is going to change and there is one + * Ready list per priority. */ + if (listIS_CONTAINED_WITHIN(&(pxReadyTasksLists[uxPriorityUsedOnEntry]), &(pxTCB->xStateListItem)) != + pdFALSE) { + if (uxListRemove(&(pxTCB->xStateListItem)) == (UBaseType_t) 0) { + /* It is known that the task is in its ready list so + * there is no need to check again and the port level + * reset macro can be called directly. */ + portRESET_READY_PRIORITY(pxTCB->uxPriority, uxTopReadyPriority); + } else { + mtCOVERAGE_TEST_MARKER(); + } + + prvAddTaskToReadyList(pxTCB); + } else { + mtCOVERAGE_TEST_MARKER(); + } + } else { + mtCOVERAGE_TEST_MARKER(); + } + } else { + mtCOVERAGE_TEST_MARKER(); + } + } else { + mtCOVERAGE_TEST_MARKER(); + } +} + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if (portCRITICAL_NESTING_IN_TCB == 1) + + void vTaskEnterCritical( void ) + { + portDISABLE_INTERRUPTS(); + + if( xSchedulerRunning != pdFALSE ) + { + ( pxCurrentTCB->uxCriticalNesting )++; + + /* This is not the interrupt safe version of the enter critical + * function so assert() if it is being called from an interrupt + * context. Only API functions that end in "FromISR" can be used in an + * interrupt. Only assert if the critical nesting count is 1 to + * protect against recursive calls if the assert function also uses a + * critical section. */ + if( pxCurrentTCB->uxCriticalNesting == 1 ) + { + portASSERT_IF_IN_ISR(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + +#endif /* portCRITICAL_NESTING_IN_TCB */ +/*-----------------------------------------------------------*/ + +#if (portCRITICAL_NESTING_IN_TCB == 1) + + void vTaskExitCritical( void ) + { + if( xSchedulerRunning != pdFALSE ) + { + if( pxCurrentTCB->uxCriticalNesting > 0U ) + { + ( pxCurrentTCB->uxCriticalNesting )--; + + if( pxCurrentTCB->uxCriticalNesting == 0U ) + { + portENABLE_INTERRUPTS(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + +#endif /* portCRITICAL_NESTING_IN_TCB */ +/*-----------------------------------------------------------*/ + +#if ((configUSE_TRACE_FACILITY == 1) && (configUSE_STATS_FORMATTING_FUNCTIONS > 0)) + + static char * prvWriteNameToBuffer( char * pcBuffer, + const char * pcTaskName ) + { + size_t x; + + /* Start by copying the entire string. */ + strcpy( pcBuffer, pcTaskName ); + + /* Pad the end of the string with spaces to ensure columns line up when + * printed out. */ + for( x = strlen( pcBuffer ); x < ( size_t ) ( configMAX_TASK_NAME_LEN - 1 ); x++ ) + { + pcBuffer[ x ] = ' '; + } + + /* Terminate. */ + pcBuffer[ x ] = ( char ) 0x00; + + /* Return the new end of string. */ + return &( pcBuffer[ x ] ); + } + +#endif /* ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) */ +/*-----------------------------------------------------------*/ + +#if ((configUSE_TRACE_FACILITY == 1) && (configUSE_STATS_FORMATTING_FUNCTIONS > 0) && (configSUPPORT_DYNAMIC_ALLOCATION == 1)) + + void vTaskList( char * pcWriteBuffer ) + { + TaskStatus_t * pxTaskStatusArray; + UBaseType_t uxArraySize, x; + char cStatus; + + /* + * PLEASE NOTE: + * + * This function is provided for convenience only, and is used by many + * of the demo applications. Do not consider it to be part of the + * scheduler. + * + * vTaskList() calls uxTaskGetSystemState(), then formats part of the + * uxTaskGetSystemState() output into a human readable table that + * displays task names, states and stack usage. + * + * vTaskList() has a dependency on the sprintf() C library function that + * might bloat the code size, use a lot of stack, and provide different + * results on different platforms. An alternative, tiny, third party, + * and limited functionality implementation of sprintf() is provided in + * many of the FreeRTOS/Demo sub-directories in a file called + * printf-stdarg.c (note printf-stdarg.c does not provide a full + * snprintf() implementation!). + * + * It is recommended that production systems call uxTaskGetSystemState() + * directly to get access to raw stats data, rather than indirectly + * through a call to vTaskList(). + */ + + + /* Make sure the write buffer does not contain a string. */ + *pcWriteBuffer = ( char ) 0x00; + + /* Take a snapshot of the number of tasks in case it changes while this + * function is executing. */ + uxArraySize = uxCurrentNumberOfTasks; + + /* Allocate an array index for each task. NOTE! if + * configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will + * equate to NULL. */ + pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */ + + if( pxTaskStatusArray != NULL ) + { + /* Generate the (binary) data. */ + uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, NULL ); + + /* Create a human readable table from the binary data. */ + for( x = 0; x < uxArraySize; x++ ) + { + switch( pxTaskStatusArray[ x ].eCurrentState ) + { + case eRunning: + cStatus = tskRUNNING_CHAR; + break; + + case eReady: + cStatus = tskREADY_CHAR; + break; + + case eBlocked: + cStatus = tskBLOCKED_CHAR; + break; + + case eSuspended: + cStatus = tskSUSPENDED_CHAR; + break; + + case eDeleted: + cStatus = tskDELETED_CHAR; + break; + + case eInvalid: /* Fall through. */ + default: /* Should not get here, but it is included + * to prevent static checking errors. */ + cStatus = ( char ) 0x00; + break; + } + + /* Write the task name to the string, padding with spaces so it + * can be printed in tabular form more easily. */ + pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName ); + + /* Write the rest of the string. */ + sprintf( pcWriteBuffer, "\t%c\t%u\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */ + pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */ + } + + /* Free the array again. NOTE! If configSUPPORT_DYNAMIC_ALLOCATION + * is 0 then vPortFree() will be #defined to nothing. */ + vPortFree( pxTaskStatusArray ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + +#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ +/*----------------------------------------------------------*/ + +#if ((configGENERATE_RUN_TIME_STATS == 1) && (configUSE_STATS_FORMATTING_FUNCTIONS > 0) && (configSUPPORT_DYNAMIC_ALLOCATION == 1)) + + void vTaskGetRunTimeStats( char * pcWriteBuffer ) + { + TaskStatus_t * pxTaskStatusArray; + UBaseType_t uxArraySize, x; + uint32_t ulTotalTime, ulStatsAsPercentage; + + #if ( configUSE_TRACE_FACILITY != 1 ) + { + #error configUSE_TRACE_FACILITY must also be set to 1 in FreeRTOSConfig.h to use vTaskGetRunTimeStats(). + } + #endif + + /* + * PLEASE NOTE: + * + * This function is provided for convenience only, and is used by many + * of the demo applications. Do not consider it to be part of the + * scheduler. + * + * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part + * of the uxTaskGetSystemState() output into a human readable table that + * displays the amount of time each task has spent in the Running state + * in both absolute and percentage terms. + * + * vTaskGetRunTimeStats() has a dependency on the sprintf() C library + * function that might bloat the code size, use a lot of stack, and + * provide different results on different platforms. An alternative, + * tiny, third party, and limited functionality implementation of + * sprintf() is provided in many of the FreeRTOS/Demo sub-directories in + * a file called printf-stdarg.c (note printf-stdarg.c does not provide + * a full snprintf() implementation!). + * + * It is recommended that production systems call uxTaskGetSystemState() + * directly to get access to raw stats data, rather than indirectly + * through a call to vTaskGetRunTimeStats(). + */ + + /* Make sure the write buffer does not contain a string. */ + *pcWriteBuffer = ( char ) 0x00; + + /* Take a snapshot of the number of tasks in case it changes while this + * function is executing. */ + uxArraySize = uxCurrentNumberOfTasks; + + /* Allocate an array index for each task. NOTE! If + * configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will + * equate to NULL. */ + pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */ + + if( pxTaskStatusArray != NULL ) + { + /* Generate the (binary) data. */ + uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalTime ); + + /* For percentage calculations. */ + ulTotalTime /= 100UL; + + /* Avoid divide by zero errors. */ + if( ulTotalTime > 0UL ) + { + /* Create a human readable table from the binary data. */ + for( x = 0; x < uxArraySize; x++ ) + { + /* What percentage of the total run time has the task used? + * This will always be rounded down to the nearest integer. + * ulTotalRunTimeDiv100 has already been divided by 100. */ + ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalTime; + + /* Write the task name to the string, padding with + * spaces so it can be printed in tabular form more + * easily. */ + pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName ); + + if( ulStatsAsPercentage > 0UL ) + { + #ifdef portLU_PRINTF_SPECIFIER_REQUIRED + { + sprintf( pcWriteBuffer, "\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage ); + } + #else + { + /* sizeof( int ) == sizeof( long ) so a smaller + * printf() library can be used. */ + sprintf( pcWriteBuffer, "\t%u\t\t%u%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */ + } + #endif + } + else + { + /* If the percentage is zero here then the task has + * consumed less than 1% of the total run time. */ + #ifdef portLU_PRINTF_SPECIFIER_REQUIRED + { + sprintf( pcWriteBuffer, "\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter ); + } + #else + { + /* sizeof( int ) == sizeof( long ) so a smaller + * printf() library can be used. */ + sprintf( pcWriteBuffer, "\t%u\t\t<1%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */ + } + #endif + } + + pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */ + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Free the array again. NOTE! If configSUPPORT_DYNAMIC_ALLOCATION + * is 0 then vPortFree() will be #defined to nothing. */ + vPortFree( pxTaskStatusArray ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + +#endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */ + +/*-----------------------------------------------------------*/ + +TickType_t uxTaskResetEventItemValue(void) { + TickType_t uxReturn; + + uxReturn = listGET_LIST_ITEM_VALUE(&(pxCurrentTCB->xEventListItem)); + + /* Reset the event list item to its normal value - so it can be used with + * queues and semaphores. */ + listSET_LIST_ITEM_VALUE(&(pxCurrentTCB->xEventListItem), ((TickType_t) configMAX_PRIORITIES - + (TickType_t) pxCurrentTCB->uxPriority)); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + + return uxReturn; +} +/*-----------------------------------------------------------*/ + +#if (configUSE_MUTEXES == 1) + +TaskHandle_t pvTaskIncrementMutexHeldCount(void) { + /* If xSemaphoreCreateMutex() is called before any tasks have been created + * then pxCurrentTCB will be NULL. */ + if (pxCurrentTCB != NULL) { + (pxCurrentTCB->uxMutexesHeld)++; + } + + return pxCurrentTCB; +} + +#endif /* configUSE_MUTEXES */ +/*-----------------------------------------------------------*/ + +#if (configUSE_TASK_NOTIFICATIONS == 1) + +uint32_t ulTaskGenericNotifyTake(UBaseType_t uxIndexToWait, + BaseType_t xClearCountOnExit, + TickType_t xTicksToWait) { + uint32_t ulReturn; + + configASSERT(uxIndexToWait < configTASK_NOTIFICATION_ARRAY_ENTRIES); + + taskENTER_CRITICAL(); + { + /* Only block if the notification count is not already non-zero. */ + if (pxCurrentTCB->ulNotifiedValue[uxIndexToWait] == 0UL) { + /* Mark this task as waiting for a notification. */ + pxCurrentTCB->ucNotifyState[uxIndexToWait] = taskWAITING_NOTIFICATION; + + if (xTicksToWait > (TickType_t) 0) { + prvAddCurrentTaskToDelayedList(xTicksToWait, pdTRUE); + traceTASK_NOTIFY_TAKE_BLOCK(uxIndexToWait); + + /* All ports are written to allow a yield in a critical + * section (some will yield immediately, others wait until the + * critical section exits) - but it is not something that + * application code should ever do. */ + portYIELD_WITHIN_API(); + } else { + mtCOVERAGE_TEST_MARKER(); + } + } else { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + taskENTER_CRITICAL(); + { + traceTASK_NOTIFY_TAKE(uxIndexToWait); + ulReturn = pxCurrentTCB->ulNotifiedValue[uxIndexToWait]; + + if (ulReturn != 0UL) { + if (xClearCountOnExit != pdFALSE) { + pxCurrentTCB->ulNotifiedValue[uxIndexToWait] = 0UL; + } else { + pxCurrentTCB->ulNotifiedValue[uxIndexToWait] = ulReturn - (uint32_t) 1; + } + } else { + mtCOVERAGE_TEST_MARKER(); + } + + pxCurrentTCB->ucNotifyState[uxIndexToWait] = taskNOT_WAITING_NOTIFICATION; + } + taskEXIT_CRITICAL(); + + return ulReturn; +} + +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + +#if (configUSE_TASK_NOTIFICATIONS == 1) + +BaseType_t xTaskGenericNotifyWait(UBaseType_t uxIndexToWait, + uint32_t ulBitsToClearOnEntry, + uint32_t ulBitsToClearOnExit, + uint32_t *pulNotificationValue, + TickType_t xTicksToWait) { + BaseType_t xReturn; + + configASSERT(uxIndexToWait < configTASK_NOTIFICATION_ARRAY_ENTRIES); + + taskENTER_CRITICAL(); + { + /* Only block if a notification is not already pending. */ + if (pxCurrentTCB->ucNotifyState[uxIndexToWait] != taskNOTIFICATION_RECEIVED) { + /* Clear bits in the task's notification value as bits may get + * set by the notifying task or interrupt. This can be used to + * clear the value to zero. */ + pxCurrentTCB->ulNotifiedValue[uxIndexToWait] &= ~ulBitsToClearOnEntry; + + /* Mark this task as waiting for a notification. */ + pxCurrentTCB->ucNotifyState[uxIndexToWait] = taskWAITING_NOTIFICATION; + + if (xTicksToWait > (TickType_t) 0) { + prvAddCurrentTaskToDelayedList(xTicksToWait, pdTRUE); + traceTASK_NOTIFY_WAIT_BLOCK(uxIndexToWait); + + /* All ports are written to allow a yield in a critical + * section (some will yield immediately, others wait until the + * critical section exits) - but it is not something that + * application code should ever do. */ + portYIELD_WITHIN_API(); + } else { + mtCOVERAGE_TEST_MARKER(); + } + } else { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + taskENTER_CRITICAL(); + { + traceTASK_NOTIFY_WAIT(uxIndexToWait); + + if (pulNotificationValue != NULL) { + /* Output the current notification value, which may or may not + * have changed. */ + *pulNotificationValue = pxCurrentTCB->ulNotifiedValue[uxIndexToWait]; + } + + /* If ucNotifyValue is set then either the task never entered the + * blocked state (because a notification was already pending) or the + * task unblocked because of a notification. Otherwise the task + * unblocked because of a timeout. */ + if (pxCurrentTCB->ucNotifyState[uxIndexToWait] != taskNOTIFICATION_RECEIVED) { + /* A notification was not received. */ + xReturn = pdFALSE; + } else { + /* A notification was already pending or a notification was + * received while the task was waiting. */ + pxCurrentTCB->ulNotifiedValue[uxIndexToWait] &= ~ulBitsToClearOnExit; + xReturn = pdTRUE; + } + + pxCurrentTCB->ucNotifyState[uxIndexToWait] = taskNOT_WAITING_NOTIFICATION; + } + taskEXIT_CRITICAL(); + + return xReturn; +} + +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + +#if (configUSE_TASK_NOTIFICATIONS == 1) + +BaseType_t xTaskGenericNotify(TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + uint32_t ulValue, + eNotifyAction eAction, + uint32_t *pulPreviousNotificationValue) { + TCB_t *pxTCB; + BaseType_t xReturn = pdPASS; + uint8_t ucOriginalNotifyState; + + configASSERT(uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES); + configASSERT(xTaskToNotify); + pxTCB = xTaskToNotify; + + taskENTER_CRITICAL(); + { + if (pulPreviousNotificationValue != NULL) { + *pulPreviousNotificationValue = pxTCB->ulNotifiedValue[uxIndexToNotify]; + } + + ucOriginalNotifyState = pxTCB->ucNotifyState[uxIndexToNotify]; + + pxTCB->ucNotifyState[uxIndexToNotify] = taskNOTIFICATION_RECEIVED; + + switch (eAction) { + case eSetBits: + pxTCB->ulNotifiedValue[uxIndexToNotify] |= ulValue; + break; + + case eIncrement: + (pxTCB->ulNotifiedValue[uxIndexToNotify])++; + break; + + case eSetValueWithOverwrite: + pxTCB->ulNotifiedValue[uxIndexToNotify] = ulValue; + break; + + case eSetValueWithoutOverwrite: + + if (ucOriginalNotifyState != taskNOTIFICATION_RECEIVED) { + pxTCB->ulNotifiedValue[uxIndexToNotify] = ulValue; + } else { + /* The value could not be written to the task. */ + xReturn = pdFAIL; + } + + break; + + case eNoAction: + + /* The task is being notified without its notify value being + * updated. */ + break; + + default: + + /* Should not get here if all enums are handled. + * Artificially force an assert by testing a value the + * compiler can't assume is const. */ + configASSERT(xTickCount == (TickType_t) 0); + + break; + } + + traceTASK_NOTIFY(uxIndexToNotify); + + /* If the task is in the blocked state specifically to wait for a + * notification then unblock it now. */ + if (ucOriginalNotifyState == taskWAITING_NOTIFICATION) { + (void) uxListRemove(&(pxTCB->xStateListItem));prvAddTaskToReadyList(pxTCB); + + /* The task should not have been on an event list. */ + configASSERT(listLIST_ITEM_CONTAINER(&(pxTCB->xEventListItem)) == NULL); + +#if (configUSE_TICKLESS_IDLE != 0) + { + /* If a task is blocked waiting for a notification then + * xNextTaskUnblockTime might be set to the blocked task's time + * out time. If the task is unblocked for a reason other than + * a timeout xNextTaskUnblockTime is normally left unchanged, + * because it will automatically get reset to a new value when + * the tick count equals xNextTaskUnblockTime. However if + * tickless idling is used it might be more important to enter + * sleep mode at the earliest possible time - so reset + * xNextTaskUnblockTime here to ensure it is updated at the + * earliest possible time. */ + prvResetNextTaskUnblockTime(); + } +#endif + + if (pxTCB->uxPriority > pxCurrentTCB->uxPriority) { + /* The notified task has a priority above the currently + * executing task so a yield is required. */ + taskYIELD_IF_USING_PREEMPTION(); + } else { + mtCOVERAGE_TEST_MARKER(); + } + } else { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + return xReturn; +} + +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + +#if (configUSE_TASK_NOTIFICATIONS == 1) + +BaseType_t xTaskGenericNotifyFromISR(TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + uint32_t ulValue, + eNotifyAction eAction, + uint32_t *pulPreviousNotificationValue, + BaseType_t *pxHigherPriorityTaskWoken) { + TCB_t *pxTCB; + uint8_t ucOriginalNotifyState; + BaseType_t xReturn = pdPASS; + UBaseType_t uxSavedInterruptStatus; + + configASSERT(xTaskToNotify); + configASSERT(uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES); + + /* RTOS ports that support interrupt nesting have the concept of a + * maximum system call (or maximum API call) interrupt priority. + * Interrupts that are above the maximum system call priority are keep + * permanently enabled, even when the RTOS kernel is in a critical section, + * but cannot make any calls to FreeRTOS API functions. If configASSERT() + * is defined in FreeRTOSConfig.h then + * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has + * been assigned a priority above the configured maximum system call + * priority. Only FreeRTOS functions that end in FromISR can be called + * from interrupts that have been assigned a priority at or (logically) + * below the maximum system call interrupt priority. FreeRTOS maintains a + * separate interrupt safe API to ensure interrupt entry is as fast and as + * simple as possible. More information (albeit Cortex-M specific) is + * provided on the following link: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + pxTCB = xTaskToNotify; + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + if (pulPreviousNotificationValue != NULL) { + *pulPreviousNotificationValue = pxTCB->ulNotifiedValue[uxIndexToNotify]; + } + + ucOriginalNotifyState = pxTCB->ucNotifyState[uxIndexToNotify]; + pxTCB->ucNotifyState[uxIndexToNotify] = taskNOTIFICATION_RECEIVED; + + switch (eAction) { + case eSetBits: + pxTCB->ulNotifiedValue[uxIndexToNotify] |= ulValue; + break; + + case eIncrement: + (pxTCB->ulNotifiedValue[uxIndexToNotify])++; + break; + + case eSetValueWithOverwrite: + pxTCB->ulNotifiedValue[uxIndexToNotify] = ulValue; + break; + + case eSetValueWithoutOverwrite: + + if (ucOriginalNotifyState != taskNOTIFICATION_RECEIVED) { + pxTCB->ulNotifiedValue[uxIndexToNotify] = ulValue; + } else { + /* The value could not be written to the task. */ + xReturn = pdFAIL; + } + + break; + + case eNoAction: + + /* The task is being notified without its notify value being + * updated. */ + break; + + default: + + /* Should not get here if all enums are handled. + * Artificially force an assert by testing a value the + * compiler can't assume is const. */ + configASSERT(xTickCount == (TickType_t) 0); + break; + } + + traceTASK_NOTIFY_FROM_ISR(uxIndexToNotify); + + /* If the task is in the blocked state specifically to wait for a + * notification then unblock it now. */ + if (ucOriginalNotifyState == taskWAITING_NOTIFICATION) { + /* The task should not have been on an event list. */ + configASSERT(listLIST_ITEM_CONTAINER(&(pxTCB->xEventListItem)) == NULL); + + if (uxSchedulerSuspended == (UBaseType_t) pdFALSE) { + (void) uxListRemove(&(pxTCB->xStateListItem));prvAddTaskToReadyList(pxTCB); + } else { + /* The delayed and ready lists cannot be accessed, so hold + * this task pending until the scheduler is resumed. */ + vListInsertEnd(&(xPendingReadyList), &(pxTCB->xEventListItem)); + } + + if (pxTCB->uxPriority > pxCurrentTCB->uxPriority) { + /* The notified task has a priority above the currently + * executing task so a yield is required. */ + if (pxHigherPriorityTaskWoken != NULL) { + *pxHigherPriorityTaskWoken = pdTRUE; + } + + /* Mark that a yield is pending in case the user is not + * using the "xHigherPriorityTaskWoken" parameter to an ISR + * safe FreeRTOS function. */ + xYieldPending = pdTRUE; + } else { + mtCOVERAGE_TEST_MARKER(); + } + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR(uxSavedInterruptStatus); + + return xReturn; +} + +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + +#if (configUSE_TASK_NOTIFICATIONS == 1) + +void vTaskGenericNotifyGiveFromISR(TaskHandle_t xTaskToNotify, + UBaseType_t uxIndexToNotify, + BaseType_t *pxHigherPriorityTaskWoken) { + TCB_t *pxTCB; + uint8_t ucOriginalNotifyState; + UBaseType_t uxSavedInterruptStatus; + + configASSERT(xTaskToNotify); + configASSERT(uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES); + + /* RTOS ports that support interrupt nesting have the concept of a + * maximum system call (or maximum API call) interrupt priority. + * Interrupts that are above the maximum system call priority are keep + * permanently enabled, even when the RTOS kernel is in a critical section, + * but cannot make any calls to FreeRTOS API functions. If configASSERT() + * is defined in FreeRTOSConfig.h then + * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion + * failure if a FreeRTOS API function is called from an interrupt that has + * been assigned a priority above the configured maximum system call + * priority. Only FreeRTOS functions that end in FromISR can be called + * from interrupts that have been assigned a priority at or (logically) + * below the maximum system call interrupt priority. FreeRTOS maintains a + * separate interrupt safe API to ensure interrupt entry is as fast and as + * simple as possible. More information (albeit Cortex-M specific) is + * provided on the following link: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); + + pxTCB = xTaskToNotify; + + uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); + { + ucOriginalNotifyState = pxTCB->ucNotifyState[uxIndexToNotify]; + pxTCB->ucNotifyState[uxIndexToNotify] = taskNOTIFICATION_RECEIVED; + + /* 'Giving' is equivalent to incrementing a count in a counting + * semaphore. */ + (pxTCB->ulNotifiedValue[uxIndexToNotify])++; + + traceTASK_NOTIFY_GIVE_FROM_ISR(uxIndexToNotify); + + /* If the task is in the blocked state specifically to wait for a + * notification then unblock it now. */ + if (ucOriginalNotifyState == taskWAITING_NOTIFICATION) { + /* The task should not have been on an event list. */ + configASSERT(listLIST_ITEM_CONTAINER(&(pxTCB->xEventListItem)) == NULL); + + if (uxSchedulerSuspended == (UBaseType_t) pdFALSE) { + (void) uxListRemove(&(pxTCB->xStateListItem));prvAddTaskToReadyList(pxTCB); + } else { + /* The delayed and ready lists cannot be accessed, so hold + * this task pending until the scheduler is resumed. */ + vListInsertEnd(&(xPendingReadyList), &(pxTCB->xEventListItem)); + } + + if (pxTCB->uxPriority > pxCurrentTCB->uxPriority) { + /* The notified task has a priority above the currently + * executing task so a yield is required. */ + if (pxHigherPriorityTaskWoken != NULL) { + *pxHigherPriorityTaskWoken = pdTRUE; + } + + /* Mark that a yield is pending in case the user is not + * using the "xHigherPriorityTaskWoken" parameter in an ISR + * safe FreeRTOS function. */ + xYieldPending = pdTRUE; + } else { + mtCOVERAGE_TEST_MARKER(); + } + } + } + portCLEAR_INTERRUPT_MASK_FROM_ISR(uxSavedInterruptStatus); +} + +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + +#if (configUSE_TASK_NOTIFICATIONS == 1) + +BaseType_t xTaskGenericNotifyStateClear(TaskHandle_t xTask, + UBaseType_t uxIndexToClear) { + TCB_t *pxTCB; + BaseType_t xReturn; + + configASSERT(uxIndexToClear < configTASK_NOTIFICATION_ARRAY_ENTRIES); + + /* If null is passed in here then it is the calling task that is having + * its notification state cleared. */ + pxTCB = prvGetTCBFromHandle(xTask); + + taskENTER_CRITICAL(); + { + if (pxTCB->ucNotifyState[uxIndexToClear] == taskNOTIFICATION_RECEIVED) { + pxTCB->ucNotifyState[uxIndexToClear] = taskNOT_WAITING_NOTIFICATION; + xReturn = pdPASS; + } else { + xReturn = pdFAIL; + } + } + taskEXIT_CRITICAL(); + + return xReturn; +} + +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + +#if (configUSE_TASK_NOTIFICATIONS == 1) + +uint32_t ulTaskGenericNotifyValueClear(TaskHandle_t xTask, + UBaseType_t uxIndexToClear, + uint32_t ulBitsToClear) { + TCB_t *pxTCB; + uint32_t ulReturn; + + /* If null is passed in here then it is the calling task that is having + * its notification state cleared. */ + pxTCB = prvGetTCBFromHandle(xTask); + + taskENTER_CRITICAL(); + { + /* Return the notification as it was before the bits were cleared, + * then clear the bit mask. */ + ulReturn = pxTCB->ulNotifiedValue[uxIndexToClear]; + pxTCB->ulNotifiedValue[uxIndexToClear] &= ~ulBitsToClear; + } + taskEXIT_CRITICAL(); + + return ulReturn; +} + +#endif /* configUSE_TASK_NOTIFICATIONS */ +/*-----------------------------------------------------------*/ + +#if ((configGENERATE_RUN_TIME_STATS == 1) && (INCLUDE_xTaskGetIdleTaskHandle == 1)) + + uint32_t ulTaskGetIdleRunTimeCounter( void ) + { + return xIdleTaskHandle->ulRunTimeCounter; + } + +#endif + +/*-----------------------------------------------------------*/ + +static void prvAddCurrentTaskToDelayedList(TickType_t xTicksToWait, + const BaseType_t xCanBlockIndefinitely) { + TickType_t xTimeToWake; + const TickType_t xConstTickCount = xTickCount; + +#if (INCLUDE_xTaskAbortDelay == 1) + { + /* About to enter a delayed list, so ensure the ucDelayAborted flag is + * reset to pdFALSE so it can be detected as having been set to pdTRUE + * when the task leaves the Blocked state. */ + pxCurrentTCB->ucDelayAborted = pdFALSE; + } +#endif + + /* Remove the task from the ready list before adding it to the blocked list + * as the same list item is used for both lists. */ + if (uxListRemove(&(pxCurrentTCB->xStateListItem)) == (UBaseType_t) 0) { + /* The current task must be in a ready list, so there is no need to + * check, and the port reset macro can be called directly. */ + portRESET_READY_PRIORITY(pxCurrentTCB->uxPriority, + uxTopReadyPriority); /*lint !e931 pxCurrentTCB cannot change as it is the calling task. pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */ + } else { + mtCOVERAGE_TEST_MARKER(); + } + +#if (INCLUDE_vTaskSuspend == 1) + { + if ((xTicksToWait == portMAX_DELAY) && (xCanBlockIndefinitely != pdFALSE)) { + /* Add the task to the suspended task list instead of a delayed task + * list to ensure it is not woken by a timing event. It will block + * indefinitely. */ + vListInsertEnd(&xSuspendedTaskList, &(pxCurrentTCB->xStateListItem)); + } else { + /* Calculate the time at which the task should be woken if the event + * does not occur. This may overflow but this doesn't matter, the + * kernel will manage it correctly. */ + xTimeToWake = xConstTickCount + xTicksToWait; + + /* The list item will be inserted in wake time order. */ + listSET_LIST_ITEM_VALUE(&(pxCurrentTCB->xStateListItem), xTimeToWake); + + if (xTimeToWake < xConstTickCount) { + /* Wake time has overflowed. Place this item in the overflow + * list. */ + vListInsert(pxOverflowDelayedTaskList, &(pxCurrentTCB->xStateListItem)); + } else { + /* The wake time has not overflowed, so the current block list + * is used. */ + vListInsert(pxDelayedTaskList, &(pxCurrentTCB->xStateListItem)); + + /* If the task entering the blocked state was placed at the + * head of the list of blocked tasks then xNextTaskUnblockTime + * needs to be updated too. */ + if (xTimeToWake < xNextTaskUnblockTime) { + xNextTaskUnblockTime = xTimeToWake; + } else { + mtCOVERAGE_TEST_MARKER(); + } + } + } + } +#else /* INCLUDE_vTaskSuspend */ + { + /* Calculate the time at which the task should be woken if the event + * does not occur. This may overflow but this doesn't matter, the kernel + * will manage it correctly. */ + xTimeToWake = xConstTickCount + xTicksToWait; + + /* The list item will be inserted in wake time order. */ + listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake ); + + if( xTimeToWake < xConstTickCount ) + { + /* Wake time has overflowed. Place this item in the overflow list. */ + vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); + } + else + { + /* The wake time has not overflowed, so the current block list is used. */ + vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); + + /* If the task entering the blocked state was placed at the head of the + * list of blocked tasks then xNextTaskUnblockTime needs to be updated + * too. */ + if( xTimeToWake < xNextTaskUnblockTime ) + { + xNextTaskUnblockTime = xTimeToWake; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */ + ( void ) xCanBlockIndefinitely; + } +#endif /* INCLUDE_vTaskSuspend */ +} + +/* Code below here allows additional code to be inserted into this source file, + * especially where access to file scope functions and data is needed (for example + * when performing module tests). */ + +#ifdef FREERTOS_MODULE_TEST +#include "tasks_test_access_functions.h" +#endif + + +#if (configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1) + + #include "freertos_tasks_c_additions.h" + + #ifdef FREERTOS_TASKS_C_ADDITIONS_INIT + static void freertos_tasks_c_additions_init( void ) + { + FREERTOS_TASKS_C_ADDITIONS_INIT(); + } + #endif + +#endif /* if ( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 ) */ + + +// Добавьте в конец файла task.c (после всех функций) + +void vTaskGetCurrentTaskStackInfo( void ** ppvStackStart, void ** ppvStackEnd ) +{ + TCB_t * pxTCB = pxCurrentTCB; + + if( ppvStackStart != NULL ) + { + *ppvStackStart = ( void * ) pxTCB->pxStack; + } + + if( ppvStackEnd != NULL ) + { +#if ( configRECORD_STACK_HIGH_ADDRESS == 1 ) + *ppvStackEnd = ( void * ) pxTCB->pxEndOfStack; +#else + // Если pxEndOfStack не определён, можно вычислить его, зная размер стека. + // Но размер стека (в словах) не хранится в TCB. Поэтому либо включите + // configRECORD_STACK_HIGH_ADDRESS, либо используйте фиксированный лимит. + *ppvStackEnd = NULL; +#endif + } +} \ No newline at end of file diff --git a/MODULES/FreeRTOS/src/timers.c b/MODULES/FreeRTOS/src/timers.c new file mode 100644 index 0000000..583b269 --- /dev/null +++ b/MODULES/FreeRTOS/src/timers.c @@ -0,0 +1,1144 @@ +/* + * FreeRTOS Kernel V10.4.3 LTS Patch 2 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" + +#if ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 0 ) + #error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available. +#endif + +/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified + * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined + * for the header files above, but not in this file, in order to generate the + * correct privileged Vs unprivileged linkage and placement. */ +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e9021 !e961 !e750. */ + + +/* This entire source file will be skipped if the application is not configured + * to include software timer functionality. This #if is closed at the very bottom + * of this file. If you want to include software timer functionality then ensure + * configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */ +#if ( configUSE_TIMERS == 1 ) + +/* Misc definitions. */ + #define tmrNO_DELAY ( TickType_t ) 0U + +/* The name assigned to the timer service task. This can be overridden by + * defining trmTIMER_SERVICE_TASK_NAME in FreeRTOSConfig.h. */ + #ifndef configTIMER_SERVICE_TASK_NAME + #define configTIMER_SERVICE_TASK_NAME "Tmr Svc" + #endif + +/* Bit definitions used in the ucStatus member of a timer structure. */ + #define tmrSTATUS_IS_ACTIVE ( ( uint8_t ) 0x01 ) + #define tmrSTATUS_IS_STATICALLY_ALLOCATED ( ( uint8_t ) 0x02 ) + #define tmrSTATUS_IS_AUTORELOAD ( ( uint8_t ) 0x04 ) + +/* The definition of the timers themselves. */ + typedef struct tmrTimerControl /* The old naming convention is used to prevent breaking kernel aware debuggers. */ + { + const char * pcTimerName; /*<< Text name. This is not used by the kernel, it is included simply to make debugging easier. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + ListItem_t xTimerListItem; /*<< Standard linked list item as used by all kernel features for event management. */ + TickType_t xTimerPeriodInTicks; /*<< How quickly and often the timer expires. */ + void * pvTimerID; /*<< An ID to identify the timer. This allows the timer to be identified when the same callback is used for multiple timers. */ + TimerCallbackFunction_t pxCallbackFunction; /*<< The function that will be called when the timer expires. */ + #if ( configUSE_TRACE_FACILITY == 1 ) + UBaseType_t uxTimerNumber; /*<< An ID assigned by trace tools such as FreeRTOS+Trace */ + #endif + uint8_t ucStatus; /*<< Holds bits to say if the timer was statically allocated or not, and if it is active or not. */ + } xTIMER; + +/* The old xTIMER name is maintained above then typedefed to the new Timer_t + * name below to enable the use of older kernel aware debuggers. */ + typedef xTIMER Timer_t; + +/* The definition of messages that can be sent and received on the timer queue. + * Two types of message can be queued - messages that manipulate a software timer, + * and messages that request the execution of a non-timer related callback. The + * two message types are defined in two separate structures, xTimerParametersType + * and xCallbackParametersType respectively. */ + typedef struct tmrTimerParameters + { + TickType_t xMessageValue; /*<< An optional value used by a subset of commands, for example, when changing the period of a timer. */ + Timer_t * pxTimer; /*<< The timer to which the command will be applied. */ + } TimerParameter_t; + + + typedef struct tmrCallbackParameters + { + PendedFunction_t pxCallbackFunction; /* << The callback function to execute. */ + void * pvParameter1; /* << The value that will be used as the callback functions first parameter. */ + uint32_t ulParameter2; /* << The value that will be used as the callback functions second parameter. */ + } CallbackParameters_t; + +/* The structure that contains the two message types, along with an identifier + * that is used to determine which message type is valid. */ + typedef struct tmrTimerQueueMessage + { + BaseType_t xMessageID; /*<< The command being sent to the timer service task. */ + union + { + TimerParameter_t xTimerParameters; + + /* Don't include xCallbackParameters if it is not going to be used as + * it makes the structure (and therefore the timer queue) larger. */ + #if ( INCLUDE_xTimerPendFunctionCall == 1 ) + CallbackParameters_t xCallbackParameters; + #endif /* INCLUDE_xTimerPendFunctionCall */ + } u; + } DaemonTaskMessage_t; + +/*lint -save -e956 A manual analysis and inspection has been used to determine + * which static variables must be declared volatile. */ + +/* The list in which active timers are stored. Timers are referenced in expire + * time order, with the nearest expiry time at the front of the list. Only the + * timer service task is allowed to access these lists. + * xActiveTimerList1 and xActiveTimerList2 could be at function scope but that + * breaks some kernel aware debuggers, and debuggers that reply on removing the + * static qualifier. */ + PRIVILEGED_DATA static List_t xActiveTimerList1; + PRIVILEGED_DATA static List_t xActiveTimerList2; + PRIVILEGED_DATA static List_t * pxCurrentTimerList; + PRIVILEGED_DATA static List_t * pxOverflowTimerList; + +/* A queue that is used to send commands to the timer service task. */ + PRIVILEGED_DATA static QueueHandle_t xTimerQueue = NULL; + PRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL; + +/*lint -restore */ + +/*-----------------------------------------------------------*/ + +/* + * Initialise the infrastructure used by the timer service task if it has not + * been initialised already. + */ + static void prvCheckForValidListAndQueue( void ) PRIVILEGED_FUNCTION; + +/* + * The timer service task (daemon). Timer functionality is controlled by this + * task. Other tasks communicate with the timer service task using the + * xTimerQueue queue. + */ + static portTASK_FUNCTION_PROTO( prvTimerTask, pvParameters ) PRIVILEGED_FUNCTION; + +/* + * Called by the timer service task to interpret and process a command it + * received on the timer queue. + */ + static void prvProcessReceivedCommands( void ) PRIVILEGED_FUNCTION; + +/* + * Insert the timer into either xActiveTimerList1, or xActiveTimerList2, + * depending on if the expire time causes a timer counter overflow. + */ + static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, + const TickType_t xNextExpiryTime, + const TickType_t xTimeNow, + const TickType_t xCommandTime ) PRIVILEGED_FUNCTION; + +/* + * An active timer has reached its expire time. Reload the timer if it is an + * auto-reload timer, then call its callback. + */ + static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, + const TickType_t xTimeNow ) PRIVILEGED_FUNCTION; + +/* + * The tick count has overflowed. Switch the timer lists after ensuring the + * current timer list does not still reference some timers. + */ + static void prvSwitchTimerLists( void ) PRIVILEGED_FUNCTION; + +/* + * Obtain the current tick count, setting *pxTimerListsWereSwitched to pdTRUE + * if a tick count overflow occurred since prvSampleTimeNow() was last called. + */ + static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) PRIVILEGED_FUNCTION; + +/* + * If the timer list contains any active timers then return the expire time of + * the timer that will expire first and set *pxListWasEmpty to false. If the + * timer list does not contain any timers then return 0 and set *pxListWasEmpty + * to pdTRUE. + */ + static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) PRIVILEGED_FUNCTION; + +/* + * If a timer has expired, process it. Otherwise, block the timer service task + * until either a timer does expire or a command is received. + */ + static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, + BaseType_t xListWasEmpty ) PRIVILEGED_FUNCTION; + +/* + * Called after a Timer_t structure has been allocated either statically or + * dynamically to fill in the structure's members. + */ + static void prvInitialiseNewTimer( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const TickType_t xTimerPeriodInTicks, + const UBaseType_t uxAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction, + Timer_t * pxNewTimer ) PRIVILEGED_FUNCTION; +/*-----------------------------------------------------------*/ + + BaseType_t xTimerCreateTimerTask( void ) + { + BaseType_t xReturn = pdFAIL; + + /* This function is called when the scheduler is started if + * configUSE_TIMERS is set to 1. Check that the infrastructure used by the + * timer service task has been created/initialised. If timers have already + * been created then the initialisation will already have been performed. */ + prvCheckForValidListAndQueue(); + + if( xTimerQueue != NULL ) + { + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + StaticTask_t * pxTimerTaskTCBBuffer = NULL; + StackType_t * pxTimerTaskStackBuffer = NULL; + uint32_t ulTimerTaskStackSize; + + vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize ); + xTimerTaskHandle = xTaskCreateStatic( prvTimerTask, + configTIMER_SERVICE_TASK_NAME, + ulTimerTaskStackSize, + NULL, + ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, + pxTimerTaskStackBuffer, + pxTimerTaskTCBBuffer ); + + if( xTimerTaskHandle != NULL ) + { + xReturn = pdPASS; + } + } + #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ + { + xReturn = xTaskCreate( prvTimerTask, + configTIMER_SERVICE_TASK_NAME, + configTIMER_TASK_STACK_DEPTH, + NULL, + ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, + &xTimerTaskHandle ); + } + #endif /* configSUPPORT_STATIC_ALLOCATION */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + configASSERT( xReturn ); + return xReturn; + } +/*-----------------------------------------------------------*/ + + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + + TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const TickType_t xTimerPeriodInTicks, + const UBaseType_t uxAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction ) + { + Timer_t * pxNewTimer; + + pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */ + + if( pxNewTimer != NULL ) + { + /* Status is thus far zero as the timer is not created statically + * and has not been started. The auto-reload bit may get set in + * prvInitialiseNewTimer. */ + pxNewTimer->ucStatus = 0x00; + prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer ); + } + + return pxNewTimer; + } + + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + + TimerHandle_t xTimerCreateStatic( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const TickType_t xTimerPeriodInTicks, + const UBaseType_t uxAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction, + StaticTimer_t * pxTimerBuffer ) + { + Timer_t * pxNewTimer; + + #if ( configASSERT_DEFINED == 1 ) + { + /* Sanity check that the size of the structure used to declare a + * variable of type StaticTimer_t equals the size of the real timer + * structure. */ + volatile size_t xSize = sizeof( StaticTimer_t ); + configASSERT( xSize == sizeof( Timer_t ) ); + ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ + } + #endif /* configASSERT_DEFINED */ + + /* A pointer to a StaticTimer_t structure MUST be provided, use it. */ + configASSERT( pxTimerBuffer ); + pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 !e9087 StaticTimer_t is a pointer to a Timer_t, so guaranteed to be aligned and sized correctly (checked by an assert()), so this is safe. */ + + if( pxNewTimer != NULL ) + { + /* Timers can be created statically or dynamically so note this + * timer was created statically in case it is later deleted. The + * auto-reload bit may get set in prvInitialiseNewTimer(). */ + pxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED; + + prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer ); + } + + return pxNewTimer; + } + + #endif /* configSUPPORT_STATIC_ALLOCATION */ +/*-----------------------------------------------------------*/ + + static void prvInitialiseNewTimer( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + const TickType_t xTimerPeriodInTicks, + const UBaseType_t uxAutoReload, + void * const pvTimerID, + TimerCallbackFunction_t pxCallbackFunction, + Timer_t * pxNewTimer ) + { + /* 0 is not a valid value for xTimerPeriodInTicks. */ + configASSERT( ( xTimerPeriodInTicks > 0 ) ); + + if( pxNewTimer != NULL ) + { + /* Ensure the infrastructure used by the timer service task has been + * created/initialised. */ + prvCheckForValidListAndQueue(); + + /* Initialise the timer structure members using the function + * parameters. */ + pxNewTimer->pcTimerName = pcTimerName; + pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks; + pxNewTimer->pvTimerID = pvTimerID; + pxNewTimer->pxCallbackFunction = pxCallbackFunction; + vListInitialiseItem( &( pxNewTimer->xTimerListItem ) ); + + if( uxAutoReload != pdFALSE ) + { + pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD; + } + + traceTIMER_CREATE( pxNewTimer ); + } + } +/*-----------------------------------------------------------*/ + + BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, + const BaseType_t xCommandID, + const TickType_t xOptionalValue, + BaseType_t * const pxHigherPriorityTaskWoken, + const TickType_t xTicksToWait ) + { + BaseType_t xReturn = pdFAIL; + DaemonTaskMessage_t xMessage; + + configASSERT( xTimer ); + + /* Send a message to the timer service task to perform a particular action + * on a particular timer definition. */ + if( xTimerQueue != NULL ) + { + /* Send a command to the timer service task to start the xTimer timer. */ + xMessage.xMessageID = xCommandID; + xMessage.u.xTimerParameters.xMessageValue = xOptionalValue; + xMessage.u.xTimerParameters.pxTimer = xTimer; + + if( xCommandID < tmrFIRST_FROM_ISR_COMMAND ) + { + if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING ) + { + xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait ); + } + else + { + xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY ); + } + } + else + { + xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken ); + } + + traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xReturn; + } +/*-----------------------------------------------------------*/ + + TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) + { + /* If xTimerGetTimerDaemonTaskHandle() is called before the scheduler has been + * started, then xTimerTaskHandle will be NULL. */ + configASSERT( ( xTimerTaskHandle != NULL ) ); + return xTimerTaskHandle; + } +/*-----------------------------------------------------------*/ + + TickType_t xTimerGetPeriod( TimerHandle_t xTimer ) + { + Timer_t * pxTimer = xTimer; + + configASSERT( xTimer ); + return pxTimer->xTimerPeriodInTicks; + } +/*-----------------------------------------------------------*/ + + void vTimerSetReloadMode( TimerHandle_t xTimer, + const UBaseType_t uxAutoReload ) + { + Timer_t * pxTimer = xTimer; + + configASSERT( xTimer ); + taskENTER_CRITICAL(); + { + if( uxAutoReload != pdFALSE ) + { + pxTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD; + } + else + { + pxTimer->ucStatus &= ~tmrSTATUS_IS_AUTORELOAD; + } + } + taskEXIT_CRITICAL(); + } +/*-----------------------------------------------------------*/ + + UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer ) + { + Timer_t * pxTimer = xTimer; + UBaseType_t uxReturn; + + configASSERT( xTimer ); + taskENTER_CRITICAL(); + { + if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) == 0 ) + { + /* Not an auto-reload timer. */ + uxReturn = ( UBaseType_t ) pdFALSE; + } + else + { + /* Is an auto-reload timer. */ + uxReturn = ( UBaseType_t ) pdTRUE; + } + } + taskEXIT_CRITICAL(); + + return uxReturn; + } +/*-----------------------------------------------------------*/ + + TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) + { + Timer_t * pxTimer = xTimer; + TickType_t xReturn; + + configASSERT( xTimer ); + xReturn = listGET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ) ); + return xReturn; + } +/*-----------------------------------------------------------*/ + + const char * pcTimerGetName( TimerHandle_t xTimer ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ + { + Timer_t * pxTimer = xTimer; + + configASSERT( xTimer ); + return pxTimer->pcTimerName; + } +/*-----------------------------------------------------------*/ + + static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, + const TickType_t xTimeNow ) + { + BaseType_t xResult; + Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + + /* Remove the timer from the list of active timers. A check has already + * been performed to ensure the list is not empty. */ + + ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); + traceTIMER_EXPIRED( pxTimer ); + + /* If the timer is an auto-reload timer then calculate the next + * expiry time and re-insert the timer in the list of active timers. */ + if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) + { + /* The timer is inserted into a list using a time relative to anything + * other than the current time. It will therefore be inserted into the + * correct list relative to the time this task thinks it is now. */ + if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE ) + { + /* The timer expired before it was added to the active timer + * list. Reload it now. */ + xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY ); + configASSERT( xResult ); + ( void ) xResult; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; + mtCOVERAGE_TEST_MARKER(); + } + + /* Call the timer callback. */ + pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); + } +/*-----------------------------------------------------------*/ + + static portTASK_FUNCTION( prvTimerTask, pvParameters ) + { + TickType_t xNextExpireTime; + BaseType_t xListWasEmpty; + + /* Just to avoid compiler warnings. */ + ( void ) pvParameters; + + #if ( configUSE_DAEMON_TASK_STARTUP_HOOK == 1 ) + { + extern void vApplicationDaemonTaskStartupHook( void ); + + /* Allow the application writer to execute some code in the context of + * this task at the point the task starts executing. This is useful if the + * application includes initialisation code that would benefit from + * executing after the scheduler has been started. */ + vApplicationDaemonTaskStartupHook(); + } + #endif /* configUSE_DAEMON_TASK_STARTUP_HOOK */ + + for( ; ; ) + { + /* Query the timers list to see if it contains any timers, and if so, + * obtain the time at which the next timer will expire. */ + xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); + + /* If a timer has expired, process it. Otherwise, block this task + * until either a timer does expire, or a command is received. */ + prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty ); + + /* Empty the command queue. */ + prvProcessReceivedCommands(); + } + } +/*-----------------------------------------------------------*/ + + static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, + BaseType_t xListWasEmpty ) + { + TickType_t xTimeNow; + BaseType_t xTimerListsWereSwitched; + + vTaskSuspendAll(); + { + /* Obtain the time now to make an assessment as to whether the timer + * has expired or not. If obtaining the time causes the lists to switch + * then don't process this timer as any timers that remained in the list + * when the lists were switched will have been processed within the + * prvSampleTimeNow() function. */ + xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); + + if( xTimerListsWereSwitched == pdFALSE ) + { + /* The tick count has not overflowed, has the timer expired? */ + if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) ) + { + ( void ) xTaskResumeAll(); + prvProcessExpiredTimer( xNextExpireTime, xTimeNow ); + } + else + { + /* The tick count has not overflowed, and the next expire + * time has not been reached yet. This task should therefore + * block to wait for the next expire time or a command to be + * received - whichever comes first. The following line cannot + * be reached unless xNextExpireTime > xTimeNow, except in the + * case when the current timer list is empty. */ + if( xListWasEmpty != pdFALSE ) + { + /* The current timer list is empty - is the overflow list + * also empty? */ + xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList ); + } + + vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty ); + + if( xTaskResumeAll() == pdFALSE ) + { + /* Yield to wait for either a command to arrive, or the + * block time to expire. If a command arrived between the + * critical section being exited and this yield then the yield + * will not cause the task to block. */ + portYIELD_WITHIN_API(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + } + else + { + ( void ) xTaskResumeAll(); + } + } + } +/*-----------------------------------------------------------*/ + + static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) + { + TickType_t xNextExpireTime; + + /* Timers are listed in expiry time order, with the head of the list + * referencing the task that will expire first. Obtain the time at which + * the timer with the nearest expiry time will expire. If there are no + * active timers then just set the next expire time to 0. That will cause + * this task to unblock when the tick count overflows, at which point the + * timer lists will be switched and the next expiry time can be + * re-assessed. */ + *pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList ); + + if( *pxListWasEmpty == pdFALSE ) + { + xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); + } + else + { + /* Ensure the task unblocks when the tick count rolls over. */ + xNextExpireTime = ( TickType_t ) 0U; + } + + return xNextExpireTime; + } +/*-----------------------------------------------------------*/ + + static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) + { + TickType_t xTimeNow; + PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */ + + xTimeNow = xTaskGetTickCount(); + + if( xTimeNow < xLastTime ) + { + prvSwitchTimerLists(); + *pxTimerListsWereSwitched = pdTRUE; + } + else + { + *pxTimerListsWereSwitched = pdFALSE; + } + + xLastTime = xTimeNow; + + return xTimeNow; + } +/*-----------------------------------------------------------*/ + + static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, + const TickType_t xNextExpiryTime, + const TickType_t xTimeNow, + const TickType_t xCommandTime ) + { + BaseType_t xProcessTimerNow = pdFALSE; + + listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime ); + listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); + + if( xNextExpiryTime <= xTimeNow ) + { + /* Has the expiry time elapsed between the command to start/reset a + * timer was issued, and the time the command was processed? */ + if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ + { + /* The time between a command being issued and the command being + * processed actually exceeds the timers period. */ + xProcessTimerNow = pdTRUE; + } + else + { + vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) ); + } + } + else + { + if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) ) + { + /* If, since the command was issued, the tick count has overflowed + * but the expiry time has not, then the timer must have already passed + * its expiry time and should be processed immediately. */ + xProcessTimerNow = pdTRUE; + } + else + { + vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); + } + } + + return xProcessTimerNow; + } +/*-----------------------------------------------------------*/ + + static void prvProcessReceivedCommands( void ) + { + DaemonTaskMessage_t xMessage; + Timer_t * pxTimer; + BaseType_t xTimerListsWereSwitched, xResult; + TickType_t xTimeNow; + + while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ + { + #if ( INCLUDE_xTimerPendFunctionCall == 1 ) + { + /* Negative commands are pended function calls rather than timer + * commands. */ + if( xMessage.xMessageID < ( BaseType_t ) 0 ) + { + const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters ); + + /* The timer uses the xCallbackParameters member to request a + * callback be executed. Check the callback is not NULL. */ + configASSERT( pxCallback ); + + /* Call the function. */ + pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* INCLUDE_xTimerPendFunctionCall */ + + /* Commands that are positive are timer commands rather than pended + * function calls. */ + if( xMessage.xMessageID >= ( BaseType_t ) 0 ) + { + /* The messages uses the xTimerParameters member to work on a + * software timer. */ + pxTimer = xMessage.u.xTimerParameters.pxTimer; + + if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */ + { + /* The timer is in a list, remove it. */ + ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.u.xTimerParameters.xMessageValue ); + + /* In this case the xTimerListsWereSwitched parameter is not used, but + * it must be present in the function call. prvSampleTimeNow() must be + * called after the message is received from xTimerQueue so there is no + * possibility of a higher priority task adding a message to the message + * queue with a time that is ahead of the timer daemon task (because it + * pre-empted the timer daemon task after the xTimeNow value was set). */ + xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); + + switch( xMessage.xMessageID ) + { + case tmrCOMMAND_START: + case tmrCOMMAND_START_FROM_ISR: + case tmrCOMMAND_RESET: + case tmrCOMMAND_RESET_FROM_ISR: + case tmrCOMMAND_START_DONT_TRACE: + /* Start or restart a timer. */ + pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; + + if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE ) + { + /* The timer expired before it was added to the active + * timer list. Process it now. */ + pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); + traceTIMER_EXPIRED( pxTimer ); + + if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) + { + xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY ); + configASSERT( xResult ); + ( void ) xResult; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + break; + + case tmrCOMMAND_STOP: + case tmrCOMMAND_STOP_FROM_ISR: + /* The timer has already been removed from the active list. */ + pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; + break; + + case tmrCOMMAND_CHANGE_PERIOD: + case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR: + pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; + pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue; + configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) ); + + /* The new period does not really have a reference, and can + * be longer or shorter than the old one. The command time is + * therefore set to the current time, and as the period cannot + * be zero the next expiry time can only be in the future, + * meaning (unlike for the xTimerStart() case above) there is + * no fail case that needs to be handled here. */ + ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow ); + break; + + case tmrCOMMAND_DELETE: + #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) + { + /* The timer has already been removed from the active list, + * just free up the memory if the memory was dynamically + * allocated. */ + if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 ) + { + vPortFree( pxTimer ); + } + else + { + pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; + } + } + #else /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */ + { + /* If dynamic allocation is not enabled, the memory + * could not have been dynamically allocated. So there is + * no need to free the memory - just mark the timer as + * "not active". */ + pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; + } + #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ + break; + + default: + /* Don't expect to get here. */ + break; + } + } + } + } +/*-----------------------------------------------------------*/ + + static void prvSwitchTimerLists( void ) + { + TickType_t xNextExpireTime, xReloadTime; + List_t * pxTemp; + Timer_t * pxTimer; + BaseType_t xResult; + + /* The tick count has overflowed. The timer lists must be switched. + * If there are any timers still referenced from the current timer list + * then they must have expired and should be processed before the lists + * are switched. */ + while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) + { + xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); + + /* Remove the timer from the list. */ + pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ + ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); + traceTIMER_EXPIRED( pxTimer ); + + /* Execute its callback, then send a command to restart the timer if + * it is an auto-reload timer. It cannot be restarted here as the lists + * have not yet been switched. */ + pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); + + if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) + { + /* Calculate the reload value, and if the reload value results in + * the timer going into the same timer list then it has already expired + * and the timer should be re-inserted into the current list so it is + * processed again within this loop. Otherwise a command should be sent + * to restart the timer to ensure it is only inserted into a list after + * the lists have been swapped. */ + xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ); + + if( xReloadTime > xNextExpireTime ) + { + listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime ); + listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); + vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); + } + else + { + xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY ); + configASSERT( xResult ); + ( void ) xResult; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + + pxTemp = pxCurrentTimerList; + pxCurrentTimerList = pxOverflowTimerList; + pxOverflowTimerList = pxTemp; + } +/*-----------------------------------------------------------*/ + + static void prvCheckForValidListAndQueue( void ) + { + /* Check that the list from which active timers are referenced, and the + * queue used to communicate with the timer service, have been + * initialised. */ + taskENTER_CRITICAL(); + { + if( xTimerQueue == NULL ) + { + vListInitialise( &xActiveTimerList1 ); + vListInitialise( &xActiveTimerList2 ); + pxCurrentTimerList = &xActiveTimerList1; + pxOverflowTimerList = &xActiveTimerList2; + + #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) + { + /* The timer queue is allocated statically in case + * configSUPPORT_DYNAMIC_ALLOCATION is 0. */ + PRIVILEGED_DATA static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ + PRIVILEGED_DATA static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ + + xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue ); + } + #else + { + xTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, sizeof( DaemonTaskMessage_t ) ); + } + #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ + + #if ( configQUEUE_REGISTRY_SIZE > 0 ) + { + if( xTimerQueue != NULL ) + { + vQueueAddToRegistry( xTimerQueue, "TmrQ" ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* configQUEUE_REGISTRY_SIZE */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + } +/*-----------------------------------------------------------*/ + + BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) + { + BaseType_t xReturn; + Timer_t * pxTimer = xTimer; + + configASSERT( xTimer ); + + /* Is the timer in the list of active timers? */ + taskENTER_CRITICAL(); + { + if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 ) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + } + taskEXIT_CRITICAL(); + + return xReturn; + } /*lint !e818 Can't be pointer to const due to the typedef. */ +/*-----------------------------------------------------------*/ + + void * pvTimerGetTimerID( const TimerHandle_t xTimer ) + { + Timer_t * const pxTimer = xTimer; + void * pvReturn; + + configASSERT( xTimer ); + + taskENTER_CRITICAL(); + { + pvReturn = pxTimer->pvTimerID; + } + taskEXIT_CRITICAL(); + + return pvReturn; + } +/*-----------------------------------------------------------*/ + + void vTimerSetTimerID( TimerHandle_t xTimer, + void * pvNewID ) + { + Timer_t * const pxTimer = xTimer; + + configASSERT( xTimer ); + + taskENTER_CRITICAL(); + { + pxTimer->pvTimerID = pvNewID; + } + taskEXIT_CRITICAL(); + } +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTimerPendFunctionCall == 1 ) + + BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, + void * pvParameter1, + uint32_t ulParameter2, + BaseType_t * pxHigherPriorityTaskWoken ) + { + DaemonTaskMessage_t xMessage; + BaseType_t xReturn; + + /* Complete the message with the function parameters and post it to the + * daemon task. */ + xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR; + xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend; + xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1; + xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2; + + xReturn = xQueueSendFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken ); + + tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, xReturn ); + + return xReturn; + } + + #endif /* INCLUDE_xTimerPendFunctionCall */ +/*-----------------------------------------------------------*/ + + #if ( INCLUDE_xTimerPendFunctionCall == 1 ) + + BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, + void * pvParameter1, + uint32_t ulParameter2, + TickType_t xTicksToWait ) + { + DaemonTaskMessage_t xMessage; + BaseType_t xReturn; + + /* This function can only be called after a timer has been created or + * after the scheduler has been started because, until then, the timer + * queue does not exist. */ + configASSERT( xTimerQueue ); + + /* Complete the message with the function parameters and post it to the + * daemon task. */ + xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK; + xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend; + xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1; + xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2; + + xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait ); + + tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, xReturn ); + + return xReturn; + } + + #endif /* INCLUDE_xTimerPendFunctionCall */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer ) + { + return ( ( Timer_t * ) xTimer )->uxTimerNumber; + } + + #endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + + #if ( configUSE_TRACE_FACILITY == 1 ) + + void vTimerSetTimerNumber( TimerHandle_t xTimer, + UBaseType_t uxTimerNumber ) + { + ( ( Timer_t * ) xTimer )->uxTimerNumber = uxTimerNumber; + } + + #endif /* configUSE_TRACE_FACILITY */ +/*-----------------------------------------------------------*/ + +/* This entire source file will be skipped if the application is not configured + * to include software timer functionality. If you want to include software timer + * functionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */ +#endif /* configUSE_TIMERS == 1 */ diff --git a/MODULES/FreeRTOSCmsis/Inc/freertos_mpool.h b/MODULES/FreeRTOSCmsis/Inc/freertos_mpool.h new file mode 100644 index 0000000..cea5017 --- /dev/null +++ b/MODULES/FreeRTOSCmsis/Inc/freertos_mpool.h @@ -0,0 +1,63 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: freertos_mpool.h + * Purpose: CMSIS RTOS2 wrapper for FreeRTOS + * + *---------------------------------------------------------------------------*/ + +#ifndef FREERTOS_MPOOL_H_ +#define FREERTOS_MPOOL_H_ + +#include +#include "FreeRTOS.h" +#include "semphr.h" + +/* Memory Pool implementation definitions */ +#define MPOOL_STATUS 0x5EED0000U + +/* Memory Block header */ +typedef struct { + void *next; /* Pointer to next block */ +} MemPoolBlock_t; + +/* Memory Pool control block */ +typedef struct MemPoolDef_t { + MemPoolBlock_t *head; /* Pointer to head block */ + SemaphoreHandle_t sem; /* Pool semaphore handle */ + uint8_t *mem_arr; /* Pool memory array */ + uint32_t mem_sz; /* Pool memory array size */ + const char *name; /* Pointer to name string */ + uint32_t bl_sz; /* Size of a single block */ + uint32_t bl_cnt; /* Number of blocks */ + uint32_t n; /* Block allocation index */ + volatile uint32_t status; /* Object status flags */ +#if (configSUPPORT_STATIC_ALLOCATION == 1) + StaticSemaphore_t mem_sem; /* Semaphore object memory */ +#endif +} MemPool_t; + +/* No need to hide static object type, just align to coding style */ +#define StaticMemPool_t MemPool_t + +/* Define memory pool control block size */ +#define MEMPOOL_CB_SIZE (sizeof(StaticMemPool_t)) + +/* Define size of the byte array required to create count of blocks of given size */ +#define MEMPOOL_ARR_SIZE(bl_count, bl_size) (((((bl_size) + (4 - 1)) / 4) * 4)*(bl_count)) + +#endif /* FREERTOS_MPOOL_H_ */ diff --git a/MODULES/FreeRTOSCmsis/Inc/freertos_os2.h b/MODULES/FreeRTOSCmsis/Inc/freertos_os2.h new file mode 100644 index 0000000..37432e8 --- /dev/null +++ b/MODULES/FreeRTOSCmsis/Inc/freertos_os2.h @@ -0,0 +1,315 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: freertos_os2.h + * Purpose: CMSIS RTOS2 wrapper for FreeRTOS + * + *---------------------------------------------------------------------------*/ + +#ifndef FREERTOS_OS2_H_ +#define FREERTOS_OS2_H_ + +#ifndef RISC5 + +#include +#include + +#include "FreeRTOS.h" // ARM.FreeRTOS::RTOS:Core + + +#include CMSIS_device_header + +/* + CMSIS-RTOS2 FreeRTOS image size optimization definitions. + + Note: Definitions configUSE_OS2 can be used to optimize FreeRTOS image size when + certain functionality is not required when using CMSIS-RTOS2 API. + In general optimization decisions are left to the tool chain but in cases + when coding style prevents it to optimize the code following optional + definitions can be used. +*/ + +/* + Option to exclude CMSIS-RTOS2 functions osThreadSuspend and osThreadResume from + the application image. +*/ +#ifndef configUSE_OS2_THREAD_SUSPEND_RESUME +#define configUSE_OS2_THREAD_SUSPEND_RESUME 1 +#endif + +/* + Option to exclude CMSIS-RTOS2 function osThreadEnumerate from the application image. +*/ +#ifndef configUSE_OS2_THREAD_ENUMERATE +#define configUSE_OS2_THREAD_ENUMERATE 1 +#endif + +/* + Option to disable CMSIS-RTOS2 function osEventFlagsSet and osEventFlagsClear + operation from ISR. +*/ +#ifndef configUSE_OS2_EVENTFLAGS_FROM_ISR +#define configUSE_OS2_EVENTFLAGS_FROM_ISR 1 +#endif + +/* + Option to exclude CMSIS-RTOS2 Thread Flags API functions from the application image. +*/ +#ifndef configUSE_OS2_THREAD_FLAGS +#define configUSE_OS2_THREAD_FLAGS configUSE_TASK_NOTIFICATIONS +#endif + +/* + Option to exclude CMSIS-RTOS2 Timer API functions from the application image. +*/ +#ifndef configUSE_OS2_TIMER +#define configUSE_OS2_TIMER configUSE_TIMERS +#endif + +/* + Option to exclude CMSIS-RTOS2 Mutex API functions from the application image. +*/ +#ifndef configUSE_OS2_MUTEX +#define configUSE_OS2_MUTEX configUSE_MUTEXES +#endif + + +/* + CMSIS-RTOS2 FreeRTOS configuration check (FreeRTOSConfig.h). + + Note: CMSIS-RTOS API requires functions included by using following definitions. + In case if certain API function is not used compiler will optimize it away. +*/ +#if (INCLUDE_xSemaphoreGetMutexHolder == 0) + /* + CMSIS-RTOS2 function osMutexGetOwner uses FreeRTOS function xSemaphoreGetMutexHolder. In case if + osMutexGetOwner is not used in the application image, compiler will optimize it away. + Set #define INCLUDE_xSemaphoreGetMutexHolder 1 to fix this error. + */ + #error "Definition INCLUDE_xSemaphoreGetMutexHolder must equal 1 to implement Mutex Management API." +#endif +#if (INCLUDE_vTaskDelay == 0) + /* + CMSIS-RTOS2 function osDelay uses FreeRTOS function vTaskDelay. In case if + osDelay is not used in the application image, compiler will optimize it away. + Set #define INCLUDE_vTaskDelay 1 to fix this error. + */ + #error "Definition INCLUDE_vTaskDelay must equal 1 to implement Generic Wait Functions API." +#endif +#if (INCLUDE_vTaskDelayUntil == 0) + /* + CMSIS-RTOS2 function osDelayUntil uses FreeRTOS function vTaskDelayUntil. In case if + osDelayUntil is not used in the application image, compiler will optimize it away. + Set #define INCLUDE_vTaskDelayUntil 1 to fix this error. + */ + #error "Definition INCLUDE_vTaskDelayUntil must equal 1 to implement Generic Wait Functions API." +#endif +#if (INCLUDE_vTaskDelete == 0) + /* + CMSIS-RTOS2 function osThreadTerminate and osThreadExit uses FreeRTOS function + vTaskDelete. In case if they are not used in the application image, compiler + will optimize them away. + Set #define INCLUDE_vTaskDelete 1 to fix this error. + */ + #error "Definition INCLUDE_vTaskDelete must equal 1 to implement Thread Management API." +#endif +#if (INCLUDE_xTaskGetCurrentTaskHandle == 0) + /* + CMSIS-RTOS2 API uses FreeRTOS function xTaskGetCurrentTaskHandle to implement + functions osThreadGetId, osThreadFlagsClear and osThreadFlagsGet. In case if these + functions are not used in the application image, compiler will optimize them away. + Set #define INCLUDE_xTaskGetCurrentTaskHandle 1 to fix this error. + */ + #error "Definition INCLUDE_xTaskGetCurrentTaskHandle must equal 1 to implement Thread Management API." +#endif +#if (INCLUDE_xTaskGetSchedulerState == 0) + /* + CMSIS-RTOS2 API uses FreeRTOS function xTaskGetSchedulerState to implement Kernel + tick handling and therefore it is vital that xTaskGetSchedulerState is included into + the application image. + Set #define INCLUDE_xTaskGetSchedulerState 1 to fix this error. + */ + #error "Definition INCLUDE_xTaskGetSchedulerState must equal 1 to implement Kernel Information and Control API." +#endif +#if (INCLUDE_uxTaskGetStackHighWaterMark == 0) + /* + CMSIS-RTOS2 function osThreadGetStackSpace uses FreeRTOS function uxTaskGetStackHighWaterMark. + In case if osThreadGetStackSpace is not used in the application image, compiler will + optimize it away. + Set #define INCLUDE_uxTaskGetStackHighWaterMark 1 to fix this error. + */ + #error "Definition INCLUDE_uxTaskGetStackHighWaterMark must equal 1 to implement Thread Management API." +#endif +#if (INCLUDE_uxTaskPriorityGet == 0) + /* + CMSIS-RTOS2 function osThreadGetPriority uses FreeRTOS function uxTaskPriorityGet. In case if + osThreadGetPriority is not used in the application image, compiler will optimize it away. + Set #define INCLUDE_uxTaskPriorityGet 1 to fix this error. + */ + #error "Definition INCLUDE_uxTaskPriorityGet must equal 1 to implement Thread Management API." +#endif +#if (INCLUDE_vTaskPrioritySet == 0) + /* + CMSIS-RTOS2 function osThreadSetPriority uses FreeRTOS function vTaskPrioritySet. In case if + osThreadSetPriority is not used in the application image, compiler will optimize it away. + Set #define INCLUDE_vTaskPrioritySet 1 to fix this error. + */ + #error "Definition INCLUDE_vTaskPrioritySet must equal 1 to implement Thread Management API." +#endif +#if (INCLUDE_eTaskGetState == 0) + /* + CMSIS-RTOS2 API uses FreeRTOS function vTaskDelayUntil to implement functions osThreadGetState + and osThreadTerminate. In case if these functions are not used in the application image, + compiler will optimize them away. + Set #define INCLUDE_eTaskGetState 1 to fix this error. + */ + #error "Definition INCLUDE_eTaskGetState must equal 1 to implement Thread Management API." +#endif +#if (INCLUDE_vTaskSuspend == 0) + /* + CMSIS-RTOS2 API uses FreeRTOS functions vTaskSuspend and vTaskResume to implement + functions osThreadSuspend and osThreadResume. In case if these functions are not + used in the application image, compiler will optimize them away. + Set #define INCLUDE_vTaskSuspend 1 to fix this error. + + Alternatively, if the application does not use osThreadSuspend and + osThreadResume they can be excluded from the image code by setting: + #define configUSE_OS2_THREAD_SUSPEND_RESUME 0 (in FreeRTOSConfig.h) + */ + #if (configUSE_OS2_THREAD_SUSPEND_RESUME == 1) + #error "Definition INCLUDE_vTaskSuspend must equal 1 to implement Kernel Information and Control API." + #endif +#endif +#if (INCLUDE_xTimerPendFunctionCall == 0) + /* + CMSIS-RTOS2 function osEventFlagsSet and osEventFlagsClear, when called from + the ISR, call FreeRTOS functions xEventGroupSetBitsFromISR and + xEventGroupClearBitsFromISR which are only enabled if timers are operational and + xTimerPendFunctionCall in enabled. + Set #define INCLUDE_xTimerPendFunctionCall 1 and #define configUSE_TIMERS 1 + to fix this error. + + Alternatively, if the application does not use osEventFlagsSet and osEventFlagsClear + from the ISR their operation from ISR can be restricted by setting: + #define configUSE_OS2_EVENTFLAGS_FROM_ISR 0 (in FreeRTOSConfig.h) + */ + #if (configUSE_OS2_EVENTFLAGS_FROM_ISR == 1) + #error "Definition INCLUDE_xTimerPendFunctionCall must equal 1 to implement Event Flags API." + #endif +#endif + +#if (configUSE_TIMERS == 0) + /* + CMSIS-RTOS2 Timer Management API functions use FreeRTOS timer functions to implement + timer management. In case if these functions are not used in the application image, + compiler will optimize them away. + Set #define configUSE_TIMERS 1 to fix this error. + + Alternatively, if the application does not use timer functions they can be + excluded from the image code by setting: + #define configUSE_OS2_TIMER 0 (in FreeRTOSConfig.h) + */ + #if (configUSE_OS2_TIMER == 1) + #error "Definition configUSE_TIMERS must equal 1 to implement Timer Management API." + #endif +#endif + +#if (configUSE_MUTEXES == 0) + /* + CMSIS-RTOS2 Mutex Management API functions use FreeRTOS mutex functions to implement + mutex management. In case if these functions are not used in the application image, + compiler will optimize them away. + Set #define configUSE_MUTEXES 1 to fix this error. + + Alternatively, if the application does not use mutex functions they can be + excluded from the image code by setting: + #define configUSE_OS2_MUTEX 0 (in FreeRTOSConfig.h) + */ + #if (configUSE_OS2_MUTEX == 1) + #error "Definition configUSE_MUTEXES must equal 1 to implement Mutex Management API." + #endif +#endif + +#if (configUSE_COUNTING_SEMAPHORES == 0) + /* + CMSIS-RTOS2 Memory Pool functions use FreeRTOS function xSemaphoreCreateCounting + to implement memory pools. In case if these functions are not used in the application image, + compiler will optimize them away. + Set #define configUSE_COUNTING_SEMAPHORES 1 to fix this error. + */ + #error "Definition configUSE_COUNTING_SEMAPHORES must equal 1 to implement Memory Pool API." +#endif +#if (configUSE_TASK_NOTIFICATIONS == 0) + /* + CMSIS-RTOS2 Thread Flags API functions use FreeRTOS Task Notification functions to implement + thread flag management. In case if these functions are not used in the application image, + compiler will optimize them away. + Set #define configUSE_TASK_NOTIFICATIONS 1 to fix this error. + + Alternatively, if the application does not use thread flags functions they can be + excluded from the image code by setting: + #define configUSE_OS2_THREAD_FLAGS 0 (in FreeRTOSConfig.h) + */ + #if (configUSE_OS2_THREAD_FLAGS == 1) + #error "Definition configUSE_TASK_NOTIFICATIONS must equal 1 to implement Thread Flags API." + #endif +#endif + +#if (configUSE_TRACE_FACILITY == 0) + /* + CMSIS-RTOS2 function osThreadEnumerate requires FreeRTOS function uxTaskGetSystemState + which is only enabled if configUSE_TRACE_FACILITY == 1. + Set #define configUSE_TRACE_FACILITY 1 to fix this error. + + Alternatively, if the application does not use osThreadEnumerate it can be + excluded from the image code by setting: + #define configUSE_OS2_THREAD_ENUMERATE 0 (in FreeRTOSConfig.h) + */ + #if (configUSE_OS2_THREAD_ENUMERATE == 1) + #error "Definition configUSE_TRACE_FACILITY must equal 1 to implement osThreadEnumerate." + #endif +#endif + +#if (configUSE_16_BIT_TICKS == 1) + /* + CMSIS-RTOS2 wrapper for FreeRTOS relies on 32-bit tick timer which is also optimal on + a 32-bit CPU architectures. + Set #define configUSE_16_BIT_TICKS 0 to fix this error. + */ + #error "Definition configUSE_16_BIT_TICKS must be zero to implement CMSIS-RTOS2 API." +#endif + +#if (configMAX_PRIORITIES != 56) + /* + CMSIS-RTOS2 defines 56 different priorities (see osPriority_t) and portable CMSIS-RTOS2 + implementation should implement the same number of priorities. + Set #define configMAX_PRIORITIES 56 to fix this error. + */ + #error "Definition configMAX_PRIORITIES must equal 56 to implement Thread Management API." +#endif +#if (configUSE_PORT_OPTIMISED_TASK_SELECTION != 0) + /* + CMSIS-RTOS2 requires handling of 56 different priorities (see osPriority_t) while FreeRTOS port + optimised selection for Cortex core only handles 32 different priorities. + Set #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 to fix this error. + */ + #error "Definition configUSE_PORT_OPTIMISED_TASK_SELECTION must be zero to implement Thread Management API." +#endif + +#endif + +#endif /* FREERTOS_OS2_H_ */ diff --git a/MODULES/FreeRTOSCmsis/Inc/systickcounter.h b/MODULES/FreeRTOSCmsis/Inc/systickcounter.h new file mode 100644 index 0000000..7db655c --- /dev/null +++ b/MODULES/FreeRTOSCmsis/Inc/systickcounter.h @@ -0,0 +1,11 @@ +// +// Created by cfif on 13.06.23. +// + +#ifndef GONEC_FULL_SYSTICKCOUNTER_H +#define GONEC_FULL_SYSTICKCOUNTER_H + +#include "stdint.h" + +extern volatile uint64_t __sys_tick_counter; +#endif //GONEC_FULL_SYSTICKCOUNTER_H diff --git a/MODULES/FreeRTOSCmsis/Src/cmsis_os2.c b/MODULES/FreeRTOSCmsis/Src/cmsis_os2.c new file mode 100644 index 0000000..305951a --- /dev/null +++ b/MODULES/FreeRTOSCmsis/Src/cmsis_os2.c @@ -0,0 +1,2915 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: cmsis_os2.c + * Purpose: CMSIS RTOS2 wrapper for FreeRTOS + * + *---------------------------------------------------------------------------*/ + +#ifdef RISC5 + +#include + +#include "cmsis_os2.h" // ::CMSIS:RTOS2 + +#include "FreeRTOS.h" // ARM.FreeRTOS::RTOS:Core +#include "task.h" // ARM.FreeRTOS::RTOS:Core +#include "event_groups.h" // ARM.FreeRTOS::RTOS:Event Groups +#include "semphr.h" // ARM.FreeRTOS::RTOS:Core + +#include "freertos_mpool.h" // osMemoryPool definitions +#include "freertos_os2.h" // Configuration check and setup +#include "systickcounter.h" + +#define __WEAK __attribute__((weak)) + +static int IS_IRQ() { + return 0; +} + +__WEAK void vApplicationStackOverflowHook(TaskHandle_t xTask, signed char *pcTaskName) { + (void) xTask; + (void) pcTaskName; + configASSERT(0); +} + +__WEAK void vApplicationGetIdleTaskMemory(StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, + uint32_t *pulIdleTaskStackSize) { + /* Idle task control block and stack */ + static StaticTask_t Idle_TCB; + static StackType_t Idle_Stack[configMINIMAL_STACK_SIZE]; + + *ppxIdleTaskTCBBuffer = &Idle_TCB; + *ppxIdleTaskStackBuffer = &Idle_Stack[0]; + *pulIdleTaskStackSize = (uint32_t) configMINIMAL_STACK_SIZE; +} + +__WEAK void vApplicationGetTimerTaskMemory(StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, + uint32_t *pulTimerTaskStackSize) { + /* Timer task control block and stack */ + static StaticTask_t Timer_TCB; + static StackType_t Timer_Stack[configTIMER_TASK_STACK_DEPTH]; + + *ppxTimerTaskTCBBuffer = &Timer_TCB; + *ppxTimerTaskStackBuffer = &Timer_Stack[0]; + *pulTimerTaskStackSize = (uint32_t) configTIMER_TASK_STACK_DEPTH; +} + + +osThreadId_t osThreadNew(osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) { + const char *name; + uint32_t stack; + TaskHandle_t hTask; + UBaseType_t prio; + int32_t mem; + + hTask = NULL; + + if (!IS_IRQ() && (func != NULL)) { + stack = configMINIMAL_STACK_SIZE; + prio = (UBaseType_t) osPriorityNormal; + + name = NULL; + mem = -1; + + if (attr != NULL) { + if (attr->name != NULL) { + name = attr->name; + } + if (attr->priority != osPriorityNone) { + prio = (UBaseType_t) attr->priority; + } + + if ((prio < osPriorityIdle) || (prio > osPriorityISR) || + ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) { + return (NULL); + } + + if (attr->stack_size > 0U) { + /* In FreeRTOS stack is not in bytes, but in sizeof(StackType_t) which is 4 on ARM ports. */ + /* Stack size should be therefore 4 byte aligned in order to avoid division caused side effects */ + stack = attr->stack_size / sizeof(StackType_t); + } + + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) && + (attr->stack_mem != NULL) && (attr->stack_size > 0U)) { + mem = 1; + } else { + if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) { + mem = 0; + } + } + } else { + mem = 0; + } + + if (mem == 1) { +#if (configSUPPORT_STATIC_ALLOCATION == 1) + + hTask = xTaskCreateStatic((TaskFunction_t) func, name, stack, argument, prio, + (StackType_t *) attr->stack_mem, + (StaticTask_t *) attr->cb_mem); +#endif + } else { + if (mem == 0) { +#if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + if (xTaskCreate((TaskFunction_t) func, name, (uint16_t) stack, argument, prio, &hTask) != pdPASS) { + hTask = NULL; + } +#endif + } + } + } + + return ((osThreadId_t) hTask); +} + +osStatus_t osThreadResume(osThreadId_t thread_id) { + TaskHandle_t hTask = (TaskHandle_t) thread_id; + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } else if (hTask == NULL) { + stat = osErrorParameter; + } else { + stat = osOK; + vTaskResume(hTask); + } + + return (stat); +} + + +osMessageQueueId_t osMessageQueueNew(uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) { + QueueHandle_t hQueue; + int32_t mem; +#if (configQUEUE_REGISTRY_SIZE > 0) + const char *name; +#endif + + hQueue = NULL; + + if (!IS_IRQ() && (msg_count > 0U) && (msg_size > 0U)) { + mem = -1; + + if (attr != NULL) { + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) && + (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) { + mem = 1; + } else { + if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && + (attr->mq_mem == NULL) && (attr->mq_size == 0U)) { + mem = 0; + } + } + } else { + mem = 0; + } + + if (mem == 1) { +#if (configSUPPORT_STATIC_ALLOCATION == 1) + hQueue = xQueueCreateStatic (msg_count, msg_size, attr->mq_mem, attr->cb_mem); +#endif + } else { + if (mem == 0) { +#if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + hQueue = xQueueCreate (msg_count, msg_size); +#endif + } + } + +#if (configQUEUE_REGISTRY_SIZE > 0) + if (hQueue != NULL) { + if (attr != NULL) { + name = attr->name; + } else { + name = NULL; + } + vQueueAddToRegistry(hQueue, name); + } +#endif + + } + + return ((osMessageQueueId_t) hQueue); +} + +osStatus_t osMessageQueuePut(osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) { + QueueHandle_t hQueue = (QueueHandle_t) mq_id; + osStatus_t stat; + BaseType_t yield; + + (void) msg_prio; /* Message priority is ignored */ + + stat = osOK; + + if ((hQueue == NULL) || (msg_ptr == NULL)) { + stat = osErrorParameter; + } else { + if (xQueueSendToBack (hQueue, msg_ptr, (TickType_t) timeout) != pdPASS) { + if (timeout != 0U) { + stat = osErrorTimeout; + } else { + stat = osErrorResource; + } + } + } + + return (stat); +} + +osStatus_t osMessageQueuePutISR(osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) { + QueueHandle_t hQueue = (QueueHandle_t) mq_id; + osStatus_t stat; + BaseType_t yield; + + (void) msg_prio; /* Message priority is ignored */ + + stat = osOK; + + if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) { + stat = osErrorParameter; + } else { + yield = pdFALSE; + + if (xQueueSendToBackFromISR (hQueue, msg_ptr, &yield) != pdTRUE) { + stat = osErrorResource; + } else { + portYIELD_FROM_ISR (yield); + } + } + + return (stat); +} + + +osStatus_t osMessageQueueGet(osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) { + QueueHandle_t hQueue = (QueueHandle_t) mq_id; + osStatus_t stat; + BaseType_t yield; + + (void) msg_prio; /* Message priority is ignored */ + + stat = osOK; + + if ((hQueue == NULL) || (msg_ptr == NULL)) { + stat = osErrorParameter; + } else { + if (xQueueReceive(hQueue, msg_ptr, (TickType_t) timeout) != pdPASS) { + if (timeout != 0U) { + stat = osErrorTimeout; + } else { + stat = osErrorResource; + } + } + } + + return (stat); +} + +osStatus_t osMessageQueueGetISR(osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) { + QueueHandle_t hQueue = (QueueHandle_t) mq_id; + osStatus_t stat; + BaseType_t yield; + + (void) msg_prio; /* Message priority is ignored */ + + stat = osOK; + + if ((hQueue == NULL) || (msg_ptr == NULL)) { + stat = osErrorParameter; + } else { + if (xQueueReceive(hQueue, msg_ptr, (TickType_t) timeout) != pdPASS) { + if (timeout != 0U) { + stat = osErrorTimeout; + } else { + stat = osErrorResource; + } + } + } + + return (stat); +} + +uint32_t osMessageQueueGetCapacity(osMessageQueueId_t mq_id) { + StaticQueue_t *mq = (StaticQueue_t *) mq_id; + uint32_t capacity; + + if (mq == NULL) { + capacity = 0U; + } else { + /* capacity = pxQueue->uxLength */ + capacity = mq->uxDummy4[1]; + } + + return (capacity); +} + +uint32_t osMessageQueueGetMsgSize(osMessageQueueId_t mq_id) { + StaticQueue_t *mq = (StaticQueue_t *) mq_id; + uint32_t size; + + if (mq == NULL) { + size = 0U; + } else { + /* size = pxQueue->uxItemSize */ + size = mq->uxDummy4[2]; + } + + return (size); +} + +uint32_t osMessageQueueGetCount(osMessageQueueId_t mq_id) { + QueueHandle_t hQueue = (QueueHandle_t) mq_id; + UBaseType_t count; + + if (hQueue == NULL) { + count = 0U; + } else { + count = uxQueueMessagesWaitingFromISR(hQueue); + } + + return ((uint32_t) count); +} + +uint32_t osMessageQueueGetCountISR(osMessageQueueId_t mq_id) { + QueueHandle_t hQueue = (QueueHandle_t) mq_id; + UBaseType_t count; + + if (hQueue == NULL) { + count = 0U; + } else { + count = uxQueueMessagesWaitingFromISR(hQueue); + } + return ((uint32_t) count); +} + + +uint32_t osMessageQueueGetSpace(osMessageQueueId_t mq_id) { + StaticQueue_t *mq = (StaticQueue_t *) mq_id; + uint32_t space; + uint32_t isrm; + + if (mq == NULL) { + space = 0U; + } else { + isrm = taskENTER_CRITICAL_FROM_ISR(); + + /* space = pxQueue->uxLength - pxQueue->uxMessagesWaiting; */ + space = mq->uxDummy4[1] - mq->uxDummy4[0]; + + taskEXIT_CRITICAL_FROM_ISR(isrm); + } + + return (space); +} + +uint32_t osMessageQueueGetSpaceISR(osMessageQueueId_t mq_id) { + StaticQueue_t *mq = (StaticQueue_t *) mq_id; + uint32_t space; + uint32_t isrm; + + if (mq == NULL) { + space = 0U; + } else { + isrm = taskENTER_CRITICAL_FROM_ISR(); + + /* space = pxQueue->uxLength - pxQueue->uxMessagesWaiting; */ + space = mq->uxDummy4[1] - mq->uxDummy4[0]; + + taskEXIT_CRITICAL_FROM_ISR(isrm); + } + + return (space); +} + + +osStatus_t osMessageQueueReset(osMessageQueueId_t mq_id) { + QueueHandle_t hQueue = (QueueHandle_t) mq_id; + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } else if (hQueue == NULL) { + stat = osErrorParameter; + } else { + stat = osOK; + (void) xQueueReset (hQueue); + } + + return (stat); +} + +osStatus_t osMessageQueueDelete(osMessageQueueId_t mq_id) { + QueueHandle_t hQueue = (QueueHandle_t) mq_id; + osStatus_t stat; + +#ifndef USE_FreeRTOS_HEAP_1 + if (IS_IRQ()) { + stat = osErrorISR; + } else if (hQueue == NULL) { + stat = osErrorParameter; + } else { +#if (configQUEUE_REGISTRY_SIZE > 0) + vQueueUnregisterQueue(hQueue); +#endif + + stat = osOK; + vQueueDelete(hQueue); + } +#else + stat = osError; +#endif + + return (stat); +} + + +#endif + +#ifndef RISC5 + +#include + +#include "cmsis_os2.h" // ::CMSIS:RTOS2 +#include "cmsis_compiler.h" // Compiler agnostic definitions + +#include "FreeRTOS.h" // ARM.FreeRTOS::RTOS:Core +#include "task.h" // ARM.FreeRTOS::RTOS:Core +#include "event_groups.h" // ARM.FreeRTOS::RTOS:Event Groups +#include "semphr.h" // ARM.FreeRTOS::RTOS:Core + +#include "freertos_mpool.h" // osMemoryPool definitions +#include "freertos_os2.h" // Configuration check and setup +#include "systickcounter.h" + +/*---------------------------------------------------------------------------*/ +#ifndef __ARM_ARCH_6M__ +#define __ARM_ARCH_6M__ 0 +#endif +#ifndef __ARM_ARCH_7M__ +#define __ARM_ARCH_7M__ 1 +#endif +#ifndef __ARM_ARCH_7EM__ +#define __ARM_ARCH_7EM__ 0 +#endif +#ifndef __ARM_ARCH_8M_MAIN__ +#define __ARM_ARCH_8M_MAIN__ 0 +#endif +#ifndef __ARM_ARCH_7A__ +#define __ARM_ARCH_7A__ 0 +#endif + +#if ((__ARM_ARCH_7M__ == 1U) || \ + (__ARM_ARCH_7EM__ == 1U) || \ + (__ARM_ARCH_8M_MAIN__ == 1U)) +#define IS_IRQ_MASKED() ((__get_PRIMASK() != 0U) || (__get_BASEPRI() != 0U)) +#elif (__ARM_ARCH_6M__ == 1U) +#define IS_IRQ_MASKED() (__get_PRIMASK() != 0U) +#elif (__ARM_ARCH_7A__ == 1U) +/* CPSR mask bits */ +#define CPSR_MASKBIT_I 0x80U + +#define IS_IRQ_MASKED() ((__get_CPSR() & CPSR_MASKBIT_I) != 0U) +#else +#define IS_IRQ_MASKED() (__get_PRIMASK() != 0U) +#endif + +#if (__ARM_ARCH_7A__ == 1U) +/* CPSR mode bitmasks */ +#define CPSR_MODE_USER 0x10U +#define CPSR_MODE_SYSTEM 0x1FU + +#define IS_IRQ_MODE() ((__get_mode() != CPSR_MODE_USER) && (__get_mode() != CPSR_MODE_SYSTEM)) +#else +#define IS_IRQ_MODE() (__get_IPSR() != 0U) +#endif + +#define IS_IRQ() IS_IRQ_MODE() + +#define SVCall_IRQ_NBR (IRQn_Type) -5 /* SVCall_IRQ_NBR added as SV_Call handler name is not the same for CM0 and for all other CMx */ + +/* Limits */ +#define MAX_BITS_TASK_NOTIFY 31U +#define MAX_BITS_EVENT_GROUPS 24U + +#define THREAD_FLAGS_INVALID_BITS (~((1UL << MAX_BITS_TASK_NOTIFY) - 1U)) +#define EVENT_FLAGS_INVALID_BITS (~((1UL << MAX_BITS_EVENT_GROUPS) - 1U)) + +/* Kernel version and identification string definition (major.minor.rev: mmnnnrrrr dec) */ +#define KERNEL_VERSION (((uint32_t)tskKERNEL_VERSION_MAJOR * 10000000UL) | \ + ((uint32_t)tskKERNEL_VERSION_MINOR * 10000UL) | \ + ((uint32_t)tskKERNEL_VERSION_BUILD * 1UL)) + +#define KERNEL_ID ("FreeRTOS " tskKERNEL_VERSION_NUMBER) + +/* Timer callback information structure definition */ +typedef struct { + osTimerFunc_t func; + void *arg; +} TimerCallback_t; + +/* Kernel initialization state */ +static osKernelState_t KernelState = osKernelInactive; + +/* + Heap region definition used by heap_5 variant + + Define configAPPLICATION_ALLOCATED_HEAP as nonzero value in FreeRTOSConfig.h if + heap regions are already defined and vPortDefineHeapRegions is called in application. + + Otherwise vPortDefineHeapRegions will be called by osKernelInitialize using + definition configHEAP_5_REGIONS as parameter. Overriding configHEAP_5_REGIONS + is possible by defining it globally or in FreeRTOSConfig.h. +*/ +#if defined(USE_FreeRTOS_HEAP_5) +#if (configAPPLICATION_ALLOCATED_HEAP == 0) + /* + FreeRTOS heap is not defined by the application. + Single region of size configTOTAL_HEAP_SIZE (defined in FreeRTOSConfig.h) + is provided by default. Define configHEAP_5_REGIONS to provide custom + HeapRegion_t array. + */ +#define HEAP_5_REGION_SETUP 1 + +#ifndef configHEAP_5_REGIONS +#define configHEAP_5_REGIONS xHeapRegions + + static uint8_t ucHeap[configTOTAL_HEAP_SIZE]; + + static HeapRegion_t xHeapRegions[] = { + { ucHeap, configTOTAL_HEAP_SIZE }, + { NULL, 0 } + }; +#else + /* Global definition is provided to override default heap array */ + extern HeapRegion_t configHEAP_5_REGIONS[]; +#endif +#else + /* + The application already defined the array used for the FreeRTOS heap and + called vPortDefineHeapRegions to initialize heap. + */ +#define HEAP_5_REGION_SETUP 0 +#endif /* configAPPLICATION_ALLOCATED_HEAP */ +#endif /* USE_FreeRTOS_HEAP_5 */ + +#if defined(SysTick) +#undef SysTick_Handler + +/* CMSIS SysTick interrupt handler prototype */ +extern void SysTick_Handler (void); +/* FreeRTOS tick timer interrupt handler prototype */ +extern void xPortSysTickHandler (void); + +/* + SysTick handler implementation that also clears overflow flag. +*/ +#if (USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION == 0) +volatile uint64_t __sys_tick_counter = 0; + +void SysTick_Handler (void) { + // Clear overflow flag + SysTick->CTRL; + ++__sys_tick_counter; + + if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) { + /// Call tick handler + xPortSysTickHandler(); + } + +} + +#endif +#endif /* SysTick */ + +/* + Setup SVC to reset value. +*/ +__STATIC_INLINE void SVC_Setup (void) { +#if (__ARM_ARCH_7A__ == 0U) + /* Service Call interrupt might be configured before kernel start */ + /* and when its priority is lower or equal to BASEPRI, svc intruction */ + /* causes a Hard Fault. */ + NVIC_SetPriority (SVCall_IRQ_NBR, 0U); +#endif +} + +/* + Function macro used to retrieve semaphore count from ISR +*/ +#ifndef uxSemaphoreGetCountFromISR +#define uxSemaphoreGetCountFromISR( xSemaphore ) uxQueueMessagesWaitingFromISR( ( QueueHandle_t ) ( xSemaphore ) ) +#endif + +/* Get OS Tick count value */ +static uint32_t OS_Tick_GetCount (void); +/* Get OS Tick overflow status */ +static uint32_t OS_Tick_GetOverflow (void); +/* Get OS Tick interval */ +static uint32_t OS_Tick_GetInterval (void); +/*---------------------------------------------------------------------------*/ + +osStatus_t osKernelInitialize (void) { + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else { + if (KernelState == osKernelInactive) { +#if defined(USE_TRACE_EVENT_RECORDER) + EvrFreeRTOSSetup(0U); +#endif +#if defined(USE_FreeRTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1) + vPortDefineHeapRegions (configHEAP_5_REGIONS); +#endif + KernelState = osKernelReady; + stat = osOK; + } else { + stat = osError; + } + } + + return (stat); +} + +osStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size) { + + if (version != NULL) { + /* Version encoding is major.minor.rev: mmnnnrrrr dec */ + version->api = KERNEL_VERSION; + version->kernel = KERNEL_VERSION; + } + + if ((id_buf != NULL) && (id_size != 0U)) { + if (id_size > sizeof(KERNEL_ID)) { + id_size = sizeof(KERNEL_ID); + } + memcpy(id_buf, KERNEL_ID, id_size); + } + + return (osOK); +} + +osKernelState_t osKernelGetState (void) { + osKernelState_t state; + + switch (xTaskGetSchedulerState()) { + case taskSCHEDULER_RUNNING: + state = osKernelRunning; + break; + + case taskSCHEDULER_SUSPENDED: + state = osKernelLocked; + break; + + case taskSCHEDULER_NOT_STARTED: + default: + if (KernelState == osKernelReady) { + state = osKernelReady; + } else { + state = osKernelInactive; + } + break; + } + + return (state); +} + +osStatus_t osKernelStart (void) { + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else { + if (KernelState == osKernelReady) { + /* Ensure SVC priority is at the reset value */ + SVC_Setup(); + /* Change state to enable IRQ masking check */ + KernelState = osKernelRunning; + /* Start the kernel scheduler */ + vTaskStartScheduler(); + stat = osOK; + } else { + stat = osError; + } + } + + return (stat); +} + +int32_t osKernelLock (void) { + int32_t lock; + + if (IS_IRQ()) { + lock = (int32_t)osErrorISR; + } + else { + switch (xTaskGetSchedulerState()) { + case taskSCHEDULER_SUSPENDED: + lock = 1; + break; + + case taskSCHEDULER_RUNNING: + vTaskSuspendAll(); + lock = 0; + break; + + case taskSCHEDULER_NOT_STARTED: + default: + lock = (int32_t)osError; + break; + } + } + + return (lock); +} + +int32_t osKernelUnlock (void) { + int32_t lock; + + if (IS_IRQ()) { + lock = (int32_t)osErrorISR; + } + else { + switch (xTaskGetSchedulerState()) { + case taskSCHEDULER_SUSPENDED: + lock = 1; + + if (xTaskResumeAll() != pdTRUE) { + if (xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED) { + lock = (int32_t)osError; + } + } + break; + + case taskSCHEDULER_RUNNING: + lock = 0; + break; + + case taskSCHEDULER_NOT_STARTED: + default: + lock = (int32_t)osError; + break; + } + } + + return (lock); +} + +int32_t osKernelRestoreLock (int32_t lock) { + + if (IS_IRQ()) { + lock = (int32_t)osErrorISR; + } + else { + switch (xTaskGetSchedulerState()) { + case taskSCHEDULER_SUSPENDED: + case taskSCHEDULER_RUNNING: + if (lock == 1) { + vTaskSuspendAll(); + } + else { + if (lock != 0) { + lock = (int32_t)osError; + } + else { + if (xTaskResumeAll() != pdTRUE) { + if (xTaskGetSchedulerState() != taskSCHEDULER_RUNNING) { + lock = (int32_t)osError; + } + } + } + } + break; + + case taskSCHEDULER_NOT_STARTED: + default: + lock = (int32_t)osError; + break; + } + } + + return (lock); +} + +uint32_t osKernelGetTickCount (void) { + TickType_t ticks; + + if (IS_IRQ()) { + ticks = xTaskGetTickCountFromISR(); + } else { + ticks = xTaskGetTickCount(); + } + + return (ticks); +} + +uint32_t osKernelGetTickFreq (void) { + return (configTICK_RATE_HZ); +} + +/* Get OS Tick count value */ +static uint32_t OS_Tick_GetCount (void) { + uint32_t load = SysTick->LOAD; + return (load - SysTick->VAL); +} + +/* Get OS Tick overflow status */ +static uint32_t OS_Tick_GetOverflow (void) { + return ((SysTick->CTRL >> 16) & 1U); +} + +/* Get OS Tick interval */ +static uint32_t OS_Tick_GetInterval (void) { + return (SysTick->LOAD + 1U); +} + +uint32_t osKernelGetSysTimerCount (void) { + uint32_t irqmask = IS_IRQ_MASKED(); + TickType_t ticks; + uint32_t val; + + __disable_irq(); + + ticks = xTaskGetTickCount(); + val = OS_Tick_GetCount(); + + if (OS_Tick_GetOverflow() != 0U) { + val = OS_Tick_GetCount(); + ticks++; + } + val += ticks * OS_Tick_GetInterval(); + + if (irqmask == 0U) { + __enable_irq(); + } + + return (val); +} + +uint32_t osKernelGetSysTimerFreq (void) { + return (configCPU_CLOCK_HZ); +} + +/*---------------------------------------------------------------------------*/ + +osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) { + const char *name; + uint32_t stack; + TaskHandle_t hTask; + UBaseType_t prio; + int32_t mem; + + hTask = NULL; + + if (!IS_IRQ() && (func != NULL)) { + stack = configMINIMAL_STACK_SIZE; + prio = (UBaseType_t)osPriorityNormal; + + name = NULL; + mem = -1; + + if (attr != NULL) { + if (attr->name != NULL) { + name = attr->name; + } + if (attr->priority != osPriorityNone) { + prio = (UBaseType_t)attr->priority; + } + + if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) { + return (NULL); + } + + if (attr->stack_size > 0U) { + /* In FreeRTOS stack is not in bytes, but in sizeof(StackType_t) which is 4 on ARM ports. */ + /* Stack size should be therefore 4 byte aligned in order to avoid division caused side effects */ + stack = attr->stack_size / sizeof(StackType_t); + } + + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) && + (attr->stack_mem != NULL) && (attr->stack_size > 0U)) { + mem = 1; + } + else { + if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) { + mem = 0; + } + } + } + else { + mem = 0; + } + + if (mem == 1) { +#if (configSUPPORT_STATIC_ALLOCATION == 1) + + hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem, + (StaticTask_t *)attr->cb_mem); +#endif + } + else { + if (mem == 0) { +#if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + if (xTaskCreate ((TaskFunction_t)func, name, (uint16_t)stack, argument, prio, &hTask) != pdPASS) { + hTask = NULL; + } +#endif + } + } + } + + return ((osThreadId_t)hTask); +} + +const char *osThreadGetName (osThreadId_t thread_id) { + TaskHandle_t hTask = (TaskHandle_t)thread_id; + const char *name; + + if (IS_IRQ() || (hTask == NULL)) { + name = NULL; + } else { + name = pcTaskGetName (hTask); + } + + return (name); +} + +osThreadId_t osThreadGetId (void) { + osThreadId_t id; + + id = (osThreadId_t)xTaskGetCurrentTaskHandle(); + + return (id); +} + +osThreadState_t osThreadGetState (osThreadId_t thread_id) { + TaskHandle_t hTask = (TaskHandle_t)thread_id; + osThreadState_t state; + + if (IS_IRQ() || (hTask == NULL)) { + state = osThreadError; + } + else { + switch (eTaskGetState (hTask)) { + case eRunning: state = osThreadRunning; break; + case eReady: state = osThreadReady; break; + case eBlocked: + case eSuspended: state = osThreadBlocked; break; + case eDeleted: state = osThreadTerminated; break; + case eInvalid: + default: state = osThreadError; break; + } + } + + return (state); +} + +uint32_t osThreadGetStackSpace (osThreadId_t thread_id) { + TaskHandle_t hTask = (TaskHandle_t)thread_id; + uint32_t sz; + + if (IS_IRQ() || (hTask == NULL)) { + sz = 0U; + } else { + sz = (uint32_t)(uxTaskGetStackHighWaterMark(hTask) * sizeof(StackType_t)); + } + + return (sz); +} + +osStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority) { + TaskHandle_t hTask = (TaskHandle_t)thread_id; + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if ((hTask == NULL) || (priority < osPriorityIdle) || (priority > osPriorityISR)) { + stat = osErrorParameter; + } + else { + stat = osOK; + vTaskPrioritySet (hTask, (UBaseType_t)priority); + } + + return (stat); +} + +osPriority_t osThreadGetPriority (osThreadId_t thread_id) { + TaskHandle_t hTask = (TaskHandle_t)thread_id; + osPriority_t prio; + + if (IS_IRQ() || (hTask == NULL)) { + prio = osPriorityError; + } else { + prio = (osPriority_t)((int32_t)uxTaskPriorityGet (hTask)); + } + + return (prio); +} + +osStatus_t osThreadYield (void) { + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } else { + stat = osOK; + taskYIELD(); + } + + return (stat); +} + +#if (configUSE_OS2_THREAD_SUSPEND_RESUME == 1) +osStatus_t osThreadSuspend (osThreadId_t thread_id) { + TaskHandle_t hTask = (TaskHandle_t)thread_id; + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hTask == NULL) { + stat = osErrorParameter; + } + else { + stat = osOK; + vTaskSuspend (hTask); + } + + return (stat); +} + +osStatus_t osThreadResume (osThreadId_t thread_id) { + TaskHandle_t hTask = (TaskHandle_t)thread_id; + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hTask == NULL) { + stat = osErrorParameter; + } + else { + stat = osOK; + vTaskResume (hTask); + } + + return (stat); +} +#endif /* (configUSE_OS2_THREAD_SUSPEND_RESUME == 1) */ + +__NO_RETURN void osThreadExit (void) { +#ifndef USE_FreeRTOS_HEAP_1 + vTaskDelete (NULL); +#endif + for (;;); +} + +osStatus_t osThreadTerminate (osThreadId_t thread_id) { + TaskHandle_t hTask = (TaskHandle_t)thread_id; + osStatus_t stat; +#ifndef USE_FreeRTOS_HEAP_1 + eTaskState tstate; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hTask == NULL) { + stat = osErrorParameter; + } + else { + tstate = eTaskGetState (hTask); + + if (tstate != eDeleted) { + stat = osOK; + vTaskDelete (hTask); + } else { + stat = osErrorResource; + } + } +#else + stat = osError; +#endif + + return (stat); +} + +uint32_t osThreadGetCount (void) { + uint32_t count; + + if (IS_IRQ()) { + count = 0U; + } else { + count = uxTaskGetNumberOfTasks(); + } + + return (count); +} + +#if (configUSE_OS2_THREAD_ENUMERATE == 1) +uint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items) { + uint32_t i, count; + TaskStatus_t *task; + + if (IS_IRQ() || (thread_array == NULL) || (array_items == 0U)) { + count = 0U; + } else { + vTaskSuspendAll(); + + count = uxTaskGetNumberOfTasks(); + task = pvPortMalloc (count * sizeof(TaskStatus_t)); + + if (task != NULL) { + count = uxTaskGetSystemState (task, count, NULL); + + for (i = 0U; (i < count) && (i < array_items); i++) { + thread_array[i] = (osThreadId_t)task[i].xHandle; + } + count = i; + } + (void)xTaskResumeAll(); + + vPortFree (task); + } + + return (count); +} +#endif /* (configUSE_OS2_THREAD_ENUMERATE == 1) */ + +#if (configUSE_OS2_THREAD_FLAGS == 1) +uint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) { + TaskHandle_t hTask = (TaskHandle_t)thread_id; + uint32_t rflags; + BaseType_t yield; + + if ((hTask == NULL) || ((flags & THREAD_FLAGS_INVALID_BITS) != 0U)) { + rflags = (uint32_t)osErrorParameter; + } + else { + rflags = (uint32_t)osError; + + if (IS_IRQ()) { + yield = pdFALSE; + + (void)xTaskNotifyFromISR (hTask, flags, eSetBits, &yield); + (void)xTaskNotifyAndQueryFromISR (hTask, 0, eNoAction, &rflags, NULL); + + portYIELD_FROM_ISR (yield); + } + else { + (void)xTaskNotify (hTask, flags, eSetBits); + (void)xTaskNotifyAndQuery (hTask, 0, eNoAction, &rflags); + } + } + /* Return flags after setting */ + return (rflags); +} + +uint32_t osThreadFlagsClear (uint32_t flags) { + TaskHandle_t hTask; + uint32_t rflags, cflags; + + if (IS_IRQ()) { + rflags = (uint32_t)osErrorISR; + } + else if ((flags & THREAD_FLAGS_INVALID_BITS) != 0U) { + rflags = (uint32_t)osErrorParameter; + } + else { + hTask = xTaskGetCurrentTaskHandle(); + + if (xTaskNotifyAndQuery (hTask, 0, eNoAction, &cflags) == pdPASS) { + rflags = cflags; + cflags &= ~flags; + + if (xTaskNotify (hTask, cflags, eSetValueWithOverwrite) != pdPASS) { + rflags = (uint32_t)osError; + } + } + else { + rflags = (uint32_t)osError; + } + } + + /* Return flags before clearing */ + return (rflags); +} + +uint32_t osThreadFlagsGet (void) { + TaskHandle_t hTask; + uint32_t rflags; + + if (IS_IRQ()) { + rflags = (uint32_t)osErrorISR; + } + else { + hTask = xTaskGetCurrentTaskHandle(); + + if (xTaskNotifyAndQuery (hTask, 0, eNoAction, &rflags) != pdPASS) { + rflags = (uint32_t)osError; + } + } + + return (rflags); +} + +uint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout) { + uint32_t rflags, nval; + uint32_t clear; + TickType_t t0, td, tout; + BaseType_t rval; + + if (IS_IRQ()) { + rflags = (uint32_t)osErrorISR; + } + else if ((flags & THREAD_FLAGS_INVALID_BITS) != 0U) { + rflags = (uint32_t)osErrorParameter; + } + else { + if ((options & osFlagsNoClear) == osFlagsNoClear) { + clear = 0U; + } else { + clear = flags; + } + + rflags = 0U; + tout = timeout; + + t0 = xTaskGetTickCount(); + do { + rval = xTaskNotifyWait (0, clear, &nval, tout); + + if (rval == pdPASS) { + rflags &= flags; + rflags |= nval; + + if ((options & osFlagsWaitAll) == osFlagsWaitAll) { + if ((flags & rflags) == flags) { + break; + } else { + if (timeout == 0U) { + rflags = (uint32_t)osErrorResource; + break; + } + } + } + else { + if ((flags & rflags) != 0) { + break; + } else { + if (timeout == 0U) { + rflags = (uint32_t)osErrorResource; + break; + } + } + } + + /* Update timeout */ + td = xTaskGetTickCount() - t0; + + if (td > tout) { + tout = 0; + } else { + tout -= td; + } + } + else { + if (timeout == 0) { + rflags = (uint32_t)osErrorResource; + } else { + rflags = (uint32_t)osErrorTimeout; + } + } + } + while (rval != pdFAIL); + } + + /* Return flags before clearing */ + return (rflags); +} +#endif /* (configUSE_OS2_THREAD_FLAGS == 1) */ + +osStatus_t osDelay (uint32_t ticks) { + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else { + stat = osOK; + + if (ticks != 0U) { + vTaskDelay(ticks); + } + } + + return (stat); +} + +osStatus_t osDelayUntil (uint32_t ticks) { + TickType_t tcnt, delay; + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else { + stat = osOK; + tcnt = xTaskGetTickCount(); + + /* Determine remaining number of ticks to delay */ + delay = (TickType_t)ticks - tcnt; + + /* Check if target tick has not expired */ + if((delay != 0U) && (0 == (delay >> (8 * sizeof(TickType_t) - 1)))) { + vTaskDelayUntil (&tcnt, delay); + } + else + { + /* No delay or already expired */ + stat = osErrorParameter; + } + } + + return (stat); +} + +/*---------------------------------------------------------------------------*/ +#if (configUSE_OS2_TIMER == 1) + +static void TimerCallback (TimerHandle_t hTimer) { + TimerCallback_t *callb; + + callb = (TimerCallback_t *)pvTimerGetTimerID (hTimer); + + if (callb != NULL) { + callb->func (callb->arg); + } +} + +osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) { + const char *name; + TimerHandle_t hTimer; + TimerCallback_t *callb; + UBaseType_t reload; + int32_t mem; + + hTimer = NULL; + + if (!IS_IRQ() && (func != NULL)) { + /* Allocate memory to store callback function and argument */ + callb = pvPortMalloc (sizeof(TimerCallback_t)); + + if (callb != NULL) { + callb->func = func; + callb->arg = argument; + + if (type == osTimerOnce) { + reload = pdFALSE; + } else { + reload = pdTRUE; + } + + mem = -1; + name = NULL; + + if (attr != NULL) { + if (attr->name != NULL) { + name = attr->name; + } + + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTimer_t))) { + mem = 1; + } + else { + if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { + mem = 0; + } + } + } + else { + mem = 0; + } + + if (mem == 1) { +#if (configSUPPORT_STATIC_ALLOCATION == 1) + hTimer = xTimerCreateStatic (name, 1, reload, callb, TimerCallback, (StaticTimer_t *)attr->cb_mem); +#endif + } + else { + if (mem == 0) { +#if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + hTimer = xTimerCreate (name, 1, reload, callb, TimerCallback); +#endif + } + } + + if ((hTimer == NULL) && (callb != NULL)) { + vPortFree (callb); + } + } + } + + return ((osTimerId_t)hTimer); +} + +const char *osTimerGetName (osTimerId_t timer_id) { + TimerHandle_t hTimer = (TimerHandle_t)timer_id; + const char *p; + + if (IS_IRQ() || (hTimer == NULL)) { + p = NULL; + } else { + p = pcTimerGetName (hTimer); + } + + return (p); +} + +osStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks) { + TimerHandle_t hTimer = (TimerHandle_t)timer_id; + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hTimer == NULL) { + stat = osErrorParameter; + } + else { + if (xTimerChangePeriod (hTimer, ticks, 0) == pdPASS) { + stat = osOK; + } else { + stat = osErrorResource; + } + } + + return (stat); +} + +osStatus_t osTimerStop (osTimerId_t timer_id) { + TimerHandle_t hTimer = (TimerHandle_t)timer_id; + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hTimer == NULL) { + stat = osErrorParameter; + } + else { + if (xTimerIsTimerActive (hTimer) == pdFALSE) { + stat = osErrorResource; + } + else { + if (xTimerStop (hTimer, 0) == pdPASS) { + stat = osOK; + } else { + stat = osError; + } + } + } + + return (stat); +} + +uint32_t osTimerIsRunning (osTimerId_t timer_id) { + TimerHandle_t hTimer = (TimerHandle_t)timer_id; + uint32_t running; + + if (IS_IRQ() || (hTimer == NULL)) { + running = 0U; + } else { + running = (uint32_t)xTimerIsTimerActive (hTimer); + } + + return (running); +} + +osStatus_t osTimerDelete (osTimerId_t timer_id) { + TimerHandle_t hTimer = (TimerHandle_t)timer_id; + osStatus_t stat; +#ifndef USE_FreeRTOS_HEAP_1 + TimerCallback_t *callb; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hTimer == NULL) { + stat = osErrorParameter; + } + else { + callb = (TimerCallback_t *)pvTimerGetTimerID (hTimer); + + if (xTimerDelete (hTimer, 0) == pdPASS) { + vPortFree (callb); + stat = osOK; + } else { + stat = osErrorResource; + } + } +#else + stat = osError; +#endif + + return (stat); +} +#endif /* (configUSE_OS2_TIMER == 1) */ + +/*---------------------------------------------------------------------------*/ + +osEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr) { + EventGroupHandle_t hEventGroup; + int32_t mem; + + hEventGroup = NULL; + + if (!IS_IRQ()) { + mem = -1; + + if (attr != NULL) { + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticEventGroup_t))) { + mem = 1; + } + else { + if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { + mem = 0; + } + } + } + else { + mem = 0; + } + + if (mem == 1) { +#if (configSUPPORT_STATIC_ALLOCATION == 1) + hEventGroup = xEventGroupCreateStatic (attr->cb_mem); +#endif + } + else { + if (mem == 0) { +#if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + hEventGroup = xEventGroupCreate(); +#endif + } + } + } + + return ((osEventFlagsId_t)hEventGroup); +} + +uint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags) { + EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id; + uint32_t rflags; + BaseType_t yield; + + if ((hEventGroup == NULL) || ((flags & EVENT_FLAGS_INVALID_BITS) != 0U)) { + rflags = (uint32_t)osErrorParameter; + } + else if (IS_IRQ()) { +#if (configUSE_OS2_EVENTFLAGS_FROM_ISR == 0) + (void)yield; + /* Enable timers and xTimerPendFunctionCall function to support osEventFlagsSet from ISR */ + rflags = (uint32_t)osErrorResource; +#else + yield = pdFALSE; + + if (xEventGroupSetBitsFromISR (hEventGroup, (EventBits_t)flags, &yield) == pdFAIL) { + rflags = (uint32_t)osErrorResource; + } else { + rflags = flags; + portYIELD_FROM_ISR (yield); + } +#endif + } + else { + rflags = xEventGroupSetBits (hEventGroup, (EventBits_t)flags); + } + + return (rflags); +} + +uint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags) { + EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id; + uint32_t rflags; + + if ((hEventGroup == NULL) || ((flags & EVENT_FLAGS_INVALID_BITS) != 0U)) { + rflags = (uint32_t)osErrorParameter; + } + else if (IS_IRQ()) { +#if (configUSE_OS2_EVENTFLAGS_FROM_ISR == 0) + /* Enable timers and xTimerPendFunctionCall function to support osEventFlagsSet from ISR */ + rflags = (uint32_t)osErrorResource; +#else + rflags = xEventGroupGetBitsFromISR (hEventGroup); + + if (xEventGroupClearBitsFromISR (hEventGroup, (EventBits_t)flags) == pdFAIL) { + rflags = (uint32_t)osErrorResource; + } +#endif + } + else { + rflags = xEventGroupClearBits (hEventGroup, (EventBits_t)flags); + } + + return (rflags); +} + +uint32_t osEventFlagsGet (osEventFlagsId_t ef_id) { + EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id; + uint32_t rflags; + + if (ef_id == NULL) { + rflags = 0U; + } + else if (IS_IRQ()) { + rflags = xEventGroupGetBitsFromISR (hEventGroup); + } + else { + rflags = xEventGroupGetBits (hEventGroup); + } + + return (rflags); +} + +uint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout) { + EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id; + BaseType_t wait_all; + BaseType_t exit_clr; + uint32_t rflags; + + if ((hEventGroup == NULL) || ((flags & EVENT_FLAGS_INVALID_BITS) != 0U)) { + rflags = (uint32_t)osErrorParameter; + } + else if (IS_IRQ()) { + rflags = (uint32_t)osErrorISR; + } + else { + if (options & osFlagsWaitAll) { + wait_all = pdTRUE; + } else { + wait_all = pdFAIL; + } + + if (options & osFlagsNoClear) { + exit_clr = pdFAIL; + } else { + exit_clr = pdTRUE; + } + + rflags = xEventGroupWaitBits (hEventGroup, (EventBits_t)flags, exit_clr, wait_all, (TickType_t)timeout); + + if (options & osFlagsWaitAll) { + if ((flags & rflags) != flags) { + if (timeout > 0U) { + rflags = (uint32_t)osErrorTimeout; + } else { + rflags = (uint32_t)osErrorResource; + } + } + } + else { + if ((flags & rflags) == 0U) { + if (timeout > 0U) { + rflags = (uint32_t)osErrorTimeout; + } else { + rflags = (uint32_t)osErrorResource; + } + } + } + } + + return (rflags); +} + +osStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id) { + EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id; + osStatus_t stat; + +#ifndef USE_FreeRTOS_HEAP_1 + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hEventGroup == NULL) { + stat = osErrorParameter; + } + else { + stat = osOK; + vEventGroupDelete (hEventGroup); + } +#else + stat = osError; +#endif + + return (stat); +} + +/*---------------------------------------------------------------------------*/ +#if (configUSE_OS2_MUTEX == 1) + +osMutexId_t osMutexNew (const osMutexAttr_t *attr) { + SemaphoreHandle_t hMutex; + uint32_t type; + uint32_t rmtx; + int32_t mem; +#if (configQUEUE_REGISTRY_SIZE > 0) + const char *name; +#endif + + hMutex = NULL; + + if (!IS_IRQ()) { + if (attr != NULL) { + type = attr->attr_bits; + } else { + type = 0U; + } + + if ((type & osMutexRecursive) == osMutexRecursive) { + rmtx = 1U; + } else { + rmtx = 0U; + } + + if ((type & osMutexRobust) != osMutexRobust) { + mem = -1; + + if (attr != NULL) { + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) { + mem = 1; + } + else { + if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { + mem = 0; + } + } + } + else { + mem = 0; + } + + if (mem == 1) { +#if (configSUPPORT_STATIC_ALLOCATION == 1) + if (rmtx != 0U) { +#if (configUSE_RECURSIVE_MUTEXES == 1) + hMutex = xSemaphoreCreateRecursiveMutexStatic (attr->cb_mem); +#endif + } + else { + hMutex = xSemaphoreCreateMutexStatic (attr->cb_mem); + } +#endif + } + else { + if (mem == 0) { +#if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + if (rmtx != 0U) { +#if (configUSE_RECURSIVE_MUTEXES == 1) + hMutex = xSemaphoreCreateRecursiveMutex (); +#endif + } else { + hMutex = xSemaphoreCreateMutex (); + } +#endif + } + } + +#if (configQUEUE_REGISTRY_SIZE > 0) + if (hMutex != NULL) { + if (attr != NULL) { + name = attr->name; + } else { + name = NULL; + } + vQueueAddToRegistry (hMutex, name); + } +#endif + + if ((hMutex != NULL) && (rmtx != 0U)) { + hMutex = (SemaphoreHandle_t)((uint32_t)hMutex | 1U); + } + } + } + + return ((osMutexId_t)hMutex); +} + +osStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) { + SemaphoreHandle_t hMutex; + osStatus_t stat; + uint32_t rmtx; + + hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); + + rmtx = (uint32_t)mutex_id & 1U; + + stat = osOK; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hMutex == NULL) { + stat = osErrorParameter; + } + else { + if (rmtx != 0U) { +#if (configUSE_RECURSIVE_MUTEXES == 1) + if (xSemaphoreTakeRecursive (hMutex, timeout) != pdPASS) { + if (timeout != 0U) { + stat = osErrorTimeout; + } else { + stat = osErrorResource; + } + } +#endif + } + else { + if (xSemaphoreTake (hMutex, timeout) != pdPASS) { + if (timeout != 0U) { + stat = osErrorTimeout; + } else { + stat = osErrorResource; + } + } + } + } + + return (stat); +} + +osStatus_t osMutexRelease (osMutexId_t mutex_id) { + SemaphoreHandle_t hMutex; + osStatus_t stat; + uint32_t rmtx; + + hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); + + rmtx = (uint32_t)mutex_id & 1U; + + stat = osOK; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hMutex == NULL) { + stat = osErrorParameter; + } + else { + if (rmtx != 0U) { +#if (configUSE_RECURSIVE_MUTEXES == 1) + if (xSemaphoreGiveRecursive (hMutex) != pdPASS) { + stat = osErrorResource; + } +#endif + } + else { + if (xSemaphoreGive (hMutex) != pdPASS) { + stat = osErrorResource; + } + } + } + + return (stat); +} + +osThreadId_t osMutexGetOwner (osMutexId_t mutex_id) { + SemaphoreHandle_t hMutex; + osThreadId_t owner; + + hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); + + if (IS_IRQ() || (hMutex == NULL)) { + owner = NULL; + } else { + owner = (osThreadId_t)xSemaphoreGetMutexHolder (hMutex); + } + + return (owner); +} + +osStatus_t osMutexDelete (osMutexId_t mutex_id) { + osStatus_t stat; +#ifndef USE_FreeRTOS_HEAP_1 + SemaphoreHandle_t hMutex; + + hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U); + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hMutex == NULL) { + stat = osErrorParameter; + } + else { +#if (configQUEUE_REGISTRY_SIZE > 0) + vQueueUnregisterQueue (hMutex); +#endif + stat = osOK; + vSemaphoreDelete (hMutex); + } +#else + stat = osError; +#endif + + return (stat); +} +#endif /* (configUSE_OS2_MUTEX == 1) */ + +/*---------------------------------------------------------------------------*/ + +osSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr) { + SemaphoreHandle_t hSemaphore; + int32_t mem; +#if (configQUEUE_REGISTRY_SIZE > 0) + const char *name; +#endif + + hSemaphore = NULL; + + if (!IS_IRQ() && (max_count > 0U) && (initial_count <= max_count)) { + mem = -1; + + if (attr != NULL) { + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) { + mem = 1; + } + else { + if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { + mem = 0; + } + } + } + else { + mem = 0; + } + + if (mem != -1) { + if (max_count == 1U) { + if (mem == 1) { +#if (configSUPPORT_STATIC_ALLOCATION == 1) + hSemaphore = xSemaphoreCreateBinaryStatic ((StaticSemaphore_t *)attr->cb_mem); +#endif + } + else { +#if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + hSemaphore = xSemaphoreCreateBinary(); +#endif + } + + if ((hSemaphore != NULL) && (initial_count != 0U)) { + if (xSemaphoreGive (hSemaphore) != pdPASS) { + vSemaphoreDelete (hSemaphore); + hSemaphore = NULL; + } + } + } + else { + if (mem == 1) { +#if (configSUPPORT_STATIC_ALLOCATION == 1) + hSemaphore = xSemaphoreCreateCountingStatic (max_count, initial_count, (StaticSemaphore_t *)attr->cb_mem); +#endif + } + else { +#if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + hSemaphore = xSemaphoreCreateCounting (max_count, initial_count); +#endif + } + } + +#if (configQUEUE_REGISTRY_SIZE > 0) + if (hSemaphore != NULL) { + if (attr != NULL) { + name = attr->name; + } else { + name = NULL; + } + vQueueAddToRegistry (hSemaphore, name); + } +#endif + } + } + + return ((osSemaphoreId_t)hSemaphore); +} + +osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout) { + SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id; + osStatus_t stat; + BaseType_t yield; + + stat = osOK; + + if (hSemaphore == NULL) { + stat = osErrorParameter; + } + else if (IS_IRQ()) { + if (timeout != 0U) { + stat = osErrorParameter; + } + else { + yield = pdFALSE; + + if (xSemaphoreTakeFromISR (hSemaphore, &yield) != pdPASS) { + stat = osErrorResource; + } else { + portYIELD_FROM_ISR (yield); + } + } + } + else { + if (xSemaphoreTake (hSemaphore, (TickType_t)timeout) != pdPASS) { + if (timeout != 0U) { + stat = osErrorTimeout; + } else { + stat = osErrorResource; + } + } + } + + return (stat); +} + +osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id) { + SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id; + osStatus_t stat; + BaseType_t yield; + + stat = osOK; + + if (hSemaphore == NULL) { + stat = osErrorParameter; + } + else if (IS_IRQ()) { + yield = pdFALSE; + + if (xSemaphoreGiveFromISR (hSemaphore, &yield) != pdTRUE) { + stat = osErrorResource; + } else { + portYIELD_FROM_ISR (yield); + } + } + else { + if (xSemaphoreGive (hSemaphore) != pdPASS) { + stat = osErrorResource; + } + } + + return (stat); +} + +uint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id) { + SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id; + uint32_t count; + + if (hSemaphore == NULL) { + count = 0U; + } + else if (IS_IRQ()) { + count = uxQueueMessagesWaitingFromISR (hSemaphore); + } else { + count = (uint32_t)uxSemaphoreGetCount (hSemaphore); + } + + return (count); +} + +osStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id) { + SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id; + osStatus_t stat; + +#ifndef USE_FreeRTOS_HEAP_1 + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hSemaphore == NULL) { + stat = osErrorParameter; + } + else { +#if (configQUEUE_REGISTRY_SIZE > 0) + vQueueUnregisterQueue (hSemaphore); +#endif + + stat = osOK; + vSemaphoreDelete (hSemaphore); + } +#else + stat = osError; +#endif + + return (stat); +} + +/*---------------------------------------------------------------------------*/ + +osMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) { + QueueHandle_t hQueue; + int32_t mem; +#if (configQUEUE_REGISTRY_SIZE > 0) + const char *name; +#endif + + hQueue = NULL; + + if (!IS_IRQ() && (msg_count > 0U) && (msg_size > 0U)) { + mem = -1; + + if (attr != NULL) { + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) && + (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) { + mem = 1; + } + else { + if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && + (attr->mq_mem == NULL) && (attr->mq_size == 0U)) { + mem = 0; + } + } + } + else { + mem = 0; + } + + if (mem == 1) { +#if (configSUPPORT_STATIC_ALLOCATION == 1) + hQueue = xQueueCreateStatic (msg_count, msg_size, attr->mq_mem, attr->cb_mem); +#endif + } + else { + if (mem == 0) { +#if (configSUPPORT_DYNAMIC_ALLOCATION == 1) + hQueue = xQueueCreate (msg_count, msg_size); +#endif + } + } + +#if (configQUEUE_REGISTRY_SIZE > 0) + if (hQueue != NULL) { + if (attr != NULL) { + name = attr->name; + } else { + name = NULL; + } + vQueueAddToRegistry (hQueue, name); + } +#endif + + } + + return ((osMessageQueueId_t)hQueue); +} + +osStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) { + QueueHandle_t hQueue = (QueueHandle_t)mq_id; + osStatus_t stat; + BaseType_t yield; + + (void)msg_prio; /* Message priority is ignored */ + + stat = osOK; + + if (IS_IRQ()) { + if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) { + stat = osErrorParameter; + } + else { + yield = pdFALSE; + + if (xQueueSendToBackFromISR (hQueue, msg_ptr, &yield) != pdTRUE) { + stat = osErrorResource; + } else { + portYIELD_FROM_ISR (yield); + } + } + } + else { + if ((hQueue == NULL) || (msg_ptr == NULL)) { + stat = osErrorParameter; + } + else { + if (xQueueSendToBack (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) { + if (timeout != 0U) { + stat = osErrorTimeout; + } else { + stat = osErrorResource; + } + } + } + } + + return (stat); +} + +osStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) { + QueueHandle_t hQueue = (QueueHandle_t)mq_id; + osStatus_t stat; + BaseType_t yield; + + (void)msg_prio; /* Message priority is ignored */ + + stat = osOK; + + if (IS_IRQ()) { + if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) { + stat = osErrorParameter; + } + else { + yield = pdFALSE; + + if (xQueueReceiveFromISR (hQueue, msg_ptr, &yield) != pdPASS) { + stat = osErrorResource; + } else { + portYIELD_FROM_ISR (yield); + } + } + } + else { + if ((hQueue == NULL) || (msg_ptr == NULL)) { + stat = osErrorParameter; + } + else { + if (xQueueReceive (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) { + if (timeout != 0U) { + stat = osErrorTimeout; + } else { + stat = osErrorResource; + } + } + } + } + + return (stat); +} + +uint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id) { + StaticQueue_t *mq = (StaticQueue_t *)mq_id; + uint32_t capacity; + + if (mq == NULL) { + capacity = 0U; + } else { + /* capacity = pxQueue->uxLength */ + capacity = mq->uxDummy4[1]; + } + + return (capacity); +} + +uint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id) { + StaticQueue_t *mq = (StaticQueue_t *)mq_id; + uint32_t size; + + if (mq == NULL) { + size = 0U; + } else { + /* size = pxQueue->uxItemSize */ + size = mq->uxDummy4[2]; + } + + return (size); +} + +uint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id) { + QueueHandle_t hQueue = (QueueHandle_t)mq_id; + UBaseType_t count; + + if (hQueue == NULL) { + count = 0U; + } + else if (IS_IRQ()) { + count = uxQueueMessagesWaitingFromISR (hQueue); + } + else { + count = uxQueueMessagesWaiting (hQueue); + } + + return ((uint32_t)count); +} + +uint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id) { + StaticQueue_t *mq = (StaticQueue_t *)mq_id; + uint32_t space; + uint32_t isrm; + + if (mq == NULL) { + space = 0U; + } + else if (IS_IRQ()) { + isrm = taskENTER_CRITICAL_FROM_ISR(); + + /* space = pxQueue->uxLength - pxQueue->uxMessagesWaiting; */ + space = mq->uxDummy4[1] - mq->uxDummy4[0]; + + taskEXIT_CRITICAL_FROM_ISR(isrm); + } + else { + space = (uint32_t)uxQueueSpacesAvailable ((QueueHandle_t)mq); + } + + return (space); +} + +osStatus_t osMessageQueueReset (osMessageQueueId_t mq_id) { + QueueHandle_t hQueue = (QueueHandle_t)mq_id; + osStatus_t stat; + + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hQueue == NULL) { + stat = osErrorParameter; + } + else { + stat = osOK; + (void)xQueueReset (hQueue); + } + + return (stat); +} + +osStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id) { + QueueHandle_t hQueue = (QueueHandle_t)mq_id; + osStatus_t stat; + +#ifndef USE_FreeRTOS_HEAP_1 + if (IS_IRQ()) { + stat = osErrorISR; + } + else if (hQueue == NULL) { + stat = osErrorParameter; + } + else { +#if (configQUEUE_REGISTRY_SIZE > 0) + vQueueUnregisterQueue (hQueue); +#endif + + stat = osOK; + vQueueDelete (hQueue); + } +#else + stat = osError; +#endif + + return (stat); +} + +/*---------------------------------------------------------------------------*/ +#ifdef FREERTOS_MPOOL_H_ + +/* Static memory pool functions */ +static void FreeBlock (MemPool_t *mp, void *block); +static void *AllocBlock (MemPool_t *mp); +static void *CreateBlock (MemPool_t *mp); + +osMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr) { + MemPool_t *mp; + const char *name; + int32_t mem_cb, mem_mp; + uint32_t sz; + + if (IS_IRQ()) { + mp = NULL; + } + else if ((block_count == 0U) || (block_size == 0U)) { + mp = NULL; + } + else { + mp = NULL; + sz = MEMPOOL_ARR_SIZE (block_count, block_size); + + name = NULL; + mem_cb = -1; + mem_mp = -1; + + if (attr != NULL) { + if (attr->name != NULL) { + name = attr->name; + } + + if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(MemPool_t))) { + /* Static control block is provided */ + mem_cb = 1; + } + else if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) { + /* Allocate control block memory on heap */ + mem_cb = 0; + } + + if ((attr->mp_mem == NULL) && (attr->mp_size == 0U)) { + /* Allocate memory array on heap */ + mem_mp = 0; + } + else { + if (attr->mp_mem != NULL) { + /* Check if array is 4-byte aligned */ + if (((uint32_t)attr->mp_mem & 3U) == 0U) { + /* Check if array big enough */ + if (attr->mp_size >= sz) { + /* Static memory pool array is provided */ + mem_mp = 1; + } + } + } + } + } + else { + /* Attributes not provided, allocate memory on heap */ + mem_cb = 0; + mem_mp = 0; + } + + if (mem_cb == 0) { + mp = pvPortMalloc (sizeof(MemPool_t)); + } else { + mp = attr->cb_mem; + } + + if (mp != NULL) { + /* Create a semaphore (max count == initial count == block_count) */ +#if (configSUPPORT_STATIC_ALLOCATION == 1) + mp->sem = xSemaphoreCreateCountingStatic (block_count, block_count, &mp->mem_sem); +#elif (configSUPPORT_DYNAMIC_ALLOCATION == 1) + mp->sem = xSemaphoreCreateCounting (block_count, block_count); +#else + mp->sem == NULL; +#endif + + if (mp->sem != NULL) { + /* Setup memory array */ + if (mem_mp == 0) { + mp->mem_arr = pvPortMalloc (sz); + } else { + mp->mem_arr = attr->mp_mem; + } + } + } + + if ((mp != NULL) && (mp->mem_arr != NULL)) { + /* Memory pool can be created */ + mp->head = NULL; + mp->mem_sz = sz; + mp->name = name; + mp->bl_sz = block_size; + mp->bl_cnt = block_count; + mp->n = 0U; + + /* Set heap allocated memory flags */ + mp->status = MPOOL_STATUS; + + if (mem_cb == 0) { + /* Control block on heap */ + mp->status |= 1U; + } + if (mem_mp == 0) { + /* Memory array on heap */ + mp->status |= 2U; + } + } + else { + /* Memory pool cannot be created, release allocated resources */ + if ((mem_cb == 0) && (mp != NULL)) { + /* Free control block memory */ + vPortFree (mp); + } + mp = NULL; + } + } + + return (mp); +} + +const char *osMemoryPoolGetName (osMemoryPoolId_t mp_id) { + MemPool_t *mp = (osMemoryPoolId_t)mp_id; + const char *p; + + if (IS_IRQ()) { + p = NULL; + } + else if (mp_id == NULL) { + p = NULL; + } + else { + p = mp->name; + } + + return (p); +} + +void *osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout) { + MemPool_t *mp; + void *block; + uint32_t isrm; + + if (mp_id == NULL) { + /* Invalid input parameters */ + block = NULL; + } + else { + block = NULL; + + mp = (MemPool_t *)mp_id; + + if ((mp->status & MPOOL_STATUS) == MPOOL_STATUS) { + if (IS_IRQ()) { + if (timeout == 0U) { + if (xSemaphoreTakeFromISR (mp->sem, NULL) == pdTRUE) { + if ((mp->status & MPOOL_STATUS) == MPOOL_STATUS) { + isrm = taskENTER_CRITICAL_FROM_ISR(); + + /* Get a block from the free-list */ + block = AllocBlock(mp); + + if (block == NULL) { + /* List of free blocks is empty, 'create' new block */ + block = CreateBlock(mp); + } + + taskEXIT_CRITICAL_FROM_ISR(isrm); + } + } + } + } + else { + if (xSemaphoreTake (mp->sem, (TickType_t)timeout) == pdTRUE) { + if ((mp->status & MPOOL_STATUS) == MPOOL_STATUS) { + taskENTER_CRITICAL(); + + /* Get a block from the free-list */ + block = AllocBlock(mp); + + if (block == NULL) { + /* List of free blocks is empty, 'create' new block */ + block = CreateBlock(mp); + } + + taskEXIT_CRITICAL(); + } + } + } + } + } + + return (block); +} + +osStatus_t osMemoryPoolFree (osMemoryPoolId_t mp_id, void *block) { + MemPool_t *mp; + osStatus_t stat; + uint32_t isrm; + BaseType_t yield; + + if ((mp_id == NULL) || (block == NULL)) { + /* Invalid input parameters */ + stat = osErrorParameter; + } + else { + mp = (MemPool_t *)mp_id; + + if ((mp->status & MPOOL_STATUS) != MPOOL_STATUS) { + /* Invalid object status */ + stat = osErrorResource; + } + else if ((block < (void *)&mp->mem_arr[0]) || (block > (void*)&mp->mem_arr[mp->mem_sz-1])) { + /* Block pointer outside of memory array area */ + stat = osErrorParameter; + } + else { + stat = osOK; + + if (IS_IRQ()) { + if (uxSemaphoreGetCountFromISR (mp->sem) == mp->bl_cnt) { + stat = osErrorResource; + } + else { + isrm = taskENTER_CRITICAL_FROM_ISR(); + + /* Add block to the list of free blocks */ + FreeBlock(mp, block); + + taskEXIT_CRITICAL_FROM_ISR(isrm); + + yield = pdFALSE; + xSemaphoreGiveFromISR (mp->sem, &yield); + portYIELD_FROM_ISR (yield); + } + } + else { + if (uxSemaphoreGetCount (mp->sem) == mp->bl_cnt) { + stat = osErrorResource; + } + else { + taskENTER_CRITICAL(); + + /* Add block to the list of free blocks */ + FreeBlock(mp, block); + + taskEXIT_CRITICAL(); + + xSemaphoreGive (mp->sem); + } + } + } + } + + return (stat); +} + +uint32_t osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id) { + MemPool_t *mp; + uint32_t n; + + if (mp_id == NULL) { + /* Invalid input parameters */ + n = 0U; + } + else { + mp = (MemPool_t *)mp_id; + + if ((mp->status & MPOOL_STATUS) != MPOOL_STATUS) { + /* Invalid object status */ + n = 0U; + } + else { + n = mp->bl_cnt; + } + } + + /* Return maximum number of memory blocks */ + return (n); +} + +uint32_t osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id) { + MemPool_t *mp; + uint32_t sz; + + if (mp_id == NULL) { + /* Invalid input parameters */ + sz = 0U; + } + else { + mp = (MemPool_t *)mp_id; + + if ((mp->status & MPOOL_STATUS) != MPOOL_STATUS) { + /* Invalid object status */ + sz = 0U; + } + else { + sz = mp->bl_sz; + } + } + + /* Return memory block size in bytes */ + return (sz); +} + +uint32_t osMemoryPoolGetCount (osMemoryPoolId_t mp_id) { + MemPool_t *mp; + uint32_t n; + + if (mp_id == NULL) { + /* Invalid input parameters */ + n = 0U; + } + else { + mp = (MemPool_t *)mp_id; + + if ((mp->status & MPOOL_STATUS) != MPOOL_STATUS) { + /* Invalid object status */ + n = 0U; + } + else { + if (IS_IRQ()) { + n = uxSemaphoreGetCountFromISR (mp->sem); + } else { + n = uxSemaphoreGetCount (mp->sem); + } + + n = mp->bl_cnt - n; + } + } + + /* Return number of memory blocks used */ + return (n); +} + +uint32_t osMemoryPoolGetSpace (osMemoryPoolId_t mp_id) { + MemPool_t *mp; + uint32_t n; + + if (mp_id == NULL) { + /* Invalid input parameters */ + n = 0U; + } + else { + mp = (MemPool_t *)mp_id; + + if ((mp->status & MPOOL_STATUS) != MPOOL_STATUS) { + /* Invalid object status */ + n = 0U; + } + else { + if (IS_IRQ()) { + n = uxSemaphoreGetCountFromISR (mp->sem); + } else { + n = uxSemaphoreGetCount (mp->sem); + } + } + } + + /* Return number of memory blocks available */ + return (n); +} + +osStatus_t osMemoryPoolDelete (osMemoryPoolId_t mp_id) { + MemPool_t *mp; + osStatus_t stat; + + if (mp_id == NULL) { + /* Invalid input parameters */ + stat = osErrorParameter; + } + else if (IS_IRQ()) { + stat = osErrorISR; + } + else { + mp = (MemPool_t *)mp_id; + + taskENTER_CRITICAL(); + + /* Invalidate control block status */ + mp->status = mp->status & 3U; + + /* Wake-up tasks waiting for pool semaphore */ + while (xSemaphoreGive (mp->sem) == pdTRUE); + + mp->head = NULL; + mp->bl_sz = 0U; + mp->bl_cnt = 0U; + + if ((mp->status & 2U) != 0U) { + /* Memory pool array allocated on heap */ + vPortFree (mp->mem_arr); + } + if ((mp->status & 1U) != 0U) { + /* Memory pool control block allocated on heap */ + vPortFree (mp); + } + + taskEXIT_CRITICAL(); + + stat = osOK; + } + + return (stat); +} + +/* + Create new block given according to the current block index. +*/ +static void *CreateBlock (MemPool_t *mp) { + MemPoolBlock_t *p = NULL; + + if (mp->n < mp->bl_cnt) { + /* Unallocated blocks exist, set pointer to new block */ + p = (void *)(mp->mem_arr + (mp->bl_sz * mp->n)); + + /* Increment block index */ + mp->n += 1U; + } + + return (p); +} + +/* + Allocate a block by reading the list of free blocks. +*/ +static void *AllocBlock (MemPool_t *mp) { + MemPoolBlock_t *p = NULL; + + if (mp->head != NULL) { + /* List of free block exists, get head block */ + p = mp->head; + + /* Head block is now next on the list */ + mp->head = p->next; + } + + return (p); +} + +/* + Free block by putting it to the list of free blocks. +*/ +static void FreeBlock (MemPool_t *mp, void *block) { + MemPoolBlock_t *p = block; + + /* Store current head into block memory space */ + p->next = mp->head; + + /* Store current block as new head */ + mp->head = p; +} +#endif /* FREERTOS_MPOOL_H_ */ +/*---------------------------------------------------------------------------*/ + +/* Callback function prototypes */ +extern void vApplicationIdleHook (void); +extern void vApplicationTickHook (void); +extern void vApplicationMallocFailedHook (void); +extern void vApplicationDaemonTaskStartupHook (void); +extern void vApplicationStackOverflowHook (TaskHandle_t xTask, const char *pcTaskName); + +/** + Dummy implementation of the callback function vApplicationIdleHook(). +*/ +#if (configUSE_IDLE_HOOK == 1) +__WEAK void vApplicationIdleHook (void){} +#endif + +/** + Dummy implementation of the callback function vApplicationTickHook(). +*/ +#if (configUSE_TICK_HOOK == 1) + __WEAK void vApplicationTickHook (void){} +#endif + +/** + Dummy implementation of the callback function vApplicationMallocFailedHook(). +*/ +#if (configUSE_MALLOC_FAILED_HOOK == 1) +__WEAK void vApplicationMallocFailedHook (void){} +#endif + +/** + Dummy implementation of the callback function vApplicationDaemonTaskStartupHook(). +*/ +#if (configUSE_DAEMON_TASK_STARTUP_HOOK == 1) +__WEAK void vApplicationDaemonTaskStartupHook (void){} +#endif + +/** + Dummy implementation of the callback function vApplicationStackOverflowHook(). +*/ +#if (configCHECK_FOR_STACK_OVERFLOW > 0) +__WEAK void vApplicationStackOverflowHook (TaskHandle_t xTask, const char *pcTaskName) { + (void)xTask; + (void)pcTaskName; + configASSERT(0); +} +#endif + +/*---------------------------------------------------------------------------*/ +#if (configSUPPORT_STATIC_ALLOCATION == 1) +/* External Idle and Timer task static memory allocation functions */ +extern void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize); +extern void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize); + +/* + vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION + equals to 1 and is required for static memory allocation support. +*/ +__WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) { + /* Idle task control block and stack */ + static StaticTask_t Idle_TCB; + static StackType_t Idle_Stack[configMINIMAL_STACK_SIZE]; + + *ppxIdleTaskTCBBuffer = &Idle_TCB; + *ppxIdleTaskStackBuffer = &Idle_Stack[0]; + *pulIdleTaskStackSize = (uint32_t)configMINIMAL_STACK_SIZE; +} + +/* + vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION + equals to 1 and is required for static memory allocation support. +*/ +__WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) { + /* Timer task control block and stack */ + static StaticTask_t Timer_TCB; + static StackType_t Timer_Stack[configTIMER_TASK_STACK_DEPTH]; + + *ppxTimerTaskTCBBuffer = &Timer_TCB; + *ppxTimerTaskStackBuffer = &Timer_Stack[0]; + *pulTimerTaskStackSize = (uint32_t)configTIMER_TASK_STACK_DEPTH; +} +#endif + +#endif diff --git a/MODULES/FreeRTOSCmsis/modular.json b/MODULES/FreeRTOSCmsis/modular.json new file mode 100644 index 0000000..b65f344 --- /dev/null +++ b/MODULES/FreeRTOSCmsis/modular.json @@ -0,0 +1,22 @@ +{ + "dep": [ + { + "type": "local", + + "dir": "./MODULES/CmsisRtosInterface" + }, + { + "type": "local", + + "dir": "./MODULES/FreeRTOS" + } + ], + "cmake": { + "inc_dirs": [ + "Inc" + ], + "srcs": [ + "Src/**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/FreeRTOSHeap4/Src/heap_4.c b/MODULES/FreeRTOSHeap4/Src/heap_4.c new file mode 100644 index 0000000..fb8e035 --- /dev/null +++ b/MODULES/FreeRTOSHeap4/Src/heap_4.c @@ -0,0 +1,502 @@ +/* + * FreeRTOS Kernel V10.4.3 LTS Patch 2 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* + * A sample implementation of pvPortMalloc() and vPortFree() that combines + * (coalescences) adjacent memory blocks as they are freed, and in so doing + * limits memory fragmentation. + * + * See heap_1.c, heap_2.c and heap_3.c for alternative implementations, and the + * memory management pages of https://www.FreeRTOS.org for more information. + */ +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining + * all the API functions to use the MPU wrappers. That should only be done when + * task.h is included from an application file. */ +#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#include "FreeRTOS.h" +#include "task.h" + +#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE + +#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) + #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0 +#endif + +/* Block sizes must not get too small. */ +#define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) ) + +/* Assumes 8bit bytes! */ +#define heapBITS_PER_BYTE ( ( size_t ) 8 ) + +/* Allocate the memory for the heap. */ +#if ( configAPPLICATION_ALLOCATED_HEAP == 1 ) + +/* The application writer has already defined the array used for the RTOS +* heap - probably so it can be placed in a special segment or address. */ + extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; +#else + PRIVILEGED_DATA static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ]; +#endif /* configAPPLICATION_ALLOCATED_HEAP */ + +/* Define the linked list structure. This is used to link free blocks in order + * of their memory address. */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK * pxNextFreeBlock; /*<< The next free block in the list. */ + size_t xBlockSize; /*<< The size of the free block. */ +} BlockLink_t; + +/*-----------------------------------------------------------*/ + +/* + * Inserts a block of memory that is being freed into the correct position in + * the list of free memory blocks. The block being freed will be merged with + * the block in front it and/or the block behind it if the memory blocks are + * adjacent to each other. + */ +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) PRIVILEGED_FUNCTION; + +/* + * Called automatically to setup the required heap structures the first time + * pvPortMalloc() is called. + */ +static void prvHeapInit( void ) PRIVILEGED_FUNCTION; + +/*-----------------------------------------------------------*/ + +/* The size of the structure placed at the beginning of each allocated memory + * block must by correctly byte aligned. */ +static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); + +/* Create a couple of list links to mark the start and end of the list. */ +PRIVILEGED_DATA static BlockLink_t xStart, * pxEnd = NULL; + +/* Keeps track of the number of calls to allocate and free memory as well as the + * number of free bytes remaining, but says nothing about fragmentation. */ +PRIVILEGED_DATA static size_t xFreeBytesRemaining = 0U; +PRIVILEGED_DATA static size_t xMinimumEverFreeBytesRemaining = 0U; +PRIVILEGED_DATA static size_t xNumberOfSuccessfulAllocations = 0; +PRIVILEGED_DATA static size_t xNumberOfSuccessfulFrees = 0; + +/* Gets set to the top bit of an size_t type. When this bit in the xBlockSize + * member of an BlockLink_t structure is set then the block belongs to the + * application. When the bit is free the block is still part of the free heap + * space. */ +PRIVILEGED_DATA static size_t xBlockAllocatedBit = 0; + +/*-----------------------------------------------------------*/ + +void * pvPortMalloc( size_t xWantedSize ) +{ + BlockLink_t * pxBlock, * pxPreviousBlock, * pxNewBlockLink; + void * pvReturn = NULL; + + vTaskSuspendAll(); + { + /* If this is the first call to malloc then the heap will require + * initialisation to setup the list of free blocks. */ + if( pxEnd == NULL ) + { + prvHeapInit(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Check the requested block size is not so large that the top bit is + * set. The top bit of the block size member of the BlockLink_t structure + * is used to determine who owns the block - the application or the + * kernel, so it must be free. */ + if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) + { + /* The wanted size must be increased so it can contain a BlockLink_t + * structure in addition to the requested amount of bytes. */ + if( ( xWantedSize > 0 ) && + ( ( xWantedSize + xHeapStructSize ) > xWantedSize ) ) /* Overflow check */ + { + xWantedSize += xHeapStructSize; + + /* Ensure that blocks are always aligned. */ + if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 ) + { + /* Byte alignment required. Check for overflow. */ + if( ( xWantedSize + ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ) ) + > xWantedSize ) + { + xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ); + configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 ); + } + else + { + xWantedSize = 0; + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xWantedSize = 0; + } + + if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) + { + /* Traverse the list from the start (lowest address) block until + * one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + + while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If the end marker was reached then a block of adequate size + * was not found. */ + if( pxBlock != pxEnd ) + { + /* Return the memory space pointed to - jumping over the + * BlockLink_t structure at its start. */ + pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); + + /* This block is being returned for use so must be taken out + * of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into + * two. */ + if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) + { + /* This block is to be split into two. Create a new + * block following the number of bytes requested. The void + * cast is used to prevent byte alignment warnings from the + * compiler. */ + pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); + configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 ); + + /* Calculate the sizes of two blocks split from the + * single block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + prvInsertBlockIntoFreeList( pxNewBlockLink ); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + + if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* The block is being returned - it is allocated and owned + * by the application and has no "next" block. */ + pxBlock->xBlockSize |= xBlockAllocatedBit; + pxBlock->pxNextFreeBlock = NULL; + xNumberOfSuccessfulAllocations++; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + traceMALLOC( pvReturn, xWantedSize ); + } + ( void ) xTaskResumeAll(); + + #if ( configUSE_MALLOC_FAILED_HOOK == 1 ) + { + if( pvReturn == NULL ) + { + extern void vApplicationMallocFailedHook( void ); + vApplicationMallocFailedHook(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + #endif /* if ( configUSE_MALLOC_FAILED_HOOK == 1 ) */ + + configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 ); + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree( void * pv ) +{ + uint8_t * puc = ( uint8_t * ) pv; + BlockLink_t * pxLink; + + if( pv != NULL ) + { + /* The memory being freed will have an BlockLink_t structure immediately + * before it. */ + puc -= xHeapStructSize; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = ( void * ) puc; + + /* Check the block is actually allocated. */ + configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); + configASSERT( pxLink->pxNextFreeBlock == NULL ); + + if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) + { + if( pxLink->pxNextFreeBlock == NULL ) + { + /* The block is being returned to the heap - it is no longer + * allocated. */ + pxLink->xBlockSize &= ~xBlockAllocatedBit; + + vTaskSuspendAll(); + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + traceFREE( pv, pxLink->xBlockSize ); + prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); + xNumberOfSuccessfulFrees++; + } + ( void ) xTaskResumeAll(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize( void ) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetMinimumEverFreeHeapSize( void ) +{ + return xMinimumEverFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +void vPortInitialiseBlocks( void ) +{ + /* This just exists to keep the linker quiet. */ +} +/*-----------------------------------------------------------*/ + +static void prvHeapInit( void ) /* PRIVILEGED_FUNCTION */ +{ + BlockLink_t * pxFirstFreeBlock; + uint8_t * pucAlignedHeap; + size_t uxAddress; + size_t xTotalHeapSize = configTOTAL_HEAP_SIZE; + + /* Ensure the heap starts on a correctly aligned boundary. */ + uxAddress = ( size_t ) ucHeap; + + if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 ) + { + uxAddress += ( portBYTE_ALIGNMENT - 1 ); + uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); + xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; + } + + pucAlignedHeap = ( uint8_t * ) uxAddress; + + /* xStart is used to hold a pointer to the first item in the list of free + * blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; + xStart.xBlockSize = ( size_t ) 0; + + /* pxEnd is used to mark the end of the list of free blocks and is inserted + * at the end of the heap space. */ + uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; + uxAddress -= xHeapStructSize; + uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); + pxEnd = ( void * ) uxAddress; + pxEnd->xBlockSize = 0; + pxEnd->pxNextFreeBlock = NULL; + + /* To start with there is a single free block that is sized to take up the + * entire heap space, minus the space taken by pxEnd. */ + pxFirstFreeBlock = ( void * ) pucAlignedHeap; + pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; + pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + + /* Only one block exists - and it covers the entire usable heap space. */ + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + + /* Work out the position of the top bit in a size_t variable. */ + xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ); +} +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) /* PRIVILEGED_FUNCTION */ +{ + BlockLink_t * pxIterator; + uint8_t * puc; + + /* Iterate through the list until a block is found that has a higher address + * than the block being inserted. */ + for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) + { + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxIterator; + + if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + pxBlockToInsert = pxIterator; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Do the block being inserted, and the block it is being inserted before + * make a contiguous block of memory? */ + puc = ( uint8_t * ) pxBlockToInsert; + + if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) + { + if( pxIterator->pxNextFreeBlock != pxEnd ) + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + } + + /* If the block being inserted plugged a gab, so was merged with the block + * before and the block after, then it's pxNextFreeBlock pointer will have + * already been set, and should not be set here as that would make it point + * to itself. */ + if( pxIterator != pxBlockToInsert ) + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } +} +/*-----------------------------------------------------------*/ + +void vPortGetHeapStats( HeapStats_t * pxHeapStats ) +{ + BlockLink_t * pxBlock; + size_t xBlocks = 0, xMaxSize = 0, xMinSize = portMAX_DELAY; /* portMAX_DELAY used as a portable way of getting the maximum value. */ + + vTaskSuspendAll(); + { + pxBlock = xStart.pxNextFreeBlock; + + /* pxBlock will be NULL if the heap has not been initialised. The heap + * is initialised automatically when the first allocation is made. */ + if( pxBlock != NULL ) + { + do + { + /* Increment the number of blocks and record the largest block seen + * so far. */ + xBlocks++; + + if( pxBlock->xBlockSize > xMaxSize ) + { + xMaxSize = pxBlock->xBlockSize; + } + + if( pxBlock->xBlockSize < xMinSize ) + { + xMinSize = pxBlock->xBlockSize; + } + + /* Move to the next block in the chain until the last block is + * reached. */ + pxBlock = pxBlock->pxNextFreeBlock; + } while( pxBlock != pxEnd ); + } + } + ( void ) xTaskResumeAll(); + + pxHeapStats->xSizeOfLargestFreeBlockInBytes = xMaxSize; + pxHeapStats->xSizeOfSmallestFreeBlockInBytes = xMinSize; + pxHeapStats->xNumberOfFreeBlocks = xBlocks; + + taskENTER_CRITICAL(); + { + pxHeapStats->xAvailableHeapSpaceInBytes = xFreeBytesRemaining; + pxHeapStats->xNumberOfSuccessfulAllocations = xNumberOfSuccessfulAllocations; + pxHeapStats->xNumberOfSuccessfulFrees = xNumberOfSuccessfulFrees; + pxHeapStats->xMinimumEverFreeBytesRemaining = xMinimumEverFreeBytesRemaining; + } + taskEXIT_CRITICAL(); +} diff --git a/MODULES/FreeRTOSHeap4/modular.json b/MODULES/FreeRTOSHeap4/modular.json new file mode 100644 index 0000000..2fb11cb --- /dev/null +++ b/MODULES/FreeRTOSHeap4/modular.json @@ -0,0 +1,14 @@ +{ + "dep": [ + { + "type": "local", + + "dir": "./MODULES/FreeRTOS" + } + ], + "cmake": { + "srcs": [ + "Src/**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/FreeRTOSHeap4_CM7_CMSIS/modular.json b/MODULES/FreeRTOSHeap4_CM7_CMSIS/modular.json new file mode 100644 index 0000000..df57abd --- /dev/null +++ b/MODULES/FreeRTOSHeap4_CM7_CMSIS/modular.json @@ -0,0 +1,24 @@ +{ + "dep": [ + { + "type": "local", + + "dir": "./MODULES/FreeRTOS" + }, + { + "type": "local", + + "dir": "./MODULES/FreeRTOSHeap4" + }, + { + "type": "local", + + "dir": "./MODULES/FreeRTOSPortable_GCC_CM7" + }, + { + "type": "local", + + "dir": "./MODULES/FreeRTOSCmsis" + } + ] +} \ No newline at end of file diff --git a/MODULES/FreeRTOSPortable_GCC_CM7/Inc/portmacro.h b/MODULES/FreeRTOSPortable_GCC_CM7/Inc/portmacro.h new file mode 100644 index 0000000..c0cd00a --- /dev/null +++ b/MODULES/FreeRTOSPortable_GCC_CM7/Inc/portmacro.h @@ -0,0 +1,248 @@ +/* + * FreeRTOS Kernel V10.4.3 LTS Patch 3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + * 1 tab == 4 spaces! + */ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + +#if ( configUSE_16_BIT_TICKS == 1 ) +typedef uint16_t TickType_t; +#define portMAX_DELAY ( TickType_t ) 0xffff +#else +typedef uint32_t TickType_t; +#define portMAX_DELAY ( TickType_t ) 0xffffffffUL + +/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + * not need to be guarded with a critical section. */ +#define portTICK_TYPE_IS_ATOMIC 1 +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specifics. */ +#define portSTACK_GROWTH ( -1 ) +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portBYTE_ALIGNMENT 8 +#define portDONT_DISCARD __attribute__( ( used ) ) +/*-----------------------------------------------------------*/ + +/* Scheduler utilities. */ +#define portYIELD() \ + { \ + /* Set a PendSV to request a context switch. */ \ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \ + \ + /* Barriers are normally not required but do ensure the code is completely \ + * within the specified behaviour for the architecture. */ \ + __asm volatile ( "dsb" ::: "memory" ); \ + __asm volatile ( "isb" ); \ + } + +#define portNVIC_INT_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed04 ) ) +#define portNVIC_PENDSVSET_BIT ( 1UL << 28UL ) +#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD() +#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x ) +/*-----------------------------------------------------------*/ + +/* Critical section management. */ +extern void vPortEnterCritical(void); +extern void vPortExitCritical(void); +#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vPortSetBASEPRI( x ) +#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() +#define portENABLE_INTERRUPTS() vPortSetBASEPRI( 0 ) +#define portENTER_CRITICAL() vPortEnterCritical() +#define portEXIT_CRITICAL() vPortExitCritical() + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. These are + * not necessary for to use this port. They are defined so the common demo files + * (which build with all the ports) will build. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) +/*-----------------------------------------------------------*/ + +/* Tickless idle/low power functionality. */ +#ifndef portSUPPRESS_TICKS_AND_SLEEP +extern void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime); +#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) +#endif +/*-----------------------------------------------------------*/ + +/* Architecture specific optimisations. */ +#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#endif + +#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 + +/* Generic helper function. */ +__attribute__((always_inline)) static inline uint8_t ucPortCountLeadingZeros(uint32_t ulBitmap) +{ + uint8_t ucReturn; + + __asm volatile("clz %0, %1" : "=r"(ucReturn) : "r"(ulBitmap) : "memory"); + + return ucReturn; +} + +/* Check the configuration. */ +#if ( configMAX_PRIORITIES > 32 ) +#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice. +#endif + +/* Store/clear the ready priorities in a bit map. */ +#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) ) +#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) ) + +/*-----------------------------------------------------------*/ + +#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) ) + +#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */ + +/*-----------------------------------------------------------*/ + +#ifdef configASSERT +void vPortValidateInterruptPriority(void); +#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() vPortValidateInterruptPriority() +#endif + +/* portNOP() is not required by this port. */ +#define portNOP() + +#define portINLINE __inline + +#ifndef portFORCE_INLINE +#define portFORCE_INLINE inline __attribute__( ( always_inline ) ) +#endif + +portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt(void) +{ + uint32_t ulCurrentInterrupt; + BaseType_t xReturn; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile("mrs %0, ipsr" : "=r"(ulCurrentInterrupt)::"memory"); + + if (ulCurrentInterrupt == 0) + { + xReturn = pdFALSE; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} + +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static void vPortRaiseBASEPRI(void) +{ + uint32_t ulNewBASEPRI; + + __asm volatile + ( + " mov %0, %1 \n"\ + " cpsid i \n"\ + " msr basepri, %0 \n"\ + " isb \n"\ + " dsb \n"\ + " cpsie i \n"\ + : "=r"(ulNewBASEPRI) : "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) : "memory" + ); +} + +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI(void) +{ + uint32_t ulOriginalBASEPRI, ulNewBASEPRI; + + __asm volatile + ( + " mrs %0, basepri \n"\ + " mov %1, %2 \n"\ + " cpsid i \n"\ + " msr basepri, %1 \n"\ + " isb \n"\ + " dsb \n"\ + " cpsie i \n"\ + : "=r"(ulOriginalBASEPRI), "=r"(ulNewBASEPRI) : "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) : "memory" + ); + + /* This return will not be reached but is necessary to prevent compiler + * warnings. */ + return ulOriginalBASEPRI; +} +/*-----------------------------------------------------------*/ + +portFORCE_INLINE static void vPortSetBASEPRI(uint32_t ulNewMaskValue) +{ + __asm volatile + ( + " msr basepri, %0 "::"r"(ulNewMaskValue) : "memory" + ); +} +/*-----------------------------------------------------------*/ + +#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ diff --git a/MODULES/FreeRTOSPortable_GCC_CM7/Src/port.c b/MODULES/FreeRTOSPortable_GCC_CM7/Src/port.c new file mode 100644 index 0000000..a8ac666 --- /dev/null +++ b/MODULES/FreeRTOSPortable_GCC_CM7/Src/port.c @@ -0,0 +1,773 @@ +/* + * FreeRTOS Kernel V10.4.3 LTS Patch 3 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/*----------------------------------------------------------- +* Implementation of functions defined in portable.h for the ARM CM7 port. +*----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#ifndef __VFP_FP__ +#error This port can only be used when the project options are configured to enable hardware floating point support. +#endif + +#ifndef configSYSTICK_CLOCK_HZ +#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ +/* Ensure the SysTick is clocked at the same frequency as the core. */ +#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL ) +#else + +/* The way the SysTick is clocked is not modified in case it is not the same + * as the core. */ +#define portNVIC_SYSTICK_CLK_BIT ( 0 ) +#endif + +/* Constants required to manipulate the core. Registers first... */ +#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) ) +#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) ) +#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) ) +#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) ) +/* ...then bits in the registers. */ +#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL ) +#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL ) +#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL ) +#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL ) +#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL ) + +#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL ) +#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL ) + +/* Constants required to check the validity of an interrupt priority. */ +#define portFIRST_USER_INTERRUPT_NUMBER ( 16 ) +#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 ) +#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) ) +#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff ) +#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 ) +#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 ) +#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL ) +#define portPRIGROUP_SHIFT ( 8UL ) + +/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */ +#define portVECTACTIVE_MASK ( 0xFFUL ) + +/* Constants required to manipulate the VFP. */ +#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */ +#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL ) + +/* Constants required to set up the initial stack. */ +#define portINITIAL_XPSR ( 0x01000000 ) +#define portINITIAL_EXC_RETURN ( 0xfffffffd ) + +/* The systick is a 24-bit counter. */ +#define portMAX_24_BIT_NUMBER ( 0xffffffUL ) + +/* For strict compliance with the Cortex-M spec the task start address should + * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */ +#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL ) + +/* A fiddle factor to estimate the number of SysTick counts that would have + * occurred while the SysTick counter is stopped during tickless idle + * calculations. */ +#define portMISSED_COUNTS_FACTOR ( 45UL ) + +/* Let the user override the pre-loading of the initial LR with the address of + * prvTaskExitError() in case it messes up unwinding of the stack in the + * debugger. */ +#ifdef configTASK_RETURN_ADDRESS +#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS +#else +#define portTASK_RETURN_ADDRESS prvTaskExitError +#endif + +/* + * Setup the timer to generate the tick interrupts. The implementation in this + * file is weak to allow application writers to change the timer used to + * generate the tick interrupt. + */ +void vPortSetupTimerInterrupt(void); + +/* + * Exception handlers. + */ +void xPortPendSVHandler(void) __attribute__((naked)); +void xPortSysTickHandler(void); +void vPortSVCHandler(void) __attribute__((naked)); + +/* + * Start first task is a separate function so it can be tested in isolation. + */ +static void prvPortStartFirstTask(void) __attribute__((naked)); + +/* + * Function to enable the VFP. + */ +static void vPortEnableVFP(void) __attribute__((naked)); + +/* + * Used to catch tasks that attempt to return from their implementing function. + */ +static void prvTaskExitError(void); + +/*-----------------------------------------------------------*/ + +/* Each task maintains its own interrupt status in the critical nesting + * variable. */ +static UBaseType_t uxCriticalNesting = 0xaaaaaaaa; + +/* + * The number of SysTick increments that make up one tick period. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) +static uint32_t ulTimerCountsForOneTick = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * The maximum number of tick periods that can be suppressed is limited by the + * 24 bit resolution of the SysTick timer. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) +static uint32_t xMaximumPossibleSuppressedTicks = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Compensate for the CPU cycles that pass while the SysTick is stopped (low + * power functionality only. + */ +#if ( configUSE_TICKLESS_IDLE == 1 ) +static uint32_t ulStoppedTimerCompensation = 0; +#endif /* configUSE_TICKLESS_IDLE */ + +/* + * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure + * FreeRTOS API functions are not called from interrupts that have been assigned + * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY. + */ +#if ( configASSERT_DEFINED == 1 ) +static uint8_t ucMaxSysCallPriority = 0; +static uint32_t ulMaxPRIGROUPValue = 0; +static const volatile uint8_t *const pcInterruptPriorityRegisters = (const volatile uint8_t *const) portNVIC_IP_REGISTERS_OFFSET_16; +#endif /* configASSERT_DEFINED */ + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack(StackType_t *pxTopOfStack, + TaskFunction_t pxCode, + void *pvParameters) +{ + /* Simulate the stack frame as it would be created by a context switch + * interrupt. */ + + /* Offset added to account for the way the MCU uses the stack on entry/exit + * of interrupts, and to ensure alignment. */ + pxTopOfStack--; + + *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ + pxTopOfStack--; + *pxTopOfStack = ((StackType_t) pxCode) & portSTART_ADDRESS_MASK; /* PC */ + pxTopOfStack--; + *pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS; /* LR */ + + /* Save code space by skipping register initialisation. */ + pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ + *pxTopOfStack = (StackType_t) pvParameters; /* R0 */ + + /* A save method is being used that requires each task to maintain its + * own exec return value. */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_EXC_RETURN; + + pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +static void prvTaskExitError(void) +{ + volatile uint32_t ulDummy = 0; + + /* A function that implements a task must not exit or attempt to return to + * its caller as there is nothing to return to. If a task wants to exit it + * should instead call vTaskDelete( NULL ). + * + * Artificially force an assert() to be triggered if configASSERT() is + * defined, then stop here so application writers can catch the error. */ + configASSERT(uxCriticalNesting == ~0UL); + portDISABLE_INTERRUPTS(); + + while (ulDummy == 0) + { + /* This file calls prvTaskExitError() after the scheduler has been + * started to remove a compiler warning about the function being defined + * but never called. ulDummy is used purely to quieten other warnings + * about code appearing after this function is called - making ulDummy + * volatile makes the compiler think the function could return and + * therefore not output an 'unreachable code' warning for code that appears + * after it. */ + } +} +/*-----------------------------------------------------------*/ + +void vPortSVCHandler(void) +{ + __asm volatile( + " ldr r3, pxCurrentTCBConst2 \n"/* Restore the context. */ + " ldr r1, [r3] \n"/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */ + " ldr r0, [r1] \n"/* The first item in pxCurrentTCB is the task top of stack. */ + " ldmia r0!, {r4-r11, r14} \n"/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */ + " msr psp, r0 \n"/* Restore the task stack pointer. */ + " isb \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" + " bx r14 \n" + " \n" + " .align 4 \n" + "pxCurrentTCBConst2: .word pxCurrentTCB \n" + ); +} +/*-----------------------------------------------------------*/ + +static void prvPortStartFirstTask(void) +{ + /* Start the first task. This also clears the bit that indicates the FPU is + * in use in case the FPU was used before the scheduler was started - which + * would otherwise result in the unnecessary leaving of space in the SVC stack + * for lazy saving of FPU registers. */ + __asm volatile( + " ldr r0, =0xE000ED08 \n"/* Use the NVIC offset register to locate the stack. */ + " ldr r0, [r0] \n" + " ldr r0, [r0] \n" + " msr msp, r0 \n"/* Set the msp back to the start of the stack. */ + " mov r0, #0 \n"/* Clear the bit that indicates the FPU is in use, see comment above. */ + " msr control, r0 \n" + " cpsie i \n"/* Globally enable interrupts. */ + " cpsie f \n" + " dsb \n" + " isb \n" + " svc 0 \n"/* System call to start first task. */ + " nop \n" + " .ltorg \n" + ); +} +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +BaseType_t xPortStartScheduler(void) +{ + /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. + * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ + configASSERT(configMAX_SYSCALL_INTERRUPT_PRIORITY); + +#if ( configASSERT_DEFINED == 1 ) + { + volatile uint32_t ulOriginalPriority; + volatile uint8_t *const pucFirstUserPriorityRegister = (volatile uint8_t *const)(portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER); + volatile uint8_t ucMaxPriorityValue; + + /* Determine the maximum priority from which ISR safe FreeRTOS API + * functions can be called. ISR safe functions are those that end in + * "FromISR". FreeRTOS maintains separate thread and ISR API functions to + * ensure interrupt entry is as fast and simple as possible. + * + * Save the interrupt priority value that is about to be clobbered. */ + ulOriginalPriority = *pucFirstUserPriorityRegister; + + /* Determine the number of priority bits available. First write to all + * possible bits. */ + *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; + + /* Read the value back to see how many bits stuck. */ + ucMaxPriorityValue = *pucFirstUserPriorityRegister; + + /* Use the same mask on the maximum system call priority. */ + ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; + + /* Calculate the maximum acceptable priority group value for the number + * of bits read back. */ + ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; + + while ((ucMaxPriorityValue & portTOP_BIT_OF_BYTE) == portTOP_BIT_OF_BYTE) + { + ulMaxPRIGROUPValue--; + ucMaxPriorityValue <<= (uint8_t) 0x01; + } + +#ifdef __NVIC_PRIO_BITS + { + /* Check the CMSIS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT((portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue) == __NVIC_PRIO_BITS); + } +#endif + +#ifdef configPRIO_BITS + { + /* Check the FreeRTOS configuration that defines the number of + * priority bits matches the number of priority bits actually queried + * from the hardware. */ + configASSERT((portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue) == configPRIO_BITS); + } +#endif + + /* Shift the priority group value back to its position within the AIRCR + * register. */ + ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; + ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; + + /* Restore the clobbered interrupt priority register to its original + * value. */ + *pucFirstUserPriorityRegister = ulOriginalPriority; + } +#endif /* conifgASSERT_DEFINED */ + + /* Make PendSV and SysTick the lowest priority interrupts. */ + portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI; + portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI; + + /* Start the timer that generates the tick ISR. Interrupts are disabled + * here already. */ + vPortSetupTimerInterrupt(); + + /* Initialise the critical nesting count ready for the first task. */ + uxCriticalNesting = 0; + + /* Ensure the VFP is enabled - it should be anyway. */ + vPortEnableVFP(); + + /* Lazy save always. */ + *(portFPCCR) |= portASPEN_AND_LSPEN_BITS; + + /* Start the first task. */ + prvPortStartFirstTask(); + + /* Should never get here as the tasks will now be executing! Call the task + * exit error function to prevent compiler warnings about a static function + * not being called in the case that the application writer overrides this + * functionality by defining configTASK_RETURN_ADDRESS. Call + * vTaskSwitchContext() so link time optimisation does not remove the + * symbol. */ + vTaskSwitchContext(); + prvTaskExitError(); + + /* Should not get here! */ + return 0; +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler(void) +{ + /* Not implemented in ports where there is nothing to return to. + * Artificially force an assert. */ + configASSERT(uxCriticalNesting == 1000UL); +} +/*-----------------------------------------------------------*/ + +void vPortEnterCritical(void) +{ + portDISABLE_INTERRUPTS(); + uxCriticalNesting++; + + /* This is not the interrupt safe version of the enter critical function so + * assert() if it is being called from an interrupt context. Only API + * functions that end in "FromISR" can be used in an interrupt. Only assert if + * the critical nesting count is 1 to protect against recursive calls if the + * assert function also uses a critical section. */ + if (uxCriticalNesting == 1) + { + configASSERT((portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK) == 0); + } +} +/*-----------------------------------------------------------*/ + +void vPortExitCritical(void) +{ + configASSERT(uxCriticalNesting); + uxCriticalNesting--; + + if (uxCriticalNesting == 0) + { + portENABLE_INTERRUPTS(); + } +} +/*-----------------------------------------------------------*/ + +void xPortPendSVHandler(void) +{ + /* This is a naked function. */ + + __asm volatile + ( + " mrs r0, psp \n" + " isb \n" + " \n" + " ldr r3, pxCurrentTCBConst \n"/* Get the location of the current TCB. */ + " ldr r2, [r3] \n" + " \n" + " tst r14, #0x10 \n"/* Is the task using the FPU context? If so, push high vfp registers. */ + " it eq \n" + " vstmdbeq r0!, {s16-s31} \n" + " \n" + " stmdb r0!, {r4-r11, r14} \n"/* Save the core registers. */ + " str r0, [r2] \n"/* Save the new top of stack into the first member of the TCB. */ + " \n" + " stmdb sp!, {r0, r3} \n" + " mov r0, %0 \n" + " cpsid i \n"/* Errata workaround. */ + " msr basepri, r0 \n" + " dsb \n" + " isb \n" + " cpsie i \n"/* Errata workaround. */ + " bl vTaskSwitchContext \n" + " mov r0, #0 \n" + " msr basepri, r0 \n" + " ldmia sp!, {r0, r3} \n" + " \n" + " ldr r1, [r3] \n"/* The first item in pxCurrentTCB is the task top of stack. */ + " ldr r0, [r1] \n" + " \n" + " ldmia r0!, {r4-r11, r14} \n"/* Pop the core registers. */ + " \n" + " tst r14, #0x10 \n"/* Is the task using the FPU context? If so, pop the high vfp registers too. */ + " it eq \n" + " vldmiaeq r0!, {s16-s31} \n" + " \n" + " msr psp, r0 \n" + " isb \n" + " \n" +#ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */ +#if WORKAROUND_PMU_CM001 == 1 + " push { r14 } \n" + " pop { pc } \n" +#endif +#endif + " \n" + " bx r14 \n" + " \n" + " .align 4 \n" + "pxCurrentTCBConst: .word pxCurrentTCB \n" + ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) + ); +} +/*-----------------------------------------------------------*/ + +void xPortSysTickHandler(void) +{ + /* The SysTick runs at the lowest interrupt priority, so when this interrupt + * executes all interrupts must be unmasked. There is therefore no need to + * save and then restore the interrupt mask value as its value is already + * known. */ + portDISABLE_INTERRUPTS(); + { + /* Increment the RTOS tick. */ + if (xTaskIncrementTick() != pdFALSE) + { + /* A context switch is required. Context switching is performed in + * the PendSV interrupt. Pend the PendSV interrupt. */ + portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; + } + } + portENABLE_INTERRUPTS(); +} +/*-----------------------------------------------------------*/ + +#if ( configUSE_TICKLESS_IDLE == 1 ) + +__attribute__((weak)) void vPortSuppressTicksAndSleep(TickType_t xExpectedIdleTime) +{ + uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements; + TickType_t xModifiableIdleTime; + + /* Make sure the SysTick reload value does not overflow the counter. */ + if (xExpectedIdleTime > xMaximumPossibleSuppressedTicks) + { + xExpectedIdleTime = xMaximumPossibleSuppressedTicks; + } + + /* Stop the SysTick momentarily. The time the SysTick is stopped for + * is accounted for as best it can be, but using the tickless mode will + * inevitably result in some tiny drift of the time maintained by the + * kernel with respect to calendar time. */ + portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT; + + /* Calculate the reload value required to wait xExpectedIdleTime + * tick periods. -1 is used because this code will execute part way + * through one of the tick periods. */ + ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + (ulTimerCountsForOneTick * (xExpectedIdleTime - 1UL)); + + if (ulReloadValue > ulStoppedTimerCompensation) + { + ulReloadValue -= ulStoppedTimerCompensation; + } + + /* Enter a critical section but don't use the taskENTER_CRITICAL() + * method as that will mask interrupts that should exit sleep mode. */ + __asm volatile("cpsid i" ::: "memory"); + __asm volatile("dsb"); + __asm volatile("isb"); + + /* If a context switch is pending or a task is waiting for the scheduler + * to be unsuspended then abandon the low power entry. */ + if (eTaskConfirmSleepModeStatus() == eAbortSleep) + { + /* Restart from whatever is left in the count register to complete + * this tick period. */ + portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Reset the reload register to the value required for normal tick + * periods. */ + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Re-enable interrupts - see comments above the cpsid instruction() + * above. */ + __asm volatile("cpsie i" ::: "memory"); + } + else + { + /* Set the new reload value. */ + portNVIC_SYSTICK_LOAD_REG = ulReloadValue; + + /* Clear the SysTick count flag and set the count value back to + * zero. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Restart SysTick. */ + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + + /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can + * set its parameter to 0 to indicate that its implementation contains + * its own wait for interrupt or wait for event instruction, and so wfi + * should not be executed again. However, the original expected idle + * time variable must remain unmodified, so a copy is taken. */ + xModifiableIdleTime = xExpectedIdleTime; + configPRE_SLEEP_PROCESSING(xModifiableIdleTime); + + if (xModifiableIdleTime > 0) + { + __asm volatile("dsb" ::: "memory"); + __asm volatile("wfi"); + __asm volatile("isb"); + } + + configPOST_SLEEP_PROCESSING(xExpectedIdleTime); + + /* Re-enable interrupts to allow the interrupt that brought the MCU + * out of sleep mode to execute immediately. see comments above + * __disable_interrupt() call above. */ + __asm volatile("cpsie i" ::: "memory"); + __asm volatile("dsb"); + __asm volatile("isb"); + + /* Disable interrupts again because the clock is about to be stopped + * and interrupts that execute while the clock is stopped will increase + * any slippage between the time maintained by the RTOS and calendar + * time. */ + __asm volatile("cpsid i" ::: "memory"); + __asm volatile("dsb"); + __asm volatile("isb"); + + /* Disable the SysTick clock without reading the + * portNVIC_SYSTICK_CTRL_REG register to ensure the + * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again, + * the time the SysTick is stopped for is accounted for as best it can + * be, but using the tickless mode will inevitably result in some tiny + * drift of the time maintained by the kernel with respect to calendar + * time*/ + portNVIC_SYSTICK_CTRL_REG = (portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT); + + /* Determine if the SysTick clock has already counted to zero and + * been set back to the current reload value (the reload back being + * correct for the entire expected idle time) or if the SysTick is yet + * to count to zero (in which case an interrupt other than the SysTick + * must have brought the system out of sleep mode). */ + if ((portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT) != 0) + { + uint32_t ulCalculatedLoadValue; + + /* The tick interrupt is already pending, and the SysTick count + * reloaded with ulReloadValue. Reset the + * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick + * period. */ + ulCalculatedLoadValue = (ulTimerCountsForOneTick - 1UL) - (ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG); + + /* Don't allow a tiny value, or values that have somehow + * underflowed because the post sleep hook did something + * that took too long. */ + if ((ulCalculatedLoadValue < ulStoppedTimerCompensation) || (ulCalculatedLoadValue > ulTimerCountsForOneTick)) + { + ulCalculatedLoadValue = (ulTimerCountsForOneTick - 1UL); + } + + portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue; + + /* As the pending tick will be processed as soon as this + * function exits, the tick value maintained by the tick is stepped + * forward by one less than the time spent waiting. */ + ulCompleteTickPeriods = xExpectedIdleTime - 1UL; + } + else + { + /* Something other than the tick interrupt ended the sleep. + * Work out how long the sleep lasted rounded to complete tick + * periods (not the ulReload value which accounted for part + * ticks). */ + ulCompletedSysTickDecrements = (xExpectedIdleTime * ulTimerCountsForOneTick) - portNVIC_SYSTICK_CURRENT_VALUE_REG; + + /* How many complete tick periods passed while the processor + * was waiting? */ + ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick; + + /* The reload value is set to whatever fraction of a single tick + * period remains. */ + portNVIC_SYSTICK_LOAD_REG = ((ulCompleteTickPeriods + 1UL) * ulTimerCountsForOneTick) - ulCompletedSysTickDecrements; + } + + /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG + * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard + * value. */ + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT; + vTaskStepTick(ulCompleteTickPeriods); + portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL; + + /* Exit with interrupts enabled. */ + __asm volatile("cpsie i" ::: "memory"); + } +} + +#endif /* #if configUSE_TICKLESS_IDLE */ +/*-----------------------------------------------------------*/ + +/* + * Setup the systick timer to generate the tick interrupts at the required + * frequency. + */ +__attribute__((weak)) void vPortSetupTimerInterrupt(void) +{ + /* Calculate the constants required to configure the tick interrupt. */ +#if ( configUSE_TICKLESS_IDLE == 1 ) + { + ulTimerCountsForOneTick = (configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ); + xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick; + ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / (configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ); + } +#endif /* configUSE_TICKLESS_IDLE */ + + /* Stop and clear the SysTick. */ + portNVIC_SYSTICK_CTRL_REG = 0UL; + portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; + + /* Configure SysTick to interrupt at the requested rate. */ + portNVIC_SYSTICK_LOAD_REG = (configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ) - 1UL; + portNVIC_SYSTICK_CTRL_REG = (portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT); +} +/*-----------------------------------------------------------*/ + +/* This is a naked function. */ +static void vPortEnableVFP(void) +{ + __asm volatile + ( + " ldr.w r0, =0xE000ED88 \n"/* The FPU enable bits are in the CPACR. */ + " ldr r1, [r0] \n" + " \n" + " orr r1, r1, #( 0xf << 20 ) \n"/* Enable CP10 and CP11 coprocessors, then save back. */ + " str r1, [r0] \n" + " bx r14 \n" + " .ltorg \n" + ); +} +/*-----------------------------------------------------------*/ + +#if ( configASSERT_DEFINED == 1 ) + +void vPortValidateInterruptPriority(void) +{ + uint32_t ulCurrentInterrupt; + uint8_t ucCurrentPriority; + + /* Obtain the number of the currently executing interrupt. */ + __asm volatile("mrs %0, ipsr" : "=r"(ulCurrentInterrupt)::"memory"); + + /* Is the interrupt number a user defined interrupt? */ + if (ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER) + { + /* Look up the interrupt's priority. */ + ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; + + /* The following assertion will fail if a service routine (ISR) for + * an interrupt that has been assigned a priority above + * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API + * function. ISR safe FreeRTOS API functions must *only* be called + * from interrupts that have been assigned a priority at or below + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Numerically low interrupt priority numbers represent logically high + * interrupt priorities, therefore the priority of the interrupt must + * be set to a value equal to or numerically *higher* than + * configMAX_SYSCALL_INTERRUPT_PRIORITY. + * + * Interrupts that use the FreeRTOS API must not be left at their + * default priority of zero as that is the highest possible priority, + * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY, + * and therefore also guaranteed to be invalid. + * + * FreeRTOS maintains separate thread and ISR API functions to ensure + * interrupt entry is as fast and simple as possible. + * + * The following links provide detailed information: + * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html + * https://www.FreeRTOS.org/FAQHelp.html */ + configASSERT(ucCurrentPriority >= ucMaxSysCallPriority); + } + + /* Priority grouping: The interrupt controller (NVIC) allows the bits + * that define each interrupt's priority to be split between bits that + * define the interrupt's pre-emption priority bits and bits that define + * the interrupt's sub-priority. For simplicity all bits must be defined + * to be pre-emption priority bits. The following assertion will fail if + * this is not the case (if some bits represent a sub-priority). + * + * If the application only uses CMSIS libraries for interrupt + * configuration then the correct setting can be achieved on all Cortex-M + * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the + * scheduler. Note however that some vendor specific peripheral libraries + * assume a non-zero priority group setting, in which cases using a value + * of zero will result in unpredictable behaviour. */ + configASSERT((portAIRCR_REG & portPRIORITY_GROUP_MASK) <= ulMaxPRIGROUPValue); +} + +#endif /* configASSERT_DEFINED */ diff --git a/MODULES/FreeRTOSPortable_GCC_CM7/modular.json b/MODULES/FreeRTOSPortable_GCC_CM7/modular.json new file mode 100644 index 0000000..33c2653 --- /dev/null +++ b/MODULES/FreeRTOSPortable_GCC_CM7/modular.json @@ -0,0 +1,17 @@ +{ + "dep": [ + { + "type": "local", + + "dir": "./MODULES/FreeRTOS" + } + ], + "cmake": { + "inc_dirs": [ + "Inc" + ], + "srcs": [ + "Src/**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/GpioPinInterface/Inc/GpioPinInterface.h b/MODULES/GpioPinInterface/Inc/GpioPinInterface.h new file mode 100644 index 0000000..b14c6a3 --- /dev/null +++ b/MODULES/GpioPinInterface/Inc/GpioPinInterface.h @@ -0,0 +1,19 @@ +// +// Created by CFIF on 8/24/22. +// + +#ifndef ABSTRACTGPIOPIN_GPIOPININTERFACE_H +#define ABSTRACTGPIOPIN_GPIOPININTERFACE_H + +#include "stdint.h" +#include "stdbool.h" + +typedef struct { + bool reverse; + uint8_t port; + uint32_t pin; +} tGpioPin; + +#define GpioPinEnable(PIN) GpioPinSet(PIN,true) +#define GpioPinDisable(PIN) GpioPinSet(PIN,false) +#endif //ABSTRACTGPIOPIN_GPIOPININTERFACE_H diff --git a/MODULES/GpioPinInterface/modular.json b/MODULES/GpioPinInterface/modular.json new file mode 100644 index 0000000..9bdd478 --- /dev/null +++ b/MODULES/GpioPinInterface/modular.json @@ -0,0 +1,7 @@ +{ + "cmake": { + "inc_dirs": [ + "Inc" + ] + } +} \ No newline at end of file diff --git a/MODULES/GpioPin_Flagchip_FC7240/Inc/GpioPin.h b/MODULES/GpioPin_Flagchip_FC7240/Inc/GpioPin.h new file mode 100644 index 0000000..4460466 --- /dev/null +++ b/MODULES/GpioPin_Flagchip_FC7240/Inc/GpioPin.h @@ -0,0 +1,39 @@ +// +// Created by cfif on 16.09.22. +// + +#ifndef HVAC_M7_GPIOPIN_H +#define HVAC_M7_GPIOPIN_H + +#include "GpioPinInterface.h" +#include CMSIS_device_header +#include "fc7xxx_driver_pcc.h" +#include "fc7xxx_driver_port.h" +#include "fc7xxx_driver_gpio.h" +#include "fc7xxx_driver_scg.h" + +#define GPIO_PIN_NOREVERSE false +#define GPIO_PIN_REVERSE true + +typedef enum +{ + GPIO_OPEN = 0, + GPIO_PUSH_PULL = 1 +} eType_PUSH_PULL_OPEN_DARIN; + +tGpioPin vInitGpioPinPull( + GPIO_InstanceType port, + uint32_t pinMask, + GPIO_PinDirectionType direction, + bool reverse, + GPIO_PinLevelType ePinLevel, + eType_PUSH_PULL_OPEN_DARIN bPullEn, + PORT_PullStatusType ePullSel +); + + +void GpioPinSet(tGpioPin *pin, bool value); +bool GpioPinGet(tGpioPin *pin); +void GpioPinToggle(tGpioPin *pin); + +#endif //HVAC_M7_GPIOPIN_H diff --git a/MODULES/GpioPin_Flagchip_FC7240/Src/GpioPin.c b/MODULES/GpioPin_Flagchip_FC7240/Src/GpioPin.c new file mode 100644 index 0000000..a020b31 --- /dev/null +++ b/MODULES/GpioPin_Flagchip_FC7240/Src/GpioPin.c @@ -0,0 +1,65 @@ +// +// Created by cfif on 16.09.22. +// +#include "GpioPin.h" + +tGpioPin vInitGpioPinPull( + GPIO_InstanceType port, + uint32_t pinMask, + GPIO_PinDirectionType direction, + bool reverse, + GPIO_PinLevelType ePinLevel, + eType_PUSH_PULL_OPEN_DARIN bPullEn, + PORT_PullStatusType ePullSel +) { + PORT_InitType tInitStruct = {0}; + GPIO_InitType tGpioInitStruct = {0}; + + tInitStruct.bPullEn = bPullEn; + tInitStruct.ePullSel = ePullSel; + tInitStruct.u32PortPins = pinMask; + tInitStruct.uPortPinMux.u32PortPinMode = PORT_GPIO_MODE; + PORT_InitPins((PORT_InstanceType)port, &tInitStruct); + + tGpioInitStruct.u32GpioPins = pinMask; + tGpioInitStruct.ePinDirection = direction; + tGpioInitStruct.ePinLevel = ePinLevel; + GPIO_InitPins(port, &tGpioInitStruct); + + tGpioPin pin = { + .port = port, + .pin = pinMask, + .reverse = reverse + }; + + return pin; +} + +void GpioPinSet(tGpioPin *pin, bool value) { + if (pin->reverse) { + value = !value; + } + + if (value) { + GPIO_WritePins(pin->port, pin->pin, GPIO_HIGH); + } else { + GPIO_WritePins(pin->port, pin->pin, GPIO_LOW); + } +} + +bool GpioPinGet(tGpioPin *pin) { + bool value; + if (GPIO_ReadPins(pin->port, pin->pin)) { + value = true; + } else { //if value == RESET; + value = false; + } + if (pin->reverse) { + value = !value; + } + return value; +} + +void GpioPinToggle(tGpioPin *pin) { + GPIO_Toggle(pin->port, pin->pin); +} \ No newline at end of file diff --git a/MODULES/GpioPin_Flagchip_FC7240/modular.json b/MODULES/GpioPin_Flagchip_FC7240/modular.json new file mode 100644 index 0000000..e5aa446 --- /dev/null +++ b/MODULES/GpioPin_Flagchip_FC7240/modular.json @@ -0,0 +1,17 @@ +{ + "dep": [ + { + "type": "local", + + "dir": "./MODULES/GpioPinInterface" + } + ], + "cmake": { + "inc_dirs": [ + "Inc" + ], + "srcs": [ + "Src/**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_ADC_TASKS/AdcFilter.c b/MODULES/HVAC_M7_ADC_TASKS/AdcFilter.c new file mode 100644 index 0000000..4c95c22 --- /dev/null +++ b/MODULES/HVAC_M7_ADC_TASKS/AdcFilter.c @@ -0,0 +1,87 @@ +#include "AdcFilter.h" +#include "stddef.h" + +bool ADC_Filter_Init(ADC_Filter* filter, uint8_t size) { + if (filter == NULL || size > MAX_ADC_FILTER_SIZE) { + return false; + } + + // Разрешаем size == 0 (фильтр отключён) + for (uint8_t i = 0; i < ADC_BUFFER_SIZE; i++) { + filter->buffer[i] = 0; + } + + filter->sum = 0; + filter->size = size; + filter->index = 0; + filter->count = 0; + + return true; +} + +void ADC_Filter_Reset(ADC_Filter* filter) { + if (filter == NULL) return; + + for (uint8_t i = 0; i < ADC_BUFFER_SIZE; i++) { + filter->buffer[i] = 0; + } + + filter->sum = 0; + filter->index = 0; + filter->count = 0; + // размер не меняем +} + +uint16_t ADC_Filter_Update(ADC_Filter* filter, uint16_t adc_value) { + if (filter == NULL) return 0; + + // Если фильтр отключён, возвращаем сырое значение + if (filter->size == 0) { + return adc_value; + } + + // Переходный период (буфер не заполнен) + if (filter->count < filter->size) { + filter->buffer[filter->index] = adc_value; + filter->sum += adc_value; + filter->count++; + filter->index = (filter->index + 1) % filter->size; + return (uint16_t)(filter->sum / filter->count); + } + + // Нормальный режим работы + uint16_t old_value = filter->buffer[filter->index]; + filter->buffer[filter->index] = adc_value; + filter->sum = filter->sum - old_value + adc_value; + filter->index = (filter->index + 1) % filter->size; + + // Округление при делении + return (uint16_t)((filter->sum + (filter->size >> 1)) / filter->size); +} + +uint16_t ADC_Filter_GetCurrent(const ADC_Filter* filter) { + if (filter == NULL || filter->count == 0 || filter->size == 0) { + return 0; + } + return (uint16_t)((filter->sum + (filter->count >> 1)) / filter->count); +} + +bool ADC_Filter_IsReady(const ADC_Filter* filter) { + return (filter != NULL && filter->size > 0 && filter->count == filter->size); +} + +uint16_t ADC_Filter_GetVariance(const ADC_Filter* filter) { + if (filter == NULL || filter->count == 0 || filter->size == 0) { + return 0; + } + + uint16_t mean = ADC_Filter_GetCurrent(filter); + uint32_t variance_sum = 0; + + for (uint8_t i = 0; i < filter->count; i++) { + int32_t diff = (int32_t)filter->buffer[i] - mean; + variance_sum += (diff * diff); + } + + return (uint16_t)(variance_sum / filter->count); +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_ADC_TASKS/AdcFilter.h b/MODULES/HVAC_M7_ADC_TASKS/AdcFilter.h new file mode 100644 index 0000000..cbff92f --- /dev/null +++ b/MODULES/HVAC_M7_ADC_TASKS/AdcFilter.h @@ -0,0 +1,34 @@ +#ifndef HVAC_M7_ADCFILTER_H +#define HVAC_M7_ADCFILTER_H + +#include "stdint.h" +#include "stdbool.h" + +// Максимальный размер фильтра (может быть 0 для отключения) +#ifndef MAX_ADC_FILTER_SIZE +#define MAX_ADC_FILTER_SIZE 32 +#endif + +// Если размер равен 0, используем буфер из 1 элемента (для избежания ошибок компиляции) +#if MAX_ADC_FILTER_SIZE == 0 +#define ADC_BUFFER_SIZE 1 +#else +#define ADC_BUFFER_SIZE MAX_ADC_FILTER_SIZE +#endif + +typedef struct { + uint16_t buffer[ADC_BUFFER_SIZE]; // кольцевой буфер + uint32_t sum; // сумма элементов + uint8_t size; // размер окна (0 – фильтр отключён) + uint8_t index; // текущий индекс + uint8_t count; // количество накопленных данных +} ADC_Filter; + +bool ADC_Filter_Init(ADC_Filter* filter, uint8_t size); +uint16_t ADC_Filter_Update(ADC_Filter* filter, uint16_t adc_value); +uint16_t ADC_Filter_GetCurrent(const ADC_Filter* filter); +bool ADC_Filter_IsReady(const ADC_Filter* filter); +uint16_t ADC_Filter_GetVariance(const ADC_Filter* filter); +void ADC_Filter_Reset(ADC_Filter* filter); + +#endif //HVAC_M7_ADCFILTER_H \ No newline at end of file diff --git a/MODULES/HVAC_M7_ADC_TASKS/AdcTasks.c b/MODULES/HVAC_M7_ADC_TASKS/AdcTasks.c new file mode 100644 index 0000000..8a03d0b --- /dev/null +++ b/MODULES/HVAC_M7_ADC_TASKS/AdcTasks.c @@ -0,0 +1,757 @@ +// +// Created by cfif on 15.12.2025. +// +#include "AdcTasks.h" +#include "CmsisRtosThreadUtils.h" +#include +#include "memory.h" +#include "ADC_Temp.h" +#include "ADC_Temp_Fast.h" + + +#define LOG_SIGN "ADC" +#define LOGGER env->logger + +void Adc_0_Init(tAdc0Task *env, + tAdcIO *adcIO, + tGpios *gpios, + tLoggerInterface *logger +) { + + env->adcIO = adcIO; + env->access = osMutexNew(NULL); + env->logger = logger; + env->gpios = gpios; + + env->queueRandom = osMessageQueueNew(10, 4, NULL); + env->queueCmdBusADCData = osMessageQueueNew(1, sizeof(CmdBusADCData), NULL); + + ADC_Filter_Init(&env->ADC0_Filter_data.Sensor_Ambient_Temp, MAX_ADC_FILTER_SIZE); + ADC_Filter_Init(&env->ADC0_Filter_data.IGN_ANS, MAX_ADC_FILTER_SIZE); + ADC_Filter_Init(&env->ADC0_Filter_data.Sensor_AC_Pressure, MAX_ADC_FILTER_SIZE); + ADC_Filter_Init(&env->ADC0_Filter_data.Sensor_Incar_Temp_FL, MAX_ADC_FILTER_SIZE); + ADC_Filter_Init(&env->ADC0_Filter_data.Sensor_Incar_Temp_RL, MAX_ADC_FILTER_SIZE); + ADC_Filter_Init(&env->ADC0_Filter_data.Sensor_Rear_Evap_Temp, MAX_ADC_FILTER_SIZE); + ADC_Filter_Init(&env->ADC0_Filter_data.Sensor_Evap_Temp, MAX_ADC_FILTER_SIZE); + ADC_Filter_Init(&env->ADC0_Filter_data.Sensor_Rear_Duct1, MAX_ADC_FILTER_SIZE); + ADC_Filter_Init(&env->ADC0_Filter_data.Sensor_Rear_Duct2, MAX_ADC_FILTER_SIZE); + ADC_Filter_Init(&env->ADC0_Filter_data.Sensor_Front_Duct1, MAX_ADC_FILTER_SIZE); + ADC_Filter_Init(&env->ADC0_Filter_data.Sensor_Front_Duct2, MAX_ADC_FILTER_SIZE); + ADC_Filter_Init(&env->ADC0_Filter_data.Sensor_Front_Duct3, MAX_ADC_FILTER_SIZE); + ADC_Filter_Init(&env->ADC0_Filter_data.Sensor_Front_Duct4, MAX_ADC_FILTER_SIZE); + ADC_Filter_Init(&env->ADC0_Filter_data.Sensor_Rear_Duct3, MAX_ADC_FILTER_SIZE); + ADC_Filter_Init(&env->ADC0_Filter_data.Sensor_Rear_Duct4, MAX_ADC_FILTER_SIZE); + ADC_Filter_Init(&env->ADC0_Filter_data.Sensor_Incar_Temp_FR, MAX_ADC_FILTER_SIZE); + ADC_Filter_Init(&env->ADC0_Filter_data.Sensor_Incar_Temp_RR, MAX_ADC_FILTER_SIZE); + ADC_Filter_Init(&env->ADC0_Filter_data.Sensor_Rear_Duct5, MAX_ADC_FILTER_SIZE); + ADC_Filter_Init(&env->ADC0_Filter_data.Sensor_Rear_Duct6, MAX_ADC_FILTER_SIZE); + ADC_Filter_Init(&env->ADC0_Filter_data.Reserve_Sensor_Duct_Temp_1, MAX_ADC_FILTER_SIZE); + ADC_Filter_Init(&env->ADC0_Filter_data.Sensor_Front_Duct5, MAX_ADC_FILTER_SIZE); + ADC_Filter_Init(&env->ADC0_Filter_data.Sensor_Front_Duct6, MAX_ADC_FILTER_SIZE); + ADC_Filter_Init(&env->ADC0_Filter_data.Pressure_DIAG, MAX_ADC_FILTER_SIZE); + ADC_Filter_Init(&env->ADC0_Filter_data.Reserve_Sensor_Duct_Temp_2, MAX_ADC_FILTER_SIZE); + ADC_Filter_Init(&env->ADC0_Filter_data.Sensor_PT_rHVAC_P, MAX_ADC_FILTER_SIZE); + ADC_Filter_Init(&env->ADC0_Filter_data.Sensor_A_T_reserve, MAX_ADC_FILTER_SIZE); + + + ADC_Filter_Init(&env->ADC0_Filter_data.BTS5120_2EKA_ShutoffValvePowerTXV1, MAX_ADC_FILTER_SIZE); + ADC_Filter_Init(&env->ADC0_Filter_data.BTS5180_2EKA_ShutOFFValveFront, MAX_ADC_FILTER_SIZE); + ADC_Filter_Init(&env->ADC0_Filter_data.BTS5180_2EKA_TwoWayValve, MAX_ADC_FILTER_SIZE); + ADC_Filter_Init(&env->ADC0_Filter_data.BTS5180_2EKA_FrontIncarMotor, MAX_ADC_FILTER_SIZE); + ADC_Filter_Init(&env->ADC0_Filter_data.BTS5180_2EKA_ChannelPTCPower1, MAX_ADC_FILTER_SIZE); + + ADC_Filter_Init(&env->ADC0_Filter_data.BTS5120_2EKA_ShutoffValvePowerTXV2, MAX_ADC_FILTER_SIZE); + ADC_Filter_Init(&env->ADC0_Filter_data.BTS5180_2EKA_ShutOFFValveRear, MAX_ADC_FILTER_SIZE); + ADC_Filter_Init(&env->ADC0_Filter_data.BTS5180_2EKA_ReservePowerSupply, MAX_ADC_FILTER_SIZE); + ADC_Filter_Init(&env->ADC0_Filter_data.BTS5180_2EKA_RearIncarMotor, MAX_ADC_FILTER_SIZE); + ADC_Filter_Init(&env->ADC0_Filter_data.BTS5180_2EKA_ChannelPTCPower2, MAX_ADC_FILTER_SIZE); + + + InitThreadAtrStatic(&env->thread.attr, "Adc0", env->thread.controlBlock, env->thread.stack, + osPriorityNormal); +} + +void BTS5180_120(tAdc0Task *env, char *desc, uint16_t adc_value) { + float kILIS = 550.0f; + + float ERROR_THRESHOLD_HIGH_V = 4.9f; + float ERROR_THRESHOLD_LOW_V = 0.1f; + uint16_t ERROR_THRESHOLD_HIGH_CODE = (uint16_t) (ERROR_THRESHOLD_HIGH_V * 4095.0f / 5.0f); +// uint16_t ERROR_THRESHOLD_LOW_CODE = (uint16_t) (ERROR_THRESHOLD_LOW_V * 4095.0f / 5.0f); + +// if (adc_value >= ERROR_THRESHOLD_HIGH_CODE) { +// LoggerFormatInfo(LOGGER, LOG_SIGN, "%s: Error !!! (adc = %d)", desc, adc_value) +// } else { + // Преобразование в напряжение + float U = (float) adc_value * 5.0f / 4095.0f; + float I = U / 1200; // Ток диагностики R = 1200 + float Iout = I * kILIS; // Ток устройства + LoggerFormatInfo(LOGGER, LOG_SIGN, + "%s: U = %f I = %f Iout = %f", + desc, U, I, Iout) +// } + +} + +void VN7008AJ(tAdc0Task *env, char *desc, uint16_t adc_value) { + + float RSENSE = 2490.0f; // Сопротивление датчика, Ом (На схеме) + float K_TYPICAL = 5890.0f; // Типичный коэффициент из даташита на микросхему + + float ERROR_THRESHOLD_HIGH_V = 4.9f; + float ERROR_THRESHOLD_LOW_V = 0.1f; + uint16_t ERROR_THRESHOLD_HIGH_CODE = (uint16_t) (ERROR_THRESHOLD_HIGH_V * 4095.0f / 5.0f); +// uint16_t ERROR_THRESHOLD_LOW_CODE = (uint16_t) (ERROR_THRESHOLD_LOW_V * 4095.0f / 5.0f); + + // 1. Проверка на ошибку +// if (adc_value >= ERROR_THRESHOLD_HIGH_CODE) { +// LoggerFormatInfo(LOGGER, LOG_SIGN, "%s: Error !!! (adc = %d)", desc, adc_value) +// } else { + + // 2. Преобразование в напряжение + float vsense = (float) adc_value * 5.0f / 4095.0f; + + // 3. Вычисление тока + float Isense = vsense / RSENSE; + float Iout = Isense * K_TYPICAL; + + LoggerFormatInfo(LOGGER, LOG_SIGN, + "%s: U = %f I = %f Iout = %f", + desc, vsense, Isense, Iout) +// } + +} + +/** + * Расчет сопротивления NTC для схемы с делителем напряжения + * + * Схема: VCC --- R_series --- NTC --- GND + * АЦП подключен к точке соединения R_series и NTC + * + * @param adc_value - значение АЦП (0..adc_max) + * @param R_series - сопротивление балластного резистора (Ом) + * @param Vcc_mv - напряжение питания делителя (мВ) + * @param Vref_mv - опорное напряжение АЦП (мВ) + * @param adc_max - максимальное значение АЦП (4095 для 12 бит) + * @return - сопротивление NTC (Ом) + */ +float calculate_ntc_resistance(uint16_t adc_value, + float R_series, + float Vcc_mv, + float Vref_mv, + uint16_t adc_max) { + // Защита от деления на ноль + if (adc_value == 0) { + return 0; // Rntc = бесконечность (обрыв) - NTC не подключен + } + + if (adc_value >= adc_max) { + return 0.0f; // Rntc = 0 (короткое замыкание) + } + + // Напряжение на NTC, измеренное АЦП (используем Vref АЦП) + float V_ntc = (float) adc_value / adc_max * Vref_mv; + + // Проверка, что V_ntc не превышает Vcc + if (V_ntc > Vcc_mv) { + V_ntc = Vcc_mv; // Ограничиваем физически возможным значением + } + + // Напряжение на балластном резисторе + float V_r1 = Vcc_mv - V_ntc; + + // Защита от отрицательного напряжения + if (V_r1 <= 0.0f) { + return 0.0f; // Короткое замыкание + } + + // Закон Ома: Rntc = R_series * (V_ntc / V_r1) + float Rntc = R_series * (V_ntc / V_r1); + + // Ограничиваем разумными пределами (1 Ом ... 10 МОм) + if (Rntc < 1.0f) Rntc = 1.0f; + if (Rntc > 10000000.0f) Rntc = 10000000.0f; + + return Rntc; +} + + + +void ANALOG_SENSOR(tAdc0Task *env, char *desc, uint16_t adc_value, eNtcTable NtcTable, float R) { + float ERROR_THRESHOLD_HIGH_V = 4.9f; + float ERROR_THRESHOLD_LOW_V = 0.1f; + uint16_t ERROR_THRESHOLD_HIGH_CODE = (uint16_t) (ERROR_THRESHOLD_HIGH_V * 4095.0f / 4.96f); + uint16_t ERROR_THRESHOLD_LOW_CODE = (uint16_t) (ERROR_THRESHOLD_LOW_V * 4095.0f / 4.96f); + + // 1. Проверка на ошибку + if (adc_value >= ERROR_THRESHOLD_HIGH_CODE || adc_value <= ERROR_THRESHOLD_LOW_CODE) { + LoggerFormatInfo(LOGGER, LOG_SIGN, "%s: Error !!! (adc = %d)", desc, adc_value) + } else { + // Преобразование в напряжение + float U = (float) adc_value * 5.0f / 4095.0f; + + float temp = 0; + float Rntc = 0; + + switch (NtcTable) { + + case TABLE_NONE: + LoggerFormatInfo(LOGGER, LOG_SIGN, "%s: U = %f (adc = %d)", desc, U, adc_value) + return; + + case TABLE_DUCT: + if (R == 3000) { + temp = get_temperature_by_adc(temperature_table_duct_KST45_table_3000, 1024, adc_value); +// temp = lookup_table_get_temp(temperature_table_duct_KST45_table_3000, adc_value); + Rntc = calculate_ntc_resistance(adc_value, 3000, 4.96f, 5.0f, 4095); + } + if (R == 20000) { + temp = get_temperature_by_adc(temperature_table_duct_KST45_table_20000, 1024, adc_value); +// temp = lookup_table_get_temp(temperature_table_duct_KST45_table_20000, adc_value); + Rntc = calculate_ntc_resistance(adc_value, 20000, 4.96f, 5.0f, 4095); + } + + break; + case TABLE_INCAR: + temp = get_temperature_by_adc(incar_lookup_table, 1024, adc_value); +// temp = lookup_table_get_temp(incar_lookup_table, adc_value); + Rntc = calculate_ntc_resistance(adc_value, 20000, 4.96f, 5.0f, 4095); + break; + case TABLE_AMBIENT: + temp = get_temperature_by_adc(ambient_lookup_table, 1024, adc_value); +// temp = lookup_table_get_temp(ambient_lookup_table, adc_value); + Rntc = calculate_ntc_resistance(adc_value, 20000, 4.96f, 5.0f, 4095); + break; + + } + + + + LoggerFormatInfo(LOGGER, LOG_SIGN, "%s: U = %f (adc = %d) Temp = %f Rntc = %f", desc, U, adc_value, temp / 10, Rntc) + } + +} + + + +static _Noreturn void Adc0_Thread(tAdc0Task *env) { + + uint32_t ADC_Pointer_Data; + + for (;;) { + + env->ADC_ChannelCount = env->adcIO->get(env->adcIO->env, &ADC_Pointer_Data, 5000); + + uint32_t *pData = (uint32_t *) ADC_Pointer_Data; + + uint32_t count = osMessageQueueGetSpace(env->queueRandom); + + if (count) { + + uint32_t seed = 0; + + for (uint8_t i = 0; i < 28; ++i) { + seed = seed | ((pData[i] & 1) << i); + } + + for (uint8_t i = 0; i < 4; ++i) { + seed = seed | (((pData[i] >> 1) & 1) << (i + 28)); + } + + osStatus_t status = osMessageQueuePut(env->queueRandom, &seed, 0, 0U); + } + + +// if (osMutexAcquire(env->modelTaskAccess, 5000) == osOK) { + + tADC0_data *ADC0_data = (tADC0_data *) ADC_Pointer_Data; + + + env->cmdBusADCData.Sensor_Ambient_Temp = ADC_Filter_Update(&env->ADC0_Filter_data.Sensor_Ambient_Temp,ADC0_data->Sensor_Ambient_Temp); + env->cmdBusADCData.IGN_ANS = ADC_Filter_Update(&env->ADC0_Filter_data.IGN_ANS, ADC0_data->IGN_ANS); + env->cmdBusADCData.Sensor_AC_Pressure = ADC_Filter_Update(&env->ADC0_Filter_data.Sensor_AC_Pressure,ADC0_data->Sensor_AC_Pressure); + env->cmdBusADCData.Sensor_Incar_Temp_FL = ADC_Filter_Update(&env->ADC0_Filter_data.Sensor_Incar_Temp_FL,ADC0_data->Sensor_Incar_Temp_FL); + env->cmdBusADCData.Sensor_Incar_Temp_RL = ADC_Filter_Update(&env->ADC0_Filter_data.Sensor_Incar_Temp_RL,ADC0_data->Sensor_Incar_Temp_RL); + env->cmdBusADCData.Sensor_Rear_Evap_Temp = ADC_Filter_Update(&env->ADC0_Filter_data.Sensor_Rear_Evap_Temp,ADC0_data->Sensor_Rear_Evap_Temp); + + env->cmdBusADCData.Sensor_Evap_Temp = ADC_Filter_Update(&env->ADC0_Filter_data.Sensor_Evap_Temp,ADC0_data->Sensor_Evap_Temp); + + env->cmdBusADCData.Sensor_Rear_Duct1 = ADC_Filter_Update(&env->ADC0_Filter_data.Sensor_Rear_Duct1,ADC0_data->Sensor_Rear_Duct1); + env->cmdBusADCData.Sensor_Rear_Duct2 = ADC_Filter_Update(&env->ADC0_Filter_data.Sensor_Rear_Duct2,ADC0_data->Sensor_Rear_Duct2); + env->cmdBusADCData.Sensor_Front_Duct1 = ADC_Filter_Update(&env->ADC0_Filter_data.Sensor_Front_Duct1,ADC0_data->Sensor_Front_Duct1); + env->cmdBusADCData.Sensor_Front_Duct2 = ADC_Filter_Update(&env->ADC0_Filter_data.Sensor_Front_Duct2,ADC0_data->Sensor_Front_Duct2); + env->cmdBusADCData.Sensor_Front_Duct3 = ADC_Filter_Update(&env->ADC0_Filter_data.Sensor_Front_Duct3,ADC0_data->Sensor_Front_Duct3); + env->cmdBusADCData.Sensor_Front_Duct4 = ADC_Filter_Update(&env->ADC0_Filter_data.Sensor_Front_Duct4,ADC0_data->Sensor_Front_Duct4); + + env->cmdBusADCData.Sensor_Rear_Duct3 = ADC_Filter_Update(&env->ADC0_Filter_data.Sensor_Rear_Duct3,ADC0_data->Sensor_Rear_Duct3); + + env->cmdBusADCData.Sensor_Rear_Duct4 = ADC_Filter_Update(&env->ADC0_Filter_data.Sensor_Rear_Duct4,ADC0_data->Sensor_Rear_Duct4); + env->cmdBusADCData.Sensor_Incar_Temp_FR = ADC_Filter_Update(&env->ADC0_Filter_data.Sensor_Incar_Temp_FR,ADC0_data->Sensor_Incar_Temp_FR); + env->cmdBusADCData.Sensor_Incar_Temp_RR = ADC_Filter_Update(&env->ADC0_Filter_data.Sensor_Incar_Temp_RR,ADC0_data->Sensor_Incar_Temp_RR); + env->cmdBusADCData.Sensor_Rear_Duct5 = ADC_Filter_Update(&env->ADC0_Filter_data.Sensor_Rear_Duct5,ADC0_data->Sensor_Rear_Duct5); + env->cmdBusADCData.Sensor_Rear_Duct6 = ADC_Filter_Update(&env->ADC0_Filter_data.Sensor_Rear_Duct6,ADC0_data->Sensor_Rear_Duct6); + env->cmdBusADCData.Reserve_Sensor_Duct_Temp_1 = ADC_Filter_Update(&env->ADC0_Filter_data.Reserve_Sensor_Duct_Temp_1, ADC0_data->Reserve_Sensor_Duct_Temp_1); + env->cmdBusADCData.Sensor_Front_Duct5 = ADC_Filter_Update(&env->ADC0_Filter_data.Sensor_Front_Duct5,ADC0_data->Sensor_Front_Duct5); + env->cmdBusADCData.Sensor_Front_Duct6 = ADC_Filter_Update(&env->ADC0_Filter_data.Sensor_Front_Duct6,ADC0_data->Sensor_Front_Duct6); + env->cmdBusADCData.Pressure_DIAG = ADC_Filter_Update(&env->ADC0_Filter_data.Pressure_DIAG,ADC0_data->Pressure_DIAG); + env->cmdBusADCData.Reserve_Sensor_Duct_Temp_2 = ADC_Filter_Update(&env->ADC0_Filter_data.Reserve_Sensor_Duct_Temp_2, ADC0_data->Reserve_Sensor_Duct_Temp_2); + + + + + + + + + + + + // rtDW.ADC_Data_Model.Sensor_PT_rHVAC_P = ADC_Filter_Update(&env->ADC0_Filter_data.Sensor_PT_rHVAC_P, ADC0_data->Sensor_PT_rHVAC_P); +// rtDW.ADC_Data_Model.Sensor_A_T_reserve = ADC_Filter_Update(&env->ADC0_Filter_data.Sensor_A_T_reserve, ADC0_data->Sensor_A_T_reserve); + + + +/* + rtDW.ADC_Data_Model.Sensor_Front_Duct1 = 3071; + rtDW.ADC_Data_Model.Sensor_Front_Duct2 = 3031; + rtDW.ADC_Data_Model.Sensor_Front_Duct3 = 2993; + rtDW.ADC_Data_Model.Sensor_Front_Duct4 = 2952; + rtDW.ADC_Data_Model.Sensor_Front_Duct5 = 2912; + rtDW.ADC_Data_Model.Sensor_Front_Duct6 = 2871; + + rtDW.ADC_Data_Model.Sensor_Rear_Duct1 = 2829; + rtDW.ADC_Data_Model.Sensor_Rear_Duct2 = 2787; + rtDW.ADC_Data_Model.Sensor_Rear_Duct3 = 2744; + rtDW.ADC_Data_Model.Sensor_Rear_Duct4 = 2701; +*/ + + +/* + rtDW.ADC_Data_Model.Sensor_Ambient_Temp = pData[0]; + rtDW.ADC_Data_Model.IGN_ANS = pData[1]; + rtDW.ADC_Data_Model.Sensor_AC_Pressure = pData[2]; + rtDW.ADC_Data_Model.Sensor_Incar_Temp_FL = pData[3]; + rtDW.ADC_Data_Model.Sensor_Incar_Temp_RL = pData[4]; + rtDW.ADC_Data_Model.Sensor_Rear_Evap_Temp = pData[5]; + rtDW.ADC_Data_Model.Sensor_Evap_Temp = pData[6]; + rtDW.ADC_Data_Model.Sensor_Rear_Duct1 = pData[7]; + rtDW.ADC_Data_Model.Sensor_Rear_Duct2 = pData[8]; + rtDW.ADC_Data_Model.Sensor_Front_Duct1 = pData[9]; + rtDW.ADC_Data_Model.Sensor_Front_Duct2 = pData[10]; + rtDW.ADC_Data_Model.Sensor_Front_Duct3 = pData[11]; + rtDW.ADC_Data_Model.Sensor_Front_Duct4 = pData[12]; + rtDW.ADC_Data_Model.Sensor_Rear_Duct3 = pData[13]; + rtDW.ADC_Data_Model.Sensor_Rear_Duct4 = pData[14]; + rtDW.ADC_Data_Model.Sensor_Incar_Temp_FR = pData[15]; + rtDW.ADC_Data_Model.Sensor_Incar_Temp_RR = pData[16]; + rtDW.ADC_Data_Model.Sensor_Rear_Duct5 = pData[17]; + rtDW.ADC_Data_Model.Sensor_Rear_Duct6 = pData[18]; + rtDW.ADC_Data_Model.Reserve_Sensor_Duct_Temp_1 = pData[19]; + rtDW.ADC_Data_Model.Sensor_Front_Duct5 = pData[20]; + rtDW.ADC_Data_Model.Sensor_Front_Duct6 = pData[21]; + + rtDW.ADC_Data_Model.Pressure_DIAG = pData[23]; + rtDW.ADC_Data_Model.Reserve_Sensor_Duct_Temp_2 = pData[28]; +*/ +// rtDW.ADC_Data_Model.Sensor_PT_rHVAC_P = pData[29]; +// rtDW.ADC_Data_Model.Sensor_A_T_reserve = pData[30]; + + if (env->ADC0_BTS5120_2EKA_Channel == 0) { + env->ADC0_BTS5120_2EKA_Channel = 1; + + GpioPinSet(&env->gpios->power.BTS5120_2EKA_ShutoffValvePowerTXV.ShutSelTXV_SEL_Diag, true); + GpioPinSet(&env->gpios->power.BTS5180_2EKA_ShutOFFValveFrontRear.ShutSel_SEL_Diag, true); + GpioPinSet(&env->gpios->power.BTS5180_2EKA_TwoWayValveAndReservePowerSupply.TwoWayValve_SEL_Diag, true); + GpioPinSet(&env->gpios->power.BTS5180_2EKA_FrontRearIncarMotor.Incar_SEL_Diag, true); + GpioPinSet(&env->gpios->power.BTS5180_2EKA_2xChannelPTCPower.PtcRelayDriver_SEL_Diag, true); + + env->cmdBusADCData.BTS5120_2EKA_ShutoffValvePowerTXV1 = ADC_Filter_Update(&env->ADC0_Filter_data.BTS5120_2EKA_ShutoffValvePowerTXV1,ADC0_data->BTS5120_2EKA_ShutoffValvePowerTXV1_BTS5120_2EKA_ShutoffValvePowerTXV2); + env->cmdBusADCData.BTS5180_2EKA_ShutOFFValveFront = ADC_Filter_Update(&env->ADC0_Filter_data.BTS5180_2EKA_ShutOFFValveFront,ADC0_data->BTS5180_2EKA_ShutOFFValveFront_BTS5180_2EKA_ShutOFFValveRear); + env->cmdBusADCData.BTS5180_2EKA_TwoWayValve = ADC_Filter_Update(&env->ADC0_Filter_data.BTS5180_2EKA_TwoWayValve, ADC0_data->BTS5180_2EKA_TwoWayValve_BTS5180_2EKA_ReservePowerSupply); + env->cmdBusADCData.BTS5180_2EKA_FrontIncarMotor = ADC_Filter_Update(&env->ADC0_Filter_data.BTS5180_2EKA_FrontIncarMotor, ADC0_data->BTS5180_2EKA_FrontIncarMotor_BTS5180_2EKA_RearIncarMotor); + env->cmdBusADCData.BTS5180_2EKA_ChannelPTCPower1 = ADC_Filter_Update(&env->ADC0_Filter_data.BTS5180_2EKA_ChannelPTCPower1, ADC0_data->BTS5180_2EKA_ChannelPTCPower1_BTS5180_2EKA_ChannelPTCPower2); +/* + rtDW.ADC_Data_Model.BTS5120_2EKA_ShutoffValvePowerTXV1 = pData[22]; // + rtDW.ADC_Data_Model.BTS5180_2EKA_ShutOFFValveFront = pData[24]; // + rtDW.ADC_Data_Model.BTS5180_2EKA_TwoWayValve = pData[25]; // + rtDW.ADC_Data_Model.BTS5180_2EKA_FrontIncarMotor = pData[26]; // + rtDW.ADC_Data_Model.BTS5180_2EKA_ChannelPTCPower1 = pData[27]; // +*/ + } else { + env->ADC0_BTS5120_2EKA_Channel = 0; + + GpioPinSet(&env->gpios->power.BTS5120_2EKA_ShutoffValvePowerTXV.ShutSelTXV_SEL_Diag, false); + GpioPinSet(&env->gpios->power.BTS5180_2EKA_ShutOFFValveFrontRear.ShutSel_SEL_Diag, false); + GpioPinSet(&env->gpios->power.BTS5180_2EKA_TwoWayValveAndReservePowerSupply.TwoWayValve_SEL_Diag,false); + GpioPinSet(&env->gpios->power.BTS5180_2EKA_FrontRearIncarMotor.Incar_SEL_Diag, false); + GpioPinSet(&env->gpios->power.BTS5180_2EKA_2xChannelPTCPower.PtcRelayDriver_SEL_Diag, false); + + env->cmdBusADCData.BTS5120_2EKA_ShutoffValvePowerTXV2 = ADC_Filter_Update(&env->ADC0_Filter_data.BTS5120_2EKA_ShutoffValvePowerTXV2,ADC0_data->BTS5120_2EKA_ShutoffValvePowerTXV1_BTS5120_2EKA_ShutoffValvePowerTXV2); + env->cmdBusADCData.BTS5180_2EKA_ShutOFFValveRear = ADC_Filter_Update(&env->ADC0_Filter_data.BTS5180_2EKA_ShutOFFValveRear, ADC0_data->BTS5180_2EKA_ShutOFFValveFront_BTS5180_2EKA_ShutOFFValveRear); + env->cmdBusADCData.BTS5180_2EKA_ReservePowerSupply = ADC_Filter_Update(&env->ADC0_Filter_data.BTS5180_2EKA_ReservePowerSupply,ADC0_data->BTS5180_2EKA_TwoWayValve_BTS5180_2EKA_ReservePowerSupply); + env->cmdBusADCData.BTS5180_2EKA_RearIncarMotor = ADC_Filter_Update(&env->ADC0_Filter_data.BTS5180_2EKA_RearIncarMotor, ADC0_data->BTS5180_2EKA_FrontIncarMotor_BTS5180_2EKA_RearIncarMotor); + env->cmdBusADCData.BTS5180_2EKA_ChannelPTCPower2 = ADC_Filter_Update(&env->ADC0_Filter_data.BTS5180_2EKA_ChannelPTCPower2, ADC0_data->BTS5180_2EKA_ChannelPTCPower1_BTS5180_2EKA_ChannelPTCPower2); + +/* + rtDW.ADC_Data_Model.BTS5120_2EKA_ShutoffValvePowerTXV2 = pData[22]; // + rtDW.ADC_Data_Model.BTS5180_2EKA_ShutOFFValveRear = pData[24]; // + rtDW.ADC_Data_Model.BTS5180_2EKA_ReservePowerSupply = pData[25]; // + rtDW.ADC_Data_Model.BTS5180_2EKA_RearIncarMotor = pData[26]; // + rtDW.ADC_Data_Model.BTS5180_2EKA_ChannelPTCPower2 = pData[27]; // +*/ + } + + +// float IGN_ANS = (float) rtDW.ADC_Data_Model.IGN_ANS * 27.75f / 4095.0f; +// LoggerFormatInfo(LOGGER, LOG_SIGN, "IGN = %f", IGN_ANS); + + + +//////////////////////////////////////----DEBUG----//////////////////////////////////////////////////////////////////// + + + + + + + +/* + + LoggerErrorStatic(LOGGER, LOG_SIGN, "======================================================================"); + + BTS5180_120(env, "BTS5120_2EKA_ShutoffValvePowerTXV1", + rtDW.ADC_Data_Model.BTS5120_2EKA_ShutoffValvePowerTXV1); + BTS5180_120(env, "BTS5120_2EKA_ShutoffValvePowerTXV2", + rtDW.ADC_Data_Model.BTS5120_2EKA_ShutoffValvePowerTXV2); + + BTS5180_120(env, "BTS5180_2EKA_ShutOFFValveFront", rtDW.ADC_Data_Model.BTS5180_2EKA_ShutOFFValveFront); + BTS5180_120(env, "BTS5180_2EKA_ShutOFFValveRear", rtDW.ADC_Data_Model.BTS5180_2EKA_ShutOFFValveRear); + + BTS5180_120(env, "BTS5180_2EKA_TwoWayValve", rtDW.ADC_Data_Model.BTS5180_2EKA_TwoWayValve); + BTS5180_120(env, "BTS5180_2EKA_ReservePowerSupply", + rtDW.ADC_Data_Model.BTS5180_2EKA_ReservePowerSupply); + + BTS5180_120(env, "BTS5180_2EKA_FrontIncarMotor", rtDW.ADC_Data_Model.BTS5180_2EKA_FrontIncarMotor); + BTS5180_120(env, "BTS5180_2EKA_RearIncarMotor", rtDW.ADC_Data_Model.BTS5180_2EKA_RearIncarMotor); + + BTS5180_120(env, "BTS5180_2EKA_ChannelPTCPower1", rtDW.ADC_Data_Model.BTS5180_2EKA_ChannelPTCPower1); + BTS5180_120(env, "BTS5180_2EKA_ChannelPTCPower2", rtDW.ADC_Data_Model.BTS5180_2EKA_ChannelPTCPower2); + + + LoggerErrorStatic(LOGGER, LOG_SIGN, "======================================================================"); + + ANALOG_SENSOR(env, "Sensor_Ambient_Temp", rtDW.ADC_Data_Model.Sensor_Ambient_Temp, TABLE_AMBIENT, 20000); + ANALOG_SENSOR(env, "Sensor_AC_Pressure", rtDW.ADC_Data_Model.Sensor_AC_Pressure, TABLE_NONE, 0); + + LoggerErrorStatic(LOGGER, LOG_SIGN, "======================================================================"); + + ANALOG_SENSOR(env, "Sensor_Incar_Temp_FL", rtDW.ADC_Data_Model.Sensor_Incar_Temp_FL, TABLE_INCAR, 20000); + ANALOG_SENSOR(env, "Sensor_Incar_Temp_RL", rtDW.ADC_Data_Model.Sensor_Incar_Temp_RL, TABLE_INCAR, 20000); + ANALOG_SENSOR(env, "Sensor_Incar_Temp_FR", rtDW.ADC_Data_Model.Sensor_Incar_Temp_FR, TABLE_INCAR, 20000); + ANALOG_SENSOR(env, "Sensor_Incar_Temp_RR", rtDW.ADC_Data_Model.Sensor_Incar_Temp_RR, TABLE_INCAR, 20000); + + LoggerErrorStatic(LOGGER, LOG_SIGN, "======================================================================"); + + ANALOG_SENSOR(env, "Sensor_Rear_Evap_Temp", rtDW.ADC_Data_Model.Sensor_Rear_Evap_Temp, TABLE_DUCT, 20000); + ANALOG_SENSOR(env, "Sensor_Evap_Temp", rtDW.ADC_Data_Model.Sensor_Evap_Temp, TABLE_DUCT, 20000); + + LoggerErrorStatic(LOGGER, LOG_SIGN, "======================================================================"); + ANALOG_SENSOR(env, "Sensor_Rear_Duct1 (dbg_Sen_Duct_RL_Fb)", rtDW.ADC_Data_Model.Sensor_Rear_Duct1, TABLE_DUCT, 3000); + ANALOG_SENSOR(env, "Sensor_Rear_Duct2 (dbg_Sen_Duct_RR_Fb)", rtDW.ADC_Data_Model.Sensor_Rear_Duct2, TABLE_DUCT, 3000); + ANALOG_SENSOR(env, "Sensor_Rear_Duct3 (dbg_Sen_Duct_RL_Side_Fb)", rtDW.ADC_Data_Model.Sensor_Rear_Duct3, TABLE_DUCT, 3000); + ANALOG_SENSOR(env, "Sensor_Rear_Duct4 (dbg_Sen_Duct_RR_Side_Fb)", rtDW.ADC_Data_Model.Sensor_Rear_Duct4, TABLE_DUCT, 3000); + // ANALOG_SENSOR(env, "Sensor_Rear_Duct5", rtDW.ADC_Data_Model.Sensor_Rear_Duct5, TABLE_DUCT, 3000); + // ANALOG_SENSOR(env, "Sensor_Rear_Duct6", rtDW.ADC_Data_Model.Sensor_Rear_Duct6, TABLE_DUCT, 3000); + LoggerErrorStatic(LOGGER, LOG_SIGN, "======================================================================"); + ANALOG_SENSOR(env, "Sensor_Front_Duct1 (dbg_Sen_Duct_FL_Upper_Fb)", rtDW.ADC_Data_Model.Sensor_Front_Duct1, TABLE_DUCT, 3000); + ANALOG_SENSOR(env, "Sensor_Front_Duct2 (dbg_Sen_Duct_FR_Upper_Fb)", rtDW.ADC_Data_Model.Sensor_Front_Duct2, TABLE_DUCT, 3000); + ANALOG_SENSOR(env, "Sensor_Front_Duct3 (dbg_Sen_Duct_FL_Lower_Fb)", rtDW.ADC_Data_Model.Sensor_Front_Duct3, TABLE_DUCT, 3000); + ANALOG_SENSOR(env, "Sensor_Front_Duct4 (dbg_Sen_Duct_FR_Lower_Fb)", rtDW.ADC_Data_Model.Sensor_Front_Duct4, TABLE_DUCT, 3000); + ANALOG_SENSOR(env, "Sensor_Front_Duct5 (dbg_Sen_Duct_FL_Side_Fb)", rtDW.ADC_Data_Model.Sensor_Front_Duct5, TABLE_DUCT, 3000); + ANALOG_SENSOR(env, "Sensor_Front_Duct6 (dbg_Sen_Duct_FR_Side_Fb)", rtDW.ADC_Data_Model.Sensor_Front_Duct6, TABLE_DUCT, 3000); + LoggerErrorStatic(LOGGER, LOG_SIGN, "======================================================================"); +*/ + + + + + + + + + + + + + + + + + +// ANALOG_SENSOR(env, "Reserve_Sensor_Duct_Temp_1", rtDW.ADC_Data_Model.Reserve_Sensor_Duct_Temp_1, TABLE_DUCT,20000); + + +/* + ANALOG_SENSOR(env, "Sensor_Front_Duct1 (dbg_Sen_Duct_FL_Upper_Fb)", rtDW.ADC_Data_Model.Sensor_Front_Duct1, TABLE_DUCT, 3000); + ANALOG_SENSOR(env, "Sensor_Front_Duct2 (dbg_Sen_Duct_FR_Upper_Fb)", rtDW.ADC_Data_Model.Sensor_Front_Duct2, TABLE_DUCT, 3000); + ANALOG_SENSOR(env, "Sensor_Front_Duct3 (dbg_Sen_Duct_FL_Lower_Fb)", rtDW.ADC_Data_Model.Sensor_Front_Duct3, TABLE_DUCT, 3000); + ANALOG_SENSOR(env, "Sensor_Front_Duct4 (dbg_Sen_Duct_FR_Lower_Fb)", rtDW.ADC_Data_Model.Sensor_Front_Duct4, TABLE_DUCT, 3000); + ANALOG_SENSOR(env, "Sensor_Front_Duct5 (dbg_Sen_Duct_FL_Side_Fb)", rtDW.ADC_Data_Model.Sensor_Front_Duct5, TABLE_DUCT, 3000); + ANALOG_SENSOR(env, "Sensor_Front_Duct6 (dbg_Sen_Duct_FR_Side_Fb)", rtDW.ADC_Data_Model.Sensor_Front_Duct6, TABLE_DUCT, 3000); + */ +/* + LoggerErrorStatic(LOGGER, LOG_SIGN, "======================================================================"); + ANALOG_SENSOR(env, "Sensor_AC_Pressure", rtDW.ADC_Data_Model.Sensor_AC_Pressure, TABLE_NONE, 0); + + ANALOG_SENSOR(env, "Sensor_Front_Duct1 (dbg_Sen_Duct_FL_Upper_Fb)", rtDW.ADC_Data_Model.Sensor_Front_Duct1, TABLE_DUCT, 3000); + ANALOG_SENSOR(env, "Sensor_Front_Duct2 (dbg_Sen_Duct_FR_Upper_Fb)", rtDW.ADC_Data_Model.Sensor_Front_Duct2, TABLE_DUCT, 3000); + ANALOG_SENSOR(env, "Sensor_Front_Duct3 (dbg_Sen_Duct_FL_Lower_Fb)", rtDW.ADC_Data_Model.Sensor_Front_Duct3, TABLE_DUCT, 3000); + ANALOG_SENSOR(env, "Sensor_Front_Duct4 (dbg_Sen_Duct_FR_Lower_Fb)", rtDW.ADC_Data_Model.Sensor_Front_Duct4, TABLE_DUCT, 3000); + ANALOG_SENSOR(env, "Sensor_Front_Duct5 (dbg_Sen_Duct_FL_Side_Fb)", rtDW.ADC_Data_Model.Sensor_Front_Duct5, TABLE_DUCT, 3000); + ANALOG_SENSOR(env, "Sensor_Front_Duct6 (dbg_Sen_Duct_FR_Side_Fb)", rtDW.ADC_Data_Model.Sensor_Front_Duct6, TABLE_DUCT, 3000); + ANALOG_SENSOR(env, "Sensor_Evap_Temp", rtDW.ADC_Data_Model.Sensor_Evap_Temp, TABLE_DUCT, 20000); + + ANALOG_SENSOR(env, "Sensor_Rear_Duct1 (dbg_Sen_Duct_RL_Fb)", rtDW.ADC_Data_Model.Sensor_Rear_Duct1, TABLE_DUCT, 3000); + ANALOG_SENSOR(env, "Sensor_Rear_Duct2 (dbg_Sen_Duct_RR_Fb)", rtDW.ADC_Data_Model.Sensor_Rear_Duct2, TABLE_DUCT, 3000); + ANALOG_SENSOR(env, "Sensor_Rear_Duct3 (dbg_Sen_Duct_RL_Side_Fb)", rtDW.ADC_Data_Model.Sensor_Rear_Duct3, TABLE_DUCT, 3000); + ANALOG_SENSOR(env, "Sensor_Rear_Duct4 (dbg_Sen_Duct_RR_Side_Fb)", rtDW.ADC_Data_Model.Sensor_Rear_Duct4, TABLE_DUCT, 3000); + ANALOG_SENSOR(env, "Sensor_Rear_Evap_Temp", rtDW.ADC_Data_Model.Sensor_Rear_Evap_Temp, TABLE_DUCT, 20000); + + LoggerErrorStatic(LOGGER, LOG_SIGN, "======================================================================"); + ANALOG_SENSOR(env, "Sensor_Incar_Temp_FL", rtDW.ADC_Data_Model.Sensor_Incar_Temp_FL, TABLE_INCAR, 20000); + ANALOG_SENSOR(env, "Sensor_Incar_Temp_RL", rtDW.ADC_Data_Model.Sensor_Incar_Temp_RL, TABLE_INCAR, 20000); + ANALOG_SENSOR(env, "Sensor_Incar_Temp_FR", rtDW.ADC_Data_Model.Sensor_Incar_Temp_FR, TABLE_INCAR, 20000); + ANALOG_SENSOR(env, "Sensor_Incar_Temp_RR", rtDW.ADC_Data_Model.Sensor_Incar_Temp_RR, TABLE_INCAR, 20000); + LoggerErrorStatic(LOGGER, LOG_SIGN, "======================================================================"); +*/ + +// ANALOG_SENSOR(env, "Sensor_Rear_Duct3", rtDW.ADC_Data_Model.Sensor_Rear_Duct3, TABLE_DUCT, 3000); + +// float Rntc = calculate_ntc_resistance(rtDW.ADC_Data_Model.Sensor_Rear_Duct3, 3000, 4.96f, 5, 4095); +// LoggerFormatInfo(LOGGER, LOG_SIGN, "Rntc = %f", Rntc) + + +/* + ANALOG_SENSOR(env, "Pressure_DIAG", rtDW.ADC_Data_Model.Pressure_DIAG, TABLE_NONE, 0); + + ANALOG_SENSOR(env, "Reserve_Sensor_Duct_Temp_2", rtDW.ADC_Data_Model.Reserve_Sensor_Duct_Temp_2, TABLE_DUCT, + 20000); +*/ + +/* + ANALOG_SENSOR(env, "Sensor_PT_rHVAC_P", rtDW.ADC_Data_Model.Sensor_PT_rHVAC_P); + ANALOG_SENSOR(env, "Sensor_A_T_reserve", rtDW.ADC_Data_Model.Sensor_A_T_reserve); +*/ + +//////////////////////////////////////----DEBUG----//////////////////////////////////////////////////////////////////// + + + + uint32_t countQueueCmdBusADCData = osMessageQueueGetSpace(env->queueCmdBusADCData); + + if (countQueueCmdBusADCData) { + osStatus_t status = osMessageQueuePut(env->queueCmdBusADCData, &env->cmdBusADCData, 0, 0U); + } + + + + + + + + +// osMutexRelease(env->modelTaskAccess); +// } else { +// LoggerErrorStatic(LOGGER, LOG_SIGN, "Access error Adc0_Thread"); +// } + +// ++env->step; + + if (env->step > MAX_ADC_FILTER_SIZE * 2) { + SystemDelayMs(10); + } + } +} + +void getCmdBusADCData(tAdc0Task *env, CmdBusADCData *cmdBusADCData) { + + osStatus_t status = osOK; + + uint32_t countQueue_space = osMessageQueueGetSpace(env->queueCmdBusADCData); + if (countQueue_space == 0) { + status = osMessageQueueGet(env->queueCmdBusADCData, cmdBusADCData, 0, 0); + } + +} + + +uint32_t getRandom32(tAdc0Task *env) { + + uint32_t random = 0; + + osStatus_t status = osMessageQueueGet(env->queueRandom, &random, 0, 0); + + if (status == osOK) { + return random; + } else { + return 0x11223344; + } + + return 0; +} + +void Adc_0_StartThread(tAdc0Task *env) { + if (!env->thread.id) { + env->thread.id = osThreadNew((osThreadFunc_t) (Adc0_Thread), (void *) (env), &env->thread.attr); + } +} + + +void Adc_1_Init(tAdc1Task *env, + tAdcIO *adcIO, + tGpios *gpios, + tLoggerInterface *logger) { + + env->adcIO = adcIO; + env->logger = logger; + env->access = osMutexNew(NULL); + env->gpios = gpios; + + env->queueCmdBusADC2Data = osMessageQueueNew(1, sizeof(CmdBusADC2Data), NULL); + + ADC_Filter_Init(&env->ADC1_Filter_data.VN7008AJ_DIAG_FrontLINActuatorPowerDriverAB, MAX_ADC_FILTER_SIZE); + ADC_Filter_Init(&env->ADC1_Filter_data.VN7008AJ_DIAG_RearLINActuatorPowerDriverC, MAX_ADC_FILTER_SIZE); + ADC_Filter_Init(&env->ADC1_Filter_data.PBATT_CHECK, MAX_ADC_FILTER_SIZE); + ADC_Filter_Init(&env->ADC1_Filter_data.VN7008AJ_FrontLINActuatorPowerDriverAB, MAX_ADC_FILTER_SIZE); + ADC_Filter_Init(&env->ADC1_Filter_data.VN7008AJ_RearLINActuatorPowerDriverC, MAX_ADC_FILTER_SIZE); + + InitThreadAtrStatic(&env->thread.attr, "Adc1", env->thread.controlBlock, env->thread.stack, + osPriorityNormal); +} + + +static _Noreturn void Adc1_Thread(tAdc1Task *env) { + + uint32_t ADC_Pointer_Data; + + for (;;) { + env->ADC_ChannelCount = env->adcIO->get(env->adcIO->env, &ADC_Pointer_Data, 5000); + +// uint32_t *pData = (uint32_t *) ADC_Pointer_Data; + +// if (osMutexAcquire(env->modelTaskAccess, 5000) == osOK) { + + tADC1_data *ADC1_data = (tADC1_data *) ADC_Pointer_Data; + + env->cmdBusADC2Data.VN7008AJ_DIAG_FrontLINActuatorPowerDriverAB = ADC_Filter_Update(&env->ADC1_Filter_data.VN7008AJ_DIAG_FrontLINActuatorPowerDriverAB,ADC1_data->VN7008AJ_DIAG_FrontLINActuatorPowerDriverAB); + env->cmdBusADC2Data.VN7008AJ_DIAG_RearLINActuatorPowerDriverC = ADC_Filter_Update(&env->ADC1_Filter_data.VN7008AJ_DIAG_RearLINActuatorPowerDriverC,ADC1_data->VN7008AJ_DIAG_RearLINActuatorPowerDriverC); + env->cmdBusADC2Data.PBATT_CHECK = ADC_Filter_Update(&env->ADC1_Filter_data.PBATT_CHECK,ADC1_data->PBATT_CHECK); + env->cmdBusADC2Data.VN7008AJ_FrontLINActuatorPowerDriverAB = ADC_Filter_Update(&env->ADC1_Filter_data.VN7008AJ_FrontLINActuatorPowerDriverAB,ADC1_data->VN7008AJ_FrontLINActuatorPowerDriverAB); + env->cmdBusADC2Data.VN7008AJ_RearLINActuatorPowerDriverC = ADC_Filter_Update(&env->ADC1_Filter_data.VN7008AJ_RearLINActuatorPowerDriverC,ADC1_data->VN7008AJ_RearLINActuatorPowerDriverC); + + uint32_t countQueueCmdBusADC2Data = osMessageQueueGetSpace(env->queueCmdBusADC2Data); + + if (countQueueCmdBusADC2Data) { + osStatus_t status = osMessageQueuePut(env->queueCmdBusADC2Data, &env->cmdBusADC2Data, 0, 0U); + } +/* + rtDW.ADC_Data_Model.VN7008AJ_DIAG_FrontLINActuatorPowerDriverAB = pData[0]; + rtDW.ADC_Data_Model.VN7008AJ_DIAG_RearLINActuatorPowerDriverC = pData[1]; + rtDW.ADC_Data_Model.PBATT_CHECK = pData[2]; + rtDW.ADC_Data_Model.VN7008AJ_FrontLINActuatorPowerDriverAB = pData[3]; + rtDW.ADC_Data_Model.VN7008AJ_RearLINActuatorPowerDriverC = pData[4]; +*/ +/* + rtDW.ADC_Data_Model.PT_F_HVAC_VCC_DIAG = pData[5]; // PT_F_HVAC_VCC_DIAG + rtDW.ADC_Data_Model.PT_HVBchiller_VCC_DIAG = pData[6]; // PT_HVBchiller_VCC_DIAG + rtDW.ADC_Data_Model.PT_R_HVAC_VCC_DIAG = pData[7]; // PT_R_HVAC_VCC_DIAG + rtDW.ADC_Data_Model.Sensor_PT_fHVAC_P = pData[8]; + rtDW.ADC_Data_Model.Sensor_PT_fHVAC_T = pData[9]; + rtDW.ADC_Data_Model.Sensor_PT_rHVAC_T = pData[10]; + rtDW.ADC_Data_Model.Sensor_HVBchiller_P = pData[11]; + rtDW.ADC_Data_Model.Sensor_HVBchiller_T = pData[12]; + rtDW.ADC_Data_Model.Sensor_PT_P_reserve = pData[13]; + rtDW.ADC_Data_Model.Sensor_PT_T_reserve = pData[14]; + rtDW.ADC_Data_Model.Sensor_B_T_reserve = pData[15]; +*/ + +//////////////////////////////////////----DEBUG----//////////////////////////////////////////////////////////////////// +/* + ANALOG_SENSOR(env, "PT_F_HVAC_VCC_DIAG", rtDW.ADC_Data_Model.PT_F_HVAC_VCC_DIAG); + ANALOG_SENSOR(env, "PT_HVBchiller_VCC_DIAG", rtDW.ADC_Data_Model.PT_HVBchiller_VCC_DIAG); + ANALOG_SENSOR(env, "PT_R_HVAC_VCC_DIAG", rtDW.ADC_Data_Model.PT_R_HVAC_VCC_DIAG); + + + ANALOG_SENSOR(env, "Sensor_PT_fHVAC_P", rtDW.ADC_Data_Model.Sensor_PT_fHVAC_P); + ANALOG_SENSOR(env, "Sensor_PT_rHVAC_T", rtDW.ADC_Data_Model.Sensor_PT_rHVAC_T); + ANALOG_SENSOR(env, "Sensor_HVBchiller_P", rtDW.ADC_Data_Model.Sensor_HVBchiller_P); + ANALOG_SENSOR(env, "Sensor_HVBchiller_T", rtDW.ADC_Data_Model.Sensor_HVBchiller_T); + ANALOG_SENSOR(env, "Sensor_PT_P_reserve", rtDW.ADC_Data_Model.Sensor_PT_P_reserve); + ANALOG_SENSOR(env, "Sensor_PT_T_reserve", rtDW.ADC_Data_Model.Sensor_PT_T_reserve); + ANALOG_SENSOR(env, "Sensor_B_T_reserve", rtDW.ADC_Data_Model.Sensor_B_T_reserve); +*/ + + + + + + + +/* + LoggerErrorStatic(LOGGER, LOG_SIGN, "======================================================================"); + ANALOG_SENSOR((tAdc0Task*)env, "VN7008AJ_DIAG_FrontLINActuatorPowerDriverAB", + rtDW.ADC_Data_Model.VN7008AJ_DIAG_FrontLINActuatorPowerDriverAB, TABLE_NONE, 0); + ANALOG_SENSOR((tAdc0Task*)env, "VN7008AJ_DIAG_RearLINActuatorPowerDriverC", + rtDW.ADC_Data_Model.VN7008AJ_DIAG_RearLINActuatorPowerDriverC, TABLE_NONE, 0); + + VN7008AJ((tAdc0Task*)env, "VN7008AJ_FrontLINActuatorPowerDriverAB", + rtDW.ADC_Data_Model.VN7008AJ_FrontLINActuatorPowerDriverAB); + VN7008AJ((tAdc0Task*)env, "VN7008AJ_RearLINActuatorPowerDriverC", + rtDW.ADC_Data_Model.VN7008AJ_RearLINActuatorPowerDriverC); + LoggerErrorStatic(LOGGER, LOG_SIGN, "======================================================================"); +*/ + + + + + + + + + +//////////////////////////////////////----DEBUG----//////////////////////////////////////////////////////////////////// + + +// float V_ref = (float) pData[16] / 4095.0f * 5.0f; +// LoggerFormatInfo(LOGGER, LOG_SIGN, "V_ref = %f", V_ref) + +// osMutexRelease(env->modelTaskAccess); +// } else { +// LoggerErrorStatic(LOGGER, LOG_SIGN, "Access error Adc1_Thread"); +// } + +// ++env->step; + + if (env->step > MAX_ADC_FILTER_SIZE * 2) { + SystemDelayMs(10); + } + } +} + +void getCmdBusADC2Data(tAdc1Task *env, CmdBusADC2Data *cmdBusADC2Data) { + osStatus_t status = osOK; + + uint32_t countQueue_space = osMessageQueueGetSpace(env->queueCmdBusADC2Data); + if (countQueue_space == 0) { + status = osMessageQueueGet(env->queueCmdBusADC2Data, cmdBusADC2Data, 0, 0); + } + + +} + + +void Adc_1_StartThread(tAdc1Task *env) { + if (!env->thread.id) { + env->thread.id = osThreadNew((osThreadFunc_t) (Adc1_Thread), (void *) (env), &env->thread.attr); + } +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_ADC_TASKS/AdcTasks.h b/MODULES/HVAC_M7_ADC_TASKS/AdcTasks.h new file mode 100644 index 0000000..de08d71 --- /dev/null +++ b/MODULES/HVAC_M7_ADC_TASKS/AdcTasks.h @@ -0,0 +1,292 @@ +// +// Created by cfif on 15.12.2025. +// + +#ifndef HVAC_M7_ADCTASKS_H +#define HVAC_M7_ADCTASKS_H + +#include "AdcIO.h" +#include "stdbool.h" +#include +#include "Gpios.h" +#include "LoggerInterface.h" +#include "AdcFilter.h" +#include "HVAC_model.h" + +/* +typedef struct { + uint32_t Sensor_Ambient_Temp; + uint32_t IGN_ANS; + uint32_t Sensor_AC_Pressure; + uint32_t Sensor_Incar_Temp_FL; + uint32_t Sensor_Incar_Temp_RL; + uint32_t Sensor_Rear_Evap_Temp; + uint32_t Sensor_Evap_Temp; + uint32_t Sensor_Rear_Duct1; + uint32_t Sensor_Rear_Duct2; + uint32_t Sensor_Front_Duct1; + uint32_t Sensor_Front_Duct2; + uint32_t Sensor_Front_Duct3; + uint32_t Sensor_Front_Duct4; + uint32_t Sensor_Rear_Duct3; + uint32_t Sensor_Rear_Duct4; + uint32_t Sensor_Incar_Temp_FR; + uint32_t Sensor_Incar_Temp_RR; + uint32_t Sensor_Rear_Duct5; + uint32_t Sensor_Rear_Duct6; + uint32_t Reserve_Sensor_Duct_Temp_1; + uint32_t Sensor_Front_Duct5; + uint32_t Sensor_Front_Duct6; + + uint32_t BTS5120_2EKA_ShutoffValvePowerTXV1; // + uint32_t BTS5120_2EKA_ShutoffValvePowerTXV2; // + + uint32_t Pressure_DIAG; + + uint32_t BTS5180_2EKA_ShutOFFValveFront; // + uint32_t BTS5180_2EKA_ShutOFFValveRear; // + + uint32_t BTS5180_2EKA_TwoWayValve; // + uint32_t BTS5180_2EKA_ReservePowerSupply; // + + uint32_t BTS5180_2EKA_FrontIncarMotor; // + uint32_t BTS5180_2EKA_RearIncarMotor; // + + uint32_t BTS5180_2EKA_ChannelPTCPower1; // + uint32_t BTS5180_2EKA_ChannelPTCPower2; // + + uint32_t Reserve_Sensor_Duct_Temp_2; + + uint32_t Sensor_PT_rHVAC_P; + uint32_t Sensor_A_T_reserve; + +} tADC0_data; +*/ + +typedef struct { + uint32_t Sensor_Ambient_Temp; + uint32_t IGN_ANS; + uint32_t Sensor_AC_Pressure; + uint32_t Sensor_Incar_Temp_FL; + uint32_t Sensor_Incar_Temp_RL; + uint32_t Sensor_Rear_Evap_Temp; + uint32_t Sensor_Evap_Temp; + uint32_t Sensor_Rear_Duct1; + uint32_t Sensor_Rear_Duct2; + uint32_t Sensor_Front_Duct1; + uint32_t Sensor_Front_Duct2; + uint32_t Sensor_Front_Duct3; + uint32_t Sensor_Front_Duct4; + uint32_t Sensor_Rear_Duct3; + uint32_t Sensor_Rear_Duct4; + uint32_t Sensor_Incar_Temp_FR; + uint32_t Sensor_Incar_Temp_RR; + uint32_t Sensor_Rear_Duct5; + uint32_t Sensor_Rear_Duct6; + uint32_t Reserve_Sensor_Duct_Temp_1; + uint32_t Sensor_Front_Duct5; + uint32_t Sensor_Front_Duct6; + + uint32_t BTS5120_2EKA_ShutoffValvePowerTXV1_BTS5120_2EKA_ShutoffValvePowerTXV2; // + + uint32_t Pressure_DIAG; + + uint32_t BTS5180_2EKA_ShutOFFValveFront_BTS5180_2EKA_ShutOFFValveRear; // + + uint32_t BTS5180_2EKA_TwoWayValve_BTS5180_2EKA_ReservePowerSupply; // + + + uint32_t BTS5180_2EKA_FrontIncarMotor_BTS5180_2EKA_RearIncarMotor; // + + uint32_t BTS5180_2EKA_ChannelPTCPower1_BTS5180_2EKA_ChannelPTCPower2; // + + uint32_t Reserve_Sensor_Duct_Temp_2; + + uint32_t Sensor_PT_rHVAC_P; + uint32_t Sensor_A_T_reserve; + +} tADC0_data; + + +typedef struct { + uint32_t VN7008AJ_DIAG_FrontLINActuatorPowerDriverAB; + uint32_t VN7008AJ_DIAG_RearLINActuatorPowerDriverC; + uint32_t PBATT_CHECK; + uint32_t VN7008AJ_FrontLINActuatorPowerDriverAB; + uint32_t VN7008AJ_RearLINActuatorPowerDriverC; + + uint32_t PT_F_HVAC_VCC_DIAG; + uint32_t PT_HVBchiller_VCC_DIAG; + uint32_t PT_R_HVAC_VCC_DIAG; + uint32_t Sensor_PT_fHVAC_P; + uint32_t Sensor_PT_fHVAC_T; + uint32_t Sensor_PT_rHVAC_T; + uint32_t Sensor_HVBchiller_P; + uint32_t Sensor_HVBchiller_T; + uint32_t Sensor_PT_P_reserve; + uint32_t Sensor_PT_T_reserve; + uint32_t Sensor_B_T_reserve; + +} tADC1_data; + +typedef struct { + ADC_Filter Sensor_Ambient_Temp; + ADC_Filter IGN_ANS; + ADC_Filter Sensor_AC_Pressure; + ADC_Filter Sensor_Incar_Temp_FL; + ADC_Filter Sensor_Incar_Temp_RL; + ADC_Filter Sensor_Rear_Evap_Temp; + ADC_Filter Sensor_Evap_Temp; + ADC_Filter Sensor_Rear_Duct1; + ADC_Filter Sensor_Rear_Duct2; + ADC_Filter Sensor_Front_Duct1; + ADC_Filter Sensor_Front_Duct2; + ADC_Filter Sensor_Front_Duct3; + ADC_Filter Sensor_Front_Duct4; + ADC_Filter Sensor_Rear_Duct3; + ADC_Filter Sensor_Rear_Duct4; + ADC_Filter Sensor_Incar_Temp_FR; + ADC_Filter Sensor_Incar_Temp_RR; + ADC_Filter Sensor_Rear_Duct5; + ADC_Filter Sensor_Rear_Duct6; + ADC_Filter Reserve_Sensor_Duct_Temp_1; + ADC_Filter Sensor_Front_Duct5; + ADC_Filter Sensor_Front_Duct6; + + ADC_Filter BTS5120_2EKA_ShutoffValvePowerTXV1; // + ADC_Filter BTS5120_2EKA_ShutoffValvePowerTXV2; // + + ADC_Filter Pressure_DIAG; + + ADC_Filter BTS5180_2EKA_ShutOFFValveFront; // + ADC_Filter BTS5180_2EKA_ShutOFFValveRear; // + + ADC_Filter BTS5180_2EKA_TwoWayValve; // + ADC_Filter BTS5180_2EKA_ReservePowerSupply; // + + ADC_Filter BTS5180_2EKA_FrontIncarMotor; // + ADC_Filter BTS5180_2EKA_RearIncarMotor; // + + ADC_Filter BTS5180_2EKA_ChannelPTCPower1; // + ADC_Filter BTS5180_2EKA_ChannelPTCPower2; // + + ADC_Filter Reserve_Sensor_Duct_Temp_2; + + ADC_Filter Sensor_PT_rHVAC_P; + ADC_Filter Sensor_A_T_reserve; + +} tADC0_Filter_data; + +typedef struct { + ADC_Filter VN7008AJ_DIAG_FrontLINActuatorPowerDriverAB; + ADC_Filter VN7008AJ_DIAG_RearLINActuatorPowerDriverC; + ADC_Filter PBATT_CHECK; + ADC_Filter VN7008AJ_FrontLINActuatorPowerDriverAB; + ADC_Filter VN7008AJ_RearLINActuatorPowerDriverC; + + ADC_Filter PT_F_HVAC_VCC_DIAG; + ADC_Filter PT_HVBchiller_VCC_DIAG; + ADC_Filter PT_R_HVAC_VCC_DIAG; + ADC_Filter Sensor_PT_fHVAC_P; + ADC_Filter Sensor_PT_fHVAC_T; + ADC_Filter Sensor_PT_rHVAC_T; + ADC_Filter Sensor_HVBchiller_P; + ADC_Filter Sensor_HVBchiller_T; + ADC_Filter Sensor_PT_P_reserve; + ADC_Filter Sensor_PT_T_reserve; + ADC_Filter Sensor_B_T_reserve; + +} tADC1_Filter_data; + + +typedef struct { + + tAdcIO *adcIO; + osMutexId_t access; + tLoggerInterface *logger; + + tADC0_data ADC0_Data; + tADC0_Filter_data ADC0_Filter_data; + + + uint8_t ADC_ChannelCount; + + tGpios *gpios; + + uint8_t ADC0_BTS5120_2EKA_Channel; + + osMessageQueueId_t queueRandom; + + CmdBusADCData cmdBusADCData; + osMessageQueueId_t queueCmdBusADCData; + + uint32_t step; + + struct { + osThreadId_t id; + uint32_t stack[384]; + StaticTask_t controlBlock; + osThreadAttr_t attr; + } thread; + +} tAdc0Task; + + +typedef struct { + uint16_t VN7008AJ_DIAG_FrontLINActuatorPowerDriverAB; + uint16_t VN7008AJ_DIAG_RearLINActuatorPowerDriverC; + uint16_t PBATT_CHECK; + uint16_t VN7008AJ_FrontLINActuatorPowerDriverAB; + uint16_t VN7008AJ_RearLINActuatorPowerDriverC; +} CmdBusADC2Data; + +typedef struct { + + tAdcIO *adcIO; + osMutexId_t access; + tLoggerInterface *logger; + + tADC1_data ADC1_Data; + tADC1_Filter_data ADC1_Filter_data; + + + + uint8_t ADC_ChannelCount; + + tGpios *gpios; + + CmdBusADC2Data cmdBusADC2Data; + osMessageQueueId_t queueCmdBusADC2Data; + + uint32_t step; + + struct { + osThreadId_t id; + uint32_t stack[384]; + StaticTask_t controlBlock; + osThreadAttr_t attr; + } thread; + +} tAdc1Task; + +uint32_t getRandom32(tAdc0Task *env); + +void Adc_0_Init(tAdc0Task *env, + tAdcIO *adcIO, + tGpios *gpios, + tLoggerInterface *logger); + +void Adc_0_StartThread(tAdc0Task *env); + +void getCmdBusADCData(tAdc0Task *env, CmdBusADCData *cmdBusADCData); + +void Adc_1_Init(tAdc1Task *env, + tAdcIO *adcIO, + tGpios *gpios, + tLoggerInterface *logger); + +void Adc_1_StartThread(tAdc1Task *env); + +void getCmdBusADC2Data(tAdc1Task *env, CmdBusADC2Data *cmdBusADC2Data); + +#endif //HVAC_M7_ADCTASKS_H diff --git a/MODULES/HVAC_M7_ADC_TASKS/modular.json b/MODULES/HVAC_M7_ADC_TASKS/modular.json new file mode 100644 index 0000000..99df025 --- /dev/null +++ b/MODULES/HVAC_M7_ADC_TASKS/modular.json @@ -0,0 +1,10 @@ +{ + "cmake": { + "inc_dirs": [ + "./" + ], + "srcs": [ + "./**.c" + ] + } +} diff --git a/MODULES/HVAC_M7_ADC_TEMP/ADC_Temp.c b/MODULES/HVAC_M7_ADC_TEMP/ADC_Temp.c new file mode 100644 index 0000000..84ef434 --- /dev/null +++ b/MODULES/HVAC_M7_ADC_TEMP/ADC_Temp.c @@ -0,0 +1,627 @@ +// +// Created by cfif on 02.12.2025. +// +#include "ADC_Temp.h" +#include +#include +#include + +// Структура для хранения табличных данных +typedef struct { + int temp_c; // Температура (°C) + float r_nom; // Номинальное сопротивление (Ω) +} ntc_table_entry; + +// Таблица из документа KST45 (Duct) +static const ntc_table_entry ntc_table_duct[] = { + {-40, 100950.0f}, + {-35, 72777.0f}, + {-30, 53100.0f}, + {-25, 39111.0f}, + {-20, 29121.0f}, + {-15, 21879.0f}, + {-10, 16599.0f}, + {-5, 12695.0f}, + {0, 9795.0f}, + {5, 7616.0f}, + {10, 5970.0f}, + {15, 4712.0f}, + {20, 3747.0f}, + {25, 3000.0f}, + {30, 2417.0f}, + {35, 1959.0f}, + {40, 1598.0f}, + {45, 1311.0f}, + {50, 1081.0f}, + {55, 895.9f}, + {60, 746.4f}, + {65, 624.9f}, + {70, 525.6f}, + {75, 444.4f}, + {80, 377.4f}, + {85, 321.7f} +}; + +// Таблица из документа Incar +static const ntc_table_entry ntc_table_incar[] = { + {-40, 101000.0f}, + {-35, 72600.0f}, + {-30, 52720.0f}, + {-25, 38660.0f}, + {-20, 28620.0f}, + {-15, 21390.0f}, + {-10, 16120.0f}, + {-5, 12260.0f}, + {-4, 11620.0f}, + {-3, 11010.0f}, + {-2, 10440.0f}, + {-1, 9907.0f}, + {0, 9399.0f}, + {1, 8924.0f}, + {2, 8473.0f}, + {3, 8048.0f}, + {4, 7646.0f}, + {5, 7267.0f}, + {6, 6909.0f}, + {7, 6570.0f}, + {8, 6250.0f}, + {9, 5947.0f}, + {10, 5661.0f}, + {15, 4441.0f}, + {20, 3512.0f}, + {25, 2795.0f}, + {30, 2239.0f}, + {35, 1806.0f}, + {40, 1464.0f}, + {45, 1195.0f}, + {50, 980.0f}, + {55, 809.0f}, + {60, 670.0f}, + {65, 559.0f}, + {70, 468.0f}, + {75, 394.0f}, + {80, 333.0f}, + {85, 283.0f} +}; + +// Таблица для NTC 10 кОм (Ambient) +static const ntc_table_entry ntc_table_ambient[] = { + {-40, 332776.0f}, + {-35, 240264.0f}, + {-30, 175427.0f}, + {-25, 129449.0f}, + {-20, 96481.0f}, + {-15, 72592.0f}, + {-10, 55109.0f}, + {-5, 42193.0f}, + {0, 32566.0f}, + {5, 25338.0f}, + {10, 19869.0f}, + {15, 15695.0f}, + {20, 12486.0f}, + {25, 10000.0f}, + {30, 8060.0f}, + {35, 6536.0f}, + {40, 5331.0f}, + {45, 4373.0f}, + {50, 3606.0f}, + {55, 2990.0f}, + {60, 2490.0f}, + {65, 2085.0f}, + {70, 1754.0f}, + {75, 1482.0f}, + {80, 1257.0f}, + {85, 1071.0f}, + {90, 916.4f}, + {95, 786.9f}, + {100, 678.1f}, + {105, 586.5f}, + {110, 509.1f}, + {115, 443.3f}, + {120, 387.3f}, + {125, 339.5f}, + {130, 298.4f}, + {135, 263.1f}, + {140, 232.6f}, + {145, 206.1f}, + {150, 183.2f} +}; + +// Глобальная структура для хранения таблиц быстрого доступа +fast_lookup_tables_t g_fast_tables = { + .duct_initialized = false, + .incar_initialized = false, + .ambient_initialized = false, + .duct_r1 = 3300.0f, + .incar_r1 = 3300.0f, + .ambient_r1 = 3300.0f +}; + +// Активная конфигурация +static ntc_config_t active_config = { + .table_type = TABLE_DUCT, + .r1 = 3300.0f, + .start_temp = -40, + .end_temp = 85, + .table_size = TABLE_SIZE_DUCT +}; + +// Вспомогательная функция для получения таблицы по типу +static const ntc_table_entry* get_table_by_type(eNtcTable table_type, uint16_t* size, int16_t* start_temp, int16_t* end_temp) { + const ntc_table_entry* table = NULL; + *size = 0; + + switch(table_type) { + case TABLE_DUCT: + table = ntc_table_duct; + *size = TABLE_SIZE_DUCT; + *start_temp = -40; + *end_temp = 85; + break; + case TABLE_INCAR: + table = ntc_table_incar; + *size = TABLE_SIZE_INCAR; + *start_temp = -40; + *end_temp = 85; + break; + case TABLE_AMBIENT: + table = ntc_table_ambient; + *size = TABLE_SIZE_AMBIENT; + *start_temp = -40; + *end_temp = 150; + break; + default: + table = ntc_table_duct; + *size = TABLE_SIZE_DUCT; + *start_temp = -40; + *end_temp = 85; + break; + } + return table; +} + +// Функция для получения указателя на таблицу быстрого доступа по типу +static adc_temp_lookup* get_fast_table_by_type(eNtcTable table_type) { + switch(table_type) { + case TABLE_DUCT: + return g_fast_tables.duct; + case TABLE_INCAR: + return g_fast_tables.incar; + case TABLE_AMBIENT: + return g_fast_tables.ambient; + default: + return g_fast_tables.duct; + } +} + +// Функция для получения статуса инициализации таблицы +static bool is_table_initialized(eNtcTable table_type) { + switch(table_type) { + case TABLE_DUCT: + return g_fast_tables.duct_initialized; + case TABLE_INCAR: + return g_fast_tables.incar_initialized; + case TABLE_AMBIENT: + return g_fast_tables.ambient_initialized; + default: + return false; + } +} + +// Функция расчёта сопротивления NTC из значения АЦП +static float calculate_resistance(uint16_t adc_value, float r1) { + if (adc_value == 0 || adc_value >= (uint16_t) ADC_MAX) { + return 0.0f; + } + float R_ntc = r1 * (float) adc_value / (ADC_MAX - (float) adc_value); + return R_ntc; +} + +// Бинарный поиск в таблице +static int find_interval_index(float resistance, const ntc_table_entry* table, uint16_t table_size) { + int left = 0; + int right = table_size - 1; + + // Проверка границ + if (resistance >= table[0].r_nom) return 0; + if (resistance <= table[right].r_nom) return right - 1; + + // Бинарный поиск + while (left <= right) { + int mid = left + (right - left) / 2; + + if (mid < table_size - 1 && + resistance <= table[mid].r_nom && + resistance >= table[mid + 1].r_nom) { + return mid; + } + + if (resistance > table[mid].r_nom) { + right = mid - 1; + } else { + left = mid + 1; + } + } + + return -1; // Не найден +} + +// Интерполяция с использованием уравнения Стейнхарта-Харта между точками +static float interpolate_steinhart(float resistance, int index, const ntc_table_entry* table) { + // Берем две соседние точки из таблицы + float t1 = (float) table[index].temp_c + 273.15f; // в Кельвинах + float t2 = (float) table[index + 1].temp_c + 273.15f; + float r1 = table[index].r_nom; + float r2 = table[index + 1].r_nom; + + // Вычисляем коэффициент B для интервала + float B = logf(r1 / r2) / (1.0f / t1 - 1.0f / t2); + + // Используем уравнение Стейнхарта-Харта для вычисления температуры + float steinhart = logf(resistance / r1) / B + 1.0f / t1; + float temp_k = 1.0f / steinhart; + + return temp_k - 273.15f; // Конвертация в °C +} + +// Линейная интерполяция в логарифмическом масштабе +static float interpolate_log_linear(float resistance, int index, const ntc_table_entry* table) { + float t1 = (float) table[index].temp_c; + float t2 = (float) table[index + 1].temp_c; + float r1 = table[index].r_nom; + float r2 = table[index + 1].r_nom; + + float log_r1 = logf(r1); + float log_r2 = logf(r2); + float log_r = logf(resistance); + + return t1 + (t2 - t1) * (log_r - log_r1) / (log_r2 - log_r1); +} + +// Более надежная версия с проверкой параметров +static float interpolate_steinhart_full(float resistance, int index, const ntc_table_entry* table) { + // Проверка корректности входных данных + if (resistance <= 0.0f) { + return -273.15f; // Абсолютный ноль при некорректном сопротивлении + } + + // Для повышения точности можно использовать таблицу как справочную, + // но основное вычисление - по уравнению с коэффициентами + double L = logf(resistance); + + // Для термисторов NTC коэффициент C обычно очень маленький (порядка 1e-7...1e-8) + // Убедимся, что кубический член вычислен корректно + double L3 = L * L * L; + double inv_T = koef_A + koef_B * L + koef_C * L3; + + // Проверка на физическую реализуемость (температура должна быть положительной в Кельвинах) + if (inv_T <= 0.0f || inv_T > 1.0f) { // 1/T не может быть <= 0 (T < 0K) или слишком большим + // В случае ошибки возвращаем температуру из таблицы по индексу + return (float) table[index].temp_c; + } + + double temp_K = 1.0f / inv_T; + + // Дополнительная проверка диапазона (например, для NTC обычно -50...+150°C) + if (temp_K < 223.15f || temp_K > 423.15f) { // -50°C...150°C в Кельвинах + // Возвращаем значение из таблицы как запасной вариант + return (float) table[index].temp_c; + } + + return (float) (temp_K - 273.15f); +} + +// Основная функция для получения температуры с указанием таблицы и R1 +float get_temperature_from_adc_with_table(uint16_t adc_value, eAlg alg, eNtcTable table_type, float r1) { + float resistance = calculate_resistance(adc_value, r1); + + if (resistance <= 0.0f) { + return -273.15f; // Ошибка + } + + uint16_t table_size; + int16_t start_temp, end_temp; + const ntc_table_entry* table = get_table_by_type(table_type, &table_size, &start_temp, &end_temp); + + int index = find_interval_index(resistance, table, table_size); + + if (index < 0 || index >= table_size - 1) { + // Вне диапазона таблицы + if (resistance >= table[0].r_nom) return (float) start_temp; + if (resistance <= table[table_size - 1].r_nom) return (float) end_temp; + return -273.15f; // Ошибка + } + + if (alg == ALG_STEINHART) { + return interpolate_steinhart(resistance, index, table); + } else if (alg == ALG_STEINHART_FULL) { + return interpolate_steinhart_full(resistance, index, table); + } else { + return interpolate_log_linear(resistance, index, table); + } +} + +// Функция для получения температуры с активной конфигурацией +float get_temperature_from_adc(uint16_t adc_value, eAlg alg) { + return get_temperature_from_adc_with_table(adc_value, alg, active_config.table_type, active_config.r1); +} + +// Функция для получения сопротивления из значения АЦП с указанием таблицы +float get_resistance_from_adc_with_table(uint16_t adc_value, eNtcTable table_type, float r1) { + return calculate_resistance(adc_value, r1); +} + +// Функция для получения сопротивления с активной конфигурацией +float get_resistance_from_adc(uint16_t adc_value) { + return calculate_resistance(adc_value, active_config.r1); +} + +// Инициализация таблицы быстрого поиска для конкретной таблицы +void init_fast_lookup_table(eNtcTable table_type, float r1, eAlg use_alg) { + uint16_t table_size; + int16_t start_temp, end_temp; + const ntc_table_entry* table = get_table_by_type(table_type, &table_size, &start_temp, &end_temp); + adc_temp_lookup* fast_table = get_fast_table_by_type(table_type); + + // Сохраняем значение R1 для этой таблицы + if (table_type == TABLE_DUCT) { + g_fast_tables.duct_r1 = r1; + } else if (table_type == TABLE_INCAR) { + g_fast_tables.incar_r1 = r1; + } else { + g_fast_tables.ambient_r1 = r1; + } + + // Находим рабочий диапазон АЦП + uint16_t min_valid_adc = 0; + uint16_t max_valid_adc = 0; + + // Значения для граничных точек + float temp_at_min_adc = 0.0f; + float temp_at_max_adc = 0.0f; + float res_at_min_adc = 0.0f; + float res_at_max_adc = 0.0f; + + // Ищем минимальное АЦП, при котором температура >= start_temp (максимальная температура) + for (uint16_t adc = 1; adc < ADC_MAX; adc++) { + float resistance = calculate_resistance(adc, r1); + float temp = get_temperature_from_adc_with_table(adc, use_alg, table_type, r1); + + if (temp >= start_temp && temp <= end_temp) { + min_valid_adc = adc; + temp_at_min_adc = temp; + res_at_min_adc = resistance; + break; + } + } + + // Ищем максимальное АЦП, при котором температура <= end_temp (минимальная температура) + for (uint16_t adc = (uint16_t)(ADC_MAX - 1); adc > 0; adc--) { + float resistance = calculate_resistance(adc, r1); + float temp = get_temperature_from_adc_with_table(adc, use_alg, table_type, r1); + + if (temp >= start_temp && temp <= end_temp) { + max_valid_adc = adc; + temp_at_max_adc = temp; + res_at_max_adc = resistance; + break; + } + } + + // Заполняем таблицу для всего диапазона ADC от 0 до 4095 + uint32_t adc_step = ((uint32_t)(ADC_MAX - 1) * 1000) / (TABLE_SIZE_LOOKUP - 1); + uint32_t current_adc = 0; + uint16_t prev_adc = 0; + + for (uint16_t i = 0; i < TABLE_SIZE_LOOKUP; i++) { + uint16_t adc; + + if (i == 0) { + adc = 0; + current_adc = 0; + prev_adc = 0; + } else if (i == TABLE_SIZE_LOOKUP - 1) { + adc = (uint16_t)(ADC_MAX - 1); + } else { + current_adc += adc_step; + adc = (uint16_t)(current_adc / 1000); + + // Убеждаемся, что значения монотонно возрастают и нет дубликатов + if (adc <= prev_adc) { + adc = prev_adc + 1; + } + + // Убеждаемся, что не выходим за пределы + if (adc >= (uint16_t)(ADC_MAX - 1)) { + adc = (uint16_t)(ADC_MAX - 2); + } + } + + float resistance; + float temp; + + // Определяем, находится ли ADC в рабочем диапазоне + if (adc <= min_valid_adc) { + // Зона низких ADC (высокая температура) - используем граничное значение + resistance = res_at_min_adc; + temp = temp_at_min_adc; + } else if (adc >= max_valid_adc) { + // Зона высоких ADC (низкая температура) - используем граничное значение + resistance = res_at_max_adc; + temp = temp_at_max_adc; + } else { + // В рабочем диапазоне - вычисляем нормально + resistance = calculate_resistance(adc, r1); + temp = get_temperature_from_adc_with_table(adc, use_alg, table_type, r1); + } + + fast_table[i].adc_value = adc; + fast_table[i].temp_c = (int16_t)(temp * 10.0f); + fast_table[i].resistance_ohm = resistance; + fast_table[i].table_type = table_type; + + prev_adc = adc; + } + + // Устанавливаем флаг инициализации + if (table_type == TABLE_DUCT) { + g_fast_tables.duct_initialized = true; + } else if (table_type == TABLE_INCAR) { + g_fast_tables.incar_initialized = true; + } else { + g_fast_tables.ambient_initialized = true; + } +} + +// Инициализация таблицы Duct +void init_duct_table(float r1, eAlg use_alg) { + init_fast_lookup_table(TABLE_DUCT, r1, use_alg); +} + +// Инициализация таблицы Incar +void init_incar_table(float r1, eAlg use_alg) { + init_fast_lookup_table(TABLE_INCAR, r1, use_alg); +} + +// Инициализация таблицы Ambient +void init_ambient_table(float r1, eAlg use_alg) { + init_fast_lookup_table(TABLE_AMBIENT, r1, use_alg); +} + +// Инициализация всех трех таблиц +void init_all_tables(float r1_duct, float r1_incar, float r1_ambient, eAlg use_alg) { + init_fast_lookup_table(TABLE_DUCT, r1_duct, use_alg); + init_fast_lookup_table(TABLE_INCAR, r1_incar, use_alg); + init_fast_lookup_table(TABLE_AMBIENT, r1_ambient, use_alg); +} + +// Установка активной конфигурации +void set_active_config(eNtcTable table_type, float r1) { + active_config.table_type = table_type; + active_config.r1 = r1; + + uint16_t table_size; + get_table_by_type(table_type, &table_size, &active_config.start_temp, &active_config.end_temp); + active_config.table_size = table_size; +} + +// Получение активной конфигурации +const ntc_config_t* get_active_config(void) { + return &active_config; +} + +// Получение таблиц быстрого доступа +const fast_lookup_tables_t* get_fast_tables(void) { + return &g_fast_tables; +} + +// Быстрая функция для конкретной таблицы +int16_t get_temperature_log_fast_for_table(uint16_t adc_value, eNtcTable table_type) { + if (!is_table_initialized(table_type)) { + // Если таблица не инициализирована, используем обычный расчет + float r1 = (table_type == TABLE_DUCT) ? g_fast_tables.duct_r1 : + ((table_type == TABLE_INCAR) ? g_fast_tables.incar_r1 : g_fast_tables.ambient_r1); + float temp = get_temperature_from_adc_with_table(adc_value, ALG_STEINHART, table_type, r1); + return (int16_t)(temp * 10.0f); + } + + adc_temp_lookup* fast_table = get_fast_table_by_type(table_type); + + // Простой линейный поиск (так как таблица небольшая - 4096 элементов) + for (uint16_t i = 0; i < TABLE_SIZE_LOOKUP - 1; i++) { + if (adc_value >= fast_table[i].adc_value && adc_value <= fast_table[i + 1].adc_value) { + // Линейная интерполяция + uint16_t adc1 = fast_table[i].adc_value; + uint16_t adc2 = fast_table[i + 1].adc_value; + int16_t temp1 = fast_table[i].temp_c; + int16_t temp2 = fast_table[i + 1].temp_c; + + if (adc2 == adc1) { + return temp1; + } + + return temp1 + ((int32_t)(temp2 - temp1) * (adc_value - adc1)) / (adc2 - adc1); + } + } + + // Если не нашли, возвращаем ближайшее значение + if (adc_value <= fast_table[0].adc_value) { + return fast_table[0].temp_c; + } else { + return fast_table[TABLE_SIZE_LOOKUP - 1].temp_c; + } +} + +// Быстрые функции с использованием активной таблицы +int16_t get_temperature_log_fast(uint16_t adc_value) { + return get_temperature_log_fast_for_table(adc_value, active_config.table_type); +} + +// Альтернативная простая версия +int16_t get_temperature_linear_fast(uint16_t adc_value) { + return get_temperature_log_fast_for_table(adc_value, active_config.table_type); +} + +// Функция для получения сопротивления из температуры для конкретной таблицы +float get_resistance_log_fast_for_table(int16_t temperature_c10, eNtcTable table_type) { + if (!is_table_initialized(table_type)) { + return 0.0f; + } + + adc_temp_lookup* fast_table = get_fast_table_by_type(table_type); + + // Защита от выхода за границы + if (temperature_c10 >= fast_table[0].temp_c) { + return fast_table[0].resistance_ohm; + } + if (temperature_c10 <= fast_table[TABLE_SIZE_LOOKUP - 1].temp_c) { + return fast_table[TABLE_SIZE_LOOKUP - 1].resistance_ohm; + } + + // Бинарный поиск интервала по температуре + int left = 0; + int right = TABLE_SIZE_LOOKUP - 1; + + while (left <= right) { + int mid = left + (right - left) / 2; + + if (temperature_c10 <= fast_table[mid].temp_c && + temperature_c10 >= fast_table[mid + 1].temp_c) { + // Нашли интервал + int16_t temp_high = fast_table[mid].temp_c; + int16_t temp_low = fast_table[mid + 1].temp_c; + float res_high = fast_table[mid].resistance_ohm; + float res_low = fast_table[mid + 1].resistance_ohm; + + if (temp_high == temp_low) { + return res_high; + } + + // Интерполяция в логарифмическом масштабе + float log_res_high = logf(res_high); + float log_res_low = logf(res_low); + float log_res = log_res_high + (log_res_low - log_res_high) * + (float)(temp_high - temperature_c10) / (float)(temp_high - temp_low); + + return expf(log_res); + } + + if (temperature_c10 > fast_table[mid].temp_c) { + right = mid - 1; + } else { + left = mid + 1; + } + } + + return fast_table[TABLE_SIZE_LOOKUP - 1].resistance_ohm; +} + +// Функция для получения сопротивления из температуры (обратное преобразование) +float get_resistance_log_fast(int16_t temperature_c10) { + return get_resistance_log_fast_for_table(temperature_c10, active_config.table_type); +} + +// Упрощенная версия с линейным поиском +float get_resistance_fast_simple(int16_t temperature_c10) { + return get_resistance_log_fast_for_table(temperature_c10, active_config.table_type); +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_ADC_TEMP/ADC_Temp.h b/MODULES/HVAC_M7_ADC_TEMP/ADC_Temp.h new file mode 100644 index 0000000..95f8d6d --- /dev/null +++ b/MODULES/HVAC_M7_ADC_TEMP/ADC_Temp.h @@ -0,0 +1,97 @@ +// +// Created by cfif on 04.12.2025. +// + +#ifndef MDF_ADC_TEMP_KST45_14_2_H +#define MDF_ADC_TEMP_KST45_14_2_H + +#include +#include "stdbool.h" + +// Типы таблиц NTC +typedef enum { + TABLE_DUCT = 0, // Таблица из документа KST45 (Duct) + TABLE_INCAR = 1, // Таблица из документа Incar + TABLE_AMBIENT = 2, // Таблица для NTC 10 кОм (Ambient) + TABLE_NONE = 0xFF // Таблица не задана +} eNtcTable; + +// Алгоритмы расчёта температуры +typedef enum { + ALG_STEINHART = 0, + ALG_STEINHART_FULL = 1, + ALG_LINEAR = 2 +} eAlg; + +// Константы +#define ADC_MAX 4095.0f // 12-битный АЦП + +// Параметры Steinhart-Hart для термистора (общие для всех таблиц) +#define koef_A 0.001741624168166423 +#define koef_B 0.00017003940268680147 +#define koef_C 0.0000004890545443703666 + +// Размеры таблиц +#define TABLE_SIZE_DUCT 26 +#define TABLE_SIZE_INCAR 38 +#define TABLE_SIZE_AMBIENT 39 +#define TABLE_SIZE_LOOKUP 1024 + +// Предварительно вычисленная таблица для быстрого доступа для каждой таблицы +typedef struct { + uint16_t adc_value; // Значение АЦП + int16_t temp_c; // Температура в °C * 10 (для фиксированной точки) + float resistance_ohm; // Сопротивление в Ом, соответствующее значению АЦП + eNtcTable table_type; // Тип таблицы, для которой вычислены данные +} adc_temp_lookup; + +// Структура конфигурации для NTC +typedef struct { + eNtcTable table_type; // Тип используемой таблицы + float r1; // Сопротивление делителя напряжения (Ом) + int16_t start_temp; // Начальная температура таблицы (°C) + int16_t end_temp; // Конечная температура таблицы (°C) + uint16_t table_size; // Размер таблицы +} ntc_config_t; + +// Структура для хранения таблиц быстрого доступа для каждой конфигурации +typedef struct { + adc_temp_lookup duct[TABLE_SIZE_LOOKUP]; + adc_temp_lookup incar[TABLE_SIZE_LOOKUP]; + adc_temp_lookup ambient[TABLE_SIZE_LOOKUP]; + bool duct_initialized; + bool incar_initialized; + bool ambient_initialized; + float duct_r1; + float incar_r1; + float ambient_r1; +} fast_lookup_tables_t; + +// Глобальная структура для доступа к таблицам +extern fast_lookup_tables_t g_fast_tables; + +// Функции инициализации и конфигурации +void init_fast_lookup_table(eNtcTable table_type, float r1, eAlg use_alg); +void init_duct_table(float r1, eAlg use_alg); +void init_incar_table(float r1, eAlg use_alg); +void init_ambient_table(float r1, eAlg use_alg); +void init_all_tables(float r1_duct, float r1_incar, float r1_ambient, eAlg use_alg); +void set_active_config(eNtcTable table_type, float r1); +const ntc_config_t* get_active_config(void); +const fast_lookup_tables_t* get_fast_tables(void); + +// Основные функции получения температуры +float get_temperature_from_adc(uint16_t adc_value, eAlg alg); +float get_temperature_from_adc_with_table(uint16_t adc_value, eAlg alg, eNtcTable table_type, float r1); +float get_resistance_from_adc(uint16_t adc_value); +float get_resistance_from_adc_with_table(uint16_t adc_value, eNtcTable table_type, float r1); + +// Быстрые функции с использованием предварительно вычисленной таблицы +int16_t get_temperature_log_fast(uint16_t adc_value); +int16_t get_temperature_log_fast_for_table(uint16_t adc_value, eNtcTable table_type); +int16_t get_temperature_linear_fast(uint16_t adc_value); +float get_resistance_log_fast(int16_t temperature_c10); +float get_resistance_log_fast_for_table(int16_t temperature_c10, eNtcTable table_type); +float get_resistance_fast_simple(int16_t temperature_c10); + +#endif //MDF_ADC_TEMP_KST45_14_2_H \ No newline at end of file diff --git a/MODULES/HVAC_M7_ADC_TEMP/ADC_Temp_Fast.c b/MODULES/HVAC_M7_ADC_TEMP/ADC_Temp_Fast.c new file mode 100644 index 0000000..611d1e1 --- /dev/null +++ b/MODULES/HVAC_M7_ADC_TEMP/ADC_Temp_Fast.c @@ -0,0 +1,4190 @@ +// +// Created by cfif on 06.05.2026. +// +#include "ADC_Temp_Fast.h" +//const TablePoint temperature_table_duct_KST45_table_3000[]; +//const TablePoint temperature_table_duct_KST45_table_20000[]; +//const TablePoint incar_lookup_table[]; +//const TablePoint ambient_lookup_table[]; + +const TablePoint temperature_table_duct_KST45_table_3000[] = { + {0, 850, 321.70f}, + {3, 850, 321.70f}, + {7, 850, 321.70f}, + {11, 850, 321.70f}, + {15, 850, 321.70f}, + {19, 850, 321.70f}, + {23, 850, 321.70f}, + {27, 850, 321.70f}, + {31, 850, 321.70f}, + {35, 850, 321.70f}, + {39, 850, 321.70f}, + {43, 850, 321.70f}, + {47, 850, 321.70f}, + {51, 850, 321.70f}, + {55, 850, 321.70f}, + {59, 850, 321.70f}, + {63, 850, 321.70f}, + {67, 850, 321.70f}, + {71, 850, 321.70f}, + {75, 850, 321.70f}, + {79, 850, 321.70f}, + {83, 850, 321.70f}, + {87, 850, 321.70f}, + {91, 850, 321.70f}, + {95, 850, 321.70f}, + {99, 850, 321.70f}, + {103, 850, 321.70f}, + {107, 850, 321.70f}, + {111, 850, 321.70f}, + {115, 850, 321.70f}, + {119, 850, 321.70f}, + {123, 850, 321.70f}, + {127, 850, 321.70f}, + {131, 850, 321.70f}, + {135, 850, 321.70f}, + {139, 850, 321.70f}, + {143, 850, 321.70f}, + {147, 850, 321.70f}, + {151, 850, 321.70f}, + {155, 850, 321.70f}, + {159, 850, 321.70f}, + {163, 850, 321.70f}, + {167, 850, 321.70f}, + {171, 850, 321.70f}, + {175, 850, 321.70f}, + {179, 850, 321.70f}, + {183, 850, 321.70f}, + {187, 850, 321.70f}, + {191, 850, 321.70f}, + {195, 850, 321.70f}, + {199, 850, 321.70f}, + {203, 850, 321.70f}, + {207, 850, 321.70f}, + {211, 850, 321.70f}, + {215, 850, 321.70f}, + {219, 850, 321.70f}, + {223, 850, 321.70f}, + {227, 850, 321.70f}, + {231, 850, 321.70f}, + {235, 850, 321.70f}, + {239, 850, 321.70f}, + {243, 850, 321.70f}, + {247, 850, 321.70f}, + {251, 850, 321.70f}, + {255, 850, 321.70f}, + {259, 850, 321.70f}, + {263, 850, 321.70f}, + {267, 850, 321.70f}, + {271, 850, 321.70f}, + {275, 850, 321.70f}, + {279, 850, 321.70f}, + {283, 850, 321.70f}, + {287, 850, 321.70f}, + {291, 850, 321.70f}, + {295, 850, 321.70f}, + {299, 850, 321.70f}, + {303, 850, 321.70f}, + {307, 850, 321.70f}, + {311, 850, 321.70f}, + {315, 850, 321.70f}, + {319, 850, 321.70f}, + {323, 850, 321.70f}, + {327, 850, 321.70f}, + {331, 850, 321.70f}, + {335, 850, 321.70f}, + {339, 850, 321.70f}, + {343, 850, 321.70f}, + {347, 850, 321.70f}, + {351, 850, 321.70f}, + {355, 850, 321.70f}, + {359, 850, 321.70f}, + {363, 850, 321.70f}, + {367, 850, 321.70f}, + {371, 850, 321.70f}, + {375, 850, 321.70f}, + {379, 850, 321.70f}, + {383, 850, 321.70f}, + {387, 850, 321.70f}, + {391, 850, 321.70f}, + {395, 848, 323.13f}, + {399, 845, 326.76f}, + {403, 841, 330.40f}, + {407, 838, 334.04f}, + {411, 834, 337.69f}, + {415, 831, 341.35f}, + {419, 827, 345.02f}, + {423, 824, 348.70f}, + {427, 821, 352.38f}, + {431, 818, 356.08f}, + {435, 814, 359.78f}, + {439, 811, 363.49f}, + {443, 808, 367.20f}, + {447, 805, 370.93f}, + {451, 802, 374.66f}, + {455, 799, 378.41f}, + {459, 796, 382.16f}, + {463, 793, 385.91f}, + {467, 790, 389.68f}, + {471, 787, 393.46f}, + {475, 784, 397.24f}, + {479, 781, 401.03f}, + {483, 778, 404.83f}, + {487, 775, 408.64f}, + {491, 772, 412.46f}, + {495, 769, 416.29f}, + {499, 767, 420.12f}, + {503, 764, 423.97f}, + {507, 761, 427.82f}, + {511, 758, 431.68f}, + {515, 756, 435.55f}, + {519, 753, 439.43f}, + {523, 750, 443.32f}, + {527, 748, 447.21f}, + {531, 745, 451.12f}, + {535, 742, 455.03f}, + {539, 740, 458.95f}, + {543, 737, 462.88f}, + {547, 735, 466.82f}, + {551, 732, 470.77f}, + {555, 730, 474.73f}, + {559, 727, 478.70f}, + {563, 725, 482.68f}, + {567, 722, 486.66f}, + {571, 720, 490.66f}, + {575, 717, 494.66f}, + {579, 715, 498.67f}, + {583, 713, 502.70f}, + {587, 710, 506.73f}, + {591, 708, 510.77f}, + {595, 706, 514.82f}, + {599, 703, 518.88f}, + {603, 701, 522.95f}, + {607, 699, 527.03f}, + {611, 696, 531.11f}, + {615, 694, 535.21f}, + {619, 692, 539.32f}, + {623, 690, 543.43f}, + {627, 688, 547.56f}, + {631, 685, 551.70f}, + {635, 683, 555.84f}, + {639, 681, 560.00f}, + {643, 679, 564.16f}, + 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9496.12f}, + {3091, 5, 9547.59f}, + {3095, 3, 9599.48f}, + {3099, 2, 9651.80f}, + {3103, 1, 9704.56f}, + {3107, 0, 9757.76f}, + {3111, 0, 9811.41f}, + {3115, -1, 9865.50f}, + {3119, -2, 9920.06f}, + {3123, -3, 9975.09f}, + {3127, -4, 10030.58f}, + {3131, -5, 10086.55f}, + {3135, -6, 10143.01f}, + {3139, -7, 10199.95f}, + {3143, -9, 10257.39f}, + {3147, -10, 10315.33f}, + {3151, -11, 10373.78f}, + {3155, -12, 10432.74f}, + {3159, -13, 10492.23f}, + {3163, -14, 10552.24f}, + {3167, -15, 10612.80f}, + {3171, -16, 10673.89f}, + {3175, -17, 10735.54f}, + {3179, -19, 10797.75f}, + {3183, -20, 10860.51f}, + {3187, -21, 10923.86f}, + {3191, -22, 10987.79f}, + {3195, -23, 11052.30f}, + {3199, -24, 11117.42f}, + {3203, -25, 11183.14f}, + {3207, -26, 11249.47f}, + {3211, -28, 11316.43f}, + {3215, -29, 11384.03f}, + {3219, -30, 11452.25f}, + {3223, -31, 11521.14f}, + {3227, -32, 11590.68f}, + {3231, -33, 11660.89f}, + {3235, -34, 11731.78f}, + {3239, -36, 11803.36f}, + {3243, -37, 11875.64f}, + {3247, -38, 11948.63f}, + {3251, -39, 12022.33f}, + {3255, -40, 12096.77f}, + {3259, -42, 12171.95f}, + {3263, -43, 12247.88f}, + {3267, -44, 12324.58f}, + {3271, -45, 12402.05f}, + {3275, -46, 12480.31f}, + {3279, -47, 12559.37f}, + {3283, -49, 12639.24f}, + {3287, -50, 12719.93f}, + {3291, -51, 12801.46f}, + {3295, -52, 12883.84f}, + {3299, -54, 12967.09f}, + {3303, -55, 13051.21f}, + {3307, -56, 13136.22f}, + {3311, -57, 13222.14f}, + {3315, -58, 13308.98f}, + {3319, -60, 13396.75f}, + {3323, -61, 13485.47f}, + {3327, -62, 13575.16f}, + {3331, -63, 13665.83f}, + {3335, -65, 13757.49f}, + {3339, -66, 13850.17f}, + {3343, -67, 13943.89f}, + {3347, -68, 14038.65f}, + {3351, -70, 14134.47f}, + {3355, -71, 14231.38f}, + {3359, -72, 14329.39f}, + {3363, -74, 14428.52f}, + {3367, -75, 14528.80f}, + {3371, -76, 14630.23f}, + {3375, -77, 14732.84f}, + {3379, -79, 14836.66f}, + {3383, -80, 14941.70f}, + {3387, -81, 15047.99f}, + {3391, -83, 15155.53f}, + {3395, -84, 15264.38f}, + {3399, -85, 15374.52f}, + {3403, -87, 15486.02f}, + {3407, -88, 15598.87f}, + {3411, -89, 15713.10f}, + {3415, -91, 15828.75f}, + {3419, -92, 15945.83f}, + {3423, -93, 16064.39f}, + {3427, -95, 16184.43f}, + {3431, -96, 16306.01f}, + {3435, -98, 16429.12f}, + {3439, -99, 16553.82f}, + {3443, -100, 16680.12f}, + {3447, -102, 16808.07f}, + {3451, -103, 16937.70f}, + {3455, -105, 17069.03f}, + {3459, -106, 17202.11f}, + {3463, -108, 17336.96f}, + {3467, -109, 17473.63f}, + {3471, -110, 17612.14f}, + {3475, -112, 17752.53f}, + {3479, -113, 17894.87f}, + {3483, -115, 18039.15f}, + {3487, -116, 18185.46f}, + {3491, -118, 18333.80f}, + {3495, -119, 18484.24f}, + {3499, -121, 18636.81f}, + {3503, -122, 18791.58f}, + {3507, -124, 18948.56f}, + {3511, -125, 19107.82f}, + {3515, -127, 19269.43f}, + {3519, -128, 19433.39f}, + {3523, -130, 19599.81f}, + {3527, -131, 19768.70f}, + {3531, -133, 19940.14f}, + {3535, -134, 20114.18f}, + {3539, -136, 20290.89f}, + {3543, -138, 20470.30f}, + {3547, -139, 20652.50f}, + {3551, -141, 20837.57f}, + {3555, -142, 21025.54f}, + {3559, -144, 21216.52f}, + {3563, -146, 21410.54f}, + {3567, -147, 21607.71f}, + {3571, -149, 21808.08f}, + {3575, -151, 22011.75f}, + {3579, -152, 22218.77f}, + {3583, -154, 22429.25f}, + {3587, -156, 22643.30f}, + {3591, -157, 22860.96f}, + {3595, -159, 23082.36f}, + {3599, -161, 23307.57f}, + {3603, -162, 23536.72f}, + {3607, -164, 23769.88f}, + {3611, -166, 24007.19f}, + {3615, -168, 24248.73f}, + {3619, -169, 24494.62f}, + {3623, -171, 24745.02f}, + {3627, -173, 24999.99f}, + {3631, -175, 25259.72f}, + {3635, -177, 25524.29f}, + {3639, -179, 25793.89f}, + {3643, -180, 26068.60f}, + {3647, -182, 26348.60f}, + {3651, -184, 26634.08f}, + {3655, -186, 26925.14f}, + {3659, -188, 27222.01f}, + {3663, -190, 27524.79f}, + {3667, -192, 27833.73f}, + {3671, -194, 28148.96f}, + {3675, -196, 28470.73f}, + {3679, -198, 28799.19f}, + {3683, -200, 29134.57f}, + {3687, -202, 29477.14f}, + {3691, -204, 29827.05f}, + {3695, -206, 30184.63f}, + {3699, -208, 30550.04f}, + {3703, -210, 30923.63f}, + {3707, -212, 31305.59f}, + {3711, -214, 31696.29f}, + {3715, -216, 32095.96f}, + {3719, -218, 32504.93f}, + {3723, -221, 32923.60f}, + {3727, -223, 33352.21f}, + {3731, -225, 33791.22f}, + {3735, -227, 34240.91f}, + {3739, -229, 34701.79f}, + {3743, -232, 35174.16f}, + {3747, -234, 35658.57f}, + {3751, -236, 36155.38f}, + {3755, -239, 36665.12f}, + {3759, -241, 37188.37f}, + {3763, -243, 37725.55f}, + {3767, -246, 38277.35f}, + {3771, -248, 38844.24f}, + {3775, -251, 39426.98f}, + {3779, -253, 40026.12f}, + {3783, -256, 40642.49f}, + {3787, -258, 41276.70f}, + {3791, -261, 41929.63f}, + {3795, -264, 42602.16f}, + {3799, -266, 43295.07f}, + {3803, -269, 44009.43f}, + {3807, -272, 44746.11f}, + {3811, -275, 45506.32f}, + {3815, -277, 46291.05f}, + {3819, -280, 47101.67f}, + {3823, -283, 47939.31f}, + {3827, -286, 48805.44f}, + {3831, -289, 49701.62f}, + {3835, -292, 50629.26f}, + {3839, -295, 51590.25f}, + {3843, -298, 52586.19f}, + {3847, -301, 53619.26f}, + {3851, -304, 54691.34f}, + {3855, -308, 55804.81f}, + {3859, -311, 56962.22f}, + {3863, -314, 58165.99f}, + {3867, -318, 59419.20f}, + {3871, -321, 60724.71f}, + {3875, -325, 62086.14f}, + {3879, -328, 63506.86f}, + {3883, -332, 64991.14f}, + {3887, -336, 66543.02f}, + {3891, -339, 68167.41f}, + {3895, -343, 69869.66f}, + {3899, -347, 71655.16f}, + {3903, -351, 73530.56f}, + {3907, -355, 75502.40f}, + {3911, -359, 77578.76f}, + {3915, -364, 79767.70f}, + {3919, -368, 82079.13f}, + {3923, -373, 84523.12f}, + {3927, -377, 87111.68f}, + {3931, -382, 89858.31f}, + {3935, -387, 92777.34f}, + {3939, -392, 95886.16f}, + {3943, -397, 99203.21f}, + {3947, -400, 100950.00f}, + {3951, -400, 100950.00f}, + {3955, -400, 100950.00f}, + {3959, -400, 100950.00f}, + {3963, -400, 100950.00f}, + {3967, -400, 100950.00f}, + {3971, -400, 100950.00f}, + {3975, -400, 100950.00f}, + {3979, -400, 100950.00f}, + {3983, -400, 100950.00f}, + {3987, -400, 100950.00f}, + {3991, -400, 100950.00f}, + {3995, -400, 100950.00f}, + {3999, -400, 100950.00f}, + {4003, -400, 100950.00f}, + {4007, -400, 100950.00f}, + {4011, -400, 100950.00f}, + {4015, -400, 100950.00f}, + {4019, -400, 100950.00f}, + {4023, -400, 100950.00f}, + {4027, -400, 100950.00f}, + {4031, -400, 100950.00f}, + {4035, -400, 100950.00f}, + {4039, -400, 100950.00f}, + {4043, -400, 100950.00f}, + {4047, -400, 100950.00f}, + {4051, -400, 100950.00f}, + {4055, -400, 100950.00f}, + {4059, -400, 100950.00f}, + {4063, -400, 100950.00f}, + {4067, -400, 100950.00f}, + {4071, -400, 100950.00f}, + {4075, -400, 100950.00f}, + {4079, -400, 100950.00f}, + {4083, -400, 100950.00f}, + {4087, -400, 100950.00f}, + {4091, -400, 100950.00f} +}; + + +const TablePoint temperature_table_duct_KST45_table_20000[] = { + {0, 850, 321.70f}, + {3, 850, 321.70f}, + {7, 850, 321.70f}, + {11, 850, 321.70f}, + {15, 850, 321.70f}, + {19, 850, 321.70f}, + {23, 850, 321.70f}, + {27, 850, 321.70f}, + {31, 850, 321.70f}, + {35, 850, 321.70f}, + {39, 850, 321.70f}, + {43, 850, 321.70f}, + {47, 850, 321.70f}, + {51, 850, 321.70f}, + {55, 850, 321.70f}, + {59, 850, 321.70f}, + {63, 850, 321.70f}, + {67, 836, 335.40f}, + {71, 818, 355.78f}, + {75, 800, 376.20f}, + {79, 784, 396.66f}, + {83, 769, 417.17f}, + {87, 754, 437.71f}, + {91, 740, 458.30f}, + {95, 727, 478.92f}, + {99, 714, 499.59f}, + {103, 702, 520.30f}, + {107, 691, 541.05f}, + {111, 680, 561.85f}, + {115, 670, 582.69f}, + {119, 659, 603.56f}, + {123, 650, 624.49f}, + {127, 640, 645.45f}, + {131, 631, 666.46f}, + {135, 622, 687.51f}, + {139, 614, 708.60f}, + {143, 606, 729.73f}, + {147, 598, 750.91f}, + {151, 590, 772.13f}, + {155, 583, 793.40f}, + {159, 575, 814.71f}, + {163, 568, 836.06f}, + {167, 561, 857.46f}, + {171, 555, 878.90f}, + {175, 548, 900.38f}, + {179, 542, 921.91f}, + {183, 536, 943.48f}, + {187, 530, 965.10f}, + {191, 524, 986.76f}, + {195, 518, 1008.47f}, + {199, 512, 1030.22f}, + {203, 507, 1052.02f}, + {207, 501, 1073.86f}, + {211, 496, 1095.75f}, + {215, 491, 1117.68f}, + {219, 486, 1139.66f}, + {223, 481, 1161.69f}, + {227, 476, 1183.76f}, + {231, 471, 1205.88f}, + {235, 466, 1228.04f}, + {239, 462, 1250.25f}, + {243, 457, 1272.50f}, + {247, 453, 1294.81f}, + {251, 448, 1317.16f}, + {255, 444, 1339.55f}, + {259, 440, 1362.00f}, + {263, 436, 1384.49f}, + {267, 431, 1407.03f}, + {271, 427, 1429.61f}, + {275, 423, 1452.24f}, + {279, 420, 1474.93f}, + {283, 416, 1497.66f}, + {287, 412, 1520.43f}, + {291, 408, 1543.26f}, + {295, 405, 1566.13f}, + {299, 401, 1589.06f}, + {303, 397, 1612.03f}, + {307, 394, 1635.05f}, + {311, 390, 1658.12f}, + {315, 387, 1681.24f}, + {319, 384, 1704.41f}, + {323, 380, 1727.62f}, + {327, 377, 1750.89f}, + {331, 374, 1774.21f}, + {335, 370, 1797.58f}, + {339, 367, 1820.99f}, + {343, 364, 1844.46f}, + {347, 361, 1867.98f}, + {351, 358, 1891.55f}, + {355, 355, 1915.17f}, + {359, 352, 1938.84f}, + {363, 349, 1962.57f}, + {367, 346, 1986.34f}, + {371, 343, 2010.16f}, + {375, 340, 2034.04f}, + {379, 338, 2057.97f}, + {383, 335, 2081.95f}, + {387, 332, 2105.98f}, + {391, 329, 2130.07f}, + {395, 327, 2154.21f}, + {399, 324, 2178.40f}, + {403, 321, 2202.64f}, + {407, 319, 2226.94f}, + {411, 316, 2251.29f}, + {415, 314, 2275.69f}, + {419, 311, 2300.15f}, + {423, 309, 2324.66f}, + {427, 306, 2349.23f}, + {431, 304, 2373.84f}, + {435, 301, 2398.52f}, + {439, 299, 2423.25f}, + {443, 297, 2448.03f}, + {447, 294, 2472.86f}, + {451, 292, 2497.76f}, + {455, 289, 2522.70f}, + {459, 287, 2547.71f}, + {463, 285, 2572.77f}, + {467, 283, 2597.88f}, + {471, 280, 2623.05f}, + {475, 278, 2648.28f}, + {479, 276, 2673.56f}, + {483, 274, 2698.90f}, + {487, 272, 2724.29f}, + {491, 269, 2749.75f}, + {495, 267, 2775.25f}, + {499, 265, 2800.82f}, + {503, 263, 2826.45f}, + {507, 261, 2852.13f}, + {511, 259, 2877.87f}, + {515, 257, 2903.67f}, + {519, 255, 2929.52f}, + {523, 253, 2955.44f}, + {527, 251, 2981.41f}, + {531, 249, 3007.44f}, + {535, 247, 3033.53f}, + {539, 245, 3059.68f}, + {543, 243, 3085.89f}, + {547, 241, 3112.16f}, + {551, 239, 3138.49f}, + {555, 237, 3164.88f}, + {559, 235, 3191.33f}, + {563, 234, 3217.84f}, + {567, 232, 3244.41f}, + {571, 230, 3271.04f}, + {575, 228, 3297.74f}, + {579, 226, 3324.49f}, + {583, 224, 3351.31f}, + {587, 223, 3378.18f}, + {591, 221, 3405.12f}, + {595, 219, 3432.12f}, + {599, 217, 3459.19f}, + {603, 216, 3486.31f}, + {607, 214, 3513.50f}, + {611, 212, 3540.76f}, + {615, 210, 3568.07f}, + {619, 209, 3595.45f}, + {623, 207, 3622.89f}, + {627, 205, 3650.40f}, + {631, 204, 3677.97f}, + {635, 202, 3705.61f}, + {639, 200, 3733.31f}, + {643, 199, 3761.07f}, + {647, 197, 3788.90f}, + {651, 195, 3816.79f}, + {655, 194, 3844.75f}, + {659, 192, 3872.78f}, + {663, 191, 3900.87f}, + {667, 189, 3929.03f}, + {671, 187, 3957.25f}, + {675, 186, 3985.55f}, + {679, 184, 4013.90f}, + {683, 183, 4042.33f}, + {687, 181, 4070.82f}, + {691, 180, 4099.38f}, + {695, 178, 4128.01f}, + {699, 177, 4156.71f}, + {703, 175, 4185.47f}, + {707, 174, 4214.30f}, + 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-314, 58177.13f}, + {3027, -315, 58479.20f}, + {3031, -316, 58783.60f}, + {3035, -317, 59090.38f}, + {3039, -318, 59399.56f}, + {3043, -318, 59711.16f}, + {3047, -319, 60025.21f}, + {3051, -320, 60341.75f}, + {3055, -321, 60660.82f}, + {3059, -322, 60982.42f}, + {3063, -323, 61306.60f}, + {3067, -323, 61633.38f}, + {3071, -324, 61962.80f}, + {3075, -325, 62294.89f}, + {3079, -326, 62629.67f}, + {3083, -327, 62967.20f}, + {3087, -328, 63307.49f}, + {3091, -329, 63650.59f}, + {3095, -329, 63996.52f}, + {3099, -330, 64345.34f}, + {3103, -331, 64697.05f}, + {3107, -332, 65051.72f}, + {3111, -333, 65409.37f}, + {3115, -334, 65770.02f}, + {3119, -335, 66133.75f}, + {3123, -335, 66500.57f}, + {3127, -336, 66870.54f}, + {3131, -337, 67243.68f}, + {3135, -338, 67620.04f}, + {3139, -339, 67999.66f}, + {3143, -340, 68382.59f}, + {3147, -341, 68768.84f}, + {3151, -342, 69158.50f}, + {3155, -342, 69551.60f}, + {3159, -343, 69948.18f}, + {3163, -344, 70348.29f}, + {3167, -345, 70751.98f}, + {3171, -346, 71159.29f}, + {3175, -347, 71570.27f}, + {3179, -348, 71984.98f}, + {3183, -349, 72403.43f}, + {3187, -350, 72825.73f}, + {3191, -351, 73251.91f}, + {3195, -351, 73682.02f}, + {3199, -352, 74116.12f}, + {3203, -353, 74554.27f}, + {3207, -354, 74996.50f}, + {3211, -355, 75442.89f}, + {3215, -356, 75893.50f}, + {3219, -357, 76348.36f}, + {3223, -358, 76807.58f}, + {3227, -359, 77271.20f}, + {3231, -360, 77739.28f}, + {3235, -361, 78211.88f}, + {3239, -362, 78689.09f}, + {3243, -363, 79170.95f}, + {3247, -364, 79657.54f}, + {3251, -364, 80148.90f}, + {3255, -365, 80645.15f}, + {3259, -366, 81146.35f}, + {3263, -367, 81652.56f}, + {3267, -368, 82163.88f}, + {3271, -369, 82680.35f}, + {3275, -370, 83202.08f}, + {3279, -371, 83729.13f}, + {3283, -372, 84261.60f}, + {3287, -373, 84799.54f}, + {3291, -374, 85343.08f}, + {3295, -375, 85892.29f}, + {3299, -376, 86447.25f}, + {3303, -377, 87008.06f}, + {3307, -378, 87574.81f}, + {3311, -379, 88147.60f}, + {3315, -380, 88726.52f}, + {3319, -381, 89311.68f}, + {3323, -382, 89903.13f}, + {3327, -383, 90501.05f}, + {3331, -384, 91105.52f}, + {3335, -385, 91716.62f}, + {3339, -386, 92334.50f}, + {3343, -387, 92959.24f}, + {3347, -388, 93590.98f}, + {3351, -389, 94229.81f}, + {3355, -390, 94875.84f}, + {3359, -391, 95529.29f}, + {3363, -392, 96190.14f}, + {3367, -393, 96858.67f}, + {3371, -394, 97534.87f}, + {3375, -395, 98218.94f}, + {3379, -396, 98911.08f}, + {3383, -398, 99611.31f}, + {3387, -399, 100319.90f}, + {3391, -400, 100950.00f}, + {3395, -400, 100950.00f}, + {3399, -400, 100950.00f}, + {3403, -400, 100950.00f}, + {3407, -400, 100950.00f}, + {3411, -400, 100950.00f}, + {3415, -400, 100950.00f}, + {3419, -400, 100950.00f}, + {3423, -400, 100950.00f}, + {3427, -400, 100950.00f}, + {3431, -400, 100950.00f}, + {3435, -400, 100950.00f}, + {3439, -400, 100950.00f}, + {3443, -400, 100950.00f}, + {3447, -400, 100950.00f}, + {3451, -400, 100950.00f}, + {3455, -400, 100950.00f}, + {3459, -400, 100950.00f}, + {3463, -400, 100950.00f}, + {3467, -400, 100950.00f}, + {3471, -400, 100950.00f}, + {3475, -400, 100950.00f}, + {3479, -400, 100950.00f}, + {3483, -400, 100950.00f}, + {3487, -400, 100950.00f}, + {3491, -400, 100950.00f}, + {3495, -400, 100950.00f}, + {3499, -400, 100950.00f}, + {3503, -400, 100950.00f}, + {3507, -400, 100950.00f}, + {3511, -400, 100950.00f}, + {3515, -400, 100950.00f}, + {3519, -400, 100950.00f}, + {3523, -400, 100950.00f}, + {3527, -400, 100950.00f}, + {3531, -400, 100950.00f}, + {3535, -400, 100950.00f}, + {3539, -400, 100950.00f}, + {3543, -400, 100950.00f}, + {3547, -400, 100950.00f}, + {3551, -400, 100950.00f}, + {3555, -400, 100950.00f}, + {3559, -400, 100950.00f}, + {3563, -400, 100950.00f}, + {3567, -400, 100950.00f}, + {3571, -400, 100950.00f}, + {3575, -400, 100950.00f}, + {3579, -400, 100950.00f}, + {3583, -400, 100950.00f}, + {3587, -400, 100950.00f}, + {3591, -400, 100950.00f}, + {3595, -400, 100950.00f}, + {3599, -400, 100950.00f}, + {3603, -400, 100950.00f}, + {3607, -400, 100950.00f}, + {3611, -400, 100950.00f}, + {3615, -400, 100950.00f}, + {3619, -400, 100950.00f}, + {3623, -400, 100950.00f}, + {3627, -400, 100950.00f}, + {3631, -400, 100950.00f}, + {3635, -400, 100950.00f}, + {3639, -400, 100950.00f}, + {3643, -400, 100950.00f}, + {3647, -400, 100950.00f}, + {3651, -400, 100950.00f}, + {3655, -400, 100950.00f}, + {3659, -400, 100950.00f}, + {3663, -400, 100950.00f}, + {3667, -400, 100950.00f}, + {3671, -400, 100950.00f}, + {3675, -400, 100950.00f}, + {3679, -400, 100950.00f}, + {3683, -400, 100950.00f}, + {3687, -400, 100950.00f}, + {3691, -400, 100950.00f}, + {3695, -400, 100950.00f}, + {3699, -400, 100950.00f}, + {3703, -400, 100950.00f}, + {3707, -400, 100950.00f}, + {3711, -400, 100950.00f}, + {3715, -400, 100950.00f}, + {3719, -400, 100950.00f}, + {3723, -400, 100950.00f}, + {3727, -400, 100950.00f}, + {3731, -400, 100950.00f}, + {3735, -400, 100950.00f}, + {3739, -400, 100950.00f}, + {3743, -400, 100950.00f}, + {3747, -400, 100950.00f}, + {3751, -400, 100950.00f}, + {3755, -400, 100950.00f}, + {3759, -400, 100950.00f}, + {3763, -400, 100950.00f}, + {3767, -400, 100950.00f}, + {3771, -400, 100950.00f}, + {3775, -400, 100950.00f}, + {3779, -400, 100950.00f}, + {3783, -400, 100950.00f}, + {3787, -400, 100950.00f}, + {3791, -400, 100950.00f}, + {3795, -400, 100950.00f}, + {3799, -400, 100950.00f}, + {3803, -400, 100950.00f}, + {3807, -400, 100950.00f}, + {3811, -400, 100950.00f}, + {3815, -400, 100950.00f}, + {3819, -400, 100950.00f}, + {3823, -400, 100950.00f}, + {3827, -400, 100950.00f}, + {3831, -400, 100950.00f}, + {3835, -400, 100950.00f}, + {3839, -400, 100950.00f}, + {3843, -400, 100950.00f}, + {3847, -400, 100950.00f}, + {3851, -400, 100950.00f}, + {3855, -400, 100950.00f}, + {3859, -400, 100950.00f}, + {3863, -400, 100950.00f}, + {3867, -400, 100950.00f}, + {3871, -400, 100950.00f}, + {3875, -400, 100950.00f}, + {3879, -400, 100950.00f}, + {3883, -400, 100950.00f}, + {3887, -400, 100950.00f}, + {3891, -400, 100950.00f}, + {3895, -400, 100950.00f}, + {3899, -400, 100950.00f}, + {3903, -400, 100950.00f}, + {3907, -400, 100950.00f}, + {3911, -400, 100950.00f}, + {3915, -400, 100950.00f}, + {3919, -400, 100950.00f}, + {3923, -400, 100950.00f}, + {3927, -400, 100950.00f}, + {3931, -400, 100950.00f}, + {3935, -400, 100950.00f}, + {3939, -400, 100950.00f}, + {3943, -400, 100950.00f}, + {3947, -400, 100950.00f}, + {3951, -400, 100950.00f}, + {3955, -400, 100950.00f}, + {3959, -400, 100950.00f}, + {3963, -400, 100950.00f}, + {3967, -400, 100950.00f}, + {3971, -400, 100950.00f}, + {3975, -400, 100950.00f}, + {3979, -400, 100950.00f}, + {3983, -400, 100950.00f}, + {3987, -400, 100950.00f}, + {3991, -400, 100950.00f}, + {3995, -400, 100950.00f}, + {3999, -400, 100950.00f}, + {4003, -400, 100950.00f}, + {4007, -400, 100950.00f}, + {4011, -400, 100950.00f}, + {4015, -400, 100950.00f}, + {4019, -400, 100950.00f}, + {4023, -400, 100950.00f}, + {4027, -400, 100950.00f}, + {4031, -400, 100950.00f}, + {4035, -400, 100950.00f}, + {4039, -400, 100950.00f}, + {4043, -400, 100950.00f}, + {4047, -400, 100950.00f}, + {4051, -400, 100950.00f}, + {4055, -400, 100950.00f}, + {4059, -400, 100950.00f}, + {4063, -400, 100950.00f}, + {4067, -400, 100950.00f}, + {4071, -400, 100950.00f}, + {4075, -400, 100950.00f}, + {4079, -400, 100950.00f}, + {4083, -400, 100950.00f}, + {4087, -400, 100950.00f}, + {4091, -400, 100950.00f} +}; + +const TablePoint incar_lookup_table[] = { + {0, 850, 283.00f}, + {3, 850, 283.00f}, + {7, 850, 283.00f}, + {11, 850, 283.00f}, + {15, 850, 283.00f}, + {19, 850, 283.00f}, + {23, 850, 283.00f}, + {27, 850, 283.00f}, + {31, 850, 283.00f}, + {35, 850, 283.00f}, + {39, 850, 283.00f}, + {43, 850, 283.00f}, + {47, 850, 283.00f}, + {51, 850, 283.00f}, + {55, 850, 283.00f}, + {59, 837, 294.76f}, + {63, 816, 315.06f}, + {67, 797, 335.40f}, + {71, 780, 355.78f}, + {75, 763, 376.20f}, + {79, 748, 396.66f}, + {83, 733, 417.17f}, + {87, 719, 437.71f}, + {91, 706, 458.30f}, + {95, 693, 478.92f}, + {99, 681, 499.59f}, + {103, 670, 520.30f}, + {107, 659, 541.05f}, + {111, 648, 561.85f}, + {115, 638, 582.69f}, + {119, 628, 603.56f}, + {123, 619, 624.49f}, + {127, 610, 645.45f}, + {131, 601, 666.46f}, + {135, 593, 687.51f}, + {139, 584, 708.60f}, + {143, 577, 729.73f}, + {147, 569, 750.91f}, + {151, 562, 772.13f}, + {155, 555, 793.40f}, + {159, 548, 814.71f}, + {163, 541, 836.06f}, + {167, 534, 857.46f}, + {171, 528, 878.90f}, + {175, 521, 900.38f}, + {179, 515, 921.91f}, + {183, 509, 943.48f}, + {187, 503, 965.10f}, + {191, 498, 986.76f}, + {195, 492, 1008.47f}, + {199, 487, 1030.22f}, + {203, 481, 1052.02f}, + {207, 476, 1073.86f}, + {211, 471, 1095.75f}, + {215, 466, 1117.68f}, + {219, 461, 1139.66f}, + {223, 457, 1161.69f}, + {227, 452, 1183.76f}, + {231, 447, 1205.88f}, + {235, 443, 1228.04f}, + {239, 438, 1250.25f}, + {243, 434, 1272.50f}, + {247, 430, 1294.81f}, + {251, 425, 1317.16f}, + {255, 421, 1339.55f}, + {259, 417, 1362.00f}, + {263, 413, 1384.49f}, + {267, 409, 1407.03f}, + {271, 405, 1429.61f}, + {275, 401, 1452.24f}, + {279, 398, 1474.93f}, + {283, 394, 1497.66f}, + {287, 390, 1520.43f}, + {291, 387, 1543.26f}, + {295, 383, 1566.13f}, + {299, 380, 1589.06f}, + {303, 376, 1612.03f}, + {307, 373, 1635.05f}, + {311, 370, 1658.12f}, + {315, 366, 1681.24f}, + {319, 363, 1704.41f}, + {323, 360, 1727.62f}, + {327, 357, 1750.89f}, + {331, 354, 1774.21f}, + {335, 351, 1797.58f}, + {339, 348, 1820.99f}, + {343, 345, 1844.46f}, + {347, 342, 1867.98f}, + {351, 339, 1891.55f}, + {355, 336, 1915.17f}, + {359, 333, 1938.84f}, + {363, 330, 1962.57f}, + {367, 327, 1986.34f}, + {371, 324, 2010.16f}, + {375, 322, 2034.04f}, + {379, 319, 2057.97f}, + {383, 316, 2081.95f}, + {387, 314, 2105.98f}, + {391, 311, 2130.07f}, + {395, 308, 2154.21f}, + {399, 306, 2178.40f}, + {403, 303, 2202.64f}, + {407, 301, 2226.94f}, + {411, 298, 2251.29f}, + {415, 296, 2275.69f}, + {419, 293, 2300.15f}, + {423, 291, 2324.66f}, + {427, 289, 2349.23f}, + {431, 286, 2373.84f}, + {435, 284, 2398.52f}, + {439, 281, 2423.25f}, + {443, 279, 2448.03f}, + {447, 277, 2472.86f}, + {451, 275, 2497.76f}, + {455, 272, 2522.70f}, + {459, 270, 2547.71f}, + {463, 268, 2572.77f}, + {467, 266, 2597.88f}, + {471, 264, 2623.05f}, + {475, 262, 2648.28f}, + {479, 259, 2673.56f}, + {483, 257, 2698.90f}, + {487, 255, 2724.29f}, + {491, 253, 2749.75f}, + {495, 251, 2775.25f}, + {499, 249, 2800.82f}, + {503, 247, 2826.45f}, + {507, 245, 2852.13f}, + {511, 243, 2877.87f}, + {515, 241, 2903.67f}, + {519, 239, 2929.52f}, + {523, 237, 2955.44f}, + {527, 235, 2981.41f}, + {531, 233, 3007.44f}, + {535, 231, 3033.53f}, + {539, 229, 3059.68f}, + {543, 228, 3085.89f}, + {547, 226, 3112.16f}, + {551, 224, 3138.49f}, + {555, 222, 3164.88f}, + {559, 220, 3191.33f}, + {563, 218, 3217.84f}, + {567, 217, 3244.41f}, + {571, 215, 3271.04f}, + {575, 213, 3297.74f}, + {579, 211, 3324.49f}, + {583, 210, 3351.31f}, + {587, 208, 3378.18f}, + {591, 206, 3405.12f}, + {595, 204, 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{2923, -295, 51314.91f}, + {2927, -296, 51566.19f}, + {2931, -297, 51819.24f}, + {2935, -298, 52074.10f}, + {2939, -298, 52330.77f}, + {2943, -299, 52589.25f}, + {2947, -300, 52849.61f}, + {2951, -301, 53111.84f}, + {2955, -301, 53375.96f}, + {2959, -302, 53642.00f}, + {2963, -303, 53909.98f}, + {2967, -304, 54179.91f}, + {2971, -305, 54451.82f}, + {2975, -305, 54725.72f}, + {2979, -306, 55001.66f}, + {2983, -307, 55279.64f}, + {2987, -308, 55559.69f}, + {2991, -309, 55841.83f}, + {2995, -309, 56126.09f}, + {2999, -310, 56412.48f}, + {3003, -311, 56701.04f}, + {3007, -312, 56991.78f}, + {3011, -313, 57284.72f}, + {3015, -313, 57579.92f}, + {3019, -314, 57877.38f}, + {3023, -315, 58177.13f}, + {3027, -316, 58479.20f}, + {3031, -317, 58783.60f}, + {3035, -318, 59090.38f}, + {3039, -318, 59399.56f}, + {3043, -319, 59711.16f}, + {3047, -320, 60025.21f}, + {3051, -321, 60341.75f}, + {3055, -322, 60660.82f}, + {3059, -323, 60982.42f}, + {3063, -323, 61306.60f}, + {3067, -324, 61633.38f}, + {3071, -325, 61962.80f}, + {3075, -326, 62294.89f}, + {3079, -327, 62629.67f}, + {3083, -328, 62967.20f}, + {3087, -328, 63307.49f}, + {3091, -329, 63650.59f}, + {3095, -330, 63996.52f}, + {3099, -331, 64345.34f}, + {3103, -332, 64697.05f}, + {3107, -333, 65051.72f}, + {3111, -333, 65409.37f}, + {3115, -334, 65770.02f}, + {3119, -335, 66133.75f}, + {3123, -336, 66500.57f}, + {3127, -337, 66870.54f}, + {3131, -338, 67243.68f}, + {3135, -339, 67620.04f}, + {3139, -339, 67999.66f}, + {3143, -340, 68382.59f}, + {3147, -341, 68768.84f}, + {3151, -342, 69158.50f}, + {3155, -343, 69551.60f}, + {3159, -344, 69948.18f}, + {3163, -345, 70348.29f}, + {3167, -346, 70751.98f}, + {3171, -346, 71159.29f}, + {3175, -347, 71570.27f}, + {3179, -348, 71984.98f}, + {3183, -349, 72403.43f}, + {3187, -350, 72825.73f}, + {3191, -351, 73251.91f}, + {3195, -352, 73682.02f}, + {3199, -353, 74116.12f}, + {3203, -354, 74554.27f}, + {3207, -355, 74996.50f}, + {3211, -355, 75442.89f}, + {3215, -356, 75893.50f}, + {3219, -357, 76348.36f}, + {3223, -358, 76807.58f}, + {3227, -359, 77271.20f}, + {3231, -360, 77739.28f}, + {3235, -361, 78211.88f}, + {3239, -362, 78689.09f}, + {3243, -363, 79170.95f}, + {3247, -364, 79657.54f}, + {3251, -365, 80148.90f}, + {3255, -366, 80645.15f}, + {3259, -367, 81146.35f}, + {3263, -368, 81652.56f}, + {3267, -368, 82163.88f}, + {3271, -369, 82680.35f}, + {3275, -370, 83202.08f}, + {3279, -371, 83729.13f}, + {3283, -372, 84261.60f}, + {3287, -373, 84799.54f}, + {3291, -374, 85343.08f}, + {3295, -375, 85892.29f}, + {3299, -376, 86447.25f}, + {3303, -377, 87008.06f}, + {3307, -378, 87574.81f}, + {3311, -379, 88147.60f}, + {3315, -380, 88726.52f}, + {3319, -381, 89311.68f}, + {3323, -382, 89903.13f}, + {3327, -383, 90501.05f}, + {3331, -384, 91105.52f}, + {3335, -385, 91716.62f}, + {3339, -386, 92334.50f}, + {3343, -387, 92959.24f}, + {3347, -388, 93590.98f}, + {3351, -389, 94229.81f}, + {3355, -390, 94875.84f}, + {3359, -391, 95529.29f}, + {3363, -392, 96190.14f}, + {3367, -393, 96858.67f}, + {3371, -394, 97534.87f}, + {3375, -395, 98218.94f}, + {3379, -396, 98911.08f}, + {3383, -397, 99611.31f}, + {3387, -398, 100319.90f}, + {3391, -400, 101000.00f}, + {3395, -400, 101000.00f}, + {3399, -400, 101000.00f}, + {3403, -400, 101000.00f}, + {3407, -400, 101000.00f}, + {3411, -400, 101000.00f}, + {3415, -400, 101000.00f}, + {3419, -400, 101000.00f}, + {3423, -400, 101000.00f}, + {3427, -400, 101000.00f}, + {3431, -400, 101000.00f}, + {3435, -400, 101000.00f}, + {3439, -400, 101000.00f}, + {3443, -400, 101000.00f}, + {3447, -400, 101000.00f}, + {3451, -400, 101000.00f}, + {3455, -400, 101000.00f}, + {3459, -400, 101000.00f}, + {3463, -400, 101000.00f}, + {3467, -400, 101000.00f}, + {3471, -400, 101000.00f}, + {3475, -400, 101000.00f}, + {3479, -400, 101000.00f}, + {3483, -400, 101000.00f}, + {3487, -400, 101000.00f}, + {3491, -400, 101000.00f}, + {3495, -400, 101000.00f}, + {3499, -400, 101000.00f}, + {3503, -400, 101000.00f}, + {3507, -400, 101000.00f}, + {3511, -400, 101000.00f}, + {3515, -400, 101000.00f}, + {3519, -400, 101000.00f}, + {3523, -400, 101000.00f}, + {3527, -400, 101000.00f}, + {3531, -400, 101000.00f}, + {3535, -400, 101000.00f}, + {3539, -400, 101000.00f}, + {3543, -400, 101000.00f}, + {3547, -400, 101000.00f}, + {3551, -400, 101000.00f}, + {3555, -400, 101000.00f}, + {3559, -400, 101000.00f}, + {3563, -400, 101000.00f}, + {3567, -400, 101000.00f}, + {3571, -400, 101000.00f}, + {3575, -400, 101000.00f}, + {3579, -400, 101000.00f}, + {3583, -400, 101000.00f}, + {3587, -400, 101000.00f}, + {3591, -400, 101000.00f}, + {3595, -400, 101000.00f}, + {3599, -400, 101000.00f}, + {3603, -400, 101000.00f}, + {3607, -400, 101000.00f}, + {3611, -400, 101000.00f}, + {3615, -400, 101000.00f}, + {3619, -400, 101000.00f}, + {3623, -400, 101000.00f}, + {3627, -400, 101000.00f}, + {3631, -400, 101000.00f}, + {3635, -400, 101000.00f}, + {3639, -400, 101000.00f}, + {3643, -400, 101000.00f}, + {3647, -400, 101000.00f}, + {3651, -400, 101000.00f}, + {3655, -400, 101000.00f}, + {3659, -400, 101000.00f}, + {3663, -400, 101000.00f}, + {3667, -400, 101000.00f}, + {3671, -400, 101000.00f}, + {3675, -400, 101000.00f}, + {3679, -400, 101000.00f}, + {3683, -400, 101000.00f}, + {3687, -400, 101000.00f}, + {3691, -400, 101000.00f}, + {3695, -400, 101000.00f}, + {3699, -400, 101000.00f}, + {3703, -400, 101000.00f}, + {3707, -400, 101000.00f}, + {3711, -400, 101000.00f}, + {3715, -400, 101000.00f}, + {3719, -400, 101000.00f}, + {3723, -400, 101000.00f}, + {3727, -400, 101000.00f}, + {3731, -400, 101000.00f}, + {3735, -400, 101000.00f}, + {3739, -400, 101000.00f}, + {3743, -400, 101000.00f}, + {3747, -400, 101000.00f}, + {3751, -400, 101000.00f}, + {3755, -400, 101000.00f}, + {3759, -400, 101000.00f}, + {3763, -400, 101000.00f}, + {3767, -400, 101000.00f}, + {3771, -400, 101000.00f}, + {3775, -400, 101000.00f}, + {3779, -400, 101000.00f}, + {3783, -400, 101000.00f}, + {3787, -400, 101000.00f}, + {3791, -400, 101000.00f}, + {3795, -400, 101000.00f}, + {3799, -400, 101000.00f}, + {3803, -400, 101000.00f}, + {3807, -400, 101000.00f}, + {3811, -400, 101000.00f}, + {3815, -400, 101000.00f}, + {3819, -400, 101000.00f}, + {3823, -400, 101000.00f}, + {3827, -400, 101000.00f}, + {3831, -400, 101000.00f}, + {3835, -400, 101000.00f}, + {3839, -400, 101000.00f}, + {3843, -400, 101000.00f}, + {3847, -400, 101000.00f}, + {3851, -400, 101000.00f}, + {3855, -400, 101000.00f}, + {3859, -400, 101000.00f}, + {3863, -400, 101000.00f}, + {3867, -400, 101000.00f}, + {3871, -400, 101000.00f}, + {3875, -400, 101000.00f}, + {3879, -400, 101000.00f}, + {3883, -400, 101000.00f}, + {3887, -400, 101000.00f}, + {3891, -400, 101000.00f}, + {3895, -400, 101000.00f}, + {3899, -400, 101000.00f}, + {3903, -400, 101000.00f}, + {3907, -400, 101000.00f}, + {3911, -400, 101000.00f}, + {3915, -400, 101000.00f}, + {3919, -400, 101000.00f}, + {3923, -400, 101000.00f}, + {3927, -400, 101000.00f}, + {3931, -400, 101000.00f}, + {3935, -400, 101000.00f}, + {3939, -400, 101000.00f}, + {3943, -400, 101000.00f}, + {3947, -400, 101000.00f}, + {3951, -400, 101000.00f}, + {3955, -400, 101000.00f}, + {3959, -400, 101000.00f}, + {3963, -400, 101000.00f}, + {3967, -400, 101000.00f}, + {3971, -400, 101000.00f}, + {3975, -400, 101000.00f}, + {3979, -400, 101000.00f}, + {3983, -400, 101000.00f}, + {3987, -400, 101000.00f}, + {3991, -400, 101000.00f}, + {3995, -400, 101000.00f}, + {3999, -400, 101000.00f}, + {4003, -400, 101000.00f}, + {4007, -400, 101000.00f}, + {4011, -400, 101000.00f}, + {4015, -400, 101000.00f}, + {4019, -400, 101000.00f}, + {4023, -400, 101000.00f}, + {4027, -400, 101000.00f}, + {4031, -400, 101000.00f}, + {4035, -400, 101000.00f}, + {4039, -400, 101000.00f}, + {4043, -400, 101000.00f}, + {4047, -400, 101000.00f}, + {4051, -400, 101000.00f}, + {4055, -400, 101000.00f}, + {4059, -400, 101000.00f}, + {4063, -400, 101000.00f}, + {4067, -400, 101000.00f}, + {4071, -400, 101000.00f}, + {4075, -400, 101000.00f}, + {4079, -400, 101000.00f}, + {4083, -400, 101000.00f}, + {4087, -400, 101000.00f}, + {4091, -400, 101000.00f} +}; + + +const TablePoint ambient_lookup_table[] = { + {0, 1500, 183.20f}, + {3, 1500, 183.20f}, + {7, 1500, 183.20f}, + {11, 1500, 183.20f}, + {15, 1500, 183.20f}, + {19, 1500, 183.20f}, + {23, 1500, 183.20f}, + {27, 1500, 183.20f}, + {31, 1500, 183.20f}, + {35, 1500, 183.20f}, + {39, 1475, 193.87f}, + {43, 1434, 213.97f}, + {47, 1397, 234.11f}, + {51, 1363, 254.29f}, + {55, 1333, 274.50f}, + {59, 1304, 294.76f}, + {63, 1278, 315.06f}, + {67, 1254, 335.40f}, + {71, 1232, 355.78f}, + {75, 1210, 376.20f}, + {79, 1191, 396.66f}, + {83, 1172, 417.17f}, + {87, 1154, 437.71f}, + {91, 1137, 458.30f}, + {95, 1121, 478.92f}, + {99, 1106, 499.59f}, + {103, 1092, 520.30f}, + {107, 1078, 541.05f}, + {111, 1065, 561.85f}, + {115, 1052, 582.69f}, + {119, 1040, 603.56f}, + {123, 1028, 624.49f}, + {127, 1016, 645.45f}, + {131, 1005, 666.46f}, + {135, 995, 687.51f}, + {139, 985, 708.60f}, + {143, 975, 729.73f}, + {147, 965, 750.91f}, + {151, 956, 772.13f}, + {155, 947, 793.40f}, + {159, 938, 814.71f}, + {163, 929, 836.06f}, + {167, 921, 857.46f}, + {171, 913, 878.90f}, + {175, 905, 900.38f}, + {179, 898, 921.91f}, + {183, 890, 943.48f}, + {187, 883, 965.10f}, + {191, 876, 986.76f}, + {195, 869, 1008.47f}, + {199, 862, 1030.22f}, + {203, 855, 1052.02f}, + {207, 849, 1073.86f}, + {211, 842, 1095.75f}, + {215, 836, 1117.68f}, + {219, 830, 1139.66f}, + {223, 824, 1161.69f}, + {227, 818, 1183.76f}, + {231, 812, 1205.88f}, + {235, 807, 1228.04f}, + {239, 801, 1250.25f}, + {243, 796, 1272.50f}, + {247, 790, 1294.81f}, + {251, 785, 1317.16f}, + {255, 780, 1339.55f}, + {259, 775, 1362.00f}, + {263, 770, 1384.49f}, + {267, 765, 1407.03f}, + {271, 760, 1429.61f}, + {275, 756, 1452.24f}, + {279, 751, 1474.93f}, + {283, 746, 1497.66f}, + {287, 742, 1520.43f}, + {291, 737, 1543.26f}, + {295, 733, 1566.13f}, + {299, 729, 1589.06f}, + {303, 724, 1612.03f}, + {307, 720, 1635.05f}, + {311, 716, 1658.12f}, + {315, 712, 1681.24f}, + {319, 708, 1704.41f}, + {323, 704, 1727.62f}, + {327, 700, 1750.89f}, + {331, 696, 1774.21f}, + {335, 692, 1797.58f}, + {339, 689, 1820.99f}, + {343, 685, 1844.46f}, + {347, 681, 1867.98f}, + {351, 677, 1891.55f}, + {355, 674, 1915.17f}, + {359, 670, 1938.84f}, + {363, 667, 1962.57f}, + {367, 663, 1986.34f}, + {371, 660, 2010.16f}, + {375, 657, 2034.04f}, + {379, 653, 2057.97f}, + {383, 650, 2081.95f}, + {387, 647, 2105.98f}, + {391, 643, 2130.07f}, + {395, 640, 2154.21f}, + {399, 637, 2178.40f}, + {403, 634, 2202.64f}, + {407, 631, 2226.94f}, + {411, 628, 2251.29f}, + {415, 625, 2275.69f}, + {419, 622, 2300.15f}, + {423, 619, 2324.66f}, + {427, 616, 2349.23f}, + {431, 613, 2373.84f}, + {435, 610, 2398.52f}, + {439, 607, 2423.25f}, + {443, 604, 2448.03f}, + {447, 601, 2472.86f}, + {451, 599, 2497.76f}, + {455, 596, 2522.70f}, + {459, 593, 2547.71f}, + {463, 590, 2572.77f}, + {467, 588, 2597.88f}, + {471, 585, 2623.05f}, + {475, 582, 2648.28f}, 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{4019, -400, 332776.00f}, + {4023, -400, 332776.00f}, + {4027, -400, 332776.00f}, + {4031, -400, 332776.00f}, + {4035, -400, 332776.00f}, + {4039, -400, 332776.00f}, + {4043, -400, 332776.00f}, + {4047, -400, 332776.00f}, + {4051, -400, 332776.00f}, + {4055, -400, 332776.00f}, + {4059, -400, 332776.00f}, + {4063, -400, 332776.00f}, + {4067, -400, 332776.00f}, + {4071, -400, 332776.00f}, + {4075, -400, 332776.00f}, + {4079, -400, 332776.00f}, + {4083, -400, 332776.00f}, + {4087, -400, 332776.00f}, + {4091, -400, 332776.00f} +}; + +// Быстрый поиск температуры по ADC (прямая индексация) +int16_t lookup_table_get_temp(const TablePoint *table, uint16_t adc_value) { + if (adc_value >= 4096) return table[4095].temp; + return table[adc_value].temp; +} + +// Быстрый поиск сопротивления по ADC (прямая индексация) +float lookup_table_get_resistance(const TablePoint *table, uint16_t adc_value) { + if (adc_value >= 4096) return table[4095].resistance; + return table[adc_value].resistance; +} + + +// Функция получения температуры по ADC с линейной интерполяцией +float get_temperature_by_adc(const TablePoint *table, int table_size, int adc_value) { + // Проверка границ + if (adc_value <= table[0].adc) { + return table[0].temp; + } + if (adc_value >= table[table_size - 1].adc) { + return table[table_size - 1].temp; + } + + // Бинарный поиск интервала + int left = 0; + int right = table_size - 1; + + while (right - left > 1) { + int mid = (left + right) / 2; + if (table[mid].adc <= adc_value) { + left = mid; + } else { + right = mid; + } + } + + // Линейная интерполяция + float t = (float) (adc_value - table[left].adc) / + (table[right].adc - table[left].adc); + + return table[left].temp + t * (table[right].temp - table[left].temp); +} + +// Функция получения сопротивления по температуре с линейной интерполяцией +float get_resistance_by_temperature_linear(const TablePoint *table, int table_size, float temperature) { + // Проверка границ + if (temperature <= table[table_size - 1].temp) { + return table[table_size - 1].resistance; + } + if (temperature >= table[0].temp) { + return table[0].resistance; + } + + // Поиск интервала по температуре (таблица отсортирована по убыванию температуры) + int left = 0; + int right = table_size - 1; + + for (int i = 0; i < table_size - 1; i++) { + if (temperature <= table[i].temp && temperature >= table[i + 1].temp) { + left = i; + right = i + 1; + break; + } + } + + // Линейная интерполяция сопротивления + float t = (temperature - table[left].temp) / + (table[right].temp - table[left].temp); + + return table[left].resistance + t * (table[right].resistance - table[left].resistance); +} diff --git a/MODULES/HVAC_M7_ADC_TEMP/ADC_Temp_Fast.h b/MODULES/HVAC_M7_ADC_TEMP/ADC_Temp_Fast.h new file mode 100644 index 0000000..45c10b9 --- /dev/null +++ b/MODULES/HVAC_M7_ADC_TEMP/ADC_Temp_Fast.h @@ -0,0 +1,30 @@ +// +// Created by cfif on 06.05.2026. +// + +#ifndef HVAC_M7_ADC_TEMP_FAST_H +#define HVAC_M7_ADC_TEMP_FAST_H + +#include "stdint.h" + +// Структура для точки таблицы +typedef struct { + uint16_t adc; + int16_t temp; + float resistance; +} TablePoint; + +extern const TablePoint temperature_table_duct_KST45_table_3000[]; +extern const TablePoint temperature_table_duct_KST45_table_20000[]; +extern const TablePoint incar_lookup_table[]; +extern const TablePoint ambient_lookup_table[]; + +float get_temperature_by_adc(const TablePoint* table, int table_size, int adc_value); +float get_resistance_by_temperature_linear(const TablePoint* table, int table_size, float temperature); + +// Быстрый поиск температуры по ADC (прямая индексация) +int16_t lookup_table_get_temp(const TablePoint *table, uint16_t adc_value); +// Быстрый поиск сопротивления по ADC (прямая индексация) +float lookup_table_get_resistance(const TablePoint *table, uint16_t adc_value); + +#endif //HVAC_M7_ADC_TEMP_FAST_H diff --git a/MODULES/HVAC_M7_ADC_TEMP/ADC_pressure.c b/MODULES/HVAC_M7_ADC_TEMP/ADC_pressure.c new file mode 100644 index 0000000..9683616 --- /dev/null +++ b/MODULES/HVAC_M7_ADC_TEMP/ADC_pressure.c @@ -0,0 +1,52 @@ +// +// Created by cfif on 27.01.2026. +// +#include "stdint.h" + +// Функция для вычисления давления в кгс/см² +float calculate_pressure_kgf_cm2(uint32_t adc_value) { + float vdd = 5.0f; // Напряжение питания + float vout; // Выходное напряжение датчика + float pressure; // Давление в кгс/см² + + // Преобразуем значение АЦП в напряжение (12 бит = 4095) + vout = ((float)adc_value / 4095.0f) * vdd; + + // Вычисляем давление по формуле из даташита: + // Vout = Vdd * (0.025 * P + 0.1) + // Решаем относительно P: + // P = (Vout/Vdd - 0.1) / 0.025 + pressure = (vout/vdd - 0.1f) / 0.025f; + + return pressure; +} + +// Функция для вычисления давления в MPa +float calculate_pressure_mpa(uint32_t adc_value) { + float vdd = 5.0f; + float vout; + float pressure; + + vout = ((float)adc_value / 4095.0f) * vdd; + + // Для MPa: Vout = Vdd * (0.254929 * P + 0.1) + // P = (Vout/Vdd - 0.1) / 0.254929 + pressure = (vout/vdd - 0.1f) / 0.254929f; + + return pressure; +} + +// Функция для вычисления давления в PSIA +float calculate_pressure_psia(uint32_t adc_value) { + float vdd = 5.0f; + float vout; + float pressure; + + vout = ((float)adc_value / 4095.0f) * vdd; + + // Для PSIA: Vout = Vdd * (0.001758 * P + 0.074126) + // P = (Vout/Vdd - 0.074126) / 0.001758 + pressure = (vout/vdd - 0.074126f) / 0.001758f; + + return pressure; +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_ADC_TEMP/modular.json b/MODULES/HVAC_M7_ADC_TEMP/modular.json new file mode 100644 index 0000000..9589ff8 --- /dev/null +++ b/MODULES/HVAC_M7_ADC_TEMP/modular.json @@ -0,0 +1,13 @@ +{ + "dep": [ + + ], + "cmake": { + "inc_dirs": [ + "./" + ], + "srcs": [ + "./**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_Adcs/Adcs.c b/MODULES/HVAC_M7_Adcs/Adcs.c new file mode 100644 index 0000000..ce2524f --- /dev/null +++ b/MODULES/HVAC_M7_Adcs/Adcs.c @@ -0,0 +1,616 @@ +// +// Created by CFIF on 14.12.23. +// +#include +#include "fc7xxx_driver_port.h" +#include "Adcs.h" + +#define LOG_SIGN "INIT" +#define LOGGER logger + +tAdcs ADCS; + +void Bsp_ADC0_HandleResult(const uint32_t *const pBuffer) { + Get_ADC_Result(ADCS.adc_0_IO.env); +} + +void Bsp_ADC1_HandleResult(const uint32_t *const pBuffer) { + Get_ADC_Result(ADCS.adc_1_IO.env); +} + + + +#define ADC0_CHN_NUM_EN 31 +static uint32_t s_aAdc0ResultBuf[ADC0_CHN_NUM_EN] = {0U}; +static const ADC_ChannelCfgType s_aChannelsAdc0[ADC0_CHN_NUM_EN] = + { + + { + .eChannel = ADC_CHANNEL_0, //PA25: Sensor_Ambient_Temp + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + { + .eChannel = ADC_CHANNEL_1, //PE5: IGN_ANS_PE5_ADC0_1 (Напряжение зажигание ДЕЛИТЕЛЬ) + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC_CHANNEL_2, //PA26: Sensor_AC_Pressure + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC_CHANNEL_3, //PE12: Sensor_Incar_Temp_FL + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC_CHANNEL_4, //PE4: Sensor_Incar_Temp_RL + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC_CHANNEL_5, //PE13: Sensor_Rear_Evap_Temp + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC_CHANNEL_6, //PA27: Sensor_Evap_Temp + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC_CHANNEL_7, //PA28: Sensor_Rear_Duct1 + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC_CHANNEL_8, //PD17: Sensor_Rear_Duct2 + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC_CHANNEL_9, //PA29: Sensor_Front_Duct1 + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC_CHANNEL_10, //PD16: Sensor_Front_Duct2 + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC_CHANNEL_11, //PD15: Sensor_Front_Duct3 + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC_CHANNEL_12, //PE9: Sensor_Front_Duct4 + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC_CHANNEL_13, //PA31: Sensor_Rear_Duct3 + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC_CHANNEL_14, //PB20: Sensor_Rear_Duct4 + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC_CHANNEL_15, //PB21: Sensor_Incar_Temp_FR + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC_CHANNEL_16, //PE0: Sensor_Incar_Temp_RR + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + + { + .eChannel = ADC_CHANNEL_17, //PE1: Sensor_Rear_Duct5 + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC_CHANNEL_18, //PE24: Sensor_Rear_Duct6 + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC_CHANNEL_19, //PE23: Reserve_Sensor_Duct_Temp_1 + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC_CHANNEL_21, //PA14: Sensor_Front_Duct5 + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC_CHANNEL_22, //PE20: Sensor_Front_Duct6 + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC_CHANNEL_23, //PE19: BTS5120_2EKA_ShutoffValvePowerTXV + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + + { + .eChannel = ADC_CHANNEL_25, //PE6: Pressure_DIAG_PE6_ADC_0_25 (Напряжение датчика давления ДЕЛИТЕЛЬ) + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC_CHANNEL_26, //PA15: BTS5180_2EKA_ShutOFFValveFrontRear + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC_CHANNEL_27, //PE18: Вывод диагностики BTS5180_2EKA_TwoWayValveAndReservePowerSupply (0 - Канал 0; 1 - Канал 1) + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC_CHANNEL_28, //PA16: BTS5180_2EKA_FrontRearIncarMotor + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC_CHANNEL_30, //PC7: Вывод диагностики BTS5180_2EKA_2xChannelPTCPower (0 - Канал 0; 1 - Канал 1) + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC_CHANNEL_31, //PD31: Reserve_Sensor_Duct_Temp_2 + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + + { + .eChannel = ADC_CHANNEL_29, //PC6: Sensor_PT_rHVAC_P + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC_CHANNEL_24, //PE2: Sensor_A_T_reserve + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + } + + }; + + +#define ADC1_CHN_NUM_EN 17 +static uint32_t s_aAdc1ResultBuf[ADC1_CHN_NUM_EN] = {0U}; +static const ADC_ChannelCfgType s_aChannelsAdc1[ADC1_CHN_NUM_EN] = + { + { + .eChannel = ADC_CHANNEL_0, //PE10: Напряжение VN7008AJ_DIAG_FrontLINActuatorPowerDriverAB (ДЕЛИТЕЛЬ) + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC_CHANNEL_1, //PD0: tVN7008AJ_DIAG_RearLINActuatorPowerDriverC (ДЕЛИТЕЛЬ) + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + + { + .eChannel = ADC_CHANNEL_2, //PE15: PBATT_CHECK_PE15_ADC1_2 (Напряжение сети ДЕЛИТЕЛЬ) + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC_CHANNEL_3, //PA8: VN7008AJ_FrontLINActuatorPowerDriverAB + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC_CHANNEL_4, //PE11: tVN7008AJ_RearLINActuatorPowerDriverC + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + + { + .eChannel = ADC_CHANNEL_9, //PA6: PT_F_HVAC_VCC_DIAG + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + + { + .eChannel = ADC_CHANNEL_18, //PB14: PT_HVBchiller_VCC_DIAG + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC_CHANNEL_28, //PB8: PT_R_HVAC_VCC_DIAG + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + + + + + { + .eChannel = ADC_CHANNEL_17, //PB15: Sensor_PT_fHVAC_P + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC_CHANNEL_8, //PE7: Sensor_PT_fHVAC_T + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC_CHANNEL_20, //PC25: Sensor_PT_rHVAC_T + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC_CHANNEL_21, //PC26: Sensor_HVBchiller_P + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC_CHANNEL_24, //PD25: Sensor_HVBchiller_T + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC_CHANNEL_25, //PB9: Sensor_PT_P_reserve + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC_CHANNEL_26, //PD26: Sensor_PT_T_reserve + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC_CHANNEL_30, //PA0: Sensor_B_T_reserve + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_3 + }, + + { + .eChannel = ADC1_CHANNEL_VREFH, + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_0 + }, + + }; + + +/* +#define ADC0_CHN_NUM_EN 1 +static uint32_t s_aAdc0ResultBuf[ADC0_CHN_NUM_EN] = {0U}; +static const ADC_ChannelCfgType s_aChannelsAdc0[ADC0_CHN_NUM_EN] = + { + { + .eChannel = ADC_CHANNEL_0, + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_1 + } + }; + +#define ADC1_CHN_NUM_EN 1 +static uint32_t s_aAdc1ResultBuf[ADC1_CHN_NUM_EN] = {0U}; +static const ADC_ChannelCfgType s_aChannelsAdc1[ADC1_CHN_NUM_EN] = + { + { + .eChannel = ADC_CHANNEL_25, + .eSampleTimeOption = ADC_SAMPLE_TIME_OPTION_1 + } + }; +*/ + +void Adcs_Init(tLoggerInterface *logger) { + tAdcs *env = &ADCS; + + PORT_InitType tInitStruct = {0}; + tInitStruct.bPullEn = false; + tInitStruct.ePullSel = PORT_PULL_UP; + + //PA25: Sensor_Ambient_Temp + tInitStruct.u32PortPins = PORT_PIN_25; + tInitStruct.uPortPinMux.u32PortPinMode = PORTA_25_ADC0_SE0; + PORT_InitPins(PORT_A, &tInitStruct); + + //PE5: IGN_ANS_PE5_ADC0_1 (Напряжение зажигание ДЕЛИТЕЛЬ) + tInitStruct.u32PortPins = PORT_PIN_5; + tInitStruct.uPortPinMux.u32PortPinMode = PORTE_5_ADC0_SE1; + PORT_InitPins(PORT_E, &tInitStruct); + + //PA26: Sensor_AC_Pressure + tInitStruct.u32PortPins = PORT_PIN_26; + tInitStruct.uPortPinMux.u32PortPinMode = PORTA_26_ADC0_SE2; + PORT_InitPins(PORT_A, &tInitStruct); + + //PE12: Sensor_Incar_Temp_FL + tInitStruct.u32PortPins = PORT_PIN_12; + tInitStruct.uPortPinMux.u32PortPinMode = PORTE_12_ADC0_SE3; + PORT_InitPins(PORT_E, &tInitStruct); + + //PE4: Sensor_Incar_Temp_RL + tInitStruct.u32PortPins = PORT_PIN_4; + tInitStruct.uPortPinMux.u32PortPinMode = PORTE_4_ADC0_SE4; + PORT_InitPins(PORT_E, &tInitStruct); + + //PE13: Sensor_Rear_Evap_Temp + tInitStruct.u32PortPins = PORT_PIN_13; + tInitStruct.uPortPinMux.u32PortPinMode = PORTE_13_ADC0_SE5; + PORT_InitPins(PORT_E, &tInitStruct); + + //PA27: Sensor_Evap_Temp + tInitStruct.u32PortPins = PORT_PIN_27; + tInitStruct.uPortPinMux.u32PortPinMode = PORTA_27_ADC0_SE6; + PORT_InitPins(PORT_A, &tInitStruct); + + //PA28: Sensor_Rear_Duct1 + tInitStruct.u32PortPins = PORT_PIN_28; + tInitStruct.uPortPinMux.u32PortPinMode = PORTA_28_ADC0_SE7; + PORT_InitPins(PORT_A, &tInitStruct); + + // PD17: Sensor_Rear_Duct2 + tInitStruct.u32PortPins = PORT_PIN_17; + tInitStruct.uPortPinMux.u32PortPinMode = PORTD_17_ADC0_SE8; + PORT_InitPins(PORT_D, &tInitStruct); + + //PA29: Sensor_Front_Duct1 + tInitStruct.u32PortPins = PORT_PIN_29; + tInitStruct.uPortPinMux.u32PortPinMode = PORTA_29_ADC0_SE9; + PORT_InitPins(PORT_A, &tInitStruct); + + //PD16: Sensor_Front_Duct2 + tInitStruct.u32PortPins = PORT_PIN_16; + tInitStruct.uPortPinMux.u32PortPinMode = PORTD_16_ADC0_SE10_CMP0_IN0; + PORT_InitPins(PORT_D, &tInitStruct); + + //PD15: Sensor_Front_Duct3 + tInitStruct.u32PortPins = PORT_PIN_15; + tInitStruct.uPortPinMux.u32PortPinMode = PORTD_15_ADC0_SE11_CMP0_IN1; + PORT_InitPins(PORT_D, &tInitStruct); + + //PE9: Sensor_Front_Duct4 + tInitStruct.u32PortPins = PORT_PIN_9; + tInitStruct.uPortPinMux.u32PortPinMode = PORTE_9_ADC0_SE12_CMP0_IN2; + PORT_InitPins(PORT_E, &tInitStruct); + + //PA31: Sensor_Rear_Duct3 + tInitStruct.u32PortPins = PORT_PIN_31; + tInitStruct.uPortPinMux.u32PortPinMode = PORTA_31_ADC0_SE13_CMP0_IN3; + PORT_InitPins(PORT_A, &tInitStruct); + + //PB20: Sensor_Rear_Duct4 + tInitStruct.u32PortPins = PORT_PIN_20; + tInitStruct.uPortPinMux.u32PortPinMode = PORTB_20_ADC0_SE14; + PORT_InitPins(PORT_B, &tInitStruct); + + //PB21: Sensor_Incar_Temp_FR + tInitStruct.u32PortPins = PORT_PIN_21; + tInitStruct.uPortPinMux.u32PortPinMode = PORTB_21_ADC0_SE15; + PORT_InitPins(PORT_B, &tInitStruct); + + //PE0: Sensor_Incar_Temp_RR + tInitStruct.u32PortPins = PORT_PIN_0; + tInitStruct.uPortPinMux.u32PortPinMode = PORTE_0_ADC0_SE16; + PORT_InitPins(PORT_E, &tInitStruct); + + //PE1: Sensor_Rear_Duct5 + tInitStruct.u32PortPins = PORT_PIN_1; + tInitStruct.uPortPinMux.u32PortPinMode = PORTE_1_ADC0_SE17; + PORT_InitPins(PORT_E, &tInitStruct); + + //PE24: Sensor_Rear_Duct6 + tInitStruct.u32PortPins = PORT_PIN_24; + tInitStruct.uPortPinMux.u32PortPinMode = PORTE_24_ADC0_SE18; + PORT_InitPins(PORT_E, &tInitStruct); + + //PE23: Reserve_Sensor_Duct_Temp_1 + tInitStruct.u32PortPins = PORT_PIN_23; + tInitStruct.uPortPinMux.u32PortPinMode = PORTE_23_ADC0_SE19; + PORT_InitPins(PORT_E, &tInitStruct); + + ///////////////////////////////////////////////////////////////////////////////// + + //PA14: Sensor_Front_Duct5 + tInitStruct.u32PortPins = PORT_PIN_14; + tInitStruct.uPortPinMux.u32PortPinMode = PORTA_14_ADC0_SE21; + PORT_InitPins(PORT_A, &tInitStruct); + + + //PE20: Sensor_Front_Duct6 + tInitStruct.u32PortPins = PORT_PIN_20; + tInitStruct.uPortPinMux.u32PortPinMode = PORTE_20_ADC0_SE22; + PORT_InitPins(PORT_E, &tInitStruct); + + //PE19: BTS5120_2EKA_ShutoffValvePowerTXV + tInitStruct.u32PortPins = PORT_PIN_23; + tInitStruct.uPortPinMux.u32PortPinMode = PORTE_19_ADC0_SE23; + PORT_InitPins(PORT_E, &tInitStruct); + + //PE6: Pressure_DIAG_PE6_ADC_0_25 (Напряжение датчика давления ДЕЛИТЕЛЬ) + tInitStruct.u32PortPins = PORT_PIN_6; + tInitStruct.uPortPinMux.u32PortPinMode = PORTE_6_ADC0_SE25; + PORT_InitPins(PORT_E, &tInitStruct); + + //PA15: BTS5180_2EKA_ShutOFFValveFrontRear + tInitStruct.u32PortPins = PORT_PIN_15; + tInitStruct.uPortPinMux.u32PortPinMode = PORTA_15_ADC0_SE26; + PORT_InitPins(PORT_A, &tInitStruct); + + //PE18: Вывод диагностики BTS5180_2EKA_TwoWayValveAndReservePowerSupply (0 - Канал 0; 1 - Канал 1) + tInitStruct.u32PortPins = PORT_PIN_18; + tInitStruct.uPortPinMux.u32PortPinMode = PORTE_18_ADC0_SE27; + PORT_InitPins(PORT_E, &tInitStruct); + + //PA16: BTS5180_2EKA_FrontRearIncarMotor + tInitStruct.u32PortPins = PORT_PIN_16; + tInitStruct.uPortPinMux.u32PortPinMode = PORTA_16_ADC0_SE28; + PORT_InitPins(PORT_A, &tInitStruct); + + ///////////////////////////////////////////////////////////////////////////////// + + //PC7: Вывод диагностики BTS5180_2EKA_2xChannelPTCPower (0 - Канал 0; 1 - Канал 1) + tInitStruct.u32PortPins = PORT_PIN_7; + tInitStruct.uPortPinMux.u32PortPinMode = PORTC_7_ADC0_SE30; + PORT_InitPins(PORT_C, &tInitStruct); + + //PD31: Reserve_Sensor_Duct_Temp_2 + tInitStruct.u32PortPins = PORT_PIN_31; + tInitStruct.uPortPinMux.u32PortPinMode = PORTD_31_ADC0_SE31; + PORT_InitPins(PORT_D, &tInitStruct); + + + //PC6: Sensor_PT_rHVAC_P + tInitStruct.u32PortPins = PORT_PIN_6; + tInitStruct.uPortPinMux.u32PortPinMode = PORTC_6_ADC0_SE29; + PORT_InitPins(PORT_C, &tInitStruct); + + //PE2: Sensor_A_T_reserve + tInitStruct.u32PortPins = PORT_PIN_2; + tInitStruct.uPortPinMux.u32PortPinMode = PORTE_2_ADC0_SE24; + PORT_InitPins(PORT_E, &tInitStruct); + + ADC_Initial( + &env->adc_0, + ADC_INSTANCE_0, // ADC_INSTANCE_0, ADC_INSTANCE_1 + + DMA_CHANNEL_4, + + DMA4_IRQn, + 0xFF, + DMA4_IRQn, + + s_aAdc0ResultBuf, + + ADC0_CHN_NUM_EN, + (ADC_ChannelCfgType *) s_aChannelsAdc0, + + 0, + 0, + 0, + + Bsp_ADC0_HandleResult + ); + + + LoggerInfoStatic(LOGGER, LOG_SIGN, "Initialization ADC0 - OK") + + + env->adc_0_IO = vAdcGetIo(&env->adc_0); + + + //PE10: Напряжение VN7008AJ_DIAG_FrontLINActuatorPowerDriverAB (ДЕЛИТЕЛЬ) + tInitStruct.u32PortPins = PORT_PIN_10; + tInitStruct.uPortPinMux.u32PortPinMode = PORTE_10_ADC1_SE0; + PORT_InitPins(PORT_E, &tInitStruct); + + //PD0: tVN7008AJ_DIAG_RearLINActuatorPowerDriverC (ДЕЛИТЕЛЬ) + tInitStruct.u32PortPins = PORT_PIN_0; + tInitStruct.uPortPinMux.u32PortPinMode = PORTD_0_ADC1_SE1; + PORT_InitPins(PORT_D, &tInitStruct); + + //PE15: PBATT_CHECK_PE15_ADC1_2 (Напряжение сети ДЕЛИТЕЛЬ) + tInitStruct.u32PortPins = PORT_PIN_15; + tInitStruct.uPortPinMux.u32PortPinMode = PORTE_15_ADC1_SE2; + PORT_InitPins(PORT_E, &tInitStruct); + + //PA8: VN7008AJ_FrontLINActuatorPowerDriverAB + tInitStruct.u32PortPins = PORT_PIN_8; + tInitStruct.uPortPinMux.u32PortPinMode = PORTA_8_ADC1_SE3; + PORT_InitPins(PORT_A, &tInitStruct); + + //PE11: tVN7008AJ_RearLINActuatorPowerDriverC + tInitStruct.u32PortPins = PORT_PIN_11; + tInitStruct.uPortPinMux.u32PortPinMode = PORTE_11_ADC1_SE4; + PORT_InitPins(PORT_E, &tInitStruct); + + //PA6: PT_F_HVAC_VCC_DIAG + tInitStruct.u32PortPins = PORT_PIN_6; + tInitStruct.uPortPinMux.u32PortPinMode = PORTA_6_ADC1_SE9; + PORT_InitPins(PORT_A, &tInitStruct); + + //PB14: PT_HVBchiller_VCC_DIAG + tInitStruct.u32PortPins = PORT_PIN_14; + tInitStruct.uPortPinMux.u32PortPinMode = PORTB_14_ADC1_SE18; + PORT_InitPins(PORT_B, &tInitStruct); + + //PB8: PT_R_HVAC_VCC_DIAG + tInitStruct.u32PortPins = PORT_PIN_8; + tInitStruct.uPortPinMux.u32PortPinMode = PORTB_8_ADC1_SE28; + PORT_InitPins(PORT_B, &tInitStruct); + + + + //PB15: Sensor_PT_fHVAC_P + tInitStruct.u32PortPins = PORT_PIN_15; + tInitStruct.uPortPinMux.u32PortPinMode = PORTB_15_ADC1_SE17; + PORT_InitPins(PORT_B, &tInitStruct); + + //PE7: Sensor_PT_fHVAC_T + tInitStruct.u32PortPins = PORT_PIN_7; + tInitStruct.uPortPinMux.u32PortPinMode = PORTE_7_ADC1_SE8; + PORT_InitPins(PORT_B, &tInitStruct); + + //PC25: Sensor_PT_rHVAC_T + tInitStruct.u32PortPins = PORT_PIN_25; + tInitStruct.uPortPinMux.u32PortPinMode = PORTC_25_ADC1_SE20; + PORT_InitPins(PORT_C, &tInitStruct); + + //PC26: Sensor_HVBchiller_P + tInitStruct.u32PortPins = PORT_PIN_26; + tInitStruct.uPortPinMux.u32PortPinMode = PORTC_26_ADC1_SE21; + PORT_InitPins(PORT_C, &tInitStruct); + + //PD25: Sensor_HVBchiller_T + tInitStruct.u32PortPins = PORT_PIN_25; + tInitStruct.uPortPinMux.u32PortPinMode = PORTD_25_ADC1_SE24; + PORT_InitPins(PORT_D, &tInitStruct); + + //PB9: Sensor_PT_P_reserve + tInitStruct.u32PortPins = PORT_PIN_9; + tInitStruct.uPortPinMux.u32PortPinMode = PORTB_9_ADC1_SE25; + PORT_InitPins(PORT_B, &tInitStruct); + + //PD26: Sensor_PT_T_reserve + tInitStruct.u32PortPins = PORT_PIN_26; + tInitStruct.uPortPinMux.u32PortPinMode = PORTD_26_ADC1_SE26; + PORT_InitPins(PORT_D, &tInitStruct); + + //PA0: Sensor_B_T_reserve + tInitStruct.u32PortPins = PORT_PIN_0; + tInitStruct.uPortPinMux.u32PortPinMode = PORTA_0_ADC1_SE30; + PORT_InitPins(PORT_A, &tInitStruct); + + + ADC_Initial( + &env->adc_1, + ADC_INSTANCE_1, // ADC_INSTANCE_0, ADC_INSTANCE_1 + + DMA_CHANNEL_3, + + DMA3_IRQn, + 0xFF, + DMA3_IRQn, + + s_aAdc1ResultBuf, + + ADC1_CHN_NUM_EN, + (ADC_ChannelCfgType *) s_aChannelsAdc1, + + 0, + 0, + 0, + + Bsp_ADC1_HandleResult + ); + + + LoggerInfoStatic(LOGGER, LOG_SIGN, "Initialization ADC1 - OK") + + + env->adc_1_IO = vAdcGetIo(&env->adc_1); +} diff --git a/MODULES/HVAC_M7_Adcs/Adcs.h b/MODULES/HVAC_M7_Adcs/Adcs.h new file mode 100644 index 0000000..42499a5 --- /dev/null +++ b/MODULES/HVAC_M7_Adcs/Adcs.h @@ -0,0 +1,23 @@ +// +// Created by CFIF on 14.12.23. +// + +#ifndef FLAG_ADCS_H +#define FLAG_ADCS_H + +#include "AdcFlagchip.h" +#include "LoggerInterface.h" + +typedef struct { + tAdcFlagchip adc_0; + tAdcIO adc_0_IO; + + tAdcFlagchip adc_1; + tAdcIO adc_1_IO; +} tAdcs; + +extern tAdcs ADCS; + +void Adcs_Init(tLoggerInterface *logger); + +#endif //FLAG_ADCS_H diff --git a/MODULES/HVAC_M7_Adcs/modular.json b/MODULES/HVAC_M7_Adcs/modular.json new file mode 100644 index 0000000..9589ff8 --- /dev/null +++ b/MODULES/HVAC_M7_Adcs/modular.json @@ -0,0 +1,13 @@ +{ + "dep": [ + + ], + "cmake": { + "inc_dirs": [ + "./" + ], + "srcs": [ + "./**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_CAN_DBG_MATRIX/butl/ccu_candb_dbg-binutil.c b/MODULES/HVAC_M7_CAN_DBG_MATRIX/butl/ccu_candb_dbg-binutil.c new file mode 100644 index 0000000..01f677c --- /dev/null +++ b/MODULES/HVAC_M7_CAN_DBG_MATRIX/butl/ccu_candb_dbg-binutil.c @@ -0,0 +1,29 @@ +// Generator version : v3.1 +// DBC filename : CCUdbg.dbc +#include "ccu_candb_dbg-binutil.h" + +// DBC file version +#if (VER_CANDB_DBG_MAJ != (0U)) || (VER_CANDB_DBG_MIN != (0U)) +#error The CCU_CANDB_DBG binutil source file has inconsistency with core dbc lib! +#endif + +#ifdef __DEF_CCU_CANDB_DBG__ + +ccu_candb_dbg_rx_t ccu_candb_dbg_rx; + +ccu_candb_dbg_tx_t ccu_candb_dbg_tx; + +#endif // __DEF_CCU_CANDB_DBG__ + +uint32_t ccu_candb_dbg_Receive(ccu_candb_dbg_rx_t* _m, const uint8_t* _d, uint32_t _id, uint8_t dlc_) +{ + uint32_t recid = 0; + if (_id == 0x400U) { + recid = Unpack_dbg_Cmd_Act_Information_candb_dbg(&(_m->dbg_Cmd_Act_Information), _d, dlc_); + } else if (_id == 0x6ABU) { + recid = Unpack_XCP_CCU_RX_candb_dbg(&(_m->XCP_CCU_RX), _d, dlc_); + } + + return recid; +} + diff --git a/MODULES/HVAC_M7_CAN_DBG_MATRIX/butl/ccu_candb_dbg-binutil.h b/MODULES/HVAC_M7_CAN_DBG_MATRIX/butl/ccu_candb_dbg-binutil.h new file mode 100644 index 0000000..e15bae2 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_DBG_MATRIX/butl/ccu_candb_dbg-binutil.h @@ -0,0 +1,65 @@ +// Generator version : v3.1 +// DBC filename : CCUdbg.dbc +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dbccodeconf.h" + +#include "candb_dbg.h" + +typedef struct { + dbg_Cmd_Act_Information_t dbg_Cmd_Act_Information; + XCP_CCU_RX_t XCP_CCU_RX; +} ccu_candb_dbg_rx_t; + + +typedef struct { + dbg_Logic_State_t dbg_Logic_State; + dbg_Logic_KM_Status_t dbg_Logic_KM_Status; + dbg_Logic_Valve_t dbg_Logic_Valve; + dbg_Logic_Blower_t dbg_Logic_Blower; + dbg_Logic_Ac_t dbg_Logic_Ac; + dbg_Logic_Rec_t dbg_Logic_Rec; + dbg_DiffBlr_ValveOpen_t dbg_DiffBlr_ValveOpen; + dbg_Act0_t dbg_Act0; + dbg_Act1_t dbg_Act1; + dbg_Act2_t dbg_Act2; + dbg_Sen_Amb_t dbg_Sen_Amb; + dbg_Sen_0_t dbg_Sen_0; + dbg_CCU_IO_t dbg_CCU_IO; + dbg_CCU_Info_t dbg_CCU_Info; + dbg_Drs_t dbg_Drs; + dbg_Sen_Incar_t dbg_Sen_Incar; + dbg_Info_Act1_t dbg_Info_Act1; + dbg_Info_Act2_t dbg_Info_Act2; + dbg_Sen_Eva_t dbg_Sen_Eva; + dbg_Sen_Duct_t dbg_Sen_Duct; + dbg_Sen_Demist_t dbg_Sen_Demist; + dbg_LIN_AirQS_Stat_t dbg_LIN_AirQS_Stat; + dbg_LIN_Aroma_Stat_t dbg_LIN_Aroma_Stat; + dbg_LIN_Ionizer_Stat_t dbg_LIN_Ionizer_Stat; + dbg_LIN_eTXV_Stat_t dbg_LIN_eTXV_Stat; + dbg_LIN_DRS_Stat_t dbg_LIN_DRS_Stat; + dbg_Auto_AF_t dbg_Auto_AF; + dbg_Auto_Duct_t dbg_Auto_Duct; + dbg_Auto_Valve_Plus_t dbg_Auto_Valve_Plus; + XCP_CCU_TX_t XCP_CCU_TX; + dbg_Stat_PID_t dbg_stat_PID; +} ccu_candb_dbg_tx_t; + +uint32_t ccu_candb_dbg_Receive(ccu_candb_dbg_rx_t *m, const uint8_t *d, uint32_t msgid, uint8_t dlc); + +#ifdef __DEF_CCU_CANDB_DBG__ + +extern ccu_candb_dbg_rx_t ccu_candb_dbg_rx; + +extern ccu_candb_dbg_tx_t ccu_candb_dbg_tx; + +#endif // __DEF_CCU_CANDB_DBG__ + +#ifdef __cplusplus +} +#endif diff --git a/MODULES/HVAC_M7_CAN_DBG_MATRIX/butl/tester_candb_dbg-binutil.c b/MODULES/HVAC_M7_CAN_DBG_MATRIX/butl/tester_candb_dbg-binutil.c new file mode 100644 index 0000000..9e3678c --- /dev/null +++ b/MODULES/HVAC_M7_CAN_DBG_MATRIX/butl/tester_candb_dbg-binutil.c @@ -0,0 +1,27 @@ +// Generator version : v3.1 +// DBC filename : CCUdbg.dbc +#include "tester_candb_dbg-binutil.h" + +// DBC file version +#if (VER_CANDB_DBG_MAJ != (0U)) || (VER_CANDB_DBG_MIN != (0U)) +#error The TESTER_CANDB_DBG binutil source file has inconsistency with core dbc lib! +#endif + +#ifdef __DEF_TESTER_CANDB_DBG__ + +tester_candb_dbg_rx_t tester_candb_dbg_rx; + +tester_candb_dbg_tx_t tester_candb_dbg_tx; + +#endif // __DEF_TESTER_CANDB_DBG__ + +uint32_t tester_candb_dbg_Receive(tester_candb_dbg_rx_t* _m, const uint8_t* _d, uint32_t _id, uint8_t dlc_) +{ + uint32_t recid = 0; + if (_id == 0x6ABU) { + recid = Unpack_XCP_CCU_RX_candb_dbg(&(_m->XCP_CCU_RX), _d, dlc_); + } + + return recid; +} + diff --git a/MODULES/HVAC_M7_CAN_DBG_MATRIX/butl/tester_candb_dbg-binutil.h b/MODULES/HVAC_M7_CAN_DBG_MATRIX/butl/tester_candb_dbg-binutil.h new file mode 100644 index 0000000..06f0151 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_DBG_MATRIX/butl/tester_candb_dbg-binutil.h @@ -0,0 +1,36 @@ +// Generator version : v3.1 +// DBC filename : CCUdbg.dbc +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dbccodeconf.h" + +#include "candb_dbg.h" + +typedef struct +{ + XCP_CCU_RX_t XCP_CCU_RX; +} tester_candb_dbg_rx_t; + +typedef struct +{ + dbg_Cmd_Act_Information_t dbg_Cmd_Act_Information; + XCP_CCU_RX_t XCP_CCU_RX; +} tester_candb_dbg_tx_t; + +uint32_t tester_candb_dbg_Receive(tester_candb_dbg_rx_t* m, const uint8_t* d, uint32_t msgid, uint8_t dlc); + +#ifdef __DEF_TESTER_CANDB_DBG__ + +extern tester_candb_dbg_rx_t tester_candb_dbg_rx; + +extern tester_candb_dbg_tx_t tester_candb_dbg_tx; + +#endif // __DEF_TESTER_CANDB_DBG__ + +#ifdef __cplusplus +} +#endif diff --git a/MODULES/HVAC_M7_CAN_DBG_MATRIX/butl/vector__xxx_candb_dbg-binutil.c b/MODULES/HVAC_M7_CAN_DBG_MATRIX/butl/vector__xxx_candb_dbg-binutil.c new file mode 100644 index 0000000..021044b --- /dev/null +++ b/MODULES/HVAC_M7_CAN_DBG_MATRIX/butl/vector__xxx_candb_dbg-binutil.c @@ -0,0 +1,139 @@ +// Generator version : v3.1 +// DBC filename : CCUdbg.dbc +#include "vector__xxx_candb_dbg-binutil.h" + +// DBC file version +#if (VER_CANDB_DBG_MAJ != (0U)) || (VER_CANDB_DBG_MIN != (0U)) +#error The VECTOR__XXX_CANDB_DBG binutil source file has inconsistency with core dbc lib! +#endif + +#ifdef __DEF_VECTOR__XXX_CANDB_DBG__ + +vector__xxx_candb_dbg_rx_t vector__xxx_candb_dbg_rx; + +#endif // __DEF_VECTOR__XXX_CANDB_DBG__ + +uint32_t vector__xxx_candb_dbg_Receive(vector__xxx_candb_dbg_rx_t* _m, const uint8_t* _d, uint32_t _id, uint8_t dlc_) +{ + uint32_t recid = 0; + if ((_id >= 0x3E0U) && (_id < 0x3FFU)) { + if ((_id >= 0x3E0U) && (_id < 0x3F0U)) { + if ((_id >= 0x3E0U) && (_id < 0x3E3U)) { + if (_id == 0x3E0U) { + recid = Unpack_dbg_Logic_State_candb_dbg(&(_m->dbg_Logic_State), _d, dlc_); + } else { + if (_id == 0x3E1U) { + recid = Unpack_dbg_Logic_KM_Status_candb_dbg(&(_m->dbg_Logic_KM_Status), _d, dlc_); + } else if (_id == 0x3E2U) { + recid = Unpack_dbg_Logic_Valve_candb_dbg(&(_m->dbg_Logic_Valve), _d, dlc_); + } + } + } else { + if ((_id >= 0x3E3U) && (_id < 0x3E5U)) { + if (_id == 0x3E3U) { + recid = Unpack_dbg_Logic_Blower_candb_dbg(&(_m->dbg_Logic_Blower), _d, dlc_); + } else if (_id == 0x3E4U) { + recid = Unpack_dbg_Logic_Ac_candb_dbg(&(_m->dbg_Logic_Ac), _d, dlc_); + } + } else { + if (_id == 0x3E5U) { + recid = Unpack_dbg_Logic_Rec_candb_dbg(&(_m->dbg_Logic_Rec), _d, dlc_); + } else if (_id == 0x3E6U) { + recid = Unpack_dbg_DiffBlr_ValveOpen_candb_dbg(&(_m->dbg_DiffBlr_ValveOpen), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x3F0U) && (_id < 0x3F8U)) { + if ((_id >= 0x3F0U) && (_id < 0x3F2U)) { + if (_id == 0x3F0U) { + recid = Unpack_dbg_Act0_candb_dbg(&(_m->dbg_Act0), _d, dlc_); + } else if (_id == 0x3F1U) { + recid = Unpack_dbg_Act1_candb_dbg(&(_m->dbg_Act1), _d, dlc_); + } + } else { + if (_id == 0x3F2U) { + recid = Unpack_dbg_Act2_candb_dbg(&(_m->dbg_Act2), _d, dlc_); + } else if (_id == 0x3F3U) { + recid = Unpack_dbg_Sen_Amb_candb_dbg(&(_m->dbg_Sen_Amb), _d, dlc_); + } + } + } else { + if ((_id >= 0x3F8U) && (_id < 0x3FCU)) { + if (_id == 0x3F8U) { + recid = Unpack_dbg_Sen_0_candb_dbg(&(_m->dbg_Sen_0), _d, dlc_); + } else if (_id == 0x3FBU) { + recid = Unpack_dbg_CCU_IO_candb_dbg(&(_m->dbg_CCU_IO), _d, dlc_); + } + } else { + if (_id == 0x3FCU) { + recid = Unpack_dbg_CCU_Info_candb_dbg(&(_m->dbg_CCU_Info), _d, dlc_); + } else if (_id == 0x3FDU) { + recid = Unpack_dbg_Drs_candb_dbg(&(_m->dbg_Drs), _d, dlc_); + } + } + } + } + } else { + if ((_id >= 0x3FFU) && (_id < 0x511U)) { + if ((_id >= 0x3FFU) && (_id < 0x504U)) { + if (_id == 0x3FFU) { + recid = Unpack_dbg_Sen_Incar_candb_dbg(&(_m->dbg_Sen_Incar), _d, dlc_); + } else { + if (_id == 0x401U) { + recid = Unpack_dbg_Info_Act1_candb_dbg(&(_m->dbg_Info_Act1), _d, dlc_); + } else if (_id == 0x402U) { + recid = Unpack_dbg_Info_Act2_candb_dbg(&(_m->dbg_Info_Act2), _d, dlc_); + } + } + } else { + if ((_id >= 0x504U) && (_id < 0x509U)) { + if (_id == 0x504U) { + recid = Unpack_dbg_Sen_Eva_candb_dbg(&(_m->dbg_Sen_Eva), _d, dlc_); + } else if (_id == 0x505U) { + recid = Unpack_dbg_Sen_Duct_candb_dbg(&(_m->dbg_Sen_Duct), _d, dlc_); + } + } else { + if (_id == 0x509U) { + recid = Unpack_dbg_Sen_Demist_candb_dbg(&(_m->dbg_Sen_Demist), _d, dlc_); + } else if (_id == 0x510U) { + recid = Unpack_dbg_LIN_AirQS_Stat_candb_dbg(&(_m->dbg_LIN_AirQS_Stat), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x511U) && (_id < 0x520U)) { + if ((_id >= 0x511U) && (_id < 0x514U)) { + if (_id == 0x511U) { + recid = Unpack_dbg_LIN_Aroma_Stat_candb_dbg(&(_m->dbg_LIN_Aroma_Stat), _d, dlc_); + } else if (_id == 0x513U) { + recid = Unpack_dbg_LIN_Ionizer_Stat_candb_dbg(&(_m->dbg_LIN_Ionizer_Stat), _d, dlc_); + } + } else { + if (_id == 0x514U) { + recid = Unpack_dbg_LIN_eTXV_Stat_candb_dbg(&(_m->dbg_LIN_eTXV_Stat), _d, dlc_); + } else if (_id == 0x518U) { + recid = Unpack_dbg_LIN_DRS_Stat_candb_dbg(&(_m->dbg_LIN_DRS_Stat), _d, dlc_); + } + } + } else { + if ((_id >= 0x520U) && (_id < 0x530U)) { + if (_id == 0x520U) { + recid = Unpack_dbg_Auto_AF_candb_dbg(&(_m->dbg_Auto_AF), _d, dlc_); + } else if (_id == 0x524U) { + recid = Unpack_dbg_Auto_Duct_candb_dbg(&(_m->dbg_Auto_Duct), _d, dlc_); + } + } else { + if (_id == 0x530U) { + recid = Unpack_dbg_Auto_Valve_Plus_candb_dbg(&(_m->dbg_Auto_Valve_Plus), _d, dlc_); + } else if (_id == 0x6BBU) { + recid = Unpack_XCP_CCU_TX_candb_dbg(&(_m->XCP_CCU_TX), _d, dlc_); + } + } + } + } + } + + return recid; +} + diff --git a/MODULES/HVAC_M7_CAN_DBG_MATRIX/butl/vector__xxx_candb_dbg-binutil.h b/MODULES/HVAC_M7_CAN_DBG_MATRIX/butl/vector__xxx_candb_dbg-binutil.h new file mode 100644 index 0000000..c5f14de --- /dev/null +++ b/MODULES/HVAC_M7_CAN_DBG_MATRIX/butl/vector__xxx_candb_dbg-binutil.h @@ -0,0 +1,59 @@ +// Generator version : v3.1 +// DBC filename : CCUdbg.dbc +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dbccodeconf.h" + +#include "candb_dbg.h" + +typedef struct +{ + dbg_Logic_State_t dbg_Logic_State; + dbg_Logic_KM_Status_t dbg_Logic_KM_Status; + dbg_Logic_Valve_t dbg_Logic_Valve; + dbg_Logic_Blower_t dbg_Logic_Blower; + dbg_Logic_Ac_t dbg_Logic_Ac; + dbg_Logic_Rec_t dbg_Logic_Rec; + dbg_DiffBlr_ValveOpen_t dbg_DiffBlr_ValveOpen; + dbg_Act0_t dbg_Act0; + dbg_Act1_t dbg_Act1; + dbg_Act2_t dbg_Act2; + dbg_Sen_Amb_t dbg_Sen_Amb; + dbg_Sen_0_t dbg_Sen_0; + dbg_CCU_IO_t dbg_CCU_IO; + dbg_CCU_Info_t dbg_CCU_Info; + dbg_Drs_t dbg_Drs; + dbg_Sen_Incar_t dbg_Sen_Incar; + dbg_Info_Act1_t dbg_Info_Act1; + dbg_Info_Act2_t dbg_Info_Act2; + dbg_Sen_Eva_t dbg_Sen_Eva; + dbg_Sen_Duct_t dbg_Sen_Duct; + dbg_Sen_Demist_t dbg_Sen_Demist; + dbg_LIN_AirQS_Stat_t dbg_LIN_AirQS_Stat; + dbg_LIN_Aroma_Stat_t dbg_LIN_Aroma_Stat; + dbg_LIN_Ionizer_Stat_t dbg_LIN_Ionizer_Stat; + dbg_LIN_eTXV_Stat_t dbg_LIN_eTXV_Stat; + dbg_LIN_DRS_Stat_t dbg_LIN_DRS_Stat; + dbg_Auto_AF_t dbg_Auto_AF; + dbg_Auto_Duct_t dbg_Auto_Duct; + dbg_Auto_Valve_Plus_t dbg_Auto_Valve_Plus; + XCP_CCU_TX_t XCP_CCU_TX; +} vector__xxx_candb_dbg_rx_t; + +// There is no any TX mapped massage. + +uint32_t vector__xxx_candb_dbg_Receive(vector__xxx_candb_dbg_rx_t* m, const uint8_t* d, uint32_t msgid, uint8_t dlc); + +#ifdef __DEF_VECTOR__XXX_CANDB_DBG__ + +extern vector__xxx_candb_dbg_rx_t vector__xxx_candb_dbg_rx; + +#endif // __DEF_VECTOR__XXX_CANDB_DBG__ + +#ifdef __cplusplus +} +#endif diff --git a/MODULES/HVAC_M7_CAN_DBG_MATRIX/conf/candb_dbg-config.h b/MODULES/HVAC_M7_CAN_DBG_MATRIX/conf/candb_dbg-config.h new file mode 100644 index 0000000..b21a6ad --- /dev/null +++ b/MODULES/HVAC_M7_CAN_DBG_MATRIX/conf/candb_dbg-config.h @@ -0,0 +1,130 @@ +// Generator version : v3.1 +// DBC filename : CCUdbg.dbc +#pragma once + +/* include common dbccode configurations */ +#include "dbccodeconf.h" + +#define __DEF_CCU_CANDB_DBG__ +/* ------------------------------------------------------------------------- * + This define enables using CAN message structs with bit-fielded signals + layout. + + Note(!): bit-feild was not tested properly. */ + +/* #define CANDB_DBG_USE_BITS_SIGNAL */ + + +/* ------------------------------------------------------------------------- * + This macro enables using CAN message descriptive struct packing functions + (by default signature of pack function intakes a few simple typed params + for loading data, len, etc). To compile you need to define the struct + __CoderDbcCanFrame_t__ which must have fields: + + u32 MsgId (CAN Frame message ID) + u8 DLC (CAN Frame payload length field) + u8 Data[8] (CAN Frame payload data) + u8 IDE (CAN Frame Extended (1) / Standard (0) ID type) + + This struct definition have to be placed (or be included) in dbccodeconf.h */ + +/* #define CANDB_DBG_USE_CANSTRUCT */ + + +/* ------------------------------------------------------------------------- * + All the signals which have values of factor != 1 or offset != 0 + will be named in message struct with posfix '_ro'. Pack to payload + operations will be made on this signal value as well as unpack from payload. + + USE_SIGFLOAT macro makes some difference: + + 1. All the '_ro' fields will have a pair field with '_phys' postfix. + If only offset != 0 is true then the type of '_phys' signal is the same + as '_ro' signal. In other case the type will be @sigfloat_t which + have to be defined in user dbccodeconf.h + + 2. In pack function '_ro' signal will be rewritten by '_phys' signal, which + requires from user to use ONLY '_phys' signal for packing frame + + 3. In unpack function '_phys' signal will be written by '_ro' signal. + User have to use '_phys' signal to read physical value. */ + +/* #define CANDB_DBG_USE_SIGFLOAT */ + + +/* ------------------------------------------------------------------------- * + Note(!) that the "canmonitorutil.h" must be accessed in include path: + + This macro adds: + + - monitor field @mon1 to message struct + + - capture system tick in unpack function and save value to mon1 field + to provide to user better missing frame detection code. For this case + user must provide function declared in canmonitorutil.h - GetSysTick() + which may return 1ms uptime. + + - calling function FMon_*** (from 'fmon' driver) inside unpack function + which is empty by default and have to be filled by user if + tests for DLC, rolling, checksum are necessary */ + +/* #define CANDB_DBG_USE_DIAG_MONITORS */ + + +/* ------------------------------------------------------------------------- * + When monitor using is enabled (CANDB_DBG_USE_DIAG_MONITORS) and define below + uncommented, additional signal will be added to message struct. ***_expt: + expected rolling counter, to perform monitoring rolling counter sequence + automatically (result may be tested in dedicated Fmon_*** function) */ + +/* #define CANDB_DBG_AUTO_ROLL */ + + +/* ------------------------------------------------------------------------- * + When monitor using is enabled (CANDB_DBG_USE_DIAG_MONITORS) and define below + uncommented, frame checksum signal may be handled automatically. + + The signal which may be marked as checksum signal must have substring + with next format: + + + where: + + - "Checksum": constant marker word + + - "XOR8": type of method, this text will be passed to GetFrameHash + (canmonitorutil.h) function as is, the best use case is to define 'enum + DbcCanCrcMethods' in canmonitorutil.h file with all possible + checksum algorithms (e.g. XOR8, XOR4 etc) + + - "3": optional value that will be passed to GetFrameHash as integer value + + Function GetFrameHash have to be implemented by user + + In pack function checksum signal will be calculated automatically + and loaded to payload + + In unpack function checksum signal is checked with calculated. + (result may be tested in dedicated Fmon_*** function). */ + +/* #define CANDB_DBG_AUTO_CSM */ + + +/* ------------------------------------------------------------------------- * + FMon handling model can be build in two ways: + + 1 - Default. In this case when specific frame unpack is called the + specific FMon_{Frame name}_{driver name} functoin will be called. + User's code scope has to define each of these functions. Each function is + responsible for the error handling of one frame + + 2 - MONO. In this case there is only one function to perform any frame + monitoring. This function has to be implemented in the user's code scope. + This function is named as FMon_MONO_{driver name}. It takes frame id + which can be used for selection of the logic for a frame monitoring. + This mode costs a bit more in runtime but when you often edit you DBC and you + have more than one project it could be more maintanable (there is + no necessity to replace source code) + + For using MONO way uncomment line below */ +/* #define CANDB_DBG_USE_MONO_FMON */ diff --git a/MODULES/HVAC_M7_CAN_DBG_MATRIX/conf/dbccodeconf.h b/MODULES/HVAC_M7_CAN_DBG_MATRIX/conf/dbccodeconf.h new file mode 100644 index 0000000..e1c7eff --- /dev/null +++ b/MODULES/HVAC_M7_CAN_DBG_MATRIX/conf/dbccodeconf.h @@ -0,0 +1,31 @@ +// Generator version : v3.1 +#pragma once + +#include + +// when USE_SIGFLOAT enabed the sigfloat_t must be defined +// typedef double sigfloat_t; + +// when USE_CANSTRUCT enabled __CoderDbcCanFrame_t__ must be defined +// #include "{header_with_can_struct}" +// typedef {can_struct} __CoderDbcCanFrame_t__; + +// if you need to allocate rx and tx messages structs put the allocation macro here +// #define __DEF_{your_driver_name}__ + +// defualt @__ext_sig__ help types definition + +typedef uint32_t ubitext_t; +typedef int32_t bitext_t; + +// To provide a way to make missing control correctly you +// have to define macro @GetSystemTick() which has to +// return kind of tick counter (e.g. 1 ms ticker) + +// #define GetSystemTick() __get__tick__() + +// To provide a way to calculate hash (crc) for CAN +// frame's data field you have to define macro @GetFrameHash + +// #define GetFrameHash(a,b,c,d,e) __get_hash__(a,b,c,d,e) + diff --git a/MODULES/HVAC_M7_CAN_DBG_MATRIX/inc/canmonitorutil.h b/MODULES/HVAC_M7_CAN_DBG_MATRIX/inc/canmonitorutil.h new file mode 100644 index 0000000..2289caa --- /dev/null +++ b/MODULES/HVAC_M7_CAN_DBG_MATRIX/inc/canmonitorutil.h @@ -0,0 +1,54 @@ +// Generator version : v3.1 +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +// declare here all availible checksum algorithms +typedef enum +{ + // XOR8 = 0, + // XOR4 = 1, + // etc + + // it is up to user to have or to skip final enum value - @CRC_ALG_COUNT + CRC_ALG_COUNT +} DbcCanCrcMethods; + +typedef struct +{ + // @last_cycle keeps tick-value when last frame was received + uint32_t last_cycle; + + // @timeout_cycle keeps maximum timeout for frame, user responsibility + // to init this field and use it in missing frame monitoring function + uint32_t timeout_cycle; + + // @frame_cnt keeps count of all the received frames + uint32_t frame_cnt; + + // setting up @roll_error bit indicates roll counting fail. + // Bit is not clearing automatically! + uint32_t roll_error : 1; + + // setting up @checksum_error bit indicates checksum checking failure. + // Bit is not clearing automatically! + uint32_t csm_error : 1; + + // setting up @cycle_error bit indicates that time was overrunned. + // Bit is not clearing automatically! + uint32_t cycle_error : 1; + + // setting up @dlc_error bit indicates that the actual length of + // CAN frame is less then defined by CAN matrix! + uint32_t dlc_error : 1; + +} FrameMonitor_t; + +#ifdef __cplusplus +} +#endif + diff --git a/MODULES/HVAC_M7_CAN_DBG_MATRIX/lib/candb_dbg-fmon.h b/MODULES/HVAC_M7_CAN_DBG_MATRIX/lib/candb_dbg-fmon.h new file mode 100644 index 0000000..7b61f91 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_DBG_MATRIX/lib/candb_dbg-fmon.h @@ -0,0 +1,136 @@ +// Generator version : v3.1 +// DBC filename : CCUdbg.dbc +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +// DBC file version +#define VER_CANDB_DBG_MAJ_FMON (0U) +#define VER_CANDB_DBG_MIN_FMON (0U) + +#include "candb_dbg-config.h" + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + +#include "canmonitorutil.h" +/* +This file contains the prototypes of all the functions that will be called +from each Unpack_*name* function to detect DBC related errors +It is the user responsibility to defined these functions in the +separated .c file. If it won't be done the linkage error will happen +*/ + +#ifdef CANDB_DBG_USE_MONO_FMON + +void _FMon_MONO_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid); + +#define FMon_dbg_Logic_State_candb_dbg(x, y) _FMon_MONO_candb_dbg((x), (y)) +#define FMon_dbg_Logic_KM_Status_candb_dbg(x, y) _FMon_MONO_candb_dbg((x), (y)) +#define FMon_dbg_Logic_Valve_candb_dbg(x, y) _FMon_MONO_candb_dbg((x), (y)) +#define FMon_dbg_Logic_Blower_candb_dbg(x, y) _FMon_MONO_candb_dbg((x), (y)) +#define FMon_dbg_Logic_Ac_candb_dbg(x, y) _FMon_MONO_candb_dbg((x), (y)) +#define FMon_dbg_Logic_Rec_candb_dbg(x, y) _FMon_MONO_candb_dbg((x), (y)) +#define FMon_dbg_DiffBlr_ValveOpen_candb_dbg(x, y) _FMon_MONO_candb_dbg((x), (y)) +#define FMon_dbg_Act0_candb_dbg(x, y) _FMon_MONO_candb_dbg((x), (y)) +#define FMon_dbg_Act1_candb_dbg(x, y) _FMon_MONO_candb_dbg((x), (y)) +#define FMon_dbg_Act2_candb_dbg(x, y) _FMon_MONO_candb_dbg((x), (y)) +#define FMon_dbg_Sen_Amb_candb_dbg(x, y) _FMon_MONO_candb_dbg((x), (y)) +#define FMon_dbg_Sen_0_candb_dbg(x, y) _FMon_MONO_candb_dbg((x), (y)) +#define FMon_dbg_CCU_IO_candb_dbg(x, y) _FMon_MONO_candb_dbg((x), (y)) +#define FMon_dbg_CCU_Info_candb_dbg(x, y) _FMon_MONO_candb_dbg((x), (y)) +#define FMon_dbg_Drs_candb_dbg(x, y) _FMon_MONO_candb_dbg((x), (y)) +#define FMon_dbg_Sen_Incar_candb_dbg(x, y) _FMon_MONO_candb_dbg((x), (y)) +#define FMon_dbg_Cmd_Act_Information_candb_dbg(x, y) _FMon_MONO_candb_dbg((x), (y)) +#define FMon_dbg_Info_Act1_candb_dbg(x, y) _FMon_MONO_candb_dbg((x), (y)) +#define FMon_dbg_Info_Act2_candb_dbg(x, y) _FMon_MONO_candb_dbg((x), (y)) +#define FMon_dbg_Sen_Eva_candb_dbg(x, y) _FMon_MONO_candb_dbg((x), (y)) +#define FMon_dbg_Sen_Duct_candb_dbg(x, y) _FMon_MONO_candb_dbg((x), (y)) +#define FMon_dbg_Sen_Demist_candb_dbg(x, y) _FMon_MONO_candb_dbg((x), (y)) +#define FMon_dbg_LIN_AirQS_Stat_candb_dbg(x, y) _FMon_MONO_candb_dbg((x), (y)) +#define FMon_dbg_LIN_Aroma_Stat_candb_dbg(x, y) _FMon_MONO_candb_dbg((x), (y)) +#define FMon_dbg_LIN_Ionizer_Stat_candb_dbg(x, y) _FMon_MONO_candb_dbg((x), (y)) +#define FMon_dbg_LIN_eTXV_Stat_candb_dbg(x, y) _FMon_MONO_candb_dbg((x), (y)) +#define FMon_dbg_LIN_DRS_Stat_candb_dbg(x, y) _FMon_MONO_candb_dbg((x), (y)) +#define FMon_dbg_Auto_AF_candb_dbg(x, y) _FMon_MONO_candb_dbg((x), (y)) +#define FMon_dbg_Auto_Duct_candb_dbg(x, y) _FMon_MONO_candb_dbg((x), (y)) +#define FMon_dbg_Auto_Valve_Plus_candb_dbg(x, y) _FMon_MONO_candb_dbg((x), (y)) +#define FMon_XCP_CCU_RX_candb_dbg(x, y) _FMon_MONO_candb_dbg((x), (y)) +#define FMon_XCP_CCU_TX_candb_dbg(x, y) _FMon_MONO_candb_dbg((x), (y)) + +#else + +void _FMon_dbg_Logic_State_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_dbg_Logic_KM_Status_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_dbg_Logic_Valve_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_dbg_Logic_Blower_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_dbg_Logic_Ac_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_dbg_Logic_Rec_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_dbg_DiffBlr_ValveOpen_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_dbg_Act0_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_dbg_Act1_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_dbg_Act2_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_dbg_Sen_Amb_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_dbg_Sen_0_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_dbg_CCU_IO_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_dbg_CCU_Info_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_dbg_Drs_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_dbg_Sen_Incar_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_dbg_Cmd_Act_Information_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_dbg_Info_Act1_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_dbg_Info_Act2_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_dbg_Sen_Eva_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_dbg_Sen_Duct_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_dbg_Sen_Demist_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_dbg_LIN_AirQS_Stat_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_dbg_LIN_Aroma_Stat_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_dbg_LIN_Ionizer_Stat_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_dbg_LIN_eTXV_Stat_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_dbg_LIN_DRS_Stat_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_dbg_Auto_AF_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_dbg_Auto_Duct_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_dbg_Auto_Valve_Plus_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_XCP_CCU_RX_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_XCP_CCU_TX_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid); + +#define FMon_dbg_Logic_State_candb_dbg(x, y) _FMon_dbg_Logic_State_candb_dbg((x), (y)) +#define FMon_dbg_Logic_KM_Status_candb_dbg(x, y) _FMon_dbg_Logic_KM_Status_candb_dbg((x), (y)) +#define FMon_dbg_Logic_Valve_candb_dbg(x, y) _FMon_dbg_Logic_Valve_candb_dbg((x), (y)) +#define FMon_dbg_Logic_Blower_candb_dbg(x, y) _FMon_dbg_Logic_Blower_candb_dbg((x), (y)) +#define FMon_dbg_Logic_Ac_candb_dbg(x, y) _FMon_dbg_Logic_Ac_candb_dbg((x), (y)) +#define FMon_dbg_Logic_Rec_candb_dbg(x, y) _FMon_dbg_Logic_Rec_candb_dbg((x), (y)) +#define FMon_dbg_DiffBlr_ValveOpen_candb_dbg(x, y) _FMon_dbg_DiffBlr_ValveOpen_candb_dbg((x), (y)) +#define FMon_dbg_Act0_candb_dbg(x, y) _FMon_dbg_Act0_candb_dbg((x), (y)) +#define FMon_dbg_Act1_candb_dbg(x, y) _FMon_dbg_Act1_candb_dbg((x), (y)) +#define FMon_dbg_Act2_candb_dbg(x, y) _FMon_dbg_Act2_candb_dbg((x), (y)) +#define FMon_dbg_Sen_Amb_candb_dbg(x, y) _FMon_dbg_Sen_Amb_candb_dbg((x), (y)) +#define FMon_dbg_Sen_0_candb_dbg(x, y) _FMon_dbg_Sen_0_candb_dbg((x), (y)) +#define FMon_dbg_CCU_IO_candb_dbg(x, y) _FMon_dbg_CCU_IO_candb_dbg((x), (y)) +#define FMon_dbg_CCU_Info_candb_dbg(x, y) _FMon_dbg_CCU_Info_candb_dbg((x), (y)) +#define FMon_dbg_Drs_candb_dbg(x, y) _FMon_dbg_Drs_candb_dbg((x), (y)) +#define FMon_dbg_Sen_Incar_candb_dbg(x, y) _FMon_dbg_Sen_Incar_candb_dbg((x), (y)) +#define FMon_dbg_Cmd_Act_Information_candb_dbg(x, y) _FMon_dbg_Cmd_Act_Information_candb_dbg((x), (y)) +#define FMon_dbg_Info_Act1_candb_dbg(x, y) _FMon_dbg_Info_Act1_candb_dbg((x), (y)) +#define FMon_dbg_Info_Act2_candb_dbg(x, y) _FMon_dbg_Info_Act2_candb_dbg((x), (y)) +#define FMon_dbg_Sen_Eva_candb_dbg(x, y) _FMon_dbg_Sen_Eva_candb_dbg((x), (y)) +#define FMon_dbg_Sen_Duct_candb_dbg(x, y) _FMon_dbg_Sen_Duct_candb_dbg((x), (y)) +#define FMon_dbg_Sen_Demist_candb_dbg(x, y) _FMon_dbg_Sen_Demist_candb_dbg((x), (y)) +#define FMon_dbg_LIN_AirQS_Stat_candb_dbg(x, y) _FMon_dbg_LIN_AirQS_Stat_candb_dbg((x), (y)) +#define FMon_dbg_LIN_Aroma_Stat_candb_dbg(x, y) _FMon_dbg_LIN_Aroma_Stat_candb_dbg((x), (y)) +#define FMon_dbg_LIN_Ionizer_Stat_candb_dbg(x, y) _FMon_dbg_LIN_Ionizer_Stat_candb_dbg((x), (y)) +#define FMon_dbg_LIN_eTXV_Stat_candb_dbg(x, y) _FMon_dbg_LIN_eTXV_Stat_candb_dbg((x), (y)) +#define FMon_dbg_LIN_DRS_Stat_candb_dbg(x, y) _FMon_dbg_LIN_DRS_Stat_candb_dbg((x), (y)) +#define FMon_dbg_Auto_AF_candb_dbg(x, y) _FMon_dbg_Auto_AF_candb_dbg((x), (y)) +#define FMon_dbg_Auto_Duct_candb_dbg(x, y) _FMon_dbg_Auto_Duct_candb_dbg((x), (y)) +#define FMon_dbg_Auto_Valve_Plus_candb_dbg(x, y) _FMon_dbg_Auto_Valve_Plus_candb_dbg((x), (y)) +#define FMon_XCP_CCU_RX_candb_dbg(x, y) _FMon_XCP_CCU_RX_candb_dbg((x), (y)) +#define FMon_XCP_CCU_TX_candb_dbg(x, y) _FMon_XCP_CCU_TX_candb_dbg((x), (y)) + +#endif + +#endif // CANDB_DBG_USE_DIAG_MONITORS + +#ifdef __cplusplus +} +#endif diff --git a/MODULES/HVAC_M7_CAN_DBG_MATRIX/lib/candb_dbg.c b/MODULES/HVAC_M7_CAN_DBG_MATRIX/lib/candb_dbg.c new file mode 100644 index 0000000..81ebb5f --- /dev/null +++ b/MODULES/HVAC_M7_CAN_DBG_MATRIX/lib/candb_dbg.c @@ -0,0 +1,2717 @@ +// Generator version : v3.1 +// DBC filename : CCUdbg.dbc +#include "candb_dbg.h" + + +// DBC file version +#if (VER_CANDB_DBG_MAJ != (0U)) || (VER_CANDB_DBG_MIN != (0U)) +#error The CANDB_DBG dbc source files have different versions +#endif + +#ifdef CANDB_DBG_USE_DIAG_MONITORS +// Function prototypes to be called each time CAN frame is unpacked +// FMon function may detect RC, CRC or DLC violation +#include "candb_dbg-fmon.h" + +#endif // CANDB_DBG_USE_DIAG_MONITORS + +// This macro guard for the case when you need to enable +// using diag monitors but there is no necessity in proper +// SysTick provider. For providing one you need define macro +// before this line - in dbccodeconf.h + +#ifndef GetSystemTick +#define GetSystemTick() (0u) +#endif + +// This macro guard is for the case when you want to build +// app with enabled optoin auto CSM, but don't yet have +// proper getframehash implementation + +#ifndef GetFrameHash +#define GetFrameHash(a,b,c,d,e) (0u) +#endif + +// This function performs extension of sign for the signals +// whose bit width value is not aligned to one of power of 2 or less than 8. +// The types 'bitext_t' and 'ubitext_t' define the biggest bit width which +// can be correctly handled. You need to select type which can contain +// n+1 bits where n is the largest signed signal width. For example if +// the most wide signed signal has a width of 31 bits you need to set +// bitext_t as int32_t and ubitext_t as uint32_t +// Defined these typedefs in @dbccodeconf.h or locally in 'dbcdrvname'-config.h +static bitext_t __ext_sig__(ubitext_t val, uint8_t bits) +{ + ubitext_t const m = (ubitext_t) (1u << (bits - 1u)); + return ((val ^ m) - m); +} + +uint32_t Unpack_dbg_Logic_State_candb_dbg(dbg_Logic_State_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Logic_Operation_Mode = (uint8_t) ( (_d[0] & (0x03U)) ); + _m->Logic_Amb_Level = (uint8_t) ( ((_d[0] >> 2U) & (0x0FU)) ); + _m->Logic_AutoDemist_Electric = (uint8_t) ( ((_d[0] >> 6U) & (0x01U)) ); + _m->Logic_AutoDemist_Garage = (uint8_t) ( ((_d[0] >> 7U) & (0x01U)) ); + _m->Logic_AutoDemist_Lv_Summer = (uint8_t) ( (_d[1] & (0x0FU)) ); + _m->Logic_RemoteStart = (uint8_t) ( ((_d[1] >> 4U) & (0x03U)) ); + _m->Logic_Rest_Mode = (uint8_t) ( ((_d[1] >> 6U) & (0x03U)) ); + _m->Logic_LoHi_Front = (uint8_t) ( (_d[2] & (0xFFU)) ); + _m->Logic_LoHi_Rear = (uint8_t) ( (_d[3] & (0xFFU)) ); + _m->Logic_2WayValve_Status = (uint8_t) ( (_d[4] & (0x03U)) ); + _m->Logic_Full_Auto_FL = (uint8_t) ( ((_d[4] >> 2U) & (0x01U)) ); + _m->Logic_Full_Auto_FR = (uint8_t) ( ((_d[4] >> 3U) & (0x01U)) ); + _m->Logic_Full_Auto_RL = (uint8_t) ( ((_d[4] >> 4U) & (0x01U)) ); + _m->Logic_Full_Auto_RR = (uint8_t) ( ((_d[4] >> 5U) & (0x01U)) ); + _m->Logic_Full_MaxAc = (uint8_t) ( ((_d[4] >> 6U) & (0x01U)) ); + _m->Logic_Full_MaxDef = (uint8_t) ( ((_d[4] >> 7U) & (0x01U)) ); + _m->Logic_Start_Ctrl_Front = (uint8_t) ( (_d[5] & (0x07U)) ); + _m->Logic_Start_Ctrl_Rear = (uint8_t) ( ((_d[5] >> 3U) & (0x07U)) ); + _m->Logic_Valve_Use_DiffBlr_R2 = (uint8_t) ( ((_d[5] >> 6U) & (0x01U)) ); + _m->Logic_Duct_WaitCorrection_FRL = (uint8_t) ( (_d[6] & (0x03U)) ); + _m->Logic_Duct_WaitCorrection_FLL = (uint8_t) ( ((_d[6] >> 2U) & (0x03U)) ); + _m->Logic_AutoDemist_Lv_Winter = (uint8_t) ( ((_d[6] >> 4U) & (0x0FU)) ); + _m->Logic_AF_WaitCorrection_FL = (uint8_t) ( (_d[7] & (0x03U)) ); + _m->Logic_AF_WaitCorrection_FR = (uint8_t) ( ((_d[7] >> 2U) & (0x03U)) ); + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < dbg_Logic_State_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_dbg_Logic_State_candb_dbg(&_m->mon1, dbg_Logic_State_CANID); +#endif // CANDB_DBG_USE_DIAG_MONITORS + + return dbg_Logic_State_CANID; +} + +#ifdef CANDB_DBG_USE_CANSTRUCT + +uint32_t Pack_dbg_Logic_State_candb_dbg(dbg_Logic_State_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Logic_State_DLC); cframe->Data[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->Logic_Operation_Mode & (0x03U)) | ((_m->Logic_Amb_Level & (0x0FU)) << 2U) | ((_m->Logic_AutoDemist_Electric & (0x01U)) << 6U) | ((_m->Logic_AutoDemist_Garage & (0x01U)) << 7U) ); + cframe->Data[1] |= (uint8_t) ( (_m->Logic_AutoDemist_Lv_Summer & (0x0FU)) | ((_m->Logic_RemoteStart & (0x03U)) << 4U) | ((_m->Logic_Rest_Mode & (0x03U)) << 6U) ); + cframe->Data[2] |= (uint8_t) ( (_m->Logic_LoHi_Front & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->Logic_LoHi_Rear & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->Logic_2WayValve_Status & (0x03U)) | ((_m->Logic_Full_Auto_FL & (0x01U)) << 2U) | ((_m->Logic_Full_Auto_FR & (0x01U)) << 3U) | ((_m->Logic_Full_Auto_RL & (0x01U)) << 4U) | ((_m->Logic_Full_Auto_RR & (0x01U)) << 5U) | ((_m->Logic_Full_MaxAc & (0x01U)) << 6U) | ((_m->Logic_Full_MaxDef & (0x01U)) << 7U) ); + cframe->Data[5] |= (uint8_t) ( (_m->Logic_Start_Ctrl_Front & (0x07U)) | ((_m->Logic_Start_Ctrl_Rear & (0x07U)) << 3U) | ((_m->Logic_Valve_Use_DiffBlr_R2 & (0x01U)) << 6U) ); + cframe->Data[6] |= (uint8_t) ( (_m->Logic_Duct_WaitCorrection_FRL & (0x03U)) | ((_m->Logic_Duct_WaitCorrection_FLL & (0x03U)) << 2U) | ((_m->Logic_AutoDemist_Lv_Winter & (0x0FU)) << 4U) ); + cframe->Data[7] |= (uint8_t) ( (_m->Logic_AF_WaitCorrection_FL & (0x03U)) | ((_m->Logic_AF_WaitCorrection_FR & (0x03U)) << 2U) ); + + cframe->MsgId = (uint32_t) dbg_Logic_State_CANID; + cframe->DLC = (uint8_t) dbg_Logic_State_DLC; + cframe->IDE = (uint8_t) dbg_Logic_State_IDE; + return dbg_Logic_State_CANID; +} + +#else + +uint32_t Pack_dbg_Logic_State_candb_dbg(dbg_Logic_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Logic_State_DLC); _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->Logic_Operation_Mode & (0x03U)) | ((_m->Logic_Amb_Level & (0x0FU)) << 2U) | ((_m->Logic_AutoDemist_Electric & (0x01U)) << 6U) | ((_m->Logic_AutoDemist_Garage & (0x01U)) << 7U) ); + _d[1] |= (uint8_t) ( (_m->Logic_AutoDemist_Lv_Summer & (0x0FU)) | ((_m->Logic_RemoteStart & (0x03U)) << 4U) | ((_m->Logic_Rest_Mode & (0x03U)) << 6U) ); + _d[2] |= (uint8_t) ( (_m->Logic_LoHi_Front & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->Logic_LoHi_Rear & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->Logic_2WayValve_Status & (0x03U)) | ((_m->Logic_Full_Auto_FL & (0x01U)) << 2U) | ((_m->Logic_Full_Auto_FR & (0x01U)) << 3U) | ((_m->Logic_Full_Auto_RL & (0x01U)) << 4U) | ((_m->Logic_Full_Auto_RR & (0x01U)) << 5U) | ((_m->Logic_Full_MaxAc & (0x01U)) << 6U) | ((_m->Logic_Full_MaxDef & (0x01U)) << 7U) ); + _d[5] |= (uint8_t) ( (_m->Logic_Start_Ctrl_Front & (0x07U)) | ((_m->Logic_Start_Ctrl_Rear & (0x07U)) << 3U) | ((_m->Logic_Valve_Use_DiffBlr_R2 & (0x01U)) << 6U) ); + _d[6] |= (uint8_t) ( (_m->Logic_Duct_WaitCorrection_FRL & (0x03U)) | ((_m->Logic_Duct_WaitCorrection_FLL & (0x03U)) << 2U) | ((_m->Logic_AutoDemist_Lv_Winter & (0x0FU)) << 4U) ); + _d[7] |= (uint8_t) ( (_m->Logic_AF_WaitCorrection_FL & (0x03U)) | ((_m->Logic_AF_WaitCorrection_FR & (0x03U)) << 2U) ); + + *_len = (uint8_t) dbg_Logic_State_DLC; + *_ide = (uint8_t) dbg_Logic_State_IDE; + return dbg_Logic_State_CANID; +} + +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Logic_KM_Status_candb_dbg(dbg_Logic_KM_Status_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Logic_KM_Mode_FL = (uint8_t) ( (_d[0] & (0x0FU)) ); + _m->Logic_KM_Mode_FR = (uint8_t) ( ((_d[0] >> 4U) & (0x0FU)) ); + _m->Logic_KM_Mode_RL = (uint8_t) ( (_d[1] & (0x0FU)) ); + _m->Logic_KM_Mode_RR = (uint8_t) ( ((_d[1] >> 4U) & (0x0FU)) ); + _m->Logic_KM_Blower_FL = (uint8_t) ( (_d[2] & (0x0FU)) ); + _m->Logic_KM_Blower_FR = (uint8_t) ( ((_d[2] >> 4U) & (0x0FU)) ); + _m->Logic_KM_Blower_RL = (uint8_t) ( (_d[3] & (0x0FU)) ); + _m->Logic_KM_Blower_RR = (uint8_t) ( ((_d[3] >> 4U) & (0x0FU)) ); + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < dbg_Logic_KM_Status_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_dbg_Logic_KM_Status_candb_dbg(&_m->mon1, dbg_Logic_KM_Status_CANID); +#endif // CANDB_DBG_USE_DIAG_MONITORS + + return dbg_Logic_KM_Status_CANID; +} + +#ifdef CANDB_DBG_USE_CANSTRUCT + +uint32_t Pack_dbg_Logic_KM_Status_candb_dbg(dbg_Logic_KM_Status_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Logic_KM_Status_DLC); cframe->Data[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->Logic_KM_Mode_FL & (0x0FU)) | ((_m->Logic_KM_Mode_FR & (0x0FU)) << 4U) ); + cframe->Data[1] |= (uint8_t) ( (_m->Logic_KM_Mode_RL & (0x0FU)) | ((_m->Logic_KM_Mode_RR & (0x0FU)) << 4U) ); + cframe->Data[2] |= (uint8_t) ( (_m->Logic_KM_Blower_FL & (0x0FU)) | ((_m->Logic_KM_Blower_FR & (0x0FU)) << 4U) ); + cframe->Data[3] |= (uint8_t) ( (_m->Logic_KM_Blower_RL & (0x0FU)) | ((_m->Logic_KM_Blower_RR & (0x0FU)) << 4U) ); + + cframe->MsgId = (uint32_t) dbg_Logic_KM_Status_CANID; + cframe->DLC = (uint8_t) dbg_Logic_KM_Status_DLC; + cframe->IDE = (uint8_t) dbg_Logic_KM_Status_IDE; + return dbg_Logic_KM_Status_CANID; +} + +#else + +uint32_t Pack_dbg_Logic_KM_Status_candb_dbg(dbg_Logic_KM_Status_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Logic_KM_Status_DLC); _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->Logic_KM_Mode_FL & (0x0FU)) | ((_m->Logic_KM_Mode_FR & (0x0FU)) << 4U) ); + _d[1] |= (uint8_t) ( (_m->Logic_KM_Mode_RL & (0x0FU)) | ((_m->Logic_KM_Mode_RR & (0x0FU)) << 4U) ); + _d[2] |= (uint8_t) ( (_m->Logic_KM_Blower_FL & (0x0FU)) | ((_m->Logic_KM_Blower_FR & (0x0FU)) << 4U) ); + _d[3] |= (uint8_t) ( (_m->Logic_KM_Blower_RL & (0x0FU)) | ((_m->Logic_KM_Blower_RR & (0x0FU)) << 4U) ); + + *_len = (uint8_t) dbg_Logic_KM_Status_DLC; + *_ide = (uint8_t) dbg_Logic_KM_Status_IDE; + return dbg_Logic_KM_Status_CANID; +} + +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Logic_Valve_candb_dbg(dbg_Logic_Valve_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Logic_Valve_Index_FL = (uint8_t) ( (_d[0] & (0xFFU)) ); + _m->Logic_Valve_Index_FR = (uint8_t) ( (_d[1] & (0xFFU)) ); + _m->Logic_Valve_Index_RL = (uint8_t) ( (_d[2] & (0xFFU)) ); + _m->Logic_Valve_Index_RR = (uint8_t) ( (_d[3] & (0xFFU)) ); + _m->Logic_Valve_Direction_FL = (uint8_t) ( (_d[4] & (0x0FU)) ); + _m->Logic_Valve_Direction_FR = (uint8_t) ( ((_d[4] >> 4U) & (0x0FU)) ); + _m->Logic_Valve_Direction_RL = (uint8_t) ( (_d[5] & (0x0FU)) ); + _m->Logic_Valve_Direction_RR = (uint8_t) ( ((_d[5] >> 4U) & (0x0FU)) ); + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < dbg_Logic_Valve_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_dbg_Logic_Valve_candb_dbg(&_m->mon1, dbg_Logic_Valve_CANID); +#endif // CANDB_DBG_USE_DIAG_MONITORS + + return dbg_Logic_Valve_CANID; +} + +#ifdef CANDB_DBG_USE_CANSTRUCT + +uint32_t Pack_dbg_Logic_Valve_candb_dbg(dbg_Logic_Valve_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Logic_Valve_DLC); cframe->Data[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->Logic_Valve_Index_FL & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->Logic_Valve_Index_FR & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->Logic_Valve_Index_RL & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->Logic_Valve_Index_RR & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->Logic_Valve_Direction_FL & (0x0FU)) | ((_m->Logic_Valve_Direction_FR & (0x0FU)) << 4U) ); + cframe->Data[5] |= (uint8_t) ( (_m->Logic_Valve_Direction_RL & (0x0FU)) | ((_m->Logic_Valve_Direction_RR & (0x0FU)) << 4U) ); + + cframe->MsgId = (uint32_t) dbg_Logic_Valve_CANID; + cframe->DLC = (uint8_t) dbg_Logic_Valve_DLC; + cframe->IDE = (uint8_t) dbg_Logic_Valve_IDE; + return dbg_Logic_Valve_CANID; +} + +#else + +uint32_t Pack_dbg_Logic_Valve_candb_dbg(dbg_Logic_Valve_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Logic_Valve_DLC); _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->Logic_Valve_Index_FL & (0xFFU)) ); + _d[1] |= (uint8_t) ( (_m->Logic_Valve_Index_FR & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->Logic_Valve_Index_RL & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->Logic_Valve_Index_RR & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->Logic_Valve_Direction_FL & (0x0FU)) | ((_m->Logic_Valve_Direction_FR & (0x0FU)) << 4U) ); + _d[5] |= (uint8_t) ( (_m->Logic_Valve_Direction_RL & (0x0FU)) | ((_m->Logic_Valve_Direction_RR & (0x0FU)) << 4U) ); + + *_len = (uint8_t) dbg_Logic_Valve_DLC; + *_ide = (uint8_t) dbg_Logic_Valve_IDE; + return dbg_Logic_Valve_CANID; +} + +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Logic_Blower_candb_dbg(dbg_Logic_Blower_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Logic_Blower_Step_FL = (uint8_t) ( (_d[0] & (0x0FU)) ); + _m->Logic_Blower_Step_FR = (uint8_t) ( ((_d[0] >> 4U) & (0x0FU)) ); + _m->Logic_Blower_Step_RL = (uint8_t) ( (_d[1] & (0x0FU)) ); + _m->Logic_Blower_Step_RR = (uint8_t) ( ((_d[1] >> 4U) & (0x0FU)) ); + _m->Logic_Blower_Pwm_Front = (uint8_t) ( (_d[2] & (0xFFU)) ); + _m->Logic_Blower_Pwm_Rear = (uint8_t) ( (_d[3] & (0xFFU)) ); + _m->Logic_Blower_AF_FL = (uint8_t) ( (_d[4] & (0xFFU)) ); + _m->Logic_Blower_AF_FR = (uint8_t) ( (_d[5] & (0xFFU)) ); + _m->Logic_Blower_AF_RL = (uint8_t) ( (_d[6] & (0xFFU)) ); + _m->Logic_Blower_AF_RR = (uint8_t) ( (_d[7] & (0xFFU)) ); + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < dbg_Logic_Blower_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_dbg_Logic_Blower_candb_dbg(&_m->mon1, dbg_Logic_Blower_CANID); +#endif // CANDB_DBG_USE_DIAG_MONITORS + + return dbg_Logic_Blower_CANID; +} + +#ifdef CANDB_DBG_USE_CANSTRUCT + +uint32_t Pack_dbg_Logic_Blower_candb_dbg(dbg_Logic_Blower_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Logic_Blower_DLC); cframe->Data[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->Logic_Blower_Step_FL & (0x0FU)) | ((_m->Logic_Blower_Step_FR & (0x0FU)) << 4U) ); + cframe->Data[1] |= (uint8_t) ( (_m->Logic_Blower_Step_RL & (0x0FU)) | ((_m->Logic_Blower_Step_RR & (0x0FU)) << 4U) ); + cframe->Data[2] |= (uint8_t) ( (_m->Logic_Blower_Pwm_Front & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->Logic_Blower_Pwm_Rear & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->Logic_Blower_AF_FL & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->Logic_Blower_AF_FR & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->Logic_Blower_AF_RL & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Logic_Blower_AF_RR & (0xFFU)) ); + + cframe->MsgId = (uint32_t) dbg_Logic_Blower_CANID; + cframe->DLC = (uint8_t) dbg_Logic_Blower_DLC; + cframe->IDE = (uint8_t) dbg_Logic_Blower_IDE; + return dbg_Logic_Blower_CANID; +} + +#else + +uint32_t Pack_dbg_Logic_Blower_candb_dbg(dbg_Logic_Blower_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Logic_Blower_DLC); _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->Logic_Blower_Step_FL & (0x0FU)) | ((_m->Logic_Blower_Step_FR & (0x0FU)) << 4U) ); + _d[1] |= (uint8_t) ( (_m->Logic_Blower_Step_RL & (0x0FU)) | ((_m->Logic_Blower_Step_RR & (0x0FU)) << 4U) ); + _d[2] |= (uint8_t) ( (_m->Logic_Blower_Pwm_Front & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->Logic_Blower_Pwm_Rear & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->Logic_Blower_AF_FL & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->Logic_Blower_AF_FR & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->Logic_Blower_AF_RL & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Logic_Blower_AF_RR & (0xFFU)) ); + + *_len = (uint8_t) dbg_Logic_Blower_DLC; + *_ide = (uint8_t) dbg_Logic_Blower_IDE; + return dbg_Logic_Blower_CANID; +} + +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Logic_Ac_candb_dbg(dbg_Logic_Ac_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Logic_Ac_Req_Front = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->Logic_Ac_Txv_Front = (uint8_t) ( ((_d[0] >> 1U) & (0x01U)) ); + _m->Logic_Ac_Txv_Rear = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + _m->Logic_Ac_Req_Rear = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + _m->Logic_Ac_Req_Chiller = (uint8_t) ( ((_d[0] >> 4U) & (0x01U)) ); + _m->Logic_Ac_Txv_Chiller = (uint8_t) ( ((_d[0] >> 5U) & (0x01U)) ); + _m->Logic_Ac_EvaCtrl = (uint8_t) ( (_d[1] & (0x0FU)) ); + _m->Logic_Ac_Comp_EmrStop_Reason = (uint8_t) ( ((_d[1] >> 4U) & (0x0FU)) ); + _m->Logic_Ac_Comp_LimitRpm_ro = (uint8_t) ( (_d[2] & (0xFFU)) ); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->Logic_Ac_Comp_LimitRpm_phys = (uint16_t) CANDB_DBG_Logic_Ac_Comp_LimitRpm_ro_fromS(_m->Logic_Ac_Comp_LimitRpm_ro); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->Logic_Ac_Txv_Closed_bySen = (uint8_t) ( (_d[3] & (0x01U)) ); + _m->Logic_Ac_Comp_Protection_Level = (uint8_t) ( ((_d[3] >> 2U) & (0x03U)) ); + _m->Logic_Ac_WinterSts_Front = (uint8_t) ( ((_d[3] >> 4U) & (0x03U)) ); + _m->Logic_Ac_WinterSts_Rear = (uint8_t) ( ((_d[3] >> 6U) & (0x03U)) ); + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < dbg_Logic_Ac_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_dbg_Logic_Ac_candb_dbg(&_m->mon1, dbg_Logic_Ac_CANID); +#endif // CANDB_DBG_USE_DIAG_MONITORS + + return dbg_Logic_Ac_CANID; +} + +#ifdef CANDB_DBG_USE_CANSTRUCT + +uint32_t Pack_dbg_Logic_Ac_candb_dbg(dbg_Logic_Ac_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Logic_Ac_DLC); cframe->Data[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->Logic_Ac_Comp_LimitRpm_ro = (uint8_t) CANDB_DBG_Logic_Ac_Comp_LimitRpm_ro_toS(_m->Logic_Ac_Comp_LimitRpm_phys); +#endif // CANDB_DBG_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->Logic_Ac_Req_Front & (0x01U)) | ((_m->Logic_Ac_Txv_Front & (0x01U)) << 1U) | ((_m->Logic_Ac_Txv_Rear & (0x01U)) << 2U) | ((_m->Logic_Ac_Req_Rear & (0x01U)) << 3U) | ((_m->Logic_Ac_Req_Chiller & (0x01U)) << 4U) | ((_m->Logic_Ac_Txv_Chiller & (0x01U)) << 5U) ); + cframe->Data[1] |= (uint8_t) ( (_m->Logic_Ac_EvaCtrl & (0x0FU)) | ((_m->Logic_Ac_Comp_EmrStop_Reason & (0x0FU)) << 4U) ); + cframe->Data[2] |= (uint8_t) ( (_m->Logic_Ac_Comp_LimitRpm_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->Logic_Ac_Txv_Closed_bySen & (0x01U)) | ((_m->Logic_Ac_Comp_Protection_Level & (0x03U)) << 2U) | ((_m->Logic_Ac_WinterSts_Front & (0x03U)) << 4U) | ((_m->Logic_Ac_WinterSts_Rear & (0x03U)) << 6U) ); + + cframe->MsgId = (uint32_t) dbg_Logic_Ac_CANID; + cframe->DLC = (uint8_t) dbg_Logic_Ac_DLC; + cframe->IDE = (uint8_t) dbg_Logic_Ac_IDE; + return dbg_Logic_Ac_CANID; +} + +#else + +uint32_t Pack_dbg_Logic_Ac_candb_dbg(dbg_Logic_Ac_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Logic_Ac_DLC); _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->Logic_Ac_Comp_LimitRpm_ro = (uint8_t) CANDB_DBG_Logic_Ac_Comp_LimitRpm_ro_toS(_m->Logic_Ac_Comp_LimitRpm_phys); +#endif // CANDB_DBG_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->Logic_Ac_Req_Front & (0x01U)) | ((_m->Logic_Ac_Txv_Front & (0x01U)) << 1U) | ((_m->Logic_Ac_Txv_Rear & (0x01U)) << 2U) | ((_m->Logic_Ac_Req_Rear & (0x01U)) << 3U) | ((_m->Logic_Ac_Req_Chiller & (0x01U)) << 4U) | ((_m->Logic_Ac_Txv_Chiller & (0x01U)) << 5U) ); + _d[1] |= (uint8_t) ( (_m->Logic_Ac_EvaCtrl & (0x0FU)) | ((_m->Logic_Ac_Comp_EmrStop_Reason & (0x0FU)) << 4U) ); + _d[2] |= (uint8_t) ( (_m->Logic_Ac_Comp_LimitRpm_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->Logic_Ac_Txv_Closed_bySen & (0x01U)) | ((_m->Logic_Ac_Comp_Protection_Level & (0x03U)) << 2U) | ((_m->Logic_Ac_WinterSts_Front & (0x03U)) << 4U) | ((_m->Logic_Ac_WinterSts_Rear & (0x03U)) << 6U) ); + + *_len = (uint8_t) dbg_Logic_Ac_DLC; + *_ide = (uint8_t) dbg_Logic_Ac_IDE; + return dbg_Logic_Ac_CANID; +} + +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Logic_Rec_candb_dbg(dbg_Logic_Rec_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Logic_Rec_Idx = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->Logic_Rec_Partial_Spd_Sts = (uint8_t) ( ((_d[0] >> 1U) & (0x01U)) ); + _m->Logic_Rec_Partial_Winter = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + _m->Logic_Rec_Partial_Summer = (uint8_t) ( ((_d[0] >> 4U) & (0x03U)) ); + _m->Logic_Rec_FreshAirPurge_Sts = (uint8_t) ( (_d[1] & (0x0FU)) ); + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < dbg_Logic_Rec_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_dbg_Logic_Rec_candb_dbg(&_m->mon1, dbg_Logic_Rec_CANID); +#endif // CANDB_DBG_USE_DIAG_MONITORS + + return dbg_Logic_Rec_CANID; +} + +#ifdef CANDB_DBG_USE_CANSTRUCT + +uint32_t Pack_dbg_Logic_Rec_candb_dbg(dbg_Logic_Rec_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Logic_Rec_DLC); cframe->Data[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->Logic_Rec_Idx & (0x01U)) | ((_m->Logic_Rec_Partial_Spd_Sts & (0x01U)) << 1U) | ((_m->Logic_Rec_Partial_Winter & (0x01U)) << 2U) | ((_m->Logic_Rec_Partial_Summer & (0x03U)) << 4U) ); + cframe->Data[1] |= (uint8_t) ( (_m->Logic_Rec_FreshAirPurge_Sts & (0x0FU)) ); + + cframe->MsgId = (uint32_t) dbg_Logic_Rec_CANID; + cframe->DLC = (uint8_t) dbg_Logic_Rec_DLC; + cframe->IDE = (uint8_t) dbg_Logic_Rec_IDE; + return dbg_Logic_Rec_CANID; +} + +#else + +uint32_t Pack_dbg_Logic_Rec_candb_dbg(dbg_Logic_Rec_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Logic_Rec_DLC); _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->Logic_Rec_Idx & (0x01U)) | ((_m->Logic_Rec_Partial_Spd_Sts & (0x01U)) << 1U) | ((_m->Logic_Rec_Partial_Winter & (0x01U)) << 2U) | ((_m->Logic_Rec_Partial_Summer & (0x03U)) << 4U) ); + _d[1] |= (uint8_t) ( (_m->Logic_Rec_FreshAirPurge_Sts & (0x0FU)) ); + + *_len = (uint8_t) dbg_Logic_Rec_DLC; + *_ide = (uint8_t) dbg_Logic_Rec_IDE; + return dbg_Logic_Rec_CANID; +} + +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_DiffBlr_ValveOpen_candb_dbg(dbg_DiffBlr_ValveOpen_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Logic_ValveOpen_MultMsg_Idx = (uint8_t) ( (_d[0] & (0x03U)) ); + _m->Logic_ValveOpen_R2_SFL = (uint8_t) ( (_d[1] & (0xFFU)) ); + _m->Logic_ValveOpen_R1_SFL = (uint8_t) ( (_d[1] & (0xFFU)) ); + _m->Logic_ValveOpen_R2_CFL = (uint8_t) ( (_d[2] & (0xFFU)) ); + _m->Logic_ValveOpen_R1_CFL = (uint8_t) ( (_d[2] & (0xFFU)) ); + _m->Logic_ValveOpen_R2_CFR = (uint8_t) ( (_d[3] & (0xFFU)) ); + _m->Logic_ValveOpen_R1_CFR = (uint8_t) ( (_d[3] & (0xFFU)) ); + _m->Logic_ValveOpen_R2_SFR = (uint8_t) ( (_d[4] & (0xFFU)) ); + _m->Logic_ValveOpen_R1_SFR = (uint8_t) ( (_d[4] & (0xFFU)) ); + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < dbg_DiffBlr_ValveOpen_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_dbg_DiffBlr_ValveOpen_candb_dbg(&_m->mon1, dbg_DiffBlr_ValveOpen_CANID); +#endif // CANDB_DBG_USE_DIAG_MONITORS + + return dbg_DiffBlr_ValveOpen_CANID; +} + +#ifdef CANDB_DBG_USE_CANSTRUCT + +uint32_t Pack_dbg_DiffBlr_ValveOpen_candb_dbg(dbg_DiffBlr_ValveOpen_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_DiffBlr_ValveOpen_DLC); cframe->Data[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->Logic_ValveOpen_MultMsg_Idx & (0x03U)) ); + cframe->Data[1] |= (uint8_t) ( (_m->Logic_ValveOpen_R2_SFL & (0xFFU)) | (_m->Logic_ValveOpen_R1_SFL & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->Logic_ValveOpen_R2_CFL & (0xFFU)) | (_m->Logic_ValveOpen_R1_CFL & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->Logic_ValveOpen_R2_CFR & (0xFFU)) | (_m->Logic_ValveOpen_R1_CFR & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->Logic_ValveOpen_R2_SFR & (0xFFU)) | (_m->Logic_ValveOpen_R1_SFR & (0xFFU)) ); + + cframe->MsgId = (uint32_t) dbg_DiffBlr_ValveOpen_CANID; + cframe->DLC = (uint8_t) dbg_DiffBlr_ValveOpen_DLC; + cframe->IDE = (uint8_t) dbg_DiffBlr_ValveOpen_IDE; + return dbg_DiffBlr_ValveOpen_CANID; +} + +#else + +uint32_t Pack_dbg_DiffBlr_ValveOpen_candb_dbg(dbg_DiffBlr_ValveOpen_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_DiffBlr_ValveOpen_DLC); _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->Logic_ValveOpen_MultMsg_Idx & (0x03U)) ); + _d[1] |= (uint8_t) ( (_m->Logic_ValveOpen_R2_SFL & (0xFFU)) | (_m->Logic_ValveOpen_R1_SFL & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->Logic_ValveOpen_R2_CFL & (0xFFU)) | (_m->Logic_ValveOpen_R1_CFL & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->Logic_ValveOpen_R2_CFR & (0xFFU)) | (_m->Logic_ValveOpen_R1_CFR & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->Logic_ValveOpen_R2_SFR & (0xFFU)) | (_m->Logic_ValveOpen_R1_SFR & (0xFFU)) ); + + *_len = (uint8_t) dbg_DiffBlr_ValveOpen_DLC; + *_ide = (uint8_t) dbg_DiffBlr_ValveOpen_IDE; + return dbg_DiffBlr_ValveOpen_CANID; +} + +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Act0_candb_dbg(dbg_Act0_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->dbg_Act00_Def = (uint8_t) ( (_d[0] & (0xFFU)) ); + _m->dbg_Act01_Vent_SFL = (uint8_t) ( (_d[1] & (0xFFU)) ); + _m->dbg_Act02_Vent_CFL = (uint8_t) ( (_d[2] & (0xFFU)) ); + _m->dbg_Act03_Foot_1FL = (uint8_t) ( (_d[3] & (0xFFU)) ); + _m->dbg_Act04_Foot_2FL = (uint8_t) ( (_d[4] & (0xFFU)) ); + _m->dbg_Act05_Vent_CFR = (uint8_t) ( (_d[5] & (0xFFU)) ); + _m->dbg_Act06_Vent_SFR = (uint8_t) ( (_d[6] & (0xFFU)) ); + _m->dbg_Act07_Foot_1FR = (uint8_t) ( (_d[7] & (0xFFU)) ); + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < dbg_Act0_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_dbg_Act0_candb_dbg(&_m->mon1, dbg_Act0_CANID); +#endif // CANDB_DBG_USE_DIAG_MONITORS + + return dbg_Act0_CANID; +} + +#ifdef CANDB_DBG_USE_CANSTRUCT + +uint32_t Pack_dbg_Act0_candb_dbg(dbg_Act0_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Act0_DLC); cframe->Data[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->dbg_Act00_Def & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->dbg_Act01_Vent_SFL & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->dbg_Act02_Vent_CFL & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->dbg_Act03_Foot_1FL & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->dbg_Act04_Foot_2FL & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->dbg_Act05_Vent_CFR & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->dbg_Act06_Vent_SFR & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->dbg_Act07_Foot_1FR & (0xFFU)) ); + + cframe->MsgId = (uint32_t) dbg_Act0_CANID; + cframe->DLC = (uint8_t) dbg_Act0_DLC; + cframe->IDE = (uint8_t) dbg_Act0_IDE; + return dbg_Act0_CANID; +} + +#else + +uint32_t Pack_dbg_Act0_candb_dbg(dbg_Act0_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Act0_DLC); _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->dbg_Act00_Def & (0xFFU)) ); + _d[1] |= (uint8_t) ( (_m->dbg_Act01_Vent_SFL & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->dbg_Act02_Vent_CFL & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->dbg_Act03_Foot_1FL & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->dbg_Act04_Foot_2FL & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->dbg_Act05_Vent_CFR & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->dbg_Act06_Vent_SFR & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->dbg_Act07_Foot_1FR & (0xFFU)) ); + + *_len = (uint8_t) dbg_Act0_DLC; + *_ide = (uint8_t) dbg_Act0_IDE; + return dbg_Act0_CANID; +} + +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Act1_candb_dbg(dbg_Act1_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->dbg_Act08_Foot_2FR = (uint8_t) ( (_d[0] & (0xFFU)) ); + _m->dbg_Act09_Vent_SRL = (uint8_t) ( (_d[1] & (0xFFU)) ); + _m->dbg_Act10_Vent_CRL = (uint8_t) ( (_d[2] & (0xFFU)) ); + _m->dbg_Act11_Foot_RL = (uint8_t) ( (_d[3] & (0xFFU)) ); + _m->dbg_Act12_Vent_CRR = (uint8_t) ( (_d[4] & (0xFFU)) ); + _m->dbg_Act13_Vent_SRR = (uint8_t) ( (_d[5] & (0xFFU)) ); + _m->dbg_Act14_Foot_RR = (uint8_t) ( (_d[6] & (0xFFU)) ); + _m->dbg_Act15_TempU_FL = (uint8_t) ( (_d[7] & (0xFFU)) ); + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < dbg_Act1_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_dbg_Act1_candb_dbg(&_m->mon1, dbg_Act1_CANID); +#endif // CANDB_DBG_USE_DIAG_MONITORS + + return dbg_Act1_CANID; +} + +#ifdef CANDB_DBG_USE_CANSTRUCT + +uint32_t Pack_dbg_Act1_candb_dbg(dbg_Act1_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Act1_DLC); cframe->Data[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->dbg_Act08_Foot_2FR & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->dbg_Act09_Vent_SRL & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->dbg_Act10_Vent_CRL & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->dbg_Act11_Foot_RL & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->dbg_Act12_Vent_CRR & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->dbg_Act13_Vent_SRR & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->dbg_Act14_Foot_RR & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->dbg_Act15_TempU_FL & (0xFFU)) ); + + cframe->MsgId = (uint32_t) dbg_Act1_CANID; + cframe->DLC = (uint8_t) dbg_Act1_DLC; + cframe->IDE = (uint8_t) dbg_Act1_IDE; + return dbg_Act1_CANID; +} + +#else + +uint32_t Pack_dbg_Act1_candb_dbg(dbg_Act1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Act1_DLC); _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->dbg_Act08_Foot_2FR & (0xFFU)) ); + _d[1] |= (uint8_t) ( (_m->dbg_Act09_Vent_SRL & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->dbg_Act10_Vent_CRL & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->dbg_Act11_Foot_RL & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->dbg_Act12_Vent_CRR & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->dbg_Act13_Vent_SRR & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->dbg_Act14_Foot_RR & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->dbg_Act15_TempU_FL & (0xFFU)) ); + + *_len = (uint8_t) dbg_Act1_DLC; + *_ide = (uint8_t) dbg_Act1_IDE; + return dbg_Act1_CANID; +} + +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Act2_candb_dbg(dbg_Act2_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->dbg_Act16_TempL_FL = (uint8_t) ( (_d[0] & (0xFFU)) ); + _m->dbg_Act17_TempU_FR = (uint8_t) ( (_d[1] & (0xFFU)) ); + _m->dbg_Act18_TempL_FR = (uint8_t) ( (_d[2] & (0xFFU)) ); + _m->dbg_Act19_Temp_RL = (uint8_t) ( (_d[3] & (0xFFU)) ); + _m->dbg_Act20_Temp_RR = (uint8_t) ( (_d[4] & (0xFFU)) ); + _m->dbg_Act21_Rec = (uint8_t) ( (_d[5] & (0xFFU)) ); + _m->dbg_Act22_OSA = (uint8_t) ( (_d[6] & (0xFFU)) ); + _m->dbg_Act23_SealingValve = (uint8_t) ( (_d[7] & (0xFFU)) ); + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < dbg_Act2_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_dbg_Act2_candb_dbg(&_m->mon1, dbg_Act2_CANID); +#endif // CANDB_DBG_USE_DIAG_MONITORS + + return dbg_Act2_CANID; +} + +#ifdef CANDB_DBG_USE_CANSTRUCT + +uint32_t Pack_dbg_Act2_candb_dbg(dbg_Act2_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Act2_DLC); cframe->Data[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->dbg_Act16_TempL_FL & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->dbg_Act17_TempU_FR & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->dbg_Act18_TempL_FR & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->dbg_Act19_Temp_RL & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->dbg_Act20_Temp_RR & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->dbg_Act21_Rec & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->dbg_Act22_OSA & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->dbg_Act23_SealingValve & (0xFFU)) ); + + cframe->MsgId = (uint32_t) dbg_Act2_CANID; + cframe->DLC = (uint8_t) dbg_Act2_DLC; + cframe->IDE = (uint8_t) dbg_Act2_IDE; + return dbg_Act2_CANID; +} + +#else + +uint32_t Pack_dbg_Act2_candb_dbg(dbg_Act2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Act2_DLC); _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->dbg_Act16_TempL_FL & (0xFFU)) ); + _d[1] |= (uint8_t) ( (_m->dbg_Act17_TempU_FR & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->dbg_Act18_TempL_FR & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->dbg_Act19_Temp_RL & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->dbg_Act20_Temp_RR & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->dbg_Act21_Rec & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->dbg_Act22_OSA & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->dbg_Act23_SealingValve & (0xFFU)) ); + + *_len = (uint8_t) dbg_Act2_DLC; + *_ide = (uint8_t) dbg_Act2_IDE; + return dbg_Act2_CANID; +} + +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Sen_Amb_candb_dbg(dbg_Sen_Amb_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->dbg_Sen_Amb_ro = (int16_t) __ext_sig__(( ((_d[1] & (0xFFU)) << 8U) | (_d[0] & (0xFFU)) ), 16); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Amb_phys = (sigfloat_t)(CANDB_DBG_dbg_Sen_Amb_ro_fromS(_m->dbg_Sen_Amb_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Sen_Amb_Raw_ro = (int16_t) __ext_sig__(( ((_d[3] & (0xFFU)) << 8U) | (_d[2] & (0xFFU)) ), 16); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Amb_Raw_phys = (sigfloat_t)(CANDB_DBG_dbg_Sen_Amb_Raw_ro_fromS(_m->dbg_Sen_Amb_Raw_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Amb_Tg_ro = (int16_t) __ext_sig__(( ((_d[5] & (0x0FU)) << 8U) | (_d[4] & (0xFFU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Amb_Tg_phys = (sigfloat_t)(CANDB_DBG_dbg_Amb_Tg_ro_fromS(_m->dbg_Amb_Tg_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < dbg_Sen_Amb_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_dbg_Sen_Amb_candb_dbg(&_m->mon1, dbg_Sen_Amb_CANID); +#endif // CANDB_DBG_USE_DIAG_MONITORS + + return dbg_Sen_Amb_CANID; +} + +#ifdef CANDB_DBG_USE_CANSTRUCT + +uint32_t Pack_dbg_Sen_Amb_candb_dbg(dbg_Sen_Amb_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Sen_Amb_DLC); cframe->Data[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Amb_ro = (int16_t) CANDB_DBG_dbg_Sen_Amb_ro_toS(_m->dbg_Sen_Amb_phys); + _m->dbg_Sen_Amb_Raw_ro = (int16_t) CANDB_DBG_dbg_Sen_Amb_Raw_ro_toS(_m->dbg_Sen_Amb_Raw_phys); + _m->dbg_Amb_Tg_ro = (int16_t) CANDB_DBG_dbg_Amb_Tg_ro_toS(_m->dbg_Amb_Tg_phys); +#endif // CANDB_DBG_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->dbg_Sen_Amb_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->dbg_Sen_Amb_ro >> 8U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->dbg_Sen_Amb_Raw_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->dbg_Sen_Amb_Raw_ro >> 8U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->dbg_Amb_Tg_ro & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->dbg_Amb_Tg_ro >> 8U) & (0x0FU)) ); + + cframe->MsgId = (uint32_t) dbg_Sen_Amb_CANID; + cframe->DLC = (uint8_t) dbg_Sen_Amb_DLC; + cframe->IDE = (uint8_t) dbg_Sen_Amb_IDE; + return dbg_Sen_Amb_CANID; +} + +#else + +uint32_t Pack_dbg_Sen_Amb_candb_dbg(dbg_Sen_Amb_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Sen_Amb_DLC); _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Amb_ro = (int16_t) CANDB_DBG_dbg_Sen_Amb_ro_toS(_m->dbg_Sen_Amb_phys); + _m->dbg_Sen_Amb_Raw_ro = (int16_t) CANDB_DBG_dbg_Sen_Amb_Raw_ro_toS(_m->dbg_Sen_Amb_Raw_phys); + _m->dbg_Amb_Tg_ro = (int16_t) CANDB_DBG_dbg_Amb_Tg_ro_toS(_m->dbg_Amb_Tg_phys); +#endif // CANDB_DBG_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->dbg_Sen_Amb_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->dbg_Sen_Amb_ro >> 8U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->dbg_Sen_Amb_Raw_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->dbg_Sen_Amb_Raw_ro >> 8U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->dbg_Amb_Tg_ro & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->dbg_Amb_Tg_ro >> 8U) & (0x0FU)) ); + + *_len = (uint8_t) dbg_Sen_Amb_DLC; + *_ide = (uint8_t) dbg_Sen_Amb_IDE; + return dbg_Sen_Amb_CANID; +} + +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Sen_0_candb_dbg(dbg_Sen_0_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->dbg_Sen_BattVolt_ro = (uint8_t) ( (_d[0] & (0xFFU)) ); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_BattVolt_phys = (sigfloat_t)(CANDB_DBG_dbg_Sen_BattVolt_ro_fromS(_m->dbg_Sen_BattVolt_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Sen_Pressure_ro = (uint16_t) ( ((_d[3] & (0x0FU)) << 8U) | (_d[2] & (0xFFU)) ); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Pressure_phys = (sigfloat_t)(CANDB_DBG_dbg_Sen_Pressure_ro_fromS(_m->dbg_Sen_Pressure_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Sen_Sun_L = (uint16_t) ( ((_d[5] & (0xFFU)) << 8U) | (_d[4] & (0xFFU)) ); + _m->dbg_Sen_Sun_R = (uint16_t) ( ((_d[7] & (0xFFU)) << 8U) | (_d[6] & (0xFFU)) ); + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < dbg_Sen_0_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_dbg_Sen_0_candb_dbg(&_m->mon1, dbg_Sen_0_CANID); +#endif // CANDB_DBG_USE_DIAG_MONITORS + + return dbg_Sen_0_CANID; +} + +#ifdef CANDB_DBG_USE_CANSTRUCT + +uint32_t Pack_dbg_Sen_0_candb_dbg(dbg_Sen_0_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Sen_0_DLC); cframe->Data[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_BattVolt_ro = (uint8_t) CANDB_DBG_dbg_Sen_BattVolt_ro_toS(_m->dbg_Sen_BattVolt_phys); + _m->dbg_Sen_Pressure_ro = (uint16_t) CANDB_DBG_dbg_Sen_Pressure_ro_toS(_m->dbg_Sen_Pressure_phys); +#endif // CANDB_DBG_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->dbg_Sen_BattVolt_ro & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->dbg_Sen_Pressure_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->dbg_Sen_Pressure_ro >> 8U) & (0x0FU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->dbg_Sen_Sun_L & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->dbg_Sen_Sun_L >> 8U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->dbg_Sen_Sun_R & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( ((_m->dbg_Sen_Sun_R >> 8U) & (0xFFU)) ); + + cframe->MsgId = (uint32_t) dbg_Sen_0_CANID; + cframe->DLC = (uint8_t) dbg_Sen_0_DLC; + cframe->IDE = (uint8_t) dbg_Sen_0_IDE; + return dbg_Sen_0_CANID; +} + +#else + +uint32_t Pack_dbg_Sen_0_candb_dbg(dbg_Sen_0_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Sen_0_DLC); _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_BattVolt_ro = (uint8_t) CANDB_DBG_dbg_Sen_BattVolt_ro_toS(_m->dbg_Sen_BattVolt_phys); + _m->dbg_Sen_Pressure_ro = (uint16_t) CANDB_DBG_dbg_Sen_Pressure_ro_toS(_m->dbg_Sen_Pressure_phys); +#endif // CANDB_DBG_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->dbg_Sen_BattVolt_ro & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->dbg_Sen_Pressure_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->dbg_Sen_Pressure_ro >> 8U) & (0x0FU)) ); + _d[4] |= (uint8_t) ( (_m->dbg_Sen_Sun_L & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->dbg_Sen_Sun_L >> 8U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->dbg_Sen_Sun_R & (0xFFU)) ); + _d[7] |= (uint8_t) ( ((_m->dbg_Sen_Sun_R >> 8U) & (0xFFU)) ); + + *_len = (uint8_t) dbg_Sen_0_DLC; + *_ide = (uint8_t) dbg_Sen_0_IDE; + return dbg_Sen_0_CANID; +} + +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_CCU_IO_candb_dbg(dbg_CCU_IO_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->dbg_IO_Txv_F = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->dbg_IO_Txv_R = (uint8_t) ( ((_d[0] >> 1U) & (0x01U)) ); + _m->dbg_IO_Txv_Ch = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + _m->dbg_IO_2WayValve = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + _m->dbg_IO_IncarMotor_F = (uint8_t) ( ((_d[0] >> 4U) & (0x01U)) ); + _m->dbg_IO_IncarMotor_R = (uint8_t) ( ((_d[0] >> 5U) & (0x01U)) ); + _m->dbg_SetTemp_FL_ro = (uint8_t) ( (_d[1] & (0xFFU)) ); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_SetTemp_FL_phys = (sigfloat_t)(CANDB_DBG_dbg_SetTemp_FL_ro_fromS(_m->dbg_SetTemp_FL_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_SetTemp_FR_ro = (uint8_t) ( (_d[2] & (0xFFU)) ); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_SetTemp_FR_phys = (sigfloat_t)(CANDB_DBG_dbg_SetTemp_FR_ro_fromS(_m->dbg_SetTemp_FR_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_SetTemp_RL_ro = (uint8_t) ( (_d[3] & (0xFFU)) ); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_SetTemp_RL_phys = (sigfloat_t)(CANDB_DBG_dbg_SetTemp_RL_ro_fromS(_m->dbg_SetTemp_RL_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_SetTemp_RR_ro = (uint8_t) ( (_d[4] & (0xFFU)) ); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_SetTemp_RR_phys = (sigfloat_t)(CANDB_DBG_dbg_SetTemp_RR_ro_fromS(_m->dbg_SetTemp_RR_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_IO_Input_Emergency = (uint8_t) ( (_d[5] & (0x01U)) ); + _m->dbg_IO_Input_FireExtinguisher = (uint8_t) ( ((_d[5] >> 1U) & (0x01U)) ); + _m->dbg_IO_Install_Sealing_Valve = (uint8_t) ( ((_d[5] >> 2U) & (0x01U)) ); + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < dbg_CCU_IO_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_dbg_CCU_IO_candb_dbg(&_m->mon1, dbg_CCU_IO_CANID); +#endif // CANDB_DBG_USE_DIAG_MONITORS + + return dbg_CCU_IO_CANID; +} + +#ifdef CANDB_DBG_USE_CANSTRUCT + +uint32_t Pack_dbg_CCU_IO_candb_dbg(dbg_CCU_IO_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_CCU_IO_DLC); cframe->Data[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_SetTemp_FL_ro = (uint8_t) CANDB_DBG_dbg_SetTemp_FL_ro_toS(_m->dbg_SetTemp_FL_phys); + _m->dbg_SetTemp_FR_ro = (uint8_t) CANDB_DBG_dbg_SetTemp_FR_ro_toS(_m->dbg_SetTemp_FR_phys); + _m->dbg_SetTemp_RL_ro = (uint8_t) CANDB_DBG_dbg_SetTemp_RL_ro_toS(_m->dbg_SetTemp_RL_phys); + _m->dbg_SetTemp_RR_ro = (uint8_t) CANDB_DBG_dbg_SetTemp_RR_ro_toS(_m->dbg_SetTemp_RR_phys); +#endif // CANDB_DBG_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->dbg_IO_Txv_F & (0x01U)) | ((_m->dbg_IO_Txv_R & (0x01U)) << 1U) | ((_m->dbg_IO_Txv_Ch & (0x01U)) << 2U) | ((_m->dbg_IO_2WayValve & (0x01U)) << 3U) | ((_m->dbg_IO_IncarMotor_F & (0x01U)) << 4U) | ((_m->dbg_IO_IncarMotor_R & (0x01U)) << 5U) ); + cframe->Data[1] |= (uint8_t) ( (_m->dbg_SetTemp_FL_ro & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->dbg_SetTemp_FR_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->dbg_SetTemp_RL_ro & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->dbg_SetTemp_RR_ro & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->dbg_IO_Input_Emergency & (0x01U)) | ((_m->dbg_IO_Input_FireExtinguisher & (0x01U)) << 1U) | ((_m->dbg_IO_Install_Sealing_Valve & (0x01U)) << 2U) ); + + cframe->MsgId = (uint32_t) dbg_CCU_IO_CANID; + cframe->DLC = (uint8_t) dbg_CCU_IO_DLC; + cframe->IDE = (uint8_t) dbg_CCU_IO_IDE; + return dbg_CCU_IO_CANID; +} + +#else + +uint32_t Pack_dbg_CCU_IO_candb_dbg(dbg_CCU_IO_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_CCU_IO_DLC); _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_SetTemp_FL_ro = (uint8_t) CANDB_DBG_dbg_SetTemp_FL_ro_toS(_m->dbg_SetTemp_FL_phys); + _m->dbg_SetTemp_FR_ro = (uint8_t) CANDB_DBG_dbg_SetTemp_FR_ro_toS(_m->dbg_SetTemp_FR_phys); + _m->dbg_SetTemp_RL_ro = (uint8_t) CANDB_DBG_dbg_SetTemp_RL_ro_toS(_m->dbg_SetTemp_RL_phys); + _m->dbg_SetTemp_RR_ro = (uint8_t) CANDB_DBG_dbg_SetTemp_RR_ro_toS(_m->dbg_SetTemp_RR_phys); +#endif // CANDB_DBG_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->dbg_IO_Txv_F & (0x01U)) | ((_m->dbg_IO_Txv_R & (0x01U)) << 1U) | ((_m->dbg_IO_Txv_Ch & (0x01U)) << 2U) | ((_m->dbg_IO_2WayValve & (0x01U)) << 3U) | ((_m->dbg_IO_IncarMotor_F & (0x01U)) << 4U) | ((_m->dbg_IO_IncarMotor_R & (0x01U)) << 5U) ); + _d[1] |= (uint8_t) ( (_m->dbg_SetTemp_FL_ro & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->dbg_SetTemp_FR_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->dbg_SetTemp_RL_ro & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->dbg_SetTemp_RR_ro & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->dbg_IO_Input_Emergency & (0x01U)) | ((_m->dbg_IO_Input_FireExtinguisher & (0x01U)) << 1U) | ((_m->dbg_IO_Install_Sealing_Valve & (0x01U)) << 2U) ); + + *_len = (uint8_t) dbg_CCU_IO_DLC; + *_ide = (uint8_t) dbg_CCU_IO_IDE; + return dbg_CCU_IO_CANID; +} + +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_CCU_Info_candb_dbg(dbg_CCU_Info_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->dbg_Info_MultMsg_Idx = (uint8_t) ( (_d[0] & (0x03U)) ); + _m->dbg_Info_Calibration_Ver_Date = (uint32_t) ( ((_d[2] & (0xFFU)) << 14U) | ((_d[1] & (0xFFU)) << 6U) | ((_d[0] >> 2U) & (0x3FU)) ); + _m->dbg_Info_CCU_SW_Ver_Date = (uint32_t) ( ((_d[2] & (0xFFU)) << 14U) | ((_d[1] & (0xFFU)) << 6U) | ((_d[0] >> 2U) & (0x3FU)) ); + _m->dbg_Info_Calibration_Ver_Rev = (uint8_t) ( (_d[3] & (0xFFU)) ); + _m->dbg_Info_CCU_SW_Ver_Rev = (uint8_t) ( (_d[3] & (0xFFU)) ); + _m->dbg_Info_ActivatedCAL = (uint8_t) ( (_d[4] & (0x0FU)) ); + _m->dbg_Info_MBD_Ver_Date = (uint32_t) ( ((_d[6] & (0xFFU)) << 14U) | ((_d[5] & (0xFFU)) << 6U) | ((_d[4] >> 2U) & (0x3FU)) ); + _m->dbg_Info_CCU_Aroma_Cfg = (uint8_t) ( ((_d[4] >> 4U) & (0x0FU)) ); + _m->dbg_Info_CCU_Algorithm_Cfg = (uint8_t) ( (_d[5] & (0x0FU)) ); + _m->dbg_Info_VehicleBody = (uint16_t) ( ((_d[7] & (0xFFU)) << 8U) | (_d[6] & (0xFFU)) ); + _m->dbg_Info_MBD_Ver_Rev = (uint8_t) ( (_d[7] & (0xFFU)) ); + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < dbg_CCU_Info_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_dbg_CCU_Info_candb_dbg(&_m->mon1, dbg_CCU_Info_CANID); +#endif // CANDB_DBG_USE_DIAG_MONITORS + + return dbg_CCU_Info_CANID; +} + +#ifdef CANDB_DBG_USE_CANSTRUCT + +uint32_t Pack_dbg_CCU_Info_candb_dbg(dbg_CCU_Info_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_CCU_Info_DLC); cframe->Data[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->dbg_Info_MultMsg_Idx & (0x03U)) | ((_m->dbg_Info_Calibration_Ver_Date & (0x3FU)) << 2U) | ((_m->dbg_Info_CCU_SW_Ver_Date & (0x3FU)) << 2U) ); + cframe->Data[1] |= (uint8_t) ( ((_m->dbg_Info_Calibration_Ver_Date >> 6U) & (0xFFU)) | ((_m->dbg_Info_CCU_SW_Ver_Date >> 6U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->dbg_Info_Calibration_Ver_Date >> 14U) & (0xFFU)) | ((_m->dbg_Info_CCU_SW_Ver_Date >> 14U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->dbg_Info_Calibration_Ver_Rev & (0xFFU)) | (_m->dbg_Info_CCU_SW_Ver_Rev & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->dbg_Info_ActivatedCAL & (0x0FU)) | ((_m->dbg_Info_MBD_Ver_Date & (0x3FU)) << 2U) | ((_m->dbg_Info_CCU_Aroma_Cfg & (0x0FU)) << 4U) ); + cframe->Data[5] |= (uint8_t) ( ((_m->dbg_Info_MBD_Ver_Date >> 6U) & (0xFFU)) | (_m->dbg_Info_CCU_Algorithm_Cfg & (0x0FU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->dbg_Info_MBD_Ver_Date >> 14U) & (0xFFU)) | (_m->dbg_Info_VehicleBody & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( ((_m->dbg_Info_VehicleBody >> 8U) & (0xFFU)) | (_m->dbg_Info_MBD_Ver_Rev & (0xFFU)) ); + + cframe->MsgId = (uint32_t) dbg_CCU_Info_CANID; + cframe->DLC = (uint8_t) dbg_CCU_Info_DLC; + cframe->IDE = (uint8_t) dbg_CCU_Info_IDE; + return dbg_CCU_Info_CANID; +} + +#else + +uint32_t Pack_dbg_CCU_Info_candb_dbg(dbg_CCU_Info_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_CCU_Info_DLC); _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->dbg_Info_MultMsg_Idx & (0x03U)) | ((_m->dbg_Info_Calibration_Ver_Date & (0x3FU)) << 2U) | ((_m->dbg_Info_CCU_SW_Ver_Date & (0x3FU)) << 2U) ); + _d[1] |= (uint8_t) ( ((_m->dbg_Info_Calibration_Ver_Date >> 6U) & (0xFFU)) | ((_m->dbg_Info_CCU_SW_Ver_Date >> 6U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->dbg_Info_Calibration_Ver_Date >> 14U) & (0xFFU)) | ((_m->dbg_Info_CCU_SW_Ver_Date >> 14U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->dbg_Info_Calibration_Ver_Rev & (0xFFU)) | (_m->dbg_Info_CCU_SW_Ver_Rev & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->dbg_Info_ActivatedCAL & (0x0FU)) | ((_m->dbg_Info_MBD_Ver_Date & (0x3FU)) << 2U) | ((_m->dbg_Info_CCU_Aroma_Cfg & (0x0FU)) << 4U) ); + _d[5] |= (uint8_t) ( ((_m->dbg_Info_MBD_Ver_Date >> 6U) & (0xFFU)) | (_m->dbg_Info_CCU_Algorithm_Cfg & (0x0FU)) ); + _d[6] |= (uint8_t) ( ((_m->dbg_Info_MBD_Ver_Date >> 14U) & (0xFFU)) | (_m->dbg_Info_VehicleBody & (0xFFU)) ); + _d[7] |= (uint8_t) ( ((_m->dbg_Info_VehicleBody >> 8U) & (0xFFU)) | (_m->dbg_Info_MBD_Ver_Rev & (0xFFU)) ); + + *_len = (uint8_t) dbg_CCU_Info_DLC; + *_ide = (uint8_t) dbg_CCU_Info_IDE; + return dbg_CCU_Info_CANID; +} + +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Drs_candb_dbg(dbg_Drs_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->dbg_Drs_0_SFL_DL = (uint8_t) ( (_d[0] & (0x7FU)) ); + _m->dbg_Drs_1_CFL_FPL = (uint8_t) ( (_d[1] & (0x7FU)) ); + _m->dbg_Drs_2_CFR_FPR = (uint8_t) ( (_d[2] & (0x7FU)) ); + _m->dbg_Drs_3_SFR_DR = (uint8_t) ( (_d[3] & (0x7FU)) ); + _m->dbg_Drs_4_SRL_RLB = (uint8_t) ( (_d[4] & (0x7FU)) ); + _m->dbg_Drs_5_CRL_FCL = (uint8_t) ( (_d[5] & (0x7FU)) ); + _m->dbg_Drs_6_CRR_FCR = (uint8_t) ( (_d[6] & (0x7FU)) ); + _m->dbg_Drs_7_SRR_RRB = (uint8_t) ( (_d[7] & (0x7FU)) ); + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < dbg_Drs_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_dbg_Drs_candb_dbg(&_m->mon1, dbg_Drs_CANID); +#endif // CANDB_DBG_USE_DIAG_MONITORS + + return dbg_Drs_CANID; +} + +#ifdef CANDB_DBG_USE_CANSTRUCT + +uint32_t Pack_dbg_Drs_candb_dbg(dbg_Drs_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Drs_DLC); cframe->Data[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->dbg_Drs_0_SFL_DL & (0x7FU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->dbg_Drs_1_CFL_FPL & (0x7FU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->dbg_Drs_2_CFR_FPR & (0x7FU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->dbg_Drs_3_SFR_DR & (0x7FU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->dbg_Drs_4_SRL_RLB & (0x7FU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->dbg_Drs_5_CRL_FCL & (0x7FU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->dbg_Drs_6_CRR_FCR & (0x7FU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->dbg_Drs_7_SRR_RRB & (0x7FU)) ); + + cframe->MsgId = (uint32_t) dbg_Drs_CANID; + cframe->DLC = (uint8_t) dbg_Drs_DLC; + cframe->IDE = (uint8_t) dbg_Drs_IDE; + return dbg_Drs_CANID; +} + +#else + +uint32_t Pack_dbg_Drs_candb_dbg(dbg_Drs_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Drs_DLC); _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->dbg_Drs_0_SFL_DL & (0x7FU)) ); + _d[1] |= (uint8_t) ( (_m->dbg_Drs_1_CFL_FPL & (0x7FU)) ); + _d[2] |= (uint8_t) ( (_m->dbg_Drs_2_CFR_FPR & (0x7FU)) ); + _d[3] |= (uint8_t) ( (_m->dbg_Drs_3_SFR_DR & (0x7FU)) ); + _d[4] |= (uint8_t) ( (_m->dbg_Drs_4_SRL_RLB & (0x7FU)) ); + _d[5] |= (uint8_t) ( (_m->dbg_Drs_5_CRL_FCL & (0x7FU)) ); + _d[6] |= (uint8_t) ( (_m->dbg_Drs_6_CRR_FCR & (0x7FU)) ); + _d[7] |= (uint8_t) ( (_m->dbg_Drs_7_SRR_RRB & (0x7FU)) ); + + *_len = (uint8_t) dbg_Drs_DLC; + *_ide = (uint8_t) dbg_Drs_IDE; + return dbg_Drs_CANID; +} + +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Sen_Incar_candb_dbg(dbg_Sen_Incar_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->dbg_Sen_Incar_MultMsg_Idx = (uint8_t) ( (_d[0] & (0x03U)) ); + _m->dbg_Sen_Incar_Raw_FL_ro = (int16_t) __ext_sig__(( ((_d[1] & (0xFFU)) << 4U) | ((_d[0] >> 4U) & (0x0FU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Incar_Raw_FL_phys = (sigfloat_t)(CANDB_DBG_dbg_Sen_Incar_Raw_FL_ro_fromS(_m->dbg_Sen_Incar_Raw_FL_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Sen_Incar_FL_ro = (int16_t) __ext_sig__(( ((_d[1] & (0xFFU)) << 4U) | ((_d[0] >> 4U) & (0x0FU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Incar_FL_phys = (sigfloat_t)(CANDB_DBG_dbg_Sen_Incar_FL_ro_fromS(_m->dbg_Sen_Incar_FL_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Sen_Incar_Raw_FR_ro = (int16_t) __ext_sig__(( ((_d[3] & (0x0FU)) << 8U) | (_d[2] & (0xFFU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Incar_Raw_FR_phys = (sigfloat_t)(CANDB_DBG_dbg_Sen_Incar_Raw_FR_ro_fromS(_m->dbg_Sen_Incar_Raw_FR_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Sen_Incar_FR_ro = (int16_t) __ext_sig__(( ((_d[3] & (0x0FU)) << 8U) | (_d[2] & (0xFFU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Incar_FR_phys = (sigfloat_t)(CANDB_DBG_dbg_Sen_Incar_FR_ro_fromS(_m->dbg_Sen_Incar_FR_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Sen_Incar_Raw_RL_ro = (int16_t) __ext_sig__(( ((_d[4] & (0xFFU)) << 4U) | ((_d[3] >> 4U) & (0x0FU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Incar_Raw_RL_phys = (sigfloat_t)(CANDB_DBG_dbg_Sen_Incar_Raw_RL_ro_fromS(_m->dbg_Sen_Incar_Raw_RL_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Sen_Incar_RL_ro = (int16_t) __ext_sig__(( ((_d[4] & (0xFFU)) << 4U) | ((_d[3] >> 4U) & (0x0FU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Incar_RL_phys = (sigfloat_t)(CANDB_DBG_dbg_Sen_Incar_RL_ro_fromS(_m->dbg_Sen_Incar_RL_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Sen_Incar_Raw_RR_ro = (int16_t) __ext_sig__(( ((_d[6] & (0x0FU)) << 8U) | (_d[5] & (0xFFU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Incar_Raw_RR_phys = (sigfloat_t)(CANDB_DBG_dbg_Sen_Incar_Raw_RR_ro_fromS(_m->dbg_Sen_Incar_Raw_RR_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Sen_Incar_RR_ro = (int16_t) __ext_sig__(( ((_d[6] & (0x0FU)) << 8U) | (_d[5] & (0xFFU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Incar_RR_phys = (sigfloat_t)(CANDB_DBG_dbg_Sen_Incar_RR_ro_fromS(_m->dbg_Sen_Incar_RR_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < dbg_Sen_Incar_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_dbg_Sen_Incar_candb_dbg(&_m->mon1, dbg_Sen_Incar_CANID); +#endif // CANDB_DBG_USE_DIAG_MONITORS + + return dbg_Sen_Incar_CANID; +} + +#ifdef CANDB_DBG_USE_CANSTRUCT + +uint32_t Pack_dbg_Sen_Incar_candb_dbg(dbg_Sen_Incar_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Sen_Incar_DLC); cframe->Data[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Incar_Raw_FL_ro = (int16_t) CANDB_DBG_dbg_Sen_Incar_Raw_FL_ro_toS(_m->dbg_Sen_Incar_Raw_FL_phys); + _m->dbg_Sen_Incar_FL_ro = (int16_t) CANDB_DBG_dbg_Sen_Incar_FL_ro_toS(_m->dbg_Sen_Incar_FL_phys); + _m->dbg_Sen_Incar_Raw_FR_ro = (int16_t) CANDB_DBG_dbg_Sen_Incar_Raw_FR_ro_toS(_m->dbg_Sen_Incar_Raw_FR_phys); + _m->dbg_Sen_Incar_FR_ro = (int16_t) CANDB_DBG_dbg_Sen_Incar_FR_ro_toS(_m->dbg_Sen_Incar_FR_phys); + _m->dbg_Sen_Incar_Raw_RL_ro = (int16_t) CANDB_DBG_dbg_Sen_Incar_Raw_RL_ro_toS(_m->dbg_Sen_Incar_Raw_RL_phys); + _m->dbg_Sen_Incar_RL_ro = (int16_t) CANDB_DBG_dbg_Sen_Incar_RL_ro_toS(_m->dbg_Sen_Incar_RL_phys); + _m->dbg_Sen_Incar_Raw_RR_ro = (int16_t) CANDB_DBG_dbg_Sen_Incar_Raw_RR_ro_toS(_m->dbg_Sen_Incar_Raw_RR_phys); + _m->dbg_Sen_Incar_RR_ro = (int16_t) CANDB_DBG_dbg_Sen_Incar_RR_ro_toS(_m->dbg_Sen_Incar_RR_phys); +#endif // CANDB_DBG_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->dbg_Sen_Incar_MultMsg_Idx & (0x03U)) | ((_m->dbg_Sen_Incar_Raw_FL_ro & (0x0FU)) << 4U) | ((_m->dbg_Sen_Incar_FL_ro & (0x0FU)) << 4U) ); + cframe->Data[1] |= (uint8_t) ( ((_m->dbg_Sen_Incar_Raw_FL_ro >> 4U) & (0xFFU)) | ((_m->dbg_Sen_Incar_FL_ro >> 4U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->dbg_Sen_Incar_Raw_FR_ro & (0xFFU)) | (_m->dbg_Sen_Incar_FR_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->dbg_Sen_Incar_Raw_FR_ro >> 8U) & (0x0FU)) | ((_m->dbg_Sen_Incar_FR_ro >> 8U) & (0x0FU)) | ((_m->dbg_Sen_Incar_Raw_RL_ro & (0x0FU)) << 4U) | ((_m->dbg_Sen_Incar_RL_ro & (0x0FU)) << 4U) ); + cframe->Data[4] |= (uint8_t) ( ((_m->dbg_Sen_Incar_Raw_RL_ro >> 4U) & (0xFFU)) | ((_m->dbg_Sen_Incar_RL_ro >> 4U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->dbg_Sen_Incar_Raw_RR_ro & (0xFFU)) | (_m->dbg_Sen_Incar_RR_ro & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->dbg_Sen_Incar_Raw_RR_ro >> 8U) & (0x0FU)) | ((_m->dbg_Sen_Incar_RR_ro >> 8U) & (0x0FU)) ); + + cframe->MsgId = (uint32_t) dbg_Sen_Incar_CANID; + cframe->DLC = (uint8_t) dbg_Sen_Incar_DLC; + cframe->IDE = (uint8_t) dbg_Sen_Incar_IDE; + return dbg_Sen_Incar_CANID; +} + +#else + +uint32_t Pack_dbg_Sen_Incar_candb_dbg(dbg_Sen_Incar_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Sen_Incar_DLC); _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Incar_Raw_FL_ro = (int16_t) CANDB_DBG_dbg_Sen_Incar_Raw_FL_ro_toS(_m->dbg_Sen_Incar_Raw_FL_phys); + _m->dbg_Sen_Incar_FL_ro = (int16_t) CANDB_DBG_dbg_Sen_Incar_FL_ro_toS(_m->dbg_Sen_Incar_FL_phys); + _m->dbg_Sen_Incar_Raw_FR_ro = (int16_t) CANDB_DBG_dbg_Sen_Incar_Raw_FR_ro_toS(_m->dbg_Sen_Incar_Raw_FR_phys); + _m->dbg_Sen_Incar_FR_ro = (int16_t) CANDB_DBG_dbg_Sen_Incar_FR_ro_toS(_m->dbg_Sen_Incar_FR_phys); + _m->dbg_Sen_Incar_Raw_RL_ro = (int16_t) CANDB_DBG_dbg_Sen_Incar_Raw_RL_ro_toS(_m->dbg_Sen_Incar_Raw_RL_phys); + _m->dbg_Sen_Incar_RL_ro = (int16_t) CANDB_DBG_dbg_Sen_Incar_RL_ro_toS(_m->dbg_Sen_Incar_RL_phys); + _m->dbg_Sen_Incar_Raw_RR_ro = (int16_t) CANDB_DBG_dbg_Sen_Incar_Raw_RR_ro_toS(_m->dbg_Sen_Incar_Raw_RR_phys); + _m->dbg_Sen_Incar_RR_ro = (int16_t) CANDB_DBG_dbg_Sen_Incar_RR_ro_toS(_m->dbg_Sen_Incar_RR_phys); +#endif // CANDB_DBG_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->dbg_Sen_Incar_MultMsg_Idx & (0x03U)) | ((_m->dbg_Sen_Incar_Raw_FL_ro & (0x0FU)) << 4U) | ((_m->dbg_Sen_Incar_FL_ro & (0x0FU)) << 4U) ); + _d[1] |= (uint8_t) ( ((_m->dbg_Sen_Incar_Raw_FL_ro >> 4U) & (0xFFU)) | ((_m->dbg_Sen_Incar_FL_ro >> 4U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->dbg_Sen_Incar_Raw_FR_ro & (0xFFU)) | (_m->dbg_Sen_Incar_FR_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->dbg_Sen_Incar_Raw_FR_ro >> 8U) & (0x0FU)) | ((_m->dbg_Sen_Incar_FR_ro >> 8U) & (0x0FU)) | ((_m->dbg_Sen_Incar_Raw_RL_ro & (0x0FU)) << 4U) | ((_m->dbg_Sen_Incar_RL_ro & (0x0FU)) << 4U) ); + _d[4] |= (uint8_t) ( ((_m->dbg_Sen_Incar_Raw_RL_ro >> 4U) & (0xFFU)) | ((_m->dbg_Sen_Incar_RL_ro >> 4U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->dbg_Sen_Incar_Raw_RR_ro & (0xFFU)) | (_m->dbg_Sen_Incar_RR_ro & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->dbg_Sen_Incar_Raw_RR_ro >> 8U) & (0x0FU)) | ((_m->dbg_Sen_Incar_RR_ro >> 8U) & (0x0FU)) ); + + *_len = (uint8_t) dbg_Sen_Incar_DLC; + *_ide = (uint8_t) dbg_Sen_Incar_IDE; + return dbg_Sen_Incar_CANID; +} + +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Cmd_Act_Information_candb_dbg(dbg_Cmd_Act_Information_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Cmd_Target_Act_Index = (uint8_t) ( (_d[0] & (0x3FU)) ); + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < dbg_Cmd_Act_Information_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_dbg_Cmd_Act_Information_candb_dbg(&_m->mon1, dbg_Cmd_Act_Information_CANID); +#endif // CANDB_DBG_USE_DIAG_MONITORS + + return dbg_Cmd_Act_Information_CANID; +} + +#ifdef CANDB_DBG_USE_CANSTRUCT + +uint32_t Pack_dbg_Cmd_Act_Information_candb_dbg(dbg_Cmd_Act_Information_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Cmd_Act_Information_DLC); cframe->Data[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->Cmd_Target_Act_Index & (0x3FU)) ); + + cframe->MsgId = (uint32_t) dbg_Cmd_Act_Information_CANID; + cframe->DLC = (uint8_t) dbg_Cmd_Act_Information_DLC; + cframe->IDE = (uint8_t) dbg_Cmd_Act_Information_IDE; + return dbg_Cmd_Act_Information_CANID; +} + +#else + +uint32_t Pack_dbg_Cmd_Act_Information_candb_dbg(dbg_Cmd_Act_Information_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Cmd_Act_Information_DLC); _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->Cmd_Target_Act_Index & (0x3FU)) ); + + *_len = (uint8_t) dbg_Cmd_Act_Information_DLC; + *_ide = (uint8_t) dbg_Cmd_Act_Information_IDE; + return dbg_Cmd_Act_Information_CANID; +} + +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Info_Act1_candb_dbg(dbg_Info_Act1_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->dbg_Info_Act_Index = (uint8_t) ( (_d[0] & (0x3FU)) ); + _m->dbg_Info_Act_App_Percent_ro = (uint16_t) ( ((_d[1] & (0xFFU)) << 2U) | ((_d[0] >> 6U) & (0x03U)) ); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Info_Act_App_Percent_phys = (sigfloat_t)(CANDB_DBG_dbg_Info_Act_App_Percent_ro_fromS(_m->dbg_Info_Act_App_Percent_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Info_Act_with_Limit_Percent_ro = (uint16_t) ( ((_d[3] & (0x03U)) << 8U) | (_d[2] & (0xFFU)) ); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Info_Act_with_Limit_Percent_phys = (sigfloat_t)(CANDB_DBG_dbg_Info_Act_with_Limit_Percent_ro_fromS(_m->dbg_Info_Act_with_Limit_Percent_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Info_Act_Current_Count = (uint16_t) ( ((_d[4] & (0x3FU)) << 6U) | ((_d[3] >> 2U) & (0x3FU)) ); + _m->dbg_Info_Act_Range_Count = (uint16_t) ( ((_d[6] & (0x03U)) << 10U) | ((_d[5] & (0xFFU)) << 2U) | ((_d[4] >> 6U) & (0x03U)) ); + _m->dbg_Info_Act_Default_Count = (uint16_t) ( ((_d[7] & (0x3FU)) << 6U) | ((_d[6] >> 2U) & (0x3FU)) ); + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < dbg_Info_Act1_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_dbg_Info_Act1_candb_dbg(&_m->mon1, dbg_Info_Act1_CANID); +#endif // CANDB_DBG_USE_DIAG_MONITORS + + return dbg_Info_Act1_CANID; +} + +#ifdef CANDB_DBG_USE_CANSTRUCT + +uint32_t Pack_dbg_Info_Act1_candb_dbg(dbg_Info_Act1_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Info_Act1_DLC); cframe->Data[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Info_Act_App_Percent_ro = (uint16_t) CANDB_DBG_dbg_Info_Act_App_Percent_ro_toS(_m->dbg_Info_Act_App_Percent_phys); + _m->dbg_Info_Act_with_Limit_Percent_ro = (uint16_t) CANDB_DBG_dbg_Info_Act_with_Limit_Percent_ro_toS(_m->dbg_Info_Act_with_Limit_Percent_phys); +#endif // CANDB_DBG_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->dbg_Info_Act_Index & (0x3FU)) | ((_m->dbg_Info_Act_App_Percent_ro & (0x03U)) << 6U) ); + cframe->Data[1] |= (uint8_t) ( ((_m->dbg_Info_Act_App_Percent_ro >> 2U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->dbg_Info_Act_with_Limit_Percent_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->dbg_Info_Act_with_Limit_Percent_ro >> 8U) & (0x03U)) | ((_m->dbg_Info_Act_Current_Count & (0x3FU)) << 2U) ); + cframe->Data[4] |= (uint8_t) ( ((_m->dbg_Info_Act_Current_Count >> 6U) & (0x3FU)) | ((_m->dbg_Info_Act_Range_Count & (0x03U)) << 6U) ); + cframe->Data[5] |= (uint8_t) ( ((_m->dbg_Info_Act_Range_Count >> 2U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->dbg_Info_Act_Range_Count >> 10U) & (0x03U)) | ((_m->dbg_Info_Act_Default_Count & (0x3FU)) << 2U) ); + cframe->Data[7] |= (uint8_t) ( ((_m->dbg_Info_Act_Default_Count >> 6U) & (0x3FU)) ); + + cframe->MsgId = (uint32_t) dbg_Info_Act1_CANID; + cframe->DLC = (uint8_t) dbg_Info_Act1_DLC; + cframe->IDE = (uint8_t) dbg_Info_Act1_IDE; + return dbg_Info_Act1_CANID; +} + +#else + +uint32_t Pack_dbg_Info_Act1_candb_dbg(dbg_Info_Act1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Info_Act1_DLC); _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Info_Act_App_Percent_ro = (uint16_t) CANDB_DBG_dbg_Info_Act_App_Percent_ro_toS(_m->dbg_Info_Act_App_Percent_phys); + _m->dbg_Info_Act_with_Limit_Percent_ro = (uint16_t) CANDB_DBG_dbg_Info_Act_with_Limit_Percent_ro_toS(_m->dbg_Info_Act_with_Limit_Percent_phys); +#endif // CANDB_DBG_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->dbg_Info_Act_Index & (0x3FU)) | ((_m->dbg_Info_Act_App_Percent_ro & (0x03U)) << 6U) ); + _d[1] |= (uint8_t) ( ((_m->dbg_Info_Act_App_Percent_ro >> 2U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->dbg_Info_Act_with_Limit_Percent_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->dbg_Info_Act_with_Limit_Percent_ro >> 8U) & (0x03U)) | ((_m->dbg_Info_Act_Current_Count & (0x3FU)) << 2U) ); + _d[4] |= (uint8_t) ( ((_m->dbg_Info_Act_Current_Count >> 6U) & (0x3FU)) | ((_m->dbg_Info_Act_Range_Count & (0x03U)) << 6U) ); + _d[5] |= (uint8_t) ( ((_m->dbg_Info_Act_Range_Count >> 2U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->dbg_Info_Act_Range_Count >> 10U) & (0x03U)) | ((_m->dbg_Info_Act_Default_Count & (0x3FU)) << 2U) ); + _d[7] |= (uint8_t) ( ((_m->dbg_Info_Act_Default_Count >> 6U) & (0x3FU)) ); + + *_len = (uint8_t) dbg_Info_Act1_DLC; + *_ide = (uint8_t) dbg_Info_Act1_IDE; + return dbg_Info_Act1_CANID; +} + +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Info_Act2_candb_dbg(dbg_Info_Act2_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->dbg_Info_Act_Msg_Missing_Flag = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->dbg_Info_Act_Internal_Fail_Flag = (uint8_t) ( ((_d[0] >> 1U) & (0x01U)) ); + _m->dbg_Info_Act_Homing_Err_Flag = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + _m->dbg_Info_Act_Range_Err_Flag = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + _m->dbg_Info_Act_Range_Fail_Flag = (uint8_t) ( ((_d[0] >> 4U) & (0x01U)) ); + _m->dbg_Info_Act_Range_Err_Operation = (uint8_t) ( ((_d[0] >> 5U) & (0x01U)) ); + _m->dbg_Info_Act_Range_Err_Check_Cnt = (uint8_t) ( (_d[1] & (0xFFU)) ); + _m->dbg_Info_Act_Range_Err_Timer = (uint16_t) ( ((_d[3] & (0x03U)) << 8U) | (_d[2] & (0xFFU)) ); + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < dbg_Info_Act2_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_dbg_Info_Act2_candb_dbg(&_m->mon1, dbg_Info_Act2_CANID); +#endif // CANDB_DBG_USE_DIAG_MONITORS + + return dbg_Info_Act2_CANID; +} + +#ifdef CANDB_DBG_USE_CANSTRUCT + +uint32_t Pack_dbg_Info_Act2_candb_dbg(dbg_Info_Act2_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Info_Act2_DLC); cframe->Data[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->dbg_Info_Act_Msg_Missing_Flag & (0x01U)) | ((_m->dbg_Info_Act_Internal_Fail_Flag & (0x01U)) << 1U) | ((_m->dbg_Info_Act_Homing_Err_Flag & (0x01U)) << 2U) | ((_m->dbg_Info_Act_Range_Err_Flag & (0x01U)) << 3U) | ((_m->dbg_Info_Act_Range_Fail_Flag & (0x01U)) << 4U) | ((_m->dbg_Info_Act_Range_Err_Operation & (0x01U)) << 5U) ); + cframe->Data[1] |= (uint8_t) ( (_m->dbg_Info_Act_Range_Err_Check_Cnt & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->dbg_Info_Act_Range_Err_Timer & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->dbg_Info_Act_Range_Err_Timer >> 8U) & (0x03U)) ); + + cframe->MsgId = (uint32_t) dbg_Info_Act2_CANID; + cframe->DLC = (uint8_t) dbg_Info_Act2_DLC; + cframe->IDE = (uint8_t) dbg_Info_Act2_IDE; + return dbg_Info_Act2_CANID; +} + +#else + +uint32_t Pack_dbg_Info_Act2_candb_dbg(dbg_Info_Act2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Info_Act2_DLC); _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->dbg_Info_Act_Msg_Missing_Flag & (0x01U)) | ((_m->dbg_Info_Act_Internal_Fail_Flag & (0x01U)) << 1U) | ((_m->dbg_Info_Act_Homing_Err_Flag & (0x01U)) << 2U) | ((_m->dbg_Info_Act_Range_Err_Flag & (0x01U)) << 3U) | ((_m->dbg_Info_Act_Range_Fail_Flag & (0x01U)) << 4U) | ((_m->dbg_Info_Act_Range_Err_Operation & (0x01U)) << 5U) ); + _d[1] |= (uint8_t) ( (_m->dbg_Info_Act_Range_Err_Check_Cnt & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->dbg_Info_Act_Range_Err_Timer & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->dbg_Info_Act_Range_Err_Timer >> 8U) & (0x03U)) ); + + *_len = (uint8_t) dbg_Info_Act2_DLC; + *_ide = (uint8_t) dbg_Info_Act2_IDE; + return dbg_Info_Act2_CANID; +} + +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Sen_Eva_candb_dbg(dbg_Sen_Eva_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->dbg_Sen_Eva_Target_ro = (int16_t) __ext_sig__(( ((_d[1] & (0x0FU)) << 8U) | (_d[0] & (0xFFU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Eva_Target_phys = (sigfloat_t)(CANDB_DBG_dbg_Sen_Eva_Target_ro_fromS(_m->dbg_Sen_Eva_Target_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Sen_Eva_Diff_FrontRear_ro = (int16_t) __ext_sig__(( ((_d[3] & (0x0FU)) << 8U) | (_d[2] & (0xFFU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Eva_Diff_FrontRear_phys = (sigfloat_t)(CANDB_DBG_dbg_Sen_Eva_Diff_FrontRear_ro_fromS(_m->dbg_Sen_Eva_Diff_FrontRear_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Sen_Eva_F_ro = (int16_t) __ext_sig__(( ((_d[5] & (0x0FU)) << 8U) | (_d[4] & (0xFFU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Eva_F_phys = (sigfloat_t)(CANDB_DBG_dbg_Sen_Eva_F_ro_fromS(_m->dbg_Sen_Eva_F_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Sen_Eva_R_ro = (int16_t) __ext_sig__(( ((_d[7] & (0x0FU)) << 8U) | (_d[6] & (0xFFU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Eva_R_phys = (sigfloat_t)(CANDB_DBG_dbg_Sen_Eva_R_ro_fromS(_m->dbg_Sen_Eva_R_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < dbg_Sen_Eva_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_dbg_Sen_Eva_candb_dbg(&_m->mon1, dbg_Sen_Eva_CANID); +#endif // CANDB_DBG_USE_DIAG_MONITORS + + return dbg_Sen_Eva_CANID; +} + +#ifdef CANDB_DBG_USE_CANSTRUCT + +uint32_t Pack_dbg_Sen_Eva_candb_dbg(dbg_Sen_Eva_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Sen_Eva_DLC); cframe->Data[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Eva_Target_ro = (int16_t) CANDB_DBG_dbg_Sen_Eva_Target_ro_toS(_m->dbg_Sen_Eva_Target_phys); + _m->dbg_Sen_Eva_Diff_FrontRear_ro = (int16_t) CANDB_DBG_dbg_Sen_Eva_Diff_FrontRear_ro_toS(_m->dbg_Sen_Eva_Diff_FrontRear_phys); + _m->dbg_Sen_Eva_F_ro = (int16_t) CANDB_DBG_dbg_Sen_Eva_F_ro_toS(_m->dbg_Sen_Eva_F_phys); + _m->dbg_Sen_Eva_R_ro = (int16_t) CANDB_DBG_dbg_Sen_Eva_R_ro_toS(_m->dbg_Sen_Eva_R_phys); +#endif // CANDB_DBG_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->dbg_Sen_Eva_Target_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->dbg_Sen_Eva_Target_ro >> 8U) & (0x0FU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->dbg_Sen_Eva_Diff_FrontRear_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->dbg_Sen_Eva_Diff_FrontRear_ro >> 8U) & (0x0FU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->dbg_Sen_Eva_F_ro & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->dbg_Sen_Eva_F_ro >> 8U) & (0x0FU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->dbg_Sen_Eva_R_ro & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( ((_m->dbg_Sen_Eva_R_ro >> 8U) & (0x0FU)) ); + + cframe->MsgId = (uint32_t) dbg_Sen_Eva_CANID; + cframe->DLC = (uint8_t) dbg_Sen_Eva_DLC; + cframe->IDE = (uint8_t) dbg_Sen_Eva_IDE; + return dbg_Sen_Eva_CANID; +} + +#else + +uint32_t Pack_dbg_Sen_Eva_candb_dbg(dbg_Sen_Eva_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Sen_Eva_DLC); _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Eva_Target_ro = (int16_t) CANDB_DBG_dbg_Sen_Eva_Target_ro_toS(_m->dbg_Sen_Eva_Target_phys); + _m->dbg_Sen_Eva_Diff_FrontRear_ro = (int16_t) CANDB_DBG_dbg_Sen_Eva_Diff_FrontRear_ro_toS(_m->dbg_Sen_Eva_Diff_FrontRear_phys); + _m->dbg_Sen_Eva_F_ro = (int16_t) CANDB_DBG_dbg_Sen_Eva_F_ro_toS(_m->dbg_Sen_Eva_F_phys); + _m->dbg_Sen_Eva_R_ro = (int16_t) CANDB_DBG_dbg_Sen_Eva_R_ro_toS(_m->dbg_Sen_Eva_R_phys); +#endif // CANDB_DBG_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->dbg_Sen_Eva_Target_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->dbg_Sen_Eva_Target_ro >> 8U) & (0x0FU)) ); + _d[2] |= (uint8_t) ( (_m->dbg_Sen_Eva_Diff_FrontRear_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->dbg_Sen_Eva_Diff_FrontRear_ro >> 8U) & (0x0FU)) ); + _d[4] |= (uint8_t) ( (_m->dbg_Sen_Eva_F_ro & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->dbg_Sen_Eva_F_ro >> 8U) & (0x0FU)) ); + _d[6] |= (uint8_t) ( (_m->dbg_Sen_Eva_R_ro & (0xFFU)) ); + _d[7] |= (uint8_t) ( ((_m->dbg_Sen_Eva_R_ro >> 8U) & (0x0FU)) ); + + *_len = (uint8_t) dbg_Sen_Eva_DLC; + *_ide = (uint8_t) dbg_Sen_Eva_IDE; + return dbg_Sen_Eva_CANID; +} + +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Sen_Duct_candb_dbg(dbg_Sen_Duct_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->dbg_Sen_Duct_MultMsg_Idx = (uint8_t) ( (_d[0] & (0x03U)) ); + _m->dbg_Sen_Duct_FL_Fb_Select = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + _m->dbg_Sen_Duct_RR_Fb_Select = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + _m->dbg_Sen_Duct_RL_Fb_Select = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + _m->dbg_Sen_Duct_FR_Fb_Select = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + _m->dbg_Sen_Duct_RL_Tgt_ro = (int16_t) __ext_sig__(( ((_d[1] & (0xFFU)) << 4U) | ((_d[0] >> 4U) & (0x0FU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Duct_RL_Tgt_phys = (sigfloat_t)(CANDB_DBG_dbg_Sen_Duct_RL_Tgt_ro_fromS(_m->dbg_Sen_Duct_RL_Tgt_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Sen_Duct_FR_Upper_Tgt_ro = (int16_t) __ext_sig__(( ((_d[1] & (0xFFU)) << 4U) | ((_d[0] >> 4U) & (0x0FU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Duct_FR_Upper_Tgt_phys = (sigfloat_t)(CANDB_DBG_dbg_Sen_Duct_FR_Upper_Tgt_ro_fromS(_m->dbg_Sen_Duct_FR_Upper_Tgt_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Sen_Duct_RR_Tgt_ro = (int16_t) __ext_sig__(( ((_d[1] & (0xFFU)) << 4U) | ((_d[0] >> 4U) & (0x0FU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Duct_RR_Tgt_phys = (sigfloat_t)(CANDB_DBG_dbg_Sen_Duct_RR_Tgt_ro_fromS(_m->dbg_Sen_Duct_RR_Tgt_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Sen_Duct_FL_Upper_Tgt_ro = (int16_t) __ext_sig__(( ((_d[1] & (0xFFU)) << 4U) | ((_d[0] >> 4U) & (0x0FU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Duct_FL_Upper_Tgt_phys = (sigfloat_t)(CANDB_DBG_dbg_Sen_Duct_FL_Upper_Tgt_ro_fromS(_m->dbg_Sen_Duct_FL_Upper_Tgt_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Sen_Duct_RR_Fb_ro = (int16_t) __ext_sig__(( ((_d[3] & (0x0FU)) << 8U) | (_d[2] & (0xFFU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Duct_RR_Fb_phys = (sigfloat_t)(CANDB_DBG_dbg_Sen_Duct_RR_Fb_ro_fromS(_m->dbg_Sen_Duct_RR_Fb_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Sen_Duct_RL_Fb_ro = (int16_t) __ext_sig__(( ((_d[3] & (0x0FU)) << 8U) | (_d[2] & (0xFFU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Duct_RL_Fb_phys = (sigfloat_t)(CANDB_DBG_dbg_Sen_Duct_RL_Fb_ro_fromS(_m->dbg_Sen_Duct_RL_Fb_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Sen_Duct_FR_Upper_Fb_ro = (int16_t) __ext_sig__(( ((_d[3] & (0x0FU)) << 8U) | (_d[2] & (0xFFU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Duct_FR_Upper_Fb_phys = (sigfloat_t)(CANDB_DBG_dbg_Sen_Duct_FR_Upper_Fb_ro_fromS(_m->dbg_Sen_Duct_FR_Upper_Fb_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Sen_Duct_FL_Upper_Fb_ro = (int16_t) __ext_sig__(( ((_d[3] & (0x0FU)) << 8U) | (_d[2] & (0xFFU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Duct_FL_Upper_Fb_phys = (sigfloat_t)(CANDB_DBG_dbg_Sen_Duct_FL_Upper_Fb_ro_fromS(_m->dbg_Sen_Duct_FL_Upper_Fb_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Sen_Duct_FR_Side_Fb_ro = (int16_t) __ext_sig__(( ((_d[4] & (0xFFU)) << 4U) | ((_d[3] >> 4U) & (0x0FU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Duct_FR_Side_Fb_phys = (sigfloat_t)(CANDB_DBG_dbg_Sen_Duct_FR_Side_Fb_ro_fromS(_m->dbg_Sen_Duct_FR_Side_Fb_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Sen_Duct_FL_Side_Fb_ro = (int16_t) __ext_sig__(( ((_d[4] & (0xFFU)) << 4U) | ((_d[3] >> 4U) & (0x0FU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Duct_FL_Side_Fb_phys = (sigfloat_t)(CANDB_DBG_dbg_Sen_Duct_FL_Side_Fb_ro_fromS(_m->dbg_Sen_Duct_FL_Side_Fb_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Sen_Duct_RL_Side_Fb_ro = (int16_t) __ext_sig__(( ((_d[4] & (0xFFU)) << 4U) | ((_d[3] >> 4U) & (0x0FU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Duct_RL_Side_Fb_phys = (sigfloat_t)(CANDB_DBG_dbg_Sen_Duct_RL_Side_Fb_ro_fromS(_m->dbg_Sen_Duct_RL_Side_Fb_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Sen_Duct_RR_Side_Fb_ro = (int16_t) __ext_sig__(( ((_d[4] & (0xFFU)) << 4U) | ((_d[3] >> 4U) & (0x0FU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Duct_RR_Side_Fb_phys = (sigfloat_t)(CANDB_DBG_dbg_Sen_Duct_RR_Side_Fb_ro_fromS(_m->dbg_Sen_Duct_RR_Side_Fb_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Sen_Duct_FR_Lower_Tgt_ro = (int16_t) __ext_sig__(( ((_d[6] & (0x0FU)) << 8U) | (_d[5] & (0xFFU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Duct_FR_Lower_Tgt_phys = (sigfloat_t)(CANDB_DBG_dbg_Sen_Duct_FR_Lower_Tgt_ro_fromS(_m->dbg_Sen_Duct_FR_Lower_Tgt_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Sen_Duct_FL_Lower_Tgt_ro = (int16_t) __ext_sig__(( ((_d[6] & (0x0FU)) << 8U) | (_d[5] & (0xFFU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Duct_FL_Lower_Tgt_phys = (sigfloat_t)(CANDB_DBG_dbg_Sen_Duct_FL_Lower_Tgt_ro_fromS(_m->dbg_Sen_Duct_FL_Lower_Tgt_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Sen_Duct_FR_Lower_Fb_ro = (int16_t) __ext_sig__(( ((_d[7] & (0xFFU)) << 4U) | ((_d[6] >> 4U) & (0x0FU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Duct_FR_Lower_Fb_phys = (sigfloat_t)(CANDB_DBG_dbg_Sen_Duct_FR_Lower_Fb_ro_fromS(_m->dbg_Sen_Duct_FR_Lower_Fb_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Sen_Duct_FL_Lower_Fb_ro = (int16_t) __ext_sig__(( ((_d[7] & (0xFFU)) << 4U) | ((_d[6] >> 4U) & (0x0FU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Duct_FL_Lower_Fb_phys = (sigfloat_t)(CANDB_DBG_dbg_Sen_Duct_FL_Lower_Fb_ro_fromS(_m->dbg_Sen_Duct_FL_Lower_Fb_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < dbg_Sen_Duct_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_dbg_Sen_Duct_candb_dbg(&_m->mon1, dbg_Sen_Duct_CANID); +#endif // CANDB_DBG_USE_DIAG_MONITORS + + return dbg_Sen_Duct_CANID; +} + +#ifdef CANDB_DBG_USE_CANSTRUCT + +uint32_t Pack_dbg_Sen_Duct_candb_dbg(dbg_Sen_Duct_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Sen_Duct_DLC); cframe->Data[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Duct_RL_Tgt_ro = (int16_t) CANDB_DBG_dbg_Sen_Duct_RL_Tgt_ro_toS(_m->dbg_Sen_Duct_RL_Tgt_phys); + _m->dbg_Sen_Duct_FR_Upper_Tgt_ro = (int16_t) CANDB_DBG_dbg_Sen_Duct_FR_Upper_Tgt_ro_toS(_m->dbg_Sen_Duct_FR_Upper_Tgt_phys); + _m->dbg_Sen_Duct_RR_Tgt_ro = (int16_t) CANDB_DBG_dbg_Sen_Duct_RR_Tgt_ro_toS(_m->dbg_Sen_Duct_RR_Tgt_phys); + _m->dbg_Sen_Duct_FL_Upper_Tgt_ro = (int16_t) CANDB_DBG_dbg_Sen_Duct_FL_Upper_Tgt_ro_toS(_m->dbg_Sen_Duct_FL_Upper_Tgt_phys); + _m->dbg_Sen_Duct_RR_Fb_ro = (int16_t) CANDB_DBG_dbg_Sen_Duct_RR_Fb_ro_toS(_m->dbg_Sen_Duct_RR_Fb_phys); + _m->dbg_Sen_Duct_RL_Fb_ro = (int16_t) CANDB_DBG_dbg_Sen_Duct_RL_Fb_ro_toS(_m->dbg_Sen_Duct_RL_Fb_phys); + _m->dbg_Sen_Duct_FR_Upper_Fb_ro = (int16_t) CANDB_DBG_dbg_Sen_Duct_FR_Upper_Fb_ro_toS(_m->dbg_Sen_Duct_FR_Upper_Fb_phys); + _m->dbg_Sen_Duct_FL_Upper_Fb_ro = (int16_t) CANDB_DBG_dbg_Sen_Duct_FL_Upper_Fb_ro_toS(_m->dbg_Sen_Duct_FL_Upper_Fb_phys); + _m->dbg_Sen_Duct_FR_Side_Fb_ro = (int16_t) CANDB_DBG_dbg_Sen_Duct_FR_Side_Fb_ro_toS(_m->dbg_Sen_Duct_FR_Side_Fb_phys); + _m->dbg_Sen_Duct_FL_Side_Fb_ro = (int16_t) CANDB_DBG_dbg_Sen_Duct_FL_Side_Fb_ro_toS(_m->dbg_Sen_Duct_FL_Side_Fb_phys); + _m->dbg_Sen_Duct_RL_Side_Fb_ro = (int16_t) CANDB_DBG_dbg_Sen_Duct_RL_Side_Fb_ro_toS(_m->dbg_Sen_Duct_RL_Side_Fb_phys); + _m->dbg_Sen_Duct_RR_Side_Fb_ro = (int16_t) CANDB_DBG_dbg_Sen_Duct_RR_Side_Fb_ro_toS(_m->dbg_Sen_Duct_RR_Side_Fb_phys); + _m->dbg_Sen_Duct_FR_Lower_Tgt_ro = (int16_t) CANDB_DBG_dbg_Sen_Duct_FR_Lower_Tgt_ro_toS(_m->dbg_Sen_Duct_FR_Lower_Tgt_phys); + _m->dbg_Sen_Duct_FL_Lower_Tgt_ro = (int16_t) CANDB_DBG_dbg_Sen_Duct_FL_Lower_Tgt_ro_toS(_m->dbg_Sen_Duct_FL_Lower_Tgt_phys); + _m->dbg_Sen_Duct_FR_Lower_Fb_ro = (int16_t) CANDB_DBG_dbg_Sen_Duct_FR_Lower_Fb_ro_toS(_m->dbg_Sen_Duct_FR_Lower_Fb_phys); + _m->dbg_Sen_Duct_FL_Lower_Fb_ro = (int16_t) CANDB_DBG_dbg_Sen_Duct_FL_Lower_Fb_ro_toS(_m->dbg_Sen_Duct_FL_Lower_Fb_phys); +#endif // CANDB_DBG_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->dbg_Sen_Duct_MultMsg_Idx & (0x03U)) | ((_m->dbg_Sen_Duct_FL_Fb_Select & (0x01U)) << 3U) | ((_m->dbg_Sen_Duct_RR_Fb_Select & (0x01U)) << 3U) | ((_m->dbg_Sen_Duct_RL_Fb_Select & (0x01U)) << 3U) | ((_m->dbg_Sen_Duct_FR_Fb_Select & (0x01U)) << 3U) | ((_m->dbg_Sen_Duct_RL_Tgt_ro & (0x0FU)) << 4U) | ((_m->dbg_Sen_Duct_FR_Upper_Tgt_ro & (0x0FU)) << 4U) | ((_m->dbg_Sen_Duct_RR_Tgt_ro & (0x0FU)) << 4U) | ((_m->dbg_Sen_Duct_FL_Upper_Tgt_ro & (0x0FU)) << 4U) ); + cframe->Data[1] |= (uint8_t) ( ((_m->dbg_Sen_Duct_RL_Tgt_ro >> 4U) & (0xFFU)) | ((_m->dbg_Sen_Duct_FR_Upper_Tgt_ro >> 4U) & (0xFFU)) | ((_m->dbg_Sen_Duct_RR_Tgt_ro >> 4U) & (0xFFU)) | ((_m->dbg_Sen_Duct_FL_Upper_Tgt_ro >> 4U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->dbg_Sen_Duct_RR_Fb_ro & (0xFFU)) | (_m->dbg_Sen_Duct_RL_Fb_ro & (0xFFU)) | (_m->dbg_Sen_Duct_FR_Upper_Fb_ro & (0xFFU)) | (_m->dbg_Sen_Duct_FL_Upper_Fb_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->dbg_Sen_Duct_RR_Fb_ro >> 8U) & (0x0FU)) | ((_m->dbg_Sen_Duct_RL_Fb_ro >> 8U) & (0x0FU)) | ((_m->dbg_Sen_Duct_FR_Upper_Fb_ro >> 8U) & (0x0FU)) | ((_m->dbg_Sen_Duct_FL_Upper_Fb_ro >> 8U) & (0x0FU)) | ((_m->dbg_Sen_Duct_FR_Side_Fb_ro & (0x0FU)) << 4U) | ((_m->dbg_Sen_Duct_FL_Side_Fb_ro & (0x0FU)) << 4U) | ((_m->dbg_Sen_Duct_RL_Side_Fb_ro & (0x0FU)) << 4U) | ((_m->dbg_Sen_Duct_RR_Side_Fb_ro & (0x0FU)) << 4U) ); + cframe->Data[4] |= (uint8_t) ( ((_m->dbg_Sen_Duct_FR_Side_Fb_ro >> 4U) & (0xFFU)) | ((_m->dbg_Sen_Duct_FL_Side_Fb_ro >> 4U) & (0xFFU)) | ((_m->dbg_Sen_Duct_RL_Side_Fb_ro >> 4U) & (0xFFU)) | ((_m->dbg_Sen_Duct_RR_Side_Fb_ro >> 4U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->dbg_Sen_Duct_FR_Lower_Tgt_ro & (0xFFU)) | (_m->dbg_Sen_Duct_FL_Lower_Tgt_ro & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->dbg_Sen_Duct_FR_Lower_Tgt_ro >> 8U) & (0x0FU)) | ((_m->dbg_Sen_Duct_FL_Lower_Tgt_ro >> 8U) & (0x0FU)) | ((_m->dbg_Sen_Duct_FR_Lower_Fb_ro & (0x0FU)) << 4U) | ((_m->dbg_Sen_Duct_FL_Lower_Fb_ro & (0x0FU)) << 4U) ); + cframe->Data[7] |= (uint8_t) ( ((_m->dbg_Sen_Duct_FR_Lower_Fb_ro >> 4U) & (0xFFU)) | ((_m->dbg_Sen_Duct_FL_Lower_Fb_ro >> 4U) & (0xFFU)) ); + + cframe->MsgId = (uint32_t) dbg_Sen_Duct_CANID; + cframe->DLC = (uint8_t) dbg_Sen_Duct_DLC; + cframe->IDE = (uint8_t) dbg_Sen_Duct_IDE; + return dbg_Sen_Duct_CANID; +} + +#else + +uint32_t Pack_dbg_Sen_Duct_candb_dbg(dbg_Sen_Duct_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Sen_Duct_DLC); _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_Duct_RL_Tgt_ro = (int16_t) CANDB_DBG_dbg_Sen_Duct_RL_Tgt_ro_toS(_m->dbg_Sen_Duct_RL_Tgt_phys); + _m->dbg_Sen_Duct_FR_Upper_Tgt_ro = (int16_t) CANDB_DBG_dbg_Sen_Duct_FR_Upper_Tgt_ro_toS(_m->dbg_Sen_Duct_FR_Upper_Tgt_phys); + _m->dbg_Sen_Duct_RR_Tgt_ro = (int16_t) CANDB_DBG_dbg_Sen_Duct_RR_Tgt_ro_toS(_m->dbg_Sen_Duct_RR_Tgt_phys); + _m->dbg_Sen_Duct_FL_Upper_Tgt_ro = (int16_t) CANDB_DBG_dbg_Sen_Duct_FL_Upper_Tgt_ro_toS(_m->dbg_Sen_Duct_FL_Upper_Tgt_phys); + _m->dbg_Sen_Duct_RR_Fb_ro = (int16_t) CANDB_DBG_dbg_Sen_Duct_RR_Fb_ro_toS(_m->dbg_Sen_Duct_RR_Fb_phys); + _m->dbg_Sen_Duct_RL_Fb_ro = (int16_t) CANDB_DBG_dbg_Sen_Duct_RL_Fb_ro_toS(_m->dbg_Sen_Duct_RL_Fb_phys); + _m->dbg_Sen_Duct_FR_Upper_Fb_ro = (int16_t) CANDB_DBG_dbg_Sen_Duct_FR_Upper_Fb_ro_toS(_m->dbg_Sen_Duct_FR_Upper_Fb_phys); + _m->dbg_Sen_Duct_FL_Upper_Fb_ro = (int16_t) CANDB_DBG_dbg_Sen_Duct_FL_Upper_Fb_ro_toS(_m->dbg_Sen_Duct_FL_Upper_Fb_phys); + _m->dbg_Sen_Duct_FR_Side_Fb_ro = (int16_t) CANDB_DBG_dbg_Sen_Duct_FR_Side_Fb_ro_toS(_m->dbg_Sen_Duct_FR_Side_Fb_phys); + _m->dbg_Sen_Duct_FL_Side_Fb_ro = (int16_t) CANDB_DBG_dbg_Sen_Duct_FL_Side_Fb_ro_toS(_m->dbg_Sen_Duct_FL_Side_Fb_phys); + _m->dbg_Sen_Duct_RL_Side_Fb_ro = (int16_t) CANDB_DBG_dbg_Sen_Duct_RL_Side_Fb_ro_toS(_m->dbg_Sen_Duct_RL_Side_Fb_phys); + _m->dbg_Sen_Duct_RR_Side_Fb_ro = (int16_t) CANDB_DBG_dbg_Sen_Duct_RR_Side_Fb_ro_toS(_m->dbg_Sen_Duct_RR_Side_Fb_phys); + _m->dbg_Sen_Duct_FR_Lower_Tgt_ro = (int16_t) CANDB_DBG_dbg_Sen_Duct_FR_Lower_Tgt_ro_toS(_m->dbg_Sen_Duct_FR_Lower_Tgt_phys); + _m->dbg_Sen_Duct_FL_Lower_Tgt_ro = (int16_t) CANDB_DBG_dbg_Sen_Duct_FL_Lower_Tgt_ro_toS(_m->dbg_Sen_Duct_FL_Lower_Tgt_phys); + _m->dbg_Sen_Duct_FR_Lower_Fb_ro = (int16_t) CANDB_DBG_dbg_Sen_Duct_FR_Lower_Fb_ro_toS(_m->dbg_Sen_Duct_FR_Lower_Fb_phys); + _m->dbg_Sen_Duct_FL_Lower_Fb_ro = (int16_t) CANDB_DBG_dbg_Sen_Duct_FL_Lower_Fb_ro_toS(_m->dbg_Sen_Duct_FL_Lower_Fb_phys); +#endif // CANDB_DBG_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->dbg_Sen_Duct_MultMsg_Idx & (0x03U)) | ((_m->dbg_Sen_Duct_FL_Fb_Select & (0x01U)) << 3U) | ((_m->dbg_Sen_Duct_RR_Fb_Select & (0x01U)) << 3U) | ((_m->dbg_Sen_Duct_RL_Fb_Select & (0x01U)) << 3U) | ((_m->dbg_Sen_Duct_FR_Fb_Select & (0x01U)) << 3U) | ((_m->dbg_Sen_Duct_RL_Tgt_ro & (0x0FU)) << 4U) | ((_m->dbg_Sen_Duct_FR_Upper_Tgt_ro & (0x0FU)) << 4U) | ((_m->dbg_Sen_Duct_RR_Tgt_ro & (0x0FU)) << 4U) | ((_m->dbg_Sen_Duct_FL_Upper_Tgt_ro & (0x0FU)) << 4U) ); + _d[1] |= (uint8_t) ( ((_m->dbg_Sen_Duct_RL_Tgt_ro >> 4U) & (0xFFU)) | ((_m->dbg_Sen_Duct_FR_Upper_Tgt_ro >> 4U) & (0xFFU)) | ((_m->dbg_Sen_Duct_RR_Tgt_ro >> 4U) & (0xFFU)) | ((_m->dbg_Sen_Duct_FL_Upper_Tgt_ro >> 4U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->dbg_Sen_Duct_RR_Fb_ro & (0xFFU)) | (_m->dbg_Sen_Duct_RL_Fb_ro & (0xFFU)) | (_m->dbg_Sen_Duct_FR_Upper_Fb_ro & (0xFFU)) | (_m->dbg_Sen_Duct_FL_Upper_Fb_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->dbg_Sen_Duct_RR_Fb_ro >> 8U) & (0x0FU)) | ((_m->dbg_Sen_Duct_RL_Fb_ro >> 8U) & (0x0FU)) | ((_m->dbg_Sen_Duct_FR_Upper_Fb_ro >> 8U) & (0x0FU)) | ((_m->dbg_Sen_Duct_FL_Upper_Fb_ro >> 8U) & (0x0FU)) | ((_m->dbg_Sen_Duct_FR_Side_Fb_ro & (0x0FU)) << 4U) | ((_m->dbg_Sen_Duct_FL_Side_Fb_ro & (0x0FU)) << 4U) | ((_m->dbg_Sen_Duct_RL_Side_Fb_ro & (0x0FU)) << 4U) | ((_m->dbg_Sen_Duct_RR_Side_Fb_ro & (0x0FU)) << 4U) ); + _d[4] |= (uint8_t) ( ((_m->dbg_Sen_Duct_FR_Side_Fb_ro >> 4U) & (0xFFU)) | ((_m->dbg_Sen_Duct_FL_Side_Fb_ro >> 4U) & (0xFFU)) | ((_m->dbg_Sen_Duct_RL_Side_Fb_ro >> 4U) & (0xFFU)) | ((_m->dbg_Sen_Duct_RR_Side_Fb_ro >> 4U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->dbg_Sen_Duct_FR_Lower_Tgt_ro & (0xFFU)) | (_m->dbg_Sen_Duct_FL_Lower_Tgt_ro & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->dbg_Sen_Duct_FR_Lower_Tgt_ro >> 8U) & (0x0FU)) | ((_m->dbg_Sen_Duct_FL_Lower_Tgt_ro >> 8U) & (0x0FU)) | ((_m->dbg_Sen_Duct_FR_Lower_Fb_ro & (0x0FU)) << 4U) | ((_m->dbg_Sen_Duct_FL_Lower_Fb_ro & (0x0FU)) << 4U) ); + _d[7] |= (uint8_t) ( ((_m->dbg_Sen_Duct_FR_Lower_Fb_ro >> 4U) & (0xFFU)) | ((_m->dbg_Sen_Duct_FL_Lower_Fb_ro >> 4U) & (0xFFU)) ); + + *_len = (uint8_t) dbg_Sen_Duct_DLC; + *_ide = (uint8_t) dbg_Sen_Duct_IDE; + return dbg_Sen_Duct_CANID; +} + +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Sen_Demist_candb_dbg(dbg_Sen_Demist_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->dbg_Sen_DewPoint_Diff_ro = (int16_t) __ext_sig__(( ((_d[1] & (0xFFU)) << 8U) | (_d[0] & (0xFFU)) ), 16); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_DewPoint_Diff_phys = (sigfloat_t)(CANDB_DBG_dbg_Sen_DewPoint_Diff_ro_fromS(_m->dbg_Sen_DewPoint_Diff_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Sen_WindShield_Humidity_ro = (uint16_t) ( ((_d[3] & (0x03U)) << 8U) | (_d[2] & (0xFFU)) ); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_WindShield_Humidity_phys = (sigfloat_t)(CANDB_DBG_dbg_Sen_WindShield_Humidity_ro_fromS(_m->dbg_Sen_WindShield_Humidity_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Sen_WindShield_Temp_ro = (int16_t) __ext_sig__(( ((_d[5] & (0xFFU)) << 8U) | (_d[4] & (0xFFU)) ), 16); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_WindShield_Temp_phys = (sigfloat_t)(CANDB_DBG_dbg_Sen_WindShield_Temp_ro_fromS(_m->dbg_Sen_WindShield_Temp_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < dbg_Sen_Demist_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_dbg_Sen_Demist_candb_dbg(&_m->mon1, dbg_Sen_Demist_CANID); +#endif // CANDB_DBG_USE_DIAG_MONITORS + + return dbg_Sen_Demist_CANID; +} + +#ifdef CANDB_DBG_USE_CANSTRUCT + +uint32_t Pack_dbg_Sen_Demist_candb_dbg(dbg_Sen_Demist_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Sen_Demist_DLC); cframe->Data[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_DewPoint_Diff_ro = (int16_t) CANDB_DBG_dbg_Sen_DewPoint_Diff_ro_toS(_m->dbg_Sen_DewPoint_Diff_phys); + _m->dbg_Sen_WindShield_Humidity_ro = (uint16_t) CANDB_DBG_dbg_Sen_WindShield_Humidity_ro_toS(_m->dbg_Sen_WindShield_Humidity_phys); + _m->dbg_Sen_WindShield_Temp_ro = (int16_t) CANDB_DBG_dbg_Sen_WindShield_Temp_ro_toS(_m->dbg_Sen_WindShield_Temp_phys); +#endif // CANDB_DBG_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->dbg_Sen_DewPoint_Diff_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->dbg_Sen_DewPoint_Diff_ro >> 8U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->dbg_Sen_WindShield_Humidity_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->dbg_Sen_WindShield_Humidity_ro >> 8U) & (0x03U)) ); + cframe->Data[4] |= (uint8_t) ( (_m->dbg_Sen_WindShield_Temp_ro & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->dbg_Sen_WindShield_Temp_ro >> 8U) & (0xFFU)) ); + + cframe->MsgId = (uint32_t) dbg_Sen_Demist_CANID; + cframe->DLC = (uint8_t) dbg_Sen_Demist_DLC; + cframe->IDE = (uint8_t) dbg_Sen_Demist_IDE; + return dbg_Sen_Demist_CANID; +} + +#else + +uint32_t Pack_dbg_Sen_Demist_candb_dbg(dbg_Sen_Demist_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Sen_Demist_DLC); _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Sen_DewPoint_Diff_ro = (int16_t) CANDB_DBG_dbg_Sen_DewPoint_Diff_ro_toS(_m->dbg_Sen_DewPoint_Diff_phys); + _m->dbg_Sen_WindShield_Humidity_ro = (uint16_t) CANDB_DBG_dbg_Sen_WindShield_Humidity_ro_toS(_m->dbg_Sen_WindShield_Humidity_phys); + _m->dbg_Sen_WindShield_Temp_ro = (int16_t) CANDB_DBG_dbg_Sen_WindShield_Temp_ro_toS(_m->dbg_Sen_WindShield_Temp_phys); +#endif // CANDB_DBG_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->dbg_Sen_DewPoint_Diff_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->dbg_Sen_DewPoint_Diff_ro >> 8U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->dbg_Sen_WindShield_Humidity_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->dbg_Sen_WindShield_Humidity_ro >> 8U) & (0x03U)) ); + _d[4] |= (uint8_t) ( (_m->dbg_Sen_WindShield_Temp_ro & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->dbg_Sen_WindShield_Temp_ro >> 8U) & (0xFFU)) ); + + *_len = (uint8_t) dbg_Sen_Demist_DLC; + *_ide = (uint8_t) dbg_Sen_Demist_IDE; + return dbg_Sen_Demist_CANID; +} + +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_LIN_AirQS_Stat_candb_dbg(dbg_LIN_AirQS_Stat_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->LIN_AirQS_LinRespErr_Stat = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->LIN_AirQualSen_Stat = (uint8_t) ( ((_d[0] >> 1U) & (0x03U)) ); + _m->LIN_AirQualSenCombined_Val = (uint8_t) ( ((_d[0] >> 3U) & (0x03U)) ); + _m->LIN_AirQualSen_Error_Stat = (uint8_t) ( ((_d[1] >> 1U) & (0x03U)) ); + _m->LIN_AirQualSenCOlvl_Val = (uint8_t) ( ((_d[1] >> 4U) & (0x0FU)) ); + _m->LIN_AirQualSenNOxlvl_Val = (uint8_t) ( (_d[2] & (0x0FU)) ); + _m->LIN_AirQualSenNH3lvl_Val = (uint8_t) ( ((_d[2] >> 4U) & (0x0FU)) ); + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < dbg_LIN_AirQS_Stat_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_dbg_LIN_AirQS_Stat_candb_dbg(&_m->mon1, dbg_LIN_AirQS_Stat_CANID); +#endif // CANDB_DBG_USE_DIAG_MONITORS + + return dbg_LIN_AirQS_Stat_CANID; +} + +#ifdef CANDB_DBG_USE_CANSTRUCT + +uint32_t Pack_dbg_LIN_AirQS_Stat_candb_dbg(dbg_LIN_AirQS_Stat_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_LIN_AirQS_Stat_DLC); cframe->Data[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->LIN_AirQS_LinRespErr_Stat & (0x01U)) | ((_m->LIN_AirQualSen_Stat & (0x03U)) << 1U) | ((_m->LIN_AirQualSenCombined_Val & (0x03U)) << 3U) ); + cframe->Data[1] |= (uint8_t) ( ((_m->LIN_AirQualSen_Error_Stat & (0x03U)) << 1U) | ((_m->LIN_AirQualSenCOlvl_Val & (0x0FU)) << 4U) ); + cframe->Data[2] |= (uint8_t) ( (_m->LIN_AirQualSenNOxlvl_Val & (0x0FU)) | ((_m->LIN_AirQualSenNH3lvl_Val & (0x0FU)) << 4U) ); + + cframe->MsgId = (uint32_t) dbg_LIN_AirQS_Stat_CANID; + cframe->DLC = (uint8_t) dbg_LIN_AirQS_Stat_DLC; + cframe->IDE = (uint8_t) dbg_LIN_AirQS_Stat_IDE; + return dbg_LIN_AirQS_Stat_CANID; +} + +#else + +uint32_t Pack_dbg_LIN_AirQS_Stat_candb_dbg(dbg_LIN_AirQS_Stat_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_LIN_AirQS_Stat_DLC); _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->LIN_AirQS_LinRespErr_Stat & (0x01U)) | ((_m->LIN_AirQualSen_Stat & (0x03U)) << 1U) | ((_m->LIN_AirQualSenCombined_Val & (0x03U)) << 3U) ); + _d[1] |= (uint8_t) ( ((_m->LIN_AirQualSen_Error_Stat & (0x03U)) << 1U) | ((_m->LIN_AirQualSenCOlvl_Val & (0x0FU)) << 4U) ); + _d[2] |= (uint8_t) ( (_m->LIN_AirQualSenNOxlvl_Val & (0x0FU)) | ((_m->LIN_AirQualSenNH3lvl_Val & (0x0FU)) << 4U) ); + + *_len = (uint8_t) dbg_LIN_AirQS_Stat_DLC; + *_ide = (uint8_t) dbg_LIN_AirQS_Stat_IDE; + return dbg_LIN_AirQS_Stat_CANID; +} + +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_LIN_Aroma_Stat_candb_dbg(dbg_LIN_Aroma_Stat_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->LIN_AromaLinRespErr_Stat = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->LIN_Aroma_1CartridgeSw = (uint8_t) ( ((_d[0] >> 1U) & (0x01U)) ); + _m->LIN_Aroma_2CartridgeSw = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + _m->LIN_Aroma_3CartridgeSw = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + _m->LIN_Aroma_Error_Stat = (uint8_t) ( ((_d[0] >> 4U) & (0x03U)) ); + _m->LIN_Aroma_Intens = (uint8_t) ( ((_d[0] >> 6U) & (0x03U)) ); + _m->LIN_Aroma_CartridgeSel = (uint8_t) ( (_d[1] & (0x03U)) ); + _m->LIN_Aroma_1CartridgeFlavor = (uint8_t) ( ((_d[1] >> 2U) & (0x0FU)) ); + _m->LIN_Aroma_2CartridgeFlavor = (uint8_t) ( (_d[2] & (0x0FU)) ); + _m->LIN_Aroma_3CartridgeFlavor = (uint8_t) ( ((_d[2] >> 4U) & (0x0FU)) ); + _m->LIN_Aroma_1CartridgeCapacity_ro = (uint8_t) ( (_d[3] & (0x0FU)) ); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->LIN_Aroma_1CartridgeCapacity_phys = (uint8_t) CANDB_DBG_LIN_Aroma_1CartridgeCapacity_ro_fromS(_m->LIN_Aroma_1CartridgeCapacity_ro); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->LIN_Aroma_2CartridgeCapacity_ro = (uint8_t) ( ((_d[3] >> 4U) & (0x0FU)) ); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->LIN_Aroma_2CartridgeCapacity_phys = (uint8_t) CANDB_DBG_LIN_Aroma_2CartridgeCapacity_ro_fromS(_m->LIN_Aroma_2CartridgeCapacity_ro); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->LIN_Aroma_3CartridgeCapacity_ro = (uint8_t) ( (_d[4] & (0x0FU)) ); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->LIN_Aroma_3CartridgeCapacity_phys = (uint8_t) CANDB_DBG_LIN_Aroma_3CartridgeCapacity_ro_fromS(_m->LIN_Aroma_3CartridgeCapacity_ro); +#endif // CANDB_DBG_USE_SIGFLOAT + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < dbg_LIN_Aroma_Stat_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_dbg_LIN_Aroma_Stat_candb_dbg(&_m->mon1, dbg_LIN_Aroma_Stat_CANID); +#endif // CANDB_DBG_USE_DIAG_MONITORS + + return dbg_LIN_Aroma_Stat_CANID; +} + +#ifdef CANDB_DBG_USE_CANSTRUCT + +uint32_t Pack_dbg_LIN_Aroma_Stat_candb_dbg(dbg_LIN_Aroma_Stat_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_LIN_Aroma_Stat_DLC); cframe->Data[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->LIN_Aroma_1CartridgeCapacity_ro = (uint8_t) CANDB_DBG_LIN_Aroma_1CartridgeCapacity_ro_toS(_m->LIN_Aroma_1CartridgeCapacity_phys); + _m->LIN_Aroma_2CartridgeCapacity_ro = (uint8_t) CANDB_DBG_LIN_Aroma_2CartridgeCapacity_ro_toS(_m->LIN_Aroma_2CartridgeCapacity_phys); + _m->LIN_Aroma_3CartridgeCapacity_ro = (uint8_t) CANDB_DBG_LIN_Aroma_3CartridgeCapacity_ro_toS(_m->LIN_Aroma_3CartridgeCapacity_phys); +#endif // CANDB_DBG_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->LIN_AromaLinRespErr_Stat & (0x01U)) | ((_m->LIN_Aroma_1CartridgeSw & (0x01U)) << 1U) | ((_m->LIN_Aroma_2CartridgeSw & (0x01U)) << 2U) | ((_m->LIN_Aroma_3CartridgeSw & (0x01U)) << 3U) | ((_m->LIN_Aroma_Error_Stat & (0x03U)) << 4U) | ((_m->LIN_Aroma_Intens & (0x03U)) << 6U) ); + cframe->Data[1] |= (uint8_t) ( (_m->LIN_Aroma_CartridgeSel & (0x03U)) | ((_m->LIN_Aroma_1CartridgeFlavor & (0x0FU)) << 2U) ); + cframe->Data[2] |= (uint8_t) ( (_m->LIN_Aroma_2CartridgeFlavor & (0x0FU)) | ((_m->LIN_Aroma_3CartridgeFlavor & (0x0FU)) << 4U) ); + cframe->Data[3] |= (uint8_t) ( (_m->LIN_Aroma_1CartridgeCapacity_ro & (0x0FU)) | ((_m->LIN_Aroma_2CartridgeCapacity_ro & (0x0FU)) << 4U) ); + cframe->Data[4] |= (uint8_t) ( (_m->LIN_Aroma_3CartridgeCapacity_ro & (0x0FU)) ); + + cframe->MsgId = (uint32_t) dbg_LIN_Aroma_Stat_CANID; + cframe->DLC = (uint8_t) dbg_LIN_Aroma_Stat_DLC; + cframe->IDE = (uint8_t) dbg_LIN_Aroma_Stat_IDE; + return dbg_LIN_Aroma_Stat_CANID; +} + +#else + +uint32_t Pack_dbg_LIN_Aroma_Stat_candb_dbg(dbg_LIN_Aroma_Stat_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_LIN_Aroma_Stat_DLC); _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->LIN_Aroma_1CartridgeCapacity_ro = (uint8_t) CANDB_DBG_LIN_Aroma_1CartridgeCapacity_ro_toS(_m->LIN_Aroma_1CartridgeCapacity_phys); + _m->LIN_Aroma_2CartridgeCapacity_ro = (uint8_t) CANDB_DBG_LIN_Aroma_2CartridgeCapacity_ro_toS(_m->LIN_Aroma_2CartridgeCapacity_phys); + _m->LIN_Aroma_3CartridgeCapacity_ro = (uint8_t) CANDB_DBG_LIN_Aroma_3CartridgeCapacity_ro_toS(_m->LIN_Aroma_3CartridgeCapacity_phys); +#endif // CANDB_DBG_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->LIN_AromaLinRespErr_Stat & (0x01U)) | ((_m->LIN_Aroma_1CartridgeSw & (0x01U)) << 1U) | ((_m->LIN_Aroma_2CartridgeSw & (0x01U)) << 2U) | ((_m->LIN_Aroma_3CartridgeSw & (0x01U)) << 3U) | ((_m->LIN_Aroma_Error_Stat & (0x03U)) << 4U) | ((_m->LIN_Aroma_Intens & (0x03U)) << 6U) ); + _d[1] |= (uint8_t) ( (_m->LIN_Aroma_CartridgeSel & (0x03U)) | ((_m->LIN_Aroma_1CartridgeFlavor & (0x0FU)) << 2U) ); + _d[2] |= (uint8_t) ( (_m->LIN_Aroma_2CartridgeFlavor & (0x0FU)) | ((_m->LIN_Aroma_3CartridgeFlavor & (0x0FU)) << 4U) ); + _d[3] |= (uint8_t) ( (_m->LIN_Aroma_1CartridgeCapacity_ro & (0x0FU)) | ((_m->LIN_Aroma_2CartridgeCapacity_ro & (0x0FU)) << 4U) ); + _d[4] |= (uint8_t) ( (_m->LIN_Aroma_3CartridgeCapacity_ro & (0x0FU)) ); + + *_len = (uint8_t) dbg_LIN_Aroma_Stat_DLC; + *_ide = (uint8_t) dbg_LIN_Aroma_Stat_IDE; + return dbg_LIN_Aroma_Stat_CANID; +} + +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_LIN_Ionizer_Stat_candb_dbg(dbg_LIN_Ionizer_Stat_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->LIN_Ionizer_Err_Stat = (uint8_t) ( (_d[0] & (0x03U)) ); + _m->LIN_Ionizer_LinRespErr = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + _m->LIN_Ionizer_Ionization = (uint8_t) ( (_d[1] & (0x03U)) ); + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < dbg_LIN_Ionizer_Stat_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_dbg_LIN_Ionizer_Stat_candb_dbg(&_m->mon1, dbg_LIN_Ionizer_Stat_CANID); +#endif // CANDB_DBG_USE_DIAG_MONITORS + + return dbg_LIN_Ionizer_Stat_CANID; +} + +#ifdef CANDB_DBG_USE_CANSTRUCT + +uint32_t Pack_dbg_LIN_Ionizer_Stat_candb_dbg(dbg_LIN_Ionizer_Stat_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_LIN_Ionizer_Stat_DLC); cframe->Data[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->LIN_Ionizer_Err_Stat & (0x03U)) | ((_m->LIN_Ionizer_LinRespErr & (0x01U)) << 2U) ); + cframe->Data[1] |= (uint8_t) ( (_m->LIN_Ionizer_Ionization & (0x03U)) ); + + cframe->MsgId = (uint32_t) dbg_LIN_Ionizer_Stat_CANID; + cframe->DLC = (uint8_t) dbg_LIN_Ionizer_Stat_DLC; + cframe->IDE = (uint8_t) dbg_LIN_Ionizer_Stat_IDE; + return dbg_LIN_Ionizer_Stat_CANID; +} + +#else + +uint32_t Pack_dbg_LIN_Ionizer_Stat_candb_dbg(dbg_LIN_Ionizer_Stat_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_LIN_Ionizer_Stat_DLC); _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->LIN_Ionizer_Err_Stat & (0x03U)) | ((_m->LIN_Ionizer_LinRespErr & (0x01U)) << 2U) ); + _d[1] |= (uint8_t) ( (_m->LIN_Ionizer_Ionization & (0x03U)) ); + + *_len = (uint8_t) dbg_LIN_Ionizer_Stat_DLC; + *_ide = (uint8_t) dbg_LIN_Ionizer_Stat_IDE; + return dbg_LIN_Ionizer_Stat_CANID; +} + +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_LIN_eTXV_Stat_candb_dbg(dbg_LIN_eTXV_Stat_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->LIN_eTXVee1_Pos_Stat = (uint8_t) ( (_d[0] & (0x7FU)) ); + _m->LIN_eTXV1_LinRespErr_Stat = (uint8_t) ( ((_d[0] >> 7U) & (0x01U)) ); + _m->LIN_eTXVee1_Err_Stat = (uint8_t) ( (_d[1] & (0x03U)) ); + _m->LIN_eTXVee2_Pos_Stat = (uint8_t) ( (_d[2] & (0x7FU)) ); + _m->LIN_eTXV2_LinRespErr_Stat = (uint8_t) ( ((_d[2] >> 7U) & (0x01U)) ); + _m->LIN_eTXVee2_Err_Stat = (uint8_t) ( (_d[3] & (0x03U)) ); + _m->LIN_eTXVeeChiller1_Pos_Stat = (uint8_t) ( (_d[4] & (0x7FU)) ); + _m->LIN_eTXV3_LinRespErr_Stat = (uint8_t) ( ((_d[4] >> 7U) & (0x01U)) ); + _m->LIN_eTXVeeChiller1_Err_Stat = (uint8_t) ( (_d[5] & (0x03U)) ); + _m->LIN_eTXVeeChiller2_Pos_Stat = (uint8_t) ( (_d[6] & (0x7FU)) ); + _m->LIN_eTXV4_LinRespErr_Stat = (uint8_t) ( ((_d[6] >> 7U) & (0x01U)) ); + _m->LIN_eTXVeeChiller2_Err_Stat = (uint8_t) ( (_d[7] & (0x03U)) ); + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < dbg_LIN_eTXV_Stat_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_dbg_LIN_eTXV_Stat_candb_dbg(&_m->mon1, dbg_LIN_eTXV_Stat_CANID); +#endif // CANDB_DBG_USE_DIAG_MONITORS + + return dbg_LIN_eTXV_Stat_CANID; +} + +#ifdef CANDB_DBG_USE_CANSTRUCT + +uint32_t Pack_dbg_LIN_eTXV_Stat_candb_dbg(dbg_LIN_eTXV_Stat_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_LIN_eTXV_Stat_DLC); cframe->Data[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->LIN_eTXVee1_Pos_Stat & (0x7FU)) | ((_m->LIN_eTXV1_LinRespErr_Stat & (0x01U)) << 7U) ); + cframe->Data[1] |= (uint8_t) ( (_m->LIN_eTXVee1_Err_Stat & (0x03U)) ); + cframe->Data[2] |= (uint8_t) ( (_m->LIN_eTXVee2_Pos_Stat & (0x7FU)) | ((_m->LIN_eTXV2_LinRespErr_Stat & (0x01U)) << 7U) ); + cframe->Data[3] |= (uint8_t) ( (_m->LIN_eTXVee2_Err_Stat & (0x03U)) ); + cframe->Data[4] |= (uint8_t) ( (_m->LIN_eTXVeeChiller1_Pos_Stat & (0x7FU)) | ((_m->LIN_eTXV3_LinRespErr_Stat & (0x01U)) << 7U) ); + cframe->Data[5] |= (uint8_t) ( (_m->LIN_eTXVeeChiller1_Err_Stat & (0x03U)) ); + cframe->Data[6] |= (uint8_t) ( (_m->LIN_eTXVeeChiller2_Pos_Stat & (0x7FU)) | ((_m->LIN_eTXV4_LinRespErr_Stat & (0x01U)) << 7U) ); + cframe->Data[7] |= (uint8_t) ( (_m->LIN_eTXVeeChiller2_Err_Stat & (0x03U)) ); + + cframe->MsgId = (uint32_t) dbg_LIN_eTXV_Stat_CANID; + cframe->DLC = (uint8_t) dbg_LIN_eTXV_Stat_DLC; + cframe->IDE = (uint8_t) dbg_LIN_eTXV_Stat_IDE; + return dbg_LIN_eTXV_Stat_CANID; +} + +#else + +uint32_t Pack_dbg_LIN_eTXV_Stat_candb_dbg(dbg_LIN_eTXV_Stat_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_LIN_eTXV_Stat_DLC); _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->LIN_eTXVee1_Pos_Stat & (0x7FU)) | ((_m->LIN_eTXV1_LinRespErr_Stat & (0x01U)) << 7U) ); + _d[1] |= (uint8_t) ( (_m->LIN_eTXVee1_Err_Stat & (0x03U)) ); + _d[2] |= (uint8_t) ( (_m->LIN_eTXVee2_Pos_Stat & (0x7FU)) | ((_m->LIN_eTXV2_LinRespErr_Stat & (0x01U)) << 7U) ); + _d[3] |= (uint8_t) ( (_m->LIN_eTXVee2_Err_Stat & (0x03U)) ); + _d[4] |= (uint8_t) ( (_m->LIN_eTXVeeChiller1_Pos_Stat & (0x7FU)) | ((_m->LIN_eTXV3_LinRespErr_Stat & (0x01U)) << 7U) ); + _d[5] |= (uint8_t) ( (_m->LIN_eTXVeeChiller1_Err_Stat & (0x03U)) ); + _d[6] |= (uint8_t) ( (_m->LIN_eTXVeeChiller2_Pos_Stat & (0x7FU)) | ((_m->LIN_eTXV4_LinRespErr_Stat & (0x01U)) << 7U) ); + _d[7] |= (uint8_t) ( (_m->LIN_eTXVeeChiller2_Err_Stat & (0x03U)) ); + + *_len = (uint8_t) dbg_LIN_eTXV_Stat_DLC; + *_ide = (uint8_t) dbg_LIN_eTXV_Stat_IDE; + return dbg_LIN_eTXV_Stat_CANID; +} + +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_LIN_DRS_Stat_candb_dbg(dbg_LIN_DRS_Stat_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->LIN_DRS_DLLed1 = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->LIN_DRS_DLLed2 = (uint8_t) ( ((_d[0] >> 1U) & (0x01U)) ); + _m->LIN_DRS_DLLed3 = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + _m->LIN_DRS_DRLed1 = (uint8_t) ( ((_d[0] >> 4U) & (0x01U)) ); + _m->LIN_DRS_DRLed2 = (uint8_t) ( ((_d[0] >> 5U) & (0x01U)) ); + _m->LIN_DRS_DRLed3 = (uint8_t) ( ((_d[0] >> 6U) & (0x01U)) ); + _m->LIN_DRS_FPLLed1 = (uint8_t) ( (_d[1] & (0x01U)) ); + _m->LIN_DRS_FPLLed2 = (uint8_t) ( ((_d[1] >> 1U) & (0x01U)) ); + _m->LIN_DRS_FPLLed3 = (uint8_t) ( ((_d[1] >> 2U) & (0x01U)) ); + _m->LIN_DRS_FPRLed1 = (uint8_t) ( ((_d[1] >> 4U) & (0x01U)) ); + _m->LIN_DRS_FPRLed2 = (uint8_t) ( ((_d[1] >> 5U) & (0x01U)) ); + _m->LIN_DRS_FPRLed3 = (uint8_t) ( ((_d[1] >> 6U) & (0x01U)) ); + _m->LIN_DRS_RLBLed1 = (uint8_t) ( (_d[2] & (0x01U)) ); + _m->LIN_DRS_RLBLed2 = (uint8_t) ( ((_d[2] >> 1U) & (0x01U)) ); + _m->LIN_DRS_RLBLed3 = (uint8_t) ( ((_d[2] >> 2U) & (0x01U)) ); + _m->LIN_DRS_RRBLed1 = (uint8_t) ( ((_d[2] >> 4U) & (0x01U)) ); + _m->LIN_DRS_RRBLed2 = (uint8_t) ( ((_d[2] >> 5U) & (0x01U)) ); + _m->LIN_DRS_RRBLed3 = (uint8_t) ( ((_d[2] >> 6U) & (0x01U)) ); + _m->LIN_DRS_FCLLed1 = (uint8_t) ( (_d[3] & (0x01U)) ); + _m->LIN_DRS_FCLLed2 = (uint8_t) ( ((_d[3] >> 1U) & (0x01U)) ); + _m->LIN_DRS_FCLLed3 = (uint8_t) ( ((_d[3] >> 2U) & (0x01U)) ); + _m->LIN_DRS_FCRLed1 = (uint8_t) ( ((_d[3] >> 4U) & (0x01U)) ); + _m->LIN_DRS_FCRLed2 = (uint8_t) ( ((_d[3] >> 5U) & (0x01U)) ); + _m->LIN_DRS_FCRLed3 = (uint8_t) ( ((_d[3] >> 6U) & (0x01U)) ); + _m->LIN_DRS_BCM_IndFadingTime_ro = (uint8_t) ( (_d[4] & (0x1FU)) ); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->LIN_DRS_BCM_IndFadingTime_phys = (sigfloat_t)(CANDB_DBG_LIN_DRS_BCM_IndFadingTime_ro_fromS(_m->LIN_DRS_BCM_IndFadingTime_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->LIN_DRS_BCM_SwIndIntens = (uint8_t) ( ((_d[4] >> 5U) & (0x01U)) ); + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < dbg_LIN_DRS_Stat_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_dbg_LIN_DRS_Stat_candb_dbg(&_m->mon1, dbg_LIN_DRS_Stat_CANID); +#endif // CANDB_DBG_USE_DIAG_MONITORS + + return dbg_LIN_DRS_Stat_CANID; +} + +#ifdef CANDB_DBG_USE_CANSTRUCT + +uint32_t Pack_dbg_LIN_DRS_Stat_candb_dbg(dbg_LIN_DRS_Stat_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_LIN_DRS_Stat_DLC); cframe->Data[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->LIN_DRS_BCM_IndFadingTime_ro = (uint8_t) CANDB_DBG_LIN_DRS_BCM_IndFadingTime_ro_toS(_m->LIN_DRS_BCM_IndFadingTime_phys); +#endif // CANDB_DBG_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->LIN_DRS_DLLed1 & (0x01U)) | ((_m->LIN_DRS_DLLed2 & (0x01U)) << 1U) | ((_m->LIN_DRS_DLLed3 & (0x01U)) << 2U) | ((_m->LIN_DRS_DRLed1 & (0x01U)) << 4U) | ((_m->LIN_DRS_DRLed2 & (0x01U)) << 5U) | ((_m->LIN_DRS_DRLed3 & (0x01U)) << 6U) ); + cframe->Data[1] |= (uint8_t) ( (_m->LIN_DRS_FPLLed1 & (0x01U)) | ((_m->LIN_DRS_FPLLed2 & (0x01U)) << 1U) | ((_m->LIN_DRS_FPLLed3 & (0x01U)) << 2U) | ((_m->LIN_DRS_FPRLed1 & (0x01U)) << 4U) | ((_m->LIN_DRS_FPRLed2 & (0x01U)) << 5U) | ((_m->LIN_DRS_FPRLed3 & (0x01U)) << 6U) ); + cframe->Data[2] |= (uint8_t) ( (_m->LIN_DRS_RLBLed1 & (0x01U)) | ((_m->LIN_DRS_RLBLed2 & (0x01U)) << 1U) | ((_m->LIN_DRS_RLBLed3 & (0x01U)) << 2U) | ((_m->LIN_DRS_RRBLed1 & (0x01U)) << 4U) | ((_m->LIN_DRS_RRBLed2 & (0x01U)) << 5U) | ((_m->LIN_DRS_RRBLed3 & (0x01U)) << 6U) ); + cframe->Data[3] |= (uint8_t) ( (_m->LIN_DRS_FCLLed1 & (0x01U)) | ((_m->LIN_DRS_FCLLed2 & (0x01U)) << 1U) | ((_m->LIN_DRS_FCLLed3 & (0x01U)) << 2U) | ((_m->LIN_DRS_FCRLed1 & (0x01U)) << 4U) | ((_m->LIN_DRS_FCRLed2 & (0x01U)) << 5U) | ((_m->LIN_DRS_FCRLed3 & (0x01U)) << 6U) ); + cframe->Data[4] |= (uint8_t) ( (_m->LIN_DRS_BCM_IndFadingTime_ro & (0x1FU)) | ((_m->LIN_DRS_BCM_SwIndIntens & (0x01U)) << 5U) ); + + cframe->MsgId = (uint32_t) dbg_LIN_DRS_Stat_CANID; + cframe->DLC = (uint8_t) dbg_LIN_DRS_Stat_DLC; + cframe->IDE = (uint8_t) dbg_LIN_DRS_Stat_IDE; + return dbg_LIN_DRS_Stat_CANID; +} + +#else + +uint32_t Pack_dbg_LIN_DRS_Stat_candb_dbg(dbg_LIN_DRS_Stat_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_LIN_DRS_Stat_DLC); _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->LIN_DRS_BCM_IndFadingTime_ro = (uint8_t) CANDB_DBG_LIN_DRS_BCM_IndFadingTime_ro_toS(_m->LIN_DRS_BCM_IndFadingTime_phys); +#endif // CANDB_DBG_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->LIN_DRS_DLLed1 & (0x01U)) | ((_m->LIN_DRS_DLLed2 & (0x01U)) << 1U) | ((_m->LIN_DRS_DLLed3 & (0x01U)) << 2U) | ((_m->LIN_DRS_DRLed1 & (0x01U)) << 4U) | ((_m->LIN_DRS_DRLed2 & (0x01U)) << 5U) | ((_m->LIN_DRS_DRLed3 & (0x01U)) << 6U) ); + _d[1] |= (uint8_t) ( (_m->LIN_DRS_FPLLed1 & (0x01U)) | ((_m->LIN_DRS_FPLLed2 & (0x01U)) << 1U) | ((_m->LIN_DRS_FPLLed3 & (0x01U)) << 2U) | ((_m->LIN_DRS_FPRLed1 & (0x01U)) << 4U) | ((_m->LIN_DRS_FPRLed2 & (0x01U)) << 5U) | ((_m->LIN_DRS_FPRLed3 & (0x01U)) << 6U) ); + _d[2] |= (uint8_t) ( (_m->LIN_DRS_RLBLed1 & (0x01U)) | ((_m->LIN_DRS_RLBLed2 & (0x01U)) << 1U) | ((_m->LIN_DRS_RLBLed3 & (0x01U)) << 2U) | ((_m->LIN_DRS_RRBLed1 & (0x01U)) << 4U) | ((_m->LIN_DRS_RRBLed2 & (0x01U)) << 5U) | ((_m->LIN_DRS_RRBLed3 & (0x01U)) << 6U) ); + _d[3] |= (uint8_t) ( (_m->LIN_DRS_FCLLed1 & (0x01U)) | ((_m->LIN_DRS_FCLLed2 & (0x01U)) << 1U) | ((_m->LIN_DRS_FCLLed3 & (0x01U)) << 2U) | ((_m->LIN_DRS_FCRLed1 & (0x01U)) << 4U) | ((_m->LIN_DRS_FCRLed2 & (0x01U)) << 5U) | ((_m->LIN_DRS_FCRLed3 & (0x01U)) << 6U) ); + _d[4] |= (uint8_t) ( (_m->LIN_DRS_BCM_IndFadingTime_ro & (0x1FU)) | ((_m->LIN_DRS_BCM_SwIndIntens & (0x01U)) << 5U) ); + + *_len = (uint8_t) dbg_LIN_DRS_Stat_DLC; + *_ide = (uint8_t) dbg_LIN_DRS_Stat_IDE; + return dbg_LIN_DRS_Stat_CANID; +} + +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Auto_AF_candb_dbg(dbg_Auto_AF_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->dbg_Auto_AF_MultMsg_Idx = (uint8_t) ( (_d[0] & (0x03U)) ); + _m->dbg_Auto_AF_Correct_FL = (int16_t) __ext_sig__(( ((_d[1] & (0xFFU)) << 4U) | ((_d[0] >> 4U) & (0x0FU)) ), 12); + _m->dbg_Auto_AF_Correct_FR = (int16_t) __ext_sig__(( ((_d[1] & (0xFFU)) << 4U) | ((_d[0] >> 4U) & (0x0FU)) ), 12); + _m->dbg_Auto_AF_Correct_RL = (int16_t) __ext_sig__(( ((_d[1] & (0xFFU)) << 4U) | ((_d[0] >> 4U) & (0x0FU)) ), 12); + _m->dbg_Auto_AF_Correct_RR = (int16_t) __ext_sig__(( ((_d[1] & (0xFFU)) << 4U) | ((_d[0] >> 4U) & (0x0FU)) ), 12); + _m->dbg_Auto_AF_Vtg_RL = (int16_t) __ext_sig__(( ((_d[3] & (0x0FU)) << 8U) | (_d[2] & (0xFFU)) ), 12); + _m->dbg_Auto_AF_Vtg_FL = (int16_t) __ext_sig__(( ((_d[3] & (0x0FU)) << 8U) | (_d[2] & (0xFFU)) ), 12); + _m->dbg_Auto_AF_Vtg_FR = (int16_t) __ext_sig__(( ((_d[3] & (0x0FU)) << 8U) | (_d[2] & (0xFFU)) ), 12); + _m->dbg_Auto_AF_Vtg_RR = (int16_t) __ext_sig__(( ((_d[3] & (0x0FU)) << 8U) | (_d[2] & (0xFFU)) ), 12); + _m->dbg_Auto_AF_Incar_RL = (int16_t) __ext_sig__(( ((_d[4] & (0xFFU)) << 4U) | ((_d[3] >> 4U) & (0x0FU)) ), 12); + _m->dbg_Auto_AF_Incar_FR = (int16_t) __ext_sig__(( ((_d[4] & (0xFFU)) << 4U) | ((_d[3] >> 4U) & (0x0FU)) ), 12); + _m->dbg_Auto_AF_Incar_RR = (int16_t) __ext_sig__(( ((_d[4] & (0xFFU)) << 4U) | ((_d[3] >> 4U) & (0x0FU)) ), 12); + _m->dbg_Auto_AF_Incar_FL = (int16_t) __ext_sig__(( ((_d[4] & (0xFFU)) << 4U) | ((_d[3] >> 4U) & (0x0FU)) ), 12); + _m->dbg_Auto_AF_Amb_RL = (int16_t) __ext_sig__(( ((_d[6] & (0x0FU)) << 8U) | (_d[5] & (0xFFU)) ), 12); + _m->dbg_Auto_AF_Amb_FR = (int16_t) __ext_sig__(( ((_d[6] & (0x0FU)) << 8U) | (_d[5] & (0xFFU)) ), 12); + _m->dbg_Auto_AF_Sun_RR = (int16_t) __ext_sig__(( ((_d[6] & (0x0FU)) << 8U) | (_d[5] & (0xFFU)) ), 12); + _m->dbg_Auto_AF_Amb_FL = (int16_t) __ext_sig__(( ((_d[6] & (0x0FU)) << 8U) | (_d[5] & (0xFFU)) ), 12); + _m->dbg_Auto_AF_Sun_FR = (int16_t) __ext_sig__(( ((_d[7] & (0xFFU)) << 4U) | ((_d[6] >> 4U) & (0x0FU)) ), 12); + _m->dbg_Auto_AF_Sun_RL = (int16_t) __ext_sig__(( ((_d[7] & (0xFFU)) << 4U) | ((_d[6] >> 4U) & (0x0FU)) ), 12); + _m->dbg_Auto_AF_Amb_RR = (int16_t) __ext_sig__(( ((_d[7] & (0xFFU)) << 4U) | ((_d[6] >> 4U) & (0x0FU)) ), 12); + _m->dbg_Auto_AF_Sun_FL = (int16_t) __ext_sig__(( ((_d[7] & (0xFFU)) << 4U) | ((_d[6] >> 4U) & (0x0FU)) ), 12); + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < dbg_Auto_AF_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_dbg_Auto_AF_candb_dbg(&_m->mon1, dbg_Auto_AF_CANID); +#endif // CANDB_DBG_USE_DIAG_MONITORS + + return dbg_Auto_AF_CANID; +} + +#ifdef CANDB_DBG_USE_CANSTRUCT + +uint32_t Pack_dbg_Auto_AF_candb_dbg(dbg_Auto_AF_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Auto_AF_DLC); cframe->Data[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->dbg_Auto_AF_MultMsg_Idx & (0x03U)) | ((_m->dbg_Auto_AF_Correct_FL & (0x0FU)) << 4U) | ((_m->dbg_Auto_AF_Correct_FR & (0x0FU)) << 4U) | ((_m->dbg_Auto_AF_Correct_RL & (0x0FU)) << 4U) | ((_m->dbg_Auto_AF_Correct_RR & (0x0FU)) << 4U) ); + cframe->Data[1] |= (uint8_t) ( ((_m->dbg_Auto_AF_Correct_FL >> 4U) & (0xFFU)) | ((_m->dbg_Auto_AF_Correct_FR >> 4U) & (0xFFU)) | ((_m->dbg_Auto_AF_Correct_RL >> 4U) & (0xFFU)) | ((_m->dbg_Auto_AF_Correct_RR >> 4U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->dbg_Auto_AF_Vtg_RL & (0xFFU)) | (_m->dbg_Auto_AF_Vtg_FL & (0xFFU)) | (_m->dbg_Auto_AF_Vtg_FR & (0xFFU)) | (_m->dbg_Auto_AF_Vtg_RR & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->dbg_Auto_AF_Vtg_RL >> 8U) & (0x0FU)) | ((_m->dbg_Auto_AF_Vtg_FL >> 8U) & (0x0FU)) | ((_m->dbg_Auto_AF_Vtg_FR >> 8U) & (0x0FU)) | ((_m->dbg_Auto_AF_Vtg_RR >> 8U) & (0x0FU)) | ((_m->dbg_Auto_AF_Incar_RL & (0x0FU)) << 4U) | ((_m->dbg_Auto_AF_Incar_FR & (0x0FU)) << 4U) | ((_m->dbg_Auto_AF_Incar_RR & (0x0FU)) << 4U) | ((_m->dbg_Auto_AF_Incar_FL & (0x0FU)) << 4U) ); + cframe->Data[4] |= (uint8_t) ( ((_m->dbg_Auto_AF_Incar_RL >> 4U) & (0xFFU)) | ((_m->dbg_Auto_AF_Incar_FR >> 4U) & (0xFFU)) | ((_m->dbg_Auto_AF_Incar_RR >> 4U) & (0xFFU)) | ((_m->dbg_Auto_AF_Incar_FL >> 4U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->dbg_Auto_AF_Amb_RL & (0xFFU)) | (_m->dbg_Auto_AF_Amb_FR & (0xFFU)) | (_m->dbg_Auto_AF_Sun_RR & (0xFFU)) | (_m->dbg_Auto_AF_Amb_FL & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->dbg_Auto_AF_Amb_RL >> 8U) & (0x0FU)) | ((_m->dbg_Auto_AF_Amb_FR >> 8U) & (0x0FU)) | ((_m->dbg_Auto_AF_Sun_RR >> 8U) & (0x0FU)) | ((_m->dbg_Auto_AF_Amb_FL >> 8U) & (0x0FU)) | ((_m->dbg_Auto_AF_Sun_FR & (0x0FU)) << 4U) | ((_m->dbg_Auto_AF_Sun_RL & (0x0FU)) << 4U) | ((_m->dbg_Auto_AF_Amb_RR & (0x0FU)) << 4U) | ((_m->dbg_Auto_AF_Sun_FL & (0x0FU)) << 4U) ); + cframe->Data[7] |= (uint8_t) ( ((_m->dbg_Auto_AF_Sun_FR >> 4U) & (0xFFU)) | ((_m->dbg_Auto_AF_Sun_RL >> 4U) & (0xFFU)) | ((_m->dbg_Auto_AF_Amb_RR >> 4U) & (0xFFU)) | ((_m->dbg_Auto_AF_Sun_FL >> 4U) & (0xFFU)) ); + + cframe->MsgId = (uint32_t) dbg_Auto_AF_CANID; + cframe->DLC = (uint8_t) dbg_Auto_AF_DLC; + cframe->IDE = (uint8_t) dbg_Auto_AF_IDE; + return dbg_Auto_AF_CANID; +} + +#else + +uint32_t Pack_dbg_Auto_AF_candb_dbg(dbg_Auto_AF_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Auto_AF_DLC); _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->dbg_Auto_AF_MultMsg_Idx & (0x03U)) | ((_m->dbg_Auto_AF_Correct_FL & (0x0FU)) << 4U) | ((_m->dbg_Auto_AF_Correct_FR & (0x0FU)) << 4U) | ((_m->dbg_Auto_AF_Correct_RL & (0x0FU)) << 4U) | ((_m->dbg_Auto_AF_Correct_RR & (0x0FU)) << 4U) ); + _d[1] |= (uint8_t) ( ((_m->dbg_Auto_AF_Correct_FL >> 4U) & (0xFFU)) | ((_m->dbg_Auto_AF_Correct_FR >> 4U) & (0xFFU)) | ((_m->dbg_Auto_AF_Correct_RL >> 4U) & (0xFFU)) | ((_m->dbg_Auto_AF_Correct_RR >> 4U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->dbg_Auto_AF_Vtg_RL & (0xFFU)) | (_m->dbg_Auto_AF_Vtg_FL & (0xFFU)) | (_m->dbg_Auto_AF_Vtg_FR & (0xFFU)) | (_m->dbg_Auto_AF_Vtg_RR & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->dbg_Auto_AF_Vtg_RL >> 8U) & (0x0FU)) | ((_m->dbg_Auto_AF_Vtg_FL >> 8U) & (0x0FU)) | ((_m->dbg_Auto_AF_Vtg_FR >> 8U) & (0x0FU)) | ((_m->dbg_Auto_AF_Vtg_RR >> 8U) & (0x0FU)) | ((_m->dbg_Auto_AF_Incar_RL & (0x0FU)) << 4U) | ((_m->dbg_Auto_AF_Incar_FR & (0x0FU)) << 4U) | ((_m->dbg_Auto_AF_Incar_RR & (0x0FU)) << 4U) | ((_m->dbg_Auto_AF_Incar_FL & (0x0FU)) << 4U) ); + _d[4] |= (uint8_t) ( ((_m->dbg_Auto_AF_Incar_RL >> 4U) & (0xFFU)) | ((_m->dbg_Auto_AF_Incar_FR >> 4U) & (0xFFU)) | ((_m->dbg_Auto_AF_Incar_RR >> 4U) & (0xFFU)) | ((_m->dbg_Auto_AF_Incar_FL >> 4U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->dbg_Auto_AF_Amb_RL & (0xFFU)) | (_m->dbg_Auto_AF_Amb_FR & (0xFFU)) | (_m->dbg_Auto_AF_Sun_RR & (0xFFU)) | (_m->dbg_Auto_AF_Amb_FL & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->dbg_Auto_AF_Amb_RL >> 8U) & (0x0FU)) | ((_m->dbg_Auto_AF_Amb_FR >> 8U) & (0x0FU)) | ((_m->dbg_Auto_AF_Sun_RR >> 8U) & (0x0FU)) | ((_m->dbg_Auto_AF_Amb_FL >> 8U) & (0x0FU)) | ((_m->dbg_Auto_AF_Sun_FR & (0x0FU)) << 4U) | ((_m->dbg_Auto_AF_Sun_RL & (0x0FU)) << 4U) | ((_m->dbg_Auto_AF_Amb_RR & (0x0FU)) << 4U) | ((_m->dbg_Auto_AF_Sun_FL & (0x0FU)) << 4U) ); + _d[7] |= (uint8_t) ( ((_m->dbg_Auto_AF_Sun_FR >> 4U) & (0xFFU)) | ((_m->dbg_Auto_AF_Sun_RL >> 4U) & (0xFFU)) | ((_m->dbg_Auto_AF_Amb_RR >> 4U) & (0xFFU)) | ((_m->dbg_Auto_AF_Sun_FL >> 4U) & (0xFFU)) ); + + *_len = (uint8_t) dbg_Auto_AF_DLC; + *_ide = (uint8_t) dbg_Auto_AF_IDE; + return dbg_Auto_AF_CANID; +} + +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Auto_Duct_candb_dbg(dbg_Auto_Duct_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->dbg_Auto_Duct_MultMsg_Idx = (uint8_t) ( (_d[0] & (0x0FU)) ); + _m->dbg_Auto_Duct_Tgt_FL_Upper_ro = (int16_t) __ext_sig__(( ((_d[1] & (0xFFU)) << 4U) | ((_d[0] >> 4U) & (0x0FU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Tgt_FL_Upper_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Duct_Tgt_FL_Upper_ro_fromS(_m->dbg_Auto_Duct_Tgt_FL_Upper_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Duct_Tg_Incar_FL_Upper_ro = (int16_t) __ext_sig__(( ((_d[1] & (0x3FU)) << 4U) | ((_d[0] >> 4U) & (0x0FU)) ), 10); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Tg_Incar_FL_Upper_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Duct_Tg_Incar_FL_Upper_ro_fromS(_m->dbg_Auto_Duct_Tg_Incar_FL_Upper_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Duct_Tgt_RR_ro = (int16_t) __ext_sig__(( ((_d[1] & (0xFFU)) << 4U) | ((_d[0] >> 4U) & (0x0FU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Tgt_RR_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Duct_Tgt_RR_ro_fromS(_m->dbg_Auto_Duct_Tgt_RR_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Duct_Tgt_RL_ro = (int16_t) __ext_sig__(( ((_d[1] & (0xFFU)) << 4U) | ((_d[0] >> 4U) & (0x0FU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Tgt_RL_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Duct_Tgt_RL_ro_fromS(_m->dbg_Auto_Duct_Tgt_RL_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Duct_Tgt_FR_Upper_ro = (int16_t) __ext_sig__(( ((_d[1] & (0xFFU)) << 4U) | ((_d[0] >> 4U) & (0x0FU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Tgt_FR_Upper_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Duct_Tgt_FR_Upper_ro_fromS(_m->dbg_Auto_Duct_Tgt_FR_Upper_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Duct_Tgt_FR_Lower_ro = (int16_t) __ext_sig__(( ((_d[1] & (0xFFU)) << 4U) | ((_d[0] >> 4U) & (0x0FU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Tgt_FR_Lower_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Duct_Tgt_FR_Lower_ro_fromS(_m->dbg_Auto_Duct_Tgt_FR_Lower_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Duct_Tgt_FL_Lower_ro = (int16_t) __ext_sig__(( ((_d[1] & (0xFFU)) << 4U) | ((_d[0] >> 4U) & (0x0FU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Tgt_FL_Lower_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Duct_Tgt_FL_Lower_ro_fromS(_m->dbg_Auto_Duct_Tgt_FL_Lower_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Duct_Tg_Incar_FR_Upper_ro = (int16_t) __ext_sig__(( ((_d[2] & (0xFFU)) << 2U) | ((_d[1] >> 6U) & (0x03U)) ), 10); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Tg_Incar_FR_Upper_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Duct_Tg_Incar_FR_Upper_ro_fromS(_m->dbg_Auto_Duct_Tg_Incar_FR_Upper_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Duct_Tg_FL_Upper_ro = (int16_t) __ext_sig__(( ((_d[3] & (0x0FU)) << 8U) | (_d[2] & (0xFFU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Tg_FL_Upper_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Duct_Tg_FL_Upper_ro_fromS(_m->dbg_Auto_Duct_Tg_FL_Upper_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Duct_Tg_FL_Lower_ro = (int16_t) __ext_sig__(( ((_d[3] & (0x0FU)) << 8U) | (_d[2] & (0xFFU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Tg_FL_Lower_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Duct_Tg_FL_Lower_ro_fromS(_m->dbg_Auto_Duct_Tg_FL_Lower_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Duct_Tg_FR_Lower_ro = (int16_t) __ext_sig__(( ((_d[3] & (0x0FU)) << 8U) | (_d[2] & (0xFFU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Tg_FR_Lower_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Duct_Tg_FR_Lower_ro_fromS(_m->dbg_Auto_Duct_Tg_FR_Lower_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Duct_Tg_FR_Upper_ro = (int16_t) __ext_sig__(( ((_d[3] & (0x0FU)) << 8U) | (_d[2] & (0xFFU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Tg_FR_Upper_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Duct_Tg_FR_Upper_ro_fromS(_m->dbg_Auto_Duct_Tg_FR_Upper_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Duct_Tg_RL_ro = (int16_t) __ext_sig__(( ((_d[3] & (0x0FU)) << 8U) | (_d[2] & (0xFFU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Tg_RL_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Duct_Tg_RL_ro_fromS(_m->dbg_Auto_Duct_Tg_RL_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Duct_Tg_RR_ro = (int16_t) __ext_sig__(( ((_d[3] & (0x0FU)) << 8U) | (_d[2] & (0xFFU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Tg_RR_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Duct_Tg_RR_ro_fromS(_m->dbg_Auto_Duct_Tg_RR_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Duct_Tg_Incar_FL_Lower_ro = (int16_t) __ext_sig__(( ((_d[4] & (0x03U)) << 8U) | (_d[3] & (0xFFU)) ), 10); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Tg_Incar_FL_Lower_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Duct_Tg_Incar_FL_Lower_ro_fromS(_m->dbg_Auto_Duct_Tg_Incar_FL_Lower_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Duct_Incar_FL_Lower_ro = (int16_t) __ext_sig__(( ((_d[4] & (0xFFU)) << 4U) | ((_d[3] >> 4U) & (0x0FU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Incar_FL_Lower_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Duct_Incar_FL_Lower_ro_fromS(_m->dbg_Auto_Duct_Incar_FL_Lower_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Duct_Incar_RR_ro = (int16_t) __ext_sig__(( ((_d[4] & (0xFFU)) << 4U) | ((_d[3] >> 4U) & (0x0FU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Incar_RR_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Duct_Incar_RR_ro_fromS(_m->dbg_Auto_Duct_Incar_RR_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Duct_Incar_RL_ro = (int16_t) __ext_sig__(( ((_d[4] & (0xFFU)) << 4U) | ((_d[3] >> 4U) & (0x0FU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Incar_RL_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Duct_Incar_RL_ro_fromS(_m->dbg_Auto_Duct_Incar_RL_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Duct_Incar_FR_Upper_ro = (int16_t) __ext_sig__(( ((_d[4] & (0xFFU)) << 4U) | ((_d[3] >> 4U) & (0x0FU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Incar_FR_Upper_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Duct_Incar_FR_Upper_ro_fromS(_m->dbg_Auto_Duct_Incar_FR_Upper_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Duct_Incar_FR_Lower_ro = (int16_t) __ext_sig__(( ((_d[4] & (0xFFU)) << 4U) | ((_d[3] >> 4U) & (0x0FU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Incar_FR_Lower_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Duct_Incar_FR_Lower_ro_fromS(_m->dbg_Auto_Duct_Incar_FR_Lower_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Duct_Incar_FL_Upper_ro = (int16_t) __ext_sig__(( ((_d[4] & (0xFFU)) << 4U) | ((_d[3] >> 4U) & (0x0FU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Incar_FL_Upper_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Duct_Incar_FL_Upper_ro_fromS(_m->dbg_Auto_Duct_Incar_FL_Upper_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Duct_Tg_Incar_FR_Lower_ro = (int16_t) __ext_sig__(( ((_d[5] & (0x0FU)) << 6U) | ((_d[4] >> 2U) & (0x3FU)) ), 10); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Tg_Incar_FR_Lower_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Duct_Tg_Incar_FR_Lower_ro_fromS(_m->dbg_Auto_Duct_Tg_Incar_FR_Lower_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Duct_Amb_RL_ro = (int16_t) __ext_sig__(( ((_d[6] & (0x0FU)) << 8U) | (_d[5] & (0xFFU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Amb_RL_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Duct_Amb_RL_ro_fromS(_m->dbg_Auto_Duct_Amb_RL_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Duct_Amb_FR_Upper_ro = (int16_t) __ext_sig__(( ((_d[6] & (0x0FU)) << 8U) | (_d[5] & (0xFFU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Amb_FR_Upper_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Duct_Amb_FR_Upper_ro_fromS(_m->dbg_Auto_Duct_Amb_FR_Upper_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Duct_Amb_FR_Lower_ro = (int16_t) __ext_sig__(( ((_d[6] & (0x0FU)) << 8U) | (_d[5] & (0xFFU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Amb_FR_Lower_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Duct_Amb_FR_Lower_ro_fromS(_m->dbg_Auto_Duct_Amb_FR_Lower_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Duct_Amb_RR_ro = (int16_t) __ext_sig__(( ((_d[6] & (0x0FU)) << 8U) | (_d[5] & (0xFFU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Amb_RR_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Duct_Amb_RR_ro_fromS(_m->dbg_Auto_Duct_Amb_RR_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Duct_Amb_FL_Lower_ro = (int16_t) __ext_sig__(( ((_d[6] & (0x0FU)) << 8U) | (_d[5] & (0xFFU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Amb_FL_Lower_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Duct_Amb_FL_Lower_ro_fromS(_m->dbg_Auto_Duct_Amb_FL_Lower_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Duct_Amb_FL_Upper_ro = (int16_t) __ext_sig__(( ((_d[6] & (0x0FU)) << 8U) | (_d[5] & (0xFFU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Amb_FL_Upper_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Duct_Amb_FL_Upper_ro_fromS(_m->dbg_Auto_Duct_Amb_FL_Upper_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Duct_Tg_Incar_RL_ro = (int16_t) __ext_sig__(( ((_d[6] & (0x3FU)) << 4U) | ((_d[5] >> 4U) & (0x0FU)) ), 10); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Tg_Incar_RL_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Duct_Tg_Incar_RL_ro_fromS(_m->dbg_Auto_Duct_Tg_Incar_RL_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Duct_Sun_FL_Lower_ro = (int16_t) __ext_sig__(( ((_d[7] & (0xFFU)) << 4U) | ((_d[6] >> 4U) & (0x0FU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Sun_FL_Lower_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Duct_Sun_FL_Lower_ro_fromS(_m->dbg_Auto_Duct_Sun_FL_Lower_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Duct_Sun_FR_Lower_ro = (int16_t) __ext_sig__(( ((_d[7] & (0xFFU)) << 4U) | ((_d[6] >> 4U) & (0x0FU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Sun_FR_Lower_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Duct_Sun_FR_Lower_ro_fromS(_m->dbg_Auto_Duct_Sun_FR_Lower_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Duct_Sun_FR_Upper_ro = (int16_t) __ext_sig__(( ((_d[7] & (0xFFU)) << 4U) | ((_d[6] >> 4U) & (0x0FU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Sun_FR_Upper_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Duct_Sun_FR_Upper_ro_fromS(_m->dbg_Auto_Duct_Sun_FR_Upper_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Duct_Sun_RL_ro = (int16_t) __ext_sig__(( ((_d[7] & (0xFFU)) << 4U) | ((_d[6] >> 4U) & (0x0FU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Sun_RL_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Duct_Sun_RL_ro_fromS(_m->dbg_Auto_Duct_Sun_RL_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Duct_Sun_FL_Upper_ro = (int16_t) __ext_sig__(( ((_d[7] & (0xFFU)) << 4U) | ((_d[6] >> 4U) & (0x0FU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Sun_FL_Upper_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Duct_Sun_FL_Upper_ro_fromS(_m->dbg_Auto_Duct_Sun_FL_Upper_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Duct_Sun_RR_ro = (int16_t) __ext_sig__(( ((_d[7] & (0xFFU)) << 4U) | ((_d[6] >> 4U) & (0x0FU)) ), 12); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Sun_RR_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Duct_Sun_RR_ro_fromS(_m->dbg_Auto_Duct_Sun_RR_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Duct_Tg_Incar_RR_ro = (int16_t) __ext_sig__(( ((_d[7] & (0xFFU)) << 2U) | ((_d[6] >> 6U) & (0x03U)) ), 10); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Tg_Incar_RR_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Duct_Tg_Incar_RR_ro_fromS(_m->dbg_Auto_Duct_Tg_Incar_RR_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < dbg_Auto_Duct_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_dbg_Auto_Duct_candb_dbg(&_m->mon1, dbg_Auto_Duct_CANID); +#endif // CANDB_DBG_USE_DIAG_MONITORS + + return dbg_Auto_Duct_CANID; +} + +#ifdef CANDB_DBG_USE_CANSTRUCT + +uint32_t Pack_dbg_Auto_Duct_candb_dbg(dbg_Auto_Duct_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Auto_Duct_DLC); cframe->Data[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Tgt_FL_Upper_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Tgt_FL_Upper_ro_toS(_m->dbg_Auto_Duct_Tgt_FL_Upper_phys); + _m->dbg_Auto_Duct_Tg_Incar_FL_Upper_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Tg_Incar_FL_Upper_ro_toS(_m->dbg_Auto_Duct_Tg_Incar_FL_Upper_phys); + _m->dbg_Auto_Duct_Tgt_RR_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Tgt_RR_ro_toS(_m->dbg_Auto_Duct_Tgt_RR_phys); + _m->dbg_Auto_Duct_Tgt_RL_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Tgt_RL_ro_toS(_m->dbg_Auto_Duct_Tgt_RL_phys); + _m->dbg_Auto_Duct_Tgt_FR_Upper_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Tgt_FR_Upper_ro_toS(_m->dbg_Auto_Duct_Tgt_FR_Upper_phys); + _m->dbg_Auto_Duct_Tgt_FR_Lower_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Tgt_FR_Lower_ro_toS(_m->dbg_Auto_Duct_Tgt_FR_Lower_phys); + _m->dbg_Auto_Duct_Tgt_FL_Lower_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Tgt_FL_Lower_ro_toS(_m->dbg_Auto_Duct_Tgt_FL_Lower_phys); + _m->dbg_Auto_Duct_Tg_Incar_FR_Upper_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Tg_Incar_FR_Upper_ro_toS(_m->dbg_Auto_Duct_Tg_Incar_FR_Upper_phys); + _m->dbg_Auto_Duct_Tg_FL_Upper_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Tg_FL_Upper_ro_toS(_m->dbg_Auto_Duct_Tg_FL_Upper_phys); + _m->dbg_Auto_Duct_Tg_FL_Lower_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Tg_FL_Lower_ro_toS(_m->dbg_Auto_Duct_Tg_FL_Lower_phys); + _m->dbg_Auto_Duct_Tg_FR_Lower_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Tg_FR_Lower_ro_toS(_m->dbg_Auto_Duct_Tg_FR_Lower_phys); + _m->dbg_Auto_Duct_Tg_FR_Upper_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Tg_FR_Upper_ro_toS(_m->dbg_Auto_Duct_Tg_FR_Upper_phys); + _m->dbg_Auto_Duct_Tg_RL_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Tg_RL_ro_toS(_m->dbg_Auto_Duct_Tg_RL_phys); + _m->dbg_Auto_Duct_Tg_RR_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Tg_RR_ro_toS(_m->dbg_Auto_Duct_Tg_RR_phys); + _m->dbg_Auto_Duct_Tg_Incar_FL_Lower_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Tg_Incar_FL_Lower_ro_toS(_m->dbg_Auto_Duct_Tg_Incar_FL_Lower_phys); + _m->dbg_Auto_Duct_Incar_FL_Lower_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Incar_FL_Lower_ro_toS(_m->dbg_Auto_Duct_Incar_FL_Lower_phys); + _m->dbg_Auto_Duct_Incar_RR_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Incar_RR_ro_toS(_m->dbg_Auto_Duct_Incar_RR_phys); + _m->dbg_Auto_Duct_Incar_RL_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Incar_RL_ro_toS(_m->dbg_Auto_Duct_Incar_RL_phys); + _m->dbg_Auto_Duct_Incar_FR_Upper_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Incar_FR_Upper_ro_toS(_m->dbg_Auto_Duct_Incar_FR_Upper_phys); + _m->dbg_Auto_Duct_Incar_FR_Lower_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Incar_FR_Lower_ro_toS(_m->dbg_Auto_Duct_Incar_FR_Lower_phys); + _m->dbg_Auto_Duct_Incar_FL_Upper_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Incar_FL_Upper_ro_toS(_m->dbg_Auto_Duct_Incar_FL_Upper_phys); + _m->dbg_Auto_Duct_Tg_Incar_FR_Lower_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Tg_Incar_FR_Lower_ro_toS(_m->dbg_Auto_Duct_Tg_Incar_FR_Lower_phys); + _m->dbg_Auto_Duct_Amb_RL_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Amb_RL_ro_toS(_m->dbg_Auto_Duct_Amb_RL_phys); + _m->dbg_Auto_Duct_Amb_FR_Upper_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Amb_FR_Upper_ro_toS(_m->dbg_Auto_Duct_Amb_FR_Upper_phys); + _m->dbg_Auto_Duct_Amb_FR_Lower_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Amb_FR_Lower_ro_toS(_m->dbg_Auto_Duct_Amb_FR_Lower_phys); + _m->dbg_Auto_Duct_Amb_RR_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Amb_RR_ro_toS(_m->dbg_Auto_Duct_Amb_RR_phys); + _m->dbg_Auto_Duct_Amb_FL_Lower_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Amb_FL_Lower_ro_toS(_m->dbg_Auto_Duct_Amb_FL_Lower_phys); + _m->dbg_Auto_Duct_Amb_FL_Upper_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Amb_FL_Upper_ro_toS(_m->dbg_Auto_Duct_Amb_FL_Upper_phys); + _m->dbg_Auto_Duct_Tg_Incar_RL_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Tg_Incar_RL_ro_toS(_m->dbg_Auto_Duct_Tg_Incar_RL_phys); + _m->dbg_Auto_Duct_Sun_FL_Lower_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Sun_FL_Lower_ro_toS(_m->dbg_Auto_Duct_Sun_FL_Lower_phys); + _m->dbg_Auto_Duct_Sun_FR_Lower_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Sun_FR_Lower_ro_toS(_m->dbg_Auto_Duct_Sun_FR_Lower_phys); + _m->dbg_Auto_Duct_Sun_FR_Upper_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Sun_FR_Upper_ro_toS(_m->dbg_Auto_Duct_Sun_FR_Upper_phys); + _m->dbg_Auto_Duct_Sun_RL_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Sun_RL_ro_toS(_m->dbg_Auto_Duct_Sun_RL_phys); + _m->dbg_Auto_Duct_Sun_FL_Upper_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Sun_FL_Upper_ro_toS(_m->dbg_Auto_Duct_Sun_FL_Upper_phys); + _m->dbg_Auto_Duct_Sun_RR_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Sun_RR_ro_toS(_m->dbg_Auto_Duct_Sun_RR_phys); + _m->dbg_Auto_Duct_Tg_Incar_RR_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Tg_Incar_RR_ro_toS(_m->dbg_Auto_Duct_Tg_Incar_RR_phys); +#endif // CANDB_DBG_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->dbg_Auto_Duct_MultMsg_Idx & (0x0FU)) | ((_m->dbg_Auto_Duct_Tgt_FL_Upper_ro & (0x0FU)) << 4U) | ((_m->dbg_Auto_Duct_Tg_Incar_FL_Upper_ro & (0x0FU)) << 4U) | ((_m->dbg_Auto_Duct_Tgt_RR_ro & (0x0FU)) << 4U) | ((_m->dbg_Auto_Duct_Tgt_RL_ro & (0x0FU)) << 4U) | ((_m->dbg_Auto_Duct_Tgt_FR_Upper_ro & (0x0FU)) << 4U) | ((_m->dbg_Auto_Duct_Tgt_FR_Lower_ro & (0x0FU)) << 4U) | ((_m->dbg_Auto_Duct_Tgt_FL_Lower_ro & (0x0FU)) << 4U) ); + cframe->Data[1] |= (uint8_t) ( ((_m->dbg_Auto_Duct_Tgt_FL_Upper_ro >> 4U) & (0xFFU)) | ((_m->dbg_Auto_Duct_Tg_Incar_FL_Upper_ro >> 4U) & (0x3FU)) | ((_m->dbg_Auto_Duct_Tgt_RR_ro >> 4U) & (0xFFU)) | ((_m->dbg_Auto_Duct_Tgt_RL_ro >> 4U) & (0xFFU)) | ((_m->dbg_Auto_Duct_Tgt_FR_Upper_ro >> 4U) & (0xFFU)) | ((_m->dbg_Auto_Duct_Tgt_FR_Lower_ro >> 4U) & (0xFFU)) | ((_m->dbg_Auto_Duct_Tgt_FL_Lower_ro >> 4U) & (0xFFU)) | ((_m->dbg_Auto_Duct_Tg_Incar_FR_Upper_ro & (0x03U)) << 6U) ); + cframe->Data[2] |= (uint8_t) ( ((_m->dbg_Auto_Duct_Tg_Incar_FR_Upper_ro >> 2U) & (0xFFU)) | (_m->dbg_Auto_Duct_Tg_FL_Upper_ro & (0xFFU)) | (_m->dbg_Auto_Duct_Tg_FL_Lower_ro & (0xFFU)) | (_m->dbg_Auto_Duct_Tg_FR_Lower_ro & (0xFFU)) | (_m->dbg_Auto_Duct_Tg_FR_Upper_ro & (0xFFU)) | (_m->dbg_Auto_Duct_Tg_RL_ro & (0xFFU)) | (_m->dbg_Auto_Duct_Tg_RR_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->dbg_Auto_Duct_Tg_FL_Upper_ro >> 8U) & (0x0FU)) | ((_m->dbg_Auto_Duct_Tg_FL_Lower_ro >> 8U) & (0x0FU)) | ((_m->dbg_Auto_Duct_Tg_FR_Lower_ro >> 8U) & (0x0FU)) | ((_m->dbg_Auto_Duct_Tg_FR_Upper_ro >> 8U) & (0x0FU)) | ((_m->dbg_Auto_Duct_Tg_RL_ro >> 8U) & (0x0FU)) | ((_m->dbg_Auto_Duct_Tg_RR_ro >> 8U) & (0x0FU)) | (_m->dbg_Auto_Duct_Tg_Incar_FL_Lower_ro & (0xFFU)) | ((_m->dbg_Auto_Duct_Incar_FL_Lower_ro & (0x0FU)) << 4U) | ((_m->dbg_Auto_Duct_Incar_RR_ro & (0x0FU)) << 4U) | ((_m->dbg_Auto_Duct_Incar_RL_ro & (0x0FU)) << 4U) | ((_m->dbg_Auto_Duct_Incar_FR_Upper_ro & (0x0FU)) << 4U) | ((_m->dbg_Auto_Duct_Incar_FR_Lower_ro & (0x0FU)) << 4U) | ((_m->dbg_Auto_Duct_Incar_FL_Upper_ro & (0x0FU)) << 4U) ); + cframe->Data[4] |= (uint8_t) ( ((_m->dbg_Auto_Duct_Tg_Incar_FL_Lower_ro >> 8U) & (0x03U)) | ((_m->dbg_Auto_Duct_Incar_FL_Lower_ro >> 4U) & (0xFFU)) | ((_m->dbg_Auto_Duct_Incar_RR_ro >> 4U) & (0xFFU)) | ((_m->dbg_Auto_Duct_Incar_RL_ro >> 4U) & (0xFFU)) | ((_m->dbg_Auto_Duct_Incar_FR_Upper_ro >> 4U) & (0xFFU)) | ((_m->dbg_Auto_Duct_Incar_FR_Lower_ro >> 4U) & (0xFFU)) | ((_m->dbg_Auto_Duct_Incar_FL_Upper_ro >> 4U) & (0xFFU)) | ((_m->dbg_Auto_Duct_Tg_Incar_FR_Lower_ro & (0x3FU)) << 2U) ); + cframe->Data[5] |= (uint8_t) ( ((_m->dbg_Auto_Duct_Tg_Incar_FR_Lower_ro >> 6U) & (0x0FU)) | (_m->dbg_Auto_Duct_Amb_RL_ro & (0xFFU)) | (_m->dbg_Auto_Duct_Amb_FR_Upper_ro & (0xFFU)) | (_m->dbg_Auto_Duct_Amb_FR_Lower_ro & (0xFFU)) | (_m->dbg_Auto_Duct_Amb_RR_ro & (0xFFU)) | (_m->dbg_Auto_Duct_Amb_FL_Lower_ro & (0xFFU)) | (_m->dbg_Auto_Duct_Amb_FL_Upper_ro & (0xFFU)) | ((_m->dbg_Auto_Duct_Tg_Incar_RL_ro & (0x0FU)) << 4U) ); + cframe->Data[6] |= (uint8_t) ( ((_m->dbg_Auto_Duct_Amb_RL_ro >> 8U) & (0x0FU)) | ((_m->dbg_Auto_Duct_Amb_FR_Upper_ro >> 8U) & (0x0FU)) | ((_m->dbg_Auto_Duct_Amb_FR_Lower_ro >> 8U) & (0x0FU)) | ((_m->dbg_Auto_Duct_Amb_RR_ro >> 8U) & (0x0FU)) | ((_m->dbg_Auto_Duct_Amb_FL_Lower_ro >> 8U) & (0x0FU)) | ((_m->dbg_Auto_Duct_Amb_FL_Upper_ro >> 8U) & (0x0FU)) | ((_m->dbg_Auto_Duct_Tg_Incar_RL_ro >> 4U) & (0x3FU)) | ((_m->dbg_Auto_Duct_Sun_FL_Lower_ro & (0x0FU)) << 4U) | ((_m->dbg_Auto_Duct_Sun_FR_Lower_ro & (0x0FU)) << 4U) | ((_m->dbg_Auto_Duct_Sun_FR_Upper_ro & (0x0FU)) << 4U) | ((_m->dbg_Auto_Duct_Sun_RL_ro & (0x0FU)) << 4U) | ((_m->dbg_Auto_Duct_Sun_FL_Upper_ro & (0x0FU)) << 4U) | ((_m->dbg_Auto_Duct_Sun_RR_ro & (0x0FU)) << 4U) | ((_m->dbg_Auto_Duct_Tg_Incar_RR_ro & (0x03U)) << 6U) ); + cframe->Data[7] |= (uint8_t) ( ((_m->dbg_Auto_Duct_Sun_FL_Lower_ro >> 4U) & (0xFFU)) | ((_m->dbg_Auto_Duct_Sun_FR_Lower_ro >> 4U) & (0xFFU)) | ((_m->dbg_Auto_Duct_Sun_FR_Upper_ro >> 4U) & (0xFFU)) | ((_m->dbg_Auto_Duct_Sun_RL_ro >> 4U) & (0xFFU)) | ((_m->dbg_Auto_Duct_Sun_FL_Upper_ro >> 4U) & (0xFFU)) | ((_m->dbg_Auto_Duct_Sun_RR_ro >> 4U) & (0xFFU)) | ((_m->dbg_Auto_Duct_Tg_Incar_RR_ro >> 2U) & (0xFFU)) ); + + cframe->MsgId = (uint32_t) dbg_Auto_Duct_CANID; + cframe->DLC = (uint8_t) dbg_Auto_Duct_DLC; + cframe->IDE = (uint8_t) dbg_Auto_Duct_IDE; + return dbg_Auto_Duct_CANID; +} + +#else + +uint32_t Pack_dbg_Auto_Duct_candb_dbg(dbg_Auto_Duct_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Auto_Duct_DLC); _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Duct_Tgt_FL_Upper_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Tgt_FL_Upper_ro_toS(_m->dbg_Auto_Duct_Tgt_FL_Upper_phys); + _m->dbg_Auto_Duct_Tg_Incar_FL_Upper_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Tg_Incar_FL_Upper_ro_toS(_m->dbg_Auto_Duct_Tg_Incar_FL_Upper_phys); + _m->dbg_Auto_Duct_Tgt_RR_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Tgt_RR_ro_toS(_m->dbg_Auto_Duct_Tgt_RR_phys); + _m->dbg_Auto_Duct_Tgt_RL_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Tgt_RL_ro_toS(_m->dbg_Auto_Duct_Tgt_RL_phys); + _m->dbg_Auto_Duct_Tgt_FR_Upper_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Tgt_FR_Upper_ro_toS(_m->dbg_Auto_Duct_Tgt_FR_Upper_phys); + _m->dbg_Auto_Duct_Tgt_FR_Lower_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Tgt_FR_Lower_ro_toS(_m->dbg_Auto_Duct_Tgt_FR_Lower_phys); + _m->dbg_Auto_Duct_Tgt_FL_Lower_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Tgt_FL_Lower_ro_toS(_m->dbg_Auto_Duct_Tgt_FL_Lower_phys); + _m->dbg_Auto_Duct_Tg_Incar_FR_Upper_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Tg_Incar_FR_Upper_ro_toS(_m->dbg_Auto_Duct_Tg_Incar_FR_Upper_phys); + _m->dbg_Auto_Duct_Tg_FL_Upper_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Tg_FL_Upper_ro_toS(_m->dbg_Auto_Duct_Tg_FL_Upper_phys); + _m->dbg_Auto_Duct_Tg_FL_Lower_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Tg_FL_Lower_ro_toS(_m->dbg_Auto_Duct_Tg_FL_Lower_phys); + _m->dbg_Auto_Duct_Tg_FR_Lower_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Tg_FR_Lower_ro_toS(_m->dbg_Auto_Duct_Tg_FR_Lower_phys); + _m->dbg_Auto_Duct_Tg_FR_Upper_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Tg_FR_Upper_ro_toS(_m->dbg_Auto_Duct_Tg_FR_Upper_phys); + _m->dbg_Auto_Duct_Tg_RL_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Tg_RL_ro_toS(_m->dbg_Auto_Duct_Tg_RL_phys); + _m->dbg_Auto_Duct_Tg_RR_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Tg_RR_ro_toS(_m->dbg_Auto_Duct_Tg_RR_phys); + _m->dbg_Auto_Duct_Tg_Incar_FL_Lower_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Tg_Incar_FL_Lower_ro_toS(_m->dbg_Auto_Duct_Tg_Incar_FL_Lower_phys); + _m->dbg_Auto_Duct_Incar_FL_Lower_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Incar_FL_Lower_ro_toS(_m->dbg_Auto_Duct_Incar_FL_Lower_phys); + _m->dbg_Auto_Duct_Incar_RR_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Incar_RR_ro_toS(_m->dbg_Auto_Duct_Incar_RR_phys); + _m->dbg_Auto_Duct_Incar_RL_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Incar_RL_ro_toS(_m->dbg_Auto_Duct_Incar_RL_phys); + _m->dbg_Auto_Duct_Incar_FR_Upper_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Incar_FR_Upper_ro_toS(_m->dbg_Auto_Duct_Incar_FR_Upper_phys); + _m->dbg_Auto_Duct_Incar_FR_Lower_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Incar_FR_Lower_ro_toS(_m->dbg_Auto_Duct_Incar_FR_Lower_phys); + _m->dbg_Auto_Duct_Incar_FL_Upper_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Incar_FL_Upper_ro_toS(_m->dbg_Auto_Duct_Incar_FL_Upper_phys); + _m->dbg_Auto_Duct_Tg_Incar_FR_Lower_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Tg_Incar_FR_Lower_ro_toS(_m->dbg_Auto_Duct_Tg_Incar_FR_Lower_phys); + _m->dbg_Auto_Duct_Amb_RL_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Amb_RL_ro_toS(_m->dbg_Auto_Duct_Amb_RL_phys); + _m->dbg_Auto_Duct_Amb_FR_Upper_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Amb_FR_Upper_ro_toS(_m->dbg_Auto_Duct_Amb_FR_Upper_phys); + _m->dbg_Auto_Duct_Amb_FR_Lower_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Amb_FR_Lower_ro_toS(_m->dbg_Auto_Duct_Amb_FR_Lower_phys); + _m->dbg_Auto_Duct_Amb_RR_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Amb_RR_ro_toS(_m->dbg_Auto_Duct_Amb_RR_phys); + _m->dbg_Auto_Duct_Amb_FL_Lower_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Amb_FL_Lower_ro_toS(_m->dbg_Auto_Duct_Amb_FL_Lower_phys); + _m->dbg_Auto_Duct_Amb_FL_Upper_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Amb_FL_Upper_ro_toS(_m->dbg_Auto_Duct_Amb_FL_Upper_phys); + _m->dbg_Auto_Duct_Tg_Incar_RL_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Tg_Incar_RL_ro_toS(_m->dbg_Auto_Duct_Tg_Incar_RL_phys); + _m->dbg_Auto_Duct_Sun_FL_Lower_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Sun_FL_Lower_ro_toS(_m->dbg_Auto_Duct_Sun_FL_Lower_phys); + _m->dbg_Auto_Duct_Sun_FR_Lower_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Sun_FR_Lower_ro_toS(_m->dbg_Auto_Duct_Sun_FR_Lower_phys); + _m->dbg_Auto_Duct_Sun_FR_Upper_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Sun_FR_Upper_ro_toS(_m->dbg_Auto_Duct_Sun_FR_Upper_phys); + _m->dbg_Auto_Duct_Sun_RL_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Sun_RL_ro_toS(_m->dbg_Auto_Duct_Sun_RL_phys); + _m->dbg_Auto_Duct_Sun_FL_Upper_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Sun_FL_Upper_ro_toS(_m->dbg_Auto_Duct_Sun_FL_Upper_phys); + _m->dbg_Auto_Duct_Sun_RR_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Sun_RR_ro_toS(_m->dbg_Auto_Duct_Sun_RR_phys); + _m->dbg_Auto_Duct_Tg_Incar_RR_ro = (int16_t) CANDB_DBG_dbg_Auto_Duct_Tg_Incar_RR_ro_toS(_m->dbg_Auto_Duct_Tg_Incar_RR_phys); +#endif // CANDB_DBG_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->dbg_Auto_Duct_MultMsg_Idx & (0x0FU)) | ((_m->dbg_Auto_Duct_Tgt_FL_Upper_ro & (0x0FU)) << 4U) | ((_m->dbg_Auto_Duct_Tg_Incar_FL_Upper_ro & (0x0FU)) << 4U) | ((_m->dbg_Auto_Duct_Tgt_RR_ro & (0x0FU)) << 4U) | ((_m->dbg_Auto_Duct_Tgt_RL_ro & (0x0FU)) << 4U) | ((_m->dbg_Auto_Duct_Tgt_FR_Upper_ro & (0x0FU)) << 4U) | ((_m->dbg_Auto_Duct_Tgt_FR_Lower_ro & (0x0FU)) << 4U) | ((_m->dbg_Auto_Duct_Tgt_FL_Lower_ro & (0x0FU)) << 4U) ); + _d[1] |= (uint8_t) ( ((_m->dbg_Auto_Duct_Tgt_FL_Upper_ro >> 4U) & (0xFFU)) | ((_m->dbg_Auto_Duct_Tg_Incar_FL_Upper_ro >> 4U) & (0x3FU)) | ((_m->dbg_Auto_Duct_Tgt_RR_ro >> 4U) & (0xFFU)) | ((_m->dbg_Auto_Duct_Tgt_RL_ro >> 4U) & (0xFFU)) | ((_m->dbg_Auto_Duct_Tgt_FR_Upper_ro >> 4U) & (0xFFU)) | ((_m->dbg_Auto_Duct_Tgt_FR_Lower_ro >> 4U) & (0xFFU)) | ((_m->dbg_Auto_Duct_Tgt_FL_Lower_ro >> 4U) & (0xFFU)) | ((_m->dbg_Auto_Duct_Tg_Incar_FR_Upper_ro & (0x03U)) << 6U) ); + _d[2] |= (uint8_t) ( ((_m->dbg_Auto_Duct_Tg_Incar_FR_Upper_ro >> 2U) & (0xFFU)) | (_m->dbg_Auto_Duct_Tg_FL_Upper_ro & (0xFFU)) | (_m->dbg_Auto_Duct_Tg_FL_Lower_ro & (0xFFU)) | (_m->dbg_Auto_Duct_Tg_FR_Lower_ro & (0xFFU)) | (_m->dbg_Auto_Duct_Tg_FR_Upper_ro & (0xFFU)) | (_m->dbg_Auto_Duct_Tg_RL_ro & (0xFFU)) | (_m->dbg_Auto_Duct_Tg_RR_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->dbg_Auto_Duct_Tg_FL_Upper_ro >> 8U) & (0x0FU)) | ((_m->dbg_Auto_Duct_Tg_FL_Lower_ro >> 8U) & (0x0FU)) | ((_m->dbg_Auto_Duct_Tg_FR_Lower_ro >> 8U) & (0x0FU)) | ((_m->dbg_Auto_Duct_Tg_FR_Upper_ro >> 8U) & (0x0FU)) | ((_m->dbg_Auto_Duct_Tg_RL_ro >> 8U) & (0x0FU)) | ((_m->dbg_Auto_Duct_Tg_RR_ro >> 8U) & (0x0FU)) | (_m->dbg_Auto_Duct_Tg_Incar_FL_Lower_ro & (0xFFU)) | ((_m->dbg_Auto_Duct_Incar_FL_Lower_ro & (0x0FU)) << 4U) | ((_m->dbg_Auto_Duct_Incar_RR_ro & (0x0FU)) << 4U) | ((_m->dbg_Auto_Duct_Incar_RL_ro & (0x0FU)) << 4U) | ((_m->dbg_Auto_Duct_Incar_FR_Upper_ro & (0x0FU)) << 4U) | ((_m->dbg_Auto_Duct_Incar_FR_Lower_ro & (0x0FU)) << 4U) | ((_m->dbg_Auto_Duct_Incar_FL_Upper_ro & (0x0FU)) << 4U) ); + _d[4] |= (uint8_t) ( ((_m->dbg_Auto_Duct_Tg_Incar_FL_Lower_ro >> 8U) & (0x03U)) | ((_m->dbg_Auto_Duct_Incar_FL_Lower_ro >> 4U) & (0xFFU)) | ((_m->dbg_Auto_Duct_Incar_RR_ro >> 4U) & (0xFFU)) | ((_m->dbg_Auto_Duct_Incar_RL_ro >> 4U) & (0xFFU)) | ((_m->dbg_Auto_Duct_Incar_FR_Upper_ro >> 4U) & (0xFFU)) | ((_m->dbg_Auto_Duct_Incar_FR_Lower_ro >> 4U) & (0xFFU)) | ((_m->dbg_Auto_Duct_Incar_FL_Upper_ro >> 4U) & (0xFFU)) | ((_m->dbg_Auto_Duct_Tg_Incar_FR_Lower_ro & (0x3FU)) << 2U) ); + _d[5] |= (uint8_t) ( ((_m->dbg_Auto_Duct_Tg_Incar_FR_Lower_ro >> 6U) & (0x0FU)) | (_m->dbg_Auto_Duct_Amb_RL_ro & (0xFFU)) | (_m->dbg_Auto_Duct_Amb_FR_Upper_ro & (0xFFU)) | (_m->dbg_Auto_Duct_Amb_FR_Lower_ro & (0xFFU)) | (_m->dbg_Auto_Duct_Amb_RR_ro & (0xFFU)) | (_m->dbg_Auto_Duct_Amb_FL_Lower_ro & (0xFFU)) | (_m->dbg_Auto_Duct_Amb_FL_Upper_ro & (0xFFU)) | ((_m->dbg_Auto_Duct_Tg_Incar_RL_ro & (0x0FU)) << 4U) ); + _d[6] |= (uint8_t) ( ((_m->dbg_Auto_Duct_Amb_RL_ro >> 8U) & (0x0FU)) | ((_m->dbg_Auto_Duct_Amb_FR_Upper_ro >> 8U) & (0x0FU)) | ((_m->dbg_Auto_Duct_Amb_FR_Lower_ro >> 8U) & (0x0FU)) | ((_m->dbg_Auto_Duct_Amb_RR_ro >> 8U) & (0x0FU)) | ((_m->dbg_Auto_Duct_Amb_FL_Lower_ro >> 8U) & (0x0FU)) | ((_m->dbg_Auto_Duct_Amb_FL_Upper_ro >> 8U) & (0x0FU)) | ((_m->dbg_Auto_Duct_Tg_Incar_RL_ro >> 4U) & (0x3FU)) | ((_m->dbg_Auto_Duct_Sun_FL_Lower_ro & (0x0FU)) << 4U) | ((_m->dbg_Auto_Duct_Sun_FR_Lower_ro & (0x0FU)) << 4U) | ((_m->dbg_Auto_Duct_Sun_FR_Upper_ro & (0x0FU)) << 4U) | ((_m->dbg_Auto_Duct_Sun_RL_ro & (0x0FU)) << 4U) | ((_m->dbg_Auto_Duct_Sun_FL_Upper_ro & (0x0FU)) << 4U) | ((_m->dbg_Auto_Duct_Sun_RR_ro & (0x0FU)) << 4U) | ((_m->dbg_Auto_Duct_Tg_Incar_RR_ro & (0x03U)) << 6U) ); + _d[7] |= (uint8_t) ( ((_m->dbg_Auto_Duct_Sun_FL_Lower_ro >> 4U) & (0xFFU)) | ((_m->dbg_Auto_Duct_Sun_FR_Lower_ro >> 4U) & (0xFFU)) | ((_m->dbg_Auto_Duct_Sun_FR_Upper_ro >> 4U) & (0xFFU)) | ((_m->dbg_Auto_Duct_Sun_RL_ro >> 4U) & (0xFFU)) | ((_m->dbg_Auto_Duct_Sun_FL_Upper_ro >> 4U) & (0xFFU)) | ((_m->dbg_Auto_Duct_Sun_RR_ro >> 4U) & (0xFFU)) | ((_m->dbg_Auto_Duct_Tg_Incar_RR_ro >> 2U) & (0xFFU)) ); + + *_len = (uint8_t) dbg_Auto_Duct_DLC; + *_ide = (uint8_t) dbg_Auto_Duct_IDE; + return dbg_Auto_Duct_CANID; +} + +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Auto_Valve_Plus_candb_dbg(dbg_Auto_Valve_Plus_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->dbg_Auto_Valve_Plus_Vent_SFL_ro = (int16_t) __ext_sig__(( ((_d[1] & (0x03U)) << 8U) | (_d[0] & (0xFFU)) ), 10); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Valve_Plus_Vent_SFL_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Valve_Plus_Vent_SFL_ro_fromS(_m->dbg_Auto_Valve_Plus_Vent_SFL_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Valve_Plus_Vent_CFL_ro = (int16_t) __ext_sig__(( ((_d[2] & (0x0FU)) << 6U) | ((_d[1] >> 2U) & (0x3FU)) ), 10); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Valve_Plus_Vent_CFL_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Valve_Plus_Vent_CFL_ro_fromS(_m->dbg_Auto_Valve_Plus_Vent_CFL_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Valve_Plus_Foot_FL_ro = (int16_t) __ext_sig__(( ((_d[3] & (0x3FU)) << 4U) | ((_d[2] >> 4U) & (0x0FU)) ), 10); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Valve_Plus_Foot_FL_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Valve_Plus_Foot_FL_ro_fromS(_m->dbg_Auto_Valve_Plus_Foot_FL_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Valve_Plus_Vent_SFR_ro = (int16_t) __ext_sig__(( ((_d[5] & (0x03U)) << 8U) | (_d[4] & (0xFFU)) ), 10); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Valve_Plus_Vent_SFR_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Valve_Plus_Vent_SFR_ro_fromS(_m->dbg_Auto_Valve_Plus_Vent_SFR_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Valve_Plus_Vent_CFR_ro = (int16_t) __ext_sig__(( ((_d[6] & (0x0FU)) << 6U) | ((_d[5] >> 2U) & (0x3FU)) ), 10); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Valve_Plus_Vent_CFR_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Valve_Plus_Vent_CFR_ro_fromS(_m->dbg_Auto_Valve_Plus_Vent_CFR_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + + _m->dbg_Auto_Valve_Plus_Foot_FR_ro = (int16_t) __ext_sig__(( ((_d[7] & (0x3FU)) << 4U) | ((_d[6] >> 4U) & (0x0FU)) ), 10); +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Valve_Plus_Foot_FR_phys = (sigfloat_t)(CANDB_DBG_dbg_Auto_Valve_Plus_Foot_FR_ro_fromS(_m->dbg_Auto_Valve_Plus_Foot_FR_ro)); +#endif // CANDB_DBG_USE_SIGFLOAT + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < dbg_Auto_Valve_Plus_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_dbg_Auto_Valve_Plus_candb_dbg(&_m->mon1, dbg_Auto_Valve_Plus_CANID); +#endif // CANDB_DBG_USE_DIAG_MONITORS + + return dbg_Auto_Valve_Plus_CANID; +} + +#ifdef CANDB_DBG_USE_CANSTRUCT + +uint32_t Pack_dbg_Auto_Valve_Plus_candb_dbg(dbg_Auto_Valve_Plus_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Auto_Valve_Plus_DLC); cframe->Data[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Valve_Plus_Vent_SFL_ro = (int16_t) CANDB_DBG_dbg_Auto_Valve_Plus_Vent_SFL_ro_toS(_m->dbg_Auto_Valve_Plus_Vent_SFL_phys); + _m->dbg_Auto_Valve_Plus_Vent_CFL_ro = (int16_t) CANDB_DBG_dbg_Auto_Valve_Plus_Vent_CFL_ro_toS(_m->dbg_Auto_Valve_Plus_Vent_CFL_phys); + _m->dbg_Auto_Valve_Plus_Foot_FL_ro = (int16_t) CANDB_DBG_dbg_Auto_Valve_Plus_Foot_FL_ro_toS(_m->dbg_Auto_Valve_Plus_Foot_FL_phys); + _m->dbg_Auto_Valve_Plus_Vent_SFR_ro = (int16_t) CANDB_DBG_dbg_Auto_Valve_Plus_Vent_SFR_ro_toS(_m->dbg_Auto_Valve_Plus_Vent_SFR_phys); + _m->dbg_Auto_Valve_Plus_Vent_CFR_ro = (int16_t) CANDB_DBG_dbg_Auto_Valve_Plus_Vent_CFR_ro_toS(_m->dbg_Auto_Valve_Plus_Vent_CFR_phys); + _m->dbg_Auto_Valve_Plus_Foot_FR_ro = (int16_t) CANDB_DBG_dbg_Auto_Valve_Plus_Foot_FR_ro_toS(_m->dbg_Auto_Valve_Plus_Foot_FR_phys); +#endif // CANDB_DBG_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->dbg_Auto_Valve_Plus_Vent_SFL_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->dbg_Auto_Valve_Plus_Vent_SFL_ro >> 8U) & (0x03U)) | ((_m->dbg_Auto_Valve_Plus_Vent_CFL_ro & (0x3FU)) << 2U) ); + cframe->Data[2] |= (uint8_t) ( ((_m->dbg_Auto_Valve_Plus_Vent_CFL_ro >> 6U) & (0x0FU)) | ((_m->dbg_Auto_Valve_Plus_Foot_FL_ro & (0x0FU)) << 4U) ); + cframe->Data[3] |= (uint8_t) ( ((_m->dbg_Auto_Valve_Plus_Foot_FL_ro >> 4U) & (0x3FU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->dbg_Auto_Valve_Plus_Vent_SFR_ro & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->dbg_Auto_Valve_Plus_Vent_SFR_ro >> 8U) & (0x03U)) | ((_m->dbg_Auto_Valve_Plus_Vent_CFR_ro & (0x3FU)) << 2U) ); + cframe->Data[6] |= (uint8_t) ( ((_m->dbg_Auto_Valve_Plus_Vent_CFR_ro >> 6U) & (0x0FU)) | ((_m->dbg_Auto_Valve_Plus_Foot_FR_ro & (0x0FU)) << 4U) ); + cframe->Data[7] |= (uint8_t) ( ((_m->dbg_Auto_Valve_Plus_Foot_FR_ro >> 4U) & (0x3FU)) ); + + cframe->MsgId = (uint32_t) dbg_Auto_Valve_Plus_CANID; + cframe->DLC = (uint8_t) dbg_Auto_Valve_Plus_DLC; + cframe->IDE = (uint8_t) dbg_Auto_Valve_Plus_IDE; + return dbg_Auto_Valve_Plus_CANID; +} + +#else + +uint32_t Pack_dbg_Auto_Valve_Plus_candb_dbg(dbg_Auto_Valve_Plus_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Auto_Valve_Plus_DLC); _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + +#ifdef CANDB_DBG_USE_SIGFLOAT + _m->dbg_Auto_Valve_Plus_Vent_SFL_ro = (int16_t) CANDB_DBG_dbg_Auto_Valve_Plus_Vent_SFL_ro_toS(_m->dbg_Auto_Valve_Plus_Vent_SFL_phys); + _m->dbg_Auto_Valve_Plus_Vent_CFL_ro = (int16_t) CANDB_DBG_dbg_Auto_Valve_Plus_Vent_CFL_ro_toS(_m->dbg_Auto_Valve_Plus_Vent_CFL_phys); + _m->dbg_Auto_Valve_Plus_Foot_FL_ro = (int16_t) CANDB_DBG_dbg_Auto_Valve_Plus_Foot_FL_ro_toS(_m->dbg_Auto_Valve_Plus_Foot_FL_phys); + _m->dbg_Auto_Valve_Plus_Vent_SFR_ro = (int16_t) CANDB_DBG_dbg_Auto_Valve_Plus_Vent_SFR_ro_toS(_m->dbg_Auto_Valve_Plus_Vent_SFR_phys); + _m->dbg_Auto_Valve_Plus_Vent_CFR_ro = (int16_t) CANDB_DBG_dbg_Auto_Valve_Plus_Vent_CFR_ro_toS(_m->dbg_Auto_Valve_Plus_Vent_CFR_phys); + _m->dbg_Auto_Valve_Plus_Foot_FR_ro = (int16_t) CANDB_DBG_dbg_Auto_Valve_Plus_Foot_FR_ro_toS(_m->dbg_Auto_Valve_Plus_Foot_FR_phys); +#endif // CANDB_DBG_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->dbg_Auto_Valve_Plus_Vent_SFL_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->dbg_Auto_Valve_Plus_Vent_SFL_ro >> 8U) & (0x03U)) | ((_m->dbg_Auto_Valve_Plus_Vent_CFL_ro & (0x3FU)) << 2U) ); + _d[2] |= (uint8_t) ( ((_m->dbg_Auto_Valve_Plus_Vent_CFL_ro >> 6U) & (0x0FU)) | ((_m->dbg_Auto_Valve_Plus_Foot_FL_ro & (0x0FU)) << 4U) ); + _d[3] |= (uint8_t) ( ((_m->dbg_Auto_Valve_Plus_Foot_FL_ro >> 4U) & (0x3FU)) ); + _d[4] |= (uint8_t) ( (_m->dbg_Auto_Valve_Plus_Vent_SFR_ro & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->dbg_Auto_Valve_Plus_Vent_SFR_ro >> 8U) & (0x03U)) | ((_m->dbg_Auto_Valve_Plus_Vent_CFR_ro & (0x3FU)) << 2U) ); + _d[6] |= (uint8_t) ( ((_m->dbg_Auto_Valve_Plus_Vent_CFR_ro >> 6U) & (0x0FU)) | ((_m->dbg_Auto_Valve_Plus_Foot_FR_ro & (0x0FU)) << 4U) ); + _d[7] |= (uint8_t) ( ((_m->dbg_Auto_Valve_Plus_Foot_FR_ro >> 4U) & (0x3FU)) ); + + *_len = (uint8_t) dbg_Auto_Valve_Plus_DLC; + *_ide = (uint8_t) dbg_Auto_Valve_Plus_IDE; + return dbg_Auto_Valve_Plus_CANID; +} + +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_XCP_CCU_RX_candb_dbg(XCP_CCU_RX_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->XcpCcuRx = (int64_t) __ext_sig__(( ((uint64_t)(_d[7] & (0xFFU)) << 56U) | ((uint64_t)(_d[6] & (0xFFU)) << 48U) | ((uint64_t)(_d[5] & (0xFFU)) << 40U) | ((uint64_t)(_d[4] & (0xFFU)) << 32U) | ((_d[3] & (0xFFU)) << 24U) | ((_d[2] & (0xFFU)) << 16U) | ((_d[1] & (0xFFU)) << 8U) | (_d[0] & (0xFFU)) ), 64); + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < XCP_CCU_RX_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_XCP_CCU_RX_candb_dbg(&_m->mon1, XCP_CCU_RX_CANID); +#endif // CANDB_DBG_USE_DIAG_MONITORS + + return XCP_CCU_RX_CANID; +} + +#ifdef CANDB_DBG_USE_CANSTRUCT + +uint32_t Pack_XCP_CCU_RX_candb_dbg(XCP_CCU_RX_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(XCP_CCU_RX_DLC); cframe->Data[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->XcpCcuRx & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->XcpCcuRx >> 8U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->XcpCcuRx >> 16U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->XcpCcuRx >> 24U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->XcpCcuRx >> 32U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->XcpCcuRx >> 40U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->XcpCcuRx >> 48U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( ((_m->XcpCcuRx >> 56U) & (0xFFU)) ); + + cframe->MsgId = (uint32_t) XCP_CCU_RX_CANID; + cframe->DLC = (uint8_t) XCP_CCU_RX_DLC; + cframe->IDE = (uint8_t) XCP_CCU_RX_IDE; + return XCP_CCU_RX_CANID; +} + +#else + +uint32_t Pack_XCP_CCU_RX_candb_dbg(XCP_CCU_RX_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(XCP_CCU_RX_DLC); _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->XcpCcuRx & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->XcpCcuRx >> 8U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->XcpCcuRx >> 16U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->XcpCcuRx >> 24U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->XcpCcuRx >> 32U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->XcpCcuRx >> 40U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->XcpCcuRx >> 48U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( ((_m->XcpCcuRx >> 56U) & (0xFFU)) ); + + *_len = (uint8_t) XCP_CCU_RX_DLC; + *_ide = (uint8_t) XCP_CCU_RX_IDE; + return XCP_CCU_RX_CANID; +} + +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_XCP_CCU_TX_candb_dbg(XCP_CCU_TX_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->XcpCcuTx = (int64_t) __ext_sig__(( ((uint64_t)(_d[7] & (0xFFU)) << 56U) | ((uint64_t)(_d[6] & (0xFFU)) << 48U) | ((uint64_t)(_d[5] & (0xFFU)) << 40U) | ((uint64_t)(_d[4] & (0xFFU)) << 32U) | ((_d[3] & (0xFFU)) << 24U) | ((_d[2] & (0xFFU)) << 16U) | ((_d[1] & (0xFFU)) << 8U) | (_d[0] & (0xFFU)) ), 64); + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < XCP_CCU_TX_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_XCP_CCU_TX_candb_dbg(&_m->mon1, XCP_CCU_TX_CANID); +#endif // CANDB_DBG_USE_DIAG_MONITORS + + return XCP_CCU_TX_CANID; +} + +#ifdef CANDB_DBG_USE_CANSTRUCT + +uint32_t Pack_XCP_CCU_TX_candb_dbg(XCP_CCU_TX_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(XCP_CCU_TX_DLC); cframe->Data[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->XcpCcuTx & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->XcpCcuTx >> 8U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->XcpCcuTx >> 16U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->XcpCcuTx >> 24U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->XcpCcuTx >> 32U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->XcpCcuTx >> 40U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->XcpCcuTx >> 48U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( ((_m->XcpCcuTx >> 56U) & (0xFFU)) ); + + cframe->MsgId = (uint32_t) XCP_CCU_TX_CANID; + cframe->DLC = (uint8_t) XCP_CCU_TX_DLC; + cframe->IDE = (uint8_t) XCP_CCU_TX_IDE; + return XCP_CCU_TX_CANID; +} + +#else + +uint32_t Pack_XCP_CCU_TX_candb_dbg(XCP_CCU_TX_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(XCP_CCU_TX_DLC); _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->XcpCcuTx & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->XcpCcuTx >> 8U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->XcpCcuTx >> 16U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->XcpCcuTx >> 24U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->XcpCcuTx >> 32U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->XcpCcuTx >> 40U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->XcpCcuTx >> 48U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( ((_m->XcpCcuTx >> 56U) & (0xFFU)) ); + + *_len = (uint8_t) XCP_CCU_TX_DLC; + *_ide = (uint8_t) XCP_CCU_TX_IDE; + return XCP_CCU_TX_CANID; +} + +#endif // CANDB_DBG_USE_CANSTRUCT + diff --git a/MODULES/HVAC_M7_CAN_DBG_MATRIX/lib/candb_dbg.h b/MODULES/HVAC_M7_CAN_DBG_MATRIX/lib/candb_dbg.h new file mode 100644 index 0000000..2f7b784 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_DBG_MATRIX/lib/candb_dbg.h @@ -0,0 +1,7071 @@ +// Generator version : v3.1 +// DBC filename : CCUdbg.dbc +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +// DBC file version +#define VER_CANDB_DBG_MAJ (0U) +#define VER_CANDB_DBG_MIN (0U) + +// include current dbc-driver compilation config +#include "candb_dbg-config.h" + +#ifdef CANDB_DBG_USE_DIAG_MONITORS +// This file must define: +// base monitor struct +#include "canmonitorutil.h" + +#endif // CANDB_DBG_USE_DIAG_MONITORS + + +// DLC maximum value which is used as the limit for frame's data buffer size. +// Client can set its own value (not sure why) in driver-config +// or can test it on some limit specified by application +// e.g.: static_assert(TESTDB_MAX_DLC_VALUE <= APPLICATION_FRAME_DATA_SIZE, "Max DLC value in the driver is too big") +#ifndef CANDB_DBG_MAX_DLC_VALUE +// The value which was found out by generator (real max value) +#define CANDB_DBG_MAX_DLC_VALUE 8U +#endif + +// The limit is used for setting frame's data bytes +#define CANDB_DBG_VALIDATE_DLC(msgDlc) (((msgDlc) <= (CANDB_DBG_MAX_DLC_VALUE)) ? (msgDlc) : (CANDB_DBG_MAX_DLC_VALUE)) + +// Initial byte value to be filles in data bytes of the frame before pack signals +// User can define its own custom value in driver-config file +#ifndef CANDB_DBG_INITIAL_BYTE_VALUE +#define CANDB_DBG_INITIAL_BYTE_VALUE 0U +#endif + + +// def @dbg_Logic_State CAN Message (992 0x3e0) +#define dbg_Logic_State_IDE (0U) +#define dbg_Logic_State_DLC (8U) +#define dbg_Logic_State_CANID (0x3e0U) + +// Value tables for @Logic_Operation_Mode signal + +#ifndef Logic_Operation_Mode_dbg_Logic_State_Full_Mode +#define Logic_Operation_Mode_dbg_Logic_State_Full_Mode (3) +#endif + +#ifndef Logic_Operation_Mode_dbg_Logic_State_Reduced_Mode +#define Logic_Operation_Mode_dbg_Logic_State_Reduced_Mode (1) +#endif + +#ifndef Logic_Operation_Mode_dbg_Logic_State_Off_Mode +#define Logic_Operation_Mode_dbg_Logic_State_Off_Mode (0) +#endif + + +// Value tables for @Logic_Amb_Level signal + +#ifndef Logic_Amb_Level_dbg_Logic_State_AMB_LV5 +#define Logic_Amb_Level_dbg_Logic_State_AMB_LV5 (5) +#endif + +#ifndef Logic_Amb_Level_dbg_Logic_State_AMB_LV4 +#define Logic_Amb_Level_dbg_Logic_State_AMB_LV4 (4) +#endif + +#ifndef Logic_Amb_Level_dbg_Logic_State_AMB_LV3 +#define Logic_Amb_Level_dbg_Logic_State_AMB_LV3 (3) +#endif + +#ifndef Logic_Amb_Level_dbg_Logic_State_AMB_LV2 +#define Logic_Amb_Level_dbg_Logic_State_AMB_LV2 (2) +#endif + +#ifndef Logic_Amb_Level_dbg_Logic_State_AMB_LV1 +#define Logic_Amb_Level_dbg_Logic_State_AMB_LV1 (1) +#endif + +#ifndef Logic_Amb_Level_dbg_Logic_State_AMB_LV0 +#define Logic_Amb_Level_dbg_Logic_State_AMB_LV0 (0) +#endif + + +// Value tables for @Logic_AutoDemist_Electric signal + +#ifndef Logic_AutoDemist_Electric_dbg_Logic_State_On +#define Logic_AutoDemist_Electric_dbg_Logic_State_On (1) +#endif + +#ifndef Logic_AutoDemist_Electric_dbg_Logic_State_OFF +#define Logic_AutoDemist_Electric_dbg_Logic_State_OFF (0) +#endif + + +// Value tables for @Logic_AutoDemist_Garage signal + +#ifndef Logic_AutoDemist_Garage_dbg_Logic_State_On +#define Logic_AutoDemist_Garage_dbg_Logic_State_On (1) +#endif + +#ifndef Logic_AutoDemist_Garage_dbg_Logic_State_OFF +#define Logic_AutoDemist_Garage_dbg_Logic_State_OFF (0) +#endif + + +// Value tables for @Logic_AutoDemist_Lv_Summer signal + +#ifndef Logic_AutoDemist_Lv_Summer_dbg_Logic_State_AutoDemist_LV4 +#define Logic_AutoDemist_Lv_Summer_dbg_Logic_State_AutoDemist_LV4 (4) +#endif + +#ifndef Logic_AutoDemist_Lv_Summer_dbg_Logic_State_AutoDemist_LV3 +#define Logic_AutoDemist_Lv_Summer_dbg_Logic_State_AutoDemist_LV3 (3) +#endif + +#ifndef Logic_AutoDemist_Lv_Summer_dbg_Logic_State_AutoDemist_LV2 +#define Logic_AutoDemist_Lv_Summer_dbg_Logic_State_AutoDemist_LV2 (2) +#endif + +#ifndef Logic_AutoDemist_Lv_Summer_dbg_Logic_State_AutoDemist_LV1 +#define Logic_AutoDemist_Lv_Summer_dbg_Logic_State_AutoDemist_LV1 (1) +#endif + +#ifndef Logic_AutoDemist_Lv_Summer_dbg_Logic_State_AutoDemist_LV0 +#define Logic_AutoDemist_Lv_Summer_dbg_Logic_State_AutoDemist_LV0 (0) +#endif + + +// Value tables for @Logic_RemoteStart signal + +#ifndef Logic_RemoteStart_dbg_Logic_State_Remote_Starte_Step_3 +#define Logic_RemoteStart_dbg_Logic_State_Remote_Starte_Step_3 (3) +#endif + +#ifndef Logic_RemoteStart_dbg_Logic_State_Remote_Starte_Step_2 +#define Logic_RemoteStart_dbg_Logic_State_Remote_Starte_Step_2 (2) +#endif + +#ifndef Logic_RemoteStart_dbg_Logic_State_Remote_Starte_Step_1 +#define Logic_RemoteStart_dbg_Logic_State_Remote_Starte_Step_1 (1) +#endif + +#ifndef Logic_RemoteStart_dbg_Logic_State_Remote_Starte_Step_0 +#define Logic_RemoteStart_dbg_Logic_State_Remote_Starte_Step_0 (0) +#endif + + +// Value tables for @Logic_Rest_Mode signal + +#ifndef Logic_Rest_Mode_dbg_Logic_State_Rest_Mode_Summer +#define Logic_Rest_Mode_dbg_Logic_State_Rest_Mode_Summer (2) +#endif + +#ifndef Logic_Rest_Mode_dbg_Logic_State_Rest_Mode_Winter +#define Logic_Rest_Mode_dbg_Logic_State_Rest_Mode_Winter (1) +#endif + +#ifndef Logic_Rest_Mode_dbg_Logic_State_No_Rest_Mode +#define Logic_Rest_Mode_dbg_Logic_State_No_Rest_Mode (0) +#endif + + +// Value tables for @Logic_LoHi_Front signal + +#ifndef Logic_LoHi_Front_dbg_Logic_State_HI_Full_4zone +#define Logic_LoHi_Front_dbg_Logic_State_HI_Full_4zone (99) +#endif + +#ifndef Logic_LoHi_Front_dbg_Logic_State_HI_Both_Left_Right +#define Logic_LoHi_Front_dbg_Logic_State_HI_Both_Left_Right (88) +#endif + +#ifndef Logic_LoHi_Front_dbg_Logic_State_HI_Left_Only +#define Logic_LoHi_Front_dbg_Logic_State_HI_Left_Only (80) +#endif + +#ifndef Logic_LoHi_Front_dbg_Logic_State_LO_Full_4zone +#define Logic_LoHi_Front_dbg_Logic_State_LO_Full_4zone (22) +#endif + +#ifndef Logic_LoHi_Front_dbg_Logic_State_LO_Both_Left_Right +#define Logic_LoHi_Front_dbg_Logic_State_LO_Both_Left_Right (11) +#endif + +#ifndef Logic_LoHi_Front_dbg_Logic_State_LO_Left_Only +#define Logic_LoHi_Front_dbg_Logic_State_LO_Left_Only (10) +#endif + +#ifndef Logic_LoHi_Front_dbg_Logic_State_HI_Right_Only +#define Logic_LoHi_Front_dbg_Logic_State_HI_Right_Only (8) +#endif + +#ifndef Logic_LoHi_Front_dbg_Logic_State_LO_Right_Only +#define Logic_LoHi_Front_dbg_Logic_State_LO_Right_Only (1) +#endif + +#ifndef Logic_LoHi_Front_dbg_Logic_State_IDLE_No_LoHi +#define Logic_LoHi_Front_dbg_Logic_State_IDLE_No_LoHi (0) +#endif + + +// Value tables for @Logic_LoHi_Rear signal + +#ifndef Logic_LoHi_Rear_dbg_Logic_State_HI_Full_4zone +#define Logic_LoHi_Rear_dbg_Logic_State_HI_Full_4zone (99) +#endif + +#ifndef Logic_LoHi_Rear_dbg_Logic_State_HI_Both_Left_Right +#define Logic_LoHi_Rear_dbg_Logic_State_HI_Both_Left_Right (88) +#endif + +#ifndef Logic_LoHi_Rear_dbg_Logic_State_HI_Left_Only +#define Logic_LoHi_Rear_dbg_Logic_State_HI_Left_Only (80) +#endif + +#ifndef Logic_LoHi_Rear_dbg_Logic_State_LO_Full_4zone +#define Logic_LoHi_Rear_dbg_Logic_State_LO_Full_4zone (22) +#endif + +#ifndef Logic_LoHi_Rear_dbg_Logic_State_LO_Both_Left_Right +#define Logic_LoHi_Rear_dbg_Logic_State_LO_Both_Left_Right (11) +#endif + +#ifndef Logic_LoHi_Rear_dbg_Logic_State_LO_Left_Only +#define Logic_LoHi_Rear_dbg_Logic_State_LO_Left_Only (10) +#endif + +#ifndef Logic_LoHi_Rear_dbg_Logic_State_HI_Right_Only +#define Logic_LoHi_Rear_dbg_Logic_State_HI_Right_Only (8) +#endif + +#ifndef Logic_LoHi_Rear_dbg_Logic_State_LO_Right_Only +#define Logic_LoHi_Rear_dbg_Logic_State_LO_Right_Only (1) +#endif + +#ifndef Logic_LoHi_Rear_dbg_Logic_State_IDLE_No_LoHi +#define Logic_LoHi_Rear_dbg_Logic_State_IDLE_No_LoHi (0) +#endif + + +// Value tables for @Logic_2WayValve_Status signal + +#ifndef Logic_2WayValve_Status_dbg_Logic_State_Open +#define Logic_2WayValve_Status_dbg_Logic_State_Open (2) +#endif + +#ifndef Logic_2WayValve_Status_dbg_Logic_State_Close_Exit +#define Logic_2WayValve_Status_dbg_Logic_State_Close_Exit (1) +#endif + +#ifndef Logic_2WayValve_Status_dbg_Logic_State_Close +#define Logic_2WayValve_Status_dbg_Logic_State_Close (0) +#endif + + +// Value tables for @Logic_Start_Ctrl_Front signal + +#ifndef Logic_Start_Ctrl_Front_dbg_Logic_State_Start_Ctrl_Step3 +#define Logic_Start_Ctrl_Front_dbg_Logic_State_Start_Ctrl_Step3 (4) +#endif + +#ifndef Logic_Start_Ctrl_Front_dbg_Logic_State_Start_Ctrl_Step1 +#define Logic_Start_Ctrl_Front_dbg_Logic_State_Start_Ctrl_Step1 (2) +#endif + +#ifndef Logic_Start_Ctrl_Front_dbg_Logic_State_Start_Ctrl_Step2 +#define Logic_Start_Ctrl_Front_dbg_Logic_State_Start_Ctrl_Step2 (3) +#endif + +#ifndef Logic_Start_Ctrl_Front_dbg_Logic_State_Start_Ctrl_Step0 +#define Logic_Start_Ctrl_Front_dbg_Logic_State_Start_Ctrl_Step0 (1) +#endif + +#ifndef Logic_Start_Ctrl_Front_dbg_Logic_State_No_Start_Ctrl +#define Logic_Start_Ctrl_Front_dbg_Logic_State_No_Start_Ctrl (0) +#endif + + +// Value tables for @Logic_Start_Ctrl_Rear signal + +#ifndef Logic_Start_Ctrl_Rear_dbg_Logic_State_Start_Ctrl_Step3 +#define Logic_Start_Ctrl_Rear_dbg_Logic_State_Start_Ctrl_Step3 (4) +#endif + +#ifndef Logic_Start_Ctrl_Rear_dbg_Logic_State_Start_Ctrl_Step1 +#define Logic_Start_Ctrl_Rear_dbg_Logic_State_Start_Ctrl_Step1 (2) +#endif + +#ifndef Logic_Start_Ctrl_Rear_dbg_Logic_State_Start_Ctrl_Step2 +#define Logic_Start_Ctrl_Rear_dbg_Logic_State_Start_Ctrl_Step2 (3) +#endif + +#ifndef Logic_Start_Ctrl_Rear_dbg_Logic_State_Start_Ctrl_Step0 +#define Logic_Start_Ctrl_Rear_dbg_Logic_State_Start_Ctrl_Step0 (1) +#endif + +#ifndef Logic_Start_Ctrl_Rear_dbg_Logic_State_No_Start_Ctrl +#define Logic_Start_Ctrl_Rear_dbg_Logic_State_No_Start_Ctrl (0) +#endif + + +// Value tables for @Logic_Duct_WaitCorrection_FRL signal + +#ifndef Logic_Duct_WaitCorrection_FRL_dbg_Logic_State_DONE +#define Logic_Duct_WaitCorrection_FRL_dbg_Logic_State_DONE (3) +#endif + +#ifndef Logic_Duct_WaitCorrection_FRL_dbg_Logic_State_CHANGE +#define Logic_Duct_WaitCorrection_FRL_dbg_Logic_State_CHANGE (2) +#endif + +#ifndef Logic_Duct_WaitCorrection_FRL_dbg_Logic_State_WAIT +#define Logic_Duct_WaitCorrection_FRL_dbg_Logic_State_WAIT (1) +#endif + +#ifndef Logic_Duct_WaitCorrection_FRL_dbg_Logic_State_OFF +#define Logic_Duct_WaitCorrection_FRL_dbg_Logic_State_OFF (0) +#endif + + +// Value tables for @Logic_Duct_WaitCorrection_FLL signal + +#ifndef Logic_Duct_WaitCorrection_FLL_dbg_Logic_State_DONE +#define Logic_Duct_WaitCorrection_FLL_dbg_Logic_State_DONE (3) +#endif + +#ifndef Logic_Duct_WaitCorrection_FLL_dbg_Logic_State_CHANGE +#define Logic_Duct_WaitCorrection_FLL_dbg_Logic_State_CHANGE (2) +#endif + +#ifndef Logic_Duct_WaitCorrection_FLL_dbg_Logic_State_WAIT +#define Logic_Duct_WaitCorrection_FLL_dbg_Logic_State_WAIT (1) +#endif + +#ifndef Logic_Duct_WaitCorrection_FLL_dbg_Logic_State_OFF +#define Logic_Duct_WaitCorrection_FLL_dbg_Logic_State_OFF (0) +#endif + + +// Value tables for @Logic_AutoDemist_Lv_Winter signal + +#ifndef Logic_AutoDemist_Lv_Winter_dbg_Logic_State_AutoDemist_LV4 +#define Logic_AutoDemist_Lv_Winter_dbg_Logic_State_AutoDemist_LV4 (4) +#endif + +#ifndef Logic_AutoDemist_Lv_Winter_dbg_Logic_State_AutoDemist_LV3 +#define Logic_AutoDemist_Lv_Winter_dbg_Logic_State_AutoDemist_LV3 (3) +#endif + +#ifndef Logic_AutoDemist_Lv_Winter_dbg_Logic_State_AutoDemist_LV2 +#define Logic_AutoDemist_Lv_Winter_dbg_Logic_State_AutoDemist_LV2 (2) +#endif + +#ifndef Logic_AutoDemist_Lv_Winter_dbg_Logic_State_AutoDemist_LV1 +#define Logic_AutoDemist_Lv_Winter_dbg_Logic_State_AutoDemist_LV1 (1) +#endif + +#ifndef Logic_AutoDemist_Lv_Winter_dbg_Logic_State_AutoDemist_LV0 +#define Logic_AutoDemist_Lv_Winter_dbg_Logic_State_AutoDemist_LV0 (0) +#endif + + +// Value tables for @Logic_AF_WaitCorrection_FL signal + +#ifndef Logic_AF_WaitCorrection_FL_dbg_Logic_State_DONE +#define Logic_AF_WaitCorrection_FL_dbg_Logic_State_DONE (3) +#endif + +#ifndef Logic_AF_WaitCorrection_FL_dbg_Logic_State_CHANGE +#define Logic_AF_WaitCorrection_FL_dbg_Logic_State_CHANGE (2) +#endif + +#ifndef Logic_AF_WaitCorrection_FL_dbg_Logic_State_WAIT +#define Logic_AF_WaitCorrection_FL_dbg_Logic_State_WAIT (1) +#endif + +#ifndef Logic_AF_WaitCorrection_FL_dbg_Logic_State_OFF +#define Logic_AF_WaitCorrection_FL_dbg_Logic_State_OFF (0) +#endif + + +// Value tables for @Logic_AF_WaitCorrection_FR signal + +#ifndef Logic_AF_WaitCorrection_FR_dbg_Logic_State_DONE +#define Logic_AF_WaitCorrection_FR_dbg_Logic_State_DONE (3) +#endif + +#ifndef Logic_AF_WaitCorrection_FR_dbg_Logic_State_CHANGE +#define Logic_AF_WaitCorrection_FR_dbg_Logic_State_CHANGE (2) +#endif + +#ifndef Logic_AF_WaitCorrection_FR_dbg_Logic_State_WAIT +#define Logic_AF_WaitCorrection_FR_dbg_Logic_State_WAIT (1) +#endif + +#ifndef Logic_AF_WaitCorrection_FR_dbg_Logic_State_OFF +#define Logic_AF_WaitCorrection_FR_dbg_Logic_State_OFF (0) +#endif + + +typedef struct +{ +#ifdef CANDB_DBG_USE_BITS_SIGNAL + + // 3 : "Full Mode" + // 1 : "Reduced Mode" + // 0 : "Off Mode" + uint8_t Logic_Operation_Mode : 2; // Bits= 2 + + // 5 : "AMB_LV5" + // 4 : "AMB_LV4" + // 3 : "AMB_LV3" + // 2 : "AMB_LV2" + // 1 : "AMB_LV1" + // 0 : "AMB_LV0" + uint8_t Logic_Amb_Level : 4; // Bits= 4 + + // 1 : "On" + // 0 : "OFF" + uint8_t Logic_AutoDemist_Electric : 1; // Bits= 1 + + // 1 : "On" + // 0 : "OFF" + uint8_t Logic_AutoDemist_Garage : 1; // Bits= 1 + + // 4 : "AutoDemist_LV4" + // 3 : "AutoDemist_LV3" + // 2 : "AutoDemist_LV2" + // 1 : "AutoDemist_LV1" + // 0 : "AutoDemist_LV0" + uint8_t Logic_AutoDemist_Lv_Summer : 4; // Bits= 4 + + // 3 : "Remote Starte Step 3" + // 2 : "Remote Starte Step 2" + // 1 : "Remote Starte Step 1" + // 0 : "Remote Starte Step 0" + uint8_t Logic_RemoteStart : 2; // Bits= 2 + + // 2 : "Rest Mode_Summer" + // 1 : "Rest Mode_Winter" + // 0 : "No Rest Mode" + uint8_t Logic_Rest_Mode : 2; // Bits= 2 + + // 99 : "HI_Full_4zone" + // 88 : "HI_Both_Left_Right" + // 80 : "HI_Left_Only" + // 22 : "LO_Full_4zone" + // 11 : "LO_Both_Left_Right" + // 10 : "LO_Left_Only" + // 8 : "HI_Right_Only" + // 1 : "LO_Right_Only" + // 0 : "IDLE_No_LoHi" + uint8_t Logic_LoHi_Front; // Bits= 8 + + // 99 : "HI_Full_4zone" + // 88 : "HI_Both_Left_Right" + // 80 : "HI_Left_Only" + // 22 : "LO_Full_4zone" + // 11 : "LO_Both_Left_Right" + // 10 : "LO_Left_Only" + // 8 : "HI_Right_Only" + // 1 : "LO_Right_Only" + // 0 : "IDLE_No_LoHi" + uint8_t Logic_LoHi_Rear; // Bits= 8 + + // 2 : "Open" + // 1 : "Close_Exit" + // 0 : "Close" + uint8_t Logic_2WayValve_Status : 2; // Bits= 2 + + uint8_t Logic_Full_Auto_FL : 1; // Bits= 1 Unit:'(off 0, on 1)' + + uint8_t Logic_Full_Auto_FR : 1; // Bits= 1 Unit:'(off 0, on 1)' + + uint8_t Logic_Full_Auto_RL : 1; // Bits= 1 Unit:'(off 0, on 1)' + + uint8_t Logic_Full_Auto_RR : 1; // Bits= 1 Unit:'(off 0, on 1)' + + uint8_t Logic_Full_MaxAc : 1; // Bits= 1 Unit:'(off 0, on 1)' + + uint8_t Logic_Full_MaxDef : 1; // Bits= 1 Unit:'(off 0, on 1)' + + // 4 : "Start_Ctrl_Step3" + // 2 : "Start_Ctrl_Step1" + // 3 : "Start_Ctrl_Step2" + // 1 : "Start_Ctrl_Step0" + // 0 : "No_Start_Ctrl" + uint8_t Logic_Start_Ctrl_Front : 3; // Bits= 3 + + // 4 : "Start_Ctrl_Step3" + // 2 : "Start_Ctrl_Step1" + // 3 : "Start_Ctrl_Step2" + // 1 : "Start_Ctrl_Step0" + // 0 : "No_Start_Ctrl" + uint8_t Logic_Start_Ctrl_Rear : 3; // Bits= 3 + + uint8_t Logic_Valve_Use_DiffBlr_R2 : 1; // Bits= 1 Unit:'(off 0, on 1)' + + // 3 : "DONE" + // 2 : "CHANGE" + // 1 : "WAIT" + // 0 : "OFF" + uint8_t Logic_Duct_WaitCorrection_FRL : 2; // Bits= 2 + + // 3 : "DONE" + // 2 : "CHANGE" + // 1 : "WAIT" + // 0 : "OFF" + uint8_t Logic_Duct_WaitCorrection_FLL : 2; // Bits= 2 + + // 4 : "AutoDemist_LV4" + // 3 : "AutoDemist_LV3" + // 2 : "AutoDemist_LV2" + // 1 : "AutoDemist_LV1" + // 0 : "AutoDemist_LV0" + uint8_t Logic_AutoDemist_Lv_Winter : 4; // Bits= 4 + + // 3 : "DONE" + // 2 : "CHANGE" + // 1 : "WAIT" + // 0 : "OFF" + uint8_t Logic_AF_WaitCorrection_FL : 2; // Bits= 2 + + // 3 : "DONE" + // 2 : "CHANGE" + // 1 : "WAIT" + // 0 : "OFF" + uint8_t Logic_AF_WaitCorrection_FR : 2; // Bits= 2 + +#else + + // 3 : "Full Mode" + // 1 : "Reduced Mode" + // 0 : "Off Mode" + uint8_t Logic_Operation_Mode; // Bits= 2 + + // 5 : "AMB_LV5" + // 4 : "AMB_LV4" + // 3 : "AMB_LV3" + // 2 : "AMB_LV2" + // 1 : "AMB_LV1" + // 0 : "AMB_LV0" + uint8_t Logic_Amb_Level; // Bits= 4 + + // 1 : "On" + // 0 : "OFF" + uint8_t Logic_AutoDemist_Electric; // Bits= 1 + + // 1 : "On" + // 0 : "OFF" + uint8_t Logic_AutoDemist_Garage; // Bits= 1 + + // 4 : "AutoDemist_LV4" + // 3 : "AutoDemist_LV3" + // 2 : "AutoDemist_LV2" + // 1 : "AutoDemist_LV1" + // 0 : "AutoDemist_LV0" + uint8_t Logic_AutoDemist_Lv_Summer; // Bits= 4 + + // 3 : "Remote Starte Step 3" + // 2 : "Remote Starte Step 2" + // 1 : "Remote Starte Step 1" + // 0 : "Remote Starte Step 0" + uint8_t Logic_RemoteStart; // Bits= 2 + + // 2 : "Rest Mode_Summer" + // 1 : "Rest Mode_Winter" + // 0 : "No Rest Mode" + uint8_t Logic_Rest_Mode; // Bits= 2 + + // 99 : "HI_Full_4zone" + // 88 : "HI_Both_Left_Right" + // 80 : "HI_Left_Only" + // 22 : "LO_Full_4zone" + // 11 : "LO_Both_Left_Right" + // 10 : "LO_Left_Only" + // 8 : "HI_Right_Only" + // 1 : "LO_Right_Only" + // 0 : "IDLE_No_LoHi" + uint8_t Logic_LoHi_Front; // Bits= 8 + + // 99 : "HI_Full_4zone" + // 88 : "HI_Both_Left_Right" + // 80 : "HI_Left_Only" + // 22 : "LO_Full_4zone" + // 11 : "LO_Both_Left_Right" + // 10 : "LO_Left_Only" + // 8 : "HI_Right_Only" + // 1 : "LO_Right_Only" + // 0 : "IDLE_No_LoHi" + uint8_t Logic_LoHi_Rear; // Bits= 8 + + // 2 : "Open" + // 1 : "Close_Exit" + // 0 : "Close" + uint8_t Logic_2WayValve_Status; // Bits= 2 + + uint8_t Logic_Full_Auto_FL; // Bits= 1 Unit:'(off 0, on 1)' + + uint8_t Logic_Full_Auto_FR; // Bits= 1 Unit:'(off 0, on 1)' + + uint8_t Logic_Full_Auto_RL; // Bits= 1 Unit:'(off 0, on 1)' + + uint8_t Logic_Full_Auto_RR; // Bits= 1 Unit:'(off 0, on 1)' + + uint8_t Logic_Full_MaxAc; // Bits= 1 Unit:'(off 0, on 1)' + + uint8_t Logic_Full_MaxDef; // Bits= 1 Unit:'(off 0, on 1)' + + // 4 : "Start_Ctrl_Step3" + // 2 : "Start_Ctrl_Step1" + // 3 : "Start_Ctrl_Step2" + // 1 : "Start_Ctrl_Step0" + // 0 : "No_Start_Ctrl" + uint8_t Logic_Start_Ctrl_Front; // Bits= 3 + + // 4 : "Start_Ctrl_Step3" + // 2 : "Start_Ctrl_Step1" + // 3 : "Start_Ctrl_Step2" + // 1 : "Start_Ctrl_Step0" + // 0 : "No_Start_Ctrl" + uint8_t Logic_Start_Ctrl_Rear; // Bits= 3 + + uint8_t Logic_Valve_Use_DiffBlr_R2; // Bits= 1 Unit:'(off 0, on 1)' + + // 3 : "DONE" + // 2 : "CHANGE" + // 1 : "WAIT" + // 0 : "OFF" + uint8_t Logic_Duct_WaitCorrection_FRL; // Bits= 2 + + // 3 : "DONE" + // 2 : "CHANGE" + // 1 : "WAIT" + // 0 : "OFF" + uint8_t Logic_Duct_WaitCorrection_FLL; // Bits= 2 + + // 4 : "AutoDemist_LV4" + // 3 : "AutoDemist_LV3" + // 2 : "AutoDemist_LV2" + // 1 : "AutoDemist_LV1" + // 0 : "AutoDemist_LV0" + uint8_t Logic_AutoDemist_Lv_Winter; // Bits= 4 + + // 3 : "DONE" + // 2 : "CHANGE" + // 1 : "WAIT" + // 0 : "OFF" + uint8_t Logic_AF_WaitCorrection_FL; // Bits= 2 + + // 3 : "DONE" + // 2 : "CHANGE" + // 1 : "WAIT" + // 0 : "OFF" + uint8_t Logic_AF_WaitCorrection_FR; // Bits= 2 + +#endif // CANDB_DBG_USE_BITS_SIGNAL + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_DBG_USE_DIAG_MONITORS + +} dbg_Logic_State_t; + +// def @dbg_Logic_KM_Status CAN Message (993 0x3e1) +#define dbg_Logic_KM_Status_IDE (0U) +#define dbg_Logic_KM_Status_DLC (4U) +#define dbg_Logic_KM_Status_CANID (0x3e1U) + +// Value tables for @Logic_KM_Mode_FL signal + +#ifndef Logic_KM_Mode_FL_dbg_Logic_KM_Status_AC_Max +#define Logic_KM_Mode_FL_dbg_Logic_KM_Status_AC_Max (6) +#endif + +#ifndef Logic_KM_Mode_FL_dbg_Logic_KM_Status_Fire_Extinguis +#define Logic_KM_Mode_FL_dbg_Logic_KM_Status_Fire_Extinguis (5) +#endif + +#ifndef Logic_KM_Mode_FL_dbg_Logic_KM_Status_Rest_Mode +#define Logic_KM_Mode_FL_dbg_Logic_KM_Status_Rest_Mode (4) +#endif + +#ifndef Logic_KM_Mode_FL_dbg_Logic_KM_Status_Auto +#define Logic_KM_Mode_FL_dbg_Logic_KM_Status_Auto (3) +#endif + +#ifndef Logic_KM_Mode_FL_dbg_Logic_KM_Status_Defrost +#define Logic_KM_Mode_FL_dbg_Logic_KM_Status_Defrost (2) +#endif + +#ifndef Logic_KM_Mode_FL_dbg_Logic_KM_Status_Manual +#define Logic_KM_Mode_FL_dbg_Logic_KM_Status_Manual (1) +#endif + +#ifndef Logic_KM_Mode_FL_dbg_Logic_KM_Status_OFF +#define Logic_KM_Mode_FL_dbg_Logic_KM_Status_OFF (0) +#endif + + +// Value tables for @Logic_KM_Mode_FR signal + +#ifndef Logic_KM_Mode_FR_dbg_Logic_KM_Status_AC_Max +#define Logic_KM_Mode_FR_dbg_Logic_KM_Status_AC_Max (6) +#endif + +#ifndef Logic_KM_Mode_FR_dbg_Logic_KM_Status_Fire_Extinguis +#define Logic_KM_Mode_FR_dbg_Logic_KM_Status_Fire_Extinguis (5) +#endif + +#ifndef Logic_KM_Mode_FR_dbg_Logic_KM_Status_Rest_Mode +#define Logic_KM_Mode_FR_dbg_Logic_KM_Status_Rest_Mode (4) +#endif + +#ifndef Logic_KM_Mode_FR_dbg_Logic_KM_Status_Auto +#define Logic_KM_Mode_FR_dbg_Logic_KM_Status_Auto (3) +#endif + +#ifndef Logic_KM_Mode_FR_dbg_Logic_KM_Status_Defrost +#define Logic_KM_Mode_FR_dbg_Logic_KM_Status_Defrost (2) +#endif + +#ifndef Logic_KM_Mode_FR_dbg_Logic_KM_Status_Manual +#define Logic_KM_Mode_FR_dbg_Logic_KM_Status_Manual (1) +#endif + +#ifndef Logic_KM_Mode_FR_dbg_Logic_KM_Status_OFF +#define Logic_KM_Mode_FR_dbg_Logic_KM_Status_OFF (0) +#endif + + +// Value tables for @Logic_KM_Mode_RL signal + +#ifndef Logic_KM_Mode_RL_dbg_Logic_KM_Status_AC_Max +#define Logic_KM_Mode_RL_dbg_Logic_KM_Status_AC_Max (6) +#endif + +#ifndef Logic_KM_Mode_RL_dbg_Logic_KM_Status_Fire_Extinguis +#define Logic_KM_Mode_RL_dbg_Logic_KM_Status_Fire_Extinguis (5) +#endif + +#ifndef Logic_KM_Mode_RL_dbg_Logic_KM_Status_Rest_Mode +#define Logic_KM_Mode_RL_dbg_Logic_KM_Status_Rest_Mode (4) +#endif + +#ifndef Logic_KM_Mode_RL_dbg_Logic_KM_Status_Auto +#define Logic_KM_Mode_RL_dbg_Logic_KM_Status_Auto (3) +#endif + +#ifndef Logic_KM_Mode_RL_dbg_Logic_KM_Status_Defrost +#define Logic_KM_Mode_RL_dbg_Logic_KM_Status_Defrost (2) +#endif + +#ifndef Logic_KM_Mode_RL_dbg_Logic_KM_Status_Manual +#define Logic_KM_Mode_RL_dbg_Logic_KM_Status_Manual (1) +#endif + +#ifndef Logic_KM_Mode_RL_dbg_Logic_KM_Status_OFF +#define Logic_KM_Mode_RL_dbg_Logic_KM_Status_OFF (0) +#endif + + +// Value tables for @Logic_KM_Mode_RR signal + +#ifndef Logic_KM_Mode_RR_dbg_Logic_KM_Status_AC_Max +#define Logic_KM_Mode_RR_dbg_Logic_KM_Status_AC_Max (6) +#endif + +#ifndef Logic_KM_Mode_RR_dbg_Logic_KM_Status_Fire_Extinguis +#define Logic_KM_Mode_RR_dbg_Logic_KM_Status_Fire_Extinguis (5) +#endif + +#ifndef Logic_KM_Mode_RR_dbg_Logic_KM_Status_Rest_Mode +#define Logic_KM_Mode_RR_dbg_Logic_KM_Status_Rest_Mode (4) +#endif + +#ifndef Logic_KM_Mode_RR_dbg_Logic_KM_Status_Auto +#define Logic_KM_Mode_RR_dbg_Logic_KM_Status_Auto (3) +#endif + +#ifndef Logic_KM_Mode_RR_dbg_Logic_KM_Status_Defrost +#define Logic_KM_Mode_RR_dbg_Logic_KM_Status_Defrost (2) +#endif + +#ifndef Logic_KM_Mode_RR_dbg_Logic_KM_Status_Manual +#define Logic_KM_Mode_RR_dbg_Logic_KM_Status_Manual (1) +#endif + +#ifndef Logic_KM_Mode_RR_dbg_Logic_KM_Status_OFF +#define Logic_KM_Mode_RR_dbg_Logic_KM_Status_OFF (0) +#endif + + +// Value tables for @Logic_KM_Blower_FL signal + +#ifndef Logic_KM_Blower_FL_dbg_Logic_KM_Status_AC_Max +#define Logic_KM_Blower_FL_dbg_Logic_KM_Status_AC_Max (6) +#endif + +#ifndef Logic_KM_Blower_FL_dbg_Logic_KM_Status_Fire_Extinguis +#define Logic_KM_Blower_FL_dbg_Logic_KM_Status_Fire_Extinguis (5) +#endif + +#ifndef Logic_KM_Blower_FL_dbg_Logic_KM_Status_Rest_Mode +#define Logic_KM_Blower_FL_dbg_Logic_KM_Status_Rest_Mode (4) +#endif + +#ifndef Logic_KM_Blower_FL_dbg_Logic_KM_Status_Auto +#define Logic_KM_Blower_FL_dbg_Logic_KM_Status_Auto (3) +#endif + +#ifndef Logic_KM_Blower_FL_dbg_Logic_KM_Status_Defrost +#define Logic_KM_Blower_FL_dbg_Logic_KM_Status_Defrost (2) +#endif + +#ifndef Logic_KM_Blower_FL_dbg_Logic_KM_Status_Manual +#define Logic_KM_Blower_FL_dbg_Logic_KM_Status_Manual (1) +#endif + +#ifndef Logic_KM_Blower_FL_dbg_Logic_KM_Status_OFF +#define Logic_KM_Blower_FL_dbg_Logic_KM_Status_OFF (0) +#endif + + +// Value tables for @Logic_KM_Blower_FR signal + +#ifndef Logic_KM_Blower_FR_dbg_Logic_KM_Status_AC_Max +#define Logic_KM_Blower_FR_dbg_Logic_KM_Status_AC_Max (6) +#endif + +#ifndef Logic_KM_Blower_FR_dbg_Logic_KM_Status_Fire_Extinguis +#define Logic_KM_Blower_FR_dbg_Logic_KM_Status_Fire_Extinguis (5) +#endif + +#ifndef Logic_KM_Blower_FR_dbg_Logic_KM_Status_Rest_Mode +#define Logic_KM_Blower_FR_dbg_Logic_KM_Status_Rest_Mode (4) +#endif + +#ifndef Logic_KM_Blower_FR_dbg_Logic_KM_Status_Auto +#define Logic_KM_Blower_FR_dbg_Logic_KM_Status_Auto (3) +#endif + +#ifndef Logic_KM_Blower_FR_dbg_Logic_KM_Status_Defrost +#define Logic_KM_Blower_FR_dbg_Logic_KM_Status_Defrost (2) +#endif + +#ifndef Logic_KM_Blower_FR_dbg_Logic_KM_Status_Manual +#define Logic_KM_Blower_FR_dbg_Logic_KM_Status_Manual (1) +#endif + +#ifndef Logic_KM_Blower_FR_dbg_Logic_KM_Status_OFF +#define Logic_KM_Blower_FR_dbg_Logic_KM_Status_OFF (0) +#endif + + +// Value tables for @Logic_KM_Blower_RL signal + +#ifndef Logic_KM_Blower_RL_dbg_Logic_KM_Status_AC_Max +#define Logic_KM_Blower_RL_dbg_Logic_KM_Status_AC_Max (6) +#endif + +#ifndef Logic_KM_Blower_RL_dbg_Logic_KM_Status_Fire_Extinguis +#define Logic_KM_Blower_RL_dbg_Logic_KM_Status_Fire_Extinguis (5) +#endif + +#ifndef Logic_KM_Blower_RL_dbg_Logic_KM_Status_Rest_Mode +#define Logic_KM_Blower_RL_dbg_Logic_KM_Status_Rest_Mode (4) +#endif + +#ifndef Logic_KM_Blower_RL_dbg_Logic_KM_Status_Auto +#define Logic_KM_Blower_RL_dbg_Logic_KM_Status_Auto (3) +#endif + +#ifndef Logic_KM_Blower_RL_dbg_Logic_KM_Status_Defrost +#define Logic_KM_Blower_RL_dbg_Logic_KM_Status_Defrost (2) +#endif + +#ifndef Logic_KM_Blower_RL_dbg_Logic_KM_Status_Manual +#define Logic_KM_Blower_RL_dbg_Logic_KM_Status_Manual (1) +#endif + +#ifndef Logic_KM_Blower_RL_dbg_Logic_KM_Status_OFF +#define Logic_KM_Blower_RL_dbg_Logic_KM_Status_OFF (0) +#endif + + +// Value tables for @Logic_KM_Blower_RR signal + +#ifndef Logic_KM_Blower_RR_dbg_Logic_KM_Status_AC_Max +#define Logic_KM_Blower_RR_dbg_Logic_KM_Status_AC_Max (6) +#endif + +#ifndef Logic_KM_Blower_RR_dbg_Logic_KM_Status_Fire_Extinguis +#define Logic_KM_Blower_RR_dbg_Logic_KM_Status_Fire_Extinguis (5) +#endif + +#ifndef Logic_KM_Blower_RR_dbg_Logic_KM_Status_Rest_Mode +#define Logic_KM_Blower_RR_dbg_Logic_KM_Status_Rest_Mode (4) +#endif + +#ifndef Logic_KM_Blower_RR_dbg_Logic_KM_Status_Auto +#define Logic_KM_Blower_RR_dbg_Logic_KM_Status_Auto (3) +#endif + +#ifndef Logic_KM_Blower_RR_dbg_Logic_KM_Status_Defrost +#define Logic_KM_Blower_RR_dbg_Logic_KM_Status_Defrost (2) +#endif + +#ifndef Logic_KM_Blower_RR_dbg_Logic_KM_Status_Manual +#define Logic_KM_Blower_RR_dbg_Logic_KM_Status_Manual (1) +#endif + +#ifndef Logic_KM_Blower_RR_dbg_Logic_KM_Status_OFF +#define Logic_KM_Blower_RR_dbg_Logic_KM_Status_OFF (0) +#endif + + +typedef struct +{ +#ifdef CANDB_DBG_USE_BITS_SIGNAL + + // 6 : "AC_Max" + // 5 : "Fire_Extinguis" + // 4 : "Rest_Mode" + // 3 : "Auto" + // 2 : "Defrost" + // 1 : "Manual" + // 0 : "OFF" + uint8_t Logic_KM_Mode_FL : 4; // Bits= 4 + + // 6 : "AC_Max" + // 5 : "Fire_Extinguis" + // 4 : "Rest_Mode" + // 3 : "Auto" + // 2 : "Defrost" + // 1 : "Manual" + // 0 : "OFF" + uint8_t Logic_KM_Mode_FR : 4; // Bits= 4 + + // 6 : "AC_Max" + // 5 : "Fire_Extinguis" + // 4 : "Rest_Mode" + // 3 : "Auto" + // 2 : "Defrost" + // 1 : "Manual" + // 0 : "OFF" + uint8_t Logic_KM_Mode_RL : 4; // Bits= 4 + + // 6 : "AC_Max" + // 5 : "Fire_Extinguis" + // 4 : "Rest_Mode" + // 3 : "Auto" + // 2 : "Defrost" + // 1 : "Manual" + // 0 : "OFF" + uint8_t Logic_KM_Mode_RR : 4; // Bits= 4 + + // 6 : "AC_Max" + // 5 : "Fire_Extinguis" + // 4 : "Rest_Mode" + // 3 : "Auto" + // 2 : "Defrost" + // 1 : "Manual" + // 0 : "OFF" + uint8_t Logic_KM_Blower_FL : 4; // Bits= 4 + + // 6 : "AC_Max" + // 5 : "Fire_Extinguis" + // 4 : "Rest_Mode" + // 3 : "Auto" + // 2 : "Defrost" + // 1 : "Manual" + // 0 : "OFF" + uint8_t Logic_KM_Blower_FR : 4; // Bits= 4 + + // 6 : "AC_Max" + // 5 : "Fire_Extinguis" + // 4 : "Rest_Mode" + // 3 : "Auto" + // 2 : "Defrost" + // 1 : "Manual" + // 0 : "OFF" + uint8_t Logic_KM_Blower_RL : 4; // Bits= 4 + + // 6 : "AC_Max" + // 5 : "Fire_Extinguis" + // 4 : "Rest_Mode" + // 3 : "Auto" + // 2 : "Defrost" + // 1 : "Manual" + // 0 : "OFF" + uint8_t Logic_KM_Blower_RR : 4; // Bits= 4 + +#else + + // 6 : "AC_Max" + // 5 : "Fire_Extinguis" + // 4 : "Rest_Mode" + // 3 : "Auto" + // 2 : "Defrost" + // 1 : "Manual" + // 0 : "OFF" + uint8_t Logic_KM_Mode_FL; // Bits= 4 + + // 6 : "AC_Max" + // 5 : "Fire_Extinguis" + // 4 : "Rest_Mode" + // 3 : "Auto" + // 2 : "Defrost" + // 1 : "Manual" + // 0 : "OFF" + uint8_t Logic_KM_Mode_FR; // Bits= 4 + + // 6 : "AC_Max" + // 5 : "Fire_Extinguis" + // 4 : "Rest_Mode" + // 3 : "Auto" + // 2 : "Defrost" + // 1 : "Manual" + // 0 : "OFF" + uint8_t Logic_KM_Mode_RL; // Bits= 4 + + // 6 : "AC_Max" + // 5 : "Fire_Extinguis" + // 4 : "Rest_Mode" + // 3 : "Auto" + // 2 : "Defrost" + // 1 : "Manual" + // 0 : "OFF" + uint8_t Logic_KM_Mode_RR; // Bits= 4 + + // 6 : "AC_Max" + // 5 : "Fire_Extinguis" + // 4 : "Rest_Mode" + // 3 : "Auto" + // 2 : "Defrost" + // 1 : "Manual" + // 0 : "OFF" + uint8_t Logic_KM_Blower_FL; // Bits= 4 + + // 6 : "AC_Max" + // 5 : "Fire_Extinguis" + // 4 : "Rest_Mode" + // 3 : "Auto" + // 2 : "Defrost" + // 1 : "Manual" + // 0 : "OFF" + uint8_t Logic_KM_Blower_FR; // Bits= 4 + + // 6 : "AC_Max" + // 5 : "Fire_Extinguis" + // 4 : "Rest_Mode" + // 3 : "Auto" + // 2 : "Defrost" + // 1 : "Manual" + // 0 : "OFF" + uint8_t Logic_KM_Blower_RL; // Bits= 4 + + // 6 : "AC_Max" + // 5 : "Fire_Extinguis" + // 4 : "Rest_Mode" + // 3 : "Auto" + // 2 : "Defrost" + // 1 : "Manual" + // 0 : "OFF" + uint8_t Logic_KM_Blower_RR; // Bits= 4 + +#endif // CANDB_DBG_USE_BITS_SIGNAL + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_DBG_USE_DIAG_MONITORS + +} dbg_Logic_KM_Status_t; + +// def @dbg_Logic_Valve CAN Message (994 0x3e2) +#define dbg_Logic_Valve_IDE (0U) +#define dbg_Logic_Valve_DLC (6U) +#define dbg_Logic_Valve_CANID (0x3e2U) + +// Value tables for @Logic_Valve_Index_FL signal + +#ifndef Logic_Valve_Index_FL_dbg_Logic_Valve__Re_Bi2Valve_manual +#define Logic_Valve_Index_FL_dbg_Logic_Valve__Re_Bi2Valve_manual (200) +#endif + +#ifndef Logic_Valve_Index_FL_dbg_Logic_Valve__Re_Vent_manual +#define Logic_Valve_Index_FL_dbg_Logic_Valve__Re_Vent_manual (190) +#endif + +#ifndef Logic_Valve_Index_FL_dbg_Logic_Valve__Re_Bi2Valve_3 +#define Logic_Valve_Index_FL_dbg_Logic_Valve__Re_Bi2Valve_3 (180) +#endif + +#ifndef Logic_Valve_Index_FL_dbg_Logic_Valve__Re_Vent_3 +#define Logic_Valve_Index_FL_dbg_Logic_Valve__Re_Vent_3 (170) +#endif + +#ifndef Logic_Valve_Index_FL_dbg_Logic_Valve__Re_Bi2Valve_2 +#define Logic_Valve_Index_FL_dbg_Logic_Valve__Re_Bi2Valve_2 (160) +#endif + +#ifndef Logic_Valve_Index_FL_dbg_Logic_Valve__Re_Vent_2 +#define Logic_Valve_Index_FL_dbg_Logic_Valve__Re_Vent_2 (150) +#endif + +#ifndef Logic_Valve_Index_FL_dbg_Logic_Valve__Re_Fo2Valve +#define Logic_Valve_Index_FL_dbg_Logic_Valve__Re_Fo2Valve (140) +#endif + +#ifndef Logic_Valve_Index_FL_dbg_Logic_Valve__Re_Bi2Valve +#define Logic_Valve_Index_FL_dbg_Logic_Valve__Re_Bi2Valve (130) +#endif + +#ifndef Logic_Valve_Index_FL_dbg_Logic_Valve__Re_Vent +#define Logic_Valve_Index_FL_dbg_Logic_Valve__Re_Vent (120) +#endif + +#ifndef Logic_Valve_Index_FL_dbg_Logic_Valve__Fr_BiValve_manual +#define Logic_Valve_Index_FL_dbg_Logic_Valve__Fr_BiValve_manual (110) +#endif + +#ifndef Logic_Valve_Index_FL_dbg_Logic_Valve__Fr_Hi2Valve +#define Logic_Valve_Index_FL_dbg_Logic_Valve__Fr_Hi2Valve (100) +#endif + +#ifndef Logic_Valve_Index_FL_dbg_Logic_Valve__Fr_Tr2Valve +#define Logic_Valve_Index_FL_dbg_Logic_Valve__Fr_Tr2Valve (90) +#endif + +#ifndef Logic_Valve_Index_FL_dbg_Logic_Valve__Fr_De2Valve +#define Logic_Valve_Index_FL_dbg_Logic_Valve__Fr_De2Valve (80) +#endif + +#ifndef Logic_Valve_Index_FL_dbg_Logic_Valve__Fr_Fd2Valve +#define Logic_Valve_Index_FL_dbg_Logic_Valve__Fr_Fd2Valve (70) +#endif + +#ifndef Logic_Valve_Index_FL_dbg_Logic_Valve__Fr_Fo2Valve +#define Logic_Valve_Index_FL_dbg_Logic_Valve__Fr_Fo2Valve (60) +#endif + +#ifndef Logic_Valve_Index_FL_dbg_Logic_Valve__Fr_AF2Valve_Summer +#define Logic_Valve_Index_FL_dbg_Logic_Valve__Fr_AF2Valve_Summer (50) +#endif + +#ifndef Logic_Valve_Index_FL_dbg_Logic_Valve__Fr_AF2Valve +#define Logic_Valve_Index_FL_dbg_Logic_Valve__Fr_AF2Valve (40) +#endif + +#ifndef Logic_Valve_Index_FL_dbg_Logic_Valve__Fr_Bi2Valve +#define Logic_Valve_Index_FL_dbg_Logic_Valve__Fr_Bi2Valve (30) +#endif + +#ifndef Logic_Valve_Index_FL_dbg_Logic_Valve__Fr_BiValve +#define Logic_Valve_Index_FL_dbg_Logic_Valve__Fr_BiValve (20) +#endif + +#ifndef Logic_Valve_Index_FL_dbg_Logic_Valve__Fr_Ve2Valve +#define Logic_Valve_Index_FL_dbg_Logic_Valve__Fr_Ve2Valve (10) +#endif + + +// Value tables for @Logic_Valve_Index_FR signal + +#ifndef Logic_Valve_Index_FR_dbg_Logic_Valve__Re_Bi2Valve_manual +#define Logic_Valve_Index_FR_dbg_Logic_Valve__Re_Bi2Valve_manual (200) +#endif + +#ifndef Logic_Valve_Index_FR_dbg_Logic_Valve__Re_Vent_manual +#define Logic_Valve_Index_FR_dbg_Logic_Valve__Re_Vent_manual (190) +#endif + +#ifndef Logic_Valve_Index_FR_dbg_Logic_Valve__Re_Bi2Valve_3 +#define Logic_Valve_Index_FR_dbg_Logic_Valve__Re_Bi2Valve_3 (180) +#endif + +#ifndef Logic_Valve_Index_FR_dbg_Logic_Valve__Re_Vent_3 +#define Logic_Valve_Index_FR_dbg_Logic_Valve__Re_Vent_3 (170) +#endif + +#ifndef Logic_Valve_Index_FR_dbg_Logic_Valve__Re_Bi2Valve_2 +#define Logic_Valve_Index_FR_dbg_Logic_Valve__Re_Bi2Valve_2 (160) +#endif + +#ifndef Logic_Valve_Index_FR_dbg_Logic_Valve__Re_Vent_2 +#define Logic_Valve_Index_FR_dbg_Logic_Valve__Re_Vent_2 (150) +#endif + +#ifndef Logic_Valve_Index_FR_dbg_Logic_Valve__Re_Fo2Valve +#define Logic_Valve_Index_FR_dbg_Logic_Valve__Re_Fo2Valve (140) +#endif + +#ifndef Logic_Valve_Index_FR_dbg_Logic_Valve__Re_Bi2Valve +#define Logic_Valve_Index_FR_dbg_Logic_Valve__Re_Bi2Valve (130) +#endif + +#ifndef Logic_Valve_Index_FR_dbg_Logic_Valve__Re_Vent +#define Logic_Valve_Index_FR_dbg_Logic_Valve__Re_Vent (120) +#endif + +#ifndef Logic_Valve_Index_FR_dbg_Logic_Valve__Fr_BiValve_manual +#define Logic_Valve_Index_FR_dbg_Logic_Valve__Fr_BiValve_manual (110) +#endif + +#ifndef Logic_Valve_Index_FR_dbg_Logic_Valve__Fr_Hi2Valve +#define Logic_Valve_Index_FR_dbg_Logic_Valve__Fr_Hi2Valve (100) +#endif + +#ifndef Logic_Valve_Index_FR_dbg_Logic_Valve__Fr_Tr2Valve +#define Logic_Valve_Index_FR_dbg_Logic_Valve__Fr_Tr2Valve (90) +#endif + +#ifndef Logic_Valve_Index_FR_dbg_Logic_Valve__Fr_De2Valve +#define Logic_Valve_Index_FR_dbg_Logic_Valve__Fr_De2Valve (80) +#endif + +#ifndef Logic_Valve_Index_FR_dbg_Logic_Valve__Fr_Fd2Valve +#define Logic_Valve_Index_FR_dbg_Logic_Valve__Fr_Fd2Valve (70) +#endif + +#ifndef Logic_Valve_Index_FR_dbg_Logic_Valve__Fr_Fo2Valve +#define Logic_Valve_Index_FR_dbg_Logic_Valve__Fr_Fo2Valve (60) +#endif + +#ifndef Logic_Valve_Index_FR_dbg_Logic_Valve__Fr_AF2Valve_Summer +#define Logic_Valve_Index_FR_dbg_Logic_Valve__Fr_AF2Valve_Summer (50) +#endif + +#ifndef Logic_Valve_Index_FR_dbg_Logic_Valve__Fr_AF2Valve +#define Logic_Valve_Index_FR_dbg_Logic_Valve__Fr_AF2Valve (40) +#endif + +#ifndef Logic_Valve_Index_FR_dbg_Logic_Valve__Fr_Bi2Valve +#define Logic_Valve_Index_FR_dbg_Logic_Valve__Fr_Bi2Valve (30) +#endif + +#ifndef Logic_Valve_Index_FR_dbg_Logic_Valve__Fr_BiValve +#define Logic_Valve_Index_FR_dbg_Logic_Valve__Fr_BiValve (20) +#endif + +#ifndef Logic_Valve_Index_FR_dbg_Logic_Valve__Fr_Ve2Valve +#define Logic_Valve_Index_FR_dbg_Logic_Valve__Fr_Ve2Valve (10) +#endif + + +// Value tables for @Logic_Valve_Index_RL signal + +#ifndef Logic_Valve_Index_RL_dbg_Logic_Valve__Re_Bi2Valve_manual +#define Logic_Valve_Index_RL_dbg_Logic_Valve__Re_Bi2Valve_manual (200) +#endif + +#ifndef Logic_Valve_Index_RL_dbg_Logic_Valve__Re_Vent_manual +#define Logic_Valve_Index_RL_dbg_Logic_Valve__Re_Vent_manual (190) +#endif + +#ifndef Logic_Valve_Index_RL_dbg_Logic_Valve__Re_Bi2Valve_3 +#define Logic_Valve_Index_RL_dbg_Logic_Valve__Re_Bi2Valve_3 (180) +#endif + +#ifndef Logic_Valve_Index_RL_dbg_Logic_Valve__Re_Vent_3 +#define Logic_Valve_Index_RL_dbg_Logic_Valve__Re_Vent_3 (170) +#endif + +#ifndef Logic_Valve_Index_RL_dbg_Logic_Valve__Re_Bi2Valve_2 +#define Logic_Valve_Index_RL_dbg_Logic_Valve__Re_Bi2Valve_2 (160) +#endif + +#ifndef Logic_Valve_Index_RL_dbg_Logic_Valve__Re_Vent_2 +#define Logic_Valve_Index_RL_dbg_Logic_Valve__Re_Vent_2 (150) +#endif + +#ifndef Logic_Valve_Index_RL_dbg_Logic_Valve__Re_Fo2Valve +#define Logic_Valve_Index_RL_dbg_Logic_Valve__Re_Fo2Valve (140) +#endif + +#ifndef Logic_Valve_Index_RL_dbg_Logic_Valve__Re_Bi2Valve +#define Logic_Valve_Index_RL_dbg_Logic_Valve__Re_Bi2Valve (130) +#endif + +#ifndef Logic_Valve_Index_RL_dbg_Logic_Valve__Re_Vent +#define Logic_Valve_Index_RL_dbg_Logic_Valve__Re_Vent (120) +#endif + +#ifndef Logic_Valve_Index_RL_dbg_Logic_Valve__Fr_BiValve_manual +#define Logic_Valve_Index_RL_dbg_Logic_Valve__Fr_BiValve_manual (110) +#endif + +#ifndef Logic_Valve_Index_RL_dbg_Logic_Valve__Fr_Hi2Valve +#define Logic_Valve_Index_RL_dbg_Logic_Valve__Fr_Hi2Valve (100) +#endif + +#ifndef Logic_Valve_Index_RL_dbg_Logic_Valve__Fr_Tr2Valve +#define Logic_Valve_Index_RL_dbg_Logic_Valve__Fr_Tr2Valve (90) +#endif + +#ifndef Logic_Valve_Index_RL_dbg_Logic_Valve__Fr_De2Valve +#define Logic_Valve_Index_RL_dbg_Logic_Valve__Fr_De2Valve (80) +#endif + +#ifndef Logic_Valve_Index_RL_dbg_Logic_Valve__Fr_Fd2Valve +#define Logic_Valve_Index_RL_dbg_Logic_Valve__Fr_Fd2Valve (70) +#endif + +#ifndef Logic_Valve_Index_RL_dbg_Logic_Valve__Fr_Fo2Valve +#define Logic_Valve_Index_RL_dbg_Logic_Valve__Fr_Fo2Valve (60) +#endif + +#ifndef Logic_Valve_Index_RL_dbg_Logic_Valve__Fr_AF2Valve_Summer +#define Logic_Valve_Index_RL_dbg_Logic_Valve__Fr_AF2Valve_Summer (50) +#endif + +#ifndef Logic_Valve_Index_RL_dbg_Logic_Valve__Fr_AF2Valve +#define Logic_Valve_Index_RL_dbg_Logic_Valve__Fr_AF2Valve (40) +#endif + +#ifndef Logic_Valve_Index_RL_dbg_Logic_Valve__Fr_Bi2Valve +#define Logic_Valve_Index_RL_dbg_Logic_Valve__Fr_Bi2Valve (30) +#endif + +#ifndef Logic_Valve_Index_RL_dbg_Logic_Valve__Fr_BiValve +#define Logic_Valve_Index_RL_dbg_Logic_Valve__Fr_BiValve (20) +#endif + +#ifndef Logic_Valve_Index_RL_dbg_Logic_Valve__Fr_Ve2Valve +#define Logic_Valve_Index_RL_dbg_Logic_Valve__Fr_Ve2Valve (10) +#endif + + +// Value tables for @Logic_Valve_Index_RR signal + +#ifndef Logic_Valve_Index_RR_dbg_Logic_Valve__Re_Bi2Valve_manual +#define Logic_Valve_Index_RR_dbg_Logic_Valve__Re_Bi2Valve_manual (200) +#endif + +#ifndef Logic_Valve_Index_RR_dbg_Logic_Valve__Re_Vent_manual +#define Logic_Valve_Index_RR_dbg_Logic_Valve__Re_Vent_manual (190) +#endif + +#ifndef Logic_Valve_Index_RR_dbg_Logic_Valve__Re_Bi2Valve_3 +#define Logic_Valve_Index_RR_dbg_Logic_Valve__Re_Bi2Valve_3 (180) +#endif + +#ifndef Logic_Valve_Index_RR_dbg_Logic_Valve__Re_Vent_3 +#define Logic_Valve_Index_RR_dbg_Logic_Valve__Re_Vent_3 (170) +#endif + +#ifndef Logic_Valve_Index_RR_dbg_Logic_Valve__Re_Bi2Valve_2 +#define Logic_Valve_Index_RR_dbg_Logic_Valve__Re_Bi2Valve_2 (160) +#endif + +#ifndef Logic_Valve_Index_RR_dbg_Logic_Valve__Re_Vent_2 +#define Logic_Valve_Index_RR_dbg_Logic_Valve__Re_Vent_2 (150) +#endif + +#ifndef Logic_Valve_Index_RR_dbg_Logic_Valve__Re_Fo2Valve +#define Logic_Valve_Index_RR_dbg_Logic_Valve__Re_Fo2Valve (140) +#endif + +#ifndef Logic_Valve_Index_RR_dbg_Logic_Valve__Re_Bi2Valve +#define Logic_Valve_Index_RR_dbg_Logic_Valve__Re_Bi2Valve (130) +#endif + +#ifndef Logic_Valve_Index_RR_dbg_Logic_Valve__Re_Vent +#define Logic_Valve_Index_RR_dbg_Logic_Valve__Re_Vent (120) +#endif + +#ifndef Logic_Valve_Index_RR_dbg_Logic_Valve__Fr_BiValve_manual +#define Logic_Valve_Index_RR_dbg_Logic_Valve__Fr_BiValve_manual (110) +#endif + +#ifndef Logic_Valve_Index_RR_dbg_Logic_Valve__Fr_Hi2Valve +#define Logic_Valve_Index_RR_dbg_Logic_Valve__Fr_Hi2Valve (100) +#endif + +#ifndef Logic_Valve_Index_RR_dbg_Logic_Valve__Fr_Tr2Valve +#define Logic_Valve_Index_RR_dbg_Logic_Valve__Fr_Tr2Valve (90) +#endif + +#ifndef Logic_Valve_Index_RR_dbg_Logic_Valve__Fr_De2Valve +#define Logic_Valve_Index_RR_dbg_Logic_Valve__Fr_De2Valve (80) +#endif + +#ifndef Logic_Valve_Index_RR_dbg_Logic_Valve__Fr_Fd2Valve +#define Logic_Valve_Index_RR_dbg_Logic_Valve__Fr_Fd2Valve (70) +#endif + +#ifndef Logic_Valve_Index_RR_dbg_Logic_Valve__Fr_Fo2Valve +#define Logic_Valve_Index_RR_dbg_Logic_Valve__Fr_Fo2Valve (60) +#endif + +#ifndef Logic_Valve_Index_RR_dbg_Logic_Valve__Fr_AF2Valve_Summer +#define Logic_Valve_Index_RR_dbg_Logic_Valve__Fr_AF2Valve_Summer (50) +#endif + +#ifndef Logic_Valve_Index_RR_dbg_Logic_Valve__Fr_AF2Valve +#define Logic_Valve_Index_RR_dbg_Logic_Valve__Fr_AF2Valve (40) +#endif + +#ifndef Logic_Valve_Index_RR_dbg_Logic_Valve__Fr_Bi2Valve +#define Logic_Valve_Index_RR_dbg_Logic_Valve__Fr_Bi2Valve (30) +#endif + +#ifndef Logic_Valve_Index_RR_dbg_Logic_Valve__Fr_BiValve +#define Logic_Valve_Index_RR_dbg_Logic_Valve__Fr_BiValve (20) +#endif + +#ifndef Logic_Valve_Index_RR_dbg_Logic_Valve__Fr_Ve2Valve +#define Logic_Valve_Index_RR_dbg_Logic_Valve__Fr_Ve2Valve (10) +#endif + + +// Value tables for @Logic_Valve_Direction_FL signal + +#ifndef Logic_Valve_Direction_FL_dbg_Logic_Valve_TriLevel__GlassVentFoot +#define Logic_Valve_Direction_FL_dbg_Logic_Valve_TriLevel__GlassVentFoot (6) +#endif + +#ifndef Logic_Valve_Direction_FL_dbg_Logic_Valve_HiLevel__GlassVent +#define Logic_Valve_Direction_FL_dbg_Logic_Valve_HiLevel__GlassVent (5) +#endif + +#ifndef Logic_Valve_Direction_FL_dbg_Logic_Valve_Def__Glass +#define Logic_Valve_Direction_FL_dbg_Logic_Valve_Def__Glass (4) +#endif + +#ifndef Logic_Valve_Direction_FL_dbg_Logic_Valve_FDef__GlassFoot +#define Logic_Valve_Direction_FL_dbg_Logic_Valve_FDef__GlassFoot (3) +#endif + +#ifndef Logic_Valve_Direction_FL_dbg_Logic_Valve_Foot__Floor +#define Logic_Valve_Direction_FL_dbg_Logic_Valve_Foot__Floor (2) +#endif + +#ifndef Logic_Valve_Direction_FL_dbg_Logic_Valve_BiLevel +#define Logic_Valve_Direction_FL_dbg_Logic_Valve_BiLevel (1) +#endif + +#ifndef Logic_Valve_Direction_FL_dbg_Logic_Valve_Face__Vent +#define Logic_Valve_Direction_FL_dbg_Logic_Valve_Face__Vent (0) +#endif + + +// Value tables for @Logic_Valve_Direction_FR signal + +#ifndef Logic_Valve_Direction_FR_dbg_Logic_Valve_TriLevel__GlassVentFoot +#define Logic_Valve_Direction_FR_dbg_Logic_Valve_TriLevel__GlassVentFoot (6) +#endif + +#ifndef Logic_Valve_Direction_FR_dbg_Logic_Valve_HiLevel__GlassVent +#define Logic_Valve_Direction_FR_dbg_Logic_Valve_HiLevel__GlassVent (5) +#endif + +#ifndef Logic_Valve_Direction_FR_dbg_Logic_Valve_Def__Glass +#define Logic_Valve_Direction_FR_dbg_Logic_Valve_Def__Glass (4) +#endif + +#ifndef Logic_Valve_Direction_FR_dbg_Logic_Valve_FDef__GlassFoot +#define Logic_Valve_Direction_FR_dbg_Logic_Valve_FDef__GlassFoot (3) +#endif + +#ifndef Logic_Valve_Direction_FR_dbg_Logic_Valve_Foot__Floor +#define Logic_Valve_Direction_FR_dbg_Logic_Valve_Foot__Floor (2) +#endif + +#ifndef Logic_Valve_Direction_FR_dbg_Logic_Valve_BiLevel +#define Logic_Valve_Direction_FR_dbg_Logic_Valve_BiLevel (1) +#endif + +#ifndef Logic_Valve_Direction_FR_dbg_Logic_Valve_Face__Vent +#define Logic_Valve_Direction_FR_dbg_Logic_Valve_Face__Vent (0) +#endif + + +// Value tables for @Logic_Valve_Direction_RL signal + +#ifndef Logic_Valve_Direction_RL_dbg_Logic_Valve_TriLevel__GlassVentFoot +#define Logic_Valve_Direction_RL_dbg_Logic_Valve_TriLevel__GlassVentFoot (6) +#endif + +#ifndef Logic_Valve_Direction_RL_dbg_Logic_Valve_HiLevel__GlassVent +#define Logic_Valve_Direction_RL_dbg_Logic_Valve_HiLevel__GlassVent (5) +#endif + +#ifndef Logic_Valve_Direction_RL_dbg_Logic_Valve_Def__Glass +#define Logic_Valve_Direction_RL_dbg_Logic_Valve_Def__Glass (4) +#endif + +#ifndef Logic_Valve_Direction_RL_dbg_Logic_Valve_FDef__GlassFoot +#define Logic_Valve_Direction_RL_dbg_Logic_Valve_FDef__GlassFoot (3) +#endif + +#ifndef Logic_Valve_Direction_RL_dbg_Logic_Valve_Foot__Floor +#define Logic_Valve_Direction_RL_dbg_Logic_Valve_Foot__Floor (2) +#endif + +#ifndef Logic_Valve_Direction_RL_dbg_Logic_Valve_BiLevel +#define Logic_Valve_Direction_RL_dbg_Logic_Valve_BiLevel (1) +#endif + +#ifndef Logic_Valve_Direction_RL_dbg_Logic_Valve_Face__Vent +#define Logic_Valve_Direction_RL_dbg_Logic_Valve_Face__Vent (0) +#endif + + +// Value tables for @Logic_Valve_Direction_RR signal + +#ifndef Logic_Valve_Direction_RR_dbg_Logic_Valve_TriLevel__GlassVentFoot +#define Logic_Valve_Direction_RR_dbg_Logic_Valve_TriLevel__GlassVentFoot (6) +#endif + +#ifndef Logic_Valve_Direction_RR_dbg_Logic_Valve_HiLevel__GlassVent +#define Logic_Valve_Direction_RR_dbg_Logic_Valve_HiLevel__GlassVent (5) +#endif + +#ifndef Logic_Valve_Direction_RR_dbg_Logic_Valve_Def__Glass +#define Logic_Valve_Direction_RR_dbg_Logic_Valve_Def__Glass (4) +#endif + +#ifndef Logic_Valve_Direction_RR_dbg_Logic_Valve_FDef__GlassFoot +#define Logic_Valve_Direction_RR_dbg_Logic_Valve_FDef__GlassFoot (3) +#endif + +#ifndef Logic_Valve_Direction_RR_dbg_Logic_Valve_Foot__Floor +#define Logic_Valve_Direction_RR_dbg_Logic_Valve_Foot__Floor (2) +#endif + +#ifndef Logic_Valve_Direction_RR_dbg_Logic_Valve_BiLevel +#define Logic_Valve_Direction_RR_dbg_Logic_Valve_BiLevel (1) +#endif + +#ifndef Logic_Valve_Direction_RR_dbg_Logic_Valve_Face__Vent +#define Logic_Valve_Direction_RR_dbg_Logic_Valve_Face__Vent (0) +#endif + + +typedef struct +{ +#ifdef CANDB_DBG_USE_BITS_SIGNAL + + // 200 : "200_Re_Bi2Valve manual" + // 190 : "190_Re_Vent manual" + // 180 : "180_Re_Bi2Valve_3" + // 170 : "170_Re_Vent_3" + // 160 : "160_Re_Bi2Valve_2" + // 150 : "150_Re_Vent_2" + // 140 : "140_Re_Fo2Valve" + // 130 : "130_Re_Bi2Valve" + // 120 : "120_Re_Vent" + // 110 : "110_Fr_BiValve manual" + // 100 : "100_Fr_Hi2Valve" + // 90 : "090_Fr_Tr2Valve" + // 80 : "080_Fr_De2Valve" + // 70 : "070_Fr_Fd2Valve" + // 60 : "060_Fr_Fo2Valve" + // 50 : "050_Fr_AF2Valve_Summer" + // 40 : "040_Fr_AF2Valve" + // 30 : "030_Fr_Bi2Valve" + // 20 : "020_Fr_BiValve" + // 10 : "010_Fr_Ve2Valve" + uint8_t Logic_Valve_Index_FL; // Bits= 8 + + // 200 : "200_Re_Bi2Valve manual" + // 190 : "190_Re_Vent manual" + // 180 : "180_Re_Bi2Valve_3" + // 170 : "170_Re_Vent_3" + // 160 : "160_Re_Bi2Valve_2" + // 150 : "150_Re_Vent_2" + // 140 : "140_Re_Fo2Valve" + // 130 : "130_Re_Bi2Valve" + // 120 : "120_Re_Vent" + // 110 : "110_Fr_BiValve manual" + // 100 : "100_Fr_Hi2Valve" + // 90 : "090_Fr_Tr2Valve" + // 80 : "080_Fr_De2Valve" + // 70 : "070_Fr_Fd2Valve" + // 60 : "060_Fr_Fo2Valve" + // 50 : "050_Fr_AF2Valve_Summer" + // 40 : "040_Fr_AF2Valve" + // 30 : "030_Fr_Bi2Valve" + // 20 : "020_Fr_BiValve" + // 10 : "010_Fr_Ve2Valve" + uint8_t Logic_Valve_Index_FR; // Bits= 8 + + // 200 : "200_Re_Bi2Valve manual" + // 190 : "190_Re_Vent manual" + // 180 : "180_Re_Bi2Valve_3" + // 170 : "170_Re_Vent_3" + // 160 : "160_Re_Bi2Valve_2" + // 150 : "150_Re_Vent_2" + // 140 : "140_Re_Fo2Valve" + // 130 : "130_Re_Bi2Valve" + // 120 : "120_Re_Vent" + // 110 : "110_Fr_BiValve manual" + // 100 : "100_Fr_Hi2Valve" + // 90 : "090_Fr_Tr2Valve" + // 80 : "080_Fr_De2Valve" + // 70 : "070_Fr_Fd2Valve" + // 60 : "060_Fr_Fo2Valve" + // 50 : "050_Fr_AF2Valve_Summer" + // 40 : "040_Fr_AF2Valve" + // 30 : "030_Fr_Bi2Valve" + // 20 : "020_Fr_BiValve" + // 10 : "010_Fr_Ve2Valve" + uint8_t Logic_Valve_Index_RL; // Bits= 8 + + // 200 : "200_Re_Bi2Valve manual" + // 190 : "190_Re_Vent manual" + // 180 : "180_Re_Bi2Valve_3" + // 170 : "170_Re_Vent_3" + // 160 : "160_Re_Bi2Valve_2" + // 150 : "150_Re_Vent_2" + // 140 : "140_Re_Fo2Valve" + // 130 : "130_Re_Bi2Valve" + // 120 : "120_Re_Vent" + // 110 : "110_Fr_BiValve manual" + // 100 : "100_Fr_Hi2Valve" + // 90 : "090_Fr_Tr2Valve" + // 80 : "080_Fr_De2Valve" + // 70 : "070_Fr_Fd2Valve" + // 60 : "060_Fr_Fo2Valve" + // 50 : "050_Fr_AF2Valve_Summer" + // 40 : "040_Fr_AF2Valve" + // 30 : "030_Fr_Bi2Valve" + // 20 : "020_Fr_BiValve" + // 10 : "010_Fr_Ve2Valve" + uint8_t Logic_Valve_Index_RR; // Bits= 8 + + // 6 : "Tri-Level / Glass&Vent&Foot" + // 5 : "Hi-Level / Glass&Vent" + // 4 : "Def / Glass" + // 3 : "FDef / Glass&Foot" + // 2 : "Foot / Floor" + // 1 : "Bi-Level" + // 0 : "Face / Vent" + uint8_t Logic_Valve_Direction_FL : 4; // Bits= 4 Unit:'-' + + // 6 : "Tri-Level / Glass&Vent&Foot" + // 5 : "Hi-Level / Glass&Vent" + // 4 : "Def / Glass" + // 3 : "FDef / Glass&Foot" + // 2 : "Foot / Floor" + // 1 : "Bi-Level" + // 0 : "Face / Vent" + uint8_t Logic_Valve_Direction_FR : 4; // Bits= 4 Unit:'-' + + // 6 : "Tri-Level / Glass&Vent&Foot" + // 5 : "Hi-Level / Glass&Vent" + // 4 : "Def / Glass" + // 3 : "FDef / Glass&Foot" + // 2 : "Foot / Floor" + // 1 : "Bi-Level" + // 0 : "Face / Vent" + uint8_t Logic_Valve_Direction_RL : 4; // Bits= 4 Unit:'-' + + // 6 : "Tri-Level / Glass&Vent&Foot" + // 5 : "Hi-Level / Glass&Vent" + // 4 : "Def / Glass" + // 3 : "FDef / Glass&Foot" + // 2 : "Foot / Floor" + // 1 : "Bi-Level" + // 0 : "Face / Vent" + uint8_t Logic_Valve_Direction_RR : 4; // Bits= 4 Unit:'-' + +#else + + // 200 : "200_Re_Bi2Valve manual" + // 190 : "190_Re_Vent manual" + // 180 : "180_Re_Bi2Valve_3" + // 170 : "170_Re_Vent_3" + // 160 : "160_Re_Bi2Valve_2" + // 150 : "150_Re_Vent_2" + // 140 : "140_Re_Fo2Valve" + // 130 : "130_Re_Bi2Valve" + // 120 : "120_Re_Vent" + // 110 : "110_Fr_BiValve manual" + // 100 : "100_Fr_Hi2Valve" + // 90 : "090_Fr_Tr2Valve" + // 80 : "080_Fr_De2Valve" + // 70 : "070_Fr_Fd2Valve" + // 60 : "060_Fr_Fo2Valve" + // 50 : "050_Fr_AF2Valve_Summer" + // 40 : "040_Fr_AF2Valve" + // 30 : "030_Fr_Bi2Valve" + // 20 : "020_Fr_BiValve" + // 10 : "010_Fr_Ve2Valve" + uint8_t Logic_Valve_Index_FL; // Bits= 8 + + // 200 : "200_Re_Bi2Valve manual" + // 190 : "190_Re_Vent manual" + // 180 : "180_Re_Bi2Valve_3" + // 170 : "170_Re_Vent_3" + // 160 : "160_Re_Bi2Valve_2" + // 150 : "150_Re_Vent_2" + // 140 : "140_Re_Fo2Valve" + // 130 : "130_Re_Bi2Valve" + // 120 : "120_Re_Vent" + // 110 : "110_Fr_BiValve manual" + // 100 : "100_Fr_Hi2Valve" + // 90 : "090_Fr_Tr2Valve" + // 80 : "080_Fr_De2Valve" + // 70 : "070_Fr_Fd2Valve" + // 60 : "060_Fr_Fo2Valve" + // 50 : "050_Fr_AF2Valve_Summer" + // 40 : "040_Fr_AF2Valve" + // 30 : "030_Fr_Bi2Valve" + // 20 : "020_Fr_BiValve" + // 10 : "010_Fr_Ve2Valve" + uint8_t Logic_Valve_Index_FR; // Bits= 8 + + // 200 : "200_Re_Bi2Valve manual" + // 190 : "190_Re_Vent manual" + // 180 : "180_Re_Bi2Valve_3" + // 170 : "170_Re_Vent_3" + // 160 : "160_Re_Bi2Valve_2" + // 150 : "150_Re_Vent_2" + // 140 : "140_Re_Fo2Valve" + // 130 : "130_Re_Bi2Valve" + // 120 : "120_Re_Vent" + // 110 : "110_Fr_BiValve manual" + // 100 : "100_Fr_Hi2Valve" + // 90 : "090_Fr_Tr2Valve" + // 80 : "080_Fr_De2Valve" + // 70 : "070_Fr_Fd2Valve" + // 60 : "060_Fr_Fo2Valve" + // 50 : "050_Fr_AF2Valve_Summer" + // 40 : "040_Fr_AF2Valve" + // 30 : "030_Fr_Bi2Valve" + // 20 : "020_Fr_BiValve" + // 10 : "010_Fr_Ve2Valve" + uint8_t Logic_Valve_Index_RL; // Bits= 8 + + // 200 : "200_Re_Bi2Valve manual" + // 190 : "190_Re_Vent manual" + // 180 : "180_Re_Bi2Valve_3" + // 170 : "170_Re_Vent_3" + // 160 : "160_Re_Bi2Valve_2" + // 150 : "150_Re_Vent_2" + // 140 : "140_Re_Fo2Valve" + // 130 : "130_Re_Bi2Valve" + // 120 : "120_Re_Vent" + // 110 : "110_Fr_BiValve manual" + // 100 : "100_Fr_Hi2Valve" + // 90 : "090_Fr_Tr2Valve" + // 80 : "080_Fr_De2Valve" + // 70 : "070_Fr_Fd2Valve" + // 60 : "060_Fr_Fo2Valve" + // 50 : "050_Fr_AF2Valve_Summer" + // 40 : "040_Fr_AF2Valve" + // 30 : "030_Fr_Bi2Valve" + // 20 : "020_Fr_BiValve" + // 10 : "010_Fr_Ve2Valve" + uint8_t Logic_Valve_Index_RR; // Bits= 8 + + // 6 : "Tri-Level / Glass&Vent&Foot" + // 5 : "Hi-Level / Glass&Vent" + // 4 : "Def / Glass" + // 3 : "FDef / Glass&Foot" + // 2 : "Foot / Floor" + // 1 : "Bi-Level" + // 0 : "Face / Vent" + uint8_t Logic_Valve_Direction_FL; // Bits= 4 Unit:'-' + + // 6 : "Tri-Level / Glass&Vent&Foot" + // 5 : "Hi-Level / Glass&Vent" + // 4 : "Def / Glass" + // 3 : "FDef / Glass&Foot" + // 2 : "Foot / Floor" + // 1 : "Bi-Level" + // 0 : "Face / Vent" + uint8_t Logic_Valve_Direction_FR; // Bits= 4 Unit:'-' + + // 6 : "Tri-Level / Glass&Vent&Foot" + // 5 : "Hi-Level / Glass&Vent" + // 4 : "Def / Glass" + // 3 : "FDef / Glass&Foot" + // 2 : "Foot / Floor" + // 1 : "Bi-Level" + // 0 : "Face / Vent" + uint8_t Logic_Valve_Direction_RL; // Bits= 4 Unit:'-' + + // 6 : "Tri-Level / Glass&Vent&Foot" + // 5 : "Hi-Level / Glass&Vent" + // 4 : "Def / Glass" + // 3 : "FDef / Glass&Foot" + // 2 : "Foot / Floor" + // 1 : "Bi-Level" + // 0 : "Face / Vent" + uint8_t Logic_Valve_Direction_RR; // Bits= 4 Unit:'-' + +#endif // CANDB_DBG_USE_BITS_SIGNAL + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_DBG_USE_DIAG_MONITORS + +} dbg_Logic_Valve_t; + +// def @dbg_Logic_Blower CAN Message (995 0x3e3) +#define dbg_Logic_Blower_IDE (0U) +#define dbg_Logic_Blower_DLC (8U) +#define dbg_Logic_Blower_CANID (0x3e3U) + +typedef struct +{ +#ifdef CANDB_DBG_USE_BITS_SIGNAL + + uint8_t Logic_Blower_Step_FL : 4; // Bits= 4 + + uint8_t Logic_Blower_Step_FR : 4; // Bits= 4 + + uint8_t Logic_Blower_Step_RL : 4; // Bits= 4 + + uint8_t Logic_Blower_Step_RR : 4; // Bits= 4 + + uint8_t Logic_Blower_Pwm_Front; // Bits= 8 Unit:'%' + + uint8_t Logic_Blower_Pwm_Rear; // Bits= 8 Unit:'%' + + uint8_t Logic_Blower_AF_FL; // Bits= 8 Unit:'AF' + + uint8_t Logic_Blower_AF_FR; // Bits= 8 Unit:'AF' + + uint8_t Logic_Blower_AF_RL; // Bits= 8 Unit:'AF' + + uint8_t Logic_Blower_AF_RR; // Bits= 8 Unit:'AF' + +#else + + uint8_t Logic_Blower_Step_FL; // Bits= 4 + + uint8_t Logic_Blower_Step_FR; // Bits= 4 + + uint8_t Logic_Blower_Step_RL; // Bits= 4 + + uint8_t Logic_Blower_Step_RR; // Bits= 4 + + uint8_t Logic_Blower_Pwm_Front; // Bits= 8 Unit:'%' + + uint8_t Logic_Blower_Pwm_Rear; // Bits= 8 Unit:'%' + + uint8_t Logic_Blower_AF_FL; // Bits= 8 Unit:'AF' + + uint8_t Logic_Blower_AF_FR; // Bits= 8 Unit:'AF' + + uint8_t Logic_Blower_AF_RL; // Bits= 8 Unit:'AF' + + uint8_t Logic_Blower_AF_RR; // Bits= 8 Unit:'AF' + +#endif // CANDB_DBG_USE_BITS_SIGNAL + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_DBG_USE_DIAG_MONITORS + +} dbg_Logic_Blower_t; + +// def @dbg_Logic_Ac CAN Message (996 0x3e4) +#define dbg_Logic_Ac_IDE (0U) +#define dbg_Logic_Ac_DLC (4U) +#define dbg_Logic_Ac_CANID (0x3e4U) + +// Value tables for @Logic_Ac_Req_Front signal + +#ifndef Logic_Ac_Req_Front_dbg_Logic_Ac_On +#define Logic_Ac_Req_Front_dbg_Logic_Ac_On (1) +#endif + +#ifndef Logic_Ac_Req_Front_dbg_Logic_Ac_Off +#define Logic_Ac_Req_Front_dbg_Logic_Ac_Off (0) +#endif + + +// Value tables for @Logic_Ac_Txv_Front signal + +#ifndef Logic_Ac_Txv_Front_dbg_Logic_Ac_On +#define Logic_Ac_Txv_Front_dbg_Logic_Ac_On (1) +#endif + +#ifndef Logic_Ac_Txv_Front_dbg_Logic_Ac_Off +#define Logic_Ac_Txv_Front_dbg_Logic_Ac_Off (0) +#endif + + +// Value tables for @Logic_Ac_Txv_Rear signal + +#ifndef Logic_Ac_Txv_Rear_dbg_Logic_Ac_On +#define Logic_Ac_Txv_Rear_dbg_Logic_Ac_On (1) +#endif + +#ifndef Logic_Ac_Txv_Rear_dbg_Logic_Ac_Off +#define Logic_Ac_Txv_Rear_dbg_Logic_Ac_Off (0) +#endif + + +// Value tables for @Logic_Ac_Req_Rear signal + +#ifndef Logic_Ac_Req_Rear_dbg_Logic_Ac_On +#define Logic_Ac_Req_Rear_dbg_Logic_Ac_On (1) +#endif + +#ifndef Logic_Ac_Req_Rear_dbg_Logic_Ac_Off +#define Logic_Ac_Req_Rear_dbg_Logic_Ac_Off (0) +#endif + + +// Value tables for @Logic_Ac_Req_Chiller signal + +#ifndef Logic_Ac_Req_Chiller_dbg_Logic_Ac_On +#define Logic_Ac_Req_Chiller_dbg_Logic_Ac_On (1) +#endif + +#ifndef Logic_Ac_Req_Chiller_dbg_Logic_Ac_Off +#define Logic_Ac_Req_Chiller_dbg_Logic_Ac_Off (0) +#endif + + +// Value tables for @Logic_Ac_Txv_Chiller signal + +#ifndef Logic_Ac_Txv_Chiller_dbg_Logic_Ac_On +#define Logic_Ac_Txv_Chiller_dbg_Logic_Ac_On (1) +#endif + +#ifndef Logic_Ac_Txv_Chiller_dbg_Logic_Ac_Off +#define Logic_Ac_Txv_Chiller_dbg_Logic_Ac_Off (0) +#endif + + +// Value tables for @Logic_Ac_EvaCtrl signal + +#ifndef Logic_Ac_EvaCtrl_dbg_Logic_Ac_Both_On_but_olny_Rear_works +#define Logic_Ac_EvaCtrl_dbg_Logic_Ac_Both_On_but_olny_Rear_works (7) +#endif + +#ifndef Logic_Ac_EvaCtrl_dbg_Logic_Ac_Both_On_but_olny_Front_works +#define Logic_Ac_EvaCtrl_dbg_Logic_Ac_Both_On_but_olny_Front_works (6) +#endif + +#ifndef Logic_Ac_EvaCtrl_dbg_Logic_Ac_Both_On_with_Rear_FB +#define Logic_Ac_EvaCtrl_dbg_Logic_Ac_Both_On_with_Rear_FB (5) +#endif + +#ifndef Logic_Ac_EvaCtrl_dbg_Logic_Ac_Both_On_with_Front_FB +#define Logic_Ac_EvaCtrl_dbg_Logic_Ac_Both_On_with_Front_FB (4) +#endif + +#ifndef Logic_Ac_EvaCtrl_dbg_Logic_Ac_Only_Rear_On +#define Logic_Ac_EvaCtrl_dbg_Logic_Ac_Only_Rear_On (3) +#endif + +#ifndef Logic_Ac_EvaCtrl_dbg_Logic_Ac_Only_Front_On +#define Logic_Ac_EvaCtrl_dbg_Logic_Ac_Only_Front_On (2) +#endif + +#ifndef Logic_Ac_EvaCtrl_dbg_Logic_Ac_Only_Chiller_On +#define Logic_Ac_EvaCtrl_dbg_Logic_Ac_Only_Chiller_On (1) +#endif + +#ifndef Logic_Ac_EvaCtrl_dbg_Logic_Ac_All_Off +#define Logic_Ac_EvaCtrl_dbg_Logic_Ac_All_Off (0) +#endif + +// signal: @Logic_Ac_Comp_LimitRpm_ro +#define CANDB_DBG_Logic_Ac_Comp_LimitRpm_ro_CovFactor (50) +#define CANDB_DBG_Logic_Ac_Comp_LimitRpm_ro_toS(x) ( (uint8_t) ((x) / (50)) ) +#define CANDB_DBG_Logic_Ac_Comp_LimitRpm_ro_fromS(x) ( ((x) * (50)) ) + +// Value tables for @Logic_Ac_WinterSts_Front signal + +#ifndef Logic_Ac_WinterSts_Front_dbg_Logic_Ac_ON_atWinter +#define Logic_Ac_WinterSts_Front_dbg_Logic_Ac_ON_atWinter (3) +#endif + +#ifndef Logic_Ac_WinterSts_Front_dbg_Logic_Ac_OFF_atWinter +#define Logic_Ac_WinterSts_Front_dbg_Logic_Ac_OFF_atWinter (2) +#endif + +#ifndef Logic_Ac_WinterSts_Front_dbg_Logic_Ac_Not_Used +#define Logic_Ac_WinterSts_Front_dbg_Logic_Ac_Not_Used (1) +#endif + +#ifndef Logic_Ac_WinterSts_Front_dbg_Logic_Ac_No_Winter +#define Logic_Ac_WinterSts_Front_dbg_Logic_Ac_No_Winter (0) +#endif + + +// Value tables for @Logic_Ac_WinterSts_Rear signal + +#ifndef Logic_Ac_WinterSts_Rear_dbg_Logic_Ac_ON_atWinter +#define Logic_Ac_WinterSts_Rear_dbg_Logic_Ac_ON_atWinter (3) +#endif + +#ifndef Logic_Ac_WinterSts_Rear_dbg_Logic_Ac_OFF_atWinter +#define Logic_Ac_WinterSts_Rear_dbg_Logic_Ac_OFF_atWinter (2) +#endif + +#ifndef Logic_Ac_WinterSts_Rear_dbg_Logic_Ac_Not_Used +#define Logic_Ac_WinterSts_Rear_dbg_Logic_Ac_Not_Used (1) +#endif + +#ifndef Logic_Ac_WinterSts_Rear_dbg_Logic_Ac_No_Winter +#define Logic_Ac_WinterSts_Rear_dbg_Logic_Ac_No_Winter (0) +#endif + + +typedef struct +{ +#ifdef CANDB_DBG_USE_BITS_SIGNAL + + // 1 : "On" + // 0 : "Off" + uint8_t Logic_Ac_Req_Front : 1; // Bits= 1 Unit:'(off 0, on 1)' + + // 1 : "On" + // 0 : "Off" + uint8_t Logic_Ac_Txv_Front : 1; // Bits= 1 Unit:'(off 0, on 1)' + + // 1 : "On" + // 0 : "Off" + uint8_t Logic_Ac_Txv_Rear : 1; // Bits= 1 Unit:'(off 0, on 1)' + + // 1 : "On" + // 0 : "Off" + uint8_t Logic_Ac_Req_Rear : 1; // Bits= 1 Unit:'(off 0, on 1)' + + // 1 : "On" + // 0 : "Off" + uint8_t Logic_Ac_Req_Chiller : 1; // Bits= 1 Unit:'(off 0, on 1)' + + // 1 : "On" + // 0 : "Off" + uint8_t Logic_Ac_Txv_Chiller : 1; // Bits= 1 Unit:'(off 0, on 1)' + + // 7 : "Both On but olny Rear works" + // 6 : "Both On but olny Front works" + // 5 : "Both On with Rear FB" + // 4 : "Both On with Front FB" + // 3 : "Only Rear On" + // 2 : "Only Front On" + // 1 : "Only Chiller On" + // 0 : "All Off" + uint8_t Logic_Ac_EvaCtrl : 4; // Bits= 4 + + uint8_t Logic_Ac_Comp_EmrStop_Reason : 4; // Bits= 4 + + uint8_t Logic_Ac_Comp_LimitRpm_ro; // Bits= 8 Factor= 50 Unit:'rpm' + +#ifdef CANDB_DBG_USE_SIGFLOAT + uint16_t Logic_Ac_Comp_LimitRpm_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + uint8_t Logic_Ac_Txv_Closed_bySen : 1; // Bits= 1 + + uint8_t Logic_Ac_Comp_Protection_Level : 2; // Bits= 2 Unit:'Lv' + + // 3 : "ON_atWinter" + // 2 : "OFF_atWinter" + // 1 : "Not_Used" + // 0 : "No_Winter" + uint8_t Logic_Ac_WinterSts_Front : 2; // Bits= 2 + + // 3 : "ON_atWinter" + // 2 : "OFF_atWinter" + // 1 : "Not_Used" + // 0 : "No_Winter" + uint8_t Logic_Ac_WinterSts_Rear : 2; // Bits= 2 + +#else + + // 1 : "On" + // 0 : "Off" + uint8_t Logic_Ac_Req_Front; // Bits= 1 Unit:'(off 0, on 1)' + + // 1 : "On" + // 0 : "Off" + uint8_t Logic_Ac_Txv_Front; // Bits= 1 Unit:'(off 0, on 1)' + + // 1 : "On" + // 0 : "Off" + uint8_t Logic_Ac_Txv_Rear; // Bits= 1 Unit:'(off 0, on 1)' + + // 1 : "On" + // 0 : "Off" + uint8_t Logic_Ac_Req_Rear; // Bits= 1 Unit:'(off 0, on 1)' + + // 1 : "On" + // 0 : "Off" + uint8_t Logic_Ac_Req_Chiller; // Bits= 1 Unit:'(off 0, on 1)' + + // 1 : "On" + // 0 : "Off" + uint8_t Logic_Ac_Txv_Chiller; // Bits= 1 Unit:'(off 0, on 1)' + + // 7 : "Both On but olny Rear works" + // 6 : "Both On but olny Front works" + // 5 : "Both On with Rear FB" + // 4 : "Both On with Front FB" + // 3 : "Only Rear On" + // 2 : "Only Front On" + // 1 : "Only Chiller On" + // 0 : "All Off" + uint8_t Logic_Ac_EvaCtrl; // Bits= 4 + + uint8_t Logic_Ac_Comp_EmrStop_Reason; // Bits= 4 + + uint8_t Logic_Ac_Comp_LimitRpm_ro; // Bits= 8 Factor= 50 Unit:'rpm' + +#ifdef CANDB_DBG_USE_SIGFLOAT + uint16_t Logic_Ac_Comp_LimitRpm_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + uint8_t Logic_Ac_Txv_Closed_bySen; // Bits= 1 + + uint8_t Logic_Ac_Comp_Protection_Level; // Bits= 2 Unit:'Lv' + + // 3 : "ON_atWinter" + // 2 : "OFF_atWinter" + // 1 : "Not_Used" + // 0 : "No_Winter" + uint8_t Logic_Ac_WinterSts_Front; // Bits= 2 + + // 3 : "ON_atWinter" + // 2 : "OFF_atWinter" + // 1 : "Not_Used" + // 0 : "No_Winter" + uint8_t Logic_Ac_WinterSts_Rear; // Bits= 2 + +#endif // CANDB_DBG_USE_BITS_SIGNAL + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_DBG_USE_DIAG_MONITORS + +} dbg_Logic_Ac_t; + +// def @dbg_Logic_Rec CAN Message (997 0x3e5) +#define dbg_Logic_Rec_IDE (0U) +#define dbg_Logic_Rec_DLC (3U) +#define dbg_Logic_Rec_CANID (0x3e5U) + +// Value tables for @Logic_Rec_Idx signal + +#ifndef Logic_Rec_Idx_dbg_Logic_Rec_REC +#define Logic_Rec_Idx_dbg_Logic_Rec_REC (1) +#endif + +#ifndef Logic_Rec_Idx_dbg_Logic_Rec_FRESH +#define Logic_Rec_Idx_dbg_Logic_Rec_FRESH (0) +#endif + + +typedef struct +{ +#ifdef CANDB_DBG_USE_BITS_SIGNAL + + // 1 : "REC" + // 0 : "FRESH" + uint8_t Logic_Rec_Idx : 1; // Bits= 1 + + uint8_t Logic_Rec_Partial_Spd_Sts : 1; // Bits= 1 + + uint8_t Logic_Rec_Partial_Winter : 1; // Bits= 1 + + uint8_t Logic_Rec_Partial_Summer : 2; // Bits= 2 + + uint8_t Logic_Rec_FreshAirPurge_Sts : 4; // Bits= 4 + +#else + + // 1 : "REC" + // 0 : "FRESH" + uint8_t Logic_Rec_Idx; // Bits= 1 + + uint8_t Logic_Rec_Partial_Spd_Sts; // Bits= 1 + + uint8_t Logic_Rec_Partial_Winter; // Bits= 1 + + uint8_t Logic_Rec_Partial_Summer; // Bits= 2 + + uint8_t Logic_Rec_FreshAirPurge_Sts; // Bits= 4 + +#endif // CANDB_DBG_USE_BITS_SIGNAL + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_DBG_USE_DIAG_MONITORS + +} dbg_Logic_Rec_t; + +// def @dbg_DiffBlr_ValveOpen CAN Message (998 0x3e6) +#define dbg_DiffBlr_ValveOpen_IDE (0U) +#define dbg_DiffBlr_ValveOpen_DLC (8U) +#define dbg_DiffBlr_ValveOpen_CANID (0x3e6U) +#define dbg_DiffBlr_ValveOpen_CYC (200U) + +typedef struct +{ +#ifdef CANDB_DBG_USE_BITS_SIGNAL + + // MULTIPLEX master signal + uint8_t Logic_ValveOpen_MultMsg_Idx : 2; // Bits= 2 + + // multiplex variable + uint8_t Logic_ValveOpen_R2_SFL; // Bits= 8 Unit:'%' + + // multiplex variable + uint8_t Logic_ValveOpen_R1_SFL; // Bits= 8 Unit:'%' + + // multiplex variable + uint8_t Logic_ValveOpen_R2_CFL; // Bits= 8 Unit:'%' + + // multiplex variable + uint8_t Logic_ValveOpen_R1_CFL; // Bits= 8 Unit:'%' + + // multiplex variable + uint8_t Logic_ValveOpen_R2_CFR; // Bits= 8 Unit:'%' + + // multiplex variable + uint8_t Logic_ValveOpen_R1_CFR; // Bits= 8 Unit:'%' + + // multiplex variable + uint8_t Logic_ValveOpen_R2_SFR; // Bits= 8 Unit:'%' + + // multiplex variable + uint8_t Logic_ValveOpen_R1_SFR; // Bits= 8 Unit:'%' + +#else + + // MULTIPLEX master signal + uint8_t Logic_ValveOpen_MultMsg_Idx; // Bits= 2 + + // multiplex variable + uint8_t Logic_ValveOpen_R2_SFL; // Bits= 8 Unit:'%' + + // multiplex variable + uint8_t Logic_ValveOpen_R1_SFL; // Bits= 8 Unit:'%' + + // multiplex variable + uint8_t Logic_ValveOpen_R2_CFL; // Bits= 8 Unit:'%' + + // multiplex variable + uint8_t Logic_ValveOpen_R1_CFL; // Bits= 8 Unit:'%' + + // multiplex variable + uint8_t Logic_ValveOpen_R2_CFR; // Bits= 8 Unit:'%' + + // multiplex variable + uint8_t Logic_ValveOpen_R1_CFR; // Bits= 8 Unit:'%' + + // multiplex variable + uint8_t Logic_ValveOpen_R2_SFR; // Bits= 8 Unit:'%' + + // multiplex variable + uint8_t Logic_ValveOpen_R1_SFR; // Bits= 8 Unit:'%' + +#endif // CANDB_DBG_USE_BITS_SIGNAL + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_DBG_USE_DIAG_MONITORS + +} dbg_DiffBlr_ValveOpen_t; + +// This is a message for not used signals, created by Vector CANdb++ DBC OLE DB Provider. +// def @dbg_Act0 CAN Message (1008 0x3f0) +#define dbg_Act0_IDE (0U) +#define dbg_Act0_DLC (8U) +#define dbg_Act0_CANID (0x3f0U) + +typedef struct +{ +#ifdef CANDB_DBG_USE_BITS_SIGNAL + + uint8_t dbg_Act00_Def; // Bits= 8 Unit:'%' + + uint8_t dbg_Act01_Vent_SFL; // Bits= 8 Unit:'%' + + uint8_t dbg_Act02_Vent_CFL; // Bits= 8 Unit:'%' + + uint8_t dbg_Act03_Foot_1FL; // Bits= 8 Unit:'%' + + uint8_t dbg_Act04_Foot_2FL; // Bits= 8 Unit:'%' + + uint8_t dbg_Act05_Vent_CFR; // Bits= 8 Unit:'%' + + uint8_t dbg_Act06_Vent_SFR; // Bits= 8 Unit:'%' + + uint8_t dbg_Act07_Foot_1FR; // Bits= 8 Unit:'%' + +#else + + uint8_t dbg_Act00_Def; // Bits= 8 Unit:'%' + + uint8_t dbg_Act01_Vent_SFL; // Bits= 8 Unit:'%' + + uint8_t dbg_Act02_Vent_CFL; // Bits= 8 Unit:'%' + + uint8_t dbg_Act03_Foot_1FL; // Bits= 8 Unit:'%' + + uint8_t dbg_Act04_Foot_2FL; // Bits= 8 Unit:'%' + + uint8_t dbg_Act05_Vent_CFR; // Bits= 8 Unit:'%' + + uint8_t dbg_Act06_Vent_SFR; // Bits= 8 Unit:'%' + + uint8_t dbg_Act07_Foot_1FR; // Bits= 8 Unit:'%' + +#endif // CANDB_DBG_USE_BITS_SIGNAL + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_DBG_USE_DIAG_MONITORS + +} dbg_Act0_t; + +// def @dbg_Act1 CAN Message (1009 0x3f1) +#define dbg_Act1_IDE (0U) +#define dbg_Act1_DLC (8U) +#define dbg_Act1_CANID (0x3f1U) + +typedef struct +{ +#ifdef CANDB_DBG_USE_BITS_SIGNAL + + uint8_t dbg_Act08_Foot_2FR; // Bits= 8 Unit:'%' + + uint8_t dbg_Act09_Vent_SRL; // Bits= 8 Unit:'%' + + uint8_t dbg_Act10_Vent_CRL; // Bits= 8 Unit:'%' + + uint8_t dbg_Act11_Foot_RL; // Bits= 8 Unit:'%' + + uint8_t dbg_Act12_Vent_CRR; // Bits= 8 Unit:'%' + + uint8_t dbg_Act13_Vent_SRR; // Bits= 8 Unit:'%' + + uint8_t dbg_Act14_Foot_RR; // Bits= 8 Unit:'%' + + uint8_t dbg_Act15_TempU_FL; // Bits= 8 Unit:'%' + +#else + + uint8_t dbg_Act08_Foot_2FR; // Bits= 8 Unit:'%' + + uint8_t dbg_Act09_Vent_SRL; // Bits= 8 Unit:'%' + + uint8_t dbg_Act10_Vent_CRL; // Bits= 8 Unit:'%' + + uint8_t dbg_Act11_Foot_RL; // Bits= 8 Unit:'%' + + uint8_t dbg_Act12_Vent_CRR; // Bits= 8 Unit:'%' + + uint8_t dbg_Act13_Vent_SRR; // Bits= 8 Unit:'%' + + uint8_t dbg_Act14_Foot_RR; // Bits= 8 Unit:'%' + + uint8_t dbg_Act15_TempU_FL; // Bits= 8 Unit:'%' + +#endif // CANDB_DBG_USE_BITS_SIGNAL + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_DBG_USE_DIAG_MONITORS + +} dbg_Act1_t; + +// def @dbg_Act2 CAN Message (1010 0x3f2) +#define dbg_Act2_IDE (0U) +#define dbg_Act2_DLC (8U) +#define dbg_Act2_CANID (0x3f2U) + +typedef struct +{ +#ifdef CANDB_DBG_USE_BITS_SIGNAL + + uint8_t dbg_Act16_TempL_FL; // Bits= 8 Unit:'%' + + uint8_t dbg_Act17_TempU_FR; // Bits= 8 Unit:'%' + + uint8_t dbg_Act18_TempL_FR; // Bits= 8 Unit:'%' + + uint8_t dbg_Act19_Temp_RL; // Bits= 8 Unit:'%' + + uint8_t dbg_Act20_Temp_RR; // Bits= 8 Unit:'%' + + uint8_t dbg_Act21_Rec; // Bits= 8 Unit:'%' + + uint8_t dbg_Act22_OSA; // Bits= 8 Unit:'%' + + uint8_t dbg_Act23_SealingValve; // Bits= 8 Unit:'%' + +#else + + uint8_t dbg_Act16_TempL_FL; // Bits= 8 Unit:'%' + + uint8_t dbg_Act17_TempU_FR; // Bits= 8 Unit:'%' + + uint8_t dbg_Act18_TempL_FR; // Bits= 8 Unit:'%' + + uint8_t dbg_Act19_Temp_RL; // Bits= 8 Unit:'%' + + uint8_t dbg_Act20_Temp_RR; // Bits= 8 Unit:'%' + + uint8_t dbg_Act21_Rec; // Bits= 8 Unit:'%' + + uint8_t dbg_Act22_OSA; // Bits= 8 Unit:'%' + + uint8_t dbg_Act23_SealingValve; // Bits= 8 Unit:'%' + +#endif // CANDB_DBG_USE_BITS_SIGNAL + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_DBG_USE_DIAG_MONITORS + +} dbg_Act2_t; + +// def @dbg_Sen_Amb CAN Message (1011 0x3f3) +#define dbg_Sen_Amb_IDE (0U) +#define dbg_Sen_Amb_DLC (6U) +#define dbg_Sen_Amb_CANID (0x3f3U) +// signal: @dbg_Sen_Amb_ro +#define CANDB_DBG_dbg_Sen_Amb_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Sen_Amb_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Sen_Amb_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Sen_Amb_Raw_ro +#define CANDB_DBG_dbg_Sen_Amb_Raw_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Sen_Amb_Raw_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Sen_Amb_Raw_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Amb_Tg_ro +#define CANDB_DBG_dbg_Amb_Tg_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Amb_Tg_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Amb_Tg_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_DBG_USE_BITS_SIGNAL + + int16_t dbg_Sen_Amb_ro; // [-] Bits=16 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Amb_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + int16_t dbg_Sen_Amb_Raw_ro; // [-] Bits=16 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Amb_Raw_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + int16_t dbg_Amb_Tg_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Amb_Tg_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + +#else + + int16_t dbg_Sen_Amb_ro; // [-] Bits=16 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Amb_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + int16_t dbg_Sen_Amb_Raw_ro; // [-] Bits=16 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Amb_Raw_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + int16_t dbg_Amb_Tg_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Amb_Tg_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + +#endif // CANDB_DBG_USE_BITS_SIGNAL + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_DBG_USE_DIAG_MONITORS + +} dbg_Sen_Amb_t; + +// def @dbg_Sen_0 CAN Message (1016 0x3f8) +#define dbg_Sen_0_IDE (0U) +#define dbg_Sen_0_DLC (8U) +#define dbg_Sen_0_CANID (0x3f8U) +#define dbg_Sen_0_CYC (250U) +// signal: @dbg_Sen_BattVolt_ro +#define CANDB_DBG_dbg_Sen_BattVolt_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Sen_BattVolt_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Sen_BattVolt_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Sen_Pressure_ro +#define CANDB_DBG_dbg_Sen_Pressure_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Sen_Pressure_ro_toS(x) ( (uint16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Sen_Pressure_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_DBG_USE_BITS_SIGNAL + + uint8_t dbg_Sen_BattVolt_ro; // Bits= 8 Factor= 0.1 Unit:'Volt' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_BattVolt_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + uint16_t dbg_Sen_Pressure_ro; // Bits=12 Factor= 0.1 Unit:'ATM' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Pressure_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + uint16_t dbg_Sen_Sun_L; // Bits=16 Unit:'W/m2' + + uint16_t dbg_Sen_Sun_R; // Bits=16 Unit:'W/m2' + +#else + + uint8_t dbg_Sen_BattVolt_ro; // Bits= 8 Factor= 0.1 Unit:'Volt' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_BattVolt_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + uint16_t dbg_Sen_Pressure_ro; // Bits=12 Factor= 0.1 Unit:'ATM' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Pressure_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + uint16_t dbg_Sen_Sun_L; // Bits=16 Unit:'W/m2' + + uint16_t dbg_Sen_Sun_R; // Bits=16 Unit:'W/m2' + +#endif // CANDB_DBG_USE_BITS_SIGNAL + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_DBG_USE_DIAG_MONITORS + +} dbg_Sen_0_t; + +// def @dbg_CCU_IO CAN Message (1019 0x3fb) +#define dbg_CCU_IO_IDE (0U) +#define dbg_CCU_IO_DLC (6U) +#define dbg_CCU_IO_CANID (0x3fbU) + +// Value tables for @dbg_IO_Txv_F signal + +#ifndef dbg_IO_Txv_F_dbg_CCU_IO_On +#define dbg_IO_Txv_F_dbg_CCU_IO_On (1) +#endif + +#ifndef dbg_IO_Txv_F_dbg_CCU_IO_Off +#define dbg_IO_Txv_F_dbg_CCU_IO_Off (0) +#endif + + +// Value tables for @dbg_IO_Txv_R signal + +#ifndef dbg_IO_Txv_R_dbg_CCU_IO_On +#define dbg_IO_Txv_R_dbg_CCU_IO_On (1) +#endif + +#ifndef dbg_IO_Txv_R_dbg_CCU_IO_Off +#define dbg_IO_Txv_R_dbg_CCU_IO_Off (0) +#endif + + +// Value tables for @dbg_IO_Txv_Ch signal + +#ifndef dbg_IO_Txv_Ch_dbg_CCU_IO_On +#define dbg_IO_Txv_Ch_dbg_CCU_IO_On (1) +#endif + +#ifndef dbg_IO_Txv_Ch_dbg_CCU_IO_Off +#define dbg_IO_Txv_Ch_dbg_CCU_IO_Off (0) +#endif + + +// Value tables for @dbg_IO_2WayValve signal + +#ifndef dbg_IO_2WayValve_dbg_CCU_IO_Open +#define dbg_IO_2WayValve_dbg_CCU_IO_Open (1) +#endif + +#ifndef dbg_IO_2WayValve_dbg_CCU_IO_Close +#define dbg_IO_2WayValve_dbg_CCU_IO_Close (0) +#endif + + +// Value tables for @dbg_IO_IncarMotor_F signal + +#ifndef dbg_IO_IncarMotor_F_dbg_CCU_IO_On +#define dbg_IO_IncarMotor_F_dbg_CCU_IO_On (1) +#endif + +#ifndef dbg_IO_IncarMotor_F_dbg_CCU_IO_Off +#define dbg_IO_IncarMotor_F_dbg_CCU_IO_Off (0) +#endif + + +// Value tables for @dbg_IO_IncarMotor_R signal + +#ifndef dbg_IO_IncarMotor_R_dbg_CCU_IO_On +#define dbg_IO_IncarMotor_R_dbg_CCU_IO_On (1) +#endif + +#ifndef dbg_IO_IncarMotor_R_dbg_CCU_IO_Off +#define dbg_IO_IncarMotor_R_dbg_CCU_IO_Off (0) +#endif + +// signal: @dbg_SetTemp_FL_ro +#define CANDB_DBG_dbg_SetTemp_FL_ro_CovFactor (0.5) +#define CANDB_DBG_dbg_SetTemp_FL_ro_toS(x) ( (uint8_t) (((x) - (16.0)) / (0.5)) ) +#define CANDB_DBG_dbg_SetTemp_FL_ro_fromS(x) ( (((x) * (0.5)) + (16.0)) ) +// signal: @dbg_SetTemp_FR_ro +#define CANDB_DBG_dbg_SetTemp_FR_ro_CovFactor (0.5) +#define CANDB_DBG_dbg_SetTemp_FR_ro_toS(x) ( (uint8_t) (((x) - (16.0)) / (0.5)) ) +#define CANDB_DBG_dbg_SetTemp_FR_ro_fromS(x) ( (((x) * (0.5)) + (16.0)) ) +// signal: @dbg_SetTemp_RL_ro +#define CANDB_DBG_dbg_SetTemp_RL_ro_CovFactor (0.5) +#define CANDB_DBG_dbg_SetTemp_RL_ro_toS(x) ( (uint8_t) (((x) - (16.0)) / (0.5)) ) +#define CANDB_DBG_dbg_SetTemp_RL_ro_fromS(x) ( (((x) * (0.5)) + (16.0)) ) +// signal: @dbg_SetTemp_RR_ro +#define CANDB_DBG_dbg_SetTemp_RR_ro_CovFactor (0.5) +#define CANDB_DBG_dbg_SetTemp_RR_ro_toS(x) ( (uint8_t) (((x) - (16.0)) / (0.5)) ) +#define CANDB_DBG_dbg_SetTemp_RR_ro_fromS(x) ( (((x) * (0.5)) + (16.0)) ) + +// Value tables for @dbg_IO_Input_Emergency signal + +#ifndef dbg_IO_Input_Emergency_dbg_CCU_IO_On +#define dbg_IO_Input_Emergency_dbg_CCU_IO_On (1) +#endif + +#ifndef dbg_IO_Input_Emergency_dbg_CCU_IO_Off +#define dbg_IO_Input_Emergency_dbg_CCU_IO_Off (0) +#endif + + +// Value tables for @dbg_IO_Input_FireExtinguisher signal + +#ifndef dbg_IO_Input_FireExtinguisher_dbg_CCU_IO_On +#define dbg_IO_Input_FireExtinguisher_dbg_CCU_IO_On (1) +#endif + +#ifndef dbg_IO_Input_FireExtinguisher_dbg_CCU_IO_Off +#define dbg_IO_Input_FireExtinguisher_dbg_CCU_IO_Off (0) +#endif + + +// Value tables for @dbg_IO_Install_Sealing_Valve signal + +#ifndef dbg_IO_Install_Sealing_Valve_dbg_CCU_IO_On +#define dbg_IO_Install_Sealing_Valve_dbg_CCU_IO_On (1) +#endif + +#ifndef dbg_IO_Install_Sealing_Valve_dbg_CCU_IO_Off +#define dbg_IO_Install_Sealing_Valve_dbg_CCU_IO_Off (0) +#endif + + +typedef struct +{ +#ifdef CANDB_DBG_USE_BITS_SIGNAL + + // 1 : "On" + // 0 : "Off" + uint8_t dbg_IO_Txv_F : 1; // Bits= 1 + + // 1 : "On" + // 0 : "Off" + uint8_t dbg_IO_Txv_R : 1; // Bits= 1 + + // 1 : "On" + // 0 : "Off" + uint8_t dbg_IO_Txv_Ch : 1; // Bits= 1 + + // 1 : "Open" + // 0 : "Close" + uint8_t dbg_IO_2WayValve : 1; // Bits= 1 + + // 1 : "On" + // 0 : "Off" + uint8_t dbg_IO_IncarMotor_F : 1; // Bits= 1 + + // 1 : "On" + // 0 : "Off" + uint8_t dbg_IO_IncarMotor_R : 1; // Bits= 1 + + uint8_t dbg_SetTemp_FL_ro; // Bits= 8 Offset= 16.0 Factor= 0.5 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_SetTemp_FL_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + uint8_t dbg_SetTemp_FR_ro; // Bits= 8 Offset= 16.0 Factor= 0.5 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_SetTemp_FR_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + uint8_t dbg_SetTemp_RL_ro; // Bits= 8 Offset= 16.0 Factor= 0.5 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_SetTemp_RL_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + uint8_t dbg_SetTemp_RR_ro; // Bits= 8 Offset= 16.0 Factor= 0.5 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_SetTemp_RR_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // 1 : "On" + // 0 : "Off" + uint8_t dbg_IO_Input_Emergency : 1; // Bits= 1 + + // 1 : "On" + // 0 : "Off" + uint8_t dbg_IO_Input_FireExtinguisher : 1; // Bits= 1 + + // 1 : "On" + // 0 : "Off" + uint8_t dbg_IO_Install_Sealing_Valve : 1; // Bits= 1 + +#else + + // 1 : "On" + // 0 : "Off" + uint8_t dbg_IO_Txv_F; // Bits= 1 + + // 1 : "On" + // 0 : "Off" + uint8_t dbg_IO_Txv_R; // Bits= 1 + + // 1 : "On" + // 0 : "Off" + uint8_t dbg_IO_Txv_Ch; // Bits= 1 + + // 1 : "Open" + // 0 : "Close" + uint8_t dbg_IO_2WayValve; // Bits= 1 + + // 1 : "On" + // 0 : "Off" + uint8_t dbg_IO_IncarMotor_F; // Bits= 1 + + // 1 : "On" + // 0 : "Off" + uint8_t dbg_IO_IncarMotor_R; // Bits= 1 + + uint8_t dbg_SetTemp_FL_ro; // Bits= 8 Offset= 16.0 Factor= 0.5 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_SetTemp_FL_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + uint8_t dbg_SetTemp_FR_ro; // Bits= 8 Offset= 16.0 Factor= 0.5 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_SetTemp_FR_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + uint8_t dbg_SetTemp_RL_ro; // Bits= 8 Offset= 16.0 Factor= 0.5 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_SetTemp_RL_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + uint8_t dbg_SetTemp_RR_ro; // Bits= 8 Offset= 16.0 Factor= 0.5 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_SetTemp_RR_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // 1 : "On" + // 0 : "Off" + uint8_t dbg_IO_Input_Emergency; // Bits= 1 + + // 1 : "On" + // 0 : "Off" + uint8_t dbg_IO_Input_FireExtinguisher; // Bits= 1 + + // 1 : "On" + // 0 : "Off" + uint8_t dbg_IO_Install_Sealing_Valve; // Bits= 1 + +#endif // CANDB_DBG_USE_BITS_SIGNAL + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_DBG_USE_DIAG_MONITORS + +} dbg_CCU_IO_t; + +// def @dbg_CCU_Info CAN Message (1020 0x3fc) +#define dbg_CCU_Info_IDE (0U) +#define dbg_CCU_Info_DLC (8U) +#define dbg_CCU_Info_CANID (0x3fcU) +#define dbg_CCU_Info_CYC (1000U) + +// Value tables for @dbg_Info_ActivatedCAL signal + +#ifndef dbg_Info_ActivatedCAL_dbg_CCU_Info_MPV_Cal +#define dbg_Info_ActivatedCAL_dbg_CCU_Info_MPV_Cal (5) +#endif + +#ifndef dbg_Info_ActivatedCAL_dbg_CCU_Info_SUV_Cal +#define dbg_Info_ActivatedCAL_dbg_CCU_Info_SUV_Cal (4) +#endif + +#ifndef dbg_Info_ActivatedCAL_dbg_CCU_Info_Limo_Cal +#define dbg_Info_ActivatedCAL_dbg_CCU_Info_Limo_Cal (3) +#endif + +#ifndef dbg_Info_ActivatedCAL_dbg_CCU_Info_SedanH_Cal +#define dbg_Info_ActivatedCAL_dbg_CCU_Info_SedanH_Cal (2) +#endif + +#ifndef dbg_Info_ActivatedCAL_dbg_CCU_Info_SedanL_Cal +#define dbg_Info_ActivatedCAL_dbg_CCU_Info_SedanL_Cal (1) +#endif + +#ifndef dbg_Info_ActivatedCAL_dbg_CCU_Info_Base_Cal +#define dbg_Info_ActivatedCAL_dbg_CCU_Info_Base_Cal (0) +#endif + + +// Value tables for @dbg_Info_CCU_Aroma_Cfg signal + +#ifndef dbg_Info_CCU_Aroma_Cfg_dbg_CCU_Info_Incomplete +#define dbg_Info_CCU_Aroma_Cfg_dbg_CCU_Info_Incomplete (15) +#endif + +#ifndef dbg_Info_CCU_Aroma_Cfg_dbg_CCU_Info_Present +#define dbg_Info_CCU_Aroma_Cfg_dbg_CCU_Info_Present (1) +#endif + +#ifndef dbg_Info_CCU_Aroma_Cfg_dbg_CCU_Info_Not_Present +#define dbg_Info_CCU_Aroma_Cfg_dbg_CCU_Info_Not_Present (0) +#endif + + +// Value tables for @dbg_Info_CCU_Algorithm_Cfg signal + +#ifndef dbg_Info_CCU_Algorithm_Cfg_dbg_CCU_Info_Incomplete +#define dbg_Info_CCU_Algorithm_Cfg_dbg_CCU_Info_Incomplete (15) +#endif + +#ifndef dbg_Info_CCU_Algorithm_Cfg_dbg_CCU_Info_Limousine_Variant +#define dbg_Info_CCU_Algorithm_Cfg_dbg_CCU_Info_Limousine_Variant (1) +#endif + +#ifndef dbg_Info_CCU_Algorithm_Cfg_dbg_CCU_Info_Stadard_Variant +#define dbg_Info_CCU_Algorithm_Cfg_dbg_CCU_Info_Stadard_Variant (0) +#endif + + +// Value tables for @dbg_Info_VehicleBody signal + +#ifndef dbg_Info_VehicleBody_dbg_CCU_Info_MPVTabletka_29 +#define dbg_Info_VehicleBody_dbg_CCU_Info_MPVTabletka_29 (12857) +#endif + +#ifndef dbg_Info_VehicleBody_dbg_CCU_Info_MPVOrbita_28 +#define dbg_Info_VehicleBody_dbg_CCU_Info_MPVOrbita_28 (12856) +#endif + +#ifndef dbg_Info_VehicleBody_dbg_CCU_Info_MPVArmored4SEAT_27 +#define dbg_Info_VehicleBody_dbg_CCU_Info_MPVArmored4SEAT_27 (12855) +#endif + +#ifndef dbg_Info_VehicleBody_dbg_CCU_Info_MPVArmored9SEAT_23 +#define dbg_Info_VehicleBody_dbg_CCU_Info_MPVArmored9SEAT_23 (12851) +#endif + +#ifndef dbg_Info_VehicleBody_dbg_CCU_Info_MPVNonArmored9SEAT_22 +#define dbg_Info_VehicleBody_dbg_CCU_Info_MPVNonArmored9SEAT_22 (12850) +#endif + +#ifndef dbg_Info_VehicleBody_dbg_CCU_Info_MPVArmored8SEAT_21 +#define dbg_Info_VehicleBody_dbg_CCU_Info_MPVArmored8SEAT_21 (12849) +#endif + +#ifndef dbg_Info_VehicleBody_dbg_CCU_Info_MPVNonArmored4SEAT_20 +#define dbg_Info_VehicleBody_dbg_CCU_Info_MPVNonArmored4SEAT_20 (12848) +#endif + +#ifndef dbg_Info_VehicleBody_dbg_CCU_Info_SUVArmored__13 +#define dbg_Info_VehicleBody_dbg_CCU_Info_SUVArmored__13 (12595) +#endif + +#ifndef dbg_Info_VehicleBody_dbg_CCU_Info_SUVNonArmored_12 +#define dbg_Info_VehicleBody_dbg_CCU_Info_SUVNonArmored_12 (12594) +#endif + +#ifndef dbg_Info_VehicleBody_dbg_CCU_Info_LimoArmoredV8CiVil_0C_NotUsed +#define dbg_Info_VehicleBody_dbg_CCU_Info_LimoArmoredV8CiVil_0C_NotUsed (12355) +#endif + +#ifndef dbg_Info_VehicleBody_dbg_CCU_Info_CabrioShow_0B_NotUsed_Phase1 +#define dbg_Info_VehicleBody_dbg_CCU_Info_CabrioShow_0B_NotUsed_Phase1 (12354) +#endif + +#ifndef dbg_Info_VehicleBody_dbg_CCU_Info_SedanLongArmored_0A +#define dbg_Info_VehicleBody_dbg_CCU_Info_SedanLongArmored_0A (12353) +#endif + +#ifndef dbg_Info_VehicleBody_dbg_CCU_Info_SedanLong__09 +#define dbg_Info_VehicleBody_dbg_CCU_Info_SedanLong__09 (12345) +#endif + +#ifndef dbg_Info_VehicleBody_dbg_CCU_Info_Sedan4x2__08_NotUsed_Phase1 +#define dbg_Info_VehicleBody_dbg_CCU_Info_Sedan4x2__08_NotUsed_Phase1 (12344) +#endif + +#ifndef dbg_Info_VehicleBody_dbg_CCU_Info_Cabrio_05 +#define dbg_Info_VehicleBody_dbg_CCU_Info_Cabrio_05 (12341) +#endif + +#ifndef dbg_Info_VehicleBody_dbg_CCU_Info_LimoArmoredV8_04 +#define dbg_Info_VehicleBody_dbg_CCU_Info_LimoArmoredV8_04 (12340) +#endif + +#ifndef dbg_Info_VehicleBody_dbg_CCU_Info_LimoArmoredV12_03 +#define dbg_Info_VehicleBody_dbg_CCU_Info_LimoArmoredV12_03 (12339) +#endif + +#ifndef dbg_Info_VehicleBody_dbg_CCU_Info_SedanArmored__01 +#define dbg_Info_VehicleBody_dbg_CCU_Info_SedanArmored__01 (12337) +#endif + +#ifndef dbg_Info_VehicleBody_dbg_CCU_Info_SedanNonArmored00 +#define dbg_Info_VehicleBody_dbg_CCU_Info_SedanNonArmored00 (12336) +#endif + + +typedef struct +{ +#ifdef CANDB_DBG_USE_BITS_SIGNAL + + // MULTIPLEX master signal + uint8_t dbg_Info_MultMsg_Idx : 2; // Bits= 2 + + // multiplex variable + uint32_t dbg_Info_Calibration_Ver_Date; // Bits=22 Unit:'yymmdd' + + // multiplex variable + uint32_t dbg_Info_CCU_SW_Ver_Date; // Bits=22 Unit:'yymmdd' + + // multiplex variable + uint8_t dbg_Info_Calibration_Ver_Rev; // Bits= 8 Unit:'Rev.' + + // multiplex variable + uint8_t dbg_Info_CCU_SW_Ver_Rev; // Bits= 8 Unit:'Rev.' + + // 5 : "MPV_Cal" + // 4 : "SUV_Cal" + // 3 : "Limo_Cal" + // 2 : "SedanH_Cal" + // 1 : "SedanL_Cal" + // 0 : "Base_Cal" + // multiplex variable + uint8_t dbg_Info_ActivatedCAL : 4; // Bits= 4 Unit:'Num' + + // multiplex variable + uint32_t dbg_Info_MBD_Ver_Date; // Bits=22 Unit:'yymmdd' + + // 15 : "Incomplete" + // 1 : "Present" + // 0 : "Not_Present" + // multiplex variable + uint8_t dbg_Info_CCU_Aroma_Cfg : 4; // Bits= 4 + + // 15 : "Incomplete" + // 1 : "Limousine_Variant" + // 0 : "Stadard_Variant" + // multiplex variable + uint8_t dbg_Info_CCU_Algorithm_Cfg : 4; // Bits= 4 + + // 12857 : "MPVTabletka ='29'" + // 12856 : "MPVOrbita ='28'" + // 12855 : "MPVArmored4SEAT ='27'" + // 12851 : "MPVArmored9SEAT ='23'" + // 12850 : "MPVNonArmored9SEAT ='22'" + // 12849 : "MPVArmored8SEAT ='21'" + // 12848 : "MPVNonArmored4SEAT ='20'" + // 12595 : "SUVArmored = '13'" + // 12594 : "SUVNonArmored ='12'" + // 12355 : "LimoArmoredV8CiVil ='0C'_NotUsed" + // 12354 : "CabrioShow ='0B'_NotUsed_Phase1" + // 12353 : "SedanLongArmored ='0A'" + // 12345 : "SedanLong = '09'" + // 12344 : "Sedan4x2 = '08'_NotUsed_Phase1" + // 12341 : "Cabrio ='05'" + // 12340 : "LimoArmoredV8 ='04'" + // 12339 : "LimoArmoredV12 ='03'" + // 12337 : "SedanArmored = '01'" + // 12336 : "SedanNonArmored='00'" + // multiplex variable + uint16_t dbg_Info_VehicleBody; // Bits=16 Unit:'Vehicle' + + // multiplex variable + uint8_t dbg_Info_MBD_Ver_Rev; // Bits= 8 Unit:'Rev.' + +#else + + // MULTIPLEX master signal + uint8_t dbg_Info_MultMsg_Idx; // Bits= 2 + + // multiplex variable + uint32_t dbg_Info_Calibration_Ver_Date; // Bits=22 Unit:'yymmdd' + + // multiplex variable + uint32_t dbg_Info_CCU_SW_Ver_Date; // Bits=22 Unit:'yymmdd' + + // multiplex variable + uint8_t dbg_Info_Calibration_Ver_Rev; // Bits= 8 Unit:'Rev.' + + // multiplex variable + uint8_t dbg_Info_CCU_SW_Ver_Rev; // Bits= 8 Unit:'Rev.' + + // 5 : "MPV_Cal" + // 4 : "SUV_Cal" + // 3 : "Limo_Cal" + // 2 : "SedanH_Cal" + // 1 : "SedanL_Cal" + // 0 : "Base_Cal" + // multiplex variable + uint8_t dbg_Info_ActivatedCAL; // Bits= 4 Unit:'Num' + + // multiplex variable + uint32_t dbg_Info_MBD_Ver_Date; // Bits=22 Unit:'yymmdd' + + // 15 : "Incomplete" + // 1 : "Present" + // 0 : "Not_Present" + // multiplex variable + uint8_t dbg_Info_CCU_Aroma_Cfg; // Bits= 4 + + // 15 : "Incomplete" + // 1 : "Limousine_Variant" + // 0 : "Stadard_Variant" + // multiplex variable + uint8_t dbg_Info_CCU_Algorithm_Cfg; // Bits= 4 + + // 12857 : "MPVTabletka ='29'" + // 12856 : "MPVOrbita ='28'" + // 12855 : "MPVArmored4SEAT ='27'" + // 12851 : "MPVArmored9SEAT ='23'" + // 12850 : "MPVNonArmored9SEAT ='22'" + // 12849 : "MPVArmored8SEAT ='21'" + // 12848 : "MPVNonArmored4SEAT ='20'" + // 12595 : "SUVArmored = '13'" + // 12594 : "SUVNonArmored ='12'" + // 12355 : "LimoArmoredV8CiVil ='0C'_NotUsed" + // 12354 : "CabrioShow ='0B'_NotUsed_Phase1" + // 12353 : "SedanLongArmored ='0A'" + // 12345 : "SedanLong = '09'" + // 12344 : "Sedan4x2 = '08'_NotUsed_Phase1" + // 12341 : "Cabrio ='05'" + // 12340 : "LimoArmoredV8 ='04'" + // 12339 : "LimoArmoredV12 ='03'" + // 12337 : "SedanArmored = '01'" + // 12336 : "SedanNonArmored='00'" + // multiplex variable + uint16_t dbg_Info_VehicleBody; // Bits=16 Unit:'Vehicle' + + // multiplex variable + uint8_t dbg_Info_MBD_Ver_Rev; // Bits= 8 Unit:'Rev.' + +#endif // CANDB_DBG_USE_BITS_SIGNAL + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_DBG_USE_DIAG_MONITORS + +} dbg_CCU_Info_t; + +// def @dbg_Drs CAN Message (1021 0x3fd) +#define dbg_Drs_IDE (0U) +#define dbg_Drs_DLC (8U) +#define dbg_Drs_CANID (0x3fdU) + +typedef struct +{ +#ifdef CANDB_DBG_USE_BITS_SIGNAL + + uint8_t dbg_Drs_0_SFL_DL : 7; // Bits= 7 Unit:'%' + + uint8_t dbg_Drs_1_CFL_FPL : 7; // Bits= 7 Unit:'%' + + uint8_t dbg_Drs_2_CFR_FPR : 7; // Bits= 7 Unit:'%' + + uint8_t dbg_Drs_3_SFR_DR : 7; // Bits= 7 Unit:'%' + + uint8_t dbg_Drs_4_SRL_RLB : 7; // Bits= 7 Unit:'%' + + uint8_t dbg_Drs_5_CRL_FCL : 7; // Bits= 7 Unit:'%' + + uint8_t dbg_Drs_6_CRR_FCR : 7; // Bits= 7 Unit:'%' + + uint8_t dbg_Drs_7_SRR_RRB : 7; // Bits= 7 Unit:'%' + +#else + + uint8_t dbg_Drs_0_SFL_DL; // Bits= 7 Unit:'%' + + uint8_t dbg_Drs_1_CFL_FPL; // Bits= 7 Unit:'%' + + uint8_t dbg_Drs_2_CFR_FPR; // Bits= 7 Unit:'%' + + uint8_t dbg_Drs_3_SFR_DR; // Bits= 7 Unit:'%' + + uint8_t dbg_Drs_4_SRL_RLB; // Bits= 7 Unit:'%' + + uint8_t dbg_Drs_5_CRL_FCL; // Bits= 7 Unit:'%' + + uint8_t dbg_Drs_6_CRR_FCR; // Bits= 7 Unit:'%' + + uint8_t dbg_Drs_7_SRR_RRB; // Bits= 7 Unit:'%' + +#endif // CANDB_DBG_USE_BITS_SIGNAL + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_DBG_USE_DIAG_MONITORS + +} dbg_Drs_t; + +// def @dbg_Sen_Incar CAN Message (1023 0x3ff) +#define dbg_Sen_Incar_IDE (0U) +#define dbg_Sen_Incar_DLC (8U) +#define dbg_Sen_Incar_CANID (0x3ffU) +#define dbg_Sen_Incar_CYC (250U) +// signal: @dbg_Sen_Incar_Raw_FL_ro +#define CANDB_DBG_dbg_Sen_Incar_Raw_FL_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Sen_Incar_Raw_FL_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Sen_Incar_Raw_FL_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Sen_Incar_FL_ro +#define CANDB_DBG_dbg_Sen_Incar_FL_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Sen_Incar_FL_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Sen_Incar_FL_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Sen_Incar_Raw_FR_ro +#define CANDB_DBG_dbg_Sen_Incar_Raw_FR_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Sen_Incar_Raw_FR_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Sen_Incar_Raw_FR_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Sen_Incar_FR_ro +#define CANDB_DBG_dbg_Sen_Incar_FR_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Sen_Incar_FR_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Sen_Incar_FR_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Sen_Incar_Raw_RL_ro +#define CANDB_DBG_dbg_Sen_Incar_Raw_RL_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Sen_Incar_Raw_RL_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Sen_Incar_Raw_RL_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Sen_Incar_RL_ro +#define CANDB_DBG_dbg_Sen_Incar_RL_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Sen_Incar_RL_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Sen_Incar_RL_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Sen_Incar_Raw_RR_ro +#define CANDB_DBG_dbg_Sen_Incar_Raw_RR_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Sen_Incar_Raw_RR_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Sen_Incar_Raw_RR_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Sen_Incar_RR_ro +#define CANDB_DBG_dbg_Sen_Incar_RR_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Sen_Incar_RR_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Sen_Incar_RR_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_DBG_USE_BITS_SIGNAL + + // MULTIPLEX master signal + uint8_t dbg_Sen_Incar_MultMsg_Idx : 2; // Bits= 2 + + // multiplex variable + int16_t dbg_Sen_Incar_Raw_FL_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Incar_Raw_FL_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Incar_FL_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Incar_FL_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Incar_Raw_FR_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Incar_Raw_FR_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Incar_FR_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Incar_FR_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Incar_Raw_RL_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Incar_Raw_RL_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Incar_RL_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Incar_RL_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Incar_Raw_RR_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Incar_Raw_RR_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Incar_RR_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Incar_RR_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + +#else + + // MULTIPLEX master signal + uint8_t dbg_Sen_Incar_MultMsg_Idx; // Bits= 2 + + // multiplex variable + int16_t dbg_Sen_Incar_Raw_FL_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Incar_Raw_FL_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Incar_FL_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Incar_FL_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Incar_Raw_FR_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Incar_Raw_FR_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Incar_FR_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Incar_FR_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Incar_Raw_RL_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Incar_Raw_RL_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Incar_RL_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Incar_RL_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Incar_Raw_RR_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Incar_Raw_RR_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Incar_RR_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Incar_RR_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + +#endif // CANDB_DBG_USE_BITS_SIGNAL + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_DBG_USE_DIAG_MONITORS + +} dbg_Sen_Incar_t; + +// def @dbg_Cmd_Act_Information CAN Message (1024 0x400) +#define dbg_Cmd_Act_Information_IDE (0U) +#define dbg_Cmd_Act_Information_DLC (8U) +#define dbg_Cmd_Act_Information_CANID (0x400U) + +// Value tables for @Cmd_Target_Act_Index signal + +#ifndef Cmd_Target_Act_Index_dbg_Cmd_Act_Information_AutoChange +#define Cmd_Target_Act_Index_dbg_Cmd_Act_Information_AutoChange (63) +#endif + +#ifndef Cmd_Target_Act_Index_dbg_Cmd_Act_Information__SealingValve +#define Cmd_Target_Act_Index_dbg_Cmd_Act_Information__SealingValve (23) +#endif + +#ifndef Cmd_Target_Act_Index_dbg_Cmd_Act_Information__OSA +#define Cmd_Target_Act_Index_dbg_Cmd_Act_Information__OSA (22) +#endif + +#ifndef Cmd_Target_Act_Index_dbg_Cmd_Act_Information__Rec +#define Cmd_Target_Act_Index_dbg_Cmd_Act_Information__Rec (21) +#endif + +#ifndef Cmd_Target_Act_Index_dbg_Cmd_Act_Information__Temp_RR +#define Cmd_Target_Act_Index_dbg_Cmd_Act_Information__Temp_RR (20) +#endif + +#ifndef Cmd_Target_Act_Index_dbg_Cmd_Act_Information__Temp_RL +#define Cmd_Target_Act_Index_dbg_Cmd_Act_Information__Temp_RL (19) +#endif + +#ifndef Cmd_Target_Act_Index_dbg_Cmd_Act_Information__TempL_FR +#define Cmd_Target_Act_Index_dbg_Cmd_Act_Information__TempL_FR (18) +#endif + +#ifndef Cmd_Target_Act_Index_dbg_Cmd_Act_Information__TempU_FR +#define Cmd_Target_Act_Index_dbg_Cmd_Act_Information__TempU_FR (17) +#endif + +#ifndef Cmd_Target_Act_Index_dbg_Cmd_Act_Information__TempL_FL +#define Cmd_Target_Act_Index_dbg_Cmd_Act_Information__TempL_FL (16) +#endif + +#ifndef Cmd_Target_Act_Index_dbg_Cmd_Act_Information__TempU_FL +#define Cmd_Target_Act_Index_dbg_Cmd_Act_Information__TempU_FL (15) +#endif + +#ifndef Cmd_Target_Act_Index_dbg_Cmd_Act_Information__Foot_RR +#define Cmd_Target_Act_Index_dbg_Cmd_Act_Information__Foot_RR (14) +#endif + +#ifndef Cmd_Target_Act_Index_dbg_Cmd_Act_Information__Vent_SRR +#define Cmd_Target_Act_Index_dbg_Cmd_Act_Information__Vent_SRR (13) +#endif + +#ifndef Cmd_Target_Act_Index_dbg_Cmd_Act_Information__Vent_CRR +#define Cmd_Target_Act_Index_dbg_Cmd_Act_Information__Vent_CRR (12) +#endif + +#ifndef Cmd_Target_Act_Index_dbg_Cmd_Act_Information__Foot_RL +#define Cmd_Target_Act_Index_dbg_Cmd_Act_Information__Foot_RL (11) +#endif + +#ifndef Cmd_Target_Act_Index_dbg_Cmd_Act_Information__Vent_CRL +#define Cmd_Target_Act_Index_dbg_Cmd_Act_Information__Vent_CRL (10) +#endif + +#ifndef Cmd_Target_Act_Index_dbg_Cmd_Act_Information__Vent_SRL +#define Cmd_Target_Act_Index_dbg_Cmd_Act_Information__Vent_SRL (9) +#endif + +#ifndef Cmd_Target_Act_Index_dbg_Cmd_Act_Information__Foot_2FR +#define Cmd_Target_Act_Index_dbg_Cmd_Act_Information__Foot_2FR (8) +#endif + +#ifndef Cmd_Target_Act_Index_dbg_Cmd_Act_Information__Foot_1FR +#define Cmd_Target_Act_Index_dbg_Cmd_Act_Information__Foot_1FR (7) +#endif + +#ifndef Cmd_Target_Act_Index_dbg_Cmd_Act_Information__Vent_SFR +#define Cmd_Target_Act_Index_dbg_Cmd_Act_Information__Vent_SFR (6) +#endif + +#ifndef Cmd_Target_Act_Index_dbg_Cmd_Act_Information__Vent_CFR +#define Cmd_Target_Act_Index_dbg_Cmd_Act_Information__Vent_CFR (5) +#endif + +#ifndef Cmd_Target_Act_Index_dbg_Cmd_Act_Information__Foot_2FL +#define Cmd_Target_Act_Index_dbg_Cmd_Act_Information__Foot_2FL (4) +#endif + +#ifndef Cmd_Target_Act_Index_dbg_Cmd_Act_Information__Foot_1FL +#define Cmd_Target_Act_Index_dbg_Cmd_Act_Information__Foot_1FL (3) +#endif + +#ifndef Cmd_Target_Act_Index_dbg_Cmd_Act_Information__Vent_CFL +#define Cmd_Target_Act_Index_dbg_Cmd_Act_Information__Vent_CFL (2) +#endif + +#ifndef Cmd_Target_Act_Index_dbg_Cmd_Act_Information__Vent_SFL +#define Cmd_Target_Act_Index_dbg_Cmd_Act_Information__Vent_SFL (1) +#endif + +#ifndef Cmd_Target_Act_Index_dbg_Cmd_Act_Information__Def +#define Cmd_Target_Act_Index_dbg_Cmd_Act_Information__Def (0) +#endif + + +typedef struct +{ +#ifdef CANDB_DBG_USE_BITS_SIGNAL + + // 63 : "AutoChange" + // 23 : "23_SealingValve" + // 22 : "22_OSA" + // 21 : "21_Rec" + // 20 : "20_Temp_RR" + // 19 : "19_Temp_RL" + // 18 : "18_TempL_FR" + // 17 : "17_TempU_FR" + // 16 : "16_TempL_FL" + // 15 : "15_TempU_FL" + // 14 : "14_Foot_RR" + // 13 : "13_Vent_SRR" + // 12 : "12_Vent_CRR" + // 11 : "11_Foot_RL" + // 10 : "10_Vent_CRL" + // 9 : "09_Vent_SRL" + // 8 : "08_Foot_2FR" + // 7 : "07_Foot_1FR" + // 6 : "06_Vent_SFR" + // 5 : "05_Vent_CFR" + // 4 : "04_Foot_2FL" + // 3 : "03_Foot_1FL" + // 2 : "02_Vent_CFL" + // 1 : "01_Vent_SFL" + // 0 : "00_Def" + uint8_t Cmd_Target_Act_Index : 6; // Bits= 6 Unit:'Index' + +#else + + // 63 : "AutoChange" + // 23 : "23_SealingValve" + // 22 : "22_OSA" + // 21 : "21_Rec" + // 20 : "20_Temp_RR" + // 19 : "19_Temp_RL" + // 18 : "18_TempL_FR" + // 17 : "17_TempU_FR" + // 16 : "16_TempL_FL" + // 15 : "15_TempU_FL" + // 14 : "14_Foot_RR" + // 13 : "13_Vent_SRR" + // 12 : "12_Vent_CRR" + // 11 : "11_Foot_RL" + // 10 : "10_Vent_CRL" + // 9 : "09_Vent_SRL" + // 8 : "08_Foot_2FR" + // 7 : "07_Foot_1FR" + // 6 : "06_Vent_SFR" + // 5 : "05_Vent_CFR" + // 4 : "04_Foot_2FL" + // 3 : "03_Foot_1FL" + // 2 : "02_Vent_CFL" + // 1 : "01_Vent_SFL" + // 0 : "00_Def" + uint8_t Cmd_Target_Act_Index; // Bits= 6 Unit:'Index' + +#endif // CANDB_DBG_USE_BITS_SIGNAL + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_DBG_USE_DIAG_MONITORS + +} dbg_Cmd_Act_Information_t; + +// def @dbg_Info_Act1 CAN Message (1025 0x401) +#define dbg_Info_Act1_IDE (0U) +#define dbg_Info_Act1_DLC (8U) +#define dbg_Info_Act1_CANID (0x401U) + +// Value tables for @dbg_Info_Act_Index signal + +#ifndef dbg_Info_Act_Index_dbg_Info_Act1__SealingValve +#define dbg_Info_Act_Index_dbg_Info_Act1__SealingValve (23) +#endif + +#ifndef dbg_Info_Act_Index_dbg_Info_Act1__OSA +#define dbg_Info_Act_Index_dbg_Info_Act1__OSA (22) +#endif + +#ifndef dbg_Info_Act_Index_dbg_Info_Act1__Rec +#define dbg_Info_Act_Index_dbg_Info_Act1__Rec (21) +#endif + +#ifndef dbg_Info_Act_Index_dbg_Info_Act1__Temp_RR +#define dbg_Info_Act_Index_dbg_Info_Act1__Temp_RR (20) +#endif + +#ifndef dbg_Info_Act_Index_dbg_Info_Act1__Temp_RL +#define dbg_Info_Act_Index_dbg_Info_Act1__Temp_RL (19) +#endif + +#ifndef dbg_Info_Act_Index_dbg_Info_Act1__TempL_FR +#define dbg_Info_Act_Index_dbg_Info_Act1__TempL_FR (18) +#endif + +#ifndef dbg_Info_Act_Index_dbg_Info_Act1__TempU_FR +#define dbg_Info_Act_Index_dbg_Info_Act1__TempU_FR (17) +#endif + +#ifndef dbg_Info_Act_Index_dbg_Info_Act1__TempL_FL +#define dbg_Info_Act_Index_dbg_Info_Act1__TempL_FL (16) +#endif + +#ifndef dbg_Info_Act_Index_dbg_Info_Act1__TempU_FL +#define dbg_Info_Act_Index_dbg_Info_Act1__TempU_FL (15) +#endif + +#ifndef dbg_Info_Act_Index_dbg_Info_Act1__Foot_RR +#define dbg_Info_Act_Index_dbg_Info_Act1__Foot_RR (14) +#endif + +#ifndef dbg_Info_Act_Index_dbg_Info_Act1__Vent_SRR +#define dbg_Info_Act_Index_dbg_Info_Act1__Vent_SRR (13) +#endif + +#ifndef dbg_Info_Act_Index_dbg_Info_Act1__Vent_CRR +#define dbg_Info_Act_Index_dbg_Info_Act1__Vent_CRR (12) +#endif + +#ifndef dbg_Info_Act_Index_dbg_Info_Act1__Foot_RL +#define dbg_Info_Act_Index_dbg_Info_Act1__Foot_RL (11) +#endif + +#ifndef dbg_Info_Act_Index_dbg_Info_Act1__Vent_CRL +#define dbg_Info_Act_Index_dbg_Info_Act1__Vent_CRL (10) +#endif + +#ifndef dbg_Info_Act_Index_dbg_Info_Act1__Vent_SRL +#define dbg_Info_Act_Index_dbg_Info_Act1__Vent_SRL (9) +#endif + +#ifndef dbg_Info_Act_Index_dbg_Info_Act1__Foot_2FR +#define dbg_Info_Act_Index_dbg_Info_Act1__Foot_2FR (8) +#endif + +#ifndef dbg_Info_Act_Index_dbg_Info_Act1__Foot_1FR +#define dbg_Info_Act_Index_dbg_Info_Act1__Foot_1FR (7) +#endif + +#ifndef dbg_Info_Act_Index_dbg_Info_Act1__Vent_SFR +#define dbg_Info_Act_Index_dbg_Info_Act1__Vent_SFR (6) +#endif + +#ifndef dbg_Info_Act_Index_dbg_Info_Act1__Vent_CFR +#define dbg_Info_Act_Index_dbg_Info_Act1__Vent_CFR (5) +#endif + +#ifndef dbg_Info_Act_Index_dbg_Info_Act1__Foot_2FL +#define dbg_Info_Act_Index_dbg_Info_Act1__Foot_2FL (4) +#endif + +#ifndef dbg_Info_Act_Index_dbg_Info_Act1__Foot_1FL +#define dbg_Info_Act_Index_dbg_Info_Act1__Foot_1FL (3) +#endif + +#ifndef dbg_Info_Act_Index_dbg_Info_Act1__Vent_CFL +#define dbg_Info_Act_Index_dbg_Info_Act1__Vent_CFL (2) +#endif + +#ifndef dbg_Info_Act_Index_dbg_Info_Act1__Vent_SFL +#define dbg_Info_Act_Index_dbg_Info_Act1__Vent_SFL (1) +#endif + +#ifndef dbg_Info_Act_Index_dbg_Info_Act1__Def +#define dbg_Info_Act_Index_dbg_Info_Act1__Def (0) +#endif + +// signal: @dbg_Info_Act_App_Percent_ro +#define CANDB_DBG_dbg_Info_Act_App_Percent_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Info_Act_App_Percent_ro_toS(x) ( (uint16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Info_Act_App_Percent_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Info_Act_with_Limit_Percent_ro +#define CANDB_DBG_dbg_Info_Act_with_Limit_Percent_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Info_Act_with_Limit_Percent_ro_toS(x) ( (uint16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Info_Act_with_Limit_Percent_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_DBG_USE_BITS_SIGNAL + + // 23 : "23_SealingValve" + // 22 : "22_OSA" + // 21 : "21_Rec" + // 20 : "20_Temp_RR" + // 19 : "19_Temp_RL" + // 18 : "18_TempL_FR" + // 17 : "17_TempU_FR" + // 16 : "16_TempL_FL" + // 15 : "15_TempU_FL" + // 14 : "14_Foot_RR" + // 13 : "13_Vent_SRR" + // 12 : "12_Vent_CRR" + // 11 : "11_Foot_RL" + // 10 : "10_Vent_CRL" + // 9 : "09_Vent_SRL" + // 8 : "08_Foot_2FR" + // 7 : "07_Foot_1FR" + // 6 : "06_Vent_SFR" + // 5 : "05_Vent_CFR" + // 4 : "04_Foot_2FL" + // 3 : "03_Foot_1FL" + // 2 : "02_Vent_CFL" + // 1 : "01_Vent_SFL" + // 0 : "00_Def" + uint8_t dbg_Info_Act_Index : 6; // Bits= 6 Unit:'Idx' + + uint16_t dbg_Info_Act_App_Percent_ro; // Bits=10 Factor= 0.1 Unit:'%' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Info_Act_App_Percent_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + uint16_t dbg_Info_Act_with_Limit_Percent_ro; // Bits=10 Factor= 0.1 Unit:'%' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Info_Act_with_Limit_Percent_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + uint16_t dbg_Info_Act_Current_Count; // Bits=12 Unit:'Count' + + uint16_t dbg_Info_Act_Range_Count; // Bits=12 Unit:'Count' + + uint16_t dbg_Info_Act_Default_Count; // Bits=12 Unit:'Count' + +#else + + // 23 : "23_SealingValve" + // 22 : "22_OSA" + // 21 : "21_Rec" + // 20 : "20_Temp_RR" + // 19 : "19_Temp_RL" + // 18 : "18_TempL_FR" + // 17 : "17_TempU_FR" + // 16 : "16_TempL_FL" + // 15 : "15_TempU_FL" + // 14 : "14_Foot_RR" + // 13 : "13_Vent_SRR" + // 12 : "12_Vent_CRR" + // 11 : "11_Foot_RL" + // 10 : "10_Vent_CRL" + // 9 : "09_Vent_SRL" + // 8 : "08_Foot_2FR" + // 7 : "07_Foot_1FR" + // 6 : "06_Vent_SFR" + // 5 : "05_Vent_CFR" + // 4 : "04_Foot_2FL" + // 3 : "03_Foot_1FL" + // 2 : "02_Vent_CFL" + // 1 : "01_Vent_SFL" + // 0 : "00_Def" + uint8_t dbg_Info_Act_Index; // Bits= 6 Unit:'Idx' + + uint16_t dbg_Info_Act_App_Percent_ro; // Bits=10 Factor= 0.1 Unit:'%' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Info_Act_App_Percent_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + uint16_t dbg_Info_Act_with_Limit_Percent_ro; // Bits=10 Factor= 0.1 Unit:'%' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Info_Act_with_Limit_Percent_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + uint16_t dbg_Info_Act_Current_Count; // Bits=12 Unit:'Count' + + uint16_t dbg_Info_Act_Range_Count; // Bits=12 Unit:'Count' + + uint16_t dbg_Info_Act_Default_Count; // Bits=12 Unit:'Count' + +#endif // CANDB_DBG_USE_BITS_SIGNAL + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_DBG_USE_DIAG_MONITORS + +} dbg_Info_Act1_t; + +// def @dbg_Info_Act2 CAN Message (1026 0x402) +#define dbg_Info_Act2_IDE (0U) +#define dbg_Info_Act2_DLC (8U) +#define dbg_Info_Act2_CANID (0x402U) + +typedef struct +{ +#ifdef CANDB_DBG_USE_BITS_SIGNAL + + uint8_t dbg_Info_Act_Msg_Missing_Flag : 1; // Bits= 1 Unit:'(clear 0, set 1)' + + uint8_t dbg_Info_Act_Internal_Fail_Flag : 1; // Bits= 1 Unit:'(clear 0, set 1)' + + uint8_t dbg_Info_Act_Homing_Err_Flag : 1; // Bits= 1 Unit:'(clear 0, set 1)' + + uint8_t dbg_Info_Act_Range_Err_Flag : 1; // Bits= 1 Unit:'(clear 0, set 1)' + + uint8_t dbg_Info_Act_Range_Fail_Flag : 1; // Bits= 1 Unit:'(clear 0, set 1)' + + uint8_t dbg_Info_Act_Range_Err_Operation : 1; // Bits= 1 Unit:'(clear 0, set 1)' + + uint8_t dbg_Info_Act_Range_Err_Check_Cnt; // Bits= 8 Unit:'count' + + uint16_t dbg_Info_Act_Range_Err_Timer; // Bits=10 Unit:'sec' + +#else + + uint8_t dbg_Info_Act_Msg_Missing_Flag; // Bits= 1 Unit:'(clear 0, set 1)' + + uint8_t dbg_Info_Act_Internal_Fail_Flag; // Bits= 1 Unit:'(clear 0, set 1)' + + uint8_t dbg_Info_Act_Homing_Err_Flag; // Bits= 1 Unit:'(clear 0, set 1)' + + uint8_t dbg_Info_Act_Range_Err_Flag; // Bits= 1 Unit:'(clear 0, set 1)' + + uint8_t dbg_Info_Act_Range_Fail_Flag; // Bits= 1 Unit:'(clear 0, set 1)' + + uint8_t dbg_Info_Act_Range_Err_Operation; // Bits= 1 Unit:'(clear 0, set 1)' + + uint8_t dbg_Info_Act_Range_Err_Check_Cnt; // Bits= 8 Unit:'count' + + uint16_t dbg_Info_Act_Range_Err_Timer; // Bits=10 Unit:'sec' + +#endif // CANDB_DBG_USE_BITS_SIGNAL + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_DBG_USE_DIAG_MONITORS + +} dbg_Info_Act2_t; + +// def @dbg_Sen_Eva CAN Message (1284 0x504) +#define dbg_Sen_Eva_IDE (0U) +#define dbg_Sen_Eva_DLC (8U) +#define dbg_Sen_Eva_CANID (0x504U) +// signal: @dbg_Sen_Eva_Target_ro +#define CANDB_DBG_dbg_Sen_Eva_Target_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Sen_Eva_Target_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Sen_Eva_Target_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Sen_Eva_Diff_FrontRear_ro +#define CANDB_DBG_dbg_Sen_Eva_Diff_FrontRear_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Sen_Eva_Diff_FrontRear_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Sen_Eva_Diff_FrontRear_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Sen_Eva_F_ro +#define CANDB_DBG_dbg_Sen_Eva_F_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Sen_Eva_F_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Sen_Eva_F_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Sen_Eva_R_ro +#define CANDB_DBG_dbg_Sen_Eva_R_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Sen_Eva_R_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Sen_Eva_R_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_DBG_USE_BITS_SIGNAL + + int16_t dbg_Sen_Eva_Target_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Eva_Target_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + int16_t dbg_Sen_Eva_Diff_FrontRear_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Eva_Diff_FrontRear_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + int16_t dbg_Sen_Eva_F_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Eva_F_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + int16_t dbg_Sen_Eva_R_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Eva_R_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + +#else + + int16_t dbg_Sen_Eva_Target_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Eva_Target_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + int16_t dbg_Sen_Eva_Diff_FrontRear_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Eva_Diff_FrontRear_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + int16_t dbg_Sen_Eva_F_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Eva_F_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + int16_t dbg_Sen_Eva_R_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Eva_R_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + +#endif // CANDB_DBG_USE_BITS_SIGNAL + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_DBG_USE_DIAG_MONITORS + +} dbg_Sen_Eva_t; + +// def @dbg_Sen_Duct CAN Message (1285 0x505) +#define dbg_Sen_Duct_IDE (0U) +#define dbg_Sen_Duct_DLC (8U) +#define dbg_Sen_Duct_CANID (0x505U) +#define dbg_Sen_Duct_CYC (250U) + +// Value tables for @dbg_Sen_Duct_MultMsg_Idx signal + +#ifndef dbg_Sen_Duct_MultMsg_Idx_dbg_Sen_Duct_RR +#define dbg_Sen_Duct_MultMsg_Idx_dbg_Sen_Duct_RR (3) +#endif + +#ifndef dbg_Sen_Duct_MultMsg_Idx_dbg_Sen_Duct_RL +#define dbg_Sen_Duct_MultMsg_Idx_dbg_Sen_Duct_RL (2) +#endif + +#ifndef dbg_Sen_Duct_MultMsg_Idx_dbg_Sen_Duct_FR +#define dbg_Sen_Duct_MultMsg_Idx_dbg_Sen_Duct_FR (1) +#endif + +#ifndef dbg_Sen_Duct_MultMsg_Idx_dbg_Sen_Duct_FL +#define dbg_Sen_Duct_MultMsg_Idx_dbg_Sen_Duct_FL (0) +#endif + + +// Value tables for @dbg_Sen_Duct_FL_Fb_Select signal + +#ifndef dbg_Sen_Duct_FL_Fb_Select_dbg_Sen_Duct_Side +#define dbg_Sen_Duct_FL_Fb_Select_dbg_Sen_Duct_Side (1) +#endif + +#ifndef dbg_Sen_Duct_FL_Fb_Select_dbg_Sen_Duct_Central +#define dbg_Sen_Duct_FL_Fb_Select_dbg_Sen_Duct_Central (0) +#endif + + +// Value tables for @dbg_Sen_Duct_RR_Fb_Select signal + +#ifndef dbg_Sen_Duct_RR_Fb_Select_dbg_Sen_Duct_Side +#define dbg_Sen_Duct_RR_Fb_Select_dbg_Sen_Duct_Side (1) +#endif + +#ifndef dbg_Sen_Duct_RR_Fb_Select_dbg_Sen_Duct_Central +#define dbg_Sen_Duct_RR_Fb_Select_dbg_Sen_Duct_Central (0) +#endif + + +// Value tables for @dbg_Sen_Duct_RL_Fb_Select signal + +#ifndef dbg_Sen_Duct_RL_Fb_Select_dbg_Sen_Duct_Side +#define dbg_Sen_Duct_RL_Fb_Select_dbg_Sen_Duct_Side (1) +#endif + +#ifndef dbg_Sen_Duct_RL_Fb_Select_dbg_Sen_Duct_Central +#define dbg_Sen_Duct_RL_Fb_Select_dbg_Sen_Duct_Central (0) +#endif + + +// Value tables for @dbg_Sen_Duct_FR_Fb_Select signal + +#ifndef dbg_Sen_Duct_FR_Fb_Select_dbg_Sen_Duct_Side +#define dbg_Sen_Duct_FR_Fb_Select_dbg_Sen_Duct_Side (1) +#endif + +#ifndef dbg_Sen_Duct_FR_Fb_Select_dbg_Sen_Duct_Central +#define dbg_Sen_Duct_FR_Fb_Select_dbg_Sen_Duct_Central (0) +#endif + +// signal: @dbg_Sen_Duct_RL_Tgt_ro +#define CANDB_DBG_dbg_Sen_Duct_RL_Tgt_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Sen_Duct_RL_Tgt_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Sen_Duct_RL_Tgt_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Sen_Duct_FR_Upper_Tgt_ro +#define CANDB_DBG_dbg_Sen_Duct_FR_Upper_Tgt_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Sen_Duct_FR_Upper_Tgt_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Sen_Duct_FR_Upper_Tgt_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Sen_Duct_RR_Tgt_ro +#define CANDB_DBG_dbg_Sen_Duct_RR_Tgt_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Sen_Duct_RR_Tgt_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Sen_Duct_RR_Tgt_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Sen_Duct_FL_Upper_Tgt_ro +#define CANDB_DBG_dbg_Sen_Duct_FL_Upper_Tgt_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Sen_Duct_FL_Upper_Tgt_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Sen_Duct_FL_Upper_Tgt_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Sen_Duct_RR_Fb_ro +#define CANDB_DBG_dbg_Sen_Duct_RR_Fb_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Sen_Duct_RR_Fb_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Sen_Duct_RR_Fb_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Sen_Duct_RL_Fb_ro +#define CANDB_DBG_dbg_Sen_Duct_RL_Fb_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Sen_Duct_RL_Fb_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Sen_Duct_RL_Fb_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Sen_Duct_FR_Upper_Fb_ro +#define CANDB_DBG_dbg_Sen_Duct_FR_Upper_Fb_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Sen_Duct_FR_Upper_Fb_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Sen_Duct_FR_Upper_Fb_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Sen_Duct_FL_Upper_Fb_ro +#define CANDB_DBG_dbg_Sen_Duct_FL_Upper_Fb_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Sen_Duct_FL_Upper_Fb_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Sen_Duct_FL_Upper_Fb_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Sen_Duct_FR_Side_Fb_ro +#define CANDB_DBG_dbg_Sen_Duct_FR_Side_Fb_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Sen_Duct_FR_Side_Fb_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Sen_Duct_FR_Side_Fb_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Sen_Duct_FL_Side_Fb_ro +#define CANDB_DBG_dbg_Sen_Duct_FL_Side_Fb_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Sen_Duct_FL_Side_Fb_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Sen_Duct_FL_Side_Fb_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Sen_Duct_RL_Side_Fb_ro +#define CANDB_DBG_dbg_Sen_Duct_RL_Side_Fb_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Sen_Duct_RL_Side_Fb_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Sen_Duct_RL_Side_Fb_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Sen_Duct_RR_Side_Fb_ro +#define CANDB_DBG_dbg_Sen_Duct_RR_Side_Fb_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Sen_Duct_RR_Side_Fb_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Sen_Duct_RR_Side_Fb_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Sen_Duct_FR_Lower_Tgt_ro +#define CANDB_DBG_dbg_Sen_Duct_FR_Lower_Tgt_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Sen_Duct_FR_Lower_Tgt_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Sen_Duct_FR_Lower_Tgt_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Sen_Duct_FL_Lower_Tgt_ro +#define CANDB_DBG_dbg_Sen_Duct_FL_Lower_Tgt_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Sen_Duct_FL_Lower_Tgt_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Sen_Duct_FL_Lower_Tgt_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Sen_Duct_FR_Lower_Fb_ro +#define CANDB_DBG_dbg_Sen_Duct_FR_Lower_Fb_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Sen_Duct_FR_Lower_Fb_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Sen_Duct_FR_Lower_Fb_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Sen_Duct_FL_Lower_Fb_ro +#define CANDB_DBG_dbg_Sen_Duct_FL_Lower_Fb_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Sen_Duct_FL_Lower_Fb_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Sen_Duct_FL_Lower_Fb_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_DBG_USE_BITS_SIGNAL + + // 3 : "RR" + // 2 : "RL" + // 1 : "FR" + // 0 : "FL" + // MULTIPLEX master signal + uint8_t dbg_Sen_Duct_MultMsg_Idx : 2; // Bits= 2 + + // 1 : "Side" + // 0 : "Central" + // multiplex variable + uint8_t dbg_Sen_Duct_FL_Fb_Select : 1; // Bits= 1 Unit:'(central 0, side 1)' + + // 1 : "Side" + // 0 : "Central" + // multiplex variable + uint8_t dbg_Sen_Duct_RR_Fb_Select : 1; // Bits= 1 Unit:'(central 0, side 1)' + + // 1 : "Side" + // 0 : "Central" + // multiplex variable + uint8_t dbg_Sen_Duct_RL_Fb_Select : 1; // Bits= 1 Unit:'(central 0, side 1)' + + // 1 : "Side" + // 0 : "Central" + // multiplex variable + uint8_t dbg_Sen_Duct_FR_Fb_Select : 1; // Bits= 1 Unit:'(central 0, side 1)' + + // multiplex variable + int16_t dbg_Sen_Duct_RL_Tgt_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Duct_RL_Tgt_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Duct_FR_Upper_Tgt_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Duct_FR_Upper_Tgt_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Duct_RR_Tgt_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Duct_RR_Tgt_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Duct_FL_Upper_Tgt_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Duct_FL_Upper_Tgt_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Duct_RR_Fb_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Duct_RR_Fb_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Duct_RL_Fb_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Duct_RL_Fb_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Duct_FR_Upper_Fb_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Duct_FR_Upper_Fb_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Duct_FL_Upper_Fb_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Duct_FL_Upper_Fb_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Duct_FR_Side_Fb_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Duct_FR_Side_Fb_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Duct_FL_Side_Fb_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Duct_FL_Side_Fb_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Duct_RL_Side_Fb_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Duct_RL_Side_Fb_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Duct_RR_Side_Fb_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Duct_RR_Side_Fb_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Duct_FR_Lower_Tgt_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Duct_FR_Lower_Tgt_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Duct_FL_Lower_Tgt_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Duct_FL_Lower_Tgt_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Duct_FR_Lower_Fb_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Duct_FR_Lower_Fb_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Duct_FL_Lower_Fb_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Duct_FL_Lower_Fb_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + +#else + + // 3 : "RR" + // 2 : "RL" + // 1 : "FR" + // 0 : "FL" + // MULTIPLEX master signal + uint8_t dbg_Sen_Duct_MultMsg_Idx; // Bits= 2 + + // 1 : "Side" + // 0 : "Central" + // multiplex variable + uint8_t dbg_Sen_Duct_FL_Fb_Select; // Bits= 1 Unit:'(central 0, side 1)' + + // 1 : "Side" + // 0 : "Central" + // multiplex variable + uint8_t dbg_Sen_Duct_RR_Fb_Select; // Bits= 1 Unit:'(central 0, side 1)' + + // 1 : "Side" + // 0 : "Central" + // multiplex variable + uint8_t dbg_Sen_Duct_RL_Fb_Select; // Bits= 1 Unit:'(central 0, side 1)' + + // 1 : "Side" + // 0 : "Central" + // multiplex variable + uint8_t dbg_Sen_Duct_FR_Fb_Select; // Bits= 1 Unit:'(central 0, side 1)' + + // multiplex variable + int16_t dbg_Sen_Duct_RL_Tgt_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Duct_RL_Tgt_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Duct_FR_Upper_Tgt_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Duct_FR_Upper_Tgt_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Duct_RR_Tgt_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Duct_RR_Tgt_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Duct_FL_Upper_Tgt_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Duct_FL_Upper_Tgt_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Duct_RR_Fb_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Duct_RR_Fb_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Duct_RL_Fb_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Duct_RL_Fb_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Duct_FR_Upper_Fb_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Duct_FR_Upper_Fb_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Duct_FL_Upper_Fb_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Duct_FL_Upper_Fb_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Duct_FR_Side_Fb_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Duct_FR_Side_Fb_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Duct_FL_Side_Fb_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Duct_FL_Side_Fb_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Duct_RL_Side_Fb_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Duct_RL_Side_Fb_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Duct_RR_Side_Fb_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Duct_RR_Side_Fb_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Duct_FR_Lower_Tgt_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Duct_FR_Lower_Tgt_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Duct_FL_Lower_Tgt_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Duct_FL_Lower_Tgt_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Duct_FR_Lower_Fb_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Duct_FR_Lower_Fb_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Sen_Duct_FL_Lower_Fb_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_Duct_FL_Lower_Fb_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + +#endif // CANDB_DBG_USE_BITS_SIGNAL + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_DBG_USE_DIAG_MONITORS + +} dbg_Sen_Duct_t; + +// def @dbg_Sen_Demist CAN Message (1289 0x509) +#define dbg_Sen_Demist_IDE (0U) +#define dbg_Sen_Demist_DLC (6U) +#define dbg_Sen_Demist_CANID (0x509U) +// signal: @dbg_Sen_DewPoint_Diff_ro +#define CANDB_DBG_dbg_Sen_DewPoint_Diff_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Sen_DewPoint_Diff_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Sen_DewPoint_Diff_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Sen_WindShield_Humidity_ro +#define CANDB_DBG_dbg_Sen_WindShield_Humidity_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Sen_WindShield_Humidity_ro_toS(x) ( (uint16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Sen_WindShield_Humidity_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Sen_WindShield_Temp_ro +#define CANDB_DBG_dbg_Sen_WindShield_Temp_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Sen_WindShield_Temp_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Sen_WindShield_Temp_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_DBG_USE_BITS_SIGNAL + + int16_t dbg_Sen_DewPoint_Diff_ro; // [-] Bits=16 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_DewPoint_Diff_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + uint16_t dbg_Sen_WindShield_Humidity_ro; // Bits=10 Factor= 0.1 Unit:'%' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_WindShield_Humidity_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + int16_t dbg_Sen_WindShield_Temp_ro; // [-] Bits=16 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_WindShield_Temp_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + +#else + + int16_t dbg_Sen_DewPoint_Diff_ro; // [-] Bits=16 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_DewPoint_Diff_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + uint16_t dbg_Sen_WindShield_Humidity_ro; // Bits=10 Factor= 0.1 Unit:'%' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_WindShield_Humidity_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + int16_t dbg_Sen_WindShield_Temp_ro; // [-] Bits=16 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Sen_WindShield_Temp_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + +#endif // CANDB_DBG_USE_BITS_SIGNAL + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_DBG_USE_DIAG_MONITORS + +} dbg_Sen_Demist_t; + +// def @dbg_LIN_AirQS_Stat CAN Message (1296 0x510) +#define dbg_LIN_AirQS_Stat_IDE (0U) +#define dbg_LIN_AirQS_Stat_DLC (3U) +#define dbg_LIN_AirQS_Stat_CANID (0x510U) + +// Value tables for @LIN_AirQS_LinRespErr_Stat signal + +#ifndef LIN_AirQS_LinRespErr_Stat_dbg_LIN_AirQS_Stat_Error +#define LIN_AirQS_LinRespErr_Stat_dbg_LIN_AirQS_Stat_Error (1) +#endif + +#ifndef LIN_AirQS_LinRespErr_Stat_dbg_LIN_AirQS_Stat_No_Error +#define LIN_AirQS_LinRespErr_Stat_dbg_LIN_AirQS_Stat_No_Error (0) +#endif + + +// Value tables for @LIN_AirQualSen_Stat signal + +#ifndef LIN_AirQualSen_Stat_dbg_LIN_AirQS_Stat_Sensor_is_off_standby_mode +#define LIN_AirQualSen_Stat_dbg_LIN_AirQS_Stat_Sensor_is_off_standby_mode (2) +#endif + +#ifndef LIN_AirQualSen_Stat_dbg_LIN_AirQS_Stat_Sensor_is_on_active_mode +#define LIN_AirQualSen_Stat_dbg_LIN_AirQS_Stat_Sensor_is_on_active_mode (1) +#endif + +#ifndef LIN_AirQualSen_Stat_dbg_LIN_AirQS_Stat_Initializing +#define LIN_AirQualSen_Stat_dbg_LIN_AirQS_Stat_Initializing (0) +#endif + + +// Value tables for @LIN_AirQualSenCombined_Val signal + +#ifndef LIN_AirQualSenCombined_Val_dbg_LIN_AirQS_Stat_Low_air_quality_ +#define LIN_AirQualSenCombined_Val_dbg_LIN_AirQS_Stat_Low_air_quality_ (3) +#endif + +#ifndef LIN_AirQualSenCombined_Val_dbg_LIN_AirQS_Stat_Medium_air_quality +#define LIN_AirQualSenCombined_Val_dbg_LIN_AirQS_Stat_Medium_air_quality (2) +#endif + +#ifndef LIN_AirQualSenCombined_Val_dbg_LIN_AirQS_Stat_Hight_air_quality +#define LIN_AirQualSenCombined_Val_dbg_LIN_AirQS_Stat_Hight_air_quality (1) +#endif + +#ifndef LIN_AirQualSenCombined_Val_dbg_LIN_AirQS_Stat_No_Clean_air +#define LIN_AirQualSenCombined_Val_dbg_LIN_AirQS_Stat_No_Clean_air (0) +#endif + + +// Value tables for @LIN_AirQualSen_Error_Stat signal + +#ifndef LIN_AirQualSen_Error_Stat_dbg_LIN_AirQS_Stat_Component_malfunction +#define LIN_AirQualSen_Error_Stat_dbg_LIN_AirQS_Stat_Component_malfunction (3) +#endif + +#ifndef LIN_AirQualSen_Error_Stat_dbg_LIN_AirQS_Stat_Supply_chain_short +#define LIN_AirQualSen_Error_Stat_dbg_LIN_AirQS_Stat_Supply_chain_short (2) +#endif + +#ifndef LIN_AirQualSen_Error_Stat_dbg_LIN_AirQS_Stat_Supply_chain_break +#define LIN_AirQualSen_Error_Stat_dbg_LIN_AirQS_Stat_Supply_chain_break (1) +#endif + +#ifndef LIN_AirQualSen_Error_Stat_dbg_LIN_AirQS_Stat_No_error +#define LIN_AirQualSen_Error_Stat_dbg_LIN_AirQS_Stat_No_error (0) +#endif + + +// Value tables for @LIN_AirQualSenCOlvl_Val signal + +#ifndef LIN_AirQualSenCOlvl_Val_dbg_LIN_AirQS_Stat_Level_10_100_pollunion_ +#define LIN_AirQualSenCOlvl_Val_dbg_LIN_AirQS_Stat_Level_10_100_pollunion_ (10) +#endif + +#ifndef LIN_AirQualSenCOlvl_Val_dbg_LIN_AirQS_Stat_Level_9_90_pollunion_ +#define LIN_AirQualSenCOlvl_Val_dbg_LIN_AirQS_Stat_Level_9_90_pollunion_ (9) +#endif + +#ifndef LIN_AirQualSenCOlvl_Val_dbg_LIN_AirQS_Stat_Level_8_80_pollunion_ +#define LIN_AirQualSenCOlvl_Val_dbg_LIN_AirQS_Stat_Level_8_80_pollunion_ (8) +#endif + +#ifndef LIN_AirQualSenCOlvl_Val_dbg_LIN_AirQS_Stat_Level_7_70_pollunion_ +#define LIN_AirQualSenCOlvl_Val_dbg_LIN_AirQS_Stat_Level_7_70_pollunion_ (7) +#endif + +#ifndef LIN_AirQualSenCOlvl_Val_dbg_LIN_AirQS_Stat_Level_6_60_pollunion_ +#define LIN_AirQualSenCOlvl_Val_dbg_LIN_AirQS_Stat_Level_6_60_pollunion_ (6) +#endif + +#ifndef LIN_AirQualSenCOlvl_Val_dbg_LIN_AirQS_Stat_Level_5_50_pollunion +#define LIN_AirQualSenCOlvl_Val_dbg_LIN_AirQS_Stat_Level_5_50_pollunion (5) +#endif + +#ifndef LIN_AirQualSenCOlvl_Val_dbg_LIN_AirQS_Stat_Level_4_40_pollunion_ +#define LIN_AirQualSenCOlvl_Val_dbg_LIN_AirQS_Stat_Level_4_40_pollunion_ (4) +#endif + +#ifndef LIN_AirQualSenCOlvl_Val_dbg_LIN_AirQS_Stat_Level_3_30_pollunion +#define LIN_AirQualSenCOlvl_Val_dbg_LIN_AirQS_Stat_Level_3_30_pollunion (3) +#endif + +#ifndef LIN_AirQualSenCOlvl_Val_dbg_LIN_AirQS_Stat_Level_2_20_pollunion +#define LIN_AirQualSenCOlvl_Val_dbg_LIN_AirQS_Stat_Level_2_20_pollunion (2) +#endif + +#ifndef LIN_AirQualSenCOlvl_Val_dbg_LIN_AirQS_Stat_Level_1_10_pollunion_ +#define LIN_AirQualSenCOlvl_Val_dbg_LIN_AirQS_Stat_Level_1_10_pollunion_ (1) +#endif + +#ifndef LIN_AirQualSenCOlvl_Val_dbg_LIN_AirQS_Stat_Level_0_clean_air +#define LIN_AirQualSenCOlvl_Val_dbg_LIN_AirQS_Stat_Level_0_clean_air (0) +#endif + + +// Value tables for @LIN_AirQualSenNOxlvl_Val signal + +#ifndef LIN_AirQualSenNOxlvl_Val_dbg_LIN_AirQS_Stat_Level_10_100_pollunion_ +#define LIN_AirQualSenNOxlvl_Val_dbg_LIN_AirQS_Stat_Level_10_100_pollunion_ (10) +#endif + +#ifndef LIN_AirQualSenNOxlvl_Val_dbg_LIN_AirQS_Stat_Level_9_90_pollunion_ +#define LIN_AirQualSenNOxlvl_Val_dbg_LIN_AirQS_Stat_Level_9_90_pollunion_ (9) +#endif + +#ifndef LIN_AirQualSenNOxlvl_Val_dbg_LIN_AirQS_Stat_Level_8_80_pollunion_ +#define LIN_AirQualSenNOxlvl_Val_dbg_LIN_AirQS_Stat_Level_8_80_pollunion_ (8) +#endif + +#ifndef LIN_AirQualSenNOxlvl_Val_dbg_LIN_AirQS_Stat_Level_7_70_pollunion_ +#define LIN_AirQualSenNOxlvl_Val_dbg_LIN_AirQS_Stat_Level_7_70_pollunion_ (7) +#endif + +#ifndef LIN_AirQualSenNOxlvl_Val_dbg_LIN_AirQS_Stat_Level_6_60_pollunion_ +#define LIN_AirQualSenNOxlvl_Val_dbg_LIN_AirQS_Stat_Level_6_60_pollunion_ (6) +#endif + +#ifndef LIN_AirQualSenNOxlvl_Val_dbg_LIN_AirQS_Stat_Level_5_50_pollunion +#define LIN_AirQualSenNOxlvl_Val_dbg_LIN_AirQS_Stat_Level_5_50_pollunion (5) +#endif + +#ifndef LIN_AirQualSenNOxlvl_Val_dbg_LIN_AirQS_Stat_Level_4_40_pollunion_ +#define LIN_AirQualSenNOxlvl_Val_dbg_LIN_AirQS_Stat_Level_4_40_pollunion_ (4) +#endif + +#ifndef LIN_AirQualSenNOxlvl_Val_dbg_LIN_AirQS_Stat_Level_3_30_pollunion +#define LIN_AirQualSenNOxlvl_Val_dbg_LIN_AirQS_Stat_Level_3_30_pollunion (3) +#endif + +#ifndef LIN_AirQualSenNOxlvl_Val_dbg_LIN_AirQS_Stat_Level_2_20_pollunion +#define LIN_AirQualSenNOxlvl_Val_dbg_LIN_AirQS_Stat_Level_2_20_pollunion (2) +#endif + +#ifndef LIN_AirQualSenNOxlvl_Val_dbg_LIN_AirQS_Stat_Level_1_10_pollunion_ +#define LIN_AirQualSenNOxlvl_Val_dbg_LIN_AirQS_Stat_Level_1_10_pollunion_ (1) +#endif + +#ifndef LIN_AirQualSenNOxlvl_Val_dbg_LIN_AirQS_Stat_Level_0_clean_air +#define LIN_AirQualSenNOxlvl_Val_dbg_LIN_AirQS_Stat_Level_0_clean_air (0) +#endif + + +// Value tables for @LIN_AirQualSenNH3lvl_Val signal + +#ifndef LIN_AirQualSenNH3lvl_Val_dbg_LIN_AirQS_Stat_Level_10_100_pollunion_ +#define LIN_AirQualSenNH3lvl_Val_dbg_LIN_AirQS_Stat_Level_10_100_pollunion_ (10) +#endif + +#ifndef LIN_AirQualSenNH3lvl_Val_dbg_LIN_AirQS_Stat_Level_9_90_pollunion_ +#define LIN_AirQualSenNH3lvl_Val_dbg_LIN_AirQS_Stat_Level_9_90_pollunion_ (9) +#endif + +#ifndef LIN_AirQualSenNH3lvl_Val_dbg_LIN_AirQS_Stat_Level_8_80_pollunion_ +#define LIN_AirQualSenNH3lvl_Val_dbg_LIN_AirQS_Stat_Level_8_80_pollunion_ (8) +#endif + +#ifndef LIN_AirQualSenNH3lvl_Val_dbg_LIN_AirQS_Stat_Level_7_70_pollunion_ +#define LIN_AirQualSenNH3lvl_Val_dbg_LIN_AirQS_Stat_Level_7_70_pollunion_ (7) +#endif + +#ifndef LIN_AirQualSenNH3lvl_Val_dbg_LIN_AirQS_Stat_Level_6_60_pollunion_ +#define LIN_AirQualSenNH3lvl_Val_dbg_LIN_AirQS_Stat_Level_6_60_pollunion_ (6) +#endif + +#ifndef LIN_AirQualSenNH3lvl_Val_dbg_LIN_AirQS_Stat_Level_5_50_pollunion +#define LIN_AirQualSenNH3lvl_Val_dbg_LIN_AirQS_Stat_Level_5_50_pollunion (5) +#endif + +#ifndef LIN_AirQualSenNH3lvl_Val_dbg_LIN_AirQS_Stat_Level_4_40_pollunion_ +#define LIN_AirQualSenNH3lvl_Val_dbg_LIN_AirQS_Stat_Level_4_40_pollunion_ (4) +#endif + +#ifndef LIN_AirQualSenNH3lvl_Val_dbg_LIN_AirQS_Stat_Level_3_30_pollunion +#define LIN_AirQualSenNH3lvl_Val_dbg_LIN_AirQS_Stat_Level_3_30_pollunion (3) +#endif + +#ifndef LIN_AirQualSenNH3lvl_Val_dbg_LIN_AirQS_Stat_Level_2_20_pollunion +#define LIN_AirQualSenNH3lvl_Val_dbg_LIN_AirQS_Stat_Level_2_20_pollunion (2) +#endif + +#ifndef LIN_AirQualSenNH3lvl_Val_dbg_LIN_AirQS_Stat_Level_1_10_pollunion_ +#define LIN_AirQualSenNH3lvl_Val_dbg_LIN_AirQS_Stat_Level_1_10_pollunion_ (1) +#endif + +#ifndef LIN_AirQualSenNH3lvl_Val_dbg_LIN_AirQS_Stat_Level_0_clean_air +#define LIN_AirQualSenNH3lvl_Val_dbg_LIN_AirQS_Stat_Level_0_clean_air (0) +#endif + + +typedef struct +{ +#ifdef CANDB_DBG_USE_BITS_SIGNAL + + // 1 : "Error" + // 0 : "No_Error" + uint8_t LIN_AirQS_LinRespErr_Stat : 1; // Bits= 1 + + // 2 : "Sensor is off (standby mode)" + // 1 : "Sensor is on (active mode)" + // 0 : "Initializing" + uint8_t LIN_AirQualSen_Stat : 2; // Bits= 2 + + // 3 : "Low air quality " + // 2 : "Medium air quality" + // 1 : "Hight air quality" + // 0 : "No (Clean air)" + uint8_t LIN_AirQualSenCombined_Val : 2; // Bits= 2 + + // 3 : "Component malfunction" + // 2 : "Supply chain short" + // 1 : "Supply chain break" + // 0 : "No error" + uint8_t LIN_AirQualSen_Error_Stat : 2; // Bits= 2 + + // 10 : "Level 10 (100% pollunion) " + // 9 : "Level 9 (90% pollunion) " + // 8 : "Level 8 (80% pollunion) " + // 7 : "Level 7 (70% pollunion) " + // 6 : "Level 6 (60% pollunion) " + // 5 : "Level 5 (50% pollunion)" + // 4 : "Level 4 (40% pollunion) " + // 3 : "Level 3 (30% pollunion)" + // 2 : "Level 2 (20% pollunion)" + // 1 : "Level 1 (10% pollunion) " + // 0 : "Level 0 (clean air)" + uint8_t LIN_AirQualSenCOlvl_Val : 4; // Bits= 4 + + // 10 : "Level 10 (100% pollunion) " + // 9 : "Level 9 (90% pollunion) " + // 8 : "Level 8 (80% pollunion) " + // 7 : "Level 7 (70% pollunion) " + // 6 : "Level 6 (60% pollunion) " + // 5 : "Level 5 (50% pollunion)" + // 4 : "Level 4 (40% pollunion) " + // 3 : "Level 3 (30% pollunion)" + // 2 : "Level 2 (20% pollunion)" + // 1 : "Level 1 (10% pollunion) " + // 0 : "Level 0 (clean air)" + uint8_t LIN_AirQualSenNOxlvl_Val : 4; // Bits= 4 + + // 10 : "Level 10 (100% pollunion) " + // 9 : "Level 9 (90% pollunion) " + // 8 : "Level 8 (80% pollunion) " + // 7 : "Level 7 (70% pollunion) " + // 6 : "Level 6 (60% pollunion) " + // 5 : "Level 5 (50% pollunion)" + // 4 : "Level 4 (40% pollunion) " + // 3 : "Level 3 (30% pollunion)" + // 2 : "Level 2 (20% pollunion)" + // 1 : "Level 1 (10% pollunion) " + // 0 : "Level 0 (clean air)" + uint8_t LIN_AirQualSenNH3lvl_Val : 4; // Bits= 4 + +#else + + // 1 : "Error" + // 0 : "No_Error" + uint8_t LIN_AirQS_LinRespErr_Stat; // Bits= 1 + + // 2 : "Sensor is off (standby mode)" + // 1 : "Sensor is on (active mode)" + // 0 : "Initializing" + uint8_t LIN_AirQualSen_Stat; // Bits= 2 + + // 3 : "Low air quality " + // 2 : "Medium air quality" + // 1 : "Hight air quality" + // 0 : "No (Clean air)" + uint8_t LIN_AirQualSenCombined_Val; // Bits= 2 + + // 3 : "Component malfunction" + // 2 : "Supply chain short" + // 1 : "Supply chain break" + // 0 : "No error" + uint8_t LIN_AirQualSen_Error_Stat; // Bits= 2 + + // 10 : "Level 10 (100% pollunion) " + // 9 : "Level 9 (90% pollunion) " + // 8 : "Level 8 (80% pollunion) " + // 7 : "Level 7 (70% pollunion) " + // 6 : "Level 6 (60% pollunion) " + // 5 : "Level 5 (50% pollunion)" + // 4 : "Level 4 (40% pollunion) " + // 3 : "Level 3 (30% pollunion)" + // 2 : "Level 2 (20% pollunion)" + // 1 : "Level 1 (10% pollunion) " + // 0 : "Level 0 (clean air)" + uint8_t LIN_AirQualSenCOlvl_Val; // Bits= 4 + + // 10 : "Level 10 (100% pollunion) " + // 9 : "Level 9 (90% pollunion) " + // 8 : "Level 8 (80% pollunion) " + // 7 : "Level 7 (70% pollunion) " + // 6 : "Level 6 (60% pollunion) " + // 5 : "Level 5 (50% pollunion)" + // 4 : "Level 4 (40% pollunion) " + // 3 : "Level 3 (30% pollunion)" + // 2 : "Level 2 (20% pollunion)" + // 1 : "Level 1 (10% pollunion) " + // 0 : "Level 0 (clean air)" + uint8_t LIN_AirQualSenNOxlvl_Val; // Bits= 4 + + // 10 : "Level 10 (100% pollunion) " + // 9 : "Level 9 (90% pollunion) " + // 8 : "Level 8 (80% pollunion) " + // 7 : "Level 7 (70% pollunion) " + // 6 : "Level 6 (60% pollunion) " + // 5 : "Level 5 (50% pollunion)" + // 4 : "Level 4 (40% pollunion) " + // 3 : "Level 3 (30% pollunion)" + // 2 : "Level 2 (20% pollunion)" + // 1 : "Level 1 (10% pollunion) " + // 0 : "Level 0 (clean air)" + uint8_t LIN_AirQualSenNH3lvl_Val; // Bits= 4 + +#endif // CANDB_DBG_USE_BITS_SIGNAL + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_DBG_USE_DIAG_MONITORS + +} dbg_LIN_AirQS_Stat_t; + +// def @dbg_LIN_Aroma_Stat CAN Message (1297 0x511) +#define dbg_LIN_Aroma_Stat_IDE (0U) +#define dbg_LIN_Aroma_Stat_DLC (5U) +#define dbg_LIN_Aroma_Stat_CANID (0x511U) + +// Value tables for @LIN_AromaLinRespErr_Stat signal + +#ifndef LIN_AromaLinRespErr_Stat_dbg_LIN_Aroma_Stat_Error +#define LIN_AromaLinRespErr_Stat_dbg_LIN_Aroma_Stat_Error (1) +#endif + +#ifndef LIN_AromaLinRespErr_Stat_dbg_LIN_Aroma_Stat_No_Error +#define LIN_AromaLinRespErr_Stat_dbg_LIN_Aroma_Stat_No_Error (0) +#endif + + +// Value tables for @LIN_Aroma_1CartridgeSw signal + +#ifndef LIN_Aroma_1CartridgeSw_dbg_LIN_Aroma_Stat_Cartridge_removed +#define LIN_Aroma_1CartridgeSw_dbg_LIN_Aroma_Stat_Cartridge_removed (1) +#endif + +#ifndef LIN_Aroma_1CartridgeSw_dbg_LIN_Aroma_Stat_Cartridge_installed +#define LIN_Aroma_1CartridgeSw_dbg_LIN_Aroma_Stat_Cartridge_installed (0) +#endif + + +// Value tables for @LIN_Aroma_2CartridgeSw signal + +#ifndef LIN_Aroma_2CartridgeSw_dbg_LIN_Aroma_Stat_Cartridge_removed +#define LIN_Aroma_2CartridgeSw_dbg_LIN_Aroma_Stat_Cartridge_removed (1) +#endif + +#ifndef LIN_Aroma_2CartridgeSw_dbg_LIN_Aroma_Stat_Cartridge_installed +#define LIN_Aroma_2CartridgeSw_dbg_LIN_Aroma_Stat_Cartridge_installed (0) +#endif + + +// Value tables for @LIN_Aroma_3CartridgeSw signal + +#ifndef LIN_Aroma_3CartridgeSw_dbg_LIN_Aroma_Stat_Cartridge_removed +#define LIN_Aroma_3CartridgeSw_dbg_LIN_Aroma_Stat_Cartridge_removed (1) +#endif + +#ifndef LIN_Aroma_3CartridgeSw_dbg_LIN_Aroma_Stat_Cartridge_installed +#define LIN_Aroma_3CartridgeSw_dbg_LIN_Aroma_Stat_Cartridge_installed (0) +#endif + + +// Value tables for @LIN_Aroma_Error_Stat signal + +#ifndef LIN_Aroma_Error_Stat_dbg_LIN_Aroma_Stat_Aroma_malfunction +#define LIN_Aroma_Error_Stat_dbg_LIN_Aroma_Stat_Aroma_malfunction (3) +#endif + +#ifndef LIN_Aroma_Error_Stat_dbg_LIN_Aroma_Stat_Supply_chain_short_circuit +#define LIN_Aroma_Error_Stat_dbg_LIN_Aroma_Stat_Supply_chain_short_circuit (2) +#endif + +#ifndef LIN_Aroma_Error_Stat_dbg_LIN_Aroma_Stat_Supply_chain_break +#define LIN_Aroma_Error_Stat_dbg_LIN_Aroma_Stat_Supply_chain_break (1) +#endif + +#ifndef LIN_Aroma_Error_Stat_dbg_LIN_Aroma_Stat_No_error +#define LIN_Aroma_Error_Stat_dbg_LIN_Aroma_Stat_No_error (0) +#endif + + +// Value tables for @LIN_Aroma_Intens signal + +#ifndef LIN_Aroma_Intens_dbg_LIN_Aroma_Stat_Aroma_malfunction +#define LIN_Aroma_Intens_dbg_LIN_Aroma_Stat_Aroma_malfunction (3) +#endif + +#ifndef LIN_Aroma_Intens_dbg_LIN_Aroma_Stat_Aromatization_mode_2_step +#define LIN_Aroma_Intens_dbg_LIN_Aroma_Stat_Aromatization_mode_2_step (2) +#endif + +#ifndef LIN_Aroma_Intens_dbg_LIN_Aroma_Stat_Aromatization_mode_1_step +#define LIN_Aroma_Intens_dbg_LIN_Aroma_Stat_Aromatization_mode_1_step (1) +#endif + +#ifndef LIN_Aroma_Intens_dbg_LIN_Aroma_Stat_Aromatization_off +#define LIN_Aroma_Intens_dbg_LIN_Aroma_Stat_Aromatization_off (0) +#endif + + +// Value tables for @LIN_Aroma_CartridgeSel signal + +#ifndef LIN_Aroma_CartridgeSel_dbg_LIN_Aroma_Stat_Third_cartridge_selected +#define LIN_Aroma_CartridgeSel_dbg_LIN_Aroma_Stat_Third_cartridge_selected (3) +#endif + +#ifndef LIN_Aroma_CartridgeSel_dbg_LIN_Aroma_Stat_Second_cartridge_selected +#define LIN_Aroma_CartridgeSel_dbg_LIN_Aroma_Stat_Second_cartridge_selected (2) +#endif + +#ifndef LIN_Aroma_CartridgeSel_dbg_LIN_Aroma_Stat_First_cartridge_selected +#define LIN_Aroma_CartridgeSel_dbg_LIN_Aroma_Stat_First_cartridge_selected (1) +#endif + +#ifndef LIN_Aroma_CartridgeSel_dbg_LIN_Aroma_Stat_No_cartridge_selected +#define LIN_Aroma_CartridgeSel_dbg_LIN_Aroma_Stat_No_cartridge_selected (0) +#endif + + +// Value tables for @LIN_Aroma_1CartridgeFlavor signal + +#ifndef LIN_Aroma_1CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_16 +#define LIN_Aroma_1CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_16 (15) +#endif + +#ifndef LIN_Aroma_1CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_15 +#define LIN_Aroma_1CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_15 (14) +#endif + +#ifndef LIN_Aroma_1CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_14 +#define LIN_Aroma_1CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_14 (13) +#endif + +#ifndef LIN_Aroma_1CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_13 +#define LIN_Aroma_1CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_13 (12) +#endif + +#ifndef LIN_Aroma_1CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_12 +#define LIN_Aroma_1CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_12 (11) +#endif + +#ifndef LIN_Aroma_1CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_11 +#define LIN_Aroma_1CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_11 (10) +#endif + +#ifndef LIN_Aroma_1CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_10 +#define LIN_Aroma_1CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_10 (9) +#endif + +#ifndef LIN_Aroma_1CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_9 +#define LIN_Aroma_1CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_9 (8) +#endif + +#ifndef LIN_Aroma_1CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_8 +#define LIN_Aroma_1CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_8 (7) +#endif + +#ifndef LIN_Aroma_1CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_7 +#define LIN_Aroma_1CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_7 (6) +#endif + +#ifndef LIN_Aroma_1CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_6 +#define LIN_Aroma_1CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_6 (5) +#endif + +#ifndef LIN_Aroma_1CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_5 +#define LIN_Aroma_1CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_5 (4) +#endif + +#ifndef LIN_Aroma_1CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_4 +#define LIN_Aroma_1CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_4 (3) +#endif + +#ifndef LIN_Aroma_1CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_3 +#define LIN_Aroma_1CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_3 (2) +#endif + +#ifndef LIN_Aroma_1CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_2 +#define LIN_Aroma_1CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_2 (1) +#endif + +#ifndef LIN_Aroma_1CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_1 +#define LIN_Aroma_1CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_1 (0) +#endif + + +// Value tables for @LIN_Aroma_2CartridgeFlavor signal + +#ifndef LIN_Aroma_2CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_16 +#define LIN_Aroma_2CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_16 (15) +#endif + +#ifndef LIN_Aroma_2CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_15 +#define LIN_Aroma_2CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_15 (14) +#endif + +#ifndef LIN_Aroma_2CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_14 +#define LIN_Aroma_2CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_14 (13) +#endif + +#ifndef LIN_Aroma_2CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_13 +#define LIN_Aroma_2CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_13 (12) +#endif + +#ifndef LIN_Aroma_2CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_12 +#define LIN_Aroma_2CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_12 (11) +#endif + +#ifndef LIN_Aroma_2CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_11 +#define LIN_Aroma_2CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_11 (10) +#endif + +#ifndef LIN_Aroma_2CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_10 +#define LIN_Aroma_2CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_10 (9) +#endif + +#ifndef LIN_Aroma_2CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_9 +#define LIN_Aroma_2CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_9 (8) +#endif + +#ifndef LIN_Aroma_2CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_8 +#define LIN_Aroma_2CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_8 (7) +#endif + +#ifndef LIN_Aroma_2CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_7 +#define LIN_Aroma_2CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_7 (6) +#endif + +#ifndef LIN_Aroma_2CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_6 +#define LIN_Aroma_2CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_6 (5) +#endif + +#ifndef LIN_Aroma_2CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_5 +#define LIN_Aroma_2CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_5 (4) +#endif + +#ifndef LIN_Aroma_2CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_4 +#define LIN_Aroma_2CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_4 (3) +#endif + +#ifndef LIN_Aroma_2CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_3 +#define LIN_Aroma_2CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_3 (2) +#endif + +#ifndef LIN_Aroma_2CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_2 +#define LIN_Aroma_2CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_2 (1) +#endif + +#ifndef LIN_Aroma_2CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_1 +#define LIN_Aroma_2CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_1 (0) +#endif + + +// Value tables for @LIN_Aroma_3CartridgeFlavor signal + +#ifndef LIN_Aroma_3CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_16 +#define LIN_Aroma_3CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_16 (15) +#endif + +#ifndef LIN_Aroma_3CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_15 +#define LIN_Aroma_3CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_15 (14) +#endif + +#ifndef LIN_Aroma_3CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_14 +#define LIN_Aroma_3CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_14 (13) +#endif + +#ifndef LIN_Aroma_3CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_13 +#define LIN_Aroma_3CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_13 (12) +#endif + +#ifndef LIN_Aroma_3CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_12 +#define LIN_Aroma_3CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_12 (11) +#endif + +#ifndef LIN_Aroma_3CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_11 +#define LIN_Aroma_3CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_11 (10) +#endif + +#ifndef LIN_Aroma_3CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_10 +#define LIN_Aroma_3CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_10 (9) +#endif + +#ifndef LIN_Aroma_3CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_9 +#define LIN_Aroma_3CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_9 (8) +#endif + +#ifndef LIN_Aroma_3CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_8 +#define LIN_Aroma_3CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_8 (7) +#endif + +#ifndef LIN_Aroma_3CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_7 +#define LIN_Aroma_3CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_7 (6) +#endif + +#ifndef LIN_Aroma_3CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_6 +#define LIN_Aroma_3CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_6 (5) +#endif + +#ifndef LIN_Aroma_3CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_5 +#define LIN_Aroma_3CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_5 (4) +#endif + +#ifndef LIN_Aroma_3CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_4 +#define LIN_Aroma_3CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_4 (3) +#endif + +#ifndef LIN_Aroma_3CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_3 +#define LIN_Aroma_3CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_3 (2) +#endif + +#ifndef LIN_Aroma_3CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_2 +#define LIN_Aroma_3CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_2 (1) +#endif + +#ifndef LIN_Aroma_3CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_1 +#define LIN_Aroma_3CartridgeFlavor_dbg_LIN_Aroma_Stat_Flavor_1 (0) +#endif + +// signal: @LIN_Aroma_1CartridgeCapacity_ro +#define CANDB_DBG_LIN_Aroma_1CartridgeCapacity_ro_CovFactor (10) +#define CANDB_DBG_LIN_Aroma_1CartridgeCapacity_ro_toS(x) ( (uint8_t) ((x) / (10)) ) +#define CANDB_DBG_LIN_Aroma_1CartridgeCapacity_ro_fromS(x) ( ((x) * (10)) ) +// signal: @LIN_Aroma_2CartridgeCapacity_ro +#define CANDB_DBG_LIN_Aroma_2CartridgeCapacity_ro_CovFactor (10) +#define CANDB_DBG_LIN_Aroma_2CartridgeCapacity_ro_toS(x) ( (uint8_t) ((x) / (10)) ) +#define CANDB_DBG_LIN_Aroma_2CartridgeCapacity_ro_fromS(x) ( ((x) * (10)) ) +// signal: @LIN_Aroma_3CartridgeCapacity_ro +#define CANDB_DBG_LIN_Aroma_3CartridgeCapacity_ro_CovFactor (10) +#define CANDB_DBG_LIN_Aroma_3CartridgeCapacity_ro_toS(x) ( (uint8_t) ((x) / (10)) ) +#define CANDB_DBG_LIN_Aroma_3CartridgeCapacity_ro_fromS(x) ( ((x) * (10)) ) + +typedef struct +{ +#ifdef CANDB_DBG_USE_BITS_SIGNAL + + // 1 : "Error" + // 0 : "No_Error" + uint8_t LIN_AromaLinRespErr_Stat : 1; // Bits= 1 + + // 1 : "Cartridge removed" + // 0 : "Cartridge installed" + uint8_t LIN_Aroma_1CartridgeSw : 1; // Bits= 1 + + // 1 : "Cartridge removed" + // 0 : "Cartridge installed" + uint8_t LIN_Aroma_2CartridgeSw : 1; // Bits= 1 + + // 1 : "Cartridge removed" + // 0 : "Cartridge installed" + uint8_t LIN_Aroma_3CartridgeSw : 1; // Bits= 1 + + // 3 : "Aroma malfunction" + // 2 : "Supply chain short circuit" + // 1 : "Supply chain break" + // 0 : "No error" + uint8_t LIN_Aroma_Error_Stat : 2; // Bits= 2 + + // 3 : "Aroma malfunction" + // 2 : "Aromatization mode 2 step" + // 1 : "Aromatization mode 1 step" + // 0 : "Aromatization off" + uint8_t LIN_Aroma_Intens : 2; // Bits= 2 + + // 3 : "Third cartridge selected" + // 2 : "Second cartridge selected" + // 1 : "First cartridge selected" + // 0 : "No cartridge selected" + uint8_t LIN_Aroma_CartridgeSel : 2; // Bits= 2 + + // 15 : "Flavor 16" + // 14 : "Flavor 15" + // 13 : "Flavor 14" + // 12 : "Flavor 13" + // 11 : "Flavor 12" + // 10 : "Flavor 11" + // 9 : "Flavor 10" + // 8 : "Flavor 9" + // 7 : "Flavor 8" + // 6 : "Flavor 7" + // 5 : "Flavor 6" + // 4 : "Flavor 5" + // 3 : "Flavor 4" + // 2 : "Flavor 3" + // 1 : "Flavor 2" + // 0 : "Flavor 1" + uint8_t LIN_Aroma_1CartridgeFlavor : 4; // Bits= 4 + + // 15 : "Flavor 16" + // 14 : "Flavor 15" + // 13 : "Flavor 14" + // 12 : "Flavor 13" + // 11 : "Flavor 12" + // 10 : "Flavor 11" + // 9 : "Flavor 10" + // 8 : "Flavor 9" + // 7 : "Flavor 8" + // 6 : "Flavor 7" + // 5 : "Flavor 6" + // 4 : "Flavor 5" + // 3 : "Flavor 4" + // 2 : "Flavor 3" + // 1 : "Flavor 2" + // 0 : "Flavor 1" + uint8_t LIN_Aroma_2CartridgeFlavor : 4; // Bits= 4 + + // 15 : "Flavor 16" + // 14 : "Flavor 15" + // 13 : "Flavor 14" + // 12 : "Flavor 13" + // 11 : "Flavor 12" + // 10 : "Flavor 11" + // 9 : "Flavor 10" + // 8 : "Flavor 9" + // 7 : "Flavor 8" + // 6 : "Flavor 7" + // 5 : "Flavor 6" + // 4 : "Flavor 5" + // 3 : "Flavor 4" + // 2 : "Flavor 3" + // 1 : "Flavor 2" + // 0 : "Flavor 1" + uint8_t LIN_Aroma_3CartridgeFlavor : 4; // Bits= 4 + + uint8_t LIN_Aroma_1CartridgeCapacity_ro : 4; // Bits= 4 Factor= 10 Unit:'%' + +#ifdef CANDB_DBG_USE_SIGFLOAT + uint8_t LIN_Aroma_1CartridgeCapacity_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + uint8_t LIN_Aroma_2CartridgeCapacity_ro : 4; // Bits= 4 Factor= 10 Unit:'%' + +#ifdef CANDB_DBG_USE_SIGFLOAT + uint8_t LIN_Aroma_2CartridgeCapacity_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + uint8_t LIN_Aroma_3CartridgeCapacity_ro : 4; // Bits= 4 Factor= 10 Unit:'%' + +#ifdef CANDB_DBG_USE_SIGFLOAT + uint8_t LIN_Aroma_3CartridgeCapacity_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + +#else + + // 1 : "Error" + // 0 : "No_Error" + uint8_t LIN_AromaLinRespErr_Stat; // Bits= 1 + + // 1 : "Cartridge removed" + // 0 : "Cartridge installed" + uint8_t LIN_Aroma_1CartridgeSw; // Bits= 1 + + // 1 : "Cartridge removed" + // 0 : "Cartridge installed" + uint8_t LIN_Aroma_2CartridgeSw; // Bits= 1 + + // 1 : "Cartridge removed" + // 0 : "Cartridge installed" + uint8_t LIN_Aroma_3CartridgeSw; // Bits= 1 + + // 3 : "Aroma malfunction" + // 2 : "Supply chain short circuit" + // 1 : "Supply chain break" + // 0 : "No error" + uint8_t LIN_Aroma_Error_Stat; // Bits= 2 + + // 3 : "Aroma malfunction" + // 2 : "Aromatization mode 2 step" + // 1 : "Aromatization mode 1 step" + // 0 : "Aromatization off" + uint8_t LIN_Aroma_Intens; // Bits= 2 + + // 3 : "Third cartridge selected" + // 2 : "Second cartridge selected" + // 1 : "First cartridge selected" + // 0 : "No cartridge selected" + uint8_t LIN_Aroma_CartridgeSel; // Bits= 2 + + // 15 : "Flavor 16" + // 14 : "Flavor 15" + // 13 : "Flavor 14" + // 12 : "Flavor 13" + // 11 : "Flavor 12" + // 10 : "Flavor 11" + // 9 : "Flavor 10" + // 8 : "Flavor 9" + // 7 : "Flavor 8" + // 6 : "Flavor 7" + // 5 : "Flavor 6" + // 4 : "Flavor 5" + // 3 : "Flavor 4" + // 2 : "Flavor 3" + // 1 : "Flavor 2" + // 0 : "Flavor 1" + uint8_t LIN_Aroma_1CartridgeFlavor; // Bits= 4 + + // 15 : "Flavor 16" + // 14 : "Flavor 15" + // 13 : "Flavor 14" + // 12 : "Flavor 13" + // 11 : "Flavor 12" + // 10 : "Flavor 11" + // 9 : "Flavor 10" + // 8 : "Flavor 9" + // 7 : "Flavor 8" + // 6 : "Flavor 7" + // 5 : "Flavor 6" + // 4 : "Flavor 5" + // 3 : "Flavor 4" + // 2 : "Flavor 3" + // 1 : "Flavor 2" + // 0 : "Flavor 1" + uint8_t LIN_Aroma_2CartridgeFlavor; // Bits= 4 + + // 15 : "Flavor 16" + // 14 : "Flavor 15" + // 13 : "Flavor 14" + // 12 : "Flavor 13" + // 11 : "Flavor 12" + // 10 : "Flavor 11" + // 9 : "Flavor 10" + // 8 : "Flavor 9" + // 7 : "Flavor 8" + // 6 : "Flavor 7" + // 5 : "Flavor 6" + // 4 : "Flavor 5" + // 3 : "Flavor 4" + // 2 : "Flavor 3" + // 1 : "Flavor 2" + // 0 : "Flavor 1" + uint8_t LIN_Aroma_3CartridgeFlavor; // Bits= 4 + + uint8_t LIN_Aroma_1CartridgeCapacity_ro; // Bits= 4 Factor= 10 Unit:'%' + +#ifdef CANDB_DBG_USE_SIGFLOAT + uint8_t LIN_Aroma_1CartridgeCapacity_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + uint8_t LIN_Aroma_2CartridgeCapacity_ro; // Bits= 4 Factor= 10 Unit:'%' + +#ifdef CANDB_DBG_USE_SIGFLOAT + uint8_t LIN_Aroma_2CartridgeCapacity_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + uint8_t LIN_Aroma_3CartridgeCapacity_ro; // Bits= 4 Factor= 10 Unit:'%' + +#ifdef CANDB_DBG_USE_SIGFLOAT + uint8_t LIN_Aroma_3CartridgeCapacity_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + +#endif // CANDB_DBG_USE_BITS_SIGNAL + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_DBG_USE_DIAG_MONITORS + +} dbg_LIN_Aroma_Stat_t; + +// def @dbg_LIN_Ionizer_Stat CAN Message (1299 0x513) +#define dbg_LIN_Ionizer_Stat_IDE (0U) +#define dbg_LIN_Ionizer_Stat_DLC (2U) +#define dbg_LIN_Ionizer_Stat_CANID (0x513U) + +// Value tables for @LIN_Ionizer_Err_Stat signal + +#ifndef LIN_Ionizer_Err_Stat_dbg_LIN_Ionizer_Stat_Component_malfunction +#define LIN_Ionizer_Err_Stat_dbg_LIN_Ionizer_Stat_Component_malfunction (3) +#endif + +#ifndef LIN_Ionizer_Err_Stat_dbg_LIN_Ionizer_Stat_Supply_chain_short +#define LIN_Ionizer_Err_Stat_dbg_LIN_Ionizer_Stat_Supply_chain_short (2) +#endif + +#ifndef LIN_Ionizer_Err_Stat_dbg_LIN_Ionizer_Stat_Supply_chain_break +#define LIN_Ionizer_Err_Stat_dbg_LIN_Ionizer_Stat_Supply_chain_break (1) +#endif + +#ifndef LIN_Ionizer_Err_Stat_dbg_LIN_Ionizer_Stat_No_error +#define LIN_Ionizer_Err_Stat_dbg_LIN_Ionizer_Stat_No_error (0) +#endif + + +// Value tables for @LIN_Ionizer_LinRespErr signal + +#ifndef LIN_Ionizer_LinRespErr_dbg_LIN_Ionizer_Stat_Error +#define LIN_Ionizer_LinRespErr_dbg_LIN_Ionizer_Stat_Error (1) +#endif + +#ifndef LIN_Ionizer_LinRespErr_dbg_LIN_Ionizer_Stat_No_Error +#define LIN_Ionizer_LinRespErr_dbg_LIN_Ionizer_Stat_No_Error (0) +#endif + + +// Value tables for @LIN_Ionizer_Ionization signal + +#ifndef LIN_Ionizer_Ionization_dbg_LIN_Ionizer_Stat_Ionization_is_off_standby_mode +#define LIN_Ionizer_Ionization_dbg_LIN_Ionizer_Stat_Ionization_is_off_standby_mode (2) +#endif + +#ifndef LIN_Ionizer_Ionization_dbg_LIN_Ionizer_Stat_Ionization_is_on_active_mode +#define LIN_Ionizer_Ionization_dbg_LIN_Ionizer_Stat_Ionization_is_on_active_mode (1) +#endif + +#ifndef LIN_Ionizer_Ionization_dbg_LIN_Ionizer_Stat_Initializing +#define LIN_Ionizer_Ionization_dbg_LIN_Ionizer_Stat_Initializing (0) +#endif + + +typedef struct +{ +#ifdef CANDB_DBG_USE_BITS_SIGNAL + + // 3 : "Component malfunction" + // 2 : "Supply chain short" + // 1 : "Supply chain break" + // 0 : "No error" + uint8_t LIN_Ionizer_Err_Stat : 2; // Bits= 2 + + // 1 : "Error" + // 0 : "No_Error" + uint8_t LIN_Ionizer_LinRespErr : 1; // Bits= 1 + + // 2 : "Ionization is off (standby mode)" + // 1 : "Ionization is on (active mode)" + // 0 : "Initializing" + uint8_t LIN_Ionizer_Ionization : 2; // Bits= 2 + +#else + + // 3 : "Component malfunction" + // 2 : "Supply chain short" + // 1 : "Supply chain break" + // 0 : "No error" + uint8_t LIN_Ionizer_Err_Stat; // Bits= 2 + + // 1 : "Error" + // 0 : "No_Error" + uint8_t LIN_Ionizer_LinRespErr; // Bits= 1 + + // 2 : "Ionization is off (standby mode)" + // 1 : "Ionization is on (active mode)" + // 0 : "Initializing" + uint8_t LIN_Ionizer_Ionization; // Bits= 2 + +#endif // CANDB_DBG_USE_BITS_SIGNAL + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_DBG_USE_DIAG_MONITORS + +} dbg_LIN_Ionizer_Stat_t; + +// def @dbg_LIN_eTXV_Stat CAN Message (1300 0x514) +#define dbg_LIN_eTXV_Stat_IDE (0U) +#define dbg_LIN_eTXV_Stat_DLC (8U) +#define dbg_LIN_eTXV_Stat_CANID (0x514U) + +// Value tables for @LIN_eTXV1_LinRespErr_Stat signal + +#ifndef LIN_eTXV1_LinRespErr_Stat_dbg_LIN_eTXV_Stat_Error +#define LIN_eTXV1_LinRespErr_Stat_dbg_LIN_eTXV_Stat_Error (1) +#endif + +#ifndef LIN_eTXV1_LinRespErr_Stat_dbg_LIN_eTXV_Stat_No_error +#define LIN_eTXV1_LinRespErr_Stat_dbg_LIN_eTXV_Stat_No_error (0) +#endif + + +// Value tables for @LIN_eTXVee1_Err_Stat signal + +#ifndef LIN_eTXVee1_Err_Stat_dbg_LIN_eTXV_Stat_Component_malfunction +#define LIN_eTXVee1_Err_Stat_dbg_LIN_eTXV_Stat_Component_malfunction (3) +#endif + +#ifndef LIN_eTXVee1_Err_Stat_dbg_LIN_eTXV_Stat_Supply_chain_short_circuit +#define LIN_eTXVee1_Err_Stat_dbg_LIN_eTXV_Stat_Supply_chain_short_circuit (2) +#endif + +#ifndef LIN_eTXVee1_Err_Stat_dbg_LIN_eTXV_Stat_Supply_chain_break +#define LIN_eTXVee1_Err_Stat_dbg_LIN_eTXV_Stat_Supply_chain_break (1) +#endif + +#ifndef LIN_eTXVee1_Err_Stat_dbg_LIN_eTXV_Stat_No_error +#define LIN_eTXVee1_Err_Stat_dbg_LIN_eTXV_Stat_No_error (0) +#endif + + +// Value tables for @LIN_eTXV2_LinRespErr_Stat signal + +#ifndef LIN_eTXV2_LinRespErr_Stat_dbg_LIN_eTXV_Stat_Error +#define LIN_eTXV2_LinRespErr_Stat_dbg_LIN_eTXV_Stat_Error (1) +#endif + +#ifndef LIN_eTXV2_LinRespErr_Stat_dbg_LIN_eTXV_Stat_No_error +#define LIN_eTXV2_LinRespErr_Stat_dbg_LIN_eTXV_Stat_No_error (0) +#endif + + +// Value tables for @LIN_eTXVee2_Err_Stat signal + +#ifndef LIN_eTXVee2_Err_Stat_dbg_LIN_eTXV_Stat_Component_malfunction +#define LIN_eTXVee2_Err_Stat_dbg_LIN_eTXV_Stat_Component_malfunction (3) +#endif + +#ifndef LIN_eTXVee2_Err_Stat_dbg_LIN_eTXV_Stat_Supply_chain_short_circuit +#define LIN_eTXVee2_Err_Stat_dbg_LIN_eTXV_Stat_Supply_chain_short_circuit (2) +#endif + +#ifndef LIN_eTXVee2_Err_Stat_dbg_LIN_eTXV_Stat_Supply_chain_break +#define LIN_eTXVee2_Err_Stat_dbg_LIN_eTXV_Stat_Supply_chain_break (1) +#endif + +#ifndef LIN_eTXVee2_Err_Stat_dbg_LIN_eTXV_Stat_No_error +#define LIN_eTXVee2_Err_Stat_dbg_LIN_eTXV_Stat_No_error (0) +#endif + + +// Value tables for @LIN_eTXV3_LinRespErr_Stat signal + +#ifndef LIN_eTXV3_LinRespErr_Stat_dbg_LIN_eTXV_Stat_Error +#define LIN_eTXV3_LinRespErr_Stat_dbg_LIN_eTXV_Stat_Error (1) +#endif + +#ifndef LIN_eTXV3_LinRespErr_Stat_dbg_LIN_eTXV_Stat_No_error +#define LIN_eTXV3_LinRespErr_Stat_dbg_LIN_eTXV_Stat_No_error (0) +#endif + + +// Value tables for @LIN_eTXVeeChiller1_Err_Stat signal + +#ifndef LIN_eTXVeeChiller1_Err_Stat_dbg_LIN_eTXV_Stat_Component_malfunction +#define LIN_eTXVeeChiller1_Err_Stat_dbg_LIN_eTXV_Stat_Component_malfunction (3) +#endif + +#ifndef LIN_eTXVeeChiller1_Err_Stat_dbg_LIN_eTXV_Stat_Supply_chain_short_circuit +#define LIN_eTXVeeChiller1_Err_Stat_dbg_LIN_eTXV_Stat_Supply_chain_short_circuit (2) +#endif + +#ifndef LIN_eTXVeeChiller1_Err_Stat_dbg_LIN_eTXV_Stat_Supply_chain_break +#define LIN_eTXVeeChiller1_Err_Stat_dbg_LIN_eTXV_Stat_Supply_chain_break (1) +#endif + +#ifndef LIN_eTXVeeChiller1_Err_Stat_dbg_LIN_eTXV_Stat_No_error +#define LIN_eTXVeeChiller1_Err_Stat_dbg_LIN_eTXV_Stat_No_error (0) +#endif + + +// Value tables for @LIN_eTXV4_LinRespErr_Stat signal + +#ifndef LIN_eTXV4_LinRespErr_Stat_dbg_LIN_eTXV_Stat_Error +#define LIN_eTXV4_LinRespErr_Stat_dbg_LIN_eTXV_Stat_Error (1) +#endif + +#ifndef LIN_eTXV4_LinRespErr_Stat_dbg_LIN_eTXV_Stat_No_error +#define LIN_eTXV4_LinRespErr_Stat_dbg_LIN_eTXV_Stat_No_error (0) +#endif + + +// Value tables for @LIN_eTXVeeChiller2_Err_Stat signal + +#ifndef LIN_eTXVeeChiller2_Err_Stat_dbg_LIN_eTXV_Stat_Component_malfunction +#define LIN_eTXVeeChiller2_Err_Stat_dbg_LIN_eTXV_Stat_Component_malfunction (3) +#endif + +#ifndef LIN_eTXVeeChiller2_Err_Stat_dbg_LIN_eTXV_Stat_Supply_chain_short_circuit +#define LIN_eTXVeeChiller2_Err_Stat_dbg_LIN_eTXV_Stat_Supply_chain_short_circuit (2) +#endif + +#ifndef LIN_eTXVeeChiller2_Err_Stat_dbg_LIN_eTXV_Stat_Supply_chain_break +#define LIN_eTXVeeChiller2_Err_Stat_dbg_LIN_eTXV_Stat_Supply_chain_break (1) +#endif + +#ifndef LIN_eTXVeeChiller2_Err_Stat_dbg_LIN_eTXV_Stat_No_error +#define LIN_eTXVeeChiller2_Err_Stat_dbg_LIN_eTXV_Stat_No_error (0) +#endif + + +typedef struct +{ +#ifdef CANDB_DBG_USE_BITS_SIGNAL + + uint8_t LIN_eTXVee1_Pos_Stat : 7; // Bits= 7 Unit:'%' + + // 1 : "Error" + // 0 : "No error" + uint8_t LIN_eTXV1_LinRespErr_Stat : 1; // Bits= 1 + + // 3 : "Component malfunction" + // 2 : "Supply chain short circuit" + // 1 : "Supply chain break" + // 0 : "No error" + uint8_t LIN_eTXVee1_Err_Stat : 2; // Bits= 2 + + uint8_t LIN_eTXVee2_Pos_Stat : 7; // Bits= 7 Unit:'%' + + // 1 : "Error" + // 0 : "No error" + uint8_t LIN_eTXV2_LinRespErr_Stat : 1; // Bits= 1 + + // 3 : "Component malfunction" + // 2 : "Supply chain short circuit" + // 1 : "Supply chain break" + // 0 : "No error" + uint8_t LIN_eTXVee2_Err_Stat : 2; // Bits= 2 + + uint8_t LIN_eTXVeeChiller1_Pos_Stat : 7; // Bits= 7 Unit:'%' + + // 1 : "Error" + // 0 : "No error" + uint8_t LIN_eTXV3_LinRespErr_Stat : 1; // Bits= 1 + + // 3 : "Component malfunction" + // 2 : "Supply chain short circuit" + // 1 : "Supply chain break" + // 0 : "No error" + uint8_t LIN_eTXVeeChiller1_Err_Stat : 2; // Bits= 2 + + uint8_t LIN_eTXVeeChiller2_Pos_Stat : 7; // Bits= 7 Unit:'%' + + // 1 : "Error" + // 0 : "No error" + uint8_t LIN_eTXV4_LinRespErr_Stat : 1; // Bits= 1 + + // 3 : "Component malfunction" + // 2 : "Supply chain short circuit" + // 1 : "Supply chain break" + // 0 : "No error" + uint8_t LIN_eTXVeeChiller2_Err_Stat : 2; // Bits= 2 + +#else + + uint8_t LIN_eTXVee1_Pos_Stat; // Bits= 7 Unit:'%' + + // 1 : "Error" + // 0 : "No error" + uint8_t LIN_eTXV1_LinRespErr_Stat; // Bits= 1 + + // 3 : "Component malfunction" + // 2 : "Supply chain short circuit" + // 1 : "Supply chain break" + // 0 : "No error" + uint8_t LIN_eTXVee1_Err_Stat; // Bits= 2 + + uint8_t LIN_eTXVee2_Pos_Stat; // Bits= 7 Unit:'%' + + // 1 : "Error" + // 0 : "No error" + uint8_t LIN_eTXV2_LinRespErr_Stat; // Bits= 1 + + // 3 : "Component malfunction" + // 2 : "Supply chain short circuit" + // 1 : "Supply chain break" + // 0 : "No error" + uint8_t LIN_eTXVee2_Err_Stat; // Bits= 2 + + uint8_t LIN_eTXVeeChiller1_Pos_Stat; // Bits= 7 Unit:'%' + + // 1 : "Error" + // 0 : "No error" + uint8_t LIN_eTXV3_LinRespErr_Stat; // Bits= 1 + + // 3 : "Component malfunction" + // 2 : "Supply chain short circuit" + // 1 : "Supply chain break" + // 0 : "No error" + uint8_t LIN_eTXVeeChiller1_Err_Stat; // Bits= 2 + + uint8_t LIN_eTXVeeChiller2_Pos_Stat; // Bits= 7 Unit:'%' + + // 1 : "Error" + // 0 : "No error" + uint8_t LIN_eTXV4_LinRespErr_Stat; // Bits= 1 + + // 3 : "Component malfunction" + // 2 : "Supply chain short circuit" + // 1 : "Supply chain break" + // 0 : "No error" + uint8_t LIN_eTXVeeChiller2_Err_Stat; // Bits= 2 + +#endif // CANDB_DBG_USE_BITS_SIGNAL + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_DBG_USE_DIAG_MONITORS + +} dbg_LIN_eTXV_Stat_t; + +// def @dbg_LIN_DRS_Stat CAN Message (1304 0x518) +#define dbg_LIN_DRS_Stat_IDE (0U) +#define dbg_LIN_DRS_Stat_DLC (5U) +#define dbg_LIN_DRS_Stat_CANID (0x518U) +// signal: @LIN_DRS_BCM_IndFadingTime_ro +#define CANDB_DBG_LIN_DRS_BCM_IndFadingTime_ro_CovFactor (0.1) +#define CANDB_DBG_LIN_DRS_BCM_IndFadingTime_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_LIN_DRS_BCM_IndFadingTime_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +// Value tables for @LIN_DRS_BCM_SwIndIntens signal + +#ifndef LIN_DRS_BCM_SwIndIntens_dbg_LIN_DRS_Stat_Low_level +#define LIN_DRS_BCM_SwIndIntens_dbg_LIN_DRS_Stat_Low_level (1) +#endif + +#ifndef LIN_DRS_BCM_SwIndIntens_dbg_LIN_DRS_Stat_Hight_level +#define LIN_DRS_BCM_SwIndIntens_dbg_LIN_DRS_Stat_Hight_level (0) +#endif + + +typedef struct +{ +#ifdef CANDB_DBG_USE_BITS_SIGNAL + + uint8_t LIN_DRS_DLLed1 : 1; // Bits= 1 + + uint8_t LIN_DRS_DLLed2 : 1; // Bits= 1 + + uint8_t LIN_DRS_DLLed3 : 1; // Bits= 1 + + uint8_t LIN_DRS_DRLed1 : 1; // Bits= 1 + + uint8_t LIN_DRS_DRLed2 : 1; // Bits= 1 + + uint8_t LIN_DRS_DRLed3 : 1; // Bits= 1 + + uint8_t LIN_DRS_FPLLed1 : 1; // Bits= 1 + + uint8_t LIN_DRS_FPLLed2 : 1; // Bits= 1 + + uint8_t LIN_DRS_FPLLed3 : 1; // Bits= 1 + + uint8_t LIN_DRS_FPRLed1 : 1; // Bits= 1 + + uint8_t LIN_DRS_FPRLed2 : 1; // Bits= 1 + + uint8_t LIN_DRS_FPRLed3 : 1; // Bits= 1 + + uint8_t LIN_DRS_RLBLed1 : 1; // Bits= 1 + + uint8_t LIN_DRS_RLBLed2 : 1; // Bits= 1 + + uint8_t LIN_DRS_RLBLed3 : 1; // Bits= 1 + + uint8_t LIN_DRS_RRBLed1 : 1; // Bits= 1 + + uint8_t LIN_DRS_RRBLed2 : 1; // Bits= 1 + + uint8_t LIN_DRS_RRBLed3 : 1; // Bits= 1 + + uint8_t LIN_DRS_FCLLed1 : 1; // Bits= 1 + + uint8_t LIN_DRS_FCLLed2 : 1; // Bits= 1 + + uint8_t LIN_DRS_FCLLed3 : 1; // Bits= 1 + + uint8_t LIN_DRS_FCRLed1 : 1; // Bits= 1 + + uint8_t LIN_DRS_FCRLed2 : 1; // Bits= 1 + + uint8_t LIN_DRS_FCRLed3 : 1; // Bits= 1 + + uint8_t LIN_DRS_BCM_IndFadingTime_ro : 5; // Bits= 5 Factor= 0.1 Unit:'sec' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t LIN_DRS_BCM_IndFadingTime_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // 1 : "Low level" + // 0 : "Hight level" + uint8_t LIN_DRS_BCM_SwIndIntens : 1; // Bits= 1 + +#else + + uint8_t LIN_DRS_DLLed1; // Bits= 1 + + uint8_t LIN_DRS_DLLed2; // Bits= 1 + + uint8_t LIN_DRS_DLLed3; // Bits= 1 + + uint8_t LIN_DRS_DRLed1; // Bits= 1 + + uint8_t LIN_DRS_DRLed2; // Bits= 1 + + uint8_t LIN_DRS_DRLed3; // Bits= 1 + + uint8_t LIN_DRS_FPLLed1; // Bits= 1 + + uint8_t LIN_DRS_FPLLed2; // Bits= 1 + + uint8_t LIN_DRS_FPLLed3; // Bits= 1 + + uint8_t LIN_DRS_FPRLed1; // Bits= 1 + + uint8_t LIN_DRS_FPRLed2; // Bits= 1 + + uint8_t LIN_DRS_FPRLed3; // Bits= 1 + + uint8_t LIN_DRS_RLBLed1; // Bits= 1 + + uint8_t LIN_DRS_RLBLed2; // Bits= 1 + + uint8_t LIN_DRS_RLBLed3; // Bits= 1 + + uint8_t LIN_DRS_RRBLed1; // Bits= 1 + + uint8_t LIN_DRS_RRBLed2; // Bits= 1 + + uint8_t LIN_DRS_RRBLed3; // Bits= 1 + + uint8_t LIN_DRS_FCLLed1; // Bits= 1 + + uint8_t LIN_DRS_FCLLed2; // Bits= 1 + + uint8_t LIN_DRS_FCLLed3; // Bits= 1 + + uint8_t LIN_DRS_FCRLed1; // Bits= 1 + + uint8_t LIN_DRS_FCRLed2; // Bits= 1 + + uint8_t LIN_DRS_FCRLed3; // Bits= 1 + + uint8_t LIN_DRS_BCM_IndFadingTime_ro; // Bits= 5 Factor= 0.1 Unit:'sec' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t LIN_DRS_BCM_IndFadingTime_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // 1 : "Low level" + // 0 : "Hight level" + uint8_t LIN_DRS_BCM_SwIndIntens; // Bits= 1 + +#endif // CANDB_DBG_USE_BITS_SIGNAL + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_DBG_USE_DIAG_MONITORS + +} dbg_LIN_DRS_Stat_t; + +// def @dbg_Auto_AF CAN Message (1312 0x520) +#define dbg_Auto_AF_IDE (0U) +#define dbg_Auto_AF_DLC (8U) +#define dbg_Auto_AF_CANID (0x520U) +#define dbg_Auto_AF_CYC (250U) + +// Value tables for @dbg_Auto_AF_MultMsg_Idx signal + +#ifndef dbg_Auto_AF_MultMsg_Idx_dbg_Auto_AF_RR +#define dbg_Auto_AF_MultMsg_Idx_dbg_Auto_AF_RR (3) +#endif + +#ifndef dbg_Auto_AF_MultMsg_Idx_dbg_Auto_AF_RL +#define dbg_Auto_AF_MultMsg_Idx_dbg_Auto_AF_RL (2) +#endif + +#ifndef dbg_Auto_AF_MultMsg_Idx_dbg_Auto_AF_FR +#define dbg_Auto_AF_MultMsg_Idx_dbg_Auto_AF_FR (1) +#endif + +#ifndef dbg_Auto_AF_MultMsg_Idx_dbg_Auto_AF_FL +#define dbg_Auto_AF_MultMsg_Idx_dbg_Auto_AF_FL (0) +#endif + + +typedef struct +{ +#ifdef CANDB_DBG_USE_BITS_SIGNAL + + // 3 : "RR" + // 2 : "RL" + // 1 : "FR" + // 0 : "FL" + // MULTIPLEX master signal + uint8_t dbg_Auto_AF_MultMsg_Idx : 2; // Bits= 2 + + // multiplex variable + int16_t dbg_Auto_AF_Correct_FL; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Correct_FR; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Correct_RL; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Correct_RR; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Vtg_RL; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Vtg_FL; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Vtg_FR; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Vtg_RR; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Incar_RL; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Incar_FR; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Incar_RR; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Incar_FL; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Amb_RL; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Amb_FR; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Sun_RR; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Amb_FL; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Sun_FR; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Sun_RL; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Amb_RR; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Sun_FL; // [-] Bits=12 Unit:'AF' + +#else + + // 3 : "RR" + // 2 : "RL" + // 1 : "FR" + // 0 : "FL" + // MULTIPLEX master signal + uint8_t dbg_Auto_AF_MultMsg_Idx; // Bits= 2 + + // multiplex variable + int16_t dbg_Auto_AF_Correct_FL; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Correct_FR; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Correct_RL; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Correct_RR; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Vtg_RL; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Vtg_FL; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Vtg_FR; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Vtg_RR; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Incar_RL; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Incar_FR; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Incar_RR; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Incar_FL; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Amb_RL; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Amb_FR; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Sun_RR; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Amb_FL; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Sun_FR; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Sun_RL; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Amb_RR; // [-] Bits=12 Unit:'AF' + + // multiplex variable + int16_t dbg_Auto_AF_Sun_FL; // [-] Bits=12 Unit:'AF' + +#endif // CANDB_DBG_USE_BITS_SIGNAL + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_DBG_USE_DIAG_MONITORS + +} dbg_Auto_AF_t; + +// def @dbg_Auto_Duct CAN Message (1316 0x524) +#define dbg_Auto_Duct_IDE (0U) +#define dbg_Auto_Duct_DLC (8U) +#define dbg_Auto_Duct_CANID (0x524U) +#define dbg_Auto_Duct_CYC (250U) + +// Value tables for @dbg_Auto_Duct_MultMsg_Idx signal + +#ifndef dbg_Auto_Duct_MultMsg_Idx_dbg_Auto_Duct_IncarTg +#define dbg_Auto_Duct_MultMsg_Idx_dbg_Auto_Duct_IncarTg (6) +#endif + +#ifndef dbg_Auto_Duct_MultMsg_Idx_dbg_Auto_Duct_RR +#define dbg_Auto_Duct_MultMsg_Idx_dbg_Auto_Duct_RR (5) +#endif + +#ifndef dbg_Auto_Duct_MultMsg_Idx_dbg_Auto_Duct_RL +#define dbg_Auto_Duct_MultMsg_Idx_dbg_Auto_Duct_RL (4) +#endif + +#ifndef dbg_Auto_Duct_MultMsg_Idx_dbg_Auto_Duct_FR_Lower +#define dbg_Auto_Duct_MultMsg_Idx_dbg_Auto_Duct_FR_Lower (3) +#endif + +#ifndef dbg_Auto_Duct_MultMsg_Idx_dbg_Auto_Duct_FR_Upper +#define dbg_Auto_Duct_MultMsg_Idx_dbg_Auto_Duct_FR_Upper (2) +#endif + +#ifndef dbg_Auto_Duct_MultMsg_Idx_dbg_Auto_Duct_FL_Lower +#define dbg_Auto_Duct_MultMsg_Idx_dbg_Auto_Duct_FL_Lower (1) +#endif + +#ifndef dbg_Auto_Duct_MultMsg_Idx_dbg_Auto_Duct_FL_Upper +#define dbg_Auto_Duct_MultMsg_Idx_dbg_Auto_Duct_FL_Upper (0) +#endif + +// signal: @dbg_Auto_Duct_Tgt_FL_Upper_ro +#define CANDB_DBG_dbg_Auto_Duct_Tgt_FL_Upper_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Duct_Tgt_FL_Upper_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Duct_Tgt_FL_Upper_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Auto_Duct_Tg_Incar_FL_Upper_ro +#define CANDB_DBG_dbg_Auto_Duct_Tg_Incar_FL_Upper_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Duct_Tg_Incar_FL_Upper_ro_toS(x) ( (int16_t) (((x) - (20.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Duct_Tg_Incar_FL_Upper_ro_fromS(x) ( (((x) * (0.1)) + (20.0)) ) +// signal: @dbg_Auto_Duct_Tgt_RR_ro +#define CANDB_DBG_dbg_Auto_Duct_Tgt_RR_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Duct_Tgt_RR_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Duct_Tgt_RR_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Auto_Duct_Tgt_RL_ro +#define CANDB_DBG_dbg_Auto_Duct_Tgt_RL_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Duct_Tgt_RL_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Duct_Tgt_RL_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Auto_Duct_Tgt_FR_Upper_ro +#define CANDB_DBG_dbg_Auto_Duct_Tgt_FR_Upper_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Duct_Tgt_FR_Upper_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Duct_Tgt_FR_Upper_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Auto_Duct_Tgt_FR_Lower_ro +#define CANDB_DBG_dbg_Auto_Duct_Tgt_FR_Lower_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Duct_Tgt_FR_Lower_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Duct_Tgt_FR_Lower_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Auto_Duct_Tgt_FL_Lower_ro +#define CANDB_DBG_dbg_Auto_Duct_Tgt_FL_Lower_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Duct_Tgt_FL_Lower_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Duct_Tgt_FL_Lower_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Auto_Duct_Tg_Incar_FR_Upper_ro +#define CANDB_DBG_dbg_Auto_Duct_Tg_Incar_FR_Upper_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Duct_Tg_Incar_FR_Upper_ro_toS(x) ( (int16_t) (((x) - (20.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Duct_Tg_Incar_FR_Upper_ro_fromS(x) ( (((x) * (0.1)) + (20.0)) ) +// signal: @dbg_Auto_Duct_Tg_FL_Upper_ro +#define CANDB_DBG_dbg_Auto_Duct_Tg_FL_Upper_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Duct_Tg_FL_Upper_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Duct_Tg_FL_Upper_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Auto_Duct_Tg_FL_Lower_ro +#define CANDB_DBG_dbg_Auto_Duct_Tg_FL_Lower_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Duct_Tg_FL_Lower_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Duct_Tg_FL_Lower_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Auto_Duct_Tg_FR_Lower_ro +#define CANDB_DBG_dbg_Auto_Duct_Tg_FR_Lower_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Duct_Tg_FR_Lower_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Duct_Tg_FR_Lower_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Auto_Duct_Tg_FR_Upper_ro +#define CANDB_DBG_dbg_Auto_Duct_Tg_FR_Upper_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Duct_Tg_FR_Upper_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Duct_Tg_FR_Upper_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Auto_Duct_Tg_RL_ro +#define CANDB_DBG_dbg_Auto_Duct_Tg_RL_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Duct_Tg_RL_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Duct_Tg_RL_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Auto_Duct_Tg_RR_ro +#define CANDB_DBG_dbg_Auto_Duct_Tg_RR_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Duct_Tg_RR_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Duct_Tg_RR_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Auto_Duct_Tg_Incar_FL_Lower_ro +#define CANDB_DBG_dbg_Auto_Duct_Tg_Incar_FL_Lower_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Duct_Tg_Incar_FL_Lower_ro_toS(x) ( (int16_t) (((x) - (20.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Duct_Tg_Incar_FL_Lower_ro_fromS(x) ( (((x) * (0.1)) + (20.0)) ) +// signal: @dbg_Auto_Duct_Incar_FL_Lower_ro +#define CANDB_DBG_dbg_Auto_Duct_Incar_FL_Lower_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Duct_Incar_FL_Lower_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Duct_Incar_FL_Lower_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Auto_Duct_Incar_RR_ro +#define CANDB_DBG_dbg_Auto_Duct_Incar_RR_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Duct_Incar_RR_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Duct_Incar_RR_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Auto_Duct_Incar_RL_ro +#define CANDB_DBG_dbg_Auto_Duct_Incar_RL_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Duct_Incar_RL_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Duct_Incar_RL_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Auto_Duct_Incar_FR_Upper_ro +#define CANDB_DBG_dbg_Auto_Duct_Incar_FR_Upper_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Duct_Incar_FR_Upper_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Duct_Incar_FR_Upper_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Auto_Duct_Incar_FR_Lower_ro +#define CANDB_DBG_dbg_Auto_Duct_Incar_FR_Lower_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Duct_Incar_FR_Lower_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Duct_Incar_FR_Lower_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Auto_Duct_Incar_FL_Upper_ro +#define CANDB_DBG_dbg_Auto_Duct_Incar_FL_Upper_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Duct_Incar_FL_Upper_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Duct_Incar_FL_Upper_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Auto_Duct_Tg_Incar_FR_Lower_ro +#define CANDB_DBG_dbg_Auto_Duct_Tg_Incar_FR_Lower_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Duct_Tg_Incar_FR_Lower_ro_toS(x) ( (int16_t) (((x) - (20.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Duct_Tg_Incar_FR_Lower_ro_fromS(x) ( (((x) * (0.1)) + (20.0)) ) +// signal: @dbg_Auto_Duct_Amb_RL_ro +#define CANDB_DBG_dbg_Auto_Duct_Amb_RL_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Duct_Amb_RL_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Duct_Amb_RL_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Auto_Duct_Amb_FR_Upper_ro +#define CANDB_DBG_dbg_Auto_Duct_Amb_FR_Upper_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Duct_Amb_FR_Upper_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Duct_Amb_FR_Upper_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Auto_Duct_Amb_FR_Lower_ro +#define CANDB_DBG_dbg_Auto_Duct_Amb_FR_Lower_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Duct_Amb_FR_Lower_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Duct_Amb_FR_Lower_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Auto_Duct_Amb_RR_ro +#define CANDB_DBG_dbg_Auto_Duct_Amb_RR_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Duct_Amb_RR_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Duct_Amb_RR_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Auto_Duct_Amb_FL_Lower_ro +#define CANDB_DBG_dbg_Auto_Duct_Amb_FL_Lower_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Duct_Amb_FL_Lower_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Duct_Amb_FL_Lower_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Auto_Duct_Amb_FL_Upper_ro +#define CANDB_DBG_dbg_Auto_Duct_Amb_FL_Upper_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Duct_Amb_FL_Upper_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Duct_Amb_FL_Upper_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Auto_Duct_Tg_Incar_RL_ro +#define CANDB_DBG_dbg_Auto_Duct_Tg_Incar_RL_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Duct_Tg_Incar_RL_ro_toS(x) ( (int16_t) (((x) - (20.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Duct_Tg_Incar_RL_ro_fromS(x) ( (((x) * (0.1)) + (20.0)) ) +// signal: @dbg_Auto_Duct_Sun_FL_Lower_ro +#define CANDB_DBG_dbg_Auto_Duct_Sun_FL_Lower_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Duct_Sun_FL_Lower_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Duct_Sun_FL_Lower_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Auto_Duct_Sun_FR_Lower_ro +#define CANDB_DBG_dbg_Auto_Duct_Sun_FR_Lower_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Duct_Sun_FR_Lower_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Duct_Sun_FR_Lower_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Auto_Duct_Sun_FR_Upper_ro +#define CANDB_DBG_dbg_Auto_Duct_Sun_FR_Upper_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Duct_Sun_FR_Upper_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Duct_Sun_FR_Upper_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Auto_Duct_Sun_RL_ro +#define CANDB_DBG_dbg_Auto_Duct_Sun_RL_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Duct_Sun_RL_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Duct_Sun_RL_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Auto_Duct_Sun_FL_Upper_ro +#define CANDB_DBG_dbg_Auto_Duct_Sun_FL_Upper_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Duct_Sun_FL_Upper_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Duct_Sun_FL_Upper_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Auto_Duct_Sun_RR_ro +#define CANDB_DBG_dbg_Auto_Duct_Sun_RR_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Duct_Sun_RR_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Duct_Sun_RR_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Auto_Duct_Tg_Incar_RR_ro +#define CANDB_DBG_dbg_Auto_Duct_Tg_Incar_RR_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Duct_Tg_Incar_RR_ro_toS(x) ( (int16_t) (((x) - (20.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Duct_Tg_Incar_RR_ro_fromS(x) ( (((x) * (0.1)) + (20.0)) ) + +typedef struct +{ +#ifdef CANDB_DBG_USE_BITS_SIGNAL + + // 6 : "IncarTg" + // 5 : "RR" + // 4 : "RL" + // 3 : "FR_Lower" + // 2 : "FR_Upper" + // 1 : "FL_Lower" + // 0 : "FL_Upper" + // MULTIPLEX master signal + uint8_t dbg_Auto_Duct_MultMsg_Idx : 4; // Bits= 4 + + // multiplex variable + int16_t dbg_Auto_Duct_Tgt_FL_Upper_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Tgt_FL_Upper_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Tg_Incar_FL_Upper_ro; // [-] Bits=10 Offset= 20.0 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Tg_Incar_FL_Upper_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Tgt_RR_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Tgt_RR_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Tgt_RL_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Tgt_RL_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Tgt_FR_Upper_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Tgt_FR_Upper_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Tgt_FR_Lower_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Tgt_FR_Lower_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Tgt_FL_Lower_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Tgt_FL_Lower_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Tg_Incar_FR_Upper_ro; // [-] Bits=10 Offset= 20.0 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Tg_Incar_FR_Upper_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Tg_FL_Upper_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Tg_FL_Upper_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Tg_FL_Lower_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Tg_FL_Lower_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Tg_FR_Lower_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Tg_FR_Lower_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Tg_FR_Upper_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Tg_FR_Upper_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Tg_RL_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Tg_RL_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Tg_RR_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Tg_RR_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Tg_Incar_FL_Lower_ro; // [-] Bits=10 Offset= 20.0 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Tg_Incar_FL_Lower_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Incar_FL_Lower_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Incar_FL_Lower_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Incar_RR_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Incar_RR_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Incar_RL_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Incar_RL_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Incar_FR_Upper_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Incar_FR_Upper_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Incar_FR_Lower_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Incar_FR_Lower_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Incar_FL_Upper_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Incar_FL_Upper_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Tg_Incar_FR_Lower_ro; // [-] Bits=10 Offset= 20.0 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Tg_Incar_FR_Lower_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Amb_RL_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Amb_RL_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Amb_FR_Upper_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Amb_FR_Upper_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Amb_FR_Lower_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Amb_FR_Lower_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Amb_RR_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Amb_RR_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Amb_FL_Lower_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Amb_FL_Lower_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Amb_FL_Upper_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Amb_FL_Upper_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Tg_Incar_RL_ro; // [-] Bits=10 Offset= 20.0 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Tg_Incar_RL_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Sun_FL_Lower_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Sun_FL_Lower_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Sun_FR_Lower_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Sun_FR_Lower_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Sun_FR_Upper_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Sun_FR_Upper_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Sun_RL_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Sun_RL_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Sun_FL_Upper_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Sun_FL_Upper_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Sun_RR_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Sun_RR_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Tg_Incar_RR_ro; // [-] Bits=10 Offset= 20.0 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Tg_Incar_RR_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + +#else + + // 6 : "IncarTg" + // 5 : "RR" + // 4 : "RL" + // 3 : "FR_Lower" + // 2 : "FR_Upper" + // 1 : "FL_Lower" + // 0 : "FL_Upper" + // MULTIPLEX master signal + uint8_t dbg_Auto_Duct_MultMsg_Idx; // Bits= 4 + + // multiplex variable + int16_t dbg_Auto_Duct_Tgt_FL_Upper_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Tgt_FL_Upper_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Tg_Incar_FL_Upper_ro; // [-] Bits=10 Offset= 20.0 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Tg_Incar_FL_Upper_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Tgt_RR_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Tgt_RR_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Tgt_RL_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Tgt_RL_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Tgt_FR_Upper_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Tgt_FR_Upper_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Tgt_FR_Lower_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Tgt_FR_Lower_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Tgt_FL_Lower_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Tgt_FL_Lower_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Tg_Incar_FR_Upper_ro; // [-] Bits=10 Offset= 20.0 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Tg_Incar_FR_Upper_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Tg_FL_Upper_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Tg_FL_Upper_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Tg_FL_Lower_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Tg_FL_Lower_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Tg_FR_Lower_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Tg_FR_Lower_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Tg_FR_Upper_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Tg_FR_Upper_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Tg_RL_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Tg_RL_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Tg_RR_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Tg_RR_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Tg_Incar_FL_Lower_ro; // [-] Bits=10 Offset= 20.0 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Tg_Incar_FL_Lower_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Incar_FL_Lower_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Incar_FL_Lower_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Incar_RR_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Incar_RR_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Incar_RL_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Incar_RL_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Incar_FR_Upper_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Incar_FR_Upper_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Incar_FR_Lower_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Incar_FR_Lower_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Incar_FL_Upper_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Incar_FL_Upper_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Tg_Incar_FR_Lower_ro; // [-] Bits=10 Offset= 20.0 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Tg_Incar_FR_Lower_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Amb_RL_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Amb_RL_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Amb_FR_Upper_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Amb_FR_Upper_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Amb_FR_Lower_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Amb_FR_Lower_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Amb_RR_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Amb_RR_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Amb_FL_Lower_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Amb_FL_Lower_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Amb_FL_Upper_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Amb_FL_Upper_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Tg_Incar_RL_ro; // [-] Bits=10 Offset= 20.0 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Tg_Incar_RL_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Sun_FL_Lower_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Sun_FL_Lower_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Sun_FR_Lower_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Sun_FR_Lower_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Sun_FR_Upper_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Sun_FR_Upper_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Sun_RL_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Sun_RL_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Sun_FL_Upper_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Sun_FL_Upper_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Sun_RR_ro; // [-] Bits=12 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Sun_RR_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + // multiplex variable + int16_t dbg_Auto_Duct_Tg_Incar_RR_ro; // [-] Bits=10 Offset= 20.0 Factor= 0.1 Unit:'��' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Duct_Tg_Incar_RR_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + +#endif // CANDB_DBG_USE_BITS_SIGNAL + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_DBG_USE_DIAG_MONITORS + +} dbg_Auto_Duct_t; + +// def @dbg_Auto_Valve_Plus CAN Message (1328 0x530) +#define dbg_Auto_Valve_Plus_IDE (0U) +#define dbg_Auto_Valve_Plus_DLC (8U) +#define dbg_Auto_Valve_Plus_CANID (0x530U) +// signal: @dbg_Auto_Valve_Plus_Vent_SFL_ro +#define CANDB_DBG_dbg_Auto_Valve_Plus_Vent_SFL_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Valve_Plus_Vent_SFL_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Valve_Plus_Vent_SFL_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Auto_Valve_Plus_Vent_CFL_ro +#define CANDB_DBG_dbg_Auto_Valve_Plus_Vent_CFL_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Valve_Plus_Vent_CFL_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Valve_Plus_Vent_CFL_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Auto_Valve_Plus_Foot_FL_ro +#define CANDB_DBG_dbg_Auto_Valve_Plus_Foot_FL_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Valve_Plus_Foot_FL_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Valve_Plus_Foot_FL_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Auto_Valve_Plus_Vent_SFR_ro +#define CANDB_DBG_dbg_Auto_Valve_Plus_Vent_SFR_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Valve_Plus_Vent_SFR_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Valve_Plus_Vent_SFR_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Auto_Valve_Plus_Vent_CFR_ro +#define CANDB_DBG_dbg_Auto_Valve_Plus_Vent_CFR_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Valve_Plus_Vent_CFR_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Valve_Plus_Vent_CFR_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @dbg_Auto_Valve_Plus_Foot_FR_ro +#define CANDB_DBG_dbg_Auto_Valve_Plus_Foot_FR_ro_CovFactor (0.1) +#define CANDB_DBG_dbg_Auto_Valve_Plus_Foot_FR_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DBG_dbg_Auto_Valve_Plus_Foot_FR_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_DBG_USE_BITS_SIGNAL + + int16_t dbg_Auto_Valve_Plus_Vent_SFL_ro; // [-] Bits=10 Factor= 0.1 Unit:'0.1%' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Valve_Plus_Vent_SFL_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + int16_t dbg_Auto_Valve_Plus_Vent_CFL_ro; // [-] Bits=10 Factor= 0.1 Unit:'0.1%' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Valve_Plus_Vent_CFL_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + int16_t dbg_Auto_Valve_Plus_Foot_FL_ro; // [-] Bits=10 Factor= 0.1 Unit:'0.1%' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Valve_Plus_Foot_FL_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + int16_t dbg_Auto_Valve_Plus_Vent_SFR_ro; // [-] Bits=10 Factor= 0.1 Unit:'0.1%' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Valve_Plus_Vent_SFR_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + int16_t dbg_Auto_Valve_Plus_Vent_CFR_ro; // [-] Bits=10 Factor= 0.1 Unit:'0.1%' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Valve_Plus_Vent_CFR_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + int16_t dbg_Auto_Valve_Plus_Foot_FR_ro; // [-] Bits=10 Factor= 0.1 Unit:'0.1%' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Valve_Plus_Foot_FR_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + +#else + + int16_t dbg_Auto_Valve_Plus_Vent_SFL_ro; // [-] Bits=10 Factor= 0.1 Unit:'0.1%' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Valve_Plus_Vent_SFL_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + int16_t dbg_Auto_Valve_Plus_Vent_CFL_ro; // [-] Bits=10 Factor= 0.1 Unit:'0.1%' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Valve_Plus_Vent_CFL_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + int16_t dbg_Auto_Valve_Plus_Foot_FL_ro; // [-] Bits=10 Factor= 0.1 Unit:'0.1%' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Valve_Plus_Foot_FL_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + int16_t dbg_Auto_Valve_Plus_Vent_SFR_ro; // [-] Bits=10 Factor= 0.1 Unit:'0.1%' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Valve_Plus_Vent_SFR_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + int16_t dbg_Auto_Valve_Plus_Vent_CFR_ro; // [-] Bits=10 Factor= 0.1 Unit:'0.1%' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Valve_Plus_Vent_CFR_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + + int16_t dbg_Auto_Valve_Plus_Foot_FR_ro; // [-] Bits=10 Factor= 0.1 Unit:'0.1%' + +#ifdef CANDB_DBG_USE_SIGFLOAT + sigfloat_t dbg_Auto_Valve_Plus_Foot_FR_phys; +#endif // CANDB_DBG_USE_SIGFLOAT + +#endif // CANDB_DBG_USE_BITS_SIGNAL + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_DBG_USE_DIAG_MONITORS + +} dbg_Auto_Valve_Plus_t; + +// def @XCP_CCU_RX CAN Message (1707 0x6ab) +#define XCP_CCU_RX_IDE (0U) +#define XCP_CCU_RX_DLC (8U) +#define XCP_CCU_RX_CANID (0x6abU) + +typedef struct +{ +#ifdef CANDB_DBG_USE_BITS_SIGNAL + + int64_t XcpCcuRx; // [-] Bits=64 Unit:'-' + +#else + + int64_t XcpCcuRx; // [-] Bits=64 Unit:'-' + +#endif // CANDB_DBG_USE_BITS_SIGNAL + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_DBG_USE_DIAG_MONITORS + +} XCP_CCU_RX_t; + +// def @XCP_CCU_TX CAN Message (1723 0x6bb) +#define XCP_CCU_TX_IDE (0U) +#define XCP_CCU_TX_DLC (8U) +#define XCP_CCU_TX_CANID (0x6bbU) + +typedef struct +{ +#ifdef CANDB_DBG_USE_BITS_SIGNAL + + int64_t XcpCcuTx; // [-] Bits=64 Unit:'-' + +#else + + int64_t XcpCcuTx; // [-] Bits=64 Unit:'-' + +#endif // CANDB_DBG_USE_BITS_SIGNAL + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_DBG_USE_DIAG_MONITORS + +} XCP_CCU_TX_t; + + +typedef struct { + + uint16_t P_FUL; + uint16_t I_FUL; + uint16_t D_FUL; + + uint16_t P_FUR; + uint16_t I_FUR; + uint16_t D_FUR; + + uint16_t P_FLL; + uint16_t I_FLL; + uint16_t D_FLL; + + + uint16_t P_FRL; + uint16_t I_FRL; + uint16_t D_FRL; + + uint16_t P_RL; + uint16_t I_RL; + uint16_t D_RL; + + uint16_t P_RR; + uint16_t I_RR; + uint16_t D_RR; + +} dbg_Stat_PID_t; + +// Function signatures + +uint32_t Unpack_dbg_Logic_State_candb_dbg(dbg_Logic_State_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_DBG_USE_CANSTRUCT +uint32_t Pack_dbg_Logic_State_candb_dbg(dbg_Logic_State_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_dbg_Logic_State_candb_dbg(dbg_Logic_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Logic_KM_Status_candb_dbg(dbg_Logic_KM_Status_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_DBG_USE_CANSTRUCT +uint32_t Pack_dbg_Logic_KM_Status_candb_dbg(dbg_Logic_KM_Status_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_dbg_Logic_KM_Status_candb_dbg(dbg_Logic_KM_Status_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Logic_Valve_candb_dbg(dbg_Logic_Valve_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_DBG_USE_CANSTRUCT +uint32_t Pack_dbg_Logic_Valve_candb_dbg(dbg_Logic_Valve_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_dbg_Logic_Valve_candb_dbg(dbg_Logic_Valve_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Logic_Blower_candb_dbg(dbg_Logic_Blower_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_DBG_USE_CANSTRUCT +uint32_t Pack_dbg_Logic_Blower_candb_dbg(dbg_Logic_Blower_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_dbg_Logic_Blower_candb_dbg(dbg_Logic_Blower_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Logic_Ac_candb_dbg(dbg_Logic_Ac_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_DBG_USE_CANSTRUCT +uint32_t Pack_dbg_Logic_Ac_candb_dbg(dbg_Logic_Ac_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_dbg_Logic_Ac_candb_dbg(dbg_Logic_Ac_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Logic_Rec_candb_dbg(dbg_Logic_Rec_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_DBG_USE_CANSTRUCT +uint32_t Pack_dbg_Logic_Rec_candb_dbg(dbg_Logic_Rec_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_dbg_Logic_Rec_candb_dbg(dbg_Logic_Rec_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_DiffBlr_ValveOpen_candb_dbg(dbg_DiffBlr_ValveOpen_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_DBG_USE_CANSTRUCT +uint32_t Pack_dbg_DiffBlr_ValveOpen_candb_dbg(dbg_DiffBlr_ValveOpen_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_dbg_DiffBlr_ValveOpen_candb_dbg(dbg_DiffBlr_ValveOpen_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Act0_candb_dbg(dbg_Act0_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_DBG_USE_CANSTRUCT +uint32_t Pack_dbg_Act0_candb_dbg(dbg_Act0_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_dbg_Act0_candb_dbg(dbg_Act0_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Act1_candb_dbg(dbg_Act1_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_DBG_USE_CANSTRUCT +uint32_t Pack_dbg_Act1_candb_dbg(dbg_Act1_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_dbg_Act1_candb_dbg(dbg_Act1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Act2_candb_dbg(dbg_Act2_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_DBG_USE_CANSTRUCT +uint32_t Pack_dbg_Act2_candb_dbg(dbg_Act2_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_dbg_Act2_candb_dbg(dbg_Act2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Sen_Amb_candb_dbg(dbg_Sen_Amb_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_DBG_USE_CANSTRUCT +uint32_t Pack_dbg_Sen_Amb_candb_dbg(dbg_Sen_Amb_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_dbg_Sen_Amb_candb_dbg(dbg_Sen_Amb_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Sen_0_candb_dbg(dbg_Sen_0_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_DBG_USE_CANSTRUCT +uint32_t Pack_dbg_Sen_0_candb_dbg(dbg_Sen_0_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_dbg_Sen_0_candb_dbg(dbg_Sen_0_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_CCU_IO_candb_dbg(dbg_CCU_IO_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_DBG_USE_CANSTRUCT +uint32_t Pack_dbg_CCU_IO_candb_dbg(dbg_CCU_IO_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_dbg_CCU_IO_candb_dbg(dbg_CCU_IO_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_CCU_Info_candb_dbg(dbg_CCU_Info_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_DBG_USE_CANSTRUCT +uint32_t Pack_dbg_CCU_Info_candb_dbg(dbg_CCU_Info_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_dbg_CCU_Info_candb_dbg(dbg_CCU_Info_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Drs_candb_dbg(dbg_Drs_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_DBG_USE_CANSTRUCT +uint32_t Pack_dbg_Drs_candb_dbg(dbg_Drs_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_dbg_Drs_candb_dbg(dbg_Drs_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Sen_Incar_candb_dbg(dbg_Sen_Incar_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_DBG_USE_CANSTRUCT +uint32_t Pack_dbg_Sen_Incar_candb_dbg(dbg_Sen_Incar_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_dbg_Sen_Incar_candb_dbg(dbg_Sen_Incar_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Cmd_Act_Information_candb_dbg(dbg_Cmd_Act_Information_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_DBG_USE_CANSTRUCT +uint32_t Pack_dbg_Cmd_Act_Information_candb_dbg(dbg_Cmd_Act_Information_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_dbg_Cmd_Act_Information_candb_dbg(dbg_Cmd_Act_Information_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Info_Act1_candb_dbg(dbg_Info_Act1_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_DBG_USE_CANSTRUCT +uint32_t Pack_dbg_Info_Act1_candb_dbg(dbg_Info_Act1_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_dbg_Info_Act1_candb_dbg(dbg_Info_Act1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Info_Act2_candb_dbg(dbg_Info_Act2_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_DBG_USE_CANSTRUCT +uint32_t Pack_dbg_Info_Act2_candb_dbg(dbg_Info_Act2_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_dbg_Info_Act2_candb_dbg(dbg_Info_Act2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Sen_Eva_candb_dbg(dbg_Sen_Eva_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_DBG_USE_CANSTRUCT +uint32_t Pack_dbg_Sen_Eva_candb_dbg(dbg_Sen_Eva_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_dbg_Sen_Eva_candb_dbg(dbg_Sen_Eva_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Sen_Duct_candb_dbg(dbg_Sen_Duct_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_DBG_USE_CANSTRUCT +uint32_t Pack_dbg_Sen_Duct_candb_dbg(dbg_Sen_Duct_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_dbg_Sen_Duct_candb_dbg(dbg_Sen_Duct_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Sen_Demist_candb_dbg(dbg_Sen_Demist_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_DBG_USE_CANSTRUCT +uint32_t Pack_dbg_Sen_Demist_candb_dbg(dbg_Sen_Demist_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_dbg_Sen_Demist_candb_dbg(dbg_Sen_Demist_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_LIN_AirQS_Stat_candb_dbg(dbg_LIN_AirQS_Stat_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_DBG_USE_CANSTRUCT +uint32_t Pack_dbg_LIN_AirQS_Stat_candb_dbg(dbg_LIN_AirQS_Stat_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_dbg_LIN_AirQS_Stat_candb_dbg(dbg_LIN_AirQS_Stat_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_LIN_Aroma_Stat_candb_dbg(dbg_LIN_Aroma_Stat_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_DBG_USE_CANSTRUCT +uint32_t Pack_dbg_LIN_Aroma_Stat_candb_dbg(dbg_LIN_Aroma_Stat_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_dbg_LIN_Aroma_Stat_candb_dbg(dbg_LIN_Aroma_Stat_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_LIN_Ionizer_Stat_candb_dbg(dbg_LIN_Ionizer_Stat_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_DBG_USE_CANSTRUCT +uint32_t Pack_dbg_LIN_Ionizer_Stat_candb_dbg(dbg_LIN_Ionizer_Stat_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_dbg_LIN_Ionizer_Stat_candb_dbg(dbg_LIN_Ionizer_Stat_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_LIN_eTXV_Stat_candb_dbg(dbg_LIN_eTXV_Stat_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_DBG_USE_CANSTRUCT +uint32_t Pack_dbg_LIN_eTXV_Stat_candb_dbg(dbg_LIN_eTXV_Stat_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_dbg_LIN_eTXV_Stat_candb_dbg(dbg_LIN_eTXV_Stat_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_LIN_DRS_Stat_candb_dbg(dbg_LIN_DRS_Stat_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_DBG_USE_CANSTRUCT +uint32_t Pack_dbg_LIN_DRS_Stat_candb_dbg(dbg_LIN_DRS_Stat_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_dbg_LIN_DRS_Stat_candb_dbg(dbg_LIN_DRS_Stat_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Auto_AF_candb_dbg(dbg_Auto_AF_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_DBG_USE_CANSTRUCT +uint32_t Pack_dbg_Auto_AF_candb_dbg(dbg_Auto_AF_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_dbg_Auto_AF_candb_dbg(dbg_Auto_AF_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Auto_Duct_candb_dbg(dbg_Auto_Duct_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_DBG_USE_CANSTRUCT +uint32_t Pack_dbg_Auto_Duct_candb_dbg(dbg_Auto_Duct_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_dbg_Auto_Duct_candb_dbg(dbg_Auto_Duct_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_dbg_Auto_Valve_Plus_candb_dbg(dbg_Auto_Valve_Plus_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_DBG_USE_CANSTRUCT +uint32_t Pack_dbg_Auto_Valve_Plus_candb_dbg(dbg_Auto_Valve_Plus_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_dbg_Auto_Valve_Plus_candb_dbg(dbg_Auto_Valve_Plus_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_XCP_CCU_RX_candb_dbg(XCP_CCU_RX_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_DBG_USE_CANSTRUCT +uint32_t Pack_XCP_CCU_RX_candb_dbg(XCP_CCU_RX_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_XCP_CCU_RX_candb_dbg(XCP_CCU_RX_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_DBG_USE_CANSTRUCT + +uint32_t Unpack_XCP_CCU_TX_candb_dbg(XCP_CCU_TX_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_DBG_USE_CANSTRUCT +uint32_t Pack_XCP_CCU_TX_candb_dbg(XCP_CCU_TX_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_XCP_CCU_TX_candb_dbg(XCP_CCU_TX_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_DBG_USE_CANSTRUCT + +#ifdef __cplusplus +} +#endif diff --git a/MODULES/HVAC_M7_CAN_DBG_MATRIX/modular.json b/MODULES/HVAC_M7_CAN_DBG_MATRIX/modular.json new file mode 100644 index 0000000..35ce3f4 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_DBG_MATRIX/modular.json @@ -0,0 +1,15 @@ +{ + "cmake": { + "inc_dirs": [ + "inc", + "butl", + "conf", + "lib" + ], + "srcs": [ + "butl/**.c", + "lib/**.c", + "usr/**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_CAN_DBG_MATRIX/usr/candb_dbg-fmon.c b/MODULES/HVAC_M7_CAN_DBG_MATRIX/usr/candb_dbg-fmon.c new file mode 100644 index 0000000..5477f17 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_DBG_MATRIX/usr/candb_dbg-fmon.c @@ -0,0 +1,216 @@ +// Generator version : v3.1 +// DBC filename : CCUdbg.dbc +#include "candb_dbg-fmon.h" + +#ifdef CANDB_DBG_USE_DIAG_MONITORS + +/* +Put the monitor function content here, keep in mind - +next generation will completely clear all manually added code (!) +*/ + +#ifdef CANDB_DBG_USE_MONO_FMON + +void _FMon_MONO_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +#else + +void _FMon_dbg_Logic_State_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_dbg_Logic_KM_Status_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_dbg_Logic_Valve_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_dbg_Logic_Blower_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_dbg_Logic_Ac_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_dbg_Logic_Rec_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_dbg_DiffBlr_ValveOpen_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_dbg_Act0_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_dbg_Act1_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_dbg_Act2_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_dbg_Sen_Amb_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_dbg_Sen_0_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_dbg_CCU_IO_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_dbg_CCU_Info_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_dbg_Drs_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_dbg_Sen_Incar_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_dbg_Cmd_Act_Information_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_dbg_Info_Act1_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_dbg_Info_Act2_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_dbg_Sen_Eva_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_dbg_Sen_Duct_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_dbg_Sen_Demist_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_dbg_LIN_AirQS_Stat_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_dbg_LIN_Aroma_Stat_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_dbg_LIN_Ionizer_Stat_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_dbg_LIN_eTXV_Stat_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_dbg_LIN_DRS_Stat_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_dbg_Auto_AF_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_dbg_Auto_Duct_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_dbg_Auto_Valve_Plus_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_XCP_CCU_RX_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_XCP_CCU_TX_candb_dbg(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +#endif // CANDB_DBG_USE_MONO_FMON + +#endif // CANDB_DBG_USE_DIAG_MONITORS diff --git a/MODULES/HVAC_M7_CAN_DEBUG_SPAM/CanSpamDebugReceiver.c b/MODULES/HVAC_M7_CAN_DEBUG_SPAM/CanSpamDebugReceiver.c new file mode 100644 index 0000000..28c7f81 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_DEBUG_SPAM/CanSpamDebugReceiver.c @@ -0,0 +1,76 @@ +// +// Created by cfif on 05.04.2024. +// +#include +#include "CanSpamDebugReceiver.h" +#include "CmsisRtosThreadUtils.h" +#include "CanPorts.h" +#include "string.h" +#include "HVAC_model.h" + +#define LOG_SIGN "CAN_DEBUG_RECEIVED" +#define LOGGER env->logger + +void CanSpamDebugReceiver_Init(tCanSpamDebugReceiver *env, + tSerialPortFrameIO *ioCanFrame, + tLoggerInterface *logger) { + + env->ioCanFrame = ioCanFrame; + env->logger = logger; + env->access = osMutexNew(NULL); + + InitThreadAtrStatic(&env->thread.attr, "CanSpamDebugRec", env->thread.controlBlock, env->thread.stack, + osPriorityNormal); +} + +static void ListenCanSpamDebugReceiver(tCanSpamDebugReceiver *env) { + + uint16_t recv = env->ioCanFrame->receive(env->ioCanFrame->env, PROTOCOL_CAN_RAW, (uint8_t *) &env->canFrame, 1, + 1000); + + if (recv == 0) + return; + + if (osMutexAcquire(env->access, 5000) == osOK) { + + uint32_t id = env->canFrame.standard_id; + + if (env->canFrame.id_type == FLEXCAN_ID_EXT) { + id = env->canFrame.extended_id; + } + + uint32_t result = ccu_candb_dbg_Receive(&ccu_candb_dbg_rx, env->canFrame.data, id, env->canFrame.dlc); + + osMutexRelease(env->access); + } else { + LoggerErrorStatic(LOGGER, LOG_SIGN, "Access error ListenCanSpamDebugReceiver"); + } + +} + +uint8_t get_CanSpamDebugReceiverMultiIndex(tCanSpamDebugReceiver *env) { + uint8_t index = 0; + + if (osMutexAcquire(env->access, 5000) == osOK) { + + index = ccu_candb_dbg_rx.dbg_Cmd_Act_Information.Cmd_Target_Act_Index; + + osMutexRelease(env->access); + } else { + LoggerErrorStatic(LOGGER, LOG_SIGN, "Access error get_CanSpamDebugReceiver"); + } + + return index; +} + +static _Noreturn void CanSpamDebugReceiver_Thread(tCanSpamDebugReceiver *env) { + for (;;) { + ListenCanSpamDebugReceiver(env); + } +} + +void CanSpamDebugReceiver_StartThread(tCanSpamDebugReceiver *env) { + if (!env->thread.id) { + env->thread.id = osThreadNew((osThreadFunc_t) (CanSpamDebugReceiver_Thread), (void *) (env), &env->thread.attr); + } +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_CAN_DEBUG_SPAM/CanSpamDebugReceiver.h b/MODULES/HVAC_M7_CAN_DEBUG_SPAM/CanSpamDebugReceiver.h new file mode 100644 index 0000000..d00cb53 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_DEBUG_SPAM/CanSpamDebugReceiver.h @@ -0,0 +1,37 @@ +// +// Created by cfif on 05.04.2024. +// + +#ifndef HVAC_CAN_SPAM_DEBUG_RECEIVER_H +#define HVAC_CAN_SPAM_DEBUG_RECEIVER_H + +#include +#include "CanSerialPortFrame.h" +#include "ccu_candb_dbg-binutil.h" +#include "LoggerInterface.h" + + +typedef struct { + + tSerialPortFrameIO *ioCanFrame; + osMutexId_t access; + can_rx_message_type canFrame; + + tLoggerInterface *logger; + + struct { + osThreadId_t id; + uint32_t stack[384]; + StaticTask_t controlBlock; + osThreadAttr_t attr; + } thread; + +} tCanSpamDebugReceiver; + +void CanSpamDebugReceiver_Init(tCanSpamDebugReceiver *env, tSerialPortFrameIO *ioCanFrame, tLoggerInterface *logger); + +void CanSpamDebugReceiver_StartThread(tCanSpamDebugReceiver *env); + +uint8_t get_CanSpamDebugReceiverMultiIndex(tCanSpamDebugReceiver *env); + +#endif //HVAC_CAN_SPAM_DEBUG_RECEIVER_H diff --git a/MODULES/HVAC_M7_CAN_DEBUG_SPAM/CanSpamDebugTransmitter.c b/MODULES/HVAC_M7_CAN_DEBUG_SPAM/CanSpamDebugTransmitter.c new file mode 100644 index 0000000..978255c --- /dev/null +++ b/MODULES/HVAC_M7_CAN_DEBUG_SPAM/CanSpamDebugTransmitter.c @@ -0,0 +1,503 @@ +// +// Created by cfif on 05.12.2025. +// +#include +#include "CanSpamDebugTransmitter.h" +#include "CmsisRtosThreadUtils.h" +#include "CanPorts.h" +#include "memory.h" +#include "HVAC_model.h" +#include "candb_dbg_fixed.h" +#include "StatusData.h" + +extern tStatus_Set_For_Model model_Status_Set_For_Model_output; +extern tStatus_Pwm_For_Model model_Status_Pwm_For_Model_output; + +#define LOG_SIGN "CAN_DEBUG_TRANSMITTER" +#define LOGGER env->logger + +void CanSpamDebugTransmitter_Init(tCanSpamDebugTransmitter *env, + tSerialPortFrameIO *ioCanFrame, + tCanSpamDebugReceiver *canSpamDebugReceiver, + tLoggerInterface *logger) { + + env->ioCanFrame = ioCanFrame; + env->logger = logger; + env->canSpamDebugReceiver = canSpamDebugReceiver; + env->access = osMutexNew(NULL); + env->dbg_Sen_Duct_MultMsg_Idx = 0; + env->dbg_Sen_Incar_MultMsg_Idx = 0; + env->dbg_DiffBlr_ValveOpen_MultMsg_Idx = 0; + env->dbg_CCU_Info_MultMsg_Idx = 0; + env->dbg_Auto_Duct_MultMsg_Idx = 0; + env->dbg_Auto_AF_MultMsg_Idx = 0; + + env->queue_ccu_candb_dbg_tx = osMessageQueueNew(1, sizeof(ccu_candb_dbg_tx_t), NULL); + + InitThreadAtrStatic(&env->thread.attr, "CanSpamDebugTrans", env->thread.controlBlock, env->thread.stack, + osPriorityNormal); +} + + +static void sendEventToCan(tCanSpamDebugTransmitter *env) { + if (env->ide) { + env->canFrame.id_type = FLEXCAN_ID_EXT; + env->canFrame.extended_id = env->can_id; + } else { + env->canFrame.id_type = FLEXCAN_ID_STD; + env->canFrame.standard_id = env->can_id; + } + + env->logger->loggingCan(env->logger->env, 2, 1, env->canFrame.dlc, env->canFrame.standard_id, + env->canFrame.data, SystemGetMs()); + + env->ioCanFrame->transmit(env->ioCanFrame->env, (uint8_t *) &env->canFrame.data, env->canFrame.dlc, + env->can_id, env->canFrame.id_type, 50); +} + + +static eTimeEventDbgTransmit isEventTransmitter(tCanSpamDebugTransmitter *env) { + +#if (dbg_Act0_SEND == 1) + if (env->time_dbg_Act0_CYC <= env->timeMs) { + env->time_dbg_Act0_CYC = env->timeMs + dbg_Act0_CYC; + + env->can_id = Pack_dbg_Act0_candb_dbg(&ccu_candb_dbg_tx.dbg_Act0, env->canFrame.data, &env->canFrame.dlc, + &env->ide); + + return event_dbg_Act0_CYC; + } +#endif + +#if (dbg_Act1_SEND == 1) + if (env->time_dbg_Act1_CYC <= env->timeMs) { + env->time_dbg_Act1_CYC = env->timeMs + dbg_Act1_CYC; + + env->can_id = Pack_dbg_Act1_candb_dbg(&ccu_candb_dbg_tx.dbg_Act1, env->canFrame.data, &env->canFrame.dlc, + &env->ide); + + return event_dbg_Act1_CYC; + } +#endif + +#if (dbg_Act2_SEND == 1) + if (env->time_dbg_Act2_CYC <= env->timeMs) { + env->time_dbg_Act2_CYC = env->timeMs + dbg_Act2_CYC; + + env->can_id = Pack_dbg_Act2_candb_dbg(&ccu_candb_dbg_tx.dbg_Act2, env->canFrame.data, &env->canFrame.dlc, + &env->ide); + + return event_dbg_Act2_CYC; + } +#endif + + +#if (dbg_Auto_AF_SEND == 1) + if (env->time_dbg_Auto_AF_CYC <= env->timeMs) { + env->time_dbg_Auto_AF_CYC = env->timeMs + dbg_Auto_AF_CYC; + + ++env->dbg_Auto_AF_MultMsg_Idx; + if (env->dbg_Auto_AF_MultMsg_Idx > 3) { + env->dbg_Auto_AF_MultMsg_Idx = 0; + } + + ccu_candb_dbg_tx.dbg_Auto_AF.dbg_Auto_AF_MultMsg_Idx = env->dbg_Auto_AF_MultMsg_Idx; + + env->can_id = Pack_dbg_Auto_AF_candb_dbg2(&ccu_candb_dbg_tx.dbg_Auto_AF, env->canFrame.data, + &env->canFrame.dlc, &env->ide); + + return event_dbg_Auto_AF_CYC; + } +#endif + +#if (dbg_Auto_Duct_SEND == 1) + if (env->time_dbg_Auto_Duct_CYC <= env->timeMs) { + env->time_dbg_Auto_Duct_CYC = env->timeMs + dbg_Auto_Duct_CYC; + + ++env->dbg_Auto_Duct_MultMsg_Idx; + if (env->dbg_Auto_Duct_MultMsg_Idx > 6) { + env->dbg_Auto_Duct_MultMsg_Idx = 0; + } + + ccu_candb_dbg_tx.dbg_Auto_Duct.dbg_Auto_Duct_MultMsg_Idx = env->dbg_Auto_Duct_MultMsg_Idx; + + env->can_id = Pack_dbg_Auto_Duct_candb_dbg2(&ccu_candb_dbg_tx.dbg_Auto_Duct, env->canFrame.data, + &env->canFrame.dlc, &env->ide); + + + return event_dbg_Auto_Duct_CYC; + } +#endif + +#if (dbg_Auto_Valve_Plus_SEND == 1) + if (env->time_dbg_Auto_Valve_Plus_CYC <= env->timeMs) { + env->time_dbg_Auto_Valve_Plus_CYC = env->timeMs + dbg_Auto_Valve_Plus_CYC; + + env->can_id = Pack_dbg_Auto_Valve_Plus_candb_dbg(&ccu_candb_dbg_tx.dbg_Auto_Valve_Plus, env->canFrame.data, + &env->canFrame.dlc, &env->ide); + + return event_dbg_Auto_Valve_Plus_CYC; + } +#endif + +#if (dbg_CCU_Info_SEND == 1) + if (env->time_dbg_CCU_Info_CYC <= env->timeMs) { + env->time_dbg_CCU_Info_CYC = env->timeMs + dbg_CCU_Info_CYC; + + ++env->dbg_CCU_Info_MultMsg_Idx; + if (env->dbg_CCU_Info_MultMsg_Idx > 1) { + env->dbg_CCU_Info_MultMsg_Idx = 0; + } + + ccu_candb_dbg_tx.dbg_CCU_Info.dbg_Info_MultMsg_Idx = env->dbg_CCU_Info_MultMsg_Idx; + + env->can_id = Pack_dbg_CCU_Info_candb_dbg2(&ccu_candb_dbg_tx.dbg_CCU_Info, env->canFrame.data, + &env->canFrame.dlc, &env->ide); + + + return event_dbg_CCU_Info_CYC; + } +#endif + +#if (dbg_CCU_IO_SEND == 1) + if (env->time_dbg_CCU_IO_CYC < env->timeMs) { + env->time_dbg_CCU_IO_CYC = env->timeMs + dbg_CCU_IO_CYC; + + env->can_id = Pack_dbg_CCU_IO_candb_dbg(&ccu_candb_dbg_tx.dbg_CCU_IO, env->canFrame.data, + &env->canFrame.dlc, &env->ide); + + return event_dbg_CCU_IO_CYC; + } +#endif + +#if (dbg_DiffBlr_ValveOpen_SEND == 1) + if (env->time_dbg_DiffBlr_ValveOpen_CYC <= env->timeMs) { + env->time_dbg_DiffBlr_ValveOpen_CYC = env->timeMs + dbg_DiffBlr_ValveOpen_CYC; + + ccu_candb_dbg_tx.dbg_DiffBlr_ValveOpen.Logic_ValveOpen_MultMsg_Idx = env->dbg_DiffBlr_ValveOpen_MultMsg_Idx; + + env->can_id = Pack_dbg_DiffBlr_ValveOpen_candb_dbg2(&ccu_candb_dbg_tx.dbg_DiffBlr_ValveOpen, env->canFrame.data, + &env->canFrame.dlc, &env->ide); + + ++env->dbg_DiffBlr_ValveOpen_MultMsg_Idx; + if (env->dbg_DiffBlr_ValveOpen_MultMsg_Idx > 3) { + env->dbg_DiffBlr_ValveOpen_MultMsg_Idx = 0; + } + + return event_dbg_DiffBlr_ValveOpen_CYC; + } +#endif + + +#if (dbg_Drs_SEND == 1) + if (env->time_dbg_Drs_CYC <= env->timeMs) { + env->time_dbg_Drs_CYC = env->timeMs + dbg_Drs_CYC; + + env->can_id = Pack_dbg_Drs_candb_dbg(&ccu_candb_dbg_tx.dbg_Drs, env->canFrame.data, + &env->canFrame.dlc, &env->ide); + + return event_dbg_Drs_CYC; + } +#endif + +#if (dbg_Info_Act1_SEND == 1) + if (env->time_dbg_Info_Act1_CYC <= env->timeMs) { + env->time_dbg_Info_Act1_CYC = env->timeMs + dbg_Info_Act1_CYC; + + env->can_id = Pack_dbg_Info_Act1_candb_dbg(&ccu_candb_dbg_tx.dbg_Info_Act1, env->canFrame.data, + &env->canFrame.dlc, &env->ide); + + return event_dbg_Info_Act1_CYC; + } +#endif + +#if (dbg_Info_Act2_SEND == 1) + if (env->time_dbg_Info_Act2_CYC <= env->timeMs) { + env->time_dbg_Info_Act2_CYC = env->timeMs + dbg_Info_Act2_CYC; + + env->can_id = Pack_dbg_Info_Act2_candb_dbg(&ccu_candb_dbg_tx.dbg_Info_Act2, env->canFrame.data, + &env->canFrame.dlc, &env->ide); + + return event_dbg_Info_Act2_CYC; + } +#endif + +#if (dbg_LIN_AirQS_Stat_SEND == 1) + if (env->time_dbg_LIN_AirQS_Stat_CYC <= env->timeMs) { + env->time_dbg_LIN_AirQS_Stat_CYC = env->timeMs + dbg_LIN_AirQS_Stat_CYC; + + env->can_id = Pack_dbg_LIN_AirQS_Stat_candb_dbg(&ccu_candb_dbg_tx.dbg_LIN_AirQS_Stat, env->canFrame.data, + &env->canFrame.dlc, &env->ide); + + return event_dbg_LIN_AirQS_Stat_CYC; + } +#endif + +#if (dbg_LIN_Aroma_Stat_SEND == 1) + if (env->time_dbg_LIN_Aroma_Stat_CYC <= env->timeMs) { + env->time_dbg_LIN_Aroma_Stat_CYC = env->timeMs + dbg_LIN_Aroma_Stat_CYC; + + env->can_id = Pack_dbg_LIN_Aroma_Stat_candb_dbg(&ccu_candb_dbg_tx.dbg_LIN_Aroma_Stat, env->canFrame.data, + &env->canFrame.dlc, &env->ide); + + return event_dbg_LIN_Aroma_Stat_CYC; + } +#endif + +#if (dbg_LIN_DRS_Stat_SEND == 1) + if (env->time_dbg_LIN_DRS_Stat_CYC <= env->timeMs) { + env->time_dbg_LIN_DRS_Stat_CYC = env->timeMs + dbg_LIN_DRS_Stat_CYC; + + env->can_id = Pack_dbg_LIN_DRS_Stat_candb_dbg(&ccu_candb_dbg_tx.dbg_LIN_DRS_Stat, env->canFrame.data, + &env->canFrame.dlc, &env->ide); + + return event_dbg_LIN_DRS_Stat_CYC; + } +#endif + +#if (dbg_LIN_eTXV_Stat_SEND == 1) + if (env->time_dbg_LIN_eTXV_Stat_CYC <= env->timeMs) { + env->time_dbg_LIN_eTXV_Stat_CYC = env->timeMs + dbg_LIN_eTXV_Stat_CYC; + + env->can_id = Pack_dbg_LIN_eTXV_Stat_candb_dbg(&ccu_candb_dbg_tx.dbg_LIN_eTXV_Stat, env->canFrame.data, + &env->canFrame.dlc, &env->ide); + + return event_dbg_LIN_eTXV_Stat_CYC; + } +#endif + +#if (dbg_LIN_Ionizer_Stat_SEND == 1) + if (env->time_dbg_LIN_Ionizer_Stat_CYC <= env->timeMs) { + env->time_dbg_LIN_Ionizer_Stat_CYC = env->timeMs + dbg_LIN_Ionizer_Stat_CYC; + + env->can_id = Pack_dbg_LIN_Ionizer_Stat_candb_dbg(&ccu_candb_dbg_tx.dbg_LIN_Ionizer_Stat, env->canFrame.data, + &env->canFrame.dlc, &env->ide); + + return event_dbg_LIN_Ionizer_Stat_CYC; + } +#endif + +#if (dbg_Logic_Ac_SEND == 1) + if (env->time_dbg_Logic_Ac_CYC <= env->timeMs) { + env->time_dbg_Logic_Ac_CYC = env->timeMs + dbg_Logic_Ac_CYC; + + env->can_id = Pack_dbg_Logic_Ac_candb_dbg(&ccu_candb_dbg_tx.dbg_Logic_Ac, env->canFrame.data, + &env->canFrame.dlc, &env->ide); + + return event_dbg_Logic_Ac_CYC; + } +#endif + +#if (dbg_Logic_Blower_SEND == 1) + if (env->time_dbg_Logic_Blower_CYC <= env->timeMs) { + env->time_dbg_Logic_Blower_CYC = env->timeMs + dbg_Logic_Blower_CYC; + + + env->can_id = Pack_dbg_Logic_Blower_candb_dbg(&ccu_candb_dbg_tx.dbg_Logic_Blower, env->canFrame.data, + &env->canFrame.dlc, &env->ide); + + return event_dbg_Logic_Blower_CYC; + } +#endif + +#if (dbg_Logic_KM_Status_SEND == 1) + if (env->time_dbg_Logic_KM_Status_CYC <= env->timeMs) { + env->time_dbg_Logic_KM_Status_CYC = env->timeMs + dbg_Logic_KM_Status_CYC; + + env->can_id = Pack_dbg_Logic_KM_Status_candb_dbg(&ccu_candb_dbg_tx.dbg_Logic_KM_Status, env->canFrame.data, + &env->canFrame.dlc, &env->ide); + + return event_dbg_Logic_KM_Status_CYC; + } +#endif + +#if (dbg_Logic_Rec_SEND == 1) + if (env->time_dbg_Logic_Rec_CYC <= env->timeMs) { + env->time_dbg_Logic_Rec_CYC = env->timeMs + dbg_Logic_Rec_CYC; + + env->can_id = Pack_dbg_Logic_Rec_candb_dbg(&ccu_candb_dbg_tx.dbg_Logic_Rec, env->canFrame.data, + &env->canFrame.dlc, &env->ide); + + return event_dbg_Logic_Rec_CYC; + } +#endif + +#if (dbg_Logic_State_SEND == 1) + if (env->time_dbg_Logic_State_CYC <= env->timeMs) { + env->time_dbg_Logic_State_CYC = env->timeMs + dbg_Logic_State_CYC; + + env->can_id = Pack_dbg_Logic_State_candb_dbg(&ccu_candb_dbg_tx.dbg_Logic_State, env->canFrame.data, + &env->canFrame.dlc, &env->ide); + + return event_dbg_Logic_State_CYC; + } +#endif + +#if (dbg_Logic_Valve_SEND == 1) + if (env->time_dbg_Logic_Valve_CYC <= env->timeMs) { + env->time_dbg_Logic_Valve_CYC = env->timeMs + dbg_Logic_Valve_CYC; + + env->can_id = Pack_dbg_Logic_Valve_candb_dbg(&ccu_candb_dbg_tx.dbg_Logic_Valve, env->canFrame.data, + &env->canFrame.dlc, &env->ide); + + return event_dbg_Logic_Valve_CYC; + } +#endif + +#if (dbg_Sen_0_SEND == 1) + if (env->time_dbg_Sen_0_CYC <= env->timeMs) { + env->time_dbg_Sen_0_CYC = env->timeMs + dbg_Sen_0_CYC; + + env->can_id = Pack_dbg_Sen_0_candb_dbg(&ccu_candb_dbg_tx.dbg_Sen_0, env->canFrame.data, + &env->canFrame.dlc, &env->ide); + + return event_dbg_Sen_0_CYC; + } +#endif + +#if (dbg_Sen_Amb_SEND == 1) + if (env->time_dbg_Sen_Amb_CYC <= env->timeMs) { + env->time_dbg_Sen_Amb_CYC = env->timeMs + dbg_Sen_Amb_CYC; + + env->can_id = Pack_dbg_Sen_Amb_candb_dbg(&ccu_candb_dbg_tx.dbg_Sen_Amb, env->canFrame.data, + &env->canFrame.dlc, &env->ide); + + return event_dbg_Sen_Amb_CYC; + } +#endif + +#if (dbg_Sen_Demist_SEND == 1) + if (env->time_dbg_Sen_Demist_CYC < env->timeMs) { + env->time_dbg_Sen_Demist_CYC = env->timeMs + dbg_Sen_Demist_CYC; + + env->can_id = Pack_dbg_Sen_Demist_candb_dbg(&ccu_candb_dbg_tx.dbg_Sen_Demist, env->canFrame.data, + &env->canFrame.dlc, &env->ide); + + return event_dbg_Sen_Demist_CYC; + } +#endif + +#if (dbg_Sen_Duct_SEND == 1) + if (env->time_dbg_Sen_Duct_CYC < env->timeMs) { + env->time_dbg_Sen_Duct_CYC = env->timeMs + dbg_Sen_Duct_CYC__; + + if (env->dbg_Sen_Duct_MultMsg_Idx >= 3) { + env->dbg_Sen_Duct_MultMsg_Idx = 0; + } else { + ++env->dbg_Sen_Duct_MultMsg_Idx; + } + + ccu_candb_dbg_tx.dbg_Sen_Duct.dbg_Sen_Duct_MultMsg_Idx = env->dbg_Sen_Duct_MultMsg_Idx; + + env->can_id = Pack_dbg_Sen_Duct_candb_dbg2(&ccu_candb_dbg_tx.dbg_Sen_Duct, env->canFrame.data, + &env->canFrame.dlc, &env->ide); + + return event_dbg_Sen_Duct_CYC; + } +#endif + +#if (dbg_Sen_Eva_SEND == 1) + if (env->time_dbg_Sen_Eva_CYC <= env->timeMs) { + env->time_dbg_Sen_Eva_CYC = env->timeMs + dbg_Sen_Eva_CYC; + + env->can_id = Pack_dbg_Sen_Eva_candb_dbg(&ccu_candb_dbg_tx.dbg_Sen_Eva, env->canFrame.data, &env->canFrame.dlc, + &env->ide); + + return event_dbg_Sen_Eva_CYC; + } +#endif + +#if (dbg_Sen_Incar_SEND == 1) + if (env->time_dbg_Sen_Incar_CYC <= env->timeMs) { + env->time_dbg_Sen_Incar_CYC = env->timeMs + dbg_Sen_Incar_CYC; + + if (env->dbg_Sen_Incar_MultMsg_Idx >= 1) { + env->dbg_Sen_Incar_MultMsg_Idx = 0; + } else { + ++env->dbg_Sen_Incar_MultMsg_Idx; + } + + ccu_candb_dbg_tx.dbg_Sen_Incar.dbg_Sen_Incar_MultMsg_Idx = env->dbg_Sen_Incar_MultMsg_Idx; + + env->can_id = Pack_dbg_Sen_Incar_candb_dbg2(&ccu_candb_dbg_tx.dbg_Sen_Incar, env->canFrame.data, + &env->canFrame.dlc, &env->ide); + + + return event_dbg_Sen_Incar_CYC; + } +#endif + + +#if (dbg_Stat_PID_SEND == 1) + if (env->time_dbg_Stat_PID_CYC <= env->timeMs) { + env->time_dbg_Stat_PID_CYC = env->timeMs + dbg_Stat_PID_SEND_CYC; + + if (env->dbg_PID_MultMsg_Idx >= 5) { + env->dbg_PID_MultMsg_Idx = 0; + } else { + ++env->dbg_PID_MultMsg_Idx; + } + + env->can_id = Pack_dbg_Stat_PID_candb_dbg2(&ccu_candb_dbg_tx.dbg_stat_PID, env->dbg_PID_MultMsg_Idx, env->canFrame.data, + &env->canFrame.dlc, &env->ide); + + return event_dbg_Stat_PID_CYC; + } +#endif + + return event_dbg_none; +} + +void set_DBG_CCU_Mute(tCanSpamDebugTransmitter *env, bool mute) { + if (osMutexAcquire(env->access, 5000) == osOK) { + env->isMute = mute; + osMutexRelease(env->access); + } else { + LoggerErrorStatic(LOGGER, LOG_SIGN, "Access error set_CCU_Mute"); + } +} + +void set_CanDebugSpamTransmitter(tCanSpamDebugTransmitter *env, ccu_candb_dbg_tx_t *p_ccu_candb_dbg_tx_t) { + + uint32_t countQueue_ccu_candb_dbg_tx = osMessageQueueGetSpace(env->queue_ccu_candb_dbg_tx); + + if (countQueue_ccu_candb_dbg_tx) { + osStatus_t status = osMessageQueuePut(env->queue_ccu_candb_dbg_tx, p_ccu_candb_dbg_tx_t, 0, 0U); + } + +} + + +static _Noreturn void CanSpamDebugTransmitter_Thread(tCanSpamDebugTransmitter *env) { + for (;;) { + SystemDelayMs(50); + + osStatus_t status = osMessageQueueGet(env->queue_ccu_candb_dbg_tx, &ccu_candb_dbg_tx, 0, 0); + + if (env->isMute == false) { + + if (osMutexAcquire(env->access, 5000) == osOK) { + + env->timeMs += 50; + + while (isEventTransmitter(env) != event_dbg_none) { + sendEventToCan(env); + } + + + osMutexRelease(env->access); + + } else { + LoggerErrorStatic(LOGGER, LOG_SIGN, "Access error CanSpamDebugTransmitter_Thread"); + } + + } + } +} + +void CanSpamDebugTransmitter_StartThread(tCanSpamDebugTransmitter *env) { + if (!env->thread.id) { + env->thread.id = osThreadNew((osThreadFunc_t) (CanSpamDebugTransmitter_Thread), (void *) (env), + &env->thread.attr); + } +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_CAN_DEBUG_SPAM/CanSpamDebugTransmitter.h b/MODULES/HVAC_M7_CAN_DEBUG_SPAM/CanSpamDebugTransmitter.h new file mode 100644 index 0000000..9f80f47 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_DEBUG_SPAM/CanSpamDebugTransmitter.h @@ -0,0 +1,187 @@ +// +// Created by cfif on 05.12.2025. +// + +#ifndef HVAC_M7_CANSPAMDEBUGTRANSMITTER_H +#define HVAC_M7_CANSPAMDEBUGTRANSMITTER_H + +#include +#include "CanSerialPortFrame.h" +#include "ccu_candb_dbg-binutil.h" +#include "LoggerInterface.h" +#include "CanSpamDebugReceiver.h" + +#define dbg_Act0_SEND 1 +#define dbg_Act1_SEND 1 +#define dbg_Act2_SEND 1 +#define dbg_Auto_AF_SEND 1 +#define dbg_Auto_Duct_SEND 1 +#define dbg_Auto_Valve_Plus_SEND 0 +#define dbg_CCU_Info_SEND 1 +#define dbg_CCU_IO_SEND 1 +#define dbg_DiffBlr_ValveOpen_SEND 0 +#define dbg_Drs_SEND 1 +#define dbg_Info_Act1_SEND 0 +#define dbg_Info_Act2_SEND 0 +#define dbg_LIN_AirQS_Stat_SEND 1 +#define dbg_LIN_Aroma_Stat_SEND 0 +#define dbg_LIN_DRS_Stat_SEND 0 +#define dbg_LIN_eTXV_Stat_SEND 0 +#define dbg_LIN_Ionizer_Stat_SEND 0 +#define dbg_Logic_Ac_SEND 1 +#define dbg_Logic_Blower_SEND 1 +#define dbg_Logic_KM_Status_SEND 0 +#define dbg_Logic_Rec_SEND 1 +#define dbg_Logic_State_SEND 1 +#define dbg_Logic_Valve_SEND 1 +#define dbg_Sen_0_SEND 1 +#define dbg_Sen_Amb_SEND 1 +#define dbg_Sen_Demist_SEND 0 +#define dbg_Sen_Duct_SEND 1 +#define dbg_Sen_Eva_SEND 1 +#define dbg_Sen_Incar_SEND 1 +#define dbg_Stat_PID_SEND 1 + + +#define dbg_Act0_CYC 100 +#define dbg_Act1_CYC 100 +#define dbg_Act2_CYC 100 +#define dbg_Auto_AF_CYC__ 100 +#define dbg_Auto_Duct_CYC__ 100 +#define dbg_Auto_Valve_Plus_CYC 100 +#define dbg_CCU_Info_CYC__ 100 +#define dbg_CCU_IO_CYC 100 +#define dbg_DiffBlr_ValveOpen_CYC__ 100 +#define dbg_Drs_CYC 100 +#define dbg_Info_Act1_CYC 100 +#define dbg_Info_Act2_CYC 100 +#define dbg_LIN_AirQS_Stat_CYC 100 +#define dbg_LIN_Aroma_Stat_CYC 100 +#define dbg_LIN_DRS_Stat_CYC 100 +#define dbg_LIN_eTXV_Stat_CYC 100 +#define dbg_LIN_Ionizer_Stat_CYC 100 +#define dbg_Logic_Ac_CYC 100 +#define dbg_Logic_Blower_CYC 100 +#define dbg_Logic_KM_Status_CYC 100 +#define dbg_Logic_Rec_CYC 100 +#define dbg_Logic_State_CYC 100 +#define dbg_Logic_Valve_CYC 100 +#define dbg_Sen_0_CYC__ 100 +#define dbg_Sen_Amb_CYC 100 +#define dbg_Sen_Demist_CYC 100 +#define dbg_Sen_Duct_CYC__ 100 +#define dbg_Sen_Eva_CYC 100 +#define dbg_Sen_Incar_CYC__ 100 +#define dbg_Stat_PID_SEND_CYC 100 + +typedef enum { + event_dbg_none = 0x00, + event_dbg_Act0_CYC = 0x01, + event_dbg_Act1_CYC = 0x02, + event_dbg_Act2_CYC = 0x03, + event_dbg_Auto_AF_CYC = 0x4, + event_dbg_Auto_Duct_CYC = 0x5, + event_dbg_Auto_Valve_Plus_CYC = 0x6, + event_dbg_CCU_Info_CYC = 0x7, + event_dbg_CCU_IO_CYC = 0x8, + event_dbg_DiffBlr_ValveOpen_CYC = 0x9, + event_dbg_Drs_CYC = 0xA, + event_dbg_Info_Act1_CYC = 0xB, + event_dbg_Info_Act2_CYC = 0xC, + event_dbg_LIN_AirQS_Stat_CYC = 0xD, + event_dbg_LIN_Aroma_Stat_CYC = 0xE, + event_dbg_LIN_DRS_Stat_CYC = 0xF, + event_dbg_LIN_eTXV_Stat_CYC = 0x10, + event_dbg_LIN_Ionizer_Stat_CYC = 0x11, + event_dbg_Logic_Ac_CYC = 0x12, + event_dbg_Logic_Blower_CYC = 0x13, + event_dbg_Logic_KM_Status_CYC = 0x14, + event_dbg_Logic_Rec_CYC = 0x15, + event_dbg_Logic_State_CYC = 0x16, + event_dbg_Logic_Valve_CYC = 0x17, + event_dbg_Sen_0_CYC = 0x18, + event_dbg_Sen_Amb_CYC = 0x19, + event_dbg_Sen_Demist_CYC = 0x1A, + event_dbg_Sen_Duct_CYC = 0x1B, + event_dbg_Sen_Eva_CYC = 0x1C, + event_dbg_Sen_Incar_CYC = 0x1D, + event_dbg_Stat_PID_CYC = 0x1E + +} eTimeEventDbgTransmit; + +typedef struct { + + tSerialPortFrameIO *ioCanFrame; + osMutexId_t access; + can_rx_message_type canFrame; + bool isMute; + + tCanSpamDebugReceiver *canSpamDebugReceiver; + + osMessageQueueId_t queue_ccu_candb_dbg_tx; + + uint32_t can_id; + uint32_t timeMs; + uint8_t ide; + + uint32_t time_dbg_Act0_CYC; + uint32_t time_dbg_Act1_CYC; + uint32_t time_dbg_Act2_CYC; + uint32_t time_dbg_Auto_AF_CYC; + uint32_t time_dbg_Auto_Duct_CYC; + uint32_t time_dbg_Auto_Valve_Plus_CYC; + uint32_t time_dbg_CCU_Info_CYC; + uint32_t time_dbg_CCU_IO_CYC; + uint32_t time_dbg_DiffBlr_ValveOpen_CYC; + uint32_t time_dbg_Drs_CYC; + uint32_t time_dbg_Info_Act1_CYC; + uint32_t time_dbg_Info_Act2_CYC; + uint32_t time_dbg_LIN_AirQS_Stat_CYC; + uint32_t time_dbg_LIN_Aroma_Stat_CYC; + uint32_t time_dbg_LIN_DRS_Stat_CYC; + uint32_t time_dbg_LIN_eTXV_Stat_CYC; + uint32_t time_dbg_LIN_Ionizer_Stat_CYC; + uint32_t time_dbg_Logic_Ac_CYC; + uint32_t time_dbg_Logic_Blower_CYC; + uint32_t time_dbg_Logic_KM_Status_CYC; + uint32_t time_dbg_Logic_Rec_CYC; + uint32_t time_dbg_Logic_State_CYC; + uint32_t time_dbg_Logic_Valve_CYC; + uint32_t time_dbg_Sen_0_CYC; + uint32_t time_dbg_Sen_Amb_CYC; + uint32_t time_dbg_Sen_Demist_CYC; + uint32_t time_dbg_Sen_Duct_CYC; + uint32_t time_dbg_Sen_Eva_CYC; + uint32_t time_dbg_Sen_Incar_CYC; + uint32_t time_dbg_Stat_PID_CYC; + + tLoggerInterface *logger; + + // Индексы для мультиплексированных сообщений + uint8_t dbg_Sen_Duct_MultMsg_Idx; + uint8_t dbg_Sen_Incar_MultMsg_Idx; + uint8_t dbg_DiffBlr_ValveOpen_MultMsg_Idx; + uint8_t dbg_CCU_Info_MultMsg_Idx; + uint8_t dbg_Auto_Duct_MultMsg_Idx; + uint8_t dbg_Auto_AF_MultMsg_Idx; + uint8_t dbg_PID_MultMsg_Idx; + + struct { + osThreadId_t id; + uint32_t stack[384]; + StaticTask_t controlBlock; + osThreadAttr_t attr; + } thread; + +} tCanSpamDebugTransmitter; + +void +CanSpamDebugTransmitter_Init(tCanSpamDebugTransmitter *env, tSerialPortFrameIO *ioCanFrame, + tCanSpamDebugReceiver *canSpamDebugReceiver, tLoggerInterface *logger); + +void CanSpamDebugTransmitter_StartThread(tCanSpamDebugTransmitter *env); + +void set_CanDebugSpamTransmitter(tCanSpamDebugTransmitter *env, ccu_candb_dbg_tx_t *p_ccu_candb_dbg_tx_t ); +void set_DBG_CCU_Mute(tCanSpamDebugTransmitter *env, bool mute); + +#endif //HVAC_M7_CANSPAMDEBUGTRANSMITTER_H \ No newline at end of file diff --git a/MODULES/HVAC_M7_CAN_DEBUG_SPAM/candb_dbg_fixed.c b/MODULES/HVAC_M7_CAN_DEBUG_SPAM/candb_dbg_fixed.c new file mode 100644 index 0000000..9219e05 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_DEBUG_SPAM/candb_dbg_fixed.c @@ -0,0 +1,700 @@ +// candb_dbg_fixed.c +// Исправленные версии функций для мультиплексированных сообщений + +#include "candb_dbg_fixed.h" + +// candb_dbg_fixed.c +// Исправленные версии функций для мультиплексированных сообщений + +#include "candb_dbg_fixed.h" + +// ============================================================================ +// 1. dbg_Sen_Incar - Датчики в салоне (MultMsg_Idx) +// ============================================================================ +/* +uint32_t Pack_dbg_Sen_Incar_candb_dbg2(dbg_Sen_Incar_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; + for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Sen_Incar_DLC); + _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + switch(_m->dbg_Sen_Incar_MultMsg_Idx) { + case 0: // Кадр 0: Raw_FL и FL + _d[0] |= (uint8_t)((_m->dbg_Sen_Incar_MultMsg_Idx & 0x03) | + ((_m->dbg_Sen_Incar_Raw_FL_ro & 0x0F) << 4)); + _d[1] |= (uint8_t)((_m->dbg_Sen_Incar_Raw_FL_ro >> 4) & 0xFF); + _d[2] |= (uint8_t)(_m->dbg_Sen_Incar_FL_ro & 0xFF); + _d[3] |= (uint8_t)(((_m->dbg_Sen_Incar_FL_ro >> 8) & 0x0F) | + ((_m->dbg_Sen_Incar_Raw_FR_ro & 0x0F) << 4)); + _d[4] |= (uint8_t)((_m->dbg_Sen_Incar_Raw_FR_ro >> 4) & 0xFF); + _d[5] |= (uint8_t)(_m->dbg_Sen_Incar_FR_ro & 0xFF); + _d[6] |= (uint8_t)((_m->dbg_Sen_Incar_FR_ro >> 8) & 0x0F); + break; + + case 1: // Кадр 1: FR и Raw_FR + _d[0] |= (uint8_t)((_m->dbg_Sen_Incar_MultMsg_Idx & 0x03) | + ((_m->dbg_Sen_Incar_FR_ro & 0x0F) << 4)); + _d[1] |= (uint8_t)((_m->dbg_Sen_Incar_FR_ro >> 4) & 0xFF); + _d[2] |= (uint8_t)(_m->dbg_Sen_Incar_Raw_FR_ro & 0xFF); + _d[3] |= (uint8_t)(((_m->dbg_Sen_Incar_Raw_FR_ro >> 8) & 0x0F) | + ((_m->dbg_Sen_Incar_Raw_RL_ro & 0x0F) << 4)); + _d[4] |= (uint8_t)((_m->dbg_Sen_Incar_Raw_RL_ro >> 4) & 0xFF); + _d[5] |= (uint8_t)(_m->dbg_Sen_Incar_RL_ro & 0xFF); + _d[6] |= (uint8_t)((_m->dbg_Sen_Incar_RL_ro >> 8) & 0x0F); + break; + + case 2: // Кадр 2: Raw_RL и RL + _d[0] |= (uint8_t)((_m->dbg_Sen_Incar_MultMsg_Idx & 0x03) | + ((_m->dbg_Sen_Incar_Raw_RL_ro & 0x0F) << 4)); + _d[1] |= (uint8_t)((_m->dbg_Sen_Incar_Raw_RL_ro >> 4) & 0xFF); + _d[2] |= (uint8_t)(_m->dbg_Sen_Incar_RL_ro & 0xFF); + _d[3] |= (uint8_t)(((_m->dbg_Sen_Incar_RL_ro >> 8) & 0x0F) | + ((_m->dbg_Sen_Incar_Raw_RR_ro & 0x0F) << 4)); + _d[4] |= (uint8_t)((_m->dbg_Sen_Incar_Raw_RR_ro >> 4) & 0xFF); + _d[5] |= (uint8_t)(_m->dbg_Sen_Incar_RR_ro & 0xFF); + _d[6] |= (uint8_t)((_m->dbg_Sen_Incar_RR_ro >> 8) & 0x0F); + break; + + case 3: // Кадр 3: RR и Raw_RR + _d[0] |= (uint8_t)((_m->dbg_Sen_Incar_MultMsg_Idx & 0x03) | + ((_m->dbg_Sen_Incar_RR_ro & 0x0F) << 4)); + _d[1] |= (uint8_t)((_m->dbg_Sen_Incar_RR_ro >> 4) & 0xFF); + _d[2] |= (uint8_t)(_m->dbg_Sen_Incar_Raw_RR_ro & 0xFF); + _d[3] |= (uint8_t)(((_m->dbg_Sen_Incar_Raw_RR_ro >> 8) & 0x0F)); + break; + } + + *_len = (uint8_t) dbg_Sen_Incar_DLC; + *_ide = (uint8_t) dbg_Sen_Incar_IDE; + return dbg_Sen_Incar_CANID; +} +*/ + + + + +uint32_t Pack_dbg_Stat_PID_candb_dbg2(dbg_Stat_PID_t *_m, uint8_t dbg_PID_MultMsg_Idx, uint8_t *_d, uint8_t *_len, + uint8_t *_ide) { + uint8_t i; + for (i = 0u; i < 8; + _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + dbg_Stat_PID_Frame0_t *dbg_Stat_PID_Frame0 = (dbg_Stat_PID_Frame0_t *) _d; + + switch (dbg_PID_MultMsg_Idx) { + case 0: + dbg_Stat_PID_Frame0->dbg_PID_MultMsg_Idx = dbg_PID_MultMsg_Idx; + dbg_Stat_PID_Frame0->dbg_P = _m->P_FUL; + dbg_Stat_PID_Frame0->dbg_I = _m->I_FUL; + dbg_Stat_PID_Frame0->dbg_D = _m->D_FUL; + break; + + case 1: + dbg_Stat_PID_Frame0->dbg_PID_MultMsg_Idx = dbg_PID_MultMsg_Idx; + dbg_Stat_PID_Frame0->dbg_P = _m->P_FUR; + dbg_Stat_PID_Frame0->dbg_I = _m->I_FUR; + dbg_Stat_PID_Frame0->dbg_D = _m->D_FUR; + break; + + case 2: + dbg_Stat_PID_Frame0->dbg_PID_MultMsg_Idx = dbg_PID_MultMsg_Idx; + dbg_Stat_PID_Frame0->dbg_P = _m->P_FLL; + dbg_Stat_PID_Frame0->dbg_I = _m->I_FLL; + dbg_Stat_PID_Frame0->dbg_D = _m->D_FLL; + break; + + case 3: + dbg_Stat_PID_Frame0->dbg_PID_MultMsg_Idx = dbg_PID_MultMsg_Idx; + dbg_Stat_PID_Frame0->dbg_P = _m->P_FRL; + dbg_Stat_PID_Frame0->dbg_I = _m->I_FRL; + dbg_Stat_PID_Frame0->dbg_D = _m->D_FRL; + break; + + case 4: + dbg_Stat_PID_Frame0->dbg_PID_MultMsg_Idx = dbg_PID_MultMsg_Idx; + dbg_Stat_PID_Frame0->dbg_P = _m->P_RL; + dbg_Stat_PID_Frame0->dbg_I = _m->I_RL; + dbg_Stat_PID_Frame0->dbg_D = _m->D_RL; + break; + + case 5: + dbg_Stat_PID_Frame0->dbg_PID_MultMsg_Idx = dbg_PID_MultMsg_Idx; + dbg_Stat_PID_Frame0->dbg_P = _m->P_RR; + dbg_Stat_PID_Frame0->dbg_I = _m->I_RR; + dbg_Stat_PID_Frame0->dbg_D = _m->D_RR; + break; + } + + + *_len = 8; + *_ide = 0; + + return (0x3f7U); +} + +uint32_t Pack_dbg_Sen_Incar_candb_dbg2(dbg_Sen_Incar_t *_m, uint8_t *_d, uint8_t *_len, uint8_t *_ide) { + uint8_t i; + for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Sen_Incar_DLC); + _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + dbg_Sen_Incar_Frame0_t *dbg_Sen_Incar_Frame0 = (dbg_Sen_Incar_Frame0_t *) _d; + + switch (_m->dbg_Sen_Incar_MultMsg_Idx) { + case 0: + + dbg_Sen_Incar_Frame0->dbg_Sen_Incar_MultMsg_Idx = _m->dbg_Sen_Incar_MultMsg_Idx; + dbg_Sen_Incar_Frame0->reserved0 = 0; + + dbg_Sen_Incar_Frame0->value1 = _m->dbg_Sen_Incar_FL_ro; + dbg_Sen_Incar_Frame0->value2 = _m->dbg_Sen_Incar_FR_ro; + dbg_Sen_Incar_Frame0->value3 = _m->dbg_Sen_Incar_RL_ro; + dbg_Sen_Incar_Frame0->value4 = _m->dbg_Sen_Incar_RR_ro; + + break; + + case 1: + dbg_Sen_Incar_Frame0->dbg_Sen_Incar_MultMsg_Idx = _m->dbg_Sen_Incar_MultMsg_Idx; + dbg_Sen_Incar_Frame0->reserved0 = 0; + + dbg_Sen_Incar_Frame0->value1 = _m->dbg_Sen_Incar_Raw_FL_ro; + dbg_Sen_Incar_Frame0->value2 = _m->dbg_Sen_Incar_Raw_FR_ro; + dbg_Sen_Incar_Frame0->value3 = _m->dbg_Sen_Incar_Raw_RL_ro; + dbg_Sen_Incar_Frame0->value4 = _m->dbg_Sen_Incar_Raw_RR_ro; + break; + + } + + *_len = (uint8_t)dbg_Sen_Incar_DLC; + *_ide = (uint8_t)dbg_Sen_Incar_IDE; + return dbg_Sen_Incar_CANID; +} + + + +// ============================================================================ +// 2. dbg_DiffBlr_ValveOpen - Открытие клапанов DiffBlr (MultMsg_Idx) +// ============================================================================ + +uint32_t Pack_dbg_DiffBlr_ValveOpen_candb_dbg2(dbg_DiffBlr_ValveOpen_t *_m, uint8_t *_d, uint8_t *_len, uint8_t *_ide) { + uint8_t i; + for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_DiffBlr_ValveOpen_DLC); + _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t)(_m->Logic_ValveOpen_MultMsg_Idx & 0x03); + + switch (_m->Logic_ValveOpen_MultMsg_Idx) { + case 0: // Кадр 0: SFL позиции + _d[1] |= (uint8_t)(_m->Logic_ValveOpen_R2_SFL & 0xFF); + _d[2] |= (uint8_t)(_m->Logic_ValveOpen_R1_SFL & 0xFF); + break; + + case 1: // Кадр 1: CFL позиции + _d[1] |= (uint8_t)(_m->Logic_ValveOpen_R2_CFL & 0xFF); + _d[2] |= (uint8_t)(_m->Logic_ValveOpen_R1_CFL & 0xFF); + break; + + case 2: // Кадр 2: CFR позиции + _d[3] |= (uint8_t)(_m->Logic_ValveOpen_R2_CFR & 0xFF); + _d[4] |= (uint8_t)(_m->Logic_ValveOpen_R1_CFR & 0xFF); + break; + + case 3: // Кадр 3: SFR позиции + _d[3] |= (uint8_t)(_m->Logic_ValveOpen_R2_SFR & 0xFF); + _d[4] |= (uint8_t)(_m->Logic_ValveOpen_R1_SFR & 0xFF); + break; + } + + *_len = (uint8_t)dbg_DiffBlr_ValveOpen_DLC; + *_ide = (uint8_t)dbg_DiffBlr_ValveOpen_IDE; + return dbg_DiffBlr_ValveOpen_CANID; +} + +// ============================================================================ +// 3. dbg_CCU_Info - Информация о CCU (MultMsg_Idx) +// ============================================================================ + +#include "DataNonVolatile.h" +#include "FirmwareMetadataSection.h" +#include "Rs_Cal_Base.h" +#include "StatusData.h" + +static uint8_t hex_to_bcd(uint8_t hex_num) { +// uint8_t high = (hex_num >> 4) & 0x0F; // Старшая цифра +// uint8_t low = hex_num & 0x0F; // Младшая цифра +// return high * 10 + low; + return hex_num; +} + +uint32_t Pack_dbg_CCU_Info_candb_dbg2(dbg_CCU_Info_t *_m, uint8_t *_d, uint8_t *_len, uint8_t *_ide) { + uint8_t i; + for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_CCU_Info_DLC); + _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + dbg_CCU_Info_Frame0_t *dbg_CCU_Info_Frame0 = (dbg_CCU_Info_Frame0_t *) _d; + dbg_CCU_Info_Frame1_t *dbg_CCU_Info_Frame1 = (dbg_CCU_Info_Frame1_t *) _d; + + tFirmwareMetaMap *firmwareMetaMap_Main = (tFirmwareMetaMap *) ADR_META_MAIN; + +// _d[0] |= (uint8_t)(_m->dbg_Info_MultMsg_Idx & 0x03); + + switch (_m->dbg_Info_MultMsg_Idx) { + case 0: // Кадр 0: Информация о калибровке + dbg_CCU_Info_Frame0->dbg_Info_MultMsg_Idx = _m->dbg_Info_MultMsg_Idx; + dbg_CCU_Info_Frame0->dbg_Info_CCU_SW_Ver_Date = + (hex_to_bcd(firmwareMetaMap_Main->internal_SW_Version.SW.year) * 10000) + + (hex_to_bcd(firmwareMetaMap_Main->internal_SW_Version.SW.month) * 100) + + hex_to_bcd(firmwareMetaMap_Main->internal_SW_Version.SW.day); + dbg_CCU_Info_Frame0->dbg_Info_CCU_SW_Ver_Rev = firmwareMetaMap_Main->internal_SW_Version.SW.revision; + dbg_CCU_Info_Frame0->dbg_Info_ActivatedCAL = 0; + dbg_CCU_Info_Frame0->dbg_Info_CCU_Aroma_Cfg = statusData.ecu.Status_CCU_Configuration.AromaConfiguration; + dbg_CCU_Info_Frame0->dbg_Info_CCU_Algorithm_Cfg = statusData.ecu.Status_CCU_Configuration.AlgorithmConfiguration; + dbg_CCU_Info_Frame0->reserved0 = 0; + dbg_CCU_Info_Frame0->dbg_Info_VehicleBody = 0; + + // _d[0] |= (uint8_t)((_m->dbg_Info_Calibration_Ver_Date & 0x3F) << 2); + // _d[1] |= (uint8_t)((_m->dbg_Info_Calibration_Ver_Date >> 6) & 0xFF); + // _d[2] |= (uint8_t)((_m->dbg_Info_Calibration_Ver_Date >> 14) & 0xFF); + // _d[3] |= (uint8_t)(_m->dbg_Info_Calibration_Ver_Rev & 0xFF); + break; + + case 1: // Кадр 1: Информация о SW + dbg_CCU_Info_Frame1->dbg_Info_MultMsg_Idx = _m->dbg_Info_MultMsg_Idx; + dbg_CCU_Info_Frame1->dbg_Info_Calibration_Ver_Date = + (g_aucCAL_FP_DATE[0] * 10000) + + (g_aucCAL_FP_DATE[1] * 100) + + g_aucCAL_FP_DATE[2]; //2 + dbg_CCU_Info_Frame1->dbg_Info_Calibration_Ver_Rev = g_aucCAL_VERSION[1]; //24 + dbg_CCU_Info_Frame1->reserved0 = 0; + dbg_CCU_Info_Frame1->dbg_Info_MBD_Ver_Date = + (hex_to_bcd(firmwareMetaMap_Main->internal_SW_Version.MDB.year) * 10000) + + (hex_to_bcd(firmwareMetaMap_Main->internal_SW_Version.MDB.month) * 100) + + hex_to_bcd(firmwareMetaMap_Main->internal_SW_Version.MDB.day); //34 + dbg_CCU_Info_Frame1->dbg_Info_MBD_Ver_Rev = firmwareMetaMap_Main->internal_SW_Version.MDB.revision;;//56 + + // _d[0] |= (uint8_t)((_m->dbg_Info_CCU_SW_Ver_Date & 0x3F) << 2); + // _d[1] |= (uint8_t)((_m->dbg_Info_CCU_SW_Ver_Date >> 6) & 0xFF); + // _d[2] |= (uint8_t)((_m->dbg_Info_CCU_SW_Ver_Date >> 14) & 0xFF); + // _d[3] |= (uint8_t)(_m->dbg_Info_CCU_SW_Ver_Rev & 0xFF); + break; + + case 2: // Кадр 2: Конфигурация и MBD версия + // _d[4] |= (uint8_t)(_m->dbg_Info_ActivatedCAL & 0x0F); + // _d[4] |= (uint8_t)((_m->dbg_Info_CCU_Aroma_Cfg & 0x0F) << 4); + // _d[5] |= (uint8_t)(_m->dbg_Info_CCU_Algorithm_Cfg & 0x0F); + // _d[5] |= (uint8_t)((_m->dbg_Info_MBD_Ver_Date & 0x3F) << 2); + // _d[6] |= (uint8_t)((_m->dbg_Info_MBD_Ver_Date >> 6) & 0xFF); + // _d[7] |= (uint8_t)((_m->dbg_Info_MBD_Ver_Date >> 14) & 0xFF); + // _d[7] |= (uint8_t)(_m->dbg_Info_MBD_Ver_Rev & 0xFF); + break; + + case 3: // Кадр 3: Информация о кузове + // _d[6] |= (uint8_t)(_m->dbg_Info_VehicleBody & 0xFF); + // _d[7] |= (uint8_t)((_m->dbg_Info_VehicleBody >> 8) & 0xFF); + break; + } + + *_len = (uint8_t)dbg_CCU_Info_DLC; + *_ide = (uint8_t)dbg_CCU_Info_IDE; + return dbg_CCU_Info_CANID; +} + +// ============================================================================ +// 4. dbg_Sen_Duct - Датчики воздуховодов (MultMsg_Idx) +// ============================================================================ +/* +uint32_t Pack_dbg_Sen_Duct_candb_dbg2(dbg_Sen_Duct_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; + for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Sen_Duct_DLC); + _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t)(_m->dbg_Sen_Duct_MultMsg_Idx & 0x03); + + switch(_m->dbg_Sen_Duct_MultMsg_Idx) { + case 0: // Кадр 0: Данные передних верхних датчиков + _d[0] |= (uint8_t)(((_m->dbg_Sen_Duct_FL_Upper_Tgt_ro & 0x0F) << 4)); + _d[1] |= (uint8_t)((_m->dbg_Sen_Duct_FL_Upper_Tgt_ro >> 4) & 0xFF); + _d[2] |= (uint8_t)(_m->dbg_Sen_Duct_FL_Upper_Fb_ro & 0xFF); + _d[3] |= (uint8_t)((_m->dbg_Sen_Duct_FL_Upper_Fb_ro >> 8) & 0x0F); + _d[3] |= (uint8_t)((_m->dbg_Sen_Duct_FR_Upper_Tgt_ro & 0x0F) << 4); + _d[4] |= (uint8_t)((_m->dbg_Sen_Duct_FR_Upper_Tgt_ro >> 4) & 0xFF); + _d[5] |= (uint8_t)(_m->dbg_Sen_Duct_FR_Upper_Fb_ro & 0xFF); + _d[6] |= (uint8_t)((_m->dbg_Sen_Duct_FR_Upper_Fb_ro >> 8) & 0x0F); + break; + + case 1: // Кадр 1: Данные задних датчиков и боковых + _d[0] |= (uint8_t)(((_m->dbg_Sen_Duct_RL_Tgt_ro & 0x0F) << 4)); + _d[1] |= (uint8_t)((_m->dbg_Sen_Duct_RL_Tgt_ro >> 4) & 0xFF); + _d[2] |= (uint8_t)(_m->dbg_Sen_Duct_RL_Fb_ro & 0xFF); + _d[3] |= (uint8_t)((_m->dbg_Sen_Duct_RL_Fb_ro >> 8) & 0x0F); + _d[3] |= (uint8_t)((_m->dbg_Sen_Duct_RR_Tgt_ro & 0x0F) << 4); + _d[4] |= (uint8_t)((_m->dbg_Sen_Duct_RR_Tgt_ro >> 4) & 0xFF); + _d[5] |= (uint8_t)(_m->dbg_Sen_Duct_RR_Fb_ro & 0xFF); + _d[6] |= (uint8_t)((_m->dbg_Sen_Duct_RR_Fb_ro >> 8) & 0x0F); + _d[6] |= (uint8_t)((_m->dbg_Sen_Duct_FL_Side_Fb_ro & 0x0F) << 4); + _d[7] |= (uint8_t)((_m->dbg_Sen_Duct_FL_Side_Fb_ro >> 4) & 0xFF); + _d[7] |= (uint8_t)((_m->dbg_Sen_Duct_FR_Side_Fb_ro & 0x0F) << 4); + break; + + case 2: // Кадр 2: Данные нижних передних датчиков + _d[0] |= (uint8_t)(((_m->dbg_Sen_Duct_FL_Lower_Tgt_ro & 0x0F) << 4)); + _d[1] |= (uint8_t)((_m->dbg_Sen_Duct_FL_Lower_Tgt_ro >> 4) & 0xFF); + _d[2] |= (uint8_t)(_m->dbg_Sen_Duct_FL_Lower_Fb_ro & 0xFF); + _d[3] |= (uint8_t)((_m->dbg_Sen_Duct_FL_Lower_Fb_ro >> 8) & 0x0F); + _d[3] |= (uint8_t)((_m->dbg_Sen_Duct_FR_Lower_Tgt_ro & 0x0F) << 4); + _d[4] |= (uint8_t)((_m->dbg_Sen_Duct_FR_Lower_Tgt_ro >> 4) & 0xFF); + _d[5] |= (uint8_t)(_m->dbg_Sen_Duct_FR_Lower_Fb_ro & 0xFF); + _d[6] |= (uint8_t)((_m->dbg_Sen_Duct_FR_Lower_Fb_ro >> 8) & 0x0F); + _d[6] |= (uint8_t)((_m->dbg_Sen_Duct_RL_Side_Fb_ro & 0x0F) << 4); + _d[7] |= (uint8_t)((_m->dbg_Sen_Duct_RL_Side_Fb_ro >> 4) & 0xFF); + _d[7] |= (uint8_t)((_m->dbg_Sen_Duct_RR_Side_Fb_ro & 0x0F) << 4); + break; + + case 3: // Кадр 3: Данные боковых датчиков + _d[0] |= (uint8_t)(((_m->dbg_Sen_Duct_FR_Side_Fb_ro & 0x0F) << 4)); + _d[1] |= (uint8_t)((_m->dbg_Sen_Duct_FR_Side_Fb_ro >> 4) & 0xFF); + _d[2] |= (uint8_t)(_m->dbg_Sen_Duct_RR_Side_Fb_ro & 0xFF); + _d[3] |= (uint8_t)((_m->dbg_Sen_Duct_RR_Side_Fb_ro >> 8) & 0x0F); + _d[3] |= (uint8_t)((_m->dbg_Sen_Duct_FL_Side_Fb_ro & 0x0F) << 4); + _d[4] |= (uint8_t)((_m->dbg_Sen_Duct_FL_Side_Fb_ro >> 4) & 0xFF); + _d[5] |= (uint8_t)(_m->dbg_Sen_Duct_RL_Side_Fb_ro & 0xFF); + _d[6] |= (uint8_t)((_m->dbg_Sen_Duct_RL_Side_Fb_ro >> 8) & 0x0F); + break; + } + + *_len = (uint8_t) dbg_Sen_Duct_DLC; + *_ide = (uint8_t) dbg_Sen_Duct_IDE; + return dbg_Sen_Duct_CANID; +} +*/ + +uint32_t Pack_dbg_Sen_Duct_candb_dbg2(dbg_Sen_Duct_t *_m, uint8_t *_d, uint8_t *_len, uint8_t *_ide) { + uint8_t i; + for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Sen_Duct_DLC); + _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + dbg_Sen_Duct_Frame0_t *dbg_Sen_Duct_Frame0 = (dbg_Sen_Duct_Frame0_t *) _d; + + switch (_m->dbg_Sen_Duct_MultMsg_Idx) { + case 0: // Кадр 0: Данные передних верхних датчиков + + dbg_Sen_Duct_Frame0->dbg_Sen_Duct_MultMsg_Idx = _m->dbg_Sen_Duct_MultMsg_Idx; + dbg_Sen_Duct_Frame0->reserved0 = 0; + dbg_Sen_Duct_Frame0->select = _m->dbg_Sen_Duct_FL_Fb_Select; + + dbg_Sen_Duct_Frame0->value1 = _m->dbg_Sen_Duct_FL_Upper_Tgt_ro; + dbg_Sen_Duct_Frame0->value2 = _m->dbg_Sen_Duct_FL_Upper_Fb_ro; + dbg_Sen_Duct_Frame0->value3 = _m->dbg_Sen_Duct_FL_Side_Fb_ro; + dbg_Sen_Duct_Frame0->value4 = _m->dbg_Sen_Duct_FL_Lower_Tgt_ro; + dbg_Sen_Duct_Frame0->value5 = _m->dbg_Sen_Duct_FL_Lower_Fb_ro; + + break; + + case 1: // Кадр 1: Данные задних датчиков и боковых + dbg_Sen_Duct_Frame0->dbg_Sen_Duct_MultMsg_Idx = _m->dbg_Sen_Duct_MultMsg_Idx; + dbg_Sen_Duct_Frame0->reserved0 = 0; + dbg_Sen_Duct_Frame0->select = _m->dbg_Sen_Duct_FR_Fb_Select; + + dbg_Sen_Duct_Frame0->value1 = _m->dbg_Sen_Duct_FR_Upper_Tgt_ro; + dbg_Sen_Duct_Frame0->value2 = _m->dbg_Sen_Duct_FR_Upper_Fb_ro; + dbg_Sen_Duct_Frame0->value3 = _m->dbg_Sen_Duct_FR_Side_Fb_ro; + dbg_Sen_Duct_Frame0->value4 = _m->dbg_Sen_Duct_FR_Lower_Tgt_ro; + dbg_Sen_Duct_Frame0->value5 = _m->dbg_Sen_Duct_FR_Lower_Fb_ro; + break; + + case 2: // Кадр 2: Данные нижних передних датчиков + dbg_Sen_Duct_Frame0->dbg_Sen_Duct_MultMsg_Idx = _m->dbg_Sen_Duct_MultMsg_Idx; + dbg_Sen_Duct_Frame0->reserved0 = 0; + dbg_Sen_Duct_Frame0->select = _m->dbg_Sen_Duct_RL_Fb_Select; + + dbg_Sen_Duct_Frame0->value1 = _m->dbg_Sen_Duct_RL_Tgt_ro; + dbg_Sen_Duct_Frame0->value2 = _m->dbg_Sen_Duct_RL_Fb_ro; + dbg_Sen_Duct_Frame0->value3 = _m->dbg_Sen_Duct_RL_Side_Fb_ro; + dbg_Sen_Duct_Frame0->value4 = 0; + dbg_Sen_Duct_Frame0->value5 = 0; + break; + + case 3: // Кадр 3: Данные боковых датчиков + dbg_Sen_Duct_Frame0->dbg_Sen_Duct_MultMsg_Idx = _m->dbg_Sen_Duct_MultMsg_Idx; + dbg_Sen_Duct_Frame0->reserved0 = 0; + dbg_Sen_Duct_Frame0->select = _m->dbg_Sen_Duct_RR_Fb_Select; + + dbg_Sen_Duct_Frame0->value1 = _m->dbg_Sen_Duct_RR_Tgt_ro; + dbg_Sen_Duct_Frame0->value2 = _m->dbg_Sen_Duct_RR_Fb_ro; + dbg_Sen_Duct_Frame0->value3 = _m->dbg_Sen_Duct_RR_Side_Fb_ro; + dbg_Sen_Duct_Frame0->value4 = 0; + dbg_Sen_Duct_Frame0->value5 = 0; + break; + } + + *_len = (uint8_t)dbg_Sen_Duct_DLC; + *_ide = (uint8_t)dbg_Sen_Duct_IDE; + return dbg_Sen_Duct_CANID; +} + + +// ============================================================================ +// 5. dbg_Auto_Duct - Автоматические воздуховоды (MultMsg_Idx) +// ============================================================================ + +uint32_t Pack_dbg_Auto_Duct_candb_dbg2(dbg_Auto_Duct_t *_m, uint8_t *_d, uint8_t *_len, uint8_t *_ide) { + uint8_t i; + for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Auto_Duct_DLC); + _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + + dbg_Auto_Duct_Frame0_t *dbg_Auto_Duct_Frame0 = (dbg_Auto_Duct_Frame0_t *) _d; + dbg_Auto_Duct_Multi_6_Frame0_t *dbg_Auto_Duct_Multi_6_Frame0 = (dbg_Auto_Duct_Multi_6_Frame0_t *) _d; + +// _d[0] |= (uint8_t) (_m->dbg_Auto_Duct_MultMsg_Idx & 0x0F); + + switch (_m->dbg_Auto_Duct_MultMsg_Idx) { + case 0: // Кадр 0: FL верхние параметры + dbg_Auto_Duct_Frame0->dbg_Auto_Duct_MultMsg_Idx = _m->dbg_Auto_Duct_MultMsg_Idx; + dbg_Auto_Duct_Frame0->value1 = _m->dbg_Auto_Duct_Tgt_FL_Upper_ro; + dbg_Auto_Duct_Frame0->value2 = _m->dbg_Auto_Duct_Tg_FL_Upper_ro; + dbg_Auto_Duct_Frame0->value3 = _m->dbg_Auto_Duct_Incar_FL_Upper_ro; + dbg_Auto_Duct_Frame0->value4 = _m->dbg_Auto_Duct_Amb_FL_Upper_ro; + dbg_Auto_Duct_Frame0->value5 = _m->dbg_Auto_Duct_Sun_FL_Upper_ro; +/* + _d[0] |= (uint8_t) ((_m->dbg_Auto_Duct_Tgt_FL_Upper_ro & 0x0F) << 4); + _d[1] |= (uint8_t) ((_m->dbg_Auto_Duct_Tgt_FL_Upper_ro >> 4) & 0xFF); + _d[2] |= (uint8_t) (_m->dbg_Auto_Duct_Tg_FL_Upper_ro & 0xFF); + _d[3] |= (uint8_t) ((_m->dbg_Auto_Duct_Tg_FL_Upper_ro >> 8) & 0x0F); + _d[3] |= (uint8_t) ((_m->dbg_Auto_Duct_Incar_FL_Upper_ro & 0x0F) << 4); + _d[4] |= (uint8_t) ((_m->dbg_Auto_Duct_Incar_FL_Upper_ro >> 4) & 0xFF); + _d[5] |= (uint8_t) (_m->dbg_Auto_Duct_Amb_FL_Upper_ro & 0xFF); + _d[6] |= (uint8_t) ((_m->dbg_Auto_Duct_Amb_FL_Upper_ro >> 8) & 0x0F); + _d[6] |= (uint8_t) ((_m->dbg_Auto_Duct_Sun_FL_Upper_ro & 0x0F) << 4); + _d[7] |= (uint8_t) ((_m->dbg_Auto_Duct_Sun_FL_Upper_ro >> 4) & 0xFF); + */ + break; + + case 1: // Кадр 1: FR верхние параметры + dbg_Auto_Duct_Frame0->dbg_Auto_Duct_MultMsg_Idx = _m->dbg_Auto_Duct_MultMsg_Idx; + dbg_Auto_Duct_Frame0->value1 = _m->dbg_Auto_Duct_Tgt_FR_Upper_ro; + dbg_Auto_Duct_Frame0->value2 = _m->dbg_Auto_Duct_Tg_FR_Upper_ro; + dbg_Auto_Duct_Frame0->value3 = _m->dbg_Auto_Duct_Incar_FR_Upper_ro; + dbg_Auto_Duct_Frame0->value4 = _m->dbg_Auto_Duct_Amb_FR_Upper_ro; + dbg_Auto_Duct_Frame0->value5 = _m->dbg_Auto_Duct_Sun_FR_Upper_ro; + /* + _d[0] |= (uint8_t) ((_m->dbg_Auto_Duct_Tgt_FR_Upper_ro & 0x0F) << 4); + _d[1] |= (uint8_t) ((_m->dbg_Auto_Duct_Tgt_FR_Upper_ro >> 4) & 0xFF); + _d[2] |= (uint8_t) (_m->dbg_Auto_Duct_Tg_FR_Upper_ro & 0xFF); + _d[3] |= (uint8_t) ((_m->dbg_Auto_Duct_Tg_FR_Upper_ro >> 8) & 0x0F); + _d[3] |= (uint8_t) ((_m->dbg_Auto_Duct_Incar_FR_Upper_ro & 0x0F) << 4); + _d[4] |= (uint8_t) ((_m->dbg_Auto_Duct_Incar_FR_Upper_ro >> 4) & 0xFF); + _d[5] |= (uint8_t) (_m->dbg_Auto_Duct_Amb_FR_Upper_ro & 0xFF); + _d[6] |= (uint8_t) ((_m->dbg_Auto_Duct_Amb_FR_Upper_ro >> 8) & 0x0F); + _d[6] |= (uint8_t) ((_m->dbg_Auto_Duct_Sun_FR_Upper_ro & 0x0F) << 4); + _d[7] |= (uint8_t) ((_m->dbg_Auto_Duct_Sun_FR_Upper_ro >> 4) & 0xFF); + */ + break; + + case 2: // Кадр 2: FL нижние параметры + dbg_Auto_Duct_Frame0->dbg_Auto_Duct_MultMsg_Idx = _m->dbg_Auto_Duct_MultMsg_Idx; + dbg_Auto_Duct_Frame0->value1 = _m->dbg_Auto_Duct_Tgt_FL_Lower_ro; + dbg_Auto_Duct_Frame0->value2 = _m->dbg_Auto_Duct_Tg_FL_Lower_ro; + dbg_Auto_Duct_Frame0->value3 = _m->dbg_Auto_Duct_Incar_FL_Lower_ro; + dbg_Auto_Duct_Frame0->value4 = _m->dbg_Auto_Duct_Amb_FL_Lower_ro; + dbg_Auto_Duct_Frame0->value5 = _m->dbg_Auto_Duct_Sun_FL_Lower_ro; + /* + _d[0] |= (uint8_t) ((_m->dbg_Auto_Duct_Tgt_FL_Lower_ro & 0x0F) << 4); + _d[1] |= (uint8_t) ((_m->dbg_Auto_Duct_Tgt_FL_Lower_ro >> 4) & 0xFF); + _d[2] |= (uint8_t) (_m->dbg_Auto_Duct_Tg_FL_Lower_ro & 0xFF); + _d[3] |= (uint8_t) ((_m->dbg_Auto_Duct_Tg_FL_Lower_ro >> 8) & 0x0F); + _d[3] |= (uint8_t) ((_m->dbg_Auto_Duct_Incar_FL_Lower_ro & 0x0F) << 4); + _d[4] |= (uint8_t) ((_m->dbg_Auto_Duct_Incar_FL_Lower_ro >> 4) & 0xFF); + _d[5] |= (uint8_t) (_m->dbg_Auto_Duct_Amb_FL_Lower_ro & 0xFF); + _d[6] |= (uint8_t) ((_m->dbg_Auto_Duct_Amb_FL_Lower_ro >> 8) & 0x0F); + _d[6] |= (uint8_t) ((_m->dbg_Auto_Duct_Sun_FL_Lower_ro & 0x0F) << 4); + _d[7] |= (uint8_t) ((_m->dbg_Auto_Duct_Sun_FL_Lower_ro >> 4) & 0xFF); + */ + break; + + case 3: // Кадр 3: FR нижние параметры + dbg_Auto_Duct_Frame0->dbg_Auto_Duct_MultMsg_Idx = _m->dbg_Auto_Duct_MultMsg_Idx; + dbg_Auto_Duct_Frame0->value1 = _m->dbg_Auto_Duct_Tgt_FR_Lower_ro; + dbg_Auto_Duct_Frame0->value2 = _m->dbg_Auto_Duct_Tg_FR_Lower_ro; + dbg_Auto_Duct_Frame0->value3 = _m->dbg_Auto_Duct_Incar_FR_Lower_ro; + dbg_Auto_Duct_Frame0->value4 = _m->dbg_Auto_Duct_Amb_FR_Lower_ro; + dbg_Auto_Duct_Frame0->value5 = _m->dbg_Auto_Duct_Sun_FR_Lower_ro; + /* + _d[0] |= (uint8_t) ((_m->dbg_Auto_Duct_Tgt_FR_Lower_ro & 0x0F) << 4); + _d[1] |= (uint8_t) ((_m->dbg_Auto_Duct_Tgt_FR_Lower_ro >> 4) & 0xFF); + _d[2] |= (uint8_t) (_m->dbg_Auto_Duct_Tg_FR_Lower_ro & 0xFF); + _d[3] |= (uint8_t) ((_m->dbg_Auto_Duct_Tg_FR_Lower_ro >> 8) & 0x0F); + _d[3] |= (uint8_t) ((_m->dbg_Auto_Duct_Incar_FR_Lower_ro & 0x0F) << 4); + _d[4] |= (uint8_t) ((_m->dbg_Auto_Duct_Incar_FR_Lower_ro >> 4) & 0xFF); + _d[5] |= (uint8_t) (_m->dbg_Auto_Duct_Amb_FR_Lower_ro & 0xFF); + _d[6] |= (uint8_t) ((_m->dbg_Auto_Duct_Amb_FR_Lower_ro >> 8) & 0x0F); + _d[6] |= (uint8_t) ((_m->dbg_Auto_Duct_Sun_FR_Lower_ro & 0x0F) << 4); + _d[7] |= (uint8_t) ((_m->dbg_Auto_Duct_Sun_FR_Lower_ro >> 4) & 0xFF); + */ + break; + + case 4: // Кадр 4: RL параметры + dbg_Auto_Duct_Frame0->dbg_Auto_Duct_MultMsg_Idx = _m->dbg_Auto_Duct_MultMsg_Idx; + dbg_Auto_Duct_Frame0->value1 = _m->dbg_Auto_Duct_Tgt_RL_ro; + dbg_Auto_Duct_Frame0->value2 = _m->dbg_Auto_Duct_Tg_RL_ro; + dbg_Auto_Duct_Frame0->value3 = _m->dbg_Auto_Duct_Incar_RL_ro; + dbg_Auto_Duct_Frame0->value4 = _m->dbg_Auto_Duct_Amb_RL_ro; + dbg_Auto_Duct_Frame0->value5 = _m->dbg_Auto_Duct_Sun_RL_ro; + + /* + _d[0] |= (uint8_t) ((_m->dbg_Auto_Duct_Tgt_RL_ro & 0x0F) << 4); + _d[1] |= (uint8_t) ((_m->dbg_Auto_Duct_Tgt_RL_ro >> 4) & 0xFF); + _d[2] |= (uint8_t) (_m->dbg_Auto_Duct_Tg_RL_ro & 0xFF); + _d[3] |= (uint8_t) ((_m->dbg_Auto_Duct_Tg_RL_ro >> 8) & 0x0F); + _d[3] |= (uint8_t) ((_m->dbg_Auto_Duct_Incar_RL_ro & 0x0F) << 4); + _d[4] |= (uint8_t) ((_m->dbg_Auto_Duct_Incar_RL_ro >> 4) & 0xFF); + _d[5] |= (uint8_t) (_m->dbg_Auto_Duct_Amb_RL_ro & 0xFF); + _d[6] |= (uint8_t) ((_m->dbg_Auto_Duct_Amb_RL_ro >> 8) & 0x0F); + _d[6] |= (uint8_t) ((_m->dbg_Auto_Duct_Sun_RL_ro & 0x0F) << 4); + _d[7] |= (uint8_t) ((_m->dbg_Auto_Duct_Sun_RL_ro >> 4) & 0xFF); + */ + break; + + case 5: // Кадр 5: RR параметры + dbg_Auto_Duct_Frame0->dbg_Auto_Duct_MultMsg_Idx = _m->dbg_Auto_Duct_MultMsg_Idx; + dbg_Auto_Duct_Frame0->value1 = _m->dbg_Auto_Duct_Tgt_RR_ro; + dbg_Auto_Duct_Frame0->value2 = _m->dbg_Auto_Duct_Tg_RR_ro; + dbg_Auto_Duct_Frame0->value3 = _m->dbg_Auto_Duct_Incar_RR_ro; + dbg_Auto_Duct_Frame0->value4 = _m->dbg_Auto_Duct_Amb_RR_ro; + dbg_Auto_Duct_Frame0->value5 = _m->dbg_Auto_Duct_Sun_RR_ro; + /* + _d[0] |= (uint8_t) ((_m->dbg_Auto_Duct_Tgt_RR_ro & 0x0F) << 4); + _d[1] |= (uint8_t) ((_m->dbg_Auto_Duct_Tgt_RR_ro >> 4) & 0xFF); + _d[2] |= (uint8_t) (_m->dbg_Auto_Duct_Tg_RR_ro & 0xFF); + _d[3] |= (uint8_t) ((_m->dbg_Auto_Duct_Tg_RR_ro >> 8) & 0x0F); + _d[3] |= (uint8_t) ((_m->dbg_Auto_Duct_Incar_RR_ro & 0x0F) << 4); + _d[4] |= (uint8_t) ((_m->dbg_Auto_Duct_Incar_RR_ro >> 4) & 0xFF); + _d[5] |= (uint8_t) (_m->dbg_Auto_Duct_Amb_RR_ro & 0xFF); + _d[6] |= (uint8_t) ((_m->dbg_Auto_Duct_Amb_RR_ro >> 8) & 0x0F); + _d[6] |= (uint8_t) ((_m->dbg_Auto_Duct_Sun_RR_ro & 0x0F) << 4); + _d[7] |= (uint8_t) ((_m->dbg_Auto_Duct_Sun_RR_ro >> 4) & 0xFF); + */ + break; + + + case 6: // Кадр 6: + dbg_Auto_Duct_Frame0->dbg_Auto_Duct_MultMsg_Idx = _m->dbg_Auto_Duct_MultMsg_Idx; + dbg_Auto_Duct_Multi_6_Frame0->value1 = _m->dbg_Auto_Duct_Tg_Incar_FL_Upper_ro; + dbg_Auto_Duct_Multi_6_Frame0->value2 = _m->dbg_Auto_Duct_Tg_Incar_FR_Upper_ro; + dbg_Auto_Duct_Multi_6_Frame0->value3 = _m->dbg_Auto_Duct_Tg_Incar_FL_Lower_ro; + dbg_Auto_Duct_Multi_6_Frame0->value4 = _m->dbg_Auto_Duct_Tg_Incar_FR_Lower_ro; + dbg_Auto_Duct_Multi_6_Frame0->value5 = _m->dbg_Auto_Duct_Tg_Incar_RL_ro; + dbg_Auto_Duct_Multi_6_Frame0->value6 = _m->dbg_Auto_Duct_Tg_Incar_RR_ro; + + break; + } + + *_len = (uint8_t)dbg_Auto_Duct_DLC; + *_ide = (uint8_t)dbg_Auto_Duct_IDE; + return dbg_Auto_Duct_CANID; +} + +// ============================================================================ +// 6. dbg_Auto_AF - Автоматическая коррекция AF (MultMsg_Idx) +// ============================================================================ + +uint32_t Pack_dbg_Auto_AF_candb_dbg2(dbg_Auto_AF_t *_m, uint8_t *_d, uint8_t *_len, uint8_t *_ide) { + uint8_t i; + for (i = 0u; i < CANDB_DBG_VALIDATE_DLC(dbg_Auto_AF_DLC); + _d[i++] = CANDB_DBG_INITIAL_BYTE_VALUE); + + + dbg_Auto_AF_Frame0_t *dbg_Auto_AF_Frame0 = (dbg_Auto_AF_Frame0_t *) _d; + +// _d[0] |= (uint8_t)(_m->dbg_Auto_AF_MultMsg_Idx & 0x03); + + switch (_m->dbg_Auto_AF_MultMsg_Idx) { + case 0: // Кадр 0: FL коррекция + dbg_Auto_AF_Frame0->dbg_Auto_AF_MultMsg_Idx = _m->dbg_Auto_AF_MultMsg_Idx; + dbg_Auto_AF_Frame0->value1 = _m->dbg_Auto_AF_Correct_FL; + dbg_Auto_AF_Frame0->value2 = _m->dbg_Auto_AF_Vtg_FL; + dbg_Auto_AF_Frame0->value3 = _m->dbg_Auto_AF_Incar_FL; + dbg_Auto_AF_Frame0->value4 = _m->dbg_Auto_AF_Amb_FL; + dbg_Auto_AF_Frame0->value5 = _m->dbg_Auto_AF_Sun_FL; +/* + _d[0] |= (uint8_t)((_m->dbg_Auto_AF_Correct_FL & 0x0F) << 4); + _d[1] |= (uint8_t)((_m->dbg_Auto_AF_Correct_FL >> 4) & 0xFF); + _d[2] |= (uint8_t)(_m->dbg_Auto_AF_Vtg_FL & 0xFF); + _d[3] |= (uint8_t)((_m->dbg_Auto_AF_Vtg_FL >> 8) & 0x0F); + _d[3] |= (uint8_t)((_m->dbg_Auto_AF_Incar_FL & 0x0F) << 4); + _d[4] |= (uint8_t)((_m->dbg_Auto_AF_Incar_FL >> 4) & 0xFF); + _d[5] |= (uint8_t)(_m->dbg_Auto_AF_Amb_FL & 0xFF); + _d[6] |= (uint8_t)((_m->dbg_Auto_AF_Amb_FL >> 8) & 0x0F); + _d[6] |= (uint8_t)((_m->dbg_Auto_AF_Sun_FL & 0x0F) << 4); + _d[7] |= (uint8_t)((_m->dbg_Auto_AF_Sun_FL >> 4) & 0xFF); + */ + break; + + case 1: // Кадр 1: FR коррекция + dbg_Auto_AF_Frame0->dbg_Auto_AF_MultMsg_Idx = _m->dbg_Auto_AF_MultMsg_Idx; + dbg_Auto_AF_Frame0->value1 = _m->dbg_Auto_AF_Correct_FR; + dbg_Auto_AF_Frame0->value2 = _m->dbg_Auto_AF_Vtg_FR; + dbg_Auto_AF_Frame0->value3 = _m->dbg_Auto_AF_Incar_FR; + dbg_Auto_AF_Frame0->value4 = _m->dbg_Auto_AF_Amb_FR; + dbg_Auto_AF_Frame0->value5 = _m->dbg_Auto_AF_Sun_FR; + /* + _d[0] |= (uint8_t)((_m->dbg_Auto_AF_Correct_FR & 0x0F) << 4); + _d[1] |= (uint8_t)((_m->dbg_Auto_AF_Correct_FR >> 4) & 0xFF); + _d[2] |= (uint8_t)(_m->dbg_Auto_AF_Vtg_FR & 0xFF); + _d[3] |= (uint8_t)((_m->dbg_Auto_AF_Vtg_FR >> 8) & 0x0F); + _d[3] |= (uint8_t)((_m->dbg_Auto_AF_Incar_FR & 0x0F) << 4); + _d[4] |= (uint8_t)((_m->dbg_Auto_AF_Incar_FR >> 4) & 0xFF); + _d[5] |= (uint8_t)(_m->dbg_Auto_AF_Amb_FR & 0xFF); + _d[6] |= (uint8_t)((_m->dbg_Auto_AF_Amb_FR >> 8) & 0x0F); + _d[6] |= (uint8_t)((_m->dbg_Auto_AF_Sun_FR & 0x0F) << 4); + _d[7] |= (uint8_t)((_m->dbg_Auto_AF_Sun_FR >> 4) & 0xFF); + */ + break; + + case 2: // Кадр 2: RL коррекция + dbg_Auto_AF_Frame0->dbg_Auto_AF_MultMsg_Idx = _m->dbg_Auto_AF_MultMsg_Idx; + dbg_Auto_AF_Frame0->value1 = _m->dbg_Auto_AF_Correct_RL; + dbg_Auto_AF_Frame0->value2 = _m->dbg_Auto_AF_Vtg_RL; + dbg_Auto_AF_Frame0->value3 = _m->dbg_Auto_AF_Incar_RL; + dbg_Auto_AF_Frame0->value4 = _m->dbg_Auto_AF_Amb_RL; + dbg_Auto_AF_Frame0->value5 = _m->dbg_Auto_AF_Sun_RL; + /* + _d[0] |= (uint8_t)((_m->dbg_Auto_AF_Correct_RL & 0x0F) << 4); + _d[1] |= (uint8_t)((_m->dbg_Auto_AF_Correct_RL >> 4) & 0xFF); + _d[2] |= (uint8_t)(_m->dbg_Auto_AF_Vtg_RL & 0xFF); + _d[3] |= (uint8_t)((_m->dbg_Auto_AF_Vtg_RL >> 8) & 0x0F); + _d[3] |= (uint8_t)((_m->dbg_Auto_AF_Incar_RL & 0x0F) << 4); + _d[4] |= (uint8_t)((_m->dbg_Auto_AF_Incar_RL >> 4) & 0xFF); + _d[5] |= (uint8_t)(_m->dbg_Auto_AF_Amb_RL & 0xFF); + _d[6] |= (uint8_t)((_m->dbg_Auto_AF_Amb_RL >> 8) & 0x0F); + _d[6] |= (uint8_t)((_m->dbg_Auto_AF_Sun_RL & 0x0F) << 4); + _d[7] |= (uint8_t)((_m->dbg_Auto_AF_Sun_RL >> 4) & 0xFF); + */ + break; + + case 3: // Кадр 3: RR коррекция + dbg_Auto_AF_Frame0->dbg_Auto_AF_MultMsg_Idx = _m->dbg_Auto_AF_MultMsg_Idx; + dbg_Auto_AF_Frame0->value1 = _m->dbg_Auto_AF_Correct_RR; + dbg_Auto_AF_Frame0->value2 = _m->dbg_Auto_AF_Vtg_RR; + dbg_Auto_AF_Frame0->value3 = _m->dbg_Auto_AF_Incar_RR; + dbg_Auto_AF_Frame0->value4 = _m->dbg_Auto_AF_Amb_RR; + dbg_Auto_AF_Frame0->value5 = _m->dbg_Auto_AF_Sun_RR; + /* + _d[0] |= (uint8_t)((_m->dbg_Auto_AF_Correct_RR & 0x0F) << 4); + _d[1] |= (uint8_t)((_m->dbg_Auto_AF_Correct_RR >> 4) & 0xFF); + _d[2] |= (uint8_t)(_m->dbg_Auto_AF_Vtg_RR & 0xFF); + _d[3] |= (uint8_t)((_m->dbg_Auto_AF_Vtg_RR >> 8) & 0x0F); + _d[3] |= (uint8_t)((_m->dbg_Auto_AF_Incar_RR & 0x0F) << 4); + _d[4] |= (uint8_t)((_m->dbg_Auto_AF_Incar_RR >> 4) & 0xFF); + _d[5] |= (uint8_t)(_m->dbg_Auto_AF_Amb_RR & 0xFF); + _d[6] |= (uint8_t)((_m->dbg_Auto_AF_Amb_RR >> 8) & 0x0F); + _d[6] |= (uint8_t)((_m->dbg_Auto_AF_Sun_RR & 0x0F) << 4); + _d[7] |= (uint8_t)((_m->dbg_Auto_AF_Sun_RR >> 4) & 0xFF); + */ + break; + } + + *_len = (uint8_t)dbg_Auto_AF_DLC; + *_ide = (uint8_t)dbg_Auto_AF_IDE; + return dbg_Auto_AF_CANID; +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_CAN_DEBUG_SPAM/candb_dbg_fixed.h b/MODULES/HVAC_M7_CAN_DEBUG_SPAM/candb_dbg_fixed.h new file mode 100644 index 0000000..27a8277 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_DEBUG_SPAM/candb_dbg_fixed.h @@ -0,0 +1,165 @@ +// candb_dbg_fixed.h +// Исправленные версии функций для мультиплексированных сообщений +// Версия без CANDB_DBG_USE_CANSTRUCT + +#ifndef CANDB_DBG_FIXED_H +#define CANDB_DBG_FIXED_H + +#include "candb_dbg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + uint32_t dbg_Sen_Duct_MultMsg_Idx: 2; + uint32_t reserved0: 1; + uint32_t select: 1; + uint32_t value1: 12; //4 + uint32_t value2: 12; //16 + uint32_t value3: 12; //28 + uint32_t value4: 12; //40 + uint32_t value5: 12; //52 +} __attribute__((packed)) dbg_Sen_Duct_Frame0_t; + +typedef struct { + uint32_t dbg_Sen_Incar_MultMsg_Idx: 2; + uint32_t reserved0: 2; + uint32_t value1: 12; //4 + uint32_t value2: 12; //16 + uint32_t value3: 12; //28 + uint32_t value4: 12; //40 +} __attribute__((packed)) dbg_Sen_Incar_Frame0_t; + +typedef struct { + uint32_t dbg_Auto_Duct_MultMsg_Idx: 4; + uint32_t value1: 12; //4 + uint32_t value2: 12; //16 + uint32_t value3: 12; //28 + uint32_t value4: 12; //40 + uint32_t value5: 12; //52 +} __attribute__((packed)) dbg_Auto_Duct_Frame0_t; + +typedef struct { + uint32_t dbg_Auto_Duct_MultMsg_Idx: 4; + uint32_t value1: 10; //4 + uint32_t value2: 10; //14 + uint32_t value3: 10; //24 + uint32_t value4: 10; //34 + uint32_t value5: 10; //44 + uint32_t value6: 10; //54 +} __attribute__((packed)) dbg_Auto_Duct_Multi_6_Frame0_t; + +typedef struct { + uint32_t dbg_Auto_AF_MultMsg_Idx: 2; + uint32_t reserved0: 2; + uint32_t value1: 12; //4 + uint32_t value2: 12; //16 + uint32_t value3: 12; //28 + uint32_t value4: 12; //40 + uint32_t value5: 12; //52 +} __attribute__((packed)) dbg_Auto_AF_Frame0_t; + + +typedef struct { + uint32_t dbg_Info_MultMsg_Idx: 2; + uint32_t dbg_Info_CCU_SW_Ver_Date: 22; + uint32_t dbg_Info_CCU_SW_Ver_Rev: 8; + uint32_t dbg_Info_ActivatedCAL: 4; + uint32_t dbg_Info_CCU_Aroma_Cfg: 4; + uint32_t dbg_Info_CCU_Algorithm_Cfg: 4; + uint32_t reserved0: 4; + uint32_t dbg_Info_VehicleBody: 16; +} __attribute__((packed)) dbg_CCU_Info_Frame0_t; + +typedef struct { + uint32_t dbg_Info_MultMsg_Idx: 2; + uint32_t dbg_Info_Calibration_Ver_Date: 22; //2 + uint32_t dbg_Info_Calibration_Ver_Rev: 8; //24 + uint32_t reserved0: 2; + uint32_t dbg_Info_MBD_Ver_Date: 22; //34 + uint32_t dbg_Info_MBD_Ver_Rev: 8;//56 +} __attribute__((packed)) dbg_CCU_Info_Frame1_t; + +typedef struct { + uint32_t dbg_PID_MultMsg_Idx: 4; + uint32_t dbg_P: 12; + uint32_t dbg_I: 12; + uint32_t dbg_D: 12; + uint32_t reserved0: 24; +} __attribute__((packed)) dbg_Stat_PID_Frame0_t; + +/** + * @brief Упаковка данных датчиков салона (исправленная версия) + * @param _m Указатель на структуру с данными + * @param _d Указатель на буфер данных (8 байт) + * @param _len Указатель на длину данных + * @param _ide Указатель на флаг IDE + * @return CAN ID сообщения + * @note Мультиплексирование по полю dbg_Sen_Incar_MultMsg_Idx (0-3) + */ +uint32_t Pack_dbg_Sen_Incar_candb_dbg2(dbg_Sen_Incar_t *_m, uint8_t *_d, uint8_t *_len, uint8_t *_ide); + +/** + * @brief Упаковка данных открытия клапанов DiffBlr (исправленная версия) + * @param _m Указатель на структуру с данными + * @param _d Указатель на буфер данных (8 байт) + * @param _len Указатель на длину данных + * @param _ide Указатель на флаг IDE + * @return CAN ID сообщения + * @note Мультиплексирование по полю Logic_ValveOpen_MultMsg_Idx (0-3) + */ +uint32_t Pack_dbg_DiffBlr_ValveOpen_candb_dbg2(dbg_DiffBlr_ValveOpen_t *_m, uint8_t *_d, uint8_t *_len, uint8_t *_ide); + +/** + * @brief Упаковка информационных данных CCU (исправленная версия) + * @param _m Указатель на структуру с данными + * @param _d Указатель на буфер данных (8 байт) + * @param _len Указатель на длину данных + * @param _ide Указатель на флаг IDE + * @return CAN ID сообщения + * @note Мультиплексирование по полю dbg_Info_MultMsg_Idx (0-3) + */ +uint32_t Pack_dbg_CCU_Info_candb_dbg2(dbg_CCU_Info_t *_m, uint8_t *_d, uint8_t *_len, uint8_t *_ide); + +/** + * @brief Упаковка данных датчиков воздуховодов (исправленная версия) + * @param _m Указатель на структуру с данными + * @param _d Указатель на буфер данных (8 байт) + * @param _len Указатель на длину данных + * @param _ide Указатель на флаг IDE + * @return CAN ID сообщения + * @note Мультиплексирование по полю dbg_Sen_Duct_MultMsg_Idx (0-3) + */ +uint32_t Pack_dbg_Sen_Duct_candb_dbg2(dbg_Sen_Duct_t *_m, uint8_t *_d, uint8_t *_len, uint8_t *_ide); + +/** + * @brief Упаковка данных автоматических воздуховодов (исправленная версия) + * @param _m Указатель на структуру с данными + * @param _d Указатель на буфер данных (8 байт) + * @param _len Указатель на длину данных + * @param _ide Указатель на флаг IDE + * @return CAN ID сообщения + * @note Мультиплексирование по полю dbg_Auto_Duct_MultMsg_Idx (0-5) + */ +uint32_t Pack_dbg_Auto_Duct_candb_dbg2(dbg_Auto_Duct_t *_m, uint8_t *_d, uint8_t *_len, uint8_t *_ide); + +/** + * @brief Упаковка данных автоматической коррекции AF (исправленная версия) + * @param _m Указатель на структуру с данными + * @param _d Указатель на буфер данных (8 байт) + * @param _len Указатель на длину данных + * @param _ide Указатель на флаг IDE + * @return CAN ID сообщения + * @note Мультиплексирование по полю dbg_Auto_AF_MultMsg_Idx (0-3) + */ +uint32_t Pack_dbg_Auto_AF_candb_dbg2(dbg_Auto_AF_t *_m, uint8_t *_d, uint8_t *_len, uint8_t *_ide); + + +uint32_t Pack_dbg_Stat_PID_candb_dbg2(dbg_Stat_PID_t *_m, uint8_t dbg_PID_MultMsg_Idx, uint8_t *_d, uint8_t *_len, uint8_t *_ide); + +#ifdef __cplusplus +} +#endif + +#endif // CANDB_DBG_FIXED_H \ No newline at end of file diff --git a/MODULES/HVAC_M7_CAN_DEBUG_SPAM/modular.json b/MODULES/HVAC_M7_CAN_DEBUG_SPAM/modular.json new file mode 100644 index 0000000..99df025 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_DEBUG_SPAM/modular.json @@ -0,0 +1,10 @@ +{ + "cmake": { + "inc_dirs": [ + "./" + ], + "srcs": [ + "./**.c" + ] + } +} diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/bcm_candb-binutil.c b/MODULES/HVAC_M7_CAN_MATRIX/butl/bcm_candb-binutil.c new file mode 100644 index 0000000..de52927 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/bcm_candb-binutil.c @@ -0,0 +1,365 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#include "bcm_candb-binutil.h" + +// DBC file version +#if (VER_CANDB_MAJ != (0U)) || (VER_CANDB_MIN != (0U)) +#error The BCM_CANDB binutil source file has inconsistency with core dbc lib! +#endif + +#ifdef __DEF_BCM_CANDB__ + +bcm_candb_rx_t bcm_candb_rx; + +bcm_candb_tx_t bcm_candb_tx; + +#endif // __DEF_BCM_CANDB__ + +uint32_t bcm_candb_Receive(bcm_candb_rx_t* _m, const uint8_t* _d, uint32_t _id, uint8_t dlc_) +{ + uint32_t recid = 0; + if ((_id >= 0xB1U) && (_id < 0x50FU)) { + if ((_id >= 0xB1U) && (_id < 0x253U)) { + if ((_id >= 0xB1U) && (_id < 0x21AU)) { + if ((_id >= 0xB1U) && (_id < 0x153U)) { + if ((_id >= 0xB1U) && (_id < 0x100U)) { + if (_id == 0xB1U) { + recid = Unpack_TCU_R932_1_candb(&(_m->TCU_R932_1), _d, dlc_); + } else if (_id == 0xF2U) { + recid = Unpack_SCU_02_candb(&(_m->SCU_02), _d, dlc_); + } + } else { + if (_id == 0x100U) { + recid = Unpack_ESC_04_candb(&(_m->ESC_04), _d, dlc_); + } else { + if (_id == 0x121U) { + recid = Unpack_VAU2_Msg1_candb(&(_m->VAU2_Msg1), _d, dlc_); + } else if (_id == 0x150U) { + recid = Unpack_EMS_Veh_candb(&(_m->EMS_Veh), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x153U) && (_id < 0x156U)) { + if (_id == 0x153U) { + recid = Unpack_EMS_Veh_02_candb(&(_m->EMS_Veh_02), _d, dlc_); + } else if (_id == 0x155U) { + recid = Unpack_EMS_EEM_01_candb(&(_m->EMS_EEM_01), _d, dlc_); + } + } else { + if (_id == 0x156U) { + recid = Unpack_EMS_EEM_02_candb(&(_m->EMS_EEM_02), _d, dlc_); + } else { + if (_id == 0x20AU) { + recid = Unpack_DAS_02_candb(&(_m->DAS_02), _d, dlc_); + } else if (_id == 0x210U) { + recid = Unpack_ACU_01_candb(&(_m->ACU_01), _d, dlc_); + } + } + } + } + } else { + if ((_id >= 0x21AU) && (_id < 0x246U)) { + if ((_id >= 0x21AU) && (_id < 0x243U)) { + if (_id == 0x21AU) { + recid = Unpack_EPB_Status_candb(&(_m->EPB_Status), _d, dlc_); + } else if (_id == 0x238U) { + recid = Unpack_SWM_ContrlsState_candb(&(_m->SWM_ContrlsState), _d, dlc_); + } + } else { + if (_id == 0x243U) { + recid = Unpack_DMFR_Msg1_candb(&(_m->DMFR_Msg1), _d, dlc_); + } else { + if (_id == 0x244U) { + recid = Unpack_DMFL_Msg1_candb(&(_m->DMFL_Msg1), _d, dlc_); + } else if (_id == 0x245U) { + recid = Unpack_DMRL_Msg1_candb(&(_m->DMRL_Msg1), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x246U) && (_id < 0x24CU)) { + if (_id == 0x246U) { + recid = Unpack_DMRR_Msg1_candb(&(_m->DMRR_Msg1), _d, dlc_); + } else { + if (_id == 0x247U) { + recid = Unpack_TM_Stat_candb(&(_m->TM_Stat), _d, dlc_); + } else if (_id == 0x249U) { + recid = Unpack_PTG_Body_Stat_candb(&(_m->PTG_Body_Stat), _d, dlc_); + } + } + } else { + if (_id == 0x24CU) { + recid = Unpack_TM_CP_candb(&(_m->TM_CP), _d, dlc_); + } else { + if (_id == 0x24FU) { + recid = Unpack_VAU2_Msg2_candb(&(_m->VAU2_Msg2), _d, dlc_); + } else if (_id == 0x252U) { + recid = Unpack_LB_pSilCU_State_candb(&(_m->LB_pSilCU_State), _d, dlc_); + } + } + } + } + } + } else { + if ((_id >= 0x253U) && (_id < 0x3D0U)) { + if ((_id >= 0x253U) && (_id < 0x368U)) { + if ((_id >= 0x253U) && (_id < 0x2B0U)) { + if (_id == 0x253U) { + recid = Unpack_RB_pSilCU_State_candb(&(_m->RB_pSilCU_State), _d, dlc_); + } else if (_id == 0x277U) { + recid = Unpack_ATS_Status_candb(&(_m->ATS_Status), _d, dlc_); + } + } else { + if (_id == 0x2B0U) { + recid = Unpack_SAS_Standard_candb(&(_m->SAS_Standard), _d, dlc_); + } else { + if (_id == 0x2E7U) { + recid = Unpack_IC_ABSOLUTE_CLOCK_candb(&(_m->IC_ABSOLUTE_CLOCK), _d, dlc_); + } else if (_id == 0x367U) { + recid = Unpack_DMFL_SMFL_REQ_CTR_SEATS_candb(&(_m->DMFL_SMFL_REQ_CTR_SEATS), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x368U) && (_id < 0x380U)) { + if (_id == 0x368U) { + recid = Unpack_DMFR_SMFR_REQ_CTR_SEATS_candb(&(_m->DMFR_SMFR_REQ_CTR_SEATS), _d, dlc_); + } else { + if (_id == 0x369U) { + recid = Unpack_DMRL_SMRL_REQ_CTR_SEATS_candb(&(_m->DMRL_SMRL_REQ_CTR_SEATS), _d, dlc_); + } else if (_id == 0x36AU) { + recid = Unpack_DMRR_SMRR_REQ_CTR_SEATS_candb(&(_m->DMRR_SMRR_REQ_CTR_SEATS), _d, dlc_); + } + } + } else { + if (_id == 0x380U) { + recid = Unpack_CCU_Msg1_candb(&(_m->CCU_Msg1), _d, dlc_); + } else { + if (_id == 0x38AU) { + recid = Unpack_Sroof_State_candb(&(_m->Sroof_State), _d, dlc_); + } else if (_id == 0x3C1U) { + recid = Unpack_ESC_08_candb(&(_m->ESC_08), _d, dlc_); + } + } + } + } + } else { + if ((_id >= 0x3D0U) && (_id < 0x4D0U)) { + if ((_id >= 0x3D0U) && (_id < 0x4AFU)) { + if (_id == 0x3D0U) { + recid = Unpack_MAS_Status_candb(&(_m->MAS_Status), _d, dlc_); + } else if (_id == 0x495U) { + recid = Unpack_CGW_COMM_REQ_candb(&(_m->CGW_COMM_REQ), _d, dlc_); + } + } else { + if (_id == 0x4AFU) { + recid = Unpack_DCDC1248_01_candb(&(_m->DCDC1248_01), _d, dlc_); + } else { + if (_id == 0x4B1U) { + recid = Unpack_DCDC1248_02_candb(&(_m->DCDC1248_02), _d, dlc_); + } else if (_id == 0x4B6U) { + recid = Unpack_FIU_Profile_candb(&(_m->FIU_Profile), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x4D0U) && (_id < 0x4D3U)) { + if (_id == 0x4D0U) { + recid = Unpack_SMFL_status_candb(&(_m->SMFL_status), _d, dlc_); + } else { + if (_id == 0x4D1U) { + recid = Unpack_SMFR_status_candb(&(_m->SMFR_status), _d, dlc_); + } else if (_id == 0x4D2U) { + recid = Unpack_SMRL_status_candb(&(_m->SMRL_status), _d, dlc_); + } + } + } else { + if (_id == 0x4D3U) { + recid = Unpack_SMRR_status_candb(&(_m->SMRR_status), _d, dlc_); + } else { + if (_id == 0x501U) { + recid = Unpack_CCU_Msg3_candb(&(_m->CCU_Msg3), _d, dlc_); + } else if (_id == 0x50BU) { + recid = Unpack_FIU_Cmd_candb(&(_m->FIU_Cmd), _d, dlc_); + } + } + } + } + } + } + } else { + if ((_id >= 0x50FU) && (_id < 0x599U)) { + if ((_id >= 0x50FU) && (_id < 0x539U)) { + if ((_id >= 0x50FU) && (_id < 0x524U)) { + if ((_id >= 0x50FU) && (_id < 0x521U)) { + if (_id == 0x50FU) { + recid = Unpack_SDM_Cmd_candb(&(_m->SDM_Cmd), _d, dlc_); + } else if (_id == 0x511U) { + recid = Unpack_HUD_MSG_STATUS_candb(&(_m->HUD_MSG_STATUS), _d, dlc_); + } + } else { + if (_id == 0x521U) { + recid = Unpack_OCUFL_MSG_candb(&(_m->OCUFL_MSG), _d, dlc_); + } else { + if (_id == 0x522U) { + recid = Unpack_OCUFR_MSG_candb(&(_m->OCUFR_MSG), _d, dlc_); + } else if (_id == 0x523U) { + recid = Unpack_OCURL_MSG_candb(&(_m->OCURL_MSG), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x524U) && (_id < 0x533U)) { + if (_id == 0x524U) { + recid = Unpack_OCURR_MSG_candb(&(_m->OCURR_MSG), _d, dlc_); + } else if (_id == 0x525U) { + recid = Unpack_RBCU_BODY_Stat_candb(&(_m->RBCU_BODY_Stat), _d, dlc_); + } + } else { + if (_id == 0x533U) { + recid = Unpack_SMFL_MEM1_candb(&(_m->SMFL_MEM1), _d, dlc_); + } else { + if (_id == 0x535U) { + recid = Unpack_SMFL_MEM2_candb(&(_m->SMFL_MEM2), _d, dlc_); + } else if (_id == 0x537U) { + recid = Unpack_SMFR_MEM1_candb(&(_m->SMFR_MEM1), _d, dlc_); + } + } + } + } + } else { + if ((_id >= 0x539U) && (_id < 0x58EU)) { + if ((_id >= 0x539U) && (_id < 0x53DU)) { + if (_id == 0x539U) { + recid = Unpack_SMFR_MEM2_candb(&(_m->SMFR_MEM2), _d, dlc_); + } else if (_id == 0x53BU) { + recid = Unpack_SMRL_MEM1_candb(&(_m->SMRL_MEM1), _d, dlc_); + } + } else { + if (_id == 0x53DU) { + recid = Unpack_SMRL_MEM2_candb(&(_m->SMRL_MEM2), _d, dlc_); + } else { + if (_id == 0x53FU) { + recid = Unpack_SMRR_MEM1_candb(&(_m->SMRR_MEM1), _d, dlc_); + } else if (_id == 0x541U) { + recid = Unpack_SMRR_MEM2_candb(&(_m->SMRR_MEM2), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x58EU) && (_id < 0x596U)) { + if (_id == 0x58EU) { + recid = Unpack_FIU_Msg1_candb(&(_m->FIU_Msg1), _d, dlc_); + } else { + if (_id == 0x58FU) { + recid = Unpack_FIU_Msg2_candb(&(_m->FIU_Msg2), _d, dlc_); + } else if (_id == 0x594U) { + recid = Unpack_FIU_Msg3_candb(&(_m->FIU_Msg3), _d, dlc_); + } + } + } else { + if (_id == 0x596U) { + recid = Unpack_WHFL_MSG1_candb(&(_m->WHFL_MSG1), _d, dlc_); + } else { + if (_id == 0x597U) { + recid = Unpack_WHFR_Msg1_candb(&(_m->WHFR_Msg1), _d, dlc_); + } else if (_id == 0x598U) { + recid = Unpack_PLDSilCU_State_candb(&(_m->PLDSilCU_State), _d, dlc_); + } + } + } + } + } + } else { + if ((_id >= 0x599U) && (_id < 0x5E9U)) { + if ((_id >= 0x599U) && (_id < 0x5A3U)) { + if ((_id >= 0x599U) && (_id < 0x59BU)) { + if (_id == 0x599U) { + recid = Unpack_PRDSilCU_State_candb(&(_m->PRDSilCU_State), _d, dlc_); + } else if (_id == 0x59AU) { + recid = Unpack_FLDSilCU_State_candb(&(_m->FLDSilCU_State), _d, dlc_); + } + } else { + if (_id == 0x59BU) { + recid = Unpack_FRDSilCU_State_candb(&(_m->FRDSilCU_State), _d, dlc_); + } else { + if (_id == 0x59CU) { + recid = Unpack_RLDSilCU_State_candb(&(_m->RLDSilCU_State), _d, dlc_); + } else if (_id == 0x59DU) { + recid = Unpack_RRDSilCU_State_candb(&(_m->RRDSilCU_State), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x5A3U) && (_id < 0x5CBU)) { + if (_id == 0x5A3U) { + recid = Unpack_FIU_CCU3_candb(&(_m->FIU_CCU3), _d, dlc_); + } else { + if (_id == 0x5AAU) { + recid = Unpack_IC_DISPLAY_CLOCK_candb(&(_m->IC_DISPLAY_CLOCK), _d, dlc_); + } else if (_id == 0x5CAU) { + recid = Unpack_ICLSilCU_State_candb(&(_m->ICLSilCU_State), _d, dlc_); + } + } + } else { + if (_id == 0x5CBU) { + recid = Unpack_ICRSilCU_State_candb(&(_m->ICRSilCU_State), _d, dlc_); + } else { + if (_id == 0x5DAU) { + recid = Unpack_SFRSilCU_State_candb(&(_m->SFRSilCU_State), _d, dlc_); + } else if (_id == 0x5DBU) { + recid = Unpack_SFLSilCU_State_candb(&(_m->SFLSilCU_State), _d, dlc_); + } + } + } + } + } else { + if ((_id >= 0x5E9U) && (_id < 0x5EFU)) { + if ((_id >= 0x5E9U) && (_id < 0x5EBU)) { + if (_id == 0x5E9U) { + recid = Unpack_RDRSilCU_State_candb(&(_m->RDRSilCU_State), _d, dlc_); + } else if (_id == 0x5EAU) { + recid = Unpack_FCSilCU_State_candb(&(_m->FCSilCU_State), _d, dlc_); + } + } else { + if (_id == 0x5EBU) { + recid = Unpack_RCLSilCU_State_candb(&(_m->RCLSilCU_State), _d, dlc_); + } else { + if (_id == 0x5ECU) { + recid = Unpack_RCRSilCU_State_candb(&(_m->RCRSilCU_State), _d, dlc_); + } else if (_id == 0x5EDU) { + recid = Unpack_RDLSilCU_State_candb(&(_m->RDLSilCU_State), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x5EFU) && (_id < 0x691U)) { + if (_id == 0x5EFU) { + recid = Unpack_CCPF_BodyTM_Stat_candb(&(_m->CCPF_BodyTM_Stat), _d, dlc_); + } else { + if (_id == 0x622U) { + recid = Unpack_VAU_BLE_Device_candb(&(_m->VAU_BLE_Device), _d, dlc_); + } else if (_id == 0x690U) { + recid = Unpack_SSL_Status_candb(&(_m->SSL_Status), _d, dlc_); + } + } + } else { + if (_id == 0x691U) { + recid = Unpack_SSR_Status_candb(&(_m->SSR_Status), _d, dlc_); + } else { + if (_id == 0x7A3U) { + recid = Unpack_Diag_To_BCM_candb(&(_m->Diag_To_BCM), _d, dlc_); + } else if (_id == 0x7DFU) { + recid = Unpack_Diag_Functional_candb(&(_m->Diag_Functional), _d, dlc_); + } + } + } + } + } + } + } + + return recid; +} + diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/bcm_candb-binutil.h b/MODULES/HVAC_M7_CAN_MATRIX/butl/bcm_candb-binutil.h new file mode 100644 index 0000000..123a36d --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/bcm_candb-binutil.h @@ -0,0 +1,150 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dbccodeconf.h" + +#include "candb.h" + +typedef struct +{ + TCU_R932_1_t TCU_R932_1; + SCU_02_t SCU_02; + ESC_04_t ESC_04; + VAU2_Msg1_t VAU2_Msg1; + EMS_Veh_t EMS_Veh; + EMS_Veh_02_t EMS_Veh_02; + EMS_EEM_01_t EMS_EEM_01; + EMS_EEM_02_t EMS_EEM_02; + DAS_02_t DAS_02; + ACU_01_t ACU_01; + EPB_Status_t EPB_Status; + SWM_ContrlsState_t SWM_ContrlsState; + DMFR_Msg1_t DMFR_Msg1; + DMFL_Msg1_t DMFL_Msg1; + DMRL_Msg1_t DMRL_Msg1; + DMRR_Msg1_t DMRR_Msg1; + TM_Stat_t TM_Stat; + PTG_Body_Stat_t PTG_Body_Stat; + TM_CP_t TM_CP; + VAU2_Msg2_t VAU2_Msg2; + LB_pSilCU_State_t LB_pSilCU_State; + RB_pSilCU_State_t RB_pSilCU_State; + ATS_Status_t ATS_Status; + SAS_Standard_t SAS_Standard; + IC_ABSOLUTE_CLOCK_t IC_ABSOLUTE_CLOCK; + DMFL_SMFL_REQ_CTR_SEATS_t DMFL_SMFL_REQ_CTR_SEATS; + DMFR_SMFR_REQ_CTR_SEATS_t DMFR_SMFR_REQ_CTR_SEATS; + DMRL_SMRL_REQ_CTR_SEATS_t DMRL_SMRL_REQ_CTR_SEATS; + DMRR_SMRR_REQ_CTR_SEATS_t DMRR_SMRR_REQ_CTR_SEATS; + CCU_Msg1_t CCU_Msg1; + Sroof_State_t Sroof_State; + ESC_08_t ESC_08; + MAS_Status_t MAS_Status; + CGW_COMM_REQ_t CGW_COMM_REQ; + DCDC1248_01_t DCDC1248_01; + DCDC1248_02_t DCDC1248_02; + FIU_Profile_t FIU_Profile; + SMFL_status_t SMFL_status; + SMFR_status_t SMFR_status; + SMRL_status_t SMRL_status; + SMRR_status_t SMRR_status; + CCU_Msg3_t CCU_Msg3; + FIU_Cmd_t FIU_Cmd; + SDM_Cmd_t SDM_Cmd; + HUD_MSG_STATUS_t HUD_MSG_STATUS; + OCUFL_MSG_t OCUFL_MSG; + OCUFR_MSG_t OCUFR_MSG; + OCURL_MSG_t OCURL_MSG; + OCURR_MSG_t OCURR_MSG; + RBCU_BODY_Stat_t RBCU_BODY_Stat; + SMFL_MEM1_t SMFL_MEM1; + SMFL_MEM2_t SMFL_MEM2; + SMFR_MEM1_t SMFR_MEM1; + SMFR_MEM2_t SMFR_MEM2; + SMRL_MEM1_t SMRL_MEM1; + SMRL_MEM2_t SMRL_MEM2; + SMRR_MEM1_t SMRR_MEM1; + SMRR_MEM2_t SMRR_MEM2; + FIU_Msg1_t FIU_Msg1; + FIU_Msg2_t FIU_Msg2; + FIU_Msg3_t FIU_Msg3; + WHFL_MSG1_t WHFL_MSG1; + WHFR_Msg1_t WHFR_Msg1; + PLDSilCU_State_t PLDSilCU_State; + PRDSilCU_State_t PRDSilCU_State; + FLDSilCU_State_t FLDSilCU_State; + FRDSilCU_State_t FRDSilCU_State; + RLDSilCU_State_t RLDSilCU_State; + RRDSilCU_State_t RRDSilCU_State; + FIU_CCU3_t FIU_CCU3; + IC_DISPLAY_CLOCK_t IC_DISPLAY_CLOCK; + ICLSilCU_State_t ICLSilCU_State; + ICRSilCU_State_t ICRSilCU_State; + SFRSilCU_State_t SFRSilCU_State; + SFLSilCU_State_t SFLSilCU_State; + RDRSilCU_State_t RDRSilCU_State; + FCSilCU_State_t FCSilCU_State; + RCLSilCU_State_t RCLSilCU_State; + RCRSilCU_State_t RCRSilCU_State; + RDLSilCU_State_t RDLSilCU_State; + CCPF_BodyTM_Stat_t CCPF_BodyTM_Stat; + VAU_BLE_Device_t VAU_BLE_Device; + SSL_Status_t SSL_Status; + SSR_Status_t SSR_Status; + Diag_To_BCM_t Diag_To_BCM; + Diag_Functional_t Diag_Functional; +} bcm_candb_rx_t; + +typedef struct +{ + BCM_Powertrain_t BCM_Powertrain; + BCM_EEM_t BCM_EEM; + BCM_ExteriorLightState_t BCM_ExteriorLightState; + BCM_StyleCmd1_t BCM_StyleCmd1; + BCM_DMS_01_t BCM_DMS_01; + BCM_VEH_STATE_t BCM_VEH_STATE; + BCM_Veh_State2_t BCM_Veh_State2; + BCM_ALS_Light_Front_t BCM_ALS_Light_Front; + BCM_ALS_Light_Rear_t BCM_ALS_Light_Rear; + BCM_Rear_Plafond_Light_Data_t BCM_Rear_Plafond_Light_Data; + BCM_Lock_CTR_t BCM_Lock_CTR; + BCM_DCDC12_CNTRL_t BCM_DCDC12_CNTRL; + BCM_IC_Info_Msg_t BCM_IC_Info_Msg; + BCM_CLIMATIC_DATA_t BCM_CLIMATIC_DATA; + VEH_VIN_t VEH_VIN; + BCM_RunningBoards_t BCM_RunningBoards; + BCM_MEM_SMFL1_t BCM_MEM_SMFL1; + BCM_MEM_SMFL2_t BCM_MEM_SMFL2; + BCM_MEM_SMFR1_t BCM_MEM_SMFR1; + BCM_MEM_SMFR2_t BCM_MEM_SMFR2; + BCM_MEM_SMRL1_t BCM_MEM_SMRL1; + BCM_MEM_SMRL2_t BCM_MEM_SMRL2; + BCM_MEM_SMRR1_t BCM_MEM_SMRR1; + BCM_MEM_SMRR2_t BCM_MEM_SMRR2; + BCM_StyleCmd2_t BCM_StyleCmd2; + BCM_StyleCmd3_t BCM_StyleCmd3; + BCM_WHF_Request_t BCM_WHF_Request; + BCM_UserConfig_Stat_t BCM_UserConfig_Stat; + Diag_From_APU_t Diag_From_APU; + Diag_To_APU_t Diag_To_APU; + Diag_From_BCM_t Diag_From_BCM; +} bcm_candb_tx_t; + +uint32_t bcm_candb_Receive(bcm_candb_rx_t* m, const uint8_t* d, uint32_t msgid, uint8_t dlc); + +#ifdef __DEF_BCM_CANDB__ + +extern bcm_candb_rx_t bcm_candb_rx; + +extern bcm_candb_tx_t bcm_candb_tx; + +#endif // __DEF_BCM_CANDB__ + +#ifdef __cplusplus +} +#endif diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/ccu_candb-binutil.c b/MODULES/HVAC_M7_CAN_MATRIX/butl/ccu_candb-binutil.c new file mode 100644 index 0000000..c636c03 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/ccu_candb-binutil.c @@ -0,0 +1,149 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#include "ccu_candb-binutil.h" + +// DBC file version +#if (VER_CANDB_MAJ != (0U)) || (VER_CANDB_MIN != (0U)) +#error The CCU_CANDB binutil source file has inconsistency with core dbc lib! +#endif + +#ifdef __DEF_CCU_CANDB__ + +ccu_candb_rx_t ccu_candb_rx; + +ccu_candb_tx_t ccu_candb_tx; + +#endif // __DEF_CCU_CANDB__ + +uint32_t ccu_candb_Receive(ccu_candb_rx_t* _m, const uint8_t* _d, uint32_t _id, uint8_t dlc_) +{ + uint32_t recid = 0; + if ((_id >= 0x100U) && (_id < 0x4D0U)) { + if ((_id >= 0x100U) && (_id < 0x24CU)) { + if ((_id >= 0x100U) && (_id < 0x157U)) { + if ((_id >= 0x100U) && (_id < 0x152U)) { + if (_id == 0x100U) { + recid = Unpack_ESC_04_candb(&(_m->ESC_04), _d, dlc_); + } else if (_id == 0x150U) { + recid = Unpack_EMS_Veh_candb(&(_m->EMS_Veh), _d, dlc_); + } + } else { + if (_id == 0x152U) { + recid = Unpack_BCM_Powertrain_candb(&(_m->BCM_Powertrain), _d, dlc_); + } else if (_id == 0x153U) { + recid = Unpack_EMS_Veh_02_candb(&(_m->EMS_Veh_02), _d, dlc_); + } + } + } else { + if ((_id >= 0x157U) && (_id < 0x244U)) { + if (_id == 0x157U) { + recid = Unpack_BCM_EEM_candb(&(_m->BCM_EEM), _d, dlc_); + } else if (_id == 0x243U) { + recid = Unpack_DMFR_Msg1_candb(&(_m->DMFR_Msg1), _d, dlc_); + } + } else { + if (_id == 0x244U) { + recid = Unpack_DMFL_Msg1_candb(&(_m->DMFL_Msg1), _d, dlc_); + } else if (_id == 0x247U) { + recid = Unpack_TM_Stat_candb(&(_m->TM_Stat), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x24CU) && (_id < 0x305U)) { + if ((_id >= 0x24CU) && (_id < 0x280U)) { + if (_id == 0x24CU) { + recid = Unpack_TM_CP_candb(&(_m->TM_CP), _d, dlc_); + } else if (_id == 0x25AU) { + recid = Unpack_HVC_CCU_Status_Msg_candb(&(_m->HVC_CCU_Status_Msg), _d, dlc_); + } + } else { + if (_id == 0x280U) { + recid = Unpack_BCM_VEH_STATE_candb(&(_m->BCM_VEH_STATE), _d, dlc_); + } else if (_id == 0x298U) { + recid = Unpack_EMS_HVC_Req_Msg_candb(&(_m->EMS_HVC_Req_Msg), _d, dlc_); + } + } + } else { + if ((_id >= 0x305U) && (_id < 0x39DU)) { + if (_id == 0x305U) { + recid = Unpack_HVC_Err_Status_Msg_candb(&(_m->HVC_Err_Status_Msg), _d, dlc_); + } else if (_id == 0x365U) { + recid = Unpack_BCM_CLIMATIC_DATA_candb(&(_m->BCM_CLIMATIC_DATA), _d, dlc_); + } + } else { + if (_id == 0x39DU) { + recid = Unpack_VCU_CCU_Req_candb(&(_m->VCU_CCU_Req), _d, dlc_); + } else if (_id == 0x3C1U) { + recid = Unpack_ESC_08_candb(&(_m->ESC_08), _d, dlc_); + } + } + } + } + } else { + if ((_id >= 0x4D0U) && (_id < 0x523U)) { + if ((_id >= 0x4D0U) && (_id < 0x50FU)) { + if ((_id >= 0x4D0U) && (_id < 0x4D2U)) { + if (_id == 0x4D0U) { + recid = Unpack_SMFL_status_candb(&(_m->SMFL_status), _d, dlc_); + } else if (_id == 0x4D1U) { + recid = Unpack_SMFR_status_candb(&(_m->SMFR_status), _d, dlc_); + } + } else { + if (_id == 0x4D2U) { + recid = Unpack_SMRL_status_candb(&(_m->SMRL_status), _d, dlc_); + } else if (_id == 0x4D3U) { + recid = Unpack_SMRR_status_candb(&(_m->SMRR_status), _d, dlc_); + } + } + } else { + if ((_id >= 0x50FU) && (_id < 0x521U)) { + if (_id == 0x50FU) { + recid = Unpack_SDM_Cmd_candb(&(_m->SDM_Cmd), _d, dlc_); + } else if (_id == 0x51AU) { + recid = Unpack_VEH_VIN_candb(&(_m->VEH_VIN), _d, dlc_); + } + } else { + if (_id == 0x521U) { + recid = Unpack_OCUFL_MSG_candb(&(_m->OCUFL_MSG), _d, dlc_); + } else if (_id == 0x522U) { + recid = Unpack_OCUFR_MSG_candb(&(_m->OCUFR_MSG), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x523U) && (_id < 0x5A2U)) { + if ((_id >= 0x523U) && (_id < 0x589U)) { + if (_id == 0x523U) { + recid = Unpack_OCURL_MSG_candb(&(_m->OCURL_MSG), _d, dlc_); + } else if (_id == 0x524U) { + recid = Unpack_OCURR_MSG_candb(&(_m->OCURR_MSG), _d, dlc_); + } + } else { + if (_id == 0x589U) { + recid = Unpack_DW_STATE_candb(&(_m->DW_STATE), _d, dlc_); + } else if (_id == 0x5A1U) { + recid = Unpack_FIU_CCU1_candb(&(_m->FIU_CCU1), _d, dlc_); + } + } + } else { + if ((_id >= 0x5A2U) && (_id < 0x7ABU)) { + if (_id == 0x5A2U) { + recid = Unpack_FIU_CCU2_candb(&(_m->FIU_CCU2), _d, dlc_); + } else if (_id == 0x5A3U) { + recid = Unpack_FIU_CCU3_candb(&(_m->FIU_CCU3), _d, dlc_); + } + } else { + if (_id == 0x7ABU) { + recid = Unpack_Diag_To_CCU_candb(&(_m->Diag_To_CCU), _d, dlc_); + } else if (_id == 0x7DFU) { + recid = Unpack_Diag_Functional_candb(&(_m->Diag_Functional), _d, dlc_); + } + } + } + } + } + + return recid; +} + diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/ccu_candb-binutil.h b/MODULES/HVAC_M7_CAN_MATRIX/butl/ccu_candb-binutil.h new file mode 100644 index 0000000..28dec70 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/ccu_candb-binutil.h @@ -0,0 +1,77 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dbccodeconf.h" + +#include "candb.h" + +typedef struct +{ + ESC_04_t ESC_04; + EMS_Veh_t EMS_Veh; + BCM_Powertrain_t BCM_Powertrain; + EMS_Veh_02_t EMS_Veh_02; + BCM_EEM_t BCM_EEM; + DMFR_Msg1_t DMFR_Msg1; + DMFL_Msg1_t DMFL_Msg1; + TM_Stat_t TM_Stat; + TM_CP_t TM_CP; + HVC_CCU_Status_Msg_t HVC_CCU_Status_Msg; + BCM_VEH_STATE_t BCM_VEH_STATE; + EMS_HVC_Req_Msg_t EMS_HVC_Req_Msg; + HVC_Err_Status_Msg_t HVC_Err_Status_Msg; + BCM_CLIMATIC_DATA_t BCM_CLIMATIC_DATA; + VCU_CCU_Req_t VCU_CCU_Req; + ESC_08_t ESC_08; + SMFL_status_t SMFL_status; + SMFR_status_t SMFR_status; + SMRL_status_t SMRL_status; + SMRR_status_t SMRR_status; + SDM_Cmd_t SDM_Cmd; + VEH_VIN_t VEH_VIN; + OCUFL_MSG_t OCUFL_MSG; + OCUFR_MSG_t OCUFR_MSG; + OCURL_MSG_t OCURL_MSG; + OCURR_MSG_t OCURR_MSG; + DW_STATE_t DW_STATE; + FIU_CCU1_t FIU_CCU1; + FIU_CCU2_t FIU_CCU2; + FIU_CCU3_t FIU_CCU3; + Diag_To_CCU_t Diag_To_CCU; + Diag_Functional_t Diag_Functional; +} ccu_candb_rx_t; + +typedef struct +{ + CCU_HVC_Req_Msg_t CCU_HVC_Req_Msg; + CCU_Stat1_t CCU_Stat1; + CCU_Stat2_t CCU_Stat2; + CCU_Requests_t CCU_Requests; + CCU_Stat3_t CCU_Stat3; + CCU_VCU_Msg1_t CCU_VCU_Msg1; + CCU_VCU_Msg2_t CCU_VCU_Msg2; + CCU_Msg1_t CCU_Msg1; + CCU_Errors_t CCU_Errors; + CCU_Msg3_t CCU_Msg3; + Diag_From_CCU_t Diag_From_CCU; + CCU_AC_Ctrl_t CCU_AC_Ctrl; +} ccu_candb_tx_t; + +uint32_t ccu_candb_Receive(ccu_candb_rx_t* m, const uint8_t* d, uint32_t msgid, uint8_t dlc); + +#ifdef __DEF_CCU_CANDB__ + +extern ccu_candb_rx_t ccu_candb_rx; + +extern ccu_candb_tx_t ccu_candb_tx; + +#endif // __DEF_CCU_CANDB__ + +#ifdef __cplusplus +} +#endif diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/cgw_candb-binutil.c b/MODULES/HVAC_M7_CAN_MATRIX/butl/cgw_candb-binutil.c new file mode 100644 index 0000000..8ae551f --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/cgw_candb-binutil.c @@ -0,0 +1,429 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#include "cgw_candb-binutil.h" + +// DBC file version +#if (VER_CANDB_MAJ != (0U)) || (VER_CANDB_MIN != (0U)) +#error The CGW_CANDB binutil source file has inconsistency with core dbc lib! +#endif + +#ifdef __DEF_CGW_CANDB__ + +cgw_candb_rx_t cgw_candb_rx; + +cgw_candb_tx_t cgw_candb_tx; + +#endif // __DEF_CGW_CANDB__ + +uint32_t cgw_candb_Receive(cgw_candb_rx_t* _m, const uint8_t* _d, uint32_t _id, uint8_t dlc_) +{ + uint32_t recid = 0; + if ((_id >= 0x51U) && (_id < 0x523U)) { + if ((_id >= 0x51U) && (_id < 0x2F0U)) { + if ((_id >= 0x51U) && (_id < 0x243U)) { + if ((_id >= 0x51U) && (_id < 0xBFU)) { + if ((_id >= 0x51U) && (_id < 0x94U)) { + if (_id == 0x51U) { + recid = Unpack_SDM_MAS_Req_candb(&(_m->SDM_MAS_Req), _d, dlc_); + } else { + if (_id == 0x8FU) { + recid = Unpack_VAU_TCU_Hash_Resp_candb(&(_m->VAU_TCU_Hash_Resp), _d, dlc_); + } else if (_id == 0x91U) { + recid = Unpack_VAU_EMS_VCU_Hash_Resp_candb(&(_m->VAU_EMS_VCU_Hash_Resp), _d, dlc_); + } + } + } else { + if (_id == 0x94U) { + recid = Unpack_VAU2_INVRL_Hash_Resp_candb(&(_m->VAU2_INVRL_Hash_Resp), _d, dlc_); + } else { + if (_id == 0x95U) { + recid = Unpack_WChF_NFC_VAU_Transfer_State_candb(&(_m->WChF_NFC_VAU_Transfer_State), _d, dlc_); + } else if (_id == 0x98U) { + recid = Unpack_VAU2_INVRR_Hash_Resp_candb(&(_m->VAU2_INVRR_Hash_Resp), _d, dlc_); + } + } + } + } else { + if ((_id >= 0xBFU) && (_id < 0x152U)) { + if (_id == 0xBFU) { + recid = Unpack_VAU2_INVF_Hash_Resp_candb(&(_m->VAU2_INVF_Hash_Resp), _d, dlc_); + } else { + if (_id == 0xE3U) { + recid = Unpack_FTCU_DAT1_candb(&(_m->FTCU_DAT1), _d, dlc_); + } else if (_id == 0xE5U) { + recid = Unpack_FTCU_DAT3_candb(&(_m->FTCU_DAT3), _d, dlc_); + } + } + } else { + if (_id == 0x152U) { + recid = Unpack_BCM_Powertrain_candb(&(_m->BCM_Powertrain), _d, dlc_); + } else { + if (_id == 0x157U) { + recid = Unpack_BCM_EEM_candb(&(_m->BCM_EEM), _d, dlc_); + } else if (_id == 0x231U) { + recid = Unpack_BCM_ExteriorLightState_candb(&(_m->BCM_ExteriorLightState), _d, dlc_); + } + } + } + } + } else { + if ((_id >= 0x243U) && (_id < 0x24CU)) { + if ((_id >= 0x243U) && (_id < 0x246U)) { + if (_id == 0x243U) { + recid = Unpack_DMFR_Msg1_candb(&(_m->DMFR_Msg1), _d, dlc_); + } else { + if (_id == 0x244U) { + recid = Unpack_DMFL_Msg1_candb(&(_m->DMFL_Msg1), _d, dlc_); + } else if (_id == 0x245U) { + recid = Unpack_DMRL_Msg1_candb(&(_m->DMRL_Msg1), _d, dlc_); + } + } + } else { + if (_id == 0x246U) { + recid = Unpack_DMRR_Msg1_candb(&(_m->DMRR_Msg1), _d, dlc_); + } else { + if (_id == 0x247U) { + recid = Unpack_TM_Stat_candb(&(_m->TM_Stat), _d, dlc_); + } else if (_id == 0x249U) { + recid = Unpack_PTG_Body_Stat_candb(&(_m->PTG_Body_Stat), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x24CU) && (_id < 0x280U)) { + if (_id == 0x24CU) { + recid = Unpack_TM_CP_candb(&(_m->TM_CP), _d, dlc_); + } else { + if (_id == 0x24FU) { + recid = Unpack_VAU2_Msg2_candb(&(_m->VAU2_Msg2), _d, dlc_); + } else if (_id == 0x251U) { + recid = Unpack_BCM_DMS_01_candb(&(_m->BCM_DMS_01), _d, dlc_); + } + } + } else { + if ((_id >= 0x280U) && (_id < 0x283U)) { + if (_id == 0x280U) { + recid = Unpack_BCM_VEH_STATE_candb(&(_m->BCM_VEH_STATE), _d, dlc_); + } else if (_id == 0x282U) { + recid = Unpack_BCM_Veh_State2_candb(&(_m->BCM_Veh_State2), _d, dlc_); + } + } else { + if (_id == 0x283U) { + recid = Unpack_BCM_ALS_Light_Front_candb(&(_m->BCM_ALS_Light_Front), _d, dlc_); + } else if (_id == 0x284U) { + recid = Unpack_BCM_ALS_Light_Rear_candb(&(_m->BCM_ALS_Light_Rear), _d, dlc_); + } + } + } + } + } + } else { + if ((_id >= 0x2F0U) && (_id < 0x4D1U)) { + if ((_id >= 0x2F0U) && (_id < 0x315U)) { + if ((_id >= 0x2F0U) && (_id < 0x311U)) { + if (_id == 0x2F0U) { + recid = Unpack_BCM_Lock_CTR_candb(&(_m->BCM_Lock_CTR), _d, dlc_); + } else { + if (_id == 0x308U) { + recid = Unpack_BCM_DCDC12_CNTRL_candb(&(_m->BCM_DCDC12_CNTRL), _d, dlc_); + } else if (_id == 0x310U) { + recid = Unpack_CCU_HVC_Req_Msg_candb(&(_m->CCU_HVC_Req_Msg), _d, dlc_); + } + } + } else { + if (_id == 0x311U) { + recid = Unpack_CCU_Stat1_candb(&(_m->CCU_Stat1), _d, dlc_); + } else { + if (_id == 0x312U) { + recid = Unpack_CCU_Stat2_candb(&(_m->CCU_Stat2), _d, dlc_); + } else if (_id == 0x314U) { + recid = Unpack_CCU_Stat3_candb(&(_m->CCU_Stat3), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x315U) && (_id < 0x365U)) { + if (_id == 0x315U) { + recid = Unpack_CCU_VCU_Msg1_candb(&(_m->CCU_VCU_Msg1), _d, dlc_); + } else { + if (_id == 0x316U) { + recid = Unpack_CCU_VCU_Msg2_candb(&(_m->CCU_VCU_Msg2), _d, dlc_); + } else if (_id == 0x362U) { + recid = Unpack_BCM_IC_Info_Msg_candb(&(_m->BCM_IC_Info_Msg), _d, dlc_); + } + } + } else { + if ((_id >= 0x365U) && (_id < 0x3CBU)) { + if (_id == 0x365U) { + recid = Unpack_BCM_CLIMATIC_DATA_candb(&(_m->BCM_CLIMATIC_DATA), _d, dlc_); + } else if (_id == 0x380U) { + recid = Unpack_CCU_Msg1_candb(&(_m->CCU_Msg1), _d, dlc_); + } + } else { + if (_id == 0x3CBU) { + recid = Unpack_WChF_Status_candb(&(_m->WChF_Status), _d, dlc_); + } else if (_id == 0x4D0U) { + recid = Unpack_SMFL_status_candb(&(_m->SMFL_status), _d, dlc_); + } + } + } + } + } else { + if ((_id >= 0x4D1U) && (_id < 0x4FEU)) { + if ((_id >= 0x4D1U) && (_id < 0x4D4U)) { + if (_id == 0x4D1U) { + recid = Unpack_SMFR_status_candb(&(_m->SMFR_status), _d, dlc_); + } else { + if (_id == 0x4D2U) { + recid = Unpack_SMRL_status_candb(&(_m->SMRL_status), _d, dlc_); + } else if (_id == 0x4D3U) { + recid = Unpack_SMRR_status_candb(&(_m->SMRR_status), _d, dlc_); + } + } + } else { + if (_id == 0x4D4U) { + recid = Unpack_DocSL_T_FL_candb(&(_m->DocSL_T_FL), _d, dlc_); + } else { + if (_id == 0x4D5U) { + recid = Unpack_DocSR_T_FR_candb(&(_m->DocSR_T_FR), _d, dlc_); + } else if (_id == 0x4F0U) { + recid = Unpack_VAU_TPMS_Msg_candb(&(_m->VAU_TPMS_Msg), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x4FEU) && (_id < 0x512U)) { + if (_id == 0x4FEU) { + recid = Unpack_CCU_Errors_candb(&(_m->CCU_Errors), _d, dlc_); + } else { + if (_id == 0x501U) { + recid = Unpack_CCU_Msg3_candb(&(_m->CCU_Msg3), _d, dlc_); + } else if (_id == 0x50EU) { + recid = Unpack_IC_SDM_Info_candb(&(_m->IC_SDM_Info), _d, dlc_); + } + } + } else { + if ((_id >= 0x512U) && (_id < 0x521U)) { + if (_id == 0x512U) { + recid = Unpack_IC_SDM_Info_02_candb(&(_m->IC_SDM_Info_02), _d, dlc_); + } else if (_id == 0x51AU) { + recid = Unpack_VEH_VIN_candb(&(_m->VEH_VIN), _d, dlc_); + } + } else { + if (_id == 0x521U) { + recid = Unpack_OCUFL_MSG_candb(&(_m->OCUFL_MSG), _d, dlc_); + } else if (_id == 0x522U) { + recid = Unpack_OCUFR_MSG_candb(&(_m->OCUFR_MSG), _d, dlc_); + } + } + } + } + } + } + } else { + if ((_id >= 0x523U) && (_id < 0x7B4U)) { + if ((_id >= 0x523U) && (_id < 0x728U)) { + if ((_id >= 0x523U) && (_id < 0x630U)) { + if ((_id >= 0x523U) && (_id < 0x5ACU)) { + if (_id == 0x523U) { + recid = Unpack_OCURL_MSG_candb(&(_m->OCURL_MSG), _d, dlc_); + } else { + if (_id == 0x524U) { + recid = Unpack_OCURR_MSG_candb(&(_m->OCURR_MSG), _d, dlc_); + } else if (_id == 0x525U) { + recid = Unpack_RBCU_BODY_Stat_candb(&(_m->RBCU_BODY_Stat), _d, dlc_); + } + } + } else { + if (_id == 0x5ACU) { + recid = Unpack_BCM_UserConfig_Stat_candb(&(_m->BCM_UserConfig_Stat), _d, dlc_); + } else { + if (_id == 0x601U) { + recid = Unpack_WChF_FIU_TransferState_candb(&(_m->WChF_FIU_TransferState), _d, dlc_); + } else if (_id == 0x622U) { + recid = Unpack_VAU_BLE_Device_candb(&(_m->VAU_BLE_Device), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x630U) && (_id < 0x703U)) { + if (_id == 0x630U) { + recid = Unpack_Diag_From_APU_candb(&(_m->Diag_From_APU), _d, dlc_); + } else { + if (_id == 0x6D0U) { + recid = Unpack_PTG_To_SupplierTool_candb(&(_m->PTG_To_SupplierTool), _d, dlc_); + } else if (_id == 0x701U) { + recid = Unpack_Diag_From_CCPF_candb(&(_m->Diag_From_CCPF), _d, dlc_); + } + } + } else { + if (_id == 0x703U) { + recid = Unpack_Diag_From_CCPR_candb(&(_m->Diag_From_CCPR), _d, dlc_); + } else { + if (_id == 0x716U) { + recid = Unpack_Diag_From_SSL_candb(&(_m->Diag_From_SSL), _d, dlc_); + } else if (_id == 0x719U) { + recid = Unpack_Diag_From_SSR_candb(&(_m->Diag_From_SSR), _d, dlc_); + } + } + } + } + } else { + if ((_id >= 0x728U) && (_id < 0x794U)) { + if ((_id >= 0x728U) && (_id < 0x72EU)) { + if (_id == 0x728U) { + recid = Unpack_Diag_From_FCSilCU_candb(&(_m->Diag_From_FCSilCU), _d, dlc_); + } else { + if (_id == 0x72CU) { + recid = Unpack_Diag_From_FLDSilCU_candb(&(_m->Diag_From_FLDSilCU), _d, dlc_); + } else if (_id == 0x72DU) { + recid = Unpack_Diag_From_FRDSilCU_candb(&(_m->Diag_From_FRDSilCU), _d, dlc_); + } + } + } else { + if (_id == 0x72EU) { + recid = Unpack_Diag_From_ICLSilCU_candb(&(_m->Diag_From_ICLSilCU), _d, dlc_); + } else { + if (_id == 0x74AU) { + recid = Unpack_Diag_From_FTCU_candb(&(_m->Diag_From_FTCU), _d, dlc_); + } else if (_id == 0x77FU) { + recid = Unpack_Diag_From_SRoof_candb(&(_m->Diag_From_SRoof), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x794U) && (_id < 0x799U)) { + if (_id == 0x794U) { + recid = Unpack_Diag_From_ICRSilCU_candb(&(_m->Diag_From_ICRSilCU), _d, dlc_); + } else { + if (_id == 0x797U) { + recid = Unpack_Diag_From_LB_pSilCU_candb(&(_m->Diag_From_LB_pSilCU), _d, dlc_); + } else if (_id == 0x798U) { + recid = Unpack_Diag_From_PLSilCU_candb(&(_m->Diag_From_PLSilCU), _d, dlc_); + } + } + } else { + if ((_id >= 0x799U) && (_id < 0x7B0U)) { + if (_id == 0x799U) { + recid = Unpack_Diag_From_PRSilCU_candb(&(_m->Diag_From_PRSilCU), _d, dlc_); + } else if (_id == 0x79CU) { + recid = Unpack_Diag_From_RB_pSilCU_candb(&(_m->Diag_From_RB_pSilCU), _d, dlc_); + } + } else { + if (_id == 0x7B0U) { + recid = Unpack_Diag_From_VAU_candb(&(_m->Diag_From_VAU), _d, dlc_); + } else if (_id == 0x7B3U) { + recid = Unpack_Diag_From_BCM_candb(&(_m->Diag_From_BCM), _d, dlc_); + } + } + } + } + } + } else { + if ((_id >= 0x7B4U) && (_id < 0x7CDU)) { + if ((_id >= 0x7B4U) && (_id < 0x7BBU)) { + if ((_id >= 0x7B4U) && (_id < 0x7B7U)) { + if (_id == 0x7B4U) { + recid = Unpack_Diag_From_DMFL_candb(&(_m->Diag_From_DMFL), _d, dlc_); + } else { + if (_id == 0x7B5U) { + recid = Unpack_Diag_From_DMFR_candb(&(_m->Diag_From_DMFR), _d, dlc_); + } else if (_id == 0x7B6U) { + recid = Unpack_Diag_From_DMRL_candb(&(_m->Diag_From_DMRL), _d, dlc_); + } + } + } else { + if (_id == 0x7B7U) { + recid = Unpack_Diag_From_DMRR_candb(&(_m->Diag_From_DMRR), _d, dlc_); + } else { + if (_id == 0x7B9U) { + recid = Unpack_Diag_From_SMRR_candb(&(_m->Diag_From_SMRR), _d, dlc_); + } else if (_id == 0x7BAU) { + recid = Unpack_Diag_From_TM_candb(&(_m->Diag_From_TM), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x7BBU) && (_id < 0x7BFU)) { + if (_id == 0x7BBU) { + recid = Unpack_Diag_From_CCU_candb(&(_m->Diag_From_CCU), _d, dlc_); + } else { + if (_id == 0x7BDU) { + recid = Unpack_Diag_From_SMFL_candb(&(_m->Diag_From_SMFL), _d, dlc_); + } else if (_id == 0x7BEU) { + recid = Unpack_Diag_From_SMFR_candb(&(_m->Diag_From_SMFR), _d, dlc_); + } + } + } else { + if ((_id >= 0x7BFU) && (_id < 0x7CBU)) { + if (_id == 0x7BFU) { + recid = Unpack_Diag_From_SMRL_candb(&(_m->Diag_From_SMRL), _d, dlc_); + } else if (_id == 0x7C6U) { + recid = Unpack_Diag_From_OCUFL_candb(&(_m->Diag_From_OCUFL), _d, dlc_); + } + } else { + if (_id == 0x7CBU) { + recid = Unpack_Diag_From_PTG_candb(&(_m->Diag_From_PTG), _d, dlc_); + } else if (_id == 0x7CCU) { + recid = Unpack_Diag_From_OCUFR_candb(&(_m->Diag_From_OCUFR), _d, dlc_); + } + } + } + } + } else { + if ((_id >= 0x7CDU) && (_id < 0x7D8U)) { + if ((_id >= 0x7CDU) && (_id < 0x7D2U)) { + if (_id == 0x7CDU) { + recid = Unpack_Diag_From_OCURL_candb(&(_m->Diag_From_OCURL), _d, dlc_); + } else { + if (_id == 0x7CEU) { + recid = Unpack_Diag_From_OCURR_candb(&(_m->Diag_From_OCURR), _d, dlc_); + } else if (_id == 0x7D1U) { + recid = Unpack_Diag_From_RCLSilCU_candb(&(_m->Diag_From_RCLSilCU), _d, dlc_); + } + } + } else { + if (_id == 0x7D2U) { + recid = Unpack_Diag_From_RCRSilCU_candb(&(_m->Diag_From_RCRSilCU), _d, dlc_); + } else { + if (_id == 0x7D3U) { + recid = Unpack_Diag_From_RDLSilCU_candb(&(_m->Diag_From_RDLSilCU), _d, dlc_); + } else if (_id == 0x7D4U) { + recid = Unpack_Diag_From_RDRSilCU_candb(&(_m->Diag_From_RDRSilCU), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x7D8U) && (_id < 0x7F7U)) { + if (_id == 0x7D8U) { + recid = Unpack_Diag_From_RLDSilCU_candb(&(_m->Diag_From_RLDSilCU), _d, dlc_); + } else { + if (_id == 0x7D9U) { + recid = Unpack_Diag_From_RRDSilCU_candb(&(_m->Diag_From_RRDSilCU), _d, dlc_); + } else if (_id == 0x7F5U) { + recid = Unpack_Diag_From_SFRSilCU_candb(&(_m->Diag_From_SFRSilCU), _d, dlc_); + } + } + } else { + if ((_id >= 0x7F7U) && (_id < 0x7F9U)) { + if (_id == 0x7F7U) { + recid = Unpack_Diag_From_SFLSilCU_candb(&(_m->Diag_From_SFLSilCU), _d, dlc_); + } else if (_id == 0x7F8U) { + recid = Unpack_Diag_From_WHFL_candb(&(_m->Diag_From_WHFL), _d, dlc_); + } + } else { + if (_id == 0x7F9U) { + recid = Unpack_Diag_From_WHFR_candb(&(_m->Diag_From_WHFR), _d, dlc_); + } else if (_id == 0x18FFF200U) { + recid = Unpack_CCU_AC_Ctrl_candb(&(_m->CCU_AC_Ctrl), _d, dlc_); + } + } + } + } + } + } + } + + return recid; +} + diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/cgw_candb-binutil.h b/MODULES/HVAC_M7_CAN_MATRIX/butl/cgw_candb-binutil.h new file mode 100644 index 0000000..7f9ffc5 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/cgw_candb-binutil.h @@ -0,0 +1,241 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dbccodeconf.h" + +#include "candb.h" + +typedef struct +{ + SDM_MAS_Req_t SDM_MAS_Req; + VAU_TCU_Hash_Resp_t VAU_TCU_Hash_Resp; + VAU_EMS_VCU_Hash_Resp_t VAU_EMS_VCU_Hash_Resp; + VAU2_INVRL_Hash_Resp_t VAU2_INVRL_Hash_Resp; + WChF_NFC_VAU_Transfer_State_t WChF_NFC_VAU_Transfer_State; + VAU2_INVRR_Hash_Resp_t VAU2_INVRR_Hash_Resp; + VAU2_INVF_Hash_Resp_t VAU2_INVF_Hash_Resp; + FTCU_DAT1_t FTCU_DAT1; + FTCU_DAT3_t FTCU_DAT3; + BCM_Powertrain_t BCM_Powertrain; + BCM_EEM_t BCM_EEM; + BCM_ExteriorLightState_t BCM_ExteriorLightState; + DMFR_Msg1_t DMFR_Msg1; + DMFL_Msg1_t DMFL_Msg1; + DMRL_Msg1_t DMRL_Msg1; + DMRR_Msg1_t DMRR_Msg1; + TM_Stat_t TM_Stat; + PTG_Body_Stat_t PTG_Body_Stat; + TM_CP_t TM_CP; + VAU2_Msg2_t VAU2_Msg2; + BCM_DMS_01_t BCM_DMS_01; + BCM_VEH_STATE_t BCM_VEH_STATE; + BCM_Veh_State2_t BCM_Veh_State2; + BCM_ALS_Light_Front_t BCM_ALS_Light_Front; + BCM_ALS_Light_Rear_t BCM_ALS_Light_Rear; + BCM_Lock_CTR_t BCM_Lock_CTR; + BCM_DCDC12_CNTRL_t BCM_DCDC12_CNTRL; + CCU_HVC_Req_Msg_t CCU_HVC_Req_Msg; + CCU_Stat1_t CCU_Stat1; + CCU_Stat2_t CCU_Stat2; + CCU_Stat3_t CCU_Stat3; + CCU_VCU_Msg1_t CCU_VCU_Msg1; + CCU_VCU_Msg2_t CCU_VCU_Msg2; + BCM_IC_Info_Msg_t BCM_IC_Info_Msg; + BCM_CLIMATIC_DATA_t BCM_CLIMATIC_DATA; + CCU_Msg1_t CCU_Msg1; + WChF_Status_t WChF_Status; + SMFL_status_t SMFL_status; + SMFR_status_t SMFR_status; + SMRL_status_t SMRL_status; + SMRR_status_t SMRR_status; + DocSL_T_FL_t DocSL_T_FL; + DocSR_T_FR_t DocSR_T_FR; + VAU_TPMS_Msg_t VAU_TPMS_Msg; + CCU_Errors_t CCU_Errors; + CCU_Msg3_t CCU_Msg3; + IC_SDM_Info_t IC_SDM_Info; + IC_SDM_Info_02_t IC_SDM_Info_02; + VEH_VIN_t VEH_VIN; + OCUFL_MSG_t OCUFL_MSG; + OCUFR_MSG_t OCUFR_MSG; + OCURL_MSG_t OCURL_MSG; + OCURR_MSG_t OCURR_MSG; + RBCU_BODY_Stat_t RBCU_BODY_Stat; + BCM_UserConfig_Stat_t BCM_UserConfig_Stat; + WChF_FIU_TransferState_t WChF_FIU_TransferState; + VAU_BLE_Device_t VAU_BLE_Device; + Diag_From_APU_t Diag_From_APU; + PTG_To_SupplierTool_t PTG_To_SupplierTool; + Diag_From_CCPF_t Diag_From_CCPF; + Diag_From_CCPR_t Diag_From_CCPR; + Diag_From_SSL_t Diag_From_SSL; + Diag_From_SSR_t Diag_From_SSR; + Diag_From_FCSilCU_t Diag_From_FCSilCU; + Diag_From_FLDSilCU_t Diag_From_FLDSilCU; + Diag_From_FRDSilCU_t Diag_From_FRDSilCU; + Diag_From_ICLSilCU_t Diag_From_ICLSilCU; + Diag_From_FTCU_t Diag_From_FTCU; + Diag_From_SRoof_t Diag_From_SRoof; + Diag_From_ICRSilCU_t Diag_From_ICRSilCU; + Diag_From_LB_pSilCU_t Diag_From_LB_pSilCU; + Diag_From_PLSilCU_t Diag_From_PLSilCU; + Diag_From_PRSilCU_t Diag_From_PRSilCU; + Diag_From_RB_pSilCU_t Diag_From_RB_pSilCU; + Diag_From_VAU_t Diag_From_VAU; + Diag_From_BCM_t Diag_From_BCM; + Diag_From_DMFL_t Diag_From_DMFL; + Diag_From_DMFR_t Diag_From_DMFR; + Diag_From_DMRL_t Diag_From_DMRL; + Diag_From_DMRR_t Diag_From_DMRR; + Diag_From_SMRR_t Diag_From_SMRR; + Diag_From_TM_t Diag_From_TM; + Diag_From_CCU_t Diag_From_CCU; + Diag_From_SMFL_t Diag_From_SMFL; + Diag_From_SMFR_t Diag_From_SMFR; + Diag_From_SMRL_t Diag_From_SMRL; + Diag_From_OCUFL_t Diag_From_OCUFL; + Diag_From_PTG_t Diag_From_PTG; + Diag_From_OCUFR_t Diag_From_OCUFR; + Diag_From_OCURL_t Diag_From_OCURL; + Diag_From_OCURR_t Diag_From_OCURR; + Diag_From_RCLSilCU_t Diag_From_RCLSilCU; + Diag_From_RCRSilCU_t Diag_From_RCRSilCU; + Diag_From_RDLSilCU_t Diag_From_RDLSilCU; + Diag_From_RDRSilCU_t Diag_From_RDRSilCU; + Diag_From_RLDSilCU_t Diag_From_RLDSilCU; + Diag_From_RRDSilCU_t Diag_From_RRDSilCU; + Diag_From_SFRSilCU_t Diag_From_SFRSilCU; + Diag_From_SFLSilCU_t Diag_From_SFLSilCU; + Diag_From_WHFL_t Diag_From_WHFL; + Diag_From_WHFR_t Diag_From_WHFR; + CCU_AC_Ctrl_t CCU_AC_Ctrl; +} cgw_candb_rx_t; + +typedef struct +{ + EMS_VCU_VAU_Immo_Req_t EMS_VCU_VAU_Immo_Req; + TCU_VAU_Immo_Req_t TCU_VAU_Immo_Req; + TCU_R932_1_t TCU_R932_1; + SCU_02_t SCU_02; + ESC_04_t ESC_04; + ESC_09_t ESC_09; + ESC_YRS_01_t ESC_YRS_01; + EMS_Veh_t EMS_Veh; + EMS_Indicators_t EMS_Indicators; + EMS_Veh_02_t EMS_Veh_02; + EMS_EEM_01_t EMS_EEM_01; + EMS_EEM_02_t EMS_EEM_02; + DAS_01_t DAS_01; + DAS_04_t DAS_04; + VCU_DriveInfo_t VCU_DriveInfo; + DAS_02_t DAS_02; + DAS_07_t DAS_07; + ACU_01_t ACU_01; + EPB_Status_t EPB_Status; + SWM_ContrlsState_t SWM_ContrlsState; + FIU_Access_Msg1_t FIU_Access_Msg1; + HVC_CCU_Status_Msg_t HVC_CCU_Status_Msg; + ATS_Status_t ATS_Status; + EMS_HVC_Req_Msg_t EMS_HVC_Req_Msg; + SAS_Standard_t SAS_Standard; + IC_ABSOLUTE_CLOCK_t IC_ABSOLUTE_CLOCK; + HVC_Err_Status_Msg_t HVC_Err_Status_Msg; + VCU_CCU_Req_t VCU_CCU_Req; + IC_DATA_MSG_t IC_DATA_MSG; + ESC_08_t ESC_08; + MAS_Status_t MAS_Status; + EPB_VM_MSG_t EPB_VM_MSG; + CGW_COMM_REQ_t CGW_COMM_REQ; + DCDC1248_01_t DCDC1248_01; + FIU_REQ_CTR_01_t FIU_REQ_CTR_01; + DCDC1248_02_t DCDC1248_02; + FIU_Access_Msg2_t FIU_Access_Msg2; + USBSw_Stat_t USBSw_Stat; + FIU_Cmd_t FIU_Cmd; + HUD_MSG_STATUS_t HUD_MSG_STATUS; + FIU_SMRL_REQ_CTR_SEATS_t FIU_SMRL_REQ_CTR_SEATS; + FIU_SMFR_REQ_CTR_SEATS_t FIU_SMFR_REQ_CTR_SEATS; + FIU_SMFL_REQ_CTR_SEATS_t FIU_SMFL_REQ_CTR_SEATS; + FIU_SMRR_REQ_CTR_SEATS_t FIU_SMRR_REQ_CTR_SEATS; + FIU_CTRL_DW_t FIU_CTRL_DW; + DW_STATE_t DW_STATE; + FIU_Msg1_t FIU_Msg1; + FIU_Msg2_t FIU_Msg2; + ERAG_DATA_MSG_t ERAG_DATA_MSG; + FIU_Msg3_t FIU_Msg3; + FIU_EngMenu_t FIU_EngMenu; + FIU_CCU1_t FIU_CCU1; + FIU_CCU2_t FIU_CCU2; + FIU_CCU3_t FIU_CCU3; + IC_DISPLAY_CLOCK_t IC_DISPLAY_CLOCK; + FIU_MAS_Main_t FIU_MAS_Main; + MAS_APA_Paths_t MAS_APA_Paths; + MAS_APA_ParkPlace_t MAS_APA_ParkPlace; + IntCOM_Info_Stat_t IntCOM_Info_Stat; + LTE_Sum_State2_t LTE_Sum_State2; + FIU_WChF_TransferState_t FIU_WChF_TransferState; + SupplierTool_To_PTG_t SupplierTool_To_PTG; + Diag_To_CCPF_t Diag_To_CCPF; + Diag_To_CCPR_t Diag_To_CCPR; + Diag_To_SSL_t Diag_To_SSL; + Diag_To_SSR_t Diag_To_SSR; + Diag_To_FCSilCU_t Diag_To_FCSilCU; + Diag_To_FLDSilCU_t Diag_To_FLDSilCU; + Diag_To_FRDSilCU_t Diag_To_FRDSilCU; + Diag_To_ICLSilCU_t Diag_To_ICLSilCU; + Diag_To_APU_t Diag_To_APU; + Diag_To_FTCU_t Diag_To_FTCU; + Diag_To_Sroof_t Diag_To_Sroof; + Diag_To_ICRSilCU_t Diag_To_ICRSilCU; + Diag_To_LB_pSilCU_t Diag_To_LB_pSilCU; + Diag_To_PLSilCU_t Diag_To_PLSilCU; + Diag_To_PRSilCU_t Diag_To_PRSilCU; + Diag_To_RB_pSilCU_t Diag_To_RB_pSilCU; + Diag_To_VAU_t Diag_To_VAU; + Diag_To_BCM_t Diag_To_BCM; + Diag_To_DMFL_t Diag_To_DMFL; + Diag_To_DMFR_t Diag_To_DMFR; + Diag_To_DMRL_t Diag_To_DMRL; + Diag_To_DMRR_t Diag_To_DMRR; + Diag_To_SMRR_t Diag_To_SMRR; + Diag_To_TM_t Diag_To_TM; + Diag_To_CCU_t Diag_To_CCU; + Diag_To_SMFL_t Diag_To_SMFL; + Diag_To_SMFR_t Diag_To_SMFR; + Diag_To_SMRL_t Diag_To_SMRL; + Diag_To_RCLSilCU_t Diag_To_RCLSilCU; + Diag_To_RCRSilCU_t Diag_To_RCRSilCU; + Diag_To_RDLSilCU_t Diag_To_RDLSilCU; + Diag_To_RDRSilCU_t Diag_To_RDRSilCU; + Diag_To_RLDSilCU_t Diag_To_RLDSilCU; + Diag_To_RRDSilCU_t Diag_To_RRDSilCU; + Diag_To_OCUFL_t Diag_To_OCUFL; + Diag_To_PTG_t Diag_To_PTG; + Diag_To_OCUFR_t Diag_To_OCUFR; + Diag_To_OCURL_t Diag_To_OCURL; + Diag_To_OCURR_t Diag_To_OCURR; + Diag_Functional_t Diag_Functional; + Diag_To_SFRSilCU_t Diag_To_SFRSilCU; + Diag_To_SFLSilCU_t Diag_To_SFLSilCU; + Diag_To_WHFL_t Diag_To_WHFL; + Diag_To_WHFR_t Diag_To_WHFR; +} cgw_candb_tx_t; + +uint32_t cgw_candb_Receive(cgw_candb_rx_t* m, const uint8_t* d, uint32_t msgid, uint8_t dlc); + +#ifdef __DEF_CGW_CANDB__ + +extern cgw_candb_rx_t cgw_candb_rx; + +extern cgw_candb_tx_t cgw_candb_tx; + +#endif // __DEF_CGW_CANDB__ + +#ifdef __cplusplus +} +#endif diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/dmfl_candb-binutil.c b/MODULES/HVAC_M7_CAN_MATRIX/butl/dmfl_candb-binutil.c new file mode 100644 index 0000000..9a435cc --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/dmfl_candb-binutil.c @@ -0,0 +1,161 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#include "dmfl_candb-binutil.h" + +// DBC file version +#if (VER_CANDB_MAJ != (0U)) || (VER_CANDB_MIN != (0U)) +#error The DMFL_CANDB binutil source file has inconsistency with core dbc lib! +#endif + +#ifdef __DEF_DMFL_CANDB__ + +dmfl_candb_rx_t dmfl_candb_rx; + +dmfl_candb_tx_t dmfl_candb_tx; + +#endif // __DEF_DMFL_CANDB__ + +uint32_t dmfl_candb_Receive(dmfl_candb_rx_t* _m, const uint8_t* _d, uint32_t _id, uint8_t dlc_) +{ + uint32_t recid = 0; + if ((_id >= 0xB1U) && (_id < 0x36AU)) { + if ((_id >= 0xB1U) && (_id < 0x231U)) { + if ((_id >= 0xB1U) && (_id < 0x162U)) { + if ((_id >= 0xB1U) && (_id < 0x157U)) { + if (_id == 0xB1U) { + recid = Unpack_TCU_R932_1_candb(&(_m->TCU_R932_1), _d, dlc_); + } else if (_id == 0x100U) { + recid = Unpack_ESC_04_candb(&(_m->ESC_04), _d, dlc_); + } + } else { + if (_id == 0x157U) { + recid = Unpack_BCM_EEM_candb(&(_m->BCM_EEM), _d, dlc_); + } else if (_id == 0x160U) { + recid = Unpack_DAS_01_candb(&(_m->DAS_01), _d, dlc_); + } + } + } else { + if ((_id >= 0x162U) && (_id < 0x20BU)) { + if (_id == 0x162U) { + recid = Unpack_DAS_04_candb(&(_m->DAS_04), _d, dlc_); + } else if (_id == 0x20AU) { + recid = Unpack_DAS_02_candb(&(_m->DAS_02), _d, dlc_); + } + } else { + if (_id == 0x20BU) { + recid = Unpack_DAS_07_candb(&(_m->DAS_07), _d, dlc_); + } else if (_id == 0x210U) { + recid = Unpack_ACU_01_candb(&(_m->ACU_01), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x231U) && (_id < 0x246U)) { + if ((_id >= 0x231U) && (_id < 0x243U)) { + if (_id == 0x231U) { + recid = Unpack_BCM_ExteriorLightState_candb(&(_m->BCM_ExteriorLightState), _d, dlc_); + } else if (_id == 0x23AU) { + recid = Unpack_BCM_StyleCmd1_candb(&(_m->BCM_StyleCmd1), _d, dlc_); + } + } else { + if (_id == 0x243U) { + recid = Unpack_DMFR_Msg1_candb(&(_m->DMFR_Msg1), _d, dlc_); + } else if (_id == 0x245U) { + recid = Unpack_DMRL_Msg1_candb(&(_m->DMRL_Msg1), _d, dlc_); + } + } + } else { + if ((_id >= 0x246U) && (_id < 0x282U)) { + if (_id == 0x246U) { + recid = Unpack_DMRR_Msg1_candb(&(_m->DMRR_Msg1), _d, dlc_); + } else if (_id == 0x280U) { + recid = Unpack_BCM_VEH_STATE_candb(&(_m->BCM_VEH_STATE), _d, dlc_); + } + } else { + if (_id == 0x282U) { + recid = Unpack_BCM_Veh_State2_candb(&(_m->BCM_Veh_State2), _d, dlc_); + } else { + if (_id == 0x2F0U) { + recid = Unpack_BCM_Lock_CTR_candb(&(_m->BCM_Lock_CTR), _d, dlc_); + } else if (_id == 0x365U) { + recid = Unpack_BCM_CLIMATIC_DATA_candb(&(_m->BCM_CLIMATIC_DATA), _d, dlc_); + } + } + } + } + } + } else { + if ((_id >= 0x36AU) && (_id < 0x594U)) { + if ((_id >= 0x36AU) && (_id < 0x4D0U)) { + if ((_id >= 0x36AU) && (_id < 0x38AU)) { + if (_id == 0x36AU) { + recid = Unpack_DMRR_SMRR_REQ_CTR_SEATS_candb(&(_m->DMRR_SMRR_REQ_CTR_SEATS), _d, dlc_); + } else if (_id == 0x380U) { + recid = Unpack_CCU_Msg1_candb(&(_m->CCU_Msg1), _d, dlc_); + } + } else { + if (_id == 0x38AU) { + recid = Unpack_Sroof_State_candb(&(_m->Sroof_State), _d, dlc_); + } else if (_id == 0x4B6U) { + recid = Unpack_FIU_Profile_candb(&(_m->FIU_Profile), _d, dlc_); + } + } + } else { + if ((_id >= 0x4D0U) && (_id < 0x51AU)) { + if (_id == 0x4D0U) { + recid = Unpack_SMFL_status_candb(&(_m->SMFL_status), _d, dlc_); + } else if (_id == 0x50FU) { + recid = Unpack_SDM_Cmd_candb(&(_m->SDM_Cmd), _d, dlc_); + } + } else { + if (_id == 0x51AU) { + recid = Unpack_VEH_VIN_candb(&(_m->VEH_VIN), _d, dlc_); + } else { + if (_id == 0x58EU) { + recid = Unpack_FIU_Msg1_candb(&(_m->FIU_Msg1), _d, dlc_); + } else if (_id == 0x58FU) { + recid = Unpack_FIU_Msg2_candb(&(_m->FIU_Msg2), _d, dlc_); + } + } + } + } + } else { + if ((_id >= 0x594U) && (_id < 0x5ACU)) { + if ((_id >= 0x594U) && (_id < 0x5A7U)) { + if (_id == 0x594U) { + recid = Unpack_FIU_Msg3_candb(&(_m->FIU_Msg3), _d, dlc_); + } else if (_id == 0x5A6U) { + recid = Unpack_BCM_StyleCmd2_candb(&(_m->BCM_StyleCmd2), _d, dlc_); + } + } else { + if (_id == 0x5A7U) { + recid = Unpack_BCM_StyleCmd3_candb(&(_m->BCM_StyleCmd3), _d, dlc_); + } else if (_id == 0x5A8U) { + recid = Unpack_BCM_WHF_Request_candb(&(_m->BCM_WHF_Request), _d, dlc_); + } + } + } else { + if ((_id >= 0x5ACU) && (_id < 0x7A4U)) { + if (_id == 0x5ACU) { + recid = Unpack_BCM_UserConfig_Stat_candb(&(_m->BCM_UserConfig_Stat), _d, dlc_); + } else if (_id == 0x71CU) { + recid = Unpack_Diag_To_FLDSilCU_candb(&(_m->Diag_To_FLDSilCU), _d, dlc_); + } + } else { + if (_id == 0x7A4U) { + recid = Unpack_Diag_To_DMFL_candb(&(_m->Diag_To_DMFL), _d, dlc_); + } else { + if (_id == 0x7DFU) { + recid = Unpack_Diag_Functional_candb(&(_m->Diag_Functional), _d, dlc_); + } else if (_id == 0x7F0U) { + recid = Unpack_Diag_To_WHFL_candb(&(_m->Diag_To_WHFL), _d, dlc_); + } + } + } + } + } + } + + return recid; +} + diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/dmfl_candb-binutil.h b/MODULES/HVAC_M7_CAN_MATRIX/butl/dmfl_candb-binutil.h new file mode 100644 index 0000000..3b9bceb --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/dmfl_candb-binutil.h @@ -0,0 +1,75 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dbccodeconf.h" + +#include "candb.h" + +typedef struct +{ + TCU_R932_1_t TCU_R932_1; + ESC_04_t ESC_04; + BCM_EEM_t BCM_EEM; + DAS_01_t DAS_01; + DAS_04_t DAS_04; + DAS_02_t DAS_02; + DAS_07_t DAS_07; + ACU_01_t ACU_01; + BCM_ExteriorLightState_t BCM_ExteriorLightState; + BCM_StyleCmd1_t BCM_StyleCmd1; + DMFR_Msg1_t DMFR_Msg1; + DMRL_Msg1_t DMRL_Msg1; + DMRR_Msg1_t DMRR_Msg1; + BCM_VEH_STATE_t BCM_VEH_STATE; + BCM_Veh_State2_t BCM_Veh_State2; + BCM_Lock_CTR_t BCM_Lock_CTR; + BCM_CLIMATIC_DATA_t BCM_CLIMATIC_DATA; + DMRR_SMRR_REQ_CTR_SEATS_t DMRR_SMRR_REQ_CTR_SEATS; + CCU_Msg1_t CCU_Msg1; + Sroof_State_t Sroof_State; + FIU_Profile_t FIU_Profile; + SMFL_status_t SMFL_status; + SDM_Cmd_t SDM_Cmd; + VEH_VIN_t VEH_VIN; + FIU_Msg1_t FIU_Msg1; + FIU_Msg2_t FIU_Msg2; + FIU_Msg3_t FIU_Msg3; + BCM_StyleCmd2_t BCM_StyleCmd2; + BCM_StyleCmd3_t BCM_StyleCmd3; + BCM_WHF_Request_t BCM_WHF_Request; + BCM_UserConfig_Stat_t BCM_UserConfig_Stat; + Diag_To_FLDSilCU_t Diag_To_FLDSilCU; + Diag_To_DMFL_t Diag_To_DMFL; + Diag_Functional_t Diag_Functional; + Diag_To_WHFL_t Diag_To_WHFL; +} dmfl_candb_rx_t; + +typedef struct +{ + DMFL_Msg1_t DMFL_Msg1; + DMFL_SMFL_REQ_CTR_SEATS_t DMFL_SMFL_REQ_CTR_SEATS; + WHFL_MSG1_t WHFL_MSG1; + FLDSilCU_State_t FLDSilCU_State; + Diag_From_FLDSilCU_t Diag_From_FLDSilCU; + Diag_From_DMFL_t Diag_From_DMFL; + Diag_From_WHFL_t Diag_From_WHFL; +} dmfl_candb_tx_t; + +uint32_t dmfl_candb_Receive(dmfl_candb_rx_t* m, const uint8_t* d, uint32_t msgid, uint8_t dlc); + +#ifdef __DEF_DMFL_CANDB__ + +extern dmfl_candb_rx_t dmfl_candb_rx; + +extern dmfl_candb_tx_t dmfl_candb_tx; + +#endif // __DEF_DMFL_CANDB__ + +#ifdef __cplusplus +} +#endif diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/dmfr_candb-binutil.c b/MODULES/HVAC_M7_CAN_MATRIX/butl/dmfr_candb-binutil.c new file mode 100644 index 0000000..1c19e22 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/dmfr_candb-binutil.c @@ -0,0 +1,149 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#include "dmfr_candb-binutil.h" + +// DBC file version +#if (VER_CANDB_MAJ != (0U)) || (VER_CANDB_MIN != (0U)) +#error The DMFR_CANDB binutil source file has inconsistency with core dbc lib! +#endif + +#ifdef __DEF_DMFR_CANDB__ + +dmfr_candb_rx_t dmfr_candb_rx; + +dmfr_candb_tx_t dmfr_candb_tx; + +#endif // __DEF_DMFR_CANDB__ + +uint32_t dmfr_candb_Receive(dmfr_candb_rx_t* _m, const uint8_t* _d, uint32_t _id, uint8_t dlc_) +{ + uint32_t recid = 0; + if ((_id >= 0xB1U) && (_id < 0x380U)) { + if ((_id >= 0xB1U) && (_id < 0x231U)) { + if ((_id >= 0xB1U) && (_id < 0x162U)) { + if ((_id >= 0xB1U) && (_id < 0x157U)) { + if (_id == 0xB1U) { + recid = Unpack_TCU_R932_1_candb(&(_m->TCU_R932_1), _d, dlc_); + } else if (_id == 0x100U) { + recid = Unpack_ESC_04_candb(&(_m->ESC_04), _d, dlc_); + } + } else { + if (_id == 0x157U) { + recid = Unpack_BCM_EEM_candb(&(_m->BCM_EEM), _d, dlc_); + } else if (_id == 0x160U) { + recid = Unpack_DAS_01_candb(&(_m->DAS_01), _d, dlc_); + } + } + } else { + if ((_id >= 0x162U) && (_id < 0x20BU)) { + if (_id == 0x162U) { + recid = Unpack_DAS_04_candb(&(_m->DAS_04), _d, dlc_); + } else if (_id == 0x20AU) { + recid = Unpack_DAS_02_candb(&(_m->DAS_02), _d, dlc_); + } + } else { + if (_id == 0x20BU) { + recid = Unpack_DAS_07_candb(&(_m->DAS_07), _d, dlc_); + } else if (_id == 0x210U) { + recid = Unpack_ACU_01_candb(&(_m->ACU_01), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x231U) && (_id < 0x282U)) { + if ((_id >= 0x231U) && (_id < 0x244U)) { + if (_id == 0x231U) { + recid = Unpack_BCM_ExteriorLightState_candb(&(_m->BCM_ExteriorLightState), _d, dlc_); + } else if (_id == 0x23AU) { + recid = Unpack_BCM_StyleCmd1_candb(&(_m->BCM_StyleCmd1), _d, dlc_); + } + } else { + if (_id == 0x244U) { + recid = Unpack_DMFL_Msg1_candb(&(_m->DMFL_Msg1), _d, dlc_); + } else if (_id == 0x280U) { + recid = Unpack_BCM_VEH_STATE_candb(&(_m->BCM_VEH_STATE), _d, dlc_); + } + } + } else { + if ((_id >= 0x282U) && (_id < 0x365U)) { + if (_id == 0x282U) { + recid = Unpack_BCM_Veh_State2_candb(&(_m->BCM_Veh_State2), _d, dlc_); + } else if (_id == 0x2F0U) { + recid = Unpack_BCM_Lock_CTR_candb(&(_m->BCM_Lock_CTR), _d, dlc_); + } + } else { + if (_id == 0x365U) { + recid = Unpack_BCM_CLIMATIC_DATA_candb(&(_m->BCM_CLIMATIC_DATA), _d, dlc_); + } else if (_id == 0x367U) { + recid = Unpack_DMFL_SMFL_REQ_CTR_SEATS_candb(&(_m->DMFL_SMFL_REQ_CTR_SEATS), _d, dlc_); + } + } + } + } + } else { + if ((_id >= 0x380U) && (_id < 0x5A6U)) { + if ((_id >= 0x380U) && (_id < 0x50FU)) { + if ((_id >= 0x380U) && (_id < 0x4B6U)) { + if (_id == 0x380U) { + recid = Unpack_CCU_Msg1_candb(&(_m->CCU_Msg1), _d, dlc_); + } else if (_id == 0x38AU) { + recid = Unpack_Sroof_State_candb(&(_m->Sroof_State), _d, dlc_); + } + } else { + if (_id == 0x4B6U) { + recid = Unpack_FIU_Profile_candb(&(_m->FIU_Profile), _d, dlc_); + } else if (_id == 0x4D1U) { + recid = Unpack_SMFR_status_candb(&(_m->SMFR_status), _d, dlc_); + } + } + } else { + if ((_id >= 0x50FU) && (_id < 0x58EU)) { + if (_id == 0x50FU) { + recid = Unpack_SDM_Cmd_candb(&(_m->SDM_Cmd), _d, dlc_); + } else if (_id == 0x51AU) { + recid = Unpack_VEH_VIN_candb(&(_m->VEH_VIN), _d, dlc_); + } + } else { + if (_id == 0x58EU) { + recid = Unpack_FIU_Msg1_candb(&(_m->FIU_Msg1), _d, dlc_); + } else if (_id == 0x594U) { + recid = Unpack_FIU_Msg3_candb(&(_m->FIU_Msg3), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x5A6U) && (_id < 0x71DU)) { + if ((_id >= 0x5A6U) && (_id < 0x5A8U)) { + if (_id == 0x5A6U) { + recid = Unpack_BCM_StyleCmd2_candb(&(_m->BCM_StyleCmd2), _d, dlc_); + } else if (_id == 0x5A7U) { + recid = Unpack_BCM_StyleCmd3_candb(&(_m->BCM_StyleCmd3), _d, dlc_); + } + } else { + if (_id == 0x5A8U) { + recid = Unpack_BCM_WHF_Request_candb(&(_m->BCM_WHF_Request), _d, dlc_); + } else if (_id == 0x5ACU) { + recid = Unpack_BCM_UserConfig_Stat_candb(&(_m->BCM_UserConfig_Stat), _d, dlc_); + } + } + } else { + if ((_id >= 0x71DU) && (_id < 0x7DFU)) { + if (_id == 0x71DU) { + recid = Unpack_Diag_To_FRDSilCU_candb(&(_m->Diag_To_FRDSilCU), _d, dlc_); + } else if (_id == 0x7A5U) { + recid = Unpack_Diag_To_DMFR_candb(&(_m->Diag_To_DMFR), _d, dlc_); + } + } else { + if (_id == 0x7DFU) { + recid = Unpack_Diag_Functional_candb(&(_m->Diag_Functional), _d, dlc_); + } else if (_id == 0x7F1U) { + recid = Unpack_Diag_To_WHFR_candb(&(_m->Diag_To_WHFR), _d, dlc_); + } + } + } + } + } + + return recid; +} + diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/dmfr_candb-binutil.h b/MODULES/HVAC_M7_CAN_MATRIX/butl/dmfr_candb-binutil.h new file mode 100644 index 0000000..ce0bf4f --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/dmfr_candb-binutil.h @@ -0,0 +1,72 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dbccodeconf.h" + +#include "candb.h" + +typedef struct +{ + TCU_R932_1_t TCU_R932_1; + ESC_04_t ESC_04; + BCM_EEM_t BCM_EEM; + DAS_01_t DAS_01; + DAS_04_t DAS_04; + DAS_02_t DAS_02; + DAS_07_t DAS_07; + ACU_01_t ACU_01; + BCM_ExteriorLightState_t BCM_ExteriorLightState; + BCM_StyleCmd1_t BCM_StyleCmd1; + DMFL_Msg1_t DMFL_Msg1; + BCM_VEH_STATE_t BCM_VEH_STATE; + BCM_Veh_State2_t BCM_Veh_State2; + BCM_Lock_CTR_t BCM_Lock_CTR; + BCM_CLIMATIC_DATA_t BCM_CLIMATIC_DATA; + DMFL_SMFL_REQ_CTR_SEATS_t DMFL_SMFL_REQ_CTR_SEATS; + CCU_Msg1_t CCU_Msg1; + Sroof_State_t Sroof_State; + FIU_Profile_t FIU_Profile; + SMFR_status_t SMFR_status; + SDM_Cmd_t SDM_Cmd; + VEH_VIN_t VEH_VIN; + FIU_Msg1_t FIU_Msg1; + FIU_Msg3_t FIU_Msg3; + BCM_StyleCmd2_t BCM_StyleCmd2; + BCM_StyleCmd3_t BCM_StyleCmd3; + BCM_WHF_Request_t BCM_WHF_Request; + BCM_UserConfig_Stat_t BCM_UserConfig_Stat; + Diag_To_FRDSilCU_t Diag_To_FRDSilCU; + Diag_To_DMFR_t Diag_To_DMFR; + Diag_Functional_t Diag_Functional; + Diag_To_WHFR_t Diag_To_WHFR; +} dmfr_candb_rx_t; + +typedef struct +{ + DMFR_Msg1_t DMFR_Msg1; + DMFR_SMFR_REQ_CTR_SEATS_t DMFR_SMFR_REQ_CTR_SEATS; + WHFR_Msg1_t WHFR_Msg1; + FRDSilCU_State_t FRDSilCU_State; + Diag_From_FRDSilCU_t Diag_From_FRDSilCU; + Diag_From_DMFR_t Diag_From_DMFR; + Diag_From_WHFR_t Diag_From_WHFR; +} dmfr_candb_tx_t; + +uint32_t dmfr_candb_Receive(dmfr_candb_rx_t* m, const uint8_t* d, uint32_t msgid, uint8_t dlc); + +#ifdef __DEF_DMFR_CANDB__ + +extern dmfr_candb_rx_t dmfr_candb_rx; + +extern dmfr_candb_tx_t dmfr_candb_tx; + +#endif // __DEF_DMFR_CANDB__ + +#ifdef __cplusplus +} +#endif diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/dmrl_candb-binutil.c b/MODULES/HVAC_M7_CAN_MATRIX/butl/dmrl_candb-binutil.c new file mode 100644 index 0000000..343016f --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/dmrl_candb-binutil.c @@ -0,0 +1,129 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#include "dmrl_candb-binutil.h" + +// DBC file version +#if (VER_CANDB_MAJ != (0U)) || (VER_CANDB_MIN != (0U)) +#error The DMRL_CANDB binutil source file has inconsistency with core dbc lib! +#endif + +#ifdef __DEF_DMRL_CANDB__ + +dmrl_candb_rx_t dmrl_candb_rx; + +dmrl_candb_tx_t dmrl_candb_tx; + +#endif // __DEF_DMRL_CANDB__ + +uint32_t dmrl_candb_Receive(dmrl_candb_rx_t* _m, const uint8_t* _d, uint32_t _id, uint8_t dlc_) +{ + uint32_t recid = 0; + if ((_id >= 0x100U) && (_id < 0x365U)) { + if ((_id >= 0x100U) && (_id < 0x210U)) { + if ((_id >= 0x100U) && (_id < 0x162U)) { + if (_id == 0x100U) { + recid = Unpack_ESC_04_candb(&(_m->ESC_04), _d, dlc_); + } else { + if (_id == 0x157U) { + recid = Unpack_BCM_EEM_candb(&(_m->BCM_EEM), _d, dlc_); + } else if (_id == 0x160U) { + recid = Unpack_DAS_01_candb(&(_m->DAS_01), _d, dlc_); + } + } + } else { + if (_id == 0x162U) { + recid = Unpack_DAS_04_candb(&(_m->DAS_04), _d, dlc_); + } else { + if (_id == 0x20AU) { + recid = Unpack_DAS_02_candb(&(_m->DAS_02), _d, dlc_); + } else if (_id == 0x20BU) { + recid = Unpack_DAS_07_candb(&(_m->DAS_07), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x210U) && (_id < 0x246U)) { + if (_id == 0x210U) { + recid = Unpack_ACU_01_candb(&(_m->ACU_01), _d, dlc_); + } else { + if (_id == 0x23AU) { + recid = Unpack_BCM_StyleCmd1_candb(&(_m->BCM_StyleCmd1), _d, dlc_); + } else if (_id == 0x244U) { + recid = Unpack_DMFL_Msg1_candb(&(_m->DMFL_Msg1), _d, dlc_); + } + } + } else { + if ((_id >= 0x246U) && (_id < 0x280U)) { + if (_id == 0x246U) { + recid = Unpack_DMRR_Msg1_candb(&(_m->DMRR_Msg1), _d, dlc_); + } else if (_id == 0x247U) { + recid = Unpack_TM_Stat_candb(&(_m->TM_Stat), _d, dlc_); + } + } else { + if (_id == 0x280U) { + recid = Unpack_BCM_VEH_STATE_candb(&(_m->BCM_VEH_STATE), _d, dlc_); + } else if (_id == 0x2F0U) { + recid = Unpack_BCM_Lock_CTR_candb(&(_m->BCM_Lock_CTR), _d, dlc_); + } + } + } + } + } else { + if ((_id >= 0x365U) && (_id < 0x594U)) { + if ((_id >= 0x365U) && (_id < 0x4D1U)) { + if (_id == 0x365U) { + recid = Unpack_BCM_CLIMATIC_DATA_candb(&(_m->BCM_CLIMATIC_DATA), _d, dlc_); + } else { + if (_id == 0x380U) { + recid = Unpack_CCU_Msg1_candb(&(_m->CCU_Msg1), _d, dlc_); + } else if (_id == 0x38AU) { + recid = Unpack_Sroof_State_candb(&(_m->Sroof_State), _d, dlc_); + } + } + } else { + if ((_id >= 0x4D1U) && (_id < 0x50FU)) { + if (_id == 0x4D1U) { + recid = Unpack_SMFR_status_candb(&(_m->SMFR_status), _d, dlc_); + } else if (_id == 0x4D2U) { + recid = Unpack_SMRL_status_candb(&(_m->SMRL_status), _d, dlc_); + } + } else { + if (_id == 0x50FU) { + recid = Unpack_SDM_Cmd_candb(&(_m->SDM_Cmd), _d, dlc_); + } else if (_id == 0x51AU) { + recid = Unpack_VEH_VIN_candb(&(_m->VEH_VIN), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x594U) && (_id < 0x5ACU)) { + if (_id == 0x594U) { + recid = Unpack_FIU_Msg3_candb(&(_m->FIU_Msg3), _d, dlc_); + } else { + if (_id == 0x5A6U) { + recid = Unpack_BCM_StyleCmd2_candb(&(_m->BCM_StyleCmd2), _d, dlc_); + } else if (_id == 0x5A7U) { + recid = Unpack_BCM_StyleCmd3_candb(&(_m->BCM_StyleCmd3), _d, dlc_); + } + } + } else { + if ((_id >= 0x5ACU) && (_id < 0x7C8U)) { + if (_id == 0x5ACU) { + recid = Unpack_BCM_UserConfig_Stat_candb(&(_m->BCM_UserConfig_Stat), _d, dlc_); + } else if (_id == 0x7A6U) { + recid = Unpack_Diag_To_DMRL_candb(&(_m->Diag_To_DMRL), _d, dlc_); + } + } else { + if (_id == 0x7C8U) { + recid = Unpack_Diag_To_RLDSilCU_candb(&(_m->Diag_To_RLDSilCU), _d, dlc_); + } else if (_id == 0x7DFU) { + recid = Unpack_Diag_Functional_candb(&(_m->Diag_Functional), _d, dlc_); + } + } + } + } + } + + return recid; +} + diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/dmrl_candb-binutil.h b/MODULES/HVAC_M7_CAN_MATRIX/butl/dmrl_candb-binutil.h new file mode 100644 index 0000000..c6fa09d --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/dmrl_candb-binutil.h @@ -0,0 +1,65 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dbccodeconf.h" + +#include "candb.h" + +typedef struct +{ + ESC_04_t ESC_04; + BCM_EEM_t BCM_EEM; + DAS_01_t DAS_01; + DAS_04_t DAS_04; + DAS_02_t DAS_02; + DAS_07_t DAS_07; + ACU_01_t ACU_01; + BCM_StyleCmd1_t BCM_StyleCmd1; + DMFL_Msg1_t DMFL_Msg1; + DMRR_Msg1_t DMRR_Msg1; + TM_Stat_t TM_Stat; + BCM_VEH_STATE_t BCM_VEH_STATE; + BCM_Lock_CTR_t BCM_Lock_CTR; + BCM_CLIMATIC_DATA_t BCM_CLIMATIC_DATA; + CCU_Msg1_t CCU_Msg1; + Sroof_State_t Sroof_State; + SMFR_status_t SMFR_status; + SMRL_status_t SMRL_status; + SDM_Cmd_t SDM_Cmd; + VEH_VIN_t VEH_VIN; + FIU_Msg3_t FIU_Msg3; + BCM_StyleCmd2_t BCM_StyleCmd2; + BCM_StyleCmd3_t BCM_StyleCmd3; + BCM_UserConfig_Stat_t BCM_UserConfig_Stat; + Diag_To_DMRL_t Diag_To_DMRL; + Diag_To_RLDSilCU_t Diag_To_RLDSilCU; + Diag_Functional_t Diag_Functional; +} dmrl_candb_rx_t; + +typedef struct +{ + DMRL_Msg1_t DMRL_Msg1; + DMRL_SMRL_REQ_CTR_SEATS_t DMRL_SMRL_REQ_CTR_SEATS; + RLDSilCU_State_t RLDSilCU_State; + Diag_From_DMRL_t Diag_From_DMRL; + Diag_From_RLDSilCU_t Diag_From_RLDSilCU; +} dmrl_candb_tx_t; + +uint32_t dmrl_candb_Receive(dmrl_candb_rx_t* m, const uint8_t* d, uint32_t msgid, uint8_t dlc); + +#ifdef __DEF_DMRL_CANDB__ + +extern dmrl_candb_rx_t dmrl_candb_rx; + +extern dmrl_candb_tx_t dmrl_candb_tx; + +#endif // __DEF_DMRL_CANDB__ + +#ifdef __cplusplus +} +#endif diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/dmrr_candb-binutil.c b/MODULES/HVAC_M7_CAN_MATRIX/butl/dmrr_candb-binutil.c new file mode 100644 index 0000000..ede32ce --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/dmrr_candb-binutil.c @@ -0,0 +1,133 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#include "dmrr_candb-binutil.h" + +// DBC file version +#if (VER_CANDB_MAJ != (0U)) || (VER_CANDB_MIN != (0U)) +#error The DMRR_CANDB binutil source file has inconsistency with core dbc lib! +#endif + +#ifdef __DEF_DMRR_CANDB__ + +dmrr_candb_rx_t dmrr_candb_rx; + +dmrr_candb_tx_t dmrr_candb_tx; + +#endif // __DEF_DMRR_CANDB__ + +uint32_t dmrr_candb_Receive(dmrr_candb_rx_t* _m, const uint8_t* _d, uint32_t _id, uint8_t dlc_) +{ + uint32_t recid = 0; + if ((_id >= 0x100U) && (_id < 0x367U)) { + if ((_id >= 0x100U) && (_id < 0x23AU)) { + if ((_id >= 0x100U) && (_id < 0x162U)) { + if (_id == 0x100U) { + recid = Unpack_ESC_04_candb(&(_m->ESC_04), _d, dlc_); + } else { + if (_id == 0x157U) { + recid = Unpack_BCM_EEM_candb(&(_m->BCM_EEM), _d, dlc_); + } else if (_id == 0x160U) { + recid = Unpack_DAS_01_candb(&(_m->DAS_01), _d, dlc_); + } + } + } else { + if ((_id >= 0x162U) && (_id < 0x20BU)) { + if (_id == 0x162U) { + recid = Unpack_DAS_04_candb(&(_m->DAS_04), _d, dlc_); + } else if (_id == 0x20AU) { + recid = Unpack_DAS_02_candb(&(_m->DAS_02), _d, dlc_); + } + } else { + if (_id == 0x20BU) { + recid = Unpack_DAS_07_candb(&(_m->DAS_07), _d, dlc_); + } else if (_id == 0x210U) { + recid = Unpack_ACU_01_candb(&(_m->ACU_01), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x23AU) && (_id < 0x247U)) { + if (_id == 0x23AU) { + recid = Unpack_BCM_StyleCmd1_candb(&(_m->BCM_StyleCmd1), _d, dlc_); + } else { + if (_id == 0x244U) { + recid = Unpack_DMFL_Msg1_candb(&(_m->DMFL_Msg1), _d, dlc_); + } else if (_id == 0x245U) { + recid = Unpack_DMRL_Msg1_candb(&(_m->DMRL_Msg1), _d, dlc_); + } + } + } else { + if ((_id >= 0x247U) && (_id < 0x2F0U)) { + if (_id == 0x247U) { + recid = Unpack_TM_Stat_candb(&(_m->TM_Stat), _d, dlc_); + } else if (_id == 0x280U) { + recid = Unpack_BCM_VEH_STATE_candb(&(_m->BCM_VEH_STATE), _d, dlc_); + } + } else { + if (_id == 0x2F0U) { + recid = Unpack_BCM_Lock_CTR_candb(&(_m->BCM_Lock_CTR), _d, dlc_); + } else if (_id == 0x365U) { + recid = Unpack_BCM_CLIMATIC_DATA_candb(&(_m->BCM_CLIMATIC_DATA), _d, dlc_); + } + } + } + } + } else { + if ((_id >= 0x367U) && (_id < 0x594U)) { + if ((_id >= 0x367U) && (_id < 0x4D1U)) { + if (_id == 0x367U) { + recid = Unpack_DMFL_SMFL_REQ_CTR_SEATS_candb(&(_m->DMFL_SMFL_REQ_CTR_SEATS), _d, dlc_); + } else { + if (_id == 0x380U) { + recid = Unpack_CCU_Msg1_candb(&(_m->CCU_Msg1), _d, dlc_); + } else if (_id == 0x38AU) { + recid = Unpack_Sroof_State_candb(&(_m->Sroof_State), _d, dlc_); + } + } + } else { + if ((_id >= 0x4D1U) && (_id < 0x50FU)) { + if (_id == 0x4D1U) { + recid = Unpack_SMFR_status_candb(&(_m->SMFR_status), _d, dlc_); + } else if (_id == 0x4D3U) { + recid = Unpack_SMRR_status_candb(&(_m->SMRR_status), _d, dlc_); + } + } else { + if (_id == 0x50FU) { + recid = Unpack_SDM_Cmd_candb(&(_m->SDM_Cmd), _d, dlc_); + } else if (_id == 0x51AU) { + recid = Unpack_VEH_VIN_candb(&(_m->VEH_VIN), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x594U) && (_id < 0x5ACU)) { + if (_id == 0x594U) { + recid = Unpack_FIU_Msg3_candb(&(_m->FIU_Msg3), _d, dlc_); + } else { + if (_id == 0x5A6U) { + recid = Unpack_BCM_StyleCmd2_candb(&(_m->BCM_StyleCmd2), _d, dlc_); + } else if (_id == 0x5A7U) { + recid = Unpack_BCM_StyleCmd3_candb(&(_m->BCM_StyleCmd3), _d, dlc_); + } + } + } else { + if ((_id >= 0x5ACU) && (_id < 0x7C9U)) { + if (_id == 0x5ACU) { + recid = Unpack_BCM_UserConfig_Stat_candb(&(_m->BCM_UserConfig_Stat), _d, dlc_); + } else if (_id == 0x7A7U) { + recid = Unpack_Diag_To_DMRR_candb(&(_m->Diag_To_DMRR), _d, dlc_); + } + } else { + if (_id == 0x7C9U) { + recid = Unpack_Diag_To_RRDSilCU_candb(&(_m->Diag_To_RRDSilCU), _d, dlc_); + } else if (_id == 0x7DFU) { + recid = Unpack_Diag_Functional_candb(&(_m->Diag_Functional), _d, dlc_); + } + } + } + } + } + + return recid; +} + diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/dmrr_candb-binutil.h b/MODULES/HVAC_M7_CAN_MATRIX/butl/dmrr_candb-binutil.h new file mode 100644 index 0000000..09ee084 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/dmrr_candb-binutil.h @@ -0,0 +1,66 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dbccodeconf.h" + +#include "candb.h" + +typedef struct +{ + ESC_04_t ESC_04; + BCM_EEM_t BCM_EEM; + DAS_01_t DAS_01; + DAS_04_t DAS_04; + DAS_02_t DAS_02; + DAS_07_t DAS_07; + ACU_01_t ACU_01; + BCM_StyleCmd1_t BCM_StyleCmd1; + DMFL_Msg1_t DMFL_Msg1; + DMRL_Msg1_t DMRL_Msg1; + TM_Stat_t TM_Stat; + BCM_VEH_STATE_t BCM_VEH_STATE; + BCM_Lock_CTR_t BCM_Lock_CTR; + BCM_CLIMATIC_DATA_t BCM_CLIMATIC_DATA; + DMFL_SMFL_REQ_CTR_SEATS_t DMFL_SMFL_REQ_CTR_SEATS; + CCU_Msg1_t CCU_Msg1; + Sroof_State_t Sroof_State; + SMFR_status_t SMFR_status; + SMRR_status_t SMRR_status; + SDM_Cmd_t SDM_Cmd; + VEH_VIN_t VEH_VIN; + FIU_Msg3_t FIU_Msg3; + BCM_StyleCmd2_t BCM_StyleCmd2; + BCM_StyleCmd3_t BCM_StyleCmd3; + BCM_UserConfig_Stat_t BCM_UserConfig_Stat; + Diag_To_DMRR_t Diag_To_DMRR; + Diag_To_RRDSilCU_t Diag_To_RRDSilCU; + Diag_Functional_t Diag_Functional; +} dmrr_candb_rx_t; + +typedef struct +{ + DMRR_Msg1_t DMRR_Msg1; + DMRR_SMRR_REQ_CTR_SEATS_t DMRR_SMRR_REQ_CTR_SEATS; + RRDSilCU_State_t RRDSilCU_State; + Diag_From_DMRR_t Diag_From_DMRR; + Diag_From_RRDSilCU_t Diag_From_RRDSilCU; +} dmrr_candb_tx_t; + +uint32_t dmrr_candb_Receive(dmrr_candb_rx_t* m, const uint8_t* d, uint32_t msgid, uint8_t dlc); + +#ifdef __DEF_DMRR_CANDB__ + +extern dmrr_candb_rx_t dmrr_candb_rx; + +extern dmrr_candb_tx_t dmrr_candb_tx; + +#endif // __DEF_DMRR_CANDB__ + +#ifdef __cplusplus +} +#endif diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/ethsw_candb-binutil.c b/MODULES/HVAC_M7_CAN_MATRIX/butl/ethsw_candb-binutil.c new file mode 100644 index 0000000..73993a0 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/ethsw_candb-binutil.c @@ -0,0 +1,47 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#include "ethsw_candb-binutil.h" + +// DBC file version +#if (VER_CANDB_MAJ != (0U)) || (VER_CANDB_MIN != (0U)) +#error The ETHSW_CANDB binutil source file has inconsistency with core dbc lib! +#endif + +#ifdef __DEF_ETHSW_CANDB__ + +ethsw_candb_rx_t ethsw_candb_rx; + +#endif // __DEF_ETHSW_CANDB__ + +uint32_t ethsw_candb_Receive(ethsw_candb_rx_t* _m, const uint8_t* _d, uint32_t _id, uint8_t dlc_) +{ + uint32_t recid = 0; + if ((_id >= 0x280U) && (_id < 0x314U)) { + if (_id == 0x280U) { + recid = Unpack_BCM_VEH_STATE_candb(&(_m->BCM_VEH_STATE), _d, dlc_); + } else { + if (_id == 0x282U) { + recid = Unpack_BCM_Veh_State2_candb(&(_m->BCM_Veh_State2), _d, dlc_); + } else if (_id == 0x312U) { + recid = Unpack_CCU_Stat2_candb(&(_m->CCU_Stat2), _d, dlc_); + } + } + } else { + if ((_id >= 0x314U) && (_id < 0x589U)) { + if (_id == 0x314U) { + recid = Unpack_CCU_Stat3_candb(&(_m->CCU_Stat3), _d, dlc_); + } else if (_id == 0x51AU) { + recid = Unpack_VEH_VIN_candb(&(_m->VEH_VIN), _d, dlc_); + } + } else { + if (_id == 0x589U) { + recid = Unpack_DW_STATE_candb(&(_m->DW_STATE), _d, dlc_); + } else if (_id == 0x7DFU) { + recid = Unpack_Diag_Functional_candb(&(_m->Diag_Functional), _d, dlc_); + } + } + } + + return recid; +} + diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/ethsw_candb-binutil.h b/MODULES/HVAC_M7_CAN_MATRIX/butl/ethsw_candb-binutil.h new file mode 100644 index 0000000..22255f6 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/ethsw_candb-binutil.h @@ -0,0 +1,36 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dbccodeconf.h" + +#include "candb.h" + +typedef struct +{ + BCM_VEH_STATE_t BCM_VEH_STATE; + BCM_Veh_State2_t BCM_Veh_State2; + CCU_Stat2_t CCU_Stat2; + CCU_Stat3_t CCU_Stat3; + VEH_VIN_t VEH_VIN; + DW_STATE_t DW_STATE; + Diag_Functional_t Diag_Functional; +} ethsw_candb_rx_t; + +// There is no any TX mapped massage. + +uint32_t ethsw_candb_Receive(ethsw_candb_rx_t* m, const uint8_t* d, uint32_t msgid, uint8_t dlc); + +#ifdef __DEF_ETHSW_CANDB__ + +extern ethsw_candb_rx_t ethsw_candb_rx; + +#endif // __DEF_ETHSW_CANDB__ + +#ifdef __cplusplus +} +#endif diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/ftcu_candb-binutil.c b/MODULES/HVAC_M7_CAN_MATRIX/butl/ftcu_candb-binutil.c new file mode 100644 index 0000000..563fc7f --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/ftcu_candb-binutil.c @@ -0,0 +1,49 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#include "ftcu_candb-binutil.h" + +// DBC file version +#if (VER_CANDB_MAJ != (0U)) || (VER_CANDB_MIN != (0U)) +#error The FTCU_CANDB binutil source file has inconsistency with core dbc lib! +#endif + +#ifdef __DEF_FTCU_CANDB__ + +ftcu_candb_rx_t ftcu_candb_rx; + +ftcu_candb_tx_t ftcu_candb_tx; + +#endif // __DEF_FTCU_CANDB__ + +uint32_t ftcu_candb_Receive(ftcu_candb_rx_t* _m, const uint8_t* _d, uint32_t _id, uint8_t dlc_) +{ + uint32_t recid = 0; + if ((_id >= 0x150U) && (_id < 0x280U)) { + if (_id == 0x150U) { + recid = Unpack_EMS_Veh_candb(&(_m->EMS_Veh), _d, dlc_); + } else { + if (_id == 0x152U) { + recid = Unpack_BCM_Powertrain_candb(&(_m->BCM_Powertrain), _d, dlc_); + } else if (_id == 0x210U) { + recid = Unpack_ACU_01_candb(&(_m->ACU_01), _d, dlc_); + } + } + } else { + if ((_id >= 0x280U) && (_id < 0x73AU)) { + if (_id == 0x280U) { + recid = Unpack_BCM_VEH_STATE_candb(&(_m->BCM_VEH_STATE), _d, dlc_); + } else if (_id == 0x51AU) { + recid = Unpack_VEH_VIN_candb(&(_m->VEH_VIN), _d, dlc_); + } + } else { + if (_id == 0x73AU) { + recid = Unpack_Diag_To_FTCU_candb(&(_m->Diag_To_FTCU), _d, dlc_); + } else if (_id == 0x7DFU) { + recid = Unpack_Diag_Functional_candb(&(_m->Diag_Functional), _d, dlc_); + } + } + } + + return recid; +} + diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/ftcu_candb-binutil.h b/MODULES/HVAC_M7_CAN_MATRIX/butl/ftcu_candb-binutil.h new file mode 100644 index 0000000..2a71d63 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/ftcu_candb-binutil.h @@ -0,0 +1,44 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dbccodeconf.h" + +#include "candb.h" + +typedef struct +{ + EMS_Veh_t EMS_Veh; + BCM_Powertrain_t BCM_Powertrain; + ACU_01_t ACU_01; + BCM_VEH_STATE_t BCM_VEH_STATE; + VEH_VIN_t VEH_VIN; + Diag_To_FTCU_t Diag_To_FTCU; + Diag_Functional_t Diag_Functional; +} ftcu_candb_rx_t; + +typedef struct +{ + FTCU_DAT1_t FTCU_DAT1; + FTCU_DAT2_t FTCU_DAT2; + FTCU_DAT3_t FTCU_DAT3; + Diag_From_FTCU_t Diag_From_FTCU; +} ftcu_candb_tx_t; + +uint32_t ftcu_candb_Receive(ftcu_candb_rx_t* m, const uint8_t* d, uint32_t msgid, uint8_t dlc); + +#ifdef __DEF_FTCU_CANDB__ + +extern ftcu_candb_rx_t ftcu_candb_rx; + +extern ftcu_candb_tx_t ftcu_candb_tx; + +#endif // __DEF_FTCU_CANDB__ + +#ifdef __cplusplus +} +#endif diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/ic_candb-binutil.c b/MODULES/HVAC_M7_CAN_MATRIX/butl/ic_candb-binutil.c new file mode 100644 index 0000000..a505a81 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/ic_candb-binutil.c @@ -0,0 +1,169 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#include "ic_candb-binutil.h" + +// DBC file version +#if (VER_CANDB_MAJ != (0U)) || (VER_CANDB_MIN != (0U)) +#error The IC_CANDB binutil source file has inconsistency with core dbc lib! +#endif + +#ifdef __DEF_IC_CANDB__ + +ic_candb_rx_t ic_candb_rx; + +ic_candb_tx_t ic_candb_tx; + +#endif // __DEF_IC_CANDB__ + +uint32_t ic_candb_Receive(ic_candb_rx_t* _m, const uint8_t* _d, uint32_t _id, uint8_t dlc_) +{ + uint32_t recid = 0; + if ((_id >= 0x8FU) && (_id < 0x282U)) { + if ((_id >= 0x8FU) && (_id < 0x243U)) { + if ((_id >= 0x8FU) && (_id < 0x152U)) { + if ((_id >= 0x8FU) && (_id < 0xE4U)) { + if (_id == 0x8FU) { + recid = Unpack_VAU_TCU_Hash_Resp_candb(&(_m->VAU_TCU_Hash_Resp), _d, dlc_); + } else if (_id == 0x91U) { + recid = Unpack_VAU_EMS_VCU_Hash_Resp_candb(&(_m->VAU_EMS_VCU_Hash_Resp), _d, dlc_); + } + } else { + if (_id == 0xE4U) { + recid = Unpack_FTCU_DAT2_candb(&(_m->FTCU_DAT2), _d, dlc_); + } else if (_id == 0x121U) { + recid = Unpack_VAU2_Msg1_candb(&(_m->VAU2_Msg1), _d, dlc_); + } + } + } else { + if ((_id >= 0x152U) && (_id < 0x157U)) { + if (_id == 0x152U) { + recid = Unpack_BCM_Powertrain_candb(&(_m->BCM_Powertrain), _d, dlc_); + } else if (_id == 0x153U) { + recid = Unpack_EMS_Veh_02_candb(&(_m->EMS_Veh_02), _d, dlc_); + } + } else { + if (_id == 0x157U) { + recid = Unpack_BCM_EEM_candb(&(_m->BCM_EEM), _d, dlc_); + } else { + if (_id == 0x20BU) { + recid = Unpack_DAS_07_candb(&(_m->DAS_07), _d, dlc_); + } else if (_id == 0x231U) { + recid = Unpack_BCM_ExteriorLightState_candb(&(_m->BCM_ExteriorLightState), _d, dlc_); + } + } + } + } + } else { + if ((_id >= 0x243U) && (_id < 0x247U)) { + if ((_id >= 0x243U) && (_id < 0x245U)) { + if (_id == 0x243U) { + recid = Unpack_DMFR_Msg1_candb(&(_m->DMFR_Msg1), _d, dlc_); + } else if (_id == 0x244U) { + recid = Unpack_DMFL_Msg1_candb(&(_m->DMFL_Msg1), _d, dlc_); + } + } else { + if (_id == 0x245U) { + recid = Unpack_DMRL_Msg1_candb(&(_m->DMRL_Msg1), _d, dlc_); + } else if (_id == 0x246U) { + recid = Unpack_DMRR_Msg1_candb(&(_m->DMRR_Msg1), _d, dlc_); + } + } + } else { + if ((_id >= 0x247U) && (_id < 0x251U)) { + if (_id == 0x247U) { + recid = Unpack_TM_Stat_candb(&(_m->TM_Stat), _d, dlc_); + } else if (_id == 0x24FU) { + recid = Unpack_VAU2_Msg2_candb(&(_m->VAU2_Msg2), _d, dlc_); + } + } else { + if (_id == 0x251U) { + recid = Unpack_BCM_DMS_01_candb(&(_m->BCM_DMS_01), _d, dlc_); + } else { + if (_id == 0x277U) { + recid = Unpack_ATS_Status_candb(&(_m->ATS_Status), _d, dlc_); + } else if (_id == 0x280U) { + recid = Unpack_BCM_VEH_STATE_candb(&(_m->BCM_VEH_STATE), _d, dlc_); + } + } + } + } + } + } else { + if ((_id >= 0x282U) && (_id < 0x4F0U)) { + if ((_id >= 0x282U) && (_id < 0x365U)) { + if ((_id >= 0x282U) && (_id < 0x305U)) { + if (_id == 0x282U) { + recid = Unpack_BCM_Veh_State2_candb(&(_m->BCM_Veh_State2), _d, dlc_); + } else if (_id == 0x2F0U) { + recid = Unpack_BCM_Lock_CTR_candb(&(_m->BCM_Lock_CTR), _d, dlc_); + } + } else { + if (_id == 0x305U) { + recid = Unpack_HVC_Err_Status_Msg_candb(&(_m->HVC_Err_Status_Msg), _d, dlc_); + } else if (_id == 0x362U) { + recid = Unpack_BCM_IC_Info_Msg_candb(&(_m->BCM_IC_Info_Msg), _d, dlc_); + } + } + } else { + if ((_id >= 0x365U) && (_id < 0x3CBU)) { + if (_id == 0x365U) { + recid = Unpack_BCM_CLIMATIC_DATA_candb(&(_m->BCM_CLIMATIC_DATA), _d, dlc_); + } else if (_id == 0x38AU) { + recid = Unpack_Sroof_State_candb(&(_m->Sroof_State), _d, dlc_); + } + } else { + if (_id == 0x3CBU) { + recid = Unpack_WChF_Status_candb(&(_m->WChF_Status), _d, dlc_); + } else { + if (_id == 0x423U) { + recid = Unpack_EPB_VM_MSG_candb(&(_m->EPB_VM_MSG), _d, dlc_); + } else if (_id == 0x4AFU) { + recid = Unpack_DCDC1248_01_candb(&(_m->DCDC1248_01), _d, dlc_); + } + } + } + } + } else { + if ((_id >= 0x4F0U) && (_id < 0x522U)) { + if ((_id >= 0x4F0U) && (_id < 0x51AU)) { + if (_id == 0x4F0U) { + recid = Unpack_VAU_TPMS_Msg_candb(&(_m->VAU_TPMS_Msg), _d, dlc_); + } else if (_id == 0x4FEU) { + recid = Unpack_CCU_Errors_candb(&(_m->CCU_Errors), _d, dlc_); + } + } else { + if (_id == 0x51AU) { + recid = Unpack_VEH_VIN_candb(&(_m->VEH_VIN), _d, dlc_); + } else { + if (_id == 0x51EU) { + recid = Unpack_BCM_RunningBoards_candb(&(_m->BCM_RunningBoards), _d, dlc_); + } else if (_id == 0x521U) { + recid = Unpack_OCUFL_MSG_candb(&(_m->OCUFL_MSG), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x522U) && (_id < 0x524U)) { + if (_id == 0x522U) { + recid = Unpack_OCUFR_MSG_candb(&(_m->OCUFR_MSG), _d, dlc_); + } else if (_id == 0x523U) { + recid = Unpack_OCURL_MSG_candb(&(_m->OCURL_MSG), _d, dlc_); + } + } else { + if (_id == 0x524U) { + recid = Unpack_OCURR_MSG_candb(&(_m->OCURR_MSG), _d, dlc_); + } else { + if (_id == 0x525U) { + recid = Unpack_RBCU_BODY_Stat_candb(&(_m->RBCU_BODY_Stat), _d, dlc_); + } else if (_id == 0x622U) { + recid = Unpack_VAU_BLE_Device_candb(&(_m->VAU_BLE_Device), _d, dlc_); + } + } + } + } + } + } + + return recid; +} + diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/ic_candb-binutil.h b/MODULES/HVAC_M7_CAN_MATRIX/butl/ic_candb-binutil.h new file mode 100644 index 0000000..46e22e9 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/ic_candb-binutil.h @@ -0,0 +1,74 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dbccodeconf.h" + +#include "candb.h" + +typedef struct +{ + VAU_TCU_Hash_Resp_t VAU_TCU_Hash_Resp; + VAU_EMS_VCU_Hash_Resp_t VAU_EMS_VCU_Hash_Resp; + FTCU_DAT2_t FTCU_DAT2; + VAU2_Msg1_t VAU2_Msg1; + BCM_Powertrain_t BCM_Powertrain; + EMS_Veh_02_t EMS_Veh_02; + BCM_EEM_t BCM_EEM; + DAS_07_t DAS_07; + BCM_ExteriorLightState_t BCM_ExteriorLightState; + DMFR_Msg1_t DMFR_Msg1; + DMFL_Msg1_t DMFL_Msg1; + DMRL_Msg1_t DMRL_Msg1; + DMRR_Msg1_t DMRR_Msg1; + TM_Stat_t TM_Stat; + VAU2_Msg2_t VAU2_Msg2; + BCM_DMS_01_t BCM_DMS_01; + ATS_Status_t ATS_Status; + BCM_VEH_STATE_t BCM_VEH_STATE; + BCM_Veh_State2_t BCM_Veh_State2; + BCM_Lock_CTR_t BCM_Lock_CTR; + HVC_Err_Status_Msg_t HVC_Err_Status_Msg; + BCM_IC_Info_Msg_t BCM_IC_Info_Msg; + BCM_CLIMATIC_DATA_t BCM_CLIMATIC_DATA; + Sroof_State_t Sroof_State; + WChF_Status_t WChF_Status; + EPB_VM_MSG_t EPB_VM_MSG; + DCDC1248_01_t DCDC1248_01; + VAU_TPMS_Msg_t VAU_TPMS_Msg; + CCU_Errors_t CCU_Errors; + VEH_VIN_t VEH_VIN; + BCM_RunningBoards_t BCM_RunningBoards; + OCUFL_MSG_t OCUFL_MSG; + OCUFR_MSG_t OCUFR_MSG; + OCURL_MSG_t OCURL_MSG; + OCURR_MSG_t OCURR_MSG; + RBCU_BODY_Stat_t RBCU_BODY_Stat; + VAU_BLE_Device_t VAU_BLE_Device; +} ic_candb_rx_t; + +typedef struct +{ + FIU_Profile_t FIU_Profile; + IC_SDM_Info_t IC_SDM_Info; + IC_SDM_Info_02_t IC_SDM_Info_02; + IC_Milleage_t IC_Milleage; +} ic_candb_tx_t; + +uint32_t ic_candb_Receive(ic_candb_rx_t* m, const uint8_t* d, uint32_t msgid, uint8_t dlc); + +#ifdef __DEF_IC_CANDB__ + +extern ic_candb_rx_t ic_candb_rx; + +extern ic_candb_tx_t ic_candb_tx; + +#endif // __DEF_IC_CANDB__ + +#ifdef __cplusplus +} +#endif diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/lb_psilcu_candb-binutil.c b/MODULES/HVAC_M7_CAN_MATRIX/butl/lb_psilcu_candb-binutil.c new file mode 100644 index 0000000..07de523 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/lb_psilcu_candb-binutil.c @@ -0,0 +1,41 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#include "lb_psilcu_candb-binutil.h" + +// DBC file version +#if (VER_CANDB_MAJ != (0U)) || (VER_CANDB_MIN != (0U)) +#error The LB_PSILCU_CANDB binutil source file has inconsistency with core dbc lib! +#endif + +#ifdef __DEF_LB_PSILCU_CANDB__ + +lb_psilcu_candb_rx_t lb_psilcu_candb_rx; + +lb_psilcu_candb_tx_t lb_psilcu_candb_tx; + +#endif // __DEF_LB_PSILCU_CANDB__ + +uint32_t lb_psilcu_candb_Receive(lb_psilcu_candb_rx_t* _m, const uint8_t* _d, uint32_t _id, uint8_t dlc_) +{ + uint32_t recid = 0; + if ((_id >= 0x23AU) && (_id < 0x5A6U)) { + if (_id == 0x23AU) { + recid = Unpack_BCM_StyleCmd1_candb(&(_m->BCM_StyleCmd1), _d, dlc_); + } else if (_id == 0x51AU) { + recid = Unpack_VEH_VIN_candb(&(_m->VEH_VIN), _d, dlc_); + } + } else { + if (_id == 0x5A6U) { + recid = Unpack_BCM_StyleCmd2_candb(&(_m->BCM_StyleCmd2), _d, dlc_); + } else { + if (_id == 0x5A7U) { + recid = Unpack_BCM_StyleCmd3_candb(&(_m->BCM_StyleCmd3), _d, dlc_); + } else if (_id == 0x787U) { + recid = Unpack_Diag_To_LB_pSilCU_candb(&(_m->Diag_To_LB_pSilCU), _d, dlc_); + } + } + } + + return recid; +} + diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/lb_psilcu_candb-binutil.h b/MODULES/HVAC_M7_CAN_MATRIX/butl/lb_psilcu_candb-binutil.h new file mode 100644 index 0000000..0a1fdee --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/lb_psilcu_candb-binutil.h @@ -0,0 +1,40 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dbccodeconf.h" + +#include "candb.h" + +typedef struct +{ + BCM_StyleCmd1_t BCM_StyleCmd1; + VEH_VIN_t VEH_VIN; + BCM_StyleCmd2_t BCM_StyleCmd2; + BCM_StyleCmd3_t BCM_StyleCmd3; + Diag_To_LB_pSilCU_t Diag_To_LB_pSilCU; +} lb_psilcu_candb_rx_t; + +typedef struct +{ + LB_pSilCU_State_t LB_pSilCU_State; + Diag_From_LB_pSilCU_t Diag_From_LB_pSilCU; +} lb_psilcu_candb_tx_t; + +uint32_t lb_psilcu_candb_Receive(lb_psilcu_candb_rx_t* m, const uint8_t* d, uint32_t msgid, uint8_t dlc); + +#ifdef __DEF_LB_PSILCU_CANDB__ + +extern lb_psilcu_candb_rx_t lb_psilcu_candb_rx; + +extern lb_psilcu_candb_tx_t lb_psilcu_candb_tx; + +#endif // __DEF_LB_PSILCU_CANDB__ + +#ifdef __cplusplus +} +#endif diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/ptg_candb-binutil.c b/MODULES/HVAC_M7_CAN_MATRIX/butl/ptg_candb-binutil.c new file mode 100644 index 0000000..be6fc4e --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/ptg_candb-binutil.c @@ -0,0 +1,61 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#include "ptg_candb-binutil.h" + +// DBC file version +#if (VER_CANDB_MAJ != (0U)) || (VER_CANDB_MIN != (0U)) +#error The PTG_CANDB binutil source file has inconsistency with core dbc lib! +#endif + +#ifdef __DEF_PTG_CANDB__ + +ptg_candb_rx_t ptg_candb_rx; + +ptg_candb_tx_t ptg_candb_tx; + +#endif // __DEF_PTG_CANDB__ + +uint32_t ptg_candb_Receive(ptg_candb_rx_t* _m, const uint8_t* _d, uint32_t _id, uint8_t dlc_) +{ + uint32_t recid = 0; + if ((_id >= 0xB1U) && (_id < 0x2F0U)) { + if ((_id >= 0xB1U) && (_id < 0x247U)) { + if (_id == 0xB1U) { + recid = Unpack_TCU_R932_1_candb(&(_m->TCU_R932_1), _d, dlc_); + } else if (_id == 0x100U) { + recid = Unpack_ESC_04_candb(&(_m->ESC_04), _d, dlc_); + } + } else { + if (_id == 0x247U) { + recid = Unpack_TM_Stat_candb(&(_m->TM_Stat), _d, dlc_); + } else { + if (_id == 0x24FU) { + recid = Unpack_VAU2_Msg2_candb(&(_m->VAU2_Msg2), _d, dlc_); + } else if (_id == 0x280U) { + recid = Unpack_BCM_VEH_STATE_candb(&(_m->BCM_VEH_STATE), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x2F0U) && (_id < 0x6D1U)) { + if (_id == 0x2F0U) { + recid = Unpack_BCM_Lock_CTR_candb(&(_m->BCM_Lock_CTR), _d, dlc_); + } else if (_id == 0x51AU) { + recid = Unpack_VEH_VIN_candb(&(_m->VEH_VIN), _d, dlc_); + } + } else { + if (_id == 0x6D1U) { + recid = Unpack_SupplierTool_To_PTG_candb(&(_m->SupplierTool_To_PTG), _d, dlc_); + } else { + if (_id == 0x7DBU) { + recid = Unpack_Diag_To_PTG_candb(&(_m->Diag_To_PTG), _d, dlc_); + } else if (_id == 0x7DFU) { + recid = Unpack_Diag_Functional_candb(&(_m->Diag_Functional), _d, dlc_); + } + } + } + } + + return recid; +} + diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/ptg_candb-binutil.h b/MODULES/HVAC_M7_CAN_MATRIX/butl/ptg_candb-binutil.h new file mode 100644 index 0000000..a2a4ad2 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/ptg_candb-binutil.h @@ -0,0 +1,46 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dbccodeconf.h" + +#include "candb.h" + +typedef struct +{ + TCU_R932_1_t TCU_R932_1; + ESC_04_t ESC_04; + TM_Stat_t TM_Stat; + VAU2_Msg2_t VAU2_Msg2; + BCM_VEH_STATE_t BCM_VEH_STATE; + BCM_Lock_CTR_t BCM_Lock_CTR; + VEH_VIN_t VEH_VIN; + SupplierTool_To_PTG_t SupplierTool_To_PTG; + Diag_To_PTG_t Diag_To_PTG; + Diag_Functional_t Diag_Functional; +} ptg_candb_rx_t; + +typedef struct +{ + PTG_Body_Stat_t PTG_Body_Stat; + PTG_To_SupplierTool_t PTG_To_SupplierTool; + Diag_From_PTG_t Diag_From_PTG; +} ptg_candb_tx_t; + +uint32_t ptg_candb_Receive(ptg_candb_rx_t* m, const uint8_t* d, uint32_t msgid, uint8_t dlc); + +#ifdef __DEF_PTG_CANDB__ + +extern ptg_candb_rx_t ptg_candb_rx; + +extern ptg_candb_tx_t ptg_candb_tx; + +#endif // __DEF_PTG_CANDB__ + +#ifdef __cplusplus +} +#endif diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/rb_psilcu_candb-binutil.c b/MODULES/HVAC_M7_CAN_MATRIX/butl/rb_psilcu_candb-binutil.c new file mode 100644 index 0000000..d9a5855 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/rb_psilcu_candb-binutil.c @@ -0,0 +1,41 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#include "rb_psilcu_candb-binutil.h" + +// DBC file version +#if (VER_CANDB_MAJ != (0U)) || (VER_CANDB_MIN != (0U)) +#error The RB_PSILCU_CANDB binutil source file has inconsistency with core dbc lib! +#endif + +#ifdef __DEF_RB_PSILCU_CANDB__ + +rb_psilcu_candb_rx_t rb_psilcu_candb_rx; + +rb_psilcu_candb_tx_t rb_psilcu_candb_tx; + +#endif // __DEF_RB_PSILCU_CANDB__ + +uint32_t rb_psilcu_candb_Receive(rb_psilcu_candb_rx_t* _m, const uint8_t* _d, uint32_t _id, uint8_t dlc_) +{ + uint32_t recid = 0; + if ((_id >= 0x23AU) && (_id < 0x5A6U)) { + if (_id == 0x23AU) { + recid = Unpack_BCM_StyleCmd1_candb(&(_m->BCM_StyleCmd1), _d, dlc_); + } else if (_id == 0x51AU) { + recid = Unpack_VEH_VIN_candb(&(_m->VEH_VIN), _d, dlc_); + } + } else { + if (_id == 0x5A6U) { + recid = Unpack_BCM_StyleCmd2_candb(&(_m->BCM_StyleCmd2), _d, dlc_); + } else { + if (_id == 0x5A7U) { + recid = Unpack_BCM_StyleCmd3_candb(&(_m->BCM_StyleCmd3), _d, dlc_); + } else if (_id == 0x78CU) { + recid = Unpack_Diag_To_RB_pSilCU_candb(&(_m->Diag_To_RB_pSilCU), _d, dlc_); + } + } + } + + return recid; +} + diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/rb_psilcu_candb-binutil.h b/MODULES/HVAC_M7_CAN_MATRIX/butl/rb_psilcu_candb-binutil.h new file mode 100644 index 0000000..5de42f2 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/rb_psilcu_candb-binutil.h @@ -0,0 +1,40 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dbccodeconf.h" + +#include "candb.h" + +typedef struct +{ + BCM_StyleCmd1_t BCM_StyleCmd1; + VEH_VIN_t VEH_VIN; + BCM_StyleCmd2_t BCM_StyleCmd2; + BCM_StyleCmd3_t BCM_StyleCmd3; + Diag_To_RB_pSilCU_t Diag_To_RB_pSilCU; +} rb_psilcu_candb_rx_t; + +typedef struct +{ + RB_pSilCU_State_t RB_pSilCU_State; + Diag_From_RB_pSilCU_t Diag_From_RB_pSilCU; +} rb_psilcu_candb_tx_t; + +uint32_t rb_psilcu_candb_Receive(rb_psilcu_candb_rx_t* m, const uint8_t* d, uint32_t msgid, uint8_t dlc); + +#ifdef __DEF_RB_PSILCU_CANDB__ + +extern rb_psilcu_candb_rx_t rb_psilcu_candb_rx; + +extern rb_psilcu_candb_tx_t rb_psilcu_candb_tx; + +#endif // __DEF_RB_PSILCU_CANDB__ + +#ifdef __cplusplus +} +#endif diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/rbcu_candb-binutil.c b/MODULES/HVAC_M7_CAN_MATRIX/butl/rbcu_candb-binutil.c new file mode 100644 index 0000000..5ef18d2 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/rbcu_candb-binutil.c @@ -0,0 +1,41 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#include "rbcu_candb-binutil.h" + +// DBC file version +#if (VER_CANDB_MAJ != (0U)) || (VER_CANDB_MIN != (0U)) +#error The RBCU_CANDB binutil source file has inconsistency with core dbc lib! +#endif + +#ifdef __DEF_RBCU_CANDB__ + +rbcu_candb_rx_t rbcu_candb_rx; + +rbcu_candb_tx_t rbcu_candb_tx; + +#endif // __DEF_RBCU_CANDB__ + +uint32_t rbcu_candb_Receive(rbcu_candb_rx_t* _m, const uint8_t* _d, uint32_t _id, uint8_t dlc_) +{ + uint32_t recid = 0; + if ((_id >= 0x100U) && (_id < 0x50BU)) { + if (_id == 0x100U) { + recid = Unpack_ESC_04_candb(&(_m->ESC_04), _d, dlc_); + } else if (_id == 0x280U) { + recid = Unpack_BCM_VEH_STATE_candb(&(_m->BCM_VEH_STATE), _d, dlc_); + } + } else { + if (_id == 0x50BU) { + recid = Unpack_FIU_Cmd_candb(&(_m->FIU_Cmd), _d, dlc_); + } else { + if (_id == 0x51AU) { + recid = Unpack_VEH_VIN_candb(&(_m->VEH_VIN), _d, dlc_); + } else if (_id == 0x51EU) { + recid = Unpack_BCM_RunningBoards_candb(&(_m->BCM_RunningBoards), _d, dlc_); + } + } + } + + return recid; +} + diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/rbcu_candb-binutil.h b/MODULES/HVAC_M7_CAN_MATRIX/butl/rbcu_candb-binutil.h new file mode 100644 index 0000000..88fa7f1 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/rbcu_candb-binutil.h @@ -0,0 +1,39 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dbccodeconf.h" + +#include "candb.h" + +typedef struct +{ + ESC_04_t ESC_04; + BCM_VEH_STATE_t BCM_VEH_STATE; + FIU_Cmd_t FIU_Cmd; + VEH_VIN_t VEH_VIN; + BCM_RunningBoards_t BCM_RunningBoards; +} rbcu_candb_rx_t; + +typedef struct +{ + RBCU_BODY_Stat_t RBCU_BODY_Stat; +} rbcu_candb_tx_t; + +uint32_t rbcu_candb_Receive(rbcu_candb_rx_t* m, const uint8_t* d, uint32_t msgid, uint8_t dlc); + +#ifdef __DEF_RBCU_CANDB__ + +extern rbcu_candb_rx_t rbcu_candb_rx; + +extern rbcu_candb_tx_t rbcu_candb_tx; + +#endif // __DEF_RBCU_CANDB__ + +#ifdef __cplusplus +} +#endif diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/sdm_candb-binutil.c b/MODULES/HVAC_M7_CAN_MATRIX/butl/sdm_candb-binutil.c new file mode 100644 index 0000000..2fce3b0 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/sdm_candb-binutil.c @@ -0,0 +1,181 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#include "sdm_candb-binutil.h" + +// DBC file version +#if (VER_CANDB_MAJ != (0U)) || (VER_CANDB_MIN != (0U)) +#error The SDM_CANDB binutil source file has inconsistency with core dbc lib! +#endif + +#ifdef __DEF_SDM_CANDB__ + +sdm_candb_rx_t sdm_candb_rx; + +sdm_candb_tx_t sdm_candb_tx; + +#endif // __DEF_SDM_CANDB__ + +uint32_t sdm_candb_Receive(sdm_candb_rx_t* _m, const uint8_t* _d, uint32_t _id, uint8_t dlc_) +{ + uint32_t recid = 0; + if ((_id >= 0x99U) && (_id < 0x3C1U)) { + if ((_id >= 0x99U) && (_id < 0x245U)) { + if ((_id >= 0x99U) && (_id < 0x152U)) { + if ((_id >= 0x99U) && (_id < 0x100U)) { + if (_id == 0x99U) { + recid = Unpack_VAU_SDM_Immo_Req_candb(&(_m->VAU_SDM_Immo_Req), _d, dlc_); + } else if (_id == 0xB1U) { + recid = Unpack_TCU_R932_1_candb(&(_m->TCU_R932_1), _d, dlc_); + } + } else { + if (_id == 0x100U) { + recid = Unpack_ESC_04_candb(&(_m->ESC_04), _d, dlc_); + } else { + if (_id == 0x150U) { + recid = Unpack_EMS_Veh_candb(&(_m->EMS_Veh), _d, dlc_); + } else if (_id == 0x151U) { + recid = Unpack_EMS_Indicators_candb(&(_m->EMS_Indicators), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x152U) && (_id < 0x231U)) { + if (_id == 0x152U) { + recid = Unpack_BCM_Powertrain_candb(&(_m->BCM_Powertrain), _d, dlc_); + } else if (_id == 0x21AU) { + recid = Unpack_EPB_Status_candb(&(_m->EPB_Status), _d, dlc_); + } + } else { + if (_id == 0x231U) { + recid = Unpack_BCM_ExteriorLightState_candb(&(_m->BCM_ExteriorLightState), _d, dlc_); + } else { + if (_id == 0x243U) { + recid = Unpack_DMFR_Msg1_candb(&(_m->DMFR_Msg1), _d, dlc_); + } else if (_id == 0x244U) { + recid = Unpack_DMFL_Msg1_candb(&(_m->DMFL_Msg1), _d, dlc_); + } + } + } + } + } else { + if ((_id >= 0x245U) && (_id < 0x2F0U)) { + if ((_id >= 0x245U) && (_id < 0x247U)) { + if (_id == 0x245U) { + recid = Unpack_DMRL_Msg1_candb(&(_m->DMRL_Msg1), _d, dlc_); + } else if (_id == 0x246U) { + recid = Unpack_DMRR_Msg1_candb(&(_m->DMRR_Msg1), _d, dlc_); + } + } else { + if (_id == 0x247U) { + recid = Unpack_TM_Stat_candb(&(_m->TM_Stat), _d, dlc_); + } else { + if (_id == 0x280U) { + recid = Unpack_BCM_VEH_STATE_candb(&(_m->BCM_VEH_STATE), _d, dlc_); + } else if (_id == 0x282U) { + recid = Unpack_BCM_Veh_State2_candb(&(_m->BCM_Veh_State2), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x2F0U) && (_id < 0x362U)) { + if (_id == 0x2F0U) { + recid = Unpack_BCM_Lock_CTR_candb(&(_m->BCM_Lock_CTR), _d, dlc_); + } else if (_id == 0x312U) { + recid = Unpack_CCU_Stat2_candb(&(_m->CCU_Stat2), _d, dlc_); + } + } else { + if (_id == 0x362U) { + recid = Unpack_BCM_IC_Info_Msg_candb(&(_m->BCM_IC_Info_Msg), _d, dlc_); + } else { + if (_id == 0x365U) { + recid = Unpack_BCM_CLIMATIC_DATA_candb(&(_m->BCM_CLIMATIC_DATA), _d, dlc_); + } else if (_id == 0x3AAU) { + recid = Unpack_IC_DATA_MSG_candb(&(_m->IC_DATA_MSG), _d, dlc_); + } + } + } + } + } + } else { + if ((_id >= 0x3C1U) && (_id < 0x514U)) { + if ((_id >= 0x3C1U) && (_id < 0x4D3U)) { + if ((_id >= 0x3C1U) && (_id < 0x4D0U)) { + if (_id == 0x3C1U) { + recid = Unpack_ESC_08_candb(&(_m->ESC_08), _d, dlc_); + } else if (_id == 0x3D0U) { + recid = Unpack_MAS_Status_candb(&(_m->MAS_Status), _d, dlc_); + } + } else { + if (_id == 0x4D0U) { + recid = Unpack_SMFL_status_candb(&(_m->SMFL_status), _d, dlc_); + } else { + if (_id == 0x4D1U) { + recid = Unpack_SMFR_status_candb(&(_m->SMFR_status), _d, dlc_); + } else if (_id == 0x4D2U) { + recid = Unpack_SMRL_status_candb(&(_m->SMRL_status), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x4D3U) && (_id < 0x501U)) { + if (_id == 0x4D3U) { + recid = Unpack_SMRR_status_candb(&(_m->SMRR_status), _d, dlc_); + } else if (_id == 0x4F0U) { + recid = Unpack_VAU_TPMS_Msg_candb(&(_m->VAU_TPMS_Msg), _d, dlc_); + } + } else { + if (_id == 0x501U) { + recid = Unpack_CCU_Msg3_candb(&(_m->CCU_Msg3), _d, dlc_); + } else { + if (_id == 0x50EU) { + recid = Unpack_IC_SDM_Info_candb(&(_m->IC_SDM_Info), _d, dlc_); + } else if (_id == 0x512U) { + recid = Unpack_IC_SDM_Info_02_candb(&(_m->IC_SDM_Info_02), _d, dlc_); + } + } + } + } + } else { + if ((_id >= 0x514U) && (_id < 0x5A3U)) { + if ((_id >= 0x514U) && (_id < 0x590U)) { + if (_id == 0x514U) { + recid = Unpack_IC_Milleage_candb(&(_m->IC_Milleage), _d, dlc_); + } else if (_id == 0x51AU) { + recid = Unpack_VEH_VIN_candb(&(_m->VEH_VIN), _d, dlc_); + } + } else { + if (_id == 0x590U) { + recid = Unpack_ERAG_DATA_MSG_candb(&(_m->ERAG_DATA_MSG), _d, dlc_); + } else { + if (_id == 0x5A1U) { + recid = Unpack_FIU_CCU1_candb(&(_m->FIU_CCU1), _d, dlc_); + } else if (_id == 0x5A2U) { + recid = Unpack_FIU_CCU2_candb(&(_m->FIU_CCU2), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x5A3U) && (_id < 0x5ADU)) { + if (_id == 0x5A3U) { + recid = Unpack_FIU_CCU3_candb(&(_m->FIU_CCU3), _d, dlc_); + } else if (_id == 0x5ACU) { + recid = Unpack_BCM_UserConfig_Stat_candb(&(_m->BCM_UserConfig_Stat), _d, dlc_); + } + } else { + if (_id == 0x5ADU) { + recid = Unpack_FIU_MAS_Main_candb(&(_m->FIU_MAS_Main), _d, dlc_); + } else { + if (_id == 0x5B1U) { + recid = Unpack_MAS_APA_Paths_candb(&(_m->MAS_APA_Paths), _d, dlc_); + } else if (_id == 0x7DFU) { + recid = Unpack_Diag_Functional_candb(&(_m->Diag_Functional), _d, dlc_); + } + } + } + } + } + } + + return recid; +} + diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/sdm_candb-binutil.h b/MODULES/HVAC_M7_CAN_MATRIX/butl/sdm_candb-binutil.h new file mode 100644 index 0000000..657ed04 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/sdm_candb-binutil.h @@ -0,0 +1,76 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dbccodeconf.h" + +#include "candb.h" + +typedef struct +{ + VAU_SDM_Immo_Req_t VAU_SDM_Immo_Req; + TCU_R932_1_t TCU_R932_1; + ESC_04_t ESC_04; + EMS_Veh_t EMS_Veh; + EMS_Indicators_t EMS_Indicators; + BCM_Powertrain_t BCM_Powertrain; + EPB_Status_t EPB_Status; + BCM_ExteriorLightState_t BCM_ExteriorLightState; + DMFR_Msg1_t DMFR_Msg1; + DMFL_Msg1_t DMFL_Msg1; + DMRL_Msg1_t DMRL_Msg1; + DMRR_Msg1_t DMRR_Msg1; + TM_Stat_t TM_Stat; + BCM_VEH_STATE_t BCM_VEH_STATE; + BCM_Veh_State2_t BCM_Veh_State2; + BCM_Lock_CTR_t BCM_Lock_CTR; + CCU_Stat2_t CCU_Stat2; + BCM_IC_Info_Msg_t BCM_IC_Info_Msg; + BCM_CLIMATIC_DATA_t BCM_CLIMATIC_DATA; + IC_DATA_MSG_t IC_DATA_MSG; + ESC_08_t ESC_08; + MAS_Status_t MAS_Status; + SMFL_status_t SMFL_status; + SMFR_status_t SMFR_status; + SMRL_status_t SMRL_status; + SMRR_status_t SMRR_status; + VAU_TPMS_Msg_t VAU_TPMS_Msg; + CCU_Msg3_t CCU_Msg3; + IC_SDM_Info_t IC_SDM_Info; + IC_SDM_Info_02_t IC_SDM_Info_02; + IC_Milleage_t IC_Milleage; + VEH_VIN_t VEH_VIN; + ERAG_DATA_MSG_t ERAG_DATA_MSG; + FIU_CCU1_t FIU_CCU1; + FIU_CCU2_t FIU_CCU2; + FIU_CCU3_t FIU_CCU3; + BCM_UserConfig_Stat_t BCM_UserConfig_Stat; + FIU_MAS_Main_t FIU_MAS_Main; + MAS_APA_Paths_t MAS_APA_Paths; + Diag_Functional_t Diag_Functional; +} sdm_candb_rx_t; + +typedef struct +{ + SDM_MAS_Req_t SDM_MAS_Req; + SDM_VAU_Hash_Resp_t SDM_VAU_Hash_Resp; + SDM_Cmd_t SDM_Cmd; +} sdm_candb_tx_t; + +uint32_t sdm_candb_Receive(sdm_candb_rx_t* m, const uint8_t* d, uint32_t msgid, uint8_t dlc); + +#ifdef __DEF_SDM_CANDB__ + +extern sdm_candb_rx_t sdm_candb_rx; + +extern sdm_candb_tx_t sdm_candb_tx; + +#endif // __DEF_SDM_CANDB__ + +#ifdef __cplusplus +} +#endif diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/smfl_candb-binutil.c b/MODULES/HVAC_M7_CAN_MATRIX/butl/smfl_candb-binutil.c new file mode 100644 index 0000000..5cd81ae --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/smfl_candb-binutil.c @@ -0,0 +1,133 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#include "smfl_candb-binutil.h" + +// DBC file version +#if (VER_CANDB_MAJ != (0U)) || (VER_CANDB_MIN != (0U)) +#error The SMFL_CANDB binutil source file has inconsistency with core dbc lib! +#endif + +#ifdef __DEF_SMFL_CANDB__ + +smfl_candb_rx_t smfl_candb_rx; + +smfl_candb_tx_t smfl_candb_tx; + +#endif // __DEF_SMFL_CANDB__ + +uint32_t smfl_candb_Receive(smfl_candb_rx_t* _m, const uint8_t* _d, uint32_t _id, uint8_t dlc_) +{ + uint32_t recid = 0; + if ((_id >= 0x130U) && (_id < 0x4B6U)) { + if ((_id >= 0x130U) && (_id < 0x251U)) { + if ((_id >= 0x130U) && (_id < 0x210U)) { + if (_id == 0x130U) { + recid = Unpack_ESC_YRS_01_candb(&(_m->ESC_YRS_01), _d, dlc_); + } else { + if (_id == 0x152U) { + recid = Unpack_BCM_Powertrain_candb(&(_m->BCM_Powertrain), _d, dlc_); + } else if (_id == 0x157U) { + recid = Unpack_BCM_EEM_candb(&(_m->BCM_EEM), _d, dlc_); + } + } + } else { + if ((_id >= 0x210U) && (_id < 0x244U)) { + if (_id == 0x210U) { + recid = Unpack_ACU_01_candb(&(_m->ACU_01), _d, dlc_); + } else if (_id == 0x23AU) { + recid = Unpack_BCM_StyleCmd1_candb(&(_m->BCM_StyleCmd1), _d, dlc_); + } + } else { + if (_id == 0x244U) { + recid = Unpack_DMFL_Msg1_candb(&(_m->DMFL_Msg1), _d, dlc_); + } else if (_id == 0x245U) { + recid = Unpack_DMRL_Msg1_candb(&(_m->DMRL_Msg1), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x251U) && (_id < 0x284U)) { + if (_id == 0x251U) { + recid = Unpack_BCM_DMS_01_candb(&(_m->BCM_DMS_01), _d, dlc_); + } else { + if (_id == 0x280U) { + recid = Unpack_BCM_VEH_STATE_candb(&(_m->BCM_VEH_STATE), _d, dlc_); + } else if (_id == 0x282U) { + recid = Unpack_BCM_Veh_State2_candb(&(_m->BCM_Veh_State2), _d, dlc_); + } + } + } else { + if ((_id >= 0x284U) && (_id < 0x313U)) { + if (_id == 0x284U) { + recid = Unpack_BCM_ALS_Light_Rear_candb(&(_m->BCM_ALS_Light_Rear), _d, dlc_); + } else if (_id == 0x285U) { + recid = Unpack_BCM_Rear_Plafond_Light_Data_candb(&(_m->BCM_Rear_Plafond_Light_Data), _d, dlc_); + } + } else { + if (_id == 0x313U) { + recid = Unpack_CCU_Requests_candb(&(_m->CCU_Requests), _d, dlc_); + } else if (_id == 0x367U) { + recid = Unpack_DMFL_SMFL_REQ_CTR_SEATS_candb(&(_m->DMFL_SMFL_REQ_CTR_SEATS), _d, dlc_); + } + } + } + } + } else { + if ((_id >= 0x4B6U) && (_id < 0x595U)) { + if ((_id >= 0x4B6U) && (_id < 0x536U)) { + if (_id == 0x4B6U) { + recid = Unpack_FIU_Profile_candb(&(_m->FIU_Profile), _d, dlc_); + } else { + if (_id == 0x51AU) { + recid = Unpack_VEH_VIN_candb(&(_m->VEH_VIN), _d, dlc_); + } else if (_id == 0x534U) { + recid = Unpack_BCM_MEM_SMFL1_candb(&(_m->BCM_MEM_SMFL1), _d, dlc_); + } + } + } else { + if ((_id >= 0x536U) && (_id < 0x553U)) { + if (_id == 0x536U) { + recid = Unpack_BCM_MEM_SMFL2_candb(&(_m->BCM_MEM_SMFL2), _d, dlc_); + } else if (_id == 0x53DU) { + recid = Unpack_SMRL_MEM2_candb(&(_m->SMRL_MEM2), _d, dlc_); + } + } else { + if (_id == 0x553U) { + recid = Unpack_FIU_SMFL_REQ_CTR_SEATS_candb(&(_m->FIU_SMFL_REQ_CTR_SEATS), _d, dlc_); + } else if (_id == 0x58EU) { + recid = Unpack_FIU_Msg1_candb(&(_m->FIU_Msg1), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x595U) && (_id < 0x7ADU)) { + if (_id == 0x595U) { + recid = Unpack_FIU_EngMenu_candb(&(_m->FIU_EngMenu), _d, dlc_); + } else { + if (_id == 0x5A6U) { + recid = Unpack_BCM_StyleCmd2_candb(&(_m->BCM_StyleCmd2), _d, dlc_); + } else if (_id == 0x5A7U) { + recid = Unpack_BCM_StyleCmd3_candb(&(_m->BCM_StyleCmd3), _d, dlc_); + } + } + } else { + if ((_id >= 0x7ADU) && (_id < 0x7DFU)) { + if (_id == 0x7ADU) { + recid = Unpack_Diag_To_SMFL_candb(&(_m->Diag_To_SMFL), _d, dlc_); + } else if (_id == 0x7D6U) { + recid = Unpack_Diag_To_OCUFL_candb(&(_m->Diag_To_OCUFL), _d, dlc_); + } + } else { + if (_id == 0x7DFU) { + recid = Unpack_Diag_Functional_candb(&(_m->Diag_Functional), _d, dlc_); + } else if (_id == 0x7E7U) { + recid = Unpack_Diag_To_SFLSilCU_candb(&(_m->Diag_To_SFLSilCU), _d, dlc_); + } + } + } + } + } + + return recid; +} + diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/smfl_candb-binutil.h b/MODULES/HVAC_M7_CAN_MATRIX/butl/smfl_candb-binutil.h new file mode 100644 index 0000000..f9189d1 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/smfl_candb-binutil.h @@ -0,0 +1,70 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dbccodeconf.h" + +#include "candb.h" + +typedef struct +{ + ESC_YRS_01_t ESC_YRS_01; + BCM_Powertrain_t BCM_Powertrain; + BCM_EEM_t BCM_EEM; + ACU_01_t ACU_01; + BCM_StyleCmd1_t BCM_StyleCmd1; + DMFL_Msg1_t DMFL_Msg1; + DMRL_Msg1_t DMRL_Msg1; + BCM_DMS_01_t BCM_DMS_01; + BCM_VEH_STATE_t BCM_VEH_STATE; + BCM_Veh_State2_t BCM_Veh_State2; + BCM_ALS_Light_Rear_t BCM_ALS_Light_Rear; + BCM_Rear_Plafond_Light_Data_t BCM_Rear_Plafond_Light_Data; + CCU_Requests_t CCU_Requests; + DMFL_SMFL_REQ_CTR_SEATS_t DMFL_SMFL_REQ_CTR_SEATS; + FIU_Profile_t FIU_Profile; + VEH_VIN_t VEH_VIN; + BCM_MEM_SMFL1_t BCM_MEM_SMFL1; + BCM_MEM_SMFL2_t BCM_MEM_SMFL2; + SMRL_MEM2_t SMRL_MEM2; + FIU_SMFL_REQ_CTR_SEATS_t FIU_SMFL_REQ_CTR_SEATS; + FIU_Msg1_t FIU_Msg1; + FIU_EngMenu_t FIU_EngMenu; + BCM_StyleCmd2_t BCM_StyleCmd2; + BCM_StyleCmd3_t BCM_StyleCmd3; + Diag_To_SMFL_t Diag_To_SMFL; + Diag_To_OCUFL_t Diag_To_OCUFL; + Diag_Functional_t Diag_Functional; + Diag_To_SFLSilCU_t Diag_To_SFLSilCU; +} smfl_candb_rx_t; + +typedef struct +{ + SMFL_status_t SMFL_status; + DocSL_T_FL_t DocSL_T_FL; + OCUFL_MSG_t OCUFL_MSG; + SMFL_MEM1_t SMFL_MEM1; + SMFL_MEM2_t SMFL_MEM2; + SFLSilCU_State_t SFLSilCU_State; + Diag_From_SMFL_t Diag_From_SMFL; + Diag_From_OCUFL_t Diag_From_OCUFL; + Diag_From_SFLSilCU_t Diag_From_SFLSilCU; +} smfl_candb_tx_t; + +uint32_t smfl_candb_Receive(smfl_candb_rx_t* m, const uint8_t* d, uint32_t msgid, uint8_t dlc); + +#ifdef __DEF_SMFL_CANDB__ + +extern smfl_candb_rx_t smfl_candb_rx; + +extern smfl_candb_tx_t smfl_candb_tx; + +#endif // __DEF_SMFL_CANDB__ + +#ifdef __cplusplus +} +#endif diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/smfr_candb-binutil.c b/MODULES/HVAC_M7_CAN_MATRIX/butl/smfr_candb-binutil.c new file mode 100644 index 0000000..363a1f6 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/smfr_candb-binutil.c @@ -0,0 +1,145 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#include "smfr_candb-binutil.h" + +// DBC file version +#if (VER_CANDB_MAJ != (0U)) || (VER_CANDB_MIN != (0U)) +#error The SMFR_CANDB binutil source file has inconsistency with core dbc lib! +#endif + +#ifdef __DEF_SMFR_CANDB__ + +smfr_candb_rx_t smfr_candb_rx; + +smfr_candb_tx_t smfr_candb_tx; + +#endif // __DEF_SMFR_CANDB__ + +uint32_t smfr_candb_Receive(smfr_candb_rx_t* _m, const uint8_t* _d, uint32_t _id, uint8_t dlc_) +{ + uint32_t recid = 0; + if ((_id >= 0x130U) && (_id < 0x36AU)) { + if ((_id >= 0x130U) && (_id < 0x246U)) { + if ((_id >= 0x130U) && (_id < 0x210U)) { + if (_id == 0x130U) { + recid = Unpack_ESC_YRS_01_candb(&(_m->ESC_YRS_01), _d, dlc_); + } else { + if (_id == 0x152U) { + recid = Unpack_BCM_Powertrain_candb(&(_m->BCM_Powertrain), _d, dlc_); + } else if (_id == 0x157U) { + recid = Unpack_BCM_EEM_candb(&(_m->BCM_EEM), _d, dlc_); + } + } + } else { + if ((_id >= 0x210U) && (_id < 0x243U)) { + if (_id == 0x210U) { + recid = Unpack_ACU_01_candb(&(_m->ACU_01), _d, dlc_); + } else if (_id == 0x23AU) { + recid = Unpack_BCM_StyleCmd1_candb(&(_m->BCM_StyleCmd1), _d, dlc_); + } + } else { + if (_id == 0x243U) { + recid = Unpack_DMFR_Msg1_candb(&(_m->DMFR_Msg1), _d, dlc_); + } else if (_id == 0x244U) { + recid = Unpack_DMFL_Msg1_candb(&(_m->DMFL_Msg1), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x246U) && (_id < 0x285U)) { + if ((_id >= 0x246U) && (_id < 0x282U)) { + if (_id == 0x246U) { + recid = Unpack_DMRR_Msg1_candb(&(_m->DMRR_Msg1), _d, dlc_); + } else if (_id == 0x280U) { + recid = Unpack_BCM_VEH_STATE_candb(&(_m->BCM_VEH_STATE), _d, dlc_); + } + } else { + if (_id == 0x282U) { + recid = Unpack_BCM_Veh_State2_candb(&(_m->BCM_Veh_State2), _d, dlc_); + } else if (_id == 0x284U) { + recid = Unpack_BCM_ALS_Light_Rear_candb(&(_m->BCM_ALS_Light_Rear), _d, dlc_); + } + } + } else { + if ((_id >= 0x285U) && (_id < 0x367U)) { + if (_id == 0x285U) { + recid = Unpack_BCM_Rear_Plafond_Light_Data_candb(&(_m->BCM_Rear_Plafond_Light_Data), _d, dlc_); + } else if (_id == 0x313U) { + recid = Unpack_CCU_Requests_candb(&(_m->CCU_Requests), _d, dlc_); + } + } else { + if (_id == 0x367U) { + recid = Unpack_DMFL_SMFL_REQ_CTR_SEATS_candb(&(_m->DMFL_SMFL_REQ_CTR_SEATS), _d, dlc_); + } else if (_id == 0x368U) { + recid = Unpack_DMFR_SMFR_REQ_CTR_SEATS_candb(&(_m->DMFR_SMFR_REQ_CTR_SEATS), _d, dlc_); + } + } + } + } + } else { + if ((_id >= 0x36AU) && (_id < 0x58EU)) { + if ((_id >= 0x36AU) && (_id < 0x52DU)) { + if ((_id >= 0x36AU) && (_id < 0x4D3U)) { + if (_id == 0x36AU) { + recid = Unpack_DMRR_SMRR_REQ_CTR_SEATS_candb(&(_m->DMRR_SMRR_REQ_CTR_SEATS), _d, dlc_); + } else if (_id == 0x4B6U) { + recid = Unpack_FIU_Profile_candb(&(_m->FIU_Profile), _d, dlc_); + } + } else { + if (_id == 0x4D3U) { + recid = Unpack_SMRR_status_candb(&(_m->SMRR_status), _d, dlc_); + } else if (_id == 0x51AU) { + recid = Unpack_VEH_VIN_candb(&(_m->VEH_VIN), _d, dlc_); + } + } + } else { + if ((_id >= 0x52DU) && (_id < 0x53AU)) { + if (_id == 0x52DU) { + recid = Unpack_FIU_SMFR_REQ_CTR_SEATS_candb(&(_m->FIU_SMFR_REQ_CTR_SEATS), _d, dlc_); + } else if (_id == 0x538U) { + recid = Unpack_BCM_MEM_SMFR1_candb(&(_m->BCM_MEM_SMFR1), _d, dlc_); + } + } else { + if (_id == 0x53AU) { + recid = Unpack_BCM_MEM_SMFR2_candb(&(_m->BCM_MEM_SMFR2), _d, dlc_); + } else if (_id == 0x541U) { + recid = Unpack_SMRR_MEM2_candb(&(_m->SMRR_MEM2), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x58EU) && (_id < 0x7AEU)) { + if ((_id >= 0x58EU) && (_id < 0x5A6U)) { + if (_id == 0x58EU) { + recid = Unpack_FIU_Msg1_candb(&(_m->FIU_Msg1), _d, dlc_); + } else if (_id == 0x595U) { + recid = Unpack_FIU_EngMenu_candb(&(_m->FIU_EngMenu), _d, dlc_); + } + } else { + if (_id == 0x5A6U) { + recid = Unpack_BCM_StyleCmd2_candb(&(_m->BCM_StyleCmd2), _d, dlc_); + } else if (_id == 0x5A7U) { + recid = Unpack_BCM_StyleCmd3_candb(&(_m->BCM_StyleCmd3), _d, dlc_); + } + } + } else { + if ((_id >= 0x7AEU) && (_id < 0x7DFU)) { + if (_id == 0x7AEU) { + recid = Unpack_Diag_To_SMFR_candb(&(_m->Diag_To_SMFR), _d, dlc_); + } else if (_id == 0x7DCU) { + recid = Unpack_Diag_To_OCUFR_candb(&(_m->Diag_To_OCUFR), _d, dlc_); + } + } else { + if (_id == 0x7DFU) { + recid = Unpack_Diag_Functional_candb(&(_m->Diag_Functional), _d, dlc_); + } else if (_id == 0x7E5U) { + recid = Unpack_Diag_To_SFRSilCU_candb(&(_m->Diag_To_SFRSilCU), _d, dlc_); + } + } + } + } + } + + return recid; +} + diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/smfr_candb-binutil.h b/MODULES/HVAC_M7_CAN_MATRIX/butl/smfr_candb-binutil.h new file mode 100644 index 0000000..1db74da --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/smfr_candb-binutil.h @@ -0,0 +1,73 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dbccodeconf.h" + +#include "candb.h" + +typedef struct +{ + ESC_YRS_01_t ESC_YRS_01; + BCM_Powertrain_t BCM_Powertrain; + BCM_EEM_t BCM_EEM; + ACU_01_t ACU_01; + BCM_StyleCmd1_t BCM_StyleCmd1; + DMFR_Msg1_t DMFR_Msg1; + DMFL_Msg1_t DMFL_Msg1; + DMRR_Msg1_t DMRR_Msg1; + BCM_VEH_STATE_t BCM_VEH_STATE; + BCM_Veh_State2_t BCM_Veh_State2; + BCM_ALS_Light_Rear_t BCM_ALS_Light_Rear; + BCM_Rear_Plafond_Light_Data_t BCM_Rear_Plafond_Light_Data; + CCU_Requests_t CCU_Requests; + DMFL_SMFL_REQ_CTR_SEATS_t DMFL_SMFL_REQ_CTR_SEATS; + DMFR_SMFR_REQ_CTR_SEATS_t DMFR_SMFR_REQ_CTR_SEATS; + DMRR_SMRR_REQ_CTR_SEATS_t DMRR_SMRR_REQ_CTR_SEATS; + FIU_Profile_t FIU_Profile; + SMRR_status_t SMRR_status; + VEH_VIN_t VEH_VIN; + FIU_SMFR_REQ_CTR_SEATS_t FIU_SMFR_REQ_CTR_SEATS; + BCM_MEM_SMFR1_t BCM_MEM_SMFR1; + BCM_MEM_SMFR2_t BCM_MEM_SMFR2; + SMRR_MEM2_t SMRR_MEM2; + FIU_Msg1_t FIU_Msg1; + FIU_EngMenu_t FIU_EngMenu; + BCM_StyleCmd2_t BCM_StyleCmd2; + BCM_StyleCmd3_t BCM_StyleCmd3; + Diag_To_SMFR_t Diag_To_SMFR; + Diag_To_OCUFR_t Diag_To_OCUFR; + Diag_Functional_t Diag_Functional; + Diag_To_SFRSilCU_t Diag_To_SFRSilCU; +} smfr_candb_rx_t; + +typedef struct +{ + SMFR_status_t SMFR_status; + DocSR_T_FR_t DocSR_T_FR; + OCUFR_MSG_t OCUFR_MSG; + SMFR_MEM1_t SMFR_MEM1; + SMFR_MEM2_t SMFR_MEM2; + SFRSilCU_State_t SFRSilCU_State; + Diag_From_SMFR_t Diag_From_SMFR; + Diag_From_OCUFR_t Diag_From_OCUFR; + Diag_From_SFRSilCU_t Diag_From_SFRSilCU; +} smfr_candb_tx_t; + +uint32_t smfr_candb_Receive(smfr_candb_rx_t* m, const uint8_t* d, uint32_t msgid, uint8_t dlc); + +#ifdef __DEF_SMFR_CANDB__ + +extern smfr_candb_rx_t smfr_candb_rx; + +extern smfr_candb_tx_t smfr_candb_tx; + +#endif // __DEF_SMFR_CANDB__ + +#ifdef __cplusplus +} +#endif diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/smrl_candb-binutil.c b/MODULES/HVAC_M7_CAN_MATRIX/butl/smrl_candb-binutil.c new file mode 100644 index 0000000..d891465 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/smrl_candb-binutil.c @@ -0,0 +1,97 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#include "smrl_candb-binutil.h" + +// DBC file version +#if (VER_CANDB_MAJ != (0U)) || (VER_CANDB_MIN != (0U)) +#error The SMRL_CANDB binutil source file has inconsistency with core dbc lib! +#endif + +#ifdef __DEF_SMRL_CANDB__ + +smrl_candb_rx_t smrl_candb_rx; + +smrl_candb_tx_t smrl_candb_tx; + +#endif // __DEF_SMRL_CANDB__ + +uint32_t smrl_candb_Receive(smrl_candb_rx_t* _m, const uint8_t* _d, uint32_t _id, uint8_t dlc_) +{ + uint32_t recid = 0; + if ((_id >= 0x130U) && (_id < 0x369U)) { + if ((_id >= 0x130U) && (_id < 0x245U)) { + if ((_id >= 0x130U) && (_id < 0x157U)) { + if (_id == 0x130U) { + recid = Unpack_ESC_YRS_01_candb(&(_m->ESC_YRS_01), _d, dlc_); + } else if (_id == 0x152U) { + recid = Unpack_BCM_Powertrain_candb(&(_m->BCM_Powertrain), _d, dlc_); + } + } else { + if (_id == 0x157U) { + recid = Unpack_BCM_EEM_candb(&(_m->BCM_EEM), _d, dlc_); + } else if (_id == 0x210U) { + recid = Unpack_ACU_01_candb(&(_m->ACU_01), _d, dlc_); + } + } + } else { + if ((_id >= 0x245U) && (_id < 0x282U)) { + if (_id == 0x245U) { + recid = Unpack_DMRL_Msg1_candb(&(_m->DMRL_Msg1), _d, dlc_); + } else if (_id == 0x280U) { + recid = Unpack_BCM_VEH_STATE_candb(&(_m->BCM_VEH_STATE), _d, dlc_); + } + } else { + if (_id == 0x282U) { + recid = Unpack_BCM_Veh_State2_candb(&(_m->BCM_Veh_State2), _d, dlc_); + } else { + if (_id == 0x284U) { + recid = Unpack_BCM_ALS_Light_Rear_candb(&(_m->BCM_ALS_Light_Rear), _d, dlc_); + } else if (_id == 0x313U) { + recid = Unpack_CCU_Requests_candb(&(_m->CCU_Requests), _d, dlc_); + } + } + } + } + } else { + if ((_id >= 0x369U) && (_id < 0x53EU)) { + if ((_id >= 0x369U) && (_id < 0x51AU)) { + if (_id == 0x369U) { + recid = Unpack_DMRL_SMRL_REQ_CTR_SEATS_candb(&(_m->DMRL_SMRL_REQ_CTR_SEATS), _d, dlc_); + } else if (_id == 0x4B6U) { + recid = Unpack_FIU_Profile_candb(&(_m->FIU_Profile), _d, dlc_); + } + } else { + if (_id == 0x51AU) { + recid = Unpack_VEH_VIN_candb(&(_m->VEH_VIN), _d, dlc_); + } else { + if (_id == 0x52CU) { + recid = Unpack_FIU_SMRL_REQ_CTR_SEATS_candb(&(_m->FIU_SMRL_REQ_CTR_SEATS), _d, dlc_); + } else if (_id == 0x53CU) { + recid = Unpack_BCM_MEM_SMRL1_candb(&(_m->BCM_MEM_SMRL1), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x53EU) && (_id < 0x7AFU)) { + if (_id == 0x53EU) { + recid = Unpack_BCM_MEM_SMRL2_candb(&(_m->BCM_MEM_SMRL2), _d, dlc_); + } else if (_id == 0x58EU) { + recid = Unpack_FIU_Msg1_candb(&(_m->FIU_Msg1), _d, dlc_); + } + } else { + if (_id == 0x7AFU) { + recid = Unpack_Diag_To_SMRL_candb(&(_m->Diag_To_SMRL), _d, dlc_); + } else { + if (_id == 0x7DDU) { + recid = Unpack_Diag_To_OCURL_candb(&(_m->Diag_To_OCURL), _d, dlc_); + } else if (_id == 0x7DFU) { + recid = Unpack_Diag_Functional_candb(&(_m->Diag_Functional), _d, dlc_); + } + } + } + } + } + + return recid; +} + diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/smrl_candb-binutil.h b/MODULES/HVAC_M7_CAN_MATRIX/butl/smrl_candb-binutil.h new file mode 100644 index 0000000..63f3c84 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/smrl_candb-binutil.h @@ -0,0 +1,58 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dbccodeconf.h" + +#include "candb.h" + +typedef struct +{ + ESC_YRS_01_t ESC_YRS_01; + BCM_Powertrain_t BCM_Powertrain; + BCM_EEM_t BCM_EEM; + ACU_01_t ACU_01; + DMRL_Msg1_t DMRL_Msg1; + BCM_VEH_STATE_t BCM_VEH_STATE; + BCM_Veh_State2_t BCM_Veh_State2; + BCM_ALS_Light_Rear_t BCM_ALS_Light_Rear; + CCU_Requests_t CCU_Requests; + DMRL_SMRL_REQ_CTR_SEATS_t DMRL_SMRL_REQ_CTR_SEATS; + FIU_Profile_t FIU_Profile; + VEH_VIN_t VEH_VIN; + FIU_SMRL_REQ_CTR_SEATS_t FIU_SMRL_REQ_CTR_SEATS; + BCM_MEM_SMRL1_t BCM_MEM_SMRL1; + BCM_MEM_SMRL2_t BCM_MEM_SMRL2; + FIU_Msg1_t FIU_Msg1; + Diag_To_SMRL_t Diag_To_SMRL; + Diag_To_OCURL_t Diag_To_OCURL; + Diag_Functional_t Diag_Functional; +} smrl_candb_rx_t; + +typedef struct +{ + SMRL_status_t SMRL_status; + OCURL_MSG_t OCURL_MSG; + SMRL_MEM1_t SMRL_MEM1; + SMRL_MEM2_t SMRL_MEM2; + Diag_From_SMRL_t Diag_From_SMRL; + Diag_From_OCURL_t Diag_From_OCURL; +} smrl_candb_tx_t; + +uint32_t smrl_candb_Receive(smrl_candb_rx_t* m, const uint8_t* d, uint32_t msgid, uint8_t dlc); + +#ifdef __DEF_SMRL_CANDB__ + +extern smrl_candb_rx_t smrl_candb_rx; + +extern smrl_candb_tx_t smrl_candb_tx; + +#endif // __DEF_SMRL_CANDB__ + +#ifdef __cplusplus +} +#endif diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/smrr_candb-binutil.c b/MODULES/HVAC_M7_CAN_MATRIX/butl/smrr_candb-binutil.c new file mode 100644 index 0000000..784a548 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/smrr_candb-binutil.c @@ -0,0 +1,105 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#include "smrr_candb-binutil.h" + +// DBC file version +#if (VER_CANDB_MAJ != (0U)) || (VER_CANDB_MIN != (0U)) +#error The SMRR_CANDB binutil source file has inconsistency with core dbc lib! +#endif + +#ifdef __DEF_SMRR_CANDB__ + +smrr_candb_rx_t smrr_candb_rx; + +smrr_candb_tx_t smrr_candb_tx; + +#endif // __DEF_SMRR_CANDB__ + +uint32_t smrr_candb_Receive(smrr_candb_rx_t* _m, const uint8_t* _d, uint32_t _id, uint8_t dlc_) +{ + uint32_t recid = 0; + if ((_id >= 0x130U) && (_id < 0x367U)) { + if ((_id >= 0x130U) && (_id < 0x246U)) { + if ((_id >= 0x130U) && (_id < 0x157U)) { + if (_id == 0x130U) { + recid = Unpack_ESC_YRS_01_candb(&(_m->ESC_YRS_01), _d, dlc_); + } else if (_id == 0x152U) { + recid = Unpack_BCM_Powertrain_candb(&(_m->BCM_Powertrain), _d, dlc_); + } + } else { + if (_id == 0x157U) { + recid = Unpack_BCM_EEM_candb(&(_m->BCM_EEM), _d, dlc_); + } else { + if (_id == 0x210U) { + recid = Unpack_ACU_01_candb(&(_m->ACU_01), _d, dlc_); + } else if (_id == 0x244U) { + recid = Unpack_DMFL_Msg1_candb(&(_m->DMFL_Msg1), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x246U) && (_id < 0x282U)) { + if (_id == 0x246U) { + recid = Unpack_DMRR_Msg1_candb(&(_m->DMRR_Msg1), _d, dlc_); + } else if (_id == 0x280U) { + recid = Unpack_BCM_VEH_STATE_candb(&(_m->BCM_VEH_STATE), _d, dlc_); + } + } else { + if (_id == 0x282U) { + recid = Unpack_BCM_Veh_State2_candb(&(_m->BCM_Veh_State2), _d, dlc_); + } else { + if (_id == 0x284U) { + recid = Unpack_BCM_ALS_Light_Rear_candb(&(_m->BCM_ALS_Light_Rear), _d, dlc_); + } else if (_id == 0x313U) { + recid = Unpack_CCU_Requests_candb(&(_m->CCU_Requests), _d, dlc_); + } + } + } + } + } else { + if ((_id >= 0x367U) && (_id < 0x542U)) { + if ((_id >= 0x367U) && (_id < 0x4B6U)) { + if (_id == 0x367U) { + recid = Unpack_DMFL_SMFL_REQ_CTR_SEATS_candb(&(_m->DMFL_SMFL_REQ_CTR_SEATS), _d, dlc_); + } else if (_id == 0x36AU) { + recid = Unpack_DMRR_SMRR_REQ_CTR_SEATS_candb(&(_m->DMRR_SMRR_REQ_CTR_SEATS), _d, dlc_); + } + } else { + if (_id == 0x4B6U) { + recid = Unpack_FIU_Profile_candb(&(_m->FIU_Profile), _d, dlc_); + } else { + if (_id == 0x51AU) { + recid = Unpack_VEH_VIN_candb(&(_m->VEH_VIN), _d, dlc_); + } else if (_id == 0x540U) { + recid = Unpack_BCM_MEM_SMRR1_candb(&(_m->BCM_MEM_SMRR1), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x542U) && (_id < 0x7A9U)) { + if (_id == 0x542U) { + recid = Unpack_BCM_MEM_SMRR2_candb(&(_m->BCM_MEM_SMRR2), _d, dlc_); + } else { + if (_id == 0x554U) { + recid = Unpack_FIU_SMRR_REQ_CTR_SEATS_candb(&(_m->FIU_SMRR_REQ_CTR_SEATS), _d, dlc_); + } else if (_id == 0x58EU) { + recid = Unpack_FIU_Msg1_candb(&(_m->FIU_Msg1), _d, dlc_); + } + } + } else { + if (_id == 0x7A9U) { + recid = Unpack_Diag_To_SMRR_candb(&(_m->Diag_To_SMRR), _d, dlc_); + } else { + if (_id == 0x7DEU) { + recid = Unpack_Diag_To_OCURR_candb(&(_m->Diag_To_OCURR), _d, dlc_); + } else if (_id == 0x7DFU) { + recid = Unpack_Diag_Functional_candb(&(_m->Diag_Functional), _d, dlc_); + } + } + } + } + } + + return recid; +} + diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/smrr_candb-binutil.h b/MODULES/HVAC_M7_CAN_MATRIX/butl/smrr_candb-binutil.h new file mode 100644 index 0000000..87e6d86 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/smrr_candb-binutil.h @@ -0,0 +1,60 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dbccodeconf.h" + +#include "candb.h" + +typedef struct +{ + ESC_YRS_01_t ESC_YRS_01; + BCM_Powertrain_t BCM_Powertrain; + BCM_EEM_t BCM_EEM; + ACU_01_t ACU_01; + DMFL_Msg1_t DMFL_Msg1; + DMRR_Msg1_t DMRR_Msg1; + BCM_VEH_STATE_t BCM_VEH_STATE; + BCM_Veh_State2_t BCM_Veh_State2; + BCM_ALS_Light_Rear_t BCM_ALS_Light_Rear; + CCU_Requests_t CCU_Requests; + DMFL_SMFL_REQ_CTR_SEATS_t DMFL_SMFL_REQ_CTR_SEATS; + DMRR_SMRR_REQ_CTR_SEATS_t DMRR_SMRR_REQ_CTR_SEATS; + FIU_Profile_t FIU_Profile; + VEH_VIN_t VEH_VIN; + BCM_MEM_SMRR1_t BCM_MEM_SMRR1; + BCM_MEM_SMRR2_t BCM_MEM_SMRR2; + FIU_SMRR_REQ_CTR_SEATS_t FIU_SMRR_REQ_CTR_SEATS; + FIU_Msg1_t FIU_Msg1; + Diag_To_SMRR_t Diag_To_SMRR; + Diag_To_OCURR_t Diag_To_OCURR; + Diag_Functional_t Diag_Functional; +} smrr_candb_rx_t; + +typedef struct +{ + SMRR_status_t SMRR_status; + OCURR_MSG_t OCURR_MSG; + SMRR_MEM1_t SMRR_MEM1; + SMRR_MEM2_t SMRR_MEM2; + Diag_From_SMRR_t Diag_From_SMRR; + Diag_From_OCURR_t Diag_From_OCURR; +} smrr_candb_tx_t; + +uint32_t smrr_candb_Receive(smrr_candb_rx_t* m, const uint8_t* d, uint32_t msgid, uint8_t dlc); + +#ifdef __DEF_SMRR_CANDB__ + +extern smrr_candb_rx_t smrr_candb_rx; + +extern smrr_candb_tx_t smrr_candb_tx; + +#endif // __DEF_SMRR_CANDB__ + +#ifdef __cplusplus +} +#endif diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/sroof_candb-binutil.c b/MODULES/HVAC_M7_CAN_MATRIX/butl/sroof_candb-binutil.c new file mode 100644 index 0000000..9b2708b --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/sroof_candb-binutil.c @@ -0,0 +1,49 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#include "sroof_candb-binutil.h" + +// DBC file version +#if (VER_CANDB_MAJ != (0U)) || (VER_CANDB_MIN != (0U)) +#error The SROOF_CANDB binutil source file has inconsistency with core dbc lib! +#endif + +#ifdef __DEF_SROOF_CANDB__ + +sroof_candb_rx_t sroof_candb_rx; + +sroof_candb_tx_t sroof_candb_tx; + +#endif // __DEF_SROOF_CANDB__ + +uint32_t sroof_candb_Receive(sroof_candb_rx_t* _m, const uint8_t* _d, uint32_t _id, uint8_t dlc_) +{ + uint32_t recid = 0; + if ((_id >= 0x157U) && (_id < 0x280U)) { + if (_id == 0x157U) { + recid = Unpack_BCM_EEM_candb(&(_m->BCM_EEM), _d, dlc_); + } else { + if (_id == 0x243U) { + recid = Unpack_DMFR_Msg1_candb(&(_m->DMFR_Msg1), _d, dlc_); + } else if (_id == 0x244U) { + recid = Unpack_DMFL_Msg1_candb(&(_m->DMFL_Msg1), _d, dlc_); + } + } + } else { + if ((_id >= 0x280U) && (_id < 0x51AU)) { + if (_id == 0x280U) { + recid = Unpack_BCM_VEH_STATE_candb(&(_m->BCM_VEH_STATE), _d, dlc_); + } else if (_id == 0x282U) { + recid = Unpack_BCM_Veh_State2_candb(&(_m->BCM_Veh_State2), _d, dlc_); + } + } else { + if (_id == 0x51AU) { + recid = Unpack_VEH_VIN_candb(&(_m->VEH_VIN), _d, dlc_); + } else if (_id == 0x76FU) { + recid = Unpack_Diag_To_Sroof_candb(&(_m->Diag_To_Sroof), _d, dlc_); + } + } + } + + return recid; +} + diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/sroof_candb-binutil.h b/MODULES/HVAC_M7_CAN_MATRIX/butl/sroof_candb-binutil.h new file mode 100644 index 0000000..2952af4 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/sroof_candb-binutil.h @@ -0,0 +1,42 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dbccodeconf.h" + +#include "candb.h" + +typedef struct +{ + BCM_EEM_t BCM_EEM; + DMFR_Msg1_t DMFR_Msg1; + DMFL_Msg1_t DMFL_Msg1; + BCM_VEH_STATE_t BCM_VEH_STATE; + BCM_Veh_State2_t BCM_Veh_State2; + VEH_VIN_t VEH_VIN; + Diag_To_Sroof_t Diag_To_Sroof; +} sroof_candb_rx_t; + +typedef struct +{ + Sroof_State_t Sroof_State; + Diag_From_SRoof_t Diag_From_SRoof; +} sroof_candb_tx_t; + +uint32_t sroof_candb_Receive(sroof_candb_rx_t* m, const uint8_t* d, uint32_t msgid, uint8_t dlc); + +#ifdef __DEF_SROOF_CANDB__ + +extern sroof_candb_rx_t sroof_candb_rx; + +extern sroof_candb_tx_t sroof_candb_tx; + +#endif // __DEF_SROOF_CANDB__ + +#ifdef __cplusplus +} +#endif diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/tm_candb-binutil.c b/MODULES/HVAC_M7_CAN_MATRIX/butl/tm_candb-binutil.c new file mode 100644 index 0000000..e286bb5 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/tm_candb-binutil.c @@ -0,0 +1,213 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#include "tm_candb-binutil.h" + +// DBC file version +#if (VER_CANDB_MAJ != (0U)) || (VER_CANDB_MIN != (0U)) +#error The TM_CANDB binutil source file has inconsistency with core dbc lib! +#endif + +#ifdef __DEF_TM_CANDB__ + +tm_candb_rx_t tm_candb_rx; + +tm_candb_tx_t tm_candb_tx; + +#endif // __DEF_TM_CANDB__ + +uint32_t tm_candb_Receive(tm_candb_rx_t* _m, const uint8_t* _d, uint32_t _id, uint8_t dlc_) +{ + uint32_t recid = 0; + if ((_id >= 0xB1U) && (_id < 0x587U)) { + if ((_id >= 0xB1U) && (_id < 0x283U)) { + if ((_id >= 0xB1U) && (_id < 0x244U)) { + if ((_id >= 0xB1U) && (_id < 0x210U)) { + if (_id == 0xB1U) { + recid = Unpack_TCU_R932_1_candb(&(_m->TCU_R932_1), _d, dlc_); + } else { + if (_id == 0x100U) { + recid = Unpack_ESC_04_candb(&(_m->ESC_04), _d, dlc_); + } else if (_id == 0x157U) { + recid = Unpack_BCM_EEM_candb(&(_m->BCM_EEM), _d, dlc_); + } + } + } else { + if (_id == 0x210U) { + recid = Unpack_ACU_01_candb(&(_m->ACU_01), _d, dlc_); + } else { + if (_id == 0x231U) { + recid = Unpack_BCM_ExteriorLightState_candb(&(_m->BCM_ExteriorLightState), _d, dlc_); + } else if (_id == 0x23AU) { + recid = Unpack_BCM_StyleCmd1_candb(&(_m->BCM_StyleCmd1), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x244U) && (_id < 0x24FU)) { + if (_id == 0x244U) { + recid = Unpack_DMFL_Msg1_candb(&(_m->DMFL_Msg1), _d, dlc_); + } else { + if (_id == 0x245U) { + recid = Unpack_DMRL_Msg1_candb(&(_m->DMRL_Msg1), _d, dlc_); + } else if (_id == 0x246U) { + recid = Unpack_DMRR_Msg1_candb(&(_m->DMRR_Msg1), _d, dlc_); + } + } + } else { + if (_id == 0x24FU) { + recid = Unpack_VAU2_Msg2_candb(&(_m->VAU2_Msg2), _d, dlc_); + } else { + if (_id == 0x280U) { + recid = Unpack_BCM_VEH_STATE_candb(&(_m->BCM_VEH_STATE), _d, dlc_); + } else if (_id == 0x282U) { + recid = Unpack_BCM_Veh_State2_candb(&(_m->BCM_Veh_State2), _d, dlc_); + } + } + } + } + } else { + if ((_id >= 0x283U) && (_id < 0x380U)) { + if ((_id >= 0x283U) && (_id < 0x2F0U)) { + if (_id == 0x283U) { + recid = Unpack_BCM_ALS_Light_Front_candb(&(_m->BCM_ALS_Light_Front), _d, dlc_); + } else { + if (_id == 0x284U) { + recid = Unpack_BCM_ALS_Light_Rear_candb(&(_m->BCM_ALS_Light_Rear), _d, dlc_); + } else if (_id == 0x285U) { + recid = Unpack_BCM_Rear_Plafond_Light_Data_candb(&(_m->BCM_Rear_Plafond_Light_Data), _d, dlc_); + } + } + } else { + if (_id == 0x2F0U) { + recid = Unpack_BCM_Lock_CTR_candb(&(_m->BCM_Lock_CTR), _d, dlc_); + } else { + if (_id == 0x362U) { + recid = Unpack_BCM_IC_Info_Msg_candb(&(_m->BCM_IC_Info_Msg), _d, dlc_); + } else if (_id == 0x365U) { + recid = Unpack_BCM_CLIMATIC_DATA_candb(&(_m->BCM_CLIMATIC_DATA), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x380U) && (_id < 0x4D5U)) { + if (_id == 0x380U) { + recid = Unpack_CCU_Msg1_candb(&(_m->CCU_Msg1), _d, dlc_); + } else { + if (_id == 0x38AU) { + recid = Unpack_Sroof_State_candb(&(_m->Sroof_State), _d, dlc_); + } else if (_id == 0x4D4U) { + recid = Unpack_DocSL_T_FL_candb(&(_m->DocSL_T_FL), _d, dlc_); + } + } + } else { + if (_id == 0x4D5U) { + recid = Unpack_DocSR_T_FR_candb(&(_m->DocSR_T_FR), _d, dlc_); + } else { + if (_id == 0x50BU) { + recid = Unpack_FIU_Cmd_candb(&(_m->FIU_Cmd), _d, dlc_); + } else if (_id == 0x51AU) { + recid = Unpack_VEH_VIN_candb(&(_m->VEH_VIN), _d, dlc_); + } + } + } + } + } + } else { + if ((_id >= 0x587U) && (_id < 0x709U)) { + if ((_id >= 0x587U) && (_id < 0x5A7U)) { + if ((_id >= 0x587U) && (_id < 0x594U)) { + if (_id == 0x587U) { + recid = Unpack_FIU_CTRL_DW_candb(&(_m->FIU_CTRL_DW), _d, dlc_); + } else { + if (_id == 0x58EU) { + recid = Unpack_FIU_Msg1_candb(&(_m->FIU_Msg1), _d, dlc_); + } else if (_id == 0x58FU) { + recid = Unpack_FIU_Msg2_candb(&(_m->FIU_Msg2), _d, dlc_); + } + } + } else { + if (_id == 0x594U) { + recid = Unpack_FIU_Msg3_candb(&(_m->FIU_Msg3), _d, dlc_); + } else { + if (_id == 0x595U) { + recid = Unpack_FIU_EngMenu_candb(&(_m->FIU_EngMenu), _d, dlc_); + } else if (_id == 0x5A6U) { + recid = Unpack_BCM_StyleCmd2_candb(&(_m->BCM_StyleCmd2), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x5A7U) && (_id < 0x702U)) { + if (_id == 0x5A7U) { + recid = Unpack_BCM_StyleCmd3_candb(&(_m->BCM_StyleCmd3), _d, dlc_); + } else { + if (_id == 0x5AAU) { + recid = Unpack_IC_DISPLAY_CLOCK_candb(&(_m->IC_DISPLAY_CLOCK), _d, dlc_); + } else if (_id == 0x5F3U) { + recid = Unpack_IntCOM_Info_Stat_candb(&(_m->IntCOM_Info_Stat), _d, dlc_); + } + } + } else { + if (_id == 0x702U) { + recid = Unpack_Diag_To_CCPF_candb(&(_m->Diag_To_CCPF), _d, dlc_); + } else { + if (_id == 0x704U) { + recid = Unpack_Diag_To_CCPR_candb(&(_m->Diag_To_CCPR), _d, dlc_); + } else if (_id == 0x706U) { + recid = Unpack_Diag_To_SSL_candb(&(_m->Diag_To_SSL), _d, dlc_); + } + } + } + } + } else { + if ((_id >= 0x709U) && (_id < 0x7AAU)) { + if ((_id >= 0x709U) && (_id < 0x784U)) { + if (_id == 0x709U) { + recid = Unpack_Diag_To_SSR_candb(&(_m->Diag_To_SSR), _d, dlc_); + } else { + if (_id == 0x718U) { + recid = Unpack_Diag_To_FCSilCU_candb(&(_m->Diag_To_FCSilCU), _d, dlc_); + } else if (_id == 0x720U) { + recid = Unpack_Diag_To_ICLSilCU_candb(&(_m->Diag_To_ICLSilCU), _d, dlc_); + } + } + } else { + if (_id == 0x784U) { + recid = Unpack_Diag_To_ICRSilCU_candb(&(_m->Diag_To_ICRSilCU), _d, dlc_); + } else { + if (_id == 0x788U) { + recid = Unpack_Diag_To_PLSilCU_candb(&(_m->Diag_To_PLSilCU), _d, dlc_); + } else if (_id == 0x789U) { + recid = Unpack_Diag_To_PRSilCU_candb(&(_m->Diag_To_PRSilCU), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x7AAU) && (_id < 0x7C3U)) { + if (_id == 0x7AAU) { + recid = Unpack_Diag_To_TM_candb(&(_m->Diag_To_TM), _d, dlc_); + } else { + if (_id == 0x7C1U) { + recid = Unpack_Diag_To_RCLSilCU_candb(&(_m->Diag_To_RCLSilCU), _d, dlc_); + } else if (_id == 0x7C2U) { + recid = Unpack_Diag_To_RCRSilCU_candb(&(_m->Diag_To_RCRSilCU), _d, dlc_); + } + } + } else { + if (_id == 0x7C3U) { + recid = Unpack_Diag_To_RDLSilCU_candb(&(_m->Diag_To_RDLSilCU), _d, dlc_); + } else { + if (_id == 0x7C4U) { + recid = Unpack_Diag_To_RDRSilCU_candb(&(_m->Diag_To_RDRSilCU), _d, dlc_); + } else if (_id == 0x7DFU) { + recid = Unpack_Diag_Functional_candb(&(_m->Diag_Functional), _d, dlc_); + } + } + } + } + } + } + + return recid; +} + diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/tm_candb-binutil.h b/MODULES/HVAC_M7_CAN_MATRIX/butl/tm_candb-binutil.h new file mode 100644 index 0000000..4606bf6 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/tm_candb-binutil.h @@ -0,0 +1,109 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dbccodeconf.h" + +#include "candb.h" + +typedef struct +{ + TCU_R932_1_t TCU_R932_1; + ESC_04_t ESC_04; + BCM_EEM_t BCM_EEM; + ACU_01_t ACU_01; + BCM_ExteriorLightState_t BCM_ExteriorLightState; + BCM_StyleCmd1_t BCM_StyleCmd1; + DMFL_Msg1_t DMFL_Msg1; + DMRL_Msg1_t DMRL_Msg1; + DMRR_Msg1_t DMRR_Msg1; + VAU2_Msg2_t VAU2_Msg2; + BCM_VEH_STATE_t BCM_VEH_STATE; + BCM_Veh_State2_t BCM_Veh_State2; + BCM_ALS_Light_Front_t BCM_ALS_Light_Front; + BCM_ALS_Light_Rear_t BCM_ALS_Light_Rear; + BCM_Rear_Plafond_Light_Data_t BCM_Rear_Plafond_Light_Data; + BCM_Lock_CTR_t BCM_Lock_CTR; + BCM_IC_Info_Msg_t BCM_IC_Info_Msg; + BCM_CLIMATIC_DATA_t BCM_CLIMATIC_DATA; + CCU_Msg1_t CCU_Msg1; + Sroof_State_t Sroof_State; + DocSL_T_FL_t DocSL_T_FL; + DocSR_T_FR_t DocSR_T_FR; + FIU_Cmd_t FIU_Cmd; + VEH_VIN_t VEH_VIN; + FIU_CTRL_DW_t FIU_CTRL_DW; + FIU_Msg1_t FIU_Msg1; + FIU_Msg2_t FIU_Msg2; + FIU_Msg3_t FIU_Msg3; + FIU_EngMenu_t FIU_EngMenu; + BCM_StyleCmd2_t BCM_StyleCmd2; + BCM_StyleCmd3_t BCM_StyleCmd3; + IC_DISPLAY_CLOCK_t IC_DISPLAY_CLOCK; + IntCOM_Info_Stat_t IntCOM_Info_Stat; + Diag_To_CCPF_t Diag_To_CCPF; + Diag_To_CCPR_t Diag_To_CCPR; + Diag_To_SSL_t Diag_To_SSL; + Diag_To_SSR_t Diag_To_SSR; + Diag_To_FCSilCU_t Diag_To_FCSilCU; + Diag_To_ICLSilCU_t Diag_To_ICLSilCU; + Diag_To_ICRSilCU_t Diag_To_ICRSilCU; + Diag_To_PLSilCU_t Diag_To_PLSilCU; + Diag_To_PRSilCU_t Diag_To_PRSilCU; + Diag_To_TM_t Diag_To_TM; + Diag_To_RCLSilCU_t Diag_To_RCLSilCU; + Diag_To_RCRSilCU_t Diag_To_RCRSilCU; + Diag_To_RDLSilCU_t Diag_To_RDLSilCU; + Diag_To_RDRSilCU_t Diag_To_RDRSilCU; + Diag_Functional_t Diag_Functional; +} tm_candb_rx_t; + +typedef struct +{ + TM_Stat_t TM_Stat; + TM_CP_t TM_CP; + PLDSilCU_State_t PLDSilCU_State; + PRDSilCU_State_t PRDSilCU_State; + ICLSilCU_State_t ICLSilCU_State; + ICRSilCU_State_t ICRSilCU_State; + RDRSilCU_State_t RDRSilCU_State; + FCSilCU_State_t FCSilCU_State; + RCLSilCU_State_t RCLSilCU_State; + RCRSilCU_State_t RCRSilCU_State; + RDLSilCU_State_t RDLSilCU_State; + CCPF_BodyTM_Stat_t CCPF_BodyTM_Stat; + SSL_Status_t SSL_Status; + SSR_Status_t SSR_Status; + Diag_From_CCPF_t Diag_From_CCPF; + Diag_From_CCPR_t Diag_From_CCPR; + Diag_From_SSL_t Diag_From_SSL; + Diag_From_SSR_t Diag_From_SSR; + Diag_From_FCSilCU_t Diag_From_FCSilCU; + Diag_From_ICLSilCU_t Diag_From_ICLSilCU; + Diag_From_ICRSilCU_t Diag_From_ICRSilCU; + Diag_From_PLSilCU_t Diag_From_PLSilCU; + Diag_From_PRSilCU_t Diag_From_PRSilCU; + Diag_From_TM_t Diag_From_TM; + Diag_From_RCLSilCU_t Diag_From_RCLSilCU; + Diag_From_RCRSilCU_t Diag_From_RCRSilCU; + Diag_From_RDLSilCU_t Diag_From_RDLSilCU; + Diag_From_RDRSilCU_t Diag_From_RDRSilCU; +} tm_candb_tx_t; + +uint32_t tm_candb_Receive(tm_candb_rx_t* m, const uint8_t* d, uint32_t msgid, uint8_t dlc); + +#ifdef __DEF_TM_CANDB__ + +extern tm_candb_rx_t tm_candb_rx; + +extern tm_candb_tx_t tm_candb_tx; + +#endif // __DEF_TM_CANDB__ + +#ifdef __cplusplus +} +#endif diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/vau_candb-binutil.c b/MODULES/HVAC_M7_CAN_MATRIX/butl/vau_candb-binutil.c new file mode 100644 index 0000000..a9ee9dd --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/vau_candb-binutil.c @@ -0,0 +1,125 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#include "vau_candb-binutil.h" + +// DBC file version +#if (VER_CANDB_MAJ != (0U)) || (VER_CANDB_MIN != (0U)) +#error The VAU_CANDB binutil source file has inconsistency with core dbc lib! +#endif + +#ifdef __DEF_VAU_CANDB__ + +vau_candb_rx_t vau_candb_rx; + +vau_candb_tx_t vau_candb_tx; + +#endif // __DEF_VAU_CANDB__ + +uint32_t vau_candb_Receive(vau_candb_rx_t* _m, const uint8_t* _d, uint32_t _id, uint8_t dlc_) +{ + uint32_t recid = 0; + if ((_id >= 0x88U) && (_id < 0x282U)) { + if ((_id >= 0x88U) && (_id < 0x243U)) { + if ((_id >= 0x88U) && (_id < 0xA0U)) { + if (_id == 0x88U) { + recid = Unpack_EMS_VCU_VAU_Immo_Req_candb(&(_m->EMS_VCU_VAU_Immo_Req), _d, dlc_); + } else { + if (_id == 0x8AU) { + recid = Unpack_TCU_VAU_Immo_Req_candb(&(_m->TCU_VAU_Immo_Req), _d, dlc_); + } else if (_id == 0x95U) { + recid = Unpack_WChF_NFC_VAU_Transfer_State_candb(&(_m->WChF_NFC_VAU_Transfer_State), _d, dlc_); + } + } + } else { + if (_id == 0xA0U) { + recid = Unpack_SDM_VAU_Hash_Resp_candb(&(_m->SDM_VAU_Hash_Resp), _d, dlc_); + } else { + if (_id == 0x152U) { + recid = Unpack_BCM_Powertrain_candb(&(_m->BCM_Powertrain), _d, dlc_); + } else if (_id == 0x242U) { + recid = Unpack_FIU_Access_Msg1_candb(&(_m->FIU_Access_Msg1), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x243U) && (_id < 0x246U)) { + if (_id == 0x243U) { + recid = Unpack_DMFR_Msg1_candb(&(_m->DMFR_Msg1), _d, dlc_); + } else { + if (_id == 0x244U) { + recid = Unpack_DMFL_Msg1_candb(&(_m->DMFL_Msg1), _d, dlc_); + } else if (_id == 0x245U) { + recid = Unpack_DMRL_Msg1_candb(&(_m->DMRL_Msg1), _d, dlc_); + } + } + } else { + if ((_id >= 0x246U) && (_id < 0x249U)) { + if (_id == 0x246U) { + recid = Unpack_DMRR_Msg1_candb(&(_m->DMRR_Msg1), _d, dlc_); + } else if (_id == 0x247U) { + recid = Unpack_TM_Stat_candb(&(_m->TM_Stat), _d, dlc_); + } + } else { + if (_id == 0x249U) { + recid = Unpack_PTG_Body_Stat_candb(&(_m->PTG_Body_Stat), _d, dlc_); + } else if (_id == 0x280U) { + recid = Unpack_BCM_VEH_STATE_candb(&(_m->BCM_VEH_STATE), _d, dlc_); + } + } + } + } + } else { + if ((_id >= 0x282U) && (_id < 0x521U)) { + if ((_id >= 0x282U) && (_id < 0x4B6U)) { + if (_id == 0x282U) { + recid = Unpack_BCM_Veh_State2_candb(&(_m->BCM_Veh_State2), _d, dlc_); + } else { + if (_id == 0x2F0U) { + recid = Unpack_BCM_Lock_CTR_candb(&(_m->BCM_Lock_CTR), _d, dlc_); + } else if (_id == 0x4B5U) { + recid = Unpack_FIU_Access_Msg2_candb(&(_m->FIU_Access_Msg2), _d, dlc_); + } + } + } else { + if (_id == 0x4B6U) { + recid = Unpack_FIU_Profile_candb(&(_m->FIU_Profile), _d, dlc_); + } else { + if (_id == 0x50BU) { + recid = Unpack_FIU_Cmd_candb(&(_m->FIU_Cmd), _d, dlc_); + } else if (_id == 0x51AU) { + recid = Unpack_VEH_VIN_candb(&(_m->VEH_VIN), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x521U) && (_id < 0x524U)) { + if (_id == 0x521U) { + recid = Unpack_OCUFL_MSG_candb(&(_m->OCUFL_MSG), _d, dlc_); + } else { + if (_id == 0x522U) { + recid = Unpack_OCUFR_MSG_candb(&(_m->OCUFR_MSG), _d, dlc_); + } else if (_id == 0x523U) { + recid = Unpack_OCURL_MSG_candb(&(_m->OCURL_MSG), _d, dlc_); + } + } + } else { + if ((_id >= 0x524U) && (_id < 0x7A0U)) { + if (_id == 0x524U) { + recid = Unpack_OCURR_MSG_candb(&(_m->OCURR_MSG), _d, dlc_); + } else if (_id == 0x5ACU) { + recid = Unpack_BCM_UserConfig_Stat_candb(&(_m->BCM_UserConfig_Stat), _d, dlc_); + } + } else { + if (_id == 0x7A0U) { + recid = Unpack_Diag_To_VAU_candb(&(_m->Diag_To_VAU), _d, dlc_); + } else if (_id == 0x7DFU) { + recid = Unpack_Diag_Functional_candb(&(_m->Diag_Functional), _d, dlc_); + } + } + } + } + } + + return recid; +} + diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/vau_candb-binutil.h b/MODULES/HVAC_M7_CAN_MATRIX/butl/vau_candb-binutil.h new file mode 100644 index 0000000..b19faa4 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/vau_candb-binutil.h @@ -0,0 +1,71 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dbccodeconf.h" + +#include "candb.h" + +typedef struct +{ + EMS_VCU_VAU_Immo_Req_t EMS_VCU_VAU_Immo_Req; + TCU_VAU_Immo_Req_t TCU_VAU_Immo_Req; + WChF_NFC_VAU_Transfer_State_t WChF_NFC_VAU_Transfer_State; + SDM_VAU_Hash_Resp_t SDM_VAU_Hash_Resp; + BCM_Powertrain_t BCM_Powertrain; + FIU_Access_Msg1_t FIU_Access_Msg1; + DMFR_Msg1_t DMFR_Msg1; + DMFL_Msg1_t DMFL_Msg1; + DMRL_Msg1_t DMRL_Msg1; + DMRR_Msg1_t DMRR_Msg1; + TM_Stat_t TM_Stat; + PTG_Body_Stat_t PTG_Body_Stat; + BCM_VEH_STATE_t BCM_VEH_STATE; + BCM_Veh_State2_t BCM_Veh_State2; + BCM_Lock_CTR_t BCM_Lock_CTR; + FIU_Access_Msg2_t FIU_Access_Msg2; + FIU_Profile_t FIU_Profile; + FIU_Cmd_t FIU_Cmd; + VEH_VIN_t VEH_VIN; + OCUFL_MSG_t OCUFL_MSG; + OCUFR_MSG_t OCUFR_MSG; + OCURL_MSG_t OCURL_MSG; + OCURR_MSG_t OCURR_MSG; + BCM_UserConfig_Stat_t BCM_UserConfig_Stat; + Diag_To_VAU_t Diag_To_VAU; + Diag_Functional_t Diag_Functional; +} vau_candb_rx_t; + +typedef struct +{ + VAU2_NFC_TransferState_t VAU2_NFC_TransferState; + VAU_TCU_Hash_Resp_t VAU_TCU_Hash_Resp; + VAU_EMS_VCU_Hash_Resp_t VAU_EMS_VCU_Hash_Resp; + VAU2_INVRL_Hash_Resp_t VAU2_INVRL_Hash_Resp; + VAU2_INVRR_Hash_Resp_t VAU2_INVRR_Hash_Resp; + VAU_SDM_Immo_Req_t VAU_SDM_Immo_Req; + VAU2_INVF_Hash_Resp_t VAU2_INVF_Hash_Resp; + VAU2_Msg1_t VAU2_Msg1; + VAU2_Msg2_t VAU2_Msg2; + VAU_TPMS_Msg_t VAU_TPMS_Msg; + VAU_BLE_Device_t VAU_BLE_Device; + Diag_From_VAU_t Diag_From_VAU; +} vau_candb_tx_t; + +uint32_t vau_candb_Receive(vau_candb_rx_t* m, const uint8_t* d, uint32_t msgid, uint8_t dlc); + +#ifdef __DEF_VAU_CANDB__ + +extern vau_candb_rx_t vau_candb_rx; + +extern vau_candb_tx_t vau_candb_tx; + +#endif // __DEF_VAU_CANDB__ + +#ifdef __cplusplus +} +#endif diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/vector__xxx_candb-binutil.c b/MODULES/HVAC_M7_CAN_MATRIX/butl/vector__xxx_candb-binutil.c new file mode 100644 index 0000000..1d49452 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/vector__xxx_candb-binutil.c @@ -0,0 +1,219 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#include "vector__xxx_candb-binutil.h" + +// DBC file version +#if (VER_CANDB_MAJ != (0U)) || (VER_CANDB_MIN != (0U)) +#error The VECTOR__XXX_CANDB binutil source file has inconsistency with core dbc lib! +#endif + +#ifdef __DEF_VECTOR__XXX_CANDB__ + +vector__xxx_candb_rx_t vector__xxx_candb_rx; + +#endif // __DEF_VECTOR__XXX_CANDB__ + +uint32_t vector__xxx_candb_Receive(vector__xxx_candb_rx_t* _m, const uint8_t* _d, uint32_t _id, uint8_t dlc_) +{ + uint32_t recid = 0; + if ((_id >= 0xB1U) && (_id < 0x3AAU)) { + if ((_id >= 0xB1U) && (_id < 0x20AU)) { + if ((_id >= 0xB1U) && (_id < 0x150U)) { + if ((_id >= 0xB1U) && (_id < 0x100U)) { + if (_id == 0xB1U) { + recid = Unpack_TCU_R932_1_candb(&(_m->TCU_R932_1), _d, dlc_); + } else { + if (_id == 0xE4U) { + recid = Unpack_FTCU_DAT2_candb(&(_m->FTCU_DAT2), _d, dlc_); + } else if (_id == 0xE5U) { + recid = Unpack_FTCU_DAT3_candb(&(_m->FTCU_DAT3), _d, dlc_); + } + } + } else { + if (_id == 0x100U) { + recid = Unpack_ESC_04_candb(&(_m->ESC_04), _d, dlc_); + } else { + if (_id == 0x112U) { + recid = Unpack_ESC_09_candb(&(_m->ESC_09), _d, dlc_); + } else if (_id == 0x130U) { + recid = Unpack_ESC_YRS_01_candb(&(_m->ESC_YRS_01), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x150U) && (_id < 0x160U)) { + if (_id == 0x150U) { + recid = Unpack_EMS_Veh_candb(&(_m->EMS_Veh), _d, dlc_); + } else { + if (_id == 0x151U) { + recid = Unpack_EMS_Indicators_candb(&(_m->EMS_Indicators), _d, dlc_); + } else if (_id == 0x153U) { + recid = Unpack_EMS_Veh_02_candb(&(_m->EMS_Veh_02), _d, dlc_); + } + } + } else { + if (_id == 0x160U) { + recid = Unpack_DAS_01_candb(&(_m->DAS_01), _d, dlc_); + } else { + if (_id == 0x162U) { + recid = Unpack_DAS_04_candb(&(_m->DAS_04), _d, dlc_); + } else if (_id == 0x18AU) { + recid = Unpack_VCU_DriveInfo_candb(&(_m->VCU_DriveInfo), _d, dlc_); + } + } + } + } + } else { + if ((_id >= 0x20AU) && (_id < 0x247U)) { + if ((_id >= 0x20AU) && (_id < 0x238U)) { + if (_id == 0x20AU) { + recid = Unpack_DAS_02_candb(&(_m->DAS_02), _d, dlc_); + } else { + if (_id == 0x210U) { + recid = Unpack_ACU_01_candb(&(_m->ACU_01), _d, dlc_); + } else if (_id == 0x21AU) { + recid = Unpack_EPB_Status_candb(&(_m->EPB_Status), _d, dlc_); + } + } + } else { + if (_id == 0x238U) { + recid = Unpack_SWM_ContrlsState_candb(&(_m->SWM_ContrlsState), _d, dlc_); + } else { + if (_id == 0x242U) { + recid = Unpack_FIU_Access_Msg1_candb(&(_m->FIU_Access_Msg1), _d, dlc_); + } else if (_id == 0x243U) { + recid = Unpack_DMFR_Msg1_candb(&(_m->DMFR_Msg1), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x247U) && (_id < 0x282U)) { + if (_id == 0x247U) { + recid = Unpack_TM_Stat_candb(&(_m->TM_Stat), _d, dlc_); + } else { + if (_id == 0x277U) { + recid = Unpack_ATS_Status_candb(&(_m->ATS_Status), _d, dlc_); + } else if (_id == 0x280U) { + recid = Unpack_BCM_VEH_STATE_candb(&(_m->BCM_VEH_STATE), _d, dlc_); + } + } + } else { + if ((_id >= 0x282U) && (_id < 0x2B0U)) { + if (_id == 0x282U) { + recid = Unpack_BCM_Veh_State2_candb(&(_m->BCM_Veh_State2), _d, dlc_); + } else if (_id == 0x298U) { + recid = Unpack_EMS_HVC_Req_Msg_candb(&(_m->EMS_HVC_Req_Msg), _d, dlc_); + } + } else { + if (_id == 0x2B0U) { + recid = Unpack_SAS_Standard_candb(&(_m->SAS_Standard), _d, dlc_); + } else if (_id == 0x314U) { + recid = Unpack_CCU_Stat3_candb(&(_m->CCU_Stat3), _d, dlc_); + } + } + } + } + } + } else { + if ((_id >= 0x3AAU) && (_id < 0x536U)) { + if ((_id >= 0x3AAU) && (_id < 0x4C0U)) { + if ((_id >= 0x3AAU) && (_id < 0x4B0U)) { + if (_id == 0x3AAU) { + recid = Unpack_IC_DATA_MSG_candb(&(_m->IC_DATA_MSG), _d, dlc_); + } else { + if (_id == 0x3D0U) { + recid = Unpack_MAS_Status_candb(&(_m->MAS_Status), _d, dlc_); + } else if (_id == 0x4AFU) { + recid = Unpack_DCDC1248_01_candb(&(_m->DCDC1248_01), _d, dlc_); + } + } + } else { + if (_id == 0x4B0U) { + recid = Unpack_FIU_REQ_CTR_01_candb(&(_m->FIU_REQ_CTR_01), _d, dlc_); + } else { + if (_id == 0x4B1U) { + recid = Unpack_DCDC1248_02_candb(&(_m->DCDC1248_02), _d, dlc_); + } else if (_id == 0x4B6U) { + recid = Unpack_FIU_Profile_candb(&(_m->FIU_Profile), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x4C0U) && (_id < 0x50FU)) { + if (_id == 0x4C0U) { + recid = Unpack_USBSw_Stat_candb(&(_m->USBSw_Stat), _d, dlc_); + } else { + if (_id == 0x4FEU) { + recid = Unpack_CCU_Errors_candb(&(_m->CCU_Errors), _d, dlc_); + } else if (_id == 0x50BU) { + recid = Unpack_FIU_Cmd_candb(&(_m->FIU_Cmd), _d, dlc_); + } + } + } else { + if (_id == 0x50FU) { + recid = Unpack_SDM_Cmd_candb(&(_m->SDM_Cmd), _d, dlc_); + } else { + if (_id == 0x511U) { + recid = Unpack_HUD_MSG_STATUS_candb(&(_m->HUD_MSG_STATUS), _d, dlc_); + } else if (_id == 0x52CU) { + recid = Unpack_FIU_SMRL_REQ_CTR_SEATS_candb(&(_m->FIU_SMRL_REQ_CTR_SEATS), _d, dlc_); + } + } + } + } + } else { + if ((_id >= 0x536U) && (_id < 0x5ACU)) { + if ((_id >= 0x536U) && (_id < 0x58EU)) { + if (_id == 0x536U) { + recid = Unpack_BCM_MEM_SMFL2_candb(&(_m->BCM_MEM_SMFL2), _d, dlc_); + } else { + if (_id == 0x554U) { + recid = Unpack_FIU_SMRR_REQ_CTR_SEATS_candb(&(_m->FIU_SMRR_REQ_CTR_SEATS), _d, dlc_); + } else if (_id == 0x587U) { + recid = Unpack_FIU_CTRL_DW_candb(&(_m->FIU_CTRL_DW), _d, dlc_); + } + } + } else { + if (_id == 0x58EU) { + recid = Unpack_FIU_Msg1_candb(&(_m->FIU_Msg1), _d, dlc_); + } else { + if (_id == 0x590U) { + recid = Unpack_ERAG_DATA_MSG_candb(&(_m->ERAG_DATA_MSG), _d, dlc_); + } else if (_id == 0x594U) { + recid = Unpack_FIU_Msg3_candb(&(_m->FIU_Msg3), _d, dlc_); + } + } + } + } else { + if ((_id >= 0x5ACU) && (_id < 0x5B2U)) { + if (_id == 0x5ACU) { + recid = Unpack_BCM_UserConfig_Stat_candb(&(_m->BCM_UserConfig_Stat), _d, dlc_); + } else { + if (_id == 0x5ADU) { + recid = Unpack_FIU_MAS_Main_candb(&(_m->FIU_MAS_Main), _d, dlc_); + } else if (_id == 0x5B1U) { + recid = Unpack_MAS_APA_Paths_candb(&(_m->MAS_APA_Paths), _d, dlc_); + } + } + } else { + if ((_id >= 0x5B2U) && (_id < 0x5F3U)) { + if (_id == 0x5B2U) { + recid = Unpack_MAS_APA_ParkPlace_candb(&(_m->MAS_APA_ParkPlace), _d, dlc_); + } else if (_id == 0x5EFU) { + recid = Unpack_CCPF_BodyTM_Stat_candb(&(_m->CCPF_BodyTM_Stat), _d, dlc_); + } + } else { + if (_id == 0x5F3U) { + recid = Unpack_IntCOM_Info_Stat_candb(&(_m->IntCOM_Info_Stat), _d, dlc_); + } else if (_id == 0x730U) { + recid = Unpack_Diag_To_APU_candb(&(_m->Diag_To_APU), _d, dlc_); + } + } + } + } + } + } + + return recid; +} + diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/vector__xxx_candb-binutil.h b/MODULES/HVAC_M7_CAN_MATRIX/butl/vector__xxx_candb-binutil.h new file mode 100644 index 0000000..29b93a6 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/vector__xxx_candb-binutil.h @@ -0,0 +1,79 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dbccodeconf.h" + +#include "candb.h" + +typedef struct +{ + TCU_R932_1_t TCU_R932_1; + FTCU_DAT2_t FTCU_DAT2; + FTCU_DAT3_t FTCU_DAT3; + ESC_04_t ESC_04; + ESC_09_t ESC_09; + ESC_YRS_01_t ESC_YRS_01; + EMS_Veh_t EMS_Veh; + EMS_Indicators_t EMS_Indicators; + EMS_Veh_02_t EMS_Veh_02; + DAS_01_t DAS_01; + DAS_04_t DAS_04; + VCU_DriveInfo_t VCU_DriveInfo; + DAS_02_t DAS_02; + ACU_01_t ACU_01; + EPB_Status_t EPB_Status; + SWM_ContrlsState_t SWM_ContrlsState; + FIU_Access_Msg1_t FIU_Access_Msg1; + DMFR_Msg1_t DMFR_Msg1; + TM_Stat_t TM_Stat; + ATS_Status_t ATS_Status; + BCM_VEH_STATE_t BCM_VEH_STATE; + BCM_Veh_State2_t BCM_Veh_State2; + EMS_HVC_Req_Msg_t EMS_HVC_Req_Msg; + SAS_Standard_t SAS_Standard; + CCU_Stat3_t CCU_Stat3; + IC_DATA_MSG_t IC_DATA_MSG; + MAS_Status_t MAS_Status; + DCDC1248_01_t DCDC1248_01; + FIU_REQ_CTR_01_t FIU_REQ_CTR_01; + DCDC1248_02_t DCDC1248_02; + FIU_Profile_t FIU_Profile; + USBSw_Stat_t USBSw_Stat; + CCU_Errors_t CCU_Errors; + FIU_Cmd_t FIU_Cmd; + SDM_Cmd_t SDM_Cmd; + HUD_MSG_STATUS_t HUD_MSG_STATUS; + FIU_SMRL_REQ_CTR_SEATS_t FIU_SMRL_REQ_CTR_SEATS; + BCM_MEM_SMFL2_t BCM_MEM_SMFL2; + FIU_SMRR_REQ_CTR_SEATS_t FIU_SMRR_REQ_CTR_SEATS; + FIU_CTRL_DW_t FIU_CTRL_DW; + FIU_Msg1_t FIU_Msg1; + ERAG_DATA_MSG_t ERAG_DATA_MSG; + FIU_Msg3_t FIU_Msg3; + BCM_UserConfig_Stat_t BCM_UserConfig_Stat; + FIU_MAS_Main_t FIU_MAS_Main; + MAS_APA_Paths_t MAS_APA_Paths; + MAS_APA_ParkPlace_t MAS_APA_ParkPlace; + CCPF_BodyTM_Stat_t CCPF_BodyTM_Stat; + IntCOM_Info_Stat_t IntCOM_Info_Stat; + Diag_To_APU_t Diag_To_APU; +} vector__xxx_candb_rx_t; + +// There is no any TX mapped massage. + +uint32_t vector__xxx_candb_Receive(vector__xxx_candb_rx_t* m, const uint8_t* d, uint32_t msgid, uint8_t dlc); + +#ifdef __DEF_VECTOR__XXX_CANDB__ + +extern vector__xxx_candb_rx_t vector__xxx_candb_rx; + +#endif // __DEF_VECTOR__XXX_CANDB__ + +#ifdef __cplusplus +} +#endif diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/wch_candb-binutil.c b/MODULES/HVAC_M7_CAN_MATRIX/butl/wch_candb-binutil.c new file mode 100644 index 0000000..851ccc4 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/wch_candb-binutil.c @@ -0,0 +1,57 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#include "wch_candb-binutil.h" + +// DBC file version +#if (VER_CANDB_MAJ != (0U)) || (VER_CANDB_MIN != (0U)) +#error The WCH_CANDB binutil source file has inconsistency with core dbc lib! +#endif + +#ifdef __DEF_WCH_CANDB__ + +wch_candb_rx_t wch_candb_rx; + +wch_candb_tx_t wch_candb_tx; + +#endif // __DEF_WCH_CANDB__ + +uint32_t wch_candb_Receive(wch_candb_rx_t* _m, const uint8_t* _d, uint32_t _id, uint8_t dlc_) +{ + uint32_t recid = 0; + if ((_id >= 0x8EU) && (_id < 0x280U)) { + if ((_id >= 0x8EU) && (_id < 0x157U)) { + if (_id == 0x8EU) { + recid = Unpack_VAU2_NFC_TransferState_candb(&(_m->VAU2_NFC_TransferState), _d, dlc_); + } else if (_id == 0x121U) { + recid = Unpack_VAU2_Msg1_candb(&(_m->VAU2_Msg1), _d, dlc_); + } + } else { + if (_id == 0x157U) { + recid = Unpack_BCM_EEM_candb(&(_m->BCM_EEM), _d, dlc_); + } else if (_id == 0x24FU) { + recid = Unpack_VAU2_Msg2_candb(&(_m->VAU2_Msg2), _d, dlc_); + } + } + } else { + if ((_id >= 0x280U) && (_id < 0x5F7U)) { + if (_id == 0x280U) { + recid = Unpack_BCM_VEH_STATE_candb(&(_m->BCM_VEH_STATE), _d, dlc_); + } else if (_id == 0x51AU) { + recid = Unpack_VEH_VIN_candb(&(_m->VEH_VIN), _d, dlc_); + } + } else { + if (_id == 0x5F7U) { + recid = Unpack_LTE_Sum_State2_candb(&(_m->LTE_Sum_State2), _d, dlc_); + } else { + if (_id == 0x604U) { + recid = Unpack_FIU_WChF_TransferState_candb(&(_m->FIU_WChF_TransferState), _d, dlc_); + } else if (_id == 0x7DFU) { + recid = Unpack_Diag_Functional_candb(&(_m->Diag_Functional), _d, dlc_); + } + } + } + } + + return recid; +} + diff --git a/MODULES/HVAC_M7_CAN_MATRIX/butl/wch_candb-binutil.h b/MODULES/HVAC_M7_CAN_MATRIX/butl/wch_candb-binutil.h new file mode 100644 index 0000000..c9cb5e2 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/butl/wch_candb-binutil.h @@ -0,0 +1,45 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dbccodeconf.h" + +#include "candb.h" + +typedef struct +{ + VAU2_NFC_TransferState_t VAU2_NFC_TransferState; + VAU2_Msg1_t VAU2_Msg1; + BCM_EEM_t BCM_EEM; + VAU2_Msg2_t VAU2_Msg2; + BCM_VEH_STATE_t BCM_VEH_STATE; + VEH_VIN_t VEH_VIN; + LTE_Sum_State2_t LTE_Sum_State2; + FIU_WChF_TransferState_t FIU_WChF_TransferState; + Diag_Functional_t Diag_Functional; +} wch_candb_rx_t; + +typedef struct +{ + WChF_NFC_VAU_Transfer_State_t WChF_NFC_VAU_Transfer_State; + WChF_Status_t WChF_Status; + WChF_FIU_TransferState_t WChF_FIU_TransferState; +} wch_candb_tx_t; + +uint32_t wch_candb_Receive(wch_candb_rx_t* m, const uint8_t* d, uint32_t msgid, uint8_t dlc); + +#ifdef __DEF_WCH_CANDB__ + +extern wch_candb_rx_t wch_candb_rx; + +extern wch_candb_tx_t wch_candb_tx; + +#endif // __DEF_WCH_CANDB__ + +#ifdef __cplusplus +} +#endif diff --git a/MODULES/HVAC_M7_CAN_MATRIX/conf/candb-config.h b/MODULES/HVAC_M7_CAN_MATRIX/conf/candb-config.h new file mode 100644 index 0000000..1f3b6b6 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/conf/candb-config.h @@ -0,0 +1,131 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#pragma once + +/* include common dbccode configurations */ +#include "dbccodeconf.h" + +#define __DEF_CCU_CANDB__ + +/* ------------------------------------------------------------------------- * + This define enables using CAN message structs with bit-fielded signals + layout. + + Note(!): bit-feild was not tested properly. */ + +/* #define CANDB_USE_BITS_SIGNAL */ + + +/* ------------------------------------------------------------------------- * + This macro enables using CAN message descriptive struct packing functions + (by default signature of pack function intakes a few simple typed params + for loading data, len, etc). To compile you need to define the struct + __CoderDbcCanFrame_t__ which must have fields: + + u32 MsgId (CAN Frame message ID) + u8 DLC (CAN Frame payload length field) + u8 Data[8] (CAN Frame payload data) + u8 IDE (CAN Frame Extended (1) / Standard (0) ID type) + + This struct definition have to be placed (or be included) in dbccodeconf.h */ + +/* #define CANDB_USE_CANSTRUCT */ + + +/* ------------------------------------------------------------------------- * + All the signals which have values of factor != 1 or offset != 0 + will be named in message struct with posfix '_ro'. Pack to payload + operations will be made on this signal value as well as unpack from payload. + + USE_SIGFLOAT macro makes some difference: + + 1. All the '_ro' fields will have a pair field with '_phys' postfix. + If only offset != 0 is true then the type of '_phys' signal is the same + as '_ro' signal. In other case the type will be @sigfloat_t which + have to be defined in user dbccodeconf.h + + 2. In pack function '_ro' signal will be rewritten by '_phys' signal, which + requires from user to use ONLY '_phys' signal for packing frame + + 3. In unpack function '_phys' signal will be written by '_ro' signal. + User have to use '_phys' signal to read physical value. */ + +/* #define CANDB_USE_SIGFLOAT */ + + +/* ------------------------------------------------------------------------- * + Note(!) that the "canmonitorutil.h" must be accessed in include path: + + This macro adds: + + - monitor field @mon1 to message struct + + - capture system tick in unpack function and save value to mon1 field + to provide to user better missing frame detection code. For this case + user must provide function declared in canmonitorutil.h - GetSysTick() + which may return 1ms uptime. + + - calling function FMon_*** (from 'fmon' driver) inside unpack function + which is empty by default and have to be filled by user if + tests for DLC, rolling, checksum are necessary */ + + //#define CANDB_USE_DIAG_MONITORS + + +/* ------------------------------------------------------------------------- * + When monitor using is enabled (CANDB_USE_DIAG_MONITORS) and define below + uncommented, additional signal will be added to message struct. ***_expt: + expected rolling counter, to perform monitoring rolling counter sequence + automatically (result may be tested in dedicated Fmon_*** function) */ + +/* #define CANDB_AUTO_ROLL */ + + +/* ------------------------------------------------------------------------- * + When monitor using is enabled (CANDB_USE_DIAG_MONITORS) and define below + uncommented, frame checksum signal may be handled automatically. + + The signal which may be marked as checksum signal must have substring + with next format: + + + where: + + - "Checksum": constant marker word + + - "XOR8": type of method, this text will be passed to GetFrameHash + (canmonitorutil.h) function as is, the best use case is to define 'enum + DbcCanCrcMethods' in canmonitorutil.h file with all possible + checksum algorithms (e.g. XOR8, XOR4 etc) + + - "3": optional value that will be passed to GetFrameHash as integer value + + Function GetFrameHash have to be implemented by user + + In pack function checksum signal will be calculated automatically + and loaded to payload + + In unpack function checksum signal is checked with calculated. + (result may be tested in dedicated Fmon_*** function). */ + +/* #define CANDB_AUTO_CSM */ + + +/* ------------------------------------------------------------------------- * + FMon handling model can be build in two ways: + + 1 - Default. In this case when specific frame unpack is called the + specific FMon_{Frame name}_{driver name} functoin will be called. + User's code scope has to define each of these functions. Each function is + responsible for the error handling of one frame + + 2 - MONO. In this case there is only one function to perform any frame + monitoring. This function has to be implemented in the user's code scope. + This function is named as FMon_MONO_{driver name}. It takes frame id + which can be used for selection of the logic for a frame monitoring. + This mode costs a bit more in runtime but when you often edit you DBC and you + have more than one project it could be more maintanable (there is + no necessity to replace source code) + + For using MONO way uncomment line below */ +/* #define CANDB_USE_MONO_FMON */ diff --git a/MODULES/HVAC_M7_CAN_MATRIX/conf/dbccodeconf.h b/MODULES/HVAC_M7_CAN_MATRIX/conf/dbccodeconf.h new file mode 100644 index 0000000..5f62b7c --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/conf/dbccodeconf.h @@ -0,0 +1,33 @@ +// Generator version : v3.1 +#pragma once + +#include +#include "SystemDelayInterface.h" + +// when USE_SIGFLOAT enabed the sigfloat_t must be defined +// typedef double sigfloat_t; + +// when USE_CANSTRUCT enabled __CoderDbcCanFrame_t__ must be defined +// #include "{header_with_can_struct}" +// typedef {can_struct} __CoderDbcCanFrame_t__; + +// if you need to allocate rx and tx messages structs put the allocation macro here +// #define __DEF_{your_driver_name}__ + +// defualt @__ext_sig__ help types definition + +typedef uint32_t ubitext_t; +typedef int32_t bitext_t; + +// To provide a way to make missing control correctly you +// have to define macro @GetSystemTick() which has to +// return kind of tick counter (e.g. 1 ms ticker) + +// #define GetSystemTick() __get__tick__() + #define GetSystemTick() (uint32_t)SystemGetMs() + +// To provide a way to calculate hash (crc) for CAN +// frame's data field you have to define macro @GetFrameHash + +// #define GetFrameHash(a,b,c,d,e) __get_hash__(a,b,c,d,e) + diff --git a/MODULES/HVAC_M7_CAN_MATRIX/inc/canmonitorutil.h b/MODULES/HVAC_M7_CAN_MATRIX/inc/canmonitorutil.h new file mode 100644 index 0000000..2289caa --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/inc/canmonitorutil.h @@ -0,0 +1,54 @@ +// Generator version : v3.1 +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +// declare here all availible checksum algorithms +typedef enum +{ + // XOR8 = 0, + // XOR4 = 1, + // etc + + // it is up to user to have or to skip final enum value - @CRC_ALG_COUNT + CRC_ALG_COUNT +} DbcCanCrcMethods; + +typedef struct +{ + // @last_cycle keeps tick-value when last frame was received + uint32_t last_cycle; + + // @timeout_cycle keeps maximum timeout for frame, user responsibility + // to init this field and use it in missing frame monitoring function + uint32_t timeout_cycle; + + // @frame_cnt keeps count of all the received frames + uint32_t frame_cnt; + + // setting up @roll_error bit indicates roll counting fail. + // Bit is not clearing automatically! + uint32_t roll_error : 1; + + // setting up @checksum_error bit indicates checksum checking failure. + // Bit is not clearing automatically! + uint32_t csm_error : 1; + + // setting up @cycle_error bit indicates that time was overrunned. + // Bit is not clearing automatically! + uint32_t cycle_error : 1; + + // setting up @dlc_error bit indicates that the actual length of + // CAN frame is less then defined by CAN matrix! + uint32_t dlc_error : 1; + +} FrameMonitor_t; + +#ifdef __cplusplus +} +#endif + diff --git a/MODULES/HVAC_M7_CAN_MATRIX/lib/candb-fmon.h b/MODULES/HVAC_M7_CAN_MATRIX/lib/candb-fmon.h new file mode 100644 index 0000000..62293f2 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/lib/candb-fmon.h @@ -0,0 +1,838 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +// DBC file version +#define VER_CANDB_MAJ_FMON (0U) +#define VER_CANDB_MIN_FMON (0U) + +#include "candb-config.h" + +#ifdef CANDB_USE_DIAG_MONITORS + +#include "canmonitorutil.h" +/* +This file contains the prototypes of all the functions that will be called +from each Unpack_*name* function to detect DBC related errors +It is the user responsibility to defined these functions in the +separated .c file. If it won't be done the linkage error will happen +*/ + +#ifdef CANDB_USE_MONO_FMON + +void _FMon_MONO_candb(FrameMonitor_t* _mon, uint32_t msgid); + +#define FMon_SDM_MAS_Req_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_EMS_VCU_VAU_Immo_Req_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_TCU_VAU_Immo_Req_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_VAU2_NFC_TransferState_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_VAU_TCU_Hash_Resp_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_VAU_EMS_VCU_Hash_Resp_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_VAU2_INVRL_Hash_Resp_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_WChF_NFC_VAU_Transfer_State_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_VAU2_INVRR_Hash_Resp_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_VAU_SDM_Immo_Req_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_SDM_VAU_Hash_Resp_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_TCU_R932_1_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_VAU2_INVF_Hash_Resp_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_FTCU_DAT1_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_FTCU_DAT2_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_FTCU_DAT3_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_SCU_02_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_ESC_04_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_ESC_09_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_VAU2_Msg1_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_ESC_YRS_01_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_EMS_Veh_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_EMS_Indicators_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_BCM_Powertrain_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_EMS_Veh_02_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_EMS_EEM_01_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_EMS_EEM_02_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_BCM_EEM_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_DAS_01_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_DAS_04_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_VCU_DriveInfo_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_DAS_02_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_DAS_07_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_ACU_01_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_EPB_Status_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_BCM_ExteriorLightState_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_SWM_ContrlsState_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_BCM_StyleCmd1_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_FIU_Access_Msg1_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_DMFR_Msg1_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_DMFL_Msg1_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_DMRL_Msg1_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_DMRR_Msg1_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_TM_Stat_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_PTG_Body_Stat_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_TM_CP_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_VAU2_Msg2_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_BCM_DMS_01_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_LB_pSilCU_State_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_RB_pSilCU_State_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_HVC_CCU_Status_Msg_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_ATS_Status_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_BCM_VEH_STATE_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_BCM_Veh_State2_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_BCM_ALS_Light_Front_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_BCM_ALS_Light_Rear_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_BCM_Rear_Plafond_Light_Data_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_EMS_HVC_Req_Msg_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_SAS_Standard_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_IC_ABSOLUTE_CLOCK_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_BCM_Lock_CTR_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_HVC_Err_Status_Msg_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_BCM_DCDC12_CNTRL_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_CCU_HVC_Req_Msg_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_CCU_Stat1_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_CCU_Stat2_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_CCU_Requests_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_CCU_Stat3_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_CCU_VCU_Msg1_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_CCU_VCU_Msg2_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_BCM_IC_Info_Msg_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_BCM_CLIMATIC_DATA_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_DMFL_SMFL_REQ_CTR_SEATS_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_DMFR_SMFR_REQ_CTR_SEATS_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_DMRL_SMRL_REQ_CTR_SEATS_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_DMRR_SMRR_REQ_CTR_SEATS_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_CCU_Msg1_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Sroof_State_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_VCU_CCU_Req_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_IC_DATA_MSG_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_ESC_08_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_WChF_Status_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_MAS_Status_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_EPB_VM_MSG_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_CGW_COMM_REQ_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_DCDC1248_01_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_FIU_REQ_CTR_01_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_DCDC1248_02_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_FIU_Access_Msg2_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_FIU_Profile_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_USBSw_Stat_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_SMFL_status_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_SMFR_status_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_SMRL_status_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_SMRR_status_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_DocSL_T_FL_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_DocSR_T_FR_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_VAU_TPMS_Msg_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_CCU_Errors_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_CCU_Msg3_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_FIU_Cmd_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_IC_SDM_Info_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_SDM_Cmd_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_HUD_MSG_STATUS_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_IC_SDM_Info_02_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_IC_Milleage_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_VEH_VIN_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_BCM_RunningBoards_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_OCUFL_MSG_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_OCUFR_MSG_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_OCURL_MSG_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_OCURR_MSG_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_RBCU_BODY_Stat_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_FIU_SMRL_REQ_CTR_SEATS_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_FIU_SMFR_REQ_CTR_SEATS_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_SMFL_MEM1_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_BCM_MEM_SMFL1_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_SMFL_MEM2_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_BCM_MEM_SMFL2_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_SMFR_MEM1_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_BCM_MEM_SMFR1_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_SMFR_MEM2_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_BCM_MEM_SMFR2_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_SMRL_MEM1_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_BCM_MEM_SMRL1_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_SMRL_MEM2_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_BCM_MEM_SMRL2_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_SMRR_MEM1_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_BCM_MEM_SMRR1_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_SMRR_MEM2_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_BCM_MEM_SMRR2_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_FIU_SMFL_REQ_CTR_SEATS_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_FIU_SMRR_REQ_CTR_SEATS_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_FIU_CTRL_DW_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_DW_STATE_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_FIU_Msg1_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_FIU_Msg2_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_ERAG_DATA_MSG_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_FIU_Msg3_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_FIU_EngMenu_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_WHFL_MSG1_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_WHFR_Msg1_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_PLDSilCU_State_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_PRDSilCU_State_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_FLDSilCU_State_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_FRDSilCU_State_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_RLDSilCU_State_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_RRDSilCU_State_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_FIU_CCU1_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_FIU_CCU2_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_FIU_CCU3_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_BCM_StyleCmd2_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_BCM_StyleCmd3_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_BCM_WHF_Request_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_IC_DISPLAY_CLOCK_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_BCM_UserConfig_Stat_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_FIU_MAS_Main_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_MAS_APA_Paths_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_MAS_APA_ParkPlace_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_ICLSilCU_State_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_ICRSilCU_State_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_SFRSilCU_State_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_SFLSilCU_State_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_RDRSilCU_State_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_FCSilCU_State_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_RCLSilCU_State_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_RCRSilCU_State_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_RDLSilCU_State_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_CCPF_BodyTM_Stat_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_IntCOM_Info_Stat_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_LTE_Sum_State2_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_WChF_FIU_TransferState_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_FIU_WChF_TransferState_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_VAU_BLE_Device_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_APU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_SSL_Status_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_SSR_Status_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_PTG_To_SupplierTool_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_SupplierTool_To_PTG_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_CCPF_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_CCPF_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_CCPR_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_CCPR_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_SSL_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_SSR_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_SSL_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_FCSilCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_SSR_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_FLDSilCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_FRDSilCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_ICLSilCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_FCSilCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_FLDSilCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_FRDSilCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_ICLSilCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_APU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_FTCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_FTCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_Sroof_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_SRoof_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_ICRSilCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_LB_pSilCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_PLSilCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_PRSilCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_RB_pSilCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_ICRSilCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_LB_pSilCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_PLSilCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_PRSilCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_RB_pSilCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_VAU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_BCM_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_DMFL_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_DMFR_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_DMRL_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_DMRR_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_SMRR_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_TM_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_CCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_SMFL_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_SMFR_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_SMRL_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_VAU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_BCM_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_DMFL_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_DMFR_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_DMRL_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_DMRR_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_SMRR_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_TM_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_CCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_SMFL_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_SMFR_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_SMRL_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_RCLSilCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_RCRSilCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_RDLSilCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_RDRSilCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_OCUFL_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_RLDSilCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_RRDSilCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_PTG_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_OCUFR_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_OCURL_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_OCURR_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_RCLSilCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_RCRSilCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_RDLSilCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_RDRSilCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_OCUFL_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_RLDSilCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_RRDSilCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_PTG_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_OCUFR_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_OCURL_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_OCURR_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_Functional_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_SFRSilCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_SFLSilCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_WHFL_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_To_WHFR_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_SFRSilCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_SFLSilCU_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_WHFL_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_Diag_From_WHFR_candb(x, y) _FMon_MONO_candb((x), (y)) +#define FMon_CCU_AC_Ctrl_candb(x, y) _FMon_MONO_candb((x), (y)) + +#else + +void _FMon_SDM_MAS_Req_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_EMS_VCU_VAU_Immo_Req_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_TCU_VAU_Immo_Req_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_VAU2_NFC_TransferState_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_VAU_TCU_Hash_Resp_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_VAU_EMS_VCU_Hash_Resp_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_VAU2_INVRL_Hash_Resp_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_WChF_NFC_VAU_Transfer_State_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_VAU2_INVRR_Hash_Resp_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_VAU_SDM_Immo_Req_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_SDM_VAU_Hash_Resp_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_TCU_R932_1_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_VAU2_INVF_Hash_Resp_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_FTCU_DAT1_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_FTCU_DAT2_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_FTCU_DAT3_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_SCU_02_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_ESC_04_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_ESC_09_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_VAU2_Msg1_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_ESC_YRS_01_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_EMS_Veh_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_EMS_Indicators_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_BCM_Powertrain_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_EMS_Veh_02_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_EMS_EEM_01_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_EMS_EEM_02_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_BCM_EEM_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_DAS_01_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_DAS_04_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_VCU_DriveInfo_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_DAS_02_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_DAS_07_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_ACU_01_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_EPB_Status_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_BCM_ExteriorLightState_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_SWM_ContrlsState_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_BCM_StyleCmd1_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_FIU_Access_Msg1_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_DMFR_Msg1_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_DMFL_Msg1_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_DMRL_Msg1_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_DMRR_Msg1_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_TM_Stat_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_PTG_Body_Stat_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_TM_CP_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_VAU2_Msg2_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_BCM_DMS_01_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_LB_pSilCU_State_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_RB_pSilCU_State_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_HVC_CCU_Status_Msg_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_ATS_Status_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_BCM_VEH_STATE_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_BCM_Veh_State2_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_BCM_ALS_Light_Front_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_BCM_ALS_Light_Rear_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_BCM_Rear_Plafond_Light_Data_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_EMS_HVC_Req_Msg_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_SAS_Standard_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_IC_ABSOLUTE_CLOCK_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_BCM_Lock_CTR_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_HVC_Err_Status_Msg_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_BCM_DCDC12_CNTRL_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_CCU_HVC_Req_Msg_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_CCU_Stat1_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_CCU_Stat2_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_CCU_Requests_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_CCU_Stat3_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_CCU_VCU_Msg1_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_CCU_VCU_Msg2_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_BCM_IC_Info_Msg_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_BCM_CLIMATIC_DATA_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_DMFL_SMFL_REQ_CTR_SEATS_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_DMFR_SMFR_REQ_CTR_SEATS_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_DMRL_SMRL_REQ_CTR_SEATS_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_DMRR_SMRR_REQ_CTR_SEATS_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_CCU_Msg1_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Sroof_State_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_VCU_CCU_Req_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_IC_DATA_MSG_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_ESC_08_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_WChF_Status_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_MAS_Status_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_EPB_VM_MSG_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_CGW_COMM_REQ_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_DCDC1248_01_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_FIU_REQ_CTR_01_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_DCDC1248_02_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_FIU_Access_Msg2_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_FIU_Profile_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_USBSw_Stat_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_SMFL_status_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_SMFR_status_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_SMRL_status_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_SMRR_status_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_DocSL_T_FL_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_DocSR_T_FR_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_VAU_TPMS_Msg_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_CCU_Errors_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_CCU_Msg3_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_FIU_Cmd_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_IC_SDM_Info_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_SDM_Cmd_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_HUD_MSG_STATUS_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_IC_SDM_Info_02_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_IC_Milleage_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_VEH_VIN_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_BCM_RunningBoards_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_OCUFL_MSG_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_OCUFR_MSG_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_OCURL_MSG_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_OCURR_MSG_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_RBCU_BODY_Stat_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_FIU_SMRL_REQ_CTR_SEATS_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_FIU_SMFR_REQ_CTR_SEATS_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_SMFL_MEM1_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_BCM_MEM_SMFL1_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_SMFL_MEM2_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_BCM_MEM_SMFL2_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_SMFR_MEM1_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_BCM_MEM_SMFR1_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_SMFR_MEM2_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_BCM_MEM_SMFR2_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_SMRL_MEM1_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_BCM_MEM_SMRL1_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_SMRL_MEM2_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_BCM_MEM_SMRL2_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_SMRR_MEM1_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_BCM_MEM_SMRR1_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_SMRR_MEM2_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_BCM_MEM_SMRR2_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_FIU_SMFL_REQ_CTR_SEATS_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_FIU_SMRR_REQ_CTR_SEATS_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_FIU_CTRL_DW_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_DW_STATE_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_FIU_Msg1_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_FIU_Msg2_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_ERAG_DATA_MSG_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_FIU_Msg3_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_FIU_EngMenu_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_WHFL_MSG1_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_WHFR_Msg1_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_PLDSilCU_State_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_PRDSilCU_State_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_FLDSilCU_State_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_FRDSilCU_State_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_RLDSilCU_State_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_RRDSilCU_State_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_FIU_CCU1_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_FIU_CCU2_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_FIU_CCU3_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_BCM_StyleCmd2_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_BCM_StyleCmd3_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_BCM_WHF_Request_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_IC_DISPLAY_CLOCK_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_BCM_UserConfig_Stat_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_FIU_MAS_Main_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_MAS_APA_Paths_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_MAS_APA_ParkPlace_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_ICLSilCU_State_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_ICRSilCU_State_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_SFRSilCU_State_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_SFLSilCU_State_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_RDRSilCU_State_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_FCSilCU_State_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_RCLSilCU_State_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_RCRSilCU_State_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_RDLSilCU_State_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_CCPF_BodyTM_Stat_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_IntCOM_Info_Stat_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_LTE_Sum_State2_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_WChF_FIU_TransferState_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_FIU_WChF_TransferState_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_VAU_BLE_Device_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_APU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_SSL_Status_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_SSR_Status_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_PTG_To_SupplierTool_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_SupplierTool_To_PTG_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_CCPF_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_CCPF_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_CCPR_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_CCPR_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_SSL_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_SSR_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_SSL_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_FCSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_SSR_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_FLDSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_FRDSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_ICLSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_FCSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_FLDSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_FRDSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_ICLSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_APU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_FTCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_FTCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_Sroof_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_SRoof_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_ICRSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_LB_pSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_PLSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_PRSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_RB_pSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_ICRSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_LB_pSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_PLSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_PRSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_RB_pSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_VAU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_BCM_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_DMFL_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_DMFR_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_DMRL_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_DMRR_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_SMRR_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_TM_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_CCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_SMFL_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_SMFR_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_SMRL_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_VAU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_BCM_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_DMFL_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_DMFR_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_DMRL_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_DMRR_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_SMRR_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_TM_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_CCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_SMFL_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_SMFR_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_SMRL_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_RCLSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_RCRSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_RDLSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_RDRSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_OCUFL_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_RLDSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_RRDSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_PTG_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_OCUFR_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_OCURL_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_OCURR_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_RCLSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_RCRSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_RDLSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_RDRSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_OCUFL_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_RLDSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_RRDSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_PTG_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_OCUFR_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_OCURL_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_OCURR_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_Functional_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_SFRSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_SFLSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_WHFL_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_To_WHFR_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_SFRSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_SFLSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_WHFL_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_Diag_From_WHFR_candb(FrameMonitor_t* _mon, uint32_t msgid); +void _FMon_CCU_AC_Ctrl_candb(FrameMonitor_t* _mon, uint32_t msgid); + +#define FMon_SDM_MAS_Req_candb(x, y) _FMon_SDM_MAS_Req_candb((x), (y)) +#define FMon_EMS_VCU_VAU_Immo_Req_candb(x, y) _FMon_EMS_VCU_VAU_Immo_Req_candb((x), (y)) +#define FMon_TCU_VAU_Immo_Req_candb(x, y) _FMon_TCU_VAU_Immo_Req_candb((x), (y)) +#define FMon_VAU2_NFC_TransferState_candb(x, y) _FMon_VAU2_NFC_TransferState_candb((x), (y)) +#define FMon_VAU_TCU_Hash_Resp_candb(x, y) _FMon_VAU_TCU_Hash_Resp_candb((x), (y)) +#define FMon_VAU_EMS_VCU_Hash_Resp_candb(x, y) _FMon_VAU_EMS_VCU_Hash_Resp_candb((x), (y)) +#define FMon_VAU2_INVRL_Hash_Resp_candb(x, y) _FMon_VAU2_INVRL_Hash_Resp_candb((x), (y)) +#define FMon_WChF_NFC_VAU_Transfer_State_candb(x, y) _FMon_WChF_NFC_VAU_Transfer_State_candb((x), (y)) +#define FMon_VAU2_INVRR_Hash_Resp_candb(x, y) _FMon_VAU2_INVRR_Hash_Resp_candb((x), (y)) +#define FMon_VAU_SDM_Immo_Req_candb(x, y) _FMon_VAU_SDM_Immo_Req_candb((x), (y)) +#define FMon_SDM_VAU_Hash_Resp_candb(x, y) _FMon_SDM_VAU_Hash_Resp_candb((x), (y)) +#define FMon_TCU_R932_1_candb(x, y) _FMon_TCU_R932_1_candb((x), (y)) +#define FMon_VAU2_INVF_Hash_Resp_candb(x, y) _FMon_VAU2_INVF_Hash_Resp_candb((x), (y)) +#define FMon_FTCU_DAT1_candb(x, y) _FMon_FTCU_DAT1_candb((x), (y)) +#define FMon_FTCU_DAT2_candb(x, y) _FMon_FTCU_DAT2_candb((x), (y)) +#define FMon_FTCU_DAT3_candb(x, y) _FMon_FTCU_DAT3_candb((x), (y)) +#define FMon_SCU_02_candb(x, y) _FMon_SCU_02_candb((x), (y)) +#define FMon_ESC_04_candb(x, y) _FMon_ESC_04_candb((x), (y)) +#define FMon_ESC_09_candb(x, y) _FMon_ESC_09_candb((x), (y)) +#define FMon_VAU2_Msg1_candb(x, y) _FMon_VAU2_Msg1_candb((x), (y)) +#define FMon_ESC_YRS_01_candb(x, y) _FMon_ESC_YRS_01_candb((x), (y)) +#define FMon_EMS_Veh_candb(x, y) _FMon_EMS_Veh_candb((x), (y)) +#define FMon_EMS_Indicators_candb(x, y) _FMon_EMS_Indicators_candb((x), (y)) +#define FMon_BCM_Powertrain_candb(x, y) _FMon_BCM_Powertrain_candb((x), (y)) +#define FMon_EMS_Veh_02_candb(x, y) _FMon_EMS_Veh_02_candb((x), (y)) +#define FMon_EMS_EEM_01_candb(x, y) _FMon_EMS_EEM_01_candb((x), (y)) +#define FMon_EMS_EEM_02_candb(x, y) _FMon_EMS_EEM_02_candb((x), (y)) +#define FMon_BCM_EEM_candb(x, y) _FMon_BCM_EEM_candb((x), (y)) +#define FMon_DAS_01_candb(x, y) _FMon_DAS_01_candb((x), (y)) +#define FMon_DAS_04_candb(x, y) _FMon_DAS_04_candb((x), (y)) +#define FMon_VCU_DriveInfo_candb(x, y) _FMon_VCU_DriveInfo_candb((x), (y)) +#define FMon_DAS_02_candb(x, y) _FMon_DAS_02_candb((x), (y)) +#define FMon_DAS_07_candb(x, y) _FMon_DAS_07_candb((x), (y)) +#define FMon_ACU_01_candb(x, y) _FMon_ACU_01_candb((x), (y)) +#define FMon_EPB_Status_candb(x, y) _FMon_EPB_Status_candb((x), (y)) +#define FMon_BCM_ExteriorLightState_candb(x, y) _FMon_BCM_ExteriorLightState_candb((x), (y)) +#define FMon_SWM_ContrlsState_candb(x, y) _FMon_SWM_ContrlsState_candb((x), (y)) +#define FMon_BCM_StyleCmd1_candb(x, y) _FMon_BCM_StyleCmd1_candb((x), (y)) +#define FMon_FIU_Access_Msg1_candb(x, y) _FMon_FIU_Access_Msg1_candb((x), (y)) +#define FMon_DMFR_Msg1_candb(x, y) _FMon_DMFR_Msg1_candb((x), (y)) +#define FMon_DMFL_Msg1_candb(x, y) _FMon_DMFL_Msg1_candb((x), (y)) +#define FMon_DMRL_Msg1_candb(x, y) _FMon_DMRL_Msg1_candb((x), (y)) +#define FMon_DMRR_Msg1_candb(x, y) _FMon_DMRR_Msg1_candb((x), (y)) +#define FMon_TM_Stat_candb(x, y) _FMon_TM_Stat_candb((x), (y)) +#define FMon_PTG_Body_Stat_candb(x, y) _FMon_PTG_Body_Stat_candb((x), (y)) +#define FMon_TM_CP_candb(x, y) _FMon_TM_CP_candb((x), (y)) +#define FMon_VAU2_Msg2_candb(x, y) _FMon_VAU2_Msg2_candb((x), (y)) +#define FMon_BCM_DMS_01_candb(x, y) _FMon_BCM_DMS_01_candb((x), (y)) +#define FMon_LB_pSilCU_State_candb(x, y) _FMon_LB_pSilCU_State_candb((x), (y)) +#define FMon_RB_pSilCU_State_candb(x, y) _FMon_RB_pSilCU_State_candb((x), (y)) +#define FMon_HVC_CCU_Status_Msg_candb(x, y) _FMon_HVC_CCU_Status_Msg_candb((x), (y)) +#define FMon_ATS_Status_candb(x, y) _FMon_ATS_Status_candb((x), (y)) +#define FMon_BCM_VEH_STATE_candb(x, y) _FMon_BCM_VEH_STATE_candb((x), (y)) +#define FMon_BCM_Veh_State2_candb(x, y) _FMon_BCM_Veh_State2_candb((x), (y)) +#define FMon_BCM_ALS_Light_Front_candb(x, y) _FMon_BCM_ALS_Light_Front_candb((x), (y)) +#define FMon_BCM_ALS_Light_Rear_candb(x, y) _FMon_BCM_ALS_Light_Rear_candb((x), (y)) +#define FMon_BCM_Rear_Plafond_Light_Data_candb(x, y) _FMon_BCM_Rear_Plafond_Light_Data_candb((x), (y)) +#define FMon_EMS_HVC_Req_Msg_candb(x, y) _FMon_EMS_HVC_Req_Msg_candb((x), (y)) +#define FMon_SAS_Standard_candb(x, y) _FMon_SAS_Standard_candb((x), (y)) +#define FMon_IC_ABSOLUTE_CLOCK_candb(x, y) _FMon_IC_ABSOLUTE_CLOCK_candb((x), (y)) +#define FMon_BCM_Lock_CTR_candb(x, y) _FMon_BCM_Lock_CTR_candb((x), (y)) +#define FMon_HVC_Err_Status_Msg_candb(x, y) _FMon_HVC_Err_Status_Msg_candb((x), (y)) +#define FMon_BCM_DCDC12_CNTRL_candb(x, y) _FMon_BCM_DCDC12_CNTRL_candb((x), (y)) +#define FMon_CCU_HVC_Req_Msg_candb(x, y) _FMon_CCU_HVC_Req_Msg_candb((x), (y)) +#define FMon_CCU_Stat1_candb(x, y) _FMon_CCU_Stat1_candb((x), (y)) +#define FMon_CCU_Stat2_candb(x, y) _FMon_CCU_Stat2_candb((x), (y)) +#define FMon_CCU_Requests_candb(x, y) _FMon_CCU_Requests_candb((x), (y)) +#define FMon_CCU_Stat3_candb(x, y) _FMon_CCU_Stat3_candb((x), (y)) +#define FMon_CCU_VCU_Msg1_candb(x, y) _FMon_CCU_VCU_Msg1_candb((x), (y)) +#define FMon_CCU_VCU_Msg2_candb(x, y) _FMon_CCU_VCU_Msg2_candb((x), (y)) +#define FMon_BCM_IC_Info_Msg_candb(x, y) _FMon_BCM_IC_Info_Msg_candb((x), (y)) +#define FMon_BCM_CLIMATIC_DATA_candb(x, y) _FMon_BCM_CLIMATIC_DATA_candb((x), (y)) +#define FMon_DMFL_SMFL_REQ_CTR_SEATS_candb(x, y) _FMon_DMFL_SMFL_REQ_CTR_SEATS_candb((x), (y)) +#define FMon_DMFR_SMFR_REQ_CTR_SEATS_candb(x, y) _FMon_DMFR_SMFR_REQ_CTR_SEATS_candb((x), (y)) +#define FMon_DMRL_SMRL_REQ_CTR_SEATS_candb(x, y) _FMon_DMRL_SMRL_REQ_CTR_SEATS_candb((x), (y)) +#define FMon_DMRR_SMRR_REQ_CTR_SEATS_candb(x, y) _FMon_DMRR_SMRR_REQ_CTR_SEATS_candb((x), (y)) +#define FMon_CCU_Msg1_candb(x, y) _FMon_CCU_Msg1_candb((x), (y)) +#define FMon_Sroof_State_candb(x, y) _FMon_Sroof_State_candb((x), (y)) +#define FMon_VCU_CCU_Req_candb(x, y) _FMon_VCU_CCU_Req_candb((x), (y)) +#define FMon_IC_DATA_MSG_candb(x, y) _FMon_IC_DATA_MSG_candb((x), (y)) +#define FMon_ESC_08_candb(x, y) _FMon_ESC_08_candb((x), (y)) +#define FMon_WChF_Status_candb(x, y) _FMon_WChF_Status_candb((x), (y)) +#define FMon_MAS_Status_candb(x, y) _FMon_MAS_Status_candb((x), (y)) +#define FMon_EPB_VM_MSG_candb(x, y) _FMon_EPB_VM_MSG_candb((x), (y)) +#define FMon_CGW_COMM_REQ_candb(x, y) _FMon_CGW_COMM_REQ_candb((x), (y)) +#define FMon_DCDC1248_01_candb(x, y) _FMon_DCDC1248_01_candb((x), (y)) +#define FMon_FIU_REQ_CTR_01_candb(x, y) _FMon_FIU_REQ_CTR_01_candb((x), (y)) +#define FMon_DCDC1248_02_candb(x, y) _FMon_DCDC1248_02_candb((x), (y)) +#define FMon_FIU_Access_Msg2_candb(x, y) _FMon_FIU_Access_Msg2_candb((x), (y)) +#define FMon_FIU_Profile_candb(x, y) _FMon_FIU_Profile_candb((x), (y)) +#define FMon_USBSw_Stat_candb(x, y) _FMon_USBSw_Stat_candb((x), (y)) +#define FMon_SMFL_status_candb(x, y) _FMon_SMFL_status_candb((x), (y)) +#define FMon_SMFR_status_candb(x, y) _FMon_SMFR_status_candb((x), (y)) +#define FMon_SMRL_status_candb(x, y) _FMon_SMRL_status_candb((x), (y)) +#define FMon_SMRR_status_candb(x, y) _FMon_SMRR_status_candb((x), (y)) +#define FMon_DocSL_T_FL_candb(x, y) _FMon_DocSL_T_FL_candb((x), (y)) +#define FMon_DocSR_T_FR_candb(x, y) _FMon_DocSR_T_FR_candb((x), (y)) +#define FMon_VAU_TPMS_Msg_candb(x, y) _FMon_VAU_TPMS_Msg_candb((x), (y)) +#define FMon_CCU_Errors_candb(x, y) _FMon_CCU_Errors_candb((x), (y)) +#define FMon_CCU_Msg3_candb(x, y) _FMon_CCU_Msg3_candb((x), (y)) +#define FMon_FIU_Cmd_candb(x, y) _FMon_FIU_Cmd_candb((x), (y)) +#define FMon_IC_SDM_Info_candb(x, y) _FMon_IC_SDM_Info_candb((x), (y)) +#define FMon_SDM_Cmd_candb(x, y) _FMon_SDM_Cmd_candb((x), (y)) +#define FMon_HUD_MSG_STATUS_candb(x, y) _FMon_HUD_MSG_STATUS_candb((x), (y)) +#define FMon_IC_SDM_Info_02_candb(x, y) _FMon_IC_SDM_Info_02_candb((x), (y)) +#define FMon_IC_Milleage_candb(x, y) _FMon_IC_Milleage_candb((x), (y)) +#define FMon_VEH_VIN_candb(x, y) _FMon_VEH_VIN_candb((x), (y)) +#define FMon_BCM_RunningBoards_candb(x, y) _FMon_BCM_RunningBoards_candb((x), (y)) +#define FMon_OCUFL_MSG_candb(x, y) _FMon_OCUFL_MSG_candb((x), (y)) +#define FMon_OCUFR_MSG_candb(x, y) _FMon_OCUFR_MSG_candb((x), (y)) +#define FMon_OCURL_MSG_candb(x, y) _FMon_OCURL_MSG_candb((x), (y)) +#define FMon_OCURR_MSG_candb(x, y) _FMon_OCURR_MSG_candb((x), (y)) +#define FMon_RBCU_BODY_Stat_candb(x, y) _FMon_RBCU_BODY_Stat_candb((x), (y)) +#define FMon_FIU_SMRL_REQ_CTR_SEATS_candb(x, y) _FMon_FIU_SMRL_REQ_CTR_SEATS_candb((x), (y)) +#define FMon_FIU_SMFR_REQ_CTR_SEATS_candb(x, y) _FMon_FIU_SMFR_REQ_CTR_SEATS_candb((x), (y)) +#define FMon_SMFL_MEM1_candb(x, y) _FMon_SMFL_MEM1_candb((x), (y)) +#define FMon_BCM_MEM_SMFL1_candb(x, y) _FMon_BCM_MEM_SMFL1_candb((x), (y)) +#define FMon_SMFL_MEM2_candb(x, y) _FMon_SMFL_MEM2_candb((x), (y)) +#define FMon_BCM_MEM_SMFL2_candb(x, y) _FMon_BCM_MEM_SMFL2_candb((x), (y)) +#define FMon_SMFR_MEM1_candb(x, y) _FMon_SMFR_MEM1_candb((x), (y)) +#define FMon_BCM_MEM_SMFR1_candb(x, y) _FMon_BCM_MEM_SMFR1_candb((x), (y)) +#define FMon_SMFR_MEM2_candb(x, y) _FMon_SMFR_MEM2_candb((x), (y)) +#define FMon_BCM_MEM_SMFR2_candb(x, y) _FMon_BCM_MEM_SMFR2_candb((x), (y)) +#define FMon_SMRL_MEM1_candb(x, y) _FMon_SMRL_MEM1_candb((x), (y)) +#define FMon_BCM_MEM_SMRL1_candb(x, y) _FMon_BCM_MEM_SMRL1_candb((x), (y)) +#define FMon_SMRL_MEM2_candb(x, y) _FMon_SMRL_MEM2_candb((x), (y)) +#define FMon_BCM_MEM_SMRL2_candb(x, y) _FMon_BCM_MEM_SMRL2_candb((x), (y)) +#define FMon_SMRR_MEM1_candb(x, y) _FMon_SMRR_MEM1_candb((x), (y)) +#define FMon_BCM_MEM_SMRR1_candb(x, y) _FMon_BCM_MEM_SMRR1_candb((x), (y)) +#define FMon_SMRR_MEM2_candb(x, y) _FMon_SMRR_MEM2_candb((x), (y)) +#define FMon_BCM_MEM_SMRR2_candb(x, y) _FMon_BCM_MEM_SMRR2_candb((x), (y)) +#define FMon_FIU_SMFL_REQ_CTR_SEATS_candb(x, y) _FMon_FIU_SMFL_REQ_CTR_SEATS_candb((x), (y)) +#define FMon_FIU_SMRR_REQ_CTR_SEATS_candb(x, y) _FMon_FIU_SMRR_REQ_CTR_SEATS_candb((x), (y)) +#define FMon_FIU_CTRL_DW_candb(x, y) _FMon_FIU_CTRL_DW_candb((x), (y)) +#define FMon_DW_STATE_candb(x, y) _FMon_DW_STATE_candb((x), (y)) +#define FMon_FIU_Msg1_candb(x, y) _FMon_FIU_Msg1_candb((x), (y)) +#define FMon_FIU_Msg2_candb(x, y) _FMon_FIU_Msg2_candb((x), (y)) +#define FMon_ERAG_DATA_MSG_candb(x, y) _FMon_ERAG_DATA_MSG_candb((x), (y)) +#define FMon_FIU_Msg3_candb(x, y) _FMon_FIU_Msg3_candb((x), (y)) +#define FMon_FIU_EngMenu_candb(x, y) _FMon_FIU_EngMenu_candb((x), (y)) +#define FMon_WHFL_MSG1_candb(x, y) _FMon_WHFL_MSG1_candb((x), (y)) +#define FMon_WHFR_Msg1_candb(x, y) _FMon_WHFR_Msg1_candb((x), (y)) +#define FMon_PLDSilCU_State_candb(x, y) _FMon_PLDSilCU_State_candb((x), (y)) +#define FMon_PRDSilCU_State_candb(x, y) _FMon_PRDSilCU_State_candb((x), (y)) +#define FMon_FLDSilCU_State_candb(x, y) _FMon_FLDSilCU_State_candb((x), (y)) +#define FMon_FRDSilCU_State_candb(x, y) _FMon_FRDSilCU_State_candb((x), (y)) +#define FMon_RLDSilCU_State_candb(x, y) _FMon_RLDSilCU_State_candb((x), (y)) +#define FMon_RRDSilCU_State_candb(x, y) _FMon_RRDSilCU_State_candb((x), (y)) +#define FMon_FIU_CCU1_candb(x, y) _FMon_FIU_CCU1_candb((x), (y)) +#define FMon_FIU_CCU2_candb(x, y) _FMon_FIU_CCU2_candb((x), (y)) +#define FMon_FIU_CCU3_candb(x, y) _FMon_FIU_CCU3_candb((x), (y)) +#define FMon_BCM_StyleCmd2_candb(x, y) _FMon_BCM_StyleCmd2_candb((x), (y)) +#define FMon_BCM_StyleCmd3_candb(x, y) _FMon_BCM_StyleCmd3_candb((x), (y)) +#define FMon_BCM_WHF_Request_candb(x, y) _FMon_BCM_WHF_Request_candb((x), (y)) +#define FMon_IC_DISPLAY_CLOCK_candb(x, y) _FMon_IC_DISPLAY_CLOCK_candb((x), (y)) +#define FMon_BCM_UserConfig_Stat_candb(x, y) _FMon_BCM_UserConfig_Stat_candb((x), (y)) +#define FMon_FIU_MAS_Main_candb(x, y) _FMon_FIU_MAS_Main_candb((x), (y)) +#define FMon_MAS_APA_Paths_candb(x, y) _FMon_MAS_APA_Paths_candb((x), (y)) +#define FMon_MAS_APA_ParkPlace_candb(x, y) _FMon_MAS_APA_ParkPlace_candb((x), (y)) +#define FMon_ICLSilCU_State_candb(x, y) _FMon_ICLSilCU_State_candb((x), (y)) +#define FMon_ICRSilCU_State_candb(x, y) _FMon_ICRSilCU_State_candb((x), (y)) +#define FMon_SFRSilCU_State_candb(x, y) _FMon_SFRSilCU_State_candb((x), (y)) +#define FMon_SFLSilCU_State_candb(x, y) _FMon_SFLSilCU_State_candb((x), (y)) +#define FMon_RDRSilCU_State_candb(x, y) _FMon_RDRSilCU_State_candb((x), (y)) +#define FMon_FCSilCU_State_candb(x, y) _FMon_FCSilCU_State_candb((x), (y)) +#define FMon_RCLSilCU_State_candb(x, y) _FMon_RCLSilCU_State_candb((x), (y)) +#define FMon_RCRSilCU_State_candb(x, y) _FMon_RCRSilCU_State_candb((x), (y)) +#define FMon_RDLSilCU_State_candb(x, y) _FMon_RDLSilCU_State_candb((x), (y)) +#define FMon_CCPF_BodyTM_Stat_candb(x, y) _FMon_CCPF_BodyTM_Stat_candb((x), (y)) +#define FMon_IntCOM_Info_Stat_candb(x, y) _FMon_IntCOM_Info_Stat_candb((x), (y)) +#define FMon_LTE_Sum_State2_candb(x, y) _FMon_LTE_Sum_State2_candb((x), (y)) +#define FMon_WChF_FIU_TransferState_candb(x, y) _FMon_WChF_FIU_TransferState_candb((x), (y)) +#define FMon_FIU_WChF_TransferState_candb(x, y) _FMon_FIU_WChF_TransferState_candb((x), (y)) +#define FMon_VAU_BLE_Device_candb(x, y) _FMon_VAU_BLE_Device_candb((x), (y)) +#define FMon_Diag_From_APU_candb(x, y) _FMon_Diag_From_APU_candb((x), (y)) +#define FMon_SSL_Status_candb(x, y) _FMon_SSL_Status_candb((x), (y)) +#define FMon_SSR_Status_candb(x, y) _FMon_SSR_Status_candb((x), (y)) +#define FMon_PTG_To_SupplierTool_candb(x, y) _FMon_PTG_To_SupplierTool_candb((x), (y)) +#define FMon_SupplierTool_To_PTG_candb(x, y) _FMon_SupplierTool_To_PTG_candb((x), (y)) +#define FMon_Diag_From_CCPF_candb(x, y) _FMon_Diag_From_CCPF_candb((x), (y)) +#define FMon_Diag_To_CCPF_candb(x, y) _FMon_Diag_To_CCPF_candb((x), (y)) +#define FMon_Diag_From_CCPR_candb(x, y) _FMon_Diag_From_CCPR_candb((x), (y)) +#define FMon_Diag_To_CCPR_candb(x, y) _FMon_Diag_To_CCPR_candb((x), (y)) +#define FMon_Diag_To_SSL_candb(x, y) _FMon_Diag_To_SSL_candb((x), (y)) +#define FMon_Diag_To_SSR_candb(x, y) _FMon_Diag_To_SSR_candb((x), (y)) +#define FMon_Diag_From_SSL_candb(x, y) _FMon_Diag_From_SSL_candb((x), (y)) +#define FMon_Diag_To_FCSilCU_candb(x, y) _FMon_Diag_To_FCSilCU_candb((x), (y)) +#define FMon_Diag_From_SSR_candb(x, y) _FMon_Diag_From_SSR_candb((x), (y)) +#define FMon_Diag_To_FLDSilCU_candb(x, y) _FMon_Diag_To_FLDSilCU_candb((x), (y)) +#define FMon_Diag_To_FRDSilCU_candb(x, y) _FMon_Diag_To_FRDSilCU_candb((x), (y)) +#define FMon_Diag_To_ICLSilCU_candb(x, y) _FMon_Diag_To_ICLSilCU_candb((x), (y)) +#define FMon_Diag_From_FCSilCU_candb(x, y) _FMon_Diag_From_FCSilCU_candb((x), (y)) +#define FMon_Diag_From_FLDSilCU_candb(x, y) _FMon_Diag_From_FLDSilCU_candb((x), (y)) +#define FMon_Diag_From_FRDSilCU_candb(x, y) _FMon_Diag_From_FRDSilCU_candb((x), (y)) +#define FMon_Diag_From_ICLSilCU_candb(x, y) _FMon_Diag_From_ICLSilCU_candb((x), (y)) +#define FMon_Diag_To_APU_candb(x, y) _FMon_Diag_To_APU_candb((x), (y)) +#define FMon_Diag_To_FTCU_candb(x, y) _FMon_Diag_To_FTCU_candb((x), (y)) +#define FMon_Diag_From_FTCU_candb(x, y) _FMon_Diag_From_FTCU_candb((x), (y)) +#define FMon_Diag_To_Sroof_candb(x, y) _FMon_Diag_To_Sroof_candb((x), (y)) +#define FMon_Diag_From_SRoof_candb(x, y) _FMon_Diag_From_SRoof_candb((x), (y)) +#define FMon_Diag_To_ICRSilCU_candb(x, y) _FMon_Diag_To_ICRSilCU_candb((x), (y)) +#define FMon_Diag_To_LB_pSilCU_candb(x, y) _FMon_Diag_To_LB_pSilCU_candb((x), (y)) +#define FMon_Diag_To_PLSilCU_candb(x, y) _FMon_Diag_To_PLSilCU_candb((x), (y)) +#define FMon_Diag_To_PRSilCU_candb(x, y) _FMon_Diag_To_PRSilCU_candb((x), (y)) +#define FMon_Diag_To_RB_pSilCU_candb(x, y) _FMon_Diag_To_RB_pSilCU_candb((x), (y)) +#define FMon_Diag_From_ICRSilCU_candb(x, y) _FMon_Diag_From_ICRSilCU_candb((x), (y)) +#define FMon_Diag_From_LB_pSilCU_candb(x, y) _FMon_Diag_From_LB_pSilCU_candb((x), (y)) +#define FMon_Diag_From_PLSilCU_candb(x, y) _FMon_Diag_From_PLSilCU_candb((x), (y)) +#define FMon_Diag_From_PRSilCU_candb(x, y) _FMon_Diag_From_PRSilCU_candb((x), (y)) +#define FMon_Diag_From_RB_pSilCU_candb(x, y) _FMon_Diag_From_RB_pSilCU_candb((x), (y)) +#define FMon_Diag_To_VAU_candb(x, y) _FMon_Diag_To_VAU_candb((x), (y)) +#define FMon_Diag_To_BCM_candb(x, y) _FMon_Diag_To_BCM_candb((x), (y)) +#define FMon_Diag_To_DMFL_candb(x, y) _FMon_Diag_To_DMFL_candb((x), (y)) +#define FMon_Diag_To_DMFR_candb(x, y) _FMon_Diag_To_DMFR_candb((x), (y)) +#define FMon_Diag_To_DMRL_candb(x, y) _FMon_Diag_To_DMRL_candb((x), (y)) +#define FMon_Diag_To_DMRR_candb(x, y) _FMon_Diag_To_DMRR_candb((x), (y)) +#define FMon_Diag_To_SMRR_candb(x, y) _FMon_Diag_To_SMRR_candb((x), (y)) +#define FMon_Diag_To_TM_candb(x, y) _FMon_Diag_To_TM_candb((x), (y)) +#define FMon_Diag_To_CCU_candb(x, y) _FMon_Diag_To_CCU_candb((x), (y)) +#define FMon_Diag_To_SMFL_candb(x, y) _FMon_Diag_To_SMFL_candb((x), (y)) +#define FMon_Diag_To_SMFR_candb(x, y) _FMon_Diag_To_SMFR_candb((x), (y)) +#define FMon_Diag_To_SMRL_candb(x, y) _FMon_Diag_To_SMRL_candb((x), (y)) +#define FMon_Diag_From_VAU_candb(x, y) _FMon_Diag_From_VAU_candb((x), (y)) +#define FMon_Diag_From_BCM_candb(x, y) _FMon_Diag_From_BCM_candb((x), (y)) +#define FMon_Diag_From_DMFL_candb(x, y) _FMon_Diag_From_DMFL_candb((x), (y)) +#define FMon_Diag_From_DMFR_candb(x, y) _FMon_Diag_From_DMFR_candb((x), (y)) +#define FMon_Diag_From_DMRL_candb(x, y) _FMon_Diag_From_DMRL_candb((x), (y)) +#define FMon_Diag_From_DMRR_candb(x, y) _FMon_Diag_From_DMRR_candb((x), (y)) +#define FMon_Diag_From_SMRR_candb(x, y) _FMon_Diag_From_SMRR_candb((x), (y)) +#define FMon_Diag_From_TM_candb(x, y) _FMon_Diag_From_TM_candb((x), (y)) +#define FMon_Diag_From_CCU_candb(x, y) _FMon_Diag_From_CCU_candb((x), (y)) +#define FMon_Diag_From_SMFL_candb(x, y) _FMon_Diag_From_SMFL_candb((x), (y)) +#define FMon_Diag_From_SMFR_candb(x, y) _FMon_Diag_From_SMFR_candb((x), (y)) +#define FMon_Diag_From_SMRL_candb(x, y) _FMon_Diag_From_SMRL_candb((x), (y)) +#define FMon_Diag_To_RCLSilCU_candb(x, y) _FMon_Diag_To_RCLSilCU_candb((x), (y)) +#define FMon_Diag_To_RCRSilCU_candb(x, y) _FMon_Diag_To_RCRSilCU_candb((x), (y)) +#define FMon_Diag_To_RDLSilCU_candb(x, y) _FMon_Diag_To_RDLSilCU_candb((x), (y)) +#define FMon_Diag_To_RDRSilCU_candb(x, y) _FMon_Diag_To_RDRSilCU_candb((x), (y)) +#define FMon_Diag_From_OCUFL_candb(x, y) _FMon_Diag_From_OCUFL_candb((x), (y)) +#define FMon_Diag_To_RLDSilCU_candb(x, y) _FMon_Diag_To_RLDSilCU_candb((x), (y)) +#define FMon_Diag_To_RRDSilCU_candb(x, y) _FMon_Diag_To_RRDSilCU_candb((x), (y)) +#define FMon_Diag_From_PTG_candb(x, y) _FMon_Diag_From_PTG_candb((x), (y)) +#define FMon_Diag_From_OCUFR_candb(x, y) _FMon_Diag_From_OCUFR_candb((x), (y)) +#define FMon_Diag_From_OCURL_candb(x, y) _FMon_Diag_From_OCURL_candb((x), (y)) +#define FMon_Diag_From_OCURR_candb(x, y) _FMon_Diag_From_OCURR_candb((x), (y)) +#define FMon_Diag_From_RCLSilCU_candb(x, y) _FMon_Diag_From_RCLSilCU_candb((x), (y)) +#define FMon_Diag_From_RCRSilCU_candb(x, y) _FMon_Diag_From_RCRSilCU_candb((x), (y)) +#define FMon_Diag_From_RDLSilCU_candb(x, y) _FMon_Diag_From_RDLSilCU_candb((x), (y)) +#define FMon_Diag_From_RDRSilCU_candb(x, y) _FMon_Diag_From_RDRSilCU_candb((x), (y)) +#define FMon_Diag_To_OCUFL_candb(x, y) _FMon_Diag_To_OCUFL_candb((x), (y)) +#define FMon_Diag_From_RLDSilCU_candb(x, y) _FMon_Diag_From_RLDSilCU_candb((x), (y)) +#define FMon_Diag_From_RRDSilCU_candb(x, y) _FMon_Diag_From_RRDSilCU_candb((x), (y)) +#define FMon_Diag_To_PTG_candb(x, y) _FMon_Diag_To_PTG_candb((x), (y)) +#define FMon_Diag_To_OCUFR_candb(x, y) _FMon_Diag_To_OCUFR_candb((x), (y)) +#define FMon_Diag_To_OCURL_candb(x, y) _FMon_Diag_To_OCURL_candb((x), (y)) +#define FMon_Diag_To_OCURR_candb(x, y) _FMon_Diag_To_OCURR_candb((x), (y)) +#define FMon_Diag_Functional_candb(x, y) _FMon_Diag_Functional_candb((x), (y)) +#define FMon_Diag_To_SFRSilCU_candb(x, y) _FMon_Diag_To_SFRSilCU_candb((x), (y)) +#define FMon_Diag_To_SFLSilCU_candb(x, y) _FMon_Diag_To_SFLSilCU_candb((x), (y)) +#define FMon_Diag_To_WHFL_candb(x, y) _FMon_Diag_To_WHFL_candb((x), (y)) +#define FMon_Diag_To_WHFR_candb(x, y) _FMon_Diag_To_WHFR_candb((x), (y)) +#define FMon_Diag_From_SFRSilCU_candb(x, y) _FMon_Diag_From_SFRSilCU_candb((x), (y)) +#define FMon_Diag_From_SFLSilCU_candb(x, y) _FMon_Diag_From_SFLSilCU_candb((x), (y)) +#define FMon_Diag_From_WHFL_candb(x, y) _FMon_Diag_From_WHFL_candb((x), (y)) +#define FMon_Diag_From_WHFR_candb(x, y) _FMon_Diag_From_WHFR_candb((x), (y)) +#define FMon_CCU_AC_Ctrl_candb(x, y) _FMon_CCU_AC_Ctrl_candb((x), (y)) + +#endif + +#endif // CANDB_USE_DIAG_MONITORS + +#ifdef __cplusplus +} +#endif diff --git a/MODULES/HVAC_M7_CAN_MATRIX/lib/candb.c b/MODULES/HVAC_M7_CAN_MATRIX/lib/candb.c new file mode 100644 index 0000000..38c4e4b --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/lib/candb.c @@ -0,0 +1,18512 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#include "candb.h" + + +// DBC file version +#if (VER_CANDB_MAJ != (0U)) || (VER_CANDB_MIN != (0U)) +#error The CANDB dbc source files have different versions +#endif + +#ifdef CANDB_USE_DIAG_MONITORS +// Function prototypes to be called each time CAN frame is unpacked +// FMon function may detect RC, CRC or DLC violation +#include "candb-fmon.h" + +#endif // CANDB_USE_DIAG_MONITORS + +// This macro guard for the case when you need to enable +// using diag monitors but there is no necessity in proper +// SysTick provider. For providing one you need define macro +// before this line - in dbccodeconf.h + +#ifndef GetSystemTick +#define GetSystemTick() (0u) +#endif + +// This macro guard is for the case when you want to build +// app with enabled optoin auto CSM, but don't yet have +// proper getframehash implementation + +#ifndef GetFrameHash +#define GetFrameHash(a,b,c,d,e) (0u) +#endif + +// This function performs extension of sign for the signals +// whose bit width value is not aligned to one of power of 2 or less than 8. +// The types 'bitext_t' and 'ubitext_t' define the biggest bit width which +// can be correctly handled. You need to select type which can contain +// n+1 bits where n is the largest signed signal width. For example if +// the most wide signed signal has a width of 31 bits you need to set +// bitext_t as int32_t and ubitext_t as uint32_t +// Defined these typedefs in @dbccodeconf.h or locally in 'dbcdrvname'-config.h +static bitext_t __ext_sig__(ubitext_t val, uint8_t bits) +{ + ubitext_t const m = (ubitext_t) (1u << (bits - 1u)); + return ((val ^ m) - m); +} + +uint32_t Unpack_SDM_MAS_Req_candb(SDM_MAS_Req_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->SDM_AVM_Active_Req = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->SDM_MAS_Mode_Req = (uint8_t) ( ((_d[0] >> 1U) & (0x01U)) ); + _m->SDM_APAactive_Req = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + _m->SDM_CntrlBtnAPA_Req = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + _m->SDM_StartAPA_Req = (uint8_t) ( ((_d[0] >> 4U) & (0x01U)) ); + _m->SDM_MASoff_Req = (uint8_t) ( ((_d[0] >> 5U) & (0x01U)) ); + _m->SDM_ManeuverAllowed_Stat = (uint8_t) ( ((_d[0] >> 6U) & (0x01U)) ); + _m->SDM_PhoneAppAvail_Stat = (uint8_t) ( ((_d[0] >> 7U) & (0x01U)) ); + _m->SDM_ParkingOutPath_Req = (uint8_t) ( (_d[1] & (0x03U)) ); + _m->SDM_CtrlAPAerr_Stat = (uint8_t) ( ((_d[1] >> 2U) & (0x07U)) ); + _m->SDM_ContinueMove_Req = (uint8_t) ( ((_d[1] >> 5U) & (0x01U)) ); + _m->SDM_FIUmaster_Req = (uint8_t) ( ((_d[1] >> 6U) & (0x01U)) ); + _m->SDM_View_Req = (uint8_t) ( (_d[2] & (0x0FU)) ); + _m->SDM_MAS_Req_RC = (uint8_t) ( ((_d[2] >> 4U) & (0x0FU)) ); + _m->SDM_MAS_Req_CS = (uint8_t) ( (_d[3] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < SDM_MAS_Req_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_SDM_MAS_Req_candb(&_m->mon1, SDM_MAS_Req_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return SDM_MAS_Req_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_SDM_MAS_Req_candb(SDM_MAS_Req_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SDM_MAS_Req_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->SDM_AVM_Active_Req & (0x01U)) | ((_m->SDM_MAS_Mode_Req & (0x01U)) << 1U) | ((_m->SDM_APAactive_Req & (0x01U)) << 2U) | ((_m->SDM_CntrlBtnAPA_Req & (0x01U)) << 3U) | ((_m->SDM_StartAPA_Req & (0x01U)) << 4U) | ((_m->SDM_MASoff_Req & (0x01U)) << 5U) | ((_m->SDM_ManeuverAllowed_Stat & (0x01U)) << 6U) | ((_m->SDM_PhoneAppAvail_Stat & (0x01U)) << 7U) ); + cframe->Data[1] |= (uint8_t) ( (_m->SDM_ParkingOutPath_Req & (0x03U)) | ((_m->SDM_CtrlAPAerr_Stat & (0x07U)) << 2U) | ((_m->SDM_ContinueMove_Req & (0x01U)) << 5U) | ((_m->SDM_FIUmaster_Req & (0x01U)) << 6U) ); + cframe->Data[2] |= (uint8_t) ( (_m->SDM_View_Req & (0x0FU)) | ((_m->SDM_MAS_Req_RC & (0x0FU)) << 4U) ); + cframe->Data[3] |= (uint8_t) ( (_m->SDM_MAS_Req_CS & (0xFFU)) ); + + cframe->MsgId = (uint32_t) SDM_MAS_Req_CANID; + cframe->DLC = (uint8_t) SDM_MAS_Req_DLC; + cframe->IDE = (uint8_t) SDM_MAS_Req_IDE; + return SDM_MAS_Req_CANID; +} + +#else + +uint32_t Pack_SDM_MAS_Req_candb(SDM_MAS_Req_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SDM_MAS_Req_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->SDM_AVM_Active_Req & (0x01U)) | ((_m->SDM_MAS_Mode_Req & (0x01U)) << 1U) | ((_m->SDM_APAactive_Req & (0x01U)) << 2U) | ((_m->SDM_CntrlBtnAPA_Req & (0x01U)) << 3U) | ((_m->SDM_StartAPA_Req & (0x01U)) << 4U) | ((_m->SDM_MASoff_Req & (0x01U)) << 5U) | ((_m->SDM_ManeuverAllowed_Stat & (0x01U)) << 6U) | ((_m->SDM_PhoneAppAvail_Stat & (0x01U)) << 7U) ); + _d[1] |= (uint8_t) ( (_m->SDM_ParkingOutPath_Req & (0x03U)) | ((_m->SDM_CtrlAPAerr_Stat & (0x07U)) << 2U) | ((_m->SDM_ContinueMove_Req & (0x01U)) << 5U) | ((_m->SDM_FIUmaster_Req & (0x01U)) << 6U) ); + _d[2] |= (uint8_t) ( (_m->SDM_View_Req & (0x0FU)) | ((_m->SDM_MAS_Req_RC & (0x0FU)) << 4U) ); + _d[3] |= (uint8_t) ( (_m->SDM_MAS_Req_CS & (0xFFU)) ); + + *_len = (uint8_t) SDM_MAS_Req_DLC; + *_ide = (uint8_t) SDM_MAS_Req_IDE; + return SDM_MAS_Req_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_EMS_VCU_VAU_Immo_Req_candb(EMS_VCU_VAU_Immo_Req_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->EMS_VCU_VAU_Immo_Req = (uint64_t) ( ((uint64_t)(_d[7] & (0xFFU)) << 56U) | ((uint64_t)(_d[6] & (0xFFU)) << 48U) | ((uint64_t)(_d[5] & (0xFFU)) << 40U) | ((uint64_t)(_d[4] & (0xFFU)) << 32U) | ((_d[3] & (0xFFU)) << 24U) | ((_d[2] & (0xFFU)) << 16U) | ((_d[1] & (0xFFU)) << 8U) | (_d[0] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < EMS_VCU_VAU_Immo_Req_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_EMS_VCU_VAU_Immo_Req_candb(&_m->mon1, EMS_VCU_VAU_Immo_Req_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return EMS_VCU_VAU_Immo_Req_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_EMS_VCU_VAU_Immo_Req_candb(EMS_VCU_VAU_Immo_Req_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(EMS_VCU_VAU_Immo_Req_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->EMS_VCU_VAU_Immo_Req & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->EMS_VCU_VAU_Immo_Req >> 8U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->EMS_VCU_VAU_Immo_Req >> 16U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->EMS_VCU_VAU_Immo_Req >> 24U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->EMS_VCU_VAU_Immo_Req >> 32U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->EMS_VCU_VAU_Immo_Req >> 40U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->EMS_VCU_VAU_Immo_Req >> 48U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( ((_m->EMS_VCU_VAU_Immo_Req >> 56U) & (0xFFU)) ); + + cframe->MsgId = (uint32_t) EMS_VCU_VAU_Immo_Req_CANID; + cframe->DLC = (uint8_t) EMS_VCU_VAU_Immo_Req_DLC; + cframe->IDE = (uint8_t) EMS_VCU_VAU_Immo_Req_IDE; + return EMS_VCU_VAU_Immo_Req_CANID; +} + +#else + +uint32_t Pack_EMS_VCU_VAU_Immo_Req_candb(EMS_VCU_VAU_Immo_Req_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(EMS_VCU_VAU_Immo_Req_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->EMS_VCU_VAU_Immo_Req & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->EMS_VCU_VAU_Immo_Req >> 8U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->EMS_VCU_VAU_Immo_Req >> 16U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->EMS_VCU_VAU_Immo_Req >> 24U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->EMS_VCU_VAU_Immo_Req >> 32U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->EMS_VCU_VAU_Immo_Req >> 40U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->EMS_VCU_VAU_Immo_Req >> 48U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( ((_m->EMS_VCU_VAU_Immo_Req >> 56U) & (0xFFU)) ); + + *_len = (uint8_t) EMS_VCU_VAU_Immo_Req_DLC; + *_ide = (uint8_t) EMS_VCU_VAU_Immo_Req_IDE; + return EMS_VCU_VAU_Immo_Req_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_TCU_VAU_Immo_Req_candb(TCU_VAU_Immo_Req_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->TCU_VAU_Immo_Req = (uint64_t) ( ((uint64_t)(_d[7] & (0xFFU)) << 56U) | ((uint64_t)(_d[6] & (0xFFU)) << 48U) | ((uint64_t)(_d[5] & (0xFFU)) << 40U) | ((uint64_t)(_d[4] & (0xFFU)) << 32U) | ((_d[3] & (0xFFU)) << 24U) | ((_d[2] & (0xFFU)) << 16U) | ((_d[1] & (0xFFU)) << 8U) | (_d[0] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < TCU_VAU_Immo_Req_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_TCU_VAU_Immo_Req_candb(&_m->mon1, TCU_VAU_Immo_Req_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return TCU_VAU_Immo_Req_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_TCU_VAU_Immo_Req_candb(TCU_VAU_Immo_Req_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(TCU_VAU_Immo_Req_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->TCU_VAU_Immo_Req & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->TCU_VAU_Immo_Req >> 8U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->TCU_VAU_Immo_Req >> 16U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->TCU_VAU_Immo_Req >> 24U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->TCU_VAU_Immo_Req >> 32U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->TCU_VAU_Immo_Req >> 40U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->TCU_VAU_Immo_Req >> 48U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( ((_m->TCU_VAU_Immo_Req >> 56U) & (0xFFU)) ); + + cframe->MsgId = (uint32_t) TCU_VAU_Immo_Req_CANID; + cframe->DLC = (uint8_t) TCU_VAU_Immo_Req_DLC; + cframe->IDE = (uint8_t) TCU_VAU_Immo_Req_IDE; + return TCU_VAU_Immo_Req_CANID; +} + +#else + +uint32_t Pack_TCU_VAU_Immo_Req_candb(TCU_VAU_Immo_Req_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(TCU_VAU_Immo_Req_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->TCU_VAU_Immo_Req & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->TCU_VAU_Immo_Req >> 8U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->TCU_VAU_Immo_Req >> 16U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->TCU_VAU_Immo_Req >> 24U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->TCU_VAU_Immo_Req >> 32U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->TCU_VAU_Immo_Req >> 40U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->TCU_VAU_Immo_Req >> 48U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( ((_m->TCU_VAU_Immo_Req >> 56U) & (0xFFU)) ); + + *_len = (uint8_t) TCU_VAU_Immo_Req_DLC; + *_ide = (uint8_t) TCU_VAU_Immo_Req_IDE; + return TCU_VAU_Immo_Req_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_VAU2_NFC_TransferState_candb(VAU2_NFC_TransferState_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->VAU_NFC_FrameNumber = (uint8_t) ( (_d[0] & (0x0FU)) ); + _m->VAU_NFC_FrameTotalNumber = (uint8_t) ( ((_d[0] >> 4U) & (0x0FU)) ); + _m->VAU_NFC_TransferData = (uint64_t) ( ((uint64_t)(_d[7] & (0xFFU)) << 48U) | ((uint64_t)(_d[6] & (0xFFU)) << 40U) | ((uint64_t)(_d[5] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[3] & (0xFFU)) << 16U) | ((_d[2] & (0xFFU)) << 8U) | (_d[1] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < VAU2_NFC_TransferState_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_VAU2_NFC_TransferState_candb(&_m->mon1, VAU2_NFC_TransferState_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return VAU2_NFC_TransferState_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_VAU2_NFC_TransferState_candb(VAU2_NFC_TransferState_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(VAU2_NFC_TransferState_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->VAU_NFC_FrameNumber & (0x0FU)) | ((_m->VAU_NFC_FrameTotalNumber & (0x0FU)) << 4U) ); + cframe->Data[1] |= (uint8_t) ( (_m->VAU_NFC_TransferData & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->VAU_NFC_TransferData >> 8U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->VAU_NFC_TransferData >> 16U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->VAU_NFC_TransferData >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->VAU_NFC_TransferData >> 32U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->VAU_NFC_TransferData >> 40U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( ((_m->VAU_NFC_TransferData >> 48U) & (0xFFU)) ); + + cframe->MsgId = (uint32_t) VAU2_NFC_TransferState_CANID; + cframe->DLC = (uint8_t) VAU2_NFC_TransferState_DLC; + cframe->IDE = (uint8_t) VAU2_NFC_TransferState_IDE; + return VAU2_NFC_TransferState_CANID; +} + +#else + +uint32_t Pack_VAU2_NFC_TransferState_candb(VAU2_NFC_TransferState_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(VAU2_NFC_TransferState_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->VAU_NFC_FrameNumber & (0x0FU)) | ((_m->VAU_NFC_FrameTotalNumber & (0x0FU)) << 4U) ); + _d[1] |= (uint8_t) ( (_m->VAU_NFC_TransferData & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->VAU_NFC_TransferData >> 8U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->VAU_NFC_TransferData >> 16U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->VAU_NFC_TransferData >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->VAU_NFC_TransferData >> 32U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->VAU_NFC_TransferData >> 40U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( ((_m->VAU_NFC_TransferData >> 48U) & (0xFFU)) ); + + *_len = (uint8_t) VAU2_NFC_TransferState_DLC; + *_ide = (uint8_t) VAU2_NFC_TransferState_IDE; + return VAU2_NFC_TransferState_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_VAU_TCU_Hash_Resp_candb(VAU_TCU_Hash_Resp_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->VAU_TCU_Hash_Resp = (uint64_t) ( ((uint64_t)(_d[7] & (0xFFU)) << 56U) | ((uint64_t)(_d[6] & (0xFFU)) << 48U) | ((uint64_t)(_d[5] & (0xFFU)) << 40U) | ((uint64_t)(_d[4] & (0xFFU)) << 32U) | ((_d[3] & (0xFFU)) << 24U) | ((_d[2] & (0xFFU)) << 16U) | ((_d[1] & (0xFFU)) << 8U) | (_d[0] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < VAU_TCU_Hash_Resp_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_VAU_TCU_Hash_Resp_candb(&_m->mon1, VAU_TCU_Hash_Resp_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return VAU_TCU_Hash_Resp_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_VAU_TCU_Hash_Resp_candb(VAU_TCU_Hash_Resp_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(VAU_TCU_Hash_Resp_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->VAU_TCU_Hash_Resp & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->VAU_TCU_Hash_Resp >> 8U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->VAU_TCU_Hash_Resp >> 16U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->VAU_TCU_Hash_Resp >> 24U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->VAU_TCU_Hash_Resp >> 32U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->VAU_TCU_Hash_Resp >> 40U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->VAU_TCU_Hash_Resp >> 48U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( ((_m->VAU_TCU_Hash_Resp >> 56U) & (0xFFU)) ); + + cframe->MsgId = (uint32_t) VAU_TCU_Hash_Resp_CANID; + cframe->DLC = (uint8_t) VAU_TCU_Hash_Resp_DLC; + cframe->IDE = (uint8_t) VAU_TCU_Hash_Resp_IDE; + return VAU_TCU_Hash_Resp_CANID; +} + +#else + +uint32_t Pack_VAU_TCU_Hash_Resp_candb(VAU_TCU_Hash_Resp_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(VAU_TCU_Hash_Resp_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->VAU_TCU_Hash_Resp & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->VAU_TCU_Hash_Resp >> 8U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->VAU_TCU_Hash_Resp >> 16U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->VAU_TCU_Hash_Resp >> 24U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->VAU_TCU_Hash_Resp >> 32U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->VAU_TCU_Hash_Resp >> 40U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->VAU_TCU_Hash_Resp >> 48U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( ((_m->VAU_TCU_Hash_Resp >> 56U) & (0xFFU)) ); + + *_len = (uint8_t) VAU_TCU_Hash_Resp_DLC; + *_ide = (uint8_t) VAU_TCU_Hash_Resp_IDE; + return VAU_TCU_Hash_Resp_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_VAU_EMS_VCU_Hash_Resp_candb(VAU_EMS_VCU_Hash_Resp_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->VAU_EMS_VCU_Hash_Resp = (uint64_t) ( ((uint64_t)(_d[7] & (0xFFU)) << 56U) | ((uint64_t)(_d[6] & (0xFFU)) << 48U) | ((uint64_t)(_d[5] & (0xFFU)) << 40U) | ((uint64_t)(_d[4] & (0xFFU)) << 32U) | ((_d[3] & (0xFFU)) << 24U) | ((_d[2] & (0xFFU)) << 16U) | ((_d[1] & (0xFFU)) << 8U) | (_d[0] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < VAU_EMS_VCU_Hash_Resp_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_VAU_EMS_VCU_Hash_Resp_candb(&_m->mon1, VAU_EMS_VCU_Hash_Resp_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return VAU_EMS_VCU_Hash_Resp_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_VAU_EMS_VCU_Hash_Resp_candb(VAU_EMS_VCU_Hash_Resp_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(VAU_EMS_VCU_Hash_Resp_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->VAU_EMS_VCU_Hash_Resp & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->VAU_EMS_VCU_Hash_Resp >> 8U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->VAU_EMS_VCU_Hash_Resp >> 16U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->VAU_EMS_VCU_Hash_Resp >> 24U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->VAU_EMS_VCU_Hash_Resp >> 32U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->VAU_EMS_VCU_Hash_Resp >> 40U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->VAU_EMS_VCU_Hash_Resp >> 48U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( ((_m->VAU_EMS_VCU_Hash_Resp >> 56U) & (0xFFU)) ); + + cframe->MsgId = (uint32_t) VAU_EMS_VCU_Hash_Resp_CANID; + cframe->DLC = (uint8_t) VAU_EMS_VCU_Hash_Resp_DLC; + cframe->IDE = (uint8_t) VAU_EMS_VCU_Hash_Resp_IDE; + return VAU_EMS_VCU_Hash_Resp_CANID; +} + +#else + +uint32_t Pack_VAU_EMS_VCU_Hash_Resp_candb(VAU_EMS_VCU_Hash_Resp_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(VAU_EMS_VCU_Hash_Resp_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->VAU_EMS_VCU_Hash_Resp & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->VAU_EMS_VCU_Hash_Resp >> 8U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->VAU_EMS_VCU_Hash_Resp >> 16U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->VAU_EMS_VCU_Hash_Resp >> 24U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->VAU_EMS_VCU_Hash_Resp >> 32U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->VAU_EMS_VCU_Hash_Resp >> 40U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->VAU_EMS_VCU_Hash_Resp >> 48U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( ((_m->VAU_EMS_VCU_Hash_Resp >> 56U) & (0xFFU)) ); + + *_len = (uint8_t) VAU_EMS_VCU_Hash_Resp_DLC; + *_ide = (uint8_t) VAU_EMS_VCU_Hash_Resp_IDE; + return VAU_EMS_VCU_Hash_Resp_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_VAU2_INVRL_Hash_Resp_candb(VAU2_INVRL_Hash_Resp_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->VAU2_INVRL_Hash_Resp = (uint64_t) ( ((uint64_t)(_d[7] & (0xFFU)) << 56U) | ((uint64_t)(_d[6] & (0xFFU)) << 48U) | ((uint64_t)(_d[5] & (0xFFU)) << 40U) | ((uint64_t)(_d[4] & (0xFFU)) << 32U) | ((_d[3] & (0xFFU)) << 24U) | ((_d[2] & (0xFFU)) << 16U) | ((_d[1] & (0xFFU)) << 8U) | (_d[0] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < VAU2_INVRL_Hash_Resp_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_VAU2_INVRL_Hash_Resp_candb(&_m->mon1, VAU2_INVRL_Hash_Resp_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return VAU2_INVRL_Hash_Resp_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_VAU2_INVRL_Hash_Resp_candb(VAU2_INVRL_Hash_Resp_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(VAU2_INVRL_Hash_Resp_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->VAU2_INVRL_Hash_Resp & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->VAU2_INVRL_Hash_Resp >> 8U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->VAU2_INVRL_Hash_Resp >> 16U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->VAU2_INVRL_Hash_Resp >> 24U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->VAU2_INVRL_Hash_Resp >> 32U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->VAU2_INVRL_Hash_Resp >> 40U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->VAU2_INVRL_Hash_Resp >> 48U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( ((_m->VAU2_INVRL_Hash_Resp >> 56U) & (0xFFU)) ); + + cframe->MsgId = (uint32_t) VAU2_INVRL_Hash_Resp_CANID; + cframe->DLC = (uint8_t) VAU2_INVRL_Hash_Resp_DLC; + cframe->IDE = (uint8_t) VAU2_INVRL_Hash_Resp_IDE; + return VAU2_INVRL_Hash_Resp_CANID; +} + +#else + +uint32_t Pack_VAU2_INVRL_Hash_Resp_candb(VAU2_INVRL_Hash_Resp_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(VAU2_INVRL_Hash_Resp_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->VAU2_INVRL_Hash_Resp & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->VAU2_INVRL_Hash_Resp >> 8U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->VAU2_INVRL_Hash_Resp >> 16U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->VAU2_INVRL_Hash_Resp >> 24U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->VAU2_INVRL_Hash_Resp >> 32U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->VAU2_INVRL_Hash_Resp >> 40U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->VAU2_INVRL_Hash_Resp >> 48U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( ((_m->VAU2_INVRL_Hash_Resp >> 56U) & (0xFFU)) ); + + *_len = (uint8_t) VAU2_INVRL_Hash_Resp_DLC; + *_ide = (uint8_t) VAU2_INVRL_Hash_Resp_IDE; + return VAU2_INVRL_Hash_Resp_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_WChF_NFC_VAU_Transfer_State_candb(WChF_NFC_VAU_Transfer_State_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->WChF_NFC_FrameNumber_Val_ro = (uint8_t) ( (_d[0] & (0x0FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->WChF_NFC_FrameNumber_Val_phys = (uint8_t) CANDB_WChF_NFC_FrameNumber_Val_ro_fromS(_m->WChF_NFC_FrameNumber_Val_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->WChF_NFCFrameTotalNum_Val = (uint8_t) ( ((_d[0] >> 4U) & (0x0FU)) ); + _m->WChF_NFCTransferData_Val = (uint64_t) ( ((uint64_t)(_d[7] & (0xFFU)) << 48U) | ((uint64_t)(_d[6] & (0xFFU)) << 40U) | ((uint64_t)(_d[5] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[3] & (0xFFU)) << 16U) | ((_d[2] & (0xFFU)) << 8U) | (_d[1] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < WChF_NFC_VAU_Transfer_State_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_WChF_NFC_VAU_Transfer_State_candb(&_m->mon1, WChF_NFC_VAU_Transfer_State_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return WChF_NFC_VAU_Transfer_State_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_WChF_NFC_VAU_Transfer_State_candb(WChF_NFC_VAU_Transfer_State_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(WChF_NFC_VAU_Transfer_State_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->WChF_NFC_FrameNumber_Val_ro = (uint8_t) CANDB_WChF_NFC_FrameNumber_Val_ro_toS(_m->WChF_NFC_FrameNumber_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->WChF_NFC_FrameNumber_Val_ro & (0x0FU)) | ((_m->WChF_NFCFrameTotalNum_Val & (0x0FU)) << 4U) ); + cframe->Data[1] |= (uint8_t) ( (_m->WChF_NFCTransferData_Val & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->WChF_NFCTransferData_Val >> 8U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->WChF_NFCTransferData_Val >> 16U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->WChF_NFCTransferData_Val >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->WChF_NFCTransferData_Val >> 32U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->WChF_NFCTransferData_Val >> 40U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( ((_m->WChF_NFCTransferData_Val >> 48U) & (0xFFU)) ); + + cframe->MsgId = (uint32_t) WChF_NFC_VAU_Transfer_State_CANID; + cframe->DLC = (uint8_t) WChF_NFC_VAU_Transfer_State_DLC; + cframe->IDE = (uint8_t) WChF_NFC_VAU_Transfer_State_IDE; + return WChF_NFC_VAU_Transfer_State_CANID; +} + +#else + +uint32_t Pack_WChF_NFC_VAU_Transfer_State_candb(WChF_NFC_VAU_Transfer_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(WChF_NFC_VAU_Transfer_State_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->WChF_NFC_FrameNumber_Val_ro = (uint8_t) CANDB_WChF_NFC_FrameNumber_Val_ro_toS(_m->WChF_NFC_FrameNumber_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->WChF_NFC_FrameNumber_Val_ro & (0x0FU)) | ((_m->WChF_NFCFrameTotalNum_Val & (0x0FU)) << 4U) ); + _d[1] |= (uint8_t) ( (_m->WChF_NFCTransferData_Val & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->WChF_NFCTransferData_Val >> 8U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->WChF_NFCTransferData_Val >> 16U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->WChF_NFCTransferData_Val >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->WChF_NFCTransferData_Val >> 32U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->WChF_NFCTransferData_Val >> 40U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( ((_m->WChF_NFCTransferData_Val >> 48U) & (0xFFU)) ); + + *_len = (uint8_t) WChF_NFC_VAU_Transfer_State_DLC; + *_ide = (uint8_t) WChF_NFC_VAU_Transfer_State_IDE; + return WChF_NFC_VAU_Transfer_State_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_VAU2_INVRR_Hash_Resp_candb(VAU2_INVRR_Hash_Resp_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->VAU2_INVRR_Hash_Resp = (uint64_t) ( ((uint64_t)(_d[7] & (0xFFU)) << 56U) | ((uint64_t)(_d[6] & (0xFFU)) << 48U) | ((uint64_t)(_d[5] & (0xFFU)) << 40U) | ((uint64_t)(_d[4] & (0xFFU)) << 32U) | ((_d[3] & (0xFFU)) << 24U) | ((_d[2] & (0xFFU)) << 16U) | ((_d[1] & (0xFFU)) << 8U) | (_d[0] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < VAU2_INVRR_Hash_Resp_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_VAU2_INVRR_Hash_Resp_candb(&_m->mon1, VAU2_INVRR_Hash_Resp_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return VAU2_INVRR_Hash_Resp_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_VAU2_INVRR_Hash_Resp_candb(VAU2_INVRR_Hash_Resp_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(VAU2_INVRR_Hash_Resp_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->VAU2_INVRR_Hash_Resp & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->VAU2_INVRR_Hash_Resp >> 8U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->VAU2_INVRR_Hash_Resp >> 16U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->VAU2_INVRR_Hash_Resp >> 24U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->VAU2_INVRR_Hash_Resp >> 32U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->VAU2_INVRR_Hash_Resp >> 40U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->VAU2_INVRR_Hash_Resp >> 48U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( ((_m->VAU2_INVRR_Hash_Resp >> 56U) & (0xFFU)) ); + + cframe->MsgId = (uint32_t) VAU2_INVRR_Hash_Resp_CANID; + cframe->DLC = (uint8_t) VAU2_INVRR_Hash_Resp_DLC; + cframe->IDE = (uint8_t) VAU2_INVRR_Hash_Resp_IDE; + return VAU2_INVRR_Hash_Resp_CANID; +} + +#else + +uint32_t Pack_VAU2_INVRR_Hash_Resp_candb(VAU2_INVRR_Hash_Resp_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(VAU2_INVRR_Hash_Resp_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->VAU2_INVRR_Hash_Resp & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->VAU2_INVRR_Hash_Resp >> 8U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->VAU2_INVRR_Hash_Resp >> 16U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->VAU2_INVRR_Hash_Resp >> 24U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->VAU2_INVRR_Hash_Resp >> 32U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->VAU2_INVRR_Hash_Resp >> 40U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->VAU2_INVRR_Hash_Resp >> 48U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( ((_m->VAU2_INVRR_Hash_Resp >> 56U) & (0xFFU)) ); + + *_len = (uint8_t) VAU2_INVRR_Hash_Resp_DLC; + *_ide = (uint8_t) VAU2_INVRR_Hash_Resp_IDE; + return VAU2_INVRR_Hash_Resp_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_VAU_SDM_Immo_Req_candb(VAU_SDM_Immo_Req_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->VAU_SDM_Immo_Req = (uint64_t) ( ((uint64_t)(_d[7] & (0xFFU)) << 56U) | ((uint64_t)(_d[6] & (0xFFU)) << 48U) | ((uint64_t)(_d[5] & (0xFFU)) << 40U) | ((uint64_t)(_d[4] & (0xFFU)) << 32U) | ((_d[3] & (0xFFU)) << 24U) | ((_d[2] & (0xFFU)) << 16U) | ((_d[1] & (0xFFU)) << 8U) | (_d[0] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < VAU_SDM_Immo_Req_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_VAU_SDM_Immo_Req_candb(&_m->mon1, VAU_SDM_Immo_Req_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return VAU_SDM_Immo_Req_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_VAU_SDM_Immo_Req_candb(VAU_SDM_Immo_Req_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(VAU_SDM_Immo_Req_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->VAU_SDM_Immo_Req & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->VAU_SDM_Immo_Req >> 8U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->VAU_SDM_Immo_Req >> 16U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->VAU_SDM_Immo_Req >> 24U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->VAU_SDM_Immo_Req >> 32U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->VAU_SDM_Immo_Req >> 40U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->VAU_SDM_Immo_Req >> 48U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( ((_m->VAU_SDM_Immo_Req >> 56U) & (0xFFU)) ); + + cframe->MsgId = (uint32_t) VAU_SDM_Immo_Req_CANID; + cframe->DLC = (uint8_t) VAU_SDM_Immo_Req_DLC; + cframe->IDE = (uint8_t) VAU_SDM_Immo_Req_IDE; + return VAU_SDM_Immo_Req_CANID; +} + +#else + +uint32_t Pack_VAU_SDM_Immo_Req_candb(VAU_SDM_Immo_Req_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(VAU_SDM_Immo_Req_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->VAU_SDM_Immo_Req & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->VAU_SDM_Immo_Req >> 8U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->VAU_SDM_Immo_Req >> 16U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->VAU_SDM_Immo_Req >> 24U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->VAU_SDM_Immo_Req >> 32U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->VAU_SDM_Immo_Req >> 40U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->VAU_SDM_Immo_Req >> 48U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( ((_m->VAU_SDM_Immo_Req >> 56U) & (0xFFU)) ); + + *_len = (uint8_t) VAU_SDM_Immo_Req_DLC; + *_ide = (uint8_t) VAU_SDM_Immo_Req_IDE; + return VAU_SDM_Immo_Req_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SDM_VAU_Hash_Resp_candb(SDM_VAU_Hash_Resp_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->SDM_VAU_Hash_RESC = (uint64_t) ( ((uint64_t)(_d[7] & (0xFFU)) << 56U) | ((uint64_t)(_d[6] & (0xFFU)) << 48U) | ((uint64_t)(_d[5] & (0xFFU)) << 40U) | ((uint64_t)(_d[4] & (0xFFU)) << 32U) | ((_d[3] & (0xFFU)) << 24U) | ((_d[2] & (0xFFU)) << 16U) | ((_d[1] & (0xFFU)) << 8U) | (_d[0] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < SDM_VAU_Hash_Resp_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_SDM_VAU_Hash_Resp_candb(&_m->mon1, SDM_VAU_Hash_Resp_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return SDM_VAU_Hash_Resp_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_SDM_VAU_Hash_Resp_candb(SDM_VAU_Hash_Resp_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SDM_VAU_Hash_Resp_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->SDM_VAU_Hash_RESC & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->SDM_VAU_Hash_RESC >> 8U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->SDM_VAU_Hash_RESC >> 16U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->SDM_VAU_Hash_RESC >> 24U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->SDM_VAU_Hash_RESC >> 32U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->SDM_VAU_Hash_RESC >> 40U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->SDM_VAU_Hash_RESC >> 48U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( ((_m->SDM_VAU_Hash_RESC >> 56U) & (0xFFU)) ); + + cframe->MsgId = (uint32_t) SDM_VAU_Hash_Resp_CANID; + cframe->DLC = (uint8_t) SDM_VAU_Hash_Resp_DLC; + cframe->IDE = (uint8_t) SDM_VAU_Hash_Resp_IDE; + return SDM_VAU_Hash_Resp_CANID; +} + +#else + +uint32_t Pack_SDM_VAU_Hash_Resp_candb(SDM_VAU_Hash_Resp_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SDM_VAU_Hash_Resp_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->SDM_VAU_Hash_RESC & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->SDM_VAU_Hash_RESC >> 8U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->SDM_VAU_Hash_RESC >> 16U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->SDM_VAU_Hash_RESC >> 24U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->SDM_VAU_Hash_RESC >> 32U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->SDM_VAU_Hash_RESC >> 40U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->SDM_VAU_Hash_RESC >> 48U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( ((_m->SDM_VAU_Hash_RESC >> 56U) & (0xFFU)) ); + + *_len = (uint8_t) SDM_VAU_Hash_Resp_DLC; + *_ide = (uint8_t) SDM_VAU_Hash_Resp_IDE; + return SDM_VAU_Hash_Resp_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_TCU_R932_1_candb(TCU_R932_1_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->numGearTarget = (uint8_t) ( (_d[0] & (0x0FU)) ); + _m->numGearEngaged = (uint8_t) ( ((_d[0] >> 4U) & (0x0FU)) ); + _m->ratEng2GbxTorqueRatio_ro = (uint16_t) ( ((_d[2] & (0x07U)) << 8U) | (_d[1] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->ratEng2GbxTorqueRatio_phys = (sigfloat_t)(CANDB_ratEng2GbxTorqueRatio_ro_fromS(_m->ratEng2GbxTorqueRatio_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->stGearLvr = (uint8_t) ( ((_d[2] >> 3U) & (0x07U)) ); + _m->stGbxMILReq = (uint8_t) ( ((_d[2] >> 6U) & (0x03U)) ); + _m->stGearboxMode = (uint8_t) ( (_d[3] & (0x07U)) ); + _m->stTransmissionWarnings = (uint8_t) ( ((_d[3] >> 3U) & (0x0FU)) ); + _m->bShiftInProgress = (uint8_t) ( ((_d[3] >> 7U) & (0x01U)) ); + _m->TCU_VehicleSpeed_ValueError = (uint8_t) ( (_d[4] & (0x01U)) ); + _m->stManualGbxMode = (uint8_t) ( ((_d[4] >> 1U) & (0x01U)) ); + _m->TCU_DriverBrakeReq = (uint8_t) ( ((_d[4] >> 2U) & (0x01U)) ); + _m->gearChangeSPDphase = (uint8_t) ( ((_d[4] >> 3U) & (0x01U)) ); + _m->TCU_VehicleSpeed_ro = (uint16_t) ( ((_d[6] & (0x0FU)) << 12U) | ((_d[5] & (0xFFU)) << 4U) | ((_d[4] >> 4U) & (0x0FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->TCU_VehicleSpeed_phys = (sigfloat_t)(CANDB_TCU_VehicleSpeed_ro_fromS(_m->TCU_VehicleSpeed_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->TCU_R932_1_RC = (uint8_t) ( ((_d[6] >> 4U) & (0x0FU)) ); + _m->TCU_R932_1_CS = (uint8_t) ( (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < TCU_R932_1_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_TCU_R932_1_candb(&_m->mon1, TCU_R932_1_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return TCU_R932_1_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_TCU_R932_1_candb(TCU_R932_1_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(TCU_R932_1_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->ratEng2GbxTorqueRatio_ro = (uint16_t) CANDB_ratEng2GbxTorqueRatio_ro_toS(_m->ratEng2GbxTorqueRatio_phys); + _m->TCU_VehicleSpeed_ro = (uint16_t) CANDB_TCU_VehicleSpeed_ro_toS(_m->TCU_VehicleSpeed_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->numGearTarget & (0x0FU)) | ((_m->numGearEngaged & (0x0FU)) << 4U) ); + cframe->Data[1] |= (uint8_t) ( (_m->ratEng2GbxTorqueRatio_ro & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->ratEng2GbxTorqueRatio_ro >> 8U) & (0x07U)) | ((_m->stGearLvr & (0x07U)) << 3U) | ((_m->stGbxMILReq & (0x03U)) << 6U) ); + cframe->Data[3] |= (uint8_t) ( (_m->stGearboxMode & (0x07U)) | ((_m->stTransmissionWarnings & (0x0FU)) << 3U) | ((_m->bShiftInProgress & (0x01U)) << 7U) ); + cframe->Data[4] |= (uint8_t) ( (_m->TCU_VehicleSpeed_ValueError & (0x01U)) | ((_m->stManualGbxMode & (0x01U)) << 1U) | ((_m->TCU_DriverBrakeReq & (0x01U)) << 2U) | ((_m->gearChangeSPDphase & (0x01U)) << 3U) | ((_m->TCU_VehicleSpeed_ro & (0x0FU)) << 4U) ); + cframe->Data[5] |= (uint8_t) ( ((_m->TCU_VehicleSpeed_ro >> 4U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->TCU_VehicleSpeed_ro >> 12U) & (0x0FU)) | ((_m->TCU_R932_1_RC & (0x0FU)) << 4U) ); + cframe->Data[7] |= (uint8_t) ( (_m->TCU_R932_1_CS & (0xFFU)) ); + + cframe->MsgId = (uint32_t) TCU_R932_1_CANID; + cframe->DLC = (uint8_t) TCU_R932_1_DLC; + cframe->IDE = (uint8_t) TCU_R932_1_IDE; + return TCU_R932_1_CANID; +} + +#else + +uint32_t Pack_TCU_R932_1_candb(TCU_R932_1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(TCU_R932_1_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->ratEng2GbxTorqueRatio_ro = (uint16_t) CANDB_ratEng2GbxTorqueRatio_ro_toS(_m->ratEng2GbxTorqueRatio_phys); + _m->TCU_VehicleSpeed_ro = (uint16_t) CANDB_TCU_VehicleSpeed_ro_toS(_m->TCU_VehicleSpeed_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->numGearTarget & (0x0FU)) | ((_m->numGearEngaged & (0x0FU)) << 4U) ); + _d[1] |= (uint8_t) ( (_m->ratEng2GbxTorqueRatio_ro & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->ratEng2GbxTorqueRatio_ro >> 8U) & (0x07U)) | ((_m->stGearLvr & (0x07U)) << 3U) | ((_m->stGbxMILReq & (0x03U)) << 6U) ); + _d[3] |= (uint8_t) ( (_m->stGearboxMode & (0x07U)) | ((_m->stTransmissionWarnings & (0x0FU)) << 3U) | ((_m->bShiftInProgress & (0x01U)) << 7U) ); + _d[4] |= (uint8_t) ( (_m->TCU_VehicleSpeed_ValueError & (0x01U)) | ((_m->stManualGbxMode & (0x01U)) << 1U) | ((_m->TCU_DriverBrakeReq & (0x01U)) << 2U) | ((_m->gearChangeSPDphase & (0x01U)) << 3U) | ((_m->TCU_VehicleSpeed_ro & (0x0FU)) << 4U) ); + _d[5] |= (uint8_t) ( ((_m->TCU_VehicleSpeed_ro >> 4U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->TCU_VehicleSpeed_ro >> 12U) & (0x0FU)) | ((_m->TCU_R932_1_RC & (0x0FU)) << 4U) ); + _d[7] |= (uint8_t) ( (_m->TCU_R932_1_CS & (0xFFU)) ); + + *_len = (uint8_t) TCU_R932_1_DLC; + *_ide = (uint8_t) TCU_R932_1_IDE; + return TCU_R932_1_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_VAU2_INVF_Hash_Resp_candb(VAU2_INVF_Hash_Resp_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->VAU2_INVF_Hash_Resp = (uint64_t) ( ((uint64_t)(_d[7] & (0xFFU)) << 56U) | ((uint64_t)(_d[6] & (0xFFU)) << 48U) | ((uint64_t)(_d[5] & (0xFFU)) << 40U) | ((uint64_t)(_d[4] & (0xFFU)) << 32U) | ((_d[3] & (0xFFU)) << 24U) | ((_d[2] & (0xFFU)) << 16U) | ((_d[1] & (0xFFU)) << 8U) | (_d[0] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < VAU2_INVF_Hash_Resp_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_VAU2_INVF_Hash_Resp_candb(&_m->mon1, VAU2_INVF_Hash_Resp_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return VAU2_INVF_Hash_Resp_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_VAU2_INVF_Hash_Resp_candb(VAU2_INVF_Hash_Resp_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(VAU2_INVF_Hash_Resp_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->VAU2_INVF_Hash_Resp & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->VAU2_INVF_Hash_Resp >> 8U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->VAU2_INVF_Hash_Resp >> 16U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->VAU2_INVF_Hash_Resp >> 24U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->VAU2_INVF_Hash_Resp >> 32U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->VAU2_INVF_Hash_Resp >> 40U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->VAU2_INVF_Hash_Resp >> 48U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( ((_m->VAU2_INVF_Hash_Resp >> 56U) & (0xFFU)) ); + + cframe->MsgId = (uint32_t) VAU2_INVF_Hash_Resp_CANID; + cframe->DLC = (uint8_t) VAU2_INVF_Hash_Resp_DLC; + cframe->IDE = (uint8_t) VAU2_INVF_Hash_Resp_IDE; + return VAU2_INVF_Hash_Resp_CANID; +} + +#else + +uint32_t Pack_VAU2_INVF_Hash_Resp_candb(VAU2_INVF_Hash_Resp_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(VAU2_INVF_Hash_Resp_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->VAU2_INVF_Hash_Resp & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->VAU2_INVF_Hash_Resp >> 8U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->VAU2_INVF_Hash_Resp >> 16U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->VAU2_INVF_Hash_Resp >> 24U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->VAU2_INVF_Hash_Resp >> 32U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->VAU2_INVF_Hash_Resp >> 40U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->VAU2_INVF_Hash_Resp >> 48U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( ((_m->VAU2_INVF_Hash_Resp >> 56U) & (0xFFU)) ); + + *_len = (uint8_t) VAU2_INVF_Hash_Resp_DLC; + *_ide = (uint8_t) VAU2_INVF_Hash_Resp_IDE; + return VAU2_INVF_Hash_Resp_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FTCU_DAT1_candb(FTCU_DAT1_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->FTCU_MeasuredCurrentPump1_Val_ro = (uint16_t) ( ((_d[1] & (0x03U)) << 8U) | (_d[0] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->FTCU_MeasuredCurrentPump1_Val_phys = (sigfloat_t)(CANDB_FTCU_MeasuredCurrentPump1_Val_ro_fromS(_m->FTCU_MeasuredCurrentPump1_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->FTCU_MeasuredCurrentPump2_Val_ro = (uint16_t) ( ((_d[2] & (0x0FU)) << 6U) | ((_d[1] >> 2U) & (0x3FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->FTCU_MeasuredCurrentPump2_Val_phys = (sigfloat_t)(CANDB_FTCU_MeasuredCurrentPump2_Val_ro_fromS(_m->FTCU_MeasuredCurrentPump2_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->FTCU_EmtrPWMPump1_Val_ro = (uint16_t) ( ((_d[3] & (0x3FU)) << 4U) | ((_d[2] >> 4U) & (0x0FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->FTCU_EmtrPWMPump1_Val_phys = (sigfloat_t)(CANDB_FTCU_EmtrPWMPump1_Val_ro_fromS(_m->FTCU_EmtrPWMPump1_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->FTCU_EmtrPWMPump2_Val_ro = (uint16_t) ( ((_d[4] & (0xFFU)) << 2U) | ((_d[3] >> 6U) & (0x03U)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->FTCU_EmtrPWMPump2_Val_phys = (sigfloat_t)(CANDB_FTCU_EmtrPWMPump2_Val_ro_fromS(_m->FTCU_EmtrPWMPump2_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < FTCU_DAT1_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_FTCU_DAT1_candb(&_m->mon1, FTCU_DAT1_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return FTCU_DAT1_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_FTCU_DAT1_candb(FTCU_DAT1_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FTCU_DAT1_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->FTCU_MeasuredCurrentPump1_Val_ro = (uint16_t) CANDB_FTCU_MeasuredCurrentPump1_Val_ro_toS(_m->FTCU_MeasuredCurrentPump1_Val_phys); + _m->FTCU_MeasuredCurrentPump2_Val_ro = (uint16_t) CANDB_FTCU_MeasuredCurrentPump2_Val_ro_toS(_m->FTCU_MeasuredCurrentPump2_Val_phys); + _m->FTCU_EmtrPWMPump1_Val_ro = (uint16_t) CANDB_FTCU_EmtrPWMPump1_Val_ro_toS(_m->FTCU_EmtrPWMPump1_Val_phys); + _m->FTCU_EmtrPWMPump2_Val_ro = (uint16_t) CANDB_FTCU_EmtrPWMPump2_Val_ro_toS(_m->FTCU_EmtrPWMPump2_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->FTCU_MeasuredCurrentPump1_Val_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->FTCU_MeasuredCurrentPump1_Val_ro >> 8U) & (0x03U)) | ((_m->FTCU_MeasuredCurrentPump2_Val_ro & (0x3FU)) << 2U) ); + cframe->Data[2] |= (uint8_t) ( ((_m->FTCU_MeasuredCurrentPump2_Val_ro >> 6U) & (0x0FU)) | ((_m->FTCU_EmtrPWMPump1_Val_ro & (0x0FU)) << 4U) ); + cframe->Data[3] |= (uint8_t) ( ((_m->FTCU_EmtrPWMPump1_Val_ro >> 4U) & (0x3FU)) | ((_m->FTCU_EmtrPWMPump2_Val_ro & (0x03U)) << 6U) ); + cframe->Data[4] |= (uint8_t) ( ((_m->FTCU_EmtrPWMPump2_Val_ro >> 2U) & (0xFFU)) ); + + cframe->MsgId = (uint32_t) FTCU_DAT1_CANID; + cframe->DLC = (uint8_t) FTCU_DAT1_DLC; + cframe->IDE = (uint8_t) FTCU_DAT1_IDE; + return FTCU_DAT1_CANID; +} + +#else + +uint32_t Pack_FTCU_DAT1_candb(FTCU_DAT1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FTCU_DAT1_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->FTCU_MeasuredCurrentPump1_Val_ro = (uint16_t) CANDB_FTCU_MeasuredCurrentPump1_Val_ro_toS(_m->FTCU_MeasuredCurrentPump1_Val_phys); + _m->FTCU_MeasuredCurrentPump2_Val_ro = (uint16_t) CANDB_FTCU_MeasuredCurrentPump2_Val_ro_toS(_m->FTCU_MeasuredCurrentPump2_Val_phys); + _m->FTCU_EmtrPWMPump1_Val_ro = (uint16_t) CANDB_FTCU_EmtrPWMPump1_Val_ro_toS(_m->FTCU_EmtrPWMPump1_Val_phys); + _m->FTCU_EmtrPWMPump2_Val_ro = (uint16_t) CANDB_FTCU_EmtrPWMPump2_Val_ro_toS(_m->FTCU_EmtrPWMPump2_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->FTCU_MeasuredCurrentPump1_Val_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->FTCU_MeasuredCurrentPump1_Val_ro >> 8U) & (0x03U)) | ((_m->FTCU_MeasuredCurrentPump2_Val_ro & (0x3FU)) << 2U) ); + _d[2] |= (uint8_t) ( ((_m->FTCU_MeasuredCurrentPump2_Val_ro >> 6U) & (0x0FU)) | ((_m->FTCU_EmtrPWMPump1_Val_ro & (0x0FU)) << 4U) ); + _d[3] |= (uint8_t) ( ((_m->FTCU_EmtrPWMPump1_Val_ro >> 4U) & (0x3FU)) | ((_m->FTCU_EmtrPWMPump2_Val_ro & (0x03U)) << 6U) ); + _d[4] |= (uint8_t) ( ((_m->FTCU_EmtrPWMPump2_Val_ro >> 2U) & (0xFFU)) ); + + *_len = (uint8_t) FTCU_DAT1_DLC; + *_ide = (uint8_t) FTCU_DAT1_IDE; + return FTCU_DAT1_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FTCU_DAT2_candb(FTCU_DAT2_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->FTCU_FuelPressure_Val = (uint16_t) ( ((_d[1] & (0x03U)) << 8U) | (_d[0] & (0xFFU)) ); + _m->FTCU_Err_Stat = (uint8_t) ( ((_d[1] >> 2U) & (0x1FU)) ); + _m->FTCU_FuelPumpOK_1_Stat = (uint8_t) ( ((_d[2] & (0x01U)) << 1U) | ((_d[1] >> 7U) & (0x01U)) ); + _m->FTCU_FuelPumpOK_2_Stat = (uint8_t) ( ((_d[2] >> 1U) & (0x03U)) ); + _m->FTCU_St_Val = (uint8_t) ( ((_d[3] & (0x07U)) << 5U) | ((_d[2] >> 3U) & (0x1FU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < FTCU_DAT2_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_FTCU_DAT2_candb(&_m->mon1, FTCU_DAT2_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return FTCU_DAT2_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_FTCU_DAT2_candb(FTCU_DAT2_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FTCU_DAT2_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->FTCU_FuelPressure_Val & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->FTCU_FuelPressure_Val >> 8U) & (0x03U)) | ((_m->FTCU_Err_Stat & (0x1FU)) << 2U) | ((_m->FTCU_FuelPumpOK_1_Stat & (0x01U)) << 7U) ); + cframe->Data[2] |= (uint8_t) ( ((_m->FTCU_FuelPumpOK_1_Stat >> 1U) & (0x01U)) | ((_m->FTCU_FuelPumpOK_2_Stat & (0x03U)) << 1U) | ((_m->FTCU_St_Val & (0x1FU)) << 3U) ); + cframe->Data[3] |= (uint8_t) ( ((_m->FTCU_St_Val >> 5U) & (0x07U)) ); + + cframe->MsgId = (uint32_t) FTCU_DAT2_CANID; + cframe->DLC = (uint8_t) FTCU_DAT2_DLC; + cframe->IDE = (uint8_t) FTCU_DAT2_IDE; + return FTCU_DAT2_CANID; +} + +#else + +uint32_t Pack_FTCU_DAT2_candb(FTCU_DAT2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FTCU_DAT2_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->FTCU_FuelPressure_Val & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->FTCU_FuelPressure_Val >> 8U) & (0x03U)) | ((_m->FTCU_Err_Stat & (0x1FU)) << 2U) | ((_m->FTCU_FuelPumpOK_1_Stat & (0x01U)) << 7U) ); + _d[2] |= (uint8_t) ( ((_m->FTCU_FuelPumpOK_1_Stat >> 1U) & (0x01U)) | ((_m->FTCU_FuelPumpOK_2_Stat & (0x03U)) << 1U) | ((_m->FTCU_St_Val & (0x1FU)) << 3U) ); + _d[3] |= (uint8_t) ( ((_m->FTCU_St_Val >> 5U) & (0x07U)) ); + + *_len = (uint8_t) FTCU_DAT2_DLC; + *_ide = (uint8_t) FTCU_DAT2_IDE; + return FTCU_DAT2_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FTCU_DAT3_candb(FTCU_DAT3_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->FTCU_CPUTemperature_Val = (int16_t) __ext_sig__(( ((_d[1] & (0x03U)) << 8U) | (_d[0] & (0xFFU)) ), 10); + _m->FTCU_Ubat_Val_ro = (uint16_t) ( ((_d[2] & (0x1FU)) << 6U) | ((_d[1] >> 2U) & (0x3FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->FTCU_Ubat_Val_phys = (sigfloat_t)(CANDB_FTCU_Ubat_Val_ro_fromS(_m->FTCU_Ubat_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->FTCU_DesiredPressure_Val = (uint16_t) ( ((_d[3] & (0x7FU)) << 3U) | ((_d[2] >> 5U) & (0x07U)) ); + _m->FTCU_FuelConsumption_Val = (uint8_t) ( ((_d[4] & (0x7FU)) << 1U) | ((_d[3] >> 7U) & (0x01U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < FTCU_DAT3_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_FTCU_DAT3_candb(&_m->mon1, FTCU_DAT3_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return FTCU_DAT3_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_FTCU_DAT3_candb(FTCU_DAT3_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FTCU_DAT3_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->FTCU_Ubat_Val_ro = (uint16_t) CANDB_FTCU_Ubat_Val_ro_toS(_m->FTCU_Ubat_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->FTCU_CPUTemperature_Val & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->FTCU_CPUTemperature_Val >> 8U) & (0x03U)) | ((_m->FTCU_Ubat_Val_ro & (0x3FU)) << 2U) ); + cframe->Data[2] |= (uint8_t) ( ((_m->FTCU_Ubat_Val_ro >> 6U) & (0x1FU)) | ((_m->FTCU_DesiredPressure_Val & (0x07U)) << 5U) ); + cframe->Data[3] |= (uint8_t) ( ((_m->FTCU_DesiredPressure_Val >> 3U) & (0x7FU)) | ((_m->FTCU_FuelConsumption_Val & (0x01U)) << 7U) ); + cframe->Data[4] |= (uint8_t) ( ((_m->FTCU_FuelConsumption_Val >> 1U) & (0x7FU)) ); + + cframe->MsgId = (uint32_t) FTCU_DAT3_CANID; + cframe->DLC = (uint8_t) FTCU_DAT3_DLC; + cframe->IDE = (uint8_t) FTCU_DAT3_IDE; + return FTCU_DAT3_CANID; +} + +#else + +uint32_t Pack_FTCU_DAT3_candb(FTCU_DAT3_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FTCU_DAT3_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->FTCU_Ubat_Val_ro = (uint16_t) CANDB_FTCU_Ubat_Val_ro_toS(_m->FTCU_Ubat_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->FTCU_CPUTemperature_Val & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->FTCU_CPUTemperature_Val >> 8U) & (0x03U)) | ((_m->FTCU_Ubat_Val_ro & (0x3FU)) << 2U) ); + _d[2] |= (uint8_t) ( ((_m->FTCU_Ubat_Val_ro >> 6U) & (0x1FU)) | ((_m->FTCU_DesiredPressure_Val & (0x07U)) << 5U) ); + _d[3] |= (uint8_t) ( ((_m->FTCU_DesiredPressure_Val >> 3U) & (0x7FU)) | ((_m->FTCU_FuelConsumption_Val & (0x01U)) << 7U) ); + _d[4] |= (uint8_t) ( ((_m->FTCU_FuelConsumption_Val >> 1U) & (0x7FU)) ); + + *_len = (uint8_t) FTCU_DAT3_DLC; + *_ide = (uint8_t) FTCU_DAT3_IDE; + return FTCU_DAT3_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SCU_02_candb(SCU_02_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->SCU_LeftFrHeight_ro = (uint8_t) ( (_d[0] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SCU_LeftFrHeight_phys = (uint16_t) CANDB_SCU_LeftFrHeight_ro_fromS(_m->SCU_LeftFrHeight_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->SCU_RightFrHeight_ro = (uint8_t) ( (_d[1] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SCU_RightFrHeight_phys = (uint16_t) CANDB_SCU_RightFrHeight_ro_fromS(_m->SCU_RightFrHeight_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->SCU_LeftRearHeight_ro = (uint8_t) ( (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SCU_LeftRearHeight_phys = (uint16_t) CANDB_SCU_LeftRearHeight_ro_fromS(_m->SCU_LeftRearHeight_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->SCU_RightRearHeight_ro = (uint8_t) ( (_d[3] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SCU_RightRearHeight_phys = (uint16_t) CANDB_SCU_RightRearHeight_ro_fromS(_m->SCU_RightRearHeight_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->SCU_02_RC = (uint8_t) ( ((_d[4] >> 4U) & (0x0FU)) ); + _m->SCU_02_CS = (uint8_t) ( (_d[5] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < SCU_02_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_SCU_02_candb(&_m->mon1, SCU_02_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return SCU_02_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_SCU_02_candb(SCU_02_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SCU_02_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->SCU_LeftFrHeight_ro = (uint8_t) CANDB_SCU_LeftFrHeight_ro_toS(_m->SCU_LeftFrHeight_phys); + _m->SCU_RightFrHeight_ro = (uint8_t) CANDB_SCU_RightFrHeight_ro_toS(_m->SCU_RightFrHeight_phys); + _m->SCU_LeftRearHeight_ro = (uint8_t) CANDB_SCU_LeftRearHeight_ro_toS(_m->SCU_LeftRearHeight_phys); + _m->SCU_RightRearHeight_ro = (uint8_t) CANDB_SCU_RightRearHeight_ro_toS(_m->SCU_RightRearHeight_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->SCU_LeftFrHeight_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->SCU_RightFrHeight_ro & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->SCU_LeftRearHeight_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->SCU_RightRearHeight_ro & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->SCU_02_RC & (0x0FU)) << 4U) ); + cframe->Data[5] |= (uint8_t) ( (_m->SCU_02_CS & (0xFFU)) ); + + cframe->MsgId = (uint32_t) SCU_02_CANID; + cframe->DLC = (uint8_t) SCU_02_DLC; + cframe->IDE = (uint8_t) SCU_02_IDE; + return SCU_02_CANID; +} + +#else + +uint32_t Pack_SCU_02_candb(SCU_02_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SCU_02_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->SCU_LeftFrHeight_ro = (uint8_t) CANDB_SCU_LeftFrHeight_ro_toS(_m->SCU_LeftFrHeight_phys); + _m->SCU_RightFrHeight_ro = (uint8_t) CANDB_SCU_RightFrHeight_ro_toS(_m->SCU_RightFrHeight_phys); + _m->SCU_LeftRearHeight_ro = (uint8_t) CANDB_SCU_LeftRearHeight_ro_toS(_m->SCU_LeftRearHeight_phys); + _m->SCU_RightRearHeight_ro = (uint8_t) CANDB_SCU_RightRearHeight_ro_toS(_m->SCU_RightRearHeight_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->SCU_LeftFrHeight_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( (_m->SCU_RightFrHeight_ro & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->SCU_LeftRearHeight_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->SCU_RightRearHeight_ro & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->SCU_02_RC & (0x0FU)) << 4U) ); + _d[5] |= (uint8_t) ( (_m->SCU_02_CS & (0xFFU)) ); + + *_len = (uint8_t) SCU_02_DLC; + *_ide = (uint8_t) SCU_02_IDE; + return SCU_02_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_ESC_04_candb(ESC_04_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->ESC_VehicleSpeed_ro = (uint16_t) ( ((_d[1] & (0xFFU)) << 8U) | (_d[0] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->ESC_VehicleSpeed_phys = (sigfloat_t)(CANDB_ESC_VehicleSpeed_ro_fromS(_m->ESC_VehicleSpeed_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->ESC_VehicleSpeed_ValueError = (uint8_t) ( (_d[2] & (0x01U)) ); + _m->ESC_Lamp = (uint8_t) ( ((_d[2] >> 1U) & (0x01U)) ); + _m->ESC_AVH_Active = (uint8_t) ( ((_d[2] >> 2U) & (0x01U)) ); + _m->ESC_Bls_Out = (uint8_t) ( ((_d[2] >> 3U) & (0x01U)) ); + _m->ESC_Bla = (uint8_t) ( ((_d[2] >> 4U) & (0x01U)) ); + _m->ESC_ABS_Lamp = (uint8_t) ( ((_d[2] >> 5U) & (0x01U)) ); + _m->ESC_EBD_Lamp = (uint8_t) ( ((_d[2] >> 6U) & (0x01U)) ); + _m->ESC_TCS_Fault = (uint8_t) ( ((_d[2] >> 7U) & (0x01U)) ); + _m->ESC_CDPDecelActive = (uint8_t) ( (_d[3] & (0x01U)) ); + _m->ESC_BLS_Fault = (uint8_t) ( ((_d[3] >> 1U) & (0x01U)) ); + _m->ESC_CtlActiveAbs = (uint8_t) ( ((_d[3] >> 2U) & (0x01U)) ); + _m->ESC_CtlActiveEbd = (uint8_t) ( ((_d[3] >> 3U) & (0x01U)) ); + _m->ESC_CtlActiveTcs = (uint8_t) ( ((_d[3] >> 4U) & (0x01U)) ); + _m->ESC_CtlActiveVdc = (uint8_t) ( ((_d[3] >> 5U) & (0x01U)) ); + _m->ESC_Passive_Lamp = (uint8_t) ( ((_d[3] >> 6U) & (0x01U)) ); + _m->ESC_Gearshift_Inhibit = (uint8_t) ( ((_d[3] >> 7U) & (0x01U)) ); + _m->ESC_HDC_Activated = (uint8_t) ( (_d[4] & (0x01U)) ); + _m->ESC_CtlActiveHDC = (uint8_t) ( ((_d[4] >> 1U) & (0x01U)) ); + _m->ESC_HDC_rejected = (uint8_t) ( ((_d[4] >> 2U) & (0x01U)) ); + _m->ESC_EmergencyBraking = (uint8_t) ( ((_d[4] >> 3U) & (0x01U)) ); + _m->ESC_RequestToEPB = (uint8_t) ( ((_d[4] >> 4U) & (0x03U)) ); + _m->ESC_CDPDecelAvailable = (uint8_t) ( ((_d[4] >> 6U) & (0x01U)) ); + _m->ESC_PEBWarningLampReq = (uint8_t) ( ((_d[4] >> 7U) & (0x01U)) ); + _m->ESC_HDC_SpeedLimit = (uint8_t) ( (_d[5] & (0xFFU)) ); + _m->CddActive_2 = (uint8_t) ( (_d[6] & (0x01U)) ); + _m->ESC_04_RC = (uint8_t) ( ((_d[6] >> 4U) & (0x0FU)) ); + _m->ESC_04_CS = (uint8_t) ( (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < ESC_04_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_ESC_04_candb(&_m->mon1, ESC_04_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return ESC_04_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_ESC_04_candb(ESC_04_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(ESC_04_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->ESC_VehicleSpeed_ro = (uint16_t) CANDB_ESC_VehicleSpeed_ro_toS(_m->ESC_VehicleSpeed_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->ESC_VehicleSpeed_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->ESC_VehicleSpeed_ro >> 8U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->ESC_VehicleSpeed_ValueError & (0x01U)) | ((_m->ESC_Lamp & (0x01U)) << 1U) | ((_m->ESC_AVH_Active & (0x01U)) << 2U) | ((_m->ESC_Bls_Out & (0x01U)) << 3U) | ((_m->ESC_Bla & (0x01U)) << 4U) | ((_m->ESC_ABS_Lamp & (0x01U)) << 5U) | ((_m->ESC_EBD_Lamp & (0x01U)) << 6U) | ((_m->ESC_TCS_Fault & (0x01U)) << 7U) ); + cframe->Data[3] |= (uint8_t) ( (_m->ESC_CDPDecelActive & (0x01U)) | ((_m->ESC_BLS_Fault & (0x01U)) << 1U) | ((_m->ESC_CtlActiveAbs & (0x01U)) << 2U) | ((_m->ESC_CtlActiveEbd & (0x01U)) << 3U) | ((_m->ESC_CtlActiveTcs & (0x01U)) << 4U) | ((_m->ESC_CtlActiveVdc & (0x01U)) << 5U) | ((_m->ESC_Passive_Lamp & (0x01U)) << 6U) | ((_m->ESC_Gearshift_Inhibit & (0x01U)) << 7U) ); + cframe->Data[4] |= (uint8_t) ( (_m->ESC_HDC_Activated & (0x01U)) | ((_m->ESC_CtlActiveHDC & (0x01U)) << 1U) | ((_m->ESC_HDC_rejected & (0x01U)) << 2U) | ((_m->ESC_EmergencyBraking & (0x01U)) << 3U) | ((_m->ESC_RequestToEPB & (0x03U)) << 4U) | ((_m->ESC_CDPDecelAvailable & (0x01U)) << 6U) | ((_m->ESC_PEBWarningLampReq & (0x01U)) << 7U) ); + cframe->Data[5] |= (uint8_t) ( (_m->ESC_HDC_SpeedLimit & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->CddActive_2 & (0x01U)) | ((_m->ESC_04_RC & (0x0FU)) << 4U) ); + cframe->Data[7] |= (uint8_t) ( (_m->ESC_04_CS & (0xFFU)) ); + + cframe->MsgId = (uint32_t) ESC_04_CANID; + cframe->DLC = (uint8_t) ESC_04_DLC; + cframe->IDE = (uint8_t) ESC_04_IDE; + return ESC_04_CANID; +} + +#else + +uint32_t Pack_ESC_04_candb(ESC_04_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(ESC_04_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->ESC_VehicleSpeed_ro = (uint16_t) CANDB_ESC_VehicleSpeed_ro_toS(_m->ESC_VehicleSpeed_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->ESC_VehicleSpeed_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->ESC_VehicleSpeed_ro >> 8U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->ESC_VehicleSpeed_ValueError & (0x01U)) | ((_m->ESC_Lamp & (0x01U)) << 1U) | ((_m->ESC_AVH_Active & (0x01U)) << 2U) | ((_m->ESC_Bls_Out & (0x01U)) << 3U) | ((_m->ESC_Bla & (0x01U)) << 4U) | ((_m->ESC_ABS_Lamp & (0x01U)) << 5U) | ((_m->ESC_EBD_Lamp & (0x01U)) << 6U) | ((_m->ESC_TCS_Fault & (0x01U)) << 7U) ); + _d[3] |= (uint8_t) ( (_m->ESC_CDPDecelActive & (0x01U)) | ((_m->ESC_BLS_Fault & (0x01U)) << 1U) | ((_m->ESC_CtlActiveAbs & (0x01U)) << 2U) | ((_m->ESC_CtlActiveEbd & (0x01U)) << 3U) | ((_m->ESC_CtlActiveTcs & (0x01U)) << 4U) | ((_m->ESC_CtlActiveVdc & (0x01U)) << 5U) | ((_m->ESC_Passive_Lamp & (0x01U)) << 6U) | ((_m->ESC_Gearshift_Inhibit & (0x01U)) << 7U) ); + _d[4] |= (uint8_t) ( (_m->ESC_HDC_Activated & (0x01U)) | ((_m->ESC_CtlActiveHDC & (0x01U)) << 1U) | ((_m->ESC_HDC_rejected & (0x01U)) << 2U) | ((_m->ESC_EmergencyBraking & (0x01U)) << 3U) | ((_m->ESC_RequestToEPB & (0x03U)) << 4U) | ((_m->ESC_CDPDecelAvailable & (0x01U)) << 6U) | ((_m->ESC_PEBWarningLampReq & (0x01U)) << 7U) ); + _d[5] |= (uint8_t) ( (_m->ESC_HDC_SpeedLimit & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->CddActive_2 & (0x01U)) | ((_m->ESC_04_RC & (0x0FU)) << 4U) ); + _d[7] |= (uint8_t) ( (_m->ESC_04_CS & (0xFFU)) ); + + *_len = (uint8_t) ESC_04_DLC; + *_ide = (uint8_t) ESC_04_IDE; + return ESC_04_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_ESC_09_candb(ESC_09_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->ESC_VacuumPressure_Val_ro = (uint8_t) ( (_d[0] & (0x1FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->ESC_VacuumPressure_Val_phys = (int8_t) CANDB_ESC_VacuumPressure_Val_ro_fromS(_m->ESC_VacuumPressure_Val_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->ESC_VacuumSignalReserved = (uint8_t) ( ((_d[0] >> 5U) & (0x03U)) ); + _m->ESC_BrakePressureMC_Val_ro = (uint16_t) ( ((_d[2] & (0x0FU)) << 8U) | (_d[1] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->ESC_BrakePressureMC_Val_phys = (sigfloat_t)(CANDB_ESC_BrakePressureMC_Val_ro_fromS(_m->ESC_BrakePressureMC_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->ESC_09_RC = (uint8_t) ( ((_d[2] >> 4U) & (0x0FU)) ); + _m->ESC_09_CS = (uint8_t) ( (_d[3] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < ESC_09_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_ESC_09_candb(&_m->mon1, ESC_09_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return ESC_09_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_ESC_09_candb(ESC_09_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(ESC_09_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->ESC_VacuumPressure_Val_ro = (uint8_t) CANDB_ESC_VacuumPressure_Val_ro_toS(_m->ESC_VacuumPressure_Val_phys); + _m->ESC_BrakePressureMC_Val_ro = (uint16_t) CANDB_ESC_BrakePressureMC_Val_ro_toS(_m->ESC_BrakePressureMC_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->ESC_VacuumPressure_Val_ro & (0x1FU)) | ((_m->ESC_VacuumSignalReserved & (0x03U)) << 5U) ); + cframe->Data[1] |= (uint8_t) ( (_m->ESC_BrakePressureMC_Val_ro & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->ESC_BrakePressureMC_Val_ro >> 8U) & (0x0FU)) | ((_m->ESC_09_RC & (0x0FU)) << 4U) ); + cframe->Data[3] |= (uint8_t) ( (_m->ESC_09_CS & (0xFFU)) ); + + cframe->MsgId = (uint32_t) ESC_09_CANID; + cframe->DLC = (uint8_t) ESC_09_DLC; + cframe->IDE = (uint8_t) ESC_09_IDE; + return ESC_09_CANID; +} + +#else + +uint32_t Pack_ESC_09_candb(ESC_09_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(ESC_09_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->ESC_VacuumPressure_Val_ro = (uint8_t) CANDB_ESC_VacuumPressure_Val_ro_toS(_m->ESC_VacuumPressure_Val_phys); + _m->ESC_BrakePressureMC_Val_ro = (uint16_t) CANDB_ESC_BrakePressureMC_Val_ro_toS(_m->ESC_BrakePressureMC_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->ESC_VacuumPressure_Val_ro & (0x1FU)) | ((_m->ESC_VacuumSignalReserved & (0x03U)) << 5U) ); + _d[1] |= (uint8_t) ( (_m->ESC_BrakePressureMC_Val_ro & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->ESC_BrakePressureMC_Val_ro >> 8U) & (0x0FU)) | ((_m->ESC_09_RC & (0x0FU)) << 4U) ); + _d[3] |= (uint8_t) ( (_m->ESC_09_CS & (0xFFU)) ); + + *_len = (uint8_t) ESC_09_DLC; + *_ide = (uint8_t) ESC_09_IDE; + return ESC_09_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_VAU2_Msg1_candb(VAU2_Msg1_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->VAU_Comm_Req = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->VAU_BCM_Authentication_Resp = (uint8_t) ( ((_d[0] >> 1U) & (0x0FU)) ); + _m->VAU_FL_DoorHandle_Req = (uint8_t) ( ((_d[0] >> 5U) & (0x07U)) ); + _m->VAU_FR_DoorHandle_Req = (uint8_t) ( (_d[1] & (0x07U)) ); + _m->VAU_RL_DoorHandle_Req = (uint8_t) ( ((_d[1] >> 3U) & (0x07U)) ); + _m->VAU_Alarm_Req = (uint8_t) ( ((_d[1] >> 6U) & (0x03U)) ); + _m->VAU_RR_DoorHandle_Req = (uint8_t) ( (_d[2] & (0x07U)) ); + _m->VAU_NFC_Cmd = (uint8_t) ( ((_d[2] >> 3U) & (0x07U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < VAU2_Msg1_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_VAU2_Msg1_candb(&_m->mon1, VAU2_Msg1_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return VAU2_Msg1_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_VAU2_Msg1_candb(VAU2_Msg1_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(VAU2_Msg1_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->VAU_Comm_Req & (0x01U)) | ((_m->VAU_BCM_Authentication_Resp & (0x0FU)) << 1U) | ((_m->VAU_FL_DoorHandle_Req & (0x07U)) << 5U) ); + cframe->Data[1] |= (uint8_t) ( (_m->VAU_FR_DoorHandle_Req & (0x07U)) | ((_m->VAU_RL_DoorHandle_Req & (0x07U)) << 3U) | ((_m->VAU_Alarm_Req & (0x03U)) << 6U) ); + cframe->Data[2] |= (uint8_t) ( (_m->VAU_RR_DoorHandle_Req & (0x07U)) | ((_m->VAU_NFC_Cmd & (0x07U)) << 3U) ); + + cframe->MsgId = (uint32_t) VAU2_Msg1_CANID; + cframe->DLC = (uint8_t) VAU2_Msg1_DLC; + cframe->IDE = (uint8_t) VAU2_Msg1_IDE; + return VAU2_Msg1_CANID; +} + +#else + +uint32_t Pack_VAU2_Msg1_candb(VAU2_Msg1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(VAU2_Msg1_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->VAU_Comm_Req & (0x01U)) | ((_m->VAU_BCM_Authentication_Resp & (0x0FU)) << 1U) | ((_m->VAU_FL_DoorHandle_Req & (0x07U)) << 5U) ); + _d[1] |= (uint8_t) ( (_m->VAU_FR_DoorHandle_Req & (0x07U)) | ((_m->VAU_RL_DoorHandle_Req & (0x07U)) << 3U) | ((_m->VAU_Alarm_Req & (0x03U)) << 6U) ); + _d[2] |= (uint8_t) ( (_m->VAU_RR_DoorHandle_Req & (0x07U)) | ((_m->VAU_NFC_Cmd & (0x07U)) << 3U) ); + + *_len = (uint8_t) VAU2_Msg1_DLC; + *_ide = (uint8_t) VAU2_Msg1_IDE; + return VAU2_Msg1_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_ESC_YRS_01_candb(ESC_YRS_01_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->ESC_PSIP1_Val_ro = (uint16_t) ( ((_d[1] & (0xFFU)) << 8U) | (_d[0] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->ESC_PSIP1_Val_phys = (sigfloat_t)(CANDB_ESC_PSIP1_Val_ro_fromS(_m->ESC_PSIP1_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->ESC_CLU_Stat = (uint8_t) ( (_d[2] & (0x0FU)) ); + _m->ESC_PSIP1_Stat = (uint8_t) ( ((_d[2] >> 4U) & (0x0FU)) ); + _m->ESC_Reserve1 = (uint8_t) ( (_d[3] & (0xFFU)) ); + _m->ESC_AY_Val_ro = (uint16_t) ( ((_d[5] & (0xFFU)) << 8U) | (_d[4] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->ESC_AY_Val_phys = (sigfloat_t)(CANDB_ESC_AY_Val_ro_fromS(_m->ESC_AY_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->ESC_YRS_01_RC = (uint8_t) ( (_d[6] & (0x0FU)) ); + _m->ESC_AY_Stat = (uint8_t) ( ((_d[6] >> 4U) & (0x0FU)) ); + _m->ESC_YRS_01_CS = (uint8_t) ( (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < ESC_YRS_01_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_ESC_YRS_01_candb(&_m->mon1, ESC_YRS_01_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return ESC_YRS_01_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_ESC_YRS_01_candb(ESC_YRS_01_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(ESC_YRS_01_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->ESC_PSIP1_Val_ro = (uint16_t) CANDB_ESC_PSIP1_Val_ro_toS(_m->ESC_PSIP1_Val_phys); + _m->ESC_AY_Val_ro = (uint16_t) CANDB_ESC_AY_Val_ro_toS(_m->ESC_AY_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->ESC_PSIP1_Val_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->ESC_PSIP1_Val_ro >> 8U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->ESC_CLU_Stat & (0x0FU)) | ((_m->ESC_PSIP1_Stat & (0x0FU)) << 4U) ); + cframe->Data[3] |= (uint8_t) ( (_m->ESC_Reserve1 & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->ESC_AY_Val_ro & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->ESC_AY_Val_ro >> 8U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->ESC_YRS_01_RC & (0x0FU)) | ((_m->ESC_AY_Stat & (0x0FU)) << 4U) ); + cframe->Data[7] |= (uint8_t) ( (_m->ESC_YRS_01_CS & (0xFFU)) ); + + cframe->MsgId = (uint32_t) ESC_YRS_01_CANID; + cframe->DLC = (uint8_t) ESC_YRS_01_DLC; + cframe->IDE = (uint8_t) ESC_YRS_01_IDE; + return ESC_YRS_01_CANID; +} + +#else + +uint32_t Pack_ESC_YRS_01_candb(ESC_YRS_01_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(ESC_YRS_01_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->ESC_PSIP1_Val_ro = (uint16_t) CANDB_ESC_PSIP1_Val_ro_toS(_m->ESC_PSIP1_Val_phys); + _m->ESC_AY_Val_ro = (uint16_t) CANDB_ESC_AY_Val_ro_toS(_m->ESC_AY_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->ESC_PSIP1_Val_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->ESC_PSIP1_Val_ro >> 8U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->ESC_CLU_Stat & (0x0FU)) | ((_m->ESC_PSIP1_Stat & (0x0FU)) << 4U) ); + _d[3] |= (uint8_t) ( (_m->ESC_Reserve1 & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->ESC_AY_Val_ro & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->ESC_AY_Val_ro >> 8U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->ESC_YRS_01_RC & (0x0FU)) | ((_m->ESC_AY_Stat & (0x0FU)) << 4U) ); + _d[7] |= (uint8_t) ( (_m->ESC_YRS_01_CS & (0xFFU)) ); + + *_len = (uint8_t) ESC_YRS_01_DLC; + *_ide = (uint8_t) ESC_YRS_01_IDE; + return ESC_YRS_01_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_EMS_Veh_candb(EMS_Veh_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->EMS_nICEngineSpeed3_Val_ro = (uint16_t) ( ((_d[1] & (0xFFU)) << 8U) | (_d[0] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->EMS_nICEngineSpeed3_Val_phys = (sigfloat_t)(CANDB_EMS_nICEngineSpeed3_Val_ro_fromS(_m->EMS_nICEngineSpeed3_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->EMS_EngCoolTemp_Val_ro = (uint8_t) ( (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->EMS_EngCoolTemp_Val_phys = (int16_t) CANDB_EMS_EngCoolTemp_Val_ro_fromS(_m->EMS_EngCoolTemp_Val_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->EMS_BARO_ENG_Val = (uint8_t) ( (_d[3] & (0xFFU)) ); + _m->EMS_AccelPdlPosnOBD_Val = (uint8_t) ( (_d[4] & (0xFFU)) ); + _m->EMS_EngTrqStatic_Val_ro = (uint16_t) ( ((_d[6] & (0x1FU)) << 8U) | (_d[5] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->EMS_EngTrqStatic_Val_phys = (sigfloat_t)(CANDB_EMS_EngTrqStatic_Val_ro_fromS(_m->EMS_EngTrqStatic_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->EMS_HvSystemFailure = (uint8_t) ( ((_d[6] >> 5U) & (0x03U)) ); + _m->EMS_CoolLiquidLowWarning = (uint8_t) ( ((_d[6] >> 7U) & (0x01U)) ); + _m->EMS_InstFuelConsumption = (uint8_t) ( (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < EMS_Veh_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_EMS_Veh_candb(&_m->mon1, EMS_Veh_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return EMS_Veh_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_EMS_Veh_candb(EMS_Veh_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(EMS_Veh_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->EMS_nICEngineSpeed3_Val_ro = (uint16_t) CANDB_EMS_nICEngineSpeed3_Val_ro_toS(_m->EMS_nICEngineSpeed3_Val_phys); + _m->EMS_EngCoolTemp_Val_ro = (uint8_t) CANDB_EMS_EngCoolTemp_Val_ro_toS(_m->EMS_EngCoolTemp_Val_phys); + _m->EMS_EngTrqStatic_Val_ro = (uint16_t) CANDB_EMS_EngTrqStatic_Val_ro_toS(_m->EMS_EngTrqStatic_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->EMS_nICEngineSpeed3_Val_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->EMS_nICEngineSpeed3_Val_ro >> 8U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->EMS_EngCoolTemp_Val_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->EMS_BARO_ENG_Val & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->EMS_AccelPdlPosnOBD_Val & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->EMS_EngTrqStatic_Val_ro & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->EMS_EngTrqStatic_Val_ro >> 8U) & (0x1FU)) | ((_m->EMS_HvSystemFailure & (0x03U)) << 5U) | ((_m->EMS_CoolLiquidLowWarning & (0x01U)) << 7U) ); + cframe->Data[7] |= (uint8_t) ( (_m->EMS_InstFuelConsumption & (0xFFU)) ); + + cframe->MsgId = (uint32_t) EMS_Veh_CANID; + cframe->DLC = (uint8_t) EMS_Veh_DLC; + cframe->IDE = (uint8_t) EMS_Veh_IDE; + return EMS_Veh_CANID; +} + +#else + +uint32_t Pack_EMS_Veh_candb(EMS_Veh_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(EMS_Veh_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->EMS_nICEngineSpeed3_Val_ro = (uint16_t) CANDB_EMS_nICEngineSpeed3_Val_ro_toS(_m->EMS_nICEngineSpeed3_Val_phys); + _m->EMS_EngCoolTemp_Val_ro = (uint8_t) CANDB_EMS_EngCoolTemp_Val_ro_toS(_m->EMS_EngCoolTemp_Val_phys); + _m->EMS_EngTrqStatic_Val_ro = (uint16_t) CANDB_EMS_EngTrqStatic_Val_ro_toS(_m->EMS_EngTrqStatic_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->EMS_nICEngineSpeed3_Val_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->EMS_nICEngineSpeed3_Val_ro >> 8U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->EMS_EngCoolTemp_Val_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->EMS_BARO_ENG_Val & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->EMS_AccelPdlPosnOBD_Val & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->EMS_EngTrqStatic_Val_ro & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->EMS_EngTrqStatic_Val_ro >> 8U) & (0x1FU)) | ((_m->EMS_HvSystemFailure & (0x03U)) << 5U) | ((_m->EMS_CoolLiquidLowWarning & (0x01U)) << 7U) ); + _d[7] |= (uint8_t) ( (_m->EMS_InstFuelConsumption & (0xFFU)) ); + + *_len = (uint8_t) EMS_Veh_DLC; + *_ide = (uint8_t) EMS_Veh_IDE; + return EMS_Veh_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_EMS_Indicators_candb(EMS_Indicators_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->EMS_EngOilTemp_Val_ro = (uint8_t) ( (_d[0] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->EMS_EngOilTemp_Val_phys = (int16_t) CANDB_EMS_EngOilTemp_Val_ro_fromS(_m->EMS_EngOilTemp_Val_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->EMS_OilLvl_Val_ro = (uint8_t) ( (_d[1] & (0x7FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->EMS_OilLvl_Val_phys = (sigfloat_t)(CANDB_EMS_OilLvl_Val_ro_fromS(_m->EMS_OilLvl_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->EMS_MILblink_Req = (uint8_t) ( (_d[2] & (0x01U)) ); + _m->EMS_EngOilLvInd_Stat = (uint8_t) ( ((_d[2] >> 1U) & (0x03U)) ); + _m->EMS_MILon_Req = (uint8_t) ( ((_d[2] >> 3U) & (0x01U)) ); + _m->EMS_LTCcoolantLvl_Stat = (uint8_t) ( ((_d[2] >> 4U) & (0x01U)) ); + _m->EMS_OilPresWarn_Stat = (uint8_t) ( ((_d[2] >> 5U) & (0x01U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < EMS_Indicators_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_EMS_Indicators_candb(&_m->mon1, EMS_Indicators_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return EMS_Indicators_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_EMS_Indicators_candb(EMS_Indicators_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(EMS_Indicators_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->EMS_EngOilTemp_Val_ro = (uint8_t) CANDB_EMS_EngOilTemp_Val_ro_toS(_m->EMS_EngOilTemp_Val_phys); + _m->EMS_OilLvl_Val_ro = (uint8_t) CANDB_EMS_OilLvl_Val_ro_toS(_m->EMS_OilLvl_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->EMS_EngOilTemp_Val_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->EMS_OilLvl_Val_ro & (0x7FU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->EMS_MILblink_Req & (0x01U)) | ((_m->EMS_EngOilLvInd_Stat & (0x03U)) << 1U) | ((_m->EMS_MILon_Req & (0x01U)) << 3U) | ((_m->EMS_LTCcoolantLvl_Stat & (0x01U)) << 4U) | ((_m->EMS_OilPresWarn_Stat & (0x01U)) << 5U) ); + + cframe->MsgId = (uint32_t) EMS_Indicators_CANID; + cframe->DLC = (uint8_t) EMS_Indicators_DLC; + cframe->IDE = (uint8_t) EMS_Indicators_IDE; + return EMS_Indicators_CANID; +} + +#else + +uint32_t Pack_EMS_Indicators_candb(EMS_Indicators_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(EMS_Indicators_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->EMS_EngOilTemp_Val_ro = (uint8_t) CANDB_EMS_EngOilTemp_Val_ro_toS(_m->EMS_EngOilTemp_Val_phys); + _m->EMS_OilLvl_Val_ro = (uint8_t) CANDB_EMS_OilLvl_Val_ro_toS(_m->EMS_OilLvl_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->EMS_EngOilTemp_Val_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( (_m->EMS_OilLvl_Val_ro & (0x7FU)) ); + _d[2] |= (uint8_t) ( (_m->EMS_MILblink_Req & (0x01U)) | ((_m->EMS_EngOilLvInd_Stat & (0x03U)) << 1U) | ((_m->EMS_MILon_Req & (0x01U)) << 3U) | ((_m->EMS_LTCcoolantLvl_Stat & (0x01U)) << 4U) | ((_m->EMS_OilPresWarn_Stat & (0x01U)) << 5U) ); + + *_len = (uint8_t) EMS_Indicators_DLC; + *_ide = (uint8_t) EMS_Indicators_IDE; + return EMS_Indicators_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_Powertrain_candb(BCM_Powertrain_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->BCM_AmbTempRaw_ro = (uint16_t) ( ((_d[1] & (0xFFU)) << 8U) | (_d[0] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_AmbTempRaw_phys = (sigfloat_t)(CANDB_BCM_AmbTempRaw_ro_fromS(_m->BCM_AmbTempRaw_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->AvgFuelLvl_ro = (uint16_t) ( ((_d[3] & (0x01U)) << 8U) | (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->AvgFuelLvl_phys = (sigfloat_t)(CANDB_AvgFuelLvl_ro_fromS(_m->AvgFuelLvl_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_T50_Request = (uint8_t) ( ((_d[3] >> 5U) & (0x01U)) ); + _m->RemoteICEStartReq = (uint8_t) ( ((_d[3] >> 6U) & (0x01U)) ); + _m->BCM_HVAC_Pump_Req = (uint8_t) ( ((_d[3] >> 7U) & (0x01U)) ); + _m->BCM_Powertrain_RC = (uint8_t) ( (_d[4] & (0x0FU)) ); + _m->BCM_VAU_Authorization_Req = (uint8_t) ( ((_d[4] >> 5U) & (0x07U)) ); + _m->BCM_Powertrain_CS = (uint8_t) ( (_d[5] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < BCM_Powertrain_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_BCM_Powertrain_candb(&_m->mon1, BCM_Powertrain_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return BCM_Powertrain_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_BCM_Powertrain_candb(BCM_Powertrain_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_Powertrain_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_AmbTempRaw_ro = (uint16_t) CANDB_BCM_AmbTempRaw_ro_toS(_m->BCM_AmbTempRaw_phys); + _m->AvgFuelLvl_ro = (uint16_t) CANDB_AvgFuelLvl_ro_toS(_m->AvgFuelLvl_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->BCM_AmbTempRaw_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->BCM_AmbTempRaw_ro >> 8U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->AvgFuelLvl_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->AvgFuelLvl_ro >> 8U) & (0x01U)) | ((_m->BCM_T50_Request & (0x01U)) << 5U) | ((_m->RemoteICEStartReq & (0x01U)) << 6U) | ((_m->BCM_HVAC_Pump_Req & (0x01U)) << 7U) ); + cframe->Data[4] |= (uint8_t) ( (_m->BCM_Powertrain_RC & (0x0FU)) | ((_m->BCM_VAU_Authorization_Req & (0x07U)) << 5U) ); + cframe->Data[5] |= (uint8_t) ( (_m->BCM_Powertrain_CS & (0xFFU)) ); + + cframe->MsgId = (uint32_t) BCM_Powertrain_CANID; + cframe->DLC = (uint8_t) BCM_Powertrain_DLC; + cframe->IDE = (uint8_t) BCM_Powertrain_IDE; + return BCM_Powertrain_CANID; +} + +#else + +uint32_t Pack_BCM_Powertrain_candb(BCM_Powertrain_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_Powertrain_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_AmbTempRaw_ro = (uint16_t) CANDB_BCM_AmbTempRaw_ro_toS(_m->BCM_AmbTempRaw_phys); + _m->AvgFuelLvl_ro = (uint16_t) CANDB_AvgFuelLvl_ro_toS(_m->AvgFuelLvl_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->BCM_AmbTempRaw_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->BCM_AmbTempRaw_ro >> 8U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->AvgFuelLvl_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->AvgFuelLvl_ro >> 8U) & (0x01U)) | ((_m->BCM_T50_Request & (0x01U)) << 5U) | ((_m->RemoteICEStartReq & (0x01U)) << 6U) | ((_m->BCM_HVAC_Pump_Req & (0x01U)) << 7U) ); + _d[4] |= (uint8_t) ( (_m->BCM_Powertrain_RC & (0x0FU)) | ((_m->BCM_VAU_Authorization_Req & (0x07U)) << 5U) ); + _d[5] |= (uint8_t) ( (_m->BCM_Powertrain_CS & (0xFFU)) ); + + *_len = (uint8_t) BCM_Powertrain_DLC; + *_ide = (uint8_t) BCM_Powertrain_IDE; + return BCM_Powertrain_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_EMS_Veh_02_candb(EMS_Veh_02_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->EMS_CoEng_Stat = (uint8_t) ( (_d[0] & (0x07U)) ); + _m->BMS_ActualTemp_Val_ro = (uint8_t) ( ((_d[1] & (0x07U)) << 5U) | ((_d[0] >> 3U) & (0x1FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BMS_ActualTemp_Val_phys = (sigfloat_t)(CANDB_BMS_ActualTemp_Val_ro_fromS(_m->BMS_ActualTemp_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->EMS_NAMI_Stat = (uint8_t) ( ((_d[1] >> 3U) & (0x01U)) ); + _m->EMS_Veh_02_RC = (uint8_t) ( ((_d[1] >> 4U) & (0x0FU)) ); + _m->EMS_Veh_02_CS = (uint8_t) ( (_d[2] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < EMS_Veh_02_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_EMS_Veh_02_candb(&_m->mon1, EMS_Veh_02_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return EMS_Veh_02_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_EMS_Veh_02_candb(EMS_Veh_02_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(EMS_Veh_02_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BMS_ActualTemp_Val_ro = (uint8_t) CANDB_BMS_ActualTemp_Val_ro_toS(_m->BMS_ActualTemp_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->EMS_CoEng_Stat & (0x07U)) | ((_m->BMS_ActualTemp_Val_ro & (0x1FU)) << 3U) ); + cframe->Data[1] |= (uint8_t) ( ((_m->BMS_ActualTemp_Val_ro >> 5U) & (0x07U)) | ((_m->EMS_NAMI_Stat & (0x01U)) << 3U) | ((_m->EMS_Veh_02_RC & (0x0FU)) << 4U) ); + cframe->Data[2] |= (uint8_t) ( (_m->EMS_Veh_02_CS & (0xFFU)) ); + + cframe->MsgId = (uint32_t) EMS_Veh_02_CANID; + cframe->DLC = (uint8_t) EMS_Veh_02_DLC; + cframe->IDE = (uint8_t) EMS_Veh_02_IDE; + return EMS_Veh_02_CANID; +} + +#else + +uint32_t Pack_EMS_Veh_02_candb(EMS_Veh_02_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(EMS_Veh_02_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BMS_ActualTemp_Val_ro = (uint8_t) CANDB_BMS_ActualTemp_Val_ro_toS(_m->BMS_ActualTemp_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->EMS_CoEng_Stat & (0x07U)) | ((_m->BMS_ActualTemp_Val_ro & (0x1FU)) << 3U) ); + _d[1] |= (uint8_t) ( ((_m->BMS_ActualTemp_Val_ro >> 5U) & (0x07U)) | ((_m->EMS_NAMI_Stat & (0x01U)) << 3U) | ((_m->EMS_Veh_02_RC & (0x0FU)) << 4U) ); + _d[2] |= (uint8_t) ( (_m->EMS_Veh_02_CS & (0xFFU)) ); + + *_len = (uint8_t) EMS_Veh_02_DLC; + *_ide = (uint8_t) EMS_Veh_02_IDE; + return EMS_Veh_02_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_EMS_EEM_01_candb(EMS_EEM_01_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->EMS_ActCurrLV_DCDC1_ro = (uint16_t) ( ((_d[1] & (0xFFU)) << 8U) | (_d[0] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->EMS_ActCurrLV_DCDC1_phys = (sigfloat_t)(CANDB_EMS_ActCurrLV_DCDC1_ro_fromS(_m->EMS_ActCurrLV_DCDC1_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->EMS_ActVoltLV_DCDC1_ro = (uint16_t) ( ((_d[3] & (0x03U)) << 8U) | (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->EMS_ActVoltLV_DCDC1_phys = (sigfloat_t)(CANDB_EMS_ActVoltLV_DCDC1_ro_fromS(_m->EMS_ActVoltLV_DCDC1_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->EMS_ErrPrfLim_DCDC1 = (uint8_t) ( ((_d[3] >> 2U) & (0x01U)) ); + _m->EMS_Err_DCDC1 = (uint8_t) ( ((_d[3] >> 3U) & (0x01U)) ); + _m->EMS_stMode_DCDC1 = (uint8_t) ( ((_d[3] >> 4U) & (0x01U)) ); + _m->EMS_UtilRate_DCDC1_ro = (uint16_t) ( ((_d[5] & (0x03U)) << 8U) | (_d[4] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->EMS_UtilRate_DCDC1_phys = (sigfloat_t)(CANDB_EMS_UtilRate_DCDC1_ro_fromS(_m->EMS_UtilRate_DCDC1_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->EMS_EEM_01_RC = (uint8_t) ( ((_d[5] >> 4U) & (0x0FU)) ); + _m->EMS_EEM_01_CS = (uint8_t) ( (_d[6] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < EMS_EEM_01_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_EMS_EEM_01_candb(&_m->mon1, EMS_EEM_01_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return EMS_EEM_01_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_EMS_EEM_01_candb(EMS_EEM_01_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(EMS_EEM_01_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->EMS_ActCurrLV_DCDC1_ro = (uint16_t) CANDB_EMS_ActCurrLV_DCDC1_ro_toS(_m->EMS_ActCurrLV_DCDC1_phys); + _m->EMS_ActVoltLV_DCDC1_ro = (uint16_t) CANDB_EMS_ActVoltLV_DCDC1_ro_toS(_m->EMS_ActVoltLV_DCDC1_phys); + _m->EMS_UtilRate_DCDC1_ro = (uint16_t) CANDB_EMS_UtilRate_DCDC1_ro_toS(_m->EMS_UtilRate_DCDC1_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->EMS_ActCurrLV_DCDC1_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->EMS_ActCurrLV_DCDC1_ro >> 8U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->EMS_ActVoltLV_DCDC1_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->EMS_ActVoltLV_DCDC1_ro >> 8U) & (0x03U)) | ((_m->EMS_ErrPrfLim_DCDC1 & (0x01U)) << 2U) | ((_m->EMS_Err_DCDC1 & (0x01U)) << 3U) | ((_m->EMS_stMode_DCDC1 & (0x01U)) << 4U) ); + cframe->Data[4] |= (uint8_t) ( (_m->EMS_UtilRate_DCDC1_ro & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->EMS_UtilRate_DCDC1_ro >> 8U) & (0x03U)) | ((_m->EMS_EEM_01_RC & (0x0FU)) << 4U) ); + cframe->Data[6] |= (uint8_t) ( (_m->EMS_EEM_01_CS & (0xFFU)) ); + + cframe->MsgId = (uint32_t) EMS_EEM_01_CANID; + cframe->DLC = (uint8_t) EMS_EEM_01_DLC; + cframe->IDE = (uint8_t) EMS_EEM_01_IDE; + return EMS_EEM_01_CANID; +} + +#else + +uint32_t Pack_EMS_EEM_01_candb(EMS_EEM_01_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(EMS_EEM_01_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->EMS_ActCurrLV_DCDC1_ro = (uint16_t) CANDB_EMS_ActCurrLV_DCDC1_ro_toS(_m->EMS_ActCurrLV_DCDC1_phys); + _m->EMS_ActVoltLV_DCDC1_ro = (uint16_t) CANDB_EMS_ActVoltLV_DCDC1_ro_toS(_m->EMS_ActVoltLV_DCDC1_phys); + _m->EMS_UtilRate_DCDC1_ro = (uint16_t) CANDB_EMS_UtilRate_DCDC1_ro_toS(_m->EMS_UtilRate_DCDC1_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->EMS_ActCurrLV_DCDC1_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->EMS_ActCurrLV_DCDC1_ro >> 8U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->EMS_ActVoltLV_DCDC1_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->EMS_ActVoltLV_DCDC1_ro >> 8U) & (0x03U)) | ((_m->EMS_ErrPrfLim_DCDC1 & (0x01U)) << 2U) | ((_m->EMS_Err_DCDC1 & (0x01U)) << 3U) | ((_m->EMS_stMode_DCDC1 & (0x01U)) << 4U) ); + _d[4] |= (uint8_t) ( (_m->EMS_UtilRate_DCDC1_ro & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->EMS_UtilRate_DCDC1_ro >> 8U) & (0x03U)) | ((_m->EMS_EEM_01_RC & (0x0FU)) << 4U) ); + _d[6] |= (uint8_t) ( (_m->EMS_EEM_01_CS & (0xFFU)) ); + + *_len = (uint8_t) EMS_EEM_01_DLC; + *_ide = (uint8_t) EMS_EEM_01_IDE; + return EMS_EEM_01_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_EMS_EEM_02_candb(EMS_EEM_02_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->EMS_ActCurrLV_DCDC2_ro = (uint16_t) ( ((_d[1] & (0xFFU)) << 8U) | (_d[0] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->EMS_ActCurrLV_DCDC2_phys = (sigfloat_t)(CANDB_EMS_ActCurrLV_DCDC2_ro_fromS(_m->EMS_ActCurrLV_DCDC2_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->EMS_ActVoltLV_DCDC2_ro = (uint16_t) ( ((_d[3] & (0x03U)) << 8U) | (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->EMS_ActVoltLV_DCDC2_phys = (sigfloat_t)(CANDB_EMS_ActVoltLV_DCDC2_ro_fromS(_m->EMS_ActVoltLV_DCDC2_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->EMS_ErrPrfLim_DCDC2 = (uint8_t) ( ((_d[3] >> 2U) & (0x01U)) ); + _m->EMS_Err_DCDC2 = (uint8_t) ( ((_d[3] >> 3U) & (0x01U)) ); + _m->EMS_stMode_DCDC2 = (uint8_t) ( ((_d[3] >> 4U) & (0x01U)) ); + _m->EMS_UtilRate_DCDC2_ro = (uint16_t) ( ((_d[5] & (0x03U)) << 8U) | (_d[4] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->EMS_UtilRate_DCDC2_phys = (sigfloat_t)(CANDB_EMS_UtilRate_DCDC2_ro_fromS(_m->EMS_UtilRate_DCDC2_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->EMS_EEM_02_RC = (uint8_t) ( ((_d[5] >> 4U) & (0x0FU)) ); + _m->EMS_EEM_02_CS = (uint8_t) ( (_d[6] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < EMS_EEM_02_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_EMS_EEM_02_candb(&_m->mon1, EMS_EEM_02_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return EMS_EEM_02_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_EMS_EEM_02_candb(EMS_EEM_02_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(EMS_EEM_02_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->EMS_ActCurrLV_DCDC2_ro = (uint16_t) CANDB_EMS_ActCurrLV_DCDC2_ro_toS(_m->EMS_ActCurrLV_DCDC2_phys); + _m->EMS_ActVoltLV_DCDC2_ro = (uint16_t) CANDB_EMS_ActVoltLV_DCDC2_ro_toS(_m->EMS_ActVoltLV_DCDC2_phys); + _m->EMS_UtilRate_DCDC2_ro = (uint16_t) CANDB_EMS_UtilRate_DCDC2_ro_toS(_m->EMS_UtilRate_DCDC2_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->EMS_ActCurrLV_DCDC2_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->EMS_ActCurrLV_DCDC2_ro >> 8U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->EMS_ActVoltLV_DCDC2_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->EMS_ActVoltLV_DCDC2_ro >> 8U) & (0x03U)) | ((_m->EMS_ErrPrfLim_DCDC2 & (0x01U)) << 2U) | ((_m->EMS_Err_DCDC2 & (0x01U)) << 3U) | ((_m->EMS_stMode_DCDC2 & (0x01U)) << 4U) ); + cframe->Data[4] |= (uint8_t) ( (_m->EMS_UtilRate_DCDC2_ro & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->EMS_UtilRate_DCDC2_ro >> 8U) & (0x03U)) | ((_m->EMS_EEM_02_RC & (0x0FU)) << 4U) ); + cframe->Data[6] |= (uint8_t) ( (_m->EMS_EEM_02_CS & (0xFFU)) ); + + cframe->MsgId = (uint32_t) EMS_EEM_02_CANID; + cframe->DLC = (uint8_t) EMS_EEM_02_DLC; + cframe->IDE = (uint8_t) EMS_EEM_02_IDE; + return EMS_EEM_02_CANID; +} + +#else + +uint32_t Pack_EMS_EEM_02_candb(EMS_EEM_02_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(EMS_EEM_02_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->EMS_ActCurrLV_DCDC2_ro = (uint16_t) CANDB_EMS_ActCurrLV_DCDC2_ro_toS(_m->EMS_ActCurrLV_DCDC2_phys); + _m->EMS_ActVoltLV_DCDC2_ro = (uint16_t) CANDB_EMS_ActVoltLV_DCDC2_ro_toS(_m->EMS_ActVoltLV_DCDC2_phys); + _m->EMS_UtilRate_DCDC2_ro = (uint16_t) CANDB_EMS_UtilRate_DCDC2_ro_toS(_m->EMS_UtilRate_DCDC2_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->EMS_ActCurrLV_DCDC2_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->EMS_ActCurrLV_DCDC2_ro >> 8U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->EMS_ActVoltLV_DCDC2_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->EMS_ActVoltLV_DCDC2_ro >> 8U) & (0x03U)) | ((_m->EMS_ErrPrfLim_DCDC2 & (0x01U)) << 2U) | ((_m->EMS_Err_DCDC2 & (0x01U)) << 3U) | ((_m->EMS_stMode_DCDC2 & (0x01U)) << 4U) ); + _d[4] |= (uint8_t) ( (_m->EMS_UtilRate_DCDC2_ro & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->EMS_UtilRate_DCDC2_ro >> 8U) & (0x03U)) | ((_m->EMS_EEM_02_RC & (0x0FU)) << 4U) ); + _d[6] |= (uint8_t) ( (_m->EMS_EEM_02_CS & (0xFFU)) ); + + *_len = (uint8_t) EMS_EEM_02_DLC; + *_ide = (uint8_t) EMS_EEM_02_IDE; + return EMS_EEM_02_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_EEM_candb(BCM_EEM_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->BCM_EEM_VolReqLV_DCDC1_ro = (uint16_t) ( ((_d[1] & (0x03U)) << 8U) | (_d[0] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_EEM_VolReqLV_DCDC1_phys = (sigfloat_t)(CANDB_BCM_EEM_VolReqLV_DCDC1_ro_fromS(_m->BCM_EEM_VolReqLV_DCDC1_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_EEM_StPowMgn = (uint8_t) ( ((_d[1] >> 2U) & (0x07U)) ); + _m->BCM_EEM_PowMngtReqDisp = (uint8_t) ( ((_d[1] >> 5U) & (0x01U)) ); + _m->BCM_EEM_VolReqLV_DCDC2_ro = (uint16_t) ( ((_d[3] & (0x03U)) << 8U) | (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_EEM_VolReqLV_DCDC2_phys = (sigfloat_t)(CANDB_BCM_EEM_VolReqLV_DCDC2_ro_fromS(_m->BCM_EEM_VolReqLV_DCDC2_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_EEM_RC = (uint8_t) ( ((_d[3] >> 4U) & (0x0FU)) ); + _m->BCM_EEM_CS = (uint8_t) ( (_d[4] & (0xFFU)) ); + _m->BCM_EEM_CurrLimLV_DCDC1_ro = (uint16_t) ( ((_d[6] & (0x0FU)) << 8U) | (_d[5] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_EEM_CurrLimLV_DCDC1_phys = (sigfloat_t)(CANDB_BCM_EEM_CurrLimLV_DCDC1_ro_fromS(_m->BCM_EEM_CurrLimLV_DCDC1_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_EEM_CurrLimLV_DCDC2_ro = (uint16_t) ( ((_d[7] & (0xFFU)) << 4U) | ((_d[6] >> 4U) & (0x0FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_EEM_CurrLimLV_DCDC2_phys = (sigfloat_t)(CANDB_BCM_EEM_CurrLimLV_DCDC2_ro_fromS(_m->BCM_EEM_CurrLimLV_DCDC2_ro)); +#endif // CANDB_USE_SIGFLOAT + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < BCM_EEM_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_BCM_EEM_candb(&_m->mon1, BCM_EEM_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return BCM_EEM_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_BCM_EEM_candb(BCM_EEM_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_EEM_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_EEM_VolReqLV_DCDC1_ro = (uint16_t) CANDB_BCM_EEM_VolReqLV_DCDC1_ro_toS(_m->BCM_EEM_VolReqLV_DCDC1_phys); + _m->BCM_EEM_VolReqLV_DCDC2_ro = (uint16_t) CANDB_BCM_EEM_VolReqLV_DCDC2_ro_toS(_m->BCM_EEM_VolReqLV_DCDC2_phys); + _m->BCM_EEM_CurrLimLV_DCDC1_ro = (uint16_t) CANDB_BCM_EEM_CurrLimLV_DCDC1_ro_toS(_m->BCM_EEM_CurrLimLV_DCDC1_phys); + _m->BCM_EEM_CurrLimLV_DCDC2_ro = (uint16_t) CANDB_BCM_EEM_CurrLimLV_DCDC2_ro_toS(_m->BCM_EEM_CurrLimLV_DCDC2_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->BCM_EEM_VolReqLV_DCDC1_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->BCM_EEM_VolReqLV_DCDC1_ro >> 8U) & (0x03U)) | ((_m->BCM_EEM_StPowMgn & (0x07U)) << 2U) | ((_m->BCM_EEM_PowMngtReqDisp & (0x01U)) << 5U) ); + cframe->Data[2] |= (uint8_t) ( (_m->BCM_EEM_VolReqLV_DCDC2_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->BCM_EEM_VolReqLV_DCDC2_ro >> 8U) & (0x03U)) | ((_m->BCM_EEM_RC & (0x0FU)) << 4U) ); + cframe->Data[4] |= (uint8_t) ( (_m->BCM_EEM_CS & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->BCM_EEM_CurrLimLV_DCDC1_ro & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->BCM_EEM_CurrLimLV_DCDC1_ro >> 8U) & (0x0FU)) | ((_m->BCM_EEM_CurrLimLV_DCDC2_ro & (0x0FU)) << 4U) ); + cframe->Data[7] |= (uint8_t) ( ((_m->BCM_EEM_CurrLimLV_DCDC2_ro >> 4U) & (0xFFU)) ); + + cframe->MsgId = (uint32_t) BCM_EEM_CANID; + cframe->DLC = (uint8_t) BCM_EEM_DLC; + cframe->IDE = (uint8_t) BCM_EEM_IDE; + return BCM_EEM_CANID; +} + +#else + +uint32_t Pack_BCM_EEM_candb(BCM_EEM_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_EEM_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_EEM_VolReqLV_DCDC1_ro = (uint16_t) CANDB_BCM_EEM_VolReqLV_DCDC1_ro_toS(_m->BCM_EEM_VolReqLV_DCDC1_phys); + _m->BCM_EEM_VolReqLV_DCDC2_ro = (uint16_t) CANDB_BCM_EEM_VolReqLV_DCDC2_ro_toS(_m->BCM_EEM_VolReqLV_DCDC2_phys); + _m->BCM_EEM_CurrLimLV_DCDC1_ro = (uint16_t) CANDB_BCM_EEM_CurrLimLV_DCDC1_ro_toS(_m->BCM_EEM_CurrLimLV_DCDC1_phys); + _m->BCM_EEM_CurrLimLV_DCDC2_ro = (uint16_t) CANDB_BCM_EEM_CurrLimLV_DCDC2_ro_toS(_m->BCM_EEM_CurrLimLV_DCDC2_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->BCM_EEM_VolReqLV_DCDC1_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->BCM_EEM_VolReqLV_DCDC1_ro >> 8U) & (0x03U)) | ((_m->BCM_EEM_StPowMgn & (0x07U)) << 2U) | ((_m->BCM_EEM_PowMngtReqDisp & (0x01U)) << 5U) ); + _d[2] |= (uint8_t) ( (_m->BCM_EEM_VolReqLV_DCDC2_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->BCM_EEM_VolReqLV_DCDC2_ro >> 8U) & (0x03U)) | ((_m->BCM_EEM_RC & (0x0FU)) << 4U) ); + _d[4] |= (uint8_t) ( (_m->BCM_EEM_CS & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->BCM_EEM_CurrLimLV_DCDC1_ro & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->BCM_EEM_CurrLimLV_DCDC1_ro >> 8U) & (0x0FU)) | ((_m->BCM_EEM_CurrLimLV_DCDC2_ro & (0x0FU)) << 4U) ); + _d[7] |= (uint8_t) ( ((_m->BCM_EEM_CurrLimLV_DCDC2_ro >> 4U) & (0xFFU)) ); + + *_len = (uint8_t) BCM_EEM_DLC; + *_ide = (uint8_t) BCM_EEM_IDE; + return BCM_EEM_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_DAS_01_candb(DAS_01_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->DAS_CcAfsDecel_Req_ro = (uint16_t) ( ((_d[1] & (0xFFU)) << 8U) | (_d[0] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->DAS_CcAfsDecel_Req_phys = (sigfloat_t)(CANDB_DAS_CcAfsDecel_Req_ro_fromS(_m->DAS_CcAfsDecel_Req_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->DAS_AebRdaDecel_Req_ro = (uint16_t) ( ((_d[3] & (0xFFU)) << 8U) | (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->DAS_AebRdaDecel_Req_phys = (sigfloat_t)(CANDB_DAS_AebRdaDecel_Req_ro_fromS(_m->DAS_AebRdaDecel_Req_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->DAS_CcBrakeLight_Req = (uint8_t) ( (_d[4] & (0x01U)) ); + _m->DAS_AebBoost_Req = (uint8_t) ( ((_d[4] >> 1U) & (0x01U)) ); + _m->DAS_AebPrefill_Req = (uint8_t) ( ((_d[4] >> 2U) & (0x01U)) ); + _m->DAS_AebPreCrash_Req = (uint8_t) ( ((_d[4] >> 3U) & (0x01U)) ); + _m->DAS_01_RC = (uint8_t) ( ((_d[4] >> 4U) & (0x0FU)) ); + _m->DAS_01_CS = (uint8_t) ( (_d[5] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < DAS_01_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_DAS_01_candb(&_m->mon1, DAS_01_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return DAS_01_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_DAS_01_candb(DAS_01_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(DAS_01_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->DAS_CcAfsDecel_Req_ro = (uint16_t) CANDB_DAS_CcAfsDecel_Req_ro_toS(_m->DAS_CcAfsDecel_Req_phys); + _m->DAS_AebRdaDecel_Req_ro = (uint16_t) CANDB_DAS_AebRdaDecel_Req_ro_toS(_m->DAS_AebRdaDecel_Req_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->DAS_CcAfsDecel_Req_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->DAS_CcAfsDecel_Req_ro >> 8U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->DAS_AebRdaDecel_Req_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->DAS_AebRdaDecel_Req_ro >> 8U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->DAS_CcBrakeLight_Req & (0x01U)) | ((_m->DAS_AebBoost_Req & (0x01U)) << 1U) | ((_m->DAS_AebPrefill_Req & (0x01U)) << 2U) | ((_m->DAS_AebPreCrash_Req & (0x01U)) << 3U) | ((_m->DAS_01_RC & (0x0FU)) << 4U) ); + cframe->Data[5] |= (uint8_t) ( (_m->DAS_01_CS & (0xFFU)) ); + + cframe->MsgId = (uint32_t) DAS_01_CANID; + cframe->DLC = (uint8_t) DAS_01_DLC; + cframe->IDE = (uint8_t) DAS_01_IDE; + return DAS_01_CANID; +} + +#else + +uint32_t Pack_DAS_01_candb(DAS_01_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(DAS_01_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->DAS_CcAfsDecel_Req_ro = (uint16_t) CANDB_DAS_CcAfsDecel_Req_ro_toS(_m->DAS_CcAfsDecel_Req_phys); + _m->DAS_AebRdaDecel_Req_ro = (uint16_t) CANDB_DAS_AebRdaDecel_Req_ro_toS(_m->DAS_AebRdaDecel_Req_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->DAS_CcAfsDecel_Req_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->DAS_CcAfsDecel_Req_ro >> 8U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->DAS_AebRdaDecel_Req_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->DAS_AebRdaDecel_Req_ro >> 8U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->DAS_CcBrakeLight_Req & (0x01U)) | ((_m->DAS_AebBoost_Req & (0x01U)) << 1U) | ((_m->DAS_AebPrefill_Req & (0x01U)) << 2U) | ((_m->DAS_AebPreCrash_Req & (0x01U)) << 3U) | ((_m->DAS_01_RC & (0x0FU)) << 4U) ); + _d[5] |= (uint8_t) ( (_m->DAS_01_CS & (0xFFU)) ); + + *_len = (uint8_t) DAS_01_DLC; + *_ide = (uint8_t) DAS_01_IDE; + return DAS_01_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_DAS_04_candb(DAS_04_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->DAS_AfsBrakeJerkLvl_Stat = (uint8_t) ( (_d[0] & (0xFFU)) ); + _m->DAS_CcDecelFlag_Req = (uint8_t) ( (_d[1] & (0x01U)) ); + _m->DAS_CcBrakeStandSt_Req = (uint8_t) ( ((_d[1] >> 1U) & (0x01U)) ); + _m->DAS_CcMode_Stat = (uint8_t) ( ((_d[1] >> 2U) & (0x03U)) ); + _m->DAS_AfsBrakeJerkEnab_Stat = (uint8_t) ( ((_d[1] >> 4U) & (0x01U)) ); + _m->DAS_AfsBrakeJerk_Req = (uint8_t) ( ((_d[1] >> 5U) & (0x01U)) ); + _m->DAS_CcBrakeRelease_Req = (uint8_t) ( ((_d[1] >> 6U) & (0x01U)) ); + _m->DAS_AebMode_Stat = (uint8_t) ( ((_d[1] >> 7U) & (0x01U)) ); + _m->DAS_AebDecelFlag_Req = (uint8_t) ( (_d[2] & (0x01U)) ); + _m->DAS_CcFuncError_Stat = (uint8_t) ( ((_d[2] >> 1U) & (0x01U)) ); + _m->DAS_AebRdaStand_Req = (uint8_t) ( ((_d[2] >> 2U) & (0x01U)) ); + _m->DAS_AebFuncError_Stat = (uint8_t) ( ((_d[2] >> 3U) & (0x01U)) ); + _m->DAS_04_RC = (uint8_t) ( ((_d[2] >> 4U) & (0x0FU)) ); + _m->DAS_04_CS = (uint8_t) ( (_d[3] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < DAS_04_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_DAS_04_candb(&_m->mon1, DAS_04_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return DAS_04_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_DAS_04_candb(DAS_04_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(DAS_04_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->DAS_AfsBrakeJerkLvl_Stat & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->DAS_CcDecelFlag_Req & (0x01U)) | ((_m->DAS_CcBrakeStandSt_Req & (0x01U)) << 1U) | ((_m->DAS_CcMode_Stat & (0x03U)) << 2U) | ((_m->DAS_AfsBrakeJerkEnab_Stat & (0x01U)) << 4U) | ((_m->DAS_AfsBrakeJerk_Req & (0x01U)) << 5U) | ((_m->DAS_CcBrakeRelease_Req & (0x01U)) << 6U) | ((_m->DAS_AebMode_Stat & (0x01U)) << 7U) ); + cframe->Data[2] |= (uint8_t) ( (_m->DAS_AebDecelFlag_Req & (0x01U)) | ((_m->DAS_CcFuncError_Stat & (0x01U)) << 1U) | ((_m->DAS_AebRdaStand_Req & (0x01U)) << 2U) | ((_m->DAS_AebFuncError_Stat & (0x01U)) << 3U) | ((_m->DAS_04_RC & (0x0FU)) << 4U) ); + cframe->Data[3] |= (uint8_t) ( (_m->DAS_04_CS & (0xFFU)) ); + + cframe->MsgId = (uint32_t) DAS_04_CANID; + cframe->DLC = (uint8_t) DAS_04_DLC; + cframe->IDE = (uint8_t) DAS_04_IDE; + return DAS_04_CANID; +} + +#else + +uint32_t Pack_DAS_04_candb(DAS_04_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(DAS_04_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->DAS_AfsBrakeJerkLvl_Stat & (0xFFU)) ); + _d[1] |= (uint8_t) ( (_m->DAS_CcDecelFlag_Req & (0x01U)) | ((_m->DAS_CcBrakeStandSt_Req & (0x01U)) << 1U) | ((_m->DAS_CcMode_Stat & (0x03U)) << 2U) | ((_m->DAS_AfsBrakeJerkEnab_Stat & (0x01U)) << 4U) | ((_m->DAS_AfsBrakeJerk_Req & (0x01U)) << 5U) | ((_m->DAS_CcBrakeRelease_Req & (0x01U)) << 6U) | ((_m->DAS_AebMode_Stat & (0x01U)) << 7U) ); + _d[2] |= (uint8_t) ( (_m->DAS_AebDecelFlag_Req & (0x01U)) | ((_m->DAS_CcFuncError_Stat & (0x01U)) << 1U) | ((_m->DAS_AebRdaStand_Req & (0x01U)) << 2U) | ((_m->DAS_AebFuncError_Stat & (0x01U)) << 3U) | ((_m->DAS_04_RC & (0x0FU)) << 4U) ); + _d[3] |= (uint8_t) ( (_m->DAS_04_CS & (0xFFU)) ); + + *_len = (uint8_t) DAS_04_DLC; + *_ide = (uint8_t) DAS_04_IDE; + return DAS_04_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_VCU_DriveInfo_candb(VCU_DriveInfo_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->VCU_SpecBut_Stat = (uint8_t) ( (_d[0] & (0x03U)) ); + _m->VCU_Fault_Stat = (uint8_t) ( ((_d[1] >> 3U) & (0x01U)) ); + _m->VCU_OverallActMotTrq_Val_ro = (uint16_t) ( ((_d[3] & (0xFFU)) << 8U) | (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->VCU_OverallActMotTrq_Val_phys = (sigfloat_t)(CANDB_VCU_OverallActMotTrq_Val_ro_fromS(_m->VCU_OverallActMotTrq_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->VCU_DriveInfo_RC = (uint8_t) ( ((_d[6] >> 4U) & (0x0FU)) ); + _m->VCU_DriveInfo_CS = (uint8_t) ( (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < VCU_DriveInfo_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_VCU_DriveInfo_candb(&_m->mon1, VCU_DriveInfo_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return VCU_DriveInfo_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_VCU_DriveInfo_candb(VCU_DriveInfo_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(VCU_DriveInfo_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->VCU_OverallActMotTrq_Val_ro = (uint16_t) CANDB_VCU_OverallActMotTrq_Val_ro_toS(_m->VCU_OverallActMotTrq_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->VCU_SpecBut_Stat & (0x03U)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->VCU_Fault_Stat & (0x01U)) << 3U) ); + cframe->Data[2] |= (uint8_t) ( (_m->VCU_OverallActMotTrq_Val_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->VCU_OverallActMotTrq_Val_ro >> 8U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->VCU_DriveInfo_RC & (0x0FU)) << 4U) ); + cframe->Data[7] |= (uint8_t) ( (_m->VCU_DriveInfo_CS & (0xFFU)) ); + + cframe->MsgId = (uint32_t) VCU_DriveInfo_CANID; + cframe->DLC = (uint8_t) VCU_DriveInfo_DLC; + cframe->IDE = (uint8_t) VCU_DriveInfo_IDE; + return VCU_DriveInfo_CANID; +} + +#else + +uint32_t Pack_VCU_DriveInfo_candb(VCU_DriveInfo_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(VCU_DriveInfo_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->VCU_OverallActMotTrq_Val_ro = (uint16_t) CANDB_VCU_OverallActMotTrq_Val_ro_toS(_m->VCU_OverallActMotTrq_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->VCU_SpecBut_Stat & (0x03U)) ); + _d[1] |= (uint8_t) ( ((_m->VCU_Fault_Stat & (0x01U)) << 3U) ); + _d[2] |= (uint8_t) ( (_m->VCU_OverallActMotTrq_Val_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->VCU_OverallActMotTrq_Val_ro >> 8U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->VCU_DriveInfo_RC & (0x0FU)) << 4U) ); + _d[7] |= (uint8_t) ( (_m->VCU_DriveInfo_CS & (0xFFU)) ); + + *_len = (uint8_t) VCU_DriveInfo_DLC; + *_ide = (uint8_t) VCU_DriveInfo_IDE; + return VCU_DriveInfo_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_DAS_02_candb(DAS_02_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->DAS_LkaAngleFlag_Req = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->DAS_AfsMode_Stat = (uint8_t) ( ((_d[0] >> 1U) & (0x01U)) ); + _m->DAS_AfsDecelFlag_Req = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + _m->DAS_AfsFuncError_Stat = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + _m->DAS_AfsExecute_Req = (uint8_t) ( ((_d[0] >> 4U) & (0x01U)) ); + _m->DAS_AfsSos_Req = (uint8_t) ( ((_d[0] >> 5U) & (0x01U)) ); + _m->DAS_AfsEpb_Req = (uint8_t) ( ((_d[0] >> 6U) & (0x01U)) ); + _m->DAS_RdaMode_Stat = (uint8_t) ( ((_d[0] >> 7U) & (0x01U)) ); + _m->DAS_RdaDecelFlag_Req = (uint8_t) ( (_d[1] & (0x01U)) ); + _m->DAS_RdaFuncError_Stat = (uint8_t) ( ((_d[1] >> 1U) & (0x01U)) ); + _m->DAS_LkaMode_Stat = (uint8_t) ( ((_d[1] >> 2U) & (0x03U)) ); + _m->DAS_LkaFuncError_Stat = (uint8_t) ( ((_d[1] >> 4U) & (0x01U)) ); + _m->DAS_LdpAngleFlag_Req = (uint8_t) ( ((_d[1] >> 5U) & (0x01U)) ); + _m->DAS_LdpMode_Stat = (uint8_t) ( ((_d[1] >> 6U) & (0x01U)) ); + _m->DAS_LdwFuncError_Stat = (uint8_t) ( ((_d[1] >> 7U) & (0x01U)) ); + _m->DAS_AlccAngleFlag_Req = (uint8_t) ( (_d[2] & (0x01U)) ); + _m->DAS_AlccMode_Stat = (uint8_t) ( ((_d[2] >> 1U) & (0x01U)) ); + _m->DAS_LccFuncError_Stat = (uint8_t) ( ((_d[2] >> 2U) & (0x01U)) ); + _m->DAS_ApaAngleFlag_Req = (uint8_t) ( ((_d[2] >> 3U) & (0x01U)) ); + _m->DAS_LkaSteeringMode_Stat = (uint8_t) ( ((_d[2] >> 4U) & (0x01U)) ); + _m->DAS_AfsNotifError_Req = (uint8_t) ( ((_d[2] >> 5U) & (0x01U)) ); + _m->DAS_RctcMode_Stat = (uint8_t) ( ((_d[2] >> 6U) & (0x01U)) ); + _m->DAS_RctcDecelFlag_Req = (uint8_t) ( ((_d[2] >> 7U) & (0x01U)) ); + _m->DAS_RctcFuncError_Stat = (uint8_t) ( (_d[3] & (0x01U)) ); + _m->DAS_RctcNotifError_Req = (uint8_t) ( ((_d[3] >> 1U) & (0x01U)) ); + _m->DAS_AccFuncError_Stat = (uint8_t) ( ((_d[3] >> 2U) & (0x01U)) ); + _m->DAS_APAMode_Stat = (uint8_t) ( ((_d[3] >> 3U) & (0x01U)) ); + _m->DAS_ApaFuncError_Stat = (uint8_t) ( ((_d[3] >> 4U) & (0x01U)) ); + _m->DAS_LkaAngle_Req_ro = (uint16_t) ( ((_d[5] & (0x3FU)) << 8U) | (_d[4] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->DAS_LkaAngle_Req_phys = (sigfloat_t)(CANDB_DAS_LkaAngle_Req_ro_fromS(_m->DAS_LkaAngle_Req_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->DAS_RsaAngleDirection_Req = (uint8_t) ( ((_d[5] >> 6U) & (0x03U)) ); + _m->DAS_02_RC = (uint8_t) ( ((_d[6] >> 4U) & (0x0FU)) ); + _m->DAS_02_CS = (uint8_t) ( (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < DAS_02_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_DAS_02_candb(&_m->mon1, DAS_02_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return DAS_02_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_DAS_02_candb(DAS_02_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(DAS_02_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->DAS_LkaAngle_Req_ro = (uint16_t) CANDB_DAS_LkaAngle_Req_ro_toS(_m->DAS_LkaAngle_Req_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->DAS_LkaAngleFlag_Req & (0x01U)) | ((_m->DAS_AfsMode_Stat & (0x01U)) << 1U) | ((_m->DAS_AfsDecelFlag_Req & (0x01U)) << 2U) | ((_m->DAS_AfsFuncError_Stat & (0x01U)) << 3U) | ((_m->DAS_AfsExecute_Req & (0x01U)) << 4U) | ((_m->DAS_AfsSos_Req & (0x01U)) << 5U) | ((_m->DAS_AfsEpb_Req & (0x01U)) << 6U) | ((_m->DAS_RdaMode_Stat & (0x01U)) << 7U) ); + cframe->Data[1] |= (uint8_t) ( (_m->DAS_RdaDecelFlag_Req & (0x01U)) | ((_m->DAS_RdaFuncError_Stat & (0x01U)) << 1U) | ((_m->DAS_LkaMode_Stat & (0x03U)) << 2U) | ((_m->DAS_LkaFuncError_Stat & (0x01U)) << 4U) | ((_m->DAS_LdpAngleFlag_Req & (0x01U)) << 5U) | ((_m->DAS_LdpMode_Stat & (0x01U)) << 6U) | ((_m->DAS_LdwFuncError_Stat & (0x01U)) << 7U) ); + cframe->Data[2] |= (uint8_t) ( (_m->DAS_AlccAngleFlag_Req & (0x01U)) | ((_m->DAS_AlccMode_Stat & (0x01U)) << 1U) | ((_m->DAS_LccFuncError_Stat & (0x01U)) << 2U) | ((_m->DAS_ApaAngleFlag_Req & (0x01U)) << 3U) | ((_m->DAS_LkaSteeringMode_Stat & (0x01U)) << 4U) | ((_m->DAS_AfsNotifError_Req & (0x01U)) << 5U) | ((_m->DAS_RctcMode_Stat & (0x01U)) << 6U) | ((_m->DAS_RctcDecelFlag_Req & (0x01U)) << 7U) ); + cframe->Data[3] |= (uint8_t) ( (_m->DAS_RctcFuncError_Stat & (0x01U)) | ((_m->DAS_RctcNotifError_Req & (0x01U)) << 1U) | ((_m->DAS_AccFuncError_Stat & (0x01U)) << 2U) | ((_m->DAS_APAMode_Stat & (0x01U)) << 3U) | ((_m->DAS_ApaFuncError_Stat & (0x01U)) << 4U) ); + cframe->Data[4] |= (uint8_t) ( (_m->DAS_LkaAngle_Req_ro & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->DAS_LkaAngle_Req_ro >> 8U) & (0x3FU)) | ((_m->DAS_RsaAngleDirection_Req & (0x03U)) << 6U) ); + cframe->Data[6] |= (uint8_t) ( ((_m->DAS_02_RC & (0x0FU)) << 4U) ); + cframe->Data[7] |= (uint8_t) ( (_m->DAS_02_CS & (0xFFU)) ); + + cframe->MsgId = (uint32_t) DAS_02_CANID; + cframe->DLC = (uint8_t) DAS_02_DLC; + cframe->IDE = (uint8_t) DAS_02_IDE; + return DAS_02_CANID; +} + +#else + +uint32_t Pack_DAS_02_candb(DAS_02_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(DAS_02_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->DAS_LkaAngle_Req_ro = (uint16_t) CANDB_DAS_LkaAngle_Req_ro_toS(_m->DAS_LkaAngle_Req_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->DAS_LkaAngleFlag_Req & (0x01U)) | ((_m->DAS_AfsMode_Stat & (0x01U)) << 1U) | ((_m->DAS_AfsDecelFlag_Req & (0x01U)) << 2U) | ((_m->DAS_AfsFuncError_Stat & (0x01U)) << 3U) | ((_m->DAS_AfsExecute_Req & (0x01U)) << 4U) | ((_m->DAS_AfsSos_Req & (0x01U)) << 5U) | ((_m->DAS_AfsEpb_Req & (0x01U)) << 6U) | ((_m->DAS_RdaMode_Stat & (0x01U)) << 7U) ); + _d[1] |= (uint8_t) ( (_m->DAS_RdaDecelFlag_Req & (0x01U)) | ((_m->DAS_RdaFuncError_Stat & (0x01U)) << 1U) | ((_m->DAS_LkaMode_Stat & (0x03U)) << 2U) | ((_m->DAS_LkaFuncError_Stat & (0x01U)) << 4U) | ((_m->DAS_LdpAngleFlag_Req & (0x01U)) << 5U) | ((_m->DAS_LdpMode_Stat & (0x01U)) << 6U) | ((_m->DAS_LdwFuncError_Stat & (0x01U)) << 7U) ); + _d[2] |= (uint8_t) ( (_m->DAS_AlccAngleFlag_Req & (0x01U)) | ((_m->DAS_AlccMode_Stat & (0x01U)) << 1U) | ((_m->DAS_LccFuncError_Stat & (0x01U)) << 2U) | ((_m->DAS_ApaAngleFlag_Req & (0x01U)) << 3U) | ((_m->DAS_LkaSteeringMode_Stat & (0x01U)) << 4U) | ((_m->DAS_AfsNotifError_Req & (0x01U)) << 5U) | ((_m->DAS_RctcMode_Stat & (0x01U)) << 6U) | ((_m->DAS_RctcDecelFlag_Req & (0x01U)) << 7U) ); + _d[3] |= (uint8_t) ( (_m->DAS_RctcFuncError_Stat & (0x01U)) | ((_m->DAS_RctcNotifError_Req & (0x01U)) << 1U) | ((_m->DAS_AccFuncError_Stat & (0x01U)) << 2U) | ((_m->DAS_APAMode_Stat & (0x01U)) << 3U) | ((_m->DAS_ApaFuncError_Stat & (0x01U)) << 4U) ); + _d[4] |= (uint8_t) ( (_m->DAS_LkaAngle_Req_ro & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->DAS_LkaAngle_Req_ro >> 8U) & (0x3FU)) | ((_m->DAS_RsaAngleDirection_Req & (0x03U)) << 6U) ); + _d[6] |= (uint8_t) ( ((_m->DAS_02_RC & (0x0FU)) << 4U) ); + _d[7] |= (uint8_t) ( (_m->DAS_02_CS & (0xFFU)) ); + + *_len = (uint8_t) DAS_02_DLC; + *_ide = (uint8_t) DAS_02_IDE; + return DAS_02_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_DAS_07_candb(DAS_07_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->DAS_LkaWarnSound_Req = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->DAS_LkaShootdownSound_Req = (uint8_t) ( ((_d[0] >> 1U) & (0x01U)) ); + _m->DAS_LkaWarnNotif_Req = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + _m->DAS_LkaNotifError_Req = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + _m->DAS_RdaWarn_Req = (uint8_t) ( ((_d[0] >> 4U) & (0x01U)) ); + _m->DAS_RctcWarn_Req = (uint8_t) ( ((_d[0] >> 5U) & (0x01U)) ); + _m->DAS_RdaNotifError_Req = (uint8_t) ( ((_d[0] >> 6U) & (0x01U)) ); + _m->DAS_LdwMode_Stat = (uint8_t) ( ((_d[1] & (0x03U)) << 1U) | ((_d[0] >> 7U) & (0x01U)) ); + _m->DAS_LdpLeftLaneWarn_Req = (uint8_t) ( ((_d[1] >> 2U) & (0x01U)) ); + _m->DAS_LdpRightLaneWarn_Req = (uint8_t) ( ((_d[1] >> 3U) & (0x01U)) ); + _m->DAS_ALccNotifError_Req = (uint8_t) ( ((_d[1] >> 4U) & (0x01U)) ); + _m->DAS_LdwLeftLaneWarn_Req = (uint8_t) ( ((_d[1] >> 5U) & (0x01U)) ); + _m->DAS_LdwRightLaneWarn_Req = (uint8_t) ( ((_d[1] >> 6U) & (0x01U)) ); + _m->DAS_LdwSound_Req = (uint8_t) ( ((_d[1] >> 7U) & (0x01U)) ); + _m->DAS_LdwNotifError_Req = (uint8_t) ( (_d[2] & (0x01U)) ); + _m->DAS_LccMode_Stat = (uint8_t) ( ((_d[2] >> 1U) & (0x03U)) ); + _m->DAS_DowMode_Stat = (uint8_t) ( ((_d[2] >> 3U) & (0x01U)) ); + _m->DAS_LccLeftLed_Req = (uint8_t) ( ((_d[2] >> 4U) & (0x01U)) ); + _m->DAS_LccRightLed_Req = (uint8_t) ( ((_d[2] >> 5U) & (0x01U)) ); + _m->DAS_LccLeftWarn_Req = (uint8_t) ( (_d[3] & (0x01U)) ); + _m->DAS_LccRightWarn_Req = (uint8_t) ( ((_d[3] >> 1U) & (0x01U)) ); + _m->DAS_LccSound_Req = (uint8_t) ( ((_d[3] >> 2U) & (0x01U)) ); + _m->DAS_LccNotifError_Req = (uint8_t) ( ((_d[3] >> 3U) & (0x01U)) ); + _m->DAS_DowNotifError_Req = (uint8_t) ( ((_d[3] >> 4U) & (0x01U)) ); + _m->DAS_LdpNotifError_Req = (uint8_t) ( ((_d[3] >> 5U) & (0x01U)) ); + _m->DAS_07_RC = (uint8_t) ( ((_d[4] >> 4U) & (0x0FU)) ); + _m->DAS_07_CS = (uint8_t) ( (_d[5] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < DAS_07_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_DAS_07_candb(&_m->mon1, DAS_07_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return DAS_07_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_DAS_07_candb(DAS_07_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(DAS_07_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->DAS_LkaWarnSound_Req & (0x01U)) | ((_m->DAS_LkaShootdownSound_Req & (0x01U)) << 1U) | ((_m->DAS_LkaWarnNotif_Req & (0x01U)) << 2U) | ((_m->DAS_LkaNotifError_Req & (0x01U)) << 3U) | ((_m->DAS_RdaWarn_Req & (0x01U)) << 4U) | ((_m->DAS_RctcWarn_Req & (0x01U)) << 5U) | ((_m->DAS_RdaNotifError_Req & (0x01U)) << 6U) | ((_m->DAS_LdwMode_Stat & (0x01U)) << 7U) ); + cframe->Data[1] |= (uint8_t) ( ((_m->DAS_LdwMode_Stat >> 1U) & (0x03U)) | ((_m->DAS_LdpLeftLaneWarn_Req & (0x01U)) << 2U) | ((_m->DAS_LdpRightLaneWarn_Req & (0x01U)) << 3U) | ((_m->DAS_ALccNotifError_Req & (0x01U)) << 4U) | ((_m->DAS_LdwLeftLaneWarn_Req & (0x01U)) << 5U) | ((_m->DAS_LdwRightLaneWarn_Req & (0x01U)) << 6U) | ((_m->DAS_LdwSound_Req & (0x01U)) << 7U) ); + cframe->Data[2] |= (uint8_t) ( (_m->DAS_LdwNotifError_Req & (0x01U)) | ((_m->DAS_LccMode_Stat & (0x03U)) << 1U) | ((_m->DAS_DowMode_Stat & (0x01U)) << 3U) | ((_m->DAS_LccLeftLed_Req & (0x01U)) << 4U) | ((_m->DAS_LccRightLed_Req & (0x01U)) << 5U) ); + cframe->Data[3] |= (uint8_t) ( (_m->DAS_LccLeftWarn_Req & (0x01U)) | ((_m->DAS_LccRightWarn_Req & (0x01U)) << 1U) | ((_m->DAS_LccSound_Req & (0x01U)) << 2U) | ((_m->DAS_LccNotifError_Req & (0x01U)) << 3U) | ((_m->DAS_DowNotifError_Req & (0x01U)) << 4U) | ((_m->DAS_LdpNotifError_Req & (0x01U)) << 5U) ); + cframe->Data[4] |= (uint8_t) ( ((_m->DAS_07_RC & (0x0FU)) << 4U) ); + cframe->Data[5] |= (uint8_t) ( (_m->DAS_07_CS & (0xFFU)) ); + + cframe->MsgId = (uint32_t) DAS_07_CANID; + cframe->DLC = (uint8_t) DAS_07_DLC; + cframe->IDE = (uint8_t) DAS_07_IDE; + return DAS_07_CANID; +} + +#else + +uint32_t Pack_DAS_07_candb(DAS_07_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(DAS_07_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->DAS_LkaWarnSound_Req & (0x01U)) | ((_m->DAS_LkaShootdownSound_Req & (0x01U)) << 1U) | ((_m->DAS_LkaWarnNotif_Req & (0x01U)) << 2U) | ((_m->DAS_LkaNotifError_Req & (0x01U)) << 3U) | ((_m->DAS_RdaWarn_Req & (0x01U)) << 4U) | ((_m->DAS_RctcWarn_Req & (0x01U)) << 5U) | ((_m->DAS_RdaNotifError_Req & (0x01U)) << 6U) | ((_m->DAS_LdwMode_Stat & (0x01U)) << 7U) ); + _d[1] |= (uint8_t) ( ((_m->DAS_LdwMode_Stat >> 1U) & (0x03U)) | ((_m->DAS_LdpLeftLaneWarn_Req & (0x01U)) << 2U) | ((_m->DAS_LdpRightLaneWarn_Req & (0x01U)) << 3U) | ((_m->DAS_ALccNotifError_Req & (0x01U)) << 4U) | ((_m->DAS_LdwLeftLaneWarn_Req & (0x01U)) << 5U) | ((_m->DAS_LdwRightLaneWarn_Req & (0x01U)) << 6U) | ((_m->DAS_LdwSound_Req & (0x01U)) << 7U) ); + _d[2] |= (uint8_t) ( (_m->DAS_LdwNotifError_Req & (0x01U)) | ((_m->DAS_LccMode_Stat & (0x03U)) << 1U) | ((_m->DAS_DowMode_Stat & (0x01U)) << 3U) | ((_m->DAS_LccLeftLed_Req & (0x01U)) << 4U) | ((_m->DAS_LccRightLed_Req & (0x01U)) << 5U) ); + _d[3] |= (uint8_t) ( (_m->DAS_LccLeftWarn_Req & (0x01U)) | ((_m->DAS_LccRightWarn_Req & (0x01U)) << 1U) | ((_m->DAS_LccSound_Req & (0x01U)) << 2U) | ((_m->DAS_LccNotifError_Req & (0x01U)) << 3U) | ((_m->DAS_DowNotifError_Req & (0x01U)) << 4U) | ((_m->DAS_LdpNotifError_Req & (0x01U)) << 5U) ); + _d[4] |= (uint8_t) ( ((_m->DAS_07_RC & (0x0FU)) << 4U) ); + _d[5] |= (uint8_t) ( (_m->DAS_07_CS & (0xFFU)) ); + + *_len = (uint8_t) DAS_07_DLC; + *_ide = (uint8_t) DAS_07_IDE; + return DAS_07_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_ACU_01_candb(ACU_01_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->ACU_CrashEventDetect_Stat = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->ACU_SysDeactEn_Stat = (uint8_t) ( ((_d[0] >> 1U) & (0x01U)) ); + _m->DrivSeatBeltWarning = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + _m->PassSeatBeltWarning = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + _m->RILRequestStatus = (uint8_t) ( ((_d[0] >> 4U) & (0x03U)) ); + _m->ACU_AirbagFrontPsngr_Stat = (uint8_t) ( ((_d[0] >> 6U) & (0x03U)) ); + _m->RLSeatBeltWarning = (uint8_t) ( (_d[1] & (0x01U)) ); + _m->RRSeatBeltWarning = (uint8_t) ( ((_d[1] >> 1U) & (0x01U)) ); + _m->FrontBuckleDriver_L = (uint8_t) ( ((_d[1] >> 2U) & (0x03U)) ); + _m->ACU_01_RC = (uint8_t) ( ((_d[1] >> 4U) & (0x0FU)) ); + _m->ACU_01_CS = (uint8_t) ( (_d[2] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < ACU_01_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_ACU_01_candb(&_m->mon1, ACU_01_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return ACU_01_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_ACU_01_candb(ACU_01_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(ACU_01_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->ACU_CrashEventDetect_Stat & (0x01U)) | ((_m->ACU_SysDeactEn_Stat & (0x01U)) << 1U) | ((_m->DrivSeatBeltWarning & (0x01U)) << 2U) | ((_m->PassSeatBeltWarning & (0x01U)) << 3U) | ((_m->RILRequestStatus & (0x03U)) << 4U) | ((_m->ACU_AirbagFrontPsngr_Stat & (0x03U)) << 6U) ); + cframe->Data[1] |= (uint8_t) ( (_m->RLSeatBeltWarning & (0x01U)) | ((_m->RRSeatBeltWarning & (0x01U)) << 1U) | ((_m->FrontBuckleDriver_L & (0x03U)) << 2U) | ((_m->ACU_01_RC & (0x0FU)) << 4U) ); + cframe->Data[2] |= (uint8_t) ( (_m->ACU_01_CS & (0xFFU)) ); + + cframe->MsgId = (uint32_t) ACU_01_CANID; + cframe->DLC = (uint8_t) ACU_01_DLC; + cframe->IDE = (uint8_t) ACU_01_IDE; + return ACU_01_CANID; +} + +#else + +uint32_t Pack_ACU_01_candb(ACU_01_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(ACU_01_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->ACU_CrashEventDetect_Stat & (0x01U)) | ((_m->ACU_SysDeactEn_Stat & (0x01U)) << 1U) | ((_m->DrivSeatBeltWarning & (0x01U)) << 2U) | ((_m->PassSeatBeltWarning & (0x01U)) << 3U) | ((_m->RILRequestStatus & (0x03U)) << 4U) | ((_m->ACU_AirbagFrontPsngr_Stat & (0x03U)) << 6U) ); + _d[1] |= (uint8_t) ( (_m->RLSeatBeltWarning & (0x01U)) | ((_m->RRSeatBeltWarning & (0x01U)) << 1U) | ((_m->FrontBuckleDriver_L & (0x03U)) << 2U) | ((_m->ACU_01_RC & (0x0FU)) << 4U) ); + _d[2] |= (uint8_t) ( (_m->ACU_01_CS & (0xFFU)) ); + + *_len = (uint8_t) ACU_01_DLC; + *_ide = (uint8_t) ACU_01_IDE; + return ACU_01_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_EPB_Status_candb(EPB_Status_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->EPB_AppliedForce_Stat = (uint8_t) ( (_d[0] & (0x07U)) ); + _m->EPB_BrakeLight_Req = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + _m->EPB_CurrParkBrake_Stat = (uint8_t) ( ((_d[0] >> 4U) & (0x07U)) ); + _m->EPB_AudibleChime_Req = (uint8_t) ( ((_d[0] >> 7U) & (0x01U)) ); + _m->EPB_TargetDecel_Val_ro = (uint8_t) ( (_d[1] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->EPB_TargetDecel_Val_phys = (sigfloat_t)(CANDB_EPB_TargetDecel_Val_ro_fromS(_m->EPB_TargetDecel_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->EPB_CurrEPBSw_Stat = (uint8_t) ( (_d[2] & (0x07U)) ); + _m->EPB_DynamicEmergencyApply_Stat = (uint8_t) ( ((_d[2] >> 4U) & (0x01U)) ); + _m->EPB_Indicator_Req = (uint8_t) ( ((_d[2] >> 5U) & (0x03U)) ); + _m->EPB_Failure_Stat = (uint8_t) ( ((_d[2] >> 7U) & (0x01U)) ); + _m->EPB_Status_RC = (uint8_t) ( ((_d[3] >> 4U) & (0x0FU)) ); + _m->EPB_Status_CS = (uint8_t) ( (_d[4] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < EPB_Status_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_EPB_Status_candb(&_m->mon1, EPB_Status_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return EPB_Status_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_EPB_Status_candb(EPB_Status_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(EPB_Status_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->EPB_TargetDecel_Val_ro = (uint8_t) CANDB_EPB_TargetDecel_Val_ro_toS(_m->EPB_TargetDecel_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->EPB_AppliedForce_Stat & (0x07U)) | ((_m->EPB_BrakeLight_Req & (0x01U)) << 3U) | ((_m->EPB_CurrParkBrake_Stat & (0x07U)) << 4U) | ((_m->EPB_AudibleChime_Req & (0x01U)) << 7U) ); + cframe->Data[1] |= (uint8_t) ( (_m->EPB_TargetDecel_Val_ro & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->EPB_CurrEPBSw_Stat & (0x07U)) | ((_m->EPB_DynamicEmergencyApply_Stat & (0x01U)) << 4U) | ((_m->EPB_Indicator_Req & (0x03U)) << 5U) | ((_m->EPB_Failure_Stat & (0x01U)) << 7U) ); + cframe->Data[3] |= (uint8_t) ( ((_m->EPB_Status_RC & (0x0FU)) << 4U) ); + cframe->Data[4] |= (uint8_t) ( (_m->EPB_Status_CS & (0xFFU)) ); + + cframe->MsgId = (uint32_t) EPB_Status_CANID; + cframe->DLC = (uint8_t) EPB_Status_DLC; + cframe->IDE = (uint8_t) EPB_Status_IDE; + return EPB_Status_CANID; +} + +#else + +uint32_t Pack_EPB_Status_candb(EPB_Status_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(EPB_Status_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->EPB_TargetDecel_Val_ro = (uint8_t) CANDB_EPB_TargetDecel_Val_ro_toS(_m->EPB_TargetDecel_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->EPB_AppliedForce_Stat & (0x07U)) | ((_m->EPB_BrakeLight_Req & (0x01U)) << 3U) | ((_m->EPB_CurrParkBrake_Stat & (0x07U)) << 4U) | ((_m->EPB_AudibleChime_Req & (0x01U)) << 7U) ); + _d[1] |= (uint8_t) ( (_m->EPB_TargetDecel_Val_ro & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->EPB_CurrEPBSw_Stat & (0x07U)) | ((_m->EPB_DynamicEmergencyApply_Stat & (0x01U)) << 4U) | ((_m->EPB_Indicator_Req & (0x03U)) << 5U) | ((_m->EPB_Failure_Stat & (0x01U)) << 7U) ); + _d[3] |= (uint8_t) ( ((_m->EPB_Status_RC & (0x0FU)) << 4U) ); + _d[4] |= (uint8_t) ( (_m->EPB_Status_CS & (0xFFU)) ); + + *_len = (uint8_t) EPB_Status_DLC; + *_ide = (uint8_t) EPB_Status_IDE; + return EPB_Status_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_ExteriorLightState_candb(BCM_ExteriorLightState_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->BCM_PositionLightRearState = (uint8_t) ( ((_d[0] >> 1U) & (0x01U)) ); + _m->BCM_TurnIndL_Req = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + _m->BCM_TurnIndR_Req = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + _m->BCM_PosLghtsState = (uint8_t) ( ((_d[0] >> 4U) & (0x01U)) ); + _m->BCM_RearFogLightState = (uint8_t) ( ((_d[0] >> 5U) & (0x01U)) ); + _m->BCM_BrakeLightState = (uint8_t) ( ((_d[0] >> 6U) & (0x01U)) ); + _m->BCM_ReverseLightState = (uint8_t) ( ((_d[0] >> 7U) & (0x01U)) ); + _m->BCM_HighBeamState = (uint8_t) ( (_d[1] & (0x07U)) ); + _m->BCM_LightSwitchPos = (uint8_t) ( ((_d[1] >> 3U) & (0x03U)) ); + _m->BCM_LowBeamState = (uint8_t) ( ((_d[1] >> 5U) & (0x07U)) ); + _m->BCM_AllWthrLght_State = (uint8_t) ( ((_d[2] >> 4U) & (0x01U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < BCM_ExteriorLightState_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_BCM_ExteriorLightState_candb(&_m->mon1, BCM_ExteriorLightState_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return BCM_ExteriorLightState_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_BCM_ExteriorLightState_candb(BCM_ExteriorLightState_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_ExteriorLightState_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->BCM_PositionLightRearState & (0x01U)) << 1U) | ((_m->BCM_TurnIndL_Req & (0x01U)) << 2U) | ((_m->BCM_TurnIndR_Req & (0x01U)) << 3U) | ((_m->BCM_PosLghtsState & (0x01U)) << 4U) | ((_m->BCM_RearFogLightState & (0x01U)) << 5U) | ((_m->BCM_BrakeLightState & (0x01U)) << 6U) | ((_m->BCM_ReverseLightState & (0x01U)) << 7U) ); + cframe->Data[1] |= (uint8_t) ( (_m->BCM_HighBeamState & (0x07U)) | ((_m->BCM_LightSwitchPos & (0x03U)) << 3U) | ((_m->BCM_LowBeamState & (0x07U)) << 5U) ); + cframe->Data[2] |= (uint8_t) ( ((_m->BCM_AllWthrLght_State & (0x01U)) << 4U) ); + + cframe->MsgId = (uint32_t) BCM_ExteriorLightState_CANID; + cframe->DLC = (uint8_t) BCM_ExteriorLightState_DLC; + cframe->IDE = (uint8_t) BCM_ExteriorLightState_IDE; + return BCM_ExteriorLightState_CANID; +} + +#else + +uint32_t Pack_BCM_ExteriorLightState_candb(BCM_ExteriorLightState_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_ExteriorLightState_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->BCM_PositionLightRearState & (0x01U)) << 1U) | ((_m->BCM_TurnIndL_Req & (0x01U)) << 2U) | ((_m->BCM_TurnIndR_Req & (0x01U)) << 3U) | ((_m->BCM_PosLghtsState & (0x01U)) << 4U) | ((_m->BCM_RearFogLightState & (0x01U)) << 5U) | ((_m->BCM_BrakeLightState & (0x01U)) << 6U) | ((_m->BCM_ReverseLightState & (0x01U)) << 7U) ); + _d[1] |= (uint8_t) ( (_m->BCM_HighBeamState & (0x07U)) | ((_m->BCM_LightSwitchPos & (0x03U)) << 3U) | ((_m->BCM_LowBeamState & (0x07U)) << 5U) ); + _d[2] |= (uint8_t) ( ((_m->BCM_AllWthrLght_State & (0x01U)) << 4U) ); + + *_len = (uint8_t) BCM_ExteriorLightState_DLC; + *_ide = (uint8_t) BCM_ExteriorLightState_IDE; + return BCM_ExteriorLightState_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SWM_ContrlsState_candb(SWM_ContrlsState_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->SWM_MODE_Req = (uint8_t) ( (_d[0] & (0x03U)) ); + _m->SWM_CNCL_Req = (uint8_t) ( ((_d[0] >> 2U) & (0x03U)) ); + _m->SWM_ACCSpeedDecrease_Req = (uint8_t) ( ((_d[0] >> 4U) & (0x03U)) ); + _m->SWM_ACCSpeedIncrease_Req = (uint8_t) ( ((_d[0] >> 6U) & (0x03U)) ); + _m->SWM_UserFunc_Req = (uint8_t) ( (_d[1] & (0x03U)) ); + _m->SWM_DIS_Req = (uint8_t) ( ((_d[1] >> 2U) & (0x03U)) ); + _m->SWM_RES_Req = (uint8_t) ( ((_d[1] >> 4U) & (0x03U)) ); + _m->SWM_SETSpeed_Req = (uint8_t) ( ((_d[1] >> 6U) & (0x03U)) ); + _m->SWM_TELBtn_Req = (uint8_t) ( (_d[2] & (0x03U)) ); + _m->SWM_Home_Req = (uint8_t) ( ((_d[2] >> 2U) & (0x03U)) ); + _m->SWM_Back_Req = (uint8_t) ( ((_d[2] >> 4U) & (0x03U)) ); + _m->SWM_ICNextBtn_Req = (uint8_t) ( ((_d[2] >> 6U) & (0x03U)) ); + _m->SWM_ICPrevBtn_Req = (uint8_t) ( (_d[3] & (0x03U)) ); + _m->SWM_ICUpBtn_Req = (uint8_t) ( ((_d[3] >> 2U) & (0x03U)) ); + _m->SWM_ICDownBtn_Req = (uint8_t) ( ((_d[3] >> 4U) & (0x03U)) ); + _m->SWM_ICConfBtn_Req = (uint8_t) ( ((_d[3] >> 6U) & (0x03U)) ); + _m->SWM_MMCNextBtn_Req = (uint8_t) ( (_d[4] & (0x03U)) ); + _m->SWM_MMCPrevBtn_Req = (uint8_t) ( ((_d[4] >> 2U) & (0x03U)) ); + _m->SWM_VoiceCntrl_Req = (uint8_t) ( ((_d[4] >> 4U) & (0x03U)) ); + _m->SWM_VolumeUpBtn_Req = (uint8_t) ( ((_d[4] >> 6U) & (0x03U)) ); + _m->SWM_VolumeDownBtn_Req = (uint8_t) ( (_d[5] & (0x03U)) ); + _m->SWM_VolumeMute_Req = (uint8_t) ( ((_d[5] >> 2U) & (0x03U)) ); + _m->SWM_UpshiftPaddle_Req = (uint8_t) ( ((_d[5] >> 4U) & (0x03U)) ); + _m->SWM_DownshiftPaddle_Req = (uint8_t) ( ((_d[5] >> 6U) & (0x03U)) ); + _m->SWM_ContrlsState_RC = (uint8_t) ( (_d[6] & (0x0FU)) ); + _m->SWM_Heating_Stat = (uint8_t) ( ((_d[6] >> 4U) & (0x03U)) ); + _m->SWM_PosHand_Stat = (uint8_t) ( ((_d[6] >> 6U) & (0x03U)) ); + _m->SWM_ContrlsState_CS = (uint8_t) ( (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < SWM_ContrlsState_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_SWM_ContrlsState_candb(&_m->mon1, SWM_ContrlsState_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return SWM_ContrlsState_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_SWM_ContrlsState_candb(SWM_ContrlsState_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SWM_ContrlsState_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->SWM_MODE_Req & (0x03U)) | ((_m->SWM_CNCL_Req & (0x03U)) << 2U) | ((_m->SWM_ACCSpeedDecrease_Req & (0x03U)) << 4U) | ((_m->SWM_ACCSpeedIncrease_Req & (0x03U)) << 6U) ); + cframe->Data[1] |= (uint8_t) ( (_m->SWM_UserFunc_Req & (0x03U)) | ((_m->SWM_DIS_Req & (0x03U)) << 2U) | ((_m->SWM_RES_Req & (0x03U)) << 4U) | ((_m->SWM_SETSpeed_Req & (0x03U)) << 6U) ); + cframe->Data[2] |= (uint8_t) ( (_m->SWM_TELBtn_Req & (0x03U)) | ((_m->SWM_Home_Req & (0x03U)) << 2U) | ((_m->SWM_Back_Req & (0x03U)) << 4U) | ((_m->SWM_ICNextBtn_Req & (0x03U)) << 6U) ); + cframe->Data[3] |= (uint8_t) ( (_m->SWM_ICPrevBtn_Req & (0x03U)) | ((_m->SWM_ICUpBtn_Req & (0x03U)) << 2U) | ((_m->SWM_ICDownBtn_Req & (0x03U)) << 4U) | ((_m->SWM_ICConfBtn_Req & (0x03U)) << 6U) ); + cframe->Data[4] |= (uint8_t) ( (_m->SWM_MMCNextBtn_Req & (0x03U)) | ((_m->SWM_MMCPrevBtn_Req & (0x03U)) << 2U) | ((_m->SWM_VoiceCntrl_Req & (0x03U)) << 4U) | ((_m->SWM_VolumeUpBtn_Req & (0x03U)) << 6U) ); + cframe->Data[5] |= (uint8_t) ( (_m->SWM_VolumeDownBtn_Req & (0x03U)) | ((_m->SWM_VolumeMute_Req & (0x03U)) << 2U) | ((_m->SWM_UpshiftPaddle_Req & (0x03U)) << 4U) | ((_m->SWM_DownshiftPaddle_Req & (0x03U)) << 6U) ); + cframe->Data[6] |= (uint8_t) ( (_m->SWM_ContrlsState_RC & (0x0FU)) | ((_m->SWM_Heating_Stat & (0x03U)) << 4U) | ((_m->SWM_PosHand_Stat & (0x03U)) << 6U) ); + cframe->Data[7] |= (uint8_t) ( (_m->SWM_ContrlsState_CS & (0xFFU)) ); + + cframe->MsgId = (uint32_t) SWM_ContrlsState_CANID; + cframe->DLC = (uint8_t) SWM_ContrlsState_DLC; + cframe->IDE = (uint8_t) SWM_ContrlsState_IDE; + return SWM_ContrlsState_CANID; +} + +#else + +uint32_t Pack_SWM_ContrlsState_candb(SWM_ContrlsState_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SWM_ContrlsState_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->SWM_MODE_Req & (0x03U)) | ((_m->SWM_CNCL_Req & (0x03U)) << 2U) | ((_m->SWM_ACCSpeedDecrease_Req & (0x03U)) << 4U) | ((_m->SWM_ACCSpeedIncrease_Req & (0x03U)) << 6U) ); + _d[1] |= (uint8_t) ( (_m->SWM_UserFunc_Req & (0x03U)) | ((_m->SWM_DIS_Req & (0x03U)) << 2U) | ((_m->SWM_RES_Req & (0x03U)) << 4U) | ((_m->SWM_SETSpeed_Req & (0x03U)) << 6U) ); + _d[2] |= (uint8_t) ( (_m->SWM_TELBtn_Req & (0x03U)) | ((_m->SWM_Home_Req & (0x03U)) << 2U) | ((_m->SWM_Back_Req & (0x03U)) << 4U) | ((_m->SWM_ICNextBtn_Req & (0x03U)) << 6U) ); + _d[3] |= (uint8_t) ( (_m->SWM_ICPrevBtn_Req & (0x03U)) | ((_m->SWM_ICUpBtn_Req & (0x03U)) << 2U) | ((_m->SWM_ICDownBtn_Req & (0x03U)) << 4U) | ((_m->SWM_ICConfBtn_Req & (0x03U)) << 6U) ); + _d[4] |= (uint8_t) ( (_m->SWM_MMCNextBtn_Req & (0x03U)) | ((_m->SWM_MMCPrevBtn_Req & (0x03U)) << 2U) | ((_m->SWM_VoiceCntrl_Req & (0x03U)) << 4U) | ((_m->SWM_VolumeUpBtn_Req & (0x03U)) << 6U) ); + _d[5] |= (uint8_t) ( (_m->SWM_VolumeDownBtn_Req & (0x03U)) | ((_m->SWM_VolumeMute_Req & (0x03U)) << 2U) | ((_m->SWM_UpshiftPaddle_Req & (0x03U)) << 4U) | ((_m->SWM_DownshiftPaddle_Req & (0x03U)) << 6U) ); + _d[6] |= (uint8_t) ( (_m->SWM_ContrlsState_RC & (0x0FU)) | ((_m->SWM_Heating_Stat & (0x03U)) << 4U) | ((_m->SWM_PosHand_Stat & (0x03U)) << 6U) ); + _d[7] |= (uint8_t) ( (_m->SWM_ContrlsState_CS & (0xFFU)) ); + + *_len = (uint8_t) SWM_ContrlsState_DLC; + *_ide = (uint8_t) SWM_ContrlsState_IDE; + return SWM_ContrlsState_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_StyleCmd1_candb(BCM_StyleCmd1_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->BCM_ControlledZone_Stat = (uint8_t) ( (_d[0] & (0x3FU)) ); + _m->BCM_ChannelNumber_Req = (uint8_t) ( ((_d[1] & (0x03U)) << 2U) | ((_d[0] >> 6U) & (0x03U)) ); + _m->BCM_ModuleConfiguration_Stat = (uint8_t) ( ((_d[1] >> 2U) & (0x07U)) ); + _m->BCM_ScenarioBrightness_Val = (uint8_t) ( ((_d[2] & (0x0FU)) << 3U) | ((_d[1] >> 5U) & (0x07U)) ); + _m->BCM_ConfigurationMsgAmount_Val = (uint8_t) ( ((_d[3] & (0x03U)) << 4U) | ((_d[2] >> 4U) & (0x0FU)) ); + _m->BCM_Reserved1 = (uint8_t) ( ((_d[4] & (0x03U)) << 6U) | ((_d[3] >> 2U) & (0x3FU)) ); + _m->BCM_Reserved2 = (uint8_t) ( ((_d[5] & (0x03U)) << 6U) | ((_d[4] >> 2U) & (0x3FU)) ); + _m->BCM_Reserved3 = (uint8_t) ( ((_d[6] & (0x03U)) << 6U) | ((_d[5] >> 2U) & (0x3FU)) ); + _m->BCM_Reserved4 = (uint8_t) ( ((_d[7] & (0x03U)) << 6U) | ((_d[6] >> 2U) & (0x3FU)) ); + _m->BCM_Reserved5 = (uint8_t) ( ((_d[7] >> 2U) & (0x3FU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < BCM_StyleCmd1_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_BCM_StyleCmd1_candb(&_m->mon1, BCM_StyleCmd1_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return BCM_StyleCmd1_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_BCM_StyleCmd1_candb(BCM_StyleCmd1_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_StyleCmd1_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->BCM_ControlledZone_Stat & (0x3FU)) | ((_m->BCM_ChannelNumber_Req & (0x03U)) << 6U) ); + cframe->Data[1] |= (uint8_t) ( ((_m->BCM_ChannelNumber_Req >> 2U) & (0x03U)) | ((_m->BCM_ModuleConfiguration_Stat & (0x07U)) << 2U) | ((_m->BCM_ScenarioBrightness_Val & (0x07U)) << 5U) ); + cframe->Data[2] |= (uint8_t) ( ((_m->BCM_ScenarioBrightness_Val >> 3U) & (0x0FU)) | ((_m->BCM_ConfigurationMsgAmount_Val & (0x0FU)) << 4U) ); + cframe->Data[3] |= (uint8_t) ( ((_m->BCM_ConfigurationMsgAmount_Val >> 4U) & (0x03U)) | ((_m->BCM_Reserved1 & (0x3FU)) << 2U) ); + cframe->Data[4] |= (uint8_t) ( ((_m->BCM_Reserved1 >> 6U) & (0x03U)) | ((_m->BCM_Reserved2 & (0x3FU)) << 2U) ); + cframe->Data[5] |= (uint8_t) ( ((_m->BCM_Reserved2 >> 6U) & (0x03U)) | ((_m->BCM_Reserved3 & (0x3FU)) << 2U) ); + cframe->Data[6] |= (uint8_t) ( ((_m->BCM_Reserved3 >> 6U) & (0x03U)) | ((_m->BCM_Reserved4 & (0x3FU)) << 2U) ); + cframe->Data[7] |= (uint8_t) ( ((_m->BCM_Reserved4 >> 6U) & (0x03U)) | ((_m->BCM_Reserved5 & (0x3FU)) << 2U) ); + + cframe->MsgId = (uint32_t) BCM_StyleCmd1_CANID; + cframe->DLC = (uint8_t) BCM_StyleCmd1_DLC; + cframe->IDE = (uint8_t) BCM_StyleCmd1_IDE; + return BCM_StyleCmd1_CANID; +} + +#else + +uint32_t Pack_BCM_StyleCmd1_candb(BCM_StyleCmd1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_StyleCmd1_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->BCM_ControlledZone_Stat & (0x3FU)) | ((_m->BCM_ChannelNumber_Req & (0x03U)) << 6U) ); + _d[1] |= (uint8_t) ( ((_m->BCM_ChannelNumber_Req >> 2U) & (0x03U)) | ((_m->BCM_ModuleConfiguration_Stat & (0x07U)) << 2U) | ((_m->BCM_ScenarioBrightness_Val & (0x07U)) << 5U) ); + _d[2] |= (uint8_t) ( ((_m->BCM_ScenarioBrightness_Val >> 3U) & (0x0FU)) | ((_m->BCM_ConfigurationMsgAmount_Val & (0x0FU)) << 4U) ); + _d[3] |= (uint8_t) ( ((_m->BCM_ConfigurationMsgAmount_Val >> 4U) & (0x03U)) | ((_m->BCM_Reserved1 & (0x3FU)) << 2U) ); + _d[4] |= (uint8_t) ( ((_m->BCM_Reserved1 >> 6U) & (0x03U)) | ((_m->BCM_Reserved2 & (0x3FU)) << 2U) ); + _d[5] |= (uint8_t) ( ((_m->BCM_Reserved2 >> 6U) & (0x03U)) | ((_m->BCM_Reserved3 & (0x3FU)) << 2U) ); + _d[6] |= (uint8_t) ( ((_m->BCM_Reserved3 >> 6U) & (0x03U)) | ((_m->BCM_Reserved4 & (0x3FU)) << 2U) ); + _d[7] |= (uint8_t) ( ((_m->BCM_Reserved4 >> 6U) & (0x03U)) | ((_m->BCM_Reserved5 & (0x3FU)) << 2U) ); + + *_len = (uint8_t) BCM_StyleCmd1_DLC; + *_ide = (uint8_t) BCM_StyleCmd1_IDE; + return BCM_StyleCmd1_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_Access_Msg1_candb(FIU_Access_Msg1_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->FIU_BTDevice_Stat = (uint8_t) ( (_d[0] & (0x03U)) ); + _m->FIU_NAVI_Stat = (uint8_t) ( ((_d[0] >> 2U) & (0x03U)) ); + _m->FIU_Deleting_Req = (uint8_t) ( ((_d[0] >> 5U) & (0x03U)) ); + _m->FIU_Pairing_Req = (uint8_t) ( ((_d[0] >> 7U) & (0x01U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < FIU_Access_Msg1_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_FIU_Access_Msg1_candb(&_m->mon1, FIU_Access_Msg1_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return FIU_Access_Msg1_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_FIU_Access_Msg1_candb(FIU_Access_Msg1_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_Access_Msg1_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->FIU_BTDevice_Stat & (0x03U)) | ((_m->FIU_NAVI_Stat & (0x03U)) << 2U) | ((_m->FIU_Deleting_Req & (0x03U)) << 5U) | ((_m->FIU_Pairing_Req & (0x01U)) << 7U) ); + + cframe->MsgId = (uint32_t) FIU_Access_Msg1_CANID; + cframe->DLC = (uint8_t) FIU_Access_Msg1_DLC; + cframe->IDE = (uint8_t) FIU_Access_Msg1_IDE; + return FIU_Access_Msg1_CANID; +} + +#else + +uint32_t Pack_FIU_Access_Msg1_candb(FIU_Access_Msg1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_Access_Msg1_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->FIU_BTDevice_Stat & (0x03U)) | ((_m->FIU_NAVI_Stat & (0x03U)) << 2U) | ((_m->FIU_Deleting_Req & (0x03U)) << 5U) | ((_m->FIU_Pairing_Req & (0x01U)) << 7U) ); + + *_len = (uint8_t) FIU_Access_Msg1_DLC; + *_ide = (uint8_t) FIU_Access_Msg1_IDE; + return FIU_Access_Msg1_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_DMFR_Msg1_candb(DMFR_Msg1_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->DMFR_WarningInd = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->DMFR_DoorLockState = (uint8_t) ( ((_d[0] >> 1U) & (0x03U)) ); + _m->DMFR_DoorAjarState = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + _m->DMFR_DoorAjarFault_Stat = (uint8_t) ( ((_d[0] >> 4U) & (0x01U)) ); + _m->DMFR_MirrorHeating_Status = (uint8_t) ( ((_d[0] >> 5U) & (0x03U)) ); + _m->DMFR_WindowFullyClosed_Stat = (uint8_t) ( ((_d[0] >> 7U) & (0x01U)) ); + _m->DMFR_IntDoorHandle_Req = (uint8_t) ( (_d[1] & (0x01U)) ); + _m->DMFR_IntDoorLockSw_Cmd = (uint8_t) ( ((_d[1] >> 1U) & (0x03U)) ); + _m->DMFR_ShortDrop_Stat = (uint8_t) ( ((_d[1] >> 3U) & (0x01U)) ); + _m->DMFR_Comm_Req = (uint8_t) ( ((_d[1] >> 4U) & (0x01U)) ); + _m->DMFR_DoorMovement_Stat = (uint8_t) ( ((_d[1] >> 5U) & (0x07U)) ); + _m->DMFR_DoorDirection_Stat = (uint8_t) ( (_d[2] & (0x03U)) ); + _m->DMFR_Antipinch_Stat = (uint8_t) ( ((_d[2] >> 2U) & (0x01U)) ); + _m->DMFR_BSDLed_Stat = (uint8_t) ( ((_d[2] >> 3U) & (0x01U)) ); + _m->DMFR_DoorCloseSw_Req = (uint8_t) ( ((_d[2] >> 4U) & (0x01U)) ); + _m->DMFR_TurnInd_Stat = (uint8_t) ( ((_d[2] >> 6U) & (0x03U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < DMFR_Msg1_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_DMFR_Msg1_candb(&_m->mon1, DMFR_Msg1_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return DMFR_Msg1_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_DMFR_Msg1_candb(DMFR_Msg1_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(DMFR_Msg1_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->DMFR_WarningInd & (0x01U)) | ((_m->DMFR_DoorLockState & (0x03U)) << 1U) | ((_m->DMFR_DoorAjarState & (0x01U)) << 3U) | ((_m->DMFR_DoorAjarFault_Stat & (0x01U)) << 4U) | ((_m->DMFR_MirrorHeating_Status & (0x03U)) << 5U) | ((_m->DMFR_WindowFullyClosed_Stat & (0x01U)) << 7U) ); + cframe->Data[1] |= (uint8_t) ( (_m->DMFR_IntDoorHandle_Req & (0x01U)) | ((_m->DMFR_IntDoorLockSw_Cmd & (0x03U)) << 1U) | ((_m->DMFR_ShortDrop_Stat & (0x01U)) << 3U) | ((_m->DMFR_Comm_Req & (0x01U)) << 4U) | ((_m->DMFR_DoorMovement_Stat & (0x07U)) << 5U) ); + cframe->Data[2] |= (uint8_t) ( (_m->DMFR_DoorDirection_Stat & (0x03U)) | ((_m->DMFR_Antipinch_Stat & (0x01U)) << 2U) | ((_m->DMFR_BSDLed_Stat & (0x01U)) << 3U) | ((_m->DMFR_DoorCloseSw_Req & (0x01U)) << 4U) | ((_m->DMFR_TurnInd_Stat & (0x03U)) << 6U) ); + + cframe->MsgId = (uint32_t) DMFR_Msg1_CANID; + cframe->DLC = (uint8_t) DMFR_Msg1_DLC; + cframe->IDE = (uint8_t) DMFR_Msg1_IDE; + return DMFR_Msg1_CANID; +} + +#else + +uint32_t Pack_DMFR_Msg1_candb(DMFR_Msg1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(DMFR_Msg1_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->DMFR_WarningInd & (0x01U)) | ((_m->DMFR_DoorLockState & (0x03U)) << 1U) | ((_m->DMFR_DoorAjarState & (0x01U)) << 3U) | ((_m->DMFR_DoorAjarFault_Stat & (0x01U)) << 4U) | ((_m->DMFR_MirrorHeating_Status & (0x03U)) << 5U) | ((_m->DMFR_WindowFullyClosed_Stat & (0x01U)) << 7U) ); + _d[1] |= (uint8_t) ( (_m->DMFR_IntDoorHandle_Req & (0x01U)) | ((_m->DMFR_IntDoorLockSw_Cmd & (0x03U)) << 1U) | ((_m->DMFR_ShortDrop_Stat & (0x01U)) << 3U) | ((_m->DMFR_Comm_Req & (0x01U)) << 4U) | ((_m->DMFR_DoorMovement_Stat & (0x07U)) << 5U) ); + _d[2] |= (uint8_t) ( (_m->DMFR_DoorDirection_Stat & (0x03U)) | ((_m->DMFR_Antipinch_Stat & (0x01U)) << 2U) | ((_m->DMFR_BSDLed_Stat & (0x01U)) << 3U) | ((_m->DMFR_DoorCloseSw_Req & (0x01U)) << 4U) | ((_m->DMFR_TurnInd_Stat & (0x03U)) << 6U) ); + + *_len = (uint8_t) DMFR_Msg1_DLC; + *_ide = (uint8_t) DMFR_Msg1_IDE; + return DMFR_Msg1_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_DMFL_Msg1_candb(DMFL_Msg1_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->DMFL_KeyCylinder_Req = (uint8_t) ( (_d[0] & (0x03U)) ); + _m->DMFL_WarningInd = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + _m->DMFL_DoorLockState = (uint8_t) ( ((_d[0] >> 3U) & (0x03U)) ); + _m->DMFL_DoorAjarState = (uint8_t) ( ((_d[0] >> 5U) & (0x01U)) ); + _m->DMFL_ChildLockCentralTab_Stat = (uint8_t) ( ((_d[0] >> 6U) & (0x01U)) ); + _m->DMFL_DoorCloseSw_Req = (uint8_t) ( ((_d[0] >> 7U) & (0x01U)) ); + _m->DMFL_MirrorHeating_Status = (uint8_t) ( (_d[1] & (0x03U)) ); + _m->DMFL_IntDoorHandle_Req = (uint8_t) ( ((_d[1] >> 2U) & (0x01U)) ); + _m->DMFL_ChildLock_RLwindow_Stat = (uint8_t) ( ((_d[1] >> 3U) & (0x01U)) ); + _m->DMFL_ChildLockRLTab_Stat = (uint8_t) ( ((_d[1] >> 4U) & (0x01U)) ); + _m->DMFL_IntDoorLockSw_Cmd = (uint8_t) ( ((_d[1] >> 5U) & (0x03U)) ); + _m->DMFL_ChildLockRRTab_Stat = (uint8_t) ( ((_d[1] >> 7U) & (0x01U)) ); + _m->DMFL_FRWindow_Cmd = (uint8_t) ( ((_d[2] >> 1U) & (0x07U)) ); + _m->DMFL_RLWindow_Cmd = (uint8_t) ( ((_d[2] >> 4U) & (0x07U)) ); + _m->DMFL_RightMirrorTilt_Cmd = (uint8_t) ( ((_d[2] >> 7U) & (0x01U)) ); + _m->DMFL_RRWindow_Cmd = (uint8_t) ( (_d[3] & (0x07U)) ); + _m->DMFL_RightMirrorAdjust_Cmd = (uint8_t) ( ((_d[3] >> 3U) & (0x07U)) ); + _m->DMFL_RightMirrorFold_Cmd = (uint8_t) ( ((_d[3] >> 6U) & (0x03U)) ); + _m->DMFL_WindowFullyClosed_Stat = (uint8_t) ( (_d[4] & (0x01U)) ); + _m->DMFL_Comm_Req = (uint8_t) ( ((_d[4] >> 2U) & (0x01U)) ); + _m->DMFL_ChildLock_Stat = (uint8_t) ( ((_d[4] >> 3U) & (0x01U)) ); + _m->DMFL_DoorMovement_Stat = (uint8_t) ( ((_d[4] >> 4U) & (0x07U)) ); + _m->DMFL_Antipinch_Stat = (uint8_t) ( ((_d[4] >> 7U) & (0x01U)) ); + _m->DMFL_DoorDirection_Stat = (uint8_t) ( (_d[5] & (0x03U)) ); + _m->DMFL_BSDLed_Stat = (uint8_t) ( ((_d[5] >> 2U) & (0x01U)) ); + _m->DMFL_DoorAjarFault_Stat = (uint8_t) ( ((_d[5] >> 3U) & (0x01U)) ); + _m->DMFL_ShortDrop_Stat = (uint8_t) ( ((_d[5] >> 4U) & (0x01U)) ); + _m->DMFL_TurnInd_Stat = (uint8_t) ( ((_d[5] >> 5U) & (0x03U)) ); + _m->DMFL_ChildLock_RRwindow_Stat = (uint8_t) ( ((_d[5] >> 7U) & (0x01U)) ); + _m->DMFL_RearWindowCurtain_Req = (uint8_t) ( (_d[6] & (0x03U)) ); + _m->DMFL_ChildLock_RLdoor_Stat = (uint8_t) ( ((_d[6] >> 2U) & (0x01U)) ); + _m->DMFL_ChildLock_RRdoor_Stat = (uint8_t) ( ((_d[6] >> 4U) & (0x01U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < DMFL_Msg1_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_DMFL_Msg1_candb(&_m->mon1, DMFL_Msg1_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return DMFL_Msg1_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_DMFL_Msg1_candb(DMFL_Msg1_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(DMFL_Msg1_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->DMFL_KeyCylinder_Req & (0x03U)) | ((_m->DMFL_WarningInd & (0x01U)) << 2U) | ((_m->DMFL_DoorLockState & (0x03U)) << 3U) | ((_m->DMFL_DoorAjarState & (0x01U)) << 5U) | ((_m->DMFL_ChildLockCentralTab_Stat & (0x01U)) << 6U) | ((_m->DMFL_DoorCloseSw_Req & (0x01U)) << 7U) ); + cframe->Data[1] |= (uint8_t) ( (_m->DMFL_MirrorHeating_Status & (0x03U)) | ((_m->DMFL_IntDoorHandle_Req & (0x01U)) << 2U) | ((_m->DMFL_ChildLock_RLwindow_Stat & (0x01U)) << 3U) | ((_m->DMFL_ChildLockRLTab_Stat & (0x01U)) << 4U) | ((_m->DMFL_IntDoorLockSw_Cmd & (0x03U)) << 5U) | ((_m->DMFL_ChildLockRRTab_Stat & (0x01U)) << 7U) ); + cframe->Data[2] |= (uint8_t) ( ((_m->DMFL_FRWindow_Cmd & (0x07U)) << 1U) | ((_m->DMFL_RLWindow_Cmd & (0x07U)) << 4U) | ((_m->DMFL_RightMirrorTilt_Cmd & (0x01U)) << 7U) ); + cframe->Data[3] |= (uint8_t) ( (_m->DMFL_RRWindow_Cmd & (0x07U)) | ((_m->DMFL_RightMirrorAdjust_Cmd & (0x07U)) << 3U) | ((_m->DMFL_RightMirrorFold_Cmd & (0x03U)) << 6U) ); + cframe->Data[4] |= (uint8_t) ( (_m->DMFL_WindowFullyClosed_Stat & (0x01U)) | ((_m->DMFL_Comm_Req & (0x01U)) << 2U) | ((_m->DMFL_ChildLock_Stat & (0x01U)) << 3U) | ((_m->DMFL_DoorMovement_Stat & (0x07U)) << 4U) | ((_m->DMFL_Antipinch_Stat & (0x01U)) << 7U) ); + cframe->Data[5] |= (uint8_t) ( (_m->DMFL_DoorDirection_Stat & (0x03U)) | ((_m->DMFL_BSDLed_Stat & (0x01U)) << 2U) | ((_m->DMFL_DoorAjarFault_Stat & (0x01U)) << 3U) | ((_m->DMFL_ShortDrop_Stat & (0x01U)) << 4U) | ((_m->DMFL_TurnInd_Stat & (0x03U)) << 5U) | ((_m->DMFL_ChildLock_RRwindow_Stat & (0x01U)) << 7U) ); + cframe->Data[6] |= (uint8_t) ( (_m->DMFL_RearWindowCurtain_Req & (0x03U)) | ((_m->DMFL_ChildLock_RLdoor_Stat & (0x01U)) << 2U) | ((_m->DMFL_ChildLock_RRdoor_Stat & (0x01U)) << 4U) ); + + cframe->MsgId = (uint32_t) DMFL_Msg1_CANID; + cframe->DLC = (uint8_t) DMFL_Msg1_DLC; + cframe->IDE = (uint8_t) DMFL_Msg1_IDE; + return DMFL_Msg1_CANID; +} + +#else + +uint32_t Pack_DMFL_Msg1_candb(DMFL_Msg1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(DMFL_Msg1_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->DMFL_KeyCylinder_Req & (0x03U)) | ((_m->DMFL_WarningInd & (0x01U)) << 2U) | ((_m->DMFL_DoorLockState & (0x03U)) << 3U) | ((_m->DMFL_DoorAjarState & (0x01U)) << 5U) | ((_m->DMFL_ChildLockCentralTab_Stat & (0x01U)) << 6U) | ((_m->DMFL_DoorCloseSw_Req & (0x01U)) << 7U) ); + _d[1] |= (uint8_t) ( (_m->DMFL_MirrorHeating_Status & (0x03U)) | ((_m->DMFL_IntDoorHandle_Req & (0x01U)) << 2U) | ((_m->DMFL_ChildLock_RLwindow_Stat & (0x01U)) << 3U) | ((_m->DMFL_ChildLockRLTab_Stat & (0x01U)) << 4U) | ((_m->DMFL_IntDoorLockSw_Cmd & (0x03U)) << 5U) | ((_m->DMFL_ChildLockRRTab_Stat & (0x01U)) << 7U) ); + _d[2] |= (uint8_t) ( ((_m->DMFL_FRWindow_Cmd & (0x07U)) << 1U) | ((_m->DMFL_RLWindow_Cmd & (0x07U)) << 4U) | ((_m->DMFL_RightMirrorTilt_Cmd & (0x01U)) << 7U) ); + _d[3] |= (uint8_t) ( (_m->DMFL_RRWindow_Cmd & (0x07U)) | ((_m->DMFL_RightMirrorAdjust_Cmd & (0x07U)) << 3U) | ((_m->DMFL_RightMirrorFold_Cmd & (0x03U)) << 6U) ); + _d[4] |= (uint8_t) ( (_m->DMFL_WindowFullyClosed_Stat & (0x01U)) | ((_m->DMFL_Comm_Req & (0x01U)) << 2U) | ((_m->DMFL_ChildLock_Stat & (0x01U)) << 3U) | ((_m->DMFL_DoorMovement_Stat & (0x07U)) << 4U) | ((_m->DMFL_Antipinch_Stat & (0x01U)) << 7U) ); + _d[5] |= (uint8_t) ( (_m->DMFL_DoorDirection_Stat & (0x03U)) | ((_m->DMFL_BSDLed_Stat & (0x01U)) << 2U) | ((_m->DMFL_DoorAjarFault_Stat & (0x01U)) << 3U) | ((_m->DMFL_ShortDrop_Stat & (0x01U)) << 4U) | ((_m->DMFL_TurnInd_Stat & (0x03U)) << 5U) | ((_m->DMFL_ChildLock_RRwindow_Stat & (0x01U)) << 7U) ); + _d[6] |= (uint8_t) ( (_m->DMFL_RearWindowCurtain_Req & (0x03U)) | ((_m->DMFL_ChildLock_RLdoor_Stat & (0x01U)) << 2U) | ((_m->DMFL_ChildLock_RRdoor_Stat & (0x01U)) << 4U) ); + + *_len = (uint8_t) DMFL_Msg1_DLC; + *_ide = (uint8_t) DMFL_Msg1_IDE; + return DMFL_Msg1_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_DMRL_Msg1_candb(DMRL_Msg1_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->DMRL_WarningInd = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->DMRL_DoorLockState = (uint8_t) ( ((_d[0] >> 1U) & (0x03U)) ); + _m->DMRL_DoorAjarState = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + _m->DMRL_DoorCloseSw_Req = (uint8_t) ( ((_d[0] >> 4U) & (0x01U)) ); + _m->DMRL_IntDoorHandle_Req = (uint8_t) ( ((_d[0] >> 5U) & (0x01U)) ); + _m->DMRL_IntDoorLockSw_Cmd = (uint8_t) ( ((_d[0] >> 6U) & (0x03U)) ); + _m->DMRL_ChildLock_Stat = (uint8_t) ( (_d[1] & (0x03U)) ); + _m->DMRL_VolumeLevel_Cmd = (uint8_t) ( ((_d[1] >> 2U) & (0x07U)) ); + _m->DMRL_WindowFullyClosed_Stat = (uint8_t) ( ((_d[1] >> 5U) & (0x01U)) ); + _m->DMRL_Multimedia_Req = (uint8_t) ( (_d[2] & (0x03U)) ); + _m->DMRL_Comm_Req = (uint8_t) ( ((_d[2] >> 2U) & (0x01U)) ); + _m->DMRL_DoorAjarFault_Stat = (uint8_t) ( ((_d[2] >> 3U) & (0x01U)) ); + _m->DMRL_DoorMovement_Stat = (uint8_t) ( ((_d[2] >> 4U) & (0x07U)) ); + _m->DMRL_Antipinch_Stat = (uint8_t) ( ((_d[2] >> 7U) & (0x01U)) ); + _m->DMRL_DoorDirection_Stat = (uint8_t) ( (_d[3] & (0x03U)) ); + _m->DMRL_RR_Window_Cmd = (uint8_t) ( ((_d[3] >> 3U) & (0x07U)) ); + _m->DMRL_ElcromeBright_Stat = (uint8_t) ( ((_d[3] >> 6U) & (0x03U)) ); + _m->DMRL_SunShade_Stat = (uint8_t) ( (_d[4] & (0x07U)) ); + _m->DMRL_RearCurtain_Req = (uint8_t) ( ((_d[4] >> 4U) & (0x03U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < DMRL_Msg1_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_DMRL_Msg1_candb(&_m->mon1, DMRL_Msg1_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return DMRL_Msg1_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_DMRL_Msg1_candb(DMRL_Msg1_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(DMRL_Msg1_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->DMRL_WarningInd & (0x01U)) | ((_m->DMRL_DoorLockState & (0x03U)) << 1U) | ((_m->DMRL_DoorAjarState & (0x01U)) << 3U) | ((_m->DMRL_DoorCloseSw_Req & (0x01U)) << 4U) | ((_m->DMRL_IntDoorHandle_Req & (0x01U)) << 5U) | ((_m->DMRL_IntDoorLockSw_Cmd & (0x03U)) << 6U) ); + cframe->Data[1] |= (uint8_t) ( (_m->DMRL_ChildLock_Stat & (0x03U)) | ((_m->DMRL_VolumeLevel_Cmd & (0x07U)) << 2U) | ((_m->DMRL_WindowFullyClosed_Stat & (0x01U)) << 5U) ); + cframe->Data[2] |= (uint8_t) ( (_m->DMRL_Multimedia_Req & (0x03U)) | ((_m->DMRL_Comm_Req & (0x01U)) << 2U) | ((_m->DMRL_DoorAjarFault_Stat & (0x01U)) << 3U) | ((_m->DMRL_DoorMovement_Stat & (0x07U)) << 4U) | ((_m->DMRL_Antipinch_Stat & (0x01U)) << 7U) ); + cframe->Data[3] |= (uint8_t) ( (_m->DMRL_DoorDirection_Stat & (0x03U)) | ((_m->DMRL_RR_Window_Cmd & (0x07U)) << 3U) | ((_m->DMRL_ElcromeBright_Stat & (0x03U)) << 6U) ); + cframe->Data[4] |= (uint8_t) ( (_m->DMRL_SunShade_Stat & (0x07U)) | ((_m->DMRL_RearCurtain_Req & (0x03U)) << 4U) ); + + cframe->MsgId = (uint32_t) DMRL_Msg1_CANID; + cframe->DLC = (uint8_t) DMRL_Msg1_DLC; + cframe->IDE = (uint8_t) DMRL_Msg1_IDE; + return DMRL_Msg1_CANID; +} + +#else + +uint32_t Pack_DMRL_Msg1_candb(DMRL_Msg1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(DMRL_Msg1_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->DMRL_WarningInd & (0x01U)) | ((_m->DMRL_DoorLockState & (0x03U)) << 1U) | ((_m->DMRL_DoorAjarState & (0x01U)) << 3U) | ((_m->DMRL_DoorCloseSw_Req & (0x01U)) << 4U) | ((_m->DMRL_IntDoorHandle_Req & (0x01U)) << 5U) | ((_m->DMRL_IntDoorLockSw_Cmd & (0x03U)) << 6U) ); + _d[1] |= (uint8_t) ( (_m->DMRL_ChildLock_Stat & (0x03U)) | ((_m->DMRL_VolumeLevel_Cmd & (0x07U)) << 2U) | ((_m->DMRL_WindowFullyClosed_Stat & (0x01U)) << 5U) ); + _d[2] |= (uint8_t) ( (_m->DMRL_Multimedia_Req & (0x03U)) | ((_m->DMRL_Comm_Req & (0x01U)) << 2U) | ((_m->DMRL_DoorAjarFault_Stat & (0x01U)) << 3U) | ((_m->DMRL_DoorMovement_Stat & (0x07U)) << 4U) | ((_m->DMRL_Antipinch_Stat & (0x01U)) << 7U) ); + _d[3] |= (uint8_t) ( (_m->DMRL_DoorDirection_Stat & (0x03U)) | ((_m->DMRL_RR_Window_Cmd & (0x07U)) << 3U) | ((_m->DMRL_ElcromeBright_Stat & (0x03U)) << 6U) ); + _d[4] |= (uint8_t) ( (_m->DMRL_SunShade_Stat & (0x07U)) | ((_m->DMRL_RearCurtain_Req & (0x03U)) << 4U) ); + + *_len = (uint8_t) DMRL_Msg1_DLC; + *_ide = (uint8_t) DMRL_Msg1_IDE; + return DMRL_Msg1_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_DMRR_Msg1_candb(DMRR_Msg1_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->DMRR_WarningInd = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->DMRR_DoorLockState = (uint8_t) ( ((_d[0] >> 1U) & (0x03U)) ); + _m->DMRR_DoorAjarState = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + _m->DMRR_DoorCloseSw_Req = (uint8_t) ( ((_d[0] >> 4U) & (0x01U)) ); + _m->DMRR_IntDoorHandle_Req = (uint8_t) ( ((_d[0] >> 5U) & (0x01U)) ); + _m->DMRR_IntDoorLockSw_Cmd = (uint8_t) ( ((_d[0] >> 6U) & (0x03U)) ); + _m->DMRR_ChildLock_Stat = (uint8_t) ( (_d[1] & (0x03U)) ); + _m->DMRR_VolumeLevel_Cmd = (uint8_t) ( ((_d[1] >> 2U) & (0x07U)) ); + _m->DMRR_WindowFullyClosed_Stat = (uint8_t) ( ((_d[1] >> 5U) & (0x01U)) ); + _m->DMRR_Multimedia_Req = (uint8_t) ( (_d[2] & (0x03U)) ); + _m->DMRR_Comm_Req = (uint8_t) ( ((_d[2] >> 2U) & (0x01U)) ); + _m->DMRR_DoorAjarFault_Stat = (uint8_t) ( ((_d[2] >> 3U) & (0x01U)) ); + _m->DMRR_DoorMovement_Stat = (uint8_t) ( ((_d[2] >> 4U) & (0x07U)) ); + _m->DMRR_Antipinch_Stat = (uint8_t) ( ((_d[2] >> 7U) & (0x01U)) ); + _m->DMRR_DoorDirection_Stat = (uint8_t) ( (_d[3] & (0x03U)) ); + _m->DMRR_RL_Window_Cmd = (uint8_t) ( ((_d[3] >> 3U) & (0x07U)) ); + _m->DMRR_ElcromeBright_Stat = (uint8_t) ( ((_d[3] >> 6U) & (0x03U)) ); + _m->DMRR_SunShade_Stat = (uint8_t) ( (_d[4] & (0x07U)) ); + _m->DMRR_RearCurtain_Req = (uint8_t) ( ((_d[4] >> 4U) & (0x03U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < DMRR_Msg1_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_DMRR_Msg1_candb(&_m->mon1, DMRR_Msg1_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return DMRR_Msg1_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_DMRR_Msg1_candb(DMRR_Msg1_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(DMRR_Msg1_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->DMRR_WarningInd & (0x01U)) | ((_m->DMRR_DoorLockState & (0x03U)) << 1U) | ((_m->DMRR_DoorAjarState & (0x01U)) << 3U) | ((_m->DMRR_DoorCloseSw_Req & (0x01U)) << 4U) | ((_m->DMRR_IntDoorHandle_Req & (0x01U)) << 5U) | ((_m->DMRR_IntDoorLockSw_Cmd & (0x03U)) << 6U) ); + cframe->Data[1] |= (uint8_t) ( (_m->DMRR_ChildLock_Stat & (0x03U)) | ((_m->DMRR_VolumeLevel_Cmd & (0x07U)) << 2U) | ((_m->DMRR_WindowFullyClosed_Stat & (0x01U)) << 5U) ); + cframe->Data[2] |= (uint8_t) ( (_m->DMRR_Multimedia_Req & (0x03U)) | ((_m->DMRR_Comm_Req & (0x01U)) << 2U) | ((_m->DMRR_DoorAjarFault_Stat & (0x01U)) << 3U) | ((_m->DMRR_DoorMovement_Stat & (0x07U)) << 4U) | ((_m->DMRR_Antipinch_Stat & (0x01U)) << 7U) ); + cframe->Data[3] |= (uint8_t) ( (_m->DMRR_DoorDirection_Stat & (0x03U)) | ((_m->DMRR_RL_Window_Cmd & (0x07U)) << 3U) | ((_m->DMRR_ElcromeBright_Stat & (0x03U)) << 6U) ); + cframe->Data[4] |= (uint8_t) ( (_m->DMRR_SunShade_Stat & (0x07U)) | ((_m->DMRR_RearCurtain_Req & (0x03U)) << 4U) ); + + cframe->MsgId = (uint32_t) DMRR_Msg1_CANID; + cframe->DLC = (uint8_t) DMRR_Msg1_DLC; + cframe->IDE = (uint8_t) DMRR_Msg1_IDE; + return DMRR_Msg1_CANID; +} + +#else + +uint32_t Pack_DMRR_Msg1_candb(DMRR_Msg1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(DMRR_Msg1_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->DMRR_WarningInd & (0x01U)) | ((_m->DMRR_DoorLockState & (0x03U)) << 1U) | ((_m->DMRR_DoorAjarState & (0x01U)) << 3U) | ((_m->DMRR_DoorCloseSw_Req & (0x01U)) << 4U) | ((_m->DMRR_IntDoorHandle_Req & (0x01U)) << 5U) | ((_m->DMRR_IntDoorLockSw_Cmd & (0x03U)) << 6U) ); + _d[1] |= (uint8_t) ( (_m->DMRR_ChildLock_Stat & (0x03U)) | ((_m->DMRR_VolumeLevel_Cmd & (0x07U)) << 2U) | ((_m->DMRR_WindowFullyClosed_Stat & (0x01U)) << 5U) ); + _d[2] |= (uint8_t) ( (_m->DMRR_Multimedia_Req & (0x03U)) | ((_m->DMRR_Comm_Req & (0x01U)) << 2U) | ((_m->DMRR_DoorAjarFault_Stat & (0x01U)) << 3U) | ((_m->DMRR_DoorMovement_Stat & (0x07U)) << 4U) | ((_m->DMRR_Antipinch_Stat & (0x01U)) << 7U) ); + _d[3] |= (uint8_t) ( (_m->DMRR_DoorDirection_Stat & (0x03U)) | ((_m->DMRR_RL_Window_Cmd & (0x07U)) << 3U) | ((_m->DMRR_ElcromeBright_Stat & (0x03U)) << 6U) ); + _d[4] |= (uint8_t) ( (_m->DMRR_SunShade_Stat & (0x07U)) | ((_m->DMRR_RearCurtain_Req & (0x03U)) << 4U) ); + + *_len = (uint8_t) DMRR_Msg1_DLC; + *_ide = (uint8_t) DMRR_Msg1_IDE; + return DMRR_Msg1_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_TM_Stat_candb(TM_Stat_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->TM_RearWindowHeating_Stat = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->TM_TrailerConnect_Stat = (uint8_t) ( ((_d[0] >> 1U) & (0x01U)) ); + _m->TM_LockAndCloseSW_Req = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + _m->TM_ExtTrunkSW_Req = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + _m->TM_WarningInd = (uint8_t) ( ((_d[0] >> 4U) & (0x01U)) ); + _m->TM_FuelLid_Stat = (uint8_t) ( ((_d[0] >> 5U) & (0x01U)) ); + _m->TM_Kick_Req = (uint8_t) ( ((_d[0] >> 6U) & (0x01U)) ); + _m->TM_Comm_Req = (uint8_t) ( ((_d[0] >> 7U) & (0x01U)) ); + _m->TM_IntTrunkSW_Req = (uint8_t) ( (_d[1] & (0x01U)) ); + _m->TM_TrunkLatch_Stat = (uint8_t) ( ((_d[1] >> 2U) & (0x03U)) ); + _m->TM_BrakeLightHM_Status = (uint8_t) ( ((_d[1] >> 4U) & (0x01U)) ); + _m->TM_FuelLidOpen_Req = (uint8_t) ( ((_d[1] >> 5U) & (0x01U)) ); + _m->TM_T30spec_Stat = (uint8_t) ( ((_d[1] >> 6U) & (0x01U)) ); + _m->TM_LicensePlateLight_State = (uint8_t) ( (_d[2] & (0x07U)) ); + _m->TM_CoolingBox_Stat = (uint8_t) ( ((_d[2] >> 3U) & (0x03U)) ); + _m->TM_RearCushion_State = (uint8_t) ( (_d[3] & (0x07U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < TM_Stat_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_TM_Stat_candb(&_m->mon1, TM_Stat_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return TM_Stat_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_TM_Stat_candb(TM_Stat_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(TM_Stat_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->TM_RearWindowHeating_Stat & (0x01U)) | ((_m->TM_TrailerConnect_Stat & (0x01U)) << 1U) | ((_m->TM_LockAndCloseSW_Req & (0x01U)) << 2U) | ((_m->TM_ExtTrunkSW_Req & (0x01U)) << 3U) | ((_m->TM_WarningInd & (0x01U)) << 4U) | ((_m->TM_FuelLid_Stat & (0x01U)) << 5U) | ((_m->TM_Kick_Req & (0x01U)) << 6U) | ((_m->TM_Comm_Req & (0x01U)) << 7U) ); + cframe->Data[1] |= (uint8_t) ( (_m->TM_IntTrunkSW_Req & (0x01U)) | ((_m->TM_TrunkLatch_Stat & (0x03U)) << 2U) | ((_m->TM_BrakeLightHM_Status & (0x01U)) << 4U) | ((_m->TM_FuelLidOpen_Req & (0x01U)) << 5U) | ((_m->TM_T30spec_Stat & (0x01U)) << 6U) ); + cframe->Data[2] |= (uint8_t) ( (_m->TM_LicensePlateLight_State & (0x07U)) | ((_m->TM_CoolingBox_Stat & (0x03U)) << 3U) ); + cframe->Data[3] |= (uint8_t) ( (_m->TM_RearCushion_State & (0x07U)) ); + + cframe->MsgId = (uint32_t) TM_Stat_CANID; + cframe->DLC = (uint8_t) TM_Stat_DLC; + cframe->IDE = (uint8_t) TM_Stat_IDE; + return TM_Stat_CANID; +} + +#else + +uint32_t Pack_TM_Stat_candb(TM_Stat_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(TM_Stat_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->TM_RearWindowHeating_Stat & (0x01U)) | ((_m->TM_TrailerConnect_Stat & (0x01U)) << 1U) | ((_m->TM_LockAndCloseSW_Req & (0x01U)) << 2U) | ((_m->TM_ExtTrunkSW_Req & (0x01U)) << 3U) | ((_m->TM_WarningInd & (0x01U)) << 4U) | ((_m->TM_FuelLid_Stat & (0x01U)) << 5U) | ((_m->TM_Kick_Req & (0x01U)) << 6U) | ((_m->TM_Comm_Req & (0x01U)) << 7U) ); + _d[1] |= (uint8_t) ( (_m->TM_IntTrunkSW_Req & (0x01U)) | ((_m->TM_TrunkLatch_Stat & (0x03U)) << 2U) | ((_m->TM_BrakeLightHM_Status & (0x01U)) << 4U) | ((_m->TM_FuelLidOpen_Req & (0x01U)) << 5U) | ((_m->TM_T30spec_Stat & (0x01U)) << 6U) ); + _d[2] |= (uint8_t) ( (_m->TM_LicensePlateLight_State & (0x07U)) | ((_m->TM_CoolingBox_Stat & (0x03U)) << 3U) ); + _d[3] |= (uint8_t) ( (_m->TM_RearCushion_State & (0x07U)) ); + + *_len = (uint8_t) TM_Stat_DLC; + *_ide = (uint8_t) TM_Stat_IDE; + return TM_Stat_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_PTG_Body_Stat_candb(PTG_Body_Stat_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->PowerTailgateAntipinchSts = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->PowerTailgateMotionStatus = (uint8_t) ( ((_d[0] >> 1U) & (0x03U)) ); + _m->PowerTailgateMemoryStored = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + _m->PowerTailgateStatus = (uint8_t) ( ((_d[0] >> 4U) & (0x07U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < PTG_Body_Stat_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_PTG_Body_Stat_candb(&_m->mon1, PTG_Body_Stat_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return PTG_Body_Stat_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_PTG_Body_Stat_candb(PTG_Body_Stat_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(PTG_Body_Stat_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->PowerTailgateAntipinchSts & (0x01U)) | ((_m->PowerTailgateMotionStatus & (0x03U)) << 1U) | ((_m->PowerTailgateMemoryStored & (0x01U)) << 3U) | ((_m->PowerTailgateStatus & (0x07U)) << 4U) ); + + cframe->MsgId = (uint32_t) PTG_Body_Stat_CANID; + cframe->DLC = (uint8_t) PTG_Body_Stat_DLC; + cframe->IDE = (uint8_t) PTG_Body_Stat_IDE; + return PTG_Body_Stat_CANID; +} + +#else + +uint32_t Pack_PTG_Body_Stat_candb(PTG_Body_Stat_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(PTG_Body_Stat_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->PowerTailgateAntipinchSts & (0x01U)) | ((_m->PowerTailgateMotionStatus & (0x03U)) << 1U) | ((_m->PowerTailgateMemoryStored & (0x01U)) << 3U) | ((_m->PowerTailgateStatus & (0x07U)) << 4U) ); + + *_len = (uint8_t) PTG_Body_Stat_DLC; + *_ide = (uint8_t) PTG_Body_Stat_IDE; + return PTG_Body_Stat_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_TM_CP_candb(TM_CP_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->CCPR_TVPowerSw_Stat = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->CCPF_RWindowHeatSw_Stat = (uint8_t) ( ((_d[0] >> 1U) & (0x01U)) ); + _m->CCPF_FWindowHeatSw_Stat = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + _m->CCPR_SrcChgSw_Stat = (uint8_t) ( ((_d[0] >> 4U) & (0x01U)) ); + _m->CCPR_DWClaritySw_Stat = (uint8_t) ( ((_d[0] >> 5U) & (0x01U)) ); + _m->CCPR_IntercomSw_Stat = (uint8_t) ( ((_d[0] >> 6U) & (0x01U)) ); + _m->CCPR_DWCntrlSw_Stat = (uint8_t) ( (_d[1] & (0x03U)) ); + _m->CCPF_MuteSw_Stat = (uint8_t) ( ((_d[1] >> 2U) & (0x03U)) ); + _m->CCPF_VolAjustSw_Stat = (uint8_t) ( ((_d[1] >> 4U) & (0x03U)) ); + _m->CCPR_PanoramicViewSw_Stat = (uint8_t) ( ((_d[1] >> 6U) & (0x03U)) ); + _m->CCPF_AutoButtonR_Stat = (uint8_t) ( (_d[2] & (0x03U)) ); + _m->CCPR_AutoButtonL_Stat = (uint8_t) ( ((_d[2] >> 2U) & (0x03U)) ); + _m->CCPR_AutoButtonR_Stat = (uint8_t) ( ((_d[2] >> 4U) & (0x03U)) ); + _m->CCPF_DefButton_Stat = (uint8_t) ( ((_d[2] >> 6U) & (0x03U)) ); + _m->CCPF_TempToggleR_Stat = (uint8_t) ( (_d[3] & (0x07U)) ); + _m->CCPF_TempToggleL_Stat = (uint8_t) ( ((_d[3] >> 3U) & (0x07U)) ); + _m->CCPF_AutoButtonL_Stat = (uint8_t) ( ((_d[3] >> 6U) & (0x03U)) ); + _m->CCPR_TempToggleR_Stat = (uint8_t) ( (_d[4] & (0x07U)) ); + _m->CCPR_TempToggleL_Stat = (uint8_t) ( ((_d[4] >> 3U) & (0x07U)) ); + _m->CCPF_RecButton_Stat = (uint8_t) ( ((_d[4] >> 6U) & (0x03U)) ); + _m->CCPF_AcMaxButton_Stat = (uint8_t) ( (_d[5] & (0x03U)) ); + _m->CCPR_TabletOffSw_Stat = (uint8_t) ( ((_d[5] >> 2U) & (0x03U)) ); + _m->CCPR_TabletExtractSw_Stat = (uint8_t) ( ((_d[5] >> 6U) & (0x01U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < TM_CP_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_TM_CP_candb(&_m->mon1, TM_CP_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return TM_CP_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_TM_CP_candb(TM_CP_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(TM_CP_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->CCPR_TVPowerSw_Stat & (0x01U)) | ((_m->CCPF_RWindowHeatSw_Stat & (0x01U)) << 1U) | ((_m->CCPF_FWindowHeatSw_Stat & (0x01U)) << 2U) | ((_m->CCPR_SrcChgSw_Stat & (0x01U)) << 4U) | ((_m->CCPR_DWClaritySw_Stat & (0x01U)) << 5U) | ((_m->CCPR_IntercomSw_Stat & (0x01U)) << 6U) ); + cframe->Data[1] |= (uint8_t) ( (_m->CCPR_DWCntrlSw_Stat & (0x03U)) | ((_m->CCPF_MuteSw_Stat & (0x03U)) << 2U) | ((_m->CCPF_VolAjustSw_Stat & (0x03U)) << 4U) | ((_m->CCPR_PanoramicViewSw_Stat & (0x03U)) << 6U) ); + cframe->Data[2] |= (uint8_t) ( (_m->CCPF_AutoButtonR_Stat & (0x03U)) | ((_m->CCPR_AutoButtonL_Stat & (0x03U)) << 2U) | ((_m->CCPR_AutoButtonR_Stat & (0x03U)) << 4U) | ((_m->CCPF_DefButton_Stat & (0x03U)) << 6U) ); + cframe->Data[3] |= (uint8_t) ( (_m->CCPF_TempToggleR_Stat & (0x07U)) | ((_m->CCPF_TempToggleL_Stat & (0x07U)) << 3U) | ((_m->CCPF_AutoButtonL_Stat & (0x03U)) << 6U) ); + cframe->Data[4] |= (uint8_t) ( (_m->CCPR_TempToggleR_Stat & (0x07U)) | ((_m->CCPR_TempToggleL_Stat & (0x07U)) << 3U) | ((_m->CCPF_RecButton_Stat & (0x03U)) << 6U) ); + cframe->Data[5] |= (uint8_t) ( (_m->CCPF_AcMaxButton_Stat & (0x03U)) | ((_m->CCPR_TabletOffSw_Stat & (0x03U)) << 2U) | ((_m->CCPR_TabletExtractSw_Stat & (0x01U)) << 6U) ); + + cframe->MsgId = (uint32_t) TM_CP_CANID; + cframe->DLC = (uint8_t) TM_CP_DLC; + cframe->IDE = (uint8_t) TM_CP_IDE; + return TM_CP_CANID; +} + +#else + +uint32_t Pack_TM_CP_candb(TM_CP_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(TM_CP_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->CCPR_TVPowerSw_Stat & (0x01U)) | ((_m->CCPF_RWindowHeatSw_Stat & (0x01U)) << 1U) | ((_m->CCPF_FWindowHeatSw_Stat & (0x01U)) << 2U) | ((_m->CCPR_SrcChgSw_Stat & (0x01U)) << 4U) | ((_m->CCPR_DWClaritySw_Stat & (0x01U)) << 5U) | ((_m->CCPR_IntercomSw_Stat & (0x01U)) << 6U) ); + _d[1] |= (uint8_t) ( (_m->CCPR_DWCntrlSw_Stat & (0x03U)) | ((_m->CCPF_MuteSw_Stat & (0x03U)) << 2U) | ((_m->CCPF_VolAjustSw_Stat & (0x03U)) << 4U) | ((_m->CCPR_PanoramicViewSw_Stat & (0x03U)) << 6U) ); + _d[2] |= (uint8_t) ( (_m->CCPF_AutoButtonR_Stat & (0x03U)) | ((_m->CCPR_AutoButtonL_Stat & (0x03U)) << 2U) | ((_m->CCPR_AutoButtonR_Stat & (0x03U)) << 4U) | ((_m->CCPF_DefButton_Stat & (0x03U)) << 6U) ); + _d[3] |= (uint8_t) ( (_m->CCPF_TempToggleR_Stat & (0x07U)) | ((_m->CCPF_TempToggleL_Stat & (0x07U)) << 3U) | ((_m->CCPF_AutoButtonL_Stat & (0x03U)) << 6U) ); + _d[4] |= (uint8_t) ( (_m->CCPR_TempToggleR_Stat & (0x07U)) | ((_m->CCPR_TempToggleL_Stat & (0x07U)) << 3U) | ((_m->CCPF_RecButton_Stat & (0x03U)) << 6U) ); + _d[5] |= (uint8_t) ( (_m->CCPF_AcMaxButton_Stat & (0x03U)) | ((_m->CCPR_TabletOffSw_Stat & (0x03U)) << 2U) | ((_m->CCPR_TabletExtractSw_Stat & (0x01U)) << 6U) ); + + *_len = (uint8_t) TM_CP_DLC; + *_ide = (uint8_t) TM_CP_IDE; + return TM_CP_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_VAU2_Msg2_candb(VAU2_Msg2_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->VAU_WarningInd = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->VAU_ExteriorKeyFobSwReq = (uint8_t) ( ((_d[0] >> 1U) & (0x0FU)) ); + _m->VAU_DeviceAreaDetecting = (uint8_t) ( ((_d[0] >> 5U) & (0x07U)) ); + _m->VAU_KeyBattLowCharge = (uint8_t) ( (_d[1] & (0x01U)) ); + _m->VAU_WelcomeLights_Req = (uint8_t) ( ((_d[1] >> 1U) & (0x01U)) ); + _m->VAU_ApproachLock_Req = (uint8_t) ( ((_d[1] >> 2U) & (0x03U)) ); + _m->VAU_Router_DevicePairing = (uint8_t) ( ((_d[1] >> 4U) & (0x0FU)) ); + _m->VAU_WChF_Req = (uint8_t) ( (_d[2] & (0x01U)) ); + _m->VAU_BLE_FL_Door_Req = (uint8_t) ( ((_d[2] >> 1U) & (0x03U)) ); + _m->VAU_BLE_FR_Door_Req = (uint8_t) ( ((_d[2] >> 3U) & (0x03U)) ); + _m->VAU_BLE_RL_Door_Req = (uint8_t) ( ((_d[2] >> 5U) & (0x03U)) ); + _m->VAU_RS_Req = (uint8_t) ( ((_d[2] >> 7U) & (0x01U)) ); + _m->VAU_BLE_RR_Door_Req = (uint8_t) ( (_d[3] & (0x03U)) ); + _m->VAU_BLE_CloseWndw_Req = (uint8_t) ( ((_d[3] >> 2U) & (0x03U)) ); + _m->VAU_BLE_TrunkOpn_Req = (uint8_t) ( ((_d[3] >> 4U) & (0x03U)) ); + _m->VAU_BLE_Lock_Req = (uint8_t) ( ((_d[3] >> 6U) & (0x03U)) ); + _m->VAU_BLE_RS_Req = (uint8_t) ( (_d[4] & (0x01U)) ); + _m->VAU_Device_ID = (uint8_t) ( ((_d[4] >> 1U) & (0x0FU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < VAU2_Msg2_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_VAU2_Msg2_candb(&_m->mon1, VAU2_Msg2_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return VAU2_Msg2_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_VAU2_Msg2_candb(VAU2_Msg2_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(VAU2_Msg2_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->VAU_WarningInd & (0x01U)) | ((_m->VAU_ExteriorKeyFobSwReq & (0x0FU)) << 1U) | ((_m->VAU_DeviceAreaDetecting & (0x07U)) << 5U) ); + cframe->Data[1] |= (uint8_t) ( (_m->VAU_KeyBattLowCharge & (0x01U)) | ((_m->VAU_WelcomeLights_Req & (0x01U)) << 1U) | ((_m->VAU_ApproachLock_Req & (0x03U)) << 2U) | ((_m->VAU_Router_DevicePairing & (0x0FU)) << 4U) ); + cframe->Data[2] |= (uint8_t) ( (_m->VAU_WChF_Req & (0x01U)) | ((_m->VAU_BLE_FL_Door_Req & (0x03U)) << 1U) | ((_m->VAU_BLE_FR_Door_Req & (0x03U)) << 3U) | ((_m->VAU_BLE_RL_Door_Req & (0x03U)) << 5U) | ((_m->VAU_RS_Req & (0x01U)) << 7U) ); + cframe->Data[3] |= (uint8_t) ( (_m->VAU_BLE_RR_Door_Req & (0x03U)) | ((_m->VAU_BLE_CloseWndw_Req & (0x03U)) << 2U) | ((_m->VAU_BLE_TrunkOpn_Req & (0x03U)) << 4U) | ((_m->VAU_BLE_Lock_Req & (0x03U)) << 6U) ); + cframe->Data[4] |= (uint8_t) ( (_m->VAU_BLE_RS_Req & (0x01U)) | ((_m->VAU_Device_ID & (0x0FU)) << 1U) ); + + cframe->MsgId = (uint32_t) VAU2_Msg2_CANID; + cframe->DLC = (uint8_t) VAU2_Msg2_DLC; + cframe->IDE = (uint8_t) VAU2_Msg2_IDE; + return VAU2_Msg2_CANID; +} + +#else + +uint32_t Pack_VAU2_Msg2_candb(VAU2_Msg2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(VAU2_Msg2_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->VAU_WarningInd & (0x01U)) | ((_m->VAU_ExteriorKeyFobSwReq & (0x0FU)) << 1U) | ((_m->VAU_DeviceAreaDetecting & (0x07U)) << 5U) ); + _d[1] |= (uint8_t) ( (_m->VAU_KeyBattLowCharge & (0x01U)) | ((_m->VAU_WelcomeLights_Req & (0x01U)) << 1U) | ((_m->VAU_ApproachLock_Req & (0x03U)) << 2U) | ((_m->VAU_Router_DevicePairing & (0x0FU)) << 4U) ); + _d[2] |= (uint8_t) ( (_m->VAU_WChF_Req & (0x01U)) | ((_m->VAU_BLE_FL_Door_Req & (0x03U)) << 1U) | ((_m->VAU_BLE_FR_Door_Req & (0x03U)) << 3U) | ((_m->VAU_BLE_RL_Door_Req & (0x03U)) << 5U) | ((_m->VAU_RS_Req & (0x01U)) << 7U) ); + _d[3] |= (uint8_t) ( (_m->VAU_BLE_RR_Door_Req & (0x03U)) | ((_m->VAU_BLE_CloseWndw_Req & (0x03U)) << 2U) | ((_m->VAU_BLE_TrunkOpn_Req & (0x03U)) << 4U) | ((_m->VAU_BLE_Lock_Req & (0x03U)) << 6U) ); + _d[4] |= (uint8_t) ( (_m->VAU_BLE_RS_Req & (0x01U)) | ((_m->VAU_Device_ID & (0x0FU)) << 1U) ); + + *_len = (uint8_t) VAU2_Msg2_DLC; + *_ide = (uint8_t) VAU2_Msg2_IDE; + return VAU2_Msg2_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_DMS_01_candb(BCM_DMS_01_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->DrivingMode_Sig = (uint8_t) ( (_d[0] & (0x0FU)) ); + _m->DMS_HDC_Req = (uint8_t) ( ((_d[0] >> 4U) & (0x01U)) ); + _m->UpwardPosReq = (uint8_t) ( ((_d[0] >> 5U) & (0x01U)) ); + _m->DownwardPosReq = (uint8_t) ( ((_d[0] >> 6U) & (0x01U)) ); + _m->DMS_ServiceMode = (uint8_t) ( ((_d[0] >> 7U) & (0x01U)) ); + _m->BCM_DMS_01_RC = (uint8_t) ( (_d[1] & (0x0FU)) ); + _m->BCM_DMS_01_CS = (uint8_t) ( (_d[2] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < BCM_DMS_01_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_BCM_DMS_01_candb(&_m->mon1, BCM_DMS_01_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return BCM_DMS_01_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_BCM_DMS_01_candb(BCM_DMS_01_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_DMS_01_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->DrivingMode_Sig & (0x0FU)) | ((_m->DMS_HDC_Req & (0x01U)) << 4U) | ((_m->UpwardPosReq & (0x01U)) << 5U) | ((_m->DownwardPosReq & (0x01U)) << 6U) | ((_m->DMS_ServiceMode & (0x01U)) << 7U) ); + cframe->Data[1] |= (uint8_t) ( (_m->BCM_DMS_01_RC & (0x0FU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->BCM_DMS_01_CS & (0xFFU)) ); + + cframe->MsgId = (uint32_t) BCM_DMS_01_CANID; + cframe->DLC = (uint8_t) BCM_DMS_01_DLC; + cframe->IDE = (uint8_t) BCM_DMS_01_IDE; + return BCM_DMS_01_CANID; +} + +#else + +uint32_t Pack_BCM_DMS_01_candb(BCM_DMS_01_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_DMS_01_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->DrivingMode_Sig & (0x0FU)) | ((_m->DMS_HDC_Req & (0x01U)) << 4U) | ((_m->UpwardPosReq & (0x01U)) << 5U) | ((_m->DownwardPosReq & (0x01U)) << 6U) | ((_m->DMS_ServiceMode & (0x01U)) << 7U) ); + _d[1] |= (uint8_t) ( (_m->BCM_DMS_01_RC & (0x0FU)) ); + _d[2] |= (uint8_t) ( (_m->BCM_DMS_01_CS & (0xFFU)) ); + + *_len = (uint8_t) BCM_DMS_01_DLC; + *_ide = (uint8_t) BCM_DMS_01_IDE; + return BCM_DMS_01_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_LB_pSilCU_State_candb(LB_pSilCU_State_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->LB_pSilCU_Module_Stat = (uint8_t) ( (_d[0] & (0x0FU)) ); + _m->LB_pSilCU_ModuleTemperature_Val = (int8_t) __ext_sig__(( ((_d[1] & (0x07U)) << 4U) | ((_d[0] >> 4U) & (0x0FU)) ), 7); + _m->LB_pSilCU_reserved1 = (int8_t) __ext_sig__(( ((_d[1] >> 3U) & (0x1FU)) ), 5); + _m->LB_pSilCU_reserved2 = (int8_t) __ext_sig__(( (_d[2] & (0xFFU)) ), 8); + _m->LB_pSilCU_reserved3 = (int8_t) __ext_sig__(( (_d[3] & (0xFFU)) ), 8); + _m->LB_pSilCU_reserved4 = (int8_t) __ext_sig__(( (_d[4] & (0xFFU)) ), 8); + _m->LB_pSilCU_reserved5 = (int8_t) __ext_sig__(( (_d[5] & (0xFFU)) ), 8); + _m->LB_pSilCU_reserved6 = (int8_t) __ext_sig__(( (_d[6] & (0xFFU)) ), 8); + _m->LB_pSilCU_reserved7 = (int8_t) __ext_sig__(( (_d[7] & (0xFFU)) ), 8); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < LB_pSilCU_State_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_LB_pSilCU_State_candb(&_m->mon1, LB_pSilCU_State_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return LB_pSilCU_State_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_LB_pSilCU_State_candb(LB_pSilCU_State_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(LB_pSilCU_State_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->LB_pSilCU_Module_Stat & (0x0FU)) | ((_m->LB_pSilCU_ModuleTemperature_Val & (0x0FU)) << 4U) ); + cframe->Data[1] |= (uint8_t) ( ((_m->LB_pSilCU_ModuleTemperature_Val >> 4U) & (0x07U)) | ((_m->LB_pSilCU_reserved1 & (0x1FU)) << 3U) ); + cframe->Data[2] |= (uint8_t) ( (_m->LB_pSilCU_reserved2 & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->LB_pSilCU_reserved3 & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->LB_pSilCU_reserved4 & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->LB_pSilCU_reserved5 & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->LB_pSilCU_reserved6 & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->LB_pSilCU_reserved7 & (0xFFU)) ); + + cframe->MsgId = (uint32_t) LB_pSilCU_State_CANID; + cframe->DLC = (uint8_t) LB_pSilCU_State_DLC; + cframe->IDE = (uint8_t) LB_pSilCU_State_IDE; + return LB_pSilCU_State_CANID; +} + +#else + +uint32_t Pack_LB_pSilCU_State_candb(LB_pSilCU_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(LB_pSilCU_State_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->LB_pSilCU_Module_Stat & (0x0FU)) | ((_m->LB_pSilCU_ModuleTemperature_Val & (0x0FU)) << 4U) ); + _d[1] |= (uint8_t) ( ((_m->LB_pSilCU_ModuleTemperature_Val >> 4U) & (0x07U)) | ((_m->LB_pSilCU_reserved1 & (0x1FU)) << 3U) ); + _d[2] |= (uint8_t) ( (_m->LB_pSilCU_reserved2 & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->LB_pSilCU_reserved3 & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->LB_pSilCU_reserved4 & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->LB_pSilCU_reserved5 & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->LB_pSilCU_reserved6 & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->LB_pSilCU_reserved7 & (0xFFU)) ); + + *_len = (uint8_t) LB_pSilCU_State_DLC; + *_ide = (uint8_t) LB_pSilCU_State_IDE; + return LB_pSilCU_State_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_RB_pSilCU_State_candb(RB_pSilCU_State_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->RB_pSilCU_Module_Stat = (int8_t) __ext_sig__(( (_d[0] & (0x0FU)) ), 4); + _m->RB_pSilCU_ModuleTemperature_Val = (int8_t) __ext_sig__(( ((_d[1] & (0x07U)) << 4U) | ((_d[0] >> 4U) & (0x0FU)) ), 7); + _m->RB_pSilCU_reserved1 = (int8_t) __ext_sig__(( ((_d[1] >> 3U) & (0x1FU)) ), 5); + _m->RB_pSilCU_reserved2 = (int8_t) __ext_sig__(( (_d[2] & (0xFFU)) ), 8); + _m->RB_pSilCU_reserved3 = (int8_t) __ext_sig__(( (_d[3] & (0xFFU)) ), 8); + _m->RB_pSilCU_reserved4 = (int8_t) __ext_sig__(( (_d[4] & (0xFFU)) ), 8); + _m->RB_pSilCU_reserved5 = (int8_t) __ext_sig__(( (_d[5] & (0xFFU)) ), 8); + _m->RB_pSilCU_reserved6 = (int8_t) __ext_sig__(( (_d[6] & (0xFFU)) ), 8); + _m->RB_pSilCU_reserved7 = (int8_t) __ext_sig__(( (_d[7] & (0xFFU)) ), 8); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < RB_pSilCU_State_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_RB_pSilCU_State_candb(&_m->mon1, RB_pSilCU_State_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return RB_pSilCU_State_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_RB_pSilCU_State_candb(RB_pSilCU_State_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(RB_pSilCU_State_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->RB_pSilCU_Module_Stat & (0x0FU)) | ((_m->RB_pSilCU_ModuleTemperature_Val & (0x0FU)) << 4U) ); + cframe->Data[1] |= (uint8_t) ( ((_m->RB_pSilCU_ModuleTemperature_Val >> 4U) & (0x07U)) | ((_m->RB_pSilCU_reserved1 & (0x1FU)) << 3U) ); + cframe->Data[2] |= (uint8_t) ( (_m->RB_pSilCU_reserved2 & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->RB_pSilCU_reserved3 & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->RB_pSilCU_reserved4 & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->RB_pSilCU_reserved5 & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->RB_pSilCU_reserved6 & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->RB_pSilCU_reserved7 & (0xFFU)) ); + + cframe->MsgId = (uint32_t) RB_pSilCU_State_CANID; + cframe->DLC = (uint8_t) RB_pSilCU_State_DLC; + cframe->IDE = (uint8_t) RB_pSilCU_State_IDE; + return RB_pSilCU_State_CANID; +} + +#else + +uint32_t Pack_RB_pSilCU_State_candb(RB_pSilCU_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(RB_pSilCU_State_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->RB_pSilCU_Module_Stat & (0x0FU)) | ((_m->RB_pSilCU_ModuleTemperature_Val & (0x0FU)) << 4U) ); + _d[1] |= (uint8_t) ( ((_m->RB_pSilCU_ModuleTemperature_Val >> 4U) & (0x07U)) | ((_m->RB_pSilCU_reserved1 & (0x1FU)) << 3U) ); + _d[2] |= (uint8_t) ( (_m->RB_pSilCU_reserved2 & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->RB_pSilCU_reserved3 & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->RB_pSilCU_reserved4 & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->RB_pSilCU_reserved5 & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->RB_pSilCU_reserved6 & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->RB_pSilCU_reserved7 & (0xFFU)) ); + + *_len = (uint8_t) RB_pSilCU_State_DLC; + *_ide = (uint8_t) RB_pSilCU_State_IDE; + return RB_pSilCU_State_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_HVC_CCU_Status_Msg_candb(HVC_CCU_Status_Msg_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->HVC_eCompActSpeed_Val_ro = (uint8_t) ( (_d[0] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->HVC_eCompActSpeed_Val_phys = (uint16_t) CANDB_HVC_eCompActSpeed_Val_ro_fromS(_m->HVC_eCompActSpeed_Val_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->HVC_eComp_Stat = (uint8_t) ( (_d[1] & (0x07U)) ); + _m->HVC_CCU_Status_RC = (uint8_t) ( ((_d[1] >> 4U) & (0x0FU)) ); + _m->HVC_CCU_Status_CS = (uint8_t) ( (_d[2] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < HVC_CCU_Status_Msg_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_HVC_CCU_Status_Msg_candb(&_m->mon1, HVC_CCU_Status_Msg_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return HVC_CCU_Status_Msg_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_HVC_CCU_Status_Msg_candb(HVC_CCU_Status_Msg_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(HVC_CCU_Status_Msg_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->HVC_eCompActSpeed_Val_ro = (uint8_t) CANDB_HVC_eCompActSpeed_Val_ro_toS(_m->HVC_eCompActSpeed_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->HVC_eCompActSpeed_Val_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->HVC_eComp_Stat & (0x07U)) | ((_m->HVC_CCU_Status_RC & (0x0FU)) << 4U) ); + cframe->Data[2] |= (uint8_t) ( (_m->HVC_CCU_Status_CS & (0xFFU)) ); + + cframe->MsgId = (uint32_t) HVC_CCU_Status_Msg_CANID; + cframe->DLC = (uint8_t) HVC_CCU_Status_Msg_DLC; + cframe->IDE = (uint8_t) HVC_CCU_Status_Msg_IDE; + return HVC_CCU_Status_Msg_CANID; +} + +#else + +uint32_t Pack_HVC_CCU_Status_Msg_candb(HVC_CCU_Status_Msg_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(HVC_CCU_Status_Msg_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->HVC_eCompActSpeed_Val_ro = (uint8_t) CANDB_HVC_eCompActSpeed_Val_ro_toS(_m->HVC_eCompActSpeed_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->HVC_eCompActSpeed_Val_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( (_m->HVC_eComp_Stat & (0x07U)) | ((_m->HVC_CCU_Status_RC & (0x0FU)) << 4U) ); + _d[2] |= (uint8_t) ( (_m->HVC_CCU_Status_CS & (0xFFU)) ); + + *_len = (uint8_t) HVC_CCU_Status_Msg_DLC; + *_ide = (uint8_t) HVC_CCU_Status_Msg_IDE; + return HVC_CCU_Status_Msg_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_ATS_Status_candb(ATS_Status_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->ATS_Err_Stat = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->ATS_AutoHoldBtn_Stat = (uint8_t) ( ((_d[0] >> 1U) & (0x03U)) ); + _m->ATS_EPBBtn_Req = (uint8_t) ( ((_d[0] >> 3U) & (0x03U)) ); + _m->ATS_GearModeBtn_Req = (uint8_t) ( ((_d[0] >> 5U) & (0x07U)) ); + _m->ATS_Status_RC = (uint8_t) ( (_d[1] & (0x0FU)) ); + _m->ATS_DriveModeBtn_Stat = (uint8_t) ( ((_d[1] >> 4U) & (0x03U)) ); + _m->ATS_Status_CS = (uint8_t) ( (_d[2] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < ATS_Status_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_ATS_Status_candb(&_m->mon1, ATS_Status_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return ATS_Status_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_ATS_Status_candb(ATS_Status_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(ATS_Status_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->ATS_Err_Stat & (0x01U)) | ((_m->ATS_AutoHoldBtn_Stat & (0x03U)) << 1U) | ((_m->ATS_EPBBtn_Req & (0x03U)) << 3U) | ((_m->ATS_GearModeBtn_Req & (0x07U)) << 5U) ); + cframe->Data[1] |= (uint8_t) ( (_m->ATS_Status_RC & (0x0FU)) | ((_m->ATS_DriveModeBtn_Stat & (0x03U)) << 4U) ); + cframe->Data[2] |= (uint8_t) ( (_m->ATS_Status_CS & (0xFFU)) ); + + cframe->MsgId = (uint32_t) ATS_Status_CANID; + cframe->DLC = (uint8_t) ATS_Status_DLC; + cframe->IDE = (uint8_t) ATS_Status_IDE; + return ATS_Status_CANID; +} + +#else + +uint32_t Pack_ATS_Status_candb(ATS_Status_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(ATS_Status_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->ATS_Err_Stat & (0x01U)) | ((_m->ATS_AutoHoldBtn_Stat & (0x03U)) << 1U) | ((_m->ATS_EPBBtn_Req & (0x03U)) << 3U) | ((_m->ATS_GearModeBtn_Req & (0x07U)) << 5U) ); + _d[1] |= (uint8_t) ( (_m->ATS_Status_RC & (0x0FU)) | ((_m->ATS_DriveModeBtn_Stat & (0x03U)) << 4U) ); + _d[2] |= (uint8_t) ( (_m->ATS_Status_CS & (0xFFU)) ); + + *_len = (uint8_t) ATS_Status_DLC; + *_ide = (uint8_t) ATS_Status_IDE; + return ATS_Status_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_VEH_STATE_candb(BCM_VEH_STATE_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->BCM_T15_Stat = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->BCM_T30d_Stat = (uint8_t) ( ((_d[0] >> 1U) & (0x01U)) ); + _m->BCM_T30i_Stat = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + _m->BCM_T15h_Stat = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + _m->BCM_SPV_Feature_Stat = (uint8_t) ( ((_d[0] >> 5U) & (0x01U)) ); + _m->StealthModeEn = (uint8_t) ( ((_d[0] >> 6U) & (0x01U)) ); + _m->BCM_VehicleType_Stat = (uint8_t) ( ((_d[0] >> 7U) & (0x01U)) ); + _m->BCM_VehicleBody_Stat = (uint8_t) ( (_d[1] & (0x0FU)) ); + _m->BCM_ADASTerm_Stat = (uint8_t) ( ((_d[1] >> 4U) & (0x01U)) ); + _m->BCM_CCTerm_Stat = (uint8_t) ( ((_d[1] >> 5U) & (0x01U)) ); + _m->BCM_T30i_DisableWarning = (uint8_t) ( ((_d[1] >> 6U) & (0x01U)) ); + _m->BCM_LightBCM_Stat = (uint8_t) ( ((_d[1] >> 7U) & (0x01U)) ); + _m->HUD_IntensityRequest = (uint8_t) ( (_d[2] & (0xFFU)) ); + _m->BCM_T30d_DisableWarning = (uint8_t) ( (_d[3] & (0x01U)) ); + _m->BCM_Light_Stat = (uint8_t) ( ((_d[3] >> 1U) & (0x01U)) ); + _m->BCM_IndFadingTime_Req_ro = (uint8_t) ( ((_d[3] >> 2U) & (0x1FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_IndFadingTime_Req_phys = (sigfloat_t)(CANDB_BCM_IndFadingTime_Req_ro_fromS(_m->BCM_IndFadingTime_Req_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_CCTermDisableWarning = (uint8_t) ( ((_d[3] >> 7U) & (0x01U)) ); + _m->BCM_PreheatFunction_Stat = (uint8_t) ( (_d[4] & (0x03U)) ); + _m->BCM_VehiclePowertrain_Stat = (uint8_t) ( ((_d[4] >> 2U) & (0x03U)) ); + _m->BCM_SwBackIntens_Val_ro = (uint8_t) ( (_d[5] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_SwBackIntens_Val_phys = (sigfloat_t)(CANDB_BCM_SwBackIntens_Val_ro_fromS(_m->BCM_SwBackIntens_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_VehicleMode_Stat = (uint8_t) ( (_d[6] & (0x0FU)) ); + _m->BCM_SwIndIntens_Stat = (uint8_t) ( ((_d[6] >> 4U) & (0x01U)) ); + _m->BCM_Vehicle_DrvMode = (uint8_t) ( ((_d[6] >> 5U) & (0x07U)) ); + _m->BCM_LVBatteryVoltage_ro = (uint8_t) ( (_d[7] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_LVBatteryVoltage_phys = (sigfloat_t)(CANDB_BCM_LVBatteryVoltage_ro_fromS(_m->BCM_LVBatteryVoltage_ro)); +#endif // CANDB_USE_SIGFLOAT + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < BCM_VEH_STATE_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_BCM_VEH_STATE_candb(&_m->mon1, BCM_VEH_STATE_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return BCM_VEH_STATE_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_BCM_VEH_STATE_candb(BCM_VEH_STATE_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_VEH_STATE_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_IndFadingTime_Req_ro = (uint8_t) CANDB_BCM_IndFadingTime_Req_ro_toS(_m->BCM_IndFadingTime_Req_phys); + _m->BCM_SwBackIntens_Val_ro = (uint8_t) CANDB_BCM_SwBackIntens_Val_ro_toS(_m->BCM_SwBackIntens_Val_phys); + _m->BCM_LVBatteryVoltage_ro = (uint8_t) CANDB_BCM_LVBatteryVoltage_ro_toS(_m->BCM_LVBatteryVoltage_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->BCM_T15_Stat & (0x01U)) | ((_m->BCM_T30d_Stat & (0x01U)) << 1U) | ((_m->BCM_T30i_Stat & (0x01U)) << 2U) | ((_m->BCM_T15h_Stat & (0x01U)) << 3U) | ((_m->BCM_SPV_Feature_Stat & (0x01U)) << 5U) | ((_m->StealthModeEn & (0x01U)) << 6U) | ((_m->BCM_VehicleType_Stat & (0x01U)) << 7U) ); + cframe->Data[1] |= (uint8_t) ( (_m->BCM_VehicleBody_Stat & (0x0FU)) | ((_m->BCM_ADASTerm_Stat & (0x01U)) << 4U) | ((_m->BCM_CCTerm_Stat & (0x01U)) << 5U) | ((_m->BCM_T30i_DisableWarning & (0x01U)) << 6U) | ((_m->BCM_LightBCM_Stat & (0x01U)) << 7U) ); + cframe->Data[2] |= (uint8_t) ( (_m->HUD_IntensityRequest & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->BCM_T30d_DisableWarning & (0x01U)) | ((_m->BCM_Light_Stat & (0x01U)) << 1U) | ((_m->BCM_IndFadingTime_Req_ro & (0x1FU)) << 2U) | ((_m->BCM_CCTermDisableWarning & (0x01U)) << 7U) ); + cframe->Data[4] |= (uint8_t) ( (_m->BCM_PreheatFunction_Stat & (0x03U)) | ((_m->BCM_VehiclePowertrain_Stat & (0x03U)) << 2U) ); + cframe->Data[5] |= (uint8_t) ( (_m->BCM_SwBackIntens_Val_ro & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->BCM_VehicleMode_Stat & (0x0FU)) | ((_m->BCM_SwIndIntens_Stat & (0x01U)) << 4U) | ((_m->BCM_Vehicle_DrvMode & (0x07U)) << 5U) ); + cframe->Data[7] |= (uint8_t) ( (_m->BCM_LVBatteryVoltage_ro & (0xFFU)) ); + + cframe->MsgId = (uint32_t) BCM_VEH_STATE_CANID; + cframe->DLC = (uint8_t) BCM_VEH_STATE_DLC; + cframe->IDE = (uint8_t) BCM_VEH_STATE_IDE; + return BCM_VEH_STATE_CANID; +} + +#else + +uint32_t Pack_BCM_VEH_STATE_candb(BCM_VEH_STATE_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_VEH_STATE_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_IndFadingTime_Req_ro = (uint8_t) CANDB_BCM_IndFadingTime_Req_ro_toS(_m->BCM_IndFadingTime_Req_phys); + _m->BCM_SwBackIntens_Val_ro = (uint8_t) CANDB_BCM_SwBackIntens_Val_ro_toS(_m->BCM_SwBackIntens_Val_phys); + _m->BCM_LVBatteryVoltage_ro = (uint8_t) CANDB_BCM_LVBatteryVoltage_ro_toS(_m->BCM_LVBatteryVoltage_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->BCM_T15_Stat & (0x01U)) | ((_m->BCM_T30d_Stat & (0x01U)) << 1U) | ((_m->BCM_T30i_Stat & (0x01U)) << 2U) | ((_m->BCM_T15h_Stat & (0x01U)) << 3U) | ((_m->BCM_SPV_Feature_Stat & (0x01U)) << 5U) | ((_m->StealthModeEn & (0x01U)) << 6U) | ((_m->BCM_VehicleType_Stat & (0x01U)) << 7U) ); + _d[1] |= (uint8_t) ( (_m->BCM_VehicleBody_Stat & (0x0FU)) | ((_m->BCM_ADASTerm_Stat & (0x01U)) << 4U) | ((_m->BCM_CCTerm_Stat & (0x01U)) << 5U) | ((_m->BCM_T30i_DisableWarning & (0x01U)) << 6U) | ((_m->BCM_LightBCM_Stat & (0x01U)) << 7U) ); + _d[2] |= (uint8_t) ( (_m->HUD_IntensityRequest & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->BCM_T30d_DisableWarning & (0x01U)) | ((_m->BCM_Light_Stat & (0x01U)) << 1U) | ((_m->BCM_IndFadingTime_Req_ro & (0x1FU)) << 2U) | ((_m->BCM_CCTermDisableWarning & (0x01U)) << 7U) ); + _d[4] |= (uint8_t) ( (_m->BCM_PreheatFunction_Stat & (0x03U)) | ((_m->BCM_VehiclePowertrain_Stat & (0x03U)) << 2U) ); + _d[5] |= (uint8_t) ( (_m->BCM_SwBackIntens_Val_ro & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->BCM_VehicleMode_Stat & (0x0FU)) | ((_m->BCM_SwIndIntens_Stat & (0x01U)) << 4U) | ((_m->BCM_Vehicle_DrvMode & (0x07U)) << 5U) ); + _d[7] |= (uint8_t) ( (_m->BCM_LVBatteryVoltage_ro & (0xFFU)) ); + + *_len = (uint8_t) BCM_VEH_STATE_DLC; + *_ide = (uint8_t) BCM_VEH_STATE_IDE; + return BCM_VEH_STATE_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_Veh_State2_candb(BCM_Veh_State2_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->BCM_MAS_Activation_Req = (uint8_t) ( (_d[0] & (0x03U)) ); + _m->BCM_HeadUpDispSw_Stat = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + _m->BCM_FootrestRL_Stat = (uint8_t) ( ((_d[0] >> 3U) & (0x03U)) ); + _m->BCM_FootrestRR_Stat = (uint8_t) ( ((_d[0] >> 5U) & (0x03U)) ); + _m->BCM_FootrestRLWarning_Stat = (uint8_t) ( ((_d[0] >> 7U) & (0x01U)) ); + _m->BCM_AmbientTempHMI_ro = (uint8_t) ( (_d[1] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_AmbientTempHMI_phys = (sigfloat_t)(CANDB_BCM_AmbientTempHMI_ro_fromS(_m->BCM_AmbientTempHMI_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_GovernmentComSw_Stat = (uint8_t) ( (_d[2] & (0x01U)) ); + _m->BCM_RearWindowHeatingLED = (uint8_t) ( ((_d[2] >> 1U) & (0x01U)) ); + _m->BCM_FootrestRRWarning_Stat = (uint8_t) ( ((_d[2] >> 2U) & (0x01U)) ); + _m->BCM_GovernmentHandset_Stat = (uint8_t) ( ((_d[2] >> 3U) & (0x01U)) ); + _m->BCM_EasyExitSMRL_Stat = (uint8_t) ( ((_d[2] >> 4U) & (0x01U)) ); + _m->BCM_EasyExitSMRR_Stat = (uint8_t) ( ((_d[2] >> 5U) & (0x01U)) ); + _m->BCM_EasyExitSMFR_Stat = (uint8_t) ( ((_d[2] >> 6U) & (0x01U)) ); + _m->BCM_EasyExitSMFL_Stat = (uint8_t) ( ((_d[2] >> 7U) & (0x01U)) ); + _m->BCM_LccBtn_Stat = (uint8_t) ( (_d[3] & (0x01U)) ); + _m->BCM_LdwBtn_Stat = (uint8_t) ( ((_d[3] >> 1U) & (0x01U)) ); + _m->BCM_AdasSensClear_Stat = (uint8_t) ( ((_d[3] >> 2U) & (0x01U)) ); + _m->BCM_T15h_Deactivation_Req = (uint8_t) ( ((_d[3] >> 3U) & (0x01U)) ); + _m->BCM_RemoteStart_Stat = (uint8_t) ( ((_d[3] >> 4U) & (0x03U)) ); + _m->BCM_AntiTheft_Stat = (uint8_t) ( ((_d[3] >> 6U) & (0x01U)) ); + _m->BCM_PanoramicViewLed_Cmd = (uint8_t) ( ((_d[3] >> 7U) & (0x01U)) ); + _m->BCM_ElcromeMirror_Req_ro = (uint8_t) ( (_d[4] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_ElcromeMirror_Req_phys = (sigfloat_t)(CANDB_BCM_ElcromeMirror_Req_ro_fromS(_m->BCM_ElcromeMirror_Req_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_AdasSensWSHeat_Req = (uint8_t) ( (_d[5] & (0x03U)) ); + _m->BCM_RearWasherVlv_Req = (uint8_t) ( ((_d[5] >> 5U) & (0x01U)) ); + _m->BCM_RoofControl_Req = (uint8_t) ( ((_d[5] >> 6U) & (0x03U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < BCM_Veh_State2_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_BCM_Veh_State2_candb(&_m->mon1, BCM_Veh_State2_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return BCM_Veh_State2_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_BCM_Veh_State2_candb(BCM_Veh_State2_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_Veh_State2_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_AmbientTempHMI_ro = (uint8_t) CANDB_BCM_AmbientTempHMI_ro_toS(_m->BCM_AmbientTempHMI_phys); + _m->BCM_ElcromeMirror_Req_ro = (uint8_t) CANDB_BCM_ElcromeMirror_Req_ro_toS(_m->BCM_ElcromeMirror_Req_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->BCM_MAS_Activation_Req & (0x03U)) | ((_m->BCM_HeadUpDispSw_Stat & (0x01U)) << 2U) | ((_m->BCM_FootrestRL_Stat & (0x03U)) << 3U) | ((_m->BCM_FootrestRR_Stat & (0x03U)) << 5U) | ((_m->BCM_FootrestRLWarning_Stat & (0x01U)) << 7U) ); + cframe->Data[1] |= (uint8_t) ( (_m->BCM_AmbientTempHMI_ro & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->BCM_GovernmentComSw_Stat & (0x01U)) | ((_m->BCM_RearWindowHeatingLED & (0x01U)) << 1U) | ((_m->BCM_FootrestRRWarning_Stat & (0x01U)) << 2U) | ((_m->BCM_GovernmentHandset_Stat & (0x01U)) << 3U) | ((_m->BCM_EasyExitSMRL_Stat & (0x01U)) << 4U) | ((_m->BCM_EasyExitSMRR_Stat & (0x01U)) << 5U) | ((_m->BCM_EasyExitSMFR_Stat & (0x01U)) << 6U) | ((_m->BCM_EasyExitSMFL_Stat & (0x01U)) << 7U) ); + cframe->Data[3] |= (uint8_t) ( (_m->BCM_LccBtn_Stat & (0x01U)) | ((_m->BCM_LdwBtn_Stat & (0x01U)) << 1U) | ((_m->BCM_AdasSensClear_Stat & (0x01U)) << 2U) | ((_m->BCM_T15h_Deactivation_Req & (0x01U)) << 3U) | ((_m->BCM_RemoteStart_Stat & (0x03U)) << 4U) | ((_m->BCM_AntiTheft_Stat & (0x01U)) << 6U) | ((_m->BCM_PanoramicViewLed_Cmd & (0x01U)) << 7U) ); + cframe->Data[4] |= (uint8_t) ( (_m->BCM_ElcromeMirror_Req_ro & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->BCM_AdasSensWSHeat_Req & (0x03U)) | ((_m->BCM_RearWasherVlv_Req & (0x01U)) << 5U) | ((_m->BCM_RoofControl_Req & (0x03U)) << 6U) ); + + cframe->MsgId = (uint32_t) BCM_Veh_State2_CANID; + cframe->DLC = (uint8_t) BCM_Veh_State2_DLC; + cframe->IDE = (uint8_t) BCM_Veh_State2_IDE; + return BCM_Veh_State2_CANID; +} + +#else + +uint32_t Pack_BCM_Veh_State2_candb(BCM_Veh_State2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_Veh_State2_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_AmbientTempHMI_ro = (uint8_t) CANDB_BCM_AmbientTempHMI_ro_toS(_m->BCM_AmbientTempHMI_phys); + _m->BCM_ElcromeMirror_Req_ro = (uint8_t) CANDB_BCM_ElcromeMirror_Req_ro_toS(_m->BCM_ElcromeMirror_Req_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->BCM_MAS_Activation_Req & (0x03U)) | ((_m->BCM_HeadUpDispSw_Stat & (0x01U)) << 2U) | ((_m->BCM_FootrestRL_Stat & (0x03U)) << 3U) | ((_m->BCM_FootrestRR_Stat & (0x03U)) << 5U) | ((_m->BCM_FootrestRLWarning_Stat & (0x01U)) << 7U) ); + _d[1] |= (uint8_t) ( (_m->BCM_AmbientTempHMI_ro & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->BCM_GovernmentComSw_Stat & (0x01U)) | ((_m->BCM_RearWindowHeatingLED & (0x01U)) << 1U) | ((_m->BCM_FootrestRRWarning_Stat & (0x01U)) << 2U) | ((_m->BCM_GovernmentHandset_Stat & (0x01U)) << 3U) | ((_m->BCM_EasyExitSMRL_Stat & (0x01U)) << 4U) | ((_m->BCM_EasyExitSMRR_Stat & (0x01U)) << 5U) | ((_m->BCM_EasyExitSMFR_Stat & (0x01U)) << 6U) | ((_m->BCM_EasyExitSMFL_Stat & (0x01U)) << 7U) ); + _d[3] |= (uint8_t) ( (_m->BCM_LccBtn_Stat & (0x01U)) | ((_m->BCM_LdwBtn_Stat & (0x01U)) << 1U) | ((_m->BCM_AdasSensClear_Stat & (0x01U)) << 2U) | ((_m->BCM_T15h_Deactivation_Req & (0x01U)) << 3U) | ((_m->BCM_RemoteStart_Stat & (0x03U)) << 4U) | ((_m->BCM_AntiTheft_Stat & (0x01U)) << 6U) | ((_m->BCM_PanoramicViewLed_Cmd & (0x01U)) << 7U) ); + _d[4] |= (uint8_t) ( (_m->BCM_ElcromeMirror_Req_ro & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->BCM_AdasSensWSHeat_Req & (0x03U)) | ((_m->BCM_RearWasherVlv_Req & (0x01U)) << 5U) | ((_m->BCM_RoofControl_Req & (0x03U)) << 6U) ); + + *_len = (uint8_t) BCM_Veh_State2_DLC; + *_ide = (uint8_t) BCM_Veh_State2_IDE; + return BCM_Veh_State2_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_ALS_Light_Front_candb(BCM_ALS_Light_Front_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->BCM_ALSZoneSelectFront_Stat = (uint8_t) ( (_d[0] & (0x07U)) ); + _m->BCM_ALSFadingTimeFront_Val_ro = (uint8_t) ( (_d[1] & (0x3FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_ALSFadingTimeFront_Val_phys = (sigfloat_t)(CANDB_BCM_ALSFadingTimeFront_Val_ro_fromS(_m->BCM_ALSFadingTimeFront_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_ALSFadingFront_Req = (uint8_t) ( ((_d[1] >> 6U) & (0x01U)) ); + _m->BCM_ALSLightStateFront_Req = (uint8_t) ( ((_d[1] >> 7U) & (0x01U)) ); + _m->BCM_ALSIntensRedFront_Val = (uint8_t) ( (_d[2] & (0xFFU)) ); + _m->BCM_ALSIntensGreenFront_Val = (uint8_t) ( (_d[3] & (0xFFU)) ); + _m->BCM_ALSIntensBlueFront_Val = (uint8_t) ( (_d[4] & (0xFFU)) ); + _m->BCM_ALSAmbIntensFront_Val_ro = (uint8_t) ( (_d[5] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_ALSAmbIntensFront_Val_phys = (sigfloat_t)(CANDB_BCM_ALSAmbIntensFront_Val_ro_fromS(_m->BCM_ALSAmbIntensFront_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < BCM_ALS_Light_Front_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_BCM_ALS_Light_Front_candb(&_m->mon1, BCM_ALS_Light_Front_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return BCM_ALS_Light_Front_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_BCM_ALS_Light_Front_candb(BCM_ALS_Light_Front_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_ALS_Light_Front_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_ALSFadingTimeFront_Val_ro = (uint8_t) CANDB_BCM_ALSFadingTimeFront_Val_ro_toS(_m->BCM_ALSFadingTimeFront_Val_phys); + _m->BCM_ALSAmbIntensFront_Val_ro = (uint8_t) CANDB_BCM_ALSAmbIntensFront_Val_ro_toS(_m->BCM_ALSAmbIntensFront_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->BCM_ALSZoneSelectFront_Stat & (0x07U)) ); + cframe->Data[1] |= (uint8_t) ( (_m->BCM_ALSFadingTimeFront_Val_ro & (0x3FU)) | ((_m->BCM_ALSFadingFront_Req & (0x01U)) << 6U) | ((_m->BCM_ALSLightStateFront_Req & (0x01U)) << 7U) ); + cframe->Data[2] |= (uint8_t) ( (_m->BCM_ALSIntensRedFront_Val & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->BCM_ALSIntensGreenFront_Val & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->BCM_ALSIntensBlueFront_Val & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->BCM_ALSAmbIntensFront_Val_ro & (0xFFU)) ); + + cframe->MsgId = (uint32_t) BCM_ALS_Light_Front_CANID; + cframe->DLC = (uint8_t) BCM_ALS_Light_Front_DLC; + cframe->IDE = (uint8_t) BCM_ALS_Light_Front_IDE; + return BCM_ALS_Light_Front_CANID; +} + +#else + +uint32_t Pack_BCM_ALS_Light_Front_candb(BCM_ALS_Light_Front_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_ALS_Light_Front_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_ALSFadingTimeFront_Val_ro = (uint8_t) CANDB_BCM_ALSFadingTimeFront_Val_ro_toS(_m->BCM_ALSFadingTimeFront_Val_phys); + _m->BCM_ALSAmbIntensFront_Val_ro = (uint8_t) CANDB_BCM_ALSAmbIntensFront_Val_ro_toS(_m->BCM_ALSAmbIntensFront_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->BCM_ALSZoneSelectFront_Stat & (0x07U)) ); + _d[1] |= (uint8_t) ( (_m->BCM_ALSFadingTimeFront_Val_ro & (0x3FU)) | ((_m->BCM_ALSFadingFront_Req & (0x01U)) << 6U) | ((_m->BCM_ALSLightStateFront_Req & (0x01U)) << 7U) ); + _d[2] |= (uint8_t) ( (_m->BCM_ALSIntensRedFront_Val & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->BCM_ALSIntensGreenFront_Val & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->BCM_ALSIntensBlueFront_Val & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->BCM_ALSAmbIntensFront_Val_ro & (0xFFU)) ); + + *_len = (uint8_t) BCM_ALS_Light_Front_DLC; + *_ide = (uint8_t) BCM_ALS_Light_Front_IDE; + return BCM_ALS_Light_Front_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_ALS_Light_Rear_candb(BCM_ALS_Light_Rear_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->BCM_ALSZoneSelectRear_Stat = (uint8_t) ( (_d[0] & (0x07U)) ); + _m->BCM_ALSFadingTimeRear_Val_ro = (uint8_t) ( (_d[1] & (0x3FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_ALSFadingTimeRear_Val_phys = (sigfloat_t)(CANDB_BCM_ALSFadingTimeRear_Val_ro_fromS(_m->BCM_ALSFadingTimeRear_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_ALSFadingRear_Req = (uint8_t) ( ((_d[1] >> 6U) & (0x01U)) ); + _m->BCM_ALSLightStateRear_Req = (uint8_t) ( ((_d[1] >> 7U) & (0x01U)) ); + _m->BCM_ALSIntensRedRear_Val = (uint8_t) ( (_d[2] & (0xFFU)) ); + _m->BCM_ALSIntensGreenRear_Val = (uint8_t) ( (_d[3] & (0xFFU)) ); + _m->BCM_ALSIntensBlueRear_Val = (uint8_t) ( (_d[4] & (0xFFU)) ); + _m->BCM_ALSAmbIntensRear_Val_ro = (uint8_t) ( (_d[5] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_ALSAmbIntensRear_Val_phys = (sigfloat_t)(CANDB_BCM_ALSAmbIntensRear_Val_ro_fromS(_m->BCM_ALSAmbIntensRear_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < BCM_ALS_Light_Rear_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_BCM_ALS_Light_Rear_candb(&_m->mon1, BCM_ALS_Light_Rear_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return BCM_ALS_Light_Rear_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_BCM_ALS_Light_Rear_candb(BCM_ALS_Light_Rear_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_ALS_Light_Rear_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_ALSFadingTimeRear_Val_ro = (uint8_t) CANDB_BCM_ALSFadingTimeRear_Val_ro_toS(_m->BCM_ALSFadingTimeRear_Val_phys); + _m->BCM_ALSAmbIntensRear_Val_ro = (uint8_t) CANDB_BCM_ALSAmbIntensRear_Val_ro_toS(_m->BCM_ALSAmbIntensRear_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->BCM_ALSZoneSelectRear_Stat & (0x07U)) ); + cframe->Data[1] |= (uint8_t) ( (_m->BCM_ALSFadingTimeRear_Val_ro & (0x3FU)) | ((_m->BCM_ALSFadingRear_Req & (0x01U)) << 6U) | ((_m->BCM_ALSLightStateRear_Req & (0x01U)) << 7U) ); + cframe->Data[2] |= (uint8_t) ( (_m->BCM_ALSIntensRedRear_Val & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->BCM_ALSIntensGreenRear_Val & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->BCM_ALSIntensBlueRear_Val & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->BCM_ALSAmbIntensRear_Val_ro & (0xFFU)) ); + + cframe->MsgId = (uint32_t) BCM_ALS_Light_Rear_CANID; + cframe->DLC = (uint8_t) BCM_ALS_Light_Rear_DLC; + cframe->IDE = (uint8_t) BCM_ALS_Light_Rear_IDE; + return BCM_ALS_Light_Rear_CANID; +} + +#else + +uint32_t Pack_BCM_ALS_Light_Rear_candb(BCM_ALS_Light_Rear_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_ALS_Light_Rear_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_ALSFadingTimeRear_Val_ro = (uint8_t) CANDB_BCM_ALSFadingTimeRear_Val_ro_toS(_m->BCM_ALSFadingTimeRear_Val_phys); + _m->BCM_ALSAmbIntensRear_Val_ro = (uint8_t) CANDB_BCM_ALSAmbIntensRear_Val_ro_toS(_m->BCM_ALSAmbIntensRear_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->BCM_ALSZoneSelectRear_Stat & (0x07U)) ); + _d[1] |= (uint8_t) ( (_m->BCM_ALSFadingTimeRear_Val_ro & (0x3FU)) | ((_m->BCM_ALSFadingRear_Req & (0x01U)) << 6U) | ((_m->BCM_ALSLightStateRear_Req & (0x01U)) << 7U) ); + _d[2] |= (uint8_t) ( (_m->BCM_ALSIntensRedRear_Val & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->BCM_ALSIntensGreenRear_Val & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->BCM_ALSIntensBlueRear_Val & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->BCM_ALSAmbIntensRear_Val_ro & (0xFFU)) ); + + *_len = (uint8_t) BCM_ALS_Light_Rear_DLC; + *_ide = (uint8_t) BCM_ALS_Light_Rear_IDE; + return BCM_ALS_Light_Rear_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_Rear_Plafond_Light_Data_candb(BCM_Rear_Plafond_Light_Data_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->BCM_PlafondRedColorSetRear_Val = (uint8_t) ( (_d[0] & (0xFFU)) ); + _m->BCM_PlafondGreenColorSetRear_Val = (uint8_t) ( (_d[1] & (0xFFU)) ); + _m->BCM_PlafondBlueColorSetRear_Val = (uint8_t) ( (_d[2] & (0xFFU)) ); + _m->BCM_PlafondRGBIntensityRear_Val_ro = (uint8_t) ( (_d[3] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_PlafondRGBIntensityRear_Val_phys = (sigfloat_t)(CANDB_BCM_PlafondRGBIntensityRear_Val_ro_fromS(_m->BCM_PlafondRGBIntensityRear_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_Plafond_W_IntensityRear_Val_ro = (uint8_t) ( (_d[4] & (0x7FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_Plafond_W_IntensityRear_Val_phys = (sigfloat_t)(CANDB_BCM_Plafond_W_IntensityRear_Val_ro_fromS(_m->BCM_Plafond_W_IntensityRear_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_PlafondRGBStateRear_Req = (uint8_t) ( ((_d[4] >> 7U) & (0x01U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < BCM_Rear_Plafond_Light_Data_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_BCM_Rear_Plafond_Light_Data_candb(&_m->mon1, BCM_Rear_Plafond_Light_Data_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return BCM_Rear_Plafond_Light_Data_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_BCM_Rear_Plafond_Light_Data_candb(BCM_Rear_Plafond_Light_Data_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_Rear_Plafond_Light_Data_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_PlafondRGBIntensityRear_Val_ro = (uint8_t) CANDB_BCM_PlafondRGBIntensityRear_Val_ro_toS(_m->BCM_PlafondRGBIntensityRear_Val_phys); + _m->BCM_Plafond_W_IntensityRear_Val_ro = (uint8_t) CANDB_BCM_Plafond_W_IntensityRear_Val_ro_toS(_m->BCM_Plafond_W_IntensityRear_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->BCM_PlafondRedColorSetRear_Val & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->BCM_PlafondGreenColorSetRear_Val & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->BCM_PlafondBlueColorSetRear_Val & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->BCM_PlafondRGBIntensityRear_Val_ro & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->BCM_Plafond_W_IntensityRear_Val_ro & (0x7FU)) | ((_m->BCM_PlafondRGBStateRear_Req & (0x01U)) << 7U) ); + + cframe->MsgId = (uint32_t) BCM_Rear_Plafond_Light_Data_CANID; + cframe->DLC = (uint8_t) BCM_Rear_Plafond_Light_Data_DLC; + cframe->IDE = (uint8_t) BCM_Rear_Plafond_Light_Data_IDE; + return BCM_Rear_Plafond_Light_Data_CANID; +} + +#else + +uint32_t Pack_BCM_Rear_Plafond_Light_Data_candb(BCM_Rear_Plafond_Light_Data_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_Rear_Plafond_Light_Data_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_PlafondRGBIntensityRear_Val_ro = (uint8_t) CANDB_BCM_PlafondRGBIntensityRear_Val_ro_toS(_m->BCM_PlafondRGBIntensityRear_Val_phys); + _m->BCM_Plafond_W_IntensityRear_Val_ro = (uint8_t) CANDB_BCM_Plafond_W_IntensityRear_Val_ro_toS(_m->BCM_Plafond_W_IntensityRear_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->BCM_PlafondRedColorSetRear_Val & (0xFFU)) ); + _d[1] |= (uint8_t) ( (_m->BCM_PlafondGreenColorSetRear_Val & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->BCM_PlafondBlueColorSetRear_Val & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->BCM_PlafondRGBIntensityRear_Val_ro & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->BCM_Plafond_W_IntensityRear_Val_ro & (0x7FU)) | ((_m->BCM_PlafondRGBStateRear_Req & (0x01U)) << 7U) ); + + *_len = (uint8_t) BCM_Rear_Plafond_Light_Data_DLC; + *_ide = (uint8_t) BCM_Rear_Plafond_Light_Data_IDE; + return BCM_Rear_Plafond_Light_Data_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_EMS_HVC_Req_Msg_candb(EMS_HVC_Req_Msg_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->EMS_eCompHVRequest_Stat = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->EMS_eCompOnPerm = (uint8_t) ( ((_d[0] >> 1U) & (0x01U)) ); + _m->EMS_eCompChiller_Req = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + _m->EMS_eCompHVCurLimit_Val_ro = (uint16_t) ( ((_d[1] & (0x0FU)) << 5U) | ((_d[0] >> 3U) & (0x1FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->EMS_eCompHVCurLimit_Val_phys = (sigfloat_t)(CANDB_EMS_eCompHVCurLimit_Val_ro_fromS(_m->EMS_eCompHVCurLimit_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->EMS_HVC_Req_RC = (uint8_t) ( ((_d[1] >> 4U) & (0x0FU)) ); + _m->EMS_HVC_Req_CS = (uint8_t) ( (_d[2] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < EMS_HVC_Req_Msg_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_EMS_HVC_Req_Msg_candb(&_m->mon1, EMS_HVC_Req_Msg_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return EMS_HVC_Req_Msg_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_EMS_HVC_Req_Msg_candb(EMS_HVC_Req_Msg_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(EMS_HVC_Req_Msg_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->EMS_eCompHVCurLimit_Val_ro = (uint16_t) CANDB_EMS_eCompHVCurLimit_Val_ro_toS(_m->EMS_eCompHVCurLimit_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->EMS_eCompHVRequest_Stat & (0x01U)) | ((_m->EMS_eCompOnPerm & (0x01U)) << 1U) | ((_m->EMS_eCompChiller_Req & (0x01U)) << 2U) | ((_m->EMS_eCompHVCurLimit_Val_ro & (0x1FU)) << 3U) ); + cframe->Data[1] |= (uint8_t) ( ((_m->EMS_eCompHVCurLimit_Val_ro >> 5U) & (0x0FU)) | ((_m->EMS_HVC_Req_RC & (0x0FU)) << 4U) ); + cframe->Data[2] |= (uint8_t) ( (_m->EMS_HVC_Req_CS & (0xFFU)) ); + + cframe->MsgId = (uint32_t) EMS_HVC_Req_Msg_CANID; + cframe->DLC = (uint8_t) EMS_HVC_Req_Msg_DLC; + cframe->IDE = (uint8_t) EMS_HVC_Req_Msg_IDE; + return EMS_HVC_Req_Msg_CANID; +} + +#else + +uint32_t Pack_EMS_HVC_Req_Msg_candb(EMS_HVC_Req_Msg_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(EMS_HVC_Req_Msg_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->EMS_eCompHVCurLimit_Val_ro = (uint16_t) CANDB_EMS_eCompHVCurLimit_Val_ro_toS(_m->EMS_eCompHVCurLimit_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->EMS_eCompHVRequest_Stat & (0x01U)) | ((_m->EMS_eCompOnPerm & (0x01U)) << 1U) | ((_m->EMS_eCompChiller_Req & (0x01U)) << 2U) | ((_m->EMS_eCompHVCurLimit_Val_ro & (0x1FU)) << 3U) ); + _d[1] |= (uint8_t) ( ((_m->EMS_eCompHVCurLimit_Val_ro >> 5U) & (0x0FU)) | ((_m->EMS_HVC_Req_RC & (0x0FU)) << 4U) ); + _d[2] |= (uint8_t) ( (_m->EMS_HVC_Req_CS & (0xFFU)) ); + + *_len = (uint8_t) EMS_HVC_Req_Msg_DLC; + *_ide = (uint8_t) EMS_HVC_Req_Msg_IDE; + return EMS_HVC_Req_Msg_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SAS_Standard_candb(SAS_Standard_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->SAS_Angle_ro = (int16_t) __ext_sig__(( ((_d[1] & (0xFFU)) << 8U) | (_d[0] & (0xFFU)) ), 16); +#ifdef CANDB_USE_SIGFLOAT + _m->SAS_Angle_phys = (sigfloat_t)(CANDB_SAS_Angle_ro_fromS(_m->SAS_Angle_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SAS_Speed_ro = (uint8_t) ( (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SAS_Speed_phys = (uint16_t) CANDB_SAS_Speed_ro_fromS(_m->SAS_Speed_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->SAS_OK_Stat = (uint8_t) ( (_d[3] & (0x01U)) ); + _m->SAS_CAL_Stat = (uint8_t) ( ((_d[3] >> 1U) & (0x01U)) ); + _m->SAS_TRIM_Stat = (uint8_t) ( ((_d[3] >> 2U) & (0x01U)) ); + _m->SAS_SF1_5_Stat = (uint8_t) ( ((_d[3] >> 3U) & (0x1FU)) ); + _m->SAS_Standard_RC = (uint8_t) ( (_d[4] & (0x0FU)) ); + _m->SAS_Standard_CS = (uint8_t) ( ((_d[4] >> 4U) & (0x0FU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < SAS_Standard_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_SAS_Standard_candb(&_m->mon1, SAS_Standard_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return SAS_Standard_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_SAS_Standard_candb(SAS_Standard_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SAS_Standard_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->SAS_Angle_ro = (int16_t) CANDB_SAS_Angle_ro_toS(_m->SAS_Angle_phys); + _m->SAS_Speed_ro = (uint8_t) CANDB_SAS_Speed_ro_toS(_m->SAS_Speed_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->SAS_Angle_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->SAS_Angle_ro >> 8U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->SAS_Speed_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->SAS_OK_Stat & (0x01U)) | ((_m->SAS_CAL_Stat & (0x01U)) << 1U) | ((_m->SAS_TRIM_Stat & (0x01U)) << 2U) | ((_m->SAS_SF1_5_Stat & (0x1FU)) << 3U) ); + cframe->Data[4] |= (uint8_t) ( (_m->SAS_Standard_RC & (0x0FU)) | ((_m->SAS_Standard_CS & (0x0FU)) << 4U) ); + + cframe->MsgId = (uint32_t) SAS_Standard_CANID; + cframe->DLC = (uint8_t) SAS_Standard_DLC; + cframe->IDE = (uint8_t) SAS_Standard_IDE; + return SAS_Standard_CANID; +} + +#else + +uint32_t Pack_SAS_Standard_candb(SAS_Standard_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SAS_Standard_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->SAS_Angle_ro = (int16_t) CANDB_SAS_Angle_ro_toS(_m->SAS_Angle_phys); + _m->SAS_Speed_ro = (uint8_t) CANDB_SAS_Speed_ro_toS(_m->SAS_Speed_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->SAS_Angle_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->SAS_Angle_ro >> 8U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->SAS_Speed_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->SAS_OK_Stat & (0x01U)) | ((_m->SAS_CAL_Stat & (0x01U)) << 1U) | ((_m->SAS_TRIM_Stat & (0x01U)) << 2U) | ((_m->SAS_SF1_5_Stat & (0x1FU)) << 3U) ); + _d[4] |= (uint8_t) ( (_m->SAS_Standard_RC & (0x0FU)) | ((_m->SAS_Standard_CS & (0x0FU)) << 4U) ); + + *_len = (uint8_t) SAS_Standard_DLC; + *_ide = (uint8_t) SAS_Standard_IDE; + return SAS_Standard_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_IC_ABSOLUTE_CLOCK_candb(IC_ABSOLUTE_CLOCK_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->IC_AbsoluteDateAndTime = (uint32_t) ( ((_d[3] & (0xFFU)) << 24U) | ((_d[2] & (0xFFU)) << 16U) | ((_d[1] & (0xFFU)) << 8U) | (_d[0] & (0xFFU)) ); + _m->IC_ABSOLUTE_CLOCK_RC = (uint8_t) ( ((_d[4] >> 4U) & (0x0FU)) ); + _m->IC_ABSOLUTE_CLOCK_CS = (uint8_t) ( (_d[5] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < IC_ABSOLUTE_CLOCK_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_IC_ABSOLUTE_CLOCK_candb(&_m->mon1, IC_ABSOLUTE_CLOCK_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return IC_ABSOLUTE_CLOCK_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_IC_ABSOLUTE_CLOCK_candb(IC_ABSOLUTE_CLOCK_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(IC_ABSOLUTE_CLOCK_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->IC_AbsoluteDateAndTime & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->IC_AbsoluteDateAndTime >> 8U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->IC_AbsoluteDateAndTime >> 16U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->IC_AbsoluteDateAndTime >> 24U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->IC_ABSOLUTE_CLOCK_RC & (0x0FU)) << 4U) ); + cframe->Data[5] |= (uint8_t) ( (_m->IC_ABSOLUTE_CLOCK_CS & (0xFFU)) ); + + cframe->MsgId = (uint32_t) IC_ABSOLUTE_CLOCK_CANID; + cframe->DLC = (uint8_t) IC_ABSOLUTE_CLOCK_DLC; + cframe->IDE = (uint8_t) IC_ABSOLUTE_CLOCK_IDE; + return IC_ABSOLUTE_CLOCK_CANID; +} + +#else + +uint32_t Pack_IC_ABSOLUTE_CLOCK_candb(IC_ABSOLUTE_CLOCK_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(IC_ABSOLUTE_CLOCK_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->IC_AbsoluteDateAndTime & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->IC_AbsoluteDateAndTime >> 8U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->IC_AbsoluteDateAndTime >> 16U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->IC_AbsoluteDateAndTime >> 24U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->IC_ABSOLUTE_CLOCK_RC & (0x0FU)) << 4U) ); + _d[5] |= (uint8_t) ( (_m->IC_ABSOLUTE_CLOCK_CS & (0xFFU)) ); + + *_len = (uint8_t) IC_ABSOLUTE_CLOCK_DLC; + *_ide = (uint8_t) IC_ABSOLUTE_CLOCK_IDE; + return IC_ABSOLUTE_CLOCK_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_Lock_CTR_candb(BCM_Lock_CTR_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->VehicleLockStateReason = (uint8_t) ( (_d[0] & (0x0FU)) ); + _m->BCM_FrontLeftLockCmd = (uint8_t) ( ((_d[0] >> 4U) & (0x07U)) ); + _m->BCM_TrunkLatchRelease_Req = (uint8_t) ( ((_d[0] >> 7U) & (0x01U)) ); + _m->BCM_FrontRightLockCmd = (uint8_t) ( (_d[1] & (0x07U)) ); + _m->PTG_MovementCmd = (uint8_t) ( ((_d[1] >> 3U) & (0x03U)) ); + _m->BCM_RearLeftLockCmd = (uint8_t) ( ((_d[1] >> 5U) & (0x07U)) ); + _m->BCM_RearRightLockCmd = (uint8_t) ( (_d[2] & (0x07U)) ); + _m->BCM_FLDoorClose_Req = (uint8_t) ( ((_d[2] >> 3U) & (0x03U)) ); + _m->PTG_MemorySetRequest = (uint8_t) ( ((_d[2] >> 5U) & (0x03U)) ); + _m->VehicleLockState = (uint8_t) ( ((_d[2] >> 7U) & (0x01U)) ); + _m->BCM_DoorAjarState_FL = (uint8_t) ( (_d[3] & (0x03U)) ); + _m->BCM_DoorAjarState_FR = (uint8_t) ( ((_d[3] >> 2U) & (0x03U)) ); + _m->BCM_DoorAjarState_RL = (uint8_t) ( ((_d[3] >> 4U) & (0x03U)) ); + _m->BCM_DoorAjarState_RR = (uint8_t) ( ((_d[3] >> 6U) & (0x03U)) ); + _m->BCM_VehDoubleLock_Stat = (uint8_t) ( (_d[4] & (0x01U)) ); + _m->BCM_FuelLidUnlock_Req = (uint8_t) ( ((_d[4] >> 1U) & (0x01U)) ); + _m->BCM_HVlid_Stat = (uint8_t) ( ((_d[4] >> 2U) & (0x01U)) ); + _m->BCM_RRDoorClose_Req = (uint8_t) ( ((_d[4] >> 3U) & (0x03U)) ); + _m->BCM_WindowsClose_Cmd = (uint8_t) ( ((_d[4] >> 5U) & (0x01U)) ); + _m->BCM_FRDoorClose_Req = (uint8_t) ( ((_d[4] >> 6U) & (0x03U)) ); + _m->BCM_HoodOpen_Stat = (uint8_t) ( (_d[5] & (0x03U)) ); + _m->BCM_PanicAlertActive = (uint8_t) ( ((_d[5] >> 2U) & (0x01U)) ); + _m->BCM_RLDoorClose_Req = (uint8_t) ( ((_d[5] >> 3U) & (0x03U)) ); + _m->BCM_RearWiperWipe_Req = (uint8_t) ( ((_d[5] >> 5U) & (0x01U)) ); + _m->BCM_AlarmOFF_Stat = (uint8_t) ( ((_d[5] >> 6U) & (0x01U)) ); + _m->BCM_MovementSensOFF_Stat = (uint8_t) ( ((_d[5] >> 7U) & (0x01U)) ); + _m->BCM_DoorMovDis_Stat = (uint8_t) ( (_d[6] & (0x01U)) ); + _m->BCM_Alarm_Req = (uint8_t) ( ((_d[6] >> 1U) & (0x01U)) ); + _m->BCM_Alarm_Reason = (uint8_t) ( ((_d[6] >> 2U) & (0x0FU)) ); + _m->BCM_DoorHandleLight_Req = (uint8_t) ( ((_d[6] >> 6U) & (0x01U)) ); + _m->BCM_WindowsOpen_Req = (uint8_t) ( ((_d[6] >> 7U) & (0x01U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < BCM_Lock_CTR_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_BCM_Lock_CTR_candb(&_m->mon1, BCM_Lock_CTR_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return BCM_Lock_CTR_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_BCM_Lock_CTR_candb(BCM_Lock_CTR_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_Lock_CTR_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->VehicleLockStateReason & (0x0FU)) | ((_m->BCM_FrontLeftLockCmd & (0x07U)) << 4U) | ((_m->BCM_TrunkLatchRelease_Req & (0x01U)) << 7U) ); + cframe->Data[1] |= (uint8_t) ( (_m->BCM_FrontRightLockCmd & (0x07U)) | ((_m->PTG_MovementCmd & (0x03U)) << 3U) | ((_m->BCM_RearLeftLockCmd & (0x07U)) << 5U) ); + cframe->Data[2] |= (uint8_t) ( (_m->BCM_RearRightLockCmd & (0x07U)) | ((_m->BCM_FLDoorClose_Req & (0x03U)) << 3U) | ((_m->PTG_MemorySetRequest & (0x03U)) << 5U) | ((_m->VehicleLockState & (0x01U)) << 7U) ); + cframe->Data[3] |= (uint8_t) ( (_m->BCM_DoorAjarState_FL & (0x03U)) | ((_m->BCM_DoorAjarState_FR & (0x03U)) << 2U) | ((_m->BCM_DoorAjarState_RL & (0x03U)) << 4U) | ((_m->BCM_DoorAjarState_RR & (0x03U)) << 6U) ); + cframe->Data[4] |= (uint8_t) ( (_m->BCM_VehDoubleLock_Stat & (0x01U)) | ((_m->BCM_FuelLidUnlock_Req & (0x01U)) << 1U) | ((_m->BCM_HVlid_Stat & (0x01U)) << 2U) | ((_m->BCM_RRDoorClose_Req & (0x03U)) << 3U) | ((_m->BCM_WindowsClose_Cmd & (0x01U)) << 5U) | ((_m->BCM_FRDoorClose_Req & (0x03U)) << 6U) ); + cframe->Data[5] |= (uint8_t) ( (_m->BCM_HoodOpen_Stat & (0x03U)) | ((_m->BCM_PanicAlertActive & (0x01U)) << 2U) | ((_m->BCM_RLDoorClose_Req & (0x03U)) << 3U) | ((_m->BCM_RearWiperWipe_Req & (0x01U)) << 5U) | ((_m->BCM_AlarmOFF_Stat & (0x01U)) << 6U) | ((_m->BCM_MovementSensOFF_Stat & (0x01U)) << 7U) ); + cframe->Data[6] |= (uint8_t) ( (_m->BCM_DoorMovDis_Stat & (0x01U)) | ((_m->BCM_Alarm_Req & (0x01U)) << 1U) | ((_m->BCM_Alarm_Reason & (0x0FU)) << 2U) | ((_m->BCM_DoorHandleLight_Req & (0x01U)) << 6U) | ((_m->BCM_WindowsOpen_Req & (0x01U)) << 7U) ); + + cframe->MsgId = (uint32_t) BCM_Lock_CTR_CANID; + cframe->DLC = (uint8_t) BCM_Lock_CTR_DLC; + cframe->IDE = (uint8_t) BCM_Lock_CTR_IDE; + return BCM_Lock_CTR_CANID; +} + +#else + +uint32_t Pack_BCM_Lock_CTR_candb(BCM_Lock_CTR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_Lock_CTR_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->VehicleLockStateReason & (0x0FU)) | ((_m->BCM_FrontLeftLockCmd & (0x07U)) << 4U) | ((_m->BCM_TrunkLatchRelease_Req & (0x01U)) << 7U) ); + _d[1] |= (uint8_t) ( (_m->BCM_FrontRightLockCmd & (0x07U)) | ((_m->PTG_MovementCmd & (0x03U)) << 3U) | ((_m->BCM_RearLeftLockCmd & (0x07U)) << 5U) ); + _d[2] |= (uint8_t) ( (_m->BCM_RearRightLockCmd & (0x07U)) | ((_m->BCM_FLDoorClose_Req & (0x03U)) << 3U) | ((_m->PTG_MemorySetRequest & (0x03U)) << 5U) | ((_m->VehicleLockState & (0x01U)) << 7U) ); + _d[3] |= (uint8_t) ( (_m->BCM_DoorAjarState_FL & (0x03U)) | ((_m->BCM_DoorAjarState_FR & (0x03U)) << 2U) | ((_m->BCM_DoorAjarState_RL & (0x03U)) << 4U) | ((_m->BCM_DoorAjarState_RR & (0x03U)) << 6U) ); + _d[4] |= (uint8_t) ( (_m->BCM_VehDoubleLock_Stat & (0x01U)) | ((_m->BCM_FuelLidUnlock_Req & (0x01U)) << 1U) | ((_m->BCM_HVlid_Stat & (0x01U)) << 2U) | ((_m->BCM_RRDoorClose_Req & (0x03U)) << 3U) | ((_m->BCM_WindowsClose_Cmd & (0x01U)) << 5U) | ((_m->BCM_FRDoorClose_Req & (0x03U)) << 6U) ); + _d[5] |= (uint8_t) ( (_m->BCM_HoodOpen_Stat & (0x03U)) | ((_m->BCM_PanicAlertActive & (0x01U)) << 2U) | ((_m->BCM_RLDoorClose_Req & (0x03U)) << 3U) | ((_m->BCM_RearWiperWipe_Req & (0x01U)) << 5U) | ((_m->BCM_AlarmOFF_Stat & (0x01U)) << 6U) | ((_m->BCM_MovementSensOFF_Stat & (0x01U)) << 7U) ); + _d[6] |= (uint8_t) ( (_m->BCM_DoorMovDis_Stat & (0x01U)) | ((_m->BCM_Alarm_Req & (0x01U)) << 1U) | ((_m->BCM_Alarm_Reason & (0x0FU)) << 2U) | ((_m->BCM_DoorHandleLight_Req & (0x01U)) << 6U) | ((_m->BCM_WindowsOpen_Req & (0x01U)) << 7U) ); + + *_len = (uint8_t) BCM_Lock_CTR_DLC; + *_ide = (uint8_t) BCM_Lock_CTR_IDE; + return BCM_Lock_CTR_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_HVC_Err_Status_Msg_candb(HVC_Err_Status_Msg_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->HVC_CompSpeed_Val_ro = (uint8_t) ( (_d[0] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->HVC_CompSpeed_Val_phys = (uint16_t) CANDB_HVC_CompSpeed_Val_ro_fromS(_m->HVC_CompSpeed_Val_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->HVC_Comp_Stat = (uint8_t) ( (_d[1] & (0x03U)) ); + _m->HVC_Reserved01 = (uint8_t) ( ((_d[1] >> 2U) & (0x3FU)) ); + _m->HVC_CompInputV_Val_ro = (uint8_t) ( (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->HVC_CompInputV_Val_phys = (uint16_t) CANDB_HVC_CompInputV_Val_ro_fromS(_m->HVC_CompInputV_Val_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->HVC_CompInputC_Val_ro = (uint8_t) ( (_d[3] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->HVC_CompInputC_Val_phys = (sigfloat_t)(CANDB_HVC_CompInputC_Val_ro_fromS(_m->HVC_CompInputC_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->HVC_CompInvTemp_Val_ro = (uint8_t) ( (_d[4] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->HVC_CompInvTemp_Val_phys = (int16_t) CANDB_HVC_CompInvTemp_Val_ro_fromS(_m->HVC_CompInvTemp_Val_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->HVC_CompPhaseC_Val_ro = (uint8_t) ( (_d[5] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->HVC_CompPhaseC_Val_phys = (sigfloat_t)(CANDB_HVC_CompPhaseC_Val_ro_fromS(_m->HVC_CompPhaseC_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->HVC_CompUV_Stat = (uint8_t) ( (_d[6] & (0x01U)) ); + _m->HVC_CompOV_Stat = (uint8_t) ( ((_d[6] >> 1U) & (0x01U)) ); + _m->HVC_CompOvHeat_Stat = (uint8_t) ( ((_d[6] >> 2U) & (0x01U)) ); + _m->HVC_CompOvTorque_Stat = (uint8_t) ( ((_d[6] >> 3U) & (0x01U)) ); + _m->HVC_CompLowVoltErr_Stat = (uint8_t) ( ((_d[6] >> 4U) & (0x01U)) ); + _m->HVC_CompComErr_Stat = (uint8_t) ( ((_d[6] >> 5U) & (0x01U)) ); + _m->HVC_Reserved02 = (uint8_t) ( ((_d[6] >> 6U) & (0x03U)) ); + _m->HVC_CompTempSensErr_Stat = (uint8_t) ( (_d[7] & (0x01U)) ); + _m->HVC_CompCurrSensErr_Stat = (uint8_t) ( ((_d[7] >> 1U) & (0x01U)) ); + _m->HVC_CompCurrShortCirc_Stat = (uint8_t) ( ((_d[7] >> 2U) & (0x01U)) ); + _m->HVC_CompInPowSupply_Stat = (uint8_t) ( ((_d[7] >> 3U) & (0x01U)) ); + _m->HVC_CompTorqueStallErr_Stat = (uint8_t) ( ((_d[7] >> 4U) & (0x01U)) ); + _m->HVC_CompVoltSensErr_Stat = (uint8_t) ( ((_d[7] >> 5U) & (0x01U)) ); + _m->HVC_Reserved03 = (uint8_t) ( ((_d[7] >> 6U) & (0x03U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < HVC_Err_Status_Msg_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_HVC_Err_Status_Msg_candb(&_m->mon1, HVC_Err_Status_Msg_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return HVC_Err_Status_Msg_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_HVC_Err_Status_Msg_candb(HVC_Err_Status_Msg_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(HVC_Err_Status_Msg_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->HVC_CompSpeed_Val_ro = (uint8_t) CANDB_HVC_CompSpeed_Val_ro_toS(_m->HVC_CompSpeed_Val_phys); + _m->HVC_CompInputV_Val_ro = (uint8_t) CANDB_HVC_CompInputV_Val_ro_toS(_m->HVC_CompInputV_Val_phys); + _m->HVC_CompInputC_Val_ro = (uint8_t) CANDB_HVC_CompInputC_Val_ro_toS(_m->HVC_CompInputC_Val_phys); + _m->HVC_CompInvTemp_Val_ro = (uint8_t) CANDB_HVC_CompInvTemp_Val_ro_toS(_m->HVC_CompInvTemp_Val_phys); + _m->HVC_CompPhaseC_Val_ro = (uint8_t) CANDB_HVC_CompPhaseC_Val_ro_toS(_m->HVC_CompPhaseC_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->HVC_CompSpeed_Val_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->HVC_Comp_Stat & (0x03U)) | ((_m->HVC_Reserved01 & (0x3FU)) << 2U) ); + cframe->Data[2] |= (uint8_t) ( (_m->HVC_CompInputV_Val_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->HVC_CompInputC_Val_ro & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->HVC_CompInvTemp_Val_ro & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->HVC_CompPhaseC_Val_ro & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->HVC_CompUV_Stat & (0x01U)) | ((_m->HVC_CompOV_Stat & (0x01U)) << 1U) | ((_m->HVC_CompOvHeat_Stat & (0x01U)) << 2U) | ((_m->HVC_CompOvTorque_Stat & (0x01U)) << 3U) | ((_m->HVC_CompLowVoltErr_Stat & (0x01U)) << 4U) | ((_m->HVC_CompComErr_Stat & (0x01U)) << 5U) | ((_m->HVC_Reserved02 & (0x03U)) << 6U) ); + cframe->Data[7] |= (uint8_t) ( (_m->HVC_CompTempSensErr_Stat & (0x01U)) | ((_m->HVC_CompCurrSensErr_Stat & (0x01U)) << 1U) | ((_m->HVC_CompCurrShortCirc_Stat & (0x01U)) << 2U) | ((_m->HVC_CompInPowSupply_Stat & (0x01U)) << 3U) | ((_m->HVC_CompTorqueStallErr_Stat & (0x01U)) << 4U) | ((_m->HVC_CompVoltSensErr_Stat & (0x01U)) << 5U) | ((_m->HVC_Reserved03 & (0x03U)) << 6U) ); + + cframe->MsgId = (uint32_t) HVC_Err_Status_Msg_CANID; + cframe->DLC = (uint8_t) HVC_Err_Status_Msg_DLC; + cframe->IDE = (uint8_t) HVC_Err_Status_Msg_IDE; + return HVC_Err_Status_Msg_CANID; +} + +#else + +uint32_t Pack_HVC_Err_Status_Msg_candb(HVC_Err_Status_Msg_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(HVC_Err_Status_Msg_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->HVC_CompSpeed_Val_ro = (uint8_t) CANDB_HVC_CompSpeed_Val_ro_toS(_m->HVC_CompSpeed_Val_phys); + _m->HVC_CompInputV_Val_ro = (uint8_t) CANDB_HVC_CompInputV_Val_ro_toS(_m->HVC_CompInputV_Val_phys); + _m->HVC_CompInputC_Val_ro = (uint8_t) CANDB_HVC_CompInputC_Val_ro_toS(_m->HVC_CompInputC_Val_phys); + _m->HVC_CompInvTemp_Val_ro = (uint8_t) CANDB_HVC_CompInvTemp_Val_ro_toS(_m->HVC_CompInvTemp_Val_phys); + _m->HVC_CompPhaseC_Val_ro = (uint8_t) CANDB_HVC_CompPhaseC_Val_ro_toS(_m->HVC_CompPhaseC_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->HVC_CompSpeed_Val_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( (_m->HVC_Comp_Stat & (0x03U)) | ((_m->HVC_Reserved01 & (0x3FU)) << 2U) ); + _d[2] |= (uint8_t) ( (_m->HVC_CompInputV_Val_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->HVC_CompInputC_Val_ro & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->HVC_CompInvTemp_Val_ro & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->HVC_CompPhaseC_Val_ro & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->HVC_CompUV_Stat & (0x01U)) | ((_m->HVC_CompOV_Stat & (0x01U)) << 1U) | ((_m->HVC_CompOvHeat_Stat & (0x01U)) << 2U) | ((_m->HVC_CompOvTorque_Stat & (0x01U)) << 3U) | ((_m->HVC_CompLowVoltErr_Stat & (0x01U)) << 4U) | ((_m->HVC_CompComErr_Stat & (0x01U)) << 5U) | ((_m->HVC_Reserved02 & (0x03U)) << 6U) ); + _d[7] |= (uint8_t) ( (_m->HVC_CompTempSensErr_Stat & (0x01U)) | ((_m->HVC_CompCurrSensErr_Stat & (0x01U)) << 1U) | ((_m->HVC_CompCurrShortCirc_Stat & (0x01U)) << 2U) | ((_m->HVC_CompInPowSupply_Stat & (0x01U)) << 3U) | ((_m->HVC_CompTorqueStallErr_Stat & (0x01U)) << 4U) | ((_m->HVC_CompVoltSensErr_Stat & (0x01U)) << 5U) | ((_m->HVC_Reserved03 & (0x03U)) << 6U) ); + + *_len = (uint8_t) HVC_Err_Status_Msg_DLC; + *_ide = (uint8_t) HVC_Err_Status_Msg_IDE; + return HVC_Err_Status_Msg_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_DCDC12_CNTRL_candb(BCM_DCDC12_CNTRL_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->BCM_DCDC1248_01_CS = (uint8_t) ( (_d[0] & (0xFFU)) ); + _m->BCM_DCDC1248_01_RC = (uint8_t) ( (_d[1] & (0x0FU)) ); + _m->BCM_DCDC1248_CurrLim12_ro = (uint16_t) ( ((_d[2] & (0x1FU)) << 4U) | ((_d[1] >> 4U) & (0x0FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_DCDC1248_CurrLim12_phys = (int16_t) CANDB_BCM_DCDC1248_CurrLim12_ro_fromS(_m->BCM_DCDC1248_CurrLim12_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_DCDC1248_DesVolt12_ro = (uint16_t) ( ((_d[3] & (0x7FU)) << 3U) | ((_d[2] >> 5U) & (0x07U)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_DCDC1248_DesVolt12_phys = (sigfloat_t)(CANDB_BCM_DCDC1248_DesVolt12_ro_fromS(_m->BCM_DCDC1248_DesVolt12_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_Volt_DCDC12_Req_ro = (uint8_t) ( (_d[4] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_Volt_DCDC12_Req_phys = (sigfloat_t)(CANDB_BCM_Volt_DCDC12_Req_ro_fromS(_m->BCM_Volt_DCDC12_Req_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_CurrLim_DCDC12 = (uint8_t) ( (_d[5] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < BCM_DCDC12_CNTRL_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_BCM_DCDC12_CNTRL_candb(&_m->mon1, BCM_DCDC12_CNTRL_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return BCM_DCDC12_CNTRL_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_BCM_DCDC12_CNTRL_candb(BCM_DCDC12_CNTRL_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_DCDC12_CNTRL_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_DCDC1248_CurrLim12_ro = (uint16_t) CANDB_BCM_DCDC1248_CurrLim12_ro_toS(_m->BCM_DCDC1248_CurrLim12_phys); + _m->BCM_DCDC1248_DesVolt12_ro = (uint16_t) CANDB_BCM_DCDC1248_DesVolt12_ro_toS(_m->BCM_DCDC1248_DesVolt12_phys); + _m->BCM_Volt_DCDC12_Req_ro = (uint8_t) CANDB_BCM_Volt_DCDC12_Req_ro_toS(_m->BCM_Volt_DCDC12_Req_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->BCM_DCDC1248_01_CS & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->BCM_DCDC1248_01_RC & (0x0FU)) | ((_m->BCM_DCDC1248_CurrLim12_ro & (0x0FU)) << 4U) ); + cframe->Data[2] |= (uint8_t) ( ((_m->BCM_DCDC1248_CurrLim12_ro >> 4U) & (0x1FU)) | ((_m->BCM_DCDC1248_DesVolt12_ro & (0x07U)) << 5U) ); + cframe->Data[3] |= (uint8_t) ( ((_m->BCM_DCDC1248_DesVolt12_ro >> 3U) & (0x7FU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->BCM_Volt_DCDC12_Req_ro & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->BCM_CurrLim_DCDC12 & (0xFFU)) ); + + cframe->MsgId = (uint32_t) BCM_DCDC12_CNTRL_CANID; + cframe->DLC = (uint8_t) BCM_DCDC12_CNTRL_DLC; + cframe->IDE = (uint8_t) BCM_DCDC12_CNTRL_IDE; + return BCM_DCDC12_CNTRL_CANID; +} + +#else + +uint32_t Pack_BCM_DCDC12_CNTRL_candb(BCM_DCDC12_CNTRL_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_DCDC12_CNTRL_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_DCDC1248_CurrLim12_ro = (uint16_t) CANDB_BCM_DCDC1248_CurrLim12_ro_toS(_m->BCM_DCDC1248_CurrLim12_phys); + _m->BCM_DCDC1248_DesVolt12_ro = (uint16_t) CANDB_BCM_DCDC1248_DesVolt12_ro_toS(_m->BCM_DCDC1248_DesVolt12_phys); + _m->BCM_Volt_DCDC12_Req_ro = (uint8_t) CANDB_BCM_Volt_DCDC12_Req_ro_toS(_m->BCM_Volt_DCDC12_Req_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->BCM_DCDC1248_01_CS & (0xFFU)) ); + _d[1] |= (uint8_t) ( (_m->BCM_DCDC1248_01_RC & (0x0FU)) | ((_m->BCM_DCDC1248_CurrLim12_ro & (0x0FU)) << 4U) ); + _d[2] |= (uint8_t) ( ((_m->BCM_DCDC1248_CurrLim12_ro >> 4U) & (0x1FU)) | ((_m->BCM_DCDC1248_DesVolt12_ro & (0x07U)) << 5U) ); + _d[3] |= (uint8_t) ( ((_m->BCM_DCDC1248_DesVolt12_ro >> 3U) & (0x7FU)) ); + _d[4] |= (uint8_t) ( (_m->BCM_Volt_DCDC12_Req_ro & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->BCM_CurrLim_DCDC12 & (0xFFU)) ); + + *_len = (uint8_t) BCM_DCDC12_CNTRL_DLC; + *_ide = (uint8_t) BCM_DCDC12_CNTRL_IDE; + return BCM_DCDC12_CNTRL_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_CCU_HVC_Req_Msg_candb(CCU_HVC_Req_Msg_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->CCU_eCompSpeedReq_Val_ro = (uint8_t) ( (_d[0] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->CCU_eCompSpeedReq_Val_phys = (uint16_t) CANDB_CCU_eCompSpeedReq_Val_ro_fromS(_m->CCU_eCompSpeedReq_Val_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->CCU_eCompReq_Stat = (uint8_t) ( (_d[1] & (0x01U)) ); + _m->CCU_LowTempValve_Req = (uint8_t) ( ((_d[1] >> 1U) & (0x03U)) ); + _m->CCU_HVC_Req_RC = (uint8_t) ( ((_d[1] >> 4U) & (0x0FU)) ); + _m->CCU_HVC_Req_CS = (uint8_t) ( (_d[2] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < CCU_HVC_Req_Msg_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_CCU_HVC_Req_Msg_candb(&_m->mon1, CCU_HVC_Req_Msg_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return CCU_HVC_Req_Msg_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_CCU_HVC_Req_Msg_candb(CCU_HVC_Req_Msg_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(CCU_HVC_Req_Msg_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->CCU_eCompSpeedReq_Val_ro = (uint8_t) CANDB_CCU_eCompSpeedReq_Val_ro_toS(_m->CCU_eCompSpeedReq_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->CCU_eCompSpeedReq_Val_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->CCU_eCompReq_Stat & (0x01U)) | ((_m->CCU_LowTempValve_Req & (0x03U)) << 1U) | ((_m->CCU_HVC_Req_RC & (0x0FU)) << 4U) ); + cframe->Data[2] |= (uint8_t) ( (_m->CCU_HVC_Req_CS & (0xFFU)) ); + + cframe->MsgId = (uint32_t) CCU_HVC_Req_Msg_CANID; + cframe->DLC = (uint8_t) CCU_HVC_Req_Msg_DLC; + cframe->IDE = (uint8_t) CCU_HVC_Req_Msg_IDE; + return CCU_HVC_Req_Msg_CANID; +} + +#else + +uint32_t Pack_CCU_HVC_Req_Msg_candb(CCU_HVC_Req_Msg_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(CCU_HVC_Req_Msg_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->CCU_eCompSpeedReq_Val_ro = (uint8_t) CANDB_CCU_eCompSpeedReq_Val_ro_toS(_m->CCU_eCompSpeedReq_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->CCU_eCompSpeedReq_Val_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( (_m->CCU_eCompReq_Stat & (0x01U)) | ((_m->CCU_LowTempValve_Req & (0x03U)) << 1U) | ((_m->CCU_HVC_Req_RC & (0x0FU)) << 4U) ); + _d[2] |= (uint8_t) ( (_m->CCU_HVC_Req_CS & (0xFFU)) ); + + *_len = (uint8_t) CCU_HVC_Req_Msg_DLC; + *_ide = (uint8_t) CCU_HVC_Req_Msg_IDE; + return CCU_HVC_Req_Msg_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_CCU_Stat1_candb(CCU_Stat1_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->CCU_ModeFL_Stat = (uint8_t) ( (_d[0] & (0x03U)) ); + _m->CCU_ModeFR_Stat = (uint8_t) ( ((_d[0] >> 2U) & (0x03U)) ); + _m->CCU_ModeRL_Stat = (uint8_t) ( ((_d[0] >> 4U) & (0x03U)) ); + _m->CCU_ModeRR_Stat = (uint8_t) ( ((_d[0] >> 6U) & (0x03U)) ); + _m->CCU_AutoModeFL_Stat = (uint8_t) ( (_d[1] & (0x07U)) ); + _m->CCU_AutoModeFR_Stat = (uint8_t) ( ((_d[1] >> 3U) & (0x07U)) ); + _m->CCU_AirDirectionRL_Face_Stat = (uint8_t) ( ((_d[1] >> 6U) & (0x01U)) ); + _m->CCU_AirDirectionRL_Foot_Stat = (uint8_t) ( ((_d[1] >> 7U) & (0x01U)) ); + _m->CCU_AutoModeRL_Stat = (uint8_t) ( (_d[2] & (0x07U)) ); + _m->CCU_AutoModeRR_Stat = (uint8_t) ( ((_d[2] >> 3U) & (0x07U)) ); + _m->CCU_AirDirectionRR_Face_Stat = (uint8_t) ( ((_d[2] >> 6U) & (0x01U)) ); + _m->CCU_AirDirectionRR_Foot_Stat = (uint8_t) ( ((_d[2] >> 7U) & (0x01U)) ); + _m->CCU_AirDirectionFL_Def_Stat = (uint8_t) ( (_d[3] & (0x01U)) ); + _m->CCU_AirDirectionFL_Face_Stat = (uint8_t) ( ((_d[3] >> 1U) & (0x01U)) ); + _m->CCU_AirDirectionFL_Foot_Stat = (uint8_t) ( ((_d[3] >> 2U) & (0x01U)) ); + _m->CCU_AirDirectionFR_Def_Stat = (uint8_t) ( ((_d[3] >> 3U) & (0x01U)) ); + _m->CCU_AirDirectionFR_Face_Stat = (uint8_t) ( ((_d[3] >> 4U) & (0x01U)) ); + _m->CCU_AirDirectionFR_Foot_Stat = (uint8_t) ( ((_d[3] >> 5U) & (0x01U)) ); + _m->CCU_Recirculation_Stat = (uint8_t) ( ((_d[3] >> 6U) & (0x03U)) ); + _m->CCU_BlowerSpeedFL_Stat = (uint8_t) ( (_d[4] & (0x07U)) ); + _m->CCU_TargetTempFL_Stat_ro = (uint8_t) ( ((_d[4] >> 3U) & (0x1FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->CCU_TargetTempFL_Stat_phys = (sigfloat_t)(CANDB_CCU_TargetTempFL_Stat_ro_fromS(_m->CCU_TargetTempFL_Stat_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->CCU_BlowerSpeedFR_Stat = (uint8_t) ( (_d[5] & (0x07U)) ); + _m->CCU_TargetTempFR_Stat_ro = (uint8_t) ( ((_d[5] >> 3U) & (0x1FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->CCU_TargetTempFR_Stat_phys = (sigfloat_t)(CANDB_CCU_TargetTempFR_Stat_ro_fromS(_m->CCU_TargetTempFR_Stat_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->CCU_BlowerSpeedRL_Stat = (uint8_t) ( (_d[6] & (0x07U)) ); + _m->CCU_TargetTempRR_Stat_ro = (uint8_t) ( ((_d[6] >> 3U) & (0x1FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->CCU_TargetTempRR_Stat_phys = (sigfloat_t)(CANDB_CCU_TargetTempRR_Stat_ro_fromS(_m->CCU_TargetTempRR_Stat_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->CCU_BlowerSpeedRR_Stat = (uint8_t) ( (_d[7] & (0x07U)) ); + _m->CCU_TargetTempRL_Stat_ro = (uint8_t) ( ((_d[7] >> 3U) & (0x1FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->CCU_TargetTempRL_Stat_phys = (sigfloat_t)(CANDB_CCU_TargetTempRL_Stat_ro_fromS(_m->CCU_TargetTempRL_Stat_ro)); +#endif // CANDB_USE_SIGFLOAT + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < CCU_Stat1_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_CCU_Stat1_candb(&_m->mon1, CCU_Stat1_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return CCU_Stat1_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_CCU_Stat1_candb(CCU_Stat1_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(CCU_Stat1_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->CCU_TargetTempFL_Stat_ro = (uint8_t) CANDB_CCU_TargetTempFL_Stat_ro_toS(_m->CCU_TargetTempFL_Stat_phys); + _m->CCU_TargetTempFR_Stat_ro = (uint8_t) CANDB_CCU_TargetTempFR_Stat_ro_toS(_m->CCU_TargetTempFR_Stat_phys); + _m->CCU_TargetTempRR_Stat_ro = (uint8_t) CANDB_CCU_TargetTempRR_Stat_ro_toS(_m->CCU_TargetTempRR_Stat_phys); + _m->CCU_TargetTempRL_Stat_ro = (uint8_t) CANDB_CCU_TargetTempRL_Stat_ro_toS(_m->CCU_TargetTempRL_Stat_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->CCU_ModeFL_Stat & (0x03U)) | ((_m->CCU_ModeFR_Stat & (0x03U)) << 2U) | ((_m->CCU_ModeRL_Stat & (0x03U)) << 4U) | ((_m->CCU_ModeRR_Stat & (0x03U)) << 6U) ); + cframe->Data[1] |= (uint8_t) ( (_m->CCU_AutoModeFL_Stat & (0x07U)) | ((_m->CCU_AutoModeFR_Stat & (0x07U)) << 3U) | ((_m->CCU_AirDirectionRL_Face_Stat & (0x01U)) << 6U) | ((_m->CCU_AirDirectionRL_Foot_Stat & (0x01U)) << 7U) ); + cframe->Data[2] |= (uint8_t) ( (_m->CCU_AutoModeRL_Stat & (0x07U)) | ((_m->CCU_AutoModeRR_Stat & (0x07U)) << 3U) | ((_m->CCU_AirDirectionRR_Face_Stat & (0x01U)) << 6U) | ((_m->CCU_AirDirectionRR_Foot_Stat & (0x01U)) << 7U) ); + cframe->Data[3] |= (uint8_t) ( (_m->CCU_AirDirectionFL_Def_Stat & (0x01U)) | ((_m->CCU_AirDirectionFL_Face_Stat & (0x01U)) << 1U) | ((_m->CCU_AirDirectionFL_Foot_Stat & (0x01U)) << 2U) | ((_m->CCU_AirDirectionFR_Def_Stat & (0x01U)) << 3U) | ((_m->CCU_AirDirectionFR_Face_Stat & (0x01U)) << 4U) | ((_m->CCU_AirDirectionFR_Foot_Stat & (0x01U)) << 5U) | ((_m->CCU_Recirculation_Stat & (0x03U)) << 6U) ); + cframe->Data[4] |= (uint8_t) ( (_m->CCU_BlowerSpeedFL_Stat & (0x07U)) | ((_m->CCU_TargetTempFL_Stat_ro & (0x1FU)) << 3U) ); + cframe->Data[5] |= (uint8_t) ( (_m->CCU_BlowerSpeedFR_Stat & (0x07U)) | ((_m->CCU_TargetTempFR_Stat_ro & (0x1FU)) << 3U) ); + cframe->Data[6] |= (uint8_t) ( (_m->CCU_BlowerSpeedRL_Stat & (0x07U)) | ((_m->CCU_TargetTempRR_Stat_ro & (0x1FU)) << 3U) ); + cframe->Data[7] |= (uint8_t) ( (_m->CCU_BlowerSpeedRR_Stat & (0x07U)) | ((_m->CCU_TargetTempRL_Stat_ro & (0x1FU)) << 3U) ); + + cframe->MsgId = (uint32_t) CCU_Stat1_CANID; + cframe->DLC = (uint8_t) CCU_Stat1_DLC; + cframe->IDE = (uint8_t) CCU_Stat1_IDE; + return CCU_Stat1_CANID; +} + +#else + +uint32_t Pack_CCU_Stat1_candb(CCU_Stat1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(CCU_Stat1_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->CCU_TargetTempFL_Stat_ro = (uint8_t) CANDB_CCU_TargetTempFL_Stat_ro_toS(_m->CCU_TargetTempFL_Stat_phys); + _m->CCU_TargetTempFR_Stat_ro = (uint8_t) CANDB_CCU_TargetTempFR_Stat_ro_toS(_m->CCU_TargetTempFR_Stat_phys); + _m->CCU_TargetTempRR_Stat_ro = (uint8_t) CANDB_CCU_TargetTempRR_Stat_ro_toS(_m->CCU_TargetTempRR_Stat_phys); + _m->CCU_TargetTempRL_Stat_ro = (uint8_t) CANDB_CCU_TargetTempRL_Stat_ro_toS(_m->CCU_TargetTempRL_Stat_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->CCU_ModeFL_Stat & (0x03U)) | ((_m->CCU_ModeFR_Stat & (0x03U)) << 2U) | ((_m->CCU_ModeRL_Stat & (0x03U)) << 4U) | ((_m->CCU_ModeRR_Stat & (0x03U)) << 6U) ); + _d[1] |= (uint8_t) ( (_m->CCU_AutoModeFL_Stat & (0x07U)) | ((_m->CCU_AutoModeFR_Stat & (0x07U)) << 3U) | ((_m->CCU_AirDirectionRL_Face_Stat & (0x01U)) << 6U) | ((_m->CCU_AirDirectionRL_Foot_Stat & (0x01U)) << 7U) ); + _d[2] |= (uint8_t) ( (_m->CCU_AutoModeRL_Stat & (0x07U)) | ((_m->CCU_AutoModeRR_Stat & (0x07U)) << 3U) | ((_m->CCU_AirDirectionRR_Face_Stat & (0x01U)) << 6U) | ((_m->CCU_AirDirectionRR_Foot_Stat & (0x01U)) << 7U) ); + _d[3] |= (uint8_t) ( (_m->CCU_AirDirectionFL_Def_Stat & (0x01U)) | ((_m->CCU_AirDirectionFL_Face_Stat & (0x01U)) << 1U) | ((_m->CCU_AirDirectionFL_Foot_Stat & (0x01U)) << 2U) | ((_m->CCU_AirDirectionFR_Def_Stat & (0x01U)) << 3U) | ((_m->CCU_AirDirectionFR_Face_Stat & (0x01U)) << 4U) | ((_m->CCU_AirDirectionFR_Foot_Stat & (0x01U)) << 5U) | ((_m->CCU_Recirculation_Stat & (0x03U)) << 6U) ); + _d[4] |= (uint8_t) ( (_m->CCU_BlowerSpeedFL_Stat & (0x07U)) | ((_m->CCU_TargetTempFL_Stat_ro & (0x1FU)) << 3U) ); + _d[5] |= (uint8_t) ( (_m->CCU_BlowerSpeedFR_Stat & (0x07U)) | ((_m->CCU_TargetTempFR_Stat_ro & (0x1FU)) << 3U) ); + _d[6] |= (uint8_t) ( (_m->CCU_BlowerSpeedRL_Stat & (0x07U)) | ((_m->CCU_TargetTempRR_Stat_ro & (0x1FU)) << 3U) ); + _d[7] |= (uint8_t) ( (_m->CCU_BlowerSpeedRR_Stat & (0x07U)) | ((_m->CCU_TargetTempRL_Stat_ro & (0x1FU)) << 3U) ); + + *_len = (uint8_t) CCU_Stat1_DLC; + *_ide = (uint8_t) CCU_Stat1_IDE; + return CCU_Stat1_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_CCU_Stat2_candb(CCU_Stat2_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->CCU_AromaCartridgeSw_Stat = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->CCU_FrontZoneSync_Stat = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + _m->CCU_RearZoneSync_Stat = (uint8_t) ( ((_d[0] >> 4U) & (0x01U)) ); + _m->CCU_AllZoneSync_Stat = (uint8_t) ( ((_d[0] >> 5U) & (0x01U)) ); + _m->CCU_ACfront_Stat = (uint8_t) ( ((_d[0] >> 6U) & (0x01U)) ); + _m->CCU_ACrear_Stat = (uint8_t) ( ((_d[0] >> 7U) & (0x01U)) ); + _m->CCU_ACmaxF_Stat = (uint8_t) ( (_d[1] & (0x01U)) ); + _m->CCU_ACmaxR_Stat = (uint8_t) ( ((_d[1] >> 1U) & (0x01U)) ); + _m->CCU_Defrost_Stat = (uint8_t) ( ((_d[1] >> 2U) & (0x01U)) ); + _m->CCU_Ionization_Stat = (uint8_t) ( ((_d[1] >> 3U) & (0x01U)) ); + _m->CCU_FootTempCorFL_Stat = (uint8_t) ( (_d[2] & (0x07U)) ); + _m->CCU_FootTempCorFR_Stat = (uint8_t) ( ((_d[2] >> 3U) & (0x07U)) ); + _m->CCU_AromaIntens_Stat = (uint8_t) ( ((_d[2] >> 6U) & (0x03U)) ); + _m->CCU_FootTempCorRL_Stat = (uint8_t) ( (_d[3] & (0x07U)) ); + _m->CCU_FootTempCorRR_Stat = (uint8_t) ( ((_d[3] >> 3U) & (0x07U)) ); + _m->CCU_DeflectorSwDL_Stat = (uint8_t) ( (_d[4] & (0x03U)) ); + _m->CCU_DeflectorSwDR_Stat = (uint8_t) ( ((_d[4] >> 2U) & (0x03U)) ); + _m->CCU_DeflectorSwFPL_Stat = (uint8_t) ( ((_d[4] >> 4U) & (0x03U)) ); + _m->CCU_DeflectorSwFPR_Stat = (uint8_t) ( ((_d[4] >> 6U) & (0x03U)) ); + _m->CCU_DeflectorSwFCL_Stat = (uint8_t) ( (_d[5] & (0x03U)) ); + _m->CCU_DeflectorSwFCR_Stat = (uint8_t) ( ((_d[5] >> 2U) & (0x03U)) ); + _m->CCU_DeflectorSwRLB_Stat = (uint8_t) ( ((_d[5] >> 4U) & (0x03U)) ); + _m->CCU_DeflectorSwRRB_Stat = (uint8_t) ( ((_d[5] >> 6U) & (0x03U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < CCU_Stat2_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_CCU_Stat2_candb(&_m->mon1, CCU_Stat2_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return CCU_Stat2_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_CCU_Stat2_candb(CCU_Stat2_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(CCU_Stat2_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->CCU_AromaCartridgeSw_Stat & (0x01U)) | ((_m->CCU_FrontZoneSync_Stat & (0x01U)) << 3U) | ((_m->CCU_RearZoneSync_Stat & (0x01U)) << 4U) | ((_m->CCU_AllZoneSync_Stat & (0x01U)) << 5U) | ((_m->CCU_ACfront_Stat & (0x01U)) << 6U) | ((_m->CCU_ACrear_Stat & (0x01U)) << 7U) ); + cframe->Data[1] |= (uint8_t) ( (_m->CCU_ACmaxF_Stat & (0x01U)) | ((_m->CCU_ACmaxR_Stat & (0x01U)) << 1U) | ((_m->CCU_Defrost_Stat & (0x01U)) << 2U) | ((_m->CCU_Ionization_Stat & (0x01U)) << 3U) ); + cframe->Data[2] |= (uint8_t) ( (_m->CCU_FootTempCorFL_Stat & (0x07U)) | ((_m->CCU_FootTempCorFR_Stat & (0x07U)) << 3U) | ((_m->CCU_AromaIntens_Stat & (0x03U)) << 6U) ); + cframe->Data[3] |= (uint8_t) ( (_m->CCU_FootTempCorRL_Stat & (0x07U)) | ((_m->CCU_FootTempCorRR_Stat & (0x07U)) << 3U) ); + cframe->Data[4] |= (uint8_t) ( (_m->CCU_DeflectorSwDL_Stat & (0x03U)) | ((_m->CCU_DeflectorSwDR_Stat & (0x03U)) << 2U) | ((_m->CCU_DeflectorSwFPL_Stat & (0x03U)) << 4U) | ((_m->CCU_DeflectorSwFPR_Stat & (0x03U)) << 6U) ); + cframe->Data[5] |= (uint8_t) ( (_m->CCU_DeflectorSwFCL_Stat & (0x03U)) | ((_m->CCU_DeflectorSwFCR_Stat & (0x03U)) << 2U) | ((_m->CCU_DeflectorSwRLB_Stat & (0x03U)) << 4U) | ((_m->CCU_DeflectorSwRRB_Stat & (0x03U)) << 6U) ); + + cframe->MsgId = (uint32_t) CCU_Stat2_CANID; + cframe->DLC = (uint8_t) CCU_Stat2_DLC; + cframe->IDE = (uint8_t) CCU_Stat2_IDE; + return CCU_Stat2_CANID; +} + +#else + +uint32_t Pack_CCU_Stat2_candb(CCU_Stat2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(CCU_Stat2_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->CCU_AromaCartridgeSw_Stat & (0x01U)) | ((_m->CCU_FrontZoneSync_Stat & (0x01U)) << 3U) | ((_m->CCU_RearZoneSync_Stat & (0x01U)) << 4U) | ((_m->CCU_AllZoneSync_Stat & (0x01U)) << 5U) | ((_m->CCU_ACfront_Stat & (0x01U)) << 6U) | ((_m->CCU_ACrear_Stat & (0x01U)) << 7U) ); + _d[1] |= (uint8_t) ( (_m->CCU_ACmaxF_Stat & (0x01U)) | ((_m->CCU_ACmaxR_Stat & (0x01U)) << 1U) | ((_m->CCU_Defrost_Stat & (0x01U)) << 2U) | ((_m->CCU_Ionization_Stat & (0x01U)) << 3U) ); + _d[2] |= (uint8_t) ( (_m->CCU_FootTempCorFL_Stat & (0x07U)) | ((_m->CCU_FootTempCorFR_Stat & (0x07U)) << 3U) | ((_m->CCU_AromaIntens_Stat & (0x03U)) << 6U) ); + _d[3] |= (uint8_t) ( (_m->CCU_FootTempCorRL_Stat & (0x07U)) | ((_m->CCU_FootTempCorRR_Stat & (0x07U)) << 3U) ); + _d[4] |= (uint8_t) ( (_m->CCU_DeflectorSwDL_Stat & (0x03U)) | ((_m->CCU_DeflectorSwDR_Stat & (0x03U)) << 2U) | ((_m->CCU_DeflectorSwFPL_Stat & (0x03U)) << 4U) | ((_m->CCU_DeflectorSwFPR_Stat & (0x03U)) << 6U) ); + _d[5] |= (uint8_t) ( (_m->CCU_DeflectorSwFCL_Stat & (0x03U)) | ((_m->CCU_DeflectorSwFCR_Stat & (0x03U)) << 2U) | ((_m->CCU_DeflectorSwRLB_Stat & (0x03U)) << 4U) | ((_m->CCU_DeflectorSwRRB_Stat & (0x03U)) << 6U) ); + + *_len = (uint8_t) CCU_Stat2_DLC; + *_ide = (uint8_t) CCU_Stat2_IDE; + return CCU_Stat2_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_CCU_Requests_candb(CCU_Requests_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->CCU_CarpetHeatFL_Req = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->CCU_CarpetHeatFR_Req = (uint8_t) ( ((_d[0] >> 1U) & (0x01U)) ); + _m->CCU_CarpetHeatRL_Req = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + _m->CCU_CarpetHeatRR_Req = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < CCU_Requests_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_CCU_Requests_candb(&_m->mon1, CCU_Requests_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return CCU_Requests_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_CCU_Requests_candb(CCU_Requests_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(CCU_Requests_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->CCU_CarpetHeatFL_Req & (0x01U)) | ((_m->CCU_CarpetHeatFR_Req & (0x01U)) << 1U) | ((_m->CCU_CarpetHeatRL_Req & (0x01U)) << 2U) | ((_m->CCU_CarpetHeatRR_Req & (0x01U)) << 3U) ); + + cframe->MsgId = (uint32_t) CCU_Requests_CANID; + cframe->DLC = (uint8_t) CCU_Requests_DLC; + cframe->IDE = (uint8_t) CCU_Requests_IDE; + return CCU_Requests_CANID; +} + +#else + +uint32_t Pack_CCU_Requests_candb(CCU_Requests_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(CCU_Requests_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->CCU_CarpetHeatFL_Req & (0x01U)) | ((_m->CCU_CarpetHeatFR_Req & (0x01U)) << 1U) | ((_m->CCU_CarpetHeatRL_Req & (0x01U)) << 2U) | ((_m->CCU_CarpetHeatRR_Req & (0x01U)) << 3U) ); + + *_len = (uint8_t) CCU_Requests_DLC; + *_ide = (uint8_t) CCU_Requests_IDE; + return CCU_Requests_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_CCU_Stat3_candb(CCU_Stat3_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->CCU_AromaCartridgeCapacity_Stat_ro = (uint8_t) ( (_d[0] & (0x0FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->CCU_AromaCartridgeCapacity_Stat_phys = (uint8_t) CANDB_CCU_AromaCartridgeCapacity_Stat_ro_fromS(_m->CCU_AromaCartridgeCapacity_Stat_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->CCU_AromaCartridgeFlavor_Stat = (uint8_t) ( ((_d[1] >> 4U) & (0x0FU)) ); + _m->CCU_AromaFaultReason_Stat = (uint8_t) ( (_d[3] & (0x07U)) ); + _m->CCU_RLfootBlowDis_Stat = (uint8_t) ( ((_d[3] >> 3U) & (0x01U)) ); + _m->CCU_RRfootBlowDis_Stat = (uint8_t) ( ((_d[3] >> 4U) & (0x01U)) ); + _m->CCU_RestMode2_Stat = (uint8_t) ( ((_d[3] >> 5U) & (0x03U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < CCU_Stat3_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_CCU_Stat3_candb(&_m->mon1, CCU_Stat3_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return CCU_Stat3_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_CCU_Stat3_candb(CCU_Stat3_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(CCU_Stat3_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->CCU_AromaCartridgeCapacity_Stat_ro = (uint8_t) CANDB_CCU_AromaCartridgeCapacity_Stat_ro_toS(_m->CCU_AromaCartridgeCapacity_Stat_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->CCU_AromaCartridgeCapacity_Stat_ro & (0x0FU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->CCU_AromaCartridgeFlavor_Stat & (0x0FU)) << 4U) ); + cframe->Data[3] |= (uint8_t) ( (_m->CCU_AromaFaultReason_Stat & (0x07U)) | ((_m->CCU_RLfootBlowDis_Stat & (0x01U)) << 3U) | ((_m->CCU_RRfootBlowDis_Stat & (0x01U)) << 4U) | ((_m->CCU_RestMode2_Stat & (0x03U)) << 5U) ); + + cframe->MsgId = (uint32_t) CCU_Stat3_CANID; + cframe->DLC = (uint8_t) CCU_Stat3_DLC; + cframe->IDE = (uint8_t) CCU_Stat3_IDE; + return CCU_Stat3_CANID; +} + +#else + +uint32_t Pack_CCU_Stat3_candb(CCU_Stat3_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(CCU_Stat3_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->CCU_AromaCartridgeCapacity_Stat_ro = (uint8_t) CANDB_CCU_AromaCartridgeCapacity_Stat_ro_toS(_m->CCU_AromaCartridgeCapacity_Stat_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->CCU_AromaCartridgeCapacity_Stat_ro & (0x0FU)) ); + _d[1] |= (uint8_t) ( ((_m->CCU_AromaCartridgeFlavor_Stat & (0x0FU)) << 4U) ); + _d[3] |= (uint8_t) ( (_m->CCU_AromaFaultReason_Stat & (0x07U)) | ((_m->CCU_RLfootBlowDis_Stat & (0x01U)) << 3U) | ((_m->CCU_RRfootBlowDis_Stat & (0x01U)) << 4U) | ((_m->CCU_RestMode2_Stat & (0x03U)) << 5U) ); + + *_len = (uint8_t) CCU_Stat3_DLC; + *_ide = (uint8_t) CCU_Stat3_IDE; + return CCU_Stat3_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_CCU_VCU_Msg1_candb(CCU_VCU_Msg1_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->CCU_Sen_Pressure_ro = (uint16_t) ( ((_d[1] & (0x0FU)) << 8U) | (_d[0] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->CCU_Sen_Pressure_phys = (sigfloat_t)(CANDB_CCU_Sen_Pressure_ro_fromS(_m->CCU_Sen_Pressure_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->CCU_EvaTargetTemp_Val_ro = (int16_t) __ext_sig__(( ((_d[2] & (0xFFU)) << 4U) | ((_d[1] >> 4U) & (0x0FU)) ), 12); +#ifdef CANDB_USE_SIGFLOAT + _m->CCU_EvaTargetTemp_Val_phys = (sigfloat_t)(CANDB_CCU_EvaTargetTemp_Val_ro_fromS(_m->CCU_EvaTargetTemp_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->CCU_EvaCurrTempF_Val_ro = (int16_t) __ext_sig__(( ((_d[4] & (0x0FU)) << 8U) | (_d[3] & (0xFFU)) ), 12); +#ifdef CANDB_USE_SIGFLOAT + _m->CCU_EvaCurrTempF_Val_phys = (sigfloat_t)(CANDB_CCU_EvaCurrTempF_Val_ro_fromS(_m->CCU_EvaCurrTempF_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->CCU_EvaCurrTempR_Val_ro = (int16_t) __ext_sig__(( ((_d[5] & (0xFFU)) << 4U) | ((_d[4] >> 4U) & (0x0FU)) ), 12); +#ifdef CANDB_USE_SIGFLOAT + _m->CCU_EvaCurrTempR_Val_phys = (sigfloat_t)(CANDB_CCU_EvaCurrTempR_Val_ro_fromS(_m->CCU_EvaCurrTempR_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->CCU_LiquidHeaterTargetTemp_Req = (uint8_t) ( (_d[6] & (0x7FU)) ); + _m->CCU_VCU_Msg1_RC = (uint8_t) ( ((_d[7] >> 4U) & (0x0FU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < CCU_VCU_Msg1_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_CCU_VCU_Msg1_candb(&_m->mon1, CCU_VCU_Msg1_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return CCU_VCU_Msg1_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_CCU_VCU_Msg1_candb(CCU_VCU_Msg1_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(CCU_VCU_Msg1_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->CCU_Sen_Pressure_ro = (uint16_t) CANDB_CCU_Sen_Pressure_ro_toS(_m->CCU_Sen_Pressure_phys); + _m->CCU_EvaTargetTemp_Val_ro = (int16_t) CANDB_CCU_EvaTargetTemp_Val_ro_toS(_m->CCU_EvaTargetTemp_Val_phys); + _m->CCU_EvaCurrTempF_Val_ro = (int16_t) CANDB_CCU_EvaCurrTempF_Val_ro_toS(_m->CCU_EvaCurrTempF_Val_phys); + _m->CCU_EvaCurrTempR_Val_ro = (int16_t) CANDB_CCU_EvaCurrTempR_Val_ro_toS(_m->CCU_EvaCurrTempR_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->CCU_Sen_Pressure_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->CCU_Sen_Pressure_ro >> 8U) & (0x0FU)) | ((_m->CCU_EvaTargetTemp_Val_ro & (0x0FU)) << 4U) ); + cframe->Data[2] |= (uint8_t) ( ((_m->CCU_EvaTargetTemp_Val_ro >> 4U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->CCU_EvaCurrTempF_Val_ro & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->CCU_EvaCurrTempF_Val_ro >> 8U) & (0x0FU)) | ((_m->CCU_EvaCurrTempR_Val_ro & (0x0FU)) << 4U) ); + cframe->Data[5] |= (uint8_t) ( ((_m->CCU_EvaCurrTempR_Val_ro >> 4U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->CCU_LiquidHeaterTargetTemp_Req & (0x7FU)) ); + cframe->Data[7] |= (uint8_t) ( ((_m->CCU_VCU_Msg1_RC & (0x0FU)) << 4U) ); + + cframe->MsgId = (uint32_t) CCU_VCU_Msg1_CANID; + cframe->DLC = (uint8_t) CCU_VCU_Msg1_DLC; + cframe->IDE = (uint8_t) CCU_VCU_Msg1_IDE; + return CCU_VCU_Msg1_CANID; +} + +#else + +uint32_t Pack_CCU_VCU_Msg1_candb(CCU_VCU_Msg1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(CCU_VCU_Msg1_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->CCU_Sen_Pressure_ro = (uint16_t) CANDB_CCU_Sen_Pressure_ro_toS(_m->CCU_Sen_Pressure_phys); + _m->CCU_EvaTargetTemp_Val_ro = (int16_t) CANDB_CCU_EvaTargetTemp_Val_ro_toS(_m->CCU_EvaTargetTemp_Val_phys); + _m->CCU_EvaCurrTempF_Val_ro = (int16_t) CANDB_CCU_EvaCurrTempF_Val_ro_toS(_m->CCU_EvaCurrTempF_Val_phys); + _m->CCU_EvaCurrTempR_Val_ro = (int16_t) CANDB_CCU_EvaCurrTempR_Val_ro_toS(_m->CCU_EvaCurrTempR_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->CCU_Sen_Pressure_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->CCU_Sen_Pressure_ro >> 8U) & (0x0FU)) | ((_m->CCU_EvaTargetTemp_Val_ro & (0x0FU)) << 4U) ); + _d[2] |= (uint8_t) ( ((_m->CCU_EvaTargetTemp_Val_ro >> 4U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->CCU_EvaCurrTempF_Val_ro & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->CCU_EvaCurrTempF_Val_ro >> 8U) & (0x0FU)) | ((_m->CCU_EvaCurrTempR_Val_ro & (0x0FU)) << 4U) ); + _d[5] |= (uint8_t) ( ((_m->CCU_EvaCurrTempR_Val_ro >> 4U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->CCU_LiquidHeaterTargetTemp_Req & (0x7FU)) ); + _d[7] |= (uint8_t) ( ((_m->CCU_VCU_Msg1_RC & (0x0FU)) << 4U) ); + + *_len = (uint8_t) CCU_VCU_Msg1_DLC; + *_ide = (uint8_t) CCU_VCU_Msg1_IDE; + return CCU_VCU_Msg1_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_CCU_VCU_Msg2_candb(CCU_VCU_Msg2_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->eTXV_batChiller_Pos_Stat = (uint8_t) ( (_d[0] & (0x7FU)) ); + _m->eTXV_batChiller_Err_Stat = (uint8_t) ( (_d[1] & (0x03U)) ); + _m->eTXV_batChiller_Pressure_Val_ro = (uint8_t) ( ((_d[1] >> 2U) & (0x3FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->eTXV_batChiller_Pressure_Val_phys = (sigfloat_t)(CANDB_eTXV_batChiller_Pressure_Val_ro_fromS(_m->eTXV_batChiller_Pressure_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->eTXV_batChiller_Temp_Val_ro = (uint8_t) ( (_d[2] & (0x7FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->eTXV_batChiller_Temp_Val_phys = (int8_t) CANDB_eTXV_batChiller_Temp_Val_ro_fromS(_m->eTXV_batChiller_Temp_Val_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->eTXV_eeChiller_Pos_Stat = (uint8_t) ( (_d[3] & (0x7FU)) ); + _m->eTXV_eeChiller_Err_Stat = (uint8_t) ( (_d[4] & (0x03U)) ); + _m->eTXV_eeChiller_Pressure_Val_ro = (uint8_t) ( ((_d[4] >> 2U) & (0x3FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->eTXV_eeChiller_Pressure_Val_phys = (sigfloat_t)(CANDB_eTXV_eeChiller_Pressure_Val_ro_fromS(_m->eTXV_eeChiller_Pressure_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->eTXV_eeChiller_Temp_Val_ro = (uint8_t) ( (_d[5] & (0x7FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->eTXV_eeChiller_Temp_Val_phys = (int8_t) CANDB_eTXV_eeChiller_Temp_Val_ro_fromS(_m->eTXV_eeChiller_Temp_Val_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->CCU_VCU_Msg2_RC = (uint8_t) ( ((_d[7] >> 4U) & (0x0FU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < CCU_VCU_Msg2_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_CCU_VCU_Msg2_candb(&_m->mon1, CCU_VCU_Msg2_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return CCU_VCU_Msg2_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_CCU_VCU_Msg2_candb(CCU_VCU_Msg2_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(CCU_VCU_Msg2_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->eTXV_batChiller_Pressure_Val_ro = (uint8_t) CANDB_eTXV_batChiller_Pressure_Val_ro_toS(_m->eTXV_batChiller_Pressure_Val_phys); + _m->eTXV_batChiller_Temp_Val_ro = (uint8_t) CANDB_eTXV_batChiller_Temp_Val_ro_toS(_m->eTXV_batChiller_Temp_Val_phys); + _m->eTXV_eeChiller_Pressure_Val_ro = (uint8_t) CANDB_eTXV_eeChiller_Pressure_Val_ro_toS(_m->eTXV_eeChiller_Pressure_Val_phys); + _m->eTXV_eeChiller_Temp_Val_ro = (uint8_t) CANDB_eTXV_eeChiller_Temp_Val_ro_toS(_m->eTXV_eeChiller_Temp_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->eTXV_batChiller_Pos_Stat & (0x7FU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->eTXV_batChiller_Err_Stat & (0x03U)) | ((_m->eTXV_batChiller_Pressure_Val_ro & (0x3FU)) << 2U) ); + cframe->Data[2] |= (uint8_t) ( (_m->eTXV_batChiller_Temp_Val_ro & (0x7FU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->eTXV_eeChiller_Pos_Stat & (0x7FU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->eTXV_eeChiller_Err_Stat & (0x03U)) | ((_m->eTXV_eeChiller_Pressure_Val_ro & (0x3FU)) << 2U) ); + cframe->Data[5] |= (uint8_t) ( (_m->eTXV_eeChiller_Temp_Val_ro & (0x7FU)) ); + cframe->Data[7] |= (uint8_t) ( ((_m->CCU_VCU_Msg2_RC & (0x0FU)) << 4U) ); + + cframe->MsgId = (uint32_t) CCU_VCU_Msg2_CANID; + cframe->DLC = (uint8_t) CCU_VCU_Msg2_DLC; + cframe->IDE = (uint8_t) CCU_VCU_Msg2_IDE; + return CCU_VCU_Msg2_CANID; +} + +#else + +uint32_t Pack_CCU_VCU_Msg2_candb(CCU_VCU_Msg2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(CCU_VCU_Msg2_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->eTXV_batChiller_Pressure_Val_ro = (uint8_t) CANDB_eTXV_batChiller_Pressure_Val_ro_toS(_m->eTXV_batChiller_Pressure_Val_phys); + _m->eTXV_batChiller_Temp_Val_ro = (uint8_t) CANDB_eTXV_batChiller_Temp_Val_ro_toS(_m->eTXV_batChiller_Temp_Val_phys); + _m->eTXV_eeChiller_Pressure_Val_ro = (uint8_t) CANDB_eTXV_eeChiller_Pressure_Val_ro_toS(_m->eTXV_eeChiller_Pressure_Val_phys); + _m->eTXV_eeChiller_Temp_Val_ro = (uint8_t) CANDB_eTXV_eeChiller_Temp_Val_ro_toS(_m->eTXV_eeChiller_Temp_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->eTXV_batChiller_Pos_Stat & (0x7FU)) ); + _d[1] |= (uint8_t) ( (_m->eTXV_batChiller_Err_Stat & (0x03U)) | ((_m->eTXV_batChiller_Pressure_Val_ro & (0x3FU)) << 2U) ); + _d[2] |= (uint8_t) ( (_m->eTXV_batChiller_Temp_Val_ro & (0x7FU)) ); + _d[3] |= (uint8_t) ( (_m->eTXV_eeChiller_Pos_Stat & (0x7FU)) ); + _d[4] |= (uint8_t) ( (_m->eTXV_eeChiller_Err_Stat & (0x03U)) | ((_m->eTXV_eeChiller_Pressure_Val_ro & (0x3FU)) << 2U) ); + _d[5] |= (uint8_t) ( (_m->eTXV_eeChiller_Temp_Val_ro & (0x7FU)) ); + _d[7] |= (uint8_t) ( ((_m->CCU_VCU_Msg2_RC & (0x0FU)) << 4U) ); + + *_len = (uint8_t) CCU_VCU_Msg2_DLC; + *_ide = (uint8_t) CCU_VCU_Msg2_IDE; + return CCU_VCU_Msg2_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_IC_Info_Msg_candb(BCM_IC_Info_Msg_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->BCM_WasherFluidLevel = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->BCM_LvBatCharging_Stat = (uint8_t) ( ((_d[0] >> 1U) & (0x01U)) ); + _m->BCM_EngStartNotif_Stat = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + _m->BCM_PowerDoorsNotif_Stat = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + _m->BCM_CalSteeringWhColumnReq = (uint8_t) ( ((_d[0] >> 4U) & (0x01U)) ); + _m->BCM_AdaptiveLghtsFailure = (uint8_t) ( ((_d[0] >> 5U) & (0x01U)) ); + _m->BCM_BrakeLightLeft_Status = (uint8_t) ( ((_d[0] >> 6U) & (0x01U)) ); + _m->BCM_BrakeLightRight_Status = (uint8_t) ( ((_d[0] >> 7U) & (0x01U)) ); + _m->BCM_AllWthrLght_Fault = (uint8_t) ( (_d[1] & (0x01U)) ); + _m->BCM_LowBeamLeft_Status = (uint8_t) ( ((_d[1] >> 1U) & (0x01U)) ); + _m->BCM_LowBeamRight_Status = (uint8_t) ( ((_d[1] >> 2U) & (0x01U)) ); + _m->BCM_ReverseLightsRight_Status = (uint8_t) ( ((_d[1] >> 3U) & (0x01U)) ); + _m->BCM_RearLeft_FogLight_Status = (uint8_t) ( ((_d[1] >> 4U) & (0x01U)) ); + _m->BCM_RearRight_FogLight_Status = (uint8_t) ( ((_d[1] >> 5U) & (0x01U)) ); + _m->BCM_ReverseLightsLeft_Status = (uint8_t) ( ((_d[1] >> 6U) & (0x01U)) ); + _m->BCM_HighBeamLeft_Status = (uint8_t) ( ((_d[1] >> 7U) & (0x01U)) ); + _m->BCM_HighBeamRight_Status = (uint8_t) ( (_d[2] & (0x01U)) ); + _m->BCM_PositionLight_RL_Status = (uint8_t) ( ((_d[2] >> 1U) & (0x01U)) ); + _m->BCM_PositionLight_RR_Status = (uint8_t) ( ((_d[2] >> 2U) & (0x01U)) ); + _m->BCM_DaytimeLightRight_Status = (uint8_t) ( ((_d[2] >> 3U) & (0x01U)) ); + _m->BCM_DaytimeLightLeft_Status = (uint8_t) ( ((_d[2] >> 4U) & (0x01U)) ); + _m->BCM_WarningInd = (uint8_t) ( ((_d[2] >> 5U) & (0x01U)) ); + _m->BCM_CorneringLightRight_Status = (uint8_t) ( ((_d[2] >> 6U) & (0x01U)) ); + _m->BCM_CorneringLightLeft_Status = (uint8_t) ( ((_d[2] >> 7U) & (0x01U)) ); + _m->BCM_PosLightFL_status = (uint8_t) ( (_d[3] & (0x01U)) ); + _m->BCM_PosLightFR_status = (uint8_t) ( ((_d[3] >> 1U) & (0x01U)) ); + _m->BCM_TurnIndicatorML_Status = (uint8_t) ( ((_d[3] >> 2U) & (0x01U)) ); + _m->BCM_TurnIndicatorMR_Status = (uint8_t) ( ((_d[3] >> 3U) & (0x01U)) ); + _m->BCM_TurnIndicatorRL_Status = (uint8_t) ( ((_d[3] >> 4U) & (0x01U)) ); + _m->BCM_TurnIndicatorRR_Status = (uint8_t) ( ((_d[3] >> 5U) & (0x01U)) ); + _m->BCM_TurnIndicatorFL_Status = (uint8_t) ( ((_d[3] >> 6U) & (0x01U)) ); + _m->BCM_TurnIndicatorFR_Status = (uint8_t) ( ((_d[3] >> 7U) & (0x01U)) ); + _m->BCM_HeadLghtLevelinglFailure = (uint8_t) ( (_d[4] & (0x01U)) ); + _m->BCM_PowerSteeringCtrlFault = (uint8_t) ( ((_d[4] >> 1U) & (0x01U)) ); + _m->BCM_LvBat1_SOC = (uint8_t) ( ((_d[4] >> 2U) & (0x03U)) ); + _m->BCM_LvBat1_SOH = (uint8_t) ( ((_d[4] >> 4U) & (0x03U)) ); + _m->BCM_HighBeamAutoStatus = (uint8_t) ( ((_d[4] >> 6U) & (0x01U)) ); + _m->BCM_ExteriorSystemStatus = (uint8_t) ( ((_d[4] >> 7U) & (0x01U)) ); + _m->BCM_LvBat1_SOC_Pct = (uint8_t) ( (_d[5] & (0x7FU)) ); + _m->BCM_TrunkLidOpenWarn_Req = (uint8_t) ( ((_d[5] >> 7U) & (0x01U)) ); + _m->BCM_FuelLvl_HMI = (uint8_t) ( (_d[6] & (0x7FU)) ); + _m->BCM_SRoofManipulationWarn_Req = (uint8_t) ( ((_d[6] >> 7U) & (0x01U)) ); + _m->BCM_DrvMdLim_Stat = (uint8_t) ( (_d[7] & (0x01U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < BCM_IC_Info_Msg_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_BCM_IC_Info_Msg_candb(&_m->mon1, BCM_IC_Info_Msg_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return BCM_IC_Info_Msg_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_BCM_IC_Info_Msg_candb(BCM_IC_Info_Msg_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_IC_Info_Msg_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->BCM_WasherFluidLevel & (0x01U)) | ((_m->BCM_LvBatCharging_Stat & (0x01U)) << 1U) | ((_m->BCM_EngStartNotif_Stat & (0x01U)) << 2U) | ((_m->BCM_PowerDoorsNotif_Stat & (0x01U)) << 3U) | ((_m->BCM_CalSteeringWhColumnReq & (0x01U)) << 4U) | ((_m->BCM_AdaptiveLghtsFailure & (0x01U)) << 5U) | ((_m->BCM_BrakeLightLeft_Status & (0x01U)) << 6U) | ((_m->BCM_BrakeLightRight_Status & (0x01U)) << 7U) ); + cframe->Data[1] |= (uint8_t) ( (_m->BCM_AllWthrLght_Fault & (0x01U)) | ((_m->BCM_LowBeamLeft_Status & (0x01U)) << 1U) | ((_m->BCM_LowBeamRight_Status & (0x01U)) << 2U) | ((_m->BCM_ReverseLightsRight_Status & (0x01U)) << 3U) | ((_m->BCM_RearLeft_FogLight_Status & (0x01U)) << 4U) | ((_m->BCM_RearRight_FogLight_Status & (0x01U)) << 5U) | ((_m->BCM_ReverseLightsLeft_Status & (0x01U)) << 6U) | ((_m->BCM_HighBeamLeft_Status & (0x01U)) << 7U) ); + cframe->Data[2] |= (uint8_t) ( (_m->BCM_HighBeamRight_Status & (0x01U)) | ((_m->BCM_PositionLight_RL_Status & (0x01U)) << 1U) | ((_m->BCM_PositionLight_RR_Status & (0x01U)) << 2U) | ((_m->BCM_DaytimeLightRight_Status & (0x01U)) << 3U) | ((_m->BCM_DaytimeLightLeft_Status & (0x01U)) << 4U) | ((_m->BCM_WarningInd & (0x01U)) << 5U) | ((_m->BCM_CorneringLightRight_Status & (0x01U)) << 6U) | ((_m->BCM_CorneringLightLeft_Status & (0x01U)) << 7U) ); + cframe->Data[3] |= (uint8_t) ( (_m->BCM_PosLightFL_status & (0x01U)) | ((_m->BCM_PosLightFR_status & (0x01U)) << 1U) | ((_m->BCM_TurnIndicatorML_Status & (0x01U)) << 2U) | ((_m->BCM_TurnIndicatorMR_Status & (0x01U)) << 3U) | ((_m->BCM_TurnIndicatorRL_Status & (0x01U)) << 4U) | ((_m->BCM_TurnIndicatorRR_Status & (0x01U)) << 5U) | ((_m->BCM_TurnIndicatorFL_Status & (0x01U)) << 6U) | ((_m->BCM_TurnIndicatorFR_Status & (0x01U)) << 7U) ); + cframe->Data[4] |= (uint8_t) ( (_m->BCM_HeadLghtLevelinglFailure & (0x01U)) | ((_m->BCM_PowerSteeringCtrlFault & (0x01U)) << 1U) | ((_m->BCM_LvBat1_SOC & (0x03U)) << 2U) | ((_m->BCM_LvBat1_SOH & (0x03U)) << 4U) | ((_m->BCM_HighBeamAutoStatus & (0x01U)) << 6U) | ((_m->BCM_ExteriorSystemStatus & (0x01U)) << 7U) ); + cframe->Data[5] |= (uint8_t) ( (_m->BCM_LvBat1_SOC_Pct & (0x7FU)) | ((_m->BCM_TrunkLidOpenWarn_Req & (0x01U)) << 7U) ); + cframe->Data[6] |= (uint8_t) ( (_m->BCM_FuelLvl_HMI & (0x7FU)) | ((_m->BCM_SRoofManipulationWarn_Req & (0x01U)) << 7U) ); + cframe->Data[7] |= (uint8_t) ( (_m->BCM_DrvMdLim_Stat & (0x01U)) ); + + cframe->MsgId = (uint32_t) BCM_IC_Info_Msg_CANID; + cframe->DLC = (uint8_t) BCM_IC_Info_Msg_DLC; + cframe->IDE = (uint8_t) BCM_IC_Info_Msg_IDE; + return BCM_IC_Info_Msg_CANID; +} + +#else + +uint32_t Pack_BCM_IC_Info_Msg_candb(BCM_IC_Info_Msg_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_IC_Info_Msg_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->BCM_WasherFluidLevel & (0x01U)) | ((_m->BCM_LvBatCharging_Stat & (0x01U)) << 1U) | ((_m->BCM_EngStartNotif_Stat & (0x01U)) << 2U) | ((_m->BCM_PowerDoorsNotif_Stat & (0x01U)) << 3U) | ((_m->BCM_CalSteeringWhColumnReq & (0x01U)) << 4U) | ((_m->BCM_AdaptiveLghtsFailure & (0x01U)) << 5U) | ((_m->BCM_BrakeLightLeft_Status & (0x01U)) << 6U) | ((_m->BCM_BrakeLightRight_Status & (0x01U)) << 7U) ); + _d[1] |= (uint8_t) ( (_m->BCM_AllWthrLght_Fault & (0x01U)) | ((_m->BCM_LowBeamLeft_Status & (0x01U)) << 1U) | ((_m->BCM_LowBeamRight_Status & (0x01U)) << 2U) | ((_m->BCM_ReverseLightsRight_Status & (0x01U)) << 3U) | ((_m->BCM_RearLeft_FogLight_Status & (0x01U)) << 4U) | ((_m->BCM_RearRight_FogLight_Status & (0x01U)) << 5U) | ((_m->BCM_ReverseLightsLeft_Status & (0x01U)) << 6U) | ((_m->BCM_HighBeamLeft_Status & (0x01U)) << 7U) ); + _d[2] |= (uint8_t) ( (_m->BCM_HighBeamRight_Status & (0x01U)) | ((_m->BCM_PositionLight_RL_Status & (0x01U)) << 1U) | ((_m->BCM_PositionLight_RR_Status & (0x01U)) << 2U) | ((_m->BCM_DaytimeLightRight_Status & (0x01U)) << 3U) | ((_m->BCM_DaytimeLightLeft_Status & (0x01U)) << 4U) | ((_m->BCM_WarningInd & (0x01U)) << 5U) | ((_m->BCM_CorneringLightRight_Status & (0x01U)) << 6U) | ((_m->BCM_CorneringLightLeft_Status & (0x01U)) << 7U) ); + _d[3] |= (uint8_t) ( (_m->BCM_PosLightFL_status & (0x01U)) | ((_m->BCM_PosLightFR_status & (0x01U)) << 1U) | ((_m->BCM_TurnIndicatorML_Status & (0x01U)) << 2U) | ((_m->BCM_TurnIndicatorMR_Status & (0x01U)) << 3U) | ((_m->BCM_TurnIndicatorRL_Status & (0x01U)) << 4U) | ((_m->BCM_TurnIndicatorRR_Status & (0x01U)) << 5U) | ((_m->BCM_TurnIndicatorFL_Status & (0x01U)) << 6U) | ((_m->BCM_TurnIndicatorFR_Status & (0x01U)) << 7U) ); + _d[4] |= (uint8_t) ( (_m->BCM_HeadLghtLevelinglFailure & (0x01U)) | ((_m->BCM_PowerSteeringCtrlFault & (0x01U)) << 1U) | ((_m->BCM_LvBat1_SOC & (0x03U)) << 2U) | ((_m->BCM_LvBat1_SOH & (0x03U)) << 4U) | ((_m->BCM_HighBeamAutoStatus & (0x01U)) << 6U) | ((_m->BCM_ExteriorSystemStatus & (0x01U)) << 7U) ); + _d[5] |= (uint8_t) ( (_m->BCM_LvBat1_SOC_Pct & (0x7FU)) | ((_m->BCM_TrunkLidOpenWarn_Req & (0x01U)) << 7U) ); + _d[6] |= (uint8_t) ( (_m->BCM_FuelLvl_HMI & (0x7FU)) | ((_m->BCM_SRoofManipulationWarn_Req & (0x01U)) << 7U) ); + _d[7] |= (uint8_t) ( (_m->BCM_DrvMdLim_Stat & (0x01U)) ); + + *_len = (uint8_t) BCM_IC_Info_Msg_DLC; + *_ide = (uint8_t) BCM_IC_Info_Msg_IDE; + return BCM_IC_Info_Msg_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_CLIMATIC_DATA_candb(BCM_CLIMATIC_DATA_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->SolarSensRightVal_ro = (uint8_t) ( (_d[0] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SolarSensRightVal_phys = (sigfloat_t)(CANDB_SolarSensRightVal_ro_fromS(_m->SolarSensRightVal_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_WipeLowTempWarn_Req = (uint8_t) ( (_d[1] & (0x01U)) ); + _m->FrontWindowHeating_Status = (uint8_t) ( ((_d[1] >> 1U) & (0x01U)) ); + _m->RearWindowHeating_Status = (uint8_t) ( ((_d[1] >> 2U) & (0x01U)) ); + _m->SWM_Heating_Req = (uint8_t) ( ((_d[1] >> 3U) & (0x03U)) ); + _m->BCM_RearWindowHeating_Cmd = (uint8_t) ( ((_d[1] >> 5U) & (0x01U)) ); + _m->BCM_SteerWheelHeating_Stat = (uint8_t) ( ((_d[1] >> 6U) & (0x01U)) ); + _m->RainDetected = (uint8_t) ( ((_d[1] >> 7U) & (0x01U)) ); + _m->SolarSensLeftVal_ro = (uint8_t) ( (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SolarSensLeftVal_phys = (sigfloat_t)(CANDB_SolarSensLeftVal_ro_fromS(_m->SolarSensLeftVal_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SideWindowHeating_Status = (uint8_t) ( (_d[3] & (0x01U)) ); + _m->BCM_Wiper_Stat = (uint8_t) ( ((_d[3] >> 2U) & (0x01U)) ); + _m->BCM_SideWindowType_Stat = (uint8_t) ( ((_d[3] >> 3U) & (0x01U)) ); + _m->BCM_MirrorHeating_Cmd = (uint8_t) ( ((_d[3] >> 4U) & (0x01U)) ); + _m->BCM_WindowWashingSt = (uint8_t) ( ((_d[3] >> 5U) & (0x01U)) ); + _m->BCM_GloveBox_Stat = (uint8_t) ( ((_d[3] >> 6U) & (0x01U)) ); + _m->RainDensity = (uint8_t) ( ((_d[3] >> 7U) & (0x01U)) ); + _m->WindshieldTemp_ro = (uint8_t) ( (_d[4] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->WindshieldTemp_phys = (sigfloat_t)(CANDB_WindshieldTemp_ro_fromS(_m->WindshieldTemp_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->WindshieldHumidity_ro = (uint8_t) ( (_d[5] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->WindshieldHumidity_phys = (sigfloat_t)(CANDB_WindshieldHumidity_ro_fromS(_m->WindshieldHumidity_ro)); +#endif // CANDB_USE_SIGFLOAT + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < BCM_CLIMATIC_DATA_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_BCM_CLIMATIC_DATA_candb(&_m->mon1, BCM_CLIMATIC_DATA_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return BCM_CLIMATIC_DATA_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_BCM_CLIMATIC_DATA_candb(BCM_CLIMATIC_DATA_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_CLIMATIC_DATA_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->SolarSensRightVal_ro = (uint8_t) CANDB_SolarSensRightVal_ro_toS(_m->SolarSensRightVal_phys); + _m->SolarSensLeftVal_ro = (uint8_t) CANDB_SolarSensLeftVal_ro_toS(_m->SolarSensLeftVal_phys); + _m->WindshieldTemp_ro = (uint8_t) CANDB_WindshieldTemp_ro_toS(_m->WindshieldTemp_phys); + _m->WindshieldHumidity_ro = (uint8_t) CANDB_WindshieldHumidity_ro_toS(_m->WindshieldHumidity_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->SolarSensRightVal_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->BCM_WipeLowTempWarn_Req & (0x01U)) | ((_m->FrontWindowHeating_Status & (0x01U)) << 1U) | ((_m->RearWindowHeating_Status & (0x01U)) << 2U) | ((_m->SWM_Heating_Req & (0x03U)) << 3U) | ((_m->BCM_RearWindowHeating_Cmd & (0x01U)) << 5U) | ((_m->BCM_SteerWheelHeating_Stat & (0x01U)) << 6U) | ((_m->RainDetected & (0x01U)) << 7U) ); + cframe->Data[2] |= (uint8_t) ( (_m->SolarSensLeftVal_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->SideWindowHeating_Status & (0x01U)) | ((_m->BCM_Wiper_Stat & (0x01U)) << 2U) | ((_m->BCM_SideWindowType_Stat & (0x01U)) << 3U) | ((_m->BCM_MirrorHeating_Cmd & (0x01U)) << 4U) | ((_m->BCM_WindowWashingSt & (0x01U)) << 5U) | ((_m->BCM_GloveBox_Stat & (0x01U)) << 6U) | ((_m->RainDensity & (0x01U)) << 7U) ); + cframe->Data[4] |= (uint8_t) ( (_m->WindshieldTemp_ro & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->WindshieldHumidity_ro & (0xFFU)) ); + + cframe->MsgId = (uint32_t) BCM_CLIMATIC_DATA_CANID; + cframe->DLC = (uint8_t) BCM_CLIMATIC_DATA_DLC; + cframe->IDE = (uint8_t) BCM_CLIMATIC_DATA_IDE; + return BCM_CLIMATIC_DATA_CANID; +} + +#else + +uint32_t Pack_BCM_CLIMATIC_DATA_candb(BCM_CLIMATIC_DATA_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_CLIMATIC_DATA_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->SolarSensRightVal_ro = (uint8_t) CANDB_SolarSensRightVal_ro_toS(_m->SolarSensRightVal_phys); + _m->SolarSensLeftVal_ro = (uint8_t) CANDB_SolarSensLeftVal_ro_toS(_m->SolarSensLeftVal_phys); + _m->WindshieldTemp_ro = (uint8_t) CANDB_WindshieldTemp_ro_toS(_m->WindshieldTemp_phys); + _m->WindshieldHumidity_ro = (uint8_t) CANDB_WindshieldHumidity_ro_toS(_m->WindshieldHumidity_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->SolarSensRightVal_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( (_m->BCM_WipeLowTempWarn_Req & (0x01U)) | ((_m->FrontWindowHeating_Status & (0x01U)) << 1U) | ((_m->RearWindowHeating_Status & (0x01U)) << 2U) | ((_m->SWM_Heating_Req & (0x03U)) << 3U) | ((_m->BCM_RearWindowHeating_Cmd & (0x01U)) << 5U) | ((_m->BCM_SteerWheelHeating_Stat & (0x01U)) << 6U) | ((_m->RainDetected & (0x01U)) << 7U) ); + _d[2] |= (uint8_t) ( (_m->SolarSensLeftVal_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->SideWindowHeating_Status & (0x01U)) | ((_m->BCM_Wiper_Stat & (0x01U)) << 2U) | ((_m->BCM_SideWindowType_Stat & (0x01U)) << 3U) | ((_m->BCM_MirrorHeating_Cmd & (0x01U)) << 4U) | ((_m->BCM_WindowWashingSt & (0x01U)) << 5U) | ((_m->BCM_GloveBox_Stat & (0x01U)) << 6U) | ((_m->RainDensity & (0x01U)) << 7U) ); + _d[4] |= (uint8_t) ( (_m->WindshieldTemp_ro & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->WindshieldHumidity_ro & (0xFFU)) ); + + *_len = (uint8_t) BCM_CLIMATIC_DATA_DLC; + *_ide = (uint8_t) BCM_CLIMATIC_DATA_IDE; + return BCM_CLIMATIC_DATA_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_DMFL_SMFL_REQ_CTR_SEATS_candb(DMFL_SMFL_REQ_CTR_SEATS_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->DMFL_SeatMemReq = (uint8_t) ( (_d[0] & (0x07U)) ); + _m->DMFL_SeatHeightReq = (uint8_t) ( ((_d[0] >> 3U) & (0x03U)) ); + _m->DMFL_FrontPass_Req = (uint8_t) ( ((_d[0] >> 5U) & (0x01U)) ); + _m->DMFL_SeatLongitunalReq = (uint8_t) ( ((_d[0] >> 6U) & (0x03U)) ); + _m->DMFL_SeatBackRestInclinationReq = (uint8_t) ( (_d[1] & (0x03U)) ); + _m->DMFL_SeatMassageRequest = (uint8_t) ( ((_d[1] >> 2U) & (0x03U)) ); + _m->DMFL_SeatVentilationRequest = (uint8_t) ( ((_d[1] >> 4U) & (0x07U)) ); + _m->DMFL_SeatMassageIntence = (uint8_t) ( (_d[2] & (0x03U)) ); + _m->DMFL_SeatHeatingRequest = (uint8_t) ( ((_d[2] >> 2U) & (0x07U)) ); + _m->DMFL_SeatInclination_Req = (uint8_t) ( ((_d[2] >> 5U) & (0x03U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < DMFL_SMFL_REQ_CTR_SEATS_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_DMFL_SMFL_REQ_CTR_SEATS_candb(&_m->mon1, DMFL_SMFL_REQ_CTR_SEATS_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return DMFL_SMFL_REQ_CTR_SEATS_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_DMFL_SMFL_REQ_CTR_SEATS_candb(DMFL_SMFL_REQ_CTR_SEATS_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(DMFL_SMFL_REQ_CTR_SEATS_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->DMFL_SeatMemReq & (0x07U)) | ((_m->DMFL_SeatHeightReq & (0x03U)) << 3U) | ((_m->DMFL_FrontPass_Req & (0x01U)) << 5U) | ((_m->DMFL_SeatLongitunalReq & (0x03U)) << 6U) ); + cframe->Data[1] |= (uint8_t) ( (_m->DMFL_SeatBackRestInclinationReq & (0x03U)) | ((_m->DMFL_SeatMassageRequest & (0x03U)) << 2U) | ((_m->DMFL_SeatVentilationRequest & (0x07U)) << 4U) ); + cframe->Data[2] |= (uint8_t) ( (_m->DMFL_SeatMassageIntence & (0x03U)) | ((_m->DMFL_SeatHeatingRequest & (0x07U)) << 2U) | ((_m->DMFL_SeatInclination_Req & (0x03U)) << 5U) ); + + cframe->MsgId = (uint32_t) DMFL_SMFL_REQ_CTR_SEATS_CANID; + cframe->DLC = (uint8_t) DMFL_SMFL_REQ_CTR_SEATS_DLC; + cframe->IDE = (uint8_t) DMFL_SMFL_REQ_CTR_SEATS_IDE; + return DMFL_SMFL_REQ_CTR_SEATS_CANID; +} + +#else + +uint32_t Pack_DMFL_SMFL_REQ_CTR_SEATS_candb(DMFL_SMFL_REQ_CTR_SEATS_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(DMFL_SMFL_REQ_CTR_SEATS_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->DMFL_SeatMemReq & (0x07U)) | ((_m->DMFL_SeatHeightReq & (0x03U)) << 3U) | ((_m->DMFL_FrontPass_Req & (0x01U)) << 5U) | ((_m->DMFL_SeatLongitunalReq & (0x03U)) << 6U) ); + _d[1] |= (uint8_t) ( (_m->DMFL_SeatBackRestInclinationReq & (0x03U)) | ((_m->DMFL_SeatMassageRequest & (0x03U)) << 2U) | ((_m->DMFL_SeatVentilationRequest & (0x07U)) << 4U) ); + _d[2] |= (uint8_t) ( (_m->DMFL_SeatMassageIntence & (0x03U)) | ((_m->DMFL_SeatHeatingRequest & (0x07U)) << 2U) | ((_m->DMFL_SeatInclination_Req & (0x03U)) << 5U) ); + + *_len = (uint8_t) DMFL_SMFL_REQ_CTR_SEATS_DLC; + *_ide = (uint8_t) DMFL_SMFL_REQ_CTR_SEATS_IDE; + return DMFL_SMFL_REQ_CTR_SEATS_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_DMFR_SMFR_REQ_CTR_SEATS_candb(DMFR_SMFR_REQ_CTR_SEATS_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->DMFR_SeatMemReq = (uint8_t) ( (_d[0] & (0x07U)) ); + _m->DMFR_SeatHeightReq = (uint8_t) ( ((_d[0] >> 3U) & (0x03U)) ); + _m->DMFR_SeatLongitunalReq = (uint8_t) ( ((_d[0] >> 6U) & (0x03U)) ); + _m->DMFR_SeatBackRestInclinationReq = (uint8_t) ( (_d[1] & (0x03U)) ); + _m->DMFR_SeatMassageRequest = (uint8_t) ( ((_d[1] >> 2U) & (0x03U)) ); + _m->DMFR_SeatVentilationRequest = (uint8_t) ( ((_d[1] >> 4U) & (0x07U)) ); + _m->DMFR_SeatMassageIntence = (uint8_t) ( (_d[2] & (0x03U)) ); + _m->DMFR_SeatHeatingRequest = (uint8_t) ( ((_d[2] >> 2U) & (0x07U)) ); + _m->DMFR_SeatInclination_Req = (uint8_t) ( ((_d[2] >> 5U) & (0x03U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < DMFR_SMFR_REQ_CTR_SEATS_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_DMFR_SMFR_REQ_CTR_SEATS_candb(&_m->mon1, DMFR_SMFR_REQ_CTR_SEATS_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return DMFR_SMFR_REQ_CTR_SEATS_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_DMFR_SMFR_REQ_CTR_SEATS_candb(DMFR_SMFR_REQ_CTR_SEATS_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(DMFR_SMFR_REQ_CTR_SEATS_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->DMFR_SeatMemReq & (0x07U)) | ((_m->DMFR_SeatHeightReq & (0x03U)) << 3U) | ((_m->DMFR_SeatLongitunalReq & (0x03U)) << 6U) ); + cframe->Data[1] |= (uint8_t) ( (_m->DMFR_SeatBackRestInclinationReq & (0x03U)) | ((_m->DMFR_SeatMassageRequest & (0x03U)) << 2U) | ((_m->DMFR_SeatVentilationRequest & (0x07U)) << 4U) ); + cframe->Data[2] |= (uint8_t) ( (_m->DMFR_SeatMassageIntence & (0x03U)) | ((_m->DMFR_SeatHeatingRequest & (0x07U)) << 2U) | ((_m->DMFR_SeatInclination_Req & (0x03U)) << 5U) ); + + cframe->MsgId = (uint32_t) DMFR_SMFR_REQ_CTR_SEATS_CANID; + cframe->DLC = (uint8_t) DMFR_SMFR_REQ_CTR_SEATS_DLC; + cframe->IDE = (uint8_t) DMFR_SMFR_REQ_CTR_SEATS_IDE; + return DMFR_SMFR_REQ_CTR_SEATS_CANID; +} + +#else + +uint32_t Pack_DMFR_SMFR_REQ_CTR_SEATS_candb(DMFR_SMFR_REQ_CTR_SEATS_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(DMFR_SMFR_REQ_CTR_SEATS_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->DMFR_SeatMemReq & (0x07U)) | ((_m->DMFR_SeatHeightReq & (0x03U)) << 3U) | ((_m->DMFR_SeatLongitunalReq & (0x03U)) << 6U) ); + _d[1] |= (uint8_t) ( (_m->DMFR_SeatBackRestInclinationReq & (0x03U)) | ((_m->DMFR_SeatMassageRequest & (0x03U)) << 2U) | ((_m->DMFR_SeatVentilationRequest & (0x07U)) << 4U) ); + _d[2] |= (uint8_t) ( (_m->DMFR_SeatMassageIntence & (0x03U)) | ((_m->DMFR_SeatHeatingRequest & (0x07U)) << 2U) | ((_m->DMFR_SeatInclination_Req & (0x03U)) << 5U) ); + + *_len = (uint8_t) DMFR_SMFR_REQ_CTR_SEATS_DLC; + *_ide = (uint8_t) DMFR_SMFR_REQ_CTR_SEATS_IDE; + return DMFR_SMFR_REQ_CTR_SEATS_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_DMRL_SMRL_REQ_CTR_SEATS_candb(DMRL_SMRL_REQ_CTR_SEATS_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->DMRL_SeatMemReq = (uint8_t) ( (_d[0] & (0x07U)) ); + _m->DMRL_SeatHeightReq = (uint8_t) ( ((_d[0] >> 3U) & (0x03U)) ); + _m->DMRL_SeatLongitunalReq = (uint8_t) ( ((_d[0] >> 6U) & (0x03U)) ); + _m->DMRL_SeatBackRestInclinationReq = (uint8_t) ( (_d[1] & (0x03U)) ); + _m->DMRL_SeatMassageRequest = (uint8_t) ( ((_d[1] >> 2U) & (0x03U)) ); + _m->DMRL_SeatVentilationRequest = (uint8_t) ( ((_d[1] >> 4U) & (0x07U)) ); + _m->DMRL_SeatMassageIntence = (uint8_t) ( (_d[2] & (0x03U)) ); + _m->DMRL_SeatHeatingRequest = (uint8_t) ( ((_d[2] >> 2U) & (0x07U)) ); + _m->DMRL_SeatInclination_Req = (uint8_t) ( ((_d[2] >> 5U) & (0x03U)) ); + _m->DMRL_SeatFootRestHeightReq = (uint8_t) ( (_d[3] & (0x03U)) ); + _m->DMRL_MoreComfort_Req = (uint8_t) ( ((_d[3] >> 2U) & (0x03U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < DMRL_SMRL_REQ_CTR_SEATS_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_DMRL_SMRL_REQ_CTR_SEATS_candb(&_m->mon1, DMRL_SMRL_REQ_CTR_SEATS_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return DMRL_SMRL_REQ_CTR_SEATS_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_DMRL_SMRL_REQ_CTR_SEATS_candb(DMRL_SMRL_REQ_CTR_SEATS_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(DMRL_SMRL_REQ_CTR_SEATS_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->DMRL_SeatMemReq & (0x07U)) | ((_m->DMRL_SeatHeightReq & (0x03U)) << 3U) | ((_m->DMRL_SeatLongitunalReq & (0x03U)) << 6U) ); + cframe->Data[1] |= (uint8_t) ( (_m->DMRL_SeatBackRestInclinationReq & (0x03U)) | ((_m->DMRL_SeatMassageRequest & (0x03U)) << 2U) | ((_m->DMRL_SeatVentilationRequest & (0x07U)) << 4U) ); + cframe->Data[2] |= (uint8_t) ( (_m->DMRL_SeatMassageIntence & (0x03U)) | ((_m->DMRL_SeatHeatingRequest & (0x07U)) << 2U) | ((_m->DMRL_SeatInclination_Req & (0x03U)) << 5U) ); + cframe->Data[3] |= (uint8_t) ( (_m->DMRL_SeatFootRestHeightReq & (0x03U)) | ((_m->DMRL_MoreComfort_Req & (0x03U)) << 2U) ); + + cframe->MsgId = (uint32_t) DMRL_SMRL_REQ_CTR_SEATS_CANID; + cframe->DLC = (uint8_t) DMRL_SMRL_REQ_CTR_SEATS_DLC; + cframe->IDE = (uint8_t) DMRL_SMRL_REQ_CTR_SEATS_IDE; + return DMRL_SMRL_REQ_CTR_SEATS_CANID; +} + +#else + +uint32_t Pack_DMRL_SMRL_REQ_CTR_SEATS_candb(DMRL_SMRL_REQ_CTR_SEATS_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(DMRL_SMRL_REQ_CTR_SEATS_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->DMRL_SeatMemReq & (0x07U)) | ((_m->DMRL_SeatHeightReq & (0x03U)) << 3U) | ((_m->DMRL_SeatLongitunalReq & (0x03U)) << 6U) ); + _d[1] |= (uint8_t) ( (_m->DMRL_SeatBackRestInclinationReq & (0x03U)) | ((_m->DMRL_SeatMassageRequest & (0x03U)) << 2U) | ((_m->DMRL_SeatVentilationRequest & (0x07U)) << 4U) ); + _d[2] |= (uint8_t) ( (_m->DMRL_SeatMassageIntence & (0x03U)) | ((_m->DMRL_SeatHeatingRequest & (0x07U)) << 2U) | ((_m->DMRL_SeatInclination_Req & (0x03U)) << 5U) ); + _d[3] |= (uint8_t) ( (_m->DMRL_SeatFootRestHeightReq & (0x03U)) | ((_m->DMRL_MoreComfort_Req & (0x03U)) << 2U) ); + + *_len = (uint8_t) DMRL_SMRL_REQ_CTR_SEATS_DLC; + *_ide = (uint8_t) DMRL_SMRL_REQ_CTR_SEATS_IDE; + return DMRL_SMRL_REQ_CTR_SEATS_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_DMRR_SMRR_REQ_CTR_SEATS_candb(DMRR_SMRR_REQ_CTR_SEATS_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->DMRR_SeatMemReq = (uint8_t) ( (_d[0] & (0x07U)) ); + _m->DMRR_SeatHeightReq = (uint8_t) ( ((_d[0] >> 3U) & (0x03U)) ); + _m->DMRR_FrontPass_Req = (uint8_t) ( ((_d[0] >> 5U) & (0x01U)) ); + _m->DMRR_SeatLongitunalReq = (uint8_t) ( ((_d[0] >> 6U) & (0x03U)) ); + _m->DMRR_SeatBackRestInclinationReq = (uint8_t) ( (_d[1] & (0x03U)) ); + _m->DMRR_SeatMassageRequest = (uint8_t) ( ((_d[1] >> 2U) & (0x03U)) ); + _m->DMRR_SeatVentilationRequest = (uint8_t) ( ((_d[1] >> 4U) & (0x07U)) ); + _m->DMRR_SeatMassageIntence = (uint8_t) ( (_d[2] & (0x03U)) ); + _m->DMRR_SeatHeatingRequest = (uint8_t) ( ((_d[2] >> 2U) & (0x07U)) ); + _m->DMRR_SeatInclination_Req = (uint8_t) ( ((_d[2] >> 5U) & (0x03U)) ); + _m->DMRR_SeatFootRestHeightReq = (uint8_t) ( (_d[3] & (0x03U)) ); + _m->DMRR_MoreComfort_Req = (uint8_t) ( ((_d[3] >> 2U) & (0x03U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < DMRR_SMRR_REQ_CTR_SEATS_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_DMRR_SMRR_REQ_CTR_SEATS_candb(&_m->mon1, DMRR_SMRR_REQ_CTR_SEATS_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return DMRR_SMRR_REQ_CTR_SEATS_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_DMRR_SMRR_REQ_CTR_SEATS_candb(DMRR_SMRR_REQ_CTR_SEATS_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(DMRR_SMRR_REQ_CTR_SEATS_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->DMRR_SeatMemReq & (0x07U)) | ((_m->DMRR_SeatHeightReq & (0x03U)) << 3U) | ((_m->DMRR_FrontPass_Req & (0x01U)) << 5U) | ((_m->DMRR_SeatLongitunalReq & (0x03U)) << 6U) ); + cframe->Data[1] |= (uint8_t) ( (_m->DMRR_SeatBackRestInclinationReq & (0x03U)) | ((_m->DMRR_SeatMassageRequest & (0x03U)) << 2U) | ((_m->DMRR_SeatVentilationRequest & (0x07U)) << 4U) ); + cframe->Data[2] |= (uint8_t) ( (_m->DMRR_SeatMassageIntence & (0x03U)) | ((_m->DMRR_SeatHeatingRequest & (0x07U)) << 2U) | ((_m->DMRR_SeatInclination_Req & (0x03U)) << 5U) ); + cframe->Data[3] |= (uint8_t) ( (_m->DMRR_SeatFootRestHeightReq & (0x03U)) | ((_m->DMRR_MoreComfort_Req & (0x03U)) << 2U) ); + + cframe->MsgId = (uint32_t) DMRR_SMRR_REQ_CTR_SEATS_CANID; + cframe->DLC = (uint8_t) DMRR_SMRR_REQ_CTR_SEATS_DLC; + cframe->IDE = (uint8_t) DMRR_SMRR_REQ_CTR_SEATS_IDE; + return DMRR_SMRR_REQ_CTR_SEATS_CANID; +} + +#else + +uint32_t Pack_DMRR_SMRR_REQ_CTR_SEATS_candb(DMRR_SMRR_REQ_CTR_SEATS_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(DMRR_SMRR_REQ_CTR_SEATS_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->DMRR_SeatMemReq & (0x07U)) | ((_m->DMRR_SeatHeightReq & (0x03U)) << 3U) | ((_m->DMRR_FrontPass_Req & (0x01U)) << 5U) | ((_m->DMRR_SeatLongitunalReq & (0x03U)) << 6U) ); + _d[1] |= (uint8_t) ( (_m->DMRR_SeatBackRestInclinationReq & (0x03U)) | ((_m->DMRR_SeatMassageRequest & (0x03U)) << 2U) | ((_m->DMRR_SeatVentilationRequest & (0x07U)) << 4U) ); + _d[2] |= (uint8_t) ( (_m->DMRR_SeatMassageIntence & (0x03U)) | ((_m->DMRR_SeatHeatingRequest & (0x07U)) << 2U) | ((_m->DMRR_SeatInclination_Req & (0x03U)) << 5U) ); + _d[3] |= (uint8_t) ( (_m->DMRR_SeatFootRestHeightReq & (0x03U)) | ((_m->DMRR_MoreComfort_Req & (0x03U)) << 2U) ); + + *_len = (uint8_t) DMRR_SMRR_REQ_CTR_SEATS_DLC; + *_ide = (uint8_t) DMRR_SMRR_REQ_CTR_SEATS_IDE; + return DMRR_SMRR_REQ_CTR_SEATS_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_CCU_Msg1_candb(CCU_Msg1_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->CCU_MirrorHeating_Req = (uint8_t) ( (_d[0] & (0x03U)) ); + _m->CCU_RecirculationLed_Cmd = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + _m->CCU_DefrostLed_Req = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + _m->CCU_SideWindowHeating_Req = (uint8_t) ( ((_d[0] >> 4U) & (0x03U)) ); + _m->CCU_RearWindowHeating_Req = (uint8_t) ( ((_d[0] >> 6U) & (0x03U)) ); + _m->CCU_FrontWindowHeating_Req = (uint8_t) ( (_d[1] & (0x03U)) ); + _m->CCU_EmergAirCleaning_Stat = (uint8_t) ( ((_d[1] >> 2U) & (0x01U)) ); + _m->CCU_FireExtinguishSys_Stat = (uint8_t) ( ((_d[1] >> 3U) & (0x01U)) ); + _m->CCU_FLAutoPsngrLed_Cmd = (uint8_t) ( (_d[3] & (0x01U)) ); + _m->CCU_FRAutoPsngrLed_Cmd = (uint8_t) ( ((_d[3] >> 1U) & (0x01U)) ); + _m->CCU_RLAutoPsngrLed_Cmd = (uint8_t) ( ((_d[3] >> 2U) & (0x01U)) ); + _m->CCU_RRAutoPsngrLed_Cmd = (uint8_t) ( ((_d[3] >> 3U) & (0x01U)) ); + _m->CCU_AC_MaxLed_Cmd = (uint8_t) ( ((_d[3] >> 4U) & (0x01U)) ); + _m->CCU_MSG1_RC = (uint8_t) ( ((_d[6] >> 4U) & (0x0FU)) ); + _m->CCU_MSG1_CS = (uint8_t) ( (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < CCU_Msg1_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_CCU_Msg1_candb(&_m->mon1, CCU_Msg1_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return CCU_Msg1_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_CCU_Msg1_candb(CCU_Msg1_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(CCU_Msg1_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->CCU_MirrorHeating_Req & (0x03U)) | ((_m->CCU_RecirculationLed_Cmd & (0x01U)) << 2U) | ((_m->CCU_DefrostLed_Req & (0x01U)) << 3U) | ((_m->CCU_SideWindowHeating_Req & (0x03U)) << 4U) | ((_m->CCU_RearWindowHeating_Req & (0x03U)) << 6U) ); + cframe->Data[1] |= (uint8_t) ( (_m->CCU_FrontWindowHeating_Req & (0x03U)) | ((_m->CCU_EmergAirCleaning_Stat & (0x01U)) << 2U) | ((_m->CCU_FireExtinguishSys_Stat & (0x01U)) << 3U) ); + cframe->Data[3] |= (uint8_t) ( (_m->CCU_FLAutoPsngrLed_Cmd & (0x01U)) | ((_m->CCU_FRAutoPsngrLed_Cmd & (0x01U)) << 1U) | ((_m->CCU_RLAutoPsngrLed_Cmd & (0x01U)) << 2U) | ((_m->CCU_RRAutoPsngrLed_Cmd & (0x01U)) << 3U) | ((_m->CCU_AC_MaxLed_Cmd & (0x01U)) << 4U) ); + cframe->Data[6] |= (uint8_t) ( ((_m->CCU_MSG1_RC & (0x0FU)) << 4U) ); + cframe->Data[7] |= (uint8_t) ( (_m->CCU_MSG1_CS & (0xFFU)) ); + + cframe->MsgId = (uint32_t) CCU_Msg1_CANID; + cframe->DLC = (uint8_t) CCU_Msg1_DLC; + cframe->IDE = (uint8_t) CCU_Msg1_IDE; + return CCU_Msg1_CANID; +} + +#else + +uint32_t Pack_CCU_Msg1_candb(CCU_Msg1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(CCU_Msg1_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->CCU_MirrorHeating_Req & (0x03U)) | ((_m->CCU_RecirculationLed_Cmd & (0x01U)) << 2U) | ((_m->CCU_DefrostLed_Req & (0x01U)) << 3U) | ((_m->CCU_SideWindowHeating_Req & (0x03U)) << 4U) | ((_m->CCU_RearWindowHeating_Req & (0x03U)) << 6U) ); + _d[1] |= (uint8_t) ( (_m->CCU_FrontWindowHeating_Req & (0x03U)) | ((_m->CCU_EmergAirCleaning_Stat & (0x01U)) << 2U) | ((_m->CCU_FireExtinguishSys_Stat & (0x01U)) << 3U) ); + _d[3] |= (uint8_t) ( (_m->CCU_FLAutoPsngrLed_Cmd & (0x01U)) | ((_m->CCU_FRAutoPsngrLed_Cmd & (0x01U)) << 1U) | ((_m->CCU_RLAutoPsngrLed_Cmd & (0x01U)) << 2U) | ((_m->CCU_RRAutoPsngrLed_Cmd & (0x01U)) << 3U) | ((_m->CCU_AC_MaxLed_Cmd & (0x01U)) << 4U) ); + _d[6] |= (uint8_t) ( ((_m->CCU_MSG1_RC & (0x0FU)) << 4U) ); + _d[7] |= (uint8_t) ( (_m->CCU_MSG1_CS & (0xFFU)) ); + + *_len = (uint8_t) CCU_Msg1_DLC; + *_ide = (uint8_t) CCU_Msg1_IDE; + return CCU_Msg1_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Sroof_State_candb(Sroof_State_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Sroof_Movement_Stat = (uint8_t) ( (_d[0] & (0x03U)) ); + _m->Sroof_Position_Stat = (uint8_t) ( ((_d[0] >> 2U) & (0x03U)) ); + _m->Sroof_Antipinch_Stat = (uint8_t) ( ((_d[0] >> 4U) & (0x01U)) ); + _m->Sroof_Error_Stat = (uint8_t) ( ((_d[0] >> 5U) & (0x01U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Sroof_State_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Sroof_State_candb(&_m->mon1, Sroof_State_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Sroof_State_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Sroof_State_candb(Sroof_State_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Sroof_State_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->Sroof_Movement_Stat & (0x03U)) | ((_m->Sroof_Position_Stat & (0x03U)) << 2U) | ((_m->Sroof_Antipinch_Stat & (0x01U)) << 4U) | ((_m->Sroof_Error_Stat & (0x01U)) << 5U) ); + + cframe->MsgId = (uint32_t) Sroof_State_CANID; + cframe->DLC = (uint8_t) Sroof_State_DLC; + cframe->IDE = (uint8_t) Sroof_State_IDE; + return Sroof_State_CANID; +} + +#else + +uint32_t Pack_Sroof_State_candb(Sroof_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Sroof_State_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->Sroof_Movement_Stat & (0x03U)) | ((_m->Sroof_Position_Stat & (0x03U)) << 2U) | ((_m->Sroof_Antipinch_Stat & (0x01U)) << 4U) | ((_m->Sroof_Error_Stat & (0x01U)) << 5U) ); + + *_len = (uint8_t) Sroof_State_DLC; + *_ide = (uint8_t) Sroof_State_IDE; + return Sroof_State_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_VCU_CCU_Req_candb(VCU_CCU_Req_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->VCU_eTXV_batChiller_Pos_Req = (uint8_t) ( (_d[0] & (0x7FU)) ); + _m->VCU_eTXV_eeChiller_Pos_Req = (uint8_t) ( (_d[1] & (0x7FU)) ); + _m->VCU_LiquidHeaterCurrentTemp_Stat_ro = (uint8_t) ( (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->VCU_LiquidHeaterCurrentTemp_Stat_phys = (sigfloat_t)(CANDB_VCU_LiquidHeaterCurrentTemp_Stat_ro_fromS(_m->VCU_LiquidHeaterCurrentTemp_Stat_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->VCU_CCU_Req_RC = (uint8_t) ( (_d[3] & (0x0FU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < VCU_CCU_Req_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_VCU_CCU_Req_candb(&_m->mon1, VCU_CCU_Req_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return VCU_CCU_Req_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_VCU_CCU_Req_candb(VCU_CCU_Req_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(VCU_CCU_Req_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->VCU_LiquidHeaterCurrentTemp_Stat_ro = (uint8_t) CANDB_VCU_LiquidHeaterCurrentTemp_Stat_ro_toS(_m->VCU_LiquidHeaterCurrentTemp_Stat_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->VCU_eTXV_batChiller_Pos_Req & (0x7FU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->VCU_eTXV_eeChiller_Pos_Req & (0x7FU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->VCU_LiquidHeaterCurrentTemp_Stat_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->VCU_CCU_Req_RC & (0x0FU)) ); + + cframe->MsgId = (uint32_t) VCU_CCU_Req_CANID; + cframe->DLC = (uint8_t) VCU_CCU_Req_DLC; + cframe->IDE = (uint8_t) VCU_CCU_Req_IDE; + return VCU_CCU_Req_CANID; +} + +#else + +uint32_t Pack_VCU_CCU_Req_candb(VCU_CCU_Req_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(VCU_CCU_Req_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->VCU_LiquidHeaterCurrentTemp_Stat_ro = (uint8_t) CANDB_VCU_LiquidHeaterCurrentTemp_Stat_ro_toS(_m->VCU_LiquidHeaterCurrentTemp_Stat_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->VCU_eTXV_batChiller_Pos_Req & (0x7FU)) ); + _d[1] |= (uint8_t) ( (_m->VCU_eTXV_eeChiller_Pos_Req & (0x7FU)) ); + _d[2] |= (uint8_t) ( (_m->VCU_LiquidHeaterCurrentTemp_Stat_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->VCU_CCU_Req_RC & (0x0FU)) ); + + *_len = (uint8_t) VCU_CCU_Req_DLC; + *_ide = (uint8_t) VCU_CCU_Req_IDE; + return VCU_CCU_Req_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_IC_DATA_MSG_candb(IC_DATA_MSG_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->DisplayBacklightBrightness = (uint8_t) ( (_d[0] & (0x7FU)) ); + _m->IC_EstimatedCruiseRange_ro = (uint8_t) ( (_d[1] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->IC_EstimatedCruiseRange_phys = (uint16_t) CANDB_IC_EstimatedCruiseRange_ro_fromS(_m->IC_EstimatedCruiseRange_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->IC_ServiceDate = (int16_t) __ext_sig__(( ((_d[3] & (0xFFU)) << 8U) | (_d[2] & (0xFFU)) ), 16); + _m->IC_ServiceMileage = (int32_t) __ext_sig__(( ((_d[6] & (0x0FU)) << 16U) | ((_d[5] & (0xFFU)) << 8U) | (_d[4] & (0xFFU)) ), 20); + _m->IC_BrakePadCondition_Stat = (uint8_t) ( ((_d[6] >> 6U) & (0x01U)) ); + _m->IC_BrakeLiquidLvl_Stat = (uint8_t) ( ((_d[6] >> 7U) & (0x01U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < IC_DATA_MSG_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_IC_DATA_MSG_candb(&_m->mon1, IC_DATA_MSG_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return IC_DATA_MSG_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_IC_DATA_MSG_candb(IC_DATA_MSG_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(IC_DATA_MSG_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->IC_EstimatedCruiseRange_ro = (uint8_t) CANDB_IC_EstimatedCruiseRange_ro_toS(_m->IC_EstimatedCruiseRange_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->DisplayBacklightBrightness & (0x7FU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->IC_EstimatedCruiseRange_ro & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->IC_ServiceDate & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->IC_ServiceDate >> 8U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->IC_ServiceMileage & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->IC_ServiceMileage >> 8U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->IC_ServiceMileage >> 16U) & (0x0FU)) | ((_m->IC_BrakePadCondition_Stat & (0x01U)) << 6U) | ((_m->IC_BrakeLiquidLvl_Stat & (0x01U)) << 7U) ); + + cframe->MsgId = (uint32_t) IC_DATA_MSG_CANID; + cframe->DLC = (uint8_t) IC_DATA_MSG_DLC; + cframe->IDE = (uint8_t) IC_DATA_MSG_IDE; + return IC_DATA_MSG_CANID; +} + +#else + +uint32_t Pack_IC_DATA_MSG_candb(IC_DATA_MSG_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(IC_DATA_MSG_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->IC_EstimatedCruiseRange_ro = (uint8_t) CANDB_IC_EstimatedCruiseRange_ro_toS(_m->IC_EstimatedCruiseRange_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->DisplayBacklightBrightness & (0x7FU)) ); + _d[1] |= (uint8_t) ( (_m->IC_EstimatedCruiseRange_ro & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->IC_ServiceDate & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->IC_ServiceDate >> 8U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->IC_ServiceMileage & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->IC_ServiceMileage >> 8U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->IC_ServiceMileage >> 16U) & (0x0FU)) | ((_m->IC_BrakePadCondition_Stat & (0x01U)) << 6U) | ((_m->IC_BrakeLiquidLvl_Stat & (0x01U)) << 7U) ); + + *_len = (uint8_t) IC_DATA_MSG_DLC; + *_ide = (uint8_t) IC_DATA_MSG_IDE; + return IC_DATA_MSG_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_ESC_08_candb(ESC_08_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->ESC_Mileage_Val_ro = (uint32_t) ( ((_d[3] & (0x07U)) << 24U) | ((_d[2] & (0xFFU)) << 16U) | ((_d[1] & (0xFFU)) << 8U) | (_d[0] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->ESC_Mileage_Val_phys = (sigfloat_t)(CANDB_ESC_Mileage_Val_ro_fromS(_m->ESC_Mileage_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->ESC_08_RC = (uint8_t) ( ((_d[3] >> 4U) & (0x0FU)) ); + _m->ESC_08_CS = (uint8_t) ( (_d[4] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < ESC_08_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_ESC_08_candb(&_m->mon1, ESC_08_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return ESC_08_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_ESC_08_candb(ESC_08_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(ESC_08_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->ESC_Mileage_Val_ro = (uint32_t) CANDB_ESC_Mileage_Val_ro_toS(_m->ESC_Mileage_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->ESC_Mileage_Val_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->ESC_Mileage_Val_ro >> 8U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->ESC_Mileage_Val_ro >> 16U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->ESC_Mileage_Val_ro >> 24U) & (0x07U)) | ((_m->ESC_08_RC & (0x0FU)) << 4U) ); + cframe->Data[4] |= (uint8_t) ( (_m->ESC_08_CS & (0xFFU)) ); + + cframe->MsgId = (uint32_t) ESC_08_CANID; + cframe->DLC = (uint8_t) ESC_08_DLC; + cframe->IDE = (uint8_t) ESC_08_IDE; + return ESC_08_CANID; +} + +#else + +uint32_t Pack_ESC_08_candb(ESC_08_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(ESC_08_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->ESC_Mileage_Val_ro = (uint32_t) CANDB_ESC_Mileage_Val_ro_toS(_m->ESC_Mileage_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->ESC_Mileage_Val_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->ESC_Mileage_Val_ro >> 8U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->ESC_Mileage_Val_ro >> 16U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->ESC_Mileage_Val_ro >> 24U) & (0x07U)) | ((_m->ESC_08_RC & (0x0FU)) << 4U) ); + _d[4] |= (uint8_t) ( (_m->ESC_08_CS & (0xFFU)) ); + + *_len = (uint8_t) ESC_08_DLC; + *_ide = (uint8_t) ESC_08_IDE; + return ESC_08_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_WChF_Status_candb(WChF_Status_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->WChF_Status_Stat = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->WChF_Charge_Stat = (uint8_t) ( ((_d[0] >> 1U) & (0x01U)) ); + _m->WChF_ShortCircuit5V_Stat = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + _m->WChF_Comm_Stat = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + _m->WChF_Malfunction_Stat = (uint8_t) ( ((_d[0] >> 4U) & (0x01U)) ); + _m->WChF_NFCDevice_Stat = (uint8_t) ( ((_d[0] >> 5U) & (0x07U)) ); + _m->WChF_PowerQI_Stat_ro = (uint8_t) ( (_d[1] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->WChF_PowerQI_Stat_phys = (sigfloat_t)(CANDB_WChF_PowerQI_Stat_ro_fromS(_m->WChF_PowerQI_Stat_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->WChF_CurrentTx_Stat_ro = (uint8_t) ( (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->WChF_CurrentTx_Stat_phys = (sigfloat_t)(CANDB_WChF_CurrentTx_Stat_ro_fromS(_m->WChF_CurrentTx_Stat_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->WChF_Frequency_Stat = (uint8_t) ( (_d[3] & (0xFFU)) ); + _m->WChF_TempCoil_Stat_ro = (uint8_t) ( (_d[4] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->WChF_TempCoil_Stat_phys = (int16_t) CANDB_WChF_TempCoil_Stat_ro_fromS(_m->WChF_TempCoil_Stat_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->WChF_FAN_RPM_Stat = (uint16_t) ( ((_d[6] & (0x3FU)) << 8U) | (_d[5] & (0xFFU)) ); + _m->WChF_BT_Stat = (uint8_t) ( ((_d[6] >> 6U) & (0x01U)) ); + _m->WChF_WiFi_Stat = (uint8_t) ( ((_d[6] >> 7U) & (0x01U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < WChF_Status_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_WChF_Status_candb(&_m->mon1, WChF_Status_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return WChF_Status_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_WChF_Status_candb(WChF_Status_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(WChF_Status_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->WChF_PowerQI_Stat_ro = (uint8_t) CANDB_WChF_PowerQI_Stat_ro_toS(_m->WChF_PowerQI_Stat_phys); + _m->WChF_CurrentTx_Stat_ro = (uint8_t) CANDB_WChF_CurrentTx_Stat_ro_toS(_m->WChF_CurrentTx_Stat_phys); + _m->WChF_TempCoil_Stat_ro = (uint8_t) CANDB_WChF_TempCoil_Stat_ro_toS(_m->WChF_TempCoil_Stat_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->WChF_Status_Stat & (0x01U)) | ((_m->WChF_Charge_Stat & (0x01U)) << 1U) | ((_m->WChF_ShortCircuit5V_Stat & (0x01U)) << 2U) | ((_m->WChF_Comm_Stat & (0x01U)) << 3U) | ((_m->WChF_Malfunction_Stat & (0x01U)) << 4U) | ((_m->WChF_NFCDevice_Stat & (0x07U)) << 5U) ); + cframe->Data[1] |= (uint8_t) ( (_m->WChF_PowerQI_Stat_ro & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->WChF_CurrentTx_Stat_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->WChF_Frequency_Stat & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->WChF_TempCoil_Stat_ro & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->WChF_FAN_RPM_Stat & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->WChF_FAN_RPM_Stat >> 8U) & (0x3FU)) | ((_m->WChF_BT_Stat & (0x01U)) << 6U) | ((_m->WChF_WiFi_Stat & (0x01U)) << 7U) ); + + cframe->MsgId = (uint32_t) WChF_Status_CANID; + cframe->DLC = (uint8_t) WChF_Status_DLC; + cframe->IDE = (uint8_t) WChF_Status_IDE; + return WChF_Status_CANID; +} + +#else + +uint32_t Pack_WChF_Status_candb(WChF_Status_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(WChF_Status_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->WChF_PowerQI_Stat_ro = (uint8_t) CANDB_WChF_PowerQI_Stat_ro_toS(_m->WChF_PowerQI_Stat_phys); + _m->WChF_CurrentTx_Stat_ro = (uint8_t) CANDB_WChF_CurrentTx_Stat_ro_toS(_m->WChF_CurrentTx_Stat_phys); + _m->WChF_TempCoil_Stat_ro = (uint8_t) CANDB_WChF_TempCoil_Stat_ro_toS(_m->WChF_TempCoil_Stat_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->WChF_Status_Stat & (0x01U)) | ((_m->WChF_Charge_Stat & (0x01U)) << 1U) | ((_m->WChF_ShortCircuit5V_Stat & (0x01U)) << 2U) | ((_m->WChF_Comm_Stat & (0x01U)) << 3U) | ((_m->WChF_Malfunction_Stat & (0x01U)) << 4U) | ((_m->WChF_NFCDevice_Stat & (0x07U)) << 5U) ); + _d[1] |= (uint8_t) ( (_m->WChF_PowerQI_Stat_ro & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->WChF_CurrentTx_Stat_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->WChF_Frequency_Stat & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->WChF_TempCoil_Stat_ro & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->WChF_FAN_RPM_Stat & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->WChF_FAN_RPM_Stat >> 8U) & (0x3FU)) | ((_m->WChF_BT_Stat & (0x01U)) << 6U) | ((_m->WChF_WiFi_Stat & (0x01U)) << 7U) ); + + *_len = (uint8_t) WChF_Status_DLC; + *_ide = (uint8_t) WChF_Status_IDE; + return WChF_Status_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_MAS_Status_candb(MAS_Status_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->MAS_AVMNarrowMode_Stat = (uint8_t) ( ((_d[0] >> 1U) & (0x03U)) ); + _m->MAS_AVMUltraSonic_Stat = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + _m->MAS_AVMCameraFront_Stat = (uint8_t) ( ((_d[0] >> 4U) & (0x01U)) ); + _m->MAS_AVMCameraRear_Stat = (uint8_t) ( ((_d[0] >> 5U) & (0x01U)) ); + _m->MAS_AVMCameraLeftSide_Stat = (uint8_t) ( ((_d[0] >> 6U) & (0x01U)) ); + _m->MAS_AVMCameraRightSide_Stat = (uint8_t) ( ((_d[0] >> 7U) & (0x01U)) ); + _m->MAS_View_Stat = (uint8_t) ( (_d[1] & (0x07U)) ); + _m->MAS_Calibration_Stat = (uint8_t) ( ((_d[1] >> 3U) & (0x01U)) ); + _m->MAS_AVMUltrasonicFront_Stat = (uint8_t) ( ((_d[1] >> 4U) & (0x03U)) ); + _m->MAS_AVMUltrasonicRear_Stat = (uint8_t) ( ((_d[1] >> 6U) & (0x03U)) ); + _m->MAS_AVMUltrasonicSide_Stat = (uint8_t) ( (_d[2] & (0x03U)) ); + _m->MAS_MASmode_Stat = (uint8_t) ( ((_d[2] >> 2U) & (0x07U)) ); + _m->MAS_APAMode_Stat = (uint8_t) ( ((_d[2] >> 5U) & (0x07U)) ); + _m->MAS_AVMAutoAct_Stat = (uint8_t) ( (_d[3] & (0x01U)) ); + _m->MAS_APAManeuverSuccess_Stat = (uint8_t) ( ((_d[3] >> 1U) & (0x01U)) ); + _m->MAS_ParkingOutAvailable_Stat = (uint8_t) ( ((_d[3] >> 2U) & (0x01U)) ); + _m->MAS_ParkingOutSuccess_Stat = (uint8_t) ( ((_d[3] >> 3U) & (0x01U)) ); + _m->MAS_Status_RC = (uint8_t) ( ((_d[3] >> 4U) & (0x0FU)) ); + _m->MAS_Status_CS = (uint8_t) ( (_d[4] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < MAS_Status_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_MAS_Status_candb(&_m->mon1, MAS_Status_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return MAS_Status_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_MAS_Status_candb(MAS_Status_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(MAS_Status_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->MAS_AVMNarrowMode_Stat & (0x03U)) << 1U) | ((_m->MAS_AVMUltraSonic_Stat & (0x01U)) << 3U) | ((_m->MAS_AVMCameraFront_Stat & (0x01U)) << 4U) | ((_m->MAS_AVMCameraRear_Stat & (0x01U)) << 5U) | ((_m->MAS_AVMCameraLeftSide_Stat & (0x01U)) << 6U) | ((_m->MAS_AVMCameraRightSide_Stat & (0x01U)) << 7U) ); + cframe->Data[1] |= (uint8_t) ( (_m->MAS_View_Stat & (0x07U)) | ((_m->MAS_Calibration_Stat & (0x01U)) << 3U) | ((_m->MAS_AVMUltrasonicFront_Stat & (0x03U)) << 4U) | ((_m->MAS_AVMUltrasonicRear_Stat & (0x03U)) << 6U) ); + cframe->Data[2] |= (uint8_t) ( (_m->MAS_AVMUltrasonicSide_Stat & (0x03U)) | ((_m->MAS_MASmode_Stat & (0x07U)) << 2U) | ((_m->MAS_APAMode_Stat & (0x07U)) << 5U) ); + cframe->Data[3] |= (uint8_t) ( (_m->MAS_AVMAutoAct_Stat & (0x01U)) | ((_m->MAS_APAManeuverSuccess_Stat & (0x01U)) << 1U) | ((_m->MAS_ParkingOutAvailable_Stat & (0x01U)) << 2U) | ((_m->MAS_ParkingOutSuccess_Stat & (0x01U)) << 3U) | ((_m->MAS_Status_RC & (0x0FU)) << 4U) ); + cframe->Data[4] |= (uint8_t) ( (_m->MAS_Status_CS & (0xFFU)) ); + + cframe->MsgId = (uint32_t) MAS_Status_CANID; + cframe->DLC = (uint8_t) MAS_Status_DLC; + cframe->IDE = (uint8_t) MAS_Status_IDE; + return MAS_Status_CANID; +} + +#else + +uint32_t Pack_MAS_Status_candb(MAS_Status_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(MAS_Status_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->MAS_AVMNarrowMode_Stat & (0x03U)) << 1U) | ((_m->MAS_AVMUltraSonic_Stat & (0x01U)) << 3U) | ((_m->MAS_AVMCameraFront_Stat & (0x01U)) << 4U) | ((_m->MAS_AVMCameraRear_Stat & (0x01U)) << 5U) | ((_m->MAS_AVMCameraLeftSide_Stat & (0x01U)) << 6U) | ((_m->MAS_AVMCameraRightSide_Stat & (0x01U)) << 7U) ); + _d[1] |= (uint8_t) ( (_m->MAS_View_Stat & (0x07U)) | ((_m->MAS_Calibration_Stat & (0x01U)) << 3U) | ((_m->MAS_AVMUltrasonicFront_Stat & (0x03U)) << 4U) | ((_m->MAS_AVMUltrasonicRear_Stat & (0x03U)) << 6U) ); + _d[2] |= (uint8_t) ( (_m->MAS_AVMUltrasonicSide_Stat & (0x03U)) | ((_m->MAS_MASmode_Stat & (0x07U)) << 2U) | ((_m->MAS_APAMode_Stat & (0x07U)) << 5U) ); + _d[3] |= (uint8_t) ( (_m->MAS_AVMAutoAct_Stat & (0x01U)) | ((_m->MAS_APAManeuverSuccess_Stat & (0x01U)) << 1U) | ((_m->MAS_ParkingOutAvailable_Stat & (0x01U)) << 2U) | ((_m->MAS_ParkingOutSuccess_Stat & (0x01U)) << 3U) | ((_m->MAS_Status_RC & (0x0FU)) << 4U) ); + _d[4] |= (uint8_t) ( (_m->MAS_Status_CS & (0xFFU)) ); + + *_len = (uint8_t) MAS_Status_DLC; + *_ide = (uint8_t) MAS_Status_IDE; + return MAS_Status_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_EPB_VM_MSG_candb(EPB_VM_MSG_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->EPB_OpMode_Req = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->EPB_VM_RC = (uint8_t) ( ((_d[6] >> 4U) & (0x0FU)) ); + _m->EPB_VM_CS = (uint8_t) ( (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < EPB_VM_MSG_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_EPB_VM_MSG_candb(&_m->mon1, EPB_VM_MSG_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return EPB_VM_MSG_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_EPB_VM_MSG_candb(EPB_VM_MSG_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(EPB_VM_MSG_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->EPB_OpMode_Req & (0x01U)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->EPB_VM_RC & (0x0FU)) << 4U) ); + cframe->Data[7] |= (uint8_t) ( (_m->EPB_VM_CS & (0xFFU)) ); + + cframe->MsgId = (uint32_t) EPB_VM_MSG_CANID; + cframe->DLC = (uint8_t) EPB_VM_MSG_DLC; + cframe->IDE = (uint8_t) EPB_VM_MSG_IDE; + return EPB_VM_MSG_CANID; +} + +#else + +uint32_t Pack_EPB_VM_MSG_candb(EPB_VM_MSG_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(EPB_VM_MSG_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->EPB_OpMode_Req & (0x01U)) ); + _d[6] |= (uint8_t) ( ((_m->EPB_VM_RC & (0x0FU)) << 4U) ); + _d[7] |= (uint8_t) ( (_m->EPB_VM_CS & (0xFFU)) ); + + *_len = (uint8_t) EPB_VM_MSG_DLC; + *_ide = (uint8_t) EPB_VM_MSG_IDE; + return EPB_VM_MSG_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_CGW_COMM_REQ_candb(CGW_COMM_REQ_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->CGW_Comm_Req = (uint8_t) ( (_d[0] & (0x01U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < CGW_COMM_REQ_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_CGW_COMM_REQ_candb(&_m->mon1, CGW_COMM_REQ_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return CGW_COMM_REQ_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_CGW_COMM_REQ_candb(CGW_COMM_REQ_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(CGW_COMM_REQ_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->CGW_Comm_Req & (0x01U)) ); + + cframe->MsgId = (uint32_t) CGW_COMM_REQ_CANID; + cframe->DLC = (uint8_t) CGW_COMM_REQ_DLC; + cframe->IDE = (uint8_t) CGW_COMM_REQ_IDE; + return CGW_COMM_REQ_CANID; +} + +#else + +uint32_t Pack_CGW_COMM_REQ_candb(CGW_COMM_REQ_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(CGW_COMM_REQ_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->CGW_Comm_Req & (0x01U)) ); + + *_len = (uint8_t) CGW_COMM_REQ_DLC; + *_ide = (uint8_t) CGW_COMM_REQ_IDE; + return CGW_COMM_REQ_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_DCDC1248_01_candb(DCDC1248_01_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->DCDC1248_01_CS = (uint8_t) ( (_d[0] & (0xFFU)) ); + _m->DCDC1248_01_RC = (uint8_t) ( (_d[1] & (0x0FU)) ); + _m->DCDC1248_ActMode_Stat = (uint8_t) ( ((_d[1] >> 4U) & (0x07U)) ); + _m->DCDC1248_Warn_Stat = (uint8_t) ( ((_d[1] >> 7U) & (0x01U)) ); + _m->DCDC1248_ActCurr12_Val_ro = (uint16_t) ( ((_d[3] & (0x01U)) << 8U) | (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->DCDC1248_ActCurr12_Val_phys = (int16_t) CANDB_DCDC1248_ActCurr12_Val_ro_fromS(_m->DCDC1248_ActCurr12_Val_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->DCDC1248_ActVolt12_Val_ro = (uint16_t) ( ((_d[4] & (0x07U)) << 7U) | ((_d[3] >> 1U) & (0x7FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->DCDC1248_ActVolt12_Val_phys = (sigfloat_t)(CANDB_DCDC1248_ActVolt12_Val_ro_fromS(_m->DCDC1248_ActVolt12_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->DCDC1248_ErrInternal_Stat = (uint8_t) ( ((_d[4] >> 3U) & (0x01U)) ); + _m->DCDC1248_OvCurr12 = (uint8_t) ( ((_d[4] >> 4U) & (0x01U)) ); + _m->DCDC1248_DisChrg_Stat = (uint8_t) ( ((_d[4] >> 5U) & (0x03U)) ); + _m->DCDC1248_T15_Stat = (int8_t) __ext_sig__(( ((_d[4] >> 7U) & (0x01U)) ), 1); + _m->DCDC1248_MaxCurr12_Val_ro = (uint8_t) ( (_d[5] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->DCDC1248_MaxCurr12_Val_phys = (sigfloat_t)(CANDB_DCDC1248_MaxCurr12_Val_ro_fromS(_m->DCDC1248_MaxCurr12_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < DCDC1248_01_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_DCDC1248_01_candb(&_m->mon1, DCDC1248_01_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return DCDC1248_01_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_DCDC1248_01_candb(DCDC1248_01_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(DCDC1248_01_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->DCDC1248_ActCurr12_Val_ro = (uint16_t) CANDB_DCDC1248_ActCurr12_Val_ro_toS(_m->DCDC1248_ActCurr12_Val_phys); + _m->DCDC1248_ActVolt12_Val_ro = (uint16_t) CANDB_DCDC1248_ActVolt12_Val_ro_toS(_m->DCDC1248_ActVolt12_Val_phys); + _m->DCDC1248_MaxCurr12_Val_ro = (uint8_t) CANDB_DCDC1248_MaxCurr12_Val_ro_toS(_m->DCDC1248_MaxCurr12_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->DCDC1248_01_CS & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->DCDC1248_01_RC & (0x0FU)) | ((_m->DCDC1248_ActMode_Stat & (0x07U)) << 4U) | ((_m->DCDC1248_Warn_Stat & (0x01U)) << 7U) ); + cframe->Data[2] |= (uint8_t) ( (_m->DCDC1248_ActCurr12_Val_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->DCDC1248_ActCurr12_Val_ro >> 8U) & (0x01U)) | ((_m->DCDC1248_ActVolt12_Val_ro & (0x7FU)) << 1U) ); + cframe->Data[4] |= (uint8_t) ( ((_m->DCDC1248_ActVolt12_Val_ro >> 7U) & (0x07U)) | ((_m->DCDC1248_ErrInternal_Stat & (0x01U)) << 3U) | ((_m->DCDC1248_OvCurr12 & (0x01U)) << 4U) | ((_m->DCDC1248_DisChrg_Stat & (0x03U)) << 5U) | ((_m->DCDC1248_T15_Stat & (0x01U)) << 7U) ); + cframe->Data[5] |= (uint8_t) ( (_m->DCDC1248_MaxCurr12_Val_ro & (0xFFU)) ); + + cframe->MsgId = (uint32_t) DCDC1248_01_CANID; + cframe->DLC = (uint8_t) DCDC1248_01_DLC; + cframe->IDE = (uint8_t) DCDC1248_01_IDE; + return DCDC1248_01_CANID; +} + +#else + +uint32_t Pack_DCDC1248_01_candb(DCDC1248_01_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(DCDC1248_01_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->DCDC1248_ActCurr12_Val_ro = (uint16_t) CANDB_DCDC1248_ActCurr12_Val_ro_toS(_m->DCDC1248_ActCurr12_Val_phys); + _m->DCDC1248_ActVolt12_Val_ro = (uint16_t) CANDB_DCDC1248_ActVolt12_Val_ro_toS(_m->DCDC1248_ActVolt12_Val_phys); + _m->DCDC1248_MaxCurr12_Val_ro = (uint8_t) CANDB_DCDC1248_MaxCurr12_Val_ro_toS(_m->DCDC1248_MaxCurr12_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->DCDC1248_01_CS & (0xFFU)) ); + _d[1] |= (uint8_t) ( (_m->DCDC1248_01_RC & (0x0FU)) | ((_m->DCDC1248_ActMode_Stat & (0x07U)) << 4U) | ((_m->DCDC1248_Warn_Stat & (0x01U)) << 7U) ); + _d[2] |= (uint8_t) ( (_m->DCDC1248_ActCurr12_Val_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->DCDC1248_ActCurr12_Val_ro >> 8U) & (0x01U)) | ((_m->DCDC1248_ActVolt12_Val_ro & (0x7FU)) << 1U) ); + _d[4] |= (uint8_t) ( ((_m->DCDC1248_ActVolt12_Val_ro >> 7U) & (0x07U)) | ((_m->DCDC1248_ErrInternal_Stat & (0x01U)) << 3U) | ((_m->DCDC1248_OvCurr12 & (0x01U)) << 4U) | ((_m->DCDC1248_DisChrg_Stat & (0x03U)) << 5U) | ((_m->DCDC1248_T15_Stat & (0x01U)) << 7U) ); + _d[5] |= (uint8_t) ( (_m->DCDC1248_MaxCurr12_Val_ro & (0xFFU)) ); + + *_len = (uint8_t) DCDC1248_01_DLC; + *_ide = (uint8_t) DCDC1248_01_IDE; + return DCDC1248_01_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_REQ_CTR_01_candb(FIU_REQ_CTR_01_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->FIU_SetLanguage = (uint8_t) ( (_d[0] & (0x07U)) ); + _m->FIU_VoiceControlActive_Stat = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + _m->FIU_SERVICE_State = (uint8_t) ( ((_d[0] >> 6U) & (0x01U)) ); + _m->FIU_SOS_State = (uint8_t) ( (_d[1] & (0x01U)) ); + _m->FIU_FuelStatisticsReset_Req = (uint8_t) ( ((_d[1] >> 1U) & (0x01U)) ); + _m->FIU_UserTripStatisticsReset_Req = (uint8_t) ( ((_d[1] >> 2U) & (0x01U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < FIU_REQ_CTR_01_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_FIU_REQ_CTR_01_candb(&_m->mon1, FIU_REQ_CTR_01_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return FIU_REQ_CTR_01_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_FIU_REQ_CTR_01_candb(FIU_REQ_CTR_01_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_REQ_CTR_01_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->FIU_SetLanguage & (0x07U)) | ((_m->FIU_VoiceControlActive_Stat & (0x01U)) << 3U) | ((_m->FIU_SERVICE_State & (0x01U)) << 6U) ); + cframe->Data[1] |= (uint8_t) ( (_m->FIU_SOS_State & (0x01U)) | ((_m->FIU_FuelStatisticsReset_Req & (0x01U)) << 1U) | ((_m->FIU_UserTripStatisticsReset_Req & (0x01U)) << 2U) ); + + cframe->MsgId = (uint32_t) FIU_REQ_CTR_01_CANID; + cframe->DLC = (uint8_t) FIU_REQ_CTR_01_DLC; + cframe->IDE = (uint8_t) FIU_REQ_CTR_01_IDE; + return FIU_REQ_CTR_01_CANID; +} + +#else + +uint32_t Pack_FIU_REQ_CTR_01_candb(FIU_REQ_CTR_01_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_REQ_CTR_01_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->FIU_SetLanguage & (0x07U)) | ((_m->FIU_VoiceControlActive_Stat & (0x01U)) << 3U) | ((_m->FIU_SERVICE_State & (0x01U)) << 6U) ); + _d[1] |= (uint8_t) ( (_m->FIU_SOS_State & (0x01U)) | ((_m->FIU_FuelStatisticsReset_Req & (0x01U)) << 1U) | ((_m->FIU_UserTripStatisticsReset_Req & (0x01U)) << 2U) ); + + *_len = (uint8_t) FIU_REQ_CTR_01_DLC; + *_ide = (uint8_t) FIU_REQ_CTR_01_IDE; + return FIU_REQ_CTR_01_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_DCDC1248_02_candb(DCDC1248_02_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->DCDC1248_02_CS = (uint8_t) ( (_d[0] & (0xFFU)) ); + _m->DCDC1248_02_RC = (uint8_t) ( (_d[1] & (0x0FU)) ); + _m->DCDC1248_ActVolt48_Val_ro = (uint16_t) ( ((_d[2] & (0x3FU)) << 4U) | ((_d[1] >> 4U) & (0x0FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->DCDC1248_ActVolt48_Val_phys = (sigfloat_t)(CANDB_DCDC1248_ActVolt48_Val_ro_fromS(_m->DCDC1248_ActVolt48_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->DCDC1248_ActCurr48_Val_ro = (uint16_t) ( ((_d[3] & (0xFFU)) << 2U) | ((_d[2] >> 6U) & (0x03U)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->DCDC1248_ActCurr48_Val_phys = (int16_t) CANDB_DCDC1248_ActCurr48_Val_ro_fromS(_m->DCDC1248_ActCurr48_Val_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->DCDC1248_ActTemp_Val_ro = (uint8_t) ( (_d[4] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->DCDC1248_ActTemp_Val_phys = (int16_t) CANDB_DCDC1248_ActTemp_Val_ro_fromS(_m->DCDC1248_ActTemp_Val_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->DCDC1248_ActDisChrg_Stat = (uint8_t) ( (_d[5] & (0x03U)) ); + _m->DCDC1248_MaxCurr48_Val_ro = (uint8_t) ( (_d[6] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->DCDC1248_MaxCurr48_Val_phys = (sigfloat_t)(CANDB_DCDC1248_MaxCurr48_Val_ro_fromS(_m->DCDC1248_MaxCurr48_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < DCDC1248_02_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_DCDC1248_02_candb(&_m->mon1, DCDC1248_02_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return DCDC1248_02_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_DCDC1248_02_candb(DCDC1248_02_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(DCDC1248_02_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->DCDC1248_ActVolt48_Val_ro = (uint16_t) CANDB_DCDC1248_ActVolt48_Val_ro_toS(_m->DCDC1248_ActVolt48_Val_phys); + _m->DCDC1248_ActCurr48_Val_ro = (uint16_t) CANDB_DCDC1248_ActCurr48_Val_ro_toS(_m->DCDC1248_ActCurr48_Val_phys); + _m->DCDC1248_ActTemp_Val_ro = (uint8_t) CANDB_DCDC1248_ActTemp_Val_ro_toS(_m->DCDC1248_ActTemp_Val_phys); + _m->DCDC1248_MaxCurr48_Val_ro = (uint8_t) CANDB_DCDC1248_MaxCurr48_Val_ro_toS(_m->DCDC1248_MaxCurr48_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->DCDC1248_02_CS & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->DCDC1248_02_RC & (0x0FU)) | ((_m->DCDC1248_ActVolt48_Val_ro & (0x0FU)) << 4U) ); + cframe->Data[2] |= (uint8_t) ( ((_m->DCDC1248_ActVolt48_Val_ro >> 4U) & (0x3FU)) | ((_m->DCDC1248_ActCurr48_Val_ro & (0x03U)) << 6U) ); + cframe->Data[3] |= (uint8_t) ( ((_m->DCDC1248_ActCurr48_Val_ro >> 2U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->DCDC1248_ActTemp_Val_ro & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->DCDC1248_ActDisChrg_Stat & (0x03U)) ); + cframe->Data[6] |= (uint8_t) ( (_m->DCDC1248_MaxCurr48_Val_ro & (0xFFU)) ); + + cframe->MsgId = (uint32_t) DCDC1248_02_CANID; + cframe->DLC = (uint8_t) DCDC1248_02_DLC; + cframe->IDE = (uint8_t) DCDC1248_02_IDE; + return DCDC1248_02_CANID; +} + +#else + +uint32_t Pack_DCDC1248_02_candb(DCDC1248_02_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(DCDC1248_02_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->DCDC1248_ActVolt48_Val_ro = (uint16_t) CANDB_DCDC1248_ActVolt48_Val_ro_toS(_m->DCDC1248_ActVolt48_Val_phys); + _m->DCDC1248_ActCurr48_Val_ro = (uint16_t) CANDB_DCDC1248_ActCurr48_Val_ro_toS(_m->DCDC1248_ActCurr48_Val_phys); + _m->DCDC1248_ActTemp_Val_ro = (uint8_t) CANDB_DCDC1248_ActTemp_Val_ro_toS(_m->DCDC1248_ActTemp_Val_phys); + _m->DCDC1248_MaxCurr48_Val_ro = (uint8_t) CANDB_DCDC1248_MaxCurr48_Val_ro_toS(_m->DCDC1248_MaxCurr48_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->DCDC1248_02_CS & (0xFFU)) ); + _d[1] |= (uint8_t) ( (_m->DCDC1248_02_RC & (0x0FU)) | ((_m->DCDC1248_ActVolt48_Val_ro & (0x0FU)) << 4U) ); + _d[2] |= (uint8_t) ( ((_m->DCDC1248_ActVolt48_Val_ro >> 4U) & (0x3FU)) | ((_m->DCDC1248_ActCurr48_Val_ro & (0x03U)) << 6U) ); + _d[3] |= (uint8_t) ( ((_m->DCDC1248_ActCurr48_Val_ro >> 2U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->DCDC1248_ActTemp_Val_ro & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->DCDC1248_ActDisChrg_Stat & (0x03U)) ); + _d[6] |= (uint8_t) ( (_m->DCDC1248_MaxCurr48_Val_ro & (0xFFU)) ); + + *_len = (uint8_t) DCDC1248_02_DLC; + *_ide = (uint8_t) DCDC1248_02_IDE; + return DCDC1248_02_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_Access_Msg2_candb(FIU_Access_Msg2_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->FIU_Smartphone_Key = (uint32_t) ( ((_d[3] & (0xFFU)) << 24U) | ((_d[2] & (0xFFU)) << 16U) | ((_d[1] & (0xFFU)) << 8U) | (_d[0] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < FIU_Access_Msg2_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_FIU_Access_Msg2_candb(&_m->mon1, FIU_Access_Msg2_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return FIU_Access_Msg2_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_FIU_Access_Msg2_candb(FIU_Access_Msg2_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_Access_Msg2_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->FIU_Smartphone_Key & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->FIU_Smartphone_Key >> 8U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->FIU_Smartphone_Key >> 16U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->FIU_Smartphone_Key >> 24U) & (0xFFU)) ); + + cframe->MsgId = (uint32_t) FIU_Access_Msg2_CANID; + cframe->DLC = (uint8_t) FIU_Access_Msg2_DLC; + cframe->IDE = (uint8_t) FIU_Access_Msg2_IDE; + return FIU_Access_Msg2_CANID; +} + +#else + +uint32_t Pack_FIU_Access_Msg2_candb(FIU_Access_Msg2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_Access_Msg2_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->FIU_Smartphone_Key & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->FIU_Smartphone_Key >> 8U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->FIU_Smartphone_Key >> 16U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->FIU_Smartphone_Key >> 24U) & (0xFFU)) ); + + *_len = (uint8_t) FIU_Access_Msg2_DLC; + *_ide = (uint8_t) FIU_Access_Msg2_IDE; + return FIU_Access_Msg2_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_Profile_candb(FIU_Profile_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->FIU_CurrProfile_Front_Stat = (uint8_t) ( (_d[0] & (0x07U)) ); + _m->FIU_KeySearch_Req = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + _m->FIU_ProfileSeatFront_Stat = (uint8_t) ( ((_d[0] >> 4U) & (0x01U)) ); + _m->FIU_ProfileCustomFront_Stat = (uint8_t) ( ((_d[0] >> 5U) & (0x01U)) ); + _m->FIU_ProfileSystFront_Stat = (uint8_t) ( ((_d[0] >> 6U) & (0x01U)) ); + _m->FIU_ProfileCarSettingsFront_Stat = (uint8_t) ( ((_d[0] >> 7U) & (0x01U)) ); + _m->FIU_CurrProfile_Rear_Stat = (uint8_t) ( (_d[1] & (0x07U)) ); + _m->FIU_ProfileSeatRear_Req = (uint8_t) ( ((_d[1] >> 3U) & (0x01U)) ); + _m->FIU_ProfileCustomRear_Req = (uint8_t) ( ((_d[1] >> 4U) & (0x01U)) ); + _m->FIU_ProfileSystRear_Req = (uint8_t) ( ((_d[1] >> 5U) & (0x01U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < FIU_Profile_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_FIU_Profile_candb(&_m->mon1, FIU_Profile_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return FIU_Profile_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_FIU_Profile_candb(FIU_Profile_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_Profile_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->FIU_CurrProfile_Front_Stat & (0x07U)) | ((_m->FIU_KeySearch_Req & (0x01U)) << 3U) | ((_m->FIU_ProfileSeatFront_Stat & (0x01U)) << 4U) | ((_m->FIU_ProfileCustomFront_Stat & (0x01U)) << 5U) | ((_m->FIU_ProfileSystFront_Stat & (0x01U)) << 6U) | ((_m->FIU_ProfileCarSettingsFront_Stat & (0x01U)) << 7U) ); + cframe->Data[1] |= (uint8_t) ( (_m->FIU_CurrProfile_Rear_Stat & (0x07U)) | ((_m->FIU_ProfileSeatRear_Req & (0x01U)) << 3U) | ((_m->FIU_ProfileCustomRear_Req & (0x01U)) << 4U) | ((_m->FIU_ProfileSystRear_Req & (0x01U)) << 5U) ); + + cframe->MsgId = (uint32_t) FIU_Profile_CANID; + cframe->DLC = (uint8_t) FIU_Profile_DLC; + cframe->IDE = (uint8_t) FIU_Profile_IDE; + return FIU_Profile_CANID; +} + +#else + +uint32_t Pack_FIU_Profile_candb(FIU_Profile_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_Profile_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->FIU_CurrProfile_Front_Stat & (0x07U)) | ((_m->FIU_KeySearch_Req & (0x01U)) << 3U) | ((_m->FIU_ProfileSeatFront_Stat & (0x01U)) << 4U) | ((_m->FIU_ProfileCustomFront_Stat & (0x01U)) << 5U) | ((_m->FIU_ProfileSystFront_Stat & (0x01U)) << 6U) | ((_m->FIU_ProfileCarSettingsFront_Stat & (0x01U)) << 7U) ); + _d[1] |= (uint8_t) ( (_m->FIU_CurrProfile_Rear_Stat & (0x07U)) | ((_m->FIU_ProfileSeatRear_Req & (0x01U)) << 3U) | ((_m->FIU_ProfileCustomRear_Req & (0x01U)) << 4U) | ((_m->FIU_ProfileSystRear_Req & (0x01U)) << 5U) ); + + *_len = (uint8_t) FIU_Profile_DLC; + *_ide = (uint8_t) FIU_Profile_IDE; + return FIU_Profile_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_USBSw_Stat_candb(USBSw_Stat_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->USBSw_OutputSwitch_Stat = (uint8_t) ( (_d[0] & (0x03U)) ); + _m->USBSw_ConfCamera_Req = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < USBSw_Stat_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_USBSw_Stat_candb(&_m->mon1, USBSw_Stat_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return USBSw_Stat_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_USBSw_Stat_candb(USBSw_Stat_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(USBSw_Stat_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->USBSw_OutputSwitch_Stat & (0x03U)) | ((_m->USBSw_ConfCamera_Req & (0x01U)) << 2U) ); + + cframe->MsgId = (uint32_t) USBSw_Stat_CANID; + cframe->DLC = (uint8_t) USBSw_Stat_DLC; + cframe->IDE = (uint8_t) USBSw_Stat_IDE; + return USBSw_Stat_CANID; +} + +#else + +uint32_t Pack_USBSw_Stat_candb(USBSw_Stat_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(USBSw_Stat_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->USBSw_OutputSwitch_Stat & (0x03U)) | ((_m->USBSw_ConfCamera_Req & (0x01U)) << 2U) ); + + *_len = (uint8_t) USBSw_Stat_DLC; + *_ide = (uint8_t) USBSw_Stat_IDE; + return USBSw_Stat_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SMFL_status_candb(SMFL_status_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->SMFL_MMmenuActivation = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->SMFL_SeatHeight_Stat = (uint8_t) ( ((_d[0] >> 3U) & (0x03U)) ); + _m->SMFL_HeadRestHeight_Stat = (uint8_t) ( ((_d[0] >> 5U) & (0x03U)) ); + _m->SMFL_SeatLongitudinal_Stat = (uint8_t) ( ((_d[1] & (0x01U)) << 1U) | ((_d[0] >> 7U) & (0x01U)) ); + _m->SMFL_HeadRestHeightInclin_Stat = (uint8_t) ( ((_d[1] >> 1U) & (0x03U)) ); + _m->SMFL_SurfaceLongitudinal_Stat = (uint8_t) ( ((_d[1] >> 3U) & (0x03U)) ); + _m->SMFL_SeatLegSupportH_Stat = (uint8_t) ( ((_d[1] >> 5U) & (0x03U)) ); + _m->SMFL_SeatInclination_Stat = (uint8_t) ( ((_d[2] & (0x01U)) << 1U) | ((_d[1] >> 7U) & (0x01U)) ); + _m->SMFL_SeatLegSupportL_Stat = (uint8_t) ( ((_d[2] >> 1U) & (0x03U)) ); + _m->SMFL_BackRestInclin_Stat = (uint8_t) ( ((_d[2] >> 3U) & (0x03U)) ); + _m->SMFL_LumbarSupportHeight_Stat = (uint8_t) ( ((_d[2] >> 5U) & (0x03U)) ); + _m->SMFL_BackRestHeadInclin_Stat = (uint8_t) ( ((_d[3] & (0x01U)) << 1U) | ((_d[2] >> 7U) & (0x01U)) ); + _m->SMFL_LumbarSupportDepth_Stat = (uint8_t) ( ((_d[3] >> 1U) & (0x03U)) ); + _m->SMFL_BackRestWidth_Stat = (uint8_t) ( ((_d[3] >> 3U) & (0x03U)) ); + _m->SMFL_CushionSupport_Stat = (uint8_t) ( ((_d[3] >> 5U) & (0x03U)) ); + _m->SMFL_SeatVentilation_Stat = (uint8_t) ( ((_d[4] & (0x01U)) << 1U) | ((_d[3] >> 7U) & (0x01U)) ); + _m->SMFL_SeatVentBalance_Stat = (uint8_t) ( ((_d[4] >> 1U) & (0x07U)) ); + _m->SMFL_Heating_Stat = (uint8_t) ( ((_d[4] >> 4U) & (0x03U)) ); + _m->SMFL_HeatBalance_Stat = (uint8_t) ( ((_d[5] & (0x01U)) << 2U) | ((_d[4] >> 6U) & (0x03U)) ); + _m->SMFL_SeatMassage_Stat = (uint8_t) ( ((_d[5] >> 1U) & (0x03U)) ); + _m->SMFL_MassageIntens_Stat = (uint8_t) ( ((_d[5] >> 3U) & (0x03U)) ); + _m->SMFL_SeatMassageType_Stat = (uint8_t) ( ((_d[5] >> 5U) & (0x07U)) ); + _m->SMFL_TabletPWR_Stat = (uint8_t) ( (_d[6] & (0x01U)) ); + _m->SMFL_CarpetHeat_Stat = (uint8_t) ( ((_d[6] >> 1U) & (0x01U)) ); + _m->SMFL_ActiveSupport_Stat = (uint8_t) ( ((_d[6] >> 2U) & (0x01U)) ); + _m->SMFL_BackrestMassageType_Stat = (uint8_t) ( ((_d[6] >> 3U) & (0x07U)) ); + _m->SMFL_TimerMassage_Stat = (uint8_t) ( (_d[7] & (0x07U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < SMFL_status_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_SMFL_status_candb(&_m->mon1, SMFL_status_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return SMFL_status_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_SMFL_status_candb(SMFL_status_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SMFL_status_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->SMFL_MMmenuActivation & (0x01U)) | ((_m->SMFL_SeatHeight_Stat & (0x03U)) << 3U) | ((_m->SMFL_HeadRestHeight_Stat & (0x03U)) << 5U) | ((_m->SMFL_SeatLongitudinal_Stat & (0x01U)) << 7U) ); + cframe->Data[1] |= (uint8_t) ( ((_m->SMFL_SeatLongitudinal_Stat >> 1U) & (0x01U)) | ((_m->SMFL_HeadRestHeightInclin_Stat & (0x03U)) << 1U) | ((_m->SMFL_SurfaceLongitudinal_Stat & (0x03U)) << 3U) | ((_m->SMFL_SeatLegSupportH_Stat & (0x03U)) << 5U) | ((_m->SMFL_SeatInclination_Stat & (0x01U)) << 7U) ); + cframe->Data[2] |= (uint8_t) ( ((_m->SMFL_SeatInclination_Stat >> 1U) & (0x01U)) | ((_m->SMFL_SeatLegSupportL_Stat & (0x03U)) << 1U) | ((_m->SMFL_BackRestInclin_Stat & (0x03U)) << 3U) | ((_m->SMFL_LumbarSupportHeight_Stat & (0x03U)) << 5U) | ((_m->SMFL_BackRestHeadInclin_Stat & (0x01U)) << 7U) ); + cframe->Data[3] |= (uint8_t) ( ((_m->SMFL_BackRestHeadInclin_Stat >> 1U) & (0x01U)) | ((_m->SMFL_LumbarSupportDepth_Stat & (0x03U)) << 1U) | ((_m->SMFL_BackRestWidth_Stat & (0x03U)) << 3U) | ((_m->SMFL_CushionSupport_Stat & (0x03U)) << 5U) | ((_m->SMFL_SeatVentilation_Stat & (0x01U)) << 7U) ); + cframe->Data[4] |= (uint8_t) ( ((_m->SMFL_SeatVentilation_Stat >> 1U) & (0x01U)) | ((_m->SMFL_SeatVentBalance_Stat & (0x07U)) << 1U) | ((_m->SMFL_Heating_Stat & (0x03U)) << 4U) | ((_m->SMFL_HeatBalance_Stat & (0x03U)) << 6U) ); + cframe->Data[5] |= (uint8_t) ( ((_m->SMFL_HeatBalance_Stat >> 2U) & (0x01U)) | ((_m->SMFL_SeatMassage_Stat & (0x03U)) << 1U) | ((_m->SMFL_MassageIntens_Stat & (0x03U)) << 3U) | ((_m->SMFL_SeatMassageType_Stat & (0x07U)) << 5U) ); + cframe->Data[6] |= (uint8_t) ( (_m->SMFL_TabletPWR_Stat & (0x01U)) | ((_m->SMFL_CarpetHeat_Stat & (0x01U)) << 1U) | ((_m->SMFL_ActiveSupport_Stat & (0x01U)) << 2U) | ((_m->SMFL_BackrestMassageType_Stat & (0x07U)) << 3U) ); + cframe->Data[7] |= (uint8_t) ( (_m->SMFL_TimerMassage_Stat & (0x07U)) ); + + cframe->MsgId = (uint32_t) SMFL_status_CANID; + cframe->DLC = (uint8_t) SMFL_status_DLC; + cframe->IDE = (uint8_t) SMFL_status_IDE; + return SMFL_status_CANID; +} + +#else + +uint32_t Pack_SMFL_status_candb(SMFL_status_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SMFL_status_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->SMFL_MMmenuActivation & (0x01U)) | ((_m->SMFL_SeatHeight_Stat & (0x03U)) << 3U) | ((_m->SMFL_HeadRestHeight_Stat & (0x03U)) << 5U) | ((_m->SMFL_SeatLongitudinal_Stat & (0x01U)) << 7U) ); + _d[1] |= (uint8_t) ( ((_m->SMFL_SeatLongitudinal_Stat >> 1U) & (0x01U)) | ((_m->SMFL_HeadRestHeightInclin_Stat & (0x03U)) << 1U) | ((_m->SMFL_SurfaceLongitudinal_Stat & (0x03U)) << 3U) | ((_m->SMFL_SeatLegSupportH_Stat & (0x03U)) << 5U) | ((_m->SMFL_SeatInclination_Stat & (0x01U)) << 7U) ); + _d[2] |= (uint8_t) ( ((_m->SMFL_SeatInclination_Stat >> 1U) & (0x01U)) | ((_m->SMFL_SeatLegSupportL_Stat & (0x03U)) << 1U) | ((_m->SMFL_BackRestInclin_Stat & (0x03U)) << 3U) | ((_m->SMFL_LumbarSupportHeight_Stat & (0x03U)) << 5U) | ((_m->SMFL_BackRestHeadInclin_Stat & (0x01U)) << 7U) ); + _d[3] |= (uint8_t) ( ((_m->SMFL_BackRestHeadInclin_Stat >> 1U) & (0x01U)) | ((_m->SMFL_LumbarSupportDepth_Stat & (0x03U)) << 1U) | ((_m->SMFL_BackRestWidth_Stat & (0x03U)) << 3U) | ((_m->SMFL_CushionSupport_Stat & (0x03U)) << 5U) | ((_m->SMFL_SeatVentilation_Stat & (0x01U)) << 7U) ); + _d[4] |= (uint8_t) ( ((_m->SMFL_SeatVentilation_Stat >> 1U) & (0x01U)) | ((_m->SMFL_SeatVentBalance_Stat & (0x07U)) << 1U) | ((_m->SMFL_Heating_Stat & (0x03U)) << 4U) | ((_m->SMFL_HeatBalance_Stat & (0x03U)) << 6U) ); + _d[5] |= (uint8_t) ( ((_m->SMFL_HeatBalance_Stat >> 2U) & (0x01U)) | ((_m->SMFL_SeatMassage_Stat & (0x03U)) << 1U) | ((_m->SMFL_MassageIntens_Stat & (0x03U)) << 3U) | ((_m->SMFL_SeatMassageType_Stat & (0x07U)) << 5U) ); + _d[6] |= (uint8_t) ( (_m->SMFL_TabletPWR_Stat & (0x01U)) | ((_m->SMFL_CarpetHeat_Stat & (0x01U)) << 1U) | ((_m->SMFL_ActiveSupport_Stat & (0x01U)) << 2U) | ((_m->SMFL_BackrestMassageType_Stat & (0x07U)) << 3U) ); + _d[7] |= (uint8_t) ( (_m->SMFL_TimerMassage_Stat & (0x07U)) ); + + *_len = (uint8_t) SMFL_status_DLC; + *_ide = (uint8_t) SMFL_status_IDE; + return SMFL_status_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SMFR_status_candb(SMFR_status_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->SMFR_MMmenuActivBtn_Stat = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->SMFR_SeatHeight_Stat = (uint8_t) ( ((_d[0] >> 3U) & (0x03U)) ); + _m->SMFR_HeadRestHeight_Stat = (uint8_t) ( ((_d[0] >> 5U) & (0x03U)) ); + _m->SMFR_SeatLongitudinal_Stat = (uint8_t) ( ((_d[1] & (0x01U)) << 1U) | ((_d[0] >> 7U) & (0x01U)) ); + _m->SMFR_HeadRestHeightInclin_Stat = (uint8_t) ( ((_d[1] >> 1U) & (0x03U)) ); + _m->SMFR_SurfaceLongitudinal_Stat = (uint8_t) ( ((_d[1] >> 3U) & (0x03U)) ); + _m->SMFR_FootRestHeight_Stat = (uint8_t) ( ((_d[1] >> 5U) & (0x03U)) ); + _m->SMFR_SeatInclination_Stat = (uint8_t) ( ((_d[2] & (0x01U)) << 1U) | ((_d[1] >> 7U) & (0x01U)) ); + _m->SMFR_SeatLegSupportL_Stat = (uint8_t) ( ((_d[2] >> 1U) & (0x03U)) ); + _m->SMFR_BackRestInclin_Stat = (uint8_t) ( ((_d[2] >> 3U) & (0x03U)) ); + _m->SMFR_LumbarSupportHeight_Stat = (uint8_t) ( ((_d[2] >> 5U) & (0x03U)) ); + _m->SMFR_BackRestHeadInclin_Stat = (uint8_t) ( ((_d[3] & (0x01U)) << 1U) | ((_d[2] >> 7U) & (0x01U)) ); + _m->SMFR_LumbarSupportDepth_Stat = (uint8_t) ( ((_d[3] >> 1U) & (0x03U)) ); + _m->SMFR_BackRestWidth_Stat = (uint8_t) ( ((_d[3] >> 3U) & (0x03U)) ); + _m->SMFR_CushionSupport_Stat = (uint8_t) ( ((_d[3] >> 5U) & (0x03U)) ); + _m->SMFR_SeatVentilation_Stat = (uint8_t) ( ((_d[4] & (0x01U)) << 1U) | ((_d[3] >> 7U) & (0x01U)) ); + _m->SMFR_SeatVentBalance_Stat = (uint8_t) ( ((_d[4] >> 1U) & (0x07U)) ); + _m->SMFR_Heating_Stat = (uint8_t) ( ((_d[4] >> 4U) & (0x03U)) ); + _m->SMFR_HeatBalance_Stat = (uint8_t) ( ((_d[5] & (0x01U)) << 2U) | ((_d[4] >> 6U) & (0x03U)) ); + _m->SMFR_SeatMassage_Stat = (uint8_t) ( ((_d[5] >> 1U) & (0x03U)) ); + _m->SMFR_MassageIntens_Stat = (uint8_t) ( ((_d[5] >> 3U) & (0x03U)) ); + _m->SMFR_SeatMassageType_Stat = (uint8_t) ( ((_d[5] >> 5U) & (0x07U)) ); + _m->SMFR_TabletPWR_Stat = (uint8_t) ( (_d[6] & (0x01U)) ); + _m->SMFR_CarpetHeat_Stat = (uint8_t) ( ((_d[6] >> 1U) & (0x01U)) ); + _m->SMFR_ActiveSupport_Stat = (uint8_t) ( ((_d[6] >> 2U) & (0x01U)) ); + _m->SMFR_BackrestMassageType_Stat = (uint8_t) ( ((_d[6] >> 3U) & (0x07U)) ); + _m->SMFR_SeatControl_Stat = (uint8_t) ( ((_d[6] >> 6U) & (0x03U)) ); + _m->SMFR_TimerMassage_Stat = (uint8_t) ( (_d[7] & (0x07U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < SMFR_status_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_SMFR_status_candb(&_m->mon1, SMFR_status_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return SMFR_status_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_SMFR_status_candb(SMFR_status_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SMFR_status_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->SMFR_MMmenuActivBtn_Stat & (0x01U)) | ((_m->SMFR_SeatHeight_Stat & (0x03U)) << 3U) | ((_m->SMFR_HeadRestHeight_Stat & (0x03U)) << 5U) | ((_m->SMFR_SeatLongitudinal_Stat & (0x01U)) << 7U) ); + cframe->Data[1] |= (uint8_t) ( ((_m->SMFR_SeatLongitudinal_Stat >> 1U) & (0x01U)) | ((_m->SMFR_HeadRestHeightInclin_Stat & (0x03U)) << 1U) | ((_m->SMFR_SurfaceLongitudinal_Stat & (0x03U)) << 3U) | ((_m->SMFR_FootRestHeight_Stat & (0x03U)) << 5U) | ((_m->SMFR_SeatInclination_Stat & (0x01U)) << 7U) ); + cframe->Data[2] |= (uint8_t) ( ((_m->SMFR_SeatInclination_Stat >> 1U) & (0x01U)) | ((_m->SMFR_SeatLegSupportL_Stat & (0x03U)) << 1U) | ((_m->SMFR_BackRestInclin_Stat & (0x03U)) << 3U) | ((_m->SMFR_LumbarSupportHeight_Stat & (0x03U)) << 5U) | ((_m->SMFR_BackRestHeadInclin_Stat & (0x01U)) << 7U) ); + cframe->Data[3] |= (uint8_t) ( ((_m->SMFR_BackRestHeadInclin_Stat >> 1U) & (0x01U)) | ((_m->SMFR_LumbarSupportDepth_Stat & (0x03U)) << 1U) | ((_m->SMFR_BackRestWidth_Stat & (0x03U)) << 3U) | ((_m->SMFR_CushionSupport_Stat & (0x03U)) << 5U) | ((_m->SMFR_SeatVentilation_Stat & (0x01U)) << 7U) ); + cframe->Data[4] |= (uint8_t) ( ((_m->SMFR_SeatVentilation_Stat >> 1U) & (0x01U)) | ((_m->SMFR_SeatVentBalance_Stat & (0x07U)) << 1U) | ((_m->SMFR_Heating_Stat & (0x03U)) << 4U) | ((_m->SMFR_HeatBalance_Stat & (0x03U)) << 6U) ); + cframe->Data[5] |= (uint8_t) ( ((_m->SMFR_HeatBalance_Stat >> 2U) & (0x01U)) | ((_m->SMFR_SeatMassage_Stat & (0x03U)) << 1U) | ((_m->SMFR_MassageIntens_Stat & (0x03U)) << 3U) | ((_m->SMFR_SeatMassageType_Stat & (0x07U)) << 5U) ); + cframe->Data[6] |= (uint8_t) ( (_m->SMFR_TabletPWR_Stat & (0x01U)) | ((_m->SMFR_CarpetHeat_Stat & (0x01U)) << 1U) | ((_m->SMFR_ActiveSupport_Stat & (0x01U)) << 2U) | ((_m->SMFR_BackrestMassageType_Stat & (0x07U)) << 3U) | ((_m->SMFR_SeatControl_Stat & (0x03U)) << 6U) ); + cframe->Data[7] |= (uint8_t) ( (_m->SMFR_TimerMassage_Stat & (0x07U)) ); + + cframe->MsgId = (uint32_t) SMFR_status_CANID; + cframe->DLC = (uint8_t) SMFR_status_DLC; + cframe->IDE = (uint8_t) SMFR_status_IDE; + return SMFR_status_CANID; +} + +#else + +uint32_t Pack_SMFR_status_candb(SMFR_status_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SMFR_status_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->SMFR_MMmenuActivBtn_Stat & (0x01U)) | ((_m->SMFR_SeatHeight_Stat & (0x03U)) << 3U) | ((_m->SMFR_HeadRestHeight_Stat & (0x03U)) << 5U) | ((_m->SMFR_SeatLongitudinal_Stat & (0x01U)) << 7U) ); + _d[1] |= (uint8_t) ( ((_m->SMFR_SeatLongitudinal_Stat >> 1U) & (0x01U)) | ((_m->SMFR_HeadRestHeightInclin_Stat & (0x03U)) << 1U) | ((_m->SMFR_SurfaceLongitudinal_Stat & (0x03U)) << 3U) | ((_m->SMFR_FootRestHeight_Stat & (0x03U)) << 5U) | ((_m->SMFR_SeatInclination_Stat & (0x01U)) << 7U) ); + _d[2] |= (uint8_t) ( ((_m->SMFR_SeatInclination_Stat >> 1U) & (0x01U)) | ((_m->SMFR_SeatLegSupportL_Stat & (0x03U)) << 1U) | ((_m->SMFR_BackRestInclin_Stat & (0x03U)) << 3U) | ((_m->SMFR_LumbarSupportHeight_Stat & (0x03U)) << 5U) | ((_m->SMFR_BackRestHeadInclin_Stat & (0x01U)) << 7U) ); + _d[3] |= (uint8_t) ( ((_m->SMFR_BackRestHeadInclin_Stat >> 1U) & (0x01U)) | ((_m->SMFR_LumbarSupportDepth_Stat & (0x03U)) << 1U) | ((_m->SMFR_BackRestWidth_Stat & (0x03U)) << 3U) | ((_m->SMFR_CushionSupport_Stat & (0x03U)) << 5U) | ((_m->SMFR_SeatVentilation_Stat & (0x01U)) << 7U) ); + _d[4] |= (uint8_t) ( ((_m->SMFR_SeatVentilation_Stat >> 1U) & (0x01U)) | ((_m->SMFR_SeatVentBalance_Stat & (0x07U)) << 1U) | ((_m->SMFR_Heating_Stat & (0x03U)) << 4U) | ((_m->SMFR_HeatBalance_Stat & (0x03U)) << 6U) ); + _d[5] |= (uint8_t) ( ((_m->SMFR_HeatBalance_Stat >> 2U) & (0x01U)) | ((_m->SMFR_SeatMassage_Stat & (0x03U)) << 1U) | ((_m->SMFR_MassageIntens_Stat & (0x03U)) << 3U) | ((_m->SMFR_SeatMassageType_Stat & (0x07U)) << 5U) ); + _d[6] |= (uint8_t) ( (_m->SMFR_TabletPWR_Stat & (0x01U)) | ((_m->SMFR_CarpetHeat_Stat & (0x01U)) << 1U) | ((_m->SMFR_ActiveSupport_Stat & (0x01U)) << 2U) | ((_m->SMFR_BackrestMassageType_Stat & (0x07U)) << 3U) | ((_m->SMFR_SeatControl_Stat & (0x03U)) << 6U) ); + _d[7] |= (uint8_t) ( (_m->SMFR_TimerMassage_Stat & (0x07U)) ); + + *_len = (uint8_t) SMFR_status_DLC; + *_ide = (uint8_t) SMFR_status_IDE; + return SMFR_status_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SMRL_status_candb(SMRL_status_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->SMRL_MMmenuActivBtn_Stat = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->SMRL_SeatHeight_Stat = (uint8_t) ( ((_d[0] >> 3U) & (0x03U)) ); + _m->SMRL_HeadRestHeight_Stat = (uint8_t) ( ((_d[0] >> 5U) & (0x03U)) ); + _m->SMRL_SeatLongitudinal_Stat = (uint8_t) ( ((_d[1] & (0x01U)) << 1U) | ((_d[0] >> 7U) & (0x01U)) ); + _m->SMRL_HeadRestHeightInclin_Stat = (uint8_t) ( ((_d[1] >> 1U) & (0x03U)) ); + _m->SMRL_SurfaceLongitudinal_Stat = (uint8_t) ( ((_d[1] >> 3U) & (0x03U)) ); + _m->SMRL_SeatLegSupportH_Stat = (uint8_t) ( ((_d[1] >> 5U) & (0x03U)) ); + _m->SMRL_SeatInclination_Stat = (uint8_t) ( ((_d[2] & (0x01U)) << 1U) | ((_d[1] >> 7U) & (0x01U)) ); + _m->SMRL_SeatLegSupportL_Stat = (uint8_t) ( ((_d[2] >> 1U) & (0x03U)) ); + _m->SMRL_BackRestInclin_Stat = (uint8_t) ( ((_d[2] >> 3U) & (0x03U)) ); + _m->SMRL_LumbarSupportHeight_Stat = (uint8_t) ( ((_d[2] >> 5U) & (0x03U)) ); + _m->SMRL_BackRestHeadInclin_Stat = (uint8_t) ( ((_d[3] & (0x01U)) << 1U) | ((_d[2] >> 7U) & (0x01U)) ); + _m->SMRL_LumbarSupportDepth_Stat = (uint8_t) ( ((_d[3] >> 1U) & (0x03U)) ); + _m->SMRL_BackRestWidth_Stat = (uint8_t) ( ((_d[3] >> 3U) & (0x03U)) ); + _m->SMRL_CushionSuppor_Stat = (uint8_t) ( ((_d[3] >> 5U) & (0x03U)) ); + _m->SMRL_SeatVentilation_Stat = (uint8_t) ( ((_d[4] & (0x01U)) << 1U) | ((_d[3] >> 7U) & (0x01U)) ); + _m->SMRL_SeatVentBalance_Stat = (uint8_t) ( ((_d[4] >> 1U) & (0x07U)) ); + _m->SMRL_Heating_Stat = (uint8_t) ( ((_d[4] >> 4U) & (0x03U)) ); + _m->SMRL_HeatBalance_Stat = (uint8_t) ( ((_d[5] & (0x01U)) << 2U) | ((_d[4] >> 6U) & (0x03U)) ); + _m->SMRL_SeatMassage_Stat = (uint8_t) ( ((_d[5] >> 1U) & (0x03U)) ); + _m->SMRL_MassageIntens_Stat = (uint8_t) ( ((_d[5] >> 3U) & (0x03U)) ); + _m->SMRL_SeatMassageType_Stat = (uint8_t) ( ((_d[5] >> 5U) & (0x07U)) ); + _m->SMRL_MoreComfort_Stat = (uint8_t) ( (_d[6] & (0x01U)) ); + _m->SMRL_CarpetHeat_Stat = (uint8_t) ( ((_d[6] >> 1U) & (0x01U)) ); + _m->SMRL_ActiveSupport_Stat = (uint8_t) ( ((_d[6] >> 2U) & (0x01U)) ); + _m->SMRL_BackrestMassageType_Stat = (uint8_t) ( ((_d[6] >> 3U) & (0x07U)) ); + _m->SMRL_TimerMassage_Stat = (uint8_t) ( (_d[7] & (0x07U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < SMRL_status_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_SMRL_status_candb(&_m->mon1, SMRL_status_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return SMRL_status_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_SMRL_status_candb(SMRL_status_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SMRL_status_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->SMRL_MMmenuActivBtn_Stat & (0x01U)) | ((_m->SMRL_SeatHeight_Stat & (0x03U)) << 3U) | ((_m->SMRL_HeadRestHeight_Stat & (0x03U)) << 5U) | ((_m->SMRL_SeatLongitudinal_Stat & (0x01U)) << 7U) ); + cframe->Data[1] |= (uint8_t) ( ((_m->SMRL_SeatLongitudinal_Stat >> 1U) & (0x01U)) | ((_m->SMRL_HeadRestHeightInclin_Stat & (0x03U)) << 1U) | ((_m->SMRL_SurfaceLongitudinal_Stat & (0x03U)) << 3U) | ((_m->SMRL_SeatLegSupportH_Stat & (0x03U)) << 5U) | ((_m->SMRL_SeatInclination_Stat & (0x01U)) << 7U) ); + cframe->Data[2] |= (uint8_t) ( ((_m->SMRL_SeatInclination_Stat >> 1U) & (0x01U)) | ((_m->SMRL_SeatLegSupportL_Stat & (0x03U)) << 1U) | ((_m->SMRL_BackRestInclin_Stat & (0x03U)) << 3U) | ((_m->SMRL_LumbarSupportHeight_Stat & (0x03U)) << 5U) | ((_m->SMRL_BackRestHeadInclin_Stat & (0x01U)) << 7U) ); + cframe->Data[3] |= (uint8_t) ( ((_m->SMRL_BackRestHeadInclin_Stat >> 1U) & (0x01U)) | ((_m->SMRL_LumbarSupportDepth_Stat & (0x03U)) << 1U) | ((_m->SMRL_BackRestWidth_Stat & (0x03U)) << 3U) | ((_m->SMRL_CushionSuppor_Stat & (0x03U)) << 5U) | ((_m->SMRL_SeatVentilation_Stat & (0x01U)) << 7U) ); + cframe->Data[4] |= (uint8_t) ( ((_m->SMRL_SeatVentilation_Stat >> 1U) & (0x01U)) | ((_m->SMRL_SeatVentBalance_Stat & (0x07U)) << 1U) | ((_m->SMRL_Heating_Stat & (0x03U)) << 4U) | ((_m->SMRL_HeatBalance_Stat & (0x03U)) << 6U) ); + cframe->Data[5] |= (uint8_t) ( ((_m->SMRL_HeatBalance_Stat >> 2U) & (0x01U)) | ((_m->SMRL_SeatMassage_Stat & (0x03U)) << 1U) | ((_m->SMRL_MassageIntens_Stat & (0x03U)) << 3U) | ((_m->SMRL_SeatMassageType_Stat & (0x07U)) << 5U) ); + cframe->Data[6] |= (uint8_t) ( (_m->SMRL_MoreComfort_Stat & (0x01U)) | ((_m->SMRL_CarpetHeat_Stat & (0x01U)) << 1U) | ((_m->SMRL_ActiveSupport_Stat & (0x01U)) << 2U) | ((_m->SMRL_BackrestMassageType_Stat & (0x07U)) << 3U) ); + cframe->Data[7] |= (uint8_t) ( (_m->SMRL_TimerMassage_Stat & (0x07U)) ); + + cframe->MsgId = (uint32_t) SMRL_status_CANID; + cframe->DLC = (uint8_t) SMRL_status_DLC; + cframe->IDE = (uint8_t) SMRL_status_IDE; + return SMRL_status_CANID; +} + +#else + +uint32_t Pack_SMRL_status_candb(SMRL_status_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SMRL_status_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->SMRL_MMmenuActivBtn_Stat & (0x01U)) | ((_m->SMRL_SeatHeight_Stat & (0x03U)) << 3U) | ((_m->SMRL_HeadRestHeight_Stat & (0x03U)) << 5U) | ((_m->SMRL_SeatLongitudinal_Stat & (0x01U)) << 7U) ); + _d[1] |= (uint8_t) ( ((_m->SMRL_SeatLongitudinal_Stat >> 1U) & (0x01U)) | ((_m->SMRL_HeadRestHeightInclin_Stat & (0x03U)) << 1U) | ((_m->SMRL_SurfaceLongitudinal_Stat & (0x03U)) << 3U) | ((_m->SMRL_SeatLegSupportH_Stat & (0x03U)) << 5U) | ((_m->SMRL_SeatInclination_Stat & (0x01U)) << 7U) ); + _d[2] |= (uint8_t) ( ((_m->SMRL_SeatInclination_Stat >> 1U) & (0x01U)) | ((_m->SMRL_SeatLegSupportL_Stat & (0x03U)) << 1U) | ((_m->SMRL_BackRestInclin_Stat & (0x03U)) << 3U) | ((_m->SMRL_LumbarSupportHeight_Stat & (0x03U)) << 5U) | ((_m->SMRL_BackRestHeadInclin_Stat & (0x01U)) << 7U) ); + _d[3] |= (uint8_t) ( ((_m->SMRL_BackRestHeadInclin_Stat >> 1U) & (0x01U)) | ((_m->SMRL_LumbarSupportDepth_Stat & (0x03U)) << 1U) | ((_m->SMRL_BackRestWidth_Stat & (0x03U)) << 3U) | ((_m->SMRL_CushionSuppor_Stat & (0x03U)) << 5U) | ((_m->SMRL_SeatVentilation_Stat & (0x01U)) << 7U) ); + _d[4] |= (uint8_t) ( ((_m->SMRL_SeatVentilation_Stat >> 1U) & (0x01U)) | ((_m->SMRL_SeatVentBalance_Stat & (0x07U)) << 1U) | ((_m->SMRL_Heating_Stat & (0x03U)) << 4U) | ((_m->SMRL_HeatBalance_Stat & (0x03U)) << 6U) ); + _d[5] |= (uint8_t) ( ((_m->SMRL_HeatBalance_Stat >> 2U) & (0x01U)) | ((_m->SMRL_SeatMassage_Stat & (0x03U)) << 1U) | ((_m->SMRL_MassageIntens_Stat & (0x03U)) << 3U) | ((_m->SMRL_SeatMassageType_Stat & (0x07U)) << 5U) ); + _d[6] |= (uint8_t) ( (_m->SMRL_MoreComfort_Stat & (0x01U)) | ((_m->SMRL_CarpetHeat_Stat & (0x01U)) << 1U) | ((_m->SMRL_ActiveSupport_Stat & (0x01U)) << 2U) | ((_m->SMRL_BackrestMassageType_Stat & (0x07U)) << 3U) ); + _d[7] |= (uint8_t) ( (_m->SMRL_TimerMassage_Stat & (0x07U)) ); + + *_len = (uint8_t) SMRL_status_DLC; + *_ide = (uint8_t) SMRL_status_IDE; + return SMRL_status_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SMRR_status_candb(SMRR_status_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->SMRR_MMmenuActivBtn_Stat = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->SMRR_SeatHeight_Stat = (uint8_t) ( ((_d[0] >> 3U) & (0x03U)) ); + _m->SMRR_HeadRestHeight_Stat = (uint8_t) ( ((_d[0] >> 5U) & (0x03U)) ); + _m->SMRR_SeatLongitudinal_Stat = (uint8_t) ( ((_d[1] & (0x01U)) << 1U) | ((_d[0] >> 7U) & (0x01U)) ); + _m->SMRR_HeadRestHeightInclin_Stat = (uint8_t) ( ((_d[1] >> 1U) & (0x03U)) ); + _m->SMRR_SurfaceLongitudinal_Stat = (uint8_t) ( ((_d[1] >> 3U) & (0x03U)) ); + _m->SMRR_SeatLegSupportH_Stat = (uint8_t) ( ((_d[1] >> 5U) & (0x03U)) ); + _m->SMRR_SeatInclination_Stat = (uint8_t) ( ((_d[2] & (0x01U)) << 1U) | ((_d[1] >> 7U) & (0x01U)) ); + _m->SMRR_SeatLegSupportL_Stat = (uint8_t) ( ((_d[2] >> 1U) & (0x03U)) ); + _m->SMRR_BackRestInclin_Stat = (uint8_t) ( ((_d[2] >> 3U) & (0x03U)) ); + _m->SMRR_LumbarSupportHeigh_Stat = (uint8_t) ( ((_d[2] >> 5U) & (0x03U)) ); + _m->SMRR_BackRestHeadInclin_Stat = (uint8_t) ( ((_d[3] & (0x01U)) << 1U) | ((_d[2] >> 7U) & (0x01U)) ); + _m->SMRR_LumbarSupportDepth_Stat = (uint8_t) ( ((_d[3] >> 1U) & (0x03U)) ); + _m->SMRR_BackRestWidth_Stat = (uint8_t) ( ((_d[3] >> 3U) & (0x03U)) ); + _m->SMRR_CushionSupport_Stat = (uint8_t) ( ((_d[3] >> 5U) & (0x03U)) ); + _m->SMRR_SeatVentilation_Stat = (uint8_t) ( ((_d[4] & (0x01U)) << 1U) | ((_d[3] >> 7U) & (0x01U)) ); + _m->SMRR_SeatVentBalance_Stat = (uint8_t) ( ((_d[4] >> 1U) & (0x07U)) ); + _m->SMRR_Heating_Stat = (uint8_t) ( ((_d[4] >> 4U) & (0x03U)) ); + _m->SMRR_HeatBalance_Stat = (uint8_t) ( ((_d[5] & (0x01U)) << 2U) | ((_d[4] >> 6U) & (0x03U)) ); + _m->SMRR_SeatMassage_Stat = (uint8_t) ( ((_d[5] >> 1U) & (0x03U)) ); + _m->SMRR_MassageIntens_Stat = (uint8_t) ( ((_d[5] >> 3U) & (0x03U)) ); + _m->SMRR_SeatMassageType_Stat = (uint8_t) ( ((_d[5] >> 5U) & (0x07U)) ); + _m->SMRR_MoreComfort_Req = (uint8_t) ( (_d[6] & (0x01U)) ); + _m->SMRR_CarpetHeat_Stat = (uint8_t) ( ((_d[6] >> 1U) & (0x01U)) ); + _m->SMRR_ActiveSupport_Stat = (uint8_t) ( ((_d[6] >> 2U) & (0x01U)) ); + _m->SMRR_BackrestMassageType_Stat = (uint8_t) ( ((_d[6] >> 3U) & (0x07U)) ); + _m->SMRR_TimerMassage_Stat = (uint8_t) ( (_d[7] & (0x07U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < SMRR_status_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_SMRR_status_candb(&_m->mon1, SMRR_status_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return SMRR_status_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_SMRR_status_candb(SMRR_status_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SMRR_status_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->SMRR_MMmenuActivBtn_Stat & (0x01U)) | ((_m->SMRR_SeatHeight_Stat & (0x03U)) << 3U) | ((_m->SMRR_HeadRestHeight_Stat & (0x03U)) << 5U) | ((_m->SMRR_SeatLongitudinal_Stat & (0x01U)) << 7U) ); + cframe->Data[1] |= (uint8_t) ( ((_m->SMRR_SeatLongitudinal_Stat >> 1U) & (0x01U)) | ((_m->SMRR_HeadRestHeightInclin_Stat & (0x03U)) << 1U) | ((_m->SMRR_SurfaceLongitudinal_Stat & (0x03U)) << 3U) | ((_m->SMRR_SeatLegSupportH_Stat & (0x03U)) << 5U) | ((_m->SMRR_SeatInclination_Stat & (0x01U)) << 7U) ); + cframe->Data[2] |= (uint8_t) ( ((_m->SMRR_SeatInclination_Stat >> 1U) & (0x01U)) | ((_m->SMRR_SeatLegSupportL_Stat & (0x03U)) << 1U) | ((_m->SMRR_BackRestInclin_Stat & (0x03U)) << 3U) | ((_m->SMRR_LumbarSupportHeigh_Stat & (0x03U)) << 5U) | ((_m->SMRR_BackRestHeadInclin_Stat & (0x01U)) << 7U) ); + cframe->Data[3] |= (uint8_t) ( ((_m->SMRR_BackRestHeadInclin_Stat >> 1U) & (0x01U)) | ((_m->SMRR_LumbarSupportDepth_Stat & (0x03U)) << 1U) | ((_m->SMRR_BackRestWidth_Stat & (0x03U)) << 3U) | ((_m->SMRR_CushionSupport_Stat & (0x03U)) << 5U) | ((_m->SMRR_SeatVentilation_Stat & (0x01U)) << 7U) ); + cframe->Data[4] |= (uint8_t) ( ((_m->SMRR_SeatVentilation_Stat >> 1U) & (0x01U)) | ((_m->SMRR_SeatVentBalance_Stat & (0x07U)) << 1U) | ((_m->SMRR_Heating_Stat & (0x03U)) << 4U) | ((_m->SMRR_HeatBalance_Stat & (0x03U)) << 6U) ); + cframe->Data[5] |= (uint8_t) ( ((_m->SMRR_HeatBalance_Stat >> 2U) & (0x01U)) | ((_m->SMRR_SeatMassage_Stat & (0x03U)) << 1U) | ((_m->SMRR_MassageIntens_Stat & (0x03U)) << 3U) | ((_m->SMRR_SeatMassageType_Stat & (0x07U)) << 5U) ); + cframe->Data[6] |= (uint8_t) ( (_m->SMRR_MoreComfort_Req & (0x01U)) | ((_m->SMRR_CarpetHeat_Stat & (0x01U)) << 1U) | ((_m->SMRR_ActiveSupport_Stat & (0x01U)) << 2U) | ((_m->SMRR_BackrestMassageType_Stat & (0x07U)) << 3U) ); + cframe->Data[7] |= (uint8_t) ( (_m->SMRR_TimerMassage_Stat & (0x07U)) ); + + cframe->MsgId = (uint32_t) SMRR_status_CANID; + cframe->DLC = (uint8_t) SMRR_status_DLC; + cframe->IDE = (uint8_t) SMRR_status_IDE; + return SMRR_status_CANID; +} + +#else + +uint32_t Pack_SMRR_status_candb(SMRR_status_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SMRR_status_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->SMRR_MMmenuActivBtn_Stat & (0x01U)) | ((_m->SMRR_SeatHeight_Stat & (0x03U)) << 3U) | ((_m->SMRR_HeadRestHeight_Stat & (0x03U)) << 5U) | ((_m->SMRR_SeatLongitudinal_Stat & (0x01U)) << 7U) ); + _d[1] |= (uint8_t) ( ((_m->SMRR_SeatLongitudinal_Stat >> 1U) & (0x01U)) | ((_m->SMRR_HeadRestHeightInclin_Stat & (0x03U)) << 1U) | ((_m->SMRR_SurfaceLongitudinal_Stat & (0x03U)) << 3U) | ((_m->SMRR_SeatLegSupportH_Stat & (0x03U)) << 5U) | ((_m->SMRR_SeatInclination_Stat & (0x01U)) << 7U) ); + _d[2] |= (uint8_t) ( ((_m->SMRR_SeatInclination_Stat >> 1U) & (0x01U)) | ((_m->SMRR_SeatLegSupportL_Stat & (0x03U)) << 1U) | ((_m->SMRR_BackRestInclin_Stat & (0x03U)) << 3U) | ((_m->SMRR_LumbarSupportHeigh_Stat & (0x03U)) << 5U) | ((_m->SMRR_BackRestHeadInclin_Stat & (0x01U)) << 7U) ); + _d[3] |= (uint8_t) ( ((_m->SMRR_BackRestHeadInclin_Stat >> 1U) & (0x01U)) | ((_m->SMRR_LumbarSupportDepth_Stat & (0x03U)) << 1U) | ((_m->SMRR_BackRestWidth_Stat & (0x03U)) << 3U) | ((_m->SMRR_CushionSupport_Stat & (0x03U)) << 5U) | ((_m->SMRR_SeatVentilation_Stat & (0x01U)) << 7U) ); + _d[4] |= (uint8_t) ( ((_m->SMRR_SeatVentilation_Stat >> 1U) & (0x01U)) | ((_m->SMRR_SeatVentBalance_Stat & (0x07U)) << 1U) | ((_m->SMRR_Heating_Stat & (0x03U)) << 4U) | ((_m->SMRR_HeatBalance_Stat & (0x03U)) << 6U) ); + _d[5] |= (uint8_t) ( ((_m->SMRR_HeatBalance_Stat >> 2U) & (0x01U)) | ((_m->SMRR_SeatMassage_Stat & (0x03U)) << 1U) | ((_m->SMRR_MassageIntens_Stat & (0x03U)) << 3U) | ((_m->SMRR_SeatMassageType_Stat & (0x07U)) << 5U) ); + _d[6] |= (uint8_t) ( (_m->SMRR_MoreComfort_Req & (0x01U)) | ((_m->SMRR_CarpetHeat_Stat & (0x01U)) << 1U) | ((_m->SMRR_ActiveSupport_Stat & (0x01U)) << 2U) | ((_m->SMRR_BackrestMassageType_Stat & (0x07U)) << 3U) ); + _d[7] |= (uint8_t) ( (_m->SMRR_TimerMassage_Stat & (0x07U)) ); + + *_len = (uint8_t) SMRR_status_DLC; + *_ide = (uint8_t) SMRR_status_IDE; + return SMRR_status_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_DocSL_T_FL_candb(DocSL_T_FL_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->DocSL_EjectButtons_Stat = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->DocSL_TiltLimitUpper_Stat = (uint8_t) ( ((_d[0] >> 1U) & (0x01U)) ); + _m->DocSL_TiltLimitLower_Stat = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + _m->DocSL_T_Availability_Stat = (uint8_t) ( ((_d[0] >> 4U) & (0x01U)) ); + _m->DocSL_MechLock_Stat = (uint8_t) ( ((_d[0] >> 5U) & (0x03U)) ); + _m->DocSL_Error_Stat = (uint8_t) ( (_d[1] & (0x03U)) ); + _m->DocSL_TabletTilt_Val = (uint8_t) ( (_d[2] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < DocSL_T_FL_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_DocSL_T_FL_candb(&_m->mon1, DocSL_T_FL_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return DocSL_T_FL_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_DocSL_T_FL_candb(DocSL_T_FL_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(DocSL_T_FL_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->DocSL_EjectButtons_Stat & (0x01U)) | ((_m->DocSL_TiltLimitUpper_Stat & (0x01U)) << 1U) | ((_m->DocSL_TiltLimitLower_Stat & (0x01U)) << 2U) | ((_m->DocSL_T_Availability_Stat & (0x01U)) << 4U) | ((_m->DocSL_MechLock_Stat & (0x03U)) << 5U) ); + cframe->Data[1] |= (uint8_t) ( (_m->DocSL_Error_Stat & (0x03U)) ); + cframe->Data[2] |= (uint8_t) ( (_m->DocSL_TabletTilt_Val & (0xFFU)) ); + + cframe->MsgId = (uint32_t) DocSL_T_FL_CANID; + cframe->DLC = (uint8_t) DocSL_T_FL_DLC; + cframe->IDE = (uint8_t) DocSL_T_FL_IDE; + return DocSL_T_FL_CANID; +} + +#else + +uint32_t Pack_DocSL_T_FL_candb(DocSL_T_FL_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(DocSL_T_FL_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->DocSL_EjectButtons_Stat & (0x01U)) | ((_m->DocSL_TiltLimitUpper_Stat & (0x01U)) << 1U) | ((_m->DocSL_TiltLimitLower_Stat & (0x01U)) << 2U) | ((_m->DocSL_T_Availability_Stat & (0x01U)) << 4U) | ((_m->DocSL_MechLock_Stat & (0x03U)) << 5U) ); + _d[1] |= (uint8_t) ( (_m->DocSL_Error_Stat & (0x03U)) ); + _d[2] |= (uint8_t) ( (_m->DocSL_TabletTilt_Val & (0xFFU)) ); + + *_len = (uint8_t) DocSL_T_FL_DLC; + *_ide = (uint8_t) DocSL_T_FL_IDE; + return DocSL_T_FL_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_DocSR_T_FR_candb(DocSR_T_FR_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->DocSR_EjectButtons_Stat = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->DocSR_TiltLimitUpper_Stat = (uint8_t) ( ((_d[0] >> 1U) & (0x01U)) ); + _m->DocSR_TiltLimitLower_Stat = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + _m->DocSR_T_Availability_Stat = (uint8_t) ( ((_d[0] >> 4U) & (0x01U)) ); + _m->DocSR_MechLock_Stat = (uint8_t) ( ((_d[0] >> 5U) & (0x03U)) ); + _m->DocSR_Error_Stat = (uint8_t) ( (_d[1] & (0x03U)) ); + _m->DocSR_TabletTilt_Val = (uint8_t) ( (_d[2] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < DocSR_T_FR_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_DocSR_T_FR_candb(&_m->mon1, DocSR_T_FR_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return DocSR_T_FR_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_DocSR_T_FR_candb(DocSR_T_FR_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(DocSR_T_FR_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->DocSR_EjectButtons_Stat & (0x01U)) | ((_m->DocSR_TiltLimitUpper_Stat & (0x01U)) << 1U) | ((_m->DocSR_TiltLimitLower_Stat & (0x01U)) << 2U) | ((_m->DocSR_T_Availability_Stat & (0x01U)) << 4U) | ((_m->DocSR_MechLock_Stat & (0x03U)) << 5U) ); + cframe->Data[1] |= (uint8_t) ( (_m->DocSR_Error_Stat & (0x03U)) ); + cframe->Data[2] |= (uint8_t) ( (_m->DocSR_TabletTilt_Val & (0xFFU)) ); + + cframe->MsgId = (uint32_t) DocSR_T_FR_CANID; + cframe->DLC = (uint8_t) DocSR_T_FR_DLC; + cframe->IDE = (uint8_t) DocSR_T_FR_IDE; + return DocSR_T_FR_CANID; +} + +#else + +uint32_t Pack_DocSR_T_FR_candb(DocSR_T_FR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(DocSR_T_FR_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->DocSR_EjectButtons_Stat & (0x01U)) | ((_m->DocSR_TiltLimitUpper_Stat & (0x01U)) << 1U) | ((_m->DocSR_TiltLimitLower_Stat & (0x01U)) << 2U) | ((_m->DocSR_T_Availability_Stat & (0x01U)) << 4U) | ((_m->DocSR_MechLock_Stat & (0x03U)) << 5U) ); + _d[1] |= (uint8_t) ( (_m->DocSR_Error_Stat & (0x03U)) ); + _d[2] |= (uint8_t) ( (_m->DocSR_TabletTilt_Val & (0xFFU)) ); + + *_len = (uint8_t) DocSR_T_FR_DLC; + *_ide = (uint8_t) DocSR_T_FR_IDE; + return DocSR_T_FR_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_VAU_TPMS_Msg_candb(VAU_TPMS_Msg_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->VAU_TPMS_TireLocation = (uint8_t) ( (_d[0] & (0xFFU)) ); + _m->VAU_TPMS_TirePressureRR_ro = (uint8_t) ( (_d[1] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->VAU_TPMS_TirePressureRR_phys = (uint16_t) CANDB_VAU_TPMS_TirePressureRR_ro_fromS(_m->VAU_TPMS_TirePressureRR_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->VAU_TPMS_TirePressureRL_ro = (uint8_t) ( (_d[1] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->VAU_TPMS_TirePressureRL_phys = (uint16_t) CANDB_VAU_TPMS_TirePressureRL_ro_fromS(_m->VAU_TPMS_TirePressureRL_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->VAU_TPMS_TirePressureFR_ro = (uint8_t) ( (_d[1] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->VAU_TPMS_TirePressureFR_phys = (uint16_t) CANDB_VAU_TPMS_TirePressureFR_ro_fromS(_m->VAU_TPMS_TirePressureFR_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->VAU_TPMS_TirePressureFL_ro = (uint8_t) ( (_d[1] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->VAU_TPMS_TirePressureFL_phys = (uint16_t) CANDB_VAU_TPMS_TirePressureFL_ro_fromS(_m->VAU_TPMS_TirePressureFL_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->VAU_TPMS_SensorTemperatureRR_ro = (uint8_t) ( (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->VAU_TPMS_SensorTemperatureRR_phys = (int16_t) CANDB_VAU_TPMS_SensorTemperatureRR_ro_fromS(_m->VAU_TPMS_SensorTemperatureRR_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->VAU_TPMS_SensorTemperatureRL_ro = (uint8_t) ( (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->VAU_TPMS_SensorTemperatureRL_phys = (int16_t) CANDB_VAU_TPMS_SensorTemperatureRL_ro_fromS(_m->VAU_TPMS_SensorTemperatureRL_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->VAU_TPMS_SensorTemperatureFR_ro = (uint8_t) ( (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->VAU_TPMS_SensorTemperatureFR_phys = (int16_t) CANDB_VAU_TPMS_SensorTemperatureFR_ro_fromS(_m->VAU_TPMS_SensorTemperatureFR_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->VAU_TPMS_SensorTemperatureFL_ro = (uint8_t) ( (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->VAU_TPMS_SensorTemperatureFL_phys = (int16_t) CANDB_VAU_TPMS_SensorTemperatureFL_ro_fromS(_m->VAU_TPMS_SensorTemperatureFL_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->VAU_TPMS_PressureSetSuccessRL = (uint8_t) ( (_d[3] & (0x01U)) ); + _m->VAU_TPMS_PressureSetSuccessFL = (uint8_t) ( (_d[3] & (0x01U)) ); + _m->VAU_TPMS_PressureSetSuccessRR = (uint8_t) ( (_d[3] & (0x01U)) ); + _m->VAU_TPMS_PressureSetSuccessFR = (uint8_t) ( (_d[3] & (0x01U)) ); + _m->VAU_TPMS_PressureSetSensorErrFR = (uint8_t) ( ((_d[3] >> 1U) & (0x01U)) ); + _m->VAU_TPMS_PressureSetSensorErrFL = (uint8_t) ( ((_d[3] >> 1U) & (0x01U)) ); + _m->VAU_TPMS_PressureSetSensorErrRL = (uint8_t) ( ((_d[3] >> 1U) & (0x01U)) ); + _m->VAU_TPMS_PressureSetSensorErrRR = (uint8_t) ( ((_d[3] >> 1U) & (0x01U)) ); + _m->VAU_TPMS_PressureSetErrFR = (uint8_t) ( ((_d[3] >> 2U) & (0x01U)) ); + _m->VAU_TPMS_PressureSetErrRL = (uint8_t) ( ((_d[3] >> 2U) & (0x01U)) ); + _m->VAU_TPMS_PressureSetErrFL = (uint8_t) ( ((_d[3] >> 2U) & (0x01U)) ); + _m->VAU_TPMS_PressureSetErrRR = (uint8_t) ( ((_d[3] >> 2U) & (0x01U)) ); + _m->VAU_TPMS_BatteryStatusRL = (uint8_t) ( ((_d[3] >> 3U) & (0x01U)) ); + _m->VAU_TPMS_BatteryStatusRR = (uint8_t) ( ((_d[3] >> 3U) & (0x01U)) ); + _m->VAU_TPMS_BatteryStatusFL = (uint8_t) ( ((_d[3] >> 3U) & (0x01U)) ); + _m->VAU_TPMS_BatteryStatusFR = (uint8_t) ( ((_d[3] >> 3U) & (0x01U)) ); + _m->VAU_TPMS_SensorEmissionCauseFL = (uint8_t) ( ((_d[3] >> 4U) & (0x03U)) ); + _m->VAU_TPMS_SensorEmissionCauseRR = (uint8_t) ( ((_d[3] >> 4U) & (0x03U)) ); + _m->VAU_TPMS_SensorEmissionCauseRL = (uint8_t) ( ((_d[3] >> 4U) & (0x03U)) ); + _m->VAU_TPMS_SensorEmissionCauseFR = (uint8_t) ( ((_d[3] >> 4U) & (0x03U)) ); + _m->VAU_TPMS_SensorOperationModeRR = (uint8_t) ( ((_d[3] >> 6U) & (0x03U)) ); + _m->VAU_TPMS_SensorOperationModeRL = (uint8_t) ( ((_d[3] >> 6U) & (0x03U)) ); + _m->VAU_TPMS_SensorOperationModeFR = (uint8_t) ( ((_d[3] >> 6U) & (0x03U)) ); + _m->VAU_TPMS_SensorOperationModeFL = (uint8_t) ( ((_d[3] >> 6U) & (0x03U)) ); + _m->VAU_TPMS_DataTimestampRR = (uint16_t) ( ((_d[6] & (0xFFU)) << 8U) | (_d[5] & (0xFFU)) ); + _m->VAU_TPMS_DataTimestampRL = (uint16_t) ( ((_d[6] & (0xFFU)) << 8U) | (_d[5] & (0xFFU)) ); + _m->VAU_TPMS_DataTimestampFR = (uint16_t) ( ((_d[6] & (0xFFU)) << 8U) | (_d[5] & (0xFFU)) ); + _m->VAU_TPMS_DataTimestampFL = (uint16_t) ( ((_d[6] & (0xFFU)) << 8U) | (_d[5] & (0xFFU)) ); + _m->VAU_TPMS_TirePressureFaultRL = (uint8_t) ( (_d[7] & (0x07U)) ); + _m->VAU_TPMS_TirePressureFaultFR = (uint8_t) ( (_d[7] & (0x07U)) ); + _m->VAU_TPMS_TirePressureFaultFL = (uint8_t) ( (_d[7] & (0x07U)) ); + _m->VAU_TPMS_TirePressureFaultRR = (uint8_t) ( (_d[7] & (0x07U)) ); + _m->TPMS_SensorTempFaultFR = (uint8_t) ( ((_d[7] >> 3U) & (0x03U)) ); + _m->TPMS_SensorTempFaultRR = (uint8_t) ( ((_d[7] >> 3U) & (0x03U)) ); + _m->TPMS_SensorTempFaultFL = (uint8_t) ( ((_d[7] >> 3U) & (0x03U)) ); + _m->TPMS_SensorTempFaultRL = (uint8_t) ( ((_d[7] >> 3U) & (0x03U)) ); + _m->VAU_TPMS_SensorFaultFR = (uint8_t) ( ((_d[7] >> 5U) & (0x01U)) ); + _m->VAU_TPMS_SensorFaultRR = (uint8_t) ( ((_d[7] >> 5U) & (0x01U)) ); + _m->VAU_TPMS_SensorFaultRL = (uint8_t) ( ((_d[7] >> 5U) & (0x01U)) ); + _m->VAU_TPMS_SensorFaultFL = (uint8_t) ( ((_d[7] >> 5U) & (0x01U)) ); + _m->VAU_TPMS_SensorPresenceFR = (uint8_t) ( ((_d[7] >> 6U) & (0x01U)) ); + _m->VAU_TPMS_SensorPresenceRL = (uint8_t) ( ((_d[7] >> 6U) & (0x01U)) ); + _m->VAU_TPMS_SensorPresenceFL = (uint8_t) ( ((_d[7] >> 6U) & (0x01U)) ); + _m->VAU_TPMS_SensorPresenceRR = (uint8_t) ( ((_d[7] >> 6U) & (0x01U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < VAU_TPMS_Msg_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_VAU_TPMS_Msg_candb(&_m->mon1, VAU_TPMS_Msg_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return VAU_TPMS_Msg_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_VAU_TPMS_Msg_candb(VAU_TPMS_Msg_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(VAU_TPMS_Msg_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->VAU_TPMS_TirePressureRR_ro = (uint8_t) CANDB_VAU_TPMS_TirePressureRR_ro_toS(_m->VAU_TPMS_TirePressureRR_phys); + _m->VAU_TPMS_TirePressureRL_ro = (uint8_t) CANDB_VAU_TPMS_TirePressureRL_ro_toS(_m->VAU_TPMS_TirePressureRL_phys); + _m->VAU_TPMS_TirePressureFR_ro = (uint8_t) CANDB_VAU_TPMS_TirePressureFR_ro_toS(_m->VAU_TPMS_TirePressureFR_phys); + _m->VAU_TPMS_TirePressureFL_ro = (uint8_t) CANDB_VAU_TPMS_TirePressureFL_ro_toS(_m->VAU_TPMS_TirePressureFL_phys); + _m->VAU_TPMS_SensorTemperatureRR_ro = (uint8_t) CANDB_VAU_TPMS_SensorTemperatureRR_ro_toS(_m->VAU_TPMS_SensorTemperatureRR_phys); + _m->VAU_TPMS_SensorTemperatureRL_ro = (uint8_t) CANDB_VAU_TPMS_SensorTemperatureRL_ro_toS(_m->VAU_TPMS_SensorTemperatureRL_phys); + _m->VAU_TPMS_SensorTemperatureFR_ro = (uint8_t) CANDB_VAU_TPMS_SensorTemperatureFR_ro_toS(_m->VAU_TPMS_SensorTemperatureFR_phys); + _m->VAU_TPMS_SensorTemperatureFL_ro = (uint8_t) CANDB_VAU_TPMS_SensorTemperatureFL_ro_toS(_m->VAU_TPMS_SensorTemperatureFL_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->VAU_TPMS_TireLocation & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->VAU_TPMS_TirePressureRR_ro & (0xFFU)) | (_m->VAU_TPMS_TirePressureRL_ro & (0xFFU)) | (_m->VAU_TPMS_TirePressureFR_ro & (0xFFU)) | (_m->VAU_TPMS_TirePressureFL_ro & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->VAU_TPMS_SensorTemperatureRR_ro & (0xFFU)) | (_m->VAU_TPMS_SensorTemperatureRL_ro & (0xFFU)) | (_m->VAU_TPMS_SensorTemperatureFR_ro & (0xFFU)) | (_m->VAU_TPMS_SensorTemperatureFL_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->VAU_TPMS_PressureSetSuccessRL & (0x01U)) | (_m->VAU_TPMS_PressureSetSuccessFL & (0x01U)) | (_m->VAU_TPMS_PressureSetSuccessRR & (0x01U)) | (_m->VAU_TPMS_PressureSetSuccessFR & (0x01U)) | ((_m->VAU_TPMS_PressureSetSensorErrFR & (0x01U)) << 1U) | ((_m->VAU_TPMS_PressureSetSensorErrFL & (0x01U)) << 1U) | ((_m->VAU_TPMS_PressureSetSensorErrRL & (0x01U)) << 1U) | ((_m->VAU_TPMS_PressureSetSensorErrRR & (0x01U)) << 1U) | ((_m->VAU_TPMS_PressureSetErrFR & (0x01U)) << 2U) | ((_m->VAU_TPMS_PressureSetErrRL & (0x01U)) << 2U) | ((_m->VAU_TPMS_PressureSetErrFL & (0x01U)) << 2U) | ((_m->VAU_TPMS_PressureSetErrRR & (0x01U)) << 2U) | ((_m->VAU_TPMS_BatteryStatusRL & (0x01U)) << 3U) | ((_m->VAU_TPMS_BatteryStatusRR & (0x01U)) << 3U) | ((_m->VAU_TPMS_BatteryStatusFL & (0x01U)) << 3U) | ((_m->VAU_TPMS_BatteryStatusFR & (0x01U)) << 3U) | ((_m->VAU_TPMS_SensorEmissionCauseFL & (0x03U)) << 4U) | ((_m->VAU_TPMS_SensorEmissionCauseRR & (0x03U)) << 4U) | ((_m->VAU_TPMS_SensorEmissionCauseRL & (0x03U)) << 4U) | ((_m->VAU_TPMS_SensorEmissionCauseFR & (0x03U)) << 4U) | ((_m->VAU_TPMS_SensorOperationModeRR & (0x03U)) << 6U) | ((_m->VAU_TPMS_SensorOperationModeRL & (0x03U)) << 6U) | ((_m->VAU_TPMS_SensorOperationModeFR & (0x03U)) << 6U) | ((_m->VAU_TPMS_SensorOperationModeFL & (0x03U)) << 6U) ); + cframe->Data[5] |= (uint8_t) ( (_m->VAU_TPMS_DataTimestampRR & (0xFFU)) | (_m->VAU_TPMS_DataTimestampRL & (0xFFU)) | (_m->VAU_TPMS_DataTimestampFR & (0xFFU)) | (_m->VAU_TPMS_DataTimestampFL & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->VAU_TPMS_DataTimestampRR >> 8U) & (0xFFU)) | ((_m->VAU_TPMS_DataTimestampRL >> 8U) & (0xFFU)) | ((_m->VAU_TPMS_DataTimestampFR >> 8U) & (0xFFU)) | ((_m->VAU_TPMS_DataTimestampFL >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->VAU_TPMS_TirePressureFaultRL & (0x07U)) | (_m->VAU_TPMS_TirePressureFaultFR & (0x07U)) | (_m->VAU_TPMS_TirePressureFaultFL & (0x07U)) | (_m->VAU_TPMS_TirePressureFaultRR & (0x07U)) | ((_m->TPMS_SensorTempFaultFR & (0x03U)) << 3U) | ((_m->TPMS_SensorTempFaultRR & (0x03U)) << 3U) | ((_m->TPMS_SensorTempFaultFL & (0x03U)) << 3U) | ((_m->TPMS_SensorTempFaultRL & (0x03U)) << 3U) | ((_m->VAU_TPMS_SensorFaultFR & (0x01U)) << 5U) | ((_m->VAU_TPMS_SensorFaultRR & (0x01U)) << 5U) | ((_m->VAU_TPMS_SensorFaultRL & (0x01U)) << 5U) | ((_m->VAU_TPMS_SensorFaultFL & (0x01U)) << 5U) | ((_m->VAU_TPMS_SensorPresenceFR & (0x01U)) << 6U) | ((_m->VAU_TPMS_SensorPresenceRL & (0x01U)) << 6U) | ((_m->VAU_TPMS_SensorPresenceFL & (0x01U)) << 6U) | ((_m->VAU_TPMS_SensorPresenceRR & (0x01U)) << 6U) ); + + cframe->MsgId = (uint32_t) VAU_TPMS_Msg_CANID; + cframe->DLC = (uint8_t) VAU_TPMS_Msg_DLC; + cframe->IDE = (uint8_t) VAU_TPMS_Msg_IDE; + return VAU_TPMS_Msg_CANID; +} + +#else + +uint32_t Pack_VAU_TPMS_Msg_candb(VAU_TPMS_Msg_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(VAU_TPMS_Msg_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->VAU_TPMS_TirePressureRR_ro = (uint8_t) CANDB_VAU_TPMS_TirePressureRR_ro_toS(_m->VAU_TPMS_TirePressureRR_phys); + _m->VAU_TPMS_TirePressureRL_ro = (uint8_t) CANDB_VAU_TPMS_TirePressureRL_ro_toS(_m->VAU_TPMS_TirePressureRL_phys); + _m->VAU_TPMS_TirePressureFR_ro = (uint8_t) CANDB_VAU_TPMS_TirePressureFR_ro_toS(_m->VAU_TPMS_TirePressureFR_phys); + _m->VAU_TPMS_TirePressureFL_ro = (uint8_t) CANDB_VAU_TPMS_TirePressureFL_ro_toS(_m->VAU_TPMS_TirePressureFL_phys); + _m->VAU_TPMS_SensorTemperatureRR_ro = (uint8_t) CANDB_VAU_TPMS_SensorTemperatureRR_ro_toS(_m->VAU_TPMS_SensorTemperatureRR_phys); + _m->VAU_TPMS_SensorTemperatureRL_ro = (uint8_t) CANDB_VAU_TPMS_SensorTemperatureRL_ro_toS(_m->VAU_TPMS_SensorTemperatureRL_phys); + _m->VAU_TPMS_SensorTemperatureFR_ro = (uint8_t) CANDB_VAU_TPMS_SensorTemperatureFR_ro_toS(_m->VAU_TPMS_SensorTemperatureFR_phys); + _m->VAU_TPMS_SensorTemperatureFL_ro = (uint8_t) CANDB_VAU_TPMS_SensorTemperatureFL_ro_toS(_m->VAU_TPMS_SensorTemperatureFL_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->VAU_TPMS_TireLocation & (0xFFU)) ); + _d[1] |= (uint8_t) ( (_m->VAU_TPMS_TirePressureRR_ro & (0xFFU)) | (_m->VAU_TPMS_TirePressureRL_ro & (0xFFU)) | (_m->VAU_TPMS_TirePressureFR_ro & (0xFFU)) | (_m->VAU_TPMS_TirePressureFL_ro & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->VAU_TPMS_SensorTemperatureRR_ro & (0xFFU)) | (_m->VAU_TPMS_SensorTemperatureRL_ro & (0xFFU)) | (_m->VAU_TPMS_SensorTemperatureFR_ro & (0xFFU)) | (_m->VAU_TPMS_SensorTemperatureFL_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->VAU_TPMS_PressureSetSuccessRL & (0x01U)) | (_m->VAU_TPMS_PressureSetSuccessFL & (0x01U)) | (_m->VAU_TPMS_PressureSetSuccessRR & (0x01U)) | (_m->VAU_TPMS_PressureSetSuccessFR & (0x01U)) | ((_m->VAU_TPMS_PressureSetSensorErrFR & (0x01U)) << 1U) | ((_m->VAU_TPMS_PressureSetSensorErrFL & (0x01U)) << 1U) | ((_m->VAU_TPMS_PressureSetSensorErrRL & (0x01U)) << 1U) | ((_m->VAU_TPMS_PressureSetSensorErrRR & (0x01U)) << 1U) | ((_m->VAU_TPMS_PressureSetErrFR & (0x01U)) << 2U) | ((_m->VAU_TPMS_PressureSetErrRL & (0x01U)) << 2U) | ((_m->VAU_TPMS_PressureSetErrFL & (0x01U)) << 2U) | ((_m->VAU_TPMS_PressureSetErrRR & (0x01U)) << 2U) | ((_m->VAU_TPMS_BatteryStatusRL & (0x01U)) << 3U) | ((_m->VAU_TPMS_BatteryStatusRR & (0x01U)) << 3U) | ((_m->VAU_TPMS_BatteryStatusFL & (0x01U)) << 3U) | ((_m->VAU_TPMS_BatteryStatusFR & (0x01U)) << 3U) | ((_m->VAU_TPMS_SensorEmissionCauseFL & (0x03U)) << 4U) | ((_m->VAU_TPMS_SensorEmissionCauseRR & (0x03U)) << 4U) | ((_m->VAU_TPMS_SensorEmissionCauseRL & (0x03U)) << 4U) | ((_m->VAU_TPMS_SensorEmissionCauseFR & (0x03U)) << 4U) | ((_m->VAU_TPMS_SensorOperationModeRR & (0x03U)) << 6U) | ((_m->VAU_TPMS_SensorOperationModeRL & (0x03U)) << 6U) | ((_m->VAU_TPMS_SensorOperationModeFR & (0x03U)) << 6U) | ((_m->VAU_TPMS_SensorOperationModeFL & (0x03U)) << 6U) ); + _d[5] |= (uint8_t) ( (_m->VAU_TPMS_DataTimestampRR & (0xFFU)) | (_m->VAU_TPMS_DataTimestampRL & (0xFFU)) | (_m->VAU_TPMS_DataTimestampFR & (0xFFU)) | (_m->VAU_TPMS_DataTimestampFL & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->VAU_TPMS_DataTimestampRR >> 8U) & (0xFFU)) | ((_m->VAU_TPMS_DataTimestampRL >> 8U) & (0xFFU)) | ((_m->VAU_TPMS_DataTimestampFR >> 8U) & (0xFFU)) | ((_m->VAU_TPMS_DataTimestampFL >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->VAU_TPMS_TirePressureFaultRL & (0x07U)) | (_m->VAU_TPMS_TirePressureFaultFR & (0x07U)) | (_m->VAU_TPMS_TirePressureFaultFL & (0x07U)) | (_m->VAU_TPMS_TirePressureFaultRR & (0x07U)) | ((_m->TPMS_SensorTempFaultFR & (0x03U)) << 3U) | ((_m->TPMS_SensorTempFaultRR & (0x03U)) << 3U) | ((_m->TPMS_SensorTempFaultFL & (0x03U)) << 3U) | ((_m->TPMS_SensorTempFaultRL & (0x03U)) << 3U) | ((_m->VAU_TPMS_SensorFaultFR & (0x01U)) << 5U) | ((_m->VAU_TPMS_SensorFaultRR & (0x01U)) << 5U) | ((_m->VAU_TPMS_SensorFaultRL & (0x01U)) << 5U) | ((_m->VAU_TPMS_SensorFaultFL & (0x01U)) << 5U) | ((_m->VAU_TPMS_SensorPresenceFR & (0x01U)) << 6U) | ((_m->VAU_TPMS_SensorPresenceRL & (0x01U)) << 6U) | ((_m->VAU_TPMS_SensorPresenceFL & (0x01U)) << 6U) | ((_m->VAU_TPMS_SensorPresenceRR & (0x01U)) << 6U) ); + + *_len = (uint8_t) VAU_TPMS_Msg_DLC; + *_ide = (uint8_t) VAU_TPMS_Msg_IDE; + return VAU_TPMS_Msg_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_CCU_Errors_candb(CCU_Errors_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->CCU_IncarTempErrF_Stat = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->CCU_IncarTempErrR_Stat = (uint8_t) ( ((_d[0] >> 1U) & (0x01U)) ); + _m->CCU_DuctTempSenErrF_Stat = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + _m->CCU_DuctTempSenErrR_Stat = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + _m->CCU_EvaTempSenErrF_Stat = (uint8_t) ( ((_d[0] >> 4U) & (0x01U)) ); + _m->CCU_EvaTempSenErrR_Stat = (uint8_t) ( ((_d[0] >> 5U) & (0x01U)) ); + _m->CCU_DeflectorSwErrF_Stat = (uint8_t) ( ((_d[0] >> 6U) & (0x01U)) ); + _m->CCU_DeflectorSwErrR_Stat = (uint8_t) ( ((_d[0] >> 7U) & (0x01U)) ); + _m->CCU_PressSenErr_Stat = (uint8_t) ( (_d[1] & (0x01U)) ); + _m->CCU_AmbienTemptSenErr_Stat = (uint8_t) ( ((_d[1] >> 1U) & (0x01U)) ); + _m->CCU_SealingValveErr_Stat = (uint8_t) ( ((_d[1] >> 2U) & (0x01U)) ); + _m->CCU_ETXVerr_Stat = (uint8_t) ( ((_d[1] >> 3U) & (0x01U)) ); + _m->CCU_HVACfanOrTXVerrF_Stat = (uint8_t) ( ((_d[1] >> 4U) & (0x01U)) ); + _m->CCU_HVACfanOrTXVerrR_Stat = (uint8_t) ( ((_d[1] >> 5U) & (0x01U)) ); + _m->CCU_ActuatorErrF_Stat = (uint8_t) ( ((_d[1] >> 6U) & (0x01U)) ); + _m->CCU_ActuatorErrR_Stat = (uint8_t) ( ((_d[1] >> 7U) & (0x01U)) ); + _m->CCU_UltravioletErr_Stat = (uint8_t) ( (_d[2] & (0x03U)) ); + _m->CCU_VinRecordErr_Stat = (uint8_t) ( ((_d[2] >> 2U) & (0x01U)) ); + _m->CCU_AirQualSenErr_Stat = (uint8_t) ( ((_d[2] >> 3U) & (0x07U)) ); + _m->CCU_CommErr_Stat = (uint8_t) ( ((_d[2] >> 6U) & (0x01U)) ); + _m->CCU_TWVerr_Stat = (uint8_t) ( ((_d[2] >> 7U) & (0x01U)) ); + _m->CCU_IonizationErr_Stat = (uint8_t) ( (_d[3] & (0x07U)) ); + _m->CCU_AromaErr_Stat = (uint8_t) ( ((_d[3] >> 3U) & (0x07U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < CCU_Errors_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_CCU_Errors_candb(&_m->mon1, CCU_Errors_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return CCU_Errors_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_CCU_Errors_candb(CCU_Errors_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(CCU_Errors_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->CCU_IncarTempErrF_Stat & (0x01U)) | ((_m->CCU_IncarTempErrR_Stat & (0x01U)) << 1U) | ((_m->CCU_DuctTempSenErrF_Stat & (0x01U)) << 2U) | ((_m->CCU_DuctTempSenErrR_Stat & (0x01U)) << 3U) | ((_m->CCU_EvaTempSenErrF_Stat & (0x01U)) << 4U) | ((_m->CCU_EvaTempSenErrR_Stat & (0x01U)) << 5U) | ((_m->CCU_DeflectorSwErrF_Stat & (0x01U)) << 6U) | ((_m->CCU_DeflectorSwErrR_Stat & (0x01U)) << 7U) ); + cframe->Data[1] |= (uint8_t) ( (_m->CCU_PressSenErr_Stat & (0x01U)) | ((_m->CCU_AmbienTemptSenErr_Stat & (0x01U)) << 1U) | ((_m->CCU_SealingValveErr_Stat & (0x01U)) << 2U) | ((_m->CCU_ETXVerr_Stat & (0x01U)) << 3U) | ((_m->CCU_HVACfanOrTXVerrF_Stat & (0x01U)) << 4U) | ((_m->CCU_HVACfanOrTXVerrR_Stat & (0x01U)) << 5U) | ((_m->CCU_ActuatorErrF_Stat & (0x01U)) << 6U) | ((_m->CCU_ActuatorErrR_Stat & (0x01U)) << 7U) ); + cframe->Data[2] |= (uint8_t) ( (_m->CCU_UltravioletErr_Stat & (0x03U)) | ((_m->CCU_VinRecordErr_Stat & (0x01U)) << 2U) | ((_m->CCU_AirQualSenErr_Stat & (0x07U)) << 3U) | ((_m->CCU_CommErr_Stat & (0x01U)) << 6U) | ((_m->CCU_TWVerr_Stat & (0x01U)) << 7U) ); + cframe->Data[3] |= (uint8_t) ( (_m->CCU_IonizationErr_Stat & (0x07U)) | ((_m->CCU_AromaErr_Stat & (0x07U)) << 3U) ); + + cframe->MsgId = (uint32_t) CCU_Errors_CANID; + cframe->DLC = (uint8_t) CCU_Errors_DLC; + cframe->IDE = (uint8_t) CCU_Errors_IDE; + return CCU_Errors_CANID; +} + +#else + +uint32_t Pack_CCU_Errors_candb(CCU_Errors_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(CCU_Errors_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->CCU_IncarTempErrF_Stat & (0x01U)) | ((_m->CCU_IncarTempErrR_Stat & (0x01U)) << 1U) | ((_m->CCU_DuctTempSenErrF_Stat & (0x01U)) << 2U) | ((_m->CCU_DuctTempSenErrR_Stat & (0x01U)) << 3U) | ((_m->CCU_EvaTempSenErrF_Stat & (0x01U)) << 4U) | ((_m->CCU_EvaTempSenErrR_Stat & (0x01U)) << 5U) | ((_m->CCU_DeflectorSwErrF_Stat & (0x01U)) << 6U) | ((_m->CCU_DeflectorSwErrR_Stat & (0x01U)) << 7U) ); + _d[1] |= (uint8_t) ( (_m->CCU_PressSenErr_Stat & (0x01U)) | ((_m->CCU_AmbienTemptSenErr_Stat & (0x01U)) << 1U) | ((_m->CCU_SealingValveErr_Stat & (0x01U)) << 2U) | ((_m->CCU_ETXVerr_Stat & (0x01U)) << 3U) | ((_m->CCU_HVACfanOrTXVerrF_Stat & (0x01U)) << 4U) | ((_m->CCU_HVACfanOrTXVerrR_Stat & (0x01U)) << 5U) | ((_m->CCU_ActuatorErrF_Stat & (0x01U)) << 6U) | ((_m->CCU_ActuatorErrR_Stat & (0x01U)) << 7U) ); + _d[2] |= (uint8_t) ( (_m->CCU_UltravioletErr_Stat & (0x03U)) | ((_m->CCU_VinRecordErr_Stat & (0x01U)) << 2U) | ((_m->CCU_AirQualSenErr_Stat & (0x07U)) << 3U) | ((_m->CCU_CommErr_Stat & (0x01U)) << 6U) | ((_m->CCU_TWVerr_Stat & (0x01U)) << 7U) ); + _d[3] |= (uint8_t) ( (_m->CCU_IonizationErr_Stat & (0x07U)) | ((_m->CCU_AromaErr_Stat & (0x07U)) << 3U) ); + + *_len = (uint8_t) CCU_Errors_DLC; + *_ide = (uint8_t) CCU_Errors_IDE; + return CCU_Errors_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_CCU_Msg3_candb(CCU_Msg3_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->CCU_FAN_Req = (uint8_t) ( (_d[0] & (0x7FU)) ); + _m->CCU_RestMode_Stat = (uint8_t) ( (_d[1] & (0x03U)) ); + _m->CCU_IncarTempSum_Val_ro = (uint8_t) ( (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->CCU_IncarTempSum_Val_phys = (sigfloat_t)(CANDB_CCU_IncarTempSum_Val_ro_fromS(_m->CCU_IncarTempSum_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->CCU_MSG3_RC = (uint8_t) ( (_d[3] & (0x0FU)) ); + _m->CCU_MSG3_CS = (uint8_t) ( (_d[4] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < CCU_Msg3_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_CCU_Msg3_candb(&_m->mon1, CCU_Msg3_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return CCU_Msg3_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_CCU_Msg3_candb(CCU_Msg3_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(CCU_Msg3_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->CCU_IncarTempSum_Val_ro = (uint8_t) CANDB_CCU_IncarTempSum_Val_ro_toS(_m->CCU_IncarTempSum_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->CCU_FAN_Req & (0x7FU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->CCU_RestMode_Stat & (0x03U)) ); + cframe->Data[2] |= (uint8_t) ( (_m->CCU_IncarTempSum_Val_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->CCU_MSG3_RC & (0x0FU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->CCU_MSG3_CS & (0xFFU)) ); + + cframe->MsgId = (uint32_t) CCU_Msg3_CANID; + cframe->DLC = (uint8_t) CCU_Msg3_DLC; + cframe->IDE = (uint8_t) CCU_Msg3_IDE; + return CCU_Msg3_CANID; +} + +#else + +uint32_t Pack_CCU_Msg3_candb(CCU_Msg3_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(CCU_Msg3_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->CCU_IncarTempSum_Val_ro = (uint8_t) CANDB_CCU_IncarTempSum_Val_ro_toS(_m->CCU_IncarTempSum_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->CCU_FAN_Req & (0x7FU)) ); + _d[1] |= (uint8_t) ( (_m->CCU_RestMode_Stat & (0x03U)) ); + _d[2] |= (uint8_t) ( (_m->CCU_IncarTempSum_Val_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->CCU_MSG3_RC & (0x0FU)) ); + _d[4] |= (uint8_t) ( (_m->CCU_MSG3_CS & (0xFFU)) ); + + *_len = (uint8_t) CCU_Msg3_DLC; + *_ide = (uint8_t) CCU_Msg3_IDE; + return CCU_Msg3_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_Cmd_candb(FIU_Cmd_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->FIU_RunningBoards_Stat = (uint8_t) ( (_d[0] & (0x03U)) ); + _m->FIU_Vehicle_DrvMode_Req = (uint8_t) ( ((_d[0] >> 5U) & (0x07U)) ); + _m->FIU_RStrapCntrl_Req = (uint8_t) ( (_d[1] & (0x01U)) ); + _m->FIU_RStrapCushCntrl_Req = (uint8_t) ( ((_d[1] >> 1U) & (0x01U)) ); + _m->FIU_LStrapCntrl_Req = (uint8_t) ( ((_d[1] >> 2U) & (0x01U)) ); + _m->FIU_LStrapCushCntrl_Req = (uint8_t) ( ((_d[1] >> 3U) & (0x01U)) ); + _m->FIU_Lift_Req = (uint8_t) ( ((_d[1] >> 4U) & (0x01U)) ); + _m->FIU_HDC_Req = (uint8_t) ( ((_d[1] >> 5U) & (0x01U)) ); + _m->FIU_Prolongation_Req = (uint8_t) ( ((_d[1] >> 6U) & (0x01U)) ); + _m->FIU_ServiceMode_Req = (uint8_t) ( ((_d[1] >> 7U) & (0x01U)) ); + _m->FIU_PressureSet_Req = (uint8_t) ( (_d[3] & (0x01U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < FIU_Cmd_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_FIU_Cmd_candb(&_m->mon1, FIU_Cmd_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return FIU_Cmd_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_FIU_Cmd_candb(FIU_Cmd_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_Cmd_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->FIU_RunningBoards_Stat & (0x03U)) | ((_m->FIU_Vehicle_DrvMode_Req & (0x07U)) << 5U) ); + cframe->Data[1] |= (uint8_t) ( (_m->FIU_RStrapCntrl_Req & (0x01U)) | ((_m->FIU_RStrapCushCntrl_Req & (0x01U)) << 1U) | ((_m->FIU_LStrapCntrl_Req & (0x01U)) << 2U) | ((_m->FIU_LStrapCushCntrl_Req & (0x01U)) << 3U) | ((_m->FIU_Lift_Req & (0x01U)) << 4U) | ((_m->FIU_HDC_Req & (0x01U)) << 5U) | ((_m->FIU_Prolongation_Req & (0x01U)) << 6U) | ((_m->FIU_ServiceMode_Req & (0x01U)) << 7U) ); + cframe->Data[3] |= (uint8_t) ( (_m->FIU_PressureSet_Req & (0x01U)) ); + + cframe->MsgId = (uint32_t) FIU_Cmd_CANID; + cframe->DLC = (uint8_t) FIU_Cmd_DLC; + cframe->IDE = (uint8_t) FIU_Cmd_IDE; + return FIU_Cmd_CANID; +} + +#else + +uint32_t Pack_FIU_Cmd_candb(FIU_Cmd_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_Cmd_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->FIU_RunningBoards_Stat & (0x03U)) | ((_m->FIU_Vehicle_DrvMode_Req & (0x07U)) << 5U) ); + _d[1] |= (uint8_t) ( (_m->FIU_RStrapCntrl_Req & (0x01U)) | ((_m->FIU_RStrapCushCntrl_Req & (0x01U)) << 1U) | ((_m->FIU_LStrapCntrl_Req & (0x01U)) << 2U) | ((_m->FIU_LStrapCushCntrl_Req & (0x01U)) << 3U) | ((_m->FIU_Lift_Req & (0x01U)) << 4U) | ((_m->FIU_HDC_Req & (0x01U)) << 5U) | ((_m->FIU_Prolongation_Req & (0x01U)) << 6U) | ((_m->FIU_ServiceMode_Req & (0x01U)) << 7U) ); + _d[3] |= (uint8_t) ( (_m->FIU_PressureSet_Req & (0x01U)) ); + + *_len = (uint8_t) FIU_Cmd_DLC; + *_ide = (uint8_t) FIU_Cmd_IDE; + return FIU_Cmd_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_IC_SDM_Info_candb(IC_SDM_Info_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->IC_AverageConsumpUser_ro = (uint16_t) ( ((_d[1] & (0x03U)) << 8U) | (_d[0] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->IC_AverageConsumpUser_phys = (sigfloat_t)(CANDB_IC_AverageConsumpUser_ro_fromS(_m->IC_AverageConsumpUser_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->IC_AverageConsumpTrip_ro = (uint16_t) ( ((_d[1] & (0x03U)) << 8U) | (_d[0] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->IC_AverageConsumpTrip_phys = (sigfloat_t)(CANDB_IC_AverageConsumpTrip_ro_fromS(_m->IC_AverageConsumpTrip_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->IC_UserRange_ro = (uint32_t) ( ((_d[3] & (0x07U)) << 14U) | ((_d[2] & (0xFFU)) << 6U) | ((_d[1] >> 2U) & (0x3FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->IC_UserRange_phys = (sigfloat_t)(CANDB_IC_UserRange_ro_fromS(_m->IC_UserRange_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->IC_TripRange_ro = (uint32_t) ( ((_d[3] & (0x07U)) << 14U) | ((_d[2] & (0xFFU)) << 6U) | ((_d[1] >> 2U) & (0x3FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->IC_TripRange_phys = (sigfloat_t)(CANDB_IC_TripRange_ro_fromS(_m->IC_TripRange_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->IC_UserAverageSpeed_ro = (uint16_t) ( ((_d[5] & (0x01U)) << 13U) | ((_d[4] & (0xFFU)) << 5U) | ((_d[3] >> 3U) & (0x1FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->IC_UserAverageSpeed_phys = (sigfloat_t)(CANDB_IC_UserAverageSpeed_ro_fromS(_m->IC_UserAverageSpeed_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->IC_TripAverageSpeed_ro = (uint16_t) ( ((_d[5] & (0x01U)) << 13U) | ((_d[4] & (0xFFU)) << 5U) | ((_d[3] >> 3U) & (0x1FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->IC_TripAverageSpeed_phys = (sigfloat_t)(CANDB_IC_TripAverageSpeed_ro_fromS(_m->IC_TripAverageSpeed_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->IC_UserMinute = (uint8_t) ( ((_d[5] >> 1U) & (0x3FU)) ); + _m->IC_TripMinute = (uint8_t) ( ((_d[5] >> 1U) & (0x3FU)) ); + _m->IC_UserHour = (uint8_t) ( ((_d[6] & (0x0FU)) << 1U) | ((_d[5] >> 7U) & (0x01U)) ); + _m->IC_TripHour = (uint8_t) ( ((_d[6] & (0x0FU)) << 1U) | ((_d[5] >> 7U) & (0x01U)) ); + _m->IC_UserDay = (uint16_t) ( ((_d[7] & (0x3FU)) << 4U) | ((_d[6] >> 4U) & (0x0FU)) ); + _m->IC_TripDay = (uint16_t) ( ((_d[7] & (0x3FU)) << 4U) | ((_d[6] >> 4U) & (0x0FU)) ); + _m->IC_TCCU_Mult = (uint8_t) ( ((_d[7] >> 7U) & (0x01U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < IC_SDM_Info_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_IC_SDM_Info_candb(&_m->mon1, IC_SDM_Info_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return IC_SDM_Info_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_IC_SDM_Info_candb(IC_SDM_Info_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(IC_SDM_Info_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->IC_AverageConsumpUser_ro = (uint16_t) CANDB_IC_AverageConsumpUser_ro_toS(_m->IC_AverageConsumpUser_phys); + _m->IC_AverageConsumpTrip_ro = (uint16_t) CANDB_IC_AverageConsumpTrip_ro_toS(_m->IC_AverageConsumpTrip_phys); + _m->IC_UserRange_ro = (uint32_t) CANDB_IC_UserRange_ro_toS(_m->IC_UserRange_phys); + _m->IC_TripRange_ro = (uint32_t) CANDB_IC_TripRange_ro_toS(_m->IC_TripRange_phys); + _m->IC_UserAverageSpeed_ro = (uint16_t) CANDB_IC_UserAverageSpeed_ro_toS(_m->IC_UserAverageSpeed_phys); + _m->IC_TripAverageSpeed_ro = (uint16_t) CANDB_IC_TripAverageSpeed_ro_toS(_m->IC_TripAverageSpeed_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->IC_AverageConsumpUser_ro & (0xFFU)) | (_m->IC_AverageConsumpTrip_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->IC_AverageConsumpUser_ro >> 8U) & (0x03U)) | ((_m->IC_AverageConsumpTrip_ro >> 8U) & (0x03U)) | ((_m->IC_UserRange_ro & (0x3FU)) << 2U) | ((_m->IC_TripRange_ro & (0x3FU)) << 2U) ); + cframe->Data[2] |= (uint8_t) ( ((_m->IC_UserRange_ro >> 6U) & (0xFFU)) | ((_m->IC_TripRange_ro >> 6U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->IC_UserRange_ro >> 14U) & (0x07U)) | ((_m->IC_TripRange_ro >> 14U) & (0x07U)) | ((_m->IC_UserAverageSpeed_ro & (0x1FU)) << 3U) | ((_m->IC_TripAverageSpeed_ro & (0x1FU)) << 3U) ); + cframe->Data[4] |= (uint8_t) ( ((_m->IC_UserAverageSpeed_ro >> 5U) & (0xFFU)) | ((_m->IC_TripAverageSpeed_ro >> 5U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->IC_UserAverageSpeed_ro >> 13U) & (0x01U)) | ((_m->IC_TripAverageSpeed_ro >> 13U) & (0x01U)) | ((_m->IC_UserMinute & (0x3FU)) << 1U) | ((_m->IC_TripMinute & (0x3FU)) << 1U) | ((_m->IC_UserHour & (0x01U)) << 7U) | ((_m->IC_TripHour & (0x01U)) << 7U) ); + cframe->Data[6] |= (uint8_t) ( ((_m->IC_UserHour >> 1U) & (0x0FU)) | ((_m->IC_TripHour >> 1U) & (0x0FU)) | ((_m->IC_UserDay & (0x0FU)) << 4U) | ((_m->IC_TripDay & (0x0FU)) << 4U) ); + cframe->Data[7] |= (uint8_t) ( ((_m->IC_UserDay >> 4U) & (0x3FU)) | ((_m->IC_TripDay >> 4U) & (0x3FU)) | ((_m->IC_TCCU_Mult & (0x01U)) << 7U) ); + + cframe->MsgId = (uint32_t) IC_SDM_Info_CANID; + cframe->DLC = (uint8_t) IC_SDM_Info_DLC; + cframe->IDE = (uint8_t) IC_SDM_Info_IDE; + return IC_SDM_Info_CANID; +} + +#else + +uint32_t Pack_IC_SDM_Info_candb(IC_SDM_Info_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(IC_SDM_Info_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->IC_AverageConsumpUser_ro = (uint16_t) CANDB_IC_AverageConsumpUser_ro_toS(_m->IC_AverageConsumpUser_phys); + _m->IC_AverageConsumpTrip_ro = (uint16_t) CANDB_IC_AverageConsumpTrip_ro_toS(_m->IC_AverageConsumpTrip_phys); + _m->IC_UserRange_ro = (uint32_t) CANDB_IC_UserRange_ro_toS(_m->IC_UserRange_phys); + _m->IC_TripRange_ro = (uint32_t) CANDB_IC_TripRange_ro_toS(_m->IC_TripRange_phys); + _m->IC_UserAverageSpeed_ro = (uint16_t) CANDB_IC_UserAverageSpeed_ro_toS(_m->IC_UserAverageSpeed_phys); + _m->IC_TripAverageSpeed_ro = (uint16_t) CANDB_IC_TripAverageSpeed_ro_toS(_m->IC_TripAverageSpeed_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->IC_AverageConsumpUser_ro & (0xFFU)) | (_m->IC_AverageConsumpTrip_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->IC_AverageConsumpUser_ro >> 8U) & (0x03U)) | ((_m->IC_AverageConsumpTrip_ro >> 8U) & (0x03U)) | ((_m->IC_UserRange_ro & (0x3FU)) << 2U) | ((_m->IC_TripRange_ro & (0x3FU)) << 2U) ); + _d[2] |= (uint8_t) ( ((_m->IC_UserRange_ro >> 6U) & (0xFFU)) | ((_m->IC_TripRange_ro >> 6U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->IC_UserRange_ro >> 14U) & (0x07U)) | ((_m->IC_TripRange_ro >> 14U) & (0x07U)) | ((_m->IC_UserAverageSpeed_ro & (0x1FU)) << 3U) | ((_m->IC_TripAverageSpeed_ro & (0x1FU)) << 3U) ); + _d[4] |= (uint8_t) ( ((_m->IC_UserAverageSpeed_ro >> 5U) & (0xFFU)) | ((_m->IC_TripAverageSpeed_ro >> 5U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->IC_UserAverageSpeed_ro >> 13U) & (0x01U)) | ((_m->IC_TripAverageSpeed_ro >> 13U) & (0x01U)) | ((_m->IC_UserMinute & (0x3FU)) << 1U) | ((_m->IC_TripMinute & (0x3FU)) << 1U) | ((_m->IC_UserHour & (0x01U)) << 7U) | ((_m->IC_TripHour & (0x01U)) << 7U) ); + _d[6] |= (uint8_t) ( ((_m->IC_UserHour >> 1U) & (0x0FU)) | ((_m->IC_TripHour >> 1U) & (0x0FU)) | ((_m->IC_UserDay & (0x0FU)) << 4U) | ((_m->IC_TripDay & (0x0FU)) << 4U) ); + _d[7] |= (uint8_t) ( ((_m->IC_UserDay >> 4U) & (0x3FU)) | ((_m->IC_TripDay >> 4U) & (0x3FU)) | ((_m->IC_TCCU_Mult & (0x01U)) << 7U) ); + + *_len = (uint8_t) IC_SDM_Info_DLC; + *_ide = (uint8_t) IC_SDM_Info_IDE; + return IC_SDM_Info_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SDM_Cmd_candb(SDM_Cmd_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->SDM_ExteriorKeyFobSw_Req = (uint8_t) ( (_d[0] & (0x0FU)) ); + _m->SDM_DMRL_Req = (uint8_t) ( ((_d[0] >> 4U) & (0x07U)) ); + _m->SDM_Comm_Req = (uint8_t) ( ((_d[0] >> 7U) & (0x01U)) ); + _m->SDM_DMRR_Req = (uint8_t) ( (_d[1] & (0x07U)) ); + _m->SDM_VisualFeedback_Req = (uint8_t) ( ((_d[1] >> 3U) & (0x01U)) ); + _m->SDM_AudibleFeedback_Req = (uint8_t) ( ((_d[1] >> 4U) & (0x01U)) ); + _m->SDM_DMFL_Req = (uint8_t) ( ((_d[1] >> 5U) & (0x07U)) ); + _m->SDM_DMFR_Req = (uint8_t) ( (_d[2] & (0x07U)) ); + _m->SDM_Aroma_Req = (uint8_t) ( ((_d[2] >> 3U) & (0x03U)) ); + _m->SDM_PrepSalon_Req = (uint8_t) ( ((_d[2] >> 5U) & (0x01U)) ); + _m->SDM_AromaIntens_Req = (uint8_t) ( ((_d[2] >> 6U) & (0x03U)) ); + _m->SDM_StyleIllGlobal_Req = (uint8_t) ( (_d[3] & (0x03U)) ); + _m->SDM_StyleIllTheme_Req = (uint8_t) ( ((_d[3] >> 2U) & (0x1FU)) ); + _m->SDM_StopPrep_Req = (uint8_t) ( ((_d[3] >> 7U) & (0x01U)) ); + _m->SDM_StyleIllBright_Val = (uint8_t) ( (_d[4] & (0x7FU)) ); + _m->SDM_OverAirUpd_Stat = (uint8_t) ( ((_d[4] >> 7U) & (0x01U)) ); + _m->SDM_UV_Req = (uint8_t) ( (_d[5] & (0x01U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < SDM_Cmd_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_SDM_Cmd_candb(&_m->mon1, SDM_Cmd_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return SDM_Cmd_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_SDM_Cmd_candb(SDM_Cmd_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SDM_Cmd_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->SDM_ExteriorKeyFobSw_Req & (0x0FU)) | ((_m->SDM_DMRL_Req & (0x07U)) << 4U) | ((_m->SDM_Comm_Req & (0x01U)) << 7U) ); + cframe->Data[1] |= (uint8_t) ( (_m->SDM_DMRR_Req & (0x07U)) | ((_m->SDM_VisualFeedback_Req & (0x01U)) << 3U) | ((_m->SDM_AudibleFeedback_Req & (0x01U)) << 4U) | ((_m->SDM_DMFL_Req & (0x07U)) << 5U) ); + cframe->Data[2] |= (uint8_t) ( (_m->SDM_DMFR_Req & (0x07U)) | ((_m->SDM_Aroma_Req & (0x03U)) << 3U) | ((_m->SDM_PrepSalon_Req & (0x01U)) << 5U) | ((_m->SDM_AromaIntens_Req & (0x03U)) << 6U) ); + cframe->Data[3] |= (uint8_t) ( (_m->SDM_StyleIllGlobal_Req & (0x03U)) | ((_m->SDM_StyleIllTheme_Req & (0x1FU)) << 2U) | ((_m->SDM_StopPrep_Req & (0x01U)) << 7U) ); + cframe->Data[4] |= (uint8_t) ( (_m->SDM_StyleIllBright_Val & (0x7FU)) | ((_m->SDM_OverAirUpd_Stat & (0x01U)) << 7U) ); + cframe->Data[5] |= (uint8_t) ( (_m->SDM_UV_Req & (0x01U)) ); + + cframe->MsgId = (uint32_t) SDM_Cmd_CANID; + cframe->DLC = (uint8_t) SDM_Cmd_DLC; + cframe->IDE = (uint8_t) SDM_Cmd_IDE; + return SDM_Cmd_CANID; +} + +#else + +uint32_t Pack_SDM_Cmd_candb(SDM_Cmd_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SDM_Cmd_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->SDM_ExteriorKeyFobSw_Req & (0x0FU)) | ((_m->SDM_DMRL_Req & (0x07U)) << 4U) | ((_m->SDM_Comm_Req & (0x01U)) << 7U) ); + _d[1] |= (uint8_t) ( (_m->SDM_DMRR_Req & (0x07U)) | ((_m->SDM_VisualFeedback_Req & (0x01U)) << 3U) | ((_m->SDM_AudibleFeedback_Req & (0x01U)) << 4U) | ((_m->SDM_DMFL_Req & (0x07U)) << 5U) ); + _d[2] |= (uint8_t) ( (_m->SDM_DMFR_Req & (0x07U)) | ((_m->SDM_Aroma_Req & (0x03U)) << 3U) | ((_m->SDM_PrepSalon_Req & (0x01U)) << 5U) | ((_m->SDM_AromaIntens_Req & (0x03U)) << 6U) ); + _d[3] |= (uint8_t) ( (_m->SDM_StyleIllGlobal_Req & (0x03U)) | ((_m->SDM_StyleIllTheme_Req & (0x1FU)) << 2U) | ((_m->SDM_StopPrep_Req & (0x01U)) << 7U) ); + _d[4] |= (uint8_t) ( (_m->SDM_StyleIllBright_Val & (0x7FU)) | ((_m->SDM_OverAirUpd_Stat & (0x01U)) << 7U) ); + _d[5] |= (uint8_t) ( (_m->SDM_UV_Req & (0x01U)) ); + + *_len = (uint8_t) SDM_Cmd_DLC; + *_ide = (uint8_t) SDM_Cmd_IDE; + return SDM_Cmd_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_HUD_MSG_STATUS_candb(HUD_MSG_STATUS_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->HUD_Activation_Stat = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->HUD_ReadyFlag_Stat = (uint8_t) ( ((_d[0] >> 1U) & (0x01U)) ); + _m->HUD_NAVI_Active_Stat = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < HUD_MSG_STATUS_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_HUD_MSG_STATUS_candb(&_m->mon1, HUD_MSG_STATUS_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return HUD_MSG_STATUS_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_HUD_MSG_STATUS_candb(HUD_MSG_STATUS_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(HUD_MSG_STATUS_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->HUD_Activation_Stat & (0x01U)) | ((_m->HUD_ReadyFlag_Stat & (0x01U)) << 1U) | ((_m->HUD_NAVI_Active_Stat & (0x01U)) << 2U) ); + + cframe->MsgId = (uint32_t) HUD_MSG_STATUS_CANID; + cframe->DLC = (uint8_t) HUD_MSG_STATUS_DLC; + cframe->IDE = (uint8_t) HUD_MSG_STATUS_IDE; + return HUD_MSG_STATUS_CANID; +} + +#else + +uint32_t Pack_HUD_MSG_STATUS_candb(HUD_MSG_STATUS_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(HUD_MSG_STATUS_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->HUD_Activation_Stat & (0x01U)) | ((_m->HUD_ReadyFlag_Stat & (0x01U)) << 1U) | ((_m->HUD_NAVI_Active_Stat & (0x01U)) << 2U) ); + + *_len = (uint8_t) HUD_MSG_STATUS_DLC; + *_ide = (uint8_t) HUD_MSG_STATUS_IDE; + return HUD_MSG_STATUS_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_IC_SDM_Info_02_candb(IC_SDM_Info_02_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->IC_AverageConsump_ro = (uint16_t) ( ((_d[1] & (0x03U)) << 8U) | (_d[0] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->IC_AverageConsump_phys = (sigfloat_t)(CANDB_IC_AverageConsump_ro_fromS(_m->IC_AverageConsump_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->IC_CurrentConsumptionUnit = (uint8_t) ( ((_d[1] >> 2U) & (0x01U)) ); + _m->IC_CurrentConsump_ro = (uint16_t) ( ((_d[3] & (0x03U)) << 8U) | (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->IC_CurrentConsump_phys = (sigfloat_t)(CANDB_IC_CurrentConsump_ro_fromS(_m->IC_CurrentConsump_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->IC_CruisingRange = (uint16_t) ( ((_d[5] & (0x03U)) << 8U) | (_d[4] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < IC_SDM_Info_02_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_IC_SDM_Info_02_candb(&_m->mon1, IC_SDM_Info_02_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return IC_SDM_Info_02_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_IC_SDM_Info_02_candb(IC_SDM_Info_02_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(IC_SDM_Info_02_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->IC_AverageConsump_ro = (uint16_t) CANDB_IC_AverageConsump_ro_toS(_m->IC_AverageConsump_phys); + _m->IC_CurrentConsump_ro = (uint16_t) CANDB_IC_CurrentConsump_ro_toS(_m->IC_CurrentConsump_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->IC_AverageConsump_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->IC_AverageConsump_ro >> 8U) & (0x03U)) | ((_m->IC_CurrentConsumptionUnit & (0x01U)) << 2U) ); + cframe->Data[2] |= (uint8_t) ( (_m->IC_CurrentConsump_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->IC_CurrentConsump_ro >> 8U) & (0x03U)) ); + cframe->Data[4] |= (uint8_t) ( (_m->IC_CruisingRange & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->IC_CruisingRange >> 8U) & (0x03U)) ); + + cframe->MsgId = (uint32_t) IC_SDM_Info_02_CANID; + cframe->DLC = (uint8_t) IC_SDM_Info_02_DLC; + cframe->IDE = (uint8_t) IC_SDM_Info_02_IDE; + return IC_SDM_Info_02_CANID; +} + +#else + +uint32_t Pack_IC_SDM_Info_02_candb(IC_SDM_Info_02_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(IC_SDM_Info_02_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->IC_AverageConsump_ro = (uint16_t) CANDB_IC_AverageConsump_ro_toS(_m->IC_AverageConsump_phys); + _m->IC_CurrentConsump_ro = (uint16_t) CANDB_IC_CurrentConsump_ro_toS(_m->IC_CurrentConsump_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->IC_AverageConsump_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->IC_AverageConsump_ro >> 8U) & (0x03U)) | ((_m->IC_CurrentConsumptionUnit & (0x01U)) << 2U) ); + _d[2] |= (uint8_t) ( (_m->IC_CurrentConsump_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->IC_CurrentConsump_ro >> 8U) & (0x03U)) ); + _d[4] |= (uint8_t) ( (_m->IC_CruisingRange & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->IC_CruisingRange >> 8U) & (0x03U)) ); + + *_len = (uint8_t) IC_SDM_Info_02_DLC; + *_ide = (uint8_t) IC_SDM_Info_02_IDE; + return IC_SDM_Info_02_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_IC_Milleage_candb(IC_Milleage_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->IC_Mileage_Val_ro = (uint32_t) ( ((_d[3] & (0x07U)) << 24U) | ((_d[2] & (0xFFU)) << 16U) | ((_d[1] & (0xFFU)) << 8U) | (_d[0] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->IC_Mileage_Val_phys = (sigfloat_t)(CANDB_IC_Mileage_Val_ro_fromS(_m->IC_Mileage_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->IC_Mileage_RC = (uint8_t) ( ((_d[3] >> 4U) & (0x0FU)) ); + _m->IC_Mileage_CS = (uint8_t) ( (_d[4] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < IC_Milleage_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_IC_Milleage_candb(&_m->mon1, IC_Milleage_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return IC_Milleage_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_IC_Milleage_candb(IC_Milleage_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(IC_Milleage_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->IC_Mileage_Val_ro = (uint32_t) CANDB_IC_Mileage_Val_ro_toS(_m->IC_Mileage_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->IC_Mileage_Val_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->IC_Mileage_Val_ro >> 8U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->IC_Mileage_Val_ro >> 16U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->IC_Mileage_Val_ro >> 24U) & (0x07U)) | ((_m->IC_Mileage_RC & (0x0FU)) << 4U) ); + cframe->Data[4] |= (uint8_t) ( (_m->IC_Mileage_CS & (0xFFU)) ); + + cframe->MsgId = (uint32_t) IC_Milleage_CANID; + cframe->DLC = (uint8_t) IC_Milleage_DLC; + cframe->IDE = (uint8_t) IC_Milleage_IDE; + return IC_Milleage_CANID; +} + +#else + +uint32_t Pack_IC_Milleage_candb(IC_Milleage_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(IC_Milleage_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->IC_Mileage_Val_ro = (uint32_t) CANDB_IC_Mileage_Val_ro_toS(_m->IC_Mileage_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->IC_Mileage_Val_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->IC_Mileage_Val_ro >> 8U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->IC_Mileage_Val_ro >> 16U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->IC_Mileage_Val_ro >> 24U) & (0x07U)) | ((_m->IC_Mileage_RC & (0x0FU)) << 4U) ); + _d[4] |= (uint8_t) ( (_m->IC_Mileage_CS & (0xFFU)) ); + + *_len = (uint8_t) IC_Milleage_DLC; + *_ide = (uint8_t) IC_Milleage_IDE; + return IC_Milleage_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_VEH_VIN_candb(VEH_VIN_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->VIN_Addressing = (uint8_t) ( (_d[0] & (0x03U)) ); + _m->VIN_Char1 = (uint8_t) ( (_d[1] & (0xFFU)) ); + _m->VIN_Char8 = (uint8_t) ( (_d[1] & (0xFFU)) ); + _m->VIN_Char15 = (uint8_t) ( (_d[1] & (0xFFU)) ); + _m->VIN_Char16 = (uint8_t) ( (_d[2] & (0xFFU)) ); + _m->VIN_Char2 = (uint8_t) ( (_d[2] & (0xFFU)) ); + _m->VIN_Char9 = (uint8_t) ( (_d[2] & (0xFFU)) ); + _m->VIN_Char10 = (uint8_t) ( (_d[3] & (0xFFU)) ); + _m->VIN_Char17 = (uint8_t) ( (_d[3] & (0xFFU)) ); + _m->VIN_Char3 = (uint8_t) ( (_d[3] & (0xFFU)) ); + _m->VIN_Char4 = (uint8_t) ( (_d[4] & (0xFFU)) ); + _m->VIN_Char11 = (uint8_t) ( (_d[4] & (0xFFU)) ); + _m->VIN_Char12 = (uint8_t) ( (_d[5] & (0xFFU)) ); + _m->VIN_Char5 = (uint8_t) ( (_d[5] & (0xFFU)) ); + _m->VIN_Char6 = (uint8_t) ( (_d[6] & (0xFFU)) ); + _m->VIN_Char13 = (uint8_t) ( (_d[6] & (0xFFU)) ); + _m->VIN_Char7 = (uint8_t) ( (_d[7] & (0xFFU)) ); + _m->VIN_Char14 = (uint8_t) ( (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < VEH_VIN_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_VEH_VIN_candb(&_m->mon1, VEH_VIN_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return VEH_VIN_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_VEH_VIN_candb(VEH_VIN_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(VEH_VIN_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->VIN_Addressing & (0x03U)) ); + cframe->Data[1] |= (uint8_t) ( (_m->VIN_Char1 & (0xFFU)) | (_m->VIN_Char8 & (0xFFU)) | (_m->VIN_Char15 & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->VIN_Char16 & (0xFFU)) | (_m->VIN_Char2 & (0xFFU)) | (_m->VIN_Char9 & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->VIN_Char10 & (0xFFU)) | (_m->VIN_Char17 & (0xFFU)) | (_m->VIN_Char3 & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->VIN_Char4 & (0xFFU)) | (_m->VIN_Char11 & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->VIN_Char12 & (0xFFU)) | (_m->VIN_Char5 & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->VIN_Char6 & (0xFFU)) | (_m->VIN_Char13 & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->VIN_Char7 & (0xFFU)) | (_m->VIN_Char14 & (0xFFU)) ); + + cframe->MsgId = (uint32_t) VEH_VIN_CANID; + cframe->DLC = (uint8_t) VEH_VIN_DLC; + cframe->IDE = (uint8_t) VEH_VIN_IDE; + return VEH_VIN_CANID; +} + +#else + +uint32_t Pack_VEH_VIN_candb(VEH_VIN_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(VEH_VIN_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->VIN_Addressing & (0x03U)) ); + _d[1] |= (uint8_t) ( (_m->VIN_Char1 & (0xFFU)) | (_m->VIN_Char8 & (0xFFU)) | (_m->VIN_Char15 & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->VIN_Char16 & (0xFFU)) | (_m->VIN_Char2 & (0xFFU)) | (_m->VIN_Char9 & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->VIN_Char10 & (0xFFU)) | (_m->VIN_Char17 & (0xFFU)) | (_m->VIN_Char3 & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->VIN_Char4 & (0xFFU)) | (_m->VIN_Char11 & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->VIN_Char12 & (0xFFU)) | (_m->VIN_Char5 & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->VIN_Char6 & (0xFFU)) | (_m->VIN_Char13 & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->VIN_Char7 & (0xFFU)) | (_m->VIN_Char14 & (0xFFU)) ); + + *_len = (uint8_t) VEH_VIN_DLC; + *_ide = (uint8_t) VEH_VIN_IDE; + return VEH_VIN_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_RunningBoards_candb(BCM_RunningBoards_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->BCM_LeftMotion_Cmd = (uint8_t) ( (_d[0] & (0x03U)) ); + _m->BCM_RightMotion_Cmd = (uint8_t) ( ((_d[0] >> 2U) & (0x03U)) ); + _m->BCM_Buzzer_Cmd = (uint8_t) ( ((_d[0] >> 4U) & (0x01U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < BCM_RunningBoards_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_BCM_RunningBoards_candb(&_m->mon1, BCM_RunningBoards_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return BCM_RunningBoards_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_BCM_RunningBoards_candb(BCM_RunningBoards_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_RunningBoards_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->BCM_LeftMotion_Cmd & (0x03U)) | ((_m->BCM_RightMotion_Cmd & (0x03U)) << 2U) | ((_m->BCM_Buzzer_Cmd & (0x01U)) << 4U) ); + + cframe->MsgId = (uint32_t) BCM_RunningBoards_CANID; + cframe->DLC = (uint8_t) BCM_RunningBoards_DLC; + cframe->IDE = (uint8_t) BCM_RunningBoards_IDE; + return BCM_RunningBoards_CANID; +} + +#else + +uint32_t Pack_BCM_RunningBoards_candb(BCM_RunningBoards_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_RunningBoards_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->BCM_LeftMotion_Cmd & (0x03U)) | ((_m->BCM_RightMotion_Cmd & (0x03U)) << 2U) | ((_m->BCM_Buzzer_Cmd & (0x01U)) << 4U) ); + + *_len = (uint8_t) BCM_RunningBoards_DLC; + *_ide = (uint8_t) BCM_RunningBoards_IDE; + return BCM_RunningBoards_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_OCUFL_MSG_candb(OCUFL_MSG_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->OCUFL_OccupantWeight_Stat = (uint8_t) ( (_d[0] & (0x03U)) ); + _m->OCUFL_SeatOccupied_Stat = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + _m->OCUFL_SensorError_Stat = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + _m->OCUFL_MSG_RC = (uint8_t) ( ((_d[0] >> 4U) & (0x0FU)) ); + _m->OCUFL_MSG_CS = (uint8_t) ( (_d[1] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < OCUFL_MSG_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_OCUFL_MSG_candb(&_m->mon1, OCUFL_MSG_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return OCUFL_MSG_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_OCUFL_MSG_candb(OCUFL_MSG_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(OCUFL_MSG_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->OCUFL_OccupantWeight_Stat & (0x03U)) | ((_m->OCUFL_SeatOccupied_Stat & (0x01U)) << 2U) | ((_m->OCUFL_SensorError_Stat & (0x01U)) << 3U) | ((_m->OCUFL_MSG_RC & (0x0FU)) << 4U) ); + cframe->Data[1] |= (uint8_t) ( (_m->OCUFL_MSG_CS & (0xFFU)) ); + + cframe->MsgId = (uint32_t) OCUFL_MSG_CANID; + cframe->DLC = (uint8_t) OCUFL_MSG_DLC; + cframe->IDE = (uint8_t) OCUFL_MSG_IDE; + return OCUFL_MSG_CANID; +} + +#else + +uint32_t Pack_OCUFL_MSG_candb(OCUFL_MSG_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(OCUFL_MSG_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->OCUFL_OccupantWeight_Stat & (0x03U)) | ((_m->OCUFL_SeatOccupied_Stat & (0x01U)) << 2U) | ((_m->OCUFL_SensorError_Stat & (0x01U)) << 3U) | ((_m->OCUFL_MSG_RC & (0x0FU)) << 4U) ); + _d[1] |= (uint8_t) ( (_m->OCUFL_MSG_CS & (0xFFU)) ); + + *_len = (uint8_t) OCUFL_MSG_DLC; + *_ide = (uint8_t) OCUFL_MSG_IDE; + return OCUFL_MSG_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_OCUFR_MSG_candb(OCUFR_MSG_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->OCUFR_OccupantWeight_Stat = (uint8_t) ( (_d[0] & (0x03U)) ); + _m->OCUFR_SeatOccupied_Stat = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + _m->OCUFR_SensorError_Stat = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + _m->OCUFR_MSG_RC = (uint8_t) ( ((_d[0] >> 4U) & (0x0FU)) ); + _m->OCUFR_MSG_CS = (uint8_t) ( (_d[1] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < OCUFR_MSG_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_OCUFR_MSG_candb(&_m->mon1, OCUFR_MSG_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return OCUFR_MSG_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_OCUFR_MSG_candb(OCUFR_MSG_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(OCUFR_MSG_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->OCUFR_OccupantWeight_Stat & (0x03U)) | ((_m->OCUFR_SeatOccupied_Stat & (0x01U)) << 2U) | ((_m->OCUFR_SensorError_Stat & (0x01U)) << 3U) | ((_m->OCUFR_MSG_RC & (0x0FU)) << 4U) ); + cframe->Data[1] |= (uint8_t) ( (_m->OCUFR_MSG_CS & (0xFFU)) ); + + cframe->MsgId = (uint32_t) OCUFR_MSG_CANID; + cframe->DLC = (uint8_t) OCUFR_MSG_DLC; + cframe->IDE = (uint8_t) OCUFR_MSG_IDE; + return OCUFR_MSG_CANID; +} + +#else + +uint32_t Pack_OCUFR_MSG_candb(OCUFR_MSG_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(OCUFR_MSG_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->OCUFR_OccupantWeight_Stat & (0x03U)) | ((_m->OCUFR_SeatOccupied_Stat & (0x01U)) << 2U) | ((_m->OCUFR_SensorError_Stat & (0x01U)) << 3U) | ((_m->OCUFR_MSG_RC & (0x0FU)) << 4U) ); + _d[1] |= (uint8_t) ( (_m->OCUFR_MSG_CS & (0xFFU)) ); + + *_len = (uint8_t) OCUFR_MSG_DLC; + *_ide = (uint8_t) OCUFR_MSG_IDE; + return OCUFR_MSG_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_OCURL_MSG_candb(OCURL_MSG_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->OCURL_OccupantWeight_Stat = (uint8_t) ( (_d[0] & (0x03U)) ); + _m->OCURL_SeatOccupied_Stat = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + _m->OCURL_SensorError_Stat = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + _m->OCURL_MSG_RC = (uint8_t) ( ((_d[0] >> 4U) & (0x0FU)) ); + _m->OCURL_MSG_CS = (uint8_t) ( (_d[1] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < OCURL_MSG_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_OCURL_MSG_candb(&_m->mon1, OCURL_MSG_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return OCURL_MSG_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_OCURL_MSG_candb(OCURL_MSG_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(OCURL_MSG_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->OCURL_OccupantWeight_Stat & (0x03U)) | ((_m->OCURL_SeatOccupied_Stat & (0x01U)) << 2U) | ((_m->OCURL_SensorError_Stat & (0x01U)) << 3U) | ((_m->OCURL_MSG_RC & (0x0FU)) << 4U) ); + cframe->Data[1] |= (uint8_t) ( (_m->OCURL_MSG_CS & (0xFFU)) ); + + cframe->MsgId = (uint32_t) OCURL_MSG_CANID; + cframe->DLC = (uint8_t) OCURL_MSG_DLC; + cframe->IDE = (uint8_t) OCURL_MSG_IDE; + return OCURL_MSG_CANID; +} + +#else + +uint32_t Pack_OCURL_MSG_candb(OCURL_MSG_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(OCURL_MSG_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->OCURL_OccupantWeight_Stat & (0x03U)) | ((_m->OCURL_SeatOccupied_Stat & (0x01U)) << 2U) | ((_m->OCURL_SensorError_Stat & (0x01U)) << 3U) | ((_m->OCURL_MSG_RC & (0x0FU)) << 4U) ); + _d[1] |= (uint8_t) ( (_m->OCURL_MSG_CS & (0xFFU)) ); + + *_len = (uint8_t) OCURL_MSG_DLC; + *_ide = (uint8_t) OCURL_MSG_IDE; + return OCURL_MSG_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_OCURR_MSG_candb(OCURR_MSG_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->OCURR_OccupantWeight_Stat = (uint8_t) ( (_d[0] & (0x03U)) ); + _m->OCURR_SeatOccupied_Stat = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + _m->OCURR_SensorError_Stat = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + _m->OCURR_MSG_RC = (uint8_t) ( ((_d[0] >> 4U) & (0x0FU)) ); + _m->OCURR_MSG_CS = (uint8_t) ( (_d[1] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < OCURR_MSG_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_OCURR_MSG_candb(&_m->mon1, OCURR_MSG_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return OCURR_MSG_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_OCURR_MSG_candb(OCURR_MSG_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(OCURR_MSG_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->OCURR_OccupantWeight_Stat & (0x03U)) | ((_m->OCURR_SeatOccupied_Stat & (0x01U)) << 2U) | ((_m->OCURR_SensorError_Stat & (0x01U)) << 3U) | ((_m->OCURR_MSG_RC & (0x0FU)) << 4U) ); + cframe->Data[1] |= (uint8_t) ( (_m->OCURR_MSG_CS & (0xFFU)) ); + + cframe->MsgId = (uint32_t) OCURR_MSG_CANID; + cframe->DLC = (uint8_t) OCURR_MSG_DLC; + cframe->IDE = (uint8_t) OCURR_MSG_IDE; + return OCURR_MSG_CANID; +} + +#else + +uint32_t Pack_OCURR_MSG_candb(OCURR_MSG_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(OCURR_MSG_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->OCURR_OccupantWeight_Stat & (0x03U)) | ((_m->OCURR_SeatOccupied_Stat & (0x01U)) << 2U) | ((_m->OCURR_SensorError_Stat & (0x01U)) << 3U) | ((_m->OCURR_MSG_RC & (0x0FU)) << 4U) ); + _d[1] |= (uint8_t) ( (_m->OCURR_MSG_CS & (0xFFU)) ); + + *_len = (uint8_t) OCURR_MSG_DLC; + *_ide = (uint8_t) OCURR_MSG_IDE; + return OCURR_MSG_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_RBCU_BODY_Stat_candb(RBCU_BODY_Stat_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->RBCU_LeftErr_Stat = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->RBCU_LeftAntipinch_Stat = (uint8_t) ( ((_d[0] >> 1U) & (0x01U)) ); + _m->RBCU_LeftMotion_Stat = (uint8_t) ( ((_d[0] >> 2U) & (0x03U)) ); + _m->RBCU_LeftPosition_Stat = (uint8_t) ( ((_d[0] >> 4U) & (0x03U)) ); + _m->RBCU_LeftCalibration_Stat = (uint8_t) ( ((_d[0] >> 6U) & (0x01U)) ); + _m->RBCU_RightErr_Stat = (uint8_t) ( ((_d[0] >> 7U) & (0x01U)) ); + _m->RBCU_RightAntipinch_Stat = (uint8_t) ( (_d[1] & (0x01U)) ); + _m->RBCU_RightMotion_Stat = (uint8_t) ( ((_d[1] >> 1U) & (0x03U)) ); + _m->RBCU_RightPosition_Stat = (uint8_t) ( ((_d[1] >> 3U) & (0x03U)) ); + _m->RBCU_RightCalibration_Stat = (uint8_t) ( ((_d[1] >> 5U) & (0x01U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < RBCU_BODY_Stat_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_RBCU_BODY_Stat_candb(&_m->mon1, RBCU_BODY_Stat_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return RBCU_BODY_Stat_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_RBCU_BODY_Stat_candb(RBCU_BODY_Stat_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(RBCU_BODY_Stat_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->RBCU_LeftErr_Stat & (0x01U)) | ((_m->RBCU_LeftAntipinch_Stat & (0x01U)) << 1U) | ((_m->RBCU_LeftMotion_Stat & (0x03U)) << 2U) | ((_m->RBCU_LeftPosition_Stat & (0x03U)) << 4U) | ((_m->RBCU_LeftCalibration_Stat & (0x01U)) << 6U) | ((_m->RBCU_RightErr_Stat & (0x01U)) << 7U) ); + cframe->Data[1] |= (uint8_t) ( (_m->RBCU_RightAntipinch_Stat & (0x01U)) | ((_m->RBCU_RightMotion_Stat & (0x03U)) << 1U) | ((_m->RBCU_RightPosition_Stat & (0x03U)) << 3U) | ((_m->RBCU_RightCalibration_Stat & (0x01U)) << 5U) ); + + cframe->MsgId = (uint32_t) RBCU_BODY_Stat_CANID; + cframe->DLC = (uint8_t) RBCU_BODY_Stat_DLC; + cframe->IDE = (uint8_t) RBCU_BODY_Stat_IDE; + return RBCU_BODY_Stat_CANID; +} + +#else + +uint32_t Pack_RBCU_BODY_Stat_candb(RBCU_BODY_Stat_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(RBCU_BODY_Stat_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->RBCU_LeftErr_Stat & (0x01U)) | ((_m->RBCU_LeftAntipinch_Stat & (0x01U)) << 1U) | ((_m->RBCU_LeftMotion_Stat & (0x03U)) << 2U) | ((_m->RBCU_LeftPosition_Stat & (0x03U)) << 4U) | ((_m->RBCU_LeftCalibration_Stat & (0x01U)) << 6U) | ((_m->RBCU_RightErr_Stat & (0x01U)) << 7U) ); + _d[1] |= (uint8_t) ( (_m->RBCU_RightAntipinch_Stat & (0x01U)) | ((_m->RBCU_RightMotion_Stat & (0x03U)) << 1U) | ((_m->RBCU_RightPosition_Stat & (0x03U)) << 3U) | ((_m->RBCU_RightCalibration_Stat & (0x01U)) << 5U) ); + + *_len = (uint8_t) RBCU_BODY_Stat_DLC; + *_ide = (uint8_t) RBCU_BODY_Stat_IDE; + return RBCU_BODY_Stat_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_SMRL_REQ_CTR_SEATS_candb(FIU_SMRL_REQ_CTR_SEATS_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->FIU_SMRL_SeatHeight_Req = (uint8_t) ( (_d[0] & (0x03U)) ); + _m->FIU_SMRL_HeadRestHeight_Req = (uint8_t) ( ((_d[0] >> 2U) & (0x03U)) ); + _m->FIU_SMRL_SeatLongitudinal_Req = (uint8_t) ( ((_d[0] >> 4U) & (0x03U)) ); + _m->FIU_SMRL_SeatHeadRestInclin_Req = (uint8_t) ( ((_d[0] >> 6U) & (0x03U)) ); + _m->FIU_SMRL_SeatSurfaceLong_Req = (uint8_t) ( (_d[1] & (0x03U)) ); + _m->FIU_SMRL_SeatLegSupportH_Req = (uint8_t) ( ((_d[1] >> 2U) & (0x03U)) ); + _m->FIU_SMRL_SeatLegSupportLong_Req = (uint8_t) ( ((_d[1] >> 4U) & (0x03U)) ); + _m->FIU_SMRL_SeatInclination_Req = (uint8_t) ( ((_d[1] >> 6U) & (0x03U)) ); + _m->FIU_SMRL_SeatBackRestInc_Req = (uint8_t) ( (_d[2] & (0x03U)) ); + _m->FIU_SMRL_SeatLumbarSupportH_Req = (uint8_t) ( ((_d[2] >> 2U) & (0x03U)) ); + _m->FIU_SMRL_SeatBackRestHeadInc_Req = (uint8_t) ( ((_d[2] >> 4U) & (0x03U)) ); + _m->FIU_SMRL_SeatLumbarSupDepth_Req = (uint8_t) ( ((_d[2] >> 6U) & (0x03U)) ); + _m->FIU_SMRL_BackRestWidth_Req = (uint8_t) ( (_d[3] & (0x03U)) ); + _m->FIU_SMRL_SeatCushionSupport_Req = (uint8_t) ( ((_d[3] >> 2U) & (0x03U)) ); + _m->FIU_SMRL_SeatMassage_Req = (uint8_t) ( ((_d[3] >> 4U) & (0x03U)) ); + _m->FIU_SMRL_SeatVentilation_Req = (uint8_t) ( ((_d[3] >> 6U) & (0x03U)) ); + _m->FIU_SMRL_SeatVentBalance_Req = (uint8_t) ( (_d[4] & (0x07U)) ); + _m->FIU_SMRL_SeatMassageIntence_Req = (uint8_t) ( ((_d[4] >> 3U) & (0x03U)) ); + _m->FIU_SMRL_SeatHeating_Req = (uint8_t) ( ((_d[4] >> 5U) & (0x03U)) ); + _m->FIU_SMRL_ActiveSupport_Req = (uint8_t) ( ((_d[4] >> 7U) & (0x01U)) ); + _m->FIU_SMRL_SeatHeatBalance_Req = (uint8_t) ( (_d[5] & (0x07U)) ); + _m->FIU_SMRL_SeatMassageType_Req = (uint8_t) ( ((_d[5] >> 3U) & (0x07U)) ); + _m->FIU_SMRL_BackrestMassageType_Req = (uint8_t) ( ((_d[6] & (0x01U)) << 2U) | ((_d[5] >> 6U) & (0x03U)) ); + _m->FIU_SMRL_ComfortMode_Req = (uint8_t) ( ((_d[6] >> 1U) & (0x01U)) ); + _m->FIU_SMRL_ComfortScenario_Req = (uint8_t) ( ((_d[6] >> 2U) & (0x03U)) ); + _m->FIU_SMRL_CarpetHeat_Req = (uint8_t) ( ((_d[6] >> 4U) & (0x01U)) ); + _m->FIU_SMRL_TimerMassage_Req = (uint8_t) ( ((_d[6] >> 5U) & (0x07U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < FIU_SMRL_REQ_CTR_SEATS_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_FIU_SMRL_REQ_CTR_SEATS_candb(&_m->mon1, FIU_SMRL_REQ_CTR_SEATS_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return FIU_SMRL_REQ_CTR_SEATS_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_FIU_SMRL_REQ_CTR_SEATS_candb(FIU_SMRL_REQ_CTR_SEATS_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_SMRL_REQ_CTR_SEATS_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->FIU_SMRL_SeatHeight_Req & (0x03U)) | ((_m->FIU_SMRL_HeadRestHeight_Req & (0x03U)) << 2U) | ((_m->FIU_SMRL_SeatLongitudinal_Req & (0x03U)) << 4U) | ((_m->FIU_SMRL_SeatHeadRestInclin_Req & (0x03U)) << 6U) ); + cframe->Data[1] |= (uint8_t) ( (_m->FIU_SMRL_SeatSurfaceLong_Req & (0x03U)) | ((_m->FIU_SMRL_SeatLegSupportH_Req & (0x03U)) << 2U) | ((_m->FIU_SMRL_SeatLegSupportLong_Req & (0x03U)) << 4U) | ((_m->FIU_SMRL_SeatInclination_Req & (0x03U)) << 6U) ); + cframe->Data[2] |= (uint8_t) ( (_m->FIU_SMRL_SeatBackRestInc_Req & (0x03U)) | ((_m->FIU_SMRL_SeatLumbarSupportH_Req & (0x03U)) << 2U) | ((_m->FIU_SMRL_SeatBackRestHeadInc_Req & (0x03U)) << 4U) | ((_m->FIU_SMRL_SeatLumbarSupDepth_Req & (0x03U)) << 6U) ); + cframe->Data[3] |= (uint8_t) ( (_m->FIU_SMRL_BackRestWidth_Req & (0x03U)) | ((_m->FIU_SMRL_SeatCushionSupport_Req & (0x03U)) << 2U) | ((_m->FIU_SMRL_SeatMassage_Req & (0x03U)) << 4U) | ((_m->FIU_SMRL_SeatVentilation_Req & (0x03U)) << 6U) ); + cframe->Data[4] |= (uint8_t) ( (_m->FIU_SMRL_SeatVentBalance_Req & (0x07U)) | ((_m->FIU_SMRL_SeatMassageIntence_Req & (0x03U)) << 3U) | ((_m->FIU_SMRL_SeatHeating_Req & (0x03U)) << 5U) | ((_m->FIU_SMRL_ActiveSupport_Req & (0x01U)) << 7U) ); + cframe->Data[5] |= (uint8_t) ( (_m->FIU_SMRL_SeatHeatBalance_Req & (0x07U)) | ((_m->FIU_SMRL_SeatMassageType_Req & (0x07U)) << 3U) | ((_m->FIU_SMRL_BackrestMassageType_Req & (0x03U)) << 6U) ); + cframe->Data[6] |= (uint8_t) ( ((_m->FIU_SMRL_BackrestMassageType_Req >> 2U) & (0x01U)) | ((_m->FIU_SMRL_ComfortMode_Req & (0x01U)) << 1U) | ((_m->FIU_SMRL_ComfortScenario_Req & (0x03U)) << 2U) | ((_m->FIU_SMRL_CarpetHeat_Req & (0x01U)) << 4U) | ((_m->FIU_SMRL_TimerMassage_Req & (0x07U)) << 5U) ); + + cframe->MsgId = (uint32_t) FIU_SMRL_REQ_CTR_SEATS_CANID; + cframe->DLC = (uint8_t) FIU_SMRL_REQ_CTR_SEATS_DLC; + cframe->IDE = (uint8_t) FIU_SMRL_REQ_CTR_SEATS_IDE; + return FIU_SMRL_REQ_CTR_SEATS_CANID; +} + +#else + +uint32_t Pack_FIU_SMRL_REQ_CTR_SEATS_candb(FIU_SMRL_REQ_CTR_SEATS_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_SMRL_REQ_CTR_SEATS_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->FIU_SMRL_SeatHeight_Req & (0x03U)) | ((_m->FIU_SMRL_HeadRestHeight_Req & (0x03U)) << 2U) | ((_m->FIU_SMRL_SeatLongitudinal_Req & (0x03U)) << 4U) | ((_m->FIU_SMRL_SeatHeadRestInclin_Req & (0x03U)) << 6U) ); + _d[1] |= (uint8_t) ( (_m->FIU_SMRL_SeatSurfaceLong_Req & (0x03U)) | ((_m->FIU_SMRL_SeatLegSupportH_Req & (0x03U)) << 2U) | ((_m->FIU_SMRL_SeatLegSupportLong_Req & (0x03U)) << 4U) | ((_m->FIU_SMRL_SeatInclination_Req & (0x03U)) << 6U) ); + _d[2] |= (uint8_t) ( (_m->FIU_SMRL_SeatBackRestInc_Req & (0x03U)) | ((_m->FIU_SMRL_SeatLumbarSupportH_Req & (0x03U)) << 2U) | ((_m->FIU_SMRL_SeatBackRestHeadInc_Req & (0x03U)) << 4U) | ((_m->FIU_SMRL_SeatLumbarSupDepth_Req & (0x03U)) << 6U) ); + _d[3] |= (uint8_t) ( (_m->FIU_SMRL_BackRestWidth_Req & (0x03U)) | ((_m->FIU_SMRL_SeatCushionSupport_Req & (0x03U)) << 2U) | ((_m->FIU_SMRL_SeatMassage_Req & (0x03U)) << 4U) | ((_m->FIU_SMRL_SeatVentilation_Req & (0x03U)) << 6U) ); + _d[4] |= (uint8_t) ( (_m->FIU_SMRL_SeatVentBalance_Req & (0x07U)) | ((_m->FIU_SMRL_SeatMassageIntence_Req & (0x03U)) << 3U) | ((_m->FIU_SMRL_SeatHeating_Req & (0x03U)) << 5U) | ((_m->FIU_SMRL_ActiveSupport_Req & (0x01U)) << 7U) ); + _d[5] |= (uint8_t) ( (_m->FIU_SMRL_SeatHeatBalance_Req & (0x07U)) | ((_m->FIU_SMRL_SeatMassageType_Req & (0x07U)) << 3U) | ((_m->FIU_SMRL_BackrestMassageType_Req & (0x03U)) << 6U) ); + _d[6] |= (uint8_t) ( ((_m->FIU_SMRL_BackrestMassageType_Req >> 2U) & (0x01U)) | ((_m->FIU_SMRL_ComfortMode_Req & (0x01U)) << 1U) | ((_m->FIU_SMRL_ComfortScenario_Req & (0x03U)) << 2U) | ((_m->FIU_SMRL_CarpetHeat_Req & (0x01U)) << 4U) | ((_m->FIU_SMRL_TimerMassage_Req & (0x07U)) << 5U) ); + + *_len = (uint8_t) FIU_SMRL_REQ_CTR_SEATS_DLC; + *_ide = (uint8_t) FIU_SMRL_REQ_CTR_SEATS_IDE; + return FIU_SMRL_REQ_CTR_SEATS_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_SMFR_REQ_CTR_SEATS_candb(FIU_SMFR_REQ_CTR_SEATS_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->FIU_SMFR_SeatHeight_Req = (uint8_t) ( (_d[0] & (0x03U)) ); + _m->FIU_SMFR_HeadRest_Height_Req = (uint8_t) ( ((_d[0] >> 2U) & (0x03U)) ); + _m->FIU_SMFR_SeatLongitunalReq = (uint8_t) ( ((_d[0] >> 4U) & (0x03U)) ); + _m->FIU_SMFR_SeatHeadRestInclin_Req = (uint8_t) ( ((_d[0] >> 6U) & (0x03U)) ); + _m->FIU_SMFR_SeatSurfaceLong_Req = (uint8_t) ( (_d[1] & (0x03U)) ); + _m->FIU_SMFR_SeatLegSupportH_Req = (uint8_t) ( ((_d[1] >> 2U) & (0x03U)) ); + _m->FIU_SMFR_SeatLegSupportLong_Req = (uint8_t) ( ((_d[1] >> 4U) & (0x03U)) ); + _m->FIU_SMFR_SeatInclination_Req = (uint8_t) ( ((_d[1] >> 6U) & (0x03U)) ); + _m->FIU_SMFR_SeatBackRestInc_Req = (uint8_t) ( (_d[2] & (0x03U)) ); + _m->FIU_SMFR_SeatLumbarSupHeight_Req = (uint8_t) ( ((_d[2] >> 2U) & (0x03U)) ); + _m->FIU_SMFR_SeatBackRestHeadInc_Req = (uint8_t) ( ((_d[2] >> 4U) & (0x03U)) ); + _m->FIU_SMFR_SeatLumbarSupDepth_Req = (uint8_t) ( ((_d[2] >> 6U) & (0x03U)) ); + _m->FIU_SMFR_BackRestWidth_Req = (uint8_t) ( (_d[3] & (0x03U)) ); + _m->FIU_SMFR_SeatCushionSupport_Req = (uint8_t) ( ((_d[3] >> 2U) & (0x03U)) ); + _m->FIU_SMFR_SeatMassage_Req = (uint8_t) ( ((_d[3] >> 4U) & (0x03U)) ); + _m->FIU_SMFR_SeatVentilation_Req = (uint8_t) ( ((_d[3] >> 6U) & (0x03U)) ); + _m->FIU_SMFR_SeatVentBalance_Req = (uint8_t) ( (_d[4] & (0x07U)) ); + _m->FIU_SMFR_SeatMassageIntence_Req = (uint8_t) ( ((_d[4] >> 3U) & (0x03U)) ); + _m->FIU_SMFR_SeatHeating_Req = (uint8_t) ( ((_d[4] >> 5U) & (0x03U)) ); + _m->FIU_SMFR_ActiveSupport_Req = (uint8_t) ( ((_d[4] >> 7U) & (0x01U)) ); + _m->FIU_SMFR_SeatHeatBalance_Req = (uint8_t) ( (_d[5] & (0x07U)) ); + _m->FIU_SMFR_SeatMassageType_Req = (uint8_t) ( ((_d[5] >> 3U) & (0x07U)) ); + _m->FIU_SMFR_BackrestMassageType_Req = (uint8_t) ( ((_d[6] & (0x01U)) << 2U) | ((_d[5] >> 6U) & (0x03U)) ); + _m->FIU_SMFR_ComfortMode_Req = (uint8_t) ( ((_d[6] >> 1U) & (0x01U)) ); + _m->FIU_SMFR_ComfortScenario_Req = (uint8_t) ( ((_d[6] >> 2U) & (0x03U)) ); + _m->FIU_SMFR_CarpetHeat_Req = (uint8_t) ( ((_d[6] >> 4U) & (0x01U)) ); + _m->FIU_SMFR_TimerMassage_Req = (uint8_t) ( ((_d[6] >> 5U) & (0x07U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < FIU_SMFR_REQ_CTR_SEATS_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_FIU_SMFR_REQ_CTR_SEATS_candb(&_m->mon1, FIU_SMFR_REQ_CTR_SEATS_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return FIU_SMFR_REQ_CTR_SEATS_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_FIU_SMFR_REQ_CTR_SEATS_candb(FIU_SMFR_REQ_CTR_SEATS_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_SMFR_REQ_CTR_SEATS_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->FIU_SMFR_SeatHeight_Req & (0x03U)) | ((_m->FIU_SMFR_HeadRest_Height_Req & (0x03U)) << 2U) | ((_m->FIU_SMFR_SeatLongitunalReq & (0x03U)) << 4U) | ((_m->FIU_SMFR_SeatHeadRestInclin_Req & (0x03U)) << 6U) ); + cframe->Data[1] |= (uint8_t) ( (_m->FIU_SMFR_SeatSurfaceLong_Req & (0x03U)) | ((_m->FIU_SMFR_SeatLegSupportH_Req & (0x03U)) << 2U) | ((_m->FIU_SMFR_SeatLegSupportLong_Req & (0x03U)) << 4U) | ((_m->FIU_SMFR_SeatInclination_Req & (0x03U)) << 6U) ); + cframe->Data[2] |= (uint8_t) ( (_m->FIU_SMFR_SeatBackRestInc_Req & (0x03U)) | ((_m->FIU_SMFR_SeatLumbarSupHeight_Req & (0x03U)) << 2U) | ((_m->FIU_SMFR_SeatBackRestHeadInc_Req & (0x03U)) << 4U) | ((_m->FIU_SMFR_SeatLumbarSupDepth_Req & (0x03U)) << 6U) ); + cframe->Data[3] |= (uint8_t) ( (_m->FIU_SMFR_BackRestWidth_Req & (0x03U)) | ((_m->FIU_SMFR_SeatCushionSupport_Req & (0x03U)) << 2U) | ((_m->FIU_SMFR_SeatMassage_Req & (0x03U)) << 4U) | ((_m->FIU_SMFR_SeatVentilation_Req & (0x03U)) << 6U) ); + cframe->Data[4] |= (uint8_t) ( (_m->FIU_SMFR_SeatVentBalance_Req & (0x07U)) | ((_m->FIU_SMFR_SeatMassageIntence_Req & (0x03U)) << 3U) | ((_m->FIU_SMFR_SeatHeating_Req & (0x03U)) << 5U) | ((_m->FIU_SMFR_ActiveSupport_Req & (0x01U)) << 7U) ); + cframe->Data[5] |= (uint8_t) ( (_m->FIU_SMFR_SeatHeatBalance_Req & (0x07U)) | ((_m->FIU_SMFR_SeatMassageType_Req & (0x07U)) << 3U) | ((_m->FIU_SMFR_BackrestMassageType_Req & (0x03U)) << 6U) ); + cframe->Data[6] |= (uint8_t) ( ((_m->FIU_SMFR_BackrestMassageType_Req >> 2U) & (0x01U)) | ((_m->FIU_SMFR_ComfortMode_Req & (0x01U)) << 1U) | ((_m->FIU_SMFR_ComfortScenario_Req & (0x03U)) << 2U) | ((_m->FIU_SMFR_CarpetHeat_Req & (0x01U)) << 4U) | ((_m->FIU_SMFR_TimerMassage_Req & (0x07U)) << 5U) ); + + cframe->MsgId = (uint32_t) FIU_SMFR_REQ_CTR_SEATS_CANID; + cframe->DLC = (uint8_t) FIU_SMFR_REQ_CTR_SEATS_DLC; + cframe->IDE = (uint8_t) FIU_SMFR_REQ_CTR_SEATS_IDE; + return FIU_SMFR_REQ_CTR_SEATS_CANID; +} + +#else + +uint32_t Pack_FIU_SMFR_REQ_CTR_SEATS_candb(FIU_SMFR_REQ_CTR_SEATS_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_SMFR_REQ_CTR_SEATS_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->FIU_SMFR_SeatHeight_Req & (0x03U)) | ((_m->FIU_SMFR_HeadRest_Height_Req & (0x03U)) << 2U) | ((_m->FIU_SMFR_SeatLongitunalReq & (0x03U)) << 4U) | ((_m->FIU_SMFR_SeatHeadRestInclin_Req & (0x03U)) << 6U) ); + _d[1] |= (uint8_t) ( (_m->FIU_SMFR_SeatSurfaceLong_Req & (0x03U)) | ((_m->FIU_SMFR_SeatLegSupportH_Req & (0x03U)) << 2U) | ((_m->FIU_SMFR_SeatLegSupportLong_Req & (0x03U)) << 4U) | ((_m->FIU_SMFR_SeatInclination_Req & (0x03U)) << 6U) ); + _d[2] |= (uint8_t) ( (_m->FIU_SMFR_SeatBackRestInc_Req & (0x03U)) | ((_m->FIU_SMFR_SeatLumbarSupHeight_Req & (0x03U)) << 2U) | ((_m->FIU_SMFR_SeatBackRestHeadInc_Req & (0x03U)) << 4U) | ((_m->FIU_SMFR_SeatLumbarSupDepth_Req & (0x03U)) << 6U) ); + _d[3] |= (uint8_t) ( (_m->FIU_SMFR_BackRestWidth_Req & (0x03U)) | ((_m->FIU_SMFR_SeatCushionSupport_Req & (0x03U)) << 2U) | ((_m->FIU_SMFR_SeatMassage_Req & (0x03U)) << 4U) | ((_m->FIU_SMFR_SeatVentilation_Req & (0x03U)) << 6U) ); + _d[4] |= (uint8_t) ( (_m->FIU_SMFR_SeatVentBalance_Req & (0x07U)) | ((_m->FIU_SMFR_SeatMassageIntence_Req & (0x03U)) << 3U) | ((_m->FIU_SMFR_SeatHeating_Req & (0x03U)) << 5U) | ((_m->FIU_SMFR_ActiveSupport_Req & (0x01U)) << 7U) ); + _d[5] |= (uint8_t) ( (_m->FIU_SMFR_SeatHeatBalance_Req & (0x07U)) | ((_m->FIU_SMFR_SeatMassageType_Req & (0x07U)) << 3U) | ((_m->FIU_SMFR_BackrestMassageType_Req & (0x03U)) << 6U) ); + _d[6] |= (uint8_t) ( ((_m->FIU_SMFR_BackrestMassageType_Req >> 2U) & (0x01U)) | ((_m->FIU_SMFR_ComfortMode_Req & (0x01U)) << 1U) | ((_m->FIU_SMFR_ComfortScenario_Req & (0x03U)) << 2U) | ((_m->FIU_SMFR_CarpetHeat_Req & (0x01U)) << 4U) | ((_m->FIU_SMFR_TimerMassage_Req & (0x07U)) << 5U) ); + + *_len = (uint8_t) FIU_SMFR_REQ_CTR_SEATS_DLC; + *_ide = (uint8_t) FIU_SMFR_REQ_CTR_SEATS_IDE; + return FIU_SMFR_REQ_CTR_SEATS_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SMFL_MEM1_candb(SMFL_MEM1_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->SMFL_PosnActSeatI_Val_ro = (uint8_t) ( (_d[0] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMFL_PosnActSeatI_Val_phys = (sigfloat_t)(CANDB_SMFL_PosnActSeatI_Val_ro_fromS(_m->SMFL_PosnActSeatI_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMFL_PosnActSeatBRW_Val_ro = (uint8_t) ( (_d[1] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMFL_PosnActSeatBRW_Val_phys = (uint16_t) CANDB_SMFL_PosnActSeatBRW_Val_ro_fromS(_m->SMFL_PosnActSeatBRW_Val_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->SMFL_PosnActSeatFRH_Val_ro = (uint8_t) ( (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMFL_PosnActSeatFRH_Val_phys = (sigfloat_t)(CANDB_SMFL_PosnActSeatFRH_Val_ro_fromS(_m->SMFL_PosnActSeatFRH_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMFL_PosnActSeatFRL_Val_ro = (uint8_t) ( (_d[3] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMFL_PosnActSeatFRL_Val_phys = (sigfloat_t)(CANDB_SMFL_PosnActSeatFRL_Val_ro_fromS(_m->SMFL_PosnActSeatFRL_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMFL_PosnActSeatH_Val_ro = (uint8_t) ( (_d[4] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMFL_PosnActSeatH_Val_phys = (sigfloat_t)(CANDB_SMFL_PosnActSeatH_Val_ro_fromS(_m->SMFL_PosnActSeatH_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMFL_PosnActSeatHRH_Val_ro = (uint8_t) ( (_d[5] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMFL_PosnActSeatHRH_Val_phys = (sigfloat_t)(CANDB_SMFL_PosnActSeatHRH_Val_ro_fromS(_m->SMFL_PosnActSeatHRH_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMFL_PosnActSeatL_Val_ro = (uint8_t) ( (_d[6] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMFL_PosnActSeatL_Val_phys = (sigfloat_t)(CANDB_SMFL_PosnActSeatL_Val_ro_fromS(_m->SMFL_PosnActSeatL_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMFL_PosnActSeatSL_Val_ro = (uint8_t) ( (_d[7] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMFL_PosnActSeatSL_Val_phys = (sigfloat_t)(CANDB_SMFL_PosnActSeatSL_Val_ro_fromS(_m->SMFL_PosnActSeatSL_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < SMFL_MEM1_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_SMFL_MEM1_candb(&_m->mon1, SMFL_MEM1_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return SMFL_MEM1_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_SMFL_MEM1_candb(SMFL_MEM1_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SMFL_MEM1_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->SMFL_PosnActSeatI_Val_ro = (uint8_t) CANDB_SMFL_PosnActSeatI_Val_ro_toS(_m->SMFL_PosnActSeatI_Val_phys); + _m->SMFL_PosnActSeatBRW_Val_ro = (uint8_t) CANDB_SMFL_PosnActSeatBRW_Val_ro_toS(_m->SMFL_PosnActSeatBRW_Val_phys); + _m->SMFL_PosnActSeatFRH_Val_ro = (uint8_t) CANDB_SMFL_PosnActSeatFRH_Val_ro_toS(_m->SMFL_PosnActSeatFRH_Val_phys); + _m->SMFL_PosnActSeatFRL_Val_ro = (uint8_t) CANDB_SMFL_PosnActSeatFRL_Val_ro_toS(_m->SMFL_PosnActSeatFRL_Val_phys); + _m->SMFL_PosnActSeatH_Val_ro = (uint8_t) CANDB_SMFL_PosnActSeatH_Val_ro_toS(_m->SMFL_PosnActSeatH_Val_phys); + _m->SMFL_PosnActSeatHRH_Val_ro = (uint8_t) CANDB_SMFL_PosnActSeatHRH_Val_ro_toS(_m->SMFL_PosnActSeatHRH_Val_phys); + _m->SMFL_PosnActSeatL_Val_ro = (uint8_t) CANDB_SMFL_PosnActSeatL_Val_ro_toS(_m->SMFL_PosnActSeatL_Val_phys); + _m->SMFL_PosnActSeatSL_Val_ro = (uint8_t) CANDB_SMFL_PosnActSeatSL_Val_ro_toS(_m->SMFL_PosnActSeatSL_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->SMFL_PosnActSeatI_Val_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->SMFL_PosnActSeatBRW_Val_ro & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->SMFL_PosnActSeatFRH_Val_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->SMFL_PosnActSeatFRL_Val_ro & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->SMFL_PosnActSeatH_Val_ro & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->SMFL_PosnActSeatHRH_Val_ro & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->SMFL_PosnActSeatL_Val_ro & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->SMFL_PosnActSeatSL_Val_ro & (0xFFU)) ); + + cframe->MsgId = (uint32_t) SMFL_MEM1_CANID; + cframe->DLC = (uint8_t) SMFL_MEM1_DLC; + cframe->IDE = (uint8_t) SMFL_MEM1_IDE; + return SMFL_MEM1_CANID; +} + +#else + +uint32_t Pack_SMFL_MEM1_candb(SMFL_MEM1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SMFL_MEM1_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->SMFL_PosnActSeatI_Val_ro = (uint8_t) CANDB_SMFL_PosnActSeatI_Val_ro_toS(_m->SMFL_PosnActSeatI_Val_phys); + _m->SMFL_PosnActSeatBRW_Val_ro = (uint8_t) CANDB_SMFL_PosnActSeatBRW_Val_ro_toS(_m->SMFL_PosnActSeatBRW_Val_phys); + _m->SMFL_PosnActSeatFRH_Val_ro = (uint8_t) CANDB_SMFL_PosnActSeatFRH_Val_ro_toS(_m->SMFL_PosnActSeatFRH_Val_phys); + _m->SMFL_PosnActSeatFRL_Val_ro = (uint8_t) CANDB_SMFL_PosnActSeatFRL_Val_ro_toS(_m->SMFL_PosnActSeatFRL_Val_phys); + _m->SMFL_PosnActSeatH_Val_ro = (uint8_t) CANDB_SMFL_PosnActSeatH_Val_ro_toS(_m->SMFL_PosnActSeatH_Val_phys); + _m->SMFL_PosnActSeatHRH_Val_ro = (uint8_t) CANDB_SMFL_PosnActSeatHRH_Val_ro_toS(_m->SMFL_PosnActSeatHRH_Val_phys); + _m->SMFL_PosnActSeatL_Val_ro = (uint8_t) CANDB_SMFL_PosnActSeatL_Val_ro_toS(_m->SMFL_PosnActSeatL_Val_phys); + _m->SMFL_PosnActSeatSL_Val_ro = (uint8_t) CANDB_SMFL_PosnActSeatSL_Val_ro_toS(_m->SMFL_PosnActSeatSL_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->SMFL_PosnActSeatI_Val_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( (_m->SMFL_PosnActSeatBRW_Val_ro & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->SMFL_PosnActSeatFRH_Val_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->SMFL_PosnActSeatFRL_Val_ro & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->SMFL_PosnActSeatH_Val_ro & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->SMFL_PosnActSeatHRH_Val_ro & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->SMFL_PosnActSeatL_Val_ro & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->SMFL_PosnActSeatSL_Val_ro & (0xFFU)) ); + + *_len = (uint8_t) SMFL_MEM1_DLC; + *_ide = (uint8_t) SMFL_MEM1_IDE; + return SMFL_MEM1_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_MEM_SMFL1_candb(BCM_MEM_SMFL1_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->BCM_FLMemPosnActSeatI_Val_ro = (uint8_t) ( (_d[0] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_FLMemPosnActSeatI_Val_phys = (sigfloat_t)(CANDB_BCM_FLMemPosnActSeatI_Val_ro_fromS(_m->BCM_FLMemPosnActSeatI_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_FLMemPosnActSeatBRW_Val_ro = (uint8_t) ( (_d[1] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_FLMemPosnActSeatBRW_Val_phys = (uint16_t) CANDB_BCM_FLMemPosnActSeatBRW_Val_ro_fromS(_m->BCM_FLMemPosnActSeatBRW_Val_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_FLMemPosnActSeatFRH_Val_ro = (uint8_t) ( (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_FLMemPosnActSeatFRH_Val_phys = (sigfloat_t)(CANDB_BCM_FLMemPosnActSeatFRH_Val_ro_fromS(_m->BCM_FLMemPosnActSeatFRH_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_FLMemPosnActSeatFRL_Val_ro = (uint8_t) ( (_d[3] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_FLMemPosnActSeatFRL_Val_phys = (sigfloat_t)(CANDB_BCM_FLMemPosnActSeatFRL_Val_ro_fromS(_m->BCM_FLMemPosnActSeatFRL_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_FLMemPosnActSeatH_Val_ro = (uint8_t) ( (_d[4] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_FLMemPosnActSeatH_Val_phys = (sigfloat_t)(CANDB_BCM_FLMemPosnActSeatH_Val_ro_fromS(_m->BCM_FLMemPosnActSeatH_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_FLMemPosnActSeatHRH_Val_ro = (uint8_t) ( (_d[5] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_FLMemPosnActSeatHRH_Val_phys = (sigfloat_t)(CANDB_BCM_FLMemPosnActSeatHRH_Val_ro_fromS(_m->BCM_FLMemPosnActSeatHRH_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_FLMemPosnActSeatL_Val_ro = (uint8_t) ( (_d[6] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_FLMemPosnActSeatL_Val_phys = (sigfloat_t)(CANDB_BCM_FLMemPosnActSeatL_Val_ro_fromS(_m->BCM_FLMemPosnActSeatL_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_FLMemPosnActSeatSL_Val_ro = (uint8_t) ( (_d[7] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_FLMemPosnActSeatSL_Val_phys = (sigfloat_t)(CANDB_BCM_FLMemPosnActSeatSL_Val_ro_fromS(_m->BCM_FLMemPosnActSeatSL_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < BCM_MEM_SMFL1_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_BCM_MEM_SMFL1_candb(&_m->mon1, BCM_MEM_SMFL1_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return BCM_MEM_SMFL1_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_BCM_MEM_SMFL1_candb(BCM_MEM_SMFL1_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_MEM_SMFL1_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_FLMemPosnActSeatI_Val_ro = (uint8_t) CANDB_BCM_FLMemPosnActSeatI_Val_ro_toS(_m->BCM_FLMemPosnActSeatI_Val_phys); + _m->BCM_FLMemPosnActSeatBRW_Val_ro = (uint8_t) CANDB_BCM_FLMemPosnActSeatBRW_Val_ro_toS(_m->BCM_FLMemPosnActSeatBRW_Val_phys); + _m->BCM_FLMemPosnActSeatFRH_Val_ro = (uint8_t) CANDB_BCM_FLMemPosnActSeatFRH_Val_ro_toS(_m->BCM_FLMemPosnActSeatFRH_Val_phys); + _m->BCM_FLMemPosnActSeatFRL_Val_ro = (uint8_t) CANDB_BCM_FLMemPosnActSeatFRL_Val_ro_toS(_m->BCM_FLMemPosnActSeatFRL_Val_phys); + _m->BCM_FLMemPosnActSeatH_Val_ro = (uint8_t) CANDB_BCM_FLMemPosnActSeatH_Val_ro_toS(_m->BCM_FLMemPosnActSeatH_Val_phys); + _m->BCM_FLMemPosnActSeatHRH_Val_ro = (uint8_t) CANDB_BCM_FLMemPosnActSeatHRH_Val_ro_toS(_m->BCM_FLMemPosnActSeatHRH_Val_phys); + _m->BCM_FLMemPosnActSeatL_Val_ro = (uint8_t) CANDB_BCM_FLMemPosnActSeatL_Val_ro_toS(_m->BCM_FLMemPosnActSeatL_Val_phys); + _m->BCM_FLMemPosnActSeatSL_Val_ro = (uint8_t) CANDB_BCM_FLMemPosnActSeatSL_Val_ro_toS(_m->BCM_FLMemPosnActSeatSL_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->BCM_FLMemPosnActSeatI_Val_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->BCM_FLMemPosnActSeatBRW_Val_ro & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->BCM_FLMemPosnActSeatFRH_Val_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->BCM_FLMemPosnActSeatFRL_Val_ro & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->BCM_FLMemPosnActSeatH_Val_ro & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->BCM_FLMemPosnActSeatHRH_Val_ro & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->BCM_FLMemPosnActSeatL_Val_ro & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->BCM_FLMemPosnActSeatSL_Val_ro & (0xFFU)) ); + + cframe->MsgId = (uint32_t) BCM_MEM_SMFL1_CANID; + cframe->DLC = (uint8_t) BCM_MEM_SMFL1_DLC; + cframe->IDE = (uint8_t) BCM_MEM_SMFL1_IDE; + return BCM_MEM_SMFL1_CANID; +} + +#else + +uint32_t Pack_BCM_MEM_SMFL1_candb(BCM_MEM_SMFL1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_MEM_SMFL1_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_FLMemPosnActSeatI_Val_ro = (uint8_t) CANDB_BCM_FLMemPosnActSeatI_Val_ro_toS(_m->BCM_FLMemPosnActSeatI_Val_phys); + _m->BCM_FLMemPosnActSeatBRW_Val_ro = (uint8_t) CANDB_BCM_FLMemPosnActSeatBRW_Val_ro_toS(_m->BCM_FLMemPosnActSeatBRW_Val_phys); + _m->BCM_FLMemPosnActSeatFRH_Val_ro = (uint8_t) CANDB_BCM_FLMemPosnActSeatFRH_Val_ro_toS(_m->BCM_FLMemPosnActSeatFRH_Val_phys); + _m->BCM_FLMemPosnActSeatFRL_Val_ro = (uint8_t) CANDB_BCM_FLMemPosnActSeatFRL_Val_ro_toS(_m->BCM_FLMemPosnActSeatFRL_Val_phys); + _m->BCM_FLMemPosnActSeatH_Val_ro = (uint8_t) CANDB_BCM_FLMemPosnActSeatH_Val_ro_toS(_m->BCM_FLMemPosnActSeatH_Val_phys); + _m->BCM_FLMemPosnActSeatHRH_Val_ro = (uint8_t) CANDB_BCM_FLMemPosnActSeatHRH_Val_ro_toS(_m->BCM_FLMemPosnActSeatHRH_Val_phys); + _m->BCM_FLMemPosnActSeatL_Val_ro = (uint8_t) CANDB_BCM_FLMemPosnActSeatL_Val_ro_toS(_m->BCM_FLMemPosnActSeatL_Val_phys); + _m->BCM_FLMemPosnActSeatSL_Val_ro = (uint8_t) CANDB_BCM_FLMemPosnActSeatSL_Val_ro_toS(_m->BCM_FLMemPosnActSeatSL_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->BCM_FLMemPosnActSeatI_Val_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( (_m->BCM_FLMemPosnActSeatBRW_Val_ro & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->BCM_FLMemPosnActSeatFRH_Val_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->BCM_FLMemPosnActSeatFRL_Val_ro & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->BCM_FLMemPosnActSeatH_Val_ro & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->BCM_FLMemPosnActSeatHRH_Val_ro & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->BCM_FLMemPosnActSeatL_Val_ro & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->BCM_FLMemPosnActSeatSL_Val_ro & (0xFFU)) ); + + *_len = (uint8_t) BCM_MEM_SMFL1_DLC; + *_ide = (uint8_t) BCM_MEM_SMFL1_IDE; + return BCM_MEM_SMFL1_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SMFL_MEM2_candb(SMFL_MEM2_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->SMFL_PosnActSeatBRHI_Val_ro = (uint8_t) ( (_d[0] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMFL_PosnActSeatBRHI_Val_phys = (sigfloat_t)(CANDB_SMFL_PosnActSeatBRHI_Val_ro_fromS(_m->SMFL_PosnActSeatBRHI_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMFL_PosnActSeatHRHI_Val_ro = (uint8_t) ( (_d[1] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMFL_PosnActSeatHRHI_Val_phys = (sigfloat_t)(CANDB_SMFL_PosnActSeatHRHI_Val_ro_fromS(_m->SMFL_PosnActSeatHRHI_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMFL_PosnActSeatBRI_Val_ro = (uint8_t) ( (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMFL_PosnActSeatBRI_Val_phys = (sigfloat_t)(CANDB_SMFL_PosnActSeatBRI_Val_ro_fromS(_m->SMFL_PosnActSeatBRI_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMFL_ActHeatBalance_Val = (uint8_t) ( (_d[3] & (0x07U)) ); + _m->SMFL_ActVentBalance_Val = (uint8_t) ( ((_d[3] >> 3U) & (0x07U)) ); + _m->SMFL_PosnPrsnSeatCS_Val_ro = (uint8_t) ( (_d[5] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMFL_PosnPrsnSeatCS_Val_phys = (sigfloat_t)(CANDB_SMFL_PosnPrsnSeatCS_Val_ro_fromS(_m->SMFL_PosnPrsnSeatCS_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMFL_PosnPrsnSeatLSH_Val_ro = (uint8_t) ( (_d[6] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMFL_PosnPrsnSeatLSH_Val_phys = (sigfloat_t)(CANDB_SMFL_PosnPrsnSeatLSH_Val_ro_fromS(_m->SMFL_PosnPrsnSeatLSH_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMFL_PosnPrsnSeatLSD_Val_ro = (uint8_t) ( (_d[7] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMFL_PosnPrsnSeatLSD_Val_phys = (sigfloat_t)(CANDB_SMFL_PosnPrsnSeatLSD_Val_ro_fromS(_m->SMFL_PosnPrsnSeatLSD_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < SMFL_MEM2_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_SMFL_MEM2_candb(&_m->mon1, SMFL_MEM2_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return SMFL_MEM2_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_SMFL_MEM2_candb(SMFL_MEM2_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SMFL_MEM2_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->SMFL_PosnActSeatBRHI_Val_ro = (uint8_t) CANDB_SMFL_PosnActSeatBRHI_Val_ro_toS(_m->SMFL_PosnActSeatBRHI_Val_phys); + _m->SMFL_PosnActSeatHRHI_Val_ro = (uint8_t) CANDB_SMFL_PosnActSeatHRHI_Val_ro_toS(_m->SMFL_PosnActSeatHRHI_Val_phys); + _m->SMFL_PosnActSeatBRI_Val_ro = (uint8_t) CANDB_SMFL_PosnActSeatBRI_Val_ro_toS(_m->SMFL_PosnActSeatBRI_Val_phys); + _m->SMFL_PosnPrsnSeatCS_Val_ro = (uint8_t) CANDB_SMFL_PosnPrsnSeatCS_Val_ro_toS(_m->SMFL_PosnPrsnSeatCS_Val_phys); + _m->SMFL_PosnPrsnSeatLSH_Val_ro = (uint8_t) CANDB_SMFL_PosnPrsnSeatLSH_Val_ro_toS(_m->SMFL_PosnPrsnSeatLSH_Val_phys); + _m->SMFL_PosnPrsnSeatLSD_Val_ro = (uint8_t) CANDB_SMFL_PosnPrsnSeatLSD_Val_ro_toS(_m->SMFL_PosnPrsnSeatLSD_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->SMFL_PosnActSeatBRHI_Val_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->SMFL_PosnActSeatHRHI_Val_ro & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->SMFL_PosnActSeatBRI_Val_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->SMFL_ActHeatBalance_Val & (0x07U)) | ((_m->SMFL_ActVentBalance_Val & (0x07U)) << 3U) ); + cframe->Data[5] |= (uint8_t) ( (_m->SMFL_PosnPrsnSeatCS_Val_ro & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->SMFL_PosnPrsnSeatLSH_Val_ro & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->SMFL_PosnPrsnSeatLSD_Val_ro & (0xFFU)) ); + + cframe->MsgId = (uint32_t) SMFL_MEM2_CANID; + cframe->DLC = (uint8_t) SMFL_MEM2_DLC; + cframe->IDE = (uint8_t) SMFL_MEM2_IDE; + return SMFL_MEM2_CANID; +} + +#else + +uint32_t Pack_SMFL_MEM2_candb(SMFL_MEM2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SMFL_MEM2_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->SMFL_PosnActSeatBRHI_Val_ro = (uint8_t) CANDB_SMFL_PosnActSeatBRHI_Val_ro_toS(_m->SMFL_PosnActSeatBRHI_Val_phys); + _m->SMFL_PosnActSeatHRHI_Val_ro = (uint8_t) CANDB_SMFL_PosnActSeatHRHI_Val_ro_toS(_m->SMFL_PosnActSeatHRHI_Val_phys); + _m->SMFL_PosnActSeatBRI_Val_ro = (uint8_t) CANDB_SMFL_PosnActSeatBRI_Val_ro_toS(_m->SMFL_PosnActSeatBRI_Val_phys); + _m->SMFL_PosnPrsnSeatCS_Val_ro = (uint8_t) CANDB_SMFL_PosnPrsnSeatCS_Val_ro_toS(_m->SMFL_PosnPrsnSeatCS_Val_phys); + _m->SMFL_PosnPrsnSeatLSH_Val_ro = (uint8_t) CANDB_SMFL_PosnPrsnSeatLSH_Val_ro_toS(_m->SMFL_PosnPrsnSeatLSH_Val_phys); + _m->SMFL_PosnPrsnSeatLSD_Val_ro = (uint8_t) CANDB_SMFL_PosnPrsnSeatLSD_Val_ro_toS(_m->SMFL_PosnPrsnSeatLSD_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->SMFL_PosnActSeatBRHI_Val_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( (_m->SMFL_PosnActSeatHRHI_Val_ro & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->SMFL_PosnActSeatBRI_Val_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->SMFL_ActHeatBalance_Val & (0x07U)) | ((_m->SMFL_ActVentBalance_Val & (0x07U)) << 3U) ); + _d[5] |= (uint8_t) ( (_m->SMFL_PosnPrsnSeatCS_Val_ro & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->SMFL_PosnPrsnSeatLSH_Val_ro & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->SMFL_PosnPrsnSeatLSD_Val_ro & (0xFFU)) ); + + *_len = (uint8_t) SMFL_MEM2_DLC; + *_ide = (uint8_t) SMFL_MEM2_IDE; + return SMFL_MEM2_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_MEM_SMFL2_candb(BCM_MEM_SMFL2_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->BCM_FLMemPosnActSeatBRHI_Val_ro = (uint8_t) ( (_d[0] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_FLMemPosnActSeatBRHI_Val_phys = (sigfloat_t)(CANDB_BCM_FLMemPosnActSeatBRHI_Val_ro_fromS(_m->BCM_FLMemPosnActSeatBRHI_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_FLMemPosnActSeatHRHI_Val_ro = (uint8_t) ( (_d[1] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_FLMemPosnActSeatHRHI_Val_phys = (sigfloat_t)(CANDB_BCM_FLMemPosnActSeatHRHI_Val_ro_fromS(_m->BCM_FLMemPosnActSeatHRHI_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_FLMemPosnActSeatBRI_Val_ro = (uint8_t) ( (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_FLMemPosnActSeatBRI_Val_phys = (sigfloat_t)(CANDB_BCM_FLMemPosnActSeatBRI_Val_ro_fromS(_m->BCM_FLMemPosnActSeatBRI_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_FLMemActHeatBalance_Val = (uint8_t) ( (_d[3] & (0x07U)) ); + _m->BCM_FLMemActVentBalance_Val = (uint8_t) ( ((_d[3] >> 3U) & (0x07U)) ); + _m->BCM_FLMemPosnPrsnSeatCS_Val_ro = (uint8_t) ( (_d[5] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_FLMemPosnPrsnSeatCS_Val_phys = (sigfloat_t)(CANDB_BCM_FLMemPosnPrsnSeatCS_Val_ro_fromS(_m->BCM_FLMemPosnPrsnSeatCS_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_FLMemPosnPrsnSeatLSH_Val_ro = (uint8_t) ( (_d[6] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_FLMemPosnPrsnSeatLSH_Val_phys = (sigfloat_t)(CANDB_BCM_FLMemPosnPrsnSeatLSH_Val_ro_fromS(_m->BCM_FLMemPosnPrsnSeatLSH_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_FLMemPosnPrsnSeatLSD_Val_ro = (uint8_t) ( (_d[7] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_FLMemPosnPrsnSeatLSD_Val_phys = (sigfloat_t)(CANDB_BCM_FLMemPosnPrsnSeatLSD_Val_ro_fromS(_m->BCM_FLMemPosnPrsnSeatLSD_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < BCM_MEM_SMFL2_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_BCM_MEM_SMFL2_candb(&_m->mon1, BCM_MEM_SMFL2_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return BCM_MEM_SMFL2_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_BCM_MEM_SMFL2_candb(BCM_MEM_SMFL2_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_MEM_SMFL2_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_FLMemPosnActSeatBRHI_Val_ro = (uint8_t) CANDB_BCM_FLMemPosnActSeatBRHI_Val_ro_toS(_m->BCM_FLMemPosnActSeatBRHI_Val_phys); + _m->BCM_FLMemPosnActSeatHRHI_Val_ro = (uint8_t) CANDB_BCM_FLMemPosnActSeatHRHI_Val_ro_toS(_m->BCM_FLMemPosnActSeatHRHI_Val_phys); + _m->BCM_FLMemPosnActSeatBRI_Val_ro = (uint8_t) CANDB_BCM_FLMemPosnActSeatBRI_Val_ro_toS(_m->BCM_FLMemPosnActSeatBRI_Val_phys); + _m->BCM_FLMemPosnPrsnSeatCS_Val_ro = (uint8_t) CANDB_BCM_FLMemPosnPrsnSeatCS_Val_ro_toS(_m->BCM_FLMemPosnPrsnSeatCS_Val_phys); + _m->BCM_FLMemPosnPrsnSeatLSH_Val_ro = (uint8_t) CANDB_BCM_FLMemPosnPrsnSeatLSH_Val_ro_toS(_m->BCM_FLMemPosnPrsnSeatLSH_Val_phys); + _m->BCM_FLMemPosnPrsnSeatLSD_Val_ro = (uint8_t) CANDB_BCM_FLMemPosnPrsnSeatLSD_Val_ro_toS(_m->BCM_FLMemPosnPrsnSeatLSD_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->BCM_FLMemPosnActSeatBRHI_Val_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->BCM_FLMemPosnActSeatHRHI_Val_ro & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->BCM_FLMemPosnActSeatBRI_Val_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->BCM_FLMemActHeatBalance_Val & (0x07U)) | ((_m->BCM_FLMemActVentBalance_Val & (0x07U)) << 3U) ); + cframe->Data[5] |= (uint8_t) ( (_m->BCM_FLMemPosnPrsnSeatCS_Val_ro & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->BCM_FLMemPosnPrsnSeatLSH_Val_ro & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->BCM_FLMemPosnPrsnSeatLSD_Val_ro & (0xFFU)) ); + + cframe->MsgId = (uint32_t) BCM_MEM_SMFL2_CANID; + cframe->DLC = (uint8_t) BCM_MEM_SMFL2_DLC; + cframe->IDE = (uint8_t) BCM_MEM_SMFL2_IDE; + return BCM_MEM_SMFL2_CANID; +} + +#else + +uint32_t Pack_BCM_MEM_SMFL2_candb(BCM_MEM_SMFL2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_MEM_SMFL2_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_FLMemPosnActSeatBRHI_Val_ro = (uint8_t) CANDB_BCM_FLMemPosnActSeatBRHI_Val_ro_toS(_m->BCM_FLMemPosnActSeatBRHI_Val_phys); + _m->BCM_FLMemPosnActSeatHRHI_Val_ro = (uint8_t) CANDB_BCM_FLMemPosnActSeatHRHI_Val_ro_toS(_m->BCM_FLMemPosnActSeatHRHI_Val_phys); + _m->BCM_FLMemPosnActSeatBRI_Val_ro = (uint8_t) CANDB_BCM_FLMemPosnActSeatBRI_Val_ro_toS(_m->BCM_FLMemPosnActSeatBRI_Val_phys); + _m->BCM_FLMemPosnPrsnSeatCS_Val_ro = (uint8_t) CANDB_BCM_FLMemPosnPrsnSeatCS_Val_ro_toS(_m->BCM_FLMemPosnPrsnSeatCS_Val_phys); + _m->BCM_FLMemPosnPrsnSeatLSH_Val_ro = (uint8_t) CANDB_BCM_FLMemPosnPrsnSeatLSH_Val_ro_toS(_m->BCM_FLMemPosnPrsnSeatLSH_Val_phys); + _m->BCM_FLMemPosnPrsnSeatLSD_Val_ro = (uint8_t) CANDB_BCM_FLMemPosnPrsnSeatLSD_Val_ro_toS(_m->BCM_FLMemPosnPrsnSeatLSD_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->BCM_FLMemPosnActSeatBRHI_Val_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( (_m->BCM_FLMemPosnActSeatHRHI_Val_ro & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->BCM_FLMemPosnActSeatBRI_Val_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->BCM_FLMemActHeatBalance_Val & (0x07U)) | ((_m->BCM_FLMemActVentBalance_Val & (0x07U)) << 3U) ); + _d[5] |= (uint8_t) ( (_m->BCM_FLMemPosnPrsnSeatCS_Val_ro & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->BCM_FLMemPosnPrsnSeatLSH_Val_ro & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->BCM_FLMemPosnPrsnSeatLSD_Val_ro & (0xFFU)) ); + + *_len = (uint8_t) BCM_MEM_SMFL2_DLC; + *_ide = (uint8_t) BCM_MEM_SMFL2_IDE; + return BCM_MEM_SMFL2_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SMFR_MEM1_candb(SMFR_MEM1_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->SMFR_PosnActSeatI_Val_ro = (uint8_t) ( (_d[0] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMFR_PosnActSeatI_Val_phys = (sigfloat_t)(CANDB_SMFR_PosnActSeatI_Val_ro_fromS(_m->SMFR_PosnActSeatI_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMFR_PosnActSeatBRW_Val_ro = (uint8_t) ( (_d[1] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMFR_PosnActSeatBRW_Val_phys = (uint16_t) CANDB_SMFR_PosnActSeatBRW_Val_ro_fromS(_m->SMFR_PosnActSeatBRW_Val_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->SMFR_PosnActSeatFRH_Val_ro = (uint8_t) ( (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMFR_PosnActSeatFRH_Val_phys = (sigfloat_t)(CANDB_SMFR_PosnActSeatFRH_Val_ro_fromS(_m->SMFR_PosnActSeatFRH_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMFR_PosnActSeatFRL_Val_ro = (uint8_t) ( (_d[3] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMFR_PosnActSeatFRL_Val_phys = (sigfloat_t)(CANDB_SMFR_PosnActSeatFRL_Val_ro_fromS(_m->SMFR_PosnActSeatFRL_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMFR_PosnActSeatH_Val_ro = (uint8_t) ( (_d[4] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMFR_PosnActSeatH_Val_phys = (sigfloat_t)(CANDB_SMFR_PosnActSeatH_Val_ro_fromS(_m->SMFR_PosnActSeatH_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMFR_PosnActSeatHRH_Val_ro = (uint8_t) ( (_d[5] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMFR_PosnActSeatHRH_Val_phys = (sigfloat_t)(CANDB_SMFR_PosnActSeatHRH_Val_ro_fromS(_m->SMFR_PosnActSeatHRH_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMFR_PosnActSeatL_Val_ro = (uint8_t) ( (_d[6] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMFR_PosnActSeatL_Val_phys = (sigfloat_t)(CANDB_SMFR_PosnActSeatL_Val_ro_fromS(_m->SMFR_PosnActSeatL_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMFR_PosnActSeatSL_Val_ro = (uint8_t) ( (_d[7] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMFR_PosnActSeatSL_Val_phys = (sigfloat_t)(CANDB_SMFR_PosnActSeatSL_Val_ro_fromS(_m->SMFR_PosnActSeatSL_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < SMFR_MEM1_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_SMFR_MEM1_candb(&_m->mon1, SMFR_MEM1_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return SMFR_MEM1_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_SMFR_MEM1_candb(SMFR_MEM1_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SMFR_MEM1_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->SMFR_PosnActSeatI_Val_ro = (uint8_t) CANDB_SMFR_PosnActSeatI_Val_ro_toS(_m->SMFR_PosnActSeatI_Val_phys); + _m->SMFR_PosnActSeatBRW_Val_ro = (uint8_t) CANDB_SMFR_PosnActSeatBRW_Val_ro_toS(_m->SMFR_PosnActSeatBRW_Val_phys); + _m->SMFR_PosnActSeatFRH_Val_ro = (uint8_t) CANDB_SMFR_PosnActSeatFRH_Val_ro_toS(_m->SMFR_PosnActSeatFRH_Val_phys); + _m->SMFR_PosnActSeatFRL_Val_ro = (uint8_t) CANDB_SMFR_PosnActSeatFRL_Val_ro_toS(_m->SMFR_PosnActSeatFRL_Val_phys); + _m->SMFR_PosnActSeatH_Val_ro = (uint8_t) CANDB_SMFR_PosnActSeatH_Val_ro_toS(_m->SMFR_PosnActSeatH_Val_phys); + _m->SMFR_PosnActSeatHRH_Val_ro = (uint8_t) CANDB_SMFR_PosnActSeatHRH_Val_ro_toS(_m->SMFR_PosnActSeatHRH_Val_phys); + _m->SMFR_PosnActSeatL_Val_ro = (uint8_t) CANDB_SMFR_PosnActSeatL_Val_ro_toS(_m->SMFR_PosnActSeatL_Val_phys); + _m->SMFR_PosnActSeatSL_Val_ro = (uint8_t) CANDB_SMFR_PosnActSeatSL_Val_ro_toS(_m->SMFR_PosnActSeatSL_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->SMFR_PosnActSeatI_Val_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->SMFR_PosnActSeatBRW_Val_ro & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->SMFR_PosnActSeatFRH_Val_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->SMFR_PosnActSeatFRL_Val_ro & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->SMFR_PosnActSeatH_Val_ro & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->SMFR_PosnActSeatHRH_Val_ro & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->SMFR_PosnActSeatL_Val_ro & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->SMFR_PosnActSeatSL_Val_ro & (0xFFU)) ); + + cframe->MsgId = (uint32_t) SMFR_MEM1_CANID; + cframe->DLC = (uint8_t) SMFR_MEM1_DLC; + cframe->IDE = (uint8_t) SMFR_MEM1_IDE; + return SMFR_MEM1_CANID; +} + +#else + +uint32_t Pack_SMFR_MEM1_candb(SMFR_MEM1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SMFR_MEM1_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->SMFR_PosnActSeatI_Val_ro = (uint8_t) CANDB_SMFR_PosnActSeatI_Val_ro_toS(_m->SMFR_PosnActSeatI_Val_phys); + _m->SMFR_PosnActSeatBRW_Val_ro = (uint8_t) CANDB_SMFR_PosnActSeatBRW_Val_ro_toS(_m->SMFR_PosnActSeatBRW_Val_phys); + _m->SMFR_PosnActSeatFRH_Val_ro = (uint8_t) CANDB_SMFR_PosnActSeatFRH_Val_ro_toS(_m->SMFR_PosnActSeatFRH_Val_phys); + _m->SMFR_PosnActSeatFRL_Val_ro = (uint8_t) CANDB_SMFR_PosnActSeatFRL_Val_ro_toS(_m->SMFR_PosnActSeatFRL_Val_phys); + _m->SMFR_PosnActSeatH_Val_ro = (uint8_t) CANDB_SMFR_PosnActSeatH_Val_ro_toS(_m->SMFR_PosnActSeatH_Val_phys); + _m->SMFR_PosnActSeatHRH_Val_ro = (uint8_t) CANDB_SMFR_PosnActSeatHRH_Val_ro_toS(_m->SMFR_PosnActSeatHRH_Val_phys); + _m->SMFR_PosnActSeatL_Val_ro = (uint8_t) CANDB_SMFR_PosnActSeatL_Val_ro_toS(_m->SMFR_PosnActSeatL_Val_phys); + _m->SMFR_PosnActSeatSL_Val_ro = (uint8_t) CANDB_SMFR_PosnActSeatSL_Val_ro_toS(_m->SMFR_PosnActSeatSL_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->SMFR_PosnActSeatI_Val_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( (_m->SMFR_PosnActSeatBRW_Val_ro & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->SMFR_PosnActSeatFRH_Val_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->SMFR_PosnActSeatFRL_Val_ro & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->SMFR_PosnActSeatH_Val_ro & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->SMFR_PosnActSeatHRH_Val_ro & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->SMFR_PosnActSeatL_Val_ro & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->SMFR_PosnActSeatSL_Val_ro & (0xFFU)) ); + + *_len = (uint8_t) SMFR_MEM1_DLC; + *_ide = (uint8_t) SMFR_MEM1_IDE; + return SMFR_MEM1_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_MEM_SMFR1_candb(BCM_MEM_SMFR1_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->BCM_FRMemPosnActSeatI_Val_ro = (uint8_t) ( (_d[0] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_FRMemPosnActSeatI_Val_phys = (sigfloat_t)(CANDB_BCM_FRMemPosnActSeatI_Val_ro_fromS(_m->BCM_FRMemPosnActSeatI_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_FRMemPosnActSeatBRW_Val_ro = (uint8_t) ( (_d[1] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_FRMemPosnActSeatBRW_Val_phys = (uint16_t) CANDB_BCM_FRMemPosnActSeatBRW_Val_ro_fromS(_m->BCM_FRMemPosnActSeatBRW_Val_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_FRMemPosnActSeatFRH_Val_ro = (uint8_t) ( (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_FRMemPosnActSeatFRH_Val_phys = (sigfloat_t)(CANDB_BCM_FRMemPosnActSeatFRH_Val_ro_fromS(_m->BCM_FRMemPosnActSeatFRH_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_FRMemPosnActSeatFRL_Val_ro = (uint8_t) ( (_d[3] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_FRMemPosnActSeatFRL_Val_phys = (sigfloat_t)(CANDB_BCM_FRMemPosnActSeatFRL_Val_ro_fromS(_m->BCM_FRMemPosnActSeatFRL_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_FRMemPosnActSeatH_Val_ro = (uint8_t) ( (_d[4] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_FRMemPosnActSeatH_Val_phys = (sigfloat_t)(CANDB_BCM_FRMemPosnActSeatH_Val_ro_fromS(_m->BCM_FRMemPosnActSeatH_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_FRMemPosnActSeatHRH_Val_ro = (uint8_t) ( (_d[5] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_FRMemPosnActSeatHRH_Val_phys = (sigfloat_t)(CANDB_BCM_FRMemPosnActSeatHRH_Val_ro_fromS(_m->BCM_FRMemPosnActSeatHRH_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_FRMemPosnActSeatL_Val_ro = (uint8_t) ( (_d[6] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_FRMemPosnActSeatL_Val_phys = (sigfloat_t)(CANDB_BCM_FRMemPosnActSeatL_Val_ro_fromS(_m->BCM_FRMemPosnActSeatL_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_FRMemPosnActSeatSL_Val_ro = (uint8_t) ( (_d[7] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_FRMemPosnActSeatSL_Val_phys = (sigfloat_t)(CANDB_BCM_FRMemPosnActSeatSL_Val_ro_fromS(_m->BCM_FRMemPosnActSeatSL_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < BCM_MEM_SMFR1_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_BCM_MEM_SMFR1_candb(&_m->mon1, BCM_MEM_SMFR1_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return BCM_MEM_SMFR1_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_BCM_MEM_SMFR1_candb(BCM_MEM_SMFR1_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_MEM_SMFR1_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_FRMemPosnActSeatI_Val_ro = (uint8_t) CANDB_BCM_FRMemPosnActSeatI_Val_ro_toS(_m->BCM_FRMemPosnActSeatI_Val_phys); + _m->BCM_FRMemPosnActSeatBRW_Val_ro = (uint8_t) CANDB_BCM_FRMemPosnActSeatBRW_Val_ro_toS(_m->BCM_FRMemPosnActSeatBRW_Val_phys); + _m->BCM_FRMemPosnActSeatFRH_Val_ro = (uint8_t) CANDB_BCM_FRMemPosnActSeatFRH_Val_ro_toS(_m->BCM_FRMemPosnActSeatFRH_Val_phys); + _m->BCM_FRMemPosnActSeatFRL_Val_ro = (uint8_t) CANDB_BCM_FRMemPosnActSeatFRL_Val_ro_toS(_m->BCM_FRMemPosnActSeatFRL_Val_phys); + _m->BCM_FRMemPosnActSeatH_Val_ro = (uint8_t) CANDB_BCM_FRMemPosnActSeatH_Val_ro_toS(_m->BCM_FRMemPosnActSeatH_Val_phys); + _m->BCM_FRMemPosnActSeatHRH_Val_ro = (uint8_t) CANDB_BCM_FRMemPosnActSeatHRH_Val_ro_toS(_m->BCM_FRMemPosnActSeatHRH_Val_phys); + _m->BCM_FRMemPosnActSeatL_Val_ro = (uint8_t) CANDB_BCM_FRMemPosnActSeatL_Val_ro_toS(_m->BCM_FRMemPosnActSeatL_Val_phys); + _m->BCM_FRMemPosnActSeatSL_Val_ro = (uint8_t) CANDB_BCM_FRMemPosnActSeatSL_Val_ro_toS(_m->BCM_FRMemPosnActSeatSL_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->BCM_FRMemPosnActSeatI_Val_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->BCM_FRMemPosnActSeatBRW_Val_ro & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->BCM_FRMemPosnActSeatFRH_Val_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->BCM_FRMemPosnActSeatFRL_Val_ro & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->BCM_FRMemPosnActSeatH_Val_ro & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->BCM_FRMemPosnActSeatHRH_Val_ro & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->BCM_FRMemPosnActSeatL_Val_ro & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->BCM_FRMemPosnActSeatSL_Val_ro & (0xFFU)) ); + + cframe->MsgId = (uint32_t) BCM_MEM_SMFR1_CANID; + cframe->DLC = (uint8_t) BCM_MEM_SMFR1_DLC; + cframe->IDE = (uint8_t) BCM_MEM_SMFR1_IDE; + return BCM_MEM_SMFR1_CANID; +} + +#else + +uint32_t Pack_BCM_MEM_SMFR1_candb(BCM_MEM_SMFR1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_MEM_SMFR1_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_FRMemPosnActSeatI_Val_ro = (uint8_t) CANDB_BCM_FRMemPosnActSeatI_Val_ro_toS(_m->BCM_FRMemPosnActSeatI_Val_phys); + _m->BCM_FRMemPosnActSeatBRW_Val_ro = (uint8_t) CANDB_BCM_FRMemPosnActSeatBRW_Val_ro_toS(_m->BCM_FRMemPosnActSeatBRW_Val_phys); + _m->BCM_FRMemPosnActSeatFRH_Val_ro = (uint8_t) CANDB_BCM_FRMemPosnActSeatFRH_Val_ro_toS(_m->BCM_FRMemPosnActSeatFRH_Val_phys); + _m->BCM_FRMemPosnActSeatFRL_Val_ro = (uint8_t) CANDB_BCM_FRMemPosnActSeatFRL_Val_ro_toS(_m->BCM_FRMemPosnActSeatFRL_Val_phys); + _m->BCM_FRMemPosnActSeatH_Val_ro = (uint8_t) CANDB_BCM_FRMemPosnActSeatH_Val_ro_toS(_m->BCM_FRMemPosnActSeatH_Val_phys); + _m->BCM_FRMemPosnActSeatHRH_Val_ro = (uint8_t) CANDB_BCM_FRMemPosnActSeatHRH_Val_ro_toS(_m->BCM_FRMemPosnActSeatHRH_Val_phys); + _m->BCM_FRMemPosnActSeatL_Val_ro = (uint8_t) CANDB_BCM_FRMemPosnActSeatL_Val_ro_toS(_m->BCM_FRMemPosnActSeatL_Val_phys); + _m->BCM_FRMemPosnActSeatSL_Val_ro = (uint8_t) CANDB_BCM_FRMemPosnActSeatSL_Val_ro_toS(_m->BCM_FRMemPosnActSeatSL_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->BCM_FRMemPosnActSeatI_Val_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( (_m->BCM_FRMemPosnActSeatBRW_Val_ro & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->BCM_FRMemPosnActSeatFRH_Val_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->BCM_FRMemPosnActSeatFRL_Val_ro & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->BCM_FRMemPosnActSeatH_Val_ro & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->BCM_FRMemPosnActSeatHRH_Val_ro & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->BCM_FRMemPosnActSeatL_Val_ro & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->BCM_FRMemPosnActSeatSL_Val_ro & (0xFFU)) ); + + *_len = (uint8_t) BCM_MEM_SMFR1_DLC; + *_ide = (uint8_t) BCM_MEM_SMFR1_IDE; + return BCM_MEM_SMFR1_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SMFR_MEM2_candb(SMFR_MEM2_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->SMFR_PosnActSeatBRHI_Val_ro = (uint8_t) ( (_d[0] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMFR_PosnActSeatBRHI_Val_phys = (sigfloat_t)(CANDB_SMFR_PosnActSeatBRHI_Val_ro_fromS(_m->SMFR_PosnActSeatBRHI_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMFR_PosnActSeatHRHI_Val_ro = (uint8_t) ( (_d[1] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMFR_PosnActSeatHRHI_Val_phys = (sigfloat_t)(CANDB_SMFR_PosnActSeatHRHI_Val_ro_fromS(_m->SMFR_PosnActSeatHRHI_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMFR_PosnActSeatBRI_Val_ro = (uint8_t) ( (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMFR_PosnActSeatBRI_Val_phys = (sigfloat_t)(CANDB_SMFR_PosnActSeatBRI_Val_ro_fromS(_m->SMFR_PosnActSeatBRI_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMFR_ActHeatBalance_Val = (uint8_t) ( (_d[3] & (0x07U)) ); + _m->SMFR_ActVentBalance_Stat = (uint8_t) ( ((_d[3] >> 3U) & (0x07U)) ); + _m->SMFR_PosnPrsnSeatCS_Val_ro = (uint8_t) ( ((_d[4] & (0x3FU)) << 2U) | ((_d[3] >> 6U) & (0x03U)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMFR_PosnPrsnSeatCS_Val_phys = (sigfloat_t)(CANDB_SMFR_PosnPrsnSeatCS_Val_ro_fromS(_m->SMFR_PosnPrsnSeatCS_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMFR_PosnPrsnSeatLSH_Val_ro = (uint8_t) ( ((_d[5] & (0x3FU)) << 2U) | ((_d[4] >> 6U) & (0x03U)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMFR_PosnPrsnSeatLSH_Val_phys = (sigfloat_t)(CANDB_SMFR_PosnPrsnSeatLSH_Val_ro_fromS(_m->SMFR_PosnPrsnSeatLSH_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMFR_PosnPrsnSeatLSD_Val_ro = (uint8_t) ( ((_d[6] & (0x3FU)) << 2U) | ((_d[5] >> 6U) & (0x03U)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMFR_PosnPrsnSeatLSD_Val_phys = (sigfloat_t)(CANDB_SMFR_PosnPrsnSeatLSD_Val_ro_fromS(_m->SMFR_PosnPrsnSeatLSD_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < SMFR_MEM2_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_SMFR_MEM2_candb(&_m->mon1, SMFR_MEM2_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return SMFR_MEM2_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_SMFR_MEM2_candb(SMFR_MEM2_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SMFR_MEM2_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->SMFR_PosnActSeatBRHI_Val_ro = (uint8_t) CANDB_SMFR_PosnActSeatBRHI_Val_ro_toS(_m->SMFR_PosnActSeatBRHI_Val_phys); + _m->SMFR_PosnActSeatHRHI_Val_ro = (uint8_t) CANDB_SMFR_PosnActSeatHRHI_Val_ro_toS(_m->SMFR_PosnActSeatHRHI_Val_phys); + _m->SMFR_PosnActSeatBRI_Val_ro = (uint8_t) CANDB_SMFR_PosnActSeatBRI_Val_ro_toS(_m->SMFR_PosnActSeatBRI_Val_phys); + _m->SMFR_PosnPrsnSeatCS_Val_ro = (uint8_t) CANDB_SMFR_PosnPrsnSeatCS_Val_ro_toS(_m->SMFR_PosnPrsnSeatCS_Val_phys); + _m->SMFR_PosnPrsnSeatLSH_Val_ro = (uint8_t) CANDB_SMFR_PosnPrsnSeatLSH_Val_ro_toS(_m->SMFR_PosnPrsnSeatLSH_Val_phys); + _m->SMFR_PosnPrsnSeatLSD_Val_ro = (uint8_t) CANDB_SMFR_PosnPrsnSeatLSD_Val_ro_toS(_m->SMFR_PosnPrsnSeatLSD_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->SMFR_PosnActSeatBRHI_Val_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->SMFR_PosnActSeatHRHI_Val_ro & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->SMFR_PosnActSeatBRI_Val_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->SMFR_ActHeatBalance_Val & (0x07U)) | ((_m->SMFR_ActVentBalance_Stat & (0x07U)) << 3U) | ((_m->SMFR_PosnPrsnSeatCS_Val_ro & (0x03U)) << 6U) ); + cframe->Data[4] |= (uint8_t) ( ((_m->SMFR_PosnPrsnSeatCS_Val_ro >> 2U) & (0x3FU)) | ((_m->SMFR_PosnPrsnSeatLSH_Val_ro & (0x03U)) << 6U) ); + cframe->Data[5] |= (uint8_t) ( ((_m->SMFR_PosnPrsnSeatLSH_Val_ro >> 2U) & (0x3FU)) | ((_m->SMFR_PosnPrsnSeatLSD_Val_ro & (0x03U)) << 6U) ); + cframe->Data[6] |= (uint8_t) ( ((_m->SMFR_PosnPrsnSeatLSD_Val_ro >> 2U) & (0x3FU)) ); + + cframe->MsgId = (uint32_t) SMFR_MEM2_CANID; + cframe->DLC = (uint8_t) SMFR_MEM2_DLC; + cframe->IDE = (uint8_t) SMFR_MEM2_IDE; + return SMFR_MEM2_CANID; +} + +#else + +uint32_t Pack_SMFR_MEM2_candb(SMFR_MEM2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SMFR_MEM2_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->SMFR_PosnActSeatBRHI_Val_ro = (uint8_t) CANDB_SMFR_PosnActSeatBRHI_Val_ro_toS(_m->SMFR_PosnActSeatBRHI_Val_phys); + _m->SMFR_PosnActSeatHRHI_Val_ro = (uint8_t) CANDB_SMFR_PosnActSeatHRHI_Val_ro_toS(_m->SMFR_PosnActSeatHRHI_Val_phys); + _m->SMFR_PosnActSeatBRI_Val_ro = (uint8_t) CANDB_SMFR_PosnActSeatBRI_Val_ro_toS(_m->SMFR_PosnActSeatBRI_Val_phys); + _m->SMFR_PosnPrsnSeatCS_Val_ro = (uint8_t) CANDB_SMFR_PosnPrsnSeatCS_Val_ro_toS(_m->SMFR_PosnPrsnSeatCS_Val_phys); + _m->SMFR_PosnPrsnSeatLSH_Val_ro = (uint8_t) CANDB_SMFR_PosnPrsnSeatLSH_Val_ro_toS(_m->SMFR_PosnPrsnSeatLSH_Val_phys); + _m->SMFR_PosnPrsnSeatLSD_Val_ro = (uint8_t) CANDB_SMFR_PosnPrsnSeatLSD_Val_ro_toS(_m->SMFR_PosnPrsnSeatLSD_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->SMFR_PosnActSeatBRHI_Val_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( (_m->SMFR_PosnActSeatHRHI_Val_ro & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->SMFR_PosnActSeatBRI_Val_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->SMFR_ActHeatBalance_Val & (0x07U)) | ((_m->SMFR_ActVentBalance_Stat & (0x07U)) << 3U) | ((_m->SMFR_PosnPrsnSeatCS_Val_ro & (0x03U)) << 6U) ); + _d[4] |= (uint8_t) ( ((_m->SMFR_PosnPrsnSeatCS_Val_ro >> 2U) & (0x3FU)) | ((_m->SMFR_PosnPrsnSeatLSH_Val_ro & (0x03U)) << 6U) ); + _d[5] |= (uint8_t) ( ((_m->SMFR_PosnPrsnSeatLSH_Val_ro >> 2U) & (0x3FU)) | ((_m->SMFR_PosnPrsnSeatLSD_Val_ro & (0x03U)) << 6U) ); + _d[6] |= (uint8_t) ( ((_m->SMFR_PosnPrsnSeatLSD_Val_ro >> 2U) & (0x3FU)) ); + + *_len = (uint8_t) SMFR_MEM2_DLC; + *_ide = (uint8_t) SMFR_MEM2_IDE; + return SMFR_MEM2_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_MEM_SMFR2_candb(BCM_MEM_SMFR2_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->BCM_FRMemPosnActSeatBRHI_Val_ro = (uint8_t) ( (_d[0] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_FRMemPosnActSeatBRHI_Val_phys = (sigfloat_t)(CANDB_BCM_FRMemPosnActSeatBRHI_Val_ro_fromS(_m->BCM_FRMemPosnActSeatBRHI_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_FRMemPosnActSeatHRHI_Val_ro = (uint8_t) ( (_d[1] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_FRMemPosnActSeatHRHI_Val_phys = (sigfloat_t)(CANDB_BCM_FRMemPosnActSeatHRHI_Val_ro_fromS(_m->BCM_FRMemPosnActSeatHRHI_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_FRMemPosnActSeatBRI_Val_ro = (uint8_t) ( (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_FRMemPosnActSeatBRI_Val_phys = (sigfloat_t)(CANDB_BCM_FRMemPosnActSeatBRI_Val_ro_fromS(_m->BCM_FRMemPosnActSeatBRI_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_FRMemActHeatBalance_Val = (uint8_t) ( (_d[3] & (0x07U)) ); + _m->BCM_FRMemActVentBalance_Val = (uint8_t) ( ((_d[3] >> 3U) & (0x07U)) ); + _m->BCM_FRMemPosnPrsnSeatCS_Val_ro = (uint8_t) ( ((_d[4] & (0x3FU)) << 2U) | ((_d[3] >> 6U) & (0x03U)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_FRMemPosnPrsnSeatCS_Val_phys = (sigfloat_t)(CANDB_BCM_FRMemPosnPrsnSeatCS_Val_ro_fromS(_m->BCM_FRMemPosnPrsnSeatCS_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_FRMemPosnPrsnSeatLSH_Val_ro = (uint8_t) ( ((_d[5] & (0x3FU)) << 2U) | ((_d[4] >> 6U) & (0x03U)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_FRMemPosnPrsnSeatLSH_Val_phys = (sigfloat_t)(CANDB_BCM_FRMemPosnPrsnSeatLSH_Val_ro_fromS(_m->BCM_FRMemPosnPrsnSeatLSH_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_FRMemPosnPrsnSeatLSD_Val_ro = (uint8_t) ( ((_d[6] & (0x3FU)) << 2U) | ((_d[5] >> 6U) & (0x03U)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_FRMemPosnPrsnSeatLSD_Val_phys = (sigfloat_t)(CANDB_BCM_FRMemPosnPrsnSeatLSD_Val_ro_fromS(_m->BCM_FRMemPosnPrsnSeatLSD_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < BCM_MEM_SMFR2_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_BCM_MEM_SMFR2_candb(&_m->mon1, BCM_MEM_SMFR2_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return BCM_MEM_SMFR2_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_BCM_MEM_SMFR2_candb(BCM_MEM_SMFR2_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_MEM_SMFR2_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_FRMemPosnActSeatBRHI_Val_ro = (uint8_t) CANDB_BCM_FRMemPosnActSeatBRHI_Val_ro_toS(_m->BCM_FRMemPosnActSeatBRHI_Val_phys); + _m->BCM_FRMemPosnActSeatHRHI_Val_ro = (uint8_t) CANDB_BCM_FRMemPosnActSeatHRHI_Val_ro_toS(_m->BCM_FRMemPosnActSeatHRHI_Val_phys); + _m->BCM_FRMemPosnActSeatBRI_Val_ro = (uint8_t) CANDB_BCM_FRMemPosnActSeatBRI_Val_ro_toS(_m->BCM_FRMemPosnActSeatBRI_Val_phys); + _m->BCM_FRMemPosnPrsnSeatCS_Val_ro = (uint8_t) CANDB_BCM_FRMemPosnPrsnSeatCS_Val_ro_toS(_m->BCM_FRMemPosnPrsnSeatCS_Val_phys); + _m->BCM_FRMemPosnPrsnSeatLSH_Val_ro = (uint8_t) CANDB_BCM_FRMemPosnPrsnSeatLSH_Val_ro_toS(_m->BCM_FRMemPosnPrsnSeatLSH_Val_phys); + _m->BCM_FRMemPosnPrsnSeatLSD_Val_ro = (uint8_t) CANDB_BCM_FRMemPosnPrsnSeatLSD_Val_ro_toS(_m->BCM_FRMemPosnPrsnSeatLSD_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->BCM_FRMemPosnActSeatBRHI_Val_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->BCM_FRMemPosnActSeatHRHI_Val_ro & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->BCM_FRMemPosnActSeatBRI_Val_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->BCM_FRMemActHeatBalance_Val & (0x07U)) | ((_m->BCM_FRMemActVentBalance_Val & (0x07U)) << 3U) | ((_m->BCM_FRMemPosnPrsnSeatCS_Val_ro & (0x03U)) << 6U) ); + cframe->Data[4] |= (uint8_t) ( ((_m->BCM_FRMemPosnPrsnSeatCS_Val_ro >> 2U) & (0x3FU)) | ((_m->BCM_FRMemPosnPrsnSeatLSH_Val_ro & (0x03U)) << 6U) ); + cframe->Data[5] |= (uint8_t) ( ((_m->BCM_FRMemPosnPrsnSeatLSH_Val_ro >> 2U) & (0x3FU)) | ((_m->BCM_FRMemPosnPrsnSeatLSD_Val_ro & (0x03U)) << 6U) ); + cframe->Data[6] |= (uint8_t) ( ((_m->BCM_FRMemPosnPrsnSeatLSD_Val_ro >> 2U) & (0x3FU)) ); + + cframe->MsgId = (uint32_t) BCM_MEM_SMFR2_CANID; + cframe->DLC = (uint8_t) BCM_MEM_SMFR2_DLC; + cframe->IDE = (uint8_t) BCM_MEM_SMFR2_IDE; + return BCM_MEM_SMFR2_CANID; +} + +#else + +uint32_t Pack_BCM_MEM_SMFR2_candb(BCM_MEM_SMFR2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_MEM_SMFR2_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_FRMemPosnActSeatBRHI_Val_ro = (uint8_t) CANDB_BCM_FRMemPosnActSeatBRHI_Val_ro_toS(_m->BCM_FRMemPosnActSeatBRHI_Val_phys); + _m->BCM_FRMemPosnActSeatHRHI_Val_ro = (uint8_t) CANDB_BCM_FRMemPosnActSeatHRHI_Val_ro_toS(_m->BCM_FRMemPosnActSeatHRHI_Val_phys); + _m->BCM_FRMemPosnActSeatBRI_Val_ro = (uint8_t) CANDB_BCM_FRMemPosnActSeatBRI_Val_ro_toS(_m->BCM_FRMemPosnActSeatBRI_Val_phys); + _m->BCM_FRMemPosnPrsnSeatCS_Val_ro = (uint8_t) CANDB_BCM_FRMemPosnPrsnSeatCS_Val_ro_toS(_m->BCM_FRMemPosnPrsnSeatCS_Val_phys); + _m->BCM_FRMemPosnPrsnSeatLSH_Val_ro = (uint8_t) CANDB_BCM_FRMemPosnPrsnSeatLSH_Val_ro_toS(_m->BCM_FRMemPosnPrsnSeatLSH_Val_phys); + _m->BCM_FRMemPosnPrsnSeatLSD_Val_ro = (uint8_t) CANDB_BCM_FRMemPosnPrsnSeatLSD_Val_ro_toS(_m->BCM_FRMemPosnPrsnSeatLSD_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->BCM_FRMemPosnActSeatBRHI_Val_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( (_m->BCM_FRMemPosnActSeatHRHI_Val_ro & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->BCM_FRMemPosnActSeatBRI_Val_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->BCM_FRMemActHeatBalance_Val & (0x07U)) | ((_m->BCM_FRMemActVentBalance_Val & (0x07U)) << 3U) | ((_m->BCM_FRMemPosnPrsnSeatCS_Val_ro & (0x03U)) << 6U) ); + _d[4] |= (uint8_t) ( ((_m->BCM_FRMemPosnPrsnSeatCS_Val_ro >> 2U) & (0x3FU)) | ((_m->BCM_FRMemPosnPrsnSeatLSH_Val_ro & (0x03U)) << 6U) ); + _d[5] |= (uint8_t) ( ((_m->BCM_FRMemPosnPrsnSeatLSH_Val_ro >> 2U) & (0x3FU)) | ((_m->BCM_FRMemPosnPrsnSeatLSD_Val_ro & (0x03U)) << 6U) ); + _d[6] |= (uint8_t) ( ((_m->BCM_FRMemPosnPrsnSeatLSD_Val_ro >> 2U) & (0x3FU)) ); + + *_len = (uint8_t) BCM_MEM_SMFR2_DLC; + *_ide = (uint8_t) BCM_MEM_SMFR2_IDE; + return BCM_MEM_SMFR2_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SMRL_MEM1_candb(SMRL_MEM1_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->SMRL_PosnActSeatI_Val_ro = (uint8_t) ( (_d[0] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMRL_PosnActSeatI_Val_phys = (sigfloat_t)(CANDB_SMRL_PosnActSeatI_Val_ro_fromS(_m->SMRL_PosnActSeatI_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMRL_PosnActSeatBRW_Val_ro = (uint8_t) ( (_d[1] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMRL_PosnActSeatBRW_Val_phys = (uint16_t) CANDB_SMRL_PosnActSeatBRW_Val_ro_fromS(_m->SMRL_PosnActSeatBRW_Val_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->SMRL_PosnActSeatFRH_Val_ro = (uint8_t) ( (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMRL_PosnActSeatFRH_Val_phys = (sigfloat_t)(CANDB_SMRL_PosnActSeatFRH_Val_ro_fromS(_m->SMRL_PosnActSeatFRH_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMRL_PosnActSeatFRL_Val_ro = (uint8_t) ( (_d[3] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMRL_PosnActSeatFRL_Val_phys = (sigfloat_t)(CANDB_SMRL_PosnActSeatFRL_Val_ro_fromS(_m->SMRL_PosnActSeatFRL_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMRL_PosnActSeatH_Val_ro = (uint8_t) ( (_d[4] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMRL_PosnActSeatH_Val_phys = (sigfloat_t)(CANDB_SMRL_PosnActSeatH_Val_ro_fromS(_m->SMRL_PosnActSeatH_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMRL_PosnActSeatHRH_Val_ro = (uint8_t) ( (_d[5] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMRL_PosnActSeatHRH_Val_phys = (sigfloat_t)(CANDB_SMRL_PosnActSeatHRH_Val_ro_fromS(_m->SMRL_PosnActSeatHRH_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMRL_PosnActSeatL_Val_ro = (uint8_t) ( (_d[6] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMRL_PosnActSeatL_Val_phys = (sigfloat_t)(CANDB_SMRL_PosnActSeatL_Val_ro_fromS(_m->SMRL_PosnActSeatL_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMRL_PosnActSeatSL_Val_ro = (uint8_t) ( (_d[7] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMRL_PosnActSeatSL_Val_phys = (sigfloat_t)(CANDB_SMRL_PosnActSeatSL_Val_ro_fromS(_m->SMRL_PosnActSeatSL_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < SMRL_MEM1_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_SMRL_MEM1_candb(&_m->mon1, SMRL_MEM1_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return SMRL_MEM1_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_SMRL_MEM1_candb(SMRL_MEM1_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SMRL_MEM1_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->SMRL_PosnActSeatI_Val_ro = (uint8_t) CANDB_SMRL_PosnActSeatI_Val_ro_toS(_m->SMRL_PosnActSeatI_Val_phys); + _m->SMRL_PosnActSeatBRW_Val_ro = (uint8_t) CANDB_SMRL_PosnActSeatBRW_Val_ro_toS(_m->SMRL_PosnActSeatBRW_Val_phys); + _m->SMRL_PosnActSeatFRH_Val_ro = (uint8_t) CANDB_SMRL_PosnActSeatFRH_Val_ro_toS(_m->SMRL_PosnActSeatFRH_Val_phys); + _m->SMRL_PosnActSeatFRL_Val_ro = (uint8_t) CANDB_SMRL_PosnActSeatFRL_Val_ro_toS(_m->SMRL_PosnActSeatFRL_Val_phys); + _m->SMRL_PosnActSeatH_Val_ro = (uint8_t) CANDB_SMRL_PosnActSeatH_Val_ro_toS(_m->SMRL_PosnActSeatH_Val_phys); + _m->SMRL_PosnActSeatHRH_Val_ro = (uint8_t) CANDB_SMRL_PosnActSeatHRH_Val_ro_toS(_m->SMRL_PosnActSeatHRH_Val_phys); + _m->SMRL_PosnActSeatL_Val_ro = (uint8_t) CANDB_SMRL_PosnActSeatL_Val_ro_toS(_m->SMRL_PosnActSeatL_Val_phys); + _m->SMRL_PosnActSeatSL_Val_ro = (uint8_t) CANDB_SMRL_PosnActSeatSL_Val_ro_toS(_m->SMRL_PosnActSeatSL_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->SMRL_PosnActSeatI_Val_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->SMRL_PosnActSeatBRW_Val_ro & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->SMRL_PosnActSeatFRH_Val_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->SMRL_PosnActSeatFRL_Val_ro & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->SMRL_PosnActSeatH_Val_ro & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->SMRL_PosnActSeatHRH_Val_ro & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->SMRL_PosnActSeatL_Val_ro & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->SMRL_PosnActSeatSL_Val_ro & (0xFFU)) ); + + cframe->MsgId = (uint32_t) SMRL_MEM1_CANID; + cframe->DLC = (uint8_t) SMRL_MEM1_DLC; + cframe->IDE = (uint8_t) SMRL_MEM1_IDE; + return SMRL_MEM1_CANID; +} + +#else + +uint32_t Pack_SMRL_MEM1_candb(SMRL_MEM1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SMRL_MEM1_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->SMRL_PosnActSeatI_Val_ro = (uint8_t) CANDB_SMRL_PosnActSeatI_Val_ro_toS(_m->SMRL_PosnActSeatI_Val_phys); + _m->SMRL_PosnActSeatBRW_Val_ro = (uint8_t) CANDB_SMRL_PosnActSeatBRW_Val_ro_toS(_m->SMRL_PosnActSeatBRW_Val_phys); + _m->SMRL_PosnActSeatFRH_Val_ro = (uint8_t) CANDB_SMRL_PosnActSeatFRH_Val_ro_toS(_m->SMRL_PosnActSeatFRH_Val_phys); + _m->SMRL_PosnActSeatFRL_Val_ro = (uint8_t) CANDB_SMRL_PosnActSeatFRL_Val_ro_toS(_m->SMRL_PosnActSeatFRL_Val_phys); + _m->SMRL_PosnActSeatH_Val_ro = (uint8_t) CANDB_SMRL_PosnActSeatH_Val_ro_toS(_m->SMRL_PosnActSeatH_Val_phys); + _m->SMRL_PosnActSeatHRH_Val_ro = (uint8_t) CANDB_SMRL_PosnActSeatHRH_Val_ro_toS(_m->SMRL_PosnActSeatHRH_Val_phys); + _m->SMRL_PosnActSeatL_Val_ro = (uint8_t) CANDB_SMRL_PosnActSeatL_Val_ro_toS(_m->SMRL_PosnActSeatL_Val_phys); + _m->SMRL_PosnActSeatSL_Val_ro = (uint8_t) CANDB_SMRL_PosnActSeatSL_Val_ro_toS(_m->SMRL_PosnActSeatSL_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->SMRL_PosnActSeatI_Val_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( (_m->SMRL_PosnActSeatBRW_Val_ro & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->SMRL_PosnActSeatFRH_Val_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->SMRL_PosnActSeatFRL_Val_ro & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->SMRL_PosnActSeatH_Val_ro & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->SMRL_PosnActSeatHRH_Val_ro & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->SMRL_PosnActSeatL_Val_ro & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->SMRL_PosnActSeatSL_Val_ro & (0xFFU)) ); + + *_len = (uint8_t) SMRL_MEM1_DLC; + *_ide = (uint8_t) SMRL_MEM1_IDE; + return SMRL_MEM1_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_MEM_SMRL1_candb(BCM_MEM_SMRL1_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->BCM_RLMemPosnActSeatI_Val_ro = (uint8_t) ( (_d[0] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_RLMemPosnActSeatI_Val_phys = (sigfloat_t)(CANDB_BCM_RLMemPosnActSeatI_Val_ro_fromS(_m->BCM_RLMemPosnActSeatI_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_RLMemPosnActSeatBRW_Val_ro = (uint8_t) ( (_d[1] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_RLMemPosnActSeatBRW_Val_phys = (uint16_t) CANDB_BCM_RLMemPosnActSeatBRW_Val_ro_fromS(_m->BCM_RLMemPosnActSeatBRW_Val_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_RLMemPosnActSeatFRH_Val_ro = (uint8_t) ( (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_RLMemPosnActSeatFRH_Val_phys = (sigfloat_t)(CANDB_BCM_RLMemPosnActSeatFRH_Val_ro_fromS(_m->BCM_RLMemPosnActSeatFRH_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_RLMemPosnActSeatFRL_Val_ro = (uint8_t) ( (_d[3] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_RLMemPosnActSeatFRL_Val_phys = (sigfloat_t)(CANDB_BCM_RLMemPosnActSeatFRL_Val_ro_fromS(_m->BCM_RLMemPosnActSeatFRL_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_RLMemPosnActSeatH_Val_ro = (uint8_t) ( (_d[4] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_RLMemPosnActSeatH_Val_phys = (sigfloat_t)(CANDB_BCM_RLMemPosnActSeatH_Val_ro_fromS(_m->BCM_RLMemPosnActSeatH_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_RLMemPosnActSeatHRH_Val_ro = (uint8_t) ( (_d[5] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_RLMemPosnActSeatHRH_Val_phys = (sigfloat_t)(CANDB_BCM_RLMemPosnActSeatHRH_Val_ro_fromS(_m->BCM_RLMemPosnActSeatHRH_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_RLMemPosnActSeatL_Val_ro = (uint8_t) ( (_d[6] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_RLMemPosnActSeatL_Val_phys = (sigfloat_t)(CANDB_BCM_RLMemPosnActSeatL_Val_ro_fromS(_m->BCM_RLMemPosnActSeatL_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_RLMemPosnActSeatSL_Val_ro = (uint8_t) ( (_d[7] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_RLMemPosnActSeatSL_Val_phys = (sigfloat_t)(CANDB_BCM_RLMemPosnActSeatSL_Val_ro_fromS(_m->BCM_RLMemPosnActSeatSL_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < BCM_MEM_SMRL1_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_BCM_MEM_SMRL1_candb(&_m->mon1, BCM_MEM_SMRL1_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return BCM_MEM_SMRL1_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_BCM_MEM_SMRL1_candb(BCM_MEM_SMRL1_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_MEM_SMRL1_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_RLMemPosnActSeatI_Val_ro = (uint8_t) CANDB_BCM_RLMemPosnActSeatI_Val_ro_toS(_m->BCM_RLMemPosnActSeatI_Val_phys); + _m->BCM_RLMemPosnActSeatBRW_Val_ro = (uint8_t) CANDB_BCM_RLMemPosnActSeatBRW_Val_ro_toS(_m->BCM_RLMemPosnActSeatBRW_Val_phys); + _m->BCM_RLMemPosnActSeatFRH_Val_ro = (uint8_t) CANDB_BCM_RLMemPosnActSeatFRH_Val_ro_toS(_m->BCM_RLMemPosnActSeatFRH_Val_phys); + _m->BCM_RLMemPosnActSeatFRL_Val_ro = (uint8_t) CANDB_BCM_RLMemPosnActSeatFRL_Val_ro_toS(_m->BCM_RLMemPosnActSeatFRL_Val_phys); + _m->BCM_RLMemPosnActSeatH_Val_ro = (uint8_t) CANDB_BCM_RLMemPosnActSeatH_Val_ro_toS(_m->BCM_RLMemPosnActSeatH_Val_phys); + _m->BCM_RLMemPosnActSeatHRH_Val_ro = (uint8_t) CANDB_BCM_RLMemPosnActSeatHRH_Val_ro_toS(_m->BCM_RLMemPosnActSeatHRH_Val_phys); + _m->BCM_RLMemPosnActSeatL_Val_ro = (uint8_t) CANDB_BCM_RLMemPosnActSeatL_Val_ro_toS(_m->BCM_RLMemPosnActSeatL_Val_phys); + _m->BCM_RLMemPosnActSeatSL_Val_ro = (uint8_t) CANDB_BCM_RLMemPosnActSeatSL_Val_ro_toS(_m->BCM_RLMemPosnActSeatSL_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->BCM_RLMemPosnActSeatI_Val_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->BCM_RLMemPosnActSeatBRW_Val_ro & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->BCM_RLMemPosnActSeatFRH_Val_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->BCM_RLMemPosnActSeatFRL_Val_ro & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->BCM_RLMemPosnActSeatH_Val_ro & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->BCM_RLMemPosnActSeatHRH_Val_ro & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->BCM_RLMemPosnActSeatL_Val_ro & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->BCM_RLMemPosnActSeatSL_Val_ro & (0xFFU)) ); + + cframe->MsgId = (uint32_t) BCM_MEM_SMRL1_CANID; + cframe->DLC = (uint8_t) BCM_MEM_SMRL1_DLC; + cframe->IDE = (uint8_t) BCM_MEM_SMRL1_IDE; + return BCM_MEM_SMRL1_CANID; +} + +#else + +uint32_t Pack_BCM_MEM_SMRL1_candb(BCM_MEM_SMRL1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_MEM_SMRL1_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_RLMemPosnActSeatI_Val_ro = (uint8_t) CANDB_BCM_RLMemPosnActSeatI_Val_ro_toS(_m->BCM_RLMemPosnActSeatI_Val_phys); + _m->BCM_RLMemPosnActSeatBRW_Val_ro = (uint8_t) CANDB_BCM_RLMemPosnActSeatBRW_Val_ro_toS(_m->BCM_RLMemPosnActSeatBRW_Val_phys); + _m->BCM_RLMemPosnActSeatFRH_Val_ro = (uint8_t) CANDB_BCM_RLMemPosnActSeatFRH_Val_ro_toS(_m->BCM_RLMemPosnActSeatFRH_Val_phys); + _m->BCM_RLMemPosnActSeatFRL_Val_ro = (uint8_t) CANDB_BCM_RLMemPosnActSeatFRL_Val_ro_toS(_m->BCM_RLMemPosnActSeatFRL_Val_phys); + _m->BCM_RLMemPosnActSeatH_Val_ro = (uint8_t) CANDB_BCM_RLMemPosnActSeatH_Val_ro_toS(_m->BCM_RLMemPosnActSeatH_Val_phys); + _m->BCM_RLMemPosnActSeatHRH_Val_ro = (uint8_t) CANDB_BCM_RLMemPosnActSeatHRH_Val_ro_toS(_m->BCM_RLMemPosnActSeatHRH_Val_phys); + _m->BCM_RLMemPosnActSeatL_Val_ro = (uint8_t) CANDB_BCM_RLMemPosnActSeatL_Val_ro_toS(_m->BCM_RLMemPosnActSeatL_Val_phys); + _m->BCM_RLMemPosnActSeatSL_Val_ro = (uint8_t) CANDB_BCM_RLMemPosnActSeatSL_Val_ro_toS(_m->BCM_RLMemPosnActSeatSL_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->BCM_RLMemPosnActSeatI_Val_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( (_m->BCM_RLMemPosnActSeatBRW_Val_ro & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->BCM_RLMemPosnActSeatFRH_Val_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->BCM_RLMemPosnActSeatFRL_Val_ro & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->BCM_RLMemPosnActSeatH_Val_ro & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->BCM_RLMemPosnActSeatHRH_Val_ro & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->BCM_RLMemPosnActSeatL_Val_ro & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->BCM_RLMemPosnActSeatSL_Val_ro & (0xFFU)) ); + + *_len = (uint8_t) BCM_MEM_SMRL1_DLC; + *_ide = (uint8_t) BCM_MEM_SMRL1_IDE; + return BCM_MEM_SMRL1_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SMRL_MEM2_candb(SMRL_MEM2_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->SMRL_PosnActSeatBRHI_Val_ro = (uint8_t) ( (_d[0] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMRL_PosnActSeatBRHI_Val_phys = (sigfloat_t)(CANDB_SMRL_PosnActSeatBRHI_Val_ro_fromS(_m->SMRL_PosnActSeatBRHI_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMRL_PosnActSeatHRHI_Val_ro = (uint8_t) ( (_d[1] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMRL_PosnActSeatHRHI_Val_phys = (sigfloat_t)(CANDB_SMRL_PosnActSeatHRHI_Val_ro_fromS(_m->SMRL_PosnActSeatHRHI_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMRL_PosnActSeatBRI_Val_ro = (uint8_t) ( (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMRL_PosnActSeatBRI_Val_phys = (sigfloat_t)(CANDB_SMRL_PosnActSeatBRI_Val_ro_fromS(_m->SMRL_PosnActSeatBRI_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMRL_ActHeatBalance_Stat = (uint8_t) ( (_d[3] & (0x07U)) ); + _m->SMRL_ActVentBalance_Stat = (uint8_t) ( ((_d[3] >> 3U) & (0x07U)) ); + _m->SMRL_PosnPrsnSeatCS_Val_ro = (uint8_t) ( ((_d[4] & (0x3FU)) << 2U) | ((_d[3] >> 6U) & (0x03U)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMRL_PosnPrsnSeatCS_Val_phys = (sigfloat_t)(CANDB_SMRL_PosnPrsnSeatCS_Val_ro_fromS(_m->SMRL_PosnPrsnSeatCS_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMRL_PosnPrsnSeatLSH_Val_ro = (uint8_t) ( ((_d[5] & (0x3FU)) << 2U) | ((_d[4] >> 6U) & (0x03U)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMRL_PosnPrsnSeatLSH_Val_phys = (sigfloat_t)(CANDB_SMRL_PosnPrsnSeatLSH_Val_ro_fromS(_m->SMRL_PosnPrsnSeatLSH_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMRL_PosnPrsnSeatLSD_Val_ro = (uint8_t) ( ((_d[6] & (0x3FU)) << 2U) | ((_d[5] >> 6U) & (0x03U)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMRL_PosnPrsnSeatLSD_Val_phys = (sigfloat_t)(CANDB_SMRL_PosnPrsnSeatLSD_Val_ro_fromS(_m->SMRL_PosnPrsnSeatLSD_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < SMRL_MEM2_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_SMRL_MEM2_candb(&_m->mon1, SMRL_MEM2_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return SMRL_MEM2_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_SMRL_MEM2_candb(SMRL_MEM2_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SMRL_MEM2_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->SMRL_PosnActSeatBRHI_Val_ro = (uint8_t) CANDB_SMRL_PosnActSeatBRHI_Val_ro_toS(_m->SMRL_PosnActSeatBRHI_Val_phys); + _m->SMRL_PosnActSeatHRHI_Val_ro = (uint8_t) CANDB_SMRL_PosnActSeatHRHI_Val_ro_toS(_m->SMRL_PosnActSeatHRHI_Val_phys); + _m->SMRL_PosnActSeatBRI_Val_ro = (uint8_t) CANDB_SMRL_PosnActSeatBRI_Val_ro_toS(_m->SMRL_PosnActSeatBRI_Val_phys); + _m->SMRL_PosnPrsnSeatCS_Val_ro = (uint8_t) CANDB_SMRL_PosnPrsnSeatCS_Val_ro_toS(_m->SMRL_PosnPrsnSeatCS_Val_phys); + _m->SMRL_PosnPrsnSeatLSH_Val_ro = (uint8_t) CANDB_SMRL_PosnPrsnSeatLSH_Val_ro_toS(_m->SMRL_PosnPrsnSeatLSH_Val_phys); + _m->SMRL_PosnPrsnSeatLSD_Val_ro = (uint8_t) CANDB_SMRL_PosnPrsnSeatLSD_Val_ro_toS(_m->SMRL_PosnPrsnSeatLSD_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->SMRL_PosnActSeatBRHI_Val_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->SMRL_PosnActSeatHRHI_Val_ro & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->SMRL_PosnActSeatBRI_Val_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->SMRL_ActHeatBalance_Stat & (0x07U)) | ((_m->SMRL_ActVentBalance_Stat & (0x07U)) << 3U) | ((_m->SMRL_PosnPrsnSeatCS_Val_ro & (0x03U)) << 6U) ); + cframe->Data[4] |= (uint8_t) ( ((_m->SMRL_PosnPrsnSeatCS_Val_ro >> 2U) & (0x3FU)) | ((_m->SMRL_PosnPrsnSeatLSH_Val_ro & (0x03U)) << 6U) ); + cframe->Data[5] |= (uint8_t) ( ((_m->SMRL_PosnPrsnSeatLSH_Val_ro >> 2U) & (0x3FU)) | ((_m->SMRL_PosnPrsnSeatLSD_Val_ro & (0x03U)) << 6U) ); + cframe->Data[6] |= (uint8_t) ( ((_m->SMRL_PosnPrsnSeatLSD_Val_ro >> 2U) & (0x3FU)) ); + + cframe->MsgId = (uint32_t) SMRL_MEM2_CANID; + cframe->DLC = (uint8_t) SMRL_MEM2_DLC; + cframe->IDE = (uint8_t) SMRL_MEM2_IDE; + return SMRL_MEM2_CANID; +} + +#else + +uint32_t Pack_SMRL_MEM2_candb(SMRL_MEM2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SMRL_MEM2_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->SMRL_PosnActSeatBRHI_Val_ro = (uint8_t) CANDB_SMRL_PosnActSeatBRHI_Val_ro_toS(_m->SMRL_PosnActSeatBRHI_Val_phys); + _m->SMRL_PosnActSeatHRHI_Val_ro = (uint8_t) CANDB_SMRL_PosnActSeatHRHI_Val_ro_toS(_m->SMRL_PosnActSeatHRHI_Val_phys); + _m->SMRL_PosnActSeatBRI_Val_ro = (uint8_t) CANDB_SMRL_PosnActSeatBRI_Val_ro_toS(_m->SMRL_PosnActSeatBRI_Val_phys); + _m->SMRL_PosnPrsnSeatCS_Val_ro = (uint8_t) CANDB_SMRL_PosnPrsnSeatCS_Val_ro_toS(_m->SMRL_PosnPrsnSeatCS_Val_phys); + _m->SMRL_PosnPrsnSeatLSH_Val_ro = (uint8_t) CANDB_SMRL_PosnPrsnSeatLSH_Val_ro_toS(_m->SMRL_PosnPrsnSeatLSH_Val_phys); + _m->SMRL_PosnPrsnSeatLSD_Val_ro = (uint8_t) CANDB_SMRL_PosnPrsnSeatLSD_Val_ro_toS(_m->SMRL_PosnPrsnSeatLSD_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->SMRL_PosnActSeatBRHI_Val_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( (_m->SMRL_PosnActSeatHRHI_Val_ro & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->SMRL_PosnActSeatBRI_Val_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->SMRL_ActHeatBalance_Stat & (0x07U)) | ((_m->SMRL_ActVentBalance_Stat & (0x07U)) << 3U) | ((_m->SMRL_PosnPrsnSeatCS_Val_ro & (0x03U)) << 6U) ); + _d[4] |= (uint8_t) ( ((_m->SMRL_PosnPrsnSeatCS_Val_ro >> 2U) & (0x3FU)) | ((_m->SMRL_PosnPrsnSeatLSH_Val_ro & (0x03U)) << 6U) ); + _d[5] |= (uint8_t) ( ((_m->SMRL_PosnPrsnSeatLSH_Val_ro >> 2U) & (0x3FU)) | ((_m->SMRL_PosnPrsnSeatLSD_Val_ro & (0x03U)) << 6U) ); + _d[6] |= (uint8_t) ( ((_m->SMRL_PosnPrsnSeatLSD_Val_ro >> 2U) & (0x3FU)) ); + + *_len = (uint8_t) SMRL_MEM2_DLC; + *_ide = (uint8_t) SMRL_MEM2_IDE; + return SMRL_MEM2_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_MEM_SMRL2_candb(BCM_MEM_SMRL2_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->BCM_RLMemPosnActSeatBRHI_Val_ro = (uint8_t) ( (_d[0] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_RLMemPosnActSeatBRHI_Val_phys = (sigfloat_t)(CANDB_BCM_RLMemPosnActSeatBRHI_Val_ro_fromS(_m->BCM_RLMemPosnActSeatBRHI_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_RLMemPosnActSeatHRHI_Val_ro = (uint8_t) ( (_d[1] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_RLMemPosnActSeatHRHI_Val_phys = (sigfloat_t)(CANDB_BCM_RLMemPosnActSeatHRHI_Val_ro_fromS(_m->BCM_RLMemPosnActSeatHRHI_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_RLMemPosnActSeatBRI_Val_ro = (uint8_t) ( (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_RLMemPosnActSeatBRI_Val_phys = (sigfloat_t)(CANDB_BCM_RLMemPosnActSeatBRI_Val_ro_fromS(_m->BCM_RLMemPosnActSeatBRI_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_RLMemActHeatBalance_Val = (uint8_t) ( (_d[3] & (0x07U)) ); + _m->BCM_RLMemActVentBalance_Val = (uint8_t) ( ((_d[3] >> 3U) & (0x07U)) ); + _m->BCM_RLMemPosnPrsnSeatCS_Val_ro = (uint8_t) ( ((_d[4] & (0x3FU)) << 2U) | ((_d[3] >> 6U) & (0x03U)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_RLMemPosnPrsnSeatCS_Val_phys = (sigfloat_t)(CANDB_BCM_RLMemPosnPrsnSeatCS_Val_ro_fromS(_m->BCM_RLMemPosnPrsnSeatCS_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_RLMemPosnPrsnSeatLSH_Val_ro = (uint8_t) ( ((_d[5] & (0x3FU)) << 2U) | ((_d[4] >> 6U) & (0x03U)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_RLMemPosnPrsnSeatLSH_Val_phys = (sigfloat_t)(CANDB_BCM_RLMemPosnPrsnSeatLSH_Val_ro_fromS(_m->BCM_RLMemPosnPrsnSeatLSH_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_RLMemPosnPrsnSeatLSD_Val_ro = (uint8_t) ( ((_d[6] & (0x3FU)) << 2U) | ((_d[5] >> 6U) & (0x03U)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_RLMemPosnPrsnSeatLSD_Val_phys = (sigfloat_t)(CANDB_BCM_RLMemPosnPrsnSeatLSD_Val_ro_fromS(_m->BCM_RLMemPosnPrsnSeatLSD_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < BCM_MEM_SMRL2_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_BCM_MEM_SMRL2_candb(&_m->mon1, BCM_MEM_SMRL2_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return BCM_MEM_SMRL2_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_BCM_MEM_SMRL2_candb(BCM_MEM_SMRL2_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_MEM_SMRL2_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_RLMemPosnActSeatBRHI_Val_ro = (uint8_t) CANDB_BCM_RLMemPosnActSeatBRHI_Val_ro_toS(_m->BCM_RLMemPosnActSeatBRHI_Val_phys); + _m->BCM_RLMemPosnActSeatHRHI_Val_ro = (uint8_t) CANDB_BCM_RLMemPosnActSeatHRHI_Val_ro_toS(_m->BCM_RLMemPosnActSeatHRHI_Val_phys); + _m->BCM_RLMemPosnActSeatBRI_Val_ro = (uint8_t) CANDB_BCM_RLMemPosnActSeatBRI_Val_ro_toS(_m->BCM_RLMemPosnActSeatBRI_Val_phys); + _m->BCM_RLMemPosnPrsnSeatCS_Val_ro = (uint8_t) CANDB_BCM_RLMemPosnPrsnSeatCS_Val_ro_toS(_m->BCM_RLMemPosnPrsnSeatCS_Val_phys); + _m->BCM_RLMemPosnPrsnSeatLSH_Val_ro = (uint8_t) CANDB_BCM_RLMemPosnPrsnSeatLSH_Val_ro_toS(_m->BCM_RLMemPosnPrsnSeatLSH_Val_phys); + _m->BCM_RLMemPosnPrsnSeatLSD_Val_ro = (uint8_t) CANDB_BCM_RLMemPosnPrsnSeatLSD_Val_ro_toS(_m->BCM_RLMemPosnPrsnSeatLSD_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->BCM_RLMemPosnActSeatBRHI_Val_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->BCM_RLMemPosnActSeatHRHI_Val_ro & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->BCM_RLMemPosnActSeatBRI_Val_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->BCM_RLMemActHeatBalance_Val & (0x07U)) | ((_m->BCM_RLMemActVentBalance_Val & (0x07U)) << 3U) | ((_m->BCM_RLMemPosnPrsnSeatCS_Val_ro & (0x03U)) << 6U) ); + cframe->Data[4] |= (uint8_t) ( ((_m->BCM_RLMemPosnPrsnSeatCS_Val_ro >> 2U) & (0x3FU)) | ((_m->BCM_RLMemPosnPrsnSeatLSH_Val_ro & (0x03U)) << 6U) ); + cframe->Data[5] |= (uint8_t) ( ((_m->BCM_RLMemPosnPrsnSeatLSH_Val_ro >> 2U) & (0x3FU)) | ((_m->BCM_RLMemPosnPrsnSeatLSD_Val_ro & (0x03U)) << 6U) ); + cframe->Data[6] |= (uint8_t) ( ((_m->BCM_RLMemPosnPrsnSeatLSD_Val_ro >> 2U) & (0x3FU)) ); + + cframe->MsgId = (uint32_t) BCM_MEM_SMRL2_CANID; + cframe->DLC = (uint8_t) BCM_MEM_SMRL2_DLC; + cframe->IDE = (uint8_t) BCM_MEM_SMRL2_IDE; + return BCM_MEM_SMRL2_CANID; +} + +#else + +uint32_t Pack_BCM_MEM_SMRL2_candb(BCM_MEM_SMRL2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_MEM_SMRL2_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_RLMemPosnActSeatBRHI_Val_ro = (uint8_t) CANDB_BCM_RLMemPosnActSeatBRHI_Val_ro_toS(_m->BCM_RLMemPosnActSeatBRHI_Val_phys); + _m->BCM_RLMemPosnActSeatHRHI_Val_ro = (uint8_t) CANDB_BCM_RLMemPosnActSeatHRHI_Val_ro_toS(_m->BCM_RLMemPosnActSeatHRHI_Val_phys); + _m->BCM_RLMemPosnActSeatBRI_Val_ro = (uint8_t) CANDB_BCM_RLMemPosnActSeatBRI_Val_ro_toS(_m->BCM_RLMemPosnActSeatBRI_Val_phys); + _m->BCM_RLMemPosnPrsnSeatCS_Val_ro = (uint8_t) CANDB_BCM_RLMemPosnPrsnSeatCS_Val_ro_toS(_m->BCM_RLMemPosnPrsnSeatCS_Val_phys); + _m->BCM_RLMemPosnPrsnSeatLSH_Val_ro = (uint8_t) CANDB_BCM_RLMemPosnPrsnSeatLSH_Val_ro_toS(_m->BCM_RLMemPosnPrsnSeatLSH_Val_phys); + _m->BCM_RLMemPosnPrsnSeatLSD_Val_ro = (uint8_t) CANDB_BCM_RLMemPosnPrsnSeatLSD_Val_ro_toS(_m->BCM_RLMemPosnPrsnSeatLSD_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->BCM_RLMemPosnActSeatBRHI_Val_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( (_m->BCM_RLMemPosnActSeatHRHI_Val_ro & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->BCM_RLMemPosnActSeatBRI_Val_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->BCM_RLMemActHeatBalance_Val & (0x07U)) | ((_m->BCM_RLMemActVentBalance_Val & (0x07U)) << 3U) | ((_m->BCM_RLMemPosnPrsnSeatCS_Val_ro & (0x03U)) << 6U) ); + _d[4] |= (uint8_t) ( ((_m->BCM_RLMemPosnPrsnSeatCS_Val_ro >> 2U) & (0x3FU)) | ((_m->BCM_RLMemPosnPrsnSeatLSH_Val_ro & (0x03U)) << 6U) ); + _d[5] |= (uint8_t) ( ((_m->BCM_RLMemPosnPrsnSeatLSH_Val_ro >> 2U) & (0x3FU)) | ((_m->BCM_RLMemPosnPrsnSeatLSD_Val_ro & (0x03U)) << 6U) ); + _d[6] |= (uint8_t) ( ((_m->BCM_RLMemPosnPrsnSeatLSD_Val_ro >> 2U) & (0x3FU)) ); + + *_len = (uint8_t) BCM_MEM_SMRL2_DLC; + *_ide = (uint8_t) BCM_MEM_SMRL2_IDE; + return BCM_MEM_SMRL2_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SMRR_MEM1_candb(SMRR_MEM1_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->SMRR_PosnActSeatI_Val_ro = (uint8_t) ( (_d[0] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMRR_PosnActSeatI_Val_phys = (sigfloat_t)(CANDB_SMRR_PosnActSeatI_Val_ro_fromS(_m->SMRR_PosnActSeatI_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMRR_PosnActSeatBRW_Val_ro = (uint8_t) ( (_d[1] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMRR_PosnActSeatBRW_Val_phys = (uint16_t) CANDB_SMRR_PosnActSeatBRW_Val_ro_fromS(_m->SMRR_PosnActSeatBRW_Val_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->SMRR_PosnActSeatFRH_Val_ro = (uint8_t) ( (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMRR_PosnActSeatFRH_Val_phys = (sigfloat_t)(CANDB_SMRR_PosnActSeatFRH_Val_ro_fromS(_m->SMRR_PosnActSeatFRH_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMRR_PosnActSeatFRL_Val_ro = (uint8_t) ( (_d[3] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMRR_PosnActSeatFRL_Val_phys = (sigfloat_t)(CANDB_SMRR_PosnActSeatFRL_Val_ro_fromS(_m->SMRR_PosnActSeatFRL_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMRR_PosnActSeatH_Val_ro = (uint8_t) ( (_d[4] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMRR_PosnActSeatH_Val_phys = (sigfloat_t)(CANDB_SMRR_PosnActSeatH_Val_ro_fromS(_m->SMRR_PosnActSeatH_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMRR_PosnActSeatHRH_Val_ro = (uint8_t) ( (_d[5] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMRR_PosnActSeatHRH_Val_phys = (sigfloat_t)(CANDB_SMRR_PosnActSeatHRH_Val_ro_fromS(_m->SMRR_PosnActSeatHRH_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMRR_PosnActSeatL_Val_ro = (uint8_t) ( (_d[6] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMRR_PosnActSeatL_Val_phys = (sigfloat_t)(CANDB_SMRR_PosnActSeatL_Val_ro_fromS(_m->SMRR_PosnActSeatL_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMRR_PosnActSeatSL_Val_ro = (uint8_t) ( (_d[7] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMRR_PosnActSeatSL_Val_phys = (sigfloat_t)(CANDB_SMRR_PosnActSeatSL_Val_ro_fromS(_m->SMRR_PosnActSeatSL_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < SMRR_MEM1_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_SMRR_MEM1_candb(&_m->mon1, SMRR_MEM1_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return SMRR_MEM1_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_SMRR_MEM1_candb(SMRR_MEM1_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SMRR_MEM1_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->SMRR_PosnActSeatI_Val_ro = (uint8_t) CANDB_SMRR_PosnActSeatI_Val_ro_toS(_m->SMRR_PosnActSeatI_Val_phys); + _m->SMRR_PosnActSeatBRW_Val_ro = (uint8_t) CANDB_SMRR_PosnActSeatBRW_Val_ro_toS(_m->SMRR_PosnActSeatBRW_Val_phys); + _m->SMRR_PosnActSeatFRH_Val_ro = (uint8_t) CANDB_SMRR_PosnActSeatFRH_Val_ro_toS(_m->SMRR_PosnActSeatFRH_Val_phys); + _m->SMRR_PosnActSeatFRL_Val_ro = (uint8_t) CANDB_SMRR_PosnActSeatFRL_Val_ro_toS(_m->SMRR_PosnActSeatFRL_Val_phys); + _m->SMRR_PosnActSeatH_Val_ro = (uint8_t) CANDB_SMRR_PosnActSeatH_Val_ro_toS(_m->SMRR_PosnActSeatH_Val_phys); + _m->SMRR_PosnActSeatHRH_Val_ro = (uint8_t) CANDB_SMRR_PosnActSeatHRH_Val_ro_toS(_m->SMRR_PosnActSeatHRH_Val_phys); + _m->SMRR_PosnActSeatL_Val_ro = (uint8_t) CANDB_SMRR_PosnActSeatL_Val_ro_toS(_m->SMRR_PosnActSeatL_Val_phys); + _m->SMRR_PosnActSeatSL_Val_ro = (uint8_t) CANDB_SMRR_PosnActSeatSL_Val_ro_toS(_m->SMRR_PosnActSeatSL_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->SMRR_PosnActSeatI_Val_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->SMRR_PosnActSeatBRW_Val_ro & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->SMRR_PosnActSeatFRH_Val_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->SMRR_PosnActSeatFRL_Val_ro & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->SMRR_PosnActSeatH_Val_ro & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->SMRR_PosnActSeatHRH_Val_ro & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->SMRR_PosnActSeatL_Val_ro & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->SMRR_PosnActSeatSL_Val_ro & (0xFFU)) ); + + cframe->MsgId = (uint32_t) SMRR_MEM1_CANID; + cframe->DLC = (uint8_t) SMRR_MEM1_DLC; + cframe->IDE = (uint8_t) SMRR_MEM1_IDE; + return SMRR_MEM1_CANID; +} + +#else + +uint32_t Pack_SMRR_MEM1_candb(SMRR_MEM1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SMRR_MEM1_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->SMRR_PosnActSeatI_Val_ro = (uint8_t) CANDB_SMRR_PosnActSeatI_Val_ro_toS(_m->SMRR_PosnActSeatI_Val_phys); + _m->SMRR_PosnActSeatBRW_Val_ro = (uint8_t) CANDB_SMRR_PosnActSeatBRW_Val_ro_toS(_m->SMRR_PosnActSeatBRW_Val_phys); + _m->SMRR_PosnActSeatFRH_Val_ro = (uint8_t) CANDB_SMRR_PosnActSeatFRH_Val_ro_toS(_m->SMRR_PosnActSeatFRH_Val_phys); + _m->SMRR_PosnActSeatFRL_Val_ro = (uint8_t) CANDB_SMRR_PosnActSeatFRL_Val_ro_toS(_m->SMRR_PosnActSeatFRL_Val_phys); + _m->SMRR_PosnActSeatH_Val_ro = (uint8_t) CANDB_SMRR_PosnActSeatH_Val_ro_toS(_m->SMRR_PosnActSeatH_Val_phys); + _m->SMRR_PosnActSeatHRH_Val_ro = (uint8_t) CANDB_SMRR_PosnActSeatHRH_Val_ro_toS(_m->SMRR_PosnActSeatHRH_Val_phys); + _m->SMRR_PosnActSeatL_Val_ro = (uint8_t) CANDB_SMRR_PosnActSeatL_Val_ro_toS(_m->SMRR_PosnActSeatL_Val_phys); + _m->SMRR_PosnActSeatSL_Val_ro = (uint8_t) CANDB_SMRR_PosnActSeatSL_Val_ro_toS(_m->SMRR_PosnActSeatSL_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->SMRR_PosnActSeatI_Val_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( (_m->SMRR_PosnActSeatBRW_Val_ro & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->SMRR_PosnActSeatFRH_Val_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->SMRR_PosnActSeatFRL_Val_ro & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->SMRR_PosnActSeatH_Val_ro & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->SMRR_PosnActSeatHRH_Val_ro & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->SMRR_PosnActSeatL_Val_ro & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->SMRR_PosnActSeatSL_Val_ro & (0xFFU)) ); + + *_len = (uint8_t) SMRR_MEM1_DLC; + *_ide = (uint8_t) SMRR_MEM1_IDE; + return SMRR_MEM1_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_MEM_SMRR1_candb(BCM_MEM_SMRR1_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->BCM_RRMemPosnActSeatI_Val_ro = (uint8_t) ( (_d[0] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_RRMemPosnActSeatI_Val_phys = (sigfloat_t)(CANDB_BCM_RRMemPosnActSeatI_Val_ro_fromS(_m->BCM_RRMemPosnActSeatI_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_RRMemPosnActSeatBRW_Val_ro = (uint8_t) ( (_d[1] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_RRMemPosnActSeatBRW_Val_phys = (uint16_t) CANDB_BCM_RRMemPosnActSeatBRW_Val_ro_fromS(_m->BCM_RRMemPosnActSeatBRW_Val_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_RRMemPosnActSeatFRH_Val_ro = (uint8_t) ( (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_RRMemPosnActSeatFRH_Val_phys = (sigfloat_t)(CANDB_BCM_RRMemPosnActSeatFRH_Val_ro_fromS(_m->BCM_RRMemPosnActSeatFRH_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_RRMemPosnActSeatFRL_Val_ro = (uint8_t) ( (_d[3] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_RRMemPosnActSeatFRL_Val_phys = (sigfloat_t)(CANDB_BCM_RRMemPosnActSeatFRL_Val_ro_fromS(_m->BCM_RRMemPosnActSeatFRL_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_RRMemPosnActSeatH_Val_ro = (uint8_t) ( (_d[4] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_RRMemPosnActSeatH_Val_phys = (sigfloat_t)(CANDB_BCM_RRMemPosnActSeatH_Val_ro_fromS(_m->BCM_RRMemPosnActSeatH_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_RRMemPosnActSeatHRH_Val_ro = (uint8_t) ( (_d[5] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_RRMemPosnActSeatHRH_Val_phys = (sigfloat_t)(CANDB_BCM_RRMemPosnActSeatHRH_Val_ro_fromS(_m->BCM_RRMemPosnActSeatHRH_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_RRMemPosnActSeatL_Val_ro = (uint8_t) ( (_d[6] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_RRMemPosnActSeatL_Val_phys = (sigfloat_t)(CANDB_BCM_RRMemPosnActSeatL_Val_ro_fromS(_m->BCM_RRMemPosnActSeatL_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_RRMemPosnActSeatSL_Val_ro = (uint8_t) ( (_d[7] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_RRMemPosnActSeatSL_Val_phys = (sigfloat_t)(CANDB_BCM_RRMemPosnActSeatSL_Val_ro_fromS(_m->BCM_RRMemPosnActSeatSL_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < BCM_MEM_SMRR1_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_BCM_MEM_SMRR1_candb(&_m->mon1, BCM_MEM_SMRR1_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return BCM_MEM_SMRR1_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_BCM_MEM_SMRR1_candb(BCM_MEM_SMRR1_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_MEM_SMRR1_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_RRMemPosnActSeatI_Val_ro = (uint8_t) CANDB_BCM_RRMemPosnActSeatI_Val_ro_toS(_m->BCM_RRMemPosnActSeatI_Val_phys); + _m->BCM_RRMemPosnActSeatBRW_Val_ro = (uint8_t) CANDB_BCM_RRMemPosnActSeatBRW_Val_ro_toS(_m->BCM_RRMemPosnActSeatBRW_Val_phys); + _m->BCM_RRMemPosnActSeatFRH_Val_ro = (uint8_t) CANDB_BCM_RRMemPosnActSeatFRH_Val_ro_toS(_m->BCM_RRMemPosnActSeatFRH_Val_phys); + _m->BCM_RRMemPosnActSeatFRL_Val_ro = (uint8_t) CANDB_BCM_RRMemPosnActSeatFRL_Val_ro_toS(_m->BCM_RRMemPosnActSeatFRL_Val_phys); + _m->BCM_RRMemPosnActSeatH_Val_ro = (uint8_t) CANDB_BCM_RRMemPosnActSeatH_Val_ro_toS(_m->BCM_RRMemPosnActSeatH_Val_phys); + _m->BCM_RRMemPosnActSeatHRH_Val_ro = (uint8_t) CANDB_BCM_RRMemPosnActSeatHRH_Val_ro_toS(_m->BCM_RRMemPosnActSeatHRH_Val_phys); + _m->BCM_RRMemPosnActSeatL_Val_ro = (uint8_t) CANDB_BCM_RRMemPosnActSeatL_Val_ro_toS(_m->BCM_RRMemPosnActSeatL_Val_phys); + _m->BCM_RRMemPosnActSeatSL_Val_ro = (uint8_t) CANDB_BCM_RRMemPosnActSeatSL_Val_ro_toS(_m->BCM_RRMemPosnActSeatSL_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->BCM_RRMemPosnActSeatI_Val_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->BCM_RRMemPosnActSeatBRW_Val_ro & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->BCM_RRMemPosnActSeatFRH_Val_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->BCM_RRMemPosnActSeatFRL_Val_ro & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->BCM_RRMemPosnActSeatH_Val_ro & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->BCM_RRMemPosnActSeatHRH_Val_ro & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->BCM_RRMemPosnActSeatL_Val_ro & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->BCM_RRMemPosnActSeatSL_Val_ro & (0xFFU)) ); + + cframe->MsgId = (uint32_t) BCM_MEM_SMRR1_CANID; + cframe->DLC = (uint8_t) BCM_MEM_SMRR1_DLC; + cframe->IDE = (uint8_t) BCM_MEM_SMRR1_IDE; + return BCM_MEM_SMRR1_CANID; +} + +#else + +uint32_t Pack_BCM_MEM_SMRR1_candb(BCM_MEM_SMRR1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_MEM_SMRR1_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_RRMemPosnActSeatI_Val_ro = (uint8_t) CANDB_BCM_RRMemPosnActSeatI_Val_ro_toS(_m->BCM_RRMemPosnActSeatI_Val_phys); + _m->BCM_RRMemPosnActSeatBRW_Val_ro = (uint8_t) CANDB_BCM_RRMemPosnActSeatBRW_Val_ro_toS(_m->BCM_RRMemPosnActSeatBRW_Val_phys); + _m->BCM_RRMemPosnActSeatFRH_Val_ro = (uint8_t) CANDB_BCM_RRMemPosnActSeatFRH_Val_ro_toS(_m->BCM_RRMemPosnActSeatFRH_Val_phys); + _m->BCM_RRMemPosnActSeatFRL_Val_ro = (uint8_t) CANDB_BCM_RRMemPosnActSeatFRL_Val_ro_toS(_m->BCM_RRMemPosnActSeatFRL_Val_phys); + _m->BCM_RRMemPosnActSeatH_Val_ro = (uint8_t) CANDB_BCM_RRMemPosnActSeatH_Val_ro_toS(_m->BCM_RRMemPosnActSeatH_Val_phys); + _m->BCM_RRMemPosnActSeatHRH_Val_ro = (uint8_t) CANDB_BCM_RRMemPosnActSeatHRH_Val_ro_toS(_m->BCM_RRMemPosnActSeatHRH_Val_phys); + _m->BCM_RRMemPosnActSeatL_Val_ro = (uint8_t) CANDB_BCM_RRMemPosnActSeatL_Val_ro_toS(_m->BCM_RRMemPosnActSeatL_Val_phys); + _m->BCM_RRMemPosnActSeatSL_Val_ro = (uint8_t) CANDB_BCM_RRMemPosnActSeatSL_Val_ro_toS(_m->BCM_RRMemPosnActSeatSL_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->BCM_RRMemPosnActSeatI_Val_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( (_m->BCM_RRMemPosnActSeatBRW_Val_ro & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->BCM_RRMemPosnActSeatFRH_Val_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->BCM_RRMemPosnActSeatFRL_Val_ro & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->BCM_RRMemPosnActSeatH_Val_ro & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->BCM_RRMemPosnActSeatHRH_Val_ro & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->BCM_RRMemPosnActSeatL_Val_ro & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->BCM_RRMemPosnActSeatSL_Val_ro & (0xFFU)) ); + + *_len = (uint8_t) BCM_MEM_SMRR1_DLC; + *_ide = (uint8_t) BCM_MEM_SMRR1_IDE; + return BCM_MEM_SMRR1_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SMRR_MEM2_candb(SMRR_MEM2_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->SMRR_PosnActSeatBRHI_Val_ro = (uint8_t) ( (_d[0] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMRR_PosnActSeatBRHI_Val_phys = (sigfloat_t)(CANDB_SMRR_PosnActSeatBRHI_Val_ro_fromS(_m->SMRR_PosnActSeatBRHI_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMRR_PosnActSeatHRHI_Val_ro = (uint8_t) ( (_d[1] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMRR_PosnActSeatHRHI_Val_phys = (sigfloat_t)(CANDB_SMRR_PosnActSeatHRHI_Val_ro_fromS(_m->SMRR_PosnActSeatHRHI_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMRR_PosnActSeatBRI_Val_ro = (uint8_t) ( (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMRR_PosnActSeatBRI_Val_phys = (sigfloat_t)(CANDB_SMRR_PosnActSeatBRI_Val_ro_fromS(_m->SMRR_PosnActSeatBRI_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMRR_ActHeatBalance_Stat = (uint8_t) ( (_d[3] & (0x07U)) ); + _m->SMRR_ActVentBalance_Stat = (uint8_t) ( ((_d[3] >> 3U) & (0x07U)) ); + _m->SMRR_PosnPrsnSeatCS_Val_ro = (uint8_t) ( ((_d[4] & (0x3FU)) << 2U) | ((_d[3] >> 6U) & (0x03U)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMRR_PosnPrsnSeatCS_Val_phys = (sigfloat_t)(CANDB_SMRR_PosnPrsnSeatCS_Val_ro_fromS(_m->SMRR_PosnPrsnSeatCS_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMRR_PosnPrsnSeatLSH_Val_ro = (uint8_t) ( ((_d[5] & (0x3FU)) << 2U) | ((_d[4] >> 6U) & (0x03U)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMRR_PosnPrsnSeatLSH_Val_phys = (sigfloat_t)(CANDB_SMRR_PosnPrsnSeatLSH_Val_ro_fromS(_m->SMRR_PosnPrsnSeatLSH_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->SMRR_PosnPrsnSeatLSD_Val_ro = (uint8_t) ( ((_d[6] & (0x3FU)) << 2U) | ((_d[5] >> 6U) & (0x03U)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->SMRR_PosnPrsnSeatLSD_Val_phys = (sigfloat_t)(CANDB_SMRR_PosnPrsnSeatLSD_Val_ro_fromS(_m->SMRR_PosnPrsnSeatLSD_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < SMRR_MEM2_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_SMRR_MEM2_candb(&_m->mon1, SMRR_MEM2_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return SMRR_MEM2_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_SMRR_MEM2_candb(SMRR_MEM2_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SMRR_MEM2_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->SMRR_PosnActSeatBRHI_Val_ro = (uint8_t) CANDB_SMRR_PosnActSeatBRHI_Val_ro_toS(_m->SMRR_PosnActSeatBRHI_Val_phys); + _m->SMRR_PosnActSeatHRHI_Val_ro = (uint8_t) CANDB_SMRR_PosnActSeatHRHI_Val_ro_toS(_m->SMRR_PosnActSeatHRHI_Val_phys); + _m->SMRR_PosnActSeatBRI_Val_ro = (uint8_t) CANDB_SMRR_PosnActSeatBRI_Val_ro_toS(_m->SMRR_PosnActSeatBRI_Val_phys); + _m->SMRR_PosnPrsnSeatCS_Val_ro = (uint8_t) CANDB_SMRR_PosnPrsnSeatCS_Val_ro_toS(_m->SMRR_PosnPrsnSeatCS_Val_phys); + _m->SMRR_PosnPrsnSeatLSH_Val_ro = (uint8_t) CANDB_SMRR_PosnPrsnSeatLSH_Val_ro_toS(_m->SMRR_PosnPrsnSeatLSH_Val_phys); + _m->SMRR_PosnPrsnSeatLSD_Val_ro = (uint8_t) CANDB_SMRR_PosnPrsnSeatLSD_Val_ro_toS(_m->SMRR_PosnPrsnSeatLSD_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->SMRR_PosnActSeatBRHI_Val_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->SMRR_PosnActSeatHRHI_Val_ro & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->SMRR_PosnActSeatBRI_Val_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->SMRR_ActHeatBalance_Stat & (0x07U)) | ((_m->SMRR_ActVentBalance_Stat & (0x07U)) << 3U) | ((_m->SMRR_PosnPrsnSeatCS_Val_ro & (0x03U)) << 6U) ); + cframe->Data[4] |= (uint8_t) ( ((_m->SMRR_PosnPrsnSeatCS_Val_ro >> 2U) & (0x3FU)) | ((_m->SMRR_PosnPrsnSeatLSH_Val_ro & (0x03U)) << 6U) ); + cframe->Data[5] |= (uint8_t) ( ((_m->SMRR_PosnPrsnSeatLSH_Val_ro >> 2U) & (0x3FU)) | ((_m->SMRR_PosnPrsnSeatLSD_Val_ro & (0x03U)) << 6U) ); + cframe->Data[6] |= (uint8_t) ( ((_m->SMRR_PosnPrsnSeatLSD_Val_ro >> 2U) & (0x3FU)) ); + + cframe->MsgId = (uint32_t) SMRR_MEM2_CANID; + cframe->DLC = (uint8_t) SMRR_MEM2_DLC; + cframe->IDE = (uint8_t) SMRR_MEM2_IDE; + return SMRR_MEM2_CANID; +} + +#else + +uint32_t Pack_SMRR_MEM2_candb(SMRR_MEM2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SMRR_MEM2_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->SMRR_PosnActSeatBRHI_Val_ro = (uint8_t) CANDB_SMRR_PosnActSeatBRHI_Val_ro_toS(_m->SMRR_PosnActSeatBRHI_Val_phys); + _m->SMRR_PosnActSeatHRHI_Val_ro = (uint8_t) CANDB_SMRR_PosnActSeatHRHI_Val_ro_toS(_m->SMRR_PosnActSeatHRHI_Val_phys); + _m->SMRR_PosnActSeatBRI_Val_ro = (uint8_t) CANDB_SMRR_PosnActSeatBRI_Val_ro_toS(_m->SMRR_PosnActSeatBRI_Val_phys); + _m->SMRR_PosnPrsnSeatCS_Val_ro = (uint8_t) CANDB_SMRR_PosnPrsnSeatCS_Val_ro_toS(_m->SMRR_PosnPrsnSeatCS_Val_phys); + _m->SMRR_PosnPrsnSeatLSH_Val_ro = (uint8_t) CANDB_SMRR_PosnPrsnSeatLSH_Val_ro_toS(_m->SMRR_PosnPrsnSeatLSH_Val_phys); + _m->SMRR_PosnPrsnSeatLSD_Val_ro = (uint8_t) CANDB_SMRR_PosnPrsnSeatLSD_Val_ro_toS(_m->SMRR_PosnPrsnSeatLSD_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->SMRR_PosnActSeatBRHI_Val_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( (_m->SMRR_PosnActSeatHRHI_Val_ro & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->SMRR_PosnActSeatBRI_Val_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->SMRR_ActHeatBalance_Stat & (0x07U)) | ((_m->SMRR_ActVentBalance_Stat & (0x07U)) << 3U) | ((_m->SMRR_PosnPrsnSeatCS_Val_ro & (0x03U)) << 6U) ); + _d[4] |= (uint8_t) ( ((_m->SMRR_PosnPrsnSeatCS_Val_ro >> 2U) & (0x3FU)) | ((_m->SMRR_PosnPrsnSeatLSH_Val_ro & (0x03U)) << 6U) ); + _d[5] |= (uint8_t) ( ((_m->SMRR_PosnPrsnSeatLSH_Val_ro >> 2U) & (0x3FU)) | ((_m->SMRR_PosnPrsnSeatLSD_Val_ro & (0x03U)) << 6U) ); + _d[6] |= (uint8_t) ( ((_m->SMRR_PosnPrsnSeatLSD_Val_ro >> 2U) & (0x3FU)) ); + + *_len = (uint8_t) SMRR_MEM2_DLC; + *_ide = (uint8_t) SMRR_MEM2_IDE; + return SMRR_MEM2_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_MEM_SMRR2_candb(BCM_MEM_SMRR2_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->BCM_RRMemPosnActSeatBRHI_Val_ro = (uint8_t) ( (_d[0] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_RRMemPosnActSeatBRHI_Val_phys = (sigfloat_t)(CANDB_BCM_RRMemPosnActSeatBRHI_Val_ro_fromS(_m->BCM_RRMemPosnActSeatBRHI_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_RRMemPosnActSeatHRHI_Val_ro = (uint8_t) ( (_d[1] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_RRMemPosnActSeatHRHI_Val_phys = (sigfloat_t)(CANDB_BCM_RRMemPosnActSeatHRHI_Val_ro_fromS(_m->BCM_RRMemPosnActSeatHRHI_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_RRMemPosnActSeatBRI_Val_ro = (uint8_t) ( (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_RRMemPosnActSeatBRI_Val_phys = (sigfloat_t)(CANDB_BCM_RRMemPosnActSeatBRI_Val_ro_fromS(_m->BCM_RRMemPosnActSeatBRI_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_RRMemActHeatBalance_Val = (uint8_t) ( (_d[3] & (0x07U)) ); + _m->BCM_RRMemActVentBalance_Val = (uint8_t) ( ((_d[3] >> 3U) & (0x07U)) ); + _m->BCM_RRMemPosnPrsnSeatCS_Val_ro = (uint8_t) ( ((_d[4] & (0x3FU)) << 2U) | ((_d[3] >> 6U) & (0x03U)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_RRMemPosnPrsnSeatCS_Val_phys = (sigfloat_t)(CANDB_BCM_RRMemPosnPrsnSeatCS_Val_ro_fromS(_m->BCM_RRMemPosnPrsnSeatCS_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_RRMemPosnPrsnSeatLSH_Val_ro = (uint8_t) ( ((_d[5] & (0x3FU)) << 2U) | ((_d[4] >> 6U) & (0x03U)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_RRMemPosnPrsnSeatLSH_Val_phys = (sigfloat_t)(CANDB_BCM_RRMemPosnPrsnSeatLSH_Val_ro_fromS(_m->BCM_RRMemPosnPrsnSeatLSH_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_RRMemPosnPrsnSeatLSD_Val_ro = (uint8_t) ( ((_d[6] & (0x3FU)) << 2U) | ((_d[5] >> 6U) & (0x03U)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_RRMemPosnPrsnSeatLSD_Val_phys = (sigfloat_t)(CANDB_BCM_RRMemPosnPrsnSeatLSD_Val_ro_fromS(_m->BCM_RRMemPosnPrsnSeatLSD_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < BCM_MEM_SMRR2_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_BCM_MEM_SMRR2_candb(&_m->mon1, BCM_MEM_SMRR2_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return BCM_MEM_SMRR2_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_BCM_MEM_SMRR2_candb(BCM_MEM_SMRR2_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_MEM_SMRR2_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_RRMemPosnActSeatBRHI_Val_ro = (uint8_t) CANDB_BCM_RRMemPosnActSeatBRHI_Val_ro_toS(_m->BCM_RRMemPosnActSeatBRHI_Val_phys); + _m->BCM_RRMemPosnActSeatHRHI_Val_ro = (uint8_t) CANDB_BCM_RRMemPosnActSeatHRHI_Val_ro_toS(_m->BCM_RRMemPosnActSeatHRHI_Val_phys); + _m->BCM_RRMemPosnActSeatBRI_Val_ro = (uint8_t) CANDB_BCM_RRMemPosnActSeatBRI_Val_ro_toS(_m->BCM_RRMemPosnActSeatBRI_Val_phys); + _m->BCM_RRMemPosnPrsnSeatCS_Val_ro = (uint8_t) CANDB_BCM_RRMemPosnPrsnSeatCS_Val_ro_toS(_m->BCM_RRMemPosnPrsnSeatCS_Val_phys); + _m->BCM_RRMemPosnPrsnSeatLSH_Val_ro = (uint8_t) CANDB_BCM_RRMemPosnPrsnSeatLSH_Val_ro_toS(_m->BCM_RRMemPosnPrsnSeatLSH_Val_phys); + _m->BCM_RRMemPosnPrsnSeatLSD_Val_ro = (uint8_t) CANDB_BCM_RRMemPosnPrsnSeatLSD_Val_ro_toS(_m->BCM_RRMemPosnPrsnSeatLSD_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->BCM_RRMemPosnActSeatBRHI_Val_ro & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->BCM_RRMemPosnActSeatHRHI_Val_ro & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->BCM_RRMemPosnActSeatBRI_Val_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->BCM_RRMemActHeatBalance_Val & (0x07U)) | ((_m->BCM_RRMemActVentBalance_Val & (0x07U)) << 3U) | ((_m->BCM_RRMemPosnPrsnSeatCS_Val_ro & (0x03U)) << 6U) ); + cframe->Data[4] |= (uint8_t) ( ((_m->BCM_RRMemPosnPrsnSeatCS_Val_ro >> 2U) & (0x3FU)) | ((_m->BCM_RRMemPosnPrsnSeatLSH_Val_ro & (0x03U)) << 6U) ); + cframe->Data[5] |= (uint8_t) ( ((_m->BCM_RRMemPosnPrsnSeatLSH_Val_ro >> 2U) & (0x3FU)) | ((_m->BCM_RRMemPosnPrsnSeatLSD_Val_ro & (0x03U)) << 6U) ); + cframe->Data[6] |= (uint8_t) ( ((_m->BCM_RRMemPosnPrsnSeatLSD_Val_ro >> 2U) & (0x3FU)) ); + + cframe->MsgId = (uint32_t) BCM_MEM_SMRR2_CANID; + cframe->DLC = (uint8_t) BCM_MEM_SMRR2_DLC; + cframe->IDE = (uint8_t) BCM_MEM_SMRR2_IDE; + return BCM_MEM_SMRR2_CANID; +} + +#else + +uint32_t Pack_BCM_MEM_SMRR2_candb(BCM_MEM_SMRR2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_MEM_SMRR2_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_RRMemPosnActSeatBRHI_Val_ro = (uint8_t) CANDB_BCM_RRMemPosnActSeatBRHI_Val_ro_toS(_m->BCM_RRMemPosnActSeatBRHI_Val_phys); + _m->BCM_RRMemPosnActSeatHRHI_Val_ro = (uint8_t) CANDB_BCM_RRMemPosnActSeatHRHI_Val_ro_toS(_m->BCM_RRMemPosnActSeatHRHI_Val_phys); + _m->BCM_RRMemPosnActSeatBRI_Val_ro = (uint8_t) CANDB_BCM_RRMemPosnActSeatBRI_Val_ro_toS(_m->BCM_RRMemPosnActSeatBRI_Val_phys); + _m->BCM_RRMemPosnPrsnSeatCS_Val_ro = (uint8_t) CANDB_BCM_RRMemPosnPrsnSeatCS_Val_ro_toS(_m->BCM_RRMemPosnPrsnSeatCS_Val_phys); + _m->BCM_RRMemPosnPrsnSeatLSH_Val_ro = (uint8_t) CANDB_BCM_RRMemPosnPrsnSeatLSH_Val_ro_toS(_m->BCM_RRMemPosnPrsnSeatLSH_Val_phys); + _m->BCM_RRMemPosnPrsnSeatLSD_Val_ro = (uint8_t) CANDB_BCM_RRMemPosnPrsnSeatLSD_Val_ro_toS(_m->BCM_RRMemPosnPrsnSeatLSD_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->BCM_RRMemPosnActSeatBRHI_Val_ro & (0xFFU)) ); + _d[1] |= (uint8_t) ( (_m->BCM_RRMemPosnActSeatHRHI_Val_ro & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->BCM_RRMemPosnActSeatBRI_Val_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->BCM_RRMemActHeatBalance_Val & (0x07U)) | ((_m->BCM_RRMemActVentBalance_Val & (0x07U)) << 3U) | ((_m->BCM_RRMemPosnPrsnSeatCS_Val_ro & (0x03U)) << 6U) ); + _d[4] |= (uint8_t) ( ((_m->BCM_RRMemPosnPrsnSeatCS_Val_ro >> 2U) & (0x3FU)) | ((_m->BCM_RRMemPosnPrsnSeatLSH_Val_ro & (0x03U)) << 6U) ); + _d[5] |= (uint8_t) ( ((_m->BCM_RRMemPosnPrsnSeatLSH_Val_ro >> 2U) & (0x3FU)) | ((_m->BCM_RRMemPosnPrsnSeatLSD_Val_ro & (0x03U)) << 6U) ); + _d[6] |= (uint8_t) ( ((_m->BCM_RRMemPosnPrsnSeatLSD_Val_ro >> 2U) & (0x3FU)) ); + + *_len = (uint8_t) BCM_MEM_SMRR2_DLC; + *_ide = (uint8_t) BCM_MEM_SMRR2_IDE; + return BCM_MEM_SMRR2_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_SMFL_REQ_CTR_SEATS_candb(FIU_SMFL_REQ_CTR_SEATS_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->FIU_SMFL_SeatHeight_Req = (uint8_t) ( (_d[0] & (0x03U)) ); + _m->FIU_SMFL_HeadRestHeight_Req = (uint8_t) ( ((_d[0] >> 2U) & (0x03U)) ); + _m->FIU_SMFL_SeatLongitunalReq = (uint8_t) ( ((_d[0] >> 4U) & (0x03U)) ); + _m->FIU_SMFL_SeatHeadRestInclin_Req = (uint8_t) ( ((_d[0] >> 6U) & (0x03U)) ); + _m->FIU_SMFL_SeatSurfaceLong_Req = (uint8_t) ( (_d[1] & (0x03U)) ); + _m->FIU_SMFL_SeatLegSupportH_Req = (uint8_t) ( ((_d[1] >> 2U) & (0x03U)) ); + _m->FIU_SMFL_SeatLegSupportLong_Req = (uint8_t) ( ((_d[1] >> 4U) & (0x03U)) ); + _m->FIU_SMFL_SeatInclination_Req = (uint8_t) ( ((_d[1] >> 6U) & (0x03U)) ); + _m->FIU_SMFL_SeatBackRestInc_Req = (uint8_t) ( (_d[2] & (0x03U)) ); + _m->FIU_SMFL_SeatLumbarSupHeight_Req = (uint8_t) ( ((_d[2] >> 2U) & (0x03U)) ); + _m->FIU_SMFL_SeatBackRestHeadInc_Req = (uint8_t) ( ((_d[2] >> 4U) & (0x03U)) ); + _m->FIU_SMFL_SeatLumbarSupDepth_Req = (uint8_t) ( ((_d[2] >> 6U) & (0x03U)) ); + _m->FIU_SMFL_BackRestWidth_Req = (uint8_t) ( (_d[3] & (0x03U)) ); + _m->FIU_SMFL_SeatCushionSupport_Req = (uint8_t) ( ((_d[3] >> 2U) & (0x03U)) ); + _m->FIU_SMFL_SeatMassage_Req = (uint8_t) ( ((_d[3] >> 4U) & (0x03U)) ); + _m->FIU_SMFL_SeatVentilation_Req = (uint8_t) ( ((_d[3] >> 6U) & (0x03U)) ); + _m->FIU_SMFL_SeatVentBalance_Req = (uint8_t) ( (_d[4] & (0x07U)) ); + _m->FIU_SMFL_SeatMassageIntence_Req = (uint8_t) ( ((_d[4] >> 3U) & (0x03U)) ); + _m->FIU_SMFL_SeatHeating_Req = (uint8_t) ( ((_d[4] >> 5U) & (0x03U)) ); + _m->FIU_SMFL_ActiveSupport_Req = (uint8_t) ( ((_d[4] >> 7U) & (0x01U)) ); + _m->FIU_SMFL_SeatHeatBalance_Req = (uint8_t) ( (_d[5] & (0x07U)) ); + _m->FIU_SMFL_SeatMassageType_Req = (uint8_t) ( ((_d[5] >> 3U) & (0x07U)) ); + _m->FIU_SMFL_BackrestMassageType_Req = (uint8_t) ( ((_d[6] & (0x01U)) << 2U) | ((_d[5] >> 6U) & (0x03U)) ); + _m->FIU_SMFL_ComfortMode_Req = (uint8_t) ( ((_d[6] >> 1U) & (0x01U)) ); + _m->FIU_SMFL_ComfortScenario_Req = (uint8_t) ( ((_d[6] >> 2U) & (0x03U)) ); + _m->FIU_SMFL_CarpetHeat_Req = (uint8_t) ( ((_d[6] >> 4U) & (0x01U)) ); + _m->FIU_SMFL_TimerMassage_Req = (uint8_t) ( ((_d[6] >> 5U) & (0x07U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < FIU_SMFL_REQ_CTR_SEATS_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_FIU_SMFL_REQ_CTR_SEATS_candb(&_m->mon1, FIU_SMFL_REQ_CTR_SEATS_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return FIU_SMFL_REQ_CTR_SEATS_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_FIU_SMFL_REQ_CTR_SEATS_candb(FIU_SMFL_REQ_CTR_SEATS_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_SMFL_REQ_CTR_SEATS_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->FIU_SMFL_SeatHeight_Req & (0x03U)) | ((_m->FIU_SMFL_HeadRestHeight_Req & (0x03U)) << 2U) | ((_m->FIU_SMFL_SeatLongitunalReq & (0x03U)) << 4U) | ((_m->FIU_SMFL_SeatHeadRestInclin_Req & (0x03U)) << 6U) ); + cframe->Data[1] |= (uint8_t) ( (_m->FIU_SMFL_SeatSurfaceLong_Req & (0x03U)) | ((_m->FIU_SMFL_SeatLegSupportH_Req & (0x03U)) << 2U) | ((_m->FIU_SMFL_SeatLegSupportLong_Req & (0x03U)) << 4U) | ((_m->FIU_SMFL_SeatInclination_Req & (0x03U)) << 6U) ); + cframe->Data[2] |= (uint8_t) ( (_m->FIU_SMFL_SeatBackRestInc_Req & (0x03U)) | ((_m->FIU_SMFL_SeatLumbarSupHeight_Req & (0x03U)) << 2U) | ((_m->FIU_SMFL_SeatBackRestHeadInc_Req & (0x03U)) << 4U) | ((_m->FIU_SMFL_SeatLumbarSupDepth_Req & (0x03U)) << 6U) ); + cframe->Data[3] |= (uint8_t) ( (_m->FIU_SMFL_BackRestWidth_Req & (0x03U)) | ((_m->FIU_SMFL_SeatCushionSupport_Req & (0x03U)) << 2U) | ((_m->FIU_SMFL_SeatMassage_Req & (0x03U)) << 4U) | ((_m->FIU_SMFL_SeatVentilation_Req & (0x03U)) << 6U) ); + cframe->Data[4] |= (uint8_t) ( (_m->FIU_SMFL_SeatVentBalance_Req & (0x07U)) | ((_m->FIU_SMFL_SeatMassageIntence_Req & (0x03U)) << 3U) | ((_m->FIU_SMFL_SeatHeating_Req & (0x03U)) << 5U) | ((_m->FIU_SMFL_ActiveSupport_Req & (0x01U)) << 7U) ); + cframe->Data[5] |= (uint8_t) ( (_m->FIU_SMFL_SeatHeatBalance_Req & (0x07U)) | ((_m->FIU_SMFL_SeatMassageType_Req & (0x07U)) << 3U) | ((_m->FIU_SMFL_BackrestMassageType_Req & (0x03U)) << 6U) ); + cframe->Data[6] |= (uint8_t) ( ((_m->FIU_SMFL_BackrestMassageType_Req >> 2U) & (0x01U)) | ((_m->FIU_SMFL_ComfortMode_Req & (0x01U)) << 1U) | ((_m->FIU_SMFL_ComfortScenario_Req & (0x03U)) << 2U) | ((_m->FIU_SMFL_CarpetHeat_Req & (0x01U)) << 4U) | ((_m->FIU_SMFL_TimerMassage_Req & (0x07U)) << 5U) ); + + cframe->MsgId = (uint32_t) FIU_SMFL_REQ_CTR_SEATS_CANID; + cframe->DLC = (uint8_t) FIU_SMFL_REQ_CTR_SEATS_DLC; + cframe->IDE = (uint8_t) FIU_SMFL_REQ_CTR_SEATS_IDE; + return FIU_SMFL_REQ_CTR_SEATS_CANID; +} + +#else + +uint32_t Pack_FIU_SMFL_REQ_CTR_SEATS_candb(FIU_SMFL_REQ_CTR_SEATS_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_SMFL_REQ_CTR_SEATS_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->FIU_SMFL_SeatHeight_Req & (0x03U)) | ((_m->FIU_SMFL_HeadRestHeight_Req & (0x03U)) << 2U) | ((_m->FIU_SMFL_SeatLongitunalReq & (0x03U)) << 4U) | ((_m->FIU_SMFL_SeatHeadRestInclin_Req & (0x03U)) << 6U) ); + _d[1] |= (uint8_t) ( (_m->FIU_SMFL_SeatSurfaceLong_Req & (0x03U)) | ((_m->FIU_SMFL_SeatLegSupportH_Req & (0x03U)) << 2U) | ((_m->FIU_SMFL_SeatLegSupportLong_Req & (0x03U)) << 4U) | ((_m->FIU_SMFL_SeatInclination_Req & (0x03U)) << 6U) ); + _d[2] |= (uint8_t) ( (_m->FIU_SMFL_SeatBackRestInc_Req & (0x03U)) | ((_m->FIU_SMFL_SeatLumbarSupHeight_Req & (0x03U)) << 2U) | ((_m->FIU_SMFL_SeatBackRestHeadInc_Req & (0x03U)) << 4U) | ((_m->FIU_SMFL_SeatLumbarSupDepth_Req & (0x03U)) << 6U) ); + _d[3] |= (uint8_t) ( (_m->FIU_SMFL_BackRestWidth_Req & (0x03U)) | ((_m->FIU_SMFL_SeatCushionSupport_Req & (0x03U)) << 2U) | ((_m->FIU_SMFL_SeatMassage_Req & (0x03U)) << 4U) | ((_m->FIU_SMFL_SeatVentilation_Req & (0x03U)) << 6U) ); + _d[4] |= (uint8_t) ( (_m->FIU_SMFL_SeatVentBalance_Req & (0x07U)) | ((_m->FIU_SMFL_SeatMassageIntence_Req & (0x03U)) << 3U) | ((_m->FIU_SMFL_SeatHeating_Req & (0x03U)) << 5U) | ((_m->FIU_SMFL_ActiveSupport_Req & (0x01U)) << 7U) ); + _d[5] |= (uint8_t) ( (_m->FIU_SMFL_SeatHeatBalance_Req & (0x07U)) | ((_m->FIU_SMFL_SeatMassageType_Req & (0x07U)) << 3U) | ((_m->FIU_SMFL_BackrestMassageType_Req & (0x03U)) << 6U) ); + _d[6] |= (uint8_t) ( ((_m->FIU_SMFL_BackrestMassageType_Req >> 2U) & (0x01U)) | ((_m->FIU_SMFL_ComfortMode_Req & (0x01U)) << 1U) | ((_m->FIU_SMFL_ComfortScenario_Req & (0x03U)) << 2U) | ((_m->FIU_SMFL_CarpetHeat_Req & (0x01U)) << 4U) | ((_m->FIU_SMFL_TimerMassage_Req & (0x07U)) << 5U) ); + + *_len = (uint8_t) FIU_SMFL_REQ_CTR_SEATS_DLC; + *_ide = (uint8_t) FIU_SMFL_REQ_CTR_SEATS_IDE; + return FIU_SMFL_REQ_CTR_SEATS_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_SMRR_REQ_CTR_SEATS_candb(FIU_SMRR_REQ_CTR_SEATS_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->FIU_SMRR_SeatHeight_Req = (uint8_t) ( (_d[0] & (0x03U)) ); + _m->FIU_SMRR_HeadRest_Height_Req = (uint8_t) ( ((_d[0] >> 2U) & (0x03U)) ); + _m->FIU_SMRR_SeatLongitunalReq = (uint8_t) ( ((_d[0] >> 4U) & (0x03U)) ); + _m->FIU_SMRR_SeatHeadRestInclin_Req = (uint8_t) ( ((_d[0] >> 6U) & (0x03U)) ); + _m->FIU_SMRR_SeatSurfaceLong_Req = (uint8_t) ( (_d[1] & (0x03U)) ); + _m->FIU_SMRR_SeatLegSupportH_Req = (uint8_t) ( ((_d[1] >> 2U) & (0x03U)) ); + _m->FIU_SMRR_SeatLegSupportLong_Req = (uint8_t) ( ((_d[1] >> 4U) & (0x03U)) ); + _m->FIU_SMRR_SeatInclination_Req = (uint8_t) ( ((_d[1] >> 6U) & (0x03U)) ); + _m->FIU_SMRR_SeatBackRestInc_Req = (uint8_t) ( (_d[2] & (0x03U)) ); + _m->FIU_SMRR_SeatLumbarSupportH_Req = (uint8_t) ( ((_d[2] >> 2U) & (0x03U)) ); + _m->FIU_SMRR_SeatBackRestHeadInc_Req = (uint8_t) ( ((_d[2] >> 4U) & (0x03U)) ); + _m->FIU_SMRR_SeatLumbarSupDepth_Req = (uint8_t) ( ((_d[2] >> 6U) & (0x03U)) ); + _m->FIU_SMRR_BackRestWidth_Req = (uint8_t) ( (_d[3] & (0x03U)) ); + _m->FIU_SMRR_SeatCushionSupport_Req = (uint8_t) ( ((_d[3] >> 2U) & (0x03U)) ); + _m->FIU_SMRR_SeatMassage_Req = (uint8_t) ( ((_d[3] >> 4U) & (0x03U)) ); + _m->FIU_SMRR_SeatVentilation_Req = (uint8_t) ( ((_d[3] >> 6U) & (0x03U)) ); + _m->FIU_SMRR_SeatVentBalance_Req = (uint8_t) ( (_d[4] & (0x07U)) ); + _m->FIU_SMRR_SeatMassageIntence_Req = (uint8_t) ( ((_d[4] >> 3U) & (0x03U)) ); + _m->FIU_SMRR_SeatHeating_Req = (uint8_t) ( ((_d[4] >> 5U) & (0x03U)) ); + _m->FIU_SMRR_ActiveSupport_Req = (uint8_t) ( ((_d[4] >> 7U) & (0x01U)) ); + _m->FIU_SMRR_SeatHeatBalance_Req = (uint8_t) ( (_d[5] & (0x07U)) ); + _m->FIU_SMRR_SeatMassageType_Req = (uint8_t) ( ((_d[5] >> 3U) & (0x07U)) ); + _m->FIU_SMRR_BackrestMassageType_Req = (uint8_t) ( ((_d[6] & (0x01U)) << 2U) | ((_d[5] >> 6U) & (0x03U)) ); + _m->FIU_SMRR_ComfortMode_Req = (uint8_t) ( ((_d[6] >> 1U) & (0x01U)) ); + _m->FIU_SMRR_ComfortScenario_Req = (uint8_t) ( ((_d[6] >> 2U) & (0x03U)) ); + _m->FIU_SMRR_CarpetHeat_Req = (uint8_t) ( ((_d[6] >> 4U) & (0x01U)) ); + _m->FIU_SMRR_TimerMassage_Req = (uint8_t) ( ((_d[6] >> 5U) & (0x07U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < FIU_SMRR_REQ_CTR_SEATS_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_FIU_SMRR_REQ_CTR_SEATS_candb(&_m->mon1, FIU_SMRR_REQ_CTR_SEATS_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return FIU_SMRR_REQ_CTR_SEATS_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_FIU_SMRR_REQ_CTR_SEATS_candb(FIU_SMRR_REQ_CTR_SEATS_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_SMRR_REQ_CTR_SEATS_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->FIU_SMRR_SeatHeight_Req & (0x03U)) | ((_m->FIU_SMRR_HeadRest_Height_Req & (0x03U)) << 2U) | ((_m->FIU_SMRR_SeatLongitunalReq & (0x03U)) << 4U) | ((_m->FIU_SMRR_SeatHeadRestInclin_Req & (0x03U)) << 6U) ); + cframe->Data[1] |= (uint8_t) ( (_m->FIU_SMRR_SeatSurfaceLong_Req & (0x03U)) | ((_m->FIU_SMRR_SeatLegSupportH_Req & (0x03U)) << 2U) | ((_m->FIU_SMRR_SeatLegSupportLong_Req & (0x03U)) << 4U) | ((_m->FIU_SMRR_SeatInclination_Req & (0x03U)) << 6U) ); + cframe->Data[2] |= (uint8_t) ( (_m->FIU_SMRR_SeatBackRestInc_Req & (0x03U)) | ((_m->FIU_SMRR_SeatLumbarSupportH_Req & (0x03U)) << 2U) | ((_m->FIU_SMRR_SeatBackRestHeadInc_Req & (0x03U)) << 4U) | ((_m->FIU_SMRR_SeatLumbarSupDepth_Req & (0x03U)) << 6U) ); + cframe->Data[3] |= (uint8_t) ( (_m->FIU_SMRR_BackRestWidth_Req & (0x03U)) | ((_m->FIU_SMRR_SeatCushionSupport_Req & (0x03U)) << 2U) | ((_m->FIU_SMRR_SeatMassage_Req & (0x03U)) << 4U) | ((_m->FIU_SMRR_SeatVentilation_Req & (0x03U)) << 6U) ); + cframe->Data[4] |= (uint8_t) ( (_m->FIU_SMRR_SeatVentBalance_Req & (0x07U)) | ((_m->FIU_SMRR_SeatMassageIntence_Req & (0x03U)) << 3U) | ((_m->FIU_SMRR_SeatHeating_Req & (0x03U)) << 5U) | ((_m->FIU_SMRR_ActiveSupport_Req & (0x01U)) << 7U) ); + cframe->Data[5] |= (uint8_t) ( (_m->FIU_SMRR_SeatHeatBalance_Req & (0x07U)) | ((_m->FIU_SMRR_SeatMassageType_Req & (0x07U)) << 3U) | ((_m->FIU_SMRR_BackrestMassageType_Req & (0x03U)) << 6U) ); + cframe->Data[6] |= (uint8_t) ( ((_m->FIU_SMRR_BackrestMassageType_Req >> 2U) & (0x01U)) | ((_m->FIU_SMRR_ComfortMode_Req & (0x01U)) << 1U) | ((_m->FIU_SMRR_ComfortScenario_Req & (0x03U)) << 2U) | ((_m->FIU_SMRR_CarpetHeat_Req & (0x01U)) << 4U) | ((_m->FIU_SMRR_TimerMassage_Req & (0x07U)) << 5U) ); + + cframe->MsgId = (uint32_t) FIU_SMRR_REQ_CTR_SEATS_CANID; + cframe->DLC = (uint8_t) FIU_SMRR_REQ_CTR_SEATS_DLC; + cframe->IDE = (uint8_t) FIU_SMRR_REQ_CTR_SEATS_IDE; + return FIU_SMRR_REQ_CTR_SEATS_CANID; +} + +#else + +uint32_t Pack_FIU_SMRR_REQ_CTR_SEATS_candb(FIU_SMRR_REQ_CTR_SEATS_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_SMRR_REQ_CTR_SEATS_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->FIU_SMRR_SeatHeight_Req & (0x03U)) | ((_m->FIU_SMRR_HeadRest_Height_Req & (0x03U)) << 2U) | ((_m->FIU_SMRR_SeatLongitunalReq & (0x03U)) << 4U) | ((_m->FIU_SMRR_SeatHeadRestInclin_Req & (0x03U)) << 6U) ); + _d[1] |= (uint8_t) ( (_m->FIU_SMRR_SeatSurfaceLong_Req & (0x03U)) | ((_m->FIU_SMRR_SeatLegSupportH_Req & (0x03U)) << 2U) | ((_m->FIU_SMRR_SeatLegSupportLong_Req & (0x03U)) << 4U) | ((_m->FIU_SMRR_SeatInclination_Req & (0x03U)) << 6U) ); + _d[2] |= (uint8_t) ( (_m->FIU_SMRR_SeatBackRestInc_Req & (0x03U)) | ((_m->FIU_SMRR_SeatLumbarSupportH_Req & (0x03U)) << 2U) | ((_m->FIU_SMRR_SeatBackRestHeadInc_Req & (0x03U)) << 4U) | ((_m->FIU_SMRR_SeatLumbarSupDepth_Req & (0x03U)) << 6U) ); + _d[3] |= (uint8_t) ( (_m->FIU_SMRR_BackRestWidth_Req & (0x03U)) | ((_m->FIU_SMRR_SeatCushionSupport_Req & (0x03U)) << 2U) | ((_m->FIU_SMRR_SeatMassage_Req & (0x03U)) << 4U) | ((_m->FIU_SMRR_SeatVentilation_Req & (0x03U)) << 6U) ); + _d[4] |= (uint8_t) ( (_m->FIU_SMRR_SeatVentBalance_Req & (0x07U)) | ((_m->FIU_SMRR_SeatMassageIntence_Req & (0x03U)) << 3U) | ((_m->FIU_SMRR_SeatHeating_Req & (0x03U)) << 5U) | ((_m->FIU_SMRR_ActiveSupport_Req & (0x01U)) << 7U) ); + _d[5] |= (uint8_t) ( (_m->FIU_SMRR_SeatHeatBalance_Req & (0x07U)) | ((_m->FIU_SMRR_SeatMassageType_Req & (0x07U)) << 3U) | ((_m->FIU_SMRR_BackrestMassageType_Req & (0x03U)) << 6U) ); + _d[6] |= (uint8_t) ( ((_m->FIU_SMRR_BackrestMassageType_Req >> 2U) & (0x01U)) | ((_m->FIU_SMRR_ComfortMode_Req & (0x01U)) << 1U) | ((_m->FIU_SMRR_ComfortScenario_Req & (0x03U)) << 2U) | ((_m->FIU_SMRR_CarpetHeat_Req & (0x01U)) << 4U) | ((_m->FIU_SMRR_TimerMassage_Req & (0x07U)) << 5U) ); + + *_len = (uint8_t) FIU_SMRR_REQ_CTR_SEATS_DLC; + *_ide = (uint8_t) FIU_SMRR_REQ_CTR_SEATS_IDE; + return FIU_SMRR_REQ_CTR_SEATS_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_CTRL_DW_candb(FIU_CTRL_DW_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->FIU_DWDisplayCntrl_Req = (uint8_t) ( (_d[0] & (0x03U)) ); + _m->FIU_DWGlassCntrl_Req = (uint8_t) ( ((_d[0] >> 2U) & (0x03U)) ); + _m->FIU_DWDisplayMovCntrl_Req = (uint8_t) ( ((_d[0] >> 4U) & (0x03U)) ); + _m->FIU_DWGlassMovCntrl_Req = (uint8_t) ( ((_d[0] >> 6U) & (0x03U)) ); + _m->FIU_DWDisplDimmingMode_Req = (uint8_t) ( (_d[1] & (0x03U)) ); + _m->FIU_DWVideoSignalSrc_Req = (uint8_t) ( ((_d[1] >> 2U) & (0x07U)) ); + _m->FIU_DWDispAutoDimmingVal_Req_ro = (uint8_t) ( (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->FIU_DWDispAutoDimmingVal_Req_phys = (sigfloat_t)(CANDB_FIU_DWDispAutoDimmingVal_Req_ro_fromS(_m->FIU_DWDispAutoDimmingVal_Req_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->FIU_DWDispManualDimming_Val_ro = (uint8_t) ( (_d[3] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->FIU_DWDispManualDimming_Val_phys = (sigfloat_t)(CANDB_FIU_DWDispManualDimming_Val_ro_fromS(_m->FIU_DWDispManualDimming_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < FIU_CTRL_DW_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_FIU_CTRL_DW_candb(&_m->mon1, FIU_CTRL_DW_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return FIU_CTRL_DW_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_FIU_CTRL_DW_candb(FIU_CTRL_DW_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_CTRL_DW_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->FIU_DWDispAutoDimmingVal_Req_ro = (uint8_t) CANDB_FIU_DWDispAutoDimmingVal_Req_ro_toS(_m->FIU_DWDispAutoDimmingVal_Req_phys); + _m->FIU_DWDispManualDimming_Val_ro = (uint8_t) CANDB_FIU_DWDispManualDimming_Val_ro_toS(_m->FIU_DWDispManualDimming_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->FIU_DWDisplayCntrl_Req & (0x03U)) | ((_m->FIU_DWGlassCntrl_Req & (0x03U)) << 2U) | ((_m->FIU_DWDisplayMovCntrl_Req & (0x03U)) << 4U) | ((_m->FIU_DWGlassMovCntrl_Req & (0x03U)) << 6U) ); + cframe->Data[1] |= (uint8_t) ( (_m->FIU_DWDisplDimmingMode_Req & (0x03U)) | ((_m->FIU_DWVideoSignalSrc_Req & (0x07U)) << 2U) ); + cframe->Data[2] |= (uint8_t) ( (_m->FIU_DWDispAutoDimmingVal_Req_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->FIU_DWDispManualDimming_Val_ro & (0xFFU)) ); + + cframe->MsgId = (uint32_t) FIU_CTRL_DW_CANID; + cframe->DLC = (uint8_t) FIU_CTRL_DW_DLC; + cframe->IDE = (uint8_t) FIU_CTRL_DW_IDE; + return FIU_CTRL_DW_CANID; +} + +#else + +uint32_t Pack_FIU_CTRL_DW_candb(FIU_CTRL_DW_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_CTRL_DW_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->FIU_DWDispAutoDimmingVal_Req_ro = (uint8_t) CANDB_FIU_DWDispAutoDimmingVal_Req_ro_toS(_m->FIU_DWDispAutoDimmingVal_Req_phys); + _m->FIU_DWDispManualDimming_Val_ro = (uint8_t) CANDB_FIU_DWDispManualDimming_Val_ro_toS(_m->FIU_DWDispManualDimming_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->FIU_DWDisplayCntrl_Req & (0x03U)) | ((_m->FIU_DWGlassCntrl_Req & (0x03U)) << 2U) | ((_m->FIU_DWDisplayMovCntrl_Req & (0x03U)) << 4U) | ((_m->FIU_DWGlassMovCntrl_Req & (0x03U)) << 6U) ); + _d[1] |= (uint8_t) ( (_m->FIU_DWDisplDimmingMode_Req & (0x03U)) | ((_m->FIU_DWVideoSignalSrc_Req & (0x07U)) << 2U) ); + _d[2] |= (uint8_t) ( (_m->FIU_DWDispAutoDimmingVal_Req_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->FIU_DWDispManualDimming_Val_ro & (0xFFU)) ); + + *_len = (uint8_t) FIU_CTRL_DW_DLC; + *_ide = (uint8_t) FIU_CTRL_DW_IDE; + return FIU_CTRL_DW_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_DW_STATE_candb(DW_STATE_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->DW_Display_Stat = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->DW_MediaPower_Stat = (uint8_t) ( ((_d[0] >> 1U) & (0x01U)) ); + _m->DW_Display_Req = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + _m->DW_Glass_Stat = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + _m->DW_AntiPinchFlag_Stat = (uint8_t) ( ((_d[0] >> 4U) & (0x01U)) ); + _m->DW_CurrentVideoSigSrc_Stat = (uint8_t) ( ((_d[0] >> 5U) & (0x07U)) ); + _m->DW_DisplayPosition_Stat = (uint8_t) ( (_d[1] & (0x03U)) ); + _m->DW_GlassPosition_Stat = (uint8_t) ( ((_d[1] >> 2U) & (0x03U)) ); + _m->DW_MovingDisplay_Stat = (uint8_t) ( ((_d[1] >> 4U) & (0x03U)) ); + _m->DW_MovingGlass_Stat = (uint8_t) ( ((_d[1] >> 6U) & (0x03U)) ); + _m->DW_DisplayDimmingMode_Stat = (uint8_t) ( (_d[2] & (0x03U)) ); + _m->DW_DetectedMMSSrc_Stat = (uint8_t) ( ((_d[2] >> 3U) & (0x01U)) ); + _m->DW_DetectedCAMSrc_Stat = (uint8_t) ( ((_d[2] >> 4U) & (0x01U)) ); + _m->DW_DetectedHDMI1Src_Stat = (uint8_t) ( ((_d[2] >> 5U) & (0x01U)) ); + _m->DW_DetectedHDMI2Src_Stat = (uint8_t) ( ((_d[2] >> 6U) & (0x01U)) ); + _m->DW_DetectedHDMISockSrc_Stat = (uint8_t) ( ((_d[2] >> 7U) & (0x01U)) ); + _m->DW_DisplayBrightness_Stat_ro = (uint8_t) ( (_d[3] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->DW_DisplayBrightness_Stat_phys = (sigfloat_t)(CANDB_DW_DisplayBrightness_Stat_ro_fromS(_m->DW_DisplayBrightness_Stat_ro)); +#endif // CANDB_USE_SIGFLOAT + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < DW_STATE_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_DW_STATE_candb(&_m->mon1, DW_STATE_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return DW_STATE_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_DW_STATE_candb(DW_STATE_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(DW_STATE_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->DW_DisplayBrightness_Stat_ro = (uint8_t) CANDB_DW_DisplayBrightness_Stat_ro_toS(_m->DW_DisplayBrightness_Stat_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->DW_Display_Stat & (0x01U)) | ((_m->DW_MediaPower_Stat & (0x01U)) << 1U) | ((_m->DW_Display_Req & (0x01U)) << 2U) | ((_m->DW_Glass_Stat & (0x01U)) << 3U) | ((_m->DW_AntiPinchFlag_Stat & (0x01U)) << 4U) | ((_m->DW_CurrentVideoSigSrc_Stat & (0x07U)) << 5U) ); + cframe->Data[1] |= (uint8_t) ( (_m->DW_DisplayPosition_Stat & (0x03U)) | ((_m->DW_GlassPosition_Stat & (0x03U)) << 2U) | ((_m->DW_MovingDisplay_Stat & (0x03U)) << 4U) | ((_m->DW_MovingGlass_Stat & (0x03U)) << 6U) ); + cframe->Data[2] |= (uint8_t) ( (_m->DW_DisplayDimmingMode_Stat & (0x03U)) | ((_m->DW_DetectedMMSSrc_Stat & (0x01U)) << 3U) | ((_m->DW_DetectedCAMSrc_Stat & (0x01U)) << 4U) | ((_m->DW_DetectedHDMI1Src_Stat & (0x01U)) << 5U) | ((_m->DW_DetectedHDMI2Src_Stat & (0x01U)) << 6U) | ((_m->DW_DetectedHDMISockSrc_Stat & (0x01U)) << 7U) ); + cframe->Data[3] |= (uint8_t) ( (_m->DW_DisplayBrightness_Stat_ro & (0xFFU)) ); + + cframe->MsgId = (uint32_t) DW_STATE_CANID; + cframe->DLC = (uint8_t) DW_STATE_DLC; + cframe->IDE = (uint8_t) DW_STATE_IDE; + return DW_STATE_CANID; +} + +#else + +uint32_t Pack_DW_STATE_candb(DW_STATE_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(DW_STATE_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->DW_DisplayBrightness_Stat_ro = (uint8_t) CANDB_DW_DisplayBrightness_Stat_ro_toS(_m->DW_DisplayBrightness_Stat_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->DW_Display_Stat & (0x01U)) | ((_m->DW_MediaPower_Stat & (0x01U)) << 1U) | ((_m->DW_Display_Req & (0x01U)) << 2U) | ((_m->DW_Glass_Stat & (0x01U)) << 3U) | ((_m->DW_AntiPinchFlag_Stat & (0x01U)) << 4U) | ((_m->DW_CurrentVideoSigSrc_Stat & (0x07U)) << 5U) ); + _d[1] |= (uint8_t) ( (_m->DW_DisplayPosition_Stat & (0x03U)) | ((_m->DW_GlassPosition_Stat & (0x03U)) << 2U) | ((_m->DW_MovingDisplay_Stat & (0x03U)) << 4U) | ((_m->DW_MovingGlass_Stat & (0x03U)) << 6U) ); + _d[2] |= (uint8_t) ( (_m->DW_DisplayDimmingMode_Stat & (0x03U)) | ((_m->DW_DetectedMMSSrc_Stat & (0x01U)) << 3U) | ((_m->DW_DetectedCAMSrc_Stat & (0x01U)) << 4U) | ((_m->DW_DetectedHDMI1Src_Stat & (0x01U)) << 5U) | ((_m->DW_DetectedHDMI2Src_Stat & (0x01U)) << 6U) | ((_m->DW_DetectedHDMISockSrc_Stat & (0x01U)) << 7U) ); + _d[3] |= (uint8_t) ( (_m->DW_DisplayBrightness_Stat_ro & (0xFFU)) ); + + *_len = (uint8_t) DW_STATE_DLC; + *_ide = (uint8_t) DW_STATE_IDE; + return DW_STATE_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_Msg1_candb(FIU_Msg1_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->FIU_HeadlightWashing_Req = (uint8_t) ( ((_d[0] >> 1U) & (0x01U)) ); + _m->FIU_AutoWiper_Req = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + _m->FIU_WelcomeLeavingLight_Req = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + _m->FIU_WelcomeLeavingLightTime_Req = (uint8_t) ( ((_d[0] >> 4U) & (0x03U)) ); + _m->FIU_WindowsRainClosing_Req = (uint8_t) ( ((_d[0] >> 6U) & (0x01U)) ); + _m->FIU_MirrorsAutoFold_Req = (uint8_t) ( ((_d[0] >> 7U) & (0x01U)) ); + _m->FIU_AutoTiltMirrors_Req = (uint8_t) ( (_d[1] & (0x01U)) ); + _m->FIU_SteeringWheelAutoHeat_Req = (uint8_t) ( ((_d[1] >> 1U) & (0x01U)) ); + _m->FIU_DoorsLock_Req = (uint8_t) ( ((_d[1] >> 2U) & (0x01U)) ); + _m->FIU_DoorsDriveLock_Req = (uint8_t) ( ((_d[1] >> 3U) & (0x01U)) ); + _m->FIU_AudibleLockFdBack_Req = (uint8_t) ( ((_d[1] >> 4U) & (0x01U)) ); + _m->FIU_ApproachAccess_Req = (uint8_t) ( ((_d[1] >> 6U) & (0x01U)) ); + _m->FIU_TrnkDoorCloseBySpeed_Req = (uint8_t) ( ((_d[1] >> 7U) & (0x01U)) ); + _m->FIU_WelcomeLightAnimation_Req = (uint8_t) ( (_d[2] & (0x01U)) ); + _m->FIU_MAS_CamerasWashing_Req = (uint8_t) ( (_d[3] & (0x01U)) ); + _m->FIU_DoorCntrlRR_Req = (uint8_t) ( (_d[4] & (0x03U)) ); + _m->FIU_DoorCntrlFR_Req = (uint8_t) ( ((_d[4] >> 2U) & (0x03U)) ); + _m->FIU_DoorCntrlFL_Req = (uint8_t) ( ((_d[4] >> 4U) & (0x03U)) ); + _m->FIU_DoorCntrlRL_Req = (uint8_t) ( ((_d[4] >> 6U) & (0x03U)) ); + _m->FIU_DoorCntrlTrunk_Req = (uint8_t) ( (_d[5] & (0x03U)) ); + _m->FIU_EasyExitEnableRR_Req = (uint8_t) ( ((_d[5] >> 2U) & (0x01U)) ); + _m->FIU_EasyExitEnableRL_Req = (uint8_t) ( ((_d[5] >> 3U) & (0x01U)) ); + _m->FIU_EasyExitEnableFR_Req = (uint8_t) ( ((_d[5] >> 4U) & (0x01U)) ); + _m->FIU_EasyExitEnableFL_Req = (uint8_t) ( ((_d[5] >> 5U) & (0x01U)) ); + _m->FIU_FrontCeilingBright_Val_ro = (uint8_t) ( (_d[6] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->FIU_FrontCeilingBright_Val_phys = (sigfloat_t)(CANDB_FIU_FrontCeilingBright_Val_ro_fromS(_m->FIU_FrontCeilingBright_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->FIU_RearCeilingBright_Val_ro = (uint8_t) ( (_d[7] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->FIU_RearCeilingBright_Val_phys = (sigfloat_t)(CANDB_FIU_RearCeilingBright_Val_ro_fromS(_m->FIU_RearCeilingBright_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < FIU_Msg1_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_FIU_Msg1_candb(&_m->mon1, FIU_Msg1_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return FIU_Msg1_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_FIU_Msg1_candb(FIU_Msg1_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_Msg1_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->FIU_FrontCeilingBright_Val_ro = (uint8_t) CANDB_FIU_FrontCeilingBright_Val_ro_toS(_m->FIU_FrontCeilingBright_Val_phys); + _m->FIU_RearCeilingBright_Val_ro = (uint8_t) CANDB_FIU_RearCeilingBright_Val_ro_toS(_m->FIU_RearCeilingBright_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( ((_m->FIU_HeadlightWashing_Req & (0x01U)) << 1U) | ((_m->FIU_AutoWiper_Req & (0x01U)) << 2U) | ((_m->FIU_WelcomeLeavingLight_Req & (0x01U)) << 3U) | ((_m->FIU_WelcomeLeavingLightTime_Req & (0x03U)) << 4U) | ((_m->FIU_WindowsRainClosing_Req & (0x01U)) << 6U) | ((_m->FIU_MirrorsAutoFold_Req & (0x01U)) << 7U) ); + cframe->Data[1] |= (uint8_t) ( (_m->FIU_AutoTiltMirrors_Req & (0x01U)) | ((_m->FIU_SteeringWheelAutoHeat_Req & (0x01U)) << 1U) | ((_m->FIU_DoorsLock_Req & (0x01U)) << 2U) | ((_m->FIU_DoorsDriveLock_Req & (0x01U)) << 3U) | ((_m->FIU_AudibleLockFdBack_Req & (0x01U)) << 4U) | ((_m->FIU_ApproachAccess_Req & (0x01U)) << 6U) | ((_m->FIU_TrnkDoorCloseBySpeed_Req & (0x01U)) << 7U) ); + cframe->Data[2] |= (uint8_t) ( (_m->FIU_WelcomeLightAnimation_Req & (0x01U)) ); + cframe->Data[3] |= (uint8_t) ( (_m->FIU_MAS_CamerasWashing_Req & (0x01U)) ); + cframe->Data[4] |= (uint8_t) ( (_m->FIU_DoorCntrlRR_Req & (0x03U)) | ((_m->FIU_DoorCntrlFR_Req & (0x03U)) << 2U) | ((_m->FIU_DoorCntrlFL_Req & (0x03U)) << 4U) | ((_m->FIU_DoorCntrlRL_Req & (0x03U)) << 6U) ); + cframe->Data[5] |= (uint8_t) ( (_m->FIU_DoorCntrlTrunk_Req & (0x03U)) | ((_m->FIU_EasyExitEnableRR_Req & (0x01U)) << 2U) | ((_m->FIU_EasyExitEnableRL_Req & (0x01U)) << 3U) | ((_m->FIU_EasyExitEnableFR_Req & (0x01U)) << 4U) | ((_m->FIU_EasyExitEnableFL_Req & (0x01U)) << 5U) ); + cframe->Data[6] |= (uint8_t) ( (_m->FIU_FrontCeilingBright_Val_ro & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->FIU_RearCeilingBright_Val_ro & (0xFFU)) ); + + cframe->MsgId = (uint32_t) FIU_Msg1_CANID; + cframe->DLC = (uint8_t) FIU_Msg1_DLC; + cframe->IDE = (uint8_t) FIU_Msg1_IDE; + return FIU_Msg1_CANID; +} + +#else + +uint32_t Pack_FIU_Msg1_candb(FIU_Msg1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_Msg1_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->FIU_FrontCeilingBright_Val_ro = (uint8_t) CANDB_FIU_FrontCeilingBright_Val_ro_toS(_m->FIU_FrontCeilingBright_Val_phys); + _m->FIU_RearCeilingBright_Val_ro = (uint8_t) CANDB_FIU_RearCeilingBright_Val_ro_toS(_m->FIU_RearCeilingBright_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( ((_m->FIU_HeadlightWashing_Req & (0x01U)) << 1U) | ((_m->FIU_AutoWiper_Req & (0x01U)) << 2U) | ((_m->FIU_WelcomeLeavingLight_Req & (0x01U)) << 3U) | ((_m->FIU_WelcomeLeavingLightTime_Req & (0x03U)) << 4U) | ((_m->FIU_WindowsRainClosing_Req & (0x01U)) << 6U) | ((_m->FIU_MirrorsAutoFold_Req & (0x01U)) << 7U) ); + _d[1] |= (uint8_t) ( (_m->FIU_AutoTiltMirrors_Req & (0x01U)) | ((_m->FIU_SteeringWheelAutoHeat_Req & (0x01U)) << 1U) | ((_m->FIU_DoorsLock_Req & (0x01U)) << 2U) | ((_m->FIU_DoorsDriveLock_Req & (0x01U)) << 3U) | ((_m->FIU_AudibleLockFdBack_Req & (0x01U)) << 4U) | ((_m->FIU_ApproachAccess_Req & (0x01U)) << 6U) | ((_m->FIU_TrnkDoorCloseBySpeed_Req & (0x01U)) << 7U) ); + _d[2] |= (uint8_t) ( (_m->FIU_WelcomeLightAnimation_Req & (0x01U)) ); + _d[3] |= (uint8_t) ( (_m->FIU_MAS_CamerasWashing_Req & (0x01U)) ); + _d[4] |= (uint8_t) ( (_m->FIU_DoorCntrlRR_Req & (0x03U)) | ((_m->FIU_DoorCntrlFR_Req & (0x03U)) << 2U) | ((_m->FIU_DoorCntrlFL_Req & (0x03U)) << 4U) | ((_m->FIU_DoorCntrlRL_Req & (0x03U)) << 6U) ); + _d[5] |= (uint8_t) ( (_m->FIU_DoorCntrlTrunk_Req & (0x03U)) | ((_m->FIU_EasyExitEnableRR_Req & (0x01U)) << 2U) | ((_m->FIU_EasyExitEnableRL_Req & (0x01U)) << 3U) | ((_m->FIU_EasyExitEnableFR_Req & (0x01U)) << 4U) | ((_m->FIU_EasyExitEnableFL_Req & (0x01U)) << 5U) ); + _d[6] |= (uint8_t) ( (_m->FIU_FrontCeilingBright_Val_ro & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->FIU_RearCeilingBright_Val_ro & (0xFFU)) ); + + *_len = (uint8_t) FIU_Msg1_DLC; + *_ide = (uint8_t) FIU_Msg1_IDE; + return FIU_Msg1_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_Msg2_candb(FIU_Msg2_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->FIU_StyleIllGlobal_Req = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->FIU_ChildLock_RLtablet_Req = (uint8_t) ( ((_d[0] >> 1U) & (0x01U)) ); + _m->FIU_ConfCamera_Req = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + _m->FIU_StyleIllTheme_Req = (uint8_t) ( ((_d[0] >> 3U) & (0x0FU)) ); + _m->FIU_ChildLock_RRtablet_Req = (uint8_t) ( ((_d[0] >> 7U) & (0x01U)) ); + _m->FIU_ChildLock_RRdoor_Req = (uint8_t) ( (_d[1] & (0x01U)) ); + _m->FIU_ChildLock_RCtablet_Req = (uint8_t) ( ((_d[1] >> 1U) & (0x01U)) ); + _m->FIU_ChildLock_RLdoor_Req = (uint8_t) ( ((_d[1] >> 3U) & (0x01U)) ); + _m->FIU_StyleLghtVoice_Req = (uint8_t) ( ((_d[1] >> 5U) & (0x01U)) ); + _m->FIU_AlarmOFF_Req = (uint8_t) ( ((_d[1] >> 6U) & (0x01U)) ); + _m->FIU_MovementSensOFF_Req = (uint8_t) ( ((_d[1] >> 7U) & (0x01U)) ); + _m->FIU_ChildLock_RLwindow_Req = (uint8_t) ( (_d[2] & (0x01U)) ); + _m->FIU_CoolingBox_Req = (uint8_t) ( ((_d[2] >> 3U) & (0x03U)) ); + _m->FIU_ChildLock_RRwindow_Req = (uint8_t) ( (_d[3] & (0x01U)) ); + _m->FIU_TrafficSide_Stat = (uint8_t) ( ((_d[3] >> 7U) & (0x01U)) ); + _m->FIU_UnlockExternal_Req = (uint8_t) ( (_d[4] & (0x01U)) ); + _m->FIU_StyleIllBright_Val = (uint8_t) ( (_d[5] & (0x7FU)) ); + _m->FIU_UnlockAfterDrive_Req = (uint8_t) ( (_d[7] & (0x01U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < FIU_Msg2_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_FIU_Msg2_candb(&_m->mon1, FIU_Msg2_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return FIU_Msg2_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_FIU_Msg2_candb(FIU_Msg2_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_Msg2_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->FIU_StyleIllGlobal_Req & (0x01U)) | ((_m->FIU_ChildLock_RLtablet_Req & (0x01U)) << 1U) | ((_m->FIU_ConfCamera_Req & (0x01U)) << 2U) | ((_m->FIU_StyleIllTheme_Req & (0x0FU)) << 3U) | ((_m->FIU_ChildLock_RRtablet_Req & (0x01U)) << 7U) ); + cframe->Data[1] |= (uint8_t) ( (_m->FIU_ChildLock_RRdoor_Req & (0x01U)) | ((_m->FIU_ChildLock_RCtablet_Req & (0x01U)) << 1U) | ((_m->FIU_ChildLock_RLdoor_Req & (0x01U)) << 3U) | ((_m->FIU_StyleLghtVoice_Req & (0x01U)) << 5U) | ((_m->FIU_AlarmOFF_Req & (0x01U)) << 6U) | ((_m->FIU_MovementSensOFF_Req & (0x01U)) << 7U) ); + cframe->Data[2] |= (uint8_t) ( (_m->FIU_ChildLock_RLwindow_Req & (0x01U)) | ((_m->FIU_CoolingBox_Req & (0x03U)) << 3U) ); + cframe->Data[3] |= (uint8_t) ( (_m->FIU_ChildLock_RRwindow_Req & (0x01U)) | ((_m->FIU_TrafficSide_Stat & (0x01U)) << 7U) ); + cframe->Data[4] |= (uint8_t) ( (_m->FIU_UnlockExternal_Req & (0x01U)) ); + cframe->Data[5] |= (uint8_t) ( (_m->FIU_StyleIllBright_Val & (0x7FU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->FIU_UnlockAfterDrive_Req & (0x01U)) ); + + cframe->MsgId = (uint32_t) FIU_Msg2_CANID; + cframe->DLC = (uint8_t) FIU_Msg2_DLC; + cframe->IDE = (uint8_t) FIU_Msg2_IDE; + return FIU_Msg2_CANID; +} + +#else + +uint32_t Pack_FIU_Msg2_candb(FIU_Msg2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_Msg2_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->FIU_StyleIllGlobal_Req & (0x01U)) | ((_m->FIU_ChildLock_RLtablet_Req & (0x01U)) << 1U) | ((_m->FIU_ConfCamera_Req & (0x01U)) << 2U) | ((_m->FIU_StyleIllTheme_Req & (0x0FU)) << 3U) | ((_m->FIU_ChildLock_RRtablet_Req & (0x01U)) << 7U) ); + _d[1] |= (uint8_t) ( (_m->FIU_ChildLock_RRdoor_Req & (0x01U)) | ((_m->FIU_ChildLock_RCtablet_Req & (0x01U)) << 1U) | ((_m->FIU_ChildLock_RLdoor_Req & (0x01U)) << 3U) | ((_m->FIU_StyleLghtVoice_Req & (0x01U)) << 5U) | ((_m->FIU_AlarmOFF_Req & (0x01U)) << 6U) | ((_m->FIU_MovementSensOFF_Req & (0x01U)) << 7U) ); + _d[2] |= (uint8_t) ( (_m->FIU_ChildLock_RLwindow_Req & (0x01U)) | ((_m->FIU_CoolingBox_Req & (0x03U)) << 3U) ); + _d[3] |= (uint8_t) ( (_m->FIU_ChildLock_RRwindow_Req & (0x01U)) | ((_m->FIU_TrafficSide_Stat & (0x01U)) << 7U) ); + _d[4] |= (uint8_t) ( (_m->FIU_UnlockExternal_Req & (0x01U)) ); + _d[5] |= (uint8_t) ( (_m->FIU_StyleIllBright_Val & (0x7FU)) ); + _d[7] |= (uint8_t) ( (_m->FIU_UnlockAfterDrive_Req & (0x01U)) ); + + *_len = (uint8_t) FIU_Msg2_DLC; + *_ide = (uint8_t) FIU_Msg2_IDE; + return FIU_Msg2_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_ERAG_DATA_MSG_candb(ERAG_DATA_MSG_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->ERAG_FailureSts = (uint8_t) ( (_d[0] & (0x0FU)) ); + _m->ERAG_MuteReq = (uint8_t) ( ((_d[0] >> 4U) & (0x01U)) ); + _m->ERAG_Status = (uint8_t) ( (_d[1] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < ERAG_DATA_MSG_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_ERAG_DATA_MSG_candb(&_m->mon1, ERAG_DATA_MSG_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return ERAG_DATA_MSG_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_ERAG_DATA_MSG_candb(ERAG_DATA_MSG_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(ERAG_DATA_MSG_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->ERAG_FailureSts & (0x0FU)) | ((_m->ERAG_MuteReq & (0x01U)) << 4U) ); + cframe->Data[1] |= (uint8_t) ( (_m->ERAG_Status & (0xFFU)) ); + + cframe->MsgId = (uint32_t) ERAG_DATA_MSG_CANID; + cframe->DLC = (uint8_t) ERAG_DATA_MSG_DLC; + cframe->IDE = (uint8_t) ERAG_DATA_MSG_IDE; + return ERAG_DATA_MSG_CANID; +} + +#else + +uint32_t Pack_ERAG_DATA_MSG_candb(ERAG_DATA_MSG_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(ERAG_DATA_MSG_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->ERAG_FailureSts & (0x0FU)) | ((_m->ERAG_MuteReq & (0x01U)) << 4U) ); + _d[1] |= (uint8_t) ( (_m->ERAG_Status & (0xFFU)) ); + + *_len = (uint8_t) ERAG_DATA_MSG_DLC; + *_ide = (uint8_t) ERAG_DATA_MSG_IDE; + return ERAG_DATA_MSG_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_Msg3_candb(FIU_Msg3_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->FIU_ArmrestHeatFL_Req = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->FIU_ArmrestHeatFR_Req = (uint8_t) ( ((_d[0] >> 1U) & (0x01U)) ); + _m->FIU_ArmrestHeatRL_Req = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + _m->FIU_ArmrestHeatRR_Req = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + _m->FIU_FL_Synx_Req = (uint8_t) ( ((_d[0] >> 4U) & (0x03U)) ); + _m->FIU_FR_Synx_Req = (uint8_t) ( ((_d[0] >> 6U) & (0x03U)) ); + _m->FIU_RL_Synx_Req = (uint8_t) ( (_d[1] & (0x03U)) ); + _m->FIU_RR_Synx_Req = (uint8_t) ( ((_d[1] >> 2U) & (0x03U)) ); + _m->FIU_SchedTue_Stat = (uint8_t) ( ((_d[1] >> 4U) & (0x01U)) ); + _m->FIU_SchedWed_Stat = (uint8_t) ( ((_d[1] >> 5U) & (0x01U)) ); + _m->FIU_SchedThu_Stat = (uint8_t) ( ((_d[1] >> 6U) & (0x01U)) ); + _m->FIU_SchedFri_Stat = (uint8_t) ( ((_d[1] >> 7U) & (0x01U)) ); + _m->FIU_ICimage_Req = (uint8_t) ( (_d[2] & (0x03U)) ); + _m->FIU_ProjectionOnRoad_Req = (uint8_t) ( ((_d[2] >> 2U) & (0x01U)) ); + _m->FIU_RearSideWindowsElcrome_Req = (uint8_t) ( ((_d[2] >> 3U) & (0x03U)) ); + _m->FIU_ProjectionRoadSigns_Req = (uint8_t) ( ((_d[2] >> 5U) & (0x01U)) ); + _m->FIU_ProjectionNavigation_Req = (uint8_t) ( ((_d[2] >> 6U) & (0x01U)) ); + _m->FIU_ProjectionLiveObj_Req = (uint8_t) ( ((_d[2] >> 7U) & (0x01U)) ); + _m->FIU_SchedSat_Stat = (uint8_t) ( (_d[3] & (0x01U)) ); + _m->FIU_SchedSu_Stat = (uint8_t) ( ((_d[3] >> 1U) & (0x01U)) ); + _m->FIU_Sched_StartTimeHours_Val = (uint8_t) ( ((_d[3] >> 2U) & (0x1FU)) ); + _m->FIU_SchedStart_Stat = (uint8_t) ( ((_d[3] >> 7U) & (0x01U)) ); + _m->FIU_ChrgLim_Val = (uint8_t) ( (_d[4] & (0x07U)) ); + _m->FIU_DischrgLim_Val = (uint8_t) ( ((_d[4] >> 3U) & (0x07U)) ); + _m->FIU_ReduceChrgCurr_Stat = (uint8_t) ( ((_d[4] >> 6U) & (0x01U)) ); + _m->FIU_SchedMon_Stat = (uint8_t) ( ((_d[4] >> 7U) & (0x01U)) ); + _m->FIU_Sched_StartTimeMinutes_Val_ro = (uint8_t) ( (_d[5] & (0x0FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->FIU_Sched_StartTimeMinutes_Val_phys = (uint8_t) CANDB_FIU_Sched_StartTimeMinutes_Val_ro_fromS(_m->FIU_Sched_StartTimeMinutes_Val_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->FIU_Sched_EndTimeMinutes_Val_ro = (uint8_t) ( ((_d[5] >> 4U) & (0x0FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->FIU_Sched_EndTimeMinutes_Val_phys = (uint8_t) CANDB_FIU_Sched_EndTimeMinutes_Val_ro_fromS(_m->FIU_Sched_EndTimeMinutes_Val_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->FIU_Sched_EndTimeHours_Val = (uint8_t) ( (_d[6] & (0x1FU)) ); + _m->FIU_SchedEnd_Stat = (uint8_t) ( ((_d[6] >> 5U) & (0x01U)) ); + _m->FIU_PrepearClim_Stat = (uint8_t) ( ((_d[6] >> 6U) & (0x01U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < FIU_Msg3_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_FIU_Msg3_candb(&_m->mon1, FIU_Msg3_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return FIU_Msg3_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_FIU_Msg3_candb(FIU_Msg3_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_Msg3_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->FIU_Sched_StartTimeMinutes_Val_ro = (uint8_t) CANDB_FIU_Sched_StartTimeMinutes_Val_ro_toS(_m->FIU_Sched_StartTimeMinutes_Val_phys); + _m->FIU_Sched_EndTimeMinutes_Val_ro = (uint8_t) CANDB_FIU_Sched_EndTimeMinutes_Val_ro_toS(_m->FIU_Sched_EndTimeMinutes_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->FIU_ArmrestHeatFL_Req & (0x01U)) | ((_m->FIU_ArmrestHeatFR_Req & (0x01U)) << 1U) | ((_m->FIU_ArmrestHeatRL_Req & (0x01U)) << 2U) | ((_m->FIU_ArmrestHeatRR_Req & (0x01U)) << 3U) | ((_m->FIU_FL_Synx_Req & (0x03U)) << 4U) | ((_m->FIU_FR_Synx_Req & (0x03U)) << 6U) ); + cframe->Data[1] |= (uint8_t) ( (_m->FIU_RL_Synx_Req & (0x03U)) | ((_m->FIU_RR_Synx_Req & (0x03U)) << 2U) | ((_m->FIU_SchedTue_Stat & (0x01U)) << 4U) | ((_m->FIU_SchedWed_Stat & (0x01U)) << 5U) | ((_m->FIU_SchedThu_Stat & (0x01U)) << 6U) | ((_m->FIU_SchedFri_Stat & (0x01U)) << 7U) ); + cframe->Data[2] |= (uint8_t) ( (_m->FIU_ICimage_Req & (0x03U)) | ((_m->FIU_ProjectionOnRoad_Req & (0x01U)) << 2U) | ((_m->FIU_RearSideWindowsElcrome_Req & (0x03U)) << 3U) | ((_m->FIU_ProjectionRoadSigns_Req & (0x01U)) << 5U) | ((_m->FIU_ProjectionNavigation_Req & (0x01U)) << 6U) | ((_m->FIU_ProjectionLiveObj_Req & (0x01U)) << 7U) ); + cframe->Data[3] |= (uint8_t) ( (_m->FIU_SchedSat_Stat & (0x01U)) | ((_m->FIU_SchedSu_Stat & (0x01U)) << 1U) | ((_m->FIU_Sched_StartTimeHours_Val & (0x1FU)) << 2U) | ((_m->FIU_SchedStart_Stat & (0x01U)) << 7U) ); + cframe->Data[4] |= (uint8_t) ( (_m->FIU_ChrgLim_Val & (0x07U)) | ((_m->FIU_DischrgLim_Val & (0x07U)) << 3U) | ((_m->FIU_ReduceChrgCurr_Stat & (0x01U)) << 6U) | ((_m->FIU_SchedMon_Stat & (0x01U)) << 7U) ); + cframe->Data[5] |= (uint8_t) ( (_m->FIU_Sched_StartTimeMinutes_Val_ro & (0x0FU)) | ((_m->FIU_Sched_EndTimeMinutes_Val_ro & (0x0FU)) << 4U) ); + cframe->Data[6] |= (uint8_t) ( (_m->FIU_Sched_EndTimeHours_Val & (0x1FU)) | ((_m->FIU_SchedEnd_Stat & (0x01U)) << 5U) | ((_m->FIU_PrepearClim_Stat & (0x01U)) << 6U) ); + + cframe->MsgId = (uint32_t) FIU_Msg3_CANID; + cframe->DLC = (uint8_t) FIU_Msg3_DLC; + cframe->IDE = (uint8_t) FIU_Msg3_IDE; + return FIU_Msg3_CANID; +} + +#else + +uint32_t Pack_FIU_Msg3_candb(FIU_Msg3_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_Msg3_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->FIU_Sched_StartTimeMinutes_Val_ro = (uint8_t) CANDB_FIU_Sched_StartTimeMinutes_Val_ro_toS(_m->FIU_Sched_StartTimeMinutes_Val_phys); + _m->FIU_Sched_EndTimeMinutes_Val_ro = (uint8_t) CANDB_FIU_Sched_EndTimeMinutes_Val_ro_toS(_m->FIU_Sched_EndTimeMinutes_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->FIU_ArmrestHeatFL_Req & (0x01U)) | ((_m->FIU_ArmrestHeatFR_Req & (0x01U)) << 1U) | ((_m->FIU_ArmrestHeatRL_Req & (0x01U)) << 2U) | ((_m->FIU_ArmrestHeatRR_Req & (0x01U)) << 3U) | ((_m->FIU_FL_Synx_Req & (0x03U)) << 4U) | ((_m->FIU_FR_Synx_Req & (0x03U)) << 6U) ); + _d[1] |= (uint8_t) ( (_m->FIU_RL_Synx_Req & (0x03U)) | ((_m->FIU_RR_Synx_Req & (0x03U)) << 2U) | ((_m->FIU_SchedTue_Stat & (0x01U)) << 4U) | ((_m->FIU_SchedWed_Stat & (0x01U)) << 5U) | ((_m->FIU_SchedThu_Stat & (0x01U)) << 6U) | ((_m->FIU_SchedFri_Stat & (0x01U)) << 7U) ); + _d[2] |= (uint8_t) ( (_m->FIU_ICimage_Req & (0x03U)) | ((_m->FIU_ProjectionOnRoad_Req & (0x01U)) << 2U) | ((_m->FIU_RearSideWindowsElcrome_Req & (0x03U)) << 3U) | ((_m->FIU_ProjectionRoadSigns_Req & (0x01U)) << 5U) | ((_m->FIU_ProjectionNavigation_Req & (0x01U)) << 6U) | ((_m->FIU_ProjectionLiveObj_Req & (0x01U)) << 7U) ); + _d[3] |= (uint8_t) ( (_m->FIU_SchedSat_Stat & (0x01U)) | ((_m->FIU_SchedSu_Stat & (0x01U)) << 1U) | ((_m->FIU_Sched_StartTimeHours_Val & (0x1FU)) << 2U) | ((_m->FIU_SchedStart_Stat & (0x01U)) << 7U) ); + _d[4] |= (uint8_t) ( (_m->FIU_ChrgLim_Val & (0x07U)) | ((_m->FIU_DischrgLim_Val & (0x07U)) << 3U) | ((_m->FIU_ReduceChrgCurr_Stat & (0x01U)) << 6U) | ((_m->FIU_SchedMon_Stat & (0x01U)) << 7U) ); + _d[5] |= (uint8_t) ( (_m->FIU_Sched_StartTimeMinutes_Val_ro & (0x0FU)) | ((_m->FIU_Sched_EndTimeMinutes_Val_ro & (0x0FU)) << 4U) ); + _d[6] |= (uint8_t) ( (_m->FIU_Sched_EndTimeHours_Val & (0x1FU)) | ((_m->FIU_SchedEnd_Stat & (0x01U)) << 5U) | ((_m->FIU_PrepearClim_Stat & (0x01U)) << 6U) ); + + *_len = (uint8_t) FIU_Msg3_DLC; + *_ide = (uint8_t) FIU_Msg3_IDE; + return FIU_Msg3_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_EngMenu_candb(FIU_EngMenu_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->FIU_EngMenuTabLock_RL_Req = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->FIU_EngMenuTabLock_RR_Req = (uint8_t) ( ((_d[0] >> 1U) & (0x01U)) ); + _m->FIU_EngMenuTabLock_RC_Req = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < FIU_EngMenu_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_FIU_EngMenu_candb(&_m->mon1, FIU_EngMenu_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return FIU_EngMenu_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_FIU_EngMenu_candb(FIU_EngMenu_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_EngMenu_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->FIU_EngMenuTabLock_RL_Req & (0x01U)) | ((_m->FIU_EngMenuTabLock_RR_Req & (0x01U)) << 1U) | ((_m->FIU_EngMenuTabLock_RC_Req & (0x01U)) << 2U) ); + + cframe->MsgId = (uint32_t) FIU_EngMenu_CANID; + cframe->DLC = (uint8_t) FIU_EngMenu_DLC; + cframe->IDE = (uint8_t) FIU_EngMenu_IDE; + return FIU_EngMenu_CANID; +} + +#else + +uint32_t Pack_FIU_EngMenu_candb(FIU_EngMenu_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_EngMenu_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->FIU_EngMenuTabLock_RL_Req & (0x01U)) | ((_m->FIU_EngMenuTabLock_RR_Req & (0x01U)) << 1U) | ((_m->FIU_EngMenuTabLock_RC_Req & (0x01U)) << 2U) ); + + *_len = (uint8_t) FIU_EngMenu_DLC; + *_ide = (uint8_t) FIU_EngMenu_IDE; + return FIU_EngMenu_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_WHFL_MSG1_candb(WHFL_MSG1_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->WHFL_PowerMode_Stat = (uint8_t) ( (_d[0] & (0x07U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < WHFL_MSG1_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_WHFL_MSG1_candb(&_m->mon1, WHFL_MSG1_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return WHFL_MSG1_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_WHFL_MSG1_candb(WHFL_MSG1_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(WHFL_MSG1_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->WHFL_PowerMode_Stat & (0x07U)) ); + + cframe->MsgId = (uint32_t) WHFL_MSG1_CANID; + cframe->DLC = (uint8_t) WHFL_MSG1_DLC; + cframe->IDE = (uint8_t) WHFL_MSG1_IDE; + return WHFL_MSG1_CANID; +} + +#else + +uint32_t Pack_WHFL_MSG1_candb(WHFL_MSG1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(WHFL_MSG1_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->WHFL_PowerMode_Stat & (0x07U)) ); + + *_len = (uint8_t) WHFL_MSG1_DLC; + *_ide = (uint8_t) WHFL_MSG1_IDE; + return WHFL_MSG1_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_WHFR_Msg1_candb(WHFR_Msg1_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->WHFR_PowerMode_Stat = (uint8_t) ( (_d[0] & (0x07U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < WHFR_Msg1_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_WHFR_Msg1_candb(&_m->mon1, WHFR_Msg1_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return WHFR_Msg1_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_WHFR_Msg1_candb(WHFR_Msg1_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(WHFR_Msg1_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->WHFR_PowerMode_Stat & (0x07U)) ); + + cframe->MsgId = (uint32_t) WHFR_Msg1_CANID; + cframe->DLC = (uint8_t) WHFR_Msg1_DLC; + cframe->IDE = (uint8_t) WHFR_Msg1_IDE; + return WHFR_Msg1_CANID; +} + +#else + +uint32_t Pack_WHFR_Msg1_candb(WHFR_Msg1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(WHFR_Msg1_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->WHFR_PowerMode_Stat & (0x07U)) ); + + *_len = (uint8_t) WHFR_Msg1_DLC; + *_ide = (uint8_t) WHFR_Msg1_IDE; + return WHFR_Msg1_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_PLDSilCU_State_candb(PLDSilCU_State_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->PLDSilCU_Module_Stat = (int8_t) __ext_sig__(( (_d[0] & (0x0FU)) ), 4); + _m->PLDSilCU_ModuleTemperature_Val = (int8_t) __ext_sig__(( ((_d[1] & (0x07U)) << 4U) | ((_d[0] >> 4U) & (0x0FU)) ), 7); + _m->PLDSilCU_reserved1 = (int8_t) __ext_sig__(( ((_d[1] >> 3U) & (0x1FU)) ), 5); + _m->PLDSilCU_reserved2 = (int8_t) __ext_sig__(( (_d[2] & (0xFFU)) ), 8); + _m->PLDSilCU_reserved3 = (int8_t) __ext_sig__(( (_d[3] & (0xFFU)) ), 8); + _m->PLDSilCU_reserved4 = (int8_t) __ext_sig__(( (_d[4] & (0xFFU)) ), 8); + _m->PLDSilCU_reserved5 = (int8_t) __ext_sig__(( (_d[5] & (0xFFU)) ), 8); + _m->PLDSilCU_reserved6 = (int8_t) __ext_sig__(( (_d[6] & (0xFFU)) ), 8); + _m->PLDSilCU_reserved7 = (int8_t) __ext_sig__(( (_d[7] & (0xFFU)) ), 8); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < PLDSilCU_State_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_PLDSilCU_State_candb(&_m->mon1, PLDSilCU_State_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return PLDSilCU_State_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_PLDSilCU_State_candb(PLDSilCU_State_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(PLDSilCU_State_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->PLDSilCU_Module_Stat & (0x0FU)) | ((_m->PLDSilCU_ModuleTemperature_Val & (0x0FU)) << 4U) ); + cframe->Data[1] |= (uint8_t) ( ((_m->PLDSilCU_ModuleTemperature_Val >> 4U) & (0x07U)) | ((_m->PLDSilCU_reserved1 & (0x1FU)) << 3U) ); + cframe->Data[2] |= (uint8_t) ( (_m->PLDSilCU_reserved2 & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->PLDSilCU_reserved3 & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->PLDSilCU_reserved4 & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->PLDSilCU_reserved5 & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->PLDSilCU_reserved6 & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->PLDSilCU_reserved7 & (0xFFU)) ); + + cframe->MsgId = (uint32_t) PLDSilCU_State_CANID; + cframe->DLC = (uint8_t) PLDSilCU_State_DLC; + cframe->IDE = (uint8_t) PLDSilCU_State_IDE; + return PLDSilCU_State_CANID; +} + +#else + +uint32_t Pack_PLDSilCU_State_candb(PLDSilCU_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(PLDSilCU_State_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->PLDSilCU_Module_Stat & (0x0FU)) | ((_m->PLDSilCU_ModuleTemperature_Val & (0x0FU)) << 4U) ); + _d[1] |= (uint8_t) ( ((_m->PLDSilCU_ModuleTemperature_Val >> 4U) & (0x07U)) | ((_m->PLDSilCU_reserved1 & (0x1FU)) << 3U) ); + _d[2] |= (uint8_t) ( (_m->PLDSilCU_reserved2 & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->PLDSilCU_reserved3 & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->PLDSilCU_reserved4 & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->PLDSilCU_reserved5 & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->PLDSilCU_reserved6 & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->PLDSilCU_reserved7 & (0xFFU)) ); + + *_len = (uint8_t) PLDSilCU_State_DLC; + *_ide = (uint8_t) PLDSilCU_State_IDE; + return PLDSilCU_State_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_PRDSilCU_State_candb(PRDSilCU_State_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->PRDSilCU_Module_Stat = (int8_t) __ext_sig__(( (_d[0] & (0x0FU)) ), 4); + _m->PRDSilCU_ModuleTemperature_Val = (int8_t) __ext_sig__(( ((_d[1] & (0x07U)) << 4U) | ((_d[0] >> 4U) & (0x0FU)) ), 7); + _m->PRDSilCU_reserved1 = (int8_t) __ext_sig__(( ((_d[1] >> 3U) & (0x1FU)) ), 5); + _m->PRDSilCU_reserved2 = (int8_t) __ext_sig__(( (_d[2] & (0xFFU)) ), 8); + _m->PRDSilCU_reserved3 = (int8_t) __ext_sig__(( (_d[3] & (0xFFU)) ), 8); + _m->PRDSilCU_reserved4 = (int8_t) __ext_sig__(( (_d[4] & (0xFFU)) ), 8); + _m->PRDSilCU_reserved5 = (int8_t) __ext_sig__(( (_d[5] & (0xFFU)) ), 8); + _m->PRDSilCU_reserved6 = (int8_t) __ext_sig__(( (_d[6] & (0xFFU)) ), 8); + _m->PRDSilCU_reserved7 = (int8_t) __ext_sig__(( (_d[7] & (0xFFU)) ), 8); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < PRDSilCU_State_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_PRDSilCU_State_candb(&_m->mon1, PRDSilCU_State_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return PRDSilCU_State_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_PRDSilCU_State_candb(PRDSilCU_State_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(PRDSilCU_State_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->PRDSilCU_Module_Stat & (0x0FU)) | ((_m->PRDSilCU_ModuleTemperature_Val & (0x0FU)) << 4U) ); + cframe->Data[1] |= (uint8_t) ( ((_m->PRDSilCU_ModuleTemperature_Val >> 4U) & (0x07U)) | ((_m->PRDSilCU_reserved1 & (0x1FU)) << 3U) ); + cframe->Data[2] |= (uint8_t) ( (_m->PRDSilCU_reserved2 & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->PRDSilCU_reserved3 & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->PRDSilCU_reserved4 & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->PRDSilCU_reserved5 & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->PRDSilCU_reserved6 & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->PRDSilCU_reserved7 & (0xFFU)) ); + + cframe->MsgId = (uint32_t) PRDSilCU_State_CANID; + cframe->DLC = (uint8_t) PRDSilCU_State_DLC; + cframe->IDE = (uint8_t) PRDSilCU_State_IDE; + return PRDSilCU_State_CANID; +} + +#else + +uint32_t Pack_PRDSilCU_State_candb(PRDSilCU_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(PRDSilCU_State_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->PRDSilCU_Module_Stat & (0x0FU)) | ((_m->PRDSilCU_ModuleTemperature_Val & (0x0FU)) << 4U) ); + _d[1] |= (uint8_t) ( ((_m->PRDSilCU_ModuleTemperature_Val >> 4U) & (0x07U)) | ((_m->PRDSilCU_reserved1 & (0x1FU)) << 3U) ); + _d[2] |= (uint8_t) ( (_m->PRDSilCU_reserved2 & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->PRDSilCU_reserved3 & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->PRDSilCU_reserved4 & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->PRDSilCU_reserved5 & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->PRDSilCU_reserved6 & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->PRDSilCU_reserved7 & (0xFFU)) ); + + *_len = (uint8_t) PRDSilCU_State_DLC; + *_ide = (uint8_t) PRDSilCU_State_IDE; + return PRDSilCU_State_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FLDSilCU_State_candb(FLDSilCU_State_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->FLDSilCU_Module_Stat = (int8_t) __ext_sig__(( (_d[0] & (0x0FU)) ), 4); + _m->FLDSilCU_ModuleTemperature_Val = (int8_t) __ext_sig__(( ((_d[1] & (0x07U)) << 4U) | ((_d[0] >> 4U) & (0x0FU)) ), 7); + _m->FLDSilCU_reserved1 = (int8_t) __ext_sig__(( ((_d[1] >> 3U) & (0x1FU)) ), 5); + _m->FLDSilCU_reserved2 = (int8_t) __ext_sig__(( (_d[2] & (0xFFU)) ), 8); + _m->FLDSilCU_reserved3 = (int8_t) __ext_sig__(( (_d[3] & (0xFFU)) ), 8); + _m->FLDSilCU_reserved4 = (int8_t) __ext_sig__(( (_d[4] & (0xFFU)) ), 8); + _m->FLDSilCU_reserved5 = (int8_t) __ext_sig__(( (_d[5] & (0xFFU)) ), 8); + _m->FLDSilCU_reserved6 = (int8_t) __ext_sig__(( (_d[6] & (0xFFU)) ), 8); + _m->FLDSilCU_reserved7 = (int8_t) __ext_sig__(( (_d[7] & (0xFFU)) ), 8); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < FLDSilCU_State_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_FLDSilCU_State_candb(&_m->mon1, FLDSilCU_State_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return FLDSilCU_State_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_FLDSilCU_State_candb(FLDSilCU_State_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FLDSilCU_State_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->FLDSilCU_Module_Stat & (0x0FU)) | ((_m->FLDSilCU_ModuleTemperature_Val & (0x0FU)) << 4U) ); + cframe->Data[1] |= (uint8_t) ( ((_m->FLDSilCU_ModuleTemperature_Val >> 4U) & (0x07U)) | ((_m->FLDSilCU_reserved1 & (0x1FU)) << 3U) ); + cframe->Data[2] |= (uint8_t) ( (_m->FLDSilCU_reserved2 & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->FLDSilCU_reserved3 & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->FLDSilCU_reserved4 & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->FLDSilCU_reserved5 & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->FLDSilCU_reserved6 & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->FLDSilCU_reserved7 & (0xFFU)) ); + + cframe->MsgId = (uint32_t) FLDSilCU_State_CANID; + cframe->DLC = (uint8_t) FLDSilCU_State_DLC; + cframe->IDE = (uint8_t) FLDSilCU_State_IDE; + return FLDSilCU_State_CANID; +} + +#else + +uint32_t Pack_FLDSilCU_State_candb(FLDSilCU_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FLDSilCU_State_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->FLDSilCU_Module_Stat & (0x0FU)) | ((_m->FLDSilCU_ModuleTemperature_Val & (0x0FU)) << 4U) ); + _d[1] |= (uint8_t) ( ((_m->FLDSilCU_ModuleTemperature_Val >> 4U) & (0x07U)) | ((_m->FLDSilCU_reserved1 & (0x1FU)) << 3U) ); + _d[2] |= (uint8_t) ( (_m->FLDSilCU_reserved2 & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->FLDSilCU_reserved3 & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->FLDSilCU_reserved4 & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->FLDSilCU_reserved5 & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->FLDSilCU_reserved6 & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->FLDSilCU_reserved7 & (0xFFU)) ); + + *_len = (uint8_t) FLDSilCU_State_DLC; + *_ide = (uint8_t) FLDSilCU_State_IDE; + return FLDSilCU_State_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FRDSilCU_State_candb(FRDSilCU_State_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->FRDSilCU_Module_Stat = (int8_t) __ext_sig__(( (_d[0] & (0x0FU)) ), 4); + _m->FRDSilCU_ModuleTemperature_Val = (int8_t) __ext_sig__(( ((_d[1] & (0x07U)) << 4U) | ((_d[0] >> 4U) & (0x0FU)) ), 7); + _m->FRDSilCU_reserved1 = (int8_t) __ext_sig__(( ((_d[1] >> 3U) & (0x1FU)) ), 5); + _m->FRDSilCU_reserved2 = (int8_t) __ext_sig__(( (_d[2] & (0xFFU)) ), 8); + _m->FRDSilCU_reserved3 = (int8_t) __ext_sig__(( (_d[3] & (0xFFU)) ), 8); + _m->FRDSilCU_reserved4 = (int8_t) __ext_sig__(( (_d[4] & (0xFFU)) ), 8); + _m->FRDSilCU_reserved5 = (int8_t) __ext_sig__(( (_d[5] & (0xFFU)) ), 8); + _m->FRDSilCU_reserved6 = (int8_t) __ext_sig__(( (_d[6] & (0xFFU)) ), 8); + _m->FRDSilCU_reserved7 = (int8_t) __ext_sig__(( (_d[7] & (0xFFU)) ), 8); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < FRDSilCU_State_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_FRDSilCU_State_candb(&_m->mon1, FRDSilCU_State_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return FRDSilCU_State_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_FRDSilCU_State_candb(FRDSilCU_State_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FRDSilCU_State_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->FRDSilCU_Module_Stat & (0x0FU)) | ((_m->FRDSilCU_ModuleTemperature_Val & (0x0FU)) << 4U) ); + cframe->Data[1] |= (uint8_t) ( ((_m->FRDSilCU_ModuleTemperature_Val >> 4U) & (0x07U)) | ((_m->FRDSilCU_reserved1 & (0x1FU)) << 3U) ); + cframe->Data[2] |= (uint8_t) ( (_m->FRDSilCU_reserved2 & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->FRDSilCU_reserved3 & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->FRDSilCU_reserved4 & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->FRDSilCU_reserved5 & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->FRDSilCU_reserved6 & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->FRDSilCU_reserved7 & (0xFFU)) ); + + cframe->MsgId = (uint32_t) FRDSilCU_State_CANID; + cframe->DLC = (uint8_t) FRDSilCU_State_DLC; + cframe->IDE = (uint8_t) FRDSilCU_State_IDE; + return FRDSilCU_State_CANID; +} + +#else + +uint32_t Pack_FRDSilCU_State_candb(FRDSilCU_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FRDSilCU_State_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->FRDSilCU_Module_Stat & (0x0FU)) | ((_m->FRDSilCU_ModuleTemperature_Val & (0x0FU)) << 4U) ); + _d[1] |= (uint8_t) ( ((_m->FRDSilCU_ModuleTemperature_Val >> 4U) & (0x07U)) | ((_m->FRDSilCU_reserved1 & (0x1FU)) << 3U) ); + _d[2] |= (uint8_t) ( (_m->FRDSilCU_reserved2 & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->FRDSilCU_reserved3 & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->FRDSilCU_reserved4 & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->FRDSilCU_reserved5 & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->FRDSilCU_reserved6 & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->FRDSilCU_reserved7 & (0xFFU)) ); + + *_len = (uint8_t) FRDSilCU_State_DLC; + *_ide = (uint8_t) FRDSilCU_State_IDE; + return FRDSilCU_State_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_RLDSilCU_State_candb(RLDSilCU_State_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->RLDSilCU_Module_Stat = (int8_t) __ext_sig__(( (_d[0] & (0x0FU)) ), 4); + _m->RLDSilCU_ModuleTemperature_Val = (int8_t) __ext_sig__(( ((_d[1] & (0x07U)) << 4U) | ((_d[0] >> 4U) & (0x0FU)) ), 7); + _m->RLDSilCU_reserved1 = (int8_t) __ext_sig__(( ((_d[1] >> 3U) & (0x1FU)) ), 5); + _m->RLDSilCU_reserved2 = (int8_t) __ext_sig__(( (_d[2] & (0xFFU)) ), 8); + _m->RLDSilCU_reserved3 = (int8_t) __ext_sig__(( (_d[3] & (0xFFU)) ), 8); + _m->RLDSilCU_reserved4 = (int8_t) __ext_sig__(( (_d[4] & (0xFFU)) ), 8); + _m->RLDSilCU_reserved5 = (int8_t) __ext_sig__(( (_d[5] & (0xFFU)) ), 8); + _m->RLDSilCU_reserved6 = (int8_t) __ext_sig__(( (_d[6] & (0xFFU)) ), 8); + _m->RLDSilCU_reserved7 = (int8_t) __ext_sig__(( (_d[7] & (0xFFU)) ), 8); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < RLDSilCU_State_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_RLDSilCU_State_candb(&_m->mon1, RLDSilCU_State_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return RLDSilCU_State_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_RLDSilCU_State_candb(RLDSilCU_State_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(RLDSilCU_State_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->RLDSilCU_Module_Stat & (0x0FU)) | ((_m->RLDSilCU_ModuleTemperature_Val & (0x0FU)) << 4U) ); + cframe->Data[1] |= (uint8_t) ( ((_m->RLDSilCU_ModuleTemperature_Val >> 4U) & (0x07U)) | ((_m->RLDSilCU_reserved1 & (0x1FU)) << 3U) ); + cframe->Data[2] |= (uint8_t) ( (_m->RLDSilCU_reserved2 & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->RLDSilCU_reserved3 & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->RLDSilCU_reserved4 & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->RLDSilCU_reserved5 & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->RLDSilCU_reserved6 & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->RLDSilCU_reserved7 & (0xFFU)) ); + + cframe->MsgId = (uint32_t) RLDSilCU_State_CANID; + cframe->DLC = (uint8_t) RLDSilCU_State_DLC; + cframe->IDE = (uint8_t) RLDSilCU_State_IDE; + return RLDSilCU_State_CANID; +} + +#else + +uint32_t Pack_RLDSilCU_State_candb(RLDSilCU_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(RLDSilCU_State_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->RLDSilCU_Module_Stat & (0x0FU)) | ((_m->RLDSilCU_ModuleTemperature_Val & (0x0FU)) << 4U) ); + _d[1] |= (uint8_t) ( ((_m->RLDSilCU_ModuleTemperature_Val >> 4U) & (0x07U)) | ((_m->RLDSilCU_reserved1 & (0x1FU)) << 3U) ); + _d[2] |= (uint8_t) ( (_m->RLDSilCU_reserved2 & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->RLDSilCU_reserved3 & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->RLDSilCU_reserved4 & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->RLDSilCU_reserved5 & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->RLDSilCU_reserved6 & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->RLDSilCU_reserved7 & (0xFFU)) ); + + *_len = (uint8_t) RLDSilCU_State_DLC; + *_ide = (uint8_t) RLDSilCU_State_IDE; + return RLDSilCU_State_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_RRDSilCU_State_candb(RRDSilCU_State_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->RRDSilCU_Module_Stat = (int8_t) __ext_sig__(( (_d[0] & (0x0FU)) ), 4); + _m->RRDSilCU_ModuleTemperature_Val = (int8_t) __ext_sig__(( ((_d[1] & (0x07U)) << 4U) | ((_d[0] >> 4U) & (0x0FU)) ), 7); + _m->RRDSilCU_reserved1 = (int8_t) __ext_sig__(( ((_d[1] >> 3U) & (0x1FU)) ), 5); + _m->RRDSilCU_reserved2 = (int8_t) __ext_sig__(( (_d[2] & (0xFFU)) ), 8); + _m->RRDSilCU_reserved3 = (int8_t) __ext_sig__(( (_d[3] & (0xFFU)) ), 8); + _m->RRDSilCU_reserved4 = (int8_t) __ext_sig__(( (_d[4] & (0xFFU)) ), 8); + _m->RRDSilCU_reserved5 = (int8_t) __ext_sig__(( (_d[5] & (0xFFU)) ), 8); + _m->RRDSilCU_reserved6 = (int8_t) __ext_sig__(( (_d[6] & (0xFFU)) ), 8); + _m->RRDSilCU_reserved7 = (int8_t) __ext_sig__(( (_d[7] & (0xFFU)) ), 8); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < RRDSilCU_State_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_RRDSilCU_State_candb(&_m->mon1, RRDSilCU_State_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return RRDSilCU_State_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_RRDSilCU_State_candb(RRDSilCU_State_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(RRDSilCU_State_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->RRDSilCU_Module_Stat & (0x0FU)) | ((_m->RRDSilCU_ModuleTemperature_Val & (0x0FU)) << 4U) ); + cframe->Data[1] |= (uint8_t) ( ((_m->RRDSilCU_ModuleTemperature_Val >> 4U) & (0x07U)) | ((_m->RRDSilCU_reserved1 & (0x1FU)) << 3U) ); + cframe->Data[2] |= (uint8_t) ( (_m->RRDSilCU_reserved2 & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->RRDSilCU_reserved3 & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->RRDSilCU_reserved4 & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->RRDSilCU_reserved5 & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->RRDSilCU_reserved6 & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->RRDSilCU_reserved7 & (0xFFU)) ); + + cframe->MsgId = (uint32_t) RRDSilCU_State_CANID; + cframe->DLC = (uint8_t) RRDSilCU_State_DLC; + cframe->IDE = (uint8_t) RRDSilCU_State_IDE; + return RRDSilCU_State_CANID; +} + +#else + +uint32_t Pack_RRDSilCU_State_candb(RRDSilCU_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(RRDSilCU_State_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->RRDSilCU_Module_Stat & (0x0FU)) | ((_m->RRDSilCU_ModuleTemperature_Val & (0x0FU)) << 4U) ); + _d[1] |= (uint8_t) ( ((_m->RRDSilCU_ModuleTemperature_Val >> 4U) & (0x07U)) | ((_m->RRDSilCU_reserved1 & (0x1FU)) << 3U) ); + _d[2] |= (uint8_t) ( (_m->RRDSilCU_reserved2 & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->RRDSilCU_reserved3 & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->RRDSilCU_reserved4 & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->RRDSilCU_reserved5 & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->RRDSilCU_reserved6 & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->RRDSilCU_reserved7 & (0xFFU)) ); + + *_len = (uint8_t) RRDSilCU_State_DLC; + *_ide = (uint8_t) RRDSilCU_State_IDE; + return RRDSilCU_State_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_CCU1_candb(FIU_CCU1_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->FIU_TargetTempFL_Val_ro = (uint8_t) ( (_d[0] & (0x1FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->FIU_TargetTempFL_Val_phys = (sigfloat_t)(CANDB_FIU_TargetTempFL_Val_ro_fromS(_m->FIU_TargetTempFL_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->FIU_FootTempCorFL_Req = (uint8_t) ( ((_d[0] >> 5U) & (0x07U)) ); + _m->FIU_TargetTempFR_Val_ro = (uint8_t) ( (_d[1] & (0x1FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->FIU_TargetTempFR_Val_phys = (sigfloat_t)(CANDB_FIU_TargetTempFR_Val_ro_fromS(_m->FIU_TargetTempFR_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->FIU_FootTempCorFR_Req = (uint8_t) ( ((_d[1] >> 5U) & (0x07U)) ); + _m->FIU_CCmodeFL_Req = (uint8_t) ( (_d[2] & (0x03U)) ); + _m->FIU_AirDirectionFL_Def_Req = (uint8_t) ( ((_d[2] >> 2U) & (0x03U)) ); + _m->FIU_AirDirectionFL_Face_Req = (uint8_t) ( ((_d[2] >> 4U) & (0x03U)) ); + _m->FIU_AirDirectionFL_Foot_Req = (uint8_t) ( ((_d[2] >> 6U) & (0x03U)) ); + _m->FIU_CCmodeFR_Req = (uint8_t) ( (_d[3] & (0x03U)) ); + _m->FIU_AirDirectionFR_Def_Req = (uint8_t) ( ((_d[3] >> 2U) & (0x03U)) ); + _m->FIU_AirDirectionFR_Face_Req = (uint8_t) ( ((_d[3] >> 4U) & (0x03U)) ); + _m->FIU_AirDirectionFR_Foot_Req = (uint8_t) ( ((_d[3] >> 6U) & (0x03U)) ); + _m->FIU_BlowerSpeedFL_Req = (uint8_t) ( (_d[4] & (0x0FU)) ); + _m->FIU_BlowerSpeedFR_Req = (uint8_t) ( ((_d[4] >> 4U) & (0x0FU)) ); + _m->FIU_CCautoModeFL_Req = (uint8_t) ( (_d[5] & (0x07U)) ); + _m->FIU_CCautoModeFR_Req = (uint8_t) ( ((_d[5] >> 3U) & (0x07U)) ); + _m->FIU_Recirculation_Req = (uint8_t) ( ((_d[5] >> 6U) & (0x03U)) ); + _m->FIU_DeflectorSwDL_Req = (uint8_t) ( (_d[6] & (0x07U)) ); + _m->FIU_DeflectorSwDR_Req = (uint8_t) ( ((_d[6] >> 3U) & (0x07U)) ); + _m->FIU_ACfrontOFF_Req = (uint8_t) ( ((_d[6] >> 6U) & (0x03U)) ); + _m->FIU_DeflectorSwFPL_Req = (uint8_t) ( (_d[7] & (0x07U)) ); + _m->FIU_DeflectorSwFPR_Req = (uint8_t) ( ((_d[7] >> 3U) & (0x07U)) ); + _m->FIU_FrontZoneSync_Req = (uint8_t) ( ((_d[7] >> 6U) & (0x03U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < FIU_CCU1_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_FIU_CCU1_candb(&_m->mon1, FIU_CCU1_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return FIU_CCU1_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_FIU_CCU1_candb(FIU_CCU1_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_CCU1_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->FIU_TargetTempFL_Val_ro = (uint8_t) CANDB_FIU_TargetTempFL_Val_ro_toS(_m->FIU_TargetTempFL_Val_phys); + _m->FIU_TargetTempFR_Val_ro = (uint8_t) CANDB_FIU_TargetTempFR_Val_ro_toS(_m->FIU_TargetTempFR_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->FIU_TargetTempFL_Val_ro & (0x1FU)) | ((_m->FIU_FootTempCorFL_Req & (0x07U)) << 5U) ); + cframe->Data[1] |= (uint8_t) ( (_m->FIU_TargetTempFR_Val_ro & (0x1FU)) | ((_m->FIU_FootTempCorFR_Req & (0x07U)) << 5U) ); + cframe->Data[2] |= (uint8_t) ( (_m->FIU_CCmodeFL_Req & (0x03U)) | ((_m->FIU_AirDirectionFL_Def_Req & (0x03U)) << 2U) | ((_m->FIU_AirDirectionFL_Face_Req & (0x03U)) << 4U) | ((_m->FIU_AirDirectionFL_Foot_Req & (0x03U)) << 6U) ); + cframe->Data[3] |= (uint8_t) ( (_m->FIU_CCmodeFR_Req & (0x03U)) | ((_m->FIU_AirDirectionFR_Def_Req & (0x03U)) << 2U) | ((_m->FIU_AirDirectionFR_Face_Req & (0x03U)) << 4U) | ((_m->FIU_AirDirectionFR_Foot_Req & (0x03U)) << 6U) ); + cframe->Data[4] |= (uint8_t) ( (_m->FIU_BlowerSpeedFL_Req & (0x0FU)) | ((_m->FIU_BlowerSpeedFR_Req & (0x0FU)) << 4U) ); + cframe->Data[5] |= (uint8_t) ( (_m->FIU_CCautoModeFL_Req & (0x07U)) | ((_m->FIU_CCautoModeFR_Req & (0x07U)) << 3U) | ((_m->FIU_Recirculation_Req & (0x03U)) << 6U) ); + cframe->Data[6] |= (uint8_t) ( (_m->FIU_DeflectorSwDL_Req & (0x07U)) | ((_m->FIU_DeflectorSwDR_Req & (0x07U)) << 3U) | ((_m->FIU_ACfrontOFF_Req & (0x03U)) << 6U) ); + cframe->Data[7] |= (uint8_t) ( (_m->FIU_DeflectorSwFPL_Req & (0x07U)) | ((_m->FIU_DeflectorSwFPR_Req & (0x07U)) << 3U) | ((_m->FIU_FrontZoneSync_Req & (0x03U)) << 6U) ); + + cframe->MsgId = (uint32_t) FIU_CCU1_CANID; + cframe->DLC = (uint8_t) FIU_CCU1_DLC; + cframe->IDE = (uint8_t) FIU_CCU1_IDE; + return FIU_CCU1_CANID; +} + +#else + +uint32_t Pack_FIU_CCU1_candb(FIU_CCU1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_CCU1_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->FIU_TargetTempFL_Val_ro = (uint8_t) CANDB_FIU_TargetTempFL_Val_ro_toS(_m->FIU_TargetTempFL_Val_phys); + _m->FIU_TargetTempFR_Val_ro = (uint8_t) CANDB_FIU_TargetTempFR_Val_ro_toS(_m->FIU_TargetTempFR_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->FIU_TargetTempFL_Val_ro & (0x1FU)) | ((_m->FIU_FootTempCorFL_Req & (0x07U)) << 5U) ); + _d[1] |= (uint8_t) ( (_m->FIU_TargetTempFR_Val_ro & (0x1FU)) | ((_m->FIU_FootTempCorFR_Req & (0x07U)) << 5U) ); + _d[2] |= (uint8_t) ( (_m->FIU_CCmodeFL_Req & (0x03U)) | ((_m->FIU_AirDirectionFL_Def_Req & (0x03U)) << 2U) | ((_m->FIU_AirDirectionFL_Face_Req & (0x03U)) << 4U) | ((_m->FIU_AirDirectionFL_Foot_Req & (0x03U)) << 6U) ); + _d[3] |= (uint8_t) ( (_m->FIU_CCmodeFR_Req & (0x03U)) | ((_m->FIU_AirDirectionFR_Def_Req & (0x03U)) << 2U) | ((_m->FIU_AirDirectionFR_Face_Req & (0x03U)) << 4U) | ((_m->FIU_AirDirectionFR_Foot_Req & (0x03U)) << 6U) ); + _d[4] |= (uint8_t) ( (_m->FIU_BlowerSpeedFL_Req & (0x0FU)) | ((_m->FIU_BlowerSpeedFR_Req & (0x0FU)) << 4U) ); + _d[5] |= (uint8_t) ( (_m->FIU_CCautoModeFL_Req & (0x07U)) | ((_m->FIU_CCautoModeFR_Req & (0x07U)) << 3U) | ((_m->FIU_Recirculation_Req & (0x03U)) << 6U) ); + _d[6] |= (uint8_t) ( (_m->FIU_DeflectorSwDL_Req & (0x07U)) | ((_m->FIU_DeflectorSwDR_Req & (0x07U)) << 3U) | ((_m->FIU_ACfrontOFF_Req & (0x03U)) << 6U) ); + _d[7] |= (uint8_t) ( (_m->FIU_DeflectorSwFPL_Req & (0x07U)) | ((_m->FIU_DeflectorSwFPR_Req & (0x07U)) << 3U) | ((_m->FIU_FrontZoneSync_Req & (0x03U)) << 6U) ); + + *_len = (uint8_t) FIU_CCU1_DLC; + *_ide = (uint8_t) FIU_CCU1_IDE; + return FIU_CCU1_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_CCU2_candb(FIU_CCU2_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->FIU_TargetTempRL_Val_ro = (uint8_t) ( (_d[0] & (0x1FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->FIU_TargetTempRL_Val_phys = (sigfloat_t)(CANDB_FIU_TargetTempRL_Val_ro_fromS(_m->FIU_TargetTempRL_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->FIU_FootTempCorRL_Req = (uint8_t) ( ((_d[0] >> 5U) & (0x07U)) ); + _m->FIU_TargetTempRR_Val_ro = (uint8_t) ( (_d[1] & (0x1FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->FIU_TargetTempRR_Val_phys = (sigfloat_t)(CANDB_FIU_TargetTempRR_Val_ro_fromS(_m->FIU_TargetTempRR_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->FIU_FootTempCorRR_Req = (uint8_t) ( ((_d[1] >> 5U) & (0x07U)) ); + _m->FIU_CCmodeRL_Req = (uint8_t) ( (_d[2] & (0x03U)) ); + _m->FIU_AirDirectionRL_Def_Req = (uint8_t) ( ((_d[2] >> 2U) & (0x03U)) ); + _m->FIU_AirDirectionRL_Face_Req = (uint8_t) ( ((_d[2] >> 4U) & (0x03U)) ); + _m->FIU_AirDirectionRL_Foot_Req = (uint8_t) ( ((_d[2] >> 6U) & (0x03U)) ); + _m->FIU_CCmodeRR_Req = (uint8_t) ( (_d[3] & (0x03U)) ); + _m->FIU_AirDirectionRR_Def_Req = (uint8_t) ( ((_d[3] >> 2U) & (0x03U)) ); + _m->FIU_AirDirectionRR_Face_Req = (uint8_t) ( ((_d[3] >> 4U) & (0x03U)) ); + _m->FIU_AirDirectionRR_Foot_Req = (uint8_t) ( ((_d[3] >> 6U) & (0x03U)) ); + _m->FIU_BlowerSpeedRL_Req = (uint8_t) ( (_d[4] & (0x0FU)) ); + _m->FIU_BlowerSpeedRR_Req = (uint8_t) ( ((_d[4] >> 4U) & (0x0FU)) ); + _m->FIU_CCautoModeRL_Req = (uint8_t) ( (_d[5] & (0x07U)) ); + _m->FIU_CCautoModeRR_Req = (uint8_t) ( ((_d[5] >> 3U) & (0x07U)) ); + _m->FIU_DeflectorSwRLB_Req = (uint8_t) ( (_d[6] & (0x07U)) ); + _m->FIU_DeflectorSwFCL_Req = (uint8_t) ( ((_d[6] >> 3U) & (0x07U)) ); + _m->FIU_ACrearOFF_Req = (uint8_t) ( ((_d[6] >> 6U) & (0x03U)) ); + _m->FIU_DeflectorSwFCR_Req = (uint8_t) ( (_d[7] & (0x07U)) ); + _m->FIU_DeflectorSwRRB_Req = (uint8_t) ( ((_d[7] >> 3U) & (0x07U)) ); + _m->FIU_RearZoneSync_Req = (uint8_t) ( ((_d[7] >> 6U) & (0x03U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < FIU_CCU2_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_FIU_CCU2_candb(&_m->mon1, FIU_CCU2_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return FIU_CCU2_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_FIU_CCU2_candb(FIU_CCU2_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_CCU2_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->FIU_TargetTempRL_Val_ro = (uint8_t) CANDB_FIU_TargetTempRL_Val_ro_toS(_m->FIU_TargetTempRL_Val_phys); + _m->FIU_TargetTempRR_Val_ro = (uint8_t) CANDB_FIU_TargetTempRR_Val_ro_toS(_m->FIU_TargetTempRR_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->FIU_TargetTempRL_Val_ro & (0x1FU)) | ((_m->FIU_FootTempCorRL_Req & (0x07U)) << 5U) ); + cframe->Data[1] |= (uint8_t) ( (_m->FIU_TargetTempRR_Val_ro & (0x1FU)) | ((_m->FIU_FootTempCorRR_Req & (0x07U)) << 5U) ); + cframe->Data[2] |= (uint8_t) ( (_m->FIU_CCmodeRL_Req & (0x03U)) | ((_m->FIU_AirDirectionRL_Def_Req & (0x03U)) << 2U) | ((_m->FIU_AirDirectionRL_Face_Req & (0x03U)) << 4U) | ((_m->FIU_AirDirectionRL_Foot_Req & (0x03U)) << 6U) ); + cframe->Data[3] |= (uint8_t) ( (_m->FIU_CCmodeRR_Req & (0x03U)) | ((_m->FIU_AirDirectionRR_Def_Req & (0x03U)) << 2U) | ((_m->FIU_AirDirectionRR_Face_Req & (0x03U)) << 4U) | ((_m->FIU_AirDirectionRR_Foot_Req & (0x03U)) << 6U) ); + cframe->Data[4] |= (uint8_t) ( (_m->FIU_BlowerSpeedRL_Req & (0x0FU)) | ((_m->FIU_BlowerSpeedRR_Req & (0x0FU)) << 4U) ); + cframe->Data[5] |= (uint8_t) ( (_m->FIU_CCautoModeRL_Req & (0x07U)) | ((_m->FIU_CCautoModeRR_Req & (0x07U)) << 3U) ); + cframe->Data[6] |= (uint8_t) ( (_m->FIU_DeflectorSwRLB_Req & (0x07U)) | ((_m->FIU_DeflectorSwFCL_Req & (0x07U)) << 3U) | ((_m->FIU_ACrearOFF_Req & (0x03U)) << 6U) ); + cframe->Data[7] |= (uint8_t) ( (_m->FIU_DeflectorSwFCR_Req & (0x07U)) | ((_m->FIU_DeflectorSwRRB_Req & (0x07U)) << 3U) | ((_m->FIU_RearZoneSync_Req & (0x03U)) << 6U) ); + + cframe->MsgId = (uint32_t) FIU_CCU2_CANID; + cframe->DLC = (uint8_t) FIU_CCU2_DLC; + cframe->IDE = (uint8_t) FIU_CCU2_IDE; + return FIU_CCU2_CANID; +} + +#else + +uint32_t Pack_FIU_CCU2_candb(FIU_CCU2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_CCU2_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->FIU_TargetTempRL_Val_ro = (uint8_t) CANDB_FIU_TargetTempRL_Val_ro_toS(_m->FIU_TargetTempRL_Val_phys); + _m->FIU_TargetTempRR_Val_ro = (uint8_t) CANDB_FIU_TargetTempRR_Val_ro_toS(_m->FIU_TargetTempRR_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->FIU_TargetTempRL_Val_ro & (0x1FU)) | ((_m->FIU_FootTempCorRL_Req & (0x07U)) << 5U) ); + _d[1] |= (uint8_t) ( (_m->FIU_TargetTempRR_Val_ro & (0x1FU)) | ((_m->FIU_FootTempCorRR_Req & (0x07U)) << 5U) ); + _d[2] |= (uint8_t) ( (_m->FIU_CCmodeRL_Req & (0x03U)) | ((_m->FIU_AirDirectionRL_Def_Req & (0x03U)) << 2U) | ((_m->FIU_AirDirectionRL_Face_Req & (0x03U)) << 4U) | ((_m->FIU_AirDirectionRL_Foot_Req & (0x03U)) << 6U) ); + _d[3] |= (uint8_t) ( (_m->FIU_CCmodeRR_Req & (0x03U)) | ((_m->FIU_AirDirectionRR_Def_Req & (0x03U)) << 2U) | ((_m->FIU_AirDirectionRR_Face_Req & (0x03U)) << 4U) | ((_m->FIU_AirDirectionRR_Foot_Req & (0x03U)) << 6U) ); + _d[4] |= (uint8_t) ( (_m->FIU_BlowerSpeedRL_Req & (0x0FU)) | ((_m->FIU_BlowerSpeedRR_Req & (0x0FU)) << 4U) ); + _d[5] |= (uint8_t) ( (_m->FIU_CCautoModeRL_Req & (0x07U)) | ((_m->FIU_CCautoModeRR_Req & (0x07U)) << 3U) ); + _d[6] |= (uint8_t) ( (_m->FIU_DeflectorSwRLB_Req & (0x07U)) | ((_m->FIU_DeflectorSwFCL_Req & (0x07U)) << 3U) | ((_m->FIU_ACrearOFF_Req & (0x03U)) << 6U) ); + _d[7] |= (uint8_t) ( (_m->FIU_DeflectorSwFCR_Req & (0x07U)) | ((_m->FIU_DeflectorSwRRB_Req & (0x07U)) << 3U) | ((_m->FIU_RearZoneSync_Req & (0x03U)) << 6U) ); + + *_len = (uint8_t) FIU_CCU2_DLC; + *_ide = (uint8_t) FIU_CCU2_IDE; + return FIU_CCU2_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_CCU3_candb(FIU_CCU3_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->FIU_Aroma_Req = (uint8_t) ( (_d[0] & (0x03U)) ); + _m->FIU_AromaIntens_Req = (uint8_t) ( ((_d[0] >> 2U) & (0x03U)) ); + _m->FIU_Rest_Req = (uint8_t) ( ((_d[0] >> 4U) & (0x03U)) ); + _m->FIU_Ionization_Req = (uint8_t) ( ((_d[0] >> 6U) & (0x03U)) ); + _m->FIU_RLfootBlowDis_Req = (uint8_t) ( (_d[1] & (0x03U)) ); + _m->FIU_RRfootBlowDis_Req = (uint8_t) ( ((_d[1] >> 2U) & (0x03U)) ); + _m->FIU_ACmax_Req = (uint8_t) ( ((_d[1] >> 4U) & (0x03U)) ); + _m->FIU_Defrost_Req = (uint8_t) ( ((_d[1] >> 6U) & (0x03U)) ); + _m->FIU_Ultraviolet_Req = (uint8_t) ( (_d[2] & (0x03U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < FIU_CCU3_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_FIU_CCU3_candb(&_m->mon1, FIU_CCU3_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return FIU_CCU3_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_FIU_CCU3_candb(FIU_CCU3_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_CCU3_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->FIU_Aroma_Req & (0x03U)) | ((_m->FIU_AromaIntens_Req & (0x03U)) << 2U) | ((_m->FIU_Rest_Req & (0x03U)) << 4U) | ((_m->FIU_Ionization_Req & (0x03U)) << 6U) ); + cframe->Data[1] |= (uint8_t) ( (_m->FIU_RLfootBlowDis_Req & (0x03U)) | ((_m->FIU_RRfootBlowDis_Req & (0x03U)) << 2U) | ((_m->FIU_ACmax_Req & (0x03U)) << 4U) | ((_m->FIU_Defrost_Req & (0x03U)) << 6U) ); + cframe->Data[2] |= (uint8_t) ( (_m->FIU_Ultraviolet_Req & (0x03U)) ); + + cframe->MsgId = (uint32_t) FIU_CCU3_CANID; + cframe->DLC = (uint8_t) FIU_CCU3_DLC; + cframe->IDE = (uint8_t) FIU_CCU3_IDE; + return FIU_CCU3_CANID; +} + +#else + +uint32_t Pack_FIU_CCU3_candb(FIU_CCU3_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_CCU3_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->FIU_Aroma_Req & (0x03U)) | ((_m->FIU_AromaIntens_Req & (0x03U)) << 2U) | ((_m->FIU_Rest_Req & (0x03U)) << 4U) | ((_m->FIU_Ionization_Req & (0x03U)) << 6U) ); + _d[1] |= (uint8_t) ( (_m->FIU_RLfootBlowDis_Req & (0x03U)) | ((_m->FIU_RRfootBlowDis_Req & (0x03U)) << 2U) | ((_m->FIU_ACmax_Req & (0x03U)) << 4U) | ((_m->FIU_Defrost_Req & (0x03U)) << 6U) ); + _d[2] |= (uint8_t) ( (_m->FIU_Ultraviolet_Req & (0x03U)) ); + + *_len = (uint8_t) FIU_CCU3_DLC; + *_ide = (uint8_t) FIU_CCU3_IDE; + return FIU_CCU3_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_StyleCmd2_candb(BCM_StyleCmd2_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->BCM_Script_play_Req = (uint8_t) ( (_d[0] & (0x3FU)) ); + _m->BCM_StartPosition_Req = (uint8_t) ( ((_d[1] & (0x01U)) << 2U) | ((_d[0] >> 6U) & (0x03U)) ); + _m->BCM_MiddlePosition_Req = (uint8_t) ( ((_d[1] >> 1U) & (0x07U)) ); + _m->BCM_EndPosition_Req = (uint8_t) ( ((_d[1] >> 4U) & (0x07U)) ); + _m->BCM_ColorConfiguration_Stat = (uint8_t) ( ((_d[2] & (0x03U)) << 1U) | ((_d[1] >> 7U) & (0x01U)) ); + _m->BCM_Color_Width_Val_ro = (uint8_t) ( ((_d[3] & (0x03U)) << 6U) | ((_d[2] >> 2U) & (0x3FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_Color_Width_Val_phys = (sigfloat_t)(CANDB_BCM_Color_Width_Val_ro_fromS(_m->BCM_Color_Width_Val_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_RedColorParameter_Val = (uint8_t) ( ((_d[4] & (0x03U)) << 6U) | ((_d[3] >> 2U) & (0x3FU)) ); + _m->BCM_GreenColorParameter_Val = (uint8_t) ( ((_d[5] & (0x03U)) << 6U) | ((_d[4] >> 2U) & (0x3FU)) ); + _m->BCM_BlueColorParameter_Val = (uint8_t) ( ((_d[6] & (0x03U)) << 6U) | ((_d[5] >> 2U) & (0x3FU)) ); + _m->BCM_WhiteColorParameter_Val = (uint8_t) ( ((_d[7] & (0x03U)) << 6U) | ((_d[6] >> 2U) & (0x3FU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < BCM_StyleCmd2_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_BCM_StyleCmd2_candb(&_m->mon1, BCM_StyleCmd2_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return BCM_StyleCmd2_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_BCM_StyleCmd2_candb(BCM_StyleCmd2_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_StyleCmd2_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_Color_Width_Val_ro = (uint8_t) CANDB_BCM_Color_Width_Val_ro_toS(_m->BCM_Color_Width_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->BCM_Script_play_Req & (0x3FU)) | ((_m->BCM_StartPosition_Req & (0x03U)) << 6U) ); + cframe->Data[1] |= (uint8_t) ( ((_m->BCM_StartPosition_Req >> 2U) & (0x01U)) | ((_m->BCM_MiddlePosition_Req & (0x07U)) << 1U) | ((_m->BCM_EndPosition_Req & (0x07U)) << 4U) | ((_m->BCM_ColorConfiguration_Stat & (0x01U)) << 7U) ); + cframe->Data[2] |= (uint8_t) ( ((_m->BCM_ColorConfiguration_Stat >> 1U) & (0x03U)) | ((_m->BCM_Color_Width_Val_ro & (0x3FU)) << 2U) ); + cframe->Data[3] |= (uint8_t) ( ((_m->BCM_Color_Width_Val_ro >> 6U) & (0x03U)) | ((_m->BCM_RedColorParameter_Val & (0x3FU)) << 2U) ); + cframe->Data[4] |= (uint8_t) ( ((_m->BCM_RedColorParameter_Val >> 6U) & (0x03U)) | ((_m->BCM_GreenColorParameter_Val & (0x3FU)) << 2U) ); + cframe->Data[5] |= (uint8_t) ( ((_m->BCM_GreenColorParameter_Val >> 6U) & (0x03U)) | ((_m->BCM_BlueColorParameter_Val & (0x3FU)) << 2U) ); + cframe->Data[6] |= (uint8_t) ( ((_m->BCM_BlueColorParameter_Val >> 6U) & (0x03U)) | ((_m->BCM_WhiteColorParameter_Val & (0x3FU)) << 2U) ); + cframe->Data[7] |= (uint8_t) ( ((_m->BCM_WhiteColorParameter_Val >> 6U) & (0x03U)) ); + + cframe->MsgId = (uint32_t) BCM_StyleCmd2_CANID; + cframe->DLC = (uint8_t) BCM_StyleCmd2_DLC; + cframe->IDE = (uint8_t) BCM_StyleCmd2_IDE; + return BCM_StyleCmd2_CANID; +} + +#else + +uint32_t Pack_BCM_StyleCmd2_candb(BCM_StyleCmd2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_StyleCmd2_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_Color_Width_Val_ro = (uint8_t) CANDB_BCM_Color_Width_Val_ro_toS(_m->BCM_Color_Width_Val_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->BCM_Script_play_Req & (0x3FU)) | ((_m->BCM_StartPosition_Req & (0x03U)) << 6U) ); + _d[1] |= (uint8_t) ( ((_m->BCM_StartPosition_Req >> 2U) & (0x01U)) | ((_m->BCM_MiddlePosition_Req & (0x07U)) << 1U) | ((_m->BCM_EndPosition_Req & (0x07U)) << 4U) | ((_m->BCM_ColorConfiguration_Stat & (0x01U)) << 7U) ); + _d[2] |= (uint8_t) ( ((_m->BCM_ColorConfiguration_Stat >> 1U) & (0x03U)) | ((_m->BCM_Color_Width_Val_ro & (0x3FU)) << 2U) ); + _d[3] |= (uint8_t) ( ((_m->BCM_Color_Width_Val_ro >> 6U) & (0x03U)) | ((_m->BCM_RedColorParameter_Val & (0x3FU)) << 2U) ); + _d[4] |= (uint8_t) ( ((_m->BCM_RedColorParameter_Val >> 6U) & (0x03U)) | ((_m->BCM_GreenColorParameter_Val & (0x3FU)) << 2U) ); + _d[5] |= (uint8_t) ( ((_m->BCM_GreenColorParameter_Val >> 6U) & (0x03U)) | ((_m->BCM_BlueColorParameter_Val & (0x3FU)) << 2U) ); + _d[6] |= (uint8_t) ( ((_m->BCM_BlueColorParameter_Val >> 6U) & (0x03U)) | ((_m->BCM_WhiteColorParameter_Val & (0x3FU)) << 2U) ); + _d[7] |= (uint8_t) ( ((_m->BCM_WhiteColorParameter_Val >> 6U) & (0x03U)) ); + + *_len = (uint8_t) BCM_StyleCmd2_DLC; + *_ide = (uint8_t) BCM_StyleCmd2_IDE; + return BCM_StyleCmd2_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_StyleCmd3_candb(BCM_StyleCmd3_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->BCM_PlaceToPlay_Req = (uint8_t) ( (_d[0] & (0x03U)) ); + _m->BCM_TransModeOutScen_Req = (uint8_t) ( ((_d[0] >> 2U) & (0x1FU)) ); + _m->BCM_StartStopPlayTime_Req_ro = (uint8_t) ( ((_d[1] & (0x0FU)) << 1U) | ((_d[0] >> 7U) & (0x01U)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_StartStopPlayTime_Req_phys = (uint16_t) CANDB_BCM_StartStopPlayTime_Req_ro_fromS(_m->BCM_StartStopPlayTime_Req_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->BCM_Factorpurpose_Stat = (uint8_t) ( ((_d[1] >> 4U) & (0x03U)) ); + _m->BCM_FactorFunction_A_Val = (uint8_t) ( ((_d[2] & (0x3FU)) << 2U) | ((_d[1] >> 6U) & (0x03U)) ); + _m->BCM_FactorFunction_B_Val = (uint8_t) ( ((_d[3] & (0x3FU)) << 2U) | ((_d[2] >> 6U) & (0x03U)) ); + _m->BCM_FactorFunction_C_Val = (uint8_t) ( ((_d[4] & (0x3FU)) << 2U) | ((_d[3] >> 6U) & (0x03U)) ); + _m->BCM_Reserved6 = (uint8_t) ( ((_d[5] & (0x3FU)) << 2U) | ((_d[4] >> 6U) & (0x03U)) ); + _m->BCM_Reserved7 = (uint8_t) ( ((_d[6] & (0x3FU)) << 2U) | ((_d[5] >> 6U) & (0x03U)) ); + _m->BCM_Reserved8 = (uint8_t) ( ((_d[7] & (0x3FU)) << 2U) | ((_d[6] >> 6U) & (0x03U)) ); + _m->BCM_Reserved9 = (uint8_t) ( ((_d[7] >> 6U) & (0x01U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < BCM_StyleCmd3_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_BCM_StyleCmd3_candb(&_m->mon1, BCM_StyleCmd3_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return BCM_StyleCmd3_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_BCM_StyleCmd3_candb(BCM_StyleCmd3_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_StyleCmd3_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_StartStopPlayTime_Req_ro = (uint8_t) CANDB_BCM_StartStopPlayTime_Req_ro_toS(_m->BCM_StartStopPlayTime_Req_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->BCM_PlaceToPlay_Req & (0x03U)) | ((_m->BCM_TransModeOutScen_Req & (0x1FU)) << 2U) | ((_m->BCM_StartStopPlayTime_Req_ro & (0x01U)) << 7U) ); + cframe->Data[1] |= (uint8_t) ( ((_m->BCM_StartStopPlayTime_Req_ro >> 1U) & (0x0FU)) | ((_m->BCM_Factorpurpose_Stat & (0x03U)) << 4U) | ((_m->BCM_FactorFunction_A_Val & (0x03U)) << 6U) ); + cframe->Data[2] |= (uint8_t) ( ((_m->BCM_FactorFunction_A_Val >> 2U) & (0x3FU)) | ((_m->BCM_FactorFunction_B_Val & (0x03U)) << 6U) ); + cframe->Data[3] |= (uint8_t) ( ((_m->BCM_FactorFunction_B_Val >> 2U) & (0x3FU)) | ((_m->BCM_FactorFunction_C_Val & (0x03U)) << 6U) ); + cframe->Data[4] |= (uint8_t) ( ((_m->BCM_FactorFunction_C_Val >> 2U) & (0x3FU)) | ((_m->BCM_Reserved6 & (0x03U)) << 6U) ); + cframe->Data[5] |= (uint8_t) ( ((_m->BCM_Reserved6 >> 2U) & (0x3FU)) | ((_m->BCM_Reserved7 & (0x03U)) << 6U) ); + cframe->Data[6] |= (uint8_t) ( ((_m->BCM_Reserved7 >> 2U) & (0x3FU)) | ((_m->BCM_Reserved8 & (0x03U)) << 6U) ); + cframe->Data[7] |= (uint8_t) ( ((_m->BCM_Reserved8 >> 2U) & (0x3FU)) | ((_m->BCM_Reserved9 & (0x01U)) << 6U) ); + + cframe->MsgId = (uint32_t) BCM_StyleCmd3_CANID; + cframe->DLC = (uint8_t) BCM_StyleCmd3_DLC; + cframe->IDE = (uint8_t) BCM_StyleCmd3_IDE; + return BCM_StyleCmd3_CANID; +} + +#else + +uint32_t Pack_BCM_StyleCmd3_candb(BCM_StyleCmd3_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_StyleCmd3_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->BCM_StartStopPlayTime_Req_ro = (uint8_t) CANDB_BCM_StartStopPlayTime_Req_ro_toS(_m->BCM_StartStopPlayTime_Req_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->BCM_PlaceToPlay_Req & (0x03U)) | ((_m->BCM_TransModeOutScen_Req & (0x1FU)) << 2U) | ((_m->BCM_StartStopPlayTime_Req_ro & (0x01U)) << 7U) ); + _d[1] |= (uint8_t) ( ((_m->BCM_StartStopPlayTime_Req_ro >> 1U) & (0x0FU)) | ((_m->BCM_Factorpurpose_Stat & (0x03U)) << 4U) | ((_m->BCM_FactorFunction_A_Val & (0x03U)) << 6U) ); + _d[2] |= (uint8_t) ( ((_m->BCM_FactorFunction_A_Val >> 2U) & (0x3FU)) | ((_m->BCM_FactorFunction_B_Val & (0x03U)) << 6U) ); + _d[3] |= (uint8_t) ( ((_m->BCM_FactorFunction_B_Val >> 2U) & (0x3FU)) | ((_m->BCM_FactorFunction_C_Val & (0x03U)) << 6U) ); + _d[4] |= (uint8_t) ( ((_m->BCM_FactorFunction_C_Val >> 2U) & (0x3FU)) | ((_m->BCM_Reserved6 & (0x03U)) << 6U) ); + _d[5] |= (uint8_t) ( ((_m->BCM_Reserved6 >> 2U) & (0x3FU)) | ((_m->BCM_Reserved7 & (0x03U)) << 6U) ); + _d[6] |= (uint8_t) ( ((_m->BCM_Reserved7 >> 2U) & (0x3FU)) | ((_m->BCM_Reserved8 & (0x03U)) << 6U) ); + _d[7] |= (uint8_t) ( ((_m->BCM_Reserved8 >> 2U) & (0x3FU)) | ((_m->BCM_Reserved9 & (0x01U)) << 6U) ); + + *_len = (uint8_t) BCM_StyleCmd3_DLC; + *_ide = (uint8_t) BCM_StyleCmd3_IDE; + return BCM_StyleCmd3_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_WHF_Request_candb(BCM_WHF_Request_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->BCM_PowerWHF_Req = (uint8_t) ( (_d[0] & (0x07U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < BCM_WHF_Request_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_BCM_WHF_Request_candb(&_m->mon1, BCM_WHF_Request_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return BCM_WHF_Request_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_BCM_WHF_Request_candb(BCM_WHF_Request_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_WHF_Request_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->BCM_PowerWHF_Req & (0x07U)) ); + + cframe->MsgId = (uint32_t) BCM_WHF_Request_CANID; + cframe->DLC = (uint8_t) BCM_WHF_Request_DLC; + cframe->IDE = (uint8_t) BCM_WHF_Request_IDE; + return BCM_WHF_Request_CANID; +} + +#else + +uint32_t Pack_BCM_WHF_Request_candb(BCM_WHF_Request_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_WHF_Request_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->BCM_PowerWHF_Req & (0x07U)) ); + + *_len = (uint8_t) BCM_WHF_Request_DLC; + *_ide = (uint8_t) BCM_WHF_Request_IDE; + return BCM_WHF_Request_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_IC_DISPLAY_CLOCK_candb(IC_DISPLAY_CLOCK_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->IC_Year_ro = (uint8_t) ( (_d[0] & (0x7FU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->IC_Year_phys = (uint16_t) CANDB_IC_Year_ro_fromS(_m->IC_Year_ro); +#endif // CANDB_USE_SIGFLOAT + + _m->IC_Month = (uint8_t) ( (_d[1] & (0x0FU)) ); + _m->IC_Day = (uint8_t) ( (_d[2] & (0x1FU)) ); + _m->IC_Hour = (uint8_t) ( (_d[3] & (0x1FU)) ); + _m->IC_Minute = (uint8_t) ( (_d[4] & (0x3FU)) ); + _m->IC_Second = (uint8_t) ( (_d[5] & (0x3FU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < IC_DISPLAY_CLOCK_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_IC_DISPLAY_CLOCK_candb(&_m->mon1, IC_DISPLAY_CLOCK_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return IC_DISPLAY_CLOCK_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_IC_DISPLAY_CLOCK_candb(IC_DISPLAY_CLOCK_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(IC_DISPLAY_CLOCK_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->IC_Year_ro = (uint8_t) CANDB_IC_Year_ro_toS(_m->IC_Year_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->IC_Year_ro & (0x7FU)) ); + cframe->Data[1] |= (uint8_t) ( (_m->IC_Month & (0x0FU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->IC_Day & (0x1FU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->IC_Hour & (0x1FU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->IC_Minute & (0x3FU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->IC_Second & (0x3FU)) ); + + cframe->MsgId = (uint32_t) IC_DISPLAY_CLOCK_CANID; + cframe->DLC = (uint8_t) IC_DISPLAY_CLOCK_DLC; + cframe->IDE = (uint8_t) IC_DISPLAY_CLOCK_IDE; + return IC_DISPLAY_CLOCK_CANID; +} + +#else + +uint32_t Pack_IC_DISPLAY_CLOCK_candb(IC_DISPLAY_CLOCK_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(IC_DISPLAY_CLOCK_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->IC_Year_ro = (uint8_t) CANDB_IC_Year_ro_toS(_m->IC_Year_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->IC_Year_ro & (0x7FU)) ); + _d[1] |= (uint8_t) ( (_m->IC_Month & (0x0FU)) ); + _d[2] |= (uint8_t) ( (_m->IC_Day & (0x1FU)) ); + _d[3] |= (uint8_t) ( (_m->IC_Hour & (0x1FU)) ); + _d[4] |= (uint8_t) ( (_m->IC_Minute & (0x3FU)) ); + _d[5] |= (uint8_t) ( (_m->IC_Second & (0x3FU)) ); + + *_len = (uint8_t) IC_DISPLAY_CLOCK_DLC; + *_ide = (uint8_t) IC_DISPLAY_CLOCK_IDE; + return IC_DISPLAY_CLOCK_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_UserConfig_Stat_candb(BCM_UserConfig_Stat_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->BCM_StyleIllTheme_Stat = (uint8_t) ( (_d[1] & (0x0FU)) ); + _m->BCM_ConfCamera_Stat = (uint8_t) ( ((_d[1] >> 4U) & (0x03U)) ); + _m->BCM_FIU_UserNotification_Stat = (uint8_t) ( ((_d[1] >> 6U) & (0x03U)) ); + _m->BCM_StyleIllBright_Val = (uint8_t) ( (_d[2] & (0x7FU)) ); + _m->BCM_StyleIllGlobal_Stat = (uint8_t) ( ((_d[2] >> 7U) & (0x01U)) ); + _m->BCM_ApproachAccess_Stat = (uint8_t) ( (_d[3] & (0x01U)) ); + _m->BCM_UnlockAfterDrive_Stat = (uint8_t) ( ((_d[3] >> 1U) & (0x01U)) ); + _m->BCM_UnlockExternal_Stat = (uint8_t) ( ((_d[3] >> 2U) & (0x01U)) ); + _m->BCM_UnlockInternal_Stat = (uint8_t) ( ((_d[3] >> 3U) & (0x01U)) ); + _m->BCM_DoorsDriveLock_Stat = (uint8_t) ( ((_d[3] >> 4U) & (0x01U)) ); + _m->BCM_TrafficSide_Stat = (uint8_t) ( ((_d[3] >> 5U) & (0x01U)) ); + _m->BCM_WelcomeLeavingLight_Stat = (uint8_t) ( ((_d[3] >> 6U) & (0x01U)) ); + _m->BCM_WelcomeLightAnimation_Stat = (uint8_t) ( ((_d[3] >> 7U) & (0x01U)) ); + _m->BCM_ArmrestHeatFL_Stat = (uint8_t) ( (_d[4] & (0x01U)) ); + _m->BCM_ArmrestHeatFR_Stat = (uint8_t) ( ((_d[4] >> 1U) & (0x01U)) ); + _m->BCM_ArmrestHeatRL_Stat = (uint8_t) ( ((_d[4] >> 2U) & (0x01U)) ); + _m->BCM_ArmrestHeatRR_Stat = (uint8_t) ( ((_d[4] >> 3U) & (0x01U)) ); + _m->BCM_WelcomeLeavingLightTime_Stat = (uint8_t) ( ((_d[4] >> 4U) & (0x03U)) ); + _m->BCM_HeadlightWashing_Stat = (uint8_t) ( ((_d[4] >> 6U) & (0x01U)) ); + _m->BCM_MirrorsAutoFold_Stat = (uint8_t) ( ((_d[4] >> 7U) & (0x01U)) ); + _m->BCM_MirrorsAutoTilt_Stat = (uint8_t) ( (_d[5] & (0x01U)) ); + _m->BCM_WindowsRainClosing_Stat = (uint8_t) ( ((_d[5] >> 1U) & (0x01U)) ); + _m->BCM_AudibleLockFdBack_Stat = (uint8_t) ( ((_d[5] >> 2U) & (0x01U)) ); + _m->BCM_AutoWiper_Stat = (uint8_t) ( ((_d[5] >> 3U) & (0x01U)) ); + _m->BCM_TrnkDoorCloseBySpeed_Stat = (uint8_t) ( ((_d[5] >> 4U) & (0x01U)) ); + _m->BCM_RunningBoards_Stat = (uint8_t) ( ((_d[5] >> 5U) & (0x03U)) ); + _m->BCM_SteeringWheelAutoHeat_Stat = (uint8_t) ( ((_d[5] >> 7U) & (0x01U)) ); + _m->BCM_Ultraviolet_Stat = (uint8_t) ( (_d[6] & (0x01U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < BCM_UserConfig_Stat_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_BCM_UserConfig_Stat_candb(&_m->mon1, BCM_UserConfig_Stat_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return BCM_UserConfig_Stat_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_BCM_UserConfig_Stat_candb(BCM_UserConfig_Stat_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_UserConfig_Stat_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[1] |= (uint8_t) ( (_m->BCM_StyleIllTheme_Stat & (0x0FU)) | ((_m->BCM_ConfCamera_Stat & (0x03U)) << 4U) | ((_m->BCM_FIU_UserNotification_Stat & (0x03U)) << 6U) ); + cframe->Data[2] |= (uint8_t) ( (_m->BCM_StyleIllBright_Val & (0x7FU)) | ((_m->BCM_StyleIllGlobal_Stat & (0x01U)) << 7U) ); + cframe->Data[3] |= (uint8_t) ( (_m->BCM_ApproachAccess_Stat & (0x01U)) | ((_m->BCM_UnlockAfterDrive_Stat & (0x01U)) << 1U) | ((_m->BCM_UnlockExternal_Stat & (0x01U)) << 2U) | ((_m->BCM_UnlockInternal_Stat & (0x01U)) << 3U) | ((_m->BCM_DoorsDriveLock_Stat & (0x01U)) << 4U) | ((_m->BCM_TrafficSide_Stat & (0x01U)) << 5U) | ((_m->BCM_WelcomeLeavingLight_Stat & (0x01U)) << 6U) | ((_m->BCM_WelcomeLightAnimation_Stat & (0x01U)) << 7U) ); + cframe->Data[4] |= (uint8_t) ( (_m->BCM_ArmrestHeatFL_Stat & (0x01U)) | ((_m->BCM_ArmrestHeatFR_Stat & (0x01U)) << 1U) | ((_m->BCM_ArmrestHeatRL_Stat & (0x01U)) << 2U) | ((_m->BCM_ArmrestHeatRR_Stat & (0x01U)) << 3U) | ((_m->BCM_WelcomeLeavingLightTime_Stat & (0x03U)) << 4U) | ((_m->BCM_HeadlightWashing_Stat & (0x01U)) << 6U) | ((_m->BCM_MirrorsAutoFold_Stat & (0x01U)) << 7U) ); + cframe->Data[5] |= (uint8_t) ( (_m->BCM_MirrorsAutoTilt_Stat & (0x01U)) | ((_m->BCM_WindowsRainClosing_Stat & (0x01U)) << 1U) | ((_m->BCM_AudibleLockFdBack_Stat & (0x01U)) << 2U) | ((_m->BCM_AutoWiper_Stat & (0x01U)) << 3U) | ((_m->BCM_TrnkDoorCloseBySpeed_Stat & (0x01U)) << 4U) | ((_m->BCM_RunningBoards_Stat & (0x03U)) << 5U) | ((_m->BCM_SteeringWheelAutoHeat_Stat & (0x01U)) << 7U) ); + cframe->Data[6] |= (uint8_t) ( (_m->BCM_Ultraviolet_Stat & (0x01U)) ); + + cframe->MsgId = (uint32_t) BCM_UserConfig_Stat_CANID; + cframe->DLC = (uint8_t) BCM_UserConfig_Stat_DLC; + cframe->IDE = (uint8_t) BCM_UserConfig_Stat_IDE; + return BCM_UserConfig_Stat_CANID; +} + +#else + +uint32_t Pack_BCM_UserConfig_Stat_candb(BCM_UserConfig_Stat_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(BCM_UserConfig_Stat_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[1] |= (uint8_t) ( (_m->BCM_StyleIllTheme_Stat & (0x0FU)) | ((_m->BCM_ConfCamera_Stat & (0x03U)) << 4U) | ((_m->BCM_FIU_UserNotification_Stat & (0x03U)) << 6U) ); + _d[2] |= (uint8_t) ( (_m->BCM_StyleIllBright_Val & (0x7FU)) | ((_m->BCM_StyleIllGlobal_Stat & (0x01U)) << 7U) ); + _d[3] |= (uint8_t) ( (_m->BCM_ApproachAccess_Stat & (0x01U)) | ((_m->BCM_UnlockAfterDrive_Stat & (0x01U)) << 1U) | ((_m->BCM_UnlockExternal_Stat & (0x01U)) << 2U) | ((_m->BCM_UnlockInternal_Stat & (0x01U)) << 3U) | ((_m->BCM_DoorsDriveLock_Stat & (0x01U)) << 4U) | ((_m->BCM_TrafficSide_Stat & (0x01U)) << 5U) | ((_m->BCM_WelcomeLeavingLight_Stat & (0x01U)) << 6U) | ((_m->BCM_WelcomeLightAnimation_Stat & (0x01U)) << 7U) ); + _d[4] |= (uint8_t) ( (_m->BCM_ArmrestHeatFL_Stat & (0x01U)) | ((_m->BCM_ArmrestHeatFR_Stat & (0x01U)) << 1U) | ((_m->BCM_ArmrestHeatRL_Stat & (0x01U)) << 2U) | ((_m->BCM_ArmrestHeatRR_Stat & (0x01U)) << 3U) | ((_m->BCM_WelcomeLeavingLightTime_Stat & (0x03U)) << 4U) | ((_m->BCM_HeadlightWashing_Stat & (0x01U)) << 6U) | ((_m->BCM_MirrorsAutoFold_Stat & (0x01U)) << 7U) ); + _d[5] |= (uint8_t) ( (_m->BCM_MirrorsAutoTilt_Stat & (0x01U)) | ((_m->BCM_WindowsRainClosing_Stat & (0x01U)) << 1U) | ((_m->BCM_AudibleLockFdBack_Stat & (0x01U)) << 2U) | ((_m->BCM_AutoWiper_Stat & (0x01U)) << 3U) | ((_m->BCM_TrnkDoorCloseBySpeed_Stat & (0x01U)) << 4U) | ((_m->BCM_RunningBoards_Stat & (0x03U)) << 5U) | ((_m->BCM_SteeringWheelAutoHeat_Stat & (0x01U)) << 7U) ); + _d[6] |= (uint8_t) ( (_m->BCM_Ultraviolet_Stat & (0x01U)) ); + + *_len = (uint8_t) BCM_UserConfig_Stat_DLC; + *_ide = (uint8_t) BCM_UserConfig_Stat_IDE; + return BCM_UserConfig_Stat_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_MAS_Main_candb(FIU_MAS_Main_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->FIU_AVM_Active_Req = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->FIU_View_Req = (uint8_t) ( ((_d[0] >> 1U) & (0x0FU)) ); + _m->FIU_APAstartBtn_Req = (uint8_t) ( ((_d[0] >> 5U) & (0x01U)) ); + _m->FIU_MAS_Mode_Req = (uint8_t) ( ((_d[0] >> 6U) & (0x03U)) ); + _m->FIU_Narrow_Mode_Stat = (uint8_t) ( (_d[1] & (0x03U)) ); + _m->FIU_UltraSonicEnable_Stat = (uint8_t) ( ((_d[1] >> 2U) & (0x03U)) ); + _m->FIU_AutoAct_Stat = (uint8_t) ( ((_d[1] >> 4U) & (0x03U)) ); + _m->FIU_CurrentPath_Req = (uint8_t) ( ((_d[1] >> 6U) & (0x03U)) ); + _m->FIU_SDMmaster_Req = (uint8_t) ( (_d[2] & (0x01U)) ); + _m->FIU_SelectedPlace_Req = (uint8_t) ( ((_d[2] >> 1U) & (0x07U)) ); + _m->FIU_ContinueMove_Req = (uint8_t) ( ((_d[2] >> 4U) & (0x01U)) ); + _m->FIU_StopAPA_Req = (uint8_t) ( ((_d[2] >> 5U) & (0x01U)) ); + _m->FIU_SDMcom_Req = (uint8_t) ( ((_d[2] >> 6U) & (0x01U)) ); + _m->FIU_FinishMove_Req = (uint8_t) ( ((_d[2] >> 7U) & (0x01U)) ); + _m->FIU_ParkingOutPath_Req = (uint8_t) ( (_d[3] & (0x07U)) ); + _m->FIU_MAS_Main_RC = (uint8_t) ( ((_d[3] >> 4U) & (0x0FU)) ); + _m->FIU_MAS_Main_CS = (uint8_t) ( (_d[4] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < FIU_MAS_Main_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_FIU_MAS_Main_candb(&_m->mon1, FIU_MAS_Main_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return FIU_MAS_Main_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_FIU_MAS_Main_candb(FIU_MAS_Main_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_MAS_Main_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->FIU_AVM_Active_Req & (0x01U)) | ((_m->FIU_View_Req & (0x0FU)) << 1U) | ((_m->FIU_APAstartBtn_Req & (0x01U)) << 5U) | ((_m->FIU_MAS_Mode_Req & (0x03U)) << 6U) ); + cframe->Data[1] |= (uint8_t) ( (_m->FIU_Narrow_Mode_Stat & (0x03U)) | ((_m->FIU_UltraSonicEnable_Stat & (0x03U)) << 2U) | ((_m->FIU_AutoAct_Stat & (0x03U)) << 4U) | ((_m->FIU_CurrentPath_Req & (0x03U)) << 6U) ); + cframe->Data[2] |= (uint8_t) ( (_m->FIU_SDMmaster_Req & (0x01U)) | ((_m->FIU_SelectedPlace_Req & (0x07U)) << 1U) | ((_m->FIU_ContinueMove_Req & (0x01U)) << 4U) | ((_m->FIU_StopAPA_Req & (0x01U)) << 5U) | ((_m->FIU_SDMcom_Req & (0x01U)) << 6U) | ((_m->FIU_FinishMove_Req & (0x01U)) << 7U) ); + cframe->Data[3] |= (uint8_t) ( (_m->FIU_ParkingOutPath_Req & (0x07U)) | ((_m->FIU_MAS_Main_RC & (0x0FU)) << 4U) ); + cframe->Data[4] |= (uint8_t) ( (_m->FIU_MAS_Main_CS & (0xFFU)) ); + + cframe->MsgId = (uint32_t) FIU_MAS_Main_CANID; + cframe->DLC = (uint8_t) FIU_MAS_Main_DLC; + cframe->IDE = (uint8_t) FIU_MAS_Main_IDE; + return FIU_MAS_Main_CANID; +} + +#else + +uint32_t Pack_FIU_MAS_Main_candb(FIU_MAS_Main_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_MAS_Main_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->FIU_AVM_Active_Req & (0x01U)) | ((_m->FIU_View_Req & (0x0FU)) << 1U) | ((_m->FIU_APAstartBtn_Req & (0x01U)) << 5U) | ((_m->FIU_MAS_Mode_Req & (0x03U)) << 6U) ); + _d[1] |= (uint8_t) ( (_m->FIU_Narrow_Mode_Stat & (0x03U)) | ((_m->FIU_UltraSonicEnable_Stat & (0x03U)) << 2U) | ((_m->FIU_AutoAct_Stat & (0x03U)) << 4U) | ((_m->FIU_CurrentPath_Req & (0x03U)) << 6U) ); + _d[2] |= (uint8_t) ( (_m->FIU_SDMmaster_Req & (0x01U)) | ((_m->FIU_SelectedPlace_Req & (0x07U)) << 1U) | ((_m->FIU_ContinueMove_Req & (0x01U)) << 4U) | ((_m->FIU_StopAPA_Req & (0x01U)) << 5U) | ((_m->FIU_SDMcom_Req & (0x01U)) << 6U) | ((_m->FIU_FinishMove_Req & (0x01U)) << 7U) ); + _d[3] |= (uint8_t) ( (_m->FIU_ParkingOutPath_Req & (0x07U)) | ((_m->FIU_MAS_Main_RC & (0x0FU)) << 4U) ); + _d[4] |= (uint8_t) ( (_m->FIU_MAS_Main_CS & (0xFFU)) ); + + *_len = (uint8_t) FIU_MAS_Main_DLC; + *_ide = (uint8_t) FIU_MAS_Main_IDE; + return FIU_MAS_Main_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_MAS_APA_Paths_candb(MAS_APA_Paths_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->MAS_AvailablePaths_Stat = (uint8_t) ( (_d[0] & (0x03U)) ); + _m->MAS_APAPlaceParkingOut_Stat = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + _m->MAS_APADirParkingOut_Stat = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + _m->MAS_PathParkOutFL_Stat = (uint8_t) ( ((_d[0] >> 4U) & (0x01U)) ); + _m->MAS_PathParkOutFR_Stat = (uint8_t) ( ((_d[0] >> 5U) & (0x01U)) ); + _m->MAS_PathParkOutFront_Stat = (uint8_t) ( ((_d[0] >> 6U) & (0x01U)) ); + _m->MAS_PathParkOutRL_Stat = (uint8_t) ( ((_d[0] >> 7U) & (0x01U)) ); + _m->MAS_PathParkOutRR_Stat = (uint8_t) ( (_d[1] & (0x01U)) ); + _m->MAS_PathParkOutRear_Stat = (uint8_t) ( ((_d[1] >> 1U) & (0x01U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < MAS_APA_Paths_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_MAS_APA_Paths_candb(&_m->mon1, MAS_APA_Paths_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return MAS_APA_Paths_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_MAS_APA_Paths_candb(MAS_APA_Paths_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(MAS_APA_Paths_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->MAS_AvailablePaths_Stat & (0x03U)) | ((_m->MAS_APAPlaceParkingOut_Stat & (0x01U)) << 2U) | ((_m->MAS_APADirParkingOut_Stat & (0x01U)) << 3U) | ((_m->MAS_PathParkOutFL_Stat & (0x01U)) << 4U) | ((_m->MAS_PathParkOutFR_Stat & (0x01U)) << 5U) | ((_m->MAS_PathParkOutFront_Stat & (0x01U)) << 6U) | ((_m->MAS_PathParkOutRL_Stat & (0x01U)) << 7U) ); + cframe->Data[1] |= (uint8_t) ( (_m->MAS_PathParkOutRR_Stat & (0x01U)) | ((_m->MAS_PathParkOutRear_Stat & (0x01U)) << 1U) ); + + cframe->MsgId = (uint32_t) MAS_APA_Paths_CANID; + cframe->DLC = (uint8_t) MAS_APA_Paths_DLC; + cframe->IDE = (uint8_t) MAS_APA_Paths_IDE; + return MAS_APA_Paths_CANID; +} + +#else + +uint32_t Pack_MAS_APA_Paths_candb(MAS_APA_Paths_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(MAS_APA_Paths_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->MAS_AvailablePaths_Stat & (0x03U)) | ((_m->MAS_APAPlaceParkingOut_Stat & (0x01U)) << 2U) | ((_m->MAS_APADirParkingOut_Stat & (0x01U)) << 3U) | ((_m->MAS_PathParkOutFL_Stat & (0x01U)) << 4U) | ((_m->MAS_PathParkOutFR_Stat & (0x01U)) << 5U) | ((_m->MAS_PathParkOutFront_Stat & (0x01U)) << 6U) | ((_m->MAS_PathParkOutRL_Stat & (0x01U)) << 7U) ); + _d[1] |= (uint8_t) ( (_m->MAS_PathParkOutRR_Stat & (0x01U)) | ((_m->MAS_PathParkOutRear_Stat & (0x01U)) << 1U) ); + + *_len = (uint8_t) MAS_APA_Paths_DLC; + *_ide = (uint8_t) MAS_APA_Paths_IDE; + return MAS_APA_Paths_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_MAS_APA_ParkPlace_candb(MAS_APA_ParkPlace_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->MAS_APAplaceL1_Stat = (uint8_t) ( (_d[0] & (0x03U)) ); + _m->MAS_APAplaceL2_Stat = (uint8_t) ( ((_d[0] >> 2U) & (0x03U)) ); + _m->MAS_APAplaceL3_Stat = (uint8_t) ( ((_d[0] >> 4U) & (0x03U)) ); + _m->MAS_APAplaceR1_Stat = (uint8_t) ( ((_d[0] >> 6U) & (0x03U)) ); + _m->MAS_APAplaceR2_Stat = (uint8_t) ( (_d[1] & (0x03U)) ); + _m->MAS_APAplaceR3_Stat = (uint8_t) ( ((_d[1] >> 2U) & (0x03U)) ); + _m->MAS_AvailablePathsL1_Stat = (uint8_t) ( ((_d[1] >> 4U) & (0x03U)) ); + _m->MAS_AvailablePathsL2_Stat = (uint8_t) ( ((_d[1] >> 6U) & (0x03U)) ); + _m->MAS_APAplaceL1Dist_Val = (uint8_t) ( (_d[2] & (0x0FU)) ); + _m->MAS_APAplaceL2Dist_Val = (uint8_t) ( ((_d[2] >> 4U) & (0x0FU)) ); + _m->MAS_APAplaceL3Dist_Val = (uint8_t) ( (_d[3] & (0x0FU)) ); + _m->MAS_APAplaceR1Dist_Val = (uint8_t) ( ((_d[3] >> 4U) & (0x0FU)) ); + _m->MAS_APAplaceR2Dist_Val = (uint8_t) ( (_d[4] & (0x0FU)) ); + _m->MAS_APAplaceR3Dist_Val = (uint8_t) ( ((_d[4] >> 4U) & (0x0FU)) ); + _m->MAS_AvailablePathsL3_Stat = (uint8_t) ( (_d[5] & (0x03U)) ); + _m->MAS_AvailablePathsR1_Stat = (uint8_t) ( ((_d[5] >> 2U) & (0x03U)) ); + _m->MAS_AvailablePathsR2_Stat = (uint8_t) ( ((_d[5] >> 4U) & (0x03U)) ); + _m->MAS_AvailablePathsR3_Stat = (uint8_t) ( ((_d[5] >> 6U) & (0x03U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < MAS_APA_ParkPlace_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_MAS_APA_ParkPlace_candb(&_m->mon1, MAS_APA_ParkPlace_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return MAS_APA_ParkPlace_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_MAS_APA_ParkPlace_candb(MAS_APA_ParkPlace_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(MAS_APA_ParkPlace_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->MAS_APAplaceL1_Stat & (0x03U)) | ((_m->MAS_APAplaceL2_Stat & (0x03U)) << 2U) | ((_m->MAS_APAplaceL3_Stat & (0x03U)) << 4U) | ((_m->MAS_APAplaceR1_Stat & (0x03U)) << 6U) ); + cframe->Data[1] |= (uint8_t) ( (_m->MAS_APAplaceR2_Stat & (0x03U)) | ((_m->MAS_APAplaceR3_Stat & (0x03U)) << 2U) | ((_m->MAS_AvailablePathsL1_Stat & (0x03U)) << 4U) | ((_m->MAS_AvailablePathsL2_Stat & (0x03U)) << 6U) ); + cframe->Data[2] |= (uint8_t) ( (_m->MAS_APAplaceL1Dist_Val & (0x0FU)) | ((_m->MAS_APAplaceL2Dist_Val & (0x0FU)) << 4U) ); + cframe->Data[3] |= (uint8_t) ( (_m->MAS_APAplaceL3Dist_Val & (0x0FU)) | ((_m->MAS_APAplaceR1Dist_Val & (0x0FU)) << 4U) ); + cframe->Data[4] |= (uint8_t) ( (_m->MAS_APAplaceR2Dist_Val & (0x0FU)) | ((_m->MAS_APAplaceR3Dist_Val & (0x0FU)) << 4U) ); + cframe->Data[5] |= (uint8_t) ( (_m->MAS_AvailablePathsL3_Stat & (0x03U)) | ((_m->MAS_AvailablePathsR1_Stat & (0x03U)) << 2U) | ((_m->MAS_AvailablePathsR2_Stat & (0x03U)) << 4U) | ((_m->MAS_AvailablePathsR3_Stat & (0x03U)) << 6U) ); + + cframe->MsgId = (uint32_t) MAS_APA_ParkPlace_CANID; + cframe->DLC = (uint8_t) MAS_APA_ParkPlace_DLC; + cframe->IDE = (uint8_t) MAS_APA_ParkPlace_IDE; + return MAS_APA_ParkPlace_CANID; +} + +#else + +uint32_t Pack_MAS_APA_ParkPlace_candb(MAS_APA_ParkPlace_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(MAS_APA_ParkPlace_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->MAS_APAplaceL1_Stat & (0x03U)) | ((_m->MAS_APAplaceL2_Stat & (0x03U)) << 2U) | ((_m->MAS_APAplaceL3_Stat & (0x03U)) << 4U) | ((_m->MAS_APAplaceR1_Stat & (0x03U)) << 6U) ); + _d[1] |= (uint8_t) ( (_m->MAS_APAplaceR2_Stat & (0x03U)) | ((_m->MAS_APAplaceR3_Stat & (0x03U)) << 2U) | ((_m->MAS_AvailablePathsL1_Stat & (0x03U)) << 4U) | ((_m->MAS_AvailablePathsL2_Stat & (0x03U)) << 6U) ); + _d[2] |= (uint8_t) ( (_m->MAS_APAplaceL1Dist_Val & (0x0FU)) | ((_m->MAS_APAplaceL2Dist_Val & (0x0FU)) << 4U) ); + _d[3] |= (uint8_t) ( (_m->MAS_APAplaceL3Dist_Val & (0x0FU)) | ((_m->MAS_APAplaceR1Dist_Val & (0x0FU)) << 4U) ); + _d[4] |= (uint8_t) ( (_m->MAS_APAplaceR2Dist_Val & (0x0FU)) | ((_m->MAS_APAplaceR3Dist_Val & (0x0FU)) << 4U) ); + _d[5] |= (uint8_t) ( (_m->MAS_AvailablePathsL3_Stat & (0x03U)) | ((_m->MAS_AvailablePathsR1_Stat & (0x03U)) << 2U) | ((_m->MAS_AvailablePathsR2_Stat & (0x03U)) << 4U) | ((_m->MAS_AvailablePathsR3_Stat & (0x03U)) << 6U) ); + + *_len = (uint8_t) MAS_APA_ParkPlace_DLC; + *_ide = (uint8_t) MAS_APA_ParkPlace_IDE; + return MAS_APA_ParkPlace_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_ICLSilCU_State_candb(ICLSilCU_State_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->ICLSilCU_Module_Stat = (int8_t) __ext_sig__(( (_d[0] & (0x0FU)) ), 4); + _m->ICLSilCU_ModuleTemperature_Val = (int8_t) __ext_sig__(( ((_d[1] & (0x07U)) << 4U) | ((_d[0] >> 4U) & (0x0FU)) ), 7); + _m->ICLSilCU_reserved1 = (int8_t) __ext_sig__(( ((_d[1] >> 3U) & (0x1FU)) ), 5); + _m->ICLSilCU_reserved2 = (int8_t) __ext_sig__(( (_d[2] & (0xFFU)) ), 8); + _m->ICLSilCU_reserved3 = (int8_t) __ext_sig__(( (_d[3] & (0xFFU)) ), 8); + _m->ICLSilCU_reserved4 = (int8_t) __ext_sig__(( (_d[4] & (0xFFU)) ), 8); + _m->ICLSilCU_reserved5 = (int8_t) __ext_sig__(( (_d[5] & (0xFFU)) ), 8); + _m->ICLSilCU_reserved6 = (int8_t) __ext_sig__(( (_d[6] & (0xFFU)) ), 8); + _m->ICLSilCU_reserved7 = (int8_t) __ext_sig__(( (_d[7] & (0xFFU)) ), 8); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < ICLSilCU_State_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_ICLSilCU_State_candb(&_m->mon1, ICLSilCU_State_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return ICLSilCU_State_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_ICLSilCU_State_candb(ICLSilCU_State_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(ICLSilCU_State_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->ICLSilCU_Module_Stat & (0x0FU)) | ((_m->ICLSilCU_ModuleTemperature_Val & (0x0FU)) << 4U) ); + cframe->Data[1] |= (uint8_t) ( ((_m->ICLSilCU_ModuleTemperature_Val >> 4U) & (0x07U)) | ((_m->ICLSilCU_reserved1 & (0x1FU)) << 3U) ); + cframe->Data[2] |= (uint8_t) ( (_m->ICLSilCU_reserved2 & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->ICLSilCU_reserved3 & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->ICLSilCU_reserved4 & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->ICLSilCU_reserved5 & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->ICLSilCU_reserved6 & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->ICLSilCU_reserved7 & (0xFFU)) ); + + cframe->MsgId = (uint32_t) ICLSilCU_State_CANID; + cframe->DLC = (uint8_t) ICLSilCU_State_DLC; + cframe->IDE = (uint8_t) ICLSilCU_State_IDE; + return ICLSilCU_State_CANID; +} + +#else + +uint32_t Pack_ICLSilCU_State_candb(ICLSilCU_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(ICLSilCU_State_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->ICLSilCU_Module_Stat & (0x0FU)) | ((_m->ICLSilCU_ModuleTemperature_Val & (0x0FU)) << 4U) ); + _d[1] |= (uint8_t) ( ((_m->ICLSilCU_ModuleTemperature_Val >> 4U) & (0x07U)) | ((_m->ICLSilCU_reserved1 & (0x1FU)) << 3U) ); + _d[2] |= (uint8_t) ( (_m->ICLSilCU_reserved2 & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->ICLSilCU_reserved3 & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->ICLSilCU_reserved4 & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->ICLSilCU_reserved5 & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->ICLSilCU_reserved6 & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->ICLSilCU_reserved7 & (0xFFU)) ); + + *_len = (uint8_t) ICLSilCU_State_DLC; + *_ide = (uint8_t) ICLSilCU_State_IDE; + return ICLSilCU_State_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_ICRSilCU_State_candb(ICRSilCU_State_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->ICRSilCU_Module_Stat = (int8_t) __ext_sig__(( (_d[0] & (0x0FU)) ), 4); + _m->ICRSilCU_ModuleTemperature_Val = (int8_t) __ext_sig__(( ((_d[1] & (0x07U)) << 4U) | ((_d[0] >> 4U) & (0x0FU)) ), 7); + _m->ICRSilCU_reserved1 = (int8_t) __ext_sig__(( ((_d[1] >> 3U) & (0x1FU)) ), 5); + _m->ICRSilCU_reserved2 = (int8_t) __ext_sig__(( (_d[2] & (0xFFU)) ), 8); + _m->ICRSilCU_reserved3 = (int8_t) __ext_sig__(( (_d[3] & (0xFFU)) ), 8); + _m->ICRSilCU_reserved4 = (int8_t) __ext_sig__(( (_d[4] & (0xFFU)) ), 8); + _m->ICRSilCU_reserved5 = (int8_t) __ext_sig__(( (_d[5] & (0xFFU)) ), 8); + _m->ICRSilCU_reserved6 = (int8_t) __ext_sig__(( (_d[6] & (0xFFU)) ), 8); + _m->ICRSilCU_reserved7 = (int8_t) __ext_sig__(( (_d[7] & (0xFFU)) ), 8); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < ICRSilCU_State_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_ICRSilCU_State_candb(&_m->mon1, ICRSilCU_State_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return ICRSilCU_State_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_ICRSilCU_State_candb(ICRSilCU_State_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(ICRSilCU_State_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->ICRSilCU_Module_Stat & (0x0FU)) | ((_m->ICRSilCU_ModuleTemperature_Val & (0x0FU)) << 4U) ); + cframe->Data[1] |= (uint8_t) ( ((_m->ICRSilCU_ModuleTemperature_Val >> 4U) & (0x07U)) | ((_m->ICRSilCU_reserved1 & (0x1FU)) << 3U) ); + cframe->Data[2] |= (uint8_t) ( (_m->ICRSilCU_reserved2 & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->ICRSilCU_reserved3 & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->ICRSilCU_reserved4 & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->ICRSilCU_reserved5 & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->ICRSilCU_reserved6 & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->ICRSilCU_reserved7 & (0xFFU)) ); + + cframe->MsgId = (uint32_t) ICRSilCU_State_CANID; + cframe->DLC = (uint8_t) ICRSilCU_State_DLC; + cframe->IDE = (uint8_t) ICRSilCU_State_IDE; + return ICRSilCU_State_CANID; +} + +#else + +uint32_t Pack_ICRSilCU_State_candb(ICRSilCU_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(ICRSilCU_State_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->ICRSilCU_Module_Stat & (0x0FU)) | ((_m->ICRSilCU_ModuleTemperature_Val & (0x0FU)) << 4U) ); + _d[1] |= (uint8_t) ( ((_m->ICRSilCU_ModuleTemperature_Val >> 4U) & (0x07U)) | ((_m->ICRSilCU_reserved1 & (0x1FU)) << 3U) ); + _d[2] |= (uint8_t) ( (_m->ICRSilCU_reserved2 & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->ICRSilCU_reserved3 & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->ICRSilCU_reserved4 & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->ICRSilCU_reserved5 & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->ICRSilCU_reserved6 & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->ICRSilCU_reserved7 & (0xFFU)) ); + + *_len = (uint8_t) ICRSilCU_State_DLC; + *_ide = (uint8_t) ICRSilCU_State_IDE; + return ICRSilCU_State_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SFRSilCU_State_candb(SFRSilCU_State_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->SFRSilCU_Module_Stat = (uint8_t) ( (_d[0] & (0x0FU)) ); + _m->SFRSilCU_ModuleTemperature_Val = (int8_t) __ext_sig__(( ((_d[1] & (0x07U)) << 4U) | ((_d[0] >> 4U) & (0x0FU)) ), 7); + _m->SFRSilCU_reserved1 = (int8_t) __ext_sig__(( ((_d[1] >> 3U) & (0x1FU)) ), 5); + _m->SFRSilCU_reserved2 = (int8_t) __ext_sig__(( (_d[2] & (0xFFU)) ), 8); + _m->SFRSilCU_reserved3 = (int8_t) __ext_sig__(( (_d[3] & (0xFFU)) ), 8); + _m->SFRSilCU_reserved4 = (int8_t) __ext_sig__(( (_d[4] & (0xFFU)) ), 8); + _m->SFRSilCU_reserved5 = (int8_t) __ext_sig__(( (_d[5] & (0xFFU)) ), 8); + _m->SFRSilCU_reserved6 = (int8_t) __ext_sig__(( (_d[6] & (0xFFU)) ), 8); + _m->SFRSilCU_reserved7 = (int8_t) __ext_sig__(( (_d[7] & (0xFFU)) ), 8); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < SFRSilCU_State_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_SFRSilCU_State_candb(&_m->mon1, SFRSilCU_State_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return SFRSilCU_State_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_SFRSilCU_State_candb(SFRSilCU_State_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SFRSilCU_State_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->SFRSilCU_Module_Stat & (0x0FU)) | ((_m->SFRSilCU_ModuleTemperature_Val & (0x0FU)) << 4U) ); + cframe->Data[1] |= (uint8_t) ( ((_m->SFRSilCU_ModuleTemperature_Val >> 4U) & (0x07U)) | ((_m->SFRSilCU_reserved1 & (0x1FU)) << 3U) ); + cframe->Data[2] |= (uint8_t) ( (_m->SFRSilCU_reserved2 & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->SFRSilCU_reserved3 & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->SFRSilCU_reserved4 & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->SFRSilCU_reserved5 & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->SFRSilCU_reserved6 & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->SFRSilCU_reserved7 & (0xFFU)) ); + + cframe->MsgId = (uint32_t) SFRSilCU_State_CANID; + cframe->DLC = (uint8_t) SFRSilCU_State_DLC; + cframe->IDE = (uint8_t) SFRSilCU_State_IDE; + return SFRSilCU_State_CANID; +} + +#else + +uint32_t Pack_SFRSilCU_State_candb(SFRSilCU_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SFRSilCU_State_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->SFRSilCU_Module_Stat & (0x0FU)) | ((_m->SFRSilCU_ModuleTemperature_Val & (0x0FU)) << 4U) ); + _d[1] |= (uint8_t) ( ((_m->SFRSilCU_ModuleTemperature_Val >> 4U) & (0x07U)) | ((_m->SFRSilCU_reserved1 & (0x1FU)) << 3U) ); + _d[2] |= (uint8_t) ( (_m->SFRSilCU_reserved2 & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->SFRSilCU_reserved3 & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->SFRSilCU_reserved4 & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->SFRSilCU_reserved5 & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->SFRSilCU_reserved6 & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->SFRSilCU_reserved7 & (0xFFU)) ); + + *_len = (uint8_t) SFRSilCU_State_DLC; + *_ide = (uint8_t) SFRSilCU_State_IDE; + return SFRSilCU_State_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SFLSilCU_State_candb(SFLSilCU_State_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->SFLSilCU_Module_Stat = (uint8_t) ( (_d[0] & (0x0FU)) ); + _m->SFLSilCU_ModuleTemperature_Val = (int8_t) __ext_sig__(( ((_d[1] & (0x07U)) << 4U) | ((_d[0] >> 4U) & (0x0FU)) ), 7); + _m->SFLSilCU_reserved1 = (int8_t) __ext_sig__(( ((_d[1] >> 3U) & (0x1FU)) ), 5); + _m->SFLSilCU_reserved2 = (int8_t) __ext_sig__(( (_d[2] & (0xFFU)) ), 8); + _m->SFLSilCU_reserved3 = (int8_t) __ext_sig__(( (_d[3] & (0xFFU)) ), 8); + _m->SFLSilCU_reserved4 = (int8_t) __ext_sig__(( (_d[4] & (0xFFU)) ), 8); + _m->SFLSilCU_reserved5 = (int8_t) __ext_sig__(( (_d[5] & (0xFFU)) ), 8); + _m->SFLSilCU_reserved6 = (int8_t) __ext_sig__(( (_d[6] & (0xFFU)) ), 8); + _m->SFLSilCU_reserved7 = (int8_t) __ext_sig__(( (_d[7] & (0xFFU)) ), 8); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < SFLSilCU_State_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_SFLSilCU_State_candb(&_m->mon1, SFLSilCU_State_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return SFLSilCU_State_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_SFLSilCU_State_candb(SFLSilCU_State_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SFLSilCU_State_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->SFLSilCU_Module_Stat & (0x0FU)) | ((_m->SFLSilCU_ModuleTemperature_Val & (0x0FU)) << 4U) ); + cframe->Data[1] |= (uint8_t) ( ((_m->SFLSilCU_ModuleTemperature_Val >> 4U) & (0x07U)) | ((_m->SFLSilCU_reserved1 & (0x1FU)) << 3U) ); + cframe->Data[2] |= (uint8_t) ( (_m->SFLSilCU_reserved2 & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->SFLSilCU_reserved3 & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->SFLSilCU_reserved4 & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->SFLSilCU_reserved5 & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->SFLSilCU_reserved6 & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->SFLSilCU_reserved7 & (0xFFU)) ); + + cframe->MsgId = (uint32_t) SFLSilCU_State_CANID; + cframe->DLC = (uint8_t) SFLSilCU_State_DLC; + cframe->IDE = (uint8_t) SFLSilCU_State_IDE; + return SFLSilCU_State_CANID; +} + +#else + +uint32_t Pack_SFLSilCU_State_candb(SFLSilCU_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SFLSilCU_State_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->SFLSilCU_Module_Stat & (0x0FU)) | ((_m->SFLSilCU_ModuleTemperature_Val & (0x0FU)) << 4U) ); + _d[1] |= (uint8_t) ( ((_m->SFLSilCU_ModuleTemperature_Val >> 4U) & (0x07U)) | ((_m->SFLSilCU_reserved1 & (0x1FU)) << 3U) ); + _d[2] |= (uint8_t) ( (_m->SFLSilCU_reserved2 & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->SFLSilCU_reserved3 & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->SFLSilCU_reserved4 & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->SFLSilCU_reserved5 & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->SFLSilCU_reserved6 & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->SFLSilCU_reserved7 & (0xFFU)) ); + + *_len = (uint8_t) SFLSilCU_State_DLC; + *_ide = (uint8_t) SFLSilCU_State_IDE; + return SFLSilCU_State_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_RDRSilCU_State_candb(RDRSilCU_State_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->RDRSilCU_Module_Stat = (int8_t) __ext_sig__(( (_d[0] & (0x0FU)) ), 4); + _m->RDRSilCU_ModuleTemperature_Val = (int8_t) __ext_sig__(( ((_d[1] & (0x07U)) << 4U) | ((_d[0] >> 4U) & (0x0FU)) ), 7); + _m->RDRSilCU_reserved1 = (int8_t) __ext_sig__(( ((_d[1] >> 3U) & (0x1FU)) ), 5); + _m->RDRSilCU_reserved2 = (int8_t) __ext_sig__(( (_d[2] & (0xFFU)) ), 8); + _m->RDRSilCU_reserved3 = (int8_t) __ext_sig__(( (_d[3] & (0xFFU)) ), 8); + _m->RDRSilCU_reserved4 = (int8_t) __ext_sig__(( (_d[4] & (0xFFU)) ), 8); + _m->RDRSilCU_reserved5 = (int8_t) __ext_sig__(( (_d[5] & (0xFFU)) ), 8); + _m->RDRSilCU_reserved6 = (int8_t) __ext_sig__(( (_d[6] & (0xFFU)) ), 8); + _m->RDRSilCU_reserved7 = (int8_t) __ext_sig__(( (_d[7] & (0xFFU)) ), 8); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < RDRSilCU_State_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_RDRSilCU_State_candb(&_m->mon1, RDRSilCU_State_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return RDRSilCU_State_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_RDRSilCU_State_candb(RDRSilCU_State_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(RDRSilCU_State_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->RDRSilCU_Module_Stat & (0x0FU)) | ((_m->RDRSilCU_ModuleTemperature_Val & (0x0FU)) << 4U) ); + cframe->Data[1] |= (uint8_t) ( ((_m->RDRSilCU_ModuleTemperature_Val >> 4U) & (0x07U)) | ((_m->RDRSilCU_reserved1 & (0x1FU)) << 3U) ); + cframe->Data[2] |= (uint8_t) ( (_m->RDRSilCU_reserved2 & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->RDRSilCU_reserved3 & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->RDRSilCU_reserved4 & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->RDRSilCU_reserved5 & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->RDRSilCU_reserved6 & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->RDRSilCU_reserved7 & (0xFFU)) ); + + cframe->MsgId = (uint32_t) RDRSilCU_State_CANID; + cframe->DLC = (uint8_t) RDRSilCU_State_DLC; + cframe->IDE = (uint8_t) RDRSilCU_State_IDE; + return RDRSilCU_State_CANID; +} + +#else + +uint32_t Pack_RDRSilCU_State_candb(RDRSilCU_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(RDRSilCU_State_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->RDRSilCU_Module_Stat & (0x0FU)) | ((_m->RDRSilCU_ModuleTemperature_Val & (0x0FU)) << 4U) ); + _d[1] |= (uint8_t) ( ((_m->RDRSilCU_ModuleTemperature_Val >> 4U) & (0x07U)) | ((_m->RDRSilCU_reserved1 & (0x1FU)) << 3U) ); + _d[2] |= (uint8_t) ( (_m->RDRSilCU_reserved2 & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->RDRSilCU_reserved3 & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->RDRSilCU_reserved4 & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->RDRSilCU_reserved5 & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->RDRSilCU_reserved6 & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->RDRSilCU_reserved7 & (0xFFU)) ); + + *_len = (uint8_t) RDRSilCU_State_DLC; + *_ide = (uint8_t) RDRSilCU_State_IDE; + return RDRSilCU_State_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FCSilCU_State_candb(FCSilCU_State_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->FCSilCU_Module_Stat = (int8_t) __ext_sig__(( (_d[0] & (0x0FU)) ), 4); + _m->FCSilCU_ModuleTemperature_Val = (uint8_t) ( ((_d[1] & (0x07U)) << 4U) | ((_d[0] >> 4U) & (0x0FU)) ); + _m->FCSilCU_reserved1 = (int8_t) __ext_sig__(( ((_d[1] >> 3U) & (0x1FU)) ), 5); + _m->FCSilCU_reserved2 = (int8_t) __ext_sig__(( (_d[2] & (0xFFU)) ), 8); + _m->FCSilCU_reserved3 = (int8_t) __ext_sig__(( (_d[3] & (0xFFU)) ), 8); + _m->FCSilCU_reserved4 = (int8_t) __ext_sig__(( (_d[4] & (0xFFU)) ), 8); + _m->FCSilCU_reserved5 = (int8_t) __ext_sig__(( (_d[5] & (0xFFU)) ), 8); + _m->FCSilCU_reserved6 = (int8_t) __ext_sig__(( (_d[6] & (0xFFU)) ), 8); + _m->FCSilCU_reserved7 = (int8_t) __ext_sig__(( (_d[7] & (0xFFU)) ), 8); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < FCSilCU_State_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_FCSilCU_State_candb(&_m->mon1, FCSilCU_State_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return FCSilCU_State_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_FCSilCU_State_candb(FCSilCU_State_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FCSilCU_State_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->FCSilCU_Module_Stat & (0x0FU)) | ((_m->FCSilCU_ModuleTemperature_Val & (0x0FU)) << 4U) ); + cframe->Data[1] |= (uint8_t) ( ((_m->FCSilCU_ModuleTemperature_Val >> 4U) & (0x07U)) | ((_m->FCSilCU_reserved1 & (0x1FU)) << 3U) ); + cframe->Data[2] |= (uint8_t) ( (_m->FCSilCU_reserved2 & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->FCSilCU_reserved3 & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->FCSilCU_reserved4 & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->FCSilCU_reserved5 & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->FCSilCU_reserved6 & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->FCSilCU_reserved7 & (0xFFU)) ); + + cframe->MsgId = (uint32_t) FCSilCU_State_CANID; + cframe->DLC = (uint8_t) FCSilCU_State_DLC; + cframe->IDE = (uint8_t) FCSilCU_State_IDE; + return FCSilCU_State_CANID; +} + +#else + +uint32_t Pack_FCSilCU_State_candb(FCSilCU_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FCSilCU_State_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->FCSilCU_Module_Stat & (0x0FU)) | ((_m->FCSilCU_ModuleTemperature_Val & (0x0FU)) << 4U) ); + _d[1] |= (uint8_t) ( ((_m->FCSilCU_ModuleTemperature_Val >> 4U) & (0x07U)) | ((_m->FCSilCU_reserved1 & (0x1FU)) << 3U) ); + _d[2] |= (uint8_t) ( (_m->FCSilCU_reserved2 & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->FCSilCU_reserved3 & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->FCSilCU_reserved4 & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->FCSilCU_reserved5 & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->FCSilCU_reserved6 & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->FCSilCU_reserved7 & (0xFFU)) ); + + *_len = (uint8_t) FCSilCU_State_DLC; + *_ide = (uint8_t) FCSilCU_State_IDE; + return FCSilCU_State_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_RCLSilCU_State_candb(RCLSilCU_State_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->RCLSilCU_Module_Stat = (int8_t) __ext_sig__(( (_d[0] & (0x0FU)) ), 4); + _m->RCLSilCU_ModuleTemperature_Val = (int8_t) __ext_sig__(( ((_d[1] & (0x07U)) << 4U) | ((_d[0] >> 4U) & (0x0FU)) ), 7); + _m->RCLSilCU_reserved1 = (int8_t) __ext_sig__(( ((_d[1] >> 3U) & (0x1FU)) ), 5); + _m->RCLSilCU_reserved2 = (int8_t) __ext_sig__(( (_d[2] & (0xFFU)) ), 8); + _m->RCLSilCU_reserved3 = (int8_t) __ext_sig__(( (_d[3] & (0xFFU)) ), 8); + _m->RCLSilCU_reserved4 = (int8_t) __ext_sig__(( (_d[4] & (0xFFU)) ), 8); + _m->RCLSilCU_reserved5 = (int8_t) __ext_sig__(( (_d[5] & (0xFFU)) ), 8); + _m->RCLSilCU_reserved6 = (int8_t) __ext_sig__(( (_d[6] & (0xFFU)) ), 8); + _m->RCLSilCU_reserved7 = (int8_t) __ext_sig__(( (_d[7] & (0xFFU)) ), 8); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < RCLSilCU_State_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_RCLSilCU_State_candb(&_m->mon1, RCLSilCU_State_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return RCLSilCU_State_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_RCLSilCU_State_candb(RCLSilCU_State_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(RCLSilCU_State_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->RCLSilCU_Module_Stat & (0x0FU)) | ((_m->RCLSilCU_ModuleTemperature_Val & (0x0FU)) << 4U) ); + cframe->Data[1] |= (uint8_t) ( ((_m->RCLSilCU_ModuleTemperature_Val >> 4U) & (0x07U)) | ((_m->RCLSilCU_reserved1 & (0x1FU)) << 3U) ); + cframe->Data[2] |= (uint8_t) ( (_m->RCLSilCU_reserved2 & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->RCLSilCU_reserved3 & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->RCLSilCU_reserved4 & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->RCLSilCU_reserved5 & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->RCLSilCU_reserved6 & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->RCLSilCU_reserved7 & (0xFFU)) ); + + cframe->MsgId = (uint32_t) RCLSilCU_State_CANID; + cframe->DLC = (uint8_t) RCLSilCU_State_DLC; + cframe->IDE = (uint8_t) RCLSilCU_State_IDE; + return RCLSilCU_State_CANID; +} + +#else + +uint32_t Pack_RCLSilCU_State_candb(RCLSilCU_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(RCLSilCU_State_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->RCLSilCU_Module_Stat & (0x0FU)) | ((_m->RCLSilCU_ModuleTemperature_Val & (0x0FU)) << 4U) ); + _d[1] |= (uint8_t) ( ((_m->RCLSilCU_ModuleTemperature_Val >> 4U) & (0x07U)) | ((_m->RCLSilCU_reserved1 & (0x1FU)) << 3U) ); + _d[2] |= (uint8_t) ( (_m->RCLSilCU_reserved2 & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->RCLSilCU_reserved3 & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->RCLSilCU_reserved4 & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->RCLSilCU_reserved5 & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->RCLSilCU_reserved6 & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->RCLSilCU_reserved7 & (0xFFU)) ); + + *_len = (uint8_t) RCLSilCU_State_DLC; + *_ide = (uint8_t) RCLSilCU_State_IDE; + return RCLSilCU_State_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_RCRSilCU_State_candb(RCRSilCU_State_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->RCRSilCU_Module_Stat = (int8_t) __ext_sig__(( (_d[0] & (0x0FU)) ), 4); + _m->RCRSilCU_ModuleTemperature_Val = (int8_t) __ext_sig__(( ((_d[1] & (0x07U)) << 4U) | ((_d[0] >> 4U) & (0x0FU)) ), 7); + _m->RCRSilCU_reserved1 = (int8_t) __ext_sig__(( ((_d[1] >> 3U) & (0x1FU)) ), 5); + _m->RCRSilCU_reserved2 = (int8_t) __ext_sig__(( (_d[2] & (0xFFU)) ), 8); + _m->RCRSilCU_reserved3 = (int8_t) __ext_sig__(( (_d[3] & (0xFFU)) ), 8); + _m->RCRSilCU_reserved4 = (int8_t) __ext_sig__(( (_d[4] & (0xFFU)) ), 8); + _m->RCRSilCU_reserved5 = (int8_t) __ext_sig__(( (_d[5] & (0xFFU)) ), 8); + _m->RCRSilCU_reserved6 = (int8_t) __ext_sig__(( (_d[6] & (0xFFU)) ), 8); + _m->RCRSilCU_reserved7 = (int8_t) __ext_sig__(( (_d[7] & (0xFFU)) ), 8); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < RCRSilCU_State_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_RCRSilCU_State_candb(&_m->mon1, RCRSilCU_State_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return RCRSilCU_State_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_RCRSilCU_State_candb(RCRSilCU_State_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(RCRSilCU_State_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->RCRSilCU_Module_Stat & (0x0FU)) | ((_m->RCRSilCU_ModuleTemperature_Val & (0x0FU)) << 4U) ); + cframe->Data[1] |= (uint8_t) ( ((_m->RCRSilCU_ModuleTemperature_Val >> 4U) & (0x07U)) | ((_m->RCRSilCU_reserved1 & (0x1FU)) << 3U) ); + cframe->Data[2] |= (uint8_t) ( (_m->RCRSilCU_reserved2 & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->RCRSilCU_reserved3 & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->RCRSilCU_reserved4 & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->RCRSilCU_reserved5 & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->RCRSilCU_reserved6 & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->RCRSilCU_reserved7 & (0xFFU)) ); + + cframe->MsgId = (uint32_t) RCRSilCU_State_CANID; + cframe->DLC = (uint8_t) RCRSilCU_State_DLC; + cframe->IDE = (uint8_t) RCRSilCU_State_IDE; + return RCRSilCU_State_CANID; +} + +#else + +uint32_t Pack_RCRSilCU_State_candb(RCRSilCU_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(RCRSilCU_State_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->RCRSilCU_Module_Stat & (0x0FU)) | ((_m->RCRSilCU_ModuleTemperature_Val & (0x0FU)) << 4U) ); + _d[1] |= (uint8_t) ( ((_m->RCRSilCU_ModuleTemperature_Val >> 4U) & (0x07U)) | ((_m->RCRSilCU_reserved1 & (0x1FU)) << 3U) ); + _d[2] |= (uint8_t) ( (_m->RCRSilCU_reserved2 & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->RCRSilCU_reserved3 & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->RCRSilCU_reserved4 & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->RCRSilCU_reserved5 & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->RCRSilCU_reserved6 & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->RCRSilCU_reserved7 & (0xFFU)) ); + + *_len = (uint8_t) RCRSilCU_State_DLC; + *_ide = (uint8_t) RCRSilCU_State_IDE; + return RCRSilCU_State_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_RDLSilCU_State_candb(RDLSilCU_State_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->RDLSilCU_Module_Stat = (int8_t) __ext_sig__(( (_d[0] & (0x0FU)) ), 4); + _m->RDLSilCU_ModuleTemperature_Val = (int8_t) __ext_sig__(( ((_d[1] & (0x07U)) << 4U) | ((_d[0] >> 4U) & (0x0FU)) ), 7); + _m->RDLSilCU_reserved1 = (int8_t) __ext_sig__(( ((_d[1] >> 3U) & (0x1FU)) ), 5); + _m->RDLSilCU_reserved2 = (int8_t) __ext_sig__(( (_d[2] & (0xFFU)) ), 8); + _m->RDLSilCU_reserved3 = (int8_t) __ext_sig__(( (_d[3] & (0xFFU)) ), 8); + _m->RDLSilCU_reserved4 = (int8_t) __ext_sig__(( (_d[4] & (0xFFU)) ), 8); + _m->RDLSilCU_reserved5 = (int8_t) __ext_sig__(( (_d[5] & (0xFFU)) ), 8); + _m->RDLSilCU_reserved6 = (int8_t) __ext_sig__(( (_d[6] & (0xFFU)) ), 8); + _m->RDLSilCU_reserved7 = (int8_t) __ext_sig__(( (_d[7] & (0xFFU)) ), 8); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < RDLSilCU_State_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_RDLSilCU_State_candb(&_m->mon1, RDLSilCU_State_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return RDLSilCU_State_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_RDLSilCU_State_candb(RDLSilCU_State_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(RDLSilCU_State_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->RDLSilCU_Module_Stat & (0x0FU)) | ((_m->RDLSilCU_ModuleTemperature_Val & (0x0FU)) << 4U) ); + cframe->Data[1] |= (uint8_t) ( ((_m->RDLSilCU_ModuleTemperature_Val >> 4U) & (0x07U)) | ((_m->RDLSilCU_reserved1 & (0x1FU)) << 3U) ); + cframe->Data[2] |= (uint8_t) ( (_m->RDLSilCU_reserved2 & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->RDLSilCU_reserved3 & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( (_m->RDLSilCU_reserved4 & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( (_m->RDLSilCU_reserved5 & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( (_m->RDLSilCU_reserved6 & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->RDLSilCU_reserved7 & (0xFFU)) ); + + cframe->MsgId = (uint32_t) RDLSilCU_State_CANID; + cframe->DLC = (uint8_t) RDLSilCU_State_DLC; + cframe->IDE = (uint8_t) RDLSilCU_State_IDE; + return RDLSilCU_State_CANID; +} + +#else + +uint32_t Pack_RDLSilCU_State_candb(RDLSilCU_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(RDLSilCU_State_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->RDLSilCU_Module_Stat & (0x0FU)) | ((_m->RDLSilCU_ModuleTemperature_Val & (0x0FU)) << 4U) ); + _d[1] |= (uint8_t) ( ((_m->RDLSilCU_ModuleTemperature_Val >> 4U) & (0x07U)) | ((_m->RDLSilCU_reserved1 & (0x1FU)) << 3U) ); + _d[2] |= (uint8_t) ( (_m->RDLSilCU_reserved2 & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->RDLSilCU_reserved3 & (0xFFU)) ); + _d[4] |= (uint8_t) ( (_m->RDLSilCU_reserved4 & (0xFFU)) ); + _d[5] |= (uint8_t) ( (_m->RDLSilCU_reserved5 & (0xFFU)) ); + _d[6] |= (uint8_t) ( (_m->RDLSilCU_reserved6 & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->RDLSilCU_reserved7 & (0xFFU)) ); + + *_len = (uint8_t) RDLSilCU_State_DLC; + *_ide = (uint8_t) RDLSilCU_State_IDE; + return RDLSilCU_State_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_CCPF_BodyTM_Stat_candb(CCPF_BodyTM_Stat_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->CCPF_AutoButtonL_Stat = (uint8_t) ( (_d[0] & (0x03U)) ); + _m->CCPF_TempToggleL_Stat = (uint8_t) ( ((_d[0] >> 2U) & (0x07U)) ); + _m->CCPF_RecButton_Stat = (uint8_t) ( ((_d[0] >> 5U) & (0x03U)) ); + _m->CCPF_FWindowHeatSw_Stat = (uint8_t) ( ((_d[0] >> 7U) & (0x01U)) ); + _m->CCPF_AutoButtonR_Stat = (uint8_t) ( (_d[1] & (0x03U)) ); + _m->CCPF_MuteSw_Stat = (uint8_t) ( ((_d[1] >> 2U) & (0x03U)) ); + _m->CCPF_RWindowHeatSw_Stat = (uint8_t) ( ((_d[1] >> 4U) & (0x01U)) ); + _m->CCPF_TempToggleR_Stat = (uint8_t) ( ((_d[1] >> 5U) & (0x07U)) ); + _m->CCPF_VolAjustSw_Stat = (uint8_t) ( (_d[2] & (0x03U)) ); + _m->CCPF_DefButton_Stat = (uint8_t) ( ((_d[2] >> 2U) & (0x03U)) ); + _m->CCPF_AcMaxButton_Stat = (uint8_t) ( ((_d[2] >> 4U) & (0x03U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < CCPF_BodyTM_Stat_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_CCPF_BodyTM_Stat_candb(&_m->mon1, CCPF_BodyTM_Stat_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return CCPF_BodyTM_Stat_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_CCPF_BodyTM_Stat_candb(CCPF_BodyTM_Stat_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(CCPF_BodyTM_Stat_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->CCPF_AutoButtonL_Stat & (0x03U)) | ((_m->CCPF_TempToggleL_Stat & (0x07U)) << 2U) | ((_m->CCPF_RecButton_Stat & (0x03U)) << 5U) | ((_m->CCPF_FWindowHeatSw_Stat & (0x01U)) << 7U) ); + cframe->Data[1] |= (uint8_t) ( (_m->CCPF_AutoButtonR_Stat & (0x03U)) | ((_m->CCPF_MuteSw_Stat & (0x03U)) << 2U) | ((_m->CCPF_RWindowHeatSw_Stat & (0x01U)) << 4U) | ((_m->CCPF_TempToggleR_Stat & (0x07U)) << 5U) ); + cframe->Data[2] |= (uint8_t) ( (_m->CCPF_VolAjustSw_Stat & (0x03U)) | ((_m->CCPF_DefButton_Stat & (0x03U)) << 2U) | ((_m->CCPF_AcMaxButton_Stat & (0x03U)) << 4U) ); + + cframe->MsgId = (uint32_t) CCPF_BodyTM_Stat_CANID; + cframe->DLC = (uint8_t) CCPF_BodyTM_Stat_DLC; + cframe->IDE = (uint8_t) CCPF_BodyTM_Stat_IDE; + return CCPF_BodyTM_Stat_CANID; +} + +#else + +uint32_t Pack_CCPF_BodyTM_Stat_candb(CCPF_BodyTM_Stat_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(CCPF_BodyTM_Stat_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->CCPF_AutoButtonL_Stat & (0x03U)) | ((_m->CCPF_TempToggleL_Stat & (0x07U)) << 2U) | ((_m->CCPF_RecButton_Stat & (0x03U)) << 5U) | ((_m->CCPF_FWindowHeatSw_Stat & (0x01U)) << 7U) ); + _d[1] |= (uint8_t) ( (_m->CCPF_AutoButtonR_Stat & (0x03U)) | ((_m->CCPF_MuteSw_Stat & (0x03U)) << 2U) | ((_m->CCPF_RWindowHeatSw_Stat & (0x01U)) << 4U) | ((_m->CCPF_TempToggleR_Stat & (0x07U)) << 5U) ); + _d[2] |= (uint8_t) ( (_m->CCPF_VolAjustSw_Stat & (0x03U)) | ((_m->CCPF_DefButton_Stat & (0x03U)) << 2U) | ((_m->CCPF_AcMaxButton_Stat & (0x03U)) << 4U) ); + + *_len = (uint8_t) CCPF_BodyTM_Stat_DLC; + *_ide = (uint8_t) CCPF_BodyTM_Stat_IDE; + return CCPF_BodyTM_Stat_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_IntCOM_Info_Stat_candb(IntCOM_Info_Stat_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->IntCOM_PowerLed_Cmd = (uint8_t) ( (_d[0] & (0x03U)) ); + _m->IntCOM_Intercom_Req = (uint8_t) ( ((_d[0] >> 2U) & (0x01U)) ); + _m->IntCOM_Extercom_Req = (uint8_t) ( ((_d[0] >> 3U) & (0x01U)) ); + _m->IntCOM_Mute_Req = (uint8_t) ( ((_d[0] >> 4U) & (0x01U)) ); + _m->IntCom_MIC_FL = (uint8_t) ( ((_d[0] >> 5U) & (0x01U)) ); + _m->IntCom_MIC_FR = (uint8_t) ( ((_d[0] >> 6U) & (0x01U)) ); + _m->IntCom_MIC_RL = (uint8_t) ( ((_d[0] >> 7U) & (0x01U)) ); + _m->IntCom_MIC_RR = (uint8_t) ( (_d[1] & (0x01U)) ); + _m->IntCOM_ExtcomLMIC_Req = (uint8_t) ( ((_d[1] >> 1U) & (0x01U)) ); + _m->IntCOM_ExtcomRMIC_Req = (uint8_t) ( ((_d[1] >> 2U) & (0x01U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < IntCOM_Info_Stat_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_IntCOM_Info_Stat_candb(&_m->mon1, IntCOM_Info_Stat_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return IntCOM_Info_Stat_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_IntCOM_Info_Stat_candb(IntCOM_Info_Stat_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(IntCOM_Info_Stat_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->IntCOM_PowerLed_Cmd & (0x03U)) | ((_m->IntCOM_Intercom_Req & (0x01U)) << 2U) | ((_m->IntCOM_Extercom_Req & (0x01U)) << 3U) | ((_m->IntCOM_Mute_Req & (0x01U)) << 4U) | ((_m->IntCom_MIC_FL & (0x01U)) << 5U) | ((_m->IntCom_MIC_FR & (0x01U)) << 6U) | ((_m->IntCom_MIC_RL & (0x01U)) << 7U) ); + cframe->Data[1] |= (uint8_t) ( (_m->IntCom_MIC_RR & (0x01U)) | ((_m->IntCOM_ExtcomLMIC_Req & (0x01U)) << 1U) | ((_m->IntCOM_ExtcomRMIC_Req & (0x01U)) << 2U) ); + + cframe->MsgId = (uint32_t) IntCOM_Info_Stat_CANID; + cframe->DLC = (uint8_t) IntCOM_Info_Stat_DLC; + cframe->IDE = (uint8_t) IntCOM_Info_Stat_IDE; + return IntCOM_Info_Stat_CANID; +} + +#else + +uint32_t Pack_IntCOM_Info_Stat_candb(IntCOM_Info_Stat_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(IntCOM_Info_Stat_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->IntCOM_PowerLed_Cmd & (0x03U)) | ((_m->IntCOM_Intercom_Req & (0x01U)) << 2U) | ((_m->IntCOM_Extercom_Req & (0x01U)) << 3U) | ((_m->IntCOM_Mute_Req & (0x01U)) << 4U) | ((_m->IntCom_MIC_FL & (0x01U)) << 5U) | ((_m->IntCom_MIC_FR & (0x01U)) << 6U) | ((_m->IntCom_MIC_RL & (0x01U)) << 7U) ); + _d[1] |= (uint8_t) ( (_m->IntCom_MIC_RR & (0x01U)) | ((_m->IntCOM_ExtcomLMIC_Req & (0x01U)) << 1U) | ((_m->IntCOM_ExtcomRMIC_Req & (0x01U)) << 2U) ); + + *_len = (uint8_t) IntCOM_Info_Stat_DLC; + *_ide = (uint8_t) IntCOM_Info_Stat_IDE; + return IntCOM_Info_Stat_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_LTE_Sum_State2_candb(LTE_Sum_State2_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->LTE_FrameCode_Stat = (uint8_t) ( (_d[0] & (0x0FU)) ); + _m->LTE_Flow_Stat = (uint8_t) ( ((_d[0] >> 4U) & (0x0FU)) ); + _m->LTE_FrameNum_Val = (uint8_t) ( ((_d[0] >> 4U) & (0x0FU)) ); + _m->LTE_DataLenM = (uint16_t) ( ((_d[1] & (0xFFU)) << 4U) | ((_d[0] >> 4U) & (0x0FU)) ); + _m->LTE_DataLenS = (uint8_t) ( ((_d[0] >> 4U) & (0x0FU)) ); + _m->LTE_BlockSize_Val = (uint8_t) ( (_d[1] & (0xFFU)) ); + _m->LTE_Data1_Val = (uint64_t) ( ((uint64_t)(_d[7] & (0xFFU)) << 48U) | ((uint64_t)(_d[6] & (0xFFU)) << 40U) | ((uint64_t)(_d[5] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[3] & (0xFFU)) << 16U) | ((_d[2] & (0xFFU)) << 8U) | (_d[1] & (0xFFU)) ); + _m->LTE_Data3_Val = (uint64_t) ( ((uint64_t)(_d[7] & (0xFFU)) << 48U) | ((uint64_t)(_d[6] & (0xFFU)) << 40U) | ((uint64_t)(_d[5] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[3] & (0xFFU)) << 16U) | ((_d[2] & (0xFFU)) << 8U) | (_d[1] & (0xFFU)) ); + _m->LTE_MinSepTime_Val = (uint8_t) ( (_d[2] & (0xFFU)) ); + _m->LTE_Data2_Val = (uint64_t) ( ((uint64_t)(_d[7] & (0xFFU)) << 40U) | ((uint64_t)(_d[6] & (0xFFU)) << 32U) | ((_d[5] & (0xFFU)) << 24U) | ((_d[4] & (0xFFU)) << 16U) | ((_d[3] & (0xFFU)) << 8U) | (_d[2] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < LTE_Sum_State2_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_LTE_Sum_State2_candb(&_m->mon1, LTE_Sum_State2_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return LTE_Sum_State2_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_LTE_Sum_State2_candb(LTE_Sum_State2_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(LTE_Sum_State2_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->LTE_FrameCode_Stat & (0x0FU)) | ((_m->LTE_Flow_Stat & (0x0FU)) << 4U) | ((_m->LTE_FrameNum_Val & (0x0FU)) << 4U) | ((_m->LTE_DataLenM & (0x0FU)) << 4U) | ((_m->LTE_DataLenS & (0x0FU)) << 4U) ); + cframe->Data[1] |= (uint8_t) ( ((_m->LTE_DataLenM >> 4U) & (0xFFU)) | (_m->LTE_BlockSize_Val & (0xFFU)) | (_m->LTE_Data1_Val & (0xFFU)) | (_m->LTE_Data3_Val & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->LTE_Data1_Val >> 8U) & (0xFFU)) | ((_m->LTE_Data3_Val >> 8U) & (0xFFU)) | (_m->LTE_MinSepTime_Val & (0xFFU)) | (_m->LTE_Data2_Val & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->LTE_Data1_Val >> 16U) & (0xFFU)) | ((_m->LTE_Data3_Val >> 16U) & (0xFFU)) | ((_m->LTE_Data2_Val >> 8U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->LTE_Data1_Val >> 24U) & (0xFFU)) | ((_m->LTE_Data3_Val >> 24U) & (0xFFU)) | ((_m->LTE_Data2_Val >> 16U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->LTE_Data1_Val >> 32U) & (0xFFU)) | ((_m->LTE_Data3_Val >> 32U) & (0xFFU)) | ((_m->LTE_Data2_Val >> 24U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->LTE_Data1_Val >> 40U) & (0xFFU)) | ((_m->LTE_Data3_Val >> 40U) & (0xFFU)) | ((_m->LTE_Data2_Val >> 32U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( ((_m->LTE_Data1_Val >> 48U) & (0xFFU)) | ((_m->LTE_Data3_Val >> 48U) & (0xFFU)) | ((_m->LTE_Data2_Val >> 40U) & (0xFFU)) ); + + cframe->MsgId = (uint32_t) LTE_Sum_State2_CANID; + cframe->DLC = (uint8_t) LTE_Sum_State2_DLC; + cframe->IDE = (uint8_t) LTE_Sum_State2_IDE; + return LTE_Sum_State2_CANID; +} + +#else + +uint32_t Pack_LTE_Sum_State2_candb(LTE_Sum_State2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(LTE_Sum_State2_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->LTE_FrameCode_Stat & (0x0FU)) | ((_m->LTE_Flow_Stat & (0x0FU)) << 4U) | ((_m->LTE_FrameNum_Val & (0x0FU)) << 4U) | ((_m->LTE_DataLenM & (0x0FU)) << 4U) | ((_m->LTE_DataLenS & (0x0FU)) << 4U) ); + _d[1] |= (uint8_t) ( ((_m->LTE_DataLenM >> 4U) & (0xFFU)) | (_m->LTE_BlockSize_Val & (0xFFU)) | (_m->LTE_Data1_Val & (0xFFU)) | (_m->LTE_Data3_Val & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->LTE_Data1_Val >> 8U) & (0xFFU)) | ((_m->LTE_Data3_Val >> 8U) & (0xFFU)) | (_m->LTE_MinSepTime_Val & (0xFFU)) | (_m->LTE_Data2_Val & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->LTE_Data1_Val >> 16U) & (0xFFU)) | ((_m->LTE_Data3_Val >> 16U) & (0xFFU)) | ((_m->LTE_Data2_Val >> 8U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->LTE_Data1_Val >> 24U) & (0xFFU)) | ((_m->LTE_Data3_Val >> 24U) & (0xFFU)) | ((_m->LTE_Data2_Val >> 16U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->LTE_Data1_Val >> 32U) & (0xFFU)) | ((_m->LTE_Data3_Val >> 32U) & (0xFFU)) | ((_m->LTE_Data2_Val >> 24U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->LTE_Data1_Val >> 40U) & (0xFFU)) | ((_m->LTE_Data3_Val >> 40U) & (0xFFU)) | ((_m->LTE_Data2_Val >> 32U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( ((_m->LTE_Data1_Val >> 48U) & (0xFFU)) | ((_m->LTE_Data3_Val >> 48U) & (0xFFU)) | ((_m->LTE_Data2_Val >> 40U) & (0xFFU)) ); + + *_len = (uint8_t) LTE_Sum_State2_DLC; + *_ide = (uint8_t) LTE_Sum_State2_IDE; + return LTE_Sum_State2_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_WChF_FIU_TransferState_candb(WChF_FIU_TransferState_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->WChF_Flow_Stat = (uint8_t) ( (_d[0] & (0x0FU)) ); + _m->WChF_FrameNum_Val = (uint8_t) ( (_d[0] & (0x0FU)) ); + _m->WChF_DataLenM = (uint16_t) ( ((_d[0] & (0x0FU)) << 8U) | (_d[1] & (0xFFU)) ); + _m->WChF_DataLenS = (uint8_t) ( (_d[0] & (0x0FU)) ); + _m->WChF_FrameCode_Stat = (uint8_t) ( ((_d[0] >> 4U) & (0x0FU)) ); + _m->WChF_BlockSize_Val = (uint8_t) ( (_d[1] & (0xFFU)) ); + _m->WChF_Data1_Val = (uint64_t) ( ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + _m->WChF_Data3_Val = (uint64_t) ( ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + _m->WChF_MinSepTime_Val = (uint8_t) ( (_d[2] & (0xFFU)) ); + _m->WChF_Data2_Val = (uint64_t) ( ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < WChF_FIU_TransferState_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_WChF_FIU_TransferState_candb(&_m->mon1, WChF_FIU_TransferState_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return WChF_FIU_TransferState_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_WChF_FIU_TransferState_candb(WChF_FIU_TransferState_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(WChF_FIU_TransferState_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->WChF_Flow_Stat & (0x0FU)) | (_m->WChF_FrameNum_Val & (0x0FU)) | ((_m->WChF_DataLenM >> 8U) & (0x0FU)) | (_m->WChF_DataLenS & (0x0FU)) | ((_m->WChF_FrameCode_Stat & (0x0FU)) << 4U) ); + cframe->Data[1] |= (uint8_t) ( (_m->WChF_DataLenM & (0xFFU)) | (_m->WChF_BlockSize_Val & (0xFFU)) | ((_m->WChF_Data1_Val >> 48U) & (0xFFU)) | ((_m->WChF_Data3_Val >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->WChF_Data1_Val >> 40U) & (0xFFU)) | ((_m->WChF_Data3_Val >> 40U) & (0xFFU)) | (_m->WChF_MinSepTime_Val & (0xFFU)) | ((_m->WChF_Data2_Val >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->WChF_Data1_Val >> 32U) & (0xFFU)) | ((_m->WChF_Data3_Val >> 32U) & (0xFFU)) | ((_m->WChF_Data2_Val >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->WChF_Data1_Val >> 24U) & (0xFFU)) | ((_m->WChF_Data3_Val >> 24U) & (0xFFU)) | ((_m->WChF_Data2_Val >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->WChF_Data1_Val >> 16U) & (0xFFU)) | ((_m->WChF_Data3_Val >> 16U) & (0xFFU)) | ((_m->WChF_Data2_Val >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->WChF_Data1_Val >> 8U) & (0xFFU)) | ((_m->WChF_Data3_Val >> 8U) & (0xFFU)) | ((_m->WChF_Data2_Val >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->WChF_Data1_Val & (0xFFU)) | (_m->WChF_Data3_Val & (0xFFU)) | (_m->WChF_Data2_Val & (0xFFU)) ); + + cframe->MsgId = (uint32_t) WChF_FIU_TransferState_CANID; + cframe->DLC = (uint8_t) WChF_FIU_TransferState_DLC; + cframe->IDE = (uint8_t) WChF_FIU_TransferState_IDE; + return WChF_FIU_TransferState_CANID; +} + +#else + +uint32_t Pack_WChF_FIU_TransferState_candb(WChF_FIU_TransferState_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(WChF_FIU_TransferState_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->WChF_Flow_Stat & (0x0FU)) | (_m->WChF_FrameNum_Val & (0x0FU)) | ((_m->WChF_DataLenM >> 8U) & (0x0FU)) | (_m->WChF_DataLenS & (0x0FU)) | ((_m->WChF_FrameCode_Stat & (0x0FU)) << 4U) ); + _d[1] |= (uint8_t) ( (_m->WChF_DataLenM & (0xFFU)) | (_m->WChF_BlockSize_Val & (0xFFU)) | ((_m->WChF_Data1_Val >> 48U) & (0xFFU)) | ((_m->WChF_Data3_Val >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->WChF_Data1_Val >> 40U) & (0xFFU)) | ((_m->WChF_Data3_Val >> 40U) & (0xFFU)) | (_m->WChF_MinSepTime_Val & (0xFFU)) | ((_m->WChF_Data2_Val >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->WChF_Data1_Val >> 32U) & (0xFFU)) | ((_m->WChF_Data3_Val >> 32U) & (0xFFU)) | ((_m->WChF_Data2_Val >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->WChF_Data1_Val >> 24U) & (0xFFU)) | ((_m->WChF_Data3_Val >> 24U) & (0xFFU)) | ((_m->WChF_Data2_Val >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->WChF_Data1_Val >> 16U) & (0xFFU)) | ((_m->WChF_Data3_Val >> 16U) & (0xFFU)) | ((_m->WChF_Data2_Val >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->WChF_Data1_Val >> 8U) & (0xFFU)) | ((_m->WChF_Data3_Val >> 8U) & (0xFFU)) | ((_m->WChF_Data2_Val >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->WChF_Data1_Val & (0xFFU)) | (_m->WChF_Data3_Val & (0xFFU)) | (_m->WChF_Data2_Val & (0xFFU)) ); + + *_len = (uint8_t) WChF_FIU_TransferState_DLC; + *_ide = (uint8_t) WChF_FIU_TransferState_IDE; + return WChF_FIU_TransferState_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_WChF_TransferState_candb(FIU_WChF_TransferState_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->FIU_Flow_Stat = (uint8_t) ( (_d[0] & (0x0FU)) ); + _m->FIU_FrameNum_Val = (uint8_t) ( (_d[0] & (0x0FU)) ); + _m->FIU_DataLenM = (uint16_t) ( ((_d[0] & (0x0FU)) << 8U) | (_d[1] & (0xFFU)) ); + _m->FIU_DataLenS = (uint8_t) ( (_d[0] & (0x0FU)) ); + _m->FIU_FrameCode_Stat = (uint8_t) ( ((_d[0] >> 4U) & (0x0FU)) ); + _m->FIU_BlockSize_Val = (uint8_t) ( (_d[1] & (0xFFU)) ); + _m->FIU_Data1_Val = (uint64_t) ( ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + _m->FIU_Data3_Val = (uint64_t) ( ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + _m->FIU_MinSepTime_Val = (uint8_t) ( (_d[2] & (0xFFU)) ); + _m->FIU_Data2_Val = (uint64_t) ( ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < FIU_WChF_TransferState_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_FIU_WChF_TransferState_candb(&_m->mon1, FIU_WChF_TransferState_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return FIU_WChF_TransferState_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_FIU_WChF_TransferState_candb(FIU_WChF_TransferState_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_WChF_TransferState_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->FIU_Flow_Stat & (0x0FU)) | (_m->FIU_FrameNum_Val & (0x0FU)) | ((_m->FIU_DataLenM >> 8U) & (0x0FU)) | (_m->FIU_DataLenS & (0x0FU)) | ((_m->FIU_FrameCode_Stat & (0x0FU)) << 4U) ); + cframe->Data[1] |= (uint8_t) ( (_m->FIU_DataLenM & (0xFFU)) | (_m->FIU_BlockSize_Val & (0xFFU)) | ((_m->FIU_Data1_Val >> 48U) & (0xFFU)) | ((_m->FIU_Data3_Val >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->FIU_Data1_Val >> 40U) & (0xFFU)) | ((_m->FIU_Data3_Val >> 40U) & (0xFFU)) | (_m->FIU_MinSepTime_Val & (0xFFU)) | ((_m->FIU_Data2_Val >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->FIU_Data1_Val >> 32U) & (0xFFU)) | ((_m->FIU_Data3_Val >> 32U) & (0xFFU)) | ((_m->FIU_Data2_Val >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->FIU_Data1_Val >> 24U) & (0xFFU)) | ((_m->FIU_Data3_Val >> 24U) & (0xFFU)) | ((_m->FIU_Data2_Val >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->FIU_Data1_Val >> 16U) & (0xFFU)) | ((_m->FIU_Data3_Val >> 16U) & (0xFFU)) | ((_m->FIU_Data2_Val >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->FIU_Data1_Val >> 8U) & (0xFFU)) | ((_m->FIU_Data3_Val >> 8U) & (0xFFU)) | ((_m->FIU_Data2_Val >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->FIU_Data1_Val & (0xFFU)) | (_m->FIU_Data3_Val & (0xFFU)) | (_m->FIU_Data2_Val & (0xFFU)) ); + + cframe->MsgId = (uint32_t) FIU_WChF_TransferState_CANID; + cframe->DLC = (uint8_t) FIU_WChF_TransferState_DLC; + cframe->IDE = (uint8_t) FIU_WChF_TransferState_IDE; + return FIU_WChF_TransferState_CANID; +} + +#else + +uint32_t Pack_FIU_WChF_TransferState_candb(FIU_WChF_TransferState_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(FIU_WChF_TransferState_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->FIU_Flow_Stat & (0x0FU)) | (_m->FIU_FrameNum_Val & (0x0FU)) | ((_m->FIU_DataLenM >> 8U) & (0x0FU)) | (_m->FIU_DataLenS & (0x0FU)) | ((_m->FIU_FrameCode_Stat & (0x0FU)) << 4U) ); + _d[1] |= (uint8_t) ( (_m->FIU_DataLenM & (0xFFU)) | (_m->FIU_BlockSize_Val & (0xFFU)) | ((_m->FIU_Data1_Val >> 48U) & (0xFFU)) | ((_m->FIU_Data3_Val >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->FIU_Data1_Val >> 40U) & (0xFFU)) | ((_m->FIU_Data3_Val >> 40U) & (0xFFU)) | (_m->FIU_MinSepTime_Val & (0xFFU)) | ((_m->FIU_Data2_Val >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->FIU_Data1_Val >> 32U) & (0xFFU)) | ((_m->FIU_Data3_Val >> 32U) & (0xFFU)) | ((_m->FIU_Data2_Val >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->FIU_Data1_Val >> 24U) & (0xFFU)) | ((_m->FIU_Data3_Val >> 24U) & (0xFFU)) | ((_m->FIU_Data2_Val >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->FIU_Data1_Val >> 16U) & (0xFFU)) | ((_m->FIU_Data3_Val >> 16U) & (0xFFU)) | ((_m->FIU_Data2_Val >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->FIU_Data1_Val >> 8U) & (0xFFU)) | ((_m->FIU_Data3_Val >> 8U) & (0xFFU)) | ((_m->FIU_Data2_Val >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->FIU_Data1_Val & (0xFFU)) | (_m->FIU_Data3_Val & (0xFFU)) | (_m->FIU_Data2_Val & (0xFFU)) ); + + *_len = (uint8_t) FIU_WChF_TransferState_DLC; + *_ide = (uint8_t) FIU_WChF_TransferState_IDE; + return FIU_WChF_TransferState_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_VAU_BLE_Device_candb(VAU_BLE_Device_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->VAU_BLEZoneLoc_Stat = (uint8_t) ( (_d[0] & (0x0FU)) ); + _m->VAU_BLEPassword_Val = (uint32_t) ( ((_d[2] & (0xFFU)) << 12U) | ((_d[1] & (0xFFU)) << 4U) | ((_d[0] >> 4U) & (0x0FU)) ); + _m->VAU_BLEDevice_ID = (uint8_t) ( (_d[3] & (0x07U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < VAU_BLE_Device_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_VAU_BLE_Device_candb(&_m->mon1, VAU_BLE_Device_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return VAU_BLE_Device_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_VAU_BLE_Device_candb(VAU_BLE_Device_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(VAU_BLE_Device_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->VAU_BLEZoneLoc_Stat & (0x0FU)) | ((_m->VAU_BLEPassword_Val & (0x0FU)) << 4U) ); + cframe->Data[1] |= (uint8_t) ( ((_m->VAU_BLEPassword_Val >> 4U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->VAU_BLEPassword_Val >> 12U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->VAU_BLEDevice_ID & (0x07U)) ); + + cframe->MsgId = (uint32_t) VAU_BLE_Device_CANID; + cframe->DLC = (uint8_t) VAU_BLE_Device_DLC; + cframe->IDE = (uint8_t) VAU_BLE_Device_IDE; + return VAU_BLE_Device_CANID; +} + +#else + +uint32_t Pack_VAU_BLE_Device_candb(VAU_BLE_Device_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(VAU_BLE_Device_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->VAU_BLEZoneLoc_Stat & (0x0FU)) | ((_m->VAU_BLEPassword_Val & (0x0FU)) << 4U) ); + _d[1] |= (uint8_t) ( ((_m->VAU_BLEPassword_Val >> 4U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->VAU_BLEPassword_Val >> 12U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->VAU_BLEDevice_ID & (0x07U)) ); + + *_len = (uint8_t) VAU_BLE_Device_DLC; + *_ide = (uint8_t) VAU_BLE_Device_IDE; + return VAU_BLE_Device_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_APU_candb(Diag_From_APU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_APU = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_APU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_APU_candb(&_m->mon1, Diag_From_APU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_APU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_APU_candb(Diag_From_APU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_APU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_APU >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_APU >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_APU >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_APU >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_APU >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_APU >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_APU >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_APU & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_APU_CANID; + cframe->DLC = (uint8_t) Diag_From_APU_DLC; + cframe->IDE = (uint8_t) Diag_From_APU_IDE; + return Diag_From_APU_CANID; +} + +#else + +uint32_t Pack_Diag_From_APU_candb(Diag_From_APU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_APU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_APU >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_APU >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_APU >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_APU >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_APU >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_APU >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_APU >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_APU & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_APU_DLC; + *_ide = (uint8_t) Diag_From_APU_IDE; + return Diag_From_APU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SSL_Status_candb(SSL_Status_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->SSL_FootrestAutoClose_Req = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->SSL_Position_Stat = (uint8_t) ( ((_d[0] >> 1U) & (0x07U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < SSL_Status_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_SSL_Status_candb(&_m->mon1, SSL_Status_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return SSL_Status_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_SSL_Status_candb(SSL_Status_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SSL_Status_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->SSL_FootrestAutoClose_Req & (0x01U)) | ((_m->SSL_Position_Stat & (0x07U)) << 1U) ); + + cframe->MsgId = (uint32_t) SSL_Status_CANID; + cframe->DLC = (uint8_t) SSL_Status_DLC; + cframe->IDE = (uint8_t) SSL_Status_IDE; + return SSL_Status_CANID; +} + +#else + +uint32_t Pack_SSL_Status_candb(SSL_Status_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SSL_Status_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->SSL_FootrestAutoClose_Req & (0x01U)) | ((_m->SSL_Position_Stat & (0x07U)) << 1U) ); + + *_len = (uint8_t) SSL_Status_DLC; + *_ide = (uint8_t) SSL_Status_IDE; + return SSL_Status_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SSR_Status_candb(SSR_Status_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->SSR_FootrestAutoClose_Req = (uint8_t) ( (_d[0] & (0x01U)) ); + _m->SSR_Position_Stat = (uint8_t) ( ((_d[0] >> 1U) & (0x07U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < SSR_Status_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_SSR_Status_candb(&_m->mon1, SSR_Status_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return SSR_Status_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_SSR_Status_candb(SSR_Status_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SSR_Status_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->SSR_FootrestAutoClose_Req & (0x01U)) | ((_m->SSR_Position_Stat & (0x07U)) << 1U) ); + + cframe->MsgId = (uint32_t) SSR_Status_CANID; + cframe->DLC = (uint8_t) SSR_Status_DLC; + cframe->IDE = (uint8_t) SSR_Status_IDE; + return SSR_Status_CANID; +} + +#else + +uint32_t Pack_SSR_Status_candb(SSR_Status_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SSR_Status_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->SSR_FootrestAutoClose_Req & (0x01U)) | ((_m->SSR_Position_Stat & (0x07U)) << 1U) ); + + *_len = (uint8_t) SSR_Status_DLC; + *_ide = (uint8_t) SSR_Status_IDE; + return SSR_Status_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_PTG_To_SupplierTool_candb(PTG_To_SupplierTool_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->PTG_To_SupplierTool_Sig = (uint64_t) ( ((uint64_t)(_d[7] & (0xFFU)) << 56U) | ((uint64_t)(_d[6] & (0xFFU)) << 48U) | ((uint64_t)(_d[5] & (0xFFU)) << 40U) | ((uint64_t)(_d[4] & (0xFFU)) << 32U) | ((_d[3] & (0xFFU)) << 24U) | ((_d[2] & (0xFFU)) << 16U) | ((_d[1] & (0xFFU)) << 8U) | (_d[0] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < PTG_To_SupplierTool_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_PTG_To_SupplierTool_candb(&_m->mon1, PTG_To_SupplierTool_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return PTG_To_SupplierTool_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_PTG_To_SupplierTool_candb(PTG_To_SupplierTool_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(PTG_To_SupplierTool_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->PTG_To_SupplierTool_Sig & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->PTG_To_SupplierTool_Sig >> 8U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->PTG_To_SupplierTool_Sig >> 16U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->PTG_To_SupplierTool_Sig >> 24U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->PTG_To_SupplierTool_Sig >> 32U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->PTG_To_SupplierTool_Sig >> 40U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->PTG_To_SupplierTool_Sig >> 48U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( ((_m->PTG_To_SupplierTool_Sig >> 56U) & (0xFFU)) ); + + cframe->MsgId = (uint32_t) PTG_To_SupplierTool_CANID; + cframe->DLC = (uint8_t) PTG_To_SupplierTool_DLC; + cframe->IDE = (uint8_t) PTG_To_SupplierTool_IDE; + return PTG_To_SupplierTool_CANID; +} + +#else + +uint32_t Pack_PTG_To_SupplierTool_candb(PTG_To_SupplierTool_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(PTG_To_SupplierTool_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->PTG_To_SupplierTool_Sig & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->PTG_To_SupplierTool_Sig >> 8U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->PTG_To_SupplierTool_Sig >> 16U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->PTG_To_SupplierTool_Sig >> 24U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->PTG_To_SupplierTool_Sig >> 32U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->PTG_To_SupplierTool_Sig >> 40U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->PTG_To_SupplierTool_Sig >> 48U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( ((_m->PTG_To_SupplierTool_Sig >> 56U) & (0xFFU)) ); + + *_len = (uint8_t) PTG_To_SupplierTool_DLC; + *_ide = (uint8_t) PTG_To_SupplierTool_IDE; + return PTG_To_SupplierTool_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SupplierTool_To_PTG_candb(SupplierTool_To_PTG_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->SupplierTool_To_PTG_Sig = (uint64_t) ( ((uint64_t)(_d[7] & (0xFFU)) << 56U) | ((uint64_t)(_d[6] & (0xFFU)) << 48U) | ((uint64_t)(_d[5] & (0xFFU)) << 40U) | ((uint64_t)(_d[4] & (0xFFU)) << 32U) | ((_d[3] & (0xFFU)) << 24U) | ((_d[2] & (0xFFU)) << 16U) | ((_d[1] & (0xFFU)) << 8U) | (_d[0] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < SupplierTool_To_PTG_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_SupplierTool_To_PTG_candb(&_m->mon1, SupplierTool_To_PTG_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return SupplierTool_To_PTG_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_SupplierTool_To_PTG_candb(SupplierTool_To_PTG_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SupplierTool_To_PTG_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( (_m->SupplierTool_To_PTG_Sig & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->SupplierTool_To_PTG_Sig >> 8U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->SupplierTool_To_PTG_Sig >> 16U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->SupplierTool_To_PTG_Sig >> 24U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->SupplierTool_To_PTG_Sig >> 32U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->SupplierTool_To_PTG_Sig >> 40U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->SupplierTool_To_PTG_Sig >> 48U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( ((_m->SupplierTool_To_PTG_Sig >> 56U) & (0xFFU)) ); + + cframe->MsgId = (uint32_t) SupplierTool_To_PTG_CANID; + cframe->DLC = (uint8_t) SupplierTool_To_PTG_DLC; + cframe->IDE = (uint8_t) SupplierTool_To_PTG_IDE; + return SupplierTool_To_PTG_CANID; +} + +#else + +uint32_t Pack_SupplierTool_To_PTG_candb(SupplierTool_To_PTG_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(SupplierTool_To_PTG_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( (_m->SupplierTool_To_PTG_Sig & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->SupplierTool_To_PTG_Sig >> 8U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->SupplierTool_To_PTG_Sig >> 16U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->SupplierTool_To_PTG_Sig >> 24U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->SupplierTool_To_PTG_Sig >> 32U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->SupplierTool_To_PTG_Sig >> 40U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->SupplierTool_To_PTG_Sig >> 48U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( ((_m->SupplierTool_To_PTG_Sig >> 56U) & (0xFFU)) ); + + *_len = (uint8_t) SupplierTool_To_PTG_DLC; + *_ide = (uint8_t) SupplierTool_To_PTG_IDE; + return SupplierTool_To_PTG_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_CCPF_candb(Diag_From_CCPF_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_CCPF = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_CCPF_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_CCPF_candb(&_m->mon1, Diag_From_CCPF_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_CCPF_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_CCPF_candb(Diag_From_CCPF_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_CCPF_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_CCPF >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_CCPF >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_CCPF >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_CCPF >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_CCPF >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_CCPF >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_CCPF >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_CCPF & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_CCPF_CANID; + cframe->DLC = (uint8_t) Diag_From_CCPF_DLC; + cframe->IDE = (uint8_t) Diag_From_CCPF_IDE; + return Diag_From_CCPF_CANID; +} + +#else + +uint32_t Pack_Diag_From_CCPF_candb(Diag_From_CCPF_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_CCPF_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_CCPF >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_CCPF >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_CCPF >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_CCPF >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_CCPF >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_CCPF >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_CCPF >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_CCPF & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_CCPF_DLC; + *_ide = (uint8_t) Diag_From_CCPF_IDE; + return Diag_From_CCPF_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_CCPF_candb(Diag_To_CCPF_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_CCPF = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_CCPF_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_CCPF_candb(&_m->mon1, Diag_To_CCPF_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_CCPF_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_CCPF_candb(Diag_To_CCPF_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_CCPF_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_CCPF >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_CCPF >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_CCPF >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_CCPF >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_CCPF >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_CCPF >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_CCPF >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_CCPF & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_CCPF_CANID; + cframe->DLC = (uint8_t) Diag_To_CCPF_DLC; + cframe->IDE = (uint8_t) Diag_To_CCPF_IDE; + return Diag_To_CCPF_CANID; +} + +#else + +uint32_t Pack_Diag_To_CCPF_candb(Diag_To_CCPF_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_CCPF_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_CCPF >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_CCPF >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_CCPF >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_CCPF >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_CCPF >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_CCPF >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_CCPF >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_CCPF & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_CCPF_DLC; + *_ide = (uint8_t) Diag_To_CCPF_IDE; + return Diag_To_CCPF_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_CCPR_candb(Diag_From_CCPR_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_CCPR = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_CCPR_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_CCPR_candb(&_m->mon1, Diag_From_CCPR_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_CCPR_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_CCPR_candb(Diag_From_CCPR_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_CCPR_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_CCPR >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_CCPR >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_CCPR >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_CCPR >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_CCPR >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_CCPR >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_CCPR >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_CCPR & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_CCPR_CANID; + cframe->DLC = (uint8_t) Diag_From_CCPR_DLC; + cframe->IDE = (uint8_t) Diag_From_CCPR_IDE; + return Diag_From_CCPR_CANID; +} + +#else + +uint32_t Pack_Diag_From_CCPR_candb(Diag_From_CCPR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_CCPR_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_CCPR >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_CCPR >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_CCPR >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_CCPR >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_CCPR >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_CCPR >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_CCPR >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_CCPR & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_CCPR_DLC; + *_ide = (uint8_t) Diag_From_CCPR_IDE; + return Diag_From_CCPR_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_CCPR_candb(Diag_To_CCPR_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_CCPR = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_CCPR_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_CCPR_candb(&_m->mon1, Diag_To_CCPR_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_CCPR_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_CCPR_candb(Diag_To_CCPR_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_CCPR_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_CCPR >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_CCPR >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_CCPR >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_CCPR >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_CCPR >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_CCPR >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_CCPR >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_CCPR & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_CCPR_CANID; + cframe->DLC = (uint8_t) Diag_To_CCPR_DLC; + cframe->IDE = (uint8_t) Diag_To_CCPR_IDE; + return Diag_To_CCPR_CANID; +} + +#else + +uint32_t Pack_Diag_To_CCPR_candb(Diag_To_CCPR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_CCPR_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_CCPR >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_CCPR >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_CCPR >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_CCPR >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_CCPR >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_CCPR >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_CCPR >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_CCPR & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_CCPR_DLC; + *_ide = (uint8_t) Diag_To_CCPR_IDE; + return Diag_To_CCPR_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_SSL_candb(Diag_To_SSL_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_SSL = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_SSL_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_SSL_candb(&_m->mon1, Diag_To_SSL_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_SSL_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_SSL_candb(Diag_To_SSL_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_SSL_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_SSL >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_SSL >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_SSL >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_SSL >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_SSL >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_SSL >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_SSL >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_SSL & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_SSL_CANID; + cframe->DLC = (uint8_t) Diag_To_SSL_DLC; + cframe->IDE = (uint8_t) Diag_To_SSL_IDE; + return Diag_To_SSL_CANID; +} + +#else + +uint32_t Pack_Diag_To_SSL_candb(Diag_To_SSL_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_SSL_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_SSL >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_SSL >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_SSL >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_SSL >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_SSL >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_SSL >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_SSL >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_SSL & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_SSL_DLC; + *_ide = (uint8_t) Diag_To_SSL_IDE; + return Diag_To_SSL_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_SSR_candb(Diag_To_SSR_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_SSR = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_SSR_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_SSR_candb(&_m->mon1, Diag_To_SSR_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_SSR_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_SSR_candb(Diag_To_SSR_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_SSR_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_SSR >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_SSR >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_SSR >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_SSR >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_SSR >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_SSR >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_SSR >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_SSR & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_SSR_CANID; + cframe->DLC = (uint8_t) Diag_To_SSR_DLC; + cframe->IDE = (uint8_t) Diag_To_SSR_IDE; + return Diag_To_SSR_CANID; +} + +#else + +uint32_t Pack_Diag_To_SSR_candb(Diag_To_SSR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_SSR_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_SSR >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_SSR >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_SSR >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_SSR >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_SSR >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_SSR >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_SSR >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_SSR & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_SSR_DLC; + *_ide = (uint8_t) Diag_To_SSR_IDE; + return Diag_To_SSR_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_SSL_candb(Diag_From_SSL_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_SSL = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_SSL_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_SSL_candb(&_m->mon1, Diag_From_SSL_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_SSL_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_SSL_candb(Diag_From_SSL_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_SSL_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_SSL >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_SSL >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_SSL >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_SSL >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_SSL >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_SSL >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_SSL >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_SSL & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_SSL_CANID; + cframe->DLC = (uint8_t) Diag_From_SSL_DLC; + cframe->IDE = (uint8_t) Diag_From_SSL_IDE; + return Diag_From_SSL_CANID; +} + +#else + +uint32_t Pack_Diag_From_SSL_candb(Diag_From_SSL_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_SSL_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_SSL >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_SSL >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_SSL >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_SSL >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_SSL >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_SSL >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_SSL >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_SSL & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_SSL_DLC; + *_ide = (uint8_t) Diag_From_SSL_IDE; + return Diag_From_SSL_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_FCSilCU_candb(Diag_To_FCSilCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_FCSilCU = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_FCSilCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_FCSilCU_candb(&_m->mon1, Diag_To_FCSilCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_FCSilCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_FCSilCU_candb(Diag_To_FCSilCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_FCSilCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_FCSilCU >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_FCSilCU >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_FCSilCU >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_FCSilCU >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_FCSilCU >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_FCSilCU >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_FCSilCU >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_FCSilCU & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_FCSilCU_CANID; + cframe->DLC = (uint8_t) Diag_To_FCSilCU_DLC; + cframe->IDE = (uint8_t) Diag_To_FCSilCU_IDE; + return Diag_To_FCSilCU_CANID; +} + +#else + +uint32_t Pack_Diag_To_FCSilCU_candb(Diag_To_FCSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_FCSilCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_FCSilCU >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_FCSilCU >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_FCSilCU >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_FCSilCU >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_FCSilCU >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_FCSilCU >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_FCSilCU >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_FCSilCU & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_FCSilCU_DLC; + *_ide = (uint8_t) Diag_To_FCSilCU_IDE; + return Diag_To_FCSilCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_SSR_candb(Diag_From_SSR_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_SSR = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_SSR_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_SSR_candb(&_m->mon1, Diag_From_SSR_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_SSR_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_SSR_candb(Diag_From_SSR_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_SSR_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_SSR >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_SSR >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_SSR >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_SSR >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_SSR >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_SSR >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_SSR >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_SSR & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_SSR_CANID; + cframe->DLC = (uint8_t) Diag_From_SSR_DLC; + cframe->IDE = (uint8_t) Diag_From_SSR_IDE; + return Diag_From_SSR_CANID; +} + +#else + +uint32_t Pack_Diag_From_SSR_candb(Diag_From_SSR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_SSR_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_SSR >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_SSR >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_SSR >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_SSR >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_SSR >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_SSR >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_SSR >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_SSR & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_SSR_DLC; + *_ide = (uint8_t) Diag_From_SSR_IDE; + return Diag_From_SSR_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_FLDSilCU_candb(Diag_To_FLDSilCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_FLDSilCU = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_FLDSilCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_FLDSilCU_candb(&_m->mon1, Diag_To_FLDSilCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_FLDSilCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_FLDSilCU_candb(Diag_To_FLDSilCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_FLDSilCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_FLDSilCU >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_FLDSilCU >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_FLDSilCU >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_FLDSilCU >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_FLDSilCU >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_FLDSilCU >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_FLDSilCU >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_FLDSilCU & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_FLDSilCU_CANID; + cframe->DLC = (uint8_t) Diag_To_FLDSilCU_DLC; + cframe->IDE = (uint8_t) Diag_To_FLDSilCU_IDE; + return Diag_To_FLDSilCU_CANID; +} + +#else + +uint32_t Pack_Diag_To_FLDSilCU_candb(Diag_To_FLDSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_FLDSilCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_FLDSilCU >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_FLDSilCU >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_FLDSilCU >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_FLDSilCU >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_FLDSilCU >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_FLDSilCU >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_FLDSilCU >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_FLDSilCU & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_FLDSilCU_DLC; + *_ide = (uint8_t) Diag_To_FLDSilCU_IDE; + return Diag_To_FLDSilCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_FRDSilCU_candb(Diag_To_FRDSilCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_FRDSilCU = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_FRDSilCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_FRDSilCU_candb(&_m->mon1, Diag_To_FRDSilCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_FRDSilCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_FRDSilCU_candb(Diag_To_FRDSilCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_FRDSilCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_FRDSilCU >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_FRDSilCU >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_FRDSilCU >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_FRDSilCU >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_FRDSilCU >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_FRDSilCU >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_FRDSilCU >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_FRDSilCU & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_FRDSilCU_CANID; + cframe->DLC = (uint8_t) Diag_To_FRDSilCU_DLC; + cframe->IDE = (uint8_t) Diag_To_FRDSilCU_IDE; + return Diag_To_FRDSilCU_CANID; +} + +#else + +uint32_t Pack_Diag_To_FRDSilCU_candb(Diag_To_FRDSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_FRDSilCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_FRDSilCU >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_FRDSilCU >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_FRDSilCU >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_FRDSilCU >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_FRDSilCU >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_FRDSilCU >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_FRDSilCU >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_FRDSilCU & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_FRDSilCU_DLC; + *_ide = (uint8_t) Diag_To_FRDSilCU_IDE; + return Diag_To_FRDSilCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_ICLSilCU_candb(Diag_To_ICLSilCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_ICLSilCU = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_ICLSilCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_ICLSilCU_candb(&_m->mon1, Diag_To_ICLSilCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_ICLSilCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_ICLSilCU_candb(Diag_To_ICLSilCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_ICLSilCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_ICLSilCU >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_ICLSilCU >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_ICLSilCU >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_ICLSilCU >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_ICLSilCU >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_ICLSilCU >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_ICLSilCU >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_ICLSilCU & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_ICLSilCU_CANID; + cframe->DLC = (uint8_t) Diag_To_ICLSilCU_DLC; + cframe->IDE = (uint8_t) Diag_To_ICLSilCU_IDE; + return Diag_To_ICLSilCU_CANID; +} + +#else + +uint32_t Pack_Diag_To_ICLSilCU_candb(Diag_To_ICLSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_ICLSilCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_ICLSilCU >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_ICLSilCU >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_ICLSilCU >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_ICLSilCU >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_ICLSilCU >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_ICLSilCU >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_ICLSilCU >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_ICLSilCU & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_ICLSilCU_DLC; + *_ide = (uint8_t) Diag_To_ICLSilCU_IDE; + return Diag_To_ICLSilCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_FCSilCU_candb(Diag_From_FCSilCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_FCSilCU = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_FCSilCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_FCSilCU_candb(&_m->mon1, Diag_From_FCSilCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_FCSilCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_FCSilCU_candb(Diag_From_FCSilCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_FCSilCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_FCSilCU >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_FCSilCU >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_FCSilCU >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_FCSilCU >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_FCSilCU >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_FCSilCU >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_FCSilCU >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_FCSilCU & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_FCSilCU_CANID; + cframe->DLC = (uint8_t) Diag_From_FCSilCU_DLC; + cframe->IDE = (uint8_t) Diag_From_FCSilCU_IDE; + return Diag_From_FCSilCU_CANID; +} + +#else + +uint32_t Pack_Diag_From_FCSilCU_candb(Diag_From_FCSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_FCSilCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_FCSilCU >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_FCSilCU >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_FCSilCU >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_FCSilCU >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_FCSilCU >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_FCSilCU >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_FCSilCU >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_FCSilCU & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_FCSilCU_DLC; + *_ide = (uint8_t) Diag_From_FCSilCU_IDE; + return Diag_From_FCSilCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_FLDSilCU_candb(Diag_From_FLDSilCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_FLDSilCU = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_FLDSilCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_FLDSilCU_candb(&_m->mon1, Diag_From_FLDSilCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_FLDSilCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_FLDSilCU_candb(Diag_From_FLDSilCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_FLDSilCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_FLDSilCU >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_FLDSilCU >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_FLDSilCU >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_FLDSilCU >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_FLDSilCU >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_FLDSilCU >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_FLDSilCU >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_FLDSilCU & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_FLDSilCU_CANID; + cframe->DLC = (uint8_t) Diag_From_FLDSilCU_DLC; + cframe->IDE = (uint8_t) Diag_From_FLDSilCU_IDE; + return Diag_From_FLDSilCU_CANID; +} + +#else + +uint32_t Pack_Diag_From_FLDSilCU_candb(Diag_From_FLDSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_FLDSilCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_FLDSilCU >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_FLDSilCU >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_FLDSilCU >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_FLDSilCU >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_FLDSilCU >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_FLDSilCU >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_FLDSilCU >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_FLDSilCU & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_FLDSilCU_DLC; + *_ide = (uint8_t) Diag_From_FLDSilCU_IDE; + return Diag_From_FLDSilCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_FRDSilCU_candb(Diag_From_FRDSilCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_FRDSilCU = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_FRDSilCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_FRDSilCU_candb(&_m->mon1, Diag_From_FRDSilCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_FRDSilCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_FRDSilCU_candb(Diag_From_FRDSilCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_FRDSilCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_FRDSilCU >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_FRDSilCU >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_FRDSilCU >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_FRDSilCU >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_FRDSilCU >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_FRDSilCU >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_FRDSilCU >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_FRDSilCU & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_FRDSilCU_CANID; + cframe->DLC = (uint8_t) Diag_From_FRDSilCU_DLC; + cframe->IDE = (uint8_t) Diag_From_FRDSilCU_IDE; + return Diag_From_FRDSilCU_CANID; +} + +#else + +uint32_t Pack_Diag_From_FRDSilCU_candb(Diag_From_FRDSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_FRDSilCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_FRDSilCU >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_FRDSilCU >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_FRDSilCU >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_FRDSilCU >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_FRDSilCU >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_FRDSilCU >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_FRDSilCU >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_FRDSilCU & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_FRDSilCU_DLC; + *_ide = (uint8_t) Diag_From_FRDSilCU_IDE; + return Diag_From_FRDSilCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_ICLSilCU_candb(Diag_From_ICLSilCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_ICLSilCU = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_ICLSilCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_ICLSilCU_candb(&_m->mon1, Diag_From_ICLSilCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_ICLSilCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_ICLSilCU_candb(Diag_From_ICLSilCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_ICLSilCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_ICLSilCU >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_ICLSilCU >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_ICLSilCU >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_ICLSilCU >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_ICLSilCU >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_ICLSilCU >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_ICLSilCU >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_ICLSilCU & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_ICLSilCU_CANID; + cframe->DLC = (uint8_t) Diag_From_ICLSilCU_DLC; + cframe->IDE = (uint8_t) Diag_From_ICLSilCU_IDE; + return Diag_From_ICLSilCU_CANID; +} + +#else + +uint32_t Pack_Diag_From_ICLSilCU_candb(Diag_From_ICLSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_ICLSilCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_ICLSilCU >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_ICLSilCU >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_ICLSilCU >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_ICLSilCU >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_ICLSilCU >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_ICLSilCU >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_ICLSilCU >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_ICLSilCU & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_ICLSilCU_DLC; + *_ide = (uint8_t) Diag_From_ICLSilCU_IDE; + return Diag_From_ICLSilCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_APU_candb(Diag_To_APU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_APU = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_APU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_APU_candb(&_m->mon1, Diag_To_APU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_APU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_APU_candb(Diag_To_APU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_APU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_APU >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_APU >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_APU >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_APU >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_APU >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_APU >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_APU >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_APU & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_APU_CANID; + cframe->DLC = (uint8_t) Diag_To_APU_DLC; + cframe->IDE = (uint8_t) Diag_To_APU_IDE; + return Diag_To_APU_CANID; +} + +#else + +uint32_t Pack_Diag_To_APU_candb(Diag_To_APU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_APU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_APU >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_APU >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_APU >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_APU >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_APU >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_APU >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_APU >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_APU & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_APU_DLC; + *_ide = (uint8_t) Diag_To_APU_IDE; + return Diag_To_APU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_FTCU_candb(Diag_To_FTCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_FTCU_Sig = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_FTCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_FTCU_candb(&_m->mon1, Diag_To_FTCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_FTCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_FTCU_candb(Diag_To_FTCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_FTCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_FTCU_Sig >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_FTCU_Sig >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_FTCU_Sig >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_FTCU_Sig >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_FTCU_Sig >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_FTCU_Sig >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_FTCU_Sig >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_FTCU_Sig & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_FTCU_CANID; + cframe->DLC = (uint8_t) Diag_To_FTCU_DLC; + cframe->IDE = (uint8_t) Diag_To_FTCU_IDE; + return Diag_To_FTCU_CANID; +} + +#else + +uint32_t Pack_Diag_To_FTCU_candb(Diag_To_FTCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_FTCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_FTCU_Sig >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_FTCU_Sig >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_FTCU_Sig >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_FTCU_Sig >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_FTCU_Sig >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_FTCU_Sig >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_FTCU_Sig >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_FTCU_Sig & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_FTCU_DLC; + *_ide = (uint8_t) Diag_To_FTCU_IDE; + return Diag_To_FTCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_FTCU_candb(Diag_From_FTCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_FTCU = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_FTCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_FTCU_candb(&_m->mon1, Diag_From_FTCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_FTCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_FTCU_candb(Diag_From_FTCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_FTCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_FTCU >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_FTCU >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_FTCU >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_FTCU >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_FTCU >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_FTCU >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_FTCU >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_FTCU & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_FTCU_CANID; + cframe->DLC = (uint8_t) Diag_From_FTCU_DLC; + cframe->IDE = (uint8_t) Diag_From_FTCU_IDE; + return Diag_From_FTCU_CANID; +} + +#else + +uint32_t Pack_Diag_From_FTCU_candb(Diag_From_FTCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_FTCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_FTCU >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_FTCU >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_FTCU >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_FTCU >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_FTCU >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_FTCU >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_FTCU >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_FTCU & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_FTCU_DLC; + *_ide = (uint8_t) Diag_From_FTCU_IDE; + return Diag_From_FTCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_Sroof_candb(Diag_To_Sroof_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_Sroof = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_Sroof_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_Sroof_candb(&_m->mon1, Diag_To_Sroof_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_Sroof_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_Sroof_candb(Diag_To_Sroof_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_Sroof_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_Sroof >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_Sroof >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_Sroof >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_Sroof >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_Sroof >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_Sroof >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_Sroof >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_Sroof & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_Sroof_CANID; + cframe->DLC = (uint8_t) Diag_To_Sroof_DLC; + cframe->IDE = (uint8_t) Diag_To_Sroof_IDE; + return Diag_To_Sroof_CANID; +} + +#else + +uint32_t Pack_Diag_To_Sroof_candb(Diag_To_Sroof_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_Sroof_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_Sroof >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_Sroof >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_Sroof >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_Sroof >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_Sroof >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_Sroof >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_Sroof >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_Sroof & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_Sroof_DLC; + *_ide = (uint8_t) Diag_To_Sroof_IDE; + return Diag_To_Sroof_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_SRoof_candb(Diag_From_SRoof_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_SRoof = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_SRoof_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_SRoof_candb(&_m->mon1, Diag_From_SRoof_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_SRoof_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_SRoof_candb(Diag_From_SRoof_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_SRoof_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_SRoof >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_SRoof >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_SRoof >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_SRoof >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_SRoof >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_SRoof >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_SRoof >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_SRoof & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_SRoof_CANID; + cframe->DLC = (uint8_t) Diag_From_SRoof_DLC; + cframe->IDE = (uint8_t) Diag_From_SRoof_IDE; + return Diag_From_SRoof_CANID; +} + +#else + +uint32_t Pack_Diag_From_SRoof_candb(Diag_From_SRoof_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_SRoof_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_SRoof >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_SRoof >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_SRoof >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_SRoof >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_SRoof >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_SRoof >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_SRoof >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_SRoof & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_SRoof_DLC; + *_ide = (uint8_t) Diag_From_SRoof_IDE; + return Diag_From_SRoof_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_ICRSilCU_candb(Diag_To_ICRSilCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_ICRSilCU = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_ICRSilCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_ICRSilCU_candb(&_m->mon1, Diag_To_ICRSilCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_ICRSilCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_ICRSilCU_candb(Diag_To_ICRSilCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_ICRSilCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_ICRSilCU >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_ICRSilCU >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_ICRSilCU >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_ICRSilCU >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_ICRSilCU >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_ICRSilCU >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_ICRSilCU >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_ICRSilCU & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_ICRSilCU_CANID; + cframe->DLC = (uint8_t) Diag_To_ICRSilCU_DLC; + cframe->IDE = (uint8_t) Diag_To_ICRSilCU_IDE; + return Diag_To_ICRSilCU_CANID; +} + +#else + +uint32_t Pack_Diag_To_ICRSilCU_candb(Diag_To_ICRSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_ICRSilCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_ICRSilCU >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_ICRSilCU >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_ICRSilCU >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_ICRSilCU >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_ICRSilCU >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_ICRSilCU >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_ICRSilCU >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_ICRSilCU & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_ICRSilCU_DLC; + *_ide = (uint8_t) Diag_To_ICRSilCU_IDE; + return Diag_To_ICRSilCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_LB_pSilCU_candb(Diag_To_LB_pSilCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_LB_pSilCU = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_LB_pSilCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_LB_pSilCU_candb(&_m->mon1, Diag_To_LB_pSilCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_LB_pSilCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_LB_pSilCU_candb(Diag_To_LB_pSilCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_LB_pSilCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_LB_pSilCU >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_LB_pSilCU >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_LB_pSilCU >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_LB_pSilCU >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_LB_pSilCU >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_LB_pSilCU >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_LB_pSilCU >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_LB_pSilCU & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_LB_pSilCU_CANID; + cframe->DLC = (uint8_t) Diag_To_LB_pSilCU_DLC; + cframe->IDE = (uint8_t) Diag_To_LB_pSilCU_IDE; + return Diag_To_LB_pSilCU_CANID; +} + +#else + +uint32_t Pack_Diag_To_LB_pSilCU_candb(Diag_To_LB_pSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_LB_pSilCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_LB_pSilCU >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_LB_pSilCU >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_LB_pSilCU >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_LB_pSilCU >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_LB_pSilCU >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_LB_pSilCU >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_LB_pSilCU >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_LB_pSilCU & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_LB_pSilCU_DLC; + *_ide = (uint8_t) Diag_To_LB_pSilCU_IDE; + return Diag_To_LB_pSilCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_PLSilCU_candb(Diag_To_PLSilCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_PLSilCU = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_PLSilCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_PLSilCU_candb(&_m->mon1, Diag_To_PLSilCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_PLSilCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_PLSilCU_candb(Diag_To_PLSilCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_PLSilCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_PLSilCU >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_PLSilCU >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_PLSilCU >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_PLSilCU >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_PLSilCU >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_PLSilCU >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_PLSilCU >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_PLSilCU & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_PLSilCU_CANID; + cframe->DLC = (uint8_t) Diag_To_PLSilCU_DLC; + cframe->IDE = (uint8_t) Diag_To_PLSilCU_IDE; + return Diag_To_PLSilCU_CANID; +} + +#else + +uint32_t Pack_Diag_To_PLSilCU_candb(Diag_To_PLSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_PLSilCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_PLSilCU >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_PLSilCU >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_PLSilCU >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_PLSilCU >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_PLSilCU >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_PLSilCU >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_PLSilCU >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_PLSilCU & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_PLSilCU_DLC; + *_ide = (uint8_t) Diag_To_PLSilCU_IDE; + return Diag_To_PLSilCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_PRSilCU_candb(Diag_To_PRSilCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_PRSilCU = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_PRSilCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_PRSilCU_candb(&_m->mon1, Diag_To_PRSilCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_PRSilCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_PRSilCU_candb(Diag_To_PRSilCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_PRSilCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_PRSilCU >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_PRSilCU >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_PRSilCU >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_PRSilCU >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_PRSilCU >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_PRSilCU >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_PRSilCU >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_PRSilCU & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_PRSilCU_CANID; + cframe->DLC = (uint8_t) Diag_To_PRSilCU_DLC; + cframe->IDE = (uint8_t) Diag_To_PRSilCU_IDE; + return Diag_To_PRSilCU_CANID; +} + +#else + +uint32_t Pack_Diag_To_PRSilCU_candb(Diag_To_PRSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_PRSilCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_PRSilCU >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_PRSilCU >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_PRSilCU >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_PRSilCU >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_PRSilCU >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_PRSilCU >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_PRSilCU >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_PRSilCU & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_PRSilCU_DLC; + *_ide = (uint8_t) Diag_To_PRSilCU_IDE; + return Diag_To_PRSilCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_RB_pSilCU_candb(Diag_To_RB_pSilCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_RB_pSilCU = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_RB_pSilCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_RB_pSilCU_candb(&_m->mon1, Diag_To_RB_pSilCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_RB_pSilCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_RB_pSilCU_candb(Diag_To_RB_pSilCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_RB_pSilCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_RB_pSilCU >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_RB_pSilCU >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_RB_pSilCU >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_RB_pSilCU >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_RB_pSilCU >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_RB_pSilCU >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_RB_pSilCU >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_RB_pSilCU & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_RB_pSilCU_CANID; + cframe->DLC = (uint8_t) Diag_To_RB_pSilCU_DLC; + cframe->IDE = (uint8_t) Diag_To_RB_pSilCU_IDE; + return Diag_To_RB_pSilCU_CANID; +} + +#else + +uint32_t Pack_Diag_To_RB_pSilCU_candb(Diag_To_RB_pSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_RB_pSilCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_RB_pSilCU >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_RB_pSilCU >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_RB_pSilCU >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_RB_pSilCU >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_RB_pSilCU >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_RB_pSilCU >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_RB_pSilCU >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_RB_pSilCU & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_RB_pSilCU_DLC; + *_ide = (uint8_t) Diag_To_RB_pSilCU_IDE; + return Diag_To_RB_pSilCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_ICRSilCU_candb(Diag_From_ICRSilCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_ICRSilCU = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_ICRSilCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_ICRSilCU_candb(&_m->mon1, Diag_From_ICRSilCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_ICRSilCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_ICRSilCU_candb(Diag_From_ICRSilCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_ICRSilCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_ICRSilCU >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_ICRSilCU >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_ICRSilCU >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_ICRSilCU >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_ICRSilCU >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_ICRSilCU >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_ICRSilCU >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_ICRSilCU & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_ICRSilCU_CANID; + cframe->DLC = (uint8_t) Diag_From_ICRSilCU_DLC; + cframe->IDE = (uint8_t) Diag_From_ICRSilCU_IDE; + return Diag_From_ICRSilCU_CANID; +} + +#else + +uint32_t Pack_Diag_From_ICRSilCU_candb(Diag_From_ICRSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_ICRSilCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_ICRSilCU >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_ICRSilCU >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_ICRSilCU >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_ICRSilCU >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_ICRSilCU >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_ICRSilCU >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_ICRSilCU >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_ICRSilCU & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_ICRSilCU_DLC; + *_ide = (uint8_t) Diag_From_ICRSilCU_IDE; + return Diag_From_ICRSilCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_LB_pSilCU_candb(Diag_From_LB_pSilCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_LB_pSilCU = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_LB_pSilCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_LB_pSilCU_candb(&_m->mon1, Diag_From_LB_pSilCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_LB_pSilCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_LB_pSilCU_candb(Diag_From_LB_pSilCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_LB_pSilCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_LB_pSilCU >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_LB_pSilCU >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_LB_pSilCU >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_LB_pSilCU >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_LB_pSilCU >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_LB_pSilCU >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_LB_pSilCU >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_LB_pSilCU & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_LB_pSilCU_CANID; + cframe->DLC = (uint8_t) Diag_From_LB_pSilCU_DLC; + cframe->IDE = (uint8_t) Diag_From_LB_pSilCU_IDE; + return Diag_From_LB_pSilCU_CANID; +} + +#else + +uint32_t Pack_Diag_From_LB_pSilCU_candb(Diag_From_LB_pSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_LB_pSilCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_LB_pSilCU >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_LB_pSilCU >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_LB_pSilCU >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_LB_pSilCU >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_LB_pSilCU >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_LB_pSilCU >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_LB_pSilCU >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_LB_pSilCU & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_LB_pSilCU_DLC; + *_ide = (uint8_t) Diag_From_LB_pSilCU_IDE; + return Diag_From_LB_pSilCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_PLSilCU_candb(Diag_From_PLSilCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_PLSilCU = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_PLSilCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_PLSilCU_candb(&_m->mon1, Diag_From_PLSilCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_PLSilCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_PLSilCU_candb(Diag_From_PLSilCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_PLSilCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_PLSilCU >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_PLSilCU >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_PLSilCU >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_PLSilCU >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_PLSilCU >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_PLSilCU >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_PLSilCU >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_PLSilCU & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_PLSilCU_CANID; + cframe->DLC = (uint8_t) Diag_From_PLSilCU_DLC; + cframe->IDE = (uint8_t) Diag_From_PLSilCU_IDE; + return Diag_From_PLSilCU_CANID; +} + +#else + +uint32_t Pack_Diag_From_PLSilCU_candb(Diag_From_PLSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_PLSilCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_PLSilCU >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_PLSilCU >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_PLSilCU >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_PLSilCU >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_PLSilCU >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_PLSilCU >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_PLSilCU >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_PLSilCU & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_PLSilCU_DLC; + *_ide = (uint8_t) Diag_From_PLSilCU_IDE; + return Diag_From_PLSilCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_PRSilCU_candb(Diag_From_PRSilCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_PRSilCU = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_PRSilCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_PRSilCU_candb(&_m->mon1, Diag_From_PRSilCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_PRSilCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_PRSilCU_candb(Diag_From_PRSilCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_PRSilCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_PRSilCU >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_PRSilCU >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_PRSilCU >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_PRSilCU >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_PRSilCU >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_PRSilCU >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_PRSilCU >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_PRSilCU & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_PRSilCU_CANID; + cframe->DLC = (uint8_t) Diag_From_PRSilCU_DLC; + cframe->IDE = (uint8_t) Diag_From_PRSilCU_IDE; + return Diag_From_PRSilCU_CANID; +} + +#else + +uint32_t Pack_Diag_From_PRSilCU_candb(Diag_From_PRSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_PRSilCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_PRSilCU >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_PRSilCU >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_PRSilCU >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_PRSilCU >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_PRSilCU >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_PRSilCU >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_PRSilCU >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_PRSilCU & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_PRSilCU_DLC; + *_ide = (uint8_t) Diag_From_PRSilCU_IDE; + return Diag_From_PRSilCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_RB_pSilCU_candb(Diag_From_RB_pSilCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_RB_pSilCU = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_RB_pSilCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_RB_pSilCU_candb(&_m->mon1, Diag_From_RB_pSilCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_RB_pSilCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_RB_pSilCU_candb(Diag_From_RB_pSilCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_RB_pSilCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_RB_pSilCU >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_RB_pSilCU >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_RB_pSilCU >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_RB_pSilCU >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_RB_pSilCU >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_RB_pSilCU >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_RB_pSilCU >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_RB_pSilCU & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_RB_pSilCU_CANID; + cframe->DLC = (uint8_t) Diag_From_RB_pSilCU_DLC; + cframe->IDE = (uint8_t) Diag_From_RB_pSilCU_IDE; + return Diag_From_RB_pSilCU_CANID; +} + +#else + +uint32_t Pack_Diag_From_RB_pSilCU_candb(Diag_From_RB_pSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_RB_pSilCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_RB_pSilCU >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_RB_pSilCU >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_RB_pSilCU >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_RB_pSilCU >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_RB_pSilCU >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_RB_pSilCU >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_RB_pSilCU >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_RB_pSilCU & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_RB_pSilCU_DLC; + *_ide = (uint8_t) Diag_From_RB_pSilCU_IDE; + return Diag_From_RB_pSilCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_VAU_candb(Diag_To_VAU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_VAU_Sig = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_VAU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_VAU_candb(&_m->mon1, Diag_To_VAU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_VAU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_VAU_candb(Diag_To_VAU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_VAU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_VAU_Sig >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_VAU_Sig >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_VAU_Sig >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_VAU_Sig >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_VAU_Sig >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_VAU_Sig >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_VAU_Sig >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_VAU_Sig & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_VAU_CANID; + cframe->DLC = (uint8_t) Diag_To_VAU_DLC; + cframe->IDE = (uint8_t) Diag_To_VAU_IDE; + return Diag_To_VAU_CANID; +} + +#else + +uint32_t Pack_Diag_To_VAU_candb(Diag_To_VAU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_VAU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_VAU_Sig >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_VAU_Sig >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_VAU_Sig >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_VAU_Sig >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_VAU_Sig >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_VAU_Sig >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_VAU_Sig >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_VAU_Sig & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_VAU_DLC; + *_ide = (uint8_t) Diag_To_VAU_IDE; + return Diag_To_VAU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_BCM_candb(Diag_To_BCM_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_BCM_Sig = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_BCM_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_BCM_candb(&_m->mon1, Diag_To_BCM_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_BCM_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_BCM_candb(Diag_To_BCM_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_BCM_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_BCM_Sig >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_BCM_Sig >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_BCM_Sig >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_BCM_Sig >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_BCM_Sig >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_BCM_Sig >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_BCM_Sig >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_BCM_Sig & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_BCM_CANID; + cframe->DLC = (uint8_t) Diag_To_BCM_DLC; + cframe->IDE = (uint8_t) Diag_To_BCM_IDE; + return Diag_To_BCM_CANID; +} + +#else + +uint32_t Pack_Diag_To_BCM_candb(Diag_To_BCM_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_BCM_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_BCM_Sig >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_BCM_Sig >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_BCM_Sig >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_BCM_Sig >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_BCM_Sig >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_BCM_Sig >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_BCM_Sig >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_BCM_Sig & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_BCM_DLC; + *_ide = (uint8_t) Diag_To_BCM_IDE; + return Diag_To_BCM_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_DMFL_candb(Diag_To_DMFL_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_DMFL_Sig = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_DMFL_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_DMFL_candb(&_m->mon1, Diag_To_DMFL_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_DMFL_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_DMFL_candb(Diag_To_DMFL_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_DMFL_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_DMFL_Sig >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_DMFL_Sig >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_DMFL_Sig >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_DMFL_Sig >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_DMFL_Sig >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_DMFL_Sig >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_DMFL_Sig >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_DMFL_Sig & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_DMFL_CANID; + cframe->DLC = (uint8_t) Diag_To_DMFL_DLC; + cframe->IDE = (uint8_t) Diag_To_DMFL_IDE; + return Diag_To_DMFL_CANID; +} + +#else + +uint32_t Pack_Diag_To_DMFL_candb(Diag_To_DMFL_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_DMFL_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_DMFL_Sig >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_DMFL_Sig >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_DMFL_Sig >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_DMFL_Sig >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_DMFL_Sig >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_DMFL_Sig >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_DMFL_Sig >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_DMFL_Sig & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_DMFL_DLC; + *_ide = (uint8_t) Diag_To_DMFL_IDE; + return Diag_To_DMFL_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_DMFR_candb(Diag_To_DMFR_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_DMFR_Sig = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_DMFR_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_DMFR_candb(&_m->mon1, Diag_To_DMFR_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_DMFR_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_DMFR_candb(Diag_To_DMFR_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_DMFR_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_DMFR_Sig >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_DMFR_Sig >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_DMFR_Sig >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_DMFR_Sig >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_DMFR_Sig >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_DMFR_Sig >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_DMFR_Sig >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_DMFR_Sig & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_DMFR_CANID; + cframe->DLC = (uint8_t) Diag_To_DMFR_DLC; + cframe->IDE = (uint8_t) Diag_To_DMFR_IDE; + return Diag_To_DMFR_CANID; +} + +#else + +uint32_t Pack_Diag_To_DMFR_candb(Diag_To_DMFR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_DMFR_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_DMFR_Sig >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_DMFR_Sig >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_DMFR_Sig >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_DMFR_Sig >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_DMFR_Sig >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_DMFR_Sig >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_DMFR_Sig >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_DMFR_Sig & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_DMFR_DLC; + *_ide = (uint8_t) Diag_To_DMFR_IDE; + return Diag_To_DMFR_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_DMRL_candb(Diag_To_DMRL_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_DMRL_Sig = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_DMRL_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_DMRL_candb(&_m->mon1, Diag_To_DMRL_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_DMRL_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_DMRL_candb(Diag_To_DMRL_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_DMRL_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_DMRL_Sig >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_DMRL_Sig >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_DMRL_Sig >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_DMRL_Sig >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_DMRL_Sig >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_DMRL_Sig >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_DMRL_Sig >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_DMRL_Sig & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_DMRL_CANID; + cframe->DLC = (uint8_t) Diag_To_DMRL_DLC; + cframe->IDE = (uint8_t) Diag_To_DMRL_IDE; + return Diag_To_DMRL_CANID; +} + +#else + +uint32_t Pack_Diag_To_DMRL_candb(Diag_To_DMRL_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_DMRL_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_DMRL_Sig >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_DMRL_Sig >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_DMRL_Sig >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_DMRL_Sig >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_DMRL_Sig >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_DMRL_Sig >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_DMRL_Sig >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_DMRL_Sig & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_DMRL_DLC; + *_ide = (uint8_t) Diag_To_DMRL_IDE; + return Diag_To_DMRL_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_DMRR_candb(Diag_To_DMRR_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_DMRR_Sig = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_DMRR_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_DMRR_candb(&_m->mon1, Diag_To_DMRR_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_DMRR_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_DMRR_candb(Diag_To_DMRR_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_DMRR_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_DMRR_Sig >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_DMRR_Sig >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_DMRR_Sig >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_DMRR_Sig >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_DMRR_Sig >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_DMRR_Sig >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_DMRR_Sig >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_DMRR_Sig & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_DMRR_CANID; + cframe->DLC = (uint8_t) Diag_To_DMRR_DLC; + cframe->IDE = (uint8_t) Diag_To_DMRR_IDE; + return Diag_To_DMRR_CANID; +} + +#else + +uint32_t Pack_Diag_To_DMRR_candb(Diag_To_DMRR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_DMRR_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_DMRR_Sig >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_DMRR_Sig >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_DMRR_Sig >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_DMRR_Sig >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_DMRR_Sig >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_DMRR_Sig >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_DMRR_Sig >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_DMRR_Sig & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_DMRR_DLC; + *_ide = (uint8_t) Diag_To_DMRR_IDE; + return Diag_To_DMRR_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_SMRR_candb(Diag_To_SMRR_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_SMRR_Sig = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_SMRR_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_SMRR_candb(&_m->mon1, Diag_To_SMRR_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_SMRR_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_SMRR_candb(Diag_To_SMRR_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_SMRR_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_SMRR_Sig >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_SMRR_Sig >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_SMRR_Sig >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_SMRR_Sig >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_SMRR_Sig >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_SMRR_Sig >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_SMRR_Sig >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_SMRR_Sig & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_SMRR_CANID; + cframe->DLC = (uint8_t) Diag_To_SMRR_DLC; + cframe->IDE = (uint8_t) Diag_To_SMRR_IDE; + return Diag_To_SMRR_CANID; +} + +#else + +uint32_t Pack_Diag_To_SMRR_candb(Diag_To_SMRR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_SMRR_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_SMRR_Sig >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_SMRR_Sig >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_SMRR_Sig >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_SMRR_Sig >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_SMRR_Sig >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_SMRR_Sig >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_SMRR_Sig >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_SMRR_Sig & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_SMRR_DLC; + *_ide = (uint8_t) Diag_To_SMRR_IDE; + return Diag_To_SMRR_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_TM_candb(Diag_To_TM_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_TMDTM_Sig = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_TM_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_TM_candb(&_m->mon1, Diag_To_TM_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_TM_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_TM_candb(Diag_To_TM_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_TM_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_TMDTM_Sig >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_TMDTM_Sig >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_TMDTM_Sig >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_TMDTM_Sig >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_TMDTM_Sig >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_TMDTM_Sig >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_TMDTM_Sig >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_TMDTM_Sig & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_TM_CANID; + cframe->DLC = (uint8_t) Diag_To_TM_DLC; + cframe->IDE = (uint8_t) Diag_To_TM_IDE; + return Diag_To_TM_CANID; +} + +#else + +uint32_t Pack_Diag_To_TM_candb(Diag_To_TM_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_TM_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_TMDTM_Sig >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_TMDTM_Sig >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_TMDTM_Sig >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_TMDTM_Sig >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_TMDTM_Sig >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_TMDTM_Sig >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_TMDTM_Sig >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_TMDTM_Sig & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_TM_DLC; + *_ide = (uint8_t) Diag_To_TM_IDE; + return Diag_To_TM_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_CCU_candb(Diag_To_CCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_CCU_Sig = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_CCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_CCU_candb(&_m->mon1, Diag_To_CCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_CCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_CCU_candb(Diag_To_CCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_CCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_CCU_Sig >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_CCU_Sig >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_CCU_Sig >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_CCU_Sig >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_CCU_Sig >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_CCU_Sig >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_CCU_Sig >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_CCU_Sig & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_CCU_CANID; + cframe->DLC = (uint8_t) Diag_To_CCU_DLC; + cframe->IDE = (uint8_t) Diag_To_CCU_IDE; + return Diag_To_CCU_CANID; +} + +#else + +uint32_t Pack_Diag_To_CCU_candb(Diag_To_CCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_CCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_CCU_Sig >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_CCU_Sig >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_CCU_Sig >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_CCU_Sig >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_CCU_Sig >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_CCU_Sig >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_CCU_Sig >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_CCU_Sig & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_CCU_DLC; + *_ide = (uint8_t) Diag_To_CCU_IDE; + return Diag_To_CCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_SMFL_candb(Diag_To_SMFL_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_SMFL_Sig = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_SMFL_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_SMFL_candb(&_m->mon1, Diag_To_SMFL_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_SMFL_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_SMFL_candb(Diag_To_SMFL_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_SMFL_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_SMFL_Sig >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_SMFL_Sig >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_SMFL_Sig >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_SMFL_Sig >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_SMFL_Sig >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_SMFL_Sig >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_SMFL_Sig >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_SMFL_Sig & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_SMFL_CANID; + cframe->DLC = (uint8_t) Diag_To_SMFL_DLC; + cframe->IDE = (uint8_t) Diag_To_SMFL_IDE; + return Diag_To_SMFL_CANID; +} + +#else + +uint32_t Pack_Diag_To_SMFL_candb(Diag_To_SMFL_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_SMFL_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_SMFL_Sig >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_SMFL_Sig >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_SMFL_Sig >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_SMFL_Sig >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_SMFL_Sig >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_SMFL_Sig >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_SMFL_Sig >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_SMFL_Sig & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_SMFL_DLC; + *_ide = (uint8_t) Diag_To_SMFL_IDE; + return Diag_To_SMFL_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_SMFR_candb(Diag_To_SMFR_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_SMFR_Sig = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_SMFR_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_SMFR_candb(&_m->mon1, Diag_To_SMFR_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_SMFR_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_SMFR_candb(Diag_To_SMFR_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_SMFR_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_SMFR_Sig >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_SMFR_Sig >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_SMFR_Sig >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_SMFR_Sig >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_SMFR_Sig >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_SMFR_Sig >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_SMFR_Sig >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_SMFR_Sig & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_SMFR_CANID; + cframe->DLC = (uint8_t) Diag_To_SMFR_DLC; + cframe->IDE = (uint8_t) Diag_To_SMFR_IDE; + return Diag_To_SMFR_CANID; +} + +#else + +uint32_t Pack_Diag_To_SMFR_candb(Diag_To_SMFR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_SMFR_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_SMFR_Sig >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_SMFR_Sig >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_SMFR_Sig >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_SMFR_Sig >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_SMFR_Sig >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_SMFR_Sig >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_SMFR_Sig >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_SMFR_Sig & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_SMFR_DLC; + *_ide = (uint8_t) Diag_To_SMFR_IDE; + return Diag_To_SMFR_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_SMRL_candb(Diag_To_SMRL_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_SMRL_Sig = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_SMRL_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_SMRL_candb(&_m->mon1, Diag_To_SMRL_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_SMRL_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_SMRL_candb(Diag_To_SMRL_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_SMRL_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_SMRL_Sig >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_SMRL_Sig >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_SMRL_Sig >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_SMRL_Sig >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_SMRL_Sig >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_SMRL_Sig >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_SMRL_Sig >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_SMRL_Sig & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_SMRL_CANID; + cframe->DLC = (uint8_t) Diag_To_SMRL_DLC; + cframe->IDE = (uint8_t) Diag_To_SMRL_IDE; + return Diag_To_SMRL_CANID; +} + +#else + +uint32_t Pack_Diag_To_SMRL_candb(Diag_To_SMRL_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_SMRL_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_SMRL_Sig >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_SMRL_Sig >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_SMRL_Sig >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_SMRL_Sig >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_SMRL_Sig >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_SMRL_Sig >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_SMRL_Sig >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_SMRL_Sig & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_SMRL_DLC; + *_ide = (uint8_t) Diag_To_SMRL_IDE; + return Diag_To_SMRL_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_VAU_candb(Diag_From_VAU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_VAU_Sig = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_VAU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_VAU_candb(&_m->mon1, Diag_From_VAU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_VAU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_VAU_candb(Diag_From_VAU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_VAU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_VAU_Sig >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_VAU_Sig >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_VAU_Sig >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_VAU_Sig >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_VAU_Sig >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_VAU_Sig >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_VAU_Sig >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_VAU_Sig & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_VAU_CANID; + cframe->DLC = (uint8_t) Diag_From_VAU_DLC; + cframe->IDE = (uint8_t) Diag_From_VAU_IDE; + return Diag_From_VAU_CANID; +} + +#else + +uint32_t Pack_Diag_From_VAU_candb(Diag_From_VAU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_VAU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_VAU_Sig >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_VAU_Sig >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_VAU_Sig >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_VAU_Sig >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_VAU_Sig >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_VAU_Sig >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_VAU_Sig >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_VAU_Sig & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_VAU_DLC; + *_ide = (uint8_t) Diag_From_VAU_IDE; + return Diag_From_VAU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_BCM_candb(Diag_From_BCM_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_BCM_Sig = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_BCM_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_BCM_candb(&_m->mon1, Diag_From_BCM_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_BCM_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_BCM_candb(Diag_From_BCM_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_BCM_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_BCM_Sig >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_BCM_Sig >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_BCM_Sig >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_BCM_Sig >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_BCM_Sig >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_BCM_Sig >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_BCM_Sig >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_BCM_Sig & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_BCM_CANID; + cframe->DLC = (uint8_t) Diag_From_BCM_DLC; + cframe->IDE = (uint8_t) Diag_From_BCM_IDE; + return Diag_From_BCM_CANID; +} + +#else + +uint32_t Pack_Diag_From_BCM_candb(Diag_From_BCM_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_BCM_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_BCM_Sig >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_BCM_Sig >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_BCM_Sig >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_BCM_Sig >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_BCM_Sig >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_BCM_Sig >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_BCM_Sig >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_BCM_Sig & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_BCM_DLC; + *_ide = (uint8_t) Diag_From_BCM_IDE; + return Diag_From_BCM_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_DMFL_candb(Diag_From_DMFL_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_DMFL_Sig = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_DMFL_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_DMFL_candb(&_m->mon1, Diag_From_DMFL_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_DMFL_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_DMFL_candb(Diag_From_DMFL_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_DMFL_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_DMFL_Sig >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_DMFL_Sig >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_DMFL_Sig >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_DMFL_Sig >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_DMFL_Sig >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_DMFL_Sig >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_DMFL_Sig >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_DMFL_Sig & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_DMFL_CANID; + cframe->DLC = (uint8_t) Diag_From_DMFL_DLC; + cframe->IDE = (uint8_t) Diag_From_DMFL_IDE; + return Diag_From_DMFL_CANID; +} + +#else + +uint32_t Pack_Diag_From_DMFL_candb(Diag_From_DMFL_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_DMFL_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_DMFL_Sig >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_DMFL_Sig >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_DMFL_Sig >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_DMFL_Sig >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_DMFL_Sig >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_DMFL_Sig >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_DMFL_Sig >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_DMFL_Sig & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_DMFL_DLC; + *_ide = (uint8_t) Diag_From_DMFL_IDE; + return Diag_From_DMFL_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_DMFR_candb(Diag_From_DMFR_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_DMFR_Sig = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_DMFR_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_DMFR_candb(&_m->mon1, Diag_From_DMFR_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_DMFR_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_DMFR_candb(Diag_From_DMFR_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_DMFR_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_DMFR_Sig >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_DMFR_Sig >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_DMFR_Sig >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_DMFR_Sig >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_DMFR_Sig >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_DMFR_Sig >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_DMFR_Sig >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_DMFR_Sig & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_DMFR_CANID; + cframe->DLC = (uint8_t) Diag_From_DMFR_DLC; + cframe->IDE = (uint8_t) Diag_From_DMFR_IDE; + return Diag_From_DMFR_CANID; +} + +#else + +uint32_t Pack_Diag_From_DMFR_candb(Diag_From_DMFR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_DMFR_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_DMFR_Sig >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_DMFR_Sig >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_DMFR_Sig >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_DMFR_Sig >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_DMFR_Sig >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_DMFR_Sig >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_DMFR_Sig >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_DMFR_Sig & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_DMFR_DLC; + *_ide = (uint8_t) Diag_From_DMFR_IDE; + return Diag_From_DMFR_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_DMRL_candb(Diag_From_DMRL_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_DMRL_Sig = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_DMRL_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_DMRL_candb(&_m->mon1, Diag_From_DMRL_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_DMRL_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_DMRL_candb(Diag_From_DMRL_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_DMRL_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_DMRL_Sig >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_DMRL_Sig >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_DMRL_Sig >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_DMRL_Sig >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_DMRL_Sig >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_DMRL_Sig >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_DMRL_Sig >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_DMRL_Sig & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_DMRL_CANID; + cframe->DLC = (uint8_t) Diag_From_DMRL_DLC; + cframe->IDE = (uint8_t) Diag_From_DMRL_IDE; + return Diag_From_DMRL_CANID; +} + +#else + +uint32_t Pack_Diag_From_DMRL_candb(Diag_From_DMRL_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_DMRL_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_DMRL_Sig >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_DMRL_Sig >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_DMRL_Sig >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_DMRL_Sig >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_DMRL_Sig >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_DMRL_Sig >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_DMRL_Sig >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_DMRL_Sig & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_DMRL_DLC; + *_ide = (uint8_t) Diag_From_DMRL_IDE; + return Diag_From_DMRL_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_DMRR_candb(Diag_From_DMRR_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_DMRR_Sig = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_DMRR_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_DMRR_candb(&_m->mon1, Diag_From_DMRR_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_DMRR_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_DMRR_candb(Diag_From_DMRR_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_DMRR_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_DMRR_Sig >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_DMRR_Sig >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_DMRR_Sig >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_DMRR_Sig >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_DMRR_Sig >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_DMRR_Sig >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_DMRR_Sig >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_DMRR_Sig & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_DMRR_CANID; + cframe->DLC = (uint8_t) Diag_From_DMRR_DLC; + cframe->IDE = (uint8_t) Diag_From_DMRR_IDE; + return Diag_From_DMRR_CANID; +} + +#else + +uint32_t Pack_Diag_From_DMRR_candb(Diag_From_DMRR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_DMRR_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_DMRR_Sig >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_DMRR_Sig >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_DMRR_Sig >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_DMRR_Sig >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_DMRR_Sig >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_DMRR_Sig >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_DMRR_Sig >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_DMRR_Sig & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_DMRR_DLC; + *_ide = (uint8_t) Diag_From_DMRR_IDE; + return Diag_From_DMRR_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_SMRR_candb(Diag_From_SMRR_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_SMRR_Sig = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_SMRR_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_SMRR_candb(&_m->mon1, Diag_From_SMRR_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_SMRR_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_SMRR_candb(Diag_From_SMRR_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_SMRR_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_SMRR_Sig >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_SMRR_Sig >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_SMRR_Sig >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_SMRR_Sig >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_SMRR_Sig >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_SMRR_Sig >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_SMRR_Sig >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_SMRR_Sig & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_SMRR_CANID; + cframe->DLC = (uint8_t) Diag_From_SMRR_DLC; + cframe->IDE = (uint8_t) Diag_From_SMRR_IDE; + return Diag_From_SMRR_CANID; +} + +#else + +uint32_t Pack_Diag_From_SMRR_candb(Diag_From_SMRR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_SMRR_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_SMRR_Sig >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_SMRR_Sig >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_SMRR_Sig >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_SMRR_Sig >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_SMRR_Sig >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_SMRR_Sig >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_SMRR_Sig >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_SMRR_Sig & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_SMRR_DLC; + *_ide = (uint8_t) Diag_From_SMRR_IDE; + return Diag_From_SMRR_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_TM_candb(Diag_From_TM_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_TM = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_TM_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_TM_candb(&_m->mon1, Diag_From_TM_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_TM_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_TM_candb(Diag_From_TM_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_TM_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_TM >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_TM >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_TM >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_TM >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_TM >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_TM >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_TM >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_TM & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_TM_CANID; + cframe->DLC = (uint8_t) Diag_From_TM_DLC; + cframe->IDE = (uint8_t) Diag_From_TM_IDE; + return Diag_From_TM_CANID; +} + +#else + +uint32_t Pack_Diag_From_TM_candb(Diag_From_TM_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_TM_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_TM >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_TM >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_TM >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_TM >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_TM >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_TM >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_TM >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_TM & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_TM_DLC; + *_ide = (uint8_t) Diag_From_TM_IDE; + return Diag_From_TM_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_CCU_candb(Diag_From_CCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_CCU_Sig = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_CCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_CCU_candb(&_m->mon1, Diag_From_CCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_CCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_CCU_candb(Diag_From_CCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_CCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_CCU_Sig >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_CCU_Sig >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_CCU_Sig >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_CCU_Sig >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_CCU_Sig >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_CCU_Sig >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_CCU_Sig >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_CCU_Sig & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_CCU_CANID; + cframe->DLC = (uint8_t) Diag_From_CCU_DLC; + cframe->IDE = (uint8_t) Diag_From_CCU_IDE; + return Diag_From_CCU_CANID; +} + +#else + +uint32_t Pack_Diag_From_CCU_candb(Diag_From_CCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_CCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_CCU_Sig >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_CCU_Sig >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_CCU_Sig >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_CCU_Sig >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_CCU_Sig >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_CCU_Sig >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_CCU_Sig >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_CCU_Sig & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_CCU_DLC; + *_ide = (uint8_t) Diag_From_CCU_IDE; + return Diag_From_CCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_SMFL_candb(Diag_From_SMFL_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_SMFL_Sig = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_SMFL_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_SMFL_candb(&_m->mon1, Diag_From_SMFL_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_SMFL_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_SMFL_candb(Diag_From_SMFL_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_SMFL_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_SMFL_Sig >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_SMFL_Sig >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_SMFL_Sig >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_SMFL_Sig >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_SMFL_Sig >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_SMFL_Sig >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_SMFL_Sig >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_SMFL_Sig & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_SMFL_CANID; + cframe->DLC = (uint8_t) Diag_From_SMFL_DLC; + cframe->IDE = (uint8_t) Diag_From_SMFL_IDE; + return Diag_From_SMFL_CANID; +} + +#else + +uint32_t Pack_Diag_From_SMFL_candb(Diag_From_SMFL_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_SMFL_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_SMFL_Sig >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_SMFL_Sig >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_SMFL_Sig >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_SMFL_Sig >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_SMFL_Sig >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_SMFL_Sig >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_SMFL_Sig >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_SMFL_Sig & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_SMFL_DLC; + *_ide = (uint8_t) Diag_From_SMFL_IDE; + return Diag_From_SMFL_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_SMFR_candb(Diag_From_SMFR_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_SMFR_Sig = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_SMFR_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_SMFR_candb(&_m->mon1, Diag_From_SMFR_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_SMFR_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_SMFR_candb(Diag_From_SMFR_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_SMFR_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_SMFR_Sig >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_SMFR_Sig >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_SMFR_Sig >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_SMFR_Sig >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_SMFR_Sig >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_SMFR_Sig >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_SMFR_Sig >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_SMFR_Sig & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_SMFR_CANID; + cframe->DLC = (uint8_t) Diag_From_SMFR_DLC; + cframe->IDE = (uint8_t) Diag_From_SMFR_IDE; + return Diag_From_SMFR_CANID; +} + +#else + +uint32_t Pack_Diag_From_SMFR_candb(Diag_From_SMFR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_SMFR_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_SMFR_Sig >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_SMFR_Sig >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_SMFR_Sig >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_SMFR_Sig >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_SMFR_Sig >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_SMFR_Sig >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_SMFR_Sig >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_SMFR_Sig & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_SMFR_DLC; + *_ide = (uint8_t) Diag_From_SMFR_IDE; + return Diag_From_SMFR_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_SMRL_candb(Diag_From_SMRL_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_SMRL_Sig = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_SMRL_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_SMRL_candb(&_m->mon1, Diag_From_SMRL_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_SMRL_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_SMRL_candb(Diag_From_SMRL_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_SMRL_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_SMRL_Sig >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_SMRL_Sig >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_SMRL_Sig >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_SMRL_Sig >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_SMRL_Sig >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_SMRL_Sig >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_SMRL_Sig >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_SMRL_Sig & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_SMRL_CANID; + cframe->DLC = (uint8_t) Diag_From_SMRL_DLC; + cframe->IDE = (uint8_t) Diag_From_SMRL_IDE; + return Diag_From_SMRL_CANID; +} + +#else + +uint32_t Pack_Diag_From_SMRL_candb(Diag_From_SMRL_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_SMRL_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_SMRL_Sig >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_SMRL_Sig >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_SMRL_Sig >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_SMRL_Sig >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_SMRL_Sig >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_SMRL_Sig >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_SMRL_Sig >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_SMRL_Sig & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_SMRL_DLC; + *_ide = (uint8_t) Diag_From_SMRL_IDE; + return Diag_From_SMRL_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_RCLSilCU_candb(Diag_To_RCLSilCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_RCLSilCU = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_RCLSilCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_RCLSilCU_candb(&_m->mon1, Diag_To_RCLSilCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_RCLSilCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_RCLSilCU_candb(Diag_To_RCLSilCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_RCLSilCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_RCLSilCU >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_RCLSilCU >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_RCLSilCU >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_RCLSilCU >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_RCLSilCU >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_RCLSilCU >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_RCLSilCU >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_RCLSilCU & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_RCLSilCU_CANID; + cframe->DLC = (uint8_t) Diag_To_RCLSilCU_DLC; + cframe->IDE = (uint8_t) Diag_To_RCLSilCU_IDE; + return Diag_To_RCLSilCU_CANID; +} + +#else + +uint32_t Pack_Diag_To_RCLSilCU_candb(Diag_To_RCLSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_RCLSilCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_RCLSilCU >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_RCLSilCU >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_RCLSilCU >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_RCLSilCU >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_RCLSilCU >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_RCLSilCU >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_RCLSilCU >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_RCLSilCU & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_RCLSilCU_DLC; + *_ide = (uint8_t) Diag_To_RCLSilCU_IDE; + return Diag_To_RCLSilCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_RCRSilCU_candb(Diag_To_RCRSilCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_RCRSilCU = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_RCRSilCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_RCRSilCU_candb(&_m->mon1, Diag_To_RCRSilCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_RCRSilCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_RCRSilCU_candb(Diag_To_RCRSilCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_RCRSilCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_RCRSilCU >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_RCRSilCU >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_RCRSilCU >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_RCRSilCU >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_RCRSilCU >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_RCRSilCU >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_RCRSilCU >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_RCRSilCU & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_RCRSilCU_CANID; + cframe->DLC = (uint8_t) Diag_To_RCRSilCU_DLC; + cframe->IDE = (uint8_t) Diag_To_RCRSilCU_IDE; + return Diag_To_RCRSilCU_CANID; +} + +#else + +uint32_t Pack_Diag_To_RCRSilCU_candb(Diag_To_RCRSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_RCRSilCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_RCRSilCU >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_RCRSilCU >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_RCRSilCU >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_RCRSilCU >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_RCRSilCU >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_RCRSilCU >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_RCRSilCU >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_RCRSilCU & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_RCRSilCU_DLC; + *_ide = (uint8_t) Diag_To_RCRSilCU_IDE; + return Diag_To_RCRSilCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_RDLSilCU_candb(Diag_To_RDLSilCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_RDLSilCU = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_RDLSilCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_RDLSilCU_candb(&_m->mon1, Diag_To_RDLSilCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_RDLSilCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_RDLSilCU_candb(Diag_To_RDLSilCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_RDLSilCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_RDLSilCU >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_RDLSilCU >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_RDLSilCU >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_RDLSilCU >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_RDLSilCU >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_RDLSilCU >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_RDLSilCU >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_RDLSilCU & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_RDLSilCU_CANID; + cframe->DLC = (uint8_t) Diag_To_RDLSilCU_DLC; + cframe->IDE = (uint8_t) Diag_To_RDLSilCU_IDE; + return Diag_To_RDLSilCU_CANID; +} + +#else + +uint32_t Pack_Diag_To_RDLSilCU_candb(Diag_To_RDLSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_RDLSilCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_RDLSilCU >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_RDLSilCU >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_RDLSilCU >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_RDLSilCU >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_RDLSilCU >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_RDLSilCU >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_RDLSilCU >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_RDLSilCU & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_RDLSilCU_DLC; + *_ide = (uint8_t) Diag_To_RDLSilCU_IDE; + return Diag_To_RDLSilCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_RDRSilCU_candb(Diag_To_RDRSilCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_RDRSilCU = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_RDRSilCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_RDRSilCU_candb(&_m->mon1, Diag_To_RDRSilCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_RDRSilCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_RDRSilCU_candb(Diag_To_RDRSilCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_RDRSilCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_RDRSilCU >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_RDRSilCU >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_RDRSilCU >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_RDRSilCU >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_RDRSilCU >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_RDRSilCU >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_RDRSilCU >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_RDRSilCU & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_RDRSilCU_CANID; + cframe->DLC = (uint8_t) Diag_To_RDRSilCU_DLC; + cframe->IDE = (uint8_t) Diag_To_RDRSilCU_IDE; + return Diag_To_RDRSilCU_CANID; +} + +#else + +uint32_t Pack_Diag_To_RDRSilCU_candb(Diag_To_RDRSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_RDRSilCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_RDRSilCU >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_RDRSilCU >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_RDRSilCU >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_RDRSilCU >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_RDRSilCU >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_RDRSilCU >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_RDRSilCU >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_RDRSilCU & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_RDRSilCU_DLC; + *_ide = (uint8_t) Diag_To_RDRSilCU_IDE; + return Diag_To_RDRSilCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_OCUFL_candb(Diag_From_OCUFL_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_OCUFL = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_OCUFL_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_OCUFL_candb(&_m->mon1, Diag_From_OCUFL_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_OCUFL_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_OCUFL_candb(Diag_From_OCUFL_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_OCUFL_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_OCUFL >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_OCUFL >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_OCUFL >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_OCUFL >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_OCUFL >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_OCUFL >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_OCUFL >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_OCUFL & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_OCUFL_CANID; + cframe->DLC = (uint8_t) Diag_From_OCUFL_DLC; + cframe->IDE = (uint8_t) Diag_From_OCUFL_IDE; + return Diag_From_OCUFL_CANID; +} + +#else + +uint32_t Pack_Diag_From_OCUFL_candb(Diag_From_OCUFL_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_OCUFL_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_OCUFL >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_OCUFL >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_OCUFL >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_OCUFL >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_OCUFL >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_OCUFL >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_OCUFL >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_OCUFL & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_OCUFL_DLC; + *_ide = (uint8_t) Diag_From_OCUFL_IDE; + return Diag_From_OCUFL_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_RLDSilCU_candb(Diag_To_RLDSilCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_RLDSilCU = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_RLDSilCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_RLDSilCU_candb(&_m->mon1, Diag_To_RLDSilCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_RLDSilCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_RLDSilCU_candb(Diag_To_RLDSilCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_RLDSilCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_RLDSilCU >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_RLDSilCU >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_RLDSilCU >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_RLDSilCU >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_RLDSilCU >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_RLDSilCU >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_RLDSilCU >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_RLDSilCU & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_RLDSilCU_CANID; + cframe->DLC = (uint8_t) Diag_To_RLDSilCU_DLC; + cframe->IDE = (uint8_t) Diag_To_RLDSilCU_IDE; + return Diag_To_RLDSilCU_CANID; +} + +#else + +uint32_t Pack_Diag_To_RLDSilCU_candb(Diag_To_RLDSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_RLDSilCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_RLDSilCU >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_RLDSilCU >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_RLDSilCU >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_RLDSilCU >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_RLDSilCU >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_RLDSilCU >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_RLDSilCU >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_RLDSilCU & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_RLDSilCU_DLC; + *_ide = (uint8_t) Diag_To_RLDSilCU_IDE; + return Diag_To_RLDSilCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_RRDSilCU_candb(Diag_To_RRDSilCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_RRDSilCU = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_RRDSilCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_RRDSilCU_candb(&_m->mon1, Diag_To_RRDSilCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_RRDSilCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_RRDSilCU_candb(Diag_To_RRDSilCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_RRDSilCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_RRDSilCU >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_RRDSilCU >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_RRDSilCU >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_RRDSilCU >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_RRDSilCU >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_RRDSilCU >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_RRDSilCU >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_RRDSilCU & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_RRDSilCU_CANID; + cframe->DLC = (uint8_t) Diag_To_RRDSilCU_DLC; + cframe->IDE = (uint8_t) Diag_To_RRDSilCU_IDE; + return Diag_To_RRDSilCU_CANID; +} + +#else + +uint32_t Pack_Diag_To_RRDSilCU_candb(Diag_To_RRDSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_RRDSilCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_RRDSilCU >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_RRDSilCU >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_RRDSilCU >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_RRDSilCU >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_RRDSilCU >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_RRDSilCU >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_RRDSilCU >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_RRDSilCU & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_RRDSilCU_DLC; + *_ide = (uint8_t) Diag_To_RRDSilCU_IDE; + return Diag_To_RRDSilCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_PTG_candb(Diag_From_PTG_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_PTG = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_PTG_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_PTG_candb(&_m->mon1, Diag_From_PTG_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_PTG_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_PTG_candb(Diag_From_PTG_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_PTG_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_PTG >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_PTG >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_PTG >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_PTG >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_PTG >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_PTG >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_PTG >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_PTG & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_PTG_CANID; + cframe->DLC = (uint8_t) Diag_From_PTG_DLC; + cframe->IDE = (uint8_t) Diag_From_PTG_IDE; + return Diag_From_PTG_CANID; +} + +#else + +uint32_t Pack_Diag_From_PTG_candb(Diag_From_PTG_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_PTG_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_PTG >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_PTG >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_PTG >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_PTG >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_PTG >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_PTG >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_PTG >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_PTG & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_PTG_DLC; + *_ide = (uint8_t) Diag_From_PTG_IDE; + return Diag_From_PTG_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_OCUFR_candb(Diag_From_OCUFR_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_OCUFR = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_OCUFR_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_OCUFR_candb(&_m->mon1, Diag_From_OCUFR_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_OCUFR_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_OCUFR_candb(Diag_From_OCUFR_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_OCUFR_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_OCUFR >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_OCUFR >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_OCUFR >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_OCUFR >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_OCUFR >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_OCUFR >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_OCUFR >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_OCUFR & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_OCUFR_CANID; + cframe->DLC = (uint8_t) Diag_From_OCUFR_DLC; + cframe->IDE = (uint8_t) Diag_From_OCUFR_IDE; + return Diag_From_OCUFR_CANID; +} + +#else + +uint32_t Pack_Diag_From_OCUFR_candb(Diag_From_OCUFR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_OCUFR_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_OCUFR >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_OCUFR >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_OCUFR >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_OCUFR >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_OCUFR >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_OCUFR >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_OCUFR >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_OCUFR & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_OCUFR_DLC; + *_ide = (uint8_t) Diag_From_OCUFR_IDE; + return Diag_From_OCUFR_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_OCURL_candb(Diag_From_OCURL_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_OCURL = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_OCURL_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_OCURL_candb(&_m->mon1, Diag_From_OCURL_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_OCURL_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_OCURL_candb(Diag_From_OCURL_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_OCURL_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_OCURL >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_OCURL >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_OCURL >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_OCURL >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_OCURL >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_OCURL >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_OCURL >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_OCURL & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_OCURL_CANID; + cframe->DLC = (uint8_t) Diag_From_OCURL_DLC; + cframe->IDE = (uint8_t) Diag_From_OCURL_IDE; + return Diag_From_OCURL_CANID; +} + +#else + +uint32_t Pack_Diag_From_OCURL_candb(Diag_From_OCURL_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_OCURL_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_OCURL >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_OCURL >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_OCURL >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_OCURL >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_OCURL >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_OCURL >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_OCURL >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_OCURL & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_OCURL_DLC; + *_ide = (uint8_t) Diag_From_OCURL_IDE; + return Diag_From_OCURL_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_OCURR_candb(Diag_From_OCURR_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_OCURR = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_OCURR_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_OCURR_candb(&_m->mon1, Diag_From_OCURR_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_OCURR_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_OCURR_candb(Diag_From_OCURR_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_OCURR_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_OCURR >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_OCURR >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_OCURR >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_OCURR >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_OCURR >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_OCURR >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_OCURR >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_OCURR & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_OCURR_CANID; + cframe->DLC = (uint8_t) Diag_From_OCURR_DLC; + cframe->IDE = (uint8_t) Diag_From_OCURR_IDE; + return Diag_From_OCURR_CANID; +} + +#else + +uint32_t Pack_Diag_From_OCURR_candb(Diag_From_OCURR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_OCURR_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_OCURR >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_OCURR >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_OCURR >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_OCURR >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_OCURR >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_OCURR >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_OCURR >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_OCURR & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_OCURR_DLC; + *_ide = (uint8_t) Diag_From_OCURR_IDE; + return Diag_From_OCURR_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_RCLSilCU_candb(Diag_From_RCLSilCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_RCLSilCU = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_RCLSilCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_RCLSilCU_candb(&_m->mon1, Diag_From_RCLSilCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_RCLSilCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_RCLSilCU_candb(Diag_From_RCLSilCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_RCLSilCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_RCLSilCU >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_RCLSilCU >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_RCLSilCU >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_RCLSilCU >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_RCLSilCU >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_RCLSilCU >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_RCLSilCU >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_RCLSilCU & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_RCLSilCU_CANID; + cframe->DLC = (uint8_t) Diag_From_RCLSilCU_DLC; + cframe->IDE = (uint8_t) Diag_From_RCLSilCU_IDE; + return Diag_From_RCLSilCU_CANID; +} + +#else + +uint32_t Pack_Diag_From_RCLSilCU_candb(Diag_From_RCLSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_RCLSilCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_RCLSilCU >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_RCLSilCU >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_RCLSilCU >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_RCLSilCU >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_RCLSilCU >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_RCLSilCU >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_RCLSilCU >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_RCLSilCU & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_RCLSilCU_DLC; + *_ide = (uint8_t) Diag_From_RCLSilCU_IDE; + return Diag_From_RCLSilCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_RCRSilCU_candb(Diag_From_RCRSilCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_RCRSilCU = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_RCRSilCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_RCRSilCU_candb(&_m->mon1, Diag_From_RCRSilCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_RCRSilCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_RCRSilCU_candb(Diag_From_RCRSilCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_RCRSilCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_RCRSilCU >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_RCRSilCU >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_RCRSilCU >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_RCRSilCU >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_RCRSilCU >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_RCRSilCU >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_RCRSilCU >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_RCRSilCU & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_RCRSilCU_CANID; + cframe->DLC = (uint8_t) Diag_From_RCRSilCU_DLC; + cframe->IDE = (uint8_t) Diag_From_RCRSilCU_IDE; + return Diag_From_RCRSilCU_CANID; +} + +#else + +uint32_t Pack_Diag_From_RCRSilCU_candb(Diag_From_RCRSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_RCRSilCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_RCRSilCU >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_RCRSilCU >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_RCRSilCU >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_RCRSilCU >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_RCRSilCU >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_RCRSilCU >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_RCRSilCU >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_RCRSilCU & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_RCRSilCU_DLC; + *_ide = (uint8_t) Diag_From_RCRSilCU_IDE; + return Diag_From_RCRSilCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_RDLSilCU_candb(Diag_From_RDLSilCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_RDLSilCU = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_RDLSilCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_RDLSilCU_candb(&_m->mon1, Diag_From_RDLSilCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_RDLSilCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_RDLSilCU_candb(Diag_From_RDLSilCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_RDLSilCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_RDLSilCU >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_RDLSilCU >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_RDLSilCU >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_RDLSilCU >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_RDLSilCU >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_RDLSilCU >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_RDLSilCU >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_RDLSilCU & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_RDLSilCU_CANID; + cframe->DLC = (uint8_t) Diag_From_RDLSilCU_DLC; + cframe->IDE = (uint8_t) Diag_From_RDLSilCU_IDE; + return Diag_From_RDLSilCU_CANID; +} + +#else + +uint32_t Pack_Diag_From_RDLSilCU_candb(Diag_From_RDLSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_RDLSilCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_RDLSilCU >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_RDLSilCU >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_RDLSilCU >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_RDLSilCU >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_RDLSilCU >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_RDLSilCU >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_RDLSilCU >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_RDLSilCU & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_RDLSilCU_DLC; + *_ide = (uint8_t) Diag_From_RDLSilCU_IDE; + return Diag_From_RDLSilCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_RDRSilCU_candb(Diag_From_RDRSilCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_RDRSilCU = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_RDRSilCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_RDRSilCU_candb(&_m->mon1, Diag_From_RDRSilCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_RDRSilCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_RDRSilCU_candb(Diag_From_RDRSilCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_RDRSilCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_RDRSilCU >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_RDRSilCU >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_RDRSilCU >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_RDRSilCU >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_RDRSilCU >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_RDRSilCU >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_RDRSilCU >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_RDRSilCU & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_RDRSilCU_CANID; + cframe->DLC = (uint8_t) Diag_From_RDRSilCU_DLC; + cframe->IDE = (uint8_t) Diag_From_RDRSilCU_IDE; + return Diag_From_RDRSilCU_CANID; +} + +#else + +uint32_t Pack_Diag_From_RDRSilCU_candb(Diag_From_RDRSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_RDRSilCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_RDRSilCU >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_RDRSilCU >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_RDRSilCU >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_RDRSilCU >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_RDRSilCU >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_RDRSilCU >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_RDRSilCU >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_RDRSilCU & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_RDRSilCU_DLC; + *_ide = (uint8_t) Diag_From_RDRSilCU_IDE; + return Diag_From_RDRSilCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_OCUFL_candb(Diag_To_OCUFL_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_OCUFL = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_OCUFL_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_OCUFL_candb(&_m->mon1, Diag_To_OCUFL_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_OCUFL_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_OCUFL_candb(Diag_To_OCUFL_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_OCUFL_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_OCUFL >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_OCUFL >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_OCUFL >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_OCUFL >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_OCUFL >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_OCUFL >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_OCUFL >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_OCUFL & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_OCUFL_CANID; + cframe->DLC = (uint8_t) Diag_To_OCUFL_DLC; + cframe->IDE = (uint8_t) Diag_To_OCUFL_IDE; + return Diag_To_OCUFL_CANID; +} + +#else + +uint32_t Pack_Diag_To_OCUFL_candb(Diag_To_OCUFL_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_OCUFL_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_OCUFL >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_OCUFL >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_OCUFL >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_OCUFL >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_OCUFL >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_OCUFL >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_OCUFL >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_OCUFL & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_OCUFL_DLC; + *_ide = (uint8_t) Diag_To_OCUFL_IDE; + return Diag_To_OCUFL_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_RLDSilCU_candb(Diag_From_RLDSilCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_RLDSilCU = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_RLDSilCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_RLDSilCU_candb(&_m->mon1, Diag_From_RLDSilCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_RLDSilCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_RLDSilCU_candb(Diag_From_RLDSilCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_RLDSilCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_RLDSilCU >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_RLDSilCU >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_RLDSilCU >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_RLDSilCU >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_RLDSilCU >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_RLDSilCU >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_RLDSilCU >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_RLDSilCU & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_RLDSilCU_CANID; + cframe->DLC = (uint8_t) Diag_From_RLDSilCU_DLC; + cframe->IDE = (uint8_t) Diag_From_RLDSilCU_IDE; + return Diag_From_RLDSilCU_CANID; +} + +#else + +uint32_t Pack_Diag_From_RLDSilCU_candb(Diag_From_RLDSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_RLDSilCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_RLDSilCU >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_RLDSilCU >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_RLDSilCU >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_RLDSilCU >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_RLDSilCU >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_RLDSilCU >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_RLDSilCU >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_RLDSilCU & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_RLDSilCU_DLC; + *_ide = (uint8_t) Diag_From_RLDSilCU_IDE; + return Diag_From_RLDSilCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_RRDSilCU_candb(Diag_From_RRDSilCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_RRDSilCU = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_RRDSilCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_RRDSilCU_candb(&_m->mon1, Diag_From_RRDSilCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_RRDSilCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_RRDSilCU_candb(Diag_From_RRDSilCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_RRDSilCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_RRDSilCU >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_RRDSilCU >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_RRDSilCU >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_RRDSilCU >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_RRDSilCU >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_RRDSilCU >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_RRDSilCU >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_RRDSilCU & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_RRDSilCU_CANID; + cframe->DLC = (uint8_t) Diag_From_RRDSilCU_DLC; + cframe->IDE = (uint8_t) Diag_From_RRDSilCU_IDE; + return Diag_From_RRDSilCU_CANID; +} + +#else + +uint32_t Pack_Diag_From_RRDSilCU_candb(Diag_From_RRDSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_RRDSilCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_RRDSilCU >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_RRDSilCU >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_RRDSilCU >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_RRDSilCU >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_RRDSilCU >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_RRDSilCU >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_RRDSilCU >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_RRDSilCU & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_RRDSilCU_DLC; + *_ide = (uint8_t) Diag_From_RRDSilCU_IDE; + return Diag_From_RRDSilCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_PTG_candb(Diag_To_PTG_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_PTG = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_PTG_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_PTG_candb(&_m->mon1, Diag_To_PTG_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_PTG_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_PTG_candb(Diag_To_PTG_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_PTG_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_PTG >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_PTG >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_PTG >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_PTG >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_PTG >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_PTG >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_PTG >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_PTG & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_PTG_CANID; + cframe->DLC = (uint8_t) Diag_To_PTG_DLC; + cframe->IDE = (uint8_t) Diag_To_PTG_IDE; + return Diag_To_PTG_CANID; +} + +#else + +uint32_t Pack_Diag_To_PTG_candb(Diag_To_PTG_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_PTG_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_PTG >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_PTG >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_PTG >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_PTG >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_PTG >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_PTG >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_PTG >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_PTG & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_PTG_DLC; + *_ide = (uint8_t) Diag_To_PTG_IDE; + return Diag_To_PTG_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_OCUFR_candb(Diag_To_OCUFR_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_OCUFR = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_OCUFR_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_OCUFR_candb(&_m->mon1, Diag_To_OCUFR_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_OCUFR_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_OCUFR_candb(Diag_To_OCUFR_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_OCUFR_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_OCUFR >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_OCUFR >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_OCUFR >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_OCUFR >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_OCUFR >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_OCUFR >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_OCUFR >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_OCUFR & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_OCUFR_CANID; + cframe->DLC = (uint8_t) Diag_To_OCUFR_DLC; + cframe->IDE = (uint8_t) Diag_To_OCUFR_IDE; + return Diag_To_OCUFR_CANID; +} + +#else + +uint32_t Pack_Diag_To_OCUFR_candb(Diag_To_OCUFR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_OCUFR_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_OCUFR >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_OCUFR >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_OCUFR >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_OCUFR >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_OCUFR >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_OCUFR >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_OCUFR >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_OCUFR & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_OCUFR_DLC; + *_ide = (uint8_t) Diag_To_OCUFR_IDE; + return Diag_To_OCUFR_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_OCURL_candb(Diag_To_OCURL_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_OCURL = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_OCURL_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_OCURL_candb(&_m->mon1, Diag_To_OCURL_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_OCURL_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_OCURL_candb(Diag_To_OCURL_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_OCURL_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_OCURL >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_OCURL >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_OCURL >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_OCURL >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_OCURL >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_OCURL >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_OCURL >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_OCURL & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_OCURL_CANID; + cframe->DLC = (uint8_t) Diag_To_OCURL_DLC; + cframe->IDE = (uint8_t) Diag_To_OCURL_IDE; + return Diag_To_OCURL_CANID; +} + +#else + +uint32_t Pack_Diag_To_OCURL_candb(Diag_To_OCURL_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_OCURL_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_OCURL >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_OCURL >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_OCURL >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_OCURL >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_OCURL >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_OCURL >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_OCURL >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_OCURL & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_OCURL_DLC; + *_ide = (uint8_t) Diag_To_OCURL_IDE; + return Diag_To_OCURL_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_OCURR_candb(Diag_To_OCURR_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_OCURR = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_OCURR_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_OCURR_candb(&_m->mon1, Diag_To_OCURR_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_OCURR_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_OCURR_candb(Diag_To_OCURR_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_OCURR_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_OCURR >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_OCURR >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_OCURR >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_OCURR >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_OCURR >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_OCURR >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_OCURR >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_OCURR & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_OCURR_CANID; + cframe->DLC = (uint8_t) Diag_To_OCURR_DLC; + cframe->IDE = (uint8_t) Diag_To_OCURR_IDE; + return Diag_To_OCURR_CANID; +} + +#else + +uint32_t Pack_Diag_To_OCURR_candb(Diag_To_OCURR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_OCURR_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_OCURR >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_OCURR >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_OCURR >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_OCURR >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_OCURR >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_OCURR >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_OCURR >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_OCURR & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_OCURR_DLC; + *_ide = (uint8_t) Diag_To_OCURR_IDE; + return Diag_To_OCURR_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_Functional_candb(Diag_Functional_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_Functional_Sig = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_Functional_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_Functional_candb(&_m->mon1, Diag_Functional_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_Functional_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_Functional_candb(Diag_Functional_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_Functional_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_Functional_Sig >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_Functional_Sig >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_Functional_Sig >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_Functional_Sig >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_Functional_Sig >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_Functional_Sig >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_Functional_Sig >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_Functional_Sig & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_Functional_CANID; + cframe->DLC = (uint8_t) Diag_Functional_DLC; + cframe->IDE = (uint8_t) Diag_Functional_IDE; + return Diag_Functional_CANID; +} + +#else + +uint32_t Pack_Diag_Functional_candb(Diag_Functional_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_Functional_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_Functional_Sig >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_Functional_Sig >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_Functional_Sig >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_Functional_Sig >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_Functional_Sig >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_Functional_Sig >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_Functional_Sig >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_Functional_Sig & (0xFFU)) ); + + *_len = (uint8_t) Diag_Functional_DLC; + *_ide = (uint8_t) Diag_Functional_IDE; + return Diag_Functional_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_SFRSilCU_candb(Diag_To_SFRSilCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_SFRSilCU = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_SFRSilCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_SFRSilCU_candb(&_m->mon1, Diag_To_SFRSilCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_SFRSilCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_SFRSilCU_candb(Diag_To_SFRSilCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_SFRSilCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_SFRSilCU >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_SFRSilCU >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_SFRSilCU >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_SFRSilCU >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_SFRSilCU >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_SFRSilCU >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_SFRSilCU >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_SFRSilCU & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_SFRSilCU_CANID; + cframe->DLC = (uint8_t) Diag_To_SFRSilCU_DLC; + cframe->IDE = (uint8_t) Diag_To_SFRSilCU_IDE; + return Diag_To_SFRSilCU_CANID; +} + +#else + +uint32_t Pack_Diag_To_SFRSilCU_candb(Diag_To_SFRSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_SFRSilCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_SFRSilCU >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_SFRSilCU >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_SFRSilCU >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_SFRSilCU >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_SFRSilCU >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_SFRSilCU >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_SFRSilCU >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_SFRSilCU & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_SFRSilCU_DLC; + *_ide = (uint8_t) Diag_To_SFRSilCU_IDE; + return Diag_To_SFRSilCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_SFLSilCU_candb(Diag_To_SFLSilCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_SFLSilCU = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_SFLSilCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_SFLSilCU_candb(&_m->mon1, Diag_To_SFLSilCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_SFLSilCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_SFLSilCU_candb(Diag_To_SFLSilCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_SFLSilCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_SFLSilCU >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_SFLSilCU >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_SFLSilCU >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_SFLSilCU >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_SFLSilCU >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_SFLSilCU >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_SFLSilCU >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_SFLSilCU & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_SFLSilCU_CANID; + cframe->DLC = (uint8_t) Diag_To_SFLSilCU_DLC; + cframe->IDE = (uint8_t) Diag_To_SFLSilCU_IDE; + return Diag_To_SFLSilCU_CANID; +} + +#else + +uint32_t Pack_Diag_To_SFLSilCU_candb(Diag_To_SFLSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_SFLSilCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_SFLSilCU >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_SFLSilCU >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_SFLSilCU >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_SFLSilCU >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_SFLSilCU >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_SFLSilCU >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_SFLSilCU >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_SFLSilCU & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_SFLSilCU_DLC; + *_ide = (uint8_t) Diag_To_SFLSilCU_IDE; + return Diag_To_SFLSilCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_WHFL_candb(Diag_To_WHFL_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_WHFL = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_WHFL_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_WHFL_candb(&_m->mon1, Diag_To_WHFL_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_WHFL_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_WHFL_candb(Diag_To_WHFL_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_WHFL_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_WHFL >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_WHFL >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_WHFL >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_WHFL >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_WHFL >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_WHFL >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_WHFL >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_WHFL & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_WHFL_CANID; + cframe->DLC = (uint8_t) Diag_To_WHFL_DLC; + cframe->IDE = (uint8_t) Diag_To_WHFL_IDE; + return Diag_To_WHFL_CANID; +} + +#else + +uint32_t Pack_Diag_To_WHFL_candb(Diag_To_WHFL_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_WHFL_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_WHFL >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_WHFL >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_WHFL >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_WHFL >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_WHFL >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_WHFL >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_WHFL >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_WHFL & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_WHFL_DLC; + *_ide = (uint8_t) Diag_To_WHFL_IDE; + return Diag_To_WHFL_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_WHFR_candb(Diag_To_WHFR_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_To_WHFR = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_To_WHFR_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_To_WHFR_candb(&_m->mon1, Diag_To_WHFR_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_To_WHFR_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_To_WHFR_candb(Diag_To_WHFR_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_WHFR_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_To_WHFR >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_To_WHFR >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_To_WHFR >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_To_WHFR >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_To_WHFR >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_To_WHFR >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_To_WHFR >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_To_WHFR & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_To_WHFR_CANID; + cframe->DLC = (uint8_t) Diag_To_WHFR_DLC; + cframe->IDE = (uint8_t) Diag_To_WHFR_IDE; + return Diag_To_WHFR_CANID; +} + +#else + +uint32_t Pack_Diag_To_WHFR_candb(Diag_To_WHFR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_To_WHFR_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_To_WHFR >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_To_WHFR >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_To_WHFR >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_To_WHFR >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_To_WHFR >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_To_WHFR >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_To_WHFR >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_To_WHFR & (0xFFU)) ); + + *_len = (uint8_t) Diag_To_WHFR_DLC; + *_ide = (uint8_t) Diag_To_WHFR_IDE; + return Diag_To_WHFR_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_SFRSilCU_candb(Diag_From_SFRSilCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_SFRSilCU = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_SFRSilCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_SFRSilCU_candb(&_m->mon1, Diag_From_SFRSilCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_SFRSilCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_SFRSilCU_candb(Diag_From_SFRSilCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_SFRSilCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_SFRSilCU >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_SFRSilCU >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_SFRSilCU >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_SFRSilCU >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_SFRSilCU >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_SFRSilCU >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_SFRSilCU >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_SFRSilCU & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_SFRSilCU_CANID; + cframe->DLC = (uint8_t) Diag_From_SFRSilCU_DLC; + cframe->IDE = (uint8_t) Diag_From_SFRSilCU_IDE; + return Diag_From_SFRSilCU_CANID; +} + +#else + +uint32_t Pack_Diag_From_SFRSilCU_candb(Diag_From_SFRSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_SFRSilCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_SFRSilCU >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_SFRSilCU >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_SFRSilCU >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_SFRSilCU >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_SFRSilCU >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_SFRSilCU >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_SFRSilCU >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_SFRSilCU & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_SFRSilCU_DLC; + *_ide = (uint8_t) Diag_From_SFRSilCU_IDE; + return Diag_From_SFRSilCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_SFLSilCU_candb(Diag_From_SFLSilCU_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_SFLSilCU = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_SFLSilCU_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_SFLSilCU_candb(&_m->mon1, Diag_From_SFLSilCU_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_SFLSilCU_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_SFLSilCU_candb(Diag_From_SFLSilCU_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_SFLSilCU_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_SFLSilCU >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_SFLSilCU >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_SFLSilCU >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_SFLSilCU >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_SFLSilCU >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_SFLSilCU >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_SFLSilCU >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_SFLSilCU & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_SFLSilCU_CANID; + cframe->DLC = (uint8_t) Diag_From_SFLSilCU_DLC; + cframe->IDE = (uint8_t) Diag_From_SFLSilCU_IDE; + return Diag_From_SFLSilCU_CANID; +} + +#else + +uint32_t Pack_Diag_From_SFLSilCU_candb(Diag_From_SFLSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_SFLSilCU_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_SFLSilCU >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_SFLSilCU >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_SFLSilCU >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_SFLSilCU >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_SFLSilCU >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_SFLSilCU >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_SFLSilCU >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_SFLSilCU & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_SFLSilCU_DLC; + *_ide = (uint8_t) Diag_From_SFLSilCU_IDE; + return Diag_From_SFLSilCU_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_WHFL_candb(Diag_From_WHFL_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_WHFL = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_WHFL_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_WHFL_candb(&_m->mon1, Diag_From_WHFL_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_WHFL_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_WHFL_candb(Diag_From_WHFL_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_WHFL_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_WHFL >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_WHFL >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_WHFL >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_WHFL >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_WHFL >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_WHFL >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_WHFL >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_WHFL & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_WHFL_CANID; + cframe->DLC = (uint8_t) Diag_From_WHFL_DLC; + cframe->IDE = (uint8_t) Diag_From_WHFL_IDE; + return Diag_From_WHFL_CANID; +} + +#else + +uint32_t Pack_Diag_From_WHFL_candb(Diag_From_WHFL_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_WHFL_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_WHFL >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_WHFL >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_WHFL >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_WHFL >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_WHFL >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_WHFL >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_WHFL >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_WHFL & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_WHFL_DLC; + *_ide = (uint8_t) Diag_From_WHFL_IDE; + return Diag_From_WHFL_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_WHFR_candb(Diag_From_WHFR_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->Diag_From_WHFR = (uint64_t) ( ((uint64_t)(_d[0] & (0xFFU)) << 56U) | ((uint64_t)(_d[1] & (0xFFU)) << 48U) | ((uint64_t)(_d[2] & (0xFFU)) << 40U) | ((uint64_t)(_d[3] & (0xFFU)) << 32U) | ((_d[4] & (0xFFU)) << 24U) | ((_d[5] & (0xFFU)) << 16U) | ((_d[6] & (0xFFU)) << 8U) | (_d[7] & (0xFFU)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < Diag_From_WHFR_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_Diag_From_WHFR_candb(&_m->mon1, Diag_From_WHFR_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return Diag_From_WHFR_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_Diag_From_WHFR_candb(Diag_From_WHFR_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_WHFR_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + + cframe->Data[0] |= (uint8_t) ( ((_m->Diag_From_WHFR >> 56U) & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->Diag_From_WHFR >> 48U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( ((_m->Diag_From_WHFR >> 40U) & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( ((_m->Diag_From_WHFR >> 32U) & (0xFFU)) ); + cframe->Data[4] |= (uint8_t) ( ((_m->Diag_From_WHFR >> 24U) & (0xFFU)) ); + cframe->Data[5] |= (uint8_t) ( ((_m->Diag_From_WHFR >> 16U) & (0xFFU)) ); + cframe->Data[6] |= (uint8_t) ( ((_m->Diag_From_WHFR >> 8U) & (0xFFU)) ); + cframe->Data[7] |= (uint8_t) ( (_m->Diag_From_WHFR & (0xFFU)) ); + + cframe->MsgId = (uint32_t) Diag_From_WHFR_CANID; + cframe->DLC = (uint8_t) Diag_From_WHFR_DLC; + cframe->IDE = (uint8_t) Diag_From_WHFR_IDE; + return Diag_From_WHFR_CANID; +} + +#else + +uint32_t Pack_Diag_From_WHFR_candb(Diag_From_WHFR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(Diag_From_WHFR_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + + _d[0] |= (uint8_t) ( ((_m->Diag_From_WHFR >> 56U) & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->Diag_From_WHFR >> 48U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( ((_m->Diag_From_WHFR >> 40U) & (0xFFU)) ); + _d[3] |= (uint8_t) ( ((_m->Diag_From_WHFR >> 32U) & (0xFFU)) ); + _d[4] |= (uint8_t) ( ((_m->Diag_From_WHFR >> 24U) & (0xFFU)) ); + _d[5] |= (uint8_t) ( ((_m->Diag_From_WHFR >> 16U) & (0xFFU)) ); + _d[6] |= (uint8_t) ( ((_m->Diag_From_WHFR >> 8U) & (0xFFU)) ); + _d[7] |= (uint8_t) ( (_m->Diag_From_WHFR & (0xFFU)) ); + + *_len = (uint8_t) Diag_From_WHFR_DLC; + *_ide = (uint8_t) Diag_From_WHFR_IDE; + return Diag_From_WHFR_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_CCU_AC_Ctrl_candb(CCU_AC_Ctrl_t* _m, const uint8_t* _d, uint8_t dlc_) +{ + (void)dlc_; + _m->CCU_VCU_ACSpeedReq = (uint16_t) ( ((_d[1] & (0xFFU)) << 8U) | (_d[0] & (0xFFU)) ); + _m->CCU_ACMaxPowerConsumptionAllow_ro = (uint8_t) ( (_d[2] & (0xFFU)) ); +#ifdef CANDB_USE_SIGFLOAT + _m->CCU_ACMaxPowerConsumptionAllow_phys = (sigfloat_t)(CANDB_CCU_ACMaxPowerConsumptionAllow_ro_fromS(_m->CCU_ACMaxPowerConsumptionAllow_ro)); +#endif // CANDB_USE_SIGFLOAT + + _m->CCU_VCU_AC_WorkReq = (uint8_t) ( (_d[3] & (0x01U)) ); + +#ifdef CANDB_USE_DIAG_MONITORS + _m->mon1.dlc_error = (dlc_ < CCU_AC_Ctrl_DLC); + _m->mon1.last_cycle = GetSystemTick(); + _m->mon1.frame_cnt++; + + FMon_CCU_AC_Ctrl_candb(&_m->mon1, CCU_AC_Ctrl_CANID); +#endif // CANDB_USE_DIAG_MONITORS + + return CCU_AC_Ctrl_CANID; +} + +#ifdef CANDB_USE_CANSTRUCT + +uint32_t Pack_CCU_AC_Ctrl_candb(CCU_AC_Ctrl_t* _m, __CoderDbcCanFrame_t__* cframe) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(CCU_AC_Ctrl_DLC); cframe->Data[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->CCU_ACMaxPowerConsumptionAllow_ro = (uint8_t) CANDB_CCU_ACMaxPowerConsumptionAllow_ro_toS(_m->CCU_ACMaxPowerConsumptionAllow_phys); +#endif // CANDB_USE_SIGFLOAT + + cframe->Data[0] |= (uint8_t) ( (_m->CCU_VCU_ACSpeedReq & (0xFFU)) ); + cframe->Data[1] |= (uint8_t) ( ((_m->CCU_VCU_ACSpeedReq >> 8U) & (0xFFU)) ); + cframe->Data[2] |= (uint8_t) ( (_m->CCU_ACMaxPowerConsumptionAllow_ro & (0xFFU)) ); + cframe->Data[3] |= (uint8_t) ( (_m->CCU_VCU_AC_WorkReq & (0x01U)) ); + + cframe->MsgId = (uint32_t) CCU_AC_Ctrl_CANID; + cframe->DLC = (uint8_t) CCU_AC_Ctrl_DLC; + cframe->IDE = (uint8_t) CCU_AC_Ctrl_IDE; + return CCU_AC_Ctrl_CANID; +} + +#else + +uint32_t Pack_CCU_AC_Ctrl_candb(CCU_AC_Ctrl_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide) +{ + uint8_t i; for (i = 0u; i < CANDB_VALIDATE_DLC(CCU_AC_Ctrl_DLC); _d[i++] = CANDB_INITIAL_BYTE_VALUE); + +#ifdef CANDB_USE_SIGFLOAT + _m->CCU_ACMaxPowerConsumptionAllow_ro = (uint8_t) CANDB_CCU_ACMaxPowerConsumptionAllow_ro_toS(_m->CCU_ACMaxPowerConsumptionAllow_phys); +#endif // CANDB_USE_SIGFLOAT + + _d[0] |= (uint8_t) ( (_m->CCU_VCU_ACSpeedReq & (0xFFU)) ); + _d[1] |= (uint8_t) ( ((_m->CCU_VCU_ACSpeedReq >> 8U) & (0xFFU)) ); + _d[2] |= (uint8_t) ( (_m->CCU_ACMaxPowerConsumptionAllow_ro & (0xFFU)) ); + _d[3] |= (uint8_t) ( (_m->CCU_VCU_AC_WorkReq & (0x01U)) ); + + *_len = (uint8_t) CCU_AC_Ctrl_DLC; + *_ide = (uint8_t) CCU_AC_Ctrl_IDE; + return CCU_AC_Ctrl_CANID; +} + +#endif // CANDB_USE_CANSTRUCT + diff --git a/MODULES/HVAC_M7_CAN_MATRIX/lib/candb.h b/MODULES/HVAC_M7_CAN_MATRIX/lib/candb.h new file mode 100644 index 0000000..c29057f --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/lib/candb.h @@ -0,0 +1,58406 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +// DBC file version +#define VER_CANDB_MAJ (0U) +#define VER_CANDB_MIN (0U) + +// include current dbc-driver compilation config +#include "candb-config.h" + +#ifdef CANDB_USE_DIAG_MONITORS +// This file must define: +// base monitor struct +#include "canmonitorutil.h" + +#endif // CANDB_USE_DIAG_MONITORS + + +// DLC maximum value which is used as the limit for frame's data buffer size. +// Client can set its own value (not sure why) in driver-config +// or can test it on some limit specified by application +// e.g.: static_assert(TESTDB_MAX_DLC_VALUE <= APPLICATION_FRAME_DATA_SIZE, "Max DLC value in the driver is too big") +#ifndef CANDB_MAX_DLC_VALUE +// The value which was found out by generator (real max value) +#define CANDB_MAX_DLC_VALUE 8U +#endif + +// The limit is used for setting frame's data bytes +#define CANDB_VALIDATE_DLC(msgDlc) (((msgDlc) <= (CANDB_MAX_DLC_VALUE)) ? (msgDlc) : (CANDB_MAX_DLC_VALUE)) + +// Initial byte value to be filles in data bytes of the frame before pack signals +// User can define its own custom value in driver-config file +#ifndef CANDB_INITIAL_BYTE_VALUE +#define CANDB_INITIAL_BYTE_VALUE 0U +#endif + + +// def @SDM_MAS_Req CAN Message (81 0x51) +#define SDM_MAS_Req_IDE (0U) +#define SDM_MAS_Req_DLC (4U) +#define SDM_MAS_Req_CANID (0x51U) +#define SDM_MAS_Req_CYC (100U) + +// Value tables for @SDM_AVM_Active_Req signal + +#ifndef SDM_AVM_Active_Req_SDM_MAS_Req_Requested +#define SDM_AVM_Active_Req_SDM_MAS_Req_Requested (1) +#endif + +#ifndef SDM_AVM_Active_Req_SDM_MAS_Req_Not_requested +#define SDM_AVM_Active_Req_SDM_MAS_Req_Not_requested (0) +#endif + + +// Value tables for @SDM_MAS_Mode_Req signal + +#ifndef SDM_MAS_Mode_Req_SDM_MAS_Req_APA +#define SDM_MAS_Mode_Req_SDM_MAS_Req_APA (2) +#endif + +#ifndef SDM_MAS_Mode_Req_SDM_MAS_Req_AVM +#define SDM_MAS_Mode_Req_SDM_MAS_Req_AVM (1) +#endif + +#ifndef SDM_MAS_Mode_Req_SDM_MAS_Req_No_change +#define SDM_MAS_Mode_Req_SDM_MAS_Req_No_change (0) +#endif + + +// Value tables for @SDM_APAactive_Req signal + +#ifndef SDM_APAactive_Req_SDM_MAS_Req_Not_requested +#define SDM_APAactive_Req_SDM_MAS_Req_Not_requested (0) +#endif + +#ifndef SDM_APAactive_Req_SDM_MAS_Req_Requested +#define SDM_APAactive_Req_SDM_MAS_Req_Requested (1) +#endif + + +// Value tables for @SDM_CntrlBtnAPA_Req signal + +#ifndef SDM_CntrlBtnAPA_Req_SDM_MAS_Req_Button_not_pressed +#define SDM_CntrlBtnAPA_Req_SDM_MAS_Req_Button_not_pressed (0) +#endif + +#ifndef SDM_CntrlBtnAPA_Req_SDM_MAS_Req_Button_pressed +#define SDM_CntrlBtnAPA_Req_SDM_MAS_Req_Button_pressed (1) +#endif + + +// Value tables for @SDM_StartAPA_Req signal + +#ifndef SDM_StartAPA_Req_SDM_MAS_Req_Not_requested +#define SDM_StartAPA_Req_SDM_MAS_Req_Not_requested (0) +#endif + +#ifndef SDM_StartAPA_Req_SDM_MAS_Req_Requested +#define SDM_StartAPA_Req_SDM_MAS_Req_Requested (1) +#endif + + +// Value tables for @SDM_MASoff_Req signal + +#ifndef SDM_MASoff_Req_SDM_MAS_Req_Not_requested +#define SDM_MASoff_Req_SDM_MAS_Req_Not_requested (0) +#endif + +#ifndef SDM_MASoff_Req_SDM_MAS_Req_Requested +#define SDM_MASoff_Req_SDM_MAS_Req_Requested (1) +#endif + + +// Value tables for @SDM_ManeuverAllowed_Stat signal + +#ifndef SDM_ManeuverAllowed_Stat_SDM_MAS_Req_Not_accepted +#define SDM_ManeuverAllowed_Stat_SDM_MAS_Req_Not_accepted (0) +#endif + +#ifndef SDM_ManeuverAllowed_Stat_SDM_MAS_Req_Accepted +#define SDM_ManeuverAllowed_Stat_SDM_MAS_Req_Accepted (1) +#endif + + +// Value tables for @SDM_PhoneAppAvail_Stat signal + +#ifndef SDM_PhoneAppAvail_Stat_SDM_MAS_Req_Available +#define SDM_PhoneAppAvail_Stat_SDM_MAS_Req_Available (1) +#endif + +#ifndef SDM_PhoneAppAvail_Stat_SDM_MAS_Req_Not_available +#define SDM_PhoneAppAvail_Stat_SDM_MAS_Req_Not_available (0) +#endif + + +// Value tables for @SDM_ParkingOutPath_Req signal + +#ifndef SDM_ParkingOutPath_Req_SDM_MAS_Req_Straight +#define SDM_ParkingOutPath_Req_SDM_MAS_Req_Straight (3) +#endif + +#ifndef SDM_ParkingOutPath_Req_SDM_MAS_Req_Nothing +#define SDM_ParkingOutPath_Req_SDM_MAS_Req_Nothing (0) +#endif + +#ifndef SDM_ParkingOutPath_Req_SDM_MAS_Req_Left +#define SDM_ParkingOutPath_Req_SDM_MAS_Req_Left (1) +#endif + +#ifndef SDM_ParkingOutPath_Req_SDM_MAS_Req_Right +#define SDM_ParkingOutPath_Req_SDM_MAS_Req_Right (2) +#endif + + +// Value tables for @SDM_CtrlAPAerr_Stat signal + +#ifndef SDM_CtrlAPAerr_Stat_SDM_MAS_Req_No_error +#define SDM_CtrlAPAerr_Stat_SDM_MAS_Req_No_error (0) +#endif + +#ifndef SDM_CtrlAPAerr_Stat_SDM_MAS_Req_No_connection +#define SDM_CtrlAPAerr_Stat_SDM_MAS_Req_No_connection (1) +#endif + +#ifndef SDM_CtrlAPAerr_Stat_SDM_MAS_Req_Too_far +#define SDM_CtrlAPAerr_Stat_SDM_MAS_Req_Too_far (2) +#endif + +#ifndef SDM_CtrlAPAerr_Stat_SDM_MAS_Req_Malfunction +#define SDM_CtrlAPAerr_Stat_SDM_MAS_Req_Malfunction (3) +#endif + +#ifndef SDM_CtrlAPAerr_Stat_SDM_MAS_Req_Rejected_by_user +#define SDM_CtrlAPAerr_Stat_SDM_MAS_Req_Rejected_by_user (4) +#endif + + +// Value tables for @SDM_ContinueMove_Req signal + +#ifndef SDM_ContinueMove_Req_SDM_MAS_Req_Requested +#define SDM_ContinueMove_Req_SDM_MAS_Req_Requested (1) +#endif + +#ifndef SDM_ContinueMove_Req_SDM_MAS_Req_Not_requested +#define SDM_ContinueMove_Req_SDM_MAS_Req_Not_requested (0) +#endif + + +// Value tables for @SDM_FIUmaster_Req signal + +#ifndef SDM_FIUmaster_Req_SDM_MAS_Req_Requested +#define SDM_FIUmaster_Req_SDM_MAS_Req_Requested (1) +#endif + +#ifndef SDM_FIUmaster_Req_SDM_MAS_Req_Not_requested +#define SDM_FIUmaster_Req_SDM_MAS_Req_Not_requested (0) +#endif + + +// Value tables for @SDM_View_Req signal + +#ifndef SDM_View_Req_SDM_MAS_Req_D_Rear_Right +#define SDM_View_Req_SDM_MAS_Req_D_Rear_Right (7) +#endif + +#ifndef SDM_View_Req_SDM_MAS_Req_D_Rear_Left +#define SDM_View_Req_SDM_MAS_Req_D_Rear_Left (6) +#endif + +#ifndef SDM_View_Req_SDM_MAS_Req_D_Front_Right +#define SDM_View_Req_SDM_MAS_Req_D_Front_Right (5) +#endif + +#ifndef SDM_View_Req_SDM_MAS_Req_D_Front_Left +#define SDM_View_Req_SDM_MAS_Req_D_Front_Left (4) +#endif + +#ifndef SDM_View_Req_SDM_MAS_Req_D_Main_Rear_Top_View +#define SDM_View_Req_SDM_MAS_Req_D_Main_Rear_Top_View (3) +#endif + +#ifndef SDM_View_Req_SDM_MAS_Req_D_Rear +#define SDM_View_Req_SDM_MAS_Req_D_Rear (2) +#endif + +#ifndef SDM_View_Req_SDM_MAS_Req_D_Front +#define SDM_View_Req_SDM_MAS_Req_D_Front (1) +#endif + +#ifndef SDM_View_Req_SDM_MAS_Req_Nothing +#define SDM_View_Req_SDM_MAS_Req_Nothing (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Request from SDM to enable AVM or APA (active for 3 frames) + // 1 : "Requested" + // 0 : "Not requested" + uint8_t SDM_AVM_Active_Req : 1; // Bits= 1 + + // Request from SDM to enable AVM or APA. The signal value should be 3 frames long (SDM_AVM_Active_Req, SDM_MAS_Mode_Req, SDM_View_Req) + // 2 : "APA" + // 1 : "AVM" + // 0 : "No change" + uint8_t SDM_MAS_Mode_Req : 1; // Bits= 1 + + // Request to parking out + // 0 : "Not requested" + // 1 : "Requested" + uint8_t SDM_APAactive_Req : 1; // Bits= 1 + + // Status, defined that driver pressed the Control button in phone display + // 0 : "Button not pressed" + // 1 : "Button pressed" + uint8_t SDM_CntrlBtnAPA_Req : 1; // Bits= 1 + + // Request for remote start of APA + // 0 : "Not requested" + // 1 : "Requested" + uint8_t SDM_StartAPA_Req : 1; // Bits= 1 + + // MAS off request + // 0 : "Not requested" + // 1 : "Requested" + uint8_t SDM_MASoff_Req : 1; // Bits= 1 + + // Moving init from SDM on user phone + // 0 : "Not accepted" + // 1 : "Accepted" + uint8_t SDM_ManeuverAllowed_Stat : 1; // Bits= 1 + + // Status of the application presence on the phone. + // 1 : "Available" + // 0 : "Not available" + uint8_t SDM_PhoneAppAvail_Stat : 1; // Bits= 1 + + // The parking out path, that selected by the user + // 3 : "Straight" + // 0 : "Nothing" + // 1 : "Left" + // 2 : "Right" + uint8_t SDM_ParkingOutPath_Req : 2; // Bits= 2 + + // Control APA from phone error status + // 0 : "No error" + // 1 : "No connection" + // 2 : "Too far" + // 3 : "Malfunction" + // 4 : "Rejected by user" + uint8_t SDM_CtrlAPAerr_Stat : 3; // Bits= 3 + + // This is a request to continue a parking maneuver from SDM + // 1 : "Requested" + // 0 : "Not requested" + uint8_t SDM_ContinueMove_Req : 1; // Bits= 1 + + // Request from SDM to change control to FIU. + // 1 : "Requested" + // 0 : "Not requested" + uint8_t SDM_FIUmaster_Req : 1; // Bits= 1 + + // Request from SDM to activate the view + // 7 : "3D Rear Right" + // 6 : "3D Rear Left" + // 5 : "3D Front Right" + // 4 : "3D Front Left" + // 3 : "3D Main (Rear Top View)" + // 2 : "2D Rear" + // 1 : "2D Front" + // 0 : "Nothing" + uint8_t SDM_View_Req : 4; // Bits= 4 + + // Rolling Counter [0 - 15] + uint8_t SDM_MAS_Req_RC : 4; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t SDM_MAS_Req_CS; // Bits= 8 + +#else + + // Request from SDM to enable AVM or APA (active for 3 frames) + // 1 : "Requested" + // 0 : "Not requested" + uint8_t SDM_AVM_Active_Req; // Bits= 1 + + // Request from SDM to enable AVM or APA. The signal value should be 3 frames long (SDM_AVM_Active_Req, SDM_MAS_Mode_Req, SDM_View_Req) + // 2 : "APA" + // 1 : "AVM" + // 0 : "No change" + uint8_t SDM_MAS_Mode_Req; // Bits= 1 + + // Request to parking out + // 0 : "Not requested" + // 1 : "Requested" + uint8_t SDM_APAactive_Req; // Bits= 1 + + // Status, defined that driver pressed the Control button in phone display + // 0 : "Button not pressed" + // 1 : "Button pressed" + uint8_t SDM_CntrlBtnAPA_Req; // Bits= 1 + + // Request for remote start of APA + // 0 : "Not requested" + // 1 : "Requested" + uint8_t SDM_StartAPA_Req; // Bits= 1 + + // MAS off request + // 0 : "Not requested" + // 1 : "Requested" + uint8_t SDM_MASoff_Req; // Bits= 1 + + // Moving init from SDM on user phone + // 0 : "Not accepted" + // 1 : "Accepted" + uint8_t SDM_ManeuverAllowed_Stat; // Bits= 1 + + // Status of the application presence on the phone. + // 1 : "Available" + // 0 : "Not available" + uint8_t SDM_PhoneAppAvail_Stat; // Bits= 1 + + // The parking out path, that selected by the user + // 3 : "Straight" + // 0 : "Nothing" + // 1 : "Left" + // 2 : "Right" + uint8_t SDM_ParkingOutPath_Req; // Bits= 2 + + // Control APA from phone error status + // 0 : "No error" + // 1 : "No connection" + // 2 : "Too far" + // 3 : "Malfunction" + // 4 : "Rejected by user" + uint8_t SDM_CtrlAPAerr_Stat; // Bits= 3 + + // This is a request to continue a parking maneuver from SDM + // 1 : "Requested" + // 0 : "Not requested" + uint8_t SDM_ContinueMove_Req; // Bits= 1 + + // Request from SDM to change control to FIU. + // 1 : "Requested" + // 0 : "Not requested" + uint8_t SDM_FIUmaster_Req; // Bits= 1 + + // Request from SDM to activate the view + // 7 : "3D Rear Right" + // 6 : "3D Rear Left" + // 5 : "3D Front Right" + // 4 : "3D Front Left" + // 3 : "3D Main (Rear Top View)" + // 2 : "2D Rear" + // 1 : "2D Front" + // 0 : "Nothing" + uint8_t SDM_View_Req; // Bits= 4 + + // Rolling Counter [0 - 15] + uint8_t SDM_MAS_Req_RC; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t SDM_MAS_Req_CS; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} SDM_MAS_Req_t; + +// def @EMS_VCU_VAU_Immo_Req CAN Message (136 0x88) +#define EMS_VCU_VAU_Immo_Req_IDE (0U) +#define EMS_VCU_VAU_Immo_Req_DLC (8U) +#define EMS_VCU_VAU_Immo_Req_CANID (0x88U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + uint64_t EMS_VCU_VAU_Immo_Req; // Bits=64 + +#else + + uint64_t EMS_VCU_VAU_Immo_Req; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} EMS_VCU_VAU_Immo_Req_t; + +// def @TCU_VAU_Immo_Req CAN Message (138 0x8a) +#define TCU_VAU_Immo_Req_IDE (0U) +#define TCU_VAU_Immo_Req_DLC (8U) +#define TCU_VAU_Immo_Req_CANID (0x8aU) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + uint64_t TCU_VAU_Immo_Req; // Bits=64 + +#else + + uint64_t TCU_VAU_Immo_Req; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} TCU_VAU_Immo_Req_t; + +// def @VAU2_NFC_TransferState CAN Message (142 0x8e) +#define VAU2_NFC_TransferState_IDE (0U) +#define VAU2_NFC_TransferState_DLC (8U) +#define VAU2_NFC_TransferState_CANID (0x8eU) + +// Value tables for @VAU_NFC_FrameNumber signal + +#ifndef VAU_NFC_FrameNumber_VAU2_NFC_TransferState_Max_Frame +#define VAU_NFC_FrameNumber_VAU2_NFC_TransferState_Max_Frame (21) +#endif + +#ifndef VAU_NFC_FrameNumber_VAU2_NFC_TransferState_Fourth_Frame +#define VAU_NFC_FrameNumber_VAU2_NFC_TransferState_Fourth_Frame (3) +#endif + +#ifndef VAU_NFC_FrameNumber_VAU2_NFC_TransferState_Third_Frame +#define VAU_NFC_FrameNumber_VAU2_NFC_TransferState_Third_Frame (2) +#endif + +#ifndef VAU_NFC_FrameNumber_VAU2_NFC_TransferState_Second_Frame +#define VAU_NFC_FrameNumber_VAU2_NFC_TransferState_Second_Frame (1) +#endif + +#ifndef VAU_NFC_FrameNumber_VAU2_NFC_TransferState_First_Frame +#define VAU_NFC_FrameNumber_VAU2_NFC_TransferState_First_Frame (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Number of frame with useful data + // 21 : "Max. Frame" + // 3 : "Fourth Frame" + // 2 : "Third Frame" + // 1 : "Second Frame" + // 0 : "First Frame" + uint8_t VAU_NFC_FrameNumber : 4; // Bits= 4 + + // Total number of frames, which will be transferred in active NFC sesion + uint8_t VAU_NFC_FrameTotalNumber : 4; // Bits= 4 + + // Useful information transmitted from the VAU block to the WchF block + uint64_t VAU_NFC_TransferData; // Bits=56 + +#else + + // Number of frame with useful data + // 21 : "Max. Frame" + // 3 : "Fourth Frame" + // 2 : "Third Frame" + // 1 : "Second Frame" + // 0 : "First Frame" + uint8_t VAU_NFC_FrameNumber; // Bits= 4 + + // Total number of frames, which will be transferred in active NFC sesion + uint8_t VAU_NFC_FrameTotalNumber; // Bits= 4 + + // Useful information transmitted from the VAU block to the WchF block + uint64_t VAU_NFC_TransferData; // Bits=56 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} VAU2_NFC_TransferState_t; + +// def @VAU_TCU_Hash_Resp CAN Message (143 0x8f) +#define VAU_TCU_Hash_Resp_IDE (0U) +#define VAU_TCU_Hash_Resp_DLC (8U) +#define VAU_TCU_Hash_Resp_CANID (0x8fU) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Response to Immo request from TCU when starting the engine + uint64_t VAU_TCU_Hash_Resp; // Bits=64 + +#else + + // Response to Immo request from TCU when starting the engine + uint64_t VAU_TCU_Hash_Resp; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} VAU_TCU_Hash_Resp_t; + +// def @VAU_EMS_VCU_Hash_Resp CAN Message (145 0x91) +#define VAU_EMS_VCU_Hash_Resp_IDE (0U) +#define VAU_EMS_VCU_Hash_Resp_DLC (8U) +#define VAU_EMS_VCU_Hash_Resp_CANID (0x91U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Response to Immo request from EMS when starting the engine + uint64_t VAU_EMS_VCU_Hash_Resp; // Bits=64 + +#else + + // Response to Immo request from EMS when starting the engine + uint64_t VAU_EMS_VCU_Hash_Resp; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} VAU_EMS_VCU_Hash_Resp_t; + +// def @VAU2_INVRL_Hash_Resp CAN Message (148 0x94) +#define VAU2_INVRL_Hash_Resp_IDE (0U) +#define VAU2_INVRL_Hash_Resp_DLC (8U) +#define VAU2_INVRL_Hash_Resp_CANID (0x94U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Response to authorization request to start movement VAU->INV2 + uint64_t VAU2_INVRL_Hash_Resp; // Bits=64 + +#else + + // Response to authorization request to start movement VAU->INV2 + uint64_t VAU2_INVRL_Hash_Resp; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} VAU2_INVRL_Hash_Resp_t; + +// def @WChF_NFC_VAU_Transfer_State CAN Message (149 0x95) +#define WChF_NFC_VAU_Transfer_State_IDE (0U) +#define WChF_NFC_VAU_Transfer_State_DLC (8U) +#define WChF_NFC_VAU_Transfer_State_CANID (0x95U) +// signal: @WChF_NFC_FrameNumber_Val_ro +#define CANDB_WChF_NFC_FrameNumber_Val_ro_CovFactor (1) +#define CANDB_WChF_NFC_FrameNumber_Val_ro_toS(x) ( (uint8_t) ((x) - (1)) ) +#define CANDB_WChF_NFC_FrameNumber_Val_ro_fromS(x) ( ((x) + (1)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Number of frame with useful data + uint8_t WChF_NFC_FrameNumber_Val_ro : 4; // Bits= 4 Offset= 1 + +#ifdef CANDB_USE_SIGFLOAT + uint8_t WChF_NFC_FrameNumber_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Total number of frames, which will be transferred in active NFC sesion + uint8_t WChF_NFCFrameTotalNum_Val : 4; // Bits= 4 + + // Smartphone_Hash_Immo + uint64_t WChF_NFCTransferData_Val; // Bits=56 + +#else + + // Number of frame with useful data + uint8_t WChF_NFC_FrameNumber_Val_ro; // Bits= 4 Offset= 1 + +#ifdef CANDB_USE_SIGFLOAT + uint8_t WChF_NFC_FrameNumber_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Total number of frames, which will be transferred in active NFC sesion + uint8_t WChF_NFCFrameTotalNum_Val; // Bits= 4 + + // Smartphone_Hash_Immo + uint64_t WChF_NFCTransferData_Val; // Bits=56 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} WChF_NFC_VAU_Transfer_State_t; + +// def @VAU2_INVRR_Hash_Resp CAN Message (152 0x98) +#define VAU2_INVRR_Hash_Resp_IDE (0U) +#define VAU2_INVRR_Hash_Resp_DLC (8U) +#define VAU2_INVRR_Hash_Resp_CANID (0x98U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Response to authorization request to start movement VAU->INV3 + uint64_t VAU2_INVRR_Hash_Resp; // Bits=64 + +#else + + // Response to authorization request to start movement VAU->INV3 + uint64_t VAU2_INVRR_Hash_Resp; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} VAU2_INVRR_Hash_Resp_t; + +// def @VAU_SDM_Immo_Req CAN Message (153 0x99) +#define VAU_SDM_Immo_Req_IDE (0U) +#define VAU_SDM_Immo_Req_DLC (8U) +#define VAU_SDM_Immo_Req_CANID (0x99U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Immo request to SDM unit + uint64_t VAU_SDM_Immo_Req; // Bits=64 + +#else + + // Immo request to SDM unit + uint64_t VAU_SDM_Immo_Req; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} VAU_SDM_Immo_Req_t; + +// def @SDM_VAU_Hash_Resp CAN Message (160 0xa0) +#define SDM_VAU_Hash_Resp_IDE (0U) +#define SDM_VAU_Hash_Resp_DLC (8U) +#define SDM_VAU_Hash_Resp_CANID (0xa0U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Hash_SDM + // 0x0 to 0xFF + uint64_t SDM_VAU_Hash_RESC; // Bits=64 + +#else + + // Hash_SDM + // 0x0 to 0xFF + uint64_t SDM_VAU_Hash_RESC; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} SDM_VAU_Hash_Resp_t; + +// def @TCU_R932_1 CAN Message (177 0xb1) +#define TCU_R932_1_IDE (0U) +#define TCU_R932_1_DLC (8U) +#define TCU_R932_1_CANID (0xb1U) +#define TCU_R932_1_CYC (10U) + +// Value tables for @numGearTarget signal + +#ifndef numGearTarget_TCU_R932_1_Default +#define numGearTarget_TCU_R932_1_Default (15) +#endif + +#ifndef numGearTarget_TCU_R932_1_Unavailable +#define numGearTarget_TCU_R932_1_Unavailable (14) +#endif + +#ifndef numGearTarget_TCU_R932_1_Undefined +#define numGearTarget_TCU_R932_1_Undefined (13) +#endif + +#ifndef numGearTarget_TCU_R932_1_Undefined +#define numGearTarget_TCU_R932_1_Undefined (12) +#endif + +#ifndef numGearTarget_TCU_R932_1_Undefined +#define numGearTarget_TCU_R932_1_Undefined (11) +#endif + +#ifndef numGearTarget_TCU_R932_1_Reverse +#define numGearTarget_TCU_R932_1_Reverse (10) +#endif + +#ifndef numGearTarget_TCU_R932_1_Ninth_gear +#define numGearTarget_TCU_R932_1_Ninth_gear (9) +#endif + +#ifndef numGearTarget_TCU_R932_1_Eight_gear +#define numGearTarget_TCU_R932_1_Eight_gear (8) +#endif + +#ifndef numGearTarget_TCU_R932_1_Seventh_gear +#define numGearTarget_TCU_R932_1_Seventh_gear (7) +#endif + +#ifndef numGearTarget_TCU_R932_1_Sixth_gear +#define numGearTarget_TCU_R932_1_Sixth_gear (6) +#endif + +#ifndef numGearTarget_TCU_R932_1_Fifth_gear +#define numGearTarget_TCU_R932_1_Fifth_gear (5) +#endif + +#ifndef numGearTarget_TCU_R932_1_Fourth_gear +#define numGearTarget_TCU_R932_1_Fourth_gear (4) +#endif + +#ifndef numGearTarget_TCU_R932_1_Third_gear +#define numGearTarget_TCU_R932_1_Third_gear (3) +#endif + +#ifndef numGearTarget_TCU_R932_1_Second_gear +#define numGearTarget_TCU_R932_1_Second_gear (2) +#endif + +#ifndef numGearTarget_TCU_R932_1_First_gear +#define numGearTarget_TCU_R932_1_First_gear (1) +#endif + +#ifndef numGearTarget_TCU_R932_1_Neutral +#define numGearTarget_TCU_R932_1_Neutral (0) +#endif + + +// Value tables for @numGearEngaged signal + +#ifndef numGearEngaged_TCU_R932_1_Default +#define numGearEngaged_TCU_R932_1_Default (15) +#endif + +#ifndef numGearEngaged_TCU_R932_1_Unavailable +#define numGearEngaged_TCU_R932_1_Unavailable (14) +#endif + +#ifndef numGearEngaged_TCU_R932_1_Undefined +#define numGearEngaged_TCU_R932_1_Undefined (13) +#endif + +#ifndef numGearEngaged_TCU_R932_1_Undefined +#define numGearEngaged_TCU_R932_1_Undefined (12) +#endif + +#ifndef numGearEngaged_TCU_R932_1_Undefined +#define numGearEngaged_TCU_R932_1_Undefined (11) +#endif + +#ifndef numGearEngaged_TCU_R932_1_Reverse +#define numGearEngaged_TCU_R932_1_Reverse (10) +#endif + +#ifndef numGearEngaged_TCU_R932_1_Ninth_gear +#define numGearEngaged_TCU_R932_1_Ninth_gear (9) +#endif + +#ifndef numGearEngaged_TCU_R932_1_Eight_gear +#define numGearEngaged_TCU_R932_1_Eight_gear (8) +#endif + +#ifndef numGearEngaged_TCU_R932_1_Seventh_gear +#define numGearEngaged_TCU_R932_1_Seventh_gear (7) +#endif + +#ifndef numGearEngaged_TCU_R932_1_Sixth_gear +#define numGearEngaged_TCU_R932_1_Sixth_gear (6) +#endif + +#ifndef numGearEngaged_TCU_R932_1_Fifth_gear +#define numGearEngaged_TCU_R932_1_Fifth_gear (5) +#endif + +#ifndef numGearEngaged_TCU_R932_1_Fourth_gear +#define numGearEngaged_TCU_R932_1_Fourth_gear (4) +#endif + +#ifndef numGearEngaged_TCU_R932_1_Third_gear +#define numGearEngaged_TCU_R932_1_Third_gear (3) +#endif + +#ifndef numGearEngaged_TCU_R932_1_Second_gear +#define numGearEngaged_TCU_R932_1_Second_gear (2) +#endif + +#ifndef numGearEngaged_TCU_R932_1_First_gear +#define numGearEngaged_TCU_R932_1_First_gear (1) +#endif + +#ifndef numGearEngaged_TCU_R932_1_Neutral +#define numGearEngaged_TCU_R932_1_Neutral (0) +#endif + +// signal: @ratEng2GbxTorqueRatio_ro +#define CANDB_ratEng2GbxTorqueRatio_ro_CovFactor (0.01) +#define CANDB_ratEng2GbxTorqueRatio_ro_toS(x) ( (uint16_t) (((x) - (0.0)) / (0.01)) ) +#define CANDB_ratEng2GbxTorqueRatio_ro_fromS(x) ( (((x) * (0.01)) + (0.0)) ) + +// Value tables for @stGearLvr signal + +#ifndef stGearLvr_TCU_R932_1_Default +#define stGearLvr_TCU_R932_1_Default (7) +#endif + +#ifndef stGearLvr_TCU_R932_1_Not_available +#define stGearLvr_TCU_R932_1_Not_available (6) +#endif + +#ifndef stGearLvr_TCU_R932_1_undefined +#define stGearLvr_TCU_R932_1_undefined (5) +#endif + +#ifndef stGearLvr_TCU_R932_1_D +#define stGearLvr_TCU_R932_1_D (4) +#endif + +#ifndef stGearLvr_TCU_R932_1_N +#define stGearLvr_TCU_R932_1_N (3) +#endif + +#ifndef stGearLvr_TCU_R932_1_R +#define stGearLvr_TCU_R932_1_R (2) +#endif + +#ifndef stGearLvr_TCU_R932_1_P +#define stGearLvr_TCU_R932_1_P (1) +#endif + +#ifndef stGearLvr_TCU_R932_1_Error +#define stGearLvr_TCU_R932_1_Error (0) +#endif + + +// Value tables for @stGbxMILReq signal + +#ifndef stGbxMILReq_TCU_R932_1_Default +#define stGbxMILReq_TCU_R932_1_Default (3) +#endif + +#ifndef stGbxMILReq_TCU_R932_1_Not_Available +#define stGbxMILReq_TCU_R932_1_Not_Available (2) +#endif + +#ifndef stGbxMILReq_TCU_R932_1_MIL_ON +#define stGbxMILReq_TCU_R932_1_MIL_ON (1) +#endif + +#ifndef stGbxMILReq_TCU_R932_1_MIL_OFF +#define stGbxMILReq_TCU_R932_1_MIL_OFF (0) +#endif + + +// Value tables for @stGearboxMode signal + +#ifndef stGearboxMode_TCU_R932_1_Default +#define stGearboxMode_TCU_R932_1_Default (7) +#endif + +#ifndef stGearboxMode_TCU_R932_1_Not_available +#define stGearboxMode_TCU_R932_1_Not_available (6) +#endif + +#ifndef stGearboxMode_TCU_R932_1_Undefined +#define stGearboxMode_TCU_R932_1_Undefined (5) +#endif + +#ifndef stGearboxMode_TCU_R932_1_All_Season +#define stGearboxMode_TCU_R932_1_All_Season (4) +#endif + +#ifndef stGearboxMode_TCU_R932_1_Auto +#define stGearboxMode_TCU_R932_1_Auto (3) +#endif + +#ifndef stGearboxMode_TCU_R932_1_Comfort +#define stGearboxMode_TCU_R932_1_Comfort (2) +#endif + +#ifndef stGearboxMode_TCU_R932_1_Sport +#define stGearboxMode_TCU_R932_1_Sport (1) +#endif + +#ifndef stGearboxMode_TCU_R932_1_Error +#define stGearboxMode_TCU_R932_1_Error (0) +#endif + + +// Value tables for @stTransmissionWarnings signal + +#ifndef stTransmissionWarnings_TCU_R932_1_Default +#define stTransmissionWarnings_TCU_R932_1_Default (15) +#endif + +#ifndef stTransmissionWarnings_TCU_R932_1_Not_available +#define stTransmissionWarnings_TCU_R932_1_Not_available (14) +#endif + +#ifndef stTransmissionWarnings_TCU_R932_1_Undefined +#define stTransmissionWarnings_TCU_R932_1_Undefined (13) +#endif + +#ifndef stTransmissionWarnings_TCU_R932_1_Undefined +#define stTransmissionWarnings_TCU_R932_1_Undefined (12) +#endif + +#ifndef stTransmissionWarnings_TCU_R932_1_Undefined +#define stTransmissionWarnings_TCU_R932_1_Undefined (11) +#endif + +#ifndef stTransmissionWarnings_TCU_R932_1_Undefined +#define stTransmissionWarnings_TCU_R932_1_Undefined (10) +#endif + +#ifndef stTransmissionWarnings_TCU_R932_1_Undefined +#define stTransmissionWarnings_TCU_R932_1_Undefined (9) +#endif + +#ifndef stTransmissionWarnings_TCU_R932_1_Undefined +#define stTransmissionWarnings_TCU_R932_1_Undefined (8) +#endif + +#ifndef stTransmissionWarnings_TCU_R932_1_Undefined +#define stTransmissionWarnings_TCU_R932_1_Undefined (7) +#endif + +#ifndef stTransmissionWarnings_TCU_R932_1_Drive_to_stop +#define stTransmissionWarnings_TCU_R932_1_Drive_to_stop (6) +#endif + +#ifndef stTransmissionWarnings_TCU_R932_1_Limited_functionality +#define stTransmissionWarnings_TCU_R932_1_Limited_functionality (5) +#endif + +#ifndef stTransmissionWarnings_TCU_R932_1_No_failures +#define stTransmissionWarnings_TCU_R932_1_No_failures (4) +#endif + +#ifndef stTransmissionWarnings_TCU_R932_1_Critical_Failure +#define stTransmissionWarnings_TCU_R932_1_Critical_Failure (3) +#endif + +#ifndef stTransmissionWarnings_TCU_R932_1_Reserved +#define stTransmissionWarnings_TCU_R932_1_Reserved (2) +#endif + +#ifndef stTransmissionWarnings_TCU_R932_1_Overheat +#define stTransmissionWarnings_TCU_R932_1_Overheat (1) +#endif + +#ifndef stTransmissionWarnings_TCU_R932_1_Reserved +#define stTransmissionWarnings_TCU_R932_1_Reserved (0) +#endif + + +// Value tables for @bShiftInProgress signal + +#ifndef bShiftInProgress_TCU_R932_1_Shift_in_progress +#define bShiftInProgress_TCU_R932_1_Shift_in_progress (1) +#endif + +#ifndef bShiftInProgress_TCU_R932_1_Not_shifting +#define bShiftInProgress_TCU_R932_1_Not_shifting (0) +#endif + + +// Value tables for @TCU_VehicleSpeed_ValueError signal + +#ifndef TCU_VehicleSpeed_ValueError_TCU_R932_1_Invalid_value_in_vehicle_speed_signal +#define TCU_VehicleSpeed_ValueError_TCU_R932_1_Invalid_value_in_vehicle_speed_signal (1) +#endif + +#ifndef TCU_VehicleSpeed_ValueError_TCU_R932_1_Valid_value_in_vehicle_speed_signal +#define TCU_VehicleSpeed_ValueError_TCU_R932_1_Valid_value_in_vehicle_speed_signal (0) +#endif + + +// Value tables for @stManualGbxMode signal + +#ifndef stManualGbxMode_TCU_R932_1_Manual +#define stManualGbxMode_TCU_R932_1_Manual (1) +#endif + +#ifndef stManualGbxMode_TCU_R932_1_Auto +#define stManualGbxMode_TCU_R932_1_Auto (0) +#endif + + +// Value tables for @TCU_DriverBrakeReq signal + +#ifndef TCU_DriverBrakeReq_TCU_R932_1_Brake_pedal_requested +#define TCU_DriverBrakeReq_TCU_R932_1_Brake_pedal_requested (1) +#endif + +#ifndef TCU_DriverBrakeReq_TCU_R932_1_No_Request +#define TCU_DriverBrakeReq_TCU_R932_1_No_Request (0) +#endif + + +// Value tables for @gearChangeSPDphase signal + +#ifndef gearChangeSPDphase_TCU_R932_1_not_changing +#define gearChangeSPDphase_TCU_R932_1_not_changing (1) +#endif + +#ifndef gearChangeSPDphase_TCU_R932_1_changing +#define gearChangeSPDphase_TCU_R932_1_changing (0) +#endif + +// signal: @TCU_VehicleSpeed_ro +#define CANDB_TCU_VehicleSpeed_ro_CovFactor (0.01) +#define CANDB_TCU_VehicleSpeed_ro_toS(x) ( (uint16_t) (((x) - (0.0)) / (0.01)) ) +#define CANDB_TCU_VehicleSpeed_ro_fromS(x) ( (((x) * (0.01)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Gear target + // 15 : "Default" + // 14 : "Unavailable" + // 13 : "Undefined" + // 12 : "Undefined" + // 11 : "Undefined" + // 10 : "Reverse" + // 9 : "Ninth gear" + // 8 : "Eight gear" + // 7 : "Seventh gear" + // 6 : "Sixth gear" + // 5 : "Fifth gear" + // 4 : "Fourth gear" + // 3 : "Third gear" + // 2 : "Second gear" + // 1 : "First gear" + // 0 : "Neutral" + uint8_t numGearTarget : 4; // Bits= 4 + + // Actual gear + // 15 : "Default" + // 14 : "Unavailable" + // 13 : "Undefined" + // 12 : "Undefined" + // 11 : "Undefined" + // 10 : "Reverse" + // 9 : "Ninth gear" + // 8 : "Eight gear" + // 7 : "Seventh gear" + // 6 : "Sixth gear" + // 5 : "Fifth gear" + // 4 : "Fourth gear" + // 3 : "Third gear" + // 2 : "Second gear" + // 1 : "First gear" + // 0 : "Neutral" + uint8_t numGearEngaged : 4; // Bits= 4 + + // Engine to gearbox out torque ratio (without differential) + uint16_t ratEng2GbxTorqueRatio_ro; // Bits=11 Factor= 0.01 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t ratEng2GbxTorqueRatio_phys; +#endif // CANDB_USE_SIGFLOAT + + // Signal gear lever (PRND) position for HEV + // 7 : "Default" + // 6 : "Not available" + // 5 : "undefined" + // 4 : "D" + // 3 : "N" + // 2 : "R" + // 1 : "P" + // 0 : "Error" + uint8_t stGearLvr : 3; // Bits= 3 + + // TCU MIL lamp + // 3 : "Default" + // 2 : "Not Available" + // 1 : "MIL ON" + // 0 : "MIL OFF" + uint8_t stGbxMILReq : 2; // Bits= 2 + + // Gearbox mode, Driving mode settings in TCU + // 7 : "Default" + // 6 : "Not available" + // 5 : "Undefined" + // 4 : "All Season" + // 3 : "Auto" + // 2 : "Comfort" + // 1 : "Sport" + // 0 : "Error" + uint8_t stGearboxMode : 3; // Bits= 3 + + // TCU MIL lamp + // 15 : "Default" + // 14 : "Not available" + // 13 : "Undefined" + // 12 : "Undefined" + // 11 : "Undefined" + // 10 : "Undefined" + // 9 : "Undefined" + // 8 : "Undefined" + // 7 : "Undefined" + // 6 : "Drive to stop" + // 5 : "Limited functionality" + // 4 : "No failures" + // 3 : "Critical Failure" + // 2 : "Reserved" + // 1 : "Overheat" + // 0 : "Reserved" + uint8_t stTransmissionWarnings : 4; // Bits= 4 + + // Shift is in progress + // 1 : "Shift in progress" + // 0 : "Not shifting" + uint8_t bShiftInProgress : 1; // Bits= 1 + + // Indicates if the signal vehicleSpeed has valid value + // 1 : "Invalid value in vehicle speed signal" + // 0 : "Valid value in vehicle speed signal" + uint8_t TCU_VehicleSpeed_ValueError : 1; // Bits= 1 + + // Manual gear shift mode + // 1 : "Manual" + // 0 : "Auto" + uint8_t stManualGbxMode : 1; // Bits= 1 + + // Indicates a request to the user for pressing the brake pedal: + // $0 = No request + // $1 = Brake pedal requested + // 1 : "Brake pedal requested" + // 0 : "No Request" + uint8_t TCU_DriverBrakeReq : 1; // Bits= 1 + + // Speed ratio changing stage of gearshift + // 1 : "not changing" + // 0 : "changing" + uint8_t gearChangeSPDphase : 1; // Bits= 1 + + // calculated vehicle speed value + uint16_t TCU_VehicleSpeed_ro; // Bits=16 Factor= 0.01 Unit:'km/h' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t TCU_VehicleSpeed_phys; +#endif // CANDB_USE_SIGFLOAT + + // Rolling Counter [0 - 15] + uint8_t TCU_R932_1_RC : 4; // Bits= 4 + + // Checksum XOR8 of the data field this message + // Checksum computed as per XOR algorithm: + // Byte 1 XOR byte 2 .... XOR byte n-1. (n = packet length.) + uint8_t TCU_R932_1_CS; // Bits= 8 + +#else + + // Gear target + // 15 : "Default" + // 14 : "Unavailable" + // 13 : "Undefined" + // 12 : "Undefined" + // 11 : "Undefined" + // 10 : "Reverse" + // 9 : "Ninth gear" + // 8 : "Eight gear" + // 7 : "Seventh gear" + // 6 : "Sixth gear" + // 5 : "Fifth gear" + // 4 : "Fourth gear" + // 3 : "Third gear" + // 2 : "Second gear" + // 1 : "First gear" + // 0 : "Neutral" + uint8_t numGearTarget; // Bits= 4 + + // Actual gear + // 15 : "Default" + // 14 : "Unavailable" + // 13 : "Undefined" + // 12 : "Undefined" + // 11 : "Undefined" + // 10 : "Reverse" + // 9 : "Ninth gear" + // 8 : "Eight gear" + // 7 : "Seventh gear" + // 6 : "Sixth gear" + // 5 : "Fifth gear" + // 4 : "Fourth gear" + // 3 : "Third gear" + // 2 : "Second gear" + // 1 : "First gear" + // 0 : "Neutral" + uint8_t numGearEngaged; // Bits= 4 + + // Engine to gearbox out torque ratio (without differential) + uint16_t ratEng2GbxTorqueRatio_ro; // Bits=11 Factor= 0.01 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t ratEng2GbxTorqueRatio_phys; +#endif // CANDB_USE_SIGFLOAT + + // Signal gear lever (PRND) position for HEV + // 7 : "Default" + // 6 : "Not available" + // 5 : "undefined" + // 4 : "D" + // 3 : "N" + // 2 : "R" + // 1 : "P" + // 0 : "Error" + uint8_t stGearLvr; // Bits= 3 + + // TCU MIL lamp + // 3 : "Default" + // 2 : "Not Available" + // 1 : "MIL ON" + // 0 : "MIL OFF" + uint8_t stGbxMILReq; // Bits= 2 + + // Gearbox mode, Driving mode settings in TCU + // 7 : "Default" + // 6 : "Not available" + // 5 : "Undefined" + // 4 : "All Season" + // 3 : "Auto" + // 2 : "Comfort" + // 1 : "Sport" + // 0 : "Error" + uint8_t stGearboxMode; // Bits= 3 + + // TCU MIL lamp + // 15 : "Default" + // 14 : "Not available" + // 13 : "Undefined" + // 12 : "Undefined" + // 11 : "Undefined" + // 10 : "Undefined" + // 9 : "Undefined" + // 8 : "Undefined" + // 7 : "Undefined" + // 6 : "Drive to stop" + // 5 : "Limited functionality" + // 4 : "No failures" + // 3 : "Critical Failure" + // 2 : "Reserved" + // 1 : "Overheat" + // 0 : "Reserved" + uint8_t stTransmissionWarnings; // Bits= 4 + + // Shift is in progress + // 1 : "Shift in progress" + // 0 : "Not shifting" + uint8_t bShiftInProgress; // Bits= 1 + + // Indicates if the signal vehicleSpeed has valid value + // 1 : "Invalid value in vehicle speed signal" + // 0 : "Valid value in vehicle speed signal" + uint8_t TCU_VehicleSpeed_ValueError; // Bits= 1 + + // Manual gear shift mode + // 1 : "Manual" + // 0 : "Auto" + uint8_t stManualGbxMode; // Bits= 1 + + // Indicates a request to the user for pressing the brake pedal: + // $0 = No request + // $1 = Brake pedal requested + // 1 : "Brake pedal requested" + // 0 : "No Request" + uint8_t TCU_DriverBrakeReq; // Bits= 1 + + // Speed ratio changing stage of gearshift + // 1 : "not changing" + // 0 : "changing" + uint8_t gearChangeSPDphase; // Bits= 1 + + // calculated vehicle speed value + uint16_t TCU_VehicleSpeed_ro; // Bits=16 Factor= 0.01 Unit:'km/h' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t TCU_VehicleSpeed_phys; +#endif // CANDB_USE_SIGFLOAT + + // Rolling Counter [0 - 15] + uint8_t TCU_R932_1_RC; // Bits= 4 + + // Checksum XOR8 of the data field this message + // Checksum computed as per XOR algorithm: + // Byte 1 XOR byte 2 .... XOR byte n-1. (n = packet length.) + uint8_t TCU_R932_1_CS; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} TCU_R932_1_t; + +// def @VAU2_INVF_Hash_Resp CAN Message (191 0xbf) +#define VAU2_INVF_Hash_Resp_IDE (0U) +#define VAU2_INVF_Hash_Resp_DLC (8U) +#define VAU2_INVF_Hash_Resp_CANID (0xbfU) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Response to authorization request to start movement VAU->INV1 + uint64_t VAU2_INVF_Hash_Resp; // Bits=64 + +#else + + // Response to authorization request to start movement VAU->INV1 + uint64_t VAU2_INVF_Hash_Resp; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} VAU2_INVF_Hash_Resp_t; + +// def @FTCU_DAT1 CAN Message (227 0xe3) +#define FTCU_DAT1_IDE (0U) +#define FTCU_DAT1_DLC (8U) +#define FTCU_DAT1_CANID (0xe3U) +#define FTCU_DAT1_CYC (10U) +// signal: @FTCU_MeasuredCurrentPump1_Val_ro +#define CANDB_FTCU_MeasuredCurrentPump1_Val_ro_CovFactor (0.1) +#define CANDB_FTCU_MeasuredCurrentPump1_Val_ro_toS(x) ( (uint16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_FTCU_MeasuredCurrentPump1_Val_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @FTCU_MeasuredCurrentPump2_Val_ro +#define CANDB_FTCU_MeasuredCurrentPump2_Val_ro_CovFactor (0.1) +#define CANDB_FTCU_MeasuredCurrentPump2_Val_ro_toS(x) ( (uint16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_FTCU_MeasuredCurrentPump2_Val_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @FTCU_EmtrPWMPump1_Val_ro +#define CANDB_FTCU_EmtrPWMPump1_Val_ro_CovFactor (0.1) +#define CANDB_FTCU_EmtrPWMPump1_Val_ro_toS(x) ( (uint16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_FTCU_EmtrPWMPump1_Val_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @FTCU_EmtrPWMPump2_Val_ro +#define CANDB_FTCU_EmtrPWMPump2_Val_ro_CovFactor (0.1) +#define CANDB_FTCU_EmtrPWMPump2_Val_ro_toS(x) ( (uint16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_FTCU_EmtrPWMPump2_Val_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Actual current of the FuelPump 1 + uint16_t FTCU_MeasuredCurrentPump1_Val_ro; // Bits=10 Factor= 0.1 Unit:'A' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t FTCU_MeasuredCurrentPump1_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Actual current of the FuelPump 2 + uint16_t FTCU_MeasuredCurrentPump2_Val_ro; // Bits=10 Factor= 0.1 Unit:'A' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t FTCU_MeasuredCurrentPump2_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Actual PWM of the FuelPump 1 + uint16_t FTCU_EmtrPWMPump1_Val_ro; // Bits=10 Factor= 0.1 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t FTCU_EmtrPWMPump1_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Actual PWM of the FuelPump 2 + uint16_t FTCU_EmtrPWMPump2_Val_ro; // Bits=10 Factor= 0.1 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t FTCU_EmtrPWMPump2_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#else + + // Actual current of the FuelPump 1 + uint16_t FTCU_MeasuredCurrentPump1_Val_ro; // Bits=10 Factor= 0.1 Unit:'A' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t FTCU_MeasuredCurrentPump1_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Actual current of the FuelPump 2 + uint16_t FTCU_MeasuredCurrentPump2_Val_ro; // Bits=10 Factor= 0.1 Unit:'A' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t FTCU_MeasuredCurrentPump2_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Actual PWM of the FuelPump 1 + uint16_t FTCU_EmtrPWMPump1_Val_ro; // Bits=10 Factor= 0.1 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t FTCU_EmtrPWMPump1_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Actual PWM of the FuelPump 2 + uint16_t FTCU_EmtrPWMPump2_Val_ro; // Bits=10 Factor= 0.1 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t FTCU_EmtrPWMPump2_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} FTCU_DAT1_t; + +// def @FTCU_DAT2 CAN Message (228 0xe4) +#define FTCU_DAT2_IDE (0U) +#define FTCU_DAT2_DLC (8U) +#define FTCU_DAT2_CANID (0xe4U) +#define FTCU_DAT2_CYC (10U) + +// Value tables for @FTCU_Err_Stat signal + +#ifndef FTCU_Err_Stat_FTCU_DAT2_nd_exhaust_actuator_error +#define FTCU_Err_Stat_FTCU_DAT2_nd_exhaust_actuator_error (4) +#endif + +#ifndef FTCU_Err_Stat_FTCU_DAT2_st_exhaust_actuator_error +#define FTCU_Err_Stat_FTCU_DAT2_st_exhaust_actuator_error (3) +#endif + +#ifndef FTCU_Err_Stat_FTCU_DAT2_Red_Error_No_start +#define FTCU_Err_Stat_FTCU_DAT2_Red_Error_No_start (2) +#endif + +#ifndef FTCU_Err_Stat_FTCU_DAT2_Warning_check_engine +#define FTCU_Err_Stat_FTCU_DAT2_Warning_check_engine (1) +#endif + +#ifndef FTCU_Err_Stat_FTCU_DAT2_Init +#define FTCU_Err_Stat_FTCU_DAT2_Init (0) +#endif + + +// Value tables for @FTCU_FuelPumpOK_1_Stat signal + +#ifndef FTCU_FuelPumpOK_1_Stat_FTCU_DAT2_Init_value +#define FTCU_FuelPumpOK_1_Stat_FTCU_DAT2_Init_value (2) +#endif + +#ifndef FTCU_FuelPumpOK_1_Stat_FTCU_DAT2_Fuel_pump_is_operable +#define FTCU_FuelPumpOK_1_Stat_FTCU_DAT2_Fuel_pump_is_operable (1) +#endif + +#ifndef FTCU_FuelPumpOK_1_Stat_FTCU_DAT2_Fuel_pump_not_operable +#define FTCU_FuelPumpOK_1_Stat_FTCU_DAT2_Fuel_pump_not_operable (0) +#endif + + +// Value tables for @FTCU_FuelPumpOK_2_Stat signal + +#ifndef FTCU_FuelPumpOK_2_Stat_FTCU_DAT2_Init_value +#define FTCU_FuelPumpOK_2_Stat_FTCU_DAT2_Init_value (2) +#endif + +#ifndef FTCU_FuelPumpOK_2_Stat_FTCU_DAT2_Fuel_pump_is_operable +#define FTCU_FuelPumpOK_2_Stat_FTCU_DAT2_Fuel_pump_is_operable (1) +#endif + +#ifndef FTCU_FuelPumpOK_2_Stat_FTCU_DAT2_Fuel_pump_not_operable +#define FTCU_FuelPumpOK_2_Stat_FTCU_DAT2_Fuel_pump_not_operable (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Low circuit fuel pressure (measured) + uint16_t FTCU_FuelPressure_Val; // Bits=10 Unit:'kPa' + + // Error status + // 4 : "2nd exhaust actuator error" + // 3 : "1st exhaust actuator error" + // 2 : "Red Error (No start)" + // 1 : "Warning (check engine)" + // 0 : "Init" + uint8_t FTCU_Err_Stat : 5; // Bits= 5 + + // Actual state of the FuelPump 1 + // 2 : "Init value" + // 1 : "Fuel pump is operable" + // 0 : "Fuel pump not operable" + uint8_t FTCU_FuelPumpOK_1_Stat : 2; // Bits= 2 + + // Actual state of the FuelPump 2 + // 2 : "Init value" + // 1 : "Fuel pump is operable" + // 0 : "Fuel pump not operable" + uint8_t FTCU_FuelPumpOK_2_Stat : 2; // Bits= 2 + + // Actual state of the FTCU + uint8_t FTCU_St_Val; // Bits= 8 + +#else + + // Low circuit fuel pressure (measured) + uint16_t FTCU_FuelPressure_Val; // Bits=10 Unit:'kPa' + + // Error status + // 4 : "2nd exhaust actuator error" + // 3 : "1st exhaust actuator error" + // 2 : "Red Error (No start)" + // 1 : "Warning (check engine)" + // 0 : "Init" + uint8_t FTCU_Err_Stat; // Bits= 5 + + // Actual state of the FuelPump 1 + // 2 : "Init value" + // 1 : "Fuel pump is operable" + // 0 : "Fuel pump not operable" + uint8_t FTCU_FuelPumpOK_1_Stat; // Bits= 2 + + // Actual state of the FuelPump 2 + // 2 : "Init value" + // 1 : "Fuel pump is operable" + // 0 : "Fuel pump not operable" + uint8_t FTCU_FuelPumpOK_2_Stat; // Bits= 2 + + // Actual state of the FTCU + uint8_t FTCU_St_Val; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} FTCU_DAT2_t; + +// def @FTCU_DAT3 CAN Message (229 0xe5) +#define FTCU_DAT3_IDE (0U) +#define FTCU_DAT3_DLC (8U) +#define FTCU_DAT3_CANID (0xe5U) +#define FTCU_DAT3_CYC (10U) +// signal: @FTCU_Ubat_Val_ro +#define CANDB_FTCU_Ubat_Val_ro_CovFactor (0.01) +#define CANDB_FTCU_Ubat_Val_ro_toS(x) ( (uint16_t) (((x) - (0.0)) / (0.01)) ) +#define CANDB_FTCU_Ubat_Val_ro_fromS(x) ( (((x) * (0.01)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Actual CPU temperature of the FTCU + int16_t FTCU_CPUTemperature_Val; // [-] Bits=10 Unit:'�C' + + // Actual voltage of the FTCU + uint16_t FTCU_Ubat_Val_ro; // Bits=11 Factor= 0.01 Unit:'V' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t FTCU_Ubat_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Low circuit fuel pressure (estimated) + uint16_t FTCU_DesiredPressure_Val; // Bits=10 Unit:'kPa' + + // Instantaneous fuel consumption inmilliliter/second + uint8_t FTCU_FuelConsumption_Val; // Bits= 8 Unit:'ml/s' + +#else + + // Actual CPU temperature of the FTCU + int16_t FTCU_CPUTemperature_Val; // [-] Bits=10 Unit:'�C' + + // Actual voltage of the FTCU + uint16_t FTCU_Ubat_Val_ro; // Bits=11 Factor= 0.01 Unit:'V' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t FTCU_Ubat_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Low circuit fuel pressure (estimated) + uint16_t FTCU_DesiredPressure_Val; // Bits=10 Unit:'kPa' + + // Instantaneous fuel consumption inmilliliter/second + uint8_t FTCU_FuelConsumption_Val; // Bits= 8 Unit:'ml/s' + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} FTCU_DAT3_t; + +// def @SCU_02 CAN Message (242 0xf2) +#define SCU_02_IDE (0U) +#define SCU_02_DLC (6U) +#define SCU_02_CANID (0xf2U) +#define SCU_02_CYC (100U) +// signal: @SCU_LeftFrHeight_ro +#define CANDB_SCU_LeftFrHeight_ro_CovFactor (1) +#define CANDB_SCU_LeftFrHeight_ro_toS(x) ( (uint8_t) ((x) - (80)) ) +#define CANDB_SCU_LeftFrHeight_ro_fromS(x) ( ((x) + (80)) ) +// signal: @SCU_RightFrHeight_ro +#define CANDB_SCU_RightFrHeight_ro_CovFactor (1) +#define CANDB_SCU_RightFrHeight_ro_toS(x) ( (uint8_t) ((x) - (80)) ) +#define CANDB_SCU_RightFrHeight_ro_fromS(x) ( ((x) + (80)) ) +// signal: @SCU_LeftRearHeight_ro +#define CANDB_SCU_LeftRearHeight_ro_CovFactor (1) +#define CANDB_SCU_LeftRearHeight_ro_toS(x) ( (uint8_t) ((x) - (80)) ) +#define CANDB_SCU_LeftRearHeight_ro_fromS(x) ( ((x) + (80)) ) +// signal: @SCU_RightRearHeight_ro +#define CANDB_SCU_RightRearHeight_ro_CovFactor (1) +#define CANDB_SCU_RightRearHeight_ro_toS(x) ( (uint8_t) ((x) - (80)) ) +#define CANDB_SCU_RightRearHeight_ro_fromS(x) ( ((x) + (80)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Left Front height (physical count value for height sensor pulse width) + // The range of the pulse width count value is 80-334. + // 80 is min pulse width reflecting the lowest limitation of wheel rebound. + // 334 is max pulse width reflecting the highest limitation + uint8_t SCU_LeftFrHeight_ro; // Bits= 8 Offset= 80 + +#ifdef CANDB_USE_SIGFLOAT + uint16_t SCU_LeftFrHeight_phys; +#endif // CANDB_USE_SIGFLOAT + + // Right Front height (physical count value for height sensor pulse width) + // The range of the pulse width count value is 80-334. + // 80 is min pulse width reflecting the lowest limitation of wheel rebound. + // 334 is max pulse width reflecting the highest limitatio + uint8_t SCU_RightFrHeight_ro; // Bits= 8 Offset= 80 + +#ifdef CANDB_USE_SIGFLOAT + uint16_t SCU_RightFrHeight_phys; +#endif // CANDB_USE_SIGFLOAT + + // Left Rear height (physical count value for height sensor pulse width) + // The range of the pulse width count value is 80-334. + // 80 is min pulse width reflecting the lowest limitation of wheel rebound. + // 334 is max pulse width reflecting the highest limitation + uint8_t SCU_LeftRearHeight_ro; // Bits= 8 Offset= 80 + +#ifdef CANDB_USE_SIGFLOAT + uint16_t SCU_LeftRearHeight_phys; +#endif // CANDB_USE_SIGFLOAT + + // Right Rear height (physical count value for height sensor pulse width) + // The range of the pulse width count value is 80-334. + // 80 is min pulse width reflecting the lowest limitation of wheel rebound. + // 334 is max pulse width reflecting the highest limitation + uint8_t SCU_RightRearHeight_ro; // Bits= 8 Offset= 80 + +#ifdef CANDB_USE_SIGFLOAT + uint16_t SCU_RightRearHeight_phys; +#endif // CANDB_USE_SIGFLOAT + + // Rolling Counter [0 - 15] + uint8_t SCU_02_RC : 4; // Bits= 4 + + // Checksum XOR8 of the data field this message + // Checksum computed as per XOR algorithm: + // Byte 1 XOR byte 2 .... XOR byte n-1. (n = packet length.) + uint8_t SCU_02_CS; // Bits= 8 + +#else + + // Left Front height (physical count value for height sensor pulse width) + // The range of the pulse width count value is 80-334. + // 80 is min pulse width reflecting the lowest limitation of wheel rebound. + // 334 is max pulse width reflecting the highest limitation + uint8_t SCU_LeftFrHeight_ro; // Bits= 8 Offset= 80 + +#ifdef CANDB_USE_SIGFLOAT + uint16_t SCU_LeftFrHeight_phys; +#endif // CANDB_USE_SIGFLOAT + + // Right Front height (physical count value for height sensor pulse width) + // The range of the pulse width count value is 80-334. + // 80 is min pulse width reflecting the lowest limitation of wheel rebound. + // 334 is max pulse width reflecting the highest limitatio + uint8_t SCU_RightFrHeight_ro; // Bits= 8 Offset= 80 + +#ifdef CANDB_USE_SIGFLOAT + uint16_t SCU_RightFrHeight_phys; +#endif // CANDB_USE_SIGFLOAT + + // Left Rear height (physical count value for height sensor pulse width) + // The range of the pulse width count value is 80-334. + // 80 is min pulse width reflecting the lowest limitation of wheel rebound. + // 334 is max pulse width reflecting the highest limitation + uint8_t SCU_LeftRearHeight_ro; // Bits= 8 Offset= 80 + +#ifdef CANDB_USE_SIGFLOAT + uint16_t SCU_LeftRearHeight_phys; +#endif // CANDB_USE_SIGFLOAT + + // Right Rear height (physical count value for height sensor pulse width) + // The range of the pulse width count value is 80-334. + // 80 is min pulse width reflecting the lowest limitation of wheel rebound. + // 334 is max pulse width reflecting the highest limitation + uint8_t SCU_RightRearHeight_ro; // Bits= 8 Offset= 80 + +#ifdef CANDB_USE_SIGFLOAT + uint16_t SCU_RightRearHeight_phys; +#endif // CANDB_USE_SIGFLOAT + + // Rolling Counter [0 - 15] + uint8_t SCU_02_RC; // Bits= 4 + + // Checksum XOR8 of the data field this message + // Checksum computed as per XOR algorithm: + // Byte 1 XOR byte 2 .... XOR byte n-1. (n = packet length.) + uint8_t SCU_02_CS; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} SCU_02_t; + +// def @ESC_04 CAN Message (256 0x100) +#define ESC_04_IDE (0U) +#define ESC_04_DLC (8U) +#define ESC_04_CANID (0x100U) +#define ESC_04_CYC (20U) +// signal: @ESC_VehicleSpeed_ro +#define CANDB_ESC_VehicleSpeed_ro_CovFactor (0.01) +#define CANDB_ESC_VehicleSpeed_ro_toS(x) ( (uint16_t) (((x) - (0.0)) / (0.01)) ) +#define CANDB_ESC_VehicleSpeed_ro_fromS(x) ( (((x) * (0.01)) + (0.0)) ) + +// Value tables for @ESC_VehicleSpeed_ValueError signal + +#ifndef ESC_VehicleSpeed_ValueError_ESC_04_Invalid_value_in_vehicle_speed_signal +#define ESC_VehicleSpeed_ValueError_ESC_04_Invalid_value_in_vehicle_speed_signal (1) +#endif + +#ifndef ESC_VehicleSpeed_ValueError_ESC_04_Valid_value_in_vehicle_speed_signal +#define ESC_VehicleSpeed_ValueError_ESC_04_Valid_value_in_vehicle_speed_signal (0) +#endif + + +// Value tables for @ESC_Lamp signal + +#ifndef ESC_Lamp_ESC_04_ESC_Fault +#define ESC_Lamp_ESC_04_ESC_Fault (1) +#endif + +#ifndef ESC_Lamp_ESC_04_No_Faults +#define ESC_Lamp_ESC_04_No_Faults (0) +#endif + + +// Value tables for @ESC_AVH_Active signal + +#ifndef ESC_AVH_Active_ESC_04_Active +#define ESC_AVH_Active_ESC_04_Active (1) +#endif + +#ifndef ESC_AVH_Active_ESC_04_Not_Active +#define ESC_AVH_Active_ESC_04_Not_Active (0) +#endif + + +// Value tables for @ESC_Bls_Out signal + +#ifndef ESC_Bls_Out_ESC_04_BLS_active_or_pressed +#define ESC_Bls_Out_ESC_04_BLS_active_or_pressed (1) +#endif + +#ifndef ESC_Bls_Out_ESC_04_BLS_inactive_or_not_pressed +#define ESC_Bls_Out_ESC_04_BLS_inactive_or_not_pressed (0) +#endif + + +// Value tables for @ESC_Bla signal + +#ifndef ESC_Bla_ESC_04_Brake_lights_off +#define ESC_Bla_ESC_04_Brake_lights_off (0) +#endif + +#ifndef ESC_Bla_ESC_04_Activate_brake_lights +#define ESC_Bla_ESC_04_Activate_brake_lights (1) +#endif + + +// Value tables for @ESC_ABS_Lamp signal + +#ifndef ESC_ABS_Lamp_ESC_04_ABS_Fault +#define ESC_ABS_Lamp_ESC_04_ABS_Fault (1) +#endif + +#ifndef ESC_ABS_Lamp_ESC_04_No_Faults +#define ESC_ABS_Lamp_ESC_04_No_Faults (0) +#endif + + +// Value tables for @ESC_EBD_Lamp signal + +#ifndef ESC_EBD_Lamp_ESC_04_EBD_Fault +#define ESC_EBD_Lamp_ESC_04_EBD_Fault (1) +#endif + +#ifndef ESC_EBD_Lamp_ESC_04_No_faults +#define ESC_EBD_Lamp_ESC_04_No_faults (0) +#endif + + +// Value tables for @ESC_TCS_Fault signal + +#ifndef ESC_TCS_Fault_ESC_04_TCS_Fault +#define ESC_TCS_Fault_ESC_04_TCS_Fault (1) +#endif + +#ifndef ESC_TCS_Fault_ESC_04_No_faults +#define ESC_TCS_Fault_ESC_04_No_faults (0) +#endif + + +// Value tables for @ESC_CDPDecelActive signal + +#ifndef ESC_CDPDecelActive_ESC_04_Active +#define ESC_CDPDecelActive_ESC_04_Active (1) +#endif + +#ifndef ESC_CDPDecelActive_ESC_04_Not_Active +#define ESC_CDPDecelActive_ESC_04_Not_Active (0) +#endif + + +// Value tables for @ESC_BLS_Fault signal + +#ifndef ESC_BLS_Fault_ESC_04_BLS_Faulty +#define ESC_BLS_Fault_ESC_04_BLS_Faulty (1) +#endif + +#ifndef ESC_BLS_Fault_ESC_04_BLS_not_faulty +#define ESC_BLS_Fault_ESC_04_BLS_not_faulty (0) +#endif + + +// Value tables for @ESC_CtlActiveAbs signal + +#ifndef ESC_CtlActiveAbs_ESC_04_ABS_control_active +#define ESC_CtlActiveAbs_ESC_04_ABS_control_active (1) +#endif + +#ifndef ESC_CtlActiveAbs_ESC_04_ABS_control_not_active +#define ESC_CtlActiveAbs_ESC_04_ABS_control_not_active (0) +#endif + + +// Value tables for @ESC_CtlActiveEbd signal + +#ifndef ESC_CtlActiveEbd_ESC_04_EBD_control_active +#define ESC_CtlActiveEbd_ESC_04_EBD_control_active (1) +#endif + +#ifndef ESC_CtlActiveEbd_ESC_04_EBD_control_not_active +#define ESC_CtlActiveEbd_ESC_04_EBD_control_not_active (0) +#endif + + +// Value tables for @ESC_CtlActiveTcs signal + +#ifndef ESC_CtlActiveTcs_ESC_04_TCS_control_active +#define ESC_CtlActiveTcs_ESC_04_TCS_control_active (1) +#endif + +#ifndef ESC_CtlActiveTcs_ESC_04_TCS_control_not_active +#define ESC_CtlActiveTcs_ESC_04_TCS_control_not_active (0) +#endif + + +// Value tables for @ESC_CtlActiveVdc signal + +#ifndef ESC_CtlActiveVdc_ESC_04_VDC_control_currently_active +#define ESC_CtlActiveVdc_ESC_04_VDC_control_currently_active (1) +#endif + +#ifndef ESC_CtlActiveVdc_ESC_04_VDC_control_not_active +#define ESC_CtlActiveVdc_ESC_04_VDC_control_not_active (0) +#endif + + +// Value tables for @ESC_Passive_Lamp signal + +#ifndef ESC_Passive_Lamp_ESC_04_Passive_lamp_ON +#define ESC_Passive_Lamp_ESC_04_Passive_lamp_ON (1) +#endif + +#ifndef ESC_Passive_Lamp_ESC_04_Passive_lamp_OFF +#define ESC_Passive_Lamp_ESC_04_Passive_lamp_OFF (0) +#endif + + +// Value tables for @ESC_Gearshift_Inhibit signal + +#ifndef ESC_Gearshift_Inhibit_ESC_04_Allow_gear_shifting +#define ESC_Gearshift_Inhibit_ESC_04_Allow_gear_shifting (0) +#endif + +#ifndef ESC_Gearshift_Inhibit_ESC_04_Inhibit_gear_shift +#define ESC_Gearshift_Inhibit_ESC_04_Inhibit_gear_shift (1) +#endif + + +// Value tables for @ESC_HDC_Activated signal + +#ifndef ESC_HDC_Activated_ESC_04_HDC_function_has_been_activated_by_driver +#define ESC_HDC_Activated_ESC_04_HDC_function_has_been_activated_by_driver (1) +#endif + +#ifndef ESC_HDC_Activated_ESC_04_HDC_function_in_inactive_state +#define ESC_HDC_Activated_ESC_04_HDC_function_in_inactive_state (0) +#endif + + +// Value tables for @ESC_CtlActiveHDC signal + +#ifndef ESC_CtlActiveHDC_ESC_04_HDC_control_active_currently +#define ESC_CtlActiveHDC_ESC_04_HDC_control_active_currently (1) +#endif + +#ifndef ESC_CtlActiveHDC_ESC_04_HDC_control_not_active +#define ESC_CtlActiveHDC_ESC_04_HDC_control_not_active (0) +#endif + + +// Value tables for @ESC_HDC_rejected signal + +#ifndef ESC_HDC_rejected_ESC_04_HDC_cannot_be_activated_in_current_driving_mode +#define ESC_HDC_rejected_ESC_04_HDC_cannot_be_activated_in_current_driving_mode (1) +#endif + +#ifndef ESC_HDC_rejected_ESC_04_HDC_can_be_activated +#define ESC_HDC_rejected_ESC_04_HDC_can_be_activated (0) +#endif + + +// Value tables for @ESC_EmergencyBraking signal + +#ifndef ESC_EmergencyBraking_ESC_04_Emergency_braking +#define ESC_EmergencyBraking_ESC_04_Emergency_braking (1) +#endif + +#ifndef ESC_EmergencyBraking_ESC_04_No_emergency_braking +#define ESC_EmergencyBraking_ESC_04_No_emergency_braking (0) +#endif + + +// Value tables for @ESC_RequestToEPB signal + +#ifndef ESC_RequestToEPB_ESC_04_Lock_Brake +#define ESC_RequestToEPB_ESC_04_Lock_Brake (3) +#endif + +#ifndef ESC_RequestToEPB_ESC_04_Release_Brake +#define ESC_RequestToEPB_ESC_04_Release_Brake (2) +#endif + +#ifndef ESC_RequestToEPB_ESC_04_No_Request +#define ESC_RequestToEPB_ESC_04_No_Request (1) +#endif + +#ifndef ESC_RequestToEPB_ESC_04_Not_Initialized +#define ESC_RequestToEPB_ESC_04_Not_Initialized (0) +#endif + + +// Value tables for @ESC_CDPDecelAvailable signal + +#ifndef ESC_CDPDecelAvailable_ESC_04_Available +#define ESC_CDPDecelAvailable_ESC_04_Available (1) +#endif + +#ifndef ESC_CDPDecelAvailable_ESC_04_Not_Available +#define ESC_CDPDecelAvailable_ESC_04_Not_Available (0) +#endif + + +// Value tables for @ESC_PEBWarningLampReq signal + +#ifndef ESC_PEBWarningLampReq_ESC_04_Warning_requested +#define ESC_PEBWarningLampReq_ESC_04_Warning_requested (1) +#endif + +#ifndef ESC_PEBWarningLampReq_ESC_04_No_Warning_requested +#define ESC_PEBWarningLampReq_ESC_04_No_Warning_requested (0) +#endif + + +// Value tables for @CddActive_2 signal + +#ifndef CddActive_2_ESC_04_Active +#define CddActive_2_ESC_04_Active (1) +#endif + +#ifndef CddActive_2_ESC_04_Inactive +#define CddActive_2_ESC_04_Inactive (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Calculated vehicle speed value + uint16_t ESC_VehicleSpeed_ro; // Bits=16 Factor= 0.01 Unit:'km/h' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t ESC_VehicleSpeed_phys; +#endif // CANDB_USE_SIGFLOAT + + // Indicates if the signal vehicleSpeed has valid value + // 1 : "Invalid value in vehicle speed signal" + // 0 : "Valid value in vehicle speed signal" + uint8_t ESC_VehicleSpeed_ValueError : 1; // Bits= 1 + + // ESC lamp control signal for HMI. + // 1 : "ESC Fault" + // 0 : "No Faults" + uint8_t ESC_Lamp : 1; // Bits= 1 + + // Feedback to EPB that indicates hydraulic holding + // $0 = Not Active + // $1 = Active + // 1 : "Active" + // 0 : "Not Active" + uint8_t ESC_AVH_Active : 1; // Bits= 1 + + // Brake Light Switch. Indicates brake pedal pressing status (derived from brake light switch and brake switch) + // 1 : "BLS active or pressed" + // 0 : "BLS inactive or not pressed" + uint8_t ESC_Bls_Out : 1; // Bits= 1 + + // Brake Light Activation. Indicates braking via driver or via other functions. + // 0 : "Brake lights off" + // 1 : "Activate brake lights" + uint8_t ESC_Bla : 1; // Bits= 1 + + // ABS lamp control signal for HMI and ABS function fault indication + // 1 : "ABS Fault" + // 0 : "No Faults" + uint8_t ESC_ABS_Lamp : 1; // Bits= 1 + + // EBD function or booster fault indication for BK-Lamp control. + // 1 : "EBD Fault" + // 0 : "No faults" + uint8_t ESC_EBD_Lamp : 1; // Bits= 1 + + // TCS function fault indication + // 1 : "TCS Fault" + // 0 : "No faults" + uint8_t ESC_TCS_Fault : 1; // Bits= 1 + + // Indicates that deceleration request from EPB is executed + // $0 = Not Active + // $1 = Active + // 1 : "Active" + // 0 : "Not Active" + uint8_t ESC_CDPDecelActive : 1; // Bits= 1 + + // Brake Light Switch fault indication. + // 1 : "BLS Faulty" + // 0 : "BLS not faulty" + uint8_t ESC_BLS_Fault : 1; // Bits= 1 + + // Indicates activity of ABS control + // 1 : "ABS control active" + // 0 : "ABS control not active" + uint8_t ESC_CtlActiveAbs : 1; // Bits= 1 + + // Indicates activity of EBD control + // 1 : "EBD control active" + // 0 : "EBD control not active" + uint8_t ESC_CtlActiveEbd : 1; // Bits= 1 + + // Indicates activity of TCS control + // 1 : "TCS control active" + // 0 : "TCS control not active" + uint8_t ESC_CtlActiveTcs : 1; // Bits= 1 + + // Indicates activity of VDC control (VDC= ESC function to stabilize the vehicle; not the differential function) + // 1 : "VDC control currently active" + // 0 : "VDC control not active" + uint8_t ESC_CtlActiveVdc : 1; // Bits= 1 + + // Control signal to HMI to control passive lamp. (degraded state of ESC CU functions) + // 1 : "Passive lamp ON" + // 0 : "Passive lamp OFF" + uint8_t ESC_Passive_Lamp : 1; // Bits= 1 + + // During critical activity in ESC control unit, request to gearbox control unit to inhibit gear shifting. + // 0 : "Allow gear shifting" + // 1 : "Inhibit gear shift" + uint8_t ESC_Gearshift_Inhibit : 1; // Bits= 1 + + // Indicates that driver has activated HDC function using the HDC switch. (not controller status) + // 1 : "HDC function has been activated by driver" + // 0 : "HDC function in inactive state" + uint8_t ESC_HDC_Activated : 1; // Bits= 1 + + // HDC controller activity indication + // 1 : "HDC control active currently" + // 0 : "HDC control not active" + uint8_t ESC_CtlActiveHDC : 1; // Bits= 1 + + // HDC activation rejected, if driver presses HDC switch in wrong driving mode. + // 1 : "HDC cannot be activated in current driving mode" + // 0 : "HDC can be activated" + uint8_t ESC_HDC_rejected : 1; // Bits= 1 + + // Emergency braking function status + // 1 : "Emergency braking" + // 0 : "No emergency braking" + uint8_t ESC_EmergencyBraking : 1; // Bits= 1 + + // ESC request to open or close the park brake + // $0 = Not Initialized + // $1 = No Request + // $2 = Release Brake + // $3 = Lock Brake + // 3 : "Lock Brake" + // 2 : "Release Brake" + // 1 : "No Request" + // 0 : "Not Initialized" + uint8_t ESC_RequestToEPB : 2; // Bits= 2 + + // Indicates that CDP is available for decelerating the vehicle + // $0 = Not Available + // $1 = Available + // 1 : "Available" + // 0 : "Not Available" + uint8_t ESC_CDPDecelAvailable : 1; // Bits= 1 + + // Activate animation in IC to inform user that the vehicle was braked in both of the following cases: + // - Automatic emergency braking activation without driver braking + // - Automatic emergency braking activation with driver brake assist + // 1 : "Warning requested" + // 0 : "No Warning requested" + uint8_t ESC_PEBWarningLampReq : 1; // Bits= 1 + + // Indicates the current speed limitation due to a Hill Descent Assist phase + uint8_t ESC_HDC_SpeedLimit; // Bits= 8 Unit:'km/h' + + // Indicates cdd control active (Controlled Deceleration for Driver Assistant Systems) + // $0 = Inactive + // $1 = Active + // (CddActive duplicata) + // 1 : "Active" + // 0 : "Inactive" + uint8_t CddActive_2 : 1; // Bits= 1 + + // Rolling Counter [0 - 15] + uint8_t ESC_04_RC : 4; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t ESC_04_CS; // Bits= 8 + +#else + + // Calculated vehicle speed value + uint16_t ESC_VehicleSpeed_ro; // Bits=16 Factor= 0.01 Unit:'km/h' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t ESC_VehicleSpeed_phys; +#endif // CANDB_USE_SIGFLOAT + + // Indicates if the signal vehicleSpeed has valid value + // 1 : "Invalid value in vehicle speed signal" + // 0 : "Valid value in vehicle speed signal" + uint8_t ESC_VehicleSpeed_ValueError; // Bits= 1 + + // ESC lamp control signal for HMI. + // 1 : "ESC Fault" + // 0 : "No Faults" + uint8_t ESC_Lamp; // Bits= 1 + + // Feedback to EPB that indicates hydraulic holding + // $0 = Not Active + // $1 = Active + // 1 : "Active" + // 0 : "Not Active" + uint8_t ESC_AVH_Active; // Bits= 1 + + // Brake Light Switch. Indicates brake pedal pressing status (derived from brake light switch and brake switch) + // 1 : "BLS active or pressed" + // 0 : "BLS inactive or not pressed" + uint8_t ESC_Bls_Out; // Bits= 1 + + // Brake Light Activation. Indicates braking via driver or via other functions. + // 0 : "Brake lights off" + // 1 : "Activate brake lights" + uint8_t ESC_Bla; // Bits= 1 + + // ABS lamp control signal for HMI and ABS function fault indication + // 1 : "ABS Fault" + // 0 : "No Faults" + uint8_t ESC_ABS_Lamp; // Bits= 1 + + // EBD function or booster fault indication for BK-Lamp control. + // 1 : "EBD Fault" + // 0 : "No faults" + uint8_t ESC_EBD_Lamp; // Bits= 1 + + // TCS function fault indication + // 1 : "TCS Fault" + // 0 : "No faults" + uint8_t ESC_TCS_Fault; // Bits= 1 + + // Indicates that deceleration request from EPB is executed + // $0 = Not Active + // $1 = Active + // 1 : "Active" + // 0 : "Not Active" + uint8_t ESC_CDPDecelActive; // Bits= 1 + + // Brake Light Switch fault indication. + // 1 : "BLS Faulty" + // 0 : "BLS not faulty" + uint8_t ESC_BLS_Fault; // Bits= 1 + + // Indicates activity of ABS control + // 1 : "ABS control active" + // 0 : "ABS control not active" + uint8_t ESC_CtlActiveAbs; // Bits= 1 + + // Indicates activity of EBD control + // 1 : "EBD control active" + // 0 : "EBD control not active" + uint8_t ESC_CtlActiveEbd; // Bits= 1 + + // Indicates activity of TCS control + // 1 : "TCS control active" + // 0 : "TCS control not active" + uint8_t ESC_CtlActiveTcs; // Bits= 1 + + // Indicates activity of VDC control (VDC= ESC function to stabilize the vehicle; not the differential function) + // 1 : "VDC control currently active" + // 0 : "VDC control not active" + uint8_t ESC_CtlActiveVdc; // Bits= 1 + + // Control signal to HMI to control passive lamp. (degraded state of ESC CU functions) + // 1 : "Passive lamp ON" + // 0 : "Passive lamp OFF" + uint8_t ESC_Passive_Lamp; // Bits= 1 + + // During critical activity in ESC control unit, request to gearbox control unit to inhibit gear shifting. + // 0 : "Allow gear shifting" + // 1 : "Inhibit gear shift" + uint8_t ESC_Gearshift_Inhibit; // Bits= 1 + + // Indicates that driver has activated HDC function using the HDC switch. (not controller status) + // 1 : "HDC function has been activated by driver" + // 0 : "HDC function in inactive state" + uint8_t ESC_HDC_Activated; // Bits= 1 + + // HDC controller activity indication + // 1 : "HDC control active currently" + // 0 : "HDC control not active" + uint8_t ESC_CtlActiveHDC; // Bits= 1 + + // HDC activation rejected, if driver presses HDC switch in wrong driving mode. + // 1 : "HDC cannot be activated in current driving mode" + // 0 : "HDC can be activated" + uint8_t ESC_HDC_rejected; // Bits= 1 + + // Emergency braking function status + // 1 : "Emergency braking" + // 0 : "No emergency braking" + uint8_t ESC_EmergencyBraking; // Bits= 1 + + // ESC request to open or close the park brake + // $0 = Not Initialized + // $1 = No Request + // $2 = Release Brake + // $3 = Lock Brake + // 3 : "Lock Brake" + // 2 : "Release Brake" + // 1 : "No Request" + // 0 : "Not Initialized" + uint8_t ESC_RequestToEPB; // Bits= 2 + + // Indicates that CDP is available for decelerating the vehicle + // $0 = Not Available + // $1 = Available + // 1 : "Available" + // 0 : "Not Available" + uint8_t ESC_CDPDecelAvailable; // Bits= 1 + + // Activate animation in IC to inform user that the vehicle was braked in both of the following cases: + // - Automatic emergency braking activation without driver braking + // - Automatic emergency braking activation with driver brake assist + // 1 : "Warning requested" + // 0 : "No Warning requested" + uint8_t ESC_PEBWarningLampReq; // Bits= 1 + + // Indicates the current speed limitation due to a Hill Descent Assist phase + uint8_t ESC_HDC_SpeedLimit; // Bits= 8 Unit:'km/h' + + // Indicates cdd control active (Controlled Deceleration for Driver Assistant Systems) + // $0 = Inactive + // $1 = Active + // (CddActive duplicata) + // 1 : "Active" + // 0 : "Inactive" + uint8_t CddActive_2; // Bits= 1 + + // Rolling Counter [0 - 15] + uint8_t ESC_04_RC; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t ESC_04_CS; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} ESC_04_t; + +// def @ESC_09 CAN Message (274 0x112) +#define ESC_09_IDE (0U) +#define ESC_09_DLC (4U) +#define ESC_09_CANID (0x112U) +#define ESC_09_CYC (20U) +// signal: @ESC_VacuumPressure_Val_ro +#define CANDB_ESC_VacuumPressure_Val_ro_CovFactor (5) +#define CANDB_ESC_VacuumPressure_Val_ro_toS(x) ( (uint8_t) (((x) - (-100)) / (5)) ) +#define CANDB_ESC_VacuumPressure_Val_ro_fromS(x) ( (((x) * (5)) + (-100)) ) +// signal: @ESC_BrakePressureMC_Val_ro +#define CANDB_ESC_BrakePressureMC_Val_ro_CovFactor (0.1) +#define CANDB_ESC_BrakePressureMC_Val_ro_toS(x) ( (uint16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_ESC_BrakePressureMC_Val_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Vacuum pressure information in brake booster front chamber + uint8_t ESC_VacuumPressure_Val_ro : 5; // Bits= 5 Offset= -100 Factor= 5 Unit:'kPa' + +#ifdef CANDB_USE_SIGFLOAT + int8_t ESC_VacuumPressure_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Reserved signal for future extension. E.g. vacuum sensor status + uint8_t ESC_VacuumSignalReserved : 2; // Bits= 2 + + // Brake pressure (estimated/measured) in the master cylinder + // 0xFFF = Error + uint16_t ESC_BrakePressureMC_Val_ro; // Bits=12 Factor= 0.1 Unit:'bar' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t ESC_BrakePressureMC_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Rolling Counter [0 - 15] + uint8_t ESC_09_RC : 4; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t ESC_09_CS; // Bits= 8 + +#else + + // Vacuum pressure information in brake booster front chamber + uint8_t ESC_VacuumPressure_Val_ro; // Bits= 5 Offset= -100 Factor= 5 Unit:'kPa' + +#ifdef CANDB_USE_SIGFLOAT + int8_t ESC_VacuumPressure_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Reserved signal for future extension. E.g. vacuum sensor status + uint8_t ESC_VacuumSignalReserved; // Bits= 2 + + // Brake pressure (estimated/measured) in the master cylinder + // 0xFFF = Error + uint16_t ESC_BrakePressureMC_Val_ro; // Bits=12 Factor= 0.1 Unit:'bar' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t ESC_BrakePressureMC_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Rolling Counter [0 - 15] + uint8_t ESC_09_RC; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t ESC_09_CS; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} ESC_09_t; + +// def @VAU2_Msg1 CAN Message (289 0x121) +#define VAU2_Msg1_IDE (0U) +#define VAU2_Msg1_DLC (3U) +#define VAU2_Msg1_CANID (0x121U) +#define VAU2_Msg1_CYC (20U) + +// Value tables for @VAU_Comm_Req signal + +#ifndef VAU_Comm_Req_VAU2_Msg1_WakeUp_Request +#define VAU_Comm_Req_VAU2_Msg1_WakeUp_Request (1) +#endif + +#ifndef VAU_Comm_Req_VAU2_Msg1_No_Request +#define VAU_Comm_Req_VAU2_Msg1_No_Request (0) +#endif + + +// Value tables for @VAU_BCM_Authentication_Resp signal + +#ifndef VAU_BCM_Authentication_Resp_VAU2_Msg1_Trunk_Close_NOK +#define VAU_BCM_Authentication_Resp_VAU2_Msg1_Trunk_Close_NOK (14) +#endif + +#ifndef VAU_BCM_Authentication_Resp_VAU2_Msg1_Trunk_Close_OK +#define VAU_BCM_Authentication_Resp_VAU2_Msg1_Trunk_Close_OK (13) +#endif + +#ifndef VAU_BCM_Authentication_Resp_VAU2_Msg1_DriveTrans_NOK +#define VAU_BCM_Authentication_Resp_VAU2_Msg1_DriveTrans_NOK (12) +#endif + +#ifndef VAU_BCM_Authentication_Resp_VAU2_Msg1_DriveTrans_OK +#define VAU_BCM_Authentication_Resp_VAU2_Msg1_DriveTrans_OK (11) +#endif + +#ifndef VAU_BCM_Authentication_Resp_VAU2_Msg1_KeyDetection_Req_NOK +#define VAU_BCM_Authentication_Resp_VAU2_Msg1_KeyDetection_Req_NOK (10) +#endif + +#ifndef VAU_BCM_Authentication_Resp_VAU2_Msg1_KeyDetection_Req_OK +#define VAU_BCM_Authentication_Resp_VAU2_Msg1_KeyDetection_Req_OK (9) +#endif + +#ifndef VAU_BCM_Authentication_Resp_VAU2_Msg1_Trunk_CloseLock_NOK +#define VAU_BCM_Authentication_Resp_VAU2_Msg1_Trunk_CloseLock_NOK (8) +#endif + +#ifndef VAU_BCM_Authentication_Resp_VAU2_Msg1_Trunk_Open_NOK +#define VAU_BCM_Authentication_Resp_VAU2_Msg1_Trunk_Open_NOK (7) +#endif + +#ifndef VAU_BCM_Authentication_Resp_VAU2_Msg1_Vehicle_Lock_Permission_NOK +#define VAU_BCM_Authentication_Resp_VAU2_Msg1_Vehicle_Lock_Permission_NOK (6) +#endif + +#ifndef VAU_BCM_Authentication_Resp_VAU2_Msg1_Transition_state_NOK +#define VAU_BCM_Authentication_Resp_VAU2_Msg1_Transition_state_NOK (5) +#endif + +#ifndef VAU_BCM_Authentication_Resp_VAU2_Msg1_Trunk_CloseLock_OK +#define VAU_BCM_Authentication_Resp_VAU2_Msg1_Trunk_CloseLock_OK (4) +#endif + +#ifndef VAU_BCM_Authentication_Resp_VAU2_Msg1_Trunk_Open_OK +#define VAU_BCM_Authentication_Resp_VAU2_Msg1_Trunk_Open_OK (3) +#endif + +#ifndef VAU_BCM_Authentication_Resp_VAU2_Msg1_Vehicle_Lock_Permission_OK +#define VAU_BCM_Authentication_Resp_VAU2_Msg1_Vehicle_Lock_Permission_OK (2) +#endif + +#ifndef VAU_BCM_Authentication_Resp_VAU2_Msg1_Transition_state_OK +#define VAU_BCM_Authentication_Resp_VAU2_Msg1_Transition_state_OK (1) +#endif + +#ifndef VAU_BCM_Authentication_Resp_VAU2_Msg1_No_response +#define VAU_BCM_Authentication_Resp_VAU2_Msg1_No_response (0) +#endif + + +// Value tables for @VAU_FL_DoorHandle_Req signal + +#ifndef VAU_FL_DoorHandle_Req_VAU2_Msg1_FL_UnlockReq_Long +#define VAU_FL_DoorHandle_Req_VAU2_Msg1_FL_UnlockReq_Long (6) +#endif + +#ifndef VAU_FL_DoorHandle_Req_VAU2_Msg1_FL_LockReq_Long +#define VAU_FL_DoorHandle_Req_VAU2_Msg1_FL_LockReq_Long (5) +#endif + +#ifndef VAU_FL_DoorHandle_Req_VAU2_Msg1_FL_UnlockReq +#define VAU_FL_DoorHandle_Req_VAU2_Msg1_FL_UnlockReq (4) +#endif + +#ifndef VAU_FL_DoorHandle_Req_VAU2_Msg1_FL_LockReq +#define VAU_FL_DoorHandle_Req_VAU2_Msg1_FL_LockReq (3) +#endif + +#ifndef VAU_FL_DoorHandle_Req_VAU2_Msg1_FL_CloseReq +#define VAU_FL_DoorHandle_Req_VAU2_Msg1_FL_CloseReq (2) +#endif + +#ifndef VAU_FL_DoorHandle_Req_VAU2_Msg1_FL_OpenReq +#define VAU_FL_DoorHandle_Req_VAU2_Msg1_FL_OpenReq (1) +#endif + +#ifndef VAU_FL_DoorHandle_Req_VAU2_Msg1_No_Request +#define VAU_FL_DoorHandle_Req_VAU2_Msg1_No_Request (0) +#endif + + +// Value tables for @VAU_FR_DoorHandle_Req signal + +#ifndef VAU_FR_DoorHandle_Req_VAU2_Msg1_FR_UnlockReq_Long +#define VAU_FR_DoorHandle_Req_VAU2_Msg1_FR_UnlockReq_Long (6) +#endif + +#ifndef VAU_FR_DoorHandle_Req_VAU2_Msg1_FR_LockReq_Long +#define VAU_FR_DoorHandle_Req_VAU2_Msg1_FR_LockReq_Long (5) +#endif + +#ifndef VAU_FR_DoorHandle_Req_VAU2_Msg1_FR_UnlockReq +#define VAU_FR_DoorHandle_Req_VAU2_Msg1_FR_UnlockReq (4) +#endif + +#ifndef VAU_FR_DoorHandle_Req_VAU2_Msg1_FR_LockReq +#define VAU_FR_DoorHandle_Req_VAU2_Msg1_FR_LockReq (3) +#endif + +#ifndef VAU_FR_DoorHandle_Req_VAU2_Msg1_FR_CloseReq +#define VAU_FR_DoorHandle_Req_VAU2_Msg1_FR_CloseReq (2) +#endif + +#ifndef VAU_FR_DoorHandle_Req_VAU2_Msg1_FR_OpenReq +#define VAU_FR_DoorHandle_Req_VAU2_Msg1_FR_OpenReq (1) +#endif + +#ifndef VAU_FR_DoorHandle_Req_VAU2_Msg1_No_Request +#define VAU_FR_DoorHandle_Req_VAU2_Msg1_No_Request (0) +#endif + + +// Value tables for @VAU_RL_DoorHandle_Req signal + +#ifndef VAU_RL_DoorHandle_Req_VAU2_Msg1_RL_UnlockReq_Long +#define VAU_RL_DoorHandle_Req_VAU2_Msg1_RL_UnlockReq_Long (6) +#endif + +#ifndef VAU_RL_DoorHandle_Req_VAU2_Msg1_RL_LockReq_Long +#define VAU_RL_DoorHandle_Req_VAU2_Msg1_RL_LockReq_Long (5) +#endif + +#ifndef VAU_RL_DoorHandle_Req_VAU2_Msg1_RL_UnlockReq +#define VAU_RL_DoorHandle_Req_VAU2_Msg1_RL_UnlockReq (4) +#endif + +#ifndef VAU_RL_DoorHandle_Req_VAU2_Msg1_RL_LockReq +#define VAU_RL_DoorHandle_Req_VAU2_Msg1_RL_LockReq (3) +#endif + +#ifndef VAU_RL_DoorHandle_Req_VAU2_Msg1_RL_CloseReq +#define VAU_RL_DoorHandle_Req_VAU2_Msg1_RL_CloseReq (2) +#endif + +#ifndef VAU_RL_DoorHandle_Req_VAU2_Msg1_RL_OpenReq +#define VAU_RL_DoorHandle_Req_VAU2_Msg1_RL_OpenReq (1) +#endif + +#ifndef VAU_RL_DoorHandle_Req_VAU2_Msg1_No_Request +#define VAU_RL_DoorHandle_Req_VAU2_Msg1_No_Request (0) +#endif + + +// Value tables for @VAU_Alarm_Req signal + +#ifndef VAU_Alarm_Req_VAU2_Msg1_Hit_detected +#define VAU_Alarm_Req_VAU2_Msg1_Hit_detected (2) +#endif + +#ifndef VAU_Alarm_Req_VAU2_Msg1_Towing_detect +#define VAU_Alarm_Req_VAU2_Msg1_Towing_detect (1) +#endif + +#ifndef VAU_Alarm_Req_VAU2_Msg1_Not_requested +#define VAU_Alarm_Req_VAU2_Msg1_Not_requested (0) +#endif + + +// Value tables for @VAU_RR_DoorHandle_Req signal + +#ifndef VAU_RR_DoorHandle_Req_VAU2_Msg1_RR_UnlockReq_Long +#define VAU_RR_DoorHandle_Req_VAU2_Msg1_RR_UnlockReq_Long (6) +#endif + +#ifndef VAU_RR_DoorHandle_Req_VAU2_Msg1_RR_LockReq_Long +#define VAU_RR_DoorHandle_Req_VAU2_Msg1_RR_LockReq_Long (5) +#endif + +#ifndef VAU_RR_DoorHandle_Req_VAU2_Msg1_RR_UnlockReq +#define VAU_RR_DoorHandle_Req_VAU2_Msg1_RR_UnlockReq (4) +#endif + +#ifndef VAU_RR_DoorHandle_Req_VAU2_Msg1_RR_LockReq +#define VAU_RR_DoorHandle_Req_VAU2_Msg1_RR_LockReq (3) +#endif + +#ifndef VAU_RR_DoorHandle_Req_VAU2_Msg1_RR_CloseReq +#define VAU_RR_DoorHandle_Req_VAU2_Msg1_RR_CloseReq (2) +#endif + +#ifndef VAU_RR_DoorHandle_Req_VAU2_Msg1_RR_OpenReq +#define VAU_RR_DoorHandle_Req_VAU2_Msg1_RR_OpenReq (1) +#endif + +#ifndef VAU_RR_DoorHandle_Req_VAU2_Msg1_No_Request +#define VAU_RR_DoorHandle_Req_VAU2_Msg1_No_Request (0) +#endif + + +// Value tables for @VAU_NFC_Cmd signal + +#ifndef VAU_NFC_Cmd_VAU2_Msg1_NFC_failed_state +#define VAU_NFC_Cmd_VAU2_Msg1_NFC_failed_state (4) +#endif + +#ifndef VAU_NFC_Cmd_VAU2_Msg1_NFC_finished_state +#define VAU_NFC_Cmd_VAU2_Msg1_NFC_finished_state (3) +#endif + +#ifndef VAU_NFC_Cmd_VAU2_Msg1_NFC_normal_state +#define VAU_NFC_Cmd_VAU2_Msg1_NFC_normal_state (2) +#endif + +#ifndef VAU_NFC_Cmd_VAU2_Msg1_NFC_learning_state +#define VAU_NFC_Cmd_VAU2_Msg1_NFC_learning_state (1) +#endif + +#ifndef VAU_NFC_Cmd_VAU2_Msg1_Idle_state +#define VAU_NFC_Cmd_VAU2_Msg1_Idle_state (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Request to wake up the vehicle from VAU + // 1 : "WakeUp_Request" + // 0 : "No_Request" + uint8_t VAU_Comm_Req : 1; // Bits= 1 + + // Response to authorization of user request + // 14 : "Trunk Close NOK" + // 13 : "Trunk Close OK" + // 12 : "DriveTrans NOK" + // 11 : "DriveTrans OK" + // 10 : "KeyDetection Req NOK" + // 9 : "KeyDetection Req OK" + // 8 : "Trunk Close&Lock NOK" + // 7 : "Trunk Open NOK" + // 6 : "Vehicle Lock Permission NOK" + // 5 : "Transition state NOK" + // 4 : "Trunk Close&Lock OK" + // 3 : "Trunk Open OK" + // 2 : "Vehicle Lock Permission OK" + // 1 : "Transition state OK" + // 0 : "No response" + uint8_t VAU_BCM_Authentication_Resp : 4; // Bits= 4 + + // Request to lock/unlock from the FL handle + // 6 : "FL_UnlockReq_Long" + // 5 : "FL_LockReq_Long" + // 4 : "FL_UnlockReq" + // 3 : "FL_LockReq" + // 2 : "FL_CloseReq" + // 1 : "FL_OpenReq" + // 0 : "No_Request" + uint8_t VAU_FL_DoorHandle_Req : 3; // Bits= 3 + + // Request to lock/unlock from the FR handle + // 6 : "FR_UnlockReq_Long" + // 5 : "FR_LockReq_Long" + // 4 : "FR_UnlockReq" + // 3 : "FR_LockReq" + // 2 : "FR_CloseReq" + // 1 : "FR_OpenReq" + // 0 : "No_Request" + uint8_t VAU_FR_DoorHandle_Req : 3; // Bits= 3 + + // Request to lock/unlock from the RL handle + // 6 : "RL_UnlockReq_Long" + // 5 : "RL_LockReq_Long" + // 4 : "RL_UnlockReq" + // 3 : "RL_LockReq" + // 2 : "RL_CloseReq" + // 1 : "RL_OpenReq" + // 0 : "No_Request" + uint8_t VAU_RL_DoorHandle_Req : 3; // Bits= 3 + + // Request for activation of the anti-theft system from the VAU unit (movement sensor) + // 2 : "Hit detected" + // 1 : "Towing detect" + // 0 : "Not requested" + uint8_t VAU_Alarm_Req : 2; // Bits= 2 + + // Request to lock/unlock from the RR handle + // 6 : "RR_UnlockReq_Long" + // 5 : "RR_LockReq_Long" + // 4 : "RR_UnlockReq" + // 3 : "RR_LockReq" + // 2 : "RR_CloseReq" + // 1 : "RR_OpenReq" + // 0 : "No_Request" + uint8_t VAU_RR_DoorHandle_Req : 3; // Bits= 3 + + // Command to working state of NFC in Front Wireless Charger + // 4 : "NFC failed state" + // 3 : "NFC finished state" + // 2 : "NFC normal state" + // 1 : "NFC learning state" + // 0 : "Idle state" + uint8_t VAU_NFC_Cmd : 3; // Bits= 3 + +#else + + // Request to wake up the vehicle from VAU + // 1 : "WakeUp_Request" + // 0 : "No_Request" + uint8_t VAU_Comm_Req; // Bits= 1 + + // Response to authorization of user request + // 14 : "Trunk Close NOK" + // 13 : "Trunk Close OK" + // 12 : "DriveTrans NOK" + // 11 : "DriveTrans OK" + // 10 : "KeyDetection Req NOK" + // 9 : "KeyDetection Req OK" + // 8 : "Trunk Close&Lock NOK" + // 7 : "Trunk Open NOK" + // 6 : "Vehicle Lock Permission NOK" + // 5 : "Transition state NOK" + // 4 : "Trunk Close&Lock OK" + // 3 : "Trunk Open OK" + // 2 : "Vehicle Lock Permission OK" + // 1 : "Transition state OK" + // 0 : "No response" + uint8_t VAU_BCM_Authentication_Resp; // Bits= 4 + + // Request to lock/unlock from the FL handle + // 6 : "FL_UnlockReq_Long" + // 5 : "FL_LockReq_Long" + // 4 : "FL_UnlockReq" + // 3 : "FL_LockReq" + // 2 : "FL_CloseReq" + // 1 : "FL_OpenReq" + // 0 : "No_Request" + uint8_t VAU_FL_DoorHandle_Req; // Bits= 3 + + // Request to lock/unlock from the FR handle + // 6 : "FR_UnlockReq_Long" + // 5 : "FR_LockReq_Long" + // 4 : "FR_UnlockReq" + // 3 : "FR_LockReq" + // 2 : "FR_CloseReq" + // 1 : "FR_OpenReq" + // 0 : "No_Request" + uint8_t VAU_FR_DoorHandle_Req; // Bits= 3 + + // Request to lock/unlock from the RL handle + // 6 : "RL_UnlockReq_Long" + // 5 : "RL_LockReq_Long" + // 4 : "RL_UnlockReq" + // 3 : "RL_LockReq" + // 2 : "RL_CloseReq" + // 1 : "RL_OpenReq" + // 0 : "No_Request" + uint8_t VAU_RL_DoorHandle_Req; // Bits= 3 + + // Request for activation of the anti-theft system from the VAU unit (movement sensor) + // 2 : "Hit detected" + // 1 : "Towing detect" + // 0 : "Not requested" + uint8_t VAU_Alarm_Req; // Bits= 2 + + // Request to lock/unlock from the RR handle + // 6 : "RR_UnlockReq_Long" + // 5 : "RR_LockReq_Long" + // 4 : "RR_UnlockReq" + // 3 : "RR_LockReq" + // 2 : "RR_CloseReq" + // 1 : "RR_OpenReq" + // 0 : "No_Request" + uint8_t VAU_RR_DoorHandle_Req; // Bits= 3 + + // Command to working state of NFC in Front Wireless Charger + // 4 : "NFC failed state" + // 3 : "NFC finished state" + // 2 : "NFC normal state" + // 1 : "NFC learning state" + // 0 : "Idle state" + uint8_t VAU_NFC_Cmd; // Bits= 3 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} VAU2_Msg1_t; + +// def @ESC_YRS_01 CAN Message (304 0x130) +#define ESC_YRS_01_IDE (0U) +#define ESC_YRS_01_DLC (8U) +#define ESC_YRS_01_CANID (0x130U) +#define ESC_YRS_01_CYC (10U) +// signal: @ESC_PSIP1_Val_ro +#define CANDB_ESC_PSIP1_Val_ro_CovFactor (0.005) +#define CANDB_ESC_PSIP1_Val_ro_toS(x) ( (uint16_t) (((x) - (-163.84)) / (0.005)) ) +#define CANDB_ESC_PSIP1_Val_ro_fromS(x) ( (((x) * (0.005)) + (-163.84)) ) +// signal: @ESC_AY_Val_ro +#define CANDB_ESC_AY_Val_ro_CovFactor (0.0001274) +#define CANDB_ESC_AY_Val_ro_toS(x) ( (uint16_t) (((x) - (-4.1745)) / (0.0001274)) ) +#define CANDB_ESC_AY_Val_ro_fromS(x) ( (((x) * (0.0001274)) + (-4.1745)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Yaw rate signal routed through ESP. Signal limited by SW to +/-100 degree per sec + uint16_t ESC_PSIP1_Val_ro; // Bits=16 Offset= -163.84 Factor= 0.005 Unit:'�/s' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t ESC_PSIP1_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Sensor cluster status signal routed through ESP + // xx00 Reserved + // xx01 Reserved + // xx10 Reserved + // xx11 Reserved + // x0xx No sync underflow detected + // x1xx Sync underflow detected + // 0xxx No sync failure detected + // 1xxx Sync failure detected + uint8_t ESC_CLU_Stat : 4; // Bits= 4 + + // Qualifier for yaw rate export signal + // xx00 Signal in specification + // xx01 Sensor not available + // xx10 Signal failure + // xx11 Reserved + // x0xx Initialization finished + // x1xx Initialization running + // 0xxx Reserved + // 1xxx Reserved + uint8_t ESC_PSIP1_Stat : 4; // Bits= 4 + + // Reserve Signal. Coded with 0000h + uint8_t ESC_Reserve1; // Bits= 8 + + // Lateral Acceleration signal routed through ESP. Signal limited by SW to -/+1.8 g + uint16_t ESC_AY_Val_ro; // Bits=16 Offset= -4.1745 Factor= 0.0001274 Unit:'g' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t ESC_AY_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Rolling Counter [0 - 15] + uint8_t ESC_YRS_01_RC : 4; // Bits= 4 + + // Qualifier for lateral acceleration export signal + // xx00 Signal in specification + // xx01 Sensor not available + // xx10 Signal failure + // xx11 Reserved + // x0xx Initialization finished + // x1xx Initialization running + // 0xxx Reserved + // 1xxx Reserved + uint8_t ESC_AY_Stat : 4; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t ESC_YRS_01_CS; // Bits= 8 + +#else + + // Yaw rate signal routed through ESP. Signal limited by SW to +/-100 degree per sec + uint16_t ESC_PSIP1_Val_ro; // Bits=16 Offset= -163.84 Factor= 0.005 Unit:'�/s' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t ESC_PSIP1_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Sensor cluster status signal routed through ESP + // xx00 Reserved + // xx01 Reserved + // xx10 Reserved + // xx11 Reserved + // x0xx No sync underflow detected + // x1xx Sync underflow detected + // 0xxx No sync failure detected + // 1xxx Sync failure detected + uint8_t ESC_CLU_Stat; // Bits= 4 + + // Qualifier for yaw rate export signal + // xx00 Signal in specification + // xx01 Sensor not available + // xx10 Signal failure + // xx11 Reserved + // x0xx Initialization finished + // x1xx Initialization running + // 0xxx Reserved + // 1xxx Reserved + uint8_t ESC_PSIP1_Stat; // Bits= 4 + + // Reserve Signal. Coded with 0000h + uint8_t ESC_Reserve1; // Bits= 8 + + // Lateral Acceleration signal routed through ESP. Signal limited by SW to -/+1.8 g + uint16_t ESC_AY_Val_ro; // Bits=16 Offset= -4.1745 Factor= 0.0001274 Unit:'g' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t ESC_AY_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Rolling Counter [0 - 15] + uint8_t ESC_YRS_01_RC; // Bits= 4 + + // Qualifier for lateral acceleration export signal + // xx00 Signal in specification + // xx01 Sensor not available + // xx10 Signal failure + // xx11 Reserved + // x0xx Initialization finished + // x1xx Initialization running + // 0xxx Reserved + // 1xxx Reserved + uint8_t ESC_AY_Stat; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t ESC_YRS_01_CS; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} ESC_YRS_01_t; + +// def @EMS_Veh CAN Message (336 0x150) +#define EMS_Veh_IDE (0U) +#define EMS_Veh_DLC (8U) +#define EMS_Veh_CANID (0x150U) +#define EMS_Veh_CYC (100U) +// signal: @EMS_nICEngineSpeed3_Val_ro +#define CANDB_EMS_nICEngineSpeed3_Val_ro_CovFactor (0.25) +#define CANDB_EMS_nICEngineSpeed3_Val_ro_toS(x) ( (uint16_t) (((x) - (0.0)) / (0.25)) ) +#define CANDB_EMS_nICEngineSpeed3_Val_ro_fromS(x) ( (((x) * (0.25)) + (0.0)) ) +// signal: @EMS_EngCoolTemp_Val_ro +#define CANDB_EMS_EngCoolTemp_Val_ro_CovFactor (1) +#define CANDB_EMS_EngCoolTemp_Val_ro_toS(x) ( (uint8_t) ((x) - (-40)) ) +#define CANDB_EMS_EngCoolTemp_Val_ro_fromS(x) ( ((x) + (-40)) ) +// signal: @EMS_EngTrqStatic_Val_ro +#define CANDB_EMS_EngTrqStatic_Val_ro_CovFactor (0.25) +#define CANDB_EMS_EngTrqStatic_Val_ro_toS(x) ( (uint16_t) (((x) - (-500.0)) / (0.25)) ) +#define CANDB_EMS_EngTrqStatic_Val_ro_fromS(x) ( (((x) * (0.25)) + (-500.0)) ) + +// Value tables for @EMS_HvSystemFailure signal + +#ifndef EMS_HvSystemFailure_EMS_Veh_HVSYSTEMS_ERROR +#define EMS_HvSystemFailure_EMS_Veh_HVSYSTEMS_ERROR (3) +#endif + +#ifndef EMS_HvSystemFailure_EMS_Veh_HVSYSTEM_WARNING +#define EMS_HvSystemFailure_EMS_Veh_HVSYSTEM_WARNING (2) +#endif + +#ifndef EMS_HvSystemFailure_EMS_Veh_NO_ENERGY_SOURCE_AVAILABLE +#define EMS_HvSystemFailure_EMS_Veh_NO_ENERGY_SOURCE_AVAILABLE (1) +#endif + +#ifndef EMS_HvSystemFailure_EMS_Veh_NO_FAILURE +#define EMS_HvSystemFailure_EMS_Veh_NO_FAILURE (0) +#endif + + +// Value tables for @EMS_CoolLiquidLowWarning signal + +#ifndef EMS_CoolLiquidLowWarning_EMS_Veh_Warning +#define EMS_CoolLiquidLowWarning_EMS_Veh_Warning (1) +#endif + +#ifndef EMS_CoolLiquidLowWarning_EMS_Veh_No_Warning +#define EMS_CoolLiquidLowWarning_EMS_Veh_No_Warning (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Internal combustion engine: Engine speed + uint16_t EMS_nICEngineSpeed3_Val_ro; // Bits=16 Factor= 0.25 Unit:'rpm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t EMS_nICEngineSpeed3_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Engine coolant temperature + uint8_t EMS_EngCoolTemp_Val_ro; // Bits= 8 Offset= -40 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + int16_t EMS_EngCoolTemp_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Ambient air pressure (barometric pressure) + uint8_t EMS_BARO_ENG_Val; // Bits= 8 Unit:'kPa' + + // Accelerator pedal position + uint8_t EMS_AccelPdlPosnOBD_Val; // Bits= 8 + + // Actual engine torque + uint16_t EMS_EngTrqStatic_Val_ro; // Bits=13 Offset= -500.0 Factor= 0.25 Unit:'Nm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t EMS_EngTrqStatic_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // HV system failure: + // $0 = No failure + // $1 = No energy source available - Request for starting engine will be displayed on IC + // $2 = HV-System warning + // $3 = HV-Systems error + // 3 : "HV-SYSTEMS_ERROR" + // 2 : "HV-SYSTEM_WARNING" + // 1 : "NO_ENERGY_SOURCE_AVAILABLE" + // 0 : "NO FAILURE" + uint8_t EMS_HvSystemFailure : 2; // Bits= 2 + + // Low lnevel of cooling liquid detected => Warning requested + // $0 = No Warning + // $1 = Warning + // 1 : "Warning" + // 0 : "No Warning" + uint8_t EMS_CoolLiquidLowWarning : 1; // Bits= 1 + + // Instantaneous fuel consumption inmilliliter/second + uint8_t EMS_InstFuelConsumption; // Bits= 8 Unit:'ml/s' + +#else + + // Internal combustion engine: Engine speed + uint16_t EMS_nICEngineSpeed3_Val_ro; // Bits=16 Factor= 0.25 Unit:'rpm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t EMS_nICEngineSpeed3_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Engine coolant temperature + uint8_t EMS_EngCoolTemp_Val_ro; // Bits= 8 Offset= -40 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + int16_t EMS_EngCoolTemp_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Ambient air pressure (barometric pressure) + uint8_t EMS_BARO_ENG_Val; // Bits= 8 Unit:'kPa' + + // Accelerator pedal position + uint8_t EMS_AccelPdlPosnOBD_Val; // Bits= 8 + + // Actual engine torque + uint16_t EMS_EngTrqStatic_Val_ro; // Bits=13 Offset= -500.0 Factor= 0.25 Unit:'Nm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t EMS_EngTrqStatic_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // HV system failure: + // $0 = No failure + // $1 = No energy source available - Request for starting engine will be displayed on IC + // $2 = HV-System warning + // $3 = HV-Systems error + // 3 : "HV-SYSTEMS_ERROR" + // 2 : "HV-SYSTEM_WARNING" + // 1 : "NO_ENERGY_SOURCE_AVAILABLE" + // 0 : "NO FAILURE" + uint8_t EMS_HvSystemFailure; // Bits= 2 + + // Low lnevel of cooling liquid detected => Warning requested + // $0 = No Warning + // $1 = Warning + // 1 : "Warning" + // 0 : "No Warning" + uint8_t EMS_CoolLiquidLowWarning; // Bits= 1 + + // Instantaneous fuel consumption inmilliliter/second + uint8_t EMS_InstFuelConsumption; // Bits= 8 Unit:'ml/s' + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} EMS_Veh_t; + +// def @EMS_Indicators CAN Message (337 0x151) +#define EMS_Indicators_IDE (0U) +#define EMS_Indicators_DLC (3U) +#define EMS_Indicators_CANID (0x151U) +#define EMS_Indicators_CYC (100U) +// signal: @EMS_EngOilTemp_Val_ro +#define CANDB_EMS_EngOilTemp_Val_ro_CovFactor (1) +#define CANDB_EMS_EngOilTemp_Val_ro_toS(x) ( (uint8_t) ((x) - (-40)) ) +#define CANDB_EMS_EngOilTemp_Val_ro_fromS(x) ( ((x) + (-40)) ) +// signal: @EMS_OilLvl_Val_ro +#define CANDB_EMS_OilLvl_Val_ro_CovFactor (1.15) +#define CANDB_EMS_OilLvl_Val_ro_toS(x) ( (uint8_t) (((x) - (-20.0)) / (1.15)) ) +#define CANDB_EMS_OilLvl_Val_ro_fromS(x) ( (((x) * (1.15)) + (-20.0)) ) + +// Value tables for @EMS_MILblink_Req signal + +#ifndef EMS_MILblink_Req_EMS_Indicators_MIL_Blink +#define EMS_MILblink_Req_EMS_Indicators_MIL_Blink (1) +#endif + +#ifndef EMS_MILblink_Req_EMS_Indicators_MIL_OFF +#define EMS_MILblink_Req_EMS_Indicators_MIL_OFF (0) +#endif + + +// Value tables for @EMS_EngOilLvInd_Stat signal + +#ifndef EMS_EngOilLvInd_Stat_EMS_Indicators_Critical_low_level +#define EMS_EngOilLvInd_Stat_EMS_Indicators_Critical_low_level (3) +#endif + +#ifndef EMS_EngOilLvInd_Stat_EMS_Indicators_High_level +#define EMS_EngOilLvInd_Stat_EMS_Indicators_High_level (2) +#endif + +#ifndef EMS_EngOilLvInd_Stat_EMS_Indicators_Low_level +#define EMS_EngOilLvInd_Stat_EMS_Indicators_Low_level (1) +#endif + +#ifndef EMS_EngOilLvInd_Stat_EMS_Indicators_Normal_level +#define EMS_EngOilLvInd_Stat_EMS_Indicators_Normal_level (0) +#endif + + +// Value tables for @EMS_MILon_Req signal + +#ifndef EMS_MILon_Req_EMS_Indicators_MIL_ON +#define EMS_MILon_Req_EMS_Indicators_MIL_ON (1) +#endif + +#ifndef EMS_MILon_Req_EMS_Indicators_MIL_OFF +#define EMS_MILon_Req_EMS_Indicators_MIL_OFF (0) +#endif + + +// Value tables for @EMS_OilPresWarn_Stat signal + +#ifndef EMS_OilPresWarn_Stat_EMS_Indicators_Low_pressure +#define EMS_OilPresWarn_Stat_EMS_Indicators_Low_pressure (1) +#endif + +#ifndef EMS_OilPresWarn_Stat_EMS_Indicators_Normal_pressure +#define EMS_OilPresWarn_Stat_EMS_Indicators_Normal_pressure (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Oil temperature + uint8_t EMS_EngOilTemp_Val_ro; // Bits= 8 Offset= -40 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + int16_t EMS_EngOilTemp_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Indicates the Oil level. + uint8_t EMS_OilLvl_Val_ro : 7; // Bits= 7 Offset= -20.0 Factor= 1.15 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t EMS_OilLvl_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Request MIL blink + // 1 : "MIL Blink" + // 0 : "MIL OFF" + uint8_t EMS_MILblink_Req : 1; // Bits= 1 + + // Indicates engine oil level states. + // 3 : "Critical low level" + // 2 : "High level" + // 1 : "Low level" + // 0 : "Normal level" + uint8_t EMS_EngOilLvInd_Stat : 2; // Bits= 2 + + // MIL ON request from the engine + // 1 : "MIL ON" + // 0 : "MIL OFF" + uint8_t EMS_MILon_Req : 1; // Bits= 1 + + // LTC coolant level signal (flag) + uint8_t EMS_LTCcoolantLvl_Stat : 1; // Bits= 1 + + // Indicates whether the oil pressure is getting low. + // 1 : "Low pressure" + // 0 : "Normal pressure" + uint8_t EMS_OilPresWarn_Stat : 1; // Bits= 1 + +#else + + // Oil temperature + uint8_t EMS_EngOilTemp_Val_ro; // Bits= 8 Offset= -40 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + int16_t EMS_EngOilTemp_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Indicates the Oil level. + uint8_t EMS_OilLvl_Val_ro; // Bits= 7 Offset= -20.0 Factor= 1.15 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t EMS_OilLvl_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Request MIL blink + // 1 : "MIL Blink" + // 0 : "MIL OFF" + uint8_t EMS_MILblink_Req; // Bits= 1 + + // Indicates engine oil level states. + // 3 : "Critical low level" + // 2 : "High level" + // 1 : "Low level" + // 0 : "Normal level" + uint8_t EMS_EngOilLvInd_Stat; // Bits= 2 + + // MIL ON request from the engine + // 1 : "MIL ON" + // 0 : "MIL OFF" + uint8_t EMS_MILon_Req; // Bits= 1 + + // LTC coolant level signal (flag) + uint8_t EMS_LTCcoolantLvl_Stat; // Bits= 1 + + // Indicates whether the oil pressure is getting low. + // 1 : "Low pressure" + // 0 : "Normal pressure" + uint8_t EMS_OilPresWarn_Stat; // Bits= 1 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} EMS_Indicators_t; + +// def @BCM_Powertrain CAN Message (338 0x152) +#define BCM_Powertrain_IDE (0U) +#define BCM_Powertrain_DLC (6U) +#define BCM_Powertrain_CANID (0x152U) +#define BCM_Powertrain_CYC (10U) +// signal: @BCM_AmbTempRaw_ro +#define CANDB_BCM_AmbTempRaw_ro_CovFactor (0.01) +#define CANDB_BCM_AmbTempRaw_ro_toS(x) ( (uint16_t) (((x) - (-40.0)) / (0.01)) ) +#define CANDB_BCM_AmbTempRaw_ro_fromS(x) ( (((x) * (0.01)) + (-40.0)) ) +// signal: @AvgFuelLvl_ro +#define CANDB_AvgFuelLvl_ro_CovFactor (0.5) +#define CANDB_AvgFuelLvl_ro_toS(x) ( (uint16_t) (((x) - (0.0)) / (0.5)) ) +#define CANDB_AvgFuelLvl_ro_fromS(x) ( (((x) * (0.5)) + (0.0)) ) + +// Value tables for @BCM_T50_Request signal + +#ifndef BCM_T50_Request_BCM_Powertrain_T50_Request +#define BCM_T50_Request_BCM_Powertrain_T50_Request (1) +#endif + +#ifndef BCM_T50_Request_BCM_Powertrain_No_Request +#define BCM_T50_Request_BCM_Powertrain_No_Request (0) +#endif + + +// Value tables for @RemoteICEStartReq signal + +#ifndef RemoteICEStartReq_BCM_Powertrain_Remote_start_request_active +#define RemoteICEStartReq_BCM_Powertrain_Remote_start_request_active (1) +#endif + +#ifndef RemoteICEStartReq_BCM_Powertrain_Remote_start_request_inactive +#define RemoteICEStartReq_BCM_Powertrain_Remote_start_request_inactive (0) +#endif + + +// Value tables for @BCM_HVAC_Pump_Req signal + +#ifndef BCM_HVAC_Pump_Req_BCM_Powertrain_Request_Active +#define BCM_HVAC_Pump_Req_BCM_Powertrain_Request_Active (1) +#endif + +#ifndef BCM_HVAC_Pump_Req_BCM_Powertrain_No_request +#define BCM_HVAC_Pump_Req_BCM_Powertrain_No_request (0) +#endif + + +// Value tables for @BCM_VAU_Authorization_Req signal + +#ifndef BCM_VAU_Authorization_Req_BCM_Powertrain_TrunkClose_requested +#define BCM_VAU_Authorization_Req_BCM_Powertrain_TrunkClose_requested (7) +#endif + +#ifndef BCM_VAU_Authorization_Req_BCM_Powertrain_DriveTrans_requested +#define BCM_VAU_Authorization_Req_BCM_Powertrain_DriveTrans_requested (6) +#endif + +#ifndef BCM_VAU_Authorization_Req_BCM_Powertrain_KeyDetection_requested +#define BCM_VAU_Authorization_Req_BCM_Powertrain_KeyDetection_requested (5) +#endif + +#ifndef BCM_VAU_Authorization_Req_BCM_Powertrain_Trunk_CloseLock_requested +#define BCM_VAU_Authorization_Req_BCM_Powertrain_Trunk_CloseLock_requested (4) +#endif + +#ifndef BCM_VAU_Authorization_Req_BCM_Powertrain_TrunkOpen_requested +#define BCM_VAU_Authorization_Req_BCM_Powertrain_TrunkOpen_requested (3) +#endif + +#ifndef BCM_VAU_Authorization_Req_BCM_Powertrain_LockPermission_requested +#define BCM_VAU_Authorization_Req_BCM_Powertrain_LockPermission_requested (2) +#endif + +#ifndef BCM_VAU_Authorization_Req_BCM_Powertrain_VehicleState_Trans_requested +#define BCM_VAU_Authorization_Req_BCM_Powertrain_VehicleState_Trans_requested (1) +#endif + +#ifndef BCM_VAU_Authorization_Req_BCM_Powertrain_Not_requested +#define BCM_VAU_Authorization_Req_BCM_Powertrain_Not_requested (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Averaged ambient temperature RAW value + uint16_t BCM_AmbTempRaw_ro; // Bits=16 Offset= -40.0 Factor= 0.01 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_AmbTempRaw_phys; +#endif // CANDB_USE_SIGFLOAT + + // Signal shows how much liters of fuel remains in the vehicle fuel tank when T15=ON. + // When T15 = OFF the signal is equal to zero. + uint16_t AvgFuelLvl_ro; // Bits= 9 Factor= 0.5 Unit:'l' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t AvgFuelLvl_phys; +#endif // CANDB_USE_SIGFLOAT + + // ICE Start request. T50 should be sent as long as the engine state has not reached CoEng_st == COENG_RUNNING for starting the ICE + // 1 : "T50_Request" + // 0 : "No_Request" + uint8_t BCM_T50_Request : 1; // Bits= 1 + + // State of remote start procedure + // 1 : "Remote start request active" + // 0 : "Remote start request inactive" + uint8_t RemoteICEStartReq : 1; // Bits= 1 + + // Request for activating HVAC cooling Pump for APU. + // 1 : "Request Active" + // 0 : "No request" + uint8_t BCM_HVAC_Pump_Req : 1; // Bits= 1 + + // Rolling Counter [0 - 15] + uint8_t BCM_Powertrain_RC : 4; // Bits= 4 + + // Request to authorize lock control actions or vehicle state transition + // 7 : "TrunkClose requested" + // 6 : "DriveTrans requested" + // 5 : "KeyDetection requested" + // 4 : "Trunk_Close&Lock requested" + // 3 : "TrunkOpen requested" + // 2 : "LockPermission requested" + // 1 : "VehicleState Trans requested" + // 0 : "Not requested" + uint8_t BCM_VAU_Authorization_Req : 3; // Bits= 3 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t BCM_Powertrain_CS; // Bits= 8 + +#else + + // Averaged ambient temperature RAW value + uint16_t BCM_AmbTempRaw_ro; // Bits=16 Offset= -40.0 Factor= 0.01 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_AmbTempRaw_phys; +#endif // CANDB_USE_SIGFLOAT + + // Signal shows how much liters of fuel remains in the vehicle fuel tank when T15=ON. + // When T15 = OFF the signal is equal to zero. + uint16_t AvgFuelLvl_ro; // Bits= 9 Factor= 0.5 Unit:'l' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t AvgFuelLvl_phys; +#endif // CANDB_USE_SIGFLOAT + + // ICE Start request. T50 should be sent as long as the engine state has not reached CoEng_st == COENG_RUNNING for starting the ICE + // 1 : "T50_Request" + // 0 : "No_Request" + uint8_t BCM_T50_Request; // Bits= 1 + + // State of remote start procedure + // 1 : "Remote start request active" + // 0 : "Remote start request inactive" + uint8_t RemoteICEStartReq; // Bits= 1 + + // Request for activating HVAC cooling Pump for APU. + // 1 : "Request Active" + // 0 : "No request" + uint8_t BCM_HVAC_Pump_Req; // Bits= 1 + + // Rolling Counter [0 - 15] + uint8_t BCM_Powertrain_RC; // Bits= 4 + + // Request to authorize lock control actions or vehicle state transition + // 7 : "TrunkClose requested" + // 6 : "DriveTrans requested" + // 5 : "KeyDetection requested" + // 4 : "Trunk_Close&Lock requested" + // 3 : "TrunkOpen requested" + // 2 : "LockPermission requested" + // 1 : "VehicleState Trans requested" + // 0 : "Not requested" + uint8_t BCM_VAU_Authorization_Req; // Bits= 3 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t BCM_Powertrain_CS; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} BCM_Powertrain_t; + +// def @EMS_Veh_02 CAN Message (339 0x153) +#define EMS_Veh_02_IDE (0U) +#define EMS_Veh_02_DLC (3U) +#define EMS_Veh_02_CANID (0x153U) +#define EMS_Veh_02_CYC (20U) + +// Value tables for @EMS_CoEng_Stat signal + +#ifndef EMS_CoEng_Stat_EMS_Veh_02_CoENG_Finish +#define EMS_CoEng_Stat_EMS_Veh_02_CoENG_Finish (5) +#endif + +#ifndef EMS_CoEng_Stat_EMS_Veh_02_CoENG_Stopping +#define EMS_CoEng_Stat_EMS_Veh_02_CoENG_Stopping (4) +#endif + +#ifndef EMS_CoEng_Stat_EMS_Veh_02_CoENG_Running +#define EMS_CoEng_Stat_EMS_Veh_02_CoENG_Running (3) +#endif + +#ifndef EMS_CoEng_Stat_EMS_Veh_02_CoENG_Cranking +#define EMS_CoEng_Stat_EMS_Veh_02_CoENG_Cranking (2) +#endif + +#ifndef EMS_CoEng_Stat_EMS_Veh_02_CoENG_Ready +#define EMS_CoEng_Stat_EMS_Veh_02_CoENG_Ready (1) +#endif + +#ifndef EMS_CoEng_Stat_EMS_Veh_02_CoENG_Stanby +#define EMS_CoEng_Stat_EMS_Veh_02_CoENG_Stanby (0) +#endif + +// signal: @BMS_ActualTemp_Val_ro +#define CANDB_BMS_ActualTemp_Val_ro_CovFactor (0.5) +#define CANDB_BMS_ActualTemp_Val_ro_toS(x) ( (uint8_t) (((x) - (-40.0)) / (0.5)) ) +#define CANDB_BMS_ActualTemp_Val_ro_fromS(x) ( (((x) * (0.5)) + (-40.0)) ) + +// Value tables for @EMS_NAMI_Stat signal + +#ifndef EMS_NAMI_Stat_EMS_Veh_02_EMS_NAMI +#define EMS_NAMI_Stat_EMS_Veh_02_EMS_NAMI (1) +#endif + +#ifndef EMS_NAMI_Stat_EMS_Veh_02_EMS_Bosch +#define EMS_NAMI_Stat_EMS_Veh_02_EMS_Bosch (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Status of combustion engine + // 5 : "CoENG_Finish" + // 4 : "CoENG_Stopping" + // 3 : "CoENG_Running" + // 2 : "CoENG_Cranking" + // 1 : "CoENG_Ready" + // 0 : "CoENG_Stanby" + uint8_t EMS_CoEng_Stat : 3; // Bits= 3 + + // Actual battery temperature + uint8_t BMS_ActualTemp_Val_ro; // Bits= 8 Offset= -40.0 Factor= 0.5 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BMS_ActualTemp_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // 1 : "EMS NAMI" + // 0 : "EMS Bosch" + uint8_t EMS_NAMI_Stat : 1; // Bits= 1 + + // Rolling Counter [0 - 15] + uint8_t EMS_Veh_02_RC : 4; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t EMS_Veh_02_CS; // Bits= 8 + +#else + + // Status of combustion engine + // 5 : "CoENG_Finish" + // 4 : "CoENG_Stopping" + // 3 : "CoENG_Running" + // 2 : "CoENG_Cranking" + // 1 : "CoENG_Ready" + // 0 : "CoENG_Stanby" + uint8_t EMS_CoEng_Stat; // Bits= 3 + + // Actual battery temperature + uint8_t BMS_ActualTemp_Val_ro; // Bits= 8 Offset= -40.0 Factor= 0.5 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BMS_ActualTemp_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // 1 : "EMS NAMI" + // 0 : "EMS Bosch" + uint8_t EMS_NAMI_Stat; // Bits= 1 + + // Rolling Counter [0 - 15] + uint8_t EMS_Veh_02_RC; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t EMS_Veh_02_CS; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} EMS_Veh_02_t; + +// def @EMS_EEM_01 CAN Message (341 0x155) +#define EMS_EEM_01_IDE (0U) +#define EMS_EEM_01_DLC (7U) +#define EMS_EEM_01_CANID (0x155U) +#define EMS_EEM_01_CYC (100U) +// signal: @EMS_ActCurrLV_DCDC1_ro +#define CANDB_EMS_ActCurrLV_DCDC1_ro_CovFactor (0.1) +#define CANDB_EMS_ActCurrLV_DCDC1_ro_toS(x) ( (uint16_t) (((x) - (-3276.7)) / (0.1)) ) +#define CANDB_EMS_ActCurrLV_DCDC1_ro_fromS(x) ( (((x) * (0.1)) + (-3276.7)) ) +// signal: @EMS_ActVoltLV_DCDC1_ro +#define CANDB_EMS_ActVoltLV_DCDC1_ro_CovFactor (0.1) +#define CANDB_EMS_ActVoltLV_DCDC1_ro_toS(x) ( (uint16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_EMS_ActVoltLV_DCDC1_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +// Value tables for @EMS_ErrPrfLim_DCDC1 signal + +#ifndef EMS_ErrPrfLim_DCDC1_EMS_EEM_01_Power_limitation +#define EMS_ErrPrfLim_DCDC1_EMS_EEM_01_Power_limitation (1) +#endif + +#ifndef EMS_ErrPrfLim_DCDC1_EMS_EEM_01_No_power_limitation +#define EMS_ErrPrfLim_DCDC1_EMS_EEM_01_No_power_limitation (0) +#endif + + +// Value tables for @EMS_Err_DCDC1 signal + +#ifndef EMS_Err_DCDC1_EMS_EEM_01_DCDC1_error +#define EMS_Err_DCDC1_EMS_EEM_01_DCDC1_error (1) +#endif + +#ifndef EMS_Err_DCDC1_EMS_EEM_01_NO_DCDC1_error +#define EMS_Err_DCDC1_EMS_EEM_01_NO_DCDC1_error (0) +#endif + + +// Value tables for @EMS_stMode_DCDC1 signal + +#ifndef EMS_stMode_DCDC1_EMS_EEM_01_Buck_with_Drive_HV__LV +#define EMS_stMode_DCDC1_EMS_EEM_01_Buck_with_Drive_HV__LV (1) +#endif + +#ifndef EMS_stMode_DCDC1_EMS_EEM_01_Standby_communication_active +#define EMS_stMode_DCDC1_EMS_EEM_01_Standby_communication_active (0) +#endif + +// signal: @EMS_UtilRate_DCDC1_ro +#define CANDB_EMS_UtilRate_DCDC1_ro_CovFactor (0.1) +#define CANDB_EMS_UtilRate_DCDC1_ro_toS(x) ( (uint16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_EMS_UtilRate_DCDC1_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Actual current LV DC/DC1 + uint16_t EMS_ActCurrLV_DCDC1_ro; // Bits=16 Offset= -3276.7 Factor= 0.1 Unit:'A' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t EMS_ActCurrLV_DCDC1_phys; +#endif // CANDB_USE_SIGFLOAT + + // Actual voltage LV DC/DC1 + uint16_t EMS_ActVoltLV_DCDC1_ro; // Bits=10 Factor= 0.1 Unit:'V' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t EMS_ActVoltLV_DCDC1_phys; +#endif // CANDB_USE_SIGFLOAT + + // 1 : "Power limitation" + // 0 : "No power limitation" + uint8_t EMS_ErrPrfLim_DCDC1 : 1; // Bits= 1 + + // Error flag failure DC/DC1 (VDDC_bErrShOff or VDDC_bErrVltg) + // 1 : "DCDC1 error" + // 0 : "NO DCDC1 error" + uint8_t EMS_Err_DCDC1 : 1; // Bits= 1 + + // Operating mode DC/DC1 + // 1 : "Buck with Drive (HV --> LV)" + // 0 : "Standby, communication active" + uint8_t EMS_stMode_DCDC1 : 1; // Bits= 1 + + // Utilization DC/DC1 + uint16_t EMS_UtilRate_DCDC1_ro; // Bits=10 Factor= 0.1 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t EMS_UtilRate_DCDC1_phys; +#endif // CANDB_USE_SIGFLOAT + + // Rolling Counter [0 - 15] + uint8_t EMS_EEM_01_RC : 4; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t EMS_EEM_01_CS; // Bits= 8 + +#else + + // Actual current LV DC/DC1 + uint16_t EMS_ActCurrLV_DCDC1_ro; // Bits=16 Offset= -3276.7 Factor= 0.1 Unit:'A' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t EMS_ActCurrLV_DCDC1_phys; +#endif // CANDB_USE_SIGFLOAT + + // Actual voltage LV DC/DC1 + uint16_t EMS_ActVoltLV_DCDC1_ro; // Bits=10 Factor= 0.1 Unit:'V' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t EMS_ActVoltLV_DCDC1_phys; +#endif // CANDB_USE_SIGFLOAT + + // 1 : "Power limitation" + // 0 : "No power limitation" + uint8_t EMS_ErrPrfLim_DCDC1; // Bits= 1 + + // Error flag failure DC/DC1 (VDDC_bErrShOff or VDDC_bErrVltg) + // 1 : "DCDC1 error" + // 0 : "NO DCDC1 error" + uint8_t EMS_Err_DCDC1; // Bits= 1 + + // Operating mode DC/DC1 + // 1 : "Buck with Drive (HV --> LV)" + // 0 : "Standby, communication active" + uint8_t EMS_stMode_DCDC1; // Bits= 1 + + // Utilization DC/DC1 + uint16_t EMS_UtilRate_DCDC1_ro; // Bits=10 Factor= 0.1 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t EMS_UtilRate_DCDC1_phys; +#endif // CANDB_USE_SIGFLOAT + + // Rolling Counter [0 - 15] + uint8_t EMS_EEM_01_RC; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t EMS_EEM_01_CS; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} EMS_EEM_01_t; + +// def @EMS_EEM_02 CAN Message (342 0x156) +#define EMS_EEM_02_IDE (0U) +#define EMS_EEM_02_DLC (7U) +#define EMS_EEM_02_CANID (0x156U) +#define EMS_EEM_02_CYC (100U) +// signal: @EMS_ActCurrLV_DCDC2_ro +#define CANDB_EMS_ActCurrLV_DCDC2_ro_CovFactor (0.1) +#define CANDB_EMS_ActCurrLV_DCDC2_ro_toS(x) ( (uint16_t) (((x) - (-3276.7)) / (0.1)) ) +#define CANDB_EMS_ActCurrLV_DCDC2_ro_fromS(x) ( (((x) * (0.1)) + (-3276.7)) ) +// signal: @EMS_ActVoltLV_DCDC2_ro +#define CANDB_EMS_ActVoltLV_DCDC2_ro_CovFactor (0.1) +#define CANDB_EMS_ActVoltLV_DCDC2_ro_toS(x) ( (uint16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_EMS_ActVoltLV_DCDC2_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +// Value tables for @EMS_ErrPrfLim_DCDC2 signal + +#ifndef EMS_ErrPrfLim_DCDC2_EMS_EEM_02_Power_limitation +#define EMS_ErrPrfLim_DCDC2_EMS_EEM_02_Power_limitation (1) +#endif + +#ifndef EMS_ErrPrfLim_DCDC2_EMS_EEM_02_No_power_limitation +#define EMS_ErrPrfLim_DCDC2_EMS_EEM_02_No_power_limitation (0) +#endif + + +// Value tables for @EMS_Err_DCDC2 signal + +#ifndef EMS_Err_DCDC2_EMS_EEM_02_DCDC2_error +#define EMS_Err_DCDC2_EMS_EEM_02_DCDC2_error (1) +#endif + +#ifndef EMS_Err_DCDC2_EMS_EEM_02_NO_DCDC2_error +#define EMS_Err_DCDC2_EMS_EEM_02_NO_DCDC2_error (0) +#endif + + +// Value tables for @EMS_stMode_DCDC2 signal + +#ifndef EMS_stMode_DCDC2_EMS_EEM_02_Buck_with_Drive_HV__LV +#define EMS_stMode_DCDC2_EMS_EEM_02_Buck_with_Drive_HV__LV (1) +#endif + +#ifndef EMS_stMode_DCDC2_EMS_EEM_02_Standby_communication_active +#define EMS_stMode_DCDC2_EMS_EEM_02_Standby_communication_active (0) +#endif + +// signal: @EMS_UtilRate_DCDC2_ro +#define CANDB_EMS_UtilRate_DCDC2_ro_CovFactor (0.1) +#define CANDB_EMS_UtilRate_DCDC2_ro_toS(x) ( (uint16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_EMS_UtilRate_DCDC2_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Actual current LV DC/DC2 + uint16_t EMS_ActCurrLV_DCDC2_ro; // Bits=16 Offset= -3276.7 Factor= 0.1 Unit:'A' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t EMS_ActCurrLV_DCDC2_phys; +#endif // CANDB_USE_SIGFLOAT + + // Actual voltage LV DC/DC1 + uint16_t EMS_ActVoltLV_DCDC2_ro; // Bits=10 Factor= 0.1 Unit:'V' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t EMS_ActVoltLV_DCDC2_phys; +#endif // CANDB_USE_SIGFLOAT + + // 1 : "Power limitation" + // 0 : "No power limitation" + uint8_t EMS_ErrPrfLim_DCDC2 : 1; // Bits= 1 + + // Error flag failure DC/DC2 (VDDC_bErrShOff2 or VDDC_bErrVltg2) + // 1 : "DCDC2 error" + // 0 : "NO DCDC2 error" + uint8_t EMS_Err_DCDC2 : 1; // Bits= 1 + + // Operating mode DC/DC2 + // 1 : "Buck with Drive (HV --> LV)" + // 0 : "Standby, communication active" + uint8_t EMS_stMode_DCDC2 : 1; // Bits= 1 + + // Utilization DC/DC2 + uint16_t EMS_UtilRate_DCDC2_ro; // Bits=10 Factor= 0.1 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t EMS_UtilRate_DCDC2_phys; +#endif // CANDB_USE_SIGFLOAT + + // Rolling Counter [0 - 15] + uint8_t EMS_EEM_02_RC : 4; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t EMS_EEM_02_CS; // Bits= 8 + +#else + + // Actual current LV DC/DC2 + uint16_t EMS_ActCurrLV_DCDC2_ro; // Bits=16 Offset= -3276.7 Factor= 0.1 Unit:'A' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t EMS_ActCurrLV_DCDC2_phys; +#endif // CANDB_USE_SIGFLOAT + + // Actual voltage LV DC/DC1 + uint16_t EMS_ActVoltLV_DCDC2_ro; // Bits=10 Factor= 0.1 Unit:'V' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t EMS_ActVoltLV_DCDC2_phys; +#endif // CANDB_USE_SIGFLOAT + + // 1 : "Power limitation" + // 0 : "No power limitation" + uint8_t EMS_ErrPrfLim_DCDC2; // Bits= 1 + + // Error flag failure DC/DC2 (VDDC_bErrShOff2 or VDDC_bErrVltg2) + // 1 : "DCDC2 error" + // 0 : "NO DCDC2 error" + uint8_t EMS_Err_DCDC2; // Bits= 1 + + // Operating mode DC/DC2 + // 1 : "Buck with Drive (HV --> LV)" + // 0 : "Standby, communication active" + uint8_t EMS_stMode_DCDC2; // Bits= 1 + + // Utilization DC/DC2 + uint16_t EMS_UtilRate_DCDC2_ro; // Bits=10 Factor= 0.1 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t EMS_UtilRate_DCDC2_phys; +#endif // CANDB_USE_SIGFLOAT + + // Rolling Counter [0 - 15] + uint8_t EMS_EEM_02_RC; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t EMS_EEM_02_CS; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} EMS_EEM_02_t; + +// def @BCM_EEM CAN Message (343 0x157) +#define BCM_EEM_IDE (0U) +#define BCM_EEM_DLC (8U) +#define BCM_EEM_CANID (0x157U) +#define BCM_EEM_CYC (100U) +// signal: @BCM_EEM_VolReqLV_DCDC1_ro +#define CANDB_BCM_EEM_VolReqLV_DCDC1_ro_CovFactor (0.1) +#define CANDB_BCM_EEM_VolReqLV_DCDC1_ro_toS(x) ( (uint16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_BCM_EEM_VolReqLV_DCDC1_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +// Value tables for @BCM_EEM_StPowMgn signal + +#ifndef BCM_EEM_StPowMgn_BCM_EEM_LVbattery_no_power_source +#define BCM_EEM_StPowMgn_BCM_EEM_LVbattery_no_power_source (5) +#endif + +#ifndef BCM_EEM_StPowMgn_BCM_EEM_LVbattery_discharging_fast +#define BCM_EEM_StPowMgn_BCM_EEM_LVbattery_discharging_fast (4) +#endif + +#ifndef BCM_EEM_StPowMgn_BCM_EEM_LVbattery_discharging_slow +#define BCM_EEM_StPowMgn_BCM_EEM_LVbattery_discharging_slow (3) +#endif + +#ifndef BCM_EEM_StPowMgn_BCM_EEM_LVbattery_not_charging +#define BCM_EEM_StPowMgn_BCM_EEM_LVbattery_not_charging (2) +#endif + +#ifndef BCM_EEM_StPowMgn_BCM_EEM_LVbattery_charging_slow +#define BCM_EEM_StPowMgn_BCM_EEM_LVbattery_charging_slow (1) +#endif + +#ifndef BCM_EEM_StPowMgn_BCM_EEM_LVbattery_charged +#define BCM_EEM_StPowMgn_BCM_EEM_LVbattery_charged (0) +#endif + +// signal: @BCM_EEM_VolReqLV_DCDC2_ro +#define CANDB_BCM_EEM_VolReqLV_DCDC2_ro_CovFactor (0.1) +#define CANDB_BCM_EEM_VolReqLV_DCDC2_ro_toS(x) ( (uint16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_BCM_EEM_VolReqLV_DCDC2_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @BCM_EEM_CurrLimLV_DCDC1_ro +#define CANDB_BCM_EEM_CurrLimLV_DCDC1_ro_CovFactor (0.1) +#define CANDB_BCM_EEM_CurrLimLV_DCDC1_ro_toS(x) ( (uint16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_BCM_EEM_CurrLimLV_DCDC1_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @BCM_EEM_CurrLimLV_DCDC2_ro +#define CANDB_BCM_EEM_CurrLimLV_DCDC2_ro_CovFactor (0.1) +#define CANDB_BCM_EEM_CurrLimLV_DCDC2_ro_toS(x) ( (uint16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_BCM_EEM_CurrLimLV_DCDC2_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Requested for voltage DC/DC_1 + uint16_t BCM_EEM_VolReqLV_DCDC1_ro; // Bits=10 Factor= 0.1 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_EEM_VolReqLV_DCDC1_phys; +#endif // CANDB_USE_SIGFLOAT + + // PM state for consumer deactivation + // 5 : "LV-battery no power source" + // 4 : "LV-battery discharging fast" + // 3 : "LV-battery discharging slow" + // 2 : "LV-battery not charging" + // 1 : "LV-battery charging slow" + // 0 : "LV-battery charged" + uint8_t BCM_EEM_StPowMgn : 3; // Bits= 3 + + // Output value of driver display request for Power Management + // The signal is not use in UMP 1.5. + uint8_t BCM_EEM_PowMngtReqDisp : 1; // Bits= 1 + + // Requested voltage DC/DC_2 + uint16_t BCM_EEM_VolReqLV_DCDC2_ro; // Bits=10 Factor= 0.1 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_EEM_VolReqLV_DCDC2_phys; +#endif // CANDB_USE_SIGFLOAT + + // Rolling Counter [0 - 15] + uint8_t BCM_EEM_RC : 4; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t BCM_EEM_CS; // Bits= 8 + + // Maximal current DC/DC_1 + uint16_t BCM_EEM_CurrLimLV_DCDC1_ro; // Bits=12 Factor= 0.1 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_EEM_CurrLimLV_DCDC1_phys; +#endif // CANDB_USE_SIGFLOAT + + // Maximal current DC/DC_2 + uint16_t BCM_EEM_CurrLimLV_DCDC2_ro; // Bits=12 Factor= 0.1 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_EEM_CurrLimLV_DCDC2_phys; +#endif // CANDB_USE_SIGFLOAT + +#else + + // Requested for voltage DC/DC_1 + uint16_t BCM_EEM_VolReqLV_DCDC1_ro; // Bits=10 Factor= 0.1 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_EEM_VolReqLV_DCDC1_phys; +#endif // CANDB_USE_SIGFLOAT + + // PM state for consumer deactivation + // 5 : "LV-battery no power source" + // 4 : "LV-battery discharging fast" + // 3 : "LV-battery discharging slow" + // 2 : "LV-battery not charging" + // 1 : "LV-battery charging slow" + // 0 : "LV-battery charged" + uint8_t BCM_EEM_StPowMgn; // Bits= 3 + + // Output value of driver display request for Power Management + // The signal is not use in UMP 1.5. + uint8_t BCM_EEM_PowMngtReqDisp; // Bits= 1 + + // Requested voltage DC/DC_2 + uint16_t BCM_EEM_VolReqLV_DCDC2_ro; // Bits=10 Factor= 0.1 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_EEM_VolReqLV_DCDC2_phys; +#endif // CANDB_USE_SIGFLOAT + + // Rolling Counter [0 - 15] + uint8_t BCM_EEM_RC; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t BCM_EEM_CS; // Bits= 8 + + // Maximal current DC/DC_1 + uint16_t BCM_EEM_CurrLimLV_DCDC1_ro; // Bits=12 Factor= 0.1 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_EEM_CurrLimLV_DCDC1_phys; +#endif // CANDB_USE_SIGFLOAT + + // Maximal current DC/DC_2 + uint16_t BCM_EEM_CurrLimLV_DCDC2_ro; // Bits=12 Factor= 0.1 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_EEM_CurrLimLV_DCDC2_phys; +#endif // CANDB_USE_SIGFLOAT + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} BCM_EEM_t; + +// def @DAS_01 CAN Message (352 0x160) +#define DAS_01_IDE (0U) +#define DAS_01_DLC (6U) +#define DAS_01_CANID (0x160U) +#define DAS_01_CYC (10U) +// signal: @DAS_CcAfsDecel_Req_ro +#define CANDB_DAS_CcAfsDecel_Req_ro_CovFactor (0.001) +#define CANDB_DAS_CcAfsDecel_Req_ro_toS(x) ( (uint16_t) (((x) - (-20.0)) / (0.001)) ) +#define CANDB_DAS_CcAfsDecel_Req_ro_fromS(x) ( (((x) * (0.001)) + (-20.0)) ) +// signal: @DAS_AebRdaDecel_Req_ro +#define CANDB_DAS_AebRdaDecel_Req_ro_CovFactor (0.001) +#define CANDB_DAS_AebRdaDecel_Req_ro_toS(x) ( (uint16_t) (((x) - (-20.0)) / (0.001)) ) +#define CANDB_DAS_AebRdaDecel_Req_ro_fromS(x) ( (((x) * (0.001)) + (-20.0)) ) + +// Value tables for @DAS_CcBrakeLight_Req signal + +#ifndef DAS_CcBrakeLight_Req_DAS_01_Requested +#define DAS_CcBrakeLight_Req_DAS_01_Requested (1) +#endif + +#ifndef DAS_CcBrakeLight_Req_DAS_01_Not_requested +#define DAS_CcBrakeLight_Req_DAS_01_Not_requested (0) +#endif + + +// Value tables for @DAS_AebBoost_Req signal + +#ifndef DAS_AebBoost_Req_DAS_01_Request +#define DAS_AebBoost_Req_DAS_01_Request (1) +#endif + +#ifndef DAS_AebBoost_Req_DAS_01_No_Request +#define DAS_AebBoost_Req_DAS_01_No_Request (0) +#endif + + +// Value tables for @DAS_AebPrefill_Req signal + +#ifndef DAS_AebPrefill_Req_DAS_01_Requested +#define DAS_AebPrefill_Req_DAS_01_Requested (1) +#endif + +#ifndef DAS_AebPrefill_Req_DAS_01_Not_Requested +#define DAS_AebPrefill_Req_DAS_01_Not_Requested (0) +#endif + + +// Value tables for @DAS_AebPreCrash_Req signal + +#ifndef DAS_AebPreCrash_Req_DAS_01_Requested +#define DAS_AebPreCrash_Req_DAS_01_Requested (1) +#endif + +#ifndef DAS_AebPreCrash_Req_DAS_01_Not_requested +#define DAS_AebPreCrash_Req_DAS_01_Not_requested (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Implement deceleration of CC + uint16_t DAS_CcAfsDecel_Req_ro; // Bits=16 Offset= -20.0 Factor= 0.001 Unit:'m/s^2' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t DAS_CcAfsDecel_Req_phys; +#endif // CANDB_USE_SIGFLOAT + + // Implement deceleration, ms^2 + uint16_t DAS_AebRdaDecel_Req_ro; // Bits=16 Offset= -20.0 Factor= 0.001 Unit:'m/s^2' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t DAS_AebRdaDecel_Req_phys; +#endif // CANDB_USE_SIGFLOAT + + // CC (Cruise Control) is requesting the brake light to be turned on + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_CcBrakeLight_Req : 1; // Bits= 1 + + // AEB (Automatic Emergency Braking) is requesting brake boost + // 1 : "Request" + // 0 : "No Request" + uint8_t DAS_AebBoost_Req : 1; // Bits= 1 + + // AEB is requesting brake prefill + // 1 : "Requested" + // 0 : "Not Requested" + uint8_t DAS_AebPrefill_Req : 1; // Bits= 1 + + // AEB is inform a potential accident + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_AebPreCrash_Req : 1; // Bits= 1 + + // Rolling Counter [0 - 15] + uint8_t DAS_01_RC : 4; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t DAS_01_CS; // Bits= 8 + +#else + + // Implement deceleration of CC + uint16_t DAS_CcAfsDecel_Req_ro; // Bits=16 Offset= -20.0 Factor= 0.001 Unit:'m/s^2' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t DAS_CcAfsDecel_Req_phys; +#endif // CANDB_USE_SIGFLOAT + + // Implement deceleration, ms^2 + uint16_t DAS_AebRdaDecel_Req_ro; // Bits=16 Offset= -20.0 Factor= 0.001 Unit:'m/s^2' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t DAS_AebRdaDecel_Req_phys; +#endif // CANDB_USE_SIGFLOAT + + // CC (Cruise Control) is requesting the brake light to be turned on + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_CcBrakeLight_Req; // Bits= 1 + + // AEB (Automatic Emergency Braking) is requesting brake boost + // 1 : "Request" + // 0 : "No Request" + uint8_t DAS_AebBoost_Req; // Bits= 1 + + // AEB is requesting brake prefill + // 1 : "Requested" + // 0 : "Not Requested" + uint8_t DAS_AebPrefill_Req; // Bits= 1 + + // AEB is inform a potential accident + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_AebPreCrash_Req; // Bits= 1 + + // Rolling Counter [0 - 15] + uint8_t DAS_01_RC; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t DAS_01_CS; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} DAS_01_t; + +// def @DAS_04 CAN Message (354 0x162) +#define DAS_04_IDE (0U) +#define DAS_04_DLC (4U) +#define DAS_04_CANID (0x162U) +#define DAS_04_CYC (10U) + +// Value tables for @DAS_CcDecelFlag_Req signal + +#ifndef DAS_CcDecelFlag_Req_DAS_04_Requested +#define DAS_CcDecelFlag_Req_DAS_04_Requested (1) +#endif + +#ifndef DAS_CcDecelFlag_Req_DAS_04_Not_requested +#define DAS_CcDecelFlag_Req_DAS_04_Not_requested (0) +#endif + + +// Value tables for @DAS_CcBrakeStandSt_Req signal + +#ifndef DAS_CcBrakeStandSt_Req_DAS_04_Requested +#define DAS_CcBrakeStandSt_Req_DAS_04_Requested (1) +#endif + +#ifndef DAS_CcBrakeStandSt_Req_DAS_04_Not_requested +#define DAS_CcBrakeStandSt_Req_DAS_04_Not_requested (0) +#endif + + +// Value tables for @DAS_CcMode_Stat signal + +#ifndef DAS_CcMode_Stat_DAS_04_Override +#define DAS_CcMode_Stat_DAS_04_Override (3) +#endif + +#ifndef DAS_CcMode_Stat_DAS_04_Active +#define DAS_CcMode_Stat_DAS_04_Active (2) +#endif + +#ifndef DAS_CcMode_Stat_DAS_04_Standby +#define DAS_CcMode_Stat_DAS_04_Standby (1) +#endif + +#ifndef DAS_CcMode_Stat_DAS_04_Off +#define DAS_CcMode_Stat_DAS_04_Off (0) +#endif + + +// Value tables for @DAS_AfsBrakeJerkEnab_Stat signal + +#ifndef DAS_AfsBrakeJerkEnab_Stat_DAS_04_Enable +#define DAS_AfsBrakeJerkEnab_Stat_DAS_04_Enable (1) +#endif + +#ifndef DAS_AfsBrakeJerkEnab_Stat_DAS_04_Disable +#define DAS_AfsBrakeJerkEnab_Stat_DAS_04_Disable (0) +#endif + + +// Value tables for @DAS_AfsBrakeJerk_Req signal + +#ifndef DAS_AfsBrakeJerk_Req_DAS_04_Requested +#define DAS_AfsBrakeJerk_Req_DAS_04_Requested (1) +#endif + +#ifndef DAS_AfsBrakeJerk_Req_DAS_04_Not_requested +#define DAS_AfsBrakeJerk_Req_DAS_04_Not_requested (0) +#endif + + +// Value tables for @DAS_CcBrakeRelease_Req signal + +#ifndef DAS_CcBrakeRelease_Req_DAS_04_Requested +#define DAS_CcBrakeRelease_Req_DAS_04_Requested (1) +#endif + +#ifndef DAS_CcBrakeRelease_Req_DAS_04_Not_requsted +#define DAS_CcBrakeRelease_Req_DAS_04_Not_requsted (0) +#endif + + +// Value tables for @DAS_AebMode_Stat signal + +#ifndef DAS_AebMode_Stat_DAS_04_Active +#define DAS_AebMode_Stat_DAS_04_Active (1) +#endif + +#ifndef DAS_AebMode_Stat_DAS_04_Off +#define DAS_AebMode_Stat_DAS_04_Off (0) +#endif + + +// Value tables for @DAS_AebDecelFlag_Req signal + +#ifndef DAS_AebDecelFlag_Req_DAS_04_Requested +#define DAS_AebDecelFlag_Req_DAS_04_Requested (1) +#endif + +#ifndef DAS_AebDecelFlag_Req_DAS_04_Not_requsted +#define DAS_AebDecelFlag_Req_DAS_04_Not_requsted (0) +#endif + + +// Value tables for @DAS_CcFuncError_Stat signal + +#ifndef DAS_CcFuncError_Stat_DAS_04_Error +#define DAS_CcFuncError_Stat_DAS_04_Error (1) +#endif + +#ifndef DAS_CcFuncError_Stat_DAS_04_No_error +#define DAS_CcFuncError_Stat_DAS_04_No_error (0) +#endif + + +// Value tables for @DAS_AebRdaStand_Req signal + +#ifndef DAS_AebRdaStand_Req_DAS_04_Requested +#define DAS_AebRdaStand_Req_DAS_04_Requested (1) +#endif + +#ifndef DAS_AebRdaStand_Req_DAS_04_Not_requested +#define DAS_AebRdaStand_Req_DAS_04_Not_requested (0) +#endif + + +// Value tables for @DAS_AebFuncError_Stat signal + +#ifndef DAS_AebFuncError_Stat_DAS_04_Error +#define DAS_AebFuncError_Stat_DAS_04_Error (1) +#endif + +#ifndef DAS_AebFuncError_Stat_DAS_04_No_error +#define DAS_AebFuncError_Stat_DAS_04_No_error (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Indicates strength of Brake Jerk warning level requested by AFS + uint8_t DAS_AfsBrakeJerkLvl_Stat; // Bits= 8 + + // Cruise is requesting to implement deceleration + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_CcDecelFlag_Req : 1; // Bits= 1 + + // Cruise is requesting a car hold + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_CcBrakeStandSt_Req : 1; // Bits= 1 + + // Mode of CC + // 3 : "Override" + // 2 : "Active" + // 1 : "Standby" + // 0 : "Off" + uint8_t DAS_CcMode_Stat : 2; // Bits= 2 + + // Enable the brake jerk warning functionnality + // 1 : "Enable" + // 0 : "Disable" + uint8_t DAS_AfsBrakeJerkEnab_Stat : 1; // Bits= 1 + + // AFS requests a brake jerk to warn the driver in a hazardous situation + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_AfsBrakeJerk_Req : 1; // Bits= 1 + + // Cruise is requesting to start the car + // 1 : "Requested" + // 0 : "Not requsted" + uint8_t DAS_CcBrakeRelease_Req : 1; // Bits= 1 + + // Mode of emergency braking + // 1 : "Active" + // 0 : "Off" + uint8_t DAS_AebMode_Stat : 1; // Bits= 1 + + // AEB is requesting to implement deceleration + // 1 : "Requested" + // 0 : "Not requsted" + uint8_t DAS_AebDecelFlag_Req : 1; // Bits= 1 + + // Error symbol of CC + // 1 : "Error" + // 0 : "No error" + uint8_t DAS_CcFuncError_Stat : 1; // Bits= 1 + + // AEB or RDA is requestin enable HOLD + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_AebRdaStand_Req : 1; // Bits= 1 + + // Error symbol of AEB + // 1 : "Error" + // 0 : "No error" + uint8_t DAS_AebFuncError_Stat : 1; // Bits= 1 + + // Rolling Counter [0 - 15] + uint8_t DAS_04_RC : 4; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t DAS_04_CS; // Bits= 8 + +#else + + // Indicates strength of Brake Jerk warning level requested by AFS + uint8_t DAS_AfsBrakeJerkLvl_Stat; // Bits= 8 + + // Cruise is requesting to implement deceleration + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_CcDecelFlag_Req; // Bits= 1 + + // Cruise is requesting a car hold + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_CcBrakeStandSt_Req; // Bits= 1 + + // Mode of CC + // 3 : "Override" + // 2 : "Active" + // 1 : "Standby" + // 0 : "Off" + uint8_t DAS_CcMode_Stat; // Bits= 2 + + // Enable the brake jerk warning functionnality + // 1 : "Enable" + // 0 : "Disable" + uint8_t DAS_AfsBrakeJerkEnab_Stat; // Bits= 1 + + // AFS requests a brake jerk to warn the driver in a hazardous situation + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_AfsBrakeJerk_Req; // Bits= 1 + + // Cruise is requesting to start the car + // 1 : "Requested" + // 0 : "Not requsted" + uint8_t DAS_CcBrakeRelease_Req; // Bits= 1 + + // Mode of emergency braking + // 1 : "Active" + // 0 : "Off" + uint8_t DAS_AebMode_Stat; // Bits= 1 + + // AEB is requesting to implement deceleration + // 1 : "Requested" + // 0 : "Not requsted" + uint8_t DAS_AebDecelFlag_Req; // Bits= 1 + + // Error symbol of CC + // 1 : "Error" + // 0 : "No error" + uint8_t DAS_CcFuncError_Stat; // Bits= 1 + + // AEB or RDA is requestin enable HOLD + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_AebRdaStand_Req; // Bits= 1 + + // Error symbol of AEB + // 1 : "Error" + // 0 : "No error" + uint8_t DAS_AebFuncError_Stat; // Bits= 1 + + // Rolling Counter [0 - 15] + uint8_t DAS_04_RC; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t DAS_04_CS; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} DAS_04_t; + +// def @VCU_DriveInfo CAN Message (394 0x18a) +#define VCU_DriveInfo_IDE (0U) +#define VCU_DriveInfo_DLC (8U) +#define VCU_DriveInfo_CANID (0x18aU) +#define VCU_DriveInfo_CYC (100U) + +// Value tables for @VCU_SpecBut_Stat signal + +#ifndef VCU_SpecBut_Stat_VCU_DriveInfo_Reserved +#define VCU_SpecBut_Stat_VCU_DriveInfo_Reserved (3) +#endif + +#ifndef VCU_SpecBut_Stat_VCU_DriveInfo_Not_installed +#define VCU_SpecBut_Stat_VCU_DriveInfo_Not_installed (2) +#endif + +#ifndef VCU_SpecBut_Stat_VCU_DriveInfo_Pressed +#define VCU_SpecBut_Stat_VCU_DriveInfo_Pressed (1) +#endif + +#ifndef VCU_SpecBut_Stat_VCU_DriveInfo_Not_pressed +#define VCU_SpecBut_Stat_VCU_DriveInfo_Not_pressed (0) +#endif + + +// Value tables for @VCU_Fault_Stat signal + +#ifndef VCU_Fault_Stat_VCU_DriveInfo_Error +#define VCU_Fault_Stat_VCU_DriveInfo_Error (1) +#endif + +#ifndef VCU_Fault_Stat_VCU_DriveInfo_No_error +#define VCU_Fault_Stat_VCU_DriveInfo_No_error (0) +#endif + +// signal: @VCU_OverallActMotTrq_Val_ro +#define CANDB_VCU_OverallActMotTrq_Val_ro_CovFactor (0.25) +#define CANDB_VCU_OverallActMotTrq_Val_ro_toS(x) ( (uint16_t) (((x) - (-1533.0)) / (0.25)) ) +#define CANDB_VCU_OverallActMotTrq_Val_ro_fromS(x) ( (((x) * (0.25)) + (-1533.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Special button status + // 3 : "Reserved" + // 2 : "Not installed" + // 1 : "Pressed" + // 0 : "Not pressed" + uint8_t VCU_SpecBut_Stat : 2; // Bits= 2 + + // VCU fault status flag + // 1 : "Error" + // 0 : "No error" + uint8_t VCU_Fault_Stat : 1; // Bits= 1 + + // Total actual torque delivered by driving e-machines (for 2 and 3 motor configurations) + uint16_t VCU_OverallActMotTrq_Val_ro; // Bits=16 Offset= -1533.0 Factor= 0.25 Unit:'Nm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t VCU_OverallActMotTrq_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Rolling Counter [0 - 15] + uint8_t VCU_DriveInfo_RC : 4; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t VCU_DriveInfo_CS; // Bits= 8 + +#else + + // Special button status + // 3 : "Reserved" + // 2 : "Not installed" + // 1 : "Pressed" + // 0 : "Not pressed" + uint8_t VCU_SpecBut_Stat; // Bits= 2 + + // VCU fault status flag + // 1 : "Error" + // 0 : "No error" + uint8_t VCU_Fault_Stat; // Bits= 1 + + // Total actual torque delivered by driving e-machines (for 2 and 3 motor configurations) + uint16_t VCU_OverallActMotTrq_Val_ro; // Bits=16 Offset= -1533.0 Factor= 0.25 Unit:'Nm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t VCU_OverallActMotTrq_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Rolling Counter [0 - 15] + uint8_t VCU_DriveInfo_RC; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t VCU_DriveInfo_CS; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} VCU_DriveInfo_t; + +// def @DAS_02 CAN Message (522 0x20a) +#define DAS_02_IDE (0U) +#define DAS_02_DLC (8U) +#define DAS_02_CANID (0x20aU) +#define DAS_02_CYC (50U) + +// Value tables for @DAS_LkaAngleFlag_Req signal + +#ifndef DAS_LkaAngleFlag_Req_DAS_02_Requested +#define DAS_LkaAngleFlag_Req_DAS_02_Requested (1) +#endif + +#ifndef DAS_LkaAngleFlag_Req_DAS_02_Not_requested +#define DAS_LkaAngleFlag_Req_DAS_02_Not_requested (0) +#endif + + +// Value tables for @DAS_AfsMode_Stat signal + +#ifndef DAS_AfsMode_Stat_DAS_02_Active +#define DAS_AfsMode_Stat_DAS_02_Active (1) +#endif + +#ifndef DAS_AfsMode_Stat_DAS_02_Off +#define DAS_AfsMode_Stat_DAS_02_Off (0) +#endif + + +// Value tables for @DAS_AfsDecelFlag_Req signal + +#ifndef DAS_AfsDecelFlag_Req_DAS_02_Requested +#define DAS_AfsDecelFlag_Req_DAS_02_Requested (1) +#endif + +#ifndef DAS_AfsDecelFlag_Req_DAS_02_Not_requested +#define DAS_AfsDecelFlag_Req_DAS_02_Not_requested (0) +#endif + + +// Value tables for @DAS_AfsFuncError_Stat signal + +#ifndef DAS_AfsFuncError_Stat_DAS_02_Error +#define DAS_AfsFuncError_Stat_DAS_02_Error (1) +#endif + +#ifndef DAS_AfsFuncError_Stat_DAS_02_No_error +#define DAS_AfsFuncError_Stat_DAS_02_No_error (0) +#endif + + +// Value tables for @DAS_AfsExecute_Req signal + +#ifndef DAS_AfsExecute_Req_DAS_02_Requested +#define DAS_AfsExecute_Req_DAS_02_Requested (1) +#endif + +#ifndef DAS_AfsExecute_Req_DAS_02_Not_requested +#define DAS_AfsExecute_Req_DAS_02_Not_requested (0) +#endif + + +// Value tables for @DAS_AfsSos_Req signal + +#ifndef DAS_AfsSos_Req_DAS_02_Requested +#define DAS_AfsSos_Req_DAS_02_Requested (1) +#endif + +#ifndef DAS_AfsSos_Req_DAS_02_Not_requested +#define DAS_AfsSos_Req_DAS_02_Not_requested (0) +#endif + + +// Value tables for @DAS_AfsEpb_Req signal + +#ifndef DAS_AfsEpb_Req_DAS_02_Requested +#define DAS_AfsEpb_Req_DAS_02_Requested (1) +#endif + +#ifndef DAS_AfsEpb_Req_DAS_02_Not_requested +#define DAS_AfsEpb_Req_DAS_02_Not_requested (0) +#endif + + +// Value tables for @DAS_RdaMode_Stat signal + +#ifndef DAS_RdaMode_Stat_DAS_02_On +#define DAS_RdaMode_Stat_DAS_02_On (1) +#endif + +#ifndef DAS_RdaMode_Stat_DAS_02_Off +#define DAS_RdaMode_Stat_DAS_02_Off (0) +#endif + + +// Value tables for @DAS_RdaDecelFlag_Req signal + +#ifndef DAS_RdaDecelFlag_Req_DAS_02_Requested +#define DAS_RdaDecelFlag_Req_DAS_02_Requested (1) +#endif + +#ifndef DAS_RdaDecelFlag_Req_DAS_02_Not_requested +#define DAS_RdaDecelFlag_Req_DAS_02_Not_requested (0) +#endif + + +// Value tables for @DAS_RdaFuncError_Stat signal + +#ifndef DAS_RdaFuncError_Stat_DAS_02_Error +#define DAS_RdaFuncError_Stat_DAS_02_Error (1) +#endif + +#ifndef DAS_RdaFuncError_Stat_DAS_02_No_error +#define DAS_RdaFuncError_Stat_DAS_02_No_error (0) +#endif + + +// Value tables for @DAS_LkaMode_Stat signal + +#ifndef DAS_LkaMode_Stat_DAS_02_ActiveTakeOver +#define DAS_LkaMode_Stat_DAS_02_ActiveTakeOver (3) +#endif + +#ifndef DAS_LkaMode_Stat_DAS_02_Active +#define DAS_LkaMode_Stat_DAS_02_Active (2) +#endif + +#ifndef DAS_LkaMode_Stat_DAS_02_Standby +#define DAS_LkaMode_Stat_DAS_02_Standby (1) +#endif + +#ifndef DAS_LkaMode_Stat_DAS_02_Off +#define DAS_LkaMode_Stat_DAS_02_Off (0) +#endif + + +// Value tables for @DAS_LkaFuncError_Stat signal + +#ifndef DAS_LkaFuncError_Stat_DAS_02_Error +#define DAS_LkaFuncError_Stat_DAS_02_Error (1) +#endif + +#ifndef DAS_LkaFuncError_Stat_DAS_02_No_error +#define DAS_LkaFuncError_Stat_DAS_02_No_error (0) +#endif + + +// Value tables for @DAS_LdpAngleFlag_Req signal + +#ifndef DAS_LdpAngleFlag_Req_DAS_02_Requsted +#define DAS_LdpAngleFlag_Req_DAS_02_Requsted (1) +#endif + +#ifndef DAS_LdpAngleFlag_Req_DAS_02_Not_requested +#define DAS_LdpAngleFlag_Req_DAS_02_Not_requested (0) +#endif + + +// Value tables for @DAS_LdpMode_Stat signal + +#ifndef DAS_LdpMode_Stat_DAS_02_Active +#define DAS_LdpMode_Stat_DAS_02_Active (1) +#endif + +#ifndef DAS_LdpMode_Stat_DAS_02_Off +#define DAS_LdpMode_Stat_DAS_02_Off (0) +#endif + + +// Value tables for @DAS_LdwFuncError_Stat signal + +#ifndef DAS_LdwFuncError_Stat_DAS_02_Error +#define DAS_LdwFuncError_Stat_DAS_02_Error (1) +#endif + +#ifndef DAS_LdwFuncError_Stat_DAS_02_No_error +#define DAS_LdwFuncError_Stat_DAS_02_No_error (0) +#endif + + +// Value tables for @DAS_AlccAngleFlag_Req signal + +#ifndef DAS_AlccAngleFlag_Req_DAS_02_Requested +#define DAS_AlccAngleFlag_Req_DAS_02_Requested (1) +#endif + +#ifndef DAS_AlccAngleFlag_Req_DAS_02_Not_requsted +#define DAS_AlccAngleFlag_Req_DAS_02_Not_requsted (0) +#endif + + +// Value tables for @DAS_AlccMode_Stat signal + +#ifndef DAS_AlccMode_Stat_DAS_02_Active +#define DAS_AlccMode_Stat_DAS_02_Active (1) +#endif + +#ifndef DAS_AlccMode_Stat_DAS_02_Off +#define DAS_AlccMode_Stat_DAS_02_Off (0) +#endif + + +// Value tables for @DAS_LccFuncError_Stat signal + +#ifndef DAS_LccFuncError_Stat_DAS_02_Error +#define DAS_LccFuncError_Stat_DAS_02_Error (1) +#endif + +#ifndef DAS_LccFuncError_Stat_DAS_02_No_error +#define DAS_LccFuncError_Stat_DAS_02_No_error (0) +#endif + + +// Value tables for @DAS_ApaAngleFlag_Req signal + +#ifndef DAS_ApaAngleFlag_Req_DAS_02_Requested +#define DAS_ApaAngleFlag_Req_DAS_02_Requested (1) +#endif + +#ifndef DAS_ApaAngleFlag_Req_DAS_02_Not_requested +#define DAS_ApaAngleFlag_Req_DAS_02_Not_requested (0) +#endif + + +// Value tables for @DAS_LkaSteeringMode_Stat signal + +#ifndef DAS_LkaSteeringMode_Stat_DAS_02_Active +#define DAS_LkaSteeringMode_Stat_DAS_02_Active (1) +#endif + +#ifndef DAS_LkaSteeringMode_Stat_DAS_02_Inactive +#define DAS_LkaSteeringMode_Stat_DAS_02_Inactive (0) +#endif + + +// Value tables for @DAS_AfsNotifError_Req signal + +#ifndef DAS_AfsNotifError_Req_DAS_02_Error +#define DAS_AfsNotifError_Req_DAS_02_Error (1) +#endif + +#ifndef DAS_AfsNotifError_Req_DAS_02_No_error +#define DAS_AfsNotifError_Req_DAS_02_No_error (0) +#endif + + +// Value tables for @DAS_RctcMode_Stat signal + +#ifndef DAS_RctcMode_Stat_DAS_02_Active +#define DAS_RctcMode_Stat_DAS_02_Active (1) +#endif + +#ifndef DAS_RctcMode_Stat_DAS_02_Off +#define DAS_RctcMode_Stat_DAS_02_Off (0) +#endif + + +// Value tables for @DAS_RctcDecelFlag_Req signal + +#ifndef DAS_RctcDecelFlag_Req_DAS_02_Request +#define DAS_RctcDecelFlag_Req_DAS_02_Request (1) +#endif + +#ifndef DAS_RctcDecelFlag_Req_DAS_02_Not_request +#define DAS_RctcDecelFlag_Req_DAS_02_Not_request (0) +#endif + + +// Value tables for @DAS_RctcFuncError_Stat signal + +#ifndef DAS_RctcFuncError_Stat_DAS_02_Error +#define DAS_RctcFuncError_Stat_DAS_02_Error (1) +#endif + +#ifndef DAS_RctcFuncError_Stat_DAS_02_No_error +#define DAS_RctcFuncError_Stat_DAS_02_No_error (0) +#endif + + +// Value tables for @DAS_RctcNotifError_Req signal + +#ifndef DAS_RctcNotifError_Req_DAS_02_Error +#define DAS_RctcNotifError_Req_DAS_02_Error (1) +#endif + +#ifndef DAS_RctcNotifError_Req_DAS_02_No_error +#define DAS_RctcNotifError_Req_DAS_02_No_error (0) +#endif + + +// Value tables for @DAS_AccFuncError_Stat signal + +#ifndef DAS_AccFuncError_Stat_DAS_02_Error +#define DAS_AccFuncError_Stat_DAS_02_Error (1) +#endif + +#ifndef DAS_AccFuncError_Stat_DAS_02_No_error +#define DAS_AccFuncError_Stat_DAS_02_No_error (0) +#endif + + +// Value tables for @DAS_APAMode_Stat signal + +#ifndef DAS_APAMode_Stat_DAS_02_Move +#define DAS_APAMode_Stat_DAS_02_Move (1) +#endif + +#ifndef DAS_APAMode_Stat_DAS_02_Not_move +#define DAS_APAMode_Stat_DAS_02_Not_move (0) +#endif + + +// Value tables for @DAS_ApaFuncError_Stat signal + +#ifndef DAS_ApaFuncError_Stat_DAS_02_Error +#define DAS_ApaFuncError_Stat_DAS_02_Error (1) +#endif + +#ifndef DAS_ApaFuncError_Stat_DAS_02_No_Error +#define DAS_ApaFuncError_Stat_DAS_02_No_Error (0) +#endif + +// signal: @DAS_LkaAngle_Req_ro +#define CANDB_DAS_LkaAngle_Req_ro_CovFactor (0.1) +#define CANDB_DAS_LkaAngle_Req_ro_toS(x) ( (uint16_t) (((x) - (-819.1)) / (0.1)) ) +#define CANDB_DAS_LkaAngle_Req_ro_fromS(x) ( (((x) * (0.1)) + (-819.1)) ) + +// Value tables for @DAS_RsaAngleDirection_Req signal + +#ifndef DAS_RsaAngleDirection_Req_DAS_02_Same_direction +#define DAS_RsaAngleDirection_Req_DAS_02_Same_direction (3) +#endif + +#ifndef DAS_RsaAngleDirection_Req_DAS_02_Opposite_direction +#define DAS_RsaAngleDirection_Req_DAS_02_Opposite_direction (2) +#endif + +#ifndef DAS_RsaAngleDirection_Req_DAS_02_Zero_position +#define DAS_RsaAngleDirection_Req_DAS_02_Zero_position (1) +#endif + +#ifndef DAS_RsaAngleDirection_Req_DAS_02_No_request +#define DAS_RsaAngleDirection_Req_DAS_02_No_request (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // LKA (Lane Keeping Assist) is requesting to implement angle on steering wheel + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_LkaAngleFlag_Req : 1; // Bits= 1 + + // Mode of AFS + // 1 : "Active" + // 0 : "Off" + uint8_t DAS_AfsMode_Stat : 1; // Bits= 1 + + // AFS (Automatic forced stop) is requesting to implement deceleration + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_AfsDecelFlag_Req : 1; // Bits= 1 + + // Error of AFS + // 1 : "Error" + // 0 : "No error" + uint8_t DAS_AfsFuncError_Stat : 1; // Bits= 1 + + // AFS is requesting open door and emergency lights + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_AfsExecute_Req : 1; // Bits= 1 + + // AFS is requesting call SOS + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_AfsSos_Req : 1; // Bits= 1 + + // AFS is requesting apply the parking brake + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_AfsEpb_Req : 1; // Bits= 1 + + // Mode of RDA (Reverse driving assist) + // 1 : "On" + // 0 : "Off" + uint8_t DAS_RdaMode_Stat : 1; // Bits= 1 + + // RDA is requesting to implement deceleration + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_RdaDecelFlag_Req : 1; // Bits= 1 + + // Error of RDA + // 1 : "Error" + // 0 : "No error" + uint8_t DAS_RdaFuncError_Stat : 1; // Bits= 1 + + // Mode of LKA + // 3 : "Active+TakeOver" + // 2 : "Active" + // 1 : "Standby" + // 0 : "Off" + uint8_t DAS_LkaMode_Stat : 2; // Bits= 2 + + // Error symbol of LKA + // 1 : "Error" + // 0 : "No error" + uint8_t DAS_LkaFuncError_Stat : 1; // Bits= 1 + + // LDP is requesting to implement angle on steering wheel + // 1 : "Requsted" + // 0 : "Not requested" + uint8_t DAS_LdpAngleFlag_Req : 1; // Bits= 1 + + // Mode of LDP (Lane Departure Prevention) + // 1 : "Active" + // 0 : "Off" + uint8_t DAS_LdpMode_Stat : 1; // Bits= 1 + + // Error symbol of LDW (Lane Departure Warning) + // 1 : "Error" + // 0 : "No error" + uint8_t DAS_LdwFuncError_Stat : 1; // Bits= 1 + + // ALCC is requesting to implement angle on steering wheel + // 1 : "Requested" + // 0 : "Not requsted" + uint8_t DAS_AlccAngleFlag_Req : 1; // Bits= 1 + + // Mode of ALCC (Active Lane Change Control) + // 1 : "Active" + // 0 : "Off" + uint8_t DAS_AlccMode_Stat : 1; // Bits= 1 + + // Error symbol of LCC (Lane Change Control) + // 1 : "Error" + // 0 : "No error" + uint8_t DAS_LccFuncError_Stat : 1; // Bits= 1 + + // APA is requesting to implement angle on steering wheel + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_ApaAngleFlag_Req : 1; // Bits= 1 + + // LKA mode for RSA + // 1 : "Active" + // 0 : "Inactive" + uint8_t DAS_LkaSteeringMode_Stat : 1; // Bits= 1 + + // Error notification of AFS + // 1 : "Error" + // 0 : "No error" + uint8_t DAS_AfsNotifError_Req : 1; // Bits= 1 + + // Mode of RDA + // 1 : "Active" + // 0 : "Off" + uint8_t DAS_RctcMode_Stat : 1; // Bits= 1 + + // RCTC is requesting to implement deceleration + // 1 : "Request" + // 0 : "Not request" + uint8_t DAS_RctcDecelFlag_Req : 1; // Bits= 1 + + // Error of RCTC (Rear Cross Traffic Control) + // 1 : "Error" + // 0 : "No error" + uint8_t DAS_RctcFuncError_Stat : 1; // Bits= 1 + + // Error notification of RCTC + // 1 : "Error" + // 0 : "No error" + uint8_t DAS_RctcNotifError_Req : 1; // Bits= 1 + + // Error symbol of ACC (Adaptive Cruise Control) + // 1 : "Error" + // 0 : "No error" + uint8_t DAS_AccFuncError_Stat : 1; // Bits= 1 + + // Mode of APA + // 1 : "Move" + // 0 : "Not move" + uint8_t DAS_APAMode_Stat : 1; // Bits= 1 + + // Error of APA + // 1 : "Error" + // 0 : "No Error" + uint8_t DAS_ApaFuncError_Stat : 1; // Bits= 1 + + // Angle request + uint16_t DAS_LkaAngle_Req_ro; // Bits=14 Offset= -819.1 Factor= 0.1 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t DAS_LkaAngle_Req_phys; +#endif // CANDB_USE_SIGFLOAT + + // Rear steering actuator mode request + // 3 : "Same direction" + // 2 : "Opposite direction" + // 1 : "Zero position" + // 0 : "No request" + uint8_t DAS_RsaAngleDirection_Req : 2; // Bits= 2 + + // Rolling Counter [0 - 15] + uint8_t DAS_02_RC : 4; // Bits= 4 + + // Checksum XOR8 of the data field this message + // Checksum computed as per XOR algorithm: + // Byte 1 XOR byte 2 .... XOR byte n-1. (n = packet length.) + uint8_t DAS_02_CS; // Bits= 8 + +#else + + // LKA (Lane Keeping Assist) is requesting to implement angle on steering wheel + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_LkaAngleFlag_Req; // Bits= 1 + + // Mode of AFS + // 1 : "Active" + // 0 : "Off" + uint8_t DAS_AfsMode_Stat; // Bits= 1 + + // AFS (Automatic forced stop) is requesting to implement deceleration + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_AfsDecelFlag_Req; // Bits= 1 + + // Error of AFS + // 1 : "Error" + // 0 : "No error" + uint8_t DAS_AfsFuncError_Stat; // Bits= 1 + + // AFS is requesting open door and emergency lights + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_AfsExecute_Req; // Bits= 1 + + // AFS is requesting call SOS + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_AfsSos_Req; // Bits= 1 + + // AFS is requesting apply the parking brake + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_AfsEpb_Req; // Bits= 1 + + // Mode of RDA (Reverse driving assist) + // 1 : "On" + // 0 : "Off" + uint8_t DAS_RdaMode_Stat; // Bits= 1 + + // RDA is requesting to implement deceleration + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_RdaDecelFlag_Req; // Bits= 1 + + // Error of RDA + // 1 : "Error" + // 0 : "No error" + uint8_t DAS_RdaFuncError_Stat; // Bits= 1 + + // Mode of LKA + // 3 : "Active+TakeOver" + // 2 : "Active" + // 1 : "Standby" + // 0 : "Off" + uint8_t DAS_LkaMode_Stat; // Bits= 2 + + // Error symbol of LKA + // 1 : "Error" + // 0 : "No error" + uint8_t DAS_LkaFuncError_Stat; // Bits= 1 + + // LDP is requesting to implement angle on steering wheel + // 1 : "Requsted" + // 0 : "Not requested" + uint8_t DAS_LdpAngleFlag_Req; // Bits= 1 + + // Mode of LDP (Lane Departure Prevention) + // 1 : "Active" + // 0 : "Off" + uint8_t DAS_LdpMode_Stat; // Bits= 1 + + // Error symbol of LDW (Lane Departure Warning) + // 1 : "Error" + // 0 : "No error" + uint8_t DAS_LdwFuncError_Stat; // Bits= 1 + + // ALCC is requesting to implement angle on steering wheel + // 1 : "Requested" + // 0 : "Not requsted" + uint8_t DAS_AlccAngleFlag_Req; // Bits= 1 + + // Mode of ALCC (Active Lane Change Control) + // 1 : "Active" + // 0 : "Off" + uint8_t DAS_AlccMode_Stat; // Bits= 1 + + // Error symbol of LCC (Lane Change Control) + // 1 : "Error" + // 0 : "No error" + uint8_t DAS_LccFuncError_Stat; // Bits= 1 + + // APA is requesting to implement angle on steering wheel + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_ApaAngleFlag_Req; // Bits= 1 + + // LKA mode for RSA + // 1 : "Active" + // 0 : "Inactive" + uint8_t DAS_LkaSteeringMode_Stat; // Bits= 1 + + // Error notification of AFS + // 1 : "Error" + // 0 : "No error" + uint8_t DAS_AfsNotifError_Req; // Bits= 1 + + // Mode of RDA + // 1 : "Active" + // 0 : "Off" + uint8_t DAS_RctcMode_Stat; // Bits= 1 + + // RCTC is requesting to implement deceleration + // 1 : "Request" + // 0 : "Not request" + uint8_t DAS_RctcDecelFlag_Req; // Bits= 1 + + // Error of RCTC (Rear Cross Traffic Control) + // 1 : "Error" + // 0 : "No error" + uint8_t DAS_RctcFuncError_Stat; // Bits= 1 + + // Error notification of RCTC + // 1 : "Error" + // 0 : "No error" + uint8_t DAS_RctcNotifError_Req; // Bits= 1 + + // Error symbol of ACC (Adaptive Cruise Control) + // 1 : "Error" + // 0 : "No error" + uint8_t DAS_AccFuncError_Stat; // Bits= 1 + + // Mode of APA + // 1 : "Move" + // 0 : "Not move" + uint8_t DAS_APAMode_Stat; // Bits= 1 + + // Error of APA + // 1 : "Error" + // 0 : "No Error" + uint8_t DAS_ApaFuncError_Stat; // Bits= 1 + + // Angle request + uint16_t DAS_LkaAngle_Req_ro; // Bits=14 Offset= -819.1 Factor= 0.1 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t DAS_LkaAngle_Req_phys; +#endif // CANDB_USE_SIGFLOAT + + // Rear steering actuator mode request + // 3 : "Same direction" + // 2 : "Opposite direction" + // 1 : "Zero position" + // 0 : "No request" + uint8_t DAS_RsaAngleDirection_Req; // Bits= 2 + + // Rolling Counter [0 - 15] + uint8_t DAS_02_RC; // Bits= 4 + + // Checksum XOR8 of the data field this message + // Checksum computed as per XOR algorithm: + // Byte 1 XOR byte 2 .... XOR byte n-1. (n = packet length.) + uint8_t DAS_02_CS; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} DAS_02_t; + +// def @DAS_07 CAN Message (523 0x20b) +#define DAS_07_IDE (0U) +#define DAS_07_DLC (6U) +#define DAS_07_CANID (0x20bU) +#define DAS_07_CYC (100U) + +// Value tables for @DAS_LkaWarnSound_Req signal + +#ifndef DAS_LkaWarnSound_Req_DAS_07_Requested +#define DAS_LkaWarnSound_Req_DAS_07_Requested (1) +#endif + +#ifndef DAS_LkaWarnSound_Req_DAS_07_Not_requested +#define DAS_LkaWarnSound_Req_DAS_07_Not_requested (0) +#endif + + +// Value tables for @DAS_LkaShootdownSound_Req signal + +#ifndef DAS_LkaShootdownSound_Req_DAS_07_Requested +#define DAS_LkaShootdownSound_Req_DAS_07_Requested (1) +#endif + +#ifndef DAS_LkaShootdownSound_Req_DAS_07_Not_requested +#define DAS_LkaShootdownSound_Req_DAS_07_Not_requested (0) +#endif + + +// Value tables for @DAS_LkaWarnNotif_Req signal + +#ifndef DAS_LkaWarnNotif_Req_DAS_07_Requested +#define DAS_LkaWarnNotif_Req_DAS_07_Requested (1) +#endif + +#ifndef DAS_LkaWarnNotif_Req_DAS_07_Not_requested +#define DAS_LkaWarnNotif_Req_DAS_07_Not_requested (0) +#endif + + +// Value tables for @DAS_LkaNotifError_Req signal + +#ifndef DAS_LkaNotifError_Req_DAS_07_Error +#define DAS_LkaNotifError_Req_DAS_07_Error (1) +#endif + +#ifndef DAS_LkaNotifError_Req_DAS_07_No_error +#define DAS_LkaNotifError_Req_DAS_07_No_error (0) +#endif + + +// Value tables for @DAS_RdaWarn_Req signal + +#ifndef DAS_RdaWarn_Req_DAS_07_Requested +#define DAS_RdaWarn_Req_DAS_07_Requested (1) +#endif + +#ifndef DAS_RdaWarn_Req_DAS_07_Not_requested +#define DAS_RdaWarn_Req_DAS_07_Not_requested (0) +#endif + + +// Value tables for @DAS_RctcWarn_Req signal + +#ifndef DAS_RctcWarn_Req_DAS_07_Requested +#define DAS_RctcWarn_Req_DAS_07_Requested (1) +#endif + +#ifndef DAS_RctcWarn_Req_DAS_07_Not_requested +#define DAS_RctcWarn_Req_DAS_07_Not_requested (0) +#endif + + +// Value tables for @DAS_RdaNotifError_Req signal + +#ifndef DAS_RdaNotifError_Req_DAS_07_Error +#define DAS_RdaNotifError_Req_DAS_07_Error (1) +#endif + +#ifndef DAS_RdaNotifError_Req_DAS_07_No_error +#define DAS_RdaNotifError_Req_DAS_07_No_error (0) +#endif + + +// Value tables for @DAS_LdwMode_Stat signal + +#ifndef DAS_LdwMode_Stat_DAS_07_Active_right +#define DAS_LdwMode_Stat_DAS_07_Active_right (4) +#endif + +#ifndef DAS_LdwMode_Stat_DAS_07_Active_left +#define DAS_LdwMode_Stat_DAS_07_Active_left (3) +#endif + +#ifndef DAS_LdwMode_Stat_DAS_07_Active +#define DAS_LdwMode_Stat_DAS_07_Active (2) +#endif + +#ifndef DAS_LdwMode_Stat_DAS_07_Standby +#define DAS_LdwMode_Stat_DAS_07_Standby (1) +#endif + +#ifndef DAS_LdwMode_Stat_DAS_07_Off +#define DAS_LdwMode_Stat_DAS_07_Off (0) +#endif + + +// Value tables for @DAS_LdpLeftLaneWarn_Req signal + +#ifndef DAS_LdpLeftLaneWarn_Req_DAS_07_Requested +#define DAS_LdpLeftLaneWarn_Req_DAS_07_Requested (1) +#endif + +#ifndef DAS_LdpLeftLaneWarn_Req_DAS_07_Not_requested +#define DAS_LdpLeftLaneWarn_Req_DAS_07_Not_requested (0) +#endif + + +// Value tables for @DAS_LdpRightLaneWarn_Req signal + +#ifndef DAS_LdpRightLaneWarn_Req_DAS_07_Requested +#define DAS_LdpRightLaneWarn_Req_DAS_07_Requested (1) +#endif + +#ifndef DAS_LdpRightLaneWarn_Req_DAS_07_Not_requested +#define DAS_LdpRightLaneWarn_Req_DAS_07_Not_requested (0) +#endif + + +// Value tables for @DAS_ALccNotifError_Req signal + +#ifndef DAS_ALccNotifError_Req_DAS_07_Error +#define DAS_ALccNotifError_Req_DAS_07_Error (1) +#endif + +#ifndef DAS_ALccNotifError_Req_DAS_07_No_error +#define DAS_ALccNotifError_Req_DAS_07_No_error (0) +#endif + + +// Value tables for @DAS_LdwLeftLaneWarn_Req signal + +#ifndef DAS_LdwLeftLaneWarn_Req_DAS_07_Requested +#define DAS_LdwLeftLaneWarn_Req_DAS_07_Requested (1) +#endif + +#ifndef DAS_LdwLeftLaneWarn_Req_DAS_07_Not_requested +#define DAS_LdwLeftLaneWarn_Req_DAS_07_Not_requested (0) +#endif + + +// Value tables for @DAS_LdwRightLaneWarn_Req signal + +#ifndef DAS_LdwRightLaneWarn_Req_DAS_07_Requested +#define DAS_LdwRightLaneWarn_Req_DAS_07_Requested (1) +#endif + +#ifndef DAS_LdwRightLaneWarn_Req_DAS_07_Not_requested +#define DAS_LdwRightLaneWarn_Req_DAS_07_Not_requested (0) +#endif + + +// Value tables for @DAS_LdwSound_Req signal + +#ifndef DAS_LdwSound_Req_DAS_07_Requested +#define DAS_LdwSound_Req_DAS_07_Requested (1) +#endif + +#ifndef DAS_LdwSound_Req_DAS_07_Not_requested +#define DAS_LdwSound_Req_DAS_07_Not_requested (0) +#endif + + +// Value tables for @DAS_LdwNotifError_Req signal + +#ifndef DAS_LdwNotifError_Req_DAS_07_Error +#define DAS_LdwNotifError_Req_DAS_07_Error (1) +#endif + +#ifndef DAS_LdwNotifError_Req_DAS_07_No_error +#define DAS_LdwNotifError_Req_DAS_07_No_error (0) +#endif + + +// Value tables for @DAS_LccMode_Stat signal + +#ifndef DAS_LccMode_Stat_DAS_07_Active +#define DAS_LccMode_Stat_DAS_07_Active (2) +#endif + +#ifndef DAS_LccMode_Stat_DAS_07_Standby +#define DAS_LccMode_Stat_DAS_07_Standby (1) +#endif + +#ifndef DAS_LccMode_Stat_DAS_07_Off +#define DAS_LccMode_Stat_DAS_07_Off (0) +#endif + + +// Value tables for @DAS_DowMode_Stat signal + +#ifndef DAS_DowMode_Stat_DAS_07_Active +#define DAS_DowMode_Stat_DAS_07_Active (1) +#endif + +#ifndef DAS_DowMode_Stat_DAS_07_Off +#define DAS_DowMode_Stat_DAS_07_Off (0) +#endif + + +// Value tables for @DAS_LccLeftLed_Req signal + +#ifndef DAS_LccLeftLed_Req_DAS_07_Requested +#define DAS_LccLeftLed_Req_DAS_07_Requested (1) +#endif + +#ifndef DAS_LccLeftLed_Req_DAS_07_Not_requested +#define DAS_LccLeftLed_Req_DAS_07_Not_requested (0) +#endif + + +// Value tables for @DAS_LccRightLed_Req signal + +#ifndef DAS_LccRightLed_Req_DAS_07_Requested +#define DAS_LccRightLed_Req_DAS_07_Requested (1) +#endif + +#ifndef DAS_LccRightLed_Req_DAS_07_Not_requested +#define DAS_LccRightLed_Req_DAS_07_Not_requested (0) +#endif + + +// Value tables for @DAS_LccLeftWarn_Req signal + +#ifndef DAS_LccLeftWarn_Req_DAS_07_Requested +#define DAS_LccLeftWarn_Req_DAS_07_Requested (1) +#endif + +#ifndef DAS_LccLeftWarn_Req_DAS_07_Not_requested +#define DAS_LccLeftWarn_Req_DAS_07_Not_requested (0) +#endif + + +// Value tables for @DAS_LccRightWarn_Req signal + +#ifndef DAS_LccRightWarn_Req_DAS_07_Requested +#define DAS_LccRightWarn_Req_DAS_07_Requested (1) +#endif + +#ifndef DAS_LccRightWarn_Req_DAS_07_Not_requested +#define DAS_LccRightWarn_Req_DAS_07_Not_requested (0) +#endif + + +// Value tables for @DAS_LccSound_Req signal + +#ifndef DAS_LccSound_Req_DAS_07_Requested +#define DAS_LccSound_Req_DAS_07_Requested (1) +#endif + +#ifndef DAS_LccSound_Req_DAS_07_Not_requested +#define DAS_LccSound_Req_DAS_07_Not_requested (0) +#endif + + +// Value tables for @DAS_LccNotifError_Req signal + +#ifndef DAS_LccNotifError_Req_DAS_07_Error +#define DAS_LccNotifError_Req_DAS_07_Error (1) +#endif + +#ifndef DAS_LccNotifError_Req_DAS_07_No_error +#define DAS_LccNotifError_Req_DAS_07_No_error (0) +#endif + + +// Value tables for @DAS_DowNotifError_Req signal + +#ifndef DAS_DowNotifError_Req_DAS_07_Error +#define DAS_DowNotifError_Req_DAS_07_Error (1) +#endif + +#ifndef DAS_DowNotifError_Req_DAS_07_No_error +#define DAS_DowNotifError_Req_DAS_07_No_error (0) +#endif + + +// Value tables for @DAS_LdpNotifError_Req signal + +#ifndef DAS_LdpNotifError_Req_DAS_07_Error +#define DAS_LdpNotifError_Req_DAS_07_Error (1) +#endif + +#ifndef DAS_LdpNotifError_Req_DAS_07_No_error +#define DAS_LdpNotifError_Req_DAS_07_No_error (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Warning sound to take the steering wheel + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_LkaWarnSound_Req : 1; // Bits= 1 + + // Sound when function is turned off + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_LkaShootdownSound_Req : 1; // Bits= 1 + + // Notification to take the steering wheel + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_LkaWarnNotif_Req : 1; // Bits= 1 + + // Error notification of LKA + // 1 : "Error" + // 0 : "No error" + uint8_t DAS_LkaNotifError_Req : 1; // Bits= 1 + + // RDA is requesting warning notification + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_RdaWarn_Req : 1; // Bits= 1 + + // RCTC is requesting warning notification + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_RctcWarn_Req : 1; // Bits= 1 + + // Error notification of RDA + // 1 : "Error" + // 0 : "No error" + uint8_t DAS_RdaNotifError_Req : 1; // Bits= 1 + + // Mode of Lane Departure Warning + // 4 : "Active right" + // 3 : "Active left" + // 2 : "Active" + // 1 : "Standby" + // 0 : "Off" + uint8_t DAS_LdwMode_Stat : 3; // Bits= 3 + + // LDP is requesting warning notification Left line + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_LdpLeftLaneWarn_Req : 1; // Bits= 1 + + // LDP is requesting warning notification Right line + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_LdpRightLaneWarn_Req : 1; // Bits= 1 + + // Error notification of ALCC + // 1 : "Error" + // 0 : "No error" + uint8_t DAS_ALccNotifError_Req : 1; // Bits= 1 + + // LDW is requesting warning notification Left line + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_LdwLeftLaneWarn_Req : 1; // Bits= 1 + + // LDW is requesting warning notification Right line + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_LdwRightLaneWarn_Req : 1; // Bits= 1 + + // LDW is requesting warning sound + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_LdwSound_Req : 1; // Bits= 1 + + // Error notification of LDW + // 1 : "Error" + // 0 : "No error" + uint8_t DAS_LdwNotifError_Req : 1; // Bits= 1 + + // Mode of Lane Change Control (LCC) + // 2 : "Active" + // 1 : "Standby" + // 0 : "Off" + uint8_t DAS_LccMode_Stat : 2; // Bits= 2 + + // Mode of Door Open Warning + // 1 : "Active" + // 0 : "Off" + uint8_t DAS_DowMode_Stat : 1; // Bits= 1 + + // LCC is requesting activate left LED + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_LccLeftLed_Req : 1; // Bits= 1 + + // LCC is requesting activate right LED + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_LccRightLed_Req : 1; // Bits= 1 + + // LCC is requesting activate notification left side + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_LccLeftWarn_Req : 1; // Bits= 1 + + // LCC is requesting activate notification right side + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_LccRightWarn_Req : 1; // Bits= 1 + + // LCC is requesting sound warning + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_LccSound_Req : 1; // Bits= 1 + + // Error notification of LCC + // 1 : "Error" + // 0 : "No error" + uint8_t DAS_LccNotifError_Req : 1; // Bits= 1 + + // Error notification of DOW + // 1 : "Error" + // 0 : "No error" + uint8_t DAS_DowNotifError_Req : 1; // Bits= 1 + + // Error notification of Ldp + // 1 : "Error" + // 0 : "No error" + uint8_t DAS_LdpNotifError_Req : 1; // Bits= 1 + + // Rolling Counter [0 - 15] + uint8_t DAS_07_RC : 4; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t DAS_07_CS; // Bits= 8 + +#else + + // Warning sound to take the steering wheel + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_LkaWarnSound_Req; // Bits= 1 + + // Sound when function is turned off + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_LkaShootdownSound_Req; // Bits= 1 + + // Notification to take the steering wheel + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_LkaWarnNotif_Req; // Bits= 1 + + // Error notification of LKA + // 1 : "Error" + // 0 : "No error" + uint8_t DAS_LkaNotifError_Req; // Bits= 1 + + // RDA is requesting warning notification + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_RdaWarn_Req; // Bits= 1 + + // RCTC is requesting warning notification + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_RctcWarn_Req; // Bits= 1 + + // Error notification of RDA + // 1 : "Error" + // 0 : "No error" + uint8_t DAS_RdaNotifError_Req; // Bits= 1 + + // Mode of Lane Departure Warning + // 4 : "Active right" + // 3 : "Active left" + // 2 : "Active" + // 1 : "Standby" + // 0 : "Off" + uint8_t DAS_LdwMode_Stat; // Bits= 3 + + // LDP is requesting warning notification Left line + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_LdpLeftLaneWarn_Req; // Bits= 1 + + // LDP is requesting warning notification Right line + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_LdpRightLaneWarn_Req; // Bits= 1 + + // Error notification of ALCC + // 1 : "Error" + // 0 : "No error" + uint8_t DAS_ALccNotifError_Req; // Bits= 1 + + // LDW is requesting warning notification Left line + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_LdwLeftLaneWarn_Req; // Bits= 1 + + // LDW is requesting warning notification Right line + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_LdwRightLaneWarn_Req; // Bits= 1 + + // LDW is requesting warning sound + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_LdwSound_Req; // Bits= 1 + + // Error notification of LDW + // 1 : "Error" + // 0 : "No error" + uint8_t DAS_LdwNotifError_Req; // Bits= 1 + + // Mode of Lane Change Control (LCC) + // 2 : "Active" + // 1 : "Standby" + // 0 : "Off" + uint8_t DAS_LccMode_Stat; // Bits= 2 + + // Mode of Door Open Warning + // 1 : "Active" + // 0 : "Off" + uint8_t DAS_DowMode_Stat; // Bits= 1 + + // LCC is requesting activate left LED + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_LccLeftLed_Req; // Bits= 1 + + // LCC is requesting activate right LED + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_LccRightLed_Req; // Bits= 1 + + // LCC is requesting activate notification left side + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_LccLeftWarn_Req; // Bits= 1 + + // LCC is requesting activate notification right side + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_LccRightWarn_Req; // Bits= 1 + + // LCC is requesting sound warning + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DAS_LccSound_Req; // Bits= 1 + + // Error notification of LCC + // 1 : "Error" + // 0 : "No error" + uint8_t DAS_LccNotifError_Req; // Bits= 1 + + // Error notification of DOW + // 1 : "Error" + // 0 : "No error" + uint8_t DAS_DowNotifError_Req; // Bits= 1 + + // Error notification of Ldp + // 1 : "Error" + // 0 : "No error" + uint8_t DAS_LdpNotifError_Req; // Bits= 1 + + // Rolling Counter [0 - 15] + uint8_t DAS_07_RC; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t DAS_07_CS; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} DAS_07_t; + +// def @ACU_01 CAN Message (528 0x210) +#define ACU_01_IDE (0U) +#define ACU_01_DLC (3U) +#define ACU_01_CANID (0x210U) +#define ACU_01_CYC (100U) + +// Value tables for @ACU_CrashEventDetect_Stat signal + +#ifndef ACU_CrashEventDetect_Stat_ACU_01_Crash_event_detected +#define ACU_CrashEventDetect_Stat_ACU_01_Crash_event_detected (1) +#endif + +#ifndef ACU_CrashEventDetect_Stat_ACU_01_Crash_event_not_detected +#define ACU_CrashEventDetect_Stat_ACU_01_Crash_event_not_detected (0) +#endif + + +// Value tables for @ACU_SysDeactEn_Stat signal + +#ifndef ACU_SysDeactEn_Stat_ACU_01_Enable_Complete_airbags_deactivation +#define ACU_SysDeactEn_Stat_ACU_01_Enable_Complete_airbags_deactivation (1) +#endif + +#ifndef ACU_SysDeactEn_Stat_ACU_01_Disable_Complete_airbags_deactivation +#define ACU_SysDeactEn_Stat_ACU_01_Disable_Complete_airbags_deactivation (0) +#endif + + +// Value tables for @DrivSeatBeltWarning signal + +#ifndef DrivSeatBeltWarning_ACU_01_Warning +#define DrivSeatBeltWarning_ACU_01_Warning (1) +#endif + +#ifndef DrivSeatBeltWarning_ACU_01_No_Warning +#define DrivSeatBeltWarning_ACU_01_No_Warning (0) +#endif + + +// Value tables for @PassSeatBeltWarning signal + +#ifndef PassSeatBeltWarning_ACU_01_Warning +#define PassSeatBeltWarning_ACU_01_Warning (1) +#endif + +#ifndef PassSeatBeltWarning_ACU_01_No_Warning +#define PassSeatBeltWarning_ACU_01_No_Warning (0) +#endif + + +// Value tables for @RILRequestStatus signal + +#ifndef RILRequestStatus_ACU_01_RIL_Request_ON +#define RILRequestStatus_ACU_01_RIL_Request_ON (3) +#endif + +#ifndef RILRequestStatus_ACU_01_RIL_Blinking_Request +#define RILRequestStatus_ACU_01_RIL_Blinking_Request (2) +#endif + +#ifndef RILRequestStatus_ACU_01_Reserved +#define RILRequestStatus_ACU_01_Reserved (1) +#endif + +#ifndef RILRequestStatus_ACU_01_RIL_Request_OFF +#define RILRequestStatus_ACU_01_RIL_Request_OFF (0) +#endif + + +// Value tables for @ACU_AirbagFrontPsngr_Stat signal + +#ifndef ACU_AirbagFrontPsngr_Stat_ACU_01_Not_Used +#define ACU_AirbagFrontPsngr_Stat_ACU_01_Not_Used (3) +#endif + +#ifndef ACU_AirbagFrontPsngr_Stat_ACU_01_Inactive_Lamp_ON +#define ACU_AirbagFrontPsngr_Stat_ACU_01_Inactive_Lamp_ON (2) +#endif + +#ifndef ACU_AirbagFrontPsngr_Stat_ACU_01_Reserve +#define ACU_AirbagFrontPsngr_Stat_ACU_01_Reserve (1) +#endif + +#ifndef ACU_AirbagFrontPsngr_Stat_ACU_01_Active_Lamp_OFF +#define ACU_AirbagFrontPsngr_Stat_ACU_01_Active_Lamp_OFF (0) +#endif + + +// Value tables for @RLSeatBeltWarning signal + +#ifndef RLSeatBeltWarning_ACU_01_Warning +#define RLSeatBeltWarning_ACU_01_Warning (1) +#endif + +#ifndef RLSeatBeltWarning_ACU_01_No_Warning +#define RLSeatBeltWarning_ACU_01_No_Warning (0) +#endif + + +// Value tables for @RRSeatBeltWarning signal + +#ifndef RRSeatBeltWarning_ACU_01_Warning +#define RRSeatBeltWarning_ACU_01_Warning (1) +#endif + +#ifndef RRSeatBeltWarning_ACU_01_No_Warning +#define RRSeatBeltWarning_ACU_01_No_Warning (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // The signal is generated when an accident-related event (Crash) occurs when at least one of several accident detection algorithms (Front crash detection, Rear crash detection or Side crash detection) is performed. + // 1 : "Crash event detected" + // 0 : "Crash event not detected" + uint8_t ACU_CrashEventDetect_Stat : 1; // Bits= 1 + + // Indicates when the complet airbags deactivation is requested: + // $0 = Disable Complete airbags deactivation + // $1 = Enable Complete airbags deactivation + // 1 : "Enable Complete airbags deactivation" + // 0 : "Disable Complete airbags deactivation" + uint8_t ACU_SysDeactEn_Stat : 1; // Bits= 1 + + // When the bit is set to a '1', a warning is required due to driver seat belt not detected buckled. + // 1 : "Warning" + // 0 : "No Warning" + uint8_t DrivSeatBeltWarning : 1; // Bits= 1 + + // When the bit is set to a '1', a warning is required due to passenger seat belt not detected buckled. + // 1 : "Warning" + // 0 : "No Warning" + uint8_t PassSeatBeltWarning : 1; // Bits= 1 + + // Indicates the state of the SRS Warning Lamp in the Instrument Cluster: + // $0 = RIL Request OFF: No fault + // $1 = Reserved + // $2 = RIL Blinking Request: Deployment algorithm deactivated (because of either Remote Start state or system deactivation switch) + // $3 = R + // 3 : "RIL Request ON" + // 2 : "RIL Blinking Request" + // 1 : "Reserved" + // 0 : "RIL Request OFF" + uint8_t RILRequestStatus : 2; // Bits= 2 + + // Indicates the activation status of the front passenger airbag + // $0 = Active, Lamp OFF + // $1 = Reserved + // $2 = Inactive, Lamp ON + // 3 : "Not Used" + // 2 : "Inactive, Lamp ON" + // 1 : "Reserve" + // 0 : "Active, Lamp OFF" + uint8_t ACU_AirbagFrontPsngr_Stat : 2; // Bits= 2 + + // When the bit is set to a '1', a warning is required due to rear left seat belt not detected buckled. + // 1 : "Warning" + // 0 : "No Warning" + uint8_t RLSeatBeltWarning : 1; // Bits= 1 + + // When the bit is set to a '1', a warning is required due to rear right seat belt not detected buckled. + // 1 : "Warning" + // 0 : "No Warning" + uint8_t RRSeatBeltWarning : 1; // Bits= 1 + + // Indicates belt status & Buckle status + // Bit 0: 0 = Belt status: unbelted + // Bit 0: 1 = Belt status: belted + // Bit 1: 0 = Buckle status: normal operation + // Bit 1: 1 = Buckle status: faulty + uint8_t FrontBuckleDriver_L : 2; // Bits= 2 + + // Rolling Counter [0 - 15] + uint8_t ACU_01_RC : 4; // Bits= 4 + + // Checksum XOR8 of the data field this message + // Checksum computed as per XOR algorithm: + // Byte 1 XOR byte 2 .... XOR byte n-1. (n = packet length.) + uint8_t ACU_01_CS; // Bits= 8 + +#else + + // The signal is generated when an accident-related event (Crash) occurs when at least one of several accident detection algorithms (Front crash detection, Rear crash detection or Side crash detection) is performed. + // 1 : "Crash event detected" + // 0 : "Crash event not detected" + uint8_t ACU_CrashEventDetect_Stat; // Bits= 1 + + // Indicates when the complet airbags deactivation is requested: + // $0 = Disable Complete airbags deactivation + // $1 = Enable Complete airbags deactivation + // 1 : "Enable Complete airbags deactivation" + // 0 : "Disable Complete airbags deactivation" + uint8_t ACU_SysDeactEn_Stat; // Bits= 1 + + // When the bit is set to a '1', a warning is required due to driver seat belt not detected buckled. + // 1 : "Warning" + // 0 : "No Warning" + uint8_t DrivSeatBeltWarning; // Bits= 1 + + // When the bit is set to a '1', a warning is required due to passenger seat belt not detected buckled. + // 1 : "Warning" + // 0 : "No Warning" + uint8_t PassSeatBeltWarning; // Bits= 1 + + // Indicates the state of the SRS Warning Lamp in the Instrument Cluster: + // $0 = RIL Request OFF: No fault + // $1 = Reserved + // $2 = RIL Blinking Request: Deployment algorithm deactivated (because of either Remote Start state or system deactivation switch) + // $3 = R + // 3 : "RIL Request ON" + // 2 : "RIL Blinking Request" + // 1 : "Reserved" + // 0 : "RIL Request OFF" + uint8_t RILRequestStatus; // Bits= 2 + + // Indicates the activation status of the front passenger airbag + // $0 = Active, Lamp OFF + // $1 = Reserved + // $2 = Inactive, Lamp ON + // 3 : "Not Used" + // 2 : "Inactive, Lamp ON" + // 1 : "Reserve" + // 0 : "Active, Lamp OFF" + uint8_t ACU_AirbagFrontPsngr_Stat; // Bits= 2 + + // When the bit is set to a '1', a warning is required due to rear left seat belt not detected buckled. + // 1 : "Warning" + // 0 : "No Warning" + uint8_t RLSeatBeltWarning; // Bits= 1 + + // When the bit is set to a '1', a warning is required due to rear right seat belt not detected buckled. + // 1 : "Warning" + // 0 : "No Warning" + uint8_t RRSeatBeltWarning; // Bits= 1 + + // Indicates belt status & Buckle status + // Bit 0: 0 = Belt status: unbelted + // Bit 0: 1 = Belt status: belted + // Bit 1: 0 = Buckle status: normal operation + // Bit 1: 1 = Buckle status: faulty + uint8_t FrontBuckleDriver_L; // Bits= 2 + + // Rolling Counter [0 - 15] + uint8_t ACU_01_RC; // Bits= 4 + + // Checksum XOR8 of the data field this message + // Checksum computed as per XOR algorithm: + // Byte 1 XOR byte 2 .... XOR byte n-1. (n = packet length.) + uint8_t ACU_01_CS; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} ACU_01_t; + +// def @EPB_Status CAN Message (538 0x21a) +#define EPB_Status_IDE (0U) +#define EPB_Status_DLC (5U) +#define EPB_Status_CANID (0x21aU) +#define EPB_Status_CYC (20U) + +// Value tables for @EPB_AppliedForce_Stat signal + +#ifndef EPB_AppliedForce_Stat_EPB_Status_Maximum_force_applied +#define EPB_AppliedForce_Stat_EPB_Status_Maximum_force_applied (3) +#endif + +#ifndef EPB_AppliedForce_Stat_EPB_Status_Medium_force_applied +#define EPB_AppliedForce_Stat_EPB_Status_Medium_force_applied (2) +#endif + +#ifndef EPB_AppliedForce_Stat_EPB_Status_Low_force_applied +#define EPB_AppliedForce_Stat_EPB_Status_Low_force_applied (1) +#endif + +#ifndef EPB_AppliedForce_Stat_EPB_Status_No_force_applied +#define EPB_AppliedForce_Stat_EPB_Status_No_force_applied (0) +#endif + + +// Value tables for @EPB_BrakeLight_Req signal + +#ifndef EPB_BrakeLight_Req_EPB_Status_Request +#define EPB_BrakeLight_Req_EPB_Status_Request (1) +#endif + +#ifndef EPB_BrakeLight_Req_EPB_Status_No_request +#define EPB_BrakeLight_Req_EPB_Status_No_request (0) +#endif + + +// Value tables for @EPB_CurrParkBrake_Stat signal + +#ifndef EPB_CurrParkBrake_Stat_EPB_Status_Reserved +#define EPB_CurrParkBrake_Stat_EPB_Status_Reserved (5) +#endif + +#ifndef EPB_CurrParkBrake_Stat_EPB_Status_Engagement_under_Progress +#define EPB_CurrParkBrake_Stat_EPB_Status_Engagement_under_Progress (4) +#endif + +#ifndef EPB_CurrParkBrake_Stat_EPB_Status_Release_Under_Progress +#define EPB_CurrParkBrake_Stat_EPB_Status_Release_Under_Progress (3) +#endif + +#ifndef EPB_CurrParkBrake_Stat_EPB_Status_Engaged +#define EPB_CurrParkBrake_Stat_EPB_Status_Engaged (2) +#endif + +#ifndef EPB_CurrParkBrake_Stat_EPB_Status_Released +#define EPB_CurrParkBrake_Stat_EPB_Status_Released (1) +#endif + +#ifndef EPB_CurrParkBrake_Stat_EPB_Status_Not_Initialized +#define EPB_CurrParkBrake_Stat_EPB_Status_Not_Initialized (0) +#endif + + +// Value tables for @EPB_AudibleChime_Req signal + +#ifndef EPB_AudibleChime_Req_EPB_Status_Request +#define EPB_AudibleChime_Req_EPB_Status_Request (1) +#endif + +#ifndef EPB_AudibleChime_Req_EPB_Status_No_Request +#define EPB_AudibleChime_Req_EPB_Status_No_Request (0) +#endif + +// signal: @EPB_TargetDecel_Val_ro +#define CANDB_EPB_TargetDecel_Val_ro_CovFactor (0.05) +#define CANDB_EPB_TargetDecel_Val_ro_toS(x) ( (uint8_t) (((x) - (-4.0)) / (0.05)) ) +#define CANDB_EPB_TargetDecel_Val_ro_fromS(x) ( (((x) * (0.05)) + (-4.0)) ) + +// Value tables for @EPB_CurrEPBSw_Stat signal + +#ifndef EPB_CurrEPBSw_Stat_EPB_Status_Fault +#define EPB_CurrEPBSw_Stat_EPB_Status_Fault (3) +#endif + +#ifndef EPB_CurrEPBSw_Stat_EPB_Status_Lock_Brake +#define EPB_CurrEPBSw_Stat_EPB_Status_Lock_Brake (2) +#endif + +#ifndef EPB_CurrEPBSw_Stat_EPB_Status_Release_Brake +#define EPB_CurrEPBSw_Stat_EPB_Status_Release_Brake (1) +#endif + +#ifndef EPB_CurrEPBSw_Stat_EPB_Status_No_Request +#define EPB_CurrEPBSw_Stat_EPB_Status_No_Request (0) +#endif + + +// Value tables for @EPB_DynamicEmergencyApply_Stat signal + +#ifndef EPB_DynamicEmergencyApply_Stat_EPB_Status_Enabled +#define EPB_DynamicEmergencyApply_Stat_EPB_Status_Enabled (1) +#endif + +#ifndef EPB_DynamicEmergencyApply_Stat_EPB_Status_Not_Enabled +#define EPB_DynamicEmergencyApply_Stat_EPB_Status_Not_Enabled (0) +#endif + + +// Value tables for @EPB_Indicator_Req signal + +#ifndef EPB_Indicator_Req_EPB_Status_Failure_Indication +#define EPB_Indicator_Req_EPB_Status_Failure_Indication (3) +#endif + +#ifndef EPB_Indicator_Req_EPB_Status_Dynamic_Braking_Indication +#define EPB_Indicator_Req_EPB_Status_Dynamic_Braking_Indication (2) +#endif + +#ifndef EPB_Indicator_Req_EPB_Status_Engaged_Brake_Indication +#define EPB_Indicator_Req_EPB_Status_Engaged_Brake_Indication (1) +#endif + +#ifndef EPB_Indicator_Req_EPB_Status_No_Indication +#define EPB_Indicator_Req_EPB_Status_No_Indication (0) +#endif + + +// Value tables for @EPB_Failure_Stat signal + +#ifndef EPB_Failure_Stat_EPB_Status_Failure +#define EPB_Failure_Stat_EPB_Status_Failure (1) +#endif + +#ifndef EPB_Failure_Stat_EPB_Status_No_Failure +#define EPB_Failure_Stat_EPB_Status_No_Failure (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // State of he force applied by tightening the cable. + // $0 = No Force Applied + // $1 = Low Force Applied + // $2 = Medium Force Applied + // $3 = Maximum Force Applied + // 3 : "Maximum force applied" + // 2 : "Medium force applied" + // 1 : "Low force applied" + // 0 : "No force applied" + uint8_t EPB_AppliedForce_Stat : 3; // Bits= 3 + + // Brake light on request from EPB system + // 1 : "Request" + // 0 : "No request" + uint8_t EPB_BrakeLight_Req : 1; // Bits= 1 + + // EPB current status + // $0 = Not Initialized + // $1 = Released + // $2 = Engaged + // $3 = Release Under Progress + // $4 = Engagement Under Progress + // $5 = Reserved + // 5 : "Reserved" + // 4 : "Engagement under Progress" + // 3 : "Release Under Progress" + // 2 : "Engaged" + // 1 : "Released" + // 0 : "Not Initialized" + uint8_t EPB_CurrParkBrake_Stat : 3; // Bits= 3 + + // Audible warning request + // 1 : "Request" + // 0 : "No Request" + uint8_t EPB_AudibleChime_Req : 1; // Bits= 1 + + // Decelartion requested from EPB when EPB switch is detected pressed and vehicle speed > 7km/h + // This information will be taken into account by braking unit only if the EPB_DynamicEmergencyApply signal request is active. + // ESC requests this signal to be certi + uint8_t EPB_TargetDecel_Val_ro; // Bits= 8 Offset= -4.0 Factor= 0.05 Unit:'m/s^2' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t EPB_TargetDecel_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // EPB switch current status + // $0 = No Request + // $1 = Release Brake + // $2 = Lock Brake + // $3 = Fault + // 3 : "Fault" + // 2 : "Lock Brake" + // 1 : "Release Brake" + // 0 : "No Request" + uint8_t EPB_CurrEPBSw_Stat : 3; // Bits= 3 + + // Emergency braking from EPB button when speed > 7km/h: + // $0= Not Enabled + // $1= Enabled + // ESC requests this signal to be certified ASIL C + // 1 : "Enabled" + // 0 : "Not Enabled" + uint8_t EPB_DynamicEmergencyApply_Stat : 1; // Bits= 1 + + // Feedback from EPB for indication Parking brake activation + // Reserved = No action by ATS + // 3 : "Failure Indication" + // 2 : "Dynamic Braking Indication" + // 1 : "Engaged Brake Indication" + // 0 : "No Indication" + uint8_t EPB_Indicator_Req : 2; // Bits= 2 + + // EPB failure status: + // $0 = No failure + // $1 = Failure + // 1 : "Failure" + // 0 : "No Failure" + uint8_t EPB_Failure_Stat : 1; // Bits= 1 + + // Rolling Counter [0 - 15] + uint8_t EPB_Status_RC : 4; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t EPB_Status_CS; // Bits= 8 + +#else + + // State of he force applied by tightening the cable. + // $0 = No Force Applied + // $1 = Low Force Applied + // $2 = Medium Force Applied + // $3 = Maximum Force Applied + // 3 : "Maximum force applied" + // 2 : "Medium force applied" + // 1 : "Low force applied" + // 0 : "No force applied" + uint8_t EPB_AppliedForce_Stat; // Bits= 3 + + // Brake light on request from EPB system + // 1 : "Request" + // 0 : "No request" + uint8_t EPB_BrakeLight_Req; // Bits= 1 + + // EPB current status + // $0 = Not Initialized + // $1 = Released + // $2 = Engaged + // $3 = Release Under Progress + // $4 = Engagement Under Progress + // $5 = Reserved + // 5 : "Reserved" + // 4 : "Engagement under Progress" + // 3 : "Release Under Progress" + // 2 : "Engaged" + // 1 : "Released" + // 0 : "Not Initialized" + uint8_t EPB_CurrParkBrake_Stat; // Bits= 3 + + // Audible warning request + // 1 : "Request" + // 0 : "No Request" + uint8_t EPB_AudibleChime_Req; // Bits= 1 + + // Decelartion requested from EPB when EPB switch is detected pressed and vehicle speed > 7km/h + // This information will be taken into account by braking unit only if the EPB_DynamicEmergencyApply signal request is active. + // ESC requests this signal to be certi + uint8_t EPB_TargetDecel_Val_ro; // Bits= 8 Offset= -4.0 Factor= 0.05 Unit:'m/s^2' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t EPB_TargetDecel_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // EPB switch current status + // $0 = No Request + // $1 = Release Brake + // $2 = Lock Brake + // $3 = Fault + // 3 : "Fault" + // 2 : "Lock Brake" + // 1 : "Release Brake" + // 0 : "No Request" + uint8_t EPB_CurrEPBSw_Stat; // Bits= 3 + + // Emergency braking from EPB button when speed > 7km/h: + // $0= Not Enabled + // $1= Enabled + // ESC requests this signal to be certified ASIL C + // 1 : "Enabled" + // 0 : "Not Enabled" + uint8_t EPB_DynamicEmergencyApply_Stat; // Bits= 1 + + // Feedback from EPB for indication Parking brake activation + // Reserved = No action by ATS + // 3 : "Failure Indication" + // 2 : "Dynamic Braking Indication" + // 1 : "Engaged Brake Indication" + // 0 : "No Indication" + uint8_t EPB_Indicator_Req; // Bits= 2 + + // EPB failure status: + // $0 = No failure + // $1 = Failure + // 1 : "Failure" + // 0 : "No Failure" + uint8_t EPB_Failure_Stat; // Bits= 1 + + // Rolling Counter [0 - 15] + uint8_t EPB_Status_RC; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t EPB_Status_CS; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} EPB_Status_t; + +// def @BCM_ExteriorLightState CAN Message (561 0x231) +#define BCM_ExteriorLightState_IDE (0U) +#define BCM_ExteriorLightState_DLC (4U) +#define BCM_ExteriorLightState_CANID (0x231U) +#define BCM_ExteriorLightState_CYC (50U) + +// Value tables for @BCM_PositionLightRearState signal + +#ifndef BCM_PositionLightRearState_BCM_ExteriorLightState_On +#define BCM_PositionLightRearState_BCM_ExteriorLightState_On (1) +#endif + +#ifndef BCM_PositionLightRearState_BCM_ExteriorLightState_Off +#define BCM_PositionLightRearState_BCM_ExteriorLightState_Off (0) +#endif + + +// Value tables for @BCM_TurnIndL_Req signal + +#ifndef BCM_TurnIndL_Req_BCM_ExteriorLightState_On +#define BCM_TurnIndL_Req_BCM_ExteriorLightState_On (1) +#endif + +#ifndef BCM_TurnIndL_Req_BCM_ExteriorLightState_Off +#define BCM_TurnIndL_Req_BCM_ExteriorLightState_Off (0) +#endif + + +// Value tables for @BCM_TurnIndR_Req signal + +#ifndef BCM_TurnIndR_Req_BCM_ExteriorLightState_On +#define BCM_TurnIndR_Req_BCM_ExteriorLightState_On (1) +#endif + +#ifndef BCM_TurnIndR_Req_BCM_ExteriorLightState_Off +#define BCM_TurnIndR_Req_BCM_ExteriorLightState_Off (0) +#endif + + +// Value tables for @BCM_PosLghtsState signal + +#ifndef BCM_PosLghtsState_BCM_ExteriorLightState_Position_Lights_ON +#define BCM_PosLghtsState_BCM_ExteriorLightState_Position_Lights_ON (1) +#endif + +#ifndef BCM_PosLghtsState_BCM_ExteriorLightState_Position_Lights_OFF +#define BCM_PosLghtsState_BCM_ExteriorLightState_Position_Lights_OFF (0) +#endif + + +// Value tables for @BCM_RearFogLightState signal + +#ifndef BCM_RearFogLightState_BCM_ExteriorLightState_On +#define BCM_RearFogLightState_BCM_ExteriorLightState_On (1) +#endif + +#ifndef BCM_RearFogLightState_BCM_ExteriorLightState_Off +#define BCM_RearFogLightState_BCM_ExteriorLightState_Off (0) +#endif + + +// Value tables for @BCM_BrakeLightState signal + +#ifndef BCM_BrakeLightState_BCM_ExteriorLightState_On +#define BCM_BrakeLightState_BCM_ExteriorLightState_On (1) +#endif + +#ifndef BCM_BrakeLightState_BCM_ExteriorLightState_Off +#define BCM_BrakeLightState_BCM_ExteriorLightState_Off (0) +#endif + + +// Value tables for @BCM_ReverseLightState signal + +#ifndef BCM_ReverseLightState_BCM_ExteriorLightState_On +#define BCM_ReverseLightState_BCM_ExteriorLightState_On (1) +#endif + +#ifndef BCM_ReverseLightState_BCM_ExteriorLightState_Off +#define BCM_ReverseLightState_BCM_ExteriorLightState_Off (0) +#endif + + +// Value tables for @BCM_HighBeamState signal + +#ifndef BCM_HighBeamState_BCM_ExteriorLightState_HIgh_Beam_Auto_Active +#define BCM_HighBeamState_BCM_ExteriorLightState_HIgh_Beam_Auto_Active (3) +#endif + +#ifndef BCM_HighBeamState_BCM_ExteriorLightState_High_Beam_Auto_Standby +#define BCM_HighBeamState_BCM_ExteriorLightState_High_Beam_Auto_Standby (2) +#endif + +#ifndef BCM_HighBeamState_BCM_ExteriorLightState_High_Beam_Manual_Active +#define BCM_HighBeamState_BCM_ExteriorLightState_High_Beam_Manual_Active (1) +#endif + +#ifndef BCM_HighBeamState_BCM_ExteriorLightState_Lights_Inactive +#define BCM_HighBeamState_BCM_ExteriorLightState_Lights_Inactive (0) +#endif + + +// Value tables for @BCM_LightSwitchPos signal + +#ifndef BCM_LightSwitchPos_BCM_ExteriorLightState_Position_Lights_Mode +#define BCM_LightSwitchPos_BCM_ExteriorLightState_Position_Lights_Mode (3) +#endif + +#ifndef BCM_LightSwitchPos_BCM_ExteriorLightState_Low_Beam_Mode +#define BCM_LightSwitchPos_BCM_ExteriorLightState_Low_Beam_Mode (2) +#endif + +#ifndef BCM_LightSwitchPos_BCM_ExteriorLightState_Auto_ON +#define BCM_LightSwitchPos_BCM_ExteriorLightState_Auto_ON (1) +#endif + +#ifndef BCM_LightSwitchPos_BCM_ExteriorLightState_OFF_Mode +#define BCM_LightSwitchPos_BCM_ExteriorLightState_OFF_Mode (0) +#endif + + +// Value tables for @BCM_LowBeamState signal + +#ifndef BCM_LowBeamState_BCM_ExteriorLightState_On_W_mode +#define BCM_LowBeamState_BCM_ExteriorLightState_On_W_mode (4) +#endif + +#ifndef BCM_LowBeamState_BCM_ExteriorLightState_On_E_mode +#define BCM_LowBeamState_BCM_ExteriorLightState_On_E_mode (3) +#endif + +#ifndef BCM_LowBeamState_BCM_ExteriorLightState_On_V_mode +#define BCM_LowBeamState_BCM_ExteriorLightState_On_V_mode (2) +#endif + +#ifndef BCM_LowBeamState_BCM_ExteriorLightState_On_C_mode +#define BCM_LowBeamState_BCM_ExteriorLightState_On_C_mode (1) +#endif + +#ifndef BCM_LowBeamState_BCM_ExteriorLightState_OFF +#define BCM_LowBeamState_BCM_ExteriorLightState_OFF (0) +#endif + + +// Value tables for @BCM_AllWthrLght_State signal + +#ifndef BCM_AllWthrLght_State_BCM_ExteriorLightState_All_Weather_Lights_ON +#define BCM_AllWthrLght_State_BCM_ExteriorLightState_All_Weather_Lights_ON (1) +#endif + +#ifndef BCM_AllWthrLght_State_BCM_ExteriorLightState_All_Weather_Lights_OFF +#define BCM_AllWthrLght_State_BCM_ExteriorLightState_All_Weather_Lights_OFF (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Rear Position Light Control Signal + // 1 : "On" + // 0 : "Off" + uint8_t BCM_PositionLightRearState : 1; // Bits= 1 + + // Left Direction Indicator Control Signal + // 1 : "On" + // 0 : "Off" + uint8_t BCM_TurnIndL_Req : 1; // Bits= 1 + + // Right Direction Indicator Control Signal + // 1 : "On" + // 0 : "Off" + uint8_t BCM_TurnIndR_Req : 1; // Bits= 1 + + // State of position lights + // 1 : "Position Lights ON" + // 0 : "Position Lights OFF" + uint8_t BCM_PosLghtsState : 1; // Bits= 1 + + // Rear Fog Light Control Signal + // 1 : "On" + // 0 : "Off" + uint8_t BCM_RearFogLightState : 1; // Bits= 1 + + // Brake Light Control Signal + // 1 : "On" + // 0 : "Off" + uint8_t BCM_BrakeLightState : 1; // Bits= 1 + + // Reverse Light Control Signal + // 1 : "On" + // 0 : "Off" + uint8_t BCM_ReverseLightState : 1; // Bits= 1 + + // State of High Beam Lights for acivating an indicator on IC. + // 3 : "HIgh Beam Auto Active" + // 2 : "High Beam Auto Standby" + // 1 : "High Beam Manual Active" + // 0 : "Lights Inactive" + uint8_t BCM_HighBeamState : 3; // Bits= 3 + + // Selected position of light control switch + // 3 : "Position Lights Mode" + // 2 : "Low Beam Mode" + // 1 : "Auto ON" + // 0 : "OFF Mode" + uint8_t BCM_LightSwitchPos : 2; // Bits= 2 + + // State of Low Beam Lights + // 4 : "On W mode" + // 3 : "On E mode" + // 2 : "On V mode" + // 1 : "On C mode" + // 0 : "OFF" + uint8_t BCM_LowBeamState : 3; // Bits= 3 + + // State of all-weather light function + // 1 : "All Weather Lights ON" + // 0 : "All Weather Lights OFF" + uint8_t BCM_AllWthrLght_State : 1; // Bits= 1 + +#else + + // Rear Position Light Control Signal + // 1 : "On" + // 0 : "Off" + uint8_t BCM_PositionLightRearState; // Bits= 1 + + // Left Direction Indicator Control Signal + // 1 : "On" + // 0 : "Off" + uint8_t BCM_TurnIndL_Req; // Bits= 1 + + // Right Direction Indicator Control Signal + // 1 : "On" + // 0 : "Off" + uint8_t BCM_TurnIndR_Req; // Bits= 1 + + // State of position lights + // 1 : "Position Lights ON" + // 0 : "Position Lights OFF" + uint8_t BCM_PosLghtsState; // Bits= 1 + + // Rear Fog Light Control Signal + // 1 : "On" + // 0 : "Off" + uint8_t BCM_RearFogLightState; // Bits= 1 + + // Brake Light Control Signal + // 1 : "On" + // 0 : "Off" + uint8_t BCM_BrakeLightState; // Bits= 1 + + // Reverse Light Control Signal + // 1 : "On" + // 0 : "Off" + uint8_t BCM_ReverseLightState; // Bits= 1 + + // State of High Beam Lights for acivating an indicator on IC. + // 3 : "HIgh Beam Auto Active" + // 2 : "High Beam Auto Standby" + // 1 : "High Beam Manual Active" + // 0 : "Lights Inactive" + uint8_t BCM_HighBeamState; // Bits= 3 + + // Selected position of light control switch + // 3 : "Position Lights Mode" + // 2 : "Low Beam Mode" + // 1 : "Auto ON" + // 0 : "OFF Mode" + uint8_t BCM_LightSwitchPos; // Bits= 2 + + // State of Low Beam Lights + // 4 : "On W mode" + // 3 : "On E mode" + // 2 : "On V mode" + // 1 : "On C mode" + // 0 : "OFF" + uint8_t BCM_LowBeamState; // Bits= 3 + + // State of all-weather light function + // 1 : "All Weather Lights ON" + // 0 : "All Weather Lights OFF" + uint8_t BCM_AllWthrLght_State; // Bits= 1 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} BCM_ExteriorLightState_t; + +// def @SWM_ContrlsState CAN Message (568 0x238) +#define SWM_ContrlsState_IDE (0U) +#define SWM_ContrlsState_DLC (8U) +#define SWM_ContrlsState_CANID (0x238U) +#define SWM_ContrlsState_CYC (100U) + +// Value tables for @SWM_MODE_Req signal + +#ifndef SWM_MODE_Req_SWM_ContrlsState_Failure +#define SWM_MODE_Req_SWM_ContrlsState_Failure (3) +#endif + +#ifndef SWM_MODE_Req_SWM_ContrlsState_Pressed +#define SWM_MODE_Req_SWM_ContrlsState_Pressed (2) +#endif + +#ifndef SWM_MODE_Req_SWM_ContrlsState_Reserved +#define SWM_MODE_Req_SWM_ContrlsState_Reserved (0) +#endif + +#ifndef SWM_MODE_Req_SWM_ContrlsState_Released +#define SWM_MODE_Req_SWM_ContrlsState_Released (1) +#endif + + +// Value tables for @SWM_CNCL_Req signal + +#ifndef SWM_CNCL_Req_SWM_ContrlsState_Failure +#define SWM_CNCL_Req_SWM_ContrlsState_Failure (3) +#endif + +#ifndef SWM_CNCL_Req_SWM_ContrlsState_Pressed +#define SWM_CNCL_Req_SWM_ContrlsState_Pressed (2) +#endif + +#ifndef SWM_CNCL_Req_SWM_ContrlsState_Reserved +#define SWM_CNCL_Req_SWM_ContrlsState_Reserved (0) +#endif + +#ifndef SWM_CNCL_Req_SWM_ContrlsState_Released +#define SWM_CNCL_Req_SWM_ContrlsState_Released (1) +#endif + + +// Value tables for @SWM_ACCSpeedDecrease_Req signal + +#ifndef SWM_ACCSpeedDecrease_Req_SWM_ContrlsState_Failure +#define SWM_ACCSpeedDecrease_Req_SWM_ContrlsState_Failure (3) +#endif + +#ifndef SWM_ACCSpeedDecrease_Req_SWM_ContrlsState_Pressed +#define SWM_ACCSpeedDecrease_Req_SWM_ContrlsState_Pressed (2) +#endif + +#ifndef SWM_ACCSpeedDecrease_Req_SWM_ContrlsState_Reserved +#define SWM_ACCSpeedDecrease_Req_SWM_ContrlsState_Reserved (0) +#endif + +#ifndef SWM_ACCSpeedDecrease_Req_SWM_ContrlsState_Released +#define SWM_ACCSpeedDecrease_Req_SWM_ContrlsState_Released (1) +#endif + + +// Value tables for @SWM_ACCSpeedIncrease_Req signal + +#ifndef SWM_ACCSpeedIncrease_Req_SWM_ContrlsState_Failure +#define SWM_ACCSpeedIncrease_Req_SWM_ContrlsState_Failure (3) +#endif + +#ifndef SWM_ACCSpeedIncrease_Req_SWM_ContrlsState_Pressed +#define SWM_ACCSpeedIncrease_Req_SWM_ContrlsState_Pressed (2) +#endif + +#ifndef SWM_ACCSpeedIncrease_Req_SWM_ContrlsState_Reserved +#define SWM_ACCSpeedIncrease_Req_SWM_ContrlsState_Reserved (0) +#endif + +#ifndef SWM_ACCSpeedIncrease_Req_SWM_ContrlsState_Released +#define SWM_ACCSpeedIncrease_Req_SWM_ContrlsState_Released (1) +#endif + + +// Value tables for @SWM_UserFunc_Req signal + +#ifndef SWM_UserFunc_Req_SWM_ContrlsState_Failure +#define SWM_UserFunc_Req_SWM_ContrlsState_Failure (3) +#endif + +#ifndef SWM_UserFunc_Req_SWM_ContrlsState_Pressed +#define SWM_UserFunc_Req_SWM_ContrlsState_Pressed (2) +#endif + +#ifndef SWM_UserFunc_Req_SWM_ContrlsState_Reserved +#define SWM_UserFunc_Req_SWM_ContrlsState_Reserved (0) +#endif + +#ifndef SWM_UserFunc_Req_SWM_ContrlsState_Released +#define SWM_UserFunc_Req_SWM_ContrlsState_Released (1) +#endif + + +// Value tables for @SWM_DIS_Req signal + +#ifndef SWM_DIS_Req_SWM_ContrlsState_Failure +#define SWM_DIS_Req_SWM_ContrlsState_Failure (3) +#endif + +#ifndef SWM_DIS_Req_SWM_ContrlsState_Pressed +#define SWM_DIS_Req_SWM_ContrlsState_Pressed (2) +#endif + +#ifndef SWM_DIS_Req_SWM_ContrlsState_Reserved +#define SWM_DIS_Req_SWM_ContrlsState_Reserved (0) +#endif + +#ifndef SWM_DIS_Req_SWM_ContrlsState_Released +#define SWM_DIS_Req_SWM_ContrlsState_Released (1) +#endif + + +// Value tables for @SWM_RES_Req signal + +#ifndef SWM_RES_Req_SWM_ContrlsState_Failure +#define SWM_RES_Req_SWM_ContrlsState_Failure (3) +#endif + +#ifndef SWM_RES_Req_SWM_ContrlsState_Pressed +#define SWM_RES_Req_SWM_ContrlsState_Pressed (2) +#endif + +#ifndef SWM_RES_Req_SWM_ContrlsState_Reserved +#define SWM_RES_Req_SWM_ContrlsState_Reserved (0) +#endif + +#ifndef SWM_RES_Req_SWM_ContrlsState_Released +#define SWM_RES_Req_SWM_ContrlsState_Released (1) +#endif + + +// Value tables for @SWM_SETSpeed_Req signal + +#ifndef SWM_SETSpeed_Req_SWM_ContrlsState_Failure +#define SWM_SETSpeed_Req_SWM_ContrlsState_Failure (3) +#endif + +#ifndef SWM_SETSpeed_Req_SWM_ContrlsState_Pressed +#define SWM_SETSpeed_Req_SWM_ContrlsState_Pressed (2) +#endif + +#ifndef SWM_SETSpeed_Req_SWM_ContrlsState_Reserved +#define SWM_SETSpeed_Req_SWM_ContrlsState_Reserved (0) +#endif + +#ifndef SWM_SETSpeed_Req_SWM_ContrlsState_Released +#define SWM_SETSpeed_Req_SWM_ContrlsState_Released (1) +#endif + + +// Value tables for @SWM_TELBtn_Req signal + +#ifndef SWM_TELBtn_Req_SWM_ContrlsState_Failure +#define SWM_TELBtn_Req_SWM_ContrlsState_Failure (3) +#endif + +#ifndef SWM_TELBtn_Req_SWM_ContrlsState_Pressed +#define SWM_TELBtn_Req_SWM_ContrlsState_Pressed (2) +#endif + +#ifndef SWM_TELBtn_Req_SWM_ContrlsState_Reserved +#define SWM_TELBtn_Req_SWM_ContrlsState_Reserved (0) +#endif + +#ifndef SWM_TELBtn_Req_SWM_ContrlsState_Released +#define SWM_TELBtn_Req_SWM_ContrlsState_Released (1) +#endif + + +// Value tables for @SWM_Home_Req signal + +#ifndef SWM_Home_Req_SWM_ContrlsState_Failure +#define SWM_Home_Req_SWM_ContrlsState_Failure (3) +#endif + +#ifndef SWM_Home_Req_SWM_ContrlsState_Pressed +#define SWM_Home_Req_SWM_ContrlsState_Pressed (2) +#endif + +#ifndef SWM_Home_Req_SWM_ContrlsState_Reserved +#define SWM_Home_Req_SWM_ContrlsState_Reserved (0) +#endif + +#ifndef SWM_Home_Req_SWM_ContrlsState_Released +#define SWM_Home_Req_SWM_ContrlsState_Released (1) +#endif + + +// Value tables for @SWM_Back_Req signal + +#ifndef SWM_Back_Req_SWM_ContrlsState_Failure +#define SWM_Back_Req_SWM_ContrlsState_Failure (3) +#endif + +#ifndef SWM_Back_Req_SWM_ContrlsState_Pressed +#define SWM_Back_Req_SWM_ContrlsState_Pressed (2) +#endif + +#ifndef SWM_Back_Req_SWM_ContrlsState_Reserved +#define SWM_Back_Req_SWM_ContrlsState_Reserved (0) +#endif + +#ifndef SWM_Back_Req_SWM_ContrlsState_Released +#define SWM_Back_Req_SWM_ContrlsState_Released (1) +#endif + + +// Value tables for @SWM_ICNextBtn_Req signal + +#ifndef SWM_ICNextBtn_Req_SWM_ContrlsState_Failure +#define SWM_ICNextBtn_Req_SWM_ContrlsState_Failure (3) +#endif + +#ifndef SWM_ICNextBtn_Req_SWM_ContrlsState_Pressed +#define SWM_ICNextBtn_Req_SWM_ContrlsState_Pressed (2) +#endif + +#ifndef SWM_ICNextBtn_Req_SWM_ContrlsState_Reserved +#define SWM_ICNextBtn_Req_SWM_ContrlsState_Reserved (0) +#endif + +#ifndef SWM_ICNextBtn_Req_SWM_ContrlsState_Released +#define SWM_ICNextBtn_Req_SWM_ContrlsState_Released (1) +#endif + + +// Value tables for @SWM_ICPrevBtn_Req signal + +#ifndef SWM_ICPrevBtn_Req_SWM_ContrlsState_Failure +#define SWM_ICPrevBtn_Req_SWM_ContrlsState_Failure (3) +#endif + +#ifndef SWM_ICPrevBtn_Req_SWM_ContrlsState_Pressed +#define SWM_ICPrevBtn_Req_SWM_ContrlsState_Pressed (2) +#endif + +#ifndef SWM_ICPrevBtn_Req_SWM_ContrlsState_Reserved +#define SWM_ICPrevBtn_Req_SWM_ContrlsState_Reserved (0) +#endif + +#ifndef SWM_ICPrevBtn_Req_SWM_ContrlsState_Released +#define SWM_ICPrevBtn_Req_SWM_ContrlsState_Released (1) +#endif + + +// Value tables for @SWM_ICUpBtn_Req signal + +#ifndef SWM_ICUpBtn_Req_SWM_ContrlsState_Failure +#define SWM_ICUpBtn_Req_SWM_ContrlsState_Failure (3) +#endif + +#ifndef SWM_ICUpBtn_Req_SWM_ContrlsState_Pressed +#define SWM_ICUpBtn_Req_SWM_ContrlsState_Pressed (2) +#endif + +#ifndef SWM_ICUpBtn_Req_SWM_ContrlsState_Reserved +#define SWM_ICUpBtn_Req_SWM_ContrlsState_Reserved (0) +#endif + +#ifndef SWM_ICUpBtn_Req_SWM_ContrlsState_Released +#define SWM_ICUpBtn_Req_SWM_ContrlsState_Released (1) +#endif + + +// Value tables for @SWM_ICDownBtn_Req signal + +#ifndef SWM_ICDownBtn_Req_SWM_ContrlsState_Failure +#define SWM_ICDownBtn_Req_SWM_ContrlsState_Failure (3) +#endif + +#ifndef SWM_ICDownBtn_Req_SWM_ContrlsState_Pressed +#define SWM_ICDownBtn_Req_SWM_ContrlsState_Pressed (2) +#endif + +#ifndef SWM_ICDownBtn_Req_SWM_ContrlsState_Reserved +#define SWM_ICDownBtn_Req_SWM_ContrlsState_Reserved (0) +#endif + +#ifndef SWM_ICDownBtn_Req_SWM_ContrlsState_Released +#define SWM_ICDownBtn_Req_SWM_ContrlsState_Released (1) +#endif + + +// Value tables for @SWM_ICConfBtn_Req signal + +#ifndef SWM_ICConfBtn_Req_SWM_ContrlsState_Failure +#define SWM_ICConfBtn_Req_SWM_ContrlsState_Failure (3) +#endif + +#ifndef SWM_ICConfBtn_Req_SWM_ContrlsState_Pressed +#define SWM_ICConfBtn_Req_SWM_ContrlsState_Pressed (2) +#endif + +#ifndef SWM_ICConfBtn_Req_SWM_ContrlsState_Reserved +#define SWM_ICConfBtn_Req_SWM_ContrlsState_Reserved (0) +#endif + +#ifndef SWM_ICConfBtn_Req_SWM_ContrlsState_Released +#define SWM_ICConfBtn_Req_SWM_ContrlsState_Released (1) +#endif + + +// Value tables for @SWM_MMCNextBtn_Req signal + +#ifndef SWM_MMCNextBtn_Req_SWM_ContrlsState_Failure +#define SWM_MMCNextBtn_Req_SWM_ContrlsState_Failure (3) +#endif + +#ifndef SWM_MMCNextBtn_Req_SWM_ContrlsState_Pressed +#define SWM_MMCNextBtn_Req_SWM_ContrlsState_Pressed (2) +#endif + +#ifndef SWM_MMCNextBtn_Req_SWM_ContrlsState_Released +#define SWM_MMCNextBtn_Req_SWM_ContrlsState_Released (1) +#endif + +#ifndef SWM_MMCNextBtn_Req_SWM_ContrlsState_Reserved +#define SWM_MMCNextBtn_Req_SWM_ContrlsState_Reserved (0) +#endif + + +// Value tables for @SWM_MMCPrevBtn_Req signal + +#ifndef SWM_MMCPrevBtn_Req_SWM_ContrlsState_Failure +#define SWM_MMCPrevBtn_Req_SWM_ContrlsState_Failure (3) +#endif + +#ifndef SWM_MMCPrevBtn_Req_SWM_ContrlsState_Pressed +#define SWM_MMCPrevBtn_Req_SWM_ContrlsState_Pressed (2) +#endif + +#ifndef SWM_MMCPrevBtn_Req_SWM_ContrlsState_Released +#define SWM_MMCPrevBtn_Req_SWM_ContrlsState_Released (1) +#endif + +#ifndef SWM_MMCPrevBtn_Req_SWM_ContrlsState_Reserved +#define SWM_MMCPrevBtn_Req_SWM_ContrlsState_Reserved (0) +#endif + + +// Value tables for @SWM_VoiceCntrl_Req signal + +#ifndef SWM_VoiceCntrl_Req_SWM_ContrlsState_Failure +#define SWM_VoiceCntrl_Req_SWM_ContrlsState_Failure (3) +#endif + +#ifndef SWM_VoiceCntrl_Req_SWM_ContrlsState_Pressed +#define SWM_VoiceCntrl_Req_SWM_ContrlsState_Pressed (2) +#endif + +#ifndef SWM_VoiceCntrl_Req_SWM_ContrlsState_Released +#define SWM_VoiceCntrl_Req_SWM_ContrlsState_Released (1) +#endif + +#ifndef SWM_VoiceCntrl_Req_SWM_ContrlsState_Reserved +#define SWM_VoiceCntrl_Req_SWM_ContrlsState_Reserved (0) +#endif + + +// Value tables for @SWM_VolumeUpBtn_Req signal + +#ifndef SWM_VolumeUpBtn_Req_SWM_ContrlsState_Failure +#define SWM_VolumeUpBtn_Req_SWM_ContrlsState_Failure (3) +#endif + +#ifndef SWM_VolumeUpBtn_Req_SWM_ContrlsState_Pressed +#define SWM_VolumeUpBtn_Req_SWM_ContrlsState_Pressed (2) +#endif + +#ifndef SWM_VolumeUpBtn_Req_SWM_ContrlsState_Released +#define SWM_VolumeUpBtn_Req_SWM_ContrlsState_Released (1) +#endif + +#ifndef SWM_VolumeUpBtn_Req_SWM_ContrlsState_Reserved +#define SWM_VolumeUpBtn_Req_SWM_ContrlsState_Reserved (0) +#endif + + +// Value tables for @SWM_VolumeDownBtn_Req signal + +#ifndef SWM_VolumeDownBtn_Req_SWM_ContrlsState_Failure +#define SWM_VolumeDownBtn_Req_SWM_ContrlsState_Failure (3) +#endif + +#ifndef SWM_VolumeDownBtn_Req_SWM_ContrlsState_Pressed +#define SWM_VolumeDownBtn_Req_SWM_ContrlsState_Pressed (2) +#endif + +#ifndef SWM_VolumeDownBtn_Req_SWM_ContrlsState_Released +#define SWM_VolumeDownBtn_Req_SWM_ContrlsState_Released (1) +#endif + +#ifndef SWM_VolumeDownBtn_Req_SWM_ContrlsState_Reserved +#define SWM_VolumeDownBtn_Req_SWM_ContrlsState_Reserved (0) +#endif + + +// Value tables for @SWM_VolumeMute_Req signal + +#ifndef SWM_VolumeMute_Req_SWM_ContrlsState_Failure +#define SWM_VolumeMute_Req_SWM_ContrlsState_Failure (3) +#endif + +#ifndef SWM_VolumeMute_Req_SWM_ContrlsState_Pressed +#define SWM_VolumeMute_Req_SWM_ContrlsState_Pressed (2) +#endif + +#ifndef SWM_VolumeMute_Req_SWM_ContrlsState_Released +#define SWM_VolumeMute_Req_SWM_ContrlsState_Released (1) +#endif + +#ifndef SWM_VolumeMute_Req_SWM_ContrlsState_Reserved +#define SWM_VolumeMute_Req_SWM_ContrlsState_Reserved (0) +#endif + + +// Value tables for @SWM_UpshiftPaddle_Req signal + +#ifndef SWM_UpshiftPaddle_Req_SWM_ContrlsState_Failure +#define SWM_UpshiftPaddle_Req_SWM_ContrlsState_Failure (3) +#endif + +#ifndef SWM_UpshiftPaddle_Req_SWM_ContrlsState_Pressed +#define SWM_UpshiftPaddle_Req_SWM_ContrlsState_Pressed (2) +#endif + +#ifndef SWM_UpshiftPaddle_Req_SWM_ContrlsState_Reserved +#define SWM_UpshiftPaddle_Req_SWM_ContrlsState_Reserved (0) +#endif + +#ifndef SWM_UpshiftPaddle_Req_SWM_ContrlsState_Released +#define SWM_UpshiftPaddle_Req_SWM_ContrlsState_Released (1) +#endif + + +// Value tables for @SWM_DownshiftPaddle_Req signal + +#ifndef SWM_DownshiftPaddle_Req_SWM_ContrlsState_Failure +#define SWM_DownshiftPaddle_Req_SWM_ContrlsState_Failure (3) +#endif + +#ifndef SWM_DownshiftPaddle_Req_SWM_ContrlsState_Pressed +#define SWM_DownshiftPaddle_Req_SWM_ContrlsState_Pressed (2) +#endif + +#ifndef SWM_DownshiftPaddle_Req_SWM_ContrlsState_Reserved +#define SWM_DownshiftPaddle_Req_SWM_ContrlsState_Reserved (0) +#endif + +#ifndef SWM_DownshiftPaddle_Req_SWM_ContrlsState_Released +#define SWM_DownshiftPaddle_Req_SWM_ContrlsState_Released (1) +#endif + + +// Value tables for @SWM_Heating_Stat signal + +#ifndef SWM_Heating_Stat_SWM_ContrlsState_Reserved +#define SWM_Heating_Stat_SWM_ContrlsState_Reserved (3) +#endif + +#ifndef SWM_Heating_Stat_SWM_ContrlsState_Failure +#define SWM_Heating_Stat_SWM_ContrlsState_Failure (2) +#endif + +#ifndef SWM_Heating_Stat_SWM_ContrlsState_Heating_active +#define SWM_Heating_Stat_SWM_ContrlsState_Heating_active (1) +#endif + +#ifndef SWM_Heating_Stat_SWM_ContrlsState_Heating_inactive +#define SWM_Heating_Stat_SWM_ContrlsState_Heating_inactive (0) +#endif + + +// Value tables for @SWM_PosHand_Stat signal + +#ifndef SWM_PosHand_Stat_SWM_ContrlsState_Not_on_steereng_wheel +#define SWM_PosHand_Stat_SWM_ContrlsState_Not_on_steereng_wheel (1) +#endif + +#ifndef SWM_PosHand_Stat_SWM_ContrlsState_On_steering_wheel +#define SWM_PosHand_Stat_SWM_ContrlsState_On_steering_wheel (0) +#endif + +#ifndef SWM_PosHand_Stat_SWM_ContrlsState_Reserved +#define SWM_PosHand_Stat_SWM_ContrlsState_Reserved (3) +#endif + +#ifndef SWM_PosHand_Stat_SWM_ContrlsState_Failure +#define SWM_PosHand_Stat_SWM_ContrlsState_Failure (2) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Press change mode ACC or CC or LIM + // 3 : "Failure" + // 2 : "Pressed" + // 0 : "Reserved" + // 1 : "Released" + uint8_t SWM_MODE_Req : 2; // Bits= 2 + + // Press activate/switch on stand by mode (ACC/CC/LIM) + // 3 : "Failure" + // 2 : "Pressed" + // 0 : "Reserved" + // 1 : "Released" + uint8_t SWM_CNCL_Req : 2; // Bits= 2 + + // Decrease ACC/CC/LIM speed value + // 3 : "Failure" + // 2 : "Pressed" + // 0 : "Reserved" + // 1 : "Released" + uint8_t SWM_ACCSpeedDecrease_Req : 2; // Bits= 2 + + // Increase ACC/CC/LIM speed value + // 3 : "Failure" + // 2 : "Pressed" + // 0 : "Reserved" + // 1 : "Released" + uint8_t SWM_ACCSpeedIncrease_Req : 2; // Bits= 2 + + // User's choosen MMC function switch + // 3 : "Failure" + // 2 : "Pressed" + // 0 : "Reserved" + // 1 : "Released" + uint8_t SWM_UserFunc_Req : 2; // Bits= 2 + + // Distance button pressed + // 3 : "Failure" + // 2 : "Pressed" + // 0 : "Reserved" + // 1 : "Released" + uint8_t SWM_DIS_Req : 2; // Bits= 2 + + // Press switch off/switch on stand by mode (ACC/CC/LIM) + // 3 : "Failure" + // 2 : "Pressed" + // 0 : "Reserved" + // 1 : "Released" + uint8_t SWM_RES_Req : 2; // Bits= 2 + + // Set vehicle speed ACC/CC/LIM + // 3 : "Failure" + // 2 : "Pressed" + // 0 : "Reserved" + // 1 : "Released" + uint8_t SWM_SETSpeed_Req : 2; // Bits= 2 + + // Telephone function turn on or answer incoming call + // 3 : "Failure" + // 2 : "Pressed" + // 0 : "Reserved" + // 1 : "Released" + uint8_t SWM_TELBtn_Req : 2; // Bits= 2 + + // Call IC's main menu + // 3 : "Failure" + // 2 : "Pressed" + // 0 : "Reserved" + // 1 : "Released" + uint8_t SWM_Home_Req : 2; // Bits= 2 + + // Go back IC's menu + // 3 : "Failure" + // 2 : "Pressed" + // 0 : "Reserved" + // 1 : "Released" + uint8_t SWM_Back_Req : 2; // Bits= 2 + + // Show next IC's menu + // 3 : "Failure" + // 2 : "Pressed" + // 0 : "Reserved" + // 1 : "Released" + uint8_t SWM_ICNextBtn_Req : 2; // Bits= 2 + + // Show previous IC's menu + // 3 : "Failure" + // 2 : "Pressed" + // 0 : "Reserved" + // 1 : "Released" + uint8_t SWM_ICPrevBtn_Req : 2; // Bits= 2 + + // Move up in selected menu + // 3 : "Failure" + // 2 : "Pressed" + // 0 : "Reserved" + // 1 : "Released" + uint8_t SWM_ICUpBtn_Req : 2; // Bits= 2 + + // Move down in selected menu + // 3 : "Failure" + // 2 : "Pressed" + // 0 : "Reserved" + // 1 : "Released" + uint8_t SWM_ICDownBtn_Req : 2; // Bits= 2 + + // Activate selected menu + // 3 : "Failure" + // 2 : "Pressed" + // 0 : "Reserved" + // 1 : "Released" + uint8_t SWM_ICConfBtn_Req : 2; // Bits= 2 + + // MMC control + // 3 : "Failure" + // 2 : "Pressed" + // 1 : "Released" + // 0 : "Reserved" + uint8_t SWM_MMCNextBtn_Req : 2; // Bits= 2 + + // MMC control + // 3 : "Failure" + // 2 : "Pressed" + // 1 : "Released" + // 0 : "Reserved" + uint8_t SWM_MMCPrevBtn_Req : 2; // Bits= 2 + + // Call Voice control + // 3 : "Failure" + // 2 : "Pressed" + // 1 : "Released" + // 0 : "Reserved" + uint8_t SWM_VoiceCntrl_Req : 2; // Bits= 2 + + // Volume up + // 3 : "Failure" + // 2 : "Pressed" + // 1 : "Released" + // 0 : "Reserved" + uint8_t SWM_VolumeUpBtn_Req : 2; // Bits= 2 + + // Volume down + // 3 : "Failure" + // 2 : "Pressed" + // 1 : "Released" + // 0 : "Reserved" + uint8_t SWM_VolumeDownBtn_Req : 2; // Bits= 2 + + // Mute active + // 3 : "Failure" + // 2 : "Pressed" + // 1 : "Released" + // 0 : "Reserved" + uint8_t SWM_VolumeMute_Req : 2; // Bits= 2 + + // Indicates a driver request for changing up a gear via the steering wheel paddle: + // 0x0 = Reserved + // 0x1 = Released + // 0x2 = Pressed + // 0x3 = Failure + // 3 : "Failure" + // 2 : "Pressed" + // 0 : "Reserved" + // 1 : "Released" + uint8_t SWM_UpshiftPaddle_Req : 2; // Bits= 2 + + // Indicates a driver request for changing down a gear via the steering wheel paddle: + // 0x0 = Reserved + // 0x1 = Released + // 0x2 = Pressed + // 0x3 = Failure + // 3 : "Failure" + // 2 : "Pressed" + // 0 : "Reserved" + // 1 : "Released" + uint8_t SWM_DownshiftPaddle_Req : 2; // Bits= 2 + + // Rolling Counter [0 - 15] + uint8_t SWM_ContrlsState_RC : 4; // Bits= 4 + + // Steering wheel heating status + // 3 : "Reserved" + // 2 : "Failure" + // 1 : "Heating active" + // 0 : "Heating inactive" + uint8_t SWM_Heating_Stat : 2; // Bits= 2 + + // Hand position on steering wheel status signal + // 1 : "Not on steereng wheel" + // 0 : "On steering wheel" + // 3 : "Reserved" + // 2 : "Failure" + uint8_t SWM_PosHand_Stat : 2; // Bits= 2 + + // Checksum XOR8 of the data field this message + // Checksum computed as per XOR algorithm: + // Byte 1 XOR byte 2 .... XOR byte n-1. (n = packet length.) + uint8_t SWM_ContrlsState_CS; // Bits= 8 + +#else + + // Press change mode ACC or CC or LIM + // 3 : "Failure" + // 2 : "Pressed" + // 0 : "Reserved" + // 1 : "Released" + uint8_t SWM_MODE_Req; // Bits= 2 + + // Press activate/switch on stand by mode (ACC/CC/LIM) + // 3 : "Failure" + // 2 : "Pressed" + // 0 : "Reserved" + // 1 : "Released" + uint8_t SWM_CNCL_Req; // Bits= 2 + + // Decrease ACC/CC/LIM speed value + // 3 : "Failure" + // 2 : "Pressed" + // 0 : "Reserved" + // 1 : "Released" + uint8_t SWM_ACCSpeedDecrease_Req; // Bits= 2 + + // Increase ACC/CC/LIM speed value + // 3 : "Failure" + // 2 : "Pressed" + // 0 : "Reserved" + // 1 : "Released" + uint8_t SWM_ACCSpeedIncrease_Req; // Bits= 2 + + // User's choosen MMC function switch + // 3 : "Failure" + // 2 : "Pressed" + // 0 : "Reserved" + // 1 : "Released" + uint8_t SWM_UserFunc_Req; // Bits= 2 + + // Distance button pressed + // 3 : "Failure" + // 2 : "Pressed" + // 0 : "Reserved" + // 1 : "Released" + uint8_t SWM_DIS_Req; // Bits= 2 + + // Press switch off/switch on stand by mode (ACC/CC/LIM) + // 3 : "Failure" + // 2 : "Pressed" + // 0 : "Reserved" + // 1 : "Released" + uint8_t SWM_RES_Req; // Bits= 2 + + // Set vehicle speed ACC/CC/LIM + // 3 : "Failure" + // 2 : "Pressed" + // 0 : "Reserved" + // 1 : "Released" + uint8_t SWM_SETSpeed_Req; // Bits= 2 + + // Telephone function turn on or answer incoming call + // 3 : "Failure" + // 2 : "Pressed" + // 0 : "Reserved" + // 1 : "Released" + uint8_t SWM_TELBtn_Req; // Bits= 2 + + // Call IC's main menu + // 3 : "Failure" + // 2 : "Pressed" + // 0 : "Reserved" + // 1 : "Released" + uint8_t SWM_Home_Req; // Bits= 2 + + // Go back IC's menu + // 3 : "Failure" + // 2 : "Pressed" + // 0 : "Reserved" + // 1 : "Released" + uint8_t SWM_Back_Req; // Bits= 2 + + // Show next IC's menu + // 3 : "Failure" + // 2 : "Pressed" + // 0 : "Reserved" + // 1 : "Released" + uint8_t SWM_ICNextBtn_Req; // Bits= 2 + + // Show previous IC's menu + // 3 : "Failure" + // 2 : "Pressed" + // 0 : "Reserved" + // 1 : "Released" + uint8_t SWM_ICPrevBtn_Req; // Bits= 2 + + // Move up in selected menu + // 3 : "Failure" + // 2 : "Pressed" + // 0 : "Reserved" + // 1 : "Released" + uint8_t SWM_ICUpBtn_Req; // Bits= 2 + + // Move down in selected menu + // 3 : "Failure" + // 2 : "Pressed" + // 0 : "Reserved" + // 1 : "Released" + uint8_t SWM_ICDownBtn_Req; // Bits= 2 + + // Activate selected menu + // 3 : "Failure" + // 2 : "Pressed" + // 0 : "Reserved" + // 1 : "Released" + uint8_t SWM_ICConfBtn_Req; // Bits= 2 + + // MMC control + // 3 : "Failure" + // 2 : "Pressed" + // 1 : "Released" + // 0 : "Reserved" + uint8_t SWM_MMCNextBtn_Req; // Bits= 2 + + // MMC control + // 3 : "Failure" + // 2 : "Pressed" + // 1 : "Released" + // 0 : "Reserved" + uint8_t SWM_MMCPrevBtn_Req; // Bits= 2 + + // Call Voice control + // 3 : "Failure" + // 2 : "Pressed" + // 1 : "Released" + // 0 : "Reserved" + uint8_t SWM_VoiceCntrl_Req; // Bits= 2 + + // Volume up + // 3 : "Failure" + // 2 : "Pressed" + // 1 : "Released" + // 0 : "Reserved" + uint8_t SWM_VolumeUpBtn_Req; // Bits= 2 + + // Volume down + // 3 : "Failure" + // 2 : "Pressed" + // 1 : "Released" + // 0 : "Reserved" + uint8_t SWM_VolumeDownBtn_Req; // Bits= 2 + + // Mute active + // 3 : "Failure" + // 2 : "Pressed" + // 1 : "Released" + // 0 : "Reserved" + uint8_t SWM_VolumeMute_Req; // Bits= 2 + + // Indicates a driver request for changing up a gear via the steering wheel paddle: + // 0x0 = Reserved + // 0x1 = Released + // 0x2 = Pressed + // 0x3 = Failure + // 3 : "Failure" + // 2 : "Pressed" + // 0 : "Reserved" + // 1 : "Released" + uint8_t SWM_UpshiftPaddle_Req; // Bits= 2 + + // Indicates a driver request for changing down a gear via the steering wheel paddle: + // 0x0 = Reserved + // 0x1 = Released + // 0x2 = Pressed + // 0x3 = Failure + // 3 : "Failure" + // 2 : "Pressed" + // 0 : "Reserved" + // 1 : "Released" + uint8_t SWM_DownshiftPaddle_Req; // Bits= 2 + + // Rolling Counter [0 - 15] + uint8_t SWM_ContrlsState_RC; // Bits= 4 + + // Steering wheel heating status + // 3 : "Reserved" + // 2 : "Failure" + // 1 : "Heating active" + // 0 : "Heating inactive" + uint8_t SWM_Heating_Stat; // Bits= 2 + + // Hand position on steering wheel status signal + // 1 : "Not on steereng wheel" + // 0 : "On steering wheel" + // 3 : "Reserved" + // 2 : "Failure" + uint8_t SWM_PosHand_Stat; // Bits= 2 + + // Checksum XOR8 of the data field this message + // Checksum computed as per XOR algorithm: + // Byte 1 XOR byte 2 .... XOR byte n-1. (n = packet length.) + uint8_t SWM_ContrlsState_CS; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} SWM_ContrlsState_t; + +// def @BCM_StyleCmd1 CAN Message (570 0x23a) +#define BCM_StyleCmd1_IDE (0U) +#define BCM_StyleCmd1_DLC (8U) +#define BCM_StyleCmd1_CANID (0x23aU) + +// Value tables for @BCM_ControlledZone_Stat signal + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_PRSILCU_zone_ +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_PRSILCU_zone_ (18) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Reserved +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Reserved (61) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Reserved +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Reserved (60) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Reserved +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Reserved (59) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Reserved +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Reserved (58) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Reserved +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Reserved (57) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Reserved +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Reserved (56) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Reserved +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Reserved (55) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Reserved +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Reserved (54) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Reserved +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Reserved (53) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Reserved +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Reserved (52) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Reserved +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Reserved (51) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Reserved +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Reserved (50) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Reserved +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Reserved (49) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Reserved +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Reserved (48) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Reserved +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Reserved (47) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Reserved +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Reserved (46) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_PLSILCU__PRSILCU_zone +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_PLSILCU__PRSILCU_zone (45) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Rear_deck__ICR_zone +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Rear_deck__ICR_zone (44) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Front_doors__Bpillars__partition_zone +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Front_doors__Bpillars__partition_zone (43) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Rear_doors__rear_console_zone +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Rear_doors__rear_console_zone (42) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_LBpSilCU__RBpSilCU_zone +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_LBpSilCU__RBpSilCU_zone (41) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Zone_Left_doors +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Zone_Left_doors (20) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Zone_ICS +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Zone_ICS (19) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1__color_gradient_zone +#define BCM_ControlledZone_Stat_BCM_StyleCmd1__color_gradient_zone (40) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1__color_3_channel_zone +#define BCM_ControlledZone_Stat_BCM_StyleCmd1__color_3_channel_zone (39) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1__color_2_channel_zone +#define BCM_ControlledZone_Stat_BCM_StyleCmd1__color_2_channel_zone (38) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1__color_1_channel_zone +#define BCM_ControlledZone_Stat_BCM_StyleCmd1__color_1_channel_zone (37) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_All_doors_zone +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_All_doors_zone (36) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Front_seats_zone +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Front_seats_zone (35) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_RLBSil +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_RLBSil (14) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Reserved +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Reserved (62) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Rear_Right_Zone +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Rear_Right_Zone (34) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Rear_Left_Zone +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Rear_Left_Zone (33) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Front_Right_Zone +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Front_Right_Zone (32) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Front_Left_Zone +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Front_Left_Zone (31) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Left_Zone +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Left_Zone (30) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Right_Zone +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Right_Zone (29) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Rear_Zone_ +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Rear_Zone_ (28) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Front_Zone_ +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Front_Zone_ (27) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Zone_FCSILCU +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Zone_FCSILCU (26) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Zone_RCSILCU +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Zone_RCSILCU (25) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Zone_RDSILCU +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Zone_RDSILCU (24) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Zone_Rear_doors +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Zone_Rear_doors (23) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Zone_Front_doors +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Zone_Front_doors (22) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Zone_Right_doors +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Zone_Right_doors (21) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_Reserved +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_Reserved (63) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_PLSILCU_zone +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_PLSILCU_zone (17) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_LBpSilCU +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_LBpSilCU (16) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_RBpSilCU +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_RBpSilCU (15) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_RRBSil +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_RRBSil (13) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_RDLSilCU +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_RDLSilCU (12) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_RDRSilCU +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_RDRSilCU (11) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_RCRSilCU +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_RCRSilCU (10) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_RCLSilCU +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_RCLSilCU (9) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_FCSilCUL +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_FCSilCUL (8) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_FCSilCUR +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_FCSilCUR (7) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_ICSilCUL +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_ICSilCUL (6) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_ICSilCUR +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_ICSilCUR (5) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_RLDSilCU +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_RLDSilCU (4) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_RRDSilCU +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_RRDSilCU (3) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_FLDSilCU +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_FLDSilCU (2) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_FRDSilCU +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_FRDSilCU (1) +#endif + +#ifndef BCM_ControlledZone_Stat_BCM_StyleCmd1_All_conrol_units +#define BCM_ControlledZone_Stat_BCM_StyleCmd1_All_conrol_units (0) +#endif + + +// Value tables for @BCM_ChannelNumber_Req signal + +#ifndef BCM_ChannelNumber_Req_BCM_StyleCmd1__3_and_4_channels +#define BCM_ChannelNumber_Req_BCM_StyleCmd1__3_and_4_channels (13) +#endif + +#ifndef BCM_ChannelNumber_Req_BCM_StyleCmd1__2_and_4_channels +#define BCM_ChannelNumber_Req_BCM_StyleCmd1__2_and_4_channels (12) +#endif + +#ifndef BCM_ChannelNumber_Req_BCM_StyleCmd1__2_and_3_channels +#define BCM_ChannelNumber_Req_BCM_StyleCmd1__2_and_3_channels (11) +#endif + +#ifndef BCM_ChannelNumber_Req_BCM_StyleCmd1__and_4_channels +#define BCM_ChannelNumber_Req_BCM_StyleCmd1__and_4_channels (10) +#endif + +#ifndef BCM_ChannelNumber_Req_BCM_StyleCmd1__and_4_channels +#define BCM_ChannelNumber_Req_BCM_StyleCmd1__and_4_channels (9) +#endif + +#ifndef BCM_ChannelNumber_Req_BCM_StyleCmd1__and_3_channels +#define BCM_ChannelNumber_Req_BCM_StyleCmd1__and_3_channels (8) +#endif + +#ifndef BCM_ChannelNumber_Req_BCM_StyleCmd1__3_and_4_channels +#define BCM_ChannelNumber_Req_BCM_StyleCmd1__3_and_4_channels (14) +#endif + +#ifndef BCM_ChannelNumber_Req_BCM_StyleCmd1__and_4_channels +#define BCM_ChannelNumber_Req_BCM_StyleCmd1__and_4_channels (7) +#endif + +#ifndef BCM_ChannelNumber_Req_BCM_StyleCmd1__and_3_channels +#define BCM_ChannelNumber_Req_BCM_StyleCmd1__and_3_channels (6) +#endif + +#ifndef BCM_ChannelNumber_Req_BCM_StyleCmd1__and_2_channels +#define BCM_ChannelNumber_Req_BCM_StyleCmd1__and_2_channels (5) +#endif + +#ifndef BCM_ChannelNumber_Req_BCM_StyleCmd1__4th_channel +#define BCM_ChannelNumber_Req_BCM_StyleCmd1__4th_channel (4) +#endif + +#ifndef BCM_ChannelNumber_Req_BCM_StyleCmd1__3rd_channel +#define BCM_ChannelNumber_Req_BCM_StyleCmd1__3rd_channel (3) +#endif + +#ifndef BCM_ChannelNumber_Req_BCM_StyleCmd1__2nd_channel +#define BCM_ChannelNumber_Req_BCM_StyleCmd1__2nd_channel (2) +#endif + +#ifndef BCM_ChannelNumber_Req_BCM_StyleCmd1__1st_channel +#define BCM_ChannelNumber_Req_BCM_StyleCmd1__1st_channel (1) +#endif + +#ifndef BCM_ChannelNumber_Req_BCM_StyleCmd1__All_channels +#define BCM_ChannelNumber_Req_BCM_StyleCmd1__All_channels (0) +#endif + + +// Value tables for @BCM_ModuleConfiguration_Stat signal + +#ifndef BCM_ModuleConfiguration_Stat_BCM_StyleCmd1__Set_soft_via_bootloader +#define BCM_ModuleConfiguration_Stat_BCM_StyleCmd1__Set_soft_via_bootloader (7) +#endif + +#ifndef BCM_ModuleConfiguration_Stat_BCM_StyleCmd1__Reserved +#define BCM_ModuleConfiguration_Stat_BCM_StyleCmd1__Reserved (6) +#endif + +#ifndef BCM_ModuleConfiguration_Stat_BCM_StyleCmd1__Reserved +#define BCM_ModuleConfiguration_Stat_BCM_StyleCmd1__Reserved (5) +#endif + +#ifndef BCM_ModuleConfiguration_Stat_BCM_StyleCmd1__Send_module_temperature +#define BCM_ModuleConfiguration_Stat_BCM_StyleCmd1__Send_module_temperature (4) +#endif + +#ifndef BCM_ModuleConfiguration_Stat_BCM_StyleCmd1__Send_module_state +#define BCM_ModuleConfiguration_Stat_BCM_StyleCmd1__Send_module_state (3) +#endif + +#ifndef BCM_ModuleConfiguration_Stat_BCM_StyleCmd1__Configuration_mode +#define BCM_ModuleConfiguration_Stat_BCM_StyleCmd1__Configuration_mode (2) +#endif + +#ifndef BCM_ModuleConfiguration_Stat_BCM_StyleCmd1__Turn_on_modules +#define BCM_ModuleConfiguration_Stat_BCM_StyleCmd1__Turn_on_modules (1) +#endif + +#ifndef BCM_ModuleConfiguration_Stat_BCM_StyleCmd1__Turn_off_modules +#define BCM_ModuleConfiguration_Stat_BCM_StyleCmd1__Turn_off_modules (0) +#endif + + +// Value tables for @BCM_ScenarioBrightness_Val signal + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved (124) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved (123) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved (122) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved (121) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved (120) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved (119) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved (118) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved (117) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved (116) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved (115) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved (114) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved (113) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved (112) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved (111) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved (110) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved (109) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved (108) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved (107) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved (106) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved (105) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved (104) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved (103) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved (102) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (98) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (97) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (96) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (95) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (94) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (93) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (92) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (91) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (90) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (89) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (88) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (87) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (86) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (85) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (84) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (83) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (82) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (81) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (80) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (79) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (78) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (77) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (76) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (75) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (74) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (73) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (72) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (71) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (70) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (69) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (68) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (67) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (66) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (65) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (64) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (63) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (62) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (61) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (60) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (59) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (58) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (57) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (56) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (55) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (54) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (53) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (52) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (51) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (50) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (49) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (48) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (47) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (46) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (45) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (44) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (43) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (42) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (41) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (40) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (39) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (38) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (37) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (36) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (35) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (34) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (33) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (32) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (31) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (30) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (29) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (28) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (27) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (26) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (25) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (24) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (23) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (22) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (21) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (20) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (19) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (18) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (17) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (16) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (15) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (14) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (13) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (12) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (11) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (10) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (9) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (8) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (7) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (6) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (5) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (4) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (3) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (2) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved (125) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved (127) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved (126) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1__Reserved (101) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1__100 +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1__100 (100) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1_ (99) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1__1 +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1__1 (1) +#endif + +#ifndef BCM_ScenarioBrightness_Val_BCM_StyleCmd1__0 +#define BCM_ScenarioBrightness_Val_BCM_StyleCmd1__0 (0) +#endif + + +// Value tables for @BCM_Reserved5 signal + +#ifndef BCM_Reserved5_BCM_StyleCmd1__Value +#define BCM_Reserved5_BCM_StyleCmd1__Value (63) +#endif + +#ifndef BCM_Reserved5_BCM_StyleCmd1__Value +#define BCM_Reserved5_BCM_StyleCmd1__Value (1) +#endif + +#ifndef BCM_Reserved5_BCM_StyleCmd1__Value +#define BCM_Reserved5_BCM_StyleCmd1__Value (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Indicates, which module used for current action + // 18 : "PRSILCU zone " + // 61 : "Reserved" + // 60 : "Reserved" + // 59 : "Reserved" + // 58 : "Reserved" + // 57 : "Reserved" + // 56 : "Reserved" + // 55 : "Reserved" + // 54 : "Reserved" + // 53 : "Reserved" + // 52 : "Reserved" + // 51 : "Reserved" + // 50 : "Reserved" + // 49 : "Reserved" + // 48 : "Reserved" + // 47 : "Reserved" + // 46 : "Reserved" + // 45 : "PLSILCU + PRSILCU zone" + // 44 : "Rear deck & ICR zone" + // 43 : "Front doors & B-pillars & partition zone" + // 42 : "Rear doors & rear console zone" + // 41 : "LB-pSilCU + RB-pSilCU zone" + // 20 : "Zone Left doors" + // 19 : "Zone ICS" + // 40 : "2 color gradient zone" + // 39 : "1 color 3 channel zone" + // 38 : "1 color 2 channel zone" + // 37 : "1 color 1 channel zone" + // 36 : "All doors zone" + // 35 : "Front seats zone" + // 14 : "RLBSil" + // 62 : "Reserved" + // 34 : "Rear Right Zone" + // 33 : "Rear Left Zone" + // 32 : "Front Right Zone" + // 31 : "Front Left Zone" + // 30 : "Left Zone" + // 29 : "Right Zone" + // 28 : "Rear Zone " + // 27 : "Front Zone " + // 26 : "Zone FCSILCU" + // 25 : "Zone RCSILCU" + // 24 : "Zone RDSILCU" + // 23 : "Zone Rear doors" + // 22 : "Zone Front doors" + // 21 : "Zone Right doors" + // 63 : "Reserved" + // 17 : "PLSILCU zone" + // 16 : "LB-pSilCU" + // 15 : "RB-pSilCU" + // 13 : "RRBSil" + // 12 : "RDLSilCU" + // 11 : "RDRSilCU" + // 10 : "RCRSilCU" + // 9 : "RCLSilCU" + // 8 : "FCSilCUL" + // 7 : "FCSilCUR" + // 6 : "ICSilCUL" + // 5 : "ICSilCUR" + // 4 : "RLDSilCU" + // 3 : "RRDSilCU" + // 2 : "FLDSilCU" + // 1 : "FRDSilCU" + // 0 : "All conrol units" + uint8_t BCM_ControlledZone_Stat : 6; // Bits= 6 + + // Selected channel of style illumination control unit(s) + // 13 : "2, 3 and 4 channels" + // 12 : "1, 2 and 4 channels" + // 11 : "1, 2 and 3 channels" + // 10 : "3 and 4 channels" + // 9 : "2 and 4 channels" + // 8 : "2 and 3 channels" + // 14 : "1, 3 and 4 channels" + // 7 : "1 and 4 channels" + // 6 : "1 and 3 channels" + // 5 : "1 and 2 channels" + // 4 : " 4th channel" + // 3 : " 3rd channel" + // 2 : " 2nd channel" + // 1 : " 1st channel" + // 0 : " All channels" + uint8_t BCM_ChannelNumber_Req : 4; // Bits= 4 + + // Type of command for selected modules + // 7 : " Set soft via bootloader" + // 6 : " Reserved" + // 5 : " Reserved" + // 4 : " Send module temperature" + // 3 : " Send module state" + // 2 : " Configuration mode" + // 1 : " Turn on module/-s" + // 0 : " Turn off module/-s" + uint8_t BCM_ModuleConfiguration_Stat : 3; // Bits= 3 + + // Required level of style illumination brightness + // 124 : " Reserved" + // 123 : " Reserved" + // 122 : " Reserved" + // 121 : " Reserved" + // 120 : " Reserved" + // 119 : " Reserved" + // 118 : " Reserved" + // 117 : " Reserved" + // 116 : " Reserved" + // 115 : " Reserved" + // 114 : " Reserved" + // 113 : " Reserved" + // 112 : " Reserved" + // 111 : " Reserved" + // 110 : " Reserved" + // 109 : " Reserved" + // 108 : " Reserved" + // 107 : " Reserved" + // 106 : " Reserved" + // 105 : " Reserved" + // 104 : " Reserved" + // 103 : " Reserved" + // 102 : " Reserved" + // 98 : "98%" + // 97 : "97%" + // 96 : "96%" + // 95 : "95%" + // 94 : "94%" + // 93 : "93%" + // 92 : "92%" + // 91 : "91%" + // 90 : "90%" + // 89 : "89%" + // 88 : "88%" + // 87 : "87%" + // 86 : "86%" + // 85 : "85%" + // 84 : "84%" + // 83 : "83%" + // 82 : "82%" + // 81 : "81%" + // 80 : "80%" + // 79 : "79%" + // 78 : "78%" + // 77 : "77%" + // 76 : "76%" + // 75 : "75%" + // 74 : "74%" + // 73 : "73%" + // 72 : "72%" + // 71 : "71%" + // 70 : "70%" + // 69 : "69%" + // 68 : "68%" + // 67 : "67%" + // 66 : "66%" + // 65 : "65%" + // 64 : "64%" + // 63 : "63%" + // 62 : "62%" + // 61 : "61%" + // 60 : "60%" + // 59 : "59%" + // 58 : "58%" + // 57 : "57%" + // 56 : "56%" + // 55 : "55%" + // 54 : "54%" + // 53 : "53%" + // 52 : "52%" + // 51 : "51%" + // 50 : "50%" + // 49 : "49%" + // 48 : "48%" + // 47 : "47%" + // 46 : "46%" + // 45 : "45%" + // 44 : "44%" + // 43 : "43%" + // 42 : "42%" + // 41 : "41%" + // 40 : "40%" + // 39 : "39%" + // 38 : "38%" + // 37 : "37%" + // 36 : "36%" + // 35 : "35%" + // 34 : "34%" + // 33 : "33%" + // 32 : "32%" + // 31 : "31%" + // 30 : "30%" + // 29 : "29%" + // 28 : "28%" + // 27 : "27%" + // 26 : "26%" + // 25 : "25%" + // 24 : "24%" + // 23 : "23%" + // 22 : "22%" + // 21 : "21%" + // 20 : "20%" + // 19 : "19%" + // 18 : "18%" + // 17 : "17%" + // 16 : "16%" + // 15 : "15%" + // 14 : "14%" + // 13 : "13%" + // 12 : "12%" + // 11 : "11%" + // 10 : "10%" + // 9 : "9%" + // 8 : "8%" + // 7 : "7%" + // 6 : "6%" + // 5 : "5%" + // 4 : "4%" + // 3 : "3%" + // 2 : "2%" + // 125 : " Reserved" + // 127 : " Reserved" + // 126 : " Reserved" + // 101 : " Reserved" + // 100 : " 100%" + // 99 : "99%" + // 1 : " 1%" + // 0 : " 0%" + uint8_t BCM_ScenarioBrightness_Val : 7; // Bits= 7 Unit:'%' + + // Amount of messages to configure a scenario + uint8_t BCM_ConfigurationMsgAmount_Val : 6; // Bits= 6 Unit:'msg' + + // Reserved + uint8_t BCM_Reserved1; // Bits= 8 + + // Reserved + uint8_t BCM_Reserved2; // Bits= 8 + + // Reserved + uint8_t BCM_Reserved3; // Bits= 8 + + // Reserved + uint8_t BCM_Reserved4; // Bits= 8 + + // Reserved + // 63 : "63 Value" + // 1 : "1 Value" + // 0 : "0 Value" + uint8_t BCM_Reserved5 : 6; // Bits= 6 + +#else + + // Indicates, which module used for current action + // 18 : "PRSILCU zone " + // 61 : "Reserved" + // 60 : "Reserved" + // 59 : "Reserved" + // 58 : "Reserved" + // 57 : "Reserved" + // 56 : "Reserved" + // 55 : "Reserved" + // 54 : "Reserved" + // 53 : "Reserved" + // 52 : "Reserved" + // 51 : "Reserved" + // 50 : "Reserved" + // 49 : "Reserved" + // 48 : "Reserved" + // 47 : "Reserved" + // 46 : "Reserved" + // 45 : "PLSILCU + PRSILCU zone" + // 44 : "Rear deck & ICR zone" + // 43 : "Front doors & B-pillars & partition zone" + // 42 : "Rear doors & rear console zone" + // 41 : "LB-pSilCU + RB-pSilCU zone" + // 20 : "Zone Left doors" + // 19 : "Zone ICS" + // 40 : "2 color gradient zone" + // 39 : "1 color 3 channel zone" + // 38 : "1 color 2 channel zone" + // 37 : "1 color 1 channel zone" + // 36 : "All doors zone" + // 35 : "Front seats zone" + // 14 : "RLBSil" + // 62 : "Reserved" + // 34 : "Rear Right Zone" + // 33 : "Rear Left Zone" + // 32 : "Front Right Zone" + // 31 : "Front Left Zone" + // 30 : "Left Zone" + // 29 : "Right Zone" + // 28 : "Rear Zone " + // 27 : "Front Zone " + // 26 : "Zone FCSILCU" + // 25 : "Zone RCSILCU" + // 24 : "Zone RDSILCU" + // 23 : "Zone Rear doors" + // 22 : "Zone Front doors" + // 21 : "Zone Right doors" + // 63 : "Reserved" + // 17 : "PLSILCU zone" + // 16 : "LB-pSilCU" + // 15 : "RB-pSilCU" + // 13 : "RRBSil" + // 12 : "RDLSilCU" + // 11 : "RDRSilCU" + // 10 : "RCRSilCU" + // 9 : "RCLSilCU" + // 8 : "FCSilCUL" + // 7 : "FCSilCUR" + // 6 : "ICSilCUL" + // 5 : "ICSilCUR" + // 4 : "RLDSilCU" + // 3 : "RRDSilCU" + // 2 : "FLDSilCU" + // 1 : "FRDSilCU" + // 0 : "All conrol units" + uint8_t BCM_ControlledZone_Stat; // Bits= 6 + + // Selected channel of style illumination control unit(s) + // 13 : "2, 3 and 4 channels" + // 12 : "1, 2 and 4 channels" + // 11 : "1, 2 and 3 channels" + // 10 : "3 and 4 channels" + // 9 : "2 and 4 channels" + // 8 : "2 and 3 channels" + // 14 : "1, 3 and 4 channels" + // 7 : "1 and 4 channels" + // 6 : "1 and 3 channels" + // 5 : "1 and 2 channels" + // 4 : " 4th channel" + // 3 : " 3rd channel" + // 2 : " 2nd channel" + // 1 : " 1st channel" + // 0 : " All channels" + uint8_t BCM_ChannelNumber_Req; // Bits= 4 + + // Type of command for selected modules + // 7 : " Set soft via bootloader" + // 6 : " Reserved" + // 5 : " Reserved" + // 4 : " Send module temperature" + // 3 : " Send module state" + // 2 : " Configuration mode" + // 1 : " Turn on module/-s" + // 0 : " Turn off module/-s" + uint8_t BCM_ModuleConfiguration_Stat; // Bits= 3 + + // Required level of style illumination brightness + // 124 : " Reserved" + // 123 : " Reserved" + // 122 : " Reserved" + // 121 : " Reserved" + // 120 : " Reserved" + // 119 : " Reserved" + // 118 : " Reserved" + // 117 : " Reserved" + // 116 : " Reserved" + // 115 : " Reserved" + // 114 : " Reserved" + // 113 : " Reserved" + // 112 : " Reserved" + // 111 : " Reserved" + // 110 : " Reserved" + // 109 : " Reserved" + // 108 : " Reserved" + // 107 : " Reserved" + // 106 : " Reserved" + // 105 : " Reserved" + // 104 : " Reserved" + // 103 : " Reserved" + // 102 : " Reserved" + // 98 : "98%" + // 97 : "97%" + // 96 : "96%" + // 95 : "95%" + // 94 : "94%" + // 93 : "93%" + // 92 : "92%" + // 91 : "91%" + // 90 : "90%" + // 89 : "89%" + // 88 : "88%" + // 87 : "87%" + // 86 : "86%" + // 85 : "85%" + // 84 : "84%" + // 83 : "83%" + // 82 : "82%" + // 81 : "81%" + // 80 : "80%" + // 79 : "79%" + // 78 : "78%" + // 77 : "77%" + // 76 : "76%" + // 75 : "75%" + // 74 : "74%" + // 73 : "73%" + // 72 : "72%" + // 71 : "71%" + // 70 : "70%" + // 69 : "69%" + // 68 : "68%" + // 67 : "67%" + // 66 : "66%" + // 65 : "65%" + // 64 : "64%" + // 63 : "63%" + // 62 : "62%" + // 61 : "61%" + // 60 : "60%" + // 59 : "59%" + // 58 : "58%" + // 57 : "57%" + // 56 : "56%" + // 55 : "55%" + // 54 : "54%" + // 53 : "53%" + // 52 : "52%" + // 51 : "51%" + // 50 : "50%" + // 49 : "49%" + // 48 : "48%" + // 47 : "47%" + // 46 : "46%" + // 45 : "45%" + // 44 : "44%" + // 43 : "43%" + // 42 : "42%" + // 41 : "41%" + // 40 : "40%" + // 39 : "39%" + // 38 : "38%" + // 37 : "37%" + // 36 : "36%" + // 35 : "35%" + // 34 : "34%" + // 33 : "33%" + // 32 : "32%" + // 31 : "31%" + // 30 : "30%" + // 29 : "29%" + // 28 : "28%" + // 27 : "27%" + // 26 : "26%" + // 25 : "25%" + // 24 : "24%" + // 23 : "23%" + // 22 : "22%" + // 21 : "21%" + // 20 : "20%" + // 19 : "19%" + // 18 : "18%" + // 17 : "17%" + // 16 : "16%" + // 15 : "15%" + // 14 : "14%" + // 13 : "13%" + // 12 : "12%" + // 11 : "11%" + // 10 : "10%" + // 9 : "9%" + // 8 : "8%" + // 7 : "7%" + // 6 : "6%" + // 5 : "5%" + // 4 : "4%" + // 3 : "3%" + // 2 : "2%" + // 125 : " Reserved" + // 127 : " Reserved" + // 126 : " Reserved" + // 101 : " Reserved" + // 100 : " 100%" + // 99 : "99%" + // 1 : " 1%" + // 0 : " 0%" + uint8_t BCM_ScenarioBrightness_Val; // Bits= 7 Unit:'%' + + // Amount of messages to configure a scenario + uint8_t BCM_ConfigurationMsgAmount_Val; // Bits= 6 Unit:'msg' + + // Reserved + uint8_t BCM_Reserved1; // Bits= 8 + + // Reserved + uint8_t BCM_Reserved2; // Bits= 8 + + // Reserved + uint8_t BCM_Reserved3; // Bits= 8 + + // Reserved + uint8_t BCM_Reserved4; // Bits= 8 + + // Reserved + // 63 : "63 Value" + // 1 : "1 Value" + // 0 : "0 Value" + uint8_t BCM_Reserved5; // Bits= 6 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} BCM_StyleCmd1_t; + +// def @FIU_Access_Msg1 CAN Message (578 0x242) +#define FIU_Access_Msg1_IDE (0U) +#define FIU_Access_Msg1_DLC (1U) +#define FIU_Access_Msg1_CANID (0x242U) +#define FIU_Access_Msg1_CYC (500U) + +// Value tables for @FIU_BTDevice_Stat signal + +#ifndef FIU_BTDevice_Stat_FIU_Access_Msg1_Reserved +#define FIU_BTDevice_Stat_FIU_Access_Msg1_Reserved (3) +#endif + +#ifndef FIU_BTDevice_Stat_FIU_Access_Msg1_Smartphone_Disconnected +#define FIU_BTDevice_Stat_FIU_Access_Msg1_Smartphone_Disconnected (2) +#endif + +#ifndef FIU_BTDevice_Stat_FIU_Access_Msg1_Smartphone_Connected +#define FIU_BTDevice_Stat_FIU_Access_Msg1_Smartphone_Connected (1) +#endif + +#ifndef FIU_BTDevice_Stat_FIU_Access_Msg1_Not_requested +#define FIU_BTDevice_Stat_FIU_Access_Msg1_Not_requested (0) +#endif + + +// Value tables for @FIU_NAVI_Stat signal + +#ifndef FIU_NAVI_Stat_FIU_Access_Msg1_Reserved +#define FIU_NAVI_Stat_FIU_Access_Msg1_Reserved (3) +#endif + +#ifndef FIU_NAVI_Stat_FIU_Access_Msg1_Map_error +#define FIU_NAVI_Stat_FIU_Access_Msg1_Map_error (2) +#endif + +#ifndef FIU_NAVI_Stat_FIU_Access_Msg1_Map_is_not_available +#define FIU_NAVI_Stat_FIU_Access_Msg1_Map_is_not_available (1) +#endif + +#ifndef FIU_NAVI_Stat_FIU_Access_Msg1_Not_requested +#define FIU_NAVI_Stat_FIU_Access_Msg1_Not_requested (0) +#endif + + +// Value tables for @FIU_Deleting_Req signal + +#ifndef FIU_Deleting_Req_FIU_Access_Msg1_Reserved +#define FIU_Deleting_Req_FIU_Access_Msg1_Reserved (2) +#endif + +#ifndef FIU_Deleting_Req_FIU_Access_Msg1_Smartphone_deleting_requested +#define FIU_Deleting_Req_FIU_Access_Msg1_Smartphone_deleting_requested (1) +#endif + +#ifndef FIU_Deleting_Req_FIU_Access_Msg1_Not_requested +#define FIU_Deleting_Req_FIU_Access_Msg1_Not_requested (0) +#endif + + +// Value tables for @FIU_Pairing_Req signal + +#ifndef FIU_Pairing_Req_FIU_Access_Msg1_Smartphone_pairing_requested +#define FIU_Pairing_Req_FIU_Access_Msg1_Smartphone_pairing_requested (1) +#endif + +#ifndef FIU_Pairing_Req_FIU_Access_Msg1_Not_requested +#define FIU_Pairing_Req_FIU_Access_Msg1_Not_requested (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Bluetooth device connected + // 3 : "Reserved" + // 2 : "Smartphone Disconnected" + // 1 : "Smartphone Connected" + // 0 : "Not requested" + uint8_t FIU_BTDevice_Stat : 2; // Bits= 2 + + // Navigation accessibility information + // 3 : "Reserved" + // 2 : "Map error" + // 1 : "Map is not available" + // 0 : "Not requested" + uint8_t FIU_NAVI_Stat : 2; // Bits= 2 + + // Smartphone deleting request + // 2 : "Reserved" + // 1 : "Smartphone deleting requested" + // 0 : "Not requested" + uint8_t FIU_Deleting_Req : 2; // Bits= 2 + + // Smartphone pairing request + // 1 : "Smartphone pairing requested" + // 0 : "Not requested" + uint8_t FIU_Pairing_Req : 1; // Bits= 1 + +#else + + // Bluetooth device connected + // 3 : "Reserved" + // 2 : "Smartphone Disconnected" + // 1 : "Smartphone Connected" + // 0 : "Not requested" + uint8_t FIU_BTDevice_Stat; // Bits= 2 + + // Navigation accessibility information + // 3 : "Reserved" + // 2 : "Map error" + // 1 : "Map is not available" + // 0 : "Not requested" + uint8_t FIU_NAVI_Stat; // Bits= 2 + + // Smartphone deleting request + // 2 : "Reserved" + // 1 : "Smartphone deleting requested" + // 0 : "Not requested" + uint8_t FIU_Deleting_Req; // Bits= 2 + + // Smartphone pairing request + // 1 : "Smartphone pairing requested" + // 0 : "Not requested" + uint8_t FIU_Pairing_Req; // Bits= 1 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} FIU_Access_Msg1_t; + +// def @DMFR_Msg1 CAN Message (579 0x243) +#define DMFR_Msg1_IDE (0U) +#define DMFR_Msg1_DLC (4U) +#define DMFR_Msg1_CANID (0x243U) +#define DMFR_Msg1_CYC (50U) + +// Value tables for @DMFR_WarningInd signal + +#ifndef DMFR_WarningInd_DMFR_Msg1_Warning_Active +#define DMFR_WarningInd_DMFR_Msg1_Warning_Active (1) +#endif + +#ifndef DMFR_WarningInd_DMFR_Msg1_No_Warning +#define DMFR_WarningInd_DMFR_Msg1_No_Warning (0) +#endif + + +// Value tables for @DMFR_DoorLockState signal + +#ifndef DMFR_DoorLockState_DMFR_Msg1_Fault +#define DMFR_DoorLockState_DMFR_Msg1_Fault (2) +#endif + +#ifndef DMFR_DoorLockState_DMFR_Msg1_Door_Locked +#define DMFR_DoorLockState_DMFR_Msg1_Door_Locked (1) +#endif + +#ifndef DMFR_DoorLockState_DMFR_Msg1_Door_Unlocked +#define DMFR_DoorLockState_DMFR_Msg1_Door_Unlocked (0) +#endif + + +// Value tables for @DMFR_DoorAjarState signal + +#ifndef DMFR_DoorAjarState_DMFR_Msg1_Door_Close +#define DMFR_DoorAjarState_DMFR_Msg1_Door_Close (1) +#endif + +#ifndef DMFR_DoorAjarState_DMFR_Msg1_Door_Open +#define DMFR_DoorAjarState_DMFR_Msg1_Door_Open (0) +#endif + + +// Value tables for @DMFR_DoorAjarFault_Stat signal + +#ifndef DMFR_DoorAjarFault_Stat_DMFR_Msg1_Fault_detect +#define DMFR_DoorAjarFault_Stat_DMFR_Msg1_Fault_detect (1) +#endif + +#ifndef DMFR_DoorAjarFault_Stat_DMFR_Msg1_No_fault_detect +#define DMFR_DoorAjarFault_Stat_DMFR_Msg1_No_fault_detect (0) +#endif + + +// Value tables for @DMFR_MirrorHeating_Status signal + +#ifndef DMFR_MirrorHeating_Status_DMFR_Msg1_Fault +#define DMFR_MirrorHeating_Status_DMFR_Msg1_Fault (3) +#endif + +#ifndef DMFR_MirrorHeating_Status_DMFR_Msg1_Heating_off +#define DMFR_MirrorHeating_Status_DMFR_Msg1_Heating_off (2) +#endif + +#ifndef DMFR_MirrorHeating_Status_DMFR_Msg1_Heating_on +#define DMFR_MirrorHeating_Status_DMFR_Msg1_Heating_on (1) +#endif + +#ifndef DMFR_MirrorHeating_Status_DMFR_Msg1_Unknown +#define DMFR_MirrorHeating_Status_DMFR_Msg1_Unknown (0) +#endif + + +// Value tables for @DMFR_WindowFullyClosed_Stat signal + +#ifndef DMFR_WindowFullyClosed_Stat_DMFR_Msg1_Window_fully_closed +#define DMFR_WindowFullyClosed_Stat_DMFR_Msg1_Window_fully_closed (1) +#endif + +#ifndef DMFR_WindowFullyClosed_Stat_DMFR_Msg1_Window_not_fully_closed +#define DMFR_WindowFullyClosed_Stat_DMFR_Msg1_Window_not_fully_closed (0) +#endif + + +// Value tables for @DMFR_IntDoorHandle_Req signal + +#ifndef DMFR_IntDoorHandle_Req_DMFR_Msg1_Requested +#define DMFR_IntDoorHandle_Req_DMFR_Msg1_Requested (1) +#endif + +#ifndef DMFR_IntDoorHandle_Req_DMFR_Msg1_No_request +#define DMFR_IntDoorHandle_Req_DMFR_Msg1_No_request (0) +#endif + + +// Value tables for @DMFR_IntDoorLockSw_Cmd signal + +#ifndef DMFR_IntDoorLockSw_Cmd_DMFR_Msg1_Lock_requested +#define DMFR_IntDoorLockSw_Cmd_DMFR_Msg1_Lock_requested (2) +#endif + +#ifndef DMFR_IntDoorLockSw_Cmd_DMFR_Msg1_Unlock_requested +#define DMFR_IntDoorLockSw_Cmd_DMFR_Msg1_Unlock_requested (1) +#endif + +#ifndef DMFR_IntDoorLockSw_Cmd_DMFR_Msg1_No_requested +#define DMFR_IntDoorLockSw_Cmd_DMFR_Msg1_No_requested (0) +#endif + + +// Value tables for @DMFR_ShortDrop_Stat signal + +#ifndef DMFR_ShortDrop_Stat_DMFR_Msg1_Window_above_short_drop_point +#define DMFR_ShortDrop_Stat_DMFR_Msg1_Window_above_short_drop_point (0) +#endif + +#ifndef DMFR_ShortDrop_Stat_DMFR_Msg1_Window_is_in_OR_below_short_drop_point +#define DMFR_ShortDrop_Stat_DMFR_Msg1_Window_is_in_OR_below_short_drop_point (1) +#endif + + +// Value tables for @DMFR_Comm_Req signal + +#ifndef DMFR_Comm_Req_DMFR_Msg1_Requested +#define DMFR_Comm_Req_DMFR_Msg1_Requested (1) +#endif + +#ifndef DMFR_Comm_Req_DMFR_Msg1_Not_requested +#define DMFR_Comm_Req_DMFR_Msg1_Not_requested (0) +#endif + + +// Value tables for @DMFR_DoorMovement_Stat signal + +#ifndef DMFR_DoorMovement_Stat_DMFR_Msg1_Fault +#define DMFR_DoorMovement_Stat_DMFR_Msg1_Fault (4) +#endif + +#ifndef DMFR_DoorMovement_Stat_DMFR_Msg1_Fully_open +#define DMFR_DoorMovement_Stat_DMFR_Msg1_Fully_open (3) +#endif + +#ifndef DMFR_DoorMovement_Stat_DMFR_Msg1_Intermediate +#define DMFR_DoorMovement_Stat_DMFR_Msg1_Intermediate (2) +#endif + +#ifndef DMFR_DoorMovement_Stat_DMFR_Msg1_Fully_closed +#define DMFR_DoorMovement_Stat_DMFR_Msg1_Fully_closed (1) +#endif + +#ifndef DMFR_DoorMovement_Stat_DMFR_Msg1_Unknown +#define DMFR_DoorMovement_Stat_DMFR_Msg1_Unknown (0) +#endif + + +// Value tables for @DMFR_DoorDirection_Stat signal + +#ifndef DMFR_DoorDirection_Stat_DMFR_Msg1_Closing +#define DMFR_DoorDirection_Stat_DMFR_Msg1_Closing (2) +#endif + +#ifndef DMFR_DoorDirection_Stat_DMFR_Msg1_Opening +#define DMFR_DoorDirection_Stat_DMFR_Msg1_Opening (1) +#endif + +#ifndef DMFR_DoorDirection_Stat_DMFR_Msg1_Stopped +#define DMFR_DoorDirection_Stat_DMFR_Msg1_Stopped (0) +#endif + + +// Value tables for @DMFR_Antipinch_Stat signal + +#ifndef DMFR_Antipinch_Stat_DMFR_Msg1_Pinch_detected +#define DMFR_Antipinch_Stat_DMFR_Msg1_Pinch_detected (1) +#endif + +#ifndef DMFR_Antipinch_Stat_DMFR_Msg1_Pinch_not_detected +#define DMFR_Antipinch_Stat_DMFR_Msg1_Pinch_not_detected (0) +#endif + + +// Value tables for @DMFR_BSDLed_Stat signal + +#ifndef DMFR_BSDLed_Stat_DMFR_Msg1_Error +#define DMFR_BSDLed_Stat_DMFR_Msg1_Error (1) +#endif + +#ifndef DMFR_BSDLed_Stat_DMFR_Msg1_No_error +#define DMFR_BSDLed_Stat_DMFR_Msg1_No_error (0) +#endif + + +// Value tables for @DMFR_DoorCloseSw_Req signal + +#ifndef DMFR_DoorCloseSw_Req_DMFR_Msg1_External_Door_Close_request +#define DMFR_DoorCloseSw_Req_DMFR_Msg1_External_Door_Close_request (1) +#endif + +#ifndef DMFR_DoorCloseSw_Req_DMFR_Msg1_No_Req +#define DMFR_DoorCloseSw_Req_DMFR_Msg1_No_Req (0) +#endif + + +// Value tables for @DMFR_TurnInd_Stat signal + +#ifndef DMFR_TurnInd_Stat_DMFR_Msg1_Error +#define DMFR_TurnInd_Stat_DMFR_Msg1_Error (2) +#endif + +#ifndef DMFR_TurnInd_Stat_DMFR_Msg1_On +#define DMFR_TurnInd_Stat_DMFR_Msg1_On (1) +#endif + +#ifndef DMFR_TurnInd_Stat_DMFR_Msg1_Off +#define DMFR_TurnInd_Stat_DMFR_Msg1_Off (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Request from DMFR to switch warning indicator in instrument cluster + // 1 : "Warning_Active" + // 0 : "No_Warning" + uint8_t DMFR_WarningInd : 1; // Bits= 1 + + // FR Door Lock Status + // 2 : "Fault" + // 1 : "Door_Locked" + // 0 : "Door Unlocked" + uint8_t DMFR_DoorLockState : 2; // Bits= 2 + + // FR door opening status + // 1 : "Door_Close" + // 0 : "Door_Open" + uint8_t DMFR_DoorAjarState : 1; // Bits= 1 + + // The fault status of ajar sensor in door lock + // 1 : "Fault detect" + // 0 : "No fault detect" + uint8_t DMFR_DoorAjarFault_Stat : 1; // Bits= 1 + + // FR mirror heating status + // 3 : "Fault" + // 2 : "Heating off" + // 1 : "Heating on" + // 0 : "Unknown" + uint8_t DMFR_MirrorHeating_Status : 2; // Bits= 2 + + // Completeness of window closing status + // 1 : "Window fully closed" + // 0 : "Window not fully closed" + uint8_t DMFR_WindowFullyClosed_Stat : 1; // Bits= 1 + + // State of FR door internal handle: engaged or not + // 1 : "Requested" + // 0 : "No request" + uint8_t DMFR_IntDoorHandle_Req : 1; // Bits= 1 + + // Interior door lock switch command + // 2 : "Lock requested" + // 1 : "Unlock requested" + // 0 : "No requested" + uint8_t DMFR_IntDoorLockSw_Cmd : 2; // Bits= 2 + + // FR window short drop position state + // 0 : "Window above short drop point" + // 1 : "Window is in OR below short drop point" + uint8_t DMFR_ShortDrop_Stat : 1; // Bits= 1 + + // Request to wake up the car from the FR door + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DMFR_Comm_Req : 1; // Bits= 1 + + // FR door electric drive status + // 4 : "Fault" + // 3 : "Fully open" + // 2 : "Intermediate" + // 1 : "Fully closed" + // 0 : "Unknown" + uint8_t DMFR_DoorMovement_Stat : 3; // Bits= 3 + + // Direction of movement of the FR door + // 2 : "Closing" + // 1 : "Opening" + // 0 : "Stopped" + uint8_t DMFR_DoorDirection_Stat : 2; // Bits= 2 + + // State of antipinch function of FR door + // 1 : "Pinch detected" + // 0 : "Pinch not detected" + uint8_t DMFR_Antipinch_Stat : 1; // Bits= 1 + + // FR Mirror Blind Spot Indicator Status + // 1 : "Error" + // 0 : "No error" + uint8_t DMFR_BSDLed_Stat : 1; // Bits= 1 + + // Request for power closing door from external switch on door panel + // 1 : "External Door Close request" + // 0 : "No Req" + uint8_t DMFR_DoorCloseSw_Req : 1; // Bits= 1 + + // FR turn signal repeater status + // 2 : "Error" + // 1 : "On" + // 0 : "Off" + uint8_t DMFR_TurnInd_Stat : 2; // Bits= 2 + +#else + + // Request from DMFR to switch warning indicator in instrument cluster + // 1 : "Warning_Active" + // 0 : "No_Warning" + uint8_t DMFR_WarningInd; // Bits= 1 + + // FR Door Lock Status + // 2 : "Fault" + // 1 : "Door_Locked" + // 0 : "Door Unlocked" + uint8_t DMFR_DoorLockState; // Bits= 2 + + // FR door opening status + // 1 : "Door_Close" + // 0 : "Door_Open" + uint8_t DMFR_DoorAjarState; // Bits= 1 + + // The fault status of ajar sensor in door lock + // 1 : "Fault detect" + // 0 : "No fault detect" + uint8_t DMFR_DoorAjarFault_Stat; // Bits= 1 + + // FR mirror heating status + // 3 : "Fault" + // 2 : "Heating off" + // 1 : "Heating on" + // 0 : "Unknown" + uint8_t DMFR_MirrorHeating_Status; // Bits= 2 + + // Completeness of window closing status + // 1 : "Window fully closed" + // 0 : "Window not fully closed" + uint8_t DMFR_WindowFullyClosed_Stat; // Bits= 1 + + // State of FR door internal handle: engaged or not + // 1 : "Requested" + // 0 : "No request" + uint8_t DMFR_IntDoorHandle_Req; // Bits= 1 + + // Interior door lock switch command + // 2 : "Lock requested" + // 1 : "Unlock requested" + // 0 : "No requested" + uint8_t DMFR_IntDoorLockSw_Cmd; // Bits= 2 + + // FR window short drop position state + // 0 : "Window above short drop point" + // 1 : "Window is in OR below short drop point" + uint8_t DMFR_ShortDrop_Stat; // Bits= 1 + + // Request to wake up the car from the FR door + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DMFR_Comm_Req; // Bits= 1 + + // FR door electric drive status + // 4 : "Fault" + // 3 : "Fully open" + // 2 : "Intermediate" + // 1 : "Fully closed" + // 0 : "Unknown" + uint8_t DMFR_DoorMovement_Stat; // Bits= 3 + + // Direction of movement of the FR door + // 2 : "Closing" + // 1 : "Opening" + // 0 : "Stopped" + uint8_t DMFR_DoorDirection_Stat; // Bits= 2 + + // State of antipinch function of FR door + // 1 : "Pinch detected" + // 0 : "Pinch not detected" + uint8_t DMFR_Antipinch_Stat; // Bits= 1 + + // FR Mirror Blind Spot Indicator Status + // 1 : "Error" + // 0 : "No error" + uint8_t DMFR_BSDLed_Stat; // Bits= 1 + + // Request for power closing door from external switch on door panel + // 1 : "External Door Close request" + // 0 : "No Req" + uint8_t DMFR_DoorCloseSw_Req; // Bits= 1 + + // FR turn signal repeater status + // 2 : "Error" + // 1 : "On" + // 0 : "Off" + uint8_t DMFR_TurnInd_Stat; // Bits= 2 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} DMFR_Msg1_t; + +// def @DMFL_Msg1 CAN Message (580 0x244) +#define DMFL_Msg1_IDE (0U) +#define DMFL_Msg1_DLC (8U) +#define DMFL_Msg1_CANID (0x244U) +#define DMFL_Msg1_CYC (50U) + +// Value tables for @DMFL_KeyCylinder_Req signal + +#ifndef DMFL_KeyCylinder_Req_DMFL_Msg1_Fault +#define DMFL_KeyCylinder_Req_DMFL_Msg1_Fault (3) +#endif + +#ifndef DMFL_KeyCylinder_Req_DMFL_Msg1_Lock_Req +#define DMFL_KeyCylinder_Req_DMFL_Msg1_Lock_Req (2) +#endif + +#ifndef DMFL_KeyCylinder_Req_DMFL_Msg1_Unlock_Req +#define DMFL_KeyCylinder_Req_DMFL_Msg1_Unlock_Req (1) +#endif + +#ifndef DMFL_KeyCylinder_Req_DMFL_Msg1_No_Request +#define DMFL_KeyCylinder_Req_DMFL_Msg1_No_Request (0) +#endif + + +// Value tables for @DMFL_WarningInd signal + +#ifndef DMFL_WarningInd_DMFL_Msg1_Warning_Active +#define DMFL_WarningInd_DMFL_Msg1_Warning_Active (1) +#endif + +#ifndef DMFL_WarningInd_DMFL_Msg1_No_Warning +#define DMFL_WarningInd_DMFL_Msg1_No_Warning (0) +#endif + + +// Value tables for @DMFL_DoorLockState signal + +#ifndef DMFL_DoorLockState_DMFL_Msg1_Fault +#define DMFL_DoorLockState_DMFL_Msg1_Fault (2) +#endif + +#ifndef DMFL_DoorLockState_DMFL_Msg1_Door_Locked +#define DMFL_DoorLockState_DMFL_Msg1_Door_Locked (1) +#endif + +#ifndef DMFL_DoorLockState_DMFL_Msg1_Door_Unlocked +#define DMFL_DoorLockState_DMFL_Msg1_Door_Unlocked (0) +#endif + + +// Value tables for @DMFL_DoorAjarState signal + +#ifndef DMFL_DoorAjarState_DMFL_Msg1_Door_Close +#define DMFL_DoorAjarState_DMFL_Msg1_Door_Close (1) +#endif + +#ifndef DMFL_DoorAjarState_DMFL_Msg1_Door_Open +#define DMFL_DoorAjarState_DMFL_Msg1_Door_Open (0) +#endif + + +// Value tables for @DMFL_ChildLockCentralTab_Stat signal + +#ifndef DMFL_ChildLockCentralTab_Stat_DMFL_Msg1_Function_active +#define DMFL_ChildLockCentralTab_Stat_DMFL_Msg1_Function_active (1) +#endif + +#ifndef DMFL_ChildLockCentralTab_Stat_DMFL_Msg1_Function_inactive +#define DMFL_ChildLockCentralTab_Stat_DMFL_Msg1_Function_inactive (0) +#endif + + +// Value tables for @DMFL_DoorCloseSw_Req signal + +#ifndef DMFL_DoorCloseSw_Req_DMFL_Msg1_External_Door_Close_request +#define DMFL_DoorCloseSw_Req_DMFL_Msg1_External_Door_Close_request (1) +#endif + +#ifndef DMFL_DoorCloseSw_Req_DMFL_Msg1_No_Req +#define DMFL_DoorCloseSw_Req_DMFL_Msg1_No_Req (0) +#endif + + +// Value tables for @DMFL_MirrorHeating_Status signal + +#ifndef DMFL_MirrorHeating_Status_DMFL_Msg1_Fault +#define DMFL_MirrorHeating_Status_DMFL_Msg1_Fault (3) +#endif + +#ifndef DMFL_MirrorHeating_Status_DMFL_Msg1_Heating_off +#define DMFL_MirrorHeating_Status_DMFL_Msg1_Heating_off (2) +#endif + +#ifndef DMFL_MirrorHeating_Status_DMFL_Msg1_Heating_on +#define DMFL_MirrorHeating_Status_DMFL_Msg1_Heating_on (1) +#endif + +#ifndef DMFL_MirrorHeating_Status_DMFL_Msg1_Unknown +#define DMFL_MirrorHeating_Status_DMFL_Msg1_Unknown (0) +#endif + + +// Value tables for @DMFL_IntDoorHandle_Req signal + +#ifndef DMFL_IntDoorHandle_Req_DMFL_Msg1_Requested +#define DMFL_IntDoorHandle_Req_DMFL_Msg1_Requested (1) +#endif + +#ifndef DMFL_IntDoorHandle_Req_DMFL_Msg1_No_request +#define DMFL_IntDoorHandle_Req_DMFL_Msg1_No_request (0) +#endif + + +// Value tables for @DMFL_ChildLock_RLwindow_Stat signal + +#ifndef DMFL_ChildLock_RLwindow_Stat_DMFL_Msg1_Function_active +#define DMFL_ChildLock_RLwindow_Stat_DMFL_Msg1_Function_active (1) +#endif + +#ifndef DMFL_ChildLock_RLwindow_Stat_DMFL_Msg1_Function_inactive +#define DMFL_ChildLock_RLwindow_Stat_DMFL_Msg1_Function_inactive (0) +#endif + + +// Value tables for @DMFL_ChildLockRLTab_Stat signal + +#ifndef DMFL_ChildLockRLTab_Stat_DMFL_Msg1_Function_active +#define DMFL_ChildLockRLTab_Stat_DMFL_Msg1_Function_active (1) +#endif + +#ifndef DMFL_ChildLockRLTab_Stat_DMFL_Msg1_Function_inactive +#define DMFL_ChildLockRLTab_Stat_DMFL_Msg1_Function_inactive (0) +#endif + + +// Value tables for @DMFL_IntDoorLockSw_Cmd signal + +#ifndef DMFL_IntDoorLockSw_Cmd_DMFL_Msg1_Lock_requested +#define DMFL_IntDoorLockSw_Cmd_DMFL_Msg1_Lock_requested (2) +#endif + +#ifndef DMFL_IntDoorLockSw_Cmd_DMFL_Msg1_Unlock_requested +#define DMFL_IntDoorLockSw_Cmd_DMFL_Msg1_Unlock_requested (1) +#endif + +#ifndef DMFL_IntDoorLockSw_Cmd_DMFL_Msg1_No_requested +#define DMFL_IntDoorLockSw_Cmd_DMFL_Msg1_No_requested (0) +#endif + + +// Value tables for @DMFL_ChildLockRRTab_Stat signal + +#ifndef DMFL_ChildLockRRTab_Stat_DMFL_Msg1_Function_active +#define DMFL_ChildLockRRTab_Stat_DMFL_Msg1_Function_active (1) +#endif + +#ifndef DMFL_ChildLockRRTab_Stat_DMFL_Msg1_Function_inactive +#define DMFL_ChildLockRRTab_Stat_DMFL_Msg1_Function_inactive (0) +#endif + + +// Value tables for @DMFL_FRWindow_Cmd signal + +#ifndef DMFL_FRWindow_Cmd_DMFL_Msg1_Auto_up +#define DMFL_FRWindow_Cmd_DMFL_Msg1_Auto_up (4) +#endif + +#ifndef DMFL_FRWindow_Cmd_DMFL_Msg1_Auto_down +#define DMFL_FRWindow_Cmd_DMFL_Msg1_Auto_down (3) +#endif + +#ifndef DMFL_FRWindow_Cmd_DMFL_Msg1_Manual_up +#define DMFL_FRWindow_Cmd_DMFL_Msg1_Manual_up (2) +#endif + +#ifndef DMFL_FRWindow_Cmd_DMFL_Msg1_Manual_down +#define DMFL_FRWindow_Cmd_DMFL_Msg1_Manual_down (1) +#endif + +#ifndef DMFL_FRWindow_Cmd_DMFL_Msg1_No_action +#define DMFL_FRWindow_Cmd_DMFL_Msg1_No_action (0) +#endif + + +// Value tables for @DMFL_RLWindow_Cmd signal + +#ifndef DMFL_RLWindow_Cmd_DMFL_Msg1_Auto_up +#define DMFL_RLWindow_Cmd_DMFL_Msg1_Auto_up (4) +#endif + +#ifndef DMFL_RLWindow_Cmd_DMFL_Msg1_Auto_down +#define DMFL_RLWindow_Cmd_DMFL_Msg1_Auto_down (3) +#endif + +#ifndef DMFL_RLWindow_Cmd_DMFL_Msg1_Manual_up +#define DMFL_RLWindow_Cmd_DMFL_Msg1_Manual_up (2) +#endif + +#ifndef DMFL_RLWindow_Cmd_DMFL_Msg1_Manual_down +#define DMFL_RLWindow_Cmd_DMFL_Msg1_Manual_down (1) +#endif + +#ifndef DMFL_RLWindow_Cmd_DMFL_Msg1_No_action +#define DMFL_RLWindow_Cmd_DMFL_Msg1_No_action (0) +#endif + + +// Value tables for @DMFL_RightMirrorTilt_Cmd signal + +#ifndef DMFL_RightMirrorTilt_Cmd_DMFL_Msg1_On +#define DMFL_RightMirrorTilt_Cmd_DMFL_Msg1_On (1) +#endif + +#ifndef DMFL_RightMirrorTilt_Cmd_DMFL_Msg1_Off +#define DMFL_RightMirrorTilt_Cmd_DMFL_Msg1_Off (0) +#endif + + +// Value tables for @DMFL_RRWindow_Cmd signal + +#ifndef DMFL_RRWindow_Cmd_DMFL_Msg1_Auto_up +#define DMFL_RRWindow_Cmd_DMFL_Msg1_Auto_up (4) +#endif + +#ifndef DMFL_RRWindow_Cmd_DMFL_Msg1_Auto_down +#define DMFL_RRWindow_Cmd_DMFL_Msg1_Auto_down (3) +#endif + +#ifndef DMFL_RRWindow_Cmd_DMFL_Msg1_Manual_up +#define DMFL_RRWindow_Cmd_DMFL_Msg1_Manual_up (2) +#endif + +#ifndef DMFL_RRWindow_Cmd_DMFL_Msg1_Manual_down +#define DMFL_RRWindow_Cmd_DMFL_Msg1_Manual_down (1) +#endif + +#ifndef DMFL_RRWindow_Cmd_DMFL_Msg1_No_action +#define DMFL_RRWindow_Cmd_DMFL_Msg1_No_action (0) +#endif + + +// Value tables for @DMFL_RightMirrorAdjust_Cmd signal + +#ifndef DMFL_RightMirrorAdjust_Cmd_DMFL_Msg1_Right +#define DMFL_RightMirrorAdjust_Cmd_DMFL_Msg1_Right (4) +#endif + +#ifndef DMFL_RightMirrorAdjust_Cmd_DMFL_Msg1_Left +#define DMFL_RightMirrorAdjust_Cmd_DMFL_Msg1_Left (3) +#endif + +#ifndef DMFL_RightMirrorAdjust_Cmd_DMFL_Msg1_Down +#define DMFL_RightMirrorAdjust_Cmd_DMFL_Msg1_Down (2) +#endif + +#ifndef DMFL_RightMirrorAdjust_Cmd_DMFL_Msg1_Up +#define DMFL_RightMirrorAdjust_Cmd_DMFL_Msg1_Up (1) +#endif + +#ifndef DMFL_RightMirrorAdjust_Cmd_DMFL_Msg1_No_action +#define DMFL_RightMirrorAdjust_Cmd_DMFL_Msg1_No_action (0) +#endif + + +// Value tables for @DMFL_RightMirrorFold_Cmd signal + +#ifndef DMFL_RightMirrorFold_Cmd_DMFL_Msg1_Unfold +#define DMFL_RightMirrorFold_Cmd_DMFL_Msg1_Unfold (2) +#endif + +#ifndef DMFL_RightMirrorFold_Cmd_DMFL_Msg1_Fold +#define DMFL_RightMirrorFold_Cmd_DMFL_Msg1_Fold (1) +#endif + +#ifndef DMFL_RightMirrorFold_Cmd_DMFL_Msg1_No_action +#define DMFL_RightMirrorFold_Cmd_DMFL_Msg1_No_action (0) +#endif + + +// Value tables for @DMFL_WindowFullyClosed_Stat signal + +#ifndef DMFL_WindowFullyClosed_Stat_DMFL_Msg1_Window_fully_closed +#define DMFL_WindowFullyClosed_Stat_DMFL_Msg1_Window_fully_closed (1) +#endif + +#ifndef DMFL_WindowFullyClosed_Stat_DMFL_Msg1_Window_not_fully_closed +#define DMFL_WindowFullyClosed_Stat_DMFL_Msg1_Window_not_fully_closed (0) +#endif + + +// Value tables for @DMFL_Comm_Req signal + +#ifndef DMFL_Comm_Req_DMFL_Msg1_Requested +#define DMFL_Comm_Req_DMFL_Msg1_Requested (1) +#endif + +#ifndef DMFL_Comm_Req_DMFL_Msg1_Not_requested +#define DMFL_Comm_Req_DMFL_Msg1_Not_requested (0) +#endif + + +// Value tables for @DMFL_ChildLock_Stat signal + +#ifndef DMFL_ChildLock_Stat_DMFL_Msg1_Function_active +#define DMFL_ChildLock_Stat_DMFL_Msg1_Function_active (1) +#endif + +#ifndef DMFL_ChildLock_Stat_DMFL_Msg1_Function_inactive +#define DMFL_ChildLock_Stat_DMFL_Msg1_Function_inactive (0) +#endif + + +// Value tables for @DMFL_DoorMovement_Stat signal + +#ifndef DMFL_DoorMovement_Stat_DMFL_Msg1_Fault +#define DMFL_DoorMovement_Stat_DMFL_Msg1_Fault (4) +#endif + +#ifndef DMFL_DoorMovement_Stat_DMFL_Msg1_Fully_open +#define DMFL_DoorMovement_Stat_DMFL_Msg1_Fully_open (3) +#endif + +#ifndef DMFL_DoorMovement_Stat_DMFL_Msg1_Intermediate +#define DMFL_DoorMovement_Stat_DMFL_Msg1_Intermediate (2) +#endif + +#ifndef DMFL_DoorMovement_Stat_DMFL_Msg1_Fully_closed +#define DMFL_DoorMovement_Stat_DMFL_Msg1_Fully_closed (1) +#endif + +#ifndef DMFL_DoorMovement_Stat_DMFL_Msg1_Unknown +#define DMFL_DoorMovement_Stat_DMFL_Msg1_Unknown (0) +#endif + + +// Value tables for @DMFL_Antipinch_Stat signal + +#ifndef DMFL_Antipinch_Stat_DMFL_Msg1_Pinch_detected +#define DMFL_Antipinch_Stat_DMFL_Msg1_Pinch_detected (1) +#endif + +#ifndef DMFL_Antipinch_Stat_DMFL_Msg1_Pinch_not_detected +#define DMFL_Antipinch_Stat_DMFL_Msg1_Pinch_not_detected (0) +#endif + + +// Value tables for @DMFL_DoorDirection_Stat signal + +#ifndef DMFL_DoorDirection_Stat_DMFL_Msg1_Closing +#define DMFL_DoorDirection_Stat_DMFL_Msg1_Closing (2) +#endif + +#ifndef DMFL_DoorDirection_Stat_DMFL_Msg1_Opening +#define DMFL_DoorDirection_Stat_DMFL_Msg1_Opening (1) +#endif + +#ifndef DMFL_DoorDirection_Stat_DMFL_Msg1_Stopped +#define DMFL_DoorDirection_Stat_DMFL_Msg1_Stopped (0) +#endif + + +// Value tables for @DMFL_BSDLed_Stat signal + +#ifndef DMFL_BSDLed_Stat_DMFL_Msg1_Error +#define DMFL_BSDLed_Stat_DMFL_Msg1_Error (1) +#endif + +#ifndef DMFL_BSDLed_Stat_DMFL_Msg1_No_error +#define DMFL_BSDLed_Stat_DMFL_Msg1_No_error (0) +#endif + + +// Value tables for @DMFL_DoorAjarFault_Stat signal + +#ifndef DMFL_DoorAjarFault_Stat_DMFL_Msg1_Fault_detect +#define DMFL_DoorAjarFault_Stat_DMFL_Msg1_Fault_detect (1) +#endif + +#ifndef DMFL_DoorAjarFault_Stat_DMFL_Msg1_No_fault_detect +#define DMFL_DoorAjarFault_Stat_DMFL_Msg1_No_fault_detect (0) +#endif + + +// Value tables for @DMFL_ShortDrop_Stat signal + +#ifndef DMFL_ShortDrop_Stat_DMFL_Msg1_Window_above_short_drop_point +#define DMFL_ShortDrop_Stat_DMFL_Msg1_Window_above_short_drop_point (0) +#endif + +#ifndef DMFL_ShortDrop_Stat_DMFL_Msg1_Window_is_in_OR_below_short_drop_point +#define DMFL_ShortDrop_Stat_DMFL_Msg1_Window_is_in_OR_below_short_drop_point (1) +#endif + + +// Value tables for @DMFL_TurnInd_Stat signal + +#ifndef DMFL_TurnInd_Stat_DMFL_Msg1_Error +#define DMFL_TurnInd_Stat_DMFL_Msg1_Error (2) +#endif + +#ifndef DMFL_TurnInd_Stat_DMFL_Msg1_On +#define DMFL_TurnInd_Stat_DMFL_Msg1_On (1) +#endif + +#ifndef DMFL_TurnInd_Stat_DMFL_Msg1_Off +#define DMFL_TurnInd_Stat_DMFL_Msg1_Off (0) +#endif + + +// Value tables for @DMFL_ChildLock_RRwindow_Stat signal + +#ifndef DMFL_ChildLock_RRwindow_Stat_DMFL_Msg1_Function_active +#define DMFL_ChildLock_RRwindow_Stat_DMFL_Msg1_Function_active (1) +#endif + +#ifndef DMFL_ChildLock_RRwindow_Stat_DMFL_Msg1_Function_inactive +#define DMFL_ChildLock_RRwindow_Stat_DMFL_Msg1_Function_inactive (0) +#endif + + +// Value tables for @DMFL_RearWindowCurtain_Req signal + +#ifndef DMFL_RearWindowCurtain_Req_DMFL_Msg1_Short_pressed +#define DMFL_RearWindowCurtain_Req_DMFL_Msg1_Short_pressed (1) +#endif + +#ifndef DMFL_RearWindowCurtain_Req_DMFL_Msg1_Not_requested +#define DMFL_RearWindowCurtain_Req_DMFL_Msg1_Not_requested (0) +#endif + +#ifndef DMFL_RearWindowCurtain_Req_DMFL_Msg1_Long_pressed +#define DMFL_RearWindowCurtain_Req_DMFL_Msg1_Long_pressed (2) +#endif + + +// Value tables for @DMFL_ChildLock_RLdoor_Stat signal + +#ifndef DMFL_ChildLock_RLdoor_Stat_DMFL_Msg1_Function_active +#define DMFL_ChildLock_RLdoor_Stat_DMFL_Msg1_Function_active (1) +#endif + +#ifndef DMFL_ChildLock_RLdoor_Stat_DMFL_Msg1_Function_inactive +#define DMFL_ChildLock_RLdoor_Stat_DMFL_Msg1_Function_inactive (0) +#endif + + +// Value tables for @DMFL_ChildLock_RRdoor_Stat signal + +#ifndef DMFL_ChildLock_RRdoor_Stat_DMFL_Msg1_Function_active +#define DMFL_ChildLock_RRdoor_Stat_DMFL_Msg1_Function_active (1) +#endif + +#ifndef DMFL_ChildLock_RRdoor_Stat_DMFL_Msg1_Function_inactive +#define DMFL_ChildLock_RRdoor_Stat_DMFL_Msg1_Function_inactive (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Request from the door lock cylinder + // 3 : "Fault" + // 2 : "Lock_Req" + // 1 : "Unlock_Req" + // 0 : "No_Request" + uint8_t DMFL_KeyCylinder_Req : 2; // Bits= 2 + + // Request from DMFL to switch warning indicator in instrument cluster + // 1 : "Warning_Active" + // 0 : "No_Warning" + uint8_t DMFL_WarningInd : 1; // Bits= 1 + + // FL Door Lock Status + // 2 : "Fault" + // 1 : "Door_Locked" + // 0 : "Door Unlocked" + uint8_t DMFL_DoorLockState : 2; // Bits= 2 + + // FL door opening status + // 1 : "Door_Close" + // 0 : "Door_Open" + uint8_t DMFL_DoorAjarState : 1; // Bits= 1 + + // State of Child lock function for central tab + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t DMFL_ChildLockCentralTab_Stat : 1; // Bits= 1 + + // Request for power closing door from external switch on door panel + // 1 : "External Door Close request" + // 0 : "No Req" + uint8_t DMFL_DoorCloseSw_Req : 1; // Bits= 1 + + // FL mirror heating status + // 3 : "Fault" + // 2 : "Heating off" + // 1 : "Heating on" + // 0 : "Unknown" + uint8_t DMFL_MirrorHeating_Status : 2; // Bits= 2 + + // State of FL door internal handle: engaged or not + // 1 : "Requested" + // 0 : "No request" + uint8_t DMFL_IntDoorHandle_Req : 1; // Bits= 1 + + // Disable RL Window control + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t DMFL_ChildLock_RLwindow_Stat : 1; // Bits= 1 + + // State of Child lock function for rear left tab + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t DMFL_ChildLockRLTab_Stat : 1; // Bits= 1 + + // Interior door lock switch command + // 2 : "Lock requested" + // 1 : "Unlock requested" + // 0 : "No requested" + uint8_t DMFL_IntDoorLockSw_Cmd : 2; // Bits= 2 + + // State of Child lock function for rear right tab + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t DMFL_ChildLockRRTab_Stat : 1; // Bits= 1 + + // FR Window move command + // 4 : "Auto up" + // 3 : "Auto down" + // 2 : "Manual up" + // 1 : "Manual down" + // 0 : "No action" + uint8_t DMFL_FRWindow_Cmd : 3; // Bits= 3 + + // RL Window move command + // 4 : "Auto up" + // 3 : "Auto down" + // 2 : "Manual up" + // 1 : "Manual down" + // 0 : "No action" + uint8_t DMFL_RLWindow_Cmd : 3; // Bits= 3 + + // Right mirror tilt command + // 1 : "On" + // 0 : "Off" + uint8_t DMFL_RightMirrorTilt_Cmd : 1; // Bits= 1 + + // RR Window move command + // 4 : "Auto up" + // 3 : "Auto down" + // 2 : "Manual up" + // 1 : "Manual down" + // 0 : "No action" + uint8_t DMFL_RRWindow_Cmd : 3; // Bits= 3 + + // Right Mirror Adjustment command + // 4 : "Right" + // 3 : "Left" + // 2 : "Down" + // 1 : "Up" + // 0 : "No action" + uint8_t DMFL_RightMirrorAdjust_Cmd : 3; // Bits= 3 + + // Right Mirror folding command + // 2 : "Unfold" + // 1 : "Fold" + // 0 : "No action" + uint8_t DMFL_RightMirrorFold_Cmd : 2; // Bits= 2 + + // Completeness of window closing status + // 1 : "Window fully closed" + // 0 : "Window not fully closed" + uint8_t DMFL_WindowFullyClosed_Stat : 1; // Bits= 1 + + // Request to wake up the car from the FL door + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DMFL_Comm_Req : 1; // Bits= 1 + + // Status of activation child lock function via switch on driver door + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t DMFL_ChildLock_Stat : 1; // Bits= 1 + + // FL door electric drive status + // 4 : "Fault" + // 3 : "Fully open" + // 2 : "Intermediate" + // 1 : "Fully closed" + // 0 : "Unknown" + uint8_t DMFL_DoorMovement_Stat : 3; // Bits= 3 + + // State of antipinch function of FL door + // 1 : "Pinch detected" + // 0 : "Pinch not detected" + uint8_t DMFL_Antipinch_Stat : 1; // Bits= 1 + + // Direction of movement of the FL door + // 2 : "Closing" + // 1 : "Opening" + // 0 : "Stopped" + uint8_t DMFL_DoorDirection_Stat : 2; // Bits= 2 + + // State of FL blind spot led + // 1 : "Error" + // 0 : "No error" + uint8_t DMFL_BSDLed_Stat : 1; // Bits= 1 + + // The fault status of ajar sensor in door lock + // 1 : "Fault detect" + // 0 : "No fault detect" + uint8_t DMFL_DoorAjarFault_Stat : 1; // Bits= 1 + + // FL window short drop position state + // 0 : "Window above short drop point" + // 1 : "Window is in OR below short drop point" + uint8_t DMFL_ShortDrop_Stat : 1; // Bits= 1 + + // FL turn signal repeater status + // 2 : "Error" + // 1 : "On" + // 0 : "Off" + uint8_t DMFL_TurnInd_Stat : 2; // Bits= 2 + + // Disable RR Window control + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t DMFL_ChildLock_RRwindow_Stat : 1; // Bits= 1 + + // Request to control rear window curtain from switch on FL door + // 1 : "Short pressed" + // 0 : "Not requested" + // 2 : "Long pressed" + uint8_t DMFL_RearWindowCurtain_Req : 2; // Bits= 2 + + // State of Child lock function for RL door lock + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t DMFL_ChildLock_RLdoor_Stat : 1; // Bits= 1 + + // RR Window Child Lock Control + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t DMFL_ChildLock_RRdoor_Stat : 1; // Bits= 1 + +#else + + // Request from the door lock cylinder + // 3 : "Fault" + // 2 : "Lock_Req" + // 1 : "Unlock_Req" + // 0 : "No_Request" + uint8_t DMFL_KeyCylinder_Req; // Bits= 2 + + // Request from DMFL to switch warning indicator in instrument cluster + // 1 : "Warning_Active" + // 0 : "No_Warning" + uint8_t DMFL_WarningInd; // Bits= 1 + + // FL Door Lock Status + // 2 : "Fault" + // 1 : "Door_Locked" + // 0 : "Door Unlocked" + uint8_t DMFL_DoorLockState; // Bits= 2 + + // FL door opening status + // 1 : "Door_Close" + // 0 : "Door_Open" + uint8_t DMFL_DoorAjarState; // Bits= 1 + + // State of Child lock function for central tab + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t DMFL_ChildLockCentralTab_Stat; // Bits= 1 + + // Request for power closing door from external switch on door panel + // 1 : "External Door Close request" + // 0 : "No Req" + uint8_t DMFL_DoorCloseSw_Req; // Bits= 1 + + // FL mirror heating status + // 3 : "Fault" + // 2 : "Heating off" + // 1 : "Heating on" + // 0 : "Unknown" + uint8_t DMFL_MirrorHeating_Status; // Bits= 2 + + // State of FL door internal handle: engaged or not + // 1 : "Requested" + // 0 : "No request" + uint8_t DMFL_IntDoorHandle_Req; // Bits= 1 + + // Disable RL Window control + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t DMFL_ChildLock_RLwindow_Stat; // Bits= 1 + + // State of Child lock function for rear left tab + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t DMFL_ChildLockRLTab_Stat; // Bits= 1 + + // Interior door lock switch command + // 2 : "Lock requested" + // 1 : "Unlock requested" + // 0 : "No requested" + uint8_t DMFL_IntDoorLockSw_Cmd; // Bits= 2 + + // State of Child lock function for rear right tab + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t DMFL_ChildLockRRTab_Stat; // Bits= 1 + + // FR Window move command + // 4 : "Auto up" + // 3 : "Auto down" + // 2 : "Manual up" + // 1 : "Manual down" + // 0 : "No action" + uint8_t DMFL_FRWindow_Cmd; // Bits= 3 + + // RL Window move command + // 4 : "Auto up" + // 3 : "Auto down" + // 2 : "Manual up" + // 1 : "Manual down" + // 0 : "No action" + uint8_t DMFL_RLWindow_Cmd; // Bits= 3 + + // Right mirror tilt command + // 1 : "On" + // 0 : "Off" + uint8_t DMFL_RightMirrorTilt_Cmd; // Bits= 1 + + // RR Window move command + // 4 : "Auto up" + // 3 : "Auto down" + // 2 : "Manual up" + // 1 : "Manual down" + // 0 : "No action" + uint8_t DMFL_RRWindow_Cmd; // Bits= 3 + + // Right Mirror Adjustment command + // 4 : "Right" + // 3 : "Left" + // 2 : "Down" + // 1 : "Up" + // 0 : "No action" + uint8_t DMFL_RightMirrorAdjust_Cmd; // Bits= 3 + + // Right Mirror folding command + // 2 : "Unfold" + // 1 : "Fold" + // 0 : "No action" + uint8_t DMFL_RightMirrorFold_Cmd; // Bits= 2 + + // Completeness of window closing status + // 1 : "Window fully closed" + // 0 : "Window not fully closed" + uint8_t DMFL_WindowFullyClosed_Stat; // Bits= 1 + + // Request to wake up the car from the FL door + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DMFL_Comm_Req; // Bits= 1 + + // Status of activation child lock function via switch on driver door + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t DMFL_ChildLock_Stat; // Bits= 1 + + // FL door electric drive status + // 4 : "Fault" + // 3 : "Fully open" + // 2 : "Intermediate" + // 1 : "Fully closed" + // 0 : "Unknown" + uint8_t DMFL_DoorMovement_Stat; // Bits= 3 + + // State of antipinch function of FL door + // 1 : "Pinch detected" + // 0 : "Pinch not detected" + uint8_t DMFL_Antipinch_Stat; // Bits= 1 + + // Direction of movement of the FL door + // 2 : "Closing" + // 1 : "Opening" + // 0 : "Stopped" + uint8_t DMFL_DoorDirection_Stat; // Bits= 2 + + // State of FL blind spot led + // 1 : "Error" + // 0 : "No error" + uint8_t DMFL_BSDLed_Stat; // Bits= 1 + + // The fault status of ajar sensor in door lock + // 1 : "Fault detect" + // 0 : "No fault detect" + uint8_t DMFL_DoorAjarFault_Stat; // Bits= 1 + + // FL window short drop position state + // 0 : "Window above short drop point" + // 1 : "Window is in OR below short drop point" + uint8_t DMFL_ShortDrop_Stat; // Bits= 1 + + // FL turn signal repeater status + // 2 : "Error" + // 1 : "On" + // 0 : "Off" + uint8_t DMFL_TurnInd_Stat; // Bits= 2 + + // Disable RR Window control + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t DMFL_ChildLock_RRwindow_Stat; // Bits= 1 + + // Request to control rear window curtain from switch on FL door + // 1 : "Short pressed" + // 0 : "Not requested" + // 2 : "Long pressed" + uint8_t DMFL_RearWindowCurtain_Req; // Bits= 2 + + // State of Child lock function for RL door lock + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t DMFL_ChildLock_RLdoor_Stat; // Bits= 1 + + // RR Window Child Lock Control + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t DMFL_ChildLock_RRdoor_Stat; // Bits= 1 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} DMFL_Msg1_t; + +// def @DMRL_Msg1 CAN Message (581 0x245) +#define DMRL_Msg1_IDE (0U) +#define DMRL_Msg1_DLC (5U) +#define DMRL_Msg1_CANID (0x245U) +#define DMRL_Msg1_CYC (50U) + +// Value tables for @DMRL_WarningInd signal + +#ifndef DMRL_WarningInd_DMRL_Msg1_Warning_Active +#define DMRL_WarningInd_DMRL_Msg1_Warning_Active (1) +#endif + +#ifndef DMRL_WarningInd_DMRL_Msg1_No_Warning +#define DMRL_WarningInd_DMRL_Msg1_No_Warning (0) +#endif + + +// Value tables for @DMRL_DoorLockState signal + +#ifndef DMRL_DoorLockState_DMRL_Msg1_Fault +#define DMRL_DoorLockState_DMRL_Msg1_Fault (2) +#endif + +#ifndef DMRL_DoorLockState_DMRL_Msg1_Door_Locked +#define DMRL_DoorLockState_DMRL_Msg1_Door_Locked (1) +#endif + +#ifndef DMRL_DoorLockState_DMRL_Msg1_Door_Unlocked +#define DMRL_DoorLockState_DMRL_Msg1_Door_Unlocked (0) +#endif + + +// Value tables for @DMRL_DoorAjarState signal + +#ifndef DMRL_DoorAjarState_DMRL_Msg1_Door_Close +#define DMRL_DoorAjarState_DMRL_Msg1_Door_Close (1) +#endif + +#ifndef DMRL_DoorAjarState_DMRL_Msg1_Door_Open +#define DMRL_DoorAjarState_DMRL_Msg1_Door_Open (0) +#endif + + +// Value tables for @DMRL_DoorCloseSw_Req signal + +#ifndef DMRL_DoorCloseSw_Req_DMRL_Msg1_External_Door_Close_request +#define DMRL_DoorCloseSw_Req_DMRL_Msg1_External_Door_Close_request (1) +#endif + +#ifndef DMRL_DoorCloseSw_Req_DMRL_Msg1_No_Req +#define DMRL_DoorCloseSw_Req_DMRL_Msg1_No_Req (0) +#endif + + +// Value tables for @DMRL_IntDoorHandle_Req signal + +#ifndef DMRL_IntDoorHandle_Req_DMRL_Msg1_Requested +#define DMRL_IntDoorHandle_Req_DMRL_Msg1_Requested (1) +#endif + +#ifndef DMRL_IntDoorHandle_Req_DMRL_Msg1_No_request +#define DMRL_IntDoorHandle_Req_DMRL_Msg1_No_request (0) +#endif + + +// Value tables for @DMRL_IntDoorLockSw_Cmd signal + +#ifndef DMRL_IntDoorLockSw_Cmd_DMRL_Msg1_Lock_requested +#define DMRL_IntDoorLockSw_Cmd_DMRL_Msg1_Lock_requested (2) +#endif + +#ifndef DMRL_IntDoorLockSw_Cmd_DMRL_Msg1_Unlock_requested +#define DMRL_IntDoorLockSw_Cmd_DMRL_Msg1_Unlock_requested (1) +#endif + +#ifndef DMRL_IntDoorLockSw_Cmd_DMRL_Msg1_No_requested +#define DMRL_IntDoorLockSw_Cmd_DMRL_Msg1_No_requested (0) +#endif + + +// Value tables for @DMRL_ChildLock_Stat signal + +#ifndef DMRL_ChildLock_Stat_DMRL_Msg1_Error +#define DMRL_ChildLock_Stat_DMRL_Msg1_Error (2) +#endif + +#ifndef DMRL_ChildLock_Stat_DMRL_Msg1_Locked +#define DMRL_ChildLock_Stat_DMRL_Msg1_Locked (1) +#endif + +#ifndef DMRL_ChildLock_Stat_DMRL_Msg1_Unlocked +#define DMRL_ChildLock_Stat_DMRL_Msg1_Unlocked (0) +#endif + + +// Value tables for @DMRL_VolumeLevel_Cmd signal + +#ifndef DMRL_VolumeLevel_Cmd_DMRL_Msg1_Long_Press_Voice_Assist_Req +#define DMRL_VolumeLevel_Cmd_DMRL_Msg1_Long_Press_Voice_Assist_Req (4) +#endif + +#ifndef DMRL_VolumeLevel_Cmd_DMRL_Msg1_Short_Press_Mute_Req__Volume_Off +#define DMRL_VolumeLevel_Cmd_DMRL_Msg1_Short_Press_Mute_Req__Volume_Off (3) +#endif + +#ifndef DMRL_VolumeLevel_Cmd_DMRL_Msg1_Decrease_Volume +#define DMRL_VolumeLevel_Cmd_DMRL_Msg1_Decrease_Volume (2) +#endif + +#ifndef DMRL_VolumeLevel_Cmd_DMRL_Msg1_Increase_Volume +#define DMRL_VolumeLevel_Cmd_DMRL_Msg1_Increase_Volume (1) +#endif + +#ifndef DMRL_VolumeLevel_Cmd_DMRL_Msg1_No_Request +#define DMRL_VolumeLevel_Cmd_DMRL_Msg1_No_Request (0) +#endif + + +// Value tables for @DMRL_WindowFullyClosed_Stat signal + +#ifndef DMRL_WindowFullyClosed_Stat_DMRL_Msg1_Window_fully_closed +#define DMRL_WindowFullyClosed_Stat_DMRL_Msg1_Window_fully_closed (1) +#endif + +#ifndef DMRL_WindowFullyClosed_Stat_DMRL_Msg1_Window_not_fully_closed +#define DMRL_WindowFullyClosed_Stat_DMRL_Msg1_Window_not_fully_closed (0) +#endif + + +// Value tables for @DMRL_Multimedia_Req signal + +#ifndef DMRL_Multimedia_Req_DMRL_Msg1_MMS_ONOFF_requested +#define DMRL_Multimedia_Req_DMRL_Msg1_MMS_ONOFF_requested (2) +#endif + +#ifndef DMRL_Multimedia_Req_DMRL_Msg1_Mute_ONOFF_requested +#define DMRL_Multimedia_Req_DMRL_Msg1_Mute_ONOFF_requested (1) +#endif + +#ifndef DMRL_Multimedia_Req_DMRL_Msg1_Not_requested +#define DMRL_Multimedia_Req_DMRL_Msg1_Not_requested (0) +#endif + + +// Value tables for @DMRL_Comm_Req signal + +#ifndef DMRL_Comm_Req_DMRL_Msg1_Requested +#define DMRL_Comm_Req_DMRL_Msg1_Requested (1) +#endif + +#ifndef DMRL_Comm_Req_DMRL_Msg1_Not_requested +#define DMRL_Comm_Req_DMRL_Msg1_Not_requested (0) +#endif + + +// Value tables for @DMRL_DoorAjarFault_Stat signal + +#ifndef DMRL_DoorAjarFault_Stat_DMRL_Msg1_Fault_detect +#define DMRL_DoorAjarFault_Stat_DMRL_Msg1_Fault_detect (1) +#endif + +#ifndef DMRL_DoorAjarFault_Stat_DMRL_Msg1_No_fault_detect +#define DMRL_DoorAjarFault_Stat_DMRL_Msg1_No_fault_detect (0) +#endif + + +// Value tables for @DMRL_DoorMovement_Stat signal + +#ifndef DMRL_DoorMovement_Stat_DMRL_Msg1_Fault +#define DMRL_DoorMovement_Stat_DMRL_Msg1_Fault (4) +#endif + +#ifndef DMRL_DoorMovement_Stat_DMRL_Msg1_Fully_open +#define DMRL_DoorMovement_Stat_DMRL_Msg1_Fully_open (3) +#endif + +#ifndef DMRL_DoorMovement_Stat_DMRL_Msg1_Intermediate +#define DMRL_DoorMovement_Stat_DMRL_Msg1_Intermediate (2) +#endif + +#ifndef DMRL_DoorMovement_Stat_DMRL_Msg1_Fully_closed +#define DMRL_DoorMovement_Stat_DMRL_Msg1_Fully_closed (1) +#endif + +#ifndef DMRL_DoorMovement_Stat_DMRL_Msg1_Unknown +#define DMRL_DoorMovement_Stat_DMRL_Msg1_Unknown (0) +#endif + + +// Value tables for @DMRL_Antipinch_Stat signal + +#ifndef DMRL_Antipinch_Stat_DMRL_Msg1_Pinch_detected +#define DMRL_Antipinch_Stat_DMRL_Msg1_Pinch_detected (1) +#endif + +#ifndef DMRL_Antipinch_Stat_DMRL_Msg1_Pinch_not_detected +#define DMRL_Antipinch_Stat_DMRL_Msg1_Pinch_not_detected (0) +#endif + + +// Value tables for @DMRL_DoorDirection_Stat signal + +#ifndef DMRL_DoorDirection_Stat_DMRL_Msg1_Closing +#define DMRL_DoorDirection_Stat_DMRL_Msg1_Closing (2) +#endif + +#ifndef DMRL_DoorDirection_Stat_DMRL_Msg1_Opening +#define DMRL_DoorDirection_Stat_DMRL_Msg1_Opening (1) +#endif + +#ifndef DMRL_DoorDirection_Stat_DMRL_Msg1_Stopped +#define DMRL_DoorDirection_Stat_DMRL_Msg1_Stopped (0) +#endif + + +// Value tables for @DMRL_RR_Window_Cmd signal + +#ifndef DMRL_RR_Window_Cmd_DMRL_Msg1_Auto_up +#define DMRL_RR_Window_Cmd_DMRL_Msg1_Auto_up (4) +#endif + +#ifndef DMRL_RR_Window_Cmd_DMRL_Msg1_Auto_down +#define DMRL_RR_Window_Cmd_DMRL_Msg1_Auto_down (3) +#endif + +#ifndef DMRL_RR_Window_Cmd_DMRL_Msg1_Manual_up +#define DMRL_RR_Window_Cmd_DMRL_Msg1_Manual_up (2) +#endif + +#ifndef DMRL_RR_Window_Cmd_DMRL_Msg1_Manual_down +#define DMRL_RR_Window_Cmd_DMRL_Msg1_Manual_down (1) +#endif + +#ifndef DMRL_RR_Window_Cmd_DMRL_Msg1_No_action +#define DMRL_RR_Window_Cmd_DMRL_Msg1_No_action (0) +#endif + + +// Value tables for @DMRL_ElcromeBright_Stat signal + +#ifndef DMRL_ElcromeBright_Stat_DMRL_Msg1_Strong_Dimmming +#define DMRL_ElcromeBright_Stat_DMRL_Msg1_Strong_Dimmming (3) +#endif + +#ifndef DMRL_ElcromeBright_Stat_DMRL_Msg1_Medium_Dimming +#define DMRL_ElcromeBright_Stat_DMRL_Msg1_Medium_Dimming (2) +#endif + +#ifndef DMRL_ElcromeBright_Stat_DMRL_Msg1_Soft_Dimming +#define DMRL_ElcromeBright_Stat_DMRL_Msg1_Soft_Dimming (1) +#endif + +#ifndef DMRL_ElcromeBright_Stat_DMRL_Msg1_Dimming_switched_off +#define DMRL_ElcromeBright_Stat_DMRL_Msg1_Dimming_switched_off (0) +#endif + + +// Value tables for @DMRL_SunShade_Stat signal + +#ifndef DMRL_SunShade_Stat_DMRL_Msg1_Stopped +#define DMRL_SunShade_Stat_DMRL_Msg1_Stopped (4) +#endif + +#ifndef DMRL_SunShade_Stat_DMRL_Msg1_Closing +#define DMRL_SunShade_Stat_DMRL_Msg1_Closing (3) +#endif + +#ifndef DMRL_SunShade_Stat_DMRL_Msg1_Opening +#define DMRL_SunShade_Stat_DMRL_Msg1_Opening (2) +#endif + +#ifndef DMRL_SunShade_Stat_DMRL_Msg1_Closed +#define DMRL_SunShade_Stat_DMRL_Msg1_Closed (1) +#endif + +#ifndef DMRL_SunShade_Stat_DMRL_Msg1_Open +#define DMRL_SunShade_Stat_DMRL_Msg1_Open (0) +#endif + + +// Value tables for @DMRL_RearCurtain_Req signal + +#ifndef DMRL_RearCurtain_Req_DMRL_Msg1_Short_pressed +#define DMRL_RearCurtain_Req_DMRL_Msg1_Short_pressed (1) +#endif + +#ifndef DMRL_RearCurtain_Req_DMRL_Msg1_Not_requested +#define DMRL_RearCurtain_Req_DMRL_Msg1_Not_requested (0) +#endif + +#ifndef DMRL_RearCurtain_Req_DMRL_Msg1_Long_pressed +#define DMRL_RearCurtain_Req_DMRL_Msg1_Long_pressed (2) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Request from DMRL to switch warning indicator in instrument cluster + // 1 : "Warning_Active" + // 0 : "No_Warning" + uint8_t DMRL_WarningInd : 1; // Bits= 1 + + // RL Door Lock Status + // 2 : "Fault" + // 1 : "Door_Locked" + // 0 : "Door Unlocked" + uint8_t DMRL_DoorLockState : 2; // Bits= 2 + + // RL door opening status + // 1 : "Door_Close" + // 0 : "Door_Open" + uint8_t DMRL_DoorAjarState : 1; // Bits= 1 + + // Request for power closing door from external switch on door panel + // 1 : "External Door Close request" + // 0 : "No Req" + uint8_t DMRL_DoorCloseSw_Req : 1; // Bits= 1 + + // State of RL door internal handle: engaged or not + // 1 : "Requested" + // 0 : "No request" + uint8_t DMRL_IntDoorHandle_Req : 1; // Bits= 1 + + // Interior door lock switch command + // 2 : "Lock requested" + // 1 : "Unlock requested" + // 0 : "No requested" + uint8_t DMRL_IntDoorLockSw_Cmd : 2; // Bits= 2 + + // Indicates the Child Lock status + // 2 : "Error" + // 1 : "Locked" + // 0 : "Unlocked" + uint8_t DMRL_ChildLock_Stat : 2; // Bits= 2 + + // The request to change volumme level via RL MMS joystic. + // 4 : "Long Press (Voice Assist Req)" + // 3 : "Short Press (Mute Req - Volume Off)" + // 2 : "Decrease Volume" + // 1 : "Increase Volume" + // 0 : "No Request" + uint8_t DMRL_VolumeLevel_Cmd : 3; // Bits= 3 + + // Completeness of window closing status + // 1 : "Window fully closed" + // 0 : "Window not fully closed" + uint8_t DMRL_WindowFullyClosed_Stat : 1; // Bits= 1 + + // Request to turn off/on the multimedia system from the RL passenger + // 2 : "MMS ON/OFF requested" + // 1 : "Mute ON/OFF requested" + // 0 : "Not requested" + uint8_t DMRL_Multimedia_Req : 2; // Bits= 2 + + // Request to wake up the car from the RL door + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DMRL_Comm_Req : 1; // Bits= 1 + + // The fault status of ajar sensor in door lock + // 1 : "Fault detect" + // 0 : "No fault detect" + uint8_t DMRL_DoorAjarFault_Stat : 1; // Bits= 1 + + // RL door electric drive status + // 4 : "Fault" + // 3 : "Fully open" + // 2 : "Intermediate" + // 1 : "Fully closed" + // 0 : "Unknown" + uint8_t DMRL_DoorMovement_Stat : 3; // Bits= 3 + + // State of antipinch function of RL door + // 1 : "Pinch detected" + // 0 : "Pinch not detected" + uint8_t DMRL_Antipinch_Stat : 1; // Bits= 1 + + // Direction of movement of the RL door + // 2 : "Closing" + // 1 : "Opening" + // 0 : "Stopped" + uint8_t DMRL_DoorDirection_Stat : 2; // Bits= 2 + + // Request to control RL window from RR door + // 4 : "Auto up" + // 3 : "Auto down" + // 2 : "Manual up" + // 1 : "Manual down" + // 0 : "No action" + uint8_t DMRL_RR_Window_Cmd : 3; // Bits= 3 + + // RL door glass tinting status + // 3 : "Strong Dimmming" + // 2 : "Medium Dimming" + // 1 : "Soft Dimming" + // 0 : "Dimming switched off" + uint8_t DMRL_ElcromeBright_Stat : 2; // Bits= 2 + + // State of RL window sun shade + // 4 : "Stopped" + // 3 : "Closing" + // 2 : "Opening" + // 1 : "Closed" + // 0 : "Open" + uint8_t DMRL_SunShade_Stat : 3; // Bits= 3 + + // Rear window blind control request from RL passenger + // 1 : "Short pressed" + // 0 : "Not requested" + // 2 : "Long pressed" + uint8_t DMRL_RearCurtain_Req : 2; // Bits= 2 + +#else + + // Request from DMRL to switch warning indicator in instrument cluster + // 1 : "Warning_Active" + // 0 : "No_Warning" + uint8_t DMRL_WarningInd; // Bits= 1 + + // RL Door Lock Status + // 2 : "Fault" + // 1 : "Door_Locked" + // 0 : "Door Unlocked" + uint8_t DMRL_DoorLockState; // Bits= 2 + + // RL door opening status + // 1 : "Door_Close" + // 0 : "Door_Open" + uint8_t DMRL_DoorAjarState; // Bits= 1 + + // Request for power closing door from external switch on door panel + // 1 : "External Door Close request" + // 0 : "No Req" + uint8_t DMRL_DoorCloseSw_Req; // Bits= 1 + + // State of RL door internal handle: engaged or not + // 1 : "Requested" + // 0 : "No request" + uint8_t DMRL_IntDoorHandle_Req; // Bits= 1 + + // Interior door lock switch command + // 2 : "Lock requested" + // 1 : "Unlock requested" + // 0 : "No requested" + uint8_t DMRL_IntDoorLockSw_Cmd; // Bits= 2 + + // Indicates the Child Lock status + // 2 : "Error" + // 1 : "Locked" + // 0 : "Unlocked" + uint8_t DMRL_ChildLock_Stat; // Bits= 2 + + // The request to change volumme level via RL MMS joystic. + // 4 : "Long Press (Voice Assist Req)" + // 3 : "Short Press (Mute Req - Volume Off)" + // 2 : "Decrease Volume" + // 1 : "Increase Volume" + // 0 : "No Request" + uint8_t DMRL_VolumeLevel_Cmd; // Bits= 3 + + // Completeness of window closing status + // 1 : "Window fully closed" + // 0 : "Window not fully closed" + uint8_t DMRL_WindowFullyClosed_Stat; // Bits= 1 + + // Request to turn off/on the multimedia system from the RL passenger + // 2 : "MMS ON/OFF requested" + // 1 : "Mute ON/OFF requested" + // 0 : "Not requested" + uint8_t DMRL_Multimedia_Req; // Bits= 2 + + // Request to wake up the car from the RL door + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DMRL_Comm_Req; // Bits= 1 + + // The fault status of ajar sensor in door lock + // 1 : "Fault detect" + // 0 : "No fault detect" + uint8_t DMRL_DoorAjarFault_Stat; // Bits= 1 + + // RL door electric drive status + // 4 : "Fault" + // 3 : "Fully open" + // 2 : "Intermediate" + // 1 : "Fully closed" + // 0 : "Unknown" + uint8_t DMRL_DoorMovement_Stat; // Bits= 3 + + // State of antipinch function of RL door + // 1 : "Pinch detected" + // 0 : "Pinch not detected" + uint8_t DMRL_Antipinch_Stat; // Bits= 1 + + // Direction of movement of the RL door + // 2 : "Closing" + // 1 : "Opening" + // 0 : "Stopped" + uint8_t DMRL_DoorDirection_Stat; // Bits= 2 + + // Request to control RL window from RR door + // 4 : "Auto up" + // 3 : "Auto down" + // 2 : "Manual up" + // 1 : "Manual down" + // 0 : "No action" + uint8_t DMRL_RR_Window_Cmd; // Bits= 3 + + // RL door glass tinting status + // 3 : "Strong Dimmming" + // 2 : "Medium Dimming" + // 1 : "Soft Dimming" + // 0 : "Dimming switched off" + uint8_t DMRL_ElcromeBright_Stat; // Bits= 2 + + // State of RL window sun shade + // 4 : "Stopped" + // 3 : "Closing" + // 2 : "Opening" + // 1 : "Closed" + // 0 : "Open" + uint8_t DMRL_SunShade_Stat; // Bits= 3 + + // Rear window blind control request from RL passenger + // 1 : "Short pressed" + // 0 : "Not requested" + // 2 : "Long pressed" + uint8_t DMRL_RearCurtain_Req; // Bits= 2 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} DMRL_Msg1_t; + +// def @DMRR_Msg1 CAN Message (582 0x246) +#define DMRR_Msg1_IDE (0U) +#define DMRR_Msg1_DLC (5U) +#define DMRR_Msg1_CANID (0x246U) +#define DMRR_Msg1_CYC (50U) + +// Value tables for @DMRR_WarningInd signal + +#ifndef DMRR_WarningInd_DMRR_Msg1_Warning_Active +#define DMRR_WarningInd_DMRR_Msg1_Warning_Active (1) +#endif + +#ifndef DMRR_WarningInd_DMRR_Msg1_No_Warning +#define DMRR_WarningInd_DMRR_Msg1_No_Warning (0) +#endif + + +// Value tables for @DMRR_DoorLockState signal + +#ifndef DMRR_DoorLockState_DMRR_Msg1_Fault +#define DMRR_DoorLockState_DMRR_Msg1_Fault (2) +#endif + +#ifndef DMRR_DoorLockState_DMRR_Msg1_Door_Locked +#define DMRR_DoorLockState_DMRR_Msg1_Door_Locked (1) +#endif + +#ifndef DMRR_DoorLockState_DMRR_Msg1_Door_Unlocked +#define DMRR_DoorLockState_DMRR_Msg1_Door_Unlocked (0) +#endif + + +// Value tables for @DMRR_DoorAjarState signal + +#ifndef DMRR_DoorAjarState_DMRR_Msg1_Door_Close +#define DMRR_DoorAjarState_DMRR_Msg1_Door_Close (1) +#endif + +#ifndef DMRR_DoorAjarState_DMRR_Msg1_Door_Open +#define DMRR_DoorAjarState_DMRR_Msg1_Door_Open (0) +#endif + + +// Value tables for @DMRR_DoorCloseSw_Req signal + +#ifndef DMRR_DoorCloseSw_Req_DMRR_Msg1_External_Door_Close_request +#define DMRR_DoorCloseSw_Req_DMRR_Msg1_External_Door_Close_request (1) +#endif + +#ifndef DMRR_DoorCloseSw_Req_DMRR_Msg1_No_Req +#define DMRR_DoorCloseSw_Req_DMRR_Msg1_No_Req (0) +#endif + + +// Value tables for @DMRR_IntDoorHandle_Req signal + +#ifndef DMRR_IntDoorHandle_Req_DMRR_Msg1_Requested +#define DMRR_IntDoorHandle_Req_DMRR_Msg1_Requested (1) +#endif + +#ifndef DMRR_IntDoorHandle_Req_DMRR_Msg1_No_request +#define DMRR_IntDoorHandle_Req_DMRR_Msg1_No_request (0) +#endif + + +// Value tables for @DMRR_IntDoorLockSw_Cmd signal + +#ifndef DMRR_IntDoorLockSw_Cmd_DMRR_Msg1_Lock_requested +#define DMRR_IntDoorLockSw_Cmd_DMRR_Msg1_Lock_requested (2) +#endif + +#ifndef DMRR_IntDoorLockSw_Cmd_DMRR_Msg1_Unlock_requested +#define DMRR_IntDoorLockSw_Cmd_DMRR_Msg1_Unlock_requested (1) +#endif + +#ifndef DMRR_IntDoorLockSw_Cmd_DMRR_Msg1_No_requested +#define DMRR_IntDoorLockSw_Cmd_DMRR_Msg1_No_requested (0) +#endif + + +// Value tables for @DMRR_ChildLock_Stat signal + +#ifndef DMRR_ChildLock_Stat_DMRR_Msg1_Error +#define DMRR_ChildLock_Stat_DMRR_Msg1_Error (2) +#endif + +#ifndef DMRR_ChildLock_Stat_DMRR_Msg1_Locked +#define DMRR_ChildLock_Stat_DMRR_Msg1_Locked (1) +#endif + +#ifndef DMRR_ChildLock_Stat_DMRR_Msg1_Unlocked +#define DMRR_ChildLock_Stat_DMRR_Msg1_Unlocked (0) +#endif + + +// Value tables for @DMRR_VolumeLevel_Cmd signal + +#ifndef DMRR_VolumeLevel_Cmd_DMRR_Msg1_Short_Press_Mute_Req__Volume_Off +#define DMRR_VolumeLevel_Cmd_DMRR_Msg1_Short_Press_Mute_Req__Volume_Off (3) +#endif + +#ifndef DMRR_VolumeLevel_Cmd_DMRR_Msg1_Decrease_sound +#define DMRR_VolumeLevel_Cmd_DMRR_Msg1_Decrease_sound (2) +#endif + +#ifndef DMRR_VolumeLevel_Cmd_DMRR_Msg1_Increase_sound +#define DMRR_VolumeLevel_Cmd_DMRR_Msg1_Increase_sound (1) +#endif + +#ifndef DMRR_VolumeLevel_Cmd_DMRR_Msg1_No_request +#define DMRR_VolumeLevel_Cmd_DMRR_Msg1_No_request (0) +#endif + +#ifndef DMRR_VolumeLevel_Cmd_DMRR_Msg1_Long_Press_Voice_Assist_Req +#define DMRR_VolumeLevel_Cmd_DMRR_Msg1_Long_Press_Voice_Assist_Req (4) +#endif + + +// Value tables for @DMRR_WindowFullyClosed_Stat signal + +#ifndef DMRR_WindowFullyClosed_Stat_DMRR_Msg1_Window_fully_closed +#define DMRR_WindowFullyClosed_Stat_DMRR_Msg1_Window_fully_closed (1) +#endif + +#ifndef DMRR_WindowFullyClosed_Stat_DMRR_Msg1_Window_not_fully_closed +#define DMRR_WindowFullyClosed_Stat_DMRR_Msg1_Window_not_fully_closed (0) +#endif + + +// Value tables for @DMRR_Multimedia_Req signal + +#ifndef DMRR_Multimedia_Req_DMRR_Msg1_MMS_ONOFF_requested +#define DMRR_Multimedia_Req_DMRR_Msg1_MMS_ONOFF_requested (2) +#endif + +#ifndef DMRR_Multimedia_Req_DMRR_Msg1_Mute_ONOFF_requested +#define DMRR_Multimedia_Req_DMRR_Msg1_Mute_ONOFF_requested (1) +#endif + +#ifndef DMRR_Multimedia_Req_DMRR_Msg1_Not_requested +#define DMRR_Multimedia_Req_DMRR_Msg1_Not_requested (0) +#endif + + +// Value tables for @DMRR_Comm_Req signal + +#ifndef DMRR_Comm_Req_DMRR_Msg1_Requested +#define DMRR_Comm_Req_DMRR_Msg1_Requested (1) +#endif + +#ifndef DMRR_Comm_Req_DMRR_Msg1_Not_requested +#define DMRR_Comm_Req_DMRR_Msg1_Not_requested (0) +#endif + + +// Value tables for @DMRR_DoorAjarFault_Stat signal + +#ifndef DMRR_DoorAjarFault_Stat_DMRR_Msg1_Fault_detect +#define DMRR_DoorAjarFault_Stat_DMRR_Msg1_Fault_detect (1) +#endif + +#ifndef DMRR_DoorAjarFault_Stat_DMRR_Msg1_No_fault_detect +#define DMRR_DoorAjarFault_Stat_DMRR_Msg1_No_fault_detect (0) +#endif + + +// Value tables for @DMRR_DoorMovement_Stat signal + +#ifndef DMRR_DoorMovement_Stat_DMRR_Msg1_Fault +#define DMRR_DoorMovement_Stat_DMRR_Msg1_Fault (4) +#endif + +#ifndef DMRR_DoorMovement_Stat_DMRR_Msg1_Fully_open +#define DMRR_DoorMovement_Stat_DMRR_Msg1_Fully_open (3) +#endif + +#ifndef DMRR_DoorMovement_Stat_DMRR_Msg1_Intermediate +#define DMRR_DoorMovement_Stat_DMRR_Msg1_Intermediate (2) +#endif + +#ifndef DMRR_DoorMovement_Stat_DMRR_Msg1_Fully_closed +#define DMRR_DoorMovement_Stat_DMRR_Msg1_Fully_closed (1) +#endif + +#ifndef DMRR_DoorMovement_Stat_DMRR_Msg1_Unknown +#define DMRR_DoorMovement_Stat_DMRR_Msg1_Unknown (0) +#endif + + +// Value tables for @DMRR_Antipinch_Stat signal + +#ifndef DMRR_Antipinch_Stat_DMRR_Msg1_Pinch_detected +#define DMRR_Antipinch_Stat_DMRR_Msg1_Pinch_detected (1) +#endif + +#ifndef DMRR_Antipinch_Stat_DMRR_Msg1_Pinch_not_detected +#define DMRR_Antipinch_Stat_DMRR_Msg1_Pinch_not_detected (0) +#endif + + +// Value tables for @DMRR_DoorDirection_Stat signal + +#ifndef DMRR_DoorDirection_Stat_DMRR_Msg1_Closing +#define DMRR_DoorDirection_Stat_DMRR_Msg1_Closing (2) +#endif + +#ifndef DMRR_DoorDirection_Stat_DMRR_Msg1_Opening +#define DMRR_DoorDirection_Stat_DMRR_Msg1_Opening (1) +#endif + +#ifndef DMRR_DoorDirection_Stat_DMRR_Msg1_Stopped +#define DMRR_DoorDirection_Stat_DMRR_Msg1_Stopped (0) +#endif + + +// Value tables for @DMRR_RL_Window_Cmd signal + +#ifndef DMRR_RL_Window_Cmd_DMRR_Msg1_Auto_up +#define DMRR_RL_Window_Cmd_DMRR_Msg1_Auto_up (4) +#endif + +#ifndef DMRR_RL_Window_Cmd_DMRR_Msg1_Auto_down +#define DMRR_RL_Window_Cmd_DMRR_Msg1_Auto_down (3) +#endif + +#ifndef DMRR_RL_Window_Cmd_DMRR_Msg1_Manual_up +#define DMRR_RL_Window_Cmd_DMRR_Msg1_Manual_up (2) +#endif + +#ifndef DMRR_RL_Window_Cmd_DMRR_Msg1_Manual_down +#define DMRR_RL_Window_Cmd_DMRR_Msg1_Manual_down (1) +#endif + +#ifndef DMRR_RL_Window_Cmd_DMRR_Msg1_No_action +#define DMRR_RL_Window_Cmd_DMRR_Msg1_No_action (0) +#endif + + +// Value tables for @DMRR_ElcromeBright_Stat signal + +#ifndef DMRR_ElcromeBright_Stat_DMRR_Msg1_Strong_Dimmming +#define DMRR_ElcromeBright_Stat_DMRR_Msg1_Strong_Dimmming (3) +#endif + +#ifndef DMRR_ElcromeBright_Stat_DMRR_Msg1_Medium_Dimming +#define DMRR_ElcromeBright_Stat_DMRR_Msg1_Medium_Dimming (2) +#endif + +#ifndef DMRR_ElcromeBright_Stat_DMRR_Msg1_Soft_Dimming +#define DMRR_ElcromeBright_Stat_DMRR_Msg1_Soft_Dimming (1) +#endif + +#ifndef DMRR_ElcromeBright_Stat_DMRR_Msg1_Dimming_switched_off +#define DMRR_ElcromeBright_Stat_DMRR_Msg1_Dimming_switched_off (0) +#endif + + +// Value tables for @DMRR_SunShade_Stat signal + +#ifndef DMRR_SunShade_Stat_DMRR_Msg1_Stopped +#define DMRR_SunShade_Stat_DMRR_Msg1_Stopped (4) +#endif + +#ifndef DMRR_SunShade_Stat_DMRR_Msg1_Closing +#define DMRR_SunShade_Stat_DMRR_Msg1_Closing (3) +#endif + +#ifndef DMRR_SunShade_Stat_DMRR_Msg1_Opening +#define DMRR_SunShade_Stat_DMRR_Msg1_Opening (2) +#endif + +#ifndef DMRR_SunShade_Stat_DMRR_Msg1_Closed +#define DMRR_SunShade_Stat_DMRR_Msg1_Closed (1) +#endif + +#ifndef DMRR_SunShade_Stat_DMRR_Msg1_Open +#define DMRR_SunShade_Stat_DMRR_Msg1_Open (0) +#endif + + +// Value tables for @DMRR_RearCurtain_Req signal + +#ifndef DMRR_RearCurtain_Req_DMRR_Msg1_Short_pressed +#define DMRR_RearCurtain_Req_DMRR_Msg1_Short_pressed (1) +#endif + +#ifndef DMRR_RearCurtain_Req_DMRR_Msg1_Not_requested +#define DMRR_RearCurtain_Req_DMRR_Msg1_Not_requested (0) +#endif + +#ifndef DMRR_RearCurtain_Req_DMRR_Msg1_Long_pressed +#define DMRR_RearCurtain_Req_DMRR_Msg1_Long_pressed (2) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Request from DMRR to switch warning indicator in instrument cluster + // 1 : "Warning_Active" + // 0 : "No_Warning" + uint8_t DMRR_WarningInd : 1; // Bits= 1 + + // RR Door Lock Status + // 2 : "Fault" + // 1 : "Door_Locked" + // 0 : "Door Unlocked" + uint8_t DMRR_DoorLockState : 2; // Bits= 2 + + // RR door opening status + // 1 : "Door_Close" + // 0 : "Door_Open" + uint8_t DMRR_DoorAjarState : 1; // Bits= 1 + + // Request for power closing door from external switch on door panel + // 1 : "External Door Close request" + // 0 : "No Req" + uint8_t DMRR_DoorCloseSw_Req : 1; // Bits= 1 + + // State of RR door internal handle: engaged or not + // 1 : "Requested" + // 0 : "No request" + uint8_t DMRR_IntDoorHandle_Req : 1; // Bits= 1 + + // Interior door lock switch command + // 2 : "Lock requested" + // 1 : "Unlock requested" + // 0 : "No requested" + uint8_t DMRR_IntDoorLockSw_Cmd : 2; // Bits= 2 + + // Indicates the Child Lock status + // 2 : "Error" + // 1 : "Locked" + // 0 : "Unlocked" + uint8_t DMRR_ChildLock_Stat : 2; // Bits= 2 + + // 3 : "Short Press (Mute Req - Volume Off)" + // 2 : "Decrease sound" + // 1 : "Increase sound" + // 0 : "No request" + // 4 : "Long Press (Voice Assist Req)" + uint8_t DMRR_VolumeLevel_Cmd : 3; // Bits= 3 + + // Completeness of window closing status + // 1 : "Window fully closed" + // 0 : "Window not fully closed" + uint8_t DMRR_WindowFullyClosed_Stat : 1; // Bits= 1 + + // Request to turn off/on the multimedia system from the RR passenger + // 2 : "MMS ON/OFF requested" + // 1 : "Mute ON/OFF requested" + // 0 : "Not requested" + uint8_t DMRR_Multimedia_Req : 2; // Bits= 2 + + // Request to wake up the car from the RR door + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DMRR_Comm_Req : 1; // Bits= 1 + + // The fault status of ajar sensor in door lock + // 1 : "Fault detect" + // 0 : "No fault detect" + uint8_t DMRR_DoorAjarFault_Stat : 1; // Bits= 1 + + // RR door electric drive status + // 4 : "Fault" + // 3 : "Fully open" + // 2 : "Intermediate" + // 1 : "Fully closed" + // 0 : "Unknown" + uint8_t DMRR_DoorMovement_Stat : 3; // Bits= 3 + + // State of antipinch function of RR door + // 1 : "Pinch detected" + // 0 : "Pinch not detected" + uint8_t DMRR_Antipinch_Stat : 1; // Bits= 1 + + // Direction of movement of the RR door + // 2 : "Closing" + // 1 : "Opening" + // 0 : "Stopped" + uint8_t DMRR_DoorDirection_Stat : 2; // Bits= 2 + + // Request to control RL window from RR door + // 4 : "Auto up" + // 3 : "Auto down" + // 2 : "Manual up" + // 1 : "Manual down" + // 0 : "No action" + uint8_t DMRR_RL_Window_Cmd : 3; // Bits= 3 + + // RR door glass tinting status + // 3 : "Strong Dimmming" + // 2 : "Medium Dimming" + // 1 : "Soft Dimming" + // 0 : "Dimming switched off" + uint8_t DMRR_ElcromeBright_Stat : 2; // Bits= 2 + + // State of RR window sun shade + // 4 : "Stopped" + // 3 : "Closing" + // 2 : "Opening" + // 1 : "Closed" + // 0 : "Open" + uint8_t DMRR_SunShade_Stat : 3; // Bits= 3 + + // Rear window blind control request from RR passenger + // 1 : "Short pressed" + // 0 : "Not requested" + // 2 : "Long pressed" + uint8_t DMRR_RearCurtain_Req : 2; // Bits= 2 + +#else + + // Request from DMRR to switch warning indicator in instrument cluster + // 1 : "Warning_Active" + // 0 : "No_Warning" + uint8_t DMRR_WarningInd; // Bits= 1 + + // RR Door Lock Status + // 2 : "Fault" + // 1 : "Door_Locked" + // 0 : "Door Unlocked" + uint8_t DMRR_DoorLockState; // Bits= 2 + + // RR door opening status + // 1 : "Door_Close" + // 0 : "Door_Open" + uint8_t DMRR_DoorAjarState; // Bits= 1 + + // Request for power closing door from external switch on door panel + // 1 : "External Door Close request" + // 0 : "No Req" + uint8_t DMRR_DoorCloseSw_Req; // Bits= 1 + + // State of RR door internal handle: engaged or not + // 1 : "Requested" + // 0 : "No request" + uint8_t DMRR_IntDoorHandle_Req; // Bits= 1 + + // Interior door lock switch command + // 2 : "Lock requested" + // 1 : "Unlock requested" + // 0 : "No requested" + uint8_t DMRR_IntDoorLockSw_Cmd; // Bits= 2 + + // Indicates the Child Lock status + // 2 : "Error" + // 1 : "Locked" + // 0 : "Unlocked" + uint8_t DMRR_ChildLock_Stat; // Bits= 2 + + // 3 : "Short Press (Mute Req - Volume Off)" + // 2 : "Decrease sound" + // 1 : "Increase sound" + // 0 : "No request" + // 4 : "Long Press (Voice Assist Req)" + uint8_t DMRR_VolumeLevel_Cmd; // Bits= 3 + + // Completeness of window closing status + // 1 : "Window fully closed" + // 0 : "Window not fully closed" + uint8_t DMRR_WindowFullyClosed_Stat; // Bits= 1 + + // Request to turn off/on the multimedia system from the RR passenger + // 2 : "MMS ON/OFF requested" + // 1 : "Mute ON/OFF requested" + // 0 : "Not requested" + uint8_t DMRR_Multimedia_Req; // Bits= 2 + + // Request to wake up the car from the RR door + // 1 : "Requested" + // 0 : "Not requested" + uint8_t DMRR_Comm_Req; // Bits= 1 + + // The fault status of ajar sensor in door lock + // 1 : "Fault detect" + // 0 : "No fault detect" + uint8_t DMRR_DoorAjarFault_Stat; // Bits= 1 + + // RR door electric drive status + // 4 : "Fault" + // 3 : "Fully open" + // 2 : "Intermediate" + // 1 : "Fully closed" + // 0 : "Unknown" + uint8_t DMRR_DoorMovement_Stat; // Bits= 3 + + // State of antipinch function of RR door + // 1 : "Pinch detected" + // 0 : "Pinch not detected" + uint8_t DMRR_Antipinch_Stat; // Bits= 1 + + // Direction of movement of the RR door + // 2 : "Closing" + // 1 : "Opening" + // 0 : "Stopped" + uint8_t DMRR_DoorDirection_Stat; // Bits= 2 + + // Request to control RL window from RR door + // 4 : "Auto up" + // 3 : "Auto down" + // 2 : "Manual up" + // 1 : "Manual down" + // 0 : "No action" + uint8_t DMRR_RL_Window_Cmd; // Bits= 3 + + // RR door glass tinting status + // 3 : "Strong Dimmming" + // 2 : "Medium Dimming" + // 1 : "Soft Dimming" + // 0 : "Dimming switched off" + uint8_t DMRR_ElcromeBright_Stat; // Bits= 2 + + // State of RR window sun shade + // 4 : "Stopped" + // 3 : "Closing" + // 2 : "Opening" + // 1 : "Closed" + // 0 : "Open" + uint8_t DMRR_SunShade_Stat; // Bits= 3 + + // Rear window blind control request from RR passenger + // 1 : "Short pressed" + // 0 : "Not requested" + // 2 : "Long pressed" + uint8_t DMRR_RearCurtain_Req; // Bits= 2 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} DMRR_Msg1_t; + +// The DLC and Layout must be as in UMP_1 because PTG is receive this message +// def @TM_Stat CAN Message (583 0x247) +#define TM_Stat_IDE (0U) +#define TM_Stat_DLC (4U) +#define TM_Stat_CANID (0x247U) +#define TM_Stat_CYC (50U) + +// Value tables for @TM_RearWindowHeating_Stat signal + +#ifndef TM_RearWindowHeating_Stat_TM_Stat_Heating_ON +#define TM_RearWindowHeating_Stat_TM_Stat_Heating_ON (1) +#endif + +#ifndef TM_RearWindowHeating_Stat_TM_Stat_Heating_OFF +#define TM_RearWindowHeating_Stat_TM_Stat_Heating_OFF (0) +#endif + + +// Value tables for @TM_TrailerConnect_Stat signal + +#ifndef TM_TrailerConnect_Stat_TM_Stat_Connected +#define TM_TrailerConnect_Stat_TM_Stat_Connected (1) +#endif + +#ifndef TM_TrailerConnect_Stat_TM_Stat_Not_Connected +#define TM_TrailerConnect_Stat_TM_Stat_Not_Connected (0) +#endif + + +// Value tables for @TM_LockAndCloseSW_Req signal + +#ifndef TM_LockAndCloseSW_Req_TM_Stat_CloseLockReq +#define TM_LockAndCloseSW_Req_TM_Stat_CloseLockReq (1) +#endif + +#ifndef TM_LockAndCloseSW_Req_TM_Stat_No_Request +#define TM_LockAndCloseSW_Req_TM_Stat_No_Request (0) +#endif + + +// Value tables for @TM_ExtTrunkSW_Req signal + +#ifndef TM_ExtTrunkSW_Req_TM_Stat_TrunkOpenReq +#define TM_ExtTrunkSW_Req_TM_Stat_TrunkOpenReq (1) +#endif + +#ifndef TM_ExtTrunkSW_Req_TM_Stat_No_Request +#define TM_ExtTrunkSW_Req_TM_Stat_No_Request (0) +#endif + + +// Value tables for @TM_WarningInd signal + +#ifndef TM_WarningInd_TM_Stat_Warning_Active +#define TM_WarningInd_TM_Stat_Warning_Active (1) +#endif + +#ifndef TM_WarningInd_TM_Stat_No_Warning +#define TM_WarningInd_TM_Stat_No_Warning (0) +#endif + + +// Value tables for @TM_FuelLid_Stat signal + +#ifndef TM_FuelLid_Stat_TM_Stat_HV_lid_opened +#define TM_FuelLid_Stat_TM_Stat_HV_lid_opened (1) +#endif + +#ifndef TM_FuelLid_Stat_TM_Stat_Lid_closed +#define TM_FuelLid_Stat_TM_Stat_Lid_closed (0) +#endif + + +// Value tables for @TM_Kick_Req signal + +#ifndef TM_Kick_Req_TM_Stat_KickReqActive +#define TM_Kick_Req_TM_Stat_KickReqActive (1) +#endif + +#ifndef TM_Kick_Req_TM_Stat_No_Request +#define TM_Kick_Req_TM_Stat_No_Request (0) +#endif + + +// Value tables for @TM_Comm_Req signal + +#ifndef TM_Comm_Req_TM_Stat_WakeUp_Request +#define TM_Comm_Req_TM_Stat_WakeUp_Request (1) +#endif + +#ifndef TM_Comm_Req_TM_Stat_No_Request +#define TM_Comm_Req_TM_Stat_No_Request (0) +#endif + + +// Value tables for @TM_IntTrunkSW_Req signal + +#ifndef TM_IntTrunkSW_Req_TM_Stat_TrunkOpenReq +#define TM_IntTrunkSW_Req_TM_Stat_TrunkOpenReq (1) +#endif + +#ifndef TM_IntTrunkSW_Req_TM_Stat_No_Request +#define TM_IntTrunkSW_Req_TM_Stat_No_Request (0) +#endif + + +// Value tables for @TM_TrunkLatch_Stat signal + +#ifndef TM_TrunkLatch_Stat_TM_Stat_Open +#define TM_TrunkLatch_Stat_TM_Stat_Open (3) +#endif + +#ifndef TM_TrunkLatch_Stat_TM_Stat_Secondary_position +#define TM_TrunkLatch_Stat_TM_Stat_Secondary_position (2) +#endif + +#ifndef TM_TrunkLatch_Stat_TM_Stat_Primary_position +#define TM_TrunkLatch_Stat_TM_Stat_Primary_position (1) +#endif + +#ifndef TM_TrunkLatch_Stat_TM_Stat_Unknown +#define TM_TrunkLatch_Stat_TM_Stat_Unknown (0) +#endif + + +// Value tables for @TM_BrakeLightHM_Status signal + +#ifndef TM_BrakeLightHM_Status_TM_Stat_HighMount_brake_light_failure +#define TM_BrakeLightHM_Status_TM_Stat_HighMount_brake_light_failure (1) +#endif + +#ifndef TM_BrakeLightHM_Status_TM_Stat_No_failure +#define TM_BrakeLightHM_Status_TM_Stat_No_failure (0) +#endif + + +// Value tables for @TM_FuelLidOpen_Req signal + +#ifndef TM_FuelLidOpen_Req_TM_Stat_Fuel_lid_open_request +#define TM_FuelLidOpen_Req_TM_Stat_Fuel_lid_open_request (1) +#endif + +#ifndef TM_FuelLidOpen_Req_TM_Stat_No__request +#define TM_FuelLidOpen_Req_TM_Stat_No__request (0) +#endif + + +// Value tables for @TM_T30spec_Stat signal + +#ifndef TM_T30spec_Stat_TM_Stat_Terminal_on +#define TM_T30spec_Stat_TM_Stat_Terminal_on (1) +#endif + +#ifndef TM_T30spec_Stat_TM_Stat_Terminal_off +#define TM_T30spec_Stat_TM_Stat_Terminal_off (0) +#endif + + +// Value tables for @TM_LicensePlateLight_State signal + +#ifndef TM_LicensePlateLight_State_TM_Stat_License_Plate_Lamp_Failure +#define TM_LicensePlateLight_State_TM_Stat_License_Plate_Lamp_Failure (2) +#endif + +#ifndef TM_LicensePlateLight_State_TM_Stat_Lamps_Active +#define TM_LicensePlateLight_State_TM_Stat_Lamps_Active (1) +#endif + +#ifndef TM_LicensePlateLight_State_TM_Stat_Lamps_inactive +#define TM_LicensePlateLight_State_TM_Stat_Lamps_inactive (0) +#endif + + +// Value tables for @TM_CoolingBox_Stat signal + +#ifndef TM_CoolingBox_Stat_TM_Stat_Normal_9C +#define TM_CoolingBox_Stat_TM_Stat_Normal_9C (3) +#endif + +#ifndef TM_CoolingBox_Stat_TM_Stat_Soft_5C +#define TM_CoolingBox_Stat_TM_Stat_Soft_5C (2) +#endif + +#ifndef TM_CoolingBox_Stat_TM_Stat_Off +#define TM_CoolingBox_Stat_TM_Stat_Off (1) +#endif + +#ifndef TM_CoolingBox_Stat_TM_Stat_Reserved +#define TM_CoolingBox_Stat_TM_Stat_Reserved (0) +#endif + + +// Value tables for @TM_RearCushion_State signal + +#ifndef TM_RearCushion_State_TM_Stat_Stopped +#define TM_RearCushion_State_TM_Stat_Stopped (4) +#endif + +#ifndef TM_RearCushion_State_TM_Stat_Closing +#define TM_RearCushion_State_TM_Stat_Closing (3) +#endif + +#ifndef TM_RearCushion_State_TM_Stat_Opening +#define TM_RearCushion_State_TM_Stat_Opening (2) +#endif + +#ifndef TM_RearCushion_State_TM_Stat_Closed +#define TM_RearCushion_State_TM_Stat_Closed (1) +#endif + +#ifndef TM_RearCushion_State_TM_Stat_Open +#define TM_RearCushion_State_TM_Stat_Open (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // State of rear window heating + // 1 : "Heating ON" + // 0 : "Heating OFF" + uint8_t TM_RearWindowHeating_Stat : 1; // Bits= 1 + + // Trailer connect status signal + // Indicates wether the trailer is connected or not + // 1 : "Connected" + // 0 : "Not Connected" + uint8_t TM_TrailerConnect_Stat : 1; // Bits= 1 + + // State of interior trunk lid close an lock swich + // 1 : "Close&LockReq" + // 0 : "No_Request" + uint8_t TM_LockAndCloseSW_Req : 1; // Bits= 1 + + // Exterior switch on the trunk used to open the trunk: + // 0x0 = No Request + // 0x1 = Unlock request + // 1 : "TrunkOpenReq" + // 0 : "No_Request" + uint8_t TM_ExtTrunkSW_Req : 1; // Bits= 1 + + // Request a warning message to be displayed on IC: + // $0 = No Warning + // $1 = Warning requested + // 1 : "Warning_Active" + // 0 : "No_Warning" + uint8_t TM_WarningInd : 1; // Bits= 1 + + // Fuel lid open status + // 1 : "HV lid opened" + // 0 : "Lid closed" + uint8_t TM_FuelLid_Stat : 1; // Bits= 1 + + // Request to open or close trunk lid from kick sensor + // 1 : "KickReqActive" + // 0 : "No_Request" + uint8_t TM_Kick_Req : 1; // Bits= 1 + + // Request to initiate/ maintain communication activity from TM + // 1 : "WakeUp_Request" + // 0 : "No_Request" + uint8_t TM_Comm_Req : 1; // Bits= 1 + + // State of interior trunk lid close swich + // 1 : "TrunkOpenReq" + // 0 : "No_Request" + uint8_t TM_IntTrunkSW_Req : 1; // Bits= 1 + + // Indicates the trunk latch position + // 3 : "Open" + // 2 : "Secondary position" + // 1 : "Primary position" + // 0 : "Unknown" + uint8_t TM_TrunkLatch_Stat : 2; // Bits= 2 + + // Current status of brake lights + // 1 : "HighMount brake light failure" + // 0 : "No failure" + uint8_t TM_BrakeLightHM_Status : 1; // Bits= 1 + + // Fuel lid unlock request for PHEV vehicles + // 1 : "Fuel lid open request" + // 0 : "No request" + uint8_t TM_FuelLidOpen_Req : 1; // Bits= 1 + + // Terminal T30 from additional battery + // 1 : "Terminal on" + // 0 : "Terminal off" + uint8_t TM_T30spec_Stat : 1; // Bits= 1 + + // State of license plate lights + // 2 : "License Plate Lamp Failure" + // 1 : "Lamps Active" + // 0 : "Lamps inactive" + uint8_t TM_LicensePlateLight_State : 3; // Bits= 3 + + // Cooling box temperature status + // 3 : "Normal 9�C" + // 2 : "Soft 5�C" + // 1 : "Off" + // 0 : "Reserved" + uint8_t TM_CoolingBox_Stat : 2; // Bits= 2 Unit:'2' + + // The state of rear window cushion + // 4 : "Stopped" + // 3 : "Closing" + // 2 : "Opening" + // 1 : "Closed" + // 0 : "Open" + uint8_t TM_RearCushion_State : 3; // Bits= 3 + +#else + + // State of rear window heating + // 1 : "Heating ON" + // 0 : "Heating OFF" + uint8_t TM_RearWindowHeating_Stat; // Bits= 1 + + // Trailer connect status signal + // Indicates wether the trailer is connected or not + // 1 : "Connected" + // 0 : "Not Connected" + uint8_t TM_TrailerConnect_Stat; // Bits= 1 + + // State of interior trunk lid close an lock swich + // 1 : "Close&LockReq" + // 0 : "No_Request" + uint8_t TM_LockAndCloseSW_Req; // Bits= 1 + + // Exterior switch on the trunk used to open the trunk: + // 0x0 = No Request + // 0x1 = Unlock request + // 1 : "TrunkOpenReq" + // 0 : "No_Request" + uint8_t TM_ExtTrunkSW_Req; // Bits= 1 + + // Request a warning message to be displayed on IC: + // $0 = No Warning + // $1 = Warning requested + // 1 : "Warning_Active" + // 0 : "No_Warning" + uint8_t TM_WarningInd; // Bits= 1 + + // Fuel lid open status + // 1 : "HV lid opened" + // 0 : "Lid closed" + uint8_t TM_FuelLid_Stat; // Bits= 1 + + // Request to open or close trunk lid from kick sensor + // 1 : "KickReqActive" + // 0 : "No_Request" + uint8_t TM_Kick_Req; // Bits= 1 + + // Request to initiate/ maintain communication activity from TM + // 1 : "WakeUp_Request" + // 0 : "No_Request" + uint8_t TM_Comm_Req; // Bits= 1 + + // State of interior trunk lid close swich + // 1 : "TrunkOpenReq" + // 0 : "No_Request" + uint8_t TM_IntTrunkSW_Req; // Bits= 1 + + // Indicates the trunk latch position + // 3 : "Open" + // 2 : "Secondary position" + // 1 : "Primary position" + // 0 : "Unknown" + uint8_t TM_TrunkLatch_Stat; // Bits= 2 + + // Current status of brake lights + // 1 : "HighMount brake light failure" + // 0 : "No failure" + uint8_t TM_BrakeLightHM_Status; // Bits= 1 + + // Fuel lid unlock request for PHEV vehicles + // 1 : "Fuel lid open request" + // 0 : "No request" + uint8_t TM_FuelLidOpen_Req; // Bits= 1 + + // Terminal T30 from additional battery + // 1 : "Terminal on" + // 0 : "Terminal off" + uint8_t TM_T30spec_Stat; // Bits= 1 + + // State of license plate lights + // 2 : "License Plate Lamp Failure" + // 1 : "Lamps Active" + // 0 : "Lamps inactive" + uint8_t TM_LicensePlateLight_State; // Bits= 3 + + // Cooling box temperature status + // 3 : "Normal 9�C" + // 2 : "Soft 5�C" + // 1 : "Off" + // 0 : "Reserved" + uint8_t TM_CoolingBox_Stat; // Bits= 2 Unit:'2' + + // The state of rear window cushion + // 4 : "Stopped" + // 3 : "Closing" + // 2 : "Opening" + // 1 : "Closed" + // 0 : "Open" + uint8_t TM_RearCushion_State; // Bits= 3 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} TM_Stat_t; + +// def @PTG_Body_Stat CAN Message (585 0x249) +#define PTG_Body_Stat_IDE (0U) +#define PTG_Body_Stat_DLC (1U) +#define PTG_Body_Stat_CANID (0x249U) +#define PTG_Body_Stat_CYC (50U) + +// Value tables for @PowerTailgateAntipinchSts signal + +#ifndef PowerTailgateAntipinchSts_PTG_Body_Stat_Pinch_Occured +#define PowerTailgateAntipinchSts_PTG_Body_Stat_Pinch_Occured (1) +#endif + +#ifndef PowerTailgateAntipinchSts_PTG_Body_Stat_Normal +#define PowerTailgateAntipinchSts_PTG_Body_Stat_Normal (0) +#endif + + +// Value tables for @PowerTailgateMotionStatus signal + +#ifndef PowerTailgateMotionStatus_PTG_Body_Stat_Closing +#define PowerTailgateMotionStatus_PTG_Body_Stat_Closing (2) +#endif + +#ifndef PowerTailgateMotionStatus_PTG_Body_Stat_Openning +#define PowerTailgateMotionStatus_PTG_Body_Stat_Openning (1) +#endif + +#ifndef PowerTailgateMotionStatus_PTG_Body_Stat_Stopped +#define PowerTailgateMotionStatus_PTG_Body_Stat_Stopped (0) +#endif + + +// Value tables for @PowerTailgateMemoryStored signal + +#ifndef PowerTailgateMemoryStored_PTG_Body_Stat_TRUE +#define PowerTailgateMemoryStored_PTG_Body_Stat_TRUE (1) +#endif + +#ifndef PowerTailgateMemoryStored_PTG_Body_Stat_FALSE +#define PowerTailgateMemoryStored_PTG_Body_Stat_FALSE (0) +#endif + + +// Value tables for @PowerTailgateStatus signal + +#ifndef PowerTailgateStatus_PTG_Body_Stat_Fully_Raised +#define PowerTailgateStatus_PTG_Body_Stat_Fully_Raised (4) +#endif + +#ifndef PowerTailgateStatus_PTG_Body_Stat_Memory_Position +#define PowerTailgateStatus_PTG_Body_Stat_Memory_Position (3) +#endif + +#ifndef PowerTailgateStatus_PTG_Body_Stat_Intermediate +#define PowerTailgateStatus_PTG_Body_Stat_Intermediate (2) +#endif + +#ifndef PowerTailgateStatus_PTG_Body_Stat_Fully_Lowered +#define PowerTailgateStatus_PTG_Body_Stat_Fully_Lowered (1) +#endif + +#ifndef PowerTailgateStatus_PTG_Body_Stat_Unknown +#define PowerTailgateStatus_PTG_Body_Stat_Unknown (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Indicates the tailgate antipinch status: + // $0 = Normal + // $1 = Pinch occured + // 1 : "Pinch Occured" + // 0 : "Normal" + uint8_t PowerTailgateAntipinchSts : 1; // Bits= 1 + + // Indicates the power tailgate motion status: + // $0 = Stopped + // $1 = Openning + // $2 = Closing + // 2 : "Closing" + // 1 : "Openning" + // 0 : "Stopped" + uint8_t PowerTailgateMotionStatus : 2; // Bits= 2 + + // Indicates whether the power tailgate position is stored in memory or not: + // $0 = False + // $1 = True + // 1 : "TRUE" + // 0 : "FALSE" + uint8_t PowerTailgateMemoryStored : 1; // Bits= 1 + + // Indicates the power tailgate position: + // $0 = Unknown + // $1 = Fully lowered + // $2 = Intermediate + // $3 = Memory position + // $4 = Fully raised + // 4 : "Fully Raised" + // 3 : "Memory Position" + // 2 : "Intermediate" + // 1 : "Fully Lowered" + // 0 : "Unknown" + uint8_t PowerTailgateStatus : 3; // Bits= 3 + +#else + + // Indicates the tailgate antipinch status: + // $0 = Normal + // $1 = Pinch occured + // 1 : "Pinch Occured" + // 0 : "Normal" + uint8_t PowerTailgateAntipinchSts; // Bits= 1 + + // Indicates the power tailgate motion status: + // $0 = Stopped + // $1 = Openning + // $2 = Closing + // 2 : "Closing" + // 1 : "Openning" + // 0 : "Stopped" + uint8_t PowerTailgateMotionStatus; // Bits= 2 + + // Indicates whether the power tailgate position is stored in memory or not: + // $0 = False + // $1 = True + // 1 : "TRUE" + // 0 : "FALSE" + uint8_t PowerTailgateMemoryStored; // Bits= 1 + + // Indicates the power tailgate position: + // $0 = Unknown + // $1 = Fully lowered + // $2 = Intermediate + // $3 = Memory position + // $4 = Fully raised + // 4 : "Fully Raised" + // 3 : "Memory Position" + // 2 : "Intermediate" + // 1 : "Fully Lowered" + // 0 : "Unknown" + uint8_t PowerTailgateStatus; // Bits= 3 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} PTG_Body_Stat_t; + +// def @TM_CP CAN Message (588 0x24c) +#define TM_CP_IDE (0U) +#define TM_CP_DLC (8U) +#define TM_CP_CANID (0x24cU) +#define TM_CP_CYC (100U) + +// Value tables for @CCPR_TVPowerSw_Stat signal + +#ifndef CCPR_TVPowerSw_Stat_TM_CP_Pressed +#define CCPR_TVPowerSw_Stat_TM_CP_Pressed (1) +#endif + +#ifndef CCPR_TVPowerSw_Stat_TM_CP_Not_pressed +#define CCPR_TVPowerSw_Stat_TM_CP_Not_pressed (0) +#endif + + +// Value tables for @CCPF_RWindowHeatSw_Stat signal + +#ifndef CCPF_RWindowHeatSw_Stat_TM_CP_Pressed +#define CCPF_RWindowHeatSw_Stat_TM_CP_Pressed (1) +#endif + +#ifndef CCPF_RWindowHeatSw_Stat_TM_CP_Not_pressed +#define CCPF_RWindowHeatSw_Stat_TM_CP_Not_pressed (0) +#endif + + +// Value tables for @CCPF_FWindowHeatSw_Stat signal + +#ifndef CCPF_FWindowHeatSw_Stat_TM_CP_Pressed +#define CCPF_FWindowHeatSw_Stat_TM_CP_Pressed (1) +#endif + +#ifndef CCPF_FWindowHeatSw_Stat_TM_CP_Not_pressed +#define CCPF_FWindowHeatSw_Stat_TM_CP_Not_pressed (0) +#endif + + +// Value tables for @CCPR_SrcChgSw_Stat signal + +#ifndef CCPR_SrcChgSw_Stat_TM_CP_Pressed +#define CCPR_SrcChgSw_Stat_TM_CP_Pressed (1) +#endif + +#ifndef CCPR_SrcChgSw_Stat_TM_CP_Not_pressed +#define CCPR_SrcChgSw_Stat_TM_CP_Not_pressed (0) +#endif + + +// Value tables for @CCPR_DWClaritySw_Stat signal + +#ifndef CCPR_DWClaritySw_Stat_TM_CP_Pressed +#define CCPR_DWClaritySw_Stat_TM_CP_Pressed (1) +#endif + +#ifndef CCPR_DWClaritySw_Stat_TM_CP_Not_pressed +#define CCPR_DWClaritySw_Stat_TM_CP_Not_pressed (0) +#endif + + +// Value tables for @CCPR_IntercomSw_Stat signal + +#ifndef CCPR_IntercomSw_Stat_TM_CP_Pressed +#define CCPR_IntercomSw_Stat_TM_CP_Pressed (1) +#endif + +#ifndef CCPR_IntercomSw_Stat_TM_CP_Not_pressed +#define CCPR_IntercomSw_Stat_TM_CP_Not_pressed (0) +#endif + + +// Value tables for @CCPR_DWCntrlSw_Stat signal + +#ifndef CCPR_DWCntrlSw_Stat_TM_CP_Pressed_right_button_DW_up +#define CCPR_DWCntrlSw_Stat_TM_CP_Pressed_right_button_DW_up (2) +#endif + +#ifndef CCPR_DWCntrlSw_Stat_TM_CP_Pressed_left_button_DW_down +#define CCPR_DWCntrlSw_Stat_TM_CP_Pressed_left_button_DW_down (1) +#endif + +#ifndef CCPR_DWCntrlSw_Stat_TM_CP_Not_pressed +#define CCPR_DWCntrlSw_Stat_TM_CP_Not_pressed (0) +#endif + + +// Value tables for @CCPF_MuteSw_Stat signal + +#ifndef CCPF_MuteSw_Stat_TM_CP_MMS_ONOFF_requested +#define CCPF_MuteSw_Stat_TM_CP_MMS_ONOFF_requested (2) +#endif + +#ifndef CCPF_MuteSw_Stat_TM_CP_Mute_ONOFF_requested +#define CCPF_MuteSw_Stat_TM_CP_Mute_ONOFF_requested (1) +#endif + +#ifndef CCPF_MuteSw_Stat_TM_CP_Not_requested +#define CCPF_MuteSw_Stat_TM_CP_Not_requested (0) +#endif + + +// Value tables for @CCPF_VolAjustSw_Stat signal + +#ifndef CCPF_VolAjustSw_Stat_TM_CP_Volume_ +#define CCPF_VolAjustSw_Stat_TM_CP_Volume_ (2) +#endif + +#ifndef CCPF_VolAjustSw_Stat_TM_CP_Volume_ +#define CCPF_VolAjustSw_Stat_TM_CP_Volume_ (1) +#endif + +#ifndef CCPF_VolAjustSw_Stat_TM_CP_Not_pressed +#define CCPF_VolAjustSw_Stat_TM_CP_Not_pressed (0) +#endif + + +// Value tables for @CCPR_PanoramicViewSw_Stat signal + +#ifndef CCPR_PanoramicViewSw_Stat_TM_CP_Long_pressed +#define CCPR_PanoramicViewSw_Stat_TM_CP_Long_pressed (2) +#endif + +#ifndef CCPR_PanoramicViewSw_Stat_TM_CP_Pressed +#define CCPR_PanoramicViewSw_Stat_TM_CP_Pressed (1) +#endif + +#ifndef CCPR_PanoramicViewSw_Stat_TM_CP_Not_pressed +#define CCPR_PanoramicViewSw_Stat_TM_CP_Not_pressed (0) +#endif + + +// Value tables for @CCPF_AutoButtonR_Stat signal + +#ifndef CCPF_AutoButtonR_Stat_TM_CP_Button_hold_pressed +#define CCPF_AutoButtonR_Stat_TM_CP_Button_hold_pressed (2) +#endif + +#ifndef CCPF_AutoButtonR_Stat_TM_CP_Button_Pressed +#define CCPF_AutoButtonR_Stat_TM_CP_Button_Pressed (1) +#endif + +#ifndef CCPF_AutoButtonR_Stat_TM_CP_Button_Released +#define CCPF_AutoButtonR_Stat_TM_CP_Button_Released (0) +#endif + + +// Value tables for @CCPR_AutoButtonL_Stat signal + +#ifndef CCPR_AutoButtonL_Stat_TM_CP_Button_hold_pressed +#define CCPR_AutoButtonL_Stat_TM_CP_Button_hold_pressed (2) +#endif + +#ifndef CCPR_AutoButtonL_Stat_TM_CP_Button_pressed +#define CCPR_AutoButtonL_Stat_TM_CP_Button_pressed (1) +#endif + +#ifndef CCPR_AutoButtonL_Stat_TM_CP_Button_released +#define CCPR_AutoButtonL_Stat_TM_CP_Button_released (0) +#endif + + +// Value tables for @CCPR_AutoButtonR_Stat signal + +#ifndef CCPR_AutoButtonR_Stat_TM_CP_Button_hold_pressed +#define CCPR_AutoButtonR_Stat_TM_CP_Button_hold_pressed (2) +#endif + +#ifndef CCPR_AutoButtonR_Stat_TM_CP_Button_pressed +#define CCPR_AutoButtonR_Stat_TM_CP_Button_pressed (1) +#endif + +#ifndef CCPR_AutoButtonR_Stat_TM_CP_Button_released +#define CCPR_AutoButtonR_Stat_TM_CP_Button_released (0) +#endif + + +// Value tables for @CCPF_DefButton_Stat signal + +#ifndef CCPF_DefButton_Stat_TM_CP_Button_hold_pressed +#define CCPF_DefButton_Stat_TM_CP_Button_hold_pressed (2) +#endif + +#ifndef CCPF_DefButton_Stat_TM_CP_Button_pressed +#define CCPF_DefButton_Stat_TM_CP_Button_pressed (1) +#endif + +#ifndef CCPF_DefButton_Stat_TM_CP_Button_released +#define CCPF_DefButton_Stat_TM_CP_Button_released (0) +#endif + + +// Value tables for @CCPF_TempToggleR_Stat signal + +#ifndef CCPF_TempToggleR_Stat_TM_CP_Toggle_hold_lowered_ +#define CCPF_TempToggleR_Stat_TM_CP_Toggle_hold_lowered_ (4) +#endif + +#ifndef CCPF_TempToggleR_Stat_TM_CP_Toggle_hold_raised_ +#define CCPF_TempToggleR_Stat_TM_CP_Toggle_hold_raised_ (3) +#endif + +#ifndef CCPF_TempToggleR_Stat_TM_CP_Toggle_lowered +#define CCPF_TempToggleR_Stat_TM_CP_Toggle_lowered (2) +#endif + +#ifndef CCPF_TempToggleR_Stat_TM_CP_Toggle_raised +#define CCPF_TempToggleR_Stat_TM_CP_Toggle_raised (1) +#endif + +#ifndef CCPF_TempToggleR_Stat_TM_CP_Toggle_released +#define CCPF_TempToggleR_Stat_TM_CP_Toggle_released (0) +#endif + + +// Value tables for @CCPF_TempToggleL_Stat signal + +#ifndef CCPF_TempToggleL_Stat_TM_CP_Toggle_hold_lowered_ +#define CCPF_TempToggleL_Stat_TM_CP_Toggle_hold_lowered_ (4) +#endif + +#ifndef CCPF_TempToggleL_Stat_TM_CP_Toggle_hold_raised_ +#define CCPF_TempToggleL_Stat_TM_CP_Toggle_hold_raised_ (3) +#endif + +#ifndef CCPF_TempToggleL_Stat_TM_CP_Toggle_lowered +#define CCPF_TempToggleL_Stat_TM_CP_Toggle_lowered (2) +#endif + +#ifndef CCPF_TempToggleL_Stat_TM_CP_Toggle_raised +#define CCPF_TempToggleL_Stat_TM_CP_Toggle_raised (1) +#endif + +#ifndef CCPF_TempToggleL_Stat_TM_CP_Toggle_released +#define CCPF_TempToggleL_Stat_TM_CP_Toggle_released (0) +#endif + + +// Value tables for @CCPF_AutoButtonL_Stat signal + +#ifndef CCPF_AutoButtonL_Stat_TM_CP_Button_hold_pressed +#define CCPF_AutoButtonL_Stat_TM_CP_Button_hold_pressed (2) +#endif + +#ifndef CCPF_AutoButtonL_Stat_TM_CP_Button_pressed +#define CCPF_AutoButtonL_Stat_TM_CP_Button_pressed (1) +#endif + +#ifndef CCPF_AutoButtonL_Stat_TM_CP_Button_released +#define CCPF_AutoButtonL_Stat_TM_CP_Button_released (0) +#endif + + +// Value tables for @CCPR_TempToggleR_Stat signal + +#ifndef CCPR_TempToggleR_Stat_TM_CP_Toggle_hold_lowered_ +#define CCPR_TempToggleR_Stat_TM_CP_Toggle_hold_lowered_ (4) +#endif + +#ifndef CCPR_TempToggleR_Stat_TM_CP_Toggle_hold_raised_ +#define CCPR_TempToggleR_Stat_TM_CP_Toggle_hold_raised_ (3) +#endif + +#ifndef CCPR_TempToggleR_Stat_TM_CP_Toggle_lowered +#define CCPR_TempToggleR_Stat_TM_CP_Toggle_lowered (2) +#endif + +#ifndef CCPR_TempToggleR_Stat_TM_CP_Toggle_raised +#define CCPR_TempToggleR_Stat_TM_CP_Toggle_raised (1) +#endif + +#ifndef CCPR_TempToggleR_Stat_TM_CP_Toggle_released +#define CCPR_TempToggleR_Stat_TM_CP_Toggle_released (0) +#endif + + +// Value tables for @CCPR_TempToggleL_Stat signal + +#ifndef CCPR_TempToggleL_Stat_TM_CP_Toggle_hold_lowered_ +#define CCPR_TempToggleL_Stat_TM_CP_Toggle_hold_lowered_ (4) +#endif + +#ifndef CCPR_TempToggleL_Stat_TM_CP_Toggle_hold_raised_ +#define CCPR_TempToggleL_Stat_TM_CP_Toggle_hold_raised_ (3) +#endif + +#ifndef CCPR_TempToggleL_Stat_TM_CP_Toggle_lowered +#define CCPR_TempToggleL_Stat_TM_CP_Toggle_lowered (2) +#endif + +#ifndef CCPR_TempToggleL_Stat_TM_CP_Toggle_raised +#define CCPR_TempToggleL_Stat_TM_CP_Toggle_raised (1) +#endif + +#ifndef CCPR_TempToggleL_Stat_TM_CP_Toggle_released +#define CCPR_TempToggleL_Stat_TM_CP_Toggle_released (0) +#endif + + +// Value tables for @CCPF_RecButton_Stat signal + +#ifndef CCPF_RecButton_Stat_TM_CP_Button_hold_pressed +#define CCPF_RecButton_Stat_TM_CP_Button_hold_pressed (2) +#endif + +#ifndef CCPF_RecButton_Stat_TM_CP_Button_pressed +#define CCPF_RecButton_Stat_TM_CP_Button_pressed (1) +#endif + +#ifndef CCPF_RecButton_Stat_TM_CP_Button_released +#define CCPF_RecButton_Stat_TM_CP_Button_released (0) +#endif + + +// Value tables for @CCPF_AcMaxButton_Stat signal + +#ifndef CCPF_AcMaxButton_Stat_TM_CP_Button_hold_pressed_ +#define CCPF_AcMaxButton_Stat_TM_CP_Button_hold_pressed_ (2) +#endif + +#ifndef CCPF_AcMaxButton_Stat_TM_CP_Button_pressed +#define CCPF_AcMaxButton_Stat_TM_CP_Button_pressed (1) +#endif + +#ifndef CCPF_AcMaxButton_Stat_TM_CP_Button_released +#define CCPF_AcMaxButton_Stat_TM_CP_Button_released (0) +#endif + + +// Value tables for @CCPR_TabletOffSw_Stat signal + +#ifndef CCPR_TabletOffSw_Stat_TM_CP_Mute_ONOFF_requested +#define CCPR_TabletOffSw_Stat_TM_CP_Mute_ONOFF_requested (1) +#endif + +#ifndef CCPR_TabletOffSw_Stat_TM_CP_Not_requested +#define CCPR_TabletOffSw_Stat_TM_CP_Not_requested (0) +#endif + +#ifndef CCPR_TabletOffSw_Stat_TM_CP_MMS_ONOFF_requested +#define CCPR_TabletOffSw_Stat_TM_CP_MMS_ONOFF_requested (2) +#endif + + +// Value tables for @CCPR_TabletExtractSw_Stat signal + +#ifndef CCPR_TabletExtractSw_Stat_TM_CP_Pressed +#define CCPR_TabletExtractSw_Stat_TM_CP_Pressed (1) +#endif + +#ifndef CCPR_TabletExtractSw_Stat_TM_CP_Not_pressed +#define CCPR_TabletExtractSw_Stat_TM_CP_Not_pressed (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // TV power switch status + // 1 : "Pressed" + // 0 : "Not pressed" + uint8_t CCPR_TVPowerSw_Stat : 1; // Bits= 1 + + // Rear window heating switch status + // 1 : "Pressed" + // 0 : "Not pressed" + uint8_t CCPF_RWindowHeatSw_Stat : 1; // Bits= 1 + + // Button status of the heated windshield, front door windows and side mirrors + // 1 : "Pressed" + // 0 : "Not pressed" + uint8_t CCPF_FWindowHeatSw_Stat : 1; // Bits= 1 + + // Change TV source change switch status + // 1 : "Pressed" + // 0 : "Not pressed" + uint8_t CCPR_SrcChgSw_Stat : 1; // Bits= 1 + + // Patrition transparency switch status + // 1 : "Pressed" + // 0 : "Not pressed" + uint8_t CCPR_DWClaritySw_Stat : 1; // Bits= 1 + + // Intercom switch status + // 1 : "Pressed" + // 0 : "Not pressed" + uint8_t CCPR_IntercomSw_Stat : 1; // Bits= 1 + + // Patrition control switch status + // 2 : "Pressed right button (DW up)" + // 1 : "Pressed left button (DW down)" + // 0 : "Not pressed" + uint8_t CCPR_DWCntrlSw_Stat : 2; // Bits= 2 + + // Mute button status and display FIU + // 2 : "MMS ON/OFF requested" + // 1 : "Mute ON/OFF requested" + // 0 : "Not requested" + uint8_t CCPF_MuteSw_Stat : 2; // Bits= 2 + + // Volume ajustment switch status + // 2 : "Volume -" + // 1 : "Volume +" + // 0 : "Not pressed" + uint8_t CCPF_VolAjustSw_Stat : 2; // Bits= 2 + + // Panoramic view switch status + // 2 : "Long pressed" + // 1 : "Pressed" + // 0 : "Not pressed" + uint8_t CCPR_PanoramicViewSw_Stat : 2; // Bits= 2 + + // Front climate panel right AUTO button status + // 2 : "Button hold pressed" + // 1 : "Button Pressed" + // 0 : "Button Released" + uint8_t CCPF_AutoButtonR_Stat : 2; // Bits= 2 + + // Rear climate panel left AUTO button status + // 2 : "Button hold pressed" + // 1 : "Button pressed" + // 0 : "Button released" + uint8_t CCPR_AutoButtonL_Stat : 2; // Bits= 2 + + // Rear climate panel right AUTO button status + // 2 : "Button hold pressed" + // 1 : "Button pressed" + // 0 : "Button released" + uint8_t CCPR_AutoButtonR_Stat : 2; // Bits= 2 + + // Front climate panel DEFROST button status + // 2 : "Button hold pressed" + // 1 : "Button pressed" + // 0 : "Button released" + uint8_t CCPF_DefButton_Stat : 2; // Bits= 2 + + // Front climate panel right TEMPERATURE toggle status + // 4 : "Toggle hold lowered " + // 3 : "Toggle hold raised " + // 2 : "Toggle lowered" + // 1 : "Toggle raised" + // 0 : "Toggle released" + uint8_t CCPF_TempToggleR_Stat : 3; // Bits= 3 + + // Front climate panel left TEMPERATURE toggle status + // 4 : "Toggle hold lowered " + // 3 : "Toggle hold raised " + // 2 : "Toggle lowered" + // 1 : "Toggle raised" + // 0 : "Toggle released" + uint8_t CCPF_TempToggleL_Stat : 3; // Bits= 3 + + // Front climate panel left AUTO button status + // 2 : "Button hold pressed" + // 1 : "Button pressed" + // 0 : "Button released" + uint8_t CCPF_AutoButtonL_Stat : 2; // Bits= 2 + + // Rear climate panel right TEMPERATURE toggle status + // 4 : "Toggle hold lowered " + // 3 : "Toggle hold raised " + // 2 : "Toggle lowered" + // 1 : "Toggle raised" + // 0 : "Toggle released" + uint8_t CCPR_TempToggleR_Stat : 3; // Bits= 3 + + // Rear climate panel left TEMPERATURE toggle status + // 4 : "Toggle hold lowered " + // 3 : "Toggle hold raised " + // 2 : "Toggle lowered" + // 1 : "Toggle raised" + // 0 : "Toggle released" + uint8_t CCPR_TempToggleL_Stat : 3; // Bits= 3 + + // Front climate panel RECIRCULATION button status + // 2 : "Button hold pressed" + // 1 : "Button pressed" + // 0 : "Button released" + uint8_t CCPF_RecButton_Stat : 2; // Bits= 2 + + // Front climate panel AC MAX button status + // 2 : "Button hold pressed " + // 1 : "Button pressed" + // 0 : "Button released" + uint8_t CCPF_AcMaxButton_Stat : 2; // Bits= 2 + + // Tablet On/Off switch status. + // Short Press - Screen OFF request + // Long Press - Central Tablet OFF request + // 1 : "Mute ON/OFF requested" + // 0 : "Not requested" + // 2 : "MMS ON/OFF requested" + uint8_t CCPR_TabletOffSw_Stat : 2; // Bits= 2 + + // Tablet extraction switch status + // Center rear tablet removal signal + // 1 : "Pressed" + // 0 : "Not pressed" + uint8_t CCPR_TabletExtractSw_Stat : 1; // Bits= 1 + +#else + + // TV power switch status + // 1 : "Pressed" + // 0 : "Not pressed" + uint8_t CCPR_TVPowerSw_Stat; // Bits= 1 + + // Rear window heating switch status + // 1 : "Pressed" + // 0 : "Not pressed" + uint8_t CCPF_RWindowHeatSw_Stat; // Bits= 1 + + // Button status of the heated windshield, front door windows and side mirrors + // 1 : "Pressed" + // 0 : "Not pressed" + uint8_t CCPF_FWindowHeatSw_Stat; // Bits= 1 + + // Change TV source change switch status + // 1 : "Pressed" + // 0 : "Not pressed" + uint8_t CCPR_SrcChgSw_Stat; // Bits= 1 + + // Patrition transparency switch status + // 1 : "Pressed" + // 0 : "Not pressed" + uint8_t CCPR_DWClaritySw_Stat; // Bits= 1 + + // Intercom switch status + // 1 : "Pressed" + // 0 : "Not pressed" + uint8_t CCPR_IntercomSw_Stat; // Bits= 1 + + // Patrition control switch status + // 2 : "Pressed right button (DW up)" + // 1 : "Pressed left button (DW down)" + // 0 : "Not pressed" + uint8_t CCPR_DWCntrlSw_Stat; // Bits= 2 + + // Mute button status and display FIU + // 2 : "MMS ON/OFF requested" + // 1 : "Mute ON/OFF requested" + // 0 : "Not requested" + uint8_t CCPF_MuteSw_Stat; // Bits= 2 + + // Volume ajustment switch status + // 2 : "Volume -" + // 1 : "Volume +" + // 0 : "Not pressed" + uint8_t CCPF_VolAjustSw_Stat; // Bits= 2 + + // Panoramic view switch status + // 2 : "Long pressed" + // 1 : "Pressed" + // 0 : "Not pressed" + uint8_t CCPR_PanoramicViewSw_Stat; // Bits= 2 + + // Front climate panel right AUTO button status + // 2 : "Button hold pressed" + // 1 : "Button Pressed" + // 0 : "Button Released" + uint8_t CCPF_AutoButtonR_Stat; // Bits= 2 + + // Rear climate panel left AUTO button status + // 2 : "Button hold pressed" + // 1 : "Button pressed" + // 0 : "Button released" + uint8_t CCPR_AutoButtonL_Stat; // Bits= 2 + + // Rear climate panel right AUTO button status + // 2 : "Button hold pressed" + // 1 : "Button pressed" + // 0 : "Button released" + uint8_t CCPR_AutoButtonR_Stat; // Bits= 2 + + // Front climate panel DEFROST button status + // 2 : "Button hold pressed" + // 1 : "Button pressed" + // 0 : "Button released" + uint8_t CCPF_DefButton_Stat; // Bits= 2 + + // Front climate panel right TEMPERATURE toggle status + // 4 : "Toggle hold lowered " + // 3 : "Toggle hold raised " + // 2 : "Toggle lowered" + // 1 : "Toggle raised" + // 0 : "Toggle released" + uint8_t CCPF_TempToggleR_Stat; // Bits= 3 + + // Front climate panel left TEMPERATURE toggle status + // 4 : "Toggle hold lowered " + // 3 : "Toggle hold raised " + // 2 : "Toggle lowered" + // 1 : "Toggle raised" + // 0 : "Toggle released" + uint8_t CCPF_TempToggleL_Stat; // Bits= 3 + + // Front climate panel left AUTO button status + // 2 : "Button hold pressed" + // 1 : "Button pressed" + // 0 : "Button released" + uint8_t CCPF_AutoButtonL_Stat; // Bits= 2 + + // Rear climate panel right TEMPERATURE toggle status + // 4 : "Toggle hold lowered " + // 3 : "Toggle hold raised " + // 2 : "Toggle lowered" + // 1 : "Toggle raised" + // 0 : "Toggle released" + uint8_t CCPR_TempToggleR_Stat; // Bits= 3 + + // Rear climate panel left TEMPERATURE toggle status + // 4 : "Toggle hold lowered " + // 3 : "Toggle hold raised " + // 2 : "Toggle lowered" + // 1 : "Toggle raised" + // 0 : "Toggle released" + uint8_t CCPR_TempToggleL_Stat; // Bits= 3 + + // Front climate panel RECIRCULATION button status + // 2 : "Button hold pressed" + // 1 : "Button pressed" + // 0 : "Button released" + uint8_t CCPF_RecButton_Stat; // Bits= 2 + + // Front climate panel AC MAX button status + // 2 : "Button hold pressed " + // 1 : "Button pressed" + // 0 : "Button released" + uint8_t CCPF_AcMaxButton_Stat; // Bits= 2 + + // Tablet On/Off switch status. + // Short Press - Screen OFF request + // Long Press - Central Tablet OFF request + // 1 : "Mute ON/OFF requested" + // 0 : "Not requested" + // 2 : "MMS ON/OFF requested" + uint8_t CCPR_TabletOffSw_Stat; // Bits= 2 + + // Tablet extraction switch status + // Center rear tablet removal signal + // 1 : "Pressed" + // 0 : "Not pressed" + uint8_t CCPR_TabletExtractSw_Stat; // Bits= 1 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} TM_CP_t; + +// def @VAU2_Msg2 CAN Message (591 0x24f) +#define VAU2_Msg2_IDE (0U) +#define VAU2_Msg2_DLC (5U) +#define VAU2_Msg2_CANID (0x24fU) +#define VAU2_Msg2_CYC (100U) + +// Value tables for @VAU_WarningInd signal + +#ifndef VAU_WarningInd_VAU2_Msg2_VAU_SystemFailure +#define VAU_WarningInd_VAU2_Msg2_VAU_SystemFailure (1) +#endif + +#ifndef VAU_WarningInd_VAU2_Msg2_No_Warning +#define VAU_WarningInd_VAU2_Msg2_No_Warning (0) +#endif + + +// Value tables for @VAU_ExteriorKeyFobSwReq signal + +#ifndef VAU_ExteriorKeyFobSwReq_VAU2_Msg2_Remote_Start_Pressed_Long +#define VAU_ExteriorKeyFobSwReq_VAU2_Msg2_Remote_Start_Pressed_Long (8) +#endif + +#ifndef VAU_ExteriorKeyFobSwReq_VAU2_Msg2_Reserved +#define VAU_ExteriorKeyFobSwReq_VAU2_Msg2_Reserved (7) +#endif + +#ifndef VAU_ExteriorKeyFobSwReq_VAU2_Msg2_Unlock_Pressed_Long +#define VAU_ExteriorKeyFobSwReq_VAU2_Msg2_Unlock_Pressed_Long (6) +#endif + +#ifndef VAU_ExteriorKeyFobSwReq_VAU2_Msg2_Unlock_Pressed +#define VAU_ExteriorKeyFobSwReq_VAU2_Msg2_Unlock_Pressed (5) +#endif + +#ifndef VAU_ExteriorKeyFobSwReq_VAU2_Msg2_Trunk_Pressed_Long +#define VAU_ExteriorKeyFobSwReq_VAU2_Msg2_Trunk_Pressed_Long (4) +#endif + +#ifndef VAU_ExteriorKeyFobSwReq_VAU2_Msg2_Reserved +#define VAU_ExteriorKeyFobSwReq_VAU2_Msg2_Reserved (3) +#endif + +#ifndef VAU_ExteriorKeyFobSwReq_VAU2_Msg2_Lock_Pressed_Long +#define VAU_ExteriorKeyFobSwReq_VAU2_Msg2_Lock_Pressed_Long (2) +#endif + +#ifndef VAU_ExteriorKeyFobSwReq_VAU2_Msg2_Lock_Pressed +#define VAU_ExteriorKeyFobSwReq_VAU2_Msg2_Lock_Pressed (1) +#endif + +#ifndef VAU_ExteriorKeyFobSwReq_VAU2_Msg2_No_Request +#define VAU_ExteriorKeyFobSwReq_VAU2_Msg2_No_Request (0) +#endif + + +// Value tables for @VAU_DeviceAreaDetecting signal + +#ifndef VAU_DeviceAreaDetecting_VAU2_Msg2_Smartphone_in_Vehicle_area +#define VAU_DeviceAreaDetecting_VAU2_Msg2_Smartphone_in_Vehicle_area (4) +#endif + +#ifndef VAU_DeviceAreaDetecting_VAU2_Msg2_Smartphone_in_Welcome_area +#define VAU_DeviceAreaDetecting_VAU2_Msg2_Smartphone_in_Welcome_area (3) +#endif + +#ifndef VAU_DeviceAreaDetecting_VAU2_Msg2_Key_fob_in_Vehicle_area +#define VAU_DeviceAreaDetecting_VAU2_Msg2_Key_fob_in_Vehicle_area (2) +#endif + +#ifndef VAU_DeviceAreaDetecting_VAU2_Msg2_Key_fob_in_Welcome_area +#define VAU_DeviceAreaDetecting_VAU2_Msg2_Key_fob_in_Welcome_area (1) +#endif + +#ifndef VAU_DeviceAreaDetecting_VAU2_Msg2_No_Device_Detected +#define VAU_DeviceAreaDetecting_VAU2_Msg2_No_Device_Detected (0) +#endif + + +// Value tables for @VAU_KeyBattLowCharge signal + +#ifndef VAU_KeyBattLowCharge_VAU2_Msg2_LowBatteryVoltage_Primary_key_fob +#define VAU_KeyBattLowCharge_VAU2_Msg2_LowBatteryVoltage_Primary_key_fob (1) +#endif + +#ifndef VAU_KeyBattLowCharge_VAU2_Msg2_No_Warning +#define VAU_KeyBattLowCharge_VAU2_Msg2_No_Warning (0) +#endif + + +// Value tables for @VAU_WelcomeLights_Req signal + +#ifndef VAU_WelcomeLights_Req_VAU2_Msg2_WelcomeLights_Req +#define VAU_WelcomeLights_Req_VAU2_Msg2_WelcomeLights_Req (1) +#endif + +#ifndef VAU_WelcomeLights_Req_VAU2_Msg2_No_Request +#define VAU_WelcomeLights_Req_VAU2_Msg2_No_Request (0) +#endif + + +// Value tables for @VAU_ApproachLock_Req signal + +#ifndef VAU_ApproachLock_Req_VAU2_Msg2_Reserved +#define VAU_ApproachLock_Req_VAU2_Msg2_Reserved (3) +#endif + +#ifndef VAU_ApproachLock_Req_VAU2_Msg2_VehilcleApproachUnlock_Req +#define VAU_ApproachLock_Req_VAU2_Msg2_VehilcleApproachUnlock_Req (2) +#endif + +#ifndef VAU_ApproachLock_Req_VAU2_Msg2_LeavingVehilceLock_Req +#define VAU_ApproachLock_Req_VAU2_Msg2_LeavingVehilceLock_Req (1) +#endif + +#ifndef VAU_ApproachLock_Req_VAU2_Msg2_No_Request +#define VAU_ApproachLock_Req_VAU2_Msg2_No_Request (0) +#endif + + +// Value tables for @VAU_Router_DevicePairing signal + +#ifndef VAU_Router_DevicePairing_VAU2_Msg2_Deleting_Unsuccess +#define VAU_Router_DevicePairing_VAU2_Msg2_Deleting_Unsuccess (10) +#endif + +#ifndef VAU_Router_DevicePairing_VAU2_Msg2_Deleting_Success +#define VAU_Router_DevicePairing_VAU2_Msg2_Deleting_Success (9) +#endif + +#ifndef VAU_Router_DevicePairing_VAU2_Msg2_Deleting_Inprogress +#define VAU_Router_DevicePairing_VAU2_Msg2_Deleting_Inprogress (8) +#endif + +#ifndef VAU_Router_DevicePairing_VAU2_Msg2_Pairing_Unsuccess +#define VAU_Router_DevicePairing_VAU2_Msg2_Pairing_Unsuccess (7) +#endif + +#ifndef VAU_Router_DevicePairing_VAU2_Msg2_No_Device_Detected +#define VAU_Router_DevicePairing_VAU2_Msg2_No_Device_Detected (6) +#endif + +#ifndef VAU_Router_DevicePairing_VAU2_Msg2_Key_Fob_not_in_Immo_antenna +#define VAU_Router_DevicePairing_VAU2_Msg2_Key_Fob_not_in_Immo_antenna (5) +#endif + +#ifndef VAU_Router_DevicePairing_VAU2_Msg2_Pairing_Success +#define VAU_Router_DevicePairing_VAU2_Msg2_Pairing_Success (4) +#endif + +#ifndef VAU_Router_DevicePairing_VAU2_Msg2_Pairing_Inprogress +#define VAU_Router_DevicePairing_VAU2_Msg2_Pairing_Inprogress (3) +#endif + +#ifndef VAU_Router_DevicePairing_VAU2_Msg2_BLE_DeviceDetect +#define VAU_Router_DevicePairing_VAU2_Msg2_BLE_DeviceDetect (2) +#endif + +#ifndef VAU_Router_DevicePairing_VAU2_Msg2_NFC_DeviceDetect +#define VAU_Router_DevicePairing_VAU2_Msg2_NFC_DeviceDetect (1) +#endif + +#ifndef VAU_Router_DevicePairing_VAU2_Msg2_No_Request +#define VAU_Router_DevicePairing_VAU2_Msg2_No_Request (0) +#endif + + +// Value tables for @VAU_WChF_Req signal + +#ifndef VAU_WChF_Req_VAU2_Msg2_WChF_ON_Request +#define VAU_WChF_Req_VAU2_Msg2_WChF_ON_Request (1) +#endif + +#ifndef VAU_WChF_Req_VAU2_Msg2_WChF_OFF_Request +#define VAU_WChF_Req_VAU2_Msg2_WChF_OFF_Request (0) +#endif + + +// Value tables for @VAU_BLE_FL_Door_Req signal + +#ifndef VAU_BLE_FL_Door_Req_VAU2_Msg2_Close_Door_request +#define VAU_BLE_FL_Door_Req_VAU2_Msg2_Close_Door_request (2) +#endif + +#ifndef VAU_BLE_FL_Door_Req_VAU2_Msg2_Open_Door_request +#define VAU_BLE_FL_Door_Req_VAU2_Msg2_Open_Door_request (1) +#endif + +#ifndef VAU_BLE_FL_Door_Req_VAU2_Msg2_No_request +#define VAU_BLE_FL_Door_Req_VAU2_Msg2_No_request (0) +#endif + + +// Value tables for @VAU_BLE_FR_Door_Req signal + +#ifndef VAU_BLE_FR_Door_Req_VAU2_Msg2_Close_Door_request +#define VAU_BLE_FR_Door_Req_VAU2_Msg2_Close_Door_request (2) +#endif + +#ifndef VAU_BLE_FR_Door_Req_VAU2_Msg2_Open_Door_request +#define VAU_BLE_FR_Door_Req_VAU2_Msg2_Open_Door_request (1) +#endif + +#ifndef VAU_BLE_FR_Door_Req_VAU2_Msg2_No_request +#define VAU_BLE_FR_Door_Req_VAU2_Msg2_No_request (0) +#endif + + +// Value tables for @VAU_BLE_RL_Door_Req signal + +#ifndef VAU_BLE_RL_Door_Req_VAU2_Msg2_Close_Door_request +#define VAU_BLE_RL_Door_Req_VAU2_Msg2_Close_Door_request (2) +#endif + +#ifndef VAU_BLE_RL_Door_Req_VAU2_Msg2_Open_Door_request +#define VAU_BLE_RL_Door_Req_VAU2_Msg2_Open_Door_request (1) +#endif + +#ifndef VAU_BLE_RL_Door_Req_VAU2_Msg2_No_request +#define VAU_BLE_RL_Door_Req_VAU2_Msg2_No_request (0) +#endif + + +// Value tables for @VAU_RS_Req signal + +#ifndef VAU_RS_Req_VAU2_Msg2_Remote_Start_Request +#define VAU_RS_Req_VAU2_Msg2_Remote_Start_Request (1) +#endif + +#ifndef VAU_RS_Req_VAU2_Msg2_No_Request +#define VAU_RS_Req_VAU2_Msg2_No_Request (0) +#endif + + +// Value tables for @VAU_BLE_RR_Door_Req signal + +#ifndef VAU_BLE_RR_Door_Req_VAU2_Msg2_Close_Door_request +#define VAU_BLE_RR_Door_Req_VAU2_Msg2_Close_Door_request (2) +#endif + +#ifndef VAU_BLE_RR_Door_Req_VAU2_Msg2_Open_Door_request +#define VAU_BLE_RR_Door_Req_VAU2_Msg2_Open_Door_request (1) +#endif + +#ifndef VAU_BLE_RR_Door_Req_VAU2_Msg2_No_request +#define VAU_BLE_RR_Door_Req_VAU2_Msg2_No_request (0) +#endif + + +// Value tables for @VAU_BLE_CloseWndw_Req signal + +#ifndef VAU_BLE_CloseWndw_Req_VAU2_Msg2_Close_all_windows_request +#define VAU_BLE_CloseWndw_Req_VAU2_Msg2_Close_all_windows_request (2) +#endif + +#ifndef VAU_BLE_CloseWndw_Req_VAU2_Msg2_Open_all_windows_request +#define VAU_BLE_CloseWndw_Req_VAU2_Msg2_Open_all_windows_request (1) +#endif + +#ifndef VAU_BLE_CloseWndw_Req_VAU2_Msg2_No_request +#define VAU_BLE_CloseWndw_Req_VAU2_Msg2_No_request (0) +#endif + + +// Value tables for @VAU_BLE_TrunkOpn_Req signal + +#ifndef VAU_BLE_TrunkOpn_Req_VAU2_Msg2_Close_Trunk_Lid_request +#define VAU_BLE_TrunkOpn_Req_VAU2_Msg2_Close_Trunk_Lid_request (2) +#endif + +#ifndef VAU_BLE_TrunkOpn_Req_VAU2_Msg2_Open_Trunk_Lid_request +#define VAU_BLE_TrunkOpn_Req_VAU2_Msg2_Open_Trunk_Lid_request (1) +#endif + +#ifndef VAU_BLE_TrunkOpn_Req_VAU2_Msg2_No_request +#define VAU_BLE_TrunkOpn_Req_VAU2_Msg2_No_request (0) +#endif + + +// Value tables for @VAU_BLE_Lock_Req signal + +#ifndef VAU_BLE_Lock_Req_VAU2_Msg2_Lock_Request +#define VAU_BLE_Lock_Req_VAU2_Msg2_Lock_Request (2) +#endif + +#ifndef VAU_BLE_Lock_Req_VAU2_Msg2_Unlock_Request +#define VAU_BLE_Lock_Req_VAU2_Msg2_Unlock_Request (1) +#endif + +#ifndef VAU_BLE_Lock_Req_VAU2_Msg2_No_Request +#define VAU_BLE_Lock_Req_VAU2_Msg2_No_Request (0) +#endif + + +// Value tables for @VAU_BLE_RS_Req signal + +#ifndef VAU_BLE_RS_Req_VAU2_Msg2_Remote_Start_request +#define VAU_BLE_RS_Req_VAU2_Msg2_Remote_Start_request (1) +#endif + +#ifndef VAU_BLE_RS_Req_VAU2_Msg2_No_Request +#define VAU_BLE_RS_Req_VAU2_Msg2_No_Request (0) +#endif + + +// Value tables for @VAU_Device_ID signal + +#ifndef VAU_Device_ID_VAU2_Msg2_Key_fob_ID_0xF +#define VAU_Device_ID_VAU2_Msg2_Key_fob_ID_0xF (15) +#endif + +#ifndef VAU_Device_ID_VAU2_Msg2_Key_fob_ID_0xE +#define VAU_Device_ID_VAU2_Msg2_Key_fob_ID_0xE (14) +#endif + +#ifndef VAU_Device_ID_VAU2_Msg2_Key_fob_ID_0xD +#define VAU_Device_ID_VAU2_Msg2_Key_fob_ID_0xD (13) +#endif + +#ifndef VAU_Device_ID_VAU2_Msg2_Key_fob_ID_0xC +#define VAU_Device_ID_VAU2_Msg2_Key_fob_ID_0xC (12) +#endif + +#ifndef VAU_Device_ID_VAU2_Msg2_Key_fob_ID_0xB +#define VAU_Device_ID_VAU2_Msg2_Key_fob_ID_0xB (11) +#endif + +#ifndef VAU_Device_ID_VAU2_Msg2_Key_fob_ID_0xA +#define VAU_Device_ID_VAU2_Msg2_Key_fob_ID_0xA (10) +#endif + +#ifndef VAU_Device_ID_VAU2_Msg2_Key_fob_ID_0x9 +#define VAU_Device_ID_VAU2_Msg2_Key_fob_ID_0x9 (9) +#endif + +#ifndef VAU_Device_ID_VAU2_Msg2_Key_fob_ID_0x8 +#define VAU_Device_ID_VAU2_Msg2_Key_fob_ID_0x8 (8) +#endif + +#ifndef VAU_Device_ID_VAU2_Msg2_Key_fob_ID_0x7 +#define VAU_Device_ID_VAU2_Msg2_Key_fob_ID_0x7 (7) +#endif + +#ifndef VAU_Device_ID_VAU2_Msg2_Key_fob_ID_0x6 +#define VAU_Device_ID_VAU2_Msg2_Key_fob_ID_0x6 (6) +#endif + +#ifndef VAU_Device_ID_VAU2_Msg2_Key_fob_ID_0x5 +#define VAU_Device_ID_VAU2_Msg2_Key_fob_ID_0x5 (5) +#endif + +#ifndef VAU_Device_ID_VAU2_Msg2_Key_fob_ID_0x4 +#define VAU_Device_ID_VAU2_Msg2_Key_fob_ID_0x4 (4) +#endif + +#ifndef VAU_Device_ID_VAU2_Msg2_Key_fob_ID_0x3 +#define VAU_Device_ID_VAU2_Msg2_Key_fob_ID_0x3 (3) +#endif + +#ifndef VAU_Device_ID_VAU2_Msg2_Key_fob_ID_0x2 +#define VAU_Device_ID_VAU2_Msg2_Key_fob_ID_0x2 (2) +#endif + +#ifndef VAU_Device_ID_VAU2_Msg2_Key_fob_ID_0x1 +#define VAU_Device_ID_VAU2_Msg2_Key_fob_ID_0x1 (1) +#endif + +#ifndef VAU_Device_ID_VAU2_Msg2_No_key_fob_detected +#define VAU_Device_ID_VAU2_Msg2_No_key_fob_detected (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Status of presence of errors of electrical equipment of access system + // 1 : "VAU_SystemFailure" + // 0 : "No_Warning" + uint8_t VAU_WarningInd : 1; // Bits= 1 + + // Request to lock/unlock from the key fob + // 8 : "Remote_Start_Pressed_Long" + // 7 : "Reserved" + // 6 : "Unlock_Pressed_Long" + // 5 : "Unlock_Pressed" + // 4 : "Trunk_Pressed Long" + // 3 : "Reserved" + // 2 : "Lock_Pressed_Long" + // 1 : "Lock_Pressed" + // 0 : "No_Request" + uint8_t VAU_ExteriorKeyFobSwReq : 4; // Bits= 4 + + // The zone in which the key fob was detected + // 4 : "Smartphone in ''Vehicle area''" + // 3 : "Smartphone in ''Welcome area''" + // 2 : "Key fob in ''Vehicle area''" + // 1 : "Key fob in ''Welcome area''" + // 0 : "No_Device_Detected" + uint8_t VAU_DeviceAreaDetecting : 3; // Bits= 3 + + // Indicates the key Fob battery is discharged: + // $0 = Normal Battery Charge + // $1 = Low Battery Charge + // 1 : "LowBatteryVoltage_Primary key fob" + // 0 : "No_Warning" + uint8_t VAU_KeyBattLowCharge : 1; // Bits= 1 + + // Request to activate the welcoming light when approaching the car + // 1 : "WelcomeLights_Req" + // 0 : "No_Request" + uint8_t VAU_WelcomeLights_Req : 1; // Bits= 1 + + // Request to block the car when moving away from the car with the key + // 3 : "Reserved" + // 2 : "VehilcleApproachUnlock_Req" + // 1 : "LeavingVehilceLock_Req" + // 0 : "No_Request" + uint8_t VAU_ApproachLock_Req : 2; // Bits= 2 + + // Status of execution a pairig procedure Smartphone with VAU + // 10 : "Deleting_Unsuccess" + // 9 : "Deleting_Success" + // 8 : "Deleting_Inprogress" + // 7 : "Pairing_Unsuccess" + // 6 : "No_Device_Detected" + // 5 : "Key Fob not in Immo antenna" + // 4 : "Pairing_Success" + // 3 : "Pairing_Inprogress" + // 2 : "BLE_DeviceDetect" + // 1 : "NFC_DeviceDetect" + // 0 : "No_Request" + uint8_t VAU_Router_DevicePairing : 4; // Bits= 4 + + // Permission to operate wireless charging + // 1 : "WChF ON Request" + // 0 : "WChF OFF Request" + uint8_t VAU_WChF_Req : 1; // Bits= 1 + + // Request to control the movement of the FL door via the app via BLE channel. + // 2 : "Close Door request" + // 1 : "Open Door request" + // 0 : "No request" + uint8_t VAU_BLE_FL_Door_Req : 2; // Bits= 2 + + // Request to control the movement of the FR door via the app via BLE channel. + // 2 : "Close Door request" + // 1 : "Open Door request" + // 0 : "No request" + uint8_t VAU_BLE_FR_Door_Req : 2; // Bits= 2 + + // Request to control the movement of the RL door via the app via BLE channel. + // 2 : "Close Door request" + // 1 : "Open Door request" + // 0 : "No request" + uint8_t VAU_BLE_RL_Door_Req : 2; // Bits= 2 + + // The Authorizated request for Remote Start, which recieved via SDM (User request via smartphone) + // 1 : "Remote Start_Request" + // 0 : "No_Request" + uint8_t VAU_RS_Req : 1; // Bits= 1 + + // Request to control the movement of the RR door via the app via BLE channel. + // 2 : "Close Door request" + // 1 : "Open Door request" + // 0 : "No request" + uint8_t VAU_BLE_RR_Door_Req : 2; // Bits= 2 + + // Request to close all windows via the application via BLE channel. + // 2 : "Close all windows request" + // 1 : "Open all windows request" + // 0 : "No request" + uint8_t VAU_BLE_CloseWndw_Req : 2; // Bits= 2 + + // Request to control the movement of the trunk lid via the application via BLE channel. + // 2 : "Close Trunk Lid request" + // 1 : "Open Trunk Lid request" + // 0 : "No request" + uint8_t VAU_BLE_TrunkOpn_Req : 2; // Bits= 2 + + // Requests to unlock or lock te vehicle via aplication by BLE + // 2 : "Lock Request" + // 1 : "Unlock Request" + // 0 : "No Request" + uint8_t VAU_BLE_Lock_Req : 2; // Bits= 2 + + // Request for remote car start via application via BLE channel. + // 1 : "Remote Start request" + // 0 : "No Request" + uint8_t VAU_BLE_RS_Req : 1; // Bits= 1 + + // The ID of the key that was detected in the vehicle area + // 15 : "Key fob ID 0xF" + // 14 : "Key fob ID 0xE" + // 13 : "Key fob ID 0xD" + // 12 : "Key fob ID 0xC" + // 11 : "Key fob ID 0xB" + // 10 : "Key fob ID 0xA" + // 9 : "Key fob ID 0x9" + // 8 : "Key fob ID 0x8" + // 7 : "Key fob ID 0x7" + // 6 : "Key fob ID 0x6" + // 5 : "Key fob ID 0x5" + // 4 : "Key fob ID 0x4" + // 3 : "Key fob ID 0x3" + // 2 : "Key fob ID 0x2" + // 1 : "Key fob ID 0x1" + // 0 : "No key fob detected" + uint8_t VAU_Device_ID : 4; // Bits= 4 + +#else + + // Status of presence of errors of electrical equipment of access system + // 1 : "VAU_SystemFailure" + // 0 : "No_Warning" + uint8_t VAU_WarningInd; // Bits= 1 + + // Request to lock/unlock from the key fob + // 8 : "Remote_Start_Pressed_Long" + // 7 : "Reserved" + // 6 : "Unlock_Pressed_Long" + // 5 : "Unlock_Pressed" + // 4 : "Trunk_Pressed Long" + // 3 : "Reserved" + // 2 : "Lock_Pressed_Long" + // 1 : "Lock_Pressed" + // 0 : "No_Request" + uint8_t VAU_ExteriorKeyFobSwReq; // Bits= 4 + + // The zone in which the key fob was detected + // 4 : "Smartphone in ''Vehicle area''" + // 3 : "Smartphone in ''Welcome area''" + // 2 : "Key fob in ''Vehicle area''" + // 1 : "Key fob in ''Welcome area''" + // 0 : "No_Device_Detected" + uint8_t VAU_DeviceAreaDetecting; // Bits= 3 + + // Indicates the key Fob battery is discharged: + // $0 = Normal Battery Charge + // $1 = Low Battery Charge + // 1 : "LowBatteryVoltage_Primary key fob" + // 0 : "No_Warning" + uint8_t VAU_KeyBattLowCharge; // Bits= 1 + + // Request to activate the welcoming light when approaching the car + // 1 : "WelcomeLights_Req" + // 0 : "No_Request" + uint8_t VAU_WelcomeLights_Req; // Bits= 1 + + // Request to block the car when moving away from the car with the key + // 3 : "Reserved" + // 2 : "VehilcleApproachUnlock_Req" + // 1 : "LeavingVehilceLock_Req" + // 0 : "No_Request" + uint8_t VAU_ApproachLock_Req; // Bits= 2 + + // Status of execution a pairig procedure Smartphone with VAU + // 10 : "Deleting_Unsuccess" + // 9 : "Deleting_Success" + // 8 : "Deleting_Inprogress" + // 7 : "Pairing_Unsuccess" + // 6 : "No_Device_Detected" + // 5 : "Key Fob not in Immo antenna" + // 4 : "Pairing_Success" + // 3 : "Pairing_Inprogress" + // 2 : "BLE_DeviceDetect" + // 1 : "NFC_DeviceDetect" + // 0 : "No_Request" + uint8_t VAU_Router_DevicePairing; // Bits= 4 + + // Permission to operate wireless charging + // 1 : "WChF ON Request" + // 0 : "WChF OFF Request" + uint8_t VAU_WChF_Req; // Bits= 1 + + // Request to control the movement of the FL door via the app via BLE channel. + // 2 : "Close Door request" + // 1 : "Open Door request" + // 0 : "No request" + uint8_t VAU_BLE_FL_Door_Req; // Bits= 2 + + // Request to control the movement of the FR door via the app via BLE channel. + // 2 : "Close Door request" + // 1 : "Open Door request" + // 0 : "No request" + uint8_t VAU_BLE_FR_Door_Req; // Bits= 2 + + // Request to control the movement of the RL door via the app via BLE channel. + // 2 : "Close Door request" + // 1 : "Open Door request" + // 0 : "No request" + uint8_t VAU_BLE_RL_Door_Req; // Bits= 2 + + // The Authorizated request for Remote Start, which recieved via SDM (User request via smartphone) + // 1 : "Remote Start_Request" + // 0 : "No_Request" + uint8_t VAU_RS_Req; // Bits= 1 + + // Request to control the movement of the RR door via the app via BLE channel. + // 2 : "Close Door request" + // 1 : "Open Door request" + // 0 : "No request" + uint8_t VAU_BLE_RR_Door_Req; // Bits= 2 + + // Request to close all windows via the application via BLE channel. + // 2 : "Close all windows request" + // 1 : "Open all windows request" + // 0 : "No request" + uint8_t VAU_BLE_CloseWndw_Req; // Bits= 2 + + // Request to control the movement of the trunk lid via the application via BLE channel. + // 2 : "Close Trunk Lid request" + // 1 : "Open Trunk Lid request" + // 0 : "No request" + uint8_t VAU_BLE_TrunkOpn_Req; // Bits= 2 + + // Requests to unlock or lock te vehicle via aplication by BLE + // 2 : "Lock Request" + // 1 : "Unlock Request" + // 0 : "No Request" + uint8_t VAU_BLE_Lock_Req; // Bits= 2 + + // Request for remote car start via application via BLE channel. + // 1 : "Remote Start request" + // 0 : "No Request" + uint8_t VAU_BLE_RS_Req; // Bits= 1 + + // The ID of the key that was detected in the vehicle area + // 15 : "Key fob ID 0xF" + // 14 : "Key fob ID 0xE" + // 13 : "Key fob ID 0xD" + // 12 : "Key fob ID 0xC" + // 11 : "Key fob ID 0xB" + // 10 : "Key fob ID 0xA" + // 9 : "Key fob ID 0x9" + // 8 : "Key fob ID 0x8" + // 7 : "Key fob ID 0x7" + // 6 : "Key fob ID 0x6" + // 5 : "Key fob ID 0x5" + // 4 : "Key fob ID 0x4" + // 3 : "Key fob ID 0x3" + // 2 : "Key fob ID 0x2" + // 1 : "Key fob ID 0x1" + // 0 : "No key fob detected" + uint8_t VAU_Device_ID; // Bits= 4 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} VAU2_Msg2_t; + +// def @BCM_DMS_01 CAN Message (593 0x251) +#define BCM_DMS_01_IDE (0U) +#define BCM_DMS_01_DLC (3U) +#define BCM_DMS_01_CANID (0x251U) +#define BCM_DMS_01_CYC (100U) + +// Value tables for @DrivingMode_Sig signal + +#ifndef DrivingMode_Sig_BCM_DMS_01_Signal_failure +#define DrivingMode_Sig_BCM_DMS_01_Signal_failure (4) +#endif + +#ifndef DrivingMode_Sig_BCM_DMS_01_All_Road_mode +#define DrivingMode_Sig_BCM_DMS_01_All_Road_mode (3) +#endif + +#ifndef DrivingMode_Sig_BCM_DMS_01_Comfort_mode +#define DrivingMode_Sig_BCM_DMS_01_Comfort_mode (2) +#endif + +#ifndef DrivingMode_Sig_BCM_DMS_01_Sport_mode +#define DrivingMode_Sig_BCM_DMS_01_Sport_mode (1) +#endif + +#ifndef DrivingMode_Sig_BCM_DMS_01_Auto_mode +#define DrivingMode_Sig_BCM_DMS_01_Auto_mode (0) +#endif + + +// Value tables for @DMS_HDC_Req signal + +#ifndef DMS_HDC_Req_BCM_DMS_01_Request +#define DMS_HDC_Req_BCM_DMS_01_Request (1) +#endif + +#ifndef DMS_HDC_Req_BCM_DMS_01_No_Request +#define DMS_HDC_Req_BCM_DMS_01_No_Request (0) +#endif + + +// Value tables for @UpwardPosReq signal + +#ifndef UpwardPosReq_BCM_DMS_01_Upper_suspension_position_request_ +#define UpwardPosReq_BCM_DMS_01_Upper_suspension_position_request_ (1) +#endif + +#ifndef UpwardPosReq_BCM_DMS_01_No_request +#define UpwardPosReq_BCM_DMS_01_No_request (0) +#endif + + +// Value tables for @DownwardPosReq signal + +#ifndef DownwardPosReq_BCM_DMS_01_Lower_suspension_position_request +#define DownwardPosReq_BCM_DMS_01_Lower_suspension_position_request (1) +#endif + +#ifndef DownwardPosReq_BCM_DMS_01_No_request +#define DownwardPosReq_BCM_DMS_01_No_request (0) +#endif + + +// Value tables for @DMS_ServiceMode signal + +#ifndef DMS_ServiceMode_BCM_DMS_01_Request +#define DMS_ServiceMode_BCM_DMS_01_Request (1) +#endif + +#ifndef DMS_ServiceMode_BCM_DMS_01_No_Request +#define DMS_ServiceMode_BCM_DMS_01_No_Request (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // This signal provide information about selected driving mode + // 4 : "Signal failure" + // 3 : "All Road mode" + // 2 : "Comfort mode" + // 1 : "Sport mode" + // 0 : "Auto mode" + uint8_t DrivingMode_Sig : 4; // Bits= 4 + + // Hill Descent Assist function requested by the driver: + // $0 = HDC Not Requested + // $1 = HDC Requested + // 1 : "Request" + // 0 : "No Request" + uint8_t DMS_HDC_Req : 1; // Bits= 1 + + // Request heightening the position (stepwise) + // 1 : "Upper suspension position request " + // 0 : "No request" + uint8_t UpwardPosReq : 1; // Bits= 1 + + // request lowering the position (stepwise) + // 1 : "Lower suspension position request" + // 0 : "No request" + uint8_t DownwardPosReq : 1; // Bits= 1 + + // Service Mode requested by the driver: + // $0 = Service Mode Not Requested + // $1 = Service Mode Requested + // 1 : "Request" + // 0 : "No Request" + uint8_t DMS_ServiceMode : 1; // Bits= 1 + + // Rolling Counter [0 - 15] + uint8_t BCM_DMS_01_RC : 4; // Bits= 4 + + // Checksum XOR8 of the data field this message + // Checksum computed as per XOR algorithm: + // Byte 1 XOR byte 2 .... XOR byte n-1. (n = packet length.) + uint8_t BCM_DMS_01_CS; // Bits= 8 + +#else + + // This signal provide information about selected driving mode + // 4 : "Signal failure" + // 3 : "All Road mode" + // 2 : "Comfort mode" + // 1 : "Sport mode" + // 0 : "Auto mode" + uint8_t DrivingMode_Sig; // Bits= 4 + + // Hill Descent Assist function requested by the driver: + // $0 = HDC Not Requested + // $1 = HDC Requested + // 1 : "Request" + // 0 : "No Request" + uint8_t DMS_HDC_Req; // Bits= 1 + + // Request heightening the position (stepwise) + // 1 : "Upper suspension position request " + // 0 : "No request" + uint8_t UpwardPosReq; // Bits= 1 + + // request lowering the position (stepwise) + // 1 : "Lower suspension position request" + // 0 : "No request" + uint8_t DownwardPosReq; // Bits= 1 + + // Service Mode requested by the driver: + // $0 = Service Mode Not Requested + // $1 = Service Mode Requested + // 1 : "Request" + // 0 : "No Request" + uint8_t DMS_ServiceMode; // Bits= 1 + + // Rolling Counter [0 - 15] + uint8_t BCM_DMS_01_RC; // Bits= 4 + + // Checksum XOR8 of the data field this message + // Checksum computed as per XOR algorithm: + // Byte 1 XOR byte 2 .... XOR byte n-1. (n = packet length.) + uint8_t BCM_DMS_01_CS; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} BCM_DMS_01_t; + +// def @LB_pSilCU_State CAN Message (594 0x252) +#define LB_pSilCU_State_IDE (0U) +#define LB_pSilCU_State_DLC (8U) +#define LB_pSilCU_State_CANID (0x252U) + +// Value tables for @LB_pSilCU_Module_Stat signal + +#ifndef LB_pSilCU_Module_Stat_LB_pSilCU_State_Scenario_data_message_error +#define LB_pSilCU_Module_Stat_LB_pSilCU_State_Scenario_data_message_error (8) +#endif + +#ifndef LB_pSilCU_Module_Stat_LB_pSilCU_State_Temperature_error +#define LB_pSilCU_Module_Stat_LB_pSilCU_State_Temperature_error (9) +#endif + +#ifndef LB_pSilCU_Module_Stat_LB_pSilCU_State_Channels_power_error +#define LB_pSilCU_Module_Stat_LB_pSilCU_State_Channels_power_error (10) +#endif + +#ifndef LB_pSilCU_Module_Stat_LB_pSilCU_State_Scenario_play_error +#define LB_pSilCU_Module_Stat_LB_pSilCU_State_Scenario_play_error (7) +#endif + +#ifndef LB_pSilCU_Module_Stat_LB_pSilCU_State_Launch_error +#define LB_pSilCU_Module_Stat_LB_pSilCU_State_Launch_error (6) +#endif + +#ifndef LB_pSilCU_Module_Stat_LB_pSilCU_State_Scenario_Data_is_recieved +#define LB_pSilCU_Module_Stat_LB_pSilCU_State_Scenario_Data_is_recieved (5) +#endif + +#ifndef LB_pSilCU_Module_Stat_LB_pSilCU_State_Configuration_is_going +#define LB_pSilCU_Module_Stat_LB_pSilCU_State_Configuration_is_going (4) +#endif + +#ifndef LB_pSilCU_Module_Stat_LB_pSilCU_State_Special_event_done +#define LB_pSilCU_Module_Stat_LB_pSilCU_State_Special_event_done (3) +#endif + +#ifndef LB_pSilCU_Module_Stat_LB_pSilCU_State_Scenario_have_done +#define LB_pSilCU_Module_Stat_LB_pSilCU_State_Scenario_have_done (2) +#endif + +#ifndef LB_pSilCU_Module_Stat_LB_pSilCU_State_Scenario_is_going +#define LB_pSilCU_Module_Stat_LB_pSilCU_State_Scenario_is_going (1) +#endif + +#ifndef LB_pSilCU_Module_Stat_LB_pSilCU_State_Ready +#define LB_pSilCU_Module_Stat_LB_pSilCU_State_Ready (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Module state: + // 0 - Module is ready for action + // 1 - Module has done a scenario + // 2 - Module made a special event + // 3 - Data is recieved + // 4 - Module start error + // 5 - Scenario play error + // 6 - Data error + // 7 - Temperature error + // 8 : "Scenario data message error" + // 9 : "Temperature error" + // 10 : "Channels power error" + // 7 : "Scenario play error" + // 6 : "Launch error" + // 5 : "Scenario Data is recieved" + // 4 : "Configuration is going" + // 3 : "Special event done" + // 2 : "Scenario have done" + // 1 : "Scenario is going" + // 0 : "Ready" + uint8_t LB_pSilCU_Module_Stat : 4; // Bits= 4 + + // Temperature value + int8_t LB_pSilCU_ModuleTemperature_Val : 7; // [-] Bits= 7 Unit:'�C' + + // Reserved + int8_t LB_pSilCU_reserved1 : 5; // [-] Bits= 5 + + // Reserved + int8_t LB_pSilCU_reserved2; // [-] Bits= 8 + + // Reserved + int8_t LB_pSilCU_reserved3; // [-] Bits= 8 + + // Reserved + int8_t LB_pSilCU_reserved4; // [-] Bits= 8 + + // Reserved + int8_t LB_pSilCU_reserved5; // [-] Bits= 8 + + // Reserved + int8_t LB_pSilCU_reserved6; // [-] Bits= 8 + + // Reserved + int8_t LB_pSilCU_reserved7; // [-] Bits= 8 + +#else + + // Module state: + // 0 - Module is ready for action + // 1 - Module has done a scenario + // 2 - Module made a special event + // 3 - Data is recieved + // 4 - Module start error + // 5 - Scenario play error + // 6 - Data error + // 7 - Temperature error + // 8 : "Scenario data message error" + // 9 : "Temperature error" + // 10 : "Channels power error" + // 7 : "Scenario play error" + // 6 : "Launch error" + // 5 : "Scenario Data is recieved" + // 4 : "Configuration is going" + // 3 : "Special event done" + // 2 : "Scenario have done" + // 1 : "Scenario is going" + // 0 : "Ready" + uint8_t LB_pSilCU_Module_Stat; // Bits= 4 + + // Temperature value + int8_t LB_pSilCU_ModuleTemperature_Val; // [-] Bits= 7 Unit:'�C' + + // Reserved + int8_t LB_pSilCU_reserved1; // [-] Bits= 5 + + // Reserved + int8_t LB_pSilCU_reserved2; // [-] Bits= 8 + + // Reserved + int8_t LB_pSilCU_reserved3; // [-] Bits= 8 + + // Reserved + int8_t LB_pSilCU_reserved4; // [-] Bits= 8 + + // Reserved + int8_t LB_pSilCU_reserved5; // [-] Bits= 8 + + // Reserved + int8_t LB_pSilCU_reserved6; // [-] Bits= 8 + + // Reserved + int8_t LB_pSilCU_reserved7; // [-] Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} LB_pSilCU_State_t; + +// def @RB_pSilCU_State CAN Message (595 0x253) +#define RB_pSilCU_State_IDE (0U) +#define RB_pSilCU_State_DLC (8U) +#define RB_pSilCU_State_CANID (0x253U) + +// Value tables for @RB_pSilCU_Module_Stat signal + +#ifndef RB_pSilCU_Module_Stat_RB_pSilCU_State_Scenario_data_message_error +#define RB_pSilCU_Module_Stat_RB_pSilCU_State_Scenario_data_message_error (8) +#endif + +#ifndef RB_pSilCU_Module_Stat_RB_pSilCU_State_Temperature_error +#define RB_pSilCU_Module_Stat_RB_pSilCU_State_Temperature_error (9) +#endif + +#ifndef RB_pSilCU_Module_Stat_RB_pSilCU_State_Channels_power_error +#define RB_pSilCU_Module_Stat_RB_pSilCU_State_Channels_power_error (10) +#endif + +#ifndef RB_pSilCU_Module_Stat_RB_pSilCU_State_Scenario_play_error +#define RB_pSilCU_Module_Stat_RB_pSilCU_State_Scenario_play_error (7) +#endif + +#ifndef RB_pSilCU_Module_Stat_RB_pSilCU_State_Launch_error +#define RB_pSilCU_Module_Stat_RB_pSilCU_State_Launch_error (6) +#endif + +#ifndef RB_pSilCU_Module_Stat_RB_pSilCU_State_Scenario_Data_is_recieved +#define RB_pSilCU_Module_Stat_RB_pSilCU_State_Scenario_Data_is_recieved (5) +#endif + +#ifndef RB_pSilCU_Module_Stat_RB_pSilCU_State_Configuration_is_going +#define RB_pSilCU_Module_Stat_RB_pSilCU_State_Configuration_is_going (4) +#endif + +#ifndef RB_pSilCU_Module_Stat_RB_pSilCU_State_Special_event_done +#define RB_pSilCU_Module_Stat_RB_pSilCU_State_Special_event_done (3) +#endif + +#ifndef RB_pSilCU_Module_Stat_RB_pSilCU_State_Scenario_have_done +#define RB_pSilCU_Module_Stat_RB_pSilCU_State_Scenario_have_done (2) +#endif + +#ifndef RB_pSilCU_Module_Stat_RB_pSilCU_State_Scenario_is_going +#define RB_pSilCU_Module_Stat_RB_pSilCU_State_Scenario_is_going (1) +#endif + +#ifndef RB_pSilCU_Module_Stat_RB_pSilCU_State_Ready +#define RB_pSilCU_Module_Stat_RB_pSilCU_State_Ready (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Module state: + // 0 - Module is ready for action + // 1 - Module has done a scenario + // 2 - Module made a special event + // 3 - Data is recieved + // 4 - Module start error + // 5 - Scenario play error + // 6 - Data error + // 7 - Temperature error + // 8 : "Scenario data message error" + // 9 : "Temperature error" + // 10 : "Channels power error" + // 7 : "Scenario play error" + // 6 : "Launch error" + // 5 : "Scenario Data is recieved" + // 4 : "Configuration is going" + // 3 : "Special event done" + // 2 : "Scenario have done" + // 1 : "Scenario is going" + // 0 : "Ready" + int8_t RB_pSilCU_Module_Stat : 4; // [-] Bits= 4 + + // Temperature value + int8_t RB_pSilCU_ModuleTemperature_Val : 7; // [-] Bits= 7 Unit:'�C' + + // Reserved + int8_t RB_pSilCU_reserved1 : 5; // [-] Bits= 5 + + // Reserved + int8_t RB_pSilCU_reserved2; // [-] Bits= 8 + + // Reserved + int8_t RB_pSilCU_reserved3; // [-] Bits= 8 + + // Reserved + int8_t RB_pSilCU_reserved4; // [-] Bits= 8 + + // Reserved + int8_t RB_pSilCU_reserved5; // [-] Bits= 8 + + // Reserved + int8_t RB_pSilCU_reserved6; // [-] Bits= 8 + + // Reserved + int8_t RB_pSilCU_reserved7; // [-] Bits= 8 + +#else + + // Module state: + // 0 - Module is ready for action + // 1 - Module has done a scenario + // 2 - Module made a special event + // 3 - Data is recieved + // 4 - Module start error + // 5 - Scenario play error + // 6 - Data error + // 7 - Temperature error + // 8 : "Scenario data message error" + // 9 : "Temperature error" + // 10 : "Channels power error" + // 7 : "Scenario play error" + // 6 : "Launch error" + // 5 : "Scenario Data is recieved" + // 4 : "Configuration is going" + // 3 : "Special event done" + // 2 : "Scenario have done" + // 1 : "Scenario is going" + // 0 : "Ready" + int8_t RB_pSilCU_Module_Stat; // [-] Bits= 4 + + // Temperature value + int8_t RB_pSilCU_ModuleTemperature_Val; // [-] Bits= 7 Unit:'�C' + + // Reserved + int8_t RB_pSilCU_reserved1; // [-] Bits= 5 + + // Reserved + int8_t RB_pSilCU_reserved2; // [-] Bits= 8 + + // Reserved + int8_t RB_pSilCU_reserved3; // [-] Bits= 8 + + // Reserved + int8_t RB_pSilCU_reserved4; // [-] Bits= 8 + + // Reserved + int8_t RB_pSilCU_reserved5; // [-] Bits= 8 + + // Reserved + int8_t RB_pSilCU_reserved6; // [-] Bits= 8 + + // Reserved + int8_t RB_pSilCU_reserved7; // [-] Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} RB_pSilCU_State_t; + +// def @HVC_CCU_Status_Msg CAN Message (602 0x25a) +#define HVC_CCU_Status_Msg_IDE (0U) +#define HVC_CCU_Status_Msg_DLC (3U) +#define HVC_CCU_Status_Msg_CANID (0x25aU) +#define HVC_CCU_Status_Msg_CYC (200U) +// signal: @HVC_eCompActSpeed_Val_ro +#define CANDB_HVC_eCompActSpeed_Val_ro_CovFactor (50) +#define CANDB_HVC_eCompActSpeed_Val_ro_toS(x) ( (uint8_t) ((x) / (50)) ) +#define CANDB_HVC_eCompActSpeed_Val_ro_fromS(x) ( ((x) * (50)) ) + +// Value tables for @HVC_eComp_Stat signal + +#ifndef HVC_eComp_Stat_HVC_CCU_Status_Msg_HVC_FailueSNA +#define HVC_eComp_Stat_HVC_CCU_Status_Msg_HVC_FailueSNA (4) +#endif + +#ifndef HVC_eComp_Stat_HVC_CCU_Status_Msg_HVC_init +#define HVC_eComp_Stat_HVC_CCU_Status_Msg_HVC_init (3) +#endif + +#ifndef HVC_eComp_Stat_HVC_CCU_Status_Msg_HVC_off +#define HVC_eComp_Stat_HVC_CCU_Status_Msg_HVC_off (2) +#endif + +#ifndef HVC_eComp_Stat_HVC_CCU_Status_Msg_HVC_on +#define HVC_eComp_Stat_HVC_CCU_Status_Msg_HVC_on (1) +#endif + +#ifndef HVC_eComp_Stat_HVC_CCU_Status_Msg_HVC_standby +#define HVC_eComp_Stat_HVC_CCU_Status_Msg_HVC_standby (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Compressor speed: + // 0xFF = Fault + uint8_t HVC_eCompActSpeed_Val_ro; // Bits= 8 Factor= 50 Unit:'rpm' + +#ifdef CANDB_USE_SIGFLOAT + uint16_t HVC_eCompActSpeed_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Compressor status: + // 0x0 = HVC standby + // 0x1 = Compressor ON / LIMIT/ Pre-heating + // 0x2 = Compressor OFF + // 0x3 = Init + // 0x4 = Failure/SNA + // 4 : "HVC Failue/SNA" + // 3 : "HVC init" + // 2 : "HVC off" + // 1 : "HVC on" + // 0 : "HVC standby" + uint8_t HVC_eComp_Stat : 3; // Bits= 3 + + // Rolling Counter [0 - 15] + uint8_t HVC_CCU_Status_RC : 4; // Bits= 4 + + // Checksum XOR8 of the data field this message + // Checksum computed as per XOR algorithm: + // Byte 1 XOR byte 2 .... XOR byte n-1. (n = packet length.) + uint8_t HVC_CCU_Status_CS; // Bits= 8 + +#else + + // Compressor speed: + // 0xFF = Fault + uint8_t HVC_eCompActSpeed_Val_ro; // Bits= 8 Factor= 50 Unit:'rpm' + +#ifdef CANDB_USE_SIGFLOAT + uint16_t HVC_eCompActSpeed_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Compressor status: + // 0x0 = HVC standby + // 0x1 = Compressor ON / LIMIT/ Pre-heating + // 0x2 = Compressor OFF + // 0x3 = Init + // 0x4 = Failure/SNA + // 4 : "HVC Failue/SNA" + // 3 : "HVC init" + // 2 : "HVC off" + // 1 : "HVC on" + // 0 : "HVC standby" + uint8_t HVC_eComp_Stat; // Bits= 3 + + // Rolling Counter [0 - 15] + uint8_t HVC_CCU_Status_RC; // Bits= 4 + + // Checksum XOR8 of the data field this message + // Checksum computed as per XOR algorithm: + // Byte 1 XOR byte 2 .... XOR byte n-1. (n = packet length.) + uint8_t HVC_CCU_Status_CS; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} HVC_CCU_Status_Msg_t; + +// def @ATS_Status CAN Message (631 0x277) +#define ATS_Status_IDE (0U) +#define ATS_Status_DLC (3U) +#define ATS_Status_CANID (0x277U) +#define ATS_Status_CYC (100U) + +// Value tables for @ATS_Err_Stat signal + +#ifndef ATS_Err_Stat_ATS_Status_Error +#define ATS_Err_Stat_ATS_Status_Error (1) +#endif + +#ifndef ATS_Err_Stat_ATS_Status_No_error +#define ATS_Err_Stat_ATS_Status_No_error (0) +#endif + + +// Value tables for @ATS_AutoHoldBtn_Stat signal + +#ifndef ATS_AutoHoldBtn_Stat_ATS_Status_Error +#define ATS_AutoHoldBtn_Stat_ATS_Status_Error (3) +#endif + +#ifndef ATS_AutoHoldBtn_Stat_ATS_Status_Spare +#define ATS_AutoHoldBtn_Stat_ATS_Status_Spare (2) +#endif + +#ifndef ATS_AutoHoldBtn_Stat_ATS_Status_Pressed +#define ATS_AutoHoldBtn_Stat_ATS_Status_Pressed (1) +#endif + +#ifndef ATS_AutoHoldBtn_Stat_ATS_Status_Not_pressed +#define ATS_AutoHoldBtn_Stat_ATS_Status_Not_pressed (0) +#endif + + +// Value tables for @ATS_EPBBtn_Req signal + +#ifndef ATS_EPBBtn_Req_ATS_Status_Error +#define ATS_EPBBtn_Req_ATS_Status_Error (3) +#endif + +#ifndef ATS_EPBBtn_Req_ATS_Status_Parking_brake_request +#define ATS_EPBBtn_Req_ATS_Status_Parking_brake_request (2) +#endif + +#ifndef ATS_EPBBtn_Req_ATS_Status_Parking_brake_release +#define ATS_EPBBtn_Req_ATS_Status_Parking_brake_release (1) +#endif + +#ifndef ATS_EPBBtn_Req_ATS_Status_Not_pressed +#define ATS_EPBBtn_Req_ATS_Status_Not_pressed (0) +#endif + + +// Value tables for @ATS_GearModeBtn_Req signal + +#ifndef ATS_GearModeBtn_Req_ATS_Status_Error +#define ATS_GearModeBtn_Req_ATS_Status_Error (7) +#endif + +#ifndef ATS_GearModeBtn_Req_ATS_Status_Spare +#define ATS_GearModeBtn_Req_ATS_Status_Spare (6) +#endif + +#ifndef ATS_GearModeBtn_Req_ATS_Status_Spare +#define ATS_GearModeBtn_Req_ATS_Status_Spare (5) +#endif + +#ifndef ATS_GearModeBtn_Req_ATS_Status_Drive_mode_request +#define ATS_GearModeBtn_Req_ATS_Status_Drive_mode_request (4) +#endif + +#ifndef ATS_GearModeBtn_Req_ATS_Status_Neutral_mode_request +#define ATS_GearModeBtn_Req_ATS_Status_Neutral_mode_request (3) +#endif + +#ifndef ATS_GearModeBtn_Req_ATS_Status_Reverse_mode_request +#define ATS_GearModeBtn_Req_ATS_Status_Reverse_mode_request (2) +#endif + +#ifndef ATS_GearModeBtn_Req_ATS_Status_Parking_mode_request +#define ATS_GearModeBtn_Req_ATS_Status_Parking_mode_request (1) +#endif + +#ifndef ATS_GearModeBtn_Req_ATS_Status_Not_pressed +#define ATS_GearModeBtn_Req_ATS_Status_Not_pressed (0) +#endif + + +// Value tables for @ATS_DriveModeBtn_Stat signal + +#ifndef ATS_DriveModeBtn_Stat_ATS_Status_Error +#define ATS_DriveModeBtn_Stat_ATS_Status_Error (3) +#endif + +#ifndef ATS_DriveModeBtn_Stat_ATS_Status_Pressed_Right_switch +#define ATS_DriveModeBtn_Stat_ATS_Status_Pressed_Right_switch (2) +#endif + +#ifndef ATS_DriveModeBtn_Stat_ATS_Status_Pressed_Left_switch +#define ATS_DriveModeBtn_Stat_ATS_Status_Pressed_Left_switch (1) +#endif + +#ifndef ATS_DriveModeBtn_Stat_ATS_Status_Not_pressed +#define ATS_DriveModeBtn_Stat_ATS_Status_Not_pressed (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Status error signal for ATS + // 1 : "Error" + // 0 : "No error" + uint8_t ATS_Err_Stat : 1; // Bits= 1 + + // Auto hold button status + // 3 : "Error" + // 2 : "Spare" + // 1 : "Pressed" + // 0 : "Not pressed" + uint8_t ATS_AutoHoldBtn_Stat : 2; // Bits= 2 + + // EPB manipulation button request + // 3 : "Error" + // 2 : "Parking brake request" + // 1 : "Parking brake release" + // 0 : "Not pressed" + uint8_t ATS_EPBBtn_Req : 2; // Bits= 2 + + // Gear mode change button request + // 7 : "Error" + // 6 : "Spare" + // 5 : "Spare" + // 4 : "Drive mode request" + // 3 : "Neutral mode request" + // 2 : "Reverse mode request" + // 1 : "Parking mode request" + // 0 : "Not pressed" + uint8_t ATS_GearModeBtn_Req : 3; // Bits= 3 + + // Rolling Counter [0 - 15] + uint8_t ATS_Status_RC : 4; // Bits= 4 + + // Drive mode change request from button + // 3 : "Error" + // 2 : "Pressed Right switch" + // 1 : "Pressed Left switch" + // 0 : "Not pressed" + uint8_t ATS_DriveModeBtn_Stat : 2; // Bits= 2 + + // Checksum XOR8 of the data field this message + // Checksum computed as per XOR algorithm: + // Byte 1 XOR byte 2 .... XOR byte n-1. (n = packet length.) + uint8_t ATS_Status_CS; // Bits= 8 + +#else + + // Status error signal for ATS + // 1 : "Error" + // 0 : "No error" + uint8_t ATS_Err_Stat; // Bits= 1 + + // Auto hold button status + // 3 : "Error" + // 2 : "Spare" + // 1 : "Pressed" + // 0 : "Not pressed" + uint8_t ATS_AutoHoldBtn_Stat; // Bits= 2 + + // EPB manipulation button request + // 3 : "Error" + // 2 : "Parking brake request" + // 1 : "Parking brake release" + // 0 : "Not pressed" + uint8_t ATS_EPBBtn_Req; // Bits= 2 + + // Gear mode change button request + // 7 : "Error" + // 6 : "Spare" + // 5 : "Spare" + // 4 : "Drive mode request" + // 3 : "Neutral mode request" + // 2 : "Reverse mode request" + // 1 : "Parking mode request" + // 0 : "Not pressed" + uint8_t ATS_GearModeBtn_Req; // Bits= 3 + + // Rolling Counter [0 - 15] + uint8_t ATS_Status_RC; // Bits= 4 + + // Drive mode change request from button + // 3 : "Error" + // 2 : "Pressed Right switch" + // 1 : "Pressed Left switch" + // 0 : "Not pressed" + uint8_t ATS_DriveModeBtn_Stat; // Bits= 2 + + // Checksum XOR8 of the data field this message + // Checksum computed as per XOR algorithm: + // Byte 1 XOR byte 2 .... XOR byte n-1. (n = packet length.) + uint8_t ATS_Status_CS; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} ATS_Status_t; + +// def @BCM_VEH_STATE CAN Message (640 0x280) +#define BCM_VEH_STATE_IDE (0U) +#define BCM_VEH_STATE_DLC (8U) +#define BCM_VEH_STATE_CANID (0x280U) +#define BCM_VEH_STATE_CYC (50U) + +// Value tables for @BCM_T15_Stat signal + +#ifndef BCM_T15_Stat_BCM_VEH_STATE_Terminal_active +#define BCM_T15_Stat_BCM_VEH_STATE_Terminal_active (1) +#endif + +#ifndef BCM_T15_Stat_BCM_VEH_STATE_Terminal_inactive +#define BCM_T15_Stat_BCM_VEH_STATE_Terminal_inactive (0) +#endif + + +// Value tables for @BCM_T30d_Stat signal + +#ifndef BCM_T30d_Stat_BCM_VEH_STATE_Terminal_active +#define BCM_T30d_Stat_BCM_VEH_STATE_Terminal_active (1) +#endif + +#ifndef BCM_T30d_Stat_BCM_VEH_STATE_Terminal_inactive +#define BCM_T30d_Stat_BCM_VEH_STATE_Terminal_inactive (0) +#endif + + +// Value tables for @BCM_T30i_Stat signal + +#ifndef BCM_T30i_Stat_BCM_VEH_STATE_Terminal_active +#define BCM_T30i_Stat_BCM_VEH_STATE_Terminal_active (1) +#endif + +#ifndef BCM_T30i_Stat_BCM_VEH_STATE_Terminal_inactive +#define BCM_T30i_Stat_BCM_VEH_STATE_Terminal_inactive (0) +#endif + + +// Value tables for @BCM_T15h_Stat signal + +#ifndef BCM_T15h_Stat_BCM_VEH_STATE_Terminal_active +#define BCM_T15h_Stat_BCM_VEH_STATE_Terminal_active (1) +#endif + +#ifndef BCM_T15h_Stat_BCM_VEH_STATE_Terminal_inactive +#define BCM_T15h_Stat_BCM_VEH_STATE_Terminal_inactive (0) +#endif + + +// Value tables for @BCM_SPV_Feature_Stat signal + +#ifndef BCM_SPV_Feature_Stat_BCM_VEH_STATE_SPV_vehicle_type +#define BCM_SPV_Feature_Stat_BCM_VEH_STATE_SPV_vehicle_type (1) +#endif + +#ifndef BCM_SPV_Feature_Stat_BCM_VEH_STATE_Commercial_vehicle_type +#define BCM_SPV_Feature_Stat_BCM_VEH_STATE_Commercial_vehicle_type (0) +#endif + + +// Value tables for @StealthModeEn signal + +#ifndef StealthModeEn_BCM_VEH_STATE_Stealth_Mode_enable +#define StealthModeEn_BCM_VEH_STATE_Stealth_Mode_enable (1) +#endif + +#ifndef StealthModeEn_BCM_VEH_STATE_Stealth_Mode_disable +#define StealthModeEn_BCM_VEH_STATE_Stealth_Mode_disable (0) +#endif + + +// Value tables for @BCM_VehicleType_Stat signal + +#ifndef BCM_VehicleType_Stat_BCM_VEH_STATE_Armored +#define BCM_VehicleType_Stat_BCM_VEH_STATE_Armored (1) +#endif + +#ifndef BCM_VehicleType_Stat_BCM_VEH_STATE_Normal +#define BCM_VehicleType_Stat_BCM_VEH_STATE_Normal (0) +#endif + + +// Value tables for @BCM_VehicleBody_Stat signal + +#ifndef BCM_VehicleBody_Stat_BCM_VEH_STATE_Sedan_long +#define BCM_VehicleBody_Stat_BCM_VEH_STATE_Sedan_long (6) +#endif + +#ifndef BCM_VehicleBody_Stat_BCM_VEH_STATE_Cabrio +#define BCM_VehicleBody_Stat_BCM_VEH_STATE_Cabrio (5) +#endif + +#ifndef BCM_VehicleBody_Stat_BCM_VEH_STATE_SUV +#define BCM_VehicleBody_Stat_BCM_VEH_STATE_SUV (4) +#endif + +#ifndef BCM_VehicleBody_Stat_BCM_VEH_STATE_MPV +#define BCM_VehicleBody_Stat_BCM_VEH_STATE_MPV (3) +#endif + +#ifndef BCM_VehicleBody_Stat_BCM_VEH_STATE_Limo +#define BCM_VehicleBody_Stat_BCM_VEH_STATE_Limo (2) +#endif + +#ifndef BCM_VehicleBody_Stat_BCM_VEH_STATE_Sedan +#define BCM_VehicleBody_Stat_BCM_VEH_STATE_Sedan (1) +#endif + +#ifndef BCM_VehicleBody_Stat_BCM_VEH_STATE_Not_set +#define BCM_VehicleBody_Stat_BCM_VEH_STATE_Not_set (0) +#endif + + +// Value tables for @BCM_ADASTerm_Stat signal + +#ifndef BCM_ADASTerm_Stat_BCM_VEH_STATE_Terminal_on +#define BCM_ADASTerm_Stat_BCM_VEH_STATE_Terminal_on (1) +#endif + +#ifndef BCM_ADASTerm_Stat_BCM_VEH_STATE_Terminal_off +#define BCM_ADASTerm_Stat_BCM_VEH_STATE_Terminal_off (0) +#endif + + +// Value tables for @BCM_CCTerm_Stat signal + +#ifndef BCM_CCTerm_Stat_BCM_VEH_STATE_Terminal_on +#define BCM_CCTerm_Stat_BCM_VEH_STATE_Terminal_on (1) +#endif + +#ifndef BCM_CCTerm_Stat_BCM_VEH_STATE_Terminal_off +#define BCM_CCTerm_Stat_BCM_VEH_STATE_Terminal_off (0) +#endif + + +// Value tables for @BCM_T30i_DisableWarning signal + +#ifndef BCM_T30i_DisableWarning_BCM_VEH_STATE_Warning_Active +#define BCM_T30i_DisableWarning_BCM_VEH_STATE_Warning_Active (1) +#endif + +#ifndef BCM_T30i_DisableWarning_BCM_VEH_STATE_No_Warning +#define BCM_T30i_DisableWarning_BCM_VEH_STATE_No_Warning (0) +#endif + + +// Value tables for @BCM_LightBCM_Stat signal + +#ifndef BCM_LightBCM_Stat_BCM_VEH_STATE_Terminal_on +#define BCM_LightBCM_Stat_BCM_VEH_STATE_Terminal_on (1) +#endif + +#ifndef BCM_LightBCM_Stat_BCM_VEH_STATE_Terminal_off +#define BCM_LightBCM_Stat_BCM_VEH_STATE_Terminal_off (0) +#endif + + +// Value tables for @HUD_IntensityRequest signal + +#ifndef HUD_IntensityRequest_BCM_VEH_STATE_Fault +#define HUD_IntensityRequest_BCM_VEH_STATE_Fault (255) +#endif + + +// Value tables for @BCM_T30d_DisableWarning signal + +#ifndef BCM_T30d_DisableWarning_BCM_VEH_STATE_Warning_Active +#define BCM_T30d_DisableWarning_BCM_VEH_STATE_Warning_Active (1) +#endif + +#ifndef BCM_T30d_DisableWarning_BCM_VEH_STATE_No_Warning +#define BCM_T30d_DisableWarning_BCM_VEH_STATE_No_Warning (0) +#endif + + +// Value tables for @BCM_Light_Stat signal + +#ifndef BCM_Light_Stat_BCM_VEH_STATE_Terminal_on +#define BCM_Light_Stat_BCM_VEH_STATE_Terminal_on (1) +#endif + +#ifndef BCM_Light_Stat_BCM_VEH_STATE_Terminal_off +#define BCM_Light_Stat_BCM_VEH_STATE_Terminal_off (0) +#endif + +// signal: @BCM_IndFadingTime_Req_ro +#define CANDB_BCM_IndFadingTime_Req_ro_CovFactor (0.1) +#define CANDB_BCM_IndFadingTime_Req_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_BCM_IndFadingTime_Req_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +// Value tables for @BCM_CCTermDisableWarning signal + +#ifndef BCM_CCTermDisableWarning_BCM_VEH_STATE_Warning_Active +#define BCM_CCTermDisableWarning_BCM_VEH_STATE_Warning_Active (1) +#endif + +#ifndef BCM_CCTermDisableWarning_BCM_VEH_STATE_No_Warning +#define BCM_CCTermDisableWarning_BCM_VEH_STATE_No_Warning (0) +#endif + + +// Value tables for @BCM_PreheatFunction_Stat signal + +#ifndef BCM_PreheatFunction_Stat_BCM_VEH_STATE_Preheating_Fault +#define BCM_PreheatFunction_Stat_BCM_VEH_STATE_Preheating_Fault (3) +#endif + +#ifndef BCM_PreheatFunction_Stat_BCM_VEH_STATE_Preheating_Active +#define BCM_PreheatFunction_Stat_BCM_VEH_STATE_Preheating_Active (2) +#endif + +#ifndef BCM_PreheatFunction_Stat_BCM_VEH_STATE_Preheatng_In_progress_Additional_Heating +#define BCM_PreheatFunction_Stat_BCM_VEH_STATE_Preheatng_In_progress_Additional_Heating (1) +#endif + +#ifndef BCM_PreheatFunction_Stat_BCM_VEH_STATE_Preheating_Inactive +#define BCM_PreheatFunction_Stat_BCM_VEH_STATE_Preheating_Inactive (0) +#endif + + +// Value tables for @BCM_VehiclePowertrain_Stat signal + +#ifndef BCM_VehiclePowertrain_Stat_BCM_VEH_STATE_PFCV +#define BCM_VehiclePowertrain_Stat_BCM_VEH_STATE_PFCV (3) +#endif + +#ifndef BCM_VehiclePowertrain_Stat_BCM_VEH_STATE_PHEV +#define BCM_VehiclePowertrain_Stat_BCM_VEH_STATE_PHEV (2) +#endif + +#ifndef BCM_VehiclePowertrain_Stat_BCM_VEH_STATE_BEV +#define BCM_VehiclePowertrain_Stat_BCM_VEH_STATE_BEV (1) +#endif + +#ifndef BCM_VehiclePowertrain_Stat_BCM_VEH_STATE_HEV_default +#define BCM_VehiclePowertrain_Stat_BCM_VEH_STATE_HEV_default (0) +#endif + +// signal: @BCM_SwBackIntens_Val_ro +#define CANDB_BCM_SwBackIntens_Val_ro_CovFactor (0.394) +#define CANDB_BCM_SwBackIntens_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.394)) ) +#define CANDB_BCM_SwBackIntens_Val_ro_fromS(x) ( (((x) * (0.394)) + (0.0)) ) + +// Value tables for @BCM_VehicleMode_Stat signal + +#ifndef BCM_VehicleMode_Stat_BCM_VEH_STATE_RemoteStart_Mode +#define BCM_VehicleMode_Stat_BCM_VEH_STATE_RemoteStart_Mode (6) +#endif + +#ifndef BCM_VehicleMode_Stat_BCM_VEH_STATE_Service_Mode +#define BCM_VehicleMode_Stat_BCM_VEH_STATE_Service_Mode (5) +#endif + +#ifndef BCM_VehicleMode_Stat_BCM_VEH_STATE_Drive_Mode +#define BCM_VehicleMode_Stat_BCM_VEH_STATE_Drive_Mode (4) +#endif + +#ifndef BCM_VehicleMode_Stat_BCM_VEH_STATE_Ignition_Mode +#define BCM_VehicleMode_Stat_BCM_VEH_STATE_Ignition_Mode (3) +#endif + +#ifndef BCM_VehicleMode_Stat_BCM_VEH_STATE_StandBy_Mode +#define BCM_VehicleMode_Stat_BCM_VEH_STATE_StandBy_Mode (2) +#endif + +#ifndef BCM_VehicleMode_Stat_BCM_VEH_STATE_PreHeating_Mode +#define BCM_VehicleMode_Stat_BCM_VEH_STATE_PreHeating_Mode (1) +#endif + +#ifndef BCM_VehicleMode_Stat_BCM_VEH_STATE_Sleep_Mode +#define BCM_VehicleMode_Stat_BCM_VEH_STATE_Sleep_Mode (0) +#endif + + +// Value tables for @BCM_SwIndIntens_Stat signal + +#ifndef BCM_SwIndIntens_Stat_BCM_VEH_STATE_Low_level +#define BCM_SwIndIntens_Stat_BCM_VEH_STATE_Low_level (1) +#endif + +#ifndef BCM_SwIndIntens_Stat_BCM_VEH_STATE_Hight_level +#define BCM_SwIndIntens_Stat_BCM_VEH_STATE_Hight_level (0) +#endif + + +// Value tables for @BCM_Vehicle_DrvMode signal + +#ifndef BCM_Vehicle_DrvMode_BCM_VEH_STATE_Electric +#define BCM_Vehicle_DrvMode_BCM_VEH_STATE_Electric (6) +#endif + +#ifndef BCM_Vehicle_DrvMode_BCM_VEH_STATE_Reserved +#define BCM_Vehicle_DrvMode_BCM_VEH_STATE_Reserved (5) +#endif + +#ifndef BCM_Vehicle_DrvMode_BCM_VEH_STATE_Offroad +#define BCM_Vehicle_DrvMode_BCM_VEH_STATE_Offroad (4) +#endif + +#ifndef BCM_Vehicle_DrvMode_BCM_VEH_STATE_Reserved +#define BCM_Vehicle_DrvMode_BCM_VEH_STATE_Reserved (3) +#endif + +#ifndef BCM_Vehicle_DrvMode_BCM_VEH_STATE_Range +#define BCM_Vehicle_DrvMode_BCM_VEH_STATE_Range (2) +#endif + +#ifndef BCM_Vehicle_DrvMode_BCM_VEH_STATE_Dynamic +#define BCM_Vehicle_DrvMode_BCM_VEH_STATE_Dynamic (1) +#endif + +#ifndef BCM_Vehicle_DrvMode_BCM_VEH_STATE_Comfort +#define BCM_Vehicle_DrvMode_BCM_VEH_STATE_Comfort (0) +#endif + +#ifndef BCM_Vehicle_DrvMode_BCM_VEH_STATE_Charge +#define BCM_Vehicle_DrvMode_BCM_VEH_STATE_Charge (7) +#endif + +// signal: @BCM_LVBatteryVoltage_ro +#define CANDB_BCM_LVBatteryVoltage_ro_CovFactor (0.075) +#define CANDB_BCM_LVBatteryVoltage_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.075)) ) +#define CANDB_BCM_LVBatteryVoltage_ro_fromS(x) ( (((x) * (0.075)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Terminal T15 state + // 1 : "Terminal active" + // 0 : "Terminal inactive" + uint8_t BCM_T15_Stat : 1; // Bits= 1 + + // State of T30d terminal + // 1 : "Terminal active" + // 0 : "Terminal inactive" + uint8_t BCM_T30d_Stat : 1; // Bits= 1 + + // State of T30i terminal + // 1 : "Terminal active" + // 0 : "Terminal inactive" + uint8_t BCM_T30i_Stat : 1; // Bits= 1 + + // Terminal 15h status + // 1 : "Terminal active" + // 0 : "Terminal inactive" + uint8_t BCM_T15h_Stat : 1; // Bits= 1 + + // The flag, which provide an information about vehicle type. + // Default value - 0x0 uses for commercial vehilces, + // 0x1 - SPV (Special purpose vehilces) type uses for GON vehicles + // 1 : "SPV vehicle type" + // 0 : "Commercial vehicle type" + uint8_t BCM_SPV_Feature_Stat : 1; // Bits= 1 + + // Indicates that the Stealth mode is required: + // $0 = Stealth mode disable + // $1 = Stealth mode enable + // 1 : "Stealth Mode enable" + // 0 : "Stealth Mode disable" + uint8_t StealthModeEn : 1; // Bits= 1 + + // Type of vehicle: armoured or not + // 1 : "Armored" + // 0 : "Normal" + uint8_t BCM_VehicleType_Stat : 1; // Bits= 1 + + // Vehicle's body type (sedan, limousine, etc.) + // 6 : "Sedan long" + // 5 : "Cabrio" + // 4 : "SUV" + // 3 : "MPV" + // 2 : "Limo" + // 1 : "Sedan" + // 0 : "Not set" + uint8_t BCM_VehicleBody_Stat : 4; // Bits= 4 + + // Terminal to power ADASCAN + // 1 : "Terminal on" + // 0 : "Terminal off" + uint8_t BCM_ADASTerm_Stat : 1; // Bits= 1 + + // Terminal to power climate system + // 1 : "Terminal on" + // 0 : "Terminal off" + uint8_t BCM_CCTerm_Stat : 1; // Bits= 1 + + // $0 = No Warning + // $1 = Warning Active + // 1 : "Warning Active" + // 0 : "No Warning" + uint8_t BCM_T30i_DisableWarning : 1; // Bits= 1 + + // Terminal to power all internal plafonds + // 1 : "Terminal on" + // 0 : "Terminal off" + uint8_t BCM_LightBCM_Stat : 1; // Bits= 1 + + // Head-up display intensity value from RLS + // 255 : "Fault" + uint8_t HUD_IntensityRequest; // Bits= 8 + + // T30d terminal warning status signal + // 3 sec before T30d off + // 1 : "Warning Active" + // 0 : "No Warning" + uint8_t BCM_T30d_DisableWarning : 1; // Bits= 1 + + // Terminal to power individual light sections + // 1 : "Terminal on" + // 0 : "Terminal off" + uint8_t BCM_Light_Stat : 1; // Bits= 1 + + // The timer for smoothly change switches intensity, when day detected. + uint8_t BCM_IndFadingTime_Req_ro : 5; // Bits= 5 Factor= 0.1 Unit:'s' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_IndFadingTime_Req_phys; +#endif // CANDB_USE_SIGFLOAT + + // Indicates if CC terminal will be disconnected soon + // 1 : "Warning Active" + // 0 : "No Warning" + uint8_t BCM_CCTermDisableWarning : 1; // Bits= 1 + + // Status of Preheating function: + // 0x1 � If BCM_T15_Stat = 0x0 than Preheating Inprogress, ready to Preheating phase + // 0x1 - If BCM_T15_Stat = 0x1 than Additional Heating Active + // 3 : "Preheating Fault" + // 2 : "Preheating Active" + // 1 : "Preheatng In progress/ Additional Heating" + // 0 : "Preheating Inactive" + uint8_t BCM_PreheatFunction_Stat : 2; // Bits= 2 + + // Type of vehicle powertrain + // 3 : "PFCV" + // 2 : "PHEV" + // 1 : "BEV" + // 0 : "HEV (default)" + uint8_t BCM_VehiclePowertrain_Stat : 2; // Bits= 2 + + // Background illumination level of switches + uint8_t BCM_SwBackIntens_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_SwBackIntens_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Current vehicle state according Terminal concept + // 6 : "RemoteStart_Mode" + // 5 : "Service_Mode" + // 4 : "Drive_Mode" + // 3 : "Ignition_Mode" + // 2 : "StandBy_Mode" + // 1 : "PreHeating_Mode" + // 0 : "Sleep_Mode" + uint8_t BCM_VehicleMode_Stat : 4; // Bits= 4 + + // Switches indicator intensity level + // 1 : "Low level" + // 0 : "Hight level" + uint8_t BCM_SwIndIntens_Stat : 1; // Bits= 1 + + // Vehicle drive mode, set by user + // 6 : "Electric" + // 5 : "Reserved" + // 4 : "Offroad" + // 3 : "Reserved" + // 2 : "Range" + // 1 : "Dynamic" + // 0 : "Comfort" + // 7 : "Charge" + uint8_t BCM_Vehicle_DrvMode : 3; // Bits= 3 + + // Indicates the battery voltage. Measurement from the Battery sensor + uint8_t BCM_LVBatteryVoltage_ro; // Bits= 8 Factor= 0.075 Unit:'V' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_LVBatteryVoltage_phys; +#endif // CANDB_USE_SIGFLOAT + +#else + + // Terminal T15 state + // 1 : "Terminal active" + // 0 : "Terminal inactive" + uint8_t BCM_T15_Stat; // Bits= 1 + + // State of T30d terminal + // 1 : "Terminal active" + // 0 : "Terminal inactive" + uint8_t BCM_T30d_Stat; // Bits= 1 + + // State of T30i terminal + // 1 : "Terminal active" + // 0 : "Terminal inactive" + uint8_t BCM_T30i_Stat; // Bits= 1 + + // Terminal 15h status + // 1 : "Terminal active" + // 0 : "Terminal inactive" + uint8_t BCM_T15h_Stat; // Bits= 1 + + // The flag, which provide an information about vehicle type. + // Default value - 0x0 uses for commercial vehilces, + // 0x1 - SPV (Special purpose vehilces) type uses for GON vehicles + // 1 : "SPV vehicle type" + // 0 : "Commercial vehicle type" + uint8_t BCM_SPV_Feature_Stat; // Bits= 1 + + // Indicates that the Stealth mode is required: + // $0 = Stealth mode disable + // $1 = Stealth mode enable + // 1 : "Stealth Mode enable" + // 0 : "Stealth Mode disable" + uint8_t StealthModeEn; // Bits= 1 + + // Type of vehicle: armoured or not + // 1 : "Armored" + // 0 : "Normal" + uint8_t BCM_VehicleType_Stat; // Bits= 1 + + // Vehicle's body type (sedan, limousine, etc.) + // 6 : "Sedan long" + // 5 : "Cabrio" + // 4 : "SUV" + // 3 : "MPV" + // 2 : "Limo" + // 1 : "Sedan" + // 0 : "Not set" + uint8_t BCM_VehicleBody_Stat; // Bits= 4 + + // Terminal to power ADASCAN + // 1 : "Terminal on" + // 0 : "Terminal off" + uint8_t BCM_ADASTerm_Stat; // Bits= 1 + + // Terminal to power climate system + // 1 : "Terminal on" + // 0 : "Terminal off" + uint8_t BCM_CCTerm_Stat; // Bits= 1 + + // $0 = No Warning + // $1 = Warning Active + // 1 : "Warning Active" + // 0 : "No Warning" + uint8_t BCM_T30i_DisableWarning; // Bits= 1 + + // Terminal to power all internal plafonds + // 1 : "Terminal on" + // 0 : "Terminal off" + uint8_t BCM_LightBCM_Stat; // Bits= 1 + + // Head-up display intensity value from RLS + // 255 : "Fault" + uint8_t HUD_IntensityRequest; // Bits= 8 + + // T30d terminal warning status signal + // 3 sec before T30d off + // 1 : "Warning Active" + // 0 : "No Warning" + uint8_t BCM_T30d_DisableWarning; // Bits= 1 + + // Terminal to power individual light sections + // 1 : "Terminal on" + // 0 : "Terminal off" + uint8_t BCM_Light_Stat; // Bits= 1 + + // The timer for smoothly change switches intensity, when day detected. + uint8_t BCM_IndFadingTime_Req_ro; // Bits= 5 Factor= 0.1 Unit:'s' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_IndFadingTime_Req_phys; +#endif // CANDB_USE_SIGFLOAT + + // Indicates if CC terminal will be disconnected soon + // 1 : "Warning Active" + // 0 : "No Warning" + uint8_t BCM_CCTermDisableWarning; // Bits= 1 + + // Status of Preheating function: + // 0x1 � If BCM_T15_Stat = 0x0 than Preheating Inprogress, ready to Preheating phase + // 0x1 - If BCM_T15_Stat = 0x1 than Additional Heating Active + // 3 : "Preheating Fault" + // 2 : "Preheating Active" + // 1 : "Preheatng In progress/ Additional Heating" + // 0 : "Preheating Inactive" + uint8_t BCM_PreheatFunction_Stat; // Bits= 2 + + // Type of vehicle powertrain + // 3 : "PFCV" + // 2 : "PHEV" + // 1 : "BEV" + // 0 : "HEV (default)" + uint8_t BCM_VehiclePowertrain_Stat; // Bits= 2 + + // Background illumination level of switches + uint8_t BCM_SwBackIntens_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_SwBackIntens_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Current vehicle state according Terminal concept + // 6 : "RemoteStart_Mode" + // 5 : "Service_Mode" + // 4 : "Drive_Mode" + // 3 : "Ignition_Mode" + // 2 : "StandBy_Mode" + // 1 : "PreHeating_Mode" + // 0 : "Sleep_Mode" + uint8_t BCM_VehicleMode_Stat; // Bits= 4 + + // Switches indicator intensity level + // 1 : "Low level" + // 0 : "Hight level" + uint8_t BCM_SwIndIntens_Stat; // Bits= 1 + + // Vehicle drive mode, set by user + // 6 : "Electric" + // 5 : "Reserved" + // 4 : "Offroad" + // 3 : "Reserved" + // 2 : "Range" + // 1 : "Dynamic" + // 0 : "Comfort" + // 7 : "Charge" + uint8_t BCM_Vehicle_DrvMode; // Bits= 3 + + // Indicates the battery voltage. Measurement from the Battery sensor + uint8_t BCM_LVBatteryVoltage_ro; // Bits= 8 Factor= 0.075 Unit:'V' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_LVBatteryVoltage_phys; +#endif // CANDB_USE_SIGFLOAT + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} BCM_VEH_STATE_t; + +// def @BCM_Veh_State2 CAN Message (642 0x282) +#define BCM_Veh_State2_IDE (0U) +#define BCM_Veh_State2_DLC (6U) +#define BCM_Veh_State2_CANID (0x282U) +#define BCM_Veh_State2_CYC (100U) + +// Value tables for @BCM_MAS_Activation_Req signal + +#ifndef BCM_MAS_Activation_Req_BCM_Veh_State2_Switch_requested_long_press +#define BCM_MAS_Activation_Req_BCM_Veh_State2_Switch_requested_long_press (2) +#endif + +#ifndef BCM_MAS_Activation_Req_BCM_Veh_State2_Switch_requested_short_press +#define BCM_MAS_Activation_Req_BCM_Veh_State2_Switch_requested_short_press (1) +#endif + +#ifndef BCM_MAS_Activation_Req_BCM_Veh_State2_Not_requested +#define BCM_MAS_Activation_Req_BCM_Veh_State2_Not_requested (0) +#endif + + +// Value tables for @BCM_HeadUpDispSw_Stat signal + +#ifndef BCM_HeadUpDispSw_Stat_BCM_Veh_State2_Switch_requested +#define BCM_HeadUpDispSw_Stat_BCM_Veh_State2_Switch_requested (1) +#endif + +#ifndef BCM_HeadUpDispSw_Stat_BCM_Veh_State2_Not_requested +#define BCM_HeadUpDispSw_Stat_BCM_Veh_State2_Not_requested (0) +#endif + + +// Value tables for @BCM_FootrestRL_Stat signal + +#ifndef BCM_FootrestRL_Stat_BCM_Veh_State2_Error +#define BCM_FootrestRL_Stat_BCM_Veh_State2_Error (3) +#endif + +#ifndef BCM_FootrestRL_Stat_BCM_Veh_State2_Open_Unfolded +#define BCM_FootrestRL_Stat_BCM_Veh_State2_Open_Unfolded (2) +#endif + +#ifndef BCM_FootrestRL_Stat_BCM_Veh_State2_Intermediate +#define BCM_FootrestRL_Stat_BCM_Veh_State2_Intermediate (1) +#endif + +#ifndef BCM_FootrestRL_Stat_BCM_Veh_State2_Close_Folded +#define BCM_FootrestRL_Stat_BCM_Veh_State2_Close_Folded (0) +#endif + + +// Value tables for @BCM_FootrestRR_Stat signal + +#ifndef BCM_FootrestRR_Stat_BCM_Veh_State2_Error +#define BCM_FootrestRR_Stat_BCM_Veh_State2_Error (3) +#endif + +#ifndef BCM_FootrestRR_Stat_BCM_Veh_State2_Open_Unfolded +#define BCM_FootrestRR_Stat_BCM_Veh_State2_Open_Unfolded (2) +#endif + +#ifndef BCM_FootrestRR_Stat_BCM_Veh_State2_Intermediate +#define BCM_FootrestRR_Stat_BCM_Veh_State2_Intermediate (1) +#endif + +#ifndef BCM_FootrestRR_Stat_BCM_Veh_State2_Close_Folded +#define BCM_FootrestRR_Stat_BCM_Veh_State2_Close_Folded (0) +#endif + + +// Value tables for @BCM_FootrestRLWarning_Stat signal + +#ifndef BCM_FootrestRLWarning_Stat_BCM_Veh_State2_Warning +#define BCM_FootrestRLWarning_Stat_BCM_Veh_State2_Warning (1) +#endif + +#ifndef BCM_FootrestRLWarning_Stat_BCM_Veh_State2_No_warning +#define BCM_FootrestRLWarning_Stat_BCM_Veh_State2_No_warning (0) +#endif + +// signal: @BCM_AmbientTempHMI_ro +#define CANDB_BCM_AmbientTempHMI_ro_CovFactor (0.5) +#define CANDB_BCM_AmbientTempHMI_ro_toS(x) ( (uint8_t) (((x) - (-50.0)) / (0.5)) ) +#define CANDB_BCM_AmbientTempHMI_ro_fromS(x) ( (((x) * (0.5)) + (-50.0)) ) + +// Value tables for @BCM_GovernmentComSw_Stat signal + +#ifndef BCM_GovernmentComSw_Stat_BCM_Veh_State2_Government_Com_Switch_Active +#define BCM_GovernmentComSw_Stat_BCM_Veh_State2_Government_Com_Switch_Active (1) +#endif + +#ifndef BCM_GovernmentComSw_Stat_BCM_Veh_State2_Government_Com_Switch_Inactive +#define BCM_GovernmentComSw_Stat_BCM_Veh_State2_Government_Com_Switch_Inactive (0) +#endif + + +// Value tables for @BCM_RearWindowHeatingLED signal + +#ifndef BCM_RearWindowHeatingLED_BCM_Veh_State2_On +#define BCM_RearWindowHeatingLED_BCM_Veh_State2_On (1) +#endif + +#ifndef BCM_RearWindowHeatingLED_BCM_Veh_State2_Off +#define BCM_RearWindowHeatingLED_BCM_Veh_State2_Off (0) +#endif + + +// Value tables for @BCM_FootrestRRWarning_Stat signal + +#ifndef BCM_FootrestRRWarning_Stat_BCM_Veh_State2_Warning +#define BCM_FootrestRRWarning_Stat_BCM_Veh_State2_Warning (1) +#endif + +#ifndef BCM_FootrestRRWarning_Stat_BCM_Veh_State2_No_warning +#define BCM_FootrestRRWarning_Stat_BCM_Veh_State2_No_warning (0) +#endif + + +// Value tables for @BCM_GovernmentHandset_Stat signal + +#ifndef BCM_GovernmentHandset_Stat_BCM_Veh_State2_Handset_Picked_Up +#define BCM_GovernmentHandset_Stat_BCM_Veh_State2_Handset_Picked_Up (1) +#endif + +#ifndef BCM_GovernmentHandset_Stat_BCM_Veh_State2_Handset_Not_Picked_Up +#define BCM_GovernmentHandset_Stat_BCM_Veh_State2_Handset_Not_Picked_Up (0) +#endif + + +// Value tables for @BCM_EasyExitSMRL_Stat signal + +#ifndef BCM_EasyExitSMRL_Stat_BCM_Veh_State2_easy_Exit_Enable +#define BCM_EasyExitSMRL_Stat_BCM_Veh_State2_easy_Exit_Enable (1) +#endif + +#ifndef BCM_EasyExitSMRL_Stat_BCM_Veh_State2_easy_Exit_Disable +#define BCM_EasyExitSMRL_Stat_BCM_Veh_State2_easy_Exit_Disable (0) +#endif + + +// Value tables for @BCM_EasyExitSMRR_Stat signal + +#ifndef BCM_EasyExitSMRR_Stat_BCM_Veh_State2_easy_Exit_Enable +#define BCM_EasyExitSMRR_Stat_BCM_Veh_State2_easy_Exit_Enable (1) +#endif + +#ifndef BCM_EasyExitSMRR_Stat_BCM_Veh_State2_easy_Exit_Disable +#define BCM_EasyExitSMRR_Stat_BCM_Veh_State2_easy_Exit_Disable (0) +#endif + + +// Value tables for @BCM_EasyExitSMFR_Stat signal + +#ifndef BCM_EasyExitSMFR_Stat_BCM_Veh_State2_easy_Exit_Enable +#define BCM_EasyExitSMFR_Stat_BCM_Veh_State2_easy_Exit_Enable (1) +#endif + +#ifndef BCM_EasyExitSMFR_Stat_BCM_Veh_State2_easy_Exit_Disable +#define BCM_EasyExitSMFR_Stat_BCM_Veh_State2_easy_Exit_Disable (0) +#endif + + +// Value tables for @BCM_EasyExitSMFL_Stat signal + +#ifndef BCM_EasyExitSMFL_Stat_BCM_Veh_State2_easy_Exit_Enable +#define BCM_EasyExitSMFL_Stat_BCM_Veh_State2_easy_Exit_Enable (1) +#endif + +#ifndef BCM_EasyExitSMFL_Stat_BCM_Veh_State2_easy_Exit_Disable +#define BCM_EasyExitSMFL_Stat_BCM_Veh_State2_easy_Exit_Disable (0) +#endif + + +// Value tables for @BCM_LccBtn_Stat signal + +#ifndef BCM_LccBtn_Stat_BCM_Veh_State2_Button_pressed +#define BCM_LccBtn_Stat_BCM_Veh_State2_Button_pressed (1) +#endif + +#ifndef BCM_LccBtn_Stat_BCM_Veh_State2_Button_not_pressed +#define BCM_LccBtn_Stat_BCM_Veh_State2_Button_not_pressed (0) +#endif + + +// Value tables for @BCM_LdwBtn_Stat signal + +#ifndef BCM_LdwBtn_Stat_BCM_Veh_State2_Button_pressed +#define BCM_LdwBtn_Stat_BCM_Veh_State2_Button_pressed (1) +#endif + +#ifndef BCM_LdwBtn_Stat_BCM_Veh_State2_Button_not_pressed +#define BCM_LdwBtn_Stat_BCM_Veh_State2_Button_not_pressed (0) +#endif + + +// Value tables for @BCM_AdasSensClear_Stat signal + +#ifndef BCM_AdasSensClear_Stat_BCM_Veh_State2_Washing_active +#define BCM_AdasSensClear_Stat_BCM_Veh_State2_Washing_active (1) +#endif + +#ifndef BCM_AdasSensClear_Stat_BCM_Veh_State2_Washing_inactive +#define BCM_AdasSensClear_Stat_BCM_Veh_State2_Washing_inactive (0) +#endif + + +// Value tables for @BCM_T15h_Deactivation_Req signal + +#ifndef BCM_T15h_Deactivation_Req_BCM_Veh_State2_Requested +#define BCM_T15h_Deactivation_Req_BCM_Veh_State2_Requested (1) +#endif + +#ifndef BCM_T15h_Deactivation_Req_BCM_Veh_State2_Not_requested +#define BCM_T15h_Deactivation_Req_BCM_Veh_State2_Not_requested (0) +#endif + + +// Value tables for @BCM_RemoteStart_Stat signal + +#ifndef BCM_RemoteStart_Stat_BCM_Veh_State2_Failure +#define BCM_RemoteStart_Stat_BCM_Veh_State2_Failure (3) +#endif + +#ifndef BCM_RemoteStart_Stat_BCM_Veh_State2_Active_Mode +#define BCM_RemoteStart_Stat_BCM_Veh_State2_Active_Mode (2) +#endif + +#ifndef BCM_RemoteStart_Stat_BCM_Veh_State2_Initialization_Mode +#define BCM_RemoteStart_Stat_BCM_Veh_State2_Initialization_Mode (1) +#endif + +#ifndef BCM_RemoteStart_Stat_BCM_Veh_State2_Inactive +#define BCM_RemoteStart_Stat_BCM_Veh_State2_Inactive (0) +#endif + + +// Value tables for @BCM_AntiTheft_Stat signal + +#ifndef BCM_AntiTheft_Stat_BCM_Veh_State2_Anti_Theft_Active_state +#define BCM_AntiTheft_Stat_BCM_Veh_State2_Anti_Theft_Active_state (1) +#endif + +#ifndef BCM_AntiTheft_Stat_BCM_Veh_State2_Anti_Theft_Inactive_state +#define BCM_AntiTheft_Stat_BCM_Veh_State2_Anti_Theft_Inactive_state (0) +#endif + + +// Value tables for @BCM_PanoramicViewLed_Cmd signal + +#ifndef BCM_PanoramicViewLed_Cmd_BCM_Veh_State2_On +#define BCM_PanoramicViewLed_Cmd_BCM_Veh_State2_On (1) +#endif + +#ifndef BCM_PanoramicViewLed_Cmd_BCM_Veh_State2_Off +#define BCM_PanoramicViewLed_Cmd_BCM_Veh_State2_Off (0) +#endif + +// signal: @BCM_ElcromeMirror_Req_ro +#define CANDB_BCM_ElcromeMirror_Req_ro_CovFactor (0.394) +#define CANDB_BCM_ElcromeMirror_Req_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.394)) ) +#define CANDB_BCM_ElcromeMirror_Req_ro_fromS(x) ( (((x) * (0.394)) + (0.0)) ) + +// Value tables for @BCM_AdasSensWSHeat_Req signal + +#ifndef BCM_AdasSensWSHeat_Req_BCM_Veh_State2_Error +#define BCM_AdasSensWSHeat_Req_BCM_Veh_State2_Error (2) +#endif + +#ifndef BCM_AdasSensWSHeat_Req_BCM_Veh_State2_On +#define BCM_AdasSensWSHeat_Req_BCM_Veh_State2_On (1) +#endif + +#ifndef BCM_AdasSensWSHeat_Req_BCM_Veh_State2_Off +#define BCM_AdasSensWSHeat_Req_BCM_Veh_State2_Off (0) +#endif + + +// Value tables for @BCM_RearWasherVlv_Req signal + +#ifndef BCM_RearWasherVlv_Req_BCM_Veh_State2_Rear_window_washer_valve_requested +#define BCM_RearWasherVlv_Req_BCM_Veh_State2_Rear_window_washer_valve_requested (1) +#endif + +#ifndef BCM_RearWasherVlv_Req_BCM_Veh_State2_Rear_window_washer_valve_not_requested +#define BCM_RearWasherVlv_Req_BCM_Veh_State2_Rear_window_washer_valve_not_requested (0) +#endif + + +// Value tables for @BCM_RoofControl_Req signal + +#ifndef BCM_RoofControl_Req_BCM_Veh_State2_No_request +#define BCM_RoofControl_Req_BCM_Veh_State2_No_request (0) +#endif + +#ifndef BCM_RoofControl_Req_BCM_Veh_State2_Open_roof_request +#define BCM_RoofControl_Req_BCM_Veh_State2_Open_roof_request (1) +#endif + +#ifndef BCM_RoofControl_Req_BCM_Veh_State2_Close_roof_request +#define BCM_RoofControl_Req_BCM_Veh_State2_Close_roof_request (2) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Parking assistent switch state + // 2 : "Switch requested long press" + // 1 : "Switch requested short press" + // 0 : "Not requested" + uint8_t BCM_MAS_Activation_Req : 2; // Bits= 2 + + // State of head-up display switch + // 1 : "Switch requested" + // 0 : "Not requested" + uint8_t BCM_HeadUpDispSw_Stat : 1; // Bits= 1 + + // Footrest RL status + // Status position footrest from BCM + // 3 : "Error" + // 2 : "Open (Unfolded)" + // 1 : "Intermediate" + // 0 : "Close (Folded)" + uint8_t BCM_FootrestRL_Stat : 2; // Bits= 2 + + // Footrest RR status + // Status position footrest from BCM + // 3 : "Error" + // 2 : "Open (Unfolded)" + // 1 : "Intermediate" + // 0 : "Close (Folded)" + uint8_t BCM_FootrestRR_Stat : 2; // Bits= 2 + + // Footrest RL warning status + // Straponten on warning on rear tablet + // 1 : "Warning" + // 0 : "No warning" + uint8_t BCM_FootrestRLWarning_Stat : 1; // Bits= 1 + + // Ambient temperature for inform an user + uint8_t BCM_AmbientTempHMI_ro; // Bits= 8 Offset= -50.0 Factor= 0.5 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_AmbientTempHMI_phys; +#endif // CANDB_USE_SIGFLOAT + + // The status of activating Switch for government communication. The InterCom System shall be deactivated after 5s, when switch active. + // 1 : "Government Com. Switch Active" + // 0 : "Government Com. Switch Inactive" + uint8_t BCM_GovernmentComSw_Stat : 1; // Bits= 1 + + // Request to on/off rear window heating control indicator + // 1 : "On" + // 0 : "Off" + uint8_t BCM_RearWindowHeatingLED : 1; // Bits= 1 + + // Footrest RR warning status + // Straponten on warning on rear tablet + // 1 : "Warning" + // 0 : "No warning" + uint8_t BCM_FootrestRRWarning_Stat : 1; // Bits= 1 + + // The status of handset for government communication, The Intercom system shall be deactivated immediatly, when handset is picked up. + // 1 : "Handset Picked Up" + // 0 : "Handset Not Picked Up" + uint8_t BCM_GovernmentHandset_Stat : 1; // Bits= 1 + + // Easy exit request to SMRL + // 1 : "easy Exit Enable" + // 0 : "easy Exit Disable" + uint8_t BCM_EasyExitSMRL_Stat : 1; // Bits= 1 + + // Easy exit request to SMRR + // 1 : "easy Exit Enable" + // 0 : "easy Exit Disable" + uint8_t BCM_EasyExitSMRR_Stat : 1; // Bits= 1 + + // Easy exit request to SMFR + // 1 : "easy Exit Enable" + // 0 : "easy Exit Disable" + uint8_t BCM_EasyExitSMFR_Stat : 1; // Bits= 1 + + // Easy exit request to SMFL + // 1 : "easy Exit Enable" + // 0 : "easy Exit Disable" + uint8_t BCM_EasyExitSMFL_Stat : 1; // Bits= 1 + + // Lane change Control button state + // 1 : "Button pressed" + // 0 : "Button not pressed" + uint8_t BCM_LccBtn_Stat : 1; // Bits= 1 + + // Lane departure warning control button state + // 1 : "Button pressed" + // 0 : "Button not pressed" + uint8_t BCM_LdwBtn_Stat : 1; // Bits= 1 + + // State of ADAS elements washing + // 1 : "Washing active" + // 0 : "Washing inactive" + uint8_t BCM_AdasSensClear_Stat : 1; // Bits= 1 + + // T15h terminal deactivation request signal from BCM. + // 1 : "Requested" + // 0 : "Not requested" + uint8_t BCM_T15h_Deactivation_Req : 1; // Bits= 1 + + // Satet of remote start process + // 3 : "Failure" + // 2 : "Active_Mode" + // 1 : "Initialization_Mode" + // 0 : "Inactive" + uint8_t BCM_RemoteStart_Stat : 2; // Bits= 2 + + // Status of activation Ani Theft system. + // 1 : "Anti Theft Active state" + // 0 : "Anti Theft Inactive state" + uint8_t BCM_AntiTheft_Stat : 1; // Bits= 1 + + // Request frrom BCM for activation LED indicator on Panoramic View Switch (CCPR) + // 1 : "On" + // 0 : "Off" + uint8_t BCM_PanoramicViewLed_Cmd : 1; // Bits= 1 + + // Request to control electrochrome of outside mirrors + uint8_t BCM_ElcromeMirror_Req_ro; // Bits= 8 Factor= 0.394 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_ElcromeMirror_Req_phys; +#endif // CANDB_USE_SIGFLOAT + + // ADAS is requesting heat on wind sheeld + // 2 : "Error" + // 1 : "On" + // 0 : "Off" + uint8_t BCM_AdasSensWSHeat_Req : 2; // Bits= 2 + + // Rear window washer valve request + // 1 : "Rear window washer valve requested" + // 0 : "Rear window washer valve not requested" + uint8_t BCM_RearWasherVlv_Req : 1; // Bits= 1 + + // Soft roof control request + // 0 : "No request" + // 1 : "Open roof request" + // 2 : "Close roof request" + uint8_t BCM_RoofControl_Req : 2; // Bits= 2 + +#else + + // Parking assistent switch state + // 2 : "Switch requested long press" + // 1 : "Switch requested short press" + // 0 : "Not requested" + uint8_t BCM_MAS_Activation_Req; // Bits= 2 + + // State of head-up display switch + // 1 : "Switch requested" + // 0 : "Not requested" + uint8_t BCM_HeadUpDispSw_Stat; // Bits= 1 + + // Footrest RL status + // Status position footrest from BCM + // 3 : "Error" + // 2 : "Open (Unfolded)" + // 1 : "Intermediate" + // 0 : "Close (Folded)" + uint8_t BCM_FootrestRL_Stat; // Bits= 2 + + // Footrest RR status + // Status position footrest from BCM + // 3 : "Error" + // 2 : "Open (Unfolded)" + // 1 : "Intermediate" + // 0 : "Close (Folded)" + uint8_t BCM_FootrestRR_Stat; // Bits= 2 + + // Footrest RL warning status + // Straponten on warning on rear tablet + // 1 : "Warning" + // 0 : "No warning" + uint8_t BCM_FootrestRLWarning_Stat; // Bits= 1 + + // Ambient temperature for inform an user + uint8_t BCM_AmbientTempHMI_ro; // Bits= 8 Offset= -50.0 Factor= 0.5 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_AmbientTempHMI_phys; +#endif // CANDB_USE_SIGFLOAT + + // The status of activating Switch for government communication. The InterCom System shall be deactivated after 5s, when switch active. + // 1 : "Government Com. Switch Active" + // 0 : "Government Com. Switch Inactive" + uint8_t BCM_GovernmentComSw_Stat; // Bits= 1 + + // Request to on/off rear window heating control indicator + // 1 : "On" + // 0 : "Off" + uint8_t BCM_RearWindowHeatingLED; // Bits= 1 + + // Footrest RR warning status + // Straponten on warning on rear tablet + // 1 : "Warning" + // 0 : "No warning" + uint8_t BCM_FootrestRRWarning_Stat; // Bits= 1 + + // The status of handset for government communication, The Intercom system shall be deactivated immediatly, when handset is picked up. + // 1 : "Handset Picked Up" + // 0 : "Handset Not Picked Up" + uint8_t BCM_GovernmentHandset_Stat; // Bits= 1 + + // Easy exit request to SMRL + // 1 : "easy Exit Enable" + // 0 : "easy Exit Disable" + uint8_t BCM_EasyExitSMRL_Stat; // Bits= 1 + + // Easy exit request to SMRR + // 1 : "easy Exit Enable" + // 0 : "easy Exit Disable" + uint8_t BCM_EasyExitSMRR_Stat; // Bits= 1 + + // Easy exit request to SMFR + // 1 : "easy Exit Enable" + // 0 : "easy Exit Disable" + uint8_t BCM_EasyExitSMFR_Stat; // Bits= 1 + + // Easy exit request to SMFL + // 1 : "easy Exit Enable" + // 0 : "easy Exit Disable" + uint8_t BCM_EasyExitSMFL_Stat; // Bits= 1 + + // Lane change Control button state + // 1 : "Button pressed" + // 0 : "Button not pressed" + uint8_t BCM_LccBtn_Stat; // Bits= 1 + + // Lane departure warning control button state + // 1 : "Button pressed" + // 0 : "Button not pressed" + uint8_t BCM_LdwBtn_Stat; // Bits= 1 + + // State of ADAS elements washing + // 1 : "Washing active" + // 0 : "Washing inactive" + uint8_t BCM_AdasSensClear_Stat; // Bits= 1 + + // T15h terminal deactivation request signal from BCM. + // 1 : "Requested" + // 0 : "Not requested" + uint8_t BCM_T15h_Deactivation_Req; // Bits= 1 + + // Satet of remote start process + // 3 : "Failure" + // 2 : "Active_Mode" + // 1 : "Initialization_Mode" + // 0 : "Inactive" + uint8_t BCM_RemoteStart_Stat; // Bits= 2 + + // Status of activation Ani Theft system. + // 1 : "Anti Theft Active state" + // 0 : "Anti Theft Inactive state" + uint8_t BCM_AntiTheft_Stat; // Bits= 1 + + // Request frrom BCM for activation LED indicator on Panoramic View Switch (CCPR) + // 1 : "On" + // 0 : "Off" + uint8_t BCM_PanoramicViewLed_Cmd; // Bits= 1 + + // Request to control electrochrome of outside mirrors + uint8_t BCM_ElcromeMirror_Req_ro; // Bits= 8 Factor= 0.394 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_ElcromeMirror_Req_phys; +#endif // CANDB_USE_SIGFLOAT + + // ADAS is requesting heat on wind sheeld + // 2 : "Error" + // 1 : "On" + // 0 : "Off" + uint8_t BCM_AdasSensWSHeat_Req; // Bits= 2 + + // Rear window washer valve request + // 1 : "Rear window washer valve requested" + // 0 : "Rear window washer valve not requested" + uint8_t BCM_RearWasherVlv_Req; // Bits= 1 + + // Soft roof control request + // 0 : "No request" + // 1 : "Open roof request" + // 2 : "Close roof request" + uint8_t BCM_RoofControl_Req; // Bits= 2 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} BCM_Veh_State2_t; + +// def @BCM_ALS_Light_Front CAN Message (643 0x283) +#define BCM_ALS_Light_Front_IDE (0U) +#define BCM_ALS_Light_Front_DLC (6U) +#define BCM_ALS_Light_Front_CANID (0x283U) + +// Value tables for @BCM_ALSZoneSelectFront_Stat signal + +#ifndef BCM_ALSZoneSelectFront_Stat_BCM_ALS_Light_Front_Front_and_rear_consoles_clock_and_automatic_gearbox_selector +#define BCM_ALSZoneSelectFront_Stat_BCM_ALS_Light_Front_Front_and_rear_consoles_clock_and_automatic_gearbox_selector (5) +#endif + +#ifndef BCM_ALSZoneSelectFront_Stat_BCM_ALS_Light_Front_Front_and_rear_consoles_clock +#define BCM_ALSZoneSelectFront_Stat_BCM_ALS_Light_Front_Front_and_rear_consoles_clock (4) +#endif + +#ifndef BCM_ALSZoneSelectFront_Stat_BCM_ALS_Light_Front_Automatic_gearbox_selector +#define BCM_ALSZoneSelectFront_Stat_BCM_ALS_Light_Front_Automatic_gearbox_selector (3) +#endif + +#ifndef BCM_ALSZoneSelectFront_Stat_BCM_ALS_Light_Front_Rear_console_clock +#define BCM_ALSZoneSelectFront_Stat_BCM_ALS_Light_Front_Rear_console_clock (2) +#endif + +#ifndef BCM_ALSZoneSelectFront_Stat_BCM_ALS_Light_Front_Front_console_clock +#define BCM_ALSZoneSelectFront_Stat_BCM_ALS_Light_Front_Front_console_clock (1) +#endif + +#ifndef BCM_ALSZoneSelectFront_Stat_BCM_ALS_Light_Front_Not_selected +#define BCM_ALSZoneSelectFront_Stat_BCM_ALS_Light_Front_Not_selected (0) +#endif + +// signal: @BCM_ALSFadingTimeFront_Val_ro +#define CANDB_BCM_ALSFadingTimeFront_Val_ro_CovFactor (0.1) +#define CANDB_BCM_ALSFadingTimeFront_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_BCM_ALSFadingTimeFront_Val_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +// Value tables for @BCM_ALSFadingFront_Req signal + +#ifndef BCM_ALSFadingFront_Req_BCM_ALS_Light_Front_Fading_ON_request +#define BCM_ALSFadingFront_Req_BCM_ALS_Light_Front_Fading_ON_request (1) +#endif + +#ifndef BCM_ALSFadingFront_Req_BCM_ALS_Light_Front_Fading_OFF_request +#define BCM_ALSFadingFront_Req_BCM_ALS_Light_Front_Fading_OFF_request (0) +#endif + + +// Value tables for @BCM_ALSLightStateFront_Req signal + +#ifndef BCM_ALSLightStateFront_Req_BCM_ALS_Light_Front_Light_ON_request +#define BCM_ALSLightStateFront_Req_BCM_ALS_Light_Front_Light_ON_request (1) +#endif + +#ifndef BCM_ALSLightStateFront_Req_BCM_ALS_Light_Front_Light_OFF_request +#define BCM_ALSLightStateFront_Req_BCM_ALS_Light_Front_Light_OFF_request (0) +#endif + +// signal: @BCM_ALSAmbIntensFront_Val_ro +#define CANDB_BCM_ALSAmbIntensFront_Val_ro_CovFactor (0.394) +#define CANDB_BCM_ALSAmbIntensFront_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.394)) ) +#define CANDB_BCM_ALSAmbIntensFront_Val_ro_fromS(x) ( (((x) * (0.394)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // BCM ALS zone select status + // Selected zone for ambient light set + // 5 : "Front and rear console's clock and automatic gearbox selector" + // 4 : "Front and rear console's clock" + // 3 : "Automatic gearbox selector" + // 2 : "Rear console clock" + // 1 : "Front console clock" + // 0 : "Not selected" + uint8_t BCM_ALSZoneSelectFront_Stat : 3; // Bits= 3 + + // BCM ALS fading time value + // (0..6.3)s illuminating fading time + uint8_t BCM_ALSFadingTimeFront_Val_ro : 6; // Bits= 6 Factor= 0.1 Unit:'s' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_ALSFadingTimeFront_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Smooth on/ off style illumination option selected or not for front zone + // 1 : "Fading ON request" + // 0 : "Fading OFF request" + uint8_t BCM_ALSFadingFront_Req : 1; // Bits= 1 + + // Request to on/ off style illumination for front zone + // 1 : "Light ON request" + // 0 : "Light OFF request" + uint8_t BCM_ALSLightStateFront_Req : 1; // Bits= 1 + + // BCM ALS intensity red value + // (0..255) range of red color intensity + uint8_t BCM_ALSIntensRedFront_Val; // Bits= 8 + + // BCM ALS intensity green value + // (0..255) range of green color intensity + uint8_t BCM_ALSIntensGreenFront_Val; // Bits= 8 + + // BCM ALS intensity blue value + // (0..255) range of blue color intensity + uint8_t BCM_ALSIntensBlueFront_Val; // Bits= 8 + + // BCM ALS ambient intensity value + // Ambient light overall intensity + uint8_t BCM_ALSAmbIntensFront_Val_ro; // Bits= 8 Factor= 0.394 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_ALSAmbIntensFront_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#else + + // BCM ALS zone select status + // Selected zone for ambient light set + // 5 : "Front and rear console's clock and automatic gearbox selector" + // 4 : "Front and rear console's clock" + // 3 : "Automatic gearbox selector" + // 2 : "Rear console clock" + // 1 : "Front console clock" + // 0 : "Not selected" + uint8_t BCM_ALSZoneSelectFront_Stat; // Bits= 3 + + // BCM ALS fading time value + // (0..6.3)s illuminating fading time + uint8_t BCM_ALSFadingTimeFront_Val_ro; // Bits= 6 Factor= 0.1 Unit:'s' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_ALSFadingTimeFront_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Smooth on/ off style illumination option selected or not for front zone + // 1 : "Fading ON request" + // 0 : "Fading OFF request" + uint8_t BCM_ALSFadingFront_Req; // Bits= 1 + + // Request to on/ off style illumination for front zone + // 1 : "Light ON request" + // 0 : "Light OFF request" + uint8_t BCM_ALSLightStateFront_Req; // Bits= 1 + + // BCM ALS intensity red value + // (0..255) range of red color intensity + uint8_t BCM_ALSIntensRedFront_Val; // Bits= 8 + + // BCM ALS intensity green value + // (0..255) range of green color intensity + uint8_t BCM_ALSIntensGreenFront_Val; // Bits= 8 + + // BCM ALS intensity blue value + // (0..255) range of blue color intensity + uint8_t BCM_ALSIntensBlueFront_Val; // Bits= 8 + + // BCM ALS ambient intensity value + // Ambient light overall intensity + uint8_t BCM_ALSAmbIntensFront_Val_ro; // Bits= 8 Factor= 0.394 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_ALSAmbIntensFront_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} BCM_ALS_Light_Front_t; + +// def @BCM_ALS_Light_Rear CAN Message (644 0x284) +#define BCM_ALS_Light_Rear_IDE (0U) +#define BCM_ALS_Light_Rear_DLC (6U) +#define BCM_ALS_Light_Rear_CANID (0x284U) +#define BCM_ALS_Light_Rear_CYC (100U) + +// Value tables for @BCM_ALSZoneSelectRear_Stat signal + +#ifndef BCM_ALSZoneSelectRear_Stat_BCM_ALS_Light_Rear_Rear_cupholder +#define BCM_ALSZoneSelectRear_Stat_BCM_ALS_Light_Rear_Rear_cupholder (6) +#endif + +#ifndef BCM_ALSZoneSelectRear_Stat_BCM_ALS_Light_Rear_All_zones +#define BCM_ALSZoneSelectRear_Stat_BCM_ALS_Light_Rear_All_zones (5) +#endif + +#ifndef BCM_ALSZoneSelectRear_Stat_BCM_ALS_Light_Rear_Front_and_rear_consoles_clock +#define BCM_ALSZoneSelectRear_Stat_BCM_ALS_Light_Rear_Front_and_rear_consoles_clock (4) +#endif + +#ifndef BCM_ALSZoneSelectRear_Stat_BCM_ALS_Light_Rear_Automatic_gearbox_selector +#define BCM_ALSZoneSelectRear_Stat_BCM_ALS_Light_Rear_Automatic_gearbox_selector (3) +#endif + +#ifndef BCM_ALSZoneSelectRear_Stat_BCM_ALS_Light_Rear_Rear_console_clock +#define BCM_ALSZoneSelectRear_Stat_BCM_ALS_Light_Rear_Rear_console_clock (2) +#endif + +#ifndef BCM_ALSZoneSelectRear_Stat_BCM_ALS_Light_Rear_Front_console_clock +#define BCM_ALSZoneSelectRear_Stat_BCM_ALS_Light_Rear_Front_console_clock (1) +#endif + +#ifndef BCM_ALSZoneSelectRear_Stat_BCM_ALS_Light_Rear_Not_selected +#define BCM_ALSZoneSelectRear_Stat_BCM_ALS_Light_Rear_Not_selected (0) +#endif + +// signal: @BCM_ALSFadingTimeRear_Val_ro +#define CANDB_BCM_ALSFadingTimeRear_Val_ro_CovFactor (0.1) +#define CANDB_BCM_ALSFadingTimeRear_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_BCM_ALSFadingTimeRear_Val_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +// Value tables for @BCM_ALSFadingRear_Req signal + +#ifndef BCM_ALSFadingRear_Req_BCM_ALS_Light_Rear_Fading_ON_request +#define BCM_ALSFadingRear_Req_BCM_ALS_Light_Rear_Fading_ON_request (1) +#endif + +#ifndef BCM_ALSFadingRear_Req_BCM_ALS_Light_Rear_Fading_OFF_request +#define BCM_ALSFadingRear_Req_BCM_ALS_Light_Rear_Fading_OFF_request (0) +#endif + + +// Value tables for @BCM_ALSLightStateRear_Req signal + +#ifndef BCM_ALSLightStateRear_Req_BCM_ALS_Light_Rear_Light_ON_request +#define BCM_ALSLightStateRear_Req_BCM_ALS_Light_Rear_Light_ON_request (1) +#endif + +#ifndef BCM_ALSLightStateRear_Req_BCM_ALS_Light_Rear_Light_OFF_request +#define BCM_ALSLightStateRear_Req_BCM_ALS_Light_Rear_Light_OFF_request (0) +#endif + +// signal: @BCM_ALSAmbIntensRear_Val_ro +#define CANDB_BCM_ALSAmbIntensRear_Val_ro_CovFactor (0.394) +#define CANDB_BCM_ALSAmbIntensRear_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.394)) ) +#define CANDB_BCM_ALSAmbIntensRear_Val_ro_fromS(x) ( (((x) * (0.394)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // BCM ALS zone select status + // Selected zone for ambient light set + // 6 : "Rear cupholder" + // 5 : "All zones" + // 4 : "Front and rear console's clock" + // 3 : "Automatic gearbox selector" + // 2 : "Rear console clock" + // 1 : "Front console clock" + // 0 : "Not selected" + uint8_t BCM_ALSZoneSelectRear_Stat : 3; // Bits= 3 + + // BCM ALS fading time value + // (0..6.3)s illuminating fading time + uint8_t BCM_ALSFadingTimeRear_Val_ro : 6; // Bits= 6 Factor= 0.1 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_ALSFadingTimeRear_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Smooth on/ off style illumination option selected or not for rear zone + // 1 : "Fading ON request" + // 0 : "Fading OFF request" + uint8_t BCM_ALSFadingRear_Req : 1; // Bits= 1 + + // Request to on/ off style illumination for rear zone + // 1 : "Light ON request" + // 0 : "Light OFF request" + uint8_t BCM_ALSLightStateRear_Req : 1; // Bits= 1 + + // BCM ALS intensity red value + // (0..255) range of red color intensity + uint8_t BCM_ALSIntensRedRear_Val; // Bits= 8 + + // BCM ALS intensity green value + // (0..255) range of green color intensity + uint8_t BCM_ALSIntensGreenRear_Val; // Bits= 8 + + // BCM ALS intensity blue value + // (0..255) range of blue color intensity + uint8_t BCM_ALSIntensBlueRear_Val; // Bits= 8 + + // BCM ALS ambient intensity value + // Ambient light overall intensity + uint8_t BCM_ALSAmbIntensRear_Val_ro; // Bits= 8 Factor= 0.394 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_ALSAmbIntensRear_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#else + + // BCM ALS zone select status + // Selected zone for ambient light set + // 6 : "Rear cupholder" + // 5 : "All zones" + // 4 : "Front and rear console's clock" + // 3 : "Automatic gearbox selector" + // 2 : "Rear console clock" + // 1 : "Front console clock" + // 0 : "Not selected" + uint8_t BCM_ALSZoneSelectRear_Stat; // Bits= 3 + + // BCM ALS fading time value + // (0..6.3)s illuminating fading time + uint8_t BCM_ALSFadingTimeRear_Val_ro; // Bits= 6 Factor= 0.1 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_ALSFadingTimeRear_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Smooth on/ off style illumination option selected or not for rear zone + // 1 : "Fading ON request" + // 0 : "Fading OFF request" + uint8_t BCM_ALSFadingRear_Req; // Bits= 1 + + // Request to on/ off style illumination for rear zone + // 1 : "Light ON request" + // 0 : "Light OFF request" + uint8_t BCM_ALSLightStateRear_Req; // Bits= 1 + + // BCM ALS intensity red value + // (0..255) range of red color intensity + uint8_t BCM_ALSIntensRedRear_Val; // Bits= 8 + + // BCM ALS intensity green value + // (0..255) range of green color intensity + uint8_t BCM_ALSIntensGreenRear_Val; // Bits= 8 + + // BCM ALS intensity blue value + // (0..255) range of blue color intensity + uint8_t BCM_ALSIntensBlueRear_Val; // Bits= 8 + + // BCM ALS ambient intensity value + // Ambient light overall intensity + uint8_t BCM_ALSAmbIntensRear_Val_ro; // Bits= 8 Factor= 0.394 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_ALSAmbIntensRear_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} BCM_ALS_Light_Rear_t; + +// def @BCM_Rear_Plafond_Light_Data CAN Message (645 0x285) +#define BCM_Rear_Plafond_Light_Data_IDE (0U) +#define BCM_Rear_Plafond_Light_Data_DLC (5U) +#define BCM_Rear_Plafond_Light_Data_CANID (0x285U) +#define BCM_Rear_Plafond_Light_Data_CYC (50U) +// signal: @BCM_PlafondRGBIntensityRear_Val_ro +#define CANDB_BCM_PlafondRGBIntensityRear_Val_ro_CovFactor (0.393) +#define CANDB_BCM_PlafondRGBIntensityRear_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.393)) ) +#define CANDB_BCM_PlafondRGBIntensityRear_Val_ro_fromS(x) ( (((x) * (0.393)) + (0.0)) ) +// signal: @BCM_Plafond_W_IntensityRear_Val_ro +#define CANDB_BCM_Plafond_W_IntensityRear_Val_ro_CovFactor (0.788) +#define CANDB_BCM_Plafond_W_IntensityRear_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.788)) ) +#define CANDB_BCM_Plafond_W_IntensityRear_Val_ro_fromS(x) ( (((x) * (0.788)) + (0.0)) ) + +// Value tables for @BCM_PlafondRGBStateRear_Req signal + +#ifndef BCM_PlafondRGBStateRear_Req_BCM_Rear_Plafond_Light_Data_RGB_Light_ON_request +#define BCM_PlafondRGBStateRear_Req_BCM_Rear_Plafond_Light_Data_RGB_Light_ON_request (1) +#endif + +#ifndef BCM_PlafondRGBStateRear_Req_BCM_Rear_Plafond_Light_Data_RGB_Light_OFF_request +#define BCM_PlafondRGBStateRear_Req_BCM_Rear_Plafond_Light_Data_RGB_Light_OFF_request (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // 0 to 255 range of red color intensity + uint8_t BCM_PlafondRedColorSetRear_Val; // Bits= 8 + + // 0 to 255 range of green color intensity + uint8_t BCM_PlafondGreenColorSetRear_Val; // Bits= 8 + + // 0 to 255 range of blue color intensity + uint8_t BCM_PlafondBlueColorSetRear_Val; // Bits= 8 + + // 0 to 100% RGB intensity value + uint8_t BCM_PlafondRGBIntensityRear_Val_ro; // Bits= 8 Factor= 0.393 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_PlafondRGBIntensityRear_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // 0 to 100% white color intensity value + uint8_t BCM_Plafond_W_IntensityRear_Val_ro : 7; // Bits= 7 Factor= 0.788 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_Plafond_W_IntensityRear_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Light on/ off state + // 1 : "RGB Light ON request" + // 0 : "RGB Light OFF request" + uint8_t BCM_PlafondRGBStateRear_Req : 1; // Bits= 1 + +#else + + // 0 to 255 range of red color intensity + uint8_t BCM_PlafondRedColorSetRear_Val; // Bits= 8 + + // 0 to 255 range of green color intensity + uint8_t BCM_PlafondGreenColorSetRear_Val; // Bits= 8 + + // 0 to 255 range of blue color intensity + uint8_t BCM_PlafondBlueColorSetRear_Val; // Bits= 8 + + // 0 to 100% RGB intensity value + uint8_t BCM_PlafondRGBIntensityRear_Val_ro; // Bits= 8 Factor= 0.393 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_PlafondRGBIntensityRear_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // 0 to 100% white color intensity value + uint8_t BCM_Plafond_W_IntensityRear_Val_ro; // Bits= 7 Factor= 0.788 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_Plafond_W_IntensityRear_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Light on/ off state + // 1 : "RGB Light ON request" + // 0 : "RGB Light OFF request" + uint8_t BCM_PlafondRGBStateRear_Req; // Bits= 1 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} BCM_Rear_Plafond_Light_Data_t; + +// def @EMS_HVC_Req_Msg CAN Message (664 0x298) +#define EMS_HVC_Req_Msg_IDE (0U) +#define EMS_HVC_Req_Msg_DLC (3U) +#define EMS_HVC_Req_Msg_CANID (0x298U) +#define EMS_HVC_Req_Msg_CYC (200U) + +// Value tables for @EMS_eCompHVRequest_Stat signal + +#ifndef EMS_eCompHVRequest_Stat_EMS_HVC_Req_Msg_HVactive +#define EMS_eCompHVRequest_Stat_EMS_HVC_Req_Msg_HVactive (1) +#endif + +#ifndef EMS_eCompHVRequest_Stat_EMS_HVC_Req_Msg_Standby +#define EMS_eCompHVRequest_Stat_EMS_HVC_Req_Msg_Standby (0) +#endif + + +// Value tables for @EMS_eCompOnPerm signal + +#ifndef EMS_eCompOnPerm_EMS_HVC_Req_Msg_HVC_might_be_activated +#define EMS_eCompOnPerm_EMS_HVC_Req_Msg_HVC_might_be_activated (1) +#endif + +#ifndef EMS_eCompOnPerm_EMS_HVC_Req_Msg_HVC_should_be_stopped +#define EMS_eCompOnPerm_EMS_HVC_Req_Msg_HVC_should_be_stopped (0) +#endif + + +// Value tables for @EMS_eCompChiller_Req signal + +#ifndef EMS_eCompChiller_Req_EMS_HVC_Req_Msg_Chiller_activation_request +#define EMS_eCompChiller_Req_EMS_HVC_Req_Msg_Chiller_activation_request (1) +#endif + +#ifndef EMS_eCompChiller_Req_EMS_HVC_Req_Msg_No_request +#define EMS_eCompChiller_Req_EMS_HVC_Req_Msg_No_request (0) +#endif + +// signal: @EMS_eCompHVCurLimit_Val_ro +#define CANDB_EMS_eCompHVCurLimit_Val_ro_CovFactor (0.1) +#define CANDB_EMS_eCompHVCurLimit_Val_ro_toS(x) ( (uint16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_EMS_eCompHVCurLimit_Val_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // 1 : "HV-active" + // 0 : "Standby" + uint8_t EMS_eCompHVRequest_Stat : 1; // Bits= 1 + + // 1 : "HVC might be activated" + // 0 : "HVC should be stopped" + uint8_t EMS_eCompOnPerm : 1; // Bits= 1 + + // 1 : "Chiller activation request" + // 0 : "No request" + uint8_t EMS_eCompChiller_Req : 1; // Bits= 1 + + // Maximum current limitation: + // 0x1FF = Fault + uint16_t EMS_eCompHVCurLimit_Val_ro; // Bits= 9 Factor= 0.1 Unit:'A' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t EMS_eCompHVCurLimit_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Rolling Counter [0 - 15] + uint8_t EMS_HVC_Req_RC : 4; // Bits= 4 + + // Checksum XOR8 of the data field this message + // Checksum computed as per XOR algorithm: + // Byte 1 XOR byte 2 .... XOR byte n-1. (n = packet length.) + uint8_t EMS_HVC_Req_CS; // Bits= 8 + +#else + + // 1 : "HV-active" + // 0 : "Standby" + uint8_t EMS_eCompHVRequest_Stat; // Bits= 1 + + // 1 : "HVC might be activated" + // 0 : "HVC should be stopped" + uint8_t EMS_eCompOnPerm; // Bits= 1 + + // 1 : "Chiller activation request" + // 0 : "No request" + uint8_t EMS_eCompChiller_Req; // Bits= 1 + + // Maximum current limitation: + // 0x1FF = Fault + uint16_t EMS_eCompHVCurLimit_Val_ro; // Bits= 9 Factor= 0.1 Unit:'A' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t EMS_eCompHVCurLimit_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Rolling Counter [0 - 15] + uint8_t EMS_HVC_Req_RC; // Bits= 4 + + // Checksum XOR8 of the data field this message + // Checksum computed as per XOR algorithm: + // Byte 1 XOR byte 2 .... XOR byte n-1. (n = packet length.) + uint8_t EMS_HVC_Req_CS; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} EMS_HVC_Req_Msg_t; + +// def @SAS_Standard CAN Message (688 0x2b0) +#define SAS_Standard_IDE (0U) +#define SAS_Standard_DLC (5U) +#define SAS_Standard_CANID (0x2b0U) +#define SAS_Standard_CYC (10U) +// signal: @SAS_Angle_ro +#define CANDB_SAS_Angle_ro_CovFactor (0.1) +#define CANDB_SAS_Angle_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_SAS_Angle_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @SAS_Speed_ro +#define CANDB_SAS_Speed_ro_CovFactor (4) +#define CANDB_SAS_Speed_ro_toS(x) ( (uint8_t) ((x) / (4)) ) +#define CANDB_SAS_Speed_ro_fromS(x) ( ((x) * (4)) ) + +// Value tables for @SAS_OK_Stat signal + +#ifndef SAS_OK_Stat_SAS_Standard_sensor_information_valid +#define SAS_OK_Stat_SAS_Standard_sensor_information_valid (1) +#endif + +#ifndef SAS_OK_Stat_SAS_Standard_sensor_information_invalid_internal_sensor_fault +#define SAS_OK_Stat_SAS_Standard_sensor_information_invalid_internal_sensor_fault (0) +#endif + + +// Value tables for @SAS_CAL_Stat signal + +#ifndef SAS_CAL_Stat_SAS_Standard_sensor_calibrated +#define SAS_CAL_Stat_SAS_Standard_sensor_calibrated (1) +#endif + +#ifndef SAS_CAL_Stat_SAS_Standard_Sensor_not_calibrated +#define SAS_CAL_Stat_SAS_Standard_Sensor_not_calibrated (0) +#endif + + +// Value tables for @SAS_TRIM_Stat signal + +#ifndef SAS_TRIM_Stat_SAS_Standard_sensor_trimmer +#define SAS_TRIM_Stat_SAS_Standard_sensor_trimmer (1) +#endif + +#ifndef SAS_TRIM_Stat_SAS_Standard_Sensor_not_trimmed +#define SAS_TRIM_Stat_SAS_Standard_Sensor_not_trimmed (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Steering wheel angle. Signal outputs fault value if sensor is not calibrated or sensor has detected internal failure + int16_t SAS_Angle_ro; // [-] Bits=16 Factor= 0.1 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SAS_Angle_phys; +#endif // CANDB_USE_SIGFLOAT + + // Steering Wheel rotation speed. Outputs fault value if sensor has detected internal failure. + uint8_t SAS_Speed_ro; // Bits= 8 Factor= 4 Unit:'�/s' + +#ifdef CANDB_USE_SIGFLOAT + uint16_t SAS_Speed_phys; +#endif // CANDB_USE_SIGFLOAT + + // Failure status. + // 1 : "sensor information valid" + // 0 : "sensor information invalid, internal sensor fault" + uint8_t SAS_OK_Stat : 1; // Bits= 1 + + // Calibration status + // 1 : "sensor calibrated" + // 0 : "Sensor not calibrated" + uint8_t SAS_CAL_Stat : 1; // Bits= 1 + + // Indicates trimming status of sensor done at development plants. Used only for development/ internal purposes at Bosch + // 1 : "sensor trimmer" + // 0 : "Sensor not trimmed" + uint8_t SAS_TRIM_Stat : 1; // Bits= 1 + + // Internal status flags SF1 up to SF5. Only for internal use at Bosch + uint8_t SAS_SF1_5_Stat : 5; // Bits= 5 + + // Rolling Counter [0 - 15] + uint8_t SAS_Standard_RC : 4; // Bits= 4 + + // Checksum XOR4 of the data field this message + // Temp_result = [SAS_Angle(Low byte)] XOR [SAS_Angle(High byte)] + // XOR [SAS_Speed] XOR [SAS_Stat] + // Checksum = [Temp_result (High 4bit)] XOR [Temp_result(Low 4bit)] XOR [MsgCount] + uint8_t SAS_Standard_CS : 4; // Bits= 4 + +#else + + // Steering wheel angle. Signal outputs fault value if sensor is not calibrated or sensor has detected internal failure + int16_t SAS_Angle_ro; // [-] Bits=16 Factor= 0.1 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SAS_Angle_phys; +#endif // CANDB_USE_SIGFLOAT + + // Steering Wheel rotation speed. Outputs fault value if sensor has detected internal failure. + uint8_t SAS_Speed_ro; // Bits= 8 Factor= 4 Unit:'�/s' + +#ifdef CANDB_USE_SIGFLOAT + uint16_t SAS_Speed_phys; +#endif // CANDB_USE_SIGFLOAT + + // Failure status. + // 1 : "sensor information valid" + // 0 : "sensor information invalid, internal sensor fault" + uint8_t SAS_OK_Stat; // Bits= 1 + + // Calibration status + // 1 : "sensor calibrated" + // 0 : "Sensor not calibrated" + uint8_t SAS_CAL_Stat; // Bits= 1 + + // Indicates trimming status of sensor done at development plants. Used only for development/ internal purposes at Bosch + // 1 : "sensor trimmer" + // 0 : "Sensor not trimmed" + uint8_t SAS_TRIM_Stat; // Bits= 1 + + // Internal status flags SF1 up to SF5. Only for internal use at Bosch + uint8_t SAS_SF1_5_Stat; // Bits= 5 + + // Rolling Counter [0 - 15] + uint8_t SAS_Standard_RC; // Bits= 4 + + // Checksum XOR4 of the data field this message + // Temp_result = [SAS_Angle(Low byte)] XOR [SAS_Angle(High byte)] + // XOR [SAS_Speed] XOR [SAS_Stat] + // Checksum = [Temp_result (High 4bit)] XOR [Temp_result(Low 4bit)] XOR [MsgCount] + uint8_t SAS_Standard_CS; // Bits= 4 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} SAS_Standard_t; + +// def @IC_ABSOLUTE_CLOCK CAN Message (743 0x2e7) +#define IC_ABSOLUTE_CLOCK_IDE (0U) +#define IC_ABSOLUTE_CLOCK_DLC (6U) +#define IC_ABSOLUTE_CLOCK_CANID (0x2e7U) +#define IC_ABSOLUTE_CLOCK_CYC (1000U) + +// Value tables for @IC_AbsoluteDateAndTime signal + +#ifndef IC_AbsoluteDateAndTime_IC_ABSOLUTE_CLOCK_Fault_value +#define IC_AbsoluteDateAndTime_IC_ABSOLUTE_CLOCK_Fault_value (-1) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Absolute time initiated at the assembly line moment. + // UNIX Clock date and time information. + // Epoch time = year zero => UNIX Clock = 0 => 1 January 1970 + // The Unix time number is zero at the Unix epoch, and increases by exactly 86400 per day since the epoch + // -1 : "Fault value" + uint32_t IC_AbsoluteDateAndTime; // Bits=32 + + // Rolling Counter [0 - 15] + uint8_t IC_ABSOLUTE_CLOCK_RC : 4; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t IC_ABSOLUTE_CLOCK_CS; // Bits= 8 + +#else + + // Absolute time initiated at the assembly line moment. + // UNIX Clock date and time information. + // Epoch time = year zero => UNIX Clock = 0 => 1 January 1970 + // The Unix time number is zero at the Unix epoch, and increases by exactly 86400 per day since the epoch + // -1 : "Fault value" + uint32_t IC_AbsoluteDateAndTime; // Bits=32 + + // Rolling Counter [0 - 15] + uint8_t IC_ABSOLUTE_CLOCK_RC; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t IC_ABSOLUTE_CLOCK_CS; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} IC_ABSOLUTE_CLOCK_t; + +// def @BCM_Lock_CTR CAN Message (752 0x2f0) +#define BCM_Lock_CTR_IDE (0U) +#define BCM_Lock_CTR_DLC (7U) +#define BCM_Lock_CTR_CANID (0x2f0U) +#define BCM_Lock_CTR_CYC (50U) + +// Value tables for @VehicleLockStateReason signal + +#ifndef VehicleLockStateReason_BCM_Lock_CTR_Locked_by_ReLock +#define VehicleLockStateReason_BCM_Lock_CTR_Locked_by_ReLock (11) +#endif + +#ifndef VehicleLockStateReason_BCM_Lock_CTR_Locked_drive_away +#define VehicleLockStateReason_BCM_Lock_CTR_Locked_drive_away (10) +#endif + +#ifndef VehicleLockStateReason_BCM_Lock_CTR_Locked_PreCrash +#define VehicleLockStateReason_BCM_Lock_CTR_Locked_PreCrash (9) +#endif + +#ifndef VehicleLockStateReason_BCM_Lock_CTR_Locked_Internal +#define VehicleLockStateReason_BCM_Lock_CTR_Locked_Internal (8) +#endif + +#ifndef VehicleLockStateReason_BCM_Lock_CTR_Locked_External +#define VehicleLockStateReason_BCM_Lock_CTR_Locked_External (7) +#endif + +#ifndef VehicleLockStateReason_BCM_Lock_CTR_Unlocked_by_Theft_Action +#define VehicleLockStateReason_BCM_Lock_CTR_Unlocked_by_Theft_Action (6) +#endif + +#ifndef VehicleLockStateReason_BCM_Lock_CTR_Unlocked_Post_Crash +#define VehicleLockStateReason_BCM_Lock_CTR_Unlocked_Post_Crash (5) +#endif + +#ifndef VehicleLockStateReason_BCM_Lock_CTR_Unlocked_Int_Trunk_Only +#define VehicleLockStateReason_BCM_Lock_CTR_Unlocked_Int_Trunk_Only (4) +#endif + +#ifndef VehicleLockStateReason_BCM_Lock_CTR_Unlocked_Ext_Trunk_Only +#define VehicleLockStateReason_BCM_Lock_CTR_Unlocked_Ext_Trunk_Only (3) +#endif + +#ifndef VehicleLockStateReason_BCM_Lock_CTR_Unlocked_From_Internal +#define VehicleLockStateReason_BCM_Lock_CTR_Unlocked_From_Internal (2) +#endif + +#ifndef VehicleLockStateReason_BCM_Lock_CTR_Unlocked_From_External +#define VehicleLockStateReason_BCM_Lock_CTR_Unlocked_From_External (1) +#endif + +#ifndef VehicleLockStateReason_BCM_Lock_CTR_Unknown +#define VehicleLockStateReason_BCM_Lock_CTR_Unknown (0) +#endif + + +// Value tables for @BCM_FrontLeftLockCmd signal + +#ifndef BCM_FrontLeftLockCmd_BCM_Lock_CTR_DoubleLockDisable_Req +#define BCM_FrontLeftLockCmd_BCM_Lock_CTR_DoubleLockDisable_Req (4) +#endif + +#ifndef BCM_FrontLeftLockCmd_BCM_Lock_CTR_DoubleLock_Req +#define BCM_FrontLeftLockCmd_BCM_Lock_CTR_DoubleLock_Req (3) +#endif + +#ifndef BCM_FrontLeftLockCmd_BCM_Lock_CTR_SingleLock_Req +#define BCM_FrontLeftLockCmd_BCM_Lock_CTR_SingleLock_Req (2) +#endif + +#ifndef BCM_FrontLeftLockCmd_BCM_Lock_CTR_Unlock_Req +#define BCM_FrontLeftLockCmd_BCM_Lock_CTR_Unlock_Req (1) +#endif + +#ifndef BCM_FrontLeftLockCmd_BCM_Lock_CTR_No_Request +#define BCM_FrontLeftLockCmd_BCM_Lock_CTR_No_Request (0) +#endif + + +// Value tables for @BCM_TrunkLatchRelease_Req signal + +#ifndef BCM_TrunkLatchRelease_Req_BCM_Lock_CTR_Trunk_lid_unlock_requested +#define BCM_TrunkLatchRelease_Req_BCM_Lock_CTR_Trunk_lid_unlock_requested (1) +#endif + +#ifndef BCM_TrunkLatchRelease_Req_BCM_Lock_CTR_Not_requested +#define BCM_TrunkLatchRelease_Req_BCM_Lock_CTR_Not_requested (0) +#endif + + +// Value tables for @BCM_FrontRightLockCmd signal + +#ifndef BCM_FrontRightLockCmd_BCM_Lock_CTR_DoubleLockDisable_Req +#define BCM_FrontRightLockCmd_BCM_Lock_CTR_DoubleLockDisable_Req (4) +#endif + +#ifndef BCM_FrontRightLockCmd_BCM_Lock_CTR_DoubleLock_Req +#define BCM_FrontRightLockCmd_BCM_Lock_CTR_DoubleLock_Req (3) +#endif + +#ifndef BCM_FrontRightLockCmd_BCM_Lock_CTR_SingleLock_Req +#define BCM_FrontRightLockCmd_BCM_Lock_CTR_SingleLock_Req (2) +#endif + +#ifndef BCM_FrontRightLockCmd_BCM_Lock_CTR_Unlock_Req +#define BCM_FrontRightLockCmd_BCM_Lock_CTR_Unlock_Req (1) +#endif + +#ifndef BCM_FrontRightLockCmd_BCM_Lock_CTR_No_Request +#define BCM_FrontRightLockCmd_BCM_Lock_CTR_No_Request (0) +#endif + + +// Value tables for @PTG_MovementCmd signal + +#ifndef PTG_MovementCmd_BCM_Lock_CTR_Close +#define PTG_MovementCmd_BCM_Lock_CTR_Close (2) +#endif + +#ifndef PTG_MovementCmd_BCM_Lock_CTR_Open_ +#define PTG_MovementCmd_BCM_Lock_CTR_Open_ (1) +#endif + +#ifndef PTG_MovementCmd_BCM_Lock_CTR_Stop +#define PTG_MovementCmd_BCM_Lock_CTR_Stop (0) +#endif + + +// Value tables for @BCM_RearLeftLockCmd signal + +#ifndef BCM_RearLeftLockCmd_BCM_Lock_CTR_DoubleLockDisable_Req +#define BCM_RearLeftLockCmd_BCM_Lock_CTR_DoubleLockDisable_Req (4) +#endif + +#ifndef BCM_RearLeftLockCmd_BCM_Lock_CTR_DoubleLock_Req +#define BCM_RearLeftLockCmd_BCM_Lock_CTR_DoubleLock_Req (3) +#endif + +#ifndef BCM_RearLeftLockCmd_BCM_Lock_CTR_SingleLock_Req +#define BCM_RearLeftLockCmd_BCM_Lock_CTR_SingleLock_Req (2) +#endif + +#ifndef BCM_RearLeftLockCmd_BCM_Lock_CTR_Unlock_Req +#define BCM_RearLeftLockCmd_BCM_Lock_CTR_Unlock_Req (1) +#endif + +#ifndef BCM_RearLeftLockCmd_BCM_Lock_CTR_No_Request +#define BCM_RearLeftLockCmd_BCM_Lock_CTR_No_Request (0) +#endif + + +// Value tables for @BCM_RearRightLockCmd signal + +#ifndef BCM_RearRightLockCmd_BCM_Lock_CTR_DoubleLockDisable_Req +#define BCM_RearRightLockCmd_BCM_Lock_CTR_DoubleLockDisable_Req (4) +#endif + +#ifndef BCM_RearRightLockCmd_BCM_Lock_CTR_DoubleLock_Req +#define BCM_RearRightLockCmd_BCM_Lock_CTR_DoubleLock_Req (3) +#endif + +#ifndef BCM_RearRightLockCmd_BCM_Lock_CTR_SingleLock_Req +#define BCM_RearRightLockCmd_BCM_Lock_CTR_SingleLock_Req (2) +#endif + +#ifndef BCM_RearRightLockCmd_BCM_Lock_CTR_Unlock_Req +#define BCM_RearRightLockCmd_BCM_Lock_CTR_Unlock_Req (1) +#endif + +#ifndef BCM_RearRightLockCmd_BCM_Lock_CTR_No_Request +#define BCM_RearRightLockCmd_BCM_Lock_CTR_No_Request (0) +#endif + + +// Value tables for @BCM_FLDoorClose_Req signal + +#ifndef BCM_FLDoorClose_Req_BCM_Lock_CTR_Open_door +#define BCM_FLDoorClose_Req_BCM_Lock_CTR_Open_door (2) +#endif + +#ifndef BCM_FLDoorClose_Req_BCM_Lock_CTR_Close_door +#define BCM_FLDoorClose_Req_BCM_Lock_CTR_Close_door (1) +#endif + +#ifndef BCM_FLDoorClose_Req_BCM_Lock_CTR_No_action +#define BCM_FLDoorClose_Req_BCM_Lock_CTR_No_action (0) +#endif + + +// Value tables for @PTG_MemorySetRequest signal + +#ifndef PTG_MemorySetRequest_BCM_Lock_CTR_Clear_Memory +#define PTG_MemorySetRequest_BCM_Lock_CTR_Clear_Memory (2) +#endif + +#ifndef PTG_MemorySetRequest_BCM_Lock_CTR_Store_Position_in_memory +#define PTG_MemorySetRequest_BCM_Lock_CTR_Store_Position_in_memory (1) +#endif + +#ifndef PTG_MemorySetRequest_BCM_Lock_CTR_No_Request +#define PTG_MemorySetRequest_BCM_Lock_CTR_No_Request (0) +#endif + + +// Value tables for @VehicleLockState signal + +#ifndef VehicleLockState_BCM_Lock_CTR_Vehicle_locked +#define VehicleLockState_BCM_Lock_CTR_Vehicle_locked (1) +#endif + +#ifndef VehicleLockState_BCM_Lock_CTR_Vehicle_unlocked +#define VehicleLockState_BCM_Lock_CTR_Vehicle_unlocked (0) +#endif + + +// Value tables for @BCM_DoorAjarState_FL signal + +#ifndef BCM_DoorAjarState_FL_BCM_Lock_CTR_Fault +#define BCM_DoorAjarState_FL_BCM_Lock_CTR_Fault (3) +#endif + +#ifndef BCM_DoorAjarState_FL_BCM_Lock_CTR_Door_Opened +#define BCM_DoorAjarState_FL_BCM_Lock_CTR_Door_Opened (2) +#endif + +#ifndef BCM_DoorAjarState_FL_BCM_Lock_CTR_Door_Closed +#define BCM_DoorAjarState_FL_BCM_Lock_CTR_Door_Closed (1) +#endif + +#ifndef BCM_DoorAjarState_FL_BCM_Lock_CTR_Reserved +#define BCM_DoorAjarState_FL_BCM_Lock_CTR_Reserved (0) +#endif + + +// Value tables for @BCM_DoorAjarState_FR signal + +#ifndef BCM_DoorAjarState_FR_BCM_Lock_CTR_Fault +#define BCM_DoorAjarState_FR_BCM_Lock_CTR_Fault (3) +#endif + +#ifndef BCM_DoorAjarState_FR_BCM_Lock_CTR_Door_Opened +#define BCM_DoorAjarState_FR_BCM_Lock_CTR_Door_Opened (2) +#endif + +#ifndef BCM_DoorAjarState_FR_BCM_Lock_CTR_Door_Closed +#define BCM_DoorAjarState_FR_BCM_Lock_CTR_Door_Closed (1) +#endif + +#ifndef BCM_DoorAjarState_FR_BCM_Lock_CTR_Reserved +#define BCM_DoorAjarState_FR_BCM_Lock_CTR_Reserved (0) +#endif + + +// Value tables for @BCM_DoorAjarState_RL signal + +#ifndef BCM_DoorAjarState_RL_BCM_Lock_CTR_Fault +#define BCM_DoorAjarState_RL_BCM_Lock_CTR_Fault (3) +#endif + +#ifndef BCM_DoorAjarState_RL_BCM_Lock_CTR_Door_Opened +#define BCM_DoorAjarState_RL_BCM_Lock_CTR_Door_Opened (2) +#endif + +#ifndef BCM_DoorAjarState_RL_BCM_Lock_CTR_Door_Closed +#define BCM_DoorAjarState_RL_BCM_Lock_CTR_Door_Closed (1) +#endif + +#ifndef BCM_DoorAjarState_RL_BCM_Lock_CTR_Reserved +#define BCM_DoorAjarState_RL_BCM_Lock_CTR_Reserved (0) +#endif + + +// Value tables for @BCM_DoorAjarState_RR signal + +#ifndef BCM_DoorAjarState_RR_BCM_Lock_CTR_Fault +#define BCM_DoorAjarState_RR_BCM_Lock_CTR_Fault (3) +#endif + +#ifndef BCM_DoorAjarState_RR_BCM_Lock_CTR_Door_Opened +#define BCM_DoorAjarState_RR_BCM_Lock_CTR_Door_Opened (2) +#endif + +#ifndef BCM_DoorAjarState_RR_BCM_Lock_CTR_Door_Closed +#define BCM_DoorAjarState_RR_BCM_Lock_CTR_Door_Closed (1) +#endif + +#ifndef BCM_DoorAjarState_RR_BCM_Lock_CTR_Reserved +#define BCM_DoorAjarState_RR_BCM_Lock_CTR_Reserved (0) +#endif + + +// Value tables for @BCM_VehDoubleLock_Stat signal + +#ifndef BCM_VehDoubleLock_Stat_BCM_Lock_CTR_Double_lock_active +#define BCM_VehDoubleLock_Stat_BCM_Lock_CTR_Double_lock_active (1) +#endif + +#ifndef BCM_VehDoubleLock_Stat_BCM_Lock_CTR_Double_lock_inactive +#define BCM_VehDoubleLock_Stat_BCM_Lock_CTR_Double_lock_inactive (0) +#endif + + +// Value tables for @BCM_FuelLidUnlock_Req signal + +#ifndef BCM_FuelLidUnlock_Req_BCM_Lock_CTR_Unlock_fuel_lid +#define BCM_FuelLidUnlock_Req_BCM_Lock_CTR_Unlock_fuel_lid (1) +#endif + +#ifndef BCM_FuelLidUnlock_Req_BCM_Lock_CTR_No_Action +#define BCM_FuelLidUnlock_Req_BCM_Lock_CTR_No_Action (0) +#endif + + +// Value tables for @BCM_HVlid_Stat signal + +#ifndef BCM_HVlid_Stat_BCM_Lock_CTR_HV_lid_opened +#define BCM_HVlid_Stat_BCM_Lock_CTR_HV_lid_opened (1) +#endif + +#ifndef BCM_HVlid_Stat_BCM_Lock_CTR_HV_lid_closed +#define BCM_HVlid_Stat_BCM_Lock_CTR_HV_lid_closed (0) +#endif + + +// Value tables for @BCM_RRDoorClose_Req signal + +#ifndef BCM_RRDoorClose_Req_BCM_Lock_CTR_Open_door +#define BCM_RRDoorClose_Req_BCM_Lock_CTR_Open_door (2) +#endif + +#ifndef BCM_RRDoorClose_Req_BCM_Lock_CTR_Close_door +#define BCM_RRDoorClose_Req_BCM_Lock_CTR_Close_door (1) +#endif + +#ifndef BCM_RRDoorClose_Req_BCM_Lock_CTR_No_action +#define BCM_RRDoorClose_Req_BCM_Lock_CTR_No_action (0) +#endif + + +// Value tables for @BCM_WindowsClose_Cmd signal + +#ifndef BCM_WindowsClose_Cmd_BCM_Lock_CTR_Windows_Closing_command +#define BCM_WindowsClose_Cmd_BCM_Lock_CTR_Windows_Closing_command (1) +#endif + +#ifndef BCM_WindowsClose_Cmd_BCM_Lock_CTR_No_Command +#define BCM_WindowsClose_Cmd_BCM_Lock_CTR_No_Command (0) +#endif + + +// Value tables for @BCM_FRDoorClose_Req signal + +#ifndef BCM_FRDoorClose_Req_BCM_Lock_CTR_Open_door +#define BCM_FRDoorClose_Req_BCM_Lock_CTR_Open_door (2) +#endif + +#ifndef BCM_FRDoorClose_Req_BCM_Lock_CTR_Close_door +#define BCM_FRDoorClose_Req_BCM_Lock_CTR_Close_door (1) +#endif + +#ifndef BCM_FRDoorClose_Req_BCM_Lock_CTR_No_action +#define BCM_FRDoorClose_Req_BCM_Lock_CTR_No_action (0) +#endif + + +// Value tables for @BCM_HoodOpen_Stat signal + +#ifndef BCM_HoodOpen_Stat_BCM_Lock_CTR_Sensor_error +#define BCM_HoodOpen_Stat_BCM_Lock_CTR_Sensor_error (3) +#endif + +#ifndef BCM_HoodOpen_Stat_BCM_Lock_CTR_Hood_closed +#define BCM_HoodOpen_Stat_BCM_Lock_CTR_Hood_closed (2) +#endif + +#ifndef BCM_HoodOpen_Stat_BCM_Lock_CTR_Hood_opened +#define BCM_HoodOpen_Stat_BCM_Lock_CTR_Hood_opened (1) +#endif + +#ifndef BCM_HoodOpen_Stat_BCM_Lock_CTR_Reserved +#define BCM_HoodOpen_Stat_BCM_Lock_CTR_Reserved (0) +#endif + + +// Value tables for @BCM_PanicAlertActive signal + +#ifndef BCM_PanicAlertActive_BCM_Lock_CTR_Panic_Mode_Active +#define BCM_PanicAlertActive_BCM_Lock_CTR_Panic_Mode_Active (1) +#endif + +#ifndef BCM_PanicAlertActive_BCM_Lock_CTR_Panic_Mode_Inactive +#define BCM_PanicAlertActive_BCM_Lock_CTR_Panic_Mode_Inactive (0) +#endif + + +// Value tables for @BCM_RLDoorClose_Req signal + +#ifndef BCM_RLDoorClose_Req_BCM_Lock_CTR_Open_door +#define BCM_RLDoorClose_Req_BCM_Lock_CTR_Open_door (2) +#endif + +#ifndef BCM_RLDoorClose_Req_BCM_Lock_CTR_Close_door +#define BCM_RLDoorClose_Req_BCM_Lock_CTR_Close_door (1) +#endif + +#ifndef BCM_RLDoorClose_Req_BCM_Lock_CTR_No_action +#define BCM_RLDoorClose_Req_BCM_Lock_CTR_No_action (0) +#endif + + +// Value tables for @BCM_RearWiperWipe_Req signal + +#ifndef BCM_RearWiperWipe_Req_BCM_Lock_CTR_Requested +#define BCM_RearWiperWipe_Req_BCM_Lock_CTR_Requested (1) +#endif + +#ifndef BCM_RearWiperWipe_Req_BCM_Lock_CTR_No_requested +#define BCM_RearWiperWipe_Req_BCM_Lock_CTR_No_requested (0) +#endif + + +// Value tables for @BCM_AlarmOFF_Stat signal + +#ifndef BCM_AlarmOFF_Stat_BCM_Lock_CTR_Alarm_system_disabled +#define BCM_AlarmOFF_Stat_BCM_Lock_CTR_Alarm_system_disabled (1) +#endif + +#ifndef BCM_AlarmOFF_Stat_BCM_Lock_CTR_Alarm_system_enabled +#define BCM_AlarmOFF_Stat_BCM_Lock_CTR_Alarm_system_enabled (0) +#endif + + +// Value tables for @BCM_MovementSensOFF_Stat signal + +#ifndef BCM_MovementSensOFF_Stat_BCM_Lock_CTR_Sensor_inactive +#define BCM_MovementSensOFF_Stat_BCM_Lock_CTR_Sensor_inactive (1) +#endif + +#ifndef BCM_MovementSensOFF_Stat_BCM_Lock_CTR_Sensor_active +#define BCM_MovementSensOFF_Stat_BCM_Lock_CTR_Sensor_active (0) +#endif + + +// Value tables for @BCM_DoorMovDis_Stat signal + +#ifndef BCM_DoorMovDis_Stat_BCM_Lock_CTR_Door_movement_system_disabled +#define BCM_DoorMovDis_Stat_BCM_Lock_CTR_Door_movement_system_disabled (1) +#endif + +#ifndef BCM_DoorMovDis_Stat_BCM_Lock_CTR_Door_movement_system_enabled +#define BCM_DoorMovDis_Stat_BCM_Lock_CTR_Door_movement_system_enabled (0) +#endif + + +// Value tables for @BCM_Alarm_Req signal + +#ifndef BCM_Alarm_Req_BCM_Lock_CTR_Request_Active +#define BCM_Alarm_Req_BCM_Lock_CTR_Request_Active (1) +#endif + +#ifndef BCM_Alarm_Req_BCM_Lock_CTR_No_Request +#define BCM_Alarm_Req_BCM_Lock_CTR_No_Request (0) +#endif + + +// Value tables for @BCM_Alarm_Reason signal + +#ifndef BCM_Alarm_Reason_BCM_Lock_CTR_Hit_detected +#define BCM_Alarm_Reason_BCM_Lock_CTR_Hit_detected (10) +#endif + +#ifndef BCM_Alarm_Reason_BCM_Lock_CTR_Towing_detected +#define BCM_Alarm_Reason_BCM_Lock_CTR_Towing_detected (9) +#endif + +#ifndef BCM_Alarm_Reason_BCM_Lock_CTR_Hood_open +#define BCM_Alarm_Reason_BCM_Lock_CTR_Hood_open (8) +#endif + +#ifndef BCM_Alarm_Reason_BCM_Lock_CTR_Intrusion_level_2_requested +#define BCM_Alarm_Reason_BCM_Lock_CTR_Intrusion_level_2_requested (7) +#endif + +#ifndef BCM_Alarm_Reason_BCM_Lock_CTR_Intrusion_level_1_requested +#define BCM_Alarm_Reason_BCM_Lock_CTR_Intrusion_level_1_requested (6) +#endif + +#ifndef BCM_Alarm_Reason_BCM_Lock_CTR_TrunkLid_Open +#define BCM_Alarm_Reason_BCM_Lock_CTR_TrunkLid_Open (5) +#endif + +#ifndef BCM_Alarm_Reason_BCM_Lock_CTR_RR_door_open +#define BCM_Alarm_Reason_BCM_Lock_CTR_RR_door_open (4) +#endif + +#ifndef BCM_Alarm_Reason_BCM_Lock_CTR_RL_door_open +#define BCM_Alarm_Reason_BCM_Lock_CTR_RL_door_open (3) +#endif + +#ifndef BCM_Alarm_Reason_BCM_Lock_CTR_FR_door_open +#define BCM_Alarm_Reason_BCM_Lock_CTR_FR_door_open (2) +#endif + +#ifndef BCM_Alarm_Reason_BCM_Lock_CTR_FL_door_open +#define BCM_Alarm_Reason_BCM_Lock_CTR_FL_door_open (1) +#endif + +#ifndef BCM_Alarm_Reason_BCM_Lock_CTR_No_Reasons +#define BCM_Alarm_Reason_BCM_Lock_CTR_No_Reasons (0) +#endif + + +// Value tables for @BCM_DoorHandleLight_Req signal + +#ifndef BCM_DoorHandleLight_Req_BCM_Lock_CTR_Requested +#define BCM_DoorHandleLight_Req_BCM_Lock_CTR_Requested (1) +#endif + +#ifndef BCM_DoorHandleLight_Req_BCM_Lock_CTR_No_requested +#define BCM_DoorHandleLight_Req_BCM_Lock_CTR_No_requested (0) +#endif + + +// Value tables for @BCM_WindowsOpen_Req signal + +#ifndef BCM_WindowsOpen_Req_BCM_Lock_CTR_Windows_Opening_requested +#define BCM_WindowsOpen_Req_BCM_Lock_CTR_Windows_Opening_requested (1) +#endif + +#ifndef BCM_WindowsOpen_Req_BCM_Lock_CTR_Not_requested +#define BCM_WindowsOpen_Req_BCM_Lock_CTR_Not_requested (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Reason of vehicle lock state + // 11 : "Locked by Re-Lock" + // 10 : "Locked drive away" + // 9 : "Locked Pre-Crash" + // 8 : "Locked Internal" + // 7 : "Locked External" + // 6 : "Unlocked by Theft Action" + // 5 : "Unlocked Post Crash" + // 4 : "Unlocked Int. Trunk Only" + // 3 : "Unlocked Ext. Trunk Only" + // 2 : "Unlocked From Internal" + // 1 : "Unlocked From External" + // 0 : "Unknown" + uint8_t VehicleLockStateReason : 4; // Bits= 4 + + // $0 = NO_ACTION + // $1 = UNLOCK + // $2 = LOCK + // $3 = SECURE_LOCK + // $4 = UNSECURE_LOCK + // 4 : "DoubleLockDisable_Req" + // 3 : "DoubleLock_Req" + // 2 : "SingleLock_Req" + // 1 : "Unlock_Req" + // 0 : "No_Request" + uint8_t BCM_FrontLeftLockCmd : 3; // Bits= 3 + + // Indicates whether the trunk latch is commanded to be released or not + // 1 : "Trunk lid unlock requested" + // 0 : "Not requested" + uint8_t BCM_TrunkLatchRelease_Req : 1; // Bits= 1 + + // $0 = NO_ACTION + // $1 = UNLOCK + // $2 = LOCK + // $3 = SECURE_LOCK + // $4 = UNSECURE_LOCK + // 4 : "DoubleLockDisable_Req" + // 3 : "DoubleLock_Req" + // 2 : "SingleLock_Req" + // 1 : "Unlock_Req" + // 0 : "No_Request" + uint8_t BCM_FrontRightLockCmd : 3; // Bits= 3 + + // Indicates the power tailgate movement command: + // 0x0 = Stop + // 0x1 = Open + // 0x2 = Close + // 2 : "Close" + // 1 : "Open " + // 0 : "Stop" + uint8_t PTG_MovementCmd : 2; // Bits= 2 + + // $0 = NO_ACTION + // $1 = UNLOCK + // $2 = LOCK + // $3 = SECURE_LOCK + // $4 = UNSECURE_LOCK + // 4 : "DoubleLockDisable_Req" + // 3 : "DoubleLock_Req" + // 2 : "SingleLock_Req" + // 1 : "Unlock_Req" + // 0 : "No_Request" + uint8_t BCM_RearLeftLockCmd : 3; // Bits= 3 + + // $0 = NO_ACTION + // $1 = UNLOCK + // $2 = LOCK + // $3 = SECURE_LOCK + // $4 = UNSECURE_LOCK + // 4 : "DoubleLockDisable_Req" + // 3 : "DoubleLock_Req" + // 2 : "SingleLock_Req" + // 1 : "Unlock_Req" + // 0 : "No_Request" + uint8_t BCM_RearRightLockCmd : 3; // Bits= 3 + + // Current command to control movement of FL door + // 2 : "Open door" + // 1 : "Close door" + // 0 : "No action" + uint8_t BCM_FLDoorClose_Req : 2; // Bits= 2 + + // Request of storing or clearing the power tailgate position in memory: + // $0 = No Action + // $1 = Store memory + // $2 = Clear memory + // 2 : "Clear Memory" + // 1 : "Store Position in memory" + // 0 : "No Request" + uint8_t PTG_MemorySetRequest : 2; // Bits= 2 + + // State of vehicle side doors and trunk locks: locked or unlocked + // 1 : "Vehicle locked" + // 0 : "Vehicle unlocked" + uint8_t VehicleLockState : 1; // Bits= 1 + + // State of FL door Only for ESC. + // 3 : "Fault" + // 2 : "Door Opened" + // 1 : "Door Closed" + // 0 : "Reserved" + uint8_t BCM_DoorAjarState_FL : 2; // Bits= 2 + + // The signal only for active safety system + // 3 : "Fault" + // 2 : "Door Opened" + // 1 : "Door Closed" + // 0 : "Reserved" + uint8_t BCM_DoorAjarState_FR : 2; // Bits= 2 + + // State of RL door (legacy signal) + // 3 : "Fault" + // 2 : "Door Opened" + // 1 : "Door Closed" + // 0 : "Reserved" + uint8_t BCM_DoorAjarState_RL : 2; // Bits= 2 + + // State of RR door (legacy signal + // 3 : "Fault" + // 2 : "Door Opened" + // 1 : "Door Closed" + // 0 : "Reserved" + uint8_t BCM_DoorAjarState_RR : 2; // Bits= 2 + + // Vehicle secure locking status + // 1 : "Double lock active" + // 0 : "Double lock inactive" + uint8_t BCM_VehDoubleLock_Stat : 1; // Bits= 1 + + // Fuel (gasoline or hydrogen) and high-voltage lid unlock command + // 1 : "Unlock fuel lid" + // 0 : "No Action" + uint8_t BCM_FuelLidUnlock_Req : 1; // Bits= 1 + + // HV lid open status + // 1 : "HV lid opened" + // 0 : "HV lid closed" + uint8_t BCM_HVlid_Stat : 1; // Bits= 1 + + // Command to control RR door opening/ closing + // 2 : "Open door" + // 1 : "Close door" + // 0 : "No action" + uint8_t BCM_RRDoorClose_Req : 2; // Bits= 2 + + // The BCM shall command to Close the windows, when user request is detect. + // 1 : "Windows Closing command" + // 0 : "No Command" + uint8_t BCM_WindowsClose_Cmd : 1; // Bits= 1 + + // Current command to control movement of FR door + // 2 : "Open door" + // 1 : "Close door" + // 0 : "No action" + uint8_t BCM_FRDoorClose_Req : 2; // Bits= 2 + + // Current status of hood + // 3 : "Sensor error" + // 2 : "Hood closed" + // 1 : "Hood opened" + // 0 : "Reserved" + uint8_t BCM_HoodOpen_Stat : 2; // Bits= 2 + + // State of Panic Mode activation + // 1 : "Panic Mode Active" + // 0 : "Panic Mode Inactive" + uint8_t BCM_PanicAlertActive : 1; // Bits= 1 + + // Command to control RL door opening/ closing + // 2 : "Open door" + // 1 : "Close door" + // 0 : "No action" + uint8_t BCM_RLDoorClose_Req : 2; // Bits= 2 + + // Indicate a rear wiper wipe request + // 1 : "Requested" + // 0 : "No requested" + uint8_t BCM_RearWiperWipe_Req : 1; // Bits= 1 + + // Disabling alarm system + // 1 : "Alarm system disabled" + // 0 : "Alarm system enabled" + uint8_t BCM_AlarmOFF_Stat : 1; // Bits= 1 + + // State of movement sensor actvation + // 1 : "Sensor inactive" + // 0 : "Sensor active" + uint8_t BCM_MovementSensOFF_Stat : 1; // Bits= 1 + + // Door movement system status + // 1 : "Door movement system disabled" + // 0 : "Door movement system enabled" + uint8_t BCM_DoorMovDis_Stat : 1; // Bits= 1 + + // Indicates if at least one alarm reason active or not + // 1 : "Request_Active" + // 0 : "No_Request" + uint8_t BCM_Alarm_Req : 1; // Bits= 1 + + // Reason of vehicle alarm function actuation + // 10 : "Hit detected" + // 9 : "Towing detected" + // 8 : "Hood open" + // 7 : "Intrusion level 2 requested" + // 6 : "Intrusion level 1 requested" + // 5 : "TrunkLid_Open" + // 4 : "RR door open" + // 3 : "RL door open" + // 2 : "FR door open" + // 1 : "FL door open" + // 0 : "No_Reasons" + uint8_t BCM_Alarm_Reason : 4; // Bits= 4 + + // Command to control exterior door handle lights + // 1 : "Requested" + // 0 : "No requested" + uint8_t BCM_DoorHandleLight_Req : 1; // Bits= 1 + + // The BCM shall command to Open the windows, when user request is detect. + // 1 : "Windows Opening requested" + // 0 : "Not requested" + uint8_t BCM_WindowsOpen_Req : 1; // Bits= 1 + +#else + + // Reason of vehicle lock state + // 11 : "Locked by Re-Lock" + // 10 : "Locked drive away" + // 9 : "Locked Pre-Crash" + // 8 : "Locked Internal" + // 7 : "Locked External" + // 6 : "Unlocked by Theft Action" + // 5 : "Unlocked Post Crash" + // 4 : "Unlocked Int. Trunk Only" + // 3 : "Unlocked Ext. Trunk Only" + // 2 : "Unlocked From Internal" + // 1 : "Unlocked From External" + // 0 : "Unknown" + uint8_t VehicleLockStateReason; // Bits= 4 + + // $0 = NO_ACTION + // $1 = UNLOCK + // $2 = LOCK + // $3 = SECURE_LOCK + // $4 = UNSECURE_LOCK + // 4 : "DoubleLockDisable_Req" + // 3 : "DoubleLock_Req" + // 2 : "SingleLock_Req" + // 1 : "Unlock_Req" + // 0 : "No_Request" + uint8_t BCM_FrontLeftLockCmd; // Bits= 3 + + // Indicates whether the trunk latch is commanded to be released or not + // 1 : "Trunk lid unlock requested" + // 0 : "Not requested" + uint8_t BCM_TrunkLatchRelease_Req; // Bits= 1 + + // $0 = NO_ACTION + // $1 = UNLOCK + // $2 = LOCK + // $3 = SECURE_LOCK + // $4 = UNSECURE_LOCK + // 4 : "DoubleLockDisable_Req" + // 3 : "DoubleLock_Req" + // 2 : "SingleLock_Req" + // 1 : "Unlock_Req" + // 0 : "No_Request" + uint8_t BCM_FrontRightLockCmd; // Bits= 3 + + // Indicates the power tailgate movement command: + // 0x0 = Stop + // 0x1 = Open + // 0x2 = Close + // 2 : "Close" + // 1 : "Open " + // 0 : "Stop" + uint8_t PTG_MovementCmd; // Bits= 2 + + // $0 = NO_ACTION + // $1 = UNLOCK + // $2 = LOCK + // $3 = SECURE_LOCK + // $4 = UNSECURE_LOCK + // 4 : "DoubleLockDisable_Req" + // 3 : "DoubleLock_Req" + // 2 : "SingleLock_Req" + // 1 : "Unlock_Req" + // 0 : "No_Request" + uint8_t BCM_RearLeftLockCmd; // Bits= 3 + + // $0 = NO_ACTION + // $1 = UNLOCK + // $2 = LOCK + // $3 = SECURE_LOCK + // $4 = UNSECURE_LOCK + // 4 : "DoubleLockDisable_Req" + // 3 : "DoubleLock_Req" + // 2 : "SingleLock_Req" + // 1 : "Unlock_Req" + // 0 : "No_Request" + uint8_t BCM_RearRightLockCmd; // Bits= 3 + + // Current command to control movement of FL door + // 2 : "Open door" + // 1 : "Close door" + // 0 : "No action" + uint8_t BCM_FLDoorClose_Req; // Bits= 2 + + // Request of storing or clearing the power tailgate position in memory: + // $0 = No Action + // $1 = Store memory + // $2 = Clear memory + // 2 : "Clear Memory" + // 1 : "Store Position in memory" + // 0 : "No Request" + uint8_t PTG_MemorySetRequest; // Bits= 2 + + // State of vehicle side doors and trunk locks: locked or unlocked + // 1 : "Vehicle locked" + // 0 : "Vehicle unlocked" + uint8_t VehicleLockState; // Bits= 1 + + // State of FL door Only for ESC. + // 3 : "Fault" + // 2 : "Door Opened" + // 1 : "Door Closed" + // 0 : "Reserved" + uint8_t BCM_DoorAjarState_FL; // Bits= 2 + + // The signal only for active safety system + // 3 : "Fault" + // 2 : "Door Opened" + // 1 : "Door Closed" + // 0 : "Reserved" + uint8_t BCM_DoorAjarState_FR; // Bits= 2 + + // State of RL door (legacy signal) + // 3 : "Fault" + // 2 : "Door Opened" + // 1 : "Door Closed" + // 0 : "Reserved" + uint8_t BCM_DoorAjarState_RL; // Bits= 2 + + // State of RR door (legacy signal + // 3 : "Fault" + // 2 : "Door Opened" + // 1 : "Door Closed" + // 0 : "Reserved" + uint8_t BCM_DoorAjarState_RR; // Bits= 2 + + // Vehicle secure locking status + // 1 : "Double lock active" + // 0 : "Double lock inactive" + uint8_t BCM_VehDoubleLock_Stat; // Bits= 1 + + // Fuel (gasoline or hydrogen) and high-voltage lid unlock command + // 1 : "Unlock fuel lid" + // 0 : "No Action" + uint8_t BCM_FuelLidUnlock_Req; // Bits= 1 + + // HV lid open status + // 1 : "HV lid opened" + // 0 : "HV lid closed" + uint8_t BCM_HVlid_Stat; // Bits= 1 + + // Command to control RR door opening/ closing + // 2 : "Open door" + // 1 : "Close door" + // 0 : "No action" + uint8_t BCM_RRDoorClose_Req; // Bits= 2 + + // The BCM shall command to Close the windows, when user request is detect. + // 1 : "Windows Closing command" + // 0 : "No Command" + uint8_t BCM_WindowsClose_Cmd; // Bits= 1 + + // Current command to control movement of FR door + // 2 : "Open door" + // 1 : "Close door" + // 0 : "No action" + uint8_t BCM_FRDoorClose_Req; // Bits= 2 + + // Current status of hood + // 3 : "Sensor error" + // 2 : "Hood closed" + // 1 : "Hood opened" + // 0 : "Reserved" + uint8_t BCM_HoodOpen_Stat; // Bits= 2 + + // State of Panic Mode activation + // 1 : "Panic Mode Active" + // 0 : "Panic Mode Inactive" + uint8_t BCM_PanicAlertActive; // Bits= 1 + + // Command to control RL door opening/ closing + // 2 : "Open door" + // 1 : "Close door" + // 0 : "No action" + uint8_t BCM_RLDoorClose_Req; // Bits= 2 + + // Indicate a rear wiper wipe request + // 1 : "Requested" + // 0 : "No requested" + uint8_t BCM_RearWiperWipe_Req; // Bits= 1 + + // Disabling alarm system + // 1 : "Alarm system disabled" + // 0 : "Alarm system enabled" + uint8_t BCM_AlarmOFF_Stat; // Bits= 1 + + // State of movement sensor actvation + // 1 : "Sensor inactive" + // 0 : "Sensor active" + uint8_t BCM_MovementSensOFF_Stat; // Bits= 1 + + // Door movement system status + // 1 : "Door movement system disabled" + // 0 : "Door movement system enabled" + uint8_t BCM_DoorMovDis_Stat; // Bits= 1 + + // Indicates if at least one alarm reason active or not + // 1 : "Request_Active" + // 0 : "No_Request" + uint8_t BCM_Alarm_Req; // Bits= 1 + + // Reason of vehicle alarm function actuation + // 10 : "Hit detected" + // 9 : "Towing detected" + // 8 : "Hood open" + // 7 : "Intrusion level 2 requested" + // 6 : "Intrusion level 1 requested" + // 5 : "TrunkLid_Open" + // 4 : "RR door open" + // 3 : "RL door open" + // 2 : "FR door open" + // 1 : "FL door open" + // 0 : "No_Reasons" + uint8_t BCM_Alarm_Reason; // Bits= 4 + + // Command to control exterior door handle lights + // 1 : "Requested" + // 0 : "No requested" + uint8_t BCM_DoorHandleLight_Req; // Bits= 1 + + // The BCM shall command to Open the windows, when user request is detect. + // 1 : "Windows Opening requested" + // 0 : "Not requested" + uint8_t BCM_WindowsOpen_Req; // Bits= 1 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} BCM_Lock_CTR_t; + +// def @HVC_Err_Status_Msg CAN Message (773 0x305) +#define HVC_Err_Status_Msg_IDE (0U) +#define HVC_Err_Status_Msg_DLC (8U) +#define HVC_Err_Status_Msg_CANID (0x305U) +#define HVC_Err_Status_Msg_CYC (100U) +// signal: @HVC_CompSpeed_Val_ro +#define CANDB_HVC_CompSpeed_Val_ro_CovFactor (50) +#define CANDB_HVC_CompSpeed_Val_ro_toS(x) ( (uint8_t) ((x) / (50)) ) +#define CANDB_HVC_CompSpeed_Val_ro_fromS(x) ( ((x) * (50)) ) + +// Value tables for @HVC_Comp_Stat signal + +#ifndef HVC_Comp_Stat_HVC_Err_Status_Msg_COMP_FAULT +#define HVC_Comp_Stat_HVC_Err_Status_Msg_COMP_FAULT (3) +#endif + +#ifndef HVC_Comp_Stat_HVC_Err_Status_Msg_POWER_LIMIT +#define HVC_Comp_Stat_HVC_Err_Status_Msg_POWER_LIMIT (2) +#endif + +#ifndef HVC_Comp_Stat_HVC_Err_Status_Msg_COMP_ON +#define HVC_Comp_Stat_HVC_Err_Status_Msg_COMP_ON (1) +#endif + +#ifndef HVC_Comp_Stat_HVC_Err_Status_Msg_COMP_OFF +#define HVC_Comp_Stat_HVC_Err_Status_Msg_COMP_OFF (0) +#endif + +// signal: @HVC_CompInputV_Val_ro +#define CANDB_HVC_CompInputV_Val_ro_CovFactor (2) +#define CANDB_HVC_CompInputV_Val_ro_toS(x) ( (uint8_t) ((x) / (2)) ) +#define CANDB_HVC_CompInputV_Val_ro_fromS(x) ( ((x) * (2)) ) +// signal: @HVC_CompInputC_Val_ro +#define CANDB_HVC_CompInputC_Val_ro_CovFactor (0.5) +#define CANDB_HVC_CompInputC_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.5)) ) +#define CANDB_HVC_CompInputC_Val_ro_fromS(x) ( (((x) * (0.5)) + (0.0)) ) +// signal: @HVC_CompInvTemp_Val_ro +#define CANDB_HVC_CompInvTemp_Val_ro_CovFactor (1) +#define CANDB_HVC_CompInvTemp_Val_ro_toS(x) ( (uint8_t) ((x) - (-50)) ) +#define CANDB_HVC_CompInvTemp_Val_ro_fromS(x) ( ((x) + (-50)) ) +// signal: @HVC_CompPhaseC_Val_ro +#define CANDB_HVC_CompPhaseC_Val_ro_CovFactor (0.5) +#define CANDB_HVC_CompPhaseC_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.5)) ) +#define CANDB_HVC_CompPhaseC_Val_ro_fromS(x) ( (((x) * (0.5)) + (0.0)) ) + +// Value tables for @HVC_CompUV_Stat signal + +#ifndef HVC_CompUV_Stat_HVC_Err_Status_Msg_True +#define HVC_CompUV_Stat_HVC_Err_Status_Msg_True (1) +#endif + +#ifndef HVC_CompUV_Stat_HVC_Err_Status_Msg_False +#define HVC_CompUV_Stat_HVC_Err_Status_Msg_False (0) +#endif + + +// Value tables for @HVC_CompOV_Stat signal + +#ifndef HVC_CompOV_Stat_HVC_Err_Status_Msg_True +#define HVC_CompOV_Stat_HVC_Err_Status_Msg_True (1) +#endif + +#ifndef HVC_CompOV_Stat_HVC_Err_Status_Msg_False +#define HVC_CompOV_Stat_HVC_Err_Status_Msg_False (0) +#endif + + +// Value tables for @HVC_CompOvHeat_Stat signal + +#ifndef HVC_CompOvHeat_Stat_HVC_Err_Status_Msg_True +#define HVC_CompOvHeat_Stat_HVC_Err_Status_Msg_True (1) +#endif + +#ifndef HVC_CompOvHeat_Stat_HVC_Err_Status_Msg_False +#define HVC_CompOvHeat_Stat_HVC_Err_Status_Msg_False (0) +#endif + + +// Value tables for @HVC_CompOvTorque_Stat signal + +#ifndef HVC_CompOvTorque_Stat_HVC_Err_Status_Msg_True +#define HVC_CompOvTorque_Stat_HVC_Err_Status_Msg_True (1) +#endif + +#ifndef HVC_CompOvTorque_Stat_HVC_Err_Status_Msg_False +#define HVC_CompOvTorque_Stat_HVC_Err_Status_Msg_False (0) +#endif + + +// Value tables for @HVC_CompLowVoltErr_Stat signal + +#ifndef HVC_CompLowVoltErr_Stat_HVC_Err_Status_Msg_True +#define HVC_CompLowVoltErr_Stat_HVC_Err_Status_Msg_True (1) +#endif + +#ifndef HVC_CompLowVoltErr_Stat_HVC_Err_Status_Msg_False +#define HVC_CompLowVoltErr_Stat_HVC_Err_Status_Msg_False (0) +#endif + + +// Value tables for @HVC_CompComErr_Stat signal + +#ifndef HVC_CompComErr_Stat_HVC_Err_Status_Msg_True +#define HVC_CompComErr_Stat_HVC_Err_Status_Msg_True (1) +#endif + +#ifndef HVC_CompComErr_Stat_HVC_Err_Status_Msg_False +#define HVC_CompComErr_Stat_HVC_Err_Status_Msg_False (0) +#endif + + +// Value tables for @HVC_CompTempSensErr_Stat signal + +#ifndef HVC_CompTempSensErr_Stat_HVC_Err_Status_Msg_True +#define HVC_CompTempSensErr_Stat_HVC_Err_Status_Msg_True (1) +#endif + +#ifndef HVC_CompTempSensErr_Stat_HVC_Err_Status_Msg_False +#define HVC_CompTempSensErr_Stat_HVC_Err_Status_Msg_False (0) +#endif + + +// Value tables for @HVC_CompCurrSensErr_Stat signal + +#ifndef HVC_CompCurrSensErr_Stat_HVC_Err_Status_Msg_True +#define HVC_CompCurrSensErr_Stat_HVC_Err_Status_Msg_True (1) +#endif + +#ifndef HVC_CompCurrSensErr_Stat_HVC_Err_Status_Msg_False +#define HVC_CompCurrSensErr_Stat_HVC_Err_Status_Msg_False (0) +#endif + + +// Value tables for @HVC_CompCurrShortCirc_Stat signal + +#ifndef HVC_CompCurrShortCirc_Stat_HVC_Err_Status_Msg_True +#define HVC_CompCurrShortCirc_Stat_HVC_Err_Status_Msg_True (1) +#endif + +#ifndef HVC_CompCurrShortCirc_Stat_HVC_Err_Status_Msg_False +#define HVC_CompCurrShortCirc_Stat_HVC_Err_Status_Msg_False (0) +#endif + + +// Value tables for @HVC_CompInPowSupply_Stat signal + +#ifndef HVC_CompInPowSupply_Stat_HVC_Err_Status_Msg_True +#define HVC_CompInPowSupply_Stat_HVC_Err_Status_Msg_True (1) +#endif + +#ifndef HVC_CompInPowSupply_Stat_HVC_Err_Status_Msg_False +#define HVC_CompInPowSupply_Stat_HVC_Err_Status_Msg_False (0) +#endif + + +// Value tables for @HVC_CompTorqueStallErr_Stat signal + +#ifndef HVC_CompTorqueStallErr_Stat_HVC_Err_Status_Msg_True +#define HVC_CompTorqueStallErr_Stat_HVC_Err_Status_Msg_True (1) +#endif + +#ifndef HVC_CompTorqueStallErr_Stat_HVC_Err_Status_Msg_False +#define HVC_CompTorqueStallErr_Stat_HVC_Err_Status_Msg_False (0) +#endif + + +// Value tables for @HVC_CompVoltSensErr_Stat signal + +#ifndef HVC_CompVoltSensErr_Stat_HVC_Err_Status_Msg_True +#define HVC_CompVoltSensErr_Stat_HVC_Err_Status_Msg_True (1) +#endif + +#ifndef HVC_CompVoltSensErr_Stat_HVC_Err_Status_Msg_False +#define HVC_CompVoltSensErr_Stat_HVC_Err_Status_Msg_False (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // High voltage compressor speed in revolutions per minute + // $FF = Signal Not Available + uint8_t HVC_CompSpeed_Val_ro; // Bits= 8 Factor= 50 Unit:'rpm' + +#ifdef CANDB_USE_SIGFLOAT + uint16_t HVC_CompSpeed_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // High voltage compressor status: + // $0 = Compressor off + // $1 = Compressor on + // $2 = Power limit + // $3 = Compressor failure / Signal Not Available + // 3 : "COMP_FAULT" + // 2 : "POWER_LIMIT" + // 1 : "COMP_ON" + // 0 : "COMP_OFF" + uint8_t HVC_Comp_Stat : 2; // Bits= 2 + + // Reserved space in the HVC_State message: 6 bits + uint8_t HVC_Reserved01 : 6; // Bits= 6 + + // High voltage compressor input voltage: + // 0xFF = Fault/SNA + uint8_t HVC_CompInputV_Val_ro; // Bits= 8 Factor= 2 Unit:'V' + +#ifdef CANDB_USE_SIGFLOAT + uint16_t HVC_CompInputV_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // High voltage compressor input current: + // 0xFF = Fault/SNA + uint8_t HVC_CompInputC_Val_ro; // Bits= 8 Factor= 0.5 Unit:'A' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t HVC_CompInputC_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // High voltage compressor inverter temperature: + // 0xFF = Fault/SNA + uint8_t HVC_CompInvTemp_Val_ro; // Bits= 8 Offset= -50 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + int16_t HVC_CompInvTemp_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // High voltage compressor motor phase current: + // 0xFF = Fault/SNA + uint8_t HVC_CompPhaseC_Val_ro; // Bits= 8 Factor= 0.5 Unit:'A' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t HVC_CompPhaseC_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // High voltage compressor under voltage detected + // 1 : "True" + // 0 : "False" + uint8_t HVC_CompUV_Stat : 1; // Bits= 1 + + // High voltage compressor over voltage detected + // 1 : "True" + // 0 : "False" + uint8_t HVC_CompOV_Stat : 1; // Bits= 1 + + // High voltage compressor over heat detected + // 1 : "True" + // 0 : "False" + uint8_t HVC_CompOvHeat_Stat : 1; // Bits= 1 + + // High voltage compressor over torque detected. (overload) + // 1 : "True" + // 0 : "False" + uint8_t HVC_CompOvTorque_Stat : 1; // Bits= 1 + + // High voltage compressor low voltage error detected + // 1 : "True" + // 0 : "False" + uint8_t HVC_CompLowVoltErr_Stat : 1; // Bits= 1 + + // High voltage compressor communication error detected. + // 1 : "True" + // 0 : "False" + uint8_t HVC_CompComErr_Stat : 1; // Bits= 1 + + // Reserved space in the HVC_State message: 2 bits + uint8_t HVC_Reserved02 : 2; // Bits= 2 + + // High voltage compressor temperature sensor error detected. + // 1 : "True" + // 0 : "False" + uint8_t HVC_CompTempSensErr_Stat : 1; // Bits= 1 + + // High voltage compressor current sensor error detected. + // 1 : "True" + // 0 : "False" + uint8_t HVC_CompCurrSensErr_Stat : 1; // Bits= 1 + + // High voltage compressor current short-circuit detected. + // 1 : "True" + // 0 : "False" + uint8_t HVC_CompCurrShortCirc_Stat : 1; // Bits= 1 + + // High voltage compressor in power supply detected. + // 1 : "True" + // 0 : "False" + uint8_t HVC_CompInPowSupply_Stat : 1; // Bits= 1 + + // High voltage compressor torque stall detected. (overload (stall)) + // 1 : "True" + // 0 : "False" + uint8_t HVC_CompTorqueStallErr_Stat : 1; // Bits= 1 + + // High voltage compressor voltage sensor error detected. + // 1 : "True" + // 0 : "False" + uint8_t HVC_CompVoltSensErr_Stat : 1; // Bits= 1 + + // Reserved space in the HVC_State message: 2 bits + uint8_t HVC_Reserved03 : 2; // Bits= 2 + +#else + + // High voltage compressor speed in revolutions per minute + // $FF = Signal Not Available + uint8_t HVC_CompSpeed_Val_ro; // Bits= 8 Factor= 50 Unit:'rpm' + +#ifdef CANDB_USE_SIGFLOAT + uint16_t HVC_CompSpeed_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // High voltage compressor status: + // $0 = Compressor off + // $1 = Compressor on + // $2 = Power limit + // $3 = Compressor failure / Signal Not Available + // 3 : "COMP_FAULT" + // 2 : "POWER_LIMIT" + // 1 : "COMP_ON" + // 0 : "COMP_OFF" + uint8_t HVC_Comp_Stat; // Bits= 2 + + // Reserved space in the HVC_State message: 6 bits + uint8_t HVC_Reserved01; // Bits= 6 + + // High voltage compressor input voltage: + // 0xFF = Fault/SNA + uint8_t HVC_CompInputV_Val_ro; // Bits= 8 Factor= 2 Unit:'V' + +#ifdef CANDB_USE_SIGFLOAT + uint16_t HVC_CompInputV_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // High voltage compressor input current: + // 0xFF = Fault/SNA + uint8_t HVC_CompInputC_Val_ro; // Bits= 8 Factor= 0.5 Unit:'A' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t HVC_CompInputC_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // High voltage compressor inverter temperature: + // 0xFF = Fault/SNA + uint8_t HVC_CompInvTemp_Val_ro; // Bits= 8 Offset= -50 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + int16_t HVC_CompInvTemp_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // High voltage compressor motor phase current: + // 0xFF = Fault/SNA + uint8_t HVC_CompPhaseC_Val_ro; // Bits= 8 Factor= 0.5 Unit:'A' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t HVC_CompPhaseC_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // High voltage compressor under voltage detected + // 1 : "True" + // 0 : "False" + uint8_t HVC_CompUV_Stat; // Bits= 1 + + // High voltage compressor over voltage detected + // 1 : "True" + // 0 : "False" + uint8_t HVC_CompOV_Stat; // Bits= 1 + + // High voltage compressor over heat detected + // 1 : "True" + // 0 : "False" + uint8_t HVC_CompOvHeat_Stat; // Bits= 1 + + // High voltage compressor over torque detected. (overload) + // 1 : "True" + // 0 : "False" + uint8_t HVC_CompOvTorque_Stat; // Bits= 1 + + // High voltage compressor low voltage error detected + // 1 : "True" + // 0 : "False" + uint8_t HVC_CompLowVoltErr_Stat; // Bits= 1 + + // High voltage compressor communication error detected. + // 1 : "True" + // 0 : "False" + uint8_t HVC_CompComErr_Stat; // Bits= 1 + + // Reserved space in the HVC_State message: 2 bits + uint8_t HVC_Reserved02; // Bits= 2 + + // High voltage compressor temperature sensor error detected. + // 1 : "True" + // 0 : "False" + uint8_t HVC_CompTempSensErr_Stat; // Bits= 1 + + // High voltage compressor current sensor error detected. + // 1 : "True" + // 0 : "False" + uint8_t HVC_CompCurrSensErr_Stat; // Bits= 1 + + // High voltage compressor current short-circuit detected. + // 1 : "True" + // 0 : "False" + uint8_t HVC_CompCurrShortCirc_Stat; // Bits= 1 + + // High voltage compressor in power supply detected. + // 1 : "True" + // 0 : "False" + uint8_t HVC_CompInPowSupply_Stat; // Bits= 1 + + // High voltage compressor torque stall detected. (overload (stall)) + // 1 : "True" + // 0 : "False" + uint8_t HVC_CompTorqueStallErr_Stat; // Bits= 1 + + // High voltage compressor voltage sensor error detected. + // 1 : "True" + // 0 : "False" + uint8_t HVC_CompVoltSensErr_Stat; // Bits= 1 + + // Reserved space in the HVC_State message: 2 bits + uint8_t HVC_Reserved03; // Bits= 2 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} HVC_Err_Status_Msg_t; + +// def @BCM_DCDC12_CNTRL CAN Message (776 0x308) +#define BCM_DCDC12_CNTRL_IDE (0U) +#define BCM_DCDC12_CNTRL_DLC (8U) +#define BCM_DCDC12_CNTRL_CANID (0x308U) +#define BCM_DCDC12_CNTRL_CYC (10U) +// signal: @BCM_DCDC1248_CurrLim12_ro +#define CANDB_BCM_DCDC1248_CurrLim12_ro_CovFactor (1) +#define CANDB_BCM_DCDC1248_CurrLim12_ro_toS(x) ( (uint16_t) ((x) - (-255)) ) +#define CANDB_BCM_DCDC1248_CurrLim12_ro_fromS(x) ( ((x) + (-255)) ) +// signal: @BCM_DCDC1248_DesVolt12_ro +#define CANDB_BCM_DCDC1248_DesVolt12_ro_CovFactor (0.1) +#define CANDB_BCM_DCDC1248_DesVolt12_ro_toS(x) ( (uint16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_BCM_DCDC1248_DesVolt12_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @BCM_Volt_DCDC12_Req_ro +#define CANDB_BCM_Volt_DCDC12_Req_ro_CovFactor (0.125) +#define CANDB_BCM_Volt_DCDC12_Req_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.125)) ) +#define CANDB_BCM_Volt_DCDC12_Req_ro_fromS(x) ( (((x) * (0.125)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t BCM_DCDC1248_01_CS; // Bits= 8 + + // Rolling Counter [0 - 15] + uint8_t BCM_DCDC1248_01_RC : 4; // Bits= 4 + + // Current limit for DCDC 12/48V (48 ->12V) convertor + uint16_t BCM_DCDC1248_CurrLim12_ro; // Bits= 9 Offset= -255 Unit:'A' + +#ifdef CANDB_USE_SIGFLOAT + int16_t BCM_DCDC1248_CurrLim12_phys; +#endif // CANDB_USE_SIGFLOAT + + // Target voltage level for DCDC 12/48V (48 ->12V) convertor + uint16_t BCM_DCDC1248_DesVolt12_ro; // Bits=10 Factor= 0.1 Unit:'V' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_DCDC1248_DesVolt12_phys; +#endif // CANDB_USE_SIGFLOAT + + // Target voltage level for DCDC12V (800 ->12V) convertor + uint8_t BCM_Volt_DCDC12_Req_ro; // Bits= 8 Factor= 0.125 Unit:'V' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_Volt_DCDC12_Req_phys; +#endif // CANDB_USE_SIGFLOAT + + // Current limit for DCDC12V (800 ->12V) convertor + uint8_t BCM_CurrLim_DCDC12; // Bits= 8 Unit:'A' + +#else + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t BCM_DCDC1248_01_CS; // Bits= 8 + + // Rolling Counter [0 - 15] + uint8_t BCM_DCDC1248_01_RC; // Bits= 4 + + // Current limit for DCDC 12/48V (48 ->12V) convertor + uint16_t BCM_DCDC1248_CurrLim12_ro; // Bits= 9 Offset= -255 Unit:'A' + +#ifdef CANDB_USE_SIGFLOAT + int16_t BCM_DCDC1248_CurrLim12_phys; +#endif // CANDB_USE_SIGFLOAT + + // Target voltage level for DCDC 12/48V (48 ->12V) convertor + uint16_t BCM_DCDC1248_DesVolt12_ro; // Bits=10 Factor= 0.1 Unit:'V' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_DCDC1248_DesVolt12_phys; +#endif // CANDB_USE_SIGFLOAT + + // Target voltage level for DCDC12V (800 ->12V) convertor + uint8_t BCM_Volt_DCDC12_Req_ro; // Bits= 8 Factor= 0.125 Unit:'V' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_Volt_DCDC12_Req_phys; +#endif // CANDB_USE_SIGFLOAT + + // Current limit for DCDC12V (800 ->12V) convertor + uint8_t BCM_CurrLim_DCDC12; // Bits= 8 Unit:'A' + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} BCM_DCDC12_CNTRL_t; + +// def @CCU_HVC_Req_Msg CAN Message (784 0x310) +#define CCU_HVC_Req_Msg_IDE (0U) +#define CCU_HVC_Req_Msg_DLC (3U) +#define CCU_HVC_Req_Msg_CANID (0x310U) +#define CCU_HVC_Req_Msg_CYC (200U) +// signal: @CCU_eCompSpeedReq_Val_ro +#define CANDB_CCU_eCompSpeedReq_Val_ro_CovFactor (50) +#define CANDB_CCU_eCompSpeedReq_Val_ro_toS(x) ( (uint8_t) ((x) / (50)) ) +#define CANDB_CCU_eCompSpeedReq_Val_ro_fromS(x) ( ((x) * (50)) ) + +// Value tables for @CCU_eCompReq_Stat signal + +#ifndef CCU_eCompReq_Stat_CCU_HVC_Req_Msg_Request +#define CCU_eCompReq_Stat_CCU_HVC_Req_Msg_Request (1) +#endif + +#ifndef CCU_eCompReq_Stat_CCU_HVC_Req_Msg_Stop_request +#define CCU_eCompReq_Stat_CCU_HVC_Req_Msg_Stop_request (0) +#endif + + +// Value tables for @CCU_LowTempValve_Req signal + +#ifndef CCU_LowTempValve_Req_CCU_HVC_Req_Msg_Open_Valve_request +#define CCU_LowTempValve_Req_CCU_HVC_Req_Msg_Open_Valve_request (2) +#endif + +#ifndef CCU_LowTempValve_Req_CCU_HVC_Req_Msg_Close_Valve_request +#define CCU_LowTempValve_Req_CCU_HVC_Req_Msg_Close_Valve_request (1) +#endif + +#ifndef CCU_LowTempValve_Req_CCU_HVC_Req_Msg_No_request +#define CCU_LowTempValve_Req_CCU_HVC_Req_Msg_No_request (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Compressor target speed: + // 0xFF = Fault value + uint8_t CCU_eCompSpeedReq_Val_ro; // Bits= 8 Factor= 50 Unit:'rpm' + +#ifdef CANDB_USE_SIGFLOAT + uint16_t CCU_eCompSpeedReq_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Request to activate air conditioner compressor + // 1 : "Request" + // 0 : "Stop request" + uint8_t CCU_eCompReq_Stat : 1; // Bits= 1 + + // request to EMS for closing the low temperature circuit valve + // 2 : "Open Valve request" + // 1 : "Close Valve request" + // 0 : "No request" + uint8_t CCU_LowTempValve_Req : 2; // Bits= 2 + + // Rolling Counter [0 - 15] + uint8_t CCU_HVC_Req_RC : 4; // Bits= 4 + + // Checksum XOR8 of the data field this message + // Checksum computed as per XOR algorithm: + // Byte 1 XOR byte 2 .... XOR byte n-1. (n = packet length.) + uint8_t CCU_HVC_Req_CS; // Bits= 8 + +#else + + // Compressor target speed: + // 0xFF = Fault value + uint8_t CCU_eCompSpeedReq_Val_ro; // Bits= 8 Factor= 50 Unit:'rpm' + +#ifdef CANDB_USE_SIGFLOAT + uint16_t CCU_eCompSpeedReq_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Request to activate air conditioner compressor + // 1 : "Request" + // 0 : "Stop request" + uint8_t CCU_eCompReq_Stat; // Bits= 1 + + // request to EMS for closing the low temperature circuit valve + // 2 : "Open Valve request" + // 1 : "Close Valve request" + // 0 : "No request" + uint8_t CCU_LowTempValve_Req; // Bits= 2 + + // Rolling Counter [0 - 15] + uint8_t CCU_HVC_Req_RC; // Bits= 4 + + // Checksum XOR8 of the data field this message + // Checksum computed as per XOR algorithm: + // Byte 1 XOR byte 2 .... XOR byte n-1. (n = packet length.) + uint8_t CCU_HVC_Req_CS; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} CCU_HVC_Req_Msg_t; + +// def @CCU_Stat1 CAN Message (785 0x311) +#define CCU_Stat1_IDE (0U) +#define CCU_Stat1_DLC (8U) +#define CCU_Stat1_CANID (0x311U) +#define CCU_Stat1_CYC (100U) + +// Value tables for @CCU_ModeFL_Stat signal + +#ifndef CCU_ModeFL_Stat_CCU_Stat1_Semiauto_mode_is_active +#define CCU_ModeFL_Stat_CCU_Stat1_Semiauto_mode_is_active (2) +#endif + +#ifndef CCU_ModeFL_Stat_CCU_Stat1_Auto_mode_is_active +#define CCU_ModeFL_Stat_CCU_Stat1_Auto_mode_is_active (1) +#endif + +#ifndef CCU_ModeFL_Stat_CCU_Stat1_Manual_mode_is_active +#define CCU_ModeFL_Stat_CCU_Stat1_Manual_mode_is_active (0) +#endif + + +// Value tables for @CCU_ModeFR_Stat signal + +#ifndef CCU_ModeFR_Stat_CCU_Stat1_Semiauto_mode_is_active +#define CCU_ModeFR_Stat_CCU_Stat1_Semiauto_mode_is_active (2) +#endif + +#ifndef CCU_ModeFR_Stat_CCU_Stat1_Auto_mode_is_active +#define CCU_ModeFR_Stat_CCU_Stat1_Auto_mode_is_active (1) +#endif + +#ifndef CCU_ModeFR_Stat_CCU_Stat1_Manual_mode_is_active +#define CCU_ModeFR_Stat_CCU_Stat1_Manual_mode_is_active (0) +#endif + + +// Value tables for @CCU_ModeRL_Stat signal + +#ifndef CCU_ModeRL_Stat_CCU_Stat1_Semiauto_mode_is_active +#define CCU_ModeRL_Stat_CCU_Stat1_Semiauto_mode_is_active (2) +#endif + +#ifndef CCU_ModeRL_Stat_CCU_Stat1_Auto_mode_is_active +#define CCU_ModeRL_Stat_CCU_Stat1_Auto_mode_is_active (1) +#endif + +#ifndef CCU_ModeRL_Stat_CCU_Stat1_Manual_mode_is_active +#define CCU_ModeRL_Stat_CCU_Stat1_Manual_mode_is_active (0) +#endif + + +// Value tables for @CCU_ModeRR_Stat signal + +#ifndef CCU_ModeRR_Stat_CCU_Stat1_Semiauto_mode_is_active +#define CCU_ModeRR_Stat_CCU_Stat1_Semiauto_mode_is_active (2) +#endif + +#ifndef CCU_ModeRR_Stat_CCU_Stat1_Auto_mode_is_active +#define CCU_ModeRR_Stat_CCU_Stat1_Auto_mode_is_active (1) +#endif + +#ifndef CCU_ModeRR_Stat_CCU_Stat1_Manual_mode_is_active +#define CCU_ModeRR_Stat_CCU_Stat1_Manual_mode_is_active (0) +#endif + + +// Value tables for @CCU_AutoModeFL_Stat signal + +#ifndef CCU_AutoModeFL_Stat_CCU_Stat1_Auto_mode_5_is_active +#define CCU_AutoModeFL_Stat_CCU_Stat1_Auto_mode_5_is_active (5) +#endif + +#ifndef CCU_AutoModeFL_Stat_CCU_Stat1_Auto_mode_4_is_active +#define CCU_AutoModeFL_Stat_CCU_Stat1_Auto_mode_4_is_active (4) +#endif + +#ifndef CCU_AutoModeFL_Stat_CCU_Stat1_Auto_mode_3_is_active +#define CCU_AutoModeFL_Stat_CCU_Stat1_Auto_mode_3_is_active (3) +#endif + +#ifndef CCU_AutoModeFL_Stat_CCU_Stat1_Auto_mode_2_is_active +#define CCU_AutoModeFL_Stat_CCU_Stat1_Auto_mode_2_is_active (2) +#endif + +#ifndef CCU_AutoModeFL_Stat_CCU_Stat1_Auto_mode_1_is_active +#define CCU_AutoModeFL_Stat_CCU_Stat1_Auto_mode_1_is_active (1) +#endif + +#ifndef CCU_AutoModeFL_Stat_CCU_Stat1_Auto_mode_is_inactive +#define CCU_AutoModeFL_Stat_CCU_Stat1_Auto_mode_is_inactive (0) +#endif + + +// Value tables for @CCU_AutoModeFR_Stat signal + +#ifndef CCU_AutoModeFR_Stat_CCU_Stat1_Auto_mode_5_is_active +#define CCU_AutoModeFR_Stat_CCU_Stat1_Auto_mode_5_is_active (5) +#endif + +#ifndef CCU_AutoModeFR_Stat_CCU_Stat1_Auto_mode_4_is_active +#define CCU_AutoModeFR_Stat_CCU_Stat1_Auto_mode_4_is_active (4) +#endif + +#ifndef CCU_AutoModeFR_Stat_CCU_Stat1_Auto_mode_3_is_active +#define CCU_AutoModeFR_Stat_CCU_Stat1_Auto_mode_3_is_active (3) +#endif + +#ifndef CCU_AutoModeFR_Stat_CCU_Stat1_Auto_mode_2_is_active +#define CCU_AutoModeFR_Stat_CCU_Stat1_Auto_mode_2_is_active (2) +#endif + +#ifndef CCU_AutoModeFR_Stat_CCU_Stat1_Auto_mode_1_is_active +#define CCU_AutoModeFR_Stat_CCU_Stat1_Auto_mode_1_is_active (1) +#endif + +#ifndef CCU_AutoModeFR_Stat_CCU_Stat1_Auto_mode_is_inactive +#define CCU_AutoModeFR_Stat_CCU_Stat1_Auto_mode_is_inactive (0) +#endif + + +// Value tables for @CCU_AirDirectionRL_Face_Stat signal + +#ifndef CCU_AirDirectionRL_Face_Stat_CCU_Stat1_Active +#define CCU_AirDirectionRL_Face_Stat_CCU_Stat1_Active (1) +#endif + +#ifndef CCU_AirDirectionRL_Face_Stat_CCU_Stat1_Inactive +#define CCU_AirDirectionRL_Face_Stat_CCU_Stat1_Inactive (0) +#endif + + +// Value tables for @CCU_AirDirectionRL_Foot_Stat signal + +#ifndef CCU_AirDirectionRL_Foot_Stat_CCU_Stat1_Active +#define CCU_AirDirectionRL_Foot_Stat_CCU_Stat1_Active (1) +#endif + +#ifndef CCU_AirDirectionRL_Foot_Stat_CCU_Stat1_Inactive +#define CCU_AirDirectionRL_Foot_Stat_CCU_Stat1_Inactive (0) +#endif + + +// Value tables for @CCU_AutoModeRL_Stat signal + +#ifndef CCU_AutoModeRL_Stat_CCU_Stat1_Auto_mode_5_is_active +#define CCU_AutoModeRL_Stat_CCU_Stat1_Auto_mode_5_is_active (5) +#endif + +#ifndef CCU_AutoModeRL_Stat_CCU_Stat1_Auto_mode_4_is_active +#define CCU_AutoModeRL_Stat_CCU_Stat1_Auto_mode_4_is_active (4) +#endif + +#ifndef CCU_AutoModeRL_Stat_CCU_Stat1_Auto_mode_3_is_active +#define CCU_AutoModeRL_Stat_CCU_Stat1_Auto_mode_3_is_active (3) +#endif + +#ifndef CCU_AutoModeRL_Stat_CCU_Stat1_Auto_mode_2_is_active +#define CCU_AutoModeRL_Stat_CCU_Stat1_Auto_mode_2_is_active (2) +#endif + +#ifndef CCU_AutoModeRL_Stat_CCU_Stat1_Auto_mode_1_is_active +#define CCU_AutoModeRL_Stat_CCU_Stat1_Auto_mode_1_is_active (1) +#endif + +#ifndef CCU_AutoModeRL_Stat_CCU_Stat1_Auto_mode_is_inactive +#define CCU_AutoModeRL_Stat_CCU_Stat1_Auto_mode_is_inactive (0) +#endif + + +// Value tables for @CCU_AutoModeRR_Stat signal + +#ifndef CCU_AutoModeRR_Stat_CCU_Stat1_Auto_mode_5_is_active +#define CCU_AutoModeRR_Stat_CCU_Stat1_Auto_mode_5_is_active (5) +#endif + +#ifndef CCU_AutoModeRR_Stat_CCU_Stat1_Auto_mode_4_is_active +#define CCU_AutoModeRR_Stat_CCU_Stat1_Auto_mode_4_is_active (4) +#endif + +#ifndef CCU_AutoModeRR_Stat_CCU_Stat1_Auto_mode_3_is_active +#define CCU_AutoModeRR_Stat_CCU_Stat1_Auto_mode_3_is_active (3) +#endif + +#ifndef CCU_AutoModeRR_Stat_CCU_Stat1_Auto_mode_2_is_active +#define CCU_AutoModeRR_Stat_CCU_Stat1_Auto_mode_2_is_active (2) +#endif + +#ifndef CCU_AutoModeRR_Stat_CCU_Stat1_Auto_mode_1_is_active +#define CCU_AutoModeRR_Stat_CCU_Stat1_Auto_mode_1_is_active (1) +#endif + +#ifndef CCU_AutoModeRR_Stat_CCU_Stat1_Auto_mode_is_inactive +#define CCU_AutoModeRR_Stat_CCU_Stat1_Auto_mode_is_inactive (0) +#endif + + +// Value tables for @CCU_AirDirectionRR_Face_Stat signal + +#ifndef CCU_AirDirectionRR_Face_Stat_CCU_Stat1_Active +#define CCU_AirDirectionRR_Face_Stat_CCU_Stat1_Active (1) +#endif + +#ifndef CCU_AirDirectionRR_Face_Stat_CCU_Stat1_Inactive +#define CCU_AirDirectionRR_Face_Stat_CCU_Stat1_Inactive (0) +#endif + + +// Value tables for @CCU_AirDirectionRR_Foot_Stat signal + +#ifndef CCU_AirDirectionRR_Foot_Stat_CCU_Stat1_Active +#define CCU_AirDirectionRR_Foot_Stat_CCU_Stat1_Active (1) +#endif + +#ifndef CCU_AirDirectionRR_Foot_Stat_CCU_Stat1_Inactive +#define CCU_AirDirectionRR_Foot_Stat_CCU_Stat1_Inactive (0) +#endif + + +// Value tables for @CCU_AirDirectionFL_Def_Stat signal + +#ifndef CCU_AirDirectionFL_Def_Stat_CCU_Stat1_Active +#define CCU_AirDirectionFL_Def_Stat_CCU_Stat1_Active (1) +#endif + +#ifndef CCU_AirDirectionFL_Def_Stat_CCU_Stat1_Inactive +#define CCU_AirDirectionFL_Def_Stat_CCU_Stat1_Inactive (0) +#endif + + +// Value tables for @CCU_AirDirectionFL_Face_Stat signal + +#ifndef CCU_AirDirectionFL_Face_Stat_CCU_Stat1_Active +#define CCU_AirDirectionFL_Face_Stat_CCU_Stat1_Active (1) +#endif + +#ifndef CCU_AirDirectionFL_Face_Stat_CCU_Stat1_Inactive +#define CCU_AirDirectionFL_Face_Stat_CCU_Stat1_Inactive (0) +#endif + + +// Value tables for @CCU_AirDirectionFL_Foot_Stat signal + +#ifndef CCU_AirDirectionFL_Foot_Stat_CCU_Stat1_Active +#define CCU_AirDirectionFL_Foot_Stat_CCU_Stat1_Active (1) +#endif + +#ifndef CCU_AirDirectionFL_Foot_Stat_CCU_Stat1_Inactive +#define CCU_AirDirectionFL_Foot_Stat_CCU_Stat1_Inactive (0) +#endif + + +// Value tables for @CCU_AirDirectionFR_Def_Stat signal + +#ifndef CCU_AirDirectionFR_Def_Stat_CCU_Stat1_Active +#define CCU_AirDirectionFR_Def_Stat_CCU_Stat1_Active (1) +#endif + +#ifndef CCU_AirDirectionFR_Def_Stat_CCU_Stat1_Inactive +#define CCU_AirDirectionFR_Def_Stat_CCU_Stat1_Inactive (0) +#endif + + +// Value tables for @CCU_AirDirectionFR_Face_Stat signal + +#ifndef CCU_AirDirectionFR_Face_Stat_CCU_Stat1_Active +#define CCU_AirDirectionFR_Face_Stat_CCU_Stat1_Active (1) +#endif + +#ifndef CCU_AirDirectionFR_Face_Stat_CCU_Stat1_Inactive +#define CCU_AirDirectionFR_Face_Stat_CCU_Stat1_Inactive (0) +#endif + + +// Value tables for @CCU_AirDirectionFR_Foot_Stat signal + +#ifndef CCU_AirDirectionFR_Foot_Stat_CCU_Stat1_Active +#define CCU_AirDirectionFR_Foot_Stat_CCU_Stat1_Active (1) +#endif + +#ifndef CCU_AirDirectionFR_Foot_Stat_CCU_Stat1_Inactive +#define CCU_AirDirectionFR_Foot_Stat_CCU_Stat1_Inactive (0) +#endif + + +// Value tables for @CCU_Recirculation_Stat signal + +#ifndef CCU_Recirculation_Stat_CCU_Stat1_Auto_recirculation_mode +#define CCU_Recirculation_Stat_CCU_Stat1_Auto_recirculation_mode (2) +#endif + +#ifndef CCU_Recirculation_Stat_CCU_Stat1_Recirculation_mode_Rec_on +#define CCU_Recirculation_Stat_CCU_Stat1_Recirculation_mode_Rec_on (1) +#endif + +#ifndef CCU_Recirculation_Stat_CCU_Stat1_Fresh_air_mode_Rec_off +#define CCU_Recirculation_Stat_CCU_Stat1_Fresh_air_mode_Rec_off (0) +#endif + + +// Value tables for @CCU_BlowerSpeedFL_Stat signal + +#ifndef CCU_BlowerSpeedFL_Stat_CCU_Stat1__step +#define CCU_BlowerSpeedFL_Stat_CCU_Stat1__step (7) +#endif + +#ifndef CCU_BlowerSpeedFL_Stat_CCU_Stat1__step +#define CCU_BlowerSpeedFL_Stat_CCU_Stat1__step (6) +#endif + +#ifndef CCU_BlowerSpeedFL_Stat_CCU_Stat1__step +#define CCU_BlowerSpeedFL_Stat_CCU_Stat1__step (5) +#endif + +#ifndef CCU_BlowerSpeedFL_Stat_CCU_Stat1__step +#define CCU_BlowerSpeedFL_Stat_CCU_Stat1__step (4) +#endif + +#ifndef CCU_BlowerSpeedFL_Stat_CCU_Stat1__step +#define CCU_BlowerSpeedFL_Stat_CCU_Stat1__step (3) +#endif + +#ifndef CCU_BlowerSpeedFL_Stat_CCU_Stat1__step +#define CCU_BlowerSpeedFL_Stat_CCU_Stat1__step (2) +#endif + +#ifndef CCU_BlowerSpeedFL_Stat_CCU_Stat1__step +#define CCU_BlowerSpeedFL_Stat_CCU_Stat1__step (1) +#endif + +#ifndef CCU_BlowerSpeedFL_Stat_CCU_Stat1_Blower_off +#define CCU_BlowerSpeedFL_Stat_CCU_Stat1_Blower_off (0) +#endif + +// signal: @CCU_TargetTempFL_Stat_ro +#define CANDB_CCU_TargetTempFL_Stat_ro_CovFactor (0.5) +#define CANDB_CCU_TargetTempFL_Stat_ro_toS(x) ( (uint8_t) (((x) - (16.0)) / (0.5)) ) +#define CANDB_CCU_TargetTempFL_Stat_ro_fromS(x) ( (((x) * (0.5)) + (16.0)) ) + +// Value tables for @CCU_BlowerSpeedFR_Stat signal + +#ifndef CCU_BlowerSpeedFR_Stat_CCU_Stat1__step +#define CCU_BlowerSpeedFR_Stat_CCU_Stat1__step (7) +#endif + +#ifndef CCU_BlowerSpeedFR_Stat_CCU_Stat1__step +#define CCU_BlowerSpeedFR_Stat_CCU_Stat1__step (6) +#endif + +#ifndef CCU_BlowerSpeedFR_Stat_CCU_Stat1__step +#define CCU_BlowerSpeedFR_Stat_CCU_Stat1__step (5) +#endif + +#ifndef CCU_BlowerSpeedFR_Stat_CCU_Stat1__step +#define CCU_BlowerSpeedFR_Stat_CCU_Stat1__step (4) +#endif + +#ifndef CCU_BlowerSpeedFR_Stat_CCU_Stat1__step +#define CCU_BlowerSpeedFR_Stat_CCU_Stat1__step (3) +#endif + +#ifndef CCU_BlowerSpeedFR_Stat_CCU_Stat1__step +#define CCU_BlowerSpeedFR_Stat_CCU_Stat1__step (2) +#endif + +#ifndef CCU_BlowerSpeedFR_Stat_CCU_Stat1__step +#define CCU_BlowerSpeedFR_Stat_CCU_Stat1__step (1) +#endif + +#ifndef CCU_BlowerSpeedFR_Stat_CCU_Stat1_Blower_off +#define CCU_BlowerSpeedFR_Stat_CCU_Stat1_Blower_off (0) +#endif + +// signal: @CCU_TargetTempFR_Stat_ro +#define CANDB_CCU_TargetTempFR_Stat_ro_CovFactor (0.5) +#define CANDB_CCU_TargetTempFR_Stat_ro_toS(x) ( (uint8_t) (((x) - (16.0)) / (0.5)) ) +#define CANDB_CCU_TargetTempFR_Stat_ro_fromS(x) ( (((x) * (0.5)) + (16.0)) ) + +// Value tables for @CCU_BlowerSpeedRL_Stat signal + +#ifndef CCU_BlowerSpeedRL_Stat_CCU_Stat1__step +#define CCU_BlowerSpeedRL_Stat_CCU_Stat1__step (7) +#endif + +#ifndef CCU_BlowerSpeedRL_Stat_CCU_Stat1__step +#define CCU_BlowerSpeedRL_Stat_CCU_Stat1__step (6) +#endif + +#ifndef CCU_BlowerSpeedRL_Stat_CCU_Stat1__step +#define CCU_BlowerSpeedRL_Stat_CCU_Stat1__step (5) +#endif + +#ifndef CCU_BlowerSpeedRL_Stat_CCU_Stat1__step +#define CCU_BlowerSpeedRL_Stat_CCU_Stat1__step (4) +#endif + +#ifndef CCU_BlowerSpeedRL_Stat_CCU_Stat1__step +#define CCU_BlowerSpeedRL_Stat_CCU_Stat1__step (3) +#endif + +#ifndef CCU_BlowerSpeedRL_Stat_CCU_Stat1__step +#define CCU_BlowerSpeedRL_Stat_CCU_Stat1__step (2) +#endif + +#ifndef CCU_BlowerSpeedRL_Stat_CCU_Stat1__step +#define CCU_BlowerSpeedRL_Stat_CCU_Stat1__step (1) +#endif + +#ifndef CCU_BlowerSpeedRL_Stat_CCU_Stat1_Blower_off +#define CCU_BlowerSpeedRL_Stat_CCU_Stat1_Blower_off (0) +#endif + +// signal: @CCU_TargetTempRR_Stat_ro +#define CANDB_CCU_TargetTempRR_Stat_ro_CovFactor (0.5) +#define CANDB_CCU_TargetTempRR_Stat_ro_toS(x) ( (uint8_t) (((x) - (16.0)) / (0.5)) ) +#define CANDB_CCU_TargetTempRR_Stat_ro_fromS(x) ( (((x) * (0.5)) + (16.0)) ) + +// Value tables for @CCU_BlowerSpeedRR_Stat signal + +#ifndef CCU_BlowerSpeedRR_Stat_CCU_Stat1__step +#define CCU_BlowerSpeedRR_Stat_CCU_Stat1__step (7) +#endif + +#ifndef CCU_BlowerSpeedRR_Stat_CCU_Stat1__step +#define CCU_BlowerSpeedRR_Stat_CCU_Stat1__step (6) +#endif + +#ifndef CCU_BlowerSpeedRR_Stat_CCU_Stat1__step +#define CCU_BlowerSpeedRR_Stat_CCU_Stat1__step (5) +#endif + +#ifndef CCU_BlowerSpeedRR_Stat_CCU_Stat1__step +#define CCU_BlowerSpeedRR_Stat_CCU_Stat1__step (4) +#endif + +#ifndef CCU_BlowerSpeedRR_Stat_CCU_Stat1__step +#define CCU_BlowerSpeedRR_Stat_CCU_Stat1__step (3) +#endif + +#ifndef CCU_BlowerSpeedRR_Stat_CCU_Stat1__step +#define CCU_BlowerSpeedRR_Stat_CCU_Stat1__step (2) +#endif + +#ifndef CCU_BlowerSpeedRR_Stat_CCU_Stat1__step +#define CCU_BlowerSpeedRR_Stat_CCU_Stat1__step (1) +#endif + +#ifndef CCU_BlowerSpeedRR_Stat_CCU_Stat1_Blower_off +#define CCU_BlowerSpeedRR_Stat_CCU_Stat1_Blower_off (0) +#endif + +// signal: @CCU_TargetTempRL_Stat_ro +#define CANDB_CCU_TargetTempRL_Stat_ro_CovFactor (0.5) +#define CANDB_CCU_TargetTempRL_Stat_ro_toS(x) ( (uint8_t) (((x) - (16.0)) / (0.5)) ) +#define CANDB_CCU_TargetTempRL_Stat_ro_fromS(x) ( (((x) * (0.5)) + (16.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Climate control mode for front left zone status + // 2 : "Semi-auto mode is active" + // 1 : "Auto mode is active" + // 0 : "Manual mode is active" + uint8_t CCU_ModeFL_Stat : 2; // Bits= 2 + + // Climate control mode for front right zone status + // 2 : "Semi-auto mode is active" + // 1 : "Auto mode is active" + // 0 : "Manual mode is active" + uint8_t CCU_ModeFR_Stat : 2; // Bits= 2 + + // Climate control mode for rear left zone status + // 2 : "Semi-auto mode is active" + // 1 : "Auto mode is active" + // 0 : "Manual mode is active" + uint8_t CCU_ModeRL_Stat : 2; // Bits= 2 + + // Climate control mode for rear right zone status + // 2 : "Semi-auto mode is active" + // 1 : "Auto mode is active" + // 0 : "Manual mode is active" + uint8_t CCU_ModeRR_Stat : 2; // Bits= 2 + + // Climate control auto mode for front left zone status + // 5 : "Auto mode 5 is active" + // 4 : "Auto mode 4 is active" + // 3 : "Auto mode 3 is active" + // 2 : "Auto mode 2 is active" + // 1 : "Auto mode 1 is active" + // 0 : "Auto mode is inactive" + uint8_t CCU_AutoModeFL_Stat : 3; // Bits= 3 + + // Climate control auto mode for front right zone status + // 5 : "Auto mode 5 is active" + // 4 : "Auto mode 4 is active" + // 3 : "Auto mode 3 is active" + // 2 : "Auto mode 2 is active" + // 1 : "Auto mode 1 is active" + // 0 : "Auto mode is inactive" + uint8_t CCU_AutoModeFR_Stat : 3; // Bits= 3 + + // Airflow direction mode for rear left zone status + // 1 : "Active" + // 0 : "Inactive" + uint8_t CCU_AirDirectionRL_Face_Stat : 1; // Bits= 1 + + // Airflow direction mode for rear left zone status + // 1 : "Active" + // 0 : "Inactive" + uint8_t CCU_AirDirectionRL_Foot_Stat : 1; // Bits= 1 + + // Climate control auto mode for rear left zone status + // 5 : "Auto mode 5 is active" + // 4 : "Auto mode 4 is active" + // 3 : "Auto mode 3 is active" + // 2 : "Auto mode 2 is active" + // 1 : "Auto mode 1 is active" + // 0 : "Auto mode is inactive" + uint8_t CCU_AutoModeRL_Stat : 3; // Bits= 3 + + // Climate control auto mode for rear right zone status + // 5 : "Auto mode 5 is active" + // 4 : "Auto mode 4 is active" + // 3 : "Auto mode 3 is active" + // 2 : "Auto mode 2 is active" + // 1 : "Auto mode 1 is active" + // 0 : "Auto mode is inactive" + uint8_t CCU_AutoModeRR_Stat : 3; // Bits= 3 + + // Airflow direction mode for rear right zone status + // 1 : "Active" + // 0 : "Inactive" + uint8_t CCU_AirDirectionRR_Face_Stat : 1; // Bits= 1 + + // Airflow direction mode for rear right zone status + // 1 : "Active" + // 0 : "Inactive" + uint8_t CCU_AirDirectionRR_Foot_Stat : 1; // Bits= 1 + + // Airflow direction mode for front left zone status + // 1 : "Active" + // 0 : "Inactive" + uint8_t CCU_AirDirectionFL_Def_Stat : 1; // Bits= 1 + + // Airflow direction mode for front left zone status + // 1 : "Active" + // 0 : "Inactive" + uint8_t CCU_AirDirectionFL_Face_Stat : 1; // Bits= 1 + + // Airflow direction mode for front left zone status + // 1 : "Active" + // 0 : "Inactive" + uint8_t CCU_AirDirectionFL_Foot_Stat : 1; // Bits= 1 + + // Airflow direction mode for front right zone status + // 1 : "Active" + // 0 : "Inactive" + uint8_t CCU_AirDirectionFR_Def_Stat : 1; // Bits= 1 + + // Airflow direction mode for front right zone status + // 1 : "Active" + // 0 : "Inactive" + uint8_t CCU_AirDirectionFR_Face_Stat : 1; // Bits= 1 + + // Airflow direction mode for front right zone status + // 1 : "Active" + // 0 : "Inactive" + uint8_t CCU_AirDirectionFR_Foot_Stat : 1; // Bits= 1 + + // Recirculation mode status + // 2 : "Auto recirculation mode" + // 1 : "Recirculation mode (Rec on)" + // 0 : "Fresh air mode (Rec off)" + uint8_t CCU_Recirculation_Stat : 2; // Bits= 2 + + // Blower speed for front left zone status + // 7 : "7 step" + // 6 : "6 step" + // 5 : "5 step" + // 4 : "4 step" + // 3 : "3 step" + // 2 : "2 step" + // 1 : "1 step" + // 0 : "Blower off" + uint8_t CCU_BlowerSpeedFL_Stat : 3; // Bits= 3 + + // Target temperature for front left zone status + uint8_t CCU_TargetTempFL_Stat_ro : 5; // Bits= 5 Offset= 16.0 Factor= 0.5 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t CCU_TargetTempFL_Stat_phys; +#endif // CANDB_USE_SIGFLOAT + + // Blower speed for front right zone status + // 7 : "7 step" + // 6 : "6 step" + // 5 : "5 step" + // 4 : "4 step" + // 3 : "3 step" + // 2 : "2 step" + // 1 : "1 step" + // 0 : "Blower off" + uint8_t CCU_BlowerSpeedFR_Stat : 3; // Bits= 3 + + // Target temperature for front right zone status + uint8_t CCU_TargetTempFR_Stat_ro : 5; // Bits= 5 Offset= 16.0 Factor= 0.5 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t CCU_TargetTempFR_Stat_phys; +#endif // CANDB_USE_SIGFLOAT + + // Blower speed for rear left zone status + // 7 : "7 step" + // 6 : "6 step" + // 5 : "5 step" + // 4 : "4 step" + // 3 : "3 step" + // 2 : "2 step" + // 1 : "1 step" + // 0 : "Blower off" + uint8_t CCU_BlowerSpeedRL_Stat : 3; // Bits= 3 + + // Target temperature for rear right zone status + uint8_t CCU_TargetTempRR_Stat_ro : 5; // Bits= 5 Offset= 16.0 Factor= 0.5 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t CCU_TargetTempRR_Stat_phys; +#endif // CANDB_USE_SIGFLOAT + + // Blower speed for rear right zone status + // 7 : "7 step" + // 6 : "6 step" + // 5 : "5 step" + // 4 : "4 step" + // 3 : "3 step" + // 2 : "2 step" + // 1 : "1 step" + // 0 : "Blower off" + uint8_t CCU_BlowerSpeedRR_Stat : 3; // Bits= 3 + + // Target temperature for rear left zone status + uint8_t CCU_TargetTempRL_Stat_ro : 5; // Bits= 5 Offset= 16.0 Factor= 0.5 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t CCU_TargetTempRL_Stat_phys; +#endif // CANDB_USE_SIGFLOAT + +#else + + // Climate control mode for front left zone status + // 2 : "Semi-auto mode is active" + // 1 : "Auto mode is active" + // 0 : "Manual mode is active" + uint8_t CCU_ModeFL_Stat; // Bits= 2 + + // Climate control mode for front right zone status + // 2 : "Semi-auto mode is active" + // 1 : "Auto mode is active" + // 0 : "Manual mode is active" + uint8_t CCU_ModeFR_Stat; // Bits= 2 + + // Climate control mode for rear left zone status + // 2 : "Semi-auto mode is active" + // 1 : "Auto mode is active" + // 0 : "Manual mode is active" + uint8_t CCU_ModeRL_Stat; // Bits= 2 + + // Climate control mode for rear right zone status + // 2 : "Semi-auto mode is active" + // 1 : "Auto mode is active" + // 0 : "Manual mode is active" + uint8_t CCU_ModeRR_Stat; // Bits= 2 + + // Climate control auto mode for front left zone status + // 5 : "Auto mode 5 is active" + // 4 : "Auto mode 4 is active" + // 3 : "Auto mode 3 is active" + // 2 : "Auto mode 2 is active" + // 1 : "Auto mode 1 is active" + // 0 : "Auto mode is inactive" + uint8_t CCU_AutoModeFL_Stat; // Bits= 3 + + // Climate control auto mode for front right zone status + // 5 : "Auto mode 5 is active" + // 4 : "Auto mode 4 is active" + // 3 : "Auto mode 3 is active" + // 2 : "Auto mode 2 is active" + // 1 : "Auto mode 1 is active" + // 0 : "Auto mode is inactive" + uint8_t CCU_AutoModeFR_Stat; // Bits= 3 + + // Airflow direction mode for rear left zone status + // 1 : "Active" + // 0 : "Inactive" + uint8_t CCU_AirDirectionRL_Face_Stat; // Bits= 1 + + // Airflow direction mode for rear left zone status + // 1 : "Active" + // 0 : "Inactive" + uint8_t CCU_AirDirectionRL_Foot_Stat; // Bits= 1 + + // Climate control auto mode for rear left zone status + // 5 : "Auto mode 5 is active" + // 4 : "Auto mode 4 is active" + // 3 : "Auto mode 3 is active" + // 2 : "Auto mode 2 is active" + // 1 : "Auto mode 1 is active" + // 0 : "Auto mode is inactive" + uint8_t CCU_AutoModeRL_Stat; // Bits= 3 + + // Climate control auto mode for rear right zone status + // 5 : "Auto mode 5 is active" + // 4 : "Auto mode 4 is active" + // 3 : "Auto mode 3 is active" + // 2 : "Auto mode 2 is active" + // 1 : "Auto mode 1 is active" + // 0 : "Auto mode is inactive" + uint8_t CCU_AutoModeRR_Stat; // Bits= 3 + + // Airflow direction mode for rear right zone status + // 1 : "Active" + // 0 : "Inactive" + uint8_t CCU_AirDirectionRR_Face_Stat; // Bits= 1 + + // Airflow direction mode for rear right zone status + // 1 : "Active" + // 0 : "Inactive" + uint8_t CCU_AirDirectionRR_Foot_Stat; // Bits= 1 + + // Airflow direction mode for front left zone status + // 1 : "Active" + // 0 : "Inactive" + uint8_t CCU_AirDirectionFL_Def_Stat; // Bits= 1 + + // Airflow direction mode for front left zone status + // 1 : "Active" + // 0 : "Inactive" + uint8_t CCU_AirDirectionFL_Face_Stat; // Bits= 1 + + // Airflow direction mode for front left zone status + // 1 : "Active" + // 0 : "Inactive" + uint8_t CCU_AirDirectionFL_Foot_Stat; // Bits= 1 + + // Airflow direction mode for front right zone status + // 1 : "Active" + // 0 : "Inactive" + uint8_t CCU_AirDirectionFR_Def_Stat; // Bits= 1 + + // Airflow direction mode for front right zone status + // 1 : "Active" + // 0 : "Inactive" + uint8_t CCU_AirDirectionFR_Face_Stat; // Bits= 1 + + // Airflow direction mode for front right zone status + // 1 : "Active" + // 0 : "Inactive" + uint8_t CCU_AirDirectionFR_Foot_Stat; // Bits= 1 + + // Recirculation mode status + // 2 : "Auto recirculation mode" + // 1 : "Recirculation mode (Rec on)" + // 0 : "Fresh air mode (Rec off)" + uint8_t CCU_Recirculation_Stat; // Bits= 2 + + // Blower speed for front left zone status + // 7 : "7 step" + // 6 : "6 step" + // 5 : "5 step" + // 4 : "4 step" + // 3 : "3 step" + // 2 : "2 step" + // 1 : "1 step" + // 0 : "Blower off" + uint8_t CCU_BlowerSpeedFL_Stat; // Bits= 3 + + // Target temperature for front left zone status + uint8_t CCU_TargetTempFL_Stat_ro; // Bits= 5 Offset= 16.0 Factor= 0.5 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t CCU_TargetTempFL_Stat_phys; +#endif // CANDB_USE_SIGFLOAT + + // Blower speed for front right zone status + // 7 : "7 step" + // 6 : "6 step" + // 5 : "5 step" + // 4 : "4 step" + // 3 : "3 step" + // 2 : "2 step" + // 1 : "1 step" + // 0 : "Blower off" + uint8_t CCU_BlowerSpeedFR_Stat; // Bits= 3 + + // Target temperature for front right zone status + uint8_t CCU_TargetTempFR_Stat_ro; // Bits= 5 Offset= 16.0 Factor= 0.5 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t CCU_TargetTempFR_Stat_phys; +#endif // CANDB_USE_SIGFLOAT + + // Blower speed for rear left zone status + // 7 : "7 step" + // 6 : "6 step" + // 5 : "5 step" + // 4 : "4 step" + // 3 : "3 step" + // 2 : "2 step" + // 1 : "1 step" + // 0 : "Blower off" + uint8_t CCU_BlowerSpeedRL_Stat; // Bits= 3 + + // Target temperature for rear right zone status + uint8_t CCU_TargetTempRR_Stat_ro; // Bits= 5 Offset= 16.0 Factor= 0.5 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t CCU_TargetTempRR_Stat_phys; +#endif // CANDB_USE_SIGFLOAT + + // Blower speed for rear right zone status + // 7 : "7 step" + // 6 : "6 step" + // 5 : "5 step" + // 4 : "4 step" + // 3 : "3 step" + // 2 : "2 step" + // 1 : "1 step" + // 0 : "Blower off" + uint8_t CCU_BlowerSpeedRR_Stat; // Bits= 3 + + // Target temperature for rear left zone status + uint8_t CCU_TargetTempRL_Stat_ro; // Bits= 5 Offset= 16.0 Factor= 0.5 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t CCU_TargetTempRL_Stat_phys; +#endif // CANDB_USE_SIGFLOAT + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} CCU_Stat1_t; + +// def @CCU_Stat2 CAN Message (786 0x312) +#define CCU_Stat2_IDE (0U) +#define CCU_Stat2_DLC (6U) +#define CCU_Stat2_CANID (0x312U) +#define CCU_Stat2_CYC (100U) + +// Value tables for @CCU_AromaCartridgeSw_Stat signal + +#ifndef CCU_AromaCartridgeSw_Stat_CCU_Stat2_Cartridge_extracted +#define CCU_AromaCartridgeSw_Stat_CCU_Stat2_Cartridge_extracted (1) +#endif + +#ifndef CCU_AromaCartridgeSw_Stat_CCU_Stat2_artridge_installed +#define CCU_AromaCartridgeSw_Stat_CCU_Stat2_artridge_installed (0) +#endif + + +// Value tables for @CCU_FrontZoneSync_Stat signal + +#ifndef CCU_FrontZoneSync_Stat_CCU_Stat2_Sync_on +#define CCU_FrontZoneSync_Stat_CCU_Stat2_Sync_on (1) +#endif + +#ifndef CCU_FrontZoneSync_Stat_CCU_Stat2_Sync_off +#define CCU_FrontZoneSync_Stat_CCU_Stat2_Sync_off (0) +#endif + + +// Value tables for @CCU_RearZoneSync_Stat signal + +#ifndef CCU_RearZoneSync_Stat_CCU_Stat2_Sync_on +#define CCU_RearZoneSync_Stat_CCU_Stat2_Sync_on (1) +#endif + +#ifndef CCU_RearZoneSync_Stat_CCU_Stat2_Sync_off +#define CCU_RearZoneSync_Stat_CCU_Stat2_Sync_off (0) +#endif + + +// Value tables for @CCU_AllZoneSync_Stat signal + +#ifndef CCU_AllZoneSync_Stat_CCU_Stat2_Sync_on +#define CCU_AllZoneSync_Stat_CCU_Stat2_Sync_on (1) +#endif + +#ifndef CCU_AllZoneSync_Stat_CCU_Stat2_Sync_off +#define CCU_AllZoneSync_Stat_CCU_Stat2_Sync_off (0) +#endif + + +// Value tables for @CCU_ACfront_Stat signal + +#ifndef CCU_ACfront_Stat_CCU_Stat2_AC_front_on +#define CCU_ACfront_Stat_CCU_Stat2_AC_front_on (1) +#endif + +#ifndef CCU_ACfront_Stat_CCU_Stat2_AC_front_off +#define CCU_ACfront_Stat_CCU_Stat2_AC_front_off (0) +#endif + + +// Value tables for @CCU_ACrear_Stat signal + +#ifndef CCU_ACrear_Stat_CCU_Stat2_AC_rear_on +#define CCU_ACrear_Stat_CCU_Stat2_AC_rear_on (1) +#endif + +#ifndef CCU_ACrear_Stat_CCU_Stat2_AC_rear_off +#define CCU_ACrear_Stat_CCU_Stat2_AC_rear_off (0) +#endif + + +// Value tables for @CCU_ACmaxF_Stat signal + +#ifndef CCU_ACmaxF_Stat_CCU_Stat2_AC_MAX_on +#define CCU_ACmaxF_Stat_CCU_Stat2_AC_MAX_on (1) +#endif + +#ifndef CCU_ACmaxF_Stat_CCU_Stat2_AC_MAX_off +#define CCU_ACmaxF_Stat_CCU_Stat2_AC_MAX_off (0) +#endif + + +// Value tables for @CCU_ACmaxR_Stat signal + +#ifndef CCU_ACmaxR_Stat_CCU_Stat2_AC_MAX_on +#define CCU_ACmaxR_Stat_CCU_Stat2_AC_MAX_on (1) +#endif + +#ifndef CCU_ACmaxR_Stat_CCU_Stat2_AC_MAX_off +#define CCU_ACmaxR_Stat_CCU_Stat2_AC_MAX_off (0) +#endif + + +// Value tables for @CCU_Defrost_Stat signal + +#ifndef CCU_Defrost_Stat_CCU_Stat2_Defrost_is_active +#define CCU_Defrost_Stat_CCU_Stat2_Defrost_is_active (1) +#endif + +#ifndef CCU_Defrost_Stat_CCU_Stat2_Defrost_is_inactive +#define CCU_Defrost_Stat_CCU_Stat2_Defrost_is_inactive (0) +#endif + + +// Value tables for @CCU_Ionization_Stat signal + +#ifndef CCU_Ionization_Stat_CCU_Stat2_Ionizer_is_on +#define CCU_Ionization_Stat_CCU_Stat2_Ionizer_is_on (1) +#endif + +#ifndef CCU_Ionization_Stat_CCU_Stat2_Ionizer_is_off +#define CCU_Ionization_Stat_CCU_Stat2_Ionizer_is_off (0) +#endif + + +// Value tables for @CCU_FootTempCorFL_Stat signal + +#ifndef CCU_FootTempCorFL_Stat_CCU_Stat2__step +#define CCU_FootTempCorFL_Stat_CCU_Stat2__step (6) +#endif + +#ifndef CCU_FootTempCorFL_Stat_CCU_Stat2__step +#define CCU_FootTempCorFL_Stat_CCU_Stat2__step (5) +#endif + +#ifndef CCU_FootTempCorFL_Stat_CCU_Stat2__step +#define CCU_FootTempCorFL_Stat_CCU_Stat2__step (4) +#endif + +#ifndef CCU_FootTempCorFL_Stat_CCU_Stat2__step +#define CCU_FootTempCorFL_Stat_CCU_Stat2__step (3) +#endif + +#ifndef CCU_FootTempCorFL_Stat_CCU_Stat2__step +#define CCU_FootTempCorFL_Stat_CCU_Stat2__step (2) +#endif + +#ifndef CCU_FootTempCorFL_Stat_CCU_Stat2__step +#define CCU_FootTempCorFL_Stat_CCU_Stat2__step (1) +#endif + +#ifndef CCU_FootTempCorFL_Stat_CCU_Stat2__step +#define CCU_FootTempCorFL_Stat_CCU_Stat2__step (0) +#endif + + +// Value tables for @CCU_FootTempCorFR_Stat signal + +#ifndef CCU_FootTempCorFR_Stat_CCU_Stat2__step +#define CCU_FootTempCorFR_Stat_CCU_Stat2__step (6) +#endif + +#ifndef CCU_FootTempCorFR_Stat_CCU_Stat2__step +#define CCU_FootTempCorFR_Stat_CCU_Stat2__step (5) +#endif + +#ifndef CCU_FootTempCorFR_Stat_CCU_Stat2__step +#define CCU_FootTempCorFR_Stat_CCU_Stat2__step (4) +#endif + +#ifndef CCU_FootTempCorFR_Stat_CCU_Stat2__step +#define CCU_FootTempCorFR_Stat_CCU_Stat2__step (3) +#endif + +#ifndef CCU_FootTempCorFR_Stat_CCU_Stat2__step +#define CCU_FootTempCorFR_Stat_CCU_Stat2__step (2) +#endif + +#ifndef CCU_FootTempCorFR_Stat_CCU_Stat2__step +#define CCU_FootTempCorFR_Stat_CCU_Stat2__step (1) +#endif + +#ifndef CCU_FootTempCorFR_Stat_CCU_Stat2__step +#define CCU_FootTempCorFR_Stat_CCU_Stat2__step (0) +#endif + + +// Value tables for @CCU_AromaIntens_Stat signal + +#ifndef CCU_AromaIntens_Stat_CCU_Stat2_Aromatization_mode_3_step +#define CCU_AromaIntens_Stat_CCU_Stat2_Aromatization_mode_3_step (3) +#endif + +#ifndef CCU_AromaIntens_Stat_CCU_Stat2_Aromatization_mode_2_step +#define CCU_AromaIntens_Stat_CCU_Stat2_Aromatization_mode_2_step (2) +#endif + +#ifndef CCU_AromaIntens_Stat_CCU_Stat2_Aromatization_mode_1_step +#define CCU_AromaIntens_Stat_CCU_Stat2_Aromatization_mode_1_step (1) +#endif + +#ifndef CCU_AromaIntens_Stat_CCU_Stat2_Aromatization_off +#define CCU_AromaIntens_Stat_CCU_Stat2_Aromatization_off (0) +#endif + + +// Value tables for @CCU_FootTempCorRL_Stat signal + +#ifndef CCU_FootTempCorRL_Stat_CCU_Stat2__step +#define CCU_FootTempCorRL_Stat_CCU_Stat2__step (6) +#endif + +#ifndef CCU_FootTempCorRL_Stat_CCU_Stat2__step +#define CCU_FootTempCorRL_Stat_CCU_Stat2__step (5) +#endif + +#ifndef CCU_FootTempCorRL_Stat_CCU_Stat2__step +#define CCU_FootTempCorRL_Stat_CCU_Stat2__step (4) +#endif + +#ifndef CCU_FootTempCorRL_Stat_CCU_Stat2__step +#define CCU_FootTempCorRL_Stat_CCU_Stat2__step (3) +#endif + +#ifndef CCU_FootTempCorRL_Stat_CCU_Stat2__step +#define CCU_FootTempCorRL_Stat_CCU_Stat2__step (2) +#endif + +#ifndef CCU_FootTempCorRL_Stat_CCU_Stat2__step +#define CCU_FootTempCorRL_Stat_CCU_Stat2__step (1) +#endif + +#ifndef CCU_FootTempCorRL_Stat_CCU_Stat2__step +#define CCU_FootTempCorRL_Stat_CCU_Stat2__step (0) +#endif + + +// Value tables for @CCU_FootTempCorRR_Stat signal + +#ifndef CCU_FootTempCorRR_Stat_CCU_Stat2__step +#define CCU_FootTempCorRR_Stat_CCU_Stat2__step (6) +#endif + +#ifndef CCU_FootTempCorRR_Stat_CCU_Stat2__step +#define CCU_FootTempCorRR_Stat_CCU_Stat2__step (5) +#endif + +#ifndef CCU_FootTempCorRR_Stat_CCU_Stat2__step +#define CCU_FootTempCorRR_Stat_CCU_Stat2__step (4) +#endif + +#ifndef CCU_FootTempCorRR_Stat_CCU_Stat2__step +#define CCU_FootTempCorRR_Stat_CCU_Stat2__step (3) +#endif + +#ifndef CCU_FootTempCorRR_Stat_CCU_Stat2__step +#define CCU_FootTempCorRR_Stat_CCU_Stat2__step (2) +#endif + +#ifndef CCU_FootTempCorRR_Stat_CCU_Stat2__step +#define CCU_FootTempCorRR_Stat_CCU_Stat2__step (1) +#endif + +#ifndef CCU_FootTempCorRR_Stat_CCU_Stat2__step +#define CCU_FootTempCorRR_Stat_CCU_Stat2__step (0) +#endif + + +// Value tables for @CCU_DeflectorSwDL_Stat signal + +#ifndef CCU_DeflectorSwDL_Stat_CCU_Stat2_LED_3_step +#define CCU_DeflectorSwDL_Stat_CCU_Stat2_LED_3_step (3) +#endif + +#ifndef CCU_DeflectorSwDL_Stat_CCU_Stat2_LED_2_step +#define CCU_DeflectorSwDL_Stat_CCU_Stat2_LED_2_step (2) +#endif + +#ifndef CCU_DeflectorSwDL_Stat_CCU_Stat2_LED_1_step +#define CCU_DeflectorSwDL_Stat_CCU_Stat2_LED_1_step (1) +#endif + +#ifndef CCU_DeflectorSwDL_Stat_CCU_Stat2_No_LED +#define CCU_DeflectorSwDL_Stat_CCU_Stat2_No_LED (0) +#endif + + +// Value tables for @CCU_DeflectorSwDR_Stat signal + +#ifndef CCU_DeflectorSwDR_Stat_CCU_Stat2_LED_3_step +#define CCU_DeflectorSwDR_Stat_CCU_Stat2_LED_3_step (3) +#endif + +#ifndef CCU_DeflectorSwDR_Stat_CCU_Stat2_LED_2_step +#define CCU_DeflectorSwDR_Stat_CCU_Stat2_LED_2_step (2) +#endif + +#ifndef CCU_DeflectorSwDR_Stat_CCU_Stat2_LED_1_step +#define CCU_DeflectorSwDR_Stat_CCU_Stat2_LED_1_step (1) +#endif + +#ifndef CCU_DeflectorSwDR_Stat_CCU_Stat2_No_LED +#define CCU_DeflectorSwDR_Stat_CCU_Stat2_No_LED (0) +#endif + + +// Value tables for @CCU_DeflectorSwFPL_Stat signal + +#ifndef CCU_DeflectorSwFPL_Stat_CCU_Stat2_LED_3_step +#define CCU_DeflectorSwFPL_Stat_CCU_Stat2_LED_3_step (3) +#endif + +#ifndef CCU_DeflectorSwFPL_Stat_CCU_Stat2_LED_2_step +#define CCU_DeflectorSwFPL_Stat_CCU_Stat2_LED_2_step (2) +#endif + +#ifndef CCU_DeflectorSwFPL_Stat_CCU_Stat2_LED_1_step +#define CCU_DeflectorSwFPL_Stat_CCU_Stat2_LED_1_step (1) +#endif + +#ifndef CCU_DeflectorSwFPL_Stat_CCU_Stat2_No_LED +#define CCU_DeflectorSwFPL_Stat_CCU_Stat2_No_LED (0) +#endif + + +// Value tables for @CCU_DeflectorSwFPR_Stat signal + +#ifndef CCU_DeflectorSwFPR_Stat_CCU_Stat2_LED_3_step +#define CCU_DeflectorSwFPR_Stat_CCU_Stat2_LED_3_step (3) +#endif + +#ifndef CCU_DeflectorSwFPR_Stat_CCU_Stat2_LED_2_step +#define CCU_DeflectorSwFPR_Stat_CCU_Stat2_LED_2_step (2) +#endif + +#ifndef CCU_DeflectorSwFPR_Stat_CCU_Stat2_LED_1_step +#define CCU_DeflectorSwFPR_Stat_CCU_Stat2_LED_1_step (1) +#endif + +#ifndef CCU_DeflectorSwFPR_Stat_CCU_Stat2_No_LED +#define CCU_DeflectorSwFPR_Stat_CCU_Stat2_No_LED (0) +#endif + + +// Value tables for @CCU_DeflectorSwFCL_Stat signal + +#ifndef CCU_DeflectorSwFCL_Stat_CCU_Stat2_LED_3_step +#define CCU_DeflectorSwFCL_Stat_CCU_Stat2_LED_3_step (3) +#endif + +#ifndef CCU_DeflectorSwFCL_Stat_CCU_Stat2_LED_2_step +#define CCU_DeflectorSwFCL_Stat_CCU_Stat2_LED_2_step (2) +#endif + +#ifndef CCU_DeflectorSwFCL_Stat_CCU_Stat2_LED_1_step +#define CCU_DeflectorSwFCL_Stat_CCU_Stat2_LED_1_step (1) +#endif + +#ifndef CCU_DeflectorSwFCL_Stat_CCU_Stat2_No_LED +#define CCU_DeflectorSwFCL_Stat_CCU_Stat2_No_LED (0) +#endif + + +// Value tables for @CCU_DeflectorSwFCR_Stat signal + +#ifndef CCU_DeflectorSwFCR_Stat_CCU_Stat2_LED_3_step +#define CCU_DeflectorSwFCR_Stat_CCU_Stat2_LED_3_step (3) +#endif + +#ifndef CCU_DeflectorSwFCR_Stat_CCU_Stat2_LED_2_step +#define CCU_DeflectorSwFCR_Stat_CCU_Stat2_LED_2_step (2) +#endif + +#ifndef CCU_DeflectorSwFCR_Stat_CCU_Stat2_LED_1_step +#define CCU_DeflectorSwFCR_Stat_CCU_Stat2_LED_1_step (1) +#endif + +#ifndef CCU_DeflectorSwFCR_Stat_CCU_Stat2_No_LED +#define CCU_DeflectorSwFCR_Stat_CCU_Stat2_No_LED (0) +#endif + + +// Value tables for @CCU_DeflectorSwRLB_Stat signal + +#ifndef CCU_DeflectorSwRLB_Stat_CCU_Stat2_LED_3_step +#define CCU_DeflectorSwRLB_Stat_CCU_Stat2_LED_3_step (3) +#endif + +#ifndef CCU_DeflectorSwRLB_Stat_CCU_Stat2_LED_2_step +#define CCU_DeflectorSwRLB_Stat_CCU_Stat2_LED_2_step (2) +#endif + +#ifndef CCU_DeflectorSwRLB_Stat_CCU_Stat2_LED_1_step +#define CCU_DeflectorSwRLB_Stat_CCU_Stat2_LED_1_step (1) +#endif + +#ifndef CCU_DeflectorSwRLB_Stat_CCU_Stat2_No_LED +#define CCU_DeflectorSwRLB_Stat_CCU_Stat2_No_LED (0) +#endif + + +// Value tables for @CCU_DeflectorSwRRB_Stat signal + +#ifndef CCU_DeflectorSwRRB_Stat_CCU_Stat2_LED_3_step +#define CCU_DeflectorSwRRB_Stat_CCU_Stat2_LED_3_step (3) +#endif + +#ifndef CCU_DeflectorSwRRB_Stat_CCU_Stat2_LED_2_step +#define CCU_DeflectorSwRRB_Stat_CCU_Stat2_LED_2_step (2) +#endif + +#ifndef CCU_DeflectorSwRRB_Stat_CCU_Stat2_LED_1_step +#define CCU_DeflectorSwRRB_Stat_CCU_Stat2_LED_1_step (1) +#endif + +#ifndef CCU_DeflectorSwRRB_Stat_CCU_Stat2_No_LED +#define CCU_DeflectorSwRRB_Stat_CCU_Stat2_No_LED (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Cartridge switch status from aromatization system + // 1 : "Cartridge extracted" + // 0 : "�artridge installed" + uint8_t CCU_AromaCartridgeSw_Stat : 1; // Bits= 1 + + // Front climate zones synchronization status + // 1 : "Sync on" + // 0 : "Sync off" + uint8_t CCU_FrontZoneSync_Stat : 1; // Bits= 1 + + // Rear climate zones synchronization status + // 1 : "Sync on" + // 0 : "Sync off" + uint8_t CCU_RearZoneSync_Stat : 1; // Bits= 1 + + // All climate zones synchronization status + // 1 : "Sync on" + // 0 : "Sync off" + uint8_t CCU_AllZoneSync_Stat : 1; // Bits= 1 + + // Air conditioner front status + // 1 : "AC front on" + // 0 : "AC front off" + uint8_t CCU_ACfront_Stat : 1; // Bits= 1 + + // Air conditioner rear status + // 1 : "AC rear on" + // 0 : "AC rear off" + uint8_t CCU_ACrear_Stat : 1; // Bits= 1 + + // AC MAX mode for front zone status + // 1 : "AC MAX on" + // 0 : "AC MAX off" + uint8_t CCU_ACmaxF_Stat : 1; // Bits= 1 + + // AC MAX mode for rear zone status + // 1 : "AC MAX on" + // 0 : "AC MAX off" + uint8_t CCU_ACmaxR_Stat : 1; // Bits= 1 + + // Defrost mode status + // 1 : "Defrost is active" + // 0 : "Defrost is inactive" + uint8_t CCU_Defrost_Stat : 1; // Bits= 1 + + // Ionization system mode status + // 1 : "Ionizer is on" + // 0 : "Ionizer is off" + uint8_t CCU_Ionization_Stat : 1; // Bits= 1 + + // Footwell temperature correction for front left zone status + // 6 : "+3 step" + // 5 : "+2 step" + // 4 : "+1 step" + // 3 : "0 step" + // 2 : "-1 step" + // 1 : "-2 step" + // 0 : "-3 step" + uint8_t CCU_FootTempCorFL_Stat : 3; // Bits= 3 + + // Footwell temperature correction for front right zone status + // 6 : "+3 step" + // 5 : "+2 step" + // 4 : "+1 step" + // 3 : "0 step" + // 2 : "-1 step" + // 1 : "-2 step" + // 0 : "-3 step" + uint8_t CCU_FootTempCorFR_Stat : 3; // Bits= 3 + + // Aromatization intensity status + // 3 : "Aromatization mode 3 step" + // 2 : "Aromatization mode 2 step" + // 1 : "Aromatization mode 1 step" + // 0 : "Aromatization off" + uint8_t CCU_AromaIntens_Stat : 2; // Bits= 2 + + // Footwell temperature correction for rear left zone status + // 6 : "+3 step" + // 5 : "+2 step" + // 4 : "+1 step" + // 3 : "0 step" + // 2 : "-1 step" + // 1 : "-2 step" + // 0 : "-3 step" + uint8_t CCU_FootTempCorRL_Stat : 3; // Bits= 3 + + // Footwell temperature correction for rear right zone status + // 6 : "+3 step" + // 5 : "+2 step" + // 4 : "+1 step" + // 3 : "0 step" + // 2 : "-1 step" + // 1 : "-2 step" + // 0 : "-3 step" + uint8_t CCU_FootTempCorRR_Stat : 3; // Bits= 3 + + // Deflector driver left status + // 3 : "LED 3 step" + // 2 : "LED 2 step" + // 1 : "LED 1 step" + // 0 : "No LED" + uint8_t CCU_DeflectorSwDL_Stat : 2; // Bits= 2 + + // Deflector driver right status + // 3 : "LED 3 step" + // 2 : "LED 2 step" + // 1 : "LED 1 step" + // 0 : "No LED" + uint8_t CCU_DeflectorSwDR_Stat : 2; // Bits= 2 + + // Deflector front passenger left status + // 3 : "LED 3 step" + // 2 : "LED 2 step" + // 1 : "LED 1 step" + // 0 : "No LED" + uint8_t CCU_DeflectorSwFPL_Stat : 2; // Bits= 2 + + // Deflector front passenger right status + // 3 : "LED 3 step" + // 2 : "LED 2 step" + // 1 : "LED 1 step" + // 0 : "No LED" + uint8_t CCU_DeflectorSwFPR_Stat : 2; // Bits= 2 + + // Deflector front console left status + // 3 : "LED 3 step" + // 2 : "LED 2 step" + // 1 : "LED 1 step" + // 0 : "No LED" + uint8_t CCU_DeflectorSwFCL_Stat : 2; // Bits= 2 + + // Deflector front console right status + // 3 : "LED 3 step" + // 2 : "LED 2 step" + // 1 : "LED 1 step" + // 0 : "No LED" + uint8_t CCU_DeflectorSwFCR_Stat : 2; // Bits= 2 + + // Deflector rear left in B-pillar status + // 3 : "LED 3 step" + // 2 : "LED 2 step" + // 1 : "LED 1 step" + // 0 : "No LED" + uint8_t CCU_DeflectorSwRLB_Stat : 2; // Bits= 2 + + // Deflector rear right in B-pillar status + // 3 : "LED 3 step" + // 2 : "LED 2 step" + // 1 : "LED 1 step" + // 0 : "No LED" + uint8_t CCU_DeflectorSwRRB_Stat : 2; // Bits= 2 + +#else + + // Cartridge switch status from aromatization system + // 1 : "Cartridge extracted" + // 0 : "�artridge installed" + uint8_t CCU_AromaCartridgeSw_Stat; // Bits= 1 + + // Front climate zones synchronization status + // 1 : "Sync on" + // 0 : "Sync off" + uint8_t CCU_FrontZoneSync_Stat; // Bits= 1 + + // Rear climate zones synchronization status + // 1 : "Sync on" + // 0 : "Sync off" + uint8_t CCU_RearZoneSync_Stat; // Bits= 1 + + // All climate zones synchronization status + // 1 : "Sync on" + // 0 : "Sync off" + uint8_t CCU_AllZoneSync_Stat; // Bits= 1 + + // Air conditioner front status + // 1 : "AC front on" + // 0 : "AC front off" + uint8_t CCU_ACfront_Stat; // Bits= 1 + + // Air conditioner rear status + // 1 : "AC rear on" + // 0 : "AC rear off" + uint8_t CCU_ACrear_Stat; // Bits= 1 + + // AC MAX mode for front zone status + // 1 : "AC MAX on" + // 0 : "AC MAX off" + uint8_t CCU_ACmaxF_Stat; // Bits= 1 + + // AC MAX mode for rear zone status + // 1 : "AC MAX on" + // 0 : "AC MAX off" + uint8_t CCU_ACmaxR_Stat; // Bits= 1 + + // Defrost mode status + // 1 : "Defrost is active" + // 0 : "Defrost is inactive" + uint8_t CCU_Defrost_Stat; // Bits= 1 + + // Ionization system mode status + // 1 : "Ionizer is on" + // 0 : "Ionizer is off" + uint8_t CCU_Ionization_Stat; // Bits= 1 + + // Footwell temperature correction for front left zone status + // 6 : "+3 step" + // 5 : "+2 step" + // 4 : "+1 step" + // 3 : "0 step" + // 2 : "-1 step" + // 1 : "-2 step" + // 0 : "-3 step" + uint8_t CCU_FootTempCorFL_Stat; // Bits= 3 + + // Footwell temperature correction for front right zone status + // 6 : "+3 step" + // 5 : "+2 step" + // 4 : "+1 step" + // 3 : "0 step" + // 2 : "-1 step" + // 1 : "-2 step" + // 0 : "-3 step" + uint8_t CCU_FootTempCorFR_Stat; // Bits= 3 + + // Aromatization intensity status + // 3 : "Aromatization mode 3 step" + // 2 : "Aromatization mode 2 step" + // 1 : "Aromatization mode 1 step" + // 0 : "Aromatization off" + uint8_t CCU_AromaIntens_Stat; // Bits= 2 + + // Footwell temperature correction for rear left zone status + // 6 : "+3 step" + // 5 : "+2 step" + // 4 : "+1 step" + // 3 : "0 step" + // 2 : "-1 step" + // 1 : "-2 step" + // 0 : "-3 step" + uint8_t CCU_FootTempCorRL_Stat; // Bits= 3 + + // Footwell temperature correction for rear right zone status + // 6 : "+3 step" + // 5 : "+2 step" + // 4 : "+1 step" + // 3 : "0 step" + // 2 : "-1 step" + // 1 : "-2 step" + // 0 : "-3 step" + uint8_t CCU_FootTempCorRR_Stat; // Bits= 3 + + // Deflector driver left status + // 3 : "LED 3 step" + // 2 : "LED 2 step" + // 1 : "LED 1 step" + // 0 : "No LED" + uint8_t CCU_DeflectorSwDL_Stat; // Bits= 2 + + // Deflector driver right status + // 3 : "LED 3 step" + // 2 : "LED 2 step" + // 1 : "LED 1 step" + // 0 : "No LED" + uint8_t CCU_DeflectorSwDR_Stat; // Bits= 2 + + // Deflector front passenger left status + // 3 : "LED 3 step" + // 2 : "LED 2 step" + // 1 : "LED 1 step" + // 0 : "No LED" + uint8_t CCU_DeflectorSwFPL_Stat; // Bits= 2 + + // Deflector front passenger right status + // 3 : "LED 3 step" + // 2 : "LED 2 step" + // 1 : "LED 1 step" + // 0 : "No LED" + uint8_t CCU_DeflectorSwFPR_Stat; // Bits= 2 + + // Deflector front console left status + // 3 : "LED 3 step" + // 2 : "LED 2 step" + // 1 : "LED 1 step" + // 0 : "No LED" + uint8_t CCU_DeflectorSwFCL_Stat; // Bits= 2 + + // Deflector front console right status + // 3 : "LED 3 step" + // 2 : "LED 2 step" + // 1 : "LED 1 step" + // 0 : "No LED" + uint8_t CCU_DeflectorSwFCR_Stat; // Bits= 2 + + // Deflector rear left in B-pillar status + // 3 : "LED 3 step" + // 2 : "LED 2 step" + // 1 : "LED 1 step" + // 0 : "No LED" + uint8_t CCU_DeflectorSwRLB_Stat; // Bits= 2 + + // Deflector rear right in B-pillar status + // 3 : "LED 3 step" + // 2 : "LED 2 step" + // 1 : "LED 1 step" + // 0 : "No LED" + uint8_t CCU_DeflectorSwRRB_Stat; // Bits= 2 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} CCU_Stat2_t; + +// def @CCU_Requests CAN Message (787 0x313) +#define CCU_Requests_IDE (0U) +#define CCU_Requests_DLC (1U) +#define CCU_Requests_CANID (0x313U) +#define CCU_Requests_CYC (200U) + +// Value tables for @CCU_CarpetHeatFL_Req signal + +#ifndef CCU_CarpetHeatFL_Req_CCU_Requests_Carpet_heating_requested +#define CCU_CarpetHeatFL_Req_CCU_Requests_Carpet_heating_requested (1) +#endif + +#ifndef CCU_CarpetHeatFL_Req_CCU_Requests_Carpet_heating_not_requested +#define CCU_CarpetHeatFL_Req_CCU_Requests_Carpet_heating_not_requested (0) +#endif + + +// Value tables for @CCU_CarpetHeatFR_Req signal + +#ifndef CCU_CarpetHeatFR_Req_CCU_Requests_Carpet_heating_requested +#define CCU_CarpetHeatFR_Req_CCU_Requests_Carpet_heating_requested (1) +#endif + +#ifndef CCU_CarpetHeatFR_Req_CCU_Requests_Carpet_heating_not_requested +#define CCU_CarpetHeatFR_Req_CCU_Requests_Carpet_heating_not_requested (0) +#endif + + +// Value tables for @CCU_CarpetHeatRL_Req signal + +#ifndef CCU_CarpetHeatRL_Req_CCU_Requests_Carpet_heating_requested +#define CCU_CarpetHeatRL_Req_CCU_Requests_Carpet_heating_requested (1) +#endif + +#ifndef CCU_CarpetHeatRL_Req_CCU_Requests_Carpet_heating_not_requested +#define CCU_CarpetHeatRL_Req_CCU_Requests_Carpet_heating_not_requested (0) +#endif + + +// Value tables for @CCU_CarpetHeatRR_Req signal + +#ifndef CCU_CarpetHeatRR_Req_CCU_Requests_Carpet_heating_requested +#define CCU_CarpetHeatRR_Req_CCU_Requests_Carpet_heating_requested (1) +#endif + +#ifndef CCU_CarpetHeatRR_Req_CCU_Requests_Carpet_heating_not_requested +#define CCU_CarpetHeatRR_Req_CCU_Requests_Carpet_heating_not_requested (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Carpet heating request for front left zone + // 1 : "Carpet heating requested" + // 0 : "Carpet heating not requested" + uint8_t CCU_CarpetHeatFL_Req : 1; // Bits= 1 + + // Carpet heating request for front right zone + // 1 : "Carpet heating requested" + // 0 : "Carpet heating not requested" + uint8_t CCU_CarpetHeatFR_Req : 1; // Bits= 1 + + // Carpet heating request for rear left zone + // 1 : "Carpet heating requested" + // 0 : "Carpet heating not requested" + uint8_t CCU_CarpetHeatRL_Req : 1; // Bits= 1 + + // Carpet heating request for rear right zone + // 1 : "Carpet heating requested" + // 0 : "Carpet heating not requested" + uint8_t CCU_CarpetHeatRR_Req : 1; // Bits= 1 + +#else + + // Carpet heating request for front left zone + // 1 : "Carpet heating requested" + // 0 : "Carpet heating not requested" + uint8_t CCU_CarpetHeatFL_Req; // Bits= 1 + + // Carpet heating request for front right zone + // 1 : "Carpet heating requested" + // 0 : "Carpet heating not requested" + uint8_t CCU_CarpetHeatFR_Req; // Bits= 1 + + // Carpet heating request for rear left zone + // 1 : "Carpet heating requested" + // 0 : "Carpet heating not requested" + uint8_t CCU_CarpetHeatRL_Req; // Bits= 1 + + // Carpet heating request for rear right zone + // 1 : "Carpet heating requested" + // 0 : "Carpet heating not requested" + uint8_t CCU_CarpetHeatRR_Req; // Bits= 1 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} CCU_Requests_t; + +// def @CCU_Stat3 CAN Message (788 0x314) +#define CCU_Stat3_IDE (0U) +#define CCU_Stat3_DLC (4U) +#define CCU_Stat3_CANID (0x314U) +#define CCU_Stat3_CYC (250U) +// signal: @CCU_AromaCartridgeCapacity_Stat_ro +#define CANDB_CCU_AromaCartridgeCapacity_Stat_ro_CovFactor (10) +#define CANDB_CCU_AromaCartridgeCapacity_Stat_ro_toS(x) ( (uint8_t) ((x) / (10)) ) +#define CANDB_CCU_AromaCartridgeCapacity_Stat_ro_fromS(x) ( ((x) * (10)) ) + +// Value tables for @CCU_AromaCartridgeFlavor_Stat signal + +#ifndef CCU_AromaCartridgeFlavor_Stat_CCU_Stat3_Flavor_16 +#define CCU_AromaCartridgeFlavor_Stat_CCU_Stat3_Flavor_16 (15) +#endif + +#ifndef CCU_AromaCartridgeFlavor_Stat_CCU_Stat3_Flavor_15 +#define CCU_AromaCartridgeFlavor_Stat_CCU_Stat3_Flavor_15 (14) +#endif + +#ifndef CCU_AromaCartridgeFlavor_Stat_CCU_Stat3_Flavor_14 +#define CCU_AromaCartridgeFlavor_Stat_CCU_Stat3_Flavor_14 (13) +#endif + +#ifndef CCU_AromaCartridgeFlavor_Stat_CCU_Stat3_Flavor_13 +#define CCU_AromaCartridgeFlavor_Stat_CCU_Stat3_Flavor_13 (12) +#endif + +#ifndef CCU_AromaCartridgeFlavor_Stat_CCU_Stat3_Flavor_12 +#define CCU_AromaCartridgeFlavor_Stat_CCU_Stat3_Flavor_12 (11) +#endif + +#ifndef CCU_AromaCartridgeFlavor_Stat_CCU_Stat3_Flavor_11 +#define CCU_AromaCartridgeFlavor_Stat_CCU_Stat3_Flavor_11 (10) +#endif + +#ifndef CCU_AromaCartridgeFlavor_Stat_CCU_Stat3_Flavor_10 +#define CCU_AromaCartridgeFlavor_Stat_CCU_Stat3_Flavor_10 (9) +#endif + +#ifndef CCU_AromaCartridgeFlavor_Stat_CCU_Stat3_Flavor_9 +#define CCU_AromaCartridgeFlavor_Stat_CCU_Stat3_Flavor_9 (8) +#endif + +#ifndef CCU_AromaCartridgeFlavor_Stat_CCU_Stat3_Flavor_8 +#define CCU_AromaCartridgeFlavor_Stat_CCU_Stat3_Flavor_8 (7) +#endif + +#ifndef CCU_AromaCartridgeFlavor_Stat_CCU_Stat3_Flavor_7 +#define CCU_AromaCartridgeFlavor_Stat_CCU_Stat3_Flavor_7 (6) +#endif + +#ifndef CCU_AromaCartridgeFlavor_Stat_CCU_Stat3_Flavor_6 +#define CCU_AromaCartridgeFlavor_Stat_CCU_Stat3_Flavor_6 (5) +#endif + +#ifndef CCU_AromaCartridgeFlavor_Stat_CCU_Stat3_Flavor_5 +#define CCU_AromaCartridgeFlavor_Stat_CCU_Stat3_Flavor_5 (4) +#endif + +#ifndef CCU_AromaCartridgeFlavor_Stat_CCU_Stat3_Flavor_4 +#define CCU_AromaCartridgeFlavor_Stat_CCU_Stat3_Flavor_4 (3) +#endif + +#ifndef CCU_AromaCartridgeFlavor_Stat_CCU_Stat3_Flavor_3 +#define CCU_AromaCartridgeFlavor_Stat_CCU_Stat3_Flavor_3 (2) +#endif + +#ifndef CCU_AromaCartridgeFlavor_Stat_CCU_Stat3_Flavor_2 +#define CCU_AromaCartridgeFlavor_Stat_CCU_Stat3_Flavor_2 (1) +#endif + +#ifndef CCU_AromaCartridgeFlavor_Stat_CCU_Stat3_Flavor_1 +#define CCU_AromaCartridgeFlavor_Stat_CCU_Stat3_Flavor_1 (0) +#endif + + +// Value tables for @CCU_AromaFaultReason_Stat signal + +#ifndef CCU_AromaFaultReason_Stat_CCU_Stat3_Communication_or_hardware_error +#define CCU_AromaFaultReason_Stat_CCU_Stat3_Communication_or_hardware_error (5) +#endif + +#ifndef CCU_AromaFaultReason_Stat_CCU_Stat3_Selected_cartridge_ejected_or_empty +#define CCU_AromaFaultReason_Stat_CCU_Stat3_Selected_cartridge_ejected_or_empty (4) +#endif + +#ifndef CCU_AromaFaultReason_Stat_CCU_Stat3_Front_HVAC_fan_speed_too_fast +#define CCU_AromaFaultReason_Stat_CCU_Stat3_Front_HVAC_fan_speed_too_fast (3) +#endif + +#ifndef CCU_AromaFaultReason_Stat_CCU_Stat3_Front_HVAC_fan_speed_too_low +#define CCU_AromaFaultReason_Stat_CCU_Stat3_Front_HVAC_fan_speed_too_low (2) +#endif + +#ifndef CCU_AromaFaultReason_Stat_CCU_Stat3_Front_HVAC_fan_off +#define CCU_AromaFaultReason_Stat_CCU_Stat3_Front_HVAC_fan_off (1) +#endif + +#ifndef CCU_AromaFaultReason_Stat_CCU_Stat3_No_fault +#define CCU_AromaFaultReason_Stat_CCU_Stat3_No_fault (0) +#endif + + +// Value tables for @CCU_RLfootBlowDis_Stat signal + +#ifndef CCU_RLfootBlowDis_Stat_CCU_Stat3_Rear_footwell_blowing_disabled_limitation_ON +#define CCU_RLfootBlowDis_Stat_CCU_Stat3_Rear_footwell_blowing_disabled_limitation_ON (1) +#endif + +#ifndef CCU_RLfootBlowDis_Stat_CCU_Stat3_Rear_footwell_blowing_enabled_limitation_OFF +#define CCU_RLfootBlowDis_Stat_CCU_Stat3_Rear_footwell_blowing_enabled_limitation_OFF (0) +#endif + + +// Value tables for @CCU_RRfootBlowDis_Stat signal + +#ifndef CCU_RRfootBlowDis_Stat_CCU_Stat3_Rear_footwell_blowing_disabled_limitation_ON +#define CCU_RRfootBlowDis_Stat_CCU_Stat3_Rear_footwell_blowing_disabled_limitation_ON (1) +#endif + +#ifndef CCU_RRfootBlowDis_Stat_CCU_Stat3_Rear_footwell_blowing_enabled_limitation_OFF +#define CCU_RRfootBlowDis_Stat_CCU_Stat3_Rear_footwell_blowing_enabled_limitation_OFF (0) +#endif + + +// Value tables for @CCU_RestMode2_Stat signal + +#ifndef CCU_RestMode2_Stat_CCU_Stat3_Inactive +#define CCU_RestMode2_Stat_CCU_Stat3_Inactive (3) +#endif + +#ifndef CCU_RestMode2_Stat_CCU_Stat3_Active +#define CCU_RestMode2_Stat_CCU_Stat3_Active (2) +#endif + +#ifndef CCU_RestMode2_Stat_CCU_Stat3_Standby +#define CCU_RestMode2_Stat_CCU_Stat3_Standby (1) +#endif + +#ifndef CCU_RestMode2_Stat_CCU_Stat3_Not_requested +#define CCU_RestMode2_Stat_CCU_Stat3_Not_requested (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Aroma cartridge capacity status + uint8_t CCU_AromaCartridgeCapacity_Stat_ro : 4; // Bits= 4 Factor= 10 + +#ifdef CANDB_USE_SIGFLOAT + uint8_t CCU_AromaCartridgeCapacity_Stat_phys; +#endif // CANDB_USE_SIGFLOAT + + // Aroma cartridge flavor status + // 15 : "Flavor 16" + // 14 : "Flavor 15" + // 13 : "Flavor 14" + // 12 : "Flavor 13" + // 11 : "Flavor 12" + // 10 : "Flavor 11" + // 9 : "Flavor 10" + // 8 : "Flavor 9" + // 7 : "Flavor 8" + // 6 : "Flavor 7" + // 5 : "Flavor 6" + // 4 : "Flavor 5" + // 3 : "Flavor 4" + // 2 : "Flavor 3" + // 1 : "Flavor 2" + // 0 : "Flavor 1" + uint8_t CCU_AromaCartridgeFlavor_Stat : 4; // Bits= 4 + + // The reason why the aromatization system does not turn on + // 5 : "Communication or hardware error" + // 4 : "Selected cartridge ejected or empty" + // 3 : "Front HVAC fan speed too fast" + // 2 : "Front HVAC fan speed too low" + // 1 : "Front HVAC fan off" + // 0 : "No fault" + uint8_t CCU_AromaFaultReason_Stat : 3; // Bits= 3 + + // Rear left passenger footwell blowing disable status (summer mode) + // 1 : "Rear footwell blowing disabled (limitation ON)" + // 0 : "Rear footwell blowing enabled (limitation OFF)" + uint8_t CCU_RLfootBlowDis_Stat : 1; // Bits= 1 + + // Rear right passenger footwell blowing disable status (summer mode) + // 1 : "Rear footwell blowing disabled (limitation ON)" + // 0 : "Rear footwell blowing enabled (limitation OFF)" + uint8_t CCU_RRfootBlowDis_Stat : 1; // Bits= 1 + + // CCU REST mode status + // 3 : "Inactive" + // 2 : "Active" + // 1 : "Standby" + // 0 : "Not requested" + uint8_t CCU_RestMode2_Stat : 2; // Bits= 2 + +#else + + // Aroma cartridge capacity status + uint8_t CCU_AromaCartridgeCapacity_Stat_ro; // Bits= 4 Factor= 10 + +#ifdef CANDB_USE_SIGFLOAT + uint8_t CCU_AromaCartridgeCapacity_Stat_phys; +#endif // CANDB_USE_SIGFLOAT + + // Aroma cartridge flavor status + // 15 : "Flavor 16" + // 14 : "Flavor 15" + // 13 : "Flavor 14" + // 12 : "Flavor 13" + // 11 : "Flavor 12" + // 10 : "Flavor 11" + // 9 : "Flavor 10" + // 8 : "Flavor 9" + // 7 : "Flavor 8" + // 6 : "Flavor 7" + // 5 : "Flavor 6" + // 4 : "Flavor 5" + // 3 : "Flavor 4" + // 2 : "Flavor 3" + // 1 : "Flavor 2" + // 0 : "Flavor 1" + uint8_t CCU_AromaCartridgeFlavor_Stat; // Bits= 4 + + // The reason why the aromatization system does not turn on + // 5 : "Communication or hardware error" + // 4 : "Selected cartridge ejected or empty" + // 3 : "Front HVAC fan speed too fast" + // 2 : "Front HVAC fan speed too low" + // 1 : "Front HVAC fan off" + // 0 : "No fault" + uint8_t CCU_AromaFaultReason_Stat; // Bits= 3 + + // Rear left passenger footwell blowing disable status (summer mode) + // 1 : "Rear footwell blowing disabled (limitation ON)" + // 0 : "Rear footwell blowing enabled (limitation OFF)" + uint8_t CCU_RLfootBlowDis_Stat; // Bits= 1 + + // Rear right passenger footwell blowing disable status (summer mode) + // 1 : "Rear footwell blowing disabled (limitation ON)" + // 0 : "Rear footwell blowing enabled (limitation OFF)" + uint8_t CCU_RRfootBlowDis_Stat; // Bits= 1 + + // CCU REST mode status + // 3 : "Inactive" + // 2 : "Active" + // 1 : "Standby" + // 0 : "Not requested" + uint8_t CCU_RestMode2_Stat; // Bits= 2 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} CCU_Stat3_t; + +// def @CCU_VCU_Msg1 CAN Message (789 0x315) +#define CCU_VCU_Msg1_IDE (0U) +#define CCU_VCU_Msg1_DLC (8U) +#define CCU_VCU_Msg1_CANID (0x315U) +#define CCU_VCU_Msg1_CYC (200U) +// signal: @CCU_Sen_Pressure_ro +#define CANDB_CCU_Sen_Pressure_ro_CovFactor (0.1) +#define CANDB_CCU_Sen_Pressure_ro_toS(x) ( (uint16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_CCU_Sen_Pressure_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @CCU_EvaTargetTemp_Val_ro +#define CANDB_CCU_EvaTargetTemp_Val_ro_CovFactor (0.1) +#define CANDB_CCU_EvaTargetTemp_Val_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_CCU_EvaTargetTemp_Val_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @CCU_EvaCurrTempF_Val_ro +#define CANDB_CCU_EvaCurrTempF_Val_ro_CovFactor (0.1) +#define CANDB_CCU_EvaCurrTempF_Val_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_CCU_EvaCurrTempF_Val_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @CCU_EvaCurrTempR_Val_ro +#define CANDB_CCU_EvaCurrTempR_Val_ro_CovFactor (0.1) +#define CANDB_CCU_EvaCurrTempR_Val_ro_toS(x) ( (int16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_CCU_EvaCurrTempR_Val_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // AC pressure sensor value + uint16_t CCU_Sen_Pressure_ro; // Bits=12 Factor= 0.1 Unit:'ATM' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t CCU_Sen_Pressure_phys; +#endif // CANDB_USE_SIGFLOAT + + // Evaporators target temperature =dbg_Sen_Eva_Target in LocalCCU-CAN + int16_t CCU_EvaTargetTemp_Val_ro; // [-] Bits=12 Factor= 0.1 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t CCU_EvaTargetTemp_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Front evaporator current temperature =dbg_Sen_Eva_F in LocalCCU-CAN + int16_t CCU_EvaCurrTempF_Val_ro; // [-] Bits=12 Factor= 0.1 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t CCU_EvaCurrTempF_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Rear evaporator current temperature =dbg_Sen_Eva_R in LocalCCU-CAN + int16_t CCU_EvaCurrTempR_Val_ro; // [-] Bits=12 Factor= 0.1 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t CCU_EvaCurrTempR_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Request to VCU for target temperature Liquid HVAC Heater + uint8_t CCU_LiquidHeaterTargetTemp_Req : 7; // Bits= 7 Unit:'�C' + + // Rolling Counter [0 - 15] + uint8_t CCU_VCU_Msg1_RC : 4; // Bits= 4 + +#else + + // AC pressure sensor value + uint16_t CCU_Sen_Pressure_ro; // Bits=12 Factor= 0.1 Unit:'ATM' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t CCU_Sen_Pressure_phys; +#endif // CANDB_USE_SIGFLOAT + + // Evaporators target temperature =dbg_Sen_Eva_Target in LocalCCU-CAN + int16_t CCU_EvaTargetTemp_Val_ro; // [-] Bits=12 Factor= 0.1 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t CCU_EvaTargetTemp_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Front evaporator current temperature =dbg_Sen_Eva_F in LocalCCU-CAN + int16_t CCU_EvaCurrTempF_Val_ro; // [-] Bits=12 Factor= 0.1 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t CCU_EvaCurrTempF_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Rear evaporator current temperature =dbg_Sen_Eva_R in LocalCCU-CAN + int16_t CCU_EvaCurrTempR_Val_ro; // [-] Bits=12 Factor= 0.1 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t CCU_EvaCurrTempR_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Request to VCU for target temperature Liquid HVAC Heater + uint8_t CCU_LiquidHeaterTargetTemp_Req; // Bits= 7 Unit:'�C' + + // Rolling Counter [0 - 15] + uint8_t CCU_VCU_Msg1_RC; // Bits= 4 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} CCU_VCU_Msg1_t; + +// def @CCU_VCU_Msg2 CAN Message (790 0x316) +#define CCU_VCU_Msg2_IDE (0U) +#define CCU_VCU_Msg2_DLC (8U) +#define CCU_VCU_Msg2_CANID (0x316U) +#define CCU_VCU_Msg2_CYC (200U) + +// Value tables for @eTXV_batChiller_Err_Stat signal + +#ifndef eTXV_batChiller_Err_Stat_CCU_VCU_Msg2_No_error +#define eTXV_batChiller_Err_Stat_CCU_VCU_Msg2_No_error (0) +#endif + +#ifndef eTXV_batChiller_Err_Stat_CCU_VCU_Msg2_Supply_chain_break +#define eTXV_batChiller_Err_Stat_CCU_VCU_Msg2_Supply_chain_break (1) +#endif + +#ifndef eTXV_batChiller_Err_Stat_CCU_VCU_Msg2_Supply_chain_short_circuit +#define eTXV_batChiller_Err_Stat_CCU_VCU_Msg2_Supply_chain_short_circuit (2) +#endif + +#ifndef eTXV_batChiller_Err_Stat_CCU_VCU_Msg2_Component_malfunction +#define eTXV_batChiller_Err_Stat_CCU_VCU_Msg2_Component_malfunction (3) +#endif + +// signal: @eTXV_batChiller_Pressure_Val_ro +#define CANDB_eTXV_batChiller_Pressure_Val_ro_CovFactor (0.1) +#define CANDB_eTXV_batChiller_Pressure_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_eTXV_batChiller_Pressure_Val_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @eTXV_batChiller_Temp_Val_ro +#define CANDB_eTXV_batChiller_Temp_Val_ro_CovFactor (1) +#define CANDB_eTXV_batChiller_Temp_Val_ro_toS(x) ( (uint8_t) ((x) - (-40)) ) +#define CANDB_eTXV_batChiller_Temp_Val_ro_fromS(x) ( ((x) + (-40)) ) + +// Value tables for @eTXV_eeChiller_Err_Stat signal + +#ifndef eTXV_eeChiller_Err_Stat_CCU_VCU_Msg2_No_error +#define eTXV_eeChiller_Err_Stat_CCU_VCU_Msg2_No_error (0) +#endif + +#ifndef eTXV_eeChiller_Err_Stat_CCU_VCU_Msg2_Supply_chain_break +#define eTXV_eeChiller_Err_Stat_CCU_VCU_Msg2_Supply_chain_break (1) +#endif + +#ifndef eTXV_eeChiller_Err_Stat_CCU_VCU_Msg2_Supply_chain_short_circuit +#define eTXV_eeChiller_Err_Stat_CCU_VCU_Msg2_Supply_chain_short_circuit (2) +#endif + +#ifndef eTXV_eeChiller_Err_Stat_CCU_VCU_Msg2_Component_malfunction +#define eTXV_eeChiller_Err_Stat_CCU_VCU_Msg2_Component_malfunction (3) +#endif + +// signal: @eTXV_eeChiller_Pressure_Val_ro +#define CANDB_eTXV_eeChiller_Pressure_Val_ro_CovFactor (0.1) +#define CANDB_eTXV_eeChiller_Pressure_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_eTXV_eeChiller_Pressure_Val_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @eTXV_eeChiller_Temp_Val_ro +#define CANDB_eTXV_eeChiller_Temp_Val_ro_CovFactor (1) +#define CANDB_eTXV_eeChiller_Temp_Val_ro_toS(x) ( (uint8_t) ((x) - (-40)) ) +#define CANDB_eTXV_eeChiller_Temp_Val_ro_fromS(x) ( ((x) + (-40)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Battery chiller eTXV position status + uint8_t eTXV_batChiller_Pos_Stat : 7; // Bits= 7 Unit:'%' + + // Battery chiller eTXV error status + // 0 : "No error" + // 1 : "Supply chain break" + // 2 : "Supply chain short circuit" + // 3 : "Component malfunction" + uint8_t eTXV_batChiller_Err_Stat : 2; // Bits= 2 + + // Battery chiller eTXV pressure value + uint8_t eTXV_batChiller_Pressure_Val_ro : 6; // Bits= 6 Factor= 0.1 Unit:'MPaG' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t eTXV_batChiller_Pressure_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Battery chiller eTXV temperature value + uint8_t eTXV_batChiller_Temp_Val_ro : 7; // Bits= 7 Offset= -40 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + int8_t eTXV_batChiller_Temp_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Electrical components chiller eTXV position status + uint8_t eTXV_eeChiller_Pos_Stat : 7; // Bits= 7 Unit:'%' + + // Electrical components eTXV error status + // 0 : "No error" + // 1 : "Supply chain break" + // 2 : "Supply chain short circuit" + // 3 : "Component malfunction" + uint8_t eTXV_eeChiller_Err_Stat : 2; // Bits= 2 + + // Electrical components eTXV pressure value + uint8_t eTXV_eeChiller_Pressure_Val_ro : 6; // Bits= 6 Factor= 0.1 Unit:'MPaG' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t eTXV_eeChiller_Pressure_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Electrical components eTXV temperature value + uint8_t eTXV_eeChiller_Temp_Val_ro : 7; // Bits= 7 Offset= -40 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + int8_t eTXV_eeChiller_Temp_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Rolling Counter [0 - 15] + uint8_t CCU_VCU_Msg2_RC : 4; // Bits= 4 + +#else + + // Battery chiller eTXV position status + uint8_t eTXV_batChiller_Pos_Stat; // Bits= 7 Unit:'%' + + // Battery chiller eTXV error status + // 0 : "No error" + // 1 : "Supply chain break" + // 2 : "Supply chain short circuit" + // 3 : "Component malfunction" + uint8_t eTXV_batChiller_Err_Stat; // Bits= 2 + + // Battery chiller eTXV pressure value + uint8_t eTXV_batChiller_Pressure_Val_ro; // Bits= 6 Factor= 0.1 Unit:'MPaG' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t eTXV_batChiller_Pressure_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Battery chiller eTXV temperature value + uint8_t eTXV_batChiller_Temp_Val_ro; // Bits= 7 Offset= -40 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + int8_t eTXV_batChiller_Temp_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Electrical components chiller eTXV position status + uint8_t eTXV_eeChiller_Pos_Stat; // Bits= 7 Unit:'%' + + // Electrical components eTXV error status + // 0 : "No error" + // 1 : "Supply chain break" + // 2 : "Supply chain short circuit" + // 3 : "Component malfunction" + uint8_t eTXV_eeChiller_Err_Stat; // Bits= 2 + + // Electrical components eTXV pressure value + uint8_t eTXV_eeChiller_Pressure_Val_ro; // Bits= 6 Factor= 0.1 Unit:'MPaG' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t eTXV_eeChiller_Pressure_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Electrical components eTXV temperature value + uint8_t eTXV_eeChiller_Temp_Val_ro; // Bits= 7 Offset= -40 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + int8_t eTXV_eeChiller_Temp_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Rolling Counter [0 - 15] + uint8_t CCU_VCU_Msg2_RC; // Bits= 4 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} CCU_VCU_Msg2_t; + +// def @BCM_IC_Info_Msg CAN Message (866 0x362) +#define BCM_IC_Info_Msg_IDE (0U) +#define BCM_IC_Info_Msg_DLC (8U) +#define BCM_IC_Info_Msg_CANID (0x362U) +#define BCM_IC_Info_Msg_CYC (1000U) + +// Value tables for @BCM_WasherFluidLevel signal + +#ifndef BCM_WasherFluidLevel_BCM_IC_Info_Msg_Water_fluid_low_level +#define BCM_WasherFluidLevel_BCM_IC_Info_Msg_Water_fluid_low_level (1) +#endif + +#ifndef BCM_WasherFluidLevel_BCM_IC_Info_Msg_Washer_fluid_normal +#define BCM_WasherFluidLevel_BCM_IC_Info_Msg_Washer_fluid_normal (0) +#endif + + +// Value tables for @BCM_LvBatCharging_Stat signal + +#ifndef BCM_LvBatCharging_Stat_BCM_IC_Info_Msg_LV_Battery_Discharging +#define BCM_LvBatCharging_Stat_BCM_IC_Info_Msg_LV_Battery_Discharging (1) +#endif + +#ifndef BCM_LvBatCharging_Stat_BCM_IC_Info_Msg_LV_Battery_Charging +#define BCM_LvBatCharging_Stat_BCM_IC_Info_Msg_LV_Battery_Charging (0) +#endif + + +// Value tables for @BCM_EngStartNotif_Stat signal + +#ifndef BCM_EngStartNotif_Stat_BCM_IC_Info_Msg_Notification_Active +#define BCM_EngStartNotif_Stat_BCM_IC_Info_Msg_Notification_Active (1) +#endif + +#ifndef BCM_EngStartNotif_Stat_BCM_IC_Info_Msg_No_Notification_ +#define BCM_EngStartNotif_Stat_BCM_IC_Info_Msg_No_Notification_ (0) +#endif + + +// Value tables for @BCM_PowerDoorsNotif_Stat signal + +#ifndef BCM_PowerDoorsNotif_Stat_BCM_IC_Info_Msg_PowerDoorsDisable_notification_Active +#define BCM_PowerDoorsNotif_Stat_BCM_IC_Info_Msg_PowerDoorsDisable_notification_Active (1) +#endif + +#ifndef BCM_PowerDoorsNotif_Stat_BCM_IC_Info_Msg_PowerDoorsDisable_notification_Inactive +#define BCM_PowerDoorsNotif_Stat_BCM_IC_Info_Msg_PowerDoorsDisable_notification_Inactive (0) +#endif + + +// Value tables for @BCM_CalSteeringWhColumnReq signal + +#ifndef BCM_CalSteeringWhColumnReq_BCM_IC_Info_Msg_Calibration_Requested +#define BCM_CalSteeringWhColumnReq_BCM_IC_Info_Msg_Calibration_Requested (1) +#endif + +#ifndef BCM_CalSteeringWhColumnReq_BCM_IC_Info_Msg_Calbrration_Not_Requested +#define BCM_CalSteeringWhColumnReq_BCM_IC_Info_Msg_Calbrration_Not_Requested (0) +#endif + + +// Value tables for @BCM_AdaptiveLghtsFailure signal + +#ifndef BCM_AdaptiveLghtsFailure_BCM_IC_Info_Msg_Failure_Detect +#define BCM_AdaptiveLghtsFailure_BCM_IC_Info_Msg_Failure_Detect (1) +#endif + +#ifndef BCM_AdaptiveLghtsFailure_BCM_IC_Info_Msg_No_Failure +#define BCM_AdaptiveLghtsFailure_BCM_IC_Info_Msg_No_Failure (0) +#endif + + +// Value tables for @BCM_BrakeLightLeft_Status signal + +#ifndef BCM_BrakeLightLeft_Status_BCM_IC_Info_Msg_Left_brake_light_lamp_failure +#define BCM_BrakeLightLeft_Status_BCM_IC_Info_Msg_Left_brake_light_lamp_failure (1) +#endif + +#ifndef BCM_BrakeLightLeft_Status_BCM_IC_Info_Msg_No_failure +#define BCM_BrakeLightLeft_Status_BCM_IC_Info_Msg_No_failure (0) +#endif + + +// Value tables for @BCM_BrakeLightRight_Status signal + +#ifndef BCM_BrakeLightRight_Status_BCM_IC_Info_Msg_Right_brake_light_lamp_failure +#define BCM_BrakeLightRight_Status_BCM_IC_Info_Msg_Right_brake_light_lamp_failure (1) +#endif + +#ifndef BCM_BrakeLightRight_Status_BCM_IC_Info_Msg_No_failure +#define BCM_BrakeLightRight_Status_BCM_IC_Info_Msg_No_failure (0) +#endif + + +// Value tables for @BCM_AllWthrLght_Fault signal + +#ifndef BCM_AllWthrLght_Fault_BCM_IC_Info_Msg_Fault_detect +#define BCM_AllWthrLght_Fault_BCM_IC_Info_Msg_Fault_detect (1) +#endif + +#ifndef BCM_AllWthrLght_Fault_BCM_IC_Info_Msg_No_Fault +#define BCM_AllWthrLght_Fault_BCM_IC_Info_Msg_No_Fault (0) +#endif + + +// Value tables for @BCM_LowBeamLeft_Status signal + +#ifndef BCM_LowBeamLeft_Status_BCM_IC_Info_Msg_Left_lowbeam_lamp_failure +#define BCM_LowBeamLeft_Status_BCM_IC_Info_Msg_Left_lowbeam_lamp_failure (1) +#endif + +#ifndef BCM_LowBeamLeft_Status_BCM_IC_Info_Msg_No_failure +#define BCM_LowBeamLeft_Status_BCM_IC_Info_Msg_No_failure (0) +#endif + + +// Value tables for @BCM_LowBeamRight_Status signal + +#ifndef BCM_LowBeamRight_Status_BCM_IC_Info_Msg_Right_lowbeam_lamp_failure +#define BCM_LowBeamRight_Status_BCM_IC_Info_Msg_Right_lowbeam_lamp_failure (1) +#endif + +#ifndef BCM_LowBeamRight_Status_BCM_IC_Info_Msg_No_failure +#define BCM_LowBeamRight_Status_BCM_IC_Info_Msg_No_failure (0) +#endif + + +// Value tables for @BCM_ReverseLightsRight_Status signal + +#ifndef BCM_ReverseLightsRight_Status_BCM_IC_Info_Msg_Reverse_light_right_lamp_failure +#define BCM_ReverseLightsRight_Status_BCM_IC_Info_Msg_Reverse_light_right_lamp_failure (1) +#endif + +#ifndef BCM_ReverseLightsRight_Status_BCM_IC_Info_Msg_No_failure +#define BCM_ReverseLightsRight_Status_BCM_IC_Info_Msg_No_failure (0) +#endif + + +// Value tables for @BCM_RearLeft_FogLight_Status signal + +#ifndef BCM_RearLeft_FogLight_Status_BCM_IC_Info_Msg_Light_failure +#define BCM_RearLeft_FogLight_Status_BCM_IC_Info_Msg_Light_failure (1) +#endif + +#ifndef BCM_RearLeft_FogLight_Status_BCM_IC_Info_Msg_No_failure +#define BCM_RearLeft_FogLight_Status_BCM_IC_Info_Msg_No_failure (0) +#endif + + +// Value tables for @BCM_RearRight_FogLight_Status signal + +#ifndef BCM_RearRight_FogLight_Status_BCM_IC_Info_Msg_Light_failure +#define BCM_RearRight_FogLight_Status_BCM_IC_Info_Msg_Light_failure (1) +#endif + +#ifndef BCM_RearRight_FogLight_Status_BCM_IC_Info_Msg_No_failure +#define BCM_RearRight_FogLight_Status_BCM_IC_Info_Msg_No_failure (0) +#endif + + +// Value tables for @BCM_ReverseLightsLeft_Status signal + +#ifndef BCM_ReverseLightsLeft_Status_BCM_IC_Info_Msg_Reverse_light_left_lamp_failure +#define BCM_ReverseLightsLeft_Status_BCM_IC_Info_Msg_Reverse_light_left_lamp_failure (1) +#endif + +#ifndef BCM_ReverseLightsLeft_Status_BCM_IC_Info_Msg_No_failure +#define BCM_ReverseLightsLeft_Status_BCM_IC_Info_Msg_No_failure (0) +#endif + + +// Value tables for @BCM_HighBeamLeft_Status signal + +#ifndef BCM_HighBeamLeft_Status_BCM_IC_Info_Msg_Left_highbeam_lamp_failure +#define BCM_HighBeamLeft_Status_BCM_IC_Info_Msg_Left_highbeam_lamp_failure (1) +#endif + +#ifndef BCM_HighBeamLeft_Status_BCM_IC_Info_Msg_No_failure +#define BCM_HighBeamLeft_Status_BCM_IC_Info_Msg_No_failure (0) +#endif + + +// Value tables for @BCM_HighBeamRight_Status signal + +#ifndef BCM_HighBeamRight_Status_BCM_IC_Info_Msg_Right_highbeam_lamp_failure +#define BCM_HighBeamRight_Status_BCM_IC_Info_Msg_Right_highbeam_lamp_failure (1) +#endif + +#ifndef BCM_HighBeamRight_Status_BCM_IC_Info_Msg_No_failure +#define BCM_HighBeamRight_Status_BCM_IC_Info_Msg_No_failure (0) +#endif + + +// Value tables for @BCM_PositionLight_RL_Status signal + +#ifndef BCM_PositionLight_RL_Status_BCM_IC_Info_Msg_RL_position_light_lamp_failure +#define BCM_PositionLight_RL_Status_BCM_IC_Info_Msg_RL_position_light_lamp_failure (1) +#endif + +#ifndef BCM_PositionLight_RL_Status_BCM_IC_Info_Msg_No_failure +#define BCM_PositionLight_RL_Status_BCM_IC_Info_Msg_No_failure (0) +#endif + + +// Value tables for @BCM_PositionLight_RR_Status signal + +#ifndef BCM_PositionLight_RR_Status_BCM_IC_Info_Msg_RR_position_light_lamp_failure +#define BCM_PositionLight_RR_Status_BCM_IC_Info_Msg_RR_position_light_lamp_failure (1) +#endif + +#ifndef BCM_PositionLight_RR_Status_BCM_IC_Info_Msg_No_failure +#define BCM_PositionLight_RR_Status_BCM_IC_Info_Msg_No_failure (0) +#endif + + +// Value tables for @BCM_DaytimeLightRight_Status signal + +#ifndef BCM_DaytimeLightRight_Status_BCM_IC_Info_Msg_Right_daytime_running_lamp_fault +#define BCM_DaytimeLightRight_Status_BCM_IC_Info_Msg_Right_daytime_running_lamp_fault (1) +#endif + +#ifndef BCM_DaytimeLightRight_Status_BCM_IC_Info_Msg_No_failure +#define BCM_DaytimeLightRight_Status_BCM_IC_Info_Msg_No_failure (0) +#endif + + +// Value tables for @BCM_DaytimeLightLeft_Status signal + +#ifndef BCM_DaytimeLightLeft_Status_BCM_IC_Info_Msg_Left_daytime_running_lamp_failure +#define BCM_DaytimeLightLeft_Status_BCM_IC_Info_Msg_Left_daytime_running_lamp_failure (1) +#endif + +#ifndef BCM_DaytimeLightLeft_Status_BCM_IC_Info_Msg_No_failure +#define BCM_DaytimeLightLeft_Status_BCM_IC_Info_Msg_No_failure (0) +#endif + + +// Value tables for @BCM_WarningInd signal + +#ifndef BCM_WarningInd_BCM_IC_Info_Msg_Warning_requested +#define BCM_WarningInd_BCM_IC_Info_Msg_Warning_requested (1) +#endif + +#ifndef BCM_WarningInd_BCM_IC_Info_Msg_No_Warning +#define BCM_WarningInd_BCM_IC_Info_Msg_No_Warning (0) +#endif + + +// Value tables for @BCM_CorneringLightRight_Status signal + +#ifndef BCM_CorneringLightRight_Status_BCM_IC_Info_Msg_Right_cornering_light_lamp_failure +#define BCM_CorneringLightRight_Status_BCM_IC_Info_Msg_Right_cornering_light_lamp_failure (1) +#endif + +#ifndef BCM_CorneringLightRight_Status_BCM_IC_Info_Msg_No_failure +#define BCM_CorneringLightRight_Status_BCM_IC_Info_Msg_No_failure (0) +#endif + + +// Value tables for @BCM_CorneringLightLeft_Status signal + +#ifndef BCM_CorneringLightLeft_Status_BCM_IC_Info_Msg_Left_cornering_light_lamp_failure +#define BCM_CorneringLightLeft_Status_BCM_IC_Info_Msg_Left_cornering_light_lamp_failure (1) +#endif + +#ifndef BCM_CorneringLightLeft_Status_BCM_IC_Info_Msg_No_failure +#define BCM_CorneringLightLeft_Status_BCM_IC_Info_Msg_No_failure (0) +#endif + + +// Value tables for @BCM_PosLightFL_status signal + +#ifndef BCM_PosLightFL_status_BCM_IC_Info_Msg_FL_position_light_lamp_failure +#define BCM_PosLightFL_status_BCM_IC_Info_Msg_FL_position_light_lamp_failure (1) +#endif + +#ifndef BCM_PosLightFL_status_BCM_IC_Info_Msg_No_fault +#define BCM_PosLightFL_status_BCM_IC_Info_Msg_No_fault (0) +#endif + + +// Value tables for @BCM_PosLightFR_status signal + +#ifndef BCM_PosLightFR_status_BCM_IC_Info_Msg_FR_position_light_lamp_failure +#define BCM_PosLightFR_status_BCM_IC_Info_Msg_FR_position_light_lamp_failure (1) +#endif + +#ifndef BCM_PosLightFR_status_BCM_IC_Info_Msg_No_fault +#define BCM_PosLightFR_status_BCM_IC_Info_Msg_No_fault (0) +#endif + + +// Value tables for @BCM_TurnIndicatorML_Status signal + +#ifndef BCM_TurnIndicatorML_Status_BCM_IC_Info_Msg_L_mirror_turn_indicator_failure +#define BCM_TurnIndicatorML_Status_BCM_IC_Info_Msg_L_mirror_turn_indicator_failure (1) +#endif + +#ifndef BCM_TurnIndicatorML_Status_BCM_IC_Info_Msg_No_failure +#define BCM_TurnIndicatorML_Status_BCM_IC_Info_Msg_No_failure (0) +#endif + + +// Value tables for @BCM_TurnIndicatorMR_Status signal + +#ifndef BCM_TurnIndicatorMR_Status_BCM_IC_Info_Msg_R_mirror_turn_indicator_failure +#define BCM_TurnIndicatorMR_Status_BCM_IC_Info_Msg_R_mirror_turn_indicator_failure (1) +#endif + +#ifndef BCM_TurnIndicatorMR_Status_BCM_IC_Info_Msg_No_failure +#define BCM_TurnIndicatorMR_Status_BCM_IC_Info_Msg_No_failure (0) +#endif + + +// Value tables for @BCM_TurnIndicatorRL_Status signal + +#ifndef BCM_TurnIndicatorRL_Status_BCM_IC_Info_Msg_Rear_left_turn_indicator_failure +#define BCM_TurnIndicatorRL_Status_BCM_IC_Info_Msg_Rear_left_turn_indicator_failure (1) +#endif + +#ifndef BCM_TurnIndicatorRL_Status_BCM_IC_Info_Msg_No_failure +#define BCM_TurnIndicatorRL_Status_BCM_IC_Info_Msg_No_failure (0) +#endif + + +// Value tables for @BCM_TurnIndicatorRR_Status signal + +#ifndef BCM_TurnIndicatorRR_Status_BCM_IC_Info_Msg_RearRight_turn_indicator_failure +#define BCM_TurnIndicatorRR_Status_BCM_IC_Info_Msg_RearRight_turn_indicator_failure (1) +#endif + +#ifndef BCM_TurnIndicatorRR_Status_BCM_IC_Info_Msg_No_failure +#define BCM_TurnIndicatorRR_Status_BCM_IC_Info_Msg_No_failure (0) +#endif + + +// Value tables for @BCM_TurnIndicatorFL_Status signal + +#ifndef BCM_TurnIndicatorFL_Status_BCM_IC_Info_Msg_FL_turn_indicator_failure +#define BCM_TurnIndicatorFL_Status_BCM_IC_Info_Msg_FL_turn_indicator_failure (1) +#endif + +#ifndef BCM_TurnIndicatorFL_Status_BCM_IC_Info_Msg_No_failure +#define BCM_TurnIndicatorFL_Status_BCM_IC_Info_Msg_No_failure (0) +#endif + + +// Value tables for @BCM_TurnIndicatorFR_Status signal + +#ifndef BCM_TurnIndicatorFR_Status_BCM_IC_Info_Msg_FR_turn_indicator_failure +#define BCM_TurnIndicatorFR_Status_BCM_IC_Info_Msg_FR_turn_indicator_failure (1) +#endif + +#ifndef BCM_TurnIndicatorFR_Status_BCM_IC_Info_Msg_No_failure +#define BCM_TurnIndicatorFR_Status_BCM_IC_Info_Msg_No_failure (0) +#endif + + +// Value tables for @BCM_HeadLghtLevelinglFailure signal + +#ifndef BCM_HeadLghtLevelinglFailure_BCM_IC_Info_Msg_True +#define BCM_HeadLghtLevelinglFailure_BCM_IC_Info_Msg_True (1) +#endif + +#ifndef BCM_HeadLghtLevelinglFailure_BCM_IC_Info_Msg_False +#define BCM_HeadLghtLevelinglFailure_BCM_IC_Info_Msg_False (0) +#endif + + +// Value tables for @BCM_PowerSteeringCtrlFault signal + +#ifndef BCM_PowerSteeringCtrlFault_BCM_IC_Info_Msg_Steering_Fluid_Control_Fault +#define BCM_PowerSteeringCtrlFault_BCM_IC_Info_Msg_Steering_Fluid_Control_Fault (1) +#endif + +#ifndef BCM_PowerSteeringCtrlFault_BCM_IC_Info_Msg_No_Action +#define BCM_PowerSteeringCtrlFault_BCM_IC_Info_Msg_No_Action (0) +#endif + + +// Value tables for @BCM_LvBat1_SOC signal + +#ifndef BCM_LvBat1_SOC_BCM_IC_Info_Msg_Battery_Discharge +#define BCM_LvBat1_SOC_BCM_IC_Info_Msg_Battery_Discharge (3) +#endif + +#ifndef BCM_LvBat1_SOC_BCM_IC_Info_Msg_Battery_Requiered_Charging +#define BCM_LvBat1_SOC_BCM_IC_Info_Msg_Battery_Requiered_Charging (2) +#endif + +#ifndef BCM_LvBat1_SOC_BCM_IC_Info_Msg_Battery_Charge_Normal_ +#define BCM_LvBat1_SOC_BCM_IC_Info_Msg_Battery_Charge_Normal_ (1) +#endif + +#ifndef BCM_LvBat1_SOC_BCM_IC_Info_Msg_Battery_Charge_Full +#define BCM_LvBat1_SOC_BCM_IC_Info_Msg_Battery_Charge_Full (0) +#endif + + +// Value tables for @BCM_LvBat1_SOH signal + +#ifndef BCM_LvBat1_SOH_BCM_IC_Info_Msg_Extemally_Low_State_of_Health_ +#define BCM_LvBat1_SOH_BCM_IC_Info_Msg_Extemally_Low_State_of_Health_ (2) +#endif + +#ifndef BCM_LvBat1_SOH_BCM_IC_Info_Msg_Low_State_of_Health_Battery +#define BCM_LvBat1_SOH_BCM_IC_Info_Msg_Low_State_of_Health_Battery (1) +#endif + +#ifndef BCM_LvBat1_SOH_BCM_IC_Info_Msg_Normal_State_of_Health_Battery +#define BCM_LvBat1_SOH_BCM_IC_Info_Msg_Normal_State_of_Health_Battery (0) +#endif + + +// Value tables for @BCM_HighBeamAutoStatus signal + +#ifndef BCM_HighBeamAutoStatus_BCM_IC_Info_Msg_Auto_High_Beam_Unavailable +#define BCM_HighBeamAutoStatus_BCM_IC_Info_Msg_Auto_High_Beam_Unavailable (1) +#endif + +#ifndef BCM_HighBeamAutoStatus_BCM_IC_Info_Msg_Auto_High_Beam_Available +#define BCM_HighBeamAutoStatus_BCM_IC_Info_Msg_Auto_High_Beam_Available (0) +#endif + + +// Value tables for @BCM_ExteriorSystemStatus signal + +#ifndef BCM_ExteriorSystemStatus_BCM_IC_Info_Msg_Exterior_Lights_System_Failure +#define BCM_ExteriorSystemStatus_BCM_IC_Info_Msg_Exterior_Lights_System_Failure (1) +#endif + +#ifndef BCM_ExteriorSystemStatus_BCM_IC_Info_Msg_No_Failure +#define BCM_ExteriorSystemStatus_BCM_IC_Info_Msg_No_Failure (0) +#endif + + +// Value tables for @BCM_LvBat1_SOC_Pct signal + +#ifndef BCM_LvBat1_SOC_Pct_BCM_IC_Info_Msg_Error +#define BCM_LvBat1_SOC_Pct_BCM_IC_Info_Msg_Error (127) +#endif + + +// Value tables for @BCM_TrunkLidOpenWarn_Req signal + +#ifndef BCM_TrunkLidOpenWarn_Req_BCM_IC_Info_Msg_Trunk_lid_is_opened_Soft_Roof_cannot_be_manipulated +#define BCM_TrunkLidOpenWarn_Req_BCM_IC_Info_Msg_Trunk_lid_is_opened_Soft_Roof_cannot_be_manipulated (1) +#endif + +#ifndef BCM_TrunkLidOpenWarn_Req_BCM_IC_Info_Msg_No_restrictions_on_manipulating_Soft_Roof +#define BCM_TrunkLidOpenWarn_Req_BCM_IC_Info_Msg_No_restrictions_on_manipulating_Soft_Roof (0) +#endif + + +// Value tables for @BCM_FuelLvl_HMI signal + +#ifndef BCM_FuelLvl_HMI_BCM_IC_Info_Msg_Fault +#define BCM_FuelLvl_HMI_BCM_IC_Info_Msg_Fault (127) +#endif + +#ifndef BCM_FuelLvl_HMI_BCM_IC_Info_Msg___Empty_Tank +#define BCM_FuelLvl_HMI_BCM_IC_Info_Msg___Empty_Tank (0) +#endif + + +// Value tables for @BCM_SRoofManipulationWarn_Req signal + +#ifndef BCM_SRoofManipulationWarn_Req_BCM_IC_Info_Msg_Soft_Roof_is_not_in_completely_open_or_close_position_Trunk_lid_cannot_be_opened +#define BCM_SRoofManipulationWarn_Req_BCM_IC_Info_Msg_Soft_Roof_is_not_in_completely_open_or_close_position_Trunk_lid_cannot_be_opened (1) +#endif + +#ifndef BCM_SRoofManipulationWarn_Req_BCM_IC_Info_Msg_No_restrictions_on_opening_Trunk_lid +#define BCM_SRoofManipulationWarn_Req_BCM_IC_Info_Msg_No_restrictions_on_opening_Trunk_lid (0) +#endif + + +// Value tables for @BCM_DrvMdLim_Stat signal + +#ifndef BCM_DrvMdLim_Stat_BCM_IC_Info_Msg_Warning_Active +#define BCM_DrvMdLim_Stat_BCM_IC_Info_Msg_Warning_Active (1) +#endif + +#ifndef BCM_DrvMdLim_Stat_BCM_IC_Info_Msg_Warning_Inactive +#define BCM_DrvMdLim_Stat_BCM_IC_Info_Msg_Warning_Inactive (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Washer Fluid Level + // 1 : "Water fluid low level" + // 0 : "Washer fluid normal" + uint8_t BCM_WasherFluidLevel : 1; // Bits= 1 + + // State of charging a Low Voltage Battery + // 1 : "LV Battery Discharging" + // 0 : "LV Battery Charging" + uint8_t BCM_LvBatCharging_Stat : 1; // Bits= 1 + + // User notification to smoothly transit from �engine running in remote start� mode to �Drive� mode + // 1 : "Notification Active" + // 0 : "No Notification " + uint8_t BCM_EngStartNotif_Stat : 1; // Bits= 1 + + // Notice of limitation of operation of electric door drive + // 1 : "PowerDoorsDisable notification Active" + // 0 : "PowerDoorsDisable notification Inactive" + uint8_t BCM_PowerDoorsNotif_Stat : 1; // Bits= 1 + + // Request to notify user about steering whell calibration + // 1 : "Calibration Requested" + // 0 : "Calbrration Not Requested" + uint8_t BCM_CalSteeringWhColumnReq : 1; // Bits= 1 + + // The failure in exterior lights,which changes the light beam when turning. + // 1 : "Failure Detect" + // 0 : "No Failure" + uint8_t BCM_AdaptiveLghtsFailure : 1; // Bits= 1 + + // Current status of brake lights + // 1 : "Left brake light lamp failure" + // 0 : "No failure" + uint8_t BCM_BrakeLightLeft_Status : 1; // Bits= 1 + + // Current status of brake lights + // 1 : "Right brake light lamp failure" + // 0 : "No failure" + uint8_t BCM_BrakeLightRight_Status : 1; // Bits= 1 + + // Error status of all-weather function + // 1 : "Fault detect" + // 0 : "No Fault" + uint8_t BCM_AllWthrLght_Fault : 1; // Bits= 1 + + // Current status of low-beam lights + // 1 : "Left low-beam lamp failure" + // 0 : "No failure" + uint8_t BCM_LowBeamLeft_Status : 1; // Bits= 1 + + // Current status of low-beam lights + // 1 : "Right low-beam lamp failure" + // 0 : "No failure" + uint8_t BCM_LowBeamRight_Status : 1; // Bits= 1 + + // Current status of reverse lights + // 1 : "Reverse light right lamp failure" + // 0 : "No failure" + uint8_t BCM_ReverseLightsRight_Status : 1; // Bits= 1 + + // Error status of rear left fog light + // 1 : "Light failure" + // 0 : "No failure" + uint8_t BCM_RearLeft_FogLight_Status : 1; // Bits= 1 + + // Error status of rear right fog light + // 1 : "Light failure" + // 0 : "No failure" + uint8_t BCM_RearRight_FogLight_Status : 1; // Bits= 1 + + // Current status of reverse lights + // 1 : "Reverse light left lamp failure" + // 0 : "No failure" + uint8_t BCM_ReverseLightsLeft_Status : 1; // Bits= 1 + + // Current status of high-beam lights + // 1 : "Left high-beam lamp failure" + // 0 : "No failure" + uint8_t BCM_HighBeamLeft_Status : 1; // Bits= 1 + + // Current status of high-beam lights + // 1 : "Right high-beam lamp failure" + // 0 : "No failure" + uint8_t BCM_HighBeamRight_Status : 1; // Bits= 1 + + // Error status of rear left position light + // 1 : "RL position light lamp failure" + // 0 : "No failure" + uint8_t BCM_PositionLight_RL_Status : 1; // Bits= 1 + + // Error status of rear right position light + // 1 : "RR position light lamp failure" + // 0 : "No failure" + uint8_t BCM_PositionLight_RR_Status : 1; // Bits= 1 + + // Current status of daytime running lights / position lights + // 1 : "Right daytime running lamp fault" + // 0 : "No failure" + uint8_t BCM_DaytimeLightRight_Status : 1; // Bits= 1 + + // Current status of daytime running lights / position lights + // 1 : "Left daytime running lamp failure" + // 0 : "No failure" + uint8_t BCM_DaytimeLightLeft_Status : 1; // Bits= 1 + + // Request a warning message to be displayed on IC: + // $0 = No Warning + // $1 = Warning requested + // 1 : "Warning requested" + // 0 : "No Warning" + uint8_t BCM_WarningInd : 1; // Bits= 1 + + // Current status of cornering lights + // 1 : "Right cornering light lamp failure" + // 0 : "No failure" + uint8_t BCM_CorneringLightRight_Status : 1; // Bits= 1 + + // Current status of cornering lights + // 1 : "Left cornering light lamp failure" + // 0 : "No failure" + uint8_t BCM_CorneringLightLeft_Status : 1; // Bits= 1 + + // Error status of front left position light + // 1 : "FL position light lamp failure" + // 0 : "No fault" + uint8_t BCM_PosLightFL_status : 1; // Bits= 1 + + // Error status of front right position light + // 1 : "FR position light lamp failure" + // 0 : "No fault" + uint8_t BCM_PosLightFR_status : 1; // Bits= 1 + + // Error status of side left direction indicator + // 1 : "L mirror turn indicator failure" + // 0 : "No failure" + uint8_t BCM_TurnIndicatorML_Status : 1; // Bits= 1 + + // Error status of side right direction indicator + // 1 : "R mirror turn indicator failure" + // 0 : "No failure" + uint8_t BCM_TurnIndicatorMR_Status : 1; // Bits= 1 + + // Error status of rear left direction indicator + // 1 : "Rear left turn indicator failure" + // 0 : "No failure" + uint8_t BCM_TurnIndicatorRL_Status : 1; // Bits= 1 + + // Error status of rear right direction indicator + // 1 : "RearRight turn indicator failure" + // 0 : "No failure" + uint8_t BCM_TurnIndicatorRR_Status : 1; // Bits= 1 + + // Error status of front left direction indicator + // 1 : "FL turn indicator failure" + // 0 : "No failure" + uint8_t BCM_TurnIndicatorFL_Status : 1; // Bits= 1 + + // Error status of front right direction indicator + // 1 : "FR turn indicator failure" + // 0 : "No failure" + uint8_t BCM_TurnIndicatorFR_Status : 1; // Bits= 1 + + // Indicate to the driver that the leveling system has failed + // $0 = FALSE + // $1 = TRUE + // 1 : "True" + // 0 : "False" + uint8_t BCM_HeadLghtLevelinglFailure : 1; // Bits= 1 + + // Request the power steering fluid control fault indication: + // $0 = No Action + // $1 = Stering Fluid Control Fault + // 1 : "Steering Fluid Control Fault" + // 0 : "No Action" + uint8_t BCM_PowerSteeringCtrlFault : 1; // Bits= 1 + + // State of Charge main Low Battery Voltage + // 3 : "Battery Discharge" + // 2 : "Battery Requiered Charging" + // 1 : "Battery Charge Normal " + // 0 : "Battery Charge Full" + uint8_t BCM_LvBat1_SOC : 2; // Bits= 2 + + // State of Health main Low Battery Voltage + // 2 : "Extemally Low State of Health " + // 1 : "Low State of Health Battery" + // 0 : "Normal State of Health Battery" + uint8_t BCM_LvBat1_SOH : 2; // Bits= 2 + + // State of availability auto high beam function + // 1 : "Auto High Beam Unavailable" + // 0 : "Auto High Beam Available" + uint8_t BCM_HighBeamAutoStatus : 1; // Bits= 1 + + // General failure of exterior light system + // 1 : "Exterior Lights System Failure" + // 0 : "No Failure" + uint8_t BCM_ExteriorSystemStatus : 1; // Bits= 1 + + // SOC of LV battery in percents + // 127 : "Error" + uint8_t BCM_LvBat1_SOC_Pct : 7; // Bits= 7 Unit:'%' + + // Indicates to user inability of soft roof control due to trunk lid open + // 1 : "Trunk lid is opened, Soft Roof cannot be manipulated" + // 0 : "No restrictions on manipulating Soft Roof" + uint8_t BCM_TrunkLidOpenWarn_Req : 1; // Bits= 1 + + // Fuel Level in percents + // 127 : "Fault" + // 0 : "0% - Empty Tank" + uint8_t BCM_FuelLvl_HMI : 7; // Bits= 7 Unit:'%' + + // Indicates to user inability of open trunk lid due to soft roof control + // 1 : "Soft Roof is not in completely open or close position, Trunk lid cannot be opened" + // 0 : "No restrictions on opening Trunk lid" + uint8_t BCM_SRoofManipulationWarn_Req : 1; // Bits= 1 + + // Automatic mode change alert + // 1 : "Warning Active" + // 0 : "Warning Inactive" + uint8_t BCM_DrvMdLim_Stat : 1; // Bits= 1 + +#else + + // Washer Fluid Level + // 1 : "Water fluid low level" + // 0 : "Washer fluid normal" + uint8_t BCM_WasherFluidLevel; // Bits= 1 + + // State of charging a Low Voltage Battery + // 1 : "LV Battery Discharging" + // 0 : "LV Battery Charging" + uint8_t BCM_LvBatCharging_Stat; // Bits= 1 + + // User notification to smoothly transit from �engine running in remote start� mode to �Drive� mode + // 1 : "Notification Active" + // 0 : "No Notification " + uint8_t BCM_EngStartNotif_Stat; // Bits= 1 + + // Notice of limitation of operation of electric door drive + // 1 : "PowerDoorsDisable notification Active" + // 0 : "PowerDoorsDisable notification Inactive" + uint8_t BCM_PowerDoorsNotif_Stat; // Bits= 1 + + // Request to notify user about steering whell calibration + // 1 : "Calibration Requested" + // 0 : "Calbrration Not Requested" + uint8_t BCM_CalSteeringWhColumnReq; // Bits= 1 + + // The failure in exterior lights,which changes the light beam when turning. + // 1 : "Failure Detect" + // 0 : "No Failure" + uint8_t BCM_AdaptiveLghtsFailure; // Bits= 1 + + // Current status of brake lights + // 1 : "Left brake light lamp failure" + // 0 : "No failure" + uint8_t BCM_BrakeLightLeft_Status; // Bits= 1 + + // Current status of brake lights + // 1 : "Right brake light lamp failure" + // 0 : "No failure" + uint8_t BCM_BrakeLightRight_Status; // Bits= 1 + + // Error status of all-weather function + // 1 : "Fault detect" + // 0 : "No Fault" + uint8_t BCM_AllWthrLght_Fault; // Bits= 1 + + // Current status of low-beam lights + // 1 : "Left low-beam lamp failure" + // 0 : "No failure" + uint8_t BCM_LowBeamLeft_Status; // Bits= 1 + + // Current status of low-beam lights + // 1 : "Right low-beam lamp failure" + // 0 : "No failure" + uint8_t BCM_LowBeamRight_Status; // Bits= 1 + + // Current status of reverse lights + // 1 : "Reverse light right lamp failure" + // 0 : "No failure" + uint8_t BCM_ReverseLightsRight_Status; // Bits= 1 + + // Error status of rear left fog light + // 1 : "Light failure" + // 0 : "No failure" + uint8_t BCM_RearLeft_FogLight_Status; // Bits= 1 + + // Error status of rear right fog light + // 1 : "Light failure" + // 0 : "No failure" + uint8_t BCM_RearRight_FogLight_Status; // Bits= 1 + + // Current status of reverse lights + // 1 : "Reverse light left lamp failure" + // 0 : "No failure" + uint8_t BCM_ReverseLightsLeft_Status; // Bits= 1 + + // Current status of high-beam lights + // 1 : "Left high-beam lamp failure" + // 0 : "No failure" + uint8_t BCM_HighBeamLeft_Status; // Bits= 1 + + // Current status of high-beam lights + // 1 : "Right high-beam lamp failure" + // 0 : "No failure" + uint8_t BCM_HighBeamRight_Status; // Bits= 1 + + // Error status of rear left position light + // 1 : "RL position light lamp failure" + // 0 : "No failure" + uint8_t BCM_PositionLight_RL_Status; // Bits= 1 + + // Error status of rear right position light + // 1 : "RR position light lamp failure" + // 0 : "No failure" + uint8_t BCM_PositionLight_RR_Status; // Bits= 1 + + // Current status of daytime running lights / position lights + // 1 : "Right daytime running lamp fault" + // 0 : "No failure" + uint8_t BCM_DaytimeLightRight_Status; // Bits= 1 + + // Current status of daytime running lights / position lights + // 1 : "Left daytime running lamp failure" + // 0 : "No failure" + uint8_t BCM_DaytimeLightLeft_Status; // Bits= 1 + + // Request a warning message to be displayed on IC: + // $0 = No Warning + // $1 = Warning requested + // 1 : "Warning requested" + // 0 : "No Warning" + uint8_t BCM_WarningInd; // Bits= 1 + + // Current status of cornering lights + // 1 : "Right cornering light lamp failure" + // 0 : "No failure" + uint8_t BCM_CorneringLightRight_Status; // Bits= 1 + + // Current status of cornering lights + // 1 : "Left cornering light lamp failure" + // 0 : "No failure" + uint8_t BCM_CorneringLightLeft_Status; // Bits= 1 + + // Error status of front left position light + // 1 : "FL position light lamp failure" + // 0 : "No fault" + uint8_t BCM_PosLightFL_status; // Bits= 1 + + // Error status of front right position light + // 1 : "FR position light lamp failure" + // 0 : "No fault" + uint8_t BCM_PosLightFR_status; // Bits= 1 + + // Error status of side left direction indicator + // 1 : "L mirror turn indicator failure" + // 0 : "No failure" + uint8_t BCM_TurnIndicatorML_Status; // Bits= 1 + + // Error status of side right direction indicator + // 1 : "R mirror turn indicator failure" + // 0 : "No failure" + uint8_t BCM_TurnIndicatorMR_Status; // Bits= 1 + + // Error status of rear left direction indicator + // 1 : "Rear left turn indicator failure" + // 0 : "No failure" + uint8_t BCM_TurnIndicatorRL_Status; // Bits= 1 + + // Error status of rear right direction indicator + // 1 : "RearRight turn indicator failure" + // 0 : "No failure" + uint8_t BCM_TurnIndicatorRR_Status; // Bits= 1 + + // Error status of front left direction indicator + // 1 : "FL turn indicator failure" + // 0 : "No failure" + uint8_t BCM_TurnIndicatorFL_Status; // Bits= 1 + + // Error status of front right direction indicator + // 1 : "FR turn indicator failure" + // 0 : "No failure" + uint8_t BCM_TurnIndicatorFR_Status; // Bits= 1 + + // Indicate to the driver that the leveling system has failed + // $0 = FALSE + // $1 = TRUE + // 1 : "True" + // 0 : "False" + uint8_t BCM_HeadLghtLevelinglFailure; // Bits= 1 + + // Request the power steering fluid control fault indication: + // $0 = No Action + // $1 = Stering Fluid Control Fault + // 1 : "Steering Fluid Control Fault" + // 0 : "No Action" + uint8_t BCM_PowerSteeringCtrlFault; // Bits= 1 + + // State of Charge main Low Battery Voltage + // 3 : "Battery Discharge" + // 2 : "Battery Requiered Charging" + // 1 : "Battery Charge Normal " + // 0 : "Battery Charge Full" + uint8_t BCM_LvBat1_SOC; // Bits= 2 + + // State of Health main Low Battery Voltage + // 2 : "Extemally Low State of Health " + // 1 : "Low State of Health Battery" + // 0 : "Normal State of Health Battery" + uint8_t BCM_LvBat1_SOH; // Bits= 2 + + // State of availability auto high beam function + // 1 : "Auto High Beam Unavailable" + // 0 : "Auto High Beam Available" + uint8_t BCM_HighBeamAutoStatus; // Bits= 1 + + // General failure of exterior light system + // 1 : "Exterior Lights System Failure" + // 0 : "No Failure" + uint8_t BCM_ExteriorSystemStatus; // Bits= 1 + + // SOC of LV battery in percents + // 127 : "Error" + uint8_t BCM_LvBat1_SOC_Pct; // Bits= 7 Unit:'%' + + // Indicates to user inability of soft roof control due to trunk lid open + // 1 : "Trunk lid is opened, Soft Roof cannot be manipulated" + // 0 : "No restrictions on manipulating Soft Roof" + uint8_t BCM_TrunkLidOpenWarn_Req; // Bits= 1 + + // Fuel Level in percents + // 127 : "Fault" + // 0 : "0% - Empty Tank" + uint8_t BCM_FuelLvl_HMI; // Bits= 7 Unit:'%' + + // Indicates to user inability of open trunk lid due to soft roof control + // 1 : "Soft Roof is not in completely open or close position, Trunk lid cannot be opened" + // 0 : "No restrictions on opening Trunk lid" + uint8_t BCM_SRoofManipulationWarn_Req; // Bits= 1 + + // Automatic mode change alert + // 1 : "Warning Active" + // 0 : "Warning Inactive" + uint8_t BCM_DrvMdLim_Stat; // Bits= 1 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} BCM_IC_Info_Msg_t; + +// def @BCM_CLIMATIC_DATA CAN Message (869 0x365) +#define BCM_CLIMATIC_DATA_IDE (0U) +#define BCM_CLIMATIC_DATA_DLC (6U) +#define BCM_CLIMATIC_DATA_CANID (0x365U) +#define BCM_CLIMATIC_DATA_CYC (250U) +// signal: @SolarSensRightVal_ro +#define CANDB_SolarSensRightVal_ro_CovFactor (4.01575) +#define CANDB_SolarSensRightVal_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (4.01575)) ) +#define CANDB_SolarSensRightVal_ro_fromS(x) ( (((x) * (4.01575)) + (0.0)) ) + +// Value tables for @BCM_WipeLowTempWarn_Req signal + +#ifndef BCM_WipeLowTempWarn_Req_BCM_CLIMATIC_DATA_Low_temp_warning_requested +#define BCM_WipeLowTempWarn_Req_BCM_CLIMATIC_DATA_Low_temp_warning_requested (1) +#endif + +#ifndef BCM_WipeLowTempWarn_Req_BCM_CLIMATIC_DATA_No_request +#define BCM_WipeLowTempWarn_Req_BCM_CLIMATIC_DATA_No_request (0) +#endif + + +// Value tables for @FrontWindowHeating_Status signal + +#ifndef FrontWindowHeating_Status_BCM_CLIMATIC_DATA_Heating_ON +#define FrontWindowHeating_Status_BCM_CLIMATIC_DATA_Heating_ON (1) +#endif + +#ifndef FrontWindowHeating_Status_BCM_CLIMATIC_DATA_Heating_OFF +#define FrontWindowHeating_Status_BCM_CLIMATIC_DATA_Heating_OFF (0) +#endif + + +// Value tables for @RearWindowHeating_Status signal + +#ifndef RearWindowHeating_Status_BCM_CLIMATIC_DATA_Heating_ON +#define RearWindowHeating_Status_BCM_CLIMATIC_DATA_Heating_ON (1) +#endif + +#ifndef RearWindowHeating_Status_BCM_CLIMATIC_DATA_Heating_OFF +#define RearWindowHeating_Status_BCM_CLIMATIC_DATA_Heating_OFF (0) +#endif + + +// Value tables for @SWM_Heating_Req signal + +#ifndef SWM_Heating_Req_BCM_CLIMATIC_DATA_Fault +#define SWM_Heating_Req_BCM_CLIMATIC_DATA_Fault (3) +#endif + +#ifndef SWM_Heating_Req_BCM_CLIMATIC_DATA_Heating_OFF +#define SWM_Heating_Req_BCM_CLIMATIC_DATA_Heating_OFF (2) +#endif + +#ifndef SWM_Heating_Req_BCM_CLIMATIC_DATA_Heating_ON +#define SWM_Heating_Req_BCM_CLIMATIC_DATA_Heating_ON (1) +#endif + +#ifndef SWM_Heating_Req_BCM_CLIMATIC_DATA_Unknown +#define SWM_Heating_Req_BCM_CLIMATIC_DATA_Unknown (0) +#endif + + +// Value tables for @BCM_RearWindowHeating_Cmd signal + +#ifndef BCM_RearWindowHeating_Cmd_BCM_CLIMATIC_DATA_Heating_ON +#define BCM_RearWindowHeating_Cmd_BCM_CLIMATIC_DATA_Heating_ON (1) +#endif + +#ifndef BCM_RearWindowHeating_Cmd_BCM_CLIMATIC_DATA_Heating_OFF +#define BCM_RearWindowHeating_Cmd_BCM_CLIMATIC_DATA_Heating_OFF (0) +#endif + + +// Value tables for @BCM_SteerWheelHeating_Stat signal + +#ifndef BCM_SteerWheelHeating_Stat_BCM_CLIMATIC_DATA_Heating_ON +#define BCM_SteerWheelHeating_Stat_BCM_CLIMATIC_DATA_Heating_ON (1) +#endif + +#ifndef BCM_SteerWheelHeating_Stat_BCM_CLIMATIC_DATA_Heating_OFF +#define BCM_SteerWheelHeating_Stat_BCM_CLIMATIC_DATA_Heating_OFF (0) +#endif + + +// Value tables for @RainDetected signal + +#ifndef RainDetected_BCM_CLIMATIC_DATA_TRUE +#define RainDetected_BCM_CLIMATIC_DATA_TRUE (1) +#endif + +#ifndef RainDetected_BCM_CLIMATIC_DATA_FALSE +#define RainDetected_BCM_CLIMATIC_DATA_FALSE (0) +#endif + +// signal: @SolarSensLeftVal_ro +#define CANDB_SolarSensLeftVal_ro_CovFactor (4.01575) +#define CANDB_SolarSensLeftVal_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (4.01575)) ) +#define CANDB_SolarSensLeftVal_ro_fromS(x) ( (((x) * (4.01575)) + (0.0)) ) + +// Value tables for @SideWindowHeating_Status signal + +#ifndef SideWindowHeating_Status_BCM_CLIMATIC_DATA_Heating_ON +#define SideWindowHeating_Status_BCM_CLIMATIC_DATA_Heating_ON (1) +#endif + +#ifndef SideWindowHeating_Status_BCM_CLIMATIC_DATA_Heating_OFF +#define SideWindowHeating_Status_BCM_CLIMATIC_DATA_Heating_OFF (0) +#endif + + +// Value tables for @BCM_Wiper_Stat signal + +#ifndef BCM_Wiper_Stat_BCM_CLIMATIC_DATA_Active +#define BCM_Wiper_Stat_BCM_CLIMATIC_DATA_Active (1) +#endif + +#ifndef BCM_Wiper_Stat_BCM_CLIMATIC_DATA_Inactive +#define BCM_Wiper_Stat_BCM_CLIMATIC_DATA_Inactive (0) +#endif + + +// Value tables for @BCM_SideWindowType_Stat signal + +#ifndef BCM_SideWindowType_Stat_BCM_CLIMATIC_DATA_Side_window_heaters_present +#define BCM_SideWindowType_Stat_BCM_CLIMATIC_DATA_Side_window_heaters_present (1) +#endif + +#ifndef BCM_SideWindowType_Stat_BCM_CLIMATIC_DATA_Side_window_heaters_not_present +#define BCM_SideWindowType_Stat_BCM_CLIMATIC_DATA_Side_window_heaters_not_present (0) +#endif + + +// Value tables for @BCM_MirrorHeating_Cmd signal + +#ifndef BCM_MirrorHeating_Cmd_BCM_CLIMATIC_DATA_Heating_ON +#define BCM_MirrorHeating_Cmd_BCM_CLIMATIC_DATA_Heating_ON (1) +#endif + +#ifndef BCM_MirrorHeating_Cmd_BCM_CLIMATIC_DATA_Heating_OFF +#define BCM_MirrorHeating_Cmd_BCM_CLIMATIC_DATA_Heating_OFF (0) +#endif + + +// Value tables for @BCM_WindowWashingSt signal + +#ifndef BCM_WindowWashingSt_BCM_CLIMATIC_DATA_Window_Washing_On +#define BCM_WindowWashingSt_BCM_CLIMATIC_DATA_Window_Washing_On (1) +#endif + +#ifndef BCM_WindowWashingSt_BCM_CLIMATIC_DATA_Window_Washing_Off +#define BCM_WindowWashingSt_BCM_CLIMATIC_DATA_Window_Washing_Off (0) +#endif + + +// Value tables for @BCM_GloveBox_Stat signal + +#ifndef BCM_GloveBox_Stat_BCM_CLIMATIC_DATA_Glove_box_opened +#define BCM_GloveBox_Stat_BCM_CLIMATIC_DATA_Glove_box_opened (1) +#endif + +#ifndef BCM_GloveBox_Stat_BCM_CLIMATIC_DATA_Glove_box_closed +#define BCM_GloveBox_Stat_BCM_CLIMATIC_DATA_Glove_box_closed (0) +#endif + + +// Value tables for @RainDensity signal + +#ifndef RainDensity_BCM_CLIMATIC_DATA_High_Density +#define RainDensity_BCM_CLIMATIC_DATA_High_Density (1) +#endif + +#ifndef RainDensity_BCM_CLIMATIC_DATA_Low_Density +#define RainDensity_BCM_CLIMATIC_DATA_Low_Density (0) +#endif + +// signal: @WindshieldTemp_ro +#define CANDB_WindshieldTemp_ro_CovFactor (0.5) +#define CANDB_WindshieldTemp_ro_toS(x) ( (uint8_t) (((x) - (-40.0)) / (0.5)) ) +#define CANDB_WindshieldTemp_ro_fromS(x) ( (((x) * (0.5)) + (-40.0)) ) +// signal: @WindshieldHumidity_ro +#define CANDB_WindshieldHumidity_ro_CovFactor (0.5) +#define CANDB_WindshieldHumidity_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.5)) ) +#define CANDB_WindshieldHumidity_ro_fromS(x) ( (((x) * (0.5)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Solar radiation value from right sensor + uint8_t SolarSensRightVal_ro; // Bits= 8 Factor= 4.01575 Unit:'W/qm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SolarSensRightVal_phys; +#endif // CANDB_USE_SIGFLOAT + + // Indicates to driver: front wiper pause due to low external temperature + // 1 : "Low temp warning requested" + // 0 : "No request" + uint8_t BCM_WipeLowTempWarn_Req : 1; // Bits= 1 + + // State of front window heating + // 1 : "Heating ON" + // 0 : "Heating OFF" + uint8_t FrontWindowHeating_Status : 1; // Bits= 1 + + // State of rear window heating + // 1 : "Heating ON" + // 0 : "Heating OFF" + uint8_t RearWindowHeating_Status : 1; // Bits= 1 + + // Request to on/ off steering wheel heating + // 3 : "Fault" + // 2 : "Heating OFF" + // 1 : "Heating ON" + // 0 : "Unknown" + uint8_t SWM_Heating_Req : 2; // Bits= 2 + + // Request to on/off rear window heating + // 1 : "Heating ON" + // 0 : "Heating OFF" + uint8_t BCM_RearWindowHeating_Cmd : 1; // Bits= 1 + + // Status of a steer wheel heating + // 1 : "Heating ON" + // 0 : "Heating OFF" + uint8_t BCM_SteerWheelHeating_Stat : 1; // Bits= 1 + + // Indicates the rain detected or not + // 1 : "TRUE" + // 0 : "FALSE" + uint8_t RainDetected : 1; // Bits= 1 + + // Solar radiation value from left sensor + uint8_t SolarSensLeftVal_ro; // Bits= 8 Factor= 4.01575 Unit:'W/qm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SolarSensLeftVal_phys; +#endif // CANDB_USE_SIGFLOAT + + // State of side windows heating + // 1 : "Heating ON" + // 0 : "Heating OFF" + uint8_t SideWindowHeating_Status : 1; // Bits= 1 + + // Wiper status + // Indicates the wiper status + // 1 : "Active" + // 0 : "Inactive" + uint8_t BCM_Wiper_Stat : 1; // Bits= 1 + + // Indicates side window heaters installed on vehicle or not + // 1 : "Side window heaters present" + // 0 : "Side window heaters not present" + uint8_t BCM_SideWindowType_Stat : 1; // Bits= 1 + + // Request to on/off outside miror heating + // 1 : "Heating ON" + // 0 : "Heating OFF" + uint8_t BCM_MirrorHeating_Cmd : 1; // Bits= 1 + + // Indicates the window washer status + // 1 : "Window Washing On" + // 0 : "Window Washing Off" + uint8_t BCM_WindowWashingSt : 1; // Bits= 1 + + // Current state of glove box (open or closed) + // 1 : "Glove box opened" + // 0 : "Glove box closed" + uint8_t BCM_GloveBox_Stat : 1; // Bits= 1 + + // Indicates the density of rainstatus: + // 0x0 = Low Density + // 0x1 = High Density + // 1 : "High Density" + // 0 : "Low Density" + uint8_t RainDensity : 1; // Bits= 1 + + // Temperature of front windshield zone + uint8_t WindshieldTemp_ro; // Bits= 8 Offset= -40.0 Factor= 0.5 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t WindshieldTemp_phys; +#endif // CANDB_USE_SIGFLOAT + + // Level of humidity in front windshield zone + uint8_t WindshieldHumidity_ro; // Bits= 8 Factor= 0.5 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t WindshieldHumidity_phys; +#endif // CANDB_USE_SIGFLOAT + +#else + + // Solar radiation value from right sensor + uint8_t SolarSensRightVal_ro; // Bits= 8 Factor= 4.01575 Unit:'W/qm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SolarSensRightVal_phys; +#endif // CANDB_USE_SIGFLOAT + + // Indicates to driver: front wiper pause due to low external temperature + // 1 : "Low temp warning requested" + // 0 : "No request" + uint8_t BCM_WipeLowTempWarn_Req; // Bits= 1 + + // State of front window heating + // 1 : "Heating ON" + // 0 : "Heating OFF" + uint8_t FrontWindowHeating_Status; // Bits= 1 + + // State of rear window heating + // 1 : "Heating ON" + // 0 : "Heating OFF" + uint8_t RearWindowHeating_Status; // Bits= 1 + + // Request to on/ off steering wheel heating + // 3 : "Fault" + // 2 : "Heating OFF" + // 1 : "Heating ON" + // 0 : "Unknown" + uint8_t SWM_Heating_Req; // Bits= 2 + + // Request to on/off rear window heating + // 1 : "Heating ON" + // 0 : "Heating OFF" + uint8_t BCM_RearWindowHeating_Cmd; // Bits= 1 + + // Status of a steer wheel heating + // 1 : "Heating ON" + // 0 : "Heating OFF" + uint8_t BCM_SteerWheelHeating_Stat; // Bits= 1 + + // Indicates the rain detected or not + // 1 : "TRUE" + // 0 : "FALSE" + uint8_t RainDetected; // Bits= 1 + + // Solar radiation value from left sensor + uint8_t SolarSensLeftVal_ro; // Bits= 8 Factor= 4.01575 Unit:'W/qm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SolarSensLeftVal_phys; +#endif // CANDB_USE_SIGFLOAT + + // State of side windows heating + // 1 : "Heating ON" + // 0 : "Heating OFF" + uint8_t SideWindowHeating_Status; // Bits= 1 + + // Wiper status + // Indicates the wiper status + // 1 : "Active" + // 0 : "Inactive" + uint8_t BCM_Wiper_Stat; // Bits= 1 + + // Indicates side window heaters installed on vehicle or not + // 1 : "Side window heaters present" + // 0 : "Side window heaters not present" + uint8_t BCM_SideWindowType_Stat; // Bits= 1 + + // Request to on/off outside miror heating + // 1 : "Heating ON" + // 0 : "Heating OFF" + uint8_t BCM_MirrorHeating_Cmd; // Bits= 1 + + // Indicates the window washer status + // 1 : "Window Washing On" + // 0 : "Window Washing Off" + uint8_t BCM_WindowWashingSt; // Bits= 1 + + // Current state of glove box (open or closed) + // 1 : "Glove box opened" + // 0 : "Glove box closed" + uint8_t BCM_GloveBox_Stat; // Bits= 1 + + // Indicates the density of rainstatus: + // 0x0 = Low Density + // 0x1 = High Density + // 1 : "High Density" + // 0 : "Low Density" + uint8_t RainDensity; // Bits= 1 + + // Temperature of front windshield zone + uint8_t WindshieldTemp_ro; // Bits= 8 Offset= -40.0 Factor= 0.5 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t WindshieldTemp_phys; +#endif // CANDB_USE_SIGFLOAT + + // Level of humidity in front windshield zone + uint8_t WindshieldHumidity_ro; // Bits= 8 Factor= 0.5 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t WindshieldHumidity_phys; +#endif // CANDB_USE_SIGFLOAT + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} BCM_CLIMATIC_DATA_t; + +// def @DMFL_SMFL_REQ_CTR_SEATS CAN Message (871 0x367) +#define DMFL_SMFL_REQ_CTR_SEATS_IDE (0U) +#define DMFL_SMFL_REQ_CTR_SEATS_DLC (3U) +#define DMFL_SMFL_REQ_CTR_SEATS_CANID (0x367U) +#define DMFL_SMFL_REQ_CTR_SEATS_CYC (100U) + +// Value tables for @DMFL_SeatMemReq signal + +#ifndef DMFL_SeatMemReq_DMFL_SMFL_REQ_CTR_SEATS_request_to_upload_mem_3 +#define DMFL_SeatMemReq_DMFL_SMFL_REQ_CTR_SEATS_request_to_upload_mem_3 (6) +#endif + +#ifndef DMFL_SeatMemReq_DMFL_SMFL_REQ_CTR_SEATS_request_to_upload_mem_2 +#define DMFL_SeatMemReq_DMFL_SMFL_REQ_CTR_SEATS_request_to_upload_mem_2 (5) +#endif + +#ifndef DMFL_SeatMemReq_DMFL_SMFL_REQ_CTR_SEATS_request_to_upload_mem_1 +#define DMFL_SeatMemReq_DMFL_SMFL_REQ_CTR_SEATS_request_to_upload_mem_1 (4) +#endif + +#ifndef DMFL_SeatMemReq_DMFL_SMFL_REQ_CTR_SEATS_request_to_save_mem_3 +#define DMFL_SeatMemReq_DMFL_SMFL_REQ_CTR_SEATS_request_to_save_mem_3 (3) +#endif + +#ifndef DMFL_SeatMemReq_DMFL_SMFL_REQ_CTR_SEATS_request_to_save_mem_2 +#define DMFL_SeatMemReq_DMFL_SMFL_REQ_CTR_SEATS_request_to_save_mem_2 (2) +#endif + +#ifndef DMFL_SeatMemReq_DMFL_SMFL_REQ_CTR_SEATS_request_to_save_mem_1 +#define DMFL_SeatMemReq_DMFL_SMFL_REQ_CTR_SEATS_request_to_save_mem_1 (1) +#endif + +#ifndef DMFL_SeatMemReq_DMFL_SMFL_REQ_CTR_SEATS_No_request +#define DMFL_SeatMemReq_DMFL_SMFL_REQ_CTR_SEATS_No_request (0) +#endif + + +// Value tables for @DMFL_SeatHeightReq signal + +#ifndef DMFL_SeatHeightReq_DMFL_SMFL_REQ_CTR_SEATS_Reserved +#define DMFL_SeatHeightReq_DMFL_SMFL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef DMFL_SeatHeightReq_DMFL_SMFL_REQ_CTR_SEATS_Decrease +#define DMFL_SeatHeightReq_DMFL_SMFL_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef DMFL_SeatHeightReq_DMFL_SMFL_REQ_CTR_SEATS_Increase +#define DMFL_SeatHeightReq_DMFL_SMFL_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef DMFL_SeatHeightReq_DMFL_SMFL_REQ_CTR_SEATS_No_action +#define DMFL_SeatHeightReq_DMFL_SMFL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @DMFL_FrontPass_Req signal + +#ifndef DMFL_FrontPass_Req_DMFL_SMFL_REQ_CTR_SEATS_Seat_control_change_requested +#define DMFL_FrontPass_Req_DMFL_SMFL_REQ_CTR_SEATS_Seat_control_change_requested (1) +#endif + +#ifndef DMFL_FrontPass_Req_DMFL_SMFL_REQ_CTR_SEATS_Not_requested +#define DMFL_FrontPass_Req_DMFL_SMFL_REQ_CTR_SEATS_Not_requested (0) +#endif + + +// Value tables for @DMFL_SeatLongitunalReq signal + +#ifndef DMFL_SeatLongitunalReq_DMFL_SMFL_REQ_CTR_SEATS_Reserved +#define DMFL_SeatLongitunalReq_DMFL_SMFL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef DMFL_SeatLongitunalReq_DMFL_SMFL_REQ_CTR_SEATS_Decrease +#define DMFL_SeatLongitunalReq_DMFL_SMFL_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef DMFL_SeatLongitunalReq_DMFL_SMFL_REQ_CTR_SEATS_Increase +#define DMFL_SeatLongitunalReq_DMFL_SMFL_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef DMFL_SeatLongitunalReq_DMFL_SMFL_REQ_CTR_SEATS_No_action +#define DMFL_SeatLongitunalReq_DMFL_SMFL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @DMFL_SeatBackRestInclinationReq signal + +#ifndef DMFL_SeatBackRestInclinationReq_DMFL_SMFL_REQ_CTR_SEATS_Reserved +#define DMFL_SeatBackRestInclinationReq_DMFL_SMFL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef DMFL_SeatBackRestInclinationReq_DMFL_SMFL_REQ_CTR_SEATS_Decrease +#define DMFL_SeatBackRestInclinationReq_DMFL_SMFL_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef DMFL_SeatBackRestInclinationReq_DMFL_SMFL_REQ_CTR_SEATS_Increase +#define DMFL_SeatBackRestInclinationReq_DMFL_SMFL_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef DMFL_SeatBackRestInclinationReq_DMFL_SMFL_REQ_CTR_SEATS_No_action +#define DMFL_SeatBackRestInclinationReq_DMFL_SMFL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @DMFL_SeatMassageRequest signal + +#ifndef DMFL_SeatMassageRequest_DMFL_SMFL_REQ_CTR_SEATS_Reserved +#define DMFL_SeatMassageRequest_DMFL_SMFL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef DMFL_SeatMassageRequest_DMFL_SMFL_REQ_CTR_SEATS_Massage_ON +#define DMFL_SeatMassageRequest_DMFL_SMFL_REQ_CTR_SEATS_Massage_ON (2) +#endif + +#ifndef DMFL_SeatMassageRequest_DMFL_SMFL_REQ_CTR_SEATS_Massage_OFF +#define DMFL_SeatMassageRequest_DMFL_SMFL_REQ_CTR_SEATS_Massage_OFF (1) +#endif + +#ifndef DMFL_SeatMassageRequest_DMFL_SMFL_REQ_CTR_SEATS_No_action +#define DMFL_SeatMassageRequest_DMFL_SMFL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @DMFL_SeatVentilationRequest signal + +#ifndef DMFL_SeatVentilationRequest_DMFL_SMFL_REQ_CTR_SEATS_Reserved +#define DMFL_SeatVentilationRequest_DMFL_SMFL_REQ_CTR_SEATS_Reserved (7) +#endif + +#ifndef DMFL_SeatVentilationRequest_DMFL_SMFL_REQ_CTR_SEATS_Reserved +#define DMFL_SeatVentilationRequest_DMFL_SMFL_REQ_CTR_SEATS_Reserved (6) +#endif + +#ifndef DMFL_SeatVentilationRequest_DMFL_SMFL_REQ_CTR_SEATS_Reserved +#define DMFL_SeatVentilationRequest_DMFL_SMFL_REQ_CTR_SEATS_Reserved (5) +#endif + +#ifndef DMFL_SeatVentilationRequest_DMFL_SMFL_REQ_CTR_SEATS_No_action +#define DMFL_SeatVentilationRequest_DMFL_SMFL_REQ_CTR_SEATS_No_action (4) +#endif + +#ifndef DMFL_SeatVentilationRequest_DMFL_SMFL_REQ_CTR_SEATS_High_power +#define DMFL_SeatVentilationRequest_DMFL_SMFL_REQ_CTR_SEATS_High_power (3) +#endif + +#ifndef DMFL_SeatVentilationRequest_DMFL_SMFL_REQ_CTR_SEATS_Middle_power +#define DMFL_SeatVentilationRequest_DMFL_SMFL_REQ_CTR_SEATS_Middle_power (2) +#endif + +#ifndef DMFL_SeatVentilationRequest_DMFL_SMFL_REQ_CTR_SEATS_Low_power +#define DMFL_SeatVentilationRequest_DMFL_SMFL_REQ_CTR_SEATS_Low_power (1) +#endif + +#ifndef DMFL_SeatVentilationRequest_DMFL_SMFL_REQ_CTR_SEATS_Off +#define DMFL_SeatVentilationRequest_DMFL_SMFL_REQ_CTR_SEATS_Off (0) +#endif + + +// Value tables for @DMFL_SeatMassageIntence signal + +#ifndef DMFL_SeatMassageIntence_DMFL_SMFL_REQ_CTR_SEATS_High_power +#define DMFL_SeatMassageIntence_DMFL_SMFL_REQ_CTR_SEATS_High_power (3) +#endif + +#ifndef DMFL_SeatMassageIntence_DMFL_SMFL_REQ_CTR_SEATS_Middle_power +#define DMFL_SeatMassageIntence_DMFL_SMFL_REQ_CTR_SEATS_Middle_power (2) +#endif + +#ifndef DMFL_SeatMassageIntence_DMFL_SMFL_REQ_CTR_SEATS_Low_power +#define DMFL_SeatMassageIntence_DMFL_SMFL_REQ_CTR_SEATS_Low_power (1) +#endif + +#ifndef DMFL_SeatMassageIntence_DMFL_SMFL_REQ_CTR_SEATS_No_action +#define DMFL_SeatMassageIntence_DMFL_SMFL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @DMFL_SeatHeatingRequest signal + +#ifndef DMFL_SeatHeatingRequest_DMFL_SMFL_REQ_CTR_SEATS_Reserved +#define DMFL_SeatHeatingRequest_DMFL_SMFL_REQ_CTR_SEATS_Reserved (7) +#endif + +#ifndef DMFL_SeatHeatingRequest_DMFL_SMFL_REQ_CTR_SEATS_Reserved +#define DMFL_SeatHeatingRequest_DMFL_SMFL_REQ_CTR_SEATS_Reserved (6) +#endif + +#ifndef DMFL_SeatHeatingRequest_DMFL_SMFL_REQ_CTR_SEATS_Reserved +#define DMFL_SeatHeatingRequest_DMFL_SMFL_REQ_CTR_SEATS_Reserved (5) +#endif + +#ifndef DMFL_SeatHeatingRequest_DMFL_SMFL_REQ_CTR_SEATS_No_action +#define DMFL_SeatHeatingRequest_DMFL_SMFL_REQ_CTR_SEATS_No_action (4) +#endif + +#ifndef DMFL_SeatHeatingRequest_DMFL_SMFL_REQ_CTR_SEATS_High_power +#define DMFL_SeatHeatingRequest_DMFL_SMFL_REQ_CTR_SEATS_High_power (3) +#endif + +#ifndef DMFL_SeatHeatingRequest_DMFL_SMFL_REQ_CTR_SEATS_Middle_power +#define DMFL_SeatHeatingRequest_DMFL_SMFL_REQ_CTR_SEATS_Middle_power (2) +#endif + +#ifndef DMFL_SeatHeatingRequest_DMFL_SMFL_REQ_CTR_SEATS_Low_power +#define DMFL_SeatHeatingRequest_DMFL_SMFL_REQ_CTR_SEATS_Low_power (1) +#endif + +#ifndef DMFL_SeatHeatingRequest_DMFL_SMFL_REQ_CTR_SEATS_Off +#define DMFL_SeatHeatingRequest_DMFL_SMFL_REQ_CTR_SEATS_Off (0) +#endif + + +// Value tables for @DMFL_SeatInclination_Req signal + +#ifndef DMFL_SeatInclination_Req_DMFL_SMFL_REQ_CTR_SEATS_Reserved +#define DMFL_SeatInclination_Req_DMFL_SMFL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef DMFL_SeatInclination_Req_DMFL_SMFL_REQ_CTR_SEATS_Decrease +#define DMFL_SeatInclination_Req_DMFL_SMFL_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef DMFL_SeatInclination_Req_DMFL_SMFL_REQ_CTR_SEATS_Increase +#define DMFL_SeatInclination_Req_DMFL_SMFL_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef DMFL_SeatInclination_Req_DMFL_SMFL_REQ_CTR_SEATS_No_action +#define DMFL_SeatInclination_Req_DMFL_SMFL_REQ_CTR_SEATS_No_action (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Request for saving the seat positions + // 0x0 = No request + // 0x1 = request to save mem 1 + // 0x2 = request to save mem 2 + // 0x3 = Reserved + // 6 : "request to upload mem 3" + // 5 : "request to upload mem 2" + // 4 : "request to upload mem 1" + // 3 : "request to save mem 3" + // 2 : "request to save mem 2" + // 1 : "request to save mem 1" + // 0 : "No request" + uint8_t DMFL_SeatMemReq : 3; // Bits= 3 + + // Signal for regulation Seat Height FL + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t DMFL_SeatHeightReq : 2; // Bits= 2 + + // Request for control of FL seat from driver's side + // 1 : "Seat control change requested" + // 0 : "Not requested" + uint8_t DMFL_FrontPass_Req : 1; // Bits= 1 + + // Signal for regulation FL seat longitunal + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t DMFL_SeatLongitunalReq : 2; // Bits= 2 + + // Signal for regulation FL seat backrest lnclination + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t DMFL_SeatBackRestInclinationReq : 2; // Bits= 2 + + // Signal for seat massage activation + // 3 : "Reserved" + // 2 : "Massage ON" + // 1 : "Massage OFF" + // 0 : "No action" + uint8_t DMFL_SeatMassageRequest : 2; // Bits= 2 + + // Signal for ventilation activation mode + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Reserved" + // 4 : "No action" + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "Off" + uint8_t DMFL_SeatVentilationRequest : 3; // Bits= 3 + + // Signal for seat massage intencity regulation + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "No action" + uint8_t DMFL_SeatMassageIntence : 2; // Bits= 2 + + // Signal for seat heating activation mode + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Reserved" + // 4 : "No action" + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "Off" + uint8_t DMFL_SeatHeatingRequest : 3; // Bits= 3 + + // Signal for regulation FL seat inclination + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t DMFL_SeatInclination_Req : 2; // Bits= 2 + +#else + + // Request for saving the seat positions + // 0x0 = No request + // 0x1 = request to save mem 1 + // 0x2 = request to save mem 2 + // 0x3 = Reserved + // 6 : "request to upload mem 3" + // 5 : "request to upload mem 2" + // 4 : "request to upload mem 1" + // 3 : "request to save mem 3" + // 2 : "request to save mem 2" + // 1 : "request to save mem 1" + // 0 : "No request" + uint8_t DMFL_SeatMemReq; // Bits= 3 + + // Signal for regulation Seat Height FL + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t DMFL_SeatHeightReq; // Bits= 2 + + // Request for control of FL seat from driver's side + // 1 : "Seat control change requested" + // 0 : "Not requested" + uint8_t DMFL_FrontPass_Req; // Bits= 1 + + // Signal for regulation FL seat longitunal + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t DMFL_SeatLongitunalReq; // Bits= 2 + + // Signal for regulation FL seat backrest lnclination + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t DMFL_SeatBackRestInclinationReq; // Bits= 2 + + // Signal for seat massage activation + // 3 : "Reserved" + // 2 : "Massage ON" + // 1 : "Massage OFF" + // 0 : "No action" + uint8_t DMFL_SeatMassageRequest; // Bits= 2 + + // Signal for ventilation activation mode + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Reserved" + // 4 : "No action" + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "Off" + uint8_t DMFL_SeatVentilationRequest; // Bits= 3 + + // Signal for seat massage intencity regulation + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "No action" + uint8_t DMFL_SeatMassageIntence; // Bits= 2 + + // Signal for seat heating activation mode + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Reserved" + // 4 : "No action" + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "Off" + uint8_t DMFL_SeatHeatingRequest; // Bits= 3 + + // Signal for regulation FL seat inclination + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t DMFL_SeatInclination_Req; // Bits= 2 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} DMFL_SMFL_REQ_CTR_SEATS_t; + +// def @DMFR_SMFR_REQ_CTR_SEATS CAN Message (872 0x368) +#define DMFR_SMFR_REQ_CTR_SEATS_IDE (0U) +#define DMFR_SMFR_REQ_CTR_SEATS_DLC (3U) +#define DMFR_SMFR_REQ_CTR_SEATS_CANID (0x368U) +#define DMFR_SMFR_REQ_CTR_SEATS_CYC (100U) + +// Value tables for @DMFR_SeatMemReq signal + +#ifndef DMFR_SeatMemReq_DMFR_SMFR_REQ_CTR_SEATS_request_to_upload_mem_3 +#define DMFR_SeatMemReq_DMFR_SMFR_REQ_CTR_SEATS_request_to_upload_mem_3 (6) +#endif + +#ifndef DMFR_SeatMemReq_DMFR_SMFR_REQ_CTR_SEATS_request_to_upload_mem_2 +#define DMFR_SeatMemReq_DMFR_SMFR_REQ_CTR_SEATS_request_to_upload_mem_2 (5) +#endif + +#ifndef DMFR_SeatMemReq_DMFR_SMFR_REQ_CTR_SEATS_request_to_upload_mem_1 +#define DMFR_SeatMemReq_DMFR_SMFR_REQ_CTR_SEATS_request_to_upload_mem_1 (4) +#endif + +#ifndef DMFR_SeatMemReq_DMFR_SMFR_REQ_CTR_SEATS_request_to_save_mem_3 +#define DMFR_SeatMemReq_DMFR_SMFR_REQ_CTR_SEATS_request_to_save_mem_3 (3) +#endif + +#ifndef DMFR_SeatMemReq_DMFR_SMFR_REQ_CTR_SEATS_request_to_save_mem_2 +#define DMFR_SeatMemReq_DMFR_SMFR_REQ_CTR_SEATS_request_to_save_mem_2 (2) +#endif + +#ifndef DMFR_SeatMemReq_DMFR_SMFR_REQ_CTR_SEATS_request_to_save_mem_1 +#define DMFR_SeatMemReq_DMFR_SMFR_REQ_CTR_SEATS_request_to_save_mem_1 (1) +#endif + +#ifndef DMFR_SeatMemReq_DMFR_SMFR_REQ_CTR_SEATS_No_request +#define DMFR_SeatMemReq_DMFR_SMFR_REQ_CTR_SEATS_No_request (0) +#endif + + +// Value tables for @DMFR_SeatHeightReq signal + +#ifndef DMFR_SeatHeightReq_DMFR_SMFR_REQ_CTR_SEATS_Resertved +#define DMFR_SeatHeightReq_DMFR_SMFR_REQ_CTR_SEATS_Resertved (3) +#endif + +#ifndef DMFR_SeatHeightReq_DMFR_SMFR_REQ_CTR_SEATS_Decrease +#define DMFR_SeatHeightReq_DMFR_SMFR_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef DMFR_SeatHeightReq_DMFR_SMFR_REQ_CTR_SEATS_Increase +#define DMFR_SeatHeightReq_DMFR_SMFR_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef DMFR_SeatHeightReq_DMFR_SMFR_REQ_CTR_SEATS_No_action +#define DMFR_SeatHeightReq_DMFR_SMFR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @DMFR_SeatLongitunalReq signal + +#ifndef DMFR_SeatLongitunalReq_DMFR_SMFR_REQ_CTR_SEATS_Reserved +#define DMFR_SeatLongitunalReq_DMFR_SMFR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef DMFR_SeatLongitunalReq_DMFR_SMFR_REQ_CTR_SEATS_Decrease +#define DMFR_SeatLongitunalReq_DMFR_SMFR_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef DMFR_SeatLongitunalReq_DMFR_SMFR_REQ_CTR_SEATS_Increase +#define DMFR_SeatLongitunalReq_DMFR_SMFR_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef DMFR_SeatLongitunalReq_DMFR_SMFR_REQ_CTR_SEATS_No_action +#define DMFR_SeatLongitunalReq_DMFR_SMFR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @DMFR_SeatBackRestInclinationReq signal + +#ifndef DMFR_SeatBackRestInclinationReq_DMFR_SMFR_REQ_CTR_SEATS_Reserved +#define DMFR_SeatBackRestInclinationReq_DMFR_SMFR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef DMFR_SeatBackRestInclinationReq_DMFR_SMFR_REQ_CTR_SEATS_Decrease +#define DMFR_SeatBackRestInclinationReq_DMFR_SMFR_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef DMFR_SeatBackRestInclinationReq_DMFR_SMFR_REQ_CTR_SEATS_Increase +#define DMFR_SeatBackRestInclinationReq_DMFR_SMFR_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef DMFR_SeatBackRestInclinationReq_DMFR_SMFR_REQ_CTR_SEATS_No_action +#define DMFR_SeatBackRestInclinationReq_DMFR_SMFR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @DMFR_SeatMassageRequest signal + +#ifndef DMFR_SeatMassageRequest_DMFR_SMFR_REQ_CTR_SEATS_Reserved +#define DMFR_SeatMassageRequest_DMFR_SMFR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef DMFR_SeatMassageRequest_DMFR_SMFR_REQ_CTR_SEATS_Massage_ON +#define DMFR_SeatMassageRequest_DMFR_SMFR_REQ_CTR_SEATS_Massage_ON (2) +#endif + +#ifndef DMFR_SeatMassageRequest_DMFR_SMFR_REQ_CTR_SEATS_Massage_OFF +#define DMFR_SeatMassageRequest_DMFR_SMFR_REQ_CTR_SEATS_Massage_OFF (1) +#endif + +#ifndef DMFR_SeatMassageRequest_DMFR_SMFR_REQ_CTR_SEATS_No_action +#define DMFR_SeatMassageRequest_DMFR_SMFR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @DMFR_SeatVentilationRequest signal + +#ifndef DMFR_SeatVentilationRequest_DMFR_SMFR_REQ_CTR_SEATS_Reserved +#define DMFR_SeatVentilationRequest_DMFR_SMFR_REQ_CTR_SEATS_Reserved (7) +#endif + +#ifndef DMFR_SeatVentilationRequest_DMFR_SMFR_REQ_CTR_SEATS_Reserved +#define DMFR_SeatVentilationRequest_DMFR_SMFR_REQ_CTR_SEATS_Reserved (6) +#endif + +#ifndef DMFR_SeatVentilationRequest_DMFR_SMFR_REQ_CTR_SEATS_Reserved +#define DMFR_SeatVentilationRequest_DMFR_SMFR_REQ_CTR_SEATS_Reserved (5) +#endif + +#ifndef DMFR_SeatVentilationRequest_DMFR_SMFR_REQ_CTR_SEATS_No_action +#define DMFR_SeatVentilationRequest_DMFR_SMFR_REQ_CTR_SEATS_No_action (4) +#endif + +#ifndef DMFR_SeatVentilationRequest_DMFR_SMFR_REQ_CTR_SEATS_High_power +#define DMFR_SeatVentilationRequest_DMFR_SMFR_REQ_CTR_SEATS_High_power (3) +#endif + +#ifndef DMFR_SeatVentilationRequest_DMFR_SMFR_REQ_CTR_SEATS_Middle_power +#define DMFR_SeatVentilationRequest_DMFR_SMFR_REQ_CTR_SEATS_Middle_power (2) +#endif + +#ifndef DMFR_SeatVentilationRequest_DMFR_SMFR_REQ_CTR_SEATS_Low_power +#define DMFR_SeatVentilationRequest_DMFR_SMFR_REQ_CTR_SEATS_Low_power (1) +#endif + +#ifndef DMFR_SeatVentilationRequest_DMFR_SMFR_REQ_CTR_SEATS_Off +#define DMFR_SeatVentilationRequest_DMFR_SMFR_REQ_CTR_SEATS_Off (0) +#endif + + +// Value tables for @DMFR_SeatMassageIntence signal + +#ifndef DMFR_SeatMassageIntence_DMFR_SMFR_REQ_CTR_SEATS_High_power +#define DMFR_SeatMassageIntence_DMFR_SMFR_REQ_CTR_SEATS_High_power (3) +#endif + +#ifndef DMFR_SeatMassageIntence_DMFR_SMFR_REQ_CTR_SEATS_Middle_power +#define DMFR_SeatMassageIntence_DMFR_SMFR_REQ_CTR_SEATS_Middle_power (2) +#endif + +#ifndef DMFR_SeatMassageIntence_DMFR_SMFR_REQ_CTR_SEATS_Low_power +#define DMFR_SeatMassageIntence_DMFR_SMFR_REQ_CTR_SEATS_Low_power (1) +#endif + +#ifndef DMFR_SeatMassageIntence_DMFR_SMFR_REQ_CTR_SEATS_No_action +#define DMFR_SeatMassageIntence_DMFR_SMFR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @DMFR_SeatHeatingRequest signal + +#ifndef DMFR_SeatHeatingRequest_DMFR_SMFR_REQ_CTR_SEATS_Reserved +#define DMFR_SeatHeatingRequest_DMFR_SMFR_REQ_CTR_SEATS_Reserved (7) +#endif + +#ifndef DMFR_SeatHeatingRequest_DMFR_SMFR_REQ_CTR_SEATS_Reserved +#define DMFR_SeatHeatingRequest_DMFR_SMFR_REQ_CTR_SEATS_Reserved (6) +#endif + +#ifndef DMFR_SeatHeatingRequest_DMFR_SMFR_REQ_CTR_SEATS_Reserved +#define DMFR_SeatHeatingRequest_DMFR_SMFR_REQ_CTR_SEATS_Reserved (5) +#endif + +#ifndef DMFR_SeatHeatingRequest_DMFR_SMFR_REQ_CTR_SEATS_No_action +#define DMFR_SeatHeatingRequest_DMFR_SMFR_REQ_CTR_SEATS_No_action (4) +#endif + +#ifndef DMFR_SeatHeatingRequest_DMFR_SMFR_REQ_CTR_SEATS_High_power +#define DMFR_SeatHeatingRequest_DMFR_SMFR_REQ_CTR_SEATS_High_power (3) +#endif + +#ifndef DMFR_SeatHeatingRequest_DMFR_SMFR_REQ_CTR_SEATS_Middle_power +#define DMFR_SeatHeatingRequest_DMFR_SMFR_REQ_CTR_SEATS_Middle_power (2) +#endif + +#ifndef DMFR_SeatHeatingRequest_DMFR_SMFR_REQ_CTR_SEATS_Low_power +#define DMFR_SeatHeatingRequest_DMFR_SMFR_REQ_CTR_SEATS_Low_power (1) +#endif + +#ifndef DMFR_SeatHeatingRequest_DMFR_SMFR_REQ_CTR_SEATS_Off +#define DMFR_SeatHeatingRequest_DMFR_SMFR_REQ_CTR_SEATS_Off (0) +#endif + + +// Value tables for @DMFR_SeatInclination_Req signal + +#ifndef DMFR_SeatInclination_Req_DMFR_SMFR_REQ_CTR_SEATS_Reserved +#define DMFR_SeatInclination_Req_DMFR_SMFR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef DMFR_SeatInclination_Req_DMFR_SMFR_REQ_CTR_SEATS_Decrease +#define DMFR_SeatInclination_Req_DMFR_SMFR_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef DMFR_SeatInclination_Req_DMFR_SMFR_REQ_CTR_SEATS_Increase +#define DMFR_SeatInclination_Req_DMFR_SMFR_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef DMFR_SeatInclination_Req_DMFR_SMFR_REQ_CTR_SEATS_No_action +#define DMFR_SeatInclination_Req_DMFR_SMFR_REQ_CTR_SEATS_No_action (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Signal for configuration selection memory + // 6 : "request to upload mem 3" + // 5 : "request to upload mem 2" + // 4 : "request to upload mem 1" + // 3 : "request to save mem 3" + // 2 : "request to save mem 2" + // 1 : "request to save mem 1" + // 0 : "No request" + uint8_t DMFR_SeatMemReq : 3; // Bits= 3 + + // Signal for regulation Seat Height FR + // 3 : "Resertved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t DMFR_SeatHeightReq : 2; // Bits= 2 + + // Signal for regulation FR seat longitunal + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t DMFR_SeatLongitunalReq : 2; // Bits= 2 + + // Signal for regulation FR seat backrest lnclination + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t DMFR_SeatBackRestInclinationReq : 2; // Bits= 2 + + // Signal for seat massage activation + // 3 : "Reserved" + // 2 : "Massage ON" + // 1 : "Massage OFF" + // 0 : "No action" + uint8_t DMFR_SeatMassageRequest : 2; // Bits= 2 + + // Signal for ventilation activation mode + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Reserved" + // 4 : "No action" + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "Off" + uint8_t DMFR_SeatVentilationRequest : 3; // Bits= 3 + + // Signal for seat massage intencity regulation + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "No action" + uint8_t DMFR_SeatMassageIntence : 2; // Bits= 2 + + // Signal for seat heating activation mode + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Reserved" + // 4 : "No action" + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "Off" + uint8_t DMFR_SeatHeatingRequest : 3; // Bits= 3 + + // Signal for regulation FR seat inclination + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t DMFR_SeatInclination_Req : 2; // Bits= 2 + +#else + + // Signal for configuration selection memory + // 6 : "request to upload mem 3" + // 5 : "request to upload mem 2" + // 4 : "request to upload mem 1" + // 3 : "request to save mem 3" + // 2 : "request to save mem 2" + // 1 : "request to save mem 1" + // 0 : "No request" + uint8_t DMFR_SeatMemReq; // Bits= 3 + + // Signal for regulation Seat Height FR + // 3 : "Resertved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t DMFR_SeatHeightReq; // Bits= 2 + + // Signal for regulation FR seat longitunal + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t DMFR_SeatLongitunalReq; // Bits= 2 + + // Signal for regulation FR seat backrest lnclination + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t DMFR_SeatBackRestInclinationReq; // Bits= 2 + + // Signal for seat massage activation + // 3 : "Reserved" + // 2 : "Massage ON" + // 1 : "Massage OFF" + // 0 : "No action" + uint8_t DMFR_SeatMassageRequest; // Bits= 2 + + // Signal for ventilation activation mode + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Reserved" + // 4 : "No action" + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "Off" + uint8_t DMFR_SeatVentilationRequest; // Bits= 3 + + // Signal for seat massage intencity regulation + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "No action" + uint8_t DMFR_SeatMassageIntence; // Bits= 2 + + // Signal for seat heating activation mode + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Reserved" + // 4 : "No action" + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "Off" + uint8_t DMFR_SeatHeatingRequest; // Bits= 3 + + // Signal for regulation FR seat inclination + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t DMFR_SeatInclination_Req; // Bits= 2 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} DMFR_SMFR_REQ_CTR_SEATS_t; + +// def @DMRL_SMRL_REQ_CTR_SEATS CAN Message (873 0x369) +#define DMRL_SMRL_REQ_CTR_SEATS_IDE (0U) +#define DMRL_SMRL_REQ_CTR_SEATS_DLC (4U) +#define DMRL_SMRL_REQ_CTR_SEATS_CANID (0x369U) +#define DMRL_SMRL_REQ_CTR_SEATS_CYC (100U) + +// Value tables for @DMRL_SeatMemReq signal + +#ifndef DMRL_SeatMemReq_DMRL_SMRL_REQ_CTR_SEATS_Request_to_upload_MEM_3 +#define DMRL_SeatMemReq_DMRL_SMRL_REQ_CTR_SEATS_Request_to_upload_MEM_3 (6) +#endif + +#ifndef DMRL_SeatMemReq_DMRL_SMRL_REQ_CTR_SEATS_Request_to_upload_MEM_2 +#define DMRL_SeatMemReq_DMRL_SMRL_REQ_CTR_SEATS_Request_to_upload_MEM_2 (5) +#endif + +#ifndef DMRL_SeatMemReq_DMRL_SMRL_REQ_CTR_SEATS_Request_to_upload_MEM_1 +#define DMRL_SeatMemReq_DMRL_SMRL_REQ_CTR_SEATS_Request_to_upload_MEM_1 (4) +#endif + +#ifndef DMRL_SeatMemReq_DMRL_SMRL_REQ_CTR_SEATS_Request_to_save_MEM_3 +#define DMRL_SeatMemReq_DMRL_SMRL_REQ_CTR_SEATS_Request_to_save_MEM_3 (3) +#endif + +#ifndef DMRL_SeatMemReq_DMRL_SMRL_REQ_CTR_SEATS_Request_to_save_MEM_2 +#define DMRL_SeatMemReq_DMRL_SMRL_REQ_CTR_SEATS_Request_to_save_MEM_2 (2) +#endif + +#ifndef DMRL_SeatMemReq_DMRL_SMRL_REQ_CTR_SEATS_Request_to_save_MEM_1 +#define DMRL_SeatMemReq_DMRL_SMRL_REQ_CTR_SEATS_Request_to_save_MEM_1 (1) +#endif + +#ifndef DMRL_SeatMemReq_DMRL_SMRL_REQ_CTR_SEATS_Not_requested +#define DMRL_SeatMemReq_DMRL_SMRL_REQ_CTR_SEATS_Not_requested (0) +#endif + + +// Value tables for @DMRL_SeatHeightReq signal + +#ifndef DMRL_SeatHeightReq_DMRL_SMRL_REQ_CTR_SEATS_Reserved +#define DMRL_SeatHeightReq_DMRL_SMRL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef DMRL_SeatHeightReq_DMRL_SMRL_REQ_CTR_SEATS_Decrease +#define DMRL_SeatHeightReq_DMRL_SMRL_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef DMRL_SeatHeightReq_DMRL_SMRL_REQ_CTR_SEATS_Increase +#define DMRL_SeatHeightReq_DMRL_SMRL_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef DMRL_SeatHeightReq_DMRL_SMRL_REQ_CTR_SEATS_No_action +#define DMRL_SeatHeightReq_DMRL_SMRL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @DMRL_SeatLongitunalReq signal + +#ifndef DMRL_SeatLongitunalReq_DMRL_SMRL_REQ_CTR_SEATS_Reserved +#define DMRL_SeatLongitunalReq_DMRL_SMRL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef DMRL_SeatLongitunalReq_DMRL_SMRL_REQ_CTR_SEATS_Decrease +#define DMRL_SeatLongitunalReq_DMRL_SMRL_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef DMRL_SeatLongitunalReq_DMRL_SMRL_REQ_CTR_SEATS_Increase +#define DMRL_SeatLongitunalReq_DMRL_SMRL_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef DMRL_SeatLongitunalReq_DMRL_SMRL_REQ_CTR_SEATS_No_action +#define DMRL_SeatLongitunalReq_DMRL_SMRL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @DMRL_SeatBackRestInclinationReq signal + +#ifndef DMRL_SeatBackRestInclinationReq_DMRL_SMRL_REQ_CTR_SEATS_Reserved +#define DMRL_SeatBackRestInclinationReq_DMRL_SMRL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef DMRL_SeatBackRestInclinationReq_DMRL_SMRL_REQ_CTR_SEATS_Decrease +#define DMRL_SeatBackRestInclinationReq_DMRL_SMRL_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef DMRL_SeatBackRestInclinationReq_DMRL_SMRL_REQ_CTR_SEATS_Increase +#define DMRL_SeatBackRestInclinationReq_DMRL_SMRL_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef DMRL_SeatBackRestInclinationReq_DMRL_SMRL_REQ_CTR_SEATS_No_action +#define DMRL_SeatBackRestInclinationReq_DMRL_SMRL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @DMRL_SeatMassageRequest signal + +#ifndef DMRL_SeatMassageRequest_DMRL_SMRL_REQ_CTR_SEATS_Reserved +#define DMRL_SeatMassageRequest_DMRL_SMRL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef DMRL_SeatMassageRequest_DMRL_SMRL_REQ_CTR_SEATS_Massage_ON +#define DMRL_SeatMassageRequest_DMRL_SMRL_REQ_CTR_SEATS_Massage_ON (2) +#endif + +#ifndef DMRL_SeatMassageRequest_DMRL_SMRL_REQ_CTR_SEATS_Massage_OFF +#define DMRL_SeatMassageRequest_DMRL_SMRL_REQ_CTR_SEATS_Massage_OFF (1) +#endif + +#ifndef DMRL_SeatMassageRequest_DMRL_SMRL_REQ_CTR_SEATS_No_action +#define DMRL_SeatMassageRequest_DMRL_SMRL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @DMRL_SeatVentilationRequest signal + +#ifndef DMRL_SeatVentilationRequest_DMRL_SMRL_REQ_CTR_SEATS_Reserved +#define DMRL_SeatVentilationRequest_DMRL_SMRL_REQ_CTR_SEATS_Reserved (7) +#endif + +#ifndef DMRL_SeatVentilationRequest_DMRL_SMRL_REQ_CTR_SEATS_Reserved +#define DMRL_SeatVentilationRequest_DMRL_SMRL_REQ_CTR_SEATS_Reserved (6) +#endif + +#ifndef DMRL_SeatVentilationRequest_DMRL_SMRL_REQ_CTR_SEATS_Reserved +#define DMRL_SeatVentilationRequest_DMRL_SMRL_REQ_CTR_SEATS_Reserved (5) +#endif + +#ifndef DMRL_SeatVentilationRequest_DMRL_SMRL_REQ_CTR_SEATS_No_action +#define DMRL_SeatVentilationRequest_DMRL_SMRL_REQ_CTR_SEATS_No_action (4) +#endif + +#ifndef DMRL_SeatVentilationRequest_DMRL_SMRL_REQ_CTR_SEATS_High_power +#define DMRL_SeatVentilationRequest_DMRL_SMRL_REQ_CTR_SEATS_High_power (3) +#endif + +#ifndef DMRL_SeatVentilationRequest_DMRL_SMRL_REQ_CTR_SEATS_Middle_power +#define DMRL_SeatVentilationRequest_DMRL_SMRL_REQ_CTR_SEATS_Middle_power (2) +#endif + +#ifndef DMRL_SeatVentilationRequest_DMRL_SMRL_REQ_CTR_SEATS_Low_power +#define DMRL_SeatVentilationRequest_DMRL_SMRL_REQ_CTR_SEATS_Low_power (1) +#endif + +#ifndef DMRL_SeatVentilationRequest_DMRL_SMRL_REQ_CTR_SEATS_Off +#define DMRL_SeatVentilationRequest_DMRL_SMRL_REQ_CTR_SEATS_Off (0) +#endif + + +// Value tables for @DMRL_SeatMassageIntence signal + +#ifndef DMRL_SeatMassageIntence_DMRL_SMRL_REQ_CTR_SEATS_High_power +#define DMRL_SeatMassageIntence_DMRL_SMRL_REQ_CTR_SEATS_High_power (3) +#endif + +#ifndef DMRL_SeatMassageIntence_DMRL_SMRL_REQ_CTR_SEATS_Middle_power +#define DMRL_SeatMassageIntence_DMRL_SMRL_REQ_CTR_SEATS_Middle_power (2) +#endif + +#ifndef DMRL_SeatMassageIntence_DMRL_SMRL_REQ_CTR_SEATS_Low_power +#define DMRL_SeatMassageIntence_DMRL_SMRL_REQ_CTR_SEATS_Low_power (1) +#endif + +#ifndef DMRL_SeatMassageIntence_DMRL_SMRL_REQ_CTR_SEATS_No_action +#define DMRL_SeatMassageIntence_DMRL_SMRL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @DMRL_SeatHeatingRequest signal + +#ifndef DMRL_SeatHeatingRequest_DMRL_SMRL_REQ_CTR_SEATS_Reserved +#define DMRL_SeatHeatingRequest_DMRL_SMRL_REQ_CTR_SEATS_Reserved (7) +#endif + +#ifndef DMRL_SeatHeatingRequest_DMRL_SMRL_REQ_CTR_SEATS_Reserved +#define DMRL_SeatHeatingRequest_DMRL_SMRL_REQ_CTR_SEATS_Reserved (6) +#endif + +#ifndef DMRL_SeatHeatingRequest_DMRL_SMRL_REQ_CTR_SEATS_Reserved +#define DMRL_SeatHeatingRequest_DMRL_SMRL_REQ_CTR_SEATS_Reserved (5) +#endif + +#ifndef DMRL_SeatHeatingRequest_DMRL_SMRL_REQ_CTR_SEATS_No_action +#define DMRL_SeatHeatingRequest_DMRL_SMRL_REQ_CTR_SEATS_No_action (4) +#endif + +#ifndef DMRL_SeatHeatingRequest_DMRL_SMRL_REQ_CTR_SEATS_High_power +#define DMRL_SeatHeatingRequest_DMRL_SMRL_REQ_CTR_SEATS_High_power (3) +#endif + +#ifndef DMRL_SeatHeatingRequest_DMRL_SMRL_REQ_CTR_SEATS_Middle_power +#define DMRL_SeatHeatingRequest_DMRL_SMRL_REQ_CTR_SEATS_Middle_power (2) +#endif + +#ifndef DMRL_SeatHeatingRequest_DMRL_SMRL_REQ_CTR_SEATS_Low_power +#define DMRL_SeatHeatingRequest_DMRL_SMRL_REQ_CTR_SEATS_Low_power (1) +#endif + +#ifndef DMRL_SeatHeatingRequest_DMRL_SMRL_REQ_CTR_SEATS_Off +#define DMRL_SeatHeatingRequest_DMRL_SMRL_REQ_CTR_SEATS_Off (0) +#endif + + +// Value tables for @DMRL_SeatInclination_Req signal + +#ifndef DMRL_SeatInclination_Req_DMRL_SMRL_REQ_CTR_SEATS_Reserved +#define DMRL_SeatInclination_Req_DMRL_SMRL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef DMRL_SeatInclination_Req_DMRL_SMRL_REQ_CTR_SEATS_Decrease +#define DMRL_SeatInclination_Req_DMRL_SMRL_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef DMRL_SeatInclination_Req_DMRL_SMRL_REQ_CTR_SEATS_Increase +#define DMRL_SeatInclination_Req_DMRL_SMRL_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef DMRL_SeatInclination_Req_DMRL_SMRL_REQ_CTR_SEATS_No_action +#define DMRL_SeatInclination_Req_DMRL_SMRL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @DMRL_SeatFootRestHeightReq signal + +#ifndef DMRL_SeatFootRestHeightReq_DMRL_SMRL_REQ_CTR_SEATS_Reserved +#define DMRL_SeatFootRestHeightReq_DMRL_SMRL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef DMRL_SeatFootRestHeightReq_DMRL_SMRL_REQ_CTR_SEATS_Decrease +#define DMRL_SeatFootRestHeightReq_DMRL_SMRL_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef DMRL_SeatFootRestHeightReq_DMRL_SMRL_REQ_CTR_SEATS_Increase +#define DMRL_SeatFootRestHeightReq_DMRL_SMRL_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef DMRL_SeatFootRestHeightReq_DMRL_SMRL_REQ_CTR_SEATS_No_action +#define DMRL_SeatFootRestHeightReq_DMRL_SMRL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @DMRL_MoreComfort_Req signal + +#ifndef DMRL_MoreComfort_Req_DMRL_SMRL_REQ_CTR_SEATS_Unfold_requested +#define DMRL_MoreComfort_Req_DMRL_SMRL_REQ_CTR_SEATS_Unfold_requested (2) +#endif + +#ifndef DMRL_MoreComfort_Req_DMRL_SMRL_REQ_CTR_SEATS_Fold_requested +#define DMRL_MoreComfort_Req_DMRL_SMRL_REQ_CTR_SEATS_Fold_requested (1) +#endif + +#ifndef DMRL_MoreComfort_Req_DMRL_SMRL_REQ_CTR_SEATS_Not_requested +#define DMRL_MoreComfort_Req_DMRL_SMRL_REQ_CTR_SEATS_Not_requested (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Signal for configuration selection memory + // 6 : "Request to upload MEM 3" + // 5 : "Request to upload MEM 2" + // 4 : "Request to upload MEM 1" + // 3 : "Request to save MEM 3" + // 2 : "Request to save MEM 2" + // 1 : "Request to save MEM 1" + // 0 : "Not requested" + uint8_t DMRL_SeatMemReq : 3; // Bits= 3 + + // Signal for regulation Seat Height RL + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t DMRL_SeatHeightReq : 2; // Bits= 2 + + // Signal for regulation RL seat longitunal + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t DMRL_SeatLongitunalReq : 2; // Bits= 2 + + // Signal for regulation RL seat backrest lnclination + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t DMRL_SeatBackRestInclinationReq : 2; // Bits= 2 + + // Signal for seat massage activation + // 3 : "Reserved" + // 2 : "Massage ON" + // 1 : "Massage OFF" + // 0 : "No action" + uint8_t DMRL_SeatMassageRequest : 2; // Bits= 2 + + // Signal for ventilation activation mode + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Reserved" + // 4 : "No action" + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "Off" + uint8_t DMRL_SeatVentilationRequest : 3; // Bits= 3 + + // Signal for seat massage intencity regulation + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "No action" + uint8_t DMRL_SeatMassageIntence : 2; // Bits= 2 + + // Signal for seat heating activation mode + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Reserved" + // 4 : "No action" + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "Off" + uint8_t DMRL_SeatHeatingRequest : 3; // Bits= 3 + + // Signal for regulation RL seat inclination + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t DMRL_SeatInclination_Req : 2; // Bits= 2 + + // Signal for regulation RL seat foot rest height + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t DMRL_SeatFootRestHeightReq : 2; // Bits= 2 + + // Request for comfort mode RL seat + // 2 : "Unfold requested" + // 1 : "Fold requested" + // 0 : "Not requested" + uint8_t DMRL_MoreComfort_Req : 2; // Bits= 2 + +#else + + // Signal for configuration selection memory + // 6 : "Request to upload MEM 3" + // 5 : "Request to upload MEM 2" + // 4 : "Request to upload MEM 1" + // 3 : "Request to save MEM 3" + // 2 : "Request to save MEM 2" + // 1 : "Request to save MEM 1" + // 0 : "Not requested" + uint8_t DMRL_SeatMemReq; // Bits= 3 + + // Signal for regulation Seat Height RL + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t DMRL_SeatHeightReq; // Bits= 2 + + // Signal for regulation RL seat longitunal + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t DMRL_SeatLongitunalReq; // Bits= 2 + + // Signal for regulation RL seat backrest lnclination + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t DMRL_SeatBackRestInclinationReq; // Bits= 2 + + // Signal for seat massage activation + // 3 : "Reserved" + // 2 : "Massage ON" + // 1 : "Massage OFF" + // 0 : "No action" + uint8_t DMRL_SeatMassageRequest; // Bits= 2 + + // Signal for ventilation activation mode + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Reserved" + // 4 : "No action" + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "Off" + uint8_t DMRL_SeatVentilationRequest; // Bits= 3 + + // Signal for seat massage intencity regulation + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "No action" + uint8_t DMRL_SeatMassageIntence; // Bits= 2 + + // Signal for seat heating activation mode + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Reserved" + // 4 : "No action" + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "Off" + uint8_t DMRL_SeatHeatingRequest; // Bits= 3 + + // Signal for regulation RL seat inclination + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t DMRL_SeatInclination_Req; // Bits= 2 + + // Signal for regulation RL seat foot rest height + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t DMRL_SeatFootRestHeightReq; // Bits= 2 + + // Request for comfort mode RL seat + // 2 : "Unfold requested" + // 1 : "Fold requested" + // 0 : "Not requested" + uint8_t DMRL_MoreComfort_Req; // Bits= 2 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} DMRL_SMRL_REQ_CTR_SEATS_t; + +// def @DMRR_SMRR_REQ_CTR_SEATS CAN Message (874 0x36a) +#define DMRR_SMRR_REQ_CTR_SEATS_IDE (0U) +#define DMRR_SMRR_REQ_CTR_SEATS_DLC (4U) +#define DMRR_SMRR_REQ_CTR_SEATS_CANID (0x36aU) +#define DMRR_SMRR_REQ_CTR_SEATS_CYC (100U) + +// Value tables for @DMRR_SeatMemReq signal + +#ifndef DMRR_SeatMemReq_DMRR_SMRR_REQ_CTR_SEATS_request_to_upload_mem_3 +#define DMRR_SeatMemReq_DMRR_SMRR_REQ_CTR_SEATS_request_to_upload_mem_3 (6) +#endif + +#ifndef DMRR_SeatMemReq_DMRR_SMRR_REQ_CTR_SEATS_request_to_upload_mem_2 +#define DMRR_SeatMemReq_DMRR_SMRR_REQ_CTR_SEATS_request_to_upload_mem_2 (5) +#endif + +#ifndef DMRR_SeatMemReq_DMRR_SMRR_REQ_CTR_SEATS_request_to_upload_mem_1 +#define DMRR_SeatMemReq_DMRR_SMRR_REQ_CTR_SEATS_request_to_upload_mem_1 (4) +#endif + +#ifndef DMRR_SeatMemReq_DMRR_SMRR_REQ_CTR_SEATS_request_to_save_mem_3 +#define DMRR_SeatMemReq_DMRR_SMRR_REQ_CTR_SEATS_request_to_save_mem_3 (3) +#endif + +#ifndef DMRR_SeatMemReq_DMRR_SMRR_REQ_CTR_SEATS_request_to_save_mem_2 +#define DMRR_SeatMemReq_DMRR_SMRR_REQ_CTR_SEATS_request_to_save_mem_2 (2) +#endif + +#ifndef DMRR_SeatMemReq_DMRR_SMRR_REQ_CTR_SEATS_request_to_save_mem_1 +#define DMRR_SeatMemReq_DMRR_SMRR_REQ_CTR_SEATS_request_to_save_mem_1 (1) +#endif + +#ifndef DMRR_SeatMemReq_DMRR_SMRR_REQ_CTR_SEATS_No_request +#define DMRR_SeatMemReq_DMRR_SMRR_REQ_CTR_SEATS_No_request (0) +#endif + + +// Value tables for @DMRR_SeatHeightReq signal + +#ifndef DMRR_SeatHeightReq_DMRR_SMRR_REQ_CTR_SEATS_Reserved +#define DMRR_SeatHeightReq_DMRR_SMRR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef DMRR_SeatHeightReq_DMRR_SMRR_REQ_CTR_SEATS_Decrease +#define DMRR_SeatHeightReq_DMRR_SMRR_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef DMRR_SeatHeightReq_DMRR_SMRR_REQ_CTR_SEATS_Increase +#define DMRR_SeatHeightReq_DMRR_SMRR_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef DMRR_SeatHeightReq_DMRR_SMRR_REQ_CTR_SEATS_No_action +#define DMRR_SeatHeightReq_DMRR_SMRR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @DMRR_FrontPass_Req signal + +#ifndef DMRR_FrontPass_Req_DMRR_SMRR_REQ_CTR_SEATS_Seat_control_change_requested +#define DMRR_FrontPass_Req_DMRR_SMRR_REQ_CTR_SEATS_Seat_control_change_requested (1) +#endif + +#ifndef DMRR_FrontPass_Req_DMRR_SMRR_REQ_CTR_SEATS_Not_requested +#define DMRR_FrontPass_Req_DMRR_SMRR_REQ_CTR_SEATS_Not_requested (0) +#endif + + +// Value tables for @DMRR_SeatLongitunalReq signal + +#ifndef DMRR_SeatLongitunalReq_DMRR_SMRR_REQ_CTR_SEATS_Reserved +#define DMRR_SeatLongitunalReq_DMRR_SMRR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef DMRR_SeatLongitunalReq_DMRR_SMRR_REQ_CTR_SEATS_Decrease +#define DMRR_SeatLongitunalReq_DMRR_SMRR_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef DMRR_SeatLongitunalReq_DMRR_SMRR_REQ_CTR_SEATS_Increase +#define DMRR_SeatLongitunalReq_DMRR_SMRR_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef DMRR_SeatLongitunalReq_DMRR_SMRR_REQ_CTR_SEATS_No_action +#define DMRR_SeatLongitunalReq_DMRR_SMRR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @DMRR_SeatBackRestInclinationReq signal + +#ifndef DMRR_SeatBackRestInclinationReq_DMRR_SMRR_REQ_CTR_SEATS_Reserved +#define DMRR_SeatBackRestInclinationReq_DMRR_SMRR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef DMRR_SeatBackRestInclinationReq_DMRR_SMRR_REQ_CTR_SEATS_Decrease +#define DMRR_SeatBackRestInclinationReq_DMRR_SMRR_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef DMRR_SeatBackRestInclinationReq_DMRR_SMRR_REQ_CTR_SEATS_Increase +#define DMRR_SeatBackRestInclinationReq_DMRR_SMRR_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef DMRR_SeatBackRestInclinationReq_DMRR_SMRR_REQ_CTR_SEATS_No_action +#define DMRR_SeatBackRestInclinationReq_DMRR_SMRR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @DMRR_SeatMassageRequest signal + +#ifndef DMRR_SeatMassageRequest_DMRR_SMRR_REQ_CTR_SEATS_Reserved +#define DMRR_SeatMassageRequest_DMRR_SMRR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef DMRR_SeatMassageRequest_DMRR_SMRR_REQ_CTR_SEATS_Massage_ON +#define DMRR_SeatMassageRequest_DMRR_SMRR_REQ_CTR_SEATS_Massage_ON (2) +#endif + +#ifndef DMRR_SeatMassageRequest_DMRR_SMRR_REQ_CTR_SEATS_Massage_OFF +#define DMRR_SeatMassageRequest_DMRR_SMRR_REQ_CTR_SEATS_Massage_OFF (1) +#endif + +#ifndef DMRR_SeatMassageRequest_DMRR_SMRR_REQ_CTR_SEATS_No_action +#define DMRR_SeatMassageRequest_DMRR_SMRR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @DMRR_SeatVentilationRequest signal + +#ifndef DMRR_SeatVentilationRequest_DMRR_SMRR_REQ_CTR_SEATS_Reserved +#define DMRR_SeatVentilationRequest_DMRR_SMRR_REQ_CTR_SEATS_Reserved (7) +#endif + +#ifndef DMRR_SeatVentilationRequest_DMRR_SMRR_REQ_CTR_SEATS_Reserved +#define DMRR_SeatVentilationRequest_DMRR_SMRR_REQ_CTR_SEATS_Reserved (6) +#endif + +#ifndef DMRR_SeatVentilationRequest_DMRR_SMRR_REQ_CTR_SEATS_Reserved +#define DMRR_SeatVentilationRequest_DMRR_SMRR_REQ_CTR_SEATS_Reserved (5) +#endif + +#ifndef DMRR_SeatVentilationRequest_DMRR_SMRR_REQ_CTR_SEATS_No_action +#define DMRR_SeatVentilationRequest_DMRR_SMRR_REQ_CTR_SEATS_No_action (4) +#endif + +#ifndef DMRR_SeatVentilationRequest_DMRR_SMRR_REQ_CTR_SEATS_High_power +#define DMRR_SeatVentilationRequest_DMRR_SMRR_REQ_CTR_SEATS_High_power (3) +#endif + +#ifndef DMRR_SeatVentilationRequest_DMRR_SMRR_REQ_CTR_SEATS_Middle_power +#define DMRR_SeatVentilationRequest_DMRR_SMRR_REQ_CTR_SEATS_Middle_power (2) +#endif + +#ifndef DMRR_SeatVentilationRequest_DMRR_SMRR_REQ_CTR_SEATS_Low_power +#define DMRR_SeatVentilationRequest_DMRR_SMRR_REQ_CTR_SEATS_Low_power (1) +#endif + +#ifndef DMRR_SeatVentilationRequest_DMRR_SMRR_REQ_CTR_SEATS_Off +#define DMRR_SeatVentilationRequest_DMRR_SMRR_REQ_CTR_SEATS_Off (0) +#endif + + +// Value tables for @DMRR_SeatMassageIntence signal + +#ifndef DMRR_SeatMassageIntence_DMRR_SMRR_REQ_CTR_SEATS_High_power +#define DMRR_SeatMassageIntence_DMRR_SMRR_REQ_CTR_SEATS_High_power (3) +#endif + +#ifndef DMRR_SeatMassageIntence_DMRR_SMRR_REQ_CTR_SEATS_Middle_power +#define DMRR_SeatMassageIntence_DMRR_SMRR_REQ_CTR_SEATS_Middle_power (2) +#endif + +#ifndef DMRR_SeatMassageIntence_DMRR_SMRR_REQ_CTR_SEATS_Low_power +#define DMRR_SeatMassageIntence_DMRR_SMRR_REQ_CTR_SEATS_Low_power (1) +#endif + +#ifndef DMRR_SeatMassageIntence_DMRR_SMRR_REQ_CTR_SEATS_No_action +#define DMRR_SeatMassageIntence_DMRR_SMRR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @DMRR_SeatHeatingRequest signal + +#ifndef DMRR_SeatHeatingRequest_DMRR_SMRR_REQ_CTR_SEATS_Reserved +#define DMRR_SeatHeatingRequest_DMRR_SMRR_REQ_CTR_SEATS_Reserved (7) +#endif + +#ifndef DMRR_SeatHeatingRequest_DMRR_SMRR_REQ_CTR_SEATS_Reserved +#define DMRR_SeatHeatingRequest_DMRR_SMRR_REQ_CTR_SEATS_Reserved (6) +#endif + +#ifndef DMRR_SeatHeatingRequest_DMRR_SMRR_REQ_CTR_SEATS_Reserved +#define DMRR_SeatHeatingRequest_DMRR_SMRR_REQ_CTR_SEATS_Reserved (5) +#endif + +#ifndef DMRR_SeatHeatingRequest_DMRR_SMRR_REQ_CTR_SEATS_No_action +#define DMRR_SeatHeatingRequest_DMRR_SMRR_REQ_CTR_SEATS_No_action (4) +#endif + +#ifndef DMRR_SeatHeatingRequest_DMRR_SMRR_REQ_CTR_SEATS_High_power +#define DMRR_SeatHeatingRequest_DMRR_SMRR_REQ_CTR_SEATS_High_power (3) +#endif + +#ifndef DMRR_SeatHeatingRequest_DMRR_SMRR_REQ_CTR_SEATS_Middle_power +#define DMRR_SeatHeatingRequest_DMRR_SMRR_REQ_CTR_SEATS_Middle_power (2) +#endif + +#ifndef DMRR_SeatHeatingRequest_DMRR_SMRR_REQ_CTR_SEATS_Low_power +#define DMRR_SeatHeatingRequest_DMRR_SMRR_REQ_CTR_SEATS_Low_power (1) +#endif + +#ifndef DMRR_SeatHeatingRequest_DMRR_SMRR_REQ_CTR_SEATS_Off +#define DMRR_SeatHeatingRequest_DMRR_SMRR_REQ_CTR_SEATS_Off (0) +#endif + + +// Value tables for @DMRR_SeatInclination_Req signal + +#ifndef DMRR_SeatInclination_Req_DMRR_SMRR_REQ_CTR_SEATS_Reserved +#define DMRR_SeatInclination_Req_DMRR_SMRR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef DMRR_SeatInclination_Req_DMRR_SMRR_REQ_CTR_SEATS_Decrease +#define DMRR_SeatInclination_Req_DMRR_SMRR_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef DMRR_SeatInclination_Req_DMRR_SMRR_REQ_CTR_SEATS_Increase +#define DMRR_SeatInclination_Req_DMRR_SMRR_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef DMRR_SeatInclination_Req_DMRR_SMRR_REQ_CTR_SEATS_No_action +#define DMRR_SeatInclination_Req_DMRR_SMRR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @DMRR_SeatFootRestHeightReq signal + +#ifndef DMRR_SeatFootRestHeightReq_DMRR_SMRR_REQ_CTR_SEATS_Reserved +#define DMRR_SeatFootRestHeightReq_DMRR_SMRR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef DMRR_SeatFootRestHeightReq_DMRR_SMRR_REQ_CTR_SEATS_Decrease +#define DMRR_SeatFootRestHeightReq_DMRR_SMRR_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef DMRR_SeatFootRestHeightReq_DMRR_SMRR_REQ_CTR_SEATS_Increase +#define DMRR_SeatFootRestHeightReq_DMRR_SMRR_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef DMRR_SeatFootRestHeightReq_DMRR_SMRR_REQ_CTR_SEATS_No_action +#define DMRR_SeatFootRestHeightReq_DMRR_SMRR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @DMRR_MoreComfort_Req signal + +#ifndef DMRR_MoreComfort_Req_DMRR_SMRR_REQ_CTR_SEATS_Unfold_requested +#define DMRR_MoreComfort_Req_DMRR_SMRR_REQ_CTR_SEATS_Unfold_requested (2) +#endif + +#ifndef DMRR_MoreComfort_Req_DMRR_SMRR_REQ_CTR_SEATS_Fold_requested +#define DMRR_MoreComfort_Req_DMRR_SMRR_REQ_CTR_SEATS_Fold_requested (1) +#endif + +#ifndef DMRR_MoreComfort_Req_DMRR_SMRR_REQ_CTR_SEATS_Not_requested +#define DMRR_MoreComfort_Req_DMRR_SMRR_REQ_CTR_SEATS_Not_requested (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Request for saving the seat positions + // 0x0 = No request + // 0x1 = request to save mem 1 + // 0x2 = request to save mem 2 + // 0x3 = Reserved + // 6 : "request to upload mem 3" + // 5 : "request to upload mem 2" + // 4 : "request to upload mem 1" + // 3 : "request to save mem 3" + // 2 : "request to save mem 2" + // 1 : "request to save mem 1" + // 0 : "No request" + uint8_t DMRR_SeatMemReq : 3; // Bits= 3 + + // Signal for regulation Seat Height RR + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t DMRR_SeatHeightReq : 2; // Bits= 2 + + // Request to control the FR seat from the RL passenger side + // 1 : "Seat control change requested" + // 0 : "Not requested" + uint8_t DMRR_FrontPass_Req : 1; // Bits= 1 + + // Signal for regulation RR seat longitunal + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t DMRR_SeatLongitunalReq : 2; // Bits= 2 + + // Signal for regulation RR seat backrest lnclination + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t DMRR_SeatBackRestInclinationReq : 2; // Bits= 2 + + // Signal for seat massage activation + // 3 : "Reserved" + // 2 : "Massage ON" + // 1 : "Massage OFF" + // 0 : "No action" + uint8_t DMRR_SeatMassageRequest : 2; // Bits= 2 + + // Signal for ventilation activation mode + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Reserved" + // 4 : "No action" + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "Off" + uint8_t DMRR_SeatVentilationRequest : 3; // Bits= 3 + + // Signal for seat massage intencity regulation + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "No action" + uint8_t DMRR_SeatMassageIntence : 2; // Bits= 2 + + // Signal for seat heating activation mode + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Reserved" + // 4 : "No action" + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "Off" + uint8_t DMRR_SeatHeatingRequest : 3; // Bits= 3 + + // Signal for regulation RR seat inclination + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t DMRR_SeatInclination_Req : 2; // Bits= 2 + + // Signal for regulation RR seat foot rest height + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t DMRR_SeatFootRestHeightReq : 2; // Bits= 2 + + // Request for comfort mode RR seat + // 2 : "Unfold requested" + // 1 : "Fold requested" + // 0 : "Not requested" + uint8_t DMRR_MoreComfort_Req : 2; // Bits= 2 + +#else + + // Request for saving the seat positions + // 0x0 = No request + // 0x1 = request to save mem 1 + // 0x2 = request to save mem 2 + // 0x3 = Reserved + // 6 : "request to upload mem 3" + // 5 : "request to upload mem 2" + // 4 : "request to upload mem 1" + // 3 : "request to save mem 3" + // 2 : "request to save mem 2" + // 1 : "request to save mem 1" + // 0 : "No request" + uint8_t DMRR_SeatMemReq; // Bits= 3 + + // Signal for regulation Seat Height RR + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t DMRR_SeatHeightReq; // Bits= 2 + + // Request to control the FR seat from the RL passenger side + // 1 : "Seat control change requested" + // 0 : "Not requested" + uint8_t DMRR_FrontPass_Req; // Bits= 1 + + // Signal for regulation RR seat longitunal + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t DMRR_SeatLongitunalReq; // Bits= 2 + + // Signal for regulation RR seat backrest lnclination + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t DMRR_SeatBackRestInclinationReq; // Bits= 2 + + // Signal for seat massage activation + // 3 : "Reserved" + // 2 : "Massage ON" + // 1 : "Massage OFF" + // 0 : "No action" + uint8_t DMRR_SeatMassageRequest; // Bits= 2 + + // Signal for ventilation activation mode + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Reserved" + // 4 : "No action" + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "Off" + uint8_t DMRR_SeatVentilationRequest; // Bits= 3 + + // Signal for seat massage intencity regulation + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "No action" + uint8_t DMRR_SeatMassageIntence; // Bits= 2 + + // Signal for seat heating activation mode + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Reserved" + // 4 : "No action" + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "Off" + uint8_t DMRR_SeatHeatingRequest; // Bits= 3 + + // Signal for regulation RR seat inclination + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t DMRR_SeatInclination_Req; // Bits= 2 + + // Signal for regulation RR seat foot rest height + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t DMRR_SeatFootRestHeightReq; // Bits= 2 + + // Request for comfort mode RR seat + // 2 : "Unfold requested" + // 1 : "Fold requested" + // 0 : "Not requested" + uint8_t DMRR_MoreComfort_Req; // Bits= 2 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} DMRR_SMRR_REQ_CTR_SEATS_t; + +// def @CCU_Msg1 CAN Message (896 0x380) +#define CCU_Msg1_IDE (0U) +#define CCU_Msg1_DLC (8U) +#define CCU_Msg1_CANID (0x380U) +#define CCU_Msg1_CYC (250U) + +// Value tables for @CCU_MirrorHeating_Req signal + +#ifndef CCU_MirrorHeating_Req_CCU_Msg1_Error +#define CCU_MirrorHeating_Req_CCU_Msg1_Error (3) +#endif + +#ifndef CCU_MirrorHeating_Req_CCU_Msg1_Heating_off_requested +#define CCU_MirrorHeating_Req_CCU_Msg1_Heating_off_requested (2) +#endif + +#ifndef CCU_MirrorHeating_Req_CCU_Msg1_Heating_on_requested +#define CCU_MirrorHeating_Req_CCU_Msg1_Heating_on_requested (1) +#endif + +#ifndef CCU_MirrorHeating_Req_CCU_Msg1_Unknown +#define CCU_MirrorHeating_Req_CCU_Msg1_Unknown (0) +#endif + + +// Value tables for @CCU_RecirculationLed_Cmd signal + +#ifndef CCU_RecirculationLed_Cmd_CCU_Msg1_On +#define CCU_RecirculationLed_Cmd_CCU_Msg1_On (1) +#endif + +#ifndef CCU_RecirculationLed_Cmd_CCU_Msg1_Off +#define CCU_RecirculationLed_Cmd_CCU_Msg1_Off (0) +#endif + + +// Value tables for @CCU_DefrostLed_Req signal + +#ifndef CCU_DefrostLed_Req_CCU_Msg1_On +#define CCU_DefrostLed_Req_CCU_Msg1_On (1) +#endif + +#ifndef CCU_DefrostLed_Req_CCU_Msg1_Off +#define CCU_DefrostLed_Req_CCU_Msg1_Off (0) +#endif + + +// Value tables for @CCU_SideWindowHeating_Req signal + +#ifndef CCU_SideWindowHeating_Req_CCU_Msg1_Error +#define CCU_SideWindowHeating_Req_CCU_Msg1_Error (3) +#endif + +#ifndef CCU_SideWindowHeating_Req_CCU_Msg1_Heating_off_requested +#define CCU_SideWindowHeating_Req_CCU_Msg1_Heating_off_requested (2) +#endif + +#ifndef CCU_SideWindowHeating_Req_CCU_Msg1_Heating_on_requested +#define CCU_SideWindowHeating_Req_CCU_Msg1_Heating_on_requested (1) +#endif + +#ifndef CCU_SideWindowHeating_Req_CCU_Msg1_Unknown +#define CCU_SideWindowHeating_Req_CCU_Msg1_Unknown (0) +#endif + + +// Value tables for @CCU_RearWindowHeating_Req signal + +#ifndef CCU_RearWindowHeating_Req_CCU_Msg1_Error +#define CCU_RearWindowHeating_Req_CCU_Msg1_Error (3) +#endif + +#ifndef CCU_RearWindowHeating_Req_CCU_Msg1_Heating_off_requested +#define CCU_RearWindowHeating_Req_CCU_Msg1_Heating_off_requested (2) +#endif + +#ifndef CCU_RearWindowHeating_Req_CCU_Msg1_Heating_on_requested +#define CCU_RearWindowHeating_Req_CCU_Msg1_Heating_on_requested (1) +#endif + +#ifndef CCU_RearWindowHeating_Req_CCU_Msg1_Unknown +#define CCU_RearWindowHeating_Req_CCU_Msg1_Unknown (0) +#endif + + +// Value tables for @CCU_FrontWindowHeating_Req signal + +#ifndef CCU_FrontWindowHeating_Req_CCU_Msg1_Error +#define CCU_FrontWindowHeating_Req_CCU_Msg1_Error (3) +#endif + +#ifndef CCU_FrontWindowHeating_Req_CCU_Msg1_Heating_off_requested +#define CCU_FrontWindowHeating_Req_CCU_Msg1_Heating_off_requested (2) +#endif + +#ifndef CCU_FrontWindowHeating_Req_CCU_Msg1_Heating_on_requested +#define CCU_FrontWindowHeating_Req_CCU_Msg1_Heating_on_requested (1) +#endif + +#ifndef CCU_FrontWindowHeating_Req_CCU_Msg1_Unknown +#define CCU_FrontWindowHeating_Req_CCU_Msg1_Unknown (0) +#endif + + +// Value tables for @CCU_EmergAirCleaning_Stat signal + +#ifndef CCU_EmergAirCleaning_Stat_CCU_Msg1_Active +#define CCU_EmergAirCleaning_Stat_CCU_Msg1_Active (1) +#endif + +#ifndef CCU_EmergAirCleaning_Stat_CCU_Msg1_Incative +#define CCU_EmergAirCleaning_Stat_CCU_Msg1_Incative (0) +#endif + + +// Value tables for @CCU_FireExtinguishSys_Stat signal + +#ifndef CCU_FireExtinguishSys_Stat_CCU_Msg1_Active +#define CCU_FireExtinguishSys_Stat_CCU_Msg1_Active (1) +#endif + +#ifndef CCU_FireExtinguishSys_Stat_CCU_Msg1_Inactive +#define CCU_FireExtinguishSys_Stat_CCU_Msg1_Inactive (0) +#endif + + +// Value tables for @CCU_FLAutoPsngrLed_Cmd signal + +#ifndef CCU_FLAutoPsngrLed_Cmd_CCU_Msg1_On +#define CCU_FLAutoPsngrLed_Cmd_CCU_Msg1_On (1) +#endif + +#ifndef CCU_FLAutoPsngrLed_Cmd_CCU_Msg1_Off +#define CCU_FLAutoPsngrLed_Cmd_CCU_Msg1_Off (0) +#endif + + +// Value tables for @CCU_FRAutoPsngrLed_Cmd signal + +#ifndef CCU_FRAutoPsngrLed_Cmd_CCU_Msg1_On +#define CCU_FRAutoPsngrLed_Cmd_CCU_Msg1_On (1) +#endif + +#ifndef CCU_FRAutoPsngrLed_Cmd_CCU_Msg1_Off +#define CCU_FRAutoPsngrLed_Cmd_CCU_Msg1_Off (0) +#endif + + +// Value tables for @CCU_RLAutoPsngrLed_Cmd signal + +#ifndef CCU_RLAutoPsngrLed_Cmd_CCU_Msg1_On +#define CCU_RLAutoPsngrLed_Cmd_CCU_Msg1_On (1) +#endif + +#ifndef CCU_RLAutoPsngrLed_Cmd_CCU_Msg1_Off +#define CCU_RLAutoPsngrLed_Cmd_CCU_Msg1_Off (0) +#endif + + +// Value tables for @CCU_RRAutoPsngrLed_Cmd signal + +#ifndef CCU_RRAutoPsngrLed_Cmd_CCU_Msg1_On +#define CCU_RRAutoPsngrLed_Cmd_CCU_Msg1_On (1) +#endif + +#ifndef CCU_RRAutoPsngrLed_Cmd_CCU_Msg1_Off +#define CCU_RRAutoPsngrLed_Cmd_CCU_Msg1_Off (0) +#endif + + +// Value tables for @CCU_AC_MaxLed_Cmd signal + +#ifndef CCU_AC_MaxLed_Cmd_CCU_Msg1_On +#define CCU_AC_MaxLed_Cmd_CCU_Msg1_On (1) +#endif + +#ifndef CCU_AC_MaxLed_Cmd_CCU_Msg1_Off +#define CCU_AC_MaxLed_Cmd_CCU_Msg1_Off (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Request to activate mirrors heating + // 3 : "Error" + // 2 : "Heating off requested" + // 1 : "Heating on requested" + // 0 : "Unknown" + uint8_t CCU_MirrorHeating_Req : 2; // Bits= 2 + + // Air recirculation LED indicator command + // 1 : "On" + // 0 : "Off" + uint8_t CCU_RecirculationLed_Cmd : 1; // Bits= 1 + + // Defrost function LED indicator on/off request + // 1 : "On" + // 0 : "Off" + uint8_t CCU_DefrostLed_Req : 1; // Bits= 1 + + // Request to activate side windows heating + // 3 : "Error" + // 2 : "Heating off requested" + // 1 : "Heating on requested" + // 0 : "Unknown" + uint8_t CCU_SideWindowHeating_Req : 2; // Bits= 2 + + // Request to activate rear window heating + // 3 : "Error" + // 2 : "Heating off requested" + // 1 : "Heating on requested" + // 0 : "Unknown" + uint8_t CCU_RearWindowHeating_Req : 2; // Bits= 2 + + // Request to activate front window heating + // 3 : "Error" + // 2 : "Heating off requested" + // 1 : "Heating on requested" + // 0 : "Unknown" + uint8_t CCU_FrontWindowHeating_Req : 2; // Bits= 2 + + // Status of emergency air cleaning system + // 1 : "Active" + // 0 : "Incative" + uint8_t CCU_EmergAirCleaning_Stat : 1; // Bits= 1 + + // Status of fire extinguishing system + // 1 : "Active" + // 0 : "Inactive" + uint8_t CCU_FireExtinguishSys_Stat : 1; // Bits= 1 + + // Automate climate control On/Off LED command + // 1 : "On" + // 0 : "Off" + uint8_t CCU_FLAutoPsngrLed_Cmd : 1; // Bits= 1 + + // Automate climate control On/Off LED command + // 1 : "On" + // 0 : "Off" + uint8_t CCU_FRAutoPsngrLed_Cmd : 1; // Bits= 1 + + // Automate climate control On/Off LED command + // 1 : "On" + // 0 : "Off" + uint8_t CCU_RLAutoPsngrLed_Cmd : 1; // Bits= 1 + + // Automate climate control On/Off LED command + // 1 : "On" + // 0 : "Off" + uint8_t CCU_RRAutoPsngrLed_Cmd : 1; // Bits= 1 + + // LED indicator command in CCPF when automatic Coditioner with max power is Active + // 1 : "On" + // 0 : "Off" + uint8_t CCU_AC_MaxLed_Cmd : 1; // Bits= 1 + + // Rolling Counter [0 - 15] + uint8_t CCU_MSG1_RC : 4; // Bits= 4 + + // Checksum XOR8 of the data field this message + // Checksum computed as per XOR algorithm: + // Byte 1 XOR byte 2 .... XOR byte n-1. (n = packet length.) + uint8_t CCU_MSG1_CS; // Bits= 8 + +#else + + // Request to activate mirrors heating + // 3 : "Error" + // 2 : "Heating off requested" + // 1 : "Heating on requested" + // 0 : "Unknown" + uint8_t CCU_MirrorHeating_Req; // Bits= 2 + + // Air recirculation LED indicator command + // 1 : "On" + // 0 : "Off" + uint8_t CCU_RecirculationLed_Cmd; // Bits= 1 + + // Defrost function LED indicator on/off request + // 1 : "On" + // 0 : "Off" + uint8_t CCU_DefrostLed_Req; // Bits= 1 + + // Request to activate side windows heating + // 3 : "Error" + // 2 : "Heating off requested" + // 1 : "Heating on requested" + // 0 : "Unknown" + uint8_t CCU_SideWindowHeating_Req; // Bits= 2 + + // Request to activate rear window heating + // 3 : "Error" + // 2 : "Heating off requested" + // 1 : "Heating on requested" + // 0 : "Unknown" + uint8_t CCU_RearWindowHeating_Req; // Bits= 2 + + // Request to activate front window heating + // 3 : "Error" + // 2 : "Heating off requested" + // 1 : "Heating on requested" + // 0 : "Unknown" + uint8_t CCU_FrontWindowHeating_Req; // Bits= 2 + + // Status of emergency air cleaning system + // 1 : "Active" + // 0 : "Incative" + uint8_t CCU_EmergAirCleaning_Stat; // Bits= 1 + + // Status of fire extinguishing system + // 1 : "Active" + // 0 : "Inactive" + uint8_t CCU_FireExtinguishSys_Stat; // Bits= 1 + + // Automate climate control On/Off LED command + // 1 : "On" + // 0 : "Off" + uint8_t CCU_FLAutoPsngrLed_Cmd; // Bits= 1 + + // Automate climate control On/Off LED command + // 1 : "On" + // 0 : "Off" + uint8_t CCU_FRAutoPsngrLed_Cmd; // Bits= 1 + + // Automate climate control On/Off LED command + // 1 : "On" + // 0 : "Off" + uint8_t CCU_RLAutoPsngrLed_Cmd; // Bits= 1 + + // Automate climate control On/Off LED command + // 1 : "On" + // 0 : "Off" + uint8_t CCU_RRAutoPsngrLed_Cmd; // Bits= 1 + + // LED indicator command in CCPF when automatic Coditioner with max power is Active + // 1 : "On" + // 0 : "Off" + uint8_t CCU_AC_MaxLed_Cmd; // Bits= 1 + + // Rolling Counter [0 - 15] + uint8_t CCU_MSG1_RC; // Bits= 4 + + // Checksum XOR8 of the data field this message + // Checksum computed as per XOR algorithm: + // Byte 1 XOR byte 2 .... XOR byte n-1. (n = packet length.) + uint8_t CCU_MSG1_CS; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} CCU_Msg1_t; + +// def @Sroof_State CAN Message (906 0x38a) +#define Sroof_State_IDE (0U) +#define Sroof_State_DLC (1U) +#define Sroof_State_CANID (0x38aU) +#define Sroof_State_CYC (100U) + +// Value tables for @Sroof_Movement_Stat signal + +#ifndef Sroof_Movement_Stat_Sroof_State_Roof_is_closing +#define Sroof_Movement_Stat_Sroof_State_Roof_is_closing (2) +#endif + +#ifndef Sroof_Movement_Stat_Sroof_State_Roof_is_stopped +#define Sroof_Movement_Stat_Sroof_State_Roof_is_stopped (0) +#endif + +#ifndef Sroof_Movement_Stat_Sroof_State_Roof_is_opening +#define Sroof_Movement_Stat_Sroof_State_Roof_is_opening (1) +#endif + + +// Value tables for @Sroof_Position_Stat signal + +#ifndef Sroof_Position_Stat_Sroof_State_Roof_in_unknown_state +#define Sroof_Position_Stat_Sroof_State_Roof_in_unknown_state (0) +#endif + +#ifndef Sroof_Position_Stat_Sroof_State_Roof_is_closed +#define Sroof_Position_Stat_Sroof_State_Roof_is_closed (1) +#endif + +#ifndef Sroof_Position_Stat_Sroof_State_Roof_in_middle_state +#define Sroof_Position_Stat_Sroof_State_Roof_in_middle_state (2) +#endif + +#ifndef Sroof_Position_Stat_Sroof_State_Roof_is_opened +#define Sroof_Position_Stat_Sroof_State_Roof_is_opened (3) +#endif + + +// Value tables for @Sroof_Antipinch_Stat signal + +#ifndef Sroof_Antipinch_Stat_Sroof_State_No_antipinch +#define Sroof_Antipinch_Stat_Sroof_State_No_antipinch (0) +#endif + +#ifndef Sroof_Antipinch_Stat_Sroof_State_Antipinch_detect +#define Sroof_Antipinch_Stat_Sroof_State_Antipinch_detect (1) +#endif + + +// Value tables for @Sroof_Error_Stat signal + +#ifndef Sroof_Error_Stat_Sroof_State_No_error +#define Sroof_Error_Stat_Sroof_State_No_error (0) +#endif + +#ifndef Sroof_Error_Stat_Sroof_State_System_error +#define Sroof_Error_Stat_Sroof_State_System_error (1) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Current roof motion status + // 2 : "Roof is closing" + // 0 : "Roof is stopped" + // 1 : "Roof is opening" + uint8_t Sroof_Movement_Stat : 2; // Bits= 2 + + // Current roof position. + // 0 : "Roof in unknown state" + // 1 : "Roof is closed" + // 2 : "Roof in middle state" + // 3 : "Roof is opened" + uint8_t Sroof_Position_Stat : 2; // Bits= 2 + + // Antipinch detection status + // 0 : "No antipinch" + // 1 : "Antipinch detect" + uint8_t Sroof_Antipinch_Stat : 1; // Bits= 1 + + // Errors in the operation of the convertible roof control system + // 0 : "No error" + // 1 : "System error" + uint8_t Sroof_Error_Stat : 1; // Bits= 1 + +#else + + // Current roof motion status + // 2 : "Roof is closing" + // 0 : "Roof is stopped" + // 1 : "Roof is opening" + uint8_t Sroof_Movement_Stat; // Bits= 2 + + // Current roof position. + // 0 : "Roof in unknown state" + // 1 : "Roof is closed" + // 2 : "Roof in middle state" + // 3 : "Roof is opened" + uint8_t Sroof_Position_Stat; // Bits= 2 + + // Antipinch detection status + // 0 : "No antipinch" + // 1 : "Antipinch detect" + uint8_t Sroof_Antipinch_Stat; // Bits= 1 + + // Errors in the operation of the convertible roof control system + // 0 : "No error" + // 1 : "System error" + uint8_t Sroof_Error_Stat; // Bits= 1 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Sroof_State_t; + +// def @VCU_CCU_Req CAN Message (925 0x39d) +#define VCU_CCU_Req_IDE (0U) +#define VCU_CCU_Req_DLC (4U) +#define VCU_CCU_Req_CANID (0x39dU) +#define VCU_CCU_Req_CYC (200U) +// signal: @VCU_LiquidHeaterCurrentTemp_Stat_ro +#define CANDB_VCU_LiquidHeaterCurrentTemp_Stat_ro_CovFactor (0.5) +#define CANDB_VCU_LiquidHeaterCurrentTemp_Stat_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.5)) ) +#define CANDB_VCU_LiquidHeaterCurrentTemp_Stat_ro_fromS(x) ( (((x) * (0.5)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + uint8_t VCU_eTXV_batChiller_Pos_Req : 7; // Bits= 7 Unit:'%' + + uint8_t VCU_eTXV_eeChiller_Pos_Req : 7; // Bits= 7 Unit:'%' + + // Status from VCU about current temperature Liquid HVAC Heater + uint8_t VCU_LiquidHeaterCurrentTemp_Stat_ro; // Bits= 8 Factor= 0.5 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t VCU_LiquidHeaterCurrentTemp_Stat_phys; +#endif // CANDB_USE_SIGFLOAT + + // Rolling Counter [0 - 15] + uint8_t VCU_CCU_Req_RC : 4; // Bits= 4 + +#else + + uint8_t VCU_eTXV_batChiller_Pos_Req; // Bits= 7 Unit:'%' + + uint8_t VCU_eTXV_eeChiller_Pos_Req; // Bits= 7 Unit:'%' + + // Status from VCU about current temperature Liquid HVAC Heater + uint8_t VCU_LiquidHeaterCurrentTemp_Stat_ro; // Bits= 8 Factor= 0.5 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t VCU_LiquidHeaterCurrentTemp_Stat_phys; +#endif // CANDB_USE_SIGFLOAT + + // Rolling Counter [0 - 15] + uint8_t VCU_CCU_Req_RC; // Bits= 4 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} VCU_CCU_Req_t; + +// def @IC_DATA_MSG CAN Message (938 0x3aa) +#define IC_DATA_MSG_IDE (0U) +#define IC_DATA_MSG_DLC (7U) +#define IC_DATA_MSG_CANID (0x3aaU) +#define IC_DATA_MSG_CYC (100U) +// signal: @IC_EstimatedCruiseRange_ro +#define CANDB_IC_EstimatedCruiseRange_ro_CovFactor (10) +#define CANDB_IC_EstimatedCruiseRange_ro_toS(x) ( (uint8_t) ((x) / (10)) ) +#define CANDB_IC_EstimatedCruiseRange_ro_fromS(x) ( ((x) * (10)) ) + +// Value tables for @IC_BrakePadCondition_Stat signal + +#ifndef IC_BrakePadCondition_Stat_IC_DATA_MSG_Low_condition +#define IC_BrakePadCondition_Stat_IC_DATA_MSG_Low_condition (1) +#endif + +#ifndef IC_BrakePadCondition_Stat_IC_DATA_MSG_Normal +#define IC_BrakePadCondition_Stat_IC_DATA_MSG_Normal (0) +#endif + + +// Value tables for @IC_BrakeLiquidLvl_Stat signal + +#ifndef IC_BrakeLiquidLvl_Stat_IC_DATA_MSG_Low_level +#define IC_BrakeLiquidLvl_Stat_IC_DATA_MSG_Low_level (1) +#endif + +#ifndef IC_BrakeLiquidLvl_Stat_IC_DATA_MSG_Normal +#define IC_BrakeLiquidLvl_Stat_IC_DATA_MSG_Normal (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Sends to FIU the calculated brightness of the screen. + // This calculation is made by using the internal light sensor data and the SI_BCMBacklightBrightness received from BCM. + // [0% - 100%] + uint8_t DisplayBacklightBrightness : 7; // Bits= 7 Unit:'%' + + // Indicates an estimation of the autonomy. + uint8_t IC_EstimatedCruiseRange_ro; // Bits= 8 Factor= 10 + +#ifdef CANDB_USE_SIGFLOAT + uint16_t IC_EstimatedCruiseRange_phys; +#endif // CANDB_USE_SIGFLOAT + + // Indication of Days to visit service + int16_t IC_ServiceDate; // [-] Bits=16 Unit:'day' + + // Indication of mileage to visit service + int32_t IC_ServiceMileage; // [-] Bits=20 Unit:'km' + + // Status of brake pad condition + // 1 : "Low condition" + // 0 : "Normal" + uint8_t IC_BrakePadCondition_Stat : 1; // Bits= 1 + + // Status of brake liquid level + // 1 : "Low level" + // 0 : "Normal" + uint8_t IC_BrakeLiquidLvl_Stat : 1; // Bits= 1 + +#else + + // Sends to FIU the calculated brightness of the screen. + // This calculation is made by using the internal light sensor data and the SI_BCMBacklightBrightness received from BCM. + // [0% - 100%] + uint8_t DisplayBacklightBrightness; // Bits= 7 Unit:'%' + + // Indicates an estimation of the autonomy. + uint8_t IC_EstimatedCruiseRange_ro; // Bits= 8 Factor= 10 + +#ifdef CANDB_USE_SIGFLOAT + uint16_t IC_EstimatedCruiseRange_phys; +#endif // CANDB_USE_SIGFLOAT + + // Indication of Days to visit service + int16_t IC_ServiceDate; // [-] Bits=16 Unit:'day' + + // Indication of mileage to visit service + int32_t IC_ServiceMileage; // [-] Bits=20 Unit:'km' + + // Status of brake pad condition + // 1 : "Low condition" + // 0 : "Normal" + uint8_t IC_BrakePadCondition_Stat; // Bits= 1 + + // Status of brake liquid level + // 1 : "Low level" + // 0 : "Normal" + uint8_t IC_BrakeLiquidLvl_Stat; // Bits= 1 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} IC_DATA_MSG_t; + +// def @ESC_08 CAN Message (961 0x3c1) +#define ESC_08_IDE (0U) +#define ESC_08_DLC (5U) +#define ESC_08_CANID (0x3c1U) +#define ESC_08_CYC (500U) +// signal: @ESC_Mileage_Val_ro +#define CANDB_ESC_Mileage_Val_ro_CovFactor (0.1) +#define CANDB_ESC_Mileage_Val_ro_toS(x) ( (uint32_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_ESC_Mileage_Val_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Mileage/ odometer signal to provide vehicle mileage information. + // 0x7FFFFFF = Error + uint32_t ESC_Mileage_Val_ro; // Bits=27 Factor= 0.1 Unit:'km' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t ESC_Mileage_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Rolling Counter [0 - 15] + uint8_t ESC_08_RC : 4; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t ESC_08_CS; // Bits= 8 + +#else + + // Mileage/ odometer signal to provide vehicle mileage information. + // 0x7FFFFFF = Error + uint32_t ESC_Mileage_Val_ro; // Bits=27 Factor= 0.1 Unit:'km' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t ESC_Mileage_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Rolling Counter [0 - 15] + uint8_t ESC_08_RC; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t ESC_08_CS; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} ESC_08_t; + +// def @WChF_Status CAN Message (971 0x3cb) +#define WChF_Status_IDE (0U) +#define WChF_Status_DLC (8U) +#define WChF_Status_CANID (0x3cbU) +#define WChF_Status_CYC (500U) + +// Value tables for @WChF_Status_Stat signal + +#ifndef WChF_Status_Stat_WChF_Status_On +#define WChF_Status_Stat_WChF_Status_On (1) +#endif + +#ifndef WChF_Status_Stat_WChF_Status_Off +#define WChF_Status_Stat_WChF_Status_Off (0) +#endif + + +// Value tables for @WChF_Charge_Stat signal + +#ifndef WChF_Charge_Stat_WChF_Status_On +#define WChF_Charge_Stat_WChF_Status_On (1) +#endif + +#ifndef WChF_Charge_Stat_WChF_Status_Off +#define WChF_Charge_Stat_WChF_Status_Off (0) +#endif + + +// Value tables for @WChF_ShortCircuit5V_Stat signal + +#ifndef WChF_ShortCircuit5V_Stat_WChF_Status_Failure +#define WChF_ShortCircuit5V_Stat_WChF_Status_Failure (1) +#endif + +#ifndef WChF_ShortCircuit5V_Stat_WChF_Status_No_failure +#define WChF_ShortCircuit5V_Stat_WChF_Status_No_failure (0) +#endif + + +// Value tables for @WChF_Comm_Stat signal + +#ifndef WChF_Comm_Stat_WChF_Status_Failure +#define WChF_Comm_Stat_WChF_Status_Failure (1) +#endif + +#ifndef WChF_Comm_Stat_WChF_Status_No_failure +#define WChF_Comm_Stat_WChF_Status_No_failure (0) +#endif + + +// Value tables for @WChF_Malfunction_Stat signal + +#ifndef WChF_Malfunction_Stat_WChF_Status_Failure +#define WChF_Malfunction_Stat_WChF_Status_Failure (1) +#endif + +#ifndef WChF_Malfunction_Stat_WChF_Status_No_failure +#define WChF_Malfunction_Stat_WChF_Status_No_failure (0) +#endif + + +// Value tables for @WChF_NFCDevice_Stat signal + +#ifndef WChF_NFCDevice_Stat_WChF_Status_Reserved +#define WChF_NFCDevice_Stat_WChF_Status_Reserved (7) +#endif + +#ifndef WChF_NFCDevice_Stat_WChF_Status_Reserved +#define WChF_NFCDevice_Stat_WChF_Status_Reserved (6) +#endif + +#ifndef WChF_NFCDevice_Stat_WChF_Status_Reserved +#define WChF_NFCDevice_Stat_WChF_Status_Reserved (5) +#endif + +#ifndef WChF_NFCDevice_Stat_WChF_Status_Reserved +#define WChF_NFCDevice_Stat_WChF_Status_Reserved (4) +#endif + +#ifndef WChF_NFCDevice_Stat_WChF_Status_Reserved +#define WChF_NFCDevice_Stat_WChF_Status_Reserved (3) +#endif + +#ifndef WChF_NFCDevice_Stat_WChF_Status_NFC_Smartphone_detect +#define WChF_NFCDevice_Stat_WChF_Status_NFC_Smartphone_detect (2) +#endif + +#ifndef WChF_NFCDevice_Stat_WChF_Status_NFC_card_detect +#define WChF_NFCDevice_Stat_WChF_Status_NFC_card_detect (1) +#endif + +#ifndef WChF_NFCDevice_Stat_WChF_Status_No_devices_detect +#define WChF_NFCDevice_Stat_WChF_Status_No_devices_detect (0) +#endif + +// signal: @WChF_PowerQI_Stat_ro +#define CANDB_WChF_PowerQI_Stat_ro_CovFactor (0.1) +#define CANDB_WChF_PowerQI_Stat_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_WChF_PowerQI_Stat_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @WChF_CurrentTx_Stat_ro +#define CANDB_WChF_CurrentTx_Stat_ro_CovFactor (0.1) +#define CANDB_WChF_CurrentTx_Stat_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_WChF_CurrentTx_Stat_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +// Value tables for @WChF_Frequency_Stat signal + +#ifndef WChF_Frequency_Stat_WChF_Status_Signal_not_availablefailure +#define WChF_Frequency_Stat_WChF_Status_Signal_not_availablefailure (255) +#endif + +// signal: @WChF_TempCoil_Stat_ro +#define CANDB_WChF_TempCoil_Stat_ro_CovFactor (1) +#define CANDB_WChF_TempCoil_Stat_ro_toS(x) ( (uint8_t) ((x) - (-40)) ) +#define CANDB_WChF_TempCoil_Stat_ro_fromS(x) ( ((x) + (-40)) ) + +// Value tables for @WChF_BT_Stat signal + +#ifndef WChF_BT_Stat_WChF_Status_WChf_has_BT_info +#define WChF_BT_Stat_WChF_Status_WChf_has_BT_info (1) +#endif + +#ifndef WChF_BT_Stat_WChF_Status_WChF_has_no_BT_info +#define WChF_BT_Stat_WChF_Status_WChF_has_no_BT_info (0) +#endif + + +// Value tables for @WChF_WiFi_Stat signal + +#ifndef WChF_WiFi_Stat_WChF_Status_WChF_has_WiFi_info +#define WChF_WiFi_Stat_WChF_Status_WChF_has_WiFi_info (1) +#endif + +#ifndef WChF_WiFi_Stat_WChF_Status_WChF_has_no_WiFi_info +#define WChF_WiFi_Stat_WChF_Status_WChF_has_no_WiFi_info (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Work status on state on/off + // 1 : "On" + // 0 : "Off" + uint8_t WChF_Status_Stat : 1; // Bits= 1 + + // Status charge on/off + // 1 : "On" + // 0 : "Off" + uint8_t WChF_Charge_Stat : 1; // Bits= 1 + + // Supply chain short circuit + // 1 : "Failure" + // 0 : "No failure" + uint8_t WChF_ShortCircuit5V_Stat : 1; // Bits= 1 + + // Communication error + // 1 : "Failure" + // 0 : "No failure" + uint8_t WChF_Comm_Stat : 1; // Bits= 1 + + // Malfunction of the upper PCB with antenna, coil. + // 1 : "Failure" + // 0 : "No failure" + uint8_t WChF_Malfunction_Stat : 1; // Bits= 1 + + // NFC device detection status + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Reserved" + // 4 : "Reserved" + // 3 : "Reserved" + // 2 : "NFC Smartphone detect" + // 1 : "NFC card detect" + // 0 : "No devices detect" + uint8_t WChF_NFCDevice_Stat : 3; // Bits= 3 + + // Status about the current power QI of the current charge + uint8_t WChF_PowerQI_Stat_ro; // Bits= 8 Factor= 0.1 Unit:'W' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t WChF_PowerQI_Stat_phys; +#endif // CANDB_USE_SIGFLOAT + + // Status about current charging current + uint8_t WChF_CurrentTx_Stat_ro; // Bits= 8 Factor= 0.1 Unit:'A' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t WChF_CurrentTx_Stat_phys; +#endif // CANDB_USE_SIGFLOAT + + // Status about current frequency + // 255 : "Signal not available/failure" + uint8_t WChF_Frequency_Stat; // Bits= 8 Unit:'kHz' + + // Status about coil temperature + uint8_t WChF_TempCoil_Stat_ro; // Bits= 8 Offset= -40 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + int16_t WChF_TempCoil_Stat_phys; +#endif // CANDB_USE_SIGFLOAT + + uint16_t WChF_FAN_RPM_Stat; // Bits=14 Unit:'rpm' + + // Availability of Bluetooth information + // 1 : "WChf has BT info" + // 0 : "WChF has no BT info" + uint8_t WChF_BT_Stat : 1; // Bits= 1 + + // Availability of WiFi information + // 1 : "WChF has WiFi info" + // 0 : "WChF has no WiFi info" + uint8_t WChF_WiFi_Stat : 1; // Bits= 1 + +#else + + // Work status on state on/off + // 1 : "On" + // 0 : "Off" + uint8_t WChF_Status_Stat; // Bits= 1 + + // Status charge on/off + // 1 : "On" + // 0 : "Off" + uint8_t WChF_Charge_Stat; // Bits= 1 + + // Supply chain short circuit + // 1 : "Failure" + // 0 : "No failure" + uint8_t WChF_ShortCircuit5V_Stat; // Bits= 1 + + // Communication error + // 1 : "Failure" + // 0 : "No failure" + uint8_t WChF_Comm_Stat; // Bits= 1 + + // Malfunction of the upper PCB with antenna, coil. + // 1 : "Failure" + // 0 : "No failure" + uint8_t WChF_Malfunction_Stat; // Bits= 1 + + // NFC device detection status + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Reserved" + // 4 : "Reserved" + // 3 : "Reserved" + // 2 : "NFC Smartphone detect" + // 1 : "NFC card detect" + // 0 : "No devices detect" + uint8_t WChF_NFCDevice_Stat; // Bits= 3 + + // Status about the current power QI of the current charge + uint8_t WChF_PowerQI_Stat_ro; // Bits= 8 Factor= 0.1 Unit:'W' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t WChF_PowerQI_Stat_phys; +#endif // CANDB_USE_SIGFLOAT + + // Status about current charging current + uint8_t WChF_CurrentTx_Stat_ro; // Bits= 8 Factor= 0.1 Unit:'A' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t WChF_CurrentTx_Stat_phys; +#endif // CANDB_USE_SIGFLOAT + + // Status about current frequency + // 255 : "Signal not available/failure" + uint8_t WChF_Frequency_Stat; // Bits= 8 Unit:'kHz' + + // Status about coil temperature + uint8_t WChF_TempCoil_Stat_ro; // Bits= 8 Offset= -40 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + int16_t WChF_TempCoil_Stat_phys; +#endif // CANDB_USE_SIGFLOAT + + uint16_t WChF_FAN_RPM_Stat; // Bits=14 Unit:'rpm' + + // Availability of Bluetooth information + // 1 : "WChf has BT info" + // 0 : "WChF has no BT info" + uint8_t WChF_BT_Stat; // Bits= 1 + + // Availability of WiFi information + // 1 : "WChF has WiFi info" + // 0 : "WChF has no WiFi info" + uint8_t WChF_WiFi_Stat; // Bits= 1 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} WChF_Status_t; + +// def @MAS_Status CAN Message (976 0x3d0) +#define MAS_Status_IDE (0U) +#define MAS_Status_DLC (8U) +#define MAS_Status_CANID (0x3d0U) +#define MAS_Status_CYC (100U) + +// Value tables for @MAS_AVMNarrowMode_Stat signal + +#ifndef MAS_AVMNarrowMode_Stat_MAS_Status_Narrow +#define MAS_AVMNarrowMode_Stat_MAS_Status_Narrow (2) +#endif + +#ifndef MAS_AVMNarrowMode_Stat_MAS_Status_Wide_full +#define MAS_AVMNarrowMode_Stat_MAS_Status_Wide_full (1) +#endif + +#ifndef MAS_AVMNarrowMode_Stat_MAS_Status_Nothing +#define MAS_AVMNarrowMode_Stat_MAS_Status_Nothing (0) +#endif + + +// Value tables for @MAS_AVMUltraSonic_Stat signal + +#ifndef MAS_AVMUltraSonic_Stat_MAS_Status_Active +#define MAS_AVMUltraSonic_Stat_MAS_Status_Active (1) +#endif + +#ifndef MAS_AVMUltraSonic_Stat_MAS_Status_Inactive +#define MAS_AVMUltraSonic_Stat_MAS_Status_Inactive (0) +#endif + + +// Value tables for @MAS_AVMCameraFront_Stat signal + +#ifndef MAS_AVMCameraFront_Stat_MAS_Status_Error +#define MAS_AVMCameraFront_Stat_MAS_Status_Error (1) +#endif + +#ifndef MAS_AVMCameraFront_Stat_MAS_Status_Not_Error +#define MAS_AVMCameraFront_Stat_MAS_Status_Not_Error (0) +#endif + + +// Value tables for @MAS_AVMCameraRear_Stat signal + +#ifndef MAS_AVMCameraRear_Stat_MAS_Status_Error +#define MAS_AVMCameraRear_Stat_MAS_Status_Error (1) +#endif + +#ifndef MAS_AVMCameraRear_Stat_MAS_Status_Not_Error +#define MAS_AVMCameraRear_Stat_MAS_Status_Not_Error (0) +#endif + + +// Value tables for @MAS_AVMCameraLeftSide_Stat signal + +#ifndef MAS_AVMCameraLeftSide_Stat_MAS_Status_Error +#define MAS_AVMCameraLeftSide_Stat_MAS_Status_Error (1) +#endif + +#ifndef MAS_AVMCameraLeftSide_Stat_MAS_Status_Not_Error +#define MAS_AVMCameraLeftSide_Stat_MAS_Status_Not_Error (0) +#endif + + +// Value tables for @MAS_AVMCameraRightSide_Stat signal + +#ifndef MAS_AVMCameraRightSide_Stat_MAS_Status_Error +#define MAS_AVMCameraRightSide_Stat_MAS_Status_Error (1) +#endif + +#ifndef MAS_AVMCameraRightSide_Stat_MAS_Status_Not_Error +#define MAS_AVMCameraRightSide_Stat_MAS_Status_Not_Error (0) +#endif + + +// Value tables for @MAS_View_Stat signal + +#ifndef MAS_View_Stat_MAS_Status_Parking_View +#define MAS_View_Stat_MAS_Status_Parking_View (7) +#endif + +#ifndef MAS_View_Stat_MAS_Status_D_Free_View_Rotation +#define MAS_View_Stat_MAS_Status_D_Free_View_Rotation (6) +#endif + +#ifndef MAS_View_Stat_MAS_Status_D_Right +#define MAS_View_Stat_MAS_Status_D_Right (5) +#endif + +#ifndef MAS_View_Stat_MAS_Status_D_Left +#define MAS_View_Stat_MAS_Status_D_Left (4) +#endif + +#ifndef MAS_View_Stat_MAS_Status_D_Main_Rear_Top_View +#define MAS_View_Stat_MAS_Status_D_Main_Rear_Top_View (3) +#endif + +#ifndef MAS_View_Stat_MAS_Status_D_Rear +#define MAS_View_Stat_MAS_Status_D_Rear (2) +#endif + +#ifndef MAS_View_Stat_MAS_Status_D_Front +#define MAS_View_Stat_MAS_Status_D_Front (1) +#endif + +#ifndef MAS_View_Stat_MAS_Status_Nothing +#define MAS_View_Stat_MAS_Status_Nothing (0) +#endif + + +// Value tables for @MAS_Calibration_Stat signal + +#ifndef MAS_Calibration_Stat_MAS_Status_Calibration_started +#define MAS_Calibration_Stat_MAS_Status_Calibration_started (1) +#endif + +#ifndef MAS_Calibration_Stat_MAS_Status_Calibration_not_started +#define MAS_Calibration_Stat_MAS_Status_Calibration_not_started (0) +#endif + + +// Value tables for @MAS_AVMUltrasonicFront_Stat signal + +#ifndef MAS_AVMUltrasonicFront_Stat_MAS_Status_Sensor_error +#define MAS_AVMUltrasonicFront_Stat_MAS_Status_Sensor_error (2) +#endif + +#ifndef MAS_AVMUltrasonicFront_Stat_MAS_Status_Dirt_or_blocked +#define MAS_AVMUltrasonicFront_Stat_MAS_Status_Dirt_or_blocked (1) +#endif + +#ifndef MAS_AVMUltrasonicFront_Stat_MAS_Status_Available +#define MAS_AVMUltrasonicFront_Stat_MAS_Status_Available (0) +#endif + + +// Value tables for @MAS_AVMUltrasonicRear_Stat signal + +#ifndef MAS_AVMUltrasonicRear_Stat_MAS_Status_Sensor_error +#define MAS_AVMUltrasonicRear_Stat_MAS_Status_Sensor_error (2) +#endif + +#ifndef MAS_AVMUltrasonicRear_Stat_MAS_Status_Dirt_or_blocked +#define MAS_AVMUltrasonicRear_Stat_MAS_Status_Dirt_or_blocked (1) +#endif + +#ifndef MAS_AVMUltrasonicRear_Stat_MAS_Status_Available +#define MAS_AVMUltrasonicRear_Stat_MAS_Status_Available (0) +#endif + + +// Value tables for @MAS_AVMUltrasonicSide_Stat signal + +#ifndef MAS_AVMUltrasonicSide_Stat_MAS_Status_Sensor_error +#define MAS_AVMUltrasonicSide_Stat_MAS_Status_Sensor_error (2) +#endif + +#ifndef MAS_AVMUltrasonicSide_Stat_MAS_Status_Dirt_or_blocked +#define MAS_AVMUltrasonicSide_Stat_MAS_Status_Dirt_or_blocked (1) +#endif + +#ifndef MAS_AVMUltrasonicSide_Stat_MAS_Status_Available +#define MAS_AVMUltrasonicSide_Stat_MAS_Status_Available (0) +#endif + + +// Value tables for @MAS_MASmode_Stat signal + +#ifndef MAS_MASmode_Stat_MAS_Status_Error +#define MAS_MASmode_Stat_MAS_Status_Error (4) +#endif + +#ifndef MAS_MASmode_Stat_MAS_Status_Not_avaliable +#define MAS_MASmode_Stat_MAS_Status_Not_avaliable (3) +#endif + +#ifndef MAS_MASmode_Stat_MAS_Status_APA +#define MAS_MASmode_Stat_MAS_Status_APA (2) +#endif + +#ifndef MAS_MASmode_Stat_MAS_Status_AVM +#define MAS_MASmode_Stat_MAS_Status_AVM (1) +#endif + +#ifndef MAS_MASmode_Stat_MAS_Status_MAS_not_requested +#define MAS_MASmode_Stat_MAS_Status_MAS_not_requested (0) +#endif + + +// Value tables for @MAS_APAMode_Stat signal + +#ifndef MAS_APAMode_Stat_MAS_Status_APA_is_not_active +#define MAS_APAMode_Stat_MAS_Status_APA_is_not_active (0) +#endif + +#ifndef MAS_APAMode_Stat_MAS_Status_Init +#define MAS_APAMode_Stat_MAS_Status_Init (1) +#endif + +#ifndef MAS_APAMode_Stat_MAS_Status_Search +#define MAS_APAMode_Stat_MAS_Status_Search (2) +#endif + +#ifndef MAS_APAMode_Stat_MAS_Status_Search_paused +#define MAS_APAMode_Stat_MAS_Status_Search_paused (3) +#endif + +#ifndef MAS_APAMode_Stat_MAS_Status_Select +#define MAS_APAMode_Stat_MAS_Status_Select (4) +#endif + +#ifndef MAS_APAMode_Stat_MAS_Status_Move +#define MAS_APAMode_Stat_MAS_Status_Move (5) +#endif + +#ifndef MAS_APAMode_Stat_MAS_Status_Move_paused +#define MAS_APAMode_Stat_MAS_Status_Move_paused (6) +#endif + +#ifndef MAS_APAMode_Stat_MAS_Status_Fatal_Error +#define MAS_APAMode_Stat_MAS_Status_Fatal_Error (7) +#endif + + +// Value tables for @MAS_AVMAutoAct_Stat signal + +#ifndef MAS_AVMAutoAct_Stat_MAS_Status_Automatic_activation_OFF +#define MAS_AVMAutoAct_Stat_MAS_Status_Automatic_activation_OFF (1) +#endif + +#ifndef MAS_AVMAutoAct_Stat_MAS_Status_Automatic_activation_ON +#define MAS_AVMAutoAct_Stat_MAS_Status_Automatic_activation_ON (0) +#endif + + +// Value tables for @MAS_APAManeuverSuccess_Stat signal + +#ifndef MAS_APAManeuverSuccess_Stat_MAS_Status_Not_started_or_not_success +#define MAS_APAManeuverSuccess_Stat_MAS_Status_Not_started_or_not_success (0) +#endif + +#ifndef MAS_APAManeuverSuccess_Stat_MAS_Status_Success +#define MAS_APAManeuverSuccess_Stat_MAS_Status_Success (1) +#endif + + +// Value tables for @MAS_ParkingOutAvailable_Stat signal + +#ifndef MAS_ParkingOutAvailable_Stat_MAS_Status_AutoParkOut_not_available +#define MAS_ParkingOutAvailable_Stat_MAS_Status_AutoParkOut_not_available (0) +#endif + +#ifndef MAS_ParkingOutAvailable_Stat_MAS_Status_AutoParkOut_is_available +#define MAS_ParkingOutAvailable_Stat_MAS_Status_AutoParkOut_is_available (1) +#endif + + +// Value tables for @MAS_ParkingOutSuccess_Stat signal + +#ifndef MAS_ParkingOutSuccess_Stat_MAS_Status_Parking_Out_is_not_executed +#define MAS_ParkingOutSuccess_Stat_MAS_Status_Parking_Out_is_not_executed (0) +#endif + +#ifndef MAS_ParkingOutSuccess_Stat_MAS_Status_Parking_Out_is_Successful +#define MAS_ParkingOutSuccess_Stat_MAS_Status_Parking_Out_is_Successful (1) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // 0 - AVM is not in 2D mode + // 1 - AVM is in wide mode, i.e. shows only the image from the camera in 2D View + // 2 - AVM shows the image from the camera + Top view + // 2 : "Narrow" + // 1 : "Wide (full)" + // 0 : "Nothing" + uint8_t MAS_AVMNarrowMode_Stat : 2; // Bits= 2 + + // 0 -MAS is not activated by parking sensors, does not show the distance to objects, and does not transmit sound to the DSP. + // 1 : "Active" + // 0 : "Inactive" + uint8_t MAS_AVMUltraSonic_Stat : 1; // Bits= 1 + + // FIU should show information that the camera is not available. + // 1 : "Error" + // 0 : "Not Error" + uint8_t MAS_AVMCameraFront_Stat : 1; // Bits= 1 + + // FIU should show information that the camera is not available. + // 1 : "Error" + // 0 : "Not Error" + uint8_t MAS_AVMCameraRear_Stat : 1; // Bits= 1 + + // FIU should show information that the camera is not available. + // 1 : "Error" + // 0 : "Not Error" + uint8_t MAS_AVMCameraLeftSide_Stat : 1; // Bits= 1 + + // FIU should show information that the camera is not available. + // 1 : "Error" + // 0 : "Not Error" + uint8_t MAS_AVMCameraRightSide_Stat : 1; // Bits= 1 + + // On this signal, FIU will understand which view mode to make active + // 7 : "Parking View" + // 6 : "3D Free View (Rotation)" + // 5 : "3D Right" + // 4 : "3D Left" + // 3 : "3D Main (Rear Top View)" + // 2 : "2D Rear" + // 1 : "2D Front" + // 0 : "Nothing" + uint8_t MAS_View_Stat : 3; // Bits= 3 + + // 1 : "Calibration started" + // 0 : "Calibration not started" + uint8_t MAS_Calibration_Stat : 1; // Bits= 1 + + // The FIU must show the user that the information from the front parking sensors cannot be trusted. + // 2 : "Sensor error" + // 1 : "Dirt or blocked" + // 0 : "Available" + uint8_t MAS_AVMUltrasonicFront_Stat : 2; // Bits= 2 + + // The FIU must show the user that the information from the front parking sensors cannot be trusted. + // 2 : "Sensor error" + // 1 : "Dirt or blocked" + // 0 : "Available" + uint8_t MAS_AVMUltrasonicRear_Stat : 2; // Bits= 2 + + // The FIU must show the user that the information from the side parking sensors cannot be trusted. + // 2 : "Sensor error" + // 1 : "Dirt or blocked" + // 0 : "Available" + uint8_t MAS_AVMUltrasonicSide_Stat : 2; // Bits= 2 + + // Current mode + // 0x0 - MAS func (AVM, APA) not active + // 0x1- MAS in AVM mode (Souround view + USS) + // 0x2 - MAS in APA mode (Autopark/Remote autopark) + // 0x3 - MAS resp on req from FIU or BCM with vehspeed >15 km/h (active for 3 frames) + // 0x4 - MAS system in Error + // 4 : "Error" + // 3 : "Not avaliable" + // 2 : "APA" + // 1 : "AVM" + // 0 : "MAS not requested" + uint8_t MAS_MASmode_Stat : 3; // Bits= 3 + + // Current APA mode + // 0 : "APA is not active" + // 1 : "Init" + // 2 : "Search" + // 3 : "Search paused" + // 4 : "Select" + // 5 : "Move" + // 6 : "Move paused" + // 7 : "Fatal Error" + uint8_t MAS_APAMode_Stat : 3; // Bits= 3 + + // Automatic activation set less than 15 km/h + // 1 : "Automatic activation OFF" + // 0 : "Automatic activation ON" + uint8_t MAS_AVMAutoAct_Stat : 1; // Bits= 1 + + // 0x0 (APA did not execute a parking maneuver successfully OR the parking maneuver was not started) 0x1 (APA executed a parking maneuver successfully) + // 0 : "Not started or not success" + // 1 : "Success" + uint8_t MAS_APAManeuverSuccess_Stat : 1; // Bits= 1 + + // Avaluablity of automatic parking out + // 0 : "AutoParkOut not available" + // 1 : "AutoParkOut is available" + uint8_t MAS_ParkingOutAvailable_Stat : 1; // Bits= 1 + + // Successful execution status of Parking Out + // 0 : "Parking Out is not executed" + // 1 : "Parking Out is Successful" + uint8_t MAS_ParkingOutSuccess_Stat : 1; // Bits= 1 + + // Rolling Counter [0 - 15] + uint8_t MAS_Status_RC : 4; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t MAS_Status_CS; // Bits= 8 + +#else + + // 0 - AVM is not in 2D mode + // 1 - AVM is in wide mode, i.e. shows only the image from the camera in 2D View + // 2 - AVM shows the image from the camera + Top view + // 2 : "Narrow" + // 1 : "Wide (full)" + // 0 : "Nothing" + uint8_t MAS_AVMNarrowMode_Stat; // Bits= 2 + + // 0 -MAS is not activated by parking sensors, does not show the distance to objects, and does not transmit sound to the DSP. + // 1 : "Active" + // 0 : "Inactive" + uint8_t MAS_AVMUltraSonic_Stat; // Bits= 1 + + // FIU should show information that the camera is not available. + // 1 : "Error" + // 0 : "Not Error" + uint8_t MAS_AVMCameraFront_Stat; // Bits= 1 + + // FIU should show information that the camera is not available. + // 1 : "Error" + // 0 : "Not Error" + uint8_t MAS_AVMCameraRear_Stat; // Bits= 1 + + // FIU should show information that the camera is not available. + // 1 : "Error" + // 0 : "Not Error" + uint8_t MAS_AVMCameraLeftSide_Stat; // Bits= 1 + + // FIU should show information that the camera is not available. + // 1 : "Error" + // 0 : "Not Error" + uint8_t MAS_AVMCameraRightSide_Stat; // Bits= 1 + + // On this signal, FIU will understand which view mode to make active + // 7 : "Parking View" + // 6 : "3D Free View (Rotation)" + // 5 : "3D Right" + // 4 : "3D Left" + // 3 : "3D Main (Rear Top View)" + // 2 : "2D Rear" + // 1 : "2D Front" + // 0 : "Nothing" + uint8_t MAS_View_Stat; // Bits= 3 + + // 1 : "Calibration started" + // 0 : "Calibration not started" + uint8_t MAS_Calibration_Stat; // Bits= 1 + + // The FIU must show the user that the information from the front parking sensors cannot be trusted. + // 2 : "Sensor error" + // 1 : "Dirt or blocked" + // 0 : "Available" + uint8_t MAS_AVMUltrasonicFront_Stat; // Bits= 2 + + // The FIU must show the user that the information from the front parking sensors cannot be trusted. + // 2 : "Sensor error" + // 1 : "Dirt or blocked" + // 0 : "Available" + uint8_t MAS_AVMUltrasonicRear_Stat; // Bits= 2 + + // The FIU must show the user that the information from the side parking sensors cannot be trusted. + // 2 : "Sensor error" + // 1 : "Dirt or blocked" + // 0 : "Available" + uint8_t MAS_AVMUltrasonicSide_Stat; // Bits= 2 + + // Current mode + // 0x0 - MAS func (AVM, APA) not active + // 0x1- MAS in AVM mode (Souround view + USS) + // 0x2 - MAS in APA mode (Autopark/Remote autopark) + // 0x3 - MAS resp on req from FIU or BCM with vehspeed >15 km/h (active for 3 frames) + // 0x4 - MAS system in Error + // 4 : "Error" + // 3 : "Not avaliable" + // 2 : "APA" + // 1 : "AVM" + // 0 : "MAS not requested" + uint8_t MAS_MASmode_Stat; // Bits= 3 + + // Current APA mode + // 0 : "APA is not active" + // 1 : "Init" + // 2 : "Search" + // 3 : "Search paused" + // 4 : "Select" + // 5 : "Move" + // 6 : "Move paused" + // 7 : "Fatal Error" + uint8_t MAS_APAMode_Stat; // Bits= 3 + + // Automatic activation set less than 15 km/h + // 1 : "Automatic activation OFF" + // 0 : "Automatic activation ON" + uint8_t MAS_AVMAutoAct_Stat; // Bits= 1 + + // 0x0 (APA did not execute a parking maneuver successfully OR the parking maneuver was not started) 0x1 (APA executed a parking maneuver successfully) + // 0 : "Not started or not success" + // 1 : "Success" + uint8_t MAS_APAManeuverSuccess_Stat; // Bits= 1 + + // Avaluablity of automatic parking out + // 0 : "AutoParkOut not available" + // 1 : "AutoParkOut is available" + uint8_t MAS_ParkingOutAvailable_Stat; // Bits= 1 + + // Successful execution status of Parking Out + // 0 : "Parking Out is not executed" + // 1 : "Parking Out is Successful" + uint8_t MAS_ParkingOutSuccess_Stat; // Bits= 1 + + // Rolling Counter [0 - 15] + uint8_t MAS_Status_RC; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t MAS_Status_CS; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} MAS_Status_t; + +// AVH function request +// def @EPB_VM_MSG CAN Message (1059 0x423) +#define EPB_VM_MSG_IDE (0U) +#define EPB_VM_MSG_DLC (8U) +#define EPB_VM_MSG_CANID (0x423U) +#define EPB_VM_MSG_CYC (100U) + +// Value tables for @EPB_OpMode_Req signal + +#ifndef EPB_OpMode_Req_EPB_VM_MSG_Manual_mode +#define EPB_OpMode_Req_EPB_VM_MSG_Manual_mode (1) +#endif + +#ifndef EPB_OpMode_Req_EPB_VM_MSG_Full_mode +#define EPB_OpMode_Req_EPB_VM_MSG_Full_mode (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // AVH function request + // 1 : "Manual mode" + // 0 : "Full mode" + uint8_t EPB_OpMode_Req : 1; // Bits= 1 + + // Rolling Counter [0 - 15] + uint8_t EPB_VM_RC : 4; // Bits= 4 + + // Checksum XOR8 of the data field this message + // Checksum computed as per XOR algorithm: + // Byte 1 XOR byte 2 .... XOR byte n-1. (n = packet length.) + uint8_t EPB_VM_CS; // Bits= 8 + +#else + + // AVH function request + // 1 : "Manual mode" + // 0 : "Full mode" + uint8_t EPB_OpMode_Req; // Bits= 1 + + // Rolling Counter [0 - 15] + uint8_t EPB_VM_RC; // Bits= 4 + + // Checksum XOR8 of the data field this message + // Checksum computed as per XOR algorithm: + // Byte 1 XOR byte 2 .... XOR byte n-1. (n = packet length.) + uint8_t EPB_VM_CS; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} EPB_VM_MSG_t; + +// def @CGW_COMM_REQ CAN Message (1173 0x495) +#define CGW_COMM_REQ_IDE (0U) +#define CGW_COMM_REQ_DLC (1U) +#define CGW_COMM_REQ_CANID (0x495U) +#define CGW_COMM_REQ_CYC (500U) + +// Value tables for @CGW_Comm_Req signal + +#ifndef CGW_Comm_Req_CGW_COMM_REQ_True +#define CGW_Comm_Req_CGW_COMM_REQ_True (1) +#endif + +#ifndef CGW_Comm_Req_CGW_COMM_REQ_False +#define CGW_Comm_Req_CGW_COMM_REQ_False (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Request communication to EMS + // 1 : "True" + // 0 : "False" + uint8_t CGW_Comm_Req : 1; // Bits= 1 + +#else + + // Request communication to EMS + // 1 : "True" + // 0 : "False" + uint8_t CGW_Comm_Req; // Bits= 1 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} CGW_COMM_REQ_t; + +// def @DCDC1248_01 CAN Message (1199 0x4af) +#define DCDC1248_01_IDE (0U) +#define DCDC1248_01_DLC (6U) +#define DCDC1248_01_CANID (0x4afU) +#define DCDC1248_01_CYC (10U) + +// Value tables for @DCDC1248_ActMode_Stat signal + +#ifndef DCDC1248_ActMode_Stat_DCDC1248_01_DCDC1248_Warning +#define DCDC1248_ActMode_Stat_DCDC1248_01_DCDC1248_Warning (3) +#endif + +#ifndef DCDC1248_ActMode_Stat_DCDC1248_01_DCDC1248_Error +#define DCDC1248_ActMode_Stat_DCDC1248_01_DCDC1248_Error (7) +#endif + +#ifndef DCDC1248_ActMode_Stat_DCDC1248_01_ACT12_48 +#define DCDC1248_ActMode_Stat_DCDC1248_01_ACT12_48 (2) +#endif + +#ifndef DCDC1248_ActMode_Stat_DCDC1248_01_ACT48_12 +#define DCDC1248_ActMode_Stat_DCDC1248_01_ACT48_12 (1) +#endif + +#ifndef DCDC1248_ActMode_Stat_DCDC1248_01_Standby +#define DCDC1248_ActMode_Stat_DCDC1248_01_Standby (0) +#endif + + +// Value tables for @DCDC1248_Warn_Stat signal + +#ifndef DCDC1248_Warn_Stat_DCDC1248_01_On +#define DCDC1248_Warn_Stat_DCDC1248_01_On (1) +#endif + +#ifndef DCDC1248_Warn_Stat_DCDC1248_01_Off +#define DCDC1248_Warn_Stat_DCDC1248_01_Off (0) +#endif + +// signal: @DCDC1248_ActCurr12_Val_ro +#define CANDB_DCDC1248_ActCurr12_Val_ro_CovFactor (1) +#define CANDB_DCDC1248_ActCurr12_Val_ro_toS(x) ( (uint16_t) ((x) - (-255)) ) +#define CANDB_DCDC1248_ActCurr12_Val_ro_fromS(x) ( ((x) + (-255)) ) +// signal: @DCDC1248_ActVolt12_Val_ro +#define CANDB_DCDC1248_ActVolt12_Val_ro_CovFactor (0.1) +#define CANDB_DCDC1248_ActVolt12_Val_ro_toS(x) ( (uint16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DCDC1248_ActVolt12_Val_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +// Value tables for @DCDC1248_ErrInternal_Stat signal + +#ifndef DCDC1248_ErrInternal_Stat_DCDC1248_01_On +#define DCDC1248_ErrInternal_Stat_DCDC1248_01_On (1) +#endif + +#ifndef DCDC1248_ErrInternal_Stat_DCDC1248_01_Off +#define DCDC1248_ErrInternal_Stat_DCDC1248_01_Off (0) +#endif + + +// Value tables for @DCDC1248_DisChrg_Stat signal + +#ifndef DCDC1248_DisChrg_Stat_DCDC1248_01_Error +#define DCDC1248_DisChrg_Stat_DCDC1248_01_Error (3) +#endif + +#ifndef DCDC1248_DisChrg_Stat_DCDC1248_01_On +#define DCDC1248_DisChrg_Stat_DCDC1248_01_On (1) +#endif + +#ifndef DCDC1248_DisChrg_Stat_DCDC1248_01_Off +#define DCDC1248_DisChrg_Stat_DCDC1248_01_Off (0) +#endif + +// signal: @DCDC1248_MaxCurr12_Val_ro +#define CANDB_DCDC1248_MaxCurr12_Val_ro_CovFactor (0.4) +#define CANDB_DCDC1248_MaxCurr12_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.4)) ) +#define CANDB_DCDC1248_MaxCurr12_Val_ro_fromS(x) ( (((x) * (0.4)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Checksum XOR8 of the data field this message + // Checksum computed as per XOR algorithm: + // Byte 1 XOR byte 2 .... XOR byte n-1. (n = packet length.) + uint8_t DCDC1248_01_CS; // Bits= 8 + + // Rolling Counter [0 - 15] + uint8_t DCDC1248_01_RC : 4; // Bits= 4 + + // 3 : "DCDC1248_Warning" + // 7 : "DCDC1248_Error" + // 2 : "ACT12_48" + // 1 : "ACT48_12" + // 0 : "Standby" + uint8_t DCDC1248_ActMode_Stat : 3; // Bits= 3 + + // 1 : "On" + // 0 : "Off" + uint8_t DCDC1248_Warn_Stat : 1; // Bits= 1 + + uint16_t DCDC1248_ActCurr12_Val_ro; // Bits= 9 Offset= -255 Unit:'A' + +#ifdef CANDB_USE_SIGFLOAT + int16_t DCDC1248_ActCurr12_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + uint16_t DCDC1248_ActVolt12_Val_ro; // Bits=10 Factor= 0.1 Unit:'V' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t DCDC1248_ActVolt12_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // 1 : "On" + // 0 : "Off" + uint8_t DCDC1248_ErrInternal_Stat : 1; // Bits= 1 + + uint8_t DCDC1248_OvCurr12 : 1; // Bits= 1 + + // Disable charging status + // 3 : "Error" + // 1 : "On" + // 0 : "Off" + uint8_t DCDC1248_DisChrg_Stat : 2; // Bits= 2 + + int8_t DCDC1248_T15_Stat : 1; // [-] Bits= 1 + + uint8_t DCDC1248_MaxCurr12_Val_ro; // Bits= 8 Factor= 0.4 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t DCDC1248_MaxCurr12_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#else + + // Checksum XOR8 of the data field this message + // Checksum computed as per XOR algorithm: + // Byte 1 XOR byte 2 .... XOR byte n-1. (n = packet length.) + uint8_t DCDC1248_01_CS; // Bits= 8 + + // Rolling Counter [0 - 15] + uint8_t DCDC1248_01_RC; // Bits= 4 + + // 3 : "DCDC1248_Warning" + // 7 : "DCDC1248_Error" + // 2 : "ACT12_48" + // 1 : "ACT48_12" + // 0 : "Standby" + uint8_t DCDC1248_ActMode_Stat; // Bits= 3 + + // 1 : "On" + // 0 : "Off" + uint8_t DCDC1248_Warn_Stat; // Bits= 1 + + uint16_t DCDC1248_ActCurr12_Val_ro; // Bits= 9 Offset= -255 Unit:'A' + +#ifdef CANDB_USE_SIGFLOAT + int16_t DCDC1248_ActCurr12_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + uint16_t DCDC1248_ActVolt12_Val_ro; // Bits=10 Factor= 0.1 Unit:'V' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t DCDC1248_ActVolt12_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // 1 : "On" + // 0 : "Off" + uint8_t DCDC1248_ErrInternal_Stat; // Bits= 1 + + uint8_t DCDC1248_OvCurr12; // Bits= 1 + + // Disable charging status + // 3 : "Error" + // 1 : "On" + // 0 : "Off" + uint8_t DCDC1248_DisChrg_Stat; // Bits= 2 + + int8_t DCDC1248_T15_Stat; // [-] Bits= 1 + + uint8_t DCDC1248_MaxCurr12_Val_ro; // Bits= 8 Factor= 0.4 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t DCDC1248_MaxCurr12_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} DCDC1248_01_t; + +// def @FIU_REQ_CTR_01 CAN Message (1200 0x4b0) +#define FIU_REQ_CTR_01_IDE (0U) +#define FIU_REQ_CTR_01_DLC (8U) +#define FIU_REQ_CTR_01_CANID (0x4b0U) + +// Value tables for @FIU_SetLanguage signal + +#ifndef FIU_SetLanguage_FIU_REQ_CTR_01_Chinese +#define FIU_SetLanguage_FIU_REQ_CTR_01_Chinese (3) +#endif + +#ifndef FIU_SetLanguage_FIU_REQ_CTR_01_Arabic +#define FIU_SetLanguage_FIU_REQ_CTR_01_Arabic (2) +#endif + +#ifndef FIU_SetLanguage_FIU_REQ_CTR_01_Russia +#define FIU_SetLanguage_FIU_REQ_CTR_01_Russia (1) +#endif + +#ifndef FIU_SetLanguage_FIU_REQ_CTR_01_English +#define FIU_SetLanguage_FIU_REQ_CTR_01_English (0) +#endif + + +// Value tables for @FIU_VoiceControlActive_Stat signal + +#ifndef FIU_VoiceControlActive_Stat_FIU_REQ_CTR_01_Active +#define FIU_VoiceControlActive_Stat_FIU_REQ_CTR_01_Active (1) +#endif + +#ifndef FIU_VoiceControlActive_Stat_FIU_REQ_CTR_01_Inactive +#define FIU_VoiceControlActive_Stat_FIU_REQ_CTR_01_Inactive (0) +#endif + + +// Value tables for @FIU_SERVICE_State signal + +#ifndef FIU_SERVICE_State_FIU_REQ_CTR_01_Pressed +#define FIU_SERVICE_State_FIU_REQ_CTR_01_Pressed (1) +#endif + +#ifndef FIU_SERVICE_State_FIU_REQ_CTR_01_Not_Pressed +#define FIU_SERVICE_State_FIU_REQ_CTR_01_Not_Pressed (0) +#endif + + +// Value tables for @FIU_SOS_State signal + +#ifndef FIU_SOS_State_FIU_REQ_CTR_01_Pressed +#define FIU_SOS_State_FIU_REQ_CTR_01_Pressed (1) +#endif + +#ifndef FIU_SOS_State_FIU_REQ_CTR_01_Not_Pressed +#define FIU_SOS_State_FIU_REQ_CTR_01_Not_Pressed (0) +#endif + + +// Value tables for @FIU_FuelStatisticsReset_Req signal + +#ifndef FIU_FuelStatisticsReset_Req_FIU_REQ_CTR_01_Button_pressed +#define FIU_FuelStatisticsReset_Req_FIU_REQ_CTR_01_Button_pressed (1) +#endif + +#ifndef FIU_FuelStatisticsReset_Req_FIU_REQ_CTR_01_Not_Pressed +#define FIU_FuelStatisticsReset_Req_FIU_REQ_CTR_01_Not_Pressed (0) +#endif + + +// Value tables for @FIU_UserTripStatisticsReset_Req signal + +#ifndef FIU_UserTripStatisticsReset_Req_FIU_REQ_CTR_01_Button_pressed +#define FIU_UserTripStatisticsReset_Req_FIU_REQ_CTR_01_Button_pressed (1) +#endif + +#ifndef FIU_UserTripStatisticsReset_Req_FIU_REQ_CTR_01_Not_Pressed +#define FIU_UserTripStatisticsReset_Req_FIU_REQ_CTR_01_Not_Pressed (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Requesst the language to be used by IC + // $0 = Russian + // $1 = English + // 3 : "Chinese" + // 2 : "Arabic" + // 1 : "Russia" + // 0 : "English" + uint8_t FIU_SetLanguage : 3; // Bits= 3 + + // Indicates the status of the voice control: + // $0 = Inactive + // $1 = Active + // 1 : "Active" + // 0 : "Inactive + + uint8_t FIU_VoiceControlActive_Stat : 1; // Bits= 1 + + // Indicates the SERVICE button state: + // 0x0 = Button Not Pressed + // 0x1 = Button Pressed + // 1 : "Pressed" + // 0 : "Not Pressed" + uint8_t FIU_SERVICE_State : 1; // Bits= 1 + + // Indicates the SOS button state: + // 0x0 = Button Not Pressed + // 0x1 = Button Pressed + // 1 : "Pressed" + // 0 : "Not Pressed" + uint8_t FIU_SOS_State : 1; // Bits= 1 + + // Reset Fuel statistics: + // 0x0 = Nothing shall happens + // 0x1 = Fuel statistics shall be reset + // 1 : "Button pressed" + // 0 : "Not Pressed" + uint8_t FIU_FuelStatisticsReset_Req : 1; // Bits= 1 + + // Reset User trip statistics: + // 0x0 = Nothing shall happens + // 0x1 = Uset trip statistics shall be reset + // 1 : "Button pressed" + // 0 : "Not Pressed" + uint8_t FIU_UserTripStatisticsReset_Req : 1; // Bits= 1 + +#else + + // Requesst the language to be used by IC + // $0 = Russian + // $1 = English + // 3 : "Chinese" + // 2 : "Arabic" + // 1 : "Russia" + // 0 : "English" + uint8_t FIU_SetLanguage; // Bits= 3 + + // Indicates the status of the voice control: + // $0 = Inactive + // $1 = Active + // 1 : "Active" + // 0 : "Inactive + + uint8_t FIU_VoiceControlActive_Stat; // Bits= 1 + + // Indicates the SERVICE button state: + // 0x0 = Button Not Pressed + // 0x1 = Button Pressed + // 1 : "Pressed" + // 0 : "Not Pressed" + uint8_t FIU_SERVICE_State; // Bits= 1 + + // Indicates the SOS button state: + // 0x0 = Button Not Pressed + // 0x1 = Button Pressed + // 1 : "Pressed" + // 0 : "Not Pressed" + uint8_t FIU_SOS_State; // Bits= 1 + + // Reset Fuel statistics: + // 0x0 = Nothing shall happens + // 0x1 = Fuel statistics shall be reset + // 1 : "Button pressed" + // 0 : "Not Pressed" + uint8_t FIU_FuelStatisticsReset_Req; // Bits= 1 + + // Reset User trip statistics: + // 0x0 = Nothing shall happens + // 0x1 = Uset trip statistics shall be reset + // 1 : "Button pressed" + // 0 : "Not Pressed" + uint8_t FIU_UserTripStatisticsReset_Req; // Bits= 1 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} FIU_REQ_CTR_01_t; + +// def @DCDC1248_02 CAN Message (1201 0x4b1) +#define DCDC1248_02_IDE (0U) +#define DCDC1248_02_DLC (7U) +#define DCDC1248_02_CANID (0x4b1U) +#define DCDC1248_02_CYC (10U) +// signal: @DCDC1248_ActVolt48_Val_ro +#define CANDB_DCDC1248_ActVolt48_Val_ro_CovFactor (0.1) +#define CANDB_DCDC1248_ActVolt48_Val_ro_toS(x) ( (uint16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_DCDC1248_ActVolt48_Val_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @DCDC1248_ActCurr48_Val_ro +#define CANDB_DCDC1248_ActCurr48_Val_ro_CovFactor (1) +#define CANDB_DCDC1248_ActCurr48_Val_ro_toS(x) ( (uint16_t) ((x) - (-255)) ) +#define CANDB_DCDC1248_ActCurr48_Val_ro_fromS(x) ( ((x) + (-255)) ) +// signal: @DCDC1248_ActTemp_Val_ro +#define CANDB_DCDC1248_ActTemp_Val_ro_CovFactor (1) +#define CANDB_DCDC1248_ActTemp_Val_ro_toS(x) ( (uint8_t) ((x) - (-40)) ) +#define CANDB_DCDC1248_ActTemp_Val_ro_fromS(x) ( ((x) + (-40)) ) + +// Value tables for @DCDC1248_ActDisChrg_Stat signal + +#ifndef DCDC1248_ActDisChrg_Stat_DCDC1248_02_Complete_discharge +#define DCDC1248_ActDisChrg_Stat_DCDC1248_02_Complete_discharge (2) +#endif + +#ifndef DCDC1248_ActDisChrg_Stat_DCDC1248_02_Active_discharge +#define DCDC1248_ActDisChrg_Stat_DCDC1248_02_Active_discharge (1) +#endif + +#ifndef DCDC1248_ActDisChrg_Stat_DCDC1248_02_Stand_by +#define DCDC1248_ActDisChrg_Stat_DCDC1248_02_Stand_by (0) +#endif + +// signal: @DCDC1248_MaxCurr48_Val_ro +#define CANDB_DCDC1248_MaxCurr48_Val_ro_CovFactor (0.4) +#define CANDB_DCDC1248_MaxCurr48_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.4)) ) +#define CANDB_DCDC1248_MaxCurr48_Val_ro_fromS(x) ( (((x) * (0.4)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Checksum XOR8 of the data field this message + // Checksum computed as per XOR algorithm: + // Byte 1 XOR byte 2 .... XOR byte n-1. (n = packet length.) + uint8_t DCDC1248_02_CS; // Bits= 8 + + // Rolling Counter [0 - 15] + uint8_t DCDC1248_02_RC : 4; // Bits= 4 + + uint16_t DCDC1248_ActVolt48_Val_ro; // Bits=10 Factor= 0.1 Unit:'V' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t DCDC1248_ActVolt48_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + uint16_t DCDC1248_ActCurr48_Val_ro; // Bits=10 Offset= -255 Unit:'A' + +#ifdef CANDB_USE_SIGFLOAT + int16_t DCDC1248_ActCurr48_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + uint8_t DCDC1248_ActTemp_Val_ro; // Bits= 8 Offset= -40 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + int16_t DCDC1248_ActTemp_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // 2 : "Complete discharge" + // 1 : "Active discharge" + // 0 : "Stand by" + uint8_t DCDC1248_ActDisChrg_Stat : 2; // Bits= 2 + + uint8_t DCDC1248_MaxCurr48_Val_ro; // Bits= 8 Factor= 0.4 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t DCDC1248_MaxCurr48_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#else + + // Checksum XOR8 of the data field this message + // Checksum computed as per XOR algorithm: + // Byte 1 XOR byte 2 .... XOR byte n-1. (n = packet length.) + uint8_t DCDC1248_02_CS; // Bits= 8 + + // Rolling Counter [0 - 15] + uint8_t DCDC1248_02_RC; // Bits= 4 + + uint16_t DCDC1248_ActVolt48_Val_ro; // Bits=10 Factor= 0.1 Unit:'V' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t DCDC1248_ActVolt48_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + uint16_t DCDC1248_ActCurr48_Val_ro; // Bits=10 Offset= -255 Unit:'A' + +#ifdef CANDB_USE_SIGFLOAT + int16_t DCDC1248_ActCurr48_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + uint8_t DCDC1248_ActTemp_Val_ro; // Bits= 8 Offset= -40 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + int16_t DCDC1248_ActTemp_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // 2 : "Complete discharge" + // 1 : "Active discharge" + // 0 : "Stand by" + uint8_t DCDC1248_ActDisChrg_Stat; // Bits= 2 + + uint8_t DCDC1248_MaxCurr48_Val_ro; // Bits= 8 Factor= 0.4 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t DCDC1248_MaxCurr48_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} DCDC1248_02_t; + +// def @FIU_Access_Msg2 CAN Message (1205 0x4b5) +#define FIU_Access_Msg2_IDE (0U) +#define FIU_Access_Msg2_DLC (4U) +#define FIU_Access_Msg2_CANID (0x4b5U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Smartphone access key + uint32_t FIU_Smartphone_Key; // Bits=32 + +#else + + // Smartphone access key + uint32_t FIU_Smartphone_Key; // Bits=32 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} FIU_Access_Msg2_t; + +// def @FIU_Profile CAN Message (1206 0x4b6) +#define FIU_Profile_IDE (0U) +#define FIU_Profile_DLC (3U) +#define FIU_Profile_CANID (0x4b6U) +#define FIU_Profile_CYC (250U) + +// Value tables for @FIU_CurrProfile_Front_Stat signal + +#ifndef FIU_CurrProfile_Front_Stat_FIU_Profile_Guest +#define FIU_CurrProfile_Front_Stat_FIU_Profile_Guest (0) +#endif + +#ifndef FIU_CurrProfile_Front_Stat_FIU_Profile_Profile_1 +#define FIU_CurrProfile_Front_Stat_FIU_Profile_Profile_1 (1) +#endif + +#ifndef FIU_CurrProfile_Front_Stat_FIU_Profile_Profile_2 +#define FIU_CurrProfile_Front_Stat_FIU_Profile_Profile_2 (2) +#endif + +#ifndef FIU_CurrProfile_Front_Stat_FIU_Profile_Profile_3 +#define FIU_CurrProfile_Front_Stat_FIU_Profile_Profile_3 (3) +#endif + +#ifndef FIU_CurrProfile_Front_Stat_FIU_Profile_Profile_4 +#define FIU_CurrProfile_Front_Stat_FIU_Profile_Profile_4 (4) +#endif + +#ifndef FIU_CurrProfile_Front_Stat_FIU_Profile_Profile_5 +#define FIU_CurrProfile_Front_Stat_FIU_Profile_Profile_5 (5) +#endif + +#ifndef FIU_CurrProfile_Front_Stat_FIU_Profile_Reserved +#define FIU_CurrProfile_Front_Stat_FIU_Profile_Reserved (6) +#endif + +#ifndef FIU_CurrProfile_Front_Stat_FIU_Profile_Reserved +#define FIU_CurrProfile_Front_Stat_FIU_Profile_Reserved (7) +#endif + + +// Value tables for @FIU_KeySearch_Req signal + +#ifndef FIU_KeySearch_Req_FIU_Profile_Not_requested +#define FIU_KeySearch_Req_FIU_Profile_Not_requested (0) +#endif + +#ifndef FIU_KeySearch_Req_FIU_Profile_Requested +#define FIU_KeySearch_Req_FIU_Profile_Requested (1) +#endif + + +// Value tables for @FIU_ProfileSeatFront_Stat signal + +#ifndef FIU_ProfileSeatFront_Stat_FIU_Profile_OFF +#define FIU_ProfileSeatFront_Stat_FIU_Profile_OFF (0) +#endif + +#ifndef FIU_ProfileSeatFront_Stat_FIU_Profile_ON +#define FIU_ProfileSeatFront_Stat_FIU_Profile_ON (1) +#endif + + +// Value tables for @FIU_ProfileCustomFront_Stat signal + +#ifndef FIU_ProfileCustomFront_Stat_FIU_Profile_OFF +#define FIU_ProfileCustomFront_Stat_FIU_Profile_OFF (0) +#endif + +#ifndef FIU_ProfileCustomFront_Stat_FIU_Profile_ON +#define FIU_ProfileCustomFront_Stat_FIU_Profile_ON (1) +#endif + + +// Value tables for @FIU_ProfileSystFront_Stat signal + +#ifndef FIU_ProfileSystFront_Stat_FIU_Profile_OFF +#define FIU_ProfileSystFront_Stat_FIU_Profile_OFF (0) +#endif + +#ifndef FIU_ProfileSystFront_Stat_FIU_Profile_ON +#define FIU_ProfileSystFront_Stat_FIU_Profile_ON (1) +#endif + + +// Value tables for @FIU_ProfileCarSettingsFront_Stat signal + +#ifndef FIU_ProfileCarSettingsFront_Stat_FIU_Profile_OFF +#define FIU_ProfileCarSettingsFront_Stat_FIU_Profile_OFF (0) +#endif + +#ifndef FIU_ProfileCarSettingsFront_Stat_FIU_Profile_ON +#define FIU_ProfileCarSettingsFront_Stat_FIU_Profile_ON (1) +#endif + + +// Value tables for @FIU_CurrProfile_Rear_Stat signal + +#ifndef FIU_CurrProfile_Rear_Stat_FIU_Profile_Guest +#define FIU_CurrProfile_Rear_Stat_FIU_Profile_Guest (0) +#endif + +#ifndef FIU_CurrProfile_Rear_Stat_FIU_Profile_Profile_1 +#define FIU_CurrProfile_Rear_Stat_FIU_Profile_Profile_1 (1) +#endif + +#ifndef FIU_CurrProfile_Rear_Stat_FIU_Profile_Profile_2 +#define FIU_CurrProfile_Rear_Stat_FIU_Profile_Profile_2 (2) +#endif + +#ifndef FIU_CurrProfile_Rear_Stat_FIU_Profile_Profile_3 +#define FIU_CurrProfile_Rear_Stat_FIU_Profile_Profile_3 (3) +#endif + +#ifndef FIU_CurrProfile_Rear_Stat_FIU_Profile_Profile_4 +#define FIU_CurrProfile_Rear_Stat_FIU_Profile_Profile_4 (4) +#endif + +#ifndef FIU_CurrProfile_Rear_Stat_FIU_Profile_Profile_5 +#define FIU_CurrProfile_Rear_Stat_FIU_Profile_Profile_5 (5) +#endif + +#ifndef FIU_CurrProfile_Rear_Stat_FIU_Profile_Reserved +#define FIU_CurrProfile_Rear_Stat_FIU_Profile_Reserved (6) +#endif + +#ifndef FIU_CurrProfile_Rear_Stat_FIU_Profile_Reserved +#define FIU_CurrProfile_Rear_Stat_FIU_Profile_Reserved (7) +#endif + + +// Value tables for @FIU_ProfileSeatRear_Req signal + +#ifndef FIU_ProfileSeatRear_Req_FIU_Profile_OFF +#define FIU_ProfileSeatRear_Req_FIU_Profile_OFF (0) +#endif + +#ifndef FIU_ProfileSeatRear_Req_FIU_Profile_ON +#define FIU_ProfileSeatRear_Req_FIU_Profile_ON (1) +#endif + + +// Value tables for @FIU_ProfileCustomRear_Req signal + +#ifndef FIU_ProfileCustomRear_Req_FIU_Profile_OFF +#define FIU_ProfileCustomRear_Req_FIU_Profile_OFF (0) +#endif + +#ifndef FIU_ProfileCustomRear_Req_FIU_Profile_ON +#define FIU_ProfileCustomRear_Req_FIU_Profile_ON (1) +#endif + + +// Value tables for @FIU_ProfileSystRear_Req signal + +#ifndef FIU_ProfileSystRear_Req_FIU_Profile_OFF +#define FIU_ProfileSystRear_Req_FIU_Profile_OFF (0) +#endif + +#ifndef FIU_ProfileSystRear_Req_FIU_Profile_ON +#define FIU_ProfileSystRear_Req_FIU_Profile_ON (1) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Indicate current profile on FIU for others units + // 0 : "Guest" + // 1 : "Profile 1" + // 2 : "Profile 2" + // 3 : "Profile 3" + // 4 : "Profile 4" + // 5 : "Profile 5" + // 6 : "Reserved" + // 7 : "Reserved" + uint8_t FIU_CurrProfile_Front_Stat : 3; // Bits= 3 + + // Request for key search + // 0 : "Not requested" + // 1 : "Requested" + uint8_t FIU_KeySearch_Req : 1; // Bits= 1 + + // ON/OFF 'Seat and Memory' setting in Profile for FIU + // 0 : "OFF" + // 1 : "ON" + uint8_t FIU_ProfileSeatFront_Stat : 1; // Bits= 1 + + // ON/OFF 'Customization' setting in Profile for FIU + // 0 : "OFF" + // 1 : "ON" + uint8_t FIU_ProfileCustomFront_Stat : 1; // Bits= 1 + + // ON/OFF 'System settings' setting in Profile for FIU + // 0 : "OFF" + // 1 : "ON" + uint8_t FIU_ProfileSystFront_Stat : 1; // Bits= 1 + + // ON/OFF 'Car settings' setting in Profile for FIU + // 0 : "OFF" + // 1 : "ON" + uint8_t FIU_ProfileCarSettingsFront_Stat : 1; // Bits= 1 + + // Indicate current profile on central tablet for others units + // 0 : "Guest" + // 1 : "Profile 1" + // 2 : "Profile 2" + // 3 : "Profile 3" + // 4 : "Profile 4" + // 5 : "Profile 5" + // 6 : "Reserved" + // 7 : "Reserved" + uint8_t FIU_CurrProfile_Rear_Stat : 3; // Bits= 3 + + // ON/OFF 'Customization' setting in Profile for central tablet + // 0 : "OFF" + // 1 : "ON" + uint8_t FIU_ProfileSeatRear_Req : 1; // Bits= 1 + + // ON/OFF 'System settings' setting in Profile for central tablet + // 0 : "OFF" + // 1 : "ON" + uint8_t FIU_ProfileCustomRear_Req : 1; // Bits= 1 + + // ON/OFF 'Car settings' setting in Profile for central tablet + // 0 : "OFF" + // 1 : "ON" + uint8_t FIU_ProfileSystRear_Req : 1; // Bits= 1 + +#else + + // Indicate current profile on FIU for others units + // 0 : "Guest" + // 1 : "Profile 1" + // 2 : "Profile 2" + // 3 : "Profile 3" + // 4 : "Profile 4" + // 5 : "Profile 5" + // 6 : "Reserved" + // 7 : "Reserved" + uint8_t FIU_CurrProfile_Front_Stat; // Bits= 3 + + // Request for key search + // 0 : "Not requested" + // 1 : "Requested" + uint8_t FIU_KeySearch_Req; // Bits= 1 + + // ON/OFF 'Seat and Memory' setting in Profile for FIU + // 0 : "OFF" + // 1 : "ON" + uint8_t FIU_ProfileSeatFront_Stat; // Bits= 1 + + // ON/OFF 'Customization' setting in Profile for FIU + // 0 : "OFF" + // 1 : "ON" + uint8_t FIU_ProfileCustomFront_Stat; // Bits= 1 + + // ON/OFF 'System settings' setting in Profile for FIU + // 0 : "OFF" + // 1 : "ON" + uint8_t FIU_ProfileSystFront_Stat; // Bits= 1 + + // ON/OFF 'Car settings' setting in Profile for FIU + // 0 : "OFF" + // 1 : "ON" + uint8_t FIU_ProfileCarSettingsFront_Stat; // Bits= 1 + + // Indicate current profile on central tablet for others units + // 0 : "Guest" + // 1 : "Profile 1" + // 2 : "Profile 2" + // 3 : "Profile 3" + // 4 : "Profile 4" + // 5 : "Profile 5" + // 6 : "Reserved" + // 7 : "Reserved" + uint8_t FIU_CurrProfile_Rear_Stat; // Bits= 3 + + // ON/OFF 'Customization' setting in Profile for central tablet + // 0 : "OFF" + // 1 : "ON" + uint8_t FIU_ProfileSeatRear_Req; // Bits= 1 + + // ON/OFF 'System settings' setting in Profile for central tablet + // 0 : "OFF" + // 1 : "ON" + uint8_t FIU_ProfileCustomRear_Req; // Bits= 1 + + // ON/OFF 'Car settings' setting in Profile for central tablet + // 0 : "OFF" + // 1 : "ON" + uint8_t FIU_ProfileSystRear_Req; // Bits= 1 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} FIU_Profile_t; + +// def @USBSw_Stat CAN Message (1216 0x4c0) +#define USBSw_Stat_IDE (0U) +#define USBSw_Stat_DLC (1U) +#define USBSw_Stat_CANID (0x4c0U) +#define USBSw_Stat_CYC (250U) + +// Value tables for @USBSw_OutputSwitch_Stat signal + +#ifndef USBSw_OutputSwitch_Stat_USBSw_Stat_USB_Switch_Error +#define USBSw_OutputSwitch_Stat_USBSw_Stat_USB_Switch_Error (3) +#endif + +#ifndef USBSw_OutputSwitch_Stat_USBSw_Stat_USB_socket_to_laptop +#define USBSw_OutputSwitch_Stat_USBSw_Stat_USB_socket_to_laptop (2) +#endif + +#ifndef USBSw_OutputSwitch_Stat_USBSw_Stat_FIU +#define USBSw_OutputSwitch_Stat_USBSw_Stat_FIU (1) +#endif + +#ifndef USBSw_OutputSwitch_Stat_USBSw_Stat_No_output_inactive +#define USBSw_OutputSwitch_Stat_USBSw_Stat_No_output_inactive (0) +#endif + + +// Value tables for @USBSw_ConfCamera_Req signal + +#ifndef USBSw_ConfCamera_Req_USBSw_Stat_Active +#define USBSw_ConfCamera_Req_USBSw_Stat_Active (1) +#endif + +#ifndef USBSw_ConfCamera_Req_USBSw_Stat_Inactive +#define USBSw_ConfCamera_Req_USBSw_Stat_Inactive (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Current output switch state + // 3 : "USB Switch Error" + // 2 : "USB socket to laptop" + // 1 : "FIU" + // 0 : "No output (inactive)" + uint8_t USBSw_OutputSwitch_Stat : 2; // Bits= 2 + + // Request to activate the camera for video conferencing + // 1 : "Active" + // 0 : "Inactive" + uint8_t USBSw_ConfCamera_Req : 1; // Bits= 1 + +#else + + // Current output switch state + // 3 : "USB Switch Error" + // 2 : "USB socket to laptop" + // 1 : "FIU" + // 0 : "No output (inactive)" + uint8_t USBSw_OutputSwitch_Stat; // Bits= 2 + + // Request to activate the camera for video conferencing + // 1 : "Active" + // 0 : "Inactive" + uint8_t USBSw_ConfCamera_Req; // Bits= 1 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} USBSw_Stat_t; + +// def @SMFL_status CAN Message (1232 0x4d0) +#define SMFL_status_IDE (0U) +#define SMFL_status_DLC (8U) +#define SMFL_status_CANID (0x4d0U) +#define SMFL_status_CYC (250U) + +// Value tables for @SMFL_MMmenuActivation signal + +#ifndef SMFL_MMmenuActivation_SMFL_status_MM_menu_activation_button_pressed +#define SMFL_MMmenuActivation_SMFL_status_MM_menu_activation_button_pressed (1) +#endif + +#ifndef SMFL_MMmenuActivation_SMFL_status_MM_menu_activation_button_not_pressed +#define SMFL_MMmenuActivation_SMFL_status_MM_menu_activation_button_not_pressed (0) +#endif + + +// Value tables for @SMFL_SeatHeight_Stat signal + +#ifndef SMFL_SeatHeight_Stat_SMFL_status_Reserved +#define SMFL_SeatHeight_Stat_SMFL_status_Reserved (3) +#endif + +#ifndef SMFL_SeatHeight_Stat_SMFL_status_Decrease +#define SMFL_SeatHeight_Stat_SMFL_status_Decrease (2) +#endif + +#ifndef SMFL_SeatHeight_Stat_SMFL_status_Increase +#define SMFL_SeatHeight_Stat_SMFL_status_Increase (1) +#endif + +#ifndef SMFL_SeatHeight_Stat_SMFL_status_No_action +#define SMFL_SeatHeight_Stat_SMFL_status_No_action (0) +#endif + + +// Value tables for @SMFL_HeadRestHeight_Stat signal + +#ifndef SMFL_HeadRestHeight_Stat_SMFL_status_Reserved +#define SMFL_HeadRestHeight_Stat_SMFL_status_Reserved (3) +#endif + +#ifndef SMFL_HeadRestHeight_Stat_SMFL_status_Decrease +#define SMFL_HeadRestHeight_Stat_SMFL_status_Decrease (2) +#endif + +#ifndef SMFL_HeadRestHeight_Stat_SMFL_status_Increase +#define SMFL_HeadRestHeight_Stat_SMFL_status_Increase (1) +#endif + +#ifndef SMFL_HeadRestHeight_Stat_SMFL_status_No_action +#define SMFL_HeadRestHeight_Stat_SMFL_status_No_action (0) +#endif + + +// Value tables for @SMFL_SeatLongitudinal_Stat signal + +#ifndef SMFL_SeatLongitudinal_Stat_SMFL_status_Reserved +#define SMFL_SeatLongitudinal_Stat_SMFL_status_Reserved (3) +#endif + +#ifndef SMFL_SeatLongitudinal_Stat_SMFL_status_Decrease +#define SMFL_SeatLongitudinal_Stat_SMFL_status_Decrease (2) +#endif + +#ifndef SMFL_SeatLongitudinal_Stat_SMFL_status_Increase +#define SMFL_SeatLongitudinal_Stat_SMFL_status_Increase (1) +#endif + +#ifndef SMFL_SeatLongitudinal_Stat_SMFL_status_No_action +#define SMFL_SeatLongitudinal_Stat_SMFL_status_No_action (0) +#endif + + +// Value tables for @SMFL_HeadRestHeightInclin_Stat signal + +#ifndef SMFL_HeadRestHeightInclin_Stat_SMFL_status_Reserved +#define SMFL_HeadRestHeightInclin_Stat_SMFL_status_Reserved (3) +#endif + +#ifndef SMFL_HeadRestHeightInclin_Stat_SMFL_status_Decrease +#define SMFL_HeadRestHeightInclin_Stat_SMFL_status_Decrease (2) +#endif + +#ifndef SMFL_HeadRestHeightInclin_Stat_SMFL_status_Increase +#define SMFL_HeadRestHeightInclin_Stat_SMFL_status_Increase (1) +#endif + +#ifndef SMFL_HeadRestHeightInclin_Stat_SMFL_status_No_action +#define SMFL_HeadRestHeightInclin_Stat_SMFL_status_No_action (0) +#endif + + +// Value tables for @SMFL_SurfaceLongitudinal_Stat signal + +#ifndef SMFL_SurfaceLongitudinal_Stat_SMFL_status_Reserved +#define SMFL_SurfaceLongitudinal_Stat_SMFL_status_Reserved (3) +#endif + +#ifndef SMFL_SurfaceLongitudinal_Stat_SMFL_status_Decrease +#define SMFL_SurfaceLongitudinal_Stat_SMFL_status_Decrease (2) +#endif + +#ifndef SMFL_SurfaceLongitudinal_Stat_SMFL_status_Increase +#define SMFL_SurfaceLongitudinal_Stat_SMFL_status_Increase (1) +#endif + +#ifndef SMFL_SurfaceLongitudinal_Stat_SMFL_status_No_action +#define SMFL_SurfaceLongitudinal_Stat_SMFL_status_No_action (0) +#endif + + +// Value tables for @SMFL_SeatLegSupportH_Stat signal + +#ifndef SMFL_SeatLegSupportH_Stat_SMFL_status_Reserved +#define SMFL_SeatLegSupportH_Stat_SMFL_status_Reserved (3) +#endif + +#ifndef SMFL_SeatLegSupportH_Stat_SMFL_status_Decrease +#define SMFL_SeatLegSupportH_Stat_SMFL_status_Decrease (2) +#endif + +#ifndef SMFL_SeatLegSupportH_Stat_SMFL_status_Increase +#define SMFL_SeatLegSupportH_Stat_SMFL_status_Increase (1) +#endif + +#ifndef SMFL_SeatLegSupportH_Stat_SMFL_status_No_action +#define SMFL_SeatLegSupportH_Stat_SMFL_status_No_action (0) +#endif + + +// Value tables for @SMFL_SeatInclination_Stat signal + +#ifndef SMFL_SeatInclination_Stat_SMFL_status_Reserved +#define SMFL_SeatInclination_Stat_SMFL_status_Reserved (3) +#endif + +#ifndef SMFL_SeatInclination_Stat_SMFL_status_Decrease +#define SMFL_SeatInclination_Stat_SMFL_status_Decrease (2) +#endif + +#ifndef SMFL_SeatInclination_Stat_SMFL_status_Increase +#define SMFL_SeatInclination_Stat_SMFL_status_Increase (1) +#endif + +#ifndef SMFL_SeatInclination_Stat_SMFL_status_No_action +#define SMFL_SeatInclination_Stat_SMFL_status_No_action (0) +#endif + + +// Value tables for @SMFL_SeatLegSupportL_Stat signal + +#ifndef SMFL_SeatLegSupportL_Stat_SMFL_status_Reserved +#define SMFL_SeatLegSupportL_Stat_SMFL_status_Reserved (3) +#endif + +#ifndef SMFL_SeatLegSupportL_Stat_SMFL_status_Decrease +#define SMFL_SeatLegSupportL_Stat_SMFL_status_Decrease (2) +#endif + +#ifndef SMFL_SeatLegSupportL_Stat_SMFL_status_Increase +#define SMFL_SeatLegSupportL_Stat_SMFL_status_Increase (1) +#endif + +#ifndef SMFL_SeatLegSupportL_Stat_SMFL_status_No_action +#define SMFL_SeatLegSupportL_Stat_SMFL_status_No_action (0) +#endif + + +// Value tables for @SMFL_BackRestInclin_Stat signal + +#ifndef SMFL_BackRestInclin_Stat_SMFL_status_Reserved +#define SMFL_BackRestInclin_Stat_SMFL_status_Reserved (3) +#endif + +#ifndef SMFL_BackRestInclin_Stat_SMFL_status_Decrease +#define SMFL_BackRestInclin_Stat_SMFL_status_Decrease (2) +#endif + +#ifndef SMFL_BackRestInclin_Stat_SMFL_status_Increase +#define SMFL_BackRestInclin_Stat_SMFL_status_Increase (1) +#endif + +#ifndef SMFL_BackRestInclin_Stat_SMFL_status_No_action +#define SMFL_BackRestInclin_Stat_SMFL_status_No_action (0) +#endif + + +// Value tables for @SMFL_LumbarSupportHeight_Stat signal + +#ifndef SMFL_LumbarSupportHeight_Stat_SMFL_status_Reserved +#define SMFL_LumbarSupportHeight_Stat_SMFL_status_Reserved (3) +#endif + +#ifndef SMFL_LumbarSupportHeight_Stat_SMFL_status_Decrease +#define SMFL_LumbarSupportHeight_Stat_SMFL_status_Decrease (2) +#endif + +#ifndef SMFL_LumbarSupportHeight_Stat_SMFL_status_Increase +#define SMFL_LumbarSupportHeight_Stat_SMFL_status_Increase (1) +#endif + +#ifndef SMFL_LumbarSupportHeight_Stat_SMFL_status_No_action +#define SMFL_LumbarSupportHeight_Stat_SMFL_status_No_action (0) +#endif + + +// Value tables for @SMFL_BackRestHeadInclin_Stat signal + +#ifndef SMFL_BackRestHeadInclin_Stat_SMFL_status_Reserved +#define SMFL_BackRestHeadInclin_Stat_SMFL_status_Reserved (3) +#endif + +#ifndef SMFL_BackRestHeadInclin_Stat_SMFL_status_Decrease +#define SMFL_BackRestHeadInclin_Stat_SMFL_status_Decrease (2) +#endif + +#ifndef SMFL_BackRestHeadInclin_Stat_SMFL_status_Increase +#define SMFL_BackRestHeadInclin_Stat_SMFL_status_Increase (1) +#endif + +#ifndef SMFL_BackRestHeadInclin_Stat_SMFL_status_No_action +#define SMFL_BackRestHeadInclin_Stat_SMFL_status_No_action (0) +#endif + + +// Value tables for @SMFL_LumbarSupportDepth_Stat signal + +#ifndef SMFL_LumbarSupportDepth_Stat_SMFL_status_Reserved +#define SMFL_LumbarSupportDepth_Stat_SMFL_status_Reserved (3) +#endif + +#ifndef SMFL_LumbarSupportDepth_Stat_SMFL_status_Decrease +#define SMFL_LumbarSupportDepth_Stat_SMFL_status_Decrease (2) +#endif + +#ifndef SMFL_LumbarSupportDepth_Stat_SMFL_status_Increase +#define SMFL_LumbarSupportDepth_Stat_SMFL_status_Increase (1) +#endif + +#ifndef SMFL_LumbarSupportDepth_Stat_SMFL_status_No_action +#define SMFL_LumbarSupportDepth_Stat_SMFL_status_No_action (0) +#endif + + +// Value tables for @SMFL_BackRestWidth_Stat signal + +#ifndef SMFL_BackRestWidth_Stat_SMFL_status_Reserved +#define SMFL_BackRestWidth_Stat_SMFL_status_Reserved (3) +#endif + +#ifndef SMFL_BackRestWidth_Stat_SMFL_status_Decrease +#define SMFL_BackRestWidth_Stat_SMFL_status_Decrease (2) +#endif + +#ifndef SMFL_BackRestWidth_Stat_SMFL_status_Increase +#define SMFL_BackRestWidth_Stat_SMFL_status_Increase (1) +#endif + +#ifndef SMFL_BackRestWidth_Stat_SMFL_status_No_action +#define SMFL_BackRestWidth_Stat_SMFL_status_No_action (0) +#endif + + +// Value tables for @SMFL_CushionSupport_Stat signal + +#ifndef SMFL_CushionSupport_Stat_SMFL_status_Reserved +#define SMFL_CushionSupport_Stat_SMFL_status_Reserved (3) +#endif + +#ifndef SMFL_CushionSupport_Stat_SMFL_status_Decrease +#define SMFL_CushionSupport_Stat_SMFL_status_Decrease (2) +#endif + +#ifndef SMFL_CushionSupport_Stat_SMFL_status_Increase +#define SMFL_CushionSupport_Stat_SMFL_status_Increase (1) +#endif + +#ifndef SMFL_CushionSupport_Stat_SMFL_status_No_action +#define SMFL_CushionSupport_Stat_SMFL_status_No_action (0) +#endif + + +// Value tables for @SMFL_SeatVentilation_Stat signal + +#ifndef SMFL_SeatVentilation_Stat_SMFL_status_High_Power +#define SMFL_SeatVentilation_Stat_SMFL_status_High_Power (3) +#endif + +#ifndef SMFL_SeatVentilation_Stat_SMFL_status_Middle_Power +#define SMFL_SeatVentilation_Stat_SMFL_status_Middle_Power (2) +#endif + +#ifndef SMFL_SeatVentilation_Stat_SMFL_status_Low_Power +#define SMFL_SeatVentilation_Stat_SMFL_status_Low_Power (1) +#endif + +#ifndef SMFL_SeatVentilation_Stat_SMFL_status_No_action +#define SMFL_SeatVentilation_Stat_SMFL_status_No_action (0) +#endif + + +// Value tables for @SMFL_SeatVentBalance_Stat signal + +#ifndef SMFL_SeatVentBalance_Stat_SMFL_status_Backrest_100_Cushion_00_3 +#define SMFL_SeatVentBalance_Stat_SMFL_status_Backrest_100_Cushion_00_3 (7) +#endif + +#ifndef SMFL_SeatVentBalance_Stat_SMFL_status_Backrest_100_Cushion_33_2 +#define SMFL_SeatVentBalance_Stat_SMFL_status_Backrest_100_Cushion_33_2 (6) +#endif + +#ifndef SMFL_SeatVentBalance_Stat_SMFL_status_Backrest_100_Cushion_67_1 +#define SMFL_SeatVentBalance_Stat_SMFL_status_Backrest_100_Cushion_67_1 (5) +#endif + +#ifndef SMFL_SeatVentBalance_Stat_SMFL_status_Backrest_100_Cushion_100_0 +#define SMFL_SeatVentBalance_Stat_SMFL_status_Backrest_100_Cushion_100_0 (4) +#endif + +#ifndef SMFL_SeatVentBalance_Stat_SMFL_status_Backrest_67_Cushion_100_1 +#define SMFL_SeatVentBalance_Stat_SMFL_status_Backrest_67_Cushion_100_1 (3) +#endif + +#ifndef SMFL_SeatVentBalance_Stat_SMFL_status_Backrest_33_Cushion_100_2 +#define SMFL_SeatVentBalance_Stat_SMFL_status_Backrest_33_Cushion_100_2 (2) +#endif + +#ifndef SMFL_SeatVentBalance_Stat_SMFL_status_Backrest_00_Cushion_100_3 +#define SMFL_SeatVentBalance_Stat_SMFL_status_Backrest_00_Cushion_100_3 (1) +#endif + +#ifndef SMFL_SeatVentBalance_Stat_SMFL_status_No_action +#define SMFL_SeatVentBalance_Stat_SMFL_status_No_action (0) +#endif + + +// Value tables for @SMFL_Heating_Stat signal + +#ifndef SMFL_Heating_Stat_SMFL_status_High_Power +#define SMFL_Heating_Stat_SMFL_status_High_Power (3) +#endif + +#ifndef SMFL_Heating_Stat_SMFL_status_Middle_Power +#define SMFL_Heating_Stat_SMFL_status_Middle_Power (2) +#endif + +#ifndef SMFL_Heating_Stat_SMFL_status_Low_Power +#define SMFL_Heating_Stat_SMFL_status_Low_Power (1) +#endif + +#ifndef SMFL_Heating_Stat_SMFL_status_No_action +#define SMFL_Heating_Stat_SMFL_status_No_action (0) +#endif + + +// Value tables for @SMFL_HeatBalance_Stat signal + +#ifndef SMFL_HeatBalance_Stat_SMFL_status_Backrest_100_Cushion_00_3 +#define SMFL_HeatBalance_Stat_SMFL_status_Backrest_100_Cushion_00_3 (7) +#endif + +#ifndef SMFL_HeatBalance_Stat_SMFL_status_Backrest_100_Cushion_33_2 +#define SMFL_HeatBalance_Stat_SMFL_status_Backrest_100_Cushion_33_2 (6) +#endif + +#ifndef SMFL_HeatBalance_Stat_SMFL_status_Backrest_100_Cushion_67_1 +#define SMFL_HeatBalance_Stat_SMFL_status_Backrest_100_Cushion_67_1 (5) +#endif + +#ifndef SMFL_HeatBalance_Stat_SMFL_status_Backrest_100_Cushion_100_0 +#define SMFL_HeatBalance_Stat_SMFL_status_Backrest_100_Cushion_100_0 (4) +#endif + +#ifndef SMFL_HeatBalance_Stat_SMFL_status_Backrest_67_Cushion_100_1 +#define SMFL_HeatBalance_Stat_SMFL_status_Backrest_67_Cushion_100_1 (3) +#endif + +#ifndef SMFL_HeatBalance_Stat_SMFL_status_Backrest_33_Cushion_100_2 +#define SMFL_HeatBalance_Stat_SMFL_status_Backrest_33_Cushion_100_2 (2) +#endif + +#ifndef SMFL_HeatBalance_Stat_SMFL_status_Backrest_00_Cushion_100_3 +#define SMFL_HeatBalance_Stat_SMFL_status_Backrest_00_Cushion_100_3 (1) +#endif + +#ifndef SMFL_HeatBalance_Stat_SMFL_status_No_action +#define SMFL_HeatBalance_Stat_SMFL_status_No_action (0) +#endif + + +// Value tables for @SMFL_SeatMassage_Stat signal + +#ifndef SMFL_SeatMassage_Stat_SMFL_status_Reserved +#define SMFL_SeatMassage_Stat_SMFL_status_Reserved (3) +#endif + +#ifndef SMFL_SeatMassage_Stat_SMFL_status_Massage_ON +#define SMFL_SeatMassage_Stat_SMFL_status_Massage_ON (2) +#endif + +#ifndef SMFL_SeatMassage_Stat_SMFL_status_Massage_OFF +#define SMFL_SeatMassage_Stat_SMFL_status_Massage_OFF (1) +#endif + +#ifndef SMFL_SeatMassage_Stat_SMFL_status_No_action +#define SMFL_SeatMassage_Stat_SMFL_status_No_action (0) +#endif + + +// Value tables for @SMFL_MassageIntens_Stat signal + +#ifndef SMFL_MassageIntens_Stat_SMFL_status_High_power +#define SMFL_MassageIntens_Stat_SMFL_status_High_power (3) +#endif + +#ifndef SMFL_MassageIntens_Stat_SMFL_status_Middle_power +#define SMFL_MassageIntens_Stat_SMFL_status_Middle_power (2) +#endif + +#ifndef SMFL_MassageIntens_Stat_SMFL_status_Low_power +#define SMFL_MassageIntens_Stat_SMFL_status_Low_power (1) +#endif + +#ifndef SMFL_MassageIntens_Stat_SMFL_status_No_action +#define SMFL_MassageIntens_Stat_SMFL_status_No_action (0) +#endif + + +// Value tables for @SMFL_SeatMassageType_Stat signal + +#ifndef SMFL_SeatMassageType_Stat_SMFL_status_Type_7_Velvet +#define SMFL_SeatMassageType_Stat_SMFL_status_Type_7_Velvet (7) +#endif + +#ifndef SMFL_SeatMassageType_Stat_SMFL_status_Type_6_Sonnet +#define SMFL_SeatMassageType_Stat_SMFL_status_Type_6_Sonnet (6) +#endif + +#ifndef SMFL_SeatMassageType_Stat_SMFL_status_Type_5_Quantum +#define SMFL_SeatMassageType_Stat_SMFL_status_Type_5_Quantum (5) +#endif + +#ifndef SMFL_SeatMassageType_Stat_SMFL_status_Type_4_Cashmere +#define SMFL_SeatMassageType_Stat_SMFL_status_Type_4_Cashmere (4) +#endif + +#ifndef SMFL_SeatMassageType_Stat_SMFL_status_Type_3_Harmony +#define SMFL_SeatMassageType_Stat_SMFL_status_Type_3_Harmony (3) +#endif + +#ifndef SMFL_SeatMassageType_Stat_SMFL_status_Type_2_Orbital +#define SMFL_SeatMassageType_Stat_SMFL_status_Type_2_Orbital (2) +#endif + +#ifndef SMFL_SeatMassageType_Stat_SMFL_status_Type_1_Insight +#define SMFL_SeatMassageType_Stat_SMFL_status_Type_1_Insight (1) +#endif + +#ifndef SMFL_SeatMassageType_Stat_SMFL_status_No_action +#define SMFL_SeatMassageType_Stat_SMFL_status_No_action (0) +#endif + + +// Value tables for @SMFL_TabletPWR_Stat signal + +#ifndef SMFL_TabletPWR_Stat_SMFL_status_On +#define SMFL_TabletPWR_Stat_SMFL_status_On (1) +#endif + +#ifndef SMFL_TabletPWR_Stat_SMFL_status_Off +#define SMFL_TabletPWR_Stat_SMFL_status_Off (0) +#endif + + +// Value tables for @SMFL_CarpetHeat_Stat signal + +#ifndef SMFL_CarpetHeat_Stat_SMFL_status_Carpet_heating_is_active +#define SMFL_CarpetHeat_Stat_SMFL_status_Carpet_heating_is_active (1) +#endif + +#ifndef SMFL_CarpetHeat_Stat_SMFL_status_Carpet_heating_is_inactive +#define SMFL_CarpetHeat_Stat_SMFL_status_Carpet_heating_is_inactive (0) +#endif + + +// Value tables for @SMFL_ActiveSupport_Stat signal + +#ifndef SMFL_ActiveSupport_Stat_SMFL_status_Active +#define SMFL_ActiveSupport_Stat_SMFL_status_Active (1) +#endif + +#ifndef SMFL_ActiveSupport_Stat_SMFL_status_Inactive +#define SMFL_ActiveSupport_Stat_SMFL_status_Inactive (0) +#endif + + +// Value tables for @SMFL_BackrestMassageType_Stat signal + +#ifndef SMFL_BackrestMassageType_Stat_SMFL_status_Reserved +#define SMFL_BackrestMassageType_Stat_SMFL_status_Reserved (7) +#endif + +#ifndef SMFL_BackrestMassageType_Stat_SMFL_status_Reserved +#define SMFL_BackrestMassageType_Stat_SMFL_status_Reserved (6) +#endif + +#ifndef SMFL_BackrestMassageType_Stat_SMFL_status_Type_5_Elegy +#define SMFL_BackrestMassageType_Stat_SMFL_status_Type_5_Elegy (5) +#endif + +#ifndef SMFL_BackrestMassageType_Stat_SMFL_status_Type_4_Caprice +#define SMFL_BackrestMassageType_Stat_SMFL_status_Type_4_Caprice (4) +#endif + +#ifndef SMFL_BackrestMassageType_Stat_SMFL_status_Type_3_Pulse +#define SMFL_BackrestMassageType_Stat_SMFL_status_Type_3_Pulse (3) +#endif + +#ifndef SMFL_BackrestMassageType_Stat_SMFL_status_Type_2_Energy +#define SMFL_BackrestMassageType_Stat_SMFL_status_Type_2_Energy (2) +#endif + +#ifndef SMFL_BackrestMassageType_Stat_SMFL_status_Type_1_Synchrony +#define SMFL_BackrestMassageType_Stat_SMFL_status_Type_1_Synchrony (1) +#endif + +#ifndef SMFL_BackrestMassageType_Stat_SMFL_status_No_action +#define SMFL_BackrestMassageType_Stat_SMFL_status_No_action (0) +#endif + + +// Value tables for @SMFL_TimerMassage_Stat signal + +#ifndef SMFL_TimerMassage_Stat_SMFL_status_Reserved +#define SMFL_TimerMassage_Stat_SMFL_status_Reserved (7) +#endif + +#ifndef SMFL_TimerMassage_Stat_SMFL_status_Reserved +#define SMFL_TimerMassage_Stat_SMFL_status_Reserved (6) +#endif + +#ifndef SMFL_TimerMassage_Stat_SMFL_status__min +#define SMFL_TimerMassage_Stat_SMFL_status__min (5) +#endif + +#ifndef SMFL_TimerMassage_Stat_SMFL_status__min +#define SMFL_TimerMassage_Stat_SMFL_status__min (4) +#endif + +#ifndef SMFL_TimerMassage_Stat_SMFL_status__min +#define SMFL_TimerMassage_Stat_SMFL_status__min (3) +#endif + +#ifndef SMFL_TimerMassage_Stat_SMFL_status__min +#define SMFL_TimerMassage_Stat_SMFL_status__min (2) +#endif + +#ifndef SMFL_TimerMassage_Stat_SMFL_status__min +#define SMFL_TimerMassage_Stat_SMFL_status__min (1) +#endif + +#ifndef SMFL_TimerMassage_Stat_SMFL_status__min +#define SMFL_TimerMassage_Stat_SMFL_status__min (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Signal of pressing MM menu button on SMFL + // 1 : "MM menu activation button pressed" + // 0 : "MM menu activation button not pressed" + uint8_t SMFL_MMmenuActivation : 1; // Bits= 1 + + // FL seat height changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFL_SeatHeight_Stat : 2; // Bits= 2 + + // FL seat headrest height changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFL_HeadRestHeight_Stat : 2; // Bits= 2 + + // FL seat longitudinal changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFL_SeatLongitudinal_Stat : 2; // Bits= 2 + + // FL seat headrest height inclination changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFL_HeadRestHeightInclin_Stat : 2; // Bits= 2 + + // FL seat surface longitudinal changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFL_SurfaceLongitudinal_Stat : 2; // Bits= 2 + + // FL seat footrest changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFL_SeatLegSupportH_Stat : 2; // Bits= 2 + + // FL seat inclination status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFL_SeatInclination_Stat : 2; // Bits= 2 + + // FL seat footrest longitudinal changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFL_SeatLegSupportL_Stat : 2; // Bits= 2 + + // FL seat backrest inclination status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFL_BackRestInclin_Stat : 2; // Bits= 2 + + // FL seat lumbar support height status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFL_LumbarSupportHeight_Stat : 2; // Bits= 2 + + // FL seat backrest head inclination status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFL_BackRestHeadInclin_Stat : 2; // Bits= 2 + + // FL seat lumbar support depth status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFL_LumbarSupportDepth_Stat : 2; // Bits= 2 + + // FL seat backrest width status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFL_BackRestWidth_Stat : 2; // Bits= 2 + + // FL seat cushion support inclination status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFL_CushionSupport_Stat : 2; // Bits= 2 + + // FL seat ventilation status + // 3 : "High Power" + // 2 : "Middle Power" + // 1 : "Low Power" + // 0 : "No action" + uint8_t SMFL_SeatVentilation_Stat : 2; // Bits= 2 + + // FL seat ventilation balance status + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 00%, Cushion 100%: -3" + // 0 : "No action" + uint8_t SMFL_SeatVentBalance_Stat : 3; // Bits= 3 + + // FL seat heating status + // 3 : "High Power" + // 2 : "Middle Power" + // 1 : "Low Power" + // 0 : "No action" + uint8_t SMFL_Heating_Stat : 2; // Bits= 2 + + // FL seat heating balance status + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 00%, Cushion 100%: -3" + // 0 : "No action" + uint8_t SMFL_HeatBalance_Stat : 3; // Bits= 3 + + // FL seat massage status + // 3 : "Reserved" + // 2 : "Massage ON" + // 1 : "Massage OFF" + // 0 : "No action" + uint8_t SMFL_SeatMassage_Stat : 2; // Bits= 2 + + // FL seat massage intencivity status + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "No action" + uint8_t SMFL_MassageIntens_Stat : 2; // Bits= 2 + + // FL seat massage type status + // 7 : "Type 7 (Velvet)" + // 6 : "Type 6 (Sonnet)" + // 5 : "Type 5 (Quantum)" + // 4 : "Type 4 (Cashmere)" + // 3 : "Type 3 (Harmony)" + // 2 : "Type 2 (Orbital)" + // 1 : "Type 1 (Insight)" + // 0 : "No action" + uint8_t SMFL_SeatMassageType_Stat : 3; // Bits= 3 + + // Of DocSL+T Tablet power on/off status + // 1 : "On" + // 0 : "Off" + uint8_t SMFL_TabletPWR_Stat : 1; // Bits= 1 + + // Carpet heating status for front left zone + // 1 : "Carpet heating is active" + // 0 : "Carpet heating is inactive" + uint8_t SMFL_CarpetHeat_Stat : 1; // Bits= 1 + + // Active lateral status + // 1 : "Active" + // 0 : "Inactive" + uint8_t SMFL_ActiveSupport_Stat : 1; // Bits= 1 + + // Signal for backrest massage type (mode) + // (RL backrest massage type request) + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Type 5 (Elegy)" + // 4 : "Type 4 (Caprice)" + // 3 : "Type 3 (Pulse)" + // 2 : "Type 2 (Energy)" + // 1 : "Type 1 (Synchrony)" + // 0 : "No action" + uint8_t SMFL_BackrestMassageType_Stat : 3; // Bits= 3 + + // FL seat massage timer status + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "5 min" + // 4 : "10 min" + // 3 : "15 min" + // 2 : "20 min" + // 1 : "25 min" + // 0 : "30 min" + uint8_t SMFL_TimerMassage_Stat : 3; // Bits= 3 + +#else + + // Signal of pressing MM menu button on SMFL + // 1 : "MM menu activation button pressed" + // 0 : "MM menu activation button not pressed" + uint8_t SMFL_MMmenuActivation; // Bits= 1 + + // FL seat height changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFL_SeatHeight_Stat; // Bits= 2 + + // FL seat headrest height changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFL_HeadRestHeight_Stat; // Bits= 2 + + // FL seat longitudinal changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFL_SeatLongitudinal_Stat; // Bits= 2 + + // FL seat headrest height inclination changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFL_HeadRestHeightInclin_Stat; // Bits= 2 + + // FL seat surface longitudinal changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFL_SurfaceLongitudinal_Stat; // Bits= 2 + + // FL seat footrest changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFL_SeatLegSupportH_Stat; // Bits= 2 + + // FL seat inclination status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFL_SeatInclination_Stat; // Bits= 2 + + // FL seat footrest longitudinal changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFL_SeatLegSupportL_Stat; // Bits= 2 + + // FL seat backrest inclination status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFL_BackRestInclin_Stat; // Bits= 2 + + // FL seat lumbar support height status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFL_LumbarSupportHeight_Stat; // Bits= 2 + + // FL seat backrest head inclination status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFL_BackRestHeadInclin_Stat; // Bits= 2 + + // FL seat lumbar support depth status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFL_LumbarSupportDepth_Stat; // Bits= 2 + + // FL seat backrest width status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFL_BackRestWidth_Stat; // Bits= 2 + + // FL seat cushion support inclination status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFL_CushionSupport_Stat; // Bits= 2 + + // FL seat ventilation status + // 3 : "High Power" + // 2 : "Middle Power" + // 1 : "Low Power" + // 0 : "No action" + uint8_t SMFL_SeatVentilation_Stat; // Bits= 2 + + // FL seat ventilation balance status + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 00%, Cushion 100%: -3" + // 0 : "No action" + uint8_t SMFL_SeatVentBalance_Stat; // Bits= 3 + + // FL seat heating status + // 3 : "High Power" + // 2 : "Middle Power" + // 1 : "Low Power" + // 0 : "No action" + uint8_t SMFL_Heating_Stat; // Bits= 2 + + // FL seat heating balance status + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 00%, Cushion 100%: -3" + // 0 : "No action" + uint8_t SMFL_HeatBalance_Stat; // Bits= 3 + + // FL seat massage status + // 3 : "Reserved" + // 2 : "Massage ON" + // 1 : "Massage OFF" + // 0 : "No action" + uint8_t SMFL_SeatMassage_Stat; // Bits= 2 + + // FL seat massage intencivity status + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "No action" + uint8_t SMFL_MassageIntens_Stat; // Bits= 2 + + // FL seat massage type status + // 7 : "Type 7 (Velvet)" + // 6 : "Type 6 (Sonnet)" + // 5 : "Type 5 (Quantum)" + // 4 : "Type 4 (Cashmere)" + // 3 : "Type 3 (Harmony)" + // 2 : "Type 2 (Orbital)" + // 1 : "Type 1 (Insight)" + // 0 : "No action" + uint8_t SMFL_SeatMassageType_Stat; // Bits= 3 + + // Of DocSL+T Tablet power on/off status + // 1 : "On" + // 0 : "Off" + uint8_t SMFL_TabletPWR_Stat; // Bits= 1 + + // Carpet heating status for front left zone + // 1 : "Carpet heating is active" + // 0 : "Carpet heating is inactive" + uint8_t SMFL_CarpetHeat_Stat; // Bits= 1 + + // Active lateral status + // 1 : "Active" + // 0 : "Inactive" + uint8_t SMFL_ActiveSupport_Stat; // Bits= 1 + + // Signal for backrest massage type (mode) + // (RL backrest massage type request) + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Type 5 (Elegy)" + // 4 : "Type 4 (Caprice)" + // 3 : "Type 3 (Pulse)" + // 2 : "Type 2 (Energy)" + // 1 : "Type 1 (Synchrony)" + // 0 : "No action" + uint8_t SMFL_BackrestMassageType_Stat; // Bits= 3 + + // FL seat massage timer status + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "5 min" + // 4 : "10 min" + // 3 : "15 min" + // 2 : "20 min" + // 1 : "25 min" + // 0 : "30 min" + uint8_t SMFL_TimerMassage_Stat; // Bits= 3 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} SMFL_status_t; + +// def @SMFR_status CAN Message (1233 0x4d1) +#define SMFR_status_IDE (0U) +#define SMFR_status_DLC (8U) +#define SMFR_status_CANID (0x4d1U) +#define SMFR_status_CYC (250U) + +// Value tables for @SMFR_MMmenuActivBtn_Stat signal + +#ifndef SMFR_MMmenuActivBtn_Stat_SMFR_status_MM_menu_activation_button_pressed +#define SMFR_MMmenuActivBtn_Stat_SMFR_status_MM_menu_activation_button_pressed (1) +#endif + +#ifndef SMFR_MMmenuActivBtn_Stat_SMFR_status_MM_menu_activation_button_not_pressed +#define SMFR_MMmenuActivBtn_Stat_SMFR_status_MM_menu_activation_button_not_pressed (0) +#endif + + +// Value tables for @SMFR_SeatHeight_Stat signal + +#ifndef SMFR_SeatHeight_Stat_SMFR_status_Reserved +#define SMFR_SeatHeight_Stat_SMFR_status_Reserved (3) +#endif + +#ifndef SMFR_SeatHeight_Stat_SMFR_status_Decrease +#define SMFR_SeatHeight_Stat_SMFR_status_Decrease (2) +#endif + +#ifndef SMFR_SeatHeight_Stat_SMFR_status_Increase +#define SMFR_SeatHeight_Stat_SMFR_status_Increase (1) +#endif + +#ifndef SMFR_SeatHeight_Stat_SMFR_status_No_action +#define SMFR_SeatHeight_Stat_SMFR_status_No_action (0) +#endif + + +// Value tables for @SMFR_HeadRestHeight_Stat signal + +#ifndef SMFR_HeadRestHeight_Stat_SMFR_status_Reserved +#define SMFR_HeadRestHeight_Stat_SMFR_status_Reserved (3) +#endif + +#ifndef SMFR_HeadRestHeight_Stat_SMFR_status_Decrease +#define SMFR_HeadRestHeight_Stat_SMFR_status_Decrease (2) +#endif + +#ifndef SMFR_HeadRestHeight_Stat_SMFR_status_Increase +#define SMFR_HeadRestHeight_Stat_SMFR_status_Increase (1) +#endif + +#ifndef SMFR_HeadRestHeight_Stat_SMFR_status_No_action +#define SMFR_HeadRestHeight_Stat_SMFR_status_No_action (0) +#endif + + +// Value tables for @SMFR_SeatLongitudinal_Stat signal + +#ifndef SMFR_SeatLongitudinal_Stat_SMFR_status_Reserved +#define SMFR_SeatLongitudinal_Stat_SMFR_status_Reserved (3) +#endif + +#ifndef SMFR_SeatLongitudinal_Stat_SMFR_status_Decrease +#define SMFR_SeatLongitudinal_Stat_SMFR_status_Decrease (2) +#endif + +#ifndef SMFR_SeatLongitudinal_Stat_SMFR_status_Increase +#define SMFR_SeatLongitudinal_Stat_SMFR_status_Increase (1) +#endif + +#ifndef SMFR_SeatLongitudinal_Stat_SMFR_status_No_action +#define SMFR_SeatLongitudinal_Stat_SMFR_status_No_action (0) +#endif + + +// Value tables for @SMFR_HeadRestHeightInclin_Stat signal + +#ifndef SMFR_HeadRestHeightInclin_Stat_SMFR_status_Reserved +#define SMFR_HeadRestHeightInclin_Stat_SMFR_status_Reserved (3) +#endif + +#ifndef SMFR_HeadRestHeightInclin_Stat_SMFR_status_Decrease +#define SMFR_HeadRestHeightInclin_Stat_SMFR_status_Decrease (2) +#endif + +#ifndef SMFR_HeadRestHeightInclin_Stat_SMFR_status_Increase +#define SMFR_HeadRestHeightInclin_Stat_SMFR_status_Increase (1) +#endif + +#ifndef SMFR_HeadRestHeightInclin_Stat_SMFR_status_No_action +#define SMFR_HeadRestHeightInclin_Stat_SMFR_status_No_action (0) +#endif + + +// Value tables for @SMFR_SurfaceLongitudinal_Stat signal + +#ifndef SMFR_SurfaceLongitudinal_Stat_SMFR_status_Reserved +#define SMFR_SurfaceLongitudinal_Stat_SMFR_status_Reserved (3) +#endif + +#ifndef SMFR_SurfaceLongitudinal_Stat_SMFR_status_Decrease +#define SMFR_SurfaceLongitudinal_Stat_SMFR_status_Decrease (2) +#endif + +#ifndef SMFR_SurfaceLongitudinal_Stat_SMFR_status_Increase +#define SMFR_SurfaceLongitudinal_Stat_SMFR_status_Increase (1) +#endif + +#ifndef SMFR_SurfaceLongitudinal_Stat_SMFR_status_No_action +#define SMFR_SurfaceLongitudinal_Stat_SMFR_status_No_action (0) +#endif + + +// Value tables for @SMFR_FootRestHeight_Stat signal + +#ifndef SMFR_FootRestHeight_Stat_SMFR_status_Reserved +#define SMFR_FootRestHeight_Stat_SMFR_status_Reserved (3) +#endif + +#ifndef SMFR_FootRestHeight_Stat_SMFR_status_Decrease +#define SMFR_FootRestHeight_Stat_SMFR_status_Decrease (2) +#endif + +#ifndef SMFR_FootRestHeight_Stat_SMFR_status_Increase +#define SMFR_FootRestHeight_Stat_SMFR_status_Increase (1) +#endif + +#ifndef SMFR_FootRestHeight_Stat_SMFR_status_No_action +#define SMFR_FootRestHeight_Stat_SMFR_status_No_action (0) +#endif + + +// Value tables for @SMFR_SeatInclination_Stat signal + +#ifndef SMFR_SeatInclination_Stat_SMFR_status_Reserved +#define SMFR_SeatInclination_Stat_SMFR_status_Reserved (3) +#endif + +#ifndef SMFR_SeatInclination_Stat_SMFR_status_Decrease +#define SMFR_SeatInclination_Stat_SMFR_status_Decrease (2) +#endif + +#ifndef SMFR_SeatInclination_Stat_SMFR_status_Increase +#define SMFR_SeatInclination_Stat_SMFR_status_Increase (1) +#endif + +#ifndef SMFR_SeatInclination_Stat_SMFR_status_No_action +#define SMFR_SeatInclination_Stat_SMFR_status_No_action (0) +#endif + + +// Value tables for @SMFR_SeatLegSupportL_Stat signal + +#ifndef SMFR_SeatLegSupportL_Stat_SMFR_status_Reserved +#define SMFR_SeatLegSupportL_Stat_SMFR_status_Reserved (3) +#endif + +#ifndef SMFR_SeatLegSupportL_Stat_SMFR_status_Decrease +#define SMFR_SeatLegSupportL_Stat_SMFR_status_Decrease (2) +#endif + +#ifndef SMFR_SeatLegSupportL_Stat_SMFR_status_Increase +#define SMFR_SeatLegSupportL_Stat_SMFR_status_Increase (1) +#endif + +#ifndef SMFR_SeatLegSupportL_Stat_SMFR_status_No_action +#define SMFR_SeatLegSupportL_Stat_SMFR_status_No_action (0) +#endif + + +// Value tables for @SMFR_BackRestInclin_Stat signal + +#ifndef SMFR_BackRestInclin_Stat_SMFR_status_Reserved +#define SMFR_BackRestInclin_Stat_SMFR_status_Reserved (3) +#endif + +#ifndef SMFR_BackRestInclin_Stat_SMFR_status_Decrease +#define SMFR_BackRestInclin_Stat_SMFR_status_Decrease (2) +#endif + +#ifndef SMFR_BackRestInclin_Stat_SMFR_status_Increase +#define SMFR_BackRestInclin_Stat_SMFR_status_Increase (1) +#endif + +#ifndef SMFR_BackRestInclin_Stat_SMFR_status_No_action +#define SMFR_BackRestInclin_Stat_SMFR_status_No_action (0) +#endif + + +// Value tables for @SMFR_LumbarSupportHeight_Stat signal + +#ifndef SMFR_LumbarSupportHeight_Stat_SMFR_status_Reserved +#define SMFR_LumbarSupportHeight_Stat_SMFR_status_Reserved (3) +#endif + +#ifndef SMFR_LumbarSupportHeight_Stat_SMFR_status_Decrease +#define SMFR_LumbarSupportHeight_Stat_SMFR_status_Decrease (2) +#endif + +#ifndef SMFR_LumbarSupportHeight_Stat_SMFR_status_Increase +#define SMFR_LumbarSupportHeight_Stat_SMFR_status_Increase (1) +#endif + +#ifndef SMFR_LumbarSupportHeight_Stat_SMFR_status_No_action +#define SMFR_LumbarSupportHeight_Stat_SMFR_status_No_action (0) +#endif + + +// Value tables for @SMFR_BackRestHeadInclin_Stat signal + +#ifndef SMFR_BackRestHeadInclin_Stat_SMFR_status_Reserved +#define SMFR_BackRestHeadInclin_Stat_SMFR_status_Reserved (3) +#endif + +#ifndef SMFR_BackRestHeadInclin_Stat_SMFR_status_Decrease +#define SMFR_BackRestHeadInclin_Stat_SMFR_status_Decrease (2) +#endif + +#ifndef SMFR_BackRestHeadInclin_Stat_SMFR_status_Increase +#define SMFR_BackRestHeadInclin_Stat_SMFR_status_Increase (1) +#endif + +#ifndef SMFR_BackRestHeadInclin_Stat_SMFR_status_No_action +#define SMFR_BackRestHeadInclin_Stat_SMFR_status_No_action (0) +#endif + + +// Value tables for @SMFR_LumbarSupportDepth_Stat signal + +#ifndef SMFR_LumbarSupportDepth_Stat_SMFR_status_Reserved +#define SMFR_LumbarSupportDepth_Stat_SMFR_status_Reserved (3) +#endif + +#ifndef SMFR_LumbarSupportDepth_Stat_SMFR_status_Decrease +#define SMFR_LumbarSupportDepth_Stat_SMFR_status_Decrease (2) +#endif + +#ifndef SMFR_LumbarSupportDepth_Stat_SMFR_status_Increase +#define SMFR_LumbarSupportDepth_Stat_SMFR_status_Increase (1) +#endif + +#ifndef SMFR_LumbarSupportDepth_Stat_SMFR_status_No_action +#define SMFR_LumbarSupportDepth_Stat_SMFR_status_No_action (0) +#endif + + +// Value tables for @SMFR_BackRestWidth_Stat signal + +#ifndef SMFR_BackRestWidth_Stat_SMFR_status_Reserved +#define SMFR_BackRestWidth_Stat_SMFR_status_Reserved (3) +#endif + +#ifndef SMFR_BackRestWidth_Stat_SMFR_status_Decrease +#define SMFR_BackRestWidth_Stat_SMFR_status_Decrease (2) +#endif + +#ifndef SMFR_BackRestWidth_Stat_SMFR_status_Increase +#define SMFR_BackRestWidth_Stat_SMFR_status_Increase (1) +#endif + +#ifndef SMFR_BackRestWidth_Stat_SMFR_status_No_action +#define SMFR_BackRestWidth_Stat_SMFR_status_No_action (0) +#endif + + +// Value tables for @SMFR_CushionSupport_Stat signal + +#ifndef SMFR_CushionSupport_Stat_SMFR_status_Reserved +#define SMFR_CushionSupport_Stat_SMFR_status_Reserved (3) +#endif + +#ifndef SMFR_CushionSupport_Stat_SMFR_status_Decrease +#define SMFR_CushionSupport_Stat_SMFR_status_Decrease (2) +#endif + +#ifndef SMFR_CushionSupport_Stat_SMFR_status_Increase +#define SMFR_CushionSupport_Stat_SMFR_status_Increase (1) +#endif + +#ifndef SMFR_CushionSupport_Stat_SMFR_status_No_action +#define SMFR_CushionSupport_Stat_SMFR_status_No_action (0) +#endif + + +// Value tables for @SMFR_SeatVentilation_Stat signal + +#ifndef SMFR_SeatVentilation_Stat_SMFR_status_High_Power +#define SMFR_SeatVentilation_Stat_SMFR_status_High_Power (3) +#endif + +#ifndef SMFR_SeatVentilation_Stat_SMFR_status_Middle_Power +#define SMFR_SeatVentilation_Stat_SMFR_status_Middle_Power (2) +#endif + +#ifndef SMFR_SeatVentilation_Stat_SMFR_status_Low_Power +#define SMFR_SeatVentilation_Stat_SMFR_status_Low_Power (1) +#endif + +#ifndef SMFR_SeatVentilation_Stat_SMFR_status_No_action +#define SMFR_SeatVentilation_Stat_SMFR_status_No_action (0) +#endif + + +// Value tables for @SMFR_SeatVentBalance_Stat signal + +#ifndef SMFR_SeatVentBalance_Stat_SMFR_status_Backrest_100_Cushion_00_3 +#define SMFR_SeatVentBalance_Stat_SMFR_status_Backrest_100_Cushion_00_3 (7) +#endif + +#ifndef SMFR_SeatVentBalance_Stat_SMFR_status_Backrest_100_Cushion_33_2 +#define SMFR_SeatVentBalance_Stat_SMFR_status_Backrest_100_Cushion_33_2 (6) +#endif + +#ifndef SMFR_SeatVentBalance_Stat_SMFR_status_Backrest_100_Cushion_67_1 +#define SMFR_SeatVentBalance_Stat_SMFR_status_Backrest_100_Cushion_67_1 (5) +#endif + +#ifndef SMFR_SeatVentBalance_Stat_SMFR_status_Backrest_100_Cushion_100_0 +#define SMFR_SeatVentBalance_Stat_SMFR_status_Backrest_100_Cushion_100_0 (4) +#endif + +#ifndef SMFR_SeatVentBalance_Stat_SMFR_status_Backrest_67_Cushion_100_1 +#define SMFR_SeatVentBalance_Stat_SMFR_status_Backrest_67_Cushion_100_1 (3) +#endif + +#ifndef SMFR_SeatVentBalance_Stat_SMFR_status_Backrest_33_Cushion_100_2 +#define SMFR_SeatVentBalance_Stat_SMFR_status_Backrest_33_Cushion_100_2 (2) +#endif + +#ifndef SMFR_SeatVentBalance_Stat_SMFR_status_Backrest_00_Cushion_100_3 +#define SMFR_SeatVentBalance_Stat_SMFR_status_Backrest_00_Cushion_100_3 (1) +#endif + +#ifndef SMFR_SeatVentBalance_Stat_SMFR_status_No_action +#define SMFR_SeatVentBalance_Stat_SMFR_status_No_action (0) +#endif + + +// Value tables for @SMFR_Heating_Stat signal + +#ifndef SMFR_Heating_Stat_SMFR_status_High_Power +#define SMFR_Heating_Stat_SMFR_status_High_Power (3) +#endif + +#ifndef SMFR_Heating_Stat_SMFR_status_Middle_Power +#define SMFR_Heating_Stat_SMFR_status_Middle_Power (2) +#endif + +#ifndef SMFR_Heating_Stat_SMFR_status_Low_Power +#define SMFR_Heating_Stat_SMFR_status_Low_Power (1) +#endif + +#ifndef SMFR_Heating_Stat_SMFR_status_No_action +#define SMFR_Heating_Stat_SMFR_status_No_action (0) +#endif + + +// Value tables for @SMFR_HeatBalance_Stat signal + +#ifndef SMFR_HeatBalance_Stat_SMFR_status_Backrest_100_Cushion_00_3 +#define SMFR_HeatBalance_Stat_SMFR_status_Backrest_100_Cushion_00_3 (7) +#endif + +#ifndef SMFR_HeatBalance_Stat_SMFR_status_Backrest_100_Cushion_33_2 +#define SMFR_HeatBalance_Stat_SMFR_status_Backrest_100_Cushion_33_2 (6) +#endif + +#ifndef SMFR_HeatBalance_Stat_SMFR_status_Backrest_100_Cushion_67_1 +#define SMFR_HeatBalance_Stat_SMFR_status_Backrest_100_Cushion_67_1 (5) +#endif + +#ifndef SMFR_HeatBalance_Stat_SMFR_status_Backrest_100_Cushion_100_0 +#define SMFR_HeatBalance_Stat_SMFR_status_Backrest_100_Cushion_100_0 (4) +#endif + +#ifndef SMFR_HeatBalance_Stat_SMFR_status_Backrest_67_Cushion_100_1 +#define SMFR_HeatBalance_Stat_SMFR_status_Backrest_67_Cushion_100_1 (3) +#endif + +#ifndef SMFR_HeatBalance_Stat_SMFR_status_Backrest_33_Cushion_100_2 +#define SMFR_HeatBalance_Stat_SMFR_status_Backrest_33_Cushion_100_2 (2) +#endif + +#ifndef SMFR_HeatBalance_Stat_SMFR_status_Backrest_00_Cushion_100_3 +#define SMFR_HeatBalance_Stat_SMFR_status_Backrest_00_Cushion_100_3 (1) +#endif + +#ifndef SMFR_HeatBalance_Stat_SMFR_status_No_action +#define SMFR_HeatBalance_Stat_SMFR_status_No_action (0) +#endif + + +// Value tables for @SMFR_SeatMassage_Stat signal + +#ifndef SMFR_SeatMassage_Stat_SMFR_status_Reserved +#define SMFR_SeatMassage_Stat_SMFR_status_Reserved (3) +#endif + +#ifndef SMFR_SeatMassage_Stat_SMFR_status_Massage_ON +#define SMFR_SeatMassage_Stat_SMFR_status_Massage_ON (2) +#endif + +#ifndef SMFR_SeatMassage_Stat_SMFR_status_Massage_OFF +#define SMFR_SeatMassage_Stat_SMFR_status_Massage_OFF (1) +#endif + +#ifndef SMFR_SeatMassage_Stat_SMFR_status_No_Request +#define SMFR_SeatMassage_Stat_SMFR_status_No_Request (0) +#endif + + +// Value tables for @SMFR_MassageIntens_Stat signal + +#ifndef SMFR_MassageIntens_Stat_SMFR_status_High_power +#define SMFR_MassageIntens_Stat_SMFR_status_High_power (3) +#endif + +#ifndef SMFR_MassageIntens_Stat_SMFR_status_Middle_power +#define SMFR_MassageIntens_Stat_SMFR_status_Middle_power (2) +#endif + +#ifndef SMFR_MassageIntens_Stat_SMFR_status_Low_power +#define SMFR_MassageIntens_Stat_SMFR_status_Low_power (1) +#endif + +#ifndef SMFR_MassageIntens_Stat_SMFR_status_No_Request +#define SMFR_MassageIntens_Stat_SMFR_status_No_Request (0) +#endif + + +// Value tables for @SMFR_SeatMassageType_Stat signal + +#ifndef SMFR_SeatMassageType_Stat_SMFR_status_Type_7_Velvet +#define SMFR_SeatMassageType_Stat_SMFR_status_Type_7_Velvet (7) +#endif + +#ifndef SMFR_SeatMassageType_Stat_SMFR_status_Type_6_Sonnet +#define SMFR_SeatMassageType_Stat_SMFR_status_Type_6_Sonnet (6) +#endif + +#ifndef SMFR_SeatMassageType_Stat_SMFR_status_Type_5_Quantum +#define SMFR_SeatMassageType_Stat_SMFR_status_Type_5_Quantum (5) +#endif + +#ifndef SMFR_SeatMassageType_Stat_SMFR_status_Type_4_Cashmere +#define SMFR_SeatMassageType_Stat_SMFR_status_Type_4_Cashmere (4) +#endif + +#ifndef SMFR_SeatMassageType_Stat_SMFR_status_Type_3_Harmony +#define SMFR_SeatMassageType_Stat_SMFR_status_Type_3_Harmony (3) +#endif + +#ifndef SMFR_SeatMassageType_Stat_SMFR_status_Type_2_Orbital +#define SMFR_SeatMassageType_Stat_SMFR_status_Type_2_Orbital (2) +#endif + +#ifndef SMFR_SeatMassageType_Stat_SMFR_status_Type_1_Insight +#define SMFR_SeatMassageType_Stat_SMFR_status_Type_1_Insight (1) +#endif + +#ifndef SMFR_SeatMassageType_Stat_SMFR_status_No_action +#define SMFR_SeatMassageType_Stat_SMFR_status_No_action (0) +#endif + + +// Value tables for @SMFR_TabletPWR_Stat signal + +#ifndef SMFR_TabletPWR_Stat_SMFR_status_On +#define SMFR_TabletPWR_Stat_SMFR_status_On (1) +#endif + +#ifndef SMFR_TabletPWR_Stat_SMFR_status_Off +#define SMFR_TabletPWR_Stat_SMFR_status_Off (0) +#endif + + +// Value tables for @SMFR_CarpetHeat_Stat signal + +#ifndef SMFR_CarpetHeat_Stat_SMFR_status_Carpet_heating_is_active +#define SMFR_CarpetHeat_Stat_SMFR_status_Carpet_heating_is_active (1) +#endif + +#ifndef SMFR_CarpetHeat_Stat_SMFR_status_Carpet_heating_is_inactive +#define SMFR_CarpetHeat_Stat_SMFR_status_Carpet_heating_is_inactive (0) +#endif + + +// Value tables for @SMFR_ActiveSupport_Stat signal + +#ifndef SMFR_ActiveSupport_Stat_SMFR_status_Active +#define SMFR_ActiveSupport_Stat_SMFR_status_Active (1) +#endif + +#ifndef SMFR_ActiveSupport_Stat_SMFR_status_Inactive +#define SMFR_ActiveSupport_Stat_SMFR_status_Inactive (0) +#endif + + +// Value tables for @SMFR_BackrestMassageType_Stat signal + +#ifndef SMFR_BackrestMassageType_Stat_SMFR_status_Reserved +#define SMFR_BackrestMassageType_Stat_SMFR_status_Reserved (7) +#endif + +#ifndef SMFR_BackrestMassageType_Stat_SMFR_status_Reserved +#define SMFR_BackrestMassageType_Stat_SMFR_status_Reserved (6) +#endif + +#ifndef SMFR_BackrestMassageType_Stat_SMFR_status_Type_5_Elegy +#define SMFR_BackrestMassageType_Stat_SMFR_status_Type_5_Elegy (5) +#endif + +#ifndef SMFR_BackrestMassageType_Stat_SMFR_status_Type_4_Caprice +#define SMFR_BackrestMassageType_Stat_SMFR_status_Type_4_Caprice (4) +#endif + +#ifndef SMFR_BackrestMassageType_Stat_SMFR_status_Type_3_Pulse +#define SMFR_BackrestMassageType_Stat_SMFR_status_Type_3_Pulse (3) +#endif + +#ifndef SMFR_BackrestMassageType_Stat_SMFR_status_Type_2_Energy +#define SMFR_BackrestMassageType_Stat_SMFR_status_Type_2_Energy (2) +#endif + +#ifndef SMFR_BackrestMassageType_Stat_SMFR_status_Type_1_Synchrony +#define SMFR_BackrestMassageType_Stat_SMFR_status_Type_1_Synchrony (1) +#endif + +#ifndef SMFR_BackrestMassageType_Stat_SMFR_status_No_action +#define SMFR_BackrestMassageType_Stat_SMFR_status_No_action (0) +#endif + + +// Value tables for @SMFR_SeatControl_Stat signal + +#ifndef SMFR_SeatControl_Stat_SMFR_status_Seat_is_controlled_by_RR_user +#define SMFR_SeatControl_Stat_SMFR_status_Seat_is_controlled_by_RR_user (3) +#endif + +#ifndef SMFR_SeatControl_Stat_SMFR_status_Seat_is_controlled_by_FL_user +#define SMFR_SeatControl_Stat_SMFR_status_Seat_is_controlled_by_FL_user (2) +#endif + +#ifndef SMFR_SeatControl_Stat_SMFR_status_Seat_is_controlled_by_FR_user +#define SMFR_SeatControl_Stat_SMFR_status_Seat_is_controlled_by_FR_user (1) +#endif + +#ifndef SMFR_SeatControl_Stat_SMFR_status_Seat_is_not_controlled +#define SMFR_SeatControl_Stat_SMFR_status_Seat_is_not_controlled (0) +#endif + + +// Value tables for @SMFR_TimerMassage_Stat signal + +#ifndef SMFR_TimerMassage_Stat_SMFR_status_Reserved +#define SMFR_TimerMassage_Stat_SMFR_status_Reserved (7) +#endif + +#ifndef SMFR_TimerMassage_Stat_SMFR_status_Reserved +#define SMFR_TimerMassage_Stat_SMFR_status_Reserved (6) +#endif + +#ifndef SMFR_TimerMassage_Stat_SMFR_status__min +#define SMFR_TimerMassage_Stat_SMFR_status__min (5) +#endif + +#ifndef SMFR_TimerMassage_Stat_SMFR_status__min +#define SMFR_TimerMassage_Stat_SMFR_status__min (4) +#endif + +#ifndef SMFR_TimerMassage_Stat_SMFR_status__min +#define SMFR_TimerMassage_Stat_SMFR_status__min (3) +#endif + +#ifndef SMFR_TimerMassage_Stat_SMFR_status__min +#define SMFR_TimerMassage_Stat_SMFR_status__min (2) +#endif + +#ifndef SMFR_TimerMassage_Stat_SMFR_status__min +#define SMFR_TimerMassage_Stat_SMFR_status__min (1) +#endif + +#ifndef SMFR_TimerMassage_Stat_SMFR_status__min +#define SMFR_TimerMassage_Stat_SMFR_status__min (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Signal of pressing MM menu button on SMFR + // 1 : "MM menu activation button pressed" + // 0 : "MM menu activation button not pressed" + uint8_t SMFR_MMmenuActivBtn_Stat : 1; // Bits= 1 + + // FR seat height changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFR_SeatHeight_Stat : 2; // Bits= 2 + + // FR seat headrest height changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFR_HeadRestHeight_Stat : 2; // Bits= 2 + + // FR seat longitudinal changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFR_SeatLongitudinal_Stat : 2; // Bits= 2 + + // FR seat headrest height inclination changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFR_HeadRestHeightInclin_Stat : 2; // Bits= 2 + + // FR seat surface longitudinal changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFR_SurfaceLongitudinal_Stat : 2; // Bits= 2 + + // FR seat footrest changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFR_FootRestHeight_Stat : 2; // Bits= 2 + + // FR seat inclination status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFR_SeatInclination_Stat : 2; // Bits= 2 + + // FR seat footrest longitudinal changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFR_SeatLegSupportL_Stat : 2; // Bits= 2 + + // FR seat backrest inclination status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFR_BackRestInclin_Stat : 2; // Bits= 2 + + // FR seat lumbar support height status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFR_LumbarSupportHeight_Stat : 2; // Bits= 2 + + // FR seat backrest head inclination status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFR_BackRestHeadInclin_Stat : 2; // Bits= 2 + + // FR seat lumbar support depth status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFR_LumbarSupportDepth_Stat : 2; // Bits= 2 + + // FR seat backrest width status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFR_BackRestWidth_Stat : 2; // Bits= 2 + + // FR seat cushion support inclination status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFR_CushionSupport_Stat : 2; // Bits= 2 + + // FR seat ventilation status + // 3 : "High Power" + // 2 : "Middle Power" + // 1 : "Low Power" + // 0 : "No action" + uint8_t SMFR_SeatVentilation_Stat : 2; // Bits= 2 + + // FR seat ventilation balance status + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 00%, Cushion 100%: -3" + // 0 : "No action" + uint8_t SMFR_SeatVentBalance_Stat : 3; // Bits= 3 + + // FR seat heating status + // 3 : "High Power" + // 2 : "Middle Power" + // 1 : "Low Power" + // 0 : "No action" + uint8_t SMFR_Heating_Stat : 2; // Bits= 2 + + // FR seat heating balance status + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 00%, Cushion 100%: -3" + // 0 : "No action" + uint8_t SMFR_HeatBalance_Stat : 3; // Bits= 3 + + // FR seat massage status + // 3 : "Reserved" + // 2 : "Massage ON" + // 1 : "Massage OFF" + // 0 : "No Request" + uint8_t SMFR_SeatMassage_Stat : 2; // Bits= 2 + + // FR seat massage intencivity status + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "No Request" + uint8_t SMFR_MassageIntens_Stat : 2; // Bits= 2 + + // FR seat massage type status + // 7 : "Type 7 (Velvet)" + // 6 : "Type 6 (Sonnet)" + // 5 : "Type 5 (Quantum)" + // 4 : "Type 4 (Cashmere)" + // 3 : "Type 3 (Harmony)" + // 2 : "Type 2 (Orbital)" + // 1 : "Type 1 (Insight)" + // 0 : "No action" + uint8_t SMFR_SeatMassageType_Stat : 3; // Bits= 3 + + // Of DocSR+T Tablet power on/off status + // 1 : "On" + // 0 : "Off" + uint8_t SMFR_TabletPWR_Stat : 1; // Bits= 1 + + // Carpet heating status for front right zone + // 1 : "Carpet heating is active" + // 0 : "Carpet heating is inactive" + uint8_t SMFR_CarpetHeat_Stat : 1; // Bits= 1 + + // Active lateral status + // 1 : "Active" + // 0 : "Inactive" + uint8_t SMFR_ActiveSupport_Stat : 1; // Bits= 1 + + // Signal for backrest massage type (mode) + // (RL backrest massage type request) + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Type 5 (Elegy)" + // 4 : "Type 4 (Caprice)" + // 3 : "Type 3 (Pulse)" + // 2 : "Type 2 (Energy)" + // 1 : "Type 1 (Synchrony)" + // 0 : "No action" + uint8_t SMFR_BackrestMassageType_Stat : 3; // Bits= 3 + + // Signal, which inform about current master of seat travel function. + // 3 : "Seat is controlled by RR user" + // 2 : "Seat is controlled by FL user" + // 1 : "Seat is controlled by FR user" + // 0 : "Seat is not controlled" + uint8_t SMFR_SeatControl_Stat : 2; // Bits= 2 + + // FR seat massage timer status + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "5 min" + // 4 : "10 min" + // 3 : "15 min" + // 2 : "20 min" + // 1 : "25 min" + // 0 : "30 min" + uint8_t SMFR_TimerMassage_Stat : 3; // Bits= 3 + +#else + + // Signal of pressing MM menu button on SMFR + // 1 : "MM menu activation button pressed" + // 0 : "MM menu activation button not pressed" + uint8_t SMFR_MMmenuActivBtn_Stat; // Bits= 1 + + // FR seat height changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFR_SeatHeight_Stat; // Bits= 2 + + // FR seat headrest height changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFR_HeadRestHeight_Stat; // Bits= 2 + + // FR seat longitudinal changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFR_SeatLongitudinal_Stat; // Bits= 2 + + // FR seat headrest height inclination changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFR_HeadRestHeightInclin_Stat; // Bits= 2 + + // FR seat surface longitudinal changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFR_SurfaceLongitudinal_Stat; // Bits= 2 + + // FR seat footrest changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFR_FootRestHeight_Stat; // Bits= 2 + + // FR seat inclination status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFR_SeatInclination_Stat; // Bits= 2 + + // FR seat footrest longitudinal changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFR_SeatLegSupportL_Stat; // Bits= 2 + + // FR seat backrest inclination status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFR_BackRestInclin_Stat; // Bits= 2 + + // FR seat lumbar support height status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFR_LumbarSupportHeight_Stat; // Bits= 2 + + // FR seat backrest head inclination status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFR_BackRestHeadInclin_Stat; // Bits= 2 + + // FR seat lumbar support depth status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFR_LumbarSupportDepth_Stat; // Bits= 2 + + // FR seat backrest width status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFR_BackRestWidth_Stat; // Bits= 2 + + // FR seat cushion support inclination status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMFR_CushionSupport_Stat; // Bits= 2 + + // FR seat ventilation status + // 3 : "High Power" + // 2 : "Middle Power" + // 1 : "Low Power" + // 0 : "No action" + uint8_t SMFR_SeatVentilation_Stat; // Bits= 2 + + // FR seat ventilation balance status + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 00%, Cushion 100%: -3" + // 0 : "No action" + uint8_t SMFR_SeatVentBalance_Stat; // Bits= 3 + + // FR seat heating status + // 3 : "High Power" + // 2 : "Middle Power" + // 1 : "Low Power" + // 0 : "No action" + uint8_t SMFR_Heating_Stat; // Bits= 2 + + // FR seat heating balance status + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 00%, Cushion 100%: -3" + // 0 : "No action" + uint8_t SMFR_HeatBalance_Stat; // Bits= 3 + + // FR seat massage status + // 3 : "Reserved" + // 2 : "Massage ON" + // 1 : "Massage OFF" + // 0 : "No Request" + uint8_t SMFR_SeatMassage_Stat; // Bits= 2 + + // FR seat massage intencivity status + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "No Request" + uint8_t SMFR_MassageIntens_Stat; // Bits= 2 + + // FR seat massage type status + // 7 : "Type 7 (Velvet)" + // 6 : "Type 6 (Sonnet)" + // 5 : "Type 5 (Quantum)" + // 4 : "Type 4 (Cashmere)" + // 3 : "Type 3 (Harmony)" + // 2 : "Type 2 (Orbital)" + // 1 : "Type 1 (Insight)" + // 0 : "No action" + uint8_t SMFR_SeatMassageType_Stat; // Bits= 3 + + // Of DocSR+T Tablet power on/off status + // 1 : "On" + // 0 : "Off" + uint8_t SMFR_TabletPWR_Stat; // Bits= 1 + + // Carpet heating status for front right zone + // 1 : "Carpet heating is active" + // 0 : "Carpet heating is inactive" + uint8_t SMFR_CarpetHeat_Stat; // Bits= 1 + + // Active lateral status + // 1 : "Active" + // 0 : "Inactive" + uint8_t SMFR_ActiveSupport_Stat; // Bits= 1 + + // Signal for backrest massage type (mode) + // (RL backrest massage type request) + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Type 5 (Elegy)" + // 4 : "Type 4 (Caprice)" + // 3 : "Type 3 (Pulse)" + // 2 : "Type 2 (Energy)" + // 1 : "Type 1 (Synchrony)" + // 0 : "No action" + uint8_t SMFR_BackrestMassageType_Stat; // Bits= 3 + + // Signal, which inform about current master of seat travel function. + // 3 : "Seat is controlled by RR user" + // 2 : "Seat is controlled by FL user" + // 1 : "Seat is controlled by FR user" + // 0 : "Seat is not controlled" + uint8_t SMFR_SeatControl_Stat; // Bits= 2 + + // FR seat massage timer status + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "5 min" + // 4 : "10 min" + // 3 : "15 min" + // 2 : "20 min" + // 1 : "25 min" + // 0 : "30 min" + uint8_t SMFR_TimerMassage_Stat; // Bits= 3 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} SMFR_status_t; + +// def @SMRL_status CAN Message (1234 0x4d2) +#define SMRL_status_IDE (0U) +#define SMRL_status_DLC (8U) +#define SMRL_status_CANID (0x4d2U) +#define SMRL_status_CYC (250U) + +// Value tables for @SMRL_MMmenuActivBtn_Stat signal + +#ifndef SMRL_MMmenuActivBtn_Stat_SMRL_status_MM_menu_activation_button_pressed +#define SMRL_MMmenuActivBtn_Stat_SMRL_status_MM_menu_activation_button_pressed (1) +#endif + +#ifndef SMRL_MMmenuActivBtn_Stat_SMRL_status_MM_menu_activation_button_not_pressed +#define SMRL_MMmenuActivBtn_Stat_SMRL_status_MM_menu_activation_button_not_pressed (0) +#endif + + +// Value tables for @SMRL_SeatHeight_Stat signal + +#ifndef SMRL_SeatHeight_Stat_SMRL_status_Reserved +#define SMRL_SeatHeight_Stat_SMRL_status_Reserved (3) +#endif + +#ifndef SMRL_SeatHeight_Stat_SMRL_status_Decrease +#define SMRL_SeatHeight_Stat_SMRL_status_Decrease (2) +#endif + +#ifndef SMRL_SeatHeight_Stat_SMRL_status_Increase +#define SMRL_SeatHeight_Stat_SMRL_status_Increase (1) +#endif + +#ifndef SMRL_SeatHeight_Stat_SMRL_status_No_action +#define SMRL_SeatHeight_Stat_SMRL_status_No_action (0) +#endif + + +// Value tables for @SMRL_HeadRestHeight_Stat signal + +#ifndef SMRL_HeadRestHeight_Stat_SMRL_status_Reserved +#define SMRL_HeadRestHeight_Stat_SMRL_status_Reserved (3) +#endif + +#ifndef SMRL_HeadRestHeight_Stat_SMRL_status_Decrease +#define SMRL_HeadRestHeight_Stat_SMRL_status_Decrease (2) +#endif + +#ifndef SMRL_HeadRestHeight_Stat_SMRL_status_Increase +#define SMRL_HeadRestHeight_Stat_SMRL_status_Increase (1) +#endif + +#ifndef SMRL_HeadRestHeight_Stat_SMRL_status_No_action +#define SMRL_HeadRestHeight_Stat_SMRL_status_No_action (0) +#endif + + +// Value tables for @SMRL_SeatLongitudinal_Stat signal + +#ifndef SMRL_SeatLongitudinal_Stat_SMRL_status_Reserved +#define SMRL_SeatLongitudinal_Stat_SMRL_status_Reserved (3) +#endif + +#ifndef SMRL_SeatLongitudinal_Stat_SMRL_status_Decrease +#define SMRL_SeatLongitudinal_Stat_SMRL_status_Decrease (2) +#endif + +#ifndef SMRL_SeatLongitudinal_Stat_SMRL_status_Increase +#define SMRL_SeatLongitudinal_Stat_SMRL_status_Increase (1) +#endif + +#ifndef SMRL_SeatLongitudinal_Stat_SMRL_status_No_action +#define SMRL_SeatLongitudinal_Stat_SMRL_status_No_action (0) +#endif + + +// Value tables for @SMRL_HeadRestHeightInclin_Stat signal + +#ifndef SMRL_HeadRestHeightInclin_Stat_SMRL_status_Reserved +#define SMRL_HeadRestHeightInclin_Stat_SMRL_status_Reserved (3) +#endif + +#ifndef SMRL_HeadRestHeightInclin_Stat_SMRL_status_Decrease +#define SMRL_HeadRestHeightInclin_Stat_SMRL_status_Decrease (2) +#endif + +#ifndef SMRL_HeadRestHeightInclin_Stat_SMRL_status_Increase +#define SMRL_HeadRestHeightInclin_Stat_SMRL_status_Increase (1) +#endif + +#ifndef SMRL_HeadRestHeightInclin_Stat_SMRL_status_No_action +#define SMRL_HeadRestHeightInclin_Stat_SMRL_status_No_action (0) +#endif + + +// Value tables for @SMRL_SurfaceLongitudinal_Stat signal + +#ifndef SMRL_SurfaceLongitudinal_Stat_SMRL_status_Reserved +#define SMRL_SurfaceLongitudinal_Stat_SMRL_status_Reserved (3) +#endif + +#ifndef SMRL_SurfaceLongitudinal_Stat_SMRL_status_Decrease +#define SMRL_SurfaceLongitudinal_Stat_SMRL_status_Decrease (2) +#endif + +#ifndef SMRL_SurfaceLongitudinal_Stat_SMRL_status_Increase +#define SMRL_SurfaceLongitudinal_Stat_SMRL_status_Increase (1) +#endif + +#ifndef SMRL_SurfaceLongitudinal_Stat_SMRL_status_No_action +#define SMRL_SurfaceLongitudinal_Stat_SMRL_status_No_action (0) +#endif + + +// Value tables for @SMRL_SeatLegSupportH_Stat signal + +#ifndef SMRL_SeatLegSupportH_Stat_SMRL_status_Reserved +#define SMRL_SeatLegSupportH_Stat_SMRL_status_Reserved (3) +#endif + +#ifndef SMRL_SeatLegSupportH_Stat_SMRL_status_Decrease +#define SMRL_SeatLegSupportH_Stat_SMRL_status_Decrease (2) +#endif + +#ifndef SMRL_SeatLegSupportH_Stat_SMRL_status_Increase +#define SMRL_SeatLegSupportH_Stat_SMRL_status_Increase (1) +#endif + +#ifndef SMRL_SeatLegSupportH_Stat_SMRL_status_No_action +#define SMRL_SeatLegSupportH_Stat_SMRL_status_No_action (0) +#endif + + +// Value tables for @SMRL_SeatInclination_Stat signal + +#ifndef SMRL_SeatInclination_Stat_SMRL_status_Reserved +#define SMRL_SeatInclination_Stat_SMRL_status_Reserved (3) +#endif + +#ifndef SMRL_SeatInclination_Stat_SMRL_status_Decrease +#define SMRL_SeatInclination_Stat_SMRL_status_Decrease (2) +#endif + +#ifndef SMRL_SeatInclination_Stat_SMRL_status_Increase +#define SMRL_SeatInclination_Stat_SMRL_status_Increase (1) +#endif + +#ifndef SMRL_SeatInclination_Stat_SMRL_status_No_action +#define SMRL_SeatInclination_Stat_SMRL_status_No_action (0) +#endif + + +// Value tables for @SMRL_SeatLegSupportL_Stat signal + +#ifndef SMRL_SeatLegSupportL_Stat_SMRL_status_Reserved +#define SMRL_SeatLegSupportL_Stat_SMRL_status_Reserved (3) +#endif + +#ifndef SMRL_SeatLegSupportL_Stat_SMRL_status_Decrease +#define SMRL_SeatLegSupportL_Stat_SMRL_status_Decrease (2) +#endif + +#ifndef SMRL_SeatLegSupportL_Stat_SMRL_status_Increase +#define SMRL_SeatLegSupportL_Stat_SMRL_status_Increase (1) +#endif + +#ifndef SMRL_SeatLegSupportL_Stat_SMRL_status_No_action +#define SMRL_SeatLegSupportL_Stat_SMRL_status_No_action (0) +#endif + + +// Value tables for @SMRL_BackRestInclin_Stat signal + +#ifndef SMRL_BackRestInclin_Stat_SMRL_status_Reserved +#define SMRL_BackRestInclin_Stat_SMRL_status_Reserved (3) +#endif + +#ifndef SMRL_BackRestInclin_Stat_SMRL_status_Decrease +#define SMRL_BackRestInclin_Stat_SMRL_status_Decrease (2) +#endif + +#ifndef SMRL_BackRestInclin_Stat_SMRL_status_Increase +#define SMRL_BackRestInclin_Stat_SMRL_status_Increase (1) +#endif + +#ifndef SMRL_BackRestInclin_Stat_SMRL_status_No_action +#define SMRL_BackRestInclin_Stat_SMRL_status_No_action (0) +#endif + + +// Value tables for @SMRL_LumbarSupportHeight_Stat signal + +#ifndef SMRL_LumbarSupportHeight_Stat_SMRL_status_Reserved +#define SMRL_LumbarSupportHeight_Stat_SMRL_status_Reserved (3) +#endif + +#ifndef SMRL_LumbarSupportHeight_Stat_SMRL_status_Decrease +#define SMRL_LumbarSupportHeight_Stat_SMRL_status_Decrease (2) +#endif + +#ifndef SMRL_LumbarSupportHeight_Stat_SMRL_status_Increase +#define SMRL_LumbarSupportHeight_Stat_SMRL_status_Increase (1) +#endif + +#ifndef SMRL_LumbarSupportHeight_Stat_SMRL_status_No_action +#define SMRL_LumbarSupportHeight_Stat_SMRL_status_No_action (0) +#endif + + +// Value tables for @SMRL_BackRestHeadInclin_Stat signal + +#ifndef SMRL_BackRestHeadInclin_Stat_SMRL_status_Reserved +#define SMRL_BackRestHeadInclin_Stat_SMRL_status_Reserved (3) +#endif + +#ifndef SMRL_BackRestHeadInclin_Stat_SMRL_status_Decrease +#define SMRL_BackRestHeadInclin_Stat_SMRL_status_Decrease (2) +#endif + +#ifndef SMRL_BackRestHeadInclin_Stat_SMRL_status_Increase +#define SMRL_BackRestHeadInclin_Stat_SMRL_status_Increase (1) +#endif + +#ifndef SMRL_BackRestHeadInclin_Stat_SMRL_status_No_action +#define SMRL_BackRestHeadInclin_Stat_SMRL_status_No_action (0) +#endif + + +// Value tables for @SMRL_LumbarSupportDepth_Stat signal + +#ifndef SMRL_LumbarSupportDepth_Stat_SMRL_status_Reserved +#define SMRL_LumbarSupportDepth_Stat_SMRL_status_Reserved (3) +#endif + +#ifndef SMRL_LumbarSupportDepth_Stat_SMRL_status_Decrease +#define SMRL_LumbarSupportDepth_Stat_SMRL_status_Decrease (2) +#endif + +#ifndef SMRL_LumbarSupportDepth_Stat_SMRL_status_Increase +#define SMRL_LumbarSupportDepth_Stat_SMRL_status_Increase (1) +#endif + +#ifndef SMRL_LumbarSupportDepth_Stat_SMRL_status_No_action +#define SMRL_LumbarSupportDepth_Stat_SMRL_status_No_action (0) +#endif + + +// Value tables for @SMRL_BackRestWidth_Stat signal + +#ifndef SMRL_BackRestWidth_Stat_SMRL_status_Reserved +#define SMRL_BackRestWidth_Stat_SMRL_status_Reserved (3) +#endif + +#ifndef SMRL_BackRestWidth_Stat_SMRL_status_Decrease +#define SMRL_BackRestWidth_Stat_SMRL_status_Decrease (2) +#endif + +#ifndef SMRL_BackRestWidth_Stat_SMRL_status_Increase +#define SMRL_BackRestWidth_Stat_SMRL_status_Increase (1) +#endif + +#ifndef SMRL_BackRestWidth_Stat_SMRL_status_No_action +#define SMRL_BackRestWidth_Stat_SMRL_status_No_action (0) +#endif + + +// Value tables for @SMRL_CushionSuppor_Stat signal + +#ifndef SMRL_CushionSuppor_Stat_SMRL_status_Reserved +#define SMRL_CushionSuppor_Stat_SMRL_status_Reserved (3) +#endif + +#ifndef SMRL_CushionSuppor_Stat_SMRL_status_Decrease +#define SMRL_CushionSuppor_Stat_SMRL_status_Decrease (2) +#endif + +#ifndef SMRL_CushionSuppor_Stat_SMRL_status_Increase +#define SMRL_CushionSuppor_Stat_SMRL_status_Increase (1) +#endif + +#ifndef SMRL_CushionSuppor_Stat_SMRL_status_No_action +#define SMRL_CushionSuppor_Stat_SMRL_status_No_action (0) +#endif + + +// Value tables for @SMRL_SeatVentilation_Stat signal + +#ifndef SMRL_SeatVentilation_Stat_SMRL_status_High_Power +#define SMRL_SeatVentilation_Stat_SMRL_status_High_Power (3) +#endif + +#ifndef SMRL_SeatVentilation_Stat_SMRL_status_Middle_Power +#define SMRL_SeatVentilation_Stat_SMRL_status_Middle_Power (2) +#endif + +#ifndef SMRL_SeatVentilation_Stat_SMRL_status_Low_Power +#define SMRL_SeatVentilation_Stat_SMRL_status_Low_Power (1) +#endif + +#ifndef SMRL_SeatVentilation_Stat_SMRL_status_Off +#define SMRL_SeatVentilation_Stat_SMRL_status_Off (0) +#endif + + +// Value tables for @SMRL_SeatVentBalance_Stat signal + +#ifndef SMRL_SeatVentBalance_Stat_SMRL_status_Backrest_100_Cushion_00_3 +#define SMRL_SeatVentBalance_Stat_SMRL_status_Backrest_100_Cushion_00_3 (7) +#endif + +#ifndef SMRL_SeatVentBalance_Stat_SMRL_status_Backrest_100_Cushion_33_2 +#define SMRL_SeatVentBalance_Stat_SMRL_status_Backrest_100_Cushion_33_2 (6) +#endif + +#ifndef SMRL_SeatVentBalance_Stat_SMRL_status_Backrest_100_Cushion_67_1 +#define SMRL_SeatVentBalance_Stat_SMRL_status_Backrest_100_Cushion_67_1 (5) +#endif + +#ifndef SMRL_SeatVentBalance_Stat_SMRL_status_Backrest_100_Cushion_100_0 +#define SMRL_SeatVentBalance_Stat_SMRL_status_Backrest_100_Cushion_100_0 (4) +#endif + +#ifndef SMRL_SeatVentBalance_Stat_SMRL_status_Backrest_67_Cushion_100_1 +#define SMRL_SeatVentBalance_Stat_SMRL_status_Backrest_67_Cushion_100_1 (3) +#endif + +#ifndef SMRL_SeatVentBalance_Stat_SMRL_status_Backrest_33_Cushion_100_2 +#define SMRL_SeatVentBalance_Stat_SMRL_status_Backrest_33_Cushion_100_2 (2) +#endif + +#ifndef SMRL_SeatVentBalance_Stat_SMRL_status_Backrest_00_Cushion_100_3 +#define SMRL_SeatVentBalance_Stat_SMRL_status_Backrest_00_Cushion_100_3 (1) +#endif + +#ifndef SMRL_SeatVentBalance_Stat_SMRL_status_No_action +#define SMRL_SeatVentBalance_Stat_SMRL_status_No_action (0) +#endif + + +// Value tables for @SMRL_Heating_Stat signal + +#ifndef SMRL_Heating_Stat_SMRL_status_High_Power +#define SMRL_Heating_Stat_SMRL_status_High_Power (3) +#endif + +#ifndef SMRL_Heating_Stat_SMRL_status_Middle_Power +#define SMRL_Heating_Stat_SMRL_status_Middle_Power (2) +#endif + +#ifndef SMRL_Heating_Stat_SMRL_status_Low_Power +#define SMRL_Heating_Stat_SMRL_status_Low_Power (1) +#endif + +#ifndef SMRL_Heating_Stat_SMRL_status_Off +#define SMRL_Heating_Stat_SMRL_status_Off (0) +#endif + + +// Value tables for @SMRL_HeatBalance_Stat signal + +#ifndef SMRL_HeatBalance_Stat_SMRL_status_Backrest_100_Cushion_00_3 +#define SMRL_HeatBalance_Stat_SMRL_status_Backrest_100_Cushion_00_3 (7) +#endif + +#ifndef SMRL_HeatBalance_Stat_SMRL_status_Backrest_100_Cushion_33_2 +#define SMRL_HeatBalance_Stat_SMRL_status_Backrest_100_Cushion_33_2 (6) +#endif + +#ifndef SMRL_HeatBalance_Stat_SMRL_status_Backrest_100_Cushion_67_1 +#define SMRL_HeatBalance_Stat_SMRL_status_Backrest_100_Cushion_67_1 (5) +#endif + +#ifndef SMRL_HeatBalance_Stat_SMRL_status_Backrest_100_Cushion_100_0 +#define SMRL_HeatBalance_Stat_SMRL_status_Backrest_100_Cushion_100_0 (4) +#endif + +#ifndef SMRL_HeatBalance_Stat_SMRL_status_Backrest_67_Cushion_100_1 +#define SMRL_HeatBalance_Stat_SMRL_status_Backrest_67_Cushion_100_1 (3) +#endif + +#ifndef SMRL_HeatBalance_Stat_SMRL_status_Backrest_33_Cushion_100_2 +#define SMRL_HeatBalance_Stat_SMRL_status_Backrest_33_Cushion_100_2 (2) +#endif + +#ifndef SMRL_HeatBalance_Stat_SMRL_status_Backrest_00_Cushion_100_3 +#define SMRL_HeatBalance_Stat_SMRL_status_Backrest_00_Cushion_100_3 (1) +#endif + +#ifndef SMRL_HeatBalance_Stat_SMRL_status_No_action +#define SMRL_HeatBalance_Stat_SMRL_status_No_action (0) +#endif + + +// Value tables for @SMRL_SeatMassage_Stat signal + +#ifndef SMRL_SeatMassage_Stat_SMRL_status_Reserved +#define SMRL_SeatMassage_Stat_SMRL_status_Reserved (3) +#endif + +#ifndef SMRL_SeatMassage_Stat_SMRL_status_Massage_ON +#define SMRL_SeatMassage_Stat_SMRL_status_Massage_ON (2) +#endif + +#ifndef SMRL_SeatMassage_Stat_SMRL_status_Massage_OFF +#define SMRL_SeatMassage_Stat_SMRL_status_Massage_OFF (1) +#endif + +#ifndef SMRL_SeatMassage_Stat_SMRL_status_No_Request +#define SMRL_SeatMassage_Stat_SMRL_status_No_Request (0) +#endif + + +// Value tables for @SMRL_MassageIntens_Stat signal + +#ifndef SMRL_MassageIntens_Stat_SMRL_status_High_power +#define SMRL_MassageIntens_Stat_SMRL_status_High_power (3) +#endif + +#ifndef SMRL_MassageIntens_Stat_SMRL_status_Middle_power +#define SMRL_MassageIntens_Stat_SMRL_status_Middle_power (2) +#endif + +#ifndef SMRL_MassageIntens_Stat_SMRL_status_Low_power +#define SMRL_MassageIntens_Stat_SMRL_status_Low_power (1) +#endif + +#ifndef SMRL_MassageIntens_Stat_SMRL_status_Off +#define SMRL_MassageIntens_Stat_SMRL_status_Off (0) +#endif + + +// Value tables for @SMRL_SeatMassageType_Stat signal + +#ifndef SMRL_SeatMassageType_Stat_SMRL_status_Type_7_Velvet +#define SMRL_SeatMassageType_Stat_SMRL_status_Type_7_Velvet (7) +#endif + +#ifndef SMRL_SeatMassageType_Stat_SMRL_status_Type_6_Sonnet +#define SMRL_SeatMassageType_Stat_SMRL_status_Type_6_Sonnet (6) +#endif + +#ifndef SMRL_SeatMassageType_Stat_SMRL_status_Type_5_Quantum +#define SMRL_SeatMassageType_Stat_SMRL_status_Type_5_Quantum (5) +#endif + +#ifndef SMRL_SeatMassageType_Stat_SMRL_status_Type_4_Cashmere +#define SMRL_SeatMassageType_Stat_SMRL_status_Type_4_Cashmere (4) +#endif + +#ifndef SMRL_SeatMassageType_Stat_SMRL_status_Type_3_Harmony +#define SMRL_SeatMassageType_Stat_SMRL_status_Type_3_Harmony (3) +#endif + +#ifndef SMRL_SeatMassageType_Stat_SMRL_status_Type_2_Orbital +#define SMRL_SeatMassageType_Stat_SMRL_status_Type_2_Orbital (2) +#endif + +#ifndef SMRL_SeatMassageType_Stat_SMRL_status_Type_1_Insight +#define SMRL_SeatMassageType_Stat_SMRL_status_Type_1_Insight (1) +#endif + +#ifndef SMRL_SeatMassageType_Stat_SMRL_status_No_action +#define SMRL_SeatMassageType_Stat_SMRL_status_No_action (0) +#endif + + +// Value tables for @SMRL_MoreComfort_Stat signal + +#ifndef SMRL_MoreComfort_Stat_SMRL_status_Active +#define SMRL_MoreComfort_Stat_SMRL_status_Active (1) +#endif + +#ifndef SMRL_MoreComfort_Stat_SMRL_status_Inactive +#define SMRL_MoreComfort_Stat_SMRL_status_Inactive (0) +#endif + + +// Value tables for @SMRL_CarpetHeat_Stat signal + +#ifndef SMRL_CarpetHeat_Stat_SMRL_status_Carpet_heating_is_active +#define SMRL_CarpetHeat_Stat_SMRL_status_Carpet_heating_is_active (1) +#endif + +#ifndef SMRL_CarpetHeat_Stat_SMRL_status_Carpet_heating_is_inactive +#define SMRL_CarpetHeat_Stat_SMRL_status_Carpet_heating_is_inactive (0) +#endif + + +// Value tables for @SMRL_ActiveSupport_Stat signal + +#ifndef SMRL_ActiveSupport_Stat_SMRL_status_Active +#define SMRL_ActiveSupport_Stat_SMRL_status_Active (1) +#endif + +#ifndef SMRL_ActiveSupport_Stat_SMRL_status_Inactive +#define SMRL_ActiveSupport_Stat_SMRL_status_Inactive (0) +#endif + + +// Value tables for @SMRL_BackrestMassageType_Stat signal + +#ifndef SMRL_BackrestMassageType_Stat_SMRL_status_Reserved +#define SMRL_BackrestMassageType_Stat_SMRL_status_Reserved (7) +#endif + +#ifndef SMRL_BackrestMassageType_Stat_SMRL_status_Reserved +#define SMRL_BackrestMassageType_Stat_SMRL_status_Reserved (6) +#endif + +#ifndef SMRL_BackrestMassageType_Stat_SMRL_status_Type_5_Elegy +#define SMRL_BackrestMassageType_Stat_SMRL_status_Type_5_Elegy (5) +#endif + +#ifndef SMRL_BackrestMassageType_Stat_SMRL_status_Type_4_Caprice +#define SMRL_BackrestMassageType_Stat_SMRL_status_Type_4_Caprice (4) +#endif + +#ifndef SMRL_BackrestMassageType_Stat_SMRL_status_Type_3_Pulse +#define SMRL_BackrestMassageType_Stat_SMRL_status_Type_3_Pulse (3) +#endif + +#ifndef SMRL_BackrestMassageType_Stat_SMRL_status_Type_2_Energy +#define SMRL_BackrestMassageType_Stat_SMRL_status_Type_2_Energy (2) +#endif + +#ifndef SMRL_BackrestMassageType_Stat_SMRL_status_Type_1_Synchrony +#define SMRL_BackrestMassageType_Stat_SMRL_status_Type_1_Synchrony (1) +#endif + +#ifndef SMRL_BackrestMassageType_Stat_SMRL_status_No_action +#define SMRL_BackrestMassageType_Stat_SMRL_status_No_action (0) +#endif + + +// Value tables for @SMRL_TimerMassage_Stat signal + +#ifndef SMRL_TimerMassage_Stat_SMRL_status_Reserved +#define SMRL_TimerMassage_Stat_SMRL_status_Reserved (7) +#endif + +#ifndef SMRL_TimerMassage_Stat_SMRL_status_Reserved +#define SMRL_TimerMassage_Stat_SMRL_status_Reserved (6) +#endif + +#ifndef SMRL_TimerMassage_Stat_SMRL_status__min +#define SMRL_TimerMassage_Stat_SMRL_status__min (5) +#endif + +#ifndef SMRL_TimerMassage_Stat_SMRL_status__min +#define SMRL_TimerMassage_Stat_SMRL_status__min (4) +#endif + +#ifndef SMRL_TimerMassage_Stat_SMRL_status__min +#define SMRL_TimerMassage_Stat_SMRL_status__min (3) +#endif + +#ifndef SMRL_TimerMassage_Stat_SMRL_status__min +#define SMRL_TimerMassage_Stat_SMRL_status__min (2) +#endif + +#ifndef SMRL_TimerMassage_Stat_SMRL_status__min +#define SMRL_TimerMassage_Stat_SMRL_status__min (1) +#endif + +#ifndef SMRL_TimerMassage_Stat_SMRL_status__min +#define SMRL_TimerMassage_Stat_SMRL_status__min (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Signal of pressing MM menu button on SMRL + // 1 : "MM menu activation button pressed" + // 0 : "MM menu activation button not pressed" + uint8_t SMRL_MMmenuActivBtn_Stat : 1; // Bits= 1 + + // RL seat height changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRL_SeatHeight_Stat : 2; // Bits= 2 + + // RL seat headrest height changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRL_HeadRestHeight_Stat : 2; // Bits= 2 + + // RL seat longitudinal changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRL_SeatLongitudinal_Stat : 2; // Bits= 2 + + // RL seat headrest height inclination changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRL_HeadRestHeightInclin_Stat : 2; // Bits= 2 + + // RL seat surface longitudinal changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRL_SurfaceLongitudinal_Stat : 2; // Bits= 2 + + // RL seat footrest changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRL_SeatLegSupportH_Stat : 2; // Bits= 2 + + // RL seat inclination status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRL_SeatInclination_Stat : 2; // Bits= 2 + + // RL seat footrest longitudinal changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRL_SeatLegSupportL_Stat : 2; // Bits= 2 + + // RL seat backrest inclination status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRL_BackRestInclin_Stat : 2; // Bits= 2 + + // RL seat lumbar support height status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRL_LumbarSupportHeight_Stat : 2; // Bits= 2 + + // RL seat backrest head inclination status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRL_BackRestHeadInclin_Stat : 2; // Bits= 2 + + // RL seat lumbar support depth status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRL_LumbarSupportDepth_Stat : 2; // Bits= 2 + + // RL seat backrest width status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRL_BackRestWidth_Stat : 2; // Bits= 2 + + // RL seat cushion support inclination status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRL_CushionSuppor_Stat : 2; // Bits= 2 + + // RL seat ventilation status + // 3 : "High Power" + // 2 : "Middle Power" + // 1 : "Low Power" + // 0 : "Off" + uint8_t SMRL_SeatVentilation_Stat : 2; // Bits= 2 + + // RL seat ventilation balance status + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 00%, Cushion 100%: -3" + // 0 : "No action" + uint8_t SMRL_SeatVentBalance_Stat : 3; // Bits= 3 + + // RL seat heating status + // 3 : "High Power" + // 2 : "Middle Power" + // 1 : "Low Power" + // 0 : "Off" + uint8_t SMRL_Heating_Stat : 2; // Bits= 2 + + // RL seat heating balance status + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 00%, Cushion 100%: -3" + // 0 : "No action" + uint8_t SMRL_HeatBalance_Stat : 3; // Bits= 3 + + // RL seat massage status + // 3 : "Reserved" + // 2 : "Massage ON" + // 1 : "Massage OFF" + // 0 : "No Request" + uint8_t SMRL_SeatMassage_Stat : 2; // Bits= 2 + + // RL seat massage intencivity status + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "Off" + uint8_t SMRL_MassageIntens_Stat : 2; // Bits= 2 + + // RL seat massage type status + // 7 : "Type 7 (Velvet)" + // 6 : "Type 6 (Sonnet)" + // 5 : "Type 5 (Quantum)" + // 4 : "Type 4 (Cashmere)" + // 3 : "Type 3 (Harmony)" + // 2 : "Type 2 (Orbital)" + // 1 : "Type 1 (Insight)" + // 0 : "No action" + uint8_t SMRL_SeatMassageType_Stat : 3; // Bits= 3 + + // RL seat comfort mode status + // 1 : "Active" + // 0 : "Inactive" + uint8_t SMRL_MoreComfort_Stat : 1; // Bits= 1 + + // Carpet heating status for rear left zone + // 1 : "Carpet heating is active" + // 0 : "Carpet heating is inactive" + uint8_t SMRL_CarpetHeat_Stat : 1; // Bits= 1 + + // Active lateral status + // 1 : "Active" + // 0 : "Inactive" + uint8_t SMRL_ActiveSupport_Stat : 1; // Bits= 1 + + // Signal for backrest massage type (mode) + // (RL backrest massage type request) + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Type 5 (Elegy)" + // 4 : "Type 4 (Caprice)" + // 3 : "Type 3 (Pulse)" + // 2 : "Type 2 (Energy)" + // 1 : "Type 1 (Synchrony)" + // 0 : "No action" + uint8_t SMRL_BackrestMassageType_Stat : 3; // Bits= 3 + + // RL seat massage timer status + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "5 min" + // 4 : "10 min" + // 3 : "15 min" + // 2 : "20 min" + // 1 : "25 min" + // 0 : "30 min" + uint8_t SMRL_TimerMassage_Stat : 3; // Bits= 3 + +#else + + // Signal of pressing MM menu button on SMRL + // 1 : "MM menu activation button pressed" + // 0 : "MM menu activation button not pressed" + uint8_t SMRL_MMmenuActivBtn_Stat; // Bits= 1 + + // RL seat height changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRL_SeatHeight_Stat; // Bits= 2 + + // RL seat headrest height changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRL_HeadRestHeight_Stat; // Bits= 2 + + // RL seat longitudinal changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRL_SeatLongitudinal_Stat; // Bits= 2 + + // RL seat headrest height inclination changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRL_HeadRestHeightInclin_Stat; // Bits= 2 + + // RL seat surface longitudinal changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRL_SurfaceLongitudinal_Stat; // Bits= 2 + + // RL seat footrest changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRL_SeatLegSupportH_Stat; // Bits= 2 + + // RL seat inclination status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRL_SeatInclination_Stat; // Bits= 2 + + // RL seat footrest longitudinal changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRL_SeatLegSupportL_Stat; // Bits= 2 + + // RL seat backrest inclination status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRL_BackRestInclin_Stat; // Bits= 2 + + // RL seat lumbar support height status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRL_LumbarSupportHeight_Stat; // Bits= 2 + + // RL seat backrest head inclination status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRL_BackRestHeadInclin_Stat; // Bits= 2 + + // RL seat lumbar support depth status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRL_LumbarSupportDepth_Stat; // Bits= 2 + + // RL seat backrest width status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRL_BackRestWidth_Stat; // Bits= 2 + + // RL seat cushion support inclination status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRL_CushionSuppor_Stat; // Bits= 2 + + // RL seat ventilation status + // 3 : "High Power" + // 2 : "Middle Power" + // 1 : "Low Power" + // 0 : "Off" + uint8_t SMRL_SeatVentilation_Stat; // Bits= 2 + + // RL seat ventilation balance status + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 00%, Cushion 100%: -3" + // 0 : "No action" + uint8_t SMRL_SeatVentBalance_Stat; // Bits= 3 + + // RL seat heating status + // 3 : "High Power" + // 2 : "Middle Power" + // 1 : "Low Power" + // 0 : "Off" + uint8_t SMRL_Heating_Stat; // Bits= 2 + + // RL seat heating balance status + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 00%, Cushion 100%: -3" + // 0 : "No action" + uint8_t SMRL_HeatBalance_Stat; // Bits= 3 + + // RL seat massage status + // 3 : "Reserved" + // 2 : "Massage ON" + // 1 : "Massage OFF" + // 0 : "No Request" + uint8_t SMRL_SeatMassage_Stat; // Bits= 2 + + // RL seat massage intencivity status + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "Off" + uint8_t SMRL_MassageIntens_Stat; // Bits= 2 + + // RL seat massage type status + // 7 : "Type 7 (Velvet)" + // 6 : "Type 6 (Sonnet)" + // 5 : "Type 5 (Quantum)" + // 4 : "Type 4 (Cashmere)" + // 3 : "Type 3 (Harmony)" + // 2 : "Type 2 (Orbital)" + // 1 : "Type 1 (Insight)" + // 0 : "No action" + uint8_t SMRL_SeatMassageType_Stat; // Bits= 3 + + // RL seat comfort mode status + // 1 : "Active" + // 0 : "Inactive" + uint8_t SMRL_MoreComfort_Stat; // Bits= 1 + + // Carpet heating status for rear left zone + // 1 : "Carpet heating is active" + // 0 : "Carpet heating is inactive" + uint8_t SMRL_CarpetHeat_Stat; // Bits= 1 + + // Active lateral status + // 1 : "Active" + // 0 : "Inactive" + uint8_t SMRL_ActiveSupport_Stat; // Bits= 1 + + // Signal for backrest massage type (mode) + // (RL backrest massage type request) + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Type 5 (Elegy)" + // 4 : "Type 4 (Caprice)" + // 3 : "Type 3 (Pulse)" + // 2 : "Type 2 (Energy)" + // 1 : "Type 1 (Synchrony)" + // 0 : "No action" + uint8_t SMRL_BackrestMassageType_Stat; // Bits= 3 + + // RL seat massage timer status + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "5 min" + // 4 : "10 min" + // 3 : "15 min" + // 2 : "20 min" + // 1 : "25 min" + // 0 : "30 min" + uint8_t SMRL_TimerMassage_Stat; // Bits= 3 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} SMRL_status_t; + +// def @SMRR_status CAN Message (1235 0x4d3) +#define SMRR_status_IDE (0U) +#define SMRR_status_DLC (8U) +#define SMRR_status_CANID (0x4d3U) +#define SMRR_status_CYC (250U) + +// Value tables for @SMRR_MMmenuActivBtn_Stat signal + +#ifndef SMRR_MMmenuActivBtn_Stat_SMRR_status_MM_menu_activation_button_pressed +#define SMRR_MMmenuActivBtn_Stat_SMRR_status_MM_menu_activation_button_pressed (1) +#endif + +#ifndef SMRR_MMmenuActivBtn_Stat_SMRR_status_MM_menu_activation_button_not_pressed +#define SMRR_MMmenuActivBtn_Stat_SMRR_status_MM_menu_activation_button_not_pressed (0) +#endif + + +// Value tables for @SMRR_SeatHeight_Stat signal + +#ifndef SMRR_SeatHeight_Stat_SMRR_status_Reserved +#define SMRR_SeatHeight_Stat_SMRR_status_Reserved (3) +#endif + +#ifndef SMRR_SeatHeight_Stat_SMRR_status_Decrease +#define SMRR_SeatHeight_Stat_SMRR_status_Decrease (2) +#endif + +#ifndef SMRR_SeatHeight_Stat_SMRR_status_Increase +#define SMRR_SeatHeight_Stat_SMRR_status_Increase (1) +#endif + +#ifndef SMRR_SeatHeight_Stat_SMRR_status_No_action +#define SMRR_SeatHeight_Stat_SMRR_status_No_action (0) +#endif + + +// Value tables for @SMRR_HeadRestHeight_Stat signal + +#ifndef SMRR_HeadRestHeight_Stat_SMRR_status_Reserved +#define SMRR_HeadRestHeight_Stat_SMRR_status_Reserved (3) +#endif + +#ifndef SMRR_HeadRestHeight_Stat_SMRR_status_Decrease +#define SMRR_HeadRestHeight_Stat_SMRR_status_Decrease (2) +#endif + +#ifndef SMRR_HeadRestHeight_Stat_SMRR_status_Increase +#define SMRR_HeadRestHeight_Stat_SMRR_status_Increase (1) +#endif + +#ifndef SMRR_HeadRestHeight_Stat_SMRR_status_No_action +#define SMRR_HeadRestHeight_Stat_SMRR_status_No_action (0) +#endif + + +// Value tables for @SMRR_SeatLongitudinal_Stat signal + +#ifndef SMRR_SeatLongitudinal_Stat_SMRR_status_Reserved +#define SMRR_SeatLongitudinal_Stat_SMRR_status_Reserved (3) +#endif + +#ifndef SMRR_SeatLongitudinal_Stat_SMRR_status_Decrease +#define SMRR_SeatLongitudinal_Stat_SMRR_status_Decrease (2) +#endif + +#ifndef SMRR_SeatLongitudinal_Stat_SMRR_status_Increase +#define SMRR_SeatLongitudinal_Stat_SMRR_status_Increase (1) +#endif + +#ifndef SMRR_SeatLongitudinal_Stat_SMRR_status_No_action +#define SMRR_SeatLongitudinal_Stat_SMRR_status_No_action (0) +#endif + + +// Value tables for @SMRR_HeadRestHeightInclin_Stat signal + +#ifndef SMRR_HeadRestHeightInclin_Stat_SMRR_status_Reserved +#define SMRR_HeadRestHeightInclin_Stat_SMRR_status_Reserved (3) +#endif + +#ifndef SMRR_HeadRestHeightInclin_Stat_SMRR_status_Decrease +#define SMRR_HeadRestHeightInclin_Stat_SMRR_status_Decrease (2) +#endif + +#ifndef SMRR_HeadRestHeightInclin_Stat_SMRR_status_Increase +#define SMRR_HeadRestHeightInclin_Stat_SMRR_status_Increase (1) +#endif + +#ifndef SMRR_HeadRestHeightInclin_Stat_SMRR_status_No_action +#define SMRR_HeadRestHeightInclin_Stat_SMRR_status_No_action (0) +#endif + + +// Value tables for @SMRR_SurfaceLongitudinal_Stat signal + +#ifndef SMRR_SurfaceLongitudinal_Stat_SMRR_status_Reserved +#define SMRR_SurfaceLongitudinal_Stat_SMRR_status_Reserved (3) +#endif + +#ifndef SMRR_SurfaceLongitudinal_Stat_SMRR_status_Decrease +#define SMRR_SurfaceLongitudinal_Stat_SMRR_status_Decrease (2) +#endif + +#ifndef SMRR_SurfaceLongitudinal_Stat_SMRR_status_Increase +#define SMRR_SurfaceLongitudinal_Stat_SMRR_status_Increase (1) +#endif + +#ifndef SMRR_SurfaceLongitudinal_Stat_SMRR_status_No_action +#define SMRR_SurfaceLongitudinal_Stat_SMRR_status_No_action (0) +#endif + + +// Value tables for @SMRR_SeatLegSupportH_Stat signal + +#ifndef SMRR_SeatLegSupportH_Stat_SMRR_status_Reserved +#define SMRR_SeatLegSupportH_Stat_SMRR_status_Reserved (3) +#endif + +#ifndef SMRR_SeatLegSupportH_Stat_SMRR_status_Decrease +#define SMRR_SeatLegSupportH_Stat_SMRR_status_Decrease (2) +#endif + +#ifndef SMRR_SeatLegSupportH_Stat_SMRR_status_Increase +#define SMRR_SeatLegSupportH_Stat_SMRR_status_Increase (1) +#endif + +#ifndef SMRR_SeatLegSupportH_Stat_SMRR_status_No_action +#define SMRR_SeatLegSupportH_Stat_SMRR_status_No_action (0) +#endif + + +// Value tables for @SMRR_SeatInclination_Stat signal + +#ifndef SMRR_SeatInclination_Stat_SMRR_status_Reserved +#define SMRR_SeatInclination_Stat_SMRR_status_Reserved (3) +#endif + +#ifndef SMRR_SeatInclination_Stat_SMRR_status_Decrease +#define SMRR_SeatInclination_Stat_SMRR_status_Decrease (2) +#endif + +#ifndef SMRR_SeatInclination_Stat_SMRR_status_Increase +#define SMRR_SeatInclination_Stat_SMRR_status_Increase (1) +#endif + +#ifndef SMRR_SeatInclination_Stat_SMRR_status_No_action +#define SMRR_SeatInclination_Stat_SMRR_status_No_action (0) +#endif + + +// Value tables for @SMRR_SeatLegSupportL_Stat signal + +#ifndef SMRR_SeatLegSupportL_Stat_SMRR_status_Reserved +#define SMRR_SeatLegSupportL_Stat_SMRR_status_Reserved (3) +#endif + +#ifndef SMRR_SeatLegSupportL_Stat_SMRR_status_Decrease +#define SMRR_SeatLegSupportL_Stat_SMRR_status_Decrease (2) +#endif + +#ifndef SMRR_SeatLegSupportL_Stat_SMRR_status_Increase +#define SMRR_SeatLegSupportL_Stat_SMRR_status_Increase (1) +#endif + +#ifndef SMRR_SeatLegSupportL_Stat_SMRR_status_No_action +#define SMRR_SeatLegSupportL_Stat_SMRR_status_No_action (0) +#endif + + +// Value tables for @SMRR_BackRestInclin_Stat signal + +#ifndef SMRR_BackRestInclin_Stat_SMRR_status_Reserved +#define SMRR_BackRestInclin_Stat_SMRR_status_Reserved (3) +#endif + +#ifndef SMRR_BackRestInclin_Stat_SMRR_status_Decrease +#define SMRR_BackRestInclin_Stat_SMRR_status_Decrease (2) +#endif + +#ifndef SMRR_BackRestInclin_Stat_SMRR_status_Increase +#define SMRR_BackRestInclin_Stat_SMRR_status_Increase (1) +#endif + +#ifndef SMRR_BackRestInclin_Stat_SMRR_status_No_action +#define SMRR_BackRestInclin_Stat_SMRR_status_No_action (0) +#endif + + +// Value tables for @SMRR_LumbarSupportHeigh_Stat signal + +#ifndef SMRR_LumbarSupportHeigh_Stat_SMRR_status_Reserved +#define SMRR_LumbarSupportHeigh_Stat_SMRR_status_Reserved (3) +#endif + +#ifndef SMRR_LumbarSupportHeigh_Stat_SMRR_status_Decrease +#define SMRR_LumbarSupportHeigh_Stat_SMRR_status_Decrease (2) +#endif + +#ifndef SMRR_LumbarSupportHeigh_Stat_SMRR_status_Increase +#define SMRR_LumbarSupportHeigh_Stat_SMRR_status_Increase (1) +#endif + +#ifndef SMRR_LumbarSupportHeigh_Stat_SMRR_status_No_action +#define SMRR_LumbarSupportHeigh_Stat_SMRR_status_No_action (0) +#endif + + +// Value tables for @SMRR_BackRestHeadInclin_Stat signal + +#ifndef SMRR_BackRestHeadInclin_Stat_SMRR_status_Reserved +#define SMRR_BackRestHeadInclin_Stat_SMRR_status_Reserved (3) +#endif + +#ifndef SMRR_BackRestHeadInclin_Stat_SMRR_status_Decrease +#define SMRR_BackRestHeadInclin_Stat_SMRR_status_Decrease (2) +#endif + +#ifndef SMRR_BackRestHeadInclin_Stat_SMRR_status_Increase +#define SMRR_BackRestHeadInclin_Stat_SMRR_status_Increase (1) +#endif + +#ifndef SMRR_BackRestHeadInclin_Stat_SMRR_status_No_action +#define SMRR_BackRestHeadInclin_Stat_SMRR_status_No_action (0) +#endif + + +// Value tables for @SMRR_LumbarSupportDepth_Stat signal + +#ifndef SMRR_LumbarSupportDepth_Stat_SMRR_status_Reserved +#define SMRR_LumbarSupportDepth_Stat_SMRR_status_Reserved (3) +#endif + +#ifndef SMRR_LumbarSupportDepth_Stat_SMRR_status_Decrease +#define SMRR_LumbarSupportDepth_Stat_SMRR_status_Decrease (2) +#endif + +#ifndef SMRR_LumbarSupportDepth_Stat_SMRR_status_Increase +#define SMRR_LumbarSupportDepth_Stat_SMRR_status_Increase (1) +#endif + +#ifndef SMRR_LumbarSupportDepth_Stat_SMRR_status_No_action +#define SMRR_LumbarSupportDepth_Stat_SMRR_status_No_action (0) +#endif + + +// Value tables for @SMRR_BackRestWidth_Stat signal + +#ifndef SMRR_BackRestWidth_Stat_SMRR_status_Reserved +#define SMRR_BackRestWidth_Stat_SMRR_status_Reserved (3) +#endif + +#ifndef SMRR_BackRestWidth_Stat_SMRR_status_Decrease +#define SMRR_BackRestWidth_Stat_SMRR_status_Decrease (2) +#endif + +#ifndef SMRR_BackRestWidth_Stat_SMRR_status_Increase +#define SMRR_BackRestWidth_Stat_SMRR_status_Increase (1) +#endif + +#ifndef SMRR_BackRestWidth_Stat_SMRR_status_No_action +#define SMRR_BackRestWidth_Stat_SMRR_status_No_action (0) +#endif + + +// Value tables for @SMRR_CushionSupport_Stat signal + +#ifndef SMRR_CushionSupport_Stat_SMRR_status_Reserved +#define SMRR_CushionSupport_Stat_SMRR_status_Reserved (3) +#endif + +#ifndef SMRR_CushionSupport_Stat_SMRR_status_Decrease +#define SMRR_CushionSupport_Stat_SMRR_status_Decrease (2) +#endif + +#ifndef SMRR_CushionSupport_Stat_SMRR_status_Increase +#define SMRR_CushionSupport_Stat_SMRR_status_Increase (1) +#endif + +#ifndef SMRR_CushionSupport_Stat_SMRR_status_No_action +#define SMRR_CushionSupport_Stat_SMRR_status_No_action (0) +#endif + + +// Value tables for @SMRR_SeatVentilation_Stat signal + +#ifndef SMRR_SeatVentilation_Stat_SMRR_status_High_Power +#define SMRR_SeatVentilation_Stat_SMRR_status_High_Power (3) +#endif + +#ifndef SMRR_SeatVentilation_Stat_SMRR_status_Middle_Power +#define SMRR_SeatVentilation_Stat_SMRR_status_Middle_Power (2) +#endif + +#ifndef SMRR_SeatVentilation_Stat_SMRR_status_Low_Power +#define SMRR_SeatVentilation_Stat_SMRR_status_Low_Power (1) +#endif + +#ifndef SMRR_SeatVentilation_Stat_SMRR_status_Off +#define SMRR_SeatVentilation_Stat_SMRR_status_Off (0) +#endif + + +// Value tables for @SMRR_SeatVentBalance_Stat signal + +#ifndef SMRR_SeatVentBalance_Stat_SMRR_status_Backrest_100_Cushion_00_3 +#define SMRR_SeatVentBalance_Stat_SMRR_status_Backrest_100_Cushion_00_3 (7) +#endif + +#ifndef SMRR_SeatVentBalance_Stat_SMRR_status_Backrest_100_Cushion_33_2 +#define SMRR_SeatVentBalance_Stat_SMRR_status_Backrest_100_Cushion_33_2 (6) +#endif + +#ifndef SMRR_SeatVentBalance_Stat_SMRR_status_Backrest_100_Cushion_67_1 +#define SMRR_SeatVentBalance_Stat_SMRR_status_Backrest_100_Cushion_67_1 (5) +#endif + +#ifndef SMRR_SeatVentBalance_Stat_SMRR_status_Backrest_100_Cushion_100_0 +#define SMRR_SeatVentBalance_Stat_SMRR_status_Backrest_100_Cushion_100_0 (4) +#endif + +#ifndef SMRR_SeatVentBalance_Stat_SMRR_status_Backrest_67_Cushion_100_1 +#define SMRR_SeatVentBalance_Stat_SMRR_status_Backrest_67_Cushion_100_1 (3) +#endif + +#ifndef SMRR_SeatVentBalance_Stat_SMRR_status_Backrest_33_Cushion_100_2 +#define SMRR_SeatVentBalance_Stat_SMRR_status_Backrest_33_Cushion_100_2 (2) +#endif + +#ifndef SMRR_SeatVentBalance_Stat_SMRR_status_Backrest_00_Cushion_100_3 +#define SMRR_SeatVentBalance_Stat_SMRR_status_Backrest_00_Cushion_100_3 (1) +#endif + +#ifndef SMRR_SeatVentBalance_Stat_SMRR_status_No_action +#define SMRR_SeatVentBalance_Stat_SMRR_status_No_action (0) +#endif + + +// Value tables for @SMRR_Heating_Stat signal + +#ifndef SMRR_Heating_Stat_SMRR_status_High_Power +#define SMRR_Heating_Stat_SMRR_status_High_Power (3) +#endif + +#ifndef SMRR_Heating_Stat_SMRR_status_Middle_Power +#define SMRR_Heating_Stat_SMRR_status_Middle_Power (2) +#endif + +#ifndef SMRR_Heating_Stat_SMRR_status_Low_Power +#define SMRR_Heating_Stat_SMRR_status_Low_Power (1) +#endif + +#ifndef SMRR_Heating_Stat_SMRR_status_Off +#define SMRR_Heating_Stat_SMRR_status_Off (0) +#endif + + +// Value tables for @SMRR_HeatBalance_Stat signal + +#ifndef SMRR_HeatBalance_Stat_SMRR_status_Backrest_100_Cushion_00_3 +#define SMRR_HeatBalance_Stat_SMRR_status_Backrest_100_Cushion_00_3 (7) +#endif + +#ifndef SMRR_HeatBalance_Stat_SMRR_status_Backrest_100_Cushion_33_2 +#define SMRR_HeatBalance_Stat_SMRR_status_Backrest_100_Cushion_33_2 (6) +#endif + +#ifndef SMRR_HeatBalance_Stat_SMRR_status_Backrest_100_Cushion_67_1 +#define SMRR_HeatBalance_Stat_SMRR_status_Backrest_100_Cushion_67_1 (5) +#endif + +#ifndef SMRR_HeatBalance_Stat_SMRR_status_Backrest_100_Cushion_100_0 +#define SMRR_HeatBalance_Stat_SMRR_status_Backrest_100_Cushion_100_0 (4) +#endif + +#ifndef SMRR_HeatBalance_Stat_SMRR_status_Backrest_67_Cushion_100_1 +#define SMRR_HeatBalance_Stat_SMRR_status_Backrest_67_Cushion_100_1 (3) +#endif + +#ifndef SMRR_HeatBalance_Stat_SMRR_status_Backrest_33_Cushion_100_2 +#define SMRR_HeatBalance_Stat_SMRR_status_Backrest_33_Cushion_100_2 (2) +#endif + +#ifndef SMRR_HeatBalance_Stat_SMRR_status_Backrest_00_Cushion_100_3 +#define SMRR_HeatBalance_Stat_SMRR_status_Backrest_00_Cushion_100_3 (1) +#endif + +#ifndef SMRR_HeatBalance_Stat_SMRR_status_No_action +#define SMRR_HeatBalance_Stat_SMRR_status_No_action (0) +#endif + + +// Value tables for @SMRR_SeatMassage_Stat signal + +#ifndef SMRR_SeatMassage_Stat_SMRR_status_Reserved +#define SMRR_SeatMassage_Stat_SMRR_status_Reserved (3) +#endif + +#ifndef SMRR_SeatMassage_Stat_SMRR_status_Massage_ON +#define SMRR_SeatMassage_Stat_SMRR_status_Massage_ON (2) +#endif + +#ifndef SMRR_SeatMassage_Stat_SMRR_status_Massage_OFF +#define SMRR_SeatMassage_Stat_SMRR_status_Massage_OFF (1) +#endif + +#ifndef SMRR_SeatMassage_Stat_SMRR_status_No_Request +#define SMRR_SeatMassage_Stat_SMRR_status_No_Request (0) +#endif + + +// Value tables for @SMRR_MassageIntens_Stat signal + +#ifndef SMRR_MassageIntens_Stat_SMRR_status_High_power +#define SMRR_MassageIntens_Stat_SMRR_status_High_power (3) +#endif + +#ifndef SMRR_MassageIntens_Stat_SMRR_status_Middle_power +#define SMRR_MassageIntens_Stat_SMRR_status_Middle_power (2) +#endif + +#ifndef SMRR_MassageIntens_Stat_SMRR_status_Low_power +#define SMRR_MassageIntens_Stat_SMRR_status_Low_power (1) +#endif + +#ifndef SMRR_MassageIntens_Stat_SMRR_status_Off +#define SMRR_MassageIntens_Stat_SMRR_status_Off (0) +#endif + + +// Value tables for @SMRR_SeatMassageType_Stat signal + +#ifndef SMRR_SeatMassageType_Stat_SMRR_status_Type_7_Velvet +#define SMRR_SeatMassageType_Stat_SMRR_status_Type_7_Velvet (7) +#endif + +#ifndef SMRR_SeatMassageType_Stat_SMRR_status_Type_6_Sonnet +#define SMRR_SeatMassageType_Stat_SMRR_status_Type_6_Sonnet (6) +#endif + +#ifndef SMRR_SeatMassageType_Stat_SMRR_status_Type_5_Quantum +#define SMRR_SeatMassageType_Stat_SMRR_status_Type_5_Quantum (5) +#endif + +#ifndef SMRR_SeatMassageType_Stat_SMRR_status_Type_4_Cashmere +#define SMRR_SeatMassageType_Stat_SMRR_status_Type_4_Cashmere (4) +#endif + +#ifndef SMRR_SeatMassageType_Stat_SMRR_status_Type_3_Harmony +#define SMRR_SeatMassageType_Stat_SMRR_status_Type_3_Harmony (3) +#endif + +#ifndef SMRR_SeatMassageType_Stat_SMRR_status_Type_2_Orbital +#define SMRR_SeatMassageType_Stat_SMRR_status_Type_2_Orbital (2) +#endif + +#ifndef SMRR_SeatMassageType_Stat_SMRR_status_Type_1_Insight +#define SMRR_SeatMassageType_Stat_SMRR_status_Type_1_Insight (1) +#endif + +#ifndef SMRR_SeatMassageType_Stat_SMRR_status_No_action +#define SMRR_SeatMassageType_Stat_SMRR_status_No_action (0) +#endif + + +// Value tables for @SMRR_MoreComfort_Req signal + +#ifndef SMRR_MoreComfort_Req_SMRR_status_Requested +#define SMRR_MoreComfort_Req_SMRR_status_Requested (1) +#endif + +#ifndef SMRR_MoreComfort_Req_SMRR_status_Not_requested +#define SMRR_MoreComfort_Req_SMRR_status_Not_requested (0) +#endif + + +// Value tables for @SMRR_CarpetHeat_Stat signal + +#ifndef SMRR_CarpetHeat_Stat_SMRR_status_Carpet_heating_is_active +#define SMRR_CarpetHeat_Stat_SMRR_status_Carpet_heating_is_active (1) +#endif + +#ifndef SMRR_CarpetHeat_Stat_SMRR_status_Carpet_heating_is_inactive +#define SMRR_CarpetHeat_Stat_SMRR_status_Carpet_heating_is_inactive (0) +#endif + + +// Value tables for @SMRR_ActiveSupport_Stat signal + +#ifndef SMRR_ActiveSupport_Stat_SMRR_status_Active +#define SMRR_ActiveSupport_Stat_SMRR_status_Active (1) +#endif + +#ifndef SMRR_ActiveSupport_Stat_SMRR_status_Inactive +#define SMRR_ActiveSupport_Stat_SMRR_status_Inactive (0) +#endif + + +// Value tables for @SMRR_BackrestMassageType_Stat signal + +#ifndef SMRR_BackrestMassageType_Stat_SMRR_status_Reserved +#define SMRR_BackrestMassageType_Stat_SMRR_status_Reserved (7) +#endif + +#ifndef SMRR_BackrestMassageType_Stat_SMRR_status_Reserved +#define SMRR_BackrestMassageType_Stat_SMRR_status_Reserved (6) +#endif + +#ifndef SMRR_BackrestMassageType_Stat_SMRR_status_Type_5_Elegy +#define SMRR_BackrestMassageType_Stat_SMRR_status_Type_5_Elegy (5) +#endif + +#ifndef SMRR_BackrestMassageType_Stat_SMRR_status_Type_4_Caprice +#define SMRR_BackrestMassageType_Stat_SMRR_status_Type_4_Caprice (4) +#endif + +#ifndef SMRR_BackrestMassageType_Stat_SMRR_status_Type_3_Pulse +#define SMRR_BackrestMassageType_Stat_SMRR_status_Type_3_Pulse (3) +#endif + +#ifndef SMRR_BackrestMassageType_Stat_SMRR_status_Type_2_Energy +#define SMRR_BackrestMassageType_Stat_SMRR_status_Type_2_Energy (2) +#endif + +#ifndef SMRR_BackrestMassageType_Stat_SMRR_status_Type_1_Synchrony +#define SMRR_BackrestMassageType_Stat_SMRR_status_Type_1_Synchrony (1) +#endif + +#ifndef SMRR_BackrestMassageType_Stat_SMRR_status_No_action +#define SMRR_BackrestMassageType_Stat_SMRR_status_No_action (0) +#endif + + +// Value tables for @SMRR_TimerMassage_Stat signal + +#ifndef SMRR_TimerMassage_Stat_SMRR_status_Reserved +#define SMRR_TimerMassage_Stat_SMRR_status_Reserved (7) +#endif + +#ifndef SMRR_TimerMassage_Stat_SMRR_status_Reserved +#define SMRR_TimerMassage_Stat_SMRR_status_Reserved (6) +#endif + +#ifndef SMRR_TimerMassage_Stat_SMRR_status__min +#define SMRR_TimerMassage_Stat_SMRR_status__min (5) +#endif + +#ifndef SMRR_TimerMassage_Stat_SMRR_status__min +#define SMRR_TimerMassage_Stat_SMRR_status__min (4) +#endif + +#ifndef SMRR_TimerMassage_Stat_SMRR_status__min +#define SMRR_TimerMassage_Stat_SMRR_status__min (3) +#endif + +#ifndef SMRR_TimerMassage_Stat_SMRR_status__min +#define SMRR_TimerMassage_Stat_SMRR_status__min (2) +#endif + +#ifndef SMRR_TimerMassage_Stat_SMRR_status__min +#define SMRR_TimerMassage_Stat_SMRR_status__min (1) +#endif + +#ifndef SMRR_TimerMassage_Stat_SMRR_status__min +#define SMRR_TimerMassage_Stat_SMRR_status__min (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Signal of pressing MM menu button on SMRR + // 1 : "MM menu activation button pressed" + // 0 : "MM menu activation button not pressed" + uint8_t SMRR_MMmenuActivBtn_Stat : 1; // Bits= 1 + + // RR seat height changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRR_SeatHeight_Stat : 2; // Bits= 2 + + // RR seat headrest height changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRR_HeadRestHeight_Stat : 2; // Bits= 2 + + // RR seat longitudinal changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRR_SeatLongitudinal_Stat : 2; // Bits= 2 + + // RR seat headrest height inclination changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRR_HeadRestHeightInclin_Stat : 2; // Bits= 2 + + // RR seat surface longitudinal changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRR_SurfaceLongitudinal_Stat : 2; // Bits= 2 + + // RR seat footrest changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRR_SeatLegSupportH_Stat : 2; // Bits= 2 + + // RR seat inclination status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRR_SeatInclination_Stat : 2; // Bits= 2 + + // RR seat footrest longitudinal changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRR_SeatLegSupportL_Stat : 2; // Bits= 2 + + // RR seat backrest inclination status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRR_BackRestInclin_Stat : 2; // Bits= 2 + + // RR seat lumbar support height status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRR_LumbarSupportHeigh_Stat : 2; // Bits= 2 + + // RR seat backrest head inclination status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRR_BackRestHeadInclin_Stat : 2; // Bits= 2 + + // RR seat lumbar support depth status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRR_LumbarSupportDepth_Stat : 2; // Bits= 2 + + // Signal for regulation RR seat backrest width + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRR_BackRestWidth_Stat : 2; // Bits= 2 + + // RR seat cushion support inclination status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRR_CushionSupport_Stat : 2; // Bits= 2 + + // RR seat ventilation status + // 3 : "High Power" + // 2 : "Middle Power" + // 1 : "Low Power" + // 0 : "Off" + uint8_t SMRR_SeatVentilation_Stat : 2; // Bits= 2 + + // RR seat ventilation balance status + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 00%, Cushion 100%: -3" + // 0 : "No action" + uint8_t SMRR_SeatVentBalance_Stat : 3; // Bits= 3 + + // RR seat heating status + // 3 : "High Power" + // 2 : "Middle Power" + // 1 : "Low Power" + // 0 : "Off" + uint8_t SMRR_Heating_Stat : 2; // Bits= 2 + + // RR seat heating balance status + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 00%, Cushion 100%: -3" + // 0 : "No action" + uint8_t SMRR_HeatBalance_Stat : 3; // Bits= 3 + + // RR seat massage status + // 3 : "Reserved" + // 2 : "Massage ON" + // 1 : "Massage OFF" + // 0 : "No Request" + uint8_t SMRR_SeatMassage_Stat : 2; // Bits= 2 + + // RR seat massage intencivity status + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "Off" + uint8_t SMRR_MassageIntens_Stat : 2; // Bits= 2 + + // RR seat massage type status + // 7 : "Type 7 (Velvet)" + // 6 : "Type 6 (Sonnet)" + // 5 : "Type 5 (Quantum)" + // 4 : "Type 4 (Cashmere)" + // 3 : "Type 3 (Harmony)" + // 2 : "Type 2 (Orbital)" + // 1 : "Type 1 (Insight)" + // 0 : "No action" + uint8_t SMRR_SeatMassageType_Stat : 3; // Bits= 3 + + // Indicates a request to SMFR for more comfort + // 1 : "Requested" + // 0 : "Not requested" + uint8_t SMRR_MoreComfort_Req : 1; // Bits= 1 + + // Carpet heating status for rear right zone + // 1 : "Carpet heating is active" + // 0 : "Carpet heating is inactive" + uint8_t SMRR_CarpetHeat_Stat : 1; // Bits= 1 + + // Active lateral status + // 1 : "Active" + // 0 : "Inactive" + uint8_t SMRR_ActiveSupport_Stat : 1; // Bits= 1 + + // Signal for backrest massage type (mode) + // (RL backrest massage type request) + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Type 5 (Elegy)" + // 4 : "Type 4 (Caprice)" + // 3 : "Type 3 (Pulse)" + // 2 : "Type 2 (Energy)" + // 1 : "Type 1 (Synchrony)" + // 0 : "No action" + uint8_t SMRR_BackrestMassageType_Stat : 3; // Bits= 3 + + // RR seat massage timer status + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "5 min" + // 4 : "10 min" + // 3 : "15 min" + // 2 : "20 min" + // 1 : "25 min" + // 0 : "30 min" + uint8_t SMRR_TimerMassage_Stat : 3; // Bits= 3 + +#else + + // Signal of pressing MM menu button on SMRR + // 1 : "MM menu activation button pressed" + // 0 : "MM menu activation button not pressed" + uint8_t SMRR_MMmenuActivBtn_Stat; // Bits= 1 + + // RR seat height changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRR_SeatHeight_Stat; // Bits= 2 + + // RR seat headrest height changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRR_HeadRestHeight_Stat; // Bits= 2 + + // RR seat longitudinal changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRR_SeatLongitudinal_Stat; // Bits= 2 + + // RR seat headrest height inclination changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRR_HeadRestHeightInclin_Stat; // Bits= 2 + + // RR seat surface longitudinal changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRR_SurfaceLongitudinal_Stat; // Bits= 2 + + // RR seat footrest changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRR_SeatLegSupportH_Stat; // Bits= 2 + + // RR seat inclination status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRR_SeatInclination_Stat; // Bits= 2 + + // RR seat footrest longitudinal changing status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRR_SeatLegSupportL_Stat; // Bits= 2 + + // RR seat backrest inclination status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRR_BackRestInclin_Stat; // Bits= 2 + + // RR seat lumbar support height status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRR_LumbarSupportHeigh_Stat; // Bits= 2 + + // RR seat backrest head inclination status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRR_BackRestHeadInclin_Stat; // Bits= 2 + + // RR seat lumbar support depth status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRR_LumbarSupportDepth_Stat; // Bits= 2 + + // Signal for regulation RR seat backrest width + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRR_BackRestWidth_Stat; // Bits= 2 + + // RR seat cushion support inclination status + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t SMRR_CushionSupport_Stat; // Bits= 2 + + // RR seat ventilation status + // 3 : "High Power" + // 2 : "Middle Power" + // 1 : "Low Power" + // 0 : "Off" + uint8_t SMRR_SeatVentilation_Stat; // Bits= 2 + + // RR seat ventilation balance status + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 00%, Cushion 100%: -3" + // 0 : "No action" + uint8_t SMRR_SeatVentBalance_Stat; // Bits= 3 + + // RR seat heating status + // 3 : "High Power" + // 2 : "Middle Power" + // 1 : "Low Power" + // 0 : "Off" + uint8_t SMRR_Heating_Stat; // Bits= 2 + + // RR seat heating balance status + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 00%, Cushion 100%: -3" + // 0 : "No action" + uint8_t SMRR_HeatBalance_Stat; // Bits= 3 + + // RR seat massage status + // 3 : "Reserved" + // 2 : "Massage ON" + // 1 : "Massage OFF" + // 0 : "No Request" + uint8_t SMRR_SeatMassage_Stat; // Bits= 2 + + // RR seat massage intencivity status + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "Off" + uint8_t SMRR_MassageIntens_Stat; // Bits= 2 + + // RR seat massage type status + // 7 : "Type 7 (Velvet)" + // 6 : "Type 6 (Sonnet)" + // 5 : "Type 5 (Quantum)" + // 4 : "Type 4 (Cashmere)" + // 3 : "Type 3 (Harmony)" + // 2 : "Type 2 (Orbital)" + // 1 : "Type 1 (Insight)" + // 0 : "No action" + uint8_t SMRR_SeatMassageType_Stat; // Bits= 3 + + // Indicates a request to SMFR for more comfort + // 1 : "Requested" + // 0 : "Not requested" + uint8_t SMRR_MoreComfort_Req; // Bits= 1 + + // Carpet heating status for rear right zone + // 1 : "Carpet heating is active" + // 0 : "Carpet heating is inactive" + uint8_t SMRR_CarpetHeat_Stat; // Bits= 1 + + // Active lateral status + // 1 : "Active" + // 0 : "Inactive" + uint8_t SMRR_ActiveSupport_Stat; // Bits= 1 + + // Signal for backrest massage type (mode) + // (RL backrest massage type request) + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Type 5 (Elegy)" + // 4 : "Type 4 (Caprice)" + // 3 : "Type 3 (Pulse)" + // 2 : "Type 2 (Energy)" + // 1 : "Type 1 (Synchrony)" + // 0 : "No action" + uint8_t SMRR_BackrestMassageType_Stat; // Bits= 3 + + // RR seat massage timer status + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "5 min" + // 4 : "10 min" + // 3 : "15 min" + // 2 : "20 min" + // 1 : "25 min" + // 0 : "30 min" + uint8_t SMRR_TimerMassage_Stat; // Bits= 3 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} SMRR_status_t; + +// def @DocSL_T_FL CAN Message (1236 0x4d4) +#define DocSL_T_FL_IDE (0U) +#define DocSL_T_FL_DLC (3U) +#define DocSL_T_FL_CANID (0x4d4U) + +// Value tables for @DocSL_EjectButtons_Stat signal + +#ifndef DocSL_EjectButtons_Stat_DocSL_T_FL_Ejection_buttons_not_pressed +#define DocSL_EjectButtons_Stat_DocSL_T_FL_Ejection_buttons_not_pressed (0) +#endif + +#ifndef DocSL_EjectButtons_Stat_DocSL_T_FL_Ejection_button_pressed +#define DocSL_EjectButtons_Stat_DocSL_T_FL_Ejection_button_pressed (1) +#endif + + +// Value tables for @DocSL_TiltLimitUpper_Stat signal + +#ifndef DocSL_TiltLimitUpper_Stat_DocSL_T_FL_Upper_limit_not_reached +#define DocSL_TiltLimitUpper_Stat_DocSL_T_FL_Upper_limit_not_reached (0) +#endif + +#ifndef DocSL_TiltLimitUpper_Stat_DocSL_T_FL_Upper_limit_reached +#define DocSL_TiltLimitUpper_Stat_DocSL_T_FL_Upper_limit_reached (1) +#endif + + +// Value tables for @DocSL_TiltLimitLower_Stat signal + +#ifndef DocSL_TiltLimitLower_Stat_DocSL_T_FL_Lower_limit_not_reached +#define DocSL_TiltLimitLower_Stat_DocSL_T_FL_Lower_limit_not_reached (0) +#endif + +#ifndef DocSL_TiltLimitLower_Stat_DocSL_T_FL_Lower_limit_reached +#define DocSL_TiltLimitLower_Stat_DocSL_T_FL_Lower_limit_reached (1) +#endif + + +// Value tables for @DocSL_T_Availability_Stat signal + +#ifndef DocSL_T_Availability_Stat_DocSL_T_FL_Present +#define DocSL_T_Availability_Stat_DocSL_T_FL_Present (1) +#endif + +#ifndef DocSL_T_Availability_Stat_DocSL_T_FL_Missing +#define DocSL_T_Availability_Stat_DocSL_T_FL_Missing (0) +#endif + + +// Value tables for @DocSL_MechLock_Stat signal + +#ifndef DocSL_MechLock_Stat_DocSL_T_FL_Unlocked +#define DocSL_MechLock_Stat_DocSL_T_FL_Unlocked (0) +#endif + +#ifndef DocSL_MechLock_Stat_DocSL_T_FL_Transition +#define DocSL_MechLock_Stat_DocSL_T_FL_Transition (1) +#endif + +#ifndef DocSL_MechLock_Stat_DocSL_T_FL_Locked +#define DocSL_MechLock_Stat_DocSL_T_FL_Locked (2) +#endif + + +// Value tables for @DocSL_Error_Stat signal + +#ifndef DocSL_Error_Stat_DocSL_T_FL_No_error +#define DocSL_Error_Stat_DocSL_T_FL_No_error (0) +#endif + +#ifndef DocSL_Error_Stat_DocSL_T_FL_Barrier_or_pinch_detected +#define DocSL_Error_Stat_DocSL_T_FL_Barrier_or_pinch_detected (1) +#endif + +#ifndef DocSL_Error_Stat_DocSL_T_FL_Mechanical_lock_error +#define DocSL_Error_Stat_DocSL_T_FL_Mechanical_lock_error (2) +#endif + +#ifndef DocSL_Error_Stat_DocSL_T_FL_Full_failure +#define DocSL_Error_Stat_DocSL_T_FL_Full_failure (3) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Ejection buttons pressing status + // 0 : "Ejection buttons not pressed" + // 1 : "Ejection button pressed" + uint8_t DocSL_EjectButtons_Stat : 1; // Bits= 1 + + // Upper tilt limit reaching status + // 0 : "Upper limit not reached" + // 1 : "Upper limit reached" + uint8_t DocSL_TiltLimitUpper_Stat : 1; // Bits= 1 + + // Lower tilt limit reaching status + // 0 : "Lower limit not reached" + // 1 : "Lower limit reached" + uint8_t DocSL_TiltLimitLower_Stat : 1; // Bits= 1 + + // Status DocSR_T_FL missing or present LIN communications + // 1 : "Present" + // 0 : "Missing" + uint8_t DocSL_T_Availability_Stat : 1; // Bits= 1 + + // Mechanical lock status + // 0 : "Unlocked" + // 1 : "Transition" + // 2 : "Locked" + uint8_t DocSL_MechLock_Stat : 2; // Bits= 2 + + // System error status 0 - No error 1 - Electrical current limit reached 2 - Mechanical lock error 3 - More than 1 failures + // 0 : "No error" + // 1 : "Barrier or pinch detected" + // 2 : "Mechanical lock error" + // 3 : "Full failure" + uint8_t DocSL_Error_Stat : 2; // Bits= 2 + + // Current doc station absolute tilt angle 0 - 255 (0x0-0xFF) + uint8_t DocSL_TabletTilt_Val; // Bits= 8 + +#else + + // Ejection buttons pressing status + // 0 : "Ejection buttons not pressed" + // 1 : "Ejection button pressed" + uint8_t DocSL_EjectButtons_Stat; // Bits= 1 + + // Upper tilt limit reaching status + // 0 : "Upper limit not reached" + // 1 : "Upper limit reached" + uint8_t DocSL_TiltLimitUpper_Stat; // Bits= 1 + + // Lower tilt limit reaching status + // 0 : "Lower limit not reached" + // 1 : "Lower limit reached" + uint8_t DocSL_TiltLimitLower_Stat; // Bits= 1 + + // Status DocSR_T_FL missing or present LIN communications + // 1 : "Present" + // 0 : "Missing" + uint8_t DocSL_T_Availability_Stat; // Bits= 1 + + // Mechanical lock status + // 0 : "Unlocked" + // 1 : "Transition" + // 2 : "Locked" + uint8_t DocSL_MechLock_Stat; // Bits= 2 + + // System error status 0 - No error 1 - Electrical current limit reached 2 - Mechanical lock error 3 - More than 1 failures + // 0 : "No error" + // 1 : "Barrier or pinch detected" + // 2 : "Mechanical lock error" + // 3 : "Full failure" + uint8_t DocSL_Error_Stat; // Bits= 2 + + // Current doc station absolute tilt angle 0 - 255 (0x0-0xFF) + uint8_t DocSL_TabletTilt_Val; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} DocSL_T_FL_t; + +// def @DocSR_T_FR CAN Message (1237 0x4d5) +#define DocSR_T_FR_IDE (0U) +#define DocSR_T_FR_DLC (3U) +#define DocSR_T_FR_CANID (0x4d5U) + +// Value tables for @DocSR_EjectButtons_Stat signal + +#ifndef DocSR_EjectButtons_Stat_DocSR_T_FR_Ejection_buttons_not_pressed +#define DocSR_EjectButtons_Stat_DocSR_T_FR_Ejection_buttons_not_pressed (0) +#endif + +#ifndef DocSR_EjectButtons_Stat_DocSR_T_FR_Ejection_button_pressed +#define DocSR_EjectButtons_Stat_DocSR_T_FR_Ejection_button_pressed (1) +#endif + + +// Value tables for @DocSR_TiltLimitUpper_Stat signal + +#ifndef DocSR_TiltLimitUpper_Stat_DocSR_T_FR_Upper_limit_not_reached +#define DocSR_TiltLimitUpper_Stat_DocSR_T_FR_Upper_limit_not_reached (0) +#endif + +#ifndef DocSR_TiltLimitUpper_Stat_DocSR_T_FR_Upper_limit_reached +#define DocSR_TiltLimitUpper_Stat_DocSR_T_FR_Upper_limit_reached (1) +#endif + + +// Value tables for @DocSR_TiltLimitLower_Stat signal + +#ifndef DocSR_TiltLimitLower_Stat_DocSR_T_FR_Lower_limit_not_reached +#define DocSR_TiltLimitLower_Stat_DocSR_T_FR_Lower_limit_not_reached (0) +#endif + +#ifndef DocSR_TiltLimitLower_Stat_DocSR_T_FR_Lower_limit_reached +#define DocSR_TiltLimitLower_Stat_DocSR_T_FR_Lower_limit_reached (1) +#endif + + +// Value tables for @DocSR_T_Availability_Stat signal + +#ifndef DocSR_T_Availability_Stat_DocSR_T_FR_Missing +#define DocSR_T_Availability_Stat_DocSR_T_FR_Missing (0) +#endif + +#ifndef DocSR_T_Availability_Stat_DocSR_T_FR_Present +#define DocSR_T_Availability_Stat_DocSR_T_FR_Present (1) +#endif + + +// Value tables for @DocSR_MechLock_Stat signal + +#ifndef DocSR_MechLock_Stat_DocSR_T_FR_Unlocked +#define DocSR_MechLock_Stat_DocSR_T_FR_Unlocked (0) +#endif + +#ifndef DocSR_MechLock_Stat_DocSR_T_FR_Transition +#define DocSR_MechLock_Stat_DocSR_T_FR_Transition (1) +#endif + +#ifndef DocSR_MechLock_Stat_DocSR_T_FR_Locked +#define DocSR_MechLock_Stat_DocSR_T_FR_Locked (2) +#endif + + +// Value tables for @DocSR_Error_Stat signal + +#ifndef DocSR_Error_Stat_DocSR_T_FR_No_error +#define DocSR_Error_Stat_DocSR_T_FR_No_error (0) +#endif + +#ifndef DocSR_Error_Stat_DocSR_T_FR_Barrier_or_pinch_detected +#define DocSR_Error_Stat_DocSR_T_FR_Barrier_or_pinch_detected (1) +#endif + +#ifndef DocSR_Error_Stat_DocSR_T_FR_Mechanical_lock_error +#define DocSR_Error_Stat_DocSR_T_FR_Mechanical_lock_error (2) +#endif + +#ifndef DocSR_Error_Stat_DocSR_T_FR_Full_failure +#define DocSR_Error_Stat_DocSR_T_FR_Full_failure (3) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Ejection buttons pressing status + // 0 : "Ejection buttons not pressed" + // 1 : "Ejection button pressed" + uint8_t DocSR_EjectButtons_Stat : 1; // Bits= 1 + + // Upper tilt limit reaching status + // 0 : "Upper limit not reached" + // 1 : "Upper limit reached" + uint8_t DocSR_TiltLimitUpper_Stat : 1; // Bits= 1 + + // Lower tilt limit reaching status + // 0 : "Lower limit not reached" + // 1 : "Lower limit reached" + uint8_t DocSR_TiltLimitLower_Stat : 1; // Bits= 1 + + // Status DocSL_T_FL missing or present LIN communications + // 0 : "Missing" + // 1 : "Present" + uint8_t DocSR_T_Availability_Stat : 1; // Bits= 1 + + // Mechanical lock status + // 0 : "Unlocked" + // 1 : "Transition" + // 2 : "Locked" + uint8_t DocSR_MechLock_Stat : 2; // Bits= 2 + + // System error status 0 - No error 1 - Electrical current limit reached 2 - Mechanical lock error 3 - More than 1 failures + // 0 : "No error" + // 1 : "Barrier or pinch detected" + // 2 : "Mechanical lock error" + // 3 : "Full failure" + uint8_t DocSR_Error_Stat : 2; // Bits= 2 + + // Current doc station absolute tilt angle 0 - 255 (0x0-0xFF) + uint8_t DocSR_TabletTilt_Val; // Bits= 8 + +#else + + // Ejection buttons pressing status + // 0 : "Ejection buttons not pressed" + // 1 : "Ejection button pressed" + uint8_t DocSR_EjectButtons_Stat; // Bits= 1 + + // Upper tilt limit reaching status + // 0 : "Upper limit not reached" + // 1 : "Upper limit reached" + uint8_t DocSR_TiltLimitUpper_Stat; // Bits= 1 + + // Lower tilt limit reaching status + // 0 : "Lower limit not reached" + // 1 : "Lower limit reached" + uint8_t DocSR_TiltLimitLower_Stat; // Bits= 1 + + // Status DocSL_T_FL missing or present LIN communications + // 0 : "Missing" + // 1 : "Present" + uint8_t DocSR_T_Availability_Stat; // Bits= 1 + + // Mechanical lock status + // 0 : "Unlocked" + // 1 : "Transition" + // 2 : "Locked" + uint8_t DocSR_MechLock_Stat; // Bits= 2 + + // System error status 0 - No error 1 - Electrical current limit reached 2 - Mechanical lock error 3 - More than 1 failures + // 0 : "No error" + // 1 : "Barrier or pinch detected" + // 2 : "Mechanical lock error" + // 3 : "Full failure" + uint8_t DocSR_Error_Stat; // Bits= 2 + + // Current doc station absolute tilt angle 0 - 255 (0x0-0xFF) + uint8_t DocSR_TabletTilt_Val; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} DocSR_T_FR_t; + +// def @VAU_TPMS_Msg CAN Message (1264 0x4f0) +#define VAU_TPMS_Msg_IDE (0U) +#define VAU_TPMS_Msg_DLC (8U) +#define VAU_TPMS_Msg_CANID (0x4f0U) +#define VAU_TPMS_Msg_CYC (1000U) + +// Value tables for @VAU_TPMS_TireLocation signal + +#ifndef VAU_TPMS_TireLocation_VAU_TPMS_Msg_Rear_Right_tyre +#define VAU_TPMS_TireLocation_VAU_TPMS_Msg_Rear_Right_tyre (19) +#endif + +#ifndef VAU_TPMS_TireLocation_VAU_TPMS_Msg_Rear_Left_tyre +#define VAU_TPMS_TireLocation_VAU_TPMS_Msg_Rear_Left_tyre (16) +#endif + +#ifndef VAU_TPMS_TireLocation_VAU_TPMS_Msg_Front_Right_tyre +#define VAU_TPMS_TireLocation_VAU_TPMS_Msg_Front_Right_tyre (3) +#endif + +#ifndef VAU_TPMS_TireLocation_VAU_TPMS_Msg_Front_Left_tyre +#define VAU_TPMS_TireLocation_VAU_TPMS_Msg_Front_Left_tyre (0) +#endif + +// signal: @VAU_TPMS_TirePressureRR_ro +#define CANDB_VAU_TPMS_TirePressureRR_ro_CovFactor (5) +#define CANDB_VAU_TPMS_TirePressureRR_ro_toS(x) ( (uint8_t) ((x) / (5)) ) +#define CANDB_VAU_TPMS_TirePressureRR_ro_fromS(x) ( ((x) * (5)) ) +// signal: @VAU_TPMS_TirePressureRL_ro +#define CANDB_VAU_TPMS_TirePressureRL_ro_CovFactor (5) +#define CANDB_VAU_TPMS_TirePressureRL_ro_toS(x) ( (uint8_t) ((x) / (5)) ) +#define CANDB_VAU_TPMS_TirePressureRL_ro_fromS(x) ( ((x) * (5)) ) +// signal: @VAU_TPMS_TirePressureFR_ro +#define CANDB_VAU_TPMS_TirePressureFR_ro_CovFactor (5) +#define CANDB_VAU_TPMS_TirePressureFR_ro_toS(x) ( (uint8_t) ((x) / (5)) ) +#define CANDB_VAU_TPMS_TirePressureFR_ro_fromS(x) ( ((x) * (5)) ) +// signal: @VAU_TPMS_TirePressureFL_ro +#define CANDB_VAU_TPMS_TirePressureFL_ro_CovFactor (5) +#define CANDB_VAU_TPMS_TirePressureFL_ro_toS(x) ( (uint8_t) ((x) / (5)) ) +#define CANDB_VAU_TPMS_TirePressureFL_ro_fromS(x) ( ((x) * (5)) ) +// signal: @VAU_TPMS_SensorTemperatureRR_ro +#define CANDB_VAU_TPMS_SensorTemperatureRR_ro_CovFactor (1) +#define CANDB_VAU_TPMS_SensorTemperatureRR_ro_toS(x) ( (uint8_t) ((x) - (-50)) ) +#define CANDB_VAU_TPMS_SensorTemperatureRR_ro_fromS(x) ( ((x) + (-50)) ) +// signal: @VAU_TPMS_SensorTemperatureRL_ro +#define CANDB_VAU_TPMS_SensorTemperatureRL_ro_CovFactor (1) +#define CANDB_VAU_TPMS_SensorTemperatureRL_ro_toS(x) ( (uint8_t) ((x) - (-50)) ) +#define CANDB_VAU_TPMS_SensorTemperatureRL_ro_fromS(x) ( ((x) + (-50)) ) +// signal: @VAU_TPMS_SensorTemperatureFR_ro +#define CANDB_VAU_TPMS_SensorTemperatureFR_ro_CovFactor (1) +#define CANDB_VAU_TPMS_SensorTemperatureFR_ro_toS(x) ( (uint8_t) ((x) - (-50)) ) +#define CANDB_VAU_TPMS_SensorTemperatureFR_ro_fromS(x) ( ((x) + (-50)) ) +// signal: @VAU_TPMS_SensorTemperatureFL_ro +#define CANDB_VAU_TPMS_SensorTemperatureFL_ro_CovFactor (1) +#define CANDB_VAU_TPMS_SensorTemperatureFL_ro_toS(x) ( (uint8_t) ((x) - (-50)) ) +#define CANDB_VAU_TPMS_SensorTemperatureFL_ro_fromS(x) ( ((x) + (-50)) ) + +// Value tables for @VAU_TPMS_PressureSetSuccessRL signal + +#ifndef VAU_TPMS_PressureSetSuccessRL_VAU_TPMS_Msg_Pressure_set +#define VAU_TPMS_PressureSetSuccessRL_VAU_TPMS_Msg_Pressure_set (1) +#endif + +#ifndef VAU_TPMS_PressureSetSuccessRL_VAU_TPMS_Msg_No_change +#define VAU_TPMS_PressureSetSuccessRL_VAU_TPMS_Msg_No_change (0) +#endif + + +// Value tables for @VAU_TPMS_PressureSetSuccessFL signal + +#ifndef VAU_TPMS_PressureSetSuccessFL_VAU_TPMS_Msg_Pressure_set +#define VAU_TPMS_PressureSetSuccessFL_VAU_TPMS_Msg_Pressure_set (1) +#endif + +#ifndef VAU_TPMS_PressureSetSuccessFL_VAU_TPMS_Msg_No_change +#define VAU_TPMS_PressureSetSuccessFL_VAU_TPMS_Msg_No_change (0) +#endif + + +// Value tables for @VAU_TPMS_PressureSetSuccessRR signal + +#ifndef VAU_TPMS_PressureSetSuccessRR_VAU_TPMS_Msg_Pressure_set +#define VAU_TPMS_PressureSetSuccessRR_VAU_TPMS_Msg_Pressure_set (1) +#endif + +#ifndef VAU_TPMS_PressureSetSuccessRR_VAU_TPMS_Msg_No_change +#define VAU_TPMS_PressureSetSuccessRR_VAU_TPMS_Msg_No_change (0) +#endif + + +// Value tables for @VAU_TPMS_PressureSetSuccessFR signal + +#ifndef VAU_TPMS_PressureSetSuccessFR_VAU_TPMS_Msg_Pressure_set +#define VAU_TPMS_PressureSetSuccessFR_VAU_TPMS_Msg_Pressure_set (1) +#endif + +#ifndef VAU_TPMS_PressureSetSuccessFR_VAU_TPMS_Msg_No_change +#define VAU_TPMS_PressureSetSuccessFR_VAU_TPMS_Msg_No_change (0) +#endif + + +// Value tables for @VAU_TPMS_PressureSetSensorErrFR signal + +#ifndef VAU_TPMS_PressureSetSensorErrFR_VAU_TPMS_Msg_Pressure_not_set +#define VAU_TPMS_PressureSetSensorErrFR_VAU_TPMS_Msg_Pressure_not_set (1) +#endif + +#ifndef VAU_TPMS_PressureSetSensorErrFR_VAU_TPMS_Msg_No_change +#define VAU_TPMS_PressureSetSensorErrFR_VAU_TPMS_Msg_No_change (0) +#endif + + +// Value tables for @VAU_TPMS_PressureSetSensorErrFL signal + +#ifndef VAU_TPMS_PressureSetSensorErrFL_VAU_TPMS_Msg_Pressure_not_set +#define VAU_TPMS_PressureSetSensorErrFL_VAU_TPMS_Msg_Pressure_not_set (1) +#endif + +#ifndef VAU_TPMS_PressureSetSensorErrFL_VAU_TPMS_Msg_No_change +#define VAU_TPMS_PressureSetSensorErrFL_VAU_TPMS_Msg_No_change (0) +#endif + + +// Value tables for @VAU_TPMS_PressureSetSensorErrRL signal + +#ifndef VAU_TPMS_PressureSetSensorErrRL_VAU_TPMS_Msg_Pressure_not_set +#define VAU_TPMS_PressureSetSensorErrRL_VAU_TPMS_Msg_Pressure_not_set (1) +#endif + +#ifndef VAU_TPMS_PressureSetSensorErrRL_VAU_TPMS_Msg_No_change +#define VAU_TPMS_PressureSetSensorErrRL_VAU_TPMS_Msg_No_change (0) +#endif + + +// Value tables for @VAU_TPMS_PressureSetSensorErrRR signal + +#ifndef VAU_TPMS_PressureSetSensorErrRR_VAU_TPMS_Msg_Pressure_not_set +#define VAU_TPMS_PressureSetSensorErrRR_VAU_TPMS_Msg_Pressure_not_set (1) +#endif + +#ifndef VAU_TPMS_PressureSetSensorErrRR_VAU_TPMS_Msg_No_change +#define VAU_TPMS_PressureSetSensorErrRR_VAU_TPMS_Msg_No_change (0) +#endif + + +// Value tables for @VAU_TPMS_PressureSetErrFR signal + +#ifndef VAU_TPMS_PressureSetErrFR_VAU_TPMS_Msg_Pressure_not_set +#define VAU_TPMS_PressureSetErrFR_VAU_TPMS_Msg_Pressure_not_set (1) +#endif + +#ifndef VAU_TPMS_PressureSetErrFR_VAU_TPMS_Msg_No_change +#define VAU_TPMS_PressureSetErrFR_VAU_TPMS_Msg_No_change (0) +#endif + + +// Value tables for @VAU_TPMS_PressureSetErrRL signal + +#ifndef VAU_TPMS_PressureSetErrRL_VAU_TPMS_Msg_Pressure_not_set +#define VAU_TPMS_PressureSetErrRL_VAU_TPMS_Msg_Pressure_not_set (1) +#endif + +#ifndef VAU_TPMS_PressureSetErrRL_VAU_TPMS_Msg_No_change +#define VAU_TPMS_PressureSetErrRL_VAU_TPMS_Msg_No_change (0) +#endif + + +// Value tables for @VAU_TPMS_PressureSetErrFL signal + +#ifndef VAU_TPMS_PressureSetErrFL_VAU_TPMS_Msg_Pressure_not_set +#define VAU_TPMS_PressureSetErrFL_VAU_TPMS_Msg_Pressure_not_set (1) +#endif + +#ifndef VAU_TPMS_PressureSetErrFL_VAU_TPMS_Msg_No_change +#define VAU_TPMS_PressureSetErrFL_VAU_TPMS_Msg_No_change (0) +#endif + + +// Value tables for @VAU_TPMS_PressureSetErrRR signal + +#ifndef VAU_TPMS_PressureSetErrRR_VAU_TPMS_Msg_Pressure_not_set +#define VAU_TPMS_PressureSetErrRR_VAU_TPMS_Msg_Pressure_not_set (1) +#endif + +#ifndef VAU_TPMS_PressureSetErrRR_VAU_TPMS_Msg_No_change +#define VAU_TPMS_PressureSetErrRR_VAU_TPMS_Msg_No_change (0) +#endif + + +// Value tables for @VAU_TPMS_BatteryStatusRL signal + +#ifndef VAU_TPMS_BatteryStatusRL_VAU_TPMS_Msg_Low_Battery_Level +#define VAU_TPMS_BatteryStatusRL_VAU_TPMS_Msg_Low_Battery_Level (1) +#endif + +#ifndef VAU_TPMS_BatteryStatusRL_VAU_TPMS_Msg_Normal_Battery_Level +#define VAU_TPMS_BatteryStatusRL_VAU_TPMS_Msg_Normal_Battery_Level (0) +#endif + + +// Value tables for @VAU_TPMS_BatteryStatusRR signal + +#ifndef VAU_TPMS_BatteryStatusRR_VAU_TPMS_Msg_Low_Battery_Level +#define VAU_TPMS_BatteryStatusRR_VAU_TPMS_Msg_Low_Battery_Level (1) +#endif + +#ifndef VAU_TPMS_BatteryStatusRR_VAU_TPMS_Msg_Normal_Battery_Level +#define VAU_TPMS_BatteryStatusRR_VAU_TPMS_Msg_Normal_Battery_Level (0) +#endif + + +// Value tables for @VAU_TPMS_BatteryStatusFL signal + +#ifndef VAU_TPMS_BatteryStatusFL_VAU_TPMS_Msg_Low_Battery_Level +#define VAU_TPMS_BatteryStatusFL_VAU_TPMS_Msg_Low_Battery_Level (1) +#endif + +#ifndef VAU_TPMS_BatteryStatusFL_VAU_TPMS_Msg_Normal_Battery_Level +#define VAU_TPMS_BatteryStatusFL_VAU_TPMS_Msg_Normal_Battery_Level (0) +#endif + + +// Value tables for @VAU_TPMS_BatteryStatusFR signal + +#ifndef VAU_TPMS_BatteryStatusFR_VAU_TPMS_Msg_Low_Battery_Level +#define VAU_TPMS_BatteryStatusFR_VAU_TPMS_Msg_Low_Battery_Level (1) +#endif + +#ifndef VAU_TPMS_BatteryStatusFR_VAU_TPMS_Msg_Normal_Battery_Level +#define VAU_TPMS_BatteryStatusFR_VAU_TPMS_Msg_Normal_Battery_Level (0) +#endif + + +// Value tables for @VAU_TPMS_SensorEmissionCauseFL signal + +#ifndef VAU_TPMS_SensorEmissionCauseFL_VAU_TPMS_Msg_Mode_Entry +#define VAU_TPMS_SensorEmissionCauseFL_VAU_TPMS_Msg_Mode_Entry (3) +#endif + +#ifndef VAU_TPMS_SensorEmissionCauseFL_VAU_TPMS_Msg_Data_Pressure +#define VAU_TPMS_SensorEmissionCauseFL_VAU_TPMS_Msg_Data_Pressure (2) +#endif + +#ifndef VAU_TPMS_SensorEmissionCauseFL_VAU_TPMS_Msg_LF_Command +#define VAU_TPMS_SensorEmissionCauseFL_VAU_TPMS_Msg_LF_Command (1) +#endif + +#ifndef VAU_TPMS_SensorEmissionCauseFL_VAU_TPMS_Msg_Regular_Emission +#define VAU_TPMS_SensorEmissionCauseFL_VAU_TPMS_Msg_Regular_Emission (0) +#endif + + +// Value tables for @VAU_TPMS_SensorEmissionCauseRR signal + +#ifndef VAU_TPMS_SensorEmissionCauseRR_VAU_TPMS_Msg_Mode_Entry +#define VAU_TPMS_SensorEmissionCauseRR_VAU_TPMS_Msg_Mode_Entry (3) +#endif + +#ifndef VAU_TPMS_SensorEmissionCauseRR_VAU_TPMS_Msg_Data_Pressure +#define VAU_TPMS_SensorEmissionCauseRR_VAU_TPMS_Msg_Data_Pressure (2) +#endif + +#ifndef VAU_TPMS_SensorEmissionCauseRR_VAU_TPMS_Msg_LF_Command +#define VAU_TPMS_SensorEmissionCauseRR_VAU_TPMS_Msg_LF_Command (1) +#endif + +#ifndef VAU_TPMS_SensorEmissionCauseRR_VAU_TPMS_Msg_Regular_Emission +#define VAU_TPMS_SensorEmissionCauseRR_VAU_TPMS_Msg_Regular_Emission (0) +#endif + + +// Value tables for @VAU_TPMS_SensorEmissionCauseRL signal + +#ifndef VAU_TPMS_SensorEmissionCauseRL_VAU_TPMS_Msg_Mode_Entry +#define VAU_TPMS_SensorEmissionCauseRL_VAU_TPMS_Msg_Mode_Entry (3) +#endif + +#ifndef VAU_TPMS_SensorEmissionCauseRL_VAU_TPMS_Msg_Data_Pressure +#define VAU_TPMS_SensorEmissionCauseRL_VAU_TPMS_Msg_Data_Pressure (2) +#endif + +#ifndef VAU_TPMS_SensorEmissionCauseRL_VAU_TPMS_Msg_LF_Command +#define VAU_TPMS_SensorEmissionCauseRL_VAU_TPMS_Msg_LF_Command (1) +#endif + +#ifndef VAU_TPMS_SensorEmissionCauseRL_VAU_TPMS_Msg_Regular_Emission +#define VAU_TPMS_SensorEmissionCauseRL_VAU_TPMS_Msg_Regular_Emission (0) +#endif + + +// Value tables for @VAU_TPMS_SensorEmissionCauseFR signal + +#ifndef VAU_TPMS_SensorEmissionCauseFR_VAU_TPMS_Msg_Mode_Entry +#define VAU_TPMS_SensorEmissionCauseFR_VAU_TPMS_Msg_Mode_Entry (3) +#endif + +#ifndef VAU_TPMS_SensorEmissionCauseFR_VAU_TPMS_Msg_Data_Pressure +#define VAU_TPMS_SensorEmissionCauseFR_VAU_TPMS_Msg_Data_Pressure (2) +#endif + +#ifndef VAU_TPMS_SensorEmissionCauseFR_VAU_TPMS_Msg_LF_Command +#define VAU_TPMS_SensorEmissionCauseFR_VAU_TPMS_Msg_LF_Command (1) +#endif + +#ifndef VAU_TPMS_SensorEmissionCauseFR_VAU_TPMS_Msg_Regular_Emission +#define VAU_TPMS_SensorEmissionCauseFR_VAU_TPMS_Msg_Regular_Emission (0) +#endif + + +// Value tables for @VAU_TPMS_SensorOperationModeRR signal + +#ifndef VAU_TPMS_SensorOperationModeRR_VAU_TPMS_Msg_Ship +#define VAU_TPMS_SensorOperationModeRR_VAU_TPMS_Msg_Ship (3) +#endif + +#ifndef VAU_TPMS_SensorOperationModeRR_VAU_TPMS_Msg_Test +#define VAU_TPMS_SensorOperationModeRR_VAU_TPMS_Msg_Test (2) +#endif + +#ifndef VAU_TPMS_SensorOperationModeRR_VAU_TPMS_Msg_Park +#define VAU_TPMS_SensorOperationModeRR_VAU_TPMS_Msg_Park (1) +#endif + +#ifndef VAU_TPMS_SensorOperationModeRR_VAU_TPMS_Msg_Drive +#define VAU_TPMS_SensorOperationModeRR_VAU_TPMS_Msg_Drive (0) +#endif + + +// Value tables for @VAU_TPMS_SensorOperationModeRL signal + +#ifndef VAU_TPMS_SensorOperationModeRL_VAU_TPMS_Msg_Ship +#define VAU_TPMS_SensorOperationModeRL_VAU_TPMS_Msg_Ship (3) +#endif + +#ifndef VAU_TPMS_SensorOperationModeRL_VAU_TPMS_Msg_Test +#define VAU_TPMS_SensorOperationModeRL_VAU_TPMS_Msg_Test (2) +#endif + +#ifndef VAU_TPMS_SensorOperationModeRL_VAU_TPMS_Msg_Park +#define VAU_TPMS_SensorOperationModeRL_VAU_TPMS_Msg_Park (1) +#endif + +#ifndef VAU_TPMS_SensorOperationModeRL_VAU_TPMS_Msg_Drive +#define VAU_TPMS_SensorOperationModeRL_VAU_TPMS_Msg_Drive (0) +#endif + + +// Value tables for @VAU_TPMS_SensorOperationModeFR signal + +#ifndef VAU_TPMS_SensorOperationModeFR_VAU_TPMS_Msg_Ship +#define VAU_TPMS_SensorOperationModeFR_VAU_TPMS_Msg_Ship (3) +#endif + +#ifndef VAU_TPMS_SensorOperationModeFR_VAU_TPMS_Msg_Test +#define VAU_TPMS_SensorOperationModeFR_VAU_TPMS_Msg_Test (2) +#endif + +#ifndef VAU_TPMS_SensorOperationModeFR_VAU_TPMS_Msg_Park +#define VAU_TPMS_SensorOperationModeFR_VAU_TPMS_Msg_Park (1) +#endif + +#ifndef VAU_TPMS_SensorOperationModeFR_VAU_TPMS_Msg_Drive +#define VAU_TPMS_SensorOperationModeFR_VAU_TPMS_Msg_Drive (0) +#endif + + +// Value tables for @VAU_TPMS_SensorOperationModeFL signal + +#ifndef VAU_TPMS_SensorOperationModeFL_VAU_TPMS_Msg_Ship +#define VAU_TPMS_SensorOperationModeFL_VAU_TPMS_Msg_Ship (3) +#endif + +#ifndef VAU_TPMS_SensorOperationModeFL_VAU_TPMS_Msg_Test +#define VAU_TPMS_SensorOperationModeFL_VAU_TPMS_Msg_Test (2) +#endif + +#ifndef VAU_TPMS_SensorOperationModeFL_VAU_TPMS_Msg_Park +#define VAU_TPMS_SensorOperationModeFL_VAU_TPMS_Msg_Park (1) +#endif + +#ifndef VAU_TPMS_SensorOperationModeFL_VAU_TPMS_Msg_Drive +#define VAU_TPMS_SensorOperationModeFL_VAU_TPMS_Msg_Drive (0) +#endif + + +// Value tables for @VAU_TPMS_TirePressureFaultRL signal + +#ifndef VAU_TPMS_TirePressureFaultRL_VAU_TPMS_Msg_No_fault +#define VAU_TPMS_TirePressureFaultRL_VAU_TPMS_Msg_No_fault (7) +#endif + +#ifndef VAU_TPMS_TirePressureFaultRL_VAU_TPMS_Msg_Pressure_acquistion_error +#define VAU_TPMS_TirePressureFaultRL_VAU_TPMS_Msg_Pressure_acquistion_error (6) +#endif + +#ifndef VAU_TPMS_TirePressureFaultRL_VAU_TPMS_Msg_No_fault +#define VAU_TPMS_TirePressureFaultRL_VAU_TPMS_Msg_No_fault (5) +#endif + +#ifndef VAU_TPMS_TirePressureFaultRL_VAU_TPMS_Msg_Low_Pressure_Alert +#define VAU_TPMS_TirePressureFaultRL_VAU_TPMS_Msg_Low_Pressure_Alert (4) +#endif + +#ifndef VAU_TPMS_TirePressureFaultRL_VAU_TPMS_Msg_Low_Pressure_Warning +#define VAU_TPMS_TirePressureFaultRL_VAU_TPMS_Msg_Low_Pressure_Warning (3) +#endif + +#ifndef VAU_TPMS_TirePressureFaultRL_VAU_TPMS_Msg_No_Pressure_warning +#define VAU_TPMS_TirePressureFaultRL_VAU_TPMS_Msg_No_Pressure_warning (2) +#endif + +#ifndef VAU_TPMS_TirePressureFaultRL_VAU_TPMS_Msg_High_Pressure_Warning +#define VAU_TPMS_TirePressureFaultRL_VAU_TPMS_Msg_High_Pressure_Warning (1) +#endif + +#ifndef VAU_TPMS_TirePressureFaultRL_VAU_TPMS_Msg_No_fault +#define VAU_TPMS_TirePressureFaultRL_VAU_TPMS_Msg_No_fault (0) +#endif + + +// Value tables for @VAU_TPMS_TirePressureFaultFR signal + +#ifndef VAU_TPMS_TirePressureFaultFR_VAU_TPMS_Msg_No_fault +#define VAU_TPMS_TirePressureFaultFR_VAU_TPMS_Msg_No_fault (7) +#endif + +#ifndef VAU_TPMS_TirePressureFaultFR_VAU_TPMS_Msg_Pressure_acquistion_error +#define VAU_TPMS_TirePressureFaultFR_VAU_TPMS_Msg_Pressure_acquistion_error (6) +#endif + +#ifndef VAU_TPMS_TirePressureFaultFR_VAU_TPMS_Msg_No_fault +#define VAU_TPMS_TirePressureFaultFR_VAU_TPMS_Msg_No_fault (5) +#endif + +#ifndef VAU_TPMS_TirePressureFaultFR_VAU_TPMS_Msg_Low_Pressure_Alert +#define VAU_TPMS_TirePressureFaultFR_VAU_TPMS_Msg_Low_Pressure_Alert (4) +#endif + +#ifndef VAU_TPMS_TirePressureFaultFR_VAU_TPMS_Msg_Low_Pressure_Warning +#define VAU_TPMS_TirePressureFaultFR_VAU_TPMS_Msg_Low_Pressure_Warning (3) +#endif + +#ifndef VAU_TPMS_TirePressureFaultFR_VAU_TPMS_Msg_No_Pressure_warning +#define VAU_TPMS_TirePressureFaultFR_VAU_TPMS_Msg_No_Pressure_warning (2) +#endif + +#ifndef VAU_TPMS_TirePressureFaultFR_VAU_TPMS_Msg_High_Pressure_Warning +#define VAU_TPMS_TirePressureFaultFR_VAU_TPMS_Msg_High_Pressure_Warning (1) +#endif + +#ifndef VAU_TPMS_TirePressureFaultFR_VAU_TPMS_Msg_No_fault +#define VAU_TPMS_TirePressureFaultFR_VAU_TPMS_Msg_No_fault (0) +#endif + + +// Value tables for @VAU_TPMS_TirePressureFaultFL signal + +#ifndef VAU_TPMS_TirePressureFaultFL_VAU_TPMS_Msg_No_fault +#define VAU_TPMS_TirePressureFaultFL_VAU_TPMS_Msg_No_fault (7) +#endif + +#ifndef VAU_TPMS_TirePressureFaultFL_VAU_TPMS_Msg_Pressure_acquistion_error +#define VAU_TPMS_TirePressureFaultFL_VAU_TPMS_Msg_Pressure_acquistion_error (6) +#endif + +#ifndef VAU_TPMS_TirePressureFaultFL_VAU_TPMS_Msg_No_fault +#define VAU_TPMS_TirePressureFaultFL_VAU_TPMS_Msg_No_fault (5) +#endif + +#ifndef VAU_TPMS_TirePressureFaultFL_VAU_TPMS_Msg_Low_Pressure_Alert +#define VAU_TPMS_TirePressureFaultFL_VAU_TPMS_Msg_Low_Pressure_Alert (4) +#endif + +#ifndef VAU_TPMS_TirePressureFaultFL_VAU_TPMS_Msg_Low_Pressure_Warning +#define VAU_TPMS_TirePressureFaultFL_VAU_TPMS_Msg_Low_Pressure_Warning (3) +#endif + +#ifndef VAU_TPMS_TirePressureFaultFL_VAU_TPMS_Msg_No_Pressure_warning +#define VAU_TPMS_TirePressureFaultFL_VAU_TPMS_Msg_No_Pressure_warning (2) +#endif + +#ifndef VAU_TPMS_TirePressureFaultFL_VAU_TPMS_Msg_High_Pressure_Warning +#define VAU_TPMS_TirePressureFaultFL_VAU_TPMS_Msg_High_Pressure_Warning (1) +#endif + +#ifndef VAU_TPMS_TirePressureFaultFL_VAU_TPMS_Msg_No_fault +#define VAU_TPMS_TirePressureFaultFL_VAU_TPMS_Msg_No_fault (0) +#endif + + +// Value tables for @VAU_TPMS_TirePressureFaultRR signal + +#ifndef VAU_TPMS_TirePressureFaultRR_VAU_TPMS_Msg_No_fault +#define VAU_TPMS_TirePressureFaultRR_VAU_TPMS_Msg_No_fault (7) +#endif + +#ifndef VAU_TPMS_TirePressureFaultRR_VAU_TPMS_Msg_Pressure_acquistion_error +#define VAU_TPMS_TirePressureFaultRR_VAU_TPMS_Msg_Pressure_acquistion_error (6) +#endif + +#ifndef VAU_TPMS_TirePressureFaultRR_VAU_TPMS_Msg_No_fault +#define VAU_TPMS_TirePressureFaultRR_VAU_TPMS_Msg_No_fault (5) +#endif + +#ifndef VAU_TPMS_TirePressureFaultRR_VAU_TPMS_Msg_Low_Pressure_Alert +#define VAU_TPMS_TirePressureFaultRR_VAU_TPMS_Msg_Low_Pressure_Alert (4) +#endif + +#ifndef VAU_TPMS_TirePressureFaultRR_VAU_TPMS_Msg_Low_Pressure_Warning +#define VAU_TPMS_TirePressureFaultRR_VAU_TPMS_Msg_Low_Pressure_Warning (3) +#endif + +#ifndef VAU_TPMS_TirePressureFaultRR_VAU_TPMS_Msg_No_Pressure_warning +#define VAU_TPMS_TirePressureFaultRR_VAU_TPMS_Msg_No_Pressure_warning (2) +#endif + +#ifndef VAU_TPMS_TirePressureFaultRR_VAU_TPMS_Msg_High_Pressure_Warning +#define VAU_TPMS_TirePressureFaultRR_VAU_TPMS_Msg_High_Pressure_Warning (1) +#endif + +#ifndef VAU_TPMS_TirePressureFaultRR_VAU_TPMS_Msg_No_fault +#define VAU_TPMS_TirePressureFaultRR_VAU_TPMS_Msg_No_fault (0) +#endif + + +// Value tables for @TPMS_SensorTempFaultFR signal + +#ifndef TPMS_SensorTempFaultFR_VAU_TPMS_Msg_Description_for_the_value_0x3 +#define TPMS_SensorTempFaultFR_VAU_TPMS_Msg_Description_for_the_value_0x3 (3) +#endif + +#ifndef TPMS_SensorTempFaultFR_VAU_TPMS_Msg_Description_for_the_value_0x2 +#define TPMS_SensorTempFaultFR_VAU_TPMS_Msg_Description_for_the_value_0x2 (2) +#endif + +#ifndef TPMS_SensorTempFaultFR_VAU_TPMS_Msg_No_Warning +#define TPMS_SensorTempFaultFR_VAU_TPMS_Msg_No_Warning (1) +#endif + +#ifndef TPMS_SensorTempFaultFR_VAU_TPMS_Msg_High_Temp +#define TPMS_SensorTempFaultFR_VAU_TPMS_Msg_High_Temp (0) +#endif + + +// Value tables for @TPMS_SensorTempFaultRR signal + +#ifndef TPMS_SensorTempFaultRR_VAU_TPMS_Msg_Description_for_the_value_0x3 +#define TPMS_SensorTempFaultRR_VAU_TPMS_Msg_Description_for_the_value_0x3 (3) +#endif + +#ifndef TPMS_SensorTempFaultRR_VAU_TPMS_Msg_Description_for_the_value_0x2 +#define TPMS_SensorTempFaultRR_VAU_TPMS_Msg_Description_for_the_value_0x2 (2) +#endif + +#ifndef TPMS_SensorTempFaultRR_VAU_TPMS_Msg_No_Warning +#define TPMS_SensorTempFaultRR_VAU_TPMS_Msg_No_Warning (1) +#endif + +#ifndef TPMS_SensorTempFaultRR_VAU_TPMS_Msg_High_Temp +#define TPMS_SensorTempFaultRR_VAU_TPMS_Msg_High_Temp (0) +#endif + + +// Value tables for @TPMS_SensorTempFaultFL signal + +#ifndef TPMS_SensorTempFaultFL_VAU_TPMS_Msg_Description_for_the_value_0x3 +#define TPMS_SensorTempFaultFL_VAU_TPMS_Msg_Description_for_the_value_0x3 (3) +#endif + +#ifndef TPMS_SensorTempFaultFL_VAU_TPMS_Msg_Description_for_the_value_0x2 +#define TPMS_SensorTempFaultFL_VAU_TPMS_Msg_Description_for_the_value_0x2 (2) +#endif + +#ifndef TPMS_SensorTempFaultFL_VAU_TPMS_Msg_No_Warning +#define TPMS_SensorTempFaultFL_VAU_TPMS_Msg_No_Warning (1) +#endif + +#ifndef TPMS_SensorTempFaultFL_VAU_TPMS_Msg_High_Temp +#define TPMS_SensorTempFaultFL_VAU_TPMS_Msg_High_Temp (0) +#endif + + +// Value tables for @TPMS_SensorTempFaultRL signal + +#ifndef TPMS_SensorTempFaultRL_VAU_TPMS_Msg_Description_for_the_value_0x3 +#define TPMS_SensorTempFaultRL_VAU_TPMS_Msg_Description_for_the_value_0x3 (3) +#endif + +#ifndef TPMS_SensorTempFaultRL_VAU_TPMS_Msg_Description_for_the_value_0x2 +#define TPMS_SensorTempFaultRL_VAU_TPMS_Msg_Description_for_the_value_0x2 (2) +#endif + +#ifndef TPMS_SensorTempFaultRL_VAU_TPMS_Msg_No_Warning +#define TPMS_SensorTempFaultRL_VAU_TPMS_Msg_No_Warning (1) +#endif + +#ifndef TPMS_SensorTempFaultRL_VAU_TPMS_Msg_High_Temp +#define TPMS_SensorTempFaultRL_VAU_TPMS_Msg_High_Temp (0) +#endif + + +// Value tables for @VAU_TPMS_SensorFaultFR signal + +#ifndef VAU_TPMS_SensorFaultFR_VAU_TPMS_Msg_An_acquision_failure_has_occured +#define VAU_TPMS_SensorFaultFR_VAU_TPMS_Msg_An_acquision_failure_has_occured (1) +#endif + +#ifndef VAU_TPMS_SensorFaultFR_VAU_TPMS_Msg_No_failure +#define VAU_TPMS_SensorFaultFR_VAU_TPMS_Msg_No_failure (0) +#endif + + +// Value tables for @VAU_TPMS_SensorFaultRR signal + +#ifndef VAU_TPMS_SensorFaultRR_VAU_TPMS_Msg_An_acquision_failure_has_occured +#define VAU_TPMS_SensorFaultRR_VAU_TPMS_Msg_An_acquision_failure_has_occured (1) +#endif + +#ifndef VAU_TPMS_SensorFaultRR_VAU_TPMS_Msg_No_failure +#define VAU_TPMS_SensorFaultRR_VAU_TPMS_Msg_No_failure (0) +#endif + + +// Value tables for @VAU_TPMS_SensorFaultRL signal + +#ifndef VAU_TPMS_SensorFaultRL_VAU_TPMS_Msg_An_acquision_failure_has_occured +#define VAU_TPMS_SensorFaultRL_VAU_TPMS_Msg_An_acquision_failure_has_occured (1) +#endif + +#ifndef VAU_TPMS_SensorFaultRL_VAU_TPMS_Msg_No_failure +#define VAU_TPMS_SensorFaultRL_VAU_TPMS_Msg_No_failure (0) +#endif + + +// Value tables for @VAU_TPMS_SensorFaultFL signal + +#ifndef VAU_TPMS_SensorFaultFL_VAU_TPMS_Msg_An_acquision_failure_has_occured +#define VAU_TPMS_SensorFaultFL_VAU_TPMS_Msg_An_acquision_failure_has_occured (1) +#endif + +#ifndef VAU_TPMS_SensorFaultFL_VAU_TPMS_Msg_No_failure +#define VAU_TPMS_SensorFaultFL_VAU_TPMS_Msg_No_failure (0) +#endif + + +// Value tables for @VAU_TPMS_SensorPresenceFR signal + +#ifndef VAU_TPMS_SensorPresenceFR_VAU_TPMS_Msg_Sensor_Absent +#define VAU_TPMS_SensorPresenceFR_VAU_TPMS_Msg_Sensor_Absent (1) +#endif + +#ifndef VAU_TPMS_SensorPresenceFR_VAU_TPMS_Msg_Sensor_Detect +#define VAU_TPMS_SensorPresenceFR_VAU_TPMS_Msg_Sensor_Detect (0) +#endif + + +// Value tables for @VAU_TPMS_SensorPresenceRL signal + +#ifndef VAU_TPMS_SensorPresenceRL_VAU_TPMS_Msg_Sensor_Absent +#define VAU_TPMS_SensorPresenceRL_VAU_TPMS_Msg_Sensor_Absent (1) +#endif + +#ifndef VAU_TPMS_SensorPresenceRL_VAU_TPMS_Msg_Sensor_Detect +#define VAU_TPMS_SensorPresenceRL_VAU_TPMS_Msg_Sensor_Detect (0) +#endif + + +// Value tables for @VAU_TPMS_SensorPresenceFL signal + +#ifndef VAU_TPMS_SensorPresenceFL_VAU_TPMS_Msg_Sensor_Absent +#define VAU_TPMS_SensorPresenceFL_VAU_TPMS_Msg_Sensor_Absent (1) +#endif + +#ifndef VAU_TPMS_SensorPresenceFL_VAU_TPMS_Msg_Sensor_Detect +#define VAU_TPMS_SensorPresenceFL_VAU_TPMS_Msg_Sensor_Detect (0) +#endif + + +// Value tables for @VAU_TPMS_SensorPresenceRR signal + +#ifndef VAU_TPMS_SensorPresenceRR_VAU_TPMS_Msg_Sensor_Absent +#define VAU_TPMS_SensorPresenceRR_VAU_TPMS_Msg_Sensor_Absent (1) +#endif + +#ifndef VAU_TPMS_SensorPresenceRR_VAU_TPMS_Msg_Sensor_Detect +#define VAU_TPMS_SensorPresenceRR_VAU_TPMS_Msg_Sensor_Detect (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // 19 : "Rear Right tyre" + // 16 : "Rear Left tyre" + // 3 : "Front Right tyre" + // 0 : "Front Left tyre" + // MULTIPLEX master signal + uint8_t VAU_TPMS_TireLocation; // Bits= 8 + + // Indicate the measured pressure in the tyre + // multiplex variable + uint8_t VAU_TPMS_TirePressureRR_ro; // Bits= 8 Factor= 5 Unit:'kPa' + +#ifdef CANDB_USE_SIGFLOAT + uint16_t VAU_TPMS_TirePressureRR_phys; +#endif // CANDB_USE_SIGFLOAT + + // Indicate the measured pressure in the tyre + // multiplex variable + uint8_t VAU_TPMS_TirePressureRL_ro; // Bits= 8 Factor= 5 Unit:'kPa' + +#ifdef CANDB_USE_SIGFLOAT + uint16_t VAU_TPMS_TirePressureRL_phys; +#endif // CANDB_USE_SIGFLOAT + + // Indicate the measured pressure in the tyre + // multiplex variable + uint8_t VAU_TPMS_TirePressureFR_ro; // Bits= 8 Factor= 5 Unit:'kPa' + +#ifdef CANDB_USE_SIGFLOAT + uint16_t VAU_TPMS_TirePressureFR_phys; +#endif // CANDB_USE_SIGFLOAT + + // Indicate the measured pressure in the tyre + // multiplex variable + uint8_t VAU_TPMS_TirePressureFL_ro; // Bits= 8 Factor= 5 Unit:'kPa' + +#ifdef CANDB_USE_SIGFLOAT + uint16_t VAU_TPMS_TirePressureFL_phys; +#endif // CANDB_USE_SIGFLOAT + + // RR wheel temperature + // multiplex variable + uint8_t VAU_TPMS_SensorTemperatureRR_ro; // Bits= 8 Offset= -50 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + int16_t VAU_TPMS_SensorTemperatureRR_phys; +#endif // CANDB_USE_SIGFLOAT + + // RL wheel temperature + // multiplex variable + uint8_t VAU_TPMS_SensorTemperatureRL_ro; // Bits= 8 Offset= -50 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + int16_t VAU_TPMS_SensorTemperatureRL_phys; +#endif // CANDB_USE_SIGFLOAT + + // FR wheel temperature + // multiplex variable + uint8_t VAU_TPMS_SensorTemperatureFR_ro; // Bits= 8 Offset= -50 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + int16_t VAU_TPMS_SensorTemperatureFR_phys; +#endif // CANDB_USE_SIGFLOAT + + // FL wheel temperature + // multiplex variable + uint8_t VAU_TPMS_SensorTemperatureFL_ro; // Bits= 8 Offset= -50 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + int16_t VAU_TPMS_SensorTemperatureFL_phys; +#endif // CANDB_USE_SIGFLOAT + + // New nominal pressure value has been set + // 1 : "Pressure set" + // 0 : "No change" + // multiplex variable + uint8_t VAU_TPMS_PressureSetSuccessRL : 1; // Bits= 1 + + // New nominal pressure value has been set + // 1 : "Pressure set" + // 0 : "No change" + // multiplex variable + uint8_t VAU_TPMS_PressureSetSuccessFL : 1; // Bits= 1 + + // New nominal pressure value has been set + // 1 : "Pressure set" + // 0 : "No change" + // multiplex variable + uint8_t VAU_TPMS_PressureSetSuccessRR : 1; // Bits= 1 + + // New nominal pressure value has been set + // 1 : "Pressure set" + // 0 : "No change" + // multiplex variable + uint8_t VAU_TPMS_PressureSetSuccessFR : 1; // Bits= 1 + + // New nominal pressure value has not been set, check the pressure sensors + // 1 : "Pressure not set" + // 0 : "No change" + // multiplex variable + uint8_t VAU_TPMS_PressureSetSensorErrFR : 1; // Bits= 1 + + // New nominal pressure value has not been set, check the pressure sensors + // 1 : "Pressure not set" + // 0 : "No change" + // multiplex variable + uint8_t VAU_TPMS_PressureSetSensorErrFL : 1; // Bits= 1 + + // New nominal pressure value has not been set, check the pressure sensors + // 1 : "Pressure not set" + // 0 : "No change" + // multiplex variable + uint8_t VAU_TPMS_PressureSetSensorErrRL : 1; // Bits= 1 + + // New nominal pressure value has not been set, check the pressure sensors + // 1 : "Pressure not set" + // 0 : "No change" + // multiplex variable + uint8_t VAU_TPMS_PressureSetSensorErrRR : 1; // Bits= 1 + + // New nominal pressure value has not been set, check the pressure + // 1 : "Pressure not set" + // 0 : "No change" + // multiplex variable + uint8_t VAU_TPMS_PressureSetErrFR : 1; // Bits= 1 + + // New nominal pressure value has not been set, check the pressure + // 1 : "Pressure not set" + // 0 : "No change" + // multiplex variable + uint8_t VAU_TPMS_PressureSetErrRL : 1; // Bits= 1 + + // New nominal pressure value has not been set, check the pressure + // 1 : "Pressure not set" + // 0 : "No change" + // multiplex variable + uint8_t VAU_TPMS_PressureSetErrFL : 1; // Bits= 1 + + // New nominal pressure value has not been set, check the pressure + // 1 : "Pressure not set" + // 0 : "No change" + // multiplex variable + uint8_t VAU_TPMS_PressureSetErrRR : 1; // Bits= 1 + + // RL Wheel Sensor Battery Status + // 1 : "Low Battery Level" + // 0 : "Normal Battery Level" + // multiplex variable + uint8_t VAU_TPMS_BatteryStatusRL : 1; // Bits= 1 + + // RR Wheel Sensor Battery Status + // 1 : "Low Battery Level" + // 0 : "Normal Battery Level" + // multiplex variable + uint8_t VAU_TPMS_BatteryStatusRR : 1; // Bits= 1 + + // FL Wheel Sensor Battery Status + // 1 : "Low Battery Level" + // 0 : "Normal Battery Level" + // multiplex variable + uint8_t VAU_TPMS_BatteryStatusFL : 1; // Bits= 1 + + // FR Wheel Sensor Battery Status + // 1 : "Low Battery Level" + // 0 : "Normal Battery Level" + // multiplex variable + uint8_t VAU_TPMS_BatteryStatusFR : 1; // Bits= 1 + + // FL Wheel Pressure Sensor Response Status + // 3 : "Mode Entry" + // 2 : "Data Pressure" + // 1 : "LF Command" + // 0 : "Regular Emission" + // multiplex variable + uint8_t VAU_TPMS_SensorEmissionCauseFL : 2; // Bits= 2 + + // RR Wheel Pressure Sensor Response Status + // 3 : "Mode Entry" + // 2 : "Data Pressure" + // 1 : "LF Command" + // 0 : "Regular Emission" + // multiplex variable + uint8_t VAU_TPMS_SensorEmissionCauseRR : 2; // Bits= 2 + + // RL Wheel Pressure Sensor Response Status + // 3 : "Mode Entry" + // 2 : "Data Pressure" + // 1 : "LF Command" + // 0 : "Regular Emission" + // multiplex variable + uint8_t VAU_TPMS_SensorEmissionCauseRL : 2; // Bits= 2 + + // FR Wheel Pressure Sensor Response Status + // 3 : "Mode Entry" + // 2 : "Data Pressure" + // 1 : "LF Command" + // 0 : "Regular Emission" + // multiplex variable + uint8_t VAU_TPMS_SensorEmissionCauseFR : 2; // Bits= 2 + + // RR wheel pressure sensor operating mode + // 3 : "Ship" + // 2 : "Test" + // 1 : "Park" + // 0 : "Drive" + // multiplex variable + uint8_t VAU_TPMS_SensorOperationModeRR : 2; // Bits= 2 + + // RL wheel pressure sensor operating mode + // 3 : "Ship" + // 2 : "Test" + // 1 : "Park" + // 0 : "Drive" + // multiplex variable + uint8_t VAU_TPMS_SensorOperationModeRL : 2; // Bits= 2 + + // FR wheel pressure sensor operating mode + // 3 : "Ship" + // 2 : "Test" + // 1 : "Park" + // 0 : "Drive" + // multiplex variable + uint8_t VAU_TPMS_SensorOperationModeFR : 2; // Bits= 2 + + // FL wheel pressure sensor operating mode + // 3 : "Ship" + // 2 : "Test" + // 1 : "Park" + // 0 : "Drive" + // multiplex variable + uint8_t VAU_TPMS_SensorOperationModeFL : 2; // Bits= 2 + + // 0x0000 - 0x0870 Time elapsed in second since the last reception of the sensor + // 0x0871 � 0xFFFF Time > 2268s + // multiplex variable + uint16_t VAU_TPMS_DataTimestampRR; // Bits=16 + + // 0x0000 - 0x0870 Time elapsed in second since the last reception of the sensor + // 0x0871 � 0xFFFF Time > 2268s + // multiplex variable + uint16_t VAU_TPMS_DataTimestampRL; // Bits=16 + + // 0x0000 - 0x0870 Time elapsed in second since the last reception of the sensor + // 0x0871 � 0xFFFF Time > 2268s + // multiplex variable + uint16_t VAU_TPMS_DataTimestampFR; // Bits=16 + + // 0x0000 - 0x0870 Time elapsed in second since the last reception of the sensor + // 0x0871 � 0xFFFF Time > 2268s + // multiplex variable + uint16_t VAU_TPMS_DataTimestampFL; // Bits=16 + + // RL Wheel Pressure Sensor Error + // 7 : "No fault" + // 6 : "Pressure acquistion error" + // 5 : "No fault" + // 4 : "Low Pressure Alert" + // 3 : "Low Pressure Warning" + // 2 : "No Pressure warning" + // 1 : "High Pressure Warning" + // 0 : "No fault" + // multiplex variable + uint8_t VAU_TPMS_TirePressureFaultRL : 3; // Bits= 3 + + // FR Wheel Pressure Sensor Error + // 7 : "No fault" + // 6 : "Pressure acquistion error" + // 5 : "No fault" + // 4 : "Low Pressure Alert" + // 3 : "Low Pressure Warning" + // 2 : "No Pressure warning" + // 1 : "High Pressure Warning" + // 0 : "No fault" + // multiplex variable + uint8_t VAU_TPMS_TirePressureFaultFR : 3; // Bits= 3 + + // FL Wheel Pressure Sensor Error + // 7 : "No fault" + // 6 : "Pressure acquistion error" + // 5 : "No fault" + // 4 : "Low Pressure Alert" + // 3 : "Low Pressure Warning" + // 2 : "No Pressure warning" + // 1 : "High Pressure Warning" + // 0 : "No fault" + // multiplex variable + uint8_t VAU_TPMS_TirePressureFaultFL : 3; // Bits= 3 + + // RR Wheel Pressure Sensor Error + // 7 : "No fault" + // 6 : "Pressure acquistion error" + // 5 : "No fault" + // 4 : "Low Pressure Alert" + // 3 : "Low Pressure Warning" + // 2 : "No Pressure warning" + // 1 : "High Pressure Warning" + // 0 : "No fault" + // multiplex variable + uint8_t VAU_TPMS_TirePressureFaultRR : 3; // Bits= 3 + + // FR Wheel Pressure Sensor Temperature Error + // 3 : "Description for the value '0x3'" + // 2 : "Description for the value '0x2'" + // 1 : "No Warning" + // 0 : "High Temp" + // multiplex variable + uint8_t TPMS_SensorTempFaultFR : 2; // Bits= 2 + + // RR Wheel Pressure Sensor Temperature Error + // 3 : "Description for the value '0x3'" + // 2 : "Description for the value '0x2'" + // 1 : "No Warning" + // 0 : "High Temp" + // multiplex variable + uint8_t TPMS_SensorTempFaultRR : 2; // Bits= 2 + + // FL Wheel Pressure Sensor Temperature Error + // 3 : "Description for the value '0x3'" + // 2 : "Description for the value '0x2'" + // 1 : "No Warning" + // 0 : "High Temp" + // multiplex variable + uint8_t TPMS_SensorTempFaultFL : 2; // Bits= 2 + + // RL Wheel Pressure Sensor Temperature Error + // 3 : "Description for the value '0x3'" + // 2 : "Description for the value '0x2'" + // 1 : "No Warning" + // 0 : "High Temp" + // multiplex variable + uint8_t TPMS_SensorTempFaultRL : 2; // Bits= 2 + + // FR Wheel Pressure Sensor Error + // 1 : "An acquision failure has occured" + // 0 : "No failure" + // multiplex variable + uint8_t VAU_TPMS_SensorFaultFR : 1; // Bits= 1 + + // RR Wheel Pressure Sensor Error + // 1 : "An acquision failure has occured" + // 0 : "No failure" + // multiplex variable + uint8_t VAU_TPMS_SensorFaultRR : 1; // Bits= 1 + + // RL Wheel Pressure Sensor Error + // 1 : "An acquision failure has occured" + // 0 : "No failure" + // multiplex variable + uint8_t VAU_TPMS_SensorFaultRL : 1; // Bits= 1 + + // FL Wheel Pressure Sensor Error + // 1 : "An acquision failure has occured" + // 0 : "No failure" + // multiplex variable + uint8_t VAU_TPMS_SensorFaultFL : 1; // Bits= 1 + + // FR Wheel Pressure Sensor Detection Status + // 1 : "Sensor Absent" + // 0 : "Sensor Detect" + // multiplex variable + uint8_t VAU_TPMS_SensorPresenceFR : 1; // Bits= 1 + + // RL Wheel Pressure Sensor Detection Status + // 1 : "Sensor Absent" + // 0 : "Sensor Detect" + // multiplex variable + uint8_t VAU_TPMS_SensorPresenceRL : 1; // Bits= 1 + + // FL Wheel Pressure Sensor Detection Status + // 1 : "Sensor Absent" + // 0 : "Sensor Detect" + // multiplex variable + uint8_t VAU_TPMS_SensorPresenceFL : 1; // Bits= 1 + + // RR Wheel Pressure Sensor Detection Status + // 1 : "Sensor Absent" + // 0 : "Sensor Detect" + // multiplex variable + uint8_t VAU_TPMS_SensorPresenceRR : 1; // Bits= 1 + +#else + + // 19 : "Rear Right tyre" + // 16 : "Rear Left tyre" + // 3 : "Front Right tyre" + // 0 : "Front Left tyre" + // MULTIPLEX master signal + uint8_t VAU_TPMS_TireLocation; // Bits= 8 + + // Indicate the measured pressure in the tyre + // multiplex variable + uint8_t VAU_TPMS_TirePressureRR_ro; // Bits= 8 Factor= 5 Unit:'kPa' + +#ifdef CANDB_USE_SIGFLOAT + uint16_t VAU_TPMS_TirePressureRR_phys; +#endif // CANDB_USE_SIGFLOAT + + // Indicate the measured pressure in the tyre + // multiplex variable + uint8_t VAU_TPMS_TirePressureRL_ro; // Bits= 8 Factor= 5 Unit:'kPa' + +#ifdef CANDB_USE_SIGFLOAT + uint16_t VAU_TPMS_TirePressureRL_phys; +#endif // CANDB_USE_SIGFLOAT + + // Indicate the measured pressure in the tyre + // multiplex variable + uint8_t VAU_TPMS_TirePressureFR_ro; // Bits= 8 Factor= 5 Unit:'kPa' + +#ifdef CANDB_USE_SIGFLOAT + uint16_t VAU_TPMS_TirePressureFR_phys; +#endif // CANDB_USE_SIGFLOAT + + // Indicate the measured pressure in the tyre + // multiplex variable + uint8_t VAU_TPMS_TirePressureFL_ro; // Bits= 8 Factor= 5 Unit:'kPa' + +#ifdef CANDB_USE_SIGFLOAT + uint16_t VAU_TPMS_TirePressureFL_phys; +#endif // CANDB_USE_SIGFLOAT + + // RR wheel temperature + // multiplex variable + uint8_t VAU_TPMS_SensorTemperatureRR_ro; // Bits= 8 Offset= -50 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + int16_t VAU_TPMS_SensorTemperatureRR_phys; +#endif // CANDB_USE_SIGFLOAT + + // RL wheel temperature + // multiplex variable + uint8_t VAU_TPMS_SensorTemperatureRL_ro; // Bits= 8 Offset= -50 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + int16_t VAU_TPMS_SensorTemperatureRL_phys; +#endif // CANDB_USE_SIGFLOAT + + // FR wheel temperature + // multiplex variable + uint8_t VAU_TPMS_SensorTemperatureFR_ro; // Bits= 8 Offset= -50 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + int16_t VAU_TPMS_SensorTemperatureFR_phys; +#endif // CANDB_USE_SIGFLOAT + + // FL wheel temperature + // multiplex variable + uint8_t VAU_TPMS_SensorTemperatureFL_ro; // Bits= 8 Offset= -50 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + int16_t VAU_TPMS_SensorTemperatureFL_phys; +#endif // CANDB_USE_SIGFLOAT + + // New nominal pressure value has been set + // 1 : "Pressure set" + // 0 : "No change" + // multiplex variable + uint8_t VAU_TPMS_PressureSetSuccessRL; // Bits= 1 + + // New nominal pressure value has been set + // 1 : "Pressure set" + // 0 : "No change" + // multiplex variable + uint8_t VAU_TPMS_PressureSetSuccessFL; // Bits= 1 + + // New nominal pressure value has been set + // 1 : "Pressure set" + // 0 : "No change" + // multiplex variable + uint8_t VAU_TPMS_PressureSetSuccessRR; // Bits= 1 + + // New nominal pressure value has been set + // 1 : "Pressure set" + // 0 : "No change" + // multiplex variable + uint8_t VAU_TPMS_PressureSetSuccessFR; // Bits= 1 + + // New nominal pressure value has not been set, check the pressure sensors + // 1 : "Pressure not set" + // 0 : "No change" + // multiplex variable + uint8_t VAU_TPMS_PressureSetSensorErrFR; // Bits= 1 + + // New nominal pressure value has not been set, check the pressure sensors + // 1 : "Pressure not set" + // 0 : "No change" + // multiplex variable + uint8_t VAU_TPMS_PressureSetSensorErrFL; // Bits= 1 + + // New nominal pressure value has not been set, check the pressure sensors + // 1 : "Pressure not set" + // 0 : "No change" + // multiplex variable + uint8_t VAU_TPMS_PressureSetSensorErrRL; // Bits= 1 + + // New nominal pressure value has not been set, check the pressure sensors + // 1 : "Pressure not set" + // 0 : "No change" + // multiplex variable + uint8_t VAU_TPMS_PressureSetSensorErrRR; // Bits= 1 + + // New nominal pressure value has not been set, check the pressure + // 1 : "Pressure not set" + // 0 : "No change" + // multiplex variable + uint8_t VAU_TPMS_PressureSetErrFR; // Bits= 1 + + // New nominal pressure value has not been set, check the pressure + // 1 : "Pressure not set" + // 0 : "No change" + // multiplex variable + uint8_t VAU_TPMS_PressureSetErrRL; // Bits= 1 + + // New nominal pressure value has not been set, check the pressure + // 1 : "Pressure not set" + // 0 : "No change" + // multiplex variable + uint8_t VAU_TPMS_PressureSetErrFL; // Bits= 1 + + // New nominal pressure value has not been set, check the pressure + // 1 : "Pressure not set" + // 0 : "No change" + // multiplex variable + uint8_t VAU_TPMS_PressureSetErrRR; // Bits= 1 + + // RL Wheel Sensor Battery Status + // 1 : "Low Battery Level" + // 0 : "Normal Battery Level" + // multiplex variable + uint8_t VAU_TPMS_BatteryStatusRL; // Bits= 1 + + // RR Wheel Sensor Battery Status + // 1 : "Low Battery Level" + // 0 : "Normal Battery Level" + // multiplex variable + uint8_t VAU_TPMS_BatteryStatusRR; // Bits= 1 + + // FL Wheel Sensor Battery Status + // 1 : "Low Battery Level" + // 0 : "Normal Battery Level" + // multiplex variable + uint8_t VAU_TPMS_BatteryStatusFL; // Bits= 1 + + // FR Wheel Sensor Battery Status + // 1 : "Low Battery Level" + // 0 : "Normal Battery Level" + // multiplex variable + uint8_t VAU_TPMS_BatteryStatusFR; // Bits= 1 + + // FL Wheel Pressure Sensor Response Status + // 3 : "Mode Entry" + // 2 : "Data Pressure" + // 1 : "LF Command" + // 0 : "Regular Emission" + // multiplex variable + uint8_t VAU_TPMS_SensorEmissionCauseFL; // Bits= 2 + + // RR Wheel Pressure Sensor Response Status + // 3 : "Mode Entry" + // 2 : "Data Pressure" + // 1 : "LF Command" + // 0 : "Regular Emission" + // multiplex variable + uint8_t VAU_TPMS_SensorEmissionCauseRR; // Bits= 2 + + // RL Wheel Pressure Sensor Response Status + // 3 : "Mode Entry" + // 2 : "Data Pressure" + // 1 : "LF Command" + // 0 : "Regular Emission" + // multiplex variable + uint8_t VAU_TPMS_SensorEmissionCauseRL; // Bits= 2 + + // FR Wheel Pressure Sensor Response Status + // 3 : "Mode Entry" + // 2 : "Data Pressure" + // 1 : "LF Command" + // 0 : "Regular Emission" + // multiplex variable + uint8_t VAU_TPMS_SensorEmissionCauseFR; // Bits= 2 + + // RR wheel pressure sensor operating mode + // 3 : "Ship" + // 2 : "Test" + // 1 : "Park" + // 0 : "Drive" + // multiplex variable + uint8_t VAU_TPMS_SensorOperationModeRR; // Bits= 2 + + // RL wheel pressure sensor operating mode + // 3 : "Ship" + // 2 : "Test" + // 1 : "Park" + // 0 : "Drive" + // multiplex variable + uint8_t VAU_TPMS_SensorOperationModeRL; // Bits= 2 + + // FR wheel pressure sensor operating mode + // 3 : "Ship" + // 2 : "Test" + // 1 : "Park" + // 0 : "Drive" + // multiplex variable + uint8_t VAU_TPMS_SensorOperationModeFR; // Bits= 2 + + // FL wheel pressure sensor operating mode + // 3 : "Ship" + // 2 : "Test" + // 1 : "Park" + // 0 : "Drive" + // multiplex variable + uint8_t VAU_TPMS_SensorOperationModeFL; // Bits= 2 + + // 0x0000 - 0x0870 Time elapsed in second since the last reception of the sensor + // 0x0871 � 0xFFFF Time > 2268s + // multiplex variable + uint16_t VAU_TPMS_DataTimestampRR; // Bits=16 + + // 0x0000 - 0x0870 Time elapsed in second since the last reception of the sensor + // 0x0871 � 0xFFFF Time > 2268s + // multiplex variable + uint16_t VAU_TPMS_DataTimestampRL; // Bits=16 + + // 0x0000 - 0x0870 Time elapsed in second since the last reception of the sensor + // 0x0871 � 0xFFFF Time > 2268s + // multiplex variable + uint16_t VAU_TPMS_DataTimestampFR; // Bits=16 + + // 0x0000 - 0x0870 Time elapsed in second since the last reception of the sensor + // 0x0871 � 0xFFFF Time > 2268s + // multiplex variable + uint16_t VAU_TPMS_DataTimestampFL; // Bits=16 + + // RL Wheel Pressure Sensor Error + // 7 : "No fault" + // 6 : "Pressure acquistion error" + // 5 : "No fault" + // 4 : "Low Pressure Alert" + // 3 : "Low Pressure Warning" + // 2 : "No Pressure warning" + // 1 : "High Pressure Warning" + // 0 : "No fault" + // multiplex variable + uint8_t VAU_TPMS_TirePressureFaultRL; // Bits= 3 + + // FR Wheel Pressure Sensor Error + // 7 : "No fault" + // 6 : "Pressure acquistion error" + // 5 : "No fault" + // 4 : "Low Pressure Alert" + // 3 : "Low Pressure Warning" + // 2 : "No Pressure warning" + // 1 : "High Pressure Warning" + // 0 : "No fault" + // multiplex variable + uint8_t VAU_TPMS_TirePressureFaultFR; // Bits= 3 + + // FL Wheel Pressure Sensor Error + // 7 : "No fault" + // 6 : "Pressure acquistion error" + // 5 : "No fault" + // 4 : "Low Pressure Alert" + // 3 : "Low Pressure Warning" + // 2 : "No Pressure warning" + // 1 : "High Pressure Warning" + // 0 : "No fault" + // multiplex variable + uint8_t VAU_TPMS_TirePressureFaultFL; // Bits= 3 + + // RR Wheel Pressure Sensor Error + // 7 : "No fault" + // 6 : "Pressure acquistion error" + // 5 : "No fault" + // 4 : "Low Pressure Alert" + // 3 : "Low Pressure Warning" + // 2 : "No Pressure warning" + // 1 : "High Pressure Warning" + // 0 : "No fault" + // multiplex variable + uint8_t VAU_TPMS_TirePressureFaultRR; // Bits= 3 + + // FR Wheel Pressure Sensor Temperature Error + // 3 : "Description for the value '0x3'" + // 2 : "Description for the value '0x2'" + // 1 : "No Warning" + // 0 : "High Temp" + // multiplex variable + uint8_t TPMS_SensorTempFaultFR; // Bits= 2 + + // RR Wheel Pressure Sensor Temperature Error + // 3 : "Description for the value '0x3'" + // 2 : "Description for the value '0x2'" + // 1 : "No Warning" + // 0 : "High Temp" + // multiplex variable + uint8_t TPMS_SensorTempFaultRR; // Bits= 2 + + // FL Wheel Pressure Sensor Temperature Error + // 3 : "Description for the value '0x3'" + // 2 : "Description for the value '0x2'" + // 1 : "No Warning" + // 0 : "High Temp" + // multiplex variable + uint8_t TPMS_SensorTempFaultFL; // Bits= 2 + + // RL Wheel Pressure Sensor Temperature Error + // 3 : "Description for the value '0x3'" + // 2 : "Description for the value '0x2'" + // 1 : "No Warning" + // 0 : "High Temp" + // multiplex variable + uint8_t TPMS_SensorTempFaultRL; // Bits= 2 + + // FR Wheel Pressure Sensor Error + // 1 : "An acquision failure has occured" + // 0 : "No failure" + // multiplex variable + uint8_t VAU_TPMS_SensorFaultFR; // Bits= 1 + + // RR Wheel Pressure Sensor Error + // 1 : "An acquision failure has occured" + // 0 : "No failure" + // multiplex variable + uint8_t VAU_TPMS_SensorFaultRR; // Bits= 1 + + // RL Wheel Pressure Sensor Error + // 1 : "An acquision failure has occured" + // 0 : "No failure" + // multiplex variable + uint8_t VAU_TPMS_SensorFaultRL; // Bits= 1 + + // FL Wheel Pressure Sensor Error + // 1 : "An acquision failure has occured" + // 0 : "No failure" + // multiplex variable + uint8_t VAU_TPMS_SensorFaultFL; // Bits= 1 + + // FR Wheel Pressure Sensor Detection Status + // 1 : "Sensor Absent" + // 0 : "Sensor Detect" + // multiplex variable + uint8_t VAU_TPMS_SensorPresenceFR; // Bits= 1 + + // RL Wheel Pressure Sensor Detection Status + // 1 : "Sensor Absent" + // 0 : "Sensor Detect" + // multiplex variable + uint8_t VAU_TPMS_SensorPresenceRL; // Bits= 1 + + // FL Wheel Pressure Sensor Detection Status + // 1 : "Sensor Absent" + // 0 : "Sensor Detect" + // multiplex variable + uint8_t VAU_TPMS_SensorPresenceFL; // Bits= 1 + + // RR Wheel Pressure Sensor Detection Status + // 1 : "Sensor Absent" + // 0 : "Sensor Detect" + // multiplex variable + uint8_t VAU_TPMS_SensorPresenceRR; // Bits= 1 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} VAU_TPMS_Msg_t; + +// def @CCU_Errors CAN Message (1278 0x4fe) +#define CCU_Errors_IDE (0U) +#define CCU_Errors_DLC (4U) +#define CCU_Errors_CANID (0x4feU) +#define CCU_Errors_CYC (1000U) + +// Value tables for @CCU_IncarTempErrF_Stat signal + +#ifndef CCU_IncarTempErrF_Stat_CCU_Errors_Error +#define CCU_IncarTempErrF_Stat_CCU_Errors_Error (1) +#endif + +#ifndef CCU_IncarTempErrF_Stat_CCU_Errors_No_error +#define CCU_IncarTempErrF_Stat_CCU_Errors_No_error (0) +#endif + + +// Value tables for @CCU_IncarTempErrR_Stat signal + +#ifndef CCU_IncarTempErrR_Stat_CCU_Errors_Error +#define CCU_IncarTempErrR_Stat_CCU_Errors_Error (1) +#endif + +#ifndef CCU_IncarTempErrR_Stat_CCU_Errors_No_error +#define CCU_IncarTempErrR_Stat_CCU_Errors_No_error (0) +#endif + + +// Value tables for @CCU_DuctTempSenErrF_Stat signal + +#ifndef CCU_DuctTempSenErrF_Stat_CCU_Errors_Error +#define CCU_DuctTempSenErrF_Stat_CCU_Errors_Error (1) +#endif + +#ifndef CCU_DuctTempSenErrF_Stat_CCU_Errors_No_error +#define CCU_DuctTempSenErrF_Stat_CCU_Errors_No_error (0) +#endif + + +// Value tables for @CCU_DuctTempSenErrR_Stat signal + +#ifndef CCU_DuctTempSenErrR_Stat_CCU_Errors_Error +#define CCU_DuctTempSenErrR_Stat_CCU_Errors_Error (1) +#endif + +#ifndef CCU_DuctTempSenErrR_Stat_CCU_Errors_No_error +#define CCU_DuctTempSenErrR_Stat_CCU_Errors_No_error (0) +#endif + + +// Value tables for @CCU_EvaTempSenErrF_Stat signal + +#ifndef CCU_EvaTempSenErrF_Stat_CCU_Errors_Error +#define CCU_EvaTempSenErrF_Stat_CCU_Errors_Error (1) +#endif + +#ifndef CCU_EvaTempSenErrF_Stat_CCU_Errors_No_error +#define CCU_EvaTempSenErrF_Stat_CCU_Errors_No_error (0) +#endif + + +// Value tables for @CCU_EvaTempSenErrR_Stat signal + +#ifndef CCU_EvaTempSenErrR_Stat_CCU_Errors_Error +#define CCU_EvaTempSenErrR_Stat_CCU_Errors_Error (1) +#endif + +#ifndef CCU_EvaTempSenErrR_Stat_CCU_Errors_No_error +#define CCU_EvaTempSenErrR_Stat_CCU_Errors_No_error (0) +#endif + + +// Value tables for @CCU_DeflectorSwErrF_Stat signal + +#ifndef CCU_DeflectorSwErrF_Stat_CCU_Errors_Error +#define CCU_DeflectorSwErrF_Stat_CCU_Errors_Error (1) +#endif + +#ifndef CCU_DeflectorSwErrF_Stat_CCU_Errors_No_error +#define CCU_DeflectorSwErrF_Stat_CCU_Errors_No_error (0) +#endif + + +// Value tables for @CCU_DeflectorSwErrR_Stat signal + +#ifndef CCU_DeflectorSwErrR_Stat_CCU_Errors_Error +#define CCU_DeflectorSwErrR_Stat_CCU_Errors_Error (1) +#endif + +#ifndef CCU_DeflectorSwErrR_Stat_CCU_Errors_No_error +#define CCU_DeflectorSwErrR_Stat_CCU_Errors_No_error (0) +#endif + + +// Value tables for @CCU_PressSenErr_Stat signal + +#ifndef CCU_PressSenErr_Stat_CCU_Errors_Error +#define CCU_PressSenErr_Stat_CCU_Errors_Error (1) +#endif + +#ifndef CCU_PressSenErr_Stat_CCU_Errors_No_error +#define CCU_PressSenErr_Stat_CCU_Errors_No_error (0) +#endif + + +// Value tables for @CCU_AmbienTemptSenErr_Stat signal + +#ifndef CCU_AmbienTemptSenErr_Stat_CCU_Errors_Error +#define CCU_AmbienTemptSenErr_Stat_CCU_Errors_Error (1) +#endif + +#ifndef CCU_AmbienTemptSenErr_Stat_CCU_Errors_No_error +#define CCU_AmbienTemptSenErr_Stat_CCU_Errors_No_error (0) +#endif + + +// Value tables for @CCU_SealingValveErr_Stat signal + +#ifndef CCU_SealingValveErr_Stat_CCU_Errors_Error +#define CCU_SealingValveErr_Stat_CCU_Errors_Error (1) +#endif + +#ifndef CCU_SealingValveErr_Stat_CCU_Errors_No_error +#define CCU_SealingValveErr_Stat_CCU_Errors_No_error (0) +#endif + + +// Value tables for @CCU_ETXVerr_Stat signal + +#ifndef CCU_ETXVerr_Stat_CCU_Errors_Error +#define CCU_ETXVerr_Stat_CCU_Errors_Error (1) +#endif + +#ifndef CCU_ETXVerr_Stat_CCU_Errors_No_error +#define CCU_ETXVerr_Stat_CCU_Errors_No_error (0) +#endif + + +// Value tables for @CCU_HVACfanOrTXVerrF_Stat signal + +#ifndef CCU_HVACfanOrTXVerrF_Stat_CCU_Errors_Error +#define CCU_HVACfanOrTXVerrF_Stat_CCU_Errors_Error (1) +#endif + +#ifndef CCU_HVACfanOrTXVerrF_Stat_CCU_Errors_No_error +#define CCU_HVACfanOrTXVerrF_Stat_CCU_Errors_No_error (0) +#endif + + +// Value tables for @CCU_HVACfanOrTXVerrR_Stat signal + +#ifndef CCU_HVACfanOrTXVerrR_Stat_CCU_Errors_Error +#define CCU_HVACfanOrTXVerrR_Stat_CCU_Errors_Error (1) +#endif + +#ifndef CCU_HVACfanOrTXVerrR_Stat_CCU_Errors_No_error +#define CCU_HVACfanOrTXVerrR_Stat_CCU_Errors_No_error (0) +#endif + + +// Value tables for @CCU_ActuatorErrF_Stat signal + +#ifndef CCU_ActuatorErrF_Stat_CCU_Errors_Error +#define CCU_ActuatorErrF_Stat_CCU_Errors_Error (1) +#endif + +#ifndef CCU_ActuatorErrF_Stat_CCU_Errors_No_error +#define CCU_ActuatorErrF_Stat_CCU_Errors_No_error (0) +#endif + + +// Value tables for @CCU_ActuatorErrR_Stat signal + +#ifndef CCU_ActuatorErrR_Stat_CCU_Errors_Error +#define CCU_ActuatorErrR_Stat_CCU_Errors_Error (1) +#endif + +#ifndef CCU_ActuatorErrR_Stat_CCU_Errors_No_error +#define CCU_ActuatorErrR_Stat_CCU_Errors_No_error (0) +#endif + + +// Value tables for @CCU_UltravioletErr_Stat signal + +#ifndef CCU_UltravioletErr_Stat_CCU_Errors_Component_malfunction +#define CCU_UltravioletErr_Stat_CCU_Errors_Component_malfunction (3) +#endif + +#ifndef CCU_UltravioletErr_Stat_CCU_Errors_Supply_chain_short_circuit +#define CCU_UltravioletErr_Stat_CCU_Errors_Supply_chain_short_circuit (2) +#endif + +#ifndef CCU_UltravioletErr_Stat_CCU_Errors_Supply_chain_break +#define CCU_UltravioletErr_Stat_CCU_Errors_Supply_chain_break (1) +#endif + +#ifndef CCU_UltravioletErr_Stat_CCU_Errors_No_error +#define CCU_UltravioletErr_Stat_CCU_Errors_No_error (0) +#endif + + +// Value tables for @CCU_VinRecordErr_Stat signal + +#ifndef CCU_VinRecordErr_Stat_CCU_Errors_Error +#define CCU_VinRecordErr_Stat_CCU_Errors_Error (1) +#endif + +#ifndef CCU_VinRecordErr_Stat_CCU_Errors_No_error +#define CCU_VinRecordErr_Stat_CCU_Errors_No_error (0) +#endif + + +// Value tables for @CCU_AirQualSenErr_Stat signal + +#ifndef CCU_AirQualSenErr_Stat_CCU_Errors_Component_malfunction +#define CCU_AirQualSenErr_Stat_CCU_Errors_Component_malfunction (4) +#endif + +#ifndef CCU_AirQualSenErr_Stat_CCU_Errors_Communication_error +#define CCU_AirQualSenErr_Stat_CCU_Errors_Communication_error (3) +#endif + +#ifndef CCU_AirQualSenErr_Stat_CCU_Errors_Supply_chain_short_circuit +#define CCU_AirQualSenErr_Stat_CCU_Errors_Supply_chain_short_circuit (2) +#endif + +#ifndef CCU_AirQualSenErr_Stat_CCU_Errors_Supply_chain_break +#define CCU_AirQualSenErr_Stat_CCU_Errors_Supply_chain_break (1) +#endif + +#ifndef CCU_AirQualSenErr_Stat_CCU_Errors_No_error +#define CCU_AirQualSenErr_Stat_CCU_Errors_No_error (0) +#endif + + +// Value tables for @CCU_CommErr_Stat signal + +#ifndef CCU_CommErr_Stat_CCU_Errors_Error +#define CCU_CommErr_Stat_CCU_Errors_Error (1) +#endif + +#ifndef CCU_CommErr_Stat_CCU_Errors_No_error +#define CCU_CommErr_Stat_CCU_Errors_No_error (0) +#endif + + +// Value tables for @CCU_TWVerr_Stat signal + +#ifndef CCU_TWVerr_Stat_CCU_Errors_Error +#define CCU_TWVerr_Stat_CCU_Errors_Error (1) +#endif + +#ifndef CCU_TWVerr_Stat_CCU_Errors_No_error +#define CCU_TWVerr_Stat_CCU_Errors_No_error (0) +#endif + + +// Value tables for @CCU_IonizationErr_Stat signal + +#ifndef CCU_IonizationErr_Stat_CCU_Errors_Component_malfunction +#define CCU_IonizationErr_Stat_CCU_Errors_Component_malfunction (4) +#endif + +#ifndef CCU_IonizationErr_Stat_CCU_Errors_Communication_error +#define CCU_IonizationErr_Stat_CCU_Errors_Communication_error (3) +#endif + +#ifndef CCU_IonizationErr_Stat_CCU_Errors_Supply_chain_short_circuit +#define CCU_IonizationErr_Stat_CCU_Errors_Supply_chain_short_circuit (2) +#endif + +#ifndef CCU_IonizationErr_Stat_CCU_Errors_Supply_chain_break +#define CCU_IonizationErr_Stat_CCU_Errors_Supply_chain_break (1) +#endif + +#ifndef CCU_IonizationErr_Stat_CCU_Errors_No_error +#define CCU_IonizationErr_Stat_CCU_Errors_No_error (0) +#endif + + +// Value tables for @CCU_AromaErr_Stat signal + +#ifndef CCU_AromaErr_Stat_CCU_Errors_Component_malfunction +#define CCU_AromaErr_Stat_CCU_Errors_Component_malfunction (4) +#endif + +#ifndef CCU_AromaErr_Stat_CCU_Errors_Communication_error +#define CCU_AromaErr_Stat_CCU_Errors_Communication_error (3) +#endif + +#ifndef CCU_AromaErr_Stat_CCU_Errors_Supply_chain_short_circuit +#define CCU_AromaErr_Stat_CCU_Errors_Supply_chain_short_circuit (2) +#endif + +#ifndef CCU_AromaErr_Stat_CCU_Errors_Supply_chain_break +#define CCU_AromaErr_Stat_CCU_Errors_Supply_chain_break (1) +#endif + +#ifndef CCU_AromaErr_Stat_CCU_Errors_No_error +#define CCU_AromaErr_Stat_CCU_Errors_No_error (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Incar temperature sensors for front zone error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_IncarTempErrF_Stat : 1; // Bits= 1 + + // Incar temperature sensors for rear zone error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_IncarTempErrR_Stat : 1; // Bits= 1 + + // Duct temperature sensors for front zone error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_DuctTempSenErrF_Stat : 1; // Bits= 1 + + // Duct temperature sensors for rear zone error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_DuctTempSenErrR_Stat : 1; // Bits= 1 + + // Evaporator temperature sensor for front zone error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_EvaTempSenErrF_Stat : 1; // Bits= 1 + + // Evaporator temperature sensor for rear zone error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_EvaTempSenErrR_Stat : 1; // Bits= 1 + + // Deflectors for front zone error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_DeflectorSwErrF_Stat : 1; // Bits= 1 + + // Deflectors for rear zone error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_DeflectorSwErrR_Stat : 1; // Bits= 1 + + // Pressure sensors error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_PressSenErr_Stat : 1; // Bits= 1 + + // Ambient temperature sensor error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_AmbienTemptSenErr_Stat : 1; // Bits= 1 + + // Sealing valve error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_SealingValveErr_Stat : 1; // Bits= 1 + + // ETXV error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_ETXVerr_Stat : 1; // Bits= 1 + + // HVAC fan or TXV for front zone error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_HVACfanOrTXVerrF_Stat : 1; // Bits= 1 + + // HVAC fan or TXV for rear zone error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_HVACfanOrTXVerrR_Stat : 1; // Bits= 1 + + // Actuators for front zone error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_ActuatorErrF_Stat : 1; // Bits= 1 + + // Actuators for rear zone error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_ActuatorErrR_Stat : 1; // Bits= 1 + + // Ultraviolet system error status + // 3 : "Component malfunction" + // 2 : "Supply chain short circuit + + // 1 : "Supply chain break + + // 0 : "No error" + uint8_t CCU_UltravioletErr_Stat : 2; // Bits= 2 + + // CCU VIN record error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_VinRecordErr_Stat : 1; // Bits= 1 + + // Air quality sensor error status + // 4 : "Component malfunction" + // 3 : "Communication error" + // 2 : "Supply chain short circuit" + // 1 : "Supply chain break" + // 0 : "No error" + uint8_t CCU_AirQualSenErr_Stat : 3; // Bits= 3 + + // CCU communication error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_CommErr_Stat : 1; // Bits= 1 + + // Two-way valve error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_TWVerr_Stat : 1; // Bits= 1 + + // Ionization system error status + // 4 : "Component malfunction" + // 3 : "Communication error + + // 2 : "Supply chain short circuit + + // 1 : "Supply chain break + + // 0 : "No error" + uint8_t CCU_IonizationErr_Stat : 3; // Bits= 3 + + // Aromatization system error status + // 4 : "Component malfunction" + // 3 : "Communication error + + // 2 : "Supply chain short circuit + + // 1 : "Supply chain break + + // 0 : "No error" + uint8_t CCU_AromaErr_Stat : 3; // Bits= 3 + +#else + + // Incar temperature sensors for front zone error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_IncarTempErrF_Stat; // Bits= 1 + + // Incar temperature sensors for rear zone error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_IncarTempErrR_Stat; // Bits= 1 + + // Duct temperature sensors for front zone error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_DuctTempSenErrF_Stat; // Bits= 1 + + // Duct temperature sensors for rear zone error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_DuctTempSenErrR_Stat; // Bits= 1 + + // Evaporator temperature sensor for front zone error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_EvaTempSenErrF_Stat; // Bits= 1 + + // Evaporator temperature sensor for rear zone error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_EvaTempSenErrR_Stat; // Bits= 1 + + // Deflectors for front zone error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_DeflectorSwErrF_Stat; // Bits= 1 + + // Deflectors for rear zone error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_DeflectorSwErrR_Stat; // Bits= 1 + + // Pressure sensors error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_PressSenErr_Stat; // Bits= 1 + + // Ambient temperature sensor error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_AmbienTemptSenErr_Stat; // Bits= 1 + + // Sealing valve error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_SealingValveErr_Stat; // Bits= 1 + + // ETXV error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_ETXVerr_Stat; // Bits= 1 + + // HVAC fan or TXV for front zone error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_HVACfanOrTXVerrF_Stat; // Bits= 1 + + // HVAC fan or TXV for rear zone error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_HVACfanOrTXVerrR_Stat; // Bits= 1 + + // Actuators for front zone error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_ActuatorErrF_Stat; // Bits= 1 + + // Actuators for rear zone error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_ActuatorErrR_Stat; // Bits= 1 + + // Ultraviolet system error status + // 3 : "Component malfunction" + // 2 : "Supply chain short circuit + + // 1 : "Supply chain break + + // 0 : "No error" + uint8_t CCU_UltravioletErr_Stat; // Bits= 2 + + // CCU VIN record error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_VinRecordErr_Stat; // Bits= 1 + + // Air quality sensor error status + // 4 : "Component malfunction" + // 3 : "Communication error" + // 2 : "Supply chain short circuit" + // 1 : "Supply chain break" + // 0 : "No error" + uint8_t CCU_AirQualSenErr_Stat; // Bits= 3 + + // CCU communication error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_CommErr_Stat; // Bits= 1 + + // Two-way valve error status + // 1 : "Error" + // 0 : "No error" + uint8_t CCU_TWVerr_Stat; // Bits= 1 + + // Ionization system error status + // 4 : "Component malfunction" + // 3 : "Communication error + + // 2 : "Supply chain short circuit + + // 1 : "Supply chain break + + // 0 : "No error" + uint8_t CCU_IonizationErr_Stat; // Bits= 3 + + // Aromatization system error status + // 4 : "Component malfunction" + // 3 : "Communication error + + // 2 : "Supply chain short circuit + + // 1 : "Supply chain break + + // 0 : "No error" + uint8_t CCU_AromaErr_Stat; // Bits= 3 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} CCU_Errors_t; + +// def @CCU_Msg3 CAN Message (1281 0x501) +#define CCU_Msg3_IDE (0U) +#define CCU_Msg3_DLC (5U) +#define CCU_Msg3_CANID (0x501U) +#define CCU_Msg3_CYC (500U) + +// Value tables for @CCU_FAN_Req signal + +#ifndef CCU_FAN_Req_CCU_Msg3_Error +#define CCU_FAN_Req_CCU_Msg3_Error (127) +#endif + + +// Value tables for @CCU_RestMode_Stat signal + +#ifndef CCU_RestMode_Stat_CCU_Msg3_Inactive +#define CCU_RestMode_Stat_CCU_Msg3_Inactive (3) +#endif + +#ifndef CCU_RestMode_Stat_CCU_Msg3_Active +#define CCU_RestMode_Stat_CCU_Msg3_Active (2) +#endif + +#ifndef CCU_RestMode_Stat_CCU_Msg3_Standby +#define CCU_RestMode_Stat_CCU_Msg3_Standby (1) +#endif + +#ifndef CCU_RestMode_Stat_CCU_Msg3_Not_requested +#define CCU_RestMode_Stat_CCU_Msg3_Not_requested (0) +#endif + +// signal: @CCU_IncarTempSum_Val_ro +#define CANDB_CCU_IncarTempSum_Val_ro_CovFactor (0.5) +#define CANDB_CCU_IncarTempSum_Val_ro_toS(x) ( (uint8_t) (((x) - (-50.0)) / (0.5)) ) +#define CANDB_CCU_IncarTempSum_Val_ro_fromS(x) ( (((x) * (0.5)) + (-50.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Indicates the requested FAN speed from CCU system. + // 127 : "Error" + uint8_t CCU_FAN_Req : 7; // Bits= 7 Unit:'%' + + // CCU REST mode status + // 3 : "Inactive" + // 2 : "Active" + // 1 : "Standby" + // 0 : "Not requested" + uint8_t CCU_RestMode_Stat : 2; // Bits= 2 + + // Arithmetic mean air temperature inside the car + uint8_t CCU_IncarTempSum_Val_ro; // Bits= 8 Offset= -50.0 Factor= 0.5 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t CCU_IncarTempSum_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Rolling Counter [0 - 15] + uint8_t CCU_MSG3_RC : 4; // Bits= 4 + + // Checksum XOR8 of the data field this message + // Checksum computed as per XOR algorithm: + // Byte 1 XOR byte 2 .... XOR byte n-1. (n = packet length.) + uint8_t CCU_MSG3_CS; // Bits= 8 + +#else + + // Indicates the requested FAN speed from CCU system. + // 127 : "Error" + uint8_t CCU_FAN_Req; // Bits= 7 Unit:'%' + + // CCU REST mode status + // 3 : "Inactive" + // 2 : "Active" + // 1 : "Standby" + // 0 : "Not requested" + uint8_t CCU_RestMode_Stat; // Bits= 2 + + // Arithmetic mean air temperature inside the car + uint8_t CCU_IncarTempSum_Val_ro; // Bits= 8 Offset= -50.0 Factor= 0.5 Unit:'�C' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t CCU_IncarTempSum_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Rolling Counter [0 - 15] + uint8_t CCU_MSG3_RC; // Bits= 4 + + // Checksum XOR8 of the data field this message + // Checksum computed as per XOR algorithm: + // Byte 1 XOR byte 2 .... XOR byte n-1. (n = packet length.) + uint8_t CCU_MSG3_CS; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} CCU_Msg3_t; + +// def @FIU_Cmd CAN Message (1291 0x50b) +#define FIU_Cmd_IDE (0U) +#define FIU_Cmd_DLC (4U) +#define FIU_Cmd_CANID (0x50bU) + +// Value tables for @FIU_RunningBoards_Stat signal + +#ifndef FIU_RunningBoards_Stat_FIU_Cmd_Unfolded +#define FIU_RunningBoards_Stat_FIU_Cmd_Unfolded (2) +#endif + +#ifndef FIU_RunningBoards_Stat_FIU_Cmd_Folded +#define FIU_RunningBoards_Stat_FIU_Cmd_Folded (1) +#endif + +#ifndef FIU_RunningBoards_Stat_FIU_Cmd_Auto +#define FIU_RunningBoards_Stat_FIU_Cmd_Auto (0) +#endif + + +// Value tables for @FIU_Vehicle_DrvMode_Req signal + +#ifndef FIU_Vehicle_DrvMode_Req_FIU_Cmd_Charge +#define FIU_Vehicle_DrvMode_Req_FIU_Cmd_Charge (7) +#endif + +#ifndef FIU_Vehicle_DrvMode_Req_FIU_Cmd_Electric +#define FIU_Vehicle_DrvMode_Req_FIU_Cmd_Electric (6) +#endif + +#ifndef FIU_Vehicle_DrvMode_Req_FIU_Cmd_Reserved +#define FIU_Vehicle_DrvMode_Req_FIU_Cmd_Reserved (5) +#endif + +#ifndef FIU_Vehicle_DrvMode_Req_FIU_Cmd_Offroad +#define FIU_Vehicle_DrvMode_Req_FIU_Cmd_Offroad (4) +#endif + +#ifndef FIU_Vehicle_DrvMode_Req_FIU_Cmd_Reserved +#define FIU_Vehicle_DrvMode_Req_FIU_Cmd_Reserved (3) +#endif + +#ifndef FIU_Vehicle_DrvMode_Req_FIU_Cmd_Range +#define FIU_Vehicle_DrvMode_Req_FIU_Cmd_Range (2) +#endif + +#ifndef FIU_Vehicle_DrvMode_Req_FIU_Cmd_Dynamic +#define FIU_Vehicle_DrvMode_Req_FIU_Cmd_Dynamic (1) +#endif + +#ifndef FIU_Vehicle_DrvMode_Req_FIU_Cmd_Comfort +#define FIU_Vehicle_DrvMode_Req_FIU_Cmd_Comfort (0) +#endif + + +// Value tables for @FIU_RStrapCntrl_Req signal + +#ifndef FIU_RStrapCntrl_Req_FIU_Cmd_Active +#define FIU_RStrapCntrl_Req_FIU_Cmd_Active (1) +#endif + +#ifndef FIU_RStrapCntrl_Req_FIU_Cmd_Inactive +#define FIU_RStrapCntrl_Req_FIU_Cmd_Inactive (0) +#endif + + +// Value tables for @FIU_RStrapCushCntrl_Req signal + +#ifndef FIU_RStrapCushCntrl_Req_FIU_Cmd_Active +#define FIU_RStrapCushCntrl_Req_FIU_Cmd_Active (1) +#endif + +#ifndef FIU_RStrapCushCntrl_Req_FIU_Cmd_Inactive +#define FIU_RStrapCushCntrl_Req_FIU_Cmd_Inactive (0) +#endif + + +// Value tables for @FIU_LStrapCntrl_Req signal + +#ifndef FIU_LStrapCntrl_Req_FIU_Cmd_Active +#define FIU_LStrapCntrl_Req_FIU_Cmd_Active (1) +#endif + +#ifndef FIU_LStrapCntrl_Req_FIU_Cmd_Inactive +#define FIU_LStrapCntrl_Req_FIU_Cmd_Inactive (0) +#endif + + +// Value tables for @FIU_LStrapCushCntrl_Req signal + +#ifndef FIU_LStrapCushCntrl_Req_FIU_Cmd_Active +#define FIU_LStrapCushCntrl_Req_FIU_Cmd_Active (1) +#endif + +#ifndef FIU_LStrapCushCntrl_Req_FIU_Cmd_Inactive +#define FIU_LStrapCushCntrl_Req_FIU_Cmd_Inactive (0) +#endif + + +// Value tables for @FIU_Lift_Req signal + +#ifndef FIU_Lift_Req_FIU_Cmd_Active +#define FIU_Lift_Req_FIU_Cmd_Active (1) +#endif + +#ifndef FIU_Lift_Req_FIU_Cmd_Inactive +#define FIU_Lift_Req_FIU_Cmd_Inactive (0) +#endif + + +// Value tables for @FIU_HDC_Req signal + +#ifndef FIU_HDC_Req_FIU_Cmd_Active +#define FIU_HDC_Req_FIU_Cmd_Active (1) +#endif + +#ifndef FIU_HDC_Req_FIU_Cmd_Inactive +#define FIU_HDC_Req_FIU_Cmd_Inactive (0) +#endif + + +// Value tables for @FIU_Prolongation_Req signal + +#ifndef FIU_Prolongation_Req_FIU_Cmd_Active +#define FIU_Prolongation_Req_FIU_Cmd_Active (1) +#endif + +#ifndef FIU_Prolongation_Req_FIU_Cmd_Inactive +#define FIU_Prolongation_Req_FIU_Cmd_Inactive (0) +#endif + + +// Value tables for @FIU_ServiceMode_Req signal + +#ifndef FIU_ServiceMode_Req_FIU_Cmd_Active +#define FIU_ServiceMode_Req_FIU_Cmd_Active (1) +#endif + +#ifndef FIU_ServiceMode_Req_FIU_Cmd_Inactive +#define FIU_ServiceMode_Req_FIU_Cmd_Inactive (0) +#endif + + +// Value tables for @FIU_PressureSet_Req signal + +#ifndef FIU_PressureSet_Req_FIU_Cmd_Button_pressed +#define FIU_PressureSet_Req_FIU_Cmd_Button_pressed (1) +#endif + +#ifndef FIU_PressureSet_Req_FIU_Cmd_Not_pressed +#define FIU_PressureSet_Req_FIU_Cmd_Not_pressed (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Thresholds status: + // 0x0 - thresholds shall be automatic + // 0x1 - threshholds shall be alwasys fold + // 0x2 - thresholds shall be always unfold + // 2 : "Unfolded" + // 1 : "Folded" + // 0 : "Auto" + uint8_t FIU_RunningBoards_Stat : 2; // Bits= 2 + + // Vehicle drive mode request + // 7 : "Charge" + // 6 : "Electric" + // 5 : "Reserved" + // 4 : "Offroad" + // 3 : "Reserved" + // 2 : "Range" + // 1 : "Dynamic" + // 0 : "Comfort" + uint8_t FIU_Vehicle_DrvMode_Req : 3; // Bits= 3 + + // Right straponten control request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_RStrapCntrl_Req : 1; // Bits= 1 + + // Right cushion straponten control request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_RStrapCushCntrl_Req : 1; // Bits= 1 + + // Left straponten control request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_LStrapCntrl_Req : 1; // Bits= 1 + + // Left cushion straponten control request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_LStrapCushCntrl_Req : 1; // Bits= 1 + + // Suspension lift request. When button is pressed, send a impulse signal. + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_Lift_Req : 1; // Bits= 1 + + // Hill descent control activation request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_HDC_Req : 1; // Bits= 1 + + // When Vehicle Mode State is Standby and user interacts with FIU the request is set to Active + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_Prolongation_Req : 1; // Bits= 1 + + // Suspension service mod request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_ServiceMode_Req : 1; // Bits= 1 + + // Set new target pressure. + // 0x0 = nothing shall happens. + // 0x1 = then new target pressure shall be set. + // 1 : "Button pressed" + // 0 : "Not pressed" + uint8_t FIU_PressureSet_Req : 1; // Bits= 1 + +#else + + // Thresholds status: + // 0x0 - thresholds shall be automatic + // 0x1 - threshholds shall be alwasys fold + // 0x2 - thresholds shall be always unfold + // 2 : "Unfolded" + // 1 : "Folded" + // 0 : "Auto" + uint8_t FIU_RunningBoards_Stat; // Bits= 2 + + // Vehicle drive mode request + // 7 : "Charge" + // 6 : "Electric" + // 5 : "Reserved" + // 4 : "Offroad" + // 3 : "Reserved" + // 2 : "Range" + // 1 : "Dynamic" + // 0 : "Comfort" + uint8_t FIU_Vehicle_DrvMode_Req; // Bits= 3 + + // Right straponten control request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_RStrapCntrl_Req; // Bits= 1 + + // Right cushion straponten control request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_RStrapCushCntrl_Req; // Bits= 1 + + // Left straponten control request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_LStrapCntrl_Req; // Bits= 1 + + // Left cushion straponten control request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_LStrapCushCntrl_Req; // Bits= 1 + + // Suspension lift request. When button is pressed, send a impulse signal. + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_Lift_Req; // Bits= 1 + + // Hill descent control activation request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_HDC_Req; // Bits= 1 + + // When Vehicle Mode State is Standby and user interacts with FIU the request is set to Active + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_Prolongation_Req; // Bits= 1 + + // Suspension service mod request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_ServiceMode_Req; // Bits= 1 + + // Set new target pressure. + // 0x0 = nothing shall happens. + // 0x1 = then new target pressure shall be set. + // 1 : "Button pressed" + // 0 : "Not pressed" + uint8_t FIU_PressureSet_Req; // Bits= 1 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} FIU_Cmd_t; + +// def @IC_SDM_Info CAN Message (1294 0x50e) +#define IC_SDM_Info_IDE (0U) +#define IC_SDM_Info_DLC (8U) +#define IC_SDM_Info_CANID (0x50eU) +#define IC_SDM_Info_CYC (500U) +// signal: @IC_AverageConsumpUser_ro +#define CANDB_IC_AverageConsumpUser_ro_CovFactor (0.1) +#define CANDB_IC_AverageConsumpUser_ro_toS(x) ( (uint16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_IC_AverageConsumpUser_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @IC_AverageConsumpTrip_ro +#define CANDB_IC_AverageConsumpTrip_ro_CovFactor (0.1) +#define CANDB_IC_AverageConsumpTrip_ro_toS(x) ( (uint16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_IC_AverageConsumpTrip_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @IC_UserRange_ro +#define CANDB_IC_UserRange_ro_CovFactor (0.1) +#define CANDB_IC_UserRange_ro_toS(x) ( (uint32_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_IC_UserRange_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @IC_TripRange_ro +#define CANDB_IC_TripRange_ro_CovFactor (0.1) +#define CANDB_IC_TripRange_ro_toS(x) ( (uint32_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_IC_TripRange_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @IC_UserAverageSpeed_ro +#define CANDB_IC_UserAverageSpeed_ro_CovFactor (0.1) +#define CANDB_IC_UserAverageSpeed_ro_toS(x) ( (uint16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_IC_UserAverageSpeed_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @IC_TripAverageSpeed_ro +#define CANDB_IC_TripAverageSpeed_ro_CovFactor (0.1) +#define CANDB_IC_TripAverageSpeed_ro_toS(x) ( (uint16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_IC_TripAverageSpeed_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +// Value tables for @IC_TCCU_Mult signal + +#ifndef IC_TCCU_Mult_IC_SDM_Info_IC_TCCU_User +#define IC_TCCU_Mult_IC_SDM_Info_IC_TCCU_User (1) +#endif + +#ifndef IC_TCCU_Mult_IC_SDM_Info_IC_TCCU_Trip +#define IC_TCCU_Mult_IC_SDM_Info_IC_TCCU_Trip (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // User average consamption in l/100Km, step 0.1 liter/100 Km + // multiplex variable + uint16_t IC_AverageConsumpUser_ro; // Bits=10 Factor= 0.1 Unit:'l/km' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t IC_AverageConsumpUser_phys; +#endif // CANDB_USE_SIGFLOAT + + // Trip average consamption in l/100Km, step 0.1 liter/100 Km + // multiplex variable + uint16_t IC_AverageConsumpTrip_ro; // Bits=10 Factor= 0.1 Unit:'l/km' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t IC_AverageConsumpTrip_phys; +#endif // CANDB_USE_SIGFLOAT + + // User Range in Km + // multiplex variable + uint32_t IC_UserRange_ro; // Bits=17 Factor= 0.1 Unit:'km' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t IC_UserRange_phys; +#endif // CANDB_USE_SIGFLOAT + + // Trip Range in Km + // multiplex variable + uint32_t IC_TripRange_ro; // Bits=17 Factor= 0.1 Unit:'km' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t IC_TripRange_phys; +#endif // CANDB_USE_SIGFLOAT + + // User Average Speed + // multiplex variable + uint16_t IC_UserAverageSpeed_ro; // Bits=14 Factor= 0.1 Unit:'km/h' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t IC_UserAverageSpeed_phys; +#endif // CANDB_USE_SIGFLOAT + + // Trip Average Speed + // multiplex variable + uint16_t IC_TripAverageSpeed_ro; // Bits=14 Factor= 0.1 Unit:'km/h' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t IC_TripAverageSpeed_phys; +#endif // CANDB_USE_SIGFLOAT + + // User minutes + // multiplex variable + uint8_t IC_UserMinute : 6; // Bits= 6 Unit:'min' + + // Trip minutes + // multiplex variable + uint8_t IC_TripMinute : 6; // Bits= 6 Unit:'min' + + // Hours of User + // multiplex variable + uint8_t IC_UserHour : 5; // Bits= 5 Unit:'h' + + // Hours of trip + // multiplex variable + uint8_t IC_TripHour : 5; // Bits= 5 Unit:'h' + + // User days + // multiplex variable + uint16_t IC_UserDay; // Bits=10 + + // Trip days + // multiplex variable + uint16_t IC_TripDay; // Bits=10 + + // Trip/User multiplexor + // 1 : "IC_TCCU_User" + // 0 : "IC_TCCU_Trip" + // MULTIPLEX master signal + uint8_t IC_TCCU_Mult : 1; // Bits= 1 + +#else + + // User average consamption in l/100Km, step 0.1 liter/100 Km + // multiplex variable + uint16_t IC_AverageConsumpUser_ro; // Bits=10 Factor= 0.1 Unit:'l/km' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t IC_AverageConsumpUser_phys; +#endif // CANDB_USE_SIGFLOAT + + // Trip average consamption in l/100Km, step 0.1 liter/100 Km + // multiplex variable + uint16_t IC_AverageConsumpTrip_ro; // Bits=10 Factor= 0.1 Unit:'l/km' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t IC_AverageConsumpTrip_phys; +#endif // CANDB_USE_SIGFLOAT + + // User Range in Km + // multiplex variable + uint32_t IC_UserRange_ro; // Bits=17 Factor= 0.1 Unit:'km' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t IC_UserRange_phys; +#endif // CANDB_USE_SIGFLOAT + + // Trip Range in Km + // multiplex variable + uint32_t IC_TripRange_ro; // Bits=17 Factor= 0.1 Unit:'km' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t IC_TripRange_phys; +#endif // CANDB_USE_SIGFLOAT + + // User Average Speed + // multiplex variable + uint16_t IC_UserAverageSpeed_ro; // Bits=14 Factor= 0.1 Unit:'km/h' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t IC_UserAverageSpeed_phys; +#endif // CANDB_USE_SIGFLOAT + + // Trip Average Speed + // multiplex variable + uint16_t IC_TripAverageSpeed_ro; // Bits=14 Factor= 0.1 Unit:'km/h' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t IC_TripAverageSpeed_phys; +#endif // CANDB_USE_SIGFLOAT + + // User minutes + // multiplex variable + uint8_t IC_UserMinute; // Bits= 6 Unit:'min' + + // Trip minutes + // multiplex variable + uint8_t IC_TripMinute; // Bits= 6 Unit:'min' + + // Hours of User + // multiplex variable + uint8_t IC_UserHour; // Bits= 5 Unit:'h' + + // Hours of trip + // multiplex variable + uint8_t IC_TripHour; // Bits= 5 Unit:'h' + + // User days + // multiplex variable + uint16_t IC_UserDay; // Bits=10 + + // Trip days + // multiplex variable + uint16_t IC_TripDay; // Bits=10 + + // Trip/User multiplexor + // 1 : "IC_TCCU_User" + // 0 : "IC_TCCU_Trip" + // MULTIPLEX master signal + uint8_t IC_TCCU_Mult; // Bits= 1 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} IC_SDM_Info_t; + +// def @SDM_Cmd CAN Message (1295 0x50f) +#define SDM_Cmd_IDE (0U) +#define SDM_Cmd_DLC (6U) +#define SDM_Cmd_CANID (0x50fU) + +// Value tables for @SDM_ExteriorKeyFobSw_Req signal + +#ifndef SDM_ExteriorKeyFobSw_Req_SDM_Cmd_REMOTE_START_PRESSED_LONG +#define SDM_ExteriorKeyFobSw_Req_SDM_Cmd_REMOTE_START_PRESSED_LONG (8) +#endif + +#ifndef SDM_ExteriorKeyFobSw_Req_SDM_Cmd_REMOTE_START_PRESSED +#define SDM_ExteriorKeyFobSw_Req_SDM_Cmd_REMOTE_START_PRESSED (7) +#endif + +#ifndef SDM_ExteriorKeyFobSw_Req_SDM_Cmd_UNLOCK_PRESSED_LONG +#define SDM_ExteriorKeyFobSw_Req_SDM_Cmd_UNLOCK_PRESSED_LONG (6) +#endif + +#ifndef SDM_ExteriorKeyFobSw_Req_SDM_Cmd_UNLOCK_PRESSED +#define SDM_ExteriorKeyFobSw_Req_SDM_Cmd_UNLOCK_PRESSED (5) +#endif + +#ifndef SDM_ExteriorKeyFobSw_Req_SDM_Cmd_TRUNK_PRESSED_LONG +#define SDM_ExteriorKeyFobSw_Req_SDM_Cmd_TRUNK_PRESSED_LONG (4) +#endif + +#ifndef SDM_ExteriorKeyFobSw_Req_SDM_Cmd_TRUNK_PRESSED +#define SDM_ExteriorKeyFobSw_Req_SDM_Cmd_TRUNK_PRESSED (3) +#endif + +#ifndef SDM_ExteriorKeyFobSw_Req_SDM_Cmd_LOCK_PRESSED_LONG +#define SDM_ExteriorKeyFobSw_Req_SDM_Cmd_LOCK_PRESSED_LONG (2) +#endif + +#ifndef SDM_ExteriorKeyFobSw_Req_SDM_Cmd_LOCK_PRESSED +#define SDM_ExteriorKeyFobSw_Req_SDM_Cmd_LOCK_PRESSED (1) +#endif + +#ifndef SDM_ExteriorKeyFobSw_Req_SDM_Cmd_NO_ACTION +#define SDM_ExteriorKeyFobSw_Req_SDM_Cmd_NO_ACTION (0) +#endif + + +// Value tables for @SDM_DMRL_Req signal + +#ifndef SDM_DMRL_Req_SDM_Cmd_Fault +#define SDM_DMRL_Req_SDM_Cmd_Fault (7) +#endif + +#ifndef SDM_DMRL_Req_SDM_Cmd_Recerve +#define SDM_DMRL_Req_SDM_Cmd_Recerve (6) +#endif + +#ifndef SDM_DMRL_Req_SDM_Cmd_Window_auto_up +#define SDM_DMRL_Req_SDM_Cmd_Window_auto_up (5) +#endif + +#ifndef SDM_DMRL_Req_SDM_Cmd_Sun_blind_up +#define SDM_DMRL_Req_SDM_Cmd_Sun_blind_up (4) +#endif + +#ifndef SDM_DMRL_Req_SDM_Cmd_Sun_blind_down_ +#define SDM_DMRL_Req_SDM_Cmd_Sun_blind_down_ (3) +#endif + +#ifndef SDM_DMRL_Req_SDM_Cmd_Window_short_down +#define SDM_DMRL_Req_SDM_Cmd_Window_short_down (2) +#endif + +#ifndef SDM_DMRL_Req_SDM_Cmd_Window_down +#define SDM_DMRL_Req_SDM_Cmd_Window_down (1) +#endif + +#ifndef SDM_DMRL_Req_SDM_Cmd_No_action +#define SDM_DMRL_Req_SDM_Cmd_No_action (0) +#endif + + +// Value tables for @SDM_Comm_Req signal + +#ifndef SDM_Comm_Req_SDM_Cmd_TRUE +#define SDM_Comm_Req_SDM_Cmd_TRUE (1) +#endif + +#ifndef SDM_Comm_Req_SDM_Cmd_FALSE +#define SDM_Comm_Req_SDM_Cmd_FALSE (0) +#endif + + +// Value tables for @SDM_DMRR_Req signal + +#ifndef SDM_DMRR_Req_SDM_Cmd_Fault +#define SDM_DMRR_Req_SDM_Cmd_Fault (7) +#endif + +#ifndef SDM_DMRR_Req_SDM_Cmd_Recerve +#define SDM_DMRR_Req_SDM_Cmd_Recerve (6) +#endif + +#ifndef SDM_DMRR_Req_SDM_Cmd_Window_auto_up +#define SDM_DMRR_Req_SDM_Cmd_Window_auto_up (5) +#endif + +#ifndef SDM_DMRR_Req_SDM_Cmd_Sun_blind_up +#define SDM_DMRR_Req_SDM_Cmd_Sun_blind_up (4) +#endif + +#ifndef SDM_DMRR_Req_SDM_Cmd_Sun_blind_down_ +#define SDM_DMRR_Req_SDM_Cmd_Sun_blind_down_ (3) +#endif + +#ifndef SDM_DMRR_Req_SDM_Cmd_Window_short_down +#define SDM_DMRR_Req_SDM_Cmd_Window_short_down (2) +#endif + +#ifndef SDM_DMRR_Req_SDM_Cmd_Window_down +#define SDM_DMRR_Req_SDM_Cmd_Window_down (1) +#endif + +#ifndef SDM_DMRR_Req_SDM_Cmd_No_action +#define SDM_DMRR_Req_SDM_Cmd_No_action (0) +#endif + + +// Value tables for @SDM_VisualFeedback_Req signal + +#ifndef SDM_VisualFeedback_Req_SDM_Cmd_True +#define SDM_VisualFeedback_Req_SDM_Cmd_True (1) +#endif + +#ifndef SDM_VisualFeedback_Req_SDM_Cmd_False +#define SDM_VisualFeedback_Req_SDM_Cmd_False (0) +#endif + + +// Value tables for @SDM_AudibleFeedback_Req signal + +#ifndef SDM_AudibleFeedback_Req_SDM_Cmd_TRUE +#define SDM_AudibleFeedback_Req_SDM_Cmd_TRUE (1) +#endif + +#ifndef SDM_AudibleFeedback_Req_SDM_Cmd_FALSE +#define SDM_AudibleFeedback_Req_SDM_Cmd_FALSE (0) +#endif + + +// Value tables for @SDM_DMFL_Req signal + +#ifndef SDM_DMFL_Req_SDM_Cmd_Fault +#define SDM_DMFL_Req_SDM_Cmd_Fault (7) +#endif + +#ifndef SDM_DMFL_Req_SDM_Cmd_Recerve +#define SDM_DMFL_Req_SDM_Cmd_Recerve (6) +#endif + +#ifndef SDM_DMFL_Req_SDM_Cmd_Window_auto_up +#define SDM_DMFL_Req_SDM_Cmd_Window_auto_up (5) +#endif + +#ifndef SDM_DMFL_Req_SDM_Cmd_Sun_blind_up +#define SDM_DMFL_Req_SDM_Cmd_Sun_blind_up (4) +#endif + +#ifndef SDM_DMFL_Req_SDM_Cmd_Sun_blind_down_ +#define SDM_DMFL_Req_SDM_Cmd_Sun_blind_down_ (3) +#endif + +#ifndef SDM_DMFL_Req_SDM_Cmd_Window_short_down +#define SDM_DMFL_Req_SDM_Cmd_Window_short_down (2) +#endif + +#ifndef SDM_DMFL_Req_SDM_Cmd_Window_down +#define SDM_DMFL_Req_SDM_Cmd_Window_down (1) +#endif + +#ifndef SDM_DMFL_Req_SDM_Cmd_No_action +#define SDM_DMFL_Req_SDM_Cmd_No_action (0) +#endif + + +// Value tables for @SDM_DMFR_Req signal + +#ifndef SDM_DMFR_Req_SDM_Cmd_Fault +#define SDM_DMFR_Req_SDM_Cmd_Fault (7) +#endif + +#ifndef SDM_DMFR_Req_SDM_Cmd_Recerve +#define SDM_DMFR_Req_SDM_Cmd_Recerve (6) +#endif + +#ifndef SDM_DMFR_Req_SDM_Cmd_Window_auto_up +#define SDM_DMFR_Req_SDM_Cmd_Window_auto_up (5) +#endif + +#ifndef SDM_DMFR_Req_SDM_Cmd_Sun_blind_up +#define SDM_DMFR_Req_SDM_Cmd_Sun_blind_up (4) +#endif + +#ifndef SDM_DMFR_Req_SDM_Cmd_Sun_blind_down_ +#define SDM_DMFR_Req_SDM_Cmd_Sun_blind_down_ (3) +#endif + +#ifndef SDM_DMFR_Req_SDM_Cmd_Window_short_down +#define SDM_DMFR_Req_SDM_Cmd_Window_short_down (2) +#endif + +#ifndef SDM_DMFR_Req_SDM_Cmd_Window_down +#define SDM_DMFR_Req_SDM_Cmd_Window_down (1) +#endif + +#ifndef SDM_DMFR_Req_SDM_Cmd_No_action +#define SDM_DMFR_Req_SDM_Cmd_No_action (0) +#endif + + +// Value tables for @SDM_Aroma_Req signal + +#ifndef SDM_Aroma_Req_SDM_Cmd_No_change +#define SDM_Aroma_Req_SDM_Cmd_No_change (0) +#endif + +#ifndef SDM_Aroma_Req_SDM_Cmd_Aromatization_on +#define SDM_Aroma_Req_SDM_Cmd_Aromatization_on (1) +#endif + +#ifndef SDM_Aroma_Req_SDM_Cmd_Aromatization_off +#define SDM_Aroma_Req_SDM_Cmd_Aromatization_off (2) +#endif + + +// Value tables for @SDM_AromaIntens_Req signal + +#ifndef SDM_AromaIntens_Req_SDM_Cmd_Aromatization_mode_3_step +#define SDM_AromaIntens_Req_SDM_Cmd_Aromatization_mode_3_step (3) +#endif + +#ifndef SDM_AromaIntens_Req_SDM_Cmd_Aromatization_mode_2_step +#define SDM_AromaIntens_Req_SDM_Cmd_Aromatization_mode_2_step (2) +#endif + +#ifndef SDM_AromaIntens_Req_SDM_Cmd_Aromatization_mode_1_step +#define SDM_AromaIntens_Req_SDM_Cmd_Aromatization_mode_1_step (1) +#endif + +#ifndef SDM_AromaIntens_Req_SDM_Cmd_No_change +#define SDM_AromaIntens_Req_SDM_Cmd_No_change (0) +#endif + + +// Value tables for @SDM_StyleIllGlobal_Req signal + +#ifndef SDM_StyleIllGlobal_Req_SDM_Cmd_Function_active +#define SDM_StyleIllGlobal_Req_SDM_Cmd_Function_active (2) +#endif + +#ifndef SDM_StyleIllGlobal_Req_SDM_Cmd_Function_inactive +#define SDM_StyleIllGlobal_Req_SDM_Cmd_Function_inactive (1) +#endif + +#ifndef SDM_StyleIllGlobal_Req_SDM_Cmd_No_change +#define SDM_StyleIllGlobal_Req_SDM_Cmd_No_change (0) +#endif + + +// Value tables for @SDM_StyleIllTheme_Req signal + +#ifndef SDM_StyleIllTheme_Req_SDM_Cmd_No_change +#define SDM_StyleIllTheme_Req_SDM_Cmd_No_change (31) +#endif + +#ifndef SDM_StyleIllTheme_Req_SDM_Cmd_Color_theme_16 +#define SDM_StyleIllTheme_Req_SDM_Cmd_Color_theme_16 (15) +#endif + +#ifndef SDM_StyleIllTheme_Req_SDM_Cmd_Color_theme_15 +#define SDM_StyleIllTheme_Req_SDM_Cmd_Color_theme_15 (14) +#endif + +#ifndef SDM_StyleIllTheme_Req_SDM_Cmd_Color_theme_14 +#define SDM_StyleIllTheme_Req_SDM_Cmd_Color_theme_14 (13) +#endif + +#ifndef SDM_StyleIllTheme_Req_SDM_Cmd_Color_theme_13 +#define SDM_StyleIllTheme_Req_SDM_Cmd_Color_theme_13 (12) +#endif + +#ifndef SDM_StyleIllTheme_Req_SDM_Cmd_Color_theme_12 +#define SDM_StyleIllTheme_Req_SDM_Cmd_Color_theme_12 (11) +#endif + +#ifndef SDM_StyleIllTheme_Req_SDM_Cmd_Color_theme_11 +#define SDM_StyleIllTheme_Req_SDM_Cmd_Color_theme_11 (10) +#endif + +#ifndef SDM_StyleIllTheme_Req_SDM_Cmd_Color_theme_10 +#define SDM_StyleIllTheme_Req_SDM_Cmd_Color_theme_10 (9) +#endif + +#ifndef SDM_StyleIllTheme_Req_SDM_Cmd_Color_theme_9 +#define SDM_StyleIllTheme_Req_SDM_Cmd_Color_theme_9 (8) +#endif + +#ifndef SDM_StyleIllTheme_Req_SDM_Cmd_Reserved +#define SDM_StyleIllTheme_Req_SDM_Cmd_Reserved (7) +#endif + +#ifndef SDM_StyleIllTheme_Req_SDM_Cmd_Color_theme_7 +#define SDM_StyleIllTheme_Req_SDM_Cmd_Color_theme_7 (6) +#endif + +#ifndef SDM_StyleIllTheme_Req_SDM_Cmd_Color_theme_6 +#define SDM_StyleIllTheme_Req_SDM_Cmd_Color_theme_6 (5) +#endif + +#ifndef SDM_StyleIllTheme_Req_SDM_Cmd_Color_theme_5 +#define SDM_StyleIllTheme_Req_SDM_Cmd_Color_theme_5 (4) +#endif + +#ifndef SDM_StyleIllTheme_Req_SDM_Cmd_Color_theme_4 +#define SDM_StyleIllTheme_Req_SDM_Cmd_Color_theme_4 (3) +#endif + +#ifndef SDM_StyleIllTheme_Req_SDM_Cmd_Color_theme_3 +#define SDM_StyleIllTheme_Req_SDM_Cmd_Color_theme_3 (2) +#endif + +#ifndef SDM_StyleIllTheme_Req_SDM_Cmd_Color_theme_2 +#define SDM_StyleIllTheme_Req_SDM_Cmd_Color_theme_2 (1) +#endif + +#ifndef SDM_StyleIllTheme_Req_SDM_Cmd_Color_theme_1 +#define SDM_StyleIllTheme_Req_SDM_Cmd_Color_theme_1 (0) +#endif + + +// Value tables for @SDM_StyleIllBright_Val signal + +#ifndef SDM_StyleIllBright_Val_SDM_Cmd_No_change +#define SDM_StyleIllBright_Val_SDM_Cmd_No_change (127) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Commands for controlling locks from the SDM unit + // 8 : "REMOTE_START_PRESSED_LONG" + // 7 : "REMOTE_START_PRESSED" + // 6 : "UNLOCK_PRESSED_LONG" + // 5 : "UNLOCK_PRESSED" + // 4 : "TRUNK_PRESSED_LONG" + // 3 : "TRUNK_PRESSED" + // 2 : "LOCK_PRESSED_LONG" + // 1 : "LOCK_PRESSED" + // 0 : "NO_ACTION" + uint8_t SDM_ExteriorKeyFobSw_Req : 4; // Bits= 4 + + // Control of rear left door components from SDM unit + // 7 : "Fault" + // 6 : "Recerve" + // 5 : "Window auto up" + // 4 : "Sun blind up" + // 3 : "Sun blind down " + // 2 : "Window short down" + // 1 : "Window down" + // 0 : "No action" + uint8_t SDM_DMRL_Req : 3; // Bits= 3 + + // Request to wake up the vehicle from the SDM unit + // 1 : "TRUE" + // 0 : "FALSE" + uint8_t SDM_Comm_Req : 1; // Bits= 1 + + // Control of rear right door components from SDM unit + // 7 : "Fault" + // 6 : "Recerve" + // 5 : "Window auto up" + // 4 : "Sun blind up" + // 3 : "Sun blind down " + // 2 : "Window short down" + // 1 : "Window down" + // 0 : "No action" + uint8_t SDM_DMRR_Req : 3; // Bits= 3 + + // Request to activate the alarm from the SDM unit + // 1 : "True" + // 0 : "False" + uint8_t SDM_VisualFeedback_Req : 1; // Bits= 1 + + // Request to activate the sound signal from the SDM unit + // 1 : "TRUE" + // 0 : "FALSE" + uint8_t SDM_AudibleFeedback_Req : 1; // Bits= 1 + + // Control of front left door components from SDM unit + // 7 : "Fault" + // 6 : "Recerve" + // 5 : "Window auto up" + // 4 : "Sun blind up" + // 3 : "Sun blind down " + // 2 : "Window short down" + // 1 : "Window down" + // 0 : "No action" + uint8_t SDM_DMFL_Req : 3; // Bits= 3 + + // Control of front right door components from SDM unit + // 7 : "Fault" + // 6 : "Recerve" + // 5 : "Window auto up" + // 4 : "Sun blind up" + // 3 : "Sun blind down " + // 2 : "Window short down" + // 1 : "Window down" + // 0 : "No action" + uint8_t SDM_DMFR_Req : 3; // Bits= 3 + + // Aromatization activation request + // 0 : "No change" + // 1 : "Aromatization on" + // 2 : "Aromatization off" + uint8_t SDM_Aroma_Req : 2; // Bits= 2 + + // Telematics request for the preparation of the salon climate + uint8_t SDM_PrepSalon_Req : 1; // Bits= 1 + + // Aromatization intensity set request + // 3 : "Aromatization mode 3 step" + // 2 : "Aromatization mode 2 step" + // 1 : "Aromatization mode 1 step" + // 0 : "No change" + uint8_t SDM_AromaIntens_Req : 2; // Bits= 2 + + // Style illumination global ON/OFF + // 2 : "Function active" + // 1 : "Function inactive" + // 0 : "No change" + uint8_t SDM_StyleIllGlobal_Req : 2; // Bits= 2 + + // Color theme presets for style ill + // 1 - AMETHYST + // 2 - LAPIS LAZU + // 3 - SAPPHIRE + // 4 - EMERALD + // 5 - AURUS + // 6 - RUBY + // 7 - PEARL + // 8 - Reserved + // 9 - MAJORELLE_TANZ + // 10 - AQUAMARINE + // 11 - CHRYSOLITE + // 12 - CRYSTAL + // 13 - AMBER + // 14 - PYROPE + // 15 - OPAL + // 16 - DIAMOND + // 31 : "No change" + // 15 : "Color theme 16" + // 14 : "Color theme 15" + // 13 : "Color theme 14" + // 12 : "Color theme 13" + // 11 : "Color theme 12" + // 10 : "Color theme 11" + // 9 : "Color theme 10" + // 8 : "Color theme 9" + // 7 : "Reserved" + // 6 : "Color theme 7" + // 5 : "Color theme 6" + // 4 : "Color theme 5" + // 3 : "Color theme 4" + // 2 : "Color theme 3" + // 1 : "Color theme 2" + // 0 : "Color theme 1" + uint8_t SDM_StyleIllTheme_Req : 5; // Bits= 5 + + // �Telematics request for stop the preparation of the salon climate + uint8_t SDM_StopPrep_Req : 1; // Bits= 1 + + // Style illumination brightness % + // 127 : "No change" + uint8_t SDM_StyleIllBright_Val : 7; // Bits= 7 Unit:'%' + + // Over-the-Air update session state + uint8_t SDM_OverAirUpd_Stat : 1; // Bits= 1 + + // Tel_ultraviolet request + uint8_t SDM_UV_Req : 1; // Bits= 1 + +#else + + // Commands for controlling locks from the SDM unit + // 8 : "REMOTE_START_PRESSED_LONG" + // 7 : "REMOTE_START_PRESSED" + // 6 : "UNLOCK_PRESSED_LONG" + // 5 : "UNLOCK_PRESSED" + // 4 : "TRUNK_PRESSED_LONG" + // 3 : "TRUNK_PRESSED" + // 2 : "LOCK_PRESSED_LONG" + // 1 : "LOCK_PRESSED" + // 0 : "NO_ACTION" + uint8_t SDM_ExteriorKeyFobSw_Req; // Bits= 4 + + // Control of rear left door components from SDM unit + // 7 : "Fault" + // 6 : "Recerve" + // 5 : "Window auto up" + // 4 : "Sun blind up" + // 3 : "Sun blind down " + // 2 : "Window short down" + // 1 : "Window down" + // 0 : "No action" + uint8_t SDM_DMRL_Req; // Bits= 3 + + // Request to wake up the vehicle from the SDM unit + // 1 : "TRUE" + // 0 : "FALSE" + uint8_t SDM_Comm_Req; // Bits= 1 + + // Control of rear right door components from SDM unit + // 7 : "Fault" + // 6 : "Recerve" + // 5 : "Window auto up" + // 4 : "Sun blind up" + // 3 : "Sun blind down " + // 2 : "Window short down" + // 1 : "Window down" + // 0 : "No action" + uint8_t SDM_DMRR_Req; // Bits= 3 + + // Request to activate the alarm from the SDM unit + // 1 : "True" + // 0 : "False" + uint8_t SDM_VisualFeedback_Req; // Bits= 1 + + // Request to activate the sound signal from the SDM unit + // 1 : "TRUE" + // 0 : "FALSE" + uint8_t SDM_AudibleFeedback_Req; // Bits= 1 + + // Control of front left door components from SDM unit + // 7 : "Fault" + // 6 : "Recerve" + // 5 : "Window auto up" + // 4 : "Sun blind up" + // 3 : "Sun blind down " + // 2 : "Window short down" + // 1 : "Window down" + // 0 : "No action" + uint8_t SDM_DMFL_Req; // Bits= 3 + + // Control of front right door components from SDM unit + // 7 : "Fault" + // 6 : "Recerve" + // 5 : "Window auto up" + // 4 : "Sun blind up" + // 3 : "Sun blind down " + // 2 : "Window short down" + // 1 : "Window down" + // 0 : "No action" + uint8_t SDM_DMFR_Req; // Bits= 3 + + // Aromatization activation request + // 0 : "No change" + // 1 : "Aromatization on" + // 2 : "Aromatization off" + uint8_t SDM_Aroma_Req; // Bits= 2 + + // Telematics request for the preparation of the salon climate + uint8_t SDM_PrepSalon_Req; // Bits= 1 + + // Aromatization intensity set request + // 3 : "Aromatization mode 3 step" + // 2 : "Aromatization mode 2 step" + // 1 : "Aromatization mode 1 step" + // 0 : "No change" + uint8_t SDM_AromaIntens_Req; // Bits= 2 + + // Style illumination global ON/OFF + // 2 : "Function active" + // 1 : "Function inactive" + // 0 : "No change" + uint8_t SDM_StyleIllGlobal_Req; // Bits= 2 + + // Color theme presets for style ill + // 1 - AMETHYST + // 2 - LAPIS LAZU + // 3 - SAPPHIRE + // 4 - EMERALD + // 5 - AURUS + // 6 - RUBY + // 7 - PEARL + // 8 - Reserved + // 9 - MAJORELLE_TANZ + // 10 - AQUAMARINE + // 11 - CHRYSOLITE + // 12 - CRYSTAL + // 13 - AMBER + // 14 - PYROPE + // 15 - OPAL + // 16 - DIAMOND + // 31 : "No change" + // 15 : "Color theme 16" + // 14 : "Color theme 15" + // 13 : "Color theme 14" + // 12 : "Color theme 13" + // 11 : "Color theme 12" + // 10 : "Color theme 11" + // 9 : "Color theme 10" + // 8 : "Color theme 9" + // 7 : "Reserved" + // 6 : "Color theme 7" + // 5 : "Color theme 6" + // 4 : "Color theme 5" + // 3 : "Color theme 4" + // 2 : "Color theme 3" + // 1 : "Color theme 2" + // 0 : "Color theme 1" + uint8_t SDM_StyleIllTheme_Req; // Bits= 5 + + // �Telematics request for stop the preparation of the salon climate + uint8_t SDM_StopPrep_Req; // Bits= 1 + + // Style illumination brightness % + // 127 : "No change" + uint8_t SDM_StyleIllBright_Val; // Bits= 7 Unit:'%' + + // Over-the-Air update session state + uint8_t SDM_OverAirUpd_Stat; // Bits= 1 + + // Tel_ultraviolet request + uint8_t SDM_UV_Req; // Bits= 1 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} SDM_Cmd_t; + +// def @HUD_MSG_STATUS CAN Message (1297 0x511) +#define HUD_MSG_STATUS_IDE (0U) +#define HUD_MSG_STATUS_DLC (1U) +#define HUD_MSG_STATUS_CANID (0x511U) +#define HUD_MSG_STATUS_CYC (200U) + +// Value tables for @HUD_Activation_Stat signal + +#ifndef HUD_Activation_Stat_HUD_MSG_STATUS_Active +#define HUD_Activation_Stat_HUD_MSG_STATUS_Active (1) +#endif + +#ifndef HUD_Activation_Stat_HUD_MSG_STATUS_Inactive +#define HUD_Activation_Stat_HUD_MSG_STATUS_Inactive (0) +#endif + + +// Value tables for @HUD_ReadyFlag_Stat signal + +#ifndef HUD_ReadyFlag_Stat_HUD_MSG_STATUS_HUD_Ready +#define HUD_ReadyFlag_Stat_HUD_MSG_STATUS_HUD_Ready (1) +#endif + +#ifndef HUD_ReadyFlag_Stat_HUD_MSG_STATUS_HUD_not_Ready +#define HUD_ReadyFlag_Stat_HUD_MSG_STATUS_HUD_not_Ready (0) +#endif + + +// Value tables for @HUD_NAVI_Active_Stat signal + +#ifndef HUD_NAVI_Active_Stat_HUD_MSG_STATUS_Navigation_map_is_active +#define HUD_NAVI_Active_Stat_HUD_MSG_STATUS_Navigation_map_is_active (1) +#endif + +#ifndef HUD_NAVI_Active_Stat_HUD_MSG_STATUS_Navigation_map_is_not_active +#define HUD_NAVI_Active_Stat_HUD_MSG_STATUS_Navigation_map_is_not_active (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // HUD activation status + // 1 : "Active" + // 0 : "Inactive" + uint8_t HUD_Activation_Stat : 1; // Bits= 1 + + // indicates the HUD state for requesting memorized info in FIU: + // 0x0 = HUD not ready + // 0x1 = HUD Ready to receive memorized configuration. + // 1 : "HUD Ready" + // 0 : "HUD not Ready" + uint8_t HUD_ReadyFlag_Stat : 1; // Bits= 1 + + // 0x00 Navigation map is not active + // 0x01 Navigation map is active + // 1 : "Navigation map is active" + // 0 : "Navigation map is not active" + uint8_t HUD_NAVI_Active_Stat : 1; // Bits= 1 + +#else + + // HUD activation status + // 1 : "Active" + // 0 : "Inactive" + uint8_t HUD_Activation_Stat; // Bits= 1 + + // indicates the HUD state for requesting memorized info in FIU: + // 0x0 = HUD not ready + // 0x1 = HUD Ready to receive memorized configuration. + // 1 : "HUD Ready" + // 0 : "HUD not Ready" + uint8_t HUD_ReadyFlag_Stat; // Bits= 1 + + // 0x00 Navigation map is not active + // 0x01 Navigation map is active + // 1 : "Navigation map is active" + // 0 : "Navigation map is not active" + uint8_t HUD_NAVI_Active_Stat; // Bits= 1 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} HUD_MSG_STATUS_t; + +// def @IC_SDM_Info_02 CAN Message (1298 0x512) +#define IC_SDM_Info_02_IDE (0U) +#define IC_SDM_Info_02_DLC (6U) +#define IC_SDM_Info_02_CANID (0x512U) +#define IC_SDM_Info_02_CYC (500U) +// signal: @IC_AverageConsump_ro +#define CANDB_IC_AverageConsump_ro_CovFactor (0.1) +#define CANDB_IC_AverageConsump_ro_toS(x) ( (uint16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_IC_AverageConsump_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +// Value tables for @IC_CurrentConsumptionUnit signal + +#ifndef IC_CurrentConsumptionUnit_IC_SDM_Info_02_L_or_kWh_or_kg_H +#define IC_CurrentConsumptionUnit_IC_SDM_Info_02_L_or_kWh_or_kg_H (1) +#endif + +#ifndef IC_CurrentConsumptionUnit_IC_SDM_Info_02__L_or_kWh_or_kg_100_Km +#define IC_CurrentConsumptionUnit_IC_SDM_Info_02__L_or_kWh_or_kg_100_Km (0) +#endif + +// signal: @IC_CurrentConsump_ro +#define CANDB_IC_CurrentConsump_ro_CovFactor (0.1) +#define CANDB_IC_CurrentConsump_ro_toS(x) ( (uint16_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_IC_CurrentConsump_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +// Value tables for @IC_CruisingRange signal + +#ifndef IC_CruisingRange_IC_SDM_Info_02_Value_error +#define IC_CruisingRange_IC_SDM_Info_02_Value_error (1023) +#endif + +#ifndef IC_CruisingRange_IC_SDM_Info_02__Km +#define IC_CruisingRange_IC_SDM_Info_02__Km (2) +#endif + +#ifndef IC_CruisingRange_IC_SDM_Info_02__Km +#define IC_CruisingRange_IC_SDM_Info_02__Km (1) +#endif + +#ifndef IC_CruisingRange_IC_SDM_Info_02__Km +#define IC_CruisingRange_IC_SDM_Info_02__Km (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Average consamption in l/100Km, step 0.1 liter/100 Km + uint16_t IC_AverageConsump_ro; // Bits=10 Factor= 0.1 Unit:'l/km' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t IC_AverageConsump_phys; +#endif // CANDB_USE_SIGFLOAT + + // Current consumption Unit (liters, power, kilograms) + // 1 : "L or kWh or kg /H" + // 0 : " L or kWh or kg /100 Km" + uint8_t IC_CurrentConsumptionUnit : 1; // Bits= 1 + + // Current consamption in l/100Km(H), step 0.1 liter/100 Km(H). Unit according CurrentConsumptionUnit + uint16_t IC_CurrentConsump_ro; // Bits=10 Factor= 0.1 Unit:'l/km' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t IC_CurrentConsump_phys; +#endif // CANDB_USE_SIGFLOAT + + // Estimated Cruising range + // 1023 : "Value error" + // 2 : "2 Km" + // 1 : "1 Km" + // 0 : "0 Km" + uint16_t IC_CruisingRange; // Bits=10 Unit:'km' + +#else + + // Average consamption in l/100Km, step 0.1 liter/100 Km + uint16_t IC_AverageConsump_ro; // Bits=10 Factor= 0.1 Unit:'l/km' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t IC_AverageConsump_phys; +#endif // CANDB_USE_SIGFLOAT + + // Current consumption Unit (liters, power, kilograms) + // 1 : "L or kWh or kg /H" + // 0 : " L or kWh or kg /100 Km" + uint8_t IC_CurrentConsumptionUnit; // Bits= 1 + + // Current consamption in l/100Km(H), step 0.1 liter/100 Km(H). Unit according CurrentConsumptionUnit + uint16_t IC_CurrentConsump_ro; // Bits=10 Factor= 0.1 Unit:'l/km' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t IC_CurrentConsump_phys; +#endif // CANDB_USE_SIGFLOAT + + // Estimated Cruising range + // 1023 : "Value error" + // 2 : "2 Km" + // 1 : "1 Km" + // 0 : "0 Km" + uint16_t IC_CruisingRange; // Bits=10 Unit:'km' + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} IC_SDM_Info_02_t; + +// def @IC_Milleage CAN Message (1300 0x514) +#define IC_Milleage_IDE (0U) +#define IC_Milleage_DLC (5U) +#define IC_Milleage_CANID (0x514U) +#define IC_Milleage_CYC (500U) +// signal: @IC_Mileage_Val_ro +#define CANDB_IC_Mileage_Val_ro_CovFactor (0.1) +#define CANDB_IC_Mileage_Val_ro_toS(x) ( (uint32_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_IC_Mileage_Val_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Mileage/ odometer signal to provide vehicle mileage information. + // 0x7FFFFFF = Error + uint32_t IC_Mileage_Val_ro; // Bits=27 Factor= 0.1 Unit:'km' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t IC_Mileage_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Rolling Counter [0 - 15] + uint8_t IC_Mileage_RC : 4; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t IC_Mileage_CS; // Bits= 8 + +#else + + // Mileage/ odometer signal to provide vehicle mileage information. + // 0x7FFFFFF = Error + uint32_t IC_Mileage_Val_ro; // Bits=27 Factor= 0.1 Unit:'km' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t IC_Mileage_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Rolling Counter [0 - 15] + uint8_t IC_Mileage_RC; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t IC_Mileage_CS; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} IC_Milleage_t; + +// VIN Code structure: +// e.g: XKN412300H1000027 +// XKN: code WMI +// 412300: vehicle model +// H: Vehicle production year +// 1: assembling at NAMI +// 6 last characters: serial number. +// REMARK: In case of VIN programming has failed, all characters will be = '0' +// def @VEH_VIN CAN Message (1306 0x51a) +#define VEH_VIN_IDE (0U) +#define VEH_VIN_DLC (8U) +#define VEH_VIN_CANID (0x51aU) +#define VEH_VIN_CYC (5000U) + +// Value tables for @VIN_Addressing signal + +#ifndef VIN_Addressing_VEH_VIN_VIN_Part_3 +#define VIN_Addressing_VEH_VIN_VIN_Part_3 (2) +#endif + +#ifndef VIN_Addressing_VEH_VIN_VIN_Part_2 +#define VIN_Addressing_VEH_VIN_VIN_Part_2 (1) +#endif + +#ifndef VIN_Addressing_VEH_VIN_VIN_Part_1 +#define VIN_Addressing_VEH_VIN_VIN_Part_1 (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Addresses the VIN Part: + // 0x0 = Addresses VIN part 1 + // 0x1 = Addresses VIN part 2 + // 0x2 = Addresses VIN part 3 + // 2 : "VIN Part 3" + // 1 : "VIN Part 2" + // 0 : "VIN Part 1" + // MULTIPLEX master signal + uint8_t VIN_Addressing : 2; // Bits= 2 + + // VIN character 1 + // REMARK: + // In case of VIN programming has failed, character will be = '0' + // multiplex variable + uint8_t VIN_Char1; // Bits= 8 + + // VIN character 8 + // REMARK: + // In case of VIN programming has failed, character will be = '0' + // multiplex variable + uint8_t VIN_Char8; // Bits= 8 + + // VIN character 15 + // REMARK: + // In case of VIN programming has failed, character will be = '0' + // multiplex variable + uint8_t VIN_Char15; // Bits= 8 + + // VIN character 16 + // REMARK: + // In case of VIN programming has failed, character will be = '0' + // multiplex variable + uint8_t VIN_Char16; // Bits= 8 + + // VIN character 2 + // REMARK: + // In case of VIN programming has failed, character will be = '0' + // multiplex variable + uint8_t VIN_Char2; // Bits= 8 + + // VIN character 9 + // REMARK: + // In case of VIN programming has failed, character will be = '0' + // multiplex variable + uint8_t VIN_Char9; // Bits= 8 + + // VIN character 10 + // REMARK: + // In case of VIN programming has failed, character will be = '0' + // multiplex variable + uint8_t VIN_Char10; // Bits= 8 + + // VIN character 17 + // REMARK: + // In case of VIN programming has failed, character will be = '0' + // multiplex variable + uint8_t VIN_Char17; // Bits= 8 + + // VIN character 3 + // REMARK: + // In case of VIN programming has failed, character will be = '0' + // multiplex variable + uint8_t VIN_Char3; // Bits= 8 + + // VIN character 4 + // REMARK: + // In case of VIN programming has failed, character will be = '0' + // multiplex variable + uint8_t VIN_Char4; // Bits= 8 + + // VIN character 11 + // REMARK: + // In case of VIN programming has failed, character will be = '0' + // multiplex variable + uint8_t VIN_Char11; // Bits= 8 + + // VIN character 12 + // REMARK: + // In case of VIN programming has failed, character will be = '0' + // multiplex variable + uint8_t VIN_Char12; // Bits= 8 + + // VIN character 5 + // REMARK: + // In case of VIN programming has failed, character will be = '0' + // multiplex variable + uint8_t VIN_Char5; // Bits= 8 + + // VIN character 6 + // REMARK: + // In case of VIN programming has failed, character will be = '0' + // multiplex variable + uint8_t VIN_Char6; // Bits= 8 + + // VIN character 13 + // REMARK: + // In case of VIN programming has failed, character will be = '0' + // multiplex variable + uint8_t VIN_Char13; // Bits= 8 + + // VIN character 7 + // REMARK: + // In case of VIN programming has failed, character will be = '0' + // multiplex variable + uint8_t VIN_Char7; // Bits= 8 + + // VIN character 14 + // REMARK: + // In case of VIN programming has failed, character will be = '0' + // multiplex variable + uint8_t VIN_Char14; // Bits= 8 + +#else + + // Addresses the VIN Part: + // 0x0 = Addresses VIN part 1 + // 0x1 = Addresses VIN part 2 + // 0x2 = Addresses VIN part 3 + // 2 : "VIN Part 3" + // 1 : "VIN Part 2" + // 0 : "VIN Part 1" + // MULTIPLEX master signal + uint8_t VIN_Addressing; // Bits= 2 + + // VIN character 1 + // REMARK: + // In case of VIN programming has failed, character will be = '0' + // multiplex variable + uint8_t VIN_Char1; // Bits= 8 + + // VIN character 8 + // REMARK: + // In case of VIN programming has failed, character will be = '0' + // multiplex variable + uint8_t VIN_Char8; // Bits= 8 + + // VIN character 15 + // REMARK: + // In case of VIN programming has failed, character will be = '0' + // multiplex variable + uint8_t VIN_Char15; // Bits= 8 + + // VIN character 16 + // REMARK: + // In case of VIN programming has failed, character will be = '0' + // multiplex variable + uint8_t VIN_Char16; // Bits= 8 + + // VIN character 2 + // REMARK: + // In case of VIN programming has failed, character will be = '0' + // multiplex variable + uint8_t VIN_Char2; // Bits= 8 + + // VIN character 9 + // REMARK: + // In case of VIN programming has failed, character will be = '0' + // multiplex variable + uint8_t VIN_Char9; // Bits= 8 + + // VIN character 10 + // REMARK: + // In case of VIN programming has failed, character will be = '0' + // multiplex variable + uint8_t VIN_Char10; // Bits= 8 + + // VIN character 17 + // REMARK: + // In case of VIN programming has failed, character will be = '0' + // multiplex variable + uint8_t VIN_Char17; // Bits= 8 + + // VIN character 3 + // REMARK: + // In case of VIN programming has failed, character will be = '0' + // multiplex variable + uint8_t VIN_Char3; // Bits= 8 + + // VIN character 4 + // REMARK: + // In case of VIN programming has failed, character will be = '0' + // multiplex variable + uint8_t VIN_Char4; // Bits= 8 + + // VIN character 11 + // REMARK: + // In case of VIN programming has failed, character will be = '0' + // multiplex variable + uint8_t VIN_Char11; // Bits= 8 + + // VIN character 12 + // REMARK: + // In case of VIN programming has failed, character will be = '0' + // multiplex variable + uint8_t VIN_Char12; // Bits= 8 + + // VIN character 5 + // REMARK: + // In case of VIN programming has failed, character will be = '0' + // multiplex variable + uint8_t VIN_Char5; // Bits= 8 + + // VIN character 6 + // REMARK: + // In case of VIN programming has failed, character will be = '0' + // multiplex variable + uint8_t VIN_Char6; // Bits= 8 + + // VIN character 13 + // REMARK: + // In case of VIN programming has failed, character will be = '0' + // multiplex variable + uint8_t VIN_Char13; // Bits= 8 + + // VIN character 7 + // REMARK: + // In case of VIN programming has failed, character will be = '0' + // multiplex variable + uint8_t VIN_Char7; // Bits= 8 + + // VIN character 14 + // REMARK: + // In case of VIN programming has failed, character will be = '0' + // multiplex variable + uint8_t VIN_Char14; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} VEH_VIN_t; + +// def @BCM_RunningBoards CAN Message (1310 0x51e) +#define BCM_RunningBoards_IDE (0U) +#define BCM_RunningBoards_DLC (1U) +#define BCM_RunningBoards_CANID (0x51eU) +#define BCM_RunningBoards_CYC (250U) + +// Value tables for @BCM_LeftMotion_Cmd signal + +#ifndef BCM_LeftMotion_Cmd_BCM_RunningBoards_Calibration_Request +#define BCM_LeftMotion_Cmd_BCM_RunningBoards_Calibration_Request (3) +#endif + +#ifndef BCM_LeftMotion_Cmd_BCM_RunningBoards_Open_Request +#define BCM_LeftMotion_Cmd_BCM_RunningBoards_Open_Request (2) +#endif + +#ifndef BCM_LeftMotion_Cmd_BCM_RunningBoards_Close_Request +#define BCM_LeftMotion_Cmd_BCM_RunningBoards_Close_Request (1) +#endif + +#ifndef BCM_LeftMotion_Cmd_BCM_RunningBoards_No_Action +#define BCM_LeftMotion_Cmd_BCM_RunningBoards_No_Action (0) +#endif + + +// Value tables for @BCM_RightMotion_Cmd signal + +#ifndef BCM_RightMotion_Cmd_BCM_RunningBoards_Calibration_Request +#define BCM_RightMotion_Cmd_BCM_RunningBoards_Calibration_Request (3) +#endif + +#ifndef BCM_RightMotion_Cmd_BCM_RunningBoards_Open_Request +#define BCM_RightMotion_Cmd_BCM_RunningBoards_Open_Request (2) +#endif + +#ifndef BCM_RightMotion_Cmd_BCM_RunningBoards_Close_Request +#define BCM_RightMotion_Cmd_BCM_RunningBoards_Close_Request (1) +#endif + +#ifndef BCM_RightMotion_Cmd_BCM_RunningBoards_No_Action +#define BCM_RightMotion_Cmd_BCM_RunningBoards_No_Action (0) +#endif + + +// Value tables for @BCM_Buzzer_Cmd signal + +#ifndef BCM_Buzzer_Cmd_BCM_RunningBoards_Request +#define BCM_Buzzer_Cmd_BCM_RunningBoards_Request (1) +#endif + +#ifndef BCM_Buzzer_Cmd_BCM_RunningBoards_No_Request +#define BCM_Buzzer_Cmd_BCM_RunningBoards_No_Request (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Left Running board commands + // 3 : "Calibration Request" + // 2 : "Open Request" + // 1 : "Close Request" + // 0 : "No Action" + uint8_t BCM_LeftMotion_Cmd : 2; // Bits= 2 + + // Right Running board commands + // 3 : "Calibration Request" + // 2 : "Open Request" + // 1 : "Close Request" + // 0 : "No Action" + uint8_t BCM_RightMotion_Cmd : 2; // Bits= 2 + + // Buzzer action request signal. While 0x1 - buzzer active + // 1 : "Request" + // 0 : "No Request" + uint8_t BCM_Buzzer_Cmd : 1; // Bits= 1 + +#else + + // Left Running board commands + // 3 : "Calibration Request" + // 2 : "Open Request" + // 1 : "Close Request" + // 0 : "No Action" + uint8_t BCM_LeftMotion_Cmd; // Bits= 2 + + // Right Running board commands + // 3 : "Calibration Request" + // 2 : "Open Request" + // 1 : "Close Request" + // 0 : "No Action" + uint8_t BCM_RightMotion_Cmd; // Bits= 2 + + // Buzzer action request signal. While 0x1 - buzzer active + // 1 : "Request" + // 0 : "No Request" + uint8_t BCM_Buzzer_Cmd; // Bits= 1 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} BCM_RunningBoards_t; + +// def @OCUFL_MSG CAN Message (1313 0x521) +#define OCUFL_MSG_IDE (0U) +#define OCUFL_MSG_DLC (2U) +#define OCUFL_MSG_CANID (0x521U) +#define OCUFL_MSG_CYC (1000U) + +// Value tables for @OCUFL_OccupantWeight_Stat signal + +#ifndef OCUFL_OccupantWeight_Stat_OCUFL_MSG_Large_Occupant +#define OCUFL_OccupantWeight_Stat_OCUFL_MSG_Large_Occupant (3) +#endif + +#ifndef OCUFL_OccupantWeight_Stat_OCUFL_MSG_Small_Occupant +#define OCUFL_OccupantWeight_Stat_OCUFL_MSG_Small_Occupant (2) +#endif + +#ifndef OCUFL_OccupantWeight_Stat_OCUFL_MSG_Child_Seat +#define OCUFL_OccupantWeight_Stat_OCUFL_MSG_Child_Seat (1) +#endif + +#ifndef OCUFL_OccupantWeight_Stat_OCUFL_MSG_Empty +#define OCUFL_OccupantWeight_Stat_OCUFL_MSG_Empty (0) +#endif + + +// Value tables for @OCUFL_SeatOccupied_Stat signal + +#ifndef OCUFL_SeatOccupied_Stat_OCUFL_MSG_Occupied +#define OCUFL_SeatOccupied_Stat_OCUFL_MSG_Occupied (1) +#endif + +#ifndef OCUFL_SeatOccupied_Stat_OCUFL_MSG_Not_Occupied +#define OCUFL_SeatOccupied_Stat_OCUFL_MSG_Not_Occupied (0) +#endif + + +// Value tables for @OCUFL_SensorError_Stat signal + +#ifndef OCUFL_SensorError_Stat_OCUFL_MSG_Error +#define OCUFL_SensorError_Stat_OCUFL_MSG_Error (1) +#endif + +#ifndef OCUFL_SensorError_Stat_OCUFL_MSG_No_error +#define OCUFL_SensorError_Stat_OCUFL_MSG_No_error (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Front left seat weight threshold indication. + // $0 = Reserved + // $1 = Child Seat + // $2 = Small Occupant + // $3 = Large Occupant + // 3 : "Large Occupant" + // 2 : "Small Occupant" + // 1 : "Child Seat" + // 0 : "Empty" + uint8_t OCUFL_OccupantWeight_Stat : 2; // Bits= 2 + + // Front Left seat occupied indication. + // $0 = Not Occupied + // $1 = Occupied + // OCSFL_SeatOccupied OCSFL_OccupantWeight OCSFL status + // 0x00 0x00 Empty + // 0x01 + // 1 : "Occupied" + // 0 : "Not Occupied" + uint8_t OCUFL_SeatOccupied_Stat : 1; // Bits= 1 + + // Front Left seat mat sensor fault indication. + // This bit shall remain latched for the duration of the current ignition cycle. + // $0 = No Error + // $1 = Error Detected + // 1 : "Error" + // 0 : "No error" + uint8_t OCUFL_SensorError_Stat : 1; // Bits= 1 + + // Rolling Counter [0 - 15] + uint8_t OCUFL_MSG_RC : 4; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t OCUFL_MSG_CS; // Bits= 8 + +#else + + // Front left seat weight threshold indication. + // $0 = Reserved + // $1 = Child Seat + // $2 = Small Occupant + // $3 = Large Occupant + // 3 : "Large Occupant" + // 2 : "Small Occupant" + // 1 : "Child Seat" + // 0 : "Empty" + uint8_t OCUFL_OccupantWeight_Stat; // Bits= 2 + + // Front Left seat occupied indication. + // $0 = Not Occupied + // $1 = Occupied + // OCSFL_SeatOccupied OCSFL_OccupantWeight OCSFL status + // 0x00 0x00 Empty + // 0x01 + // 1 : "Occupied" + // 0 : "Not Occupied" + uint8_t OCUFL_SeatOccupied_Stat; // Bits= 1 + + // Front Left seat mat sensor fault indication. + // This bit shall remain latched for the duration of the current ignition cycle. + // $0 = No Error + // $1 = Error Detected + // 1 : "Error" + // 0 : "No error" + uint8_t OCUFL_SensorError_Stat; // Bits= 1 + + // Rolling Counter [0 - 15] + uint8_t OCUFL_MSG_RC; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t OCUFL_MSG_CS; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} OCUFL_MSG_t; + +// def @OCUFR_MSG CAN Message (1314 0x522) +#define OCUFR_MSG_IDE (0U) +#define OCUFR_MSG_DLC (2U) +#define OCUFR_MSG_CANID (0x522U) +#define OCUFR_MSG_CYC (1000U) + +// Value tables for @OCUFR_OccupantWeight_Stat signal + +#ifndef OCUFR_OccupantWeight_Stat_OCUFR_MSG_Large_Occupant +#define OCUFR_OccupantWeight_Stat_OCUFR_MSG_Large_Occupant (3) +#endif + +#ifndef OCUFR_OccupantWeight_Stat_OCUFR_MSG_Small_Occupant +#define OCUFR_OccupantWeight_Stat_OCUFR_MSG_Small_Occupant (2) +#endif + +#ifndef OCUFR_OccupantWeight_Stat_OCUFR_MSG_Child_Seat +#define OCUFR_OccupantWeight_Stat_OCUFR_MSG_Child_Seat (1) +#endif + +#ifndef OCUFR_OccupantWeight_Stat_OCUFR_MSG_Empty +#define OCUFR_OccupantWeight_Stat_OCUFR_MSG_Empty (0) +#endif + + +// Value tables for @OCUFR_SeatOccupied_Stat signal + +#ifndef OCUFR_SeatOccupied_Stat_OCUFR_MSG_Occupied +#define OCUFR_SeatOccupied_Stat_OCUFR_MSG_Occupied (1) +#endif + +#ifndef OCUFR_SeatOccupied_Stat_OCUFR_MSG_Not_Occupied +#define OCUFR_SeatOccupied_Stat_OCUFR_MSG_Not_Occupied (0) +#endif + + +// Value tables for @OCUFR_SensorError_Stat signal + +#ifndef OCUFR_SensorError_Stat_OCUFR_MSG_Error +#define OCUFR_SensorError_Stat_OCUFR_MSG_Error (1) +#endif + +#ifndef OCUFR_SensorError_Stat_OCUFR_MSG_No_error +#define OCUFR_SensorError_Stat_OCUFR_MSG_No_error (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Front right seat weight threshold indication. + // $0 = Reserved + // $1 = Child Seat + // $2 = Small Occupant + // $3 = Large Occupant + // 3 : "Large Occupant" + // 2 : "Small Occupant" + // 1 : "Child Seat" + // 0 : "Empty" + uint8_t OCUFR_OccupantWeight_Stat : 2; // Bits= 2 + + // Front Right seat occupied indication. + // $0 = Not Occupied + // $1 = Occupied + // OCSFR_SeatOccupied OCSFR_OccupantWeight OCSFR status + // 0x00 0x00 Empty + // 0x01 + // 1 : "Occupied" + // 0 : "Not Occupied" + uint8_t OCUFR_SeatOccupied_Stat : 1; // Bits= 1 + + // Front Right seat mat sensor fault indication. + // This bit shall remain latched for the duration of the current ignition cycle. + // $0 = No Error + // $1 = Error Detected + // 1 : "Error" + // 0 : "No error" + uint8_t OCUFR_SensorError_Stat : 1; // Bits= 1 + + // Rolling Counter [0 - 15] + uint8_t OCUFR_MSG_RC : 4; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t OCUFR_MSG_CS; // Bits= 8 + +#else + + // Front right seat weight threshold indication. + // $0 = Reserved + // $1 = Child Seat + // $2 = Small Occupant + // $3 = Large Occupant + // 3 : "Large Occupant" + // 2 : "Small Occupant" + // 1 : "Child Seat" + // 0 : "Empty" + uint8_t OCUFR_OccupantWeight_Stat; // Bits= 2 + + // Front Right seat occupied indication. + // $0 = Not Occupied + // $1 = Occupied + // OCSFR_SeatOccupied OCSFR_OccupantWeight OCSFR status + // 0x00 0x00 Empty + // 0x01 + // 1 : "Occupied" + // 0 : "Not Occupied" + uint8_t OCUFR_SeatOccupied_Stat; // Bits= 1 + + // Front Right seat mat sensor fault indication. + // This bit shall remain latched for the duration of the current ignition cycle. + // $0 = No Error + // $1 = Error Detected + // 1 : "Error" + // 0 : "No error" + uint8_t OCUFR_SensorError_Stat; // Bits= 1 + + // Rolling Counter [0 - 15] + uint8_t OCUFR_MSG_RC; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t OCUFR_MSG_CS; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} OCUFR_MSG_t; + +// def @OCURL_MSG CAN Message (1315 0x523) +#define OCURL_MSG_IDE (0U) +#define OCURL_MSG_DLC (2U) +#define OCURL_MSG_CANID (0x523U) +#define OCURL_MSG_CYC (1000U) + +// Value tables for @OCURL_OccupantWeight_Stat signal + +#ifndef OCURL_OccupantWeight_Stat_OCURL_MSG_Large_Occupant +#define OCURL_OccupantWeight_Stat_OCURL_MSG_Large_Occupant (3) +#endif + +#ifndef OCURL_OccupantWeight_Stat_OCURL_MSG_Small_Occupant +#define OCURL_OccupantWeight_Stat_OCURL_MSG_Small_Occupant (2) +#endif + +#ifndef OCURL_OccupantWeight_Stat_OCURL_MSG_Child_Seat +#define OCURL_OccupantWeight_Stat_OCURL_MSG_Child_Seat (1) +#endif + +#ifndef OCURL_OccupantWeight_Stat_OCURL_MSG_Empty +#define OCURL_OccupantWeight_Stat_OCURL_MSG_Empty (0) +#endif + + +// Value tables for @OCURL_SeatOccupied_Stat signal + +#ifndef OCURL_SeatOccupied_Stat_OCURL_MSG_Occupied +#define OCURL_SeatOccupied_Stat_OCURL_MSG_Occupied (1) +#endif + +#ifndef OCURL_SeatOccupied_Stat_OCURL_MSG_Not_Occupied +#define OCURL_SeatOccupied_Stat_OCURL_MSG_Not_Occupied (0) +#endif + + +// Value tables for @OCURL_SensorError_Stat signal + +#ifndef OCURL_SensorError_Stat_OCURL_MSG_Error +#define OCURL_SensorError_Stat_OCURL_MSG_Error (1) +#endif + +#ifndef OCURL_SensorError_Stat_OCURL_MSG_No_error +#define OCURL_SensorError_Stat_OCURL_MSG_No_error (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Rear left seat weight threshold indication. + // $0 = Reserved + // $1 = Child Seat + // $2 = Small Occupant + // $3 = Large Occupant + // 3 : "Large Occupant" + // 2 : "Small Occupant" + // 1 : "Child Seat" + // 0 : "Empty" + uint8_t OCURL_OccupantWeight_Stat : 2; // Bits= 2 + + // Rear Left seat occupied indication. + // $0 = Not Occupied + // $1 = Occupied + // OCSRL_SeatOccupied OCSRL_OccupantWeight OCSRL status + // 0x00 0x00 Empty + // 0x01 + // 1 : "Occupied" + // 0 : "Not Occupied" + uint8_t OCURL_SeatOccupied_Stat : 1; // Bits= 1 + + // Rear Left seat mat sensor fault indication. + // This bit shall remain latched for the duration of the current ignition cycle. + // $0 = No Error + // $1 = Error Detected + // 1 : "Error" + // 0 : "No error" + uint8_t OCURL_SensorError_Stat : 1; // Bits= 1 + + // Rolling Counter [0 - 15] + uint8_t OCURL_MSG_RC : 4; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t OCURL_MSG_CS; // Bits= 8 + +#else + + // Rear left seat weight threshold indication. + // $0 = Reserved + // $1 = Child Seat + // $2 = Small Occupant + // $3 = Large Occupant + // 3 : "Large Occupant" + // 2 : "Small Occupant" + // 1 : "Child Seat" + // 0 : "Empty" + uint8_t OCURL_OccupantWeight_Stat; // Bits= 2 + + // Rear Left seat occupied indication. + // $0 = Not Occupied + // $1 = Occupied + // OCSRL_SeatOccupied OCSRL_OccupantWeight OCSRL status + // 0x00 0x00 Empty + // 0x01 + // 1 : "Occupied" + // 0 : "Not Occupied" + uint8_t OCURL_SeatOccupied_Stat; // Bits= 1 + + // Rear Left seat mat sensor fault indication. + // This bit shall remain latched for the duration of the current ignition cycle. + // $0 = No Error + // $1 = Error Detected + // 1 : "Error" + // 0 : "No error" + uint8_t OCURL_SensorError_Stat; // Bits= 1 + + // Rolling Counter [0 - 15] + uint8_t OCURL_MSG_RC; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t OCURL_MSG_CS; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} OCURL_MSG_t; + +// def @OCURR_MSG CAN Message (1316 0x524) +#define OCURR_MSG_IDE (0U) +#define OCURR_MSG_DLC (2U) +#define OCURR_MSG_CANID (0x524U) +#define OCURR_MSG_CYC (1000U) + +// Value tables for @OCURR_OccupantWeight_Stat signal + +#ifndef OCURR_OccupantWeight_Stat_OCURR_MSG_Large_Occupant +#define OCURR_OccupantWeight_Stat_OCURR_MSG_Large_Occupant (3) +#endif + +#ifndef OCURR_OccupantWeight_Stat_OCURR_MSG_Small_Occupant +#define OCURR_OccupantWeight_Stat_OCURR_MSG_Small_Occupant (2) +#endif + +#ifndef OCURR_OccupantWeight_Stat_OCURR_MSG_Child_Seat +#define OCURR_OccupantWeight_Stat_OCURR_MSG_Child_Seat (1) +#endif + +#ifndef OCURR_OccupantWeight_Stat_OCURR_MSG_Empty +#define OCURR_OccupantWeight_Stat_OCURR_MSG_Empty (0) +#endif + + +// Value tables for @OCURR_SeatOccupied_Stat signal + +#ifndef OCURR_SeatOccupied_Stat_OCURR_MSG_Occupied +#define OCURR_SeatOccupied_Stat_OCURR_MSG_Occupied (1) +#endif + +#ifndef OCURR_SeatOccupied_Stat_OCURR_MSG_Not_Occupied +#define OCURR_SeatOccupied_Stat_OCURR_MSG_Not_Occupied (0) +#endif + + +// Value tables for @OCURR_SensorError_Stat signal + +#ifndef OCURR_SensorError_Stat_OCURR_MSG_Error +#define OCURR_SensorError_Stat_OCURR_MSG_Error (1) +#endif + +#ifndef OCURR_SensorError_Stat_OCURR_MSG_No_error +#define OCURR_SensorError_Stat_OCURR_MSG_No_error (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Rear right seat weight threshold indication. + // $0 = Reserved + // $1 = Child Seat + // $2 = Small Occupant + // $3 = Large Occupant + // 3 : "Large Occupant" + // 2 : "Small Occupant" + // 1 : "Child Seat" + // 0 : "Empty" + uint8_t OCURR_OccupantWeight_Stat : 2; // Bits= 2 + + // Rear Right seat occupied indication. + // $0 = Not Occupied + // $1 = Occupied + // OCSRR_SeatOccupied OCSRR_OccupantWeight OCSRR status + // 0x00 0x00 Empty + // 0x01 + // 1 : "Occupied" + // 0 : "Not Occupied" + uint8_t OCURR_SeatOccupied_Stat : 1; // Bits= 1 + + // Rear Right seat mat sensor fault indication. + // This bit shall remain latched for the duration of the current ignition cycle. + // $0 = No Error + // $1 = Error Detected + // 1 : "Error" + // 0 : "No error" + uint8_t OCURR_SensorError_Stat : 1; // Bits= 1 + + // Rolling Counter [0 - 15] + uint8_t OCURR_MSG_RC : 4; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t OCURR_MSG_CS; // Bits= 8 + +#else + + // Rear right seat weight threshold indication. + // $0 = Reserved + // $1 = Child Seat + // $2 = Small Occupant + // $3 = Large Occupant + // 3 : "Large Occupant" + // 2 : "Small Occupant" + // 1 : "Child Seat" + // 0 : "Empty" + uint8_t OCURR_OccupantWeight_Stat; // Bits= 2 + + // Rear Right seat occupied indication. + // $0 = Not Occupied + // $1 = Occupied + // OCSRR_SeatOccupied OCSRR_OccupantWeight OCSRR status + // 0x00 0x00 Empty + // 0x01 + // 1 : "Occupied" + // 0 : "Not Occupied" + uint8_t OCURR_SeatOccupied_Stat; // Bits= 1 + + // Rear Right seat mat sensor fault indication. + // This bit shall remain latched for the duration of the current ignition cycle. + // $0 = No Error + // $1 = Error Detected + // 1 : "Error" + // 0 : "No error" + uint8_t OCURR_SensorError_Stat; // Bits= 1 + + // Rolling Counter [0 - 15] + uint8_t OCURR_MSG_RC; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t OCURR_MSG_CS; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} OCURR_MSG_t; + +// RBCU Errors to FIU +// def @RBCU_BODY_Stat CAN Message (1317 0x525) +#define RBCU_BODY_Stat_IDE (0U) +#define RBCU_BODY_Stat_DLC (2U) +#define RBCU_BODY_Stat_CANID (0x525U) +#define RBCU_BODY_Stat_CYC (250U) + +// Value tables for @RBCU_LeftErr_Stat signal + +#ifndef RBCU_LeftErr_Stat_RBCU_BODY_Stat_Error +#define RBCU_LeftErr_Stat_RBCU_BODY_Stat_Error (1) +#endif + +#ifndef RBCU_LeftErr_Stat_RBCU_BODY_Stat_No_error +#define RBCU_LeftErr_Stat_RBCU_BODY_Stat_No_error (0) +#endif + + +// Value tables for @RBCU_LeftAntipinch_Stat signal + +#ifndef RBCU_LeftAntipinch_Stat_RBCU_BODY_Stat_Antipinch_Occurred +#define RBCU_LeftAntipinch_Stat_RBCU_BODY_Stat_Antipinch_Occurred (1) +#endif + +#ifndef RBCU_LeftAntipinch_Stat_RBCU_BODY_Stat_No_Antipinch_Occured +#define RBCU_LeftAntipinch_Stat_RBCU_BODY_Stat_No_Antipinch_Occured (0) +#endif + + +// Value tables for @RBCU_LeftMotion_Stat signal + +#ifndef RBCU_LeftMotion_Stat_RBCU_BODY_Stat_Opening +#define RBCU_LeftMotion_Stat_RBCU_BODY_Stat_Opening (2) +#endif + +#ifndef RBCU_LeftMotion_Stat_RBCU_BODY_Stat_Closing +#define RBCU_LeftMotion_Stat_RBCU_BODY_Stat_Closing (1) +#endif + +#ifndef RBCU_LeftMotion_Stat_RBCU_BODY_Stat_Stopped +#define RBCU_LeftMotion_Stat_RBCU_BODY_Stat_Stopped (0) +#endif + + +// Value tables for @RBCU_LeftPosition_Stat signal + +#ifndef RBCU_LeftPosition_Stat_RBCU_BODY_Stat_Opened +#define RBCU_LeftPosition_Stat_RBCU_BODY_Stat_Opened (3) +#endif + +#ifndef RBCU_LeftPosition_Stat_RBCU_BODY_Stat_Intermediate +#define RBCU_LeftPosition_Stat_RBCU_BODY_Stat_Intermediate (2) +#endif + +#ifndef RBCU_LeftPosition_Stat_RBCU_BODY_Stat_Closed +#define RBCU_LeftPosition_Stat_RBCU_BODY_Stat_Closed (1) +#endif + +#ifndef RBCU_LeftPosition_Stat_RBCU_BODY_Stat_Unknown +#define RBCU_LeftPosition_Stat_RBCU_BODY_Stat_Unknown (0) +#endif + + +// Value tables for @RBCU_LeftCalibration_Stat signal + +#ifndef RBCU_LeftCalibration_Stat_RBCU_BODY_Stat_Calibrated +#define RBCU_LeftCalibration_Stat_RBCU_BODY_Stat_Calibrated (1) +#endif + +#ifndef RBCU_LeftCalibration_Stat_RBCU_BODY_Stat_Not_calibrated +#define RBCU_LeftCalibration_Stat_RBCU_BODY_Stat_Not_calibrated (0) +#endif + + +// Value tables for @RBCU_RightErr_Stat signal + +#ifndef RBCU_RightErr_Stat_RBCU_BODY_Stat_Error +#define RBCU_RightErr_Stat_RBCU_BODY_Stat_Error (1) +#endif + +#ifndef RBCU_RightErr_Stat_RBCU_BODY_Stat_No_error +#define RBCU_RightErr_Stat_RBCU_BODY_Stat_No_error (0) +#endif + + +// Value tables for @RBCU_RightAntipinch_Stat signal + +#ifndef RBCU_RightAntipinch_Stat_RBCU_BODY_Stat_Antipinch_Occurred +#define RBCU_RightAntipinch_Stat_RBCU_BODY_Stat_Antipinch_Occurred (1) +#endif + +#ifndef RBCU_RightAntipinch_Stat_RBCU_BODY_Stat_No_Antipinch_Occured +#define RBCU_RightAntipinch_Stat_RBCU_BODY_Stat_No_Antipinch_Occured (0) +#endif + + +// Value tables for @RBCU_RightMotion_Stat signal + +#ifndef RBCU_RightMotion_Stat_RBCU_BODY_Stat_Opening +#define RBCU_RightMotion_Stat_RBCU_BODY_Stat_Opening (2) +#endif + +#ifndef RBCU_RightMotion_Stat_RBCU_BODY_Stat_Closing +#define RBCU_RightMotion_Stat_RBCU_BODY_Stat_Closing (1) +#endif + +#ifndef RBCU_RightMotion_Stat_RBCU_BODY_Stat_Stopped +#define RBCU_RightMotion_Stat_RBCU_BODY_Stat_Stopped (0) +#endif + + +// Value tables for @RBCU_RightPosition_Stat signal + +#ifndef RBCU_RightPosition_Stat_RBCU_BODY_Stat_Opened +#define RBCU_RightPosition_Stat_RBCU_BODY_Stat_Opened (3) +#endif + +#ifndef RBCU_RightPosition_Stat_RBCU_BODY_Stat_Intermediate +#define RBCU_RightPosition_Stat_RBCU_BODY_Stat_Intermediate (2) +#endif + +#ifndef RBCU_RightPosition_Stat_RBCU_BODY_Stat_Closed +#define RBCU_RightPosition_Stat_RBCU_BODY_Stat_Closed (1) +#endif + +#ifndef RBCU_RightPosition_Stat_RBCU_BODY_Stat_Unknown +#define RBCU_RightPosition_Stat_RBCU_BODY_Stat_Unknown (0) +#endif + + +// Value tables for @RBCU_RightCalibration_Stat signal + +#ifndef RBCU_RightCalibration_Stat_RBCU_BODY_Stat_Calibrated +#define RBCU_RightCalibration_Stat_RBCU_BODY_Stat_Calibrated (1) +#endif + +#ifndef RBCU_RightCalibration_Stat_RBCU_BODY_Stat_Not_calibrated +#define RBCU_RightCalibration_Stat_RBCU_BODY_Stat_Not_calibrated (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Left running board error case signal + // 1 : "Error" + // 0 : "No error" + uint8_t RBCU_LeftErr_Stat : 1; // Bits= 1 + + // Left running board antipinch detect status + // 1 : "Antipinch Occurred" + // 0 : "No Antipinch Occured" + uint8_t RBCU_LeftAntipinch_Stat : 1; // Bits= 1 + + // Left runing board motion status + // 2 : "Opening" + // 1 : "Closing" + // 0 : "Stopped" + uint8_t RBCU_LeftMotion_Stat : 2; // Bits= 2 + + // Left running board position status + // 3 : "Opened" + // 2 : "Intermediate" + // 1 : "Closed" + // 0 : "Unknown" + uint8_t RBCU_LeftPosition_Stat : 2; // Bits= 2 + + // Left running board calibration status + // 1 : "Calibrated" + // 0 : "Not calibrated" + uint8_t RBCU_LeftCalibration_Stat : 1; // Bits= 1 + + // Right running board error case signal + // 1 : "Error" + // 0 : "No error" + uint8_t RBCU_RightErr_Stat : 1; // Bits= 1 + + // Right running board antipinch detect status + // 1 : "Antipinch Occurred" + // 0 : "No Antipinch Occured" + uint8_t RBCU_RightAntipinch_Stat : 1; // Bits= 1 + + // Right runing board motion status + // 2 : "Opening" + // 1 : "Closing" + // 0 : "Stopped" + uint8_t RBCU_RightMotion_Stat : 2; // Bits= 2 + + // Right running board position status + // 3 : "Opened" + // 2 : "Intermediate" + // 1 : "Closed" + // 0 : "Unknown" + uint8_t RBCU_RightPosition_Stat : 2; // Bits= 2 + + // Right running board calibration status + // 1 : "Calibrated" + // 0 : "Not calibrated" + uint8_t RBCU_RightCalibration_Stat : 1; // Bits= 1 + +#else + + // Left running board error case signal + // 1 : "Error" + // 0 : "No error" + uint8_t RBCU_LeftErr_Stat; // Bits= 1 + + // Left running board antipinch detect status + // 1 : "Antipinch Occurred" + // 0 : "No Antipinch Occured" + uint8_t RBCU_LeftAntipinch_Stat; // Bits= 1 + + // Left runing board motion status + // 2 : "Opening" + // 1 : "Closing" + // 0 : "Stopped" + uint8_t RBCU_LeftMotion_Stat; // Bits= 2 + + // Left running board position status + // 3 : "Opened" + // 2 : "Intermediate" + // 1 : "Closed" + // 0 : "Unknown" + uint8_t RBCU_LeftPosition_Stat; // Bits= 2 + + // Left running board calibration status + // 1 : "Calibrated" + // 0 : "Not calibrated" + uint8_t RBCU_LeftCalibration_Stat; // Bits= 1 + + // Right running board error case signal + // 1 : "Error" + // 0 : "No error" + uint8_t RBCU_RightErr_Stat; // Bits= 1 + + // Right running board antipinch detect status + // 1 : "Antipinch Occurred" + // 0 : "No Antipinch Occured" + uint8_t RBCU_RightAntipinch_Stat; // Bits= 1 + + // Right runing board motion status + // 2 : "Opening" + // 1 : "Closing" + // 0 : "Stopped" + uint8_t RBCU_RightMotion_Stat; // Bits= 2 + + // Right running board position status + // 3 : "Opened" + // 2 : "Intermediate" + // 1 : "Closed" + // 0 : "Unknown" + uint8_t RBCU_RightPosition_Stat; // Bits= 2 + + // Right running board calibration status + // 1 : "Calibrated" + // 0 : "Not calibrated" + uint8_t RBCU_RightCalibration_Stat; // Bits= 1 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} RBCU_BODY_Stat_t; + +// def @FIU_SMRL_REQ_CTR_SEATS CAN Message (1324 0x52c) +#define FIU_SMRL_REQ_CTR_SEATS_IDE (0U) +#define FIU_SMRL_REQ_CTR_SEATS_DLC (7U) +#define FIU_SMRL_REQ_CTR_SEATS_CANID (0x52cU) + +// Value tables for @FIU_SMRL_SeatHeight_Req signal + +#ifndef FIU_SMRL_SeatHeight_Req_FIU_SMRL_REQ_CTR_SEATS_Reserved +#define FIU_SMRL_SeatHeight_Req_FIU_SMRL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMRL_SeatHeight_Req_FIU_SMRL_REQ_CTR_SEATS_Decrease +#define FIU_SMRL_SeatHeight_Req_FIU_SMRL_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMRL_SeatHeight_Req_FIU_SMRL_REQ_CTR_SEATS_Increase +#define FIU_SMRL_SeatHeight_Req_FIU_SMRL_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMRL_SeatHeight_Req_FIU_SMRL_REQ_CTR_SEATS_No_action +#define FIU_SMRL_SeatHeight_Req_FIU_SMRL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRL_HeadRestHeight_Req signal + +#ifndef FIU_SMRL_HeadRestHeight_Req_FIU_SMRL_REQ_CTR_SEATS_Reserved +#define FIU_SMRL_HeadRestHeight_Req_FIU_SMRL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMRL_HeadRestHeight_Req_FIU_SMRL_REQ_CTR_SEATS_Decrease +#define FIU_SMRL_HeadRestHeight_Req_FIU_SMRL_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMRL_HeadRestHeight_Req_FIU_SMRL_REQ_CTR_SEATS_Increase +#define FIU_SMRL_HeadRestHeight_Req_FIU_SMRL_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMRL_HeadRestHeight_Req_FIU_SMRL_REQ_CTR_SEATS_No_action +#define FIU_SMRL_HeadRestHeight_Req_FIU_SMRL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRL_SeatLongitudinal_Req signal + +#ifndef FIU_SMRL_SeatLongitudinal_Req_FIU_SMRL_REQ_CTR_SEATS_Reserved +#define FIU_SMRL_SeatLongitudinal_Req_FIU_SMRL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMRL_SeatLongitudinal_Req_FIU_SMRL_REQ_CTR_SEATS_Decrease +#define FIU_SMRL_SeatLongitudinal_Req_FIU_SMRL_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMRL_SeatLongitudinal_Req_FIU_SMRL_REQ_CTR_SEATS_Increase +#define FIU_SMRL_SeatLongitudinal_Req_FIU_SMRL_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMRL_SeatLongitudinal_Req_FIU_SMRL_REQ_CTR_SEATS_No_action +#define FIU_SMRL_SeatLongitudinal_Req_FIU_SMRL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRL_SeatHeadRestInclin_Req signal + +#ifndef FIU_SMRL_SeatHeadRestInclin_Req_FIU_SMRL_REQ_CTR_SEATS_Reserved +#define FIU_SMRL_SeatHeadRestInclin_Req_FIU_SMRL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMRL_SeatHeadRestInclin_Req_FIU_SMRL_REQ_CTR_SEATS_Decrease +#define FIU_SMRL_SeatHeadRestInclin_Req_FIU_SMRL_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMRL_SeatHeadRestInclin_Req_FIU_SMRL_REQ_CTR_SEATS_Increase +#define FIU_SMRL_SeatHeadRestInclin_Req_FIU_SMRL_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMRL_SeatHeadRestInclin_Req_FIU_SMRL_REQ_CTR_SEATS_No_action +#define FIU_SMRL_SeatHeadRestInclin_Req_FIU_SMRL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRL_SeatSurfaceLong_Req signal + +#ifndef FIU_SMRL_SeatSurfaceLong_Req_FIU_SMRL_REQ_CTR_SEATS_Reserved +#define FIU_SMRL_SeatSurfaceLong_Req_FIU_SMRL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMRL_SeatSurfaceLong_Req_FIU_SMRL_REQ_CTR_SEATS_Decrease +#define FIU_SMRL_SeatSurfaceLong_Req_FIU_SMRL_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMRL_SeatSurfaceLong_Req_FIU_SMRL_REQ_CTR_SEATS_Increase +#define FIU_SMRL_SeatSurfaceLong_Req_FIU_SMRL_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMRL_SeatSurfaceLong_Req_FIU_SMRL_REQ_CTR_SEATS_No_action +#define FIU_SMRL_SeatSurfaceLong_Req_FIU_SMRL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRL_SeatLegSupportH_Req signal + +#ifndef FIU_SMRL_SeatLegSupportH_Req_FIU_SMRL_REQ_CTR_SEATS_Reserved +#define FIU_SMRL_SeatLegSupportH_Req_FIU_SMRL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMRL_SeatLegSupportH_Req_FIU_SMRL_REQ_CTR_SEATS_Decrease +#define FIU_SMRL_SeatLegSupportH_Req_FIU_SMRL_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMRL_SeatLegSupportH_Req_FIU_SMRL_REQ_CTR_SEATS_Increase +#define FIU_SMRL_SeatLegSupportH_Req_FIU_SMRL_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMRL_SeatLegSupportH_Req_FIU_SMRL_REQ_CTR_SEATS_No_action +#define FIU_SMRL_SeatLegSupportH_Req_FIU_SMRL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRL_SeatLegSupportLong_Req signal + +#ifndef FIU_SMRL_SeatLegSupportLong_Req_FIU_SMRL_REQ_CTR_SEATS_Resertved +#define FIU_SMRL_SeatLegSupportLong_Req_FIU_SMRL_REQ_CTR_SEATS_Resertved (3) +#endif + +#ifndef FIU_SMRL_SeatLegSupportLong_Req_FIU_SMRL_REQ_CTR_SEATS_Decrease +#define FIU_SMRL_SeatLegSupportLong_Req_FIU_SMRL_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMRL_SeatLegSupportLong_Req_FIU_SMRL_REQ_CTR_SEATS_Increase +#define FIU_SMRL_SeatLegSupportLong_Req_FIU_SMRL_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMRL_SeatLegSupportLong_Req_FIU_SMRL_REQ_CTR_SEATS_No_action +#define FIU_SMRL_SeatLegSupportLong_Req_FIU_SMRL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRL_SeatInclination_Req signal + +#ifndef FIU_SMRL_SeatInclination_Req_FIU_SMRL_REQ_CTR_SEATS_Reserved +#define FIU_SMRL_SeatInclination_Req_FIU_SMRL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMRL_SeatInclination_Req_FIU_SMRL_REQ_CTR_SEATS_Decrease +#define FIU_SMRL_SeatInclination_Req_FIU_SMRL_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMRL_SeatInclination_Req_FIU_SMRL_REQ_CTR_SEATS_Increase +#define FIU_SMRL_SeatInclination_Req_FIU_SMRL_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMRL_SeatInclination_Req_FIU_SMRL_REQ_CTR_SEATS_No_action +#define FIU_SMRL_SeatInclination_Req_FIU_SMRL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRL_SeatBackRestInc_Req signal + +#ifndef FIU_SMRL_SeatBackRestInc_Req_FIU_SMRL_REQ_CTR_SEATS_Reserved +#define FIU_SMRL_SeatBackRestInc_Req_FIU_SMRL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMRL_SeatBackRestInc_Req_FIU_SMRL_REQ_CTR_SEATS_Decrease +#define FIU_SMRL_SeatBackRestInc_Req_FIU_SMRL_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMRL_SeatBackRestInc_Req_FIU_SMRL_REQ_CTR_SEATS_Increase +#define FIU_SMRL_SeatBackRestInc_Req_FIU_SMRL_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMRL_SeatBackRestInc_Req_FIU_SMRL_REQ_CTR_SEATS_No_action +#define FIU_SMRL_SeatBackRestInc_Req_FIU_SMRL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRL_SeatLumbarSupportH_Req signal + +#ifndef FIU_SMRL_SeatLumbarSupportH_Req_FIU_SMRL_REQ_CTR_SEATS_Reserved +#define FIU_SMRL_SeatLumbarSupportH_Req_FIU_SMRL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMRL_SeatLumbarSupportH_Req_FIU_SMRL_REQ_CTR_SEATS_Decrease +#define FIU_SMRL_SeatLumbarSupportH_Req_FIU_SMRL_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMRL_SeatLumbarSupportH_Req_FIU_SMRL_REQ_CTR_SEATS_Increase +#define FIU_SMRL_SeatLumbarSupportH_Req_FIU_SMRL_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMRL_SeatLumbarSupportH_Req_FIU_SMRL_REQ_CTR_SEATS_No_action +#define FIU_SMRL_SeatLumbarSupportH_Req_FIU_SMRL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRL_SeatBackRestHeadInc_Req signal + +#ifndef FIU_SMRL_SeatBackRestHeadInc_Req_FIU_SMRL_REQ_CTR_SEATS_Reserved +#define FIU_SMRL_SeatBackRestHeadInc_Req_FIU_SMRL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMRL_SeatBackRestHeadInc_Req_FIU_SMRL_REQ_CTR_SEATS_Decrease +#define FIU_SMRL_SeatBackRestHeadInc_Req_FIU_SMRL_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMRL_SeatBackRestHeadInc_Req_FIU_SMRL_REQ_CTR_SEATS_Increase +#define FIU_SMRL_SeatBackRestHeadInc_Req_FIU_SMRL_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMRL_SeatBackRestHeadInc_Req_FIU_SMRL_REQ_CTR_SEATS_No_action +#define FIU_SMRL_SeatBackRestHeadInc_Req_FIU_SMRL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRL_SeatLumbarSupDepth_Req signal + +#ifndef FIU_SMRL_SeatLumbarSupDepth_Req_FIU_SMRL_REQ_CTR_SEATS_Reserved +#define FIU_SMRL_SeatLumbarSupDepth_Req_FIU_SMRL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMRL_SeatLumbarSupDepth_Req_FIU_SMRL_REQ_CTR_SEATS_Decrease +#define FIU_SMRL_SeatLumbarSupDepth_Req_FIU_SMRL_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMRL_SeatLumbarSupDepth_Req_FIU_SMRL_REQ_CTR_SEATS_Increase +#define FIU_SMRL_SeatLumbarSupDepth_Req_FIU_SMRL_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMRL_SeatLumbarSupDepth_Req_FIU_SMRL_REQ_CTR_SEATS_No_action +#define FIU_SMRL_SeatLumbarSupDepth_Req_FIU_SMRL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRL_BackRestWidth_Req signal + +#ifndef FIU_SMRL_BackRestWidth_Req_FIU_SMRL_REQ_CTR_SEATS_Reserved +#define FIU_SMRL_BackRestWidth_Req_FIU_SMRL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMRL_BackRestWidth_Req_FIU_SMRL_REQ_CTR_SEATS_Decrease +#define FIU_SMRL_BackRestWidth_Req_FIU_SMRL_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMRL_BackRestWidth_Req_FIU_SMRL_REQ_CTR_SEATS_Increase +#define FIU_SMRL_BackRestWidth_Req_FIU_SMRL_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMRL_BackRestWidth_Req_FIU_SMRL_REQ_CTR_SEATS_No_action +#define FIU_SMRL_BackRestWidth_Req_FIU_SMRL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRL_SeatCushionSupport_Req signal + +#ifndef FIU_SMRL_SeatCushionSupport_Req_FIU_SMRL_REQ_CTR_SEATS_Reserved +#define FIU_SMRL_SeatCushionSupport_Req_FIU_SMRL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMRL_SeatCushionSupport_Req_FIU_SMRL_REQ_CTR_SEATS_Decrease +#define FIU_SMRL_SeatCushionSupport_Req_FIU_SMRL_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMRL_SeatCushionSupport_Req_FIU_SMRL_REQ_CTR_SEATS_Increase +#define FIU_SMRL_SeatCushionSupport_Req_FIU_SMRL_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMRL_SeatCushionSupport_Req_FIU_SMRL_REQ_CTR_SEATS_No_action +#define FIU_SMRL_SeatCushionSupport_Req_FIU_SMRL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRL_SeatMassage_Req signal + +#ifndef FIU_SMRL_SeatMassage_Req_FIU_SMRL_REQ_CTR_SEATS_Reserved +#define FIU_SMRL_SeatMassage_Req_FIU_SMRL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMRL_SeatMassage_Req_FIU_SMRL_REQ_CTR_SEATS_Massage_ON +#define FIU_SMRL_SeatMassage_Req_FIU_SMRL_REQ_CTR_SEATS_Massage_ON (2) +#endif + +#ifndef FIU_SMRL_SeatMassage_Req_FIU_SMRL_REQ_CTR_SEATS_Massage_OFF +#define FIU_SMRL_SeatMassage_Req_FIU_SMRL_REQ_CTR_SEATS_Massage_OFF (1) +#endif + +#ifndef FIU_SMRL_SeatMassage_Req_FIU_SMRL_REQ_CTR_SEATS_No_action +#define FIU_SMRL_SeatMassage_Req_FIU_SMRL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRL_SeatVentilation_Req signal + +#ifndef FIU_SMRL_SeatVentilation_Req_FIU_SMRL_REQ_CTR_SEATS_High_power +#define FIU_SMRL_SeatVentilation_Req_FIU_SMRL_REQ_CTR_SEATS_High_power (3) +#endif + +#ifndef FIU_SMRL_SeatVentilation_Req_FIU_SMRL_REQ_CTR_SEATS_Middle_power +#define FIU_SMRL_SeatVentilation_Req_FIU_SMRL_REQ_CTR_SEATS_Middle_power (2) +#endif + +#ifndef FIU_SMRL_SeatVentilation_Req_FIU_SMRL_REQ_CTR_SEATS_Low_power +#define FIU_SMRL_SeatVentilation_Req_FIU_SMRL_REQ_CTR_SEATS_Low_power (1) +#endif + +#ifndef FIU_SMRL_SeatVentilation_Req_FIU_SMRL_REQ_CTR_SEATS_Off +#define FIU_SMRL_SeatVentilation_Req_FIU_SMRL_REQ_CTR_SEATS_Off (0) +#endif + + +// Value tables for @FIU_SMRL_SeatVentBalance_Req signal + +#ifndef FIU_SMRL_SeatVentBalance_Req_FIU_SMRL_REQ_CTR_SEATS_Backrest_100_Cushion_00_3 +#define FIU_SMRL_SeatVentBalance_Req_FIU_SMRL_REQ_CTR_SEATS_Backrest_100_Cushion_00_3 (7) +#endif + +#ifndef FIU_SMRL_SeatVentBalance_Req_FIU_SMRL_REQ_CTR_SEATS_Backrest_100_Cushion_33_2 +#define FIU_SMRL_SeatVentBalance_Req_FIU_SMRL_REQ_CTR_SEATS_Backrest_100_Cushion_33_2 (6) +#endif + +#ifndef FIU_SMRL_SeatVentBalance_Req_FIU_SMRL_REQ_CTR_SEATS_Backrest_100_Cushion_67_1 +#define FIU_SMRL_SeatVentBalance_Req_FIU_SMRL_REQ_CTR_SEATS_Backrest_100_Cushion_67_1 (5) +#endif + +#ifndef FIU_SMRL_SeatVentBalance_Req_FIU_SMRL_REQ_CTR_SEATS_Backrest_100_Cushion_100_0 +#define FIU_SMRL_SeatVentBalance_Req_FIU_SMRL_REQ_CTR_SEATS_Backrest_100_Cushion_100_0 (4) +#endif + +#ifndef FIU_SMRL_SeatVentBalance_Req_FIU_SMRL_REQ_CTR_SEATS_Backrest_67_Cushion_100_1 +#define FIU_SMRL_SeatVentBalance_Req_FIU_SMRL_REQ_CTR_SEATS_Backrest_67_Cushion_100_1 (3) +#endif + +#ifndef FIU_SMRL_SeatVentBalance_Req_FIU_SMRL_REQ_CTR_SEATS_Backrest_33_Cushion_100_2 +#define FIU_SMRL_SeatVentBalance_Req_FIU_SMRL_REQ_CTR_SEATS_Backrest_33_Cushion_100_2 (2) +#endif + +#ifndef FIU_SMRL_SeatVentBalance_Req_FIU_SMRL_REQ_CTR_SEATS_Backrest_00_Cushion_100_3 +#define FIU_SMRL_SeatVentBalance_Req_FIU_SMRL_REQ_CTR_SEATS_Backrest_00_Cushion_100_3 (1) +#endif + +#ifndef FIU_SMRL_SeatVentBalance_Req_FIU_SMRL_REQ_CTR_SEATS_No_action +#define FIU_SMRL_SeatVentBalance_Req_FIU_SMRL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRL_SeatMassageIntence_Req signal + +#ifndef FIU_SMRL_SeatMassageIntence_Req_FIU_SMRL_REQ_CTR_SEATS_High_power +#define FIU_SMRL_SeatMassageIntence_Req_FIU_SMRL_REQ_CTR_SEATS_High_power (3) +#endif + +#ifndef FIU_SMRL_SeatMassageIntence_Req_FIU_SMRL_REQ_CTR_SEATS_Middle_power +#define FIU_SMRL_SeatMassageIntence_Req_FIU_SMRL_REQ_CTR_SEATS_Middle_power (2) +#endif + +#ifndef FIU_SMRL_SeatMassageIntence_Req_FIU_SMRL_REQ_CTR_SEATS_Low_power +#define FIU_SMRL_SeatMassageIntence_Req_FIU_SMRL_REQ_CTR_SEATS_Low_power (1) +#endif + +#ifndef FIU_SMRL_SeatMassageIntence_Req_FIU_SMRL_REQ_CTR_SEATS_No_action +#define FIU_SMRL_SeatMassageIntence_Req_FIU_SMRL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRL_SeatHeating_Req signal + +#ifndef FIU_SMRL_SeatHeating_Req_FIU_SMRL_REQ_CTR_SEATS_High_power +#define FIU_SMRL_SeatHeating_Req_FIU_SMRL_REQ_CTR_SEATS_High_power (3) +#endif + +#ifndef FIU_SMRL_SeatHeating_Req_FIU_SMRL_REQ_CTR_SEATS_Middle_power +#define FIU_SMRL_SeatHeating_Req_FIU_SMRL_REQ_CTR_SEATS_Middle_power (2) +#endif + +#ifndef FIU_SMRL_SeatHeating_Req_FIU_SMRL_REQ_CTR_SEATS_Low_power +#define FIU_SMRL_SeatHeating_Req_FIU_SMRL_REQ_CTR_SEATS_Low_power (1) +#endif + +#ifndef FIU_SMRL_SeatHeating_Req_FIU_SMRL_REQ_CTR_SEATS_Off +#define FIU_SMRL_SeatHeating_Req_FIU_SMRL_REQ_CTR_SEATS_Off (0) +#endif + + +// Value tables for @FIU_SMRL_ActiveSupport_Req signal + +#ifndef FIU_SMRL_ActiveSupport_Req_FIU_SMRL_REQ_CTR_SEATS_Active +#define FIU_SMRL_ActiveSupport_Req_FIU_SMRL_REQ_CTR_SEATS_Active (1) +#endif + +#ifndef FIU_SMRL_ActiveSupport_Req_FIU_SMRL_REQ_CTR_SEATS_Inactive +#define FIU_SMRL_ActiveSupport_Req_FIU_SMRL_REQ_CTR_SEATS_Inactive (0) +#endif + + +// Value tables for @FIU_SMRL_SeatHeatBalance_Req signal + +#ifndef FIU_SMRL_SeatHeatBalance_Req_FIU_SMRL_REQ_CTR_SEATS_Backrest_100_Cushion_00_3 +#define FIU_SMRL_SeatHeatBalance_Req_FIU_SMRL_REQ_CTR_SEATS_Backrest_100_Cushion_00_3 (7) +#endif + +#ifndef FIU_SMRL_SeatHeatBalance_Req_FIU_SMRL_REQ_CTR_SEATS_Backrest_100_Cushion_33_2 +#define FIU_SMRL_SeatHeatBalance_Req_FIU_SMRL_REQ_CTR_SEATS_Backrest_100_Cushion_33_2 (6) +#endif + +#ifndef FIU_SMRL_SeatHeatBalance_Req_FIU_SMRL_REQ_CTR_SEATS_Backrest_100_Cushion_67_1 +#define FIU_SMRL_SeatHeatBalance_Req_FIU_SMRL_REQ_CTR_SEATS_Backrest_100_Cushion_67_1 (5) +#endif + +#ifndef FIU_SMRL_SeatHeatBalance_Req_FIU_SMRL_REQ_CTR_SEATS_Backrest_100_Cushion_100_0 +#define FIU_SMRL_SeatHeatBalance_Req_FIU_SMRL_REQ_CTR_SEATS_Backrest_100_Cushion_100_0 (4) +#endif + +#ifndef FIU_SMRL_SeatHeatBalance_Req_FIU_SMRL_REQ_CTR_SEATS_Backrest_67_Cushion_100_1 +#define FIU_SMRL_SeatHeatBalance_Req_FIU_SMRL_REQ_CTR_SEATS_Backrest_67_Cushion_100_1 (3) +#endif + +#ifndef FIU_SMRL_SeatHeatBalance_Req_FIU_SMRL_REQ_CTR_SEATS_Backrest_33_Cushion_100_2 +#define FIU_SMRL_SeatHeatBalance_Req_FIU_SMRL_REQ_CTR_SEATS_Backrest_33_Cushion_100_2 (2) +#endif + +#ifndef FIU_SMRL_SeatHeatBalance_Req_FIU_SMRL_REQ_CTR_SEATS_Backrest_00_Cushion_100_3 +#define FIU_SMRL_SeatHeatBalance_Req_FIU_SMRL_REQ_CTR_SEATS_Backrest_00_Cushion_100_3 (1) +#endif + +#ifndef FIU_SMRL_SeatHeatBalance_Req_FIU_SMRL_REQ_CTR_SEATS_No_action +#define FIU_SMRL_SeatHeatBalance_Req_FIU_SMRL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRL_SeatMassageType_Req signal + +#ifndef FIU_SMRL_SeatMassageType_Req_FIU_SMRL_REQ_CTR_SEATS_Type_7_Velvet +#define FIU_SMRL_SeatMassageType_Req_FIU_SMRL_REQ_CTR_SEATS_Type_7_Velvet (7) +#endif + +#ifndef FIU_SMRL_SeatMassageType_Req_FIU_SMRL_REQ_CTR_SEATS_Type_6_Sonnet +#define FIU_SMRL_SeatMassageType_Req_FIU_SMRL_REQ_CTR_SEATS_Type_6_Sonnet (6) +#endif + +#ifndef FIU_SMRL_SeatMassageType_Req_FIU_SMRL_REQ_CTR_SEATS_Type_5_Quantum +#define FIU_SMRL_SeatMassageType_Req_FIU_SMRL_REQ_CTR_SEATS_Type_5_Quantum (5) +#endif + +#ifndef FIU_SMRL_SeatMassageType_Req_FIU_SMRL_REQ_CTR_SEATS_Type_4_Cashmere +#define FIU_SMRL_SeatMassageType_Req_FIU_SMRL_REQ_CTR_SEATS_Type_4_Cashmere (4) +#endif + +#ifndef FIU_SMRL_SeatMassageType_Req_FIU_SMRL_REQ_CTR_SEATS_Type_3_Harmony +#define FIU_SMRL_SeatMassageType_Req_FIU_SMRL_REQ_CTR_SEATS_Type_3_Harmony (3) +#endif + +#ifndef FIU_SMRL_SeatMassageType_Req_FIU_SMRL_REQ_CTR_SEATS_Type_2_Orbital +#define FIU_SMRL_SeatMassageType_Req_FIU_SMRL_REQ_CTR_SEATS_Type_2_Orbital (2) +#endif + +#ifndef FIU_SMRL_SeatMassageType_Req_FIU_SMRL_REQ_CTR_SEATS_Type_1_Insight +#define FIU_SMRL_SeatMassageType_Req_FIU_SMRL_REQ_CTR_SEATS_Type_1_Insight (1) +#endif + +#ifndef FIU_SMRL_SeatMassageType_Req_FIU_SMRL_REQ_CTR_SEATS_No_action +#define FIU_SMRL_SeatMassageType_Req_FIU_SMRL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRL_BackrestMassageType_Req signal + +#ifndef FIU_SMRL_BackrestMassageType_Req_FIU_SMRL_REQ_CTR_SEATS_Reserved +#define FIU_SMRL_BackrestMassageType_Req_FIU_SMRL_REQ_CTR_SEATS_Reserved (7) +#endif + +#ifndef FIU_SMRL_BackrestMassageType_Req_FIU_SMRL_REQ_CTR_SEATS_Reserved +#define FIU_SMRL_BackrestMassageType_Req_FIU_SMRL_REQ_CTR_SEATS_Reserved (6) +#endif + +#ifndef FIU_SMRL_BackrestMassageType_Req_FIU_SMRL_REQ_CTR_SEATS_Type_5_Elegy +#define FIU_SMRL_BackrestMassageType_Req_FIU_SMRL_REQ_CTR_SEATS_Type_5_Elegy (5) +#endif + +#ifndef FIU_SMRL_BackrestMassageType_Req_FIU_SMRL_REQ_CTR_SEATS_Type_4_Caprice +#define FIU_SMRL_BackrestMassageType_Req_FIU_SMRL_REQ_CTR_SEATS_Type_4_Caprice (4) +#endif + +#ifndef FIU_SMRL_BackrestMassageType_Req_FIU_SMRL_REQ_CTR_SEATS_Type_3_Pulse +#define FIU_SMRL_BackrestMassageType_Req_FIU_SMRL_REQ_CTR_SEATS_Type_3_Pulse (3) +#endif + +#ifndef FIU_SMRL_BackrestMassageType_Req_FIU_SMRL_REQ_CTR_SEATS_Type_2_Energy +#define FIU_SMRL_BackrestMassageType_Req_FIU_SMRL_REQ_CTR_SEATS_Type_2_Energy (2) +#endif + +#ifndef FIU_SMRL_BackrestMassageType_Req_FIU_SMRL_REQ_CTR_SEATS_Type_1_Synchrony +#define FIU_SMRL_BackrestMassageType_Req_FIU_SMRL_REQ_CTR_SEATS_Type_1_Synchrony (1) +#endif + +#ifndef FIU_SMRL_BackrestMassageType_Req_FIU_SMRL_REQ_CTR_SEATS_No_action +#define FIU_SMRL_BackrestMassageType_Req_FIU_SMRL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRL_ComfortMode_Req signal + +#ifndef FIU_SMRL_ComfortMode_Req_FIU_SMRL_REQ_CTR_SEATS_Active +#define FIU_SMRL_ComfortMode_Req_FIU_SMRL_REQ_CTR_SEATS_Active (1) +#endif + +#ifndef FIU_SMRL_ComfortMode_Req_FIU_SMRL_REQ_CTR_SEATS_Inactive +#define FIU_SMRL_ComfortMode_Req_FIU_SMRL_REQ_CTR_SEATS_Inactive (0) +#endif + + +// Value tables for @FIU_SMRL_ComfortScenario_Req signal + +#ifndef FIU_SMRL_ComfortScenario_Req_FIU_SMRL_REQ_CTR_SEATS_Type_3 +#define FIU_SMRL_ComfortScenario_Req_FIU_SMRL_REQ_CTR_SEATS_Type_3 (3) +#endif + +#ifndef FIU_SMRL_ComfortScenario_Req_FIU_SMRL_REQ_CTR_SEATS_Type_2 +#define FIU_SMRL_ComfortScenario_Req_FIU_SMRL_REQ_CTR_SEATS_Type_2 (2) +#endif + +#ifndef FIU_SMRL_ComfortScenario_Req_FIU_SMRL_REQ_CTR_SEATS_Type_1 +#define FIU_SMRL_ComfortScenario_Req_FIU_SMRL_REQ_CTR_SEATS_Type_1 (1) +#endif + +#ifndef FIU_SMRL_ComfortScenario_Req_FIU_SMRL_REQ_CTR_SEATS_No_action +#define FIU_SMRL_ComfortScenario_Req_FIU_SMRL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRL_CarpetHeat_Req signal + +#ifndef FIU_SMRL_CarpetHeat_Req_FIU_SMRL_REQ_CTR_SEATS_Active +#define FIU_SMRL_CarpetHeat_Req_FIU_SMRL_REQ_CTR_SEATS_Active (1) +#endif + +#ifndef FIU_SMRL_CarpetHeat_Req_FIU_SMRL_REQ_CTR_SEATS_Inactive +#define FIU_SMRL_CarpetHeat_Req_FIU_SMRL_REQ_CTR_SEATS_Inactive (0) +#endif + + +// Value tables for @FIU_SMRL_TimerMassage_Req signal + +#ifndef FIU_SMRL_TimerMassage_Req_FIU_SMRL_REQ_CTR_SEATS_Reserved +#define FIU_SMRL_TimerMassage_Req_FIU_SMRL_REQ_CTR_SEATS_Reserved (7) +#endif + +#ifndef FIU_SMRL_TimerMassage_Req_FIU_SMRL_REQ_CTR_SEATS__min +#define FIU_SMRL_TimerMassage_Req_FIU_SMRL_REQ_CTR_SEATS__min (6) +#endif + +#ifndef FIU_SMRL_TimerMassage_Req_FIU_SMRL_REQ_CTR_SEATS__min +#define FIU_SMRL_TimerMassage_Req_FIU_SMRL_REQ_CTR_SEATS__min (5) +#endif + +#ifndef FIU_SMRL_TimerMassage_Req_FIU_SMRL_REQ_CTR_SEATS__min +#define FIU_SMRL_TimerMassage_Req_FIU_SMRL_REQ_CTR_SEATS__min (4) +#endif + +#ifndef FIU_SMRL_TimerMassage_Req_FIU_SMRL_REQ_CTR_SEATS__min +#define FIU_SMRL_TimerMassage_Req_FIU_SMRL_REQ_CTR_SEATS__min (3) +#endif + +#ifndef FIU_SMRL_TimerMassage_Req_FIU_SMRL_REQ_CTR_SEATS__min +#define FIU_SMRL_TimerMassage_Req_FIU_SMRL_REQ_CTR_SEATS__min (2) +#endif + +#ifndef FIU_SMRL_TimerMassage_Req_FIU_SMRL_REQ_CTR_SEATS__min +#define FIU_SMRL_TimerMassage_Req_FIU_SMRL_REQ_CTR_SEATS__min (1) +#endif + +#ifndef FIU_SMRL_TimerMassage_Req_FIU_SMRL_REQ_CTR_SEATS_No_action +#define FIU_SMRL_TimerMassage_Req_FIU_SMRL_REQ_CTR_SEATS_No_action (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Signal for regulation Seat Height RL + // (RL seat base height regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRL_SeatHeight_Req : 2; // Bits= 2 + + // Signal for regulation RL head rest height + // (RL headrest height regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRL_HeadRestHeight_Req : 2; // Bits= 2 + + // Signal for regulation RL seat longitudinal + // (RL seat base longitudinal regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRL_SeatLongitudinal_Req : 2; // Bits= 2 + + // Signal for regulation RL seat inclination + // (RL headrest depth regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRL_SeatHeadRestInclin_Req : 2; // Bits= 2 + + // Signal for regulation RL seat surface longitudinal + // (RL seat pillow longitudinal regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRL_SeatSurfaceLong_Req : 2; // Bits= 2 + + // Signal for regulation RL seat leg support height + // (RL seat leg support height regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRL_SeatLegSupportH_Req : 2; // Bits= 2 + + // Signal for regulation RL seat leg support longitudinal + // (RL seat leg support longitudinal regulation request, RESERVE) + // 3 : "Resertved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRL_SeatLegSupportLong_Req : 2; // Bits= 2 + + // Signal for regulation RL seat inclination + // (RL seat pillow inclination regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRL_SeatInclination_Req : 2; // Bits= 2 + + // Signal for regulation RL seat backrest lnclination + // (RL backrest angle regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRL_SeatBackRestInc_Req : 2; // Bits= 2 + + // Signal for regulation RL seat lumbar support height + // (RL backrest lumbar support height regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRL_SeatLumbarSupportH_Req : 2; // Bits= 2 + + // Signal for regulation RL seat backrest head inclination + // (RL backrest should support regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRL_SeatBackRestHeadInc_Req : 2; // Bits= 2 + + // Signal for regulation RL seat lumbar support depth + // (RL backrest lumbar support depth regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRL_SeatLumbarSupDepth_Req : 2; // Bits= 2 + + // Signal for regulation RL seat backrest width + // (RL backrest lateral support regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRL_BackRestWidth_Req : 2; // Bits= 2 + + // Signal for regulation RL seat cushion support + // (RL seat cushion side lateral support regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRL_SeatCushionSupport_Req : 2; // Bits= 2 + + // Signal for seat massage activation + // (RL seat massage request) + // 3 : "Reserved" + // 2 : "Massage ON" + // 1 : "Massage OFF" + // 0 : "No action" + uint8_t FIU_SMRL_SeatMassage_Req : 2; // Bits= 2 + + // Signal for ventilation activation mode + // (RL seat ventilation request) + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "Off" + uint8_t FIU_SMRL_SeatVentilation_Req : 2; // Bits= 2 + + // Signal for ventilation balance mode + // (RL seat ventilation balance request) + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 00%, Cushion 100%: -3" + // 0 : "No action" + uint8_t FIU_SMRL_SeatVentBalance_Req : 3; // Bits= 3 + + // Signal for seat massage intencity regulation + // (RL seat massage intencity request) + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "No action" + uint8_t FIU_SMRL_SeatMassageIntence_Req : 2; // Bits= 2 + + // Signal for seat heating activation mode + // (RL seat heating request) + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "Off" + uint8_t FIU_SMRL_SeatHeating_Req : 2; // Bits= 2 + + // RR active lateral support request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_SMRL_ActiveSupport_Req : 1; // Bits= 1 + + // Signal for seat heating balance + // (RL seat heating balance request) + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 00%, Cushion 100%: -3" + // 0 : "No action" + uint8_t FIU_SMRL_SeatHeatBalance_Req : 3; // Bits= 3 + + // Signal for seat massage type (mode) + // (RL seat massage type request) + // 7 : "Type 7 (Velvet)" + // 6 : "Type 6 (Sonnet)" + // 5 : "Type 5 (Quantum)" + // 4 : "Type 4 (Cashmere)" + // 3 : "Type 3 (Harmony)" + // 2 : "Type 2 (Orbital)" + // 1 : "Type 1 (Insight)" + // 0 : "No action" + uint8_t FIU_SMRL_SeatMassageType_Req : 3; // Bits= 3 + + // Signal for backrest massage type (mode) + // (RL backrest massage type request) + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Type 5 (Elegy)" + // 4 : "Type 4 (Caprice)" + // 3 : "Type 3 (Pulse)" + // 2 : "Type 2 (Energy)" + // 1 : "Type 1 (Synchrony)" + // 0 : "No action" + uint8_t FIU_SMRL_BackrestMassageType_Req : 3; // Bits= 3 + + // RL comfort mode command + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_SMRL_ComfortMode_Req : 1; // Bits= 1 + + // RL comfort mode scenario command + // 3 : "Type 3" + // 2 : "Type 2" + // 1 : "Type 1" + // 0 : "No action" + uint8_t FIU_SMRL_ComfortScenario_Req : 2; // Bits= 2 + + // RR carpet heating command + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_SMRL_CarpetHeat_Req : 1; // Bits= 1 + + // Signal for setting the massage timer + // 7 : "Reserved" + // 6 : "30 min" + // 5 : "25 min" + // 4 : "20 min" + // 3 : "15 min" + // 2 : "10 min" + // 1 : "5 min" + // 0 : "No action" + uint8_t FIU_SMRL_TimerMassage_Req : 3; // Bits= 3 + +#else + + // Signal for regulation Seat Height RL + // (RL seat base height regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRL_SeatHeight_Req; // Bits= 2 + + // Signal for regulation RL head rest height + // (RL headrest height regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRL_HeadRestHeight_Req; // Bits= 2 + + // Signal for regulation RL seat longitudinal + // (RL seat base longitudinal regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRL_SeatLongitudinal_Req; // Bits= 2 + + // Signal for regulation RL seat inclination + // (RL headrest depth regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRL_SeatHeadRestInclin_Req; // Bits= 2 + + // Signal for regulation RL seat surface longitudinal + // (RL seat pillow longitudinal regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRL_SeatSurfaceLong_Req; // Bits= 2 + + // Signal for regulation RL seat leg support height + // (RL seat leg support height regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRL_SeatLegSupportH_Req; // Bits= 2 + + // Signal for regulation RL seat leg support longitudinal + // (RL seat leg support longitudinal regulation request, RESERVE) + // 3 : "Resertved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRL_SeatLegSupportLong_Req; // Bits= 2 + + // Signal for regulation RL seat inclination + // (RL seat pillow inclination regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRL_SeatInclination_Req; // Bits= 2 + + // Signal for regulation RL seat backrest lnclination + // (RL backrest angle regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRL_SeatBackRestInc_Req; // Bits= 2 + + // Signal for regulation RL seat lumbar support height + // (RL backrest lumbar support height regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRL_SeatLumbarSupportH_Req; // Bits= 2 + + // Signal for regulation RL seat backrest head inclination + // (RL backrest should support regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRL_SeatBackRestHeadInc_Req; // Bits= 2 + + // Signal for regulation RL seat lumbar support depth + // (RL backrest lumbar support depth regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRL_SeatLumbarSupDepth_Req; // Bits= 2 + + // Signal for regulation RL seat backrest width + // (RL backrest lateral support regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRL_BackRestWidth_Req; // Bits= 2 + + // Signal for regulation RL seat cushion support + // (RL seat cushion side lateral support regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRL_SeatCushionSupport_Req; // Bits= 2 + + // Signal for seat massage activation + // (RL seat massage request) + // 3 : "Reserved" + // 2 : "Massage ON" + // 1 : "Massage OFF" + // 0 : "No action" + uint8_t FIU_SMRL_SeatMassage_Req; // Bits= 2 + + // Signal for ventilation activation mode + // (RL seat ventilation request) + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "Off" + uint8_t FIU_SMRL_SeatVentilation_Req; // Bits= 2 + + // Signal for ventilation balance mode + // (RL seat ventilation balance request) + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 00%, Cushion 100%: -3" + // 0 : "No action" + uint8_t FIU_SMRL_SeatVentBalance_Req; // Bits= 3 + + // Signal for seat massage intencity regulation + // (RL seat massage intencity request) + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "No action" + uint8_t FIU_SMRL_SeatMassageIntence_Req; // Bits= 2 + + // Signal for seat heating activation mode + // (RL seat heating request) + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "Off" + uint8_t FIU_SMRL_SeatHeating_Req; // Bits= 2 + + // RR active lateral support request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_SMRL_ActiveSupport_Req; // Bits= 1 + + // Signal for seat heating balance + // (RL seat heating balance request) + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 00%, Cushion 100%: -3" + // 0 : "No action" + uint8_t FIU_SMRL_SeatHeatBalance_Req; // Bits= 3 + + // Signal for seat massage type (mode) + // (RL seat massage type request) + // 7 : "Type 7 (Velvet)" + // 6 : "Type 6 (Sonnet)" + // 5 : "Type 5 (Quantum)" + // 4 : "Type 4 (Cashmere)" + // 3 : "Type 3 (Harmony)" + // 2 : "Type 2 (Orbital)" + // 1 : "Type 1 (Insight)" + // 0 : "No action" + uint8_t FIU_SMRL_SeatMassageType_Req; // Bits= 3 + + // Signal for backrest massage type (mode) + // (RL backrest massage type request) + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Type 5 (Elegy)" + // 4 : "Type 4 (Caprice)" + // 3 : "Type 3 (Pulse)" + // 2 : "Type 2 (Energy)" + // 1 : "Type 1 (Synchrony)" + // 0 : "No action" + uint8_t FIU_SMRL_BackrestMassageType_Req; // Bits= 3 + + // RL comfort mode command + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_SMRL_ComfortMode_Req; // Bits= 1 + + // RL comfort mode scenario command + // 3 : "Type 3" + // 2 : "Type 2" + // 1 : "Type 1" + // 0 : "No action" + uint8_t FIU_SMRL_ComfortScenario_Req; // Bits= 2 + + // RR carpet heating command + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_SMRL_CarpetHeat_Req; // Bits= 1 + + // Signal for setting the massage timer + // 7 : "Reserved" + // 6 : "30 min" + // 5 : "25 min" + // 4 : "20 min" + // 3 : "15 min" + // 2 : "10 min" + // 1 : "5 min" + // 0 : "No action" + uint8_t FIU_SMRL_TimerMassage_Req; // Bits= 3 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} FIU_SMRL_REQ_CTR_SEATS_t; + +// def @FIU_SMFR_REQ_CTR_SEATS CAN Message (1325 0x52d) +#define FIU_SMFR_REQ_CTR_SEATS_IDE (0U) +#define FIU_SMFR_REQ_CTR_SEATS_DLC (7U) +#define FIU_SMFR_REQ_CTR_SEATS_CANID (0x52dU) + +// Value tables for @FIU_SMFR_SeatHeight_Req signal + +#ifndef FIU_SMFR_SeatHeight_Req_FIU_SMFR_REQ_CTR_SEATS_Reserved +#define FIU_SMFR_SeatHeight_Req_FIU_SMFR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMFR_SeatHeight_Req_FIU_SMFR_REQ_CTR_SEATS_Decrease +#define FIU_SMFR_SeatHeight_Req_FIU_SMFR_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMFR_SeatHeight_Req_FIU_SMFR_REQ_CTR_SEATS_Increase +#define FIU_SMFR_SeatHeight_Req_FIU_SMFR_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMFR_SeatHeight_Req_FIU_SMFR_REQ_CTR_SEATS_No_action +#define FIU_SMFR_SeatHeight_Req_FIU_SMFR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFR_HeadRest_Height_Req signal + +#ifndef FIU_SMFR_HeadRest_Height_Req_FIU_SMFR_REQ_CTR_SEATS_Reserved +#define FIU_SMFR_HeadRest_Height_Req_FIU_SMFR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMFR_HeadRest_Height_Req_FIU_SMFR_REQ_CTR_SEATS_Decrease +#define FIU_SMFR_HeadRest_Height_Req_FIU_SMFR_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMFR_HeadRest_Height_Req_FIU_SMFR_REQ_CTR_SEATS_Increase +#define FIU_SMFR_HeadRest_Height_Req_FIU_SMFR_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMFR_HeadRest_Height_Req_FIU_SMFR_REQ_CTR_SEATS_No_action +#define FIU_SMFR_HeadRest_Height_Req_FIU_SMFR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFR_SeatLongitunalReq signal + +#ifndef FIU_SMFR_SeatLongitunalReq_FIU_SMFR_REQ_CTR_SEATS_Reserved +#define FIU_SMFR_SeatLongitunalReq_FIU_SMFR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMFR_SeatLongitunalReq_FIU_SMFR_REQ_CTR_SEATS_Decrease +#define FIU_SMFR_SeatLongitunalReq_FIU_SMFR_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMFR_SeatLongitunalReq_FIU_SMFR_REQ_CTR_SEATS_Increase +#define FIU_SMFR_SeatLongitunalReq_FIU_SMFR_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMFR_SeatLongitunalReq_FIU_SMFR_REQ_CTR_SEATS_No_action +#define FIU_SMFR_SeatLongitunalReq_FIU_SMFR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFR_SeatHeadRestInclin_Req signal + +#ifndef FIU_SMFR_SeatHeadRestInclin_Req_FIU_SMFR_REQ_CTR_SEATS_Reserved +#define FIU_SMFR_SeatHeadRestInclin_Req_FIU_SMFR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMFR_SeatHeadRestInclin_Req_FIU_SMFR_REQ_CTR_SEATS_Decrease +#define FIU_SMFR_SeatHeadRestInclin_Req_FIU_SMFR_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMFR_SeatHeadRestInclin_Req_FIU_SMFR_REQ_CTR_SEATS_Increase +#define FIU_SMFR_SeatHeadRestInclin_Req_FIU_SMFR_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMFR_SeatHeadRestInclin_Req_FIU_SMFR_REQ_CTR_SEATS_No_action +#define FIU_SMFR_SeatHeadRestInclin_Req_FIU_SMFR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFR_SeatSurfaceLong_Req signal + +#ifndef FIU_SMFR_SeatSurfaceLong_Req_FIU_SMFR_REQ_CTR_SEATS_Reserved +#define FIU_SMFR_SeatSurfaceLong_Req_FIU_SMFR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMFR_SeatSurfaceLong_Req_FIU_SMFR_REQ_CTR_SEATS_Decrease +#define FIU_SMFR_SeatSurfaceLong_Req_FIU_SMFR_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMFR_SeatSurfaceLong_Req_FIU_SMFR_REQ_CTR_SEATS_Increase +#define FIU_SMFR_SeatSurfaceLong_Req_FIU_SMFR_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMFR_SeatSurfaceLong_Req_FIU_SMFR_REQ_CTR_SEATS_No_action +#define FIU_SMFR_SeatSurfaceLong_Req_FIU_SMFR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFR_SeatLegSupportH_Req signal + +#ifndef FIU_SMFR_SeatLegSupportH_Req_FIU_SMFR_REQ_CTR_SEATS_Reserved +#define FIU_SMFR_SeatLegSupportH_Req_FIU_SMFR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMFR_SeatLegSupportH_Req_FIU_SMFR_REQ_CTR_SEATS_Decrease +#define FIU_SMFR_SeatLegSupportH_Req_FIU_SMFR_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMFR_SeatLegSupportH_Req_FIU_SMFR_REQ_CTR_SEATS_Increase +#define FIU_SMFR_SeatLegSupportH_Req_FIU_SMFR_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMFR_SeatLegSupportH_Req_FIU_SMFR_REQ_CTR_SEATS_No_action +#define FIU_SMFR_SeatLegSupportH_Req_FIU_SMFR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFR_SeatLegSupportLong_Req signal + +#ifndef FIU_SMFR_SeatLegSupportLong_Req_FIU_SMFR_REQ_CTR_SEATS_Resertved +#define FIU_SMFR_SeatLegSupportLong_Req_FIU_SMFR_REQ_CTR_SEATS_Resertved (3) +#endif + +#ifndef FIU_SMFR_SeatLegSupportLong_Req_FIU_SMFR_REQ_CTR_SEATS_Decrease +#define FIU_SMFR_SeatLegSupportLong_Req_FIU_SMFR_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMFR_SeatLegSupportLong_Req_FIU_SMFR_REQ_CTR_SEATS_Increase +#define FIU_SMFR_SeatLegSupportLong_Req_FIU_SMFR_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMFR_SeatLegSupportLong_Req_FIU_SMFR_REQ_CTR_SEATS_No_action +#define FIU_SMFR_SeatLegSupportLong_Req_FIU_SMFR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFR_SeatInclination_Req signal + +#ifndef FIU_SMFR_SeatInclination_Req_FIU_SMFR_REQ_CTR_SEATS_Reserved +#define FIU_SMFR_SeatInclination_Req_FIU_SMFR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMFR_SeatInclination_Req_FIU_SMFR_REQ_CTR_SEATS_Decrease +#define FIU_SMFR_SeatInclination_Req_FIU_SMFR_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMFR_SeatInclination_Req_FIU_SMFR_REQ_CTR_SEATS_Increase +#define FIU_SMFR_SeatInclination_Req_FIU_SMFR_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMFR_SeatInclination_Req_FIU_SMFR_REQ_CTR_SEATS_No_action +#define FIU_SMFR_SeatInclination_Req_FIU_SMFR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFR_SeatBackRestInc_Req signal + +#ifndef FIU_SMFR_SeatBackRestInc_Req_FIU_SMFR_REQ_CTR_SEATS_Reserved +#define FIU_SMFR_SeatBackRestInc_Req_FIU_SMFR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMFR_SeatBackRestInc_Req_FIU_SMFR_REQ_CTR_SEATS_Decrease +#define FIU_SMFR_SeatBackRestInc_Req_FIU_SMFR_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMFR_SeatBackRestInc_Req_FIU_SMFR_REQ_CTR_SEATS_Increase +#define FIU_SMFR_SeatBackRestInc_Req_FIU_SMFR_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMFR_SeatBackRestInc_Req_FIU_SMFR_REQ_CTR_SEATS_No_action +#define FIU_SMFR_SeatBackRestInc_Req_FIU_SMFR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFR_SeatLumbarSupHeight_Req signal + +#ifndef FIU_SMFR_SeatLumbarSupHeight_Req_FIU_SMFR_REQ_CTR_SEATS_Reserved +#define FIU_SMFR_SeatLumbarSupHeight_Req_FIU_SMFR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMFR_SeatLumbarSupHeight_Req_FIU_SMFR_REQ_CTR_SEATS_Decrease +#define FIU_SMFR_SeatLumbarSupHeight_Req_FIU_SMFR_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMFR_SeatLumbarSupHeight_Req_FIU_SMFR_REQ_CTR_SEATS_Increase +#define FIU_SMFR_SeatLumbarSupHeight_Req_FIU_SMFR_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMFR_SeatLumbarSupHeight_Req_FIU_SMFR_REQ_CTR_SEATS_No_action +#define FIU_SMFR_SeatLumbarSupHeight_Req_FIU_SMFR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFR_SeatBackRestHeadInc_Req signal + +#ifndef FIU_SMFR_SeatBackRestHeadInc_Req_FIU_SMFR_REQ_CTR_SEATS_Reserved +#define FIU_SMFR_SeatBackRestHeadInc_Req_FIU_SMFR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMFR_SeatBackRestHeadInc_Req_FIU_SMFR_REQ_CTR_SEATS_Decrease +#define FIU_SMFR_SeatBackRestHeadInc_Req_FIU_SMFR_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMFR_SeatBackRestHeadInc_Req_FIU_SMFR_REQ_CTR_SEATS_Increase +#define FIU_SMFR_SeatBackRestHeadInc_Req_FIU_SMFR_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMFR_SeatBackRestHeadInc_Req_FIU_SMFR_REQ_CTR_SEATS_No_action +#define FIU_SMFR_SeatBackRestHeadInc_Req_FIU_SMFR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFR_SeatLumbarSupDepth_Req signal + +#ifndef FIU_SMFR_SeatLumbarSupDepth_Req_FIU_SMFR_REQ_CTR_SEATS_Reserved +#define FIU_SMFR_SeatLumbarSupDepth_Req_FIU_SMFR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMFR_SeatLumbarSupDepth_Req_FIU_SMFR_REQ_CTR_SEATS_Decrease +#define FIU_SMFR_SeatLumbarSupDepth_Req_FIU_SMFR_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMFR_SeatLumbarSupDepth_Req_FIU_SMFR_REQ_CTR_SEATS_Increase +#define FIU_SMFR_SeatLumbarSupDepth_Req_FIU_SMFR_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMFR_SeatLumbarSupDepth_Req_FIU_SMFR_REQ_CTR_SEATS_No_action +#define FIU_SMFR_SeatLumbarSupDepth_Req_FIU_SMFR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFR_BackRestWidth_Req signal + +#ifndef FIU_SMFR_BackRestWidth_Req_FIU_SMFR_REQ_CTR_SEATS_Reserved +#define FIU_SMFR_BackRestWidth_Req_FIU_SMFR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMFR_BackRestWidth_Req_FIU_SMFR_REQ_CTR_SEATS_Decrease +#define FIU_SMFR_BackRestWidth_Req_FIU_SMFR_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMFR_BackRestWidth_Req_FIU_SMFR_REQ_CTR_SEATS_Increase +#define FIU_SMFR_BackRestWidth_Req_FIU_SMFR_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMFR_BackRestWidth_Req_FIU_SMFR_REQ_CTR_SEATS_No_action +#define FIU_SMFR_BackRestWidth_Req_FIU_SMFR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFR_SeatCushionSupport_Req signal + +#ifndef FIU_SMFR_SeatCushionSupport_Req_FIU_SMFR_REQ_CTR_SEATS_Reserved +#define FIU_SMFR_SeatCushionSupport_Req_FIU_SMFR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMFR_SeatCushionSupport_Req_FIU_SMFR_REQ_CTR_SEATS_Decrease +#define FIU_SMFR_SeatCushionSupport_Req_FIU_SMFR_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMFR_SeatCushionSupport_Req_FIU_SMFR_REQ_CTR_SEATS_Increase +#define FIU_SMFR_SeatCushionSupport_Req_FIU_SMFR_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMFR_SeatCushionSupport_Req_FIU_SMFR_REQ_CTR_SEATS_No_action +#define FIU_SMFR_SeatCushionSupport_Req_FIU_SMFR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFR_SeatMassage_Req signal + +#ifndef FIU_SMFR_SeatMassage_Req_FIU_SMFR_REQ_CTR_SEATS_Reserved +#define FIU_SMFR_SeatMassage_Req_FIU_SMFR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMFR_SeatMassage_Req_FIU_SMFR_REQ_CTR_SEATS_Massage_ON +#define FIU_SMFR_SeatMassage_Req_FIU_SMFR_REQ_CTR_SEATS_Massage_ON (2) +#endif + +#ifndef FIU_SMFR_SeatMassage_Req_FIU_SMFR_REQ_CTR_SEATS_Massage_OFF +#define FIU_SMFR_SeatMassage_Req_FIU_SMFR_REQ_CTR_SEATS_Massage_OFF (1) +#endif + +#ifndef FIU_SMFR_SeatMassage_Req_FIU_SMFR_REQ_CTR_SEATS_No_action +#define FIU_SMFR_SeatMassage_Req_FIU_SMFR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFR_SeatVentilation_Req signal + +#ifndef FIU_SMFR_SeatVentilation_Req_FIU_SMFR_REQ_CTR_SEATS_High_power +#define FIU_SMFR_SeatVentilation_Req_FIU_SMFR_REQ_CTR_SEATS_High_power (3) +#endif + +#ifndef FIU_SMFR_SeatVentilation_Req_FIU_SMFR_REQ_CTR_SEATS_Middle_power +#define FIU_SMFR_SeatVentilation_Req_FIU_SMFR_REQ_CTR_SEATS_Middle_power (2) +#endif + +#ifndef FIU_SMFR_SeatVentilation_Req_FIU_SMFR_REQ_CTR_SEATS_Low_power +#define FIU_SMFR_SeatVentilation_Req_FIU_SMFR_REQ_CTR_SEATS_Low_power (1) +#endif + +#ifndef FIU_SMFR_SeatVentilation_Req_FIU_SMFR_REQ_CTR_SEATS_Off +#define FIU_SMFR_SeatVentilation_Req_FIU_SMFR_REQ_CTR_SEATS_Off (0) +#endif + + +// Value tables for @FIU_SMFR_SeatVentBalance_Req signal + +#ifndef FIU_SMFR_SeatVentBalance_Req_FIU_SMFR_REQ_CTR_SEATS_Backrest_100_Cushion_00_3 +#define FIU_SMFR_SeatVentBalance_Req_FIU_SMFR_REQ_CTR_SEATS_Backrest_100_Cushion_00_3 (7) +#endif + +#ifndef FIU_SMFR_SeatVentBalance_Req_FIU_SMFR_REQ_CTR_SEATS_Backrest_100_Cushion_33_2 +#define FIU_SMFR_SeatVentBalance_Req_FIU_SMFR_REQ_CTR_SEATS_Backrest_100_Cushion_33_2 (6) +#endif + +#ifndef FIU_SMFR_SeatVentBalance_Req_FIU_SMFR_REQ_CTR_SEATS_Backrest_100_Cushion_67_1 +#define FIU_SMFR_SeatVentBalance_Req_FIU_SMFR_REQ_CTR_SEATS_Backrest_100_Cushion_67_1 (5) +#endif + +#ifndef FIU_SMFR_SeatVentBalance_Req_FIU_SMFR_REQ_CTR_SEATS_Backrest_100_Cushion_100_0 +#define FIU_SMFR_SeatVentBalance_Req_FIU_SMFR_REQ_CTR_SEATS_Backrest_100_Cushion_100_0 (4) +#endif + +#ifndef FIU_SMFR_SeatVentBalance_Req_FIU_SMFR_REQ_CTR_SEATS_Backrest_67_Cushion_100_1 +#define FIU_SMFR_SeatVentBalance_Req_FIU_SMFR_REQ_CTR_SEATS_Backrest_67_Cushion_100_1 (3) +#endif + +#ifndef FIU_SMFR_SeatVentBalance_Req_FIU_SMFR_REQ_CTR_SEATS_Backrest_33_Cushion_100_2 +#define FIU_SMFR_SeatVentBalance_Req_FIU_SMFR_REQ_CTR_SEATS_Backrest_33_Cushion_100_2 (2) +#endif + +#ifndef FIU_SMFR_SeatVentBalance_Req_FIU_SMFR_REQ_CTR_SEATS_Backrest_00_Cushion_100_3 +#define FIU_SMFR_SeatVentBalance_Req_FIU_SMFR_REQ_CTR_SEATS_Backrest_00_Cushion_100_3 (1) +#endif + +#ifndef FIU_SMFR_SeatVentBalance_Req_FIU_SMFR_REQ_CTR_SEATS_No_action +#define FIU_SMFR_SeatVentBalance_Req_FIU_SMFR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFR_SeatMassageIntence_Req signal + +#ifndef FIU_SMFR_SeatMassageIntence_Req_FIU_SMFR_REQ_CTR_SEATS_High_power +#define FIU_SMFR_SeatMassageIntence_Req_FIU_SMFR_REQ_CTR_SEATS_High_power (3) +#endif + +#ifndef FIU_SMFR_SeatMassageIntence_Req_FIU_SMFR_REQ_CTR_SEATS_Middle_power +#define FIU_SMFR_SeatMassageIntence_Req_FIU_SMFR_REQ_CTR_SEATS_Middle_power (2) +#endif + +#ifndef FIU_SMFR_SeatMassageIntence_Req_FIU_SMFR_REQ_CTR_SEATS_Low_power +#define FIU_SMFR_SeatMassageIntence_Req_FIU_SMFR_REQ_CTR_SEATS_Low_power (1) +#endif + +#ifndef FIU_SMFR_SeatMassageIntence_Req_FIU_SMFR_REQ_CTR_SEATS_No_action +#define FIU_SMFR_SeatMassageIntence_Req_FIU_SMFR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFR_SeatHeating_Req signal + +#ifndef FIU_SMFR_SeatHeating_Req_FIU_SMFR_REQ_CTR_SEATS_High_power +#define FIU_SMFR_SeatHeating_Req_FIU_SMFR_REQ_CTR_SEATS_High_power (3) +#endif + +#ifndef FIU_SMFR_SeatHeating_Req_FIU_SMFR_REQ_CTR_SEATS_Normal_power +#define FIU_SMFR_SeatHeating_Req_FIU_SMFR_REQ_CTR_SEATS_Normal_power (2) +#endif + +#ifndef FIU_SMFR_SeatHeating_Req_FIU_SMFR_REQ_CTR_SEATS_Low_power +#define FIU_SMFR_SeatHeating_Req_FIU_SMFR_REQ_CTR_SEATS_Low_power (1) +#endif + +#ifndef FIU_SMFR_SeatHeating_Req_FIU_SMFR_REQ_CTR_SEATS_Off +#define FIU_SMFR_SeatHeating_Req_FIU_SMFR_REQ_CTR_SEATS_Off (0) +#endif + + +// Value tables for @FIU_SMFR_ActiveSupport_Req signal + +#ifndef FIU_SMFR_ActiveSupport_Req_FIU_SMFR_REQ_CTR_SEATS_Active +#define FIU_SMFR_ActiveSupport_Req_FIU_SMFR_REQ_CTR_SEATS_Active (1) +#endif + +#ifndef FIU_SMFR_ActiveSupport_Req_FIU_SMFR_REQ_CTR_SEATS_Inactive +#define FIU_SMFR_ActiveSupport_Req_FIU_SMFR_REQ_CTR_SEATS_Inactive (0) +#endif + + +// Value tables for @FIU_SMFR_SeatHeatBalance_Req signal + +#ifndef FIU_SMFR_SeatHeatBalance_Req_FIU_SMFR_REQ_CTR_SEATS_Backrest_100_Cushion_00_3 +#define FIU_SMFR_SeatHeatBalance_Req_FIU_SMFR_REQ_CTR_SEATS_Backrest_100_Cushion_00_3 (7) +#endif + +#ifndef FIU_SMFR_SeatHeatBalance_Req_FIU_SMFR_REQ_CTR_SEATS_Backrest_100_Cushion_33_2 +#define FIU_SMFR_SeatHeatBalance_Req_FIU_SMFR_REQ_CTR_SEATS_Backrest_100_Cushion_33_2 (6) +#endif + +#ifndef FIU_SMFR_SeatHeatBalance_Req_FIU_SMFR_REQ_CTR_SEATS_Backrest_100_Cushion_67_1 +#define FIU_SMFR_SeatHeatBalance_Req_FIU_SMFR_REQ_CTR_SEATS_Backrest_100_Cushion_67_1 (5) +#endif + +#ifndef FIU_SMFR_SeatHeatBalance_Req_FIU_SMFR_REQ_CTR_SEATS_Backrest_100_Cushion_100_0 +#define FIU_SMFR_SeatHeatBalance_Req_FIU_SMFR_REQ_CTR_SEATS_Backrest_100_Cushion_100_0 (4) +#endif + +#ifndef FIU_SMFR_SeatHeatBalance_Req_FIU_SMFR_REQ_CTR_SEATS_Backrest_67_Cushion_100_1 +#define FIU_SMFR_SeatHeatBalance_Req_FIU_SMFR_REQ_CTR_SEATS_Backrest_67_Cushion_100_1 (3) +#endif + +#ifndef FIU_SMFR_SeatHeatBalance_Req_FIU_SMFR_REQ_CTR_SEATS_Backrest_33_Cushion_100_2 +#define FIU_SMFR_SeatHeatBalance_Req_FIU_SMFR_REQ_CTR_SEATS_Backrest_33_Cushion_100_2 (2) +#endif + +#ifndef FIU_SMFR_SeatHeatBalance_Req_FIU_SMFR_REQ_CTR_SEATS_Backrest_00_Cushion_100_3 +#define FIU_SMFR_SeatHeatBalance_Req_FIU_SMFR_REQ_CTR_SEATS_Backrest_00_Cushion_100_3 (1) +#endif + +#ifndef FIU_SMFR_SeatHeatBalance_Req_FIU_SMFR_REQ_CTR_SEATS_No_action +#define FIU_SMFR_SeatHeatBalance_Req_FIU_SMFR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFR_SeatMassageType_Req signal + +#ifndef FIU_SMFR_SeatMassageType_Req_FIU_SMFR_REQ_CTR_SEATS_Type_7_Velvet +#define FIU_SMFR_SeatMassageType_Req_FIU_SMFR_REQ_CTR_SEATS_Type_7_Velvet (7) +#endif + +#ifndef FIU_SMFR_SeatMassageType_Req_FIU_SMFR_REQ_CTR_SEATS_Type_6_Sonnet +#define FIU_SMFR_SeatMassageType_Req_FIU_SMFR_REQ_CTR_SEATS_Type_6_Sonnet (6) +#endif + +#ifndef FIU_SMFR_SeatMassageType_Req_FIU_SMFR_REQ_CTR_SEATS_Type_5_Quantum +#define FIU_SMFR_SeatMassageType_Req_FIU_SMFR_REQ_CTR_SEATS_Type_5_Quantum (5) +#endif + +#ifndef FIU_SMFR_SeatMassageType_Req_FIU_SMFR_REQ_CTR_SEATS_Type_4_Cashmere +#define FIU_SMFR_SeatMassageType_Req_FIU_SMFR_REQ_CTR_SEATS_Type_4_Cashmere (4) +#endif + +#ifndef FIU_SMFR_SeatMassageType_Req_FIU_SMFR_REQ_CTR_SEATS_Type_3_Harmony +#define FIU_SMFR_SeatMassageType_Req_FIU_SMFR_REQ_CTR_SEATS_Type_3_Harmony (3) +#endif + +#ifndef FIU_SMFR_SeatMassageType_Req_FIU_SMFR_REQ_CTR_SEATS_Type_2_Orbital +#define FIU_SMFR_SeatMassageType_Req_FIU_SMFR_REQ_CTR_SEATS_Type_2_Orbital (2) +#endif + +#ifndef FIU_SMFR_SeatMassageType_Req_FIU_SMFR_REQ_CTR_SEATS_Type_1_Insight +#define FIU_SMFR_SeatMassageType_Req_FIU_SMFR_REQ_CTR_SEATS_Type_1_Insight (1) +#endif + +#ifndef FIU_SMFR_SeatMassageType_Req_FIU_SMFR_REQ_CTR_SEATS_No_action +#define FIU_SMFR_SeatMassageType_Req_FIU_SMFR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFR_BackrestMassageType_Req signal + +#ifndef FIU_SMFR_BackrestMassageType_Req_FIU_SMFR_REQ_CTR_SEATS_Reserved +#define FIU_SMFR_BackrestMassageType_Req_FIU_SMFR_REQ_CTR_SEATS_Reserved (7) +#endif + +#ifndef FIU_SMFR_BackrestMassageType_Req_FIU_SMFR_REQ_CTR_SEATS_Reserved +#define FIU_SMFR_BackrestMassageType_Req_FIU_SMFR_REQ_CTR_SEATS_Reserved (6) +#endif + +#ifndef FIU_SMFR_BackrestMassageType_Req_FIU_SMFR_REQ_CTR_SEATS_Type_5_Elegy +#define FIU_SMFR_BackrestMassageType_Req_FIU_SMFR_REQ_CTR_SEATS_Type_5_Elegy (5) +#endif + +#ifndef FIU_SMFR_BackrestMassageType_Req_FIU_SMFR_REQ_CTR_SEATS_Type_4_Caprice +#define FIU_SMFR_BackrestMassageType_Req_FIU_SMFR_REQ_CTR_SEATS_Type_4_Caprice (4) +#endif + +#ifndef FIU_SMFR_BackrestMassageType_Req_FIU_SMFR_REQ_CTR_SEATS_Type_3_Pulse +#define FIU_SMFR_BackrestMassageType_Req_FIU_SMFR_REQ_CTR_SEATS_Type_3_Pulse (3) +#endif + +#ifndef FIU_SMFR_BackrestMassageType_Req_FIU_SMFR_REQ_CTR_SEATS_Type_2_Energy +#define FIU_SMFR_BackrestMassageType_Req_FIU_SMFR_REQ_CTR_SEATS_Type_2_Energy (2) +#endif + +#ifndef FIU_SMFR_BackrestMassageType_Req_FIU_SMFR_REQ_CTR_SEATS_Type_1_Synchrony +#define FIU_SMFR_BackrestMassageType_Req_FIU_SMFR_REQ_CTR_SEATS_Type_1_Synchrony (1) +#endif + +#ifndef FIU_SMFR_BackrestMassageType_Req_FIU_SMFR_REQ_CTR_SEATS_No_action +#define FIU_SMFR_BackrestMassageType_Req_FIU_SMFR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFR_ComfortMode_Req signal + +#ifndef FIU_SMFR_ComfortMode_Req_FIU_SMFR_REQ_CTR_SEATS_Active +#define FIU_SMFR_ComfortMode_Req_FIU_SMFR_REQ_CTR_SEATS_Active (1) +#endif + +#ifndef FIU_SMFR_ComfortMode_Req_FIU_SMFR_REQ_CTR_SEATS_Inactive +#define FIU_SMFR_ComfortMode_Req_FIU_SMFR_REQ_CTR_SEATS_Inactive (0) +#endif + + +// Value tables for @FIU_SMFR_ComfortScenario_Req signal + +#ifndef FIU_SMFR_ComfortScenario_Req_FIU_SMFR_REQ_CTR_SEATS_Type_3 +#define FIU_SMFR_ComfortScenario_Req_FIU_SMFR_REQ_CTR_SEATS_Type_3 (3) +#endif + +#ifndef FIU_SMFR_ComfortScenario_Req_FIU_SMFR_REQ_CTR_SEATS_Type_2 +#define FIU_SMFR_ComfortScenario_Req_FIU_SMFR_REQ_CTR_SEATS_Type_2 (2) +#endif + +#ifndef FIU_SMFR_ComfortScenario_Req_FIU_SMFR_REQ_CTR_SEATS_Type_1 +#define FIU_SMFR_ComfortScenario_Req_FIU_SMFR_REQ_CTR_SEATS_Type_1 (1) +#endif + +#ifndef FIU_SMFR_ComfortScenario_Req_FIU_SMFR_REQ_CTR_SEATS_No_action +#define FIU_SMFR_ComfortScenario_Req_FIU_SMFR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFR_CarpetHeat_Req signal + +#ifndef FIU_SMFR_CarpetHeat_Req_FIU_SMFR_REQ_CTR_SEATS_Active +#define FIU_SMFR_CarpetHeat_Req_FIU_SMFR_REQ_CTR_SEATS_Active (1) +#endif + +#ifndef FIU_SMFR_CarpetHeat_Req_FIU_SMFR_REQ_CTR_SEATS_Inactive +#define FIU_SMFR_CarpetHeat_Req_FIU_SMFR_REQ_CTR_SEATS_Inactive (0) +#endif + + +// Value tables for @FIU_SMFR_TimerMassage_Req signal + +#ifndef FIU_SMFR_TimerMassage_Req_FIU_SMFR_REQ_CTR_SEATS_Reserved +#define FIU_SMFR_TimerMassage_Req_FIU_SMFR_REQ_CTR_SEATS_Reserved (7) +#endif + +#ifndef FIU_SMFR_TimerMassage_Req_FIU_SMFR_REQ_CTR_SEATS__min +#define FIU_SMFR_TimerMassage_Req_FIU_SMFR_REQ_CTR_SEATS__min (6) +#endif + +#ifndef FIU_SMFR_TimerMassage_Req_FIU_SMFR_REQ_CTR_SEATS__min +#define FIU_SMFR_TimerMassage_Req_FIU_SMFR_REQ_CTR_SEATS__min (5) +#endif + +#ifndef FIU_SMFR_TimerMassage_Req_FIU_SMFR_REQ_CTR_SEATS__min +#define FIU_SMFR_TimerMassage_Req_FIU_SMFR_REQ_CTR_SEATS__min (4) +#endif + +#ifndef FIU_SMFR_TimerMassage_Req_FIU_SMFR_REQ_CTR_SEATS__min +#define FIU_SMFR_TimerMassage_Req_FIU_SMFR_REQ_CTR_SEATS__min (3) +#endif + +#ifndef FIU_SMFR_TimerMassage_Req_FIU_SMFR_REQ_CTR_SEATS__min +#define FIU_SMFR_TimerMassage_Req_FIU_SMFR_REQ_CTR_SEATS__min (2) +#endif + +#ifndef FIU_SMFR_TimerMassage_Req_FIU_SMFR_REQ_CTR_SEATS__min +#define FIU_SMFR_TimerMassage_Req_FIU_SMFR_REQ_CTR_SEATS__min (1) +#endif + +#ifndef FIU_SMFR_TimerMassage_Req_FIU_SMFR_REQ_CTR_SEATS_No_action +#define FIU_SMFR_TimerMassage_Req_FIU_SMFR_REQ_CTR_SEATS_No_action (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Signal for regulation Seat Height FR + // (FR seat base height regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFR_SeatHeight_Req : 2; // Bits= 2 + + // Signal for regulation FR head rest height + // (FR headrest height regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFR_HeadRest_Height_Req : 2; // Bits= 2 + + // Signal for regulation FR seat longitudinal + // (FR seat base longitudinal regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFR_SeatLongitunalReq : 2; // Bits= 2 + + // Signal for regulation FR seat inclination + // (FR headrest depth regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFR_SeatHeadRestInclin_Req : 2; // Bits= 2 + + // Signal for regulation FR seat surface longitudinal + // (FR seat pillow longitudinal regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFR_SeatSurfaceLong_Req : 2; // Bits= 2 + + // Signal for regulation FR seat leg support height + // (FR seat leg support height regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFR_SeatLegSupportH_Req : 2; // Bits= 2 + + // Signal for regulation FR seat leg support longitudinal + // (FR seat leg support longitudinal regulation request, RESERVE) + // 3 : "Resertved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFR_SeatLegSupportLong_Req : 2; // Bits= 2 + + // Signal for regulation FR seat inclination + // (FR seat pillow inclination regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFR_SeatInclination_Req : 2; // Bits= 2 + + // Signal for regulation FR seat backrest lnclination + // (FR backrest angle regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFR_SeatBackRestInc_Req : 2; // Bits= 2 + + // Signal for regulation FR seat lumbar support height + // (FR backrest lumbar support height regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFR_SeatLumbarSupHeight_Req : 2; // Bits= 2 + + // Signal for regulation FR seat backrest head inclination + // (FR backrest should support regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFR_SeatBackRestHeadInc_Req : 2; // Bits= 2 + + // Signal for regulation FR seat lumbar support depth + // (FR backrest lumbar support depth regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFR_SeatLumbarSupDepth_Req : 2; // Bits= 2 + + // Signal for regulation FR seat backrest width + // (FR backrest lateral support regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFR_BackRestWidth_Req : 2; // Bits= 2 + + // Signal for regulation FR seat cushion support + // (FR seat cushion side lateral support regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFR_SeatCushionSupport_Req : 2; // Bits= 2 + + // Signal for seat massage activation + // (FR seat massage request) + // 3 : "Reserved" + // 2 : "Massage ON" + // 1 : "Massage OFF" + // 0 : "No action" + uint8_t FIU_SMFR_SeatMassage_Req : 2; // Bits= 2 + + // Signal for ventilation activation mode + // (FR seat ventilation request) + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "Off" + uint8_t FIU_SMFR_SeatVentilation_Req : 2; // Bits= 2 + + // Signal for ventilation balance mode + // (FR seat ventilation balance request) + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 00%, Cushion 100%: -3" + // 0 : "No action" + uint8_t FIU_SMFR_SeatVentBalance_Req : 3; // Bits= 3 + + // Signal for seat massage intencity regulation + // (FR seat massage intencity request) + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "No action" + uint8_t FIU_SMFR_SeatMassageIntence_Req : 2; // Bits= 2 + + // Signal for seat heating activation mode + // (FR seat heating request) + // 3 : "High power" + // 2 : "Normal power" + // 1 : "Low power" + // 0 : "Off" + uint8_t FIU_SMFR_SeatHeating_Req : 2; // Bits= 2 + + // FR active lateral support request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_SMFR_ActiveSupport_Req : 1; // Bits= 1 + + // Signal for seat heating balance + // (FR seat heating balance request) + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 00%, Cushion 100%: -3" + // 0 : "No action" + uint8_t FIU_SMFR_SeatHeatBalance_Req : 3; // Bits= 3 + + // Signal for seat massage type (mode) + // (FR seat massage type request) + // 7 : "Type 7 (Velvet)" + // 6 : "Type 6 (Sonnet)" + // 5 : "Type 5 (Quantum)" + // 4 : "Type 4 (Cashmere)" + // 3 : "Type 3 (Harmony)" + // 2 : "Type 2 (Orbital)" + // 1 : "Type 1 (Insight)" + // 0 : "No action" + uint8_t FIU_SMFR_SeatMassageType_Req : 3; // Bits= 3 + + // Signal for backrest massage type (mode) + // (FL backrest massage type command) + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Type 5 (Elegy)" + // 4 : "Type 4 (Caprice)" + // 3 : "Type 3 (Pulse)" + // 2 : "Type 2 (Energy)" + // 1 : "Type 1 (Synchrony)" + // 0 : "No action" + uint8_t FIU_SMFR_BackrestMassageType_Req : 3; // Bits= 3 + + // FR comfort mode command + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_SMFR_ComfortMode_Req : 1; // Bits= 1 + + // FR comfort mode scenario command + // 3 : "Type 3" + // 2 : "Type 2" + // 1 : "Type 1" + // 0 : "No action" + uint8_t FIU_SMFR_ComfortScenario_Req : 2; // Bits= 2 + + // FR carpet heating command + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_SMFR_CarpetHeat_Req : 1; // Bits= 1 + + // Signal for setting the massage timer + // 7 : "Reserved" + // 6 : "30 min" + // 5 : "25 min" + // 4 : "20 min" + // 3 : "15 min" + // 2 : "10 min" + // 1 : "5 min" + // 0 : "No action" + uint8_t FIU_SMFR_TimerMassage_Req : 3; // Bits= 3 + +#else + + // Signal for regulation Seat Height FR + // (FR seat base height regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFR_SeatHeight_Req; // Bits= 2 + + // Signal for regulation FR head rest height + // (FR headrest height regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFR_HeadRest_Height_Req; // Bits= 2 + + // Signal for regulation FR seat longitudinal + // (FR seat base longitudinal regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFR_SeatLongitunalReq; // Bits= 2 + + // Signal for regulation FR seat inclination + // (FR headrest depth regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFR_SeatHeadRestInclin_Req; // Bits= 2 + + // Signal for regulation FR seat surface longitudinal + // (FR seat pillow longitudinal regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFR_SeatSurfaceLong_Req; // Bits= 2 + + // Signal for regulation FR seat leg support height + // (FR seat leg support height regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFR_SeatLegSupportH_Req; // Bits= 2 + + // Signal for regulation FR seat leg support longitudinal + // (FR seat leg support longitudinal regulation request, RESERVE) + // 3 : "Resertved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFR_SeatLegSupportLong_Req; // Bits= 2 + + // Signal for regulation FR seat inclination + // (FR seat pillow inclination regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFR_SeatInclination_Req; // Bits= 2 + + // Signal for regulation FR seat backrest lnclination + // (FR backrest angle regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFR_SeatBackRestInc_Req; // Bits= 2 + + // Signal for regulation FR seat lumbar support height + // (FR backrest lumbar support height regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFR_SeatLumbarSupHeight_Req; // Bits= 2 + + // Signal for regulation FR seat backrest head inclination + // (FR backrest should support regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFR_SeatBackRestHeadInc_Req; // Bits= 2 + + // Signal for regulation FR seat lumbar support depth + // (FR backrest lumbar support depth regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFR_SeatLumbarSupDepth_Req; // Bits= 2 + + // Signal for regulation FR seat backrest width + // (FR backrest lateral support regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFR_BackRestWidth_Req; // Bits= 2 + + // Signal for regulation FR seat cushion support + // (FR seat cushion side lateral support regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFR_SeatCushionSupport_Req; // Bits= 2 + + // Signal for seat massage activation + // (FR seat massage request) + // 3 : "Reserved" + // 2 : "Massage ON" + // 1 : "Massage OFF" + // 0 : "No action" + uint8_t FIU_SMFR_SeatMassage_Req; // Bits= 2 + + // Signal for ventilation activation mode + // (FR seat ventilation request) + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "Off" + uint8_t FIU_SMFR_SeatVentilation_Req; // Bits= 2 + + // Signal for ventilation balance mode + // (FR seat ventilation balance request) + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 00%, Cushion 100%: -3" + // 0 : "No action" + uint8_t FIU_SMFR_SeatVentBalance_Req; // Bits= 3 + + // Signal for seat massage intencity regulation + // (FR seat massage intencity request) + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "No action" + uint8_t FIU_SMFR_SeatMassageIntence_Req; // Bits= 2 + + // Signal for seat heating activation mode + // (FR seat heating request) + // 3 : "High power" + // 2 : "Normal power" + // 1 : "Low power" + // 0 : "Off" + uint8_t FIU_SMFR_SeatHeating_Req; // Bits= 2 + + // FR active lateral support request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_SMFR_ActiveSupport_Req; // Bits= 1 + + // Signal for seat heating balance + // (FR seat heating balance request) + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 00%, Cushion 100%: -3" + // 0 : "No action" + uint8_t FIU_SMFR_SeatHeatBalance_Req; // Bits= 3 + + // Signal for seat massage type (mode) + // (FR seat massage type request) + // 7 : "Type 7 (Velvet)" + // 6 : "Type 6 (Sonnet)" + // 5 : "Type 5 (Quantum)" + // 4 : "Type 4 (Cashmere)" + // 3 : "Type 3 (Harmony)" + // 2 : "Type 2 (Orbital)" + // 1 : "Type 1 (Insight)" + // 0 : "No action" + uint8_t FIU_SMFR_SeatMassageType_Req; // Bits= 3 + + // Signal for backrest massage type (mode) + // (FL backrest massage type command) + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Type 5 (Elegy)" + // 4 : "Type 4 (Caprice)" + // 3 : "Type 3 (Pulse)" + // 2 : "Type 2 (Energy)" + // 1 : "Type 1 (Synchrony)" + // 0 : "No action" + uint8_t FIU_SMFR_BackrestMassageType_Req; // Bits= 3 + + // FR comfort mode command + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_SMFR_ComfortMode_Req; // Bits= 1 + + // FR comfort mode scenario command + // 3 : "Type 3" + // 2 : "Type 2" + // 1 : "Type 1" + // 0 : "No action" + uint8_t FIU_SMFR_ComfortScenario_Req; // Bits= 2 + + // FR carpet heating command + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_SMFR_CarpetHeat_Req; // Bits= 1 + + // Signal for setting the massage timer + // 7 : "Reserved" + // 6 : "30 min" + // 5 : "25 min" + // 4 : "20 min" + // 3 : "15 min" + // 2 : "10 min" + // 1 : "5 min" + // 0 : "No action" + uint8_t FIU_SMFR_TimerMassage_Req; // Bits= 3 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} FIU_SMFR_REQ_CTR_SEATS_t; + +// def @SMFL_MEM1 CAN Message (1331 0x533) +#define SMFL_MEM1_IDE (0U) +#define SMFL_MEM1_DLC (8U) +#define SMFL_MEM1_CANID (0x533U) +// signal: @SMFL_PosnActSeatI_Val_ro +#define CANDB_SMFL_PosnActSeatI_Val_ro_CovFactor (0.125) +#define CANDB_SMFL_PosnActSeatI_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.125)) ) +#define CANDB_SMFL_PosnActSeatI_Val_ro_fromS(x) ( (((x) * (0.125)) + (0.0)) ) +// signal: @SMFL_PosnActSeatBRW_Val_ro +#define CANDB_SMFL_PosnActSeatBRW_Val_ro_CovFactor (1) +#define CANDB_SMFL_PosnActSeatBRW_Val_ro_toS(x) ( (uint8_t) ((x) - (300)) ) +#define CANDB_SMFL_PosnActSeatBRW_Val_ro_fromS(x) ( ((x) + (300)) ) +// signal: @SMFL_PosnActSeatFRH_Val_ro +#define CANDB_SMFL_PosnActSeatFRH_Val_ro_CovFactor (0.8) +#define CANDB_SMFL_PosnActSeatFRH_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.8)) ) +#define CANDB_SMFL_PosnActSeatFRH_Val_ro_fromS(x) ( (((x) * (0.8)) + (0.0)) ) +// signal: @SMFL_PosnActSeatFRL_Val_ro +#define CANDB_SMFL_PosnActSeatFRL_Val_ro_CovFactor (0.25) +#define CANDB_SMFL_PosnActSeatFRL_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.25)) ) +#define CANDB_SMFL_PosnActSeatFRL_Val_ro_fromS(x) ( (((x) * (0.25)) + (0.0)) ) +// signal: @SMFL_PosnActSeatH_Val_ro +#define CANDB_SMFL_PosnActSeatH_Val_ro_CovFactor (0.8) +#define CANDB_SMFL_PosnActSeatH_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.8)) ) +#define CANDB_SMFL_PosnActSeatH_Val_ro_fromS(x) ( (((x) * (0.8)) + (0.0)) ) +// signal: @SMFL_PosnActSeatHRH_Val_ro +#define CANDB_SMFL_PosnActSeatHRH_Val_ro_CovFactor (0.5) +#define CANDB_SMFL_PosnActSeatHRH_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.5)) ) +#define CANDB_SMFL_PosnActSeatHRH_Val_ro_fromS(x) ( (((x) * (0.5)) + (0.0)) ) +// signal: @SMFL_PosnActSeatL_Val_ro +#define CANDB_SMFL_PosnActSeatL_Val_ro_CovFactor (0.8) +#define CANDB_SMFL_PosnActSeatL_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.8)) ) +#define CANDB_SMFL_PosnActSeatL_Val_ro_fromS(x) ( (((x) * (0.8)) + (0.0)) ) +// signal: @SMFL_PosnActSeatSL_Val_ro +#define CANDB_SMFL_PosnActSeatSL_Val_ro_CovFactor (0.8) +#define CANDB_SMFL_PosnActSeatSL_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.8)) ) +#define CANDB_SMFL_PosnActSeatSL_Val_ro_fromS(x) ( (((x) * (0.8)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // SMFL current seat inclination position. + uint8_t SMFL_PosnActSeatI_Val_ro; // Bits= 8 Factor= 0.125 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFL_PosnActSeatI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFL current seat back rest width position. + uint8_t SMFL_PosnActSeatBRW_Val_ro; // Bits= 8 Offset= 300 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + uint16_t SMFL_PosnActSeatBRW_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFL current seat foot rest height position. + uint8_t SMFL_PosnActSeatFRH_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFL_PosnActSeatFRH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFL current seat foot rest longitudinal position. + uint8_t SMFL_PosnActSeatFRL_Val_ro; // Bits= 8 Factor= 0.25 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFL_PosnActSeatFRL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFL current seat height position. + uint8_t SMFL_PosnActSeatH_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFL_PosnActSeatH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFL current seat head rest height position. + uint8_t SMFL_PosnActSeatHRH_Val_ro; // Bits= 8 Factor= 0.5 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFL_PosnActSeatHRH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFL current seat longitudinal position. + uint8_t SMFL_PosnActSeatL_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFL_PosnActSeatL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFL current seat surface longitudinal position. + uint8_t SMFL_PosnActSeatSL_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFL_PosnActSeatSL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#else + + // SMFL current seat inclination position. + uint8_t SMFL_PosnActSeatI_Val_ro; // Bits= 8 Factor= 0.125 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFL_PosnActSeatI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFL current seat back rest width position. + uint8_t SMFL_PosnActSeatBRW_Val_ro; // Bits= 8 Offset= 300 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + uint16_t SMFL_PosnActSeatBRW_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFL current seat foot rest height position. + uint8_t SMFL_PosnActSeatFRH_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFL_PosnActSeatFRH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFL current seat foot rest longitudinal position. + uint8_t SMFL_PosnActSeatFRL_Val_ro; // Bits= 8 Factor= 0.25 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFL_PosnActSeatFRL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFL current seat height position. + uint8_t SMFL_PosnActSeatH_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFL_PosnActSeatH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFL current seat head rest height position. + uint8_t SMFL_PosnActSeatHRH_Val_ro; // Bits= 8 Factor= 0.5 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFL_PosnActSeatHRH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFL current seat longitudinal position. + uint8_t SMFL_PosnActSeatL_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFL_PosnActSeatL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFL current seat surface longitudinal position. + uint8_t SMFL_PosnActSeatSL_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFL_PosnActSeatSL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} SMFL_MEM1_t; + +// def @BCM_MEM_SMFL1 CAN Message (1332 0x534) +#define BCM_MEM_SMFL1_IDE (0U) +#define BCM_MEM_SMFL1_DLC (8U) +#define BCM_MEM_SMFL1_CANID (0x534U) +// signal: @BCM_FLMemPosnActSeatI_Val_ro +#define CANDB_BCM_FLMemPosnActSeatI_Val_ro_CovFactor (0.125) +#define CANDB_BCM_FLMemPosnActSeatI_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.125)) ) +#define CANDB_BCM_FLMemPosnActSeatI_Val_ro_fromS(x) ( (((x) * (0.125)) + (0.0)) ) +// signal: @BCM_FLMemPosnActSeatBRW_Val_ro +#define CANDB_BCM_FLMemPosnActSeatBRW_Val_ro_CovFactor (1) +#define CANDB_BCM_FLMemPosnActSeatBRW_Val_ro_toS(x) ( (uint8_t) ((x) - (300)) ) +#define CANDB_BCM_FLMemPosnActSeatBRW_Val_ro_fromS(x) ( ((x) + (300)) ) +// signal: @BCM_FLMemPosnActSeatFRH_Val_ro +#define CANDB_BCM_FLMemPosnActSeatFRH_Val_ro_CovFactor (0.8) +#define CANDB_BCM_FLMemPosnActSeatFRH_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.8)) ) +#define CANDB_BCM_FLMemPosnActSeatFRH_Val_ro_fromS(x) ( (((x) * (0.8)) + (0.0)) ) +// signal: @BCM_FLMemPosnActSeatFRL_Val_ro +#define CANDB_BCM_FLMemPosnActSeatFRL_Val_ro_CovFactor (0.25) +#define CANDB_BCM_FLMemPosnActSeatFRL_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.25)) ) +#define CANDB_BCM_FLMemPosnActSeatFRL_Val_ro_fromS(x) ( (((x) * (0.25)) + (0.0)) ) +// signal: @BCM_FLMemPosnActSeatH_Val_ro +#define CANDB_BCM_FLMemPosnActSeatH_Val_ro_CovFactor (0.8) +#define CANDB_BCM_FLMemPosnActSeatH_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.8)) ) +#define CANDB_BCM_FLMemPosnActSeatH_Val_ro_fromS(x) ( (((x) * (0.8)) + (0.0)) ) +// signal: @BCM_FLMemPosnActSeatHRH_Val_ro +#define CANDB_BCM_FLMemPosnActSeatHRH_Val_ro_CovFactor (0.5) +#define CANDB_BCM_FLMemPosnActSeatHRH_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.5)) ) +#define CANDB_BCM_FLMemPosnActSeatHRH_Val_ro_fromS(x) ( (((x) * (0.5)) + (0.0)) ) +// signal: @BCM_FLMemPosnActSeatL_Val_ro +#define CANDB_BCM_FLMemPosnActSeatL_Val_ro_CovFactor (0.8) +#define CANDB_BCM_FLMemPosnActSeatL_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.8)) ) +#define CANDB_BCM_FLMemPosnActSeatL_Val_ro_fromS(x) ( (((x) * (0.8)) + (0.0)) ) +// signal: @BCM_FLMemPosnActSeatSL_Val_ro +#define CANDB_BCM_FLMemPosnActSeatSL_Val_ro_CovFactor (0.8) +#define CANDB_BCM_FLMemPosnActSeatSL_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.8)) ) +#define CANDB_BCM_FLMemPosnActSeatSL_Val_ro_fromS(x) ( (((x) * (0.8)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Stored SMFL seat inclination position. + uint8_t BCM_FLMemPosnActSeatI_Val_ro; // Bits= 8 Factor= 0.125 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FLMemPosnActSeatI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMFL seat back rest width position. + uint8_t BCM_FLMemPosnActSeatBRW_Val_ro; // Bits= 8 Offset= 300 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + uint16_t BCM_FLMemPosnActSeatBRW_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMFL seat foot rest height position. + uint8_t BCM_FLMemPosnActSeatFRH_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FLMemPosnActSeatFRH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMFL seat foot rest longitudinal position. + uint8_t BCM_FLMemPosnActSeatFRL_Val_ro; // Bits= 8 Factor= 0.25 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FLMemPosnActSeatFRL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMFL seat height position. + uint8_t BCM_FLMemPosnActSeatH_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FLMemPosnActSeatH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMFL seat head rest height position. + uint8_t BCM_FLMemPosnActSeatHRH_Val_ro; // Bits= 8 Factor= 0.5 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FLMemPosnActSeatHRH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMFL seat longitudinal position. + uint8_t BCM_FLMemPosnActSeatL_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FLMemPosnActSeatL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMFL seat surface longitudinal position. + uint8_t BCM_FLMemPosnActSeatSL_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FLMemPosnActSeatSL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#else + + // Stored SMFL seat inclination position. + uint8_t BCM_FLMemPosnActSeatI_Val_ro; // Bits= 8 Factor= 0.125 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FLMemPosnActSeatI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMFL seat back rest width position. + uint8_t BCM_FLMemPosnActSeatBRW_Val_ro; // Bits= 8 Offset= 300 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + uint16_t BCM_FLMemPosnActSeatBRW_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMFL seat foot rest height position. + uint8_t BCM_FLMemPosnActSeatFRH_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FLMemPosnActSeatFRH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMFL seat foot rest longitudinal position. + uint8_t BCM_FLMemPosnActSeatFRL_Val_ro; // Bits= 8 Factor= 0.25 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FLMemPosnActSeatFRL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMFL seat height position. + uint8_t BCM_FLMemPosnActSeatH_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FLMemPosnActSeatH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMFL seat head rest height position. + uint8_t BCM_FLMemPosnActSeatHRH_Val_ro; // Bits= 8 Factor= 0.5 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FLMemPosnActSeatHRH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMFL seat longitudinal position. + uint8_t BCM_FLMemPosnActSeatL_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FLMemPosnActSeatL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMFL seat surface longitudinal position. + uint8_t BCM_FLMemPosnActSeatSL_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FLMemPosnActSeatSL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} BCM_MEM_SMFL1_t; + +// def @SMFL_MEM2 CAN Message (1333 0x535) +#define SMFL_MEM2_IDE (0U) +#define SMFL_MEM2_DLC (8U) +#define SMFL_MEM2_CANID (0x535U) +// signal: @SMFL_PosnActSeatBRHI_Val_ro +#define CANDB_SMFL_PosnActSeatBRHI_Val_ro_CovFactor (0.1) +#define CANDB_SMFL_PosnActSeatBRHI_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_SMFL_PosnActSeatBRHI_Val_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @SMFL_PosnActSeatHRHI_Val_ro +#define CANDB_SMFL_PosnActSeatHRHI_Val_ro_CovFactor (0.71) +#define CANDB_SMFL_PosnActSeatHRHI_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.71)) ) +#define CANDB_SMFL_PosnActSeatHRHI_Val_ro_fromS(x) ( (((x) * (0.71)) + (0.0)) ) +// signal: @SMFL_PosnActSeatBRI_Val_ro +#define CANDB_SMFL_PosnActSeatBRI_Val_ro_CovFactor (0.1) +#define CANDB_SMFL_PosnActSeatBRI_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_SMFL_PosnActSeatBRI_Val_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +// Value tables for @SMFL_ActHeatBalance_Val signal + +#ifndef SMFL_ActHeatBalance_Val_SMFL_MEM2_Backrest_100_Cushion_00_3 +#define SMFL_ActHeatBalance_Val_SMFL_MEM2_Backrest_100_Cushion_00_3 (7) +#endif + +#ifndef SMFL_ActHeatBalance_Val_SMFL_MEM2_Backrest_100_Cushion_33_2 +#define SMFL_ActHeatBalance_Val_SMFL_MEM2_Backrest_100_Cushion_33_2 (6) +#endif + +#ifndef SMFL_ActHeatBalance_Val_SMFL_MEM2_Backrest_100_Cushion_67_1 +#define SMFL_ActHeatBalance_Val_SMFL_MEM2_Backrest_100_Cushion_67_1 (5) +#endif + +#ifndef SMFL_ActHeatBalance_Val_SMFL_MEM2_Backrest_100_Cushion_100_0 +#define SMFL_ActHeatBalance_Val_SMFL_MEM2_Backrest_100_Cushion_100_0 (4) +#endif + +#ifndef SMFL_ActHeatBalance_Val_SMFL_MEM2_Backrest_67_Cushion_100_1 +#define SMFL_ActHeatBalance_Val_SMFL_MEM2_Backrest_67_Cushion_100_1 (3) +#endif + +#ifndef SMFL_ActHeatBalance_Val_SMFL_MEM2_Backrest_33_Cushion_100_2 +#define SMFL_ActHeatBalance_Val_SMFL_MEM2_Backrest_33_Cushion_100_2 (2) +#endif + +#ifndef SMFL_ActHeatBalance_Val_SMFL_MEM2_Backrest_00_Cushion_100_3 +#define SMFL_ActHeatBalance_Val_SMFL_MEM2_Backrest_00_Cushion_100_3 (1) +#endif + +#ifndef SMFL_ActHeatBalance_Val_SMFL_MEM2_No_action +#define SMFL_ActHeatBalance_Val_SMFL_MEM2_No_action (0) +#endif + +// signal: @SMFL_PosnPrsnSeatCS_Val_ro +#define CANDB_SMFL_PosnPrsnSeatCS_Val_ro_CovFactor (0.394) +#define CANDB_SMFL_PosnPrsnSeatCS_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.394)) ) +#define CANDB_SMFL_PosnPrsnSeatCS_Val_ro_fromS(x) ( (((x) * (0.394)) + (0.0)) ) +// signal: @SMFL_PosnPrsnSeatLSH_Val_ro +#define CANDB_SMFL_PosnPrsnSeatLSH_Val_ro_CovFactor (0.394) +#define CANDB_SMFL_PosnPrsnSeatLSH_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.394)) ) +#define CANDB_SMFL_PosnPrsnSeatLSH_Val_ro_fromS(x) ( (((x) * (0.394)) + (0.0)) ) +// signal: @SMFL_PosnPrsnSeatLSD_Val_ro +#define CANDB_SMFL_PosnPrsnSeatLSD_Val_ro_CovFactor (0.394) +#define CANDB_SMFL_PosnPrsnSeatLSD_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.394)) ) +#define CANDB_SMFL_PosnPrsnSeatLSD_Val_ro_fromS(x) ( (((x) * (0.394)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // SMFL current seat back rest head inclination position. + uint8_t SMFL_PosnActSeatBRHI_Val_ro; // Bits= 8 Factor= 0.1 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFL_PosnActSeatBRHI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFL current seat head rest height inclination position. + uint8_t SMFL_PosnActSeatHRHI_Val_ro; // Bits= 8 Factor= 0.71 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFL_PosnActSeatHRHI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFL current seat back rest inclination position. + uint8_t SMFL_PosnActSeatBRI_Val_ro; // Bits= 8 Factor= 0.1 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFL_PosnActSeatBRI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFL current seat heat balance + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 00%, Cushion 100%: -3" + // 0 : "No action" + uint8_t SMFL_ActHeatBalance_Val : 3; // Bits= 3 + + // SMFL current seat ventilation balance + uint8_t SMFL_ActVentBalance_Val : 3; // Bits= 3 + + // SMFL current seat cushion support position + uint8_t SMFL_PosnPrsnSeatCS_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFL_PosnPrsnSeatCS_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFL current seat Longitudinal Surface Height + uint8_t SMFL_PosnPrsnSeatLSH_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFL_PosnPrsnSeatLSH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFL current seat Longitudinal Surface Depth + uint8_t SMFL_PosnPrsnSeatLSD_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFL_PosnPrsnSeatLSD_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#else + + // SMFL current seat back rest head inclination position. + uint8_t SMFL_PosnActSeatBRHI_Val_ro; // Bits= 8 Factor= 0.1 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFL_PosnActSeatBRHI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFL current seat head rest height inclination position. + uint8_t SMFL_PosnActSeatHRHI_Val_ro; // Bits= 8 Factor= 0.71 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFL_PosnActSeatHRHI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFL current seat back rest inclination position. + uint8_t SMFL_PosnActSeatBRI_Val_ro; // Bits= 8 Factor= 0.1 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFL_PosnActSeatBRI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFL current seat heat balance + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 00%, Cushion 100%: -3" + // 0 : "No action" + uint8_t SMFL_ActHeatBalance_Val; // Bits= 3 + + // SMFL current seat ventilation balance + uint8_t SMFL_ActVentBalance_Val; // Bits= 3 + + // SMFL current seat cushion support position + uint8_t SMFL_PosnPrsnSeatCS_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFL_PosnPrsnSeatCS_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFL current seat Longitudinal Surface Height + uint8_t SMFL_PosnPrsnSeatLSH_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFL_PosnPrsnSeatLSH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFL current seat Longitudinal Surface Depth + uint8_t SMFL_PosnPrsnSeatLSD_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFL_PosnPrsnSeatLSD_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} SMFL_MEM2_t; + +// def @BCM_MEM_SMFL2 CAN Message (1334 0x536) +#define BCM_MEM_SMFL2_IDE (0U) +#define BCM_MEM_SMFL2_DLC (8U) +#define BCM_MEM_SMFL2_CANID (0x536U) +// signal: @BCM_FLMemPosnActSeatBRHI_Val_ro +#define CANDB_BCM_FLMemPosnActSeatBRHI_Val_ro_CovFactor (0.1) +#define CANDB_BCM_FLMemPosnActSeatBRHI_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_BCM_FLMemPosnActSeatBRHI_Val_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @BCM_FLMemPosnActSeatHRHI_Val_ro +#define CANDB_BCM_FLMemPosnActSeatHRHI_Val_ro_CovFactor (0.71) +#define CANDB_BCM_FLMemPosnActSeatHRHI_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.71)) ) +#define CANDB_BCM_FLMemPosnActSeatHRHI_Val_ro_fromS(x) ( (((x) * (0.71)) + (0.0)) ) +// signal: @BCM_FLMemPosnActSeatBRI_Val_ro +#define CANDB_BCM_FLMemPosnActSeatBRI_Val_ro_CovFactor (0.1) +#define CANDB_BCM_FLMemPosnActSeatBRI_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_BCM_FLMemPosnActSeatBRI_Val_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +// Value tables for @BCM_FLMemActHeatBalance_Val signal + +#ifndef BCM_FLMemActHeatBalance_Val_BCM_MEM_SMFL2_Backrest_100_Cushion_0_3 +#define BCM_FLMemActHeatBalance_Val_BCM_MEM_SMFL2_Backrest_100_Cushion_0_3 (7) +#endif + +#ifndef BCM_FLMemActHeatBalance_Val_BCM_MEM_SMFL2_Backrest_100_Cushion_33_2 +#define BCM_FLMemActHeatBalance_Val_BCM_MEM_SMFL2_Backrest_100_Cushion_33_2 (6) +#endif + +#ifndef BCM_FLMemActHeatBalance_Val_BCM_MEM_SMFL2_Backrest_100_Cushion_67_1 +#define BCM_FLMemActHeatBalance_Val_BCM_MEM_SMFL2_Backrest_100_Cushion_67_1 (5) +#endif + +#ifndef BCM_FLMemActHeatBalance_Val_BCM_MEM_SMFL2_Backrest_100_Cushion_100_0 +#define BCM_FLMemActHeatBalance_Val_BCM_MEM_SMFL2_Backrest_100_Cushion_100_0 (4) +#endif + +#ifndef BCM_FLMemActHeatBalance_Val_BCM_MEM_SMFL2_Backrest_67_Cushion_100_1 +#define BCM_FLMemActHeatBalance_Val_BCM_MEM_SMFL2_Backrest_67_Cushion_100_1 (3) +#endif + +#ifndef BCM_FLMemActHeatBalance_Val_BCM_MEM_SMFL2_Backrest_33_Cushion_100_2 +#define BCM_FLMemActHeatBalance_Val_BCM_MEM_SMFL2_Backrest_33_Cushion_100_2 (2) +#endif + +#ifndef BCM_FLMemActHeatBalance_Val_BCM_MEM_SMFL2_Backrest_0_Cushion_100_3 +#define BCM_FLMemActHeatBalance_Val_BCM_MEM_SMFL2_Backrest_0_Cushion_100_3 (1) +#endif + +#ifndef BCM_FLMemActHeatBalance_Val_BCM_MEM_SMFL2_No_action +#define BCM_FLMemActHeatBalance_Val_BCM_MEM_SMFL2_No_action (0) +#endif + + +// Value tables for @BCM_FLMemActVentBalance_Val signal + +#ifndef BCM_FLMemActVentBalance_Val_BCM_MEM_SMFL2_Backrest_100_Cushion_0_3 +#define BCM_FLMemActVentBalance_Val_BCM_MEM_SMFL2_Backrest_100_Cushion_0_3 (7) +#endif + +#ifndef BCM_FLMemActVentBalance_Val_BCM_MEM_SMFL2_Backrest_100_Cushion_33_2 +#define BCM_FLMemActVentBalance_Val_BCM_MEM_SMFL2_Backrest_100_Cushion_33_2 (6) +#endif + +#ifndef BCM_FLMemActVentBalance_Val_BCM_MEM_SMFL2_Backrest_100_Cushion_67_1 +#define BCM_FLMemActVentBalance_Val_BCM_MEM_SMFL2_Backrest_100_Cushion_67_1 (5) +#endif + +#ifndef BCM_FLMemActVentBalance_Val_BCM_MEM_SMFL2_Backrest_100_Cushion_100_0 +#define BCM_FLMemActVentBalance_Val_BCM_MEM_SMFL2_Backrest_100_Cushion_100_0 (4) +#endif + +#ifndef BCM_FLMemActVentBalance_Val_BCM_MEM_SMFL2_Backrest_67_Cushion_100_1 +#define BCM_FLMemActVentBalance_Val_BCM_MEM_SMFL2_Backrest_67_Cushion_100_1 (3) +#endif + +#ifndef BCM_FLMemActVentBalance_Val_BCM_MEM_SMFL2_Backrest_33_Cushion_100_2 +#define BCM_FLMemActVentBalance_Val_BCM_MEM_SMFL2_Backrest_33_Cushion_100_2 (2) +#endif + +#ifndef BCM_FLMemActVentBalance_Val_BCM_MEM_SMFL2_Backrest_0_Cushion_100_3 +#define BCM_FLMemActVentBalance_Val_BCM_MEM_SMFL2_Backrest_0_Cushion_100_3 (1) +#endif + +#ifndef BCM_FLMemActVentBalance_Val_BCM_MEM_SMFL2_No_action +#define BCM_FLMemActVentBalance_Val_BCM_MEM_SMFL2_No_action (0) +#endif + +// signal: @BCM_FLMemPosnPrsnSeatCS_Val_ro +#define CANDB_BCM_FLMemPosnPrsnSeatCS_Val_ro_CovFactor (0.394) +#define CANDB_BCM_FLMemPosnPrsnSeatCS_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.394)) ) +#define CANDB_BCM_FLMemPosnPrsnSeatCS_Val_ro_fromS(x) ( (((x) * (0.394)) + (0.0)) ) +// signal: @BCM_FLMemPosnPrsnSeatLSH_Val_ro +#define CANDB_BCM_FLMemPosnPrsnSeatLSH_Val_ro_CovFactor (0.394) +#define CANDB_BCM_FLMemPosnPrsnSeatLSH_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.394)) ) +#define CANDB_BCM_FLMemPosnPrsnSeatLSH_Val_ro_fromS(x) ( (((x) * (0.394)) + (0.0)) ) +// signal: @BCM_FLMemPosnPrsnSeatLSD_Val_ro +#define CANDB_BCM_FLMemPosnPrsnSeatLSD_Val_ro_CovFactor (0.394) +#define CANDB_BCM_FLMemPosnPrsnSeatLSD_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.394)) ) +#define CANDB_BCM_FLMemPosnPrsnSeatLSD_Val_ro_fromS(x) ( (((x) * (0.394)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Stored for SMFL seat back rest head inclination position. + uint8_t BCM_FLMemPosnActSeatBRHI_Val_ro; // Bits= 8 Factor= 0.1 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FLMemPosnActSeatBRHI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMFL seat head rest height inclination position. + uint8_t BCM_FLMemPosnActSeatHRHI_Val_ro; // Bits= 8 Factor= 0.71 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FLMemPosnActSeatHRHI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMFL seat back rest inclination position. + uint8_t BCM_FLMemPosnActSeatBRI_Val_ro; // Bits= 8 Factor= 0.1 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FLMemPosnActSeatBRI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMFL seat heat balance + // 7 : "Backrest 100%, Cushion 0%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 0%, Cushion 100%: -3" + // 0 : "No action" + uint8_t BCM_FLMemActHeatBalance_Val : 3; // Bits= 3 + + // Stored for SMFL seat ventilation balance + // 7 : "Backrest 100%, Cushion 0%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 0%, Cushion 100%: -3" + // 0 : "No action" + uint8_t BCM_FLMemActVentBalance_Val : 3; // Bits= 3 + + // Stored for SMFL seat cushion support position + uint8_t BCM_FLMemPosnPrsnSeatCS_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FLMemPosnPrsnSeatCS_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Srored for SMFL seat Longitudinal Surface Height + uint8_t BCM_FLMemPosnPrsnSeatLSH_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FLMemPosnPrsnSeatLSH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Srored for SMFL seat Longitudinal Surface Depth + uint8_t BCM_FLMemPosnPrsnSeatLSD_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FLMemPosnPrsnSeatLSD_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#else + + // Stored for SMFL seat back rest head inclination position. + uint8_t BCM_FLMemPosnActSeatBRHI_Val_ro; // Bits= 8 Factor= 0.1 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FLMemPosnActSeatBRHI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMFL seat head rest height inclination position. + uint8_t BCM_FLMemPosnActSeatHRHI_Val_ro; // Bits= 8 Factor= 0.71 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FLMemPosnActSeatHRHI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMFL seat back rest inclination position. + uint8_t BCM_FLMemPosnActSeatBRI_Val_ro; // Bits= 8 Factor= 0.1 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FLMemPosnActSeatBRI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMFL seat heat balance + // 7 : "Backrest 100%, Cushion 0%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 0%, Cushion 100%: -3" + // 0 : "No action" + uint8_t BCM_FLMemActHeatBalance_Val; // Bits= 3 + + // Stored for SMFL seat ventilation balance + // 7 : "Backrest 100%, Cushion 0%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 0%, Cushion 100%: -3" + // 0 : "No action" + uint8_t BCM_FLMemActVentBalance_Val; // Bits= 3 + + // Stored for SMFL seat cushion support position + uint8_t BCM_FLMemPosnPrsnSeatCS_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FLMemPosnPrsnSeatCS_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Srored for SMFL seat Longitudinal Surface Height + uint8_t BCM_FLMemPosnPrsnSeatLSH_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FLMemPosnPrsnSeatLSH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Srored for SMFL seat Longitudinal Surface Depth + uint8_t BCM_FLMemPosnPrsnSeatLSD_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FLMemPosnPrsnSeatLSD_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} BCM_MEM_SMFL2_t; + +// def @SMFR_MEM1 CAN Message (1335 0x537) +#define SMFR_MEM1_IDE (0U) +#define SMFR_MEM1_DLC (8U) +#define SMFR_MEM1_CANID (0x537U) +// signal: @SMFR_PosnActSeatI_Val_ro +#define CANDB_SMFR_PosnActSeatI_Val_ro_CovFactor (0.125) +#define CANDB_SMFR_PosnActSeatI_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.125)) ) +#define CANDB_SMFR_PosnActSeatI_Val_ro_fromS(x) ( (((x) * (0.125)) + (0.0)) ) +// signal: @SMFR_PosnActSeatBRW_Val_ro +#define CANDB_SMFR_PosnActSeatBRW_Val_ro_CovFactor (1) +#define CANDB_SMFR_PosnActSeatBRW_Val_ro_toS(x) ( (uint8_t) ((x) - (300)) ) +#define CANDB_SMFR_PosnActSeatBRW_Val_ro_fromS(x) ( ((x) + (300)) ) +// signal: @SMFR_PosnActSeatFRH_Val_ro +#define CANDB_SMFR_PosnActSeatFRH_Val_ro_CovFactor (0.8) +#define CANDB_SMFR_PosnActSeatFRH_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.8)) ) +#define CANDB_SMFR_PosnActSeatFRH_Val_ro_fromS(x) ( (((x) * (0.8)) + (0.0)) ) +// signal: @SMFR_PosnActSeatFRL_Val_ro +#define CANDB_SMFR_PosnActSeatFRL_Val_ro_CovFactor (0.25) +#define CANDB_SMFR_PosnActSeatFRL_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.25)) ) +#define CANDB_SMFR_PosnActSeatFRL_Val_ro_fromS(x) ( (((x) * (0.25)) + (0.0)) ) +// signal: @SMFR_PosnActSeatH_Val_ro +#define CANDB_SMFR_PosnActSeatH_Val_ro_CovFactor (0.8) +#define CANDB_SMFR_PosnActSeatH_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.8)) ) +#define CANDB_SMFR_PosnActSeatH_Val_ro_fromS(x) ( (((x) * (0.8)) + (0.0)) ) +// signal: @SMFR_PosnActSeatHRH_Val_ro +#define CANDB_SMFR_PosnActSeatHRH_Val_ro_CovFactor (0.5) +#define CANDB_SMFR_PosnActSeatHRH_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.5)) ) +#define CANDB_SMFR_PosnActSeatHRH_Val_ro_fromS(x) ( (((x) * (0.5)) + (0.0)) ) +// signal: @SMFR_PosnActSeatL_Val_ro +#define CANDB_SMFR_PosnActSeatL_Val_ro_CovFactor (0.8) +#define CANDB_SMFR_PosnActSeatL_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.8)) ) +#define CANDB_SMFR_PosnActSeatL_Val_ro_fromS(x) ( (((x) * (0.8)) + (0.0)) ) +// signal: @SMFR_PosnActSeatSL_Val_ro +#define CANDB_SMFR_PosnActSeatSL_Val_ro_CovFactor (0.8) +#define CANDB_SMFR_PosnActSeatSL_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.8)) ) +#define CANDB_SMFR_PosnActSeatSL_Val_ro_fromS(x) ( (((x) * (0.8)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // SMFR current seat inclination position. + uint8_t SMFR_PosnActSeatI_Val_ro; // Bits= 8 Factor= 0.125 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFR_PosnActSeatI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFR current seat back rest width position. + uint8_t SMFR_PosnActSeatBRW_Val_ro; // Bits= 8 Offset= 300 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + uint16_t SMFR_PosnActSeatBRW_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFR current seat foot rest height position. + uint8_t SMFR_PosnActSeatFRH_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFR_PosnActSeatFRH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFR current seat foot rest longitudinal position. + uint8_t SMFR_PosnActSeatFRL_Val_ro; // Bits= 8 Factor= 0.25 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFR_PosnActSeatFRL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFR current seat height position. + uint8_t SMFR_PosnActSeatH_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFR_PosnActSeatH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFR current seat head rest height position. + uint8_t SMFR_PosnActSeatHRH_Val_ro; // Bits= 8 Factor= 0.5 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFR_PosnActSeatHRH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFR current seat longitudinal position. + uint8_t SMFR_PosnActSeatL_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFR_PosnActSeatL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFR current seat surface longitudinal position. + uint8_t SMFR_PosnActSeatSL_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFR_PosnActSeatSL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#else + + // SMFR current seat inclination position. + uint8_t SMFR_PosnActSeatI_Val_ro; // Bits= 8 Factor= 0.125 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFR_PosnActSeatI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFR current seat back rest width position. + uint8_t SMFR_PosnActSeatBRW_Val_ro; // Bits= 8 Offset= 300 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + uint16_t SMFR_PosnActSeatBRW_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFR current seat foot rest height position. + uint8_t SMFR_PosnActSeatFRH_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFR_PosnActSeatFRH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFR current seat foot rest longitudinal position. + uint8_t SMFR_PosnActSeatFRL_Val_ro; // Bits= 8 Factor= 0.25 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFR_PosnActSeatFRL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFR current seat height position. + uint8_t SMFR_PosnActSeatH_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFR_PosnActSeatH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFR current seat head rest height position. + uint8_t SMFR_PosnActSeatHRH_Val_ro; // Bits= 8 Factor= 0.5 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFR_PosnActSeatHRH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFR current seat longitudinal position. + uint8_t SMFR_PosnActSeatL_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFR_PosnActSeatL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFR current seat surface longitudinal position. + uint8_t SMFR_PosnActSeatSL_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFR_PosnActSeatSL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} SMFR_MEM1_t; + +// def @BCM_MEM_SMFR1 CAN Message (1336 0x538) +#define BCM_MEM_SMFR1_IDE (0U) +#define BCM_MEM_SMFR1_DLC (8U) +#define BCM_MEM_SMFR1_CANID (0x538U) +// signal: @BCM_FRMemPosnActSeatI_Val_ro +#define CANDB_BCM_FRMemPosnActSeatI_Val_ro_CovFactor (0.125) +#define CANDB_BCM_FRMemPosnActSeatI_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.125)) ) +#define CANDB_BCM_FRMemPosnActSeatI_Val_ro_fromS(x) ( (((x) * (0.125)) + (0.0)) ) +// signal: @BCM_FRMemPosnActSeatBRW_Val_ro +#define CANDB_BCM_FRMemPosnActSeatBRW_Val_ro_CovFactor (1) +#define CANDB_BCM_FRMemPosnActSeatBRW_Val_ro_toS(x) ( (uint8_t) ((x) - (300)) ) +#define CANDB_BCM_FRMemPosnActSeatBRW_Val_ro_fromS(x) ( ((x) + (300)) ) +// signal: @BCM_FRMemPosnActSeatFRH_Val_ro +#define CANDB_BCM_FRMemPosnActSeatFRH_Val_ro_CovFactor (0.8) +#define CANDB_BCM_FRMemPosnActSeatFRH_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.8)) ) +#define CANDB_BCM_FRMemPosnActSeatFRH_Val_ro_fromS(x) ( (((x) * (0.8)) + (0.0)) ) +// signal: @BCM_FRMemPosnActSeatFRL_Val_ro +#define CANDB_BCM_FRMemPosnActSeatFRL_Val_ro_CovFactor (0.25) +#define CANDB_BCM_FRMemPosnActSeatFRL_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.25)) ) +#define CANDB_BCM_FRMemPosnActSeatFRL_Val_ro_fromS(x) ( (((x) * (0.25)) + (0.0)) ) +// signal: @BCM_FRMemPosnActSeatH_Val_ro +#define CANDB_BCM_FRMemPosnActSeatH_Val_ro_CovFactor (0.8) +#define CANDB_BCM_FRMemPosnActSeatH_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.8)) ) +#define CANDB_BCM_FRMemPosnActSeatH_Val_ro_fromS(x) ( (((x) * (0.8)) + (0.0)) ) +// signal: @BCM_FRMemPosnActSeatHRH_Val_ro +#define CANDB_BCM_FRMemPosnActSeatHRH_Val_ro_CovFactor (0.5) +#define CANDB_BCM_FRMemPosnActSeatHRH_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.5)) ) +#define CANDB_BCM_FRMemPosnActSeatHRH_Val_ro_fromS(x) ( (((x) * (0.5)) + (0.0)) ) +// signal: @BCM_FRMemPosnActSeatL_Val_ro +#define CANDB_BCM_FRMemPosnActSeatL_Val_ro_CovFactor (0.8) +#define CANDB_BCM_FRMemPosnActSeatL_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.8)) ) +#define CANDB_BCM_FRMemPosnActSeatL_Val_ro_fromS(x) ( (((x) * (0.8)) + (0.0)) ) +// signal: @BCM_FRMemPosnActSeatSL_Val_ro +#define CANDB_BCM_FRMemPosnActSeatSL_Val_ro_CovFactor (0.8) +#define CANDB_BCM_FRMemPosnActSeatSL_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.8)) ) +#define CANDB_BCM_FRMemPosnActSeatSL_Val_ro_fromS(x) ( (((x) * (0.8)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Stored SMFR seat inclination position. + uint8_t BCM_FRMemPosnActSeatI_Val_ro; // Bits= 8 Factor= 0.125 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FRMemPosnActSeatI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMFR seat back rest width position. + uint8_t BCM_FRMemPosnActSeatBRW_Val_ro; // Bits= 8 Offset= 300 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + uint16_t BCM_FRMemPosnActSeatBRW_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMFR seat foot rest height position. + uint8_t BCM_FRMemPosnActSeatFRH_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FRMemPosnActSeatFRH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMFR seat foot rest longitudinal position. + uint8_t BCM_FRMemPosnActSeatFRL_Val_ro; // Bits= 8 Factor= 0.25 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FRMemPosnActSeatFRL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMFR seat height position. + uint8_t BCM_FRMemPosnActSeatH_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FRMemPosnActSeatH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMFR seat head rest height position. + uint8_t BCM_FRMemPosnActSeatHRH_Val_ro; // Bits= 8 Factor= 0.5 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FRMemPosnActSeatHRH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMFR seat longitudinal position. + uint8_t BCM_FRMemPosnActSeatL_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FRMemPosnActSeatL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMFR seat surface longitudinal position. + uint8_t BCM_FRMemPosnActSeatSL_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FRMemPosnActSeatSL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#else + + // Stored SMFR seat inclination position. + uint8_t BCM_FRMemPosnActSeatI_Val_ro; // Bits= 8 Factor= 0.125 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FRMemPosnActSeatI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMFR seat back rest width position. + uint8_t BCM_FRMemPosnActSeatBRW_Val_ro; // Bits= 8 Offset= 300 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + uint16_t BCM_FRMemPosnActSeatBRW_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMFR seat foot rest height position. + uint8_t BCM_FRMemPosnActSeatFRH_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FRMemPosnActSeatFRH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMFR seat foot rest longitudinal position. + uint8_t BCM_FRMemPosnActSeatFRL_Val_ro; // Bits= 8 Factor= 0.25 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FRMemPosnActSeatFRL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMFR seat height position. + uint8_t BCM_FRMemPosnActSeatH_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FRMemPosnActSeatH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMFR seat head rest height position. + uint8_t BCM_FRMemPosnActSeatHRH_Val_ro; // Bits= 8 Factor= 0.5 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FRMemPosnActSeatHRH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMFR seat longitudinal position. + uint8_t BCM_FRMemPosnActSeatL_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FRMemPosnActSeatL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMFR seat surface longitudinal position. + uint8_t BCM_FRMemPosnActSeatSL_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FRMemPosnActSeatSL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} BCM_MEM_SMFR1_t; + +// def @SMFR_MEM2 CAN Message (1337 0x539) +#define SMFR_MEM2_IDE (0U) +#define SMFR_MEM2_DLC (8U) +#define SMFR_MEM2_CANID (0x539U) +// signal: @SMFR_PosnActSeatBRHI_Val_ro +#define CANDB_SMFR_PosnActSeatBRHI_Val_ro_CovFactor (0.1) +#define CANDB_SMFR_PosnActSeatBRHI_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_SMFR_PosnActSeatBRHI_Val_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @SMFR_PosnActSeatHRHI_Val_ro +#define CANDB_SMFR_PosnActSeatHRHI_Val_ro_CovFactor (0.71) +#define CANDB_SMFR_PosnActSeatHRHI_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.71)) ) +#define CANDB_SMFR_PosnActSeatHRHI_Val_ro_fromS(x) ( (((x) * (0.71)) + (0.0)) ) +// signal: @SMFR_PosnActSeatBRI_Val_ro +#define CANDB_SMFR_PosnActSeatBRI_Val_ro_CovFactor (0.1) +#define CANDB_SMFR_PosnActSeatBRI_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_SMFR_PosnActSeatBRI_Val_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +// Value tables for @SMFR_ActHeatBalance_Val signal + +#ifndef SMFR_ActHeatBalance_Val_SMFR_MEM2_Backrest_100_Cushion_00_3 +#define SMFR_ActHeatBalance_Val_SMFR_MEM2_Backrest_100_Cushion_00_3 (7) +#endif + +#ifndef SMFR_ActHeatBalance_Val_SMFR_MEM2_Backrest_100_Cushion_33_2 +#define SMFR_ActHeatBalance_Val_SMFR_MEM2_Backrest_100_Cushion_33_2 (6) +#endif + +#ifndef SMFR_ActHeatBalance_Val_SMFR_MEM2_Backrest_100_Cushion_67_1 +#define SMFR_ActHeatBalance_Val_SMFR_MEM2_Backrest_100_Cushion_67_1 (5) +#endif + +#ifndef SMFR_ActHeatBalance_Val_SMFR_MEM2_Backrest_100_Cushion_100_0 +#define SMFR_ActHeatBalance_Val_SMFR_MEM2_Backrest_100_Cushion_100_0 (4) +#endif + +#ifndef SMFR_ActHeatBalance_Val_SMFR_MEM2_Backrest_67_Cushion_100_1 +#define SMFR_ActHeatBalance_Val_SMFR_MEM2_Backrest_67_Cushion_100_1 (3) +#endif + +#ifndef SMFR_ActHeatBalance_Val_SMFR_MEM2_Backrest_33_Cushion_100_2 +#define SMFR_ActHeatBalance_Val_SMFR_MEM2_Backrest_33_Cushion_100_2 (2) +#endif + +#ifndef SMFR_ActHeatBalance_Val_SMFR_MEM2_No_action +#define SMFR_ActHeatBalance_Val_SMFR_MEM2_No_action (0) +#endif + +#ifndef SMFR_ActHeatBalance_Val_SMFR_MEM2_Backrest_00_Cushion_100_3 +#define SMFR_ActHeatBalance_Val_SMFR_MEM2_Backrest_00_Cushion_100_3 (1) +#endif + + +// Value tables for @SMFR_ActVentBalance_Stat signal + +#ifndef SMFR_ActVentBalance_Stat_SMFR_MEM2_Backrest_100_Cushion_00_3 +#define SMFR_ActVentBalance_Stat_SMFR_MEM2_Backrest_100_Cushion_00_3 (7) +#endif + +#ifndef SMFR_ActVentBalance_Stat_SMFR_MEM2_Backrest_100_Cushion_33_2 +#define SMFR_ActVentBalance_Stat_SMFR_MEM2_Backrest_100_Cushion_33_2 (6) +#endif + +#ifndef SMFR_ActVentBalance_Stat_SMFR_MEM2_Backrest_100_Cushion_67_1 +#define SMFR_ActVentBalance_Stat_SMFR_MEM2_Backrest_100_Cushion_67_1 (5) +#endif + +#ifndef SMFR_ActVentBalance_Stat_SMFR_MEM2_Backrest_100_Cushion_100_0 +#define SMFR_ActVentBalance_Stat_SMFR_MEM2_Backrest_100_Cushion_100_0 (4) +#endif + +#ifndef SMFR_ActVentBalance_Stat_SMFR_MEM2_Backrest_67_Cushion_100_1 +#define SMFR_ActVentBalance_Stat_SMFR_MEM2_Backrest_67_Cushion_100_1 (3) +#endif + +#ifndef SMFR_ActVentBalance_Stat_SMFR_MEM2_Backrest_33_Cushion_100_2 +#define SMFR_ActVentBalance_Stat_SMFR_MEM2_Backrest_33_Cushion_100_2 (2) +#endif + +#ifndef SMFR_ActVentBalance_Stat_SMFR_MEM2_No_action +#define SMFR_ActVentBalance_Stat_SMFR_MEM2_No_action (0) +#endif + +#ifndef SMFR_ActVentBalance_Stat_SMFR_MEM2_Backrest_00_Cushion_100_3 +#define SMFR_ActVentBalance_Stat_SMFR_MEM2_Backrest_00_Cushion_100_3 (1) +#endif + +// signal: @SMFR_PosnPrsnSeatCS_Val_ro +#define CANDB_SMFR_PosnPrsnSeatCS_Val_ro_CovFactor (0.394) +#define CANDB_SMFR_PosnPrsnSeatCS_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.394)) ) +#define CANDB_SMFR_PosnPrsnSeatCS_Val_ro_fromS(x) ( (((x) * (0.394)) + (0.0)) ) +// signal: @SMFR_PosnPrsnSeatLSH_Val_ro +#define CANDB_SMFR_PosnPrsnSeatLSH_Val_ro_CovFactor (0.394) +#define CANDB_SMFR_PosnPrsnSeatLSH_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.394)) ) +#define CANDB_SMFR_PosnPrsnSeatLSH_Val_ro_fromS(x) ( (((x) * (0.394)) + (0.0)) ) +// signal: @SMFR_PosnPrsnSeatLSD_Val_ro +#define CANDB_SMFR_PosnPrsnSeatLSD_Val_ro_CovFactor (0.394) +#define CANDB_SMFR_PosnPrsnSeatLSD_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.394)) ) +#define CANDB_SMFR_PosnPrsnSeatLSD_Val_ro_fromS(x) ( (((x) * (0.394)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // SMFR current seat back rest head inclination position. + uint8_t SMFR_PosnActSeatBRHI_Val_ro; // Bits= 8 Factor= 0.1 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFR_PosnActSeatBRHI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFR current seat head rest height inclination position. + uint8_t SMFR_PosnActSeatHRHI_Val_ro; // Bits= 8 Factor= 0.71 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFR_PosnActSeatHRHI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFR current seat back rest inclination position. + uint8_t SMFR_PosnActSeatBRI_Val_ro; // Bits= 8 Factor= 0.1 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFR_PosnActSeatBRI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFR current seat heat balance + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 0 : "No action" + // 1 : "Backrest 00%, Cushion 100%: -3" + uint8_t SMFR_ActHeatBalance_Val : 3; // Bits= 3 + + // SMFR current seat ventilation balance + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 0 : "No action" + // 1 : "Backrest 00%, Cushion 100%: -3" + uint8_t SMFR_ActVentBalance_Stat : 3; // Bits= 3 + + // SMFR current seat cushion support position + uint8_t SMFR_PosnPrsnSeatCS_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFR_PosnPrsnSeatCS_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFR current seat Longitudinal Surface Height + uint8_t SMFR_PosnPrsnSeatLSH_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFR_PosnPrsnSeatLSH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFR current seat Longitudinal Surface Depth + uint8_t SMFR_PosnPrsnSeatLSD_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFR_PosnPrsnSeatLSD_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#else + + // SMFR current seat back rest head inclination position. + uint8_t SMFR_PosnActSeatBRHI_Val_ro; // Bits= 8 Factor= 0.1 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFR_PosnActSeatBRHI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFR current seat head rest height inclination position. + uint8_t SMFR_PosnActSeatHRHI_Val_ro; // Bits= 8 Factor= 0.71 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFR_PosnActSeatHRHI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFR current seat back rest inclination position. + uint8_t SMFR_PosnActSeatBRI_Val_ro; // Bits= 8 Factor= 0.1 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFR_PosnActSeatBRI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFR current seat heat balance + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 0 : "No action" + // 1 : "Backrest 00%, Cushion 100%: -3" + uint8_t SMFR_ActHeatBalance_Val; // Bits= 3 + + // SMFR current seat ventilation balance + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 0 : "No action" + // 1 : "Backrest 00%, Cushion 100%: -3" + uint8_t SMFR_ActVentBalance_Stat; // Bits= 3 + + // SMFR current seat cushion support position + uint8_t SMFR_PosnPrsnSeatCS_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFR_PosnPrsnSeatCS_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFR current seat Longitudinal Surface Height + uint8_t SMFR_PosnPrsnSeatLSH_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFR_PosnPrsnSeatLSH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMFR current seat Longitudinal Surface Depth + uint8_t SMFR_PosnPrsnSeatLSD_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMFR_PosnPrsnSeatLSD_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} SMFR_MEM2_t; + +// def @BCM_MEM_SMFR2 CAN Message (1338 0x53a) +#define BCM_MEM_SMFR2_IDE (0U) +#define BCM_MEM_SMFR2_DLC (8U) +#define BCM_MEM_SMFR2_CANID (0x53aU) +// signal: @BCM_FRMemPosnActSeatBRHI_Val_ro +#define CANDB_BCM_FRMemPosnActSeatBRHI_Val_ro_CovFactor (0.1) +#define CANDB_BCM_FRMemPosnActSeatBRHI_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_BCM_FRMemPosnActSeatBRHI_Val_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @BCM_FRMemPosnActSeatHRHI_Val_ro +#define CANDB_BCM_FRMemPosnActSeatHRHI_Val_ro_CovFactor (0.71) +#define CANDB_BCM_FRMemPosnActSeatHRHI_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.71)) ) +#define CANDB_BCM_FRMemPosnActSeatHRHI_Val_ro_fromS(x) ( (((x) * (0.71)) + (0.0)) ) +// signal: @BCM_FRMemPosnActSeatBRI_Val_ro +#define CANDB_BCM_FRMemPosnActSeatBRI_Val_ro_CovFactor (0.1) +#define CANDB_BCM_FRMemPosnActSeatBRI_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_BCM_FRMemPosnActSeatBRI_Val_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +// Value tables for @BCM_FRMemActHeatBalance_Val signal + +#ifndef BCM_FRMemActHeatBalance_Val_BCM_MEM_SMFR2_Backrest_100_Cushion_0_3 +#define BCM_FRMemActHeatBalance_Val_BCM_MEM_SMFR2_Backrest_100_Cushion_0_3 (7) +#endif + +#ifndef BCM_FRMemActHeatBalance_Val_BCM_MEM_SMFR2_Backrest_100_Cushion_33_2 +#define BCM_FRMemActHeatBalance_Val_BCM_MEM_SMFR2_Backrest_100_Cushion_33_2 (6) +#endif + +#ifndef BCM_FRMemActHeatBalance_Val_BCM_MEM_SMFR2_Backrest_100_Cushion_67_1 +#define BCM_FRMemActHeatBalance_Val_BCM_MEM_SMFR2_Backrest_100_Cushion_67_1 (5) +#endif + +#ifndef BCM_FRMemActHeatBalance_Val_BCM_MEM_SMFR2_Backrest_100_Cushion_100_0 +#define BCM_FRMemActHeatBalance_Val_BCM_MEM_SMFR2_Backrest_100_Cushion_100_0 (4) +#endif + +#ifndef BCM_FRMemActHeatBalance_Val_BCM_MEM_SMFR2_Backrest_67_Cushion_100_1 +#define BCM_FRMemActHeatBalance_Val_BCM_MEM_SMFR2_Backrest_67_Cushion_100_1 (3) +#endif + +#ifndef BCM_FRMemActHeatBalance_Val_BCM_MEM_SMFR2_Backrest_33_Cushion_100_2 +#define BCM_FRMemActHeatBalance_Val_BCM_MEM_SMFR2_Backrest_33_Cushion_100_2 (2) +#endif + +#ifndef BCM_FRMemActHeatBalance_Val_BCM_MEM_SMFR2_Backrest_0_Cushion_100_3 +#define BCM_FRMemActHeatBalance_Val_BCM_MEM_SMFR2_Backrest_0_Cushion_100_3 (1) +#endif + +#ifndef BCM_FRMemActHeatBalance_Val_BCM_MEM_SMFR2_No_action +#define BCM_FRMemActHeatBalance_Val_BCM_MEM_SMFR2_No_action (0) +#endif + + +// Value tables for @BCM_FRMemActVentBalance_Val signal + +#ifndef BCM_FRMemActVentBalance_Val_BCM_MEM_SMFR2_Backrest_100_Cushion_0_3 +#define BCM_FRMemActVentBalance_Val_BCM_MEM_SMFR2_Backrest_100_Cushion_0_3 (7) +#endif + +#ifndef BCM_FRMemActVentBalance_Val_BCM_MEM_SMFR2_Backrest_100_Cushion_33_2 +#define BCM_FRMemActVentBalance_Val_BCM_MEM_SMFR2_Backrest_100_Cushion_33_2 (6) +#endif + +#ifndef BCM_FRMemActVentBalance_Val_BCM_MEM_SMFR2_Backrest_100_Cushion_67_1 +#define BCM_FRMemActVentBalance_Val_BCM_MEM_SMFR2_Backrest_100_Cushion_67_1 (5) +#endif + +#ifndef BCM_FRMemActVentBalance_Val_BCM_MEM_SMFR2_Backrest_100_Cushion_100_0 +#define BCM_FRMemActVentBalance_Val_BCM_MEM_SMFR2_Backrest_100_Cushion_100_0 (4) +#endif + +#ifndef BCM_FRMemActVentBalance_Val_BCM_MEM_SMFR2_Backrest_67_Cushion_100_1 +#define BCM_FRMemActVentBalance_Val_BCM_MEM_SMFR2_Backrest_67_Cushion_100_1 (3) +#endif + +#ifndef BCM_FRMemActVentBalance_Val_BCM_MEM_SMFR2_Backrest_33_Cushion_100_2 +#define BCM_FRMemActVentBalance_Val_BCM_MEM_SMFR2_Backrest_33_Cushion_100_2 (2) +#endif + +#ifndef BCM_FRMemActVentBalance_Val_BCM_MEM_SMFR2_Backrest_0_Cushion_100_3 +#define BCM_FRMemActVentBalance_Val_BCM_MEM_SMFR2_Backrest_0_Cushion_100_3 (1) +#endif + +#ifndef BCM_FRMemActVentBalance_Val_BCM_MEM_SMFR2_No_action +#define BCM_FRMemActVentBalance_Val_BCM_MEM_SMFR2_No_action (0) +#endif + +// signal: @BCM_FRMemPosnPrsnSeatCS_Val_ro +#define CANDB_BCM_FRMemPosnPrsnSeatCS_Val_ro_CovFactor (0.394) +#define CANDB_BCM_FRMemPosnPrsnSeatCS_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.394)) ) +#define CANDB_BCM_FRMemPosnPrsnSeatCS_Val_ro_fromS(x) ( (((x) * (0.394)) + (0.0)) ) +// signal: @BCM_FRMemPosnPrsnSeatLSH_Val_ro +#define CANDB_BCM_FRMemPosnPrsnSeatLSH_Val_ro_CovFactor (0.394) +#define CANDB_BCM_FRMemPosnPrsnSeatLSH_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.394)) ) +#define CANDB_BCM_FRMemPosnPrsnSeatLSH_Val_ro_fromS(x) ( (((x) * (0.394)) + (0.0)) ) +// signal: @BCM_FRMemPosnPrsnSeatLSD_Val_ro +#define CANDB_BCM_FRMemPosnPrsnSeatLSD_Val_ro_CovFactor (0.394) +#define CANDB_BCM_FRMemPosnPrsnSeatLSD_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.394)) ) +#define CANDB_BCM_FRMemPosnPrsnSeatLSD_Val_ro_fromS(x) ( (((x) * (0.394)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Stored for SMFR seat back rest head inclination position. + uint8_t BCM_FRMemPosnActSeatBRHI_Val_ro; // Bits= 8 Factor= 0.1 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FRMemPosnActSeatBRHI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMFR seat head rest height inclination position. + uint8_t BCM_FRMemPosnActSeatHRHI_Val_ro; // Bits= 8 Factor= 0.71 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FRMemPosnActSeatHRHI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMFR seat back rest inclination position. + uint8_t BCM_FRMemPosnActSeatBRI_Val_ro; // Bits= 8 Factor= 0.1 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FRMemPosnActSeatBRI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMFR seat heat balance + // 7 : "Backrest 100%, Cushion 0%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 0%, Cushion 100%: -3" + // 0 : "No action" + uint8_t BCM_FRMemActHeatBalance_Val : 3; // Bits= 3 + + // Stored for SMFR seat ventilation balance + // 7 : "Backrest 100%, Cushion 0%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 0%, Cushion 100%: -3" + // 0 : "No action" + uint8_t BCM_FRMemActVentBalance_Val : 3; // Bits= 3 + + // Stored for SMFR seat cushion support position + uint8_t BCM_FRMemPosnPrsnSeatCS_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FRMemPosnPrsnSeatCS_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Srored for SMFR seat Longitudinal Surface Height + uint8_t BCM_FRMemPosnPrsnSeatLSH_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FRMemPosnPrsnSeatLSH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Srored for SMFR seat Longitudinal Surface Depth + uint8_t BCM_FRMemPosnPrsnSeatLSD_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FRMemPosnPrsnSeatLSD_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#else + + // Stored for SMFR seat back rest head inclination position. + uint8_t BCM_FRMemPosnActSeatBRHI_Val_ro; // Bits= 8 Factor= 0.1 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FRMemPosnActSeatBRHI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMFR seat head rest height inclination position. + uint8_t BCM_FRMemPosnActSeatHRHI_Val_ro; // Bits= 8 Factor= 0.71 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FRMemPosnActSeatHRHI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMFR seat back rest inclination position. + uint8_t BCM_FRMemPosnActSeatBRI_Val_ro; // Bits= 8 Factor= 0.1 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FRMemPosnActSeatBRI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMFR seat heat balance + // 7 : "Backrest 100%, Cushion 0%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 0%, Cushion 100%: -3" + // 0 : "No action" + uint8_t BCM_FRMemActHeatBalance_Val; // Bits= 3 + + // Stored for SMFR seat ventilation balance + // 7 : "Backrest 100%, Cushion 0%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 0%, Cushion 100%: -3" + // 0 : "No action" + uint8_t BCM_FRMemActVentBalance_Val; // Bits= 3 + + // Stored for SMFR seat cushion support position + uint8_t BCM_FRMemPosnPrsnSeatCS_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FRMemPosnPrsnSeatCS_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Srored for SMFR seat Longitudinal Surface Height + uint8_t BCM_FRMemPosnPrsnSeatLSH_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FRMemPosnPrsnSeatLSH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Srored for SMFR seat Longitudinal Surface Depth + uint8_t BCM_FRMemPosnPrsnSeatLSD_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_FRMemPosnPrsnSeatLSD_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} BCM_MEM_SMFR2_t; + +// def @SMRL_MEM1 CAN Message (1339 0x53b) +#define SMRL_MEM1_IDE (0U) +#define SMRL_MEM1_DLC (8U) +#define SMRL_MEM1_CANID (0x53bU) +// signal: @SMRL_PosnActSeatI_Val_ro +#define CANDB_SMRL_PosnActSeatI_Val_ro_CovFactor (0.125) +#define CANDB_SMRL_PosnActSeatI_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.125)) ) +#define CANDB_SMRL_PosnActSeatI_Val_ro_fromS(x) ( (((x) * (0.125)) + (0.0)) ) +// signal: @SMRL_PosnActSeatBRW_Val_ro +#define CANDB_SMRL_PosnActSeatBRW_Val_ro_CovFactor (1) +#define CANDB_SMRL_PosnActSeatBRW_Val_ro_toS(x) ( (uint8_t) ((x) - (300)) ) +#define CANDB_SMRL_PosnActSeatBRW_Val_ro_fromS(x) ( ((x) + (300)) ) +// signal: @SMRL_PosnActSeatFRH_Val_ro +#define CANDB_SMRL_PosnActSeatFRH_Val_ro_CovFactor (0.8) +#define CANDB_SMRL_PosnActSeatFRH_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.8)) ) +#define CANDB_SMRL_PosnActSeatFRH_Val_ro_fromS(x) ( (((x) * (0.8)) + (0.0)) ) +// signal: @SMRL_PosnActSeatFRL_Val_ro +#define CANDB_SMRL_PosnActSeatFRL_Val_ro_CovFactor (0.25) +#define CANDB_SMRL_PosnActSeatFRL_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.25)) ) +#define CANDB_SMRL_PosnActSeatFRL_Val_ro_fromS(x) ( (((x) * (0.25)) + (0.0)) ) +// signal: @SMRL_PosnActSeatH_Val_ro +#define CANDB_SMRL_PosnActSeatH_Val_ro_CovFactor (0.8) +#define CANDB_SMRL_PosnActSeatH_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.8)) ) +#define CANDB_SMRL_PosnActSeatH_Val_ro_fromS(x) ( (((x) * (0.8)) + (0.0)) ) +// signal: @SMRL_PosnActSeatHRH_Val_ro +#define CANDB_SMRL_PosnActSeatHRH_Val_ro_CovFactor (0.5) +#define CANDB_SMRL_PosnActSeatHRH_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.5)) ) +#define CANDB_SMRL_PosnActSeatHRH_Val_ro_fromS(x) ( (((x) * (0.5)) + (0.0)) ) +// signal: @SMRL_PosnActSeatL_Val_ro +#define CANDB_SMRL_PosnActSeatL_Val_ro_CovFactor (0.8) +#define CANDB_SMRL_PosnActSeatL_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.8)) ) +#define CANDB_SMRL_PosnActSeatL_Val_ro_fromS(x) ( (((x) * (0.8)) + (0.0)) ) +// signal: @SMRL_PosnActSeatSL_Val_ro +#define CANDB_SMRL_PosnActSeatSL_Val_ro_CovFactor (0.8) +#define CANDB_SMRL_PosnActSeatSL_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.8)) ) +#define CANDB_SMRL_PosnActSeatSL_Val_ro_fromS(x) ( (((x) * (0.8)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // SMRL current seat inclination position. + uint8_t SMRL_PosnActSeatI_Val_ro; // Bits= 8 Factor= 0.125 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRL_PosnActSeatI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRL current seat back rest width position. + uint8_t SMRL_PosnActSeatBRW_Val_ro; // Bits= 8 Offset= 300 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + uint16_t SMRL_PosnActSeatBRW_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRL current seat foot rest height position. + uint8_t SMRL_PosnActSeatFRH_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRL_PosnActSeatFRH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRL current seat foot rest longitudinal position. + uint8_t SMRL_PosnActSeatFRL_Val_ro; // Bits= 8 Factor= 0.25 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRL_PosnActSeatFRL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRL current seat height position. + uint8_t SMRL_PosnActSeatH_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRL_PosnActSeatH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRL current seat head rest height position. + uint8_t SMRL_PosnActSeatHRH_Val_ro; // Bits= 8 Factor= 0.5 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRL_PosnActSeatHRH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRL current seat longitudinal position. + uint8_t SMRL_PosnActSeatL_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRL_PosnActSeatL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRL current seat surface longitudinal position. + uint8_t SMRL_PosnActSeatSL_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRL_PosnActSeatSL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#else + + // SMRL current seat inclination position. + uint8_t SMRL_PosnActSeatI_Val_ro; // Bits= 8 Factor= 0.125 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRL_PosnActSeatI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRL current seat back rest width position. + uint8_t SMRL_PosnActSeatBRW_Val_ro; // Bits= 8 Offset= 300 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + uint16_t SMRL_PosnActSeatBRW_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRL current seat foot rest height position. + uint8_t SMRL_PosnActSeatFRH_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRL_PosnActSeatFRH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRL current seat foot rest longitudinal position. + uint8_t SMRL_PosnActSeatFRL_Val_ro; // Bits= 8 Factor= 0.25 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRL_PosnActSeatFRL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRL current seat height position. + uint8_t SMRL_PosnActSeatH_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRL_PosnActSeatH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRL current seat head rest height position. + uint8_t SMRL_PosnActSeatHRH_Val_ro; // Bits= 8 Factor= 0.5 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRL_PosnActSeatHRH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRL current seat longitudinal position. + uint8_t SMRL_PosnActSeatL_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRL_PosnActSeatL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRL current seat surface longitudinal position. + uint8_t SMRL_PosnActSeatSL_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRL_PosnActSeatSL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} SMRL_MEM1_t; + +// def @BCM_MEM_SMRL1 CAN Message (1340 0x53c) +#define BCM_MEM_SMRL1_IDE (0U) +#define BCM_MEM_SMRL1_DLC (8U) +#define BCM_MEM_SMRL1_CANID (0x53cU) +// signal: @BCM_RLMemPosnActSeatI_Val_ro +#define CANDB_BCM_RLMemPosnActSeatI_Val_ro_CovFactor (0.125) +#define CANDB_BCM_RLMemPosnActSeatI_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.125)) ) +#define CANDB_BCM_RLMemPosnActSeatI_Val_ro_fromS(x) ( (((x) * (0.125)) + (0.0)) ) +// signal: @BCM_RLMemPosnActSeatBRW_Val_ro +#define CANDB_BCM_RLMemPosnActSeatBRW_Val_ro_CovFactor (1) +#define CANDB_BCM_RLMemPosnActSeatBRW_Val_ro_toS(x) ( (uint8_t) ((x) - (300)) ) +#define CANDB_BCM_RLMemPosnActSeatBRW_Val_ro_fromS(x) ( ((x) + (300)) ) +// signal: @BCM_RLMemPosnActSeatFRH_Val_ro +#define CANDB_BCM_RLMemPosnActSeatFRH_Val_ro_CovFactor (0.8) +#define CANDB_BCM_RLMemPosnActSeatFRH_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.8)) ) +#define CANDB_BCM_RLMemPosnActSeatFRH_Val_ro_fromS(x) ( (((x) * (0.8)) + (0.0)) ) +// signal: @BCM_RLMemPosnActSeatFRL_Val_ro +#define CANDB_BCM_RLMemPosnActSeatFRL_Val_ro_CovFactor (0.25) +#define CANDB_BCM_RLMemPosnActSeatFRL_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.25)) ) +#define CANDB_BCM_RLMemPosnActSeatFRL_Val_ro_fromS(x) ( (((x) * (0.25)) + (0.0)) ) +// signal: @BCM_RLMemPosnActSeatH_Val_ro +#define CANDB_BCM_RLMemPosnActSeatH_Val_ro_CovFactor (0.8) +#define CANDB_BCM_RLMemPosnActSeatH_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.8)) ) +#define CANDB_BCM_RLMemPosnActSeatH_Val_ro_fromS(x) ( (((x) * (0.8)) + (0.0)) ) +// signal: @BCM_RLMemPosnActSeatHRH_Val_ro +#define CANDB_BCM_RLMemPosnActSeatHRH_Val_ro_CovFactor (0.5) +#define CANDB_BCM_RLMemPosnActSeatHRH_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.5)) ) +#define CANDB_BCM_RLMemPosnActSeatHRH_Val_ro_fromS(x) ( (((x) * (0.5)) + (0.0)) ) +// signal: @BCM_RLMemPosnActSeatL_Val_ro +#define CANDB_BCM_RLMemPosnActSeatL_Val_ro_CovFactor (0.8) +#define CANDB_BCM_RLMemPosnActSeatL_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.8)) ) +#define CANDB_BCM_RLMemPosnActSeatL_Val_ro_fromS(x) ( (((x) * (0.8)) + (0.0)) ) +// signal: @BCM_RLMemPosnActSeatSL_Val_ro +#define CANDB_BCM_RLMemPosnActSeatSL_Val_ro_CovFactor (0.8) +#define CANDB_BCM_RLMemPosnActSeatSL_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.8)) ) +#define CANDB_BCM_RLMemPosnActSeatSL_Val_ro_fromS(x) ( (((x) * (0.8)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Stored for SMRL seat inclination position + uint8_t BCM_RLMemPosnActSeatI_Val_ro; // Bits= 8 Factor= 0.125 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RLMemPosnActSeatI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMRL seat back rest width position + uint8_t BCM_RLMemPosnActSeatBRW_Val_ro; // Bits= 8 Offset= 300 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + uint16_t BCM_RLMemPosnActSeatBRW_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMRL seat foot rest height position + uint8_t BCM_RLMemPosnActSeatFRH_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RLMemPosnActSeatFRH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMRL seat foot rest longitudinal position + uint8_t BCM_RLMemPosnActSeatFRL_Val_ro; // Bits= 8 Factor= 0.25 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RLMemPosnActSeatFRL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMRL seat height position + uint8_t BCM_RLMemPosnActSeatH_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RLMemPosnActSeatH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMRL seat head rest height position + uint8_t BCM_RLMemPosnActSeatHRH_Val_ro; // Bits= 8 Factor= 0.5 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RLMemPosnActSeatHRH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMRL seat longitudinal position + uint8_t BCM_RLMemPosnActSeatL_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RLMemPosnActSeatL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMRL seat surface longitudinal position. + uint8_t BCM_RLMemPosnActSeatSL_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RLMemPosnActSeatSL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#else + + // Stored for SMRL seat inclination position + uint8_t BCM_RLMemPosnActSeatI_Val_ro; // Bits= 8 Factor= 0.125 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RLMemPosnActSeatI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMRL seat back rest width position + uint8_t BCM_RLMemPosnActSeatBRW_Val_ro; // Bits= 8 Offset= 300 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + uint16_t BCM_RLMemPosnActSeatBRW_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMRL seat foot rest height position + uint8_t BCM_RLMemPosnActSeatFRH_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RLMemPosnActSeatFRH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMRL seat foot rest longitudinal position + uint8_t BCM_RLMemPosnActSeatFRL_Val_ro; // Bits= 8 Factor= 0.25 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RLMemPosnActSeatFRL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMRL seat height position + uint8_t BCM_RLMemPosnActSeatH_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RLMemPosnActSeatH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMRL seat head rest height position + uint8_t BCM_RLMemPosnActSeatHRH_Val_ro; // Bits= 8 Factor= 0.5 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RLMemPosnActSeatHRH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMRL seat longitudinal position + uint8_t BCM_RLMemPosnActSeatL_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RLMemPosnActSeatL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMRL seat surface longitudinal position. + uint8_t BCM_RLMemPosnActSeatSL_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RLMemPosnActSeatSL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} BCM_MEM_SMRL1_t; + +// def @SMRL_MEM2 CAN Message (1341 0x53d) +#define SMRL_MEM2_IDE (0U) +#define SMRL_MEM2_DLC (8U) +#define SMRL_MEM2_CANID (0x53dU) +// signal: @SMRL_PosnActSeatBRHI_Val_ro +#define CANDB_SMRL_PosnActSeatBRHI_Val_ro_CovFactor (0.1) +#define CANDB_SMRL_PosnActSeatBRHI_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_SMRL_PosnActSeatBRHI_Val_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @SMRL_PosnActSeatHRHI_Val_ro +#define CANDB_SMRL_PosnActSeatHRHI_Val_ro_CovFactor (0.71) +#define CANDB_SMRL_PosnActSeatHRHI_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.71)) ) +#define CANDB_SMRL_PosnActSeatHRHI_Val_ro_fromS(x) ( (((x) * (0.71)) + (0.0)) ) +// signal: @SMRL_PosnActSeatBRI_Val_ro +#define CANDB_SMRL_PosnActSeatBRI_Val_ro_CovFactor (0.1) +#define CANDB_SMRL_PosnActSeatBRI_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_SMRL_PosnActSeatBRI_Val_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +// Value tables for @SMRL_ActHeatBalance_Stat signal + +#ifndef SMRL_ActHeatBalance_Stat_SMRL_MEM2_Backrest_100_Cushion_00_3 +#define SMRL_ActHeatBalance_Stat_SMRL_MEM2_Backrest_100_Cushion_00_3 (7) +#endif + +#ifndef SMRL_ActHeatBalance_Stat_SMRL_MEM2_Backrest_100_Cushion_33_2 +#define SMRL_ActHeatBalance_Stat_SMRL_MEM2_Backrest_100_Cushion_33_2 (6) +#endif + +#ifndef SMRL_ActHeatBalance_Stat_SMRL_MEM2_Backrest_100_Cushion_67_1 +#define SMRL_ActHeatBalance_Stat_SMRL_MEM2_Backrest_100_Cushion_67_1 (5) +#endif + +#ifndef SMRL_ActHeatBalance_Stat_SMRL_MEM2_Backrest_100_Cushion_100_0 +#define SMRL_ActHeatBalance_Stat_SMRL_MEM2_Backrest_100_Cushion_100_0 (4) +#endif + +#ifndef SMRL_ActHeatBalance_Stat_SMRL_MEM2_Backrest_67_Cushion_100_1 +#define SMRL_ActHeatBalance_Stat_SMRL_MEM2_Backrest_67_Cushion_100_1 (3) +#endif + +#ifndef SMRL_ActHeatBalance_Stat_SMRL_MEM2_Backrest_33_Cushion_100_2 +#define SMRL_ActHeatBalance_Stat_SMRL_MEM2_Backrest_33_Cushion_100_2 (2) +#endif + +#ifndef SMRL_ActHeatBalance_Stat_SMRL_MEM2_No_action +#define SMRL_ActHeatBalance_Stat_SMRL_MEM2_No_action (0) +#endif + +#ifndef SMRL_ActHeatBalance_Stat_SMRL_MEM2_Backrest_00_Cushion_100_3 +#define SMRL_ActHeatBalance_Stat_SMRL_MEM2_Backrest_00_Cushion_100_3 (1) +#endif + + +// Value tables for @SMRL_ActVentBalance_Stat signal + +#ifndef SMRL_ActVentBalance_Stat_SMRL_MEM2_Backrest_100_Cushion_00_3 +#define SMRL_ActVentBalance_Stat_SMRL_MEM2_Backrest_100_Cushion_00_3 (7) +#endif + +#ifndef SMRL_ActVentBalance_Stat_SMRL_MEM2_Backrest_100_Cushion_33_2 +#define SMRL_ActVentBalance_Stat_SMRL_MEM2_Backrest_100_Cushion_33_2 (6) +#endif + +#ifndef SMRL_ActVentBalance_Stat_SMRL_MEM2_Backrest_100_Cushion_67_1 +#define SMRL_ActVentBalance_Stat_SMRL_MEM2_Backrest_100_Cushion_67_1 (5) +#endif + +#ifndef SMRL_ActVentBalance_Stat_SMRL_MEM2_Backrest_100_Cushion_100_0 +#define SMRL_ActVentBalance_Stat_SMRL_MEM2_Backrest_100_Cushion_100_0 (4) +#endif + +#ifndef SMRL_ActVentBalance_Stat_SMRL_MEM2_Backrest_67_Cushion_100_1 +#define SMRL_ActVentBalance_Stat_SMRL_MEM2_Backrest_67_Cushion_100_1 (3) +#endif + +#ifndef SMRL_ActVentBalance_Stat_SMRL_MEM2_Backrest_33_Cushion_100_2 +#define SMRL_ActVentBalance_Stat_SMRL_MEM2_Backrest_33_Cushion_100_2 (2) +#endif + +#ifndef SMRL_ActVentBalance_Stat_SMRL_MEM2_No_action +#define SMRL_ActVentBalance_Stat_SMRL_MEM2_No_action (0) +#endif + +#ifndef SMRL_ActVentBalance_Stat_SMRL_MEM2_Backrest_00_Cushion_100_3 +#define SMRL_ActVentBalance_Stat_SMRL_MEM2_Backrest_00_Cushion_100_3 (1) +#endif + +// signal: @SMRL_PosnPrsnSeatCS_Val_ro +#define CANDB_SMRL_PosnPrsnSeatCS_Val_ro_CovFactor (0.394) +#define CANDB_SMRL_PosnPrsnSeatCS_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.394)) ) +#define CANDB_SMRL_PosnPrsnSeatCS_Val_ro_fromS(x) ( (((x) * (0.394)) + (0.0)) ) +// signal: @SMRL_PosnPrsnSeatLSH_Val_ro +#define CANDB_SMRL_PosnPrsnSeatLSH_Val_ro_CovFactor (0.394) +#define CANDB_SMRL_PosnPrsnSeatLSH_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.394)) ) +#define CANDB_SMRL_PosnPrsnSeatLSH_Val_ro_fromS(x) ( (((x) * (0.394)) + (0.0)) ) +// signal: @SMRL_PosnPrsnSeatLSD_Val_ro +#define CANDB_SMRL_PosnPrsnSeatLSD_Val_ro_CovFactor (0.394) +#define CANDB_SMRL_PosnPrsnSeatLSD_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.394)) ) +#define CANDB_SMRL_PosnPrsnSeatLSD_Val_ro_fromS(x) ( (((x) * (0.394)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // SMRL current seat back rest head inclination position. + uint8_t SMRL_PosnActSeatBRHI_Val_ro; // Bits= 8 Factor= 0.1 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRL_PosnActSeatBRHI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRL current seat head rest height inclination position. + uint8_t SMRL_PosnActSeatHRHI_Val_ro; // Bits= 8 Factor= 0.71 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRL_PosnActSeatHRHI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRL current seat back rest inclination position. + uint8_t SMRL_PosnActSeatBRI_Val_ro; // Bits= 8 Factor= 0.1 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRL_PosnActSeatBRI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRL current seat heat balance + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 0 : "No action" + // 1 : "Backrest 00%, Cushion 100%: -3" + uint8_t SMRL_ActHeatBalance_Stat : 3; // Bits= 3 + + // SMRL current seat ventilation balance + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 0 : "No action" + // 1 : "Backrest 00%, Cushion 100%: -3" + uint8_t SMRL_ActVentBalance_Stat : 3; // Bits= 3 + + // SMRL current seat cushion support position + uint8_t SMRL_PosnPrsnSeatCS_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRL_PosnPrsnSeatCS_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRL current seat Longitudinal Surface Height + uint8_t SMRL_PosnPrsnSeatLSH_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRL_PosnPrsnSeatLSH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRL current seat Longitudinal Surface Depth + uint8_t SMRL_PosnPrsnSeatLSD_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRL_PosnPrsnSeatLSD_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#else + + // SMRL current seat back rest head inclination position. + uint8_t SMRL_PosnActSeatBRHI_Val_ro; // Bits= 8 Factor= 0.1 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRL_PosnActSeatBRHI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRL current seat head rest height inclination position. + uint8_t SMRL_PosnActSeatHRHI_Val_ro; // Bits= 8 Factor= 0.71 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRL_PosnActSeatHRHI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRL current seat back rest inclination position. + uint8_t SMRL_PosnActSeatBRI_Val_ro; // Bits= 8 Factor= 0.1 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRL_PosnActSeatBRI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRL current seat heat balance + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 0 : "No action" + // 1 : "Backrest 00%, Cushion 100%: -3" + uint8_t SMRL_ActHeatBalance_Stat; // Bits= 3 + + // SMRL current seat ventilation balance + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 0 : "No action" + // 1 : "Backrest 00%, Cushion 100%: -3" + uint8_t SMRL_ActVentBalance_Stat; // Bits= 3 + + // SMRL current seat cushion support position + uint8_t SMRL_PosnPrsnSeatCS_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRL_PosnPrsnSeatCS_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRL current seat Longitudinal Surface Height + uint8_t SMRL_PosnPrsnSeatLSH_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRL_PosnPrsnSeatLSH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRL current seat Longitudinal Surface Depth + uint8_t SMRL_PosnPrsnSeatLSD_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRL_PosnPrsnSeatLSD_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} SMRL_MEM2_t; + +// def @BCM_MEM_SMRL2 CAN Message (1342 0x53e) +#define BCM_MEM_SMRL2_IDE (0U) +#define BCM_MEM_SMRL2_DLC (8U) +#define BCM_MEM_SMRL2_CANID (0x53eU) +// signal: @BCM_RLMemPosnActSeatBRHI_Val_ro +#define CANDB_BCM_RLMemPosnActSeatBRHI_Val_ro_CovFactor (0.1) +#define CANDB_BCM_RLMemPosnActSeatBRHI_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_BCM_RLMemPosnActSeatBRHI_Val_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @BCM_RLMemPosnActSeatHRHI_Val_ro +#define CANDB_BCM_RLMemPosnActSeatHRHI_Val_ro_CovFactor (0.71) +#define CANDB_BCM_RLMemPosnActSeatHRHI_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.71)) ) +#define CANDB_BCM_RLMemPosnActSeatHRHI_Val_ro_fromS(x) ( (((x) * (0.71)) + (0.0)) ) +// signal: @BCM_RLMemPosnActSeatBRI_Val_ro +#define CANDB_BCM_RLMemPosnActSeatBRI_Val_ro_CovFactor (0.1) +#define CANDB_BCM_RLMemPosnActSeatBRI_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_BCM_RLMemPosnActSeatBRI_Val_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +// Value tables for @BCM_RLMemActHeatBalance_Val signal + +#ifndef BCM_RLMemActHeatBalance_Val_BCM_MEM_SMRL2_Backrest_100_Cushion_0_3 +#define BCM_RLMemActHeatBalance_Val_BCM_MEM_SMRL2_Backrest_100_Cushion_0_3 (7) +#endif + +#ifndef BCM_RLMemActHeatBalance_Val_BCM_MEM_SMRL2_Backrest_100_Cushion_33_2 +#define BCM_RLMemActHeatBalance_Val_BCM_MEM_SMRL2_Backrest_100_Cushion_33_2 (6) +#endif + +#ifndef BCM_RLMemActHeatBalance_Val_BCM_MEM_SMRL2_Backrest_100_Cushion_67_1 +#define BCM_RLMemActHeatBalance_Val_BCM_MEM_SMRL2_Backrest_100_Cushion_67_1 (5) +#endif + +#ifndef BCM_RLMemActHeatBalance_Val_BCM_MEM_SMRL2_Backrest_100_Cushion_100_0 +#define BCM_RLMemActHeatBalance_Val_BCM_MEM_SMRL2_Backrest_100_Cushion_100_0 (4) +#endif + +#ifndef BCM_RLMemActHeatBalance_Val_BCM_MEM_SMRL2_Backrest_67_Cushion_100_1 +#define BCM_RLMemActHeatBalance_Val_BCM_MEM_SMRL2_Backrest_67_Cushion_100_1 (3) +#endif + +#ifndef BCM_RLMemActHeatBalance_Val_BCM_MEM_SMRL2_Backrest_33_Cushion_100_2 +#define BCM_RLMemActHeatBalance_Val_BCM_MEM_SMRL2_Backrest_33_Cushion_100_2 (2) +#endif + +#ifndef BCM_RLMemActHeatBalance_Val_BCM_MEM_SMRL2_Backrest_0_Cushion_100_3 +#define BCM_RLMemActHeatBalance_Val_BCM_MEM_SMRL2_Backrest_0_Cushion_100_3 (1) +#endif + +#ifndef BCM_RLMemActHeatBalance_Val_BCM_MEM_SMRL2_No_action +#define BCM_RLMemActHeatBalance_Val_BCM_MEM_SMRL2_No_action (0) +#endif + + +// Value tables for @BCM_RLMemActVentBalance_Val signal + +#ifndef BCM_RLMemActVentBalance_Val_BCM_MEM_SMRL2_Backrest_100_Cushion_0_3 +#define BCM_RLMemActVentBalance_Val_BCM_MEM_SMRL2_Backrest_100_Cushion_0_3 (7) +#endif + +#ifndef BCM_RLMemActVentBalance_Val_BCM_MEM_SMRL2_Backrest_100_Cushion_33_2 +#define BCM_RLMemActVentBalance_Val_BCM_MEM_SMRL2_Backrest_100_Cushion_33_2 (6) +#endif + +#ifndef BCM_RLMemActVentBalance_Val_BCM_MEM_SMRL2_Backrest_100_Cushion_67_1 +#define BCM_RLMemActVentBalance_Val_BCM_MEM_SMRL2_Backrest_100_Cushion_67_1 (5) +#endif + +#ifndef BCM_RLMemActVentBalance_Val_BCM_MEM_SMRL2_Backrest_100_Cushion_100_0 +#define BCM_RLMemActVentBalance_Val_BCM_MEM_SMRL2_Backrest_100_Cushion_100_0 (4) +#endif + +#ifndef BCM_RLMemActVentBalance_Val_BCM_MEM_SMRL2_Backrest_67_Cushion_100_1 +#define BCM_RLMemActVentBalance_Val_BCM_MEM_SMRL2_Backrest_67_Cushion_100_1 (3) +#endif + +#ifndef BCM_RLMemActVentBalance_Val_BCM_MEM_SMRL2_Backrest_33_Cushion_100_2 +#define BCM_RLMemActVentBalance_Val_BCM_MEM_SMRL2_Backrest_33_Cushion_100_2 (2) +#endif + +#ifndef BCM_RLMemActVentBalance_Val_BCM_MEM_SMRL2_Backrest_0_Cushion_100_3 +#define BCM_RLMemActVentBalance_Val_BCM_MEM_SMRL2_Backrest_0_Cushion_100_3 (1) +#endif + +#ifndef BCM_RLMemActVentBalance_Val_BCM_MEM_SMRL2_No_action +#define BCM_RLMemActVentBalance_Val_BCM_MEM_SMRL2_No_action (0) +#endif + +// signal: @BCM_RLMemPosnPrsnSeatCS_Val_ro +#define CANDB_BCM_RLMemPosnPrsnSeatCS_Val_ro_CovFactor (0.394) +#define CANDB_BCM_RLMemPosnPrsnSeatCS_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.394)) ) +#define CANDB_BCM_RLMemPosnPrsnSeatCS_Val_ro_fromS(x) ( (((x) * (0.394)) + (0.0)) ) +// signal: @BCM_RLMemPosnPrsnSeatLSH_Val_ro +#define CANDB_BCM_RLMemPosnPrsnSeatLSH_Val_ro_CovFactor (0.394) +#define CANDB_BCM_RLMemPosnPrsnSeatLSH_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.394)) ) +#define CANDB_BCM_RLMemPosnPrsnSeatLSH_Val_ro_fromS(x) ( (((x) * (0.394)) + (0.0)) ) +// signal: @BCM_RLMemPosnPrsnSeatLSD_Val_ro +#define CANDB_BCM_RLMemPosnPrsnSeatLSD_Val_ro_CovFactor (0.394) +#define CANDB_BCM_RLMemPosnPrsnSeatLSD_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.394)) ) +#define CANDB_BCM_RLMemPosnPrsnSeatLSD_Val_ro_fromS(x) ( (((x) * (0.394)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Stored for SMRL seat back rest head inclination position. + uint8_t BCM_RLMemPosnActSeatBRHI_Val_ro; // Bits= 8 Factor= 0.1 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RLMemPosnActSeatBRHI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMRL seat head rest height inclination position. + uint8_t BCM_RLMemPosnActSeatHRHI_Val_ro; // Bits= 8 Factor= 0.71 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RLMemPosnActSeatHRHI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMRL seat back rest inclination position. + uint8_t BCM_RLMemPosnActSeatBRI_Val_ro; // Bits= 8 Factor= 0.1 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RLMemPosnActSeatBRI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMRL seat heat balance + // 7 : "Backrest 100%, Cushion 0%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 0%, Cushion 100%: -3" + // 0 : "No action" + uint8_t BCM_RLMemActHeatBalance_Val : 3; // Bits= 3 + + // Stored for SMRL seat ventilation balance + // 7 : "Backrest 100%, Cushion 0%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 0%, Cushion 100%: -3" + // 0 : "No action" + uint8_t BCM_RLMemActVentBalance_Val : 3; // Bits= 3 + + // Stored for SMRL seat cushion support position + uint8_t BCM_RLMemPosnPrsnSeatCS_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RLMemPosnPrsnSeatCS_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMRL seat Longitudinal Surface Height + uint8_t BCM_RLMemPosnPrsnSeatLSH_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RLMemPosnPrsnSeatLSH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMRL seat Longitudinal Surface Depth + uint8_t BCM_RLMemPosnPrsnSeatLSD_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RLMemPosnPrsnSeatLSD_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#else + + // Stored for SMRL seat back rest head inclination position. + uint8_t BCM_RLMemPosnActSeatBRHI_Val_ro; // Bits= 8 Factor= 0.1 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RLMemPosnActSeatBRHI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMRL seat head rest height inclination position. + uint8_t BCM_RLMemPosnActSeatHRHI_Val_ro; // Bits= 8 Factor= 0.71 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RLMemPosnActSeatHRHI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMRL seat back rest inclination position. + uint8_t BCM_RLMemPosnActSeatBRI_Val_ro; // Bits= 8 Factor= 0.1 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RLMemPosnActSeatBRI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMRL seat heat balance + // 7 : "Backrest 100%, Cushion 0%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 0%, Cushion 100%: -3" + // 0 : "No action" + uint8_t BCM_RLMemActHeatBalance_Val; // Bits= 3 + + // Stored for SMRL seat ventilation balance + // 7 : "Backrest 100%, Cushion 0%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 0%, Cushion 100%: -3" + // 0 : "No action" + uint8_t BCM_RLMemActVentBalance_Val; // Bits= 3 + + // Stored for SMRL seat cushion support position + uint8_t BCM_RLMemPosnPrsnSeatCS_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RLMemPosnPrsnSeatCS_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMRL seat Longitudinal Surface Height + uint8_t BCM_RLMemPosnPrsnSeatLSH_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RLMemPosnPrsnSeatLSH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMRL seat Longitudinal Surface Depth + uint8_t BCM_RLMemPosnPrsnSeatLSD_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RLMemPosnPrsnSeatLSD_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} BCM_MEM_SMRL2_t; + +// def @SMRR_MEM1 CAN Message (1343 0x53f) +#define SMRR_MEM1_IDE (0U) +#define SMRR_MEM1_DLC (8U) +#define SMRR_MEM1_CANID (0x53fU) +// signal: @SMRR_PosnActSeatI_Val_ro +#define CANDB_SMRR_PosnActSeatI_Val_ro_CovFactor (0.125) +#define CANDB_SMRR_PosnActSeatI_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.125)) ) +#define CANDB_SMRR_PosnActSeatI_Val_ro_fromS(x) ( (((x) * (0.125)) + (0.0)) ) +// signal: @SMRR_PosnActSeatBRW_Val_ro +#define CANDB_SMRR_PosnActSeatBRW_Val_ro_CovFactor (1) +#define CANDB_SMRR_PosnActSeatBRW_Val_ro_toS(x) ( (uint8_t) ((x) - (300)) ) +#define CANDB_SMRR_PosnActSeatBRW_Val_ro_fromS(x) ( ((x) + (300)) ) +// signal: @SMRR_PosnActSeatFRH_Val_ro +#define CANDB_SMRR_PosnActSeatFRH_Val_ro_CovFactor (0.8) +#define CANDB_SMRR_PosnActSeatFRH_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.8)) ) +#define CANDB_SMRR_PosnActSeatFRH_Val_ro_fromS(x) ( (((x) * (0.8)) + (0.0)) ) +// signal: @SMRR_PosnActSeatFRL_Val_ro +#define CANDB_SMRR_PosnActSeatFRL_Val_ro_CovFactor (0.25) +#define CANDB_SMRR_PosnActSeatFRL_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.25)) ) +#define CANDB_SMRR_PosnActSeatFRL_Val_ro_fromS(x) ( (((x) * (0.25)) + (0.0)) ) +// signal: @SMRR_PosnActSeatH_Val_ro +#define CANDB_SMRR_PosnActSeatH_Val_ro_CovFactor (0.8) +#define CANDB_SMRR_PosnActSeatH_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.8)) ) +#define CANDB_SMRR_PosnActSeatH_Val_ro_fromS(x) ( (((x) * (0.8)) + (0.0)) ) +// signal: @SMRR_PosnActSeatHRH_Val_ro +#define CANDB_SMRR_PosnActSeatHRH_Val_ro_CovFactor (0.5) +#define CANDB_SMRR_PosnActSeatHRH_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.5)) ) +#define CANDB_SMRR_PosnActSeatHRH_Val_ro_fromS(x) ( (((x) * (0.5)) + (0.0)) ) +// signal: @SMRR_PosnActSeatL_Val_ro +#define CANDB_SMRR_PosnActSeatL_Val_ro_CovFactor (0.8) +#define CANDB_SMRR_PosnActSeatL_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.8)) ) +#define CANDB_SMRR_PosnActSeatL_Val_ro_fromS(x) ( (((x) * (0.8)) + (0.0)) ) +// signal: @SMRR_PosnActSeatSL_Val_ro +#define CANDB_SMRR_PosnActSeatSL_Val_ro_CovFactor (0.8) +#define CANDB_SMRR_PosnActSeatSL_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.8)) ) +#define CANDB_SMRR_PosnActSeatSL_Val_ro_fromS(x) ( (((x) * (0.8)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // SMRR current seat inclination position. + uint8_t SMRR_PosnActSeatI_Val_ro; // Bits= 8 Factor= 0.125 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRR_PosnActSeatI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRR current seat back rest width position. + uint8_t SMRR_PosnActSeatBRW_Val_ro; // Bits= 8 Offset= 300 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + uint16_t SMRR_PosnActSeatBRW_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRR current seat foot rest height position. + uint8_t SMRR_PosnActSeatFRH_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRR_PosnActSeatFRH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRR current seat foot rest longitudinal position. + uint8_t SMRR_PosnActSeatFRL_Val_ro; // Bits= 8 Factor= 0.25 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRR_PosnActSeatFRL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRR current seat height position. + uint8_t SMRR_PosnActSeatH_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRR_PosnActSeatH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRR current seat head rest height position. + uint8_t SMRR_PosnActSeatHRH_Val_ro; // Bits= 8 Factor= 0.5 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRR_PosnActSeatHRH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRR current seat longitudinal position. + uint8_t SMRR_PosnActSeatL_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRR_PosnActSeatL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRR current seat surface longitudinal position. + uint8_t SMRR_PosnActSeatSL_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRR_PosnActSeatSL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#else + + // SMRR current seat inclination position. + uint8_t SMRR_PosnActSeatI_Val_ro; // Bits= 8 Factor= 0.125 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRR_PosnActSeatI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRR current seat back rest width position. + uint8_t SMRR_PosnActSeatBRW_Val_ro; // Bits= 8 Offset= 300 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + uint16_t SMRR_PosnActSeatBRW_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRR current seat foot rest height position. + uint8_t SMRR_PosnActSeatFRH_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRR_PosnActSeatFRH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRR current seat foot rest longitudinal position. + uint8_t SMRR_PosnActSeatFRL_Val_ro; // Bits= 8 Factor= 0.25 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRR_PosnActSeatFRL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRR current seat height position. + uint8_t SMRR_PosnActSeatH_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRR_PosnActSeatH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRR current seat head rest height position. + uint8_t SMRR_PosnActSeatHRH_Val_ro; // Bits= 8 Factor= 0.5 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRR_PosnActSeatHRH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRR current seat longitudinal position. + uint8_t SMRR_PosnActSeatL_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRR_PosnActSeatL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRR current seat surface longitudinal position. + uint8_t SMRR_PosnActSeatSL_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRR_PosnActSeatSL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} SMRR_MEM1_t; + +// def @BCM_MEM_SMRR1 CAN Message (1344 0x540) +#define BCM_MEM_SMRR1_IDE (0U) +#define BCM_MEM_SMRR1_DLC (8U) +#define BCM_MEM_SMRR1_CANID (0x540U) +// signal: @BCM_RRMemPosnActSeatI_Val_ro +#define CANDB_BCM_RRMemPosnActSeatI_Val_ro_CovFactor (0.125) +#define CANDB_BCM_RRMemPosnActSeatI_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.125)) ) +#define CANDB_BCM_RRMemPosnActSeatI_Val_ro_fromS(x) ( (((x) * (0.125)) + (0.0)) ) +// signal: @BCM_RRMemPosnActSeatBRW_Val_ro +#define CANDB_BCM_RRMemPosnActSeatBRW_Val_ro_CovFactor (1) +#define CANDB_BCM_RRMemPosnActSeatBRW_Val_ro_toS(x) ( (uint8_t) ((x) - (300)) ) +#define CANDB_BCM_RRMemPosnActSeatBRW_Val_ro_fromS(x) ( ((x) + (300)) ) +// signal: @BCM_RRMemPosnActSeatFRH_Val_ro +#define CANDB_BCM_RRMemPosnActSeatFRH_Val_ro_CovFactor (0.8) +#define CANDB_BCM_RRMemPosnActSeatFRH_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.8)) ) +#define CANDB_BCM_RRMemPosnActSeatFRH_Val_ro_fromS(x) ( (((x) * (0.8)) + (0.0)) ) +// signal: @BCM_RRMemPosnActSeatFRL_Val_ro +#define CANDB_BCM_RRMemPosnActSeatFRL_Val_ro_CovFactor (0.25) +#define CANDB_BCM_RRMemPosnActSeatFRL_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.25)) ) +#define CANDB_BCM_RRMemPosnActSeatFRL_Val_ro_fromS(x) ( (((x) * (0.25)) + (0.0)) ) +// signal: @BCM_RRMemPosnActSeatH_Val_ro +#define CANDB_BCM_RRMemPosnActSeatH_Val_ro_CovFactor (0.8) +#define CANDB_BCM_RRMemPosnActSeatH_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.8)) ) +#define CANDB_BCM_RRMemPosnActSeatH_Val_ro_fromS(x) ( (((x) * (0.8)) + (0.0)) ) +// signal: @BCM_RRMemPosnActSeatHRH_Val_ro +#define CANDB_BCM_RRMemPosnActSeatHRH_Val_ro_CovFactor (0.5) +#define CANDB_BCM_RRMemPosnActSeatHRH_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.5)) ) +#define CANDB_BCM_RRMemPosnActSeatHRH_Val_ro_fromS(x) ( (((x) * (0.5)) + (0.0)) ) +// signal: @BCM_RRMemPosnActSeatL_Val_ro +#define CANDB_BCM_RRMemPosnActSeatL_Val_ro_CovFactor (0.8) +#define CANDB_BCM_RRMemPosnActSeatL_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.8)) ) +#define CANDB_BCM_RRMemPosnActSeatL_Val_ro_fromS(x) ( (((x) * (0.8)) + (0.0)) ) +// signal: @BCM_RRMemPosnActSeatSL_Val_ro +#define CANDB_BCM_RRMemPosnActSeatSL_Val_ro_CovFactor (0.8) +#define CANDB_BCM_RRMemPosnActSeatSL_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.8)) ) +#define CANDB_BCM_RRMemPosnActSeatSL_Val_ro_fromS(x) ( (((x) * (0.8)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Stored SMRR seat inclination position. + uint8_t BCM_RRMemPosnActSeatI_Val_ro; // Bits= 8 Factor= 0.125 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RRMemPosnActSeatI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMRR seat back rest width position. + uint8_t BCM_RRMemPosnActSeatBRW_Val_ro; // Bits= 8 Offset= 300 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + uint16_t BCM_RRMemPosnActSeatBRW_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMRR seat foot rest height position. + uint8_t BCM_RRMemPosnActSeatFRH_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RRMemPosnActSeatFRH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMRR seat foot rest longitudinal position. + uint8_t BCM_RRMemPosnActSeatFRL_Val_ro; // Bits= 8 Factor= 0.25 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RRMemPosnActSeatFRL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMRR seat height position. + uint8_t BCM_RRMemPosnActSeatH_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RRMemPosnActSeatH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMRR seat head rest height position. + uint8_t BCM_RRMemPosnActSeatHRH_Val_ro; // Bits= 8 Factor= 0.5 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RRMemPosnActSeatHRH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMRR seat longitudinal position. + uint8_t BCM_RRMemPosnActSeatL_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RRMemPosnActSeatL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMRR seat surface longitudinal position. + uint8_t BCM_RRMemPosnActSeatSL_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RRMemPosnActSeatSL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#else + + // Stored SMRR seat inclination position. + uint8_t BCM_RRMemPosnActSeatI_Val_ro; // Bits= 8 Factor= 0.125 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RRMemPosnActSeatI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMRR seat back rest width position. + uint8_t BCM_RRMemPosnActSeatBRW_Val_ro; // Bits= 8 Offset= 300 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + uint16_t BCM_RRMemPosnActSeatBRW_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMRR seat foot rest height position. + uint8_t BCM_RRMemPosnActSeatFRH_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RRMemPosnActSeatFRH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMRR seat foot rest longitudinal position. + uint8_t BCM_RRMemPosnActSeatFRL_Val_ro; // Bits= 8 Factor= 0.25 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RRMemPosnActSeatFRL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMRR seat height position. + uint8_t BCM_RRMemPosnActSeatH_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RRMemPosnActSeatH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMRR seat head rest height position. + uint8_t BCM_RRMemPosnActSeatHRH_Val_ro; // Bits= 8 Factor= 0.5 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RRMemPosnActSeatHRH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMRR seat longitudinal position. + uint8_t BCM_RRMemPosnActSeatL_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RRMemPosnActSeatL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored SMRR seat surface longitudinal position. + uint8_t BCM_RRMemPosnActSeatSL_Val_ro; // Bits= 8 Factor= 0.8 Unit:'mm' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RRMemPosnActSeatSL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} BCM_MEM_SMRR1_t; + +// def @SMRR_MEM2 CAN Message (1345 0x541) +#define SMRR_MEM2_IDE (0U) +#define SMRR_MEM2_DLC (8U) +#define SMRR_MEM2_CANID (0x541U) +// signal: @SMRR_PosnActSeatBRHI_Val_ro +#define CANDB_SMRR_PosnActSeatBRHI_Val_ro_CovFactor (0.1) +#define CANDB_SMRR_PosnActSeatBRHI_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_SMRR_PosnActSeatBRHI_Val_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @SMRR_PosnActSeatHRHI_Val_ro +#define CANDB_SMRR_PosnActSeatHRHI_Val_ro_CovFactor (0.71) +#define CANDB_SMRR_PosnActSeatHRHI_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.71)) ) +#define CANDB_SMRR_PosnActSeatHRHI_Val_ro_fromS(x) ( (((x) * (0.71)) + (0.0)) ) +// signal: @SMRR_PosnActSeatBRI_Val_ro +#define CANDB_SMRR_PosnActSeatBRI_Val_ro_CovFactor (0.1) +#define CANDB_SMRR_PosnActSeatBRI_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_SMRR_PosnActSeatBRI_Val_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +// Value tables for @SMRR_ActHeatBalance_Stat signal + +#ifndef SMRR_ActHeatBalance_Stat_SMRR_MEM2_Backrest_100_Cushion_00_3 +#define SMRR_ActHeatBalance_Stat_SMRR_MEM2_Backrest_100_Cushion_00_3 (7) +#endif + +#ifndef SMRR_ActHeatBalance_Stat_SMRR_MEM2_Backrest_100_Cushion_33_2 +#define SMRR_ActHeatBalance_Stat_SMRR_MEM2_Backrest_100_Cushion_33_2 (6) +#endif + +#ifndef SMRR_ActHeatBalance_Stat_SMRR_MEM2_Backrest_100_Cushion_67_1 +#define SMRR_ActHeatBalance_Stat_SMRR_MEM2_Backrest_100_Cushion_67_1 (5) +#endif + +#ifndef SMRR_ActHeatBalance_Stat_SMRR_MEM2_Backrest_100_Cushion_100_0 +#define SMRR_ActHeatBalance_Stat_SMRR_MEM2_Backrest_100_Cushion_100_0 (4) +#endif + +#ifndef SMRR_ActHeatBalance_Stat_SMRR_MEM2_Backrest_67_Cushion_100_1 +#define SMRR_ActHeatBalance_Stat_SMRR_MEM2_Backrest_67_Cushion_100_1 (3) +#endif + +#ifndef SMRR_ActHeatBalance_Stat_SMRR_MEM2_Backrest_33_Cushion_100_2 +#define SMRR_ActHeatBalance_Stat_SMRR_MEM2_Backrest_33_Cushion_100_2 (2) +#endif + +#ifndef SMRR_ActHeatBalance_Stat_SMRR_MEM2_No_action +#define SMRR_ActHeatBalance_Stat_SMRR_MEM2_No_action (0) +#endif + +#ifndef SMRR_ActHeatBalance_Stat_SMRR_MEM2_Backrest_00_Cushion_100_3 +#define SMRR_ActHeatBalance_Stat_SMRR_MEM2_Backrest_00_Cushion_100_3 (1) +#endif + + +// Value tables for @SMRR_ActVentBalance_Stat signal + +#ifndef SMRR_ActVentBalance_Stat_SMRR_MEM2_Backrest_100_Cushion_00_3 +#define SMRR_ActVentBalance_Stat_SMRR_MEM2_Backrest_100_Cushion_00_3 (7) +#endif + +#ifndef SMRR_ActVentBalance_Stat_SMRR_MEM2_Backrest_100_Cushion_33_2 +#define SMRR_ActVentBalance_Stat_SMRR_MEM2_Backrest_100_Cushion_33_2 (6) +#endif + +#ifndef SMRR_ActVentBalance_Stat_SMRR_MEM2_Backrest_100_Cushion_67_1 +#define SMRR_ActVentBalance_Stat_SMRR_MEM2_Backrest_100_Cushion_67_1 (5) +#endif + +#ifndef SMRR_ActVentBalance_Stat_SMRR_MEM2_Backrest_100_Cushion_100_0 +#define SMRR_ActVentBalance_Stat_SMRR_MEM2_Backrest_100_Cushion_100_0 (4) +#endif + +#ifndef SMRR_ActVentBalance_Stat_SMRR_MEM2_Backrest_67_Cushion_100_1 +#define SMRR_ActVentBalance_Stat_SMRR_MEM2_Backrest_67_Cushion_100_1 (3) +#endif + +#ifndef SMRR_ActVentBalance_Stat_SMRR_MEM2_Backrest_33_Cushion_100_2 +#define SMRR_ActVentBalance_Stat_SMRR_MEM2_Backrest_33_Cushion_100_2 (2) +#endif + +#ifndef SMRR_ActVentBalance_Stat_SMRR_MEM2_No_action +#define SMRR_ActVentBalance_Stat_SMRR_MEM2_No_action (0) +#endif + +#ifndef SMRR_ActVentBalance_Stat_SMRR_MEM2_Backrest_00_Cushion_100_3 +#define SMRR_ActVentBalance_Stat_SMRR_MEM2_Backrest_00_Cushion_100_3 (1) +#endif + +// signal: @SMRR_PosnPrsnSeatCS_Val_ro +#define CANDB_SMRR_PosnPrsnSeatCS_Val_ro_CovFactor (0.394) +#define CANDB_SMRR_PosnPrsnSeatCS_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.394)) ) +#define CANDB_SMRR_PosnPrsnSeatCS_Val_ro_fromS(x) ( (((x) * (0.394)) + (0.0)) ) +// signal: @SMRR_PosnPrsnSeatLSH_Val_ro +#define CANDB_SMRR_PosnPrsnSeatLSH_Val_ro_CovFactor (0.394) +#define CANDB_SMRR_PosnPrsnSeatLSH_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.394)) ) +#define CANDB_SMRR_PosnPrsnSeatLSH_Val_ro_fromS(x) ( (((x) * (0.394)) + (0.0)) ) +// signal: @SMRR_PosnPrsnSeatLSD_Val_ro +#define CANDB_SMRR_PosnPrsnSeatLSD_Val_ro_CovFactor (0.394) +#define CANDB_SMRR_PosnPrsnSeatLSD_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.394)) ) +#define CANDB_SMRR_PosnPrsnSeatLSD_Val_ro_fromS(x) ( (((x) * (0.394)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // SMRR current seat back rest head inclination position. + uint8_t SMRR_PosnActSeatBRHI_Val_ro; // Bits= 8 Factor= 0.1 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRR_PosnActSeatBRHI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRR current seat head rest height inclination position. + uint8_t SMRR_PosnActSeatHRHI_Val_ro; // Bits= 8 Factor= 0.71 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRR_PosnActSeatHRHI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRR current seat back rest inclination position. + uint8_t SMRR_PosnActSeatBRI_Val_ro; // Bits= 8 Factor= 0.1 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRR_PosnActSeatBRI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRR current seat heat balance + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 0 : "No action" + // 1 : "Backrest 00%, Cushion 100%: -3" + uint8_t SMRR_ActHeatBalance_Stat : 3; // Bits= 3 + + // SMRR current seat ventilation balance + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 0 : "No action" + // 1 : "Backrest 00%, Cushion 100%: -3" + uint8_t SMRR_ActVentBalance_Stat : 3; // Bits= 3 + + // SMRR current seat cushion support position + uint8_t SMRR_PosnPrsnSeatCS_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRR_PosnPrsnSeatCS_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRR current seat longitudinal position + uint8_t SMRR_PosnPrsnSeatLSH_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRR_PosnPrsnSeatLSH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRR current seat surface longitudinal position + uint8_t SMRR_PosnPrsnSeatLSD_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRR_PosnPrsnSeatLSD_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#else + + // SMRR current seat back rest head inclination position. + uint8_t SMRR_PosnActSeatBRHI_Val_ro; // Bits= 8 Factor= 0.1 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRR_PosnActSeatBRHI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRR current seat head rest height inclination position. + uint8_t SMRR_PosnActSeatHRHI_Val_ro; // Bits= 8 Factor= 0.71 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRR_PosnActSeatHRHI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRR current seat back rest inclination position. + uint8_t SMRR_PosnActSeatBRI_Val_ro; // Bits= 8 Factor= 0.1 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRR_PosnActSeatBRI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRR current seat heat balance + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 0 : "No action" + // 1 : "Backrest 00%, Cushion 100%: -3" + uint8_t SMRR_ActHeatBalance_Stat; // Bits= 3 + + // SMRR current seat ventilation balance + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 0 : "No action" + // 1 : "Backrest 00%, Cushion 100%: -3" + uint8_t SMRR_ActVentBalance_Stat; // Bits= 3 + + // SMRR current seat cushion support position + uint8_t SMRR_PosnPrsnSeatCS_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRR_PosnPrsnSeatCS_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRR current seat longitudinal position + uint8_t SMRR_PosnPrsnSeatLSH_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRR_PosnPrsnSeatLSH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // SMRR current seat surface longitudinal position + uint8_t SMRR_PosnPrsnSeatLSD_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t SMRR_PosnPrsnSeatLSD_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} SMRR_MEM2_t; + +// def @BCM_MEM_SMRR2 CAN Message (1346 0x542) +#define BCM_MEM_SMRR2_IDE (0U) +#define BCM_MEM_SMRR2_DLC (8U) +#define BCM_MEM_SMRR2_CANID (0x542U) +// signal: @BCM_RRMemPosnActSeatBRHI_Val_ro +#define CANDB_BCM_RRMemPosnActSeatBRHI_Val_ro_CovFactor (0.1) +#define CANDB_BCM_RRMemPosnActSeatBRHI_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_BCM_RRMemPosnActSeatBRHI_Val_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) +// signal: @BCM_RRMemPosnActSeatHRHI_Val_ro +#define CANDB_BCM_RRMemPosnActSeatHRHI_Val_ro_CovFactor (0.71) +#define CANDB_BCM_RRMemPosnActSeatHRHI_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.71)) ) +#define CANDB_BCM_RRMemPosnActSeatHRHI_Val_ro_fromS(x) ( (((x) * (0.71)) + (0.0)) ) +// signal: @BCM_RRMemPosnActSeatBRI_Val_ro +#define CANDB_BCM_RRMemPosnActSeatBRI_Val_ro_CovFactor (0.1) +#define CANDB_BCM_RRMemPosnActSeatBRI_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_BCM_RRMemPosnActSeatBRI_Val_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +// Value tables for @BCM_RRMemActHeatBalance_Val signal + +#ifndef BCM_RRMemActHeatBalance_Val_BCM_MEM_SMRR2_Backrest_100_Cushion_0_3 +#define BCM_RRMemActHeatBalance_Val_BCM_MEM_SMRR2_Backrest_100_Cushion_0_3 (7) +#endif + +#ifndef BCM_RRMemActHeatBalance_Val_BCM_MEM_SMRR2_Backrest_100_Cushion_33_2 +#define BCM_RRMemActHeatBalance_Val_BCM_MEM_SMRR2_Backrest_100_Cushion_33_2 (6) +#endif + +#ifndef BCM_RRMemActHeatBalance_Val_BCM_MEM_SMRR2_Backrest_100_Cushion_67_1 +#define BCM_RRMemActHeatBalance_Val_BCM_MEM_SMRR2_Backrest_100_Cushion_67_1 (5) +#endif + +#ifndef BCM_RRMemActHeatBalance_Val_BCM_MEM_SMRR2_Backrest_100_Cushion_100_0 +#define BCM_RRMemActHeatBalance_Val_BCM_MEM_SMRR2_Backrest_100_Cushion_100_0 (4) +#endif + +#ifndef BCM_RRMemActHeatBalance_Val_BCM_MEM_SMRR2_Backrest_67_Cushion_100_1 +#define BCM_RRMemActHeatBalance_Val_BCM_MEM_SMRR2_Backrest_67_Cushion_100_1 (3) +#endif + +#ifndef BCM_RRMemActHeatBalance_Val_BCM_MEM_SMRR2_Backrest_33_Cushion_100_2 +#define BCM_RRMemActHeatBalance_Val_BCM_MEM_SMRR2_Backrest_33_Cushion_100_2 (2) +#endif + +#ifndef BCM_RRMemActHeatBalance_Val_BCM_MEM_SMRR2_Backrest_0_Cushion_100_3 +#define BCM_RRMemActHeatBalance_Val_BCM_MEM_SMRR2_Backrest_0_Cushion_100_3 (1) +#endif + +#ifndef BCM_RRMemActHeatBalance_Val_BCM_MEM_SMRR2_No_action +#define BCM_RRMemActHeatBalance_Val_BCM_MEM_SMRR2_No_action (0) +#endif + + +// Value tables for @BCM_RRMemActVentBalance_Val signal + +#ifndef BCM_RRMemActVentBalance_Val_BCM_MEM_SMRR2_Backrest_100_Cushion_0_3 +#define BCM_RRMemActVentBalance_Val_BCM_MEM_SMRR2_Backrest_100_Cushion_0_3 (7) +#endif + +#ifndef BCM_RRMemActVentBalance_Val_BCM_MEM_SMRR2_Backrest_100_Cushion_33_2 +#define BCM_RRMemActVentBalance_Val_BCM_MEM_SMRR2_Backrest_100_Cushion_33_2 (6) +#endif + +#ifndef BCM_RRMemActVentBalance_Val_BCM_MEM_SMRR2_Backrest_100_Cushion_67_1 +#define BCM_RRMemActVentBalance_Val_BCM_MEM_SMRR2_Backrest_100_Cushion_67_1 (5) +#endif + +#ifndef BCM_RRMemActVentBalance_Val_BCM_MEM_SMRR2_Backrest_100_Cushion_100_0 +#define BCM_RRMemActVentBalance_Val_BCM_MEM_SMRR2_Backrest_100_Cushion_100_0 (4) +#endif + +#ifndef BCM_RRMemActVentBalance_Val_BCM_MEM_SMRR2_Backrest_67_Cushion_100_1 +#define BCM_RRMemActVentBalance_Val_BCM_MEM_SMRR2_Backrest_67_Cushion_100_1 (3) +#endif + +#ifndef BCM_RRMemActVentBalance_Val_BCM_MEM_SMRR2_Backrest_33_Cushion_100_2 +#define BCM_RRMemActVentBalance_Val_BCM_MEM_SMRR2_Backrest_33_Cushion_100_2 (2) +#endif + +#ifndef BCM_RRMemActVentBalance_Val_BCM_MEM_SMRR2_Backrest_0_Cushion_100_3 +#define BCM_RRMemActVentBalance_Val_BCM_MEM_SMRR2_Backrest_0_Cushion_100_3 (1) +#endif + +#ifndef BCM_RRMemActVentBalance_Val_BCM_MEM_SMRR2_No_action +#define BCM_RRMemActVentBalance_Val_BCM_MEM_SMRR2_No_action (0) +#endif + +// signal: @BCM_RRMemPosnPrsnSeatCS_Val_ro +#define CANDB_BCM_RRMemPosnPrsnSeatCS_Val_ro_CovFactor (0.394) +#define CANDB_BCM_RRMemPosnPrsnSeatCS_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.394)) ) +#define CANDB_BCM_RRMemPosnPrsnSeatCS_Val_ro_fromS(x) ( (((x) * (0.394)) + (0.0)) ) +// signal: @BCM_RRMemPosnPrsnSeatLSH_Val_ro +#define CANDB_BCM_RRMemPosnPrsnSeatLSH_Val_ro_CovFactor (0.394) +#define CANDB_BCM_RRMemPosnPrsnSeatLSH_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.394)) ) +#define CANDB_BCM_RRMemPosnPrsnSeatLSH_Val_ro_fromS(x) ( (((x) * (0.394)) + (0.0)) ) +// signal: @BCM_RRMemPosnPrsnSeatLSD_Val_ro +#define CANDB_BCM_RRMemPosnPrsnSeatLSD_Val_ro_CovFactor (0.394) +#define CANDB_BCM_RRMemPosnPrsnSeatLSD_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.394)) ) +#define CANDB_BCM_RRMemPosnPrsnSeatLSD_Val_ro_fromS(x) ( (((x) * (0.394)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Stored for SMRR seat back rest head inclination position. + uint8_t BCM_RRMemPosnActSeatBRHI_Val_ro; // Bits= 8 Factor= 0.1 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RRMemPosnActSeatBRHI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMRR seat head rest height inclination position. + uint8_t BCM_RRMemPosnActSeatHRHI_Val_ro; // Bits= 8 Factor= 0.71 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RRMemPosnActSeatHRHI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMRR seat back rest inclination position. + uint8_t BCM_RRMemPosnActSeatBRI_Val_ro; // Bits= 8 Factor= 0.1 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RRMemPosnActSeatBRI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMRR seat heat balance + // 7 : "Backrest 100%, Cushion 0%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 0%, Cushion 100%: -3" + // 0 : "No action" + uint8_t BCM_RRMemActHeatBalance_Val : 3; // Bits= 3 + + // Stored for SMRR seat ventilation balance + // 7 : "Backrest 100%, Cushion 0%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 0%, Cushion 100%: -3" + // 0 : "No action" + uint8_t BCM_RRMemActVentBalance_Val : 3; // Bits= 3 + + // Stored for SMRR seat cushion support position + uint8_t BCM_RRMemPosnPrsnSeatCS_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RRMemPosnPrsnSeatCS_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMRR seat Longitudinal Surface Height + uint8_t BCM_RRMemPosnPrsnSeatLSH_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RRMemPosnPrsnSeatLSH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Srored for SMRR seat Longitudinal Surface Depth + uint8_t BCM_RRMemPosnPrsnSeatLSD_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RRMemPosnPrsnSeatLSD_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#else + + // Stored for SMRR seat back rest head inclination position. + uint8_t BCM_RRMemPosnActSeatBRHI_Val_ro; // Bits= 8 Factor= 0.1 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RRMemPosnActSeatBRHI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMRR seat head rest height inclination position. + uint8_t BCM_RRMemPosnActSeatHRHI_Val_ro; // Bits= 8 Factor= 0.71 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RRMemPosnActSeatHRHI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMRR seat back rest inclination position. + uint8_t BCM_RRMemPosnActSeatBRI_Val_ro; // Bits= 8 Factor= 0.1 Unit:'�' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RRMemPosnActSeatBRI_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMRR seat heat balance + // 7 : "Backrest 100%, Cushion 0%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 0%, Cushion 100%: -3" + // 0 : "No action" + uint8_t BCM_RRMemActHeatBalance_Val; // Bits= 3 + + // Stored for SMRR seat ventilation balance + // 7 : "Backrest 100%, Cushion 0%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 0%, Cushion 100%: -3" + // 0 : "No action" + uint8_t BCM_RRMemActVentBalance_Val; // Bits= 3 + + // Stored for SMRR seat cushion support position + uint8_t BCM_RRMemPosnPrsnSeatCS_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RRMemPosnPrsnSeatCS_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Stored for SMRR seat Longitudinal Surface Height + uint8_t BCM_RRMemPosnPrsnSeatLSH_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RRMemPosnPrsnSeatLSH_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Srored for SMRR seat Longitudinal Surface Depth + uint8_t BCM_RRMemPosnPrsnSeatLSD_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_RRMemPosnPrsnSeatLSD_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} BCM_MEM_SMRR2_t; + +// def @FIU_SMFL_REQ_CTR_SEATS CAN Message (1363 0x553) +#define FIU_SMFL_REQ_CTR_SEATS_IDE (0U) +#define FIU_SMFL_REQ_CTR_SEATS_DLC (7U) +#define FIU_SMFL_REQ_CTR_SEATS_CANID (0x553U) + +// Value tables for @FIU_SMFL_SeatHeight_Req signal + +#ifndef FIU_SMFL_SeatHeight_Req_FIU_SMFL_REQ_CTR_SEATS_Reserved +#define FIU_SMFL_SeatHeight_Req_FIU_SMFL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMFL_SeatHeight_Req_FIU_SMFL_REQ_CTR_SEATS_Decrease +#define FIU_SMFL_SeatHeight_Req_FIU_SMFL_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMFL_SeatHeight_Req_FIU_SMFL_REQ_CTR_SEATS_Increase +#define FIU_SMFL_SeatHeight_Req_FIU_SMFL_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMFL_SeatHeight_Req_FIU_SMFL_REQ_CTR_SEATS_No_action +#define FIU_SMFL_SeatHeight_Req_FIU_SMFL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFL_HeadRestHeight_Req signal + +#ifndef FIU_SMFL_HeadRestHeight_Req_FIU_SMFL_REQ_CTR_SEATS_Reserved +#define FIU_SMFL_HeadRestHeight_Req_FIU_SMFL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMFL_HeadRestHeight_Req_FIU_SMFL_REQ_CTR_SEATS_Decrease +#define FIU_SMFL_HeadRestHeight_Req_FIU_SMFL_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMFL_HeadRestHeight_Req_FIU_SMFL_REQ_CTR_SEATS_Increase +#define FIU_SMFL_HeadRestHeight_Req_FIU_SMFL_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMFL_HeadRestHeight_Req_FIU_SMFL_REQ_CTR_SEATS_No_action +#define FIU_SMFL_HeadRestHeight_Req_FIU_SMFL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFL_SeatLongitunalReq signal + +#ifndef FIU_SMFL_SeatLongitunalReq_FIU_SMFL_REQ_CTR_SEATS_Reserved +#define FIU_SMFL_SeatLongitunalReq_FIU_SMFL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMFL_SeatLongitunalReq_FIU_SMFL_REQ_CTR_SEATS_Decrease +#define FIU_SMFL_SeatLongitunalReq_FIU_SMFL_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMFL_SeatLongitunalReq_FIU_SMFL_REQ_CTR_SEATS_Increase +#define FIU_SMFL_SeatLongitunalReq_FIU_SMFL_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMFL_SeatLongitunalReq_FIU_SMFL_REQ_CTR_SEATS_No_action +#define FIU_SMFL_SeatLongitunalReq_FIU_SMFL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFL_SeatHeadRestInclin_Req signal + +#ifndef FIU_SMFL_SeatHeadRestInclin_Req_FIU_SMFL_REQ_CTR_SEATS_Reserved +#define FIU_SMFL_SeatHeadRestInclin_Req_FIU_SMFL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMFL_SeatHeadRestInclin_Req_FIU_SMFL_REQ_CTR_SEATS_Decrease +#define FIU_SMFL_SeatHeadRestInclin_Req_FIU_SMFL_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMFL_SeatHeadRestInclin_Req_FIU_SMFL_REQ_CTR_SEATS_Increase +#define FIU_SMFL_SeatHeadRestInclin_Req_FIU_SMFL_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMFL_SeatHeadRestInclin_Req_FIU_SMFL_REQ_CTR_SEATS_No_action +#define FIU_SMFL_SeatHeadRestInclin_Req_FIU_SMFL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFL_SeatSurfaceLong_Req signal + +#ifndef FIU_SMFL_SeatSurfaceLong_Req_FIU_SMFL_REQ_CTR_SEATS_Reserved +#define FIU_SMFL_SeatSurfaceLong_Req_FIU_SMFL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMFL_SeatSurfaceLong_Req_FIU_SMFL_REQ_CTR_SEATS_Decrease +#define FIU_SMFL_SeatSurfaceLong_Req_FIU_SMFL_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMFL_SeatSurfaceLong_Req_FIU_SMFL_REQ_CTR_SEATS_Increase +#define FIU_SMFL_SeatSurfaceLong_Req_FIU_SMFL_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMFL_SeatSurfaceLong_Req_FIU_SMFL_REQ_CTR_SEATS_No_action +#define FIU_SMFL_SeatSurfaceLong_Req_FIU_SMFL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFL_SeatLegSupportH_Req signal + +#ifndef FIU_SMFL_SeatLegSupportH_Req_FIU_SMFL_REQ_CTR_SEATS_Reserved +#define FIU_SMFL_SeatLegSupportH_Req_FIU_SMFL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMFL_SeatLegSupportH_Req_FIU_SMFL_REQ_CTR_SEATS_Decrease +#define FIU_SMFL_SeatLegSupportH_Req_FIU_SMFL_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMFL_SeatLegSupportH_Req_FIU_SMFL_REQ_CTR_SEATS_Increase +#define FIU_SMFL_SeatLegSupportH_Req_FIU_SMFL_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMFL_SeatLegSupportH_Req_FIU_SMFL_REQ_CTR_SEATS_No_action +#define FIU_SMFL_SeatLegSupportH_Req_FIU_SMFL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFL_SeatLegSupportLong_Req signal + +#ifndef FIU_SMFL_SeatLegSupportLong_Req_FIU_SMFL_REQ_CTR_SEATS_Resertved +#define FIU_SMFL_SeatLegSupportLong_Req_FIU_SMFL_REQ_CTR_SEATS_Resertved (3) +#endif + +#ifndef FIU_SMFL_SeatLegSupportLong_Req_FIU_SMFL_REQ_CTR_SEATS_Decrease +#define FIU_SMFL_SeatLegSupportLong_Req_FIU_SMFL_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMFL_SeatLegSupportLong_Req_FIU_SMFL_REQ_CTR_SEATS_Increase +#define FIU_SMFL_SeatLegSupportLong_Req_FIU_SMFL_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMFL_SeatLegSupportLong_Req_FIU_SMFL_REQ_CTR_SEATS_No_action +#define FIU_SMFL_SeatLegSupportLong_Req_FIU_SMFL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFL_SeatInclination_Req signal + +#ifndef FIU_SMFL_SeatInclination_Req_FIU_SMFL_REQ_CTR_SEATS_Reserved +#define FIU_SMFL_SeatInclination_Req_FIU_SMFL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMFL_SeatInclination_Req_FIU_SMFL_REQ_CTR_SEATS_Decrease +#define FIU_SMFL_SeatInclination_Req_FIU_SMFL_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMFL_SeatInclination_Req_FIU_SMFL_REQ_CTR_SEATS_Increase +#define FIU_SMFL_SeatInclination_Req_FIU_SMFL_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMFL_SeatInclination_Req_FIU_SMFL_REQ_CTR_SEATS_No_action +#define FIU_SMFL_SeatInclination_Req_FIU_SMFL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFL_SeatBackRestInc_Req signal + +#ifndef FIU_SMFL_SeatBackRestInc_Req_FIU_SMFL_REQ_CTR_SEATS_Reserved +#define FIU_SMFL_SeatBackRestInc_Req_FIU_SMFL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMFL_SeatBackRestInc_Req_FIU_SMFL_REQ_CTR_SEATS_Decrease +#define FIU_SMFL_SeatBackRestInc_Req_FIU_SMFL_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMFL_SeatBackRestInc_Req_FIU_SMFL_REQ_CTR_SEATS_Increase +#define FIU_SMFL_SeatBackRestInc_Req_FIU_SMFL_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMFL_SeatBackRestInc_Req_FIU_SMFL_REQ_CTR_SEATS_No_action +#define FIU_SMFL_SeatBackRestInc_Req_FIU_SMFL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFL_SeatLumbarSupHeight_Req signal + +#ifndef FIU_SMFL_SeatLumbarSupHeight_Req_FIU_SMFL_REQ_CTR_SEATS_Reserved +#define FIU_SMFL_SeatLumbarSupHeight_Req_FIU_SMFL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMFL_SeatLumbarSupHeight_Req_FIU_SMFL_REQ_CTR_SEATS_Decrease +#define FIU_SMFL_SeatLumbarSupHeight_Req_FIU_SMFL_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMFL_SeatLumbarSupHeight_Req_FIU_SMFL_REQ_CTR_SEATS_Increase +#define FIU_SMFL_SeatLumbarSupHeight_Req_FIU_SMFL_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMFL_SeatLumbarSupHeight_Req_FIU_SMFL_REQ_CTR_SEATS_No_action +#define FIU_SMFL_SeatLumbarSupHeight_Req_FIU_SMFL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFL_SeatBackRestHeadInc_Req signal + +#ifndef FIU_SMFL_SeatBackRestHeadInc_Req_FIU_SMFL_REQ_CTR_SEATS_Reserved +#define FIU_SMFL_SeatBackRestHeadInc_Req_FIU_SMFL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMFL_SeatBackRestHeadInc_Req_FIU_SMFL_REQ_CTR_SEATS_Decrease +#define FIU_SMFL_SeatBackRestHeadInc_Req_FIU_SMFL_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMFL_SeatBackRestHeadInc_Req_FIU_SMFL_REQ_CTR_SEATS_Increase +#define FIU_SMFL_SeatBackRestHeadInc_Req_FIU_SMFL_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMFL_SeatBackRestHeadInc_Req_FIU_SMFL_REQ_CTR_SEATS_No_action +#define FIU_SMFL_SeatBackRestHeadInc_Req_FIU_SMFL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFL_SeatLumbarSupDepth_Req signal + +#ifndef FIU_SMFL_SeatLumbarSupDepth_Req_FIU_SMFL_REQ_CTR_SEATS_Reserved +#define FIU_SMFL_SeatLumbarSupDepth_Req_FIU_SMFL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMFL_SeatLumbarSupDepth_Req_FIU_SMFL_REQ_CTR_SEATS_Decrease +#define FIU_SMFL_SeatLumbarSupDepth_Req_FIU_SMFL_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMFL_SeatLumbarSupDepth_Req_FIU_SMFL_REQ_CTR_SEATS_Increase +#define FIU_SMFL_SeatLumbarSupDepth_Req_FIU_SMFL_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMFL_SeatLumbarSupDepth_Req_FIU_SMFL_REQ_CTR_SEATS_No_action +#define FIU_SMFL_SeatLumbarSupDepth_Req_FIU_SMFL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFL_BackRestWidth_Req signal + +#ifndef FIU_SMFL_BackRestWidth_Req_FIU_SMFL_REQ_CTR_SEATS_Reserved +#define FIU_SMFL_BackRestWidth_Req_FIU_SMFL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMFL_BackRestWidth_Req_FIU_SMFL_REQ_CTR_SEATS_Decrease +#define FIU_SMFL_BackRestWidth_Req_FIU_SMFL_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMFL_BackRestWidth_Req_FIU_SMFL_REQ_CTR_SEATS_Increase +#define FIU_SMFL_BackRestWidth_Req_FIU_SMFL_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMFL_BackRestWidth_Req_FIU_SMFL_REQ_CTR_SEATS_No_action +#define FIU_SMFL_BackRestWidth_Req_FIU_SMFL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFL_SeatCushionSupport_Req signal + +#ifndef FIU_SMFL_SeatCushionSupport_Req_FIU_SMFL_REQ_CTR_SEATS_Reserved +#define FIU_SMFL_SeatCushionSupport_Req_FIU_SMFL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMFL_SeatCushionSupport_Req_FIU_SMFL_REQ_CTR_SEATS_Decrease +#define FIU_SMFL_SeatCushionSupport_Req_FIU_SMFL_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMFL_SeatCushionSupport_Req_FIU_SMFL_REQ_CTR_SEATS_Increase +#define FIU_SMFL_SeatCushionSupport_Req_FIU_SMFL_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMFL_SeatCushionSupport_Req_FIU_SMFL_REQ_CTR_SEATS_No_action +#define FIU_SMFL_SeatCushionSupport_Req_FIU_SMFL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFL_SeatMassage_Req signal + +#ifndef FIU_SMFL_SeatMassage_Req_FIU_SMFL_REQ_CTR_SEATS_Reserved +#define FIU_SMFL_SeatMassage_Req_FIU_SMFL_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMFL_SeatMassage_Req_FIU_SMFL_REQ_CTR_SEATS_Massage_ON +#define FIU_SMFL_SeatMassage_Req_FIU_SMFL_REQ_CTR_SEATS_Massage_ON (2) +#endif + +#ifndef FIU_SMFL_SeatMassage_Req_FIU_SMFL_REQ_CTR_SEATS_Massage_OFF +#define FIU_SMFL_SeatMassage_Req_FIU_SMFL_REQ_CTR_SEATS_Massage_OFF (1) +#endif + +#ifndef FIU_SMFL_SeatMassage_Req_FIU_SMFL_REQ_CTR_SEATS_No_action +#define FIU_SMFL_SeatMassage_Req_FIU_SMFL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFL_SeatVentilation_Req signal + +#ifndef FIU_SMFL_SeatVentilation_Req_FIU_SMFL_REQ_CTR_SEATS_High_power +#define FIU_SMFL_SeatVentilation_Req_FIU_SMFL_REQ_CTR_SEATS_High_power (3) +#endif + +#ifndef FIU_SMFL_SeatVentilation_Req_FIU_SMFL_REQ_CTR_SEATS_Middle_power +#define FIU_SMFL_SeatVentilation_Req_FIU_SMFL_REQ_CTR_SEATS_Middle_power (2) +#endif + +#ifndef FIU_SMFL_SeatVentilation_Req_FIU_SMFL_REQ_CTR_SEATS_Low_power +#define FIU_SMFL_SeatVentilation_Req_FIU_SMFL_REQ_CTR_SEATS_Low_power (1) +#endif + +#ifndef FIU_SMFL_SeatVentilation_Req_FIU_SMFL_REQ_CTR_SEATS_Off +#define FIU_SMFL_SeatVentilation_Req_FIU_SMFL_REQ_CTR_SEATS_Off (0) +#endif + + +// Value tables for @FIU_SMFL_SeatVentBalance_Req signal + +#ifndef FIU_SMFL_SeatVentBalance_Req_FIU_SMFL_REQ_CTR_SEATS_Backrest_100_Cushion_00_3 +#define FIU_SMFL_SeatVentBalance_Req_FIU_SMFL_REQ_CTR_SEATS_Backrest_100_Cushion_00_3 (7) +#endif + +#ifndef FIU_SMFL_SeatVentBalance_Req_FIU_SMFL_REQ_CTR_SEATS_Backrest_100_Cushion_33_2 +#define FIU_SMFL_SeatVentBalance_Req_FIU_SMFL_REQ_CTR_SEATS_Backrest_100_Cushion_33_2 (6) +#endif + +#ifndef FIU_SMFL_SeatVentBalance_Req_FIU_SMFL_REQ_CTR_SEATS_Backrest_100_Cushion_67_1 +#define FIU_SMFL_SeatVentBalance_Req_FIU_SMFL_REQ_CTR_SEATS_Backrest_100_Cushion_67_1 (5) +#endif + +#ifndef FIU_SMFL_SeatVentBalance_Req_FIU_SMFL_REQ_CTR_SEATS_Backrest_100_Cushion_100_0 +#define FIU_SMFL_SeatVentBalance_Req_FIU_SMFL_REQ_CTR_SEATS_Backrest_100_Cushion_100_0 (4) +#endif + +#ifndef FIU_SMFL_SeatVentBalance_Req_FIU_SMFL_REQ_CTR_SEATS_Backrest_67_Cushion_100_1 +#define FIU_SMFL_SeatVentBalance_Req_FIU_SMFL_REQ_CTR_SEATS_Backrest_67_Cushion_100_1 (3) +#endif + +#ifndef FIU_SMFL_SeatVentBalance_Req_FIU_SMFL_REQ_CTR_SEATS_Backrest_33_Cushion_100_2 +#define FIU_SMFL_SeatVentBalance_Req_FIU_SMFL_REQ_CTR_SEATS_Backrest_33_Cushion_100_2 (2) +#endif + +#ifndef FIU_SMFL_SeatVentBalance_Req_FIU_SMFL_REQ_CTR_SEATS_Backrest_00_Cushion_100_3 +#define FIU_SMFL_SeatVentBalance_Req_FIU_SMFL_REQ_CTR_SEATS_Backrest_00_Cushion_100_3 (1) +#endif + +#ifndef FIU_SMFL_SeatVentBalance_Req_FIU_SMFL_REQ_CTR_SEATS_No_action +#define FIU_SMFL_SeatVentBalance_Req_FIU_SMFL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFL_SeatMassageIntence_Req signal + +#ifndef FIU_SMFL_SeatMassageIntence_Req_FIU_SMFL_REQ_CTR_SEATS_High_power +#define FIU_SMFL_SeatMassageIntence_Req_FIU_SMFL_REQ_CTR_SEATS_High_power (3) +#endif + +#ifndef FIU_SMFL_SeatMassageIntence_Req_FIU_SMFL_REQ_CTR_SEATS_Middle_power +#define FIU_SMFL_SeatMassageIntence_Req_FIU_SMFL_REQ_CTR_SEATS_Middle_power (2) +#endif + +#ifndef FIU_SMFL_SeatMassageIntence_Req_FIU_SMFL_REQ_CTR_SEATS_Low_power +#define FIU_SMFL_SeatMassageIntence_Req_FIU_SMFL_REQ_CTR_SEATS_Low_power (1) +#endif + +#ifndef FIU_SMFL_SeatMassageIntence_Req_FIU_SMFL_REQ_CTR_SEATS_No_action +#define FIU_SMFL_SeatMassageIntence_Req_FIU_SMFL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFL_SeatHeating_Req signal + +#ifndef FIU_SMFL_SeatHeating_Req_FIU_SMFL_REQ_CTR_SEATS_High_power +#define FIU_SMFL_SeatHeating_Req_FIU_SMFL_REQ_CTR_SEATS_High_power (3) +#endif + +#ifndef FIU_SMFL_SeatHeating_Req_FIU_SMFL_REQ_CTR_SEATS_Normal_power +#define FIU_SMFL_SeatHeating_Req_FIU_SMFL_REQ_CTR_SEATS_Normal_power (2) +#endif + +#ifndef FIU_SMFL_SeatHeating_Req_FIU_SMFL_REQ_CTR_SEATS_Low_power +#define FIU_SMFL_SeatHeating_Req_FIU_SMFL_REQ_CTR_SEATS_Low_power (1) +#endif + +#ifndef FIU_SMFL_SeatHeating_Req_FIU_SMFL_REQ_CTR_SEATS_Off +#define FIU_SMFL_SeatHeating_Req_FIU_SMFL_REQ_CTR_SEATS_Off (0) +#endif + + +// Value tables for @FIU_SMFL_ActiveSupport_Req signal + +#ifndef FIU_SMFL_ActiveSupport_Req_FIU_SMFL_REQ_CTR_SEATS_Active +#define FIU_SMFL_ActiveSupport_Req_FIU_SMFL_REQ_CTR_SEATS_Active (1) +#endif + +#ifndef FIU_SMFL_ActiveSupport_Req_FIU_SMFL_REQ_CTR_SEATS_Inactive +#define FIU_SMFL_ActiveSupport_Req_FIU_SMFL_REQ_CTR_SEATS_Inactive (0) +#endif + + +// Value tables for @FIU_SMFL_SeatHeatBalance_Req signal + +#ifndef FIU_SMFL_SeatHeatBalance_Req_FIU_SMFL_REQ_CTR_SEATS_Backrest_100_Cushion_00_3 +#define FIU_SMFL_SeatHeatBalance_Req_FIU_SMFL_REQ_CTR_SEATS_Backrest_100_Cushion_00_3 (7) +#endif + +#ifndef FIU_SMFL_SeatHeatBalance_Req_FIU_SMFL_REQ_CTR_SEATS_Backrest_100_Cushion_33_2 +#define FIU_SMFL_SeatHeatBalance_Req_FIU_SMFL_REQ_CTR_SEATS_Backrest_100_Cushion_33_2 (6) +#endif + +#ifndef FIU_SMFL_SeatHeatBalance_Req_FIU_SMFL_REQ_CTR_SEATS_Backrest_100_Cushion_67_1 +#define FIU_SMFL_SeatHeatBalance_Req_FIU_SMFL_REQ_CTR_SEATS_Backrest_100_Cushion_67_1 (5) +#endif + +#ifndef FIU_SMFL_SeatHeatBalance_Req_FIU_SMFL_REQ_CTR_SEATS_Backrest_100_Cushion_100_0 +#define FIU_SMFL_SeatHeatBalance_Req_FIU_SMFL_REQ_CTR_SEATS_Backrest_100_Cushion_100_0 (4) +#endif + +#ifndef FIU_SMFL_SeatHeatBalance_Req_FIU_SMFL_REQ_CTR_SEATS_Backrest_67_Cushion_100_1 +#define FIU_SMFL_SeatHeatBalance_Req_FIU_SMFL_REQ_CTR_SEATS_Backrest_67_Cushion_100_1 (3) +#endif + +#ifndef FIU_SMFL_SeatHeatBalance_Req_FIU_SMFL_REQ_CTR_SEATS_Backrest_33_Cushion_100_2 +#define FIU_SMFL_SeatHeatBalance_Req_FIU_SMFL_REQ_CTR_SEATS_Backrest_33_Cushion_100_2 (2) +#endif + +#ifndef FIU_SMFL_SeatHeatBalance_Req_FIU_SMFL_REQ_CTR_SEATS_Backrest_00_Cushion_100_3 +#define FIU_SMFL_SeatHeatBalance_Req_FIU_SMFL_REQ_CTR_SEATS_Backrest_00_Cushion_100_3 (1) +#endif + +#ifndef FIU_SMFL_SeatHeatBalance_Req_FIU_SMFL_REQ_CTR_SEATS_No_action +#define FIU_SMFL_SeatHeatBalance_Req_FIU_SMFL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFL_SeatMassageType_Req signal + +#ifndef FIU_SMFL_SeatMassageType_Req_FIU_SMFL_REQ_CTR_SEATS_Type_7_Velvet +#define FIU_SMFL_SeatMassageType_Req_FIU_SMFL_REQ_CTR_SEATS_Type_7_Velvet (7) +#endif + +#ifndef FIU_SMFL_SeatMassageType_Req_FIU_SMFL_REQ_CTR_SEATS_Type_6_Sonnet +#define FIU_SMFL_SeatMassageType_Req_FIU_SMFL_REQ_CTR_SEATS_Type_6_Sonnet (6) +#endif + +#ifndef FIU_SMFL_SeatMassageType_Req_FIU_SMFL_REQ_CTR_SEATS_Type_5_Quantum +#define FIU_SMFL_SeatMassageType_Req_FIU_SMFL_REQ_CTR_SEATS_Type_5_Quantum (5) +#endif + +#ifndef FIU_SMFL_SeatMassageType_Req_FIU_SMFL_REQ_CTR_SEATS_Type_4_Cashmere +#define FIU_SMFL_SeatMassageType_Req_FIU_SMFL_REQ_CTR_SEATS_Type_4_Cashmere (4) +#endif + +#ifndef FIU_SMFL_SeatMassageType_Req_FIU_SMFL_REQ_CTR_SEATS_Type_3_Harmony +#define FIU_SMFL_SeatMassageType_Req_FIU_SMFL_REQ_CTR_SEATS_Type_3_Harmony (3) +#endif + +#ifndef FIU_SMFL_SeatMassageType_Req_FIU_SMFL_REQ_CTR_SEATS_Type_2_Orbital +#define FIU_SMFL_SeatMassageType_Req_FIU_SMFL_REQ_CTR_SEATS_Type_2_Orbital (2) +#endif + +#ifndef FIU_SMFL_SeatMassageType_Req_FIU_SMFL_REQ_CTR_SEATS_Type_1_Insight +#define FIU_SMFL_SeatMassageType_Req_FIU_SMFL_REQ_CTR_SEATS_Type_1_Insight (1) +#endif + +#ifndef FIU_SMFL_SeatMassageType_Req_FIU_SMFL_REQ_CTR_SEATS_No_action +#define FIU_SMFL_SeatMassageType_Req_FIU_SMFL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFL_BackrestMassageType_Req signal + +#ifndef FIU_SMFL_BackrestMassageType_Req_FIU_SMFL_REQ_CTR_SEATS_Reserved +#define FIU_SMFL_BackrestMassageType_Req_FIU_SMFL_REQ_CTR_SEATS_Reserved (7) +#endif + +#ifndef FIU_SMFL_BackrestMassageType_Req_FIU_SMFL_REQ_CTR_SEATS_Reserved +#define FIU_SMFL_BackrestMassageType_Req_FIU_SMFL_REQ_CTR_SEATS_Reserved (6) +#endif + +#ifndef FIU_SMFL_BackrestMassageType_Req_FIU_SMFL_REQ_CTR_SEATS_Type_5_Elegy +#define FIU_SMFL_BackrestMassageType_Req_FIU_SMFL_REQ_CTR_SEATS_Type_5_Elegy (5) +#endif + +#ifndef FIU_SMFL_BackrestMassageType_Req_FIU_SMFL_REQ_CTR_SEATS_Type_4_Caprice +#define FIU_SMFL_BackrestMassageType_Req_FIU_SMFL_REQ_CTR_SEATS_Type_4_Caprice (4) +#endif + +#ifndef FIU_SMFL_BackrestMassageType_Req_FIU_SMFL_REQ_CTR_SEATS_Type_3_Pulse +#define FIU_SMFL_BackrestMassageType_Req_FIU_SMFL_REQ_CTR_SEATS_Type_3_Pulse (3) +#endif + +#ifndef FIU_SMFL_BackrestMassageType_Req_FIU_SMFL_REQ_CTR_SEATS_Type_2_Energy +#define FIU_SMFL_BackrestMassageType_Req_FIU_SMFL_REQ_CTR_SEATS_Type_2_Energy (2) +#endif + +#ifndef FIU_SMFL_BackrestMassageType_Req_FIU_SMFL_REQ_CTR_SEATS_Type_1_Synchrony +#define FIU_SMFL_BackrestMassageType_Req_FIU_SMFL_REQ_CTR_SEATS_Type_1_Synchrony (1) +#endif + +#ifndef FIU_SMFL_BackrestMassageType_Req_FIU_SMFL_REQ_CTR_SEATS_No_action +#define FIU_SMFL_BackrestMassageType_Req_FIU_SMFL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFL_ComfortMode_Req signal + +#ifndef FIU_SMFL_ComfortMode_Req_FIU_SMFL_REQ_CTR_SEATS_Active +#define FIU_SMFL_ComfortMode_Req_FIU_SMFL_REQ_CTR_SEATS_Active (1) +#endif + +#ifndef FIU_SMFL_ComfortMode_Req_FIU_SMFL_REQ_CTR_SEATS_Inactive +#define FIU_SMFL_ComfortMode_Req_FIU_SMFL_REQ_CTR_SEATS_Inactive (0) +#endif + + +// Value tables for @FIU_SMFL_ComfortScenario_Req signal + +#ifndef FIU_SMFL_ComfortScenario_Req_FIU_SMFL_REQ_CTR_SEATS_Type_3 +#define FIU_SMFL_ComfortScenario_Req_FIU_SMFL_REQ_CTR_SEATS_Type_3 (3) +#endif + +#ifndef FIU_SMFL_ComfortScenario_Req_FIU_SMFL_REQ_CTR_SEATS_Type_2 +#define FIU_SMFL_ComfortScenario_Req_FIU_SMFL_REQ_CTR_SEATS_Type_2 (2) +#endif + +#ifndef FIU_SMFL_ComfortScenario_Req_FIU_SMFL_REQ_CTR_SEATS_Type_1 +#define FIU_SMFL_ComfortScenario_Req_FIU_SMFL_REQ_CTR_SEATS_Type_1 (1) +#endif + +#ifndef FIU_SMFL_ComfortScenario_Req_FIU_SMFL_REQ_CTR_SEATS_No_action +#define FIU_SMFL_ComfortScenario_Req_FIU_SMFL_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMFL_CarpetHeat_Req signal + +#ifndef FIU_SMFL_CarpetHeat_Req_FIU_SMFL_REQ_CTR_SEATS_Active +#define FIU_SMFL_CarpetHeat_Req_FIU_SMFL_REQ_CTR_SEATS_Active (1) +#endif + +#ifndef FIU_SMFL_CarpetHeat_Req_FIU_SMFL_REQ_CTR_SEATS_Inactive +#define FIU_SMFL_CarpetHeat_Req_FIU_SMFL_REQ_CTR_SEATS_Inactive (0) +#endif + + +// Value tables for @FIU_SMFL_TimerMassage_Req signal + +#ifndef FIU_SMFL_TimerMassage_Req_FIU_SMFL_REQ_CTR_SEATS_Reseved +#define FIU_SMFL_TimerMassage_Req_FIU_SMFL_REQ_CTR_SEATS_Reseved (7) +#endif + +#ifndef FIU_SMFL_TimerMassage_Req_FIU_SMFL_REQ_CTR_SEATS__min +#define FIU_SMFL_TimerMassage_Req_FIU_SMFL_REQ_CTR_SEATS__min (6) +#endif + +#ifndef FIU_SMFL_TimerMassage_Req_FIU_SMFL_REQ_CTR_SEATS__min +#define FIU_SMFL_TimerMassage_Req_FIU_SMFL_REQ_CTR_SEATS__min (5) +#endif + +#ifndef FIU_SMFL_TimerMassage_Req_FIU_SMFL_REQ_CTR_SEATS__min +#define FIU_SMFL_TimerMassage_Req_FIU_SMFL_REQ_CTR_SEATS__min (4) +#endif + +#ifndef FIU_SMFL_TimerMassage_Req_FIU_SMFL_REQ_CTR_SEATS__min +#define FIU_SMFL_TimerMassage_Req_FIU_SMFL_REQ_CTR_SEATS__min (3) +#endif + +#ifndef FIU_SMFL_TimerMassage_Req_FIU_SMFL_REQ_CTR_SEATS__min +#define FIU_SMFL_TimerMassage_Req_FIU_SMFL_REQ_CTR_SEATS__min (2) +#endif + +#ifndef FIU_SMFL_TimerMassage_Req_FIU_SMFL_REQ_CTR_SEATS__min +#define FIU_SMFL_TimerMassage_Req_FIU_SMFL_REQ_CTR_SEATS__min (1) +#endif + +#ifndef FIU_SMFL_TimerMassage_Req_FIU_SMFL_REQ_CTR_SEATS_No_action +#define FIU_SMFL_TimerMassage_Req_FIU_SMFL_REQ_CTR_SEATS_No_action (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Signal for regulation Seat Height FL + // (FL seat base height regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFL_SeatHeight_Req : 2; // Bits= 2 + + // Signal for regulation FL head rest height + // (FL headrest height regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFL_HeadRestHeight_Req : 2; // Bits= 2 + + // Signal for regulation FL seat longitudinal + // (FL seat base longitudinal regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFL_SeatLongitunalReq : 2; // Bits= 2 + + // Signal for regulation FL seat inclination + // (FL headrest depth regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFL_SeatHeadRestInclin_Req : 2; // Bits= 2 + + // Signal for regulation FL seat surface longitudinal + // (FL seat pillow longitudinal regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFL_SeatSurfaceLong_Req : 2; // Bits= 2 + + // Signal for regulation FL seat leg support height + // (FL seat leg support height regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFL_SeatLegSupportH_Req : 2; // Bits= 2 + + // Signal for regulation FL seat leg support longitudinal + // (FL seat leg support longitudinal regulation request, RESERVE) + // 3 : "Resertved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFL_SeatLegSupportLong_Req : 2; // Bits= 2 + + // Signal for regulation FL seat inclination + // (FL seat pillow inclination regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFL_SeatInclination_Req : 2; // Bits= 2 + + // Signal for regulation FL seat backrest lnclination + // (FL backrest angle regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFL_SeatBackRestInc_Req : 2; // Bits= 2 + + // Signal for regulation FL seat lumbar support height + // (FL backrest lumbar support height regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFL_SeatLumbarSupHeight_Req : 2; // Bits= 2 + + // Signal for regulation FL seat backrest head inclination + // (FL backrest should support regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFL_SeatBackRestHeadInc_Req : 2; // Bits= 2 + + // Signal for regulation FL seat lumbar support depth + // (FL backrest lumbar support depth regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFL_SeatLumbarSupDepth_Req : 2; // Bits= 2 + + // Signal for regulation FL seat backrest width + // (FL backrest lateral support regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFL_BackRestWidth_Req : 2; // Bits= 2 + + // Signal for regulation FL seat cushion support + // (FL seat cushion side lateral support regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFL_SeatCushionSupport_Req : 2; // Bits= 2 + + // Signal for seat massage activation + // (FL seat massage request) + // 3 : "Reserved" + // 2 : "Massage ON" + // 1 : "Massage OFF" + // 0 : "No action" + uint8_t FIU_SMFL_SeatMassage_Req : 2; // Bits= 2 + + // Signal for ventilation activation mode + // (FL seat ventilation request) + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "Off" + uint8_t FIU_SMFL_SeatVentilation_Req : 2; // Bits= 2 + + // Signal for ventilation balance mode + // (FL seat ventilation balance request) + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 00%, Cushion 100%: -3" + // 0 : "No action" + uint8_t FIU_SMFL_SeatVentBalance_Req : 3; // Bits= 3 + + // Signal for seat massage intencity regulation + // (FL seat massage intencity request) + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "No action" + uint8_t FIU_SMFL_SeatMassageIntence_Req : 2; // Bits= 2 + + // Signal for seat heating activation mode + // (FL seat heating request) + // 3 : "High power" + // 2 : "Normal power" + // 1 : "Low power" + // 0 : "Off" + uint8_t FIU_SMFL_SeatHeating_Req : 2; // Bits= 2 + + // Active lateral support request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_SMFL_ActiveSupport_Req : 1; // Bits= 1 + + // Signal for seat heating balance + // (FL seat heating balance request) + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 00%, Cushion 100%: -3" + // 0 : "No action" + uint8_t FIU_SMFL_SeatHeatBalance_Req : 3; // Bits= 3 + + // Signal for seat massage type (mode) + // (FL seat massage type request) + // 7 : "Type 7 (Velvet)" + // 6 : "Type 6 (Sonnet)" + // 5 : "Type 5 (Quantum)" + // 4 : "Type 4 (Cashmere)" + // 3 : "Type 3 (Harmony)" + // 2 : "Type 2 (Orbital)" + // 1 : "Type 1 (Insight)" + // 0 : "No action" + uint8_t FIU_SMFL_SeatMassageType_Req : 3; // Bits= 3 + + // Signal for backrest massage type (mode) + // (FL backrest massage type command) + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Type 5 (Elegy)" + // 4 : "Type 4 (Caprice)" + // 3 : "Type 3 (Pulse)" + // 2 : "Type 2 (Energy)" + // 1 : "Type 1 (Synchrony)" + // 0 : "No action" + uint8_t FIU_SMFL_BackrestMassageType_Req : 3; // Bits= 3 + + // FL comfort mode request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_SMFL_ComfortMode_Req : 1; // Bits= 1 + + // FL comfort mode scenario request + // 3 : "Type 3" + // 2 : "Type 2" + // 1 : "Type 1" + // 0 : "No action" + uint8_t FIU_SMFL_ComfortScenario_Req : 2; // Bits= 2 + + // FL carpet heating request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_SMFL_CarpetHeat_Req : 1; // Bits= 1 + + // Signal for setting the massage timer + // 7 : "Reseved" + // 6 : "30 min" + // 5 : "25 min" + // 4 : "20 min" + // 3 : "15 min" + // 2 : "10 min" + // 1 : "5 min" + // 0 : "No action" + uint8_t FIU_SMFL_TimerMassage_Req : 3; // Bits= 3 + +#else + + // Signal for regulation Seat Height FL + // (FL seat base height regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFL_SeatHeight_Req; // Bits= 2 + + // Signal for regulation FL head rest height + // (FL headrest height regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFL_HeadRestHeight_Req; // Bits= 2 + + // Signal for regulation FL seat longitudinal + // (FL seat base longitudinal regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFL_SeatLongitunalReq; // Bits= 2 + + // Signal for regulation FL seat inclination + // (FL headrest depth regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFL_SeatHeadRestInclin_Req; // Bits= 2 + + // Signal for regulation FL seat surface longitudinal + // (FL seat pillow longitudinal regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFL_SeatSurfaceLong_Req; // Bits= 2 + + // Signal for regulation FL seat leg support height + // (FL seat leg support height regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFL_SeatLegSupportH_Req; // Bits= 2 + + // Signal for regulation FL seat leg support longitudinal + // (FL seat leg support longitudinal regulation request, RESERVE) + // 3 : "Resertved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFL_SeatLegSupportLong_Req; // Bits= 2 + + // Signal for regulation FL seat inclination + // (FL seat pillow inclination regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFL_SeatInclination_Req; // Bits= 2 + + // Signal for regulation FL seat backrest lnclination + // (FL backrest angle regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFL_SeatBackRestInc_Req; // Bits= 2 + + // Signal for regulation FL seat lumbar support height + // (FL backrest lumbar support height regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFL_SeatLumbarSupHeight_Req; // Bits= 2 + + // Signal for regulation FL seat backrest head inclination + // (FL backrest should support regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFL_SeatBackRestHeadInc_Req; // Bits= 2 + + // Signal for regulation FL seat lumbar support depth + // (FL backrest lumbar support depth regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFL_SeatLumbarSupDepth_Req; // Bits= 2 + + // Signal for regulation FL seat backrest width + // (FL backrest lateral support regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFL_BackRestWidth_Req; // Bits= 2 + + // Signal for regulation FL seat cushion support + // (FL seat cushion side lateral support regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMFL_SeatCushionSupport_Req; // Bits= 2 + + // Signal for seat massage activation + // (FL seat massage request) + // 3 : "Reserved" + // 2 : "Massage ON" + // 1 : "Massage OFF" + // 0 : "No action" + uint8_t FIU_SMFL_SeatMassage_Req; // Bits= 2 + + // Signal for ventilation activation mode + // (FL seat ventilation request) + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "Off" + uint8_t FIU_SMFL_SeatVentilation_Req; // Bits= 2 + + // Signal for ventilation balance mode + // (FL seat ventilation balance request) + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 00%, Cushion 100%: -3" + // 0 : "No action" + uint8_t FIU_SMFL_SeatVentBalance_Req; // Bits= 3 + + // Signal for seat massage intencity regulation + // (FL seat massage intencity request) + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "No action" + uint8_t FIU_SMFL_SeatMassageIntence_Req; // Bits= 2 + + // Signal for seat heating activation mode + // (FL seat heating request) + // 3 : "High power" + // 2 : "Normal power" + // 1 : "Low power" + // 0 : "Off" + uint8_t FIU_SMFL_SeatHeating_Req; // Bits= 2 + + // Active lateral support request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_SMFL_ActiveSupport_Req; // Bits= 1 + + // Signal for seat heating balance + // (FL seat heating balance request) + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 00%, Cushion 100%: -3" + // 0 : "No action" + uint8_t FIU_SMFL_SeatHeatBalance_Req; // Bits= 3 + + // Signal for seat massage type (mode) + // (FL seat massage type request) + // 7 : "Type 7 (Velvet)" + // 6 : "Type 6 (Sonnet)" + // 5 : "Type 5 (Quantum)" + // 4 : "Type 4 (Cashmere)" + // 3 : "Type 3 (Harmony)" + // 2 : "Type 2 (Orbital)" + // 1 : "Type 1 (Insight)" + // 0 : "No action" + uint8_t FIU_SMFL_SeatMassageType_Req; // Bits= 3 + + // Signal for backrest massage type (mode) + // (FL backrest massage type command) + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Type 5 (Elegy)" + // 4 : "Type 4 (Caprice)" + // 3 : "Type 3 (Pulse)" + // 2 : "Type 2 (Energy)" + // 1 : "Type 1 (Synchrony)" + // 0 : "No action" + uint8_t FIU_SMFL_BackrestMassageType_Req; // Bits= 3 + + // FL comfort mode request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_SMFL_ComfortMode_Req; // Bits= 1 + + // FL comfort mode scenario request + // 3 : "Type 3" + // 2 : "Type 2" + // 1 : "Type 1" + // 0 : "No action" + uint8_t FIU_SMFL_ComfortScenario_Req; // Bits= 2 + + // FL carpet heating request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_SMFL_CarpetHeat_Req; // Bits= 1 + + // Signal for setting the massage timer + // 7 : "Reseved" + // 6 : "30 min" + // 5 : "25 min" + // 4 : "20 min" + // 3 : "15 min" + // 2 : "10 min" + // 1 : "5 min" + // 0 : "No action" + uint8_t FIU_SMFL_TimerMassage_Req; // Bits= 3 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} FIU_SMFL_REQ_CTR_SEATS_t; + +// def @FIU_SMRR_REQ_CTR_SEATS CAN Message (1364 0x554) +#define FIU_SMRR_REQ_CTR_SEATS_IDE (0U) +#define FIU_SMRR_REQ_CTR_SEATS_DLC (7U) +#define FIU_SMRR_REQ_CTR_SEATS_CANID (0x554U) + +// Value tables for @FIU_SMRR_SeatHeight_Req signal + +#ifndef FIU_SMRR_SeatHeight_Req_FIU_SMRR_REQ_CTR_SEATS_Reserved +#define FIU_SMRR_SeatHeight_Req_FIU_SMRR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMRR_SeatHeight_Req_FIU_SMRR_REQ_CTR_SEATS_Decrease +#define FIU_SMRR_SeatHeight_Req_FIU_SMRR_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMRR_SeatHeight_Req_FIU_SMRR_REQ_CTR_SEATS_Increase +#define FIU_SMRR_SeatHeight_Req_FIU_SMRR_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMRR_SeatHeight_Req_FIU_SMRR_REQ_CTR_SEATS_No_action +#define FIU_SMRR_SeatHeight_Req_FIU_SMRR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRR_HeadRest_Height_Req signal + +#ifndef FIU_SMRR_HeadRest_Height_Req_FIU_SMRR_REQ_CTR_SEATS_Reserved +#define FIU_SMRR_HeadRest_Height_Req_FIU_SMRR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMRR_HeadRest_Height_Req_FIU_SMRR_REQ_CTR_SEATS_Decrease +#define FIU_SMRR_HeadRest_Height_Req_FIU_SMRR_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMRR_HeadRest_Height_Req_FIU_SMRR_REQ_CTR_SEATS_Increase +#define FIU_SMRR_HeadRest_Height_Req_FIU_SMRR_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMRR_HeadRest_Height_Req_FIU_SMRR_REQ_CTR_SEATS_No_action +#define FIU_SMRR_HeadRest_Height_Req_FIU_SMRR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRR_SeatLongitunalReq signal + +#ifndef FIU_SMRR_SeatLongitunalReq_FIU_SMRR_REQ_CTR_SEATS_Reserved +#define FIU_SMRR_SeatLongitunalReq_FIU_SMRR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMRR_SeatLongitunalReq_FIU_SMRR_REQ_CTR_SEATS_Decrease +#define FIU_SMRR_SeatLongitunalReq_FIU_SMRR_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMRR_SeatLongitunalReq_FIU_SMRR_REQ_CTR_SEATS_Increase +#define FIU_SMRR_SeatLongitunalReq_FIU_SMRR_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMRR_SeatLongitunalReq_FIU_SMRR_REQ_CTR_SEATS_No_action +#define FIU_SMRR_SeatLongitunalReq_FIU_SMRR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRR_SeatHeadRestInclin_Req signal + +#ifndef FIU_SMRR_SeatHeadRestInclin_Req_FIU_SMRR_REQ_CTR_SEATS_Reserved +#define FIU_SMRR_SeatHeadRestInclin_Req_FIU_SMRR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMRR_SeatHeadRestInclin_Req_FIU_SMRR_REQ_CTR_SEATS_Decrease +#define FIU_SMRR_SeatHeadRestInclin_Req_FIU_SMRR_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMRR_SeatHeadRestInclin_Req_FIU_SMRR_REQ_CTR_SEATS_Increase +#define FIU_SMRR_SeatHeadRestInclin_Req_FIU_SMRR_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMRR_SeatHeadRestInclin_Req_FIU_SMRR_REQ_CTR_SEATS_No_action +#define FIU_SMRR_SeatHeadRestInclin_Req_FIU_SMRR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRR_SeatSurfaceLong_Req signal + +#ifndef FIU_SMRR_SeatSurfaceLong_Req_FIU_SMRR_REQ_CTR_SEATS_Reserved +#define FIU_SMRR_SeatSurfaceLong_Req_FIU_SMRR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMRR_SeatSurfaceLong_Req_FIU_SMRR_REQ_CTR_SEATS_Decrease +#define FIU_SMRR_SeatSurfaceLong_Req_FIU_SMRR_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMRR_SeatSurfaceLong_Req_FIU_SMRR_REQ_CTR_SEATS_Increase +#define FIU_SMRR_SeatSurfaceLong_Req_FIU_SMRR_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMRR_SeatSurfaceLong_Req_FIU_SMRR_REQ_CTR_SEATS_No_action +#define FIU_SMRR_SeatSurfaceLong_Req_FIU_SMRR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRR_SeatLegSupportH_Req signal + +#ifndef FIU_SMRR_SeatLegSupportH_Req_FIU_SMRR_REQ_CTR_SEATS_Reserved +#define FIU_SMRR_SeatLegSupportH_Req_FIU_SMRR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMRR_SeatLegSupportH_Req_FIU_SMRR_REQ_CTR_SEATS_Decrease +#define FIU_SMRR_SeatLegSupportH_Req_FIU_SMRR_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMRR_SeatLegSupportH_Req_FIU_SMRR_REQ_CTR_SEATS_Increase +#define FIU_SMRR_SeatLegSupportH_Req_FIU_SMRR_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMRR_SeatLegSupportH_Req_FIU_SMRR_REQ_CTR_SEATS_No_action +#define FIU_SMRR_SeatLegSupportH_Req_FIU_SMRR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRR_SeatLegSupportLong_Req signal + +#ifndef FIU_SMRR_SeatLegSupportLong_Req_FIU_SMRR_REQ_CTR_SEATS_Resertved +#define FIU_SMRR_SeatLegSupportLong_Req_FIU_SMRR_REQ_CTR_SEATS_Resertved (3) +#endif + +#ifndef FIU_SMRR_SeatLegSupportLong_Req_FIU_SMRR_REQ_CTR_SEATS_Decrease +#define FIU_SMRR_SeatLegSupportLong_Req_FIU_SMRR_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMRR_SeatLegSupportLong_Req_FIU_SMRR_REQ_CTR_SEATS_Increase +#define FIU_SMRR_SeatLegSupportLong_Req_FIU_SMRR_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMRR_SeatLegSupportLong_Req_FIU_SMRR_REQ_CTR_SEATS_No_action +#define FIU_SMRR_SeatLegSupportLong_Req_FIU_SMRR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRR_SeatInclination_Req signal + +#ifndef FIU_SMRR_SeatInclination_Req_FIU_SMRR_REQ_CTR_SEATS_Reserved +#define FIU_SMRR_SeatInclination_Req_FIU_SMRR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMRR_SeatInclination_Req_FIU_SMRR_REQ_CTR_SEATS_Decrease +#define FIU_SMRR_SeatInclination_Req_FIU_SMRR_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMRR_SeatInclination_Req_FIU_SMRR_REQ_CTR_SEATS_Increase +#define FIU_SMRR_SeatInclination_Req_FIU_SMRR_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMRR_SeatInclination_Req_FIU_SMRR_REQ_CTR_SEATS_No_action +#define FIU_SMRR_SeatInclination_Req_FIU_SMRR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRR_SeatBackRestInc_Req signal + +#ifndef FIU_SMRR_SeatBackRestInc_Req_FIU_SMRR_REQ_CTR_SEATS_Reserved +#define FIU_SMRR_SeatBackRestInc_Req_FIU_SMRR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMRR_SeatBackRestInc_Req_FIU_SMRR_REQ_CTR_SEATS_Decrease +#define FIU_SMRR_SeatBackRestInc_Req_FIU_SMRR_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMRR_SeatBackRestInc_Req_FIU_SMRR_REQ_CTR_SEATS_Increase +#define FIU_SMRR_SeatBackRestInc_Req_FIU_SMRR_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMRR_SeatBackRestInc_Req_FIU_SMRR_REQ_CTR_SEATS_No_action +#define FIU_SMRR_SeatBackRestInc_Req_FIU_SMRR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRR_SeatLumbarSupportH_Req signal + +#ifndef FIU_SMRR_SeatLumbarSupportH_Req_FIU_SMRR_REQ_CTR_SEATS_Reserved +#define FIU_SMRR_SeatLumbarSupportH_Req_FIU_SMRR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMRR_SeatLumbarSupportH_Req_FIU_SMRR_REQ_CTR_SEATS_Decrease +#define FIU_SMRR_SeatLumbarSupportH_Req_FIU_SMRR_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMRR_SeatLumbarSupportH_Req_FIU_SMRR_REQ_CTR_SEATS_Increase +#define FIU_SMRR_SeatLumbarSupportH_Req_FIU_SMRR_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMRR_SeatLumbarSupportH_Req_FIU_SMRR_REQ_CTR_SEATS_No_action +#define FIU_SMRR_SeatLumbarSupportH_Req_FIU_SMRR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRR_SeatBackRestHeadInc_Req signal + +#ifndef FIU_SMRR_SeatBackRestHeadInc_Req_FIU_SMRR_REQ_CTR_SEATS_Reserved +#define FIU_SMRR_SeatBackRestHeadInc_Req_FIU_SMRR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMRR_SeatBackRestHeadInc_Req_FIU_SMRR_REQ_CTR_SEATS_Decrease +#define FIU_SMRR_SeatBackRestHeadInc_Req_FIU_SMRR_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMRR_SeatBackRestHeadInc_Req_FIU_SMRR_REQ_CTR_SEATS_Increase +#define FIU_SMRR_SeatBackRestHeadInc_Req_FIU_SMRR_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMRR_SeatBackRestHeadInc_Req_FIU_SMRR_REQ_CTR_SEATS_No_action +#define FIU_SMRR_SeatBackRestHeadInc_Req_FIU_SMRR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRR_SeatLumbarSupDepth_Req signal + +#ifndef FIU_SMRR_SeatLumbarSupDepth_Req_FIU_SMRR_REQ_CTR_SEATS_Reserved +#define FIU_SMRR_SeatLumbarSupDepth_Req_FIU_SMRR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMRR_SeatLumbarSupDepth_Req_FIU_SMRR_REQ_CTR_SEATS_Decrease +#define FIU_SMRR_SeatLumbarSupDepth_Req_FIU_SMRR_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMRR_SeatLumbarSupDepth_Req_FIU_SMRR_REQ_CTR_SEATS_Increase +#define FIU_SMRR_SeatLumbarSupDepth_Req_FIU_SMRR_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMRR_SeatLumbarSupDepth_Req_FIU_SMRR_REQ_CTR_SEATS_No_action +#define FIU_SMRR_SeatLumbarSupDepth_Req_FIU_SMRR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRR_BackRestWidth_Req signal + +#ifndef FIU_SMRR_BackRestWidth_Req_FIU_SMRR_REQ_CTR_SEATS_Reserved +#define FIU_SMRR_BackRestWidth_Req_FIU_SMRR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMRR_BackRestWidth_Req_FIU_SMRR_REQ_CTR_SEATS_Decrease +#define FIU_SMRR_BackRestWidth_Req_FIU_SMRR_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMRR_BackRestWidth_Req_FIU_SMRR_REQ_CTR_SEATS_Increase +#define FIU_SMRR_BackRestWidth_Req_FIU_SMRR_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMRR_BackRestWidth_Req_FIU_SMRR_REQ_CTR_SEATS_No_action +#define FIU_SMRR_BackRestWidth_Req_FIU_SMRR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRR_SeatCushionSupport_Req signal + +#ifndef FIU_SMRR_SeatCushionSupport_Req_FIU_SMRR_REQ_CTR_SEATS_Reserved +#define FIU_SMRR_SeatCushionSupport_Req_FIU_SMRR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMRR_SeatCushionSupport_Req_FIU_SMRR_REQ_CTR_SEATS_Decrease +#define FIU_SMRR_SeatCushionSupport_Req_FIU_SMRR_REQ_CTR_SEATS_Decrease (2) +#endif + +#ifndef FIU_SMRR_SeatCushionSupport_Req_FIU_SMRR_REQ_CTR_SEATS_Increase +#define FIU_SMRR_SeatCushionSupport_Req_FIU_SMRR_REQ_CTR_SEATS_Increase (1) +#endif + +#ifndef FIU_SMRR_SeatCushionSupport_Req_FIU_SMRR_REQ_CTR_SEATS_No_action +#define FIU_SMRR_SeatCushionSupport_Req_FIU_SMRR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRR_SeatMassage_Req signal + +#ifndef FIU_SMRR_SeatMassage_Req_FIU_SMRR_REQ_CTR_SEATS_Reserved +#define FIU_SMRR_SeatMassage_Req_FIU_SMRR_REQ_CTR_SEATS_Reserved (3) +#endif + +#ifndef FIU_SMRR_SeatMassage_Req_FIU_SMRR_REQ_CTR_SEATS_Massage_ON +#define FIU_SMRR_SeatMassage_Req_FIU_SMRR_REQ_CTR_SEATS_Massage_ON (2) +#endif + +#ifndef FIU_SMRR_SeatMassage_Req_FIU_SMRR_REQ_CTR_SEATS_Massage_OFF +#define FIU_SMRR_SeatMassage_Req_FIU_SMRR_REQ_CTR_SEATS_Massage_OFF (1) +#endif + +#ifndef FIU_SMRR_SeatMassage_Req_FIU_SMRR_REQ_CTR_SEATS_No_action +#define FIU_SMRR_SeatMassage_Req_FIU_SMRR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRR_SeatVentilation_Req signal + +#ifndef FIU_SMRR_SeatVentilation_Req_FIU_SMRR_REQ_CTR_SEATS_High_power +#define FIU_SMRR_SeatVentilation_Req_FIU_SMRR_REQ_CTR_SEATS_High_power (3) +#endif + +#ifndef FIU_SMRR_SeatVentilation_Req_FIU_SMRR_REQ_CTR_SEATS_Middle_power +#define FIU_SMRR_SeatVentilation_Req_FIU_SMRR_REQ_CTR_SEATS_Middle_power (2) +#endif + +#ifndef FIU_SMRR_SeatVentilation_Req_FIU_SMRR_REQ_CTR_SEATS_Low_power +#define FIU_SMRR_SeatVentilation_Req_FIU_SMRR_REQ_CTR_SEATS_Low_power (1) +#endif + +#ifndef FIU_SMRR_SeatVentilation_Req_FIU_SMRR_REQ_CTR_SEATS_Off +#define FIU_SMRR_SeatVentilation_Req_FIU_SMRR_REQ_CTR_SEATS_Off (0) +#endif + + +// Value tables for @FIU_SMRR_SeatVentBalance_Req signal + +#ifndef FIU_SMRR_SeatVentBalance_Req_FIU_SMRR_REQ_CTR_SEATS_Backrest_100_Cushion_00_3 +#define FIU_SMRR_SeatVentBalance_Req_FIU_SMRR_REQ_CTR_SEATS_Backrest_100_Cushion_00_3 (7) +#endif + +#ifndef FIU_SMRR_SeatVentBalance_Req_FIU_SMRR_REQ_CTR_SEATS_Backrest_100_Cushion_33_2 +#define FIU_SMRR_SeatVentBalance_Req_FIU_SMRR_REQ_CTR_SEATS_Backrest_100_Cushion_33_2 (6) +#endif + +#ifndef FIU_SMRR_SeatVentBalance_Req_FIU_SMRR_REQ_CTR_SEATS_Backrest_100_Cushion_67_1 +#define FIU_SMRR_SeatVentBalance_Req_FIU_SMRR_REQ_CTR_SEATS_Backrest_100_Cushion_67_1 (5) +#endif + +#ifndef FIU_SMRR_SeatVentBalance_Req_FIU_SMRR_REQ_CTR_SEATS_Backrest_100_Cushion_100_0 +#define FIU_SMRR_SeatVentBalance_Req_FIU_SMRR_REQ_CTR_SEATS_Backrest_100_Cushion_100_0 (4) +#endif + +#ifndef FIU_SMRR_SeatVentBalance_Req_FIU_SMRR_REQ_CTR_SEATS_Backrest_67_Cushion_100_1 +#define FIU_SMRR_SeatVentBalance_Req_FIU_SMRR_REQ_CTR_SEATS_Backrest_67_Cushion_100_1 (3) +#endif + +#ifndef FIU_SMRR_SeatVentBalance_Req_FIU_SMRR_REQ_CTR_SEATS_Backrest_33_Cushion_100_2 +#define FIU_SMRR_SeatVentBalance_Req_FIU_SMRR_REQ_CTR_SEATS_Backrest_33_Cushion_100_2 (2) +#endif + +#ifndef FIU_SMRR_SeatVentBalance_Req_FIU_SMRR_REQ_CTR_SEATS_Backrest_00_Cushion_100_3 +#define FIU_SMRR_SeatVentBalance_Req_FIU_SMRR_REQ_CTR_SEATS_Backrest_00_Cushion_100_3 (1) +#endif + +#ifndef FIU_SMRR_SeatVentBalance_Req_FIU_SMRR_REQ_CTR_SEATS_No_action +#define FIU_SMRR_SeatVentBalance_Req_FIU_SMRR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRR_SeatMassageIntence_Req signal + +#ifndef FIU_SMRR_SeatMassageIntence_Req_FIU_SMRR_REQ_CTR_SEATS_High_power +#define FIU_SMRR_SeatMassageIntence_Req_FIU_SMRR_REQ_CTR_SEATS_High_power (3) +#endif + +#ifndef FIU_SMRR_SeatMassageIntence_Req_FIU_SMRR_REQ_CTR_SEATS_Middle_power +#define FIU_SMRR_SeatMassageIntence_Req_FIU_SMRR_REQ_CTR_SEATS_Middle_power (2) +#endif + +#ifndef FIU_SMRR_SeatMassageIntence_Req_FIU_SMRR_REQ_CTR_SEATS_Low_power +#define FIU_SMRR_SeatMassageIntence_Req_FIU_SMRR_REQ_CTR_SEATS_Low_power (1) +#endif + +#ifndef FIU_SMRR_SeatMassageIntence_Req_FIU_SMRR_REQ_CTR_SEATS_No_action +#define FIU_SMRR_SeatMassageIntence_Req_FIU_SMRR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRR_SeatHeating_Req signal + +#ifndef FIU_SMRR_SeatHeating_Req_FIU_SMRR_REQ_CTR_SEATS_High_power +#define FIU_SMRR_SeatHeating_Req_FIU_SMRR_REQ_CTR_SEATS_High_power (3) +#endif + +#ifndef FIU_SMRR_SeatHeating_Req_FIU_SMRR_REQ_CTR_SEATS_Normal_power +#define FIU_SMRR_SeatHeating_Req_FIU_SMRR_REQ_CTR_SEATS_Normal_power (2) +#endif + +#ifndef FIU_SMRR_SeatHeating_Req_FIU_SMRR_REQ_CTR_SEATS_Low_power +#define FIU_SMRR_SeatHeating_Req_FIU_SMRR_REQ_CTR_SEATS_Low_power (1) +#endif + +#ifndef FIU_SMRR_SeatHeating_Req_FIU_SMRR_REQ_CTR_SEATS_Off +#define FIU_SMRR_SeatHeating_Req_FIU_SMRR_REQ_CTR_SEATS_Off (0) +#endif + + +// Value tables for @FIU_SMRR_ActiveSupport_Req signal + +#ifndef FIU_SMRR_ActiveSupport_Req_FIU_SMRR_REQ_CTR_SEATS_Active +#define FIU_SMRR_ActiveSupport_Req_FIU_SMRR_REQ_CTR_SEATS_Active (1) +#endif + +#ifndef FIU_SMRR_ActiveSupport_Req_FIU_SMRR_REQ_CTR_SEATS_Inactive +#define FIU_SMRR_ActiveSupport_Req_FIU_SMRR_REQ_CTR_SEATS_Inactive (0) +#endif + + +// Value tables for @FIU_SMRR_SeatHeatBalance_Req signal + +#ifndef FIU_SMRR_SeatHeatBalance_Req_FIU_SMRR_REQ_CTR_SEATS_Backrest_100_Cushion_00_3 +#define FIU_SMRR_SeatHeatBalance_Req_FIU_SMRR_REQ_CTR_SEATS_Backrest_100_Cushion_00_3 (7) +#endif + +#ifndef FIU_SMRR_SeatHeatBalance_Req_FIU_SMRR_REQ_CTR_SEATS_Backrest_100_Cushion_33_2 +#define FIU_SMRR_SeatHeatBalance_Req_FIU_SMRR_REQ_CTR_SEATS_Backrest_100_Cushion_33_2 (6) +#endif + +#ifndef FIU_SMRR_SeatHeatBalance_Req_FIU_SMRR_REQ_CTR_SEATS_Backrest_100_Cushion_67_1 +#define FIU_SMRR_SeatHeatBalance_Req_FIU_SMRR_REQ_CTR_SEATS_Backrest_100_Cushion_67_1 (5) +#endif + +#ifndef FIU_SMRR_SeatHeatBalance_Req_FIU_SMRR_REQ_CTR_SEATS_Backrest_100_Cushion_100_0 +#define FIU_SMRR_SeatHeatBalance_Req_FIU_SMRR_REQ_CTR_SEATS_Backrest_100_Cushion_100_0 (4) +#endif + +#ifndef FIU_SMRR_SeatHeatBalance_Req_FIU_SMRR_REQ_CTR_SEATS_Backrest_67_Cushion_100_1 +#define FIU_SMRR_SeatHeatBalance_Req_FIU_SMRR_REQ_CTR_SEATS_Backrest_67_Cushion_100_1 (3) +#endif + +#ifndef FIU_SMRR_SeatHeatBalance_Req_FIU_SMRR_REQ_CTR_SEATS_Backrest_33_Cushion_100_2 +#define FIU_SMRR_SeatHeatBalance_Req_FIU_SMRR_REQ_CTR_SEATS_Backrest_33_Cushion_100_2 (2) +#endif + +#ifndef FIU_SMRR_SeatHeatBalance_Req_FIU_SMRR_REQ_CTR_SEATS_Backrest_00_Cushion_100_3 +#define FIU_SMRR_SeatHeatBalance_Req_FIU_SMRR_REQ_CTR_SEATS_Backrest_00_Cushion_100_3 (1) +#endif + +#ifndef FIU_SMRR_SeatHeatBalance_Req_FIU_SMRR_REQ_CTR_SEATS_No_action +#define FIU_SMRR_SeatHeatBalance_Req_FIU_SMRR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRR_SeatMassageType_Req signal + +#ifndef FIU_SMRR_SeatMassageType_Req_FIU_SMRR_REQ_CTR_SEATS_Type_7_Velvet +#define FIU_SMRR_SeatMassageType_Req_FIU_SMRR_REQ_CTR_SEATS_Type_7_Velvet (7) +#endif + +#ifndef FIU_SMRR_SeatMassageType_Req_FIU_SMRR_REQ_CTR_SEATS_Type_6_Sonnet +#define FIU_SMRR_SeatMassageType_Req_FIU_SMRR_REQ_CTR_SEATS_Type_6_Sonnet (6) +#endif + +#ifndef FIU_SMRR_SeatMassageType_Req_FIU_SMRR_REQ_CTR_SEATS_Type_5_Quantum +#define FIU_SMRR_SeatMassageType_Req_FIU_SMRR_REQ_CTR_SEATS_Type_5_Quantum (5) +#endif + +#ifndef FIU_SMRR_SeatMassageType_Req_FIU_SMRR_REQ_CTR_SEATS_Type_4_Cashmere +#define FIU_SMRR_SeatMassageType_Req_FIU_SMRR_REQ_CTR_SEATS_Type_4_Cashmere (4) +#endif + +#ifndef FIU_SMRR_SeatMassageType_Req_FIU_SMRR_REQ_CTR_SEATS_Type_3_Harmony +#define FIU_SMRR_SeatMassageType_Req_FIU_SMRR_REQ_CTR_SEATS_Type_3_Harmony (3) +#endif + +#ifndef FIU_SMRR_SeatMassageType_Req_FIU_SMRR_REQ_CTR_SEATS_Type_2_Orbital +#define FIU_SMRR_SeatMassageType_Req_FIU_SMRR_REQ_CTR_SEATS_Type_2_Orbital (2) +#endif + +#ifndef FIU_SMRR_SeatMassageType_Req_FIU_SMRR_REQ_CTR_SEATS_Type_1_Insight +#define FIU_SMRR_SeatMassageType_Req_FIU_SMRR_REQ_CTR_SEATS_Type_1_Insight (1) +#endif + +#ifndef FIU_SMRR_SeatMassageType_Req_FIU_SMRR_REQ_CTR_SEATS_No_action +#define FIU_SMRR_SeatMassageType_Req_FIU_SMRR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRR_BackrestMassageType_Req signal + +#ifndef FIU_SMRR_BackrestMassageType_Req_FIU_SMRR_REQ_CTR_SEATS_Reserved +#define FIU_SMRR_BackrestMassageType_Req_FIU_SMRR_REQ_CTR_SEATS_Reserved (7) +#endif + +#ifndef FIU_SMRR_BackrestMassageType_Req_FIU_SMRR_REQ_CTR_SEATS_Reserved +#define FIU_SMRR_BackrestMassageType_Req_FIU_SMRR_REQ_CTR_SEATS_Reserved (6) +#endif + +#ifndef FIU_SMRR_BackrestMassageType_Req_FIU_SMRR_REQ_CTR_SEATS_Type_5_Elegy +#define FIU_SMRR_BackrestMassageType_Req_FIU_SMRR_REQ_CTR_SEATS_Type_5_Elegy (5) +#endif + +#ifndef FIU_SMRR_BackrestMassageType_Req_FIU_SMRR_REQ_CTR_SEATS_Type_4_Caprice +#define FIU_SMRR_BackrestMassageType_Req_FIU_SMRR_REQ_CTR_SEATS_Type_4_Caprice (4) +#endif + +#ifndef FIU_SMRR_BackrestMassageType_Req_FIU_SMRR_REQ_CTR_SEATS_Type_3_Pulse +#define FIU_SMRR_BackrestMassageType_Req_FIU_SMRR_REQ_CTR_SEATS_Type_3_Pulse (3) +#endif + +#ifndef FIU_SMRR_BackrestMassageType_Req_FIU_SMRR_REQ_CTR_SEATS_Type_2_Energy +#define FIU_SMRR_BackrestMassageType_Req_FIU_SMRR_REQ_CTR_SEATS_Type_2_Energy (2) +#endif + +#ifndef FIU_SMRR_BackrestMassageType_Req_FIU_SMRR_REQ_CTR_SEATS_Type_1_Synchrony +#define FIU_SMRR_BackrestMassageType_Req_FIU_SMRR_REQ_CTR_SEATS_Type_1_Synchrony (1) +#endif + +#ifndef FIU_SMRR_BackrestMassageType_Req_FIU_SMRR_REQ_CTR_SEATS_No_action +#define FIU_SMRR_BackrestMassageType_Req_FIU_SMRR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRR_ComfortMode_Req signal + +#ifndef FIU_SMRR_ComfortMode_Req_FIU_SMRR_REQ_CTR_SEATS_Active +#define FIU_SMRR_ComfortMode_Req_FIU_SMRR_REQ_CTR_SEATS_Active (1) +#endif + +#ifndef FIU_SMRR_ComfortMode_Req_FIU_SMRR_REQ_CTR_SEATS_Inactive +#define FIU_SMRR_ComfortMode_Req_FIU_SMRR_REQ_CTR_SEATS_Inactive (0) +#endif + + +// Value tables for @FIU_SMRR_ComfortScenario_Req signal + +#ifndef FIU_SMRR_ComfortScenario_Req_FIU_SMRR_REQ_CTR_SEATS_Type_3 +#define FIU_SMRR_ComfortScenario_Req_FIU_SMRR_REQ_CTR_SEATS_Type_3 (3) +#endif + +#ifndef FIU_SMRR_ComfortScenario_Req_FIU_SMRR_REQ_CTR_SEATS_Type_2 +#define FIU_SMRR_ComfortScenario_Req_FIU_SMRR_REQ_CTR_SEATS_Type_2 (2) +#endif + +#ifndef FIU_SMRR_ComfortScenario_Req_FIU_SMRR_REQ_CTR_SEATS_Type_1 +#define FIU_SMRR_ComfortScenario_Req_FIU_SMRR_REQ_CTR_SEATS_Type_1 (1) +#endif + +#ifndef FIU_SMRR_ComfortScenario_Req_FIU_SMRR_REQ_CTR_SEATS_No_action +#define FIU_SMRR_ComfortScenario_Req_FIU_SMRR_REQ_CTR_SEATS_No_action (0) +#endif + + +// Value tables for @FIU_SMRR_CarpetHeat_Req signal + +#ifndef FIU_SMRR_CarpetHeat_Req_FIU_SMRR_REQ_CTR_SEATS_Active +#define FIU_SMRR_CarpetHeat_Req_FIU_SMRR_REQ_CTR_SEATS_Active (1) +#endif + +#ifndef FIU_SMRR_CarpetHeat_Req_FIU_SMRR_REQ_CTR_SEATS_Inactive +#define FIU_SMRR_CarpetHeat_Req_FIU_SMRR_REQ_CTR_SEATS_Inactive (0) +#endif + + +// Value tables for @FIU_SMRR_TimerMassage_Req signal + +#ifndef FIU_SMRR_TimerMassage_Req_FIU_SMRR_REQ_CTR_SEATS_Reserved +#define FIU_SMRR_TimerMassage_Req_FIU_SMRR_REQ_CTR_SEATS_Reserved (7) +#endif + +#ifndef FIU_SMRR_TimerMassage_Req_FIU_SMRR_REQ_CTR_SEATS__min +#define FIU_SMRR_TimerMassage_Req_FIU_SMRR_REQ_CTR_SEATS__min (6) +#endif + +#ifndef FIU_SMRR_TimerMassage_Req_FIU_SMRR_REQ_CTR_SEATS__min +#define FIU_SMRR_TimerMassage_Req_FIU_SMRR_REQ_CTR_SEATS__min (5) +#endif + +#ifndef FIU_SMRR_TimerMassage_Req_FIU_SMRR_REQ_CTR_SEATS__min +#define FIU_SMRR_TimerMassage_Req_FIU_SMRR_REQ_CTR_SEATS__min (4) +#endif + +#ifndef FIU_SMRR_TimerMassage_Req_FIU_SMRR_REQ_CTR_SEATS__min +#define FIU_SMRR_TimerMassage_Req_FIU_SMRR_REQ_CTR_SEATS__min (3) +#endif + +#ifndef FIU_SMRR_TimerMassage_Req_FIU_SMRR_REQ_CTR_SEATS__min +#define FIU_SMRR_TimerMassage_Req_FIU_SMRR_REQ_CTR_SEATS__min (2) +#endif + +#ifndef FIU_SMRR_TimerMassage_Req_FIU_SMRR_REQ_CTR_SEATS__min +#define FIU_SMRR_TimerMassage_Req_FIU_SMRR_REQ_CTR_SEATS__min (1) +#endif + +#ifndef FIU_SMRR_TimerMassage_Req_FIU_SMRR_REQ_CTR_SEATS_No_action +#define FIU_SMRR_TimerMassage_Req_FIU_SMRR_REQ_CTR_SEATS_No_action (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Signal for regulation Seat Height RR + // (RR seat base height regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRR_SeatHeight_Req : 2; // Bits= 2 + + // Signal for regulation RR head rest height + // (RR headrest height regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRR_HeadRest_Height_Req : 2; // Bits= 2 + + // Signal for regulation RR seat longitudinal + // (RR seat base longitudinal regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRR_SeatLongitunalReq : 2; // Bits= 2 + + // Signal for regulation RR seat inclination + // (RR headrest depth regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRR_SeatHeadRestInclin_Req : 2; // Bits= 2 + + // Signal for regulation RR seat surface longitudinal + // (RR seat pillow longitudinal regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRR_SeatSurfaceLong_Req : 2; // Bits= 2 + + // Signal for regulation RR seat leg support height + // (RR seat leg support height regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRR_SeatLegSupportH_Req : 2; // Bits= 2 + + // Signal for regulation RR seat leg support longitudinal + // (RR seat leg support longitudinal regulation request, RESERVE) + // 3 : "Resertved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRR_SeatLegSupportLong_Req : 2; // Bits= 2 + + // Signal for regulation RR seat inclination + // (RR seat pillow inclination regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRR_SeatInclination_Req : 2; // Bits= 2 + + // Signal for regulation RR seat backrest lnclination + // (RR backrest angle regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRR_SeatBackRestInc_Req : 2; // Bits= 2 + + // Signal for regulation RR seat lumbar support height + // (RR backrest lumbar support height regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRR_SeatLumbarSupportH_Req : 2; // Bits= 2 + + // Signal for regulation RR seat backrest head inclination + // (RR backrest should support regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRR_SeatBackRestHeadInc_Req : 2; // Bits= 2 + + // Signal for regulation RR seat lumbar support depth + // (RR backrest lumbar support depth regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRR_SeatLumbarSupDepth_Req : 2; // Bits= 2 + + // Signal for regulation RR seat backrest width + // (RR backrest lateral support regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRR_BackRestWidth_Req : 2; // Bits= 2 + + // Signal for regulation RR seat cushion support + // (RR seat cushion side lateral support regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRR_SeatCushionSupport_Req : 2; // Bits= 2 + + // Signal for seat massage activation + // (RR seat massage request) + // 3 : "Reserved" + // 2 : "Massage ON" + // 1 : "Massage OFF" + // 0 : "No action" + uint8_t FIU_SMRR_SeatMassage_Req : 2; // Bits= 2 + + // Signal for ventilation activation mode + // (RR seat ventilation request) + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "Off" + uint8_t FIU_SMRR_SeatVentilation_Req : 2; // Bits= 2 + + // Signal for ventilation balance mode + // (RR seat ventilation balance request) + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 00%, Cushion 100%: -3" + // 0 : "No action" + uint8_t FIU_SMRR_SeatVentBalance_Req : 3; // Bits= 3 + + // Signal for seat massage intencity regulation + // (RR seat massage intencity request) + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "No action" + uint8_t FIU_SMRR_SeatMassageIntence_Req : 2; // Bits= 2 + + // Signal for seat heating activation mode + // (RR seat heating request) + // 3 : "High power" + // 2 : "Normal power" + // 1 : "Low power" + // 0 : "Off" + uint8_t FIU_SMRR_SeatHeating_Req : 2; // Bits= 2 + + // Active lateral support request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_SMRR_ActiveSupport_Req : 1; // Bits= 1 + + // Signal for seat heating balance + // (RR seat heating balance request) + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 00%, Cushion 100%: -3" + // 0 : "No action" + uint8_t FIU_SMRR_SeatHeatBalance_Req : 3; // Bits= 3 + + // Signal for seat massage type (mode) + // (RR seat massage type request) + // 7 : "Type 7 (Velvet)" + // 6 : "Type 6 (Sonnet)" + // 5 : "Type 5 (Quantum)" + // 4 : "Type 4 (Cashmere)" + // 3 : "Type 3 (Harmony)" + // 2 : "Type 2 (Orbital)" + // 1 : "Type 1 (Insight)" + // 0 : "No action" + uint8_t FIU_SMRR_SeatMassageType_Req : 3; // Bits= 3 + + // Signal for backrest massage type (mode) + // (RR backrest massage type request) + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Type 5 (Elegy)" + // 4 : "Type 4 (Caprice)" + // 3 : "Type 3 (Pulse)" + // 2 : "Type 2 (Energy)" + // 1 : "Type 1 (Synchrony)" + // 0 : "No action" + uint8_t FIU_SMRR_BackrestMassageType_Req : 3; // Bits= 3 + + // RR comfort mode request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_SMRR_ComfortMode_Req : 1; // Bits= 1 + + // RR comfort mode scenario request + // 3 : "Type 3" + // 2 : "Type 2" + // 1 : "Type 1" + // 0 : "No action" + uint8_t FIU_SMRR_ComfortScenario_Req : 2; // Bits= 2 + + // RR carpet heating request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_SMRR_CarpetHeat_Req : 1; // Bits= 1 + + // 7 : "Reserved" + // 6 : "30 min" + // 5 : "25 min" + // 4 : "20 min" + // 3 : "15 min" + // 2 : "10 min" + // 1 : "5 min" + // 0 : "No action" + uint8_t FIU_SMRR_TimerMassage_Req : 3; // Bits= 3 + +#else + + // Signal for regulation Seat Height RR + // (RR seat base height regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRR_SeatHeight_Req; // Bits= 2 + + // Signal for regulation RR head rest height + // (RR headrest height regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRR_HeadRest_Height_Req; // Bits= 2 + + // Signal for regulation RR seat longitudinal + // (RR seat base longitudinal regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRR_SeatLongitunalReq; // Bits= 2 + + // Signal for regulation RR seat inclination + // (RR headrest depth regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRR_SeatHeadRestInclin_Req; // Bits= 2 + + // Signal for regulation RR seat surface longitudinal + // (RR seat pillow longitudinal regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRR_SeatSurfaceLong_Req; // Bits= 2 + + // Signal for regulation RR seat leg support height + // (RR seat leg support height regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRR_SeatLegSupportH_Req; // Bits= 2 + + // Signal for regulation RR seat leg support longitudinal + // (RR seat leg support longitudinal regulation request, RESERVE) + // 3 : "Resertved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRR_SeatLegSupportLong_Req; // Bits= 2 + + // Signal for regulation RR seat inclination + // (RR seat pillow inclination regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRR_SeatInclination_Req; // Bits= 2 + + // Signal for regulation RR seat backrest lnclination + // (RR backrest angle regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRR_SeatBackRestInc_Req; // Bits= 2 + + // Signal for regulation RR seat lumbar support height + // (RR backrest lumbar support height regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRR_SeatLumbarSupportH_Req; // Bits= 2 + + // Signal for regulation RR seat backrest head inclination + // (RR backrest should support regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRR_SeatBackRestHeadInc_Req; // Bits= 2 + + // Signal for regulation RR seat lumbar support depth + // (RR backrest lumbar support depth regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRR_SeatLumbarSupDepth_Req; // Bits= 2 + + // Signal for regulation RR seat backrest width + // (RR backrest lateral support regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRR_BackRestWidth_Req; // Bits= 2 + + // Signal for regulation RR seat cushion support + // (RR seat cushion side lateral support regulation request) + // 3 : "Reserved" + // 2 : "Decrease" + // 1 : "Increase" + // 0 : "No action" + uint8_t FIU_SMRR_SeatCushionSupport_Req; // Bits= 2 + + // Signal for seat massage activation + // (RR seat massage request) + // 3 : "Reserved" + // 2 : "Massage ON" + // 1 : "Massage OFF" + // 0 : "No action" + uint8_t FIU_SMRR_SeatMassage_Req; // Bits= 2 + + // Signal for ventilation activation mode + // (RR seat ventilation request) + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "Off" + uint8_t FIU_SMRR_SeatVentilation_Req; // Bits= 2 + + // Signal for ventilation balance mode + // (RR seat ventilation balance request) + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 00%, Cushion 100%: -3" + // 0 : "No action" + uint8_t FIU_SMRR_SeatVentBalance_Req; // Bits= 3 + + // Signal for seat massage intencity regulation + // (RR seat massage intencity request) + // 3 : "High power" + // 2 : "Middle power" + // 1 : "Low power" + // 0 : "No action" + uint8_t FIU_SMRR_SeatMassageIntence_Req; // Bits= 2 + + // Signal for seat heating activation mode + // (RR seat heating request) + // 3 : "High power" + // 2 : "Normal power" + // 1 : "Low power" + // 0 : "Off" + uint8_t FIU_SMRR_SeatHeating_Req; // Bits= 2 + + // Active lateral support request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_SMRR_ActiveSupport_Req; // Bits= 1 + + // Signal for seat heating balance + // (RR seat heating balance request) + // 7 : "Backrest 100%, Cushion 00%: 3" + // 6 : "Backrest 100%, Cushion 33%: 2" + // 5 : "Backrest 100%, Cushion 67%: 1" + // 4 : "Backrest 100%, Cushion 100%: 0" + // 3 : "Backrest 67%, Cushion 100%: -1" + // 2 : "Backrest 33%, Cushion 100%: -2" + // 1 : "Backrest 00%, Cushion 100%: -3" + // 0 : "No action" + uint8_t FIU_SMRR_SeatHeatBalance_Req; // Bits= 3 + + // Signal for seat massage type (mode) + // (RR seat massage type request) + // 7 : "Type 7 (Velvet)" + // 6 : "Type 6 (Sonnet)" + // 5 : "Type 5 (Quantum)" + // 4 : "Type 4 (Cashmere)" + // 3 : "Type 3 (Harmony)" + // 2 : "Type 2 (Orbital)" + // 1 : "Type 1 (Insight)" + // 0 : "No action" + uint8_t FIU_SMRR_SeatMassageType_Req; // Bits= 3 + + // Signal for backrest massage type (mode) + // (RR backrest massage type request) + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Type 5 (Elegy)" + // 4 : "Type 4 (Caprice)" + // 3 : "Type 3 (Pulse)" + // 2 : "Type 2 (Energy)" + // 1 : "Type 1 (Synchrony)" + // 0 : "No action" + uint8_t FIU_SMRR_BackrestMassageType_Req; // Bits= 3 + + // RR comfort mode request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_SMRR_ComfortMode_Req; // Bits= 1 + + // RR comfort mode scenario request + // 3 : "Type 3" + // 2 : "Type 2" + // 1 : "Type 1" + // 0 : "No action" + uint8_t FIU_SMRR_ComfortScenario_Req; // Bits= 2 + + // RR carpet heating request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_SMRR_CarpetHeat_Req; // Bits= 1 + + // 7 : "Reserved" + // 6 : "30 min" + // 5 : "25 min" + // 4 : "20 min" + // 3 : "15 min" + // 2 : "10 min" + // 1 : "5 min" + // 0 : "No action" + uint8_t FIU_SMRR_TimerMassage_Req; // Bits= 3 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} FIU_SMRR_REQ_CTR_SEATS_t; + +// def @FIU_CTRL_DW CAN Message (1415 0x587) +#define FIU_CTRL_DW_IDE (0U) +#define FIU_CTRL_DW_DLC (5U) +#define FIU_CTRL_DW_CANID (0x587U) + +// Value tables for @FIU_DWDisplayCntrl_Req signal + +#ifndef FIU_DWDisplayCntrl_Req_FIU_CTRL_DW_Reserved_ +#define FIU_DWDisplayCntrl_Req_FIU_CTRL_DW_Reserved_ (3) +#endif + +#ifndef FIU_DWDisplayCntrl_Req_FIU_CTRL_DW_Turn_off_display +#define FIU_DWDisplayCntrl_Req_FIU_CTRL_DW_Turn_off_display (2) +#endif + +#ifndef FIU_DWDisplayCntrl_Req_FIU_CTRL_DW_Turn_on_display +#define FIU_DWDisplayCntrl_Req_FIU_CTRL_DW_Turn_on_display (1) +#endif + +#ifndef FIU_DWDisplayCntrl_Req_FIU_CTRL_DW_No_operation +#define FIU_DWDisplayCntrl_Req_FIU_CTRL_DW_No_operation (0) +#endif + + +// Value tables for @FIU_DWGlassCntrl_Req signal + +#ifndef FIU_DWGlassCntrl_Req_FIU_CTRL_DW_Reserved +#define FIU_DWGlassCntrl_Req_FIU_CTRL_DW_Reserved (3) +#endif + +#ifndef FIU_DWGlassCntrl_Req_FIU_CTRL_DW_Glass_transparency_request +#define FIU_DWGlassCntrl_Req_FIU_CTRL_DW_Glass_transparency_request (2) +#endif + +#ifndef FIU_DWGlassCntrl_Req_FIU_CTRL_DW_Glass_nontransparency_request +#define FIU_DWGlassCntrl_Req_FIU_CTRL_DW_Glass_nontransparency_request (1) +#endif + +#ifndef FIU_DWGlassCntrl_Req_FIU_CTRL_DW_No_operation +#define FIU_DWGlassCntrl_Req_FIU_CTRL_DW_No_operation (0) +#endif + + +// Value tables for @FIU_DWDisplayMovCntrl_Req signal + +#ifndef FIU_DWDisplayMovCntrl_Req_FIU_CTRL_DW_Reserved_ +#define FIU_DWDisplayMovCntrl_Req_FIU_CTRL_DW_Reserved_ (3) +#endif + +#ifndef FIU_DWDisplayMovCntrl_Req_FIU_CTRL_DW_Display_down_reguest +#define FIU_DWDisplayMovCntrl_Req_FIU_CTRL_DW_Display_down_reguest (2) +#endif + +#ifndef FIU_DWDisplayMovCntrl_Req_FIU_CTRL_DW_Display_up_request +#define FIU_DWDisplayMovCntrl_Req_FIU_CTRL_DW_Display_up_request (1) +#endif + +#ifndef FIU_DWDisplayMovCntrl_Req_FIU_CTRL_DW_No_operation_ +#define FIU_DWDisplayMovCntrl_Req_FIU_CTRL_DW_No_operation_ (0) +#endif + + +// Value tables for @FIU_DWGlassMovCntrl_Req signal + +#ifndef FIU_DWGlassMovCntrl_Req_FIU_CTRL_DW_Reserved +#define FIU_DWGlassMovCntrl_Req_FIU_CTRL_DW_Reserved (3) +#endif + +#ifndef FIU_DWGlassMovCntrl_Req_FIU_CTRL_DW_Partition_down_reguest +#define FIU_DWGlassMovCntrl_Req_FIU_CTRL_DW_Partition_down_reguest (2) +#endif + +#ifndef FIU_DWGlassMovCntrl_Req_FIU_CTRL_DW_Partition_up_request +#define FIU_DWGlassMovCntrl_Req_FIU_CTRL_DW_Partition_up_request (1) +#endif + +#ifndef FIU_DWGlassMovCntrl_Req_FIU_CTRL_DW_No_operation +#define FIU_DWGlassMovCntrl_Req_FIU_CTRL_DW_No_operation (0) +#endif + + +// Value tables for @FIU_DWDisplDimmingMode_Req signal + +#ifndef FIU_DWDisplDimmingMode_Req_FIU_CTRL_DW_Reserved +#define FIU_DWDisplDimmingMode_Req_FIU_CTRL_DW_Reserved (3) +#endif + +#ifndef FIU_DWDisplDimmingMode_Req_FIU_CTRL_DW_Manual_dimming +#define FIU_DWDisplDimmingMode_Req_FIU_CTRL_DW_Manual_dimming (2) +#endif + +#ifndef FIU_DWDisplDimmingMode_Req_FIU_CTRL_DW_Auto_dimming_ +#define FIU_DWDisplDimmingMode_Req_FIU_CTRL_DW_Auto_dimming_ (1) +#endif + +#ifndef FIU_DWDisplDimmingMode_Req_FIU_CTRL_DW_No_operation +#define FIU_DWDisplDimmingMode_Req_FIU_CTRL_DW_No_operation (0) +#endif + + +// Value tables for @FIU_DWVideoSignalSrc_Req signal + +#ifndef FIU_DWVideoSignalSrc_Req_FIU_CTRL_DW_Reserved +#define FIU_DWVideoSignalSrc_Req_FIU_CTRL_DW_Reserved (7) +#endif + +#ifndef FIU_DWVideoSignalSrc_Req_FIU_CTRL_DW_Reserved +#define FIU_DWVideoSignalSrc_Req_FIU_CTRL_DW_Reserved (6) +#endif + +#ifndef FIU_DWVideoSignalSrc_Req_FIU_CTRL_DW_HDMI_2_input +#define FIU_DWVideoSignalSrc_Req_FIU_CTRL_DW_HDMI_2_input (5) +#endif + +#ifndef FIU_DWVideoSignalSrc_Req_FIU_CTRL_DW_Video_signal_source_undefined +#define FIU_DWVideoSignalSrc_Req_FIU_CTRL_DW_Video_signal_source_undefined (0) +#endif + +#ifndef FIU_DWVideoSignalSrc_Req_FIU_CTRL_DW_HDMI_1_input +#define FIU_DWVideoSignalSrc_Req_FIU_CTRL_DW_HDMI_1_input (4) +#endif + +#ifndef FIU_DWVideoSignalSrc_Req_FIU_CTRL_DW_HDMI_socket_input +#define FIU_DWVideoSignalSrc_Req_FIU_CTRL_DW_HDMI_socket_input (3) +#endif + +#ifndef FIU_DWVideoSignalSrc_Req_FIU_CTRL_DW_Front_cam_input +#define FIU_DWVideoSignalSrc_Req_FIU_CTRL_DW_Front_cam_input (2) +#endif + +#ifndef FIU_DWVideoSignalSrc_Req_FIU_CTRL_DW_MMS_input +#define FIU_DWVideoSignalSrc_Req_FIU_CTRL_DW_MMS_input (1) +#endif + +// signal: @FIU_DWDispAutoDimmingVal_Req_ro +#define CANDB_FIU_DWDispAutoDimmingVal_Req_ro_CovFactor (0.394) +#define CANDB_FIU_DWDispAutoDimmingVal_Req_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.394)) ) +#define CANDB_FIU_DWDispAutoDimmingVal_Req_ro_fromS(x) ( (((x) * (0.394)) + (0.0)) ) +// signal: @FIU_DWDispManualDimming_Val_ro +#define CANDB_FIU_DWDispManualDimming_Val_ro_CovFactor (0.394) +#define CANDB_FIU_DWDispManualDimming_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.394)) ) +#define CANDB_FIU_DWDispManualDimming_Val_ro_fromS(x) ( (((x) * (0.394)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Request to turn on the DW display + // 3 : "Reserved " + // 2 : "Turn off display" + // 1 : "Turn on display" + // 0 : "No operation" + uint8_t FIU_DWDisplayCntrl_Req : 2; // Bits= 2 + + // Request to change the transparency of the partition + // 3 : "Reserved" + // 2 : "Glass transparency request" + // 1 : "Glass non-transparency request" + // 0 : "No operation" + uint8_t FIU_DWGlassCntrl_Req : 2; // Bits= 2 + + // Partition wall display moving request + // 3 : "Reserved " + // 2 : "Display down reguest" + // 1 : "Display up request" + // 0 : "No operation " + uint8_t FIU_DWDisplayMovCntrl_Req : 2; // Bits= 2 + + // Partition wall glass moving request + // 3 : "Reserved" + // 2 : "Partition down reguest" + // 1 : "Partition up request" + // 0 : "No operation" + uint8_t FIU_DWGlassMovCntrl_Req : 2; // Bits= 2 + + // DW Display auto dimming mode request + // 3 : "Reserved" + // 2 : "Manual dimming" + // 1 : "Auto dimming " + // 0 : "No operation" + uint8_t FIU_DWDisplDimmingMode_Req : 2; // Bits= 2 + + // Selection videosignal source + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "HDMI 2 input" + // 0 : "Video signal source undefined" + // 4 : "HDMI 1 input" + // 3 : "HDMI socket input" + // 2 : "Front cam input" + // 1 : "MMS input" + uint8_t FIU_DWVideoSignalSrc_Req : 3; // Bits= 3 + + // DW Display auto dimming value request + uint8_t FIU_DWDispAutoDimmingVal_Req_ro; // Bits= 8 Factor= 0.394 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t FIU_DWDispAutoDimmingVal_Req_phys; +#endif // CANDB_USE_SIGFLOAT + + // DW Display manual dimming value request + uint8_t FIU_DWDispManualDimming_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t FIU_DWDispManualDimming_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#else + + // Request to turn on the DW display + // 3 : "Reserved " + // 2 : "Turn off display" + // 1 : "Turn on display" + // 0 : "No operation" + uint8_t FIU_DWDisplayCntrl_Req; // Bits= 2 + + // Request to change the transparency of the partition + // 3 : "Reserved" + // 2 : "Glass transparency request" + // 1 : "Glass non-transparency request" + // 0 : "No operation" + uint8_t FIU_DWGlassCntrl_Req; // Bits= 2 + + // Partition wall display moving request + // 3 : "Reserved " + // 2 : "Display down reguest" + // 1 : "Display up request" + // 0 : "No operation " + uint8_t FIU_DWDisplayMovCntrl_Req; // Bits= 2 + + // Partition wall glass moving request + // 3 : "Reserved" + // 2 : "Partition down reguest" + // 1 : "Partition up request" + // 0 : "No operation" + uint8_t FIU_DWGlassMovCntrl_Req; // Bits= 2 + + // DW Display auto dimming mode request + // 3 : "Reserved" + // 2 : "Manual dimming" + // 1 : "Auto dimming " + // 0 : "No operation" + uint8_t FIU_DWDisplDimmingMode_Req; // Bits= 2 + + // Selection videosignal source + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "HDMI 2 input" + // 0 : "Video signal source undefined" + // 4 : "HDMI 1 input" + // 3 : "HDMI socket input" + // 2 : "Front cam input" + // 1 : "MMS input" + uint8_t FIU_DWVideoSignalSrc_Req; // Bits= 3 + + // DW Display auto dimming value request + uint8_t FIU_DWDispAutoDimmingVal_Req_ro; // Bits= 8 Factor= 0.394 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t FIU_DWDispAutoDimmingVal_Req_phys; +#endif // CANDB_USE_SIGFLOAT + + // DW Display manual dimming value request + uint8_t FIU_DWDispManualDimming_Val_ro; // Bits= 8 Factor= 0.394 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t FIU_DWDispManualDimming_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} FIU_CTRL_DW_t; + +// Dividing wall status +// def @DW_STATE CAN Message (1417 0x589) +#define DW_STATE_IDE (0U) +#define DW_STATE_DLC (4U) +#define DW_STATE_CANID (0x589U) +#define DW_STATE_CYC (100U) + +// Value tables for @DW_Display_Stat signal + +#ifndef DW_Display_Stat_DW_STATE_Display_on +#define DW_Display_Stat_DW_STATE_Display_on (1) +#endif + +#ifndef DW_Display_Stat_DW_STATE_Display_off +#define DW_Display_Stat_DW_STATE_Display_off (0) +#endif + + +// Value tables for @DW_MediaPower_Stat signal + +#ifndef DW_MediaPower_Stat_DW_STATE_Power_on +#define DW_MediaPower_Stat_DW_STATE_Power_on (1) +#endif + +#ifndef DW_MediaPower_Stat_DW_STATE_Power_off +#define DW_MediaPower_Stat_DW_STATE_Power_off (0) +#endif + + +// Value tables for @DW_Display_Req signal + +#ifndef DW_Display_Req_DW_STATE_Display_on +#define DW_Display_Req_DW_STATE_Display_on (1) +#endif + +#ifndef DW_Display_Req_DW_STATE_Display_off +#define DW_Display_Req_DW_STATE_Display_off (0) +#endif + + +// Value tables for @DW_Glass_Stat signal + +#ifndef DW_Glass_Stat_DW_STATE_Transparent_glass_state +#define DW_Glass_Stat_DW_STATE_Transparent_glass_state (1) +#endif + +#ifndef DW_Glass_Stat_DW_STATE_Nontransparent_glass_state +#define DW_Glass_Stat_DW_STATE_Nontransparent_glass_state (0) +#endif + + +// Value tables for @DW_AntiPinchFlag_Stat signal + +#ifndef DW_AntiPinchFlag_Stat_DW_STATE_Antipinch_expired_ +#define DW_AntiPinchFlag_Stat_DW_STATE_Antipinch_expired_ (1) +#endif + +#ifndef DW_AntiPinchFlag_Stat_DW_STATE_No_data +#define DW_AntiPinchFlag_Stat_DW_STATE_No_data (0) +#endif + + +// Value tables for @DW_CurrentVideoSigSrc_Stat signal + +#ifndef DW_CurrentVideoSigSrc_Stat_DW_STATE_Reserved_ +#define DW_CurrentVideoSigSrc_Stat_DW_STATE_Reserved_ (7) +#endif + +#ifndef DW_CurrentVideoSigSrc_Stat_DW_STATE_Reserved_ +#define DW_CurrentVideoSigSrc_Stat_DW_STATE_Reserved_ (6) +#endif + +#ifndef DW_CurrentVideoSigSrc_Stat_DW_STATE_HDMI_2_input +#define DW_CurrentVideoSigSrc_Stat_DW_STATE_HDMI_2_input (5) +#endif + +#ifndef DW_CurrentVideoSigSrc_Stat_DW_STATE_HDMI_1_input +#define DW_CurrentVideoSigSrc_Stat_DW_STATE_HDMI_1_input (4) +#endif + +#ifndef DW_CurrentVideoSigSrc_Stat_DW_STATE_HDMI_socket_input +#define DW_CurrentVideoSigSrc_Stat_DW_STATE_HDMI_socket_input (3) +#endif + +#ifndef DW_CurrentVideoSigSrc_Stat_DW_STATE_Front_cam_input +#define DW_CurrentVideoSigSrc_Stat_DW_STATE_Front_cam_input (2) +#endif + +#ifndef DW_CurrentVideoSigSrc_Stat_DW_STATE_MMS_input +#define DW_CurrentVideoSigSrc_Stat_DW_STATE_MMS_input (1) +#endif + +#ifndef DW_CurrentVideoSigSrc_Stat_DW_STATE_Video_signal_source_undefined +#define DW_CurrentVideoSigSrc_Stat_DW_STATE_Video_signal_source_undefined (0) +#endif + + +// Value tables for @DW_DisplayPosition_Stat signal + +#ifndef DW_DisplayPosition_Stat_DW_STATE_Reserved +#define DW_DisplayPosition_Stat_DW_STATE_Reserved (3) +#endif + +#ifndef DW_DisplayPosition_Stat_DW_STATE_Display_up_position +#define DW_DisplayPosition_Stat_DW_STATE_Display_up_position (2) +#endif + +#ifndef DW_DisplayPosition_Stat_DW_STATE_Display_down_position +#define DW_DisplayPosition_Stat_DW_STATE_Display_down_position (1) +#endif + +#ifndef DW_DisplayPosition_Stat_DW_STATE_Display_position_not_applicable +#define DW_DisplayPosition_Stat_DW_STATE_Display_position_not_applicable (0) +#endif + + +// Value tables for @DW_GlassPosition_Stat signal + +#ifndef DW_GlassPosition_Stat_DW_STATE_Reserved +#define DW_GlassPosition_Stat_DW_STATE_Reserved (3) +#endif + +#ifndef DW_GlassPosition_Stat_DW_STATE_Glass_down_position +#define DW_GlassPosition_Stat_DW_STATE_Glass_down_position (2) +#endif + +#ifndef DW_GlassPosition_Stat_DW_STATE_Glass_up_position +#define DW_GlassPosition_Stat_DW_STATE_Glass_up_position (1) +#endif + +#ifndef DW_GlassPosition_Stat_DW_STATE_Glass_position_not_applicable +#define DW_GlassPosition_Stat_DW_STATE_Glass_position_not_applicable (0) +#endif + + +// Value tables for @DW_MovingDisplay_Stat signal + +#ifndef DW_MovingDisplay_Stat_DW_STATE_Reserved +#define DW_MovingDisplay_Stat_DW_STATE_Reserved (3) +#endif + +#ifndef DW_MovingDisplay_Stat_DW_STATE_Display_moving_down +#define DW_MovingDisplay_Stat_DW_STATE_Display_moving_down (2) +#endif + +#ifndef DW_MovingDisplay_Stat_DW_STATE_Display_moving_up +#define DW_MovingDisplay_Stat_DW_STATE_Display_moving_up (1) +#endif + +#ifndef DW_MovingDisplay_Stat_DW_STATE_Display_not_moving +#define DW_MovingDisplay_Stat_DW_STATE_Display_not_moving (0) +#endif + + +// Value tables for @DW_MovingGlass_Stat signal + +#ifndef DW_MovingGlass_Stat_DW_STATE_Reserved +#define DW_MovingGlass_Stat_DW_STATE_Reserved (3) +#endif + +#ifndef DW_MovingGlass_Stat_DW_STATE_Glass_moving_down +#define DW_MovingGlass_Stat_DW_STATE_Glass_moving_down (2) +#endif + +#ifndef DW_MovingGlass_Stat_DW_STATE_Glass_moving_up +#define DW_MovingGlass_Stat_DW_STATE_Glass_moving_up (1) +#endif + +#ifndef DW_MovingGlass_Stat_DW_STATE_Glass_not_moving +#define DW_MovingGlass_Stat_DW_STATE_Glass_not_moving (0) +#endif + + +// Value tables for @DW_DisplayDimmingMode_Stat signal + +#ifndef DW_DisplayDimmingMode_Stat_DW_STATE_Error +#define DW_DisplayDimmingMode_Stat_DW_STATE_Error (3) +#endif + +#ifndef DW_DisplayDimmingMode_Stat_DW_STATE_Manual_dimming +#define DW_DisplayDimmingMode_Stat_DW_STATE_Manual_dimming (2) +#endif + +#ifndef DW_DisplayDimmingMode_Stat_DW_STATE_Auto_dimming +#define DW_DisplayDimmingMode_Stat_DW_STATE_Auto_dimming (1) +#endif + +#ifndef DW_DisplayDimmingMode_Stat_DW_STATE_Off +#define DW_DisplayDimmingMode_Stat_DW_STATE_Off (0) +#endif + + +// Value tables for @DW_DetectedMMSSrc_Stat signal + +#ifndef DW_DetectedMMSSrc_Stat_DW_STATE_Source_detected +#define DW_DetectedMMSSrc_Stat_DW_STATE_Source_detected (1) +#endif + +#ifndef DW_DetectedMMSSrc_Stat_DW_STATE_Source_off +#define DW_DetectedMMSSrc_Stat_DW_STATE_Source_off (0) +#endif + + +// Value tables for @DW_DetectedCAMSrc_Stat signal + +#ifndef DW_DetectedCAMSrc_Stat_DW_STATE_Source_detected +#define DW_DetectedCAMSrc_Stat_DW_STATE_Source_detected (1) +#endif + +#ifndef DW_DetectedCAMSrc_Stat_DW_STATE_Source_off +#define DW_DetectedCAMSrc_Stat_DW_STATE_Source_off (0) +#endif + + +// Value tables for @DW_DetectedHDMI1Src_Stat signal + +#ifndef DW_DetectedHDMI1Src_Stat_DW_STATE_Source_detected +#define DW_DetectedHDMI1Src_Stat_DW_STATE_Source_detected (1) +#endif + +#ifndef DW_DetectedHDMI1Src_Stat_DW_STATE_Source_off +#define DW_DetectedHDMI1Src_Stat_DW_STATE_Source_off (0) +#endif + + +// Value tables for @DW_DetectedHDMI2Src_Stat signal + +#ifndef DW_DetectedHDMI2Src_Stat_DW_STATE_Source_detected +#define DW_DetectedHDMI2Src_Stat_DW_STATE_Source_detected (1) +#endif + +#ifndef DW_DetectedHDMI2Src_Stat_DW_STATE_Source_off +#define DW_DetectedHDMI2Src_Stat_DW_STATE_Source_off (0) +#endif + + +// Value tables for @DW_DetectedHDMISockSrc_Stat signal + +#ifndef DW_DetectedHDMISockSrc_Stat_DW_STATE_Source_detected +#define DW_DetectedHDMISockSrc_Stat_DW_STATE_Source_detected (1) +#endif + +#ifndef DW_DetectedHDMISockSrc_Stat_DW_STATE_Source_off +#define DW_DetectedHDMISockSrc_Stat_DW_STATE_Source_off (0) +#endif + +// signal: @DW_DisplayBrightness_Stat_ro +#define CANDB_DW_DisplayBrightness_Stat_ro_CovFactor (0.394) +#define CANDB_DW_DisplayBrightness_Stat_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.394)) ) +#define CANDB_DW_DisplayBrightness_Stat_ro_fromS(x) ( (((x) * (0.394)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // DW Display state + // 1 : "Display on" + // 0 : "Display off" + uint8_t DW_Display_Stat : 1; // Bits= 1 + + // Multimedia devices power state + // 1 : "Power on" + // 0 : "Power off" + uint8_t DW_MediaPower_Stat : 1; // Bits= 1 + + // DW Display on/off request + // 1 : "Display on" + // 0 : "Display off" + uint8_t DW_Display_Req : 1; // Bits= 1 + + // DW partition transparency state + // 1 : "Transparent glass state" + // 0 : "Non-transparent glass state" + uint8_t DW_Glass_Stat : 1; // Bits= 1 + + // Anti-pinch flag + // 1 : "Anti-pinch expired " + // 0 : "No data" + uint8_t DW_AntiPinchFlag_Stat : 1; // Bits= 1 + + // Selection videosignal source + // 7 : "Reserved " + // 6 : "Reserved " + // 5 : "HDMI 2 input" + // 4 : "HDMI 1 input" + // 3 : "HDMI socket input" + // 2 : "Front cam input" + // 1 : "MMS input" + // 0 : "Video signal source undefined" + uint8_t DW_CurrentVideoSigSrc_Stat : 3; // Bits= 3 + + // Current display position + // 3 : "Reserved" + // 2 : "Display up position" + // 1 : "Display down position" + // 0 : "Display position not applicable" + uint8_t DW_DisplayPosition_Stat : 2; // Bits= 2 + + // Current partition state + // 3 : "Reserved" + // 2 : "Glass down position" + // 1 : "Glass up position" + // 0 : "Glass position not applicable" + uint8_t DW_GlassPosition_Stat : 2; // Bits= 2 + + // Partition wall display state + // 3 : "Reserved" + // 2 : "Display moving down" + // 1 : "Display moving up" + // 0 : "Display not moving" + uint8_t DW_MovingDisplay_Stat : 2; // Bits= 2 + + // Partition wall glass state + // 3 : "Reserved" + // 2 : "Glass moving down" + // 1 : "Glass moving up" + // 0 : "Glass not moving" + uint8_t DW_MovingGlass_Stat : 2; // Bits= 2 + + // DW Display dimming mode state + // 3 : "Error" + // 2 : "Manual dimming" + // 1 : "Auto dimming" + // 0 : "Off" + uint8_t DW_DisplayDimmingMode_Stat : 2; // Bits= 2 + + // Detecting a connected signal source + // 1 : "Source detected" + // 0 : "Source off" + uint8_t DW_DetectedMMSSrc_Stat : 1; // Bits= 1 + + // Detecting a connected signal source + // 1 : "Source detected" + // 0 : "Source off" + uint8_t DW_DetectedCAMSrc_Stat : 1; // Bits= 1 + + // Detecting a connected signal source + // 1 : "Source detected" + // 0 : "Source off" + uint8_t DW_DetectedHDMI1Src_Stat : 1; // Bits= 1 + + // Detecting a connected signal source + // 1 : "Source detected" + // 0 : "Source off" + uint8_t DW_DetectedHDMI2Src_Stat : 1; // Bits= 1 + + // Detecting a connected signal source + // 1 : "Source detected" + // 0 : "Source off" + uint8_t DW_DetectedHDMISockSrc_Stat : 1; // Bits= 1 + + // DW Display dimming value state, Percentage 0-100 + uint8_t DW_DisplayBrightness_Stat_ro; // Bits= 8 Factor= 0.394 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t DW_DisplayBrightness_Stat_phys; +#endif // CANDB_USE_SIGFLOAT + +#else + + // DW Display state + // 1 : "Display on" + // 0 : "Display off" + uint8_t DW_Display_Stat; // Bits= 1 + + // Multimedia devices power state + // 1 : "Power on" + // 0 : "Power off" + uint8_t DW_MediaPower_Stat; // Bits= 1 + + // DW Display on/off request + // 1 : "Display on" + // 0 : "Display off" + uint8_t DW_Display_Req; // Bits= 1 + + // DW partition transparency state + // 1 : "Transparent glass state" + // 0 : "Non-transparent glass state" + uint8_t DW_Glass_Stat; // Bits= 1 + + // Anti-pinch flag + // 1 : "Anti-pinch expired " + // 0 : "No data" + uint8_t DW_AntiPinchFlag_Stat; // Bits= 1 + + // Selection videosignal source + // 7 : "Reserved " + // 6 : "Reserved " + // 5 : "HDMI 2 input" + // 4 : "HDMI 1 input" + // 3 : "HDMI socket input" + // 2 : "Front cam input" + // 1 : "MMS input" + // 0 : "Video signal source undefined" + uint8_t DW_CurrentVideoSigSrc_Stat; // Bits= 3 + + // Current display position + // 3 : "Reserved" + // 2 : "Display up position" + // 1 : "Display down position" + // 0 : "Display position not applicable" + uint8_t DW_DisplayPosition_Stat; // Bits= 2 + + // Current partition state + // 3 : "Reserved" + // 2 : "Glass down position" + // 1 : "Glass up position" + // 0 : "Glass position not applicable" + uint8_t DW_GlassPosition_Stat; // Bits= 2 + + // Partition wall display state + // 3 : "Reserved" + // 2 : "Display moving down" + // 1 : "Display moving up" + // 0 : "Display not moving" + uint8_t DW_MovingDisplay_Stat; // Bits= 2 + + // Partition wall glass state + // 3 : "Reserved" + // 2 : "Glass moving down" + // 1 : "Glass moving up" + // 0 : "Glass not moving" + uint8_t DW_MovingGlass_Stat; // Bits= 2 + + // DW Display dimming mode state + // 3 : "Error" + // 2 : "Manual dimming" + // 1 : "Auto dimming" + // 0 : "Off" + uint8_t DW_DisplayDimmingMode_Stat; // Bits= 2 + + // Detecting a connected signal source + // 1 : "Source detected" + // 0 : "Source off" + uint8_t DW_DetectedMMSSrc_Stat; // Bits= 1 + + // Detecting a connected signal source + // 1 : "Source detected" + // 0 : "Source off" + uint8_t DW_DetectedCAMSrc_Stat; // Bits= 1 + + // Detecting a connected signal source + // 1 : "Source detected" + // 0 : "Source off" + uint8_t DW_DetectedHDMI1Src_Stat; // Bits= 1 + + // Detecting a connected signal source + // 1 : "Source detected" + // 0 : "Source off" + uint8_t DW_DetectedHDMI2Src_Stat; // Bits= 1 + + // Detecting a connected signal source + // 1 : "Source detected" + // 0 : "Source off" + uint8_t DW_DetectedHDMISockSrc_Stat; // Bits= 1 + + // DW Display dimming value state, Percentage 0-100 + uint8_t DW_DisplayBrightness_Stat_ro; // Bits= 8 Factor= 0.394 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t DW_DisplayBrightness_Stat_phys; +#endif // CANDB_USE_SIGFLOAT + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} DW_STATE_t; + +// def @FIU_Msg1 CAN Message (1422 0x58e) +#define FIU_Msg1_IDE (0U) +#define FIU_Msg1_DLC (8U) +#define FIU_Msg1_CANID (0x58eU) + +// Value tables for @FIU_HeadlightWashing_Req signal + +#ifndef FIU_HeadlightWashing_Req_FIU_Msg1_Active +#define FIU_HeadlightWashing_Req_FIU_Msg1_Active (1) +#endif + +#ifndef FIU_HeadlightWashing_Req_FIU_Msg1_Inactive +#define FIU_HeadlightWashing_Req_FIU_Msg1_Inactive (0) +#endif + + +// Value tables for @FIU_AutoWiper_Req signal + +#ifndef FIU_AutoWiper_Req_FIU_Msg1_Function_active +#define FIU_AutoWiper_Req_FIU_Msg1_Function_active (1) +#endif + +#ifndef FIU_AutoWiper_Req_FIU_Msg1_Function_inactive +#define FIU_AutoWiper_Req_FIU_Msg1_Function_inactive (0) +#endif + + +// Value tables for @FIU_WelcomeLeavingLight_Req signal + +#ifndef FIU_WelcomeLeavingLight_Req_FIU_Msg1_Active +#define FIU_WelcomeLeavingLight_Req_FIU_Msg1_Active (1) +#endif + +#ifndef FIU_WelcomeLeavingLight_Req_FIU_Msg1_Inactive +#define FIU_WelcomeLeavingLight_Req_FIU_Msg1_Inactive (0) +#endif + + +// Value tables for @FIU_WelcomeLeavingLightTime_Req signal + +#ifndef FIU_WelcomeLeavingLightTime_Req_FIU_Msg1_Function_active_for_time_60_sec +#define FIU_WelcomeLeavingLightTime_Req_FIU_Msg1_Function_active_for_time_60_sec (3) +#endif + +#ifndef FIU_WelcomeLeavingLightTime_Req_FIU_Msg1_Function_active_for_time_45_sec +#define FIU_WelcomeLeavingLightTime_Req_FIU_Msg1_Function_active_for_time_45_sec (2) +#endif + +#ifndef FIU_WelcomeLeavingLightTime_Req_FIU_Msg1_Function_active_for_time_30_sec +#define FIU_WelcomeLeavingLightTime_Req_FIU_Msg1_Function_active_for_time_30_sec (1) +#endif + +#ifndef FIU_WelcomeLeavingLightTime_Req_FIU_Msg1_Function_active_for_time_15_sec +#define FIU_WelcomeLeavingLightTime_Req_FIU_Msg1_Function_active_for_time_15_sec (0) +#endif + + +// Value tables for @FIU_WindowsRainClosing_Req signal + +#ifndef FIU_WindowsRainClosing_Req_FIU_Msg1_Active +#define FIU_WindowsRainClosing_Req_FIU_Msg1_Active (1) +#endif + +#ifndef FIU_WindowsRainClosing_Req_FIU_Msg1_Inactive +#define FIU_WindowsRainClosing_Req_FIU_Msg1_Inactive (0) +#endif + + +// Value tables for @FIU_MirrorsAutoFold_Req signal + +#ifndef FIU_MirrorsAutoFold_Req_FIU_Msg1_Active +#define FIU_MirrorsAutoFold_Req_FIU_Msg1_Active (1) +#endif + +#ifndef FIU_MirrorsAutoFold_Req_FIU_Msg1_Inactive +#define FIU_MirrorsAutoFold_Req_FIU_Msg1_Inactive (0) +#endif + + +// Value tables for @FIU_AutoTiltMirrors_Req signal + +#ifndef FIU_AutoTiltMirrors_Req_FIU_Msg1_Function_active +#define FIU_AutoTiltMirrors_Req_FIU_Msg1_Function_active (1) +#endif + +#ifndef FIU_AutoTiltMirrors_Req_FIU_Msg1_Function_inactive +#define FIU_AutoTiltMirrors_Req_FIU_Msg1_Function_inactive (0) +#endif + + +// Value tables for @FIU_SteeringWheelAutoHeat_Req signal + +#ifndef FIU_SteeringWheelAutoHeat_Req_FIU_Msg1_Active +#define FIU_SteeringWheelAutoHeat_Req_FIU_Msg1_Active (1) +#endif + +#ifndef FIU_SteeringWheelAutoHeat_Req_FIU_Msg1_Inactive +#define FIU_SteeringWheelAutoHeat_Req_FIU_Msg1_Inactive (0) +#endif + + +// Value tables for @FIU_DoorsLock_Req signal + +#ifndef FIU_DoorsLock_Req_FIU_Msg1_LockUnlock +#define FIU_DoorsLock_Req_FIU_Msg1_LockUnlock (1) +#endif + +#ifndef FIU_DoorsLock_Req_FIU_Msg1_No_action +#define FIU_DoorsLock_Req_FIU_Msg1_No_action (0) +#endif + + +// Value tables for @FIU_DoorsDriveLock_Req signal + +#ifndef FIU_DoorsDriveLock_Req_FIU_Msg1_Active +#define FIU_DoorsDriveLock_Req_FIU_Msg1_Active (1) +#endif + +#ifndef FIU_DoorsDriveLock_Req_FIU_Msg1_Inactive +#define FIU_DoorsDriveLock_Req_FIU_Msg1_Inactive (0) +#endif + + +// Value tables for @FIU_AudibleLockFdBack_Req signal + +#ifndef FIU_AudibleLockFdBack_Req_FIU_Msg1_Active +#define FIU_AudibleLockFdBack_Req_FIU_Msg1_Active (1) +#endif + +#ifndef FIU_AudibleLockFdBack_Req_FIU_Msg1_Inactive +#define FIU_AudibleLockFdBack_Req_FIU_Msg1_Inactive (0) +#endif + + +// Value tables for @FIU_ApproachAccess_Req signal + +#ifndef FIU_ApproachAccess_Req_FIU_Msg1_Active +#define FIU_ApproachAccess_Req_FIU_Msg1_Active (1) +#endif + +#ifndef FIU_ApproachAccess_Req_FIU_Msg1_Inactive +#define FIU_ApproachAccess_Req_FIU_Msg1_Inactive (0) +#endif + + +// Value tables for @FIU_TrnkDoorCloseBySpeed_Req signal + +#ifndef FIU_TrnkDoorCloseBySpeed_Req_FIU_Msg1_Active +#define FIU_TrnkDoorCloseBySpeed_Req_FIU_Msg1_Active (1) +#endif + +#ifndef FIU_TrnkDoorCloseBySpeed_Req_FIU_Msg1_Inactive +#define FIU_TrnkDoorCloseBySpeed_Req_FIU_Msg1_Inactive (0) +#endif + + +// Value tables for @FIU_WelcomeLightAnimation_Req signal + +#ifndef FIU_WelcomeLightAnimation_Req_FIU_Msg1_Active +#define FIU_WelcomeLightAnimation_Req_FIU_Msg1_Active (1) +#endif + +#ifndef FIU_WelcomeLightAnimation_Req_FIU_Msg1_Inactive +#define FIU_WelcomeLightAnimation_Req_FIU_Msg1_Inactive (0) +#endif + + +// Value tables for @FIU_MAS_CamerasWashing_Req signal + +#ifndef FIU_MAS_CamerasWashing_Req_FIU_Msg1_Front_And_Rear_cameras_washing_request +#define FIU_MAS_CamerasWashing_Req_FIU_Msg1_Front_And_Rear_cameras_washing_request (1) +#endif + +#ifndef FIU_MAS_CamerasWashing_Req_FIU_Msg1_No_request +#define FIU_MAS_CamerasWashing_Req_FIU_Msg1_No_request (0) +#endif + + +// Value tables for @FIU_DoorCntrlRR_Req signal + +#ifndef FIU_DoorCntrlRR_Req_FIU_Msg1_Close +#define FIU_DoorCntrlRR_Req_FIU_Msg1_Close (2) +#endif + +#ifndef FIU_DoorCntrlRR_Req_FIU_Msg1_Open +#define FIU_DoorCntrlRR_Req_FIU_Msg1_Open (1) +#endif + +#ifndef FIU_DoorCntrlRR_Req_FIU_Msg1_No_action +#define FIU_DoorCntrlRR_Req_FIU_Msg1_No_action (0) +#endif + + +// Value tables for @FIU_DoorCntrlFR_Req signal + +#ifndef FIU_DoorCntrlFR_Req_FIU_Msg1_Close +#define FIU_DoorCntrlFR_Req_FIU_Msg1_Close (2) +#endif + +#ifndef FIU_DoorCntrlFR_Req_FIU_Msg1_Open +#define FIU_DoorCntrlFR_Req_FIU_Msg1_Open (1) +#endif + +#ifndef FIU_DoorCntrlFR_Req_FIU_Msg1_No_action +#define FIU_DoorCntrlFR_Req_FIU_Msg1_No_action (0) +#endif + + +// Value tables for @FIU_DoorCntrlFL_Req signal + +#ifndef FIU_DoorCntrlFL_Req_FIU_Msg1_Close +#define FIU_DoorCntrlFL_Req_FIU_Msg1_Close (2) +#endif + +#ifndef FIU_DoorCntrlFL_Req_FIU_Msg1_Open +#define FIU_DoorCntrlFL_Req_FIU_Msg1_Open (1) +#endif + +#ifndef FIU_DoorCntrlFL_Req_FIU_Msg1_No_action +#define FIU_DoorCntrlFL_Req_FIU_Msg1_No_action (0) +#endif + + +// Value tables for @FIU_DoorCntrlRL_Req signal + +#ifndef FIU_DoorCntrlRL_Req_FIU_Msg1_Close +#define FIU_DoorCntrlRL_Req_FIU_Msg1_Close (2) +#endif + +#ifndef FIU_DoorCntrlRL_Req_FIU_Msg1_Open +#define FIU_DoorCntrlRL_Req_FIU_Msg1_Open (1) +#endif + +#ifndef FIU_DoorCntrlRL_Req_FIU_Msg1_No_action +#define FIU_DoorCntrlRL_Req_FIU_Msg1_No_action (0) +#endif + + +// Value tables for @FIU_DoorCntrlTrunk_Req signal + +#ifndef FIU_DoorCntrlTrunk_Req_FIU_Msg1_Close +#define FIU_DoorCntrlTrunk_Req_FIU_Msg1_Close (2) +#endif + +#ifndef FIU_DoorCntrlTrunk_Req_FIU_Msg1_Open +#define FIU_DoorCntrlTrunk_Req_FIU_Msg1_Open (1) +#endif + +#ifndef FIU_DoorCntrlTrunk_Req_FIU_Msg1_No_Actions +#define FIU_DoorCntrlTrunk_Req_FIU_Msg1_No_Actions (0) +#endif + + +// Value tables for @FIU_EasyExitEnableRR_Req signal + +#ifndef FIU_EasyExitEnableRR_Req_FIU_Msg1_Easy_exit_enable +#define FIU_EasyExitEnableRR_Req_FIU_Msg1_Easy_exit_enable (1) +#endif + +#ifndef FIU_EasyExitEnableRR_Req_FIU_Msg1_Easy_exit_disable +#define FIU_EasyExitEnableRR_Req_FIU_Msg1_Easy_exit_disable (0) +#endif + + +// Value tables for @FIU_EasyExitEnableRL_Req signal + +#ifndef FIU_EasyExitEnableRL_Req_FIU_Msg1_Easy_exit_enable +#define FIU_EasyExitEnableRL_Req_FIU_Msg1_Easy_exit_enable (1) +#endif + +#ifndef FIU_EasyExitEnableRL_Req_FIU_Msg1_Easy_exit_disable +#define FIU_EasyExitEnableRL_Req_FIU_Msg1_Easy_exit_disable (0) +#endif + + +// Value tables for @FIU_EasyExitEnableFR_Req signal + +#ifndef FIU_EasyExitEnableFR_Req_FIU_Msg1_Easy_exit_enable +#define FIU_EasyExitEnableFR_Req_FIU_Msg1_Easy_exit_enable (1) +#endif + +#ifndef FIU_EasyExitEnableFR_Req_FIU_Msg1_Easy_exit_disable +#define FIU_EasyExitEnableFR_Req_FIU_Msg1_Easy_exit_disable (0) +#endif + + +// Value tables for @FIU_EasyExitEnableFL_Req signal + +#ifndef FIU_EasyExitEnableFL_Req_FIU_Msg1_Easy_exit_enable +#define FIU_EasyExitEnableFL_Req_FIU_Msg1_Easy_exit_enable (1) +#endif + +#ifndef FIU_EasyExitEnableFL_Req_FIU_Msg1_Easy_exit_disable +#define FIU_EasyExitEnableFL_Req_FIU_Msg1_Easy_exit_disable (0) +#endif + +// signal: @FIU_FrontCeilingBright_Val_ro +#define CANDB_FIU_FrontCeilingBright_Val_ro_CovFactor (0.392) +#define CANDB_FIU_FrontCeilingBright_Val_ro_toS(x) ( (uint8_t) (((x) - (1.0)) / (0.392)) ) +#define CANDB_FIU_FrontCeilingBright_Val_ro_fromS(x) ( (((x) * (0.392)) + (1.0)) ) +// signal: @FIU_RearCeilingBright_Val_ro +#define CANDB_FIU_RearCeilingBright_Val_ro_CovFactor (0.392) +#define CANDB_FIU_RearCeilingBright_Val_ro_toS(x) ( (uint8_t) (((x) - (1.0)) / (0.392)) ) +#define CANDB_FIU_RearCeilingBright_Val_ro_fromS(x) ( (((x) * (0.392)) + (1.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // AUTO washing headlights together with windshield + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_HeadlightWashing_Req : 1; // Bits= 1 + + // Autowipering and autowashing windshield by Rain and Light sensor signals + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t FIU_AutoWiper_Req : 1; // Bits= 1 + + // Welcome and leaving light enable request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_WelcomeLeavingLight_Req : 1; // Bits= 1 + + // Welcome and leaving light working time request + // 3 : "Function active for time 60 sec" + // 2 : "Function active for time 45 sec" + // 1 : "Function active for time 30 sec" + // 0 : "Function active for time 15 sec" + uint8_t FIU_WelcomeLeavingLightTime_Req : 2; // Bits= 2 + + // Windows automatically closing when it rains + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_WindowsRainClosing_Req : 1; // Bits= 1 + + // Auto folding mirrors when secure lock action + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_MirrorsAutoFold_Req : 1; // Bits= 1 + + // When R gear is active mirrors are bend over + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t FIU_AutoTiltMirrors_Req : 1; // Bits= 1 + + // Automatically steering wheel heating request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_SteeringWheelAutoHeat_Req : 1; // Bits= 1 + + // Door Lock/Unlock + // 1 : "Lock/Unlock" + // 0 : "No action" + uint8_t FIU_DoorsLock_Req : 1; // Bits= 1 + + // Doors automatically locking when driving (speed above threshhold) + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_DoorsDriveLock_Req : 1; // Bits= 1 + + // Vehicle locking/unlocking sound enable function + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_AudibleLockFdBack_Req : 1; // Bits= 1 + + // Automatic doors lock, when user leaves vehicle + // Automatic doors unlock, when user approaches to vehicle + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_ApproachAccess_Req : 1; // Bits= 1 + + // Trunk automatically closing when driving (speed above threshhold) + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_TrnkDoorCloseBySpeed_Req : 1; // Bits= 1 + + // Welcome headlight animation enable request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_WelcomeLightAnimation_Req : 1; // Bits= 1 + + // The signal is used to activate the washer for the front and rear surround view cameras. + // 1 : "Front And Rear cameras washing request" + // 0 : "No request" + uint8_t FIU_MAS_CamerasWashing_Req : 1; // Bits= 1 + + // Request for opening or closing rear right door by electric motor + // 2 : "Close" + // 1 : "Open" + // 0 : "No action" + uint8_t FIU_DoorCntrlRR_Req : 2; // Bits= 2 + + // Request for opening or closing front right door by electric motor + // 2 : "Close" + // 1 : "Open" + // 0 : "No action" + uint8_t FIU_DoorCntrlFR_Req : 2; // Bits= 2 + + // Request for opening or closing front left door by electric motor + // 2 : "Close" + // 1 : "Open" + // 0 : "No action" + uint8_t FIU_DoorCntrlFL_Req : 2; // Bits= 2 + + // Request for opening or closing rear left door by electric motor + // 2 : "Close" + // 1 : "Open" + // 0 : "No action" + uint8_t FIU_DoorCntrlRL_Req : 2; // Bits= 2 + + // Request for opening or closing trunk lid by electric motor + // 2 : "Close" + // 1 : "Open" + // 0 : "No Actions" + uint8_t FIU_DoorCntrlTrunk_Req : 2; // Bits= 2 + + // Steering column, seat and so on stand in easy exit position + // 1 : "Easy exit enable" + // 0 : "Easy exit disable" + uint8_t FIU_EasyExitEnableRR_Req : 1; // Bits= 1 + + // Steering column, seat and so on stand in easy exit position + // 1 : "Easy exit enable" + // 0 : "Easy exit disable" + uint8_t FIU_EasyExitEnableRL_Req : 1; // Bits= 1 + + // Steering column, seat and so on stand in easy exit position + // 1 : "Easy exit enable" + // 0 : "Easy exit disable" + uint8_t FIU_EasyExitEnableFR_Req : 1; // Bits= 1 + + // Steering column, seat and so on stand in easy exit position + // 1 : "Easy exit enable" + // 0 : "Easy exit disable" + uint8_t FIU_EasyExitEnableFL_Req : 1; // Bits= 1 + + // Front ceiling light brightness value + uint8_t FIU_FrontCeilingBright_Val_ro; // Bits= 8 Offset= 1.0 Factor= 0.392 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t FIU_FrontCeilingBright_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Rear ceiling light brightness value + uint8_t FIU_RearCeilingBright_Val_ro; // Bits= 8 Offset= 1.0 Factor= 0.392 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t FIU_RearCeilingBright_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#else + + // AUTO washing headlights together with windshield + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_HeadlightWashing_Req; // Bits= 1 + + // Autowipering and autowashing windshield by Rain and Light sensor signals + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t FIU_AutoWiper_Req; // Bits= 1 + + // Welcome and leaving light enable request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_WelcomeLeavingLight_Req; // Bits= 1 + + // Welcome and leaving light working time request + // 3 : "Function active for time 60 sec" + // 2 : "Function active for time 45 sec" + // 1 : "Function active for time 30 sec" + // 0 : "Function active for time 15 sec" + uint8_t FIU_WelcomeLeavingLightTime_Req; // Bits= 2 + + // Windows automatically closing when it rains + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_WindowsRainClosing_Req; // Bits= 1 + + // Auto folding mirrors when secure lock action + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_MirrorsAutoFold_Req; // Bits= 1 + + // When R gear is active mirrors are bend over + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t FIU_AutoTiltMirrors_Req; // Bits= 1 + + // Automatically steering wheel heating request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_SteeringWheelAutoHeat_Req; // Bits= 1 + + // Door Lock/Unlock + // 1 : "Lock/Unlock" + // 0 : "No action" + uint8_t FIU_DoorsLock_Req; // Bits= 1 + + // Doors automatically locking when driving (speed above threshhold) + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_DoorsDriveLock_Req; // Bits= 1 + + // Vehicle locking/unlocking sound enable function + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_AudibleLockFdBack_Req; // Bits= 1 + + // Automatic doors lock, when user leaves vehicle + // Automatic doors unlock, when user approaches to vehicle + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_ApproachAccess_Req; // Bits= 1 + + // Trunk automatically closing when driving (speed above threshhold) + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_TrnkDoorCloseBySpeed_Req; // Bits= 1 + + // Welcome headlight animation enable request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_WelcomeLightAnimation_Req; // Bits= 1 + + // The signal is used to activate the washer for the front and rear surround view cameras. + // 1 : "Front And Rear cameras washing request" + // 0 : "No request" + uint8_t FIU_MAS_CamerasWashing_Req; // Bits= 1 + + // Request for opening or closing rear right door by electric motor + // 2 : "Close" + // 1 : "Open" + // 0 : "No action" + uint8_t FIU_DoorCntrlRR_Req; // Bits= 2 + + // Request for opening or closing front right door by electric motor + // 2 : "Close" + // 1 : "Open" + // 0 : "No action" + uint8_t FIU_DoorCntrlFR_Req; // Bits= 2 + + // Request for opening or closing front left door by electric motor + // 2 : "Close" + // 1 : "Open" + // 0 : "No action" + uint8_t FIU_DoorCntrlFL_Req; // Bits= 2 + + // Request for opening or closing rear left door by electric motor + // 2 : "Close" + // 1 : "Open" + // 0 : "No action" + uint8_t FIU_DoorCntrlRL_Req; // Bits= 2 + + // Request for opening or closing trunk lid by electric motor + // 2 : "Close" + // 1 : "Open" + // 0 : "No Actions" + uint8_t FIU_DoorCntrlTrunk_Req; // Bits= 2 + + // Steering column, seat and so on stand in easy exit position + // 1 : "Easy exit enable" + // 0 : "Easy exit disable" + uint8_t FIU_EasyExitEnableRR_Req; // Bits= 1 + + // Steering column, seat and so on stand in easy exit position + // 1 : "Easy exit enable" + // 0 : "Easy exit disable" + uint8_t FIU_EasyExitEnableRL_Req; // Bits= 1 + + // Steering column, seat and so on stand in easy exit position + // 1 : "Easy exit enable" + // 0 : "Easy exit disable" + uint8_t FIU_EasyExitEnableFR_Req; // Bits= 1 + + // Steering column, seat and so on stand in easy exit position + // 1 : "Easy exit enable" + // 0 : "Easy exit disable" + uint8_t FIU_EasyExitEnableFL_Req; // Bits= 1 + + // Front ceiling light brightness value + uint8_t FIU_FrontCeilingBright_Val_ro; // Bits= 8 Offset= 1.0 Factor= 0.392 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t FIU_FrontCeilingBright_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Rear ceiling light brightness value + uint8_t FIU_RearCeilingBright_Val_ro; // Bits= 8 Offset= 1.0 Factor= 0.392 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t FIU_RearCeilingBright_Val_phys; +#endif // CANDB_USE_SIGFLOAT + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} FIU_Msg1_t; + +// def @FIU_Msg2 CAN Message (1423 0x58f) +#define FIU_Msg2_IDE (0U) +#define FIU_Msg2_DLC (8U) +#define FIU_Msg2_CANID (0x58fU) + +// Value tables for @FIU_StyleIllGlobal_Req signal + +#ifndef FIU_StyleIllGlobal_Req_FIU_Msg2_Function_active +#define FIU_StyleIllGlobal_Req_FIU_Msg2_Function_active (1) +#endif + +#ifndef FIU_StyleIllGlobal_Req_FIU_Msg2_Function_inactive +#define FIU_StyleIllGlobal_Req_FIU_Msg2_Function_inactive (0) +#endif + + +// Value tables for @FIU_ChildLock_RLtablet_Req signal + +#ifndef FIU_ChildLock_RLtablet_Req_FIU_Msg2_Function_active +#define FIU_ChildLock_RLtablet_Req_FIU_Msg2_Function_active (1) +#endif + +#ifndef FIU_ChildLock_RLtablet_Req_FIU_Msg2_Function_inactive +#define FIU_ChildLock_RLtablet_Req_FIU_Msg2_Function_inactive (0) +#endif + + +// Value tables for @FIU_ConfCamera_Req signal + +#ifndef FIU_ConfCamera_Req_FIU_Msg2_Active +#define FIU_ConfCamera_Req_FIU_Msg2_Active (1) +#endif + +#ifndef FIU_ConfCamera_Req_FIU_Msg2_Inactive +#define FIU_ConfCamera_Req_FIU_Msg2_Inactive (0) +#endif + + +// Value tables for @FIU_StyleIllTheme_Req signal + +#ifndef FIU_StyleIllTheme_Req_FIU_Msg2_Color_theme_16 +#define FIU_StyleIllTheme_Req_FIU_Msg2_Color_theme_16 (15) +#endif + +#ifndef FIU_StyleIllTheme_Req_FIU_Msg2_Color_theme_15 +#define FIU_StyleIllTheme_Req_FIU_Msg2_Color_theme_15 (14) +#endif + +#ifndef FIU_StyleIllTheme_Req_FIU_Msg2_Color_theme_14 +#define FIU_StyleIllTheme_Req_FIU_Msg2_Color_theme_14 (13) +#endif + +#ifndef FIU_StyleIllTheme_Req_FIU_Msg2_Color_theme_13 +#define FIU_StyleIllTheme_Req_FIU_Msg2_Color_theme_13 (12) +#endif + +#ifndef FIU_StyleIllTheme_Req_FIU_Msg2_Color_theme_12 +#define FIU_StyleIllTheme_Req_FIU_Msg2_Color_theme_12 (11) +#endif + +#ifndef FIU_StyleIllTheme_Req_FIU_Msg2_Color_theme_11 +#define FIU_StyleIllTheme_Req_FIU_Msg2_Color_theme_11 (10) +#endif + +#ifndef FIU_StyleIllTheme_Req_FIU_Msg2_Color_theme_10 +#define FIU_StyleIllTheme_Req_FIU_Msg2_Color_theme_10 (9) +#endif + +#ifndef FIU_StyleIllTheme_Req_FIU_Msg2_Color_theme_9 +#define FIU_StyleIllTheme_Req_FIU_Msg2_Color_theme_9 (8) +#endif + +#ifndef FIU_StyleIllTheme_Req_FIU_Msg2_Reserved +#define FIU_StyleIllTheme_Req_FIU_Msg2_Reserved (7) +#endif + +#ifndef FIU_StyleIllTheme_Req_FIU_Msg2_Color_theme_7 +#define FIU_StyleIllTheme_Req_FIU_Msg2_Color_theme_7 (6) +#endif + +#ifndef FIU_StyleIllTheme_Req_FIU_Msg2_Color_theme_6 +#define FIU_StyleIllTheme_Req_FIU_Msg2_Color_theme_6 (5) +#endif + +#ifndef FIU_StyleIllTheme_Req_FIU_Msg2_Color_theme_5 +#define FIU_StyleIllTheme_Req_FIU_Msg2_Color_theme_5 (4) +#endif + +#ifndef FIU_StyleIllTheme_Req_FIU_Msg2_Color_theme_4 +#define FIU_StyleIllTheme_Req_FIU_Msg2_Color_theme_4 (3) +#endif + +#ifndef FIU_StyleIllTheme_Req_FIU_Msg2_Color_theme_3 +#define FIU_StyleIllTheme_Req_FIU_Msg2_Color_theme_3 (2) +#endif + +#ifndef FIU_StyleIllTheme_Req_FIU_Msg2_Color_theme_2 +#define FIU_StyleIllTheme_Req_FIU_Msg2_Color_theme_2 (1) +#endif + +#ifndef FIU_StyleIllTheme_Req_FIU_Msg2_Color_theme_1 +#define FIU_StyleIllTheme_Req_FIU_Msg2_Color_theme_1 (0) +#endif + + +// Value tables for @FIU_ChildLock_RRtablet_Req signal + +#ifndef FIU_ChildLock_RRtablet_Req_FIU_Msg2_Function_active +#define FIU_ChildLock_RRtablet_Req_FIU_Msg2_Function_active (1) +#endif + +#ifndef FIU_ChildLock_RRtablet_Req_FIU_Msg2_Function_inactive +#define FIU_ChildLock_RRtablet_Req_FIU_Msg2_Function_inactive (0) +#endif + + +// Value tables for @FIU_ChildLock_RRdoor_Req signal + +#ifndef FIU_ChildLock_RRdoor_Req_FIU_Msg2_Function_active +#define FIU_ChildLock_RRdoor_Req_FIU_Msg2_Function_active (1) +#endif + +#ifndef FIU_ChildLock_RRdoor_Req_FIU_Msg2_Function_inactive +#define FIU_ChildLock_RRdoor_Req_FIU_Msg2_Function_inactive (0) +#endif + + +// Value tables for @FIU_ChildLock_RCtablet_Req signal + +#ifndef FIU_ChildLock_RCtablet_Req_FIU_Msg2_Function_active +#define FIU_ChildLock_RCtablet_Req_FIU_Msg2_Function_active (1) +#endif + +#ifndef FIU_ChildLock_RCtablet_Req_FIU_Msg2_Function_inactive +#define FIU_ChildLock_RCtablet_Req_FIU_Msg2_Function_inactive (0) +#endif + + +// Value tables for @FIU_ChildLock_RLdoor_Req signal + +#ifndef FIU_ChildLock_RLdoor_Req_FIU_Msg2_Function_active +#define FIU_ChildLock_RLdoor_Req_FIU_Msg2_Function_active (1) +#endif + +#ifndef FIU_ChildLock_RLdoor_Req_FIU_Msg2_Function_inactive +#define FIU_ChildLock_RLdoor_Req_FIU_Msg2_Function_inactive (0) +#endif + + +// Value tables for @FIU_StyleLghtVoice_Req signal + +#ifndef FIU_StyleLghtVoice_Req_FIU_Msg2_Voice_Command_requested +#define FIU_StyleLghtVoice_Req_FIU_Msg2_Voice_Command_requested (1) +#endif + +#ifndef FIU_StyleLghtVoice_Req_FIU_Msg2_No_Voice_Command_requested_ +#define FIU_StyleLghtVoice_Req_FIU_Msg2_No_Voice_Command_requested_ (0) +#endif + + +// Value tables for @FIU_AlarmOFF_Req signal + +#ifndef FIU_AlarmOFF_Req_FIU_Msg2_Alarm_system_disabled +#define FIU_AlarmOFF_Req_FIU_Msg2_Alarm_system_disabled (1) +#endif + +#ifndef FIU_AlarmOFF_Req_FIU_Msg2_Alarm_system_enabled +#define FIU_AlarmOFF_Req_FIU_Msg2_Alarm_system_enabled (0) +#endif + + +// Value tables for @FIU_MovementSensOFF_Req signal + +#ifndef FIU_MovementSensOFF_Req_FIU_Msg2_Request_Active +#define FIU_MovementSensOFF_Req_FIU_Msg2_Request_Active (1) +#endif + +#ifndef FIU_MovementSensOFF_Req_FIU_Msg2_Request_Inactive +#define FIU_MovementSensOFF_Req_FIU_Msg2_Request_Inactive (0) +#endif + + +// Value tables for @FIU_ChildLock_RLwindow_Req signal + +#ifndef FIU_ChildLock_RLwindow_Req_FIU_Msg2_Function_active +#define FIU_ChildLock_RLwindow_Req_FIU_Msg2_Function_active (1) +#endif + +#ifndef FIU_ChildLock_RLwindow_Req_FIU_Msg2_Function_inactive +#define FIU_ChildLock_RLwindow_Req_FIU_Msg2_Function_inactive (0) +#endif + + +// Value tables for @FIU_CoolingBox_Req signal + +#ifndef FIU_CoolingBox_Req_FIU_Msg2_Normal_9C__Req +#define FIU_CoolingBox_Req_FIU_Msg2_Normal_9C__Req (3) +#endif + +#ifndef FIU_CoolingBox_Req_FIU_Msg2_Soft_5C_Req +#define FIU_CoolingBox_Req_FIU_Msg2_Soft_5C_Req (2) +#endif + +#ifndef FIU_CoolingBox_Req_FIU_Msg2_Off_Req +#define FIU_CoolingBox_Req_FIU_Msg2_Off_Req (1) +#endif + +#ifndef FIU_CoolingBox_Req_FIU_Msg2_No_change_Req +#define FIU_CoolingBox_Req_FIU_Msg2_No_change_Req (0) +#endif + + +// Value tables for @FIU_ChildLock_RRwindow_Req signal + +#ifndef FIU_ChildLock_RRwindow_Req_FIU_Msg2_Function_active +#define FIU_ChildLock_RRwindow_Req_FIU_Msg2_Function_active (1) +#endif + +#ifndef FIU_ChildLock_RRwindow_Req_FIU_Msg2_Function_inactive +#define FIU_ChildLock_RRwindow_Req_FIU_Msg2_Function_inactive (0) +#endif + + +// Value tables for @FIU_TrafficSide_Stat signal + +#ifndef FIU_TrafficSide_Stat_FIU_Msg2_RightHand +#define FIU_TrafficSide_Stat_FIU_Msg2_RightHand (1) +#endif + +#ifndef FIU_TrafficSide_Stat_FIU_Msg2_LeftHand +#define FIU_TrafficSide_Stat_FIU_Msg2_LeftHand (0) +#endif + + +// Value tables for @FIU_UnlockExternal_Req signal + +#ifndef FIU_UnlockExternal_Req_FIU_Msg2_Active +#define FIU_UnlockExternal_Req_FIU_Msg2_Active (1) +#endif + +#ifndef FIU_UnlockExternal_Req_FIU_Msg2_Inactive +#define FIU_UnlockExternal_Req_FIU_Msg2_Inactive (0) +#endif + + +// Value tables for @FIU_UnlockAfterDrive_Req signal + +#ifndef FIU_UnlockAfterDrive_Req_FIU_Msg2_Active +#define FIU_UnlockAfterDrive_Req_FIU_Msg2_Active (1) +#endif + +#ifndef FIU_UnlockAfterDrive_Req_FIU_Msg2_Inactive +#define FIU_UnlockAfterDrive_Req_FIU_Msg2_Inactive (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Style illumination global ON/OFF + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t FIU_StyleIllGlobal_Req : 1; // Bits= 1 + + // Child lock prevents rear left tablet from removing from rear compartment + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t FIU_ChildLock_RLtablet_Req : 1; // Bits= 1 + + // Request to activate the camera for video conferencing + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_ConfCamera_Req : 1; // Bits= 1 + + // Color theme presets for style ill + // 1 - AMETHYST + // 2 - LAPIS LAZU + // 3 - SAPPHIRE + // 4 - EMERALD + // 5 - AURUS + // 6 - RUBY + // 7 - PEARL + // 8 - Reserved + // 9 - MAJORELLE_TANZ + // 10 - AQUAMARINE + // 11 - CHRYSOLITE + // 12 - CRYSTAL + // 13 - AMBER + // 14 - PYROPE + // 15 - OPAL + // 16 - DIAMOND + // 15 : "Color theme 16" + // 14 : "Color theme 15" + // 13 : "Color theme 14" + // 12 : "Color theme 13" + // 11 : "Color theme 12" + // 10 : "Color theme 11" + // 9 : "Color theme 10" + // 8 : "Color theme 9" + // 7 : "Reserved" + // 6 : "Color theme 7" + // 5 : "Color theme 6" + // 4 : "Color theme 5" + // 3 : "Color theme 4" + // 2 : "Color theme 3" + // 1 : "Color theme 2" + // 0 : "Color theme 1" + uint8_t FIU_StyleIllTheme_Req : 4; // Bits= 4 + + // Child lock prevents rear right tablet from removing from rear compartment + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t FIU_ChildLock_RRtablet_Req : 1; // Bits= 1 + + // Child lock prevents rear right door from opening from rear compartment + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t FIU_ChildLock_RRdoor_Req : 1; // Bits= 1 + + // Child lock prevents rear central tablet from removing from rear compartment + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t FIU_ChildLock_RCtablet_Req : 1; // Bits= 1 + + // Child lock prevents rear left door from opening from rear compartment + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t FIU_ChildLock_RLdoor_Req : 1; // Bits= 1 + + // Request to BCM for actvatng a secial theme of styling lights,when user control the sytem via voice + // 1 : "Voice Command requested" + // 0 : "No Voice Command requested " + uint8_t FIU_StyleLghtVoice_Req : 1; // Bits= 1 + + // Disabling alarm system + // 1 : "Alarm system disabled" + // 0 : "Alarm system enabled" + uint8_t FIU_AlarmOFF_Req : 1; // Bits= 1 + + // Alarm doesn't activate when towing mode enabled (Motion sensor Inactive) + // 1 : "Request Active" + // 0 : "Request Inactive" + uint8_t FIU_MovementSensOFF_Req : 1; // Bits= 1 + + // Child lock prevents rear left window from opening from rear compartment + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t FIU_ChildLock_RLwindow_Req : 1; // Bits= 1 + + // Cooling box temperature control + // 3 : "Normal 9�C Req" + // 2 : "Soft 5�C Req" + // 1 : "Off Req" + // 0 : "No change Req" + uint8_t FIU_CoolingBox_Req : 2; // Bits= 2 + + // Child lock prevents rear right window from opening from rear compartment + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t FIU_ChildLock_RRwindow_Req : 1; // Bits= 1 + + // Selected road traffic side + // 1 : "Right-Hand" + // 0 : "Left-Hand" + uint8_t FIU_TrafficSide_Stat : 1; // Bits= 1 + + // 0x0: when external unlock request received at 1st time all doors shall unlock + // 0x1: when external unlock request received at 1st time only driver's door shall unlock, at 2nd time all doors shall unlock + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_UnlockExternal_Req : 1; // Bits= 1 + + // Style illumination brightness % + uint8_t FIU_StyleIllBright_Val : 7; // Bits= 7 Unit:'%' + + // Doors automatically unlocking after drive (selector in P position, ignition off) + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_UnlockAfterDrive_Req : 1; // Bits= 1 + +#else + + // Style illumination global ON/OFF + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t FIU_StyleIllGlobal_Req; // Bits= 1 + + // Child lock prevents rear left tablet from removing from rear compartment + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t FIU_ChildLock_RLtablet_Req; // Bits= 1 + + // Request to activate the camera for video conferencing + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_ConfCamera_Req; // Bits= 1 + + // Color theme presets for style ill + // 1 - AMETHYST + // 2 - LAPIS LAZU + // 3 - SAPPHIRE + // 4 - EMERALD + // 5 - AURUS + // 6 - RUBY + // 7 - PEARL + // 8 - Reserved + // 9 - MAJORELLE_TANZ + // 10 - AQUAMARINE + // 11 - CHRYSOLITE + // 12 - CRYSTAL + // 13 - AMBER + // 14 - PYROPE + // 15 - OPAL + // 16 - DIAMOND + // 15 : "Color theme 16" + // 14 : "Color theme 15" + // 13 : "Color theme 14" + // 12 : "Color theme 13" + // 11 : "Color theme 12" + // 10 : "Color theme 11" + // 9 : "Color theme 10" + // 8 : "Color theme 9" + // 7 : "Reserved" + // 6 : "Color theme 7" + // 5 : "Color theme 6" + // 4 : "Color theme 5" + // 3 : "Color theme 4" + // 2 : "Color theme 3" + // 1 : "Color theme 2" + // 0 : "Color theme 1" + uint8_t FIU_StyleIllTheme_Req; // Bits= 4 + + // Child lock prevents rear right tablet from removing from rear compartment + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t FIU_ChildLock_RRtablet_Req; // Bits= 1 + + // Child lock prevents rear right door from opening from rear compartment + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t FIU_ChildLock_RRdoor_Req; // Bits= 1 + + // Child lock prevents rear central tablet from removing from rear compartment + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t FIU_ChildLock_RCtablet_Req; // Bits= 1 + + // Child lock prevents rear left door from opening from rear compartment + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t FIU_ChildLock_RLdoor_Req; // Bits= 1 + + // Request to BCM for actvatng a secial theme of styling lights,when user control the sytem via voice + // 1 : "Voice Command requested" + // 0 : "No Voice Command requested " + uint8_t FIU_StyleLghtVoice_Req; // Bits= 1 + + // Disabling alarm system + // 1 : "Alarm system disabled" + // 0 : "Alarm system enabled" + uint8_t FIU_AlarmOFF_Req; // Bits= 1 + + // Alarm doesn't activate when towing mode enabled (Motion sensor Inactive) + // 1 : "Request Active" + // 0 : "Request Inactive" + uint8_t FIU_MovementSensOFF_Req; // Bits= 1 + + // Child lock prevents rear left window from opening from rear compartment + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t FIU_ChildLock_RLwindow_Req; // Bits= 1 + + // Cooling box temperature control + // 3 : "Normal 9�C Req" + // 2 : "Soft 5�C Req" + // 1 : "Off Req" + // 0 : "No change Req" + uint8_t FIU_CoolingBox_Req; // Bits= 2 + + // Child lock prevents rear right window from opening from rear compartment + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t FIU_ChildLock_RRwindow_Req; // Bits= 1 + + // Selected road traffic side + // 1 : "Right-Hand" + // 0 : "Left-Hand" + uint8_t FIU_TrafficSide_Stat; // Bits= 1 + + // 0x0: when external unlock request received at 1st time all doors shall unlock + // 0x1: when external unlock request received at 1st time only driver's door shall unlock, at 2nd time all doors shall unlock + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_UnlockExternal_Req; // Bits= 1 + + // Style illumination brightness % + uint8_t FIU_StyleIllBright_Val; // Bits= 7 Unit:'%' + + // Doors automatically unlocking after drive (selector in P position, ignition off) + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_UnlockAfterDrive_Req; // Bits= 1 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} FIU_Msg2_t; + +// def @ERAG_DATA_MSG CAN Message (1424 0x590) +#define ERAG_DATA_MSG_IDE (0U) +#define ERAG_DATA_MSG_DLC (3U) +#define ERAG_DATA_MSG_CANID (0x590U) +#define ERAG_DATA_MSG_CYC (1000U) + +// Value tables for @ERAG_FailureSts signal + +#ifndef ERAG_FailureSts_ERAG_DATA_MSG_Full_Failure +#define ERAG_FailureSts_ERAG_DATA_MSG_Full_Failure (6) +#endif + +#ifndef ERAG_FailureSts_ERAG_DATA_MSG_Unavailable_GSMGPRS +#define ERAG_FailureSts_ERAG_DATA_MSG_Unavailable_GSMGPRS (5) +#endif + +#ifndef ERAG_FailureSts_ERAG_DATA_MSG_Unavailable_GPS +#define ERAG_FailureSts_ERAG_DATA_MSG_Unavailable_GPS (4) +#endif + +#ifndef ERAG_FailureSts_ERAG_DATA_MSG_Unavailable_SOS_button +#define ERAG_FailureSts_ERAG_DATA_MSG_Unavailable_SOS_button (3) +#endif + +#ifndef ERAG_FailureSts_ERAG_DATA_MSG_Unavailable_speaker +#define ERAG_FailureSts_ERAG_DATA_MSG_Unavailable_speaker (2) +#endif + +#ifndef ERAG_FailureSts_ERAG_DATA_MSG_Unavailable_microphone +#define ERAG_FailureSts_ERAG_DATA_MSG_Unavailable_microphone (1) +#endif + +#ifndef ERAG_FailureSts_ERAG_DATA_MSG_No_Failure +#define ERAG_FailureSts_ERAG_DATA_MSG_No_Failure (0) +#endif + + +// Value tables for @ERAG_MuteReq signal + +#ifndef ERAG_MuteReq_ERAG_DATA_MSG_Mute_Active +#define ERAG_MuteReq_ERAG_DATA_MSG_Mute_Active (1) +#endif + +#ifndef ERAG_MuteReq_ERAG_DATA_MSG_Mute_Inactive +#define ERAG_MuteReq_ERAG_DATA_MSG_Mute_Inactive (0) +#endif + + +// Value tables for @ERAG_Status signal + +#ifndef ERAG_Status_ERAG_DATA_MSG_undefined +#define ERAG_Status_ERAG_DATA_MSG_undefined (31) +#endif + +#ifndef ERAG_Status_ERAG_DATA_MSG_not_used +#define ERAG_Status_ERAG_DATA_MSG_not_used (30) +#endif + +#ifndef ERAG_Status_ERAG_DATA_MSG_ +#define ERAG_Status_ERAG_DATA_MSG_ (19) +#endif + +#ifndef ERAG_Status_ERAG_DATA_MSG_not_used +#define ERAG_Status_ERAG_DATA_MSG_not_used (18) +#endif + +#ifndef ERAG_Status_ERAG_DATA_MSG_not_initialized +#define ERAG_Status_ERAG_DATA_MSG_not_initialized (17) +#endif + +#ifndef ERAG_Status_ERAG_DATA_MSG_incoming_call +#define ERAG_Status_ERAG_DATA_MSG_incoming_call (16) +#endif + +#ifndef ERAG_Status_ERAG_DATA_MSG_MSD_sends +#define ERAG_Status_ERAG_DATA_MSG_MSD_sends (15) +#endif + +#ifndef ERAG_Status_ERAG_DATA_MSG_sleep_pin +#define ERAG_Status_ERAG_DATA_MSG_sleep_pin (14) +#endif + +#ifndef ERAG_Status_ERAG_DATA_MSG_enable_sleep +#define ERAG_Status_ERAG_DATA_MSG_enable_sleep (13) +#endif + +#ifndef ERAG_Status_ERAG_DATA_MSG_dial +#define ERAG_Status_ERAG_DATA_MSG_dial (12) +#endif + +#ifndef ERAG_Status_ERAG_DATA_MSG_call_preparation +#define ERAG_Status_ERAG_DATA_MSG_call_preparation (11) +#endif + +#ifndef ERAG_Status_ERAG_DATA_MSG_registration +#define ERAG_Status_ERAG_DATA_MSG_registration (10) +#endif + +#ifndef ERAG_Status_ERAG_DATA_MSG_SERV_comm +#define ERAG_Status_ERAG_DATA_MSG_SERV_comm (9) +#endif + +#ifndef ERAG_Status_ERAG_DATA_MSG_SOS_comm +#define ERAG_Status_ERAG_DATA_MSG_SOS_comm (8) +#endif + +#ifndef ERAG_Status_ERAG_DATA_MSG_testing_sound_condition +#define ERAG_Status_ERAG_DATA_MSG_testing_sound_condition (7) +#endif + +#ifndef ERAG_Status_ERAG_DATA_MSG_testing_other +#define ERAG_Status_ERAG_DATA_MSG_testing_other (6) +#endif + +#ifndef ERAG_Status_ERAG_DATA_MSG_testing_w3 +#define ERAG_Status_ERAG_DATA_MSG_testing_w3 (5) +#endif + +#ifndef ERAG_Status_ERAG_DATA_MSG_testing_w2 +#define ERAG_Status_ERAG_DATA_MSG_testing_w2 (4) +#endif + +#ifndef ERAG_Status_ERAG_DATA_MSG_testing_w1 +#define ERAG_Status_ERAG_DATA_MSG_testing_w1 (3) +#endif + +#ifndef ERAG_Status_ERAG_DATA_MSG_sleep +#define ERAG_Status_ERAG_DATA_MSG_sleep (2) +#endif + +#ifndef ERAG_Status_ERAG_DATA_MSG_idle +#define ERAG_Status_ERAG_DATA_MSG_idle (1) +#endif + +#ifndef ERAG_Status_ERAG_DATA_MSG_initializing +#define ERAG_Status_ERAG_DATA_MSG_initializing (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Indicates the ERAG failures status: + // Bitwise indication: + // - bit position 0 set = Unavailable microphone + // - bit position 1 set = Unavailable speaker + // - bit position 2 set = No connection + // - bit position 3 set = Reserved + // 6 : "Full Failure" + // 5 : "Unavailable GSM/GPRS" + // 4 : "Unavailable GPS" + // 3 : "Unavailable SOS button" + // 2 : "Unavailable speaker" + // 1 : "Unavailable microphone" + // 0 : "No Failure" + uint8_t ERAG_FailureSts : 4; // Bits= 4 + + // Mute command + // 0x0 = Mute Inactive + // 0x1 = Mute Active + // 1 : "Mute Active" + // 0 : "Mute Inactive" + uint8_t ERAG_MuteReq : 1; // Bits= 1 + + // Indicates the ERAG status + // 31 : "undefined" + // 30 : "not_used" + // 19 : "..." + // 18 : "not_used" + // 17 : "not_initialized" + // 16 : "incoming_call" + // 15 : "MSD_sends" + // 14 : "sleep_pin" + // 13 : "enable_sleep" + // 12 : "dial" + // 11 : "call_preparation" + // 10 : "registration" + // 9 : "SERV_comm" + // 8 : "SOS_comm" + // 7 : "testing_sound condition" + // 6 : "testing_other" + // 5 : "testing_w3" + // 4 : "testing_w2" + // 3 : "testing_w1" + // 2 : "sleep" + // 1 : "idle" + // 0 : "initializing" + uint8_t ERAG_Status; // Bits= 8 + +#else + + // Indicates the ERAG failures status: + // Bitwise indication: + // - bit position 0 set = Unavailable microphone + // - bit position 1 set = Unavailable speaker + // - bit position 2 set = No connection + // - bit position 3 set = Reserved + // 6 : "Full Failure" + // 5 : "Unavailable GSM/GPRS" + // 4 : "Unavailable GPS" + // 3 : "Unavailable SOS button" + // 2 : "Unavailable speaker" + // 1 : "Unavailable microphone" + // 0 : "No Failure" + uint8_t ERAG_FailureSts; // Bits= 4 + + // Mute command + // 0x0 = Mute Inactive + // 0x1 = Mute Active + // 1 : "Mute Active" + // 0 : "Mute Inactive" + uint8_t ERAG_MuteReq; // Bits= 1 + + // Indicates the ERAG status + // 31 : "undefined" + // 30 : "not_used" + // 19 : "..." + // 18 : "not_used" + // 17 : "not_initialized" + // 16 : "incoming_call" + // 15 : "MSD_sends" + // 14 : "sleep_pin" + // 13 : "enable_sleep" + // 12 : "dial" + // 11 : "call_preparation" + // 10 : "registration" + // 9 : "SERV_comm" + // 8 : "SOS_comm" + // 7 : "testing_sound condition" + // 6 : "testing_other" + // 5 : "testing_w3" + // 4 : "testing_w2" + // 3 : "testing_w1" + // 2 : "sleep" + // 1 : "idle" + // 0 : "initializing" + uint8_t ERAG_Status; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} ERAG_DATA_MSG_t; + +// def @FIU_Msg3 CAN Message (1428 0x594) +#define FIU_Msg3_IDE (0U) +#define FIU_Msg3_DLC (8U) +#define FIU_Msg3_CANID (0x594U) + +// Value tables for @FIU_ArmrestHeatFL_Req signal + +#ifndef FIU_ArmrestHeatFL_Req_FIU_Msg3_Active +#define FIU_ArmrestHeatFL_Req_FIU_Msg3_Active (1) +#endif + +#ifndef FIU_ArmrestHeatFL_Req_FIU_Msg3_Inactive +#define FIU_ArmrestHeatFL_Req_FIU_Msg3_Inactive (0) +#endif + + +// Value tables for @FIU_ArmrestHeatFR_Req signal + +#ifndef FIU_ArmrestHeatFR_Req_FIU_Msg3_Active +#define FIU_ArmrestHeatFR_Req_FIU_Msg3_Active (1) +#endif + +#ifndef FIU_ArmrestHeatFR_Req_FIU_Msg3_Inactive +#define FIU_ArmrestHeatFR_Req_FIU_Msg3_Inactive (0) +#endif + + +// Value tables for @FIU_ArmrestHeatRL_Req signal + +#ifndef FIU_ArmrestHeatRL_Req_FIU_Msg3_Active +#define FIU_ArmrestHeatRL_Req_FIU_Msg3_Active (1) +#endif + +#ifndef FIU_ArmrestHeatRL_Req_FIU_Msg3_Inactive +#define FIU_ArmrestHeatRL_Req_FIU_Msg3_Inactive (0) +#endif + + +// Value tables for @FIU_ArmrestHeatRR_Req signal + +#ifndef FIU_ArmrestHeatRR_Req_FIU_Msg3_Active +#define FIU_ArmrestHeatRR_Req_FIU_Msg3_Active (1) +#endif + +#ifndef FIU_ArmrestHeatRR_Req_FIU_Msg3_Inactive +#define FIU_ArmrestHeatRR_Req_FIU_Msg3_Inactive (0) +#endif + + +// Value tables for @FIU_FL_Synx_Req signal + +#ifndef FIU_FL_Synx_Req_FIU_Msg3_No_synx +#define FIU_FL_Synx_Req_FIU_Msg3_No_synx (2) +#endif + +#ifndef FIU_FL_Synx_Req_FIU_Msg3_Synx +#define FIU_FL_Synx_Req_FIU_Msg3_Synx (1) +#endif + +#ifndef FIU_FL_Synx_Req_FIU_Msg3_No_change +#define FIU_FL_Synx_Req_FIU_Msg3_No_change (0) +#endif + + +// Value tables for @FIU_FR_Synx_Req signal + +#ifndef FIU_FR_Synx_Req_FIU_Msg3_No_synx +#define FIU_FR_Synx_Req_FIU_Msg3_No_synx (2) +#endif + +#ifndef FIU_FR_Synx_Req_FIU_Msg3_Synx +#define FIU_FR_Synx_Req_FIU_Msg3_Synx (1) +#endif + +#ifndef FIU_FR_Synx_Req_FIU_Msg3_No_change +#define FIU_FR_Synx_Req_FIU_Msg3_No_change (0) +#endif + + +// Value tables for @FIU_RL_Synx_Req signal + +#ifndef FIU_RL_Synx_Req_FIU_Msg3_No_synx +#define FIU_RL_Synx_Req_FIU_Msg3_No_synx (2) +#endif + +#ifndef FIU_RL_Synx_Req_FIU_Msg3_Synx +#define FIU_RL_Synx_Req_FIU_Msg3_Synx (1) +#endif + +#ifndef FIU_RL_Synx_Req_FIU_Msg3_No_change +#define FIU_RL_Synx_Req_FIU_Msg3_No_change (0) +#endif + + +// Value tables for @FIU_RR_Synx_Req signal + +#ifndef FIU_RR_Synx_Req_FIU_Msg3_No_synx +#define FIU_RR_Synx_Req_FIU_Msg3_No_synx (2) +#endif + +#ifndef FIU_RR_Synx_Req_FIU_Msg3_Synx +#define FIU_RR_Synx_Req_FIU_Msg3_Synx (1) +#endif + +#ifndef FIU_RR_Synx_Req_FIU_Msg3_No_change +#define FIU_RR_Synx_Req_FIU_Msg3_No_change (0) +#endif + + +// Value tables for @FIU_SchedTue_Stat signal + +#ifndef FIU_SchedTue_Stat_FIU_Msg3_Inactive +#define FIU_SchedTue_Stat_FIU_Msg3_Inactive (0) +#endif + +#ifndef FIU_SchedTue_Stat_FIU_Msg3_Active +#define FIU_SchedTue_Stat_FIU_Msg3_Active (1) +#endif + + +// Value tables for @FIU_SchedWed_Stat signal + +#ifndef FIU_SchedWed_Stat_FIU_Msg3_Inactive +#define FIU_SchedWed_Stat_FIU_Msg3_Inactive (0) +#endif + +#ifndef FIU_SchedWed_Stat_FIU_Msg3_Active +#define FIU_SchedWed_Stat_FIU_Msg3_Active (1) +#endif + + +// Value tables for @FIU_SchedThu_Stat signal + +#ifndef FIU_SchedThu_Stat_FIU_Msg3_Inactive +#define FIU_SchedThu_Stat_FIU_Msg3_Inactive (0) +#endif + +#ifndef FIU_SchedThu_Stat_FIU_Msg3_Active +#define FIU_SchedThu_Stat_FIU_Msg3_Active (1) +#endif + + +// Value tables for @FIU_SchedFri_Stat signal + +#ifndef FIU_SchedFri_Stat_FIU_Msg3_Inactive +#define FIU_SchedFri_Stat_FIU_Msg3_Inactive (0) +#endif + +#ifndef FIU_SchedFri_Stat_FIU_Msg3_Active +#define FIU_SchedFri_Stat_FIU_Msg3_Active (1) +#endif + + +// Value tables for @FIU_ICimage_Req signal + +#ifndef FIU_ICimage_Req_FIU_Msg3_Image_3 +#define FIU_ICimage_Req_FIU_Msg3_Image_3 (3) +#endif + +#ifndef FIU_ICimage_Req_FIU_Msg3_Image_2 +#define FIU_ICimage_Req_FIU_Msg3_Image_2 (2) +#endif + +#ifndef FIU_ICimage_Req_FIU_Msg3_Image_1 +#define FIU_ICimage_Req_FIU_Msg3_Image_1 (1) +#endif + +#ifndef FIU_ICimage_Req_FIU_Msg3_No_action +#define FIU_ICimage_Req_FIU_Msg3_No_action (0) +#endif + + +// Value tables for @FIU_ProjectionOnRoad_Req signal + +#ifndef FIU_ProjectionOnRoad_Req_FIU_Msg3_Active +#define FIU_ProjectionOnRoad_Req_FIU_Msg3_Active (1) +#endif + +#ifndef FIU_ProjectionOnRoad_Req_FIU_Msg3_Inactive +#define FIU_ProjectionOnRoad_Req_FIU_Msg3_Inactive (0) +#endif + + +// Value tables for @FIU_RearSideWindowsElcrome_Req signal + +#ifndef FIU_RearSideWindowsElcrome_Req_FIU_Msg3_Strong +#define FIU_RearSideWindowsElcrome_Req_FIU_Msg3_Strong (3) +#endif + +#ifndef FIU_RearSideWindowsElcrome_Req_FIU_Msg3_Medium +#define FIU_RearSideWindowsElcrome_Req_FIU_Msg3_Medium (2) +#endif + +#ifndef FIU_RearSideWindowsElcrome_Req_FIU_Msg3_Soft +#define FIU_RearSideWindowsElcrome_Req_FIU_Msg3_Soft (1) +#endif + +#ifndef FIU_RearSideWindowsElcrome_Req_FIU_Msg3_No_action +#define FIU_RearSideWindowsElcrome_Req_FIU_Msg3_No_action (0) +#endif + + +// Value tables for @FIU_ProjectionRoadSigns_Req signal + +#ifndef FIU_ProjectionRoadSigns_Req_FIU_Msg3_Active +#define FIU_ProjectionRoadSigns_Req_FIU_Msg3_Active (1) +#endif + +#ifndef FIU_ProjectionRoadSigns_Req_FIU_Msg3_Inactive +#define FIU_ProjectionRoadSigns_Req_FIU_Msg3_Inactive (0) +#endif + + +// Value tables for @FIU_ProjectionNavigation_Req signal + +#ifndef FIU_ProjectionNavigation_Req_FIU_Msg3_Inactive +#define FIU_ProjectionNavigation_Req_FIU_Msg3_Inactive (0) +#endif + +#ifndef FIU_ProjectionNavigation_Req_FIU_Msg3_Active +#define FIU_ProjectionNavigation_Req_FIU_Msg3_Active (1) +#endif + + +// Value tables for @FIU_ProjectionLiveObj_Req signal + +#ifndef FIU_ProjectionLiveObj_Req_FIU_Msg3_Active +#define FIU_ProjectionLiveObj_Req_FIU_Msg3_Active (1) +#endif + +#ifndef FIU_ProjectionLiveObj_Req_FIU_Msg3_Inactive +#define FIU_ProjectionLiveObj_Req_FIU_Msg3_Inactive (0) +#endif + + +// Value tables for @FIU_SchedSat_Stat signal + +#ifndef FIU_SchedSat_Stat_FIU_Msg3_Inactive +#define FIU_SchedSat_Stat_FIU_Msg3_Inactive (0) +#endif + +#ifndef FIU_SchedSat_Stat_FIU_Msg3_Active +#define FIU_SchedSat_Stat_FIU_Msg3_Active (1) +#endif + + +// Value tables for @FIU_SchedSu_Stat signal + +#ifndef FIU_SchedSu_Stat_FIU_Msg3_Inactive +#define FIU_SchedSu_Stat_FIU_Msg3_Inactive (0) +#endif + +#ifndef FIU_SchedSu_Stat_FIU_Msg3_Active +#define FIU_SchedSu_Stat_FIU_Msg3_Active (1) +#endif + + +// Value tables for @FIU_SchedStart_Stat signal + +#ifndef FIU_SchedStart_Stat_FIU_Msg3_Inactive +#define FIU_SchedStart_Stat_FIU_Msg3_Inactive (0) +#endif + +#ifndef FIU_SchedStart_Stat_FIU_Msg3_Active +#define FIU_SchedStart_Stat_FIU_Msg3_Active (1) +#endif + + +// Value tables for @FIU_ChrgLim_Val signal + +#ifndef FIU_ChrgLim_Val_FIU_Msg3_set_100__limit +#define FIU_ChrgLim_Val_FIU_Msg3_set_100__limit (7) +#endif + +#ifndef FIU_ChrgLim_Val_FIU_Msg3_set_90__limit +#define FIU_ChrgLim_Val_FIU_Msg3_set_90__limit (6) +#endif + +#ifndef FIU_ChrgLim_Val_FIU_Msg3_set_80__limit +#define FIU_ChrgLim_Val_FIU_Msg3_set_80__limit (5) +#endif + +#ifndef FIU_ChrgLim_Val_FIU_Msg3_set_70__limit +#define FIU_ChrgLim_Val_FIU_Msg3_set_70__limit (4) +#endif + +#ifndef FIU_ChrgLim_Val_FIU_Msg3_set_60__limit +#define FIU_ChrgLim_Val_FIU_Msg3_set_60__limit (3) +#endif + +#ifndef FIU_ChrgLim_Val_FIU_Msg3_Reserved +#define FIU_ChrgLim_Val_FIU_Msg3_Reserved (2) +#endif + +#ifndef FIU_ChrgLim_Val_FIU_Msg3_Reserved +#define FIU_ChrgLim_Val_FIU_Msg3_Reserved (1) +#endif + +#ifndef FIU_ChrgLim_Val_FIU_Msg3_No_change +#define FIU_ChrgLim_Val_FIU_Msg3_No_change (0) +#endif + + +// Value tables for @FIU_DischrgLim_Val signal + +#ifndef FIU_DischrgLim_Val_FIU_Msg3_Reserved +#define FIU_DischrgLim_Val_FIU_Msg3_Reserved (7) +#endif + +#ifndef FIU_DischrgLim_Val_FIU_Msg3_set_60__limit +#define FIU_DischrgLim_Val_FIU_Msg3_set_60__limit (6) +#endif + +#ifndef FIU_DischrgLim_Val_FIU_Msg3_set_50__limit +#define FIU_DischrgLim_Val_FIU_Msg3_set_50__limit (5) +#endif + +#ifndef FIU_DischrgLim_Val_FIU_Msg3_set_40__limit +#define FIU_DischrgLim_Val_FIU_Msg3_set_40__limit (4) +#endif + +#ifndef FIU_DischrgLim_Val_FIU_Msg3_set_30__limit +#define FIU_DischrgLim_Val_FIU_Msg3_set_30__limit (3) +#endif + +#ifndef FIU_DischrgLim_Val_FIU_Msg3_set_20__limit +#define FIU_DischrgLim_Val_FIU_Msg3_set_20__limit (2) +#endif + +#ifndef FIU_DischrgLim_Val_FIU_Msg3_Reserved +#define FIU_DischrgLim_Val_FIU_Msg3_Reserved (1) +#endif + +#ifndef FIU_DischrgLim_Val_FIU_Msg3_No_change +#define FIU_DischrgLim_Val_FIU_Msg3_No_change (0) +#endif + + +// Value tables for @FIU_ReduceChrgCurr_Stat signal + +#ifndef FIU_ReduceChrgCurr_Stat_FIU_Msg3_Inactive +#define FIU_ReduceChrgCurr_Stat_FIU_Msg3_Inactive (0) +#endif + +#ifndef FIU_ReduceChrgCurr_Stat_FIU_Msg3_Active +#define FIU_ReduceChrgCurr_Stat_FIU_Msg3_Active (1) +#endif + + +// Value tables for @FIU_SchedMon_Stat signal + +#ifndef FIU_SchedMon_Stat_FIU_Msg3_Inactive +#define FIU_SchedMon_Stat_FIU_Msg3_Inactive (0) +#endif + +#ifndef FIU_SchedMon_Stat_FIU_Msg3_Active +#define FIU_SchedMon_Stat_FIU_Msg3_Active (1) +#endif + +// signal: @FIU_Sched_StartTimeMinutes_Val_ro +#define CANDB_FIU_Sched_StartTimeMinutes_Val_ro_CovFactor (5) +#define CANDB_FIU_Sched_StartTimeMinutes_Val_ro_toS(x) ( (uint8_t) ((x) / (5)) ) +#define CANDB_FIU_Sched_StartTimeMinutes_Val_ro_fromS(x) ( ((x) * (5)) ) +// signal: @FIU_Sched_EndTimeMinutes_Val_ro +#define CANDB_FIU_Sched_EndTimeMinutes_Val_ro_CovFactor (5) +#define CANDB_FIU_Sched_EndTimeMinutes_Val_ro_toS(x) ( (uint8_t) ((x) / (5)) ) +#define CANDB_FIU_Sched_EndTimeMinutes_Val_ro_fromS(x) ( ((x) * (5)) ) + +// Value tables for @FIU_SchedEnd_Stat signal + +#ifndef FIU_SchedEnd_Stat_FIU_Msg3_Inactive +#define FIU_SchedEnd_Stat_FIU_Msg3_Inactive (0) +#endif + +#ifndef FIU_SchedEnd_Stat_FIU_Msg3_Active +#define FIU_SchedEnd_Stat_FIU_Msg3_Active (1) +#endif + + +// Value tables for @FIU_PrepearClim_Stat signal + +#ifndef FIU_PrepearClim_Stat_FIU_Msg3_Inactive +#define FIU_PrepearClim_Stat_FIU_Msg3_Inactive (0) +#endif + +#ifndef FIU_PrepearClim_Stat_FIU_Msg3_Active +#define FIU_PrepearClim_Stat_FIU_Msg3_Active (1) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Armrest heating request for front left zone + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_ArmrestHeatFL_Req : 1; // Bits= 1 + + // Armrest heating request for front right zone + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_ArmrestHeatFR_Req : 1; // Bits= 1 + + // Armrest heating request for rear left zone + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_ArmrestHeatRL_Req : 1; // Bits= 1 + + // Armrest heating request for rear right zone + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_ArmrestHeatRR_Req : 1; // Bits= 1 + + // SYNX mode command + // 2 : "No synx" + // 1 : "Synx" + // 0 : "No change" + uint8_t FIU_FL_Synx_Req : 2; // Bits= 2 + + // SYNX mode command + // 2 : "No synx" + // 1 : "Synx" + // 0 : "No change" + uint8_t FIU_FR_Synx_Req : 2; // Bits= 2 + + // SYNX mode command + // 2 : "No synx" + // 1 : "Synx" + // 0 : "No change" + uint8_t FIU_RL_Synx_Req : 2; // Bits= 2 + + // SYNX mode command + // 2 : "No synx" + // 1 : "Synx" + // 0 : "No change" + uint8_t FIU_RR_Synx_Req : 2; // Bits= 2 + + // Repeat function in Tuesday + // 0 : "Inactive" + // 1 : "Active" + uint8_t FIU_SchedTue_Stat : 1; // Bits= 1 + + // Repeat function in Wednesday + // 0 : "Inactive" + // 1 : "Active" + uint8_t FIU_SchedWed_Stat : 1; // Bits= 1 + + // Repeat function in Thursday + // 0 : "Inactive" + // 1 : "Active" + uint8_t FIU_SchedThu_Stat : 1; // Bits= 1 + + // Repeat function in Friday + // 0 : "Inactive" + // 1 : "Active" + uint8_t FIU_SchedFri_Stat : 1; // Bits= 1 + + // IC image changing request + // 3 : "Image 3" + // 2 : "Image 2" + // 1 : "Image 1" + // 0 : "No action" + uint8_t FIU_ICimage_Req : 2; // Bits= 2 + + // Projection on a road enable request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_ProjectionOnRoad_Req : 1; // Bits= 1 + + // Request for dimming rear side windows + // 3 : "Strong" + // 2 : "Medium" + // 1 : "Soft" + // 0 : "No action" + uint8_t FIU_RearSideWindowsElcrome_Req : 2; // Bits= 2 + + // Projection of road signs enable request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_ProjectionRoadSigns_Req : 1; // Bits= 1 + + // Projection of navigatoon system enable request + // 0 : "Inactive" + // 1 : "Active" + uint8_t FIU_ProjectionNavigation_Req : 1; // Bits= 1 + + // Projection of recognized live objects enable request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_ProjectionLiveObj_Req : 1; // Bits= 1 + + // Repeat function in Saturday + // 0 : "Inactive" + // 1 : "Active" + uint8_t FIU_SchedSat_Stat : 1; // Bits= 1 + + // Repeat function in Sunday + // 0 : "Inactive" + // 1 : "Active" + uint8_t FIU_SchedSu_Stat : 1; // Bits= 1 + + // Start charging time (Hours) + uint8_t FIU_Sched_StartTimeHours_Val : 5; // Bits= 5 Unit:'h' + + // Activate/Deactivate charging start timer + // 0 : "Inactive" + // 1 : "Active" + uint8_t FIU_SchedStart_Stat : 1; // Bits= 1 + + // Set battery charging limit + // 7 : "set 100 % limit" + // 6 : "set 90 % limit" + // 5 : "set 80 % limit" + // 4 : "set 70 % limit" + // 3 : "set 60 % limit" + // 2 : "Reserved" + // 1 : "Reserved" + // 0 : "No change" + uint8_t FIU_ChrgLim_Val : 3; // Bits= 3 + + // Set battery discharging limit + // 7 : "Reserved" + // 6 : "set 60 % limit" + // 5 : "set 50 % limit" + // 4 : "set 40 % limit" + // 3 : "set 30 % limit" + // 2 : "set 20 % limit" + // 1 : "Reserved" + // 0 : "No change" + uint8_t FIU_DischrgLim_Val : 3; // Bits= 3 + + // On/OFF Reduce charging current function + // 0 : "Inactive" + // 1 : "Active" + uint8_t FIU_ReduceChrgCurr_Stat : 1; // Bits= 1 + + // Repeat function in Monday + // 0 : "Inactive" + // 1 : "Active" + uint8_t FIU_SchedMon_Stat : 1; // Bits= 1 + + // Start charging time (Minutes) + uint8_t FIU_Sched_StartTimeMinutes_Val_ro : 4; // Bits= 4 Factor= 5 Unit:'min' + +#ifdef CANDB_USE_SIGFLOAT + uint8_t FIU_Sched_StartTimeMinutes_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // End charging time (Minutes) + uint8_t FIU_Sched_EndTimeMinutes_Val_ro : 4; // Bits= 4 Factor= 5 Unit:'min' + +#ifdef CANDB_USE_SIGFLOAT + uint8_t FIU_Sched_EndTimeMinutes_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // End charging time (Hours) + uint8_t FIU_Sched_EndTimeHours_Val : 5; // Bits= 5 Unit:'h' + + // Activate/Deactivate charging end timer + // 0 : "Inactive" + // 1 : "Active" + uint8_t FIU_SchedEnd_Stat : 1; // Bits= 1 + + // Activate/Deactivate Pre-conditional climate at end + // 0 : "Inactive" + // 1 : "Active" + uint8_t FIU_PrepearClim_Stat : 1; // Bits= 1 + +#else + + // Armrest heating request for front left zone + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_ArmrestHeatFL_Req; // Bits= 1 + + // Armrest heating request for front right zone + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_ArmrestHeatFR_Req; // Bits= 1 + + // Armrest heating request for rear left zone + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_ArmrestHeatRL_Req; // Bits= 1 + + // Armrest heating request for rear right zone + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_ArmrestHeatRR_Req; // Bits= 1 + + // SYNX mode command + // 2 : "No synx" + // 1 : "Synx" + // 0 : "No change" + uint8_t FIU_FL_Synx_Req; // Bits= 2 + + // SYNX mode command + // 2 : "No synx" + // 1 : "Synx" + // 0 : "No change" + uint8_t FIU_FR_Synx_Req; // Bits= 2 + + // SYNX mode command + // 2 : "No synx" + // 1 : "Synx" + // 0 : "No change" + uint8_t FIU_RL_Synx_Req; // Bits= 2 + + // SYNX mode command + // 2 : "No synx" + // 1 : "Synx" + // 0 : "No change" + uint8_t FIU_RR_Synx_Req; // Bits= 2 + + // Repeat function in Tuesday + // 0 : "Inactive" + // 1 : "Active" + uint8_t FIU_SchedTue_Stat; // Bits= 1 + + // Repeat function in Wednesday + // 0 : "Inactive" + // 1 : "Active" + uint8_t FIU_SchedWed_Stat; // Bits= 1 + + // Repeat function in Thursday + // 0 : "Inactive" + // 1 : "Active" + uint8_t FIU_SchedThu_Stat; // Bits= 1 + + // Repeat function in Friday + // 0 : "Inactive" + // 1 : "Active" + uint8_t FIU_SchedFri_Stat; // Bits= 1 + + // IC image changing request + // 3 : "Image 3" + // 2 : "Image 2" + // 1 : "Image 1" + // 0 : "No action" + uint8_t FIU_ICimage_Req; // Bits= 2 + + // Projection on a road enable request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_ProjectionOnRoad_Req; // Bits= 1 + + // Request for dimming rear side windows + // 3 : "Strong" + // 2 : "Medium" + // 1 : "Soft" + // 0 : "No action" + uint8_t FIU_RearSideWindowsElcrome_Req; // Bits= 2 + + // Projection of road signs enable request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_ProjectionRoadSigns_Req; // Bits= 1 + + // Projection of navigatoon system enable request + // 0 : "Inactive" + // 1 : "Active" + uint8_t FIU_ProjectionNavigation_Req; // Bits= 1 + + // Projection of recognized live objects enable request + // 1 : "Active" + // 0 : "Inactive" + uint8_t FIU_ProjectionLiveObj_Req; // Bits= 1 + + // Repeat function in Saturday + // 0 : "Inactive" + // 1 : "Active" + uint8_t FIU_SchedSat_Stat; // Bits= 1 + + // Repeat function in Sunday + // 0 : "Inactive" + // 1 : "Active" + uint8_t FIU_SchedSu_Stat; // Bits= 1 + + // Start charging time (Hours) + uint8_t FIU_Sched_StartTimeHours_Val; // Bits= 5 Unit:'h' + + // Activate/Deactivate charging start timer + // 0 : "Inactive" + // 1 : "Active" + uint8_t FIU_SchedStart_Stat; // Bits= 1 + + // Set battery charging limit + // 7 : "set 100 % limit" + // 6 : "set 90 % limit" + // 5 : "set 80 % limit" + // 4 : "set 70 % limit" + // 3 : "set 60 % limit" + // 2 : "Reserved" + // 1 : "Reserved" + // 0 : "No change" + uint8_t FIU_ChrgLim_Val; // Bits= 3 + + // Set battery discharging limit + // 7 : "Reserved" + // 6 : "set 60 % limit" + // 5 : "set 50 % limit" + // 4 : "set 40 % limit" + // 3 : "set 30 % limit" + // 2 : "set 20 % limit" + // 1 : "Reserved" + // 0 : "No change" + uint8_t FIU_DischrgLim_Val; // Bits= 3 + + // On/OFF Reduce charging current function + // 0 : "Inactive" + // 1 : "Active" + uint8_t FIU_ReduceChrgCurr_Stat; // Bits= 1 + + // Repeat function in Monday + // 0 : "Inactive" + // 1 : "Active" + uint8_t FIU_SchedMon_Stat; // Bits= 1 + + // Start charging time (Minutes) + uint8_t FIU_Sched_StartTimeMinutes_Val_ro; // Bits= 4 Factor= 5 Unit:'min' + +#ifdef CANDB_USE_SIGFLOAT + uint8_t FIU_Sched_StartTimeMinutes_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // End charging time (Minutes) + uint8_t FIU_Sched_EndTimeMinutes_Val_ro; // Bits= 4 Factor= 5 Unit:'min' + +#ifdef CANDB_USE_SIGFLOAT + uint8_t FIU_Sched_EndTimeMinutes_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // End charging time (Hours) + uint8_t FIU_Sched_EndTimeHours_Val; // Bits= 5 Unit:'h' + + // Activate/Deactivate charging end timer + // 0 : "Inactive" + // 1 : "Active" + uint8_t FIU_SchedEnd_Stat; // Bits= 1 + + // Activate/Deactivate Pre-conditional climate at end + // 0 : "Inactive" + // 1 : "Active" + uint8_t FIU_PrepearClim_Stat; // Bits= 1 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} FIU_Msg3_t; + +// def @FIU_EngMenu CAN Message (1429 0x595) +#define FIU_EngMenu_IDE (0U) +#define FIU_EngMenu_DLC (8U) +#define FIU_EngMenu_CANID (0x595U) + +// Value tables for @FIU_EngMenuTabLock_RL_Req signal + +#ifndef FIU_EngMenuTabLock_RL_Req_FIU_EngMenu_Unlock +#define FIU_EngMenuTabLock_RL_Req_FIU_EngMenu_Unlock (1) +#endif + +#ifndef FIU_EngMenuTabLock_RL_Req_FIU_EngMenu_No_action +#define FIU_EngMenuTabLock_RL_Req_FIU_EngMenu_No_action (0) +#endif + + +// Value tables for @FIU_EngMenuTabLock_RR_Req signal + +#ifndef FIU_EngMenuTabLock_RR_Req_FIU_EngMenu_Unlock +#define FIU_EngMenuTabLock_RR_Req_FIU_EngMenu_Unlock (1) +#endif + +#ifndef FIU_EngMenuTabLock_RR_Req_FIU_EngMenu_No_action +#define FIU_EngMenuTabLock_RR_Req_FIU_EngMenu_No_action (0) +#endif + + +// Value tables for @FIU_EngMenuTabLock_RC_Req signal + +#ifndef FIU_EngMenuTabLock_RC_Req_FIU_EngMenu_Unlock +#define FIU_EngMenuTabLock_RC_Req_FIU_EngMenu_Unlock (1) +#endif + +#ifndef FIU_EngMenuTabLock_RC_Req_FIU_EngMenu_No_action +#define FIU_EngMenuTabLock_RC_Req_FIU_EngMenu_No_action (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Rear left tablet lock via engineering menu + // 1 : "Unlock" + // 0 : "No action" + uint8_t FIU_EngMenuTabLock_RL_Req : 1; // Bits= 1 + + // Rear right tablet lock via engineering menu + // 1 : "Unlock" + // 0 : "No action" + uint8_t FIU_EngMenuTabLock_RR_Req : 1; // Bits= 1 + + // Rear center tablet lock via engineering menu + // 1 : "Unlock" + // 0 : "No action" + uint8_t FIU_EngMenuTabLock_RC_Req : 1; // Bits= 1 + +#else + + // Rear left tablet lock via engineering menu + // 1 : "Unlock" + // 0 : "No action" + uint8_t FIU_EngMenuTabLock_RL_Req; // Bits= 1 + + // Rear right tablet lock via engineering menu + // 1 : "Unlock" + // 0 : "No action" + uint8_t FIU_EngMenuTabLock_RR_Req; // Bits= 1 + + // Rear center tablet lock via engineering menu + // 1 : "Unlock" + // 0 : "No action" + uint8_t FIU_EngMenuTabLock_RC_Req; // Bits= 1 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} FIU_EngMenu_t; + +// def @WHFL_MSG1 CAN Message (1430 0x596) +#define WHFL_MSG1_IDE (0U) +#define WHFL_MSG1_DLC (8U) +#define WHFL_MSG1_CANID (0x596U) +#define WHFL_MSG1_CYC (1000U) + +// Value tables for @WHFL_PowerMode_Stat signal + +#ifndef WHFL_PowerMode_Stat_WHFL_MSG1_Reserved +#define WHFL_PowerMode_Stat_WHFL_MSG1_Reserved (7) +#endif + +#ifndef WHFL_PowerMode_Stat_WHFL_MSG1_Reserved +#define WHFL_PowerMode_Stat_WHFL_MSG1_Reserved (6) +#endif + +#ifndef WHFL_PowerMode_Stat_WHFL_MSG1_Invalid +#define WHFL_PowerMode_Stat_WHFL_MSG1_Invalid (5) +#endif + +#ifndef WHFL_PowerMode_Stat_WHFL_MSG1_ +#define WHFL_PowerMode_Stat_WHFL_MSG1_ (4) +#endif + +#ifndef WHFL_PowerMode_Stat_WHFL_MSG1_ +#define WHFL_PowerMode_Stat_WHFL_MSG1_ (3) +#endif + +#ifndef WHFL_PowerMode_Stat_WHFL_MSG1_ +#define WHFL_PowerMode_Stat_WHFL_MSG1_ (2) +#endif + +#ifndef WHFL_PowerMode_Stat_WHFL_MSG1_ +#define WHFL_PowerMode_Stat_WHFL_MSG1_ (1) +#endif + +#ifndef WHFL_PowerMode_Stat_WHFL_MSG1_Window_Heating_Off +#define WHFL_PowerMode_Stat_WHFL_MSG1_Window_Heating_Off (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Current status of Front Left Window Heating ECU + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Invalid" + // 4 : "100%" + // 3 : "75%" + // 2 : "50%" + // 1 : "25%" + // 0 : "Window Heating Off" + uint8_t WHFL_PowerMode_Stat : 3; // Bits= 3 + +#else + + // Current status of Front Left Window Heating ECU + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Invalid" + // 4 : "100%" + // 3 : "75%" + // 2 : "50%" + // 1 : "25%" + // 0 : "Window Heating Off" + uint8_t WHFL_PowerMode_Stat; // Bits= 3 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} WHFL_MSG1_t; + +// def @WHFR_Msg1 CAN Message (1431 0x597) +#define WHFR_Msg1_IDE (0U) +#define WHFR_Msg1_DLC (8U) +#define WHFR_Msg1_CANID (0x597U) +#define WHFR_Msg1_CYC (1000U) + +// Value tables for @WHFR_PowerMode_Stat signal + +#ifndef WHFR_PowerMode_Stat_WHFR_Msg1_Reserved +#define WHFR_PowerMode_Stat_WHFR_Msg1_Reserved (7) +#endif + +#ifndef WHFR_PowerMode_Stat_WHFR_Msg1_Reserved +#define WHFR_PowerMode_Stat_WHFR_Msg1_Reserved (6) +#endif + +#ifndef WHFR_PowerMode_Stat_WHFR_Msg1_Invalid +#define WHFR_PowerMode_Stat_WHFR_Msg1_Invalid (5) +#endif + +#ifndef WHFR_PowerMode_Stat_WHFR_Msg1_ +#define WHFR_PowerMode_Stat_WHFR_Msg1_ (4) +#endif + +#ifndef WHFR_PowerMode_Stat_WHFR_Msg1_ +#define WHFR_PowerMode_Stat_WHFR_Msg1_ (3) +#endif + +#ifndef WHFR_PowerMode_Stat_WHFR_Msg1_ +#define WHFR_PowerMode_Stat_WHFR_Msg1_ (2) +#endif + +#ifndef WHFR_PowerMode_Stat_WHFR_Msg1_ +#define WHFR_PowerMode_Stat_WHFR_Msg1_ (1) +#endif + +#ifndef WHFR_PowerMode_Stat_WHFR_Msg1_Window_Heating_Off +#define WHFR_PowerMode_Stat_WHFR_Msg1_Window_Heating_Off (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Current status of Front Left Window Heating ECU + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Invalid" + // 4 : "100%" + // 3 : "75%" + // 2 : "50%" + // 1 : "25%" + // 0 : "Window Heating Off" + uint8_t WHFR_PowerMode_Stat : 3; // Bits= 3 + +#else + + // Current status of Front Left Window Heating ECU + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Invalid" + // 4 : "100%" + // 3 : "75%" + // 2 : "50%" + // 1 : "25%" + // 0 : "Window Heating Off" + uint8_t WHFR_PowerMode_Stat; // Bits= 3 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} WHFR_Msg1_t; + +// def @PLDSilCU_State CAN Message (1432 0x598) +#define PLDSilCU_State_IDE (0U) +#define PLDSilCU_State_DLC (8U) +#define PLDSilCU_State_CANID (0x598U) + +// Value tables for @PLDSilCU_Module_Stat signal + +#ifndef PLDSilCU_Module_Stat_PLDSilCU_State_Scenario_data_message_error +#define PLDSilCU_Module_Stat_PLDSilCU_State_Scenario_data_message_error (8) +#endif + +#ifndef PLDSilCU_Module_Stat_PLDSilCU_State_Temperature_error +#define PLDSilCU_Module_Stat_PLDSilCU_State_Temperature_error (9) +#endif + +#ifndef PLDSilCU_Module_Stat_PLDSilCU_State_Channels_power_error +#define PLDSilCU_Module_Stat_PLDSilCU_State_Channels_power_error (10) +#endif + +#ifndef PLDSilCU_Module_Stat_PLDSilCU_State_Scenario_play_error +#define PLDSilCU_Module_Stat_PLDSilCU_State_Scenario_play_error (7) +#endif + +#ifndef PLDSilCU_Module_Stat_PLDSilCU_State_Launch_error +#define PLDSilCU_Module_Stat_PLDSilCU_State_Launch_error (6) +#endif + +#ifndef PLDSilCU_Module_Stat_PLDSilCU_State_Scenario_Data_is_recieved +#define PLDSilCU_Module_Stat_PLDSilCU_State_Scenario_Data_is_recieved (5) +#endif + +#ifndef PLDSilCU_Module_Stat_PLDSilCU_State_Configuration_is_going +#define PLDSilCU_Module_Stat_PLDSilCU_State_Configuration_is_going (4) +#endif + +#ifndef PLDSilCU_Module_Stat_PLDSilCU_State_Special_event_done +#define PLDSilCU_Module_Stat_PLDSilCU_State_Special_event_done (3) +#endif + +#ifndef PLDSilCU_Module_Stat_PLDSilCU_State_Scenario_have_done +#define PLDSilCU_Module_Stat_PLDSilCU_State_Scenario_have_done (2) +#endif + +#ifndef PLDSilCU_Module_Stat_PLDSilCU_State_Scenario_is_going +#define PLDSilCU_Module_Stat_PLDSilCU_State_Scenario_is_going (1) +#endif + +#ifndef PLDSilCU_Module_Stat_PLDSilCU_State_Ready +#define PLDSilCU_Module_Stat_PLDSilCU_State_Ready (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Module state: + // 0 - Module is ready for action + // 1 - Module has done a scenario + // 2 - Module made a special event + // 3 - Data is recieved + // 4 - Module start error + // 5 - Scenario play error + // 6 - Data error + // 7 - Temperature error + // 8 : "Scenario data message error" + // 9 : "Temperature error" + // 10 : "Channels power error" + // 7 : "Scenario play error" + // 6 : "Launch error" + // 5 : "Scenario Data is recieved" + // 4 : "Configuration is going" + // 3 : "Special event done" + // 2 : "Scenario have done" + // 1 : "Scenario is going" + // 0 : "Ready" + int8_t PLDSilCU_Module_Stat : 4; // [-] Bits= 4 + + // Temperature value + int8_t PLDSilCU_ModuleTemperature_Val : 7; // [-] Bits= 7 Unit:'�C' + + // Reserved + int8_t PLDSilCU_reserved1 : 5; // [-] Bits= 5 + + // Reserved + int8_t PLDSilCU_reserved2; // [-] Bits= 8 + + // Reserved + int8_t PLDSilCU_reserved3; // [-] Bits= 8 + + // Reserved + int8_t PLDSilCU_reserved4; // [-] Bits= 8 + + // Reserved + int8_t PLDSilCU_reserved5; // [-] Bits= 8 + + // Reserved + int8_t PLDSilCU_reserved6; // [-] Bits= 8 + + // Reserved + int8_t PLDSilCU_reserved7; // [-] Bits= 8 + +#else + + // Module state: + // 0 - Module is ready for action + // 1 - Module has done a scenario + // 2 - Module made a special event + // 3 - Data is recieved + // 4 - Module start error + // 5 - Scenario play error + // 6 - Data error + // 7 - Temperature error + // 8 : "Scenario data message error" + // 9 : "Temperature error" + // 10 : "Channels power error" + // 7 : "Scenario play error" + // 6 : "Launch error" + // 5 : "Scenario Data is recieved" + // 4 : "Configuration is going" + // 3 : "Special event done" + // 2 : "Scenario have done" + // 1 : "Scenario is going" + // 0 : "Ready" + int8_t PLDSilCU_Module_Stat; // [-] Bits= 4 + + // Temperature value + int8_t PLDSilCU_ModuleTemperature_Val; // [-] Bits= 7 Unit:'�C' + + // Reserved + int8_t PLDSilCU_reserved1; // [-] Bits= 5 + + // Reserved + int8_t PLDSilCU_reserved2; // [-] Bits= 8 + + // Reserved + int8_t PLDSilCU_reserved3; // [-] Bits= 8 + + // Reserved + int8_t PLDSilCU_reserved4; // [-] Bits= 8 + + // Reserved + int8_t PLDSilCU_reserved5; // [-] Bits= 8 + + // Reserved + int8_t PLDSilCU_reserved6; // [-] Bits= 8 + + // Reserved + int8_t PLDSilCU_reserved7; // [-] Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} PLDSilCU_State_t; + +// def @PRDSilCU_State CAN Message (1433 0x599) +#define PRDSilCU_State_IDE (0U) +#define PRDSilCU_State_DLC (8U) +#define PRDSilCU_State_CANID (0x599U) + +// Value tables for @PRDSilCU_Module_Stat signal + +#ifndef PRDSilCU_Module_Stat_PRDSilCU_State_Scenario_data_message_error +#define PRDSilCU_Module_Stat_PRDSilCU_State_Scenario_data_message_error (8) +#endif + +#ifndef PRDSilCU_Module_Stat_PRDSilCU_State_Temperature_error +#define PRDSilCU_Module_Stat_PRDSilCU_State_Temperature_error (9) +#endif + +#ifndef PRDSilCU_Module_Stat_PRDSilCU_State_Channels_power_error +#define PRDSilCU_Module_Stat_PRDSilCU_State_Channels_power_error (10) +#endif + +#ifndef PRDSilCU_Module_Stat_PRDSilCU_State_Scenario_play_error +#define PRDSilCU_Module_Stat_PRDSilCU_State_Scenario_play_error (7) +#endif + +#ifndef PRDSilCU_Module_Stat_PRDSilCU_State_Launch_error +#define PRDSilCU_Module_Stat_PRDSilCU_State_Launch_error (6) +#endif + +#ifndef PRDSilCU_Module_Stat_PRDSilCU_State_Scenario_Data_is_recieved +#define PRDSilCU_Module_Stat_PRDSilCU_State_Scenario_Data_is_recieved (5) +#endif + +#ifndef PRDSilCU_Module_Stat_PRDSilCU_State_Configuration_is_going +#define PRDSilCU_Module_Stat_PRDSilCU_State_Configuration_is_going (4) +#endif + +#ifndef PRDSilCU_Module_Stat_PRDSilCU_State_Special_event_done +#define PRDSilCU_Module_Stat_PRDSilCU_State_Special_event_done (3) +#endif + +#ifndef PRDSilCU_Module_Stat_PRDSilCU_State_Scenario_have_done +#define PRDSilCU_Module_Stat_PRDSilCU_State_Scenario_have_done (2) +#endif + +#ifndef PRDSilCU_Module_Stat_PRDSilCU_State_Scenario_is_going +#define PRDSilCU_Module_Stat_PRDSilCU_State_Scenario_is_going (1) +#endif + +#ifndef PRDSilCU_Module_Stat_PRDSilCU_State_Ready +#define PRDSilCU_Module_Stat_PRDSilCU_State_Ready (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Module state: + // 0 - Module is ready for action + // 1 - Module has done a scenario + // 2 - Module made a special event + // 3 - Data is recieved + // 4 - Module start error + // 5 - Scenario play error + // 6 - Data error + // 7 - Temperature error + // 8 : "Scenario data message error" + // 9 : "Temperature error" + // 10 : "Channels power error" + // 7 : "Scenario play error" + // 6 : "Launch error" + // 5 : "Scenario Data is recieved" + // 4 : "Configuration is going" + // 3 : "Special event done" + // 2 : "Scenario have done" + // 1 : "Scenario is going" + // 0 : "Ready" + int8_t PRDSilCU_Module_Stat : 4; // [-] Bits= 4 + + // Temperature value + int8_t PRDSilCU_ModuleTemperature_Val : 7; // [-] Bits= 7 Unit:'�C' + + // Reserved + int8_t PRDSilCU_reserved1 : 5; // [-] Bits= 5 + + // Reserved + int8_t PRDSilCU_reserved2; // [-] Bits= 8 + + // Reserved + int8_t PRDSilCU_reserved3; // [-] Bits= 8 + + // Reserved + int8_t PRDSilCU_reserved4; // [-] Bits= 8 + + // Reserved + int8_t PRDSilCU_reserved5; // [-] Bits= 8 + + // Reserved + int8_t PRDSilCU_reserved6; // [-] Bits= 8 + + // Reserved + int8_t PRDSilCU_reserved7; // [-] Bits= 8 + +#else + + // Module state: + // 0 - Module is ready for action + // 1 - Module has done a scenario + // 2 - Module made a special event + // 3 - Data is recieved + // 4 - Module start error + // 5 - Scenario play error + // 6 - Data error + // 7 - Temperature error + // 8 : "Scenario data message error" + // 9 : "Temperature error" + // 10 : "Channels power error" + // 7 : "Scenario play error" + // 6 : "Launch error" + // 5 : "Scenario Data is recieved" + // 4 : "Configuration is going" + // 3 : "Special event done" + // 2 : "Scenario have done" + // 1 : "Scenario is going" + // 0 : "Ready" + int8_t PRDSilCU_Module_Stat; // [-] Bits= 4 + + // Temperature value + int8_t PRDSilCU_ModuleTemperature_Val; // [-] Bits= 7 Unit:'�C' + + // Reserved + int8_t PRDSilCU_reserved1; // [-] Bits= 5 + + // Reserved + int8_t PRDSilCU_reserved2; // [-] Bits= 8 + + // Reserved + int8_t PRDSilCU_reserved3; // [-] Bits= 8 + + // Reserved + int8_t PRDSilCU_reserved4; // [-] Bits= 8 + + // Reserved + int8_t PRDSilCU_reserved5; // [-] Bits= 8 + + // Reserved + int8_t PRDSilCU_reserved6; // [-] Bits= 8 + + // Reserved + int8_t PRDSilCU_reserved7; // [-] Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} PRDSilCU_State_t; + +// def @FLDSilCU_State CAN Message (1434 0x59a) +#define FLDSilCU_State_IDE (0U) +#define FLDSilCU_State_DLC (8U) +#define FLDSilCU_State_CANID (0x59aU) + +// Value tables for @FLDSilCU_Module_Stat signal + +#ifndef FLDSilCU_Module_Stat_FLDSilCU_State_Scenario_data_message_error +#define FLDSilCU_Module_Stat_FLDSilCU_State_Scenario_data_message_error (8) +#endif + +#ifndef FLDSilCU_Module_Stat_FLDSilCU_State_Temperature_error +#define FLDSilCU_Module_Stat_FLDSilCU_State_Temperature_error (9) +#endif + +#ifndef FLDSilCU_Module_Stat_FLDSilCU_State_Channels_power_error +#define FLDSilCU_Module_Stat_FLDSilCU_State_Channels_power_error (10) +#endif + +#ifndef FLDSilCU_Module_Stat_FLDSilCU_State_Scenario_play_error +#define FLDSilCU_Module_Stat_FLDSilCU_State_Scenario_play_error (7) +#endif + +#ifndef FLDSilCU_Module_Stat_FLDSilCU_State_Launch_error +#define FLDSilCU_Module_Stat_FLDSilCU_State_Launch_error (6) +#endif + +#ifndef FLDSilCU_Module_Stat_FLDSilCU_State_Scenario_Data_is_recieved +#define FLDSilCU_Module_Stat_FLDSilCU_State_Scenario_Data_is_recieved (5) +#endif + +#ifndef FLDSilCU_Module_Stat_FLDSilCU_State_Configuration_is_going +#define FLDSilCU_Module_Stat_FLDSilCU_State_Configuration_is_going (4) +#endif + +#ifndef FLDSilCU_Module_Stat_FLDSilCU_State_Special_event_done +#define FLDSilCU_Module_Stat_FLDSilCU_State_Special_event_done (3) +#endif + +#ifndef FLDSilCU_Module_Stat_FLDSilCU_State_Scenario_have_done +#define FLDSilCU_Module_Stat_FLDSilCU_State_Scenario_have_done (2) +#endif + +#ifndef FLDSilCU_Module_Stat_FLDSilCU_State_Scenario_is_going +#define FLDSilCU_Module_Stat_FLDSilCU_State_Scenario_is_going (1) +#endif + +#ifndef FLDSilCU_Module_Stat_FLDSilCU_State_Ready +#define FLDSilCU_Module_Stat_FLDSilCU_State_Ready (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Module state: + // 0 - Module is ready for action + // 1 - Module has done a scenario + // 2 - Module made a special event + // 3 - Data is recieved + // 4 - Module start error + // 5 - Scenario play error + // 6 - Data error + // 7 - Temperature error + // 8 : "Scenario data message error" + // 9 : "Temperature error" + // 10 : "Channels power error" + // 7 : "Scenario play error" + // 6 : "Launch error" + // 5 : "Scenario Data is recieved" + // 4 : "Configuration is going" + // 3 : "Special event done" + // 2 : "Scenario have done" + // 1 : "Scenario is going" + // 0 : "Ready" + int8_t FLDSilCU_Module_Stat : 4; // [-] Bits= 4 + + // Temperature value + int8_t FLDSilCU_ModuleTemperature_Val : 7; // [-] Bits= 7 Unit:'�C' + + // Reserved + int8_t FLDSilCU_reserved1 : 5; // [-] Bits= 5 + + // Reserved + int8_t FLDSilCU_reserved2; // [-] Bits= 8 + + // Reserved + int8_t FLDSilCU_reserved3; // [-] Bits= 8 + + // Reserved + int8_t FLDSilCU_reserved4; // [-] Bits= 8 + + // Reserved + int8_t FLDSilCU_reserved5; // [-] Bits= 8 + + // Reserved + int8_t FLDSilCU_reserved6; // [-] Bits= 8 + + // Reserved + int8_t FLDSilCU_reserved7; // [-] Bits= 8 + +#else + + // Module state: + // 0 - Module is ready for action + // 1 - Module has done a scenario + // 2 - Module made a special event + // 3 - Data is recieved + // 4 - Module start error + // 5 - Scenario play error + // 6 - Data error + // 7 - Temperature error + // 8 : "Scenario data message error" + // 9 : "Temperature error" + // 10 : "Channels power error" + // 7 : "Scenario play error" + // 6 : "Launch error" + // 5 : "Scenario Data is recieved" + // 4 : "Configuration is going" + // 3 : "Special event done" + // 2 : "Scenario have done" + // 1 : "Scenario is going" + // 0 : "Ready" + int8_t FLDSilCU_Module_Stat; // [-] Bits= 4 + + // Temperature value + int8_t FLDSilCU_ModuleTemperature_Val; // [-] Bits= 7 Unit:'�C' + + // Reserved + int8_t FLDSilCU_reserved1; // [-] Bits= 5 + + // Reserved + int8_t FLDSilCU_reserved2; // [-] Bits= 8 + + // Reserved + int8_t FLDSilCU_reserved3; // [-] Bits= 8 + + // Reserved + int8_t FLDSilCU_reserved4; // [-] Bits= 8 + + // Reserved + int8_t FLDSilCU_reserved5; // [-] Bits= 8 + + // Reserved + int8_t FLDSilCU_reserved6; // [-] Bits= 8 + + // Reserved + int8_t FLDSilCU_reserved7; // [-] Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} FLDSilCU_State_t; + +// def @FRDSilCU_State CAN Message (1435 0x59b) +#define FRDSilCU_State_IDE (0U) +#define FRDSilCU_State_DLC (8U) +#define FRDSilCU_State_CANID (0x59bU) + +// Value tables for @FRDSilCU_Module_Stat signal + +#ifndef FRDSilCU_Module_Stat_FRDSilCU_State_Scenario_data_message_error +#define FRDSilCU_Module_Stat_FRDSilCU_State_Scenario_data_message_error (8) +#endif + +#ifndef FRDSilCU_Module_Stat_FRDSilCU_State_Temperature_error +#define FRDSilCU_Module_Stat_FRDSilCU_State_Temperature_error (9) +#endif + +#ifndef FRDSilCU_Module_Stat_FRDSilCU_State_Channels_power_error +#define FRDSilCU_Module_Stat_FRDSilCU_State_Channels_power_error (10) +#endif + +#ifndef FRDSilCU_Module_Stat_FRDSilCU_State_Scenario_play_error +#define FRDSilCU_Module_Stat_FRDSilCU_State_Scenario_play_error (7) +#endif + +#ifndef FRDSilCU_Module_Stat_FRDSilCU_State_Launch_error +#define FRDSilCU_Module_Stat_FRDSilCU_State_Launch_error (6) +#endif + +#ifndef FRDSilCU_Module_Stat_FRDSilCU_State_Scenario_Data_is_recieved +#define FRDSilCU_Module_Stat_FRDSilCU_State_Scenario_Data_is_recieved (5) +#endif + +#ifndef FRDSilCU_Module_Stat_FRDSilCU_State_Configuration_is_going +#define FRDSilCU_Module_Stat_FRDSilCU_State_Configuration_is_going (4) +#endif + +#ifndef FRDSilCU_Module_Stat_FRDSilCU_State_Special_event_done +#define FRDSilCU_Module_Stat_FRDSilCU_State_Special_event_done (3) +#endif + +#ifndef FRDSilCU_Module_Stat_FRDSilCU_State_Scenario_have_done +#define FRDSilCU_Module_Stat_FRDSilCU_State_Scenario_have_done (2) +#endif + +#ifndef FRDSilCU_Module_Stat_FRDSilCU_State_Scenario_is_going +#define FRDSilCU_Module_Stat_FRDSilCU_State_Scenario_is_going (1) +#endif + +#ifndef FRDSilCU_Module_Stat_FRDSilCU_State_Ready +#define FRDSilCU_Module_Stat_FRDSilCU_State_Ready (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Module state: + // 0 - Module is ready for action + // 1 - Module has done a scenario + // 2 - Module made a special event + // 3 - Data is recieved + // 4 - Module start error + // 5 - Scenario play error + // 6 - Data error + // 7 - Temperature error + // 8 : "Scenario data message error" + // 9 : "Temperature error" + // 10 : "Channels power error" + // 7 : "Scenario play error" + // 6 : "Launch error" + // 5 : "Scenario Data is recieved" + // 4 : "Configuration is going" + // 3 : "Special event done" + // 2 : "Scenario have done" + // 1 : "Scenario is going" + // 0 : "Ready" + int8_t FRDSilCU_Module_Stat : 4; // [-] Bits= 4 + + // Temperature value + int8_t FRDSilCU_ModuleTemperature_Val : 7; // [-] Bits= 7 Unit:'�C' + + // Reserved + int8_t FRDSilCU_reserved1 : 5; // [-] Bits= 5 + + // Reserved + int8_t FRDSilCU_reserved2; // [-] Bits= 8 + + // Reserved + int8_t FRDSilCU_reserved3; // [-] Bits= 8 + + // Reserved + int8_t FRDSilCU_reserved4; // [-] Bits= 8 + + // Reserved + int8_t FRDSilCU_reserved5; // [-] Bits= 8 + + // Reserved + int8_t FRDSilCU_reserved6; // [-] Bits= 8 + + // Reserved + int8_t FRDSilCU_reserved7; // [-] Bits= 8 + +#else + + // Module state: + // 0 - Module is ready for action + // 1 - Module has done a scenario + // 2 - Module made a special event + // 3 - Data is recieved + // 4 - Module start error + // 5 - Scenario play error + // 6 - Data error + // 7 - Temperature error + // 8 : "Scenario data message error" + // 9 : "Temperature error" + // 10 : "Channels power error" + // 7 : "Scenario play error" + // 6 : "Launch error" + // 5 : "Scenario Data is recieved" + // 4 : "Configuration is going" + // 3 : "Special event done" + // 2 : "Scenario have done" + // 1 : "Scenario is going" + // 0 : "Ready" + int8_t FRDSilCU_Module_Stat; // [-] Bits= 4 + + // Temperature value + int8_t FRDSilCU_ModuleTemperature_Val; // [-] Bits= 7 Unit:'�C' + + // Reserved + int8_t FRDSilCU_reserved1; // [-] Bits= 5 + + // Reserved + int8_t FRDSilCU_reserved2; // [-] Bits= 8 + + // Reserved + int8_t FRDSilCU_reserved3; // [-] Bits= 8 + + // Reserved + int8_t FRDSilCU_reserved4; // [-] Bits= 8 + + // Reserved + int8_t FRDSilCU_reserved5; // [-] Bits= 8 + + // Reserved + int8_t FRDSilCU_reserved6; // [-] Bits= 8 + + // Reserved + int8_t FRDSilCU_reserved7; // [-] Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} FRDSilCU_State_t; + +// This is a message for not used signals, created by Vector CANdb++ DBC OLE DB Provider. +// def @RLDSilCU_State CAN Message (1436 0x59c) +#define RLDSilCU_State_IDE (0U) +#define RLDSilCU_State_DLC (8U) +#define RLDSilCU_State_CANID (0x59cU) + +// Value tables for @RLDSilCU_Module_Stat signal + +#ifndef RLDSilCU_Module_Stat_RLDSilCU_State_Scenario_data_message_error +#define RLDSilCU_Module_Stat_RLDSilCU_State_Scenario_data_message_error (8) +#endif + +#ifndef RLDSilCU_Module_Stat_RLDSilCU_State_Scenario_play_error +#define RLDSilCU_Module_Stat_RLDSilCU_State_Scenario_play_error (7) +#endif + +#ifndef RLDSilCU_Module_Stat_RLDSilCU_State_Launch_error +#define RLDSilCU_Module_Stat_RLDSilCU_State_Launch_error (6) +#endif + +#ifndef RLDSilCU_Module_Stat_RLDSilCU_State_Scenario_Data_is_recieved +#define RLDSilCU_Module_Stat_RLDSilCU_State_Scenario_Data_is_recieved (5) +#endif + +#ifndef RLDSilCU_Module_Stat_RLDSilCU_State_Configuration_is_going +#define RLDSilCU_Module_Stat_RLDSilCU_State_Configuration_is_going (4) +#endif + +#ifndef RLDSilCU_Module_Stat_RLDSilCU_State_Special_event_done +#define RLDSilCU_Module_Stat_RLDSilCU_State_Special_event_done (3) +#endif + +#ifndef RLDSilCU_Module_Stat_RLDSilCU_State_Scenario_have_done +#define RLDSilCU_Module_Stat_RLDSilCU_State_Scenario_have_done (2) +#endif + +#ifndef RLDSilCU_Module_Stat_RLDSilCU_State_Scenario_is_going +#define RLDSilCU_Module_Stat_RLDSilCU_State_Scenario_is_going (1) +#endif + +#ifndef RLDSilCU_Module_Stat_RLDSilCU_State_Ready +#define RLDSilCU_Module_Stat_RLDSilCU_State_Ready (0) +#endif + +#ifndef RLDSilCU_Module_Stat_RLDSilCU_State_Temperature_error +#define RLDSilCU_Module_Stat_RLDSilCU_State_Temperature_error (9) +#endif + +#ifndef RLDSilCU_Module_Stat_RLDSilCU_State_Channels_power_error +#define RLDSilCU_Module_Stat_RLDSilCU_State_Channels_power_error (10) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Module state: + // 0 - Module is ready for action + // 1 - Module has done a scenario + // 2 - Module made a special event + // 3 - Data is recieved + // 4 - Module start error + // 5 - Scenario play error + // 6 - Data error + // 7 - Temperature error + // 8 : "Scenario data message error" + // 7 : "Scenario play error" + // 6 : "Launch error" + // 5 : "Scenario Data is recieved" + // 4 : "Configuration is going" + // 3 : "Special event done" + // 2 : "Scenario have done" + // 1 : "Scenario is going" + // 0 : "Ready" + // 9 : "Temperature error" + // 10 : "Channels power error" + int8_t RLDSilCU_Module_Stat : 4; // [-] Bits= 4 + + // Temperature value + int8_t RLDSilCU_ModuleTemperature_Val : 7; // [-] Bits= 7 Unit:'�C' + + // Reserved + int8_t RLDSilCU_reserved1 : 5; // [-] Bits= 5 + + // Reserved + int8_t RLDSilCU_reserved2; // [-] Bits= 8 + + // Reserved + int8_t RLDSilCU_reserved3; // [-] Bits= 8 + + // Reserved + int8_t RLDSilCU_reserved4; // [-] Bits= 8 + + // Reserved + int8_t RLDSilCU_reserved5; // [-] Bits= 8 + + // Reserved + int8_t RLDSilCU_reserved6; // [-] Bits= 8 + + // Reserved + int8_t RLDSilCU_reserved7; // [-] Bits= 8 + +#else + + // Module state: + // 0 - Module is ready for action + // 1 - Module has done a scenario + // 2 - Module made a special event + // 3 - Data is recieved + // 4 - Module start error + // 5 - Scenario play error + // 6 - Data error + // 7 - Temperature error + // 8 : "Scenario data message error" + // 7 : "Scenario play error" + // 6 : "Launch error" + // 5 : "Scenario Data is recieved" + // 4 : "Configuration is going" + // 3 : "Special event done" + // 2 : "Scenario have done" + // 1 : "Scenario is going" + // 0 : "Ready" + // 9 : "Temperature error" + // 10 : "Channels power error" + int8_t RLDSilCU_Module_Stat; // [-] Bits= 4 + + // Temperature value + int8_t RLDSilCU_ModuleTemperature_Val; // [-] Bits= 7 Unit:'�C' + + // Reserved + int8_t RLDSilCU_reserved1; // [-] Bits= 5 + + // Reserved + int8_t RLDSilCU_reserved2; // [-] Bits= 8 + + // Reserved + int8_t RLDSilCU_reserved3; // [-] Bits= 8 + + // Reserved + int8_t RLDSilCU_reserved4; // [-] Bits= 8 + + // Reserved + int8_t RLDSilCU_reserved5; // [-] Bits= 8 + + // Reserved + int8_t RLDSilCU_reserved6; // [-] Bits= 8 + + // Reserved + int8_t RLDSilCU_reserved7; // [-] Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} RLDSilCU_State_t; + +// def @RRDSilCU_State CAN Message (1437 0x59d) +#define RRDSilCU_State_IDE (0U) +#define RRDSilCU_State_DLC (8U) +#define RRDSilCU_State_CANID (0x59dU) + +// Value tables for @RRDSilCU_Module_Stat signal + +#ifndef RRDSilCU_Module_Stat_RRDSilCU_State_Scenario_data_message_error +#define RRDSilCU_Module_Stat_RRDSilCU_State_Scenario_data_message_error (8) +#endif + +#ifndef RRDSilCU_Module_Stat_RRDSilCU_State_Temperature_error +#define RRDSilCU_Module_Stat_RRDSilCU_State_Temperature_error (9) +#endif + +#ifndef RRDSilCU_Module_Stat_RRDSilCU_State_Channels_power_error +#define RRDSilCU_Module_Stat_RRDSilCU_State_Channels_power_error (10) +#endif + +#ifndef RRDSilCU_Module_Stat_RRDSilCU_State_Scenario_play_error +#define RRDSilCU_Module_Stat_RRDSilCU_State_Scenario_play_error (7) +#endif + +#ifndef RRDSilCU_Module_Stat_RRDSilCU_State_Launch_error +#define RRDSilCU_Module_Stat_RRDSilCU_State_Launch_error (6) +#endif + +#ifndef RRDSilCU_Module_Stat_RRDSilCU_State_Scenario_Data_is_recieved +#define RRDSilCU_Module_Stat_RRDSilCU_State_Scenario_Data_is_recieved (5) +#endif + +#ifndef RRDSilCU_Module_Stat_RRDSilCU_State_Configuration_is_going +#define RRDSilCU_Module_Stat_RRDSilCU_State_Configuration_is_going (4) +#endif + +#ifndef RRDSilCU_Module_Stat_RRDSilCU_State_Special_event_done +#define RRDSilCU_Module_Stat_RRDSilCU_State_Special_event_done (3) +#endif + +#ifndef RRDSilCU_Module_Stat_RRDSilCU_State_Scenario_have_done +#define RRDSilCU_Module_Stat_RRDSilCU_State_Scenario_have_done (2) +#endif + +#ifndef RRDSilCU_Module_Stat_RRDSilCU_State_Scenario_is_going +#define RRDSilCU_Module_Stat_RRDSilCU_State_Scenario_is_going (1) +#endif + +#ifndef RRDSilCU_Module_Stat_RRDSilCU_State_Ready +#define RRDSilCU_Module_Stat_RRDSilCU_State_Ready (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Module state: + // 0 - Module is ready for action + // 1 - Module has done a scenario + // 2 - Module made a special event + // 3 - Data is recieved + // 4 - Module start error + // 5 - Scenario play error + // 6 - Data error + // 7 - Temperature error + // 8 : "Scenario data message error" + // 9 : "Temperature error" + // 10 : "Channels power error" + // 7 : "Scenario play error" + // 6 : "Launch error" + // 5 : "Scenario Data is recieved" + // 4 : "Configuration is going" + // 3 : "Special event done" + // 2 : "Scenario have done" + // 1 : "Scenario is going" + // 0 : "Ready" + int8_t RRDSilCU_Module_Stat : 4; // [-] Bits= 4 + + // Temperature value + int8_t RRDSilCU_ModuleTemperature_Val : 7; // [-] Bits= 7 Unit:'�C' + + // Reserved + int8_t RRDSilCU_reserved1 : 5; // [-] Bits= 5 + + // Reserved + int8_t RRDSilCU_reserved2; // [-] Bits= 8 + + // Reserved + int8_t RRDSilCU_reserved3; // [-] Bits= 8 + + // Reserved + int8_t RRDSilCU_reserved4; // [-] Bits= 8 + + // Reserved + int8_t RRDSilCU_reserved5; // [-] Bits= 8 + + // Reserved + int8_t RRDSilCU_reserved6; // [-] Bits= 8 + + // Reserved + int8_t RRDSilCU_reserved7; // [-] Bits= 8 + +#else + + // Module state: + // 0 - Module is ready for action + // 1 - Module has done a scenario + // 2 - Module made a special event + // 3 - Data is recieved + // 4 - Module start error + // 5 - Scenario play error + // 6 - Data error + // 7 - Temperature error + // 8 : "Scenario data message error" + // 9 : "Temperature error" + // 10 : "Channels power error" + // 7 : "Scenario play error" + // 6 : "Launch error" + // 5 : "Scenario Data is recieved" + // 4 : "Configuration is going" + // 3 : "Special event done" + // 2 : "Scenario have done" + // 1 : "Scenario is going" + // 0 : "Ready" + int8_t RRDSilCU_Module_Stat; // [-] Bits= 4 + + // Temperature value + int8_t RRDSilCU_ModuleTemperature_Val; // [-] Bits= 7 Unit:'�C' + + // Reserved + int8_t RRDSilCU_reserved1; // [-] Bits= 5 + + // Reserved + int8_t RRDSilCU_reserved2; // [-] Bits= 8 + + // Reserved + int8_t RRDSilCU_reserved3; // [-] Bits= 8 + + // Reserved + int8_t RRDSilCU_reserved4; // [-] Bits= 8 + + // Reserved + int8_t RRDSilCU_reserved5; // [-] Bits= 8 + + // Reserved + int8_t RRDSilCU_reserved6; // [-] Bits= 8 + + // Reserved + int8_t RRDSilCU_reserved7; // [-] Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} RRDSilCU_State_t; + +// def @FIU_CCU1 CAN Message (1441 0x5a1) +#define FIU_CCU1_IDE (0U) +#define FIU_CCU1_DLC (8U) +#define FIU_CCU1_CANID (0x5a1U) +// signal: @FIU_TargetTempFL_Val_ro +#define CANDB_FIU_TargetTempFL_Val_ro_CovFactor (0.5) +#define CANDB_FIU_TargetTempFL_Val_ro_toS(x) ( (uint8_t) (((x) - (15.5)) / (0.5)) ) +#define CANDB_FIU_TargetTempFL_Val_ro_fromS(x) ( (((x) * (0.5)) + (15.5)) ) + +// Value tables for @FIU_FootTempCorFL_Req signal + +#ifndef FIU_FootTempCorFL_Req_FIU_CCU1_No_change +#define FIU_FootTempCorFL_Req_FIU_CCU1_No_change (0) +#endif + +#ifndef FIU_FootTempCorFL_Req_FIU_CCU1__step +#define FIU_FootTempCorFL_Req_FIU_CCU1__step (1) +#endif + +#ifndef FIU_FootTempCorFL_Req_FIU_CCU1__step +#define FIU_FootTempCorFL_Req_FIU_CCU1__step (2) +#endif + +#ifndef FIU_FootTempCorFL_Req_FIU_CCU1__step +#define FIU_FootTempCorFL_Req_FIU_CCU1__step (3) +#endif + +#ifndef FIU_FootTempCorFL_Req_FIU_CCU1_ +#define FIU_FootTempCorFL_Req_FIU_CCU1_ (4) +#endif + +#ifndef FIU_FootTempCorFL_Req_FIU_CCU1__step +#define FIU_FootTempCorFL_Req_FIU_CCU1__step (5) +#endif + +#ifndef FIU_FootTempCorFL_Req_FIU_CCU1__step +#define FIU_FootTempCorFL_Req_FIU_CCU1__step (6) +#endif + +#ifndef FIU_FootTempCorFL_Req_FIU_CCU1__step +#define FIU_FootTempCorFL_Req_FIU_CCU1__step (7) +#endif + +// signal: @FIU_TargetTempFR_Val_ro +#define CANDB_FIU_TargetTempFR_Val_ro_CovFactor (0.5) +#define CANDB_FIU_TargetTempFR_Val_ro_toS(x) ( (uint8_t) (((x) - (15.5)) / (0.5)) ) +#define CANDB_FIU_TargetTempFR_Val_ro_fromS(x) ( (((x) * (0.5)) + (15.5)) ) + +// Value tables for @FIU_FootTempCorFR_Req signal + +#ifndef FIU_FootTempCorFR_Req_FIU_CCU1_No_change +#define FIU_FootTempCorFR_Req_FIU_CCU1_No_change (0) +#endif + +#ifndef FIU_FootTempCorFR_Req_FIU_CCU1__step +#define FIU_FootTempCorFR_Req_FIU_CCU1__step (1) +#endif + +#ifndef FIU_FootTempCorFR_Req_FIU_CCU1__step +#define FIU_FootTempCorFR_Req_FIU_CCU1__step (2) +#endif + +#ifndef FIU_FootTempCorFR_Req_FIU_CCU1__step +#define FIU_FootTempCorFR_Req_FIU_CCU1__step (3) +#endif + +#ifndef FIU_FootTempCorFR_Req_FIU_CCU1_ +#define FIU_FootTempCorFR_Req_FIU_CCU1_ (4) +#endif + +#ifndef FIU_FootTempCorFR_Req_FIU_CCU1__step +#define FIU_FootTempCorFR_Req_FIU_CCU1__step (5) +#endif + +#ifndef FIU_FootTempCorFR_Req_FIU_CCU1__step +#define FIU_FootTempCorFR_Req_FIU_CCU1__step (6) +#endif + +#ifndef FIU_FootTempCorFR_Req_FIU_CCU1__step +#define FIU_FootTempCorFR_Req_FIU_CCU1__step (7) +#endif + + +// Value tables for @FIU_CCmodeFL_Req signal + +#ifndef FIU_CCmodeFL_Req_FIU_CCU1_No_change +#define FIU_CCmodeFL_Req_FIU_CCU1_No_change (0) +#endif + +#ifndef FIU_CCmodeFL_Req_FIU_CCU1_Manual_mode_requested +#define FIU_CCmodeFL_Req_FIU_CCU1_Manual_mode_requested (1) +#endif + +#ifndef FIU_CCmodeFL_Req_FIU_CCU1_Auto_mode_requested +#define FIU_CCmodeFL_Req_FIU_CCU1_Auto_mode_requested (2) +#endif + + +// Value tables for @FIU_AirDirectionFL_Def_Req signal + +#ifndef FIU_AirDirectionFL_Def_Req_FIU_CCU1_No_change +#define FIU_AirDirectionFL_Def_Req_FIU_CCU1_No_change (0) +#endif + +#ifndef FIU_AirDirectionFL_Def_Req_FIU_CCU1_Active +#define FIU_AirDirectionFL_Def_Req_FIU_CCU1_Active (1) +#endif + +#ifndef FIU_AirDirectionFL_Def_Req_FIU_CCU1_Inactive +#define FIU_AirDirectionFL_Def_Req_FIU_CCU1_Inactive (2) +#endif + + +// Value tables for @FIU_AirDirectionFL_Face_Req signal + +#ifndef FIU_AirDirectionFL_Face_Req_FIU_CCU1_No_change +#define FIU_AirDirectionFL_Face_Req_FIU_CCU1_No_change (0) +#endif + +#ifndef FIU_AirDirectionFL_Face_Req_FIU_CCU1_Active +#define FIU_AirDirectionFL_Face_Req_FIU_CCU1_Active (1) +#endif + +#ifndef FIU_AirDirectionFL_Face_Req_FIU_CCU1_Inactive +#define FIU_AirDirectionFL_Face_Req_FIU_CCU1_Inactive (2) +#endif + + +// Value tables for @FIU_AirDirectionFL_Foot_Req signal + +#ifndef FIU_AirDirectionFL_Foot_Req_FIU_CCU1_No_change +#define FIU_AirDirectionFL_Foot_Req_FIU_CCU1_No_change (0) +#endif + +#ifndef FIU_AirDirectionFL_Foot_Req_FIU_CCU1_Active +#define FIU_AirDirectionFL_Foot_Req_FIU_CCU1_Active (1) +#endif + +#ifndef FIU_AirDirectionFL_Foot_Req_FIU_CCU1_Inactive +#define FIU_AirDirectionFL_Foot_Req_FIU_CCU1_Inactive (2) +#endif + + +// Value tables for @FIU_CCmodeFR_Req signal + +#ifndef FIU_CCmodeFR_Req_FIU_CCU1_No_change +#define FIU_CCmodeFR_Req_FIU_CCU1_No_change (0) +#endif + +#ifndef FIU_CCmodeFR_Req_FIU_CCU1_Manual_mode_requested +#define FIU_CCmodeFR_Req_FIU_CCU1_Manual_mode_requested (1) +#endif + +#ifndef FIU_CCmodeFR_Req_FIU_CCU1_Auto_mode_requested +#define FIU_CCmodeFR_Req_FIU_CCU1_Auto_mode_requested (2) +#endif + + +// Value tables for @FIU_AirDirectionFR_Def_Req signal + +#ifndef FIU_AirDirectionFR_Def_Req_FIU_CCU1_No_change +#define FIU_AirDirectionFR_Def_Req_FIU_CCU1_No_change (0) +#endif + +#ifndef FIU_AirDirectionFR_Def_Req_FIU_CCU1_Active +#define FIU_AirDirectionFR_Def_Req_FIU_CCU1_Active (1) +#endif + +#ifndef FIU_AirDirectionFR_Def_Req_FIU_CCU1_Inactive +#define FIU_AirDirectionFR_Def_Req_FIU_CCU1_Inactive (2) +#endif + + +// Value tables for @FIU_AirDirectionFR_Face_Req signal + +#ifndef FIU_AirDirectionFR_Face_Req_FIU_CCU1_No_change +#define FIU_AirDirectionFR_Face_Req_FIU_CCU1_No_change (0) +#endif + +#ifndef FIU_AirDirectionFR_Face_Req_FIU_CCU1_Active +#define FIU_AirDirectionFR_Face_Req_FIU_CCU1_Active (1) +#endif + +#ifndef FIU_AirDirectionFR_Face_Req_FIU_CCU1_Inactive +#define FIU_AirDirectionFR_Face_Req_FIU_CCU1_Inactive (2) +#endif + + +// Value tables for @FIU_AirDirectionFR_Foot_Req signal + +#ifndef FIU_AirDirectionFR_Foot_Req_FIU_CCU1_No_change +#define FIU_AirDirectionFR_Foot_Req_FIU_CCU1_No_change (0) +#endif + +#ifndef FIU_AirDirectionFR_Foot_Req_FIU_CCU1_Active +#define FIU_AirDirectionFR_Foot_Req_FIU_CCU1_Active (1) +#endif + +#ifndef FIU_AirDirectionFR_Foot_Req_FIU_CCU1_Inactive +#define FIU_AirDirectionFR_Foot_Req_FIU_CCU1_Inactive (2) +#endif + + +// Value tables for @FIU_BlowerSpeedFL_Req signal + +#ifndef FIU_BlowerSpeedFL_Req_FIU_CCU1_No_change +#define FIU_BlowerSpeedFL_Req_FIU_CCU1_No_change (0) +#endif + +#ifndef FIU_BlowerSpeedFL_Req_FIU_CCU1__step +#define FIU_BlowerSpeedFL_Req_FIU_CCU1__step (1) +#endif + +#ifndef FIU_BlowerSpeedFL_Req_FIU_CCU1__step +#define FIU_BlowerSpeedFL_Req_FIU_CCU1__step (2) +#endif + +#ifndef FIU_BlowerSpeedFL_Req_FIU_CCU1__step +#define FIU_BlowerSpeedFL_Req_FIU_CCU1__step (3) +#endif + +#ifndef FIU_BlowerSpeedFL_Req_FIU_CCU1__step +#define FIU_BlowerSpeedFL_Req_FIU_CCU1__step (4) +#endif + +#ifndef FIU_BlowerSpeedFL_Req_FIU_CCU1__step +#define FIU_BlowerSpeedFL_Req_FIU_CCU1__step (5) +#endif + +#ifndef FIU_BlowerSpeedFL_Req_FIU_CCU1__step +#define FIU_BlowerSpeedFL_Req_FIU_CCU1__step (6) +#endif + +#ifndef FIU_BlowerSpeedFL_Req_FIU_CCU1__step +#define FIU_BlowerSpeedFL_Req_FIU_CCU1__step (7) +#endif + +#ifndef FIU_BlowerSpeedFL_Req_FIU_CCU1_Blower_off +#define FIU_BlowerSpeedFL_Req_FIU_CCU1_Blower_off (8) +#endif + + +// Value tables for @FIU_BlowerSpeedFR_Req signal + +#ifndef FIU_BlowerSpeedFR_Req_FIU_CCU1_No_change +#define FIU_BlowerSpeedFR_Req_FIU_CCU1_No_change (0) +#endif + +#ifndef FIU_BlowerSpeedFR_Req_FIU_CCU1__step +#define FIU_BlowerSpeedFR_Req_FIU_CCU1__step (1) +#endif + +#ifndef FIU_BlowerSpeedFR_Req_FIU_CCU1__step +#define FIU_BlowerSpeedFR_Req_FIU_CCU1__step (2) +#endif + +#ifndef FIU_BlowerSpeedFR_Req_FIU_CCU1__step +#define FIU_BlowerSpeedFR_Req_FIU_CCU1__step (3) +#endif + +#ifndef FIU_BlowerSpeedFR_Req_FIU_CCU1__step +#define FIU_BlowerSpeedFR_Req_FIU_CCU1__step (4) +#endif + +#ifndef FIU_BlowerSpeedFR_Req_FIU_CCU1__step +#define FIU_BlowerSpeedFR_Req_FIU_CCU1__step (5) +#endif + +#ifndef FIU_BlowerSpeedFR_Req_FIU_CCU1__step +#define FIU_BlowerSpeedFR_Req_FIU_CCU1__step (6) +#endif + +#ifndef FIU_BlowerSpeedFR_Req_FIU_CCU1__step +#define FIU_BlowerSpeedFR_Req_FIU_CCU1__step (7) +#endif + +#ifndef FIU_BlowerSpeedFR_Req_FIU_CCU1_Blower_off +#define FIU_BlowerSpeedFR_Req_FIU_CCU1_Blower_off (8) +#endif + + +// Value tables for @FIU_CCautoModeFL_Req signal + +#ifndef FIU_CCautoModeFL_Req_FIU_CCU1_No_change +#define FIU_CCautoModeFL_Req_FIU_CCU1_No_change (0) +#endif + +#ifndef FIU_CCautoModeFL_Req_FIU_CCU1_Auto_mode_1_requested +#define FIU_CCautoModeFL_Req_FIU_CCU1_Auto_mode_1_requested (1) +#endif + +#ifndef FIU_CCautoModeFL_Req_FIU_CCU1_Auto_mode_2_requested +#define FIU_CCautoModeFL_Req_FIU_CCU1_Auto_mode_2_requested (2) +#endif + +#ifndef FIU_CCautoModeFL_Req_FIU_CCU1_Auto_mode_3_requested +#define FIU_CCautoModeFL_Req_FIU_CCU1_Auto_mode_3_requested (3) +#endif + +#ifndef FIU_CCautoModeFL_Req_FIU_CCU1_Auto_mode_4_requested +#define FIU_CCautoModeFL_Req_FIU_CCU1_Auto_mode_4_requested (4) +#endif + +#ifndef FIU_CCautoModeFL_Req_FIU_CCU1_Auto_mode_5_requested +#define FIU_CCautoModeFL_Req_FIU_CCU1_Auto_mode_5_requested (5) +#endif + + +// Value tables for @FIU_CCautoModeFR_Req signal + +#ifndef FIU_CCautoModeFR_Req_FIU_CCU1_No_change +#define FIU_CCautoModeFR_Req_FIU_CCU1_No_change (0) +#endif + +#ifndef FIU_CCautoModeFR_Req_FIU_CCU1_Auto_mode_1_requested +#define FIU_CCautoModeFR_Req_FIU_CCU1_Auto_mode_1_requested (1) +#endif + +#ifndef FIU_CCautoModeFR_Req_FIU_CCU1_Auto_mode_2_requested +#define FIU_CCautoModeFR_Req_FIU_CCU1_Auto_mode_2_requested (2) +#endif + +#ifndef FIU_CCautoModeFR_Req_FIU_CCU1_Auto_mode_3_requested +#define FIU_CCautoModeFR_Req_FIU_CCU1_Auto_mode_3_requested (3) +#endif + +#ifndef FIU_CCautoModeFR_Req_FIU_CCU1_Auto_mode_4_requested +#define FIU_CCautoModeFR_Req_FIU_CCU1_Auto_mode_4_requested (4) +#endif + +#ifndef FIU_CCautoModeFR_Req_FIU_CCU1_Auto_mode_5_requested +#define FIU_CCautoModeFR_Req_FIU_CCU1_Auto_mode_5_requested (5) +#endif + + +// Value tables for @FIU_Recirculation_Req signal + +#ifndef FIU_Recirculation_Req_FIU_CCU1_No_change +#define FIU_Recirculation_Req_FIU_CCU1_No_change (0) +#endif + +#ifndef FIU_Recirculation_Req_FIU_CCU1_Recirculation_mode_Rec_on +#define FIU_Recirculation_Req_FIU_CCU1_Recirculation_mode_Rec_on (1) +#endif + +#ifndef FIU_Recirculation_Req_FIU_CCU1_Fresh_air_mode_Rec_off +#define FIU_Recirculation_Req_FIU_CCU1_Fresh_air_mode_Rec_off (2) +#endif + +#ifndef FIU_Recirculation_Req_FIU_CCU1_Auto_recirculation_mode +#define FIU_Recirculation_Req_FIU_CCU1_Auto_recirculation_mode (3) +#endif + + +// Value tables for @FIU_DeflectorSwDL_Req signal + +#ifndef FIU_DeflectorSwDL_Req_FIU_CCU1_No_LED +#define FIU_DeflectorSwDL_Req_FIU_CCU1_No_LED (4) +#endif + +#ifndef FIU_DeflectorSwDL_Req_FIU_CCU1_LED_3_step +#define FIU_DeflectorSwDL_Req_FIU_CCU1_LED_3_step (3) +#endif + +#ifndef FIU_DeflectorSwDL_Req_FIU_CCU1_LED_2_step +#define FIU_DeflectorSwDL_Req_FIU_CCU1_LED_2_step (2) +#endif + +#ifndef FIU_DeflectorSwDL_Req_FIU_CCU1_LED_1_step +#define FIU_DeflectorSwDL_Req_FIU_CCU1_LED_1_step (1) +#endif + +#ifndef FIU_DeflectorSwDL_Req_FIU_CCU1_No_change +#define FIU_DeflectorSwDL_Req_FIU_CCU1_No_change (0) +#endif + + +// Value tables for @FIU_DeflectorSwDR_Req signal + +#ifndef FIU_DeflectorSwDR_Req_FIU_CCU1_No_LED +#define FIU_DeflectorSwDR_Req_FIU_CCU1_No_LED (4) +#endif + +#ifndef FIU_DeflectorSwDR_Req_FIU_CCU1_LED_3_step +#define FIU_DeflectorSwDR_Req_FIU_CCU1_LED_3_step (3) +#endif + +#ifndef FIU_DeflectorSwDR_Req_FIU_CCU1_LED_2_step +#define FIU_DeflectorSwDR_Req_FIU_CCU1_LED_2_step (2) +#endif + +#ifndef FIU_DeflectorSwDR_Req_FIU_CCU1_LED_1_step +#define FIU_DeflectorSwDR_Req_FIU_CCU1_LED_1_step (1) +#endif + +#ifndef FIU_DeflectorSwDR_Req_FIU_CCU1_No_change +#define FIU_DeflectorSwDR_Req_FIU_CCU1_No_change (0) +#endif + + +// Value tables for @FIU_ACfrontOFF_Req signal + +#ifndef FIU_ACfrontOFF_Req_FIU_CCU1_No_change +#define FIU_ACfrontOFF_Req_FIU_CCU1_No_change (0) +#endif + +#ifndef FIU_ACfrontOFF_Req_FIU_CCU1_AC_front_ON +#define FIU_ACfrontOFF_Req_FIU_CCU1_AC_front_ON (1) +#endif + +#ifndef FIU_ACfrontOFF_Req_FIU_CCU1_AC_front_OFF +#define FIU_ACfrontOFF_Req_FIU_CCU1_AC_front_OFF (2) +#endif + + +// Value tables for @FIU_DeflectorSwFPL_Req signal + +#ifndef FIU_DeflectorSwFPL_Req_FIU_CCU1_No_LED +#define FIU_DeflectorSwFPL_Req_FIU_CCU1_No_LED (4) +#endif + +#ifndef FIU_DeflectorSwFPL_Req_FIU_CCU1_LED_3_step +#define FIU_DeflectorSwFPL_Req_FIU_CCU1_LED_3_step (3) +#endif + +#ifndef FIU_DeflectorSwFPL_Req_FIU_CCU1_LED_2_step +#define FIU_DeflectorSwFPL_Req_FIU_CCU1_LED_2_step (2) +#endif + +#ifndef FIU_DeflectorSwFPL_Req_FIU_CCU1_LED_1_step +#define FIU_DeflectorSwFPL_Req_FIU_CCU1_LED_1_step (1) +#endif + +#ifndef FIU_DeflectorSwFPL_Req_FIU_CCU1_No_change +#define FIU_DeflectorSwFPL_Req_FIU_CCU1_No_change (0) +#endif + + +// Value tables for @FIU_DeflectorSwFPR_Req signal + +#ifndef FIU_DeflectorSwFPR_Req_FIU_CCU1_No_LED +#define FIU_DeflectorSwFPR_Req_FIU_CCU1_No_LED (4) +#endif + +#ifndef FIU_DeflectorSwFPR_Req_FIU_CCU1_LED_3_step +#define FIU_DeflectorSwFPR_Req_FIU_CCU1_LED_3_step (3) +#endif + +#ifndef FIU_DeflectorSwFPR_Req_FIU_CCU1_LED_2_step +#define FIU_DeflectorSwFPR_Req_FIU_CCU1_LED_2_step (2) +#endif + +#ifndef FIU_DeflectorSwFPR_Req_FIU_CCU1_LED_1_step +#define FIU_DeflectorSwFPR_Req_FIU_CCU1_LED_1_step (1) +#endif + +#ifndef FIU_DeflectorSwFPR_Req_FIU_CCU1_No_change +#define FIU_DeflectorSwFPR_Req_FIU_CCU1_No_change (0) +#endif + + +// Value tables for @FIU_FrontZoneSync_Req signal + +#ifndef FIU_FrontZoneSync_Req_FIU_CCU1_No_change +#define FIU_FrontZoneSync_Req_FIU_CCU1_No_change (0) +#endif + +#ifndef FIU_FrontZoneSync_Req_FIU_CCU1_Sync_front +#define FIU_FrontZoneSync_Req_FIU_CCU1_Sync_front (1) +#endif + +#ifndef FIU_FrontZoneSync_Req_FIU_CCU1_Sync_all +#define FIU_FrontZoneSync_Req_FIU_CCU1_Sync_all (2) +#endif + +#ifndef FIU_FrontZoneSync_Req_FIU_CCU1_Sync_off +#define FIU_FrontZoneSync_Req_FIU_CCU1_Sync_off (3) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Target temperature for front left zone value + uint8_t FIU_TargetTempFL_Val_ro : 5; // Bits= 5 Offset= 15.5 Factor= 0.5 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t FIU_TargetTempFL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Footwell temperature correction for front left zone request + // 0 : "No change" + // 1 : "-3 step" + // 2 : "-2 step" + // 3 : "-1 step" + // 4 : "0" + // 5 : "+1 step" + // 6 : "+2 step" + // 7 : "+3 step" + uint8_t FIU_FootTempCorFL_Req : 3; // Bits= 3 + + // Target temperature for front right zone value + uint8_t FIU_TargetTempFR_Val_ro : 5; // Bits= 5 Offset= 15.5 Factor= 0.5 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t FIU_TargetTempFR_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Footwell temperature correction for front right zone request + // 0 : "No change" + // 1 : "-3 step" + // 2 : "-2 step" + // 3 : "-1 step" + // 4 : "0" + // 5 : "+1 step" + // 6 : "+2 step" + // 7 : "+3 step" + uint8_t FIU_FootTempCorFR_Req : 3; // Bits= 3 + + // Climate control mode for front left zone request + // 0 : "No change" + // 1 : "Manual mode requested" + // 2 : "Auto mode requested" + uint8_t FIU_CCmodeFL_Req : 2; // Bits= 2 + + // Airflow direction mode for front left zone request + // 0 : "No change" + // 1 : "Active" + // 2 : "Inactive" + uint8_t FIU_AirDirectionFL_Def_Req : 2; // Bits= 2 + + // Airflow direction mode for front left zone request + // 0 : "No change" + // 1 : "Active" + // 2 : "Inactive" + uint8_t FIU_AirDirectionFL_Face_Req : 2; // Bits= 2 + + // Airflow direction mode for front left zone request + // 0 : "No change" + // 1 : "Active" + // 2 : "Inactive" + uint8_t FIU_AirDirectionFL_Foot_Req : 2; // Bits= 2 + + // Climate control mode for front right zone request + // 0 : "No change" + // 1 : "Manual mode requested" + // 2 : "Auto mode requested" + uint8_t FIU_CCmodeFR_Req : 2; // Bits= 2 + + // Airflow direction mode for front right zone request + // 0 : "No change" + // 1 : "Active" + // 2 : "Inactive" + uint8_t FIU_AirDirectionFR_Def_Req : 2; // Bits= 2 + + // Airflow direction mode for front right zone request + // 0 : "No change" + // 1 : "Active" + // 2 : "Inactive" + uint8_t FIU_AirDirectionFR_Face_Req : 2; // Bits= 2 + + // Airflow direction mode for front right zone request + // 0 : "No change" + // 1 : "Active" + // 2 : "Inactive" + uint8_t FIU_AirDirectionFR_Foot_Req : 2; // Bits= 2 + + // Blower speed for front left zone request + // 0 : "No change" + // 1 : "1 step" + // 2 : "2 step" + // 3 : "3 step" + // 4 : "4 step" + // 5 : "5 step" + // 6 : "6 step" + // 7 : "7 step" + // 8 : "Blower off" + uint8_t FIU_BlowerSpeedFL_Req : 4; // Bits= 4 + + // Blower speed for front right zone request + // 0 : "No change" + // 1 : "1 step" + // 2 : "2 step" + // 3 : "3 step" + // 4 : "4 step" + // 5 : "5 step" + // 6 : "6 step" + // 7 : "7 step" + // 8 : "Blower off" + uint8_t FIU_BlowerSpeedFR_Req : 4; // Bits= 4 + + // Climate control auto mode for front left zone request + // 0 : "No change" + // 1 : "Auto mode 1 requested" + // 2 : "Auto mode 2 requested" + // 3 : "Auto mode 3 requested" + // 4 : "Auto mode 4 requested" + // 5 : "Auto mode 5 requested" + uint8_t FIU_CCautoModeFL_Req : 3; // Bits= 3 + + // Climate control auto mode for front right zone request + // 0 : "No change" + // 1 : "Auto mode 1 requested" + // 2 : "Auto mode 2 requested" + // 3 : "Auto mode 3 requested" + // 4 : "Auto mode 4 requested" + // 5 : "Auto mode 5 requested" + uint8_t FIU_CCautoModeFR_Req : 3; // Bits= 3 + + // Recirculation mode requested + // 0 : "No change" + // 1 : "Recirculation mode (Rec on)" + // 2 : "Fresh air mode (Rec off)" + // 3 : "Auto recirculation mode" + uint8_t FIU_Recirculation_Req : 2; // Bits= 2 + + // Deflector driver left request + // 4 : "No LED" + // 3 : "LED 3 step" + // 2 : "LED 2 step" + // 1 : "LED 1 step" + // 0 : "No change" + uint8_t FIU_DeflectorSwDL_Req : 3; // Bits= 3 + + // Deflector driver right request + // 4 : "No LED" + // 3 : "LED 3 step" + // 2 : "LED 2 step" + // 1 : "LED 1 step" + // 0 : "No change" + uint8_t FIU_DeflectorSwDR_Req : 3; // Bits= 3 + + // Air conditioner OFF front request + // 0 : "No change" + // 1 : "AC front ON" + // 2 : "AC front OFF" + uint8_t FIU_ACfrontOFF_Req : 2; // Bits= 2 + + // Deflector front passenger left request + // 4 : "No LED" + // 3 : "LED 3 step" + // 2 : "LED 2 step" + // 1 : "LED 1 step" + // 0 : "No change" + uint8_t FIU_DeflectorSwFPL_Req : 3; // Bits= 3 + + // Deflector front passenger right request + // 4 : "No LED" + // 3 : "LED 3 step" + // 2 : "LED 2 step" + // 1 : "LED 1 step" + // 0 : "No change" + uint8_t FIU_DeflectorSwFPR_Req : 3; // Bits= 3 + + // Front climate zones synchronization on/off request + // 0 : "No change" + // 1 : "Sync front" + // 2 : "Sync all" + // 3 : "Sync off" + uint8_t FIU_FrontZoneSync_Req : 2; // Bits= 2 + +#else + + // Target temperature for front left zone value + uint8_t FIU_TargetTempFL_Val_ro; // Bits= 5 Offset= 15.5 Factor= 0.5 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t FIU_TargetTempFL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Footwell temperature correction for front left zone request + // 0 : "No change" + // 1 : "-3 step" + // 2 : "-2 step" + // 3 : "-1 step" + // 4 : "0" + // 5 : "+1 step" + // 6 : "+2 step" + // 7 : "+3 step" + uint8_t FIU_FootTempCorFL_Req; // Bits= 3 + + // Target temperature for front right zone value + uint8_t FIU_TargetTempFR_Val_ro; // Bits= 5 Offset= 15.5 Factor= 0.5 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t FIU_TargetTempFR_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Footwell temperature correction for front right zone request + // 0 : "No change" + // 1 : "-3 step" + // 2 : "-2 step" + // 3 : "-1 step" + // 4 : "0" + // 5 : "+1 step" + // 6 : "+2 step" + // 7 : "+3 step" + uint8_t FIU_FootTempCorFR_Req; // Bits= 3 + + // Climate control mode for front left zone request + // 0 : "No change" + // 1 : "Manual mode requested" + // 2 : "Auto mode requested" + uint8_t FIU_CCmodeFL_Req; // Bits= 2 + + // Airflow direction mode for front left zone request + // 0 : "No change" + // 1 : "Active" + // 2 : "Inactive" + uint8_t FIU_AirDirectionFL_Def_Req; // Bits= 2 + + // Airflow direction mode for front left zone request + // 0 : "No change" + // 1 : "Active" + // 2 : "Inactive" + uint8_t FIU_AirDirectionFL_Face_Req; // Bits= 2 + + // Airflow direction mode for front left zone request + // 0 : "No change" + // 1 : "Active" + // 2 : "Inactive" + uint8_t FIU_AirDirectionFL_Foot_Req; // Bits= 2 + + // Climate control mode for front right zone request + // 0 : "No change" + // 1 : "Manual mode requested" + // 2 : "Auto mode requested" + uint8_t FIU_CCmodeFR_Req; // Bits= 2 + + // Airflow direction mode for front right zone request + // 0 : "No change" + // 1 : "Active" + // 2 : "Inactive" + uint8_t FIU_AirDirectionFR_Def_Req; // Bits= 2 + + // Airflow direction mode for front right zone request + // 0 : "No change" + // 1 : "Active" + // 2 : "Inactive" + uint8_t FIU_AirDirectionFR_Face_Req; // Bits= 2 + + // Airflow direction mode for front right zone request + // 0 : "No change" + // 1 : "Active" + // 2 : "Inactive" + uint8_t FIU_AirDirectionFR_Foot_Req; // Bits= 2 + + // Blower speed for front left zone request + // 0 : "No change" + // 1 : "1 step" + // 2 : "2 step" + // 3 : "3 step" + // 4 : "4 step" + // 5 : "5 step" + // 6 : "6 step" + // 7 : "7 step" + // 8 : "Blower off" + uint8_t FIU_BlowerSpeedFL_Req; // Bits= 4 + + // Blower speed for front right zone request + // 0 : "No change" + // 1 : "1 step" + // 2 : "2 step" + // 3 : "3 step" + // 4 : "4 step" + // 5 : "5 step" + // 6 : "6 step" + // 7 : "7 step" + // 8 : "Blower off" + uint8_t FIU_BlowerSpeedFR_Req; // Bits= 4 + + // Climate control auto mode for front left zone request + // 0 : "No change" + // 1 : "Auto mode 1 requested" + // 2 : "Auto mode 2 requested" + // 3 : "Auto mode 3 requested" + // 4 : "Auto mode 4 requested" + // 5 : "Auto mode 5 requested" + uint8_t FIU_CCautoModeFL_Req; // Bits= 3 + + // Climate control auto mode for front right zone request + // 0 : "No change" + // 1 : "Auto mode 1 requested" + // 2 : "Auto mode 2 requested" + // 3 : "Auto mode 3 requested" + // 4 : "Auto mode 4 requested" + // 5 : "Auto mode 5 requested" + uint8_t FIU_CCautoModeFR_Req; // Bits= 3 + + // Recirculation mode requested + // 0 : "No change" + // 1 : "Recirculation mode (Rec on)" + // 2 : "Fresh air mode (Rec off)" + // 3 : "Auto recirculation mode" + uint8_t FIU_Recirculation_Req; // Bits= 2 + + // Deflector driver left request + // 4 : "No LED" + // 3 : "LED 3 step" + // 2 : "LED 2 step" + // 1 : "LED 1 step" + // 0 : "No change" + uint8_t FIU_DeflectorSwDL_Req; // Bits= 3 + + // Deflector driver right request + // 4 : "No LED" + // 3 : "LED 3 step" + // 2 : "LED 2 step" + // 1 : "LED 1 step" + // 0 : "No change" + uint8_t FIU_DeflectorSwDR_Req; // Bits= 3 + + // Air conditioner OFF front request + // 0 : "No change" + // 1 : "AC front ON" + // 2 : "AC front OFF" + uint8_t FIU_ACfrontOFF_Req; // Bits= 2 + + // Deflector front passenger left request + // 4 : "No LED" + // 3 : "LED 3 step" + // 2 : "LED 2 step" + // 1 : "LED 1 step" + // 0 : "No change" + uint8_t FIU_DeflectorSwFPL_Req; // Bits= 3 + + // Deflector front passenger right request + // 4 : "No LED" + // 3 : "LED 3 step" + // 2 : "LED 2 step" + // 1 : "LED 1 step" + // 0 : "No change" + uint8_t FIU_DeflectorSwFPR_Req; // Bits= 3 + + // Front climate zones synchronization on/off request + // 0 : "No change" + // 1 : "Sync front" + // 2 : "Sync all" + // 3 : "Sync off" + uint8_t FIU_FrontZoneSync_Req; // Bits= 2 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} FIU_CCU1_t; + +// def @FIU_CCU2 CAN Message (1442 0x5a2) +#define FIU_CCU2_IDE (0U) +#define FIU_CCU2_DLC (8U) +#define FIU_CCU2_CANID (0x5a2U) +// signal: @FIU_TargetTempRL_Val_ro +#define CANDB_FIU_TargetTempRL_Val_ro_CovFactor (0.5) +#define CANDB_FIU_TargetTempRL_Val_ro_toS(x) ( (uint8_t) (((x) - (15.5)) / (0.5)) ) +#define CANDB_FIU_TargetTempRL_Val_ro_fromS(x) ( (((x) * (0.5)) + (15.5)) ) + +// Value tables for @FIU_FootTempCorRL_Req signal + +#ifndef FIU_FootTempCorRL_Req_FIU_CCU2_No_change +#define FIU_FootTempCorRL_Req_FIU_CCU2_No_change (0) +#endif + +#ifndef FIU_FootTempCorRL_Req_FIU_CCU2__step +#define FIU_FootTempCorRL_Req_FIU_CCU2__step (1) +#endif + +#ifndef FIU_FootTempCorRL_Req_FIU_CCU2__step +#define FIU_FootTempCorRL_Req_FIU_CCU2__step (2) +#endif + +#ifndef FIU_FootTempCorRL_Req_FIU_CCU2__step +#define FIU_FootTempCorRL_Req_FIU_CCU2__step (3) +#endif + +#ifndef FIU_FootTempCorRL_Req_FIU_CCU2_ +#define FIU_FootTempCorRL_Req_FIU_CCU2_ (4) +#endif + +#ifndef FIU_FootTempCorRL_Req_FIU_CCU2__step +#define FIU_FootTempCorRL_Req_FIU_CCU2__step (5) +#endif + +#ifndef FIU_FootTempCorRL_Req_FIU_CCU2__step +#define FIU_FootTempCorRL_Req_FIU_CCU2__step (6) +#endif + +#ifndef FIU_FootTempCorRL_Req_FIU_CCU2__step +#define FIU_FootTempCorRL_Req_FIU_CCU2__step (7) +#endif + +// signal: @FIU_TargetTempRR_Val_ro +#define CANDB_FIU_TargetTempRR_Val_ro_CovFactor (0.5) +#define CANDB_FIU_TargetTempRR_Val_ro_toS(x) ( (uint8_t) (((x) - (15.5)) / (0.5)) ) +#define CANDB_FIU_TargetTempRR_Val_ro_fromS(x) ( (((x) * (0.5)) + (15.5)) ) + +// Value tables for @FIU_FootTempCorRR_Req signal + +#ifndef FIU_FootTempCorRR_Req_FIU_CCU2_No_change +#define FIU_FootTempCorRR_Req_FIU_CCU2_No_change (0) +#endif + +#ifndef FIU_FootTempCorRR_Req_FIU_CCU2__step +#define FIU_FootTempCorRR_Req_FIU_CCU2__step (1) +#endif + +#ifndef FIU_FootTempCorRR_Req_FIU_CCU2__step +#define FIU_FootTempCorRR_Req_FIU_CCU2__step (2) +#endif + +#ifndef FIU_FootTempCorRR_Req_FIU_CCU2__step +#define FIU_FootTempCorRR_Req_FIU_CCU2__step (3) +#endif + +#ifndef FIU_FootTempCorRR_Req_FIU_CCU2_ +#define FIU_FootTempCorRR_Req_FIU_CCU2_ (4) +#endif + +#ifndef FIU_FootTempCorRR_Req_FIU_CCU2__step +#define FIU_FootTempCorRR_Req_FIU_CCU2__step (5) +#endif + +#ifndef FIU_FootTempCorRR_Req_FIU_CCU2__step +#define FIU_FootTempCorRR_Req_FIU_CCU2__step (6) +#endif + +#ifndef FIU_FootTempCorRR_Req_FIU_CCU2__step +#define FIU_FootTempCorRR_Req_FIU_CCU2__step (7) +#endif + + +// Value tables for @FIU_CCmodeRL_Req signal + +#ifndef FIU_CCmodeRL_Req_FIU_CCU2_No_change +#define FIU_CCmodeRL_Req_FIU_CCU2_No_change (0) +#endif + +#ifndef FIU_CCmodeRL_Req_FIU_CCU2_Manual_mode_requested +#define FIU_CCmodeRL_Req_FIU_CCU2_Manual_mode_requested (1) +#endif + +#ifndef FIU_CCmodeRL_Req_FIU_CCU2_Auto_mode_requested +#define FIU_CCmodeRL_Req_FIU_CCU2_Auto_mode_requested (2) +#endif + + +// Value tables for @FIU_AirDirectionRL_Def_Req signal + +#ifndef FIU_AirDirectionRL_Def_Req_FIU_CCU2_No_change +#define FIU_AirDirectionRL_Def_Req_FIU_CCU2_No_change (0) +#endif + +#ifndef FIU_AirDirectionRL_Def_Req_FIU_CCU2_Active +#define FIU_AirDirectionRL_Def_Req_FIU_CCU2_Active (1) +#endif + +#ifndef FIU_AirDirectionRL_Def_Req_FIU_CCU2_Inactive +#define FIU_AirDirectionRL_Def_Req_FIU_CCU2_Inactive (2) +#endif + + +// Value tables for @FIU_AirDirectionRL_Face_Req signal + +#ifndef FIU_AirDirectionRL_Face_Req_FIU_CCU2_No_change +#define FIU_AirDirectionRL_Face_Req_FIU_CCU2_No_change (0) +#endif + +#ifndef FIU_AirDirectionRL_Face_Req_FIU_CCU2_Active +#define FIU_AirDirectionRL_Face_Req_FIU_CCU2_Active (1) +#endif + +#ifndef FIU_AirDirectionRL_Face_Req_FIU_CCU2_Inactive +#define FIU_AirDirectionRL_Face_Req_FIU_CCU2_Inactive (2) +#endif + + +// Value tables for @FIU_AirDirectionRL_Foot_Req signal + +#ifndef FIU_AirDirectionRL_Foot_Req_FIU_CCU2_No_change +#define FIU_AirDirectionRL_Foot_Req_FIU_CCU2_No_change (0) +#endif + +#ifndef FIU_AirDirectionRL_Foot_Req_FIU_CCU2_Active +#define FIU_AirDirectionRL_Foot_Req_FIU_CCU2_Active (1) +#endif + +#ifndef FIU_AirDirectionRL_Foot_Req_FIU_CCU2_Inactive +#define FIU_AirDirectionRL_Foot_Req_FIU_CCU2_Inactive (2) +#endif + + +// Value tables for @FIU_CCmodeRR_Req signal + +#ifndef FIU_CCmodeRR_Req_FIU_CCU2_No_change +#define FIU_CCmodeRR_Req_FIU_CCU2_No_change (0) +#endif + +#ifndef FIU_CCmodeRR_Req_FIU_CCU2_Manual_mode_requested +#define FIU_CCmodeRR_Req_FIU_CCU2_Manual_mode_requested (1) +#endif + +#ifndef FIU_CCmodeRR_Req_FIU_CCU2_Auto_mode_requested +#define FIU_CCmodeRR_Req_FIU_CCU2_Auto_mode_requested (2) +#endif + + +// Value tables for @FIU_AirDirectionRR_Def_Req signal + +#ifndef FIU_AirDirectionRR_Def_Req_FIU_CCU2_No_change +#define FIU_AirDirectionRR_Def_Req_FIU_CCU2_No_change (0) +#endif + +#ifndef FIU_AirDirectionRR_Def_Req_FIU_CCU2_Active +#define FIU_AirDirectionRR_Def_Req_FIU_CCU2_Active (1) +#endif + +#ifndef FIU_AirDirectionRR_Def_Req_FIU_CCU2_Inactive +#define FIU_AirDirectionRR_Def_Req_FIU_CCU2_Inactive (2) +#endif + + +// Value tables for @FIU_AirDirectionRR_Face_Req signal + +#ifndef FIU_AirDirectionRR_Face_Req_FIU_CCU2_No_change +#define FIU_AirDirectionRR_Face_Req_FIU_CCU2_No_change (0) +#endif + +#ifndef FIU_AirDirectionRR_Face_Req_FIU_CCU2_Active +#define FIU_AirDirectionRR_Face_Req_FIU_CCU2_Active (1) +#endif + +#ifndef FIU_AirDirectionRR_Face_Req_FIU_CCU2_Inactive +#define FIU_AirDirectionRR_Face_Req_FIU_CCU2_Inactive (2) +#endif + + +// Value tables for @FIU_AirDirectionRR_Foot_Req signal + +#ifndef FIU_AirDirectionRR_Foot_Req_FIU_CCU2_No_change +#define FIU_AirDirectionRR_Foot_Req_FIU_CCU2_No_change (0) +#endif + +#ifndef FIU_AirDirectionRR_Foot_Req_FIU_CCU2_Active +#define FIU_AirDirectionRR_Foot_Req_FIU_CCU2_Active (1) +#endif + +#ifndef FIU_AirDirectionRR_Foot_Req_FIU_CCU2_Inactive +#define FIU_AirDirectionRR_Foot_Req_FIU_CCU2_Inactive (2) +#endif + + +// Value tables for @FIU_BlowerSpeedRL_Req signal + +#ifndef FIU_BlowerSpeedRL_Req_FIU_CCU2_No_change +#define FIU_BlowerSpeedRL_Req_FIU_CCU2_No_change (0) +#endif + +#ifndef FIU_BlowerSpeedRL_Req_FIU_CCU2__step +#define FIU_BlowerSpeedRL_Req_FIU_CCU2__step (1) +#endif + +#ifndef FIU_BlowerSpeedRL_Req_FIU_CCU2__step +#define FIU_BlowerSpeedRL_Req_FIU_CCU2__step (2) +#endif + +#ifndef FIU_BlowerSpeedRL_Req_FIU_CCU2__step +#define FIU_BlowerSpeedRL_Req_FIU_CCU2__step (3) +#endif + +#ifndef FIU_BlowerSpeedRL_Req_FIU_CCU2__step +#define FIU_BlowerSpeedRL_Req_FIU_CCU2__step (4) +#endif + +#ifndef FIU_BlowerSpeedRL_Req_FIU_CCU2__step +#define FIU_BlowerSpeedRL_Req_FIU_CCU2__step (5) +#endif + +#ifndef FIU_BlowerSpeedRL_Req_FIU_CCU2__step +#define FIU_BlowerSpeedRL_Req_FIU_CCU2__step (6) +#endif + +#ifndef FIU_BlowerSpeedRL_Req_FIU_CCU2__step +#define FIU_BlowerSpeedRL_Req_FIU_CCU2__step (7) +#endif + +#ifndef FIU_BlowerSpeedRL_Req_FIU_CCU2_Blower_off +#define FIU_BlowerSpeedRL_Req_FIU_CCU2_Blower_off (8) +#endif + + +// Value tables for @FIU_BlowerSpeedRR_Req signal + +#ifndef FIU_BlowerSpeedRR_Req_FIU_CCU2_No_change +#define FIU_BlowerSpeedRR_Req_FIU_CCU2_No_change (0) +#endif + +#ifndef FIU_BlowerSpeedRR_Req_FIU_CCU2__step +#define FIU_BlowerSpeedRR_Req_FIU_CCU2__step (1) +#endif + +#ifndef FIU_BlowerSpeedRR_Req_FIU_CCU2__step +#define FIU_BlowerSpeedRR_Req_FIU_CCU2__step (2) +#endif + +#ifndef FIU_BlowerSpeedRR_Req_FIU_CCU2__step +#define FIU_BlowerSpeedRR_Req_FIU_CCU2__step (3) +#endif + +#ifndef FIU_BlowerSpeedRR_Req_FIU_CCU2__step +#define FIU_BlowerSpeedRR_Req_FIU_CCU2__step (4) +#endif + +#ifndef FIU_BlowerSpeedRR_Req_FIU_CCU2__step +#define FIU_BlowerSpeedRR_Req_FIU_CCU2__step (5) +#endif + +#ifndef FIU_BlowerSpeedRR_Req_FIU_CCU2__step +#define FIU_BlowerSpeedRR_Req_FIU_CCU2__step (6) +#endif + +#ifndef FIU_BlowerSpeedRR_Req_FIU_CCU2__step +#define FIU_BlowerSpeedRR_Req_FIU_CCU2__step (7) +#endif + +#ifndef FIU_BlowerSpeedRR_Req_FIU_CCU2_Blower_off +#define FIU_BlowerSpeedRR_Req_FIU_CCU2_Blower_off (8) +#endif + + +// Value tables for @FIU_CCautoModeRL_Req signal + +#ifndef FIU_CCautoModeRL_Req_FIU_CCU2_No_change +#define FIU_CCautoModeRL_Req_FIU_CCU2_No_change (0) +#endif + +#ifndef FIU_CCautoModeRL_Req_FIU_CCU2_Auto_mode_1_requested +#define FIU_CCautoModeRL_Req_FIU_CCU2_Auto_mode_1_requested (1) +#endif + +#ifndef FIU_CCautoModeRL_Req_FIU_CCU2_Auto_mode_2_requested +#define FIU_CCautoModeRL_Req_FIU_CCU2_Auto_mode_2_requested (2) +#endif + +#ifndef FIU_CCautoModeRL_Req_FIU_CCU2_Auto_mode_3_requested +#define FIU_CCautoModeRL_Req_FIU_CCU2_Auto_mode_3_requested (3) +#endif + +#ifndef FIU_CCautoModeRL_Req_FIU_CCU2_Auto_mode_4_requested +#define FIU_CCautoModeRL_Req_FIU_CCU2_Auto_mode_4_requested (4) +#endif + +#ifndef FIU_CCautoModeRL_Req_FIU_CCU2_Auto_mode_5_requested +#define FIU_CCautoModeRL_Req_FIU_CCU2_Auto_mode_5_requested (5) +#endif + + +// Value tables for @FIU_CCautoModeRR_Req signal + +#ifndef FIU_CCautoModeRR_Req_FIU_CCU2_No_change +#define FIU_CCautoModeRR_Req_FIU_CCU2_No_change (0) +#endif + +#ifndef FIU_CCautoModeRR_Req_FIU_CCU2_Auto_mode_1_requested +#define FIU_CCautoModeRR_Req_FIU_CCU2_Auto_mode_1_requested (1) +#endif + +#ifndef FIU_CCautoModeRR_Req_FIU_CCU2_Auto_mode_2_requested +#define FIU_CCautoModeRR_Req_FIU_CCU2_Auto_mode_2_requested (2) +#endif + +#ifndef FIU_CCautoModeRR_Req_FIU_CCU2_Auto_mode_3_requested +#define FIU_CCautoModeRR_Req_FIU_CCU2_Auto_mode_3_requested (3) +#endif + +#ifndef FIU_CCautoModeRR_Req_FIU_CCU2_Auto_mode_4_requested +#define FIU_CCautoModeRR_Req_FIU_CCU2_Auto_mode_4_requested (4) +#endif + +#ifndef FIU_CCautoModeRR_Req_FIU_CCU2_Auto_mode_5_requested +#define FIU_CCautoModeRR_Req_FIU_CCU2_Auto_mode_5_requested (5) +#endif + + +// Value tables for @FIU_DeflectorSwRLB_Req signal + +#ifndef FIU_DeflectorSwRLB_Req_FIU_CCU2_No_LED +#define FIU_DeflectorSwRLB_Req_FIU_CCU2_No_LED (4) +#endif + +#ifndef FIU_DeflectorSwRLB_Req_FIU_CCU2_LED_3_step +#define FIU_DeflectorSwRLB_Req_FIU_CCU2_LED_3_step (3) +#endif + +#ifndef FIU_DeflectorSwRLB_Req_FIU_CCU2_LED_2_step +#define FIU_DeflectorSwRLB_Req_FIU_CCU2_LED_2_step (2) +#endif + +#ifndef FIU_DeflectorSwRLB_Req_FIU_CCU2_LED_1_step +#define FIU_DeflectorSwRLB_Req_FIU_CCU2_LED_1_step (1) +#endif + +#ifndef FIU_DeflectorSwRLB_Req_FIU_CCU2_No_change +#define FIU_DeflectorSwRLB_Req_FIU_CCU2_No_change (0) +#endif + + +// Value tables for @FIU_DeflectorSwFCL_Req signal + +#ifndef FIU_DeflectorSwFCL_Req_FIU_CCU2_No_LED +#define FIU_DeflectorSwFCL_Req_FIU_CCU2_No_LED (4) +#endif + +#ifndef FIU_DeflectorSwFCL_Req_FIU_CCU2_LED_3_step +#define FIU_DeflectorSwFCL_Req_FIU_CCU2_LED_3_step (3) +#endif + +#ifndef FIU_DeflectorSwFCL_Req_FIU_CCU2_LED_2_step +#define FIU_DeflectorSwFCL_Req_FIU_CCU2_LED_2_step (2) +#endif + +#ifndef FIU_DeflectorSwFCL_Req_FIU_CCU2_LED_1_step +#define FIU_DeflectorSwFCL_Req_FIU_CCU2_LED_1_step (1) +#endif + +#ifndef FIU_DeflectorSwFCL_Req_FIU_CCU2_No_change +#define FIU_DeflectorSwFCL_Req_FIU_CCU2_No_change (0) +#endif + + +// Value tables for @FIU_ACrearOFF_Req signal + +#ifndef FIU_ACrearOFF_Req_FIU_CCU2_No_change +#define FIU_ACrearOFF_Req_FIU_CCU2_No_change (0) +#endif + +#ifndef FIU_ACrearOFF_Req_FIU_CCU2_AC_front_ON +#define FIU_ACrearOFF_Req_FIU_CCU2_AC_front_ON (1) +#endif + +#ifndef FIU_ACrearOFF_Req_FIU_CCU2_AC_front_OFF +#define FIU_ACrearOFF_Req_FIU_CCU2_AC_front_OFF (2) +#endif + + +// Value tables for @FIU_DeflectorSwFCR_Req signal + +#ifndef FIU_DeflectorSwFCR_Req_FIU_CCU2_No_LED +#define FIU_DeflectorSwFCR_Req_FIU_CCU2_No_LED (4) +#endif + +#ifndef FIU_DeflectorSwFCR_Req_FIU_CCU2_LED_3_step +#define FIU_DeflectorSwFCR_Req_FIU_CCU2_LED_3_step (3) +#endif + +#ifndef FIU_DeflectorSwFCR_Req_FIU_CCU2_LED_2_step +#define FIU_DeflectorSwFCR_Req_FIU_CCU2_LED_2_step (2) +#endif + +#ifndef FIU_DeflectorSwFCR_Req_FIU_CCU2_LED_1_step +#define FIU_DeflectorSwFCR_Req_FIU_CCU2_LED_1_step (1) +#endif + +#ifndef FIU_DeflectorSwFCR_Req_FIU_CCU2_No_change +#define FIU_DeflectorSwFCR_Req_FIU_CCU2_No_change (0) +#endif + + +// Value tables for @FIU_DeflectorSwRRB_Req signal + +#ifndef FIU_DeflectorSwRRB_Req_FIU_CCU2_No_LED +#define FIU_DeflectorSwRRB_Req_FIU_CCU2_No_LED (4) +#endif + +#ifndef FIU_DeflectorSwRRB_Req_FIU_CCU2_LED_3_step +#define FIU_DeflectorSwRRB_Req_FIU_CCU2_LED_3_step (3) +#endif + +#ifndef FIU_DeflectorSwRRB_Req_FIU_CCU2_LED_2_step +#define FIU_DeflectorSwRRB_Req_FIU_CCU2_LED_2_step (2) +#endif + +#ifndef FIU_DeflectorSwRRB_Req_FIU_CCU2_LED_1_step +#define FIU_DeflectorSwRRB_Req_FIU_CCU2_LED_1_step (1) +#endif + +#ifndef FIU_DeflectorSwRRB_Req_FIU_CCU2_No_change +#define FIU_DeflectorSwRRB_Req_FIU_CCU2_No_change (0) +#endif + + +// Value tables for @FIU_RearZoneSync_Req signal + +#ifndef FIU_RearZoneSync_Req_FIU_CCU2_No_change +#define FIU_RearZoneSync_Req_FIU_CCU2_No_change (0) +#endif + +#ifndef FIU_RearZoneSync_Req_FIU_CCU2_Sync_rear +#define FIU_RearZoneSync_Req_FIU_CCU2_Sync_rear (1) +#endif + +#ifndef FIU_RearZoneSync_Req_FIU_CCU2_Sync_off +#define FIU_RearZoneSync_Req_FIU_CCU2_Sync_off (2) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Target temperature for rear left zone value + uint8_t FIU_TargetTempRL_Val_ro : 5; // Bits= 5 Offset= 15.5 Factor= 0.5 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t FIU_TargetTempRL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Footwell temperature correction for rear left zone request + // 0 : "No change" + // 1 : "-3 step" + // 2 : "-2 step" + // 3 : "-1 step" + // 4 : "0" + // 5 : "+1 step" + // 6 : "+2 step" + // 7 : "+3 step" + uint8_t FIU_FootTempCorRL_Req : 3; // Bits= 3 + + // Target temperature for rear right zone value + uint8_t FIU_TargetTempRR_Val_ro : 5; // Bits= 5 Offset= 15.5 Factor= 0.5 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t FIU_TargetTempRR_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Footwell temperature correction for rear right zone request + // 0 : "No change" + // 1 : "-3 step" + // 2 : "-2 step" + // 3 : "-1 step" + // 4 : "0" + // 5 : "+1 step" + // 6 : "+2 step" + // 7 : "+3 step" + uint8_t FIU_FootTempCorRR_Req : 3; // Bits= 3 + + // Climate control mode for rear left zone request + // 0 : "No change" + // 1 : "Manual mode requested" + // 2 : "Auto mode requested" + uint8_t FIU_CCmodeRL_Req : 2; // Bits= 2 + + // Airflow direction mode for rear left zone request + // 0 : "No change" + // 1 : "Active" + // 2 : "Inactive" + uint8_t FIU_AirDirectionRL_Def_Req : 2; // Bits= 2 + + // Airflow direction mode for rear left zone request + // 0 : "No change" + // 1 : "Active" + // 2 : "Inactive" + uint8_t FIU_AirDirectionRL_Face_Req : 2; // Bits= 2 + + // Airflow direction mode for rear left zone request + // 0 : "No change" + // 1 : "Active" + // 2 : "Inactive" + uint8_t FIU_AirDirectionRL_Foot_Req : 2; // Bits= 2 + + // Climate control mode for rear right zone request + // 0 : "No change" + // 1 : "Manual mode requested" + // 2 : "Auto mode requested" + uint8_t FIU_CCmodeRR_Req : 2; // Bits= 2 + + // Airflow direction mode for rear right zone request + // 0 : "No change" + // 1 : "Active" + // 2 : "Inactive" + uint8_t FIU_AirDirectionRR_Def_Req : 2; // Bits= 2 + + // Airflow direction mode for rear right zone request + // 0 : "No change" + // 1 : "Active" + // 2 : "Inactive" + uint8_t FIU_AirDirectionRR_Face_Req : 2; // Bits= 2 + + // Airflow direction mode for rear right zone request + // 0 : "No change" + // 1 : "Active" + // 2 : "Inactive" + uint8_t FIU_AirDirectionRR_Foot_Req : 2; // Bits= 2 + + // Blower speed for rear left zone request + // 0 : "No change" + // 1 : "1 step" + // 2 : "2 step" + // 3 : "3 step" + // 4 : "4 step" + // 5 : "5 step" + // 6 : "6 step" + // 7 : "7 step" + // 8 : "Blower off" + uint8_t FIU_BlowerSpeedRL_Req : 4; // Bits= 4 + + // Blower speed for rear right zone request + // 0 : "No change" + // 1 : "1 step" + // 2 : "2 step" + // 3 : "3 step" + // 4 : "4 step" + // 5 : "5 step" + // 6 : "6 step" + // 7 : "7 step" + // 8 : "Blower off" + uint8_t FIU_BlowerSpeedRR_Req : 4; // Bits= 4 + + // Climate control auto mode for rear left zone request + // 0 : "No change" + // 1 : "Auto mode 1 requested" + // 2 : "Auto mode 2 requested" + // 3 : "Auto mode 3 requested" + // 4 : "Auto mode 4 requested" + // 5 : "Auto mode 5 requested" + uint8_t FIU_CCautoModeRL_Req : 3; // Bits= 3 + + // Climate control auto mode for rear right zone request + // 0 : "No change" + // 1 : "Auto mode 1 requested" + // 2 : "Auto mode 2 requested" + // 3 : "Auto mode 3 requested" + // 4 : "Auto mode 4 requested" + // 5 : "Auto mode 5 requested" + uint8_t FIU_CCautoModeRR_Req : 3; // Bits= 3 + + // Deflector rear left in B-pillar request + // 4 : "No LED" + // 3 : "LED 3 step" + // 2 : "LED 2 step" + // 1 : "LED 1 step" + // 0 : "No change" + uint8_t FIU_DeflectorSwRLB_Req : 3; // Bits= 3 + + // Deflector front console left request + // 4 : "No LED" + // 3 : "LED 3 step" + // 2 : "LED 2 step" + // 1 : "LED 1 step" + // 0 : "No change" + uint8_t FIU_DeflectorSwFCL_Req : 3; // Bits= 3 + + // Air conditioner OFF rear request + // 0 : "No change" + // 1 : "AC front ON" + // 2 : "AC front OFF" + uint8_t FIU_ACrearOFF_Req : 2; // Bits= 2 + + // Deflector front console right request + // 4 : "No LED" + // 3 : "LED 3 step" + // 2 : "LED 2 step" + // 1 : "LED 1 step" + // 0 : "No change" + uint8_t FIU_DeflectorSwFCR_Req : 3; // Bits= 3 + + // Deflector rear right in B-pillar request + // 4 : "No LED" + // 3 : "LED 3 step" + // 2 : "LED 2 step" + // 1 : "LED 1 step" + // 0 : "No change" + uint8_t FIU_DeflectorSwRRB_Req : 3; // Bits= 3 + + // Rear climate zones synchronization on/off request + // 0 : "No change" + // 1 : "Sync rear" + // 2 : "Sync off" + uint8_t FIU_RearZoneSync_Req : 2; // Bits= 2 + +#else + + // Target temperature for rear left zone value + uint8_t FIU_TargetTempRL_Val_ro; // Bits= 5 Offset= 15.5 Factor= 0.5 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t FIU_TargetTempRL_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Footwell temperature correction for rear left zone request + // 0 : "No change" + // 1 : "-3 step" + // 2 : "-2 step" + // 3 : "-1 step" + // 4 : "0" + // 5 : "+1 step" + // 6 : "+2 step" + // 7 : "+3 step" + uint8_t FIU_FootTempCorRL_Req; // Bits= 3 + + // Target temperature for rear right zone value + uint8_t FIU_TargetTempRR_Val_ro; // Bits= 5 Offset= 15.5 Factor= 0.5 + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t FIU_TargetTempRR_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Footwell temperature correction for rear right zone request + // 0 : "No change" + // 1 : "-3 step" + // 2 : "-2 step" + // 3 : "-1 step" + // 4 : "0" + // 5 : "+1 step" + // 6 : "+2 step" + // 7 : "+3 step" + uint8_t FIU_FootTempCorRR_Req; // Bits= 3 + + // Climate control mode for rear left zone request + // 0 : "No change" + // 1 : "Manual mode requested" + // 2 : "Auto mode requested" + uint8_t FIU_CCmodeRL_Req; // Bits= 2 + + // Airflow direction mode for rear left zone request + // 0 : "No change" + // 1 : "Active" + // 2 : "Inactive" + uint8_t FIU_AirDirectionRL_Def_Req; // Bits= 2 + + // Airflow direction mode for rear left zone request + // 0 : "No change" + // 1 : "Active" + // 2 : "Inactive" + uint8_t FIU_AirDirectionRL_Face_Req; // Bits= 2 + + // Airflow direction mode for rear left zone request + // 0 : "No change" + // 1 : "Active" + // 2 : "Inactive" + uint8_t FIU_AirDirectionRL_Foot_Req; // Bits= 2 + + // Climate control mode for rear right zone request + // 0 : "No change" + // 1 : "Manual mode requested" + // 2 : "Auto mode requested" + uint8_t FIU_CCmodeRR_Req; // Bits= 2 + + // Airflow direction mode for rear right zone request + // 0 : "No change" + // 1 : "Active" + // 2 : "Inactive" + uint8_t FIU_AirDirectionRR_Def_Req; // Bits= 2 + + // Airflow direction mode for rear right zone request + // 0 : "No change" + // 1 : "Active" + // 2 : "Inactive" + uint8_t FIU_AirDirectionRR_Face_Req; // Bits= 2 + + // Airflow direction mode for rear right zone request + // 0 : "No change" + // 1 : "Active" + // 2 : "Inactive" + uint8_t FIU_AirDirectionRR_Foot_Req; // Bits= 2 + + // Blower speed for rear left zone request + // 0 : "No change" + // 1 : "1 step" + // 2 : "2 step" + // 3 : "3 step" + // 4 : "4 step" + // 5 : "5 step" + // 6 : "6 step" + // 7 : "7 step" + // 8 : "Blower off" + uint8_t FIU_BlowerSpeedRL_Req; // Bits= 4 + + // Blower speed for rear right zone request + // 0 : "No change" + // 1 : "1 step" + // 2 : "2 step" + // 3 : "3 step" + // 4 : "4 step" + // 5 : "5 step" + // 6 : "6 step" + // 7 : "7 step" + // 8 : "Blower off" + uint8_t FIU_BlowerSpeedRR_Req; // Bits= 4 + + // Climate control auto mode for rear left zone request + // 0 : "No change" + // 1 : "Auto mode 1 requested" + // 2 : "Auto mode 2 requested" + // 3 : "Auto mode 3 requested" + // 4 : "Auto mode 4 requested" + // 5 : "Auto mode 5 requested" + uint8_t FIU_CCautoModeRL_Req; // Bits= 3 + + // Climate control auto mode for rear right zone request + // 0 : "No change" + // 1 : "Auto mode 1 requested" + // 2 : "Auto mode 2 requested" + // 3 : "Auto mode 3 requested" + // 4 : "Auto mode 4 requested" + // 5 : "Auto mode 5 requested" + uint8_t FIU_CCautoModeRR_Req; // Bits= 3 + + // Deflector rear left in B-pillar request + // 4 : "No LED" + // 3 : "LED 3 step" + // 2 : "LED 2 step" + // 1 : "LED 1 step" + // 0 : "No change" + uint8_t FIU_DeflectorSwRLB_Req; // Bits= 3 + + // Deflector front console left request + // 4 : "No LED" + // 3 : "LED 3 step" + // 2 : "LED 2 step" + // 1 : "LED 1 step" + // 0 : "No change" + uint8_t FIU_DeflectorSwFCL_Req; // Bits= 3 + + // Air conditioner OFF rear request + // 0 : "No change" + // 1 : "AC front ON" + // 2 : "AC front OFF" + uint8_t FIU_ACrearOFF_Req; // Bits= 2 + + // Deflector front console right request + // 4 : "No LED" + // 3 : "LED 3 step" + // 2 : "LED 2 step" + // 1 : "LED 1 step" + // 0 : "No change" + uint8_t FIU_DeflectorSwFCR_Req; // Bits= 3 + + // Deflector rear right in B-pillar request + // 4 : "No LED" + // 3 : "LED 3 step" + // 2 : "LED 2 step" + // 1 : "LED 1 step" + // 0 : "No change" + uint8_t FIU_DeflectorSwRRB_Req; // Bits= 3 + + // Rear climate zones synchronization on/off request + // 0 : "No change" + // 1 : "Sync rear" + // 2 : "Sync off" + uint8_t FIU_RearZoneSync_Req; // Bits= 2 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} FIU_CCU2_t; + +// def @FIU_CCU3 CAN Message (1443 0x5a3) +#define FIU_CCU3_IDE (0U) +#define FIU_CCU3_DLC (3U) +#define FIU_CCU3_CANID (0x5a3U) + +// Value tables for @FIU_Aroma_Req signal + +#ifndef FIU_Aroma_Req_FIU_CCU3_No_change +#define FIU_Aroma_Req_FIU_CCU3_No_change (0) +#endif + +#ifndef FIU_Aroma_Req_FIU_CCU3_Aromatization_on +#define FIU_Aroma_Req_FIU_CCU3_Aromatization_on (1) +#endif + +#ifndef FIU_Aroma_Req_FIU_CCU3_Aromatization_off +#define FIU_Aroma_Req_FIU_CCU3_Aromatization_off (2) +#endif + + +// Value tables for @FIU_AromaIntens_Req signal + +#ifndef FIU_AromaIntens_Req_FIU_CCU3_No_change +#define FIU_AromaIntens_Req_FIU_CCU3_No_change (0) +#endif + +#ifndef FIU_AromaIntens_Req_FIU_CCU3_Aromatization_mode_1_step +#define FIU_AromaIntens_Req_FIU_CCU3_Aromatization_mode_1_step (1) +#endif + +#ifndef FIU_AromaIntens_Req_FIU_CCU3_Aromatization_mode_2_step +#define FIU_AromaIntens_Req_FIU_CCU3_Aromatization_mode_2_step (2) +#endif + +#ifndef FIU_AromaIntens_Req_FIU_CCU3_Aromatization_mode_3_step +#define FIU_AromaIntens_Req_FIU_CCU3_Aromatization_mode_3_step (3) +#endif + + +// Value tables for @FIU_Rest_Req signal + +#ifndef FIU_Rest_Req_FIU_CCU3_No_change +#define FIU_Rest_Req_FIU_CCU3_No_change (0) +#endif + +#ifndef FIU_Rest_Req_FIU_CCU3_Rest_mode_requested +#define FIU_Rest_Req_FIU_CCU3_Rest_mode_requested (1) +#endif + +#ifndef FIU_Rest_Req_FIU_CCU3_Rest_mode_not_requested +#define FIU_Rest_Req_FIU_CCU3_Rest_mode_not_requested (2) +#endif + + +// Value tables for @FIU_Ionization_Req signal + +#ifndef FIU_Ionization_Req_FIU_CCU3_Ionization_off +#define FIU_Ionization_Req_FIU_CCU3_Ionization_off (2) +#endif + +#ifndef FIU_Ionization_Req_FIU_CCU3_Ionization_on +#define FIU_Ionization_Req_FIU_CCU3_Ionization_on (1) +#endif + +#ifndef FIU_Ionization_Req_FIU_CCU3_No_change +#define FIU_Ionization_Req_FIU_CCU3_No_change (0) +#endif + + +// Value tables for @FIU_RLfootBlowDis_Req signal + +#ifndef FIU_RLfootBlowDis_Req_FIU_CCU3_No_change +#define FIU_RLfootBlowDis_Req_FIU_CCU3_No_change (0) +#endif + +#ifndef FIU_RLfootBlowDis_Req_FIU_CCU3_Rear_footwell_blowing_disabled_limitation_ON +#define FIU_RLfootBlowDis_Req_FIU_CCU3_Rear_footwell_blowing_disabled_limitation_ON (1) +#endif + +#ifndef FIU_RLfootBlowDis_Req_FIU_CCU3_Rear_footwell_blowing_enabled_limitation_OFF +#define FIU_RLfootBlowDis_Req_FIU_CCU3_Rear_footwell_blowing_enabled_limitation_OFF (2) +#endif + + +// Value tables for @FIU_RRfootBlowDis_Req signal + +#ifndef FIU_RRfootBlowDis_Req_FIU_CCU3_No_change +#define FIU_RRfootBlowDis_Req_FIU_CCU3_No_change (0) +#endif + +#ifndef FIU_RRfootBlowDis_Req_FIU_CCU3_Rear_footwell_blowing_disabled_limitation_ON +#define FIU_RRfootBlowDis_Req_FIU_CCU3_Rear_footwell_blowing_disabled_limitation_ON (1) +#endif + +#ifndef FIU_RRfootBlowDis_Req_FIU_CCU3_Rear_footwell_blowing_enabled_limitation_OFF +#define FIU_RRfootBlowDis_Req_FIU_CCU3_Rear_footwell_blowing_enabled_limitation_OFF (2) +#endif + + +// Value tables for @FIU_ACmax_Req signal + +#ifndef FIU_ACmax_Req_FIU_CCU3_No_change +#define FIU_ACmax_Req_FIU_CCU3_No_change (0) +#endif + +#ifndef FIU_ACmax_Req_FIU_CCU3_AC_MAX_on +#define FIU_ACmax_Req_FIU_CCU3_AC_MAX_on (1) +#endif + +#ifndef FIU_ACmax_Req_FIU_CCU3_AC_MAX_off +#define FIU_ACmax_Req_FIU_CCU3_AC_MAX_off (2) +#endif + + +// Value tables for @FIU_Defrost_Req signal + +#ifndef FIU_Defrost_Req_FIU_CCU3_No_change +#define FIU_Defrost_Req_FIU_CCU3_No_change (0) +#endif + +#ifndef FIU_Defrost_Req_FIU_CCU3_Defrost_on +#define FIU_Defrost_Req_FIU_CCU3_Defrost_on (1) +#endif + +#ifndef FIU_Defrost_Req_FIU_CCU3_Defrost_off +#define FIU_Defrost_Req_FIU_CCU3_Defrost_off (2) +#endif + + +// Value tables for @FIU_Ultraviolet_Req signal + +#ifndef FIU_Ultraviolet_Req_FIU_CCU3_Ultraviolet_off +#define FIU_Ultraviolet_Req_FIU_CCU3_Ultraviolet_off (2) +#endif + +#ifndef FIU_Ultraviolet_Req_FIU_CCU3_Ultraviolet_on +#define FIU_Ultraviolet_Req_FIU_CCU3_Ultraviolet_on (1) +#endif + +#ifndef FIU_Ultraviolet_Req_FIU_CCU3_No_change +#define FIU_Ultraviolet_Req_FIU_CCU3_No_change (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Aromatization system request + // 0 : "No change" + // 1 : "Aromatization on" + // 2 : "Aromatization off" + uint8_t FIU_Aroma_Req : 2; // Bits= 2 + + // Aromatization intensity request + // 0 : "No change" + // 1 : "Aromatization mode 1 step" + // 2 : "Aromatization mode 2 step" + // 3 : "Aromatization mode 3 step" + uint8_t FIU_AromaIntens_Req : 2; // Bits= 2 + + // Rest mode request + // 0 : "No change" + // 1 : "Rest mode requested" + // 2 : "Rest mode not requested" + uint8_t FIU_Rest_Req : 2; // Bits= 2 + + // Ionization system request + // 2 : "Ionization off" + // 1 : "Ionization on" + // 0 : "No change" + uint8_t FIU_Ionization_Req : 2; // Bits= 2 + + // Rear left passenger footwell blowing disable request (summer mode) + // 0 : "No change" + // 1 : "Rear footwell blowing disabled (limitation ON)" + // 2 : "Rear footwell blowing enabled (limitation OFF)" + uint8_t FIU_RLfootBlowDis_Req : 2; // Bits= 2 + + // Rear right passenger footwell blowing disable request (summer mode) + // 0 : "No change" + // 1 : "Rear footwell blowing disabled (limitation ON)" + // 2 : "Rear footwell blowing enabled (limitation OFF)" + uint8_t FIU_RRfootBlowDis_Req : 2; // Bits= 2 + + // AC max mode request + // 0 : "No change" + // 1 : "AC MAX on" + // 2 : "AC MAX off" + uint8_t FIU_ACmax_Req : 2; // Bits= 2 + + // Defrost max mode request + // 0 : "No change" + // 1 : "Defrost on" + // 2 : "Defrost off" + uint8_t FIU_Defrost_Req : 2; // Bits= 2 + + // Ultraviolet system mode request + // 2 : "Ultraviolet off" + // 1 : "Ultraviolet on" + // 0 : "No change" + uint8_t FIU_Ultraviolet_Req : 2; // Bits= 2 + +#else + + // Aromatization system request + // 0 : "No change" + // 1 : "Aromatization on" + // 2 : "Aromatization off" + uint8_t FIU_Aroma_Req; // Bits= 2 + + // Aromatization intensity request + // 0 : "No change" + // 1 : "Aromatization mode 1 step" + // 2 : "Aromatization mode 2 step" + // 3 : "Aromatization mode 3 step" + uint8_t FIU_AromaIntens_Req; // Bits= 2 + + // Rest mode request + // 0 : "No change" + // 1 : "Rest mode requested" + // 2 : "Rest mode not requested" + uint8_t FIU_Rest_Req; // Bits= 2 + + // Ionization system request + // 2 : "Ionization off" + // 1 : "Ionization on" + // 0 : "No change" + uint8_t FIU_Ionization_Req; // Bits= 2 + + // Rear left passenger footwell blowing disable request (summer mode) + // 0 : "No change" + // 1 : "Rear footwell blowing disabled (limitation ON)" + // 2 : "Rear footwell blowing enabled (limitation OFF)" + uint8_t FIU_RLfootBlowDis_Req; // Bits= 2 + + // Rear right passenger footwell blowing disable request (summer mode) + // 0 : "No change" + // 1 : "Rear footwell blowing disabled (limitation ON)" + // 2 : "Rear footwell blowing enabled (limitation OFF)" + uint8_t FIU_RRfootBlowDis_Req; // Bits= 2 + + // AC max mode request + // 0 : "No change" + // 1 : "AC MAX on" + // 2 : "AC MAX off" + uint8_t FIU_ACmax_Req; // Bits= 2 + + // Defrost max mode request + // 0 : "No change" + // 1 : "Defrost on" + // 2 : "Defrost off" + uint8_t FIU_Defrost_Req; // Bits= 2 + + // Ultraviolet system mode request + // 2 : "Ultraviolet off" + // 1 : "Ultraviolet on" + // 0 : "No change" + uint8_t FIU_Ultraviolet_Req; // Bits= 2 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} FIU_CCU3_t; + +// def @BCM_StyleCmd2 CAN Message (1446 0x5a6) +#define BCM_StyleCmd2_IDE (0U) +#define BCM_StyleCmd2_DLC (8U) +#define BCM_StyleCmd2_CANID (0x5a6U) + +// Value tables for @BCM_Script_play_Req signal + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__No_changes +#define BCM_Script_play_Req_BCM_StyleCmd2__No_changes (0) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__2_color_gradient +#define BCM_Script_play_Req_BCM_StyleCmd2__2_color_gradient (1) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__3_color_gradient +#define BCM_Script_play_Req_BCM_StyleCmd2__3_color_gradient (2) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Permanent_color +#define BCM_Script_play_Req_BCM_StyleCmd2__Permanent_color (3) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Brightness_gradient +#define BCM_Script_play_Req_BCM_StyleCmd2__Brightness_gradient (4) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_5_ +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_5_ (5) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_6 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_6 (6) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_63 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_63 (62) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_64 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_64 (63) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_7 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_7 (7) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_8 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_8 (8) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_9 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_9 (9) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_10 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_10 (10) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_11 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_11 (11) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_12 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_12 (12) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_13 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_13 (13) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_14 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_14 (14) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_15 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_15 (15) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_16 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_16 (16) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_17 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_17 (17) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_18 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_18 (18) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_19 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_19 (19) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_20 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_20 (20) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_21 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_21 (21) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_22 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_22 (22) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_23 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_23 (23) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_24 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_24 (24) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_25 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_25 (25) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_26 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_26 (26) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_27 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_27 (27) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_28 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_28 (28) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_29 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_29 (29) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_31 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_31 (30) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_32 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_32 (31) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_33 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_33 (32) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_34 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_34 (33) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_35 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_35 (34) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_36 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_36 (35) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_37 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_37 (36) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_38 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_38 (37) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_39 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_39 (38) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_40 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_40 (39) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_41 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_41 (40) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_42 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_42 (41) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_43 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_43 (42) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_44 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_44 (43) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_45 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_45 (44) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_46 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_46 (45) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_47 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_47 (46) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_48 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_48 (47) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_49 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_49 (48) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_50 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_50 (49) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_51 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_51 (50) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_52 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_52 (51) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_53 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_53 (52) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_54 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_54 (53) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_55 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_55 (54) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_56 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_56 (55) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_57 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_57 (56) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_58 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_58 (57) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_59 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_59 (58) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_60 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_60 (59) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_61 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_61 (60) +#endif + +#ifndef BCM_Script_play_Req_BCM_StyleCmd2__Script_62 +#define BCM_Script_play_Req_BCM_StyleCmd2__Script_62 (61) +#endif + + +// Value tables for @BCM_StartPosition_Req signal + +#ifndef BCM_StartPosition_Req_BCM_StyleCmd2__From_edges_to_center +#define BCM_StartPosition_Req_BCM_StyleCmd2__From_edges_to_center (4) +#endif + +#ifndef BCM_StartPosition_Req_BCM_StyleCmd2__Center_strip_start +#define BCM_StartPosition_Req_BCM_StyleCmd2__Center_strip_start (3) +#endif + +#ifndef BCM_StartPosition_Req_BCM_StyleCmd2__Last_LED_start_inversion +#define BCM_StartPosition_Req_BCM_StyleCmd2__Last_LED_start_inversion (2) +#endif + +#ifndef BCM_StartPosition_Req_BCM_StyleCmd2__0_LED_Start +#define BCM_StartPosition_Req_BCM_StyleCmd2__0_LED_Start (1) +#endif + +#ifndef BCM_StartPosition_Req_BCM_StyleCmd2__No_changes +#define BCM_StartPosition_Req_BCM_StyleCmd2__No_changes (0) +#endif + + +// Value tables for @BCM_MiddlePosition_Req signal + +#ifndef BCM_MiddlePosition_Req_BCM_StyleCmd2__From_edges_to_center +#define BCM_MiddlePosition_Req_BCM_StyleCmd2__From_edges_to_center (4) +#endif + +#ifndef BCM_MiddlePosition_Req_BCM_StyleCmd2__Center_strip_start +#define BCM_MiddlePosition_Req_BCM_StyleCmd2__Center_strip_start (3) +#endif + +#ifndef BCM_MiddlePosition_Req_BCM_StyleCmd2__Last_LED_start_inversion +#define BCM_MiddlePosition_Req_BCM_StyleCmd2__Last_LED_start_inversion (2) +#endif + +#ifndef BCM_MiddlePosition_Req_BCM_StyleCmd2__0_LED_Start +#define BCM_MiddlePosition_Req_BCM_StyleCmd2__0_LED_Start (1) +#endif + +#ifndef BCM_MiddlePosition_Req_BCM_StyleCmd2__No_changes +#define BCM_MiddlePosition_Req_BCM_StyleCmd2__No_changes (0) +#endif + + +// Value tables for @BCM_EndPosition_Req signal + +#ifndef BCM_EndPosition_Req_BCM_StyleCmd2__From_edges_to_center +#define BCM_EndPosition_Req_BCM_StyleCmd2__From_edges_to_center (4) +#endif + +#ifndef BCM_EndPosition_Req_BCM_StyleCmd2__Center_strip_start +#define BCM_EndPosition_Req_BCM_StyleCmd2__Center_strip_start (3) +#endif + +#ifndef BCM_EndPosition_Req_BCM_StyleCmd2__Last_LED_start_inversion +#define BCM_EndPosition_Req_BCM_StyleCmd2__Last_LED_start_inversion (2) +#endif + +#ifndef BCM_EndPosition_Req_BCM_StyleCmd2__0_LED_Start +#define BCM_EndPosition_Req_BCM_StyleCmd2__0_LED_Start (1) +#endif + +#ifndef BCM_EndPosition_Req_BCM_StyleCmd2__No_changes +#define BCM_EndPosition_Req_BCM_StyleCmd2__No_changes (0) +#endif + + +// Value tables for @BCM_ColorConfiguration_Stat signal + +#ifndef BCM_ColorConfiguration_Stat_BCM_StyleCmd2__1__2__3__4 +#define BCM_ColorConfiguration_Stat_BCM_StyleCmd2__1__2__3__4 (7) +#endif + +#ifndef BCM_ColorConfiguration_Stat_BCM_StyleCmd2__1__2__3 +#define BCM_ColorConfiguration_Stat_BCM_StyleCmd2__1__2__3 (6) +#endif + +#ifndef BCM_ColorConfiguration_Stat_BCM_StyleCmd2__1__2 +#define BCM_ColorConfiguration_Stat_BCM_StyleCmd2__1__2 (5) +#endif + +#ifndef BCM_ColorConfiguration_Stat_BCM_StyleCmd2__4th_color +#define BCM_ColorConfiguration_Stat_BCM_StyleCmd2__4th_color (4) +#endif + +#ifndef BCM_ColorConfiguration_Stat_BCM_StyleCmd2__3d_color +#define BCM_ColorConfiguration_Stat_BCM_StyleCmd2__3d_color (3) +#endif + +#ifndef BCM_ColorConfiguration_Stat_BCM_StyleCmd2__2nd_color +#define BCM_ColorConfiguration_Stat_BCM_StyleCmd2__2nd_color (2) +#endif + +#ifndef BCM_ColorConfiguration_Stat_BCM_StyleCmd2__1st_color +#define BCM_ColorConfiguration_Stat_BCM_StyleCmd2__1st_color (1) +#endif + +#ifndef BCM_ColorConfiguration_Stat_BCM_StyleCmd2__No_changes +#define BCM_ColorConfiguration_Stat_BCM_StyleCmd2__No_changes (0) +#endif + +// signal: @BCM_Color_Width_Val_ro +#define CANDB_BCM_Color_Width_Val_ro_CovFactor (0.5) +#define CANDB_BCM_Color_Width_Val_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.5)) ) +#define CANDB_BCM_Color_Width_Val_ro_fromS(x) ( (((x) * (0.5)) + (0.0)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Algorythm to play: + // 0 - No algorythm change + // 1 - Algorythm 1 + // 2 - Algorythm 2 + // ----------------------------- + // 3F - Algorythm N + // 0 : " No changes" + // 1 : " 2 color gradient" + // 2 : " 3 color gradient" + // 3 : " Permanent color" + // 4 : " Brightness gradient" + // 5 : " Script 5 " + // 6 : " Script 6" + // 62 : " Script 63" + // 63 : " Script 64" + // 7 : " Script 7" + // 8 : " Script 8" + // 9 : " Script 9" + // 10 : " Script 10" + // 11 : " Script 11" + // 12 : " Script 12" + // 13 : " Script 13" + // 14 : " Script 14" + // 15 : " Script 15" + // 16 : " Script 16" + // 17 : " Script 17" + // 18 : " Script 18" + // 19 : " Script 19" + // 20 : " Script 20" + // 21 : " Script 21" + // 22 : " Script 22" + // 23 : " Script 23" + // 24 : " Script 24" + // 25 : " Script 25" + // 26 : " Script 26" + // 27 : " Script 27" + // 28 : " Script 28" + // 29 : " Script 29" + // 30 : " Script 31" + // 31 : " Script 32" + // 32 : " Script 33" + // 33 : " Script 34" + // 34 : " Script 35" + // 35 : " Script 36" + // 36 : " Script 37" + // 37 : " Script 38" + // 38 : " Script 39" + // 39 : " Script 40" + // 40 : " Script 41" + // 41 : " Script 42" + // 42 : " Script 43" + // 43 : " Script 44" + // 44 : " Script 45" + // 45 : " Script 46" + // 46 : " Script 47" + // 47 : " Script 48" + // 48 : " Script 49" + // 49 : " Script 50" + // 50 : " Script 51" + // 51 : " Script 52" + // 52 : " Script 53" + // 53 : " Script 54" + // 54 : " Script 55" + // 55 : " Script 56" + // 56 : " Script 57" + // 57 : " Script 58" + // 58 : " Script 59" + // 59 : " Script 60" + // 60 : " Script 61" + // 61 : " Script 62" + uint8_t BCM_Script_play_Req : 6; // Bits= 6 + + // Position of scenario start: + // 0 - Start from 0 led + // 1 - Start from last led (inversion) + // 2 - Start from center + // 3 - From edges to center + // 4 : " From edges to center" + // 3 : " Center strip start" + // 2 : " Last LED start (inversion)" + // 1 : " 0 LED Start" + // 0 : " No changes" + uint8_t BCM_StartPosition_Req : 3; // Bits= 3 + + // Position of scenario middle: + // 0 - Start from 0 led + // 1 - Start from last led (inversion) + // 2 - Start from center + // 3 - From edges to center + // 4 : " From edges to center" + // 3 : " Center strip start" + // 2 : " Last LED start (inversion)" + // 1 : " 0 LED Start" + // 0 : " No changes" + uint8_t BCM_MiddlePosition_Req : 3; // Bits= 3 + + // Position of scenario end: + // 0 - Start from 0 led + // 1 - Start from last led (inversion) + // 2 - Start from center + // 3 - From edges to center + // 4 : " From edges to center" + // 3 : " Center strip start" + // 2 : " Last LED start (inversion)" + // 1 : " 0 LED Start" + // 0 : " No changes" + uint8_t BCM_EndPosition_Req : 3; // Bits= 3 + + // Color pick + // 7 : " 1 & 2 & 3 & 4" + // 6 : " 1 & 2 & 3" + // 5 : " 1 & 2" + // 4 : " 4th color" + // 3 : " 3d color" + // 2 : " 2nd color" + // 1 : " 1st color" + // 0 : " No changes" + uint8_t BCM_ColorConfiguration_Stat : 3; // Bits= 3 + + // Color width: percentage or leds amount + uint8_t BCM_Color_Width_Val_ro; // Bits= 8 Factor= 0.5 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_Color_Width_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Red color coordinate + uint8_t BCM_RedColorParameter_Val; // Bits= 8 + + // Green color coordinate + uint8_t BCM_GreenColorParameter_Val; // Bits= 8 + + // Blue color coordinate + uint8_t BCM_BlueColorParameter_Val; // Bits= 8 + + // White color coordinate + uint8_t BCM_WhiteColorParameter_Val; // Bits= 8 + +#else + + // Algorythm to play: + // 0 - No algorythm change + // 1 - Algorythm 1 + // 2 - Algorythm 2 + // ----------------------------- + // 3F - Algorythm N + // 0 : " No changes" + // 1 : " 2 color gradient" + // 2 : " 3 color gradient" + // 3 : " Permanent color" + // 4 : " Brightness gradient" + // 5 : " Script 5 " + // 6 : " Script 6" + // 62 : " Script 63" + // 63 : " Script 64" + // 7 : " Script 7" + // 8 : " Script 8" + // 9 : " Script 9" + // 10 : " Script 10" + // 11 : " Script 11" + // 12 : " Script 12" + // 13 : " Script 13" + // 14 : " Script 14" + // 15 : " Script 15" + // 16 : " Script 16" + // 17 : " Script 17" + // 18 : " Script 18" + // 19 : " Script 19" + // 20 : " Script 20" + // 21 : " Script 21" + // 22 : " Script 22" + // 23 : " Script 23" + // 24 : " Script 24" + // 25 : " Script 25" + // 26 : " Script 26" + // 27 : " Script 27" + // 28 : " Script 28" + // 29 : " Script 29" + // 30 : " Script 31" + // 31 : " Script 32" + // 32 : " Script 33" + // 33 : " Script 34" + // 34 : " Script 35" + // 35 : " Script 36" + // 36 : " Script 37" + // 37 : " Script 38" + // 38 : " Script 39" + // 39 : " Script 40" + // 40 : " Script 41" + // 41 : " Script 42" + // 42 : " Script 43" + // 43 : " Script 44" + // 44 : " Script 45" + // 45 : " Script 46" + // 46 : " Script 47" + // 47 : " Script 48" + // 48 : " Script 49" + // 49 : " Script 50" + // 50 : " Script 51" + // 51 : " Script 52" + // 52 : " Script 53" + // 53 : " Script 54" + // 54 : " Script 55" + // 55 : " Script 56" + // 56 : " Script 57" + // 57 : " Script 58" + // 58 : " Script 59" + // 59 : " Script 60" + // 60 : " Script 61" + // 61 : " Script 62" + uint8_t BCM_Script_play_Req; // Bits= 6 + + // Position of scenario start: + // 0 - Start from 0 led + // 1 - Start from last led (inversion) + // 2 - Start from center + // 3 - From edges to center + // 4 : " From edges to center" + // 3 : " Center strip start" + // 2 : " Last LED start (inversion)" + // 1 : " 0 LED Start" + // 0 : " No changes" + uint8_t BCM_StartPosition_Req; // Bits= 3 + + // Position of scenario middle: + // 0 - Start from 0 led + // 1 - Start from last led (inversion) + // 2 - Start from center + // 3 - From edges to center + // 4 : " From edges to center" + // 3 : " Center strip start" + // 2 : " Last LED start (inversion)" + // 1 : " 0 LED Start" + // 0 : " No changes" + uint8_t BCM_MiddlePosition_Req; // Bits= 3 + + // Position of scenario end: + // 0 - Start from 0 led + // 1 - Start from last led (inversion) + // 2 - Start from center + // 3 - From edges to center + // 4 : " From edges to center" + // 3 : " Center strip start" + // 2 : " Last LED start (inversion)" + // 1 : " 0 LED Start" + // 0 : " No changes" + uint8_t BCM_EndPosition_Req; // Bits= 3 + + // Color pick + // 7 : " 1 & 2 & 3 & 4" + // 6 : " 1 & 2 & 3" + // 5 : " 1 & 2" + // 4 : " 4th color" + // 3 : " 3d color" + // 2 : " 2nd color" + // 1 : " 1st color" + // 0 : " No changes" + uint8_t BCM_ColorConfiguration_Stat; // Bits= 3 + + // Color width: percentage or leds amount + uint8_t BCM_Color_Width_Val_ro; // Bits= 8 Factor= 0.5 Unit:'%' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t BCM_Color_Width_Val_phys; +#endif // CANDB_USE_SIGFLOAT + + // Red color coordinate + uint8_t BCM_RedColorParameter_Val; // Bits= 8 + + // Green color coordinate + uint8_t BCM_GreenColorParameter_Val; // Bits= 8 + + // Blue color coordinate + uint8_t BCM_BlueColorParameter_Val; // Bits= 8 + + // White color coordinate + uint8_t BCM_WhiteColorParameter_Val; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} BCM_StyleCmd2_t; + +// def @BCM_StyleCmd3 CAN Message (1447 0x5a7) +#define BCM_StyleCmd3_IDE (0U) +#define BCM_StyleCmd3_DLC (8U) +#define BCM_StyleCmd3_CANID (0x5a7U) + +// Value tables for @BCM_PlaceToPlay_Req signal + +#ifndef BCM_PlaceToPlay_Req_BCM_StyleCmd3__End_place +#define BCM_PlaceToPlay_Req_BCM_StyleCmd3__End_place (3) +#endif + +#ifndef BCM_PlaceToPlay_Req_BCM_StyleCmd3__Start_place +#define BCM_PlaceToPlay_Req_BCM_StyleCmd3__Start_place (2) +#endif + +#ifndef BCM_PlaceToPlay_Req_BCM_StyleCmd3__All_places +#define BCM_PlaceToPlay_Req_BCM_StyleCmd3__All_places (1) +#endif + +#ifndef BCM_PlaceToPlay_Req_BCM_StyleCmd3__No_changes +#define BCM_PlaceToPlay_Req_BCM_StyleCmd3__No_changes (0) +#endif + + +// Value tables for @BCM_TransModeOutScen_Req signal + +#ifndef BCM_TransModeOutScen_Req_BCM_StyleCmd3__Reserved +#define BCM_TransModeOutScen_Req_BCM_StyleCmd3__Reserved (13) +#endif + +#ifndef BCM_TransModeOutScen_Req_BCM_StyleCmd3__Reserved +#define BCM_TransModeOutScen_Req_BCM_StyleCmd3__Reserved (12) +#endif + +#ifndef BCM_TransModeOutScen_Req_BCM_StyleCmd3__Reserved +#define BCM_TransModeOutScen_Req_BCM_StyleCmd3__Reserved (11) +#endif + +#ifndef BCM_TransModeOutScen_Req_BCM_StyleCmd3__Reserved +#define BCM_TransModeOutScen_Req_BCM_StyleCmd3__Reserved (10) +#endif + +#ifndef BCM_TransModeOutScen_Req_BCM_StyleCmd3__Reserved +#define BCM_TransModeOutScen_Req_BCM_StyleCmd3__Reserved (9) +#endif + +#ifndef BCM_TransModeOutScen_Req_BCM_StyleCmd3__Reserved +#define BCM_TransModeOutScen_Req_BCM_StyleCmd3__Reserved (8) +#endif + +#ifndef BCM_TransModeOutScen_Req_BCM_StyleCmd3__Reserved +#define BCM_TransModeOutScen_Req_BCM_StyleCmd3__Reserved (7) +#endif + +#ifndef BCM_TransModeOutScen_Req_BCM_StyleCmd3__Reserved +#define BCM_TransModeOutScen_Req_BCM_StyleCmd3__Reserved (6) +#endif + +#ifndef BCM_TransModeOutScen_Req_BCM_StyleCmd3__Reserved +#define BCM_TransModeOutScen_Req_BCM_StyleCmd3__Reserved (5) +#endif + +#ifndef BCM_TransModeOutScen_Req_BCM_StyleCmd3__Reserved +#define BCM_TransModeOutScen_Req_BCM_StyleCmd3__Reserved (14) +#endif + +#ifndef BCM_TransModeOutScen_Req_BCM_StyleCmd3__Reserved +#define BCM_TransModeOutScen_Req_BCM_StyleCmd3__Reserved (15) +#endif + +#ifndef BCM_TransModeOutScen_Req_BCM_StyleCmd3__Smooth_strip_fill_with_brightness_tail +#define BCM_TransModeOutScen_Req_BCM_StyleCmd3__Smooth_strip_fill_with_brightness_tail (4) +#endif + +#ifndef BCM_TransModeOutScen_Req_BCM_StyleCmd3__Smooth_strip_fill +#define BCM_TransModeOutScen_Req_BCM_StyleCmd3__Smooth_strip_fill (3) +#endif + +#ifndef BCM_TransModeOutScen_Req_BCM_StyleCmd3__Smooth_transition +#define BCM_TransModeOutScen_Req_BCM_StyleCmd3__Smooth_transition (2) +#endif + +#ifndef BCM_TransModeOutScen_Req_BCM_StyleCmd3__Rough_transition +#define BCM_TransModeOutScen_Req_BCM_StyleCmd3__Rough_transition (1) +#endif + +#ifndef BCM_TransModeOutScen_Req_BCM_StyleCmd3__No_changes +#define BCM_TransModeOutScen_Req_BCM_StyleCmd3__No_changes (0) +#endif + +// signal: @BCM_StartStopPlayTime_Req_ro +#define CANDB_BCM_StartStopPlayTime_Req_ro_CovFactor (100) +#define CANDB_BCM_StartStopPlayTime_Req_ro_toS(x) ( (uint8_t) ((x) / (100)) ) +#define CANDB_BCM_StartStopPlayTime_Req_ro_fromS(x) ( ((x) * (100)) ) + +// Value tables for @BCM_Factorpurpose_Stat signal + +#ifndef BCM_Factorpurpose_Stat_BCM_StyleCmd3__2_Function +#define BCM_Factorpurpose_Stat_BCM_StyleCmd3__2_Function (2) +#endif + +#ifndef BCM_Factorpurpose_Stat_BCM_StyleCmd3__1_Function +#define BCM_Factorpurpose_Stat_BCM_StyleCmd3__1_Function (1) +#endif + +#ifndef BCM_Factorpurpose_Stat_BCM_StyleCmd3__No_changes_ +#define BCM_Factorpurpose_Stat_BCM_StyleCmd3__No_changes_ (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Scenario part pick (start, end or both of them) + // 3 : " End place" + // 2 : " Start place" + // 1 : " All places" + // 0 : " No changes" + uint8_t BCM_PlaceToPlay_Req : 2; // Bits= 2 + + // Transition of scenario: rough transition via rise/fall, smooth transition via rise/fall, strip fill with brightness rise/fall, etc. + // 13 : " Reserved" + // 12 : " Reserved" + // 11 : " Reserved" + // 10 : " Reserved" + // 9 : " Reserved" + // 8 : " Reserved" + // 7 : " Reserved" + // 6 : " Reserved" + // 5 : " Reserved" + // 14 : " Reserved" + // 15 : " Reserved" + // 4 : " Smooth strip fill with brightness tail" + // 3 : " Smooth strip fill" + // 2 : " Smooth transition" + // 1 : " Rough transition" + // 0 : " No changes" + uint8_t BCM_TransModeOutScen_Req : 5; // Bits= 5 + + // Play time for rise and fall + uint8_t BCM_StartStopPlayTime_Req_ro : 5; // Bits= 5 Factor= 100 Unit:'ms' + +#ifdef CANDB_USE_SIGFLOAT + uint16_t BCM_StartStopPlayTime_Req_phys; +#endif // CANDB_USE_SIGFLOAT + + // Module functions to set factors + // 2 : " 2 Function" + // 1 : " 1 Function" + // 0 : " No changes " + uint8_t BCM_Factorpurpose_Stat : 2; // Bits= 2 + + // Value of A factor + uint8_t BCM_FactorFunction_A_Val; // Bits= 8 + + // Value of B factor + uint8_t BCM_FactorFunction_B_Val; // Bits= 8 + + // Value of C factor + uint8_t BCM_FactorFunction_C_Val; // Bits= 8 + + // Reserved + uint8_t BCM_Reserved6; // Bits= 8 + + // Reserved + uint8_t BCM_Reserved7; // Bits= 8 + + // Reserved + uint8_t BCM_Reserved8; // Bits= 8 + + // Reserved + uint8_t BCM_Reserved9 : 1; // Bits= 1 + +#else + + // Scenario part pick (start, end or both of them) + // 3 : " End place" + // 2 : " Start place" + // 1 : " All places" + // 0 : " No changes" + uint8_t BCM_PlaceToPlay_Req; // Bits= 2 + + // Transition of scenario: rough transition via rise/fall, smooth transition via rise/fall, strip fill with brightness rise/fall, etc. + // 13 : " Reserved" + // 12 : " Reserved" + // 11 : " Reserved" + // 10 : " Reserved" + // 9 : " Reserved" + // 8 : " Reserved" + // 7 : " Reserved" + // 6 : " Reserved" + // 5 : " Reserved" + // 14 : " Reserved" + // 15 : " Reserved" + // 4 : " Smooth strip fill with brightness tail" + // 3 : " Smooth strip fill" + // 2 : " Smooth transition" + // 1 : " Rough transition" + // 0 : " No changes" + uint8_t BCM_TransModeOutScen_Req; // Bits= 5 + + // Play time for rise and fall + uint8_t BCM_StartStopPlayTime_Req_ro; // Bits= 5 Factor= 100 Unit:'ms' + +#ifdef CANDB_USE_SIGFLOAT + uint16_t BCM_StartStopPlayTime_Req_phys; +#endif // CANDB_USE_SIGFLOAT + + // Module functions to set factors + // 2 : " 2 Function" + // 1 : " 1 Function" + // 0 : " No changes " + uint8_t BCM_Factorpurpose_Stat; // Bits= 2 + + // Value of A factor + uint8_t BCM_FactorFunction_A_Val; // Bits= 8 + + // Value of B factor + uint8_t BCM_FactorFunction_B_Val; // Bits= 8 + + // Value of C factor + uint8_t BCM_FactorFunction_C_Val; // Bits= 8 + + // Reserved + uint8_t BCM_Reserved6; // Bits= 8 + + // Reserved + uint8_t BCM_Reserved7; // Bits= 8 + + // Reserved + uint8_t BCM_Reserved8; // Bits= 8 + + // Reserved + uint8_t BCM_Reserved9; // Bits= 1 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} BCM_StyleCmd3_t; + +// def @BCM_WHF_Request CAN Message (1448 0x5a8) +#define BCM_WHF_Request_IDE (0U) +#define BCM_WHF_Request_DLC (1U) +#define BCM_WHF_Request_CANID (0x5a8U) +#define BCM_WHF_Request_CYC (250U) + +// Value tables for @BCM_PowerWHF_Req signal + +#ifndef BCM_PowerWHF_Req_BCM_WHF_Request_ +#define BCM_PowerWHF_Req_BCM_WHF_Request_ (4) +#endif + +#ifndef BCM_PowerWHF_Req_BCM_WHF_Request_ +#define BCM_PowerWHF_Req_BCM_WHF_Request_ (3) +#endif + +#ifndef BCM_PowerWHF_Req_BCM_WHF_Request_ +#define BCM_PowerWHF_Req_BCM_WHF_Request_ (2) +#endif + +#ifndef BCM_PowerWHF_Req_BCM_WHF_Request_ +#define BCM_PowerWHF_Req_BCM_WHF_Request_ (1) +#endif + +#ifndef BCM_PowerWHF_Req_BCM_WHF_Request_Window_heater_inactive +#define BCM_PowerWHF_Req_BCM_WHF_Request_Window_heater_inactive (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Selection Front Left/Right Window Heating EMS mode state + // 4 : "100%" + // 3 : "75%" + // 2 : "50%" + // 1 : "25%" + // 0 : "Window heater inactive" + uint8_t BCM_PowerWHF_Req : 3; // Bits= 3 + +#else + + // Selection Front Left/Right Window Heating EMS mode state + // 4 : "100%" + // 3 : "75%" + // 2 : "50%" + // 1 : "25%" + // 0 : "Window heater inactive" + uint8_t BCM_PowerWHF_Req; // Bits= 3 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} BCM_WHF_Request_t; + +// def @IC_DISPLAY_CLOCK CAN Message (1450 0x5aa) +#define IC_DISPLAY_CLOCK_IDE (0U) +#define IC_DISPLAY_CLOCK_DLC (8U) +#define IC_DISPLAY_CLOCK_CANID (0x5aaU) +#define IC_DISPLAY_CLOCK_CYC (1000U) +// signal: @IC_Year_ro +#define CANDB_IC_Year_ro_CovFactor (1) +#define CANDB_IC_Year_ro_toS(x) ( (uint8_t) ((x) - (2000)) ) +#define CANDB_IC_Year_ro_fromS(x) ( ((x) + (2000)) ) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Indicates the year to be displayed + uint8_t IC_Year_ro : 7; // Bits= 7 Offset= 2000 + +#ifdef CANDB_USE_SIGFLOAT + uint16_t IC_Year_phys; +#endif // CANDB_USE_SIGFLOAT + + // Indicates the month to be displayed + uint8_t IC_Month : 4; // Bits= 4 + + // Indicates the day to be displayed + uint8_t IC_Day : 5; // Bits= 5 + + // Indicates the hour to be displayed + uint8_t IC_Hour : 5; // Bits= 5 Unit:'h' + + // Indicates the minute to be displayed + uint8_t IC_Minute : 6; // Bits= 6 Unit:'min' + + // Indicates the second to be displayed + uint8_t IC_Second : 6; // Bits= 6 Unit:'s' + +#else + + // Indicates the year to be displayed + uint8_t IC_Year_ro; // Bits= 7 Offset= 2000 + +#ifdef CANDB_USE_SIGFLOAT + uint16_t IC_Year_phys; +#endif // CANDB_USE_SIGFLOAT + + // Indicates the month to be displayed + uint8_t IC_Month; // Bits= 4 + + // Indicates the day to be displayed + uint8_t IC_Day; // Bits= 5 + + // Indicates the hour to be displayed + uint8_t IC_Hour; // Bits= 5 Unit:'h' + + // Indicates the minute to be displayed + uint8_t IC_Minute; // Bits= 6 Unit:'min' + + // Indicates the second to be displayed + uint8_t IC_Second; // Bits= 6 Unit:'s' + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} IC_DISPLAY_CLOCK_t; + +// def @BCM_UserConfig_Stat CAN Message (1452 0x5ac) +#define BCM_UserConfig_Stat_IDE (0U) +#define BCM_UserConfig_Stat_DLC (8U) +#define BCM_UserConfig_Stat_CANID (0x5acU) +#define BCM_UserConfig_Stat_CYC (500U) + +// Value tables for @BCM_StyleIllTheme_Stat signal + +#ifndef BCM_StyleIllTheme_Stat_BCM_UserConfig_Stat_Color_theme_16 +#define BCM_StyleIllTheme_Stat_BCM_UserConfig_Stat_Color_theme_16 (15) +#endif + +#ifndef BCM_StyleIllTheme_Stat_BCM_UserConfig_Stat_Color_theme_15 +#define BCM_StyleIllTheme_Stat_BCM_UserConfig_Stat_Color_theme_15 (14) +#endif + +#ifndef BCM_StyleIllTheme_Stat_BCM_UserConfig_Stat_Color_theme_14 +#define BCM_StyleIllTheme_Stat_BCM_UserConfig_Stat_Color_theme_14 (13) +#endif + +#ifndef BCM_StyleIllTheme_Stat_BCM_UserConfig_Stat_Color_theme_13 +#define BCM_StyleIllTheme_Stat_BCM_UserConfig_Stat_Color_theme_13 (12) +#endif + +#ifndef BCM_StyleIllTheme_Stat_BCM_UserConfig_Stat_Color_theme_12 +#define BCM_StyleIllTheme_Stat_BCM_UserConfig_Stat_Color_theme_12 (11) +#endif + +#ifndef BCM_StyleIllTheme_Stat_BCM_UserConfig_Stat_Color_theme_11 +#define BCM_StyleIllTheme_Stat_BCM_UserConfig_Stat_Color_theme_11 (10) +#endif + +#ifndef BCM_StyleIllTheme_Stat_BCM_UserConfig_Stat_Color_theme_10 +#define BCM_StyleIllTheme_Stat_BCM_UserConfig_Stat_Color_theme_10 (9) +#endif + +#ifndef BCM_StyleIllTheme_Stat_BCM_UserConfig_Stat_Color_theme_9 +#define BCM_StyleIllTheme_Stat_BCM_UserConfig_Stat_Color_theme_9 (8) +#endif + +#ifndef BCM_StyleIllTheme_Stat_BCM_UserConfig_Stat_Reserved +#define BCM_StyleIllTheme_Stat_BCM_UserConfig_Stat_Reserved (7) +#endif + +#ifndef BCM_StyleIllTheme_Stat_BCM_UserConfig_Stat_Color_theme_7 +#define BCM_StyleIllTheme_Stat_BCM_UserConfig_Stat_Color_theme_7 (6) +#endif + +#ifndef BCM_StyleIllTheme_Stat_BCM_UserConfig_Stat_Color_theme_6 +#define BCM_StyleIllTheme_Stat_BCM_UserConfig_Stat_Color_theme_6 (5) +#endif + +#ifndef BCM_StyleIllTheme_Stat_BCM_UserConfig_Stat_Color_theme_5 +#define BCM_StyleIllTheme_Stat_BCM_UserConfig_Stat_Color_theme_5 (4) +#endif + +#ifndef BCM_StyleIllTheme_Stat_BCM_UserConfig_Stat_Color_theme_4 +#define BCM_StyleIllTheme_Stat_BCM_UserConfig_Stat_Color_theme_4 (3) +#endif + +#ifndef BCM_StyleIllTheme_Stat_BCM_UserConfig_Stat_Color_theme_3 +#define BCM_StyleIllTheme_Stat_BCM_UserConfig_Stat_Color_theme_3 (2) +#endif + +#ifndef BCM_StyleIllTheme_Stat_BCM_UserConfig_Stat_Color_theme_2 +#define BCM_StyleIllTheme_Stat_BCM_UserConfig_Stat_Color_theme_2 (1) +#endif + +#ifndef BCM_StyleIllTheme_Stat_BCM_UserConfig_Stat_Color_theme_1 +#define BCM_StyleIllTheme_Stat_BCM_UserConfig_Stat_Color_theme_1 (0) +#endif + + +// Value tables for @BCM_ConfCamera_Stat signal + +#ifndef BCM_ConfCamera_Stat_BCM_UserConfig_Stat_Error_state +#define BCM_ConfCamera_Stat_BCM_UserConfig_Stat_Error_state (3) +#endif + +#ifndef BCM_ConfCamera_Stat_BCM_UserConfig_Stat_Intermediate_position +#define BCM_ConfCamera_Stat_BCM_UserConfig_Stat_Intermediate_position (2) +#endif + +#ifndef BCM_ConfCamera_Stat_BCM_UserConfig_Stat_Opened_active +#define BCM_ConfCamera_Stat_BCM_UserConfig_Stat_Opened_active (1) +#endif + +#ifndef BCM_ConfCamera_Stat_BCM_UserConfig_Stat_Closed_inactive +#define BCM_ConfCamera_Stat_BCM_UserConfig_Stat_Closed_inactive (0) +#endif + + +// Value tables for @BCM_FIU_UserNotification_Stat signal + +#ifndef BCM_FIU_UserNotification_Stat_BCM_UserConfig_Stat_Low_Level_Battery_notification +#define BCM_FIU_UserNotification_Stat_BCM_UserConfig_Stat_Low_Level_Battery_notification (2) +#endif + +#ifndef BCM_FIU_UserNotification_Stat_BCM_UserConfig_Stat_FIU_turns_OFF_notification +#define BCM_FIU_UserNotification_Stat_BCM_UserConfig_Stat_FIU_turns_OFF_notification (1) +#endif + +#ifndef BCM_FIU_UserNotification_Stat_BCM_UserConfig_Stat_No_notification +#define BCM_FIU_UserNotification_Stat_BCM_UserConfig_Stat_No_notification (0) +#endif + + +// Value tables for @BCM_StyleIllGlobal_Stat signal + +#ifndef BCM_StyleIllGlobal_Stat_BCM_UserConfig_Stat_Function_active +#define BCM_StyleIllGlobal_Stat_BCM_UserConfig_Stat_Function_active (1) +#endif + +#ifndef BCM_StyleIllGlobal_Stat_BCM_UserConfig_Stat_Function_inactive +#define BCM_StyleIllGlobal_Stat_BCM_UserConfig_Stat_Function_inactive (0) +#endif + + +// Value tables for @BCM_ApproachAccess_Stat signal + +#ifndef BCM_ApproachAccess_Stat_BCM_UserConfig_Stat_Function_inactive +#define BCM_ApproachAccess_Stat_BCM_UserConfig_Stat_Function_inactive (0) +#endif + +#ifndef BCM_ApproachAccess_Stat_BCM_UserConfig_Stat_Function_active +#define BCM_ApproachAccess_Stat_BCM_UserConfig_Stat_Function_active (1) +#endif + + +// Value tables for @BCM_UnlockAfterDrive_Stat signal + +#ifndef BCM_UnlockAfterDrive_Stat_BCM_UserConfig_Stat_Function_inactive +#define BCM_UnlockAfterDrive_Stat_BCM_UserConfig_Stat_Function_inactive (0) +#endif + +#ifndef BCM_UnlockAfterDrive_Stat_BCM_UserConfig_Stat_Function_active +#define BCM_UnlockAfterDrive_Stat_BCM_UserConfig_Stat_Function_active (1) +#endif + + +// Value tables for @BCM_UnlockExternal_Stat signal + +#ifndef BCM_UnlockExternal_Stat_BCM_UserConfig_Stat_Function_inactive +#define BCM_UnlockExternal_Stat_BCM_UserConfig_Stat_Function_inactive (0) +#endif + +#ifndef BCM_UnlockExternal_Stat_BCM_UserConfig_Stat_Function_active +#define BCM_UnlockExternal_Stat_BCM_UserConfig_Stat_Function_active (1) +#endif + + +// Value tables for @BCM_UnlockInternal_Stat signal + +#ifndef BCM_UnlockInternal_Stat_BCM_UserConfig_Stat_Function_inactive +#define BCM_UnlockInternal_Stat_BCM_UserConfig_Stat_Function_inactive (0) +#endif + +#ifndef BCM_UnlockInternal_Stat_BCM_UserConfig_Stat_Function_active +#define BCM_UnlockInternal_Stat_BCM_UserConfig_Stat_Function_active (1) +#endif + + +// Value tables for @BCM_DoorsDriveLock_Stat signal + +#ifndef BCM_DoorsDriveLock_Stat_BCM_UserConfig_Stat_Function_inactive +#define BCM_DoorsDriveLock_Stat_BCM_UserConfig_Stat_Function_inactive (0) +#endif + +#ifndef BCM_DoorsDriveLock_Stat_BCM_UserConfig_Stat_Function_active +#define BCM_DoorsDriveLock_Stat_BCM_UserConfig_Stat_Function_active (1) +#endif + + +// Value tables for @BCM_TrafficSide_Stat signal + +#ifndef BCM_TrafficSide_Stat_BCM_UserConfig_Stat_RightHand +#define BCM_TrafficSide_Stat_BCM_UserConfig_Stat_RightHand (1) +#endif + +#ifndef BCM_TrafficSide_Stat_BCM_UserConfig_Stat_LeftHand +#define BCM_TrafficSide_Stat_BCM_UserConfig_Stat_LeftHand (0) +#endif + + +// Value tables for @BCM_WelcomeLeavingLight_Stat signal + +#ifndef BCM_WelcomeLeavingLight_Stat_BCM_UserConfig_Stat_Inactive +#define BCM_WelcomeLeavingLight_Stat_BCM_UserConfig_Stat_Inactive (0) +#endif + +#ifndef BCM_WelcomeLeavingLight_Stat_BCM_UserConfig_Stat_Active +#define BCM_WelcomeLeavingLight_Stat_BCM_UserConfig_Stat_Active (1) +#endif + + +// Value tables for @BCM_WelcomeLightAnimation_Stat signal + +#ifndef BCM_WelcomeLightAnimation_Stat_BCM_UserConfig_Stat_Inactive +#define BCM_WelcomeLightAnimation_Stat_BCM_UserConfig_Stat_Inactive (0) +#endif + +#ifndef BCM_WelcomeLightAnimation_Stat_BCM_UserConfig_Stat_Active +#define BCM_WelcomeLightAnimation_Stat_BCM_UserConfig_Stat_Active (1) +#endif + + +// Value tables for @BCM_ArmrestHeatFL_Stat signal + +#ifndef BCM_ArmrestHeatFL_Stat_BCM_UserConfig_Stat_Inactive +#define BCM_ArmrestHeatFL_Stat_BCM_UserConfig_Stat_Inactive (0) +#endif + +#ifndef BCM_ArmrestHeatFL_Stat_BCM_UserConfig_Stat_Active +#define BCM_ArmrestHeatFL_Stat_BCM_UserConfig_Stat_Active (1) +#endif + + +// Value tables for @BCM_ArmrestHeatFR_Stat signal + +#ifndef BCM_ArmrestHeatFR_Stat_BCM_UserConfig_Stat_Inactive +#define BCM_ArmrestHeatFR_Stat_BCM_UserConfig_Stat_Inactive (0) +#endif + +#ifndef BCM_ArmrestHeatFR_Stat_BCM_UserConfig_Stat_Active +#define BCM_ArmrestHeatFR_Stat_BCM_UserConfig_Stat_Active (1) +#endif + + +// Value tables for @BCM_ArmrestHeatRL_Stat signal + +#ifndef BCM_ArmrestHeatRL_Stat_BCM_UserConfig_Stat_Inactive +#define BCM_ArmrestHeatRL_Stat_BCM_UserConfig_Stat_Inactive (0) +#endif + +#ifndef BCM_ArmrestHeatRL_Stat_BCM_UserConfig_Stat_Active +#define BCM_ArmrestHeatRL_Stat_BCM_UserConfig_Stat_Active (1) +#endif + + +// Value tables for @BCM_ArmrestHeatRR_Stat signal + +#ifndef BCM_ArmrestHeatRR_Stat_BCM_UserConfig_Stat_Inactive +#define BCM_ArmrestHeatRR_Stat_BCM_UserConfig_Stat_Inactive (0) +#endif + +#ifndef BCM_ArmrestHeatRR_Stat_BCM_UserConfig_Stat_Active +#define BCM_ArmrestHeatRR_Stat_BCM_UserConfig_Stat_Active (1) +#endif + + +// Value tables for @BCM_WelcomeLeavingLightTime_Stat signal + +#ifndef BCM_WelcomeLeavingLightTime_Stat_BCM_UserConfig_Stat_Function_active_for_time_15_sec +#define BCM_WelcomeLeavingLightTime_Stat_BCM_UserConfig_Stat_Function_active_for_time_15_sec (0) +#endif + +#ifndef BCM_WelcomeLeavingLightTime_Stat_BCM_UserConfig_Stat_Function_active_for_time_30_sec +#define BCM_WelcomeLeavingLightTime_Stat_BCM_UserConfig_Stat_Function_active_for_time_30_sec (1) +#endif + +#ifndef BCM_WelcomeLeavingLightTime_Stat_BCM_UserConfig_Stat_Function_active_for_time_45_sec +#define BCM_WelcomeLeavingLightTime_Stat_BCM_UserConfig_Stat_Function_active_for_time_45_sec (2) +#endif + +#ifndef BCM_WelcomeLeavingLightTime_Stat_BCM_UserConfig_Stat_Function_active_for_time_60_sec +#define BCM_WelcomeLeavingLightTime_Stat_BCM_UserConfig_Stat_Function_active_for_time_60_sec (3) +#endif + + +// Value tables for @BCM_HeadlightWashing_Stat signal + +#ifndef BCM_HeadlightWashing_Stat_BCM_UserConfig_Stat_Inactive +#define BCM_HeadlightWashing_Stat_BCM_UserConfig_Stat_Inactive (0) +#endif + +#ifndef BCM_HeadlightWashing_Stat_BCM_UserConfig_Stat_Active +#define BCM_HeadlightWashing_Stat_BCM_UserConfig_Stat_Active (1) +#endif + + +// Value tables for @BCM_MirrorsAutoFold_Stat signal + +#ifndef BCM_MirrorsAutoFold_Stat_BCM_UserConfig_Stat_Inactive +#define BCM_MirrorsAutoFold_Stat_BCM_UserConfig_Stat_Inactive (0) +#endif + +#ifndef BCM_MirrorsAutoFold_Stat_BCM_UserConfig_Stat_Active +#define BCM_MirrorsAutoFold_Stat_BCM_UserConfig_Stat_Active (1) +#endif + + +// Value tables for @BCM_MirrorsAutoTilt_Stat signal + +#ifndef BCM_MirrorsAutoTilt_Stat_BCM_UserConfig_Stat_Inactive +#define BCM_MirrorsAutoTilt_Stat_BCM_UserConfig_Stat_Inactive (0) +#endif + +#ifndef BCM_MirrorsAutoTilt_Stat_BCM_UserConfig_Stat_Active +#define BCM_MirrorsAutoTilt_Stat_BCM_UserConfig_Stat_Active (1) +#endif + + +// Value tables for @BCM_WindowsRainClosing_Stat signal + +#ifndef BCM_WindowsRainClosing_Stat_BCM_UserConfig_Stat_Inactive +#define BCM_WindowsRainClosing_Stat_BCM_UserConfig_Stat_Inactive (0) +#endif + +#ifndef BCM_WindowsRainClosing_Stat_BCM_UserConfig_Stat_Active +#define BCM_WindowsRainClosing_Stat_BCM_UserConfig_Stat_Active (1) +#endif + + +// Value tables for @BCM_AudibleLockFdBack_Stat signal + +#ifndef BCM_AudibleLockFdBack_Stat_BCM_UserConfig_Stat_Inactive +#define BCM_AudibleLockFdBack_Stat_BCM_UserConfig_Stat_Inactive (0) +#endif + +#ifndef BCM_AudibleLockFdBack_Stat_BCM_UserConfig_Stat_Active +#define BCM_AudibleLockFdBack_Stat_BCM_UserConfig_Stat_Active (1) +#endif + + +// Value tables for @BCM_AutoWiper_Stat signal + +#ifndef BCM_AutoWiper_Stat_BCM_UserConfig_Stat_Inactive +#define BCM_AutoWiper_Stat_BCM_UserConfig_Stat_Inactive (0) +#endif + +#ifndef BCM_AutoWiper_Stat_BCM_UserConfig_Stat_Active +#define BCM_AutoWiper_Stat_BCM_UserConfig_Stat_Active (1) +#endif + + +// Value tables for @BCM_TrnkDoorCloseBySpeed_Stat signal + +#ifndef BCM_TrnkDoorCloseBySpeed_Stat_BCM_UserConfig_Stat_Inactive +#define BCM_TrnkDoorCloseBySpeed_Stat_BCM_UserConfig_Stat_Inactive (0) +#endif + +#ifndef BCM_TrnkDoorCloseBySpeed_Stat_BCM_UserConfig_Stat_Active +#define BCM_TrnkDoorCloseBySpeed_Stat_BCM_UserConfig_Stat_Active (1) +#endif + + +// Value tables for @BCM_RunningBoards_Stat signal + +#ifndef BCM_RunningBoards_Stat_BCM_UserConfig_Stat_Auto +#define BCM_RunningBoards_Stat_BCM_UserConfig_Stat_Auto (0) +#endif + +#ifndef BCM_RunningBoards_Stat_BCM_UserConfig_Stat_Folded +#define BCM_RunningBoards_Stat_BCM_UserConfig_Stat_Folded (1) +#endif + +#ifndef BCM_RunningBoards_Stat_BCM_UserConfig_Stat_Unfolded +#define BCM_RunningBoards_Stat_BCM_UserConfig_Stat_Unfolded (2) +#endif + + +// Value tables for @BCM_SteeringWheelAutoHeat_Stat signal + +#ifndef BCM_SteeringWheelAutoHeat_Stat_BCM_UserConfig_Stat_Inactive +#define BCM_SteeringWheelAutoHeat_Stat_BCM_UserConfig_Stat_Inactive (0) +#endif + +#ifndef BCM_SteeringWheelAutoHeat_Stat_BCM_UserConfig_Stat_Active +#define BCM_SteeringWheelAutoHeat_Stat_BCM_UserConfig_Stat_Active (1) +#endif + + +// Value tables for @BCM_Ultraviolet_Stat signal + +#ifndef BCM_Ultraviolet_Stat_BCM_UserConfig_Stat_Function_Active +#define BCM_Ultraviolet_Stat_BCM_UserConfig_Stat_Function_Active (1) +#endif + +#ifndef BCM_Ultraviolet_Stat_BCM_UserConfig_Stat_Function_Inactive +#define BCM_Ultraviolet_Stat_BCM_UserConfig_Stat_Function_Inactive (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Color theme presets for style illumination + // 15 : "Color theme 16" + // 14 : "Color theme 15" + // 13 : "Color theme 14" + // 12 : "Color theme 13" + // 11 : "Color theme 12" + // 10 : "Color theme 11" + // 9 : "Color theme 10" + // 8 : "Color theme 9" + // 7 : "Reserved" + // 6 : "Color theme 7" + // 5 : "Color theme 6" + // 4 : "Color theme 5" + // 3 : "Color theme 4" + // 2 : "Color theme 3" + // 1 : "Color theme 2" + // 0 : "Color theme 1" + uint8_t BCM_StyleIllTheme_Stat : 4; // Bits= 4 + + // Current state signal of the camera electric drive + // 3 : "Error state" + // 2 : "Intermediate position" + // 1 : "Opened (active)" + // 0 : "Closed (inactive)" + uint8_t BCM_ConfCamera_Stat : 2; // Bits= 2 + + // Flag from BCM to notify the user 1 min. before the planned shutdown + // 2 : "Low Level Battery notification" + // 1 : "FIU turns OFF notification" + // 0 : "No notification" + uint8_t BCM_FIU_UserNotification_Stat : 2; // Bits= 2 + + // Style illumination brightness % + uint8_t BCM_StyleIllBright_Val : 7; // Bits= 7 Unit:'%' + + // Style illumination global ON/OFF + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t BCM_StyleIllGlobal_Stat : 1; // Bits= 1 + + // Automatic doors lock, when user leaves vehicle + // Automatic doors unlock, when user approaches to vehicle + // 0 : "Function inactive" + // 1 : "Function active" + uint8_t BCM_ApproachAccess_Stat : 1; // Bits= 1 + + // Doors automatically unlocking after drive (selector in P position, ignition off) + // 0 : "Function inactive" + // 1 : "Function active" + uint8_t BCM_UnlockAfterDrive_Stat : 1; // Bits= 1 + + // 0x0: when external unlock request received at 1st time all doors shall unlock + // 0x1: when external unlock request received at 1st time only driver's door shall unlock, at 2nd time all doors shall unlock + // 0 : "Function inactive" + // 1 : "Function active" + uint8_t BCM_UnlockExternal_Stat : 1; // Bits= 1 + + // 0x0: when requesting to open a door through the internal front door handle, all doors shall unlock + // 0x1: when requesting to open a door through the internal front door handle, only own door shall unlock + // 0 : "Function inactive" + // 1 : "Function active" + uint8_t BCM_UnlockInternal_Stat : 1; // Bits= 1 + + // Doors automatically locking when driving (speed above threshold) + // 0 : "Function inactive" + // 1 : "Function active" + uint8_t BCM_DoorsDriveLock_Stat : 1; // Bits= 1 + + // Selected road traffic side + // 1 : "Right-Hand" + // 0 : "Left-Hand" + uint8_t BCM_TrafficSide_Stat : 1; // Bits= 1 + + // Welcome and leaving light function enable status + // 0 : "Inactive" + // 1 : "Active" + uint8_t BCM_WelcomeLeavingLight_Stat : 1; // Bits= 1 + + // Welcome headlight animation enable + // 0 : "Inactive" + // 1 : "Active" + uint8_t BCM_WelcomeLightAnimation_Stat : 1; // Bits= 1 + + // Armrest heating FL function status + // 0 : "Inactive" + // 1 : "Active" + uint8_t BCM_ArmrestHeatFL_Stat : 1; // Bits= 1 + + // Armrest heating FR function status + // 0 : "Inactive" + // 1 : "Active" + uint8_t BCM_ArmrestHeatFR_Stat : 1; // Bits= 1 + + // Armrest heating RL function status + // 0 : "Inactive" + // 1 : "Active" + uint8_t BCM_ArmrestHeatRL_Stat : 1; // Bits= 1 + + // Armrest heating RR function status + // 0 : "Inactive" + // 1 : "Active" + uint8_t BCM_ArmrestHeatRR_Stat : 1; // Bits= 1 + + // Welcome and leaving light working time + // 0 : "Function active for time 15 sec" + // 1 : "Function active for time 30 sec" + // 2 : "Function active for time 45 sec" + // 3 : "Function active for time 60 sec" + uint8_t BCM_WelcomeLeavingLightTime_Stat : 2; // Bits= 2 + + // AUTO washing headlights together with windshield + // 0 : "Inactive" + // 1 : "Active" + uint8_t BCM_HeadlightWashing_Stat : 1; // Bits= 1 + + // Auto folding mirrors when secure lock action + // 0 : "Inactive" + // 1 : "Active" + uint8_t BCM_MirrorsAutoFold_Stat : 1; // Bits= 1 + + // When R gear is active mirrors are bend over + // 0 : "Inactive" + // 1 : "Active" + uint8_t BCM_MirrorsAutoTilt_Stat : 1; // Bits= 1 + + // Windows automatically closing when it rains + // 0 : "Inactive" + // 1 : "Active" + uint8_t BCM_WindowsRainClosing_Stat : 1; // Bits= 1 + + // Vehicle locking/unlocking sound enable function + // 0 : "Inactive" + // 1 : "Active" + uint8_t BCM_AudibleLockFdBack_Stat : 1; // Bits= 1 + + // Auto wipering windshield by RLS sensor signals + // 0 : "Inactive" + // 1 : "Active" + uint8_t BCM_AutoWiper_Stat : 1; // Bits= 1 + + // Trunk automatically closing when driving (speed above threshhold) + // 0 : "Inactive" + // 1 : "Active" + uint8_t BCM_TrnkDoorCloseBySpeed_Stat : 1; // Bits= 1 + + // Thresholds status: 0x0 - thresholds shall be automatic 0x1 - threshholds shall be alwasys fold 0x2 - thresholds shall be always unfold + // 0 : "Auto" + // 1 : "Folded" + // 2 : "Unfolded" + uint8_t BCM_RunningBoards_Stat : 2; // Bits= 2 + + // Automatically steering wheel heating + // 0 : "Inactive" + // 1 : "Active" + uint8_t BCM_SteeringWheelAutoHeat_Stat : 1; // Bits= 1 + + // The signal displays the status of the user turning on the ultraviolet irradiation function of the cabin after leaving it + // 1 : "Function Active" + // 0 : "Function Inactive" + uint8_t BCM_Ultraviolet_Stat : 1; // Bits= 1 + +#else + + // Color theme presets for style illumination + // 15 : "Color theme 16" + // 14 : "Color theme 15" + // 13 : "Color theme 14" + // 12 : "Color theme 13" + // 11 : "Color theme 12" + // 10 : "Color theme 11" + // 9 : "Color theme 10" + // 8 : "Color theme 9" + // 7 : "Reserved" + // 6 : "Color theme 7" + // 5 : "Color theme 6" + // 4 : "Color theme 5" + // 3 : "Color theme 4" + // 2 : "Color theme 3" + // 1 : "Color theme 2" + // 0 : "Color theme 1" + uint8_t BCM_StyleIllTheme_Stat; // Bits= 4 + + // Current state signal of the camera electric drive + // 3 : "Error state" + // 2 : "Intermediate position" + // 1 : "Opened (active)" + // 0 : "Closed (inactive)" + uint8_t BCM_ConfCamera_Stat; // Bits= 2 + + // Flag from BCM to notify the user 1 min. before the planned shutdown + // 2 : "Low Level Battery notification" + // 1 : "FIU turns OFF notification" + // 0 : "No notification" + uint8_t BCM_FIU_UserNotification_Stat; // Bits= 2 + + // Style illumination brightness % + uint8_t BCM_StyleIllBright_Val; // Bits= 7 Unit:'%' + + // Style illumination global ON/OFF + // 1 : "Function active" + // 0 : "Function inactive" + uint8_t BCM_StyleIllGlobal_Stat; // Bits= 1 + + // Automatic doors lock, when user leaves vehicle + // Automatic doors unlock, when user approaches to vehicle + // 0 : "Function inactive" + // 1 : "Function active" + uint8_t BCM_ApproachAccess_Stat; // Bits= 1 + + // Doors automatically unlocking after drive (selector in P position, ignition off) + // 0 : "Function inactive" + // 1 : "Function active" + uint8_t BCM_UnlockAfterDrive_Stat; // Bits= 1 + + // 0x0: when external unlock request received at 1st time all doors shall unlock + // 0x1: when external unlock request received at 1st time only driver's door shall unlock, at 2nd time all doors shall unlock + // 0 : "Function inactive" + // 1 : "Function active" + uint8_t BCM_UnlockExternal_Stat; // Bits= 1 + + // 0x0: when requesting to open a door through the internal front door handle, all doors shall unlock + // 0x1: when requesting to open a door through the internal front door handle, only own door shall unlock + // 0 : "Function inactive" + // 1 : "Function active" + uint8_t BCM_UnlockInternal_Stat; // Bits= 1 + + // Doors automatically locking when driving (speed above threshold) + // 0 : "Function inactive" + // 1 : "Function active" + uint8_t BCM_DoorsDriveLock_Stat; // Bits= 1 + + // Selected road traffic side + // 1 : "Right-Hand" + // 0 : "Left-Hand" + uint8_t BCM_TrafficSide_Stat; // Bits= 1 + + // Welcome and leaving light function enable status + // 0 : "Inactive" + // 1 : "Active" + uint8_t BCM_WelcomeLeavingLight_Stat; // Bits= 1 + + // Welcome headlight animation enable + // 0 : "Inactive" + // 1 : "Active" + uint8_t BCM_WelcomeLightAnimation_Stat; // Bits= 1 + + // Armrest heating FL function status + // 0 : "Inactive" + // 1 : "Active" + uint8_t BCM_ArmrestHeatFL_Stat; // Bits= 1 + + // Armrest heating FR function status + // 0 : "Inactive" + // 1 : "Active" + uint8_t BCM_ArmrestHeatFR_Stat; // Bits= 1 + + // Armrest heating RL function status + // 0 : "Inactive" + // 1 : "Active" + uint8_t BCM_ArmrestHeatRL_Stat; // Bits= 1 + + // Armrest heating RR function status + // 0 : "Inactive" + // 1 : "Active" + uint8_t BCM_ArmrestHeatRR_Stat; // Bits= 1 + + // Welcome and leaving light working time + // 0 : "Function active for time 15 sec" + // 1 : "Function active for time 30 sec" + // 2 : "Function active for time 45 sec" + // 3 : "Function active for time 60 sec" + uint8_t BCM_WelcomeLeavingLightTime_Stat; // Bits= 2 + + // AUTO washing headlights together with windshield + // 0 : "Inactive" + // 1 : "Active" + uint8_t BCM_HeadlightWashing_Stat; // Bits= 1 + + // Auto folding mirrors when secure lock action + // 0 : "Inactive" + // 1 : "Active" + uint8_t BCM_MirrorsAutoFold_Stat; // Bits= 1 + + // When R gear is active mirrors are bend over + // 0 : "Inactive" + // 1 : "Active" + uint8_t BCM_MirrorsAutoTilt_Stat; // Bits= 1 + + // Windows automatically closing when it rains + // 0 : "Inactive" + // 1 : "Active" + uint8_t BCM_WindowsRainClosing_Stat; // Bits= 1 + + // Vehicle locking/unlocking sound enable function + // 0 : "Inactive" + // 1 : "Active" + uint8_t BCM_AudibleLockFdBack_Stat; // Bits= 1 + + // Auto wipering windshield by RLS sensor signals + // 0 : "Inactive" + // 1 : "Active" + uint8_t BCM_AutoWiper_Stat; // Bits= 1 + + // Trunk automatically closing when driving (speed above threshhold) + // 0 : "Inactive" + // 1 : "Active" + uint8_t BCM_TrnkDoorCloseBySpeed_Stat; // Bits= 1 + + // Thresholds status: 0x0 - thresholds shall be automatic 0x1 - threshholds shall be alwasys fold 0x2 - thresholds shall be always unfold + // 0 : "Auto" + // 1 : "Folded" + // 2 : "Unfolded" + uint8_t BCM_RunningBoards_Stat; // Bits= 2 + + // Automatically steering wheel heating + // 0 : "Inactive" + // 1 : "Active" + uint8_t BCM_SteeringWheelAutoHeat_Stat; // Bits= 1 + + // The signal displays the status of the user turning on the ultraviolet irradiation function of the cabin after leaving it + // 1 : "Function Active" + // 0 : "Function Inactive" + uint8_t BCM_Ultraviolet_Stat; // Bits= 1 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} BCM_UserConfig_Stat_t; + +// def @FIU_MAS_Main CAN Message (1453 0x5ad) +#define FIU_MAS_Main_IDE (0U) +#define FIU_MAS_Main_DLC (5U) +#define FIU_MAS_Main_CANID (0x5adU) +#define FIU_MAS_Main_CYC (100U) + +// Value tables for @FIU_AVM_Active_Req signal + +#ifndef FIU_AVM_Active_Req_FIU_MAS_Main_Requested +#define FIU_AVM_Active_Req_FIU_MAS_Main_Requested (1) +#endif + +#ifndef FIU_AVM_Active_Req_FIU_MAS_Main_Not_requested +#define FIU_AVM_Active_Req_FIU_MAS_Main_Not_requested (0) +#endif + + +// Value tables for @FIU_View_Req signal + +#ifndef FIU_View_Req_FIU_MAS_Main_Parking_view +#define FIU_View_Req_FIU_MAS_Main_Parking_view (7) +#endif + +#ifndef FIU_View_Req_FIU_MAS_Main_D_Free_View_Rotation +#define FIU_View_Req_FIU_MAS_Main_D_Free_View_Rotation (6) +#endif + +#ifndef FIU_View_Req_FIU_MAS_Main_D_Right +#define FIU_View_Req_FIU_MAS_Main_D_Right (5) +#endif + +#ifndef FIU_View_Req_FIU_MAS_Main_D_Left +#define FIU_View_Req_FIU_MAS_Main_D_Left (4) +#endif + +#ifndef FIU_View_Req_FIU_MAS_Main_D_Main_Rear_Top_View_GTA +#define FIU_View_Req_FIU_MAS_Main_D_Main_Rear_Top_View_GTA (3) +#endif + +#ifndef FIU_View_Req_FIU_MAS_Main_D_Rear +#define FIU_View_Req_FIU_MAS_Main_D_Rear (2) +#endif + +#ifndef FIU_View_Req_FIU_MAS_Main_D_Front +#define FIU_View_Req_FIU_MAS_Main_D_Front (1) +#endif + +#ifndef FIU_View_Req_FIU_MAS_Main_Not_requested +#define FIU_View_Req_FIU_MAS_Main_Not_requested (0) +#endif + + +// Value tables for @FIU_APAstartBtn_Req signal + +#ifndef FIU_APAstartBtn_Req_FIU_MAS_Main_Not_requested +#define FIU_APAstartBtn_Req_FIU_MAS_Main_Not_requested (0) +#endif + +#ifndef FIU_APAstartBtn_Req_FIU_MAS_Main_Requested +#define FIU_APAstartBtn_Req_FIU_MAS_Main_Requested (1) +#endif + + +// Value tables for @FIU_MAS_Mode_Req signal + +#ifndef FIU_MAS_Mode_Req_FIU_MAS_Main_APA +#define FIU_MAS_Mode_Req_FIU_MAS_Main_APA (2) +#endif + +#ifndef FIU_MAS_Mode_Req_FIU_MAS_Main_AVM +#define FIU_MAS_Mode_Req_FIU_MAS_Main_AVM (1) +#endif + +#ifndef FIU_MAS_Mode_Req_FIU_MAS_Main_No_change +#define FIU_MAS_Mode_Req_FIU_MAS_Main_No_change (0) +#endif + + +// Value tables for @FIU_Narrow_Mode_Stat signal + +#ifndef FIU_Narrow_Mode_Stat_FIU_MAS_Main_Narrow +#define FIU_Narrow_Mode_Stat_FIU_MAS_Main_Narrow (2) +#endif + +#ifndef FIU_Narrow_Mode_Stat_FIU_MAS_Main_Wide_full +#define FIU_Narrow_Mode_Stat_FIU_MAS_Main_Wide_full (1) +#endif + +#ifndef FIU_Narrow_Mode_Stat_FIU_MAS_Main_No_change +#define FIU_Narrow_Mode_Stat_FIU_MAS_Main_No_change (0) +#endif + + +// Value tables for @FIU_UltraSonicEnable_Stat signal + +#ifndef FIU_UltraSonicEnable_Stat_FIU_MAS_Main_Inactive +#define FIU_UltraSonicEnable_Stat_FIU_MAS_Main_Inactive (2) +#endif + +#ifndef FIU_UltraSonicEnable_Stat_FIU_MAS_Main_Active +#define FIU_UltraSonicEnable_Stat_FIU_MAS_Main_Active (1) +#endif + +#ifndef FIU_UltraSonicEnable_Stat_FIU_MAS_Main_No_change +#define FIU_UltraSonicEnable_Stat_FIU_MAS_Main_No_change (0) +#endif + + +// Value tables for @FIU_AutoAct_Stat signal + +#ifndef FIU_AutoAct_Stat_FIU_MAS_Main_Inactive +#define FIU_AutoAct_Stat_FIU_MAS_Main_Inactive (2) +#endif + +#ifndef FIU_AutoAct_Stat_FIU_MAS_Main_Active +#define FIU_AutoAct_Stat_FIU_MAS_Main_Active (1) +#endif + +#ifndef FIU_AutoAct_Stat_FIU_MAS_Main_No_change +#define FIU_AutoAct_Stat_FIU_MAS_Main_No_change (0) +#endif + + +// Value tables for @FIU_CurrentPath_Req signal + +#ifndef FIU_CurrentPath_Req_FIU_MAS_Main_No_selection +#define FIU_CurrentPath_Req_FIU_MAS_Main_No_selection (0) +#endif + +#ifndef FIU_CurrentPath_Req_FIU_MAS_Main_Front_parking +#define FIU_CurrentPath_Req_FIU_MAS_Main_Front_parking (1) +#endif + +#ifndef FIU_CurrentPath_Req_FIU_MAS_Main_Rear_parking +#define FIU_CurrentPath_Req_FIU_MAS_Main_Rear_parking (2) +#endif + + +// Value tables for @FIU_SDMmaster_Req signal + +#ifndef FIU_SDMmaster_Req_FIU_MAS_Main_Requested +#define FIU_SDMmaster_Req_FIU_MAS_Main_Requested (1) +#endif + +#ifndef FIU_SDMmaster_Req_FIU_MAS_Main_Not_requested +#define FIU_SDMmaster_Req_FIU_MAS_Main_Not_requested (0) +#endif + + +// Value tables for @FIU_SelectedPlace_Req signal + +#ifndef FIU_SelectedPlace_Req_FIU_MAS_Main_No_selection +#define FIU_SelectedPlace_Req_FIU_MAS_Main_No_selection (0) +#endif + +#ifndef FIU_SelectedPlace_Req_FIU_MAS_Main_Left_nearest_position +#define FIU_SelectedPlace_Req_FIU_MAS_Main_Left_nearest_position (1) +#endif + +#ifndef FIU_SelectedPlace_Req_FIU_MAS_Main_Left_near_position +#define FIU_SelectedPlace_Req_FIU_MAS_Main_Left_near_position (2) +#endif + +#ifndef FIU_SelectedPlace_Req_FIU_MAS_Main_Left_far_position +#define FIU_SelectedPlace_Req_FIU_MAS_Main_Left_far_position (3) +#endif + +#ifndef FIU_SelectedPlace_Req_FIU_MAS_Main_Right_nearest_position +#define FIU_SelectedPlace_Req_FIU_MAS_Main_Right_nearest_position (4) +#endif + +#ifndef FIU_SelectedPlace_Req_FIU_MAS_Main_Right_near_position +#define FIU_SelectedPlace_Req_FIU_MAS_Main_Right_near_position (5) +#endif + +#ifndef FIU_SelectedPlace_Req_FIU_MAS_Main_Right_far_position +#define FIU_SelectedPlace_Req_FIU_MAS_Main_Right_far_position (6) +#endif + + +// Value tables for @FIU_ContinueMove_Req signal + +#ifndef FIU_ContinueMove_Req_FIU_MAS_Main_Not_requested +#define FIU_ContinueMove_Req_FIU_MAS_Main_Not_requested (0) +#endif + +#ifndef FIU_ContinueMove_Req_FIU_MAS_Main_Requested +#define FIU_ContinueMove_Req_FIU_MAS_Main_Requested (1) +#endif + + +// Value tables for @FIU_StopAPA_Req signal + +#ifndef FIU_StopAPA_Req_FIU_MAS_Main_Not_requested +#define FIU_StopAPA_Req_FIU_MAS_Main_Not_requested (0) +#endif + +#ifndef FIU_StopAPA_Req_FIU_MAS_Main_Requested +#define FIU_StopAPA_Req_FIU_MAS_Main_Requested (1) +#endif + + +// Value tables for @FIU_SDMcom_Req signal + +#ifndef FIU_SDMcom_Req_FIU_MAS_Main_Requested +#define FIU_SDMcom_Req_FIU_MAS_Main_Requested (1) +#endif + +#ifndef FIU_SDMcom_Req_FIU_MAS_Main_Not_requested +#define FIU_SDMcom_Req_FIU_MAS_Main_Not_requested (0) +#endif + + +// Value tables for @FIU_FinishMove_Req signal + +#ifndef FIU_FinishMove_Req_FIU_MAS_Main_Requested +#define FIU_FinishMove_Req_FIU_MAS_Main_Requested (1) +#endif + +#ifndef FIU_FinishMove_Req_FIU_MAS_Main_Not_requested +#define FIU_FinishMove_Req_FIU_MAS_Main_Not_requested (0) +#endif + + +// Value tables for @FIU_ParkingOutPath_Req signal + +#ifndef FIU_ParkingOutPath_Req_FIU_MAS_Main_Backward_to_the_Right +#define FIU_ParkingOutPath_Req_FIU_MAS_Main_Backward_to_the_Right (6) +#endif + +#ifndef FIU_ParkingOutPath_Req_FIU_MAS_Main_Straight_backward +#define FIU_ParkingOutPath_Req_FIU_MAS_Main_Straight_backward (5) +#endif + +#ifndef FIU_ParkingOutPath_Req_FIU_MAS_Main_Backward_to_the_Left +#define FIU_ParkingOutPath_Req_FIU_MAS_Main_Backward_to_the_Left (4) +#endif + +#ifndef FIU_ParkingOutPath_Req_FIU_MAS_Main_Forward_to_the_Right +#define FIU_ParkingOutPath_Req_FIU_MAS_Main_Forward_to_the_Right (3) +#endif + +#ifndef FIU_ParkingOutPath_Req_FIU_MAS_Main_Straight_forward +#define FIU_ParkingOutPath_Req_FIU_MAS_Main_Straight_forward (2) +#endif + +#ifndef FIU_ParkingOutPath_Req_FIU_MAS_Main_Forward_to_the_Left +#define FIU_ParkingOutPath_Req_FIU_MAS_Main_Forward_to_the_Left (1) +#endif + +#ifndef FIU_ParkingOutPath_Req_FIU_MAS_Main_Not_requested +#define FIU_ParkingOutPath_Req_FIU_MAS_Main_Not_requested (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Request from FIU to enable AVM or APA (active for 3 frames) + // 1 : "Requested" + // 0 : "Not requested" + uint8_t FIU_AVM_Active_Req : 1; // Bits= 1 + + // Request from FIU to activate the view + // 7 : "Parking view" + // 6 : "3D Free View (Rotation)" + // 5 : "3D Right" + // 4 : "3D Left" + // 3 : "3D Main (Rear Top View- GTA)" + // 2 : "2D Rear" + // 1 : "2D Front" + // 0 : "Not requested" + uint8_t FIU_View_Req : 4; // Bits= 4 + + // Status, defined that driver pressed the Start button in Init window + // 0 : "Not requested" + // 1 : "Requested" + uint8_t FIU_APAstartBtn_Req : 1; // Bits= 1 + + // Request from FIU to enable AVM or APA + // 2 : "APA" + // 1 : "AVM" + // 0 : "No change" + uint8_t FIU_MAS_Mode_Req : 2; // Bits= 2 + + // Setting from FIU + // 2 : "Narrow" + // 1 : "Wide (full)" + // 0 : "No change" + uint8_t FIU_Narrow_Mode_Stat : 2; // Bits= 2 + + // Setting from FIU + // 2 : "Inactive" + // 1 : "Active" + // 0 : "No change" + uint8_t FIU_UltraSonicEnable_Stat : 2; // Bits= 2 + + // Setting from FIU: Automatic activation when objects are detected at speeds up to 15 km/h + // 2 : "Inactive" + // 1 : "Active" + // 0 : "No change" + uint8_t FIU_AutoAct_Stat : 2; // Bits= 2 + + // The selected path by driver. This signal is a trigger for start parking maneuver + // 0 : "No selection" + // 1 : "Front parking" + // 2 : "Rear parking" + uint8_t FIU_CurrentPath_Req : 2; // Bits= 2 + + // Request to SDM for taking control of parking + // 1 : "Requested" + // 0 : "Not requested" + uint8_t FIU_SDMmaster_Req : 1; // Bits= 1 + + // The parking position, that selected by driver + // 0 : "No selection" + // 1 : "Left nearest position" + // 2 : "Left near position" + // 3 : "Left far position" + // 4 : "Right nearest position" + // 5 : "Right near position" + // 6 : "Right far position" + uint8_t FIU_SelectedPlace_Req : 3; // Bits= 3 + + // This is a request to continue a parking maneuver from FIU + // 0 : "Not requested" + // 1 : "Requested" + uint8_t FIU_ContinueMove_Req : 1; // Bits= 1 + + // Request from driver about stop APA + // 0 : "Not requested" + // 1 : "Requested" + uint8_t FIU_StopAPA_Req : 1; // Bits= 1 + + // Request to SDM for phone + // 1 : "Requested" + // 0 : "Not requested" + uint8_t FIU_SDMcom_Req : 1; // Bits= 1 + + // This is a request to finish a parking maneuver from FIU + // 1 : "Requested" + // 0 : "Not requested" + uint8_t FIU_FinishMove_Req : 1; // Bits= 1 + + // The parking out path, that selected by the user. + // 6 : "Backward to the Right" + // 5 : "Straight backward" + // 4 : "Backward to the Left" + // 3 : "Forward to the Right" + // 2 : "Straight forward" + // 1 : "Forward to the Left" + // 0 : "Not requested" + uint8_t FIU_ParkingOutPath_Req : 3; // Bits= 3 + + // Rolling counter [0 - 15] + uint8_t FIU_MAS_Main_RC : 4; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t FIU_MAS_Main_CS; // Bits= 8 + +#else + + // Request from FIU to enable AVM or APA (active for 3 frames) + // 1 : "Requested" + // 0 : "Not requested" + uint8_t FIU_AVM_Active_Req; // Bits= 1 + + // Request from FIU to activate the view + // 7 : "Parking view" + // 6 : "3D Free View (Rotation)" + // 5 : "3D Right" + // 4 : "3D Left" + // 3 : "3D Main (Rear Top View- GTA)" + // 2 : "2D Rear" + // 1 : "2D Front" + // 0 : "Not requested" + uint8_t FIU_View_Req; // Bits= 4 + + // Status, defined that driver pressed the Start button in Init window + // 0 : "Not requested" + // 1 : "Requested" + uint8_t FIU_APAstartBtn_Req; // Bits= 1 + + // Request from FIU to enable AVM or APA + // 2 : "APA" + // 1 : "AVM" + // 0 : "No change" + uint8_t FIU_MAS_Mode_Req; // Bits= 2 + + // Setting from FIU + // 2 : "Narrow" + // 1 : "Wide (full)" + // 0 : "No change" + uint8_t FIU_Narrow_Mode_Stat; // Bits= 2 + + // Setting from FIU + // 2 : "Inactive" + // 1 : "Active" + // 0 : "No change" + uint8_t FIU_UltraSonicEnable_Stat; // Bits= 2 + + // Setting from FIU: Automatic activation when objects are detected at speeds up to 15 km/h + // 2 : "Inactive" + // 1 : "Active" + // 0 : "No change" + uint8_t FIU_AutoAct_Stat; // Bits= 2 + + // The selected path by driver. This signal is a trigger for start parking maneuver + // 0 : "No selection" + // 1 : "Front parking" + // 2 : "Rear parking" + uint8_t FIU_CurrentPath_Req; // Bits= 2 + + // Request to SDM for taking control of parking + // 1 : "Requested" + // 0 : "Not requested" + uint8_t FIU_SDMmaster_Req; // Bits= 1 + + // The parking position, that selected by driver + // 0 : "No selection" + // 1 : "Left nearest position" + // 2 : "Left near position" + // 3 : "Left far position" + // 4 : "Right nearest position" + // 5 : "Right near position" + // 6 : "Right far position" + uint8_t FIU_SelectedPlace_Req; // Bits= 3 + + // This is a request to continue a parking maneuver from FIU + // 0 : "Not requested" + // 1 : "Requested" + uint8_t FIU_ContinueMove_Req; // Bits= 1 + + // Request from driver about stop APA + // 0 : "Not requested" + // 1 : "Requested" + uint8_t FIU_StopAPA_Req; // Bits= 1 + + // Request to SDM for phone + // 1 : "Requested" + // 0 : "Not requested" + uint8_t FIU_SDMcom_Req; // Bits= 1 + + // This is a request to finish a parking maneuver from FIU + // 1 : "Requested" + // 0 : "Not requested" + uint8_t FIU_FinishMove_Req; // Bits= 1 + + // The parking out path, that selected by the user. + // 6 : "Backward to the Right" + // 5 : "Straight backward" + // 4 : "Backward to the Left" + // 3 : "Forward to the Right" + // 2 : "Straight forward" + // 1 : "Forward to the Left" + // 0 : "Not requested" + uint8_t FIU_ParkingOutPath_Req; // Bits= 3 + + // Rolling counter [0 - 15] + uint8_t FIU_MAS_Main_RC; // Bits= 4 + + // Checksum CRC8 SAE J1850 of the data field this message + uint8_t FIU_MAS_Main_CS; // Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} FIU_MAS_Main_t; + +// def @MAS_APA_Paths CAN Message (1457 0x5b1) +#define MAS_APA_Paths_IDE (0U) +#define MAS_APA_Paths_DLC (2U) +#define MAS_APA_Paths_CANID (0x5b1U) + +// Value tables for @MAS_AvailablePaths_Stat signal + +#ifndef MAS_AvailablePaths_Stat_MAS_APA_Paths_No_one_path +#define MAS_AvailablePaths_Stat_MAS_APA_Paths_No_one_path (0) +#endif + +#ifndef MAS_AvailablePaths_Stat_MAS_APA_Paths_front +#define MAS_AvailablePaths_Stat_MAS_APA_Paths_front (1) +#endif + +#ifndef MAS_AvailablePaths_Stat_MAS_APA_Paths_rear +#define MAS_AvailablePaths_Stat_MAS_APA_Paths_rear (2) +#endif + +#ifndef MAS_AvailablePaths_Stat_MAS_APA_Paths_both +#define MAS_AvailablePaths_Stat_MAS_APA_Paths_both (3) +#endif + + +// Value tables for @MAS_APAPlaceParkingOut_Stat signal + +#ifndef MAS_APAPlaceParkingOut_Stat_MAS_APA_Paths_Perpendicular +#define MAS_APAPlaceParkingOut_Stat_MAS_APA_Paths_Perpendicular (1) +#endif + +#ifndef MAS_APAPlaceParkingOut_Stat_MAS_APA_Paths_Parallel +#define MAS_APAPlaceParkingOut_Stat_MAS_APA_Paths_Parallel (0) +#endif + + +// Value tables for @MAS_APADirParkingOut_Stat signal + +#ifndef MAS_APADirParkingOut_Stat_MAS_APA_Paths_Rear +#define MAS_APADirParkingOut_Stat_MAS_APA_Paths_Rear (1) +#endif + +#ifndef MAS_APADirParkingOut_Stat_MAS_APA_Paths_Front +#define MAS_APADirParkingOut_Stat_MAS_APA_Paths_Front (0) +#endif + + +// Value tables for @MAS_PathParkOutFL_Stat signal + +#ifndef MAS_PathParkOutFL_Stat_MAS_APA_Paths_Avaible +#define MAS_PathParkOutFL_Stat_MAS_APA_Paths_Avaible (1) +#endif + +#ifndef MAS_PathParkOutFL_Stat_MAS_APA_Paths_Not_avaible +#define MAS_PathParkOutFL_Stat_MAS_APA_Paths_Not_avaible (0) +#endif + + +// Value tables for @MAS_PathParkOutFR_Stat signal + +#ifndef MAS_PathParkOutFR_Stat_MAS_APA_Paths_Avaible +#define MAS_PathParkOutFR_Stat_MAS_APA_Paths_Avaible (1) +#endif + +#ifndef MAS_PathParkOutFR_Stat_MAS_APA_Paths_Not_avaible +#define MAS_PathParkOutFR_Stat_MAS_APA_Paths_Not_avaible (0) +#endif + + +// Value tables for @MAS_PathParkOutFront_Stat signal + +#ifndef MAS_PathParkOutFront_Stat_MAS_APA_Paths_Avaible +#define MAS_PathParkOutFront_Stat_MAS_APA_Paths_Avaible (1) +#endif + +#ifndef MAS_PathParkOutFront_Stat_MAS_APA_Paths_Not_avaible +#define MAS_PathParkOutFront_Stat_MAS_APA_Paths_Not_avaible (0) +#endif + + +// Value tables for @MAS_PathParkOutRL_Stat signal + +#ifndef MAS_PathParkOutRL_Stat_MAS_APA_Paths_Avaible +#define MAS_PathParkOutRL_Stat_MAS_APA_Paths_Avaible (1) +#endif + +#ifndef MAS_PathParkOutRL_Stat_MAS_APA_Paths_Not_avaible +#define MAS_PathParkOutRL_Stat_MAS_APA_Paths_Not_avaible (0) +#endif + + +// Value tables for @MAS_PathParkOutRR_Stat signal + +#ifndef MAS_PathParkOutRR_Stat_MAS_APA_Paths_Avaible +#define MAS_PathParkOutRR_Stat_MAS_APA_Paths_Avaible (1) +#endif + +#ifndef MAS_PathParkOutRR_Stat_MAS_APA_Paths_Not_avaible +#define MAS_PathParkOutRR_Stat_MAS_APA_Paths_Not_avaible (0) +#endif + + +// Value tables for @MAS_PathParkOutRear_Stat signal + +#ifndef MAS_PathParkOutRear_Stat_MAS_APA_Paths_Avaible +#define MAS_PathParkOutRear_Stat_MAS_APA_Paths_Avaible (1) +#endif + +#ifndef MAS_PathParkOutRear_Stat_MAS_APA_Paths_Not_avaible +#define MAS_PathParkOutRear_Stat_MAS_APA_Paths_Not_avaible (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Available path + // 0 : "No one path" + // 1 : "front" + // 2 : "rear" + // 3 : "both" + uint8_t MAS_AvailablePaths_Stat : 2; // Bits= 2 + + // The status shows the type of parking space the vehicle was parked in. + // 1 : "Perpendicular" + // 0 : "Parallel" + uint8_t MAS_APAPlaceParkingOut_Stat : 1; // Bits= 1 + + // The status shows the direction of vehicle in parking space + // 1 : "Rear" + // 0 : "Front" + uint8_t MAS_APADirParkingOut_Stat : 1; // Bits= 1 + + // 1 : "Avaible" + // 0 : "Not avaible" + uint8_t MAS_PathParkOutFL_Stat : 1; // Bits= 1 + + // 1 : "Avaible" + // 0 : "Not avaible" + uint8_t MAS_PathParkOutFR_Stat : 1; // Bits= 1 + + // 1 : "Avaible" + // 0 : "Not avaible" + uint8_t MAS_PathParkOutFront_Stat : 1; // Bits= 1 + + // 1 : "Avaible" + // 0 : "Not avaible" + uint8_t MAS_PathParkOutRL_Stat : 1; // Bits= 1 + + // 1 : "Avaible" + // 0 : "Not avaible" + uint8_t MAS_PathParkOutRR_Stat : 1; // Bits= 1 + + // 1 : "Avaible" + // 0 : "Not avaible" + uint8_t MAS_PathParkOutRear_Stat : 1; // Bits= 1 + +#else + + // Available path + // 0 : "No one path" + // 1 : "front" + // 2 : "rear" + // 3 : "both" + uint8_t MAS_AvailablePaths_Stat; // Bits= 2 + + // The status shows the type of parking space the vehicle was parked in. + // 1 : "Perpendicular" + // 0 : "Parallel" + uint8_t MAS_APAPlaceParkingOut_Stat; // Bits= 1 + + // The status shows the direction of vehicle in parking space + // 1 : "Rear" + // 0 : "Front" + uint8_t MAS_APADirParkingOut_Stat; // Bits= 1 + + // 1 : "Avaible" + // 0 : "Not avaible" + uint8_t MAS_PathParkOutFL_Stat; // Bits= 1 + + // 1 : "Avaible" + // 0 : "Not avaible" + uint8_t MAS_PathParkOutFR_Stat; // Bits= 1 + + // 1 : "Avaible" + // 0 : "Not avaible" + uint8_t MAS_PathParkOutFront_Stat; // Bits= 1 + + // 1 : "Avaible" + // 0 : "Not avaible" + uint8_t MAS_PathParkOutRL_Stat; // Bits= 1 + + // 1 : "Avaible" + // 0 : "Not avaible" + uint8_t MAS_PathParkOutRR_Stat; // Bits= 1 + + // 1 : "Avaible" + // 0 : "Not avaible" + uint8_t MAS_PathParkOutRear_Stat; // Bits= 1 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} MAS_APA_Paths_t; + +// def @MAS_APA_ParkPlace CAN Message (1458 0x5b2) +#define MAS_APA_ParkPlace_IDE (0U) +#define MAS_APA_ParkPlace_DLC (6U) +#define MAS_APA_ParkPlace_CANID (0x5b2U) +#define MAS_APA_ParkPlace_CYC (100U) + +// Value tables for @MAS_APAplaceL1_Stat signal + +#ifndef MAS_APAplaceL1_Stat_MAS_APA_ParkPlace_Not_detected +#define MAS_APAplaceL1_Stat_MAS_APA_ParkPlace_Not_detected (0) +#endif + +#ifndef MAS_APAplaceL1_Stat_MAS_APA_ParkPlace_Parallel +#define MAS_APAplaceL1_Stat_MAS_APA_ParkPlace_Parallel (1) +#endif + +#ifndef MAS_APAplaceL1_Stat_MAS_APA_ParkPlace_Perpendicular +#define MAS_APAplaceL1_Stat_MAS_APA_ParkPlace_Perpendicular (2) +#endif + + +// Value tables for @MAS_APAplaceL2_Stat signal + +#ifndef MAS_APAplaceL2_Stat_MAS_APA_ParkPlace_Not_detected +#define MAS_APAplaceL2_Stat_MAS_APA_ParkPlace_Not_detected (0) +#endif + +#ifndef MAS_APAplaceL2_Stat_MAS_APA_ParkPlace_Parallel +#define MAS_APAplaceL2_Stat_MAS_APA_ParkPlace_Parallel (1) +#endif + +#ifndef MAS_APAplaceL2_Stat_MAS_APA_ParkPlace_Perpendicular +#define MAS_APAplaceL2_Stat_MAS_APA_ParkPlace_Perpendicular (2) +#endif + + +// Value tables for @MAS_APAplaceL3_Stat signal + +#ifndef MAS_APAplaceL3_Stat_MAS_APA_ParkPlace_Not_detected +#define MAS_APAplaceL3_Stat_MAS_APA_ParkPlace_Not_detected (0) +#endif + +#ifndef MAS_APAplaceL3_Stat_MAS_APA_ParkPlace_Parallel +#define MAS_APAplaceL3_Stat_MAS_APA_ParkPlace_Parallel (1) +#endif + +#ifndef MAS_APAplaceL3_Stat_MAS_APA_ParkPlace_Perpendicular +#define MAS_APAplaceL3_Stat_MAS_APA_ParkPlace_Perpendicular (2) +#endif + + +// Value tables for @MAS_APAplaceR1_Stat signal + +#ifndef MAS_APAplaceR1_Stat_MAS_APA_ParkPlace_Not_detected +#define MAS_APAplaceR1_Stat_MAS_APA_ParkPlace_Not_detected (0) +#endif + +#ifndef MAS_APAplaceR1_Stat_MAS_APA_ParkPlace_Parallel +#define MAS_APAplaceR1_Stat_MAS_APA_ParkPlace_Parallel (1) +#endif + +#ifndef MAS_APAplaceR1_Stat_MAS_APA_ParkPlace_Perpendicular +#define MAS_APAplaceR1_Stat_MAS_APA_ParkPlace_Perpendicular (2) +#endif + + +// Value tables for @MAS_APAplaceR2_Stat signal + +#ifndef MAS_APAplaceR2_Stat_MAS_APA_ParkPlace_Not_detected +#define MAS_APAplaceR2_Stat_MAS_APA_ParkPlace_Not_detected (0) +#endif + +#ifndef MAS_APAplaceR2_Stat_MAS_APA_ParkPlace_Parallel +#define MAS_APAplaceR2_Stat_MAS_APA_ParkPlace_Parallel (1) +#endif + +#ifndef MAS_APAplaceR2_Stat_MAS_APA_ParkPlace_Perpendicular +#define MAS_APAplaceR2_Stat_MAS_APA_ParkPlace_Perpendicular (2) +#endif + + +// Value tables for @MAS_APAplaceR3_Stat signal + +#ifndef MAS_APAplaceR3_Stat_MAS_APA_ParkPlace_Not_detected +#define MAS_APAplaceR3_Stat_MAS_APA_ParkPlace_Not_detected (0) +#endif + +#ifndef MAS_APAplaceR3_Stat_MAS_APA_ParkPlace_Parallel +#define MAS_APAplaceR3_Stat_MAS_APA_ParkPlace_Parallel (1) +#endif + +#ifndef MAS_APAplaceR3_Stat_MAS_APA_ParkPlace_Perpendicular +#define MAS_APAplaceR3_Stat_MAS_APA_ParkPlace_Perpendicular (2) +#endif + + +// Value tables for @MAS_AvailablePathsL1_Stat signal + +#ifndef MAS_AvailablePathsL1_Stat_MAS_APA_ParkPlace_Both +#define MAS_AvailablePathsL1_Stat_MAS_APA_ParkPlace_Both (3) +#endif + +#ifndef MAS_AvailablePathsL1_Stat_MAS_APA_ParkPlace_Rear +#define MAS_AvailablePathsL1_Stat_MAS_APA_ParkPlace_Rear (2) +#endif + +#ifndef MAS_AvailablePathsL1_Stat_MAS_APA_ParkPlace_Front +#define MAS_AvailablePathsL1_Stat_MAS_APA_ParkPlace_Front (1) +#endif + +#ifndef MAS_AvailablePathsL1_Stat_MAS_APA_ParkPlace_No_available +#define MAS_AvailablePathsL1_Stat_MAS_APA_ParkPlace_No_available (0) +#endif + + +// Value tables for @MAS_AvailablePathsL2_Stat signal + +#ifndef MAS_AvailablePathsL2_Stat_MAS_APA_ParkPlace_Both +#define MAS_AvailablePathsL2_Stat_MAS_APA_ParkPlace_Both (3) +#endif + +#ifndef MAS_AvailablePathsL2_Stat_MAS_APA_ParkPlace_Rear +#define MAS_AvailablePathsL2_Stat_MAS_APA_ParkPlace_Rear (2) +#endif + +#ifndef MAS_AvailablePathsL2_Stat_MAS_APA_ParkPlace_Front +#define MAS_AvailablePathsL2_Stat_MAS_APA_ParkPlace_Front (1) +#endif + +#ifndef MAS_AvailablePathsL2_Stat_MAS_APA_ParkPlace_No_available +#define MAS_AvailablePathsL2_Stat_MAS_APA_ParkPlace_No_available (0) +#endif + + +// Value tables for @MAS_AvailablePathsL3_Stat signal + +#ifndef MAS_AvailablePathsL3_Stat_MAS_APA_ParkPlace_Both +#define MAS_AvailablePathsL3_Stat_MAS_APA_ParkPlace_Both (3) +#endif + +#ifndef MAS_AvailablePathsL3_Stat_MAS_APA_ParkPlace_Rear +#define MAS_AvailablePathsL3_Stat_MAS_APA_ParkPlace_Rear (2) +#endif + +#ifndef MAS_AvailablePathsL3_Stat_MAS_APA_ParkPlace_Front +#define MAS_AvailablePathsL3_Stat_MAS_APA_ParkPlace_Front (1) +#endif + +#ifndef MAS_AvailablePathsL3_Stat_MAS_APA_ParkPlace_No_available +#define MAS_AvailablePathsL3_Stat_MAS_APA_ParkPlace_No_available (0) +#endif + + +// Value tables for @MAS_AvailablePathsR1_Stat signal + +#ifndef MAS_AvailablePathsR1_Stat_MAS_APA_ParkPlace_Both +#define MAS_AvailablePathsR1_Stat_MAS_APA_ParkPlace_Both (3) +#endif + +#ifndef MAS_AvailablePathsR1_Stat_MAS_APA_ParkPlace_Rear +#define MAS_AvailablePathsR1_Stat_MAS_APA_ParkPlace_Rear (2) +#endif + +#ifndef MAS_AvailablePathsR1_Stat_MAS_APA_ParkPlace_Front +#define MAS_AvailablePathsR1_Stat_MAS_APA_ParkPlace_Front (1) +#endif + +#ifndef MAS_AvailablePathsR1_Stat_MAS_APA_ParkPlace_No_available +#define MAS_AvailablePathsR1_Stat_MAS_APA_ParkPlace_No_available (0) +#endif + + +// Value tables for @MAS_AvailablePathsR2_Stat signal + +#ifndef MAS_AvailablePathsR2_Stat_MAS_APA_ParkPlace_Both +#define MAS_AvailablePathsR2_Stat_MAS_APA_ParkPlace_Both (3) +#endif + +#ifndef MAS_AvailablePathsR2_Stat_MAS_APA_ParkPlace_Rear +#define MAS_AvailablePathsR2_Stat_MAS_APA_ParkPlace_Rear (2) +#endif + +#ifndef MAS_AvailablePathsR2_Stat_MAS_APA_ParkPlace_Front +#define MAS_AvailablePathsR2_Stat_MAS_APA_ParkPlace_Front (1) +#endif + +#ifndef MAS_AvailablePathsR2_Stat_MAS_APA_ParkPlace_No_available +#define MAS_AvailablePathsR2_Stat_MAS_APA_ParkPlace_No_available (0) +#endif + + +// Value tables for @MAS_AvailablePathsR3_Stat signal + +#ifndef MAS_AvailablePathsR3_Stat_MAS_APA_ParkPlace_Both +#define MAS_AvailablePathsR3_Stat_MAS_APA_ParkPlace_Both (3) +#endif + +#ifndef MAS_AvailablePathsR3_Stat_MAS_APA_ParkPlace_Rear +#define MAS_AvailablePathsR3_Stat_MAS_APA_ParkPlace_Rear (2) +#endif + +#ifndef MAS_AvailablePathsR3_Stat_MAS_APA_ParkPlace_Front +#define MAS_AvailablePathsR3_Stat_MAS_APA_ParkPlace_Front (1) +#endif + +#ifndef MAS_AvailablePathsR3_Stat_MAS_APA_ParkPlace_No_available +#define MAS_AvailablePathsR3_Stat_MAS_APA_ParkPlace_No_available (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // State of the first position found on the left + // 0 : "Not detected" + // 1 : "Parallel" + // 2 : "Perpendicular" + uint8_t MAS_APAplaceL1_Stat : 2; // Bits= 2 + + // State of the second position found on the left + // 0 : "Not detected" + // 1 : "Parallel" + // 2 : "Perpendicular" + uint8_t MAS_APAplaceL2_Stat : 2; // Bits= 2 + + // State of the third position found on the left + // 0 : "Not detected" + // 1 : "Parallel" + // 2 : "Perpendicular" + uint8_t MAS_APAplaceL3_Stat : 2; // Bits= 2 + + // State of the first position found on the right + // 0 : "Not detected" + // 1 : "Parallel" + // 2 : "Perpendicular" + uint8_t MAS_APAplaceR1_Stat : 2; // Bits= 2 + + // State of the second position found on the right + // 0 : "Not detected" + // 1 : "Parallel" + // 2 : "Perpendicular" + uint8_t MAS_APAplaceR2_Stat : 2; // Bits= 2 + + // State of the third position found on the right + // 0 : "Not detected" + // 1 : "Parallel" + // 2 : "Perpendicular" + uint8_t MAS_APAplaceR3_Stat : 2; // Bits= 2 + + // State of paths available for the first position found on the left + // 3 : "Both" + // 2 : "Rear" + // 1 : "Front" + // 0 : "No available" + uint8_t MAS_AvailablePathsL1_Stat : 2; // Bits= 2 + + // State of paths available for the second position found on the left + // 3 : "Both" + // 2 : "Rear" + // 1 : "Front" + // 0 : "No available" + uint8_t MAS_AvailablePathsL2_Stat : 2; // Bits= 2 + + // Value from 0 to 15, where 0 - the closest distance, 15 - the furthest distance + uint8_t MAS_APAplaceL1Dist_Val : 4; // Bits= 4 + + // Value from 0 to 15, where 0 - the closest distance, 15 - the furthest distance + uint8_t MAS_APAplaceL2Dist_Val : 4; // Bits= 4 + + // Value from 0 to 15, where 0 - the closest distance, 15 - the furthest distance + uint8_t MAS_APAplaceL3Dist_Val : 4; // Bits= 4 + + // Value from 0 to 15, where 0 - the closest distance, 15 - the furthest distance + uint8_t MAS_APAplaceR1Dist_Val : 4; // Bits= 4 + + // Value from 0 to 15, where 0 - the closest distance, 15 - the furthest distance + uint8_t MAS_APAplaceR2Dist_Val : 4; // Bits= 4 + + // Value from 0 to 15, where 0 - the closest distance, 15 - the furthest distance + uint8_t MAS_APAplaceR3Dist_Val : 4; // Bits= 4 + + // State of paths available for the third position found on the left + // 3 : "Both" + // 2 : "Rear" + // 1 : "Front" + // 0 : "No available" + uint8_t MAS_AvailablePathsL3_Stat : 2; // Bits= 2 + + // State of paths available for first position found on the right + // 3 : "Both" + // 2 : "Rear" + // 1 : "Front" + // 0 : "No available" + uint8_t MAS_AvailablePathsR1_Stat : 2; // Bits= 2 + + // State of paths available for the second position found on the right + // 3 : "Both" + // 2 : "Rear" + // 1 : "Front" + // 0 : "No available" + uint8_t MAS_AvailablePathsR2_Stat : 2; // Bits= 2 + + // State of paths available for the third position found on the right + // 3 : "Both" + // 2 : "Rear" + // 1 : "Front" + // 0 : "No available" + uint8_t MAS_AvailablePathsR3_Stat : 2; // Bits= 2 + +#else + + // State of the first position found on the left + // 0 : "Not detected" + // 1 : "Parallel" + // 2 : "Perpendicular" + uint8_t MAS_APAplaceL1_Stat; // Bits= 2 + + // State of the second position found on the left + // 0 : "Not detected" + // 1 : "Parallel" + // 2 : "Perpendicular" + uint8_t MAS_APAplaceL2_Stat; // Bits= 2 + + // State of the third position found on the left + // 0 : "Not detected" + // 1 : "Parallel" + // 2 : "Perpendicular" + uint8_t MAS_APAplaceL3_Stat; // Bits= 2 + + // State of the first position found on the right + // 0 : "Not detected" + // 1 : "Parallel" + // 2 : "Perpendicular" + uint8_t MAS_APAplaceR1_Stat; // Bits= 2 + + // State of the second position found on the right + // 0 : "Not detected" + // 1 : "Parallel" + // 2 : "Perpendicular" + uint8_t MAS_APAplaceR2_Stat; // Bits= 2 + + // State of the third position found on the right + // 0 : "Not detected" + // 1 : "Parallel" + // 2 : "Perpendicular" + uint8_t MAS_APAplaceR3_Stat; // Bits= 2 + + // State of paths available for the first position found on the left + // 3 : "Both" + // 2 : "Rear" + // 1 : "Front" + // 0 : "No available" + uint8_t MAS_AvailablePathsL1_Stat; // Bits= 2 + + // State of paths available for the second position found on the left + // 3 : "Both" + // 2 : "Rear" + // 1 : "Front" + // 0 : "No available" + uint8_t MAS_AvailablePathsL2_Stat; // Bits= 2 + + // Value from 0 to 15, where 0 - the closest distance, 15 - the furthest distance + uint8_t MAS_APAplaceL1Dist_Val; // Bits= 4 + + // Value from 0 to 15, where 0 - the closest distance, 15 - the furthest distance + uint8_t MAS_APAplaceL2Dist_Val; // Bits= 4 + + // Value from 0 to 15, where 0 - the closest distance, 15 - the furthest distance + uint8_t MAS_APAplaceL3Dist_Val; // Bits= 4 + + // Value from 0 to 15, where 0 - the closest distance, 15 - the furthest distance + uint8_t MAS_APAplaceR1Dist_Val; // Bits= 4 + + // Value from 0 to 15, where 0 - the closest distance, 15 - the furthest distance + uint8_t MAS_APAplaceR2Dist_Val; // Bits= 4 + + // Value from 0 to 15, where 0 - the closest distance, 15 - the furthest distance + uint8_t MAS_APAplaceR3Dist_Val; // Bits= 4 + + // State of paths available for the third position found on the left + // 3 : "Both" + // 2 : "Rear" + // 1 : "Front" + // 0 : "No available" + uint8_t MAS_AvailablePathsL3_Stat; // Bits= 2 + + // State of paths available for first position found on the right + // 3 : "Both" + // 2 : "Rear" + // 1 : "Front" + // 0 : "No available" + uint8_t MAS_AvailablePathsR1_Stat; // Bits= 2 + + // State of paths available for the second position found on the right + // 3 : "Both" + // 2 : "Rear" + // 1 : "Front" + // 0 : "No available" + uint8_t MAS_AvailablePathsR2_Stat; // Bits= 2 + + // State of paths available for the third position found on the right + // 3 : "Both" + // 2 : "Rear" + // 1 : "Front" + // 0 : "No available" + uint8_t MAS_AvailablePathsR3_Stat; // Bits= 2 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} MAS_APA_ParkPlace_t; + +// def @ICLSilCU_State CAN Message (1482 0x5ca) +#define ICLSilCU_State_IDE (0U) +#define ICLSilCU_State_DLC (8U) +#define ICLSilCU_State_CANID (0x5caU) + +// Value tables for @ICLSilCU_Module_Stat signal + +#ifndef ICLSilCU_Module_Stat_ICLSilCU_State_Scenario_data_message_error +#define ICLSilCU_Module_Stat_ICLSilCU_State_Scenario_data_message_error (8) +#endif + +#ifndef ICLSilCU_Module_Stat_ICLSilCU_State_Temperature_error +#define ICLSilCU_Module_Stat_ICLSilCU_State_Temperature_error (9) +#endif + +#ifndef ICLSilCU_Module_Stat_ICLSilCU_State_Channels_power_error +#define ICLSilCU_Module_Stat_ICLSilCU_State_Channels_power_error (10) +#endif + +#ifndef ICLSilCU_Module_Stat_ICLSilCU_State_Scenario_play_error +#define ICLSilCU_Module_Stat_ICLSilCU_State_Scenario_play_error (7) +#endif + +#ifndef ICLSilCU_Module_Stat_ICLSilCU_State_Launch_error +#define ICLSilCU_Module_Stat_ICLSilCU_State_Launch_error (6) +#endif + +#ifndef ICLSilCU_Module_Stat_ICLSilCU_State_Scenario_Data_is_recieved +#define ICLSilCU_Module_Stat_ICLSilCU_State_Scenario_Data_is_recieved (5) +#endif + +#ifndef ICLSilCU_Module_Stat_ICLSilCU_State_Configuration_is_going +#define ICLSilCU_Module_Stat_ICLSilCU_State_Configuration_is_going (4) +#endif + +#ifndef ICLSilCU_Module_Stat_ICLSilCU_State_Special_event_done +#define ICLSilCU_Module_Stat_ICLSilCU_State_Special_event_done (3) +#endif + +#ifndef ICLSilCU_Module_Stat_ICLSilCU_State_Scenario_have_done +#define ICLSilCU_Module_Stat_ICLSilCU_State_Scenario_have_done (2) +#endif + +#ifndef ICLSilCU_Module_Stat_ICLSilCU_State_Scenario_is_going +#define ICLSilCU_Module_Stat_ICLSilCU_State_Scenario_is_going (1) +#endif + +#ifndef ICLSilCU_Module_Stat_ICLSilCU_State_Ready +#define ICLSilCU_Module_Stat_ICLSilCU_State_Ready (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Module state: + // 0 - Module is ready for action + // 1 - Module has done a scenario + // 2 - Module made a special event + // 3 - Data is recieved + // 4 - Module start error + // 5 - Scenario play error + // 6 - Data error + // 7 - Temperature error + // 8 : "Scenario data message error" + // 9 : "Temperature error" + // 10 : "Channels power error" + // 7 : "Scenario play error" + // 6 : "Launch error" + // 5 : "Scenario Data is recieved" + // 4 : "Configuration is going" + // 3 : "Special event done" + // 2 : "Scenario have done" + // 1 : "Scenario is going" + // 0 : "Ready" + int8_t ICLSilCU_Module_Stat : 4; // [-] Bits= 4 + + // Temperature value + int8_t ICLSilCU_ModuleTemperature_Val : 7; // [-] Bits= 7 Unit:'�C' + + // Reseved + int8_t ICLSilCU_reserved1 : 5; // [-] Bits= 5 + + // Reseved + int8_t ICLSilCU_reserved2; // [-] Bits= 8 + + // Reseved + int8_t ICLSilCU_reserved3; // [-] Bits= 8 + + // Reseved + int8_t ICLSilCU_reserved4; // [-] Bits= 8 + + // Reseved + int8_t ICLSilCU_reserved5; // [-] Bits= 8 + + // Reseved + int8_t ICLSilCU_reserved6; // [-] Bits= 8 + + // Reseved + int8_t ICLSilCU_reserved7; // [-] Bits= 8 + +#else + + // Module state: + // 0 - Module is ready for action + // 1 - Module has done a scenario + // 2 - Module made a special event + // 3 - Data is recieved + // 4 - Module start error + // 5 - Scenario play error + // 6 - Data error + // 7 - Temperature error + // 8 : "Scenario data message error" + // 9 : "Temperature error" + // 10 : "Channels power error" + // 7 : "Scenario play error" + // 6 : "Launch error" + // 5 : "Scenario Data is recieved" + // 4 : "Configuration is going" + // 3 : "Special event done" + // 2 : "Scenario have done" + // 1 : "Scenario is going" + // 0 : "Ready" + int8_t ICLSilCU_Module_Stat; // [-] Bits= 4 + + // Temperature value + int8_t ICLSilCU_ModuleTemperature_Val; // [-] Bits= 7 Unit:'�C' + + // Reseved + int8_t ICLSilCU_reserved1; // [-] Bits= 5 + + // Reseved + int8_t ICLSilCU_reserved2; // [-] Bits= 8 + + // Reseved + int8_t ICLSilCU_reserved3; // [-] Bits= 8 + + // Reseved + int8_t ICLSilCU_reserved4; // [-] Bits= 8 + + // Reseved + int8_t ICLSilCU_reserved5; // [-] Bits= 8 + + // Reseved + int8_t ICLSilCU_reserved6; // [-] Bits= 8 + + // Reseved + int8_t ICLSilCU_reserved7; // [-] Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} ICLSilCU_State_t; + +// def @ICRSilCU_State CAN Message (1483 0x5cb) +#define ICRSilCU_State_IDE (0U) +#define ICRSilCU_State_DLC (8U) +#define ICRSilCU_State_CANID (0x5cbU) + +// Value tables for @ICRSilCU_Module_Stat signal + +#ifndef ICRSilCU_Module_Stat_ICRSilCU_State_Scenario_data_message_error +#define ICRSilCU_Module_Stat_ICRSilCU_State_Scenario_data_message_error (8) +#endif + +#ifndef ICRSilCU_Module_Stat_ICRSilCU_State_Temperature_error +#define ICRSilCU_Module_Stat_ICRSilCU_State_Temperature_error (9) +#endif + +#ifndef ICRSilCU_Module_Stat_ICRSilCU_State_Channels_power_error +#define ICRSilCU_Module_Stat_ICRSilCU_State_Channels_power_error (10) +#endif + +#ifndef ICRSilCU_Module_Stat_ICRSilCU_State_Scenario_play_error +#define ICRSilCU_Module_Stat_ICRSilCU_State_Scenario_play_error (7) +#endif + +#ifndef ICRSilCU_Module_Stat_ICRSilCU_State_Launch_error +#define ICRSilCU_Module_Stat_ICRSilCU_State_Launch_error (6) +#endif + +#ifndef ICRSilCU_Module_Stat_ICRSilCU_State_Scenario_Data_is_recieved +#define ICRSilCU_Module_Stat_ICRSilCU_State_Scenario_Data_is_recieved (5) +#endif + +#ifndef ICRSilCU_Module_Stat_ICRSilCU_State_Configuration_is_going +#define ICRSilCU_Module_Stat_ICRSilCU_State_Configuration_is_going (4) +#endif + +#ifndef ICRSilCU_Module_Stat_ICRSilCU_State_Special_event_done +#define ICRSilCU_Module_Stat_ICRSilCU_State_Special_event_done (3) +#endif + +#ifndef ICRSilCU_Module_Stat_ICRSilCU_State_Scenario_have_done +#define ICRSilCU_Module_Stat_ICRSilCU_State_Scenario_have_done (2) +#endif + +#ifndef ICRSilCU_Module_Stat_ICRSilCU_State_Scenario_is_going +#define ICRSilCU_Module_Stat_ICRSilCU_State_Scenario_is_going (1) +#endif + +#ifndef ICRSilCU_Module_Stat_ICRSilCU_State_Ready +#define ICRSilCU_Module_Stat_ICRSilCU_State_Ready (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Module state: + // 0 - Module is ready for action + // 1 - Module has done a scenario + // 2 - Module made a special event + // 3 - Data is recieved + // 4 - Module start error + // 5 - Scenario play error + // 6 - Data error + // 7 - Temperature error + // 8 : "Scenario data message error" + // 9 : "Temperature error" + // 10 : "Channels power error" + // 7 : "Scenario play error" + // 6 : "Launch error" + // 5 : "Scenario Data is recieved" + // 4 : "Configuration is going" + // 3 : "Special event done" + // 2 : "Scenario have done" + // 1 : "Scenario is going" + // 0 : "Ready" + int8_t ICRSilCU_Module_Stat : 4; // [-] Bits= 4 + + // Temperature value + int8_t ICRSilCU_ModuleTemperature_Val : 7; // [-] Bits= 7 Unit:'�C' + + // Reserved + int8_t ICRSilCU_reserved1 : 5; // [-] Bits= 5 + + // Reserved + int8_t ICRSilCU_reserved2; // [-] Bits= 8 + + // Reserved + int8_t ICRSilCU_reserved3; // [-] Bits= 8 + + // Reserved + int8_t ICRSilCU_reserved4; // [-] Bits= 8 + + // Reserved + int8_t ICRSilCU_reserved5; // [-] Bits= 8 + + // Reserved + int8_t ICRSilCU_reserved6; // [-] Bits= 8 + + // Reserved + int8_t ICRSilCU_reserved7; // [-] Bits= 8 + +#else + + // Module state: + // 0 - Module is ready for action + // 1 - Module has done a scenario + // 2 - Module made a special event + // 3 - Data is recieved + // 4 - Module start error + // 5 - Scenario play error + // 6 - Data error + // 7 - Temperature error + // 8 : "Scenario data message error" + // 9 : "Temperature error" + // 10 : "Channels power error" + // 7 : "Scenario play error" + // 6 : "Launch error" + // 5 : "Scenario Data is recieved" + // 4 : "Configuration is going" + // 3 : "Special event done" + // 2 : "Scenario have done" + // 1 : "Scenario is going" + // 0 : "Ready" + int8_t ICRSilCU_Module_Stat; // [-] Bits= 4 + + // Temperature value + int8_t ICRSilCU_ModuleTemperature_Val; // [-] Bits= 7 Unit:'�C' + + // Reserved + int8_t ICRSilCU_reserved1; // [-] Bits= 5 + + // Reserved + int8_t ICRSilCU_reserved2; // [-] Bits= 8 + + // Reserved + int8_t ICRSilCU_reserved3; // [-] Bits= 8 + + // Reserved + int8_t ICRSilCU_reserved4; // [-] Bits= 8 + + // Reserved + int8_t ICRSilCU_reserved5; // [-] Bits= 8 + + // Reserved + int8_t ICRSilCU_reserved6; // [-] Bits= 8 + + // Reserved + int8_t ICRSilCU_reserved7; // [-] Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} ICRSilCU_State_t; + +// def @SFRSilCU_State CAN Message (1498 0x5da) +#define SFRSilCU_State_IDE (0U) +#define SFRSilCU_State_DLC (8U) +#define SFRSilCU_State_CANID (0x5daU) + +// Value tables for @SFRSilCU_Module_Stat signal + +#ifndef SFRSilCU_Module_Stat_SFRSilCU_State_Scenario_data_message_error +#define SFRSilCU_Module_Stat_SFRSilCU_State_Scenario_data_message_error (8) +#endif + +#ifndef SFRSilCU_Module_Stat_SFRSilCU_State_Temperature_error +#define SFRSilCU_Module_Stat_SFRSilCU_State_Temperature_error (9) +#endif + +#ifndef SFRSilCU_Module_Stat_SFRSilCU_State_Channels_power_error +#define SFRSilCU_Module_Stat_SFRSilCU_State_Channels_power_error (10) +#endif + +#ifndef SFRSilCU_Module_Stat_SFRSilCU_State_Scenario_play_error +#define SFRSilCU_Module_Stat_SFRSilCU_State_Scenario_play_error (7) +#endif + +#ifndef SFRSilCU_Module_Stat_SFRSilCU_State_Launch_error +#define SFRSilCU_Module_Stat_SFRSilCU_State_Launch_error (6) +#endif + +#ifndef SFRSilCU_Module_Stat_SFRSilCU_State_Scenario_Data_is_recieved +#define SFRSilCU_Module_Stat_SFRSilCU_State_Scenario_Data_is_recieved (5) +#endif + +#ifndef SFRSilCU_Module_Stat_SFRSilCU_State_Configuration_is_going +#define SFRSilCU_Module_Stat_SFRSilCU_State_Configuration_is_going (4) +#endif + +#ifndef SFRSilCU_Module_Stat_SFRSilCU_State_Special_event_done +#define SFRSilCU_Module_Stat_SFRSilCU_State_Special_event_done (3) +#endif + +#ifndef SFRSilCU_Module_Stat_SFRSilCU_State_Scenario_have_done +#define SFRSilCU_Module_Stat_SFRSilCU_State_Scenario_have_done (2) +#endif + +#ifndef SFRSilCU_Module_Stat_SFRSilCU_State_Scenario_is_going +#define SFRSilCU_Module_Stat_SFRSilCU_State_Scenario_is_going (1) +#endif + +#ifndef SFRSilCU_Module_Stat_SFRSilCU_State_Ready +#define SFRSilCU_Module_Stat_SFRSilCU_State_Ready (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Module state: + // 0 - Module is ready for action + // 1 - Module has done a scenario + // 2 - Module made a special event + // 3 - Data is recieved + // 4 - Module start error + // 5 - Scenario play error + // 6 - Data error + // 7 - Temperature error + // 8 : "Scenario data message error" + // 9 : "Temperature error" + // 10 : "Channels power error" + // 7 : "Scenario play error" + // 6 : "Launch error" + // 5 : "Scenario Data is recieved" + // 4 : "Configuration is going" + // 3 : "Special event done" + // 2 : "Scenario have done" + // 1 : "Scenario is going" + // 0 : "Ready" + uint8_t SFRSilCU_Module_Stat : 4; // Bits= 4 + + // Temperature value + int8_t SFRSilCU_ModuleTemperature_Val : 7; // [-] Bits= 7 Unit:'�C' + + // Reserved + int8_t SFRSilCU_reserved1 : 5; // [-] Bits= 5 + + // Reserved + int8_t SFRSilCU_reserved2; // [-] Bits= 8 + + // Reserved + int8_t SFRSilCU_reserved3; // [-] Bits= 8 + + // Reserved + int8_t SFRSilCU_reserved4; // [-] Bits= 8 + + // Reserved + int8_t SFRSilCU_reserved5; // [-] Bits= 8 + + // Reserved + int8_t SFRSilCU_reserved6; // [-] Bits= 8 + + // Reserved + int8_t SFRSilCU_reserved7; // [-] Bits= 8 + +#else + + // Module state: + // 0 - Module is ready for action + // 1 - Module has done a scenario + // 2 - Module made a special event + // 3 - Data is recieved + // 4 - Module start error + // 5 - Scenario play error + // 6 - Data error + // 7 - Temperature error + // 8 : "Scenario data message error" + // 9 : "Temperature error" + // 10 : "Channels power error" + // 7 : "Scenario play error" + // 6 : "Launch error" + // 5 : "Scenario Data is recieved" + // 4 : "Configuration is going" + // 3 : "Special event done" + // 2 : "Scenario have done" + // 1 : "Scenario is going" + // 0 : "Ready" + uint8_t SFRSilCU_Module_Stat; // Bits= 4 + + // Temperature value + int8_t SFRSilCU_ModuleTemperature_Val; // [-] Bits= 7 Unit:'�C' + + // Reserved + int8_t SFRSilCU_reserved1; // [-] Bits= 5 + + // Reserved + int8_t SFRSilCU_reserved2; // [-] Bits= 8 + + // Reserved + int8_t SFRSilCU_reserved3; // [-] Bits= 8 + + // Reserved + int8_t SFRSilCU_reserved4; // [-] Bits= 8 + + // Reserved + int8_t SFRSilCU_reserved5; // [-] Bits= 8 + + // Reserved + int8_t SFRSilCU_reserved6; // [-] Bits= 8 + + // Reserved + int8_t SFRSilCU_reserved7; // [-] Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} SFRSilCU_State_t; + +// def @SFLSilCU_State CAN Message (1499 0x5db) +#define SFLSilCU_State_IDE (0U) +#define SFLSilCU_State_DLC (8U) +#define SFLSilCU_State_CANID (0x5dbU) + +// Value tables for @SFLSilCU_Module_Stat signal + +#ifndef SFLSilCU_Module_Stat_SFLSilCU_State_Scenario_data_message_error +#define SFLSilCU_Module_Stat_SFLSilCU_State_Scenario_data_message_error (8) +#endif + +#ifndef SFLSilCU_Module_Stat_SFLSilCU_State_Temperature_error +#define SFLSilCU_Module_Stat_SFLSilCU_State_Temperature_error (9) +#endif + +#ifndef SFLSilCU_Module_Stat_SFLSilCU_State_Channels_power_error +#define SFLSilCU_Module_Stat_SFLSilCU_State_Channels_power_error (10) +#endif + +#ifndef SFLSilCU_Module_Stat_SFLSilCU_State_Scenario_play_error +#define SFLSilCU_Module_Stat_SFLSilCU_State_Scenario_play_error (7) +#endif + +#ifndef SFLSilCU_Module_Stat_SFLSilCU_State_Launch_error +#define SFLSilCU_Module_Stat_SFLSilCU_State_Launch_error (6) +#endif + +#ifndef SFLSilCU_Module_Stat_SFLSilCU_State_Scenario_Data_is_recieved +#define SFLSilCU_Module_Stat_SFLSilCU_State_Scenario_Data_is_recieved (5) +#endif + +#ifndef SFLSilCU_Module_Stat_SFLSilCU_State_Configuration_is_going +#define SFLSilCU_Module_Stat_SFLSilCU_State_Configuration_is_going (4) +#endif + +#ifndef SFLSilCU_Module_Stat_SFLSilCU_State_Special_event_done +#define SFLSilCU_Module_Stat_SFLSilCU_State_Special_event_done (3) +#endif + +#ifndef SFLSilCU_Module_Stat_SFLSilCU_State_Scenario_have_done +#define SFLSilCU_Module_Stat_SFLSilCU_State_Scenario_have_done (2) +#endif + +#ifndef SFLSilCU_Module_Stat_SFLSilCU_State_Scenario_is_going +#define SFLSilCU_Module_Stat_SFLSilCU_State_Scenario_is_going (1) +#endif + +#ifndef SFLSilCU_Module_Stat_SFLSilCU_State_Ready +#define SFLSilCU_Module_Stat_SFLSilCU_State_Ready (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Module state: + // 0 - Module is ready for action + // 1 - Module has done a scenario + // 2 - Module made a special event + // 3 - Data is recieved + // 4 - Module start error + // 5 - Scenario play error + // 6 - Data error + // 7 - Temperature error + // 8 : "Scenario data message error" + // 9 : "Temperature error" + // 10 : "Channels power error" + // 7 : "Scenario play error" + // 6 : "Launch error" + // 5 : "Scenario Data is recieved" + // 4 : "Configuration is going" + // 3 : "Special event done" + // 2 : "Scenario have done" + // 1 : "Scenario is going" + // 0 : "Ready" + uint8_t SFLSilCU_Module_Stat : 4; // Bits= 4 + + // Temperature value + int8_t SFLSilCU_ModuleTemperature_Val : 7; // [-] Bits= 7 Unit:'�C' + + // Reserved + int8_t SFLSilCU_reserved1 : 5; // [-] Bits= 5 + + // Reserved + int8_t SFLSilCU_reserved2; // [-] Bits= 8 + + // Reserved + int8_t SFLSilCU_reserved3; // [-] Bits= 8 + + // Reserved + int8_t SFLSilCU_reserved4; // [-] Bits= 8 + + // Reserved + int8_t SFLSilCU_reserved5; // [-] Bits= 8 + + // Reserved + int8_t SFLSilCU_reserved6; // [-] Bits= 8 + + // Reserved + int8_t SFLSilCU_reserved7; // [-] Bits= 8 + +#else + + // Module state: + // 0 - Module is ready for action + // 1 - Module has done a scenario + // 2 - Module made a special event + // 3 - Data is recieved + // 4 - Module start error + // 5 - Scenario play error + // 6 - Data error + // 7 - Temperature error + // 8 : "Scenario data message error" + // 9 : "Temperature error" + // 10 : "Channels power error" + // 7 : "Scenario play error" + // 6 : "Launch error" + // 5 : "Scenario Data is recieved" + // 4 : "Configuration is going" + // 3 : "Special event done" + // 2 : "Scenario have done" + // 1 : "Scenario is going" + // 0 : "Ready" + uint8_t SFLSilCU_Module_Stat; // Bits= 4 + + // Temperature value + int8_t SFLSilCU_ModuleTemperature_Val; // [-] Bits= 7 Unit:'�C' + + // Reserved + int8_t SFLSilCU_reserved1; // [-] Bits= 5 + + // Reserved + int8_t SFLSilCU_reserved2; // [-] Bits= 8 + + // Reserved + int8_t SFLSilCU_reserved3; // [-] Bits= 8 + + // Reserved + int8_t SFLSilCU_reserved4; // [-] Bits= 8 + + // Reserved + int8_t SFLSilCU_reserved5; // [-] Bits= 8 + + // Reserved + int8_t SFLSilCU_reserved6; // [-] Bits= 8 + + // Reserved + int8_t SFLSilCU_reserved7; // [-] Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} SFLSilCU_State_t; + +// def @RDRSilCU_State CAN Message (1513 0x5e9) +#define RDRSilCU_State_IDE (0U) +#define RDRSilCU_State_DLC (8U) +#define RDRSilCU_State_CANID (0x5e9U) + +// Value tables for @RDRSilCU_Module_Stat signal + +#ifndef RDRSilCU_Module_Stat_RDRSilCU_State_Scenario_data_message_error +#define RDRSilCU_Module_Stat_RDRSilCU_State_Scenario_data_message_error (8) +#endif + +#ifndef RDRSilCU_Module_Stat_RDRSilCU_State_Temperature_error +#define RDRSilCU_Module_Stat_RDRSilCU_State_Temperature_error (9) +#endif + +#ifndef RDRSilCU_Module_Stat_RDRSilCU_State_Channels_power_error +#define RDRSilCU_Module_Stat_RDRSilCU_State_Channels_power_error (10) +#endif + +#ifndef RDRSilCU_Module_Stat_RDRSilCU_State_Scenario_play_error +#define RDRSilCU_Module_Stat_RDRSilCU_State_Scenario_play_error (7) +#endif + +#ifndef RDRSilCU_Module_Stat_RDRSilCU_State_Launch_error +#define RDRSilCU_Module_Stat_RDRSilCU_State_Launch_error (6) +#endif + +#ifndef RDRSilCU_Module_Stat_RDRSilCU_State_Scenario_Data_is_recieved +#define RDRSilCU_Module_Stat_RDRSilCU_State_Scenario_Data_is_recieved (5) +#endif + +#ifndef RDRSilCU_Module_Stat_RDRSilCU_State_Configuration_is_going +#define RDRSilCU_Module_Stat_RDRSilCU_State_Configuration_is_going (4) +#endif + +#ifndef RDRSilCU_Module_Stat_RDRSilCU_State_Special_event_done +#define RDRSilCU_Module_Stat_RDRSilCU_State_Special_event_done (3) +#endif + +#ifndef RDRSilCU_Module_Stat_RDRSilCU_State_Scenario_have_done +#define RDRSilCU_Module_Stat_RDRSilCU_State_Scenario_have_done (2) +#endif + +#ifndef RDRSilCU_Module_Stat_RDRSilCU_State_Scenario_is_going +#define RDRSilCU_Module_Stat_RDRSilCU_State_Scenario_is_going (1) +#endif + +#ifndef RDRSilCU_Module_Stat_RDRSilCU_State_Ready +#define RDRSilCU_Module_Stat_RDRSilCU_State_Ready (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Module state: + // 0 - Module is ready for action + // 1 - Module has done a scenario + // 2 - Module made a special event + // 3 - Data is recieved + // 4 - Module start error + // 5 - Scenario play error + // 6 - Data error + // 7 - Temperature error + // 8 : "Scenario data message error" + // 9 : "Temperature error" + // 10 : "Channels power error" + // 7 : "Scenario play error" + // 6 : "Launch error" + // 5 : "Scenario Data is recieved" + // 4 : "Configuration is going" + // 3 : "Special event done" + // 2 : "Scenario have done" + // 1 : "Scenario is going" + // 0 : "Ready" + int8_t RDRSilCU_Module_Stat : 4; // [-] Bits= 4 + + // Temperature value + int8_t RDRSilCU_ModuleTemperature_Val : 7; // [-] Bits= 7 Unit:'�C' + + // Reserved + int8_t RDRSilCU_reserved1 : 5; // [-] Bits= 5 + + // Reserved + int8_t RDRSilCU_reserved2; // [-] Bits= 8 + + // Reserved + int8_t RDRSilCU_reserved3; // [-] Bits= 8 + + // Reserved + int8_t RDRSilCU_reserved4; // [-] Bits= 8 + + // Reserved + int8_t RDRSilCU_reserved5; // [-] Bits= 8 + + // Reserved + int8_t RDRSilCU_reserved6; // [-] Bits= 8 + + // Reserved + int8_t RDRSilCU_reserved7; // [-] Bits= 8 + +#else + + // Module state: + // 0 - Module is ready for action + // 1 - Module has done a scenario + // 2 - Module made a special event + // 3 - Data is recieved + // 4 - Module start error + // 5 - Scenario play error + // 6 - Data error + // 7 - Temperature error + // 8 : "Scenario data message error" + // 9 : "Temperature error" + // 10 : "Channels power error" + // 7 : "Scenario play error" + // 6 : "Launch error" + // 5 : "Scenario Data is recieved" + // 4 : "Configuration is going" + // 3 : "Special event done" + // 2 : "Scenario have done" + // 1 : "Scenario is going" + // 0 : "Ready" + int8_t RDRSilCU_Module_Stat; // [-] Bits= 4 + + // Temperature value + int8_t RDRSilCU_ModuleTemperature_Val; // [-] Bits= 7 Unit:'�C' + + // Reserved + int8_t RDRSilCU_reserved1; // [-] Bits= 5 + + // Reserved + int8_t RDRSilCU_reserved2; // [-] Bits= 8 + + // Reserved + int8_t RDRSilCU_reserved3; // [-] Bits= 8 + + // Reserved + int8_t RDRSilCU_reserved4; // [-] Bits= 8 + + // Reserved + int8_t RDRSilCU_reserved5; // [-] Bits= 8 + + // Reserved + int8_t RDRSilCU_reserved6; // [-] Bits= 8 + + // Reserved + int8_t RDRSilCU_reserved7; // [-] Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} RDRSilCU_State_t; + +// def @FCSilCU_State CAN Message (1514 0x5ea) +#define FCSilCU_State_IDE (0U) +#define FCSilCU_State_DLC (8U) +#define FCSilCU_State_CANID (0x5eaU) + +// Value tables for @FCSilCU_Module_Stat signal + +#ifndef FCSilCU_Module_Stat_FCSilCU_State_Scenario_data_message_error +#define FCSilCU_Module_Stat_FCSilCU_State_Scenario_data_message_error (8) +#endif + +#ifndef FCSilCU_Module_Stat_FCSilCU_State_Temperature_error +#define FCSilCU_Module_Stat_FCSilCU_State_Temperature_error (9) +#endif + +#ifndef FCSilCU_Module_Stat_FCSilCU_State_Channels_power_error +#define FCSilCU_Module_Stat_FCSilCU_State_Channels_power_error (10) +#endif + +#ifndef FCSilCU_Module_Stat_FCSilCU_State_Scenario_play_error +#define FCSilCU_Module_Stat_FCSilCU_State_Scenario_play_error (7) +#endif + +#ifndef FCSilCU_Module_Stat_FCSilCU_State_Launch_error +#define FCSilCU_Module_Stat_FCSilCU_State_Launch_error (6) +#endif + +#ifndef FCSilCU_Module_Stat_FCSilCU_State_Scenario_Data_is_recieved +#define FCSilCU_Module_Stat_FCSilCU_State_Scenario_Data_is_recieved (5) +#endif + +#ifndef FCSilCU_Module_Stat_FCSilCU_State_Configuration_is_going +#define FCSilCU_Module_Stat_FCSilCU_State_Configuration_is_going (4) +#endif + +#ifndef FCSilCU_Module_Stat_FCSilCU_State_Special_event_done +#define FCSilCU_Module_Stat_FCSilCU_State_Special_event_done (3) +#endif + +#ifndef FCSilCU_Module_Stat_FCSilCU_State_Scenario_have_done +#define FCSilCU_Module_Stat_FCSilCU_State_Scenario_have_done (2) +#endif + +#ifndef FCSilCU_Module_Stat_FCSilCU_State_Scenario_is_going +#define FCSilCU_Module_Stat_FCSilCU_State_Scenario_is_going (1) +#endif + +#ifndef FCSilCU_Module_Stat_FCSilCU_State_Ready +#define FCSilCU_Module_Stat_FCSilCU_State_Ready (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Module state: + // 0 - Module is ready for action + // 1 - Module has done a scenario + // 2 - Module made a special event + // 3 - Data is recieved + // 4 - Module start error + // 5 - Scenario play error + // 6 - Data error + // 7 - Temperature error + // 8 : "Scenario data message error" + // 9 : "Temperature error" + // 10 : "Channels power error" + // 7 : "Scenario play error" + // 6 : "Launch error" + // 5 : "Scenario Data is recieved" + // 4 : "Configuration is going" + // 3 : "Special event done" + // 2 : "Scenario have done" + // 1 : "Scenario is going" + // 0 : "Ready" + int8_t FCSilCU_Module_Stat : 4; // [-] Bits= 4 + + // Temperature value + uint8_t FCSilCU_ModuleTemperature_Val : 7; // Bits= 7 + + // Reserved + int8_t FCSilCU_reserved1 : 5; // [-] Bits= 5 + + // Reserved + int8_t FCSilCU_reserved2; // [-] Bits= 8 + + // Reserved + int8_t FCSilCU_reserved3; // [-] Bits= 8 + + // Reserved + int8_t FCSilCU_reserved4; // [-] Bits= 8 + + // Reserved + int8_t FCSilCU_reserved5; // [-] Bits= 8 + + // Reserved + int8_t FCSilCU_reserved6; // [-] Bits= 8 + + // Reserved + int8_t FCSilCU_reserved7; // [-] Bits= 8 + +#else + + // Module state: + // 0 - Module is ready for action + // 1 - Module has done a scenario + // 2 - Module made a special event + // 3 - Data is recieved + // 4 - Module start error + // 5 - Scenario play error + // 6 - Data error + // 7 - Temperature error + // 8 : "Scenario data message error" + // 9 : "Temperature error" + // 10 : "Channels power error" + // 7 : "Scenario play error" + // 6 : "Launch error" + // 5 : "Scenario Data is recieved" + // 4 : "Configuration is going" + // 3 : "Special event done" + // 2 : "Scenario have done" + // 1 : "Scenario is going" + // 0 : "Ready" + int8_t FCSilCU_Module_Stat; // [-] Bits= 4 + + // Temperature value + uint8_t FCSilCU_ModuleTemperature_Val; // Bits= 7 + + // Reserved + int8_t FCSilCU_reserved1; // [-] Bits= 5 + + // Reserved + int8_t FCSilCU_reserved2; // [-] Bits= 8 + + // Reserved + int8_t FCSilCU_reserved3; // [-] Bits= 8 + + // Reserved + int8_t FCSilCU_reserved4; // [-] Bits= 8 + + // Reserved + int8_t FCSilCU_reserved5; // [-] Bits= 8 + + // Reserved + int8_t FCSilCU_reserved6; // [-] Bits= 8 + + // Reserved + int8_t FCSilCU_reserved7; // [-] Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} FCSilCU_State_t; + +// def @RCLSilCU_State CAN Message (1515 0x5eb) +#define RCLSilCU_State_IDE (0U) +#define RCLSilCU_State_DLC (8U) +#define RCLSilCU_State_CANID (0x5ebU) + +// Value tables for @RCLSilCU_Module_Stat signal + +#ifndef RCLSilCU_Module_Stat_RCLSilCU_State_Scenario_data_message_error +#define RCLSilCU_Module_Stat_RCLSilCU_State_Scenario_data_message_error (8) +#endif + +#ifndef RCLSilCU_Module_Stat_RCLSilCU_State_Temperature_error +#define RCLSilCU_Module_Stat_RCLSilCU_State_Temperature_error (9) +#endif + +#ifndef RCLSilCU_Module_Stat_RCLSilCU_State_Channels_power_error +#define RCLSilCU_Module_Stat_RCLSilCU_State_Channels_power_error (10) +#endif + +#ifndef RCLSilCU_Module_Stat_RCLSilCU_State_Scenario_play_error +#define RCLSilCU_Module_Stat_RCLSilCU_State_Scenario_play_error (7) +#endif + +#ifndef RCLSilCU_Module_Stat_RCLSilCU_State_Launch_error +#define RCLSilCU_Module_Stat_RCLSilCU_State_Launch_error (6) +#endif + +#ifndef RCLSilCU_Module_Stat_RCLSilCU_State_Scenario_Data_is_recieved +#define RCLSilCU_Module_Stat_RCLSilCU_State_Scenario_Data_is_recieved (5) +#endif + +#ifndef RCLSilCU_Module_Stat_RCLSilCU_State_Configuration_is_going +#define RCLSilCU_Module_Stat_RCLSilCU_State_Configuration_is_going (4) +#endif + +#ifndef RCLSilCU_Module_Stat_RCLSilCU_State_Special_event_done +#define RCLSilCU_Module_Stat_RCLSilCU_State_Special_event_done (3) +#endif + +#ifndef RCLSilCU_Module_Stat_RCLSilCU_State_Scenario_have_done +#define RCLSilCU_Module_Stat_RCLSilCU_State_Scenario_have_done (2) +#endif + +#ifndef RCLSilCU_Module_Stat_RCLSilCU_State_Scenario_is_going +#define RCLSilCU_Module_Stat_RCLSilCU_State_Scenario_is_going (1) +#endif + +#ifndef RCLSilCU_Module_Stat_RCLSilCU_State_Ready +#define RCLSilCU_Module_Stat_RCLSilCU_State_Ready (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Module state: + // 0 - Module is ready for action + // 1 - Module has done a scenario + // 2 - Module made a special event + // 3 - Data is recieved + // 4 - Module start error + // 5 - Scenario play error + // 6 - Data error + // 7 - Temperature error + // 8 : "Scenario data message error" + // 9 : "Temperature error" + // 10 : "Channels power error" + // 7 : "Scenario play error" + // 6 : "Launch error" + // 5 : "Scenario Data is recieved" + // 4 : "Configuration is going" + // 3 : "Special event done" + // 2 : "Scenario have done" + // 1 : "Scenario is going" + // 0 : "Ready" + int8_t RCLSilCU_Module_Stat : 4; // [-] Bits= 4 + + // Temperature value + int8_t RCLSilCU_ModuleTemperature_Val : 7; // [-] Bits= 7 Unit:'�C' + + // Reserved + int8_t RCLSilCU_reserved1 : 5; // [-] Bits= 5 + + // Reserved + int8_t RCLSilCU_reserved2; // [-] Bits= 8 + + // Reserved + int8_t RCLSilCU_reserved3; // [-] Bits= 8 + + // Reserved + int8_t RCLSilCU_reserved4; // [-] Bits= 8 + + // Reserved + int8_t RCLSilCU_reserved5; // [-] Bits= 8 + + // Reserved + int8_t RCLSilCU_reserved6; // [-] Bits= 8 + + // Reserved + int8_t RCLSilCU_reserved7; // [-] Bits= 8 + +#else + + // Module state: + // 0 - Module is ready for action + // 1 - Module has done a scenario + // 2 - Module made a special event + // 3 - Data is recieved + // 4 - Module start error + // 5 - Scenario play error + // 6 - Data error + // 7 - Temperature error + // 8 : "Scenario data message error" + // 9 : "Temperature error" + // 10 : "Channels power error" + // 7 : "Scenario play error" + // 6 : "Launch error" + // 5 : "Scenario Data is recieved" + // 4 : "Configuration is going" + // 3 : "Special event done" + // 2 : "Scenario have done" + // 1 : "Scenario is going" + // 0 : "Ready" + int8_t RCLSilCU_Module_Stat; // [-] Bits= 4 + + // Temperature value + int8_t RCLSilCU_ModuleTemperature_Val; // [-] Bits= 7 Unit:'�C' + + // Reserved + int8_t RCLSilCU_reserved1; // [-] Bits= 5 + + // Reserved + int8_t RCLSilCU_reserved2; // [-] Bits= 8 + + // Reserved + int8_t RCLSilCU_reserved3; // [-] Bits= 8 + + // Reserved + int8_t RCLSilCU_reserved4; // [-] Bits= 8 + + // Reserved + int8_t RCLSilCU_reserved5; // [-] Bits= 8 + + // Reserved + int8_t RCLSilCU_reserved6; // [-] Bits= 8 + + // Reserved + int8_t RCLSilCU_reserved7; // [-] Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} RCLSilCU_State_t; + +// def @RCRSilCU_State CAN Message (1516 0x5ec) +#define RCRSilCU_State_IDE (0U) +#define RCRSilCU_State_DLC (8U) +#define RCRSilCU_State_CANID (0x5ecU) + +// Value tables for @RCRSilCU_Module_Stat signal + +#ifndef RCRSilCU_Module_Stat_RCRSilCU_State_Scenario_data_message_error +#define RCRSilCU_Module_Stat_RCRSilCU_State_Scenario_data_message_error (8) +#endif + +#ifndef RCRSilCU_Module_Stat_RCRSilCU_State_Temperature_error +#define RCRSilCU_Module_Stat_RCRSilCU_State_Temperature_error (9) +#endif + +#ifndef RCRSilCU_Module_Stat_RCRSilCU_State_Channels_power_error +#define RCRSilCU_Module_Stat_RCRSilCU_State_Channels_power_error (10) +#endif + +#ifndef RCRSilCU_Module_Stat_RCRSilCU_State_Scenario_play_error +#define RCRSilCU_Module_Stat_RCRSilCU_State_Scenario_play_error (7) +#endif + +#ifndef RCRSilCU_Module_Stat_RCRSilCU_State_Launch_error +#define RCRSilCU_Module_Stat_RCRSilCU_State_Launch_error (6) +#endif + +#ifndef RCRSilCU_Module_Stat_RCRSilCU_State_Scenario_Data_is_recieved +#define RCRSilCU_Module_Stat_RCRSilCU_State_Scenario_Data_is_recieved (5) +#endif + +#ifndef RCRSilCU_Module_Stat_RCRSilCU_State_Configuration_is_going +#define RCRSilCU_Module_Stat_RCRSilCU_State_Configuration_is_going (4) +#endif + +#ifndef RCRSilCU_Module_Stat_RCRSilCU_State_Special_event_done +#define RCRSilCU_Module_Stat_RCRSilCU_State_Special_event_done (3) +#endif + +#ifndef RCRSilCU_Module_Stat_RCRSilCU_State_Scenario_have_done +#define RCRSilCU_Module_Stat_RCRSilCU_State_Scenario_have_done (2) +#endif + +#ifndef RCRSilCU_Module_Stat_RCRSilCU_State_Scenario_is_going +#define RCRSilCU_Module_Stat_RCRSilCU_State_Scenario_is_going (1) +#endif + +#ifndef RCRSilCU_Module_Stat_RCRSilCU_State_Ready +#define RCRSilCU_Module_Stat_RCRSilCU_State_Ready (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Module state: + // 0 - Module is ready for action + // 1 - Module has done a scenario + // 2 - Module made a special event + // 3 - Data is recieved + // 4 - Module start error + // 5 - Scenario play error + // 6 - Data error + // 7 - Temperature error + // 8 : "Scenario data message error" + // 9 : "Temperature error" + // 10 : "Channels power error" + // 7 : "Scenario play error" + // 6 : "Launch error" + // 5 : "Scenario Data is recieved" + // 4 : "Configuration is going" + // 3 : "Special event done" + // 2 : "Scenario have done" + // 1 : "Scenario is going" + // 0 : "Ready" + int8_t RCRSilCU_Module_Stat : 4; // [-] Bits= 4 + + // Temperature value + int8_t RCRSilCU_ModuleTemperature_Val : 7; // [-] Bits= 7 Unit:'�C' + + // Reserved + int8_t RCRSilCU_reserved1 : 5; // [-] Bits= 5 + + // Reserved + int8_t RCRSilCU_reserved2; // [-] Bits= 8 + + // Reserved + int8_t RCRSilCU_reserved3; // [-] Bits= 8 + + // Reserved + int8_t RCRSilCU_reserved4; // [-] Bits= 8 + + // Reserved + int8_t RCRSilCU_reserved5; // [-] Bits= 8 + + // Reserved + int8_t RCRSilCU_reserved6; // [-] Bits= 8 + + // Reserved + int8_t RCRSilCU_reserved7; // [-] Bits= 8 + +#else + + // Module state: + // 0 - Module is ready for action + // 1 - Module has done a scenario + // 2 - Module made a special event + // 3 - Data is recieved + // 4 - Module start error + // 5 - Scenario play error + // 6 - Data error + // 7 - Temperature error + // 8 : "Scenario data message error" + // 9 : "Temperature error" + // 10 : "Channels power error" + // 7 : "Scenario play error" + // 6 : "Launch error" + // 5 : "Scenario Data is recieved" + // 4 : "Configuration is going" + // 3 : "Special event done" + // 2 : "Scenario have done" + // 1 : "Scenario is going" + // 0 : "Ready" + int8_t RCRSilCU_Module_Stat; // [-] Bits= 4 + + // Temperature value + int8_t RCRSilCU_ModuleTemperature_Val; // [-] Bits= 7 Unit:'�C' + + // Reserved + int8_t RCRSilCU_reserved1; // [-] Bits= 5 + + // Reserved + int8_t RCRSilCU_reserved2; // [-] Bits= 8 + + // Reserved + int8_t RCRSilCU_reserved3; // [-] Bits= 8 + + // Reserved + int8_t RCRSilCU_reserved4; // [-] Bits= 8 + + // Reserved + int8_t RCRSilCU_reserved5; // [-] Bits= 8 + + // Reserved + int8_t RCRSilCU_reserved6; // [-] Bits= 8 + + // Reserved + int8_t RCRSilCU_reserved7; // [-] Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} RCRSilCU_State_t; + +// def @RDLSilCU_State CAN Message (1517 0x5ed) +#define RDLSilCU_State_IDE (0U) +#define RDLSilCU_State_DLC (8U) +#define RDLSilCU_State_CANID (0x5edU) + +// Value tables for @RDLSilCU_Module_Stat signal + +#ifndef RDLSilCU_Module_Stat_RDLSilCU_State_Scenario_data_message_error +#define RDLSilCU_Module_Stat_RDLSilCU_State_Scenario_data_message_error (8) +#endif + +#ifndef RDLSilCU_Module_Stat_RDLSilCU_State_Temperature_error +#define RDLSilCU_Module_Stat_RDLSilCU_State_Temperature_error (9) +#endif + +#ifndef RDLSilCU_Module_Stat_RDLSilCU_State_Channels_power_error +#define RDLSilCU_Module_Stat_RDLSilCU_State_Channels_power_error (10) +#endif + +#ifndef RDLSilCU_Module_Stat_RDLSilCU_State_Scenario_play_error +#define RDLSilCU_Module_Stat_RDLSilCU_State_Scenario_play_error (7) +#endif + +#ifndef RDLSilCU_Module_Stat_RDLSilCU_State_Launch_error +#define RDLSilCU_Module_Stat_RDLSilCU_State_Launch_error (6) +#endif + +#ifndef RDLSilCU_Module_Stat_RDLSilCU_State_Scenario_Data_is_recieved +#define RDLSilCU_Module_Stat_RDLSilCU_State_Scenario_Data_is_recieved (5) +#endif + +#ifndef RDLSilCU_Module_Stat_RDLSilCU_State_Configuration_is_going +#define RDLSilCU_Module_Stat_RDLSilCU_State_Configuration_is_going (4) +#endif + +#ifndef RDLSilCU_Module_Stat_RDLSilCU_State_Special_event_done +#define RDLSilCU_Module_Stat_RDLSilCU_State_Special_event_done (3) +#endif + +#ifndef RDLSilCU_Module_Stat_RDLSilCU_State_Scenario_have_done +#define RDLSilCU_Module_Stat_RDLSilCU_State_Scenario_have_done (2) +#endif + +#ifndef RDLSilCU_Module_Stat_RDLSilCU_State_Scenario_is_going +#define RDLSilCU_Module_Stat_RDLSilCU_State_Scenario_is_going (1) +#endif + +#ifndef RDLSilCU_Module_Stat_RDLSilCU_State_Ready +#define RDLSilCU_Module_Stat_RDLSilCU_State_Ready (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Module state: + // 0 - Module is ready for action + // 1 - Module has done a scenario 2 - Module made a special event 3 - Data is recieved 4 - Module start error 5 - Scenario play error 6 - Data error 7 - Temperature error + // 8 : "Scenario data message error" + // 9 : "Temperature error" + // 10 : "Channels power error" + // 7 : "Scenario play error" + // 6 : "Launch error" + // 5 : "Scenario Data is recieved" + // 4 : "Configuration is going" + // 3 : "Special event done" + // 2 : "Scenario have done" + // 1 : "Scenario is going" + // 0 : "Ready" + int8_t RDLSilCU_Module_Stat : 4; // [-] Bits= 4 + + // Temperature value + int8_t RDLSilCU_ModuleTemperature_Val : 7; // [-] Bits= 7 Unit:'�C' + + // Reserved + int8_t RDLSilCU_reserved1 : 5; // [-] Bits= 5 + + // Reserved + int8_t RDLSilCU_reserved2; // [-] Bits= 8 + + // Reserved + int8_t RDLSilCU_reserved3; // [-] Bits= 8 + + // Reserved + int8_t RDLSilCU_reserved4; // [-] Bits= 8 + + // Reserved + int8_t RDLSilCU_reserved5; // [-] Bits= 8 + + // Reserved + int8_t RDLSilCU_reserved6; // [-] Bits= 8 + + // Reserved + int8_t RDLSilCU_reserved7; // [-] Bits= 8 + +#else + + // Module state: + // 0 - Module is ready for action + // 1 - Module has done a scenario 2 - Module made a special event 3 - Data is recieved 4 - Module start error 5 - Scenario play error 6 - Data error 7 - Temperature error + // 8 : "Scenario data message error" + // 9 : "Temperature error" + // 10 : "Channels power error" + // 7 : "Scenario play error" + // 6 : "Launch error" + // 5 : "Scenario Data is recieved" + // 4 : "Configuration is going" + // 3 : "Special event done" + // 2 : "Scenario have done" + // 1 : "Scenario is going" + // 0 : "Ready" + int8_t RDLSilCU_Module_Stat; // [-] Bits= 4 + + // Temperature value + int8_t RDLSilCU_ModuleTemperature_Val; // [-] Bits= 7 Unit:'�C' + + // Reserved + int8_t RDLSilCU_reserved1; // [-] Bits= 5 + + // Reserved + int8_t RDLSilCU_reserved2; // [-] Bits= 8 + + // Reserved + int8_t RDLSilCU_reserved3; // [-] Bits= 8 + + // Reserved + int8_t RDLSilCU_reserved4; // [-] Bits= 8 + + // Reserved + int8_t RDLSilCU_reserved5; // [-] Bits= 8 + + // Reserved + int8_t RDLSilCU_reserved6; // [-] Bits= 8 + + // Reserved + int8_t RDLSilCU_reserved7; // [-] Bits= 8 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} RDLSilCU_State_t; + +// def @CCPF_BodyTM_Stat CAN Message (1519 0x5ef) +#define CCPF_BodyTM_Stat_IDE (0U) +#define CCPF_BodyTM_Stat_DLC (3U) +#define CCPF_BodyTM_Stat_CANID (0x5efU) +#define CCPF_BodyTM_Stat_CYC (50U) + +// Value tables for @CCPF_AutoButtonL_Stat signal + +#ifndef CCPF_AutoButtonL_Stat_CCPF_BodyTM_Stat_Button_hold_pressed +#define CCPF_AutoButtonL_Stat_CCPF_BodyTM_Stat_Button_hold_pressed (2) +#endif + +#ifndef CCPF_AutoButtonL_Stat_CCPF_BodyTM_Stat_Button_pressed +#define CCPF_AutoButtonL_Stat_CCPF_BodyTM_Stat_Button_pressed (1) +#endif + +#ifndef CCPF_AutoButtonL_Stat_CCPF_BodyTM_Stat_Button_released +#define CCPF_AutoButtonL_Stat_CCPF_BodyTM_Stat_Button_released (0) +#endif + + +// Value tables for @CCPF_TempToggleL_Stat signal + +#ifndef CCPF_TempToggleL_Stat_CCPF_BodyTM_Stat_Toggle_hold_lowered_ +#define CCPF_TempToggleL_Stat_CCPF_BodyTM_Stat_Toggle_hold_lowered_ (4) +#endif + +#ifndef CCPF_TempToggleL_Stat_CCPF_BodyTM_Stat_Toggle_hold_raised_ +#define CCPF_TempToggleL_Stat_CCPF_BodyTM_Stat_Toggle_hold_raised_ (3) +#endif + +#ifndef CCPF_TempToggleL_Stat_CCPF_BodyTM_Stat_Toggle_lowered +#define CCPF_TempToggleL_Stat_CCPF_BodyTM_Stat_Toggle_lowered (2) +#endif + +#ifndef CCPF_TempToggleL_Stat_CCPF_BodyTM_Stat_Toggle_raised +#define CCPF_TempToggleL_Stat_CCPF_BodyTM_Stat_Toggle_raised (1) +#endif + +#ifndef CCPF_TempToggleL_Stat_CCPF_BodyTM_Stat_Toggle_released +#define CCPF_TempToggleL_Stat_CCPF_BodyTM_Stat_Toggle_released (0) +#endif + + +// Value tables for @CCPF_RecButton_Stat signal + +#ifndef CCPF_RecButton_Stat_CCPF_BodyTM_Stat_Button_hold_pressed +#define CCPF_RecButton_Stat_CCPF_BodyTM_Stat_Button_hold_pressed (2) +#endif + +#ifndef CCPF_RecButton_Stat_CCPF_BodyTM_Stat_Button_pressed +#define CCPF_RecButton_Stat_CCPF_BodyTM_Stat_Button_pressed (1) +#endif + +#ifndef CCPF_RecButton_Stat_CCPF_BodyTM_Stat_Button_released +#define CCPF_RecButton_Stat_CCPF_BodyTM_Stat_Button_released (0) +#endif + + +// Value tables for @CCPF_FWindowHeatSw_Stat signal + +#ifndef CCPF_FWindowHeatSw_Stat_CCPF_BodyTM_Stat_Pressed +#define CCPF_FWindowHeatSw_Stat_CCPF_BodyTM_Stat_Pressed (1) +#endif + +#ifndef CCPF_FWindowHeatSw_Stat_CCPF_BodyTM_Stat_Not_pressed +#define CCPF_FWindowHeatSw_Stat_CCPF_BodyTM_Stat_Not_pressed (0) +#endif + + +// Value tables for @CCPF_AutoButtonR_Stat signal + +#ifndef CCPF_AutoButtonR_Stat_CCPF_BodyTM_Stat_Button_hold_pressed +#define CCPF_AutoButtonR_Stat_CCPF_BodyTM_Stat_Button_hold_pressed (2) +#endif + +#ifndef CCPF_AutoButtonR_Stat_CCPF_BodyTM_Stat_Button_Pressed +#define CCPF_AutoButtonR_Stat_CCPF_BodyTM_Stat_Button_Pressed (1) +#endif + +#ifndef CCPF_AutoButtonR_Stat_CCPF_BodyTM_Stat_Button_Released +#define CCPF_AutoButtonR_Stat_CCPF_BodyTM_Stat_Button_Released (0) +#endif + + +// Value tables for @CCPF_MuteSw_Stat signal + +#ifndef CCPF_MuteSw_Stat_CCPF_BodyTM_Stat_MMS_ONOFF_requested +#define CCPF_MuteSw_Stat_CCPF_BodyTM_Stat_MMS_ONOFF_requested (2) +#endif + +#ifndef CCPF_MuteSw_Stat_CCPF_BodyTM_Stat_Mute_ONOFF_requested +#define CCPF_MuteSw_Stat_CCPF_BodyTM_Stat_Mute_ONOFF_requested (1) +#endif + +#ifndef CCPF_MuteSw_Stat_CCPF_BodyTM_Stat_Not_requested +#define CCPF_MuteSw_Stat_CCPF_BodyTM_Stat_Not_requested (0) +#endif + + +// Value tables for @CCPF_RWindowHeatSw_Stat signal + +#ifndef CCPF_RWindowHeatSw_Stat_CCPF_BodyTM_Stat_Pressed +#define CCPF_RWindowHeatSw_Stat_CCPF_BodyTM_Stat_Pressed (1) +#endif + +#ifndef CCPF_RWindowHeatSw_Stat_CCPF_BodyTM_Stat_Not_pressed +#define CCPF_RWindowHeatSw_Stat_CCPF_BodyTM_Stat_Not_pressed (0) +#endif + + +// Value tables for @CCPF_TempToggleR_Stat signal + +#ifndef CCPF_TempToggleR_Stat_CCPF_BodyTM_Stat_Toggle_hold_lowered_ +#define CCPF_TempToggleR_Stat_CCPF_BodyTM_Stat_Toggle_hold_lowered_ (4) +#endif + +#ifndef CCPF_TempToggleR_Stat_CCPF_BodyTM_Stat_Toggle_hold_raised_ +#define CCPF_TempToggleR_Stat_CCPF_BodyTM_Stat_Toggle_hold_raised_ (3) +#endif + +#ifndef CCPF_TempToggleR_Stat_CCPF_BodyTM_Stat_Toggle_lowered +#define CCPF_TempToggleR_Stat_CCPF_BodyTM_Stat_Toggle_lowered (2) +#endif + +#ifndef CCPF_TempToggleR_Stat_CCPF_BodyTM_Stat_Toggle_raised +#define CCPF_TempToggleR_Stat_CCPF_BodyTM_Stat_Toggle_raised (1) +#endif + +#ifndef CCPF_TempToggleR_Stat_CCPF_BodyTM_Stat_Toggle_released +#define CCPF_TempToggleR_Stat_CCPF_BodyTM_Stat_Toggle_released (0) +#endif + + +// Value tables for @CCPF_VolAjustSw_Stat signal + +#ifndef CCPF_VolAjustSw_Stat_CCPF_BodyTM_Stat_Volume_ +#define CCPF_VolAjustSw_Stat_CCPF_BodyTM_Stat_Volume_ (2) +#endif + +#ifndef CCPF_VolAjustSw_Stat_CCPF_BodyTM_Stat_Volume_ +#define CCPF_VolAjustSw_Stat_CCPF_BodyTM_Stat_Volume_ (1) +#endif + +#ifndef CCPF_VolAjustSw_Stat_CCPF_BodyTM_Stat_Not_pressed +#define CCPF_VolAjustSw_Stat_CCPF_BodyTM_Stat_Not_pressed (0) +#endif + + +// Value tables for @CCPF_DefButton_Stat signal + +#ifndef CCPF_DefButton_Stat_CCPF_BodyTM_Stat_Button_hold_pressed +#define CCPF_DefButton_Stat_CCPF_BodyTM_Stat_Button_hold_pressed (2) +#endif + +#ifndef CCPF_DefButton_Stat_CCPF_BodyTM_Stat_Button_pressed +#define CCPF_DefButton_Stat_CCPF_BodyTM_Stat_Button_pressed (1) +#endif + +#ifndef CCPF_DefButton_Stat_CCPF_BodyTM_Stat_Button_released +#define CCPF_DefButton_Stat_CCPF_BodyTM_Stat_Button_released (0) +#endif + + +// Value tables for @CCPF_AcMaxButton_Stat signal + +#ifndef CCPF_AcMaxButton_Stat_CCPF_BodyTM_Stat_Button_hold_pressed_ +#define CCPF_AcMaxButton_Stat_CCPF_BodyTM_Stat_Button_hold_pressed_ (2) +#endif + +#ifndef CCPF_AcMaxButton_Stat_CCPF_BodyTM_Stat_Button_pressed +#define CCPF_AcMaxButton_Stat_CCPF_BodyTM_Stat_Button_pressed (1) +#endif + +#ifndef CCPF_AcMaxButton_Stat_CCPF_BodyTM_Stat_Button_released +#define CCPF_AcMaxButton_Stat_CCPF_BodyTM_Stat_Button_released (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Front climate panel left AUTO button status + // 2 : "Button hold pressed" + // 1 : "Button pressed" + // 0 : "Button released" + uint8_t CCPF_AutoButtonL_Stat : 2; // Bits= 2 + + // Front climate panel left TEMPERATURE toggle status + // 4 : "Toggle hold lowered " + // 3 : "Toggle hold raised " + // 2 : "Toggle lowered" + // 1 : "Toggle raised" + // 0 : "Toggle released" + uint8_t CCPF_TempToggleL_Stat : 3; // Bits= 3 + + // Front climate panel RECIRCULATION button status + // 2 : "Button hold pressed" + // 1 : "Button pressed" + // 0 : "Button released" + uint8_t CCPF_RecButton_Stat : 2; // Bits= 2 + + // Button status of the heated windshield, front door windows and side mirrors + // 1 : "Pressed" + // 0 : "Not pressed" + uint8_t CCPF_FWindowHeatSw_Stat : 1; // Bits= 1 + + // Front climate panel right AUTO button status + // 2 : "Button hold pressed" + // 1 : "Button Pressed" + // 0 : "Button Released" + uint8_t CCPF_AutoButtonR_Stat : 2; // Bits= 2 + + // Mute button status and display FIU + // 2 : "MMS ON/OFF requested" + // 1 : "Mute ON/OFF requested" + // 0 : "Not requested" + uint8_t CCPF_MuteSw_Stat : 2; // Bits= 2 + + // Rear window heating switch status + // 1 : "Pressed" + // 0 : "Not pressed" + uint8_t CCPF_RWindowHeatSw_Stat : 1; // Bits= 1 + + // Front climate panel right TEMPERATURE toggle status + // 4 : "Toggle hold lowered " + // 3 : "Toggle hold raised " + // 2 : "Toggle lowered" + // 1 : "Toggle raised" + // 0 : "Toggle released" + uint8_t CCPF_TempToggleR_Stat : 3; // Bits= 3 + + // Volume ajustment switch status + // 2 : "Volume -" + // 1 : "Volume +" + // 0 : "Not pressed" + uint8_t CCPF_VolAjustSw_Stat : 2; // Bits= 2 + + // Front climate panel DEFROST button status + // 2 : "Button hold pressed" + // 1 : "Button pressed" + // 0 : "Button released" + uint8_t CCPF_DefButton_Stat : 2; // Bits= 2 + + // Front climate panel AC MAX button status + // 2 : "Button hold pressed " + // 1 : "Button pressed" + // 0 : "Button released" + uint8_t CCPF_AcMaxButton_Stat : 2; // Bits= 2 + +#else + + // Front climate panel left AUTO button status + // 2 : "Button hold pressed" + // 1 : "Button pressed" + // 0 : "Button released" + uint8_t CCPF_AutoButtonL_Stat; // Bits= 2 + + // Front climate panel left TEMPERATURE toggle status + // 4 : "Toggle hold lowered " + // 3 : "Toggle hold raised " + // 2 : "Toggle lowered" + // 1 : "Toggle raised" + // 0 : "Toggle released" + uint8_t CCPF_TempToggleL_Stat; // Bits= 3 + + // Front climate panel RECIRCULATION button status + // 2 : "Button hold pressed" + // 1 : "Button pressed" + // 0 : "Button released" + uint8_t CCPF_RecButton_Stat; // Bits= 2 + + // Button status of the heated windshield, front door windows and side mirrors + // 1 : "Pressed" + // 0 : "Not pressed" + uint8_t CCPF_FWindowHeatSw_Stat; // Bits= 1 + + // Front climate panel right AUTO button status + // 2 : "Button hold pressed" + // 1 : "Button Pressed" + // 0 : "Button Released" + uint8_t CCPF_AutoButtonR_Stat; // Bits= 2 + + // Mute button status and display FIU + // 2 : "MMS ON/OFF requested" + // 1 : "Mute ON/OFF requested" + // 0 : "Not requested" + uint8_t CCPF_MuteSw_Stat; // Bits= 2 + + // Rear window heating switch status + // 1 : "Pressed" + // 0 : "Not pressed" + uint8_t CCPF_RWindowHeatSw_Stat; // Bits= 1 + + // Front climate panel right TEMPERATURE toggle status + // 4 : "Toggle hold lowered " + // 3 : "Toggle hold raised " + // 2 : "Toggle lowered" + // 1 : "Toggle raised" + // 0 : "Toggle released" + uint8_t CCPF_TempToggleR_Stat; // Bits= 3 + + // Volume ajustment switch status + // 2 : "Volume -" + // 1 : "Volume +" + // 0 : "Not pressed" + uint8_t CCPF_VolAjustSw_Stat; // Bits= 2 + + // Front climate panel DEFROST button status + // 2 : "Button hold pressed" + // 1 : "Button pressed" + // 0 : "Button released" + uint8_t CCPF_DefButton_Stat; // Bits= 2 + + // Front climate panel AC MAX button status + // 2 : "Button hold pressed " + // 1 : "Button pressed" + // 0 : "Button released" + uint8_t CCPF_AcMaxButton_Stat; // Bits= 2 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} CCPF_BodyTM_Stat_t; + +// def @IntCOM_Info_Stat CAN Message (1523 0x5f3) +#define IntCOM_Info_Stat_IDE (0U) +#define IntCOM_Info_Stat_DLC (2U) +#define IntCOM_Info_Stat_CANID (0x5f3U) +#define IntCOM_Info_Stat_CYC (100U) + +// Value tables for @IntCOM_PowerLed_Cmd signal + +#ifndef IntCOM_PowerLed_Cmd_IntCOM_Info_Stat_Call_accepted +#define IntCOM_PowerLed_Cmd_IntCOM_Info_Stat_Call_accepted (2) +#endif + +#ifndef IntCOM_PowerLed_Cmd_IntCOM_Info_Stat_Incoming_call +#define IntCOM_PowerLed_Cmd_IntCOM_Info_Stat_Incoming_call (1) +#endif + +#ifndef IntCOM_PowerLed_Cmd_IntCOM_Info_Stat_Intercom_Off +#define IntCOM_PowerLed_Cmd_IntCOM_Info_Stat_Intercom_Off (0) +#endif + + +// Value tables for @IntCOM_Intercom_Req signal + +#ifndef IntCOM_Intercom_Req_IntCOM_Info_Stat_Inactive +#define IntCOM_Intercom_Req_IntCOM_Info_Stat_Inactive (0) +#endif + +#ifndef IntCOM_Intercom_Req_IntCOM_Info_Stat_Active +#define IntCOM_Intercom_Req_IntCOM_Info_Stat_Active (1) +#endif + + +// Value tables for @IntCOM_Extercom_Req signal + +#ifndef IntCOM_Extercom_Req_IntCOM_Info_Stat_Inactive +#define IntCOM_Extercom_Req_IntCOM_Info_Stat_Inactive (0) +#endif + +#ifndef IntCOM_Extercom_Req_IntCOM_Info_Stat_Active +#define IntCOM_Extercom_Req_IntCOM_Info_Stat_Active (1) +#endif + + +// Value tables for @IntCOM_Mute_Req signal + +#ifndef IntCOM_Mute_Req_IntCOM_Info_Stat_Inactive +#define IntCOM_Mute_Req_IntCOM_Info_Stat_Inactive (0) +#endif + +#ifndef IntCOM_Mute_Req_IntCOM_Info_Stat_Active +#define IntCOM_Mute_Req_IntCOM_Info_Stat_Active (1) +#endif + + +// Value tables for @IntCom_MIC_FL signal + +#ifndef IntCom_MIC_FL_IntCOM_Info_Stat_Error +#define IntCom_MIC_FL_IntCOM_Info_Stat_Error (1) +#endif + +#ifndef IntCom_MIC_FL_IntCOM_Info_Stat_Active +#define IntCom_MIC_FL_IntCOM_Info_Stat_Active (0) +#endif + + +// Value tables for @IntCom_MIC_FR signal + +#ifndef IntCom_MIC_FR_IntCOM_Info_Stat_Error +#define IntCom_MIC_FR_IntCOM_Info_Stat_Error (1) +#endif + +#ifndef IntCom_MIC_FR_IntCOM_Info_Stat_Active +#define IntCom_MIC_FR_IntCOM_Info_Stat_Active (0) +#endif + + +// Value tables for @IntCom_MIC_RL signal + +#ifndef IntCom_MIC_RL_IntCOM_Info_Stat_Error +#define IntCom_MIC_RL_IntCOM_Info_Stat_Error (1) +#endif + +#ifndef IntCom_MIC_RL_IntCOM_Info_Stat_Active +#define IntCom_MIC_RL_IntCOM_Info_Stat_Active (0) +#endif + + +// Value tables for @IntCom_MIC_RR signal + +#ifndef IntCom_MIC_RR_IntCOM_Info_Stat_Error +#define IntCom_MIC_RR_IntCOM_Info_Stat_Error (1) +#endif + +#ifndef IntCom_MIC_RR_IntCOM_Info_Stat_Active +#define IntCom_MIC_RR_IntCOM_Info_Stat_Active (0) +#endif + + +// Value tables for @IntCOM_ExtcomLMIC_Req signal + +#ifndef IntCOM_ExtcomLMIC_Req_IntCOM_Info_Stat_Inactive +#define IntCOM_ExtcomLMIC_Req_IntCOM_Info_Stat_Inactive (0) +#endif + +#ifndef IntCOM_ExtcomLMIC_Req_IntCOM_Info_Stat_Active +#define IntCOM_ExtcomLMIC_Req_IntCOM_Info_Stat_Active (1) +#endif + + +// Value tables for @IntCOM_ExtcomRMIC_Req signal + +#ifndef IntCOM_ExtcomRMIC_Req_IntCOM_Info_Stat_Inactive +#define IntCOM_ExtcomRMIC_Req_IntCOM_Info_Stat_Inactive (0) +#endif + +#ifndef IntCOM_ExtcomRMIC_Req_IntCOM_Info_Stat_Active +#define IntCOM_ExtcomRMIC_Req_IntCOM_Info_Stat_Active (1) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Intercom power LED indicator command + // 2 : "Call accepted" + // 1 : "Incoming call" + // 0 : "Intercom Off" + uint8_t IntCOM_PowerLed_Cmd : 2; // Bits= 2 + + // Status of the switched on Intercom. + // 0 : "Inactive" + // 1 : "Active" + uint8_t IntCOM_Intercom_Req : 1; // Bits= 1 + + // Status of the switched on Extercom. + // 0 : "Inactive" + // 1 : "Active" + uint8_t IntCOM_Extercom_Req : 1; // Bits= 1 + + // Mute command + // 0x0 = Mute Inactive + // 0x1 = Mute Active + // 0 : "Inactive" + // 1 : "Active" + uint8_t IntCOM_Mute_Req : 1; // Bits= 1 + + // Status of the Driver microphone + // 1 : "Error" + // 0 : "Active" + uint8_t IntCom_MIC_FL : 1; // Bits= 1 + + // Status of the front right passenger microphone + // 1 : "Error" + // 0 : "Active" + uint8_t IntCom_MIC_FR : 1; // Bits= 1 + + // Status of the rear left passenger microphone + // 1 : "Error" + // 0 : "Active" + uint8_t IntCom_MIC_RL : 1; // Bits= 1 + + // Status of the Rear right passenger microphone + // 1 : "Error" + // 0 : "Active" + uint8_t IntCom_MIC_RR : 1; // Bits= 1 + + // Status of the left microphone on Extercom + // 0 : "Inactive" + // 1 : "Active" + uint8_t IntCOM_ExtcomLMIC_Req : 1; // Bits= 1 + + // Status of the right microphone on Extercom + // 0 : "Inactive" + // 1 : "Active" + uint8_t IntCOM_ExtcomRMIC_Req : 1; // Bits= 1 + +#else + + // Intercom power LED indicator command + // 2 : "Call accepted" + // 1 : "Incoming call" + // 0 : "Intercom Off" + uint8_t IntCOM_PowerLed_Cmd; // Bits= 2 + + // Status of the switched on Intercom. + // 0 : "Inactive" + // 1 : "Active" + uint8_t IntCOM_Intercom_Req; // Bits= 1 + + // Status of the switched on Extercom. + // 0 : "Inactive" + // 1 : "Active" + uint8_t IntCOM_Extercom_Req; // Bits= 1 + + // Mute command + // 0x0 = Mute Inactive + // 0x1 = Mute Active + // 0 : "Inactive" + // 1 : "Active" + uint8_t IntCOM_Mute_Req; // Bits= 1 + + // Status of the Driver microphone + // 1 : "Error" + // 0 : "Active" + uint8_t IntCom_MIC_FL; // Bits= 1 + + // Status of the front right passenger microphone + // 1 : "Error" + // 0 : "Active" + uint8_t IntCom_MIC_FR; // Bits= 1 + + // Status of the rear left passenger microphone + // 1 : "Error" + // 0 : "Active" + uint8_t IntCom_MIC_RL; // Bits= 1 + + // Status of the Rear right passenger microphone + // 1 : "Error" + // 0 : "Active" + uint8_t IntCom_MIC_RR; // Bits= 1 + + // Status of the left microphone on Extercom + // 0 : "Inactive" + // 1 : "Active" + uint8_t IntCOM_ExtcomLMIC_Req; // Bits= 1 + + // Status of the right microphone on Extercom + // 0 : "Inactive" + // 1 : "Active" + uint8_t IntCOM_ExtcomRMIC_Req; // Bits= 1 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} IntCOM_Info_Stat_t; + +// def @LTE_Sum_State2 CAN Message (1527 0x5f7) +#define LTE_Sum_State2_IDE (0U) +#define LTE_Sum_State2_DLC (8U) +#define LTE_Sum_State2_CANID (0x5f7U) + +// Value tables for @LTE_FrameCode_Stat signal + +#ifndef LTE_FrameCode_Stat_LTE_Sum_State2_Flow_control_frame +#define LTE_FrameCode_Stat_LTE_Sum_State2_Flow_control_frame (3) +#endif + +#ifndef LTE_FrameCode_Stat_LTE_Sum_State2_Consecutive_frame +#define LTE_FrameCode_Stat_LTE_Sum_State2_Consecutive_frame (2) +#endif + +#ifndef LTE_FrameCode_Stat_LTE_Sum_State2_First_frame +#define LTE_FrameCode_Stat_LTE_Sum_State2_First_frame (1) +#endif + +#ifndef LTE_FrameCode_Stat_LTE_Sum_State2_Single_Frame +#define LTE_FrameCode_Stat_LTE_Sum_State2_Single_Frame (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // ISO-TP (ISO - 15765) + // 0x0 - The single frame transferred (>=7 bytes) + // 0x1 - The first frame of a multi-frame message packet + // 0x2 - A frame containing subsequent data for a multi-frame packet + // 0x3 - The response from the receiver, ack a First-frame segment + // 3 : "Flow control frame" + // 2 : "Consecutive frame" + // 1 : "First frame" + // 0 : "Single Frame" + // MULTIPLEX master signal + uint8_t LTE_FrameCode_Stat : 4; // Bits= 4 + + // ISO-TP (ISO - 15765) + // Flow control status + // multiplex variable + uint8_t LTE_Flow_Stat : 4; // Bits= 4 + + // ISO-TP (ISO - 15765) + // Frame number in multiframe transmission + // multiplex variable + uint8_t LTE_FrameNum_Val : 4; // Bits= 4 + + // ISO-TP (ISO - 15765) + // Multiframe data length + // multiplex variable + uint16_t LTE_DataLenM; // Bits=12 Unit:'bytes' + + // ISO-TP (ISO - 15765) + // Single frame data length + // multiplex variable + uint8_t LTE_DataLenS : 4; // Bits= 4 Unit:'bytes' + + // ISO-TP (ISO - 15765) + // The number of data blocks that will be transmitted before the next flow control message. + // multiplex variable + uint8_t LTE_BlockSize_Val; // Bits= 8 + + // ISO-TP (ISO - 15765) + // Data block. + // multiplex variable + uint64_t LTE_Data1_Val; // Bits=56 + + // ISO-TP (ISO - 15765) + // Data block. + // multiplex variable + uint64_t LTE_Data3_Val; // Bits=56 + + // ISO-TP (ISO-15765) + // Separation Time (ST), minimum delay time between frames (end of one frame and the beginning of the other) + // 0x00...0x7F = 0...127 ms + // 0xF1...0xF9 = 100...900 us + // multiplex variable + uint8_t LTE_MinSepTime_Val; // Bits= 8 + + // ISO-TP (ISO - 15765) + // Data block. + // multiplex variable + uint64_t LTE_Data2_Val; // Bits=48 + +#else + + // ISO-TP (ISO - 15765) + // 0x0 - The single frame transferred (>=7 bytes) + // 0x1 - The first frame of a multi-frame message packet + // 0x2 - A frame containing subsequent data for a multi-frame packet + // 0x3 - The response from the receiver, ack a First-frame segment + // 3 : "Flow control frame" + // 2 : "Consecutive frame" + // 1 : "First frame" + // 0 : "Single Frame" + // MULTIPLEX master signal + uint8_t LTE_FrameCode_Stat; // Bits= 4 + + // ISO-TP (ISO - 15765) + // Flow control status + // multiplex variable + uint8_t LTE_Flow_Stat; // Bits= 4 + + // ISO-TP (ISO - 15765) + // Frame number in multiframe transmission + // multiplex variable + uint8_t LTE_FrameNum_Val; // Bits= 4 + + // ISO-TP (ISO - 15765) + // Multiframe data length + // multiplex variable + uint16_t LTE_DataLenM; // Bits=12 Unit:'bytes' + + // ISO-TP (ISO - 15765) + // Single frame data length + // multiplex variable + uint8_t LTE_DataLenS; // Bits= 4 Unit:'bytes' + + // ISO-TP (ISO - 15765) + // The number of data blocks that will be transmitted before the next flow control message. + // multiplex variable + uint8_t LTE_BlockSize_Val; // Bits= 8 + + // ISO-TP (ISO - 15765) + // Data block. + // multiplex variable + uint64_t LTE_Data1_Val; // Bits=56 + + // ISO-TP (ISO - 15765) + // Data block. + // multiplex variable + uint64_t LTE_Data3_Val; // Bits=56 + + // ISO-TP (ISO-15765) + // Separation Time (ST), minimum delay time between frames (end of one frame and the beginning of the other) + // 0x00...0x7F = 0...127 ms + // 0xF1...0xF9 = 100...900 us + // multiplex variable + uint8_t LTE_MinSepTime_Val; // Bits= 8 + + // ISO-TP (ISO - 15765) + // Data block. + // multiplex variable + uint64_t LTE_Data2_Val; // Bits=48 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} LTE_Sum_State2_t; + +// def @WChF_FIU_TransferState CAN Message (1537 0x601) +#define WChF_FIU_TransferState_IDE (0U) +#define WChF_FIU_TransferState_DLC (8U) +#define WChF_FIU_TransferState_CANID (0x601U) + +// Value tables for @WChF_FrameCode_Stat signal + +#ifndef WChF_FrameCode_Stat_WChF_FIU_TransferState_Flow_control_frame +#define WChF_FrameCode_Stat_WChF_FIU_TransferState_Flow_control_frame (3) +#endif + +#ifndef WChF_FrameCode_Stat_WChF_FIU_TransferState_Consecutive_frame +#define WChF_FrameCode_Stat_WChF_FIU_TransferState_Consecutive_frame (2) +#endif + +#ifndef WChF_FrameCode_Stat_WChF_FIU_TransferState_First_frame +#define WChF_FrameCode_Stat_WChF_FIU_TransferState_First_frame (1) +#endif + +#ifndef WChF_FrameCode_Stat_WChF_FIU_TransferState_Single_Frame +#define WChF_FrameCode_Stat_WChF_FIU_TransferState_Single_Frame (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // ISO-TP (ISO - 15765) + // Flow control status + // multiplex variable + uint8_t WChF_Flow_Stat : 4; // Bits= 4 + + // ISO-TP (ISO - 15765) + // Frame number in multiframe transmission + // multiplex variable + uint8_t WChF_FrameNum_Val : 4; // Bits= 4 + + // ISO-TP (ISO - 15765) + // Multiframe data length + // multiplex variable + uint16_t WChF_DataLenM; // Bits=12 Unit:'bytes' + + // ISO-TP (ISO - 15765) + // Single frame data length + // multiplex variable + uint8_t WChF_DataLenS : 4; // Bits= 4 Unit:'bytes' + + // ISO-TP (ISO - 15765) + // 0x0 - The single frame transferred (>=7 bytes) + // 0x1 - The first frame of a multi-frame message packet + // 0x2 - A frame containing subsequent data for a multi-frame packet + // 0x3 - The response from the receiver, ack a First-frame segment + // 3 : "Flow control frame" + // 2 : "Consecutive frame" + // 1 : "First frame" + // 0 : "Single Frame" + // MULTIPLEX master signal + uint8_t WChF_FrameCode_Stat : 4; // Bits= 4 + + // ISO-TP (ISO - 15765) + // The number of data blocks that will be transmitted before the next flow control message. + // multiplex variable + uint8_t WChF_BlockSize_Val; // Bits= 8 + + // ISO-TP (ISO - 15765) + // Data block. + // multiplex variable + uint64_t WChF_Data1_Val; // Bits=56 + + // ISO-TP (ISO - 15765) + // Data block. + // multiplex variable + uint64_t WChF_Data3_Val; // Bits=56 + + // ISO-TP (ISO-15765) + // Separation Time (ST), minimum delay time between frames (end of one frame and the beginning of the other) + // 0x00...0x7F = 0...127 ms + // 0xF1...0xF9 = 100...900 us + // multiplex variable + uint8_t WChF_MinSepTime_Val; // Bits= 8 + + // ISO-TP (ISO - 15765) + // Data block. + // multiplex variable + uint64_t WChF_Data2_Val; // Bits=48 + +#else + + // ISO-TP (ISO - 15765) + // Flow control status + // multiplex variable + uint8_t WChF_Flow_Stat; // Bits= 4 + + // ISO-TP (ISO - 15765) + // Frame number in multiframe transmission + // multiplex variable + uint8_t WChF_FrameNum_Val; // Bits= 4 + + // ISO-TP (ISO - 15765) + // Multiframe data length + // multiplex variable + uint16_t WChF_DataLenM; // Bits=12 Unit:'bytes' + + // ISO-TP (ISO - 15765) + // Single frame data length + // multiplex variable + uint8_t WChF_DataLenS; // Bits= 4 Unit:'bytes' + + // ISO-TP (ISO - 15765) + // 0x0 - The single frame transferred (>=7 bytes) + // 0x1 - The first frame of a multi-frame message packet + // 0x2 - A frame containing subsequent data for a multi-frame packet + // 0x3 - The response from the receiver, ack a First-frame segment + // 3 : "Flow control frame" + // 2 : "Consecutive frame" + // 1 : "First frame" + // 0 : "Single Frame" + // MULTIPLEX master signal + uint8_t WChF_FrameCode_Stat; // Bits= 4 + + // ISO-TP (ISO - 15765) + // The number of data blocks that will be transmitted before the next flow control message. + // multiplex variable + uint8_t WChF_BlockSize_Val; // Bits= 8 + + // ISO-TP (ISO - 15765) + // Data block. + // multiplex variable + uint64_t WChF_Data1_Val; // Bits=56 + + // ISO-TP (ISO - 15765) + // Data block. + // multiplex variable + uint64_t WChF_Data3_Val; // Bits=56 + + // ISO-TP (ISO-15765) + // Separation Time (ST), minimum delay time between frames (end of one frame and the beginning of the other) + // 0x00...0x7F = 0...127 ms + // 0xF1...0xF9 = 100...900 us + // multiplex variable + uint8_t WChF_MinSepTime_Val; // Bits= 8 + + // ISO-TP (ISO - 15765) + // Data block. + // multiplex variable + uint64_t WChF_Data2_Val; // Bits=48 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} WChF_FIU_TransferState_t; + +// def @FIU_WChF_TransferState CAN Message (1540 0x604) +#define FIU_WChF_TransferState_IDE (0U) +#define FIU_WChF_TransferState_DLC (8U) +#define FIU_WChF_TransferState_CANID (0x604U) + +// Value tables for @FIU_Flow_Stat signal + +#ifndef FIU_Flow_Stat_FIU_WChF_TransferState_Overflowabort +#define FIU_Flow_Stat_FIU_WChF_TransferState_Overflowabort (2) +#endif + +#ifndef FIU_Flow_Stat_FIU_WChF_TransferState_Continie_to_send +#define FIU_Flow_Stat_FIU_WChF_TransferState_Continie_to_send (0) +#endif + +#ifndef FIU_Flow_Stat_FIU_WChF_TransferState_Wait +#define FIU_Flow_Stat_FIU_WChF_TransferState_Wait (1) +#endif + + +// Value tables for @FIU_FrameCode_Stat signal + +#ifndef FIU_FrameCode_Stat_FIU_WChF_TransferState_Flow_control_frame +#define FIU_FrameCode_Stat_FIU_WChF_TransferState_Flow_control_frame (3) +#endif + +#ifndef FIU_FrameCode_Stat_FIU_WChF_TransferState_Consecutive_frame +#define FIU_FrameCode_Stat_FIU_WChF_TransferState_Consecutive_frame (2) +#endif + +#ifndef FIU_FrameCode_Stat_FIU_WChF_TransferState_First_frame +#define FIU_FrameCode_Stat_FIU_WChF_TransferState_First_frame (1) +#endif + +#ifndef FIU_FrameCode_Stat_FIU_WChF_TransferState_Single_Frame +#define FIU_FrameCode_Stat_FIU_WChF_TransferState_Single_Frame (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // ISO-TP (ISO - 15765) + // Flow control status + // 2 : "Overflow/abort" + // 0 : "Continie to send" + // 1 : "Wait" + // multiplex variable + uint8_t FIU_Flow_Stat : 4; // Bits= 4 + + // ISO-TP (ISO - 15765) + // Frame number in multiframe transmission + // multiplex variable + uint8_t FIU_FrameNum_Val : 4; // Bits= 4 + + // ISO-TP (ISO - 15765) + // Multiframe data length + // multiplex variable + uint16_t FIU_DataLenM; // Bits=12 Unit:'bytes' + + // ISO-TP (ISO - 15765) + // Single frame data length + // multiplex variable + uint8_t FIU_DataLenS : 4; // Bits= 4 Unit:'bytes' + + // ISO-TP (ISO - 15765) + // 0x0 - The single frame transferred (>=7 bytes) + // 0x1 - The first frame of a multi-frame message packet + // 0x2 - A frame containing subsequent data for a multi-frame packet + // 0x3 - The response from the receiver, ack a First-frame segment + // 3 : "Flow control frame" + // 2 : "Consecutive frame" + // 1 : "First frame" + // 0 : "Single Frame" + // MULTIPLEX master signal + uint8_t FIU_FrameCode_Stat : 4; // Bits= 4 + + // ISO-TP (ISO - 15765) + // The number of data blocks that will be transmitted before the next flow control message. + // multiplex variable + uint8_t FIU_BlockSize_Val; // Bits= 8 + + // ISO-TP (ISO - 15765) + // Data block. + // multiplex variable + uint64_t FIU_Data1_Val; // Bits=56 + + // ISO-TP (ISO - 15765) + // Data block. + // multiplex variable + uint64_t FIU_Data3_Val; // Bits=56 + + // ISO-TP (ISO-15765) + // Separation Time (ST), minimum delay time between frames (end of one frame and the beginning of the other) + // 0x00...0x7F = 0...127 ms + // 0xF1...0xF9 = 100...900 us + // multiplex variable + uint8_t FIU_MinSepTime_Val; // Bits= 8 + + // ISO-TP (ISO - 15765) + // Data block. + // multiplex variable + uint64_t FIU_Data2_Val; // Bits=48 + +#else + + // ISO-TP (ISO - 15765) + // Flow control status + // 2 : "Overflow/abort" + // 0 : "Continie to send" + // 1 : "Wait" + // multiplex variable + uint8_t FIU_Flow_Stat; // Bits= 4 + + // ISO-TP (ISO - 15765) + // Frame number in multiframe transmission + // multiplex variable + uint8_t FIU_FrameNum_Val; // Bits= 4 + + // ISO-TP (ISO - 15765) + // Multiframe data length + // multiplex variable + uint16_t FIU_DataLenM; // Bits=12 Unit:'bytes' + + // ISO-TP (ISO - 15765) + // Single frame data length + // multiplex variable + uint8_t FIU_DataLenS; // Bits= 4 Unit:'bytes' + + // ISO-TP (ISO - 15765) + // 0x0 - The single frame transferred (>=7 bytes) + // 0x1 - The first frame of a multi-frame message packet + // 0x2 - A frame containing subsequent data for a multi-frame packet + // 0x3 - The response from the receiver, ack a First-frame segment + // 3 : "Flow control frame" + // 2 : "Consecutive frame" + // 1 : "First frame" + // 0 : "Single Frame" + // MULTIPLEX master signal + uint8_t FIU_FrameCode_Stat; // Bits= 4 + + // ISO-TP (ISO - 15765) + // The number of data blocks that will be transmitted before the next flow control message. + // multiplex variable + uint8_t FIU_BlockSize_Val; // Bits= 8 + + // ISO-TP (ISO - 15765) + // Data block. + // multiplex variable + uint64_t FIU_Data1_Val; // Bits=56 + + // ISO-TP (ISO - 15765) + // Data block. + // multiplex variable + uint64_t FIU_Data3_Val; // Bits=56 + + // ISO-TP (ISO-15765) + // Separation Time (ST), minimum delay time between frames (end of one frame and the beginning of the other) + // 0x00...0x7F = 0...127 ms + // 0xF1...0xF9 = 100...900 us + // multiplex variable + uint8_t FIU_MinSepTime_Val; // Bits= 8 + + // ISO-TP (ISO - 15765) + // Data block. + // multiplex variable + uint64_t FIU_Data2_Val; // Bits=48 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} FIU_WChF_TransferState_t; + +// def @VAU_BLE_Device CAN Message (1570 0x622) +#define VAU_BLE_Device_IDE (0U) +#define VAU_BLE_Device_DLC (8U) +#define VAU_BLE_Device_CANID (0x622U) + +// Value tables for @VAU_BLEZoneLoc_Stat signal + +#ifndef VAU_BLEZoneLoc_Stat_VAU_BLE_Device_Rear_Side +#define VAU_BLEZoneLoc_Stat_VAU_BLE_Device_Rear_Side (10) +#endif + +#ifndef VAU_BLEZoneLoc_Stat_VAU_BLE_Device_RR_Outside +#define VAU_BLEZoneLoc_Stat_VAU_BLE_Device_RR_Outside (9) +#endif + +#ifndef VAU_BLEZoneLoc_Stat_VAU_BLE_Device_RL_Outside +#define VAU_BLEZoneLoc_Stat_VAU_BLE_Device_RL_Outside (8) +#endif + +#ifndef VAU_BLEZoneLoc_Stat_VAU_BLE_Device_FR_Outside +#define VAU_BLEZoneLoc_Stat_VAU_BLE_Device_FR_Outside (7) +#endif + +#ifndef VAU_BLEZoneLoc_Stat_VAU_BLE_Device_FL_Outside +#define VAU_BLEZoneLoc_Stat_VAU_BLE_Device_FL_Outside (6) +#endif + +#ifndef VAU_BLEZoneLoc_Stat_VAU_BLE_Device_TrunkCompartment +#define VAU_BLEZoneLoc_Stat_VAU_BLE_Device_TrunkCompartment (5) +#endif + +#ifndef VAU_BLEZoneLoc_Stat_VAU_BLE_Device_RR_Cabin +#define VAU_BLEZoneLoc_Stat_VAU_BLE_Device_RR_Cabin (4) +#endif + +#ifndef VAU_BLEZoneLoc_Stat_VAU_BLE_Device_RL_Cabin +#define VAU_BLEZoneLoc_Stat_VAU_BLE_Device_RL_Cabin (3) +#endif + +#ifndef VAU_BLEZoneLoc_Stat_VAU_BLE_Device_FR_Cabin +#define VAU_BLEZoneLoc_Stat_VAU_BLE_Device_FR_Cabin (2) +#endif + +#ifndef VAU_BLEZoneLoc_Stat_VAU_BLE_Device_FL_Cabin +#define VAU_BLEZoneLoc_Stat_VAU_BLE_Device_FL_Cabin (1) +#endif + +#ifndef VAU_BLEZoneLoc_Stat_VAU_BLE_Device_Not_located_in_Vehicle_area +#define VAU_BLEZoneLoc_Stat_VAU_BLE_Device_Not_located_in_Vehicle_area (0) +#endif + + +// Value tables for @VAU_BLEDevice_ID signal + +#ifndef VAU_BLEDevice_ID_VAU_BLE_Device_Reserved +#define VAU_BLEDevice_ID_VAU_BLE_Device_Reserved (7) +#endif + +#ifndef VAU_BLEDevice_ID_VAU_BLE_Device_Reserved +#define VAU_BLEDevice_ID_VAU_BLE_Device_Reserved (6) +#endif + +#ifndef VAU_BLEDevice_ID_VAU_BLE_Device_Smartphone_5 +#define VAU_BLEDevice_ID_VAU_BLE_Device_Smartphone_5 (5) +#endif + +#ifndef VAU_BLEDevice_ID_VAU_BLE_Device_Smartphone_4 +#define VAU_BLEDevice_ID_VAU_BLE_Device_Smartphone_4 (4) +#endif + +#ifndef VAU_BLEDevice_ID_VAU_BLE_Device_Smartphone_3 +#define VAU_BLEDevice_ID_VAU_BLE_Device_Smartphone_3 (3) +#endif + +#ifndef VAU_BLEDevice_ID_VAU_BLE_Device_Smartphone_2 +#define VAU_BLEDevice_ID_VAU_BLE_Device_Smartphone_2 (2) +#endif + +#ifndef VAU_BLEDevice_ID_VAU_BLE_Device_Smartphone_1 +#define VAU_BLEDevice_ID_VAU_BLE_Device_Smartphone_1 (1) +#endif + +#ifndef VAU_BLEDevice_ID_VAU_BLE_Device_Not_detected +#define VAU_BLEDevice_ID_VAU_BLE_Device_Not_detected (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // The zone in which the smartphone was detected + // 10 : "Rear_Side" + // 9 : "RR_Outside" + // 8 : "RL_Outside" + // 7 : "FR_Outside" + // 6 : "FL_Outside" + // 5 : "TrunkCompartment" + // 4 : "RR_Cabin" + // 3 : "RL_Cabin" + // 2 : "FR_Cabin" + // 1 : "FL_Cabin" + // 0 : "Not located in Vehicle area" + uint8_t VAU_BLEZoneLoc_Stat : 4; // Bits= 4 + + // Value of BLE pairing password + uint32_t VAU_BLEPassword_Val; // Bits=20 + + // ID of detected smartphone + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Smartphone 5" + // 4 : "Smartphone 4" + // 3 : "Smartphone 3" + // 2 : "Smartphone 2" + // 1 : "Smartphone 1" + // 0 : "Not detected" + uint8_t VAU_BLEDevice_ID : 3; // Bits= 3 + +#else + + // The zone in which the smartphone was detected + // 10 : "Rear_Side" + // 9 : "RR_Outside" + // 8 : "RL_Outside" + // 7 : "FR_Outside" + // 6 : "FL_Outside" + // 5 : "TrunkCompartment" + // 4 : "RR_Cabin" + // 3 : "RL_Cabin" + // 2 : "FR_Cabin" + // 1 : "FL_Cabin" + // 0 : "Not located in Vehicle area" + uint8_t VAU_BLEZoneLoc_Stat; // Bits= 4 + + // Value of BLE pairing password + uint32_t VAU_BLEPassword_Val; // Bits=20 + + // ID of detected smartphone + // 7 : "Reserved" + // 6 : "Reserved" + // 5 : "Smartphone 5" + // 4 : "Smartphone 4" + // 3 : "Smartphone 3" + // 2 : "Smartphone 2" + // 1 : "Smartphone 1" + // 0 : "Not detected" + uint8_t VAU_BLEDevice_ID; // Bits= 3 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} VAU_BLE_Device_t; + +// Diagnostic message +// def @Diag_From_APU CAN Message (1584 0x630) +#define Diag_From_APU_IDE (0U) +#define Diag_From_APU_DLC (8U) +#define Diag_From_APU_CANID (0x630U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_APU; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_APU; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_APU_t; + +// def @SSL_Status CAN Message (1680 0x690) +#define SSL_Status_IDE (0U) +#define SSL_Status_DLC (1U) +#define SSL_Status_CANID (0x690U) +#define SSL_Status_CYC (200U) + +// Value tables for @SSL_FootrestAutoClose_Req signal + +#ifndef SSL_FootrestAutoClose_Req_SSL_Status_Close_footrest +#define SSL_FootrestAutoClose_Req_SSL_Status_Close_footrest (1) +#endif + +#ifndef SSL_FootrestAutoClose_Req_SSL_Status_No_action +#define SSL_FootrestAutoClose_Req_SSL_Status_No_action (0) +#endif + + +// Value tables for @SSL_Position_Stat signal + +#ifndef SSL_Position_Stat_SSL_Status_Error +#define SSL_Position_Stat_SSL_Status_Error (4) +#endif + +#ifndef SSL_Position_Stat_SSL_Status_Intermediate_running +#define SSL_Position_Stat_SSL_Status_Intermediate_running (3) +#endif + +#ifndef SSL_Position_Stat_SSL_Status_Straponten_open +#define SSL_Position_Stat_SSL_Status_Straponten_open (2) +#endif + +#ifndef SSL_Position_Stat_SSL_Status_Cushion_open +#define SSL_Position_Stat_SSL_Status_Cushion_open (1) +#endif + +#ifndef SSL_Position_Stat_SSL_Status_Close +#define SSL_Position_Stat_SSL_Status_Close (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Footrest autoclosing status + // Close the footrest in automatic mode (when opening the straponten) + // 1 : "Close footrest" + // 0 : "No action" + uint8_t SSL_FootrestAutoClose_Req : 1; // Bits= 1 + + // Straponten position status + // 4 : "Error" + // 3 : "Intermediate (running)" + // 2 : "Straponten open" + // 1 : "Cushion open" + // 0 : "Close" + uint8_t SSL_Position_Stat : 3; // Bits= 3 + +#else + + // Footrest autoclosing status + // Close the footrest in automatic mode (when opening the straponten) + // 1 : "Close footrest" + // 0 : "No action" + uint8_t SSL_FootrestAutoClose_Req; // Bits= 1 + + // Straponten position status + // 4 : "Error" + // 3 : "Intermediate (running)" + // 2 : "Straponten open" + // 1 : "Cushion open" + // 0 : "Close" + uint8_t SSL_Position_Stat; // Bits= 3 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} SSL_Status_t; + +// def @SSR_Status CAN Message (1681 0x691) +#define SSR_Status_IDE (0U) +#define SSR_Status_DLC (1U) +#define SSR_Status_CANID (0x691U) +#define SSR_Status_CYC (200U) + +// Value tables for @SSR_FootrestAutoClose_Req signal + +#ifndef SSR_FootrestAutoClose_Req_SSR_Status_Close_footrest +#define SSR_FootrestAutoClose_Req_SSR_Status_Close_footrest (1) +#endif + +#ifndef SSR_FootrestAutoClose_Req_SSR_Status_No_action +#define SSR_FootrestAutoClose_Req_SSR_Status_No_action (0) +#endif + + +// Value tables for @SSR_Position_Stat signal + +#ifndef SSR_Position_Stat_SSR_Status_Error +#define SSR_Position_Stat_SSR_Status_Error (4) +#endif + +#ifndef SSR_Position_Stat_SSR_Status_Intermediate_running +#define SSR_Position_Stat_SSR_Status_Intermediate_running (3) +#endif + +#ifndef SSR_Position_Stat_SSR_Status_Straponten_open +#define SSR_Position_Stat_SSR_Status_Straponten_open (2) +#endif + +#ifndef SSR_Position_Stat_SSR_Status_Cushion_open +#define SSR_Position_Stat_SSR_Status_Cushion_open (1) +#endif + +#ifndef SSR_Position_Stat_SSR_Status_Close +#define SSR_Position_Stat_SSR_Status_Close (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Footrest autoclosing status + // Close the footrest in automatic mode (when opening the straponten) + // 1 : "Close footrest" + // 0 : "No action" + uint8_t SSR_FootrestAutoClose_Req : 1; // Bits= 1 + + // Straponten position status + // 4 : "Error" + // 3 : "Intermediate (running)" + // 2 : "Straponten open" + // 1 : "Cushion open" + // 0 : "Close" + uint8_t SSR_Position_Stat : 3; // Bits= 3 + +#else + + // Footrest autoclosing status + // Close the footrest in automatic mode (when opening the straponten) + // 1 : "Close footrest" + // 0 : "No action" + uint8_t SSR_FootrestAutoClose_Req; // Bits= 1 + + // Straponten position status + // 4 : "Error" + // 3 : "Intermediate (running)" + // 2 : "Straponten open" + // 1 : "Cushion open" + // 0 : "Close" + uint8_t SSR_Position_Stat; // Bits= 3 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} SSR_Status_t; + +// Attention! Message ID 0x6D0 also uses BCM for XCP connection. +// def @PTG_To_SupplierTool CAN Message (1744 0x6d0) +#define PTG_To_SupplierTool_IDE (0U) +#define PTG_To_SupplierTool_DLC (8U) +#define PTG_To_SupplierTool_CANID (0x6d0U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // This signal uses for calibration PTG unit. + // Attention! Message ID 0x6D0 also uses BCM for XCP connection. + uint64_t PTG_To_SupplierTool_Sig; // Bits=64 + +#else + + // This signal uses for calibration PTG unit. + // Attention! Message ID 0x6D0 also uses BCM for XCP connection. + uint64_t PTG_To_SupplierTool_Sig; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} PTG_To_SupplierTool_t; + +// Attention! Message ID 0x6D1 also uses DMFL for XCP connection. +// def @SupplierTool_To_PTG CAN Message (1745 0x6d1) +#define SupplierTool_To_PTG_IDE (0U) +#define SupplierTool_To_PTG_DLC (8U) +#define SupplierTool_To_PTG_CANID (0x6d1U) +#define SupplierTool_To_PTG_CYC (100U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // This signal uses for calibration PTG unit. + // Attention! Message ID 0x6D1 also uses DMFL for XCP connection. + uint64_t SupplierTool_To_PTG_Sig; // Bits=64 + +#else + + // This signal uses for calibration PTG unit. + // Attention! Message ID 0x6D1 also uses DMFL for XCP connection. + uint64_t SupplierTool_To_PTG_Sig; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} SupplierTool_To_PTG_t; + +// Diagnostic message +// def @Diag_From_CCPF CAN Message (1793 0x701) +#define Diag_From_CCPF_IDE (0U) +#define Diag_From_CCPF_DLC (8U) +#define Diag_From_CCPF_CANID (0x701U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_CCPF; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_CCPF; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_CCPF_t; + +// Diagnostic message +// def @Diag_To_CCPF CAN Message (1794 0x702) +#define Diag_To_CCPF_IDE (0U) +#define Diag_To_CCPF_DLC (8U) +#define Diag_To_CCPF_CANID (0x702U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_CCPF; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_CCPF; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_CCPF_t; + +// Diagnostic message +// def @Diag_From_CCPR CAN Message (1795 0x703) +#define Diag_From_CCPR_IDE (0U) +#define Diag_From_CCPR_DLC (8U) +#define Diag_From_CCPR_CANID (0x703U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_CCPR; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_CCPR; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_CCPR_t; + +// Diagnostic message +// def @Diag_To_CCPR CAN Message (1796 0x704) +#define Diag_To_CCPR_IDE (0U) +#define Diag_To_CCPR_DLC (8U) +#define Diag_To_CCPR_CANID (0x704U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_CCPR; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_CCPR; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_CCPR_t; + +// def @Diag_To_SSL CAN Message (1798 0x706) +#define Diag_To_SSL_IDE (0U) +#define Diag_To_SSL_DLC (8U) +#define Diag_To_SSL_CANID (0x706U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_SSL; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_SSL; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_SSL_t; + +// def @Diag_To_SSR CAN Message (1801 0x709) +#define Diag_To_SSR_IDE (0U) +#define Diag_To_SSR_DLC (8U) +#define Diag_To_SSR_CANID (0x709U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_SSR; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_SSR; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_SSR_t; + +// def @Diag_From_SSL CAN Message (1814 0x716) +#define Diag_From_SSL_IDE (0U) +#define Diag_From_SSL_DLC (8U) +#define Diag_From_SSL_CANID (0x716U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_SSL; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_SSL; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_SSL_t; + +// Diagnostic message +// def @Diag_To_FCSilCU CAN Message (1816 0x718) +#define Diag_To_FCSilCU_IDE (0U) +#define Diag_To_FCSilCU_DLC (8U) +#define Diag_To_FCSilCU_CANID (0x718U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_FCSilCU; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_FCSilCU; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_FCSilCU_t; + +// def @Diag_From_SSR CAN Message (1817 0x719) +#define Diag_From_SSR_IDE (0U) +#define Diag_From_SSR_DLC (8U) +#define Diag_From_SSR_CANID (0x719U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_SSR; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_SSR; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_SSR_t; + +// Diagnostic message +// def @Diag_To_FLDSilCU CAN Message (1820 0x71c) +#define Diag_To_FLDSilCU_IDE (0U) +#define Diag_To_FLDSilCU_DLC (8U) +#define Diag_To_FLDSilCU_CANID (0x71cU) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_FLDSilCU; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_FLDSilCU; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_FLDSilCU_t; + +// Diagnostic message +// def @Diag_To_FRDSilCU CAN Message (1821 0x71d) +#define Diag_To_FRDSilCU_IDE (0U) +#define Diag_To_FRDSilCU_DLC (8U) +#define Diag_To_FRDSilCU_CANID (0x71dU) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_FRDSilCU; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_FRDSilCU; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_FRDSilCU_t; + +// Diagnostic message +// def @Diag_To_ICLSilCU CAN Message (1824 0x720) +#define Diag_To_ICLSilCU_IDE (0U) +#define Diag_To_ICLSilCU_DLC (8U) +#define Diag_To_ICLSilCU_CANID (0x720U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_ICLSilCU; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_ICLSilCU; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_ICLSilCU_t; + +// Diagnostic message +// def @Diag_From_FCSilCU CAN Message (1832 0x728) +#define Diag_From_FCSilCU_IDE (0U) +#define Diag_From_FCSilCU_DLC (8U) +#define Diag_From_FCSilCU_CANID (0x728U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_FCSilCU; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_FCSilCU; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_FCSilCU_t; + +// Diagnostic message +// def @Diag_From_FLDSilCU CAN Message (1836 0x72c) +#define Diag_From_FLDSilCU_IDE (0U) +#define Diag_From_FLDSilCU_DLC (8U) +#define Diag_From_FLDSilCU_CANID (0x72cU) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_FLDSilCU; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_FLDSilCU; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_FLDSilCU_t; + +// Diagnostic message +// def @Diag_From_FRDSilCU CAN Message (1837 0x72d) +#define Diag_From_FRDSilCU_IDE (0U) +#define Diag_From_FRDSilCU_DLC (8U) +#define Diag_From_FRDSilCU_CANID (0x72dU) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_FRDSilCU; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_FRDSilCU; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_FRDSilCU_t; + +// Diagnostic message +// def @Diag_From_ICLSilCU CAN Message (1838 0x72e) +#define Diag_From_ICLSilCU_IDE (0U) +#define Diag_From_ICLSilCU_DLC (8U) +#define Diag_From_ICLSilCU_CANID (0x72eU) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_ICLSilCU; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_ICLSilCU; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_ICLSilCU_t; + +// Diagnostic message +// def @Diag_To_APU CAN Message (1840 0x730) +#define Diag_To_APU_IDE (0U) +#define Diag_To_APU_DLC (8U) +#define Diag_To_APU_CANID (0x730U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_APU; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_APU; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_APU_t; + +// Diagnostic message +// def @Diag_To_FTCU CAN Message (1850 0x73a) +#define Diag_To_FTCU_IDE (0U) +#define Diag_To_FTCU_DLC (8U) +#define Diag_To_FTCU_CANID (0x73aU) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_FTCU_Sig; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_FTCU_Sig; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_FTCU_t; + +// Diagnostic message +// def @Diag_From_FTCU CAN Message (1866 0x74a) +#define Diag_From_FTCU_IDE (0U) +#define Diag_From_FTCU_DLC (8U) +#define Diag_From_FTCU_CANID (0x74aU) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_FTCU; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_FTCU; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_FTCU_t; + +// Diagnostic message +// def @Diag_To_Sroof CAN Message (1903 0x76f) +#define Diag_To_Sroof_IDE (0U) +#define Diag_To_Sroof_DLC (8U) +#define Diag_To_Sroof_CANID (0x76fU) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_Sroof; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_Sroof; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_Sroof_t; + +// Diagnostic message +// def @Diag_From_SRoof CAN Message (1919 0x77f) +#define Diag_From_SRoof_IDE (0U) +#define Diag_From_SRoof_DLC (8U) +#define Diag_From_SRoof_CANID (0x77fU) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_SRoof; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_SRoof; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_SRoof_t; + +// Diagnostic message +// def @Diag_To_ICRSilCU CAN Message (1924 0x784) +#define Diag_To_ICRSilCU_IDE (0U) +#define Diag_To_ICRSilCU_DLC (8U) +#define Diag_To_ICRSilCU_CANID (0x784U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_ICRSilCU; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_ICRSilCU; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_ICRSilCU_t; + +// Diagnostic message +// def @Diag_To_LB_pSilCU CAN Message (1927 0x787) +#define Diag_To_LB_pSilCU_IDE (0U) +#define Diag_To_LB_pSilCU_DLC (8U) +#define Diag_To_LB_pSilCU_CANID (0x787U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_LB_pSilCU; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_LB_pSilCU; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_LB_pSilCU_t; + +// Diagnostic message +// def @Diag_To_PLSilCU CAN Message (1928 0x788) +#define Diag_To_PLSilCU_IDE (0U) +#define Diag_To_PLSilCU_DLC (8U) +#define Diag_To_PLSilCU_CANID (0x788U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_PLSilCU; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_PLSilCU; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_PLSilCU_t; + +// Diagnostic message +// def @Diag_To_PRSilCU CAN Message (1929 0x789) +#define Diag_To_PRSilCU_IDE (0U) +#define Diag_To_PRSilCU_DLC (8U) +#define Diag_To_PRSilCU_CANID (0x789U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_PRSilCU; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_PRSilCU; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_PRSilCU_t; + +// Diagnostic message +// def @Diag_To_RB_pSilCU CAN Message (1932 0x78c) +#define Diag_To_RB_pSilCU_IDE (0U) +#define Diag_To_RB_pSilCU_DLC (8U) +#define Diag_To_RB_pSilCU_CANID (0x78cU) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_RB_pSilCU; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_RB_pSilCU; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_RB_pSilCU_t; + +// Diagnostic message +// def @Diag_From_ICRSilCU CAN Message (1940 0x794) +#define Diag_From_ICRSilCU_IDE (0U) +#define Diag_From_ICRSilCU_DLC (8U) +#define Diag_From_ICRSilCU_CANID (0x794U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_ICRSilCU; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_ICRSilCU; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_ICRSilCU_t; + +// Diagnostic message +// def @Diag_From_LB_pSilCU CAN Message (1943 0x797) +#define Diag_From_LB_pSilCU_IDE (0U) +#define Diag_From_LB_pSilCU_DLC (8U) +#define Diag_From_LB_pSilCU_CANID (0x797U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_LB_pSilCU; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_LB_pSilCU; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_LB_pSilCU_t; + +// Diagnostic message +// def @Diag_From_PLSilCU CAN Message (1944 0x798) +#define Diag_From_PLSilCU_IDE (0U) +#define Diag_From_PLSilCU_DLC (8U) +#define Diag_From_PLSilCU_CANID (0x798U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_PLSilCU; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_PLSilCU; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_PLSilCU_t; + +// Diagnostic message +// def @Diag_From_PRSilCU CAN Message (1945 0x799) +#define Diag_From_PRSilCU_IDE (0U) +#define Diag_From_PRSilCU_DLC (8U) +#define Diag_From_PRSilCU_CANID (0x799U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_PRSilCU; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_PRSilCU; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_PRSilCU_t; + +// Diagnostic message +// def @Diag_From_RB_pSilCU CAN Message (1948 0x79c) +#define Diag_From_RB_pSilCU_IDE (0U) +#define Diag_From_RB_pSilCU_DLC (8U) +#define Diag_From_RB_pSilCU_CANID (0x79cU) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_RB_pSilCU; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_RB_pSilCU; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_RB_pSilCU_t; + +// Diagnostic message +// def @Diag_To_VAU CAN Message (1952 0x7a0) +#define Diag_To_VAU_IDE (0U) +#define Diag_To_VAU_DLC (8U) +#define Diag_To_VAU_CANID (0x7a0U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_VAU_Sig; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_VAU_Sig; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_VAU_t; + +// Diagnostic message +// def @Diag_To_BCM CAN Message (1955 0x7a3) +#define Diag_To_BCM_IDE (0U) +#define Diag_To_BCM_DLC (8U) +#define Diag_To_BCM_CANID (0x7a3U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_BCM_Sig; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_BCM_Sig; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_BCM_t; + +// Diagnostic message +// def @Diag_To_DMFL CAN Message (1956 0x7a4) +#define Diag_To_DMFL_IDE (0U) +#define Diag_To_DMFL_DLC (8U) +#define Diag_To_DMFL_CANID (0x7a4U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_DMFL_Sig; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_DMFL_Sig; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_DMFL_t; + +// Diagnostic message +// def @Diag_To_DMFR CAN Message (1957 0x7a5) +#define Diag_To_DMFR_IDE (0U) +#define Diag_To_DMFR_DLC (8U) +#define Diag_To_DMFR_CANID (0x7a5U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_DMFR_Sig; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_DMFR_Sig; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_DMFR_t; + +// Diagnostic message +// def @Diag_To_DMRL CAN Message (1958 0x7a6) +#define Diag_To_DMRL_IDE (0U) +#define Diag_To_DMRL_DLC (8U) +#define Diag_To_DMRL_CANID (0x7a6U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_DMRL_Sig; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_DMRL_Sig; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_DMRL_t; + +// Diagnostic message +// def @Diag_To_DMRR CAN Message (1959 0x7a7) +#define Diag_To_DMRR_IDE (0U) +#define Diag_To_DMRR_DLC (8U) +#define Diag_To_DMRR_CANID (0x7a7U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_DMRR_Sig; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_DMRR_Sig; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_DMRR_t; + +// Diagnostic message +// def @Diag_To_SMRR CAN Message (1961 0x7a9) +#define Diag_To_SMRR_IDE (0U) +#define Diag_To_SMRR_DLC (8U) +#define Diag_To_SMRR_CANID (0x7a9U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_SMRR_Sig; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_SMRR_Sig; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_SMRR_t; + +// Diagnostic message +// def @Diag_To_TM CAN Message (1962 0x7aa) +#define Diag_To_TM_IDE (0U) +#define Diag_To_TM_DLC (8U) +#define Diag_To_TM_CANID (0x7aaU) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_TMDTM_Sig; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_TMDTM_Sig; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_TM_t; + +// Diagnostic message +// def @Diag_To_CCU CAN Message (1963 0x7ab) +#define Diag_To_CCU_IDE (0U) +#define Diag_To_CCU_DLC (8U) +#define Diag_To_CCU_CANID (0x7abU) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_CCU_Sig; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_CCU_Sig; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_CCU_t; + +// Diagnostic message +// def @Diag_To_SMFL CAN Message (1965 0x7ad) +#define Diag_To_SMFL_IDE (0U) +#define Diag_To_SMFL_DLC (8U) +#define Diag_To_SMFL_CANID (0x7adU) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_SMFL_Sig; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_SMFL_Sig; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_SMFL_t; + +// Diagnostic message +// def @Diag_To_SMFR CAN Message (1966 0x7ae) +#define Diag_To_SMFR_IDE (0U) +#define Diag_To_SMFR_DLC (8U) +#define Diag_To_SMFR_CANID (0x7aeU) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_SMFR_Sig; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_SMFR_Sig; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_SMFR_t; + +// Diagnostic message +// def @Diag_To_SMRL CAN Message (1967 0x7af) +#define Diag_To_SMRL_IDE (0U) +#define Diag_To_SMRL_DLC (8U) +#define Diag_To_SMRL_CANID (0x7afU) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_SMRL_Sig; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_SMRL_Sig; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_SMRL_t; + +// Diagnostic message +// def @Diag_From_VAU CAN Message (1968 0x7b0) +#define Diag_From_VAU_IDE (0U) +#define Diag_From_VAU_DLC (8U) +#define Diag_From_VAU_CANID (0x7b0U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_VAU_Sig; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_VAU_Sig; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_VAU_t; + +// Diagnostic message +// def @Diag_From_BCM CAN Message (1971 0x7b3) +#define Diag_From_BCM_IDE (0U) +#define Diag_From_BCM_DLC (8U) +#define Diag_From_BCM_CANID (0x7b3U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_BCM_Sig; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_BCM_Sig; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_BCM_t; + +// Diagnostic message +// def @Diag_From_DMFL CAN Message (1972 0x7b4) +#define Diag_From_DMFL_IDE (0U) +#define Diag_From_DMFL_DLC (8U) +#define Diag_From_DMFL_CANID (0x7b4U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_DMFL_Sig; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_DMFL_Sig; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_DMFL_t; + +// Diagnostic message +// def @Diag_From_DMFR CAN Message (1973 0x7b5) +#define Diag_From_DMFR_IDE (0U) +#define Diag_From_DMFR_DLC (8U) +#define Diag_From_DMFR_CANID (0x7b5U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_DMFR_Sig; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_DMFR_Sig; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_DMFR_t; + +// Diagnostic message +// def @Diag_From_DMRL CAN Message (1974 0x7b6) +#define Diag_From_DMRL_IDE (0U) +#define Diag_From_DMRL_DLC (8U) +#define Diag_From_DMRL_CANID (0x7b6U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_DMRL_Sig; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_DMRL_Sig; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_DMRL_t; + +// Diagnostic message +// def @Diag_From_DMRR CAN Message (1975 0x7b7) +#define Diag_From_DMRR_IDE (0U) +#define Diag_From_DMRR_DLC (8U) +#define Diag_From_DMRR_CANID (0x7b7U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_DMRR_Sig; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_DMRR_Sig; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_DMRR_t; + +// Diagnostic message +// def @Diag_From_SMRR CAN Message (1977 0x7b9) +#define Diag_From_SMRR_IDE (0U) +#define Diag_From_SMRR_DLC (8U) +#define Diag_From_SMRR_CANID (0x7b9U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_SMRR_Sig; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_SMRR_Sig; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_SMRR_t; + +// Diagnostic message +// def @Diag_From_TM CAN Message (1978 0x7ba) +#define Diag_From_TM_IDE (0U) +#define Diag_From_TM_DLC (8U) +#define Diag_From_TM_CANID (0x7baU) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_TM; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_TM; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_TM_t; + +// Diagnostic message +// def @Diag_From_CCU CAN Message (1979 0x7bb) +#define Diag_From_CCU_IDE (0U) +#define Diag_From_CCU_DLC (8U) +#define Diag_From_CCU_CANID (0x7bbU) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_CCU_Sig; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_CCU_Sig; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_CCU_t; + +// Diagnostic message +// def @Diag_From_SMFL CAN Message (1981 0x7bd) +#define Diag_From_SMFL_IDE (0U) +#define Diag_From_SMFL_DLC (8U) +#define Diag_From_SMFL_CANID (0x7bdU) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_SMFL_Sig; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_SMFL_Sig; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_SMFL_t; + +// Diagnostic message +// def @Diag_From_SMFR CAN Message (1982 0x7be) +#define Diag_From_SMFR_IDE (0U) +#define Diag_From_SMFR_DLC (8U) +#define Diag_From_SMFR_CANID (0x7beU) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_SMFR_Sig; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_SMFR_Sig; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_SMFR_t; + +// Diagnostic message +// def @Diag_From_SMRL CAN Message (1983 0x7bf) +#define Diag_From_SMRL_IDE (0U) +#define Diag_From_SMRL_DLC (8U) +#define Diag_From_SMRL_CANID (0x7bfU) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_SMRL_Sig; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_SMRL_Sig; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_SMRL_t; + +// Diagnostic message +// def @Diag_To_RCLSilCU CAN Message (1985 0x7c1) +#define Diag_To_RCLSilCU_IDE (0U) +#define Diag_To_RCLSilCU_DLC (8U) +#define Diag_To_RCLSilCU_CANID (0x7c1U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_RCLSilCU; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_RCLSilCU; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_RCLSilCU_t; + +// Diagnostic message +// def @Diag_To_RCRSilCU CAN Message (1986 0x7c2) +#define Diag_To_RCRSilCU_IDE (0U) +#define Diag_To_RCRSilCU_DLC (8U) +#define Diag_To_RCRSilCU_CANID (0x7c2U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_RCRSilCU; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_RCRSilCU; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_RCRSilCU_t; + +// Diagnostic message +// def @Diag_To_RDLSilCU CAN Message (1987 0x7c3) +#define Diag_To_RDLSilCU_IDE (0U) +#define Diag_To_RDLSilCU_DLC (8U) +#define Diag_To_RDLSilCU_CANID (0x7c3U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_RDLSilCU; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_RDLSilCU; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_RDLSilCU_t; + +// Diagnostic message +// def @Diag_To_RDRSilCU CAN Message (1988 0x7c4) +#define Diag_To_RDRSilCU_IDE (0U) +#define Diag_To_RDRSilCU_DLC (8U) +#define Diag_To_RDRSilCU_CANID (0x7c4U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_RDRSilCU; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_RDRSilCU; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_RDRSilCU_t; + +// Diagnostic message +// def @Diag_From_OCUFL CAN Message (1990 0x7c6) +#define Diag_From_OCUFL_IDE (0U) +#define Diag_From_OCUFL_DLC (8U) +#define Diag_From_OCUFL_CANID (0x7c6U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_OCUFL; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_OCUFL; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_OCUFL_t; + +// Diagnostic message +// def @Diag_To_RLDSilCU CAN Message (1992 0x7c8) +#define Diag_To_RLDSilCU_IDE (0U) +#define Diag_To_RLDSilCU_DLC (8U) +#define Diag_To_RLDSilCU_CANID (0x7c8U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_RLDSilCU; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_RLDSilCU; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_RLDSilCU_t; + +// Diagnostic message +// def @Diag_To_RRDSilCU CAN Message (1993 0x7c9) +#define Diag_To_RRDSilCU_IDE (0U) +#define Diag_To_RRDSilCU_DLC (8U) +#define Diag_To_RRDSilCU_CANID (0x7c9U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_RRDSilCU; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_RRDSilCU; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_RRDSilCU_t; + +// Diagnostic message +// def @Diag_From_PTG CAN Message (1995 0x7cb) +#define Diag_From_PTG_IDE (0U) +#define Diag_From_PTG_DLC (8U) +#define Diag_From_PTG_CANID (0x7cbU) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_PTG; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_PTG; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_PTG_t; + +// Diagnostic message +// def @Diag_From_OCUFR CAN Message (1996 0x7cc) +#define Diag_From_OCUFR_IDE (0U) +#define Diag_From_OCUFR_DLC (8U) +#define Diag_From_OCUFR_CANID (0x7ccU) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_OCUFR; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_OCUFR; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_OCUFR_t; + +// Diagnostic message +// def @Diag_From_OCURL CAN Message (1997 0x7cd) +#define Diag_From_OCURL_IDE (0U) +#define Diag_From_OCURL_DLC (8U) +#define Diag_From_OCURL_CANID (0x7cdU) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_OCURL; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_OCURL; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_OCURL_t; + +// Diagnostic message +// def @Diag_From_OCURR CAN Message (1998 0x7ce) +#define Diag_From_OCURR_IDE (0U) +#define Diag_From_OCURR_DLC (8U) +#define Diag_From_OCURR_CANID (0x7ceU) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_OCURR; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_OCURR; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_OCURR_t; + +// Diagnostic message +// def @Diag_From_RCLSilCU CAN Message (2001 0x7d1) +#define Diag_From_RCLSilCU_IDE (0U) +#define Diag_From_RCLSilCU_DLC (8U) +#define Diag_From_RCLSilCU_CANID (0x7d1U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_RCLSilCU; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_RCLSilCU; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_RCLSilCU_t; + +// Diagnostic message +// def @Diag_From_RCRSilCU CAN Message (2002 0x7d2) +#define Diag_From_RCRSilCU_IDE (0U) +#define Diag_From_RCRSilCU_DLC (8U) +#define Diag_From_RCRSilCU_CANID (0x7d2U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_RCRSilCU; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_RCRSilCU; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_RCRSilCU_t; + +// Diagnostic message +// def @Diag_From_RDLSilCU CAN Message (2003 0x7d3) +#define Diag_From_RDLSilCU_IDE (0U) +#define Diag_From_RDLSilCU_DLC (8U) +#define Diag_From_RDLSilCU_CANID (0x7d3U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_RDLSilCU; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_RDLSilCU; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_RDLSilCU_t; + +// Diagnostic message +// def @Diag_From_RDRSilCU CAN Message (2004 0x7d4) +#define Diag_From_RDRSilCU_IDE (0U) +#define Diag_From_RDRSilCU_DLC (8U) +#define Diag_From_RDRSilCU_CANID (0x7d4U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_RDRSilCU; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_RDRSilCU; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_RDRSilCU_t; + +// Diagnostic message +// def @Diag_To_OCUFL CAN Message (2006 0x7d6) +#define Diag_To_OCUFL_IDE (0U) +#define Diag_To_OCUFL_DLC (8U) +#define Diag_To_OCUFL_CANID (0x7d6U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_OCUFL; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_OCUFL; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_OCUFL_t; + +// Diagnostic message +// def @Diag_From_RLDSilCU CAN Message (2008 0x7d8) +#define Diag_From_RLDSilCU_IDE (0U) +#define Diag_From_RLDSilCU_DLC (8U) +#define Diag_From_RLDSilCU_CANID (0x7d8U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_RLDSilCU; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_RLDSilCU; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_RLDSilCU_t; + +// Diagnostic message +// def @Diag_From_RRDSilCU CAN Message (2009 0x7d9) +#define Diag_From_RRDSilCU_IDE (0U) +#define Diag_From_RRDSilCU_DLC (8U) +#define Diag_From_RRDSilCU_CANID (0x7d9U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_RRDSilCU; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_RRDSilCU; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_RRDSilCU_t; + +// Diagnostic message +// def @Diag_To_PTG CAN Message (2011 0x7db) +#define Diag_To_PTG_IDE (0U) +#define Diag_To_PTG_DLC (8U) +#define Diag_To_PTG_CANID (0x7dbU) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_PTG; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_PTG; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_PTG_t; + +// Diagnostic message +// def @Diag_To_OCUFR CAN Message (2012 0x7dc) +#define Diag_To_OCUFR_IDE (0U) +#define Diag_To_OCUFR_DLC (8U) +#define Diag_To_OCUFR_CANID (0x7dcU) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_OCUFR; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_OCUFR; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_OCUFR_t; + +// Diagnostic message +// def @Diag_To_OCURL CAN Message (2013 0x7dd) +#define Diag_To_OCURL_IDE (0U) +#define Diag_To_OCURL_DLC (8U) +#define Diag_To_OCURL_CANID (0x7ddU) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_OCURL; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_OCURL; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_OCURL_t; + +// Diagnostic message +// def @Diag_To_OCURR CAN Message (2014 0x7de) +#define Diag_To_OCURR_IDE (0U) +#define Diag_To_OCURR_DLC (8U) +#define Diag_To_OCURR_CANID (0x7deU) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_OCURR; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_OCURR; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_OCURR_t; + +// Diagnostic message +// def @Diag_Functional CAN Message (2015 0x7df) +#define Diag_Functional_IDE (0U) +#define Diag_Functional_DLC (8U) +#define Diag_Functional_CANID (0x7dfU) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_Functional_Sig; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_Functional_Sig; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_Functional_t; + +// Diagnostic message +// def @Diag_To_SFRSilCU CAN Message (2021 0x7e5) +#define Diag_To_SFRSilCU_IDE (0U) +#define Diag_To_SFRSilCU_DLC (8U) +#define Diag_To_SFRSilCU_CANID (0x7e5U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_SFRSilCU; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_SFRSilCU; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_SFRSilCU_t; + +// Diagnostic message +// def @Diag_To_SFLSilCU CAN Message (2023 0x7e7) +#define Diag_To_SFLSilCU_IDE (0U) +#define Diag_To_SFLSilCU_DLC (8U) +#define Diag_To_SFLSilCU_CANID (0x7e7U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_SFLSilCU; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_SFLSilCU; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_SFLSilCU_t; + +// Diagnostic message +// def @Diag_To_WHFL CAN Message (2032 0x7f0) +#define Diag_To_WHFL_IDE (0U) +#define Diag_To_WHFL_DLC (8U) +#define Diag_To_WHFL_CANID (0x7f0U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_WHFL; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_WHFL; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_WHFL_t; + +// Diagnostic message +// def @Diag_To_WHFR CAN Message (2033 0x7f1) +#define Diag_To_WHFR_IDE (0U) +#define Diag_To_WHFR_DLC (8U) +#define Diag_To_WHFR_CANID (0x7f1U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_To_WHFR; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_To_WHFR; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_To_WHFR_t; + +// Diagnostic message +// def @Diag_From_SFRSilCU CAN Message (2037 0x7f5) +#define Diag_From_SFRSilCU_IDE (0U) +#define Diag_From_SFRSilCU_DLC (8U) +#define Diag_From_SFRSilCU_CANID (0x7f5U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_SFRSilCU; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_SFRSilCU; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_SFRSilCU_t; + +// Diagnostic message +// def @Diag_From_SFLSilCU CAN Message (2039 0x7f7) +#define Diag_From_SFLSilCU_IDE (0U) +#define Diag_From_SFLSilCU_DLC (8U) +#define Diag_From_SFLSilCU_CANID (0x7f7U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_SFLSilCU; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_SFLSilCU; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_SFLSilCU_t; + +// Diagnostic message +// def @Diag_From_WHFL CAN Message (2040 0x7f8) +#define Diag_From_WHFL_IDE (0U) +#define Diag_From_WHFL_DLC (8U) +#define Diag_From_WHFL_CANID (0x7f8U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_WHFL; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_WHFL; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_WHFL_t; + +// Diagnostic message +// def @Diag_From_WHFR CAN Message (2041 0x7f9) +#define Diag_From_WHFR_IDE (0U) +#define Diag_From_WHFR_DLC (8U) +#define Diag_From_WHFR_CANID (0x7f9U) + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // Diagnostic signal + uint64_t Diag_From_WHFR; // Bits=64 + +#else + + // Diagnostic signal + uint64_t Diag_From_WHFR; // Bits=64 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} Diag_From_WHFR_t; + +// def @CCU_AC_Ctrl CAN Message (419426816 0x18fff200) +#define CCU_AC_Ctrl_IDE (1U) +#define CCU_AC_Ctrl_DLC (8U) +#define CCU_AC_Ctrl_CANID (0x18fff200U) +#define CCU_AC_Ctrl_CYC (100U) + +// Value tables for @CCU_VCU_ACSpeedReq signal + +#ifndef CCU_VCU_ACSpeedReq_CCU_AC_Ctrl_Invalid +#define CCU_VCU_ACSpeedReq_CCU_AC_Ctrl_Invalid (65535) +#endif + +// signal: @CCU_ACMaxPowerConsumptionAllow_ro +#define CANDB_CCU_ACMaxPowerConsumptionAllow_ro_CovFactor (0.1) +#define CANDB_CCU_ACMaxPowerConsumptionAllow_ro_toS(x) ( (uint8_t) (((x) - (0.0)) / (0.1)) ) +#define CANDB_CCU_ACMaxPowerConsumptionAllow_ro_fromS(x) ( (((x) * (0.1)) + (0.0)) ) + +// Value tables for @CCU_VCU_AC_WorkReq signal + +#ifndef CCU_VCU_AC_WorkReq_CCU_AC_Ctrl_Active +#define CCU_VCU_AC_WorkReq_CCU_AC_Ctrl_Active (1) +#endif + +#ifndef CCU_VCU_AC_WorkReq_CCU_AC_Ctrl_Standby +#define CCU_VCU_AC_WorkReq_CCU_AC_Ctrl_Standby (0) +#endif + + +typedef struct +{ +#ifdef CANDB_USE_BITS_SIGNAL + + // 65535 : "Invalid" + uint16_t CCU_VCU_ACSpeedReq; // Bits=16 Unit:'rpm' + + uint8_t CCU_ACMaxPowerConsumptionAllow_ro; // Bits= 8 Factor= 0.1 Unit:'kW' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t CCU_ACMaxPowerConsumptionAllow_phys; +#endif // CANDB_USE_SIGFLOAT + + // 1 : "Active" + // 0 : "Standby" + uint8_t CCU_VCU_AC_WorkReq : 1; // Bits= 1 + +#else + + // 65535 : "Invalid" + uint16_t CCU_VCU_ACSpeedReq; // Bits=16 Unit:'rpm' + + uint8_t CCU_ACMaxPowerConsumptionAllow_ro; // Bits= 8 Factor= 0.1 Unit:'kW' + +#ifdef CANDB_USE_SIGFLOAT + sigfloat_t CCU_ACMaxPowerConsumptionAllow_phys; +#endif // CANDB_USE_SIGFLOAT + + // 1 : "Active" + // 0 : "Standby" + uint8_t CCU_VCU_AC_WorkReq; // Bits= 1 + +#endif // CANDB_USE_BITS_SIGNAL + +#ifdef CANDB_USE_DIAG_MONITORS + + FrameMonitor_t mon1; + +#endif // CANDB_USE_DIAG_MONITORS + +} CCU_AC_Ctrl_t; + +// Function signatures + +uint32_t Unpack_SDM_MAS_Req_candb(SDM_MAS_Req_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_SDM_MAS_Req_candb(SDM_MAS_Req_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_SDM_MAS_Req_candb(SDM_MAS_Req_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_EMS_VCU_VAU_Immo_Req_candb(EMS_VCU_VAU_Immo_Req_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_EMS_VCU_VAU_Immo_Req_candb(EMS_VCU_VAU_Immo_Req_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_EMS_VCU_VAU_Immo_Req_candb(EMS_VCU_VAU_Immo_Req_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_TCU_VAU_Immo_Req_candb(TCU_VAU_Immo_Req_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_TCU_VAU_Immo_Req_candb(TCU_VAU_Immo_Req_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_TCU_VAU_Immo_Req_candb(TCU_VAU_Immo_Req_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_VAU2_NFC_TransferState_candb(VAU2_NFC_TransferState_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_VAU2_NFC_TransferState_candb(VAU2_NFC_TransferState_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_VAU2_NFC_TransferState_candb(VAU2_NFC_TransferState_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_VAU_TCU_Hash_Resp_candb(VAU_TCU_Hash_Resp_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_VAU_TCU_Hash_Resp_candb(VAU_TCU_Hash_Resp_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_VAU_TCU_Hash_Resp_candb(VAU_TCU_Hash_Resp_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_VAU_EMS_VCU_Hash_Resp_candb(VAU_EMS_VCU_Hash_Resp_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_VAU_EMS_VCU_Hash_Resp_candb(VAU_EMS_VCU_Hash_Resp_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_VAU_EMS_VCU_Hash_Resp_candb(VAU_EMS_VCU_Hash_Resp_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_VAU2_INVRL_Hash_Resp_candb(VAU2_INVRL_Hash_Resp_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_VAU2_INVRL_Hash_Resp_candb(VAU2_INVRL_Hash_Resp_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_VAU2_INVRL_Hash_Resp_candb(VAU2_INVRL_Hash_Resp_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_WChF_NFC_VAU_Transfer_State_candb(WChF_NFC_VAU_Transfer_State_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_WChF_NFC_VAU_Transfer_State_candb(WChF_NFC_VAU_Transfer_State_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_WChF_NFC_VAU_Transfer_State_candb(WChF_NFC_VAU_Transfer_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_VAU2_INVRR_Hash_Resp_candb(VAU2_INVRR_Hash_Resp_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_VAU2_INVRR_Hash_Resp_candb(VAU2_INVRR_Hash_Resp_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_VAU2_INVRR_Hash_Resp_candb(VAU2_INVRR_Hash_Resp_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_VAU_SDM_Immo_Req_candb(VAU_SDM_Immo_Req_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_VAU_SDM_Immo_Req_candb(VAU_SDM_Immo_Req_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_VAU_SDM_Immo_Req_candb(VAU_SDM_Immo_Req_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SDM_VAU_Hash_Resp_candb(SDM_VAU_Hash_Resp_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_SDM_VAU_Hash_Resp_candb(SDM_VAU_Hash_Resp_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_SDM_VAU_Hash_Resp_candb(SDM_VAU_Hash_Resp_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_TCU_R932_1_candb(TCU_R932_1_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_TCU_R932_1_candb(TCU_R932_1_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_TCU_R932_1_candb(TCU_R932_1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_VAU2_INVF_Hash_Resp_candb(VAU2_INVF_Hash_Resp_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_VAU2_INVF_Hash_Resp_candb(VAU2_INVF_Hash_Resp_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_VAU2_INVF_Hash_Resp_candb(VAU2_INVF_Hash_Resp_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FTCU_DAT1_candb(FTCU_DAT1_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_FTCU_DAT1_candb(FTCU_DAT1_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_FTCU_DAT1_candb(FTCU_DAT1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FTCU_DAT2_candb(FTCU_DAT2_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_FTCU_DAT2_candb(FTCU_DAT2_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_FTCU_DAT2_candb(FTCU_DAT2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FTCU_DAT3_candb(FTCU_DAT3_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_FTCU_DAT3_candb(FTCU_DAT3_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_FTCU_DAT3_candb(FTCU_DAT3_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SCU_02_candb(SCU_02_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_SCU_02_candb(SCU_02_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_SCU_02_candb(SCU_02_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_ESC_04_candb(ESC_04_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_ESC_04_candb(ESC_04_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_ESC_04_candb(ESC_04_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_ESC_09_candb(ESC_09_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_ESC_09_candb(ESC_09_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_ESC_09_candb(ESC_09_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_VAU2_Msg1_candb(VAU2_Msg1_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_VAU2_Msg1_candb(VAU2_Msg1_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_VAU2_Msg1_candb(VAU2_Msg1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_ESC_YRS_01_candb(ESC_YRS_01_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_ESC_YRS_01_candb(ESC_YRS_01_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_ESC_YRS_01_candb(ESC_YRS_01_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_EMS_Veh_candb(EMS_Veh_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_EMS_Veh_candb(EMS_Veh_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_EMS_Veh_candb(EMS_Veh_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_EMS_Indicators_candb(EMS_Indicators_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_EMS_Indicators_candb(EMS_Indicators_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_EMS_Indicators_candb(EMS_Indicators_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_Powertrain_candb(BCM_Powertrain_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_BCM_Powertrain_candb(BCM_Powertrain_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_BCM_Powertrain_candb(BCM_Powertrain_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_EMS_Veh_02_candb(EMS_Veh_02_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_EMS_Veh_02_candb(EMS_Veh_02_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_EMS_Veh_02_candb(EMS_Veh_02_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_EMS_EEM_01_candb(EMS_EEM_01_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_EMS_EEM_01_candb(EMS_EEM_01_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_EMS_EEM_01_candb(EMS_EEM_01_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_EMS_EEM_02_candb(EMS_EEM_02_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_EMS_EEM_02_candb(EMS_EEM_02_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_EMS_EEM_02_candb(EMS_EEM_02_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_EEM_candb(BCM_EEM_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_BCM_EEM_candb(BCM_EEM_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_BCM_EEM_candb(BCM_EEM_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_DAS_01_candb(DAS_01_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_DAS_01_candb(DAS_01_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_DAS_01_candb(DAS_01_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_DAS_04_candb(DAS_04_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_DAS_04_candb(DAS_04_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_DAS_04_candb(DAS_04_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_VCU_DriveInfo_candb(VCU_DriveInfo_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_VCU_DriveInfo_candb(VCU_DriveInfo_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_VCU_DriveInfo_candb(VCU_DriveInfo_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_DAS_02_candb(DAS_02_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_DAS_02_candb(DAS_02_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_DAS_02_candb(DAS_02_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_DAS_07_candb(DAS_07_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_DAS_07_candb(DAS_07_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_DAS_07_candb(DAS_07_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_ACU_01_candb(ACU_01_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_ACU_01_candb(ACU_01_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_ACU_01_candb(ACU_01_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_EPB_Status_candb(EPB_Status_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_EPB_Status_candb(EPB_Status_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_EPB_Status_candb(EPB_Status_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_ExteriorLightState_candb(BCM_ExteriorLightState_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_BCM_ExteriorLightState_candb(BCM_ExteriorLightState_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_BCM_ExteriorLightState_candb(BCM_ExteriorLightState_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SWM_ContrlsState_candb(SWM_ContrlsState_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_SWM_ContrlsState_candb(SWM_ContrlsState_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_SWM_ContrlsState_candb(SWM_ContrlsState_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_StyleCmd1_candb(BCM_StyleCmd1_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_BCM_StyleCmd1_candb(BCM_StyleCmd1_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_BCM_StyleCmd1_candb(BCM_StyleCmd1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_Access_Msg1_candb(FIU_Access_Msg1_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_FIU_Access_Msg1_candb(FIU_Access_Msg1_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_FIU_Access_Msg1_candb(FIU_Access_Msg1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_DMFR_Msg1_candb(DMFR_Msg1_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_DMFR_Msg1_candb(DMFR_Msg1_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_DMFR_Msg1_candb(DMFR_Msg1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_DMFL_Msg1_candb(DMFL_Msg1_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_DMFL_Msg1_candb(DMFL_Msg1_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_DMFL_Msg1_candb(DMFL_Msg1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_DMRL_Msg1_candb(DMRL_Msg1_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_DMRL_Msg1_candb(DMRL_Msg1_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_DMRL_Msg1_candb(DMRL_Msg1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_DMRR_Msg1_candb(DMRR_Msg1_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_DMRR_Msg1_candb(DMRR_Msg1_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_DMRR_Msg1_candb(DMRR_Msg1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_TM_Stat_candb(TM_Stat_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_TM_Stat_candb(TM_Stat_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_TM_Stat_candb(TM_Stat_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_PTG_Body_Stat_candb(PTG_Body_Stat_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_PTG_Body_Stat_candb(PTG_Body_Stat_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_PTG_Body_Stat_candb(PTG_Body_Stat_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_TM_CP_candb(TM_CP_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_TM_CP_candb(TM_CP_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_TM_CP_candb(TM_CP_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_VAU2_Msg2_candb(VAU2_Msg2_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_VAU2_Msg2_candb(VAU2_Msg2_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_VAU2_Msg2_candb(VAU2_Msg2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_DMS_01_candb(BCM_DMS_01_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_BCM_DMS_01_candb(BCM_DMS_01_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_BCM_DMS_01_candb(BCM_DMS_01_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_LB_pSilCU_State_candb(LB_pSilCU_State_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_LB_pSilCU_State_candb(LB_pSilCU_State_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_LB_pSilCU_State_candb(LB_pSilCU_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_RB_pSilCU_State_candb(RB_pSilCU_State_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_RB_pSilCU_State_candb(RB_pSilCU_State_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_RB_pSilCU_State_candb(RB_pSilCU_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_HVC_CCU_Status_Msg_candb(HVC_CCU_Status_Msg_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_HVC_CCU_Status_Msg_candb(HVC_CCU_Status_Msg_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_HVC_CCU_Status_Msg_candb(HVC_CCU_Status_Msg_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_ATS_Status_candb(ATS_Status_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_ATS_Status_candb(ATS_Status_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_ATS_Status_candb(ATS_Status_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_VEH_STATE_candb(BCM_VEH_STATE_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_BCM_VEH_STATE_candb(BCM_VEH_STATE_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_BCM_VEH_STATE_candb(BCM_VEH_STATE_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_Veh_State2_candb(BCM_Veh_State2_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_BCM_Veh_State2_candb(BCM_Veh_State2_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_BCM_Veh_State2_candb(BCM_Veh_State2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_ALS_Light_Front_candb(BCM_ALS_Light_Front_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_BCM_ALS_Light_Front_candb(BCM_ALS_Light_Front_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_BCM_ALS_Light_Front_candb(BCM_ALS_Light_Front_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_ALS_Light_Rear_candb(BCM_ALS_Light_Rear_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_BCM_ALS_Light_Rear_candb(BCM_ALS_Light_Rear_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_BCM_ALS_Light_Rear_candb(BCM_ALS_Light_Rear_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_Rear_Plafond_Light_Data_candb(BCM_Rear_Plafond_Light_Data_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_BCM_Rear_Plafond_Light_Data_candb(BCM_Rear_Plafond_Light_Data_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_BCM_Rear_Plafond_Light_Data_candb(BCM_Rear_Plafond_Light_Data_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_EMS_HVC_Req_Msg_candb(EMS_HVC_Req_Msg_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_EMS_HVC_Req_Msg_candb(EMS_HVC_Req_Msg_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_EMS_HVC_Req_Msg_candb(EMS_HVC_Req_Msg_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SAS_Standard_candb(SAS_Standard_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_SAS_Standard_candb(SAS_Standard_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_SAS_Standard_candb(SAS_Standard_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_IC_ABSOLUTE_CLOCK_candb(IC_ABSOLUTE_CLOCK_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_IC_ABSOLUTE_CLOCK_candb(IC_ABSOLUTE_CLOCK_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_IC_ABSOLUTE_CLOCK_candb(IC_ABSOLUTE_CLOCK_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_Lock_CTR_candb(BCM_Lock_CTR_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_BCM_Lock_CTR_candb(BCM_Lock_CTR_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_BCM_Lock_CTR_candb(BCM_Lock_CTR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_HVC_Err_Status_Msg_candb(HVC_Err_Status_Msg_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_HVC_Err_Status_Msg_candb(HVC_Err_Status_Msg_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_HVC_Err_Status_Msg_candb(HVC_Err_Status_Msg_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_DCDC12_CNTRL_candb(BCM_DCDC12_CNTRL_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_BCM_DCDC12_CNTRL_candb(BCM_DCDC12_CNTRL_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_BCM_DCDC12_CNTRL_candb(BCM_DCDC12_CNTRL_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_CCU_HVC_Req_Msg_candb(CCU_HVC_Req_Msg_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_CCU_HVC_Req_Msg_candb(CCU_HVC_Req_Msg_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_CCU_HVC_Req_Msg_candb(CCU_HVC_Req_Msg_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_CCU_Stat1_candb(CCU_Stat1_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_CCU_Stat1_candb(CCU_Stat1_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_CCU_Stat1_candb(CCU_Stat1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_CCU_Stat2_candb(CCU_Stat2_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_CCU_Stat2_candb(CCU_Stat2_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_CCU_Stat2_candb(CCU_Stat2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_CCU_Requests_candb(CCU_Requests_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_CCU_Requests_candb(CCU_Requests_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_CCU_Requests_candb(CCU_Requests_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_CCU_Stat3_candb(CCU_Stat3_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_CCU_Stat3_candb(CCU_Stat3_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_CCU_Stat3_candb(CCU_Stat3_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_CCU_VCU_Msg1_candb(CCU_VCU_Msg1_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_CCU_VCU_Msg1_candb(CCU_VCU_Msg1_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_CCU_VCU_Msg1_candb(CCU_VCU_Msg1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_CCU_VCU_Msg2_candb(CCU_VCU_Msg2_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_CCU_VCU_Msg2_candb(CCU_VCU_Msg2_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_CCU_VCU_Msg2_candb(CCU_VCU_Msg2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_IC_Info_Msg_candb(BCM_IC_Info_Msg_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_BCM_IC_Info_Msg_candb(BCM_IC_Info_Msg_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_BCM_IC_Info_Msg_candb(BCM_IC_Info_Msg_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_CLIMATIC_DATA_candb(BCM_CLIMATIC_DATA_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_BCM_CLIMATIC_DATA_candb(BCM_CLIMATIC_DATA_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_BCM_CLIMATIC_DATA_candb(BCM_CLIMATIC_DATA_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_DMFL_SMFL_REQ_CTR_SEATS_candb(DMFL_SMFL_REQ_CTR_SEATS_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_DMFL_SMFL_REQ_CTR_SEATS_candb(DMFL_SMFL_REQ_CTR_SEATS_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_DMFL_SMFL_REQ_CTR_SEATS_candb(DMFL_SMFL_REQ_CTR_SEATS_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_DMFR_SMFR_REQ_CTR_SEATS_candb(DMFR_SMFR_REQ_CTR_SEATS_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_DMFR_SMFR_REQ_CTR_SEATS_candb(DMFR_SMFR_REQ_CTR_SEATS_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_DMFR_SMFR_REQ_CTR_SEATS_candb(DMFR_SMFR_REQ_CTR_SEATS_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_DMRL_SMRL_REQ_CTR_SEATS_candb(DMRL_SMRL_REQ_CTR_SEATS_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_DMRL_SMRL_REQ_CTR_SEATS_candb(DMRL_SMRL_REQ_CTR_SEATS_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_DMRL_SMRL_REQ_CTR_SEATS_candb(DMRL_SMRL_REQ_CTR_SEATS_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_DMRR_SMRR_REQ_CTR_SEATS_candb(DMRR_SMRR_REQ_CTR_SEATS_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_DMRR_SMRR_REQ_CTR_SEATS_candb(DMRR_SMRR_REQ_CTR_SEATS_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_DMRR_SMRR_REQ_CTR_SEATS_candb(DMRR_SMRR_REQ_CTR_SEATS_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_CCU_Msg1_candb(CCU_Msg1_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_CCU_Msg1_candb(CCU_Msg1_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_CCU_Msg1_candb(CCU_Msg1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Sroof_State_candb(Sroof_State_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Sroof_State_candb(Sroof_State_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Sroof_State_candb(Sroof_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_VCU_CCU_Req_candb(VCU_CCU_Req_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_VCU_CCU_Req_candb(VCU_CCU_Req_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_VCU_CCU_Req_candb(VCU_CCU_Req_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_IC_DATA_MSG_candb(IC_DATA_MSG_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_IC_DATA_MSG_candb(IC_DATA_MSG_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_IC_DATA_MSG_candb(IC_DATA_MSG_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_ESC_08_candb(ESC_08_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_ESC_08_candb(ESC_08_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_ESC_08_candb(ESC_08_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_WChF_Status_candb(WChF_Status_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_WChF_Status_candb(WChF_Status_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_WChF_Status_candb(WChF_Status_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_MAS_Status_candb(MAS_Status_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_MAS_Status_candb(MAS_Status_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_MAS_Status_candb(MAS_Status_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_EPB_VM_MSG_candb(EPB_VM_MSG_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_EPB_VM_MSG_candb(EPB_VM_MSG_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_EPB_VM_MSG_candb(EPB_VM_MSG_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_CGW_COMM_REQ_candb(CGW_COMM_REQ_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_CGW_COMM_REQ_candb(CGW_COMM_REQ_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_CGW_COMM_REQ_candb(CGW_COMM_REQ_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_DCDC1248_01_candb(DCDC1248_01_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_DCDC1248_01_candb(DCDC1248_01_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_DCDC1248_01_candb(DCDC1248_01_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_REQ_CTR_01_candb(FIU_REQ_CTR_01_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_FIU_REQ_CTR_01_candb(FIU_REQ_CTR_01_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_FIU_REQ_CTR_01_candb(FIU_REQ_CTR_01_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_DCDC1248_02_candb(DCDC1248_02_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_DCDC1248_02_candb(DCDC1248_02_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_DCDC1248_02_candb(DCDC1248_02_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_Access_Msg2_candb(FIU_Access_Msg2_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_FIU_Access_Msg2_candb(FIU_Access_Msg2_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_FIU_Access_Msg2_candb(FIU_Access_Msg2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_Profile_candb(FIU_Profile_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_FIU_Profile_candb(FIU_Profile_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_FIU_Profile_candb(FIU_Profile_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_USBSw_Stat_candb(USBSw_Stat_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_USBSw_Stat_candb(USBSw_Stat_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_USBSw_Stat_candb(USBSw_Stat_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SMFL_status_candb(SMFL_status_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_SMFL_status_candb(SMFL_status_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_SMFL_status_candb(SMFL_status_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SMFR_status_candb(SMFR_status_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_SMFR_status_candb(SMFR_status_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_SMFR_status_candb(SMFR_status_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SMRL_status_candb(SMRL_status_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_SMRL_status_candb(SMRL_status_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_SMRL_status_candb(SMRL_status_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SMRR_status_candb(SMRR_status_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_SMRR_status_candb(SMRR_status_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_SMRR_status_candb(SMRR_status_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_DocSL_T_FL_candb(DocSL_T_FL_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_DocSL_T_FL_candb(DocSL_T_FL_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_DocSL_T_FL_candb(DocSL_T_FL_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_DocSR_T_FR_candb(DocSR_T_FR_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_DocSR_T_FR_candb(DocSR_T_FR_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_DocSR_T_FR_candb(DocSR_T_FR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_VAU_TPMS_Msg_candb(VAU_TPMS_Msg_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_VAU_TPMS_Msg_candb(VAU_TPMS_Msg_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_VAU_TPMS_Msg_candb(VAU_TPMS_Msg_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_CCU_Errors_candb(CCU_Errors_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_CCU_Errors_candb(CCU_Errors_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_CCU_Errors_candb(CCU_Errors_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_CCU_Msg3_candb(CCU_Msg3_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_CCU_Msg3_candb(CCU_Msg3_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_CCU_Msg3_candb(CCU_Msg3_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_Cmd_candb(FIU_Cmd_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_FIU_Cmd_candb(FIU_Cmd_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_FIU_Cmd_candb(FIU_Cmd_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_IC_SDM_Info_candb(IC_SDM_Info_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_IC_SDM_Info_candb(IC_SDM_Info_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_IC_SDM_Info_candb(IC_SDM_Info_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SDM_Cmd_candb(SDM_Cmd_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_SDM_Cmd_candb(SDM_Cmd_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_SDM_Cmd_candb(SDM_Cmd_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_HUD_MSG_STATUS_candb(HUD_MSG_STATUS_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_HUD_MSG_STATUS_candb(HUD_MSG_STATUS_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_HUD_MSG_STATUS_candb(HUD_MSG_STATUS_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_IC_SDM_Info_02_candb(IC_SDM_Info_02_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_IC_SDM_Info_02_candb(IC_SDM_Info_02_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_IC_SDM_Info_02_candb(IC_SDM_Info_02_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_IC_Milleage_candb(IC_Milleage_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_IC_Milleage_candb(IC_Milleage_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_IC_Milleage_candb(IC_Milleage_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_VEH_VIN_candb(VEH_VIN_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_VEH_VIN_candb(VEH_VIN_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_VEH_VIN_candb(VEH_VIN_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_RunningBoards_candb(BCM_RunningBoards_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_BCM_RunningBoards_candb(BCM_RunningBoards_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_BCM_RunningBoards_candb(BCM_RunningBoards_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_OCUFL_MSG_candb(OCUFL_MSG_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_OCUFL_MSG_candb(OCUFL_MSG_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_OCUFL_MSG_candb(OCUFL_MSG_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_OCUFR_MSG_candb(OCUFR_MSG_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_OCUFR_MSG_candb(OCUFR_MSG_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_OCUFR_MSG_candb(OCUFR_MSG_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_OCURL_MSG_candb(OCURL_MSG_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_OCURL_MSG_candb(OCURL_MSG_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_OCURL_MSG_candb(OCURL_MSG_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_OCURR_MSG_candb(OCURR_MSG_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_OCURR_MSG_candb(OCURR_MSG_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_OCURR_MSG_candb(OCURR_MSG_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_RBCU_BODY_Stat_candb(RBCU_BODY_Stat_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_RBCU_BODY_Stat_candb(RBCU_BODY_Stat_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_RBCU_BODY_Stat_candb(RBCU_BODY_Stat_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_SMRL_REQ_CTR_SEATS_candb(FIU_SMRL_REQ_CTR_SEATS_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_FIU_SMRL_REQ_CTR_SEATS_candb(FIU_SMRL_REQ_CTR_SEATS_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_FIU_SMRL_REQ_CTR_SEATS_candb(FIU_SMRL_REQ_CTR_SEATS_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_SMFR_REQ_CTR_SEATS_candb(FIU_SMFR_REQ_CTR_SEATS_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_FIU_SMFR_REQ_CTR_SEATS_candb(FIU_SMFR_REQ_CTR_SEATS_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_FIU_SMFR_REQ_CTR_SEATS_candb(FIU_SMFR_REQ_CTR_SEATS_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SMFL_MEM1_candb(SMFL_MEM1_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_SMFL_MEM1_candb(SMFL_MEM1_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_SMFL_MEM1_candb(SMFL_MEM1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_MEM_SMFL1_candb(BCM_MEM_SMFL1_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_BCM_MEM_SMFL1_candb(BCM_MEM_SMFL1_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_BCM_MEM_SMFL1_candb(BCM_MEM_SMFL1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SMFL_MEM2_candb(SMFL_MEM2_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_SMFL_MEM2_candb(SMFL_MEM2_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_SMFL_MEM2_candb(SMFL_MEM2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_MEM_SMFL2_candb(BCM_MEM_SMFL2_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_BCM_MEM_SMFL2_candb(BCM_MEM_SMFL2_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_BCM_MEM_SMFL2_candb(BCM_MEM_SMFL2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SMFR_MEM1_candb(SMFR_MEM1_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_SMFR_MEM1_candb(SMFR_MEM1_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_SMFR_MEM1_candb(SMFR_MEM1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_MEM_SMFR1_candb(BCM_MEM_SMFR1_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_BCM_MEM_SMFR1_candb(BCM_MEM_SMFR1_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_BCM_MEM_SMFR1_candb(BCM_MEM_SMFR1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SMFR_MEM2_candb(SMFR_MEM2_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_SMFR_MEM2_candb(SMFR_MEM2_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_SMFR_MEM2_candb(SMFR_MEM2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_MEM_SMFR2_candb(BCM_MEM_SMFR2_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_BCM_MEM_SMFR2_candb(BCM_MEM_SMFR2_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_BCM_MEM_SMFR2_candb(BCM_MEM_SMFR2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SMRL_MEM1_candb(SMRL_MEM1_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_SMRL_MEM1_candb(SMRL_MEM1_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_SMRL_MEM1_candb(SMRL_MEM1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_MEM_SMRL1_candb(BCM_MEM_SMRL1_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_BCM_MEM_SMRL1_candb(BCM_MEM_SMRL1_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_BCM_MEM_SMRL1_candb(BCM_MEM_SMRL1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SMRL_MEM2_candb(SMRL_MEM2_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_SMRL_MEM2_candb(SMRL_MEM2_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_SMRL_MEM2_candb(SMRL_MEM2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_MEM_SMRL2_candb(BCM_MEM_SMRL2_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_BCM_MEM_SMRL2_candb(BCM_MEM_SMRL2_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_BCM_MEM_SMRL2_candb(BCM_MEM_SMRL2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SMRR_MEM1_candb(SMRR_MEM1_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_SMRR_MEM1_candb(SMRR_MEM1_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_SMRR_MEM1_candb(SMRR_MEM1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_MEM_SMRR1_candb(BCM_MEM_SMRR1_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_BCM_MEM_SMRR1_candb(BCM_MEM_SMRR1_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_BCM_MEM_SMRR1_candb(BCM_MEM_SMRR1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SMRR_MEM2_candb(SMRR_MEM2_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_SMRR_MEM2_candb(SMRR_MEM2_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_SMRR_MEM2_candb(SMRR_MEM2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_MEM_SMRR2_candb(BCM_MEM_SMRR2_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_BCM_MEM_SMRR2_candb(BCM_MEM_SMRR2_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_BCM_MEM_SMRR2_candb(BCM_MEM_SMRR2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_SMFL_REQ_CTR_SEATS_candb(FIU_SMFL_REQ_CTR_SEATS_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_FIU_SMFL_REQ_CTR_SEATS_candb(FIU_SMFL_REQ_CTR_SEATS_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_FIU_SMFL_REQ_CTR_SEATS_candb(FIU_SMFL_REQ_CTR_SEATS_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_SMRR_REQ_CTR_SEATS_candb(FIU_SMRR_REQ_CTR_SEATS_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_FIU_SMRR_REQ_CTR_SEATS_candb(FIU_SMRR_REQ_CTR_SEATS_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_FIU_SMRR_REQ_CTR_SEATS_candb(FIU_SMRR_REQ_CTR_SEATS_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_CTRL_DW_candb(FIU_CTRL_DW_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_FIU_CTRL_DW_candb(FIU_CTRL_DW_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_FIU_CTRL_DW_candb(FIU_CTRL_DW_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_DW_STATE_candb(DW_STATE_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_DW_STATE_candb(DW_STATE_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_DW_STATE_candb(DW_STATE_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_Msg1_candb(FIU_Msg1_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_FIU_Msg1_candb(FIU_Msg1_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_FIU_Msg1_candb(FIU_Msg1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_Msg2_candb(FIU_Msg2_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_FIU_Msg2_candb(FIU_Msg2_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_FIU_Msg2_candb(FIU_Msg2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_ERAG_DATA_MSG_candb(ERAG_DATA_MSG_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_ERAG_DATA_MSG_candb(ERAG_DATA_MSG_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_ERAG_DATA_MSG_candb(ERAG_DATA_MSG_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_Msg3_candb(FIU_Msg3_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_FIU_Msg3_candb(FIU_Msg3_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_FIU_Msg3_candb(FIU_Msg3_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_EngMenu_candb(FIU_EngMenu_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_FIU_EngMenu_candb(FIU_EngMenu_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_FIU_EngMenu_candb(FIU_EngMenu_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_WHFL_MSG1_candb(WHFL_MSG1_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_WHFL_MSG1_candb(WHFL_MSG1_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_WHFL_MSG1_candb(WHFL_MSG1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_WHFR_Msg1_candb(WHFR_Msg1_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_WHFR_Msg1_candb(WHFR_Msg1_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_WHFR_Msg1_candb(WHFR_Msg1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_PLDSilCU_State_candb(PLDSilCU_State_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_PLDSilCU_State_candb(PLDSilCU_State_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_PLDSilCU_State_candb(PLDSilCU_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_PRDSilCU_State_candb(PRDSilCU_State_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_PRDSilCU_State_candb(PRDSilCU_State_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_PRDSilCU_State_candb(PRDSilCU_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FLDSilCU_State_candb(FLDSilCU_State_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_FLDSilCU_State_candb(FLDSilCU_State_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_FLDSilCU_State_candb(FLDSilCU_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FRDSilCU_State_candb(FRDSilCU_State_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_FRDSilCU_State_candb(FRDSilCU_State_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_FRDSilCU_State_candb(FRDSilCU_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_RLDSilCU_State_candb(RLDSilCU_State_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_RLDSilCU_State_candb(RLDSilCU_State_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_RLDSilCU_State_candb(RLDSilCU_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_RRDSilCU_State_candb(RRDSilCU_State_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_RRDSilCU_State_candb(RRDSilCU_State_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_RRDSilCU_State_candb(RRDSilCU_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_CCU1_candb(FIU_CCU1_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_FIU_CCU1_candb(FIU_CCU1_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_FIU_CCU1_candb(FIU_CCU1_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_CCU2_candb(FIU_CCU2_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_FIU_CCU2_candb(FIU_CCU2_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_FIU_CCU2_candb(FIU_CCU2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_CCU3_candb(FIU_CCU3_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_FIU_CCU3_candb(FIU_CCU3_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_FIU_CCU3_candb(FIU_CCU3_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_StyleCmd2_candb(BCM_StyleCmd2_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_BCM_StyleCmd2_candb(BCM_StyleCmd2_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_BCM_StyleCmd2_candb(BCM_StyleCmd2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_StyleCmd3_candb(BCM_StyleCmd3_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_BCM_StyleCmd3_candb(BCM_StyleCmd3_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_BCM_StyleCmd3_candb(BCM_StyleCmd3_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_WHF_Request_candb(BCM_WHF_Request_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_BCM_WHF_Request_candb(BCM_WHF_Request_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_BCM_WHF_Request_candb(BCM_WHF_Request_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_IC_DISPLAY_CLOCK_candb(IC_DISPLAY_CLOCK_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_IC_DISPLAY_CLOCK_candb(IC_DISPLAY_CLOCK_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_IC_DISPLAY_CLOCK_candb(IC_DISPLAY_CLOCK_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_BCM_UserConfig_Stat_candb(BCM_UserConfig_Stat_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_BCM_UserConfig_Stat_candb(BCM_UserConfig_Stat_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_BCM_UserConfig_Stat_candb(BCM_UserConfig_Stat_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_MAS_Main_candb(FIU_MAS_Main_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_FIU_MAS_Main_candb(FIU_MAS_Main_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_FIU_MAS_Main_candb(FIU_MAS_Main_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_MAS_APA_Paths_candb(MAS_APA_Paths_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_MAS_APA_Paths_candb(MAS_APA_Paths_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_MAS_APA_Paths_candb(MAS_APA_Paths_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_MAS_APA_ParkPlace_candb(MAS_APA_ParkPlace_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_MAS_APA_ParkPlace_candb(MAS_APA_ParkPlace_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_MAS_APA_ParkPlace_candb(MAS_APA_ParkPlace_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_ICLSilCU_State_candb(ICLSilCU_State_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_ICLSilCU_State_candb(ICLSilCU_State_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_ICLSilCU_State_candb(ICLSilCU_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_ICRSilCU_State_candb(ICRSilCU_State_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_ICRSilCU_State_candb(ICRSilCU_State_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_ICRSilCU_State_candb(ICRSilCU_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SFRSilCU_State_candb(SFRSilCU_State_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_SFRSilCU_State_candb(SFRSilCU_State_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_SFRSilCU_State_candb(SFRSilCU_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SFLSilCU_State_candb(SFLSilCU_State_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_SFLSilCU_State_candb(SFLSilCU_State_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_SFLSilCU_State_candb(SFLSilCU_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_RDRSilCU_State_candb(RDRSilCU_State_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_RDRSilCU_State_candb(RDRSilCU_State_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_RDRSilCU_State_candb(RDRSilCU_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FCSilCU_State_candb(FCSilCU_State_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_FCSilCU_State_candb(FCSilCU_State_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_FCSilCU_State_candb(FCSilCU_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_RCLSilCU_State_candb(RCLSilCU_State_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_RCLSilCU_State_candb(RCLSilCU_State_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_RCLSilCU_State_candb(RCLSilCU_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_RCRSilCU_State_candb(RCRSilCU_State_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_RCRSilCU_State_candb(RCRSilCU_State_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_RCRSilCU_State_candb(RCRSilCU_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_RDLSilCU_State_candb(RDLSilCU_State_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_RDLSilCU_State_candb(RDLSilCU_State_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_RDLSilCU_State_candb(RDLSilCU_State_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_CCPF_BodyTM_Stat_candb(CCPF_BodyTM_Stat_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_CCPF_BodyTM_Stat_candb(CCPF_BodyTM_Stat_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_CCPF_BodyTM_Stat_candb(CCPF_BodyTM_Stat_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_IntCOM_Info_Stat_candb(IntCOM_Info_Stat_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_IntCOM_Info_Stat_candb(IntCOM_Info_Stat_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_IntCOM_Info_Stat_candb(IntCOM_Info_Stat_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_LTE_Sum_State2_candb(LTE_Sum_State2_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_LTE_Sum_State2_candb(LTE_Sum_State2_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_LTE_Sum_State2_candb(LTE_Sum_State2_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_WChF_FIU_TransferState_candb(WChF_FIU_TransferState_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_WChF_FIU_TransferState_candb(WChF_FIU_TransferState_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_WChF_FIU_TransferState_candb(WChF_FIU_TransferState_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_FIU_WChF_TransferState_candb(FIU_WChF_TransferState_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_FIU_WChF_TransferState_candb(FIU_WChF_TransferState_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_FIU_WChF_TransferState_candb(FIU_WChF_TransferState_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_VAU_BLE_Device_candb(VAU_BLE_Device_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_VAU_BLE_Device_candb(VAU_BLE_Device_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_VAU_BLE_Device_candb(VAU_BLE_Device_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_APU_candb(Diag_From_APU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_APU_candb(Diag_From_APU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_APU_candb(Diag_From_APU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SSL_Status_candb(SSL_Status_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_SSL_Status_candb(SSL_Status_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_SSL_Status_candb(SSL_Status_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SSR_Status_candb(SSR_Status_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_SSR_Status_candb(SSR_Status_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_SSR_Status_candb(SSR_Status_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_PTG_To_SupplierTool_candb(PTG_To_SupplierTool_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_PTG_To_SupplierTool_candb(PTG_To_SupplierTool_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_PTG_To_SupplierTool_candb(PTG_To_SupplierTool_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_SupplierTool_To_PTG_candb(SupplierTool_To_PTG_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_SupplierTool_To_PTG_candb(SupplierTool_To_PTG_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_SupplierTool_To_PTG_candb(SupplierTool_To_PTG_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_CCPF_candb(Diag_From_CCPF_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_CCPF_candb(Diag_From_CCPF_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_CCPF_candb(Diag_From_CCPF_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_CCPF_candb(Diag_To_CCPF_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_CCPF_candb(Diag_To_CCPF_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_CCPF_candb(Diag_To_CCPF_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_CCPR_candb(Diag_From_CCPR_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_CCPR_candb(Diag_From_CCPR_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_CCPR_candb(Diag_From_CCPR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_CCPR_candb(Diag_To_CCPR_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_CCPR_candb(Diag_To_CCPR_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_CCPR_candb(Diag_To_CCPR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_SSL_candb(Diag_To_SSL_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_SSL_candb(Diag_To_SSL_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_SSL_candb(Diag_To_SSL_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_SSR_candb(Diag_To_SSR_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_SSR_candb(Diag_To_SSR_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_SSR_candb(Diag_To_SSR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_SSL_candb(Diag_From_SSL_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_SSL_candb(Diag_From_SSL_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_SSL_candb(Diag_From_SSL_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_FCSilCU_candb(Diag_To_FCSilCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_FCSilCU_candb(Diag_To_FCSilCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_FCSilCU_candb(Diag_To_FCSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_SSR_candb(Diag_From_SSR_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_SSR_candb(Diag_From_SSR_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_SSR_candb(Diag_From_SSR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_FLDSilCU_candb(Diag_To_FLDSilCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_FLDSilCU_candb(Diag_To_FLDSilCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_FLDSilCU_candb(Diag_To_FLDSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_FRDSilCU_candb(Diag_To_FRDSilCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_FRDSilCU_candb(Diag_To_FRDSilCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_FRDSilCU_candb(Diag_To_FRDSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_ICLSilCU_candb(Diag_To_ICLSilCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_ICLSilCU_candb(Diag_To_ICLSilCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_ICLSilCU_candb(Diag_To_ICLSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_FCSilCU_candb(Diag_From_FCSilCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_FCSilCU_candb(Diag_From_FCSilCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_FCSilCU_candb(Diag_From_FCSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_FLDSilCU_candb(Diag_From_FLDSilCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_FLDSilCU_candb(Diag_From_FLDSilCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_FLDSilCU_candb(Diag_From_FLDSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_FRDSilCU_candb(Diag_From_FRDSilCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_FRDSilCU_candb(Diag_From_FRDSilCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_FRDSilCU_candb(Diag_From_FRDSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_ICLSilCU_candb(Diag_From_ICLSilCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_ICLSilCU_candb(Diag_From_ICLSilCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_ICLSilCU_candb(Diag_From_ICLSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_APU_candb(Diag_To_APU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_APU_candb(Diag_To_APU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_APU_candb(Diag_To_APU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_FTCU_candb(Diag_To_FTCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_FTCU_candb(Diag_To_FTCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_FTCU_candb(Diag_To_FTCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_FTCU_candb(Diag_From_FTCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_FTCU_candb(Diag_From_FTCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_FTCU_candb(Diag_From_FTCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_Sroof_candb(Diag_To_Sroof_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_Sroof_candb(Diag_To_Sroof_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_Sroof_candb(Diag_To_Sroof_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_SRoof_candb(Diag_From_SRoof_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_SRoof_candb(Diag_From_SRoof_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_SRoof_candb(Diag_From_SRoof_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_ICRSilCU_candb(Diag_To_ICRSilCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_ICRSilCU_candb(Diag_To_ICRSilCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_ICRSilCU_candb(Diag_To_ICRSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_LB_pSilCU_candb(Diag_To_LB_pSilCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_LB_pSilCU_candb(Diag_To_LB_pSilCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_LB_pSilCU_candb(Diag_To_LB_pSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_PLSilCU_candb(Diag_To_PLSilCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_PLSilCU_candb(Diag_To_PLSilCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_PLSilCU_candb(Diag_To_PLSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_PRSilCU_candb(Diag_To_PRSilCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_PRSilCU_candb(Diag_To_PRSilCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_PRSilCU_candb(Diag_To_PRSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_RB_pSilCU_candb(Diag_To_RB_pSilCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_RB_pSilCU_candb(Diag_To_RB_pSilCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_RB_pSilCU_candb(Diag_To_RB_pSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_ICRSilCU_candb(Diag_From_ICRSilCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_ICRSilCU_candb(Diag_From_ICRSilCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_ICRSilCU_candb(Diag_From_ICRSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_LB_pSilCU_candb(Diag_From_LB_pSilCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_LB_pSilCU_candb(Diag_From_LB_pSilCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_LB_pSilCU_candb(Diag_From_LB_pSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_PLSilCU_candb(Diag_From_PLSilCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_PLSilCU_candb(Diag_From_PLSilCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_PLSilCU_candb(Diag_From_PLSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_PRSilCU_candb(Diag_From_PRSilCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_PRSilCU_candb(Diag_From_PRSilCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_PRSilCU_candb(Diag_From_PRSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_RB_pSilCU_candb(Diag_From_RB_pSilCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_RB_pSilCU_candb(Diag_From_RB_pSilCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_RB_pSilCU_candb(Diag_From_RB_pSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_VAU_candb(Diag_To_VAU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_VAU_candb(Diag_To_VAU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_VAU_candb(Diag_To_VAU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_BCM_candb(Diag_To_BCM_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_BCM_candb(Diag_To_BCM_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_BCM_candb(Diag_To_BCM_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_DMFL_candb(Diag_To_DMFL_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_DMFL_candb(Diag_To_DMFL_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_DMFL_candb(Diag_To_DMFL_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_DMFR_candb(Diag_To_DMFR_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_DMFR_candb(Diag_To_DMFR_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_DMFR_candb(Diag_To_DMFR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_DMRL_candb(Diag_To_DMRL_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_DMRL_candb(Diag_To_DMRL_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_DMRL_candb(Diag_To_DMRL_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_DMRR_candb(Diag_To_DMRR_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_DMRR_candb(Diag_To_DMRR_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_DMRR_candb(Diag_To_DMRR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_SMRR_candb(Diag_To_SMRR_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_SMRR_candb(Diag_To_SMRR_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_SMRR_candb(Diag_To_SMRR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_TM_candb(Diag_To_TM_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_TM_candb(Diag_To_TM_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_TM_candb(Diag_To_TM_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_CCU_candb(Diag_To_CCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_CCU_candb(Diag_To_CCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_CCU_candb(Diag_To_CCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_SMFL_candb(Diag_To_SMFL_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_SMFL_candb(Diag_To_SMFL_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_SMFL_candb(Diag_To_SMFL_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_SMFR_candb(Diag_To_SMFR_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_SMFR_candb(Diag_To_SMFR_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_SMFR_candb(Diag_To_SMFR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_SMRL_candb(Diag_To_SMRL_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_SMRL_candb(Diag_To_SMRL_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_SMRL_candb(Diag_To_SMRL_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_VAU_candb(Diag_From_VAU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_VAU_candb(Diag_From_VAU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_VAU_candb(Diag_From_VAU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_BCM_candb(Diag_From_BCM_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_BCM_candb(Diag_From_BCM_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_BCM_candb(Diag_From_BCM_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_DMFL_candb(Diag_From_DMFL_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_DMFL_candb(Diag_From_DMFL_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_DMFL_candb(Diag_From_DMFL_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_DMFR_candb(Diag_From_DMFR_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_DMFR_candb(Diag_From_DMFR_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_DMFR_candb(Diag_From_DMFR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_DMRL_candb(Diag_From_DMRL_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_DMRL_candb(Diag_From_DMRL_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_DMRL_candb(Diag_From_DMRL_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_DMRR_candb(Diag_From_DMRR_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_DMRR_candb(Diag_From_DMRR_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_DMRR_candb(Diag_From_DMRR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_SMRR_candb(Diag_From_SMRR_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_SMRR_candb(Diag_From_SMRR_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_SMRR_candb(Diag_From_SMRR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_TM_candb(Diag_From_TM_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_TM_candb(Diag_From_TM_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_TM_candb(Diag_From_TM_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_CCU_candb(Diag_From_CCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_CCU_candb(Diag_From_CCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_CCU_candb(Diag_From_CCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_SMFL_candb(Diag_From_SMFL_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_SMFL_candb(Diag_From_SMFL_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_SMFL_candb(Diag_From_SMFL_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_SMFR_candb(Diag_From_SMFR_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_SMFR_candb(Diag_From_SMFR_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_SMFR_candb(Diag_From_SMFR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_SMRL_candb(Diag_From_SMRL_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_SMRL_candb(Diag_From_SMRL_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_SMRL_candb(Diag_From_SMRL_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_RCLSilCU_candb(Diag_To_RCLSilCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_RCLSilCU_candb(Diag_To_RCLSilCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_RCLSilCU_candb(Diag_To_RCLSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_RCRSilCU_candb(Diag_To_RCRSilCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_RCRSilCU_candb(Diag_To_RCRSilCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_RCRSilCU_candb(Diag_To_RCRSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_RDLSilCU_candb(Diag_To_RDLSilCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_RDLSilCU_candb(Diag_To_RDLSilCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_RDLSilCU_candb(Diag_To_RDLSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_RDRSilCU_candb(Diag_To_RDRSilCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_RDRSilCU_candb(Diag_To_RDRSilCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_RDRSilCU_candb(Diag_To_RDRSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_OCUFL_candb(Diag_From_OCUFL_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_OCUFL_candb(Diag_From_OCUFL_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_OCUFL_candb(Diag_From_OCUFL_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_RLDSilCU_candb(Diag_To_RLDSilCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_RLDSilCU_candb(Diag_To_RLDSilCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_RLDSilCU_candb(Diag_To_RLDSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_RRDSilCU_candb(Diag_To_RRDSilCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_RRDSilCU_candb(Diag_To_RRDSilCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_RRDSilCU_candb(Diag_To_RRDSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_PTG_candb(Diag_From_PTG_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_PTG_candb(Diag_From_PTG_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_PTG_candb(Diag_From_PTG_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_OCUFR_candb(Diag_From_OCUFR_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_OCUFR_candb(Diag_From_OCUFR_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_OCUFR_candb(Diag_From_OCUFR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_OCURL_candb(Diag_From_OCURL_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_OCURL_candb(Diag_From_OCURL_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_OCURL_candb(Diag_From_OCURL_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_OCURR_candb(Diag_From_OCURR_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_OCURR_candb(Diag_From_OCURR_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_OCURR_candb(Diag_From_OCURR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_RCLSilCU_candb(Diag_From_RCLSilCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_RCLSilCU_candb(Diag_From_RCLSilCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_RCLSilCU_candb(Diag_From_RCLSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_RCRSilCU_candb(Diag_From_RCRSilCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_RCRSilCU_candb(Diag_From_RCRSilCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_RCRSilCU_candb(Diag_From_RCRSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_RDLSilCU_candb(Diag_From_RDLSilCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_RDLSilCU_candb(Diag_From_RDLSilCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_RDLSilCU_candb(Diag_From_RDLSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_RDRSilCU_candb(Diag_From_RDRSilCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_RDRSilCU_candb(Diag_From_RDRSilCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_RDRSilCU_candb(Diag_From_RDRSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_OCUFL_candb(Diag_To_OCUFL_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_OCUFL_candb(Diag_To_OCUFL_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_OCUFL_candb(Diag_To_OCUFL_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_RLDSilCU_candb(Diag_From_RLDSilCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_RLDSilCU_candb(Diag_From_RLDSilCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_RLDSilCU_candb(Diag_From_RLDSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_RRDSilCU_candb(Diag_From_RRDSilCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_RRDSilCU_candb(Diag_From_RRDSilCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_RRDSilCU_candb(Diag_From_RRDSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_PTG_candb(Diag_To_PTG_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_PTG_candb(Diag_To_PTG_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_PTG_candb(Diag_To_PTG_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_OCUFR_candb(Diag_To_OCUFR_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_OCUFR_candb(Diag_To_OCUFR_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_OCUFR_candb(Diag_To_OCUFR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_OCURL_candb(Diag_To_OCURL_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_OCURL_candb(Diag_To_OCURL_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_OCURL_candb(Diag_To_OCURL_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_OCURR_candb(Diag_To_OCURR_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_OCURR_candb(Diag_To_OCURR_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_OCURR_candb(Diag_To_OCURR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_Functional_candb(Diag_Functional_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_Functional_candb(Diag_Functional_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_Functional_candb(Diag_Functional_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_SFRSilCU_candb(Diag_To_SFRSilCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_SFRSilCU_candb(Diag_To_SFRSilCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_SFRSilCU_candb(Diag_To_SFRSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_SFLSilCU_candb(Diag_To_SFLSilCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_SFLSilCU_candb(Diag_To_SFLSilCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_SFLSilCU_candb(Diag_To_SFLSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_WHFL_candb(Diag_To_WHFL_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_WHFL_candb(Diag_To_WHFL_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_WHFL_candb(Diag_To_WHFL_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_To_WHFR_candb(Diag_To_WHFR_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_To_WHFR_candb(Diag_To_WHFR_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_To_WHFR_candb(Diag_To_WHFR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_SFRSilCU_candb(Diag_From_SFRSilCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_SFRSilCU_candb(Diag_From_SFRSilCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_SFRSilCU_candb(Diag_From_SFRSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_SFLSilCU_candb(Diag_From_SFLSilCU_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_SFLSilCU_candb(Diag_From_SFLSilCU_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_SFLSilCU_candb(Diag_From_SFLSilCU_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_WHFL_candb(Diag_From_WHFL_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_WHFL_candb(Diag_From_WHFL_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_WHFL_candb(Diag_From_WHFL_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_Diag_From_WHFR_candb(Diag_From_WHFR_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_Diag_From_WHFR_candb(Diag_From_WHFR_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_Diag_From_WHFR_candb(Diag_From_WHFR_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +uint32_t Unpack_CCU_AC_Ctrl_candb(CCU_AC_Ctrl_t* _m, const uint8_t* _d, uint8_t dlc_); +#ifdef CANDB_USE_CANSTRUCT +uint32_t Pack_CCU_AC_Ctrl_candb(CCU_AC_Ctrl_t* _m, __CoderDbcCanFrame_t__* cframe); +#else +uint32_t Pack_CCU_AC_Ctrl_candb(CCU_AC_Ctrl_t* _m, uint8_t* _d, uint8_t* _len, uint8_t* _ide); +#endif // CANDB_USE_CANSTRUCT + +#ifdef __cplusplus +} +#endif diff --git a/MODULES/HVAC_M7_CAN_MATRIX/modular.json b/MODULES/HVAC_M7_CAN_MATRIX/modular.json new file mode 100644 index 0000000..35ce3f4 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/modular.json @@ -0,0 +1,15 @@ +{ + "cmake": { + "inc_dirs": [ + "inc", + "butl", + "conf", + "lib" + ], + "srcs": [ + "butl/**.c", + "lib/**.c", + "usr/**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_CAN_MATRIX/usr/candb-fmon.c b/MODULES/HVAC_M7_CAN_MATRIX/usr/candb-fmon.c new file mode 100644 index 0000000..f56e457 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_MATRIX/usr/candb-fmon.c @@ -0,0 +1,1620 @@ +// Generator version : v3.1 +// DBC filename : CCU.dbc +#include "candb-fmon.h" + +#ifdef CANDB_USE_DIAG_MONITORS + +/* +Put the monitor function content here, keep in mind - +next generation will completely clear all manually added code (!) +*/ + +#ifdef CANDB_USE_MONO_FMON + +void _FMon_MONO_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +#else + +void _FMon_SDM_MAS_Req_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_EMS_VCU_VAU_Immo_Req_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_TCU_VAU_Immo_Req_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_VAU2_NFC_TransferState_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_VAU_TCU_Hash_Resp_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_VAU_EMS_VCU_Hash_Resp_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_VAU2_INVRL_Hash_Resp_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_WChF_NFC_VAU_Transfer_State_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_VAU2_INVRR_Hash_Resp_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_VAU_SDM_Immo_Req_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_SDM_VAU_Hash_Resp_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_TCU_R932_1_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_VAU2_INVF_Hash_Resp_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_FTCU_DAT1_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_FTCU_DAT2_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_FTCU_DAT3_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_SCU_02_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_ESC_04_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_ESC_09_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_VAU2_Msg1_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_ESC_YRS_01_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_EMS_Veh_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_EMS_Indicators_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_BCM_Powertrain_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_EMS_Veh_02_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_EMS_EEM_01_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_EMS_EEM_02_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_BCM_EEM_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_DAS_01_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_DAS_04_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_VCU_DriveInfo_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_DAS_02_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_DAS_07_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_ACU_01_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_EPB_Status_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_BCM_ExteriorLightState_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_SWM_ContrlsState_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_BCM_StyleCmd1_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_FIU_Access_Msg1_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_DMFR_Msg1_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_DMFL_Msg1_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_DMRL_Msg1_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_DMRR_Msg1_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_TM_Stat_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_PTG_Body_Stat_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_TM_CP_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_VAU2_Msg2_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_BCM_DMS_01_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_LB_pSilCU_State_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_RB_pSilCU_State_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_HVC_CCU_Status_Msg_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_ATS_Status_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_BCM_VEH_STATE_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_BCM_Veh_State2_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_BCM_ALS_Light_Front_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_BCM_ALS_Light_Rear_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_BCM_Rear_Plafond_Light_Data_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_EMS_HVC_Req_Msg_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_SAS_Standard_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_IC_ABSOLUTE_CLOCK_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_BCM_Lock_CTR_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_HVC_Err_Status_Msg_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_BCM_DCDC12_CNTRL_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_CCU_HVC_Req_Msg_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_CCU_Stat1_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_CCU_Stat2_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_CCU_Requests_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_CCU_Stat3_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_CCU_VCU_Msg1_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_CCU_VCU_Msg2_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_BCM_IC_Info_Msg_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_BCM_CLIMATIC_DATA_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_DMFL_SMFL_REQ_CTR_SEATS_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_DMFR_SMFR_REQ_CTR_SEATS_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_DMRL_SMRL_REQ_CTR_SEATS_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_DMRR_SMRR_REQ_CTR_SEATS_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_CCU_Msg1_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Sroof_State_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_VCU_CCU_Req_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_IC_DATA_MSG_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_ESC_08_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_WChF_Status_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_MAS_Status_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_EPB_VM_MSG_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_CGW_COMM_REQ_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_DCDC1248_01_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_FIU_REQ_CTR_01_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_DCDC1248_02_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_FIU_Access_Msg2_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_FIU_Profile_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_USBSw_Stat_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_SMFL_status_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_SMFR_status_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_SMRL_status_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_SMRR_status_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_DocSL_T_FL_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_DocSR_T_FR_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_VAU_TPMS_Msg_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_CCU_Errors_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_CCU_Msg3_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_FIU_Cmd_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_IC_SDM_Info_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_SDM_Cmd_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_HUD_MSG_STATUS_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_IC_SDM_Info_02_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_IC_Milleage_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_VEH_VIN_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_BCM_RunningBoards_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_OCUFL_MSG_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_OCUFR_MSG_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_OCURL_MSG_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_OCURR_MSG_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_RBCU_BODY_Stat_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_FIU_SMRL_REQ_CTR_SEATS_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_FIU_SMFR_REQ_CTR_SEATS_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_SMFL_MEM1_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_BCM_MEM_SMFL1_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_SMFL_MEM2_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_BCM_MEM_SMFL2_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_SMFR_MEM1_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_BCM_MEM_SMFR1_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_SMFR_MEM2_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_BCM_MEM_SMFR2_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_SMRL_MEM1_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_BCM_MEM_SMRL1_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_SMRL_MEM2_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_BCM_MEM_SMRL2_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_SMRR_MEM1_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_BCM_MEM_SMRR1_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_SMRR_MEM2_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_BCM_MEM_SMRR2_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_FIU_SMFL_REQ_CTR_SEATS_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_FIU_SMRR_REQ_CTR_SEATS_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_FIU_CTRL_DW_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_DW_STATE_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_FIU_Msg1_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_FIU_Msg2_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_ERAG_DATA_MSG_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_FIU_Msg3_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_FIU_EngMenu_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_WHFL_MSG1_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_WHFR_Msg1_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_PLDSilCU_State_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_PRDSilCU_State_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_FLDSilCU_State_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_FRDSilCU_State_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_RLDSilCU_State_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_RRDSilCU_State_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_FIU_CCU1_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_FIU_CCU2_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_FIU_CCU3_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_BCM_StyleCmd2_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_BCM_StyleCmd3_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_BCM_WHF_Request_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_IC_DISPLAY_CLOCK_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_BCM_UserConfig_Stat_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_FIU_MAS_Main_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_MAS_APA_Paths_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_MAS_APA_ParkPlace_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_ICLSilCU_State_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_ICRSilCU_State_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_SFRSilCU_State_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_SFLSilCU_State_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_RDRSilCU_State_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_FCSilCU_State_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_RCLSilCU_State_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_RCRSilCU_State_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_RDLSilCU_State_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_CCPF_BodyTM_Stat_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_IntCOM_Info_Stat_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_LTE_Sum_State2_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_WChF_FIU_TransferState_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_FIU_WChF_TransferState_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_VAU_BLE_Device_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_APU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_SSL_Status_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_SSR_Status_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_PTG_To_SupplierTool_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_SupplierTool_To_PTG_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_CCPF_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_CCPF_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_CCPR_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_CCPR_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_SSL_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_SSR_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_SSL_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_FCSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_SSR_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_FLDSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_FRDSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_ICLSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_FCSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_FLDSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_FRDSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_ICLSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_APU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_FTCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_FTCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_Sroof_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_SRoof_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_ICRSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_LB_pSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_PLSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_PRSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_RB_pSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_ICRSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_LB_pSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_PLSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_PRSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_RB_pSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_VAU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_BCM_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_DMFL_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_DMFR_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_DMRL_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_DMRR_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_SMRR_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_TM_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_CCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_SMFL_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_SMFR_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_SMRL_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_VAU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_BCM_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_DMFL_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_DMFR_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_DMRL_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_DMRR_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_SMRR_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_TM_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_CCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_SMFL_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_SMFR_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_SMRL_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_RCLSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_RCRSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_RDLSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_RDRSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_OCUFL_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_RLDSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_RRDSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_PTG_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_OCUFR_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_OCURL_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_OCURR_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_RCLSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_RCRSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_RDLSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_RDRSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_OCUFL_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_RLDSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_RRDSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_PTG_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_OCUFR_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_OCURL_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_OCURR_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_Functional_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_SFRSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_SFLSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_WHFL_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_To_WHFR_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_SFRSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_SFLSilCU_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_WHFL_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_Diag_From_WHFR_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +void _FMon_CCU_AC_Ctrl_candb(FrameMonitor_t* _mon, uint32_t msgid) +{ + (void)_mon; + (void)msgid; +} + +#endif // CANDB_USE_MONO_FMON + +#endif // CANDB_USE_DIAG_MONITORS diff --git a/MODULES/HVAC_M7_CAN_SPAM/CanSpamReceiver.c b/MODULES/HVAC_M7_CAN_SPAM/CanSpamReceiver.c new file mode 100644 index 0000000..ae84265 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_SPAM/CanSpamReceiver.c @@ -0,0 +1,243 @@ +// +// Created by cfif on 05.04.2024. +// +#include +#include "CanSpamReceiver.h" +#include "CmsisRtosThreadUtils.h" +#include "CanPorts.h" +#include "string.h" +#include "HVAC_model.h" + +#define LOG_SIGN "CAN_RECEIVED" +#define LOGGER env->logger + +void CanSpamReceiver_Init(tCanSpamReceiver *env, + tSerialPortFrameIO *ioCanFrame, + tLoggerInterface *logger) { + + env->ioCanFrame = ioCanFrame; + env->logger = logger; + env->access = osMutexNew(NULL); + + + env->ccu_candb_rx_TM_CP = osMessageQueueNew(1, sizeof(ccu_candb_rx.TM_CP), NULL); + env->ccu_candb_rx_FIU_CCU1 = osMessageQueueNew(1, sizeof(ccu_candb_rx.FIU_CCU1), NULL); + env->ccu_candb_rx_FIU_CCU2 = osMessageQueueNew(1, sizeof(ccu_candb_rx.FIU_CCU2), NULL); + env->ccu_candb_rx_BCM_Powertrain = osMessageQueueNew(1, sizeof(ccu_candb_rx.BCM_Powertrain), NULL); + env->ccu_candb_rx_BCM_CLIMATIC_DATA = osMessageQueueNew(1, sizeof(ccu_candb_rx.BCM_CLIMATIC_DATA), NULL); + env->ccu_candb_rx_EMS_Veh = osMessageQueueNew(1, sizeof(ccu_candb_rx.EMS_Veh), NULL); + env->ccu_candb_rx_ESC_04 = osMessageQueueNew(1, sizeof(ccu_candb_rx.ESC_04), NULL); + env->ccu_candb_rx_BCM_VEH_STATE = osMessageQueueNew(1, sizeof(ccu_candb_rx.BCM_VEH_STATE), NULL); + env->ccu_candb_rx_EMS_HVC_Req_Msg = osMessageQueueNew(1, sizeof(ccu_candb_rx.EMS_HVC_Req_Msg), NULL); + env->ccu_candb_rx_HVC_Err_Status_Msg = osMessageQueueNew(1, sizeof(ccu_candb_rx.HVC_Err_Status_Msg), NULL); + + + InitThreadAtrStatic(&env->thread.attr, "CanSpamRec", env->thread.controlBlock, env->thread.stack, + osPriorityNormal); +} + +static void set_CanSpamReceiver(tCanSpamReceiver *env, uint32_t recid) { + osStatus_t status = osOK; + + uint32_t countQueue_ccu_candb_rx = osMessageQueueGetSpace(env->ccu_candb_rx_TM_CP); + if ((countQueue_ccu_candb_rx) && (recid == TM_CP_CANID)) { + status = osMessageQueuePut(env->ccu_candb_rx_TM_CP, &ccu_candb_rx.TM_CP, 0, 0U); + } + + countQueue_ccu_candb_rx = osMessageQueueGetSpace(env->ccu_candb_rx_FIU_CCU1); + if ((countQueue_ccu_candb_rx) && (recid == FIU_CCU1_CANID)) { + status = osMessageQueuePut(env->ccu_candb_rx_FIU_CCU1, &ccu_candb_rx.FIU_CCU1, 0, 0U); + } + + countQueue_ccu_candb_rx = osMessageQueueGetSpace(env->ccu_candb_rx_FIU_CCU2); + if ((countQueue_ccu_candb_rx) && (recid == FIU_CCU2_CANID)) { + status = osMessageQueuePut(env->ccu_candb_rx_FIU_CCU2, &ccu_candb_rx.FIU_CCU2, 0, 0U); + } + + countQueue_ccu_candb_rx = osMessageQueueGetSpace(env->ccu_candb_rx_BCM_Powertrain); + if ((countQueue_ccu_candb_rx) && (recid == BCM_Powertrain_CANID)) { + status = osMessageQueuePut(env->ccu_candb_rx_BCM_Powertrain, &ccu_candb_rx.BCM_Powertrain, 0, 0U); + } + + countQueue_ccu_candb_rx = osMessageQueueGetSpace(env->ccu_candb_rx_BCM_CLIMATIC_DATA); + if ((countQueue_ccu_candb_rx) && (recid == BCM_CLIMATIC_DATA_CANID)) { + status = osMessageQueuePut(env->ccu_candb_rx_BCM_CLIMATIC_DATA, &ccu_candb_rx.BCM_CLIMATIC_DATA, 0, 0U); + } + + countQueue_ccu_candb_rx = osMessageQueueGetSpace(env->ccu_candb_rx_EMS_Veh); + if ((countQueue_ccu_candb_rx) && (recid == EMS_Veh_CANID)) { + status = osMessageQueuePut(env->ccu_candb_rx_EMS_Veh, &ccu_candb_rx.EMS_Veh, 0, 0U); + } + + countQueue_ccu_candb_rx = osMessageQueueGetSpace(env->ccu_candb_rx_ESC_04); + if ((countQueue_ccu_candb_rx) && (recid == ESC_04_CANID)) { + status = osMessageQueuePut(env->ccu_candb_rx_ESC_04, &ccu_candb_rx.ESC_04, 0, 0U); + } + + countQueue_ccu_candb_rx = osMessageQueueGetSpace(env->ccu_candb_rx_BCM_VEH_STATE); + if ((countQueue_ccu_candb_rx) && (recid == BCM_VEH_STATE_CANID)) { + status = osMessageQueuePut(env->ccu_candb_rx_BCM_VEH_STATE, &ccu_candb_rx.BCM_VEH_STATE, 0, 0U); + } + + countQueue_ccu_candb_rx = osMessageQueueGetSpace(env->ccu_candb_rx_EMS_HVC_Req_Msg); + if ((countQueue_ccu_candb_rx) && (recid == EMS_HVC_Req_Msg_CANID)) { + status = osMessageQueuePut(env->ccu_candb_rx_EMS_HVC_Req_Msg, &ccu_candb_rx.EMS_HVC_Req_Msg, 0, 0U); + } + + countQueue_ccu_candb_rx = osMessageQueueGetSpace(env->ccu_candb_rx_HVC_Err_Status_Msg); + if ((countQueue_ccu_candb_rx) && (recid == HVC_Err_Status_Msg_CANID)) { + status = osMessageQueuePut(env->ccu_candb_rx_HVC_Err_Status_Msg, &ccu_candb_rx.HVC_Err_Status_Msg, 0, 0U); + } + +} + + +static void ListenCanSpamReceiver(tCanSpamReceiver *env) { + + uint16_t recv = env->ioCanFrame->receive(env->ioCanFrame->env, PROTOCOL_CAN_RAW, (uint8_t *) &env->canFrame, 1, + 1000); + + if (recv == 0) { + return; + } + + if (osMutexAcquire(env->access, 5000) == osOK) { + + uint32_t id = env->canFrame.standard_id; + + if (env->canFrame.id_type == FLEXCAN_ID_EXT) { + id = env->canFrame.extended_id; + } + + env->logger->loggingCan(env->logger->env, 1, 0, env->canFrame.dlc, env->canFrame.standard_id, + env->canFrame.data, SystemGetMs()); + + uint32_t recid = ccu_candb_Receive(&ccu_candb_rx, env->canFrame.data, id, env->canFrame.dlc); + + set_CanSpamReceiver(env, recid); + + osMutexRelease(env->access); + } else { + LoggerErrorStatic(LOGGER, LOG_SIGN, "Access error ListenCanSpamReceiver"); + } + +} + +bool get_is_NoNull_CanSpam_BCM_PowerTrain_Receiver(tCanSpamReceiver *env) { + if (osMutexAcquire(env->access, 5000) == osOK) { + + uint8_t *data = (uint8_t *) &ccu_candb_rx.BCM_Powertrain; + + for (uint8_t i = 0; i < (uint8_t)sizeof(BCM_Powertrain_t); ++i) { + if (data[i] != 0) { + osMutexRelease(env->access); + return true; + } + } + + osMutexRelease(env->access); + } else { + LoggerErrorStatic(LOGGER, LOG_SIGN, "Access error get_CanSpamReceiver"); + } + + return false; +} + +void get_CanSpamReceiver(tCanSpamReceiver *env) { + + osStatus_t status = osOK; + + uint32_t countQueue_ccu_candb_rx = osMessageQueueGetSpace(env->ccu_candb_rx_TM_CP); + if (countQueue_ccu_candb_rx == 0) { + status = osMessageQueueGet(env->ccu_candb_rx_TM_CP, &rtDW.TM_CP_model, 0, 0U); + } + + memset(&rtDW.FIU_CCU1_MODEL, 0, sizeof(rtDW.FIU_CCU1_MODEL)); + memset(&rtDW.FIU_CCU2_MODEL, 0, sizeof(rtDW.FIU_CCU2_MODEL)); + + countQueue_ccu_candb_rx = osMessageQueueGetSpace(env->ccu_candb_rx_FIU_CCU1); + if (countQueue_ccu_candb_rx == 0) { + status = osMessageQueueGet(env->ccu_candb_rx_FIU_CCU1, &rtDW.FIU_CCU1_MODEL, 0, 0U); + } + + countQueue_ccu_candb_rx = osMessageQueueGetSpace(env->ccu_candb_rx_FIU_CCU2); + if (countQueue_ccu_candb_rx == 0) { + status = osMessageQueueGet(env->ccu_candb_rx_FIU_CCU2, &rtDW.FIU_CCU2_MODEL, 0, 0U); + } + + countQueue_ccu_candb_rx = osMessageQueueGetSpace(env->ccu_candb_rx_BCM_Powertrain); + if (countQueue_ccu_candb_rx == 0) { + status = osMessageQueueGet(env->ccu_candb_rx_BCM_Powertrain, &rtDW.CCUCAN_BCM_Powertrain_model, 0, 0U); + } + + countQueue_ccu_candb_rx = osMessageQueueGetSpace(env->ccu_candb_rx_BCM_CLIMATIC_DATA); + if (countQueue_ccu_candb_rx == 0) { + status = osMessageQueueGet(env->ccu_candb_rx_BCM_CLIMATIC_DATA, &rtDW.CCUCAN_BCM_Climatic_model, 0, 0U); + } + + countQueue_ccu_candb_rx = osMessageQueueGetSpace(env->ccu_candb_rx_EMS_Veh); + if (countQueue_ccu_candb_rx == 0) { + status = osMessageQueueGet(env->ccu_candb_rx_EMS_Veh, &rtDW.CCUCAN_EMS_Veh_model, 0, 0U); + } + + countQueue_ccu_candb_rx = osMessageQueueGetSpace(env->ccu_candb_rx_ESC_04); + if (countQueue_ccu_candb_rx == 0) { + status = osMessageQueueGet(env->ccu_candb_rx_ESC_04, &rtDW.CCUCAN_ESC_04_model, 0, 0U); + } + + countQueue_ccu_candb_rx = osMessageQueueGetSpace(env->ccu_candb_rx_BCM_VEH_STATE); + if (countQueue_ccu_candb_rx == 0) { + status = osMessageQueueGet(env->ccu_candb_rx_BCM_VEH_STATE, &rtDW.CCUCAN_BCM_VEH_STATE_model, 0, 0U); + } + + countQueue_ccu_candb_rx = osMessageQueueGetSpace(env->ccu_candb_rx_EMS_HVC_Req_Msg); + if (countQueue_ccu_candb_rx == 0) { + status = osMessageQueueGet(env->ccu_candb_rx_EMS_HVC_Req_Msg, &rtDW.CCUCAN_EMS_HVC_REQ_MSG_MODEL, 0, 0U); + } + + countQueue_ccu_candb_rx = osMessageQueueGetSpace(env->ccu_candb_rx_HVC_Err_Status_Msg); + if (countQueue_ccu_candb_rx == 0) { + status = osMessageQueueGet(env->ccu_candb_rx_HVC_Err_Status_Msg, &rtDW.HVC_ERR_STATUS_MSG_MODEL, 0, 0U); + } + + /* + if (osMutexAcquire(env->access, 5000) == osOK) { + memcpy(&rtDW.TM_CP_model, &ccu_candb_rx.TM_CP, sizeof(rtDW.TM_CP_model)); + memcpy(&rtDW.FIU_CCU1_MODEL, &ccu_candb_rx.FIU_CCU1, sizeof(rtDW.FIU_CCU1_MODEL)); + memcpy(&rtDW.FIU_CCU2_MODEL, &ccu_candb_rx.FIU_CCU2, sizeof(rtDW.FIU_CCU2_MODEL)); +// memcpy(&rtDW.FIU_CCU3_MODEL, &ccu_candb_rx.FIU_CCU3, sizeof(rtDW.FIU_CCU3_MODEL)); + + memset(&ccu_candb_rx.FIU_CCU1,0,sizeof(ccu_candb_rx.FIU_CCU1)); + memset(&ccu_candb_rx.FIU_CCU2,0,sizeof(ccu_candb_rx.FIU_CCU2)); + + memcpy(&rtDW.CCUCAN_BCM_Powertrain_model, &ccu_candb_rx.BCM_Powertrain, + sizeof(rtDW.CCUCAN_BCM_Powertrain_model)); + memcpy(&rtDW.CCUCAN_BCM_Climatic_model, &ccu_candb_rx.BCM_CLIMATIC_DATA, + sizeof(rtDW.CCUCAN_BCM_Climatic_model)); + memcpy(&rtDW.CCUCAN_EMS_Veh_model, &ccu_candb_rx.EMS_Veh, sizeof(rtDW.CCUCAN_EMS_Veh_model)); + memcpy(&rtDW.CCUCAN_ESC_04_model, &ccu_candb_rx.ESC_04, sizeof(rtDW.CCUCAN_ESC_04_model)); + memcpy(&rtDW.CCUCAN_BCM_VEH_STATE_model, &ccu_candb_rx.BCM_VEH_STATE, sizeof(rtDW.CCUCAN_BCM_VEH_STATE_model)); + memcpy(&rtDW.CCUCAN_EMS_HVC_REQ_MSG_MODEL, &ccu_candb_rx.EMS_HVC_Req_Msg, + sizeof(rtDW.CCUCAN_EMS_HVC_REQ_MSG_MODEL)); + memcpy(&rtDW.HVC_ERR_STATUS_MSG_MODEL, &ccu_candb_rx.HVC_Err_Status_Msg, sizeof(rtDW.HVC_ERR_STATUS_MSG_MODEL)); + + osMutexRelease(env->access); + + } else { + LoggerErrorStatic(LOGGER, LOG_SIGN, "Access error get_CanSpamReceiver"); + } + */ + +} + +static _Noreturn void CanSpamReceiver_Thread(tCanSpamReceiver *env) { + for (;;) { + ListenCanSpamReceiver(env); + } +} + +void CanSpamReceiver_StartThread(tCanSpamReceiver *env) { + if (!env->thread.id) { + env->thread.id = osThreadNew((osThreadFunc_t) (CanSpamReceiver_Thread), (void *) (env), &env->thread.attr); + } +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_CAN_SPAM/CanSpamReceiver.h b/MODULES/HVAC_M7_CAN_SPAM/CanSpamReceiver.h new file mode 100644 index 0000000..ceb76e7 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_SPAM/CanSpamReceiver.h @@ -0,0 +1,50 @@ +// +// Created by cfif on 05.04.2024. +// + +#ifndef HVAC_CAN_SPAM_RECEIVER_H +#define HVAC_CAN_SPAM_RECEIVER_H + +#include +#include "CanSerialPortFrame.h" +#include "ccu_candb-binutil.h" +#include "LoggerInterface.h" + + +typedef struct { + + tSerialPortFrameIO *ioCanFrame; + osMutexId_t access; + can_rx_message_type canFrame; + + osMessageQueueId_t ccu_candb_rx_TM_CP; + osMessageQueueId_t ccu_candb_rx_FIU_CCU1; + osMessageQueueId_t ccu_candb_rx_FIU_CCU2; + osMessageQueueId_t ccu_candb_rx_BCM_Powertrain; + osMessageQueueId_t ccu_candb_rx_BCM_CLIMATIC_DATA; + osMessageQueueId_t ccu_candb_rx_EMS_Veh; + osMessageQueueId_t ccu_candb_rx_ESC_04; + osMessageQueueId_t ccu_candb_rx_BCM_VEH_STATE; + osMessageQueueId_t ccu_candb_rx_EMS_HVC_Req_Msg; + osMessageQueueId_t ccu_candb_rx_HVC_Err_Status_Msg; + + tLoggerInterface *logger; + + struct { + osThreadId_t id; + uint32_t stack[384]; + StaticTask_t controlBlock; + osThreadAttr_t attr; + } thread; + +} tCanSpamReceiver; + +void CanSpamReceiver_Init(tCanSpamReceiver *env, tSerialPortFrameIO *ioCanFrame, tLoggerInterface *logger); + +void CanSpamReceiver_StartThread(tCanSpamReceiver *env); + +void get_CanSpamReceiver(tCanSpamReceiver *env); + +bool get_is_NoNull_CanSpam_BCM_PowerTrain_Receiver(tCanSpamReceiver *env); + +#endif //HVAC_CAN_SPAM_RECEIVER_H diff --git a/MODULES/HVAC_M7_CAN_SPAM/CanSpamTransmitter.c b/MODULES/HVAC_M7_CAN_SPAM/CanSpamTransmitter.c new file mode 100644 index 0000000..21d4e7e --- /dev/null +++ b/MODULES/HVAC_M7_CAN_SPAM/CanSpamTransmitter.c @@ -0,0 +1,328 @@ +// +// Created by cfif on 05.12.2025. +// +#include +#include "CanSpamTransmitter.h" +#include "CmsisRtosThreadUtils.h" +#include "CanPorts.h" +#include "memory.h" +#include "HVAC_model.h" + +#define LOG_SIGN "CAN_TRANSMITTER" +#define LOGGER env->logger + +void CanSpamTransmitter_Init(tCanSpamTransmitter *env, + tSerialPortFrameIO *ioCanFrame, + tLoggerInterface *logger) { + + env->ioCanFrame = ioCanFrame; + env->logger = logger; + env->access = osMutexNew(NULL); + + env->queue_ccu_candb_tx = osMessageQueueNew(1, sizeof(ccu_candb_tx_t), NULL); + + InitThreadAtrStatic(&env->thread.attr, "CanSpamTrans", env->thread.controlBlock, env->thread.stack, + osPriorityNormal); +} + + +static void sendEventToCan(tCanSpamTransmitter *env) { + if (env->ide) { + env->canFrame.id_type = FLEXCAN_ID_EXT; + env->canFrame.extended_id = env->can_id; + } else { + env->canFrame.id_type = FLEXCAN_ID_STD; + env->canFrame.standard_id = env->can_id; + } + + env->logger->loggingCan(env->logger->env, 1, 1, env->canFrame.dlc, env->canFrame.standard_id, + env->canFrame.data, SystemGetMs()); + + + env->ioCanFrame->transmit(env->ioCanFrame->env, (uint8_t *) &env->canFrame.data, env->canFrame.dlc, + env->can_id, env->canFrame.id_type, 50); +} + +static eTimeEventTransmit isEventTransmitter(tCanSpamTransmitter *env) { + +#if (CCU_Stat1_SEND == 1) + if (env->time_CCU_Stat1_CYC <= env->timeMs) { + env->time_CCU_Stat1_CYC = env->timeMs + CCU_Stat1_CYC; + + env->can_id = Pack_CCU_Stat1_candb(&ccu_candb_tx.CCU_Stat1, env->canFrame.data, &env->canFrame.dlc, &env->ide); + + return event_CCU_Stat1_CYC; + } +#endif + + +#if (CCU_Stat2_SEND == 1) + if (env->time_CCU_Stat2_CYC <= env->timeMs) { + env->time_CCU_Stat2_CYC = env->timeMs + CCU_Stat2_CYC; + + env->can_id = Pack_CCU_Stat2_candb(&ccu_candb_tx.CCU_Stat2, env->canFrame.data, &env->canFrame.dlc, &env->ide); + + return event_CCU_Stat2_CYC; + } +#endif + +#if (CCU_Stat3_SEND == 1) + if (env->time_CCU_Stat3_CYC <= env->timeMs) { + env->time_CCU_Stat3_CYC = env->timeMs + CCU_Stat3_CYC; + + env->can_id = Pack_CCU_Stat3_candb(&ccu_candb_tx.CCU_Stat3, env->canFrame.data, &env->canFrame.dlc, &env->ide); + + return event_CCU_Stat3_CYC; + } +#endif + +#if (CCU_Errors_SEND == 1) + if (env->time_CCU_Errors_CYC <= env->timeMs) { + env->time_CCU_Errors_CYC = env->timeMs + CCU_Errors_CYC; + + env->can_id = Pack_CCU_Errors_candb(&ccu_candb_tx.CCU_Errors, env->canFrame.data, &env->canFrame.dlc, + &env->ide); + + + return event_CCU_Errors_CYC; + } +#endif + + +#if (CCU_Requests_SEND == 1) + if (env->time_CCU_Requests <= env->timeMs) { + env->time_CCU_Requests = env->timeMs + CCU_Requests_CYC; + + env->can_id = Pack_CCU_Requests_candb(&ccu_candb_tx.CCU_Requests, env->canFrame.data, &env->canFrame.dlc, + &env->ide); + + return event_CCU_Requests; + } +#endif + + // начало--------------------------------------0x310 CCU_HVC_Req_Msg------------------------------------------------ + // начало--------------------------------------0x310 CCU_HVC_Req_Msg------------------------------------------------ + // начало--------------------------------------0x310 CCU_HVC_Req_Msg------------------------------------------------ +#if (CCU_HVC_Req_Msg_SEND == 1) + if (env->time_CCU_HVC_Req_Msg <= env->timeMs) { + env->time_CCU_HVC_Req_Msg = env->timeMs + CCU_HVC_Req_Msg_CYC; + + // Rolling Counter [0 - 15] + if (env->CCU_HVC_Req_Msg_CCU_HVC_Req_RC >= 15) { + env->CCU_HVC_Req_Msg_CCU_HVC_Req_RC = 0; + } else { + ++env->CCU_HVC_Req_Msg_CCU_HVC_Req_RC; + } + + ccu_candb_tx.CCU_HVC_Req_Msg.CCU_HVC_Req_RC = env->CCU_HVC_Req_Msg_CCU_HVC_Req_RC; + + + // Checksum XOR8 of the data field this message + // Checksum computed as per XOR algorithm: + // Byte 1 XOR byte 2 .... XOR byte n-1. (n = packet length.) + + uint8_t d0 = (uint8_t) ((ccu_candb_tx.CCU_HVC_Req_Msg.CCU_eCompSpeedReq_Val_ro & (0xFFU))); + uint8_t d1 = (uint8_t) ((ccu_candb_tx.CCU_HVC_Req_Msg.CCU_eCompReq_Stat & (0x01U)) | + ((ccu_candb_tx.CCU_HVC_Req_Msg.CCU_LowTempValve_Req & (0x03U)) << 1U) | + ((ccu_candb_tx.CCU_HVC_Req_Msg.CCU_HVC_Req_RC & (0x0FU)) << 4U)); + + ccu_candb_tx.CCU_HVC_Req_Msg.CCU_HVC_Req_CS = d0 ^ d1; + + env->can_id = Pack_CCU_HVC_Req_Msg_candb(&ccu_candb_tx.CCU_HVC_Req_Msg, env->canFrame.data, &env->canFrame.dlc, + &env->ide); + + return event_CCU_HVC_Req_Msg; + } +#endif + // конец ---------------------------------------0x310 CCU_HVC_Req_Msg------------------------------------------------ + // конец ---------------------------------------0x310 CCU_HVC_Req_Msg------------------------------------------------ + // конец ---------------------------------------0x310 CCU_HVC_Req_Msg------------------------------------------------ + + // начало РЕЗЕРВ--------------------------------------0x315 CCU_VCU_Msg1--------------------------------------------------- + // начало РЕЗЕРВ--------------------------------------0x315 CCU_VCU_Msg1--------------------------------------------------- + // начало РЕЗЕРВ--------------------------------------0x315 CCU_VCU_Msg1--------------------------------------------------- +#if (CCU_VCU_Msg1_SEND == 1) + if (env->time_CCU_VCU_Msg1 <= env->timeMs) { + env->time_CCU_VCU_Msg1 = env->timeMs + CCU_VCU_Msg1_CYC; + + env->can_id = Pack_CCU_VCU_Msg1_candb(&ccu_candb_tx.CCU_VCU_Msg1, env->canFrame.data, &env->canFrame.dlc, + &env->ide); + + return event_CCU_VCU_Msg1; + } +#endif + // конец РЕЗЕРВ---------------------------------------0x315 CCU_VCU_Msg1--------------------------------------------------- + // конец РЕЗЕРВ---------------------------------------0x315 CCU_VCU_Msg1--------------------------------------------------- + // конец РЕЗЕРВ---------------------------------------0x315 CCU_VCU_Msg1--------------------------------------------------- + + // начало РЕЗЕРВ--------------------------------------0x316 CCU_VCU_Msg2--------------------------------------------------- + // начало РЕЗЕРВ--------------------------------------0x316 CCU_VCU_Msg2--------------------------------------------------- + // начало РЕЗЕРВ--------------------------------------0x316 CCU_VCU_Msg2--------------------------------------------------- +#if (CCU_VCU_Msg2_SEND == 1) + if (env->time_CCU_VCU_Msg2 <= env->timeMs) { + env->time_CCU_VCU_Msg2 = env->timeMs + CCU_VCU_Msg2_CYC; + + env->can_id = Pack_CCU_VCU_Msg2_candb(&ccu_candb_tx.CCU_VCU_Msg2, env->canFrame.data, &env->canFrame.dlc, + &env->ide); + + return event_CCU_VCU_Msg2; + } +#endif + // конец РЕЗЕРВ---------------------------------------0x316 CCU_VCU_Msg2--------------------------------------------------- + // конец РЕЗЕРВ---------------------------------------0x316 CCU_VCU_Msg2--------------------------------------------------- + // конец РЕЗЕРВ---------------------------------------0x316 CCU_VCU_Msg2--------------------------------------------------- + + // начало--------------------------------------0x380 CCU_Msg1------------------------------------------------------- + // начало--------------------------------------0x380 CCU_Msg1------------------------------------------------------- + // начало--------------------------------------0x380 CCU_Msg1------------------------------------------------------- +#if (CCU_Msg1_SEND == 1) + if (env->time_CCU_Msg1 <= env->timeMs) { + env->time_CCU_Msg1 = env->timeMs + CCU_Msg1_CYC; + + // Rolling Counter [0 - 15] + if (env->CCU_Msg1_CCU_MSG1_RC >= 15) { + env->CCU_Msg1_CCU_MSG1_RC = 0; + } else { + ++env->CCU_Msg1_CCU_MSG1_RC; + } + + ccu_candb_tx.CCU_Msg1.CCU_MSG1_RC = env->CCU_Msg1_CCU_MSG1_RC; + + + // Checksum XOR8 of the data field this message + // Checksum computed as per XOR algorithm: + // Byte 1 XOR byte 2 .... XOR byte n-1. (n = packet length.) + uint8_t d0 = (uint8_t) ((ccu_candb_tx.CCU_Msg1.CCU_MirrorHeating_Req & (0x03U)) | + ((ccu_candb_tx.CCU_Msg1.CCU_RecirculationLed_Cmd & (0x01U)) << 2U) | + ((ccu_candb_tx.CCU_Msg1.CCU_DefrostLed_Req & (0x01U)) << 3U) | + ((ccu_candb_tx.CCU_Msg1.CCU_SideWindowHeating_Req & (0x03U)) << 4U) | + ((ccu_candb_tx.CCU_Msg1.CCU_RearWindowHeating_Req & (0x03U)) << 6U)); + uint8_t d1 = (uint8_t) ((ccu_candb_tx.CCU_Msg1.CCU_FrontWindowHeating_Req & (0x03U)) | + ((ccu_candb_tx.CCU_Msg1.CCU_EmergAirCleaning_Stat & (0x01U)) << 2U) | + ((ccu_candb_tx.CCU_Msg1.CCU_FireExtinguishSys_Stat & (0x01U)) << 3U)); + uint8_t d3 = (uint8_t) ((ccu_candb_tx.CCU_Msg1.CCU_FLAutoPsngrLed_Cmd & (0x01U)) | + ((ccu_candb_tx.CCU_Msg1.CCU_FRAutoPsngrLed_Cmd & (0x01U)) << 1U) | + ((ccu_candb_tx.CCU_Msg1.CCU_RLAutoPsngrLed_Cmd & (0x01U)) << 2U) | + ((ccu_candb_tx.CCU_Msg1.CCU_RRAutoPsngrLed_Cmd & (0x01U)) << 3U) | + ((ccu_candb_tx.CCU_Msg1.CCU_AC_MaxLed_Cmd & (0x01U)) << 4U)); + uint8_t d6 = (uint8_t) (((ccu_candb_tx.CCU_Msg1.CCU_MSG1_RC & (0x0FU)) << 4U)); + + ccu_candb_tx.CCU_Msg1.CCU_MSG1_CS = d0 ^ d1 ^ d3 ^ d6; + + env->can_id = Pack_CCU_Msg1_candb(&ccu_candb_tx.CCU_Msg1, env->canFrame.data, &env->canFrame.dlc, &env->ide); + + return event_CCU_Msg1; + } +#endif + // начало--------------------------------------0x380 CCU_Msg1------------------------------------------------------- + // начало--------------------------------------0x380 CCU_Msg1------------------------------------------------------- + // начало--------------------------------------0x380 CCU_Msg1------------------------------------------------------- + + // начало--------------------------------------0x501 CCU_Msg3------------------------------------------------------- + // начало--------------------------------------0x501 CCU_Msg3------------------------------------------------------- + // начало--------------------------------------0x501 CCU_Msg3------------------------------------------------------- +#if (CCU_Msg3_SEND == 1) + if (env->time_CCU_Msg3 <= env->timeMs) { + env->time_CCU_Msg3 = env->timeMs + CCU_Msg3_CYC; + + // Rolling Counter [0 - 15] + if (env->CCU_Msg3_CCU_MSG3_RC >= 15) { + env->CCU_Msg3_CCU_MSG3_RC = 0; + } else { + ++env->CCU_Msg3_CCU_MSG3_RC; + } + + ccu_candb_tx.CCU_Msg3.CCU_MSG3_RC = env->CCU_Msg3_CCU_MSG3_RC; + + // Checksum XOR8 of the data field this message + // Checksum computed as per XOR algorithm: + // Byte 1 XOR byte 2 .... XOR byte n-1. (n = packet length.) + + uint8_t d0 = (uint8_t) ((ccu_candb_tx.CCU_Msg3.CCU_FAN_Req & (0x7FU))); + uint8_t d1 = (uint8_t) ((ccu_candb_tx.CCU_Msg3.CCU_RestMode_Stat & (0x03U))); + uint8_t d2 = (uint8_t) ((ccu_candb_tx.CCU_Msg3.CCU_IncarTempSum_Val_ro & (0xFFU))); + uint8_t d3 = (uint8_t) ((ccu_candb_tx.CCU_Msg3.CCU_MSG3_RC & (0x0FU))); + + ccu_candb_tx.CCU_Msg3.CCU_MSG3_CS = d0 ^ d1 ^ d2 ^ d3; + + + env->can_id = Pack_CCU_Msg3_candb(&ccu_candb_tx.CCU_Msg3, env->canFrame.data, &env->canFrame.dlc, &env->ide); + + return event_CCU_Msg3; + } +#endif + // конец--------------------------------------0x501 CCU_Msg3------------------------------------------------------- + // конец--------------------------------------0x501 CCU_Msg3------------------------------------------------------- + // конец--------------------------------------0x501 CCU_Msg3------------------------------------------------------- + + // начало РЕЗЕРВ--------------------------------------0x18FFF200 CCU_AC_Ctrl ------------------------------------------------------- + // начало РЕЗЕРВ--------------------------------------0x18FFF200 CCU_AC_Ctrl ------------------------------------------------------- + // начало РЕЗЕРВ--------------------------------------0x18FFF200 CCU_AC_Ctrl ------------------------------------------------------- +#if (CU_AC_Ctrl_SEND == 1) + if (env->time_CCU_AC_Ctrl <= env->timeMs) { + env->time_CCU_AC_Ctrl = env->timeMs + CCU_AC_Ctrl_CYC; + + env->can_id = Pack_CCU_AC_Ctrl_candb(&ccu_candb_tx.CCU_AC_Ctrl, env->canFrame.data, &env->canFrame.dlc, + &env->ide); + + return event_CCU_AC_Ctrl; + } +#endif + // конец РЕЗЕРВ--------------------------------------0x18FFF200 CCU_AC_Ctrl ------------------------------------------------------- + // конец РЕЗЕРВ--------------------------------------0x18FFF200 CCU_AC_Ctrl ------------------------------------------------------- + // конец РЕЗЕРВ--------------------------------------0x18FFF200 CCU_AC_Ctrl ------------------------------------------------------- + + return event_CCU_none; +} + +void set_CanSpamTransmitter(tCanSpamTransmitter *env, ccu_candb_tx_t *p_ccu_candb_tx) { + + uint32_t countQueue_ccu_candb_tx = osMessageQueueGetSpace(env->queue_ccu_candb_tx); + + if (countQueue_ccu_candb_tx) { + osStatus_t status = osMessageQueuePut(env->queue_ccu_candb_tx, p_ccu_candb_tx, 0, 0U); + } + +} + +void set_CCU_Mute(tCanSpamTransmitter *env, bool mute) { + if (osMutexAcquire(env->access, 5000) == osOK) { + env->isMute = mute; + osMutexRelease(env->access); + } else { + LoggerErrorStatic(LOGGER, LOG_SIGN, "Access error set_CCU_Mute"); + } +} + +static _Noreturn void CanSpamTransmitter_Thread(tCanSpamTransmitter *env) { + for (;;) { + + SystemDelayMs(100); + + osStatus_t status = osMessageQueueGet(env->queue_ccu_candb_tx, &ccu_candb_tx, 0, 0); + + if (env->isMute == false) { + + if (osMutexAcquire(env->access, 5000) == osOK) { + + env->timeMs += 100; + + while (isEventTransmitter(env) != event_CCU_none) { + sendEventToCan(env); + } + + + osMutexRelease(env->access); + } else { + LoggerErrorStatic(LOGGER, LOG_SIGN, "Access error CanSpamTransmitter_Thread"); + } + + } + } +} + +void CanSpamTransmitter_StartThread(tCanSpamTransmitter *env) { + if (!env->thread.id) { + env->thread.id = osThreadNew((osThreadFunc_t) (CanSpamTransmitter_Thread), (void *) (env), &env->thread.attr); + } +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_CAN_SPAM/CanSpamTransmitter.h b/MODULES/HVAC_M7_CAN_SPAM/CanSpamTransmitter.h new file mode 100644 index 0000000..09f1cb7 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_SPAM/CanSpamTransmitter.h @@ -0,0 +1,93 @@ +// +// Created by cfif on 05.12.2025. +// + +#ifndef HVAC_M7_CANSPAMTRANSMITTER_H +#define HVAC_M7_CANSPAMTRANSMITTER_H + +#include +#include "CanSerialPortFrame.h" +#include "ccu_candb-binutil.h" +#include "LoggerInterface.h" + +#define CCU_Stat1_SEND 1 +#define CCU_Stat2_SEND 1 +#define CCU_Stat3_SEND 0 +#define CCU_Errors_SEND 1 + +#define CCU_Requests_SEND 0 +#define CCU_HVC_Req_Msg_SEND 1 +#define CCU_VCU_Msg1_SEND 0 +#define CCU_VCU_Msg2_SEND 0 +#define CCU_Msg1_SEND 1 +#define CCU_Msg3_SEND 1 +#define CU_AC_Ctrl_SEND 0 + + +typedef enum { + event_CCU_none = 0x00, + event_CCU_Stat1_CYC = 0x01, + event_CCU_Stat2_CYC = 0x02, + event_CCU_Stat3_CYC = 0x03, + event_CCU_Errors_CYC = 0x04, + event_CCU_Requests = 0x05, + event_CCU_HVC_Req_Msg = 0x06, + event_CCU_VCU_Msg1 = 0x07, + event_CCU_VCU_Msg2 = 0x08, + event_CCU_Msg1 = 0x09, + event_CCU_Msg3 = 0x0A, + event_CCU_AC_Ctrl = 0x0B +} eTimeEventTransmit; + +typedef struct { + + tSerialPortFrameIO *ioCanFrame; + osMutexId_t access; + can_rx_message_type canFrame; + + osMessageQueueId_t queue_ccu_candb_tx; + + uint32_t can_id; + uint32_t timeMs; + uint8_t ide; + + uint32_t time_CCU_Stat1_CYC; + uint32_t time_CCU_Stat2_CYC; + uint32_t time_CCU_Stat3_CYC; + uint32_t time_CCU_Errors_CYC; + uint32_t time_CCU_Requests; + uint32_t time_CCU_HVC_Req_Msg; + uint32_t time_CCU_VCU_Msg1; + uint32_t time_CCU_VCU_Msg2; + uint32_t time_CCU_Msg1; + uint32_t time_CCU_Msg3; + uint32_t time_CCU_AC_Ctrl; + + uint8_t CCU_HVC_Req_Msg_CCU_HVC_Req_RC; + uint8_t CCU_Msg1_CCU_MSG1_RC; + uint8_t CCU_Msg3_CCU_MSG3_RC; + + bool isMute; + + tLoggerInterface *logger; + + struct { + osThreadId_t id; + uint32_t stack[384]; + StaticTask_t controlBlock; + osThreadAttr_t attr; + } thread; + +} tCanSpamTransmitter; + +void CanSpamTransmitter_Init(tCanSpamTransmitter *env, tSerialPortFrameIO *ioCanFrame, tLoggerInterface *logger); + +void CanSpamTransmitter_StartThread(tCanSpamTransmitter *env); + + + +void set_CCU_Mute(tCanSpamTransmitter *env, bool mute); + +void set_CanSpamTransmitter(tCanSpamTransmitter *env, ccu_candb_tx_t *p_ccu_candb_tx); + +#endif //HVAC_M7_CANSPAMTRANSMITTER_H diff --git a/MODULES/HVAC_M7_CAN_SPAM/modular.json b/MODULES/HVAC_M7_CAN_SPAM/modular.json new file mode 100644 index 0000000..99df025 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_SPAM/modular.json @@ -0,0 +1,10 @@ +{ + "cmake": { + "inc_dirs": [ + "./" + ], + "srcs": [ + "./**.c" + ] + } +} diff --git a/MODULES/HVAC_M7_CAN_UDS/CanUds.c b/MODULES/HVAC_M7_CAN_UDS/CanUds.c new file mode 100644 index 0000000..5870a18 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_UDS/CanUds.c @@ -0,0 +1,2927 @@ +// +// Created by cfif on 20.01.2026. +// +#include "CanUds.h" +#include "CanPorts.h" +#include "memory.h" +#include "TesterPresent_3e.h" +#include "DiagnosticSessionControl_10.h" +#include "StatusError.h" +#include "SystemDelayInterface.h" +#include "candb.h" +#include "stdio.h" +#include "fc7xxx_driver_flash.h" +#include "DownloadFile.h" +#include "crc32_m7.h" +#include "EraseMemory.h" +#include "InternalFlashPage.h" +#include "BootJump.h" + +#define LOG_SIGN "CAN_UDS" +#define LOGGER env->logger + +extern tStatus_Sensor_For_Model model_Status_Sensor_For_Model_input; +extern tStatus_Actuator_For_Model model_Status_Actuator_DoorsActuator_For_Model_input; +extern tStatus_Duct_Tgt_For_Model model_Status_Duct_Tgt_For_Model_input; +extern tStatus_Eva_Tgt_For_Model model_Status_Eva_Tgt_For_Model_input; +extern tStatus_IO_For_Model model_Status_IO_For_Model_input; +extern tStatus_Pwm_For_Model model_Status_Pwm_For_Model_input; +extern tStatus_eComp_For_Model model_Status_eComp_For_Model_input; +extern tStatus_External_For_Model model_Status_External_For_Model_input; +extern tStatus_EMS_For_Model model_Status_EMS_For_Model_input; +extern tStatus_Ionizer_Aroma_For_Model model_Status_Ionizer_Aroma_For_Model_input; +extern tStatus_Duct_Select_For_Model model_Status_Duct_Select_For_Model_input; + + +extern tStatus_Set_For_Model model_Status_Set_For_Model_output; +extern tStatus_Actuator_For_Model model_Status_Actuator_DoorsActuator_For_Model_output; +extern tStatus_Duct_Tgt_For_Model model_Status_Duct_Tgt_For_Model_output; +extern tStatus_Eva_Tgt_For_Model model_Status_Eva_Tgt_For_Model_output; +extern tStatus_IO_For_Model model_Status_IO_For_Model_output; +extern tStatus_Pwm_For_Model model_Status_Pwm_For_Model_output; +extern tStatus_eComp_For_Model model_Status_eComp_For_Model_output; +extern tStatus_External_For_Model model_Status_External_For_Model_output; +extern tStatus_EMS_For_Model model_Status_EMS_For_Model_output; +extern tStatus_Ionizer_Aroma_For_Model model_Status_Ionizer_Aroma_For_Model_output; +extern tStatus_Duct_Select_For_Model model_Status_Duct_Select_For_Model_output; + + +extern uint32_t generate_key(uint32_t seed); + + +//начало ---------------------------------------------------------------------------------------------------------------------- +//начало -----------------------------------------------ОЧРЕДИ----------------------------------------------------------------- +//начало ---------------------------------------------------------------------------------------------------------------------- + +static uint16_t getActProc(uint16_t maxPos, uint16_t pos) { + + uint16_t proc; + + if (maxPos > 0) { + proc = (pos * 1000) / maxPos; + } else { + proc = 0; + } + + if (proc > 1000) { + proc = 1000; + } + + return proc; +} + +// Тут данные должны быть с модели &env->Status_Sensor_For_Model_input и т.д. +void CanUdsInput_Set_Model(tCanUds *env) { + osStatus_t status = osOK; + + uint32_t countQueue_space = osMessageQueueGetSpace(env->queue_input_get_Status_Sensor); + if (countQueue_space) { + status = osMessageQueuePut(env->queue_input_get_Status_Sensor, &rtY.Status_Sensort_model_IO, 0, 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_input_get_Status_Actuator_DoorsActuator); + if (countQueue_space) { + + + model_Status_Actuator_DoorsActuator_For_Model_input.Motor_Def = getActProc( + rtY.Status_Actuator_model_IO.Motor_Def, Actuator_Ch0_Status_Model.in_CPOS_ALL[0]); + +// LoggerFormatInfo(LOGGER, LOG_SIGN, "Motor_Def = %d (max = %d value = %d)", model_Status_Actuator_DoorsActuator_For_Model_input.Motor_Def, rtY.Status_Actuator_model_IO.Motor_Def, Actuator_Ch0_Status_Model.in_CPOS_ALL[0]) + + model_Status_Actuator_DoorsActuator_For_Model_input.Motor_REC = getActProc( + rtY.Status_Actuator_model_IO.Motor_REC, Actuator_Ch0_Status_Model.in_CPOS_ALL[1]); + +// LoggerFormatInfo(LOGGER, LOG_SIGN, "Motor_REC = %d (max = %d value = %d)", model_Status_Actuator_DoorsActuator_For_Model_input.Motor_REC, rtY.Status_Actuator_model_IO.Motor_REC, Actuator_Ch0_Status_Model.in_CPOS_ALL[1]) + + + model_Status_Actuator_DoorsActuator_For_Model_input.Motor_OSA = getActProc( + rtY.Status_Actuator_model_IO.Motor_OSA, Actuator_Ch0_Status_Model.in_CPOS_ALL[2]); + model_Status_Actuator_DoorsActuator_For_Model_input.Motor_Temp1_FL = getActProc( + rtY.Status_Actuator_model_IO.Motor_Temp1_FL, Actuator_Ch0_Status_Model.in_CPOS_ALL[3]); + model_Status_Actuator_DoorsActuator_For_Model_input.Motor_Vent_CFL = getActProc( + rtY.Status_Actuator_model_IO.Motor_Vent_CFL, Actuator_Ch0_Status_Model.in_CPOS_ALL[4]); + model_Status_Actuator_DoorsActuator_For_Model_input.Motor_Vent_SFL = getActProc( + rtY.Status_Actuator_model_IO.Motor_Vent_SFL, Actuator_Ch0_Status_Model.in_CPOS_ALL[5]); + model_Status_Actuator_DoorsActuator_For_Model_input.Motor_Temp2_FL = getActProc( + rtY.Status_Actuator_model_IO.Motor_Temp2_FL, Actuator_Ch0_Status_Model.in_CPOS_ALL[6]); + model_Status_Actuator_DoorsActuator_For_Model_input.Motor_Foot_1FL = getActProc( + rtY.Status_Actuator_model_IO.Motor_Foot_1FL, Actuator_Ch0_Status_Model.in_CPOS_ALL[7]); + model_Status_Actuator_DoorsActuator_For_Model_input.Motor_Foot_2FL = getActProc( + rtY.Status_Actuator_model_IO.Motor_Foot_2FL, Actuator_Ch0_Status_Model.in_CPOS_ALL[8]); + + model_Status_Actuator_DoorsActuator_For_Model_input.Motor_Temp1_FR = getActProc( + rtY.Status_Actuator_model_IO.Motor_Temp1_FR, Actuator_Ch1_Status_Model.in_CPOS_ALL[0]); + +// LoggerFormatInfo(LOGGER, LOG_SIGN, "Motor_Temp1_FR = %d (max = %d value = %d)", model_Status_Actuator_DoorsActuator_For_Model_input.Motor_Temp1_FR, rtY.Status_Actuator_model_IO.Motor_Temp1_FR, Actuator_Ch1_Status_Model.in_CPOS_ALL[0]) + + + model_Status_Actuator_DoorsActuator_For_Model_input.Motor_Vent_CFR = getActProc( + rtY.Status_Actuator_model_IO.Motor_Vent_CFR, Actuator_Ch1_Status_Model.in_CPOS_ALL[1]); + model_Status_Actuator_DoorsActuator_For_Model_input.Motor_Vent_SFR = getActProc( + rtY.Status_Actuator_model_IO.Motor_Vent_SFR, Actuator_Ch1_Status_Model.in_CPOS_ALL[2]); + model_Status_Actuator_DoorsActuator_For_Model_input.Motor_Temp2_FR = getActProc( + rtY.Status_Actuator_model_IO.Motor_Temp2_FR, Actuator_Ch1_Status_Model.in_CPOS_ALL[3]); + model_Status_Actuator_DoorsActuator_For_Model_input.Motor_Foot_1FR = getActProc( + rtY.Status_Actuator_model_IO.Motor_Foot_1FR, Actuator_Ch1_Status_Model.in_CPOS_ALL[4]); + model_Status_Actuator_DoorsActuator_For_Model_input.Motor_Foot_2FR = getActProc( + rtY.Status_Actuator_model_IO.Motor_Foot_2FR, Actuator_Ch1_Status_Model.in_CPOS_ALL[5]); + + model_Status_Actuator_DoorsActuator_For_Model_input.Motor_Temp_RR = getActProc( + rtY.Status_Actuator_model_IO.Motor_Temp_RR, Actuator_Ch2_Status_Model.in_CPOS_ALL[0]); + model_Status_Actuator_DoorsActuator_For_Model_input.Motor_Temp_RL = getActProc( + rtY.Status_Actuator_model_IO.Motor_Temp_RL, Actuator_Ch2_Status_Model.in_CPOS_ALL[1]); + model_Status_Actuator_DoorsActuator_For_Model_input.Motor_Vent_SRL = getActProc( + rtY.Status_Actuator_model_IO.Motor_Vent_SRL, Actuator_Ch2_Status_Model.in_CPOS_ALL[2]); + model_Status_Actuator_DoorsActuator_For_Model_input.Motor_Foot_RL = getActProc( + rtY.Status_Actuator_model_IO.Motor_Foot_RL, Actuator_Ch2_Status_Model.in_CPOS_ALL[3]); + model_Status_Actuator_DoorsActuator_For_Model_input.Motor_Vent_CRL = getActProc( + rtY.Status_Actuator_model_IO.Motor_Vent_CRL, Actuator_Ch2_Status_Model.in_CPOS_ALL[4]); + model_Status_Actuator_DoorsActuator_For_Model_input.Motor_Vent_CRR = getActProc( + rtY.Status_Actuator_model_IO.Motor_Vent_CRR, Actuator_Ch2_Status_Model.in_CPOS_ALL[5]); + model_Status_Actuator_DoorsActuator_For_Model_input.Motor_Foot_RR = getActProc( + rtY.Status_Actuator_model_IO.Motor_Foot_RR, Actuator_Ch2_Status_Model.in_CPOS_ALL[6]); + model_Status_Actuator_DoorsActuator_For_Model_input.Motor_Vent_SRR = getActProc( + rtY.Status_Actuator_model_IO.Motor_Vent_SRR, Actuator_Ch2_Status_Model.in_CPOS_ALL[7]); + model_Status_Actuator_DoorsActuator_For_Model_input.Motor_SealingValve = getActProc( + rtY.Status_Actuator_model_IO.Motor_SealingValve, Actuator_Ch2_Status_Model.in_CPOS_ALL[8]); + + + status = osMessageQueuePut(env->queue_input_get_Status_Actuator_DoorsActuator, + &model_Status_Actuator_DoorsActuator_For_Model_input, 0, 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_input_get_Status_Duct_Tgt); + if (countQueue_space) { + status = osMessageQueuePut(env->queue_input_get_Status_Duct_Tgt, &rtY.Status_Duct_Tgt_model_IO, 0, 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_input_get_Status_Eva_Tgt); + if (countQueue_space) { + status = osMessageQueuePut(env->queue_input_get_Status_Eva_Tgt, &rtY.Status_Eva_Tgt_model_IO, 0, 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_input_get_Status_IO); + if (countQueue_space) { + status = osMessageQueuePut(env->queue_input_get_Status_IO, &model_Status_IO_For_Model_input, 0, 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_input_get_Status_Pwm); + if (countQueue_space) { + status = osMessageQueuePut(env->queue_input_get_Status_Pwm, &model_Status_Pwm_For_Model_input, 0, 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_input_get_Status_eComp); + if (countQueue_space) { + status = osMessageQueuePut(env->queue_input_get_Status_eComp, &model_Status_eComp_For_Model_input, 0, 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_input_get_Status_External); + if (countQueue_space) { + status = osMessageQueuePut(env->queue_input_get_Status_External, &model_Status_External_For_Model_input, 0, 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_input_get_Status_EMS); + if (countQueue_space) { + status = osMessageQueuePut(env->queue_input_get_Status_EMS, &model_Status_EMS_For_Model_input, 0, 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_input_get_Status_Ionizer_Aroma); + if (countQueue_space) { + status = osMessageQueuePut(env->queue_input_get_Status_Ionizer_Aroma, + &model_Status_Ionizer_Aroma_For_Model_input, 0, 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_input_get_Status_Duct_Select); + if (countQueue_space) { + status = osMessageQueuePut(env->queue_input_get_Status_Duct_Select, &rtY.Status_Duct_Select_model_IO, 0, + 0); + } +} + +// Это на вход UDS +static void CanUdsInput_Get_Model(tCanUds *env) { + + osStatus_t status = osOK; + +//---------------------- tStatus_Sensor Status_Sensor; -------------------------------------------------------------- + uint32_t countQueue_space = osMessageQueueGetSpace(env->queue_input_get_Status_Sensor); + + if (countQueue_space == 0) { + + status = osMessageQueueGet(env->queue_input_get_Status_Sensor, &env->Status_Sensor_For_Model_input, + 0, + 0); + + if (status == osOK) { + statusData.Status_Sensor.Ignition = env->Status_Sensor_For_Model_input.Ignition; + statusData.Status_Sensor.Battery = env->Status_Sensor_For_Model_input.Battery; + statusData.Status_Sensor.AMB = env->Status_Sensor_For_Model_input.AMB; + statusData.Status_Sensor.Incar_FL = env->Status_Sensor_For_Model_input.Incar_FL; + statusData.Status_Sensor.Incar_FR = env->Status_Sensor_For_Model_input.Incar_FR; + statusData.Status_Sensor.Incar_RL = env->Status_Sensor_For_Model_input.Incar_RL; + statusData.Status_Sensor.Incar_RR = env->Status_Sensor_For_Model_input.Incar_RR; + statusData.Status_Sensor.Eva_F = env->Status_Sensor_For_Model_input.Eva_F; + statusData.Status_Sensor.Eva_R = env->Status_Sensor_For_Model_input.Eva_R; + statusData.Status_Sensor.Pressure = env->Status_Sensor_For_Model_input.Pressure; + statusData.Status_Sensor.Duct_FL_Upper = env->Status_Sensor_For_Model_input.Duct_FL_Upper; + statusData.Status_Sensor.Duct_FL_Lower = env->Status_Sensor_For_Model_input.Duct_FL_Lower; + statusData.Status_Sensor.Duct_FR_Upper = env->Status_Sensor_For_Model_input.Duct_FR_Upper; + statusData.Status_Sensor.Duct_FR_Lower = env->Status_Sensor_For_Model_input.Duct_FR_Lower; + statusData.Status_Sensor.Duct_RL = env->Status_Sensor_For_Model_input.Duct_RL; + statusData.Status_Sensor.Duct_RR = env->Status_Sensor_For_Model_input.Duct_RR; + statusData.Status_Sensor.Duct_Side_FL = env->Status_Sensor_For_Model_input.Duct_Side_FL; + statusData.Status_Sensor.Duct_Side_FR = env->Status_Sensor_For_Model_input.Duct_Side_FR; + statusData.Status_Sensor.Duct_Side_RL = env->Status_Sensor_For_Model_input.Duct_Side_RL; + statusData.Status_Sensor.Duct_Side_RR = env->Status_Sensor_For_Model_input.Duct_Side_RR; + statusData.Status_Sensor.AQS = env->Status_Sensor_For_Model_input.AQS; + } + } + +//---------------------- Status_Actuator_DoorsActuator --------------------------------------------------------------- + countQueue_space = osMessageQueueGetSpace(env->queue_input_get_Status_Actuator_DoorsActuator); + + if (countQueue_space == 0) { + + status = osMessageQueueGet(env->queue_input_get_Status_Actuator_DoorsActuator, + &env->Status_Actuator_DoorsActuator_For_Model_input, + 0, 0); + + if (status == osOK) { + statusData.Status_Actuator_DoorsActuator_FB.Motor_Def = env->Status_Actuator_DoorsActuator_For_Model_input.Motor_Def; + statusData.Status_Actuator_DoorsActuator_FB.Motor_Vent_SFL = env->Status_Actuator_DoorsActuator_For_Model_input.Motor_Vent_SFL; + statusData.Status_Actuator_DoorsActuator_FB.Motor_Vent_CFL = env->Status_Actuator_DoorsActuator_For_Model_input.Motor_Vent_CFL; + statusData.Status_Actuator_DoorsActuator_FB.Motor_Foot_1FL = env->Status_Actuator_DoorsActuator_For_Model_input.Motor_Foot_1FL; + statusData.Status_Actuator_DoorsActuator_FB.Motor_Foot_2FL = env->Status_Actuator_DoorsActuator_For_Model_input.Motor_Foot_2FL; + statusData.Status_Actuator_DoorsActuator_FB.Motor_Vent_CFR = env->Status_Actuator_DoorsActuator_For_Model_input.Motor_Vent_CFR; + statusData.Status_Actuator_DoorsActuator_FB.Motor_Vent_SFR = env->Status_Actuator_DoorsActuator_For_Model_input.Motor_Vent_SFR; + statusData.Status_Actuator_DoorsActuator_FB.Motor_Foot_1FR = env->Status_Actuator_DoorsActuator_For_Model_input.Motor_Foot_1FR; + statusData.Status_Actuator_DoorsActuator_FB.Motor_Foot_2FR = env->Status_Actuator_DoorsActuator_For_Model_input.Motor_Foot_2FR; + statusData.Status_Actuator_DoorsActuator_FB.Motor_Vent_SRL = env->Status_Actuator_DoorsActuator_For_Model_input.Motor_Vent_SRL; + statusData.Status_Actuator_DoorsActuator_FB.Motor_Vent_CRL = env->Status_Actuator_DoorsActuator_For_Model_input.Motor_Vent_CRL; + statusData.Status_Actuator_DoorsActuator_FB.Motor_Foot_RL = env->Status_Actuator_DoorsActuator_For_Model_input.Motor_Foot_RL; + statusData.Status_Actuator_DoorsActuator_FB.Motor_Vent_CRR = env->Status_Actuator_DoorsActuator_For_Model_input.Motor_Vent_CRR; + statusData.Status_Actuator_DoorsActuator_FB.Motor_Vent_SRR = env->Status_Actuator_DoorsActuator_For_Model_input.Motor_Vent_SRR; + statusData.Status_Actuator_DoorsActuator_FB.Motor_Foot_RR = env->Status_Actuator_DoorsActuator_For_Model_input.Motor_Foot_RR; + statusData.Status_Actuator_DoorsActuator_FB.Motor_Temp1_FL = env->Status_Actuator_DoorsActuator_For_Model_input.Motor_Temp1_FL; + statusData.Status_Actuator_DoorsActuator_FB.Motor_Temp2_FL = env->Status_Actuator_DoorsActuator_For_Model_input.Motor_Temp2_FL; + statusData.Status_Actuator_DoorsActuator_FB.Motor_Temp1_FR = env->Status_Actuator_DoorsActuator_For_Model_input.Motor_Temp1_FR; + statusData.Status_Actuator_DoorsActuator_FB.Motor_Temp2_FR = env->Status_Actuator_DoorsActuator_For_Model_input.Motor_Temp2_FR; + statusData.Status_Actuator_DoorsActuator_FB.Motor_Temp_RL = env->Status_Actuator_DoorsActuator_For_Model_input.Motor_Temp_RL; + statusData.Status_Actuator_DoorsActuator_FB.Motor_Temp_RR = env->Status_Actuator_DoorsActuator_For_Model_input.Motor_Temp_RR; + statusData.Status_Actuator_DoorsActuator_FB.Motor_REC = env->Status_Actuator_DoorsActuator_For_Model_input.Motor_REC; + statusData.Status_Actuator_DoorsActuator_FB.Motor_OSA = env->Status_Actuator_DoorsActuator_For_Model_input.Motor_OSA; + statusData.Status_Actuator_DoorsActuator_FB.Motor_SealingValve = env->Status_Actuator_DoorsActuator_For_Model_input.Motor_SealingValve; + } + } +//---------------------- Status_Duct_Tgt ----------------------------------------------------------------------------- + countQueue_space = osMessageQueueGetSpace(env->queue_input_get_Status_Duct_Tgt); + + if (countQueue_space == 0) { + status = osMessageQueueGet(env->queue_input_get_Status_Duct_Tgt, &env->Status_Duct_Tgt_For_Model_input, 0, 0); + + if (status == osOK) { + statusData.Status_Duct_Tgt_FB.DuctTgt_Vent_FL = env->Status_Duct_Tgt_For_Model_input.DuctTgt_Vent_FL; + statusData.Status_Duct_Tgt_FB.DuctTgt_Foot_FL = env->Status_Duct_Tgt_For_Model_input.DuctTgt_Foot_FL; + statusData.Status_Duct_Tgt_FB.DuctTgt_Vent_FR = env->Status_Duct_Tgt_For_Model_input.DuctTgt_Vent_FR; + statusData.Status_Duct_Tgt_FB.DuctTgt_Foot_FR = env->Status_Duct_Tgt_For_Model_input.DuctTgt_Foot_FR; + statusData.Status_Duct_Tgt_FB.DuctTgt_RL = env->Status_Duct_Tgt_For_Model_input.DuctTgt_RL; + statusData.Status_Duct_Tgt_FB.DuctTgt_RR = env->Status_Duct_Tgt_For_Model_input.DuctTgt_RR; + } + } +//---------------------- Status_Eva_Tgt ------------------------------------------------------------------------------ + countQueue_space = osMessageQueueGetSpace(env->queue_input_get_Status_Eva_Tgt); + + if (countQueue_space == 0) { + status = osMessageQueueGet(env->queue_input_get_Status_Eva_Tgt, &env->Status_Eva_Tgt_For_Model_input, 0, 0); + + if (status == osOK) { + statusData.Status_Eva_Tgt_FB.EvaTgt_F = env->Status_Eva_Tgt_For_Model_input.EvaTgt_F; + statusData.Status_Eva_Tgt_FB.EvaTgt_R = env->Status_Eva_Tgt_For_Model_input.EvaTgt_R; + } + } + +//---------------------- Status_IO ----------------------------------------------------------------------------------- + countQueue_space = osMessageQueueGetSpace(env->queue_input_get_Status_IO); + + if (countQueue_space == 0) { + status = osMessageQueueGet(env->queue_input_get_Status_IO, &env->Status_IO_For_Model_input, 0, 0); + + if (status == osOK) { + + statusData.Status_IO_FB._2_Way_Valve = env->Status_IO_For_Model_input._2_Way_Valve; + statusData.Status_IO_FB.IncarMotor_Front = env->Status_IO_For_Model_input.IncarMotor_Front; + statusData.Status_IO_FB.IncarMotor_Rear = env->Status_IO_For_Model_input.IncarMotor_Rear; + statusData.Status_IO_FB.ShutOff_Chiller = env->Status_IO_For_Model_input.ShutOff_Chiller; + statusData.Status_IO_FB.ShutOff_Front = env->Status_IO_For_Model_input.ShutOff_Front; + statusData.Status_IO_FB.ShutOff_Rear = env->Status_IO_For_Model_input.ShutOff_Rear; + statusData.Status_IO_FB.PTC_1 = env->Status_IO_For_Model_input.PTC_1; + statusData.Status_IO_FB.PTC_2 = env->Status_IO_For_Model_input.PTC_2; + } + } +//---------------------- Status_Pwm ---------------------------------------------------------------------------------- + countQueue_space = osMessageQueueGetSpace(env->queue_input_get_Status_Pwm); + + if (countQueue_space == 0) { + status = osMessageQueueGet(env->queue_input_get_Status_Pwm, &env->Status_Pwm_For_Model_input, 0, 0); + + if (status == osOK) { + statusData.Status_Pwm_FB.Pwm_Front = env->Status_Pwm_For_Model_input.Pwm_Front; + statusData.Status_Pwm_FB.Pwm_Rear = env->Status_Pwm_For_Model_input.Pwm_Rear; + } + } + +//---------------------- Status_eComp--------------------------------------------------------------------------------- + countQueue_space = osMessageQueueGetSpace(env->queue_input_get_Status_eComp); + + if (countQueue_space == 0) { + status = osMessageQueueGet(env->queue_input_get_Status_eComp, &env->Status_eComp_For_Model_input, 0, 0); + + if (status == osOK) { + + statusData.Status_eComp_FB.eComp_Statue_Request = env->Status_eComp_For_Model_input.eComp_Statue_Request; + statusData.Status_eComp_FB.Pwm_Front = env->Status_eComp_For_Model_input.Pwm_Front; + statusData.Status_eComp_FB.LowTempValve = env->Status_eComp_For_Model_input.LowTempValve; + } + } + +//---------------------- Status_External------------------------------------------------------------------------------ + countQueue_space = osMessageQueueGetSpace(env->queue_input_get_Status_External); + + if (countQueue_space == 0) { + status = osMessageQueueGet(env->queue_input_get_Status_External, &env->Status_External_For_Model_input, 0, 0); + + if (status == osOK) { + + statusData.Status_External_FB.CoolingFan = env->Status_External_For_Model_input.CoolingFan; + } + } +//---------------------- Status_EMS----------------------------------------------------------------------------------- + countQueue_space = osMessageQueueGetSpace(env->queue_input_get_Status_EMS); + + if (countQueue_space == 0) { + status = osMessageQueueGet(env->queue_input_get_Status_EMS, &env->Status_EMS_For_Model_input, 0, 0); + + if (status == osOK) { + + statusData.Status_EMS_FB.EMS_Chiller_Req = env->Status_EMS_For_Model_input.EMS_Chiller_Req; + } + } +//---------------------- Status_Ionizer_Aroma------------------------------------------------------------------------- + countQueue_space = osMessageQueueGetSpace(env->queue_input_get_Status_Ionizer_Aroma); + + if (countQueue_space == 0) { + status = osMessageQueueGet(env->queue_input_get_Status_Ionizer_Aroma, + &env->Status_Ionizer_Aroma_For_Model_input, 0, + 0); + if (status == osOK) { + statusData.Status_Ionizer_Aroma_FB.Ionizer = env->Status_Ionizer_Aroma_For_Model_input.Ionizer; + statusData.Status_Ionizer_Aroma_FB.AromatizationIntensivity = env->Status_Ionizer_Aroma_For_Model_input.AromatizationIntensivity; + } + } + +//---------------------- Status_Duct_Select------------------------------------------------------------------------- + countQueue_space = osMessageQueueGetSpace(env->queue_input_get_Status_Duct_Select); + + if (countQueue_space == 0) { + status = osMessageQueueGet(env->queue_input_get_Status_Duct_Select, &env->Status_Duct_Select_For_Model_input, 0, + 0); + + if (status == osOK) { + statusData.Status_Duct_Select_FB.Duct_FL = env->Status_Duct_Select_For_Model_input.Duct_FL; + statusData.Status_Duct_Select_FB.Duct_FR = env->Status_Duct_Select_For_Model_input.Duct_FR; + statusData.Status_Duct_Select_FB.Duct_RL = env->Status_Duct_Select_For_Model_input.Duct_RL; + statusData.Status_Duct_Select_FB.Duct_RR = env->Status_Duct_Select_For_Model_input.Duct_RR; + } + } + +} + +// Это с выхода UDS +static void CanUdsOutput_Set_Model(tCanUds *env) { + +//---------------------- Status_Actuator_DoorsActuator --------------------------------------------------------------- + + env->Status_Actuator_DoorsActuator_For_Model_output.Motor_Def = statusData.Status_Actuator_DoorsActuator.Motor_Def; + env->Status_Actuator_DoorsActuator_For_Model_output.Motor_Vent_SFL = statusData.Status_Actuator_DoorsActuator.Motor_Vent_SFL; + env->Status_Actuator_DoorsActuator_For_Model_output.Motor_Vent_CFL = statusData.Status_Actuator_DoorsActuator.Motor_Vent_CFL; + env->Status_Actuator_DoorsActuator_For_Model_output.Motor_Foot_1FL = statusData.Status_Actuator_DoorsActuator.Motor_Foot_1FL; + env->Status_Actuator_DoorsActuator_For_Model_output.Motor_Foot_2FL = statusData.Status_Actuator_DoorsActuator.Motor_Foot_2FL; + env->Status_Actuator_DoorsActuator_For_Model_output.Motor_Vent_CFR = statusData.Status_Actuator_DoorsActuator.Motor_Vent_CFR; + env->Status_Actuator_DoorsActuator_For_Model_output.Motor_Vent_SFR = statusData.Status_Actuator_DoorsActuator.Motor_Vent_SFR; + env->Status_Actuator_DoorsActuator_For_Model_output.Motor_Foot_1FR = statusData.Status_Actuator_DoorsActuator.Motor_Foot_1FR; + env->Status_Actuator_DoorsActuator_For_Model_output.Motor_Foot_2FR = statusData.Status_Actuator_DoorsActuator.Motor_Foot_2FR; + env->Status_Actuator_DoorsActuator_For_Model_output.Motor_Vent_SRL = statusData.Status_Actuator_DoorsActuator.Motor_Vent_SRL; + env->Status_Actuator_DoorsActuator_For_Model_output.Motor_Vent_CRL = statusData.Status_Actuator_DoorsActuator.Motor_Vent_CRL; + env->Status_Actuator_DoorsActuator_For_Model_output.Motor_Foot_RL = statusData.Status_Actuator_DoorsActuator.Motor_Foot_RL; + env->Status_Actuator_DoorsActuator_For_Model_output.Motor_Vent_CRR = statusData.Status_Actuator_DoorsActuator.Motor_Vent_CRR; + env->Status_Actuator_DoorsActuator_For_Model_output.Motor_Vent_SRR = statusData.Status_Actuator_DoorsActuator.Motor_Vent_SRR; + env->Status_Actuator_DoorsActuator_For_Model_output.Motor_Foot_RR = statusData.Status_Actuator_DoorsActuator.Motor_Foot_RR; + env->Status_Actuator_DoorsActuator_For_Model_output.Motor_Temp1_FL = statusData.Status_Actuator_DoorsActuator.Motor_Temp1_FL; + env->Status_Actuator_DoorsActuator_For_Model_output.Motor_Temp2_FL = statusData.Status_Actuator_DoorsActuator.Motor_Temp2_FL; + env->Status_Actuator_DoorsActuator_For_Model_output.Motor_Temp1_FR = statusData.Status_Actuator_DoorsActuator.Motor_Temp1_FR; + env->Status_Actuator_DoorsActuator_For_Model_output.Motor_Temp2_FR = statusData.Status_Actuator_DoorsActuator.Motor_Temp2_FR; + env->Status_Actuator_DoorsActuator_For_Model_output.Motor_Temp_RL = statusData.Status_Actuator_DoorsActuator.Motor_Temp_RL; + env->Status_Actuator_DoorsActuator_For_Model_output.Motor_Temp_RR = statusData.Status_Actuator_DoorsActuator.Motor_Temp_RR; + env->Status_Actuator_DoorsActuator_For_Model_output.Motor_REC = statusData.Status_Actuator_DoorsActuator.Motor_REC; + env->Status_Actuator_DoorsActuator_For_Model_output.Motor_OSA = statusData.Status_Actuator_DoorsActuator.Motor_OSA; + env->Status_Actuator_DoorsActuator_For_Model_output.Motor_SealingValve = statusData.Status_Actuator_DoorsActuator.Motor_SealingValve; + +//---------------------- Status_Duct_Tgt ----------------------------------------------------------------------------- + + env->Status_Duct_Tgt_For_Model_output.DuctTgt_Vent_FL = statusData.Status_Duct_Tgt.DuctTgt_Vent_FL; + env->Status_Duct_Tgt_For_Model_output.DuctTgt_Foot_FL = statusData.Status_Duct_Tgt.DuctTgt_Foot_FL; + env->Status_Duct_Tgt_For_Model_output.DuctTgt_Vent_FR = statusData.Status_Duct_Tgt.DuctTgt_Vent_FR; + env->Status_Duct_Tgt_For_Model_output.DuctTgt_Foot_FR = statusData.Status_Duct_Tgt.DuctTgt_Foot_FR; + env->Status_Duct_Tgt_For_Model_output.DuctTgt_RL = statusData.Status_Duct_Tgt.DuctTgt_RL; + env->Status_Duct_Tgt_For_Model_output.DuctTgt_RR = statusData.Status_Duct_Tgt.DuctTgt_RR; + +//---------------------- Status_Eva_Tgt ------------------------------------------------------------------------------ + + env->Status_Eva_Tgt_For_Model_output.EvaTgt_F = statusData.Status_Eva_Tgt.EvaTgt_F; + env->Status_Eva_Tgt_For_Model_output.EvaTgt_R = statusData.Status_Eva_Tgt.EvaTgt_R; + +//---------------------- Status_IO ----------------------------------------------------------------------------------- + + env->Status_IO_For_Model_output._2_Way_Valve = statusData.Status_IO._2_Way_Valve; + env->Status_IO_For_Model_output.IncarMotor_Front = statusData.Status_IO.IncarMotor_Front; + env->Status_IO_For_Model_output.IncarMotor_Rear = statusData.Status_IO.IncarMotor_Rear; + env->Status_IO_For_Model_output.ShutOff_Chiller = statusData.Status_IO.ShutOff_Chiller; + env->Status_IO_For_Model_output.ShutOff_Front = statusData.Status_IO.ShutOff_Front; + env->Status_IO_For_Model_output.ShutOff_Rear = statusData.Status_IO.ShutOff_Rear; + env->Status_IO_For_Model_output.PTC_1 = statusData.Status_IO.PTC_1; + env->Status_IO_For_Model_output.PTC_2 = statusData.Status_IO.PTC_2; + +//---------------------- Status_Pwm ---------------------------------------------------------------------------------- + + env->Status_Pwm_For_Model_output.Pwm_Front = statusData.Status_Pwm.Pwm_Front; + env->Status_Pwm_For_Model_output.Pwm_Rear = statusData.Status_Pwm.Pwm_Rear; + +//---------------------- Status_eComp--------------------------------------------------------------------------------- + env->Status_eComp_For_Model_output.eComp_Statue_Request = statusData.Status_eComp.eComp_Statue_Request; + env->Status_eComp_For_Model_output.Pwm_Front = statusData.Status_eComp.Pwm_Front; + env->Status_eComp_For_Model_output.LowTempValve = statusData.Status_eComp.LowTempValve; + +//---------------------- Status_External------------------------------------------------------------------------------ + env->Status_External_For_Model_output.CoolingFan = statusData.Status_External.CoolingFan; + +//---------------------- Status_EMS----------------------------------------------------------------------------------- + env->Status_EMS_For_Model_output.EMS_Chiller_Req = statusData.Status_EMS.EMS_Chiller_Req; + +//---------------------- Status_Ionizer_Aroma------------------------------------------------------------------------- + env->Status_Ionizer_Aroma_For_Model_output.Ionizer = statusData.Status_Ionizer_Aroma.Ionizer; + env->Status_Ionizer_Aroma_For_Model_output.AromatizationIntensivity = statusData.Status_Ionizer_Aroma.AromatizationIntensivity; + +//---------------------- Status_Duct_Select------------------------------------------------------------------------- + env->Status_Duct_Select_For_Model_output.Duct_FL = statusData.Status_Duct_Select.Duct_FL; + env->Status_Duct_Select_For_Model_output.Duct_FR = statusData.Status_Duct_Select.Duct_FR; + env->Status_Duct_Select_For_Model_output.Duct_RL = statusData.Status_Duct_Select.Duct_RL; + env->Status_Duct_Select_For_Model_output.Duct_RR = statusData.Status_Duct_Select.Duct_RR; + + + osStatus_t status = osOK; + + uint32_t countQueue_space = osMessageQueueGetSpace(env->queue_output_set_Status_Set); + if (countQueue_space) { + status = osMessageQueuePut(env->queue_output_set_Status_Set, &env->Status_Set_For_Model_output, 0, + 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_output_set_Status_Actuator_DoorsActuator); + if (countQueue_space) { + status = osMessageQueuePut(env->queue_output_set_Status_Actuator_DoorsActuator, + &env->Status_Actuator_DoorsActuator_For_Model_output, 0, 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_output_set_Status_Duct_Tgt); + if (countQueue_space) { + status = osMessageQueuePut(env->queue_output_set_Status_Duct_Tgt, &env->Status_Duct_Tgt_For_Model_output, 0, 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_output_set_Status_Eva_Tgt); + if (countQueue_space) { + status = osMessageQueuePut(env->queue_output_set_Status_Eva_Tgt, &env->Status_Eva_Tgt_For_Model_output, 0, 0); + } + + + countQueue_space = osMessageQueueGetSpace(env->queue_output_set_Status_IO); + if (countQueue_space) { + status = osMessageQueuePut(env->queue_output_set_Status_IO, &env->Status_IO_For_Model_output, 0, 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_output_set_Status_Pwm); + if (countQueue_space) { + status = osMessageQueuePut(env->queue_output_set_Status_Pwm, &env->Status_Pwm_For_Model_output, 0, 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_output_set_Status_eComp); + if (countQueue_space) { + status = osMessageQueuePut(env->queue_output_set_Status_eComp, &env->Status_eComp_For_Model_output, 0, 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_output_set_Status_External); + if (countQueue_space) { + status = osMessageQueuePut(env->queue_output_set_Status_External, &env->Status_External_For_Model_output, 0, 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_output_set_Status_EMS); + if (countQueue_space) { + status = osMessageQueuePut(env->queue_output_set_Status_EMS, &env->Status_EMS_For_Model_output, 0, 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_output_set_Status_Ionizer_Aroma); + if (countQueue_space) { + status = osMessageQueuePut(env->queue_output_set_Status_Ionizer_Aroma, + &env->Status_Ionizer_Aroma_For_Model_output, + 0, 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_output_set_Status_Duct_Select); + if (countQueue_space) { + status = osMessageQueuePut(env->queue_output_set_Status_Duct_Select, &env->Status_Duct_Select_For_Model_output, + 0, + 0); + } + +} + + +// Это на вход модели +void CanUdsOutput_Get_Model(tCanUds *env) { + + osStatus_t status = osOK; + + + uint32_t countQueue_space = osMessageQueueGetSpace(env->queue_output_set_Status_Set); + if (countQueue_space == 0) { + status = osMessageQueueGet(env->queue_output_set_Status_Set, &model_Status_Set_For_Model_output, 0, + 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_output_set_Status_Actuator_DoorsActuator); + if (countQueue_space == 0) { + status = osMessageQueueGet(env->queue_output_set_Status_Actuator_DoorsActuator, + &model_Status_Actuator_DoorsActuator_For_Model_output, 0, 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_output_set_Status_Duct_Tgt); + if (countQueue_space == 0) { + status = osMessageQueueGet(env->queue_output_set_Status_Duct_Tgt, &model_Status_Duct_Tgt_For_Model_output, 0, + 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_output_set_Status_Eva_Tgt); + if (countQueue_space == 0) { + status = osMessageQueueGet(env->queue_output_set_Status_Eva_Tgt, &model_Status_Eva_Tgt_For_Model_output, 0, 0); + } + + + countQueue_space = osMessageQueueGetSpace(env->queue_output_set_Status_IO); + if (countQueue_space == 0) { + status = osMessageQueueGet(env->queue_output_set_Status_IO, &model_Status_IO_For_Model_output, 0, 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_output_set_Status_Pwm); + if (countQueue_space == 0) { + status = osMessageQueueGet(env->queue_output_set_Status_Pwm, &model_Status_Pwm_For_Model_output, 0, 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_output_set_Status_eComp); + if (countQueue_space == 0) { + status = osMessageQueueGet(env->queue_output_set_Status_eComp, &model_Status_eComp_For_Model_output, 0, 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_output_set_Status_External); + if (countQueue_space == 0) { + status = osMessageQueueGet(env->queue_output_set_Status_External, &model_Status_External_For_Model_output, 0, + 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_output_set_Status_EMS); + if (countQueue_space == 0) { + status = osMessageQueueGet(env->queue_output_set_Status_EMS, &model_Status_EMS_For_Model_output, 0, 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_output_set_Status_Ionizer_Aroma); + if (countQueue_space == 0) { + status = osMessageQueueGet(env->queue_output_set_Status_Ionizer_Aroma, + &model_Status_Ionizer_Aroma_For_Model_output, + 0, 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_output_set_Status_Duct_Select); + if (countQueue_space == 0) { + status = osMessageQueueGet(env->queue_output_set_Status_Duct_Select, &model_Status_Duct_Select_For_Model_output, + 0, + 0); + } + +} + + + +//конец ---------------------------------------------------------------------------------------------------------------------- +//конец -----------------------------------------------ОЧРЕДИ----------------------------------------------------------------- +//конец ---------------------------------------------------------------------------------------------------------------------- + +static void setDefaultSecurityAccess(tCanUds *env) { + env->SA.requestSequenceRequestSeed = false; + env->SA.stateSecurityAccess = false; + env->SA.counter_max_attempts_default = 0; + env->SA.time_counter_max_attempts_default = 0; +} + +static void setDefaultValue(tCanUds *env) { + +#if (LOG_UDS == 1) + LoggerFormatInfo(LOGGER, LOG_SIGN, "Resetting the session to default: %d", + UDS_session_defaultSession) +#endif + setDefaultSecurityAccess(env); + set_CCU_Mute(env->canSpamTransmitter, false); + set_DBG_CCU_Mute(env->canSpamDebugTransmitter, false); + set_NoBitsDTC(env->Diagnostic, false); + memset(&env->Status_Set_For_Model_output, 0, sizeof(tStatus_Set_For_Model)); +} + + + +static char strPrintfDebug_UDS[80]; + +static void PrintfDebug(uint8_t *data, uint8_t dlc) { + + switch (dlc) { + + case 0: + sprintf(strPrintfDebug_UDS, " "); + break; + case 1: + sprintf(strPrintfDebug_UDS, "%02X", data[0]); + break; + case 2: + sprintf(strPrintfDebug_UDS, "%02X:%02X", data[0], data[1]); + break; + case 3: + sprintf(strPrintfDebug_UDS, "%02X:%02X:%02X", data[0], data[1], data[2]); + break; + case 4: + sprintf(strPrintfDebug_UDS, "%02X:%02X:%02X:%02X", data[0], data[1], data[2], data[3]); + break; + case 5: + sprintf(strPrintfDebug_UDS, "%02X:%02X:%02X:%02X:%02X", data[0], data[1], data[2], data[3], + data[4]); + break; + case 6: + sprintf(strPrintfDebug_UDS, "%02X:%02X:%02X:%02X:%02X:%02X", data[0], data[1], data[2], data[3], + data[4], data[5]); + break; + case 7: + sprintf(strPrintfDebug_UDS, "%02X:%02X:%02X:%02X:%02X:%02X:%02X", data[0], data[1], data[2], + data[3], data[4], + data[5], data[6]); + break; + case 8: + sprintf(strPrintfDebug_UDS, "%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X ", data[0], data[1], + data[2], data[3], data[4], + data[5], data[6], data[7]); + break; + default: + sprintf(strPrintfDebug_UDS, " "); + } + +} + +// Проверка валидности BCD +static bool is_valid_bcd(uint8_t value) { + return ((value & 0x0F) <= 9) && ((value >> 4) <= 9); +} + +// Проверка года +static bool is_valid_year(uint8_t year) { + return is_valid_bcd(year); // 0x00-0x99 +} + +// Проверка месяца +static bool is_valid_month(uint8_t month) { + if (!is_valid_bcd(month)) return false; + uint8_t m = ((month >> 4) * 10) + (month & 0x0F); + return (m >= 1 && m <= 12); +} + +// Проверка дня (с учетом месяца и года) +static bool is_valid_day(uint8_t year, uint8_t month, uint8_t day) { + if (!is_valid_bcd(day)) return false; + + uint8_t y = ((year >> 4) * 10) + (year & 0x0F); + uint8_t m = ((month >> 4) * 10) + (month & 0x0F); + uint8_t d = ((day >> 4) * 10) + (day & 0x0F); + + if (d < 1) return false; + + // Дни в месяцах + uint8_t days_in_month[] = {31, 28, 31, 30, 31, 30, + 31, 31, 30, 31, 30, 31}; + + // Проверка на високосный год + if (m == 2) { + bool is_leap = (y % 4 == 0 && y % 100 != 0) || (y % 400 == 0); + return d <= (is_leap ? 29 : 28); + } + + return d <= days_in_month[m - 1]; +} + +static bool isSecurityAccessDenied(tCanUds *env, tPermissionSession isPermissionSession) { + bool result = false; + + switch (isPermissionSession) { + + case perm_session_defaultSession: { + if (env->currentSession == UDS_session_defaultSession) + result = true; + break; + } + + case perm_session_programmingSession: { + if (env->currentSession == UDS_session_programmingSession) + result = true; + break; + } + + case perm_session_extendedDiagnosticSession: { + if (env->currentSession == UDS_session_extendedDiagnosticSession) + result = true; + break; + } + + case perm_session_defaultSession_programmingSession: { + if ((env->currentSession == UDS_session_defaultSession) || + (env->currentSession == UDS_session_programmingSession)) + result = true; + break; + } + + case perm_session_defaultSession_extendedDiagnosticSession: { + if ((env->currentSession == UDS_session_defaultSession) || + (env->currentSession == UDS_session_extendedDiagnosticSession)) + result = true; + break; + } + + case perm_session_extendedDiagnosticSession_programmingSession: { + if ((env->currentSession == UDS_session_extendedDiagnosticSession) || + (env->currentSession == UDS_session_programmingSession)) + result = true; + break; + } + + case perm_session_all: { + result = true; + break; + } + + default: + break; + } + + return result; +} + +char *sendLogCanUdsHex(tCanUds *env, uint8_t *data, size_t size) { + memset(env->hexString, 0, sizeof(env->hexString)); + size_t len = 0; + + + uint8_t full = size / 8; + uint8_t tail = size % 8; + + for (uint8_t i = 0; i < full; ++i) { + PrintfDebug(&data[i * 8], 8); + + if ((len + strlen(strPrintfDebug_UDS)) < LEN_DEBUG_TP_BUFF) { + memcpy(&env->hexString[len], strPrintfDebug_UDS, strlen(strPrintfDebug_UDS)); + len += strlen(strPrintfDebug_UDS); + } else { + return env->hexString; + } + + } + + if (tail > 0) { + PrintfDebug(&data[full * 8], tail); + + if ((len + strlen(strPrintfDebug_UDS)) < LEN_DEBUG_TP_BUFF) { + memcpy(&env->hexString[len], strPrintfDebug_UDS, strlen(strPrintfDebug_UDS)); + len += strlen(strPrintfDebug_UDS); + } else { + return env->hexString; + } + + } + + return env->hexString; +} + +bool ReceivedCan_func(void *arg, can_rx_message_type *canFrame) { + tCanUds *env = arg; + + + return false; +} + + +void setResponseErrorPending(tCanUds *env, eUdsServices service, eUdsResponseError error) { + env->dataResponsePending[0] = 0x7F; + env->dataResponsePending[1] = service; + env->dataResponsePending[2] = error; + + CanSerialPortFrameTpTransmit(&env->canSerialPortFrameTp, env->dataResponsePending, + 3, PROTOCOL_CAN_ADR_UDS, WAIT_FRAME_WRITE); +} + +void SendUpdatePendingCrc(void *env) { + setResponseErrorPending(env, UDS_RoutineControl, UDS_error_requestCorrectlyReceived_ResponsePending); +} + +void SendUpdatePendingFlashClear(void *env) { + + tCanUds *envUds = env; + + if (SystemGetMs() > envUds->timeoutPendingClear) { + setResponseErrorPending(env, UDS_RoutineControl, UDS_error_requestCorrectlyReceived_ResponsePending); + envUds->timeoutPendingClear = SystemGetMs() + 200; + } + +} + + +uint16_t setResponseError(tCanUds *env, eUdsServices service, eUdsResponseError error) { + env->dataResponse[0] = 0x7F; + env->dataResponse[1] = service; + env->dataResponse[2] = error; + + return 3; +} + +// начало --------------------------- ПИНГ --------------------------------------------------------- +// начало --------------------------- ПИНГ --------------------------------------------------------- +// начало --------------------------- ПИНГ --------------------------------------------------------- + +static uint16_t TesterPresent_3E(tCanUds *env) { + + tUdsServiceCommand *com = (tUdsServiceCommand *) env->data->data; + + if (env->data->len < 2) { + return setResponseError(env, UDS_TesterPresent, UDS_error_incorrectMessageLengthOrInvalidFormat); + } + + tTesterPresent *testerPresent = (tTesterPresent *) env->dataResponse; + testerPresent->ServiceId = UDS_TesterPresent | 0b1000000; + testerPresent->zeroSubFunction = 0; + +// if (osMutexAcquire(env->access, 1000) == osOK) { +// env->currentSessionTesterPresentTimeout = SystemGetMs() + timeout_session_S3_Server; +// osMutexRelease(env->access); +// } else { +// LoggerErrorStatic(LOGGER, LOG_SIGN, "Access error TesterPresent_3E"); +// } + + return 2; +} +// конец --------------------------- ПИНГ --------------------------------------------------------- +// конец --------------------------- ПИНГ --------------------------------------------------------- +// конец --------------------------- ПИНГ --------------------------------------------------------- + +// начало ----------------------------- Сессия ------------------------------------------------------------- +// начало ----------------------------- Сессия ------------------------------------------------------------- +// начало ----------------------------- Сессия ------------------------------------------------------------- +static uint16_t DiagnosticSessionControl_10(tCanUds *env) { + tUdsServiceCommand *com = (tUdsServiceCommand *) env->data->data; + + if (env->data->len < 2) { + return setResponseError(env, UDS_DiagnosticSessionControl, UDS_error_incorrectMessageLengthOrInvalidFormat); + } + + if ((com->sub_function != UDS_session_defaultSession) && + (com->sub_function != UDS_session_programmingSession) && + (com->sub_function != UDS_session_extendedDiagnosticSession)) { + return setResponseError(env, UDS_DiagnosticSessionControl, UDS_error_sub_functionNotSupported); + } + +// if ((env->currentSession == UDS_session_programmingSession) && +// (com->sub_function == UDS_session_extendedDiagnosticSession)) { +// return setResponseError(env, UDS_DiagnosticSessionControl, UDS_error_conditionsNotCorrect); +// } + + + if (env->currentSession != com->sub_function) { + + env->currentSession = com->sub_function; + + //setDefaultSecurityAccess(env); + setDefaultValue(env); + statusData.Status_Active_Diagnostic_Session.Active_Diagnostic_Session = env->currentSession; + } + + tDiagnosticSessionsType *diagnosticSessionsType = (tDiagnosticSessionsType *) env->dataResponse; + diagnosticSessionsType->ServiceId = UDS_DiagnosticSessionControl | 0b1000000; + diagnosticSessionsType->diagnosticSessionType = env->data->data[1]; + + // Нормальный таймаут. Важно: Клиент может отправлять TesterPresent для поддержания сессии + // 50 мс + diagnosticSessionsType->P2 = 50; + + // Расширенный таймаут. Например, ECU может обрабатывать сложный запрос 2 секунды и отправлять NRC 0x78, затем ответ + // 500 мс + diagnosticSessionsType->P2Ex = 500; + + return 6; +} +// конец ----------------------------- Сессия -------------------------------------------------------------- +// конец ----------------------------- Сессия -------------------------------------------------------------- +// конец ----------------------------- Сессия -------------------------------------------------------------- + + +// начало --------------------------- Чтение --------------------------------------------------------- +// начало --------------------------- Чтение --------------------------------------------------------- +// начало --------------------------- Чтение --------------------------------------------------------- +static uint16_t ReadDataByIdentifier_22(tCanUds *env) { + + if (env->data->len < 3) { + return setResponseError(env, UDS_ReadDataByIdentifier, UDS_error_incorrectMessageLengthOrInvalidFormat); + } + + uint8_t dataIdentifier_hi = env->data->data[1]; + uint8_t dataIdentifier_lo = env->data->data[2]; +// uint16_t dataIdentifier = (dataIdentifier_hi << 8) | dataIdentifier_lo; + + if (dataIdentifier_hi == 0xCF) { + + if (uds_ReadDataByIdentifier_22_com_CF[dataIdentifier_lo].data != NULL) { + + + if (!isSecurityAccessDenied(env, + uds_ReadDataByIdentifier_22_com_CF[dataIdentifier_lo].isPermissionSession)) { + return setResponseError(env, UDS_ReadDataByIdentifier, UDS_error_conditionsNotCorrect); + } + + if ((uds_ReadDataByIdentifier_22_com_CF[dataIdentifier_lo].isSecurity) && (!env->SA.stateSecurityAccess)) { + return setResponseError(env, UDS_ReadDataByIdentifier, UDS_error_securityAccessDenied); + } + + + uint16_t response_size = uds_ReadDataByIdentifier_22_com_CF[dataIdentifier_lo].size; + + env->dataResponse[0] = UDS_ReadDataByIdentifier | 0b1000000; + env->dataResponse[1] = dataIdentifier_hi; + env->dataResponse[2] = dataIdentifier_lo; + memcpy(&env->dataResponse[3], uds_ReadDataByIdentifier_22_com_CF[dataIdentifier_lo].data, response_size); + + return response_size + 3; + + } + + } + + if (dataIdentifier_hi == 0xF1) { + + if (uds_ReadDataByIdentifier_22_com_F1[dataIdentifier_lo].data != NULL) { + + if (!isSecurityAccessDenied(env, + uds_ReadDataByIdentifier_22_com_F1[dataIdentifier_lo].isPermissionSession)) { + return setResponseError(env, UDS_ReadDataByIdentifier, UDS_error_conditionsNotCorrect); + } + + if ((uds_ReadDataByIdentifier_22_com_F1[dataIdentifier_lo].isSecurity) && (!env->SA.stateSecurityAccess)) { + return setResponseError(env, UDS_ReadDataByIdentifier, UDS_error_securityAccessDenied); + } + + uint16_t response_size = uds_ReadDataByIdentifier_22_com_F1[dataIdentifier_lo].size; + + env->dataResponse[0] = UDS_ReadDataByIdentifier | 0b1000000; + env->dataResponse[1] = dataIdentifier_hi; + env->dataResponse[2] = dataIdentifier_lo; + memcpy(&env->dataResponse[3], uds_ReadDataByIdentifier_22_com_F1[dataIdentifier_lo].data, response_size); + + return response_size + 3; + } + + } + + return setResponseError(env, UDS_ReadDataByIdentifier, UDS_error_requestOutOfRange); +} +// конец --------------------------- Чтение --------------------------------------------------------- +// конец --------------------------- Чтение --------------------------------------------------------- +// конец --------------------------- Чтение --------------------------------------------------------- + +// начало --------------------------- Запись --------------------------------------------------------- +// начало --------------------------- Запись --------------------------------------------------------- +// начало --------------------------- Запись --------------------------------------------------------- + +static uint16_t WriteDataByIdentifier_2E(tCanUds *env) { + + if (env->data->len < 3) { + return setResponseError(env, UDS_WriteDataByIdentifier, UDS_error_incorrectMessageLengthOrInvalidFormat); + } + + uint8_t dataIdentifier_hi = env->data->data[1]; + uint8_t dataIdentifier_lo = env->data->data[2]; +// uint16_t dataIdentifier = (dataIdentifier_hi << 8) | dataIdentifier_lo; + + if (dataIdentifier_hi == 0xCF) { + + if (uds_WriteDataByIdentifier_2E_com_CF[dataIdentifier_lo].data != NULL) { + + + if (!isSecurityAccessDenied(env, + uds_WriteDataByIdentifier_2E_com_CF[dataIdentifier_lo].isPermissionSession)) { + return setResponseError(env, UDS_WriteDataByIdentifier, UDS_error_conditionsNotCorrect); + } + + if ((uds_WriteDataByIdentifier_2E_com_CF[dataIdentifier_lo].isSecurity) && (!env->SA.stateSecurityAccess)) { + return setResponseError(env, UDS_WriteDataByIdentifier, UDS_error_securityAccessDenied); + } + + + uint16_t size = uds_WriteDataByIdentifier_2E_com_CF[dataIdentifier_lo].size; + + if (env->data->len != size + 3) { + return setResponseError(env, UDS_WriteDataByIdentifier, + UDS_error_incorrectMessageLengthOrInvalidFormat); + } + + env->dataResponse[0] = UDS_WriteDataByIdentifier | 0b1000000; + env->dataResponse[1] = dataIdentifier_hi; + env->dataResponse[2] = dataIdentifier_lo; + + // CCU_Configuration + if (dataIdentifier_lo == 0) { + tStatus_CCU_Configuration *CCU_Configuration = (tStatus_CCU_Configuration *) &env->data->data[3]; + if ((CCU_Configuration->AromaConfiguration > 1) || (CCU_Configuration->AlgorithmConfiguration > 1) || + (CCU_Configuration->RearHVACConfiguration > 1)) { + return setResponseError(env, UDS_WriteDataByIdentifier, + UDS_error_requestOutOfRange); + } + } else { + return setResponseError(env, UDS_WriteDataByIdentifier, UDS_error_requestOutOfRange); + } + + memcpy(uds_WriteDataByIdentifier_2E_com_CF[dataIdentifier_lo].data, &env->data->data[3], size); + + setResponseErrorPending(env, UDS_WriteDataByIdentifier, UDS_error_requestCorrectlyReceived_ResponsePending); + SaveToStorageFromStatusData(env->deviceStorage, &statusData.ecu); + return 3; + } + + } + + if (dataIdentifier_hi == 0xF1) { + + if (uds_WriteDataByIdentifier_2E_com_F1[dataIdentifier_lo].data != NULL) { + + if (!isSecurityAccessDenied(env, + uds_WriteDataByIdentifier_2E_com_F1[dataIdentifier_lo].isPermissionSession)) { + return setResponseError(env, UDS_WriteDataByIdentifier, UDS_error_conditionsNotCorrect); + } + + if ((uds_WriteDataByIdentifier_2E_com_F1[dataIdentifier_lo].isSecurity) && (!env->SA.stateSecurityAccess)) { + return setResponseError(env, UDS_WriteDataByIdentifier, UDS_error_securityAccessDenied); + } + + + uint16_t size = uds_WriteDataByIdentifier_2E_com_F1[dataIdentifier_lo].size; + + if (env->data->len != size + 3) { + return setResponseError(env, UDS_WriteDataByIdentifier, + UDS_error_incorrectMessageLengthOrInvalidFormat); + } + + env->dataResponse[0] = UDS_WriteDataByIdentifier | 0b1000000; + env->dataResponse[1] = dataIdentifier_hi; + env->dataResponse[2] = dataIdentifier_lo; + + + // Tester_Fingerprint + if (dataIdentifier_lo == 0x5A) { + tFingerprint *fingerprint = (tFingerprint *) &env->data->data[3]; + if (is_valid_day(fingerprint->year, fingerprint->month, fingerprint->day) == false) { + return setResponseError(env, UDS_WriteDataByIdentifier, + UDS_error_requestOutOfRange); + } + } else if (dataIdentifier_lo == 0x8C) { + + } else { + return setResponseError(env, UDS_WriteDataByIdentifier, UDS_error_requestOutOfRange); + } + + + memcpy(uds_WriteDataByIdentifier_2E_com_F1[dataIdentifier_lo].data, &env->data->data[3], size); + + setResponseErrorPending(env, UDS_WriteDataByIdentifier, UDS_error_requestCorrectlyReceived_ResponsePending); + SaveToStorageFromStatusData(env->deviceStorage, &statusData.ecu); + return 3; + } + + } + + return setResponseError(env, UDS_WriteDataByIdentifier, UDS_error_requestOutOfRange); + +} +// конец --------------------------- Запись --------------------------------------------------------- +// конец --------------------------- Запись --------------------------------------------------------- +// конец --------------------------- Запись --------------------------------------------------------- + + + +// начало --------------------------- Управление --------------------------------------------------------- +// начало --------------------------- Управление --------------------------------------------------------- +// начало --------------------------- Управление --------------------------------------------------------- +static void GetUpdateQueueIO(tCanUds *env) { + + setResponseErrorPending(env, UDS_InputOutputControlByIdentifier, UDS_error_requestCorrectlyReceived_ResponsePending); + + for (uint8_t i = 0; i < 15; ++i) { + CanUdsOutput_Set_Model(env); + CanUdsInput_Get_Model(env); + SystemDelayMs(10); + } + + +} + + +static uint16_t InputOutputControlByIdentifier_2F(tCanUds *env) { + + if (env->data->len < 4) { + return setResponseError(env, UDS_InputOutputControlByIdentifier, + UDS_error_incorrectMessageLengthOrInvalidFormat); + } + + uint8_t dataIdentifier_hi = env->data->data[1]; + uint8_t dataIdentifier_lo = env->data->data[2]; +// uint16_t dataIdentifier = (dataIdentifier_hi << 8) | dataIdentifier_lo; + + if ((env->data->data[3] != UDS_io_returnControlToECU) && + (env->data->data[3] != UDS_io_shortTermAdjustment)) { + return setResponseError(env, UDS_InputOutputControlByIdentifier, UDS_error_sub_functionNotSupported); + } + + if (dataIdentifier_hi == 0xCF) { + + if (uds_IoDataByIdentifier_2F_com_CF[dataIdentifier_lo].data != NULL) { + + if (!isSecurityAccessDenied(env, uds_IoDataByIdentifier_2F_com_CF[dataIdentifier_lo].isPermissionSession)) { + return setResponseError(env, UDS_InputOutputControlByIdentifier, UDS_error_conditionsNotCorrect); + } + + if ((uds_IoDataByIdentifier_2F_com_CF[dataIdentifier_lo].isSecurity) && (!env->SA.stateSecurityAccess)) { + return setResponseError(env, UDS_InputOutputControlByIdentifier, UDS_error_securityAccessDenied); + } + + uint16_t size = uds_IoDataByIdentifier_2F_com_CF[dataIdentifier_lo].size; + + if ((env->data->data[3] == UDS_io_shortTermAdjustment) && (env->data->len != size + 4)) { + return setResponseError(env, UDS_InputOutputControlByIdentifier, + UDS_error_incorrectMessageLengthOrInvalidFormat); + } + + env->dataResponse[0] = UDS_InputOutputControlByIdentifier | 0b1000000; + env->dataResponse[1] = dataIdentifier_hi; + env->dataResponse[2] = dataIdentifier_lo; + env->dataResponse[3] = env->data->data[3]; + + if (env->data->data[3] == UDS_io_shortTermAdjustment) { +// memcpy(&env->dataResponse[4], &env->data->data[4], size); + +// if (dataIdentifier_lo == 0x50) { +// memcpy(&env->dataResponse[4], uds_ReadDataByIdentifier_22_com_CF[2].data, size); +// } else { +// memcpy(&env->dataResponse[4], uds_ReadDataByIdentifier_22_com_CF[dataIdentifier_lo].data, size); +// } + + // Motor_Def...MotorSealingValve (percent) + if ((dataIdentifier_lo >= 0x60) && (dataIdentifier_lo <= 0x78)) { + uint16_t percent = (env->data->data[4] << 8) | env->data->data[5]; + + if (percent > 1000) { + return setResponseError(env, UDS_InputOutputControlByIdentifier, UDS_error_requestOutOfRange); + } + + uint8_t *pSet = (uint8_t * ) & env->Status_Set_For_Model_output; + + pSet[dataIdentifier_lo - 0x60] = 1; + + memcpy(uds_IoDataByIdentifier_2F_com_CF[dataIdentifier_lo].data, &env->data->data[4], size); + + GetUpdateQueueIO(env); + memcpy(&env->dataResponse[4], uds_ReadDataByIdentifier_22_com_CF[dataIdentifier_lo].data, size); + + return size + 4; + } else { + + switch (dataIdentifier_lo) { + + // Doors Actuator + case 0x50: { + + for (uint8_t i = 0; i < 24; i += 2) { + uint16_t percent = (env->data->data[4 + i] << 8) | env->data->data[5 + 1 + i]; + if (percent > 1000) { + return setResponseError(env, UDS_InputOutputControlByIdentifier, + UDS_error_requestOutOfRange); + } + } + + memset(&env->Status_Set_For_Model_output, 1, 24); + + break; + } + + // IO + case 0x51: { + for (uint8_t i = 0; i < 8; ++i) { + uint8_t on_off = env->data->data[4 + i]; + if (on_off > 1) { + return setResponseError(env, UDS_InputOutputControlByIdentifier, + UDS_error_requestOutOfRange); + } + } + + env->Status_Set_For_Model_output.IO = 1; + + break; + } + + // PWM + case 0x52: { + + tStatus_Pwm *pwm = (tStatus_Pwm *) &env->data->data[4]; + if ((pwm->Pwm_Front > 1000) || (pwm->Pwm_Rear > 1000)) { + return setResponseError(env, UDS_InputOutputControlByIdentifier, + UDS_error_requestOutOfRange); + } + + env->Status_Set_For_Model_output.Pwm = 1; + + break; + } + + // eComp + case 0x53: { + + tStatus_eComp *eComp = (tStatus_eComp *) &env->data->data[4]; + if ((eComp->eComp_Statue_Request > 1) || (eComp->LowTempValve > 1) || + ((eComp->Pwm_Front * 50) > 8500)) { + return setResponseError(env, UDS_InputOutputControlByIdentifier, + UDS_error_requestOutOfRange); + } + + + env->Status_Set_For_Model_output.eComp = 1; + + break; + } + + // External + case 0x54: { + + tStatus_External *external = (tStatus_External *) &env->data->data[4]; + if (external->CoolingFan > 1000) { + return setResponseError(env, UDS_InputOutputControlByIdentifier, + UDS_error_requestOutOfRange); + } + + env->Status_Set_For_Model_output.External = 1; + + break; + } + + // EMS + case 0x55: { + + tStatus_EMS *ems = (tStatus_EMS *) &env->data->data[4]; + if (ems->EMS_Chiller_Req > 1) { + return setResponseError(env, UDS_InputOutputControlByIdentifier, + UDS_error_requestOutOfRange); + } + + env->Status_Set_For_Model_output.EMS = 1; + + break; + } + + // Ionizer_Aroma + case 0x56: { + + tStatus_Ionizer_Aroma *ionizer_Aroma = (tStatus_Ionizer_Aroma *) &env->data->data[4]; + if ((ionizer_Aroma->Ionizer > 1) || (ionizer_Aroma->AromatizationIntensivity > 3)) { + return setResponseError(env, UDS_InputOutputControlByIdentifier, + UDS_error_requestOutOfRange); + } + + env->Status_Set_For_Model_output.Ionizer_Aroma = 1; + + break; + } + + // Duct Select + case 0x79: { + + tStatus_Duct_Select *duct_Select = (tStatus_Duct_Select *) &env->data->data[4]; + if ((duct_Select->Duct_FL > 1) || (duct_Select->Duct_FR > 1) || + (duct_Select->Duct_RL > 1) || (duct_Select->Duct_RR > 1)) { + return setResponseError(env, UDS_InputOutputControlByIdentifier, + UDS_error_requestOutOfRange); + } + + env->Status_Set_For_Model_output.Duct_Select = 1; + + break; + } + + } + + } + + memcpy(uds_IoDataByIdentifier_2F_com_CF[dataIdentifier_lo].data, &env->data->data[4], size); + + GetUpdateQueueIO(env); + memcpy(&env->dataResponse[4], uds_ReadDataByIdentifier_22_com_CF[dataIdentifier_lo].data, size); + + return size + 4; + + } else { // ВОЗВРАТ УПРАВЛЕНИЯ + + // if (dataIdentifier_lo == 0x50) { + // memcpy(&env->dataResponse[4], uds_ReadDataByIdentifier_22_com_CF[2].data, size); + // } else { + // memcpy(&env->dataResponse[4], uds_ReadDataByIdentifier_22_com_CF[dataIdentifier_lo].data, size); + // } + + // Motor_Def...MotorSealingValve (percent) + if ((dataIdentifier_lo >= 0x60) && (dataIdentifier_lo <= 0x78)) { + + uint8_t *pSet = (uint8_t * ) & env->Status_Set_For_Model_output; + pSet[dataIdentifier_lo - 0x60] = 0; + + GetUpdateQueueIO(env); + memcpy(&env->dataResponse[4], uds_ReadDataByIdentifier_22_com_CF[dataIdentifier_lo].data, size); + + return size + 4; + + } else { + + switch (dataIdentifier_lo) { + + // Doors Actuator + case 0x50: { + memset(&env->Status_Set_For_Model_output, 0, 24); + break; + } + + // IO + case 0x51: { + env->Status_Set_For_Model_output.IO = 0; + break; + } + + // PWM + case 0x52: { + env->Status_Set_For_Model_output.Pwm = 0; + break; + } + + // eComp + case 0x53: { + env->Status_Set_For_Model_output.eComp = 0; + break; + } + + // External + case 0x54: { + env->Status_Set_For_Model_output.External = 0; + break; + } + + // EMS + case 0x55: { + env->Status_Set_For_Model_output.EMS = 0; + break; + } + + // Ionizer_Aroma + case 0x56: { + env->Status_Set_For_Model_output.Ionizer_Aroma = 0; + break; + } + + // Duct Select + case 0x79: { + env->Status_Set_For_Model_output.Duct_Select = 0; + break; + } + + } + + } + + GetUpdateQueueIO(env); + memcpy(&env->dataResponse[4], uds_ReadDataByIdentifier_22_com_CF[dataIdentifier_lo].data, size); + + return size + 4; + } + + + return setResponseError(env, UDS_InputOutputControlByIdentifier, UDS_error_requestOutOfRange); + //return 4; + } + + } + + return setResponseError(env, UDS_InputOutputControlByIdentifier, UDS_error_requestOutOfRange); +} +// конец --------------------------- Управление --------------------------------------------------------- +// конец --------------------------- Управление --------------------------------------------------------- +// конец --------------------------- Управление --------------------------------------------------------- + + +// начало --------------------------- Перезагрузка --------------------------------------------------------- +// начало --------------------------- Перезагрузка --------------------------------------------------------- +// начало --------------------------- Перезагрузка --------------------------------------------------------- + +static uint16_t ECUReset_11(tCanUds *env) { + tUdsServiceCommand *com = (tUdsServiceCommand *) env->data->data; + + if (env->data->len < 2) { + return setResponseError(env, UDS_ECUResetService, + UDS_error_incorrectMessageLengthOrInvalidFormat); + } + + if ((com->sub_function != UDS_reset_hardReset) && + (com->sub_function != UDS_reset_softReset) && + (com->sub_function != UDS_reset_rapidReset)) { + return setResponseError(env, UDS_ECUResetService, UDS_error_sub_functionNotSupported); + } + + if ((env->currentSession == UDS_session_programmingSession) && + ((com->sub_function == UDS_reset_softReset) || (com->sub_function == UDS_reset_rapidReset))) { + return setResponseError(env, UDS_ECUResetService, UDS_error_conditionsNotCorrect); + } + + env->isEcuReset = true; + + env->dataResponse[0] = UDS_ECUResetService | 0b1000000;; + env->dataResponse[1] = env->data->data[1] & 0b01111111; // sub-function + + return 2; +} +// конец --------------------------- Перезагрузка --------------------------------------------------------- +// конец --------------------------- Перезагрузка --------------------------------------------------------- +// конец --------------------------- Перезагрузка --------------------------------------------------------- + + +// начало --------------------------- Очистка ошибок --------------------------------------------------------- +// начало --------------------------- Очистка ошибок --------------------------------------------------------- +// начало --------------------------- Очистка ошибок --------------------------------------------------------- + +static uint16_t UDS_ClearDiagnosticInformation_14(tCanUds *env) { + + if (env->data->len < 4) { + return setResponseError(env, UDS_ClearDiagnosticInformation, + UDS_error_incorrectMessageLengthOrInvalidFormat); + } + + if (env->currentSession == UDS_session_programmingSession) { + return setResponseError(env, UDS_ClearDiagnosticInformation, UDS_error_conditionsNotCorrect); + } + + diagnostic_ClearDiagnosticInformation_14(env->Diagnostic); + + env->dataResponse[0] = UDS_ClearDiagnosticInformation | 0b1000000; + + return 1; +} +// конец --------------------------- Очистка ошибок --------------------------------------------------------- +// конец --------------------------- Очистка ошибок --------------------------------------------------------- +// конец --------------------------- Очистка ошибок --------------------------------------------------------- + +// начало --------------------------- Чтение ошибок --------------------------------------------------------- +// начало --------------------------- Чтение ошибок --------------------------------------------------------- +// начало --------------------------- Чтение ошибок --------------------------------------------------------- + +static uint16_t UDS_ReadDTCInformation_19(tCanUds *env) { + + tUdsServiceCommand *com = (tUdsServiceCommand *) env->data->data; + + if (env->data->len < 3) { + return setResponseError(env, UDS_ReadDTCInformation, UDS_error_incorrectMessageLengthOrInvalidFormat); + } + + if ((com->sub_function != UDS_dtc_reportNumberOfDTCByStatusMask) && + (com->sub_function != UDS_dtc_reportDTCByStatusMask) && + (com->sub_function != UDS_dtc_reportDTCBySupport)) { + return setResponseError(env, UDS_ReadDTCInformation, UDS_error_sub_functionNotSupported); + } + + if (env->currentSession == UDS_session_programmingSession) { + return setResponseError(env, UDS_ReadDTCInformation, UDS_error_conditionsNotCorrect); + } + + uint16_t response_size = 0; + + env->dataResponse[0] = UDS_ReadDTCInformation | 0b1000000; + + if (com->sub_function == UDS_dtc_reportNumberOfDTCByStatusMask) { + + env->dataResponse[1] = env->data->data[1] & 0b01111111; // sub-function + + // доступные биты статусов + env->dataResponse[2] = 0x09; + // формат кодирования DTC + env->dataResponse[3] = 0; + // старший байт количества DTC + env->dataResponse[4] = 0; + + tDiagnosticDTC diagnosticDTC = {env->data->data[2], NULL}; + // младший байт количества DTC + env->dataResponse[5] = diagnostic_UDS_ReadDTCInformation_19_count(env->Diagnostic, &diagnosticDTC); + + response_size = 6; + } + + if (com->sub_function == UDS_dtc_reportDTCByStatusMask) { + + env->dataResponse[1] = env->data->data[1] & 0b01111111; // sub-function + + // доступные биты статусов + env->dataResponse[2] = 0x09; + + response_size = 3; + + tDiagnosticDTC diagnosticDTC = {env->data->data[2], &env->dataResponse[response_size]}; + response_size += diagnostic_UDS_ReadDTCInformation_19_dtc(env->Diagnostic, &diagnosticDTC); + + } + + if (com->sub_function == UDS_dtc_reportDTCBySupport) { + + env->dataResponse[1] = env->data->data[1] & 0b01111111; // sub-function + + // доступные биты статусов + env->dataResponse[2] = 0x09; + + response_size = 3; + + tDiagnosticDTC diagnosticDTC = {env->data->data[2], &env->dataResponse[response_size]}; + response_size += diagnostic_UDS_ReadDTCSupportDTC_19_dtc(env->Diagnostic, &diagnosticDTC); + } + + return response_size; +} +// конец --------------------------- Чтение ошибок --------------------------------------------------------- +// конец --------------------------- Чтение ошибок --------------------------------------------------------- +// конец --------------------------- Чтение ошибок --------------------------------------------------------- + +// начало --------------------------- Молчание ------------------------------------------------------------- +// начало --------------------------- Молчание ------------------------------------------------------------- +// начало --------------------------- Молчание ------------------------------------------------------------- + +static uint16_t CommunicationControl_28(tCanUds *env) { + + tUdsServiceCommand *com = (tUdsServiceCommand *) env->data->data; + + if (env->data->len < 3) { + return setResponseError(env, UDS_Communication_Control, + UDS_error_incorrectMessageLengthOrInvalidFormat); + } + + if ((com->sub_function != UDS_sub_enableRxAndTx) && + (com->sub_function != UDS_sub_enableRxAndDisableTx)) { + return setResponseError(env, UDS_Communication_Control, UDS_error_sub_functionNotSupported); + } + + + if ((env->currentSession == UDS_session_defaultSession) || + (env->currentSession == UDS_session_programmingSession)) { + return setResponseError(env, UDS_Communication_Control, UDS_error_conditionsNotCorrect); + } + + + if (com->sub_function == UDS_sub_enableRxAndTx) { + set_CCU_Mute(env->canSpamTransmitter, false); + set_DBG_CCU_Mute(env->canSpamDebugTransmitter, false); + + } else { + set_CCU_Mute(env->canSpamTransmitter, true); + set_DBG_CCU_Mute(env->canSpamDebugTransmitter, true); + } + + env->dataResponse[0] = UDS_Communication_Control | 0b1000000; + env->dataResponse[1] = env->data->data[1] & 0b01111111; // sub-function + + return 2; +} +// конец --------------------------- Молчание ------------------------------------------------------------- +// конец --------------------------- Молчание ------------------------------------------------------------- +// конец --------------------------- Молчание ------------------------------------------------------------- + + + +// начало --------------------------- Заморозка изменения DTC ------------------------------------------------------------- +// начало --------------------------- Заморозка изменения DTC ------------------------------------------------------------- +// начало --------------------------- Заморозка изменения DTC ------------------------------------------------------------- + +static uint16_t ControlDTCSetting_85(tCanUds *env) { + + tUdsServiceCommand *com = (tUdsServiceCommand *) env->data->data; + + if (env->data->len < 2) { + return setResponseError(env, UDS_ControlDTCSetting, + UDS_error_incorrectMessageLengthOrInvalidFormat); + } + + if ((com->sub_function != UDS_sub_dtc_on) && + (com->sub_function != UDS_sub_dtc_off)) { + return setResponseError(env, UDS_ControlDTCSetting, UDS_error_sub_functionNotSupported); + } + + if ((env->currentSession == UDS_session_defaultSession) || + (env->currentSession == UDS_session_programmingSession)) { + return setResponseError(env, UDS_ControlDTCSetting, UDS_error_conditionsNotCorrect); + } + + if (com->sub_function == UDS_sub_dtc_on) { + set_NoBitsDTC(env->Diagnostic, false); + } else { + set_NoBitsDTC(env->Diagnostic, true); // off - заморожены + } + + env->dataResponse[0] = UDS_ControlDTCSetting | 0b1000000; + env->dataResponse[1] = env->data->data[1] & 0b01111111; // sub-function + + return 2; +} +// конец --------------------------- Заморозка изменения DTC ------------------------------------------------------------- +// конец --------------------------- Заморозка изменения DTC ------------------------------------------------------------- +// конец --------------------------- Заморозка изменения DTC ------------------------------------------------------------- + + +// начало --------------------------- Функции ------------------------------------------------------------- +// начало --------------------------- Функции ------------------------------------------------------------- +// начало --------------------------- Функции ------------------------------------------------------------- + +static uint16_t vUDS_check_Programming_Preconditions(tCanUds *env, eUdsRoutineControlType udsRoutineControlType) { + + if (udsRoutineControlType != UDS_routine_StartRoutine) { + return 0xFF00 | UDS_error_sub_functionNotSupported; + } + +// env->udsFirmwareStepsMain = UDS_Firmware_Step_Preconditions; +// env->udsFirmwareStepsCalib = UDS_Firmware_Step_Preconditions; + + env->dataResponse[4] = UDS_routine_RoutineStartStopSuccess; + return 4 + 1; + +} + +static uint16_t vUDS_routine_VIN_learn(tCanUds *env, eUdsRoutineControlType udsRoutineControlType) { + + if (udsRoutineControlType != UDS_routine_StartRoutine) { + return 0xFF00 | UDS_error_sub_functionNotSupported; + } + + env->dataResponse[4] = UDS_routine_RoutineStartStopSuccess; + + return 4 + 1; +} + + +static uint16_t vUDS_routine_Compare_Checksum(tCanUds *env, eUdsRoutineControlType udsRoutineControlType) { + + if (udsRoutineControlType != UDS_routine_StartRoutine) { + return 0xFF00 | UDS_error_sub_functionNotSupported; + } + + if (env->data->len != 8) { + return 0xFF00 | UDS_error_incorrectMessageLengthOrInvalidFormat; + } + + setResponseErrorPending(env, UDS_RoutineControl, UDS_error_requestCorrectlyReceived_ResponsePending); + + uint32_t crc32_calc = UdsCrc32Update_Hardware(0xFFFFFFFF, (uint8_t *) env->CurrentBlockAdr, env->CurrentBlockSize, + SendUpdatePendingCrc, env, 200); + + uint32_t crc32_received = + (env->data->data[4] << 24) | (env->data->data[5] << 16) | (env->data->data[6] << 8) | env->data->data[7]; + + if (crc32_calc == crc32_received) { + env->dataResponse[4] = UDS_routine_RoutineStartStopSuccess; + } else { + env->dataResponse[4] = UDS_routine_RoutineStartStopFailure; + } + + + return 4 + 1; +} + +#include "fc7xxx_driver_fmc.h" + + +static uint16_t vUDS_routine_Erase_Memory(tCanUds *env, eUdsRoutineControlType udsRoutineControlType) { + + + if (udsRoutineControlType != UDS_routine_StartRoutine) { + return 0xFF00 | UDS_error_sub_functionNotSupported; + } + + if (env->data->len < 13) { + return 0xFF00 | UDS_error_incorrectMessageLengthOrInvalidFormat; + } + +// if (((env->udsFirmwareStepsMain != UDS_Firmware_Step_Preconditions) && (env->udsFirmwareStepsMain != UDS_Firmware_Step_EraseMemory)) && +// ((env->udsFirmwareStepsCalib != UDS_Firmware_Step_Preconditions) && (env->udsFirmwareStepsCalib != UDS_Firmware_Step_EraseMemory))) { +// return 0xFF00 | UDS_error_requestSequenceError; +// } + + tEraseMemory *eraseMemory = (tEraseMemory *) env->data->data; + + env->udsBlock = UDS_BlockInit; + + +// if (eraseMemory->memoryAddress == ADR_HEX_BlockBoot) { +// env->udsBlock = UDS_BlockBoot; +// } else + + if (eraseMemory->memoryAddress == ADR_HEX_BlockMain) { + env->udsBlock = UDS_BlockMain; + } + + if (eraseMemory->memoryAddress == ADR_HEX_BlockCalib) { + env->udsBlock = UDS_BlockCalib; + } + + if (env->udsBlock == UDS_BlockInit) { + return 0xFF00 | UDS_error_requestSequenceError; + } + + setResponseErrorPending(env, UDS_RoutineControl, UDS_error_requestCorrectlyReceived_ResponsePending); + + +// if (env->udsBlock == UDS_BlockBoot) { +// env->timeoutPendingClear = SystemGetMs() + 200; +// bool result1 = env->clear_flash_func(ADR_HEX_Mapped_BlockBoot, SIZE_HEX_BlockBoot, SendUpdatePendingFlashClear, +// env); +// if (result1) { +// env->dataResponse[4] = UDS_routine_RoutineStartStopSuccess; +// return 4 + 1; +// } +// } + + if (env->udsBlock == UDS_BlockMain) { + env->timeoutPendingClear = SystemGetMs() + 200; + bool result1 = env->clear_flash_func(ADR_HEX_Mapped_BlockMain, (SIZE_HEX_BlockMain / 2), + SendUpdatePendingFlashClear, env); + setResponseErrorPending(env, UDS_RoutineControl, UDS_error_requestCorrectlyReceived_ResponsePending); + bool result2 = env->clear_flash_func(ADR_HEX_Mapped_BlockMain + (SIZE_HEX_BlockMain / 2), + (SIZE_HEX_BlockMain / 2), SendUpdatePendingFlashClear, env); + + if ((result1) && (result2)) { + env->dataResponse[4] = UDS_routine_RoutineStartStopSuccess; + + env->udsFirmwareStepsMain = UDS_Firmware_Step_EraseMemory; + + return 4 + 1; + } + + } + + if (env->udsBlock == UDS_BlockCalib) { + env->timeoutPendingClear = SystemGetMs() + 200; + bool result1 = env->clear_flash_func(ADR_HEX_Mapped_BlockCalib, SIZE_HEX_BlockCalib, + SendUpdatePendingFlashClear, env); + + if (result1) { + env->dataResponse[4] = UDS_routine_RoutineStartStopSuccess; + + env->udsFirmwareStepsCalib = UDS_Firmware_Step_EraseMemory; + + return 4 + 1; + } + } + + env->dataResponse[4] = UDS_routine_RoutineStartStopFailure; + + return 4 + 1; +} + + +static uint16_t +vUDS_routine_Check_Programming_Dependancies(tCanUds *env, eUdsRoutineControlType udsRoutineControlType) { + + if (udsRoutineControlType != UDS_routine_StartRoutine) { + return 0xFF00 | UDS_error_sub_functionNotSupported; + } + +// if (((env->udsFirmwareStepsMain != UDS_Firmware_Step_EraseMemory) && (env->udsFirmwareStepsMain != UDS_Firmware_Step_Dependancies)) && +// ((env->udsFirmwareStepsCalib != UDS_Firmware_Step_EraseMemory) && (env->udsFirmwareStepsCalib != UDS_Firmware_Step_Dependancies))) { +// return 0xFF00 | UDS_error_requestSequenceError; +// } + + if ((env->udsFirmwareStepsMain != UDS_Firmware_Step_EraseMemory) || + (env->udsFirmwareStepsCalib != UDS_Firmware_Step_EraseMemory)) { + + env->dataResponse[4] = UDS_routine_RoutineStartStopFailure; + return 4 + 1; + + } + + setResponseErrorPending(env, UDS_RoutineControl, UDS_error_requestCorrectlyReceived_ResponsePending); + + bool result = P_bInternalFlashPage_CopyRange(ADR_HEX_Mapped_BlockBoot, ADR_HEX_BlockBoot, SIZE_HEX_BlockBoot, + NULL, NULL); + + if (result == false) { + env->dataResponse[4] = UDS_routine_RoutineStartStopFailure; + + return 4 + 1; + } + + + setResponseErrorPending(env, UDS_RoutineControl, UDS_error_requestCorrectlyReceived_ResponsePending); + + int resultBoot = memcmp((uint8_t *) ADR_HEX_Mapped_BlockBoot, (uint8_t *) ADR_HEX_BlockBoot, SIZE_HEX_BlockBoot); + + if (resultBoot != 0) { + env->dataResponse[4] = UDS_routine_RoutineStartStopFailure; + + return 4 + 1; + } + +// uint32_t crc32_calc = UdsCrc32Update_Hardware(0xFFFFFFFF, (uint8_t *) ADR_HEX_Mapped_BlockBoot, +// SIZE_HEX_BlockBoot - 4, +// SendUpdatePendingCrc, env, 200); +// uint32_t crc32_file = (*(uint32_t *) (ADR_HEX_Mapped_BlockBoot + SIZE_HEX_BlockBoot - 4)); +// if (crc32_calc != crc32_file) { +// env->dataResponse[4] = UDS_routine_RoutineStartStopFailure; +// return 4 + 1; +// } + +/* + if (env->udsFirmwareStepsMain != UDS_Firmware_Step_EraseMemory) { + + setResponseErrorPending(env, UDS_RoutineControl, UDS_error_requestCorrectlyReceived_ResponsePending); + uint32_t size = SIZE_HEX_BlockMain / 4; + uint32_t adr_map = ADR_HEX_Mapped_BlockMain; + uint32_t adr_orig = ADR_HEX_BlockMain; + result = P_bInternalFlashPage_CopyRange(adr_map, adr_orig, size, NULL, NULL); + if (result == false) { + env->dataResponse[4] = UDS_routine_RoutineStartStopFailure; + return 4 + 1; + } + + setResponseErrorPending(env, UDS_RoutineControl, UDS_error_requestCorrectlyReceived_ResponsePending); + adr_map = ADR_HEX_Mapped_BlockMain + size; + adr_orig = ADR_HEX_BlockMain + size; + result = P_bInternalFlashPage_CopyRange(adr_map, adr_orig, size, NULL, NULL); + if (result == false) { + env->dataResponse[4] = UDS_routine_RoutineStartStopFailure; + return 4 + 1; + } + + setResponseErrorPending(env, UDS_RoutineControl, UDS_error_requestCorrectlyReceived_ResponsePending); + adr_map = ADR_HEX_Mapped_BlockMain + size; + adr_orig = ADR_HEX_BlockMain + size; + result = P_bInternalFlashPage_CopyRange(adr_map, adr_orig, size, NULL, NULL); + if (result == false) { + env->dataResponse[4] = UDS_routine_RoutineStartStopFailure; + return 4 + 1; + } + + setResponseErrorPending(env, UDS_RoutineControl, UDS_error_requestCorrectlyReceived_ResponsePending); + adr_map = ADR_HEX_Mapped_BlockMain + size; + adr_orig = ADR_HEX_BlockMain + size; + result = P_bInternalFlashPage_CopyRange(adr_map, adr_orig, size, NULL, NULL); + if (result == false) { + env->dataResponse[4] = UDS_routine_RoutineStartStopFailure; + return 4 + 1; + } + + } + + if (env->udsFirmwareStepsCalib != UDS_Firmware_Step_EraseMemory) { + + setResponseErrorPending(env, UDS_RoutineControl, UDS_error_requestCorrectlyReceived_ResponsePending); + result = P_bInternalFlashPage_CopyRange(ADR_HEX_Mapped_BlockCalib, ADR_HEX_BlockCalib, SIZE_HEX_BlockCalib, + NULL, NULL); + + if (result == false) { + env->dataResponse[4] = UDS_routine_RoutineStartStopFailure; + + return 4 + 1; + } + + } +*/ + + setResponseErrorPending(env, UDS_RoutineControl, UDS_error_requestCorrectlyReceived_ResponsePending); + uint32_t crc32_calc = UdsCrc32Update_Hardware(0xFFFFFFFF, (uint8_t *) ADR_HEX_Mapped_BlockMain, + SIZE_HEX_BlockMain - 4, + SendUpdatePendingCrc, env, 200); + + uint32_t crc32_file = (*(uint32_t * )(ADR_HEX_Mapped_BlockMain + SIZE_HEX_BlockMain - 4)); + + if (crc32_calc != crc32_file) { + env->dataResponse[4] = UDS_routine_RoutineStartStopFailure; + + return 4 + 1; + } + + setResponseErrorPending(env, UDS_RoutineControl, UDS_error_requestCorrectlyReceived_ResponsePending); + crc32_calc = UdsCrc32Update_Hardware(0xFFFFFFFF, (uint8_t *) ADR_HEX_Mapped_BlockCalib, SIZE_HEX_BlockCalib - 4, + SendUpdatePendingCrc, env, 200); + + crc32_file = (*(uint32_t * )(ADR_HEX_Mapped_BlockCalib + SIZE_HEX_BlockCalib - 4)); + + if (crc32_calc != crc32_file) { + env->dataResponse[4] = UDS_routine_RoutineStartStopFailure; + + return 4 + 1; + } + + FMC_API_ACTIVE_BLOCK_TYPE ActiveBank = FMCDRIVER_GetActiveBlock(FMC_INSTANCE_1); + + uint64_t NumberBank; + + if (ActiveBank == FMC_Active0) { + NumberBank = 0x1122334455667788; + } else { + NumberBank = 0; + } + + result = D_bInternalFlashPage_Clear(0x04000000, NULL, NULL); + + if (result == false) { + env->dataResponse[4] = UDS_routine_RoutineStartStopFailure; + + return 4 + 1; + } + + size_t size = D_sInternalFlashPage_Write(0x04000000, 0, (uint8_t * ) & NumberBank, 8); + + if (size != 8) { + env->dataResponse[4] = UDS_routine_RoutineStartStopFailure; + + return 4 + 1; + } + + env->udsFirmwareStepsMain = UDS_Firmware_Step_None; + env->udsFirmwareStepsCalib = UDS_Firmware_Step_None; + +// env->udsFirmwareStepsMain = UDS_Firmware_Step_Dependancies; +// env->udsFirmwareStepsCalib = UDS_Firmware_Step_Dependancies; + + env->dataResponse[4] = UDS_routine_RoutineStartStopSuccess; + + return 4 + 1; +} + +static uint16_t vUDS_routine_eComp_Initialize(tCanUds *env, eUdsRoutineControlType udsRoutineControlType) { + + eUdsRoutineStartStopRoutineResult udsStartStopRoutineResult = UDS_routine_RoutineStartStopSuccess; + eUdsRequestRoutineResult udsRequestRoutineResult = UDS_routine_RoutineFinishSuccess; + + if ((udsRoutineControlType == UDS_routine_StartRoutine) || (udsRoutineControlType == UDS_routine_StopRoutine)) { + env->dataResponse[4] = udsStartStopRoutineResult; + } + + if (udsRoutineControlType == UDS_routine_RequestRoutineResults) { + env->dataResponse[4] = udsRequestRoutineResult; + } + + return 4 + 1; +} + +extern void FirmwareStopThread(); + +static uint16_t Routine_Control_31(tCanUds *env) { + + tUdsServiceCommand *com = (tUdsServiceCommand *) env->data->data; + + if (env->data->len < 4) { + return setResponseError(env, UDS_Communication_Control, + UDS_error_incorrectMessageLengthOrInvalidFormat); + } + + eUdsRoutineControlType udsRoutineControlType = env->data->data[1]; + uint8_t routineIdentifier_hi = env->data->data[2]; + uint8_t routineIdentifier_lo = env->data->data[3]; + uint16_t routineIdentifier = (routineIdentifier_hi << 8) | routineIdentifier_lo; + + if ((udsRoutineControlType != UDS_routine_StartRoutine) && (udsRoutineControlType != UDS_routine_StopRoutine) && + (udsRoutineControlType != UDS_routine_RequestRoutineResults)) { + return setResponseError(env, UDS_RoutineControl, UDS_error_sub_functionNotSupported); + } + + env->dataResponse[0] = UDS_RoutineControl | 0b1000000; + env->dataResponse[1] = env->data->data[1]; // eUdsRoutineControlType + env->dataResponse[2] = routineIdentifier_hi; + env->dataResponse[3] = routineIdentifier_lo; + + switch (routineIdentifier) { + case Check_Programming_Preconditions: { + + if (env->currentSession == UDS_session_defaultSession) { + return setResponseError(env, UDS_RoutineControl, UDS_error_conditionsNotCorrect); + } + + FirmwareStopThread(); +// if (!env->SA.stateSecurityAccess) { +// return setResponseError(env, UDS_RoutineControl, UDS_error_securityAccessDenied); +// } + + uint16_t result = vUDS_check_Programming_Preconditions(env, udsRoutineControlType); + + if (result > 0xFF00) { + return setResponseError(env, UDS_RoutineControl, result & 0xFF); + } + + return result; + + } + case UDS_routine_VIN_learn: { + + if ((env->currentSession == UDS_session_defaultSession) || + (env->currentSession == UDS_session_programmingSession)) { + return setResponseError(env, UDS_RoutineControl, UDS_error_conditionsNotCorrect); + } + + if (!env->SA.stateSecurityAccess) { + return setResponseError(env, UDS_RoutineControl, UDS_error_securityAccessDenied); + } + + uint16_t result = vUDS_routine_VIN_learn(env, udsRoutineControlType); + + if (result > 0xFF00) { + return setResponseError(env, UDS_RoutineControl, result & 0xFF); + } + + return result; + } + case UDS_routine_Compare_Checksum: { + + if ((env->currentSession == UDS_session_defaultSession) || + (env->currentSession == UDS_session_extendedDiagnosticSession)) { + return setResponseError(env, UDS_RoutineControl, UDS_error_conditionsNotCorrect); + } + + if (!env->SA.stateSecurityAccess) { + return setResponseError(env, UDS_RoutineControl, UDS_error_securityAccessDenied); + } + + uint16_t result = vUDS_routine_Compare_Checksum(env, udsRoutineControlType); + + if (result > 0xFF00) { + return setResponseError(env, UDS_RoutineControl, result & 0xFF); + } + + return result; + } + case UDS_routine_Erase_Memory: { + + if ((env->currentSession == UDS_session_defaultSession) || + (env->currentSession == UDS_session_extendedDiagnosticSession)) { + return setResponseError(env, UDS_RoutineControl, UDS_error_conditionsNotCorrect); + } + + if (!env->SA.stateSecurityAccess) { + return setResponseError(env, UDS_RoutineControl, UDS_error_securityAccessDenied); + } + + uint16_t result = vUDS_routine_Erase_Memory(env, udsRoutineControlType); + + if (result > 0xFF00) { + return setResponseError(env, UDS_RoutineControl, result & 0xFF); + } + + return result; + } + case UDS_routine_Check_Programming_Dependancies: { + + if (env->currentSession == UDS_session_extendedDiagnosticSession) { + return setResponseError(env, UDS_RoutineControl, UDS_error_conditionsNotCorrect); + } + + if (!env->SA.stateSecurityAccess) { + return setResponseError(env, UDS_RoutineControl, UDS_error_securityAccessDenied); + } + + uint16_t result = vUDS_routine_Check_Programming_Dependancies(env, udsRoutineControlType); + + if (result > 0xFF00) { + return setResponseError(env, UDS_RoutineControl, result & 0xFF); + } + + return result; + } + case UDS_routine_eComp_Initialize: { + + if ((env->currentSession == UDS_session_defaultSession) || + (env->currentSession == UDS_session_programmingSession)) { + return setResponseError(env, UDS_RoutineControl, UDS_error_conditionsNotCorrect); + } + + if (!env->SA.stateSecurityAccess) { + return setResponseError(env, UDS_RoutineControl, UDS_error_securityAccessDenied); + } + + uint16_t result = vUDS_routine_eComp_Initialize(env, udsRoutineControlType); + + if (result > 0xFF00) { + return setResponseError(env, UDS_RoutineControl, result & 0xFF); + } + + return result; + } + default: + return setResponseError(env, UDS_RoutineControl, UDS_error_requestOutOfRange); + } + +} +// конец --------------------------- Функции ------------------------------------------------------------- +// конец --------------------------- Функции ------------------------------------------------------------- +// конец --------------------------- Функции ------------------------------------------------------------- + + +// начало --------------------------- Security Access ------------------------------------------------------------- +// начало --------------------------- Security Access ------------------------------------------------------------- +// начало --------------------------- Security Access ------------------------------------------------------------- + +static uint16_t SecurityAccess_27(tCanUds *env) { + + tUdsServiceCommand *com = (tUdsServiceCommand *) env->data->data; + + if (env->data->len < 2) { + return setResponseError(env, UDS_SecurityAccess, + UDS_error_incorrectMessageLengthOrInvalidFormat); + } + + if ((com->sub_function != UDS_sub_requestSeed) && (com->sub_function != UDS_sub_sendKey)) { + return setResponseError(env, UDS_SecurityAccess, UDS_error_sub_functionNotSupported); + } + + if (env->currentSession == UDS_session_defaultSession) { + return setResponseError(env, UDS_SecurityAccess, UDS_error_conditionsNotCorrect); + } + + // Отправляется, если таймер задержки активен и получен запрос + if ((env->SA.time_counter_max_attempts_default > 0) && + (SystemGetMs() - env->SA.time_counter_max_attempts_default) < BLOCK_TIME_DEFAULT) { + return setResponseError(env, UDS_SecurityAccess, UDS_error_requiredTimeDelayNotExpired); + } + + if (com->sub_function == UDS_sub_requestSeed) { + + // Получен запрос + env->SA.requestSequenceRequestSeed = true; + + env->dataResponse[0] = UDS_SecurityAccess | 0b1000000; + env->dataResponse[1] = env->data->data[1] & 0b01111111; // sub-function + + // Доступ уже получен + if (env->SA.stateSecurityAccess) { + env->dataResponse[2] = 0; + env->dataResponse[3] = 0; + env->dataResponse[4] = 0; + env->dataResponse[5] = 0; + } else { + + env->randomSecuritySeed = getRandom32(env->adcTask0); + + if (env->randomSecuritySeed == 0) { + env->randomSecuritySeed = 0x11223344; + } + + env->dataResponse[2] = env->randomSecuritySeed >> 24; + env->dataResponse[3] = env->randomSecuritySeed >> 16; + env->dataResponse[4] = env->randomSecuritySeed >> 8; + env->dataResponse[5] = env->randomSecuritySeed; + } + return 6; + } + + if (com->sub_function == UDS_sub_sendKey) { + + if (env->data->len < 6) { + return setResponseError(env, UDS_SecurityAccess, UDS_error_requestOutOfRange); + } + + // Ранее не получен запрос UDS_sub_requestSeed + if (env->SA.requestSequenceRequestSeed == false) { + return setResponseError(env, UDS_SecurityAccess, UDS_error_requestSequenceError); + } + + if ((env->SA.time_counter_max_attempts_default > 0) && + (SystemGetMs() - env->SA.time_counter_max_attempts_default) > BLOCK_TIME_DEFAULT) { + env->SA.time_counter_max_attempts_default = 0; + env->SA.counter_max_attempts_default = 0; + } + + // Отправляется, если активирован таймер задержки из-за превышения максимального числа неудачных попыток доступа + if (env->SA.counter_max_attempts_default >= MAX_ATTEMPTS_DEFAULT) { + env->SA.time_counter_max_attempts_default = SystemGetMs(); + return setResponseError(env, UDS_SecurityAccess, UDS_error_exceededNumberOfAttempts); + } + + uint32_t securitySeedFromServer = + (env->data->data[2] << 24) | (env->data->data[3] << 16) | (env->data->data[4] << 8) | + env->data->data[5]; + + uint32_t securitySeedMy = generate_key(env->randomSecuritySeed); + + if (securitySeedMy != securitySeedFromServer) { + ++env->SA.counter_max_attempts_default; + return setResponseError(env, UDS_SecurityAccess, UDS_error_invalidKey); + } + + env->SA.stateSecurityAccess = true; + + env->dataResponse[0] = UDS_SecurityAccess | 0b1000000; + env->dataResponse[1] = env->data->data[1] & 0b01111111; // sub-function + + return 2; + } + + return setResponseError(env, UDS_SecurityAccess, UDS_error_invalidKey); +} +// конец --------------------------- Security Access ------------------------------------------------------------- +// конец --------------------------- Security Access ------------------------------------------------------------- +// конец --------------------------- Security Access ------------------------------------------------------------- + + +// начало --------------------------- RequestDownload --------------------------------------------------------- +// начало --------------------------- RequestDownload --------------------------------------------------------- +// начало --------------------------- RequestDownload --------------------------------------------------------- + + +static uint16_t RequestDownload_34(tCanUds *env) { + + tRequestDownload_Request *com = (tRequestDownload_Request *) env->data->data; + + if (env->data->len < 11) { + return setResponseError(env, UDS_RequestDownload, UDS_error_incorrectMessageLengthOrInvalidFormat); + } + + if (com->dataFormatIdentifier != 0) { + return setResponseError(env, UDS_RequestDownload, UDS_error_requestOutOfRange); + } + + env->udsBlock = UDS_BlockInit; + +// if (com->memoryAddress == ADR_HEX_BlockBoot) { +// env->udsBlock = UDS_BlockBoot; +// } + + if (com->memoryAddress == ADR_HEX_BlockMain) { + env->udsBlock = UDS_BlockMain; + } + + if (com->memoryAddress == ADR_HEX_BlockCalib) { + env->udsBlock = UDS_BlockCalib; + } + + if (env->udsBlock == UDS_BlockInit) { + return setResponseError(env, UDS_RequestDownload, UDS_error_requestSequenceError); + } + + FMC_API_ACTIVE_BLOCK_TYPE activeBlock = FMCDRIVER_GetActiveBlock(FMC_INSTANCE_1); + + env->AdrFlash = com->memoryAddress + 0x00100000; + + env->SizeWriteFlash = 0; + env->DownloadFirmwareSize = com->memorySize; + +// if (env->udsBlock == UDS_BlockBoot) { +// if (com->memorySize > SIZE_HEX_BlockBoot) { +// return setResponseError(env, UDS_RequestDownload, UDS_error_requestOutOfRange); +// } +// } + + if (env->udsBlock == UDS_BlockMain) { + + if (com->memorySize > SIZE_HEX_BlockMain) { + return setResponseError(env, UDS_RequestDownload, UDS_error_requestOutOfRange); + } + } + + if (env->udsBlock == UDS_BlockCalib) { + + if (com->memorySize > SIZE_HEX_BlockCalib) { + return setResponseError(env, UDS_RequestDownload, UDS_error_requestOutOfRange); + } + + } + + + if (env->currentSession == UDS_session_defaultSession) { + return setResponseError(env, UDS_RoutineControl, UDS_error_conditionsNotCorrect); + } + + if (!env->SA.stateSecurityAccess) { + return setResponseError(env, UDS_RoutineControl, UDS_error_securityAccessDenied); + } + + env->CurrentBlockAdr = env->AdrFlash; + env->CurrentBlockSize = env->DownloadFirmwareSize; + + tRequestDownload_Response *requestDownload_Response = (tRequestDownload_Response *) env->dataResponse; + requestDownload_Response->ServiceId = UDS_RequestDownload | 0b1000000; + requestDownload_Response->lengthFormatIdentifier = 0x20; // 2 байта - длина поля maxNumberOfBlockLength + + uint8_t countBlock = 31;//31; + requestDownload_Response->maxNumberOfBlockLength = countBlock * 128 + 2; + +// requestDownload_Response->maxNumberOfBlockLength = 10; + +#if (LOG_UDS == 1) + LoggerFormatInfo(LOGGER, LOG_SIGN, "RequestDownload: memoryAddress = %08X memorySize = %08X", env->AdrFlash, + env->DownloadFirmwareSize) +#endif + + env->stateDownload = UDS_RequestDownload; + +// vCanSerialPortSetMaskCount(env->CanIO->env, 2); + + return 4; +} +// конец --------------------------- RequestDownload --------------------------------------------------------- +// конец --------------------------- RequestDownload --------------------------------------------------------- +// конец --------------------------- RequestDownload --------------------------------------------------------- + + +// начало --------------------------- TransferData --------------------------------------------------------- +// начало --------------------------- TransferData --------------------------------------------------------- +// начало --------------------------- TransferData --------------------------------------------------------- + +static uint16_t TransferData_36(tCanUds *env) { + + tTransferData_Request *com = (tTransferData_Request *) env->data->data; + + if (env->data->len <= 2) { + return setResponseError(env, UDS_TransferData, UDS_error_incorrectMessageLengthOrInvalidFormat); + } + + if ((env->currentSession == UDS_session_defaultSession) || + (env->currentSession == UDS_session_extendedDiagnosticSession)) { + return setResponseError(env, UDS_RoutineControl, UDS_error_conditionsNotCorrect); + } + + if (!env->SA.stateSecurityAccess) { + return setResponseError(env, UDS_RoutineControl, UDS_error_securityAccessDenied); + } + + if (env->stateDownload == UDS_RequestDownload) { + env->stateDownload = UDS_TransferData; + } else { + if (env->stateDownload != UDS_TransferData) { + return setResponseError(env, UDS_RoutineControl, UDS_error_requestSequenceError); + } + } + + + if (env->SizeWriteFlash >= env->DownloadFirmwareSize) { + return setResponseError(env, UDS_RoutineControl, UDS_error_requestSequenceError); + } + + + //setResponseErrorPending(env, UDS_RoutineControl, UDS_error_requestCorrectlyReceived_ResponsePending); + +// if (osMutexAcquire(env->access, 1000) == osOK) { +// env->currentSessionTesterPresentTimeout = SystemGetMs() + timeout_session_S3_Server; +// osMutexRelease(env->access); +// } else { +// LoggerErrorStatic(LOGGER, LOG_SIGN, "Access error TransferData_36"); +// } + + bool result = env->write_flash_func(env->AdrFlash, &env->data->data[2], env->data->len - 2); + + if (result == false) { + return setResponseError(env, UDS_TransferData, UDS_error_generalProgrammingFailure); + } + + env->AdrFlash += env->data->len - 2; + env->SizeWriteFlash += env->data->len - 2; + + +#if (LOG_UDS == 1) + LoggerFormatInfo(LOGGER, LOG_SIGN, "Download: %d of %d kb", env->SizeWriteFlash / 1024, + env->DownloadFirmwareSize / 1024) +#endif + + + tTransferData_Response *transferData_Response = (tTransferData_Response *) env->dataResponse; + transferData_Response->ServiceId = UDS_TransferData | 0b1000000; + transferData_Response->blockSequenceCounter = com->blockSequenceCounter; + + return 2; +} +// конец --------------------------- TransferData --------------------------------------------------------- +// конец --------------------------- TransferData --------------------------------------------------------- +// конец --------------------------- TransferData --------------------------------------------------------- + +// начало --------------------------- RequestTransferExit --------------------------------------------------------- +// начало --------------------------- RequestTransferExit --------------------------------------------------------- +// начало --------------------------- RequestTransferExit --------------------------------------------------------- + +static uint16_t RequestTransferExit_37(tCanUds *env) { + + if ((env->currentSession == UDS_session_defaultSession) || + (env->currentSession == UDS_session_extendedDiagnosticSession)) { + return setResponseError(env, UDS_RoutineControl, UDS_error_conditionsNotCorrect); + } + + if ((env->stateDownload != UDS_TransferData) || (env->SizeWriteFlash < env->DownloadFirmwareSize)) { + return setResponseError(env, UDS_RoutineControl, UDS_error_requestSequenceError); + } else { + env->stateDownload = UDS_RequestTransferExit; + } + + + tRequestTransferExit_Request *com = (tRequestTransferExit_Request *) env->data->data; + + tRequestTransferExit_Response *requestTransferExit_Response = (tRequestTransferExit_Response *) env->dataResponse; + requestTransferExit_Response->ServiceId = UDS_RequestTransferExit | 0b1000000; + + + return 1; +} +// конец --------------------------- RequestTransferExit --------------------------------------------------------- +// конец --------------------------- RequestTransferExit --------------------------------------------------------- +// конец --------------------------- RequestTransferExit --------------------------------------------------------- + +static const eUds_com uds_com[256] = { + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {DiagnosticSessionControl_10, "DiagnosticSessionControl_10", true}, + {ECUReset_11, "ECUReset_11", true}, + {NULL, "", false}, + {NULL, "", false}, + {UDS_ClearDiagnosticInformation_14, "UDS_ClearDiagnosticInformation_14", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {UDS_ReadDTCInformation_19, "UDS_ReadDTCInformation_19", true}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {ReadDataByIdentifier_22, "ReadDataByIdentifier_22", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {SecurityAccess_27, "SecurityAccess_27", true}, + {CommunicationControl_28, "CommunicationControl_28", true}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {WriteDataByIdentifier_2E, "WriteDataByIdentifier_2E", false}, + {InputOutputControlByIdentifier_2F, "InputOutputControlByIdentifier_2F", false}, + {NULL, "", false}, + {Routine_Control_31, "Routine_Control_31", true}, + {NULL, "", false}, + {NULL, "", false}, + {RequestDownload_34, "RequestDownload_34", false}, + {NULL, "", false}, + {TransferData_36, "TransferData_36", false}, + {RequestTransferExit_37, "RequestTransferExit_37", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {TesterPresent_3E, "TesterPresent_3E", true}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {ControlDTCSetting_85, "ControlDTCSetting_85", true}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false}, + {NULL, "", false} +}; + +void ReceivedTP_func(void *arg, tCanTP_data *data) { + tCanUds *env = arg; + env->data = data; + + uint8_t com = env->data->data[0]; + + uint8_t SPRMIB = 0; + + if (uds_com[com].hasSPRMIB) { // Подавление ответа + SPRMIB = env->data->data[1] & 0x80; + env->data->data[1] &= 0x7F; + } + + if (uds_com[com].func != NULL) { + +// if (osMutexAcquire(env->access, 1000) == osOK) { + env->currentSessionTesterPresentTimeout = SystemGetMs() + timeout_session_S3_Server; +// osMutexRelease(env->access); +// } else { +// LoggerErrorStatic(LOGGER, LOG_SIGN, "Access error ReceivedTP_func"); +// } + +#if (LOG_UDS == 1) + sendLogCanUdsHex(env, env->data->data, env->data->len); + LoggerFormatInfo(LOGGER, LOG_SIGN, "> %s [%d] %s", uds_com[com].desc, env->data->len, env->hexString) +#endif + + if (osMutexAcquire(env->access, 5000) == osOK) { + + uint8_t response_size = uds_com[com].func(env); + + if (response_size) { + + if (SPRMIB == 0) { +#if (LOG_UDS == 1) + sendLogCanUdsHex(env, env->dataResponse, response_size); + LoggerFormatInfo(LOGGER, LOG_SIGN, "< %s [%d] %s", uds_com[com].desc, response_size, env->hexString) +#endif + + CanSerialPortFrameTpTransmit(&env->canSerialPortFrameTp, env->dataResponse, + response_size, PROTOCOL_CAN_ADR_UDS, WAIT_FRAME_WRITE); + } else { +#if (LOG_UDS == 1) + sendLogCanUdsHex(env, env->dataResponse, response_size); + LoggerFormatInfo(LOGGER, LOG_SIGN, "< %s Response suppression", uds_com[com].desc) +#endif + } + } + + osMutexRelease(env->access); + } else { + LoggerErrorStatic(LOGGER, LOG_SIGN, "Access error ReceivedTP_func"); + } + + + } else { + asm("nop"); + } + + if (env->isEcuReset) { + + SystemDelayMs(10); + Reset(); + //NVIC_SystemReset(); + } + +} + + +void CanUds(tCanUds *env) { + + for (;;) { + + if (osMutexAcquire(env->access, 5000) == osOK) { + + CanUdsInput_Get_Model(env); + + // Контроль TesterPresent + if ((env->currentSessionTesterPresentTimeout > 0) && + (env->currentSessionTesterPresentTimeout < SystemGetMs())) { + env->currentSessionTesterPresentTimeout = 0; + + setDefaultValue(env); + env->currentSession = UDS_session_defaultSession; + statusData.Status_Active_Diagnostic_Session.Active_Diagnostic_Session = env->currentSession; + + } + + CanUdsOutput_Set_Model(env); + + osMutexRelease(env->access); + } else { + LoggerErrorStatic(LOGGER, LOG_SIGN, "Access error CanUds"); + } + + SystemDelayMs(100); + } +} + + +void CanSerialPortCanUds_Start(tCanUds *env) { +// ThreadBlock_Start(env->T_can_Uds, env, CanUds); + if (!env->thread_Uds.id) { + env->thread_Uds.id = osThreadNew((osThreadFunc_t) (CanUds), (void *) (env), &env->thread_Uds.attr); + } + + CanSerialPortFrameTp_Start(&env->canSerialPortFrameTp); +} + + +void CanUds_Init( + tCanUds *env, + tDiagnostic *Diagnostic, + tSerialPortFrameIO *CanIO, + tDeviceStorage *deviceStorage, + tCanSpamTransmitter *canSpamTransmitter, + tCanSpamDebugTransmitter *canSpamDebugTransmitter, + tAdc0Task *adcTask0, + uds_clear_flash_func *clear_flash_func, + uds_write_flash_func *write_flash_func, + tLoggerInterface *logger) { + + env->logger = logger; + env->CanIO = CanIO; + env->deviceStorage = deviceStorage; + env->Diagnostic = Diagnostic; + env->adcTask0 = adcTask0; + env->filterIdCount = 2; + env->canSpamTransmitter = canSpamTransmitter; + env->canSpamDebugTransmitter = canSpamDebugTransmitter; + env->clear_flash_func = clear_flash_func; + env->write_flash_func = write_flash_func; + + env->access = osMutexNew(NULL); + + env->queue_input_get_Status_Sensor = osMessageQueueNew(1, sizeof(tStatus_Sensor_For_Model), NULL); + env->queue_input_get_Status_Actuator_DoorsActuator = osMessageQueueNew(1, sizeof(tStatus_Actuator_For_Model), NULL); + env->queue_input_get_Status_Duct_Tgt = osMessageQueueNew(1, sizeof(tStatus_Duct_Tgt_For_Model), NULL); + env->queue_input_get_Status_Eva_Tgt = osMessageQueueNew(1, sizeof(tStatus_Eva_Tgt_For_Model), NULL); + env->queue_input_get_Status_IO = osMessageQueueNew(1, sizeof(tStatus_IO_For_Model), NULL); + env->queue_input_get_Status_Pwm = osMessageQueueNew(1, sizeof(tStatus_Pwm_For_Model), NULL); + env->queue_input_get_Status_eComp = osMessageQueueNew(1, sizeof(tStatus_eComp_For_Model), NULL); + env->queue_input_get_Status_External = osMessageQueueNew(1, sizeof(tStatus_External_For_Model), NULL); + env->queue_input_get_Status_EMS = osMessageQueueNew(1, sizeof(tStatus_EMS_For_Model), NULL); + env->queue_input_get_Status_Ionizer_Aroma = osMessageQueueNew(1, sizeof(tStatus_Ionizer_Aroma_For_Model), NULL); + env->queue_input_get_Status_Duct_Select = osMessageQueueNew(1, sizeof(tStatus_Duct_Select_For_Model), NULL); + + + env->queue_output_set_Status_Set = osMessageQueueNew(1, sizeof(tStatus_Set_For_Model), NULL); + env->queue_output_set_Status_Actuator_DoorsActuator = osMessageQueueNew(1, sizeof(tStatus_Actuator_For_Model), + NULL); + env->queue_output_set_Status_Duct_Tgt = osMessageQueueNew(1, sizeof(tStatus_Duct_Tgt_For_Model), NULL); + env->queue_output_set_Status_Eva_Tgt = osMessageQueueNew(1, sizeof(tStatus_Eva_Tgt_For_Model), NULL); + env->queue_output_set_Status_IO = osMessageQueueNew(1, sizeof(tStatus_IO_For_Model), NULL); + env->queue_output_set_Status_Pwm = osMessageQueueNew(1, sizeof(tStatus_Pwm_For_Model), NULL); + env->queue_output_set_Status_eComp = osMessageQueueNew(1, sizeof(tStatus_eComp_For_Model), NULL); + env->queue_output_set_Status_External = osMessageQueueNew(1, sizeof(tStatus_External_For_Model), NULL); + env->queue_output_set_Status_EMS = osMessageQueueNew(1, sizeof(tStatus_EMS_For_Model), NULL); + env->queue_output_set_Status_Ionizer_Aroma = osMessageQueueNew(1, sizeof(tStatus_Ionizer_Aroma_For_Model), NULL); + env->queue_output_set_Status_Duct_Select = osMessageQueueNew(1, sizeof(tStatus_Duct_Select_For_Model), NULL); + + setDefaultStatus(); + + env->filterReqId[0] = Diag_To_CCU_CANID; + env->filterReqId[1] = Diag_Functional_CANID; + env->filterReqId[2] = 0; + env->filterReqId[3] = 0; + env->filterReqId[4] = 0; + env->filterReqId[5] = 0; + env->filterReqId[6] = 0; + + env->filterRespId[0] = Diag_From_CCU_CANID; + env->filterRespId[1] = Diag_From_CCU_CANID; + env->filterRespId[2] = 0; + env->filterRespId[3] = 0; + env->filterRespId[4] = 0; + env->filterRespId[5] = 0; + env->filterRespId[6] = 0; + + + env->filterDirReq[0] = 0; + env->filterDirReq[1] = 0; + env->filterDirReq[2] = 0; + env->filterDirReq[3] = 0; + env->filterDirReq[4] = 0; + env->filterDirReq[5] = 0; + env->filterDirReq[6] = 0; + + + CanSerialPortFrameTpInit( + &env->canSerialPortFrameTp, + + ReceivedCan_func, + env, + + ReceivedTP_func, + env, + + env->CanIO, + (tCanTP_data *) &env->canTP_Ext_data, + sizeof(env->canTP_Ext_data.data), + env->logger, + + env->filterIdCount, + env->filterReqId, + env->filterRespId, + env->filterDirReq + + ); + + env->currentSession = UDS_session_defaultSession; + statusData.Status_Active_Diagnostic_Session.Active_Diagnostic_Session = UDS_session_defaultSession; + +// InitThreadBlock(env->T_can_Uds, "UdsTester", osPriorityNormal); + InitThreadAtrStatic(&env->thread_Uds.attr, "UdsTester", env->thread_Uds.controlBlock, env->thread_Uds.stack, + osPriorityNormal); + +}; \ No newline at end of file diff --git a/MODULES/HVAC_M7_CAN_UDS/CanUds.h b/MODULES/HVAC_M7_CAN_UDS/CanUds.h new file mode 100644 index 0000000..31b7f71 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_UDS/CanUds.h @@ -0,0 +1,329 @@ +// +// Created by cfif on 20.01.2026. +// + +#ifndef HVAC_M7_CANUDS_H +#define HVAC_M7_CANUDS_H + +#include "CanSerialPortFrameTP.h" +#include "DeviceStorage.h" +#include "DiagnosticTask.h" +#include "CanSpamTransmitter.h" +#include "CanSpamDebugTransmitter.h" +#include "AdcTasks.h" +#include "StatusData.h" + +#define LOG_UDS 0 + +//#define CAN_US_QUEUE_SIZE 1 + +#define MAX_ATTEMPTS_DEFAULT 3 +#define BLOCK_TIME_DEFAULT 60000 + +#define timeout_session_S3_Server 7000 + +#define ADR_HEX_BlockBoot 0x01000000 +#define ADR_HEX_BlockMain 0x01010000 +#define ADR_HEX_BlockCalib 0x010C0000 + +#define ADR_HEX_Mapped_BlockBoot 0x01100000 +#define ADR_HEX_Mapped_BlockMain 0x01110000 +#define ADR_HEX_Mapped_BlockCalib 0x011C0000 + +#define SIZE_HEX_BlockBoot (64 * 1024) +#define SIZE_HEX_BlockMain (704 * 1024) +#define SIZE_HEX_BlockCalib (256 * 1024) + + +#define LEN_DEBUG_UDS_BUFF 128 + + +typedef enum { + UDS_Firmware_Step_None = 0, + UDS_Firmware_Step_Preconditions = 1, + UDS_Firmware_Step_EraseMemory = 2, + UDS_Firmware_Step_Dependancies = 3 + +} eUdsFirmwareSteps; + +// Время (логарифмическая шкала) +// │ +// ├── StMin (0.1-127 мс) ← Между КАДРАМИ +// │ │ +// ├── N_As, N_Bs (до 1000 мс) ← Транспортные таймауты +// │ │ +// ├── P2Server (до 50 мс) ← Между СООБЩЕНИЯМИ (UDS) +// │ │ +// ├── P2*Server (до 5000 мс) ← Ожидание при ResponsePending +// │ │ +// └── S3_Server (до 5000 мс) ← ТАЙМЕР ВСЕЙ СЕССИИ + +typedef enum { + UDS_DiagnosticSessionControl = 0x10, + UDS_ReadDTCInformation = 0x19, + UDS_ClearDiagnosticInformation = 0x14, + UDS_TesterPresent = 0x3E, + UDS_ReadDataByIdentifier = 0x22, + UDS_WriteDataByIdentifier = 0x2E, + UDS_RoutineControl = 0x31, + UDS_ECUResetService = 0x11, + UDS_InputOutputControlByIdentifier = 0x2F, + UDS_SecurityAccess = 0x27, + UDS_Communication_Control = 0x28, + UDS_ControlDTCSetting = 0x85, + UDS_RequestDownload = 0x34, + UDS_TransferData = 0x36, + UDS_RequestTransferExit = 0x37 + +} eUdsServices; + +typedef enum { + UDS_error_incorrectMessageLengthOrInvalidFormat = 0x13, + UDS_error_responseTooLong = 0x14, + UDS_error_requestOutOfRange = 0x31, + UDS_error_securityAccessDenied = 0x33, + UDS_error_invalidKey = 0x35, + UDS_error_sub_functionNotSupported = 0x12, + UDS_error_conditionsNotCorrect = 0x22, + UDS_error_requestSequenceError = 0x24, + UDS_error_exceededNumberOfAttempts = 0x36, + UDS_error_requiredTimeDelayNotExpired = 0x37, + UDS_error_generalProgrammingFailure = 0x72, + UDS_error_requestCorrectlyReceived_ResponsePending = 0x78 +} eUdsResponseError; + + +typedef enum { + UDS_session_defaultSession = 0x1, + UDS_session_programmingSession = 0x2, + UDS_session_extendedDiagnosticSession = 0x3 +} eUdsSession; + +typedef enum { + UDS_io_returnControlToECU = 0x0, + UDS_io_shortTermAdjustment = 0x3 +} eUdsIO; + +typedef enum { + UDS_dtc_reportNumberOfDTCByStatusMask = 0x01, + UDS_dtc_reportDTCByStatusMask = 0x02, + UDS_dtc_reportDTCBySupport = 0x0A +} eUdsDtc; + +typedef enum { + UDS_reset_hardReset = 0x1, + UDS_reset_softReset = 0x3, + UDS_reset_rapidReset = 0x4 +} eUdsReset; + +typedef enum { + UDS_sub_enableRxAndTx = 0x0, + UDS_sub_enableRxAndDisableTx = 0x1 +} eUdsCommunicationControl; + +typedef enum { + UDS_sub_dtc_on = 0x1, + UDS_sub_dtc_off = 0x2 +} eUdsControlDTCSetting; + +typedef enum { + UDS_sub_requestSeed = 0x1, + UDS_sub_sendKey = 0x2 +} eUdsSecurityAccess; + +typedef enum { + UDS_routine_StartRoutine = 1, + UDS_routine_StopRoutine = 2, + UDS_routine_RequestRoutineResults = 3 +} eUdsRoutineControlType; + +typedef enum { + Check_Programming_Preconditions = 0x0203, + UDS_routine_VIN_learn = 0x1300, + UDS_routine_Compare_Checksum = 0x0202, + UDS_routine_Erase_Memory = 0xFF00, + UDS_routine_Check_Programming_Dependancies = 0xFF01, + UDS_routine_eComp_Initialize = 0xCF01 +} eUdsRoutineModes; + + +typedef enum { + UDS_routine_RoutineStartStopSuccess = 0x00, + UDS_routine_RoutineStartStopFailure = 0x01 +} eUdsRoutineStartStopRoutineResult; + + +typedef enum { + UDS_routine_RoutineStop = 0, + UDS_routine_RoutineRun = 1, + UDS_routine_RoutineFinishError = 2, + UDS_routine_RoutineFinishSuccess = 3 +} eUdsRequestRoutineResult; + +typedef enum { +// UDS_BlockBoot = 0, + UDS_BlockMain = 1, + UDS_BlockCalib = 2, + UDS_BlockInit = 0xff +} eUdsBlock; + +typedef struct { + eUdsServices service; + uint8_t sub_function; + uint8_t *data; +} tUdsServiceCommand; + +typedef bool (uds_clear_flash_func)(uint32_t firstPageAddr, uint32_t totalSize, void *wdTriggerFct, + void *wdTriggerFct_env); + +typedef bool (uds_write_flash_func)(uint32_t beginPageAddr, void *sourceRamAddr, uint32_t size); + +typedef struct { + tCanSerialPortFrameTp canSerialPortFrameTp; + tLoggerInterface *logger; + tSerialPortFrameIO *CanIO; + tDeviceStorage *deviceStorage; + tDiagnostic *Diagnostic; + tCanTP_data canTP_Ext_data; + + osMutexId_t access; + + tAdc0Task *adcTask0; + + tCanTP_data *data; + uint8_t dataResponse[1024]; + uint8_t dataResponsePending[4]; + + uint8_t filterIdCount; + uint32_t filterReqId[16]; + uint32_t filterRespId[16]; + uint8_t filterDirReq[16]; + + char hexString[LEN_DEBUG_UDS_BUFF]; + + eUdsSession currentSession; + uint32_t currentSessionTesterPresentTimeout; + + tCanSpamTransmitter *canSpamTransmitter; +// tCanSpamSlowTransmitter *canSpamSlowTransmitter; + tCanSpamDebugTransmitter *canSpamDebugTransmitter; + + uint32_t randomSecuritySeed; + + struct { + bool requestSequenceRequestSeed; + bool stateSecurityAccess; + uint32_t counter_max_attempts_default; + uint32_t time_counter_max_attempts_default; + } SA; + + uds_clear_flash_func *clear_flash_func; + uds_write_flash_func *write_flash_func; + + uint32_t AdrFlash; + uint32_t SizeWriteFlash; + uint8_t blockSequenceCounter; + uint32_t DownloadFirmwareSize; + eUdsBlock udsBlock; + + eUdsFirmwareSteps udsFirmwareStepsMain; + eUdsFirmwareSteps udsFirmwareStepsCalib; + + uint32_t CurrentBlockAdr; + uint32_t CurrentBlockSize; + + bool isEcuReset; + + uint32_t timeoutPendingClear; + + eUdsServices stateDownload; + + tStatus_Sensor_For_Model Status_Sensor_For_Model_input; + tStatus_Actuator_For_Model Status_Actuator_DoorsActuator_For_Model_input; + tStatus_Duct_Tgt_For_Model Status_Duct_Tgt_For_Model_input; + tStatus_Eva_Tgt_For_Model Status_Eva_Tgt_For_Model_input; + tStatus_IO_For_Model Status_IO_For_Model_input; + tStatus_Pwm_For_Model Status_Pwm_For_Model_input; + tStatus_eComp_For_Model Status_eComp_For_Model_input; + tStatus_External_For_Model Status_External_For_Model_input; + tStatus_EMS_For_Model Status_EMS_For_Model_input; + tStatus_Ionizer_Aroma_For_Model Status_Ionizer_Aroma_For_Model_input; + tStatus_Duct_Select_For_Model Status_Duct_Select_For_Model_input; + + osMessageQueueId_t queue_input_get_Status_Sensor; + osMessageQueueId_t queue_input_get_Status_Actuator_DoorsActuator; + osMessageQueueId_t queue_input_get_Status_Duct_Tgt; + osMessageQueueId_t queue_input_get_Status_Eva_Tgt; + osMessageQueueId_t queue_input_get_Status_IO; + osMessageQueueId_t queue_input_get_Status_Pwm; + osMessageQueueId_t queue_input_get_Status_eComp; + osMessageQueueId_t queue_input_get_Status_External; + osMessageQueueId_t queue_input_get_Status_EMS; + osMessageQueueId_t queue_input_get_Status_Ionizer_Aroma; + osMessageQueueId_t queue_input_get_Status_Duct_Select; + + + tStatus_Set_For_Model Status_Set_For_Model_output; + tStatus_Actuator_For_Model Status_Actuator_DoorsActuator_For_Model_output; + tStatus_Duct_Tgt_For_Model Status_Duct_Tgt_For_Model_output; + tStatus_Eva_Tgt_For_Model Status_Eva_Tgt_For_Model_output; + tStatus_IO_For_Model Status_IO_For_Model_output; + tStatus_Pwm_For_Model Status_Pwm_For_Model_output; + tStatus_eComp_For_Model Status_eComp_For_Model_output; + tStatus_External_For_Model Status_External_For_Model_output; + tStatus_EMS_For_Model Status_EMS_For_Model_output; + tStatus_Ionizer_Aroma_For_Model Status_Ionizer_Aroma_For_Model_output; + tStatus_Duct_Select_For_Model Status_Duct_Select_For_Model_output; + + osMessageQueueId_t queue_output_set_Status_Set; + osMessageQueueId_t queue_output_set_Status_Actuator_DoorsActuator; + osMessageQueueId_t queue_output_set_Status_Duct_Tgt; + osMessageQueueId_t queue_output_set_Status_Eva_Tgt; + osMessageQueueId_t queue_output_set_Status_IO; + osMessageQueueId_t queue_output_set_Status_Pwm; + osMessageQueueId_t queue_output_set_Status_eComp; + osMessageQueueId_t queue_output_set_Status_External; + osMessageQueueId_t queue_output_set_Status_EMS; + osMessageQueueId_t queue_output_set_Status_Ionizer_Aroma; + osMessageQueueId_t queue_output_set_Status_Duct_Select; + + struct { + osThreadId_t id; + uint32_t stack[384]; + StaticTask_t controlBlock; + osThreadAttr_t attr; + } thread_Uds; + +// tStaticThreadBlock(384) T_can_Uds; +} tCanUds; + +typedef uint16_t (*uds_func_ptr)(tCanUds *env); + +typedef struct { + uds_func_ptr func; + char *desc; + bool hasSPRMIB; +} eUds_com; + + +void CanUds_Init( + tCanUds *env, + tDiagnostic *Diagnostic, + tSerialPortFrameIO *CanIO, + tDeviceStorage *deviceStorage, + tCanSpamTransmitter *canSpamTransmitter, + tCanSpamDebugTransmitter *canSpamDebugTransmitter, + tAdc0Task *adcTask0, + uds_clear_flash_func *clear_flash_func, + uds_write_flash_func *write_flash_func, + tLoggerInterface *logger); + +void CanSerialPortCanUds_Start(tCanUds *env); + +// Тут данные должны быть с модели &env->Status_Sensor_For_Model_input и т.д. +void CanUdsInput_Set_Model(tCanUds *env); + +// Это на вход модели +void CanUdsOutput_Get_Model(tCanUds *env); + +#endif //HVAC_M7_CANUDS_H diff --git a/MODULES/HVAC_M7_CAN_UDS/DiagnosticSessionControl_10.h b/MODULES/HVAC_M7_CAN_UDS/DiagnosticSessionControl_10.h new file mode 100644 index 0000000..e96d165 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_UDS/DiagnosticSessionControl_10.h @@ -0,0 +1,29 @@ +// +// Created by cfif on 06.08.2024. +// + +#ifndef SMART_COMPONENTS_UPDATE_DIAGNOSTICSESSIONCONTROL_10_H +#define SMART_COMPONENTS_UPDATE_DIAGNOSTICSESSIONCONTROL_10_H + +#include "stdint.h" + +#pragma scalar_storage_order big-endian + +// Для готовности загрузки модема +typedef struct __attribute__ ((packed)) { + uint8_t ServiceId; + uint8_t diagnosticSessionType; + uint16_t P2; + uint16_t P2Ex; +} tDiagnosticSessionsType; + + +// Для запроса сессии +typedef struct __attribute__ ((packed)) { + uint8_t ServiceId; + uint8_t diagnosticSessionType; +} tDiagnosticSessionControlRequest; + +#pragma scalar_storage_order little-endian + +#endif //SMART_COMPONENTS_UPDATE_DIAGNOSTICSESSIONCONTROL_10_H diff --git a/MODULES/HVAC_M7_CAN_UDS/DownloadFile.h b/MODULES/HVAC_M7_CAN_UDS/DownloadFile.h new file mode 100644 index 0000000..068fdf4 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_UDS/DownloadFile.h @@ -0,0 +1,46 @@ +// +// Created by cfif on 17.04.2026. +// + +#ifndef HVAC_M7_DOWNLOADFILE_H +#define HVAC_M7_DOWNLOADFILE_H + +#include "stdint.h" + +#pragma scalar_storage_order big-endian + +typedef struct __attribute__ ((packed)) { + uint8_t ServiceId; + uint8_t dataFormatIdentifier; + uint8_t addressAndLengthFormatIdentifier; + uint32_t memoryAddress; + uint32_t memorySize; +} tRequestDownload_Request; + +typedef struct __attribute__ ((packed)) { + uint8_t ServiceId; + uint8_t lengthFormatIdentifier; + uint16_t maxNumberOfBlockLength; +} tRequestDownload_Response; + +typedef struct __attribute__ ((packed)) { + uint8_t ServiceId; + uint8_t blockSequenceCounter; +} tTransferData_Request; + +typedef struct __attribute__ ((packed)) { + uint8_t ServiceId; + uint8_t blockSequenceCounter; +} tTransferData_Response; + +typedef struct __attribute__ ((packed)) { + uint8_t ServiceId; +} tRequestTransferExit_Request; + +typedef struct __attribute__ ((packed)) { + uint8_t ServiceId; +} tRequestTransferExit_Response; + +#pragma scalar_storage_order little-endian + +#endif //HVAC_M7_DOWNLOADFILE_H diff --git a/MODULES/HVAC_M7_CAN_UDS/EraseMemory.h b/MODULES/HVAC_M7_CAN_UDS/EraseMemory.h new file mode 100644 index 0000000..6e860eb --- /dev/null +++ b/MODULES/HVAC_M7_CAN_UDS/EraseMemory.h @@ -0,0 +1,23 @@ +// +// Created by cfif on 26.05.2026. +// + +#ifndef HVAC_M7_ERASEMEMORY_H +#define HVAC_M7_ERASEMEMORY_H + +#include "stdint.h" + +#pragma scalar_storage_order big-endian + +typedef struct __attribute__ ((packed)) { + uint8_t ServiceId; + uint8_t RouteControlType; + uint16_t RoutineIdentifier; + uint8_t addressAndLengthFormatIdentifier; + uint32_t memoryAddress; + uint32_t memorySize; +} tEraseMemory; + +#pragma scalar_storage_order little-endian + +#endif //HVAC_M7_ERASEMEMORY_H diff --git a/MODULES/HVAC_M7_CAN_UDS/TesterPresent_3e.h b/MODULES/HVAC_M7_CAN_UDS/TesterPresent_3e.h new file mode 100644 index 0000000..d800f32 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_UDS/TesterPresent_3e.h @@ -0,0 +1,17 @@ +// +// Created by cfif on 06.08.2024. +// + +#ifndef SMART_COMPONENTS_UPDATE_TESTERPRESENT_3E_H +#define SMART_COMPONENTS_UPDATE_TESTERPRESENT_3E_H + +#include "stdint.h" + +// Для готовности загрузки модема +typedef struct __attribute__ ((packed)) { + uint8_t ServiceId; + uint8_t zeroSubFunction; + +} tTesterPresent; + +#endif //SMART_COMPONENTS_UPDATE_TESTERPRESENT_3E_H diff --git a/MODULES/HVAC_M7_CAN_UDS/modular.json b/MODULES/HVAC_M7_CAN_UDS/modular.json new file mode 100644 index 0000000..0dd1901 --- /dev/null +++ b/MODULES/HVAC_M7_CAN_UDS/modular.json @@ -0,0 +1,10 @@ +{ + "cmake": { + "inc_dirs": [ + "./" + ], + "srcs": [ + "./**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_CRC32/crc32_m7.c b/MODULES/HVAC_M7_CRC32/crc32_m7.c new file mode 100644 index 0000000..3d6a38e --- /dev/null +++ b/MODULES/HVAC_M7_CRC32/crc32_m7.c @@ -0,0 +1,169 @@ +// +// Created by cfif on 21.04.2026. +// +#include "crc32_m7.h" +#include "fc7xxx_driver_crc.h" +#include "SystemDelayInterface.h" + +// Таблица CRC32, предвычисленная для полинома 0xEDB88320UL (отражённая форма 0x04C11DB7) +static const uint32_t crc_table[256] = { + 0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA, 0x076DC419, 0x706AF48F, + 0xE963A535, 0x9E6495A3, 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988, + 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91, 0x1DB71064, 0x6AB020F2, + 0xF3B97148, 0x84BE41DE, 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7, + 0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC, 0x14015C4F, 0x63066CD9, + 0xFA0F3D63, 0x8D080DF5, 0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172, + 0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B, 0x35B5A8FA, 0x42B2986C, + 0xDBBBC9D6, 0xACBCF940, 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59, + 0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116, 0x21B4F4B5, 0x56B3C423, + 0xCFBA9599, 0xB8BDA50F, 0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924, + 0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D, 0x76DC4190, 0x01DB7106, + 0x98D220BC, 0xEFD5102A, 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433, + 0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818, 0x7F6A0DBB, 0x086D3D2D, + 0x91646C97, 0xE6635C01, 0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E, + 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457, 0x65B0D9C6, 0x12B7E950, + 0x8BBEB8EA, 0xFCB9887C, 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65, + 0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2, 0x4ADFA541, 0x3DD895D7, + 0xA4D1C46D, 0xD3D6F4FB, 0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0, + 0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9, 0x5005713C, 0x270241AA, + 0xBE0B1010, 0xC90C2086, 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F, + 0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4, 0x59B33D17, 0x2EB40D81, + 0xB7BD5C3B, 0xC0BA6CAD, 0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A, + 0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683, 0xE3630B12, 0x94643B84, + 0x0D6D6A3E, 0x7A6A5AA8, 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1, + 0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE, 0xF762575D, 0x806567CB, + 0x196C3671, 0x6E6B06E7, 0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC, + 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5, 0xD6D6A3E8, 0xA1D1937E, + 0x38D8C2C4, 0x4FDFF252, 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B, + 0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60, 0xDF60EFC3, 0xA867DF55, + 0x316E8EEF, 0x4669BE79, 0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236, + 0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F, 0xC5BA3BBE, 0xB2BD0B28, + 0x2BB45A92, 0x5CB36A04, 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D, + 0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A, 0x9C0906A9, 0xEB0E363F, + 0x72076785, 0x05005713, 0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38, + 0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21, 0x86D3D2D4, 0xF1D4E242, + 0x68DDB3F8, 0x1FDA836E, 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777, + 0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C, 0x8F659EFF, 0xF862AE69, + 0x616BFFD3, 0x166CCF45, 0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2, + 0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB, 0xAED16A4A, 0xD9D65ADC, + 0x40DF0B66, 0x37D83BF0, 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9, + 0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6, 0xBAD03605, 0xCDD70693, + 0x54DE5729, 0x23D967BF, 0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94, + 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D +}; + + +uint32_t +UdsCrc32Update(uint32_t crc, const uint8_t *data, uint32_t len, crc32_update_func update_func, void *update_func_env, + uint32_t timeout) { + + uint32_t time = SystemGetMs() + timeout; + // Обрабатываем выровненные 4-байтовые блоки + while (len >= 4) { + uint32_t word = *(const uint32_t*)data; + + // Оптимизированная обработка 4 байт за раз + crc = (crc >> 8) ^ crc_table[(crc ^ (word >> 0)) & 0xFF]; + crc = (crc >> 8) ^ crc_table[(crc ^ (word >> 8)) & 0xFF]; + crc = (crc >> 8) ^ crc_table[(crc ^ (word >> 16)) & 0xFF]; + crc = (crc >> 8) ^ crc_table[(crc ^ (word >> 24)) & 0xFF]; + + if (SystemGetMs() > time) { + update_func(update_func_env); + time = SystemGetMs() + timeout; + } + + data += 4; + len -= 4; + } + + // Обрабатываем оставшиеся байты (0-3 байта) + while (len--) { + crc = (crc >> 8) ^ crc_table[(crc ^ *data++) & 0xFF]; + } + + return crc; +} + +uint32_t UdsCrc32Finalize(uint32_t crc) { + return crc ^ 0xFFFFFFFF; +} + +#include "fc7xxx_driver_crc.h" + +/** + * @brief Hardware CRC-32 update function + * + * Configuration that works (Test 2): + * - Polynomial: 0x04C11DB7 (direct form) + * - Write data swap: BYTE_BIT (byte + bit reflection on input) + * - Read data swap: BYTE_BIT (byte + bit reflection on output) + * - Read data FXOR: FXOR (final XOR with 0xFFFFFFFF) + * + * This matches the software implementation that uses reflected polynomial 0xEDB88320. + * + * @param crc Initial CRC value (0xFFFFFFFF for new calculation) + * @param data Pointer to data buffer + * @param len Length of data in bytes + * @param update_func Callback for timeout (can be NULL) + * @param update_func_env Environment for callback + * @param timeout Timeout in milliseconds + * @return uint32_t Updated CRC value + */ +uint32_t UdsCrc32Update_Hardware(uint32_t crc, const uint8_t *data, uint32_t len, + crc32_update_func update_func, void *update_func_env, + uint32_t timeout) +{ + CRC_InitType tInitCfg = {0}; + uint32_t u32Time = SystemGetMs() + timeout; + uint32_t u32Result; + + /* Конфигурация из Test 2 */ + tInitCfg.u32Polynomial = 0x04C11DB7UL; /* Прямой полином */ + tInitCfg.u32SeedValue = crc; /* Начальное значение */ + tInitCfg.eBitWidth = CRC_BIT_32; /* 32-битный режим */ + tInitCfg.eWriteDataSwap = WRITE_DATASWAP_BIT_BYTE; /* Байтовый + битовый swap на входе */ + tInitCfg.eReadDataSwap = READ_DATASWAP_BIT_BYTE; /* Байтовый + битовый swap на выходе */ + tInitCfg.eReadDataFXOR = READ_DATA_FXOR; /* Финальная инверсия (XOR 0xFFFFFFFF) */ + + CRC_Init(CRC_INSTANCE, &tInitCfg); + + /* Обработка данных 32-битными словами для скорости */ + while (len >= 4) + { + uint32_t u32Word = *(const uint32_t*)data; + CRC_SetCalcData_U32(CRC_INSTANCE, u32Word); + + if (update_func != NULL) + { + if (SystemGetMs() > u32Time) + { + update_func(update_func_env); + u32Time = SystemGetMs() + timeout; + } + } + + data += 4; + len -= 4; + } + + /* Обработка оставшихся байтов (0-3) */ + while (len--) + { + CRC_SetCalcData_U8(CRC_INSTANCE, *data++); + + if (update_func != NULL) + { + if (SystemGetMs() > u32Time) + { + update_func(update_func_env); + u32Time = SystemGetMs() + timeout; + } + } + } + + /* Получаем результат (уже с FXOR) */ + u32Result = CRC_GetCrcResult(CRC_INSTANCE); + + return u32Result; +} diff --git a/MODULES/HVAC_M7_CRC32/crc32_m7.h b/MODULES/HVAC_M7_CRC32/crc32_m7.h new file mode 100644 index 0000000..9dd04d4 --- /dev/null +++ b/MODULES/HVAC_M7_CRC32/crc32_m7.h @@ -0,0 +1,17 @@ +// +// Created by cfif on 21.04.2026. +// + +#ifndef HVAC_M7_CRC32_UDS_H +#define HVAC_M7_CRC32_UDS_H +#include "stdint.h" + +typedef void (crc32_update_func)(void *update_func_env); + +uint32_t UdsCrc32Update(uint32_t crc, const uint8_t *data, uint32_t len, crc32_update_func update_func, void *update_func_env, uint32_t timeout); +uint32_t UdsCrc32Finalize(uint32_t crc); +uint32_t UdsCrc32Update_Hardware(uint32_t crc, const uint8_t *data, uint32_t len, + crc32_update_func update_func, void *update_func_env, + uint32_t timeout); + +#endif //HVAC_M7_CRC32_UDS_H diff --git a/MODULES/HVAC_M7_CRC32/modular.json b/MODULES/HVAC_M7_CRC32/modular.json new file mode 100644 index 0000000..0dd1901 --- /dev/null +++ b/MODULES/HVAC_M7_CRC32/modular.json @@ -0,0 +1,10 @@ +{ + "cmake": { + "inc_dirs": [ + "./" + ], + "srcs": [ + "./**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_CanPorts/CanPorts.c b/MODULES/HVAC_M7_CanPorts/CanPorts.c new file mode 100644 index 0000000..0cd9fc1 --- /dev/null +++ b/MODULES/HVAC_M7_CanPorts/CanPorts.c @@ -0,0 +1,817 @@ +// +// Created by cfif on 03.06.2024. +// +#include "CanPorts.h" +#include "string.h" +#include "fc7xxx_driver_port.h" +#include "fc7xxx_driver_gpio.h" +#include "candb.h" +#include "candb_dbg.h" + +#define LOG_SIGN "INIT" +#define LOGGER logger + +tCanPorts CAN_PORTS; + + + + +#if (CAN_DMA_EN == 1) + +typedef struct { + uint32_t u32CanRAM[4]; +} Can_RamType; + +#define size_aRxDataBuf 16 +ALIGN(256) Can_RamType g_aRxDataBufCan0[size_aRxDataBuf]; // dma ring buffer size is 256 +ALIGN(256) Can_RamType g_aRxDataBufCan1[size_aRxDataBuf]; // dma ring buffer size is 256 + +static void DMA_TransferCompleteCallbackCan0(void) { + CanSerialPortFrameIrqRxProcessing(CAN_PORTS.Can0_IO.env, (uint32_t *) &g_aRxDataBufCan0[0]); +} + + +static void DMA_TransferCompleteCallbackCan1(void) { + CanSerialPortFrameIrqRxProcessing(CAN_PORTS.Can1_IO.env, (uint32_t *) &g_aRxDataBufCan1[0]); +} +#else + + +static void CAN0_ErrorInterrupt_CallBack(uint8_t u8CanIndex, FLEXCAN_ErrorInfoType *pErrorInfo) { + + if (pErrorInfo->u32ErrorValue & FLEXCAN_ESR1_BOFFINT_MASK) { + FLEXCAN_Stop(u8CanIndex); + vCanPort_InitCan0(); + } + + FLEXCAN_ClrErrorInfo(u8CanIndex, pErrorInfo); + PROCESS_UNUSED_VAR(u8CanIndex); + PROCESS_UNUSED_VAR(pErrorInfo); +} + +static void CAN0_RxInterrupt_CallBack(uint8_t u8CanIndex, FLEXCAN_RxMsgType *pRxCfg) { + CanSerialPortFrameIrqRxProcessingNO_DMA(CAN_PORTS.Can0_IO.env, pRxCfg); +} + +static void CAN0_RxFifoInterrupt_CallBack(uint8_t u8CanIndex, FLEXCAN_RxMsgType *pRxCfg) { + CanSerialPortFrameIrqRxProcessingNO_DMA(CAN_PORTS.Can0_IO.env, pRxCfg); +} + + + +static void CAN1_ErrorInterrupt_CallBack(uint8_t u8CanIndex, FLEXCAN_ErrorInfoType *pErrorInfo) { + + if (pErrorInfo->u32ErrorValue & FLEXCAN_ESR1_BOFFINT_MASK) { + FLEXCAN_Stop(u8CanIndex); + vCanPort_InitCan1(); + } + + FLEXCAN_ClrErrorInfo(u8CanIndex, pErrorInfo); + PROCESS_UNUSED_VAR(u8CanIndex); + PROCESS_UNUSED_VAR(pErrorInfo); +} + + +static void CAN1_RxInterrupt_CallBack(uint8_t u8CanIndex, FLEXCAN_RxMsgType *pRxCfg) { + CanSerialPortFrameIrqRxProcessingNO_DMA(CAN_PORTS.Can1_IO.env, pRxCfg); +} + +static void CAN1_RxFifoInterrupt_CallBack(uint8_t u8CanIndex, FLEXCAN_RxMsgType *pRxCfg) { + CanSerialPortFrameIrqRxProcessingNO_DMA(CAN_PORTS.Can1_IO.env, pRxCfg); +} + +#endif + + +//static void DMA_ErrorCallback(void) { +// while (1) { +// __asm("nop"); +// } +//} + +static void vCanPort_InitCAN0RxTxPin() { + PORT_InitType tInitStruct = {0U}; + GPIO_InitType tGpioInitStruct = {0}; + + // CAN0_STB + // PortC 30: MUX = GPIO output + tInitStruct.u32PortPins = PORT_PIN_30; + tInitStruct.uPortPinMux.u32PortPinMode = PORT_GPIO_MODE; + PORT_InitPins(PORT_C, &tInitStruct); + tGpioInitStruct.u32GpioPins = PORT_PIN_30; + tGpioInitStruct.ePinDirection = GPIO_OUT; + tGpioInitStruct.ePinLevel = GPIO_LOW; + GPIO_InitPins(GPIO_C, &tGpioInitStruct); + + // Port C2: MUX = ALT3, CAN0_RX + tInitStruct.u32PortPins = PORT_PIN_2; + tInitStruct.uPortPinMux.u32PortPinMode = PORTC_2_FLEXCAN0_RX; + tInitStruct.bPullEn = FALSE; + tInitStruct.ePullSel = PORT_PULL_UP; + PORT_InitPins(PORT_C, &tInitStruct); + tGpioInitStruct.u32GpioPins = PORT_PIN_2; + tGpioInitStruct.ePinDirection = GPIO_IN; + GPIO_InitPins((GPIO_InstanceType) PORT_C, &tGpioInitStruct); + + // Port C3: MUX = ALT3, CAN0_TX + tInitStruct.u32PortPins = PORT_PIN_3; + tInitStruct.uPortPinMux.u32PortPinMode = PORTC_3_FLEXCAN0_TX; + PORT_InitPins(PORT_C, &tInitStruct); + tGpioInitStruct.u32GpioPins = PORT_PIN_3; + tGpioInitStruct.ePinDirection = GPIO_OUT; + tGpioInitStruct.ePinLevel = GPIO_HIGH; + GPIO_InitPins(GPIO_C, &tGpioInitStruct); +} +/* +#define countIdCanHardSoftFilterCan0 31 +const FilterTo_FLEXCAN_RxMbFilterType IdCanHardSoftFilterCan0[countIdCanHardSoftFilterCan0] = { + {FLEXCAN_ID_STD, Diag_To_CCU_CANID, 0x7FF, PROTOCOL_CAN_UDS}, + {FLEXCAN_ID_STD, Diag_Functional_CANID, 0x7FF, PROTOCOL_CAN_UDS}, + {FLEXCAN_ID_STD, EMS_Veh_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, BCM_Powertrain_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, EMS_Veh_02_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, BCM_EEM_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, DMFR_Msg1_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, DMFL_Msg1_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, TM_Stat_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, TM_CP_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, HVC_CCU_Status_Msg_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, BCM_VEH_STATE_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, EMS_HVC_Req_Msg_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, HVC_Err_Status_Msg_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, BCM_CLIMATIC_DATA_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, VCU_CCU_Req_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, ESC_08_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, SMFL_status_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, SMFR_status_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, SMRL_status_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, SMRR_status_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, SDM_Cmd_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, VEH_VIN_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, OCUFL_MSG_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, OCUFR_MSG_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, OCURL_MSG_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, OCURR_MSG_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, DW_STATE_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, FIU_CCU1_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, FIU_CCU2_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, FIU_CCU3_CANID, 0x7FF, PROTOCOL_CAN_RAW} +}; +*/ + + +#define countIdCanHardSoftFilterCan0 13 +const FilterTo_FLEXCAN_RxMbFilterType IdCanHardSoftFilterCan0[countIdCanHardSoftFilterCan0] = { + {FLEXCAN_ID_STD, Diag_To_CCU_CANID, 0x7FF, PROTOCOL_CAN_UDS}, + {FLEXCAN_ID_STD, Diag_Functional_CANID, 0x7FF, PROTOCOL_CAN_UDS}, + {FLEXCAN_ID_STD, EMS_Veh_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, BCM_Powertrain_CANID, 0x7FF, PROTOCOL_CAN_RAW}, +// {FLEXCAN_ID_STD, EMS_Veh_02_CANID, 0x7FF, PROTOCOL_CAN_RAW}, +// {FLEXCAN_ID_STD, BCM_EEM_CANID, 0x7FF, PROTOCOL_CAN_RAW}, +// {FLEXCAN_ID_STD, DMFR_Msg1_CANID, 0x7FF, PROTOCOL_CAN_RAW}, +// {FLEXCAN_ID_STD, DMFL_Msg1_CANID, 0x7FF, PROTOCOL_CAN_RAW}, +// {FLEXCAN_ID_STD, TM_Stat_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, TM_CP_CANID, 0x7FF, PROTOCOL_CAN_RAW}, +// {FLEXCAN_ID_STD, HVC_CCU_Status_Msg_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, BCM_VEH_STATE_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, EMS_HVC_Req_Msg_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, HVC_Err_Status_Msg_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, BCM_CLIMATIC_DATA_CANID, 0x7FF, PROTOCOL_CAN_RAW}, +// {FLEXCAN_ID_STD, VCU_CCU_Req_CANID, 0x7FF, PROTOCOL_CAN_RAW}, +// {FLEXCAN_ID_STD, ESC_08_CANID, 0x7FF, PROTOCOL_CAN_RAW}, +// {FLEXCAN_ID_STD, SMFL_status_CANID, 0x7FF, PROTOCOL_CAN_RAW}, +// {FLEXCAN_ID_STD, SMFR_status_CANID, 0x7FF, PROTOCOL_CAN_RAW}, +// {FLEXCAN_ID_STD, SMRL_status_CANID, 0x7FF, PROTOCOL_CAN_RAW}, +// {FLEXCAN_ID_STD, SMRR_status_CANID, 0x7FF, PROTOCOL_CAN_RAW}, +// {FLEXCAN_ID_STD, SDM_Cmd_CANID, 0x7FF, PROTOCOL_CAN_RAW}, +// {FLEXCAN_ID_STD, VEH_VIN_CANID, 0x7FF, PROTOCOL_CAN_RAW}, +// {FLEXCAN_ID_STD, OCUFL_MSG_CANID, 0x7FF, PROTOCOL_CAN_RAW}, +// {FLEXCAN_ID_STD, OCUFR_MSG_CANID, 0x7FF, PROTOCOL_CAN_RAW}, +// {FLEXCAN_ID_STD, OCURL_MSG_CANID, 0x7FF, PROTOCOL_CAN_RAW}, +// {FLEXCAN_ID_STD, OCURR_MSG_CANID, 0x7FF, PROTOCOL_CAN_RAW}, +// {FLEXCAN_ID_STD, DW_STATE_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, FIU_CCU1_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, FIU_CCU2_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, FIU_CCU3_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, ESC_04_CANID, 0x7FF, PROTOCOL_CAN_RAW} +}; + +#define countIdCanFilterFifoCan0 1 +const FLEXCAN_RxMbFilterType IdCanFilterFifoCan0[countIdCanFilterFifoCan0] = { + {FLEXCAN_ID_STD, 0, 0} +}; + +/* +#if (CAN_DMA_EN == 1) +#define countIdCanFilterFifoCan0 7 +const FLEXCAN_RxMbFilterType IdCanFilterFifoCan0[countIdCanFilterFifoCan0] = { + {FLEXCAN_ID_STD, 0x100, 0x7FF}, + {FLEXCAN_ID_STD, 0x200, 0x7FF}, + {FLEXCAN_ID_STD, 0x300, 0x7FF}, + {FLEXCAN_ID_STD, 0x400, 0x7FF}, + {FLEXCAN_ID_STD, 0x500, 0x7FF}, + {FLEXCAN_ID_STD, Diag_To_CCU_CANID, 0x7FF}, + {FLEXCAN_ID_STD, Diag_Functional_CANID, 0x7FF} +}; +#endif +*/ + +#define countIdCanHardSoftFilterCan1 2 +const FilterTo_FLEXCAN_RxMbFilterType IdCanHardSoftFilterCan1[countIdCanHardSoftFilterCan1] = { + {FLEXCAN_ID_STD, XCP_CCU_RX_CANID, 0x7FF, PROTOCOL_CAN_XCP}, + {FLEXCAN_ID_STD, dbg_Cmd_Act_Information_CANID, 0x7FF, PROTOCOL_CAN_RAW} +}; + + +#if (CAN_DMA_EN == 1) +#define countIdCanFilterFifoCan1 1 +const FLEXCAN_RxMbFilterType IdCanFilterFifoCan1[countIdCanFilterFifoCan1] = { + {FLEXCAN_ID_STD, 0, 0} +}; +#endif + +bool vCanPort_InitCan0() { + vCanPort_InitCAN0RxTxPin(); + +#if (CAN_DMA_EN == 1) + bool result = vCanSerialPortFrameDMAInit( + &CAN_PORTS.Can0, + + FLEXCAN0, + 0, // CAN0 = 0 ... CAN3 = 3 + FlexCAN0_IRQn, // // FlexCAN0_IRQn ... FlexCAN3_IRQn + + 0xFF, + DMA_CHANNEL_0, + + DMA_REQ_FLEXCAN0, + + (uint8_t *) &g_aRxDataBufCan0[0], + size_aRxDataBuf, + + IdCanHardSoftFilterCan0, + countIdCanHardSoftFilterCan0, + + IdCanFilterFifoCan0, + countIdCanFilterFifoCan0, + + DMA0_IRQn, + 0xFF, + DMA0_IRQn, + + FLEXCAN_BAUD_500K, + FLEXCAN_ID_STD, + 0x55, + NULL, + NULL, + NULL, + NULL, + + DMA_TransferCompleteCallbackCan0, + NULL + ); +#else + + bool result = vCanSerialPortFrameMbInit( + &CAN_PORTS.Can0, + + FLEXCAN0, + 0, // CAN0 = 0 ... CAN3 = 3 + FlexCAN0_IRQn, // // FlexCAN0_IRQn ... FlexCAN3_IRQn + + 0xFF, + IdCanHardSoftFilterCan0, + countIdCanHardSoftFilterCan0, + + + FLEXCAN_BAUD_500K, + FLEXCAN_ID_STD, + 0x55, + CAN0_ErrorInterrupt_CallBack, + CAN0_RxInterrupt_CallBack, + CAN0_RxFifoInterrupt_CallBack, + NULL + ); + +#endif + + + return result; +} + + +static void vCanPort_InitCAN1RxTxPin() { + PORT_InitType tInitStruct = {0U}; + GPIO_InitType tGpioInitStruct = {0}; + + // CAN1_STB + // PortD 28: MUX = GPIO output + tInitStruct.u32PortPins = PORT_PIN_28; + tInitStruct.uPortPinMux.u32PortPinMode = PORT_GPIO_MODE; + PORT_InitPins(PORT_D, &tInitStruct); + tGpioInitStruct.u32GpioPins = PORT_PIN_28; + tGpioInitStruct.ePinDirection = GPIO_OUT; + tGpioInitStruct.ePinLevel = GPIO_LOW; + GPIO_InitPins(GPIO_D, &tGpioInitStruct); + + // PortA 12: MUX = ALT3, CAN1_RX + tInitStruct.u32PortPins = PORT_PIN_12; + tInitStruct.uPortPinMux.u32PortPinMode = PORTA_12_FLEXCAN1_RX; + tInitStruct.bPullEn = FALSE; + tInitStruct.ePullSel = PORT_PULL_UP; + PORT_InitPins(PORT_A, &tInitStruct); + tGpioInitStruct.u32GpioPins = PORT_PIN_12; + tGpioInitStruct.ePinDirection = GPIO_IN; + GPIO_InitPins((GPIO_InstanceType) PORT_A, &tGpioInitStruct); + + // PortA 13: MUX = ALT4, CAN1_TX + tInitStruct.u32PortPins = PORT_PIN_13; + tInitStruct.uPortPinMux.u32PortPinMode = PORTA_13_FLEXCAN1_TX; + PORT_InitPins(PORT_A, &tInitStruct); + tGpioInitStruct.u32GpioPins = PORT_PIN_13; + tGpioInitStruct.ePinDirection = GPIO_OUT; + tGpioInitStruct.ePinLevel = GPIO_HIGH; + GPIO_InitPins(GPIO_A, &tGpioInitStruct); +} + +bool vCanPort_InitCan1() { + + vCanPort_InitCAN1RxTxPin(); + +#if (CAN_DMA_EN == 1) + bool result = vCanSerialPortFrameDMAInit( + &CAN_PORTS.Can1, + + FLEXCAN1, + 1, // CAN0 = 0 ... CAN3 = 3 + FlexCAN1_IRQn, // // FlexCAN0_IRQn ... FlexCAN3_IRQn + + 0xFF, + DMA_CHANNEL_1, + + DMA_REQ_FLEXCAN1, + + (uint8_t *) &g_aRxDataBufCan1[0], + size_aRxDataBuf, + + IdCanHardSoftFilterCan1, + countIdCanHardSoftFilterCan1, + + IdCanFilterFifoCan1, + countIdCanFilterFifoCan1, + + DMA1_IRQn, + 0xFF, + DMA1_IRQn, + + FLEXCAN_BAUD_500K, + FLEXCAN_ID_STD, + 0x55, + NULL, + NULL, + NULL, + NULL, + + DMA_TransferCompleteCallbackCan1, + NULL + ); +#else + bool result = vCanSerialPortFrameMbInit( + &CAN_PORTS.Can1, + + FLEXCAN1, + 1, // CAN0 = 0 ... CAN3 = 3 + FlexCAN1_IRQn, // // FlexCAN0_IRQn ... FlexCAN3_IRQn + + 0xFF, + IdCanHardSoftFilterCan1, + countIdCanHardSoftFilterCan1, + + + FLEXCAN_BAUD_500K, + FLEXCAN_ID_STD, + 0x55, + CAN1_ErrorInterrupt_CallBack, + CAN1_RxInterrupt_CallBack, + CAN1_RxFifoInterrupt_CallBack, + NULL + ); + +#endif + return result; +} + + +void CanPorts_Init(tLoggerInterface *logger) { + CAN_PORTS.Can0.reInitOne = false; + bool result = vCanPort_InitCan0(); + if (result) { + LoggerInfoStatic(LOGGER, LOG_SIGN, "Initialization CAN0 - OK") + } else { + LoggerInfoStatic(LOGGER, LOG_SIGN, "Initialization CAN0 - ERROR") + } + CAN_PORTS.Can0_IO = CanPortFrame_GetIo(&CAN_PORTS.Can0); + + CAN_PORTS.Can1.reInitOne = false; + + result = vCanPort_InitCan1(); + if (result) { + LoggerInfoStatic(LOGGER, LOG_SIGN, "Initialization CAN1 - OK") + } else { + LoggerInfoStatic(LOGGER, LOG_SIGN, "Initialization CAN1 - ERROR") + } + CAN_PORTS.Can1_IO = CanPortFrame_GetIo(&CAN_PORTS.Can1); + +} + +void CAN0_IRQHandler(void) { + FLEXCAN_IRQHandler(0U); +} + +void CAN1_IRQHandler(void) { + FLEXCAN_IRQHandler(1U); +} + +void CAN2_IRQHandler(void) { + FLEXCAN_IRQHandler(2U); +} + +void CAN3_IRQHandler(void) { + FLEXCAN_IRQHandler(3U); +} + + +/* +#if (CAN_DMA_EN == 1) + +typedef struct { + uint32_t u32CanRAM[4]; +} Can_RamType; + +#define size_aRxDataBuf 16 +ALIGN(256) Can_RamType g_aRxDataBufCan0[size_aRxDataBuf]; // dma ring buffer size is 256 +ALIGN(256) Can_RamType g_aRxDataBufCan1[size_aRxDataBuf]; // dma ring buffer size is 256 + +static void DMA_TransferCompleteCallbackCan0(void) { + CanSerialPortFrameIrqRxProcessing(CAN_PORTS.Can0_IO.env, (uint32_t *) &g_aRxDataBufCan0[0]); +} + +static void DMA_TransferCompleteCallbackCan1(void) { + CanSerialPortFrameIrqRxProcessing(CAN_PORTS.Can1_IO.env, (uint32_t *) &g_aRxDataBufCan1[0]); +} +#else + +static void CAN0_ErrorInterrupt_CallBack(uint8_t u8CanIndex, FLEXCAN_ErrorInfoType *pErrorInfo) { + FLEXCAN_ClrErrorInfo(u8CanIndex, pErrorInfo); + PROCESS_UNUSED_VAR(u8CanIndex); + PROCESS_UNUSED_VAR(pErrorInfo); +} + +static void CAN0_RxInterrupt_CallBack(uint8_t u8CanIndex, FLEXCAN_RxMsgType *pRxCfg) { + CanSerialPortFrameIrqRxProcessingNO_DMA(CAN_PORTS.Can0_IO.env, pRxCfg); +} + +static void CAN0_RxFifoInterrupt_CallBack(uint8_t u8CanIndex, FLEXCAN_RxMsgType *pRxCfg) { + CanSerialPortFrameIrqRxProcessingNO_DMA(CAN_PORTS.Can0_IO.env, pRxCfg); +} + + +static void CAN1_ErrorInterrupt_CallBack(uint8_t u8CanIndex, FLEXCAN_ErrorInfoType *pErrorInfo) { + FLEXCAN_ClrErrorInfo(u8CanIndex, pErrorInfo); + PROCESS_UNUSED_VAR(u8CanIndex); + PROCESS_UNUSED_VAR(pErrorInfo); +} + +static void CAN1_RxInterrupt_CallBack(uint8_t u8CanIndex, FLEXCAN_RxMsgType *pRxCfg) { + CanSerialPortFrameIrqRxProcessingNO_DMA(CAN_PORTS.Can1_IO.env, pRxCfg); +} + +static void CAN1_RxFifoInterrupt_CallBack(uint8_t u8CanIndex, FLEXCAN_RxMsgType *pRxCfg) { + CanSerialPortFrameIrqRxProcessingNO_DMA(CAN_PORTS.Can1_IO.env, pRxCfg); +} + +#endif + + +//static void DMA_ErrorCallback(void) { +// while (1) { +// __asm("nop"); +// } +//} + +static void vCanPort_InitCAN0RxTxPin() { + PORT_InitType tInitStruct = {0U}; + GPIO_InitType tGpioInitStruct = {0}; + + // CAN0_STB + // PortC 30: MUX = GPIO output + tInitStruct.u32PortPins = PORT_PIN_30; + tInitStruct.uPortPinMux.u32PortPinMode = PORT_GPIO_MODE; + PORT_InitPins(PORT_C, &tInitStruct); + tGpioInitStruct.u32GpioPins = PORT_PIN_30; + tGpioInitStruct.ePinDirection = GPIO_OUT; + tGpioInitStruct.ePinLevel = GPIO_LOW; + GPIO_InitPins(GPIO_C, &tGpioInitStruct); + + // Port C2: MUX = ALT3, CAN0_RX + tInitStruct.u32PortPins = PORT_PIN_2; + tInitStruct.uPortPinMux.u32PortPinMode = PORTC_2_FLEXCAN0_RX; + tInitStruct.bPullEn = FALSE; + tInitStruct.ePullSel = PORT_PULL_UP; + PORT_InitPins(PORT_C, &tInitStruct); + tGpioInitStruct.u32GpioPins = PORT_PIN_2; + tGpioInitStruct.ePinDirection = GPIO_IN; + GPIO_InitPins((GPIO_InstanceType) PORT_C, &tGpioInitStruct); + + // Port C3: MUX = ALT3, CAN0_TX + tInitStruct.u32PortPins = PORT_PIN_3; + tInitStruct.uPortPinMux.u32PortPinMode = PORTC_3_FLEXCAN0_TX; + PORT_InitPins(PORT_C, &tInitStruct); + tGpioInitStruct.u32GpioPins = PORT_PIN_3; + tGpioInitStruct.ePinDirection = GPIO_OUT; + tGpioInitStruct.ePinLevel = GPIO_HIGH; + GPIO_InitPins(GPIO_C, &tGpioInitStruct); +} + +#define countIdCanHardSoftFilterCan0 31 +const FilterTo_FLEXCAN_RxMbFilterType IdCanHardSoftFilterCan0[countIdCanHardSoftFilterCan0] = { + {FLEXCAN_ID_STD, Diag_To_CCU_CANID, 0x7FF, PROTOCOL_CAN_UDS}, + {FLEXCAN_ID_STD, Diag_Functional_CANID, 0x7FF, PROTOCOL_CAN_UDS}, + {FLEXCAN_ID_STD, EMS_Veh_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, BCM_Powertrain_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, EMS_Veh_02_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, BCM_EEM_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, DMFR_Msg1_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, DMFL_Msg1_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, TM_Stat_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, TM_CP_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, HVC_CCU_Status_Msg_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, BCM_VEH_STATE_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, EMS_HVC_Req_Msg_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, HVC_Err_Status_Msg_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, BCM_CLIMATIC_DATA_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, VCU_CCU_Req_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, ESC_08_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, SMFL_status_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, SMFR_status_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, SMRL_status_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, SMRR_status_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, SDM_Cmd_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, VEH_VIN_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, OCUFL_MSG_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, OCUFR_MSG_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, OCURL_MSG_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, OCURR_MSG_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, DW_STATE_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, FIU_CCU1_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, FIU_CCU2_CANID, 0x7FF, PROTOCOL_CAN_RAW}, + {FLEXCAN_ID_STD, FIU_CCU3_CANID, 0x7FF, PROTOCOL_CAN_RAW} +}; + +#if (CAN_DMA_EN == 1) +#define countIdCanFilterFifoCan0 7 +const FLEXCAN_RxMbFilterType IdCanFilterFifoCan0[countIdCanFilterFifoCan0] = { + {FLEXCAN_ID_STD, 0x100, 0x7FF}, + {FLEXCAN_ID_STD, 0x200, 0x7FF}, + {FLEXCAN_ID_STD, 0x300, 0x7FF}, + {FLEXCAN_ID_STD, 0x400, 0x7FF}, + {FLEXCAN_ID_STD, 0x500, 0x7FF}, + {FLEXCAN_ID_STD, Diag_To_CCU_CANID, 0x7FF}, + {FLEXCAN_ID_STD, Diag_Functional_CANID, 0x7FF} +}; +#endif + + +#define countIdCanHardSoftFilterCan1 2 +const FilterTo_FLEXCAN_RxMbFilterType IdCanHardSoftFilterCan1[countIdCanHardSoftFilterCan1] = { + {FLEXCAN_ID_STD, Diag_To_CCU_CANID, 0x7FF, PROTOCOL_CAN_UDS}, + {FLEXCAN_ID_STD, Diag_Functional_CANID, 0x7FF, PROTOCOL_CAN_UDS}, +// {FLEXCAN_ID_STD, XCP_CCU_RX_CANID, 0x7FF, PROTOCOL_CAN_XCP}, +// {FLEXCAN_ID_STD, dbg_Cmd_Act_Information_CANID, 0x7FF, PROTOCOL_CAN_RAW} +}; + + +#if (CAN_DMA_EN == 1) +#define countIdCanFilterFifoCan1 7 +const FLEXCAN_RxMbFilterType IdCanFilterFifoCan1[countIdCanFilterFifoCan1] = { +// {FLEXCAN_ID_STD, 0, 0} + {FLEXCAN_ID_STD, 0x100, 0x7FF}, + {FLEXCAN_ID_STD, 0x200, 0x7FF}, + {FLEXCAN_ID_STD, 0x300, 0x7FF}, + {FLEXCAN_ID_STD, 0x400, 0x7FF}, + {FLEXCAN_ID_STD, 0x500, 0x7FF}, + {FLEXCAN_ID_STD, Diag_To_CCU_CANID, 0x7FF}, + {FLEXCAN_ID_STD, Diag_Functional_CANID, 0x7FF} +}; +#endif + +static bool vCanPort_InitCan0() { + vCanPort_InitCAN0RxTxPin(); + +#if (CAN_DMA_EN == 1) + bool result = vCanSerialPortFrameDMAInit( + &CAN_PORTS.Can0, + + FLEXCAN0, + 0, // CAN0 = 0 ... CAN3 = 3 + FlexCAN0_IRQn, // // FlexCAN0_IRQn ... FlexCAN3_IRQn + + 0xFF, + DMA_CHANNEL_0, + + DMA_REQ_FLEXCAN0, + + (uint8_t *) &g_aRxDataBufCan0[0], + size_aRxDataBuf, + + IdCanHardSoftFilterCan0, + countIdCanHardSoftFilterCan0, + + IdCanFilterFifoCan0, + countIdCanFilterFifoCan0, + + DMA0_IRQn, + 0xFF, + DMA0_IRQn, + + FLEXCAN_BAUD_500K, + FLEXCAN_ID_STD, + 0x55, + NULL, + NULL, + NULL, + NULL, + + DMA_TransferCompleteCallbackCan0, + NULL + ); +#else + + bool result = vCanSerialPortFrameMbInit( + &CAN_PORTS.Can0, + + FLEXCAN0, + 0, // CAN0 = 0 ... CAN3 = 3 + FlexCAN0_IRQn, // // FlexCAN0_IRQn ... FlexCAN3_IRQn + + 0xFF, + IdCanHardSoftFilterCan0, + countIdCanHardSoftFilterCan0, + + + FLEXCAN_BAUD_500K, + FLEXCAN_ID_STD, + 0x55, + CAN0_ErrorInterrupt_CallBack, + CAN0_RxInterrupt_CallBack, + CAN0_RxFifoInterrupt_CallBack, + NULL + ); + +#endif + + + return result; +} + + +static void vCanPort_InitCAN1RxTxPin() { + PORT_InitType tInitStruct = {0U}; + GPIO_InitType tGpioInitStruct = {0}; + + // CAN1_STB + // PortD 28: MUX = GPIO output + tInitStruct.u32PortPins = PORT_PIN_28; + tInitStruct.uPortPinMux.u32PortPinMode = PORT_GPIO_MODE; + PORT_InitPins(PORT_D, &tInitStruct); + tGpioInitStruct.u32GpioPins = PORT_PIN_28; + tGpioInitStruct.ePinDirection = GPIO_OUT; + tGpioInitStruct.ePinLevel = GPIO_LOW; + GPIO_InitPins(GPIO_D, &tGpioInitStruct); + + // PortA 12: MUX = ALT3, CAN1_RX + tInitStruct.u32PortPins = PORT_PIN_12; + tInitStruct.uPortPinMux.u32PortPinMode = PORTA_12_FLEXCAN1_RX; + tInitStruct.bPullEn = FALSE; + tInitStruct.ePullSel = PORT_PULL_UP; + PORT_InitPins(PORT_A, &tInitStruct); + tGpioInitStruct.u32GpioPins = PORT_PIN_12; + tGpioInitStruct.ePinDirection = GPIO_IN; + GPIO_InitPins((GPIO_InstanceType) PORT_A, &tGpioInitStruct); + + // PortA 13: MUX = ALT4, CAN1_TX + tInitStruct.u32PortPins = PORT_PIN_13; + tInitStruct.uPortPinMux.u32PortPinMode = PORTA_13_FLEXCAN1_TX; + PORT_InitPins(PORT_A, &tInitStruct); + tGpioInitStruct.u32GpioPins = PORT_PIN_13; + tGpioInitStruct.ePinDirection = GPIO_OUT; + tGpioInitStruct.ePinLevel = GPIO_HIGH; + GPIO_InitPins(GPIO_A, &tGpioInitStruct); +} + +static bool vCanPort_InitCan1() { + + vCanPort_InitCAN1RxTxPin(); + +#if (CAN_DMA_EN == 1) + bool result = vCanSerialPortFrameDMAInit( + &CAN_PORTS.Can1, + + FLEXCAN1, + 1, // CAN0 = 0 ... CAN3 = 3 + FlexCAN1_IRQn, // // FlexCAN0_IRQn ... FlexCAN3_IRQn + + 0xFF, + DMA_CHANNEL_1, + + DMA_REQ_FLEXCAN1, + + (uint8_t *) &g_aRxDataBufCan1[0], + size_aRxDataBuf, + + IdCanHardSoftFilterCan1, + countIdCanHardSoftFilterCan1, + + IdCanFilterFifoCan1, + countIdCanFilterFifoCan1, + + DMA1_IRQn, + 0xFF, + DMA1_IRQn, + + FLEXCAN_BAUD_500K, + FLEXCAN_ID_STD, + 0x55, + NULL, + NULL, + NULL, + NULL, + + DMA_TransferCompleteCallbackCan1, + NULL + ); +#else + bool result = vCanSerialPortFrameMbInit( + &CAN_PORTS.Can1, + + FLEXCAN1, + 1, // CAN0 = 0 ... CAN3 = 3 + FlexCAN1_IRQn, // // FlexCAN0_IRQn ... FlexCAN3_IRQn + + 0xFF, + IdCanHardSoftFilterCan1, + countIdCanHardSoftFilterCan1, + + + FLEXCAN_BAUD_500K, + FLEXCAN_ID_STD, + 0x55, + CAN1_ErrorInterrupt_CallBack, + CAN1_RxInterrupt_CallBack, + CAN1_RxFifoInterrupt_CallBack, + NULL + ); + +#endif + return result; +} + + +void CanPorts_Init(tLoggerInterface *logger) { + CAN_PORTS.Can0.reInit = false; + bool result = vCanPort_InitCan0(); + if (result) { + LoggerInfoStatic(LOGGER, LOG_SIGN, "Initialization CAN0 - OK") + } else { + LoggerInfoStatic(LOGGER, LOG_SIGN, "Initialization CAN0 - ERROR") + } + CAN_PORTS.Can0_IO = CanPortFrame_GetIo(&CAN_PORTS.Can0); + + CAN_PORTS.Can1.reInit = false; + + result = vCanPort_InitCan1(); + if (result) { + LoggerInfoStatic(LOGGER, LOG_SIGN, "Initialization CAN1 - OK") + } else { + LoggerInfoStatic(LOGGER, LOG_SIGN, "Initialization CAN1 - ERROR") + } + CAN_PORTS.Can1_IO = CanPortFrame_GetIo(&CAN_PORTS.Can1); + +} + +void CAN0_IRQHandler(void) { + FLEXCAN_IRQHandler(0U); +} + +void CAN1_IRQHandler(void) { + FLEXCAN_IRQHandler(1U); +} + +void CAN2_IRQHandler(void) { + FLEXCAN_IRQHandler(2U); +} + +void CAN3_IRQHandler(void) { + FLEXCAN_IRQHandler(3U); +} +*/ \ No newline at end of file diff --git a/MODULES/HVAC_M7_CanPorts/CanPorts.h b/MODULES/HVAC_M7_CanPorts/CanPorts.h new file mode 100644 index 0000000..543dc8c --- /dev/null +++ b/MODULES/HVAC_M7_CanPorts/CanPorts.h @@ -0,0 +1,37 @@ +// +// Created by cfif on 03.06.2024. +// + +#ifndef SMART_COMPONENTS_CANPORTS_H +#define SMART_COMPONENTS_CANPORTS_H + +#include "CanSerialPortFrame.h" +#include "LoggerInterface.h" + +#define CAN_DMA_EN 0 + +#define PROTOCOL_CAN_RAW 0 + +#define PROTOCOL_CAN_XCP 1 +#define PROTOCOL_CAN_ADR_XCP 0x6BB +#define PROTOCOL_CAN_TYPE_XCP 0x00 + +#define PROTOCOL_CAN_UDS 2 +#define PROTOCOL_CAN_ADR_UDS 0x7BB +#define PROTOCOL_CAN_TYPE_UDS 0x00 + + +typedef struct { + tCanSerialPortFrameFlagchip Can0; + tSerialPortFrameIO Can0_IO; + tCanSerialPortFrameFlagchip Can1; + tSerialPortFrameIO Can1_IO; +} tCanPorts; + +extern tCanPorts CAN_PORTS; + +void CanPorts_Init(tLoggerInterface *logger); +bool vCanPort_InitCan0(); +bool vCanPort_InitCan1(); + +#endif //SMART_COMPONENTS_CANPORTS_H diff --git a/MODULES/HVAC_M7_CanPorts/modular.json b/MODULES/HVAC_M7_CanPorts/modular.json new file mode 100644 index 0000000..0dd1901 --- /dev/null +++ b/MODULES/HVAC_M7_CanPorts/modular.json @@ -0,0 +1,10 @@ +{ + "cmake": { + "inc_dirs": [ + "./" + ], + "srcs": [ + "./**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_Command/CommandLines.c b/MODULES/HVAC_M7_Command/CommandLines.c new file mode 100644 index 0000000..759074e --- /dev/null +++ b/MODULES/HVAC_M7_Command/CommandLines.c @@ -0,0 +1,72 @@ +// +// Created by cfif on 05.04.2024. +// +#include +#include "CommandLines.h" +#include "CmsisRtosThreadUtils.h" +#include "stdio.h" +#include "CliCmd.h" +#include +#include "math.h" +#include "stdlib.h" +#include "fc7xxx_driver_rgm.h" + + +int32_t CliCmd_baseCommandHelp(void *env, tCliCmd *cli) { + CliCmd_PrintLnStatic(cli, "================================================"); + CliCmd_PrintLnStatic(cli, "Commands:"); + CliCmd_PrintLnStatic(cli, ""); + CliCmd_PrintLnStatic(cli, "reboot - Restarting the device"); + CliCmd_PrintLnStatic(cli, "mem - Memory Information"); + CliCmd_PrintLnStatic(cli, "================================================"); + + return 0; +} + +int32_t CliCmd_baseCommandReboot(void *env, tCliCmd *cli) { + NVIC_SystemReset(); + return 0; +} + + +void CommandLine_Init(tCommandLine *env, tLoggerToSerialPort *loggerToSerialPort, tSerialPortIO *cliVirtualPortIn_Io, + tSerialPortIO *cliVirtualPortOut_Io) { + + env->loggerToSerialPort = loggerToSerialPort; + + CliCmd_InitStatic(&env->cmd, loggerToSerialPort, cliVirtualPortIn_Io, cliVirtualPortOut_Io, env->mem.cmdRxLine); + CliRedirectionTable_InitStatic(&env->redirectTable, env->mem.commandPrefixes); + + CliRedirectionTable_RecAddStatic(&env->redirectTable, "help", CliCmd_baseCommandHelp, NULL); + CliRedirectionTable_RecAddStatic(&env->redirectTable, "mem", vTaskGetRunTime, env); + CliRedirectionTable_RecAddStatic(&env->redirectTable, "reboot", CliCmd_baseCommandReboot, NULL); + + + InitThreadAtrStatic(&env->thread.attr, "CommandLine", env->thread.controlBlock, env->thread.stack, + osPriorityNormal); +} + +void ListenCLICommand(tCommandLine *env) { + CliCmd_WaitLine(&env->cmd); + if (CliRedirectionTable_ProcessCmd(&env->redirectTable, &env->cmd) != 0) { + CliCmd_PrintStatic(&env->cmd, "Command "); + CliCmd_Print(&env->cmd, env->cmd.rxLine.begin, env->cmd.rxLine.length - 1); + CliCmd_PrintLnStatic(&env->cmd, " not found"); + + CliCmd_PrintLnStatic(&env->cmd, "Enter the command [ help ] for more information\n"); + + } +} + +static _Noreturn void CommandLine_Thread(tCommandLine *env) { + for (;;) { + ListenCLICommand(env); + SystemDelayMs(100); + } +} + +void CommandLine_StartThread(tCommandLine *env) { + if (!env->thread.id) { + env->thread.id = osThreadNew((osThreadFunc_t) (CommandLine_Thread), (void *) (env), &env->thread.attr); + } +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_Command/CommandLines.h b/MODULES/HVAC_M7_Command/CommandLines.h new file mode 100644 index 0000000..4bb4d1f --- /dev/null +++ b/MODULES/HVAC_M7_Command/CommandLines.h @@ -0,0 +1,42 @@ +// +// Created by cfif on 05.04.2024. +// + +#ifndef WATER_BLACKBOX2_G_COMMANDLINES_H +#define WATER_BLACKBOX2_G_COMMANDLINES_H + +#include +#include "SerialPort.h" +#include "CliCmd.h" +#include "CliRedirectTable.h" +#include "LoggerToSerialPort.h" + +typedef struct { + + struct { + tCliRedirectItem commandPrefixes[10]; + uint8_t cmdRxLine[128]; + } mem; + + tCliCmd cmd; + + tCliRedirectTable redirectTable; + + tLoggerToSerialPort *loggerToSerialPort; + + struct { + osThreadId_t id; + uint32_t stack[400]; + StaticTask_t controlBlock; + osThreadAttr_t attr; + } thread; + +} tCommandLine; + +int32_t vTaskGetRunTime(void *env, tCliCmd *cli); + +void CommandLine_Init(tCommandLine *env, tLoggerToSerialPort *loggerToSerialPort, tSerialPortIO *cliVirtualPortIn_Io, + tSerialPortIO *cliVirtualPortOut_Io); +void CommandLine_StartThread(tCommandLine *env); + +#endif //WATER_BLACKBOX2_G_COMMANDLINES_H diff --git a/MODULES/HVAC_M7_Command/TasksInfo.c b/MODULES/HVAC_M7_Command/TasksInfo.c new file mode 100644 index 0000000..9471274 --- /dev/null +++ b/MODULES/HVAC_M7_Command/TasksInfo.c @@ -0,0 +1,50 @@ +// +// Created by cfif on 17.12.2024. +// +#include +#include +#include "CommandLines.h" +#include "CliRedirectTable.h" +#include "CmsisRtosThreadUtils.h" +#include "LoggerInterface.h" + +char bufSprintf[1024]; + +int32_t vTaskGetRunTime(void *env, tCliCmd *cli) { + tCommandLine *envCommandLine = env; + + volatile UBaseType_t uxArraySize, x; + + uxArraySize = uxTaskGetNumberOfTasks(); + + TaskStatus_t pxTaskStatusArray[uxArraySize]; + + + uxArraySize = uxTaskGetSystemState((void *) pxTaskStatusArray, uxArraySize, NULL); + + uint16_t p = 1; + bufSprintf[0] = '\n'; + + for (x = 0; x < uxArraySize; x++) { + + sprintf(&bufSprintf[p], "%lu\t%d\t%s\n", + pxTaskStatusArray[x].xTaskNumber, + pxTaskStatusArray[x].usStackHighWaterMark, + pxTaskStatusArray[x].pcTaskName); + + p = strlen(bufSprintf); + + } + + CliCmd_Print(cli, bufSprintf, p); + + sprintf(bufSprintf, "Free Heap Size = %u bytes\n", (unsigned int)xPortGetFreeHeapSize()); + p = strlen(bufSprintf); + CliCmd_Print(cli, bufSprintf, p); + + sprintf(bufSprintf, "Free Logger Buf Size = %u\n", MAX_COUNT_BUF_LOG - (unsigned int)envCommandLine->loggerToSerialPort->countBufLoggerNames); + p = strlen(bufSprintf); + CliCmd_Print(cli, bufSprintf, p); + + return 0; +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_Command/modular.json b/MODULES/HVAC_M7_Command/modular.json new file mode 100644 index 0000000..58898fe --- /dev/null +++ b/MODULES/HVAC_M7_Command/modular.json @@ -0,0 +1,22 @@ +{ + "dep": [ + { + "type": "local", + + "dir": "./MODULES/CliCmd" + }, + { + "type": "local", + + "dir": "./MODULES/CliCmd_RedirectTable" + } + ], + "cmake": { + "inc_dirs": [ + "./" + ], + "srcs": [ + "./**.c" + ] + } +} diff --git a/MODULES/HVAC_M7_DOC/FC7240 Reference Manual_V0.2.pdf b/MODULES/HVAC_M7_DOC/FC7240 Reference Manual_V0.2.pdf new file mode 100755 index 0000000..6272155 Binary files /dev/null and b/MODULES/HVAC_M7_DOC/FC7240 Reference Manual_V0.2.pdf differ diff --git a/MODULES/HVAC_M7_DOC/FC7240_IO_Signal_Description_Input_Multiplexing - 副本.xlsx b/MODULES/HVAC_M7_DOC/FC7240_IO_Signal_Description_Input_Multiplexing - 副本.xlsx new file mode 100755 index 0000000..d884fa4 Binary files /dev/null and b/MODULES/HVAC_M7_DOC/FC7240_IO_Signal_Description_Input_Multiplexing - 副本.xlsx differ diff --git a/MODULES/HVAC_M7_DOC/HVAC v3 04.05.2026 (Рома).pdf b/MODULES/HVAC_M7_DOC/HVAC v3 04.05.2026 (Рома).pdf new file mode 100644 index 0000000..f9b35b0 Binary files /dev/null and b/MODULES/HVAC_M7_DOC/HVAC v3 04.05.2026 (Рома).pdf differ diff --git a/MODULES/HVAC_M7_DOC/ISO 14229-1-2013 ТД. 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+ +#endif //HVAC_DATANONVOLATATILE_PRIVATE_H diff --git a/MODULES/HVAC_M7_DataNonVolatile/DataNonVolatile.c b/MODULES/HVAC_M7_DataNonVolatile/DataNonVolatile.c new file mode 100644 index 0000000..945a273 --- /dev/null +++ b/MODULES/HVAC_M7_DataNonVolatile/DataNonVolatile.c @@ -0,0 +1,20 @@ +// +// Created by CFIF on 05.04.24. +// +#include +#include "DataNonVolatatile_Private.h" +#include "Rs_Cal_0_SedanL.h" +#include "Rs_Cal_1_SedanH.h" +#include "Rs_Cal_2_Limo.h" +#include "Rs_Cal_3_Suv.h" +#include "Rs_Cal_4_Mpv.h" + +void DeviceDataParam_InitDefaults(tDeviceDataNonVolatile *env) { + DeviceStorageInitDeviceSettings(&env->device); + env->version_param = DEVICE_DATA_VERSION_PARAM; +} + +void DeviceDataCalib_InitDefaults(tDeviceDataNonVolatile *env) { + Rs_Cal_0_SedanL(); + env->version_calib = DEVICE_DATA_VERSION_CALIB; +} diff --git a/MODULES/HVAC_M7_DataNonVolatile/DataNonVolatile.h b/MODULES/HVAC_M7_DataNonVolatile/DataNonVolatile.h new file mode 100644 index 0000000..68e4e76 --- /dev/null +++ b/MODULES/HVAC_M7_DataNonVolatile/DataNonVolatile.h @@ -0,0 +1,111 @@ +// +// Created by CFIF on 20.10.25. +// + +#ifndef HVAC_DEVICEDATANONVOLATILE_H +#define HVAC_DEVICEDATANONVOLATILE_H + +#include "DataRuntime.h" +#include "HVAC_preDefine.h" + +#define DEVICE_DATA_VERSION_CALIB 0x01 +#define DEVICE_DATA_VERSION_PARAM 0x02 + +// BCD в двоичное число +#define bcd_to_binary(bcd) (((bcd >> 4) * 10) + (bcd & 0x0F)) + +// Двоичное число в BCD +#define binary_to_bcd(binary) (((binary / 10) << 4) | (binary % 10)) + +typedef struct __attribute__ ((packed)) { + uint8_t year; // BCD: 0x18 = 2018 год + uint8_t month; // BCD: 0x10 = октябрь + uint8_t day; // BCD: 0x16 = 16 число + char tester_serial[9]; // ASCII: "123456789" +} tFingerprint; + +typedef struct __attribute__ ((packed)) { + uint8_t ModuleID; // ModuleID + char testerCode[9]; // ASCII: "123456789" + uint8_t year; // BCD: 0x18 = 2018 год + uint8_t month; // BCD: 0x10 = октябрь + uint8_t day; // BCD: 0x16 = 16 число +} tFingerprintDev; + + +typedef struct { + uint8_t year; + uint8_t month; + uint8_t day; + uint8_t revision; +} tVersionDateRevision; + +typedef struct { + tVersionDateRevision SW; + tVersionDateRevision MDB; +} tInternal_SW_Version; + +typedef enum { + AROMA_NOT_PRESENT = 0, + AROMA_PRESENT = 1, + AROMA_DEFAULT = 0xFF +} eAromaConfiguration; + +typedef enum { + ALG_STANDART = 0, + ALG_LIMOUSINE = 1, + ALG_DEFAULT = 0xFF +} eAlgorithmConfiguration; + +typedef enum { + REAR_HVAC_NOT_PRESENT = 0, + REAR_HVAC_PRESENT = 1, + REAR_HVAC_DEFAULT = 0xFF +} eRearHVACConfiguration; + +typedef struct __attribute__ ((packed)) { + eAromaConfiguration AromaConfiguration; + eAlgorithmConfiguration AlgorithmConfiguration; + eRearHVACConfiguration RearHVACConfiguration; +} tStatus_CCU_Configuration; + +typedef struct { + tInternal_SW_Version Internal_SW_Version; + char Software_classification_identification[15]; + tFingerprint Tester_Fingerprint; + tFingerprintDev Boot_SW_Fingerprint; + tFingerprintDev Application_SW_Fingerprint; + char Spare_Part_Number[27]; + char Serial_Number[26]; + char Vehicle_Identification[17]; + char ECU_hardware_number_NAMI[27]; + char ECU_hardware_number_ECU_supplier[13]; + char ECU_software_number_ECU_supplier[2]; + char ECU_boot_software_identification_ECU_supplier[2]; + tStatus_CCU_Configuration Status_CCU_Configuration; +} ecu_identification_t; + +typedef struct __attribute__ ((packed)) { + uint8_t meta_fw_name_size; + char meta_fw_name[9]; + tVersionDateRevision HW; + tInternal_SW_Version internal_SW_Version; + tFingerprintDev fingerprint; +} tFirmwareMetaMap; + +typedef struct { + ecu_identification_t identification; +} tDeviceSettings; + + +typedef struct { + uint32_t version_param; + uint32_t version_calib; + tDeviceSettings device; +} tDeviceDataNonVolatile; + +void DeviceDataParam_InitDefaults(tDeviceDataNonVolatile *env); + +void DeviceDataCalib_InitDefaults(tDeviceDataNonVolatile *env); + +#endif //HVAC_DEVICEDATANONVOLATILE_H diff --git a/MODULES/HVAC_M7_DataNonVolatile/DataNonVolatile_InitDeviceSetting.c b/MODULES/HVAC_M7_DataNonVolatile/DataNonVolatile_InitDeviceSetting.c new file mode 100644 index 0000000..385b5a7 --- /dev/null +++ b/MODULES/HVAC_M7_DataNonVolatile/DataNonVolatile_InitDeviceSetting.c @@ -0,0 +1,27 @@ +// +// Created by CFIF on 05.04.24. +// +#include "DataNonVolatatile_Private.h" +#include "memory.h" + +void DeviceStorageInitDeviceSettings(tDeviceSettings *env) { + + env->identification.Tester_Fingerprint.year = 0x18; + env->identification.Tester_Fingerprint.month = 0x10; + env->identification.Tester_Fingerprint.day = 0x16; + memcpy(&env->identification.Tester_Fingerprint.tester_serial, "123456789", + sizeof(env->identification.Tester_Fingerprint.tester_serial)); + + memset(&env->identification.Status_CCU_Configuration, 0xFF, sizeof(tStatus_CCU_Configuration)); + +/* + env->identification.Software_classification_identification[15]; + env->identification.Spare_Part_Number[27]; + env->identification.Serial_Number[26]; + env->identification.Vehicle_Identification[17]; + env->identification.ECU_hardware_number_NAMI[13]; + env->identification.ECU_hardware_number_ECU_supplier[2]; + env->identification.ECU_software_number_ECU_supplier[2]; + env->identification.ECU_boot_software_identification_ECU_supplier[2]; +*/ +} diff --git a/MODULES/HVAC_M7_DataNonVolatile/HVAC_preDefine.h b/MODULES/HVAC_M7_DataNonVolatile/HVAC_preDefine.h new file mode 100644 index 0000000..e351bec --- /dev/null +++ b/MODULES/HVAC_M7_DataNonVolatile/HVAC_preDefine.h @@ -0,0 +1,31 @@ +// +// Created by cfif on 08.08.2025. +// + +#ifndef SIMULINK_HVAC_PREDEFINE_H +#define SIMULINK_HVAC_PREDEFINE_H + +#include +#include + +#define SECT_SRAM_CAL __attribute__((section (".caldata"))) +#define SECT_FLASH_CAL __attribute__((section (".caltext"))) +#define SECT_SRAM_NVM __attribute__((section (".nvmdata"))) + +#define SECT_VEH_CAL_0 SECT_FLASH_CAL +#define SECT_VEH_CAL_1 SECT_FLASH_CAL +#define SECT_VEH_CAL_2 SECT_FLASH_CAL +#define SECT_VEH_CAL_3 SECT_FLASH_CAL +#define SECT_VEH_CAL_4 SECT_FLASH_CAL + +#define tU08 uint8_t +#define tU16 uint16_t +#define tS16 int16_t +#define tS08 int8_t + +#define M_MEMCOPY(dest, src) memcpy(dest, src, sizeof(dest)) + +#define ID_TRUE 1 +#define ID_FALSE 0 + +#endif //SIMULINK_HVAC_PREDEFINE_H diff --git a/MODULES/HVAC_M7_DataNonVolatile/Rs_Cal_Base.c b/MODULES/HVAC_M7_DataNonVolatile/Rs_Cal_Base.c new file mode 100644 index 0000000..a9adf2e --- /dev/null +++ b/MODULES/HVAC_M7_DataNonVolatile/Rs_Cal_Base.c @@ -0,0 +1,1109 @@ +/** Doxygen: File brief + ****************************************************************************** + * @file Rs_Cal_Base.c + * @brief No brief + * @remark Generated by C:\9999\Rs_Cal_R23_ver21_SedanL.xlsm + * Generated on yyyy-mm-dd hh:mm:ss + *****************************************************************************/ +/****************************************************************************** + * INCLUDE FILES + *****************************************************************************/ +#include "Rs_Cal_Base.h" + +/****************************************************************************** + * MACRO DECLARATIONS + *****************************************************************************/ +/*PRQA S 0615 EOF #suppress : More than 511 block scope identifiers, from Calibration data table, No impact*/ +/*PRQA S 1514 EOF #suppress : In the same translation(used != defined), from Calibration data table, No impact*/ +/*PRQA S 3408 EOF #suppress : To manage Cal. data separately, from Calibration data table, No Impact*/ +/****************************************************************************** + * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS) + *****************************************************************************/ +/****************************************************************************** + * GLOBAL VARIABLES DECLARATIONS + *****************************************************************************/ +SECT_SRAM_CAL tU08 g_ucCalFromRelease = ID_FALSE; +SECT_SRAM_CAL tU08 g_aucCAL_FP_DATE[3] = { 0}; +SECT_SRAM_CAL tU08 g_aucCAL_VERSION[2] = { 0}; +SECT_SRAM_CAL tU08 g_ucCAL_VARIANT = 0; +/* ------------------------------------------Cal Version : End*/ +SECT_SRAM_CAL tU16 g_ausSET_TEMP_FULL[13] = { 0}; +SECT_SRAM_CAL tU16 g_ausSET_TEMP_HALF[7] = { 0}; +/* ------------------------------------------Set Temp : End*/ +SECT_SRAM_CAL tS16 g_assINCAR_TG_FL_LV0[13] = { 0}; +SECT_SRAM_CAL tS16 g_assINCAR_TG_FR_LV0[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_FL_LV0[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_FR_LV0[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_MIN_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_MAX_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y3_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y4_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X3_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X4_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_Y1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_Y2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_X1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_X2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_Y1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_Y2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_X1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_X2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FLU_LV0[13] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FRU_LV0[13] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_MIN_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_MAX_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y3_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y4_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X3_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X4_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FLL_LV0[13] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FRL_LV0[13] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_MIN_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_MAX_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y3_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y4_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X3_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X4_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assINCAR_TG_RL_LV0[13] = { 0}; +SECT_SRAM_CAL tS16 g_assINCAR_TG_RR_LV0[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_RL_LV0[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_RR_LV0[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_MIN_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_MAX_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y3_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y4_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X3_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X4_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_Y1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_Y2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_X1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_X2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_Y1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_Y2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_X1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_X2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_RL_LV0[13] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_RR_LV0[13] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_MIN_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_MAX_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y3_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y4_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X3_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X4_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X1_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X2_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FR_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FL_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_RATE_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_MAX_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FR_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FL_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_RATE_LV0[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_MAX_LV0[7] = { 0}; +/* ------------------------------------------Lv0 : End*/ +SECT_SRAM_CAL tS16 g_assINCAR_TG_FL_LV1[13] = { 0}; +SECT_SRAM_CAL tS16 g_assINCAR_TG_FR_LV1[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_FL_LV1[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_FR_LV1[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_MIN_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_MAX_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y3_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y4_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X3_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X4_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_Y1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_Y2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_X1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_X2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_Y1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_Y2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_X1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_X2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FLU_LV1[13] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FRU_LV1[13] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_MIN_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_MAX_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y3_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y4_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X3_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X4_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FLL_LV1[13] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FRL_LV1[13] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_MIN_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_MAX_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y3_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y4_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X3_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X4_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assINCAR_TG_RL_LV1[13] = { 0}; +SECT_SRAM_CAL tS16 g_assINCAR_TG_RR_LV1[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_RL_LV1[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_RR_LV1[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_MIN_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_MAX_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y3_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y4_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X3_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X4_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_Y1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_Y2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_X1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_X2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_Y1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_Y2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_X1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_X2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_RL_LV1[13] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_RR_LV1[13] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_MIN_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_MAX_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y3_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y4_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X3_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X4_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X1_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X2_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FR_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FL_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_RATE_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_MAX_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FR_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FL_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_RATE_LV1[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_MAX_LV1[7] = { 0}; +/* ------------------------------------------Lv1 : End*/ +SECT_SRAM_CAL tS16 g_assINCAR_TG_FL_LV2[13] = { 0}; +SECT_SRAM_CAL tS16 g_assINCAR_TG_FR_LV2[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_FL_LV2[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_FR_LV2[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_MIN_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_MAX_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y3_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y4_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X3_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X4_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_Y1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_Y2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_X1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_X2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_Y1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_Y2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_X1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_X2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FLU_LV2[13] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FRU_LV2[13] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_MIN_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_MAX_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y3_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y4_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X3_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X4_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FLL_LV2[13] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FRL_LV2[13] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_MIN_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_MAX_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y3_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y4_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X3_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X4_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assINCAR_TG_RL_LV2[13] = { 0}; +SECT_SRAM_CAL tS16 g_assINCAR_TG_RR_LV2[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_RL_LV2[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_RR_LV2[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_MIN_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_MAX_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y3_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y4_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X3_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X4_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_Y1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_Y2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_X1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_X2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_Y1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_Y2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_X1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_X2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_RL_LV2[13] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_RR_LV2[13] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_MIN_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_MAX_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y3_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y4_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X3_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X4_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X1_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X2_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FR_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FL_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_RATE_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_MAX_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FR_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FL_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_RATE_LV2[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_MAX_LV2[7] = { 0}; +/* ------------------------------------------Lv2 : End*/ +SECT_SRAM_CAL tS16 g_assINCAR_TG_FL_LV3[13] = { 0}; +SECT_SRAM_CAL tS16 g_assINCAR_TG_FR_LV3[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_FL_LV3[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_FR_LV3[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_MIN_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_MAX_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y3_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y4_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X3_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X4_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_Y1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_Y2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_X1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_X2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_Y1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_Y2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_X1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_X2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FLU_LV3[13] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FRU_LV3[13] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_MIN_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_MAX_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y3_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y4_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X3_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X4_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FLL_LV3[13] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FRL_LV3[13] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_MIN_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_MAX_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y3_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y4_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X3_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X4_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assINCAR_TG_RL_LV3[13] = { 0}; +SECT_SRAM_CAL tS16 g_assINCAR_TG_RR_LV3[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_RL_LV3[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_RR_LV3[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_MIN_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_MAX_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y3_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y4_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X3_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X4_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_Y1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_Y2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_X1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_X2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_Y1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_Y2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_X1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_X2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_RL_LV3[13] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_RR_LV3[13] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_MIN_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_MAX_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y3_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y4_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X3_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X4_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X1_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X2_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FR_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FL_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_RATE_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_MAX_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FR_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FL_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_RATE_LV3[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_MAX_LV3[7] = { 0}; +/* ------------------------------------------Lv3 : End*/ +SECT_SRAM_CAL tS16 g_assINCAR_TG_FL_LV4[13] = { 0}; +SECT_SRAM_CAL tS16 g_assINCAR_TG_FR_LV4[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_FL_LV4[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_FR_LV4[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_MIN_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_MAX_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y3_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y4_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X3_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X4_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_Y1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_Y2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_X1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_X2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_Y1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_Y2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_X1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_X2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FLU_LV4[13] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FRU_LV4[13] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_MIN_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_MAX_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y3_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y4_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X3_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X4_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FLL_LV4[13] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FRL_LV4[13] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_MIN_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_MAX_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y3_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y4_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X3_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X4_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assINCAR_TG_RL_LV4[13] = { 0}; +SECT_SRAM_CAL tS16 g_assINCAR_TG_RR_LV4[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_RL_LV4[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_RR_LV4[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_MIN_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_MAX_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y3_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y4_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X3_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X4_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_Y1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_Y2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_X1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_X2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_Y1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_Y2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_X1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_X2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_RL_LV4[13] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_RR_LV4[13] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_MIN_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_MAX_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y3_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y4_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X3_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X4_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X1_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X2_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FR_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FL_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_RATE_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_MAX_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FR_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FL_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_RATE_LV4[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_MAX_LV4[7] = { 0}; +/* ------------------------------------------Lv4 : End*/ +SECT_SRAM_CAL tS16 g_assINCAR_TG_FL_LV5[13] = { 0}; +SECT_SRAM_CAL tS16 g_assINCAR_TG_FR_LV5[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_FL_LV5[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_FR_LV5[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_MIN_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_MAX_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y3_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_Y4_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X3_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_INC_X4_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_Y1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_Y2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_X1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_AMB_X2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_Y1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_Y2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_X1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVF_SUN_X2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FLU_LV5[13] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FRU_LV5[13] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_MIN_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_MAX_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y3_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y4_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X3_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X4_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FLL_LV5[13] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_FRL_LV5[13] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_MIN_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_MAX_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y3_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y4_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X3_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X4_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assINCAR_TG_RL_LV5[13] = { 0}; +SECT_SRAM_CAL tS16 g_assINCAR_TG_RR_LV5[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_RL_LV5[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVTG_RR_LV5[13] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_MIN_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_MAX_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y3_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_Y4_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X3_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_INC_X4_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_Y1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_Y2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_X1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_AMB_X2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_Y1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_Y2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_X1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assVR_SUN_X2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_RL_LV5[13] = { 0}; +SECT_SRAM_CAL tS16 g_assTG_RR_LV5[13] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_MIN_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_MAX_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y3_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y4_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X3_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_INC_X4_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X1_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X2_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FR_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FL_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_RATE_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_MAX_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FR_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FL_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_RATE_LV5[7] = { 0}; +SECT_SRAM_CAL tS16 g_assCORRECT_AF_MAX_LV5[7] = { 0}; +/* ------------------------------------------Lv5 : End*/ +SECT_SRAM_CAL tS16 g_assDUCT_TGT_DEF_VALVE_L[11] = { 0}; +SECT_SRAM_CAL tS16 g_assDUCT_TGT_DEF_VALVE_R[11] = { 0}; +/* ------------------------------------------DuctTgt Increase : End*/ +SECT_SRAM_CAL tS16 g_assAMB_LV_UP[5] = { 0}; +SECT_SRAM_CAL tS16 g_assAMB_LV_DN[5] = { 0}; +SECT_SRAM_CAL tS16 g_assAMB_LV_TG[6] = { 0}; +/* ------------------------------------------Ambient LEVEL : End*/ +SECT_SRAM_CAL tU08 g_aucMODE_BY_SET_F_LV0[13] = { 0}; +SECT_SRAM_CAL tU08 g_aucMODE_BY_SET_F_LV1[13] = { 0}; +SECT_SRAM_CAL tU08 g_aucMODE_BY_SET_F_LV2[13] = { 0}; +SECT_SRAM_CAL tU08 g_aucMODE_BY_SET_F_LV3[13] = { 0}; +SECT_SRAM_CAL tU08 g_aucMODE_BY_SET_F_LV4[13] = { 0}; +SECT_SRAM_CAL tU08 g_aucMODE_BY_SET_F_LV5[13] = { 0}; +SECT_SRAM_CAL tU16 g_ausMODE_BY_DUCT_TG_R_LV0[7] = { 0}; +SECT_SRAM_CAL tU16 g_ausMODE_BY_DUCT_TG_R_LV1[7] = { 0}; +SECT_SRAM_CAL tU16 g_ausMODE_BY_DUCT_TG_R_LV2[7] = { 0}; +SECT_SRAM_CAL tU16 g_ausMODE_BY_DUCT_TG_R_LV3[7] = { 0}; +SECT_SRAM_CAL tU16 g_ausMODE_BY_DUCT_TG_R_LV4[7] = { 0}; +SECT_SRAM_CAL tU16 g_ausMODE_BY_DUCT_TG_R_LV5[7] = { 0}; +/* ------------------------------------------Mode depend on SET for each level : End*/ +SECT_SRAM_CAL tS16 g_ssPREC_REC_ON_AMB = 0; +SECT_SRAM_CAL tS16 g_ssPREC_REC_OFF_AMB = 0; +SECT_SRAM_CAL tU08 g_aucPREC_VEH_SPD_OSA[13] = { 0}; +SECT_SRAM_CAL tS16 g_assPRE_AMB_RANGE_WINTER[7] = { 0}; +SECT_SRAM_CAL tU08 g_aucPREC_OSA_WINTER[7] = { 0}; +SECT_SRAM_CAL tU08 g_aucPREC_REC_WINTER[7] = { 0}; +SECT_SRAM_CAL tU16 g_ausPREC_HUMIDITY_NOK[7] = { 0}; +SECT_SRAM_CAL tU16 g_ausPREC_HUMIDITY_OK[7] = { 0}; +SECT_SRAM_CAL tU16 g_ausPREC_ENTRY_RPM[3] = { 0}; +SECT_SRAM_CAL tU16 g_ausPREC_EXIT_RPM[3] = { 0}; +SECT_SRAM_CAL tU16 g_ausPREC_COMP_SPD_1[3] = { 0}; +SECT_SRAM_CAL tU08 g_aucPREC_OSA_SUMMER_1[3] = { 0}; +SECT_SRAM_CAL tU08 g_aucPREC_REC_SUMMER_1[3] = { 0}; +SECT_SRAM_CAL tS16 g_assPREC_EVA_DIFF_FB_TG_F[7] = { 0}; +SECT_SRAM_CAL tU08 g_aucPREC_OSA_SUMMER_2[7] = { 0}; +SECT_SRAM_CAL tU08 g_aucPREC_REC_SUMMER_2[7] = { 0}; +SECT_SRAM_CAL tU08 g_aucPREC_EVA_DIFF[4] = { 0}; +SECT_SRAM_CAL tU08 g_ucPREC_OSA_SUMMER_3 = 0; +SECT_SRAM_CAL tU08 g_ucPREC_REC_SUMMER_3 = 0; +/* ------------------------------------------AutoRec : End*/ +SECT_SRAM_CAL tU16 g_ausFLOW_FR_VE2VALVE[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_BIVALVE[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_BI2VALVE[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_AF2VALVE[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_AF2VALVE_SUMMER[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_FO2VALVE[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_FD2VALVE[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_DE2VALVE[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_TR2VALVE[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_HI2VALVE[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_BIVALVE_MANUAL[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_RE_VENT[6] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_RE_BI2VALVE[6] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_RE_FO2VALVE[6] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_RE_VENT_2[6] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_RE_BI2VALVE_2[6] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_RE_VENT_3[6] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_RE_BI2VALVE_3[6] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_RE_VENT_MANUAL[6] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_RE_BI2VALVE_MANUAL[6] = { 0}; +/* ------------------------------------------Flow Control Valve: End*/ +SECT_SRAM_CAL tS16 g_assFLOW_BI_AMB_TGT[6] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_BI_VENT_PLUS[12] = { 0}; +SECT_SRAM_CAL tS16 g_assFLOW_BI_TEMP_TGT[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_BI_FOOT_PLUS[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_BI_VENT_VALVE_MAX[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_BI_FOOT_VALVE_MAX[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_BI_VENT_VALVE_MIN[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_BI_FOOT_VALVE_MIN[12] = { 0}; +/* ------------------------------------------Bi 2 level conditions: End*/ +SECT_SRAM_CAL tS16 g_assFLOW_B2I_AMB_TGT[6] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_BI2_VENT_PLUS[12] = { 0}; +SECT_SRAM_CAL tS16 g_assFLOW_BI2_TEMP_TGT[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_BI2_FOOT_PLUS[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_BI2_VENT_VALVE_MAX[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_BI2_FOOT_VALVE_MAX[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_BI2_VENT_VALVE_MIN[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_BI2_FOOT_VALVE_MIN[12] = { 0}; +/* ------------------------------------------AF level conditions: End*/ +SECT_SRAM_CAL tS16 g_assFLOW_AF_AMB_TGT[6] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_AF_VENT_PLUS[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_AF_BLR_AF_TGT[6] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_AF_FOOT_PLUS[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_AF_VENT_VALVE_MAX[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_AF_FOOT_VALVE_MAX[12] = { 0}; +/* ------------------------------------------AF level conditions: End*/ +SECT_SRAM_CAL tS16 g_assFLOW_AFSM_AMB_TGT[6] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_AFSM_VENT_PLUS[12] = { 0}; +SECT_SRAM_CAL tS16 g_assFLOW_AFSM_TEMP_TGT[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_AFSM_FOOT_PLUS[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_AFSM_VENT_VALVE_MAX[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucFLOW_AFSM_FOOT_VALVE_MAX[12] = { 0}; +/* ------------------------------------------AF_summer level conditions: End*/ +SECT_SRAM_CAL tU08 g_aucMODE_INDEX[11] = { 0}; +SECT_SRAM_CAL tS16 g_assFOOT_STEP_DUCT_TGT[7] = { 0}; +SECT_SRAM_CAL tS16 g_assBLR_FOOT_IND[7] = { 0}; +SECT_SRAM_CAL tS08 g_ascFOOT_STEP_VALVE_P1[11] = { 0}; +SECT_SRAM_CAL tS08 g_ascFOOT_STEP_VALVE_P2[11] = { 0}; +SECT_SRAM_CAL tS08 g_ascFOOT_STEP_VALVE_P3[11] = { 0}; +SECT_SRAM_CAL tS08 g_ascFOOT_STEP_VALVE_M1[11] = { 0}; +SECT_SRAM_CAL tS08 g_ascFOOT_STEP_VALVE_M2[11] = { 0}; +SECT_SRAM_CAL tS08 g_ascFOOT_STEP_VALVE_M3[11] = { 0}; +SECT_SRAM_CAL tS16 g_assFOOT_STEP_BLR_P1[11] = { 0}; +SECT_SRAM_CAL tS16 g_assFOOT_STEP_BLR_P2[11] = { 0}; +SECT_SRAM_CAL tS16 g_assFOOT_STEP_BLR_P3[11] = { 0}; +SECT_SRAM_CAL tS16 g_assFOOT_STEP_BLR_M1[11] = { 0}; +SECT_SRAM_CAL tS16 g_assFOOT_STEP_BLR_M2[11] = { 0}; +SECT_SRAM_CAL tS16 g_assFOOT_STEP_BLR_M3[11] = { 0}; +/* ------------------------------------------Individual foot temperature: End*/ +SECT_SRAM_CAL tU08 g_aucREAR_FOOT_VALVE_AMB_LV2[13] = { 0}; +SECT_SRAM_CAL tU08 g_aucREAR_FOOT_VALVE_AMB_LV3[13] = { 0}; +SECT_SRAM_CAL tU08 g_aucREAR_FOOT_VALVE_AMB_LV4[13] = { 0}; +/* ------------------------------------------Blowing foots from Rear HVAC: End*/ +SECT_SRAM_CAL tU16 g_ausFLOW_FR_VE2BLR_AF[8] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_BIVALVE_AF[8] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_BI2BLR_AF[8] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_FO2BLR_AF[8] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_AF2VALVE_AF[8] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_AF2VALVE_SUMMER_AF[8] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_FD2BLR_AF[8] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_DE2BLR_AF[8] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_TR2BLR_AF[8] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_FR_HI2BLR_AF[8] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_RE_VE2BLR_AF[8] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_RE_BI2BLR_AF[8] = { 0}; +SECT_SRAM_CAL tU16 g_ausFLOW_RE_FO2BLR_AF[8] = { 0}; +/* ------------------------------------------Flow Control AF: End*/ +SECT_SRAM_CAL tS08 g_ascAUTO_STEP_AF_F[5] = { 0}; +SECT_SRAM_CAL tS08 g_ascAUTO_STEP_AF_R[5] = { 0}; +SECT_SRAM_CAL tS16 g_assAUTO_STEP_DUCT_TG_U_F_LV0_1[10] = { 0}; +SECT_SRAM_CAL tS16 g_assAUTO_STEP_DUCT_TG_U_F_LV2_3[10] = { 0}; +SECT_SRAM_CAL tS16 g_assAUTO_STEP_DUCT_TG_U_F_LV4_5[10] = { 0}; +SECT_SRAM_CAL tS16 g_assAUTO_STEP_DUCT_TG_L_F_LV0_1[10] = { 0}; +SECT_SRAM_CAL tS16 g_assAUTO_STEP_DUCT_TG_L_F_LV2_3[10] = { 0}; +SECT_SRAM_CAL tS16 g_assAUTO_STEP_DUCT_TG_L_F_LV4_5[10] = { 0}; +SECT_SRAM_CAL tS16 g_assAUTO_STEP_DUCT_TG_R_LV0_1[10] = { 0}; +SECT_SRAM_CAL tS16 g_assAUTO_STEP_DUCT_TG_R_LV2_3[10] = { 0}; +SECT_SRAM_CAL tS16 g_assAUTO_STEP_DUCT_TG_R_LV4_5[10] = { 0}; +/* ------------------------------------------5 AUTO mode: End*/ +SECT_SRAM_CAL tU16 g_ausVALVE_SPACE[6] = { 0}; +SECT_SRAM_CAL tU08 g_aucVALVE_SECTION_S1_F_SIDE_VENT[9] = { 0}; +SECT_SRAM_CAL tU08 g_aucVALVE_SECTION_S1_F_CENT_VENT[9] = { 0}; +SECT_SRAM_CAL tU08 g_aucVALVE_SECTION_S1_F_DRIVER_FOOT[9] = { 0}; +SECT_SRAM_CAL tU08 g_aucVALVE_SECTION_S1_F_RIGHT_PASS[9] = { 0}; +SECT_SRAM_CAL tU08 g_aucBLR_SPD_V1_1_F[7] = { 0}; +SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_1_F_SIDE_VENT[10] = { 0}; +SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_2_F_CENT_VENT[10] = { 0}; +SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_3_F_DRIVER_FOOT[10] = { 0}; +SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_4_F_RIGHT_PASS[13] = { 0}; +SECT_SRAM_CAL tU16 g_ausVALVE_VEH_SPD[13] = { 0}; +SECT_SRAM_CAL tU08 g_aucVALVE_VEH_SPD_SIDE_VENT[13] = { 0}; +SECT_SRAM_CAL tU08 g_aucVALVE_VEH_SPD_SIDE_BI[13] = { 0}; +SECT_SRAM_CAL tU08 g_aucVALVE_VEH_SPD_SIDE_AFOOT[13] = { 0}; +SECT_SRAM_CAL tU08 g_aucVALVE_VEH_SPD_CNET_VENT[13] = { 0}; +SECT_SRAM_CAL tU08 g_aucVALVE_VEH_SPD_CENT_BI[13] = { 0}; +SECT_SRAM_CAL tU08 g_aucVALVE_VEH_SPD_CENT_AFOOT[13] = { 0}; +SECT_SRAM_CAL tU08 g_aucVALVE_VEH_SPD_FOOT_BI[13] = { 0}; +SECT_SRAM_CAL tU08 g_aucVALVE_VEH_SPD_FOOT_AFOOT[13] = { 0}; +SECT_SRAM_CAL tU08 g_aucVALVE_VEH_SPD_2FOOT[13] = { 0}; +SECT_SRAM_CAL tU08 g_aucBLR_SPD_VEH_SPD_V1_3[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucFRONT_SIDE_DRS_PERCENT[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucFRONT_CENT_DRS_PERCENT[12] = { 0}; +/* ------------------------------------------Different blower speed FRONT MODE: End*/ +SECT_SRAM_CAL tU08 g_aucVALVE_S1_R_BIPILLAR[8] = { 0}; +SECT_SRAM_CAL tU08 g_aucVALVE_S1_R_CENT_VENT[9] = { 0}; +SECT_SRAM_CAL tU08 g_aucVALVE_S1_R_FOOT[5] = { 0}; +SECT_SRAM_CAL tU08 g_aucVALVE_PERC_R_BIPILLAR[10] = { 0}; +SECT_SRAM_CAL tU08 g_aucVALVE_PERC_R_CENT_VENT[10] = { 0}; +SECT_SRAM_CAL tU08 g_aucVALVE_PERC_R_FOOT[10] = { 0}; +SECT_SRAM_CAL tU08 g_aucBLR_SPD_V1_1_R[7] = { 0}; +SECT_SRAM_CAL tU08 g_aucREAR_CEN_MIN_VALUE_BY_DRS_ZERO[7] = { 0}; +SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_1_R_BIPILLAR_MIN[8] = { 0}; +SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_2_R_CENT_VENT_MIN[9] = { 0}; +SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_3_R_FOOT_MIN[5] = { 0}; +SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_1_R_BIPILLAR_MAX[8] = { 0}; +SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_2_R_CENT_VENTR_MAX[9] = { 0}; +SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_3_R_FOOTR_MAX[5] = { 0}; +SECT_SRAM_CAL tU08 g_aucREAR_SIDE_DRS_PERCENT_VALVE[9] = { 0}; +SECT_SRAM_CAL tU08 g_aucREAR_CENT_DRS_PERCENT_VALVE[9] = { 0}; +SECT_SRAM_CAL tU08 g_aucREAR_SIDE_DRS_PERCENT_AF[9] = { 0}; +SECT_SRAM_CAL tU08 g_aucREAR_CENT_DRS_PERCENT_AF[9] = { 0}; +/* ------------------------------------------Different blower speed REAR MODE: End*/ +SECT_SRAM_CAL tU16 g_ausMIN_PWM[2] = { 0}; +/* ------------------------------------------MinPWM: End*/ +SECT_SRAM_CAL tS16 g_assSTART_ENTER_COOLANT[6] = { 0}; +SECT_SRAM_CAL tS16 g_assSTART_COOLANT_STEP0_TO_1[8] = { 0}; +SECT_SRAM_CAL tS16 g_assSTART_COOLANT_TO_STEP2[3] = { 0}; +SECT_SRAM_CAL tS16 g_assSTART_COOLANT_STEP1_BLR_F[6] = { 0}; +SECT_SRAM_CAL tS16 g_assSTART_COOLANT_STEP1_BLR_R[6] = { 0}; +SECT_SRAM_CAL tS16 g_assSTART_ENTER_INCAR[12] = { 0}; +SECT_SRAM_CAL tU16 g_ausSTART_ENTER_SETTEMP[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucSTART_INCAR_FLT_UP[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucSTART_INCAR_FLT_DN[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucSTART_VALVE_IDX_STEP1[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucSTART_AUTODEMIST2_STEP2[6] = { 0}; +SECT_SRAM_CAL tU08 g_aucSTART_ELEC_WINDOW[12] = { 0}; +SECT_SRAM_CAL tU16 g_ausSTART_BLR_AF_STEP12_F[12] = { 0}; +SECT_SRAM_CAL tU16 g_ausSTART_BLR_AF_STEP12_R[12] = { 0}; +SECT_SRAM_CAL tU16 g_ausSTART_BLR_SPD_STEP2_F[12] = { 0}; +SECT_SRAM_CAL tU16 g_ausSTART_BLR_SPD_STEP2_R[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucSTART_DUCT_TGT_STEP2_FX_U[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucSTART_DUCT_TGT_STEP2_FX_L[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucSTART_DUCT_TGT_STEP2_RX[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucSTART_VALVE_CHANGE_SPD_F[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucSTART_VALVE_CHANGE_SPD_R[12] = { 0}; +SECT_SRAM_CAL tU16 g_ausSTART_TIME_STEP1_TO_2[12] = { 0}; +SECT_SRAM_CAL tU16 g_ausSTART_TIME_STEP2_TO_3[12] = { 0}; +SECT_SRAM_CAL tS16 g_assSTART_INCAR_STEP1_TO_2[12] = { 0}; +SECT_SRAM_CAL tS16 g_assSTART_INCAR_STEP2_TO_3[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucSTART_3WAY_OPEN[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucSTART_2WAY_OPEN[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucSTART_TXV_F[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucSTART_TXV_R[12] = { 0}; +/* ------------------------------------------Start control: End*/ +SECT_SRAM_CAL tS16 g_assFAILURE_AMB_TEMP[13] = { 0}; +SECT_SRAM_CAL tS16 g_assAC_PRESSURE_LOW_HYS_UP[13] = { 0}; +SECT_SRAM_CAL tS16 g_assAC_PRESSURE_LOW_HYS_DN[13] = { 0}; +SECT_SRAM_CAL tS16 g_assAC_LOW_AMB_F[2] = { 0}; +SECT_SRAM_CAL tS16 g_assAC_CUT_OFF_AMB_F[2] = { 0}; +SECT_SRAM_CAL tS16 g_assAC_WINTER_TXV_DEWPOINT[2] = { 0}; +SECT_SRAM_CAL tS16 g_assAC_CUT_OFF_AMB_R[2] = { 0}; +SECT_SRAM_CAL tS16 g_assEVA_TG_AMB_F[13] = { 0}; +SECT_SRAM_CAL tS16 g_assEVA_TG_AMB_R[13] = { 0}; +SECT_SRAM_CAL tU08 g_ucAC_EXTRA_RPM = 0; +SECT_SRAM_CAL tS16 g_assAC_EVA_LV_SHUT_OFF[2] = { 0}; +SECT_SRAM_CAL tS16 g_assAC_PRESSURE_HYS_HI_ENG_ON[3] = { 0}; +SECT_SRAM_CAL tU16 g_usCMP_MAX_ENG_OFF = 0; +SECT_SRAM_CAL tU08 g_ucFAN_MAX_ENG_OFF = 0; +SECT_SRAM_CAL tS16 g_ssAC_WINTER_TXV_HYST = 0; +SECT_SRAM_CAL tU08 g_aucAC_PRESSURE_HYS_HI_ENG_OFF[2] = { 0}; +SECT_SRAM_CAL tU16 g_ausCMP_RPM_RESONANCE[6] = { 0}; +/* ------------------------------------------A/C Control Pressure : End*/ +SECT_SRAM_CAL tS16 g_assPRESSURE_TO_FAN_X[7] = { 0}; +SECT_SRAM_CAL tU08 g_aucPRESSURE_TO_FAN_Y[7] = { 0}; +/* ------------------------------------------CoolingFan: End*/ +SECT_SRAM_CAL tS16 g_ssREST_BATT = 0; +SECT_SRAM_CAL tS16 g_ssRESTW_AMB = 0; +SECT_SRAM_CAL tS16 g_assRESTW_WATER[2] = { 0}; +SECT_SRAM_CAL tU16 g_usRESTW_READYEXPIRETIME = 0; +SECT_SRAM_CAL tU08 g_aucRESTW_MODE[2] = { 0}; +SECT_SRAM_CAL tU16 g_usRESTW_TIMEOUTTIME = 0; +SECT_SRAM_CAL tU08 g_ucRESTW_BLRSTEP = 0; +SECT_SRAM_CAL tS16 g_ssRESTS_AMB = 0; +SECT_SRAM_CAL tU08 g_uctRESTS_READYEXPIRETIME = 0; +SECT_SRAM_CAL tU08 g_aucRESTS_MODE[2] = { 0}; +SECT_SRAM_CAL tU16 g_usRESTS_TIMEOUTTIME = 0; +SECT_SRAM_CAL tU08 g_ucRESTS_BLRSTEP = 0; +/* ------------------------------------------Rest mode: End*/ +SECT_SRAM_CAL tU16 g_usFRESH_AIR_PURGE_ENTRY_TIME = 0; +SECT_SRAM_CAL tU16 g_ausFRESH_AIR_PURGE_CHANGE_TIME[7] = { 0}; +/* ------------------------------------------Purge Rec: End*/ +SECT_SRAM_CAL tS16 g_assMAX_DEF_U_DTG[10] = { 0}; +SECT_SRAM_CAL tU16 g_ausMAX_BLR_SPD[6] = { 0}; +/* ------------------------------------------MAX DEF: End*/ +SECT_SRAM_CAL tU08 g_aucAQS_REC_LV_CO[8] = { 0}; +SECT_SRAM_CAL tU08 g_aucAQS_OSA_LV_CO[7] = { 0}; +SECT_SRAM_CAL tU08 g_aucAQS_REC_LV_NOX[8] = { 0}; +SECT_SRAM_CAL tU08 g_aucAQS_OSA_LV_NOX[7] = { 0}; +SECT_SRAM_CAL tU08 g_aucAQS_REC_LV_NH3[8] = { 0}; +SECT_SRAM_CAL tU08 g_aucAQS_OSA_LV_NH3[7] = { 0}; +SECT_SRAM_CAL tU08 g_ucAQS_REC_ON_TIME = 0; +SECT_SRAM_CAL tU08 g_aucAQS_REC_ON_WAIT[2] = { 0}; +/* ------------------------------------------Aqs: End*/ +SECT_SRAM_CAL tU16 g_usAUTODEMIST_LV2_BLR_PLUS = 0; +SECT_SRAM_CAL tU16 g_usAUTODEMIST_LV3_BLR_PLUS = 0; +SECT_SRAM_CAL tS16 g_assAUTODEMIST_OFFSET_AMB_TEMP[9] = { 0}; +SECT_SRAM_CAL tS16 g_assAUTODEMIST_OFFSET_VENT_TEMP[9] = { 0}; +SECT_SRAM_CAL tS16 g_assAUTODEMIST_STEP_UP[4] = { 0}; +SECT_SRAM_CAL tS16 g_assAUTODEMIST_STEP_DN[4] = { 0}; +SECT_SRAM_CAL tS16 g_assAUTODEMIST_WINTER[2] = { 0}; +/* ------------------------------------------Auto Demist: End*/ +SECT_SRAM_CAL tS16 g_ssAUTODEMIST_ELEC_AMB_ENTRY = 0; +SECT_SRAM_CAL tS16 g_assAUTODEMIST_ELEC_WINDSHELD_TEMP[2] = { 0}; +/* ------------------------------------------Electric AutoDemist: End*/ +SECT_SRAM_CAL tS16 g_ssAMBFILT_WATER = 0; +SECT_SRAM_CAL tU08 g_aucAMBFILT_H_CNT[2] = { 0}; +SECT_SRAM_CAL tS16 g_ssAMB_FAILSAFE = 0; +SECT_SRAM_CAL tS16 g_ssAMBKEEP_KAT = 0; +SECT_SRAM_CAL tS16 g_ssAMBKEEP_KAT_PLUS = 0; +SECT_SRAM_CAL tS16 g_ssAMBKEEP_WATER = 0; +SECT_SRAM_CAL tU08 g_aucAMBRATE_RISING[6] = { 0}; +SECT_SRAM_CAL tU08 g_aucAMBRATE_FALLING[6] = { 0}; +SECT_SRAM_CAL tU08 g_aucAMBRATE_RISING_DIFF[8] = { 0}; +SECT_SRAM_CAL tU08 g_aucAMBRATE_FALLING_DIFF[8] = { 0}; +/* ------------------------------------------Ambient: End*/ +SECT_SRAM_CAL tU16 g_ausINCARRATE_RISING_F[6] = { 0}; +SECT_SRAM_CAL tU16 g_ausINCARRATE_FALLING_F[6] = { 0}; +SECT_SRAM_CAL tU16 g_ausINCARRATE_RISING_DIFF_F[8] = { 0}; +SECT_SRAM_CAL tU16 g_ausINCARRATE_FALLING_DIFF_F[8] = { 0}; +SECT_SRAM_CAL tU16 g_ausINCARRATE_RISING_R[6] = { 0}; +SECT_SRAM_CAL tU16 g_ausINCARRATE_FALLING_R[6] = { 0}; +SECT_SRAM_CAL tU16 g_ausINCARRATE_RISING_DIFF_R[8] = { 0}; +SECT_SRAM_CAL tU16 g_ausINCARRATE_FALLING_DIFF_R[8] = { 0}; +/* ------------------------------------------Incar: End*/ +SECT_SRAM_CAL tU16 g_ausSUNRATE_RISING[6] = { 0}; +SECT_SRAM_CAL tU16 g_ausSUNRATE_FALLING[6] = { 0}; +/* ------------------------------------------Sun: End*/ +SECT_SRAM_CAL tU16 g_ausAMB_LV_CHANGE_UNIT[6] = { 0}; +SECT_SRAM_CAL tU08 g_aucAMB_LV_CHANGE_SEC[6] = { 0}; +/* ------------------------------------------Level Chage: End*/ +SECT_SRAM_CAL tS16 g_ssTHREEWAY_WATER = 0; +SECT_SRAM_CAL tS16 g_assTHREEWAY_DUCT_TGT_R[2] = { 0}; +SECT_SRAM_CAL tU08 g_aucTHEREEWAY_EXPIRING[2] = { 0}; +/* ------------------------------------------Three way: End*/ +SECT_SRAM_CAL tS16 g_assTWOWAY_REAR_DUCTTGT_R[2] = { 0}; +SECT_SRAM_CAL tU08 g_aucTWOWAY_EXPIRING[2] = { 0}; +/* ------------------------------------------two-way: End*/ +SECT_SRAM_CAL tU08 g_aucACT_HOM_SPD_FL_CH0[9] = { 0}; +SECT_SRAM_CAL tU08 g_aucACT_HOM_SPD_FR_CH1[6] = { 0}; +SECT_SRAM_CAL tU08 g_aucACT_HOM_SPD_R_CH2[9] = { 0}; +SECT_SRAM_CAL tU08 g_aucACT_HOM_SPD_R_EX_CH2[4] = { 0}; +SECT_SRAM_CAL tU08 g_aucACT_MOV_SPD_FL_CH0[9] = { 0}; +SECT_SRAM_CAL tU08 g_aucACT_MOV_SPD_FR_CH1[6] = { 0}; +SECT_SRAM_CAL tU08 g_aucACT_MOV_SPD_R_CH2[9] = { 0}; +SECT_SRAM_CAL tU08 g_aucACT_MOV_SPD_R_EX_CH2[4] = { 0}; +/* ------------------------------------------Actuator Homing: End*/ +SECT_SRAM_CAL tS16 g_assHI_MODE_ENG_TMEP[6] = { 0}; +SECT_SRAM_CAL tU08 g_aucHI_MODE_BLR_STEP_STS[6] = { 0}; +/* ------------------------------------------Hi Mode: End*/ +SECT_SRAM_CAL tU16 g_ausMinusAF_GlassPos_L[13] = { 0}; +SECT_SRAM_CAL tU16 g_ausMinusAF_GlassPos_R[13] = { 0}; +/* ------------------------------------------GlassPosition: End*/ +SECT_SRAM_CAL tS16 g_assFoot2_Lv3_Amb[6] = { 0}; +SECT_SRAM_CAL tS16 g_assFoot2_Lv4_Amb[6] = { 0}; +SECT_SRAM_CAL tS16 g_assFoot2_Lv5_Amb[6] = { 0}; +SECT_SRAM_CAL tS16 g_assFoot2_Lv3_DuctTgt_Plus[6] = { 0}; +SECT_SRAM_CAL tS16 g_assFoot2_Lv4_DuctTgt_Plus[6] = { 0}; +SECT_SRAM_CAL tS16 g_assFoot2_Lv5_DuctTgt_Plus[6] = { 0}; +SECT_SRAM_CAL tU16 g_ausFoot2_Lv1_FrontBlr_X[3] = { 0}; +SECT_SRAM_CAL tU16 g_ausFoot2_Lv1_Foot2Act_Y[3] = { 0}; +SECT_SRAM_CAL tS16 g_assFoot2_Lv2_Threshold_Diff[2] = { 0}; +SECT_SRAM_CAL tS16 g_assFoot2_Lv3_Threshold_Diff[2] = { 0}; +/* ------------------------------------------Foot2 Ctrl: End*/ +SECT_SRAM_CAL tU16 g_ausDbF_Side_Af_Bi[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Side_Af_Bi2[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Side_Af_Vent[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Side_Bi_Bi2[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Side_Bi_Vent[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Side_Bi2_Vent[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Cen_Af_Bi[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Cen_Af_Bi2[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Cen_Af_Vent[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Cen_Bi_Bi2[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Cen_Bi_Vent[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Cen_Bi2_Vent[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Foot_Af_Bi[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Foot_Af_Bi2[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Foot_Af_Vent[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Foot_Bi_Bi2[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Foot_Bi_Vent[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Foot_Bi2_Vent[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_AF_Af_Bi[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_AF_Af_Bi2[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_AF_Af_Vent[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_AF_Bi_Bi2[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_AF_Bi_Vent[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_AF_Bi2_Vent[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Pwm_Af_Bi[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Pwm_Af_Bi2[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Pwm_Af_Vent[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Pwm_Bi_Bi2[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Pwm_Bi_Vent[9] = { 0}; +SECT_SRAM_CAL tU16 g_ausDbF_Pwm_Bi2_Vent[9] = { 0}; +/* ------------------------------------------Different blower Front: End*/ +SECT_SRAM_CAL tU16 g_usAromaPwm_Min = 0; +SECT_SRAM_CAL tU16 g_usAromaPwm_Max = 0; +/* ------------------------------------------Aroma Limit Pwm: End*/ +SECT_SRAM_CAL tS16 g_assPID_COMPRESSOR[6] = { 0}; +SECT_SRAM_CAL tS16 g_assPID_VALVE_FRONT_UP[6] = { 0}; +SECT_SRAM_CAL tS16 g_assPID_VALVE_FRONT_LOW[6] = { 0}; +SECT_SRAM_CAL tS16 g_assPID2_VALVE_FRONT[6] = { 0}; +SECT_SRAM_CAL tS16 g_assPID_VALVE_REAR[6] = { 0}; +SECT_SRAM_CAL tS16 g_assPID2_VALVE_REAR[6] = { 0}; +SECT_SRAM_CAL tS16 g_assPID_VALVE_TG[15] = { 0}; +SECT_SRAM_CAL tS16 g_assPID_VALVE_SPEED[6] = { 0}; +/* ------------------------------------------PID: End*/ + +SECT_SRAM_CAL tU08 g_aucFRONT_SIDE_DRS_PERCENT_AF[12] = { 0}; +SECT_SRAM_CAL tU08 g_aucFRONT_CENT_DRS_PERCENT_AF[12] = { 0}; + + +/*********************************************************Cal Table End*/ + +/****************************************************************************** + * LOCAL VARIABLES DECLARATIONS + *****************************************************************************/ +/****************************************************************************** + * LOCAL FUNCTIONS DECLARATIONS + *****************************************************************************/ +/****************************************************************************** + * GLOBAL FUNCTIONS + *****************************************************************************/ +/****************************************************************************** + * LOCAL FUNCTIONS + *****************************************************************************/ +/* End of Excel line : 1092 */ +/****************************************************************************** + * EOF + *****************************************************************************/ diff --git a/MODULES/HVAC_M7_DataNonVolatile/Rs_Cal_Base.h b/MODULES/HVAC_M7_DataNonVolatile/Rs_Cal_Base.h new file mode 100644 index 0000000..1c4cd26 --- /dev/null +++ b/MODULES/HVAC_M7_DataNonVolatile/Rs_Cal_Base.h @@ -0,0 +1,1105 @@ +/** Doxygen: File brief + ****************************************************************************** + * @file Rs_Cal_Base.h + * @brief No brief + * @remark Generated by C:\9999\Rs_Cal_R23_ver21_SedanL.xlsm + * Generated on yyyy-mm-dd hh:mm:ss + *****************************************************************************/ +#ifndef RS_CAL_BASE_H__ +#define RS_CAL_BASE_H__ + +/****************************************************************************** + * INCLUDE FILES +*****************************************************************************/ +#include "common.h" +#include "HVAC_preDefine.h" + +/****************************************************************************** + * MACRO DECLARATIONS + *****************************************************************************/ +/*PRQA S 0777 EOF #suppress : The specified number of significant characters, from Calibtaiton data table, No impact*/ +/*PRQA S 0779 EOF #suppress : The specified number of significant characters, from Calibtaiton data table, No impact*/ +/****************************************************************************** + * GLOBAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS) + *****************************************************************************/ +/****************************************************************************** + * GLOBAL VARIABLES DECLARATIONS + *****************************************************************************/ +extern SECT_SRAM_CAL tU08 g_ucCalFromRelease; +extern SECT_SRAM_CAL tU08 g_aucCAL_FP_DATE[3]; +extern SECT_SRAM_CAL tU08 g_aucCAL_VERSION[2]; +extern SECT_SRAM_CAL tU08 g_ucCAL_VARIANT; +/* ------------------------------------------Cal Version : End*/ +extern SECT_SRAM_CAL tU16 g_ausSET_TEMP_FULL[13]; +extern SECT_SRAM_CAL tU16 g_ausSET_TEMP_HALF[7]; +/* ------------------------------------------Set Temp : End*/ +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_FL_LV0[13]; +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_FR_LV0[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_FL_LV0[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_FR_LV0[13]; +extern SECT_SRAM_CAL tS16 g_assVF_MIN_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVF_MAX_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y3_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y4_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X3_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X4_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_Y1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_Y2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_X1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_X2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_Y1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_Y2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_X1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_X2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assTG_FLU_LV0[13]; +extern SECT_SRAM_CAL tS16 g_assTG_FRU_LV0[13]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_MIN_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_MAX_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y3_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y4_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X3_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X4_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assTG_FLL_LV0[13]; +extern SECT_SRAM_CAL tS16 g_assTG_FRL_LV0[13]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_MIN_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_MAX_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y3_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y4_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X3_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X4_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_RL_LV0[13]; +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_RR_LV0[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_RL_LV0[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_RR_LV0[13]; +extern SECT_SRAM_CAL tS16 g_assVR_MIN_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVR_MAX_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y3_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y4_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X3_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X4_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_Y1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_Y2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_X1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_X2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_Y1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_Y2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_X1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_X2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assTG_RL_LV0[13]; +extern SECT_SRAM_CAL tS16 g_assTG_RR_LV0[13]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_MIN_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_MAX_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y3_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y4_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X3_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X4_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X1_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X2_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FR_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FL_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_RATE_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_MAX_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FR_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FL_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_RATE_LV0[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_MAX_LV0[7]; +/* ------------------------------------------Lv0 : End*/ +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_FL_LV1[13]; +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_FR_LV1[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_FL_LV1[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_FR_LV1[13]; +extern SECT_SRAM_CAL tS16 g_assVF_MIN_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVF_MAX_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y3_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y4_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X3_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X4_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_Y1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_Y2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_X1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_X2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_Y1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_Y2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_X1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_X2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assTG_FLU_LV1[13]; +extern SECT_SRAM_CAL tS16 g_assTG_FRU_LV1[13]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_MIN_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_MAX_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y3_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y4_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X3_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X4_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assTG_FLL_LV1[13]; +extern SECT_SRAM_CAL tS16 g_assTG_FRL_LV1[13]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_MIN_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_MAX_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y3_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y4_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X3_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X4_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_RL_LV1[13]; +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_RR_LV1[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_RL_LV1[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_RR_LV1[13]; +extern SECT_SRAM_CAL tS16 g_assVR_MIN_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVR_MAX_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y3_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y4_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X3_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X4_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_Y1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_Y2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_X1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_X2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_Y1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_Y2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_X1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_X2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assTG_RL_LV1[13]; +extern SECT_SRAM_CAL tS16 g_assTG_RR_LV1[13]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_MIN_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_MAX_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y3_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y4_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X3_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X4_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X1_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X2_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FR_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FL_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_RATE_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_MAX_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FR_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FL_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_RATE_LV1[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_MAX_LV1[7]; +/* ------------------------------------------Lv1 : End*/ +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_FL_LV2[13]; +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_FR_LV2[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_FL_LV2[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_FR_LV2[13]; +extern SECT_SRAM_CAL tS16 g_assVF_MIN_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVF_MAX_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y3_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y4_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X3_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X4_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_Y1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_Y2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_X1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_X2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_Y1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_Y2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_X1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_X2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assTG_FLU_LV2[13]; +extern SECT_SRAM_CAL tS16 g_assTG_FRU_LV2[13]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_MIN_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_MAX_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y3_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y4_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X3_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X4_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assTG_FLL_LV2[13]; +extern SECT_SRAM_CAL tS16 g_assTG_FRL_LV2[13]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_MIN_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_MAX_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y3_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y4_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X3_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X4_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_RL_LV2[13]; +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_RR_LV2[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_RL_LV2[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_RR_LV2[13]; +extern SECT_SRAM_CAL tS16 g_assVR_MIN_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVR_MAX_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y3_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y4_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X3_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X4_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_Y1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_Y2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_X1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_X2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_Y1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_Y2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_X1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_X2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assTG_RL_LV2[13]; +extern SECT_SRAM_CAL tS16 g_assTG_RR_LV2[13]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_MIN_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_MAX_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y3_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y4_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X3_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X4_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X1_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X2_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FR_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FL_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_RATE_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_MAX_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FR_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FL_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_RATE_LV2[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_MAX_LV2[7]; +/* ------------------------------------------Lv2 : End*/ +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_FL_LV3[13]; +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_FR_LV3[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_FL_LV3[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_FR_LV3[13]; +extern SECT_SRAM_CAL tS16 g_assVF_MIN_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVF_MAX_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y3_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y4_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X3_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X4_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_Y1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_Y2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_X1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_X2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_Y1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_Y2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_X1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_X2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assTG_FLU_LV3[13]; +extern SECT_SRAM_CAL tS16 g_assTG_FRU_LV3[13]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_MIN_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_MAX_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y3_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y4_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X3_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X4_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assTG_FLL_LV3[13]; +extern SECT_SRAM_CAL tS16 g_assTG_FRL_LV3[13]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_MIN_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_MAX_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y3_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y4_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X3_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X4_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_RL_LV3[13]; +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_RR_LV3[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_RL_LV3[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_RR_LV3[13]; +extern SECT_SRAM_CAL tS16 g_assVR_MIN_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVR_MAX_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y3_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y4_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X3_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X4_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_Y1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_Y2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_X1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_X2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_Y1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_Y2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_X1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_X2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assTG_RL_LV3[13]; +extern SECT_SRAM_CAL tS16 g_assTG_RR_LV3[13]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_MIN_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_MAX_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y3_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y4_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X3_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X4_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X1_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X2_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FR_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FL_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_RATE_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_MAX_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FR_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FL_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_RATE_LV3[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_MAX_LV3[7]; +/* ------------------------------------------Lv3 : End*/ +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_FL_LV4[13]; +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_FR_LV4[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_FL_LV4[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_FR_LV4[13]; +extern SECT_SRAM_CAL tS16 g_assVF_MIN_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVF_MAX_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y3_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y4_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X3_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X4_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_Y1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_Y2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_X1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_X2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_Y1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_Y2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_X1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_X2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assTG_FLU_LV4[13]; +extern SECT_SRAM_CAL tS16 g_assTG_FRU_LV4[13]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_MIN_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_MAX_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y3_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y4_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X3_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X4_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assTG_FLL_LV4[13]; +extern SECT_SRAM_CAL tS16 g_assTG_FRL_LV4[13]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_MIN_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_MAX_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y3_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y4_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X3_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X4_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_RL_LV4[13]; +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_RR_LV4[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_RL_LV4[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_RR_LV4[13]; +extern SECT_SRAM_CAL tS16 g_assVR_MIN_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVR_MAX_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y3_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y4_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X3_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X4_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_Y1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_Y2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_X1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_X2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_Y1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_Y2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_X1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_X2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assTG_RL_LV4[13]; +extern SECT_SRAM_CAL tS16 g_assTG_RR_LV4[13]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_MIN_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_MAX_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y3_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y4_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X3_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X4_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X1_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X2_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FR_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FL_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_RATE_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_MAX_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FR_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FL_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_RATE_LV4[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_MAX_LV4[7]; +/* ------------------------------------------Lv4 : End*/ +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_FL_LV5[13]; +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_FR_LV5[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_FL_LV5[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_FR_LV5[13]; +extern SECT_SRAM_CAL tS16 g_assVF_MIN_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVF_MAX_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y3_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_Y4_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X3_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVF_INC_X4_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_Y1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_Y2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_X1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVF_AMB_X2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_Y1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_Y2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_X1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVF_SUN_X2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assTG_FLU_LV5[13]; +extern SECT_SRAM_CAL tS16 g_assTG_FRU_LV5[13]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_MIN_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_MAX_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y3_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_Y4_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X3_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_INC_X4_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_Y2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_AMB_X2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_Y2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FU_SUN_X2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assTG_FLL_LV5[13]; +extern SECT_SRAM_CAL tS16 g_assTG_FRL_LV5[13]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_MIN_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_MAX_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y3_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_Y4_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X3_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_INC_X4_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_Y2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_AMB_X2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_Y2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_FL_SUN_X2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_RL_LV5[13]; +extern SECT_SRAM_CAL tS16 g_assINCAR_TG_RR_LV5[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_RL_LV5[13]; +extern SECT_SRAM_CAL tS16 g_assVTG_RR_LV5[13]; +extern SECT_SRAM_CAL tS16 g_assVR_MIN_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVR_MAX_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y3_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_Y4_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X3_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVR_INC_X4_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_Y1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_Y2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_X1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVR_AMB_X2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_Y1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_Y2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_X1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assVR_SUN_X2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assTG_RL_LV5[13]; +extern SECT_SRAM_CAL tS16 g_assTG_RR_LV5[13]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_MIN_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_MAX_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y3_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_Y4_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X3_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_INC_X4_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_Y2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_AMB_X2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_Y2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X1_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assDTG_R_SUN_X2_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FR_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_TIME_FL_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_RATE_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_DUCT_MAX_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FR_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_TIME_FL_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_RATE_LV5[7]; +extern SECT_SRAM_CAL tS16 g_assCORRECT_AF_MAX_LV5[7]; +/* ------------------------------------------Lv5 : End*/ +extern SECT_SRAM_CAL tS16 g_assDUCT_TGT_DEF_VALVE_L[11]; +extern SECT_SRAM_CAL tS16 g_assDUCT_TGT_DEF_VALVE_R[11]; +/* ------------------------------------------DuctTgt Increase : End*/ +extern SECT_SRAM_CAL tS16 g_assAMB_LV_UP[5]; +extern SECT_SRAM_CAL tS16 g_assAMB_LV_DN[5]; +extern SECT_SRAM_CAL tS16 g_assAMB_LV_TG[6]; +/* ------------------------------------------Ambient LEVEL : End*/ +extern SECT_SRAM_CAL tU08 g_aucMODE_BY_SET_F_LV0[13]; +extern SECT_SRAM_CAL tU08 g_aucMODE_BY_SET_F_LV1[13]; +extern SECT_SRAM_CAL tU08 g_aucMODE_BY_SET_F_LV2[13]; +extern SECT_SRAM_CAL tU08 g_aucMODE_BY_SET_F_LV3[13]; +extern SECT_SRAM_CAL tU08 g_aucMODE_BY_SET_F_LV4[13]; +extern SECT_SRAM_CAL tU08 g_aucMODE_BY_SET_F_LV5[13]; +extern SECT_SRAM_CAL tU16 g_ausMODE_BY_DUCT_TG_R_LV0[7]; +extern SECT_SRAM_CAL tU16 g_ausMODE_BY_DUCT_TG_R_LV1[7]; +extern SECT_SRAM_CAL tU16 g_ausMODE_BY_DUCT_TG_R_LV2[7]; +extern SECT_SRAM_CAL tU16 g_ausMODE_BY_DUCT_TG_R_LV3[7]; +extern SECT_SRAM_CAL tU16 g_ausMODE_BY_DUCT_TG_R_LV4[7]; +extern SECT_SRAM_CAL tU16 g_ausMODE_BY_DUCT_TG_R_LV5[7]; +/* ------------------------------------------Mode depend on SET for each level : End*/ +extern SECT_SRAM_CAL tS16 g_ssPREC_REC_ON_AMB; +extern SECT_SRAM_CAL tS16 g_ssPREC_REC_OFF_AMB; +extern SECT_SRAM_CAL tU08 g_aucPREC_VEH_SPD_OSA[13]; +extern SECT_SRAM_CAL tS16 g_assPRE_AMB_RANGE_WINTER[7]; +extern SECT_SRAM_CAL tU08 g_aucPREC_OSA_WINTER[7]; +extern SECT_SRAM_CAL tU08 g_aucPREC_REC_WINTER[7]; +extern SECT_SRAM_CAL tU16 g_ausPREC_HUMIDITY_NOK[7]; +extern SECT_SRAM_CAL tU16 g_ausPREC_HUMIDITY_OK[7]; +extern SECT_SRAM_CAL tU16 g_ausPREC_ENTRY_RPM[3]; +extern SECT_SRAM_CAL tU16 g_ausPREC_EXIT_RPM[3]; +extern SECT_SRAM_CAL tU16 g_ausPREC_COMP_SPD_1[3]; +extern SECT_SRAM_CAL tU08 g_aucPREC_OSA_SUMMER_1[3]; +extern SECT_SRAM_CAL tU08 g_aucPREC_REC_SUMMER_1[3]; +extern SECT_SRAM_CAL tS16 g_assPREC_EVA_DIFF_FB_TG_F[7]; +extern SECT_SRAM_CAL tU08 g_aucPREC_OSA_SUMMER_2[7]; +extern SECT_SRAM_CAL tU08 g_aucPREC_REC_SUMMER_2[7]; +extern SECT_SRAM_CAL tU08 g_aucPREC_EVA_DIFF[4]; +extern SECT_SRAM_CAL tU08 g_ucPREC_OSA_SUMMER_3; +extern SECT_SRAM_CAL tU08 g_ucPREC_REC_SUMMER_3; +/* ------------------------------------------AutoRec : End*/ +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_VE2VALVE[9]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_BIVALVE[9]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_BI2VALVE[9]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_AF2VALVE[9]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_AF2VALVE_SUMMER[9]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_FO2VALVE[9]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_FD2VALVE[9]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_DE2VALVE[9]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_TR2VALVE[9]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_HI2VALVE[9]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_BIVALVE_MANUAL[9]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_RE_VENT[6]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_RE_BI2VALVE[6]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_RE_FO2VALVE[6]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_RE_VENT_2[6]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_RE_BI2VALVE_2[6]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_RE_VENT_3[6]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_RE_BI2VALVE_3[6]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_RE_VENT_MANUAL[6]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_RE_BI2VALVE_MANUAL[6]; +/* ------------------------------------------Flow Control Valve: End*/ +extern SECT_SRAM_CAL tS16 g_assFLOW_BI_AMB_TGT[6]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_BI_VENT_PLUS[12]; +extern SECT_SRAM_CAL tS16 g_assFLOW_BI_TEMP_TGT[12]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_BI_FOOT_PLUS[12]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_BI_VENT_VALVE_MAX[12]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_BI_FOOT_VALVE_MAX[12]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_BI_VENT_VALVE_MIN[12]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_BI_FOOT_VALVE_MIN[12]; +/* ------------------------------------------Bi 2 level conditions: End*/ +extern SECT_SRAM_CAL tS16 g_assFLOW_B2I_AMB_TGT[6]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_BI2_VENT_PLUS[12]; +extern SECT_SRAM_CAL tS16 g_assFLOW_BI2_TEMP_TGT[12]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_BI2_FOOT_PLUS[12]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_BI2_VENT_VALVE_MAX[12]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_BI2_FOOT_VALVE_MAX[12]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_BI2_VENT_VALVE_MIN[12]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_BI2_FOOT_VALVE_MIN[12]; +/* ------------------------------------------AF level conditions: End*/ +extern SECT_SRAM_CAL tS16 g_assFLOW_AF_AMB_TGT[6]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_AF_VENT_PLUS[12]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_AF_BLR_AF_TGT[6]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_AF_FOOT_PLUS[12]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_AF_VENT_VALVE_MAX[12]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_AF_FOOT_VALVE_MAX[12]; +/* ------------------------------------------AF level conditions: End*/ +extern SECT_SRAM_CAL tS16 g_assFLOW_AFSM_AMB_TGT[6]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_AFSM_VENT_PLUS[12]; +extern SECT_SRAM_CAL tS16 g_assFLOW_AFSM_TEMP_TGT[12]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_AFSM_FOOT_PLUS[12]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_AFSM_VENT_VALVE_MAX[12]; +extern SECT_SRAM_CAL tU08 g_aucFLOW_AFSM_FOOT_VALVE_MAX[12]; +/* ------------------------------------------AF_summer level conditions: End*/ +extern SECT_SRAM_CAL tU08 g_aucMODE_INDEX[11]; +extern SECT_SRAM_CAL tS16 g_assFOOT_STEP_DUCT_TGT[7]; +extern SECT_SRAM_CAL tS16 g_assBLR_FOOT_IND[7]; +extern SECT_SRAM_CAL tS08 g_ascFOOT_STEP_VALVE_P1[11]; +extern SECT_SRAM_CAL tS08 g_ascFOOT_STEP_VALVE_P2[11]; +extern SECT_SRAM_CAL tS08 g_ascFOOT_STEP_VALVE_P3[11]; +extern SECT_SRAM_CAL tS08 g_ascFOOT_STEP_VALVE_M1[11]; +extern SECT_SRAM_CAL tS08 g_ascFOOT_STEP_VALVE_M2[11]; +extern SECT_SRAM_CAL tS08 g_ascFOOT_STEP_VALVE_M3[11]; +extern SECT_SRAM_CAL tS16 g_assFOOT_STEP_BLR_P1[11]; +extern SECT_SRAM_CAL tS16 g_assFOOT_STEP_BLR_P2[11]; +extern SECT_SRAM_CAL tS16 g_assFOOT_STEP_BLR_P3[11]; +extern SECT_SRAM_CAL tS16 g_assFOOT_STEP_BLR_M1[11]; +extern SECT_SRAM_CAL tS16 g_assFOOT_STEP_BLR_M2[11]; +extern SECT_SRAM_CAL tS16 g_assFOOT_STEP_BLR_M3[11]; +/* ------------------------------------------Individual foot temperature: End*/ +extern SECT_SRAM_CAL tU08 g_aucREAR_FOOT_VALVE_AMB_LV2[13]; +extern SECT_SRAM_CAL tU08 g_aucREAR_FOOT_VALVE_AMB_LV3[13]; +extern SECT_SRAM_CAL tU08 g_aucREAR_FOOT_VALVE_AMB_LV4[13]; +/* ------------------------------------------Blowing foots from Rear HVAC: End*/ +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_VE2BLR_AF[8]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_BIVALVE_AF[8]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_BI2BLR_AF[8]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_FO2BLR_AF[8]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_AF2VALVE_AF[8]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_AF2VALVE_SUMMER_AF[8]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_FD2BLR_AF[8]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_DE2BLR_AF[8]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_TR2BLR_AF[8]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_FR_HI2BLR_AF[8]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_RE_VE2BLR_AF[8]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_RE_BI2BLR_AF[8]; +extern SECT_SRAM_CAL tU16 g_ausFLOW_RE_FO2BLR_AF[8]; +/* ------------------------------------------Flow Control AF: End*/ +extern SECT_SRAM_CAL tS08 g_ascAUTO_STEP_AF_F[5]; +extern SECT_SRAM_CAL tS08 g_ascAUTO_STEP_AF_R[5]; +extern SECT_SRAM_CAL tS16 g_assAUTO_STEP_DUCT_TG_U_F_LV0_1[10]; +extern SECT_SRAM_CAL tS16 g_assAUTO_STEP_DUCT_TG_U_F_LV2_3[10]; +extern SECT_SRAM_CAL tS16 g_assAUTO_STEP_DUCT_TG_U_F_LV4_5[10]; +extern SECT_SRAM_CAL tS16 g_assAUTO_STEP_DUCT_TG_L_F_LV0_1[10]; +extern SECT_SRAM_CAL tS16 g_assAUTO_STEP_DUCT_TG_L_F_LV2_3[10]; +extern SECT_SRAM_CAL tS16 g_assAUTO_STEP_DUCT_TG_L_F_LV4_5[10]; +extern SECT_SRAM_CAL tS16 g_assAUTO_STEP_DUCT_TG_R_LV0_1[10]; +extern SECT_SRAM_CAL tS16 g_assAUTO_STEP_DUCT_TG_R_LV2_3[10]; +extern SECT_SRAM_CAL tS16 g_assAUTO_STEP_DUCT_TG_R_LV4_5[10]; +/* ------------------------------------------5 AUTO mode: End*/ +extern SECT_SRAM_CAL tU16 g_ausVALVE_SPACE[6]; +extern SECT_SRAM_CAL tU08 g_aucVALVE_SECTION_S1_F_SIDE_VENT[9]; +extern SECT_SRAM_CAL tU08 g_aucVALVE_SECTION_S1_F_CENT_VENT[9]; +extern SECT_SRAM_CAL tU08 g_aucVALVE_SECTION_S1_F_DRIVER_FOOT[9]; +extern SECT_SRAM_CAL tU08 g_aucVALVE_SECTION_S1_F_RIGHT_PASS[9]; +extern SECT_SRAM_CAL tU08 g_aucBLR_SPD_V1_1_F[7]; +extern SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_1_F_SIDE_VENT[10]; +extern SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_2_F_CENT_VENT[10]; +extern SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_3_F_DRIVER_FOOT[10]; +extern SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_4_F_RIGHT_PASS[13]; +extern SECT_SRAM_CAL tU16 g_ausVALVE_VEH_SPD[13]; +extern SECT_SRAM_CAL tU08 g_aucVALVE_VEH_SPD_SIDE_VENT[13]; +extern SECT_SRAM_CAL tU08 g_aucVALVE_VEH_SPD_SIDE_BI[13]; +extern SECT_SRAM_CAL tU08 g_aucVALVE_VEH_SPD_SIDE_AFOOT[13]; +extern SECT_SRAM_CAL tU08 g_aucVALVE_VEH_SPD_CNET_VENT[13]; +extern SECT_SRAM_CAL tU08 g_aucVALVE_VEH_SPD_CENT_BI[13]; +extern SECT_SRAM_CAL tU08 g_aucVALVE_VEH_SPD_CENT_AFOOT[13]; +extern SECT_SRAM_CAL tU08 g_aucVALVE_VEH_SPD_FOOT_BI[13]; +extern SECT_SRAM_CAL tU08 g_aucVALVE_VEH_SPD_FOOT_AFOOT[13]; +extern SECT_SRAM_CAL tU08 g_aucVALVE_VEH_SPD_2FOOT[13]; +extern SECT_SRAM_CAL tU08 g_aucBLR_SPD_VEH_SPD_V1_3[12]; +extern SECT_SRAM_CAL tU08 g_aucFRONT_SIDE_DRS_PERCENT[12]; +extern SECT_SRAM_CAL tU08 g_aucFRONT_CENT_DRS_PERCENT[12]; +/* ------------------------------------------Different blower speed FRONT MODE: End*/ +extern SECT_SRAM_CAL tU08 g_aucVALVE_S1_R_BIPILLAR[8]; +extern SECT_SRAM_CAL tU08 g_aucVALVE_S1_R_CENT_VENT[9]; +extern SECT_SRAM_CAL tU08 g_aucVALVE_S1_R_FOOT[5]; +extern SECT_SRAM_CAL tU08 g_aucVALVE_PERC_R_BIPILLAR[10]; +extern SECT_SRAM_CAL tU08 g_aucVALVE_PERC_R_CENT_VENT[10]; +extern SECT_SRAM_CAL tU08 g_aucVALVE_PERC_R_FOOT[10]; +extern SECT_SRAM_CAL tU08 g_aucBLR_SPD_V1_1_R[7]; +extern SECT_SRAM_CAL tU08 g_aucREAR_CEN_MIN_VALUE_BY_DRS_ZERO[7]; +extern SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_1_R_BIPILLAR_MIN[8]; +extern SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_2_R_CENT_VENT_MIN[9]; +extern SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_3_R_FOOT_MIN[5]; +extern SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_1_R_BIPILLAR_MAX[8]; +extern SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_2_R_CENT_VENTR_MAX[9]; +extern SECT_SRAM_CAL tU08 g_aucBLR_SPD_K2_3_R_FOOTR_MAX[5]; +extern SECT_SRAM_CAL tU08 g_aucREAR_SIDE_DRS_PERCENT_VALVE[9]; +extern SECT_SRAM_CAL tU08 g_aucREAR_CENT_DRS_PERCENT_VALVE[9]; +extern SECT_SRAM_CAL tU08 g_aucREAR_SIDE_DRS_PERCENT_AF[9]; +extern SECT_SRAM_CAL tU08 g_aucREAR_CENT_DRS_PERCENT_AF[9]; +/* ------------------------------------------Different blower speed REAR MODE: End*/ +extern SECT_SRAM_CAL tU16 g_ausMIN_PWM[2]; +/* ------------------------------------------MinPWM: End*/ +extern SECT_SRAM_CAL tS16 g_assSTART_ENTER_COOLANT[6]; +extern SECT_SRAM_CAL tS16 g_assSTART_COOLANT_STEP0_TO_1[8]; +extern SECT_SRAM_CAL tS16 g_assSTART_COOLANT_TO_STEP2[3]; +extern SECT_SRAM_CAL tS16 g_assSTART_COOLANT_STEP1_BLR_F[6]; +extern SECT_SRAM_CAL tS16 g_assSTART_COOLANT_STEP1_BLR_R[6]; +extern SECT_SRAM_CAL tS16 g_assSTART_ENTER_INCAR[12]; +extern SECT_SRAM_CAL tU16 g_ausSTART_ENTER_SETTEMP[12]; +extern SECT_SRAM_CAL tU08 g_aucSTART_INCAR_FLT_UP[12]; +extern SECT_SRAM_CAL tU08 g_aucSTART_INCAR_FLT_DN[12]; +extern SECT_SRAM_CAL tU08 g_aucSTART_VALVE_IDX_STEP1[12]; +extern SECT_SRAM_CAL tU08 g_aucSTART_AUTODEMIST2_STEP2[6]; +extern SECT_SRAM_CAL tU08 g_aucSTART_ELEC_WINDOW[12]; +extern SECT_SRAM_CAL tU16 g_ausSTART_BLR_AF_STEP12_F[12]; +extern SECT_SRAM_CAL tU16 g_ausSTART_BLR_AF_STEP12_R[12]; +extern SECT_SRAM_CAL tU16 g_ausSTART_BLR_SPD_STEP2_F[12]; +extern SECT_SRAM_CAL tU16 g_ausSTART_BLR_SPD_STEP2_R[12]; +extern SECT_SRAM_CAL tU08 g_aucSTART_DUCT_TGT_STEP2_FX_U[12]; +extern SECT_SRAM_CAL tU08 g_aucSTART_DUCT_TGT_STEP2_FX_L[12]; +extern SECT_SRAM_CAL tU08 g_aucSTART_DUCT_TGT_STEP2_RX[12]; +extern SECT_SRAM_CAL tU08 g_aucSTART_VALVE_CHANGE_SPD_F[12]; +extern SECT_SRAM_CAL tU08 g_aucSTART_VALVE_CHANGE_SPD_R[12]; +extern SECT_SRAM_CAL tU16 g_ausSTART_TIME_STEP1_TO_2[12]; +extern SECT_SRAM_CAL tU16 g_ausSTART_TIME_STEP2_TO_3[12]; +extern SECT_SRAM_CAL tS16 g_assSTART_INCAR_STEP1_TO_2[12]; +extern SECT_SRAM_CAL tS16 g_assSTART_INCAR_STEP2_TO_3[12]; +extern SECT_SRAM_CAL tU08 g_aucSTART_3WAY_OPEN[12]; +extern SECT_SRAM_CAL tU08 g_aucSTART_2WAY_OPEN[12]; +extern SECT_SRAM_CAL tU08 g_aucSTART_TXV_F[12]; +extern SECT_SRAM_CAL tU08 g_aucSTART_TXV_R[12]; +/* ------------------------------------------Start control: End*/ +extern SECT_SRAM_CAL tS16 g_assFAILURE_AMB_TEMP[13]; +extern SECT_SRAM_CAL tS16 g_assAC_PRESSURE_LOW_HYS_UP[13]; +extern SECT_SRAM_CAL tS16 g_assAC_PRESSURE_LOW_HYS_DN[13]; +extern SECT_SRAM_CAL tS16 g_assAC_LOW_AMB_F[2]; +extern SECT_SRAM_CAL tS16 g_assAC_CUT_OFF_AMB_F[2]; +extern SECT_SRAM_CAL tS16 g_assAC_WINTER_TXV_DEWPOINT[2]; +extern SECT_SRAM_CAL tS16 g_assAC_CUT_OFF_AMB_R[2]; +extern SECT_SRAM_CAL tS16 g_assEVA_TG_AMB_F[13]; +extern SECT_SRAM_CAL tS16 g_assEVA_TG_AMB_R[13]; +extern SECT_SRAM_CAL tU08 g_ucAC_EXTRA_RPM; +extern SECT_SRAM_CAL tS16 g_assAC_EVA_LV_SHUT_OFF[2]; +extern SECT_SRAM_CAL tS16 g_assAC_PRESSURE_HYS_HI_ENG_ON[3]; +extern SECT_SRAM_CAL tU16 g_usCMP_MAX_ENG_OFF; +extern SECT_SRAM_CAL tU08 g_ucFAN_MAX_ENG_OFF; +extern SECT_SRAM_CAL tS16 g_ssAC_WINTER_TXV_HYST; +extern SECT_SRAM_CAL tU08 g_aucAC_PRESSURE_HYS_HI_ENG_OFF[2]; +extern SECT_SRAM_CAL tU16 g_ausCMP_RPM_RESONANCE[6]; +/* ------------------------------------------A/C Control Pressure : End*/ +extern SECT_SRAM_CAL tS16 g_assPRESSURE_TO_FAN_X[7]; +extern SECT_SRAM_CAL tU08 g_aucPRESSURE_TO_FAN_Y[7]; +/* ------------------------------------------CoolingFan: End*/ +extern SECT_SRAM_CAL tS16 g_ssREST_BATT; +extern SECT_SRAM_CAL tS16 g_ssRESTW_AMB; +extern SECT_SRAM_CAL tS16 g_assRESTW_WATER[2]; +extern SECT_SRAM_CAL tU16 g_usRESTW_READYEXPIRETIME; +extern SECT_SRAM_CAL tU08 g_aucRESTW_MODE[2]; +extern SECT_SRAM_CAL tU16 g_usRESTW_TIMEOUTTIME; +extern SECT_SRAM_CAL tU08 g_ucRESTW_BLRSTEP; +extern SECT_SRAM_CAL tS16 g_ssRESTS_AMB; +extern SECT_SRAM_CAL tU08 g_uctRESTS_READYEXPIRETIME; +extern SECT_SRAM_CAL tU08 g_aucRESTS_MODE[2]; +extern SECT_SRAM_CAL tU16 g_usRESTS_TIMEOUTTIME; +extern SECT_SRAM_CAL tU08 g_ucRESTS_BLRSTEP; +/* ------------------------------------------Rest mode: End*/ +extern SECT_SRAM_CAL tU16 g_usFRESH_AIR_PURGE_ENTRY_TIME; +extern SECT_SRAM_CAL tU16 g_ausFRESH_AIR_PURGE_CHANGE_TIME[7]; +/* ------------------------------------------Purge Rec: End*/ +extern SECT_SRAM_CAL tS16 g_assMAX_DEF_U_DTG[10]; +extern SECT_SRAM_CAL tU16 g_ausMAX_BLR_SPD[6]; +/* ------------------------------------------MAX DEF: End*/ +extern SECT_SRAM_CAL tU08 g_aucAQS_REC_LV_CO[8]; +extern SECT_SRAM_CAL tU08 g_aucAQS_OSA_LV_CO[7]; +extern SECT_SRAM_CAL tU08 g_aucAQS_REC_LV_NOX[8]; +extern SECT_SRAM_CAL tU08 g_aucAQS_OSA_LV_NOX[7]; +extern SECT_SRAM_CAL tU08 g_aucAQS_REC_LV_NH3[8]; +extern SECT_SRAM_CAL tU08 g_aucAQS_OSA_LV_NH3[7]; +extern SECT_SRAM_CAL tU08 g_ucAQS_REC_ON_TIME; +extern SECT_SRAM_CAL tU08 g_aucAQS_REC_ON_WAIT[2]; +/* ------------------------------------------Aqs: End*/ +extern SECT_SRAM_CAL tU16 g_usAUTODEMIST_LV2_BLR_PLUS; +extern SECT_SRAM_CAL tU16 g_usAUTODEMIST_LV3_BLR_PLUS; +extern SECT_SRAM_CAL tS16 g_assAUTODEMIST_OFFSET_AMB_TEMP[9]; +extern SECT_SRAM_CAL tS16 g_assAUTODEMIST_OFFSET_VENT_TEMP[9]; +extern SECT_SRAM_CAL tS16 g_assAUTODEMIST_STEP_UP[4]; +extern SECT_SRAM_CAL tS16 g_assAUTODEMIST_STEP_DN[4]; +extern SECT_SRAM_CAL tS16 g_assAUTODEMIST_WINTER[2]; +/* ------------------------------------------Auto Demist: End*/ +extern SECT_SRAM_CAL tS16 g_ssAUTODEMIST_ELEC_AMB_ENTRY; +extern SECT_SRAM_CAL tS16 g_assAUTODEMIST_ELEC_WINDSHELD_TEMP[2]; +/* ------------------------------------------Electric AutoDemist: End*/ +extern SECT_SRAM_CAL tS16 g_ssAMBFILT_WATER; +extern SECT_SRAM_CAL tU08 g_aucAMBFILT_H_CNT[2]; +extern SECT_SRAM_CAL tS16 g_ssAMB_FAILSAFE; +extern SECT_SRAM_CAL tS16 g_ssAMBKEEP_KAT; +extern SECT_SRAM_CAL tS16 g_ssAMBKEEP_KAT_PLUS; +extern SECT_SRAM_CAL tS16 g_ssAMBKEEP_WATER; +extern SECT_SRAM_CAL tU08 g_aucAMBRATE_RISING[6]; +extern SECT_SRAM_CAL tU08 g_aucAMBRATE_FALLING[6]; +extern SECT_SRAM_CAL tU08 g_aucAMBRATE_RISING_DIFF[8]; +extern SECT_SRAM_CAL tU08 g_aucAMBRATE_FALLING_DIFF[8]; +/* ------------------------------------------Ambient: End*/ +extern SECT_SRAM_CAL tU16 g_ausINCARRATE_RISING_F[6]; +extern SECT_SRAM_CAL tU16 g_ausINCARRATE_FALLING_F[6]; +extern SECT_SRAM_CAL tU16 g_ausINCARRATE_RISING_DIFF_F[8]; +extern SECT_SRAM_CAL tU16 g_ausINCARRATE_FALLING_DIFF_F[8]; +extern SECT_SRAM_CAL tU16 g_ausINCARRATE_RISING_R[6]; +extern SECT_SRAM_CAL tU16 g_ausINCARRATE_FALLING_R[6]; +extern SECT_SRAM_CAL tU16 g_ausINCARRATE_RISING_DIFF_R[8]; +extern SECT_SRAM_CAL tU16 g_ausINCARRATE_FALLING_DIFF_R[8]; +/* ------------------------------------------Incar: End*/ +extern SECT_SRAM_CAL tU16 g_ausSUNRATE_RISING[6]; +extern SECT_SRAM_CAL tU16 g_ausSUNRATE_FALLING[6]; +/* ------------------------------------------Sun: End*/ +extern SECT_SRAM_CAL tU16 g_ausAMB_LV_CHANGE_UNIT[6]; +extern SECT_SRAM_CAL tU08 g_aucAMB_LV_CHANGE_SEC[6]; +/* ------------------------------------------Level Chage: End*/ +extern SECT_SRAM_CAL tS16 g_ssTHREEWAY_WATER; +extern SECT_SRAM_CAL tS16 g_assTHREEWAY_DUCT_TGT_R[2]; +extern SECT_SRAM_CAL tU08 g_aucTHEREEWAY_EXPIRING[2]; +/* ------------------------------------------Three way: End*/ +extern SECT_SRAM_CAL tS16 g_assTWOWAY_REAR_DUCTTGT_R[2]; +extern SECT_SRAM_CAL tU08 g_aucTWOWAY_EXPIRING[2]; +/* ------------------------------------------two-way: End*/ +extern SECT_SRAM_CAL tU08 g_aucACT_HOM_SPD_FL_CH0[9]; +extern SECT_SRAM_CAL tU08 g_aucACT_HOM_SPD_FR_CH1[6]; +extern SECT_SRAM_CAL tU08 g_aucACT_HOM_SPD_R_CH2[9]; +extern SECT_SRAM_CAL tU08 g_aucACT_HOM_SPD_R_EX_CH2[4]; +extern SECT_SRAM_CAL tU08 g_aucACT_MOV_SPD_FL_CH0[9]; +extern SECT_SRAM_CAL tU08 g_aucACT_MOV_SPD_FR_CH1[6]; +extern SECT_SRAM_CAL tU08 g_aucACT_MOV_SPD_R_CH2[9]; +extern SECT_SRAM_CAL tU08 g_aucACT_MOV_SPD_R_EX_CH2[4]; +/* ------------------------------------------Actuator Homing: End*/ +extern SECT_SRAM_CAL tS16 g_assHI_MODE_ENG_TMEP[6]; +extern SECT_SRAM_CAL tU08 g_aucHI_MODE_BLR_STEP_STS[6]; +/* ------------------------------------------Hi Mode: End*/ +extern SECT_SRAM_CAL tU16 g_ausMinusAF_GlassPos_L[13]; +extern SECT_SRAM_CAL tU16 g_ausMinusAF_GlassPos_R[13]; +/* ------------------------------------------GlassPosition: End*/ +extern SECT_SRAM_CAL tS16 g_assFoot2_Lv3_Amb[6]; +extern SECT_SRAM_CAL tS16 g_assFoot2_Lv4_Amb[6]; +extern SECT_SRAM_CAL tS16 g_assFoot2_Lv5_Amb[6]; +extern SECT_SRAM_CAL tS16 g_assFoot2_Lv3_DuctTgt_Plus[6]; +extern SECT_SRAM_CAL tS16 g_assFoot2_Lv4_DuctTgt_Plus[6]; +extern SECT_SRAM_CAL tS16 g_assFoot2_Lv5_DuctTgt_Plus[6]; +extern SECT_SRAM_CAL tU16 g_ausFoot2_Lv1_FrontBlr_X[3]; +extern SECT_SRAM_CAL tU16 g_ausFoot2_Lv1_Foot2Act_Y[3]; +extern SECT_SRAM_CAL tS16 g_assFoot2_Lv2_Threshold_Diff[2]; +extern SECT_SRAM_CAL tS16 g_assFoot2_Lv3_Threshold_Diff[2]; +/* ------------------------------------------Foot2 Ctrl: End*/ +extern SECT_SRAM_CAL tU16 g_ausDbF_Side_Af_Bi[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Side_Af_Bi2[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Side_Af_Vent[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Side_Bi_Bi2[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Side_Bi_Vent[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Side_Bi2_Vent[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Cen_Af_Bi[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Cen_Af_Bi2[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Cen_Af_Vent[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Cen_Bi_Bi2[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Cen_Bi_Vent[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Cen_Bi2_Vent[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Foot_Af_Bi[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Foot_Af_Bi2[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Foot_Af_Vent[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Foot_Bi_Bi2[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Foot_Bi_Vent[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Foot_Bi2_Vent[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_AF_Af_Bi[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_AF_Af_Bi2[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_AF_Af_Vent[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_AF_Bi_Bi2[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_AF_Bi_Vent[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_AF_Bi2_Vent[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Pwm_Af_Bi[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Pwm_Af_Bi2[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Pwm_Af_Vent[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Pwm_Bi_Bi2[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Pwm_Bi_Vent[9]; +extern SECT_SRAM_CAL tU16 g_ausDbF_Pwm_Bi2_Vent[9]; +/* ------------------------------------------Different blower Front: End*/ +extern SECT_SRAM_CAL tU16 g_usAromaPwm_Min; +extern SECT_SRAM_CAL tU16 g_usAromaPwm_Max; +/* ------------------------------------------Aroma Limit Pwm: End*/ +extern SECT_SRAM_CAL tS16 g_assPID_COMPRESSOR[6]; +extern SECT_SRAM_CAL tS16 g_assPID_VALVE_FRONT_UP[6]; +extern SECT_SRAM_CAL tS16 g_assPID_VALVE_FRONT_LOW[6]; +extern SECT_SRAM_CAL tS16 g_assPID2_VALVE_FRONT[6]; +extern SECT_SRAM_CAL tS16 g_assPID_VALVE_REAR[6]; +extern SECT_SRAM_CAL tS16 g_assPID2_VALVE_REAR[6]; +extern SECT_SRAM_CAL tS16 g_assPID_VALVE_TG[15]; +extern SECT_SRAM_CAL tS16 g_assPID_VALVE_SPEED[6]; +/* ------------------------------------------PID: End*/ + +extern SECT_SRAM_CAL tU08 g_aucFRONT_SIDE_DRS_PERCENT_AF[12]; +extern SECT_SRAM_CAL tU08 g_aucFRONT_CENT_DRS_PERCENT_AF[12]; + + +/*********************************************************Cal Table End*/ + +/****************************************************************************** + * GLOBAL FUNCTIONS DECLARATIONS + *****************************************************************************/ + +/* End of Excel line : 1087 */ +#endif /*RS_CAL_BASE_H__*/ +/****************************************************************************** + * EOF + *****************************************************************************/ diff --git a/MODULES/HVAC_M7_DataNonVolatile/calib/Rs_Cal_0_SedanL.c b/MODULES/HVAC_M7_DataNonVolatile/calib/Rs_Cal_0_SedanL.c new file mode 100644 index 0000000..b32e27e --- /dev/null +++ b/MODULES/HVAC_M7_DataNonVolatile/calib/Rs_Cal_0_SedanL.c @@ -0,0 +1,2193 @@ +/** Doxygen: File brief + ****************************************************************************** + * @file Rs_Cal_0_SedanL.c + * @brief No brief + * @remark Generated by C:\9999\Rs_Cal_R23_ver21_SedanL.xlsm + * Generated on yyyy-mm-dd hh:mm:ss + *****************************************************************************/ +/****************************************************************************** + * INCLUDE FILES + *****************************************************************************/ +#include "Rs_Cal_0_SedanL.h" + +/****************************************************************************** + * MACRO DECLARATIONS + *****************************************************************************/ +/*PRQA S 0615 EOF #suppress : More than 511 block scope identifiers, from Calibration data table, No impact*/ +/*PRQA S 1514 EOF #suppress : In the same translation(used != defined), from Calibration data table, No impact*/ +/*PRQA S 3408 EOF #suppress : To manage Cal. data separately, from Calibration data table, No Impact*/ +/****************************************************************************** + * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS) + *****************************************************************************/ +/****************************************************************************** + * GLOBAL VARIABLES DECLARATIONS + *****************************************************************************/ +SECT_VEH_CAL_0 const tU08 c_ucCalFromRelease_SedanL = ID_TRUE; +SECT_VEH_CAL_0 const tU08 c_aucCAL_FP_DATE_SedanL[3] = { VERSION_SEDANL_Y, VERSION_SEDANL_M, VERSION_SEDANL_D}; +SECT_VEH_CAL_0 const tU08 c_aucCAL_VERSION_SedanL[2] = { 0, 21}; +SECT_VEH_CAL_0 const tU08 c_ucCAL_VARIANT_SedanL = 1; +/* ------------------------------------------Cal Version : End*/ +SECT_VEH_CAL_0 const tU16 c_ausSET_TEMP_FULL_SedanL[13] = { 170, 180, 190, 200, 210, 220, 230, 240, 250, 260, 270, 280, 290}; +SECT_VEH_CAL_0 const tU16 c_ausSET_TEMP_HALF_SedanL[7] = { 170, 190, 210, 230, 250, 270, 290}; +/* ------------------------------------------Set Temp : End*/ +SECT_VEH_CAL_0 const tS16 c_assINCAR_TG_FL_LV0_SedanL[13] = { 180, 190, 200, 210, 220, 235, 245, 255, 270, 280, 290, 310, 330}; +SECT_VEH_CAL_0 const tS16 c_assINCAR_TG_FR_LV0_SedanL[13] = { 180, 190, 200, 210, 220, 235, 245, 255, 270, 280, 290, 310, 330}; +SECT_VEH_CAL_0 const tS16 c_assVTG_FL_LV0_SedanL[13] = { 120, 105, 100, 95, 90, 85, 80, 80, 70, 65, 60, 60, 60}; +SECT_VEH_CAL_0 const tS16 c_assVTG_FR_LV0_SedanL[13] = { 120, 105, 100, 95, 90, 85, 80, 80, 70, 65, 60, 60, 60}; +SECT_VEH_CAL_0 const tS16 c_assVF_MIN_LV0_SedanL[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_0 const tS16 c_assVF_MAX_LV0_SedanL[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_Y1_LV0_SedanL[7] = { 60, 60, 50, 50, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_Y2_LV0_SedanL[7] = { 20, 20, 20, 20, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_Y3_LV0_SedanL[7] = { -20, -20, -20, -10, 5, 5, 5}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_Y4_LV0_SedanL[7] = { -50, -50, -50, -20, 10, 10, 10}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_X1_LV0_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_X2_LV0_SedanL[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_X3_LV0_SedanL[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_X4_LV0_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assVF_AMB_Y1_LV0_SedanL[7] = { 10, 10, 10, 5, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVF_AMB_Y2_LV0_SedanL[7] = { 5, 7, -2, -8, 1, 7, 5}; +SECT_VEH_CAL_0 const tS16 c_assVF_AMB_X1_LV0_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assVF_AMB_X2_LV0_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assVF_SUN_Y1_LV0_SedanL[7] = { 20, 20, 20, 20, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVF_SUN_Y2_LV0_SedanL[7] = { 50, 50, 50, 50, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVF_SUN_X1_LV0_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assVF_SUN_X2_LV0_SedanL[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_0 const tS16 c_assTG_FLU_LV0_SedanL[13] = { 20, 20, 20, 50, 60, 80, 100, 125, 180, 260, 280, 300, 320}; +SECT_VEH_CAL_0 const tS16 c_assTG_FRU_LV0_SedanL[13] = { 20, 20, 20, 50, 60, 80, 100, 125, 180, 260, 280, 300, 320}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_MIN_LV0_SedanL[7] = { 20, 20, 20, 50, 50, 50, 50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_MAX_LV0_SedanL[7] = { 600, 600, 600, 600, 600, 600, 598}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_Y1_LV0_SedanL[7] = { 0, -20, -50, -50, -100, -150, -200}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_Y2_LV0_SedanL[7] = { 0, -10, -30, -50, -50, -50, -50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_Y3_LV0_SedanL[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_Y4_LV0_SedanL[7] = { 200, 200, 200, 150, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_X1_LV0_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_X2_LV0_SedanL[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_X3_LV0_SedanL[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_X4_LV0_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_AMB_Y1_LV0_SedanL[7] = { -20, -10, -30, -40, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_AMB_Y2_LV0_SedanL[7] = { 15, 40, 50, 50, 0, 20, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_AMB_X1_LV0_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_AMB_X2_LV0_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_SUN_Y1_LV0_SedanL[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_SUN_Y2_LV0_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_SUN_X1_LV0_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_SUN_X2_LV0_SedanL[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_0 const tS16 c_assTG_FLL_LV0_SedanL[13] = { 150, 150, 150, 150, 200, 250, 300, 350, 400, 450, 500, 550, 650}; +SECT_VEH_CAL_0 const tS16 c_assTG_FRL_LV0_SedanL[13] = { 150, 150, 150, 150, 200, 250, 300, 350, 400, 450, 500, 550, 650}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_MIN_LV0_SedanL[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_MAX_LV0_SedanL[7] = { 400, 450, 500, 600, 600, 600, 600}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_Y1_LV0_SedanL[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_Y2_LV0_SedanL[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_Y3_LV0_SedanL[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_Y4_LV0_SedanL[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_X1_LV0_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_X2_LV0_SedanL[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_X3_LV0_SedanL[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_X4_LV0_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_AMB_Y1_LV0_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_AMB_Y2_LV0_SedanL[7] = { 0, 50, 50, 0, -20, -50, -100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_AMB_X1_LV0_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_AMB_X2_LV0_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_SUN_Y1_LV0_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_SUN_Y2_LV0_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_SUN_X1_LV0_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_SUN_X2_LV0_SedanL[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_0 const tS16 c_assINCAR_TG_RL_LV0_SedanL[13] = { 5, 195, 200, 215, 230, 240, 250, 270, 280, 290, 300, 310, 320}; +SECT_VEH_CAL_0 const tS16 c_assINCAR_TG_RR_LV0_SedanL[13] = { 190, 195, 200, 215, 230, 240, 250, 270, 280, 290, 300, 310, 320}; +SECT_VEH_CAL_0 const tS16 c_assVTG_RL_LV0_SedanL[13] = { 110, 100, 92, 82, 75, 70, 65, 65, 60, 60, 60, 60, 60}; +SECT_VEH_CAL_0 const tS16 c_assVTG_RR_LV0_SedanL[13] = { 110, 100, 92, 82, 75, 70, 65, 65, 60, 60, 60, 60, 60}; +SECT_VEH_CAL_0 const tS16 c_assVR_MIN_LV0_SedanL[7] = { 80, 80, 40, 40, 40, 30, 30}; +SECT_VEH_CAL_0 const tS16 c_assVR_MAX_LV0_SedanL[7] = { 160, 160, 160, 160, 100, 80, 80}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_Y1_LV0_SedanL[7] = { 60, 60, 50, 50, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_Y2_LV0_SedanL[7] = { 20, 20, 20, 20, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_Y3_LV0_SedanL[7] = { -20, -20, -20, -10, 5, 5, 5}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_Y4_LV0_SedanL[7] = { -50, -50, -50, -20, 10, 10, 10}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_X1_LV0_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_X2_LV0_SedanL[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_X3_LV0_SedanL[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_X4_LV0_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assVR_AMB_Y1_LV0_SedanL[7] = { 20, 20, 20, 20, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVR_AMB_Y2_LV0_SedanL[7] = { 5, 5, -5, -10, -10, -10, 5}; +SECT_VEH_CAL_0 const tS16 c_assVR_AMB_X1_LV0_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assVR_AMB_X2_LV0_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assVR_SUN_Y1_LV0_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVR_SUN_Y2_LV0_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVR_SUN_X1_LV0_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assVR_SUN_X2_LV0_SedanL[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_0 const tS16 c_assTG_RL_LV0_SedanL[13] = { 30, 30, 30, 50, 90, 100, 120, 180, 240, 320, 400, 450, 500}; +SECT_VEH_CAL_0 const tS16 c_assTG_RR_LV0_SedanL[13] = { 30, 30, 30, 50, 90, 100, 120, 180, 240, 320, 400, 450, 500}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_MIN_LV0_SedanL[7] = { 20, 20, 20, 20, 50, 50, 50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_MAX_LV0_SedanL[7] = { 400, 400, 450, 500, 600, 600, 600}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_Y1_LV0_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_Y2_LV0_SedanL[7] = { -40, -40, -40, -40, -40, -50, -60}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_Y3_LV0_SedanL[7] = { 40, 40, 40, 40, 20, 20, 20}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_Y4_LV0_SedanL[7] = { 200, 200, 200, 100, 50, 50, 50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_X1_LV0_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_X2_LV0_SedanL[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_X3_LV0_SedanL[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_X4_LV0_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_AMB_Y1_LV0_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_AMB_Y2_LV0_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_AMB_X1_LV0_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_AMB_X2_LV0_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_SUN_Y1_LV0_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_SUN_Y2_LV0_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_SUN_X1_LV0_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_SUN_X2_LV0_SedanL[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_DUCT_TIME_FR_LV0_SedanL[7] = { 600, 600, 600, 600, 600, 600, 600}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_DUCT_TIME_FL_LV0_SedanL[7] = { 600, 600, 600, 600, 600, 600, 600}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_DUCT_RATE_LV0_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_DUCT_MAX_LV0_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_AF_TIME_FR_LV0_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_AF_TIME_FL_LV0_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_AF_RATE_LV0_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_AF_MAX_LV0_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +/* ------------------------------------------Lv0 : End*/ +SECT_VEH_CAL_0 const tS16 c_assINCAR_TG_FL_LV1_SedanL[13] = { 210, 225, 240, 255, 270, 285, 300, 310, 320, 330, 340, 350, 360}; +SECT_VEH_CAL_0 const tS16 c_assINCAR_TG_FR_LV1_SedanL[13] = { 210, 225, 240, 255, 270, 285, 300, 310, 320, 330, 340, 350, 360}; +SECT_VEH_CAL_0 const tS16 c_assVTG_FL_LV1_SedanL[13] = { 120, 110, 100, 90, 83, 78, 70, 70, 70, 70, 70, 70, 70}; +SECT_VEH_CAL_0 const tS16 c_assVTG_FR_LV1_SedanL[13] = { 120, 110, 100, 90, 83, 78, 70, 70, 70, 70, 70, 70, 70}; +SECT_VEH_CAL_0 const tS16 c_assVF_MIN_LV1_SedanL[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_0 const tS16 c_assVF_MAX_LV1_SedanL[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_Y1_LV1_SedanL[7] = { 24, 30, 30, 30, 30, 25, 20}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_Y2_LV1_SedanL[7] = { 10, 10, 10, 10, 5, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_Y3_LV1_SedanL[7] = { -10, -8, -5, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_Y4_LV1_SedanL[7] = { -30, -30, -20, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_X1_LV1_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_X2_LV1_SedanL[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_X3_LV1_SedanL[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_X4_LV1_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assVF_AMB_Y1_LV1_SedanL[7] = { 5, 4, 3, 2, -2, -3, -5}; +SECT_VEH_CAL_0 const tS16 c_assVF_AMB_Y2_LV1_SedanL[7] = { -25, -25, -20, -10, -8, 3, 10}; +SECT_VEH_CAL_0 const tS16 c_assVF_AMB_X1_LV1_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assVF_AMB_X2_LV1_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assVF_SUN_Y1_LV1_SedanL[7] = { 15, 15, 15, 11, 5, 3, 3}; +SECT_VEH_CAL_0 const tS16 c_assVF_SUN_Y2_LV1_SedanL[7] = { 33, 30, 25, 22, 10, 5, 5}; +SECT_VEH_CAL_0 const tS16 c_assVF_SUN_X1_LV1_SedanL[7] = { 500, 500, 500, 500, 500, 500, 500}; +SECT_VEH_CAL_0 const tS16 c_assVF_SUN_X2_LV1_SedanL[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_0 const tS16 c_assTG_FLU_LV1_SedanL[13] = { 50, 70, 90, 120, 130, 140, 180, 200, 240, 260, 280, 300, 320}; +SECT_VEH_CAL_0 const tS16 c_assTG_FRU_LV1_SedanL[13] = { 50, 70, 90, 120, 130, 140, 180, 200, 240, 260, 280, 300, 320}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_MIN_LV1_SedanL[7] = { 20, 20, 20, 20, 50, 50, 50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_MAX_LV1_SedanL[7] = { 400, 450, 450, 500, 600, 600, 600}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_Y1_LV1_SedanL[7] = { -8, -20, -50, -70, -100, -150, -200}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_Y2_LV1_SedanL[7] = { 0, -10, -30, -50, -50, -50, -50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_Y3_LV1_SedanL[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_Y4_LV1_SedanL[7] = { 200, 200, 200, 150, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_X1_LV1_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_X2_LV1_SedanL[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_X3_LV1_SedanL[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_X4_LV1_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_AMB_Y1_LV1_SedanL[7] = { -15, -25, -15, -27, -30, 70, 70}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_AMB_Y2_LV1_SedanL[7] = { 0, 20, 20, 25, 55, 55, 75}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_AMB_X1_LV1_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_AMB_X2_LV1_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_SUN_Y1_LV1_SedanL[7] = { -50, -50, -35, -20, -50, -50, -50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_SUN_Y2_LV1_SedanL[7] = { -100, -100, -75, -50, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_SUN_X1_LV1_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_SUN_X2_LV1_SedanL[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_0 const tS16 c_assTG_FLL_LV1_SedanL[13] = { 150, 200, 200, 200, 200, 220, 250, 280, 320, 360, 400, 450, 500}; +SECT_VEH_CAL_0 const tS16 c_assTG_FRL_LV1_SedanL[13] = { 150, 200, 200, 200, 200, 200, 220, 280, 320, 360, 400, 450, 500}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_MIN_LV1_SedanL[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_MAX_LV1_SedanL[7] = { 450, 450, 500, 600, 600, 600, 600}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_Y1_LV1_SedanL[7] = { 0, 0, 0, 0, 0, -100, -200}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_Y2_LV1_SedanL[7] = { 0, 0, 0, 0, -50, -50, -50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_Y3_LV1_SedanL[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_Y4_LV1_SedanL[7] = { 100, 100, 100, 50, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_X1_LV1_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_X2_LV1_SedanL[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_X3_LV1_SedanL[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_X4_LV1_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_AMB_Y1_LV1_SedanL[7] = { 0, 0, 65, 60, 65, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_AMB_Y2_LV1_SedanL[7] = { 45, 50, 60, 75, 100, 100, 95}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_AMB_X1_LV1_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_AMB_X2_LV1_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_SUN_Y1_LV1_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_SUN_Y2_LV1_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_SUN_X1_LV1_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_SUN_X2_LV1_SedanL[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_0 const tS16 c_assINCAR_TG_RL_LV1_SedanL[13] = { 225, 240, 255, 270, 285, 300, 310, 320, 330, 340, 350, 360, 370}; +SECT_VEH_CAL_0 const tS16 c_assINCAR_TG_RR_LV1_SedanL[13] = { 225, 240, 255, 270, 285, 300, 310, 320, 330, 340, 350, 360, 370}; +SECT_VEH_CAL_0 const tS16 c_assVTG_RL_LV1_SedanL[13] = { 115, 105, 95, 80, 65, 60, 55, 50, 50, 50, 50, 52, 55}; +SECT_VEH_CAL_0 const tS16 c_assVTG_RR_LV1_SedanL[13] = { 115, 105, 95, 80, 65, 60, 55, 50, 50, 50, 50, 52, 55}; +SECT_VEH_CAL_0 const tS16 c_assVR_MIN_LV1_SedanL[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_0 const tS16 c_assVR_MAX_LV1_SedanL[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_Y1_LV1_SedanL[7] = { 30, 30, 25, 25, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_Y2_LV1_SedanL[7] = { 15, 13, 10, 8, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_Y3_LV1_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_Y4_LV1_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_X1_LV1_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_X2_LV1_SedanL[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_X3_LV1_SedanL[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_X4_LV1_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assVR_AMB_Y1_LV1_SedanL[7] = { 0, 0, 0, 2, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVR_AMB_Y2_LV1_SedanL[7] = { -15, -15, 10, 15, 15, 5, 15}; +SECT_VEH_CAL_0 const tS16 c_assVR_AMB_X1_LV1_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assVR_AMB_X2_LV1_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assVR_SUN_Y1_LV1_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVR_SUN_Y2_LV1_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVR_SUN_X1_LV1_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assVR_SUN_X2_LV1_SedanL[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_0 const tS16 c_assTG_RL_LV1_SedanL[13] = { 30, 30, 50, 80, 90, 100, 110, 160, 200, 250, 300, 350, 400}; +SECT_VEH_CAL_0 const tS16 c_assTG_RR_LV1_SedanL[13] = { 30, 30, 50, 80, 90, 100, 110, 160, 200, 250, 300, 350, 400}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_MIN_LV1_SedanL[7] = { 20, 20, 20, 20, 50, 50, 50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_MAX_LV1_SedanL[7] = { 400, 400, 450, 500, 600, 600, 600}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_Y1_LV1_SedanL[7] = { -100, -100, -100, -100, -100, -120, -150}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_Y2_LV1_SedanL[7] = { -50, -50, -50, -20, -30, -40, -50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_Y3_LV1_SedanL[7] = { 50, 50, 50, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_Y4_LV1_SedanL[7] = { 200, 200, 200, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_X1_LV1_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_X2_LV1_SedanL[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_X3_LV1_SedanL[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_X4_LV1_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_AMB_Y1_LV1_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_AMB_Y2_LV1_SedanL[7] = { 0, 0, 0, 80, 80, 80, 80}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_AMB_X1_LV1_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_AMB_X2_LV1_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_SUN_Y1_LV1_SedanL[7] = { -15, -15, -15, -5, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_SUN_Y2_LV1_SedanL[7] = { -25, -25, -25, -15, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_SUN_X1_LV1_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_SUN_X2_LV1_SedanL[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_DUCT_TIME_FR_LV1_SedanL[7] = { 600, 600, 600, 600, 600, 600, 600}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_DUCT_TIME_FL_LV1_SedanL[7] = { 600, 600, 600, 600, 600, 600, 600}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_DUCT_RATE_LV1_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_DUCT_MAX_LV1_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_AF_TIME_FR_LV1_SedanL[7] = { 150, 150, 150, 150, 150, 150, 150}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_AF_TIME_FL_LV1_SedanL[7] = { 150, 150, 150, 150, 150, 150, 150}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_AF_RATE_LV1_SedanL[7] = { 2, 2, 2, 2, 2, 2, 2}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_AF_MAX_LV1_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +/* ------------------------------------------Lv1 : End*/ +SECT_VEH_CAL_0 const tS16 c_assINCAR_TG_FL_LV2_SedanL[13] = { 180, 190, 200, 210, 220, 230, 240, 250, 260, 270, 280, 290, 300}; +SECT_VEH_CAL_0 const tS16 c_assINCAR_TG_FR_LV2_SedanL[13] = { 180, 190, 200, 210, 220, 230, 240, 250, 260, 270, 280, 290, 300}; +SECT_VEH_CAL_0 const tS16 c_assVTG_FL_LV2_SedanL[13] = { 80, 70, 60, 58, 55, 55, 55, 55, 55, 58, 63, 70, 75}; +SECT_VEH_CAL_0 const tS16 c_assVTG_FR_LV2_SedanL[13] = { 80, 70, 60, 58, 55, 55, 55, 55, 55, 58, 63, 70, 75}; +SECT_VEH_CAL_0 const tS16 c_assVF_MIN_LV2_SedanL[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_0 const tS16 c_assVF_MAX_LV2_SedanL[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_Y1_LV2_SedanL[7] = { 30, 30, 25, 25, 15, 5, 0}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_Y2_LV2_SedanL[7] = { 10, 7, 5, 5, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_Y3_LV2_SedanL[7] = { 0, 0, 0, 5, 5, 5, 5}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_Y4_LV2_SedanL[7] = { 0, 0, 0, 10, 10, 10, 10}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_X1_LV2_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_X2_LV2_SedanL[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_X3_LV2_SedanL[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_X4_LV2_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assVF_AMB_Y1_LV2_SedanL[7] = { 15, 15, 5, 5, 5, 6, 5}; +SECT_VEH_CAL_0 const tS16 c_assVF_AMB_Y2_LV2_SedanL[7] = { 10, 15, 5, 5, 15, 21, 15}; +SECT_VEH_CAL_0 const tS16 c_assVF_AMB_X1_LV2_SedanL[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_0 const tS16 c_assVF_AMB_X2_LV2_SedanL[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_0 const tS16 c_assVF_SUN_Y1_LV2_SedanL[7] = { 0, 0, 8, 10, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVF_SUN_Y2_LV2_SedanL[7] = { 5, 5, 15, 20, 10, 5, 5}; +SECT_VEH_CAL_0 const tS16 c_assVF_SUN_X1_LV2_SedanL[7] = { 200, 200, 200, 200, 200, 200, 200}; +SECT_VEH_CAL_0 const tS16 c_assVF_SUN_X2_LV2_SedanL[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_0 const tS16 c_assTG_FLU_LV2_SedanL[13] = { 50, 70, 115, 140, 160, 190, 230, 270, 330, 355, 370, 390, 420}; +SECT_VEH_CAL_0 const tS16 c_assTG_FRU_LV2_SedanL[13] = { 50, 70, 115, 140, 160, 190, 230, 270, 330, 355, 370, 390, 420}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_MIN_LV2_SedanL[7] = { 20, 20, 20, 30, 40, 50, 50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_MAX_LV2_SedanL[7] = { 450, 450, 550, 600, 600, 600, 600}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_Y1_LV2_SedanL[7] = { -250, -250, -200, -200, -200, -200, -200}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_Y2_LV2_SedanL[7] = { -70, -60, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_Y3_LV2_SedanL[7] = { 20, 30, 40, 50, 50, 60, 60}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_Y4_LV2_SedanL[7] = { 50, 65, 80, 100, 120, 140, 160}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_X1_LV2_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_X2_LV2_SedanL[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_X3_LV2_SedanL[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_X4_LV2_SedanL[7] = { 150, 150, 150, 150, 150, 150, 150}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_AMB_Y1_LV2_SedanL[7] = { 10, 5, -20, -30, -50, -50, -25}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_AMB_Y2_LV2_SedanL[7] = { 10, 5, -20, -30, -50, -50, -25}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_AMB_X1_LV2_SedanL[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_AMB_X2_LV2_SedanL[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_SUN_Y1_LV2_SedanL[7] = { -10, -20, -20, -30, -30, -30, -30}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_SUN_Y2_LV2_SedanL[7] = { -60, -50, -60, -80, -80, -80, -80}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_SUN_X1_LV2_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_SUN_X2_LV2_SedanL[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_0 const tS16 c_assTG_FLL_LV2_SedanL[13] = { 225, 270, 290, 280, 300, 325, 380, 400, 460, 500, 540, 580, 620}; +SECT_VEH_CAL_0 const tS16 c_assTG_FRL_LV2_SedanL[13] = { 225, 270, 280, 290, 300, 325, 380, 400, 460, 500, 540, 580, 620}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_MIN_LV2_SedanL[7] = { 250, 250, 300, 300, 300, 400, 400}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_MAX_LV2_SedanL[7] = { 450, 450, 500, 800, 800, 800, 800}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_Y1_LV2_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_Y2_LV2_SedanL[7] = { -30, -30, -30, -30, -30, -30, -30}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_Y3_LV2_SedanL[7] = { 30, 40, 50, 50, 60, 80, 80}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_Y4_LV2_SedanL[7] = { 100, 160, 130, 200, 210, 235, 250}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_X1_LV2_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_X2_LV2_SedanL[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_X3_LV2_SedanL[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_X4_LV2_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_AMB_Y1_LV2_SedanL[7] = { -25, -30, -40, -50, -40, -35, -25}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_AMB_Y2_LV2_SedanL[7] = { 40, 50, 50, 20, 40, 50, 60}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_AMB_X1_LV2_SedanL[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_AMB_X2_LV2_SedanL[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_SUN_Y1_LV2_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_SUN_Y2_LV2_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_SUN_X1_LV2_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_SUN_X2_LV2_SedanL[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_0 const tS16 c_assINCAR_TG_RL_LV2_SedanL[13] = { 190, 195, 200, 215, 230, 240, 255, 270, 280, 290, 300, 310, 320}; +SECT_VEH_CAL_0 const tS16 c_assINCAR_TG_RR_LV2_SedanL[13] = { 190, 195, 200, 215, 230, 240, 255, 270, 280, 290, 300, 310, 320}; +SECT_VEH_CAL_0 const tS16 c_assVTG_RL_LV2_SedanL[13] = { 90, 83, 75, 70, 65, 62, 60, 60, 65, 70, 75, 80, 85}; +SECT_VEH_CAL_0 const tS16 c_assVTG_RR_LV2_SedanL[13] = { 90, 83, 75, 70, 65, 62, 60, 60, 65, 70, 75, 80, 85}; +SECT_VEH_CAL_0 const tS16 c_assVR_MIN_LV2_SedanL[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_0 const tS16 c_assVR_MAX_LV2_SedanL[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_Y1_LV2_SedanL[7] = { 30, 30, 30, 30, -10, -20, -20}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_Y2_LV2_SedanL[7] = { 15, 13, 10, 10, -5, -15, -20}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_Y3_LV2_SedanL[7] = { -10, -10, -10, 10, 10, 10, 10}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_Y4_LV2_SedanL[7] = { -30, -30, -30, 30, 30, 30, 30}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_X1_LV2_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_X2_LV2_SedanL[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_X3_LV2_SedanL[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_X4_LV2_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assVR_AMB_Y1_LV2_SedanL[7] = { 10, 12, 10, 5, -5, -20, -15}; +SECT_VEH_CAL_0 const tS16 c_assVR_AMB_Y2_LV2_SedanL[7] = { 10, 5, 0, 0, 5, 10, 5}; +SECT_VEH_CAL_0 const tS16 c_assVR_AMB_X1_LV2_SedanL[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_0 const tS16 c_assVR_AMB_X2_LV2_SedanL[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_0 const tS16 c_assVR_SUN_Y1_LV2_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVR_SUN_Y2_LV2_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVR_SUN_X1_LV2_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assVR_SUN_X2_LV2_SedanL[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_0 const tS16 c_assTG_RL_LV2_SedanL[13] = { 50, 50, 50, 90, 120, 160, 200, 230, 270, 320, 400, 480, 560}; +SECT_VEH_CAL_0 const tS16 c_assTG_RR_LV2_SedanL[13] = { 50, 50, 50, 90, 120, 160, 200, 230, 270, 320, 400, 480, 560}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_MIN_LV2_SedanL[7] = { 20, 20, 20, 20, 380, 400, 400}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_MAX_LV2_SedanL[7] = { 400, 400, 450, 500, 600, 600, 800}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_Y1_LV2_SedanL[7] = { -100, -100, -100, -100, -100, -100, -250}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_Y2_LV2_SedanL[7] = { -40, -40, -40, -30, -50, -80, -100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_Y3_LV2_SedanL[7] = { 50, 50, 50, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_Y4_LV2_SedanL[7] = { 200, 200, 200, 250, 250, 250, 300}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_X1_LV2_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_X2_LV2_SedanL[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_X3_LV2_SedanL[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_X4_LV2_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_AMB_Y1_LV2_SedanL[7] = { -40, -20, -30, -10, 0, -10, -60}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_AMB_Y2_LV2_SedanL[7] = { 0, 0, 0, 0, 30, 25, 20}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_AMB_X1_LV2_SedanL[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_AMB_X2_LV2_SedanL[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_SUN_Y1_LV2_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_SUN_Y2_LV2_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_SUN_X1_LV2_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_SUN_X2_LV2_SedanL[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_DUCT_TIME_FR_LV2_SedanL[7] = { 3600, 3600, 3600, 3600, 3600, 3600, 3600}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_DUCT_TIME_FL_LV2_SedanL[7] = { 3600, 3600, 3600, 3600, 3600, 3600, 3600}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_DUCT_RATE_LV2_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_DUCT_MAX_LV2_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_AF_TIME_FR_LV2_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_AF_TIME_FL_LV2_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_AF_RATE_LV2_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_AF_MAX_LV2_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +/* ------------------------------------------Lv2 : End*/ +SECT_VEH_CAL_0 const tS16 c_assINCAR_TG_FL_LV3_SedanL[13] = { 180, 190, 200, 210, 230, 245, 255, 265, 270, 280, 290, 300, 310}; +SECT_VEH_CAL_0 const tS16 c_assINCAR_TG_FR_LV3_SedanL[13] = { 180, 190, 200, 210, 230, 245, 255, 265, 270, 280, 290, 300, 310}; +SECT_VEH_CAL_0 const tS16 c_assVTG_FL_LV3_SedanL[13] = { 90, 83, 75, 68, 60, 60, 60, 65, 70, 73, 86, 88, 90}; +SECT_VEH_CAL_0 const tS16 c_assVTG_FR_LV3_SedanL[13] = { 90, 83, 75, 68, 60, 60, 60, 65, 70, 73, 86, 88, 90}; +SECT_VEH_CAL_0 const tS16 c_assVF_MIN_LV3_SedanL[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_0 const tS16 c_assVF_MAX_LV3_SedanL[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_Y1_LV3_SedanL[7] = { 15, 15, 25, 25, 15, -30, -60}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_Y2_LV3_SedanL[7] = { 5, 5, 5, 5, 0, -10, -40}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_Y3_LV3_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_Y4_LV3_SedanL[7] = { 0, 0, 0, 5, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_X1_LV3_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_X2_LV3_SedanL[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_X3_LV3_SedanL[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_X4_LV3_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assVF_AMB_Y1_LV3_SedanL[7] = { 0, -2, 0, -2, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVF_AMB_Y2_LV3_SedanL[7] = { -15, -2, 8, 8, 3, -6, -8}; +SECT_VEH_CAL_0 const tS16 c_assVF_AMB_X1_LV3_SedanL[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_0 const tS16 c_assVF_AMB_X2_LV3_SedanL[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_0 const tS16 c_assVF_SUN_Y1_LV3_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVF_SUN_Y2_LV3_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVF_SUN_X1_LV3_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assVF_SUN_X2_LV3_SedanL[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_0 const tS16 c_assTG_FLU_LV3_SedanL[13] = { 50, 90, 140, 200, 250, 285, 320, 350, 400, 435, 460, 470, 480}; +SECT_VEH_CAL_0 const tS16 c_assTG_FRU_LV3_SedanL[13] = { 50, 90, 140, 200, 250, 285, 320, 350, 400, 435, 460, 470, 480}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_MIN_LV3_SedanL[7] = { 20, 20, 20, 30, 200, 200, 250}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_MAX_LV3_SedanL[7] = { 450, 450, 550, 800, 800, 750, 700}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_Y1_LV3_SedanL[7] = { -100, -100, -100, -150, -200, -250, -300}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_Y2_LV3_SedanL[7] = { -30, -30, -50, -50, -50, -50, -100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_Y3_LV3_SedanL[7] = { 50, 50, 40, 70, 50, 30, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_Y4_LV3_SedanL[7] = { 100, 100, 100, 100, 80, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_X1_LV3_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_X2_LV3_SedanL[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_X3_LV3_SedanL[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_X4_LV3_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_AMB_Y1_LV3_SedanL[7] = { -5, -15, -50, -50, -40, -50, -30}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_AMB_Y2_LV3_SedanL[7] = { 70, 30, 5, 5, 0, -40, -45}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_AMB_X1_LV3_SedanL[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_AMB_X2_LV3_SedanL[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_SUN_Y1_LV3_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_SUN_Y2_LV3_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_SUN_X1_LV3_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_SUN_X2_LV3_SedanL[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_0 const tS16 c_assTG_FLL_LV3_SedanL[13] = { 380, 430, 480, 480, 480, 480, 500, 550, 600, 650, 700, 750, 800}; +SECT_VEH_CAL_0 const tS16 c_assTG_FRL_LV3_SedanL[13] = { 380, 430, 480, 480, 480, 480, 500, 550, 600, 650, 700, 750, 800}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_MIN_LV3_SedanL[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_MAX_LV3_SedanL[7] = { 600, 600, 800, 800, 800, 800, 950}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_Y1_LV3_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_Y2_LV3_SedanL[7] = { -50, -50, -30, -30, -50, -50, -50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_Y3_LV3_SedanL[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_Y4_LV3_SedanL[7] = { 250, 300, 160, 200, 400, 400, 400}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_X1_LV3_SedanL[7] = { -100, -100, -100, -100, -120, -130, -150}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_X2_LV3_SedanL[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_X3_LV3_SedanL[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_X4_LV3_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_AMB_Y1_LV3_SedanL[7] = { -115, -145, -115, -115, -105, -115, -120}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_AMB_Y2_LV3_SedanL[7] = { 0, 10, 50, 50, 30, 20, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_AMB_X1_LV3_SedanL[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_AMB_X2_LV3_SedanL[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_SUN_Y1_LV3_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_SUN_Y2_LV3_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_SUN_X1_LV3_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_SUN_X2_LV3_SedanL[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_0 const tS16 c_assINCAR_TG_RL_LV3_SedanL[13] = { 190, 195, 200, 215, 230, 235, 240, 255, 270, 280, 290, 300, 310}; +SECT_VEH_CAL_0 const tS16 c_assINCAR_TG_RR_LV3_SedanL[13] = { 190, 195, 200, 215, 230, 235, 240, 255, 270, 280, 290, 300, 310}; +SECT_VEH_CAL_0 const tS16 c_assVTG_RL_LV3_SedanL[13] = { 110, 100, 90, 80, 70, 60, 55, 65, 80, 85, 90, 90, 90}; +SECT_VEH_CAL_0 const tS16 c_assVTG_RR_LV3_SedanL[13] = { 110, 100, 90, 80, 70, 60, 55, 65, 80, 85, 90, 90, 90}; +SECT_VEH_CAL_0 const tS16 c_assVR_MIN_LV3_SedanL[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_0 const tS16 c_assVR_MAX_LV3_SedanL[7] = { 130, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_Y1_LV3_SedanL[7] = { 40, 40, 40, 40, -30, -40, -40}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_Y2_LV3_SedanL[7] = { 25, 25, 25, 10, 0, -20, -20}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_Y3_LV3_SedanL[7] = { 10, 10, 10, 5, 0, 20, 25}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_Y4_LV3_SedanL[7] = { 20, 20, 20, 30, 50, 50, 50}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_X1_LV3_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_X2_LV3_SedanL[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_X3_LV3_SedanL[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_X4_LV3_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assVR_AMB_Y1_LV3_SedanL[7] = { -10, -10, -3, 0, -10, -5, 0}; +SECT_VEH_CAL_0 const tS16 c_assVR_AMB_Y2_LV3_SedanL[7] = { 5, 10, 15, 15, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVR_AMB_X1_LV3_SedanL[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_0 const tS16 c_assVR_AMB_X2_LV3_SedanL[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_0 const tS16 c_assVR_SUN_Y1_LV3_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVR_SUN_Y2_LV3_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVR_SUN_X1_LV3_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assVR_SUN_X2_LV3_SedanL[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_0 const tS16 c_assTG_RL_LV3_SedanL[13] = { 50, 50, 50, 80, 120, 150, 190, 250, 320, 370, 450, 500, 600}; +SECT_VEH_CAL_0 const tS16 c_assTG_RR_LV3_SedanL[13] = { 50, 50, 50, 80, 120, 150, 190, 250, 320, 370, 450, 500, 600}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_MIN_LV3_SedanL[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_MAX_LV3_SedanL[7] = { 400, 400, 450, 650, 800, 800, 800}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_Y1_LV3_SedanL[7] = { -100, -100, -100, -100, -100, -100, -250}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_Y2_LV3_SedanL[7] = { -50, -50, -50, -50, -50, -80, -100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_Y3_LV3_SedanL[7] = { 50, 50, 50, 50, 80, 80, 80}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_Y4_LV3_SedanL[7] = { 150, 150, 175, 200, 250, 450, 450}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_X1_LV3_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_X2_LV3_SedanL[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_X3_LV3_SedanL[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_X4_LV3_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_AMB_Y1_LV3_SedanL[7] = { 0, 0, 0, 0, -20, -25, -20}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_AMB_Y2_LV3_SedanL[7] = { 0, 0, 30, 40, 10, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_AMB_X1_LV3_SedanL[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_AMB_X2_LV3_SedanL[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_SUN_Y1_LV3_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_SUN_Y2_LV3_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_SUN_X1_LV3_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_SUN_X2_LV3_SedanL[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_DUCT_TIME_FR_LV3_SedanL[7] = { 3600, 3600, 3600, 3600, 3600, 3600, 3600}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_DUCT_TIME_FL_LV3_SedanL[7] = { 3600, 3600, 3600, 3600, 3600, 3600, 3600}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_DUCT_RATE_LV3_SedanL[7] = { 5, 5, 5, 1, 1, 1, 1}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_DUCT_MAX_LV3_SedanL[7] = { 800, 800, 800, 800, 700, 600, 500}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_AF_TIME_FR_LV3_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_AF_TIME_FL_LV3_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_AF_RATE_LV3_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_AF_MAX_LV3_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +/* ------------------------------------------Lv3 : End*/ +SECT_VEH_CAL_0 const tS16 c_assINCAR_TG_FL_LV4_SedanL[13] = { 160, 180, 200, 220, 230, 240, 250, 260, 270, 280, 290, 295, 300}; +SECT_VEH_CAL_0 const tS16 c_assINCAR_TG_FR_LV4_SedanL[13] = { 160, 180, 200, 220, 230, 240, 250, 260, 270, 280, 290, 295, 300}; +SECT_VEH_CAL_0 const tS16 c_assVTG_FL_LV4_SedanL[13] = { 70, 70, 70, 70, 75, 75, 75, 75, 75, 75, 75, 75, 75}; +SECT_VEH_CAL_0 const tS16 c_assVTG_FR_LV4_SedanL[13] = { 70, 70, 70, 70, 75, 75, 75, 75, 75, 75, 75, 75, 75}; +SECT_VEH_CAL_0 const tS16 c_assVF_MIN_LV4_SedanL[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_0 const tS16 c_assVF_MAX_LV4_SedanL[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_Y1_LV4_SedanL[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_Y2_LV4_SedanL[7] = { 7, 7, 7, 7, 7, 7, 7}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_Y3_LV4_SedanL[7] = { 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_Y4_LV4_SedanL[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_X1_LV4_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_X2_LV4_SedanL[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_X3_LV4_SedanL[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_X4_LV4_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assVF_AMB_Y1_LV4_SedanL[7] = { 2, 0, -7, -5, -2, 5, 5}; +SECT_VEH_CAL_0 const tS16 c_assVF_AMB_Y2_LV4_SedanL[7] = { 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_0 const tS16 c_assVF_AMB_X1_LV4_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assVF_AMB_X2_LV4_SedanL[7] = { 150, 150, 150, 150, 150, 150, 150}; +SECT_VEH_CAL_0 const tS16 c_assVF_SUN_Y1_LV4_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVF_SUN_Y2_LV4_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVF_SUN_X1_LV4_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assVF_SUN_X2_LV4_SedanL[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_0 const tS16 c_assTG_FLU_LV4_SedanL[13] = { 150, 180, 200, 230, 260, 295, 335, 355, 365, 370, 380, 380, 390}; +SECT_VEH_CAL_0 const tS16 c_assTG_FRU_LV4_SedanL[13] = { 150, 180, 200, 230, 250, 270, 290, 310, 330, 350, 370, 380, 390}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_MIN_LV4_SedanL[7] = { 20, 20, 20, 30, 200, 200, 250}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_MAX_LV4_SedanL[7] = { 450, 450, 550, 800, 800, 800, 800}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_Y1_LV4_SedanL[7] = { -150, -150, -150, -150, -150, -150, -150}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_Y2_LV4_SedanL[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_Y3_LV4_SedanL[7] = { 60, 60, 60, 60, 60, 60, 60}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_Y4_LV4_SedanL[7] = { 50, 50, 70, 100, 100, 120, 150}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_X1_LV4_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_X2_LV4_SedanL[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_X3_LV4_SedanL[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_X4_LV4_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_AMB_Y1_LV4_SedanL[7] = { -25, -15, -5, -5, 50, 45, 45}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_AMB_Y2_LV4_SedanL[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_AMB_X1_LV4_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_AMB_X2_LV4_SedanL[7] = { 150, 150, 150, 150, 150, 150, 150}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_SUN_Y1_LV4_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_SUN_Y2_LV4_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_SUN_X1_LV4_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_SUN_X2_LV4_SedanL[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_0 const tS16 c_assTG_FLL_LV4_SedanL[13] = { 350, 400, 440, 480, 520, 560, 600, 630, 660, 700, 740, 750, 800}; +SECT_VEH_CAL_0 const tS16 c_assTG_FRL_LV4_SedanL[13] = { 350, 400, 440, 480, 520, 560, 600, 630, 660, 700, 740, 750, 800}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_MIN_LV4_SedanL[7] = { 300, 300, 300, 300, 300, 300, 400}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_MAX_LV4_SedanL[7] = { 600, 600, 800, 800, 800, 900, 900}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_Y1_LV4_SedanL[7] = { -100, -100, -100, -50, -60, -150, -200}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_Y2_LV4_SedanL[7] = { -50, -50, -50, -20, -20, -50, -80}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_Y3_LV4_SedanL[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_Y4_LV4_SedanL[7] = { 200, 200, 200, 200, 200, 200, 200}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_X1_LV4_SedanL[7] = { -100, -100, -100, -100, -100, -200, -150}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_X2_LV4_SedanL[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_X3_LV4_SedanL[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_X4_LV4_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_AMB_Y1_LV4_SedanL[7] = { 30, 30, -10, -40, -25, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_AMB_Y2_LV4_SedanL[7] = { 50, 30, 60, 120, 90, 80, 100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_AMB_X1_LV4_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_AMB_X2_LV4_SedanL[7] = { 150, 150, 150, 150, 150, 150, 150}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_SUN_Y1_LV4_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_SUN_Y2_LV4_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_SUN_X1_LV4_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_SUN_X2_LV4_SedanL[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_0 const tS16 c_assINCAR_TG_RL_LV4_SedanL[13] = { 150, 155, 160, 170, 180, 195, 205, 215, 230, 240, 250, 280, 300}; +SECT_VEH_CAL_0 const tS16 c_assINCAR_TG_RR_LV4_SedanL[13] = { 140, 145, 150, 160, 170, 185, 195, 205, 220, 230, 240, 270, 290}; +SECT_VEH_CAL_0 const tS16 c_assVTG_RL_LV4_SedanL[13] = { 120, 115, 110, 100, 95, 90, 90, 90, 90, 90, 90, 90, 90}; +SECT_VEH_CAL_0 const tS16 c_assVTG_RR_LV4_SedanL[13] = { 120, 115, 110, 100, 95, 90, 90, 90, 90, 90, 90, 90, 90}; +SECT_VEH_CAL_0 const tS16 c_assVR_MIN_LV4_SedanL[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_0 const tS16 c_assVR_MAX_LV4_SedanL[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_Y1_LV4_SedanL[7] = { 30, 30, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_Y2_LV4_SedanL[7] = { 15, 15, 25, 25, 25, 25, 25}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_Y3_LV4_SedanL[7] = { 15, 15, 20, 25, 25, 25, 25}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_Y4_LV4_SedanL[7] = { 20, 30, 40, 40, 40, 45, 60}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_X1_LV4_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_X2_LV4_SedanL[7] = { -30, -30, -30, -30, -30, -30, -30}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_X3_LV4_SedanL[7] = { 30, 30, 30, 30, 30, 30, 30}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_X4_LV4_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assVR_AMB_Y1_LV4_SedanL[7] = { -7, -10, -12, -15, -8, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVR_AMB_Y2_LV4_SedanL[7] = { -10, -20, -25, -25, -5, -5, 0}; +SECT_VEH_CAL_0 const tS16 c_assVR_AMB_X1_LV4_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assVR_AMB_X2_LV4_SedanL[7] = { 150, 150, 150, 150, 150, 150, 150}; +SECT_VEH_CAL_0 const tS16 c_assVR_SUN_Y1_LV4_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVR_SUN_Y2_LV4_SedanL[7] = { 15, 12, 10, 8, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVR_SUN_X1_LV4_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assVR_SUN_X2_LV4_SedanL[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_0 const tS16 c_assTG_RL_LV4_SedanL[13] = { 50, 50, 50, 110, 180, 220, 260, 310, 360, 390, 430, 480, 560}; +SECT_VEH_CAL_0 const tS16 c_assTG_RR_LV4_SedanL[13] = { 50, 50, 50, 110, 180, 220, 260, 310, 360, 390, 430, 480, 560}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_MIN_LV4_SedanL[7] = { 50, 50, 50, 50, 350, 450, 600}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_MAX_LV4_SedanL[7] = { 100, 400, 450, 650, 800, 800, 800}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_Y1_LV4_SedanL[7] = { -60, -60, -80, -80, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_Y2_LV4_SedanL[7] = { -30, -30, -30, -30, -40, -40, -40}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_Y3_LV4_SedanL[7] = { 10, 30, 45, 80, 80, 80, 80}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_Y4_LV4_SedanL[7] = { 40, 80, 150, 400, 400, 400, 400}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_X1_LV4_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_X2_LV4_SedanL[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_X3_LV4_SedanL[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_X4_LV4_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_AMB_Y1_LV4_SedanL[7] = { 0, 0, -30, -30, -10, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_AMB_Y2_LV4_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_AMB_X1_LV4_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_AMB_X2_LV4_SedanL[7] = { 150, 150, 150, 150, 150, 150, 150}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_SUN_Y1_LV4_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_SUN_Y2_LV4_SedanL[7] = { -25, -20, -30, -15, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_SUN_X1_LV4_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_SUN_X2_LV4_SedanL[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_DUCT_TIME_FR_LV4_SedanL[7] = { 1800, 1800, 1800, 1800, 1800, 1800, 1800}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_DUCT_TIME_FL_LV4_SedanL[7] = { 1800, 1800, 1800, 1800, 1800, 1800, 1800}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_DUCT_RATE_LV4_SedanL[7] = { 5, 5, 5, 1, 1, 1, 1}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_DUCT_MAX_LV4_SedanL[7] = { 500, 500, 500, 800, 700, 600, 500}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_AF_TIME_FR_LV4_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_AF_TIME_FL_LV4_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_AF_RATE_LV4_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_AF_MAX_LV4_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +/* ------------------------------------------Lv4 : End*/ +SECT_VEH_CAL_0 const tS16 c_assINCAR_TG_FL_LV5_SedanL[13] = { 180, 190, 200, 210, 230, 235, 240, 250, 270, 290, 310, 330, 350}; +SECT_VEH_CAL_0 const tS16 c_assINCAR_TG_FR_LV5_SedanL[13] = { 180, 190, 200, 210, 230, 235, 240, 250, 270, 290, 310, 330, 350}; +SECT_VEH_CAL_0 const tS16 c_assVTG_FL_LV5_SedanL[13] = { 75, 75, 75, 75, 80, 80, 80, 80, 80, 80, 80, 80, 80}; +SECT_VEH_CAL_0 const tS16 c_assVTG_FR_LV5_SedanL[13] = { 60, 60, 60, 65, 75, 75, 80, 80, 85, 85, 90, 90, 90}; +SECT_VEH_CAL_0 const tS16 c_assVF_MIN_LV5_SedanL[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_0 const tS16 c_assVF_MAX_LV5_SedanL[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_Y1_LV5_SedanL[7] = { 15, 15, 25, 25, 0, -15, -20}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_Y2_LV5_SedanL[7] = { 5, 10, 15, 0, 0, -10, -15}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_Y3_LV5_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_Y4_LV5_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_X1_LV5_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_X2_LV5_SedanL[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_X3_LV5_SedanL[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_0 const tS16 c_assVF_INC_X4_LV5_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assVF_AMB_Y1_LV5_SedanL[7] = { -5, -5, -5, -5, -5, -5, -5}; +SECT_VEH_CAL_0 const tS16 c_assVF_AMB_Y2_LV5_SedanL[7] = { 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_0 const tS16 c_assVF_AMB_X1_LV5_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assVF_AMB_X2_LV5_SedanL[7] = { 150, 150, 150, 150, 150, 150, 150}; +SECT_VEH_CAL_0 const tS16 c_assVF_SUN_Y1_LV5_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVF_SUN_Y2_LV5_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVF_SUN_X1_LV5_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assVF_SUN_X2_LV5_SedanL[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_0 const tS16 c_assTG_FLU_LV5_SedanL[13] = { 170, 200, 220, 250, 280, 315, 355, 375, 385, 390, 400, 400, 410}; +SECT_VEH_CAL_0 const tS16 c_assTG_FRU_LV5_SedanL[13] = { 170, 200, 220, 250, 280, 315, 355, 375, 385, 390, 400, 400, 410}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_MIN_LV5_SedanL[7] = { 20, 20, 20, 30, 200, 200, 250}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_MAX_LV5_SedanL[7] = { 450, 450, 550, 800, 800, 800, 800}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_Y1_LV5_SedanL[7] = { -100, -100, -150, -180, -200, -300, -350}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_Y2_LV5_SedanL[7] = { -30, -30, -70, -80, -65, -65, -65}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_Y3_LV5_SedanL[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_Y4_LV5_SedanL[7] = { 200, 200, 200, 100, 70, 60, 50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_X1_LV5_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_X2_LV5_SedanL[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_X3_LV5_SedanL[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_INC_X4_LV5_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_AMB_Y1_LV5_SedanL[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_AMB_Y2_LV5_SedanL[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_AMB_X1_LV5_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_AMB_X2_LV5_SedanL[7] = { 150, 150, 150, 150, 150, 150, 150}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_SUN_Y1_LV5_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_SUN_Y2_LV5_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_SUN_X1_LV5_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FU_SUN_X2_LV5_SedanL[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_0 const tS16 c_assTG_FLL_LV5_SedanL[13] = { 400, 450, 470, 510, 580, 620, 720, 750, 750, 790, 820, 830, 900}; +SECT_VEH_CAL_0 const tS16 c_assTG_FRL_LV5_SedanL[13] = { 400, 450, 470, 510, 580, 620, 720, 750, 750, 790, 820, 830, 900}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_MIN_LV5_SedanL[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_MAX_LV5_SedanL[7] = { 600, 600, 800, 800, 800, 800, 800}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_Y1_LV5_SedanL[7] = { -100, -100, -100, -50, -60, -150, -200}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_Y2_LV5_SedanL[7] = { -50, -50, -50, -20, -20, -50, -80}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_Y3_LV5_SedanL[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_Y4_LV5_SedanL[7] = { 400, 400, 400, 400, 200, 200, 200}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_X1_LV5_SedanL[7] = { -100, -100, -100, -100, -100, -200, -150}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_X2_LV5_SedanL[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_X3_LV5_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_INC_X4_LV5_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_AMB_Y1_LV5_SedanL[7] = { -50, -30, -60, -120, -90, -80, -100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_AMB_Y2_LV5_SedanL[7] = { 50, 50, 50, 50, 60, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_AMB_X1_LV5_SedanL[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_AMB_X2_LV5_SedanL[7] = { 150, 150, 150, 150, 150, 150, 150}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_SUN_Y1_LV5_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_SUN_Y2_LV5_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_SUN_X1_LV5_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assDTG_FL_SUN_X2_LV5_SedanL[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_0 const tS16 c_assINCAR_TG_RL_LV5_SedanL[13] = { 190, 195, 200, 215, 230, 235, 240, 260, 270, 285, 300, 310, 320}; +SECT_VEH_CAL_0 const tS16 c_assINCAR_TG_RR_LV5_SedanL[13] = { 190, 195, 200, 215, 230, 235, 240, 260, 270, 285, 300, 310, 320}; +SECT_VEH_CAL_0 const tS16 c_assVTG_RL_LV5_SedanL[13] = { 110, 100, 90, 80, 70, 65, 65, 65, 80, 90, 80, 90, 90}; +SECT_VEH_CAL_0 const tS16 c_assVTG_RR_LV5_SedanL[13] = { 110, 100, 90, 80, 70, 65, 65, 65, 80, 90, 80, 90, 90}; +SECT_VEH_CAL_0 const tS16 c_assVR_MIN_LV5_SedanL[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_0 const tS16 c_assVR_MAX_LV5_SedanL[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_Y1_LV5_SedanL[7] = { 80, 80, 80, 60, 60, 60, 60}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_Y2_LV5_SedanL[7] = { 25, 25, 25, 30, 10, 10, 10}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_Y3_LV5_SedanL[7] = { -10, -10, -10, 0, 0, 20, 25}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_Y4_LV5_SedanL[7] = { 20, 20, 20, 30, 50, 50, 50}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_X1_LV5_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_X2_LV5_SedanL[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_X3_LV5_SedanL[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_0 const tS16 c_assVR_INC_X4_LV5_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assVR_AMB_Y1_LV5_SedanL[7] = { 10, 20, 25, 25, 5, 5, 0}; +SECT_VEH_CAL_0 const tS16 c_assVR_AMB_Y2_LV5_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVR_AMB_X1_LV5_SedanL[7] = { -150, -150, -150, -150, -150, -150, -150}; +SECT_VEH_CAL_0 const tS16 c_assVR_AMB_X2_LV5_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assVR_SUN_Y1_LV5_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVR_SUN_Y2_LV5_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assVR_SUN_X1_LV5_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assVR_SUN_X2_LV5_SedanL[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_0 const tS16 c_assTG_RL_LV5_SedanL[13] = { 50, 50, 50, 80, 120, 150, 170, 250, 350, 370, 450, 500, 500}; +SECT_VEH_CAL_0 const tS16 c_assTG_RR_LV5_SedanL[13] = { 50, 50, 50, 80, 120, 150, 170, 250, 350, 370, 450, 500, 500}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_MIN_LV5_SedanL[7] = { 51, 51, 51, 51, 51, 51, 51}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_MAX_LV5_SedanL[7] = { 400, 400, 450, 650, 800, 800, 800}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_Y1_LV5_SedanL[7] = { -100, -100, -100, -100, -100, -100, -250}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_Y2_LV5_SedanL[7] = { -50, -50, -50, -50, -50, -80, -100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_Y3_LV5_SedanL[7] = { 50, 50, 50, 50, 80, 80, 80}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_Y4_LV5_SedanL[7] = { 250, 250, 250, 350, 450, 450, 450}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_X1_LV5_SedanL[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_X2_LV5_SedanL[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_X3_LV5_SedanL[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_INC_X4_LV5_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_AMB_Y1_LV5_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_AMB_Y2_LV5_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_AMB_X1_LV5_SedanL[7] = { -10, -10, -10, -10, -10, -10, -10}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_AMB_X2_LV5_SedanL[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_SUN_Y1_LV5_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_SUN_Y2_LV5_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_SUN_X1_LV5_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assDTG_R_SUN_X2_LV5_SedanL[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_DUCT_TIME_FR_LV5_SedanL[7] = { 3600, 3600, 3600, 3600, 3600, 3600, 3600}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_DUCT_TIME_FL_LV5_SedanL[7] = { 3600, 3600, 3600, 3600, 3600, 3600, 3600}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_DUCT_RATE_LV5_SedanL[7] = { 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_DUCT_MAX_LV5_SedanL[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_AF_TIME_FR_LV5_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_AF_TIME_FL_LV5_SedanL[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_AF_RATE_LV5_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assCORRECT_AF_MAX_LV5_SedanL[7] = { 0, 0, 0, 0, 0, 0, 0}; +/* ------------------------------------------Lv5 : End*/ +SECT_VEH_CAL_0 const tS16 c_assDUCT_TGT_DEF_VALVE_L_SedanL[11] = { 220, 200, 180, 150, 110, 80, 80, 80, 50, 50, 50}; +SECT_VEH_CAL_0 const tS16 c_assDUCT_TGT_DEF_VALVE_R_SedanL[11] = { 220, 220, 180, 150, 110, 80, 80, 80, 50, 50, 50}; +/* ------------------------------------------DuctTgt Increase : End*/ +SECT_VEH_CAL_0 const tS16 c_assAMB_LV_UP_SedanL[5] = { 650, 200, 50, -100, -500}; +SECT_VEH_CAL_0 const tS16 c_assAMB_LV_DN_SedanL[5] = { 700, 250, 100, -50, -450}; +SECT_VEH_CAL_0 const tS16 c_assAMB_LV_TG_SedanL[6] = { 600, 350, 150, 0, -200, -350}; +/* ------------------------------------------Ambient LEVEL : End*/ +SECT_VEH_CAL_0 const tU08 c_aucMODE_BY_SET_F_LV0_SedanL[13] = { 30, 30, 30, 30, 20, 20, 20, 20, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_0 const tU08 c_aucMODE_BY_SET_F_LV1_SedanL[13] = { 30, 30, 30, 30, 30, 30, 30, 30, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_0 const tU08 c_aucMODE_BY_SET_F_LV2_SedanL[13] = { 20, 20, 20, 20, 20, 20, 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_0 const tU08 c_aucMODE_BY_SET_F_LV3_SedanL[13] = { 20, 20, 20, 20, 20, 20, 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_0 const tU08 c_aucMODE_BY_SET_F_LV4_SedanL[13] = { 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_0 const tU08 c_aucMODE_BY_SET_F_LV5_SedanL[13] = { 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_0 const tU16 c_ausMODE_BY_DUCT_TG_R_LV0_SedanL[7] = { 250, 300, 450, 550, 120, 150, 180}; +SECT_VEH_CAL_0 const tU16 c_ausMODE_BY_DUCT_TG_R_LV1_SedanL[7] = { 250, 300, 450, 550, 120, 150, 180}; +SECT_VEH_CAL_0 const tU16 c_ausMODE_BY_DUCT_TG_R_LV2_SedanL[7] = { 250, 300, 450, 550, 120, 150, 180}; +SECT_VEH_CAL_0 const tU16 c_ausMODE_BY_DUCT_TG_R_LV3_SedanL[7] = { 300, 350, 450, 550, 120, 150, 180}; +SECT_VEH_CAL_0 const tU16 c_ausMODE_BY_DUCT_TG_R_LV4_SedanL[7] = { 350, 400, 500, 550, 120, 150, 180}; +SECT_VEH_CAL_0 const tU16 c_ausMODE_BY_DUCT_TG_R_LV5_SedanL[7] = { 300, 350, 450, 550, 120, 150, 180}; +/* ------------------------------------------Mode depend on SET for each level : End*/ +SECT_VEH_CAL_0 const tS16 c_ssPREC_REC_ON_AMB_SedanL = 300; +SECT_VEH_CAL_0 const tS16 c_ssPREC_REC_OFF_AMB_SedanL = 260; +SECT_VEH_CAL_0 const tU08 c_aucPREC_VEH_SPD_OSA_SedanL[13] = { 100, 95, 88, 77, 65, 57, 52, 47, 42, 38, 33, 28, 23}; +SECT_VEH_CAL_0 const tS16 c_assPRE_AMB_RANGE_WINTER_SedanL[7] = { -450, -300, -200, -150, -80, 0, 50}; +SECT_VEH_CAL_0 const tU08 c_aucPREC_OSA_WINTER_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tU08 c_aucPREC_REC_WINTER_SedanL[7] = { 15, 13, 10, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tU16 c_ausPREC_HUMIDITY_NOK_SedanL[7] = { 900, 900, 900, 900, 900, 900, 900}; +SECT_VEH_CAL_0 const tU16 c_ausPREC_HUMIDITY_OK_SedanL[7] = { 700, 700, 700, 700, 700, 700, 700}; +SECT_VEH_CAL_0 const tU16 c_ausPREC_ENTRY_RPM_SedanL[3] = { 450, 550, 800}; +SECT_VEH_CAL_0 const tU16 c_ausPREC_EXIT_RPM_SedanL[3] = { 350, 450, 700}; +SECT_VEH_CAL_0 const tU16 c_ausPREC_COMP_SPD_1_SedanL[3] = { 450, 500, 550}; +SECT_VEH_CAL_0 const tU08 c_aucPREC_OSA_SUMMER_1_SedanL[3] = { 80, 60, 45}; +SECT_VEH_CAL_0 const tU08 c_aucPREC_REC_SUMMER_1_SedanL[3] = { 20, 40, 60}; +SECT_VEH_CAL_0 const tS16 c_assPREC_EVA_DIFF_FB_TG_F_SedanL[7] = { 0, 5, 10, 15, 20, 25, 30}; +SECT_VEH_CAL_0 const tU08 c_aucPREC_OSA_SUMMER_2_SedanL[7] = { 50, 45, 40, 35, 30, 25, 20}; +SECT_VEH_CAL_0 const tU08 c_aucPREC_REC_SUMMER_2_SedanL[7] = { 50, 55, 60, 65, 70, 75, 80}; +SECT_VEH_CAL_0 const tU08 c_aucPREC_EVA_DIFF_SedanL[4] = { 80, 80, 50, 50}; +SECT_VEH_CAL_0 const tU08 c_ucPREC_OSA_SUMMER_3_SedanL = 0; +SECT_VEH_CAL_0 const tU08 c_ucPREC_REC_SUMMER_3_SedanL = 100; +/* ------------------------------------------AutoRec : End*/ +SECT_VEH_CAL_0 const tU16 c_ausFLOW_FR_VE2VALVE_SedanL[9] = { 100, 100, 100, 100, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tU16 c_ausFLOW_FR_BIVALVE_SedanL[9] = { 40, 40, 40, 40, 30, 0, 30, 0, 0}; +SECT_VEH_CAL_0 const tU16 c_ausFLOW_FR_BI2VALVE_SedanL[9] = { 70, 70, 70, 70, 30, 0, 30, 0, 0}; +SECT_VEH_CAL_0 const tU16 c_ausFLOW_FR_AF2VALVE_SedanL[9] = { 35, 25, 25, 35, 30, 0, 30, 0, 0}; +SECT_VEH_CAL_0 const tU16 c_ausFLOW_FR_AF2VALVE_SUMMER_SedanL[9] = { 25, 25, 25, 25, 30, 0, 30, 0, 10}; +SECT_VEH_CAL_0 const tU16 c_ausFLOW_FR_FO2VALVE_SedanL[9] = { 0, 0, 0, 0, 100, 0, 100, 0, 0}; +SECT_VEH_CAL_0 const tU16 c_ausFLOW_FR_FD2VALVE_SedanL[9] = { 0, 0, 0, 0, 100, 0, 100, 0, 100}; +SECT_VEH_CAL_0 const tU16 c_ausFLOW_FR_DE2VALVE_SedanL[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 100}; +SECT_VEH_CAL_0 const tU16 c_ausFLOW_FR_TR2VALVE_SedanL[9] = { 55, 55, 55, 55, 100, 0, 100, 0, 100}; +SECT_VEH_CAL_0 const tU16 c_ausFLOW_FR_HI2VALVE_SedanL[9] = { 50, 50, 50, 50, 0, 0, 0, 0, 100}; +SECT_VEH_CAL_0 const tU16 c_ausFLOW_FR_BIVALVE_MANUAL_SedanL[9] = { 50, 50, 50, 50, 60, 0, 60, 0, 0}; +SECT_VEH_CAL_0 const tU16 c_ausFLOW_RE_VENT_SedanL[6] = { 70, 80, 80, 70, 0, 0}; +SECT_VEH_CAL_0 const tU16 c_ausFLOW_RE_BI2VALVE_SedanL[6] = { 70, 80, 80, 70, 100, 100}; +SECT_VEH_CAL_0 const tU16 c_ausFLOW_RE_FO2VALVE_SedanL[6] = { 0, 20, 20, 0, 100, 100}; +SECT_VEH_CAL_0 const tU16 c_ausFLOW_RE_VENT_2_SedanL[6] = { 30, 60, 60, 30, 50, 50}; +SECT_VEH_CAL_0 const tU16 c_ausFLOW_RE_BI2VALVE_2_SedanL[6] = { 50, 30, 30, 50, 100, 100}; +SECT_VEH_CAL_0 const tU16 c_ausFLOW_RE_VENT_3_SedanL[6] = { 70, 80, 80, 70, 0, 0}; +SECT_VEH_CAL_0 const tU16 c_ausFLOW_RE_BI2VALVE_3_SedanL[6] = { 25, 25, 25, 25, 100, 100}; +SECT_VEH_CAL_0 const tU16 c_ausFLOW_RE_VENT_MANUAL_SedanL[6] = { 70, 80, 80, 70, 0, 0}; +SECT_VEH_CAL_0 const tU16 c_ausFLOW_RE_BI2VALVE_MANUAL_SedanL[6] = { 70, 40, 40, 70, 100, 100}; +/* ------------------------------------------Flow Control Valve: End*/ +SECT_VEH_CAL_0 const tS16 c_assFLOW_BI_AMB_TGT_SedanL[6] = { 450, 350, 150, 0, -150, -350}; +SECT_VEH_CAL_0 const tU08 c_aucFLOW_BI_VENT_PLUS_SedanL[12] = { 10, 10, 10, 0, 0, 0, 10, 10, 10, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assFLOW_BI_TEMP_TGT_SedanL[12] = { 300, 350, 400, 450, 500, 550, 300, 350, 400, 450, 500, 550}; +SECT_VEH_CAL_0 const tU08 c_aucFLOW_BI_FOOT_PLUS_SedanL[12] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_0 const tU08 c_aucFLOW_BI_VENT_VALVE_MAX_SedanL[12] = { 85, 85, 85, 85, 85, 85, 60, 60, 60, 60, 60, 60}; +SECT_VEH_CAL_0 const tU08 c_aucFLOW_BI_FOOT_VALVE_MAX_SedanL[12] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tU08 c_aucFLOW_BI_VENT_VALVE_MIN_SedanL[12] = { 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_0 const tU08 c_aucFLOW_BI_FOOT_VALVE_MIN_SedanL[12] = { 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}; +/* ------------------------------------------Bi 2 level conditions: End*/ +SECT_VEH_CAL_0 const tS16 c_assFLOW_B2I_AMB_TGT_SedanL[6] = { 450, 350, 100, 0, -150, -350}; +SECT_VEH_CAL_0 const tU08 c_aucFLOW_BI2_VENT_PLUS_SedanL[12] = { 20, 20, 0, 0, 0, 0, 20, 20, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assFLOW_BI2_TEMP_TGT_SedanL[12] = { 300, 350, 400, 450, 500, 550, 300, 350, 400, 450, 500, 550}; +SECT_VEH_CAL_0 const tU08 c_aucFLOW_BI2_FOOT_PLUS_SedanL[12] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_0 const tU08 c_aucFLOW_BI2_VENT_VALVE_MAX_SedanL[12] = { 85, 85, 85, 85, 85, 85, 80, 80, 80, 80, 80, 80}; +SECT_VEH_CAL_0 const tU08 c_aucFLOW_BI2_FOOT_VALVE_MAX_SedanL[12] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tU08 c_aucFLOW_BI2_VENT_VALVE_MIN_SedanL[12] = { 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_0 const tU08 c_aucFLOW_BI2_FOOT_VALVE_MIN_SedanL[12] = { 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}; +/* ------------------------------------------AF level conditions: End*/ +SECT_VEH_CAL_0 const tS16 c_assFLOW_AF_AMB_TGT_SedanL[6] = { 450, 350, 100, 0, -150, -350}; +SECT_VEH_CAL_0 const tU08 c_aucFLOW_AF_VENT_PLUS_SedanL[12] = { 0, 0, 10, 10, 0, 0, 0, 0, 10, 10, 0, 0}; +SECT_VEH_CAL_0 const tU08 c_aucFLOW_AF_BLR_AF_TGT_SedanL[6] = { 60, 60, 60, 65, 70, 70}; +SECT_VEH_CAL_0 const tU08 c_aucFLOW_AF_FOOT_PLUS_SedanL[12] = { 20, 20, 20, 100, 150, 150, 20, 20, 20, 100, 150, 150}; +SECT_VEH_CAL_0 const tU08 c_aucFLOW_AF_VENT_VALVE_MAX_SedanL[12] = { 50, 50, 50, 50, 40, 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_0 const tU08 c_aucFLOW_AF_FOOT_VALVE_MAX_SedanL[12] = { 100, 100, 100, 100, 35, 100, 100, 100, 100, 100, 35, 100}; +/* ------------------------------------------AF level conditions: End*/ +SECT_VEH_CAL_0 const tS16 c_assFLOW_AFSM_AMB_TGT_SedanL[6] = { 450, 350, 200, 0, -150, -350}; +SECT_VEH_CAL_0 const tU08 c_aucFLOW_AFSM_VENT_PLUS_SedanL[12] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_0 const tS16 c_assFLOW_AFSM_TEMP_TGT_SedanL[12] = { 300, 350, 400, 450, 500, 550, 300, 350, 400, 450, 500, 550}; +SECT_VEH_CAL_0 const tU08 c_aucFLOW_AFSM_FOOT_PLUS_SedanL[12] = { 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_0 const tU08 c_aucFLOW_AFSM_VENT_VALVE_MAX_SedanL[12] = { 50, 50, 50, 50, 50, 50, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_0 const tU08 c_aucFLOW_AFSM_FOOT_VALVE_MAX_SedanL[12] = { 60, 60, 60, 60, 60, 60, 50, 50, 50, 50, 50, 50}; +/* ------------------------------------------AF_summer level conditions: End*/ +SECT_VEH_CAL_0 const tU08 c_aucMODE_INDEX_SedanL[11] = { 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 110}; +SECT_VEH_CAL_0 const tS16 c_assFOOT_STEP_DUCT_TGT_SedanL[7] = { -400, -250, -100, 0, 100, 250, 400}; +SECT_VEH_CAL_0 const tS16 c_assBLR_FOOT_IND_SedanL[7] = { 25, 10, 5, 0, 5, 10, 25}; +SECT_VEH_CAL_0 const tS08 c_ascFOOT_STEP_VALVE_P1_SedanL[11] = { 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_0 const tS08 c_ascFOOT_STEP_VALVE_P2_SedanL[11] = { 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25}; +SECT_VEH_CAL_0 const tS08 c_ascFOOT_STEP_VALVE_P3_SedanL[11] = { 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_0 const tS08 c_ascFOOT_STEP_VALVE_M1_SedanL[11] = { 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_0 const tS08 c_ascFOOT_STEP_VALVE_M2_SedanL[11] = { 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25}; +SECT_VEH_CAL_0 const tS08 c_ascFOOT_STEP_VALVE_M3_SedanL[11] = { 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_0 const tS16 c_assFOOT_STEP_BLR_P1_SedanL[11] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_0 const tS16 c_assFOOT_STEP_BLR_P2_SedanL[11] = { 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_0 const tS16 c_assFOOT_STEP_BLR_P3_SedanL[11] = { 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 10}; +SECT_VEH_CAL_0 const tS16 c_assFOOT_STEP_BLR_M1_SedanL[11] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_0 const tS16 c_assFOOT_STEP_BLR_M2_SedanL[11] = { 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_0 const tS16 c_assFOOT_STEP_BLR_M3_SedanL[11] = { 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20}; +/* ------------------------------------------Individual foot temperature: End*/ +SECT_VEH_CAL_0 const tU08 c_aucREAR_FOOT_VALVE_AMB_LV2_SedanL[13] = { 0, 0, 0, 0, 0, 0, 5, 10, 15, 20, 25, 30, 35}; +SECT_VEH_CAL_0 const tU08 c_aucREAR_FOOT_VALVE_AMB_LV3_SedanL[13] = { 0, 0, 0, 0, 0, 0, 5, 10, 15, 20, 25, 30, 35}; +SECT_VEH_CAL_0 const tU08 c_aucREAR_FOOT_VALVE_AMB_LV4_SedanL[13] = { 0, 0, 0, 0, 0, 0, 5, 10, 15, 20, 25, 30, 35}; +/* ------------------------------------------Blowing foots from Rear HVAC: End*/ +SECT_VEH_CAL_0 const tU16 c_ausFLOW_FR_VE2BLR_AF_SedanL[8] = { 0, 30, 51, 64, 88, 114, 135, 160}; +SECT_VEH_CAL_0 const tU16 c_ausFLOW_FR_BIVALVE_AF_SedanL[8] = { 0, 30, 51, 64, 88, 114, 135, 160}; +SECT_VEH_CAL_0 const tU16 c_ausFLOW_FR_BI2BLR_AF_SedanL[8] = { 0, 30, 51, 64, 88, 114, 135, 160}; +SECT_VEH_CAL_0 const tU16 c_ausFLOW_FR_FO2BLR_AF_SedanL[8] = { 0, 30, 51, 64, 88, 114, 135, 160}; +SECT_VEH_CAL_0 const tU16 c_ausFLOW_FR_AF2VALVE_AF_SedanL[8] = { 0, 30, 51, 64, 88, 114, 135, 160}; +SECT_VEH_CAL_0 const tU16 c_ausFLOW_FR_AF2VALVE_SUMMER_AF_SedanL[8] = { 0, 30, 51, 64, 88, 114, 135, 160}; +SECT_VEH_CAL_0 const tU16 c_ausFLOW_FR_FD2BLR_AF_SedanL[8] = { 0, 30, 51, 64, 88, 114, 135, 160}; +SECT_VEH_CAL_0 const tU16 c_ausFLOW_FR_DE2BLR_AF_SedanL[8] = { 0, 30, 51, 64, 88, 114, 135, 160}; +SECT_VEH_CAL_0 const tU16 c_ausFLOW_FR_TR2BLR_AF_SedanL[8] = { 0, 30, 51, 64, 88, 114, 135, 160}; +SECT_VEH_CAL_0 const tU16 c_ausFLOW_FR_HI2BLR_AF_SedanL[8] = { 0, 30, 51, 64, 88, 114, 135, 160}; +SECT_VEH_CAL_0 const tU16 c_ausFLOW_RE_VE2BLR_AF_SedanL[8] = { 0, 30, 51, 72, 93, 114, 135, 160}; +SECT_VEH_CAL_0 const tU16 c_ausFLOW_RE_BI2BLR_AF_SedanL[8] = { 0, 30, 51, 72, 93, 114, 135, 160}; +SECT_VEH_CAL_0 const tU16 c_ausFLOW_RE_FO2BLR_AF_SedanL[8] = { 0, 30, 51, 72, 93, 114, 135, 160}; +/* ------------------------------------------Flow Control AF: End*/ +SECT_VEH_CAL_0 const tS08 c_ascAUTO_STEP_AF_F_SedanL[5] = { -25, -13, 0, 15, 30}; +SECT_VEH_CAL_0 const tS08 c_ascAUTO_STEP_AF_R_SedanL[5] = { -25, -13, 0, 15, 30}; +SECT_VEH_CAL_0 const tS16 c_assAUTO_STEP_DUCT_TG_U_F_LV0_1_SedanL[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assAUTO_STEP_DUCT_TG_U_F_LV2_3_SedanL[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assAUTO_STEP_DUCT_TG_U_F_LV4_5_SedanL[10] = { -50, 0, 0, -50, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assAUTO_STEP_DUCT_TG_L_F_LV0_1_SedanL[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assAUTO_STEP_DUCT_TG_L_F_LV2_3_SedanL[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assAUTO_STEP_DUCT_TG_L_F_LV4_5_SedanL[10] = { 50, 50, 0, -128, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assAUTO_STEP_DUCT_TG_R_LV0_1_SedanL[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assAUTO_STEP_DUCT_TG_R_LV2_3_SedanL[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assAUTO_STEP_DUCT_TG_R_LV4_5_SedanL[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +/* ------------------------------------------5 AUTO mode: End*/ +SECT_VEH_CAL_0 const tU16 c_ausVALVE_SPACE_SedanL[6] = { 300, 300, 300, 269, 275, 215}; +SECT_VEH_CAL_0 const tU08 c_aucVALVE_SECTION_S1_F_SIDE_VENT_SedanL[9] = { 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_0 const tU08 c_aucVALVE_SECTION_S1_F_CENT_VENT_SedanL[9] = { 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_0 const tU08 c_aucVALVE_SECTION_S1_F_DRIVER_FOOT_SedanL[9] = { 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_0 const tU08 c_aucVALVE_SECTION_S1_F_RIGHT_PASS_SedanL[9] = { 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_0 const tU08 c_aucBLR_SPD_V1_1_F_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tU08 c_aucBLR_SPD_K2_1_F_SIDE_VENT_SedanL[10] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tU08 c_aucBLR_SPD_K2_2_F_CENT_VENT_SedanL[10] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tU08 c_aucBLR_SPD_K2_3_F_DRIVER_FOOT_SedanL[10] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tU08 c_aucBLR_SPD_K2_4_F_RIGHT_PASS_SedanL[13] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tU16 c_ausVALVE_VEH_SPD_SedanL[13] = { 0, 40, 60, 80, 100, 120, 140, 160, 180, 200, 220, 240, 250}; +SECT_VEH_CAL_0 const tU08 c_aucVALVE_VEH_SPD_SIDE_VENT_SedanL[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_0 const tU08 c_aucVALVE_VEH_SPD_SIDE_BI_SedanL[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_0 const tU08 c_aucVALVE_VEH_SPD_SIDE_AFOOT_SedanL[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_0 const tU08 c_aucVALVE_VEH_SPD_CNET_VENT_SedanL[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_0 const tU08 c_aucVALVE_VEH_SPD_CENT_BI_SedanL[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_0 const tU08 c_aucVALVE_VEH_SPD_CENT_AFOOT_SedanL[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_0 const tU08 c_aucVALVE_VEH_SPD_FOOT_BI_SedanL[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_0 const tU08 c_aucVALVE_VEH_SPD_FOOT_AFOOT_SedanL[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_0 const tU08 c_aucVALVE_VEH_SPD_2FOOT_SedanL[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_0 const tU08 c_aucBLR_SPD_VEH_SPD_V1_3_SedanL[12] = { 100, 70, 30, 100, 70, 30, 100, 70, 30, 100, 70, 30}; +SECT_VEH_CAL_0 const tU08 c_aucFRONT_SIDE_DRS_PERCENT_SedanL[12] = { 100, 70, 30, 100, 70, 30, 100, 70, 30, 100, 70, 30}; +SECT_VEH_CAL_0 const tU08 c_aucFRONT_CENT_DRS_PERCENT_SedanL[12] = { 100, 70, 30, 100, 70, 30, 100, 70, 30, 100, 70, 30}; +/* ------------------------------------------Different blower speed FRONT MODE: End*/ +SECT_VEH_CAL_0 const tU08 c_aucVALVE_S1_R_BIPILLAR_SedanL[8] = { 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_0 const tU08 c_aucVALVE_S1_R_CENT_VENT_SedanL[9] = { 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_0 const tU08 c_aucVALVE_S1_R_FOOT_SedanL[5] = { 10, 10, 10, 10, 10}; +SECT_VEH_CAL_0 const tU08 c_aucVALVE_PERC_R_BIPILLAR_SedanL[10] = { 10, 20, 30, 40, 50, 60, 70, 80, 90, 100}; +SECT_VEH_CAL_0 const tU08 c_aucVALVE_PERC_R_CENT_VENT_SedanL[10] = { 10, 20, 30, 40, 50, 60, 70, 80, 90, 100}; +SECT_VEH_CAL_0 const tU08 c_aucVALVE_PERC_R_FOOT_SedanL[10] = { 10, 20, 30, 40, 50, 60, 70, 80, 90, 100}; +SECT_VEH_CAL_0 const tU08 c_aucBLR_SPD_V1_1_R_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tU08 c_aucREAR_CEN_MIN_VALUE_BY_DRS_ZERO_SedanL[7] = { 30, 29, 28, 27, 24, 22, 20}; +SECT_VEH_CAL_0 const tU08 c_aucBLR_SPD_K2_1_R_BIPILLAR_MIN_SedanL[8] = { 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tU08 c_aucBLR_SPD_K2_2_R_CENT_VENT_MIN_SedanL[9] = { 85, 85, 85, 85, 85, 85, 85, 85, 85}; +SECT_VEH_CAL_0 const tU08 c_aucBLR_SPD_K2_3_R_FOOT_MIN_SedanL[5] = { 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tU08 c_aucBLR_SPD_K2_1_R_BIPILLAR_MAX_SedanL[8] = { 120, 120, 120, 120, 120, 120, 120, 120}; +SECT_VEH_CAL_0 const tU08 c_aucBLR_SPD_K2_2_R_CENT_VENTR_MAX_SedanL[9] = { 122, 122, 122, 122, 122, 122, 122, 122, 122}; +SECT_VEH_CAL_0 const tU08 c_aucBLR_SPD_K2_3_R_FOOTR_MAX_SedanL[5] = { 130, 130, 130, 130, 130}; +SECT_VEH_CAL_0 const tU08 c_aucREAR_SIDE_DRS_PERCENT_VALVE_SedanL[9] = { 100, 70, 30, 100, 70, 30, 100, 70, 30}; +SECT_VEH_CAL_0 const tU08 c_aucREAR_CENT_DRS_PERCENT_VALVE_SedanL[9] = { 100, 70, 30, 100, 70, 30, 100, 70, 30}; +SECT_VEH_CAL_0 const tU08 c_aucREAR_SIDE_DRS_PERCENT_AF_SedanL[9] = { 100, 70, 30, 100, 70, 30, 100, 70, 30}; +SECT_VEH_CAL_0 const tU08 c_aucREAR_CENT_DRS_PERCENT_AF_SedanL[9] = { 100, 70, 30, 100, 70, 30, 100, 70, 30}; +/* ------------------------------------------Different blower speed REAR MODE: End*/ +SECT_VEH_CAL_0 const tU16 c_ausMIN_PWM_SedanL[2] = { 151, 151}; +/* ------------------------------------------MinPWM: End*/ +SECT_VEH_CAL_0 const tS16 c_assSTART_ENTER_COOLANT_SedanL[6] = { 600, 600, 600, 500, 400, 400}; +SECT_VEH_CAL_0 const tS16 c_assSTART_COOLANT_STEP0_TO_1_SedanL[8] = { 0, 400, 400, 400, 300, 400, 400, 400}; +SECT_VEH_CAL_0 const tS16 c_assSTART_COOLANT_TO_STEP2_SedanL[3] = { 800, 800, 850}; +SECT_VEH_CAL_0 const tS16 c_assSTART_COOLANT_STEP1_BLR_F_SedanL[6] = { 0, 0, 0, 700, 650, 650}; +SECT_VEH_CAL_0 const tS16 c_assSTART_COOLANT_STEP1_BLR_R_SedanL[6] = { 0, 0, 700, 600, 600, 600}; +SECT_VEH_CAL_0 const tS16 c_assSTART_ENTER_INCAR_SedanL[12] = { 500, 450, 500, 50, 100, 0, 500, 450, 200, 50, 100, 50}; +SECT_VEH_CAL_0 const tU16 c_ausSTART_ENTER_SETTEMP_SedanL[12] = { 260, 250, 0, 160, 0, 0, 260, 250, 200, 200, 0, 0}; +SECT_VEH_CAL_0 const tU08 c_aucSTART_INCAR_FLT_UP_SedanL[12] = { 20, 20, 20, 20, 40, 20, 20, 20, 20, 20, 40, 20}; +SECT_VEH_CAL_0 const tU08 c_aucSTART_INCAR_FLT_DN_SedanL[12] = { 20, 20, 20, 20, 40, 20, 20, 20, 20, 20, 40, 20}; +SECT_VEH_CAL_0 const tU08 c_aucSTART_VALVE_IDX_STEP1_SedanL[12] = { 10, 10, 10, 70, 70, 70, 120, 120, 140, 140, 140, 140}; +SECT_VEH_CAL_0 const tU08 c_aucSTART_AUTODEMIST2_STEP2_SedanL[6] = { 0, 0, 1, 1, 1, 1}; +SECT_VEH_CAL_0 const tU08 c_aucSTART_ELEC_WINDOW_SedanL[12] = { 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 1, 1}; +SECT_VEH_CAL_0 const tU16 c_ausSTART_BLR_AF_STEP12_F_SedanL[12] = { 160, 100, 120, 60, 60, 60, 140, 100, 100, 140, 140, 140}; +SECT_VEH_CAL_0 const tU16 c_ausSTART_BLR_AF_STEP12_R_SedanL[12] = { 160, 130, 60, 60, 60, 60, 140, 120, 100, 140, 140, 140}; +SECT_VEH_CAL_0 const tU16 c_ausSTART_BLR_SPD_STEP2_F_SedanL[12] = { 5, 1, 1, 1, 1, 1, 2, 5, 2, 3, 3, 4}; +SECT_VEH_CAL_0 const tU16 c_ausSTART_BLR_SPD_STEP2_R_SedanL[12] = { 5, 1, 1, 1, 1, 1, 2, 5, 2, 3, 4, 4}; +SECT_VEH_CAL_0 const tU08 c_aucSTART_DUCT_TGT_STEP2_FX_U_SedanL[12] = { 5, 5, 5, 50, 60, 60, 3, 3, 3, 3, 3, 3}; +SECT_VEH_CAL_0 const tU08 c_aucSTART_DUCT_TGT_STEP2_FX_L_SedanL[12] = { 15, 15, 15, 80, 80, 80, 6, 6, 6, 20, 30, 30}; +SECT_VEH_CAL_0 const tU08 c_aucSTART_DUCT_TGT_STEP2_RX_SedanL[12] = { 5, 5, 30, 60, 60, 80, 3, 3, 3, 6, 6, 6}; +SECT_VEH_CAL_0 const tU08 c_aucSTART_VALVE_CHANGE_SPD_F_SedanL[12] = { 1, 1, 1, 1, 1, 1, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_0 const tU08 c_aucSTART_VALVE_CHANGE_SPD_R_SedanL[12] = { 1, 1, 1, 1, 1, 1, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_0 const tU16 c_ausSTART_TIME_STEP1_TO_2_SedanL[12] = { 720, 720, 180, 1200, 2400, 2400, 720, 720, 1200, 1200, 2400, 2400}; +SECT_VEH_CAL_0 const tU16 c_ausSTART_TIME_STEP2_TO_3_SedanL[12] = { 120, 120, 180, 600, 600, 1200, 240, 240, 600, 600, 360, 360}; +SECT_VEH_CAL_0 const tS16 c_assSTART_INCAR_STEP1_TO_2_SedanL[12] = { 300, 300, 300, 200, 210, 250, 300, 300, 200, 230, 210, 250}; +SECT_VEH_CAL_0 const tS16 c_assSTART_INCAR_STEP2_TO_3_SedanL[12] = { 300, 300, 250, 250, 250, 280, 220, 220, 220, 220, 250, 270}; +SECT_VEH_CAL_0 const tU08 c_aucSTART_3WAY_OPEN_SedanL[12] = { 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1}; +SECT_VEH_CAL_0 const tU08 c_aucSTART_2WAY_OPEN_SedanL[12] = { 0, 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 1}; +SECT_VEH_CAL_0 const tU08 c_aucSTART_TXV_F_SedanL[12] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}; +SECT_VEH_CAL_0 const tU08 c_aucSTART_TXV_R_SedanL[12] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}; +/* ------------------------------------------Start control: End*/ +SECT_VEH_CAL_0 const tS16 c_assFAILURE_AMB_TEMP_SedanL[13] = { -200, -150, -80, -50, 0, 100, 150, 200, 250, 300, 350, 400, 450}; +SECT_VEH_CAL_0 const tS16 c_assAC_PRESSURE_LOW_HYS_UP_SedanL[13] = { 6, 8, 9, 10, 11, 15, 24, 30, 37, 55, 57, 60, 65}; +SECT_VEH_CAL_0 const tS16 c_assAC_PRESSURE_LOW_HYS_DN_SedanL[13] = { 5, 7, 8, 9, 10, 12, 15, 25, 25, 30, 30, 30, 40}; +SECT_VEH_CAL_0 const tS16 c_assAC_LOW_AMB_F_SedanL[2] = { 50, 70}; +SECT_VEH_CAL_0 const tS16 c_assAC_CUT_OFF_AMB_F_SedanL[2] = { -50, -30}; +SECT_VEH_CAL_0 const tS16 c_assAC_WINTER_TXV_DEWPOINT_SedanL[2] = { 40, 30}; +SECT_VEH_CAL_0 const tS16 c_assAC_CUT_OFF_AMB_R_SedanL[2] = { -220, -210}; +SECT_VEH_CAL_0 const tS16 c_assEVA_TG_AMB_F_SedanL[13] = { 100, 100, 80, 80, 80, 60, 50, 40, 30, 30, 25, 25, 25}; +SECT_VEH_CAL_0 const tS16 c_assEVA_TG_AMB_R_SedanL[13] = { 100, 100, 80, 80, 80, 60, 50, 40, 30, 30, 25, 25, 25}; +SECT_VEH_CAL_0 const tU08 c_ucAC_EXTRA_RPM_SedanL = 15; +SECT_VEH_CAL_0 const tS16 c_assAC_EVA_LV_SHUT_OFF_SedanL[2] = { 150, 10}; +SECT_VEH_CAL_0 const tS16 c_assAC_PRESSURE_HYS_HI_ENG_ON_SedanL[3] = { 331, 265, 186}; +SECT_VEH_CAL_0 const tU16 c_usCMP_MAX_ENG_OFF_SedanL = 3000; +SECT_VEH_CAL_0 const tU08 c_ucFAN_MAX_ENG_OFF_SedanL = 15; +SECT_VEH_CAL_0 const tS16 c_ssAC_WINTER_TXV_HYST_SedanL = 15; +SECT_VEH_CAL_0 const tU08 c_aucAC_PRESSURE_HYS_HI_ENG_OFF_SedanL[2] = { 186, 155}; +SECT_VEH_CAL_0 const tU16 c_ausCMP_RPM_RESONANCE_SedanL[6] = { 1500, 1550, 2500, 2560, 7500, 7590}; +/* ------------------------------------------A/C Control Pressure : End*/ +SECT_VEH_CAL_0 const tS16 c_assPRESSURE_TO_FAN_X_SedanL[7] = { 50, 70, 90, 100, 174, 184, 240}; +SECT_VEH_CAL_0 const tU08 c_aucPRESSURE_TO_FAN_Y_SedanL[7] = { 8, 15, 30, 50, 70, 80, 100}; +/* ------------------------------------------CoolingFan: End*/ +SECT_VEH_CAL_0 const tS16 c_ssREST_BATT_SedanL = 109; +SECT_VEH_CAL_0 const tS16 c_ssRESTW_AMB_SedanL = 100; +SECT_VEH_CAL_0 const tS16 c_assRESTW_WATER_SedanL[2] = { 550, 350}; +SECT_VEH_CAL_0 const tU16 c_usRESTW_READYEXPIRETIME_SedanL = 120; +SECT_VEH_CAL_0 const tU08 c_aucRESTW_MODE_SedanL[2] = { 70, 130}; +SECT_VEH_CAL_0 const tU16 c_usRESTW_TIMEOUTTIME_SedanL = 900; +SECT_VEH_CAL_0 const tU08 c_ucRESTW_BLRSTEP_SedanL = 2; +SECT_VEH_CAL_0 const tS16 c_ssRESTS_AMB_SedanL = 100; +SECT_VEH_CAL_0 const tU08 c_uctRESTS_READYEXPIRETIME_SedanL = 120; +SECT_VEH_CAL_0 const tU08 c_aucRESTS_MODE_SedanL[2] = { 70, 130}; +SECT_VEH_CAL_0 const tU16 c_usRESTS_TIMEOUTTIME_SedanL = 600; +SECT_VEH_CAL_0 const tU08 c_ucRESTS_BLRSTEP_SedanL = 3; +/* ------------------------------------------Rest mode: End*/ +SECT_VEH_CAL_0 const tU16 c_usFRESH_AIR_PURGE_ENTRY_TIME_SedanL = 900; +SECT_VEH_CAL_0 const tU16 c_ausFRESH_AIR_PURGE_CHANGE_TIME_SedanL[7] = { 10, 10, 10, 50, 10, 10, 10}; +/* ------------------------------------------Purge Rec: End*/ +SECT_VEH_CAL_0 const tS16 c_assMAX_DEF_U_DTG_SedanL[10] = { 850, 850, 700, 550, 400, 350, 100, 50, 50, 50}; +SECT_VEH_CAL_0 const tU16 c_ausMAX_BLR_SPD_SedanL[6] = { 160, 160, 160, 160, 160, 160}; +/* ------------------------------------------MAX DEF: End*/ +SECT_VEH_CAL_0 const tU08 c_aucAQS_REC_LV_CO_SedanL[8] = { 0, 0, 0, 0, 0, 0, 0, 4}; +SECT_VEH_CAL_0 const tU08 c_aucAQS_OSA_LV_CO_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tU08 c_aucAQS_REC_LV_NOX_SedanL[8] = { 0, 0, 0, 0, 0, 0, 0, 4}; +SECT_VEH_CAL_0 const tU08 c_aucAQS_OSA_LV_NOX_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tU08 c_aucAQS_REC_LV_NH3_SedanL[8] = { 0, 0, 0, 0, 0, 0, 0, 4}; +SECT_VEH_CAL_0 const tU08 c_aucAQS_OSA_LV_NH3_SedanL[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_0 const tU08 c_ucAQS_REC_ON_TIME_SedanL = 30; +SECT_VEH_CAL_0 const tU08 c_aucAQS_REC_ON_WAIT_SedanL[2] = { 60, 10}; +/* ------------------------------------------Aqs: End*/ +SECT_VEH_CAL_0 const tU16 c_usAUTODEMIST_LV2_BLR_PLUS_SedanL = 10; +SECT_VEH_CAL_0 const tU16 c_usAUTODEMIST_LV3_BLR_PLUS_SedanL = 30; +SECT_VEH_CAL_0 const tS16 c_assAUTODEMIST_OFFSET_AMB_TEMP_SedanL[9] = { -50, -30, -20, -10, 0, 10, 20, 30, 50}; +SECT_VEH_CAL_0 const tS16 c_assAUTODEMIST_OFFSET_VENT_TEMP_SedanL[9] = { 22, 18, 15, 11, 8, 8, 7, 5, 5}; +SECT_VEH_CAL_0 const tS16 c_assAUTODEMIST_STEP_UP_SedanL[4] = { 50, 30, 20, -10}; +SECT_VEH_CAL_0 const tS16 c_assAUTODEMIST_STEP_DN_SedanL[4] = { 55, 35, 25, 0}; +SECT_VEH_CAL_0 const tS16 c_assAUTODEMIST_WINTER_SedanL[2] = { -10, -5}; +/* ------------------------------------------Auto Demist: End*/ +SECT_VEH_CAL_0 const tS16 c_ssAUTODEMIST_ELEC_AMB_ENTRY_SedanL = -120; +SECT_VEH_CAL_0 const tS16 c_assAUTODEMIST_ELEC_WINDSHELD_TEMP_SedanL[2] = { -100, -60}; +/* ------------------------------------------Electric AutoDemist: End*/ +SECT_VEH_CAL_0 const tS16 c_ssAMBFILT_WATER_SedanL = 500; +SECT_VEH_CAL_0 const tU08 c_aucAMBFILT_H_CNT_SedanL[2] = { 200, 200}; +SECT_VEH_CAL_0 const tS16 c_ssAMB_FAILSAFE_SedanL = 230; +SECT_VEH_CAL_0 const tS16 c_ssAMBKEEP_KAT_SedanL = 200; +SECT_VEH_CAL_0 const tS16 c_ssAMBKEEP_KAT_PLUS_SedanL = 350; +SECT_VEH_CAL_0 const tS16 c_ssAMBKEEP_WATER_SedanL = 500; +SECT_VEH_CAL_0 const tU08 c_aucAMBRATE_RISING_SedanL[6] = { 30, 30, 30, 30, 30, 30}; +SECT_VEH_CAL_0 const tU08 c_aucAMBRATE_FALLING_SedanL[6] = { 30, 30, 30, 30, 30, 30}; +SECT_VEH_CAL_0 const tU08 c_aucAMBRATE_RISING_DIFF_SedanL[8] = { 120, 120, 120, 120, 155, 155, 155, 50}; +SECT_VEH_CAL_0 const tU08 c_aucAMBRATE_FALLING_DIFF_SedanL[8] = { 120, 120, 120, 255, 255, 255, 155, 50}; +/* ------------------------------------------Ambient: End*/ +SECT_VEH_CAL_0 const tU16 c_ausINCARRATE_RISING_F_SedanL[6] = { 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_0 const tU16 c_ausINCARRATE_FALLING_F_SedanL[6] = { 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_0 const tU16 c_ausINCARRATE_RISING_DIFF_F_SedanL[8] = { 100, 100, 100, 100, 100, 100, 50, 5}; +SECT_VEH_CAL_0 const tU16 c_ausINCARRATE_FALLING_DIFF_F_SedanL[8] = { 40, 40, 40, 40, 40, 40, 50, 5}; +SECT_VEH_CAL_0 const tU16 c_ausINCARRATE_RISING_R_SedanL[6] = { 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_0 const tU16 c_ausINCARRATE_FALLING_R_SedanL[6] = { 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_0 const tU16 c_ausINCARRATE_RISING_DIFF_R_SedanL[8] = { 100, 100, 100, 100, 100, 100, 50, 5}; +SECT_VEH_CAL_0 const tU16 c_ausINCARRATE_FALLING_DIFF_R_SedanL[8] = { 40, 40, 40, 40, 40, 40, 50, 5}; +/* ------------------------------------------Incar: End*/ +SECT_VEH_CAL_0 const tU16 c_ausSUNRATE_RISING_SedanL[6] = { 200, 200, 200, 200, 200, 200}; +SECT_VEH_CAL_0 const tU16 c_ausSUNRATE_FALLING_SedanL[6] = { 200, 200, 200, 200, 200, 200}; +/* ------------------------------------------Sun: End*/ +SECT_VEH_CAL_0 const tU16 c_ausAMB_LV_CHANGE_UNIT_SedanL[6] = { 1, 1, 1, 10, 10, 3}; +SECT_VEH_CAL_0 const tU08 c_aucAMB_LV_CHANGE_SEC_SedanL[6] = { 1, 1, 1, 1, 1, 1}; +/* ------------------------------------------Level Chage: End*/ +SECT_VEH_CAL_0 const tS16 c_ssTHREEWAY_WATER_SedanL = 40; +SECT_VEH_CAL_0 const tS16 c_assTHREEWAY_DUCT_TGT_R_SedanL[2] = { 20, 15}; +SECT_VEH_CAL_0 const tU08 c_aucTHEREEWAY_EXPIRING_SedanL[2] = { 60, 5}; +/* ------------------------------------------Three way: End*/ +SECT_VEH_CAL_0 const tS16 c_assTWOWAY_REAR_DUCTTGT_R_SedanL[2] = { 70, 60}; +SECT_VEH_CAL_0 const tU08 c_aucTWOWAY_EXPIRING_SedanL[2] = { 60, 5}; +/* ------------------------------------------two-way: End*/ +SECT_VEH_CAL_0 const tU08 c_aucACT_HOM_SPD_FL_CH0_SedanL[9] = { 3, 3, 3, 3, 3, 3, 3, 3, 3}; +SECT_VEH_CAL_0 const tU08 c_aucACT_HOM_SPD_FR_CH1_SedanL[6] = { 3, 3, 3, 3, 3, 3}; +SECT_VEH_CAL_0 const tU08 c_aucACT_HOM_SPD_R_CH2_SedanL[9] = { 3, 3, 3, 3, 3, 3, 3, 3, 3}; +SECT_VEH_CAL_0 const tU08 c_aucACT_HOM_SPD_R_EX_CH2_SedanL[4] = { 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tU08 c_aucACT_MOV_SPD_FL_CH0_SedanL[9] = { 3, 3, 3, 3, 3, 3, 3, 3, 3}; +SECT_VEH_CAL_0 const tU08 c_aucACT_MOV_SPD_FR_CH1_SedanL[6] = { 3, 3, 3, 3, 3, 3}; +SECT_VEH_CAL_0 const tU08 c_aucACT_MOV_SPD_R_CH2_SedanL[9] = { 3, 3, 3, 3, 3, 3, 3, 3, 3}; +SECT_VEH_CAL_0 const tU08 c_aucACT_MOV_SPD_R_EX_CH2_SedanL[4] = { 0, 0, 0, 0}; +/* ------------------------------------------Actuator Homing: End*/ +SECT_VEH_CAL_0 const tS16 c_assHI_MODE_ENG_TMEP_SedanL[6] = { 35, 45, 60, 80, 100, 120}; +SECT_VEH_CAL_0 const tU08 c_aucHI_MODE_BLR_STEP_STS_SedanL[6] = { 2, 3, 4, 5, 100, 100}; +/* ------------------------------------------Hi Mode: End*/ +SECT_VEH_CAL_0 const tU16 c_ausMinusAF_GlassPos_L_SedanL[13] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tU16 c_ausMinusAF_GlassPos_R_SedanL[13] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +/* ------------------------------------------GlassPosition: End*/ +SECT_VEH_CAL_0 const tS16 c_assFoot2_Lv3_Amb_SedanL[6] = { -150, -100, -50, 0, 50, 100}; +SECT_VEH_CAL_0 const tS16 c_assFoot2_Lv4_Amb_SedanL[6] = { -300, -250, -200, -150, -100, -50}; +SECT_VEH_CAL_0 const tS16 c_assFoot2_Lv5_Amb_SedanL[6] = { -700, -650, -600, -550, -500, -450}; +SECT_VEH_CAL_0 const tS16 c_assFoot2_Lv3_DuctTgt_Plus_SedanL[6] = { 550, 500, 450, 400, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assFoot2_Lv4_DuctTgt_Plus_SedanL[6] = { 550, 500, 450, 400, 300, 300}; +SECT_VEH_CAL_0 const tS16 c_assFoot2_Lv5_DuctTgt_Plus_SedanL[6] = { 550, 500, 450, 400, 300, 300}; +SECT_VEH_CAL_0 const tU16 c_ausFoot2_Lv1_FrontBlr_X_SedanL[3] = { 250, 500, 750}; +SECT_VEH_CAL_0 const tU16 c_ausFoot2_Lv1_Foot2Act_Y_SedanL[3] = { 250, 500, 750}; +SECT_VEH_CAL_0 const tS16 c_assFoot2_Lv2_Threshold_Diff_SedanL[2] = { 50, 35}; +SECT_VEH_CAL_0 const tS16 c_assFoot2_Lv3_Threshold_Diff_SedanL[2] = { 50, 35}; +/* ------------------------------------------Foot2 Ctrl: End*/ +SECT_VEH_CAL_0 const tU16 c_ausDbF_Side_Af_Bi_SedanL[9] = { 90, 91, 92, 93, 94, 95, 96, 97, 98}; +SECT_VEH_CAL_0 const tU16 c_ausDbF_Side_Af_Bi2_SedanL[9] = { 90, 91, 92, 93, 94, 95, 96, 97, 98}; +SECT_VEH_CAL_0 const tU16 c_ausDbF_Side_Af_Vent_SedanL[9] = { 70, 70, 65, 65, 62, 60, 55, 50, 50}; +SECT_VEH_CAL_0 const tU16 c_ausDbF_Side_Bi_Bi2_SedanL[9] = { 80, 80, 80, 80, 80, 80, 80, 80, 80}; +SECT_VEH_CAL_0 const tU16 c_ausDbF_Side_Bi_Vent_SedanL[9] = { 65, 55, 45, 40, 38, 35, 32, 30, 25}; +SECT_VEH_CAL_0 const tU16 c_ausDbF_Side_Bi2_Vent_SedanL[9] = { 80, 80, 80, 80, 80, 80, 80, 80, 80}; +SECT_VEH_CAL_0 const tU16 c_ausDbF_Cen_Af_Bi_SedanL[9] = { 90, 91, 92, 93, 94, 95, 96, 97, 98}; +SECT_VEH_CAL_0 const tU16 c_ausDbF_Cen_Af_Bi2_SedanL[9] = { 90, 91, 92, 93, 94, 95, 96, 97, 98}; +SECT_VEH_CAL_0 const tU16 c_ausDbF_Cen_Af_Vent_SedanL[9] = { 70, 70, 70, 65, 62, 60, 55, 50, 50}; +SECT_VEH_CAL_0 const tU16 c_ausDbF_Cen_Bi_Bi2_SedanL[9] = { 80, 80, 80, 80, 80, 80, 80, 80, 80}; +SECT_VEH_CAL_0 const tU16 c_ausDbF_Cen_Bi_Vent_SedanL[9] = { 65, 55, 45, 40, 38, 35, 32, 30, 25}; +SECT_VEH_CAL_0 const tU16 c_ausDbF_Cen_Bi2_Vent_SedanL[9] = { 80, 80, 80, 80, 80, 80, 80, 80, 80}; +SECT_VEH_CAL_0 const tU16 c_ausDbF_Foot_Af_Bi_SedanL[9] = { 90, 91, 92, 93, 94, 95, 96, 97, 98}; +SECT_VEH_CAL_0 const tU16 c_ausDbF_Foot_Af_Bi2_SedanL[9] = { 90, 91, 92, 93, 94, 95, 96, 97, 98}; +SECT_VEH_CAL_0 const tU16 c_ausDbF_Foot_Af_Vent_SedanL[9] = { 70, 70, 70, 65, 62, 60, 55, 50, 50}; +SECT_VEH_CAL_0 const tU16 c_ausDbF_Foot_Bi_Bi2_SedanL[9] = { 80, 80, 80, 80, 80, 80, 80, 80, 80}; +SECT_VEH_CAL_0 const tU16 c_ausDbF_Foot_Bi_Vent_SedanL[9] = { 65, 65, 65, 65, 65, 65, 65, 65, 65}; +SECT_VEH_CAL_0 const tU16 c_ausDbF_Foot_Bi2_Vent_SedanL[9] = { 80, 80, 80, 80, 80, 80, 80, 80, 80}; +SECT_VEH_CAL_0 const tU16 c_ausDbF_AF_Af_Bi_SedanL[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tU16 c_ausDbF_AF_Af_Bi2_SedanL[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tU16 c_ausDbF_AF_Af_Vent_SedanL[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tU16 c_ausDbF_AF_Bi_Bi2_SedanL[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tU16 c_ausDbF_AF_Bi_Vent_SedanL[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tU16 c_ausDbF_AF_Bi2_Vent_SedanL[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_0 const tU16 c_ausDbF_Pwm_Af_Bi_SedanL[9] = { 120, 120, 120, 120, 120, 120, 120, 120, 120}; +SECT_VEH_CAL_0 const tU16 c_ausDbF_Pwm_Af_Bi2_SedanL[9] = { 120, 120, 120, 120, 120, 120, 120, 120, 120}; +SECT_VEH_CAL_0 const tU16 c_ausDbF_Pwm_Af_Vent_SedanL[9] = { 120, 120, 85, 120, 120, 120, 120, 120, 120}; +SECT_VEH_CAL_0 const tU16 c_ausDbF_Pwm_Bi_Bi2_SedanL[9] = { 120, 120, 120, 120, 120, 120, 120, 120, 120}; +SECT_VEH_CAL_0 const tU16 c_ausDbF_Pwm_Bi_Vent_SedanL[9] = { 120, 120, 120, 120, 120, 120, 120, 120, 120}; +SECT_VEH_CAL_0 const tU16 c_ausDbF_Pwm_Bi2_Vent_SedanL[9] = { 105, 120, 120, 90, 120, 120, 120, 105, 90}; +/* ------------------------------------------Different blower Front: End*/ +SECT_VEH_CAL_0 const tU16 c_usAromaPwm_Min_SedanL = 200; +SECT_VEH_CAL_0 const tU16 c_usAromaPwm_Max_SedanL = 700; +/* ------------------------------------------Aroma Limit Pwm: End*/ + +SECT_VEH_CAL_0 const tS16 c_assPID_COMPRESSOR_SedanL[6] = { 60, 1000, 0, 100, 1, 1}; +SECT_VEH_CAL_0 const tS16 c_assPID_VALVE_FRONT_UP_SedanL[6] = { 5, 0, 0, 0, 200, -200 }; +SECT_VEH_CAL_0 const tS16 c_assPID_VALVE_FRONT_LOW_SedanL[6] = { 95, 22, 5, 0, 200, -200 }; +SECT_VEH_CAL_0 const tS16 c_assPID2_VALVE_FRONT_SedanL[6] = { 20, 1, 0, 100, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assPID_VALVE_REAR_SedanL[6] = { 95, 22, 5, 0, 200, -200 }; +SECT_VEH_CAL_0 const tS16 c_assPID2_VALVE_REAR_SedanL[6] = { 20, 1, 0, 100, 0, 0}; +SECT_VEH_CAL_0 const tS16 c_assPID_VALVE_TG_SedanL[15 ] = {0, 0, 0,7,18,20,30,35,40,45, 50,55, 70, 85, 100}; +SECT_VEH_CAL_0 const tS16 c_assPID_VALVE_SPEED_SedanL[6] = { 0, 5, 15, 30, 50, 100}; +/* ------------------------------------------PID: End*/ + +SECT_VEH_CAL_0 const tU08 c_aucFRONT_SIDE_DRS_PERCENT_AF_SedanL[12] = { 100, 70, 30, 100, 70, 30, 100, 70, 30, 100, 70, 30}; +SECT_VEH_CAL_0 const tU08 c_aucFRONT_CENT_DRS_PERCENT_AF_SedanL[12] = { 100, 70, 30, 100, 70, 30, 100, 70, 30, 100, 70, 30}; + + +/*********************************************************Cal Table End*/ + +/****************************************************************************** + * LOCAL VARIABLES DECLARATIONS + *****************************************************************************/ +/****************************************************************************** + * LOCAL FUNCTIONS DECLARATIONS + *****************************************************************************/ +/****************************************************************************** + * GLOBAL FUNCTIONS + *****************************************************************************/ + +/** Doxygen: Function brief + ****************************************************************************** + * @fn Rs_Cal_0_SedanL(void) + * @brief No brief + * @remark No description + * @param[in] (All of const data in this file) + * @param[out] All of global variable in Rs_Cal_Base.c + * @return None + *****************************************************************************/ +void Rs_Cal_0_SedanL(void) +{ + M_MEMCOPY((g_aucCAL_FP_DATE), (c_aucCAL_FP_DATE_SedanL)); + M_MEMCOPY((g_aucCAL_VERSION), (c_aucCAL_VERSION_SedanL)); + g_ucCAL_VARIANT = c_ucCAL_VARIANT_SedanL; +/* ------------------------------------------Cal Version : End*/ + M_MEMCOPY((g_ausSET_TEMP_FULL), (c_ausSET_TEMP_FULL_SedanL)); + M_MEMCOPY((g_ausSET_TEMP_HALF), (c_ausSET_TEMP_HALF_SedanL)); +/* ------------------------------------------Set Temp : End*/ + M_MEMCOPY((g_assINCAR_TG_FL_LV0), (c_assINCAR_TG_FL_LV0_SedanL)); + M_MEMCOPY((g_assINCAR_TG_FR_LV0), (c_assINCAR_TG_FR_LV0_SedanL)); + M_MEMCOPY((g_assVTG_FL_LV0), (c_assVTG_FL_LV0_SedanL)); + M_MEMCOPY((g_assVTG_FR_LV0), (c_assVTG_FR_LV0_SedanL)); + M_MEMCOPY((g_assVF_MIN_LV0), (c_assVF_MIN_LV0_SedanL)); + M_MEMCOPY((g_assVF_MAX_LV0), (c_assVF_MAX_LV0_SedanL)); + M_MEMCOPY((g_assVF_INC_Y1_LV0), (c_assVF_INC_Y1_LV0_SedanL)); + M_MEMCOPY((g_assVF_INC_Y2_LV0), (c_assVF_INC_Y2_LV0_SedanL)); + M_MEMCOPY((g_assVF_INC_Y3_LV0), (c_assVF_INC_Y3_LV0_SedanL)); + M_MEMCOPY((g_assVF_INC_Y4_LV0), (c_assVF_INC_Y4_LV0_SedanL)); + M_MEMCOPY((g_assVF_INC_X1_LV0), (c_assVF_INC_X1_LV0_SedanL)); + M_MEMCOPY((g_assVF_INC_X2_LV0), (c_assVF_INC_X2_LV0_SedanL)); + M_MEMCOPY((g_assVF_INC_X3_LV0), (c_assVF_INC_X3_LV0_SedanL)); + M_MEMCOPY((g_assVF_INC_X4_LV0), (c_assVF_INC_X4_LV0_SedanL)); + M_MEMCOPY((g_assVF_AMB_Y1_LV0), (c_assVF_AMB_Y1_LV0_SedanL)); + M_MEMCOPY((g_assVF_AMB_Y2_LV0), (c_assVF_AMB_Y2_LV0_SedanL)); + M_MEMCOPY((g_assVF_AMB_X1_LV0), (c_assVF_AMB_X1_LV0_SedanL)); + M_MEMCOPY((g_assVF_AMB_X2_LV0), (c_assVF_AMB_X2_LV0_SedanL)); + M_MEMCOPY((g_assVF_SUN_Y1_LV0), (c_assVF_SUN_Y1_LV0_SedanL)); + M_MEMCOPY((g_assVF_SUN_Y2_LV0), (c_assVF_SUN_Y2_LV0_SedanL)); + M_MEMCOPY((g_assVF_SUN_X1_LV0), (c_assVF_SUN_X1_LV0_SedanL)); + M_MEMCOPY((g_assVF_SUN_X2_LV0), (c_assVF_SUN_X2_LV0_SedanL)); + M_MEMCOPY((g_assTG_FLU_LV0), (c_assTG_FLU_LV0_SedanL)); + M_MEMCOPY((g_assTG_FRU_LV0), (c_assTG_FRU_LV0_SedanL)); + M_MEMCOPY((g_assDTG_FU_MIN_LV0), (c_assDTG_FU_MIN_LV0_SedanL)); + M_MEMCOPY((g_assDTG_FU_MAX_LV0), (c_assDTG_FU_MAX_LV0_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_Y1_LV0), (c_assDTG_FU_INC_Y1_LV0_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_Y2_LV0), (c_assDTG_FU_INC_Y2_LV0_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_Y3_LV0), (c_assDTG_FU_INC_Y3_LV0_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_Y4_LV0), (c_assDTG_FU_INC_Y4_LV0_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_X1_LV0), (c_assDTG_FU_INC_X1_LV0_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_X2_LV0), (c_assDTG_FU_INC_X2_LV0_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_X3_LV0), (c_assDTG_FU_INC_X3_LV0_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_X4_LV0), (c_assDTG_FU_INC_X4_LV0_SedanL)); + M_MEMCOPY((g_assDTG_FU_AMB_Y1_LV0), (c_assDTG_FU_AMB_Y1_LV0_SedanL)); + M_MEMCOPY((g_assDTG_FU_AMB_Y2_LV0), (c_assDTG_FU_AMB_Y2_LV0_SedanL)); + M_MEMCOPY((g_assDTG_FU_AMB_X1_LV0), (c_assDTG_FU_AMB_X1_LV0_SedanL)); + M_MEMCOPY((g_assDTG_FU_AMB_X2_LV0), (c_assDTG_FU_AMB_X2_LV0_SedanL)); + M_MEMCOPY((g_assDTG_FU_SUN_Y1_LV0), (c_assDTG_FU_SUN_Y1_LV0_SedanL)); + M_MEMCOPY((g_assDTG_FU_SUN_Y2_LV0), (c_assDTG_FU_SUN_Y2_LV0_SedanL)); + M_MEMCOPY((g_assDTG_FU_SUN_X1_LV0), (c_assDTG_FU_SUN_X1_LV0_SedanL)); + M_MEMCOPY((g_assDTG_FU_SUN_X2_LV0), (c_assDTG_FU_SUN_X2_LV0_SedanL)); + M_MEMCOPY((g_assTG_FLL_LV0), (c_assTG_FLL_LV0_SedanL)); + M_MEMCOPY((g_assTG_FRL_LV0), (c_assTG_FRL_LV0_SedanL)); + M_MEMCOPY((g_assDTG_FL_MIN_LV0), (c_assDTG_FL_MIN_LV0_SedanL)); + M_MEMCOPY((g_assDTG_FL_MAX_LV0), (c_assDTG_FL_MAX_LV0_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_Y1_LV0), (c_assDTG_FL_INC_Y1_LV0_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_Y2_LV0), (c_assDTG_FL_INC_Y2_LV0_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_Y3_LV0), (c_assDTG_FL_INC_Y3_LV0_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_Y4_LV0), (c_assDTG_FL_INC_Y4_LV0_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_X1_LV0), (c_assDTG_FL_INC_X1_LV0_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_X2_LV0), (c_assDTG_FL_INC_X2_LV0_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_X3_LV0), (c_assDTG_FL_INC_X3_LV0_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_X4_LV0), (c_assDTG_FL_INC_X4_LV0_SedanL)); + M_MEMCOPY((g_assDTG_FL_AMB_Y1_LV0), (c_assDTG_FL_AMB_Y1_LV0_SedanL)); + M_MEMCOPY((g_assDTG_FL_AMB_Y2_LV0), (c_assDTG_FL_AMB_Y2_LV0_SedanL)); + M_MEMCOPY((g_assDTG_FL_AMB_X1_LV0), (c_assDTG_FL_AMB_X1_LV0_SedanL)); + M_MEMCOPY((g_assDTG_FL_AMB_X2_LV0), (c_assDTG_FL_AMB_X2_LV0_SedanL)); + M_MEMCOPY((g_assDTG_FL_SUN_Y1_LV0), (c_assDTG_FL_SUN_Y1_LV0_SedanL)); + M_MEMCOPY((g_assDTG_FL_SUN_Y2_LV0), (c_assDTG_FL_SUN_Y2_LV0_SedanL)); + M_MEMCOPY((g_assDTG_FL_SUN_X1_LV0), (c_assDTG_FL_SUN_X1_LV0_SedanL)); + M_MEMCOPY((g_assDTG_FL_SUN_X2_LV0), (c_assDTG_FL_SUN_X2_LV0_SedanL)); + M_MEMCOPY((g_assINCAR_TG_RL_LV0), (c_assINCAR_TG_RL_LV0_SedanL)); + M_MEMCOPY((g_assINCAR_TG_RR_LV0), (c_assINCAR_TG_RR_LV0_SedanL)); + M_MEMCOPY((g_assVTG_RL_LV0), (c_assVTG_RL_LV0_SedanL)); + M_MEMCOPY((g_assVTG_RR_LV0), (c_assVTG_RR_LV0_SedanL)); + M_MEMCOPY((g_assVR_MIN_LV0), (c_assVR_MIN_LV0_SedanL)); + M_MEMCOPY((g_assVR_MAX_LV0), (c_assVR_MAX_LV0_SedanL)); + M_MEMCOPY((g_assVR_INC_Y1_LV0), (c_assVR_INC_Y1_LV0_SedanL)); + M_MEMCOPY((g_assVR_INC_Y2_LV0), (c_assVR_INC_Y2_LV0_SedanL)); + M_MEMCOPY((g_assVR_INC_Y3_LV0), (c_assVR_INC_Y3_LV0_SedanL)); + M_MEMCOPY((g_assVR_INC_Y4_LV0), (c_assVR_INC_Y4_LV0_SedanL)); + M_MEMCOPY((g_assVR_INC_X1_LV0), (c_assVR_INC_X1_LV0_SedanL)); + M_MEMCOPY((g_assVR_INC_X2_LV0), (c_assVR_INC_X2_LV0_SedanL)); + M_MEMCOPY((g_assVR_INC_X3_LV0), (c_assVR_INC_X3_LV0_SedanL)); + M_MEMCOPY((g_assVR_INC_X4_LV0), (c_assVR_INC_X4_LV0_SedanL)); + M_MEMCOPY((g_assVR_AMB_Y1_LV0), (c_assVR_AMB_Y1_LV0_SedanL)); + M_MEMCOPY((g_assVR_AMB_Y2_LV0), (c_assVR_AMB_Y2_LV0_SedanL)); + M_MEMCOPY((g_assVR_AMB_X1_LV0), (c_assVR_AMB_X1_LV0_SedanL)); + M_MEMCOPY((g_assVR_AMB_X2_LV0), (c_assVR_AMB_X2_LV0_SedanL)); + M_MEMCOPY((g_assVR_SUN_Y1_LV0), (c_assVR_SUN_Y1_LV0_SedanL)); + M_MEMCOPY((g_assVR_SUN_Y2_LV0), (c_assVR_SUN_Y2_LV0_SedanL)); + M_MEMCOPY((g_assVR_SUN_X1_LV0), (c_assVR_SUN_X1_LV0_SedanL)); + M_MEMCOPY((g_assVR_SUN_X2_LV0), (c_assVR_SUN_X2_LV0_SedanL)); + M_MEMCOPY((g_assTG_RL_LV0), (c_assTG_RL_LV0_SedanL)); + M_MEMCOPY((g_assTG_RR_LV0), (c_assTG_RR_LV0_SedanL)); + M_MEMCOPY((g_assDTG_R_MIN_LV0), (c_assDTG_R_MIN_LV0_SedanL)); + M_MEMCOPY((g_assDTG_R_MAX_LV0), (c_assDTG_R_MAX_LV0_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_Y1_LV0), (c_assDTG_R_INC_Y1_LV0_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_Y2_LV0), (c_assDTG_R_INC_Y2_LV0_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_Y3_LV0), (c_assDTG_R_INC_Y3_LV0_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_Y4_LV0), (c_assDTG_R_INC_Y4_LV0_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_X1_LV0), (c_assDTG_R_INC_X1_LV0_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_X2_LV0), (c_assDTG_R_INC_X2_LV0_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_X3_LV0), (c_assDTG_R_INC_X3_LV0_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_X4_LV0), (c_assDTG_R_INC_X4_LV0_SedanL)); + M_MEMCOPY((g_assDTG_R_AMB_Y1_LV0), (c_assDTG_R_AMB_Y1_LV0_SedanL)); + M_MEMCOPY((g_assDTG_R_AMB_Y2_LV0), (c_assDTG_R_AMB_Y2_LV0_SedanL)); + M_MEMCOPY((g_assDTG_R_AMB_X1_LV0), (c_assDTG_R_AMB_X1_LV0_SedanL)); + M_MEMCOPY((g_assDTG_R_AMB_X2_LV0), (c_assDTG_R_AMB_X2_LV0_SedanL)); + M_MEMCOPY((g_assDTG_R_SUN_Y1_LV0), (c_assDTG_R_SUN_Y1_LV0_SedanL)); + M_MEMCOPY((g_assDTG_R_SUN_Y2_LV0), (c_assDTG_R_SUN_Y2_LV0_SedanL)); + M_MEMCOPY((g_assDTG_R_SUN_X1_LV0), (c_assDTG_R_SUN_X1_LV0_SedanL)); + M_MEMCOPY((g_assDTG_R_SUN_X2_LV0), (c_assDTG_R_SUN_X2_LV0_SedanL)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FR_LV0), (c_assCORRECT_DUCT_TIME_FR_LV0_SedanL)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FL_LV0), (c_assCORRECT_DUCT_TIME_FL_LV0_SedanL)); + M_MEMCOPY((g_assCORRECT_DUCT_RATE_LV0), (c_assCORRECT_DUCT_RATE_LV0_SedanL)); + M_MEMCOPY((g_assCORRECT_DUCT_MAX_LV0), (c_assCORRECT_DUCT_MAX_LV0_SedanL)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FR_LV0), (c_assCORRECT_AF_TIME_FR_LV0_SedanL)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FL_LV0), (c_assCORRECT_AF_TIME_FL_LV0_SedanL)); + M_MEMCOPY((g_assCORRECT_AF_RATE_LV0), (c_assCORRECT_AF_RATE_LV0_SedanL)); + M_MEMCOPY((g_assCORRECT_AF_MAX_LV0), (c_assCORRECT_AF_MAX_LV0_SedanL)); +/* ------------------------------------------Lv0 : End*/ + M_MEMCOPY((g_assINCAR_TG_FL_LV1), (c_assINCAR_TG_FL_LV1_SedanL)); + M_MEMCOPY((g_assINCAR_TG_FR_LV1), (c_assINCAR_TG_FR_LV1_SedanL)); + M_MEMCOPY((g_assVTG_FL_LV1), (c_assVTG_FL_LV1_SedanL)); + M_MEMCOPY((g_assVTG_FR_LV1), (c_assVTG_FR_LV1_SedanL)); + M_MEMCOPY((g_assVF_MIN_LV1), (c_assVF_MIN_LV1_SedanL)); + M_MEMCOPY((g_assVF_MAX_LV1), (c_assVF_MAX_LV1_SedanL)); + M_MEMCOPY((g_assVF_INC_Y1_LV1), (c_assVF_INC_Y1_LV1_SedanL)); + M_MEMCOPY((g_assVF_INC_Y2_LV1), (c_assVF_INC_Y2_LV1_SedanL)); + M_MEMCOPY((g_assVF_INC_Y3_LV1), (c_assVF_INC_Y3_LV1_SedanL)); + M_MEMCOPY((g_assVF_INC_Y4_LV1), (c_assVF_INC_Y4_LV1_SedanL)); + M_MEMCOPY((g_assVF_INC_X1_LV1), (c_assVF_INC_X1_LV1_SedanL)); + M_MEMCOPY((g_assVF_INC_X2_LV1), (c_assVF_INC_X2_LV1_SedanL)); + M_MEMCOPY((g_assVF_INC_X3_LV1), (c_assVF_INC_X3_LV1_SedanL)); + M_MEMCOPY((g_assVF_INC_X4_LV1), (c_assVF_INC_X4_LV1_SedanL)); + M_MEMCOPY((g_assVF_AMB_Y1_LV1), (c_assVF_AMB_Y1_LV1_SedanL)); + M_MEMCOPY((g_assVF_AMB_Y2_LV1), (c_assVF_AMB_Y2_LV1_SedanL)); + M_MEMCOPY((g_assVF_AMB_X1_LV1), (c_assVF_AMB_X1_LV1_SedanL)); + M_MEMCOPY((g_assVF_AMB_X2_LV1), (c_assVF_AMB_X2_LV1_SedanL)); + M_MEMCOPY((g_assVF_SUN_Y1_LV1), (c_assVF_SUN_Y1_LV1_SedanL)); + M_MEMCOPY((g_assVF_SUN_Y2_LV1), (c_assVF_SUN_Y2_LV1_SedanL)); + M_MEMCOPY((g_assVF_SUN_X1_LV1), (c_assVF_SUN_X1_LV1_SedanL)); + M_MEMCOPY((g_assVF_SUN_X2_LV1), (c_assVF_SUN_X2_LV1_SedanL)); + M_MEMCOPY((g_assTG_FLU_LV1), (c_assTG_FLU_LV1_SedanL)); + M_MEMCOPY((g_assTG_FRU_LV1), (c_assTG_FRU_LV1_SedanL)); + M_MEMCOPY((g_assDTG_FU_MIN_LV1), (c_assDTG_FU_MIN_LV1_SedanL)); + M_MEMCOPY((g_assDTG_FU_MAX_LV1), (c_assDTG_FU_MAX_LV1_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_Y1_LV1), (c_assDTG_FU_INC_Y1_LV1_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_Y2_LV1), (c_assDTG_FU_INC_Y2_LV1_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_Y3_LV1), (c_assDTG_FU_INC_Y3_LV1_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_Y4_LV1), (c_assDTG_FU_INC_Y4_LV1_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_X1_LV1), (c_assDTG_FU_INC_X1_LV1_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_X2_LV1), (c_assDTG_FU_INC_X2_LV1_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_X3_LV1), (c_assDTG_FU_INC_X3_LV1_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_X4_LV1), (c_assDTG_FU_INC_X4_LV1_SedanL)); + M_MEMCOPY((g_assDTG_FU_AMB_Y1_LV1), (c_assDTG_FU_AMB_Y1_LV1_SedanL)); + M_MEMCOPY((g_assDTG_FU_AMB_Y2_LV1), (c_assDTG_FU_AMB_Y2_LV1_SedanL)); + M_MEMCOPY((g_assDTG_FU_AMB_X1_LV1), (c_assDTG_FU_AMB_X1_LV1_SedanL)); + M_MEMCOPY((g_assDTG_FU_AMB_X2_LV1), (c_assDTG_FU_AMB_X2_LV1_SedanL)); + M_MEMCOPY((g_assDTG_FU_SUN_Y1_LV1), (c_assDTG_FU_SUN_Y1_LV1_SedanL)); + M_MEMCOPY((g_assDTG_FU_SUN_Y2_LV1), (c_assDTG_FU_SUN_Y2_LV1_SedanL)); + M_MEMCOPY((g_assDTG_FU_SUN_X1_LV1), (c_assDTG_FU_SUN_X1_LV1_SedanL)); + M_MEMCOPY((g_assDTG_FU_SUN_X2_LV1), (c_assDTG_FU_SUN_X2_LV1_SedanL)); + M_MEMCOPY((g_assTG_FLL_LV1), (c_assTG_FLL_LV1_SedanL)); + M_MEMCOPY((g_assTG_FRL_LV1), (c_assTG_FRL_LV1_SedanL)); + M_MEMCOPY((g_assDTG_FL_MIN_LV1), (c_assDTG_FL_MIN_LV1_SedanL)); + M_MEMCOPY((g_assDTG_FL_MAX_LV1), (c_assDTG_FL_MAX_LV1_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_Y1_LV1), (c_assDTG_FL_INC_Y1_LV1_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_Y2_LV1), (c_assDTG_FL_INC_Y2_LV1_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_Y3_LV1), (c_assDTG_FL_INC_Y3_LV1_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_Y4_LV1), (c_assDTG_FL_INC_Y4_LV1_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_X1_LV1), (c_assDTG_FL_INC_X1_LV1_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_X2_LV1), (c_assDTG_FL_INC_X2_LV1_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_X3_LV1), (c_assDTG_FL_INC_X3_LV1_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_X4_LV1), (c_assDTG_FL_INC_X4_LV1_SedanL)); + M_MEMCOPY((g_assDTG_FL_AMB_Y1_LV1), (c_assDTG_FL_AMB_Y1_LV1_SedanL)); + M_MEMCOPY((g_assDTG_FL_AMB_Y2_LV1), (c_assDTG_FL_AMB_Y2_LV1_SedanL)); + M_MEMCOPY((g_assDTG_FL_AMB_X1_LV1), (c_assDTG_FL_AMB_X1_LV1_SedanL)); + M_MEMCOPY((g_assDTG_FL_AMB_X2_LV1), (c_assDTG_FL_AMB_X2_LV1_SedanL)); + M_MEMCOPY((g_assDTG_FL_SUN_Y1_LV1), (c_assDTG_FL_SUN_Y1_LV1_SedanL)); + M_MEMCOPY((g_assDTG_FL_SUN_Y2_LV1), (c_assDTG_FL_SUN_Y2_LV1_SedanL)); + M_MEMCOPY((g_assDTG_FL_SUN_X1_LV1), (c_assDTG_FL_SUN_X1_LV1_SedanL)); + M_MEMCOPY((g_assDTG_FL_SUN_X2_LV1), (c_assDTG_FL_SUN_X2_LV1_SedanL)); + M_MEMCOPY((g_assINCAR_TG_RL_LV1), (c_assINCAR_TG_RL_LV1_SedanL)); + M_MEMCOPY((g_assINCAR_TG_RR_LV1), (c_assINCAR_TG_RR_LV1_SedanL)); + M_MEMCOPY((g_assVTG_RL_LV1), (c_assVTG_RL_LV1_SedanL)); + M_MEMCOPY((g_assVTG_RR_LV1), (c_assVTG_RR_LV1_SedanL)); + M_MEMCOPY((g_assVR_MIN_LV1), (c_assVR_MIN_LV1_SedanL)); + M_MEMCOPY((g_assVR_MAX_LV1), (c_assVR_MAX_LV1_SedanL)); + M_MEMCOPY((g_assVR_INC_Y1_LV1), (c_assVR_INC_Y1_LV1_SedanL)); + M_MEMCOPY((g_assVR_INC_Y2_LV1), (c_assVR_INC_Y2_LV1_SedanL)); + M_MEMCOPY((g_assVR_INC_Y3_LV1), (c_assVR_INC_Y3_LV1_SedanL)); + M_MEMCOPY((g_assVR_INC_Y4_LV1), (c_assVR_INC_Y4_LV1_SedanL)); + M_MEMCOPY((g_assVR_INC_X1_LV1), (c_assVR_INC_X1_LV1_SedanL)); + M_MEMCOPY((g_assVR_INC_X2_LV1), (c_assVR_INC_X2_LV1_SedanL)); + M_MEMCOPY((g_assVR_INC_X3_LV1), (c_assVR_INC_X3_LV1_SedanL)); + M_MEMCOPY((g_assVR_INC_X4_LV1), (c_assVR_INC_X4_LV1_SedanL)); + M_MEMCOPY((g_assVR_AMB_Y1_LV1), (c_assVR_AMB_Y1_LV1_SedanL)); + M_MEMCOPY((g_assVR_AMB_Y2_LV1), (c_assVR_AMB_Y2_LV1_SedanL)); + M_MEMCOPY((g_assVR_AMB_X1_LV1), (c_assVR_AMB_X1_LV1_SedanL)); + M_MEMCOPY((g_assVR_AMB_X2_LV1), (c_assVR_AMB_X2_LV1_SedanL)); + M_MEMCOPY((g_assVR_SUN_Y1_LV1), (c_assVR_SUN_Y1_LV1_SedanL)); + M_MEMCOPY((g_assVR_SUN_Y2_LV1), (c_assVR_SUN_Y2_LV1_SedanL)); + M_MEMCOPY((g_assVR_SUN_X1_LV1), (c_assVR_SUN_X1_LV1_SedanL)); + M_MEMCOPY((g_assVR_SUN_X2_LV1), (c_assVR_SUN_X2_LV1_SedanL)); + M_MEMCOPY((g_assTG_RL_LV1), (c_assTG_RL_LV1_SedanL)); + M_MEMCOPY((g_assTG_RR_LV1), (c_assTG_RR_LV1_SedanL)); + M_MEMCOPY((g_assDTG_R_MIN_LV1), (c_assDTG_R_MIN_LV1_SedanL)); + M_MEMCOPY((g_assDTG_R_MAX_LV1), (c_assDTG_R_MAX_LV1_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_Y1_LV1), (c_assDTG_R_INC_Y1_LV1_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_Y2_LV1), (c_assDTG_R_INC_Y2_LV1_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_Y3_LV1), (c_assDTG_R_INC_Y3_LV1_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_Y4_LV1), (c_assDTG_R_INC_Y4_LV1_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_X1_LV1), (c_assDTG_R_INC_X1_LV1_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_X2_LV1), (c_assDTG_R_INC_X2_LV1_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_X3_LV1), (c_assDTG_R_INC_X3_LV1_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_X4_LV1), (c_assDTG_R_INC_X4_LV1_SedanL)); + M_MEMCOPY((g_assDTG_R_AMB_Y1_LV1), (c_assDTG_R_AMB_Y1_LV1_SedanL)); + M_MEMCOPY((g_assDTG_R_AMB_Y2_LV1), (c_assDTG_R_AMB_Y2_LV1_SedanL)); + M_MEMCOPY((g_assDTG_R_AMB_X1_LV1), (c_assDTG_R_AMB_X1_LV1_SedanL)); + M_MEMCOPY((g_assDTG_R_AMB_X2_LV1), (c_assDTG_R_AMB_X2_LV1_SedanL)); + M_MEMCOPY((g_assDTG_R_SUN_Y1_LV1), (c_assDTG_R_SUN_Y1_LV1_SedanL)); + M_MEMCOPY((g_assDTG_R_SUN_Y2_LV1), (c_assDTG_R_SUN_Y2_LV1_SedanL)); + M_MEMCOPY((g_assDTG_R_SUN_X1_LV1), (c_assDTG_R_SUN_X1_LV1_SedanL)); + M_MEMCOPY((g_assDTG_R_SUN_X2_LV1), (c_assDTG_R_SUN_X2_LV1_SedanL)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FR_LV1), (c_assCORRECT_DUCT_TIME_FR_LV1_SedanL)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FL_LV1), (c_assCORRECT_DUCT_TIME_FL_LV1_SedanL)); + M_MEMCOPY((g_assCORRECT_DUCT_RATE_LV1), (c_assCORRECT_DUCT_RATE_LV1_SedanL)); + M_MEMCOPY((g_assCORRECT_DUCT_MAX_LV1), (c_assCORRECT_DUCT_MAX_LV1_SedanL)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FR_LV1), (c_assCORRECT_AF_TIME_FR_LV1_SedanL)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FL_LV1), (c_assCORRECT_AF_TIME_FL_LV1_SedanL)); + M_MEMCOPY((g_assCORRECT_AF_RATE_LV1), (c_assCORRECT_AF_RATE_LV1_SedanL)); + M_MEMCOPY((g_assCORRECT_AF_MAX_LV1), (c_assCORRECT_AF_MAX_LV1_SedanL)); +/* ------------------------------------------Lv1 : End*/ + M_MEMCOPY((g_assINCAR_TG_FL_LV2), (c_assINCAR_TG_FL_LV2_SedanL)); + M_MEMCOPY((g_assINCAR_TG_FR_LV2), (c_assINCAR_TG_FR_LV2_SedanL)); + M_MEMCOPY((g_assVTG_FL_LV2), (c_assVTG_FL_LV2_SedanL)); + M_MEMCOPY((g_assVTG_FR_LV2), (c_assVTG_FR_LV2_SedanL)); + M_MEMCOPY((g_assVF_MIN_LV2), (c_assVF_MIN_LV2_SedanL)); + M_MEMCOPY((g_assVF_MAX_LV2), (c_assVF_MAX_LV2_SedanL)); + M_MEMCOPY((g_assVF_INC_Y1_LV2), (c_assVF_INC_Y1_LV2_SedanL)); + M_MEMCOPY((g_assVF_INC_Y2_LV2), (c_assVF_INC_Y2_LV2_SedanL)); + M_MEMCOPY((g_assVF_INC_Y3_LV2), (c_assVF_INC_Y3_LV2_SedanL)); + M_MEMCOPY((g_assVF_INC_Y4_LV2), (c_assVF_INC_Y4_LV2_SedanL)); + M_MEMCOPY((g_assVF_INC_X1_LV2), (c_assVF_INC_X1_LV2_SedanL)); + M_MEMCOPY((g_assVF_INC_X2_LV2), (c_assVF_INC_X2_LV2_SedanL)); + M_MEMCOPY((g_assVF_INC_X3_LV2), (c_assVF_INC_X3_LV2_SedanL)); + M_MEMCOPY((g_assVF_INC_X4_LV2), (c_assVF_INC_X4_LV2_SedanL)); + M_MEMCOPY((g_assVF_AMB_Y1_LV2), (c_assVF_AMB_Y1_LV2_SedanL)); + M_MEMCOPY((g_assVF_AMB_Y2_LV2), (c_assVF_AMB_Y2_LV2_SedanL)); + M_MEMCOPY((g_assVF_AMB_X1_LV2), (c_assVF_AMB_X1_LV2_SedanL)); + M_MEMCOPY((g_assVF_AMB_X2_LV2), (c_assVF_AMB_X2_LV2_SedanL)); + M_MEMCOPY((g_assVF_SUN_Y1_LV2), (c_assVF_SUN_Y1_LV2_SedanL)); + M_MEMCOPY((g_assVF_SUN_Y2_LV2), (c_assVF_SUN_Y2_LV2_SedanL)); + M_MEMCOPY((g_assVF_SUN_X1_LV2), (c_assVF_SUN_X1_LV2_SedanL)); + M_MEMCOPY((g_assVF_SUN_X2_LV2), (c_assVF_SUN_X2_LV2_SedanL)); + M_MEMCOPY((g_assTG_FLU_LV2), (c_assTG_FLU_LV2_SedanL)); + M_MEMCOPY((g_assTG_FRU_LV2), (c_assTG_FRU_LV2_SedanL)); + M_MEMCOPY((g_assDTG_FU_MIN_LV2), (c_assDTG_FU_MIN_LV2_SedanL)); + M_MEMCOPY((g_assDTG_FU_MAX_LV2), (c_assDTG_FU_MAX_LV2_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_Y1_LV2), (c_assDTG_FU_INC_Y1_LV2_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_Y2_LV2), (c_assDTG_FU_INC_Y2_LV2_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_Y3_LV2), (c_assDTG_FU_INC_Y3_LV2_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_Y4_LV2), (c_assDTG_FU_INC_Y4_LV2_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_X1_LV2), (c_assDTG_FU_INC_X1_LV2_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_X2_LV2), (c_assDTG_FU_INC_X2_LV2_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_X3_LV2), (c_assDTG_FU_INC_X3_LV2_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_X4_LV2), (c_assDTG_FU_INC_X4_LV2_SedanL)); + M_MEMCOPY((g_assDTG_FU_AMB_Y1_LV2), (c_assDTG_FU_AMB_Y1_LV2_SedanL)); + M_MEMCOPY((g_assDTG_FU_AMB_Y2_LV2), (c_assDTG_FU_AMB_Y2_LV2_SedanL)); + M_MEMCOPY((g_assDTG_FU_AMB_X1_LV2), (c_assDTG_FU_AMB_X1_LV2_SedanL)); + M_MEMCOPY((g_assDTG_FU_AMB_X2_LV2), (c_assDTG_FU_AMB_X2_LV2_SedanL)); + M_MEMCOPY((g_assDTG_FU_SUN_Y1_LV2), (c_assDTG_FU_SUN_Y1_LV2_SedanL)); + M_MEMCOPY((g_assDTG_FU_SUN_Y2_LV2), (c_assDTG_FU_SUN_Y2_LV2_SedanL)); + M_MEMCOPY((g_assDTG_FU_SUN_X1_LV2), (c_assDTG_FU_SUN_X1_LV2_SedanL)); + M_MEMCOPY((g_assDTG_FU_SUN_X2_LV2), (c_assDTG_FU_SUN_X2_LV2_SedanL)); + M_MEMCOPY((g_assTG_FLL_LV2), (c_assTG_FLL_LV2_SedanL)); + M_MEMCOPY((g_assTG_FRL_LV2), (c_assTG_FRL_LV2_SedanL)); + M_MEMCOPY((g_assDTG_FL_MIN_LV2), (c_assDTG_FL_MIN_LV2_SedanL)); + M_MEMCOPY((g_assDTG_FL_MAX_LV2), (c_assDTG_FL_MAX_LV2_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_Y1_LV2), (c_assDTG_FL_INC_Y1_LV2_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_Y2_LV2), (c_assDTG_FL_INC_Y2_LV2_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_Y3_LV2), (c_assDTG_FL_INC_Y3_LV2_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_Y4_LV2), (c_assDTG_FL_INC_Y4_LV2_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_X1_LV2), (c_assDTG_FL_INC_X1_LV2_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_X2_LV2), (c_assDTG_FL_INC_X2_LV2_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_X3_LV2), (c_assDTG_FL_INC_X3_LV2_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_X4_LV2), (c_assDTG_FL_INC_X4_LV2_SedanL)); + M_MEMCOPY((g_assDTG_FL_AMB_Y1_LV2), (c_assDTG_FL_AMB_Y1_LV2_SedanL)); + M_MEMCOPY((g_assDTG_FL_AMB_Y2_LV2), (c_assDTG_FL_AMB_Y2_LV2_SedanL)); + M_MEMCOPY((g_assDTG_FL_AMB_X1_LV2), (c_assDTG_FL_AMB_X1_LV2_SedanL)); + M_MEMCOPY((g_assDTG_FL_AMB_X2_LV2), (c_assDTG_FL_AMB_X2_LV2_SedanL)); + M_MEMCOPY((g_assDTG_FL_SUN_Y1_LV2), (c_assDTG_FL_SUN_Y1_LV2_SedanL)); + M_MEMCOPY((g_assDTG_FL_SUN_Y2_LV2), (c_assDTG_FL_SUN_Y2_LV2_SedanL)); + M_MEMCOPY((g_assDTG_FL_SUN_X1_LV2), (c_assDTG_FL_SUN_X1_LV2_SedanL)); + M_MEMCOPY((g_assDTG_FL_SUN_X2_LV2), (c_assDTG_FL_SUN_X2_LV2_SedanL)); + M_MEMCOPY((g_assINCAR_TG_RL_LV2), (c_assINCAR_TG_RL_LV2_SedanL)); + M_MEMCOPY((g_assINCAR_TG_RR_LV2), (c_assINCAR_TG_RR_LV2_SedanL)); + M_MEMCOPY((g_assVTG_RL_LV2), (c_assVTG_RL_LV2_SedanL)); + M_MEMCOPY((g_assVTG_RR_LV2), (c_assVTG_RR_LV2_SedanL)); + M_MEMCOPY((g_assVR_MIN_LV2), (c_assVR_MIN_LV2_SedanL)); + M_MEMCOPY((g_assVR_MAX_LV2), (c_assVR_MAX_LV2_SedanL)); + M_MEMCOPY((g_assVR_INC_Y1_LV2), (c_assVR_INC_Y1_LV2_SedanL)); + M_MEMCOPY((g_assVR_INC_Y2_LV2), (c_assVR_INC_Y2_LV2_SedanL)); + M_MEMCOPY((g_assVR_INC_Y3_LV2), (c_assVR_INC_Y3_LV2_SedanL)); + M_MEMCOPY((g_assVR_INC_Y4_LV2), (c_assVR_INC_Y4_LV2_SedanL)); + M_MEMCOPY((g_assVR_INC_X1_LV2), (c_assVR_INC_X1_LV2_SedanL)); + M_MEMCOPY((g_assVR_INC_X2_LV2), (c_assVR_INC_X2_LV2_SedanL)); + M_MEMCOPY((g_assVR_INC_X3_LV2), (c_assVR_INC_X3_LV2_SedanL)); + M_MEMCOPY((g_assVR_INC_X4_LV2), (c_assVR_INC_X4_LV2_SedanL)); + M_MEMCOPY((g_assVR_AMB_Y1_LV2), (c_assVR_AMB_Y1_LV2_SedanL)); + M_MEMCOPY((g_assVR_AMB_Y2_LV2), (c_assVR_AMB_Y2_LV2_SedanL)); + M_MEMCOPY((g_assVR_AMB_X1_LV2), (c_assVR_AMB_X1_LV2_SedanL)); + M_MEMCOPY((g_assVR_AMB_X2_LV2), (c_assVR_AMB_X2_LV2_SedanL)); + M_MEMCOPY((g_assVR_SUN_Y1_LV2), (c_assVR_SUN_Y1_LV2_SedanL)); + M_MEMCOPY((g_assVR_SUN_Y2_LV2), (c_assVR_SUN_Y2_LV2_SedanL)); + M_MEMCOPY((g_assVR_SUN_X1_LV2), (c_assVR_SUN_X1_LV2_SedanL)); + M_MEMCOPY((g_assVR_SUN_X2_LV2), (c_assVR_SUN_X2_LV2_SedanL)); + M_MEMCOPY((g_assTG_RL_LV2), (c_assTG_RL_LV2_SedanL)); + M_MEMCOPY((g_assTG_RR_LV2), (c_assTG_RR_LV2_SedanL)); + M_MEMCOPY((g_assDTG_R_MIN_LV2), (c_assDTG_R_MIN_LV2_SedanL)); + M_MEMCOPY((g_assDTG_R_MAX_LV2), (c_assDTG_R_MAX_LV2_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_Y1_LV2), (c_assDTG_R_INC_Y1_LV2_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_Y2_LV2), (c_assDTG_R_INC_Y2_LV2_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_Y3_LV2), (c_assDTG_R_INC_Y3_LV2_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_Y4_LV2), (c_assDTG_R_INC_Y4_LV2_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_X1_LV2), (c_assDTG_R_INC_X1_LV2_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_X2_LV2), (c_assDTG_R_INC_X2_LV2_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_X3_LV2), (c_assDTG_R_INC_X3_LV2_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_X4_LV2), (c_assDTG_R_INC_X4_LV2_SedanL)); + M_MEMCOPY((g_assDTG_R_AMB_Y1_LV2), (c_assDTG_R_AMB_Y1_LV2_SedanL)); + M_MEMCOPY((g_assDTG_R_AMB_Y2_LV2), (c_assDTG_R_AMB_Y2_LV2_SedanL)); + M_MEMCOPY((g_assDTG_R_AMB_X1_LV2), (c_assDTG_R_AMB_X1_LV2_SedanL)); + M_MEMCOPY((g_assDTG_R_AMB_X2_LV2), (c_assDTG_R_AMB_X2_LV2_SedanL)); + M_MEMCOPY((g_assDTG_R_SUN_Y1_LV2), (c_assDTG_R_SUN_Y1_LV2_SedanL)); + M_MEMCOPY((g_assDTG_R_SUN_Y2_LV2), (c_assDTG_R_SUN_Y2_LV2_SedanL)); + M_MEMCOPY((g_assDTG_R_SUN_X1_LV2), (c_assDTG_R_SUN_X1_LV2_SedanL)); + M_MEMCOPY((g_assDTG_R_SUN_X2_LV2), (c_assDTG_R_SUN_X2_LV2_SedanL)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FR_LV2), (c_assCORRECT_DUCT_TIME_FR_LV2_SedanL)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FL_LV2), (c_assCORRECT_DUCT_TIME_FL_LV2_SedanL)); + M_MEMCOPY((g_assCORRECT_DUCT_RATE_LV2), (c_assCORRECT_DUCT_RATE_LV2_SedanL)); + M_MEMCOPY((g_assCORRECT_DUCT_MAX_LV2), (c_assCORRECT_DUCT_MAX_LV2_SedanL)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FR_LV2), (c_assCORRECT_AF_TIME_FR_LV2_SedanL)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FL_LV2), (c_assCORRECT_AF_TIME_FL_LV2_SedanL)); + M_MEMCOPY((g_assCORRECT_AF_RATE_LV2), (c_assCORRECT_AF_RATE_LV2_SedanL)); + M_MEMCOPY((g_assCORRECT_AF_MAX_LV2), (c_assCORRECT_AF_MAX_LV2_SedanL)); +/* ------------------------------------------Lv2 : End*/ + M_MEMCOPY((g_assINCAR_TG_FL_LV3), (c_assINCAR_TG_FL_LV3_SedanL)); + M_MEMCOPY((g_assINCAR_TG_FR_LV3), (c_assINCAR_TG_FR_LV3_SedanL)); + M_MEMCOPY((g_assVTG_FL_LV3), (c_assVTG_FL_LV3_SedanL)); + M_MEMCOPY((g_assVTG_FR_LV3), (c_assVTG_FR_LV3_SedanL)); + M_MEMCOPY((g_assVF_MIN_LV3), (c_assVF_MIN_LV3_SedanL)); + M_MEMCOPY((g_assVF_MAX_LV3), (c_assVF_MAX_LV3_SedanL)); + M_MEMCOPY((g_assVF_INC_Y1_LV3), (c_assVF_INC_Y1_LV3_SedanL)); + M_MEMCOPY((g_assVF_INC_Y2_LV3), (c_assVF_INC_Y2_LV3_SedanL)); + M_MEMCOPY((g_assVF_INC_Y3_LV3), (c_assVF_INC_Y3_LV3_SedanL)); + M_MEMCOPY((g_assVF_INC_Y4_LV3), (c_assVF_INC_Y4_LV3_SedanL)); + M_MEMCOPY((g_assVF_INC_X1_LV3), (c_assVF_INC_X1_LV3_SedanL)); + M_MEMCOPY((g_assVF_INC_X2_LV3), (c_assVF_INC_X2_LV3_SedanL)); + M_MEMCOPY((g_assVF_INC_X3_LV3), (c_assVF_INC_X3_LV3_SedanL)); + M_MEMCOPY((g_assVF_INC_X4_LV3), (c_assVF_INC_X4_LV3_SedanL)); + M_MEMCOPY((g_assVF_AMB_Y1_LV3), (c_assVF_AMB_Y1_LV3_SedanL)); + M_MEMCOPY((g_assVF_AMB_Y2_LV3), (c_assVF_AMB_Y2_LV3_SedanL)); + M_MEMCOPY((g_assVF_AMB_X1_LV3), (c_assVF_AMB_X1_LV3_SedanL)); + M_MEMCOPY((g_assVF_AMB_X2_LV3), (c_assVF_AMB_X2_LV3_SedanL)); + M_MEMCOPY((g_assVF_SUN_Y1_LV3), (c_assVF_SUN_Y1_LV3_SedanL)); + M_MEMCOPY((g_assVF_SUN_Y2_LV3), (c_assVF_SUN_Y2_LV3_SedanL)); + M_MEMCOPY((g_assVF_SUN_X1_LV3), (c_assVF_SUN_X1_LV3_SedanL)); + M_MEMCOPY((g_assVF_SUN_X2_LV3), (c_assVF_SUN_X2_LV3_SedanL)); + M_MEMCOPY((g_assTG_FLU_LV3), (c_assTG_FLU_LV3_SedanL)); + M_MEMCOPY((g_assTG_FRU_LV3), (c_assTG_FRU_LV3_SedanL)); + M_MEMCOPY((g_assDTG_FU_MIN_LV3), (c_assDTG_FU_MIN_LV3_SedanL)); + M_MEMCOPY((g_assDTG_FU_MAX_LV3), (c_assDTG_FU_MAX_LV3_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_Y1_LV3), (c_assDTG_FU_INC_Y1_LV3_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_Y2_LV3), (c_assDTG_FU_INC_Y2_LV3_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_Y3_LV3), (c_assDTG_FU_INC_Y3_LV3_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_Y4_LV3), (c_assDTG_FU_INC_Y4_LV3_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_X1_LV3), (c_assDTG_FU_INC_X1_LV3_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_X2_LV3), (c_assDTG_FU_INC_X2_LV3_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_X3_LV3), (c_assDTG_FU_INC_X3_LV3_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_X4_LV3), (c_assDTG_FU_INC_X4_LV3_SedanL)); + M_MEMCOPY((g_assDTG_FU_AMB_Y1_LV3), (c_assDTG_FU_AMB_Y1_LV3_SedanL)); + M_MEMCOPY((g_assDTG_FU_AMB_Y2_LV3), (c_assDTG_FU_AMB_Y2_LV3_SedanL)); + M_MEMCOPY((g_assDTG_FU_AMB_X1_LV3), (c_assDTG_FU_AMB_X1_LV3_SedanL)); + M_MEMCOPY((g_assDTG_FU_AMB_X2_LV3), (c_assDTG_FU_AMB_X2_LV3_SedanL)); + M_MEMCOPY((g_assDTG_FU_SUN_Y1_LV3), (c_assDTG_FU_SUN_Y1_LV3_SedanL)); + M_MEMCOPY((g_assDTG_FU_SUN_Y2_LV3), (c_assDTG_FU_SUN_Y2_LV3_SedanL)); + M_MEMCOPY((g_assDTG_FU_SUN_X1_LV3), (c_assDTG_FU_SUN_X1_LV3_SedanL)); + M_MEMCOPY((g_assDTG_FU_SUN_X2_LV3), (c_assDTG_FU_SUN_X2_LV3_SedanL)); + M_MEMCOPY((g_assTG_FLL_LV3), (c_assTG_FLL_LV3_SedanL)); + M_MEMCOPY((g_assTG_FRL_LV3), (c_assTG_FRL_LV3_SedanL)); + M_MEMCOPY((g_assDTG_FL_MIN_LV3), (c_assDTG_FL_MIN_LV3_SedanL)); + M_MEMCOPY((g_assDTG_FL_MAX_LV3), (c_assDTG_FL_MAX_LV3_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_Y1_LV3), (c_assDTG_FL_INC_Y1_LV3_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_Y2_LV3), (c_assDTG_FL_INC_Y2_LV3_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_Y3_LV3), (c_assDTG_FL_INC_Y3_LV3_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_Y4_LV3), (c_assDTG_FL_INC_Y4_LV3_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_X1_LV3), (c_assDTG_FL_INC_X1_LV3_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_X2_LV3), (c_assDTG_FL_INC_X2_LV3_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_X3_LV3), (c_assDTG_FL_INC_X3_LV3_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_X4_LV3), (c_assDTG_FL_INC_X4_LV3_SedanL)); + M_MEMCOPY((g_assDTG_FL_AMB_Y1_LV3), (c_assDTG_FL_AMB_Y1_LV3_SedanL)); + M_MEMCOPY((g_assDTG_FL_AMB_Y2_LV3), (c_assDTG_FL_AMB_Y2_LV3_SedanL)); + M_MEMCOPY((g_assDTG_FL_AMB_X1_LV3), (c_assDTG_FL_AMB_X1_LV3_SedanL)); + M_MEMCOPY((g_assDTG_FL_AMB_X2_LV3), (c_assDTG_FL_AMB_X2_LV3_SedanL)); + M_MEMCOPY((g_assDTG_FL_SUN_Y1_LV3), (c_assDTG_FL_SUN_Y1_LV3_SedanL)); + M_MEMCOPY((g_assDTG_FL_SUN_Y2_LV3), (c_assDTG_FL_SUN_Y2_LV3_SedanL)); + M_MEMCOPY((g_assDTG_FL_SUN_X1_LV3), (c_assDTG_FL_SUN_X1_LV3_SedanL)); + M_MEMCOPY((g_assDTG_FL_SUN_X2_LV3), (c_assDTG_FL_SUN_X2_LV3_SedanL)); + M_MEMCOPY((g_assINCAR_TG_RL_LV3), (c_assINCAR_TG_RL_LV3_SedanL)); + M_MEMCOPY((g_assINCAR_TG_RR_LV3), (c_assINCAR_TG_RR_LV3_SedanL)); + M_MEMCOPY((g_assVTG_RL_LV3), (c_assVTG_RL_LV3_SedanL)); + M_MEMCOPY((g_assVTG_RR_LV3), (c_assVTG_RR_LV3_SedanL)); + M_MEMCOPY((g_assVR_MIN_LV3), (c_assVR_MIN_LV3_SedanL)); + M_MEMCOPY((g_assVR_MAX_LV3), (c_assVR_MAX_LV3_SedanL)); + M_MEMCOPY((g_assVR_INC_Y1_LV3), (c_assVR_INC_Y1_LV3_SedanL)); + M_MEMCOPY((g_assVR_INC_Y2_LV3), (c_assVR_INC_Y2_LV3_SedanL)); + M_MEMCOPY((g_assVR_INC_Y3_LV3), (c_assVR_INC_Y3_LV3_SedanL)); + M_MEMCOPY((g_assVR_INC_Y4_LV3), (c_assVR_INC_Y4_LV3_SedanL)); + M_MEMCOPY((g_assVR_INC_X1_LV3), (c_assVR_INC_X1_LV3_SedanL)); + M_MEMCOPY((g_assVR_INC_X2_LV3), (c_assVR_INC_X2_LV3_SedanL)); + M_MEMCOPY((g_assVR_INC_X3_LV3), (c_assVR_INC_X3_LV3_SedanL)); + M_MEMCOPY((g_assVR_INC_X4_LV3), (c_assVR_INC_X4_LV3_SedanL)); + M_MEMCOPY((g_assVR_AMB_Y1_LV3), (c_assVR_AMB_Y1_LV3_SedanL)); + M_MEMCOPY((g_assVR_AMB_Y2_LV3), (c_assVR_AMB_Y2_LV3_SedanL)); + M_MEMCOPY((g_assVR_AMB_X1_LV3), (c_assVR_AMB_X1_LV3_SedanL)); + M_MEMCOPY((g_assVR_AMB_X2_LV3), (c_assVR_AMB_X2_LV3_SedanL)); + M_MEMCOPY((g_assVR_SUN_Y1_LV3), (c_assVR_SUN_Y1_LV3_SedanL)); + M_MEMCOPY((g_assVR_SUN_Y2_LV3), (c_assVR_SUN_Y2_LV3_SedanL)); + M_MEMCOPY((g_assVR_SUN_X1_LV3), (c_assVR_SUN_X1_LV3_SedanL)); + M_MEMCOPY((g_assVR_SUN_X2_LV3), (c_assVR_SUN_X2_LV3_SedanL)); + M_MEMCOPY((g_assTG_RL_LV3), (c_assTG_RL_LV3_SedanL)); + M_MEMCOPY((g_assTG_RR_LV3), (c_assTG_RR_LV3_SedanL)); + M_MEMCOPY((g_assDTG_R_MIN_LV3), (c_assDTG_R_MIN_LV3_SedanL)); + M_MEMCOPY((g_assDTG_R_MAX_LV3), (c_assDTG_R_MAX_LV3_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_Y1_LV3), (c_assDTG_R_INC_Y1_LV3_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_Y2_LV3), (c_assDTG_R_INC_Y2_LV3_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_Y3_LV3), (c_assDTG_R_INC_Y3_LV3_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_Y4_LV3), (c_assDTG_R_INC_Y4_LV3_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_X1_LV3), (c_assDTG_R_INC_X1_LV3_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_X2_LV3), (c_assDTG_R_INC_X2_LV3_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_X3_LV3), (c_assDTG_R_INC_X3_LV3_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_X4_LV3), (c_assDTG_R_INC_X4_LV3_SedanL)); + M_MEMCOPY((g_assDTG_R_AMB_Y1_LV3), (c_assDTG_R_AMB_Y1_LV3_SedanL)); + M_MEMCOPY((g_assDTG_R_AMB_Y2_LV3), (c_assDTG_R_AMB_Y2_LV3_SedanL)); + M_MEMCOPY((g_assDTG_R_AMB_X1_LV3), (c_assDTG_R_AMB_X1_LV3_SedanL)); + M_MEMCOPY((g_assDTG_R_AMB_X2_LV3), (c_assDTG_R_AMB_X2_LV3_SedanL)); + M_MEMCOPY((g_assDTG_R_SUN_Y1_LV3), (c_assDTG_R_SUN_Y1_LV3_SedanL)); + M_MEMCOPY((g_assDTG_R_SUN_Y2_LV3), (c_assDTG_R_SUN_Y2_LV3_SedanL)); + M_MEMCOPY((g_assDTG_R_SUN_X1_LV3), (c_assDTG_R_SUN_X1_LV3_SedanL)); + M_MEMCOPY((g_assDTG_R_SUN_X2_LV3), (c_assDTG_R_SUN_X2_LV3_SedanL)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FR_LV3), (c_assCORRECT_DUCT_TIME_FR_LV3_SedanL)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FL_LV3), (c_assCORRECT_DUCT_TIME_FL_LV3_SedanL)); + M_MEMCOPY((g_assCORRECT_DUCT_RATE_LV3), (c_assCORRECT_DUCT_RATE_LV3_SedanL)); + M_MEMCOPY((g_assCORRECT_DUCT_MAX_LV3), (c_assCORRECT_DUCT_MAX_LV3_SedanL)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FR_LV3), (c_assCORRECT_AF_TIME_FR_LV3_SedanL)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FL_LV3), (c_assCORRECT_AF_TIME_FL_LV3_SedanL)); + M_MEMCOPY((g_assCORRECT_AF_RATE_LV3), (c_assCORRECT_AF_RATE_LV3_SedanL)); + M_MEMCOPY((g_assCORRECT_AF_MAX_LV3), (c_assCORRECT_AF_MAX_LV3_SedanL)); +/* ------------------------------------------Lv3 : End*/ + M_MEMCOPY((g_assINCAR_TG_FL_LV4), (c_assINCAR_TG_FL_LV4_SedanL)); + M_MEMCOPY((g_assINCAR_TG_FR_LV4), (c_assINCAR_TG_FR_LV4_SedanL)); + M_MEMCOPY((g_assVTG_FL_LV4), (c_assVTG_FL_LV4_SedanL)); + M_MEMCOPY((g_assVTG_FR_LV4), (c_assVTG_FR_LV4_SedanL)); + M_MEMCOPY((g_assVF_MIN_LV4), (c_assVF_MIN_LV4_SedanL)); + M_MEMCOPY((g_assVF_MAX_LV4), (c_assVF_MAX_LV4_SedanL)); + M_MEMCOPY((g_assVF_INC_Y1_LV4), (c_assVF_INC_Y1_LV4_SedanL)); + M_MEMCOPY((g_assVF_INC_Y2_LV4), (c_assVF_INC_Y2_LV4_SedanL)); + M_MEMCOPY((g_assVF_INC_Y3_LV4), (c_assVF_INC_Y3_LV4_SedanL)); + M_MEMCOPY((g_assVF_INC_Y4_LV4), (c_assVF_INC_Y4_LV4_SedanL)); + M_MEMCOPY((g_assVF_INC_X1_LV4), (c_assVF_INC_X1_LV4_SedanL)); + M_MEMCOPY((g_assVF_INC_X2_LV4), (c_assVF_INC_X2_LV4_SedanL)); + M_MEMCOPY((g_assVF_INC_X3_LV4), (c_assVF_INC_X3_LV4_SedanL)); + M_MEMCOPY((g_assVF_INC_X4_LV4), (c_assVF_INC_X4_LV4_SedanL)); + M_MEMCOPY((g_assVF_AMB_Y1_LV4), (c_assVF_AMB_Y1_LV4_SedanL)); + M_MEMCOPY((g_assVF_AMB_Y2_LV4), (c_assVF_AMB_Y2_LV4_SedanL)); + M_MEMCOPY((g_assVF_AMB_X1_LV4), (c_assVF_AMB_X1_LV4_SedanL)); + M_MEMCOPY((g_assVF_AMB_X2_LV4), (c_assVF_AMB_X2_LV4_SedanL)); + M_MEMCOPY((g_assVF_SUN_Y1_LV4), (c_assVF_SUN_Y1_LV4_SedanL)); + M_MEMCOPY((g_assVF_SUN_Y2_LV4), (c_assVF_SUN_Y2_LV4_SedanL)); + M_MEMCOPY((g_assVF_SUN_X1_LV4), (c_assVF_SUN_X1_LV4_SedanL)); + M_MEMCOPY((g_assVF_SUN_X2_LV4), (c_assVF_SUN_X2_LV4_SedanL)); + M_MEMCOPY((g_assTG_FLU_LV4), (c_assTG_FLU_LV4_SedanL)); + M_MEMCOPY((g_assTG_FRU_LV4), (c_assTG_FRU_LV4_SedanL)); + M_MEMCOPY((g_assDTG_FU_MIN_LV4), (c_assDTG_FU_MIN_LV4_SedanL)); + M_MEMCOPY((g_assDTG_FU_MAX_LV4), (c_assDTG_FU_MAX_LV4_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_Y1_LV4), (c_assDTG_FU_INC_Y1_LV4_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_Y2_LV4), (c_assDTG_FU_INC_Y2_LV4_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_Y3_LV4), (c_assDTG_FU_INC_Y3_LV4_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_Y4_LV4), (c_assDTG_FU_INC_Y4_LV4_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_X1_LV4), (c_assDTG_FU_INC_X1_LV4_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_X2_LV4), (c_assDTG_FU_INC_X2_LV4_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_X3_LV4), (c_assDTG_FU_INC_X3_LV4_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_X4_LV4), (c_assDTG_FU_INC_X4_LV4_SedanL)); + M_MEMCOPY((g_assDTG_FU_AMB_Y1_LV4), (c_assDTG_FU_AMB_Y1_LV4_SedanL)); + M_MEMCOPY((g_assDTG_FU_AMB_Y2_LV4), (c_assDTG_FU_AMB_Y2_LV4_SedanL)); + M_MEMCOPY((g_assDTG_FU_AMB_X1_LV4), (c_assDTG_FU_AMB_X1_LV4_SedanL)); + M_MEMCOPY((g_assDTG_FU_AMB_X2_LV4), (c_assDTG_FU_AMB_X2_LV4_SedanL)); + M_MEMCOPY((g_assDTG_FU_SUN_Y1_LV4), (c_assDTG_FU_SUN_Y1_LV4_SedanL)); + M_MEMCOPY((g_assDTG_FU_SUN_Y2_LV4), (c_assDTG_FU_SUN_Y2_LV4_SedanL)); + M_MEMCOPY((g_assDTG_FU_SUN_X1_LV4), (c_assDTG_FU_SUN_X1_LV4_SedanL)); + M_MEMCOPY((g_assDTG_FU_SUN_X2_LV4), (c_assDTG_FU_SUN_X2_LV4_SedanL)); + M_MEMCOPY((g_assTG_FLL_LV4), (c_assTG_FLL_LV4_SedanL)); + M_MEMCOPY((g_assTG_FRL_LV4), (c_assTG_FRL_LV4_SedanL)); + M_MEMCOPY((g_assDTG_FL_MIN_LV4), (c_assDTG_FL_MIN_LV4_SedanL)); + M_MEMCOPY((g_assDTG_FL_MAX_LV4), (c_assDTG_FL_MAX_LV4_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_Y1_LV4), (c_assDTG_FL_INC_Y1_LV4_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_Y2_LV4), (c_assDTG_FL_INC_Y2_LV4_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_Y3_LV4), (c_assDTG_FL_INC_Y3_LV4_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_Y4_LV4), (c_assDTG_FL_INC_Y4_LV4_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_X1_LV4), (c_assDTG_FL_INC_X1_LV4_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_X2_LV4), (c_assDTG_FL_INC_X2_LV4_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_X3_LV4), (c_assDTG_FL_INC_X3_LV4_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_X4_LV4), (c_assDTG_FL_INC_X4_LV4_SedanL)); + M_MEMCOPY((g_assDTG_FL_AMB_Y1_LV4), (c_assDTG_FL_AMB_Y1_LV4_SedanL)); + M_MEMCOPY((g_assDTG_FL_AMB_Y2_LV4), (c_assDTG_FL_AMB_Y2_LV4_SedanL)); + M_MEMCOPY((g_assDTG_FL_AMB_X1_LV4), (c_assDTG_FL_AMB_X1_LV4_SedanL)); + M_MEMCOPY((g_assDTG_FL_AMB_X2_LV4), (c_assDTG_FL_AMB_X2_LV4_SedanL)); + M_MEMCOPY((g_assDTG_FL_SUN_Y1_LV4), (c_assDTG_FL_SUN_Y1_LV4_SedanL)); + M_MEMCOPY((g_assDTG_FL_SUN_Y2_LV4), (c_assDTG_FL_SUN_Y2_LV4_SedanL)); + M_MEMCOPY((g_assDTG_FL_SUN_X1_LV4), (c_assDTG_FL_SUN_X1_LV4_SedanL)); + M_MEMCOPY((g_assDTG_FL_SUN_X2_LV4), (c_assDTG_FL_SUN_X2_LV4_SedanL)); + M_MEMCOPY((g_assINCAR_TG_RL_LV4), (c_assINCAR_TG_RL_LV4_SedanL)); + M_MEMCOPY((g_assINCAR_TG_RR_LV4), (c_assINCAR_TG_RR_LV4_SedanL)); + M_MEMCOPY((g_assVTG_RL_LV4), (c_assVTG_RL_LV4_SedanL)); + M_MEMCOPY((g_assVTG_RR_LV4), (c_assVTG_RR_LV4_SedanL)); + M_MEMCOPY((g_assVR_MIN_LV4), (c_assVR_MIN_LV4_SedanL)); + M_MEMCOPY((g_assVR_MAX_LV4), (c_assVR_MAX_LV4_SedanL)); + M_MEMCOPY((g_assVR_INC_Y1_LV4), (c_assVR_INC_Y1_LV4_SedanL)); + M_MEMCOPY((g_assVR_INC_Y2_LV4), (c_assVR_INC_Y2_LV4_SedanL)); + M_MEMCOPY((g_assVR_INC_Y3_LV4), (c_assVR_INC_Y3_LV4_SedanL)); + M_MEMCOPY((g_assVR_INC_Y4_LV4), (c_assVR_INC_Y4_LV4_SedanL)); + M_MEMCOPY((g_assVR_INC_X1_LV4), (c_assVR_INC_X1_LV4_SedanL)); + M_MEMCOPY((g_assVR_INC_X2_LV4), (c_assVR_INC_X2_LV4_SedanL)); + M_MEMCOPY((g_assVR_INC_X3_LV4), (c_assVR_INC_X3_LV4_SedanL)); + M_MEMCOPY((g_assVR_INC_X4_LV4), (c_assVR_INC_X4_LV4_SedanL)); + M_MEMCOPY((g_assVR_AMB_Y1_LV4), (c_assVR_AMB_Y1_LV4_SedanL)); + M_MEMCOPY((g_assVR_AMB_Y2_LV4), (c_assVR_AMB_Y2_LV4_SedanL)); + M_MEMCOPY((g_assVR_AMB_X1_LV4), (c_assVR_AMB_X1_LV4_SedanL)); + M_MEMCOPY((g_assVR_AMB_X2_LV4), (c_assVR_AMB_X2_LV4_SedanL)); + M_MEMCOPY((g_assVR_SUN_Y1_LV4), (c_assVR_SUN_Y1_LV4_SedanL)); + M_MEMCOPY((g_assVR_SUN_Y2_LV4), (c_assVR_SUN_Y2_LV4_SedanL)); + M_MEMCOPY((g_assVR_SUN_X1_LV4), (c_assVR_SUN_X1_LV4_SedanL)); + M_MEMCOPY((g_assVR_SUN_X2_LV4), (c_assVR_SUN_X2_LV4_SedanL)); + M_MEMCOPY((g_assTG_RL_LV4), (c_assTG_RL_LV4_SedanL)); + M_MEMCOPY((g_assTG_RR_LV4), (c_assTG_RR_LV4_SedanL)); + M_MEMCOPY((g_assDTG_R_MIN_LV4), (c_assDTG_R_MIN_LV4_SedanL)); + M_MEMCOPY((g_assDTG_R_MAX_LV4), (c_assDTG_R_MAX_LV4_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_Y1_LV4), (c_assDTG_R_INC_Y1_LV4_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_Y2_LV4), (c_assDTG_R_INC_Y2_LV4_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_Y3_LV4), (c_assDTG_R_INC_Y3_LV4_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_Y4_LV4), (c_assDTG_R_INC_Y4_LV4_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_X1_LV4), (c_assDTG_R_INC_X1_LV4_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_X2_LV4), (c_assDTG_R_INC_X2_LV4_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_X3_LV4), (c_assDTG_R_INC_X3_LV4_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_X4_LV4), (c_assDTG_R_INC_X4_LV4_SedanL)); + M_MEMCOPY((g_assDTG_R_AMB_Y1_LV4), (c_assDTG_R_AMB_Y1_LV4_SedanL)); + M_MEMCOPY((g_assDTG_R_AMB_Y2_LV4), (c_assDTG_R_AMB_Y2_LV4_SedanL)); + M_MEMCOPY((g_assDTG_R_AMB_X1_LV4), (c_assDTG_R_AMB_X1_LV4_SedanL)); + M_MEMCOPY((g_assDTG_R_AMB_X2_LV4), (c_assDTG_R_AMB_X2_LV4_SedanL)); + M_MEMCOPY((g_assDTG_R_SUN_Y1_LV4), (c_assDTG_R_SUN_Y1_LV4_SedanL)); + M_MEMCOPY((g_assDTG_R_SUN_Y2_LV4), (c_assDTG_R_SUN_Y2_LV4_SedanL)); + M_MEMCOPY((g_assDTG_R_SUN_X1_LV4), (c_assDTG_R_SUN_X1_LV4_SedanL)); + M_MEMCOPY((g_assDTG_R_SUN_X2_LV4), (c_assDTG_R_SUN_X2_LV4_SedanL)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FR_LV4), (c_assCORRECT_DUCT_TIME_FR_LV4_SedanL)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FL_LV4), (c_assCORRECT_DUCT_TIME_FL_LV4_SedanL)); + M_MEMCOPY((g_assCORRECT_DUCT_RATE_LV4), (c_assCORRECT_DUCT_RATE_LV4_SedanL)); + M_MEMCOPY((g_assCORRECT_DUCT_MAX_LV4), (c_assCORRECT_DUCT_MAX_LV4_SedanL)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FR_LV4), (c_assCORRECT_AF_TIME_FR_LV4_SedanL)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FL_LV4), (c_assCORRECT_AF_TIME_FL_LV4_SedanL)); + M_MEMCOPY((g_assCORRECT_AF_RATE_LV4), (c_assCORRECT_AF_RATE_LV4_SedanL)); + M_MEMCOPY((g_assCORRECT_AF_MAX_LV4), (c_assCORRECT_AF_MAX_LV4_SedanL)); +/* ------------------------------------------Lv4 : End*/ + M_MEMCOPY((g_assINCAR_TG_FL_LV5), (c_assINCAR_TG_FL_LV5_SedanL)); + M_MEMCOPY((g_assINCAR_TG_FR_LV5), (c_assINCAR_TG_FR_LV5_SedanL)); + M_MEMCOPY((g_assVTG_FL_LV5), (c_assVTG_FL_LV5_SedanL)); + M_MEMCOPY((g_assVTG_FR_LV5), (c_assVTG_FR_LV5_SedanL)); + M_MEMCOPY((g_assVF_MIN_LV5), (c_assVF_MIN_LV5_SedanL)); + M_MEMCOPY((g_assVF_MAX_LV5), (c_assVF_MAX_LV5_SedanL)); + M_MEMCOPY((g_assVF_INC_Y1_LV5), (c_assVF_INC_Y1_LV5_SedanL)); + M_MEMCOPY((g_assVF_INC_Y2_LV5), (c_assVF_INC_Y2_LV5_SedanL)); + M_MEMCOPY((g_assVF_INC_Y3_LV5), (c_assVF_INC_Y3_LV5_SedanL)); + M_MEMCOPY((g_assVF_INC_Y4_LV5), (c_assVF_INC_Y4_LV5_SedanL)); + M_MEMCOPY((g_assVF_INC_X1_LV5), (c_assVF_INC_X1_LV5_SedanL)); + M_MEMCOPY((g_assVF_INC_X2_LV5), (c_assVF_INC_X2_LV5_SedanL)); + M_MEMCOPY((g_assVF_INC_X3_LV5), (c_assVF_INC_X3_LV5_SedanL)); + M_MEMCOPY((g_assVF_INC_X4_LV5), (c_assVF_INC_X4_LV5_SedanL)); + M_MEMCOPY((g_assVF_AMB_Y1_LV5), (c_assVF_AMB_Y1_LV5_SedanL)); + M_MEMCOPY((g_assVF_AMB_Y2_LV5), (c_assVF_AMB_Y2_LV5_SedanL)); + M_MEMCOPY((g_assVF_AMB_X1_LV5), (c_assVF_AMB_X1_LV5_SedanL)); + M_MEMCOPY((g_assVF_AMB_X2_LV5), (c_assVF_AMB_X2_LV5_SedanL)); + M_MEMCOPY((g_assVF_SUN_Y1_LV5), (c_assVF_SUN_Y1_LV5_SedanL)); + M_MEMCOPY((g_assVF_SUN_Y2_LV5), (c_assVF_SUN_Y2_LV5_SedanL)); + M_MEMCOPY((g_assVF_SUN_X1_LV5), (c_assVF_SUN_X1_LV5_SedanL)); + M_MEMCOPY((g_assVF_SUN_X2_LV5), (c_assVF_SUN_X2_LV5_SedanL)); + M_MEMCOPY((g_assTG_FLU_LV5), (c_assTG_FLU_LV5_SedanL)); + M_MEMCOPY((g_assTG_FRU_LV5), (c_assTG_FRU_LV5_SedanL)); + M_MEMCOPY((g_assDTG_FU_MIN_LV5), (c_assDTG_FU_MIN_LV5_SedanL)); + M_MEMCOPY((g_assDTG_FU_MAX_LV5), (c_assDTG_FU_MAX_LV5_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_Y1_LV5), (c_assDTG_FU_INC_Y1_LV5_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_Y2_LV5), (c_assDTG_FU_INC_Y2_LV5_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_Y3_LV5), (c_assDTG_FU_INC_Y3_LV5_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_Y4_LV5), (c_assDTG_FU_INC_Y4_LV5_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_X1_LV5), (c_assDTG_FU_INC_X1_LV5_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_X2_LV5), (c_assDTG_FU_INC_X2_LV5_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_X3_LV5), (c_assDTG_FU_INC_X3_LV5_SedanL)); + M_MEMCOPY((g_assDTG_FU_INC_X4_LV5), (c_assDTG_FU_INC_X4_LV5_SedanL)); + M_MEMCOPY((g_assDTG_FU_AMB_Y1_LV5), (c_assDTG_FU_AMB_Y1_LV5_SedanL)); + M_MEMCOPY((g_assDTG_FU_AMB_Y2_LV5), (c_assDTG_FU_AMB_Y2_LV5_SedanL)); + M_MEMCOPY((g_assDTG_FU_AMB_X1_LV5), (c_assDTG_FU_AMB_X1_LV5_SedanL)); + M_MEMCOPY((g_assDTG_FU_AMB_X2_LV5), (c_assDTG_FU_AMB_X2_LV5_SedanL)); + M_MEMCOPY((g_assDTG_FU_SUN_Y1_LV5), (c_assDTG_FU_SUN_Y1_LV5_SedanL)); + M_MEMCOPY((g_assDTG_FU_SUN_Y2_LV5), (c_assDTG_FU_SUN_Y2_LV5_SedanL)); + M_MEMCOPY((g_assDTG_FU_SUN_X1_LV5), (c_assDTG_FU_SUN_X1_LV5_SedanL)); + M_MEMCOPY((g_assDTG_FU_SUN_X2_LV5), (c_assDTG_FU_SUN_X2_LV5_SedanL)); + M_MEMCOPY((g_assTG_FLL_LV5), (c_assTG_FLL_LV5_SedanL)); + M_MEMCOPY((g_assTG_FRL_LV5), (c_assTG_FRL_LV5_SedanL)); + M_MEMCOPY((g_assDTG_FL_MIN_LV5), (c_assDTG_FL_MIN_LV5_SedanL)); + M_MEMCOPY((g_assDTG_FL_MAX_LV5), (c_assDTG_FL_MAX_LV5_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_Y1_LV5), (c_assDTG_FL_INC_Y1_LV5_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_Y2_LV5), (c_assDTG_FL_INC_Y2_LV5_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_Y3_LV5), (c_assDTG_FL_INC_Y3_LV5_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_Y4_LV5), (c_assDTG_FL_INC_Y4_LV5_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_X1_LV5), (c_assDTG_FL_INC_X1_LV5_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_X2_LV5), (c_assDTG_FL_INC_X2_LV5_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_X3_LV5), (c_assDTG_FL_INC_X3_LV5_SedanL)); + M_MEMCOPY((g_assDTG_FL_INC_X4_LV5), (c_assDTG_FL_INC_X4_LV5_SedanL)); + M_MEMCOPY((g_assDTG_FL_AMB_Y1_LV5), (c_assDTG_FL_AMB_Y1_LV5_SedanL)); + M_MEMCOPY((g_assDTG_FL_AMB_Y2_LV5), (c_assDTG_FL_AMB_Y2_LV5_SedanL)); + M_MEMCOPY((g_assDTG_FL_AMB_X1_LV5), (c_assDTG_FL_AMB_X1_LV5_SedanL)); + M_MEMCOPY((g_assDTG_FL_AMB_X2_LV5), (c_assDTG_FL_AMB_X2_LV5_SedanL)); + M_MEMCOPY((g_assDTG_FL_SUN_Y1_LV5), (c_assDTG_FL_SUN_Y1_LV5_SedanL)); + M_MEMCOPY((g_assDTG_FL_SUN_Y2_LV5), (c_assDTG_FL_SUN_Y2_LV5_SedanL)); + M_MEMCOPY((g_assDTG_FL_SUN_X1_LV5), (c_assDTG_FL_SUN_X1_LV5_SedanL)); + M_MEMCOPY((g_assDTG_FL_SUN_X2_LV5), (c_assDTG_FL_SUN_X2_LV5_SedanL)); + M_MEMCOPY((g_assINCAR_TG_RL_LV5), (c_assINCAR_TG_RL_LV5_SedanL)); + M_MEMCOPY((g_assINCAR_TG_RR_LV5), (c_assINCAR_TG_RR_LV5_SedanL)); + M_MEMCOPY((g_assVTG_RL_LV5), (c_assVTG_RL_LV5_SedanL)); + M_MEMCOPY((g_assVTG_RR_LV5), (c_assVTG_RR_LV5_SedanL)); + M_MEMCOPY((g_assVR_MIN_LV5), (c_assVR_MIN_LV5_SedanL)); + M_MEMCOPY((g_assVR_MAX_LV5), (c_assVR_MAX_LV5_SedanL)); + M_MEMCOPY((g_assVR_INC_Y1_LV5), (c_assVR_INC_Y1_LV5_SedanL)); + M_MEMCOPY((g_assVR_INC_Y2_LV5), (c_assVR_INC_Y2_LV5_SedanL)); + M_MEMCOPY((g_assVR_INC_Y3_LV5), (c_assVR_INC_Y3_LV5_SedanL)); + M_MEMCOPY((g_assVR_INC_Y4_LV5), (c_assVR_INC_Y4_LV5_SedanL)); + M_MEMCOPY((g_assVR_INC_X1_LV5), (c_assVR_INC_X1_LV5_SedanL)); + M_MEMCOPY((g_assVR_INC_X2_LV5), (c_assVR_INC_X2_LV5_SedanL)); + M_MEMCOPY((g_assVR_INC_X3_LV5), (c_assVR_INC_X3_LV5_SedanL)); + M_MEMCOPY((g_assVR_INC_X4_LV5), (c_assVR_INC_X4_LV5_SedanL)); + M_MEMCOPY((g_assVR_AMB_Y1_LV5), (c_assVR_AMB_Y1_LV5_SedanL)); + M_MEMCOPY((g_assVR_AMB_Y2_LV5), (c_assVR_AMB_Y2_LV5_SedanL)); + M_MEMCOPY((g_assVR_AMB_X1_LV5), (c_assVR_AMB_X1_LV5_SedanL)); + M_MEMCOPY((g_assVR_AMB_X2_LV5), (c_assVR_AMB_X2_LV5_SedanL)); + M_MEMCOPY((g_assVR_SUN_Y1_LV5), (c_assVR_SUN_Y1_LV5_SedanL)); + M_MEMCOPY((g_assVR_SUN_Y2_LV5), (c_assVR_SUN_Y2_LV5_SedanL)); + M_MEMCOPY((g_assVR_SUN_X1_LV5), (c_assVR_SUN_X1_LV5_SedanL)); + M_MEMCOPY((g_assVR_SUN_X2_LV5), (c_assVR_SUN_X2_LV5_SedanL)); + M_MEMCOPY((g_assTG_RL_LV5), (c_assTG_RL_LV5_SedanL)); + M_MEMCOPY((g_assTG_RR_LV5), (c_assTG_RR_LV5_SedanL)); + M_MEMCOPY((g_assDTG_R_MIN_LV5), (c_assDTG_R_MIN_LV5_SedanL)); + M_MEMCOPY((g_assDTG_R_MAX_LV5), (c_assDTG_R_MAX_LV5_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_Y1_LV5), (c_assDTG_R_INC_Y1_LV5_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_Y2_LV5), (c_assDTG_R_INC_Y2_LV5_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_Y3_LV5), (c_assDTG_R_INC_Y3_LV5_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_Y4_LV5), (c_assDTG_R_INC_Y4_LV5_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_X1_LV5), (c_assDTG_R_INC_X1_LV5_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_X2_LV5), (c_assDTG_R_INC_X2_LV5_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_X3_LV5), (c_assDTG_R_INC_X3_LV5_SedanL)); + M_MEMCOPY((g_assDTG_R_INC_X4_LV5), (c_assDTG_R_INC_X4_LV5_SedanL)); + M_MEMCOPY((g_assDTG_R_AMB_Y1_LV5), (c_assDTG_R_AMB_Y1_LV5_SedanL)); + M_MEMCOPY((g_assDTG_R_AMB_Y2_LV5), (c_assDTG_R_AMB_Y2_LV5_SedanL)); + M_MEMCOPY((g_assDTG_R_AMB_X1_LV5), (c_assDTG_R_AMB_X1_LV5_SedanL)); + M_MEMCOPY((g_assDTG_R_AMB_X2_LV5), (c_assDTG_R_AMB_X2_LV5_SedanL)); + M_MEMCOPY((g_assDTG_R_SUN_Y1_LV5), (c_assDTG_R_SUN_Y1_LV5_SedanL)); + M_MEMCOPY((g_assDTG_R_SUN_Y2_LV5), (c_assDTG_R_SUN_Y2_LV5_SedanL)); + M_MEMCOPY((g_assDTG_R_SUN_X1_LV5), (c_assDTG_R_SUN_X1_LV5_SedanL)); + M_MEMCOPY((g_assDTG_R_SUN_X2_LV5), (c_assDTG_R_SUN_X2_LV5_SedanL)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FR_LV5), (c_assCORRECT_DUCT_TIME_FR_LV5_SedanL)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FL_LV5), (c_assCORRECT_DUCT_TIME_FL_LV5_SedanL)); + M_MEMCOPY((g_assCORRECT_DUCT_RATE_LV5), (c_assCORRECT_DUCT_RATE_LV5_SedanL)); + M_MEMCOPY((g_assCORRECT_DUCT_MAX_LV5), (c_assCORRECT_DUCT_MAX_LV5_SedanL)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FR_LV5), (c_assCORRECT_AF_TIME_FR_LV5_SedanL)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FL_LV5), (c_assCORRECT_AF_TIME_FL_LV5_SedanL)); + M_MEMCOPY((g_assCORRECT_AF_RATE_LV5), (c_assCORRECT_AF_RATE_LV5_SedanL)); + M_MEMCOPY((g_assCORRECT_AF_MAX_LV5), (c_assCORRECT_AF_MAX_LV5_SedanL)); +/* ------------------------------------------Lv5 : End*/ + M_MEMCOPY((g_assDUCT_TGT_DEF_VALVE_L), (c_assDUCT_TGT_DEF_VALVE_L_SedanL)); + M_MEMCOPY((g_assDUCT_TGT_DEF_VALVE_R), (c_assDUCT_TGT_DEF_VALVE_R_SedanL)); +/* ------------------------------------------DuctTgt Increase : End*/ + M_MEMCOPY((g_assAMB_LV_UP), (c_assAMB_LV_UP_SedanL)); + M_MEMCOPY((g_assAMB_LV_DN), (c_assAMB_LV_DN_SedanL)); + M_MEMCOPY((g_assAMB_LV_TG), (c_assAMB_LV_TG_SedanL)); +/* ------------------------------------------Ambient LEVEL : End*/ + M_MEMCOPY((g_aucMODE_BY_SET_F_LV0), (c_aucMODE_BY_SET_F_LV0_SedanL)); + M_MEMCOPY((g_aucMODE_BY_SET_F_LV1), (c_aucMODE_BY_SET_F_LV1_SedanL)); + M_MEMCOPY((g_aucMODE_BY_SET_F_LV2), (c_aucMODE_BY_SET_F_LV2_SedanL)); + M_MEMCOPY((g_aucMODE_BY_SET_F_LV3), (c_aucMODE_BY_SET_F_LV3_SedanL)); + M_MEMCOPY((g_aucMODE_BY_SET_F_LV4), (c_aucMODE_BY_SET_F_LV4_SedanL)); + M_MEMCOPY((g_aucMODE_BY_SET_F_LV5), (c_aucMODE_BY_SET_F_LV5_SedanL)); + M_MEMCOPY((g_ausMODE_BY_DUCT_TG_R_LV0), (c_ausMODE_BY_DUCT_TG_R_LV0_SedanL)); + M_MEMCOPY((g_ausMODE_BY_DUCT_TG_R_LV1), (c_ausMODE_BY_DUCT_TG_R_LV1_SedanL)); + M_MEMCOPY((g_ausMODE_BY_DUCT_TG_R_LV2), (c_ausMODE_BY_DUCT_TG_R_LV2_SedanL)); + M_MEMCOPY((g_ausMODE_BY_DUCT_TG_R_LV3), (c_ausMODE_BY_DUCT_TG_R_LV3_SedanL)); + M_MEMCOPY((g_ausMODE_BY_DUCT_TG_R_LV4), (c_ausMODE_BY_DUCT_TG_R_LV4_SedanL)); + M_MEMCOPY((g_ausMODE_BY_DUCT_TG_R_LV5), (c_ausMODE_BY_DUCT_TG_R_LV5_SedanL)); +/* ------------------------------------------Mode depend on SET for each level : End*/ + g_ssPREC_REC_ON_AMB = c_ssPREC_REC_ON_AMB_SedanL; + g_ssPREC_REC_OFF_AMB = c_ssPREC_REC_OFF_AMB_SedanL; + M_MEMCOPY((g_aucPREC_VEH_SPD_OSA), (c_aucPREC_VEH_SPD_OSA_SedanL)); + M_MEMCOPY((g_assPRE_AMB_RANGE_WINTER), (c_assPRE_AMB_RANGE_WINTER_SedanL)); + M_MEMCOPY((g_aucPREC_OSA_WINTER), (c_aucPREC_OSA_WINTER_SedanL)); + M_MEMCOPY((g_aucPREC_REC_WINTER), (c_aucPREC_REC_WINTER_SedanL)); + M_MEMCOPY((g_ausPREC_HUMIDITY_NOK), (c_ausPREC_HUMIDITY_NOK_SedanL)); + M_MEMCOPY((g_ausPREC_HUMIDITY_OK), (c_ausPREC_HUMIDITY_OK_SedanL)); + M_MEMCOPY((g_ausPREC_ENTRY_RPM), (c_ausPREC_ENTRY_RPM_SedanL)); + M_MEMCOPY((g_ausPREC_EXIT_RPM), (c_ausPREC_EXIT_RPM_SedanL)); + M_MEMCOPY((g_ausPREC_COMP_SPD_1), (c_ausPREC_COMP_SPD_1_SedanL)); + M_MEMCOPY((g_aucPREC_OSA_SUMMER_1), (c_aucPREC_OSA_SUMMER_1_SedanL)); + M_MEMCOPY((g_aucPREC_REC_SUMMER_1), (c_aucPREC_REC_SUMMER_1_SedanL)); + M_MEMCOPY((g_assPREC_EVA_DIFF_FB_TG_F), (c_assPREC_EVA_DIFF_FB_TG_F_SedanL)); + M_MEMCOPY((g_aucPREC_OSA_SUMMER_2), (c_aucPREC_OSA_SUMMER_2_SedanL)); + M_MEMCOPY((g_aucPREC_REC_SUMMER_2), (c_aucPREC_REC_SUMMER_2_SedanL)); + M_MEMCOPY((g_aucPREC_EVA_DIFF), (c_aucPREC_EVA_DIFF_SedanL)); + g_ucPREC_OSA_SUMMER_3 = c_ucPREC_OSA_SUMMER_3_SedanL; + g_ucPREC_REC_SUMMER_3 = c_ucPREC_REC_SUMMER_3_SedanL; +/* ------------------------------------------AutoRec : End*/ + M_MEMCOPY((g_ausFLOW_FR_VE2VALVE), (c_ausFLOW_FR_VE2VALVE_SedanL)); + M_MEMCOPY((g_ausFLOW_FR_BIVALVE), (c_ausFLOW_FR_BIVALVE_SedanL)); + M_MEMCOPY((g_ausFLOW_FR_BI2VALVE), (c_ausFLOW_FR_BI2VALVE_SedanL)); + M_MEMCOPY((g_ausFLOW_FR_AF2VALVE), (c_ausFLOW_FR_AF2VALVE_SedanL)); + M_MEMCOPY((g_ausFLOW_FR_AF2VALVE_SUMMER), (c_ausFLOW_FR_AF2VALVE_SUMMER_SedanL)); + M_MEMCOPY((g_ausFLOW_FR_FO2VALVE), (c_ausFLOW_FR_FO2VALVE_SedanL)); + M_MEMCOPY((g_ausFLOW_FR_FD2VALVE), (c_ausFLOW_FR_FD2VALVE_SedanL)); + M_MEMCOPY((g_ausFLOW_FR_DE2VALVE), (c_ausFLOW_FR_DE2VALVE_SedanL)); + M_MEMCOPY((g_ausFLOW_FR_TR2VALVE), (c_ausFLOW_FR_TR2VALVE_SedanL)); + M_MEMCOPY((g_ausFLOW_FR_HI2VALVE), (c_ausFLOW_FR_HI2VALVE_SedanL)); + M_MEMCOPY((g_ausFLOW_FR_BIVALVE_MANUAL), (c_ausFLOW_FR_BIVALVE_MANUAL_SedanL)); + M_MEMCOPY((g_ausFLOW_RE_VENT), (c_ausFLOW_RE_VENT_SedanL)); + M_MEMCOPY((g_ausFLOW_RE_BI2VALVE), (c_ausFLOW_RE_BI2VALVE_SedanL)); + M_MEMCOPY((g_ausFLOW_RE_FO2VALVE), (c_ausFLOW_RE_FO2VALVE_SedanL)); + M_MEMCOPY((g_ausFLOW_RE_VENT_2), (c_ausFLOW_RE_VENT_2_SedanL)); + M_MEMCOPY((g_ausFLOW_RE_BI2VALVE_2), (c_ausFLOW_RE_BI2VALVE_2_SedanL)); + M_MEMCOPY((g_ausFLOW_RE_VENT_3), (c_ausFLOW_RE_VENT_3_SedanL)); + M_MEMCOPY((g_ausFLOW_RE_BI2VALVE_3), (c_ausFLOW_RE_BI2VALVE_3_SedanL)); + M_MEMCOPY((g_ausFLOW_RE_VENT_MANUAL), (c_ausFLOW_RE_VENT_MANUAL_SedanL)); + M_MEMCOPY((g_ausFLOW_RE_BI2VALVE_MANUAL), (c_ausFLOW_RE_BI2VALVE_MANUAL_SedanL)); +/* ------------------------------------------Flow Control Valve: End*/ + M_MEMCOPY((g_assFLOW_BI_AMB_TGT), (c_assFLOW_BI_AMB_TGT_SedanL)); + M_MEMCOPY((g_aucFLOW_BI_VENT_PLUS), (c_aucFLOW_BI_VENT_PLUS_SedanL)); + M_MEMCOPY((g_assFLOW_BI_TEMP_TGT), (c_assFLOW_BI_TEMP_TGT_SedanL)); + M_MEMCOPY((g_aucFLOW_BI_FOOT_PLUS), (c_aucFLOW_BI_FOOT_PLUS_SedanL)); + M_MEMCOPY((g_aucFLOW_BI_VENT_VALVE_MAX), (c_aucFLOW_BI_VENT_VALVE_MAX_SedanL)); + M_MEMCOPY((g_aucFLOW_BI_FOOT_VALVE_MAX), (c_aucFLOW_BI_FOOT_VALVE_MAX_SedanL)); + M_MEMCOPY((g_aucFLOW_BI_VENT_VALVE_MIN), (c_aucFLOW_BI_VENT_VALVE_MIN_SedanL)); + M_MEMCOPY((g_aucFLOW_BI_FOOT_VALVE_MIN), (c_aucFLOW_BI_FOOT_VALVE_MIN_SedanL)); +/* ------------------------------------------Bi 2 level conditions: End*/ + M_MEMCOPY((g_assFLOW_B2I_AMB_TGT), (c_assFLOW_B2I_AMB_TGT_SedanL)); + M_MEMCOPY((g_aucFLOW_BI2_VENT_PLUS), (c_aucFLOW_BI2_VENT_PLUS_SedanL)); + M_MEMCOPY((g_assFLOW_BI2_TEMP_TGT), (c_assFLOW_BI2_TEMP_TGT_SedanL)); + M_MEMCOPY((g_aucFLOW_BI2_FOOT_PLUS), (c_aucFLOW_BI2_FOOT_PLUS_SedanL)); + M_MEMCOPY((g_aucFLOW_BI2_VENT_VALVE_MAX), (c_aucFLOW_BI2_VENT_VALVE_MAX_SedanL)); + M_MEMCOPY((g_aucFLOW_BI2_FOOT_VALVE_MAX), (c_aucFLOW_BI2_FOOT_VALVE_MAX_SedanL)); + M_MEMCOPY((g_aucFLOW_BI2_VENT_VALVE_MIN), (c_aucFLOW_BI2_VENT_VALVE_MIN_SedanL)); + M_MEMCOPY((g_aucFLOW_BI2_FOOT_VALVE_MIN), (c_aucFLOW_BI2_FOOT_VALVE_MIN_SedanL)); +/* ------------------------------------------AF level conditions: End*/ + M_MEMCOPY((g_assFLOW_AF_AMB_TGT), (c_assFLOW_AF_AMB_TGT_SedanL)); + M_MEMCOPY((g_aucFLOW_AF_VENT_PLUS), (c_aucFLOW_AF_VENT_PLUS_SedanL)); + M_MEMCOPY((g_aucFLOW_AF_BLR_AF_TGT), (c_aucFLOW_AF_BLR_AF_TGT_SedanL)); + M_MEMCOPY((g_aucFLOW_AF_FOOT_PLUS), (c_aucFLOW_AF_FOOT_PLUS_SedanL)); + M_MEMCOPY((g_aucFLOW_AF_VENT_VALVE_MAX), (c_aucFLOW_AF_VENT_VALVE_MAX_SedanL)); + M_MEMCOPY((g_aucFLOW_AF_FOOT_VALVE_MAX), (c_aucFLOW_AF_FOOT_VALVE_MAX_SedanL)); +/* ------------------------------------------AF level conditions: End*/ + M_MEMCOPY((g_assFLOW_AFSM_AMB_TGT), (c_assFLOW_AFSM_AMB_TGT_SedanL)); + M_MEMCOPY((g_aucFLOW_AFSM_VENT_PLUS), (c_aucFLOW_AFSM_VENT_PLUS_SedanL)); + M_MEMCOPY((g_assFLOW_AFSM_TEMP_TGT), (c_assFLOW_AFSM_TEMP_TGT_SedanL)); + M_MEMCOPY((g_aucFLOW_AFSM_FOOT_PLUS), (c_aucFLOW_AFSM_FOOT_PLUS_SedanL)); + M_MEMCOPY((g_aucFLOW_AFSM_VENT_VALVE_MAX), (c_aucFLOW_AFSM_VENT_VALVE_MAX_SedanL)); + M_MEMCOPY((g_aucFLOW_AFSM_FOOT_VALVE_MAX), (c_aucFLOW_AFSM_FOOT_VALVE_MAX_SedanL)); +/* ------------------------------------------AF_summer level conditions: End*/ + M_MEMCOPY((g_aucMODE_INDEX), (c_aucMODE_INDEX_SedanL)); + M_MEMCOPY((g_assFOOT_STEP_DUCT_TGT), (c_assFOOT_STEP_DUCT_TGT_SedanL)); + M_MEMCOPY((g_assBLR_FOOT_IND), (c_assBLR_FOOT_IND_SedanL)); + M_MEMCOPY((g_ascFOOT_STEP_VALVE_P1), (c_ascFOOT_STEP_VALVE_P1_SedanL)); + M_MEMCOPY((g_ascFOOT_STEP_VALVE_P2), (c_ascFOOT_STEP_VALVE_P2_SedanL)); + M_MEMCOPY((g_ascFOOT_STEP_VALVE_P3), (c_ascFOOT_STEP_VALVE_P3_SedanL)); + M_MEMCOPY((g_ascFOOT_STEP_VALVE_M1), (c_ascFOOT_STEP_VALVE_M1_SedanL)); + M_MEMCOPY((g_ascFOOT_STEP_VALVE_M2), (c_ascFOOT_STEP_VALVE_M2_SedanL)); + M_MEMCOPY((g_ascFOOT_STEP_VALVE_M3), (c_ascFOOT_STEP_VALVE_M3_SedanL)); + M_MEMCOPY((g_assFOOT_STEP_BLR_P1), (c_assFOOT_STEP_BLR_P1_SedanL)); + M_MEMCOPY((g_assFOOT_STEP_BLR_P2), (c_assFOOT_STEP_BLR_P2_SedanL)); + M_MEMCOPY((g_assFOOT_STEP_BLR_P3), (c_assFOOT_STEP_BLR_P3_SedanL)); + M_MEMCOPY((g_assFOOT_STEP_BLR_M1), (c_assFOOT_STEP_BLR_M1_SedanL)); + M_MEMCOPY((g_assFOOT_STEP_BLR_M2), (c_assFOOT_STEP_BLR_M2_SedanL)); + M_MEMCOPY((g_assFOOT_STEP_BLR_M3), (c_assFOOT_STEP_BLR_M3_SedanL)); +/* ------------------------------------------Individual foot temperature: End*/ + M_MEMCOPY((g_aucREAR_FOOT_VALVE_AMB_LV2), (c_aucREAR_FOOT_VALVE_AMB_LV2_SedanL)); + M_MEMCOPY((g_aucREAR_FOOT_VALVE_AMB_LV3), (c_aucREAR_FOOT_VALVE_AMB_LV3_SedanL)); + M_MEMCOPY((g_aucREAR_FOOT_VALVE_AMB_LV4), (c_aucREAR_FOOT_VALVE_AMB_LV4_SedanL)); +/* ------------------------------------------Blowing foots from Rear HVAC: End*/ + M_MEMCOPY((g_ausFLOW_FR_VE2BLR_AF), (c_ausFLOW_FR_VE2BLR_AF_SedanL)); + M_MEMCOPY((g_ausFLOW_FR_BIVALVE_AF), (c_ausFLOW_FR_BIVALVE_AF_SedanL)); + M_MEMCOPY((g_ausFLOW_FR_BI2BLR_AF), (c_ausFLOW_FR_BI2BLR_AF_SedanL)); + M_MEMCOPY((g_ausFLOW_FR_FO2BLR_AF), (c_ausFLOW_FR_FO2BLR_AF_SedanL)); + M_MEMCOPY((g_ausFLOW_FR_AF2VALVE_AF), (c_ausFLOW_FR_AF2VALVE_AF_SedanL)); + M_MEMCOPY((g_ausFLOW_FR_AF2VALVE_SUMMER_AF), (c_ausFLOW_FR_AF2VALVE_SUMMER_AF_SedanL)); + M_MEMCOPY((g_ausFLOW_FR_FD2BLR_AF), (c_ausFLOW_FR_FD2BLR_AF_SedanL)); + M_MEMCOPY((g_ausFLOW_FR_DE2BLR_AF), (c_ausFLOW_FR_DE2BLR_AF_SedanL)); + M_MEMCOPY((g_ausFLOW_FR_TR2BLR_AF), (c_ausFLOW_FR_TR2BLR_AF_SedanL)); + M_MEMCOPY((g_ausFLOW_FR_HI2BLR_AF), (c_ausFLOW_FR_HI2BLR_AF_SedanL)); + M_MEMCOPY((g_ausFLOW_RE_VE2BLR_AF), (c_ausFLOW_RE_VE2BLR_AF_SedanL)); + M_MEMCOPY((g_ausFLOW_RE_BI2BLR_AF), (c_ausFLOW_RE_BI2BLR_AF_SedanL)); + M_MEMCOPY((g_ausFLOW_RE_FO2BLR_AF), (c_ausFLOW_RE_FO2BLR_AF_SedanL)); +/* ------------------------------------------Flow Control AF: End*/ + M_MEMCOPY((g_ascAUTO_STEP_AF_F), (c_ascAUTO_STEP_AF_F_SedanL)); + M_MEMCOPY((g_ascAUTO_STEP_AF_R), (c_ascAUTO_STEP_AF_R_SedanL)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_U_F_LV0_1), (c_assAUTO_STEP_DUCT_TG_U_F_LV0_1_SedanL)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_U_F_LV2_3), (c_assAUTO_STEP_DUCT_TG_U_F_LV2_3_SedanL)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_U_F_LV4_5), (c_assAUTO_STEP_DUCT_TG_U_F_LV4_5_SedanL)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_L_F_LV0_1), (c_assAUTO_STEP_DUCT_TG_L_F_LV0_1_SedanL)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_L_F_LV2_3), (c_assAUTO_STEP_DUCT_TG_L_F_LV2_3_SedanL)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_L_F_LV4_5), (c_assAUTO_STEP_DUCT_TG_L_F_LV4_5_SedanL)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_R_LV0_1), (c_assAUTO_STEP_DUCT_TG_R_LV0_1_SedanL)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_R_LV2_3), (c_assAUTO_STEP_DUCT_TG_R_LV2_3_SedanL)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_R_LV4_5), (c_assAUTO_STEP_DUCT_TG_R_LV4_5_SedanL)); +/* ------------------------------------------5 AUTO mode: End*/ + M_MEMCOPY((g_ausVALVE_SPACE), (c_ausVALVE_SPACE_SedanL)); + M_MEMCOPY((g_aucVALVE_SECTION_S1_F_SIDE_VENT), (c_aucVALVE_SECTION_S1_F_SIDE_VENT_SedanL)); + M_MEMCOPY((g_aucVALVE_SECTION_S1_F_CENT_VENT), (c_aucVALVE_SECTION_S1_F_CENT_VENT_SedanL)); + M_MEMCOPY((g_aucVALVE_SECTION_S1_F_DRIVER_FOOT), (c_aucVALVE_SECTION_S1_F_DRIVER_FOOT_SedanL)); + M_MEMCOPY((g_aucVALVE_SECTION_S1_F_RIGHT_PASS), (c_aucVALVE_SECTION_S1_F_RIGHT_PASS_SedanL)); + M_MEMCOPY((g_aucBLR_SPD_V1_1_F), (c_aucBLR_SPD_V1_1_F_SedanL)); + M_MEMCOPY((g_aucBLR_SPD_K2_1_F_SIDE_VENT), (c_aucBLR_SPD_K2_1_F_SIDE_VENT_SedanL)); + M_MEMCOPY((g_aucBLR_SPD_K2_2_F_CENT_VENT), (c_aucBLR_SPD_K2_2_F_CENT_VENT_SedanL)); + M_MEMCOPY((g_aucBLR_SPD_K2_3_F_DRIVER_FOOT), (c_aucBLR_SPD_K2_3_F_DRIVER_FOOT_SedanL)); + M_MEMCOPY((g_aucBLR_SPD_K2_4_F_RIGHT_PASS), (c_aucBLR_SPD_K2_4_F_RIGHT_PASS_SedanL)); + M_MEMCOPY((g_ausVALVE_VEH_SPD), (c_ausVALVE_VEH_SPD_SedanL)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_SIDE_VENT), (c_aucVALVE_VEH_SPD_SIDE_VENT_SedanL)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_SIDE_BI), (c_aucVALVE_VEH_SPD_SIDE_BI_SedanL)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_SIDE_AFOOT), (c_aucVALVE_VEH_SPD_SIDE_AFOOT_SedanL)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_CNET_VENT), (c_aucVALVE_VEH_SPD_CNET_VENT_SedanL)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_CENT_BI), (c_aucVALVE_VEH_SPD_CENT_BI_SedanL)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_CENT_AFOOT), (c_aucVALVE_VEH_SPD_CENT_AFOOT_SedanL)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_FOOT_BI), (c_aucVALVE_VEH_SPD_FOOT_BI_SedanL)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_FOOT_AFOOT), (c_aucVALVE_VEH_SPD_FOOT_AFOOT_SedanL)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_2FOOT), (c_aucVALVE_VEH_SPD_2FOOT_SedanL)); + M_MEMCOPY((g_aucBLR_SPD_VEH_SPD_V1_3), (c_aucBLR_SPD_VEH_SPD_V1_3_SedanL)); + M_MEMCOPY((g_aucFRONT_SIDE_DRS_PERCENT), (c_aucFRONT_SIDE_DRS_PERCENT_SedanL)); + M_MEMCOPY((g_aucFRONT_CENT_DRS_PERCENT), (c_aucFRONT_CENT_DRS_PERCENT_SedanL)); +/* ------------------------------------------Different blower speed FRONT MODE: End*/ + M_MEMCOPY((g_aucVALVE_S1_R_BIPILLAR), (c_aucVALVE_S1_R_BIPILLAR_SedanL)); + M_MEMCOPY((g_aucVALVE_S1_R_CENT_VENT), (c_aucVALVE_S1_R_CENT_VENT_SedanL)); + M_MEMCOPY((g_aucVALVE_S1_R_FOOT), (c_aucVALVE_S1_R_FOOT_SedanL)); + M_MEMCOPY((g_aucVALVE_PERC_R_BIPILLAR), (c_aucVALVE_PERC_R_BIPILLAR_SedanL)); + M_MEMCOPY((g_aucVALVE_PERC_R_CENT_VENT), (c_aucVALVE_PERC_R_CENT_VENT_SedanL)); + M_MEMCOPY((g_aucVALVE_PERC_R_FOOT), (c_aucVALVE_PERC_R_FOOT_SedanL)); + M_MEMCOPY((g_aucBLR_SPD_V1_1_R), (c_aucBLR_SPD_V1_1_R_SedanL)); + M_MEMCOPY((g_aucREAR_CEN_MIN_VALUE_BY_DRS_ZERO), (c_aucREAR_CEN_MIN_VALUE_BY_DRS_ZERO_SedanL)); + M_MEMCOPY((g_aucBLR_SPD_K2_1_R_BIPILLAR_MIN), (c_aucBLR_SPD_K2_1_R_BIPILLAR_MIN_SedanL)); + M_MEMCOPY((g_aucBLR_SPD_K2_2_R_CENT_VENT_MIN), (c_aucBLR_SPD_K2_2_R_CENT_VENT_MIN_SedanL)); + M_MEMCOPY((g_aucBLR_SPD_K2_3_R_FOOT_MIN), (c_aucBLR_SPD_K2_3_R_FOOT_MIN_SedanL)); + M_MEMCOPY((g_aucBLR_SPD_K2_1_R_BIPILLAR_MAX), (c_aucBLR_SPD_K2_1_R_BIPILLAR_MAX_SedanL)); + M_MEMCOPY((g_aucBLR_SPD_K2_2_R_CENT_VENTR_MAX), (c_aucBLR_SPD_K2_2_R_CENT_VENTR_MAX_SedanL)); + M_MEMCOPY((g_aucBLR_SPD_K2_3_R_FOOTR_MAX), (c_aucBLR_SPD_K2_3_R_FOOTR_MAX_SedanL)); + M_MEMCOPY((g_aucREAR_SIDE_DRS_PERCENT_VALVE), (c_aucREAR_SIDE_DRS_PERCENT_VALVE_SedanL)); + M_MEMCOPY((g_aucREAR_CENT_DRS_PERCENT_VALVE), (c_aucREAR_CENT_DRS_PERCENT_VALVE_SedanL)); + M_MEMCOPY((g_aucREAR_SIDE_DRS_PERCENT_AF), (c_aucREAR_SIDE_DRS_PERCENT_AF_SedanL)); + M_MEMCOPY((g_aucREAR_CENT_DRS_PERCENT_AF), (c_aucREAR_CENT_DRS_PERCENT_AF_SedanL)); +/* ------------------------------------------Different blower speed REAR MODE: End*/ + M_MEMCOPY((g_ausMIN_PWM), (c_ausMIN_PWM_SedanL)); +/* ------------------------------------------MinPWM: End*/ + M_MEMCOPY((g_assSTART_ENTER_COOLANT), (c_assSTART_ENTER_COOLANT_SedanL)); + M_MEMCOPY((g_assSTART_COOLANT_STEP0_TO_1), (c_assSTART_COOLANT_STEP0_TO_1_SedanL)); + M_MEMCOPY((g_assSTART_COOLANT_TO_STEP2), (c_assSTART_COOLANT_TO_STEP2_SedanL)); + M_MEMCOPY((g_assSTART_COOLANT_STEP1_BLR_F), (c_assSTART_COOLANT_STEP1_BLR_F_SedanL)); + M_MEMCOPY((g_assSTART_COOLANT_STEP1_BLR_R), (c_assSTART_COOLANT_STEP1_BLR_R_SedanL)); + M_MEMCOPY((g_assSTART_ENTER_INCAR), (c_assSTART_ENTER_INCAR_SedanL)); + M_MEMCOPY((g_ausSTART_ENTER_SETTEMP), (c_ausSTART_ENTER_SETTEMP_SedanL)); + M_MEMCOPY((g_aucSTART_INCAR_FLT_UP), (c_aucSTART_INCAR_FLT_UP_SedanL)); + M_MEMCOPY((g_aucSTART_INCAR_FLT_DN), (c_aucSTART_INCAR_FLT_DN_SedanL)); + M_MEMCOPY((g_aucSTART_VALVE_IDX_STEP1), (c_aucSTART_VALVE_IDX_STEP1_SedanL)); + M_MEMCOPY((g_aucSTART_AUTODEMIST2_STEP2), (c_aucSTART_AUTODEMIST2_STEP2_SedanL)); + M_MEMCOPY((g_aucSTART_ELEC_WINDOW), (c_aucSTART_ELEC_WINDOW_SedanL)); + M_MEMCOPY((g_ausSTART_BLR_AF_STEP12_F), (c_ausSTART_BLR_AF_STEP12_F_SedanL)); + M_MEMCOPY((g_ausSTART_BLR_AF_STEP12_R), (c_ausSTART_BLR_AF_STEP12_R_SedanL)); + M_MEMCOPY((g_ausSTART_BLR_SPD_STEP2_F), (c_ausSTART_BLR_SPD_STEP2_F_SedanL)); + M_MEMCOPY((g_ausSTART_BLR_SPD_STEP2_R), (c_ausSTART_BLR_SPD_STEP2_R_SedanL)); + M_MEMCOPY((g_aucSTART_DUCT_TGT_STEP2_FX_U), (c_aucSTART_DUCT_TGT_STEP2_FX_U_SedanL)); + M_MEMCOPY((g_aucSTART_DUCT_TGT_STEP2_FX_L), (c_aucSTART_DUCT_TGT_STEP2_FX_L_SedanL)); + M_MEMCOPY((g_aucSTART_DUCT_TGT_STEP2_RX), (c_aucSTART_DUCT_TGT_STEP2_RX_SedanL)); + M_MEMCOPY((g_aucSTART_VALVE_CHANGE_SPD_F), (c_aucSTART_VALVE_CHANGE_SPD_F_SedanL)); + M_MEMCOPY((g_aucSTART_VALVE_CHANGE_SPD_R), (c_aucSTART_VALVE_CHANGE_SPD_R_SedanL)); + M_MEMCOPY((g_ausSTART_TIME_STEP1_TO_2), (c_ausSTART_TIME_STEP1_TO_2_SedanL)); + M_MEMCOPY((g_ausSTART_TIME_STEP2_TO_3), (c_ausSTART_TIME_STEP2_TO_3_SedanL)); + M_MEMCOPY((g_assSTART_INCAR_STEP1_TO_2), (c_assSTART_INCAR_STEP1_TO_2_SedanL)); + M_MEMCOPY((g_assSTART_INCAR_STEP2_TO_3), (c_assSTART_INCAR_STEP2_TO_3_SedanL)); + M_MEMCOPY((g_aucSTART_3WAY_OPEN), (c_aucSTART_3WAY_OPEN_SedanL)); + M_MEMCOPY((g_aucSTART_2WAY_OPEN), (c_aucSTART_2WAY_OPEN_SedanL)); + M_MEMCOPY((g_aucSTART_TXV_F), (c_aucSTART_TXV_F_SedanL)); + M_MEMCOPY((g_aucSTART_TXV_R), (c_aucSTART_TXV_R_SedanL)); +/* ------------------------------------------Start control: End*/ + M_MEMCOPY((g_assFAILURE_AMB_TEMP), (c_assFAILURE_AMB_TEMP_SedanL)); + M_MEMCOPY((g_assAC_PRESSURE_LOW_HYS_UP), (c_assAC_PRESSURE_LOW_HYS_UP_SedanL)); + M_MEMCOPY((g_assAC_PRESSURE_LOW_HYS_DN), (c_assAC_PRESSURE_LOW_HYS_DN_SedanL)); + M_MEMCOPY((g_assAC_LOW_AMB_F), (c_assAC_LOW_AMB_F_SedanL)); + M_MEMCOPY((g_assAC_CUT_OFF_AMB_F), (c_assAC_CUT_OFF_AMB_F_SedanL)); + M_MEMCOPY((g_assAC_WINTER_TXV_DEWPOINT), (c_assAC_WINTER_TXV_DEWPOINT_SedanL)); + M_MEMCOPY((g_assAC_CUT_OFF_AMB_R), (c_assAC_CUT_OFF_AMB_R_SedanL)); + M_MEMCOPY((g_assEVA_TG_AMB_F), (c_assEVA_TG_AMB_F_SedanL)); + M_MEMCOPY((g_assEVA_TG_AMB_R), (c_assEVA_TG_AMB_R_SedanL)); + g_ucAC_EXTRA_RPM = c_ucAC_EXTRA_RPM_SedanL; + M_MEMCOPY((g_assAC_EVA_LV_SHUT_OFF), (c_assAC_EVA_LV_SHUT_OFF_SedanL)); + M_MEMCOPY((g_assAC_PRESSURE_HYS_HI_ENG_ON), (c_assAC_PRESSURE_HYS_HI_ENG_ON_SedanL)); + g_usCMP_MAX_ENG_OFF = c_usCMP_MAX_ENG_OFF_SedanL; + g_ucFAN_MAX_ENG_OFF = c_ucFAN_MAX_ENG_OFF_SedanL; + g_ssAC_WINTER_TXV_HYST = c_ssAC_WINTER_TXV_HYST_SedanL; + M_MEMCOPY((g_aucAC_PRESSURE_HYS_HI_ENG_OFF), (c_aucAC_PRESSURE_HYS_HI_ENG_OFF_SedanL)); + M_MEMCOPY((g_ausCMP_RPM_RESONANCE), (c_ausCMP_RPM_RESONANCE_SedanL)); +/* ------------------------------------------A/C Control Pressure : End*/ + M_MEMCOPY((g_assPRESSURE_TO_FAN_X), (c_assPRESSURE_TO_FAN_X_SedanL)); + M_MEMCOPY((g_aucPRESSURE_TO_FAN_Y), (c_aucPRESSURE_TO_FAN_Y_SedanL)); +/* ------------------------------------------CoolingFan: End*/ + g_ssREST_BATT = c_ssREST_BATT_SedanL; + g_ssRESTW_AMB = c_ssRESTW_AMB_SedanL; + M_MEMCOPY((g_assRESTW_WATER), (c_assRESTW_WATER_SedanL)); + g_usRESTW_READYEXPIRETIME = c_usRESTW_READYEXPIRETIME_SedanL; + M_MEMCOPY((g_aucRESTW_MODE), (c_aucRESTW_MODE_SedanL)); + g_usRESTW_TIMEOUTTIME = c_usRESTW_TIMEOUTTIME_SedanL; + g_ucRESTW_BLRSTEP = c_ucRESTW_BLRSTEP_SedanL; + g_ssRESTS_AMB = c_ssRESTS_AMB_SedanL; + g_uctRESTS_READYEXPIRETIME = c_uctRESTS_READYEXPIRETIME_SedanL; + M_MEMCOPY((g_aucRESTS_MODE), (c_aucRESTS_MODE_SedanL)); + g_usRESTS_TIMEOUTTIME = c_usRESTS_TIMEOUTTIME_SedanL; + g_ucRESTS_BLRSTEP = c_ucRESTS_BLRSTEP_SedanL; +/* ------------------------------------------Rest mode: End*/ + g_usFRESH_AIR_PURGE_ENTRY_TIME = c_usFRESH_AIR_PURGE_ENTRY_TIME_SedanL; + M_MEMCOPY((g_ausFRESH_AIR_PURGE_CHANGE_TIME), (c_ausFRESH_AIR_PURGE_CHANGE_TIME_SedanL)); +/* ------------------------------------------Purge Rec: End*/ + M_MEMCOPY((g_assMAX_DEF_U_DTG), (c_assMAX_DEF_U_DTG_SedanL)); + M_MEMCOPY((g_ausMAX_BLR_SPD), (c_ausMAX_BLR_SPD_SedanL)); +/* ------------------------------------------MAX DEF: End*/ + M_MEMCOPY((g_aucAQS_REC_LV_CO), (c_aucAQS_REC_LV_CO_SedanL)); + M_MEMCOPY((g_aucAQS_OSA_LV_CO), (c_aucAQS_OSA_LV_CO_SedanL)); + M_MEMCOPY((g_aucAQS_REC_LV_NOX), (c_aucAQS_REC_LV_NOX_SedanL)); + M_MEMCOPY((g_aucAQS_OSA_LV_NOX), (c_aucAQS_OSA_LV_NOX_SedanL)); + M_MEMCOPY((g_aucAQS_REC_LV_NH3), (c_aucAQS_REC_LV_NH3_SedanL)); + M_MEMCOPY((g_aucAQS_OSA_LV_NH3), (c_aucAQS_OSA_LV_NH3_SedanL)); + g_ucAQS_REC_ON_TIME = c_ucAQS_REC_ON_TIME_SedanL; + M_MEMCOPY((g_aucAQS_REC_ON_WAIT), (c_aucAQS_REC_ON_WAIT_SedanL)); +/* ------------------------------------------Aqs: End*/ + g_usAUTODEMIST_LV2_BLR_PLUS = c_usAUTODEMIST_LV2_BLR_PLUS_SedanL; + g_usAUTODEMIST_LV3_BLR_PLUS = c_usAUTODEMIST_LV3_BLR_PLUS_SedanL; + M_MEMCOPY((g_assAUTODEMIST_OFFSET_AMB_TEMP), (c_assAUTODEMIST_OFFSET_AMB_TEMP_SedanL)); + M_MEMCOPY((g_assAUTODEMIST_OFFSET_VENT_TEMP), (c_assAUTODEMIST_OFFSET_VENT_TEMP_SedanL)); + M_MEMCOPY((g_assAUTODEMIST_STEP_UP), (c_assAUTODEMIST_STEP_UP_SedanL)); + M_MEMCOPY((g_assAUTODEMIST_STEP_DN), (c_assAUTODEMIST_STEP_DN_SedanL)); + M_MEMCOPY((g_assAUTODEMIST_WINTER), (c_assAUTODEMIST_WINTER_SedanL)); +/* ------------------------------------------Auto Demist: End*/ + g_ssAUTODEMIST_ELEC_AMB_ENTRY = c_ssAUTODEMIST_ELEC_AMB_ENTRY_SedanL; + M_MEMCOPY((g_assAUTODEMIST_ELEC_WINDSHELD_TEMP), (c_assAUTODEMIST_ELEC_WINDSHELD_TEMP_SedanL)); +/* ------------------------------------------Electric AutoDemist: End*/ + g_ssAMBFILT_WATER = c_ssAMBFILT_WATER_SedanL; + M_MEMCOPY((g_aucAMBFILT_H_CNT), (c_aucAMBFILT_H_CNT_SedanL)); + g_ssAMB_FAILSAFE = c_ssAMB_FAILSAFE_SedanL; + g_ssAMBKEEP_KAT = c_ssAMBKEEP_KAT_SedanL; + g_ssAMBKEEP_KAT_PLUS = c_ssAMBKEEP_KAT_PLUS_SedanL; + g_ssAMBKEEP_WATER = c_ssAMBKEEP_WATER_SedanL; + M_MEMCOPY((g_aucAMBRATE_RISING), (c_aucAMBRATE_RISING_SedanL)); + M_MEMCOPY((g_aucAMBRATE_FALLING), (c_aucAMBRATE_FALLING_SedanL)); + M_MEMCOPY((g_aucAMBRATE_RISING_DIFF), (c_aucAMBRATE_RISING_DIFF_SedanL)); + M_MEMCOPY((g_aucAMBRATE_FALLING_DIFF), (c_aucAMBRATE_FALLING_DIFF_SedanL)); +/* ------------------------------------------Ambient: End*/ + M_MEMCOPY((g_ausINCARRATE_RISING_F), (c_ausINCARRATE_RISING_F_SedanL)); + M_MEMCOPY((g_ausINCARRATE_FALLING_F), (c_ausINCARRATE_FALLING_F_SedanL)); + M_MEMCOPY((g_ausINCARRATE_RISING_DIFF_F), (c_ausINCARRATE_RISING_DIFF_F_SedanL)); + M_MEMCOPY((g_ausINCARRATE_FALLING_DIFF_F), (c_ausINCARRATE_FALLING_DIFF_F_SedanL)); + M_MEMCOPY((g_ausINCARRATE_RISING_R), (c_ausINCARRATE_RISING_R_SedanL)); + M_MEMCOPY((g_ausINCARRATE_FALLING_R), (c_ausINCARRATE_FALLING_R_SedanL)); + M_MEMCOPY((g_ausINCARRATE_RISING_DIFF_R), (c_ausINCARRATE_RISING_DIFF_R_SedanL)); + M_MEMCOPY((g_ausINCARRATE_FALLING_DIFF_R), (c_ausINCARRATE_FALLING_DIFF_R_SedanL)); +/* ------------------------------------------Incar: End*/ + M_MEMCOPY((g_ausSUNRATE_RISING), (c_ausSUNRATE_RISING_SedanL)); + M_MEMCOPY((g_ausSUNRATE_FALLING), (c_ausSUNRATE_FALLING_SedanL)); +/* ------------------------------------------Sun: End*/ + M_MEMCOPY((g_ausAMB_LV_CHANGE_UNIT), (c_ausAMB_LV_CHANGE_UNIT_SedanL)); + M_MEMCOPY((g_aucAMB_LV_CHANGE_SEC), (c_aucAMB_LV_CHANGE_SEC_SedanL)); +/* ------------------------------------------Level Chage: End*/ + g_ssTHREEWAY_WATER = c_ssTHREEWAY_WATER_SedanL; + M_MEMCOPY((g_assTHREEWAY_DUCT_TGT_R), (c_assTHREEWAY_DUCT_TGT_R_SedanL)); + M_MEMCOPY((g_aucTHEREEWAY_EXPIRING), (c_aucTHEREEWAY_EXPIRING_SedanL)); +/* ------------------------------------------Three way: End*/ + M_MEMCOPY((g_assTWOWAY_REAR_DUCTTGT_R), (c_assTWOWAY_REAR_DUCTTGT_R_SedanL)); + M_MEMCOPY((g_aucTWOWAY_EXPIRING), (c_aucTWOWAY_EXPIRING_SedanL)); +/* ------------------------------------------two-way: End*/ + M_MEMCOPY((g_aucACT_HOM_SPD_FL_CH0), (c_aucACT_HOM_SPD_FL_CH0_SedanL)); + M_MEMCOPY((g_aucACT_HOM_SPD_FR_CH1), (c_aucACT_HOM_SPD_FR_CH1_SedanL)); + M_MEMCOPY((g_aucACT_HOM_SPD_R_CH2), (c_aucACT_HOM_SPD_R_CH2_SedanL)); + M_MEMCOPY((g_aucACT_HOM_SPD_R_EX_CH2), (c_aucACT_HOM_SPD_R_EX_CH2_SedanL)); + M_MEMCOPY((g_aucACT_MOV_SPD_FL_CH0), (c_aucACT_MOV_SPD_FL_CH0_SedanL)); + M_MEMCOPY((g_aucACT_MOV_SPD_FR_CH1), (c_aucACT_MOV_SPD_FR_CH1_SedanL)); + M_MEMCOPY((g_aucACT_MOV_SPD_R_CH2), (c_aucACT_MOV_SPD_R_CH2_SedanL)); + M_MEMCOPY((g_aucACT_MOV_SPD_R_EX_CH2), (c_aucACT_MOV_SPD_R_EX_CH2_SedanL)); +/* ------------------------------------------Actuator Homing: End*/ + M_MEMCOPY((g_assHI_MODE_ENG_TMEP), (c_assHI_MODE_ENG_TMEP_SedanL)); + M_MEMCOPY((g_aucHI_MODE_BLR_STEP_STS), (c_aucHI_MODE_BLR_STEP_STS_SedanL)); +/* ------------------------------------------Hi Mode: End*/ + M_MEMCOPY((g_ausMinusAF_GlassPos_L), (c_ausMinusAF_GlassPos_L_SedanL)); + M_MEMCOPY((g_ausMinusAF_GlassPos_R), (c_ausMinusAF_GlassPos_R_SedanL)); +/* ------------------------------------------GlassPosition: End*/ + M_MEMCOPY((g_assFoot2_Lv3_Amb), (c_assFoot2_Lv3_Amb_SedanL)); + M_MEMCOPY((g_assFoot2_Lv4_Amb), (c_assFoot2_Lv4_Amb_SedanL)); + M_MEMCOPY((g_assFoot2_Lv5_Amb), (c_assFoot2_Lv5_Amb_SedanL)); + M_MEMCOPY((g_assFoot2_Lv3_DuctTgt_Plus), (c_assFoot2_Lv3_DuctTgt_Plus_SedanL)); + M_MEMCOPY((g_assFoot2_Lv4_DuctTgt_Plus), (c_assFoot2_Lv4_DuctTgt_Plus_SedanL)); + M_MEMCOPY((g_assFoot2_Lv5_DuctTgt_Plus), (c_assFoot2_Lv5_DuctTgt_Plus_SedanL)); + M_MEMCOPY((g_ausFoot2_Lv1_FrontBlr_X), (c_ausFoot2_Lv1_FrontBlr_X_SedanL)); + M_MEMCOPY((g_ausFoot2_Lv1_Foot2Act_Y), (c_ausFoot2_Lv1_Foot2Act_Y_SedanL)); + M_MEMCOPY((g_assFoot2_Lv2_Threshold_Diff), (c_assFoot2_Lv2_Threshold_Diff_SedanL)); + M_MEMCOPY((g_assFoot2_Lv3_Threshold_Diff), (c_assFoot2_Lv3_Threshold_Diff_SedanL)); +/* ------------------------------------------Foot2 Ctrl: End*/ + M_MEMCOPY((g_ausDbF_Side_Af_Bi), (c_ausDbF_Side_Af_Bi_SedanL)); + M_MEMCOPY((g_ausDbF_Side_Af_Bi2), (c_ausDbF_Side_Af_Bi2_SedanL)); + M_MEMCOPY((g_ausDbF_Side_Af_Vent), (c_ausDbF_Side_Af_Vent_SedanL)); + M_MEMCOPY((g_ausDbF_Side_Bi_Bi2), (c_ausDbF_Side_Bi_Bi2_SedanL)); + M_MEMCOPY((g_ausDbF_Side_Bi_Vent), (c_ausDbF_Side_Bi_Vent_SedanL)); + M_MEMCOPY((g_ausDbF_Side_Bi2_Vent), (c_ausDbF_Side_Bi2_Vent_SedanL)); + M_MEMCOPY((g_ausDbF_Cen_Af_Bi), (c_ausDbF_Cen_Af_Bi_SedanL)); + M_MEMCOPY((g_ausDbF_Cen_Af_Bi2), (c_ausDbF_Cen_Af_Bi2_SedanL)); + M_MEMCOPY((g_ausDbF_Cen_Af_Vent), (c_ausDbF_Cen_Af_Vent_SedanL)); + M_MEMCOPY((g_ausDbF_Cen_Bi_Bi2), (c_ausDbF_Cen_Bi_Bi2_SedanL)); + M_MEMCOPY((g_ausDbF_Cen_Bi_Vent), (c_ausDbF_Cen_Bi_Vent_SedanL)); + M_MEMCOPY((g_ausDbF_Cen_Bi2_Vent), (c_ausDbF_Cen_Bi2_Vent_SedanL)); + M_MEMCOPY((g_ausDbF_Foot_Af_Bi), (c_ausDbF_Foot_Af_Bi_SedanL)); + M_MEMCOPY((g_ausDbF_Foot_Af_Bi2), (c_ausDbF_Foot_Af_Bi2_SedanL)); + M_MEMCOPY((g_ausDbF_Foot_Af_Vent), (c_ausDbF_Foot_Af_Vent_SedanL)); + M_MEMCOPY((g_ausDbF_Foot_Bi_Bi2), (c_ausDbF_Foot_Bi_Bi2_SedanL)); + M_MEMCOPY((g_ausDbF_Foot_Bi_Vent), (c_ausDbF_Foot_Bi_Vent_SedanL)); + M_MEMCOPY((g_ausDbF_Foot_Bi2_Vent), (c_ausDbF_Foot_Bi2_Vent_SedanL)); + M_MEMCOPY((g_ausDbF_AF_Af_Bi), (c_ausDbF_AF_Af_Bi_SedanL)); + M_MEMCOPY((g_ausDbF_AF_Af_Bi2), (c_ausDbF_AF_Af_Bi2_SedanL)); + M_MEMCOPY((g_ausDbF_AF_Af_Vent), (c_ausDbF_AF_Af_Vent_SedanL)); + M_MEMCOPY((g_ausDbF_AF_Bi_Bi2), (c_ausDbF_AF_Bi_Bi2_SedanL)); + M_MEMCOPY((g_ausDbF_AF_Bi_Vent), (c_ausDbF_AF_Bi_Vent_SedanL)); + M_MEMCOPY((g_ausDbF_AF_Bi2_Vent), (c_ausDbF_AF_Bi2_Vent_SedanL)); + M_MEMCOPY((g_ausDbF_Pwm_Af_Bi), (c_ausDbF_Pwm_Af_Bi_SedanL)); + M_MEMCOPY((g_ausDbF_Pwm_Af_Bi2), (c_ausDbF_Pwm_Af_Bi2_SedanL)); + M_MEMCOPY((g_ausDbF_Pwm_Af_Vent), (c_ausDbF_Pwm_Af_Vent_SedanL)); + M_MEMCOPY((g_ausDbF_Pwm_Bi_Bi2), (c_ausDbF_Pwm_Bi_Bi2_SedanL)); + M_MEMCOPY((g_ausDbF_Pwm_Bi_Vent), (c_ausDbF_Pwm_Bi_Vent_SedanL)); + M_MEMCOPY((g_ausDbF_Pwm_Bi2_Vent), (c_ausDbF_Pwm_Bi2_Vent_SedanL)); +/* ------------------------------------------Different blower Front: End*/ + g_usAromaPwm_Min = c_usAromaPwm_Min_SedanL; + g_usAromaPwm_Max = c_usAromaPwm_Max_SedanL; +/* ------------------------------------------Aroma Limit Pwm: End*/ + M_MEMCOPY((g_assPID_COMPRESSOR), (c_assPID_COMPRESSOR_SedanL)); + M_MEMCOPY((g_assPID_VALVE_FRONT_UP), (c_assPID_VALVE_FRONT_UP_SedanL)); + M_MEMCOPY((g_assPID_VALVE_FRONT_LOW), (c_assPID_VALVE_FRONT_LOW_SedanL)); + M_MEMCOPY((g_assPID2_VALVE_FRONT), (c_assPID2_VALVE_FRONT_SedanL)); + M_MEMCOPY((g_assPID_VALVE_REAR), (c_assPID_VALVE_REAR_SedanL)); + M_MEMCOPY((g_assPID2_VALVE_REAR), (c_assPID2_VALVE_REAR_SedanL)); + M_MEMCOPY((g_assPID_VALVE_TG), (c_assPID_VALVE_TG_SedanL)); + M_MEMCOPY((g_assPID_VALVE_SPEED), (c_assPID_VALVE_SPEED_SedanL)); + + + /* ------------------------------------------PID: End*/ + + + M_MEMCOPY((g_aucFRONT_SIDE_DRS_PERCENT), (c_aucFRONT_SIDE_DRS_PERCENT_AF_SedanL)); + M_MEMCOPY((g_aucFRONT_CENT_DRS_PERCENT), (c_aucFRONT_CENT_DRS_PERCENT_AF_SedanL)); + +/*********************************************************Cal Table End*/ + +} +/****************************************************************************** + * LOCAL FUNCTIONS + *****************************************************************************/ +/* End of Excel line : 2159 */ +/****************************************************************************** + * EOF + *****************************************************************************/ diff --git a/MODULES/HVAC_M7_DataNonVolatile/calib/Rs_Cal_0_SedanL.h b/MODULES/HVAC_M7_DataNonVolatile/calib/Rs_Cal_0_SedanL.h new file mode 100644 index 0000000..72939af --- /dev/null +++ b/MODULES/HVAC_M7_DataNonVolatile/calib/Rs_Cal_0_SedanL.h @@ -0,0 +1,38 @@ +/** Doxygen: File brief + ****************************************************************************** + * @file Rs_Cal_0_SedanL.h + * @brief No brief + * @remark Generated by C:\9999\Rs_Cal_R23_ver21_SedanL.xlsm + * Generated on yyyy-mm-dd hh:mm:ss + *****************************************************************************/ +#ifndef RS_CAL_0_SEDANL_H__ +#define RS_CAL_0_SEDANL_H__ + +/****************************************************************************** + * INCLUDE FILES +*****************************************************************************/ +#include "rtwtypes.h" +#include "common.h" +#include "HVAC_preDefine.h" +#include "Rs_Cal_Base.h" + +/****************************************************************************** + * MACRO DECLARATIONS + *****************************************************************************/ +/****************************************************************************** + * GLOBAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS) + *****************************************************************************/ +/****************************************************************************** + * GLOBAL VARIABLES DECLARATIONS + *****************************************************************************/ +extern SECT_VEH_CAL_0 const tU08 c_ucCalFromRelease_SedanL; +/****************************************************************************** + * GLOBAL FUNCTIONS DECLARATIONS + *****************************************************************************/ +extern void Rs_Cal_0_SedanL(void); + +/* End of Excel line : 34 */ +#endif /*RS_CAL_0_SEDANL_H__*/ +/****************************************************************************** + * EOF + *****************************************************************************/ diff --git a/MODULES/HVAC_M7_DataNonVolatile/calib/Rs_Cal_1_SedanH.c b/MODULES/HVAC_M7_DataNonVolatile/calib/Rs_Cal_1_SedanH.c new file mode 100644 index 0000000..a4b044e --- /dev/null +++ b/MODULES/HVAC_M7_DataNonVolatile/calib/Rs_Cal_1_SedanH.c @@ -0,0 +1,2162 @@ +/** Doxygen: File brief + ****************************************************************************** + * @file Rs_Cal_1_SedanH.c + * @brief No brief + * @remark Generated by C:\9999\Rs_Cal_R23_ver21_SedanL.xlsm + * Generated on yyyy-mm-dd hh:mm:ss + *****************************************************************************/ +/****************************************************************************** + * INCLUDE FILES + *****************************************************************************/ +#include "Rs_Cal_1_SedanH.h" + +/****************************************************************************** + * MACRO DECLARATIONS + *****************************************************************************/ +/*PRQA S 0615 EOF #suppress : More than 511 block scope identifiers, from Calibration data table, No impact*/ +/*PRQA S 1514 EOF #suppress : In the same translation(used != defined), from Calibration data table, No impact*/ +/*PRQA S 3408 EOF #suppress : To manage Cal. data separately, from Calibration data table, No Impact*/ +/****************************************************************************** + * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS) + *****************************************************************************/ +/****************************************************************************** + * GLOBAL VARIABLES DECLARATIONS + *****************************************************************************/ +SECT_VEH_CAL_1 const tU08 c_ucCalFromRelease_SedanH = ID_TRUE; +SECT_VEH_CAL_1 const tU08 c_aucCAL_FP_DATE_SedanH[3] = { VERSION_SEDANH_Y, VERSION_SEDANH_M, VERSION_SEDANH_D}; +SECT_VEH_CAL_1 const tU08 c_aucCAL_VERSION_SedanH[2] = { 0, 20}; +SECT_VEH_CAL_1 const tU08 c_ucCAL_VARIANT_SedanH = 2; +/* ------------------------------------------Cal Version : End*/ +SECT_VEH_CAL_1 const tU16 c_ausSET_TEMP_FULL_SedanH[13] = { 170, 180, 190, 200, 210, 220, 230, 240, 250, 260, 270, 280, 290}; +SECT_VEH_CAL_1 const tU16 c_ausSET_TEMP_HALF_SedanH[7] = { 170, 190, 210, 230, 250, 270, 290}; +/* ------------------------------------------Set Temp : End*/ +SECT_VEH_CAL_1 const tS16 c_assINCAR_TG_FL_LV0_SedanH[13] = { 180, 190, 200, 210, 220, 235, 245, 255, 270, 280, 290, 310, 330}; +SECT_VEH_CAL_1 const tS16 c_assINCAR_TG_FR_LV0_SedanH[13] = { 180, 190, 200, 210, 220, 235, 245, 255, 270, 280, 290, 310, 330}; +SECT_VEH_CAL_1 const tS16 c_assVTG_FL_LV0_SedanH[13] = { 120, 105, 100, 95, 90, 85, 80, 80, 70, 65, 60, 60, 60}; +SECT_VEH_CAL_1 const tS16 c_assVTG_FR_LV0_SedanH[13] = { 120, 105, 100, 95, 90, 85, 80, 80, 70, 65, 60, 60, 60}; +SECT_VEH_CAL_1 const tS16 c_assVF_MIN_LV0_SedanH[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_1 const tS16 c_assVF_MAX_LV0_SedanH[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_Y1_LV0_SedanH[7] = { 60, 60, 50, 50, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_Y2_LV0_SedanH[7] = { 20, 20, 20, 20, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_Y3_LV0_SedanH[7] = { -20, -20, -20, -10, 5, 5, 5}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_Y4_LV0_SedanH[7] = { -50, -50, -50, -20, 10, 10, 10}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_X1_LV0_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_X2_LV0_SedanH[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_X3_LV0_SedanH[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_X4_LV0_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assVF_AMB_Y1_LV0_SedanH[7] = { 10, 10, 10, 5, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVF_AMB_Y2_LV0_SedanH[7] = { -10, -10, -10, -10, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVF_AMB_X1_LV0_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assVF_AMB_X2_LV0_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assVF_SUN_Y1_LV0_SedanH[7] = { 20, 20, 20, 20, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVF_SUN_Y2_LV0_SedanH[7] = { 50, 50, 50, 50, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVF_SUN_X1_LV0_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assVF_SUN_X2_LV0_SedanH[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_1 const tS16 c_assTG_FLU_LV0_SedanH[13] = { 20, 20, 20, 50, 60, 80, 100, 125, 180, 250, 380, 500, 550}; +SECT_VEH_CAL_1 const tS16 c_assTG_FRU_LV0_SedanH[13] = { 20, 20, 20, 50, 60, 80, 100, 125, 180, 250, 380, 500, 550}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_MIN_LV0_SedanH[7] = { 20, 20, 20, 50, 50, 50, 50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_MAX_LV0_SedanH[7] = { 600, 600, 600, 600, 600, 600, 600}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_Y1_LV0_SedanH[7] = { 0, -20, -50, -50, -100, -150, -200}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_Y2_LV0_SedanH[7] = { 0, -10, -30, -50, -50, -50, -50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_Y3_LV0_SedanH[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_Y4_LV0_SedanH[7] = { 200, 200, 200, 150, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_X1_LV0_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_X2_LV0_SedanH[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_X3_LV0_SedanH[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_X4_LV0_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_AMB_Y1_LV0_SedanH[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_AMB_Y2_LV0_SedanH[7] = { 50, 50, 50, 50, 50, 25, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_AMB_X1_LV0_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_AMB_X2_LV0_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_SUN_Y1_LV0_SedanH[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_SUN_Y2_LV0_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_SUN_X1_LV0_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_SUN_X2_LV0_SedanH[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_1 const tS16 c_assTG_FLL_LV0_SedanH[13] = { 150, 150, 150, 150, 200, 250, 300, 400, 450, 500, 600, 650, 700}; +SECT_VEH_CAL_1 const tS16 c_assTG_FRL_LV0_SedanH[13] = { 150, 150, 150, 150, 200, 250, 300, 400, 450, 500, 600, 650, 700}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_MIN_LV0_SedanH[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_MAX_LV0_SedanH[7] = { 400, 450, 500, 600, 600, 600, 600}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_Y1_LV0_SedanH[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_Y2_LV0_SedanH[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_Y3_LV0_SedanH[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_Y4_LV0_SedanH[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_X1_LV0_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_X2_LV0_SedanH[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_X3_LV0_SedanH[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_X4_LV0_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_AMB_Y1_LV0_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_AMB_Y2_LV0_SedanH[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_AMB_X1_LV0_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_AMB_X2_LV0_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_SUN_Y1_LV0_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_SUN_Y2_LV0_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_SUN_X1_LV0_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_SUN_X2_LV0_SedanH[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_1 const tS16 c_assINCAR_TG_RL_LV0_SedanH[13] = { 190, 195, 200, 215, 230, 240, 250, 270, 280, 290, 300, 310, 320}; +SECT_VEH_CAL_1 const tS16 c_assINCAR_TG_RR_LV0_SedanH[13] = { 190, 195, 200, 215, 230, 240, 250, 270, 280, 290, 300, 310, 320}; +SECT_VEH_CAL_1 const tS16 c_assVTG_RL_LV0_SedanH[13] = { 110, 100, 92, 82, 75, 70, 65, 65, 60, 60, 60, 60, 60}; +SECT_VEH_CAL_1 const tS16 c_assVTG_RR_LV0_SedanH[13] = { 110, 100, 92, 82, 75, 70, 65, 65, 60, 60, 60, 60, 60}; +SECT_VEH_CAL_1 const tS16 c_assVR_MIN_LV0_SedanH[7] = { 80, 80, 40, 40, 40, 30, 30}; +SECT_VEH_CAL_1 const tS16 c_assVR_MAX_LV0_SedanH[7] = { 160, 160, 160, 160, 100, 80, 80}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_Y1_LV0_SedanH[7] = { 60, 60, 50, 50, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_Y2_LV0_SedanH[7] = { 20, 20, 20, 20, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_Y3_LV0_SedanH[7] = { -20, -20, -20, -10, 5, 5, 5}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_Y4_LV0_SedanH[7] = { -50, -50, -50, -20, 10, 10, 10}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_X1_LV0_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_X2_LV0_SedanH[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_X3_LV0_SedanH[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_X4_LV0_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assVR_AMB_Y1_LV0_SedanH[7] = { 20, 20, 20, 20, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVR_AMB_Y2_LV0_SedanH[7] = { 0, 0, -50, -50, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVR_AMB_X1_LV0_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assVR_AMB_X2_LV0_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assVR_SUN_Y1_LV0_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVR_SUN_Y2_LV0_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVR_SUN_X1_LV0_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assVR_SUN_X2_LV0_SedanH[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_1 const tS16 c_assTG_RL_LV0_SedanH[13] = { 30, 30, 30, 50, 90, 100, 120, 180, 240, 320, 400, 450, 500}; +SECT_VEH_CAL_1 const tS16 c_assTG_RR_LV0_SedanH[13] = { 30, 30, 30, 50, 90, 100, 120, 180, 240, 320, 400, 450, 500}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_MIN_LV0_SedanH[7] = { 20, 20, 20, 20, 50, 50, 50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_MAX_LV0_SedanH[7] = { 400, 400, 450, 500, 600, 600, 600}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_Y1_LV0_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_Y2_LV0_SedanH[7] = { -40, -40, -40, -40, -40, -50, -60}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_Y3_LV0_SedanH[7] = { 40, 40, 40, 40, 20, 20, 20}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_Y4_LV0_SedanH[7] = { 200, 200, 200, 100, 50, 50, 50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_X1_LV0_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_X2_LV0_SedanH[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_X3_LV0_SedanH[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_X4_LV0_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_AMB_Y1_LV0_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_AMB_Y2_LV0_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_AMB_X1_LV0_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_AMB_X2_LV0_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_SUN_Y1_LV0_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_SUN_Y2_LV0_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_SUN_X1_LV0_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_SUN_X2_LV0_SedanH[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_DUCT_TIME_FR_LV0_SedanH[7] = { 600, 600, 600, 600, 600, 600, 600}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_DUCT_TIME_FL_LV0_SedanH[7] = { 600, 600, 600, 600, 600, 600, 600}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_DUCT_RATE_LV0_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_DUCT_MAX_LV0_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_AF_TIME_FR_LV0_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_AF_TIME_FL_LV0_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_AF_RATE_LV0_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_AF_MAX_LV0_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +/* ------------------------------------------Lv0 : End*/ +SECT_VEH_CAL_1 const tS16 c_assINCAR_TG_FL_LV1_SedanH[13] = { 210, 225, 240, 255, 270, 285, 300, 310, 320, 330, 340, 350, 360}; +SECT_VEH_CAL_1 const tS16 c_assINCAR_TG_FR_LV1_SedanH[13] = { 210, 225, 240, 255, 270, 285, 300, 310, 320, 330, 340, 350, 360}; +SECT_VEH_CAL_1 const tS16 c_assVTG_FL_LV1_SedanH[13] = { 120, 110, 100, 90, 85, 75, 70, 70, 70, 70, 70, 70, 70}; +SECT_VEH_CAL_1 const tS16 c_assVTG_FR_LV1_SedanH[13] = { 120, 110, 100, 90, 85, 75, 70, 70, 70, 70, 70, 70, 70}; +SECT_VEH_CAL_1 const tS16 c_assVF_MIN_LV1_SedanH[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_1 const tS16 c_assVF_MAX_LV1_SedanH[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_Y1_LV1_SedanH[7] = { 30, 30, 30, 30, 30, 25, 20}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_Y2_LV1_SedanH[7] = { 10, 10, 10, 10, 5, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_Y3_LV1_SedanH[7] = { -10, -8, -5, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_Y4_LV1_SedanH[7] = { -30, -30, -20, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_X1_LV1_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_X2_LV1_SedanH[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_X3_LV1_SedanH[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_X4_LV1_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assVF_AMB_Y1_LV1_SedanH[7] = { 5, 4, 3, 2, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVF_AMB_Y2_LV1_SedanH[7] = { 5, 5, 5, 5, 5, 13, 25}; +SECT_VEH_CAL_1 const tS16 c_assVF_AMB_X1_LV1_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assVF_AMB_X2_LV1_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assVF_SUN_Y1_LV1_SedanH[7] = { 15, 15, 15, 11, 5, 3, 3}; +SECT_VEH_CAL_1 const tS16 c_assVF_SUN_Y2_LV1_SedanH[7] = { 33, 30, 25, 22, 10, 5, 5}; +SECT_VEH_CAL_1 const tS16 c_assVF_SUN_X1_LV1_SedanH[7] = { 500, 500, 500, 500, 500, 500, 500}; +SECT_VEH_CAL_1 const tS16 c_assVF_SUN_X2_LV1_SedanH[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_1 const tS16 c_assTG_FLU_LV1_SedanH[13] = { 50, 70, 90, 120, 130, 140, 180, 200, 240, 260, 280, 300, 320}; +SECT_VEH_CAL_1 const tS16 c_assTG_FRU_LV1_SedanH[13] = { 50, 70, 90, 120, 130, 140, 180, 200, 240, 260, 280, 300, 320}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_MIN_LV1_SedanH[7] = { 20, 20, 20, 20, 50, 50, 50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_MAX_LV1_SedanH[7] = { 400, 450, 450, 500, 600, 600, 600}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_Y1_LV1_SedanH[7] = { 0, -20, -50, -70, -100, -150, -200}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_Y2_LV1_SedanH[7] = { 0, -10, -30, -50, -50, -50, -50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_Y3_LV1_SedanH[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_Y4_LV1_SedanH[7] = { 200, 200, 200, 150, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_X1_LV1_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_X2_LV1_SedanH[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_X3_LV1_SedanH[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_X4_LV1_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_AMB_Y1_LV1_SedanH[7] = { -50, -50, -50, -50, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_AMB_Y2_LV1_SedanH[7] = { 0, 20, 20, 25, 55, 55, 75}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_AMB_X1_LV1_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_AMB_X2_LV1_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_SUN_Y1_LV1_SedanH[7] = { -50, -50, -35, -20, -50, -50, -50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_SUN_Y2_LV1_SedanH[7] = { -100, -100, -75, -50, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_SUN_X1_LV1_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_SUN_X2_LV1_SedanH[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_1 const tS16 c_assTG_FLL_LV1_SedanH[13] = { 150, 200, 200, 200, 200, 220, 250, 280, 320, 360, 400, 450, 500}; +SECT_VEH_CAL_1 const tS16 c_assTG_FRL_LV1_SedanH[13] = { 150, 200, 200, 200, 200, 200, 220, 280, 320, 360, 400, 450, 500}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_MIN_LV1_SedanH[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_MAX_LV1_SedanH[7] = { 450, 450, 500, 600, 600, 600, 600}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_Y1_LV1_SedanH[7] = { 0, 0, 0, 0, 0, -100, -200}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_Y2_LV1_SedanH[7] = { 0, 0, 0, 0, -50, -50, -50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_Y3_LV1_SedanH[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_Y4_LV1_SedanH[7] = { 100, 100, 100, 50, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_X1_LV1_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_X2_LV1_SedanH[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_X3_LV1_SedanH[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_X4_LV1_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_AMB_Y1_LV1_SedanH[7] = { -80, -80, -80, -65, -50, -50, -50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_AMB_Y2_LV1_SedanH[7] = { 40, 40, 65, 75, 100, 100, 95}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_AMB_X1_LV1_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_AMB_X2_LV1_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_SUN_Y1_LV1_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_SUN_Y2_LV1_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_SUN_X1_LV1_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_SUN_X2_LV1_SedanH[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_1 const tS16 c_assINCAR_TG_RL_LV1_SedanH[13] = { 225, 240, 255, 270, 285, 300, 310, 320, 330, 340, 350, 360, 370}; +SECT_VEH_CAL_1 const tS16 c_assINCAR_TG_RR_LV1_SedanH[13] = { 225, 240, 255, 270, 285, 300, 310, 320, 330, 340, 350, 360, 370}; +SECT_VEH_CAL_1 const tS16 c_assVTG_RL_LV1_SedanH[13] = { 115, 105, 95, 80, 65, 60, 55, 50, 50, 50, 50, 52, 55}; +SECT_VEH_CAL_1 const tS16 c_assVTG_RR_LV1_SedanH[13] = { 115, 105, 95, 80, 65, 60, 55, 50, 50, 50, 50, 52, 55}; +SECT_VEH_CAL_1 const tS16 c_assVR_MIN_LV1_SedanH[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_1 const tS16 c_assVR_MAX_LV1_SedanH[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_Y1_LV1_SedanH[7] = { 30, 30, 25, 25, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_Y2_LV1_SedanH[7] = { 15, 13, 10, 8, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_Y3_LV1_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_Y4_LV1_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_X1_LV1_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_X2_LV1_SedanH[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_X3_LV1_SedanH[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_X4_LV1_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assVR_AMB_Y1_LV1_SedanH[7] = { 20, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVR_AMB_Y2_LV1_SedanH[7] = { -15, -15, 15, 15, 15, 15, 15}; +SECT_VEH_CAL_1 const tS16 c_assVR_AMB_X1_LV1_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assVR_AMB_X2_LV1_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assVR_SUN_Y1_LV1_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVR_SUN_Y2_LV1_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVR_SUN_X1_LV1_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assVR_SUN_X2_LV1_SedanH[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_1 const tS16 c_assTG_RL_LV1_SedanH[13] = { 30, 30, 50, 80, 90, 100, 110, 160, 200, 250, 300, 350, 400}; +SECT_VEH_CAL_1 const tS16 c_assTG_RR_LV1_SedanH[13] = { 30, 30, 50, 80, 90, 100, 110, 160, 200, 250, 300, 350, 400}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_MIN_LV1_SedanH[7] = { 20, 20, 20, 20, 50, 50, 50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_MAX_LV1_SedanH[7] = { 400, 400, 450, 500, 600, 600, 600}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_Y1_LV1_SedanH[7] = { -100, -100, -100, -100, -100, -120, -150}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_Y2_LV1_SedanH[7] = { -50, -50, -50, -20, -30, -40, -50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_Y3_LV1_SedanH[7] = { 50, 50, 50, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_Y4_LV1_SedanH[7] = { 200, 200, 200, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_X1_LV1_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_X2_LV1_SedanH[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_X3_LV1_SedanH[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_X4_LV1_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_AMB_Y1_LV1_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_AMB_Y2_LV1_SedanH[7] = { 0, 0, 0, 80, 80, 80, 80}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_AMB_X1_LV1_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_AMB_X2_LV1_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_SUN_Y1_LV1_SedanH[7] = { -15, -15, -15, -5, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_SUN_Y2_LV1_SedanH[7] = { -25, -25, -25, -15, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_SUN_X1_LV1_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_SUN_X2_LV1_SedanH[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_DUCT_TIME_FR_LV1_SedanH[7] = { 600, 600, 600, 600, 600, 600, 600}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_DUCT_TIME_FL_LV1_SedanH[7] = { 600, 600, 600, 600, 600, 600, 600}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_DUCT_RATE_LV1_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_DUCT_MAX_LV1_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_AF_TIME_FR_LV1_SedanH[7] = { 150, 150, 150, 150, 150, 150, 150}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_AF_TIME_FL_LV1_SedanH[7] = { 150, 150, 150, 150, 150, 150, 150}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_AF_RATE_LV1_SedanH[7] = { 2, 2, 2, 2, 2, 2, 2}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_AF_MAX_LV1_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +/* ------------------------------------------Lv1 : End*/ +SECT_VEH_CAL_1 const tS16 c_assINCAR_TG_FL_LV2_SedanH[13] = { 180, 190, 200, 210, 220, 230, 240, 250, 260, 270, 280, 290, 300}; +SECT_VEH_CAL_1 const tS16 c_assINCAR_TG_FR_LV2_SedanH[13] = { 180, 190, 200, 210, 220, 230, 240, 250, 260, 270, 280, 290, 300}; +SECT_VEH_CAL_1 const tS16 c_assVTG_FL_LV2_SedanH[13] = { 80, 70, 60, 58, 55, 55, 55, 55, 55, 58, 63, 70, 75}; +SECT_VEH_CAL_1 const tS16 c_assVTG_FR_LV2_SedanH[13] = { 80, 70, 60, 58, 55, 55, 55, 55, 55, 58, 63, 70, 75}; +SECT_VEH_CAL_1 const tS16 c_assVF_MIN_LV2_SedanH[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_1 const tS16 c_assVF_MAX_LV2_SedanH[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_Y1_LV2_SedanH[7] = { 30, 30, 25, 25, 15, 5, 0}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_Y2_LV2_SedanH[7] = { 10, 7, 5, 5, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_Y3_LV2_SedanH[7] = { 0, 0, 0, 5, 5, 5, 5}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_Y4_LV2_SedanH[7] = { 0, 0, 0, 10, 10, 10, 10}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_X1_LV2_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_X2_LV2_SedanH[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_X3_LV2_SedanH[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_X4_LV2_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assVF_AMB_Y1_LV2_SedanH[7] = { 15, 15, 0, -10, -10, -10, -10}; +SECT_VEH_CAL_1 const tS16 c_assVF_AMB_Y2_LV2_SedanH[7] = { 10, 15, 5, 5, 15, 21, 15}; +SECT_VEH_CAL_1 const tS16 c_assVF_AMB_X1_LV2_SedanH[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_1 const tS16 c_assVF_AMB_X2_LV2_SedanH[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_1 const tS16 c_assVF_SUN_Y1_LV2_SedanH[7] = { 0, 0, 8, 10, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVF_SUN_Y2_LV2_SedanH[7] = { 5, 5, 15, 20, 10, 5, 5}; +SECT_VEH_CAL_1 const tS16 c_assVF_SUN_X1_LV2_SedanH[7] = { 200, 200, 200, 200, 200, 200, 200}; +SECT_VEH_CAL_1 const tS16 c_assVF_SUN_X2_LV2_SedanH[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_1 const tS16 c_assTG_FLU_LV2_SedanH[13] = { 50, 70, 115, 140, 160, 190, 230, 270, 330, 355, 370, 390, 420}; +SECT_VEH_CAL_1 const tS16 c_assTG_FRU_LV2_SedanH[13] = { 50, 70, 115, 140, 160, 190, 230, 270, 330, 355, 370, 390, 420}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_MIN_LV2_SedanH[7] = { 20, 20, 20, 30, 40, 50, 50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_MAX_LV2_SedanH[7] = { 450, 450, 550, 600, 600, 600, 600}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_Y1_LV2_SedanH[7] = { -250, -250, -200, -200, -200, -200, -200}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_Y2_LV2_SedanH[7] = { -70, -60, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_Y3_LV2_SedanH[7] = { 20, 30, 40, 50, 50, 60, 60}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_Y4_LV2_SedanH[7] = { 50, 65, 80, 100, 120, 140, 160}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_X1_LV2_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_X2_LV2_SedanH[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_X3_LV2_SedanH[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_X4_LV2_SedanH[7] = { 150, 150, 150, 150, 150, 150, 150}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_AMB_Y1_LV2_SedanH[7] = { 5, 5, -20, -30, -50, -50, -25}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_AMB_Y2_LV2_SedanH[7] = { 0, 10, 40, 40, 30, 40, 30}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_AMB_X1_LV2_SedanH[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_AMB_X2_LV2_SedanH[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_SUN_Y1_LV2_SedanH[7] = { -10, -20, -20, -30, -30, -30, -30}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_SUN_Y2_LV2_SedanH[7] = { -60, -50, -60, -80, -80, -80, -80}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_SUN_X1_LV2_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_SUN_X2_LV2_SedanH[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_1 const tS16 c_assTG_FLL_LV2_SedanH[13] = { 225, 270, 290, 280, 300, 325, 380, 400, 460, 500, 540, 580, 620}; +SECT_VEH_CAL_1 const tS16 c_assTG_FRL_LV2_SedanH[13] = { 225, 270, 280, 290, 300, 325, 380, 400, 460, 500, 540, 580, 620}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_MIN_LV2_SedanH[7] = { 250, 250, 300, 300, 300, 400, 400}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_MAX_LV2_SedanH[7] = { 450, 450, 500, 800, 800, 800, 800}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_Y1_LV2_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_Y2_LV2_SedanH[7] = { -30, -30, -30, -30, -30, -30, -30}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_Y3_LV2_SedanH[7] = { 30, 40, 50, 50, 60, 80, 80}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_Y4_LV2_SedanH[7] = { 100, 160, 130, 200, 210, 235, 250}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_X1_LV2_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_X2_LV2_SedanH[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_X3_LV2_SedanH[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_X4_LV2_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_AMB_Y1_LV2_SedanH[7] = { -50, -50, -50, -40, -50, -60, -30}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_AMB_Y2_LV2_SedanH[7] = { 40, 50, 50, 20, 40, 50, 60}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_AMB_X1_LV2_SedanH[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_AMB_X2_LV2_SedanH[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_SUN_Y1_LV2_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_SUN_Y2_LV2_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_SUN_X1_LV2_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_SUN_X2_LV2_SedanH[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_1 const tS16 c_assINCAR_TG_RL_LV2_SedanH[13] = { 190, 195, 200, 215, 230, 240, 255, 270, 280, 290, 300, 310, 320}; +SECT_VEH_CAL_1 const tS16 c_assINCAR_TG_RR_LV2_SedanH[13] = { 190, 195, 200, 215, 230, 240, 255, 270, 280, 290, 300, 310, 320}; +SECT_VEH_CAL_1 const tS16 c_assVTG_RL_LV2_SedanH[13] = { 90, 83, 75, 70, 65, 62, 60, 60, 65, 70, 75, 80, 85}; +SECT_VEH_CAL_1 const tS16 c_assVTG_RR_LV2_SedanH[13] = { 90, 83, 75, 70, 65, 62, 60, 60, 65, 70, 75, 80, 85}; +SECT_VEH_CAL_1 const tS16 c_assVR_MIN_LV2_SedanH[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_1 const tS16 c_assVR_MAX_LV2_SedanH[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_Y1_LV2_SedanH[7] = { 30, 30, 30, 30, -10, -20, -20}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_Y2_LV2_SedanH[7] = { 15, 13, 10, 10, -5, -15, -20}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_Y3_LV2_SedanH[7] = { -10, -10, -10, 10, 10, 10, 10}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_Y4_LV2_SedanH[7] = { -30, -30, -30, 30, 30, 30, 30}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_X1_LV2_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_X2_LV2_SedanH[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_X3_LV2_SedanH[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_X4_LV2_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assVR_AMB_Y1_LV2_SedanH[7] = { 10, 5, 10, 5, -5, -20, -20}; +SECT_VEH_CAL_1 const tS16 c_assVR_AMB_Y2_LV2_SedanH[7] = { 10, 5, 0, 0, 5, 10, 5}; +SECT_VEH_CAL_1 const tS16 c_assVR_AMB_X1_LV2_SedanH[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_1 const tS16 c_assVR_AMB_X2_LV2_SedanH[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_1 const tS16 c_assVR_SUN_Y1_LV2_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVR_SUN_Y2_LV2_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVR_SUN_X1_LV2_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assVR_SUN_X2_LV2_SedanH[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_1 const tS16 c_assTG_RL_LV2_SedanH[13] = { 50, 50, 50, 90, 120, 160, 200, 230, 270, 320, 400, 480, 560}; +SECT_VEH_CAL_1 const tS16 c_assTG_RR_LV2_SedanH[13] = { 50, 50, 50, 90, 120, 160, 200, 230, 270, 320, 400, 480, 560}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_MIN_LV2_SedanH[7] = { 20, 20, 20, 20, 380, 400, 400}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_MAX_LV2_SedanH[7] = { 400, 400, 450, 500, 600, 600, 800}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_Y1_LV2_SedanH[7] = { -100, -100, -100, -100, -100, -100, -250}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_Y2_LV2_SedanH[7] = { -40, -40, -40, -30, -50, -80, -100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_Y3_LV2_SedanH[7] = { 50, 50, 50, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_Y4_LV2_SedanH[7] = { 200, 200, 200, 250, 250, 250, 300}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_X1_LV2_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_X2_LV2_SedanH[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_X3_LV2_SedanH[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_X4_LV2_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_AMB_Y1_LV2_SedanH[7] = { -40, -20, -30, -10, 0, -10, -60}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_AMB_Y2_LV2_SedanH[7] = { 0, 0, 0, 0, 30, 25, 20}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_AMB_X1_LV2_SedanH[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_AMB_X2_LV2_SedanH[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_SUN_Y1_LV2_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_SUN_Y2_LV2_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_SUN_X1_LV2_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_SUN_X2_LV2_SedanH[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_DUCT_TIME_FR_LV2_SedanH[7] = { 3600, 3600, 3600, 3600, 3600, 3600, 3600}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_DUCT_TIME_FL_LV2_SedanH[7] = { 3600, 3600, 3600, 3600, 3600, 3600, 3600}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_DUCT_RATE_LV2_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_DUCT_MAX_LV2_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_AF_TIME_FR_LV2_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_AF_TIME_FL_LV2_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_AF_RATE_LV2_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_AF_MAX_LV2_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +/* ------------------------------------------Lv2 : End*/ +SECT_VEH_CAL_1 const tS16 c_assINCAR_TG_FL_LV3_SedanH[13] = { 180, 190, 200, 210, 230, 245, 255, 265, 270, 280, 290, 300, 310}; +SECT_VEH_CAL_1 const tS16 c_assINCAR_TG_FR_LV3_SedanH[13] = { 180, 190, 200, 210, 230, 245, 255, 265, 270, 280, 290, 300, 310}; +SECT_VEH_CAL_1 const tS16 c_assVTG_FL_LV3_SedanH[13] = { 90, 83, 75, 68, 60, 60, 60, 65, 70, 73, 86, 88, 90}; +SECT_VEH_CAL_1 const tS16 c_assVTG_FR_LV3_SedanH[13] = { 90, 83, 75, 68, 60, 60, 60, 65, 70, 73, 86, 88, 90}; +SECT_VEH_CAL_1 const tS16 c_assVF_MIN_LV3_SedanH[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_1 const tS16 c_assVF_MAX_LV3_SedanH[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_Y1_LV3_SedanH[7] = { 15, 15, 25, 25, 15, -30, -60}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_Y2_LV3_SedanH[7] = { 5, 5, 5, 5, 0, -10, -40}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_Y3_LV3_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_Y4_LV3_SedanH[7] = { 0, 0, 0, 5, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_X1_LV3_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_X2_LV3_SedanH[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_X3_LV3_SedanH[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_X4_LV3_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assVF_AMB_Y1_LV3_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVF_AMB_Y2_LV3_SedanH[7] = { -15, -6, 8, 8, 3, -6, -8}; +SECT_VEH_CAL_1 const tS16 c_assVF_AMB_X1_LV3_SedanH[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_1 const tS16 c_assVF_AMB_X2_LV3_SedanH[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_1 const tS16 c_assVF_SUN_Y1_LV3_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVF_SUN_Y2_LV3_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVF_SUN_X1_LV3_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assVF_SUN_X2_LV3_SedanH[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_1 const tS16 c_assTG_FLU_LV3_SedanH[13] = { 50, 90, 140, 200, 250, 285, 320, 350, 400, 435, 460, 470, 480}; +SECT_VEH_CAL_1 const tS16 c_assTG_FRU_LV3_SedanH[13] = { 50, 90, 140, 200, 250, 285, 320, 350, 400, 435, 460, 470, 480}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_MIN_LV3_SedanH[7] = { 20, 20, 20, 30, 200, 200, 250}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_MAX_LV3_SedanH[7] = { 450, 450, 550, 800, 800, 750, 700}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_Y1_LV3_SedanH[7] = { -100, -100, -100, -150, -200, -250, -300}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_Y2_LV3_SedanH[7] = { -30, -30, -50, -50, -50, -50, -100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_Y3_LV3_SedanH[7] = { 50, 50, 40, 70, 50, 30, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_Y4_LV3_SedanH[7] = { 100, 100, 100, 100, 80, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_X1_LV3_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_X2_LV3_SedanH[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_X3_LV3_SedanH[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_X4_LV3_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_AMB_Y1_LV3_SedanH[7] = { 0, -15, -50, -50, -40, -50, -30}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_AMB_Y2_LV3_SedanH[7] = { 70, 30, 5, 10, 0, -40, -45}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_AMB_X1_LV3_SedanH[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_AMB_X2_LV3_SedanH[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_SUN_Y1_LV3_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_SUN_Y2_LV3_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_SUN_X1_LV3_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_SUN_X2_LV3_SedanH[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_1 const tS16 c_assTG_FLL_LV3_SedanH[13] = { 380, 430, 480, 480, 480, 480, 500, 550, 600, 650, 700, 750, 800}; +SECT_VEH_CAL_1 const tS16 c_assTG_FRL_LV3_SedanH[13] = { 380, 430, 480, 480, 480, 480, 500, 550, 600, 650, 700, 750, 800}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_MIN_LV3_SedanH[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_MAX_LV3_SedanH[7] = { 600, 600, 800, 800, 800, 800, 950}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_Y1_LV3_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_Y2_LV3_SedanH[7] = { -50, -50, -30, -30, -50, -50, -50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_Y3_LV3_SedanH[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_Y4_LV3_SedanH[7] = { 250, 300, 160, 200, 400, 400, 400}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_X1_LV3_SedanH[7] = { -100, -100, -100, -100, -120, -130, -150}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_X2_LV3_SedanH[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_X3_LV3_SedanH[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_X4_LV3_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_AMB_Y1_LV3_SedanH[7] = { -30, -60, -50, -20, -30, -50, -70}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_AMB_Y2_LV3_SedanH[7] = { 0, 10, 50, 50, 30, 20, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_AMB_X1_LV3_SedanH[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_AMB_X2_LV3_SedanH[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_SUN_Y1_LV3_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_SUN_Y2_LV3_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_SUN_X1_LV3_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_SUN_X2_LV3_SedanH[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_1 const tS16 c_assINCAR_TG_RL_LV3_SedanH[13] = { 190, 195, 200, 215, 230, 235, 240, 255, 270, 280, 290, 300, 310}; +SECT_VEH_CAL_1 const tS16 c_assINCAR_TG_RR_LV3_SedanH[13] = { 190, 195, 200, 215, 230, 235, 240, 255, 270, 280, 290, 300, 310}; +SECT_VEH_CAL_1 const tS16 c_assVTG_RL_LV3_SedanH[13] = { 110, 100, 90, 80, 70, 60, 55, 65, 80, 85, 90, 90, 90}; +SECT_VEH_CAL_1 const tS16 c_assVTG_RR_LV3_SedanH[13] = { 110, 100, 90, 80, 70, 60, 55, 65, 80, 85, 90, 90, 90}; +SECT_VEH_CAL_1 const tS16 c_assVR_MIN_LV3_SedanH[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_1 const tS16 c_assVR_MAX_LV3_SedanH[7] = { 130, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_Y1_LV3_SedanH[7] = { 40, 40, 40, 40, -30, -40, -40}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_Y2_LV3_SedanH[7] = { 25, 25, 25, 10, 0, -20, -20}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_Y3_LV3_SedanH[7] = { 10, 10, 10, 5, 0, 20, 25}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_Y4_LV3_SedanH[7] = { 20, 20, 20, 30, 50, 50, 50}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_X1_LV3_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_X2_LV3_SedanH[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_X3_LV3_SedanH[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_X4_LV3_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assVR_AMB_Y1_LV3_SedanH[7] = { -10, -10, -5, 5, -10, -5, 0}; +SECT_VEH_CAL_1 const tS16 c_assVR_AMB_Y2_LV3_SedanH[7] = { 5, 10, 15, 15, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVR_AMB_X1_LV3_SedanH[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_1 const tS16 c_assVR_AMB_X2_LV3_SedanH[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_1 const tS16 c_assVR_SUN_Y1_LV3_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVR_SUN_Y2_LV3_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVR_SUN_X1_LV3_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assVR_SUN_X2_LV3_SedanH[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_1 const tS16 c_assTG_RL_LV3_SedanH[13] = { 50, 50, 50, 80, 120, 150, 190, 250, 320, 370, 450, 500, 600}; +SECT_VEH_CAL_1 const tS16 c_assTG_RR_LV3_SedanH[13] = { 50, 50, 50, 80, 120, 150, 190, 250, 320, 370, 450, 500, 600}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_MIN_LV3_SedanH[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_MAX_LV3_SedanH[7] = { 400, 400, 450, 650, 800, 800, 800}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_Y1_LV3_SedanH[7] = { -100, -100, -100, -100, -100, -100, -250}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_Y2_LV3_SedanH[7] = { -50, -50, -50, -50, -50, -80, -100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_Y3_LV3_SedanH[7] = { 50, 50, 50, 50, 80, 80, 80}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_Y4_LV3_SedanH[7] = { 150, 150, 175, 200, 250, 450, 450}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_X1_LV3_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_X2_LV3_SedanH[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_X3_LV3_SedanH[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_X4_LV3_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_AMB_Y1_LV3_SedanH[7] = { 0, 0, 0, 0, -20, -25, -20}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_AMB_Y2_LV3_SedanH[7] = { 0, 0, 30, 40, 10, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_AMB_X1_LV3_SedanH[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_AMB_X2_LV3_SedanH[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_SUN_Y1_LV3_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_SUN_Y2_LV3_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_SUN_X1_LV3_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_SUN_X2_LV3_SedanH[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_DUCT_TIME_FR_LV3_SedanH[7] = { 3600, 3600, 3600, 3600, 3600, 3600, 3600}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_DUCT_TIME_FL_LV3_SedanH[7] = { 3600, 3600, 3600, 3600, 3600, 3600, 3600}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_DUCT_RATE_LV3_SedanH[7] = { 5, 5, 5, 1, 1, 1, 1}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_DUCT_MAX_LV3_SedanH[7] = { 800, 800, 800, 800, 700, 600, 500}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_AF_TIME_FR_LV3_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_AF_TIME_FL_LV3_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_AF_RATE_LV3_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_AF_MAX_LV3_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +/* ------------------------------------------Lv3 : End*/ +SECT_VEH_CAL_1 const tS16 c_assINCAR_TG_FL_LV4_SedanH[13] = { 160, 180, 200, 220, 230, 240, 250, 260, 270, 280, 290, 295, 300}; +SECT_VEH_CAL_1 const tS16 c_assINCAR_TG_FR_LV4_SedanH[13] = { 160, 180, 200, 220, 230, 240, 250, 260, 270, 280, 290, 295, 300}; +SECT_VEH_CAL_1 const tS16 c_assVTG_FL_LV4_SedanH[13] = { 60, 60, 62, 70, 75, 75, 75, 70, 75, 75, 75, 75, 75}; +SECT_VEH_CAL_1 const tS16 c_assVTG_FR_LV4_SedanH[13] = { 60, 60, 62, 70, 75, 75, 75, 75, 75, 75, 75, 75, 75}; +SECT_VEH_CAL_1 const tS16 c_assVF_MIN_LV4_SedanH[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_1 const tS16 c_assVF_MAX_LV4_SedanH[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_Y1_LV4_SedanH[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_Y2_LV4_SedanH[7] = { 7, 7, 7, 7, 7, 7, 7}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_Y3_LV4_SedanH[7] = { 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_Y4_LV4_SedanH[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_X1_LV4_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_X2_LV4_SedanH[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_X3_LV4_SedanH[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_X4_LV4_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assVF_AMB_Y1_LV4_SedanH[7] = { 15, 7, -7, -7, -2, 5, 7}; +SECT_VEH_CAL_1 const tS16 c_assVF_AMB_Y2_LV4_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVF_AMB_X1_LV4_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assVF_AMB_X2_LV4_SedanH[7] = { 150, 150, 150, 150, 150, 150, 150}; +SECT_VEH_CAL_1 const tS16 c_assVF_SUN_Y1_LV4_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVF_SUN_Y2_LV4_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVF_SUN_X1_LV4_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assVF_SUN_X2_LV4_SedanH[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_1 const tS16 c_assTG_FLU_LV4_SedanH[13] = { 150, 180, 200, 230, 260, 295, 335, 355, 365, 370, 380, 380, 390}; +SECT_VEH_CAL_1 const tS16 c_assTG_FRU_LV4_SedanH[13] = { 150, 180, 200, 230, 250, 270, 290, 310, 330, 350, 370, 380, 390}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_MIN_LV4_SedanH[7] = { 20, 20, 20, 30, 200, 200, 250}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_MAX_LV4_SedanH[7] = { 450, 450, 550, 800, 800, 800, 800}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_Y1_LV4_SedanH[7] = { -150, -150, -150, -150, -150, -150, -150}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_Y2_LV4_SedanH[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_Y3_LV4_SedanH[7] = { 60, 60, 60, 60, 60, 60, 60}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_Y4_LV4_SedanH[7] = { 50, 50, 70, 100, 100, 120, 150}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_X1_LV4_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_X2_LV4_SedanH[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_X3_LV4_SedanH[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_X4_LV4_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_AMB_Y1_LV4_SedanH[7] = { -30, -30, -5, -5, 35, 40, 45}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_AMB_Y2_LV4_SedanH[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_AMB_X1_LV4_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_AMB_X2_LV4_SedanH[7] = { 150, 150, 150, 150, 150, 150, 150}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_SUN_Y1_LV4_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_SUN_Y2_LV4_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_SUN_X1_LV4_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_SUN_X2_LV4_SedanH[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_1 const tS16 c_assTG_FLL_LV4_SedanH[13] = { 350, 400, 440, 480, 520, 560, 600, 630, 660, 700, 740, 750, 800}; +SECT_VEH_CAL_1 const tS16 c_assTG_FRL_LV4_SedanH[13] = { 350, 400, 440, 480, 520, 560, 600, 630, 660, 700, 740, 750, 800}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_MIN_LV4_SedanH[7] = { 300, 300, 300, 300, 300, 300, 400}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_MAX_LV4_SedanH[7] = { 600, 600, 800, 800, 800, 900, 900}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_Y1_LV4_SedanH[7] = { -100, -100, -100, -50, -60, -150, -200}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_Y2_LV4_SedanH[7] = { -50, -50, -50, -20, -20, -50, -80}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_Y3_LV4_SedanH[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_Y4_LV4_SedanH[7] = { 200, 200, 200, 200, 200, 200, 200}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_X1_LV4_SedanH[7] = { -100, -100, -100, -100, -100, -200, -150}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_X2_LV4_SedanH[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_X3_LV4_SedanH[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_X4_LV4_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_AMB_Y1_LV4_SedanH[7] = { 0, 0, -20, -50, -30, -20, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_AMB_Y2_LV4_SedanH[7] = { 50, 50, 50, 50, 60, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_AMB_X1_LV4_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_AMB_X2_LV4_SedanH[7] = { 150, 150, 150, 150, 150, 150, 150}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_SUN_Y1_LV4_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_SUN_Y2_LV4_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_SUN_X1_LV4_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_SUN_X2_LV4_SedanH[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_1 const tS16 c_assINCAR_TG_RL_LV4_SedanH[13] = { 150, 155, 160, 170, 180, 195, 205, 215, 230, 240, 250, 280, 300}; +SECT_VEH_CAL_1 const tS16 c_assINCAR_TG_RR_LV4_SedanH[13] = { 140, 145, 150, 160, 170, 185, 195, 205, 220, 230, 240, 270, 290}; +SECT_VEH_CAL_1 const tS16 c_assVTG_RL_LV4_SedanH[13] = { 120, 115, 110, 100, 95, 90, 90, 90, 90, 90, 90, 90, 90}; +SECT_VEH_CAL_1 const tS16 c_assVTG_RR_LV4_SedanH[13] = { 120, 115, 110, 100, 95, 90, 90, 90, 90, 90, 90, 90, 90}; +SECT_VEH_CAL_1 const tS16 c_assVR_MIN_LV4_SedanH[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_1 const tS16 c_assVR_MAX_LV4_SedanH[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_Y1_LV4_SedanH[7] = { 30, 30, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_Y2_LV4_SedanH[7] = { 15, 15, 25, 25, 25, 25, 25}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_Y3_LV4_SedanH[7] = { 15, 15, 20, 25, 25, 25, 25}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_Y4_LV4_SedanH[7] = { 20, 30, 40, 40, 40, 45, 60}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_X1_LV4_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_X2_LV4_SedanH[7] = { -30, -30, -30, -30, -30, -30, -30}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_X3_LV4_SedanH[7] = { 30, 30, 30, 30, 30, 30, 30}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_X4_LV4_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assVR_AMB_Y1_LV4_SedanH[7] = { -5, -10, -5, -10, -10, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVR_AMB_Y2_LV4_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVR_AMB_X1_LV4_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assVR_AMB_X2_LV4_SedanH[7] = { 150, 150, 150, 150, 150, 150, 150}; +SECT_VEH_CAL_1 const tS16 c_assVR_SUN_Y1_LV4_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVR_SUN_Y2_LV4_SedanH[7] = { 15, 12, 10, 8, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVR_SUN_X1_LV4_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assVR_SUN_X2_LV4_SedanH[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_1 const tS16 c_assTG_RL_LV4_SedanH[13] = { 50, 50, 50, 110, 180, 220, 260, 310, 360, 390, 430, 480, 560}; +SECT_VEH_CAL_1 const tS16 c_assTG_RR_LV4_SedanH[13] = { 50, 50, 50, 110, 180, 220, 260, 310, 360, 390, 430, 480, 560}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_MIN_LV4_SedanH[7] = { 50, 50, 50, 50, 350, 450, 600}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_MAX_LV4_SedanH[7] = { 100, 400, 450, 650, 800, 800, 800}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_Y1_LV4_SedanH[7] = { -60, -60, -80, -80, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_Y2_LV4_SedanH[7] = { -30, -30, -30, -30, -40, -40, -40}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_Y3_LV4_SedanH[7] = { 10, 30, 45, 80, 80, 80, 80}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_Y4_LV4_SedanH[7] = { 40, 80, 150, 400, 400, 400, 400}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_X1_LV4_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_X2_LV4_SedanH[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_X3_LV4_SedanH[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_X4_LV4_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_AMB_Y1_LV4_SedanH[7] = { 0, 0, -30, -30, -10, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_AMB_Y2_LV4_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_AMB_X1_LV4_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_AMB_X2_LV4_SedanH[7] = { 150, 150, 150, 150, 150, 150, 150}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_SUN_Y1_LV4_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_SUN_Y2_LV4_SedanH[7] = { -25, -20, -30, -15, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_SUN_X1_LV4_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_SUN_X2_LV4_SedanH[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_DUCT_TIME_FR_LV4_SedanH[7] = { 1800, 1800, 1800, 1800, 1800, 1800, 1800}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_DUCT_TIME_FL_LV4_SedanH[7] = { 1800, 1800, 1800, 1800, 1800, 1800, 1800}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_DUCT_RATE_LV4_SedanH[7] = { 5, 5, 5, 1, 1, 1, 1}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_DUCT_MAX_LV4_SedanH[7] = { 500, 500, 500, 800, 700, 600, 500}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_AF_TIME_FR_LV4_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_AF_TIME_FL_LV4_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_AF_RATE_LV4_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_AF_MAX_LV4_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +/* ------------------------------------------Lv4 : End*/ +SECT_VEH_CAL_1 const tS16 c_assINCAR_TG_FL_LV5_SedanH[13] = { 180, 190, 200, 210, 230, 235, 240, 250, 270, 290, 310, 330, 350}; +SECT_VEH_CAL_1 const tS16 c_assINCAR_TG_FR_LV5_SedanH[13] = { 180, 190, 200, 210, 230, 235, 240, 250, 270, 290, 310, 330, 350}; +SECT_VEH_CAL_1 const tS16 c_assVTG_FL_LV5_SedanH[13] = { 90, 83, 75, 62, 55, 55, 70, 70, 75, 78, 91, 93, 95}; +SECT_VEH_CAL_1 const tS16 c_assVTG_FR_LV5_SedanH[13] = { 90, 83, 75, 62, 55, 55, 70, 70, 75, 78, 91, 93, 95}; +SECT_VEH_CAL_1 const tS16 c_assVF_MIN_LV5_SedanH[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_1 const tS16 c_assVF_MAX_LV5_SedanH[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_Y1_LV5_SedanH[7] = { 15, 15, 25, 25, 0, -15, -20}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_Y2_LV5_SedanH[7] = { 5, 10, 15, 0, 0, -10, -15}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_Y3_LV5_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_Y4_LV5_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_X1_LV5_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_X2_LV5_SedanH[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_X3_LV5_SedanH[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_1 const tS16 c_assVF_INC_X4_LV5_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assVF_AMB_Y1_LV5_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVF_AMB_Y2_LV5_SedanH[7] = { 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_1 const tS16 c_assVF_AMB_X1_LV5_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assVF_AMB_X2_LV5_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assVF_SUN_Y1_LV5_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVF_SUN_Y2_LV5_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVF_SUN_X1_LV5_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assVF_SUN_X2_LV5_SedanH[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_1 const tS16 c_assTG_FLU_LV5_SedanH[13] = { 50, 70, 150, 220, 250, 350, 420, 450, 480, 500, 525, 550, 600}; +SECT_VEH_CAL_1 const tS16 c_assTG_FRU_LV5_SedanH[13] = { 50, 70, 150, 220, 250, 350, 420, 450, 480, 500, 525, 550, 600}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_MIN_LV5_SedanH[7] = { 20, 20, 20, 30, 200, 200, 250}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_MAX_LV5_SedanH[7] = { 450, 450, 550, 800, 800, 800, 800}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_Y1_LV5_SedanH[7] = { -100, -100, -150, -180, -200, -300, -350}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_Y2_LV5_SedanH[7] = { -30, -30, -70, -80, -65, -65, -65}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_Y3_LV5_SedanH[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_Y4_LV5_SedanH[7] = { 200, 200, 200, 100, 70, 60, 50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_X1_LV5_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_X2_LV5_SedanH[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_X3_LV5_SedanH[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_INC_X4_LV5_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_AMB_Y1_LV5_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_AMB_Y2_LV5_SedanH[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_AMB_X1_LV5_SedanH[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_AMB_X2_LV5_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_SUN_Y1_LV5_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_SUN_Y2_LV5_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_SUN_X1_LV5_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FU_SUN_X2_LV5_SedanH[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_1 const tS16 c_assTG_FLL_LV5_SedanH[13] = { 400, 450, 480, 500, 580, 625, 720, 750, 750, 750, 800, 850, 900}; +SECT_VEH_CAL_1 const tS16 c_assTG_FRL_LV5_SedanH[13] = { 400, 450, 480, 500, 580, 625, 720, 750, 750, 750, 800, 850, 900}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_MIN_LV5_SedanH[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_MAX_LV5_SedanH[7] = { 600, 600, 800, 800, 800, 800, 800}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_Y1_LV5_SedanH[7] = { -100, -100, -100, -50, -60, -150, -200}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_Y2_LV5_SedanH[7] = { -50, -50, -50, -20, -20, -50, -80}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_Y3_LV5_SedanH[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_Y4_LV5_SedanH[7] = { 400, 400, 400, 400, 200, 200, 200}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_X1_LV5_SedanH[7] = { -100, -100, -100, -100, -100, -200, -150}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_X2_LV5_SedanH[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_X3_LV5_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_INC_X4_LV5_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_AMB_Y1_LV5_SedanH[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_AMB_Y2_LV5_SedanH[7] = { 50, 50, 50, 50, 60, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_AMB_X1_LV5_SedanH[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_AMB_X2_LV5_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_SUN_Y1_LV5_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_SUN_Y2_LV5_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_SUN_X1_LV5_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assDTG_FL_SUN_X2_LV5_SedanH[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_1 const tS16 c_assINCAR_TG_RL_LV5_SedanH[13] = { 190, 195, 200, 215, 230, 235, 240, 260, 270, 285, 300, 310, 320}; +SECT_VEH_CAL_1 const tS16 c_assINCAR_TG_RR_LV5_SedanH[13] = { 190, 195, 200, 215, 230, 235, 240, 260, 270, 285, 300, 310, 320}; +SECT_VEH_CAL_1 const tS16 c_assVTG_RL_LV5_SedanH[13] = { 110, 100, 90, 80, 70, 65, 65, 65, 80, 90, 80, 90, 90}; +SECT_VEH_CAL_1 const tS16 c_assVTG_RR_LV5_SedanH[13] = { 110, 100, 90, 80, 70, 65, 65, 65, 80, 90, 80, 90, 90}; +SECT_VEH_CAL_1 const tS16 c_assVR_MIN_LV5_SedanH[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_1 const tS16 c_assVR_MAX_LV5_SedanH[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_Y1_LV5_SedanH[7] = { 80, 80, 80, 60, 60, 60, 60}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_Y2_LV5_SedanH[7] = { 25, 25, 25, 30, 10, 10, 10}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_Y3_LV5_SedanH[7] = { -10, -10, -10, 0, 0, 20, 25}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_Y4_LV5_SedanH[7] = { 20, 20, 20, 30, 50, 50, 50}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_X1_LV5_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_X2_LV5_SedanH[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_X3_LV5_SedanH[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_1 const tS16 c_assVR_INC_X4_LV5_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assVR_AMB_Y1_LV5_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVR_AMB_Y2_LV5_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVR_AMB_X1_LV5_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assVR_AMB_X2_LV5_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assVR_SUN_Y1_LV5_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVR_SUN_Y2_LV5_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assVR_SUN_X1_LV5_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assVR_SUN_X2_LV5_SedanH[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_1 const tS16 c_assTG_RL_LV5_SedanH[13] = { 50, 50, 50, 80, 120, 150, 170, 250, 350, 370, 450, 500, 500}; +SECT_VEH_CAL_1 const tS16 c_assTG_RR_LV5_SedanH[13] = { 50, 50, 50, 80, 120, 150, 170, 250, 350, 370, 450, 500, 500}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_MIN_LV5_SedanH[7] = { 51, 51, 51, 51, 51, 51, 51}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_MAX_LV5_SedanH[7] = { 400, 400, 450, 650, 800, 800, 800}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_Y1_LV5_SedanH[7] = { -100, -100, -100, -100, -100, -100, -250}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_Y2_LV5_SedanH[7] = { -50, -50, -50, -50, -50, -80, -100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_Y3_LV5_SedanH[7] = { 50, 50, 50, 50, 80, 80, 80}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_Y4_LV5_SedanH[7] = { 250, 250, 250, 350, 450, 450, 450}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_X1_LV5_SedanH[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_X2_LV5_SedanH[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_X3_LV5_SedanH[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_INC_X4_LV5_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_AMB_Y1_LV5_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_AMB_Y2_LV5_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_AMB_X1_LV5_SedanH[7] = { -10, -10, -10, -10, -10, -10, -10}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_AMB_X2_LV5_SedanH[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_SUN_Y1_LV5_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_SUN_Y2_LV5_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_SUN_X1_LV5_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assDTG_R_SUN_X2_LV5_SedanH[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_DUCT_TIME_FR_LV5_SedanH[7] = { 3600, 3600, 3600, 3600, 3600, 3600, 3600}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_DUCT_TIME_FL_LV5_SedanH[7] = { 3600, 3600, 3600, 3600, 3600, 3600, 3600}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_DUCT_RATE_LV5_SedanH[7] = { 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_DUCT_MAX_LV5_SedanH[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_AF_TIME_FR_LV5_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_AF_TIME_FL_LV5_SedanH[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_AF_RATE_LV5_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assCORRECT_AF_MAX_LV5_SedanH[7] = { 0, 0, 0, 0, 0, 0, 0}; +/* ------------------------------------------Lv5 : End*/ +SECT_VEH_CAL_1 const tS16 c_assDUCT_TGT_DEF_VALVE_L_SedanH[11] = { 220, 200, 180, 150, 110, 80, 80, 80, 50, 50, 50}; +SECT_VEH_CAL_1 const tS16 c_assDUCT_TGT_DEF_VALVE_R_SedanH[11] = { 220, 220, 180, 150, 110, 80, 80, 80, 50, 50, 50}; +/* ------------------------------------------DuctTgt Increase : End*/ +SECT_VEH_CAL_1 const tS16 c_assAMB_LV_UP_SedanH[5] = { 650, 200, 50, -100, -500}; +SECT_VEH_CAL_1 const tS16 c_assAMB_LV_DN_SedanH[5] = { 700, 250, 100, -50, -450}; +SECT_VEH_CAL_1 const tS16 c_assAMB_LV_TG_SedanH[6] = { 600, 350, 150, 0, -200, -350}; +/* ------------------------------------------Ambient LEVEL : End*/ +SECT_VEH_CAL_1 const tU08 c_aucMODE_BY_SET_F_LV0_SedanH[13] = { 30, 30, 30, 30, 20, 20, 20, 20, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_1 const tU08 c_aucMODE_BY_SET_F_LV1_SedanH[13] = { 30, 30, 30, 30, 30, 30, 30, 30, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_1 const tU08 c_aucMODE_BY_SET_F_LV2_SedanH[13] = { 20, 20, 20, 20, 20, 20, 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_1 const tU08 c_aucMODE_BY_SET_F_LV3_SedanH[13] = { 20, 20, 20, 20, 20, 20, 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_1 const tU08 c_aucMODE_BY_SET_F_LV4_SedanH[13] = { 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_1 const tU08 c_aucMODE_BY_SET_F_LV5_SedanH[13] = { 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_1 const tU16 c_ausMODE_BY_DUCT_TG_R_LV0_SedanH[7] = { 250, 300, 450, 550, 120, 150, 180}; +SECT_VEH_CAL_1 const tU16 c_ausMODE_BY_DUCT_TG_R_LV1_SedanH[7] = { 250, 300, 450, 550, 120, 150, 180}; +SECT_VEH_CAL_1 const tU16 c_ausMODE_BY_DUCT_TG_R_LV2_SedanH[7] = { 250, 300, 450, 550, 120, 150, 180}; +SECT_VEH_CAL_1 const tU16 c_ausMODE_BY_DUCT_TG_R_LV3_SedanH[7] = { 300, 350, 450, 550, 120, 150, 180}; +SECT_VEH_CAL_1 const tU16 c_ausMODE_BY_DUCT_TG_R_LV4_SedanH[7] = { 350, 400, 500, 550, 120, 150, 180}; +SECT_VEH_CAL_1 const tU16 c_ausMODE_BY_DUCT_TG_R_LV5_SedanH[7] = { 300, 350, 450, 550, 120, 150, 180}; +/* ------------------------------------------Mode depend on SET for each level : End*/ +SECT_VEH_CAL_1 const tS16 c_ssPREC_REC_ON_AMB_SedanH = 300; +SECT_VEH_CAL_1 const tS16 c_ssPREC_REC_OFF_AMB_SedanH = 260; +SECT_VEH_CAL_1 const tU08 c_aucPREC_VEH_SPD_OSA_SedanH[13] = { 100, 95, 92, 86, 83, 80, 75, 70, 65, 60, 55, 52, 50}; +SECT_VEH_CAL_1 const tS16 c_assPRE_AMB_RANGE_WINTER_SedanH[7] = { -450, -300, -200, -150, -80, 0, 50}; +SECT_VEH_CAL_1 const tU08 c_aucPREC_OSA_WINTER_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tU08 c_aucPREC_REC_WINTER_SedanH[7] = { 15, 13, 10, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tU16 c_ausPREC_HUMIDITY_NOK_SedanH[7] = { 900, 900, 900, 900, 900, 900, 900}; +SECT_VEH_CAL_1 const tU16 c_ausPREC_HUMIDITY_OK_SedanH[7] = { 700, 700, 700, 700, 700, 700, 700}; +SECT_VEH_CAL_1 const tU16 c_ausPREC_ENTRY_RPM_SedanH[3] = { 450, 550, 800}; +SECT_VEH_CAL_1 const tU16 c_ausPREC_EXIT_RPM_SedanH[3] = { 350, 450, 700}; +SECT_VEH_CAL_1 const tU16 c_ausPREC_COMP_SPD_1_SedanH[3] = { 450, 500, 550}; +SECT_VEH_CAL_1 const tU08 c_aucPREC_OSA_SUMMER_1_SedanH[3] = { 80, 60, 45}; +SECT_VEH_CAL_1 const tU08 c_aucPREC_REC_SUMMER_1_SedanH[3] = { 20, 40, 60}; +SECT_VEH_CAL_1 const tS16 c_assPREC_EVA_DIFF_FB_TG_F_SedanH[7] = { 0, 5, 10, 15, 20, 25, 30}; +SECT_VEH_CAL_1 const tU08 c_aucPREC_OSA_SUMMER_2_SedanH[7] = { 50, 45, 40, 35, 30, 25, 20}; +SECT_VEH_CAL_1 const tU08 c_aucPREC_REC_SUMMER_2_SedanH[7] = { 50, 55, 60, 65, 70, 75, 80}; +SECT_VEH_CAL_1 const tU08 c_aucPREC_EVA_DIFF_SedanH[4] = { 80, 80, 50, 50}; +SECT_VEH_CAL_1 const tU08 c_ucPREC_OSA_SUMMER_3_SedanH = 0; +SECT_VEH_CAL_1 const tU08 c_ucPREC_REC_SUMMER_3_SedanH = 100; +/* ------------------------------------------AutoRec : End*/ +SECT_VEH_CAL_1 const tU16 c_ausFLOW_FR_VE2VALVE_SedanH[9] = { 100, 100, 100, 100, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tU16 c_ausFLOW_FR_BIVALVE_SedanH[9] = { 40, 40, 40, 40, 30, 0, 30, 0, 0}; +SECT_VEH_CAL_1 const tU16 c_ausFLOW_FR_BI2VALVE_SedanH[9] = { 70, 70, 70, 70, 30, 0, 30, 0, 0}; +SECT_VEH_CAL_1 const tU16 c_ausFLOW_FR_AF2VALVE_SedanH[9] = { 35, 25, 25, 35, 30, 0, 30, 0, 0}; +SECT_VEH_CAL_1 const tU16 c_ausFLOW_FR_AF2VALVE_SUMMER_SedanH[9] = { 25, 25, 25, 25, 30, 0, 30, 0, 10}; +SECT_VEH_CAL_1 const tU16 c_ausFLOW_FR_FO2VALVE_SedanH[9] = { 0, 0, 0, 0, 100, 0, 100, 0, 0}; +SECT_VEH_CAL_1 const tU16 c_ausFLOW_FR_FD2VALVE_SedanH[9] = { 0, 0, 0, 0, 100, 0, 100, 0, 100}; +SECT_VEH_CAL_1 const tU16 c_ausFLOW_FR_DE2VALVE_SedanH[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 100}; +SECT_VEH_CAL_1 const tU16 c_ausFLOW_FR_TR2VALVE_SedanH[9] = { 55, 55, 55, 55, 100, 0, 100, 0, 100}; +SECT_VEH_CAL_1 const tU16 c_ausFLOW_FR_HI2VALVE_SedanH[9] = { 50, 50, 50, 50, 0, 0, 0, 0, 100}; +SECT_VEH_CAL_1 const tU16 c_ausFLOW_FR_BIVALVE_MANUAL_SedanH[9] = { 50, 50, 50, 50, 60, 0, 60, 0, 0}; +SECT_VEH_CAL_1 const tU16 c_ausFLOW_RE_VENT_SedanH[6] = { 70, 80, 80, 70, 0, 0}; +SECT_VEH_CAL_1 const tU16 c_ausFLOW_RE_BI2VALVE_SedanH[6] = { 70, 80, 80, 70, 100, 100}; +SECT_VEH_CAL_1 const tU16 c_ausFLOW_RE_FO2VALVE_SedanH[6] = { 0, 20, 20, 0, 100, 100}; +SECT_VEH_CAL_1 const tU16 c_ausFLOW_RE_VENT_2_SedanH[6] = { 30, 60, 60, 30, 50, 50}; +SECT_VEH_CAL_1 const tU16 c_ausFLOW_RE_BI2VALVE_2_SedanH[6] = { 50, 30, 30, 50, 100, 100}; +SECT_VEH_CAL_1 const tU16 c_ausFLOW_RE_VENT_3_SedanH[6] = { 70, 80, 80, 70, 0, 0}; +SECT_VEH_CAL_1 const tU16 c_ausFLOW_RE_BI2VALVE_3_SedanH[6] = { 25, 25, 25, 25, 100, 100}; +SECT_VEH_CAL_1 const tU16 c_ausFLOW_RE_VENT_MANUAL_SedanH[6] = { 70, 80, 80, 70, 0, 0}; +SECT_VEH_CAL_1 const tU16 c_ausFLOW_RE_BI2VALVE_MANUAL_SedanH[6] = { 70, 40, 40, 70, 100, 100}; +/* ------------------------------------------Flow Control Valve: End*/ +SECT_VEH_CAL_1 const tS16 c_assFLOW_BI_AMB_TGT_SedanH[6] = { 450, 350, 150, 0, -150, -350}; +SECT_VEH_CAL_1 const tU08 c_aucFLOW_BI_VENT_PLUS_SedanH[12] = { 10, 10, 10, 0, 0, 0, 10, 10, 10, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assFLOW_BI_TEMP_TGT_SedanH[12] = { 300, 350, 400, 450, 500, 550, 300, 350, 400, 450, 500, 550}; +SECT_VEH_CAL_1 const tU08 c_aucFLOW_BI_FOOT_PLUS_SedanH[12] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_1 const tU08 c_aucFLOW_BI_VENT_VALVE_MAX_SedanH[12] = { 85, 85, 85, 85, 85, 85, 60, 60, 60, 60, 60, 60}; +SECT_VEH_CAL_1 const tU08 c_aucFLOW_BI_FOOT_VALVE_MAX_SedanH[12] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tU08 c_aucFLOW_BI_VENT_VALVE_MIN_SedanH[12] = { 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_1 const tU08 c_aucFLOW_BI_FOOT_VALVE_MIN_SedanH[12] = { 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}; +/* ------------------------------------------Bi 2 level conditions: End*/ +SECT_VEH_CAL_1 const tS16 c_assFLOW_B2I_AMB_TGT_SedanH[6] = { 450, 350, 100, 0, -150, -350}; +SECT_VEH_CAL_1 const tU08 c_aucFLOW_BI2_VENT_PLUS_SedanH[12] = { 20, 20, 0, 0, 0, 0, 20, 20, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assFLOW_BI2_TEMP_TGT_SedanH[12] = { 300, 350, 400, 450, 500, 550, 300, 350, 400, 450, 500, 550}; +SECT_VEH_CAL_1 const tU08 c_aucFLOW_BI2_FOOT_PLUS_SedanH[12] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_1 const tU08 c_aucFLOW_BI2_VENT_VALVE_MAX_SedanH[12] = { 85, 85, 85, 85, 85, 85, 80, 80, 80, 80, 80, 80}; +SECT_VEH_CAL_1 const tU08 c_aucFLOW_BI2_FOOT_VALVE_MAX_SedanH[12] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tU08 c_aucFLOW_BI2_VENT_VALVE_MIN_SedanH[12] = { 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_1 const tU08 c_aucFLOW_BI2_FOOT_VALVE_MIN_SedanH[12] = { 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}; +/* ------------------------------------------AF level conditions: End*/ +SECT_VEH_CAL_1 const tS16 c_assFLOW_AF_AMB_TGT_SedanH[6] = { 450, 350, 100, 0, -150, -350}; +SECT_VEH_CAL_1 const tU08 c_aucFLOW_AF_VENT_PLUS_SedanH[12] = { 0, 0, 10, 10, 0, 0, 0, 0, 10, 10, 0, 0}; +SECT_VEH_CAL_1 const tU08 c_aucFLOW_AF_BLR_AF_TGT_SedanH[6] = { 60, 60, 60, 65, 70, 70}; +SECT_VEH_CAL_1 const tU08 c_aucFLOW_AF_FOOT_PLUS_SedanH[12] = { 20, 20, 20, 100, 150, 150, 20, 20, 20, 100, 150, 150}; +SECT_VEH_CAL_1 const tU08 c_aucFLOW_AF_VENT_VALVE_MAX_SedanH[12] = { 50, 50, 50, 50, 40, 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_1 const tU08 c_aucFLOW_AF_FOOT_VALVE_MAX_SedanH[12] = { 100, 100, 100, 100, 35, 100, 100, 100, 100, 100, 35, 100}; +/* ------------------------------------------AF level conditions: End*/ +SECT_VEH_CAL_1 const tS16 c_assFLOW_AFSM_AMB_TGT_SedanH[6] = { 450, 350, 200, 0, -150, -350}; +SECT_VEH_CAL_1 const tU08 c_aucFLOW_AFSM_VENT_PLUS_SedanH[12] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_1 const tS16 c_assFLOW_AFSM_TEMP_TGT_SedanH[12] = { 300, 350, 400, 450, 500, 550, 300, 350, 400, 450, 500, 550}; +SECT_VEH_CAL_1 const tU08 c_aucFLOW_AFSM_FOOT_PLUS_SedanH[12] = { 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_1 const tU08 c_aucFLOW_AFSM_VENT_VALVE_MAX_SedanH[12] = { 50, 50, 50, 50, 50, 50, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_1 const tU08 c_aucFLOW_AFSM_FOOT_VALVE_MAX_SedanH[12] = { 60, 60, 60, 60, 60, 60, 50, 50, 50, 50, 50, 50}; +/* ------------------------------------------AF_summer level conditions: End*/ +SECT_VEH_CAL_1 const tU08 c_aucMODE_INDEX_SedanH[11] = { 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 110}; +SECT_VEH_CAL_1 const tS16 c_assFOOT_STEP_DUCT_TGT_SedanH[7] = { -400, -250, -100, 0, 100, 250, 400}; +SECT_VEH_CAL_1 const tS16 c_assBLR_FOOT_IND_SedanH[7] = { 25, 10, 5, 0, 5, 10, 25}; +SECT_VEH_CAL_1 const tS08 c_ascFOOT_STEP_VALVE_P1_SedanH[11] = { 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_1 const tS08 c_ascFOOT_STEP_VALVE_P2_SedanH[11] = { 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25}; +SECT_VEH_CAL_1 const tS08 c_ascFOOT_STEP_VALVE_P3_SedanH[11] = { 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_1 const tS08 c_ascFOOT_STEP_VALVE_M1_SedanH[11] = { 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_1 const tS08 c_ascFOOT_STEP_VALVE_M2_SedanH[11] = { 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25}; +SECT_VEH_CAL_1 const tS08 c_ascFOOT_STEP_VALVE_M3_SedanH[11] = { 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_1 const tS16 c_assFOOT_STEP_BLR_P1_SedanH[11] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_1 const tS16 c_assFOOT_STEP_BLR_P2_SedanH[11] = { 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_1 const tS16 c_assFOOT_STEP_BLR_P3_SedanH[11] = { 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 10}; +SECT_VEH_CAL_1 const tS16 c_assFOOT_STEP_BLR_M1_SedanH[11] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_1 const tS16 c_assFOOT_STEP_BLR_M2_SedanH[11] = { 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_1 const tS16 c_assFOOT_STEP_BLR_M3_SedanH[11] = { 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20}; +/* ------------------------------------------Individual foot temperature: End*/ +SECT_VEH_CAL_1 const tU08 c_aucREAR_FOOT_VALVE_AMB_LV2_SedanH[13] = { 0, 0, 0, 0, 0, 0, 5, 10, 15, 20, 25, 30, 35}; +SECT_VEH_CAL_1 const tU08 c_aucREAR_FOOT_VALVE_AMB_LV3_SedanH[13] = { 0, 0, 0, 0, 0, 0, 5, 10, 15, 20, 25, 30, 35}; +SECT_VEH_CAL_1 const tU08 c_aucREAR_FOOT_VALVE_AMB_LV4_SedanH[13] = { 0, 0, 0, 0, 0, 0, 5, 10, 15, 20, 25, 30, 35}; +/* ------------------------------------------Blowing foots from Rear HVAC: End*/ +SECT_VEH_CAL_1 const tU16 c_ausFLOW_FR_VE2BLR_AF_SedanH[8] = { 0, 30, 51, 64, 88, 114, 135, 160}; +SECT_VEH_CAL_1 const tU16 c_ausFLOW_FR_BIVALVE_AF_SedanH[8] = { 0, 30, 51, 64, 88, 114, 135, 160}; +SECT_VEH_CAL_1 const tU16 c_ausFLOW_FR_BI2BLR_AF_SedanH[8] = { 0, 30, 51, 64, 88, 114, 135, 160}; +SECT_VEH_CAL_1 const tU16 c_ausFLOW_FR_FO2BLR_AF_SedanH[8] = { 0, 30, 51, 64, 88, 114, 135, 160}; +SECT_VEH_CAL_1 const tU16 c_ausFLOW_FR_AF2VALVE_AF_SedanH[8] = { 0, 30, 51, 64, 88, 114, 135, 160}; +SECT_VEH_CAL_1 const tU16 c_ausFLOW_FR_AF2VALVE_SUMMER_AF_SedanH[8] = { 0, 30, 51, 64, 88, 114, 135, 160}; +SECT_VEH_CAL_1 const tU16 c_ausFLOW_FR_FD2BLR_AF_SedanH[8] = { 0, 30, 51, 64, 88, 114, 135, 160}; +SECT_VEH_CAL_1 const tU16 c_ausFLOW_FR_DE2BLR_AF_SedanH[8] = { 0, 30, 51, 64, 88, 114, 135, 160}; +SECT_VEH_CAL_1 const tU16 c_ausFLOW_FR_TR2BLR_AF_SedanH[8] = { 0, 30, 51, 64, 88, 114, 135, 160}; +SECT_VEH_CAL_1 const tU16 c_ausFLOW_FR_HI2BLR_AF_SedanH[8] = { 0, 30, 51, 64, 88, 114, 135, 160}; +SECT_VEH_CAL_1 const tU16 c_ausFLOW_RE_VE2BLR_AF_SedanH[8] = { 0, 30, 51, 64, 88, 114, 135, 160}; +SECT_VEH_CAL_1 const tU16 c_ausFLOW_RE_BI2BLR_AF_SedanH[8] = { 0, 30, 51, 64, 88, 114, 135, 160}; +SECT_VEH_CAL_1 const tU16 c_ausFLOW_RE_FO2BLR_AF_SedanH[8] = { 0, 30, 51, 64, 88, 114, 135, 160}; +/* ------------------------------------------Flow Control AF: End*/ +SECT_VEH_CAL_1 const tS08 c_ascAUTO_STEP_AF_F_SedanH[5] = { -25, -13, 0, 15, 30}; +SECT_VEH_CAL_1 const tS08 c_ascAUTO_STEP_AF_R_SedanH[5] = { -25, -13, 0, 15, 30}; +SECT_VEH_CAL_1 const tS16 c_assAUTO_STEP_DUCT_TG_U_F_LV0_1_SedanH[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assAUTO_STEP_DUCT_TG_U_F_LV2_3_SedanH[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assAUTO_STEP_DUCT_TG_U_F_LV4_5_SedanH[10] = { -50, 0, 0, -50, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assAUTO_STEP_DUCT_TG_L_F_LV0_1_SedanH[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assAUTO_STEP_DUCT_TG_L_F_LV2_3_SedanH[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assAUTO_STEP_DUCT_TG_L_F_LV4_5_SedanH[10] = { 50, 50, 0, -128, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assAUTO_STEP_DUCT_TG_R_LV0_1_SedanH[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assAUTO_STEP_DUCT_TG_R_LV2_3_SedanH[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tS16 c_assAUTO_STEP_DUCT_TG_R_LV4_5_SedanH[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +/* ------------------------------------------5 AUTO mode: End*/ +SECT_VEH_CAL_1 const tU16 c_ausVALVE_SPACE_SedanH[6] = { 300, 300, 300, 269, 275, 215}; +SECT_VEH_CAL_1 const tU08 c_aucVALVE_SECTION_S1_F_SIDE_VENT_SedanH[9] = { 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_1 const tU08 c_aucVALVE_SECTION_S1_F_CENT_VENT_SedanH[9] = { 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_1 const tU08 c_aucVALVE_SECTION_S1_F_DRIVER_FOOT_SedanH[9] = { 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_1 const tU08 c_aucVALVE_SECTION_S1_F_RIGHT_PASS_SedanH[9] = { 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_1 const tU08 c_aucBLR_SPD_V1_1_F_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tU08 c_aucBLR_SPD_K2_1_F_SIDE_VENT_SedanH[10] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tU08 c_aucBLR_SPD_K2_2_F_CENT_VENT_SedanH[10] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tU08 c_aucBLR_SPD_K2_3_F_DRIVER_FOOT_SedanH[10] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tU08 c_aucBLR_SPD_K2_4_F_RIGHT_PASS_SedanH[13] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tU16 c_ausVALVE_VEH_SPD_SedanH[13] = { 0, 40, 60, 80, 90, 110, 130, 150, 170, 190, 220, 250, 300}; +SECT_VEH_CAL_1 const tU08 c_aucVALVE_VEH_SPD_SIDE_VENT_SedanH[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_1 const tU08 c_aucVALVE_VEH_SPD_SIDE_BI_SedanH[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_1 const tU08 c_aucVALVE_VEH_SPD_SIDE_AFOOT_SedanH[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_1 const tU08 c_aucVALVE_VEH_SPD_CNET_VENT_SedanH[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_1 const tU08 c_aucVALVE_VEH_SPD_CENT_BI_SedanH[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_1 const tU08 c_aucVALVE_VEH_SPD_CENT_AFOOT_SedanH[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_1 const tU08 c_aucVALVE_VEH_SPD_FOOT_BI_SedanH[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_1 const tU08 c_aucVALVE_VEH_SPD_FOOT_AFOOT_SedanH[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_1 const tU08 c_aucVALVE_VEH_SPD_2FOOT_SedanH[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_1 const tU08 c_aucBLR_SPD_VEH_SPD_V1_3_SedanH[12] = { 100, 70, 30, 100, 70, 30, 100, 70, 30, 100, 70, 30}; +SECT_VEH_CAL_1 const tU08 c_aucFRONT_SIDE_DRS_PERCENT_SedanH[12] = { 100, 70, 30, 100, 70, 30, 100, 70, 30, 100, 70, 30}; +SECT_VEH_CAL_1 const tU08 c_aucFRONT_CENT_DRS_PERCENT_SedanH[12] = { 100, 70, 30, 100, 70, 30, 100, 70, 30, 100, 70, 30}; +/* ------------------------------------------Different blower speed FRONT MODE: End*/ +SECT_VEH_CAL_1 const tU08 c_aucVALVE_S1_R_BIPILLAR_SedanH[8] = { 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_1 const tU08 c_aucVALVE_S1_R_CENT_VENT_SedanH[9] = { 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_1 const tU08 c_aucVALVE_S1_R_FOOT_SedanH[5] = { 10, 10, 10, 10, 10}; +SECT_VEH_CAL_1 const tU08 c_aucVALVE_PERC_R_BIPILLAR_SedanH[10] = { 10, 20, 30, 40, 50, 60, 70, 80, 90, 100}; +SECT_VEH_CAL_1 const tU08 c_aucVALVE_PERC_R_CENT_VENT_SedanH[10] = { 10, 20, 30, 40, 50, 60, 70, 80, 90, 100}; +SECT_VEH_CAL_1 const tU08 c_aucVALVE_PERC_R_FOOT_SedanH[10] = { 10, 20, 30, 40, 50, 60, 70, 80, 90, 100}; +SECT_VEH_CAL_1 const tU08 c_aucBLR_SPD_V1_1_R_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tU08 c_aucREAR_CEN_MIN_VALUE_BY_DRS_ZERO_SedanH[7] = { 30, 29, 28, 27, 24, 22, 20}; +SECT_VEH_CAL_1 const tU08 c_aucBLR_SPD_K2_1_R_BIPILLAR_MIN_SedanH[8] = { 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tU08 c_aucBLR_SPD_K2_2_R_CENT_VENT_MIN_SedanH[9] = { 85, 85, 85, 85, 85, 85, 85, 85, 85}; +SECT_VEH_CAL_1 const tU08 c_aucBLR_SPD_K2_3_R_FOOT_MIN_SedanH[5] = { 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tU08 c_aucBLR_SPD_K2_1_R_BIPILLAR_MAX_SedanH[8] = { 120, 120, 120, 120, 120, 120, 120, 120}; +SECT_VEH_CAL_1 const tU08 c_aucBLR_SPD_K2_2_R_CENT_VENTR_MAX_SedanH[9] = { 122, 122, 122, 122, 122, 122, 122, 122, 122}; +SECT_VEH_CAL_1 const tU08 c_aucBLR_SPD_K2_3_R_FOOTR_MAX_SedanH[5] = { 130, 130, 130, 130, 130}; +SECT_VEH_CAL_1 const tU08 c_aucREAR_SIDE_DRS_PERCENT_VALVE_SedanH[9] = { 100, 70, 30, 100, 70, 30, 100, 70, 30}; +SECT_VEH_CAL_1 const tU08 c_aucREAR_CENT_DRS_PERCENT_VALVE_SedanH[9] = { 100, 70, 30, 100, 70, 30, 100, 70, 30}; +SECT_VEH_CAL_1 const tU08 c_aucREAR_SIDE_DRS_PERCENT_AF_SedanH[9] = { 100, 70, 30, 100, 70, 30, 100, 70, 30}; +SECT_VEH_CAL_1 const tU08 c_aucREAR_CENT_DRS_PERCENT_AF_SedanH[9] = { 100, 70, 30, 100, 70, 30, 100, 70, 30}; +/* ------------------------------------------Different blower speed REAR MODE: End*/ +SECT_VEH_CAL_1 const tU16 c_ausMIN_PWM_SedanH[2] = { 151, 151}; +/* ------------------------------------------MinPWM: End*/ +SECT_VEH_CAL_1 const tS16 c_assSTART_ENTER_COOLANT_SedanH[6] = { 600, 600, 600, 500, 400, 400}; +SECT_VEH_CAL_1 const tS16 c_assSTART_COOLANT_STEP0_TO_1_SedanH[8] = { 0, 400, 400, 400, 300, 400, 400, 400}; +SECT_VEH_CAL_1 const tS16 c_assSTART_COOLANT_TO_STEP2_SedanH[3] = { 800, 800, 850}; +SECT_VEH_CAL_1 const tS16 c_assSTART_COOLANT_STEP1_BLR_F_SedanH[6] = { 0, 0, 0, 700, 650, 650}; +SECT_VEH_CAL_1 const tS16 c_assSTART_COOLANT_STEP1_BLR_R_SedanH[6] = { 0, 0, 700, 600, 600, 600}; +SECT_VEH_CAL_1 const tS16 c_assSTART_ENTER_INCAR_SedanH[12] = { 500, 450, 500, 50, 100, 0, 500, 450, 200, 50, 100, 50}; +SECT_VEH_CAL_1 const tU16 c_ausSTART_ENTER_SETTEMP_SedanH[12] = { 260, 250, 0, 160, 0, 0, 260, 250, 200, 200, 0, 0}; +SECT_VEH_CAL_1 const tU08 c_aucSTART_INCAR_FLT_UP_SedanH[12] = { 20, 20, 20, 20, 40, 20, 20, 20, 20, 20, 40, 20}; +SECT_VEH_CAL_1 const tU08 c_aucSTART_INCAR_FLT_DN_SedanH[12] = { 20, 20, 20, 20, 40, 20, 20, 20, 20, 20, 40, 20}; +SECT_VEH_CAL_1 const tU08 c_aucSTART_VALVE_IDX_STEP1_SedanH[12] = { 10, 10, 10, 70, 70, 70, 120, 120, 140, 140, 140, 140}; +SECT_VEH_CAL_1 const tU08 c_aucSTART_AUTODEMIST2_STEP2_SedanH[6] = { 0, 0, 1, 1, 1, 1}; +SECT_VEH_CAL_1 const tU08 c_aucSTART_ELEC_WINDOW_SedanH[12] = { 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 1, 1}; +SECT_VEH_CAL_1 const tU16 c_ausSTART_BLR_AF_STEP12_F_SedanH[12] = { 160, 100, 120, 60, 60, 60, 140, 100, 100, 140, 140, 140}; +SECT_VEH_CAL_1 const tU16 c_ausSTART_BLR_AF_STEP12_R_SedanH[12] = { 160, 130, 60, 60, 60, 60, 140, 120, 100, 140, 140, 140}; +SECT_VEH_CAL_1 const tU16 c_ausSTART_BLR_SPD_STEP2_F_SedanH[12] = { 5, 1, 1, 1, 1, 1, 2, 5, 2, 3, 3, 4}; +SECT_VEH_CAL_1 const tU16 c_ausSTART_BLR_SPD_STEP2_R_SedanH[12] = { 5, 1, 1, 1, 1, 1, 2, 5, 2, 3, 4, 4}; +SECT_VEH_CAL_1 const tU08 c_aucSTART_DUCT_TGT_STEP2_FX_U_SedanH[12] = { 5, 5, 5, 50, 60, 60, 3, 3, 3, 3, 3, 3}; +SECT_VEH_CAL_1 const tU08 c_aucSTART_DUCT_TGT_STEP2_FX_L_SedanH[12] = { 15, 15, 15, 80, 80, 80, 6, 6, 6, 20, 30, 30}; +SECT_VEH_CAL_1 const tU08 c_aucSTART_DUCT_TGT_STEP2_RX_SedanH[12] = { 5, 5, 30, 60, 60, 80, 3, 3, 3, 6, 6, 6}; +SECT_VEH_CAL_1 const tU08 c_aucSTART_VALVE_CHANGE_SPD_F_SedanH[12] = { 1, 1, 1, 1, 1, 1, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_1 const tU08 c_aucSTART_VALVE_CHANGE_SPD_R_SedanH[12] = { 1, 1, 1, 1, 1, 1, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_1 const tU16 c_ausSTART_TIME_STEP1_TO_2_SedanH[12] = { 720, 720, 180, 1200, 2400, 2400, 720, 720, 1200, 1200, 2400, 2400}; +SECT_VEH_CAL_1 const tU16 c_ausSTART_TIME_STEP2_TO_3_SedanH[12] = { 120, 120, 180, 600, 600, 1200, 240, 240, 600, 600, 360, 360}; +SECT_VEH_CAL_1 const tS16 c_assSTART_INCAR_STEP1_TO_2_SedanH[12] = { 300, 300, 300, 200, 210, 250, 300, 300, 200, 230, 210, 250}; +SECT_VEH_CAL_1 const tS16 c_assSTART_INCAR_STEP2_TO_3_SedanH[12] = { 300, 300, 250, 250, 250, 280, 220, 220, 220, 220, 250, 270}; +SECT_VEH_CAL_1 const tU08 c_aucSTART_3WAY_OPEN_SedanH[12] = { 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1}; +SECT_VEH_CAL_1 const tU08 c_aucSTART_2WAY_OPEN_SedanH[12] = { 0, 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 1}; +SECT_VEH_CAL_1 const tU08 c_aucSTART_TXV_F_SedanH[12] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}; +SECT_VEH_CAL_1 const tU08 c_aucSTART_TXV_R_SedanH[12] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}; +/* ------------------------------------------Start control: End*/ +SECT_VEH_CAL_1 const tS16 c_assFAILURE_AMB_TEMP_SedanH[13] = { -200, -150, -80, -50, 0, 100, 150, 200, 250, 300, 350, 400, 450}; +SECT_VEH_CAL_1 const tS16 c_assAC_PRESSURE_LOW_HYS_UP_SedanH[13] = { 6, 8, 9, 10, 11, 15, 24, 30, 37, 55, 57, 60, 65}; +SECT_VEH_CAL_1 const tS16 c_assAC_PRESSURE_LOW_HYS_DN_SedanH[13] = { 5, 7, 8, 9, 10, 12, 15, 25, 25, 30, 30, 30, 40}; +SECT_VEH_CAL_1 const tS16 c_assAC_LOW_AMB_F_SedanH[2] = { 50, 70}; +SECT_VEH_CAL_1 const tS16 c_assAC_CUT_OFF_AMB_F_SedanH[2] = { -50, -30}; +SECT_VEH_CAL_1 const tS16 c_assAC_WINTER_TXV_DEWPOINT_SedanH[2] = { 40, 30}; +SECT_VEH_CAL_1 const tS16 c_assAC_CUT_OFF_AMB_R_SedanH[2] = { -220, -210}; +SECT_VEH_CAL_1 const tS16 c_assEVA_TG_AMB_F_SedanH[13] = { 100, 100, 80, 80, 80, 60, 50, 40, 30, 30, 25, 25, 25}; +SECT_VEH_CAL_1 const tS16 c_assEVA_TG_AMB_R_SedanH[13] = { 100, 100, 80, 80, 80, 60, 50, 40, 30, 30, 25, 25, 25}; +SECT_VEH_CAL_1 const tU08 c_ucAC_EXTRA_RPM_SedanH = 15; +SECT_VEH_CAL_1 const tS16 c_assAC_EVA_LV_SHUT_OFF_SedanH[2] = { 150, 10}; +SECT_VEH_CAL_1 const tS16 c_assAC_PRESSURE_HYS_HI_ENG_ON_SedanH[3] = { 331, 265, 186}; +SECT_VEH_CAL_1 const tU16 c_usCMP_MAX_ENG_OFF_SedanH = 3000; +SECT_VEH_CAL_1 const tU08 c_ucFAN_MAX_ENG_OFF_SedanH = 15; +SECT_VEH_CAL_1 const tS16 c_ssAC_WINTER_TXV_HYST_SedanH = 15; +SECT_VEH_CAL_1 const tU08 c_aucAC_PRESSURE_HYS_HI_ENG_OFF_SedanH[2] = { 186, 155}; +SECT_VEH_CAL_1 const tU16 c_ausCMP_RPM_RESONANCE_SedanH[6] = { 1500, 1550, 2500, 2560, 7500, 7590}; +/* ------------------------------------------A/C Control Pressure : End*/ +SECT_VEH_CAL_1 const tS16 c_assPRESSURE_TO_FAN_X_SedanH[7] = { 50, 70, 90, 100, 174, 184, 240}; +SECT_VEH_CAL_1 const tU08 c_aucPRESSURE_TO_FAN_Y_SedanH[7] = { 8, 15, 30, 50, 70, 80, 100}; +/* ------------------------------------------CoolingFan: End*/ +SECT_VEH_CAL_1 const tS16 c_ssREST_BATT_SedanH = 109; +SECT_VEH_CAL_1 const tS16 c_ssRESTW_AMB_SedanH = 100; +SECT_VEH_CAL_1 const tS16 c_assRESTW_WATER_SedanH[2] = { 550, 350}; +SECT_VEH_CAL_1 const tU16 c_usRESTW_READYEXPIRETIME_SedanH = 120; +SECT_VEH_CAL_1 const tU08 c_aucRESTW_MODE_SedanH[2] = { 70, 130}; +SECT_VEH_CAL_1 const tU16 c_usRESTW_TIMEOUTTIME_SedanH = 900; +SECT_VEH_CAL_1 const tU08 c_ucRESTW_BLRSTEP_SedanH = 2; +SECT_VEH_CAL_1 const tS16 c_ssRESTS_AMB_SedanH = 100; +SECT_VEH_CAL_1 const tU08 c_uctRESTS_READYEXPIRETIME_SedanH = 120; +SECT_VEH_CAL_1 const tU08 c_aucRESTS_MODE_SedanH[2] = { 70, 130}; +SECT_VEH_CAL_1 const tU16 c_usRESTS_TIMEOUTTIME_SedanH = 600; +SECT_VEH_CAL_1 const tU08 c_ucRESTS_BLRSTEP_SedanH = 3; +/* ------------------------------------------Rest mode: End*/ +SECT_VEH_CAL_1 const tU16 c_usFRESH_AIR_PURGE_ENTRY_TIME_SedanH = 900; +SECT_VEH_CAL_1 const tU16 c_ausFRESH_AIR_PURGE_CHANGE_TIME_SedanH[7] = { 10, 10, 10, 50, 10, 10, 10}; +/* ------------------------------------------Purge Rec: End*/ +SECT_VEH_CAL_1 const tS16 c_assMAX_DEF_U_DTG_SedanH[10] = { 850, 850, 700, 550, 400, 350, 100, 50, 50, 50}; +SECT_VEH_CAL_1 const tU16 c_ausMAX_BLR_SPD_SedanH[6] = { 160, 160, 160, 160, 160, 160}; +/* ------------------------------------------MAX DEF: End*/ +SECT_VEH_CAL_1 const tU08 c_aucAQS_REC_LV_CO_SedanH[8] = { 0, 0, 0, 0, 0, 0, 0, 4}; +SECT_VEH_CAL_1 const tU08 c_aucAQS_OSA_LV_CO_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tU08 c_aucAQS_REC_LV_NOX_SedanH[8] = { 0, 0, 0, 0, 0, 0, 0, 4}; +SECT_VEH_CAL_1 const tU08 c_aucAQS_OSA_LV_NOX_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tU08 c_aucAQS_REC_LV_NH3_SedanH[8] = { 0, 0, 0, 0, 0, 0, 0, 4}; +SECT_VEH_CAL_1 const tU08 c_aucAQS_OSA_LV_NH3_SedanH[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_1 const tU08 c_ucAQS_REC_ON_TIME_SedanH = 30; +SECT_VEH_CAL_1 const tU08 c_aucAQS_REC_ON_WAIT_SedanH[2] = { 60, 10}; +/* ------------------------------------------Aqs: End*/ +SECT_VEH_CAL_1 const tU16 c_usAUTODEMIST_LV2_BLR_PLUS_SedanH = 10; +SECT_VEH_CAL_1 const tU16 c_usAUTODEMIST_LV3_BLR_PLUS_SedanH = 30; +SECT_VEH_CAL_1 const tS16 c_assAUTODEMIST_OFFSET_AMB_TEMP_SedanH[9] = { -50, -30, -20, -10, 0, 10, 20, 30, 50}; +SECT_VEH_CAL_1 const tS16 c_assAUTODEMIST_OFFSET_VENT_TEMP_SedanH[9] = { 22, 18, 15, 11, 8, 8, 7, 5, 5}; +SECT_VEH_CAL_1 const tS16 c_assAUTODEMIST_STEP_UP_SedanH[4] = { 50, 30, 20, -10}; +SECT_VEH_CAL_1 const tS16 c_assAUTODEMIST_STEP_DN_SedanH[4] = { 55, 35, 25, 0}; +SECT_VEH_CAL_1 const tS16 c_assAUTODEMIST_WINTER_SedanH[2] = { -35, -30}; +/* ------------------------------------------Auto Demist: End*/ +SECT_VEH_CAL_1 const tS16 c_ssAUTODEMIST_ELEC_AMB_ENTRY_SedanH = -300; +SECT_VEH_CAL_1 const tS16 c_assAUTODEMIST_ELEC_WINDSHELD_TEMP_SedanH[2] = { -250, -230}; +/* ------------------------------------------Electric AutoDemist: End*/ +SECT_VEH_CAL_1 const tS16 c_ssAMBFILT_WATER_SedanH = 500; +SECT_VEH_CAL_1 const tU08 c_aucAMBFILT_H_CNT_SedanH[2] = { 200, 200}; +SECT_VEH_CAL_1 const tS16 c_ssAMB_FAILSAFE_SedanH = 230; +SECT_VEH_CAL_1 const tS16 c_ssAMBKEEP_KAT_SedanH = 200; +SECT_VEH_CAL_1 const tS16 c_ssAMBKEEP_KAT_PLUS_SedanH = 350; +SECT_VEH_CAL_1 const tS16 c_ssAMBKEEP_WATER_SedanH = 500; +SECT_VEH_CAL_1 const tU08 c_aucAMBRATE_RISING_SedanH[6] = { 30, 30, 30, 30, 30, 30}; +SECT_VEH_CAL_1 const tU08 c_aucAMBRATE_FALLING_SedanH[6] = { 30, 30, 30, 30, 30, 30}; +SECT_VEH_CAL_1 const tU08 c_aucAMBRATE_RISING_DIFF_SedanH[8] = { 120, 120, 120, 120, 155, 155, 155, 50}; +SECT_VEH_CAL_1 const tU08 c_aucAMBRATE_FALLING_DIFF_SedanH[8] = { 120, 120, 120, 255, 255, 255, 155, 50}; +/* ------------------------------------------Ambient: End*/ +SECT_VEH_CAL_1 const tU16 c_ausINCARRATE_RISING_F_SedanH[6] = { 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_1 const tU16 c_ausINCARRATE_FALLING_F_SedanH[6] = { 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_1 const tU16 c_ausINCARRATE_RISING_DIFF_F_SedanH[8] = { 100, 100, 100, 100, 100, 100, 50, 5}; +SECT_VEH_CAL_1 const tU16 c_ausINCARRATE_FALLING_DIFF_F_SedanH[8] = { 40, 40, 40, 40, 40, 40, 50, 5}; +SECT_VEH_CAL_1 const tU16 c_ausINCARRATE_RISING_R_SedanH[6] = { 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_1 const tU16 c_ausINCARRATE_FALLING_R_SedanH[6] = { 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_1 const tU16 c_ausINCARRATE_RISING_DIFF_R_SedanH[8] = { 100, 100, 100, 100, 100, 100, 50, 5}; +SECT_VEH_CAL_1 const tU16 c_ausINCARRATE_FALLING_DIFF_R_SedanH[8] = { 40, 40, 40, 40, 40, 40, 50, 5}; +/* ------------------------------------------Incar: End*/ +SECT_VEH_CAL_1 const tU16 c_ausSUNRATE_RISING_SedanH[6] = { 200, 200, 200, 200, 200, 200}; +SECT_VEH_CAL_1 const tU16 c_ausSUNRATE_FALLING_SedanH[6] = { 200, 200, 200, 200, 200, 200}; +/* ------------------------------------------Sun: End*/ +SECT_VEH_CAL_1 const tU16 c_ausAMB_LV_CHANGE_UNIT_SedanH[6] = { 1, 1, 1, 10, 10, 3}; +SECT_VEH_CAL_1 const tU08 c_aucAMB_LV_CHANGE_SEC_SedanH[6] = { 1, 1, 1, 1, 1, 1}; +/* ------------------------------------------Level Chage: End*/ +SECT_VEH_CAL_1 const tS16 c_ssTHREEWAY_WATER_SedanH = 40; +SECT_VEH_CAL_1 const tS16 c_assTHREEWAY_DUCT_TGT_R_SedanH[2] = { 20, 15}; +SECT_VEH_CAL_1 const tU08 c_aucTHEREEWAY_EXPIRING_SedanH[2] = { 60, 5}; +/* ------------------------------------------Three way: End*/ +SECT_VEH_CAL_1 const tS16 c_assTWOWAY_REAR_DUCTTGT_R_SedanH[2] = { 70, 60}; +SECT_VEH_CAL_1 const tU08 c_aucTWOWAY_EXPIRING_SedanH[2] = { 60, 5}; +/* ------------------------------------------two-way: End*/ +SECT_VEH_CAL_1 const tU08 c_aucACT_HOM_SPD_FL_CH0_SedanH[9] = { 3, 3, 3, 3, 3, 3, 3, 3, 3}; +SECT_VEH_CAL_1 const tU08 c_aucACT_HOM_SPD_FR_CH1_SedanH[6] = { 3, 3, 3, 3, 3, 3}; +SECT_VEH_CAL_1 const tU08 c_aucACT_HOM_SPD_R_CH2_SedanH[9] = { 3, 3, 3, 3, 3, 3, 3, 3, 3}; +SECT_VEH_CAL_1 const tU08 c_aucACT_HOM_SPD_R_EX_CH2_SedanH[4] = { 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tU08 c_aucACT_MOV_SPD_FL_CH0_SedanH[9] = { 3, 3, 3, 3, 3, 3, 3, 3, 3}; +SECT_VEH_CAL_1 const tU08 c_aucACT_MOV_SPD_FR_CH1_SedanH[6] = { 3, 3, 3, 3, 3, 3}; +SECT_VEH_CAL_1 const tU08 c_aucACT_MOV_SPD_R_CH2_SedanH[9] = { 3, 3, 3, 3, 3, 3, 3, 3, 3}; +SECT_VEH_CAL_1 const tU08 c_aucACT_MOV_SPD_R_EX_CH2_SedanH[4] = { 0, 0, 0, 0}; +/* ------------------------------------------Actuator Homing: End*/ +SECT_VEH_CAL_1 const tS16 c_assHI_MODE_ENG_TMEP_SedanH[6] = { 35, 45, 60, 80, 100, 120}; +SECT_VEH_CAL_1 const tU08 c_aucHI_MODE_BLR_STEP_STS_SedanH[6] = { 2, 3, 4, 5, 100, 100}; +/* ------------------------------------------Hi Mode: End*/ +SECT_VEH_CAL_1 const tU16 c_ausMinusAF_GlassPos_L_SedanH[13] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tU16 c_ausMinusAF_GlassPos_R_SedanH[13] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +/* ------------------------------------------GlassPosition: End*/ +SECT_VEH_CAL_1 const tS16 c_assFoot2_Lv3_Amb_SedanH[6] = { -150, -100, -50, 0, 50, 100}; +SECT_VEH_CAL_1 const tS16 c_assFoot2_Lv4_Amb_SedanH[6] = { -300, -250, -200, -150, -100, -50}; +SECT_VEH_CAL_1 const tS16 c_assFoot2_Lv5_Amb_SedanH[6] = { -700, -650, -600, -550, -500, -450}; +SECT_VEH_CAL_1 const tS16 c_assFoot2_Lv3_DuctTgt_Plus_SedanH[6] = { 550, 500, 450, 400, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assFoot2_Lv4_DuctTgt_Plus_SedanH[6] = { 550, 500, 450, 400, 300, 300}; +SECT_VEH_CAL_1 const tS16 c_assFoot2_Lv5_DuctTgt_Plus_SedanH[6] = { 550, 500, 450, 400, 300, 300}; +SECT_VEH_CAL_1 const tU16 c_ausFoot2_Lv1_FrontBlr_X_SedanH[3] = { 250, 500, 750}; +SECT_VEH_CAL_1 const tU16 c_ausFoot2_Lv1_Foot2Act_Y_SedanH[3] = { 250, 500, 750}; +SECT_VEH_CAL_1 const tS16 c_assFoot2_Lv2_Threshold_Diff_SedanH[2] = { 50, 35}; +SECT_VEH_CAL_1 const tS16 c_assFoot2_Lv3_Threshold_Diff_SedanH[2] = { 50, 35}; +/* ------------------------------------------Foot2 Ctrl: End*/ +SECT_VEH_CAL_1 const tU16 c_ausDbF_Side_Af_Bi_SedanH[9] = { 90, 91, 92, 93, 94, 95, 96, 97, 98}; +SECT_VEH_CAL_1 const tU16 c_ausDbF_Side_Af_Bi2_SedanH[9] = { 90, 91, 92, 93, 94, 95, 96, 97, 98}; +SECT_VEH_CAL_1 const tU16 c_ausDbF_Side_Af_Vent_SedanH[9] = { 70, 70, 65, 65, 62, 60, 55, 50, 50}; +SECT_VEH_CAL_1 const tU16 c_ausDbF_Side_Bi_Bi2_SedanH[9] = { 80, 80, 80, 80, 80, 80, 80, 80, 80}; +SECT_VEH_CAL_1 const tU16 c_ausDbF_Side_Bi_Vent_SedanH[9] = { 65, 55, 45, 40, 38, 35, 32, 30, 25}; +SECT_VEH_CAL_1 const tU16 c_ausDbF_Side_Bi2_Vent_SedanH[9] = { 80, 80, 80, 80, 80, 80, 80, 80, 80}; +SECT_VEH_CAL_1 const tU16 c_ausDbF_Cen_Af_Bi_SedanH[9] = { 90, 91, 92, 93, 94, 95, 96, 97, 98}; +SECT_VEH_CAL_1 const tU16 c_ausDbF_Cen_Af_Bi2_SedanH[9] = { 90, 91, 92, 93, 94, 95, 96, 97, 98}; +SECT_VEH_CAL_1 const tU16 c_ausDbF_Cen_Af_Vent_SedanH[9] = { 70, 70, 70, 65, 62, 60, 55, 50, 50}; +SECT_VEH_CAL_1 const tU16 c_ausDbF_Cen_Bi_Bi2_SedanH[9] = { 80, 80, 80, 80, 80, 80, 80, 80, 80}; +SECT_VEH_CAL_1 const tU16 c_ausDbF_Cen_Bi_Vent_SedanH[9] = { 65, 55, 45, 40, 38, 35, 32, 30, 25}; +SECT_VEH_CAL_1 const tU16 c_ausDbF_Cen_Bi2_Vent_SedanH[9] = { 80, 80, 80, 80, 80, 80, 80, 80, 80}; +SECT_VEH_CAL_1 const tU16 c_ausDbF_Foot_Af_Bi_SedanH[9] = { 90, 91, 92, 93, 94, 95, 96, 97, 98}; +SECT_VEH_CAL_1 const tU16 c_ausDbF_Foot_Af_Bi2_SedanH[9] = { 90, 91, 92, 93, 94, 95, 96, 97, 98}; +SECT_VEH_CAL_1 const tU16 c_ausDbF_Foot_Af_Vent_SedanH[9] = { 70, 70, 70, 65, 62, 60, 55, 50, 50}; +SECT_VEH_CAL_1 const tU16 c_ausDbF_Foot_Bi_Bi2_SedanH[9] = { 80, 80, 80, 80, 80, 80, 80, 80, 80}; +SECT_VEH_CAL_1 const tU16 c_ausDbF_Foot_Bi_Vent_SedanH[9] = { 65, 65, 65, 65, 65, 65, 65, 65, 65}; +SECT_VEH_CAL_1 const tU16 c_ausDbF_Foot_Bi2_Vent_SedanH[9] = { 80, 80, 80, 80, 80, 80, 80, 80, 80}; +SECT_VEH_CAL_1 const tU16 c_ausDbF_AF_Af_Bi_SedanH[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tU16 c_ausDbF_AF_Af_Bi2_SedanH[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tU16 c_ausDbF_AF_Af_Vent_SedanH[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tU16 c_ausDbF_AF_Bi_Bi2_SedanH[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tU16 c_ausDbF_AF_Bi_Vent_SedanH[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tU16 c_ausDbF_AF_Bi2_Vent_SedanH[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_1 const tU16 c_ausDbF_Pwm_Af_Bi_SedanH[9] = { 120, 120, 120, 120, 120, 120, 120, 120, 120}; +SECT_VEH_CAL_1 const tU16 c_ausDbF_Pwm_Af_Bi2_SedanH[9] = { 120, 120, 120, 120, 120, 120, 120, 120, 120}; +SECT_VEH_CAL_1 const tU16 c_ausDbF_Pwm_Af_Vent_SedanH[9] = { 120, 120, 85, 120, 120, 120, 120, 120, 120}; +SECT_VEH_CAL_1 const tU16 c_ausDbF_Pwm_Bi_Bi2_SedanH[9] = { 120, 120, 120, 120, 120, 120, 120, 120, 120}; +SECT_VEH_CAL_1 const tU16 c_ausDbF_Pwm_Bi_Vent_SedanH[9] = { 120, 120, 120, 120, 120, 120, 120, 120, 120}; +SECT_VEH_CAL_1 const tU16 c_ausDbF_Pwm_Bi2_Vent_SedanH[9] = { 105, 120, 120, 90, 120, 120, 120, 105, 90}; +/* ------------------------------------------Different blower Front: End*/ +SECT_VEH_CAL_1 const tU16 c_usAromaPwm_Min_SedanH = 200; +SECT_VEH_CAL_1 const tU16 c_usAromaPwm_Max_SedanH = 700; +/* ------------------------------------------Aroma Limit Pwm: End*/ +/*********************************************************Cal Table End*/ + +/****************************************************************************** + * LOCAL VARIABLES DECLARATIONS + *****************************************************************************/ +/****************************************************************************** + * LOCAL FUNCTIONS DECLARATIONS + *****************************************************************************/ +/****************************************************************************** + * GLOBAL FUNCTIONS + *****************************************************************************/ + +/** Doxygen: Function brief + ****************************************************************************** + * @fn Rs_Cal_1_SedanH(void) + * @brief No brief + * @remark No description + * @param[in] (All of const data in this file) + * @param[out] All of global variable in Rs_Cal_Base.c + * @return None + *****************************************************************************/ +void Rs_Cal_1_SedanH(void) +{ + M_MEMCOPY((g_aucCAL_FP_DATE), (c_aucCAL_FP_DATE_SedanH)); + M_MEMCOPY((g_aucCAL_VERSION), (c_aucCAL_VERSION_SedanH)); + g_ucCAL_VARIANT = c_ucCAL_VARIANT_SedanH; +/* ------------------------------------------Cal Version : End*/ + M_MEMCOPY((g_ausSET_TEMP_FULL), (c_ausSET_TEMP_FULL_SedanH)); + M_MEMCOPY((g_ausSET_TEMP_HALF), (c_ausSET_TEMP_HALF_SedanH)); +/* ------------------------------------------Set Temp : End*/ + M_MEMCOPY((g_assINCAR_TG_FL_LV0), (c_assINCAR_TG_FL_LV0_SedanH)); + M_MEMCOPY((g_assINCAR_TG_FR_LV0), (c_assINCAR_TG_FR_LV0_SedanH)); + M_MEMCOPY((g_assVTG_FL_LV0), (c_assVTG_FL_LV0_SedanH)); + M_MEMCOPY((g_assVTG_FR_LV0), (c_assVTG_FR_LV0_SedanH)); + M_MEMCOPY((g_assVF_MIN_LV0), (c_assVF_MIN_LV0_SedanH)); + M_MEMCOPY((g_assVF_MAX_LV0), (c_assVF_MAX_LV0_SedanH)); + M_MEMCOPY((g_assVF_INC_Y1_LV0), (c_assVF_INC_Y1_LV0_SedanH)); + M_MEMCOPY((g_assVF_INC_Y2_LV0), (c_assVF_INC_Y2_LV0_SedanH)); + M_MEMCOPY((g_assVF_INC_Y3_LV0), (c_assVF_INC_Y3_LV0_SedanH)); + M_MEMCOPY((g_assVF_INC_Y4_LV0), (c_assVF_INC_Y4_LV0_SedanH)); + M_MEMCOPY((g_assVF_INC_X1_LV0), (c_assVF_INC_X1_LV0_SedanH)); + M_MEMCOPY((g_assVF_INC_X2_LV0), (c_assVF_INC_X2_LV0_SedanH)); + M_MEMCOPY((g_assVF_INC_X3_LV0), (c_assVF_INC_X3_LV0_SedanH)); + M_MEMCOPY((g_assVF_INC_X4_LV0), (c_assVF_INC_X4_LV0_SedanH)); + M_MEMCOPY((g_assVF_AMB_Y1_LV0), (c_assVF_AMB_Y1_LV0_SedanH)); + M_MEMCOPY((g_assVF_AMB_Y2_LV0), (c_assVF_AMB_Y2_LV0_SedanH)); + M_MEMCOPY((g_assVF_AMB_X1_LV0), (c_assVF_AMB_X1_LV0_SedanH)); + M_MEMCOPY((g_assVF_AMB_X2_LV0), (c_assVF_AMB_X2_LV0_SedanH)); + M_MEMCOPY((g_assVF_SUN_Y1_LV0), (c_assVF_SUN_Y1_LV0_SedanH)); + M_MEMCOPY((g_assVF_SUN_Y2_LV0), (c_assVF_SUN_Y2_LV0_SedanH)); + M_MEMCOPY((g_assVF_SUN_X1_LV0), (c_assVF_SUN_X1_LV0_SedanH)); + M_MEMCOPY((g_assVF_SUN_X2_LV0), (c_assVF_SUN_X2_LV0_SedanH)); + M_MEMCOPY((g_assTG_FLU_LV0), (c_assTG_FLU_LV0_SedanH)); + M_MEMCOPY((g_assTG_FRU_LV0), (c_assTG_FRU_LV0_SedanH)); + M_MEMCOPY((g_assDTG_FU_MIN_LV0), (c_assDTG_FU_MIN_LV0_SedanH)); + M_MEMCOPY((g_assDTG_FU_MAX_LV0), (c_assDTG_FU_MAX_LV0_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_Y1_LV0), (c_assDTG_FU_INC_Y1_LV0_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_Y2_LV0), (c_assDTG_FU_INC_Y2_LV0_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_Y3_LV0), (c_assDTG_FU_INC_Y3_LV0_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_Y4_LV0), (c_assDTG_FU_INC_Y4_LV0_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_X1_LV0), (c_assDTG_FU_INC_X1_LV0_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_X2_LV0), (c_assDTG_FU_INC_X2_LV0_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_X3_LV0), (c_assDTG_FU_INC_X3_LV0_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_X4_LV0), (c_assDTG_FU_INC_X4_LV0_SedanH)); + M_MEMCOPY((g_assDTG_FU_AMB_Y1_LV0), (c_assDTG_FU_AMB_Y1_LV0_SedanH)); + M_MEMCOPY((g_assDTG_FU_AMB_Y2_LV0), (c_assDTG_FU_AMB_Y2_LV0_SedanH)); + M_MEMCOPY((g_assDTG_FU_AMB_X1_LV0), (c_assDTG_FU_AMB_X1_LV0_SedanH)); + M_MEMCOPY((g_assDTG_FU_AMB_X2_LV0), (c_assDTG_FU_AMB_X2_LV0_SedanH)); + M_MEMCOPY((g_assDTG_FU_SUN_Y1_LV0), (c_assDTG_FU_SUN_Y1_LV0_SedanH)); + M_MEMCOPY((g_assDTG_FU_SUN_Y2_LV0), (c_assDTG_FU_SUN_Y2_LV0_SedanH)); + M_MEMCOPY((g_assDTG_FU_SUN_X1_LV0), (c_assDTG_FU_SUN_X1_LV0_SedanH)); + M_MEMCOPY((g_assDTG_FU_SUN_X2_LV0), (c_assDTG_FU_SUN_X2_LV0_SedanH)); + M_MEMCOPY((g_assTG_FLL_LV0), (c_assTG_FLL_LV0_SedanH)); + M_MEMCOPY((g_assTG_FRL_LV0), (c_assTG_FRL_LV0_SedanH)); + M_MEMCOPY((g_assDTG_FL_MIN_LV0), (c_assDTG_FL_MIN_LV0_SedanH)); + M_MEMCOPY((g_assDTG_FL_MAX_LV0), (c_assDTG_FL_MAX_LV0_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_Y1_LV0), (c_assDTG_FL_INC_Y1_LV0_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_Y2_LV0), (c_assDTG_FL_INC_Y2_LV0_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_Y3_LV0), (c_assDTG_FL_INC_Y3_LV0_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_Y4_LV0), (c_assDTG_FL_INC_Y4_LV0_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_X1_LV0), (c_assDTG_FL_INC_X1_LV0_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_X2_LV0), (c_assDTG_FL_INC_X2_LV0_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_X3_LV0), (c_assDTG_FL_INC_X3_LV0_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_X4_LV0), (c_assDTG_FL_INC_X4_LV0_SedanH)); + M_MEMCOPY((g_assDTG_FL_AMB_Y1_LV0), (c_assDTG_FL_AMB_Y1_LV0_SedanH)); + M_MEMCOPY((g_assDTG_FL_AMB_Y2_LV0), (c_assDTG_FL_AMB_Y2_LV0_SedanH)); + M_MEMCOPY((g_assDTG_FL_AMB_X1_LV0), (c_assDTG_FL_AMB_X1_LV0_SedanH)); + M_MEMCOPY((g_assDTG_FL_AMB_X2_LV0), (c_assDTG_FL_AMB_X2_LV0_SedanH)); + M_MEMCOPY((g_assDTG_FL_SUN_Y1_LV0), (c_assDTG_FL_SUN_Y1_LV0_SedanH)); + M_MEMCOPY((g_assDTG_FL_SUN_Y2_LV0), (c_assDTG_FL_SUN_Y2_LV0_SedanH)); + M_MEMCOPY((g_assDTG_FL_SUN_X1_LV0), (c_assDTG_FL_SUN_X1_LV0_SedanH)); + M_MEMCOPY((g_assDTG_FL_SUN_X2_LV0), (c_assDTG_FL_SUN_X2_LV0_SedanH)); + M_MEMCOPY((g_assINCAR_TG_RL_LV0), (c_assINCAR_TG_RL_LV0_SedanH)); + M_MEMCOPY((g_assINCAR_TG_RR_LV0), (c_assINCAR_TG_RR_LV0_SedanH)); + M_MEMCOPY((g_assVTG_RL_LV0), (c_assVTG_RL_LV0_SedanH)); + M_MEMCOPY((g_assVTG_RR_LV0), (c_assVTG_RR_LV0_SedanH)); + M_MEMCOPY((g_assVR_MIN_LV0), (c_assVR_MIN_LV0_SedanH)); + M_MEMCOPY((g_assVR_MAX_LV0), (c_assVR_MAX_LV0_SedanH)); + M_MEMCOPY((g_assVR_INC_Y1_LV0), (c_assVR_INC_Y1_LV0_SedanH)); + M_MEMCOPY((g_assVR_INC_Y2_LV0), (c_assVR_INC_Y2_LV0_SedanH)); + M_MEMCOPY((g_assVR_INC_Y3_LV0), (c_assVR_INC_Y3_LV0_SedanH)); + M_MEMCOPY((g_assVR_INC_Y4_LV0), (c_assVR_INC_Y4_LV0_SedanH)); + M_MEMCOPY((g_assVR_INC_X1_LV0), (c_assVR_INC_X1_LV0_SedanH)); + M_MEMCOPY((g_assVR_INC_X2_LV0), (c_assVR_INC_X2_LV0_SedanH)); + M_MEMCOPY((g_assVR_INC_X3_LV0), (c_assVR_INC_X3_LV0_SedanH)); + M_MEMCOPY((g_assVR_INC_X4_LV0), (c_assVR_INC_X4_LV0_SedanH)); + M_MEMCOPY((g_assVR_AMB_Y1_LV0), (c_assVR_AMB_Y1_LV0_SedanH)); + M_MEMCOPY((g_assVR_AMB_Y2_LV0), (c_assVR_AMB_Y2_LV0_SedanH)); + M_MEMCOPY((g_assVR_AMB_X1_LV0), (c_assVR_AMB_X1_LV0_SedanH)); + M_MEMCOPY((g_assVR_AMB_X2_LV0), (c_assVR_AMB_X2_LV0_SedanH)); + M_MEMCOPY((g_assVR_SUN_Y1_LV0), (c_assVR_SUN_Y1_LV0_SedanH)); + M_MEMCOPY((g_assVR_SUN_Y2_LV0), (c_assVR_SUN_Y2_LV0_SedanH)); + M_MEMCOPY((g_assVR_SUN_X1_LV0), (c_assVR_SUN_X1_LV0_SedanH)); + M_MEMCOPY((g_assVR_SUN_X2_LV0), (c_assVR_SUN_X2_LV0_SedanH)); + M_MEMCOPY((g_assTG_RL_LV0), (c_assTG_RL_LV0_SedanH)); + M_MEMCOPY((g_assTG_RR_LV0), (c_assTG_RR_LV0_SedanH)); + M_MEMCOPY((g_assDTG_R_MIN_LV0), (c_assDTG_R_MIN_LV0_SedanH)); + M_MEMCOPY((g_assDTG_R_MAX_LV0), (c_assDTG_R_MAX_LV0_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_Y1_LV0), (c_assDTG_R_INC_Y1_LV0_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_Y2_LV0), (c_assDTG_R_INC_Y2_LV0_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_Y3_LV0), (c_assDTG_R_INC_Y3_LV0_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_Y4_LV0), (c_assDTG_R_INC_Y4_LV0_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_X1_LV0), (c_assDTG_R_INC_X1_LV0_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_X2_LV0), (c_assDTG_R_INC_X2_LV0_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_X3_LV0), (c_assDTG_R_INC_X3_LV0_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_X4_LV0), (c_assDTG_R_INC_X4_LV0_SedanH)); + M_MEMCOPY((g_assDTG_R_AMB_Y1_LV0), (c_assDTG_R_AMB_Y1_LV0_SedanH)); + M_MEMCOPY((g_assDTG_R_AMB_Y2_LV0), (c_assDTG_R_AMB_Y2_LV0_SedanH)); + M_MEMCOPY((g_assDTG_R_AMB_X1_LV0), (c_assDTG_R_AMB_X1_LV0_SedanH)); + M_MEMCOPY((g_assDTG_R_AMB_X2_LV0), (c_assDTG_R_AMB_X2_LV0_SedanH)); + M_MEMCOPY((g_assDTG_R_SUN_Y1_LV0), (c_assDTG_R_SUN_Y1_LV0_SedanH)); + M_MEMCOPY((g_assDTG_R_SUN_Y2_LV0), (c_assDTG_R_SUN_Y2_LV0_SedanH)); + M_MEMCOPY((g_assDTG_R_SUN_X1_LV0), (c_assDTG_R_SUN_X1_LV0_SedanH)); + M_MEMCOPY((g_assDTG_R_SUN_X2_LV0), (c_assDTG_R_SUN_X2_LV0_SedanH)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FR_LV0), (c_assCORRECT_DUCT_TIME_FR_LV0_SedanH)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FL_LV0), (c_assCORRECT_DUCT_TIME_FL_LV0_SedanH)); + M_MEMCOPY((g_assCORRECT_DUCT_RATE_LV0), (c_assCORRECT_DUCT_RATE_LV0_SedanH)); + M_MEMCOPY((g_assCORRECT_DUCT_MAX_LV0), (c_assCORRECT_DUCT_MAX_LV0_SedanH)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FR_LV0), (c_assCORRECT_AF_TIME_FR_LV0_SedanH)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FL_LV0), (c_assCORRECT_AF_TIME_FL_LV0_SedanH)); + M_MEMCOPY((g_assCORRECT_AF_RATE_LV0), (c_assCORRECT_AF_RATE_LV0_SedanH)); + M_MEMCOPY((g_assCORRECT_AF_MAX_LV0), (c_assCORRECT_AF_MAX_LV0_SedanH)); +/* ------------------------------------------Lv0 : End*/ + M_MEMCOPY((g_assINCAR_TG_FL_LV1), (c_assINCAR_TG_FL_LV1_SedanH)); + M_MEMCOPY((g_assINCAR_TG_FR_LV1), (c_assINCAR_TG_FR_LV1_SedanH)); + M_MEMCOPY((g_assVTG_FL_LV1), (c_assVTG_FL_LV1_SedanH)); + M_MEMCOPY((g_assVTG_FR_LV1), (c_assVTG_FR_LV1_SedanH)); + M_MEMCOPY((g_assVF_MIN_LV1), (c_assVF_MIN_LV1_SedanH)); + M_MEMCOPY((g_assVF_MAX_LV1), (c_assVF_MAX_LV1_SedanH)); + M_MEMCOPY((g_assVF_INC_Y1_LV1), (c_assVF_INC_Y1_LV1_SedanH)); + M_MEMCOPY((g_assVF_INC_Y2_LV1), (c_assVF_INC_Y2_LV1_SedanH)); + M_MEMCOPY((g_assVF_INC_Y3_LV1), (c_assVF_INC_Y3_LV1_SedanH)); + M_MEMCOPY((g_assVF_INC_Y4_LV1), (c_assVF_INC_Y4_LV1_SedanH)); + M_MEMCOPY((g_assVF_INC_X1_LV1), (c_assVF_INC_X1_LV1_SedanH)); + M_MEMCOPY((g_assVF_INC_X2_LV1), (c_assVF_INC_X2_LV1_SedanH)); + M_MEMCOPY((g_assVF_INC_X3_LV1), (c_assVF_INC_X3_LV1_SedanH)); + M_MEMCOPY((g_assVF_INC_X4_LV1), (c_assVF_INC_X4_LV1_SedanH)); + M_MEMCOPY((g_assVF_AMB_Y1_LV1), (c_assVF_AMB_Y1_LV1_SedanH)); + M_MEMCOPY((g_assVF_AMB_Y2_LV1), (c_assVF_AMB_Y2_LV1_SedanH)); + M_MEMCOPY((g_assVF_AMB_X1_LV1), (c_assVF_AMB_X1_LV1_SedanH)); + M_MEMCOPY((g_assVF_AMB_X2_LV1), (c_assVF_AMB_X2_LV1_SedanH)); + M_MEMCOPY((g_assVF_SUN_Y1_LV1), (c_assVF_SUN_Y1_LV1_SedanH)); + M_MEMCOPY((g_assVF_SUN_Y2_LV1), (c_assVF_SUN_Y2_LV1_SedanH)); + M_MEMCOPY((g_assVF_SUN_X1_LV1), (c_assVF_SUN_X1_LV1_SedanH)); + M_MEMCOPY((g_assVF_SUN_X2_LV1), (c_assVF_SUN_X2_LV1_SedanH)); + M_MEMCOPY((g_assTG_FLU_LV1), (c_assTG_FLU_LV1_SedanH)); + M_MEMCOPY((g_assTG_FRU_LV1), (c_assTG_FRU_LV1_SedanH)); + M_MEMCOPY((g_assDTG_FU_MIN_LV1), (c_assDTG_FU_MIN_LV1_SedanH)); + M_MEMCOPY((g_assDTG_FU_MAX_LV1), (c_assDTG_FU_MAX_LV1_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_Y1_LV1), (c_assDTG_FU_INC_Y1_LV1_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_Y2_LV1), (c_assDTG_FU_INC_Y2_LV1_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_Y3_LV1), (c_assDTG_FU_INC_Y3_LV1_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_Y4_LV1), (c_assDTG_FU_INC_Y4_LV1_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_X1_LV1), (c_assDTG_FU_INC_X1_LV1_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_X2_LV1), (c_assDTG_FU_INC_X2_LV1_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_X3_LV1), (c_assDTG_FU_INC_X3_LV1_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_X4_LV1), (c_assDTG_FU_INC_X4_LV1_SedanH)); + M_MEMCOPY((g_assDTG_FU_AMB_Y1_LV1), (c_assDTG_FU_AMB_Y1_LV1_SedanH)); + M_MEMCOPY((g_assDTG_FU_AMB_Y2_LV1), (c_assDTG_FU_AMB_Y2_LV1_SedanH)); + M_MEMCOPY((g_assDTG_FU_AMB_X1_LV1), (c_assDTG_FU_AMB_X1_LV1_SedanH)); + M_MEMCOPY((g_assDTG_FU_AMB_X2_LV1), (c_assDTG_FU_AMB_X2_LV1_SedanH)); + M_MEMCOPY((g_assDTG_FU_SUN_Y1_LV1), (c_assDTG_FU_SUN_Y1_LV1_SedanH)); + M_MEMCOPY((g_assDTG_FU_SUN_Y2_LV1), (c_assDTG_FU_SUN_Y2_LV1_SedanH)); + M_MEMCOPY((g_assDTG_FU_SUN_X1_LV1), (c_assDTG_FU_SUN_X1_LV1_SedanH)); + M_MEMCOPY((g_assDTG_FU_SUN_X2_LV1), (c_assDTG_FU_SUN_X2_LV1_SedanH)); + M_MEMCOPY((g_assTG_FLL_LV1), (c_assTG_FLL_LV1_SedanH)); + M_MEMCOPY((g_assTG_FRL_LV1), (c_assTG_FRL_LV1_SedanH)); + M_MEMCOPY((g_assDTG_FL_MIN_LV1), (c_assDTG_FL_MIN_LV1_SedanH)); + M_MEMCOPY((g_assDTG_FL_MAX_LV1), (c_assDTG_FL_MAX_LV1_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_Y1_LV1), (c_assDTG_FL_INC_Y1_LV1_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_Y2_LV1), (c_assDTG_FL_INC_Y2_LV1_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_Y3_LV1), (c_assDTG_FL_INC_Y3_LV1_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_Y4_LV1), (c_assDTG_FL_INC_Y4_LV1_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_X1_LV1), (c_assDTG_FL_INC_X1_LV1_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_X2_LV1), (c_assDTG_FL_INC_X2_LV1_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_X3_LV1), (c_assDTG_FL_INC_X3_LV1_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_X4_LV1), (c_assDTG_FL_INC_X4_LV1_SedanH)); + M_MEMCOPY((g_assDTG_FL_AMB_Y1_LV1), (c_assDTG_FL_AMB_Y1_LV1_SedanH)); + M_MEMCOPY((g_assDTG_FL_AMB_Y2_LV1), (c_assDTG_FL_AMB_Y2_LV1_SedanH)); + M_MEMCOPY((g_assDTG_FL_AMB_X1_LV1), (c_assDTG_FL_AMB_X1_LV1_SedanH)); + M_MEMCOPY((g_assDTG_FL_AMB_X2_LV1), (c_assDTG_FL_AMB_X2_LV1_SedanH)); + M_MEMCOPY((g_assDTG_FL_SUN_Y1_LV1), (c_assDTG_FL_SUN_Y1_LV1_SedanH)); + M_MEMCOPY((g_assDTG_FL_SUN_Y2_LV1), (c_assDTG_FL_SUN_Y2_LV1_SedanH)); + M_MEMCOPY((g_assDTG_FL_SUN_X1_LV1), (c_assDTG_FL_SUN_X1_LV1_SedanH)); + M_MEMCOPY((g_assDTG_FL_SUN_X2_LV1), (c_assDTG_FL_SUN_X2_LV1_SedanH)); + M_MEMCOPY((g_assINCAR_TG_RL_LV1), (c_assINCAR_TG_RL_LV1_SedanH)); + M_MEMCOPY((g_assINCAR_TG_RR_LV1), (c_assINCAR_TG_RR_LV1_SedanH)); + M_MEMCOPY((g_assVTG_RL_LV1), (c_assVTG_RL_LV1_SedanH)); + M_MEMCOPY((g_assVTG_RR_LV1), (c_assVTG_RR_LV1_SedanH)); + M_MEMCOPY((g_assVR_MIN_LV1), (c_assVR_MIN_LV1_SedanH)); + M_MEMCOPY((g_assVR_MAX_LV1), (c_assVR_MAX_LV1_SedanH)); + M_MEMCOPY((g_assVR_INC_Y1_LV1), (c_assVR_INC_Y1_LV1_SedanH)); + M_MEMCOPY((g_assVR_INC_Y2_LV1), (c_assVR_INC_Y2_LV1_SedanH)); + M_MEMCOPY((g_assVR_INC_Y3_LV1), (c_assVR_INC_Y3_LV1_SedanH)); + M_MEMCOPY((g_assVR_INC_Y4_LV1), (c_assVR_INC_Y4_LV1_SedanH)); + M_MEMCOPY((g_assVR_INC_X1_LV1), (c_assVR_INC_X1_LV1_SedanH)); + M_MEMCOPY((g_assVR_INC_X2_LV1), (c_assVR_INC_X2_LV1_SedanH)); + M_MEMCOPY((g_assVR_INC_X3_LV1), (c_assVR_INC_X3_LV1_SedanH)); + M_MEMCOPY((g_assVR_INC_X4_LV1), (c_assVR_INC_X4_LV1_SedanH)); + M_MEMCOPY((g_assVR_AMB_Y1_LV1), (c_assVR_AMB_Y1_LV1_SedanH)); + M_MEMCOPY((g_assVR_AMB_Y2_LV1), (c_assVR_AMB_Y2_LV1_SedanH)); + M_MEMCOPY((g_assVR_AMB_X1_LV1), (c_assVR_AMB_X1_LV1_SedanH)); + M_MEMCOPY((g_assVR_AMB_X2_LV1), (c_assVR_AMB_X2_LV1_SedanH)); + M_MEMCOPY((g_assVR_SUN_Y1_LV1), (c_assVR_SUN_Y1_LV1_SedanH)); + M_MEMCOPY((g_assVR_SUN_Y2_LV1), (c_assVR_SUN_Y2_LV1_SedanH)); + M_MEMCOPY((g_assVR_SUN_X1_LV1), (c_assVR_SUN_X1_LV1_SedanH)); + M_MEMCOPY((g_assVR_SUN_X2_LV1), (c_assVR_SUN_X2_LV1_SedanH)); + M_MEMCOPY((g_assTG_RL_LV1), (c_assTG_RL_LV1_SedanH)); + M_MEMCOPY((g_assTG_RR_LV1), (c_assTG_RR_LV1_SedanH)); + M_MEMCOPY((g_assDTG_R_MIN_LV1), (c_assDTG_R_MIN_LV1_SedanH)); + M_MEMCOPY((g_assDTG_R_MAX_LV1), (c_assDTG_R_MAX_LV1_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_Y1_LV1), (c_assDTG_R_INC_Y1_LV1_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_Y2_LV1), (c_assDTG_R_INC_Y2_LV1_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_Y3_LV1), (c_assDTG_R_INC_Y3_LV1_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_Y4_LV1), (c_assDTG_R_INC_Y4_LV1_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_X1_LV1), (c_assDTG_R_INC_X1_LV1_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_X2_LV1), (c_assDTG_R_INC_X2_LV1_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_X3_LV1), (c_assDTG_R_INC_X3_LV1_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_X4_LV1), (c_assDTG_R_INC_X4_LV1_SedanH)); + M_MEMCOPY((g_assDTG_R_AMB_Y1_LV1), (c_assDTG_R_AMB_Y1_LV1_SedanH)); + M_MEMCOPY((g_assDTG_R_AMB_Y2_LV1), (c_assDTG_R_AMB_Y2_LV1_SedanH)); + M_MEMCOPY((g_assDTG_R_AMB_X1_LV1), (c_assDTG_R_AMB_X1_LV1_SedanH)); + M_MEMCOPY((g_assDTG_R_AMB_X2_LV1), (c_assDTG_R_AMB_X2_LV1_SedanH)); + M_MEMCOPY((g_assDTG_R_SUN_Y1_LV1), (c_assDTG_R_SUN_Y1_LV1_SedanH)); + M_MEMCOPY((g_assDTG_R_SUN_Y2_LV1), (c_assDTG_R_SUN_Y2_LV1_SedanH)); + M_MEMCOPY((g_assDTG_R_SUN_X1_LV1), (c_assDTG_R_SUN_X1_LV1_SedanH)); + M_MEMCOPY((g_assDTG_R_SUN_X2_LV1), (c_assDTG_R_SUN_X2_LV1_SedanH)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FR_LV1), (c_assCORRECT_DUCT_TIME_FR_LV1_SedanH)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FL_LV1), (c_assCORRECT_DUCT_TIME_FL_LV1_SedanH)); + M_MEMCOPY((g_assCORRECT_DUCT_RATE_LV1), (c_assCORRECT_DUCT_RATE_LV1_SedanH)); + M_MEMCOPY((g_assCORRECT_DUCT_MAX_LV1), (c_assCORRECT_DUCT_MAX_LV1_SedanH)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FR_LV1), (c_assCORRECT_AF_TIME_FR_LV1_SedanH)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FL_LV1), (c_assCORRECT_AF_TIME_FL_LV1_SedanH)); + M_MEMCOPY((g_assCORRECT_AF_RATE_LV1), (c_assCORRECT_AF_RATE_LV1_SedanH)); + M_MEMCOPY((g_assCORRECT_AF_MAX_LV1), (c_assCORRECT_AF_MAX_LV1_SedanH)); +/* ------------------------------------------Lv1 : End*/ + M_MEMCOPY((g_assINCAR_TG_FL_LV2), (c_assINCAR_TG_FL_LV2_SedanH)); + M_MEMCOPY((g_assINCAR_TG_FR_LV2), (c_assINCAR_TG_FR_LV2_SedanH)); + M_MEMCOPY((g_assVTG_FL_LV2), (c_assVTG_FL_LV2_SedanH)); + M_MEMCOPY((g_assVTG_FR_LV2), (c_assVTG_FR_LV2_SedanH)); + M_MEMCOPY((g_assVF_MIN_LV2), (c_assVF_MIN_LV2_SedanH)); + M_MEMCOPY((g_assVF_MAX_LV2), (c_assVF_MAX_LV2_SedanH)); + M_MEMCOPY((g_assVF_INC_Y1_LV2), (c_assVF_INC_Y1_LV2_SedanH)); + M_MEMCOPY((g_assVF_INC_Y2_LV2), (c_assVF_INC_Y2_LV2_SedanH)); + M_MEMCOPY((g_assVF_INC_Y3_LV2), (c_assVF_INC_Y3_LV2_SedanH)); + M_MEMCOPY((g_assVF_INC_Y4_LV2), (c_assVF_INC_Y4_LV2_SedanH)); + M_MEMCOPY((g_assVF_INC_X1_LV2), (c_assVF_INC_X1_LV2_SedanH)); + M_MEMCOPY((g_assVF_INC_X2_LV2), (c_assVF_INC_X2_LV2_SedanH)); + M_MEMCOPY((g_assVF_INC_X3_LV2), (c_assVF_INC_X3_LV2_SedanH)); + M_MEMCOPY((g_assVF_INC_X4_LV2), (c_assVF_INC_X4_LV2_SedanH)); + M_MEMCOPY((g_assVF_AMB_Y1_LV2), (c_assVF_AMB_Y1_LV2_SedanH)); + M_MEMCOPY((g_assVF_AMB_Y2_LV2), (c_assVF_AMB_Y2_LV2_SedanH)); + M_MEMCOPY((g_assVF_AMB_X1_LV2), (c_assVF_AMB_X1_LV2_SedanH)); + M_MEMCOPY((g_assVF_AMB_X2_LV2), (c_assVF_AMB_X2_LV2_SedanH)); + M_MEMCOPY((g_assVF_SUN_Y1_LV2), (c_assVF_SUN_Y1_LV2_SedanH)); + M_MEMCOPY((g_assVF_SUN_Y2_LV2), (c_assVF_SUN_Y2_LV2_SedanH)); + M_MEMCOPY((g_assVF_SUN_X1_LV2), (c_assVF_SUN_X1_LV2_SedanH)); + M_MEMCOPY((g_assVF_SUN_X2_LV2), (c_assVF_SUN_X2_LV2_SedanH)); + M_MEMCOPY((g_assTG_FLU_LV2), (c_assTG_FLU_LV2_SedanH)); + M_MEMCOPY((g_assTG_FRU_LV2), (c_assTG_FRU_LV2_SedanH)); + M_MEMCOPY((g_assDTG_FU_MIN_LV2), (c_assDTG_FU_MIN_LV2_SedanH)); + M_MEMCOPY((g_assDTG_FU_MAX_LV2), (c_assDTG_FU_MAX_LV2_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_Y1_LV2), (c_assDTG_FU_INC_Y1_LV2_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_Y2_LV2), (c_assDTG_FU_INC_Y2_LV2_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_Y3_LV2), (c_assDTG_FU_INC_Y3_LV2_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_Y4_LV2), (c_assDTG_FU_INC_Y4_LV2_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_X1_LV2), (c_assDTG_FU_INC_X1_LV2_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_X2_LV2), (c_assDTG_FU_INC_X2_LV2_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_X3_LV2), (c_assDTG_FU_INC_X3_LV2_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_X4_LV2), (c_assDTG_FU_INC_X4_LV2_SedanH)); + M_MEMCOPY((g_assDTG_FU_AMB_Y1_LV2), (c_assDTG_FU_AMB_Y1_LV2_SedanH)); + M_MEMCOPY((g_assDTG_FU_AMB_Y2_LV2), (c_assDTG_FU_AMB_Y2_LV2_SedanH)); + M_MEMCOPY((g_assDTG_FU_AMB_X1_LV2), (c_assDTG_FU_AMB_X1_LV2_SedanH)); + M_MEMCOPY((g_assDTG_FU_AMB_X2_LV2), (c_assDTG_FU_AMB_X2_LV2_SedanH)); + M_MEMCOPY((g_assDTG_FU_SUN_Y1_LV2), (c_assDTG_FU_SUN_Y1_LV2_SedanH)); + M_MEMCOPY((g_assDTG_FU_SUN_Y2_LV2), (c_assDTG_FU_SUN_Y2_LV2_SedanH)); + M_MEMCOPY((g_assDTG_FU_SUN_X1_LV2), (c_assDTG_FU_SUN_X1_LV2_SedanH)); + M_MEMCOPY((g_assDTG_FU_SUN_X2_LV2), (c_assDTG_FU_SUN_X2_LV2_SedanH)); + M_MEMCOPY((g_assTG_FLL_LV2), (c_assTG_FLL_LV2_SedanH)); + M_MEMCOPY((g_assTG_FRL_LV2), (c_assTG_FRL_LV2_SedanH)); + M_MEMCOPY((g_assDTG_FL_MIN_LV2), (c_assDTG_FL_MIN_LV2_SedanH)); + M_MEMCOPY((g_assDTG_FL_MAX_LV2), (c_assDTG_FL_MAX_LV2_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_Y1_LV2), (c_assDTG_FL_INC_Y1_LV2_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_Y2_LV2), (c_assDTG_FL_INC_Y2_LV2_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_Y3_LV2), (c_assDTG_FL_INC_Y3_LV2_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_Y4_LV2), (c_assDTG_FL_INC_Y4_LV2_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_X1_LV2), (c_assDTG_FL_INC_X1_LV2_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_X2_LV2), (c_assDTG_FL_INC_X2_LV2_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_X3_LV2), (c_assDTG_FL_INC_X3_LV2_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_X4_LV2), (c_assDTG_FL_INC_X4_LV2_SedanH)); + M_MEMCOPY((g_assDTG_FL_AMB_Y1_LV2), (c_assDTG_FL_AMB_Y1_LV2_SedanH)); + M_MEMCOPY((g_assDTG_FL_AMB_Y2_LV2), (c_assDTG_FL_AMB_Y2_LV2_SedanH)); + M_MEMCOPY((g_assDTG_FL_AMB_X1_LV2), (c_assDTG_FL_AMB_X1_LV2_SedanH)); + M_MEMCOPY((g_assDTG_FL_AMB_X2_LV2), (c_assDTG_FL_AMB_X2_LV2_SedanH)); + M_MEMCOPY((g_assDTG_FL_SUN_Y1_LV2), (c_assDTG_FL_SUN_Y1_LV2_SedanH)); + M_MEMCOPY((g_assDTG_FL_SUN_Y2_LV2), (c_assDTG_FL_SUN_Y2_LV2_SedanH)); + M_MEMCOPY((g_assDTG_FL_SUN_X1_LV2), (c_assDTG_FL_SUN_X1_LV2_SedanH)); + M_MEMCOPY((g_assDTG_FL_SUN_X2_LV2), (c_assDTG_FL_SUN_X2_LV2_SedanH)); + M_MEMCOPY((g_assINCAR_TG_RL_LV2), (c_assINCAR_TG_RL_LV2_SedanH)); + M_MEMCOPY((g_assINCAR_TG_RR_LV2), (c_assINCAR_TG_RR_LV2_SedanH)); + M_MEMCOPY((g_assVTG_RL_LV2), (c_assVTG_RL_LV2_SedanH)); + M_MEMCOPY((g_assVTG_RR_LV2), (c_assVTG_RR_LV2_SedanH)); + M_MEMCOPY((g_assVR_MIN_LV2), (c_assVR_MIN_LV2_SedanH)); + M_MEMCOPY((g_assVR_MAX_LV2), (c_assVR_MAX_LV2_SedanH)); + M_MEMCOPY((g_assVR_INC_Y1_LV2), (c_assVR_INC_Y1_LV2_SedanH)); + M_MEMCOPY((g_assVR_INC_Y2_LV2), (c_assVR_INC_Y2_LV2_SedanH)); + M_MEMCOPY((g_assVR_INC_Y3_LV2), (c_assVR_INC_Y3_LV2_SedanH)); + M_MEMCOPY((g_assVR_INC_Y4_LV2), (c_assVR_INC_Y4_LV2_SedanH)); + M_MEMCOPY((g_assVR_INC_X1_LV2), (c_assVR_INC_X1_LV2_SedanH)); + M_MEMCOPY((g_assVR_INC_X2_LV2), (c_assVR_INC_X2_LV2_SedanH)); + M_MEMCOPY((g_assVR_INC_X3_LV2), (c_assVR_INC_X3_LV2_SedanH)); + M_MEMCOPY((g_assVR_INC_X4_LV2), (c_assVR_INC_X4_LV2_SedanH)); + M_MEMCOPY((g_assVR_AMB_Y1_LV2), (c_assVR_AMB_Y1_LV2_SedanH)); + M_MEMCOPY((g_assVR_AMB_Y2_LV2), (c_assVR_AMB_Y2_LV2_SedanH)); + M_MEMCOPY((g_assVR_AMB_X1_LV2), (c_assVR_AMB_X1_LV2_SedanH)); + M_MEMCOPY((g_assVR_AMB_X2_LV2), (c_assVR_AMB_X2_LV2_SedanH)); + M_MEMCOPY((g_assVR_SUN_Y1_LV2), (c_assVR_SUN_Y1_LV2_SedanH)); + M_MEMCOPY((g_assVR_SUN_Y2_LV2), (c_assVR_SUN_Y2_LV2_SedanH)); + M_MEMCOPY((g_assVR_SUN_X1_LV2), (c_assVR_SUN_X1_LV2_SedanH)); + M_MEMCOPY((g_assVR_SUN_X2_LV2), (c_assVR_SUN_X2_LV2_SedanH)); + M_MEMCOPY((g_assTG_RL_LV2), (c_assTG_RL_LV2_SedanH)); + M_MEMCOPY((g_assTG_RR_LV2), (c_assTG_RR_LV2_SedanH)); + M_MEMCOPY((g_assDTG_R_MIN_LV2), (c_assDTG_R_MIN_LV2_SedanH)); + M_MEMCOPY((g_assDTG_R_MAX_LV2), (c_assDTG_R_MAX_LV2_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_Y1_LV2), (c_assDTG_R_INC_Y1_LV2_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_Y2_LV2), (c_assDTG_R_INC_Y2_LV2_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_Y3_LV2), (c_assDTG_R_INC_Y3_LV2_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_Y4_LV2), (c_assDTG_R_INC_Y4_LV2_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_X1_LV2), (c_assDTG_R_INC_X1_LV2_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_X2_LV2), (c_assDTG_R_INC_X2_LV2_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_X3_LV2), (c_assDTG_R_INC_X3_LV2_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_X4_LV2), (c_assDTG_R_INC_X4_LV2_SedanH)); + M_MEMCOPY((g_assDTG_R_AMB_Y1_LV2), (c_assDTG_R_AMB_Y1_LV2_SedanH)); + M_MEMCOPY((g_assDTG_R_AMB_Y2_LV2), (c_assDTG_R_AMB_Y2_LV2_SedanH)); + M_MEMCOPY((g_assDTG_R_AMB_X1_LV2), (c_assDTG_R_AMB_X1_LV2_SedanH)); + M_MEMCOPY((g_assDTG_R_AMB_X2_LV2), (c_assDTG_R_AMB_X2_LV2_SedanH)); + M_MEMCOPY((g_assDTG_R_SUN_Y1_LV2), (c_assDTG_R_SUN_Y1_LV2_SedanH)); + M_MEMCOPY((g_assDTG_R_SUN_Y2_LV2), (c_assDTG_R_SUN_Y2_LV2_SedanH)); + M_MEMCOPY((g_assDTG_R_SUN_X1_LV2), (c_assDTG_R_SUN_X1_LV2_SedanH)); + M_MEMCOPY((g_assDTG_R_SUN_X2_LV2), (c_assDTG_R_SUN_X2_LV2_SedanH)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FR_LV2), (c_assCORRECT_DUCT_TIME_FR_LV2_SedanH)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FL_LV2), (c_assCORRECT_DUCT_TIME_FL_LV2_SedanH)); + M_MEMCOPY((g_assCORRECT_DUCT_RATE_LV2), (c_assCORRECT_DUCT_RATE_LV2_SedanH)); + M_MEMCOPY((g_assCORRECT_DUCT_MAX_LV2), (c_assCORRECT_DUCT_MAX_LV2_SedanH)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FR_LV2), (c_assCORRECT_AF_TIME_FR_LV2_SedanH)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FL_LV2), (c_assCORRECT_AF_TIME_FL_LV2_SedanH)); + M_MEMCOPY((g_assCORRECT_AF_RATE_LV2), (c_assCORRECT_AF_RATE_LV2_SedanH)); + M_MEMCOPY((g_assCORRECT_AF_MAX_LV2), (c_assCORRECT_AF_MAX_LV2_SedanH)); +/* ------------------------------------------Lv2 : End*/ + M_MEMCOPY((g_assINCAR_TG_FL_LV3), (c_assINCAR_TG_FL_LV3_SedanH)); + M_MEMCOPY((g_assINCAR_TG_FR_LV3), (c_assINCAR_TG_FR_LV3_SedanH)); + M_MEMCOPY((g_assVTG_FL_LV3), (c_assVTG_FL_LV3_SedanH)); + M_MEMCOPY((g_assVTG_FR_LV3), (c_assVTG_FR_LV3_SedanH)); + M_MEMCOPY((g_assVF_MIN_LV3), (c_assVF_MIN_LV3_SedanH)); + M_MEMCOPY((g_assVF_MAX_LV3), (c_assVF_MAX_LV3_SedanH)); + M_MEMCOPY((g_assVF_INC_Y1_LV3), (c_assVF_INC_Y1_LV3_SedanH)); + M_MEMCOPY((g_assVF_INC_Y2_LV3), (c_assVF_INC_Y2_LV3_SedanH)); + M_MEMCOPY((g_assVF_INC_Y3_LV3), (c_assVF_INC_Y3_LV3_SedanH)); + M_MEMCOPY((g_assVF_INC_Y4_LV3), (c_assVF_INC_Y4_LV3_SedanH)); + M_MEMCOPY((g_assVF_INC_X1_LV3), (c_assVF_INC_X1_LV3_SedanH)); + M_MEMCOPY((g_assVF_INC_X2_LV3), (c_assVF_INC_X2_LV3_SedanH)); + M_MEMCOPY((g_assVF_INC_X3_LV3), (c_assVF_INC_X3_LV3_SedanH)); + M_MEMCOPY((g_assVF_INC_X4_LV3), (c_assVF_INC_X4_LV3_SedanH)); + M_MEMCOPY((g_assVF_AMB_Y1_LV3), (c_assVF_AMB_Y1_LV3_SedanH)); + M_MEMCOPY((g_assVF_AMB_Y2_LV3), (c_assVF_AMB_Y2_LV3_SedanH)); + M_MEMCOPY((g_assVF_AMB_X1_LV3), (c_assVF_AMB_X1_LV3_SedanH)); + M_MEMCOPY((g_assVF_AMB_X2_LV3), (c_assVF_AMB_X2_LV3_SedanH)); + M_MEMCOPY((g_assVF_SUN_Y1_LV3), (c_assVF_SUN_Y1_LV3_SedanH)); + M_MEMCOPY((g_assVF_SUN_Y2_LV3), (c_assVF_SUN_Y2_LV3_SedanH)); + M_MEMCOPY((g_assVF_SUN_X1_LV3), (c_assVF_SUN_X1_LV3_SedanH)); + M_MEMCOPY((g_assVF_SUN_X2_LV3), (c_assVF_SUN_X2_LV3_SedanH)); + M_MEMCOPY((g_assTG_FLU_LV3), (c_assTG_FLU_LV3_SedanH)); + M_MEMCOPY((g_assTG_FRU_LV3), (c_assTG_FRU_LV3_SedanH)); + M_MEMCOPY((g_assDTG_FU_MIN_LV3), (c_assDTG_FU_MIN_LV3_SedanH)); + M_MEMCOPY((g_assDTG_FU_MAX_LV3), (c_assDTG_FU_MAX_LV3_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_Y1_LV3), (c_assDTG_FU_INC_Y1_LV3_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_Y2_LV3), (c_assDTG_FU_INC_Y2_LV3_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_Y3_LV3), (c_assDTG_FU_INC_Y3_LV3_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_Y4_LV3), (c_assDTG_FU_INC_Y4_LV3_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_X1_LV3), (c_assDTG_FU_INC_X1_LV3_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_X2_LV3), (c_assDTG_FU_INC_X2_LV3_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_X3_LV3), (c_assDTG_FU_INC_X3_LV3_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_X4_LV3), (c_assDTG_FU_INC_X4_LV3_SedanH)); + M_MEMCOPY((g_assDTG_FU_AMB_Y1_LV3), (c_assDTG_FU_AMB_Y1_LV3_SedanH)); + M_MEMCOPY((g_assDTG_FU_AMB_Y2_LV3), (c_assDTG_FU_AMB_Y2_LV3_SedanH)); + M_MEMCOPY((g_assDTG_FU_AMB_X1_LV3), (c_assDTG_FU_AMB_X1_LV3_SedanH)); + M_MEMCOPY((g_assDTG_FU_AMB_X2_LV3), (c_assDTG_FU_AMB_X2_LV3_SedanH)); + M_MEMCOPY((g_assDTG_FU_SUN_Y1_LV3), (c_assDTG_FU_SUN_Y1_LV3_SedanH)); + M_MEMCOPY((g_assDTG_FU_SUN_Y2_LV3), (c_assDTG_FU_SUN_Y2_LV3_SedanH)); + M_MEMCOPY((g_assDTG_FU_SUN_X1_LV3), (c_assDTG_FU_SUN_X1_LV3_SedanH)); + M_MEMCOPY((g_assDTG_FU_SUN_X2_LV3), (c_assDTG_FU_SUN_X2_LV3_SedanH)); + M_MEMCOPY((g_assTG_FLL_LV3), (c_assTG_FLL_LV3_SedanH)); + M_MEMCOPY((g_assTG_FRL_LV3), (c_assTG_FRL_LV3_SedanH)); + M_MEMCOPY((g_assDTG_FL_MIN_LV3), (c_assDTG_FL_MIN_LV3_SedanH)); + M_MEMCOPY((g_assDTG_FL_MAX_LV3), (c_assDTG_FL_MAX_LV3_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_Y1_LV3), (c_assDTG_FL_INC_Y1_LV3_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_Y2_LV3), (c_assDTG_FL_INC_Y2_LV3_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_Y3_LV3), (c_assDTG_FL_INC_Y3_LV3_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_Y4_LV3), (c_assDTG_FL_INC_Y4_LV3_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_X1_LV3), (c_assDTG_FL_INC_X1_LV3_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_X2_LV3), (c_assDTG_FL_INC_X2_LV3_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_X3_LV3), (c_assDTG_FL_INC_X3_LV3_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_X4_LV3), (c_assDTG_FL_INC_X4_LV3_SedanH)); + M_MEMCOPY((g_assDTG_FL_AMB_Y1_LV3), (c_assDTG_FL_AMB_Y1_LV3_SedanH)); + M_MEMCOPY((g_assDTG_FL_AMB_Y2_LV3), (c_assDTG_FL_AMB_Y2_LV3_SedanH)); + M_MEMCOPY((g_assDTG_FL_AMB_X1_LV3), (c_assDTG_FL_AMB_X1_LV3_SedanH)); + M_MEMCOPY((g_assDTG_FL_AMB_X2_LV3), (c_assDTG_FL_AMB_X2_LV3_SedanH)); + M_MEMCOPY((g_assDTG_FL_SUN_Y1_LV3), (c_assDTG_FL_SUN_Y1_LV3_SedanH)); + M_MEMCOPY((g_assDTG_FL_SUN_Y2_LV3), (c_assDTG_FL_SUN_Y2_LV3_SedanH)); + M_MEMCOPY((g_assDTG_FL_SUN_X1_LV3), (c_assDTG_FL_SUN_X1_LV3_SedanH)); + M_MEMCOPY((g_assDTG_FL_SUN_X2_LV3), (c_assDTG_FL_SUN_X2_LV3_SedanH)); + M_MEMCOPY((g_assINCAR_TG_RL_LV3), (c_assINCAR_TG_RL_LV3_SedanH)); + M_MEMCOPY((g_assINCAR_TG_RR_LV3), (c_assINCAR_TG_RR_LV3_SedanH)); + M_MEMCOPY((g_assVTG_RL_LV3), (c_assVTG_RL_LV3_SedanH)); + M_MEMCOPY((g_assVTG_RR_LV3), (c_assVTG_RR_LV3_SedanH)); + M_MEMCOPY((g_assVR_MIN_LV3), (c_assVR_MIN_LV3_SedanH)); + M_MEMCOPY((g_assVR_MAX_LV3), (c_assVR_MAX_LV3_SedanH)); + M_MEMCOPY((g_assVR_INC_Y1_LV3), (c_assVR_INC_Y1_LV3_SedanH)); + M_MEMCOPY((g_assVR_INC_Y2_LV3), (c_assVR_INC_Y2_LV3_SedanH)); + M_MEMCOPY((g_assVR_INC_Y3_LV3), (c_assVR_INC_Y3_LV3_SedanH)); + M_MEMCOPY((g_assVR_INC_Y4_LV3), (c_assVR_INC_Y4_LV3_SedanH)); + M_MEMCOPY((g_assVR_INC_X1_LV3), (c_assVR_INC_X1_LV3_SedanH)); + M_MEMCOPY((g_assVR_INC_X2_LV3), (c_assVR_INC_X2_LV3_SedanH)); + M_MEMCOPY((g_assVR_INC_X3_LV3), (c_assVR_INC_X3_LV3_SedanH)); + M_MEMCOPY((g_assVR_INC_X4_LV3), (c_assVR_INC_X4_LV3_SedanH)); + M_MEMCOPY((g_assVR_AMB_Y1_LV3), (c_assVR_AMB_Y1_LV3_SedanH)); + M_MEMCOPY((g_assVR_AMB_Y2_LV3), (c_assVR_AMB_Y2_LV3_SedanH)); + M_MEMCOPY((g_assVR_AMB_X1_LV3), (c_assVR_AMB_X1_LV3_SedanH)); + M_MEMCOPY((g_assVR_AMB_X2_LV3), (c_assVR_AMB_X2_LV3_SedanH)); + M_MEMCOPY((g_assVR_SUN_Y1_LV3), (c_assVR_SUN_Y1_LV3_SedanH)); + M_MEMCOPY((g_assVR_SUN_Y2_LV3), (c_assVR_SUN_Y2_LV3_SedanH)); + M_MEMCOPY((g_assVR_SUN_X1_LV3), (c_assVR_SUN_X1_LV3_SedanH)); + M_MEMCOPY((g_assVR_SUN_X2_LV3), (c_assVR_SUN_X2_LV3_SedanH)); + M_MEMCOPY((g_assTG_RL_LV3), (c_assTG_RL_LV3_SedanH)); + M_MEMCOPY((g_assTG_RR_LV3), (c_assTG_RR_LV3_SedanH)); + M_MEMCOPY((g_assDTG_R_MIN_LV3), (c_assDTG_R_MIN_LV3_SedanH)); + M_MEMCOPY((g_assDTG_R_MAX_LV3), (c_assDTG_R_MAX_LV3_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_Y1_LV3), (c_assDTG_R_INC_Y1_LV3_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_Y2_LV3), (c_assDTG_R_INC_Y2_LV3_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_Y3_LV3), (c_assDTG_R_INC_Y3_LV3_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_Y4_LV3), (c_assDTG_R_INC_Y4_LV3_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_X1_LV3), (c_assDTG_R_INC_X1_LV3_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_X2_LV3), (c_assDTG_R_INC_X2_LV3_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_X3_LV3), (c_assDTG_R_INC_X3_LV3_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_X4_LV3), (c_assDTG_R_INC_X4_LV3_SedanH)); + M_MEMCOPY((g_assDTG_R_AMB_Y1_LV3), (c_assDTG_R_AMB_Y1_LV3_SedanH)); + M_MEMCOPY((g_assDTG_R_AMB_Y2_LV3), (c_assDTG_R_AMB_Y2_LV3_SedanH)); + M_MEMCOPY((g_assDTG_R_AMB_X1_LV3), (c_assDTG_R_AMB_X1_LV3_SedanH)); + M_MEMCOPY((g_assDTG_R_AMB_X2_LV3), (c_assDTG_R_AMB_X2_LV3_SedanH)); + M_MEMCOPY((g_assDTG_R_SUN_Y1_LV3), (c_assDTG_R_SUN_Y1_LV3_SedanH)); + M_MEMCOPY((g_assDTG_R_SUN_Y2_LV3), (c_assDTG_R_SUN_Y2_LV3_SedanH)); + M_MEMCOPY((g_assDTG_R_SUN_X1_LV3), (c_assDTG_R_SUN_X1_LV3_SedanH)); + M_MEMCOPY((g_assDTG_R_SUN_X2_LV3), (c_assDTG_R_SUN_X2_LV3_SedanH)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FR_LV3), (c_assCORRECT_DUCT_TIME_FR_LV3_SedanH)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FL_LV3), (c_assCORRECT_DUCT_TIME_FL_LV3_SedanH)); + M_MEMCOPY((g_assCORRECT_DUCT_RATE_LV3), (c_assCORRECT_DUCT_RATE_LV3_SedanH)); + M_MEMCOPY((g_assCORRECT_DUCT_MAX_LV3), (c_assCORRECT_DUCT_MAX_LV3_SedanH)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FR_LV3), (c_assCORRECT_AF_TIME_FR_LV3_SedanH)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FL_LV3), (c_assCORRECT_AF_TIME_FL_LV3_SedanH)); + M_MEMCOPY((g_assCORRECT_AF_RATE_LV3), (c_assCORRECT_AF_RATE_LV3_SedanH)); + M_MEMCOPY((g_assCORRECT_AF_MAX_LV3), (c_assCORRECT_AF_MAX_LV3_SedanH)); +/* ------------------------------------------Lv3 : End*/ + M_MEMCOPY((g_assINCAR_TG_FL_LV4), (c_assINCAR_TG_FL_LV4_SedanH)); + M_MEMCOPY((g_assINCAR_TG_FR_LV4), (c_assINCAR_TG_FR_LV4_SedanH)); + M_MEMCOPY((g_assVTG_FL_LV4), (c_assVTG_FL_LV4_SedanH)); + M_MEMCOPY((g_assVTG_FR_LV4), (c_assVTG_FR_LV4_SedanH)); + M_MEMCOPY((g_assVF_MIN_LV4), (c_assVF_MIN_LV4_SedanH)); + M_MEMCOPY((g_assVF_MAX_LV4), (c_assVF_MAX_LV4_SedanH)); + M_MEMCOPY((g_assVF_INC_Y1_LV4), (c_assVF_INC_Y1_LV4_SedanH)); + M_MEMCOPY((g_assVF_INC_Y2_LV4), (c_assVF_INC_Y2_LV4_SedanH)); + M_MEMCOPY((g_assVF_INC_Y3_LV4), (c_assVF_INC_Y3_LV4_SedanH)); + M_MEMCOPY((g_assVF_INC_Y4_LV4), (c_assVF_INC_Y4_LV4_SedanH)); + M_MEMCOPY((g_assVF_INC_X1_LV4), (c_assVF_INC_X1_LV4_SedanH)); + M_MEMCOPY((g_assVF_INC_X2_LV4), (c_assVF_INC_X2_LV4_SedanH)); + M_MEMCOPY((g_assVF_INC_X3_LV4), (c_assVF_INC_X3_LV4_SedanH)); + M_MEMCOPY((g_assVF_INC_X4_LV4), (c_assVF_INC_X4_LV4_SedanH)); + M_MEMCOPY((g_assVF_AMB_Y1_LV4), (c_assVF_AMB_Y1_LV4_SedanH)); + M_MEMCOPY((g_assVF_AMB_Y2_LV4), (c_assVF_AMB_Y2_LV4_SedanH)); + M_MEMCOPY((g_assVF_AMB_X1_LV4), (c_assVF_AMB_X1_LV4_SedanH)); + M_MEMCOPY((g_assVF_AMB_X2_LV4), (c_assVF_AMB_X2_LV4_SedanH)); + M_MEMCOPY((g_assVF_SUN_Y1_LV4), (c_assVF_SUN_Y1_LV4_SedanH)); + M_MEMCOPY((g_assVF_SUN_Y2_LV4), (c_assVF_SUN_Y2_LV4_SedanH)); + M_MEMCOPY((g_assVF_SUN_X1_LV4), (c_assVF_SUN_X1_LV4_SedanH)); + M_MEMCOPY((g_assVF_SUN_X2_LV4), (c_assVF_SUN_X2_LV4_SedanH)); + M_MEMCOPY((g_assTG_FLU_LV4), (c_assTG_FLU_LV4_SedanH)); + M_MEMCOPY((g_assTG_FRU_LV4), (c_assTG_FRU_LV4_SedanH)); + M_MEMCOPY((g_assDTG_FU_MIN_LV4), (c_assDTG_FU_MIN_LV4_SedanH)); + M_MEMCOPY((g_assDTG_FU_MAX_LV4), (c_assDTG_FU_MAX_LV4_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_Y1_LV4), (c_assDTG_FU_INC_Y1_LV4_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_Y2_LV4), (c_assDTG_FU_INC_Y2_LV4_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_Y3_LV4), (c_assDTG_FU_INC_Y3_LV4_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_Y4_LV4), (c_assDTG_FU_INC_Y4_LV4_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_X1_LV4), (c_assDTG_FU_INC_X1_LV4_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_X2_LV4), (c_assDTG_FU_INC_X2_LV4_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_X3_LV4), (c_assDTG_FU_INC_X3_LV4_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_X4_LV4), (c_assDTG_FU_INC_X4_LV4_SedanH)); + M_MEMCOPY((g_assDTG_FU_AMB_Y1_LV4), (c_assDTG_FU_AMB_Y1_LV4_SedanH)); + M_MEMCOPY((g_assDTG_FU_AMB_Y2_LV4), (c_assDTG_FU_AMB_Y2_LV4_SedanH)); + M_MEMCOPY((g_assDTG_FU_AMB_X1_LV4), (c_assDTG_FU_AMB_X1_LV4_SedanH)); + M_MEMCOPY((g_assDTG_FU_AMB_X2_LV4), (c_assDTG_FU_AMB_X2_LV4_SedanH)); + M_MEMCOPY((g_assDTG_FU_SUN_Y1_LV4), (c_assDTG_FU_SUN_Y1_LV4_SedanH)); + M_MEMCOPY((g_assDTG_FU_SUN_Y2_LV4), (c_assDTG_FU_SUN_Y2_LV4_SedanH)); + M_MEMCOPY((g_assDTG_FU_SUN_X1_LV4), (c_assDTG_FU_SUN_X1_LV4_SedanH)); + M_MEMCOPY((g_assDTG_FU_SUN_X2_LV4), (c_assDTG_FU_SUN_X2_LV4_SedanH)); + M_MEMCOPY((g_assTG_FLL_LV4), (c_assTG_FLL_LV4_SedanH)); + M_MEMCOPY((g_assTG_FRL_LV4), (c_assTG_FRL_LV4_SedanH)); + M_MEMCOPY((g_assDTG_FL_MIN_LV4), (c_assDTG_FL_MIN_LV4_SedanH)); + M_MEMCOPY((g_assDTG_FL_MAX_LV4), (c_assDTG_FL_MAX_LV4_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_Y1_LV4), (c_assDTG_FL_INC_Y1_LV4_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_Y2_LV4), (c_assDTG_FL_INC_Y2_LV4_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_Y3_LV4), (c_assDTG_FL_INC_Y3_LV4_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_Y4_LV4), (c_assDTG_FL_INC_Y4_LV4_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_X1_LV4), (c_assDTG_FL_INC_X1_LV4_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_X2_LV4), (c_assDTG_FL_INC_X2_LV4_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_X3_LV4), (c_assDTG_FL_INC_X3_LV4_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_X4_LV4), (c_assDTG_FL_INC_X4_LV4_SedanH)); + M_MEMCOPY((g_assDTG_FL_AMB_Y1_LV4), (c_assDTG_FL_AMB_Y1_LV4_SedanH)); + M_MEMCOPY((g_assDTG_FL_AMB_Y2_LV4), (c_assDTG_FL_AMB_Y2_LV4_SedanH)); + M_MEMCOPY((g_assDTG_FL_AMB_X1_LV4), (c_assDTG_FL_AMB_X1_LV4_SedanH)); + M_MEMCOPY((g_assDTG_FL_AMB_X2_LV4), (c_assDTG_FL_AMB_X2_LV4_SedanH)); + M_MEMCOPY((g_assDTG_FL_SUN_Y1_LV4), (c_assDTG_FL_SUN_Y1_LV4_SedanH)); + M_MEMCOPY((g_assDTG_FL_SUN_Y2_LV4), (c_assDTG_FL_SUN_Y2_LV4_SedanH)); + M_MEMCOPY((g_assDTG_FL_SUN_X1_LV4), (c_assDTG_FL_SUN_X1_LV4_SedanH)); + M_MEMCOPY((g_assDTG_FL_SUN_X2_LV4), (c_assDTG_FL_SUN_X2_LV4_SedanH)); + M_MEMCOPY((g_assINCAR_TG_RL_LV4), (c_assINCAR_TG_RL_LV4_SedanH)); + M_MEMCOPY((g_assINCAR_TG_RR_LV4), (c_assINCAR_TG_RR_LV4_SedanH)); + M_MEMCOPY((g_assVTG_RL_LV4), (c_assVTG_RL_LV4_SedanH)); + M_MEMCOPY((g_assVTG_RR_LV4), (c_assVTG_RR_LV4_SedanH)); + M_MEMCOPY((g_assVR_MIN_LV4), (c_assVR_MIN_LV4_SedanH)); + M_MEMCOPY((g_assVR_MAX_LV4), (c_assVR_MAX_LV4_SedanH)); + M_MEMCOPY((g_assVR_INC_Y1_LV4), (c_assVR_INC_Y1_LV4_SedanH)); + M_MEMCOPY((g_assVR_INC_Y2_LV4), (c_assVR_INC_Y2_LV4_SedanH)); + M_MEMCOPY((g_assVR_INC_Y3_LV4), (c_assVR_INC_Y3_LV4_SedanH)); + M_MEMCOPY((g_assVR_INC_Y4_LV4), (c_assVR_INC_Y4_LV4_SedanH)); + M_MEMCOPY((g_assVR_INC_X1_LV4), (c_assVR_INC_X1_LV4_SedanH)); + M_MEMCOPY((g_assVR_INC_X2_LV4), (c_assVR_INC_X2_LV4_SedanH)); + M_MEMCOPY((g_assVR_INC_X3_LV4), (c_assVR_INC_X3_LV4_SedanH)); + M_MEMCOPY((g_assVR_INC_X4_LV4), (c_assVR_INC_X4_LV4_SedanH)); + M_MEMCOPY((g_assVR_AMB_Y1_LV4), (c_assVR_AMB_Y1_LV4_SedanH)); + M_MEMCOPY((g_assVR_AMB_Y2_LV4), (c_assVR_AMB_Y2_LV4_SedanH)); + M_MEMCOPY((g_assVR_AMB_X1_LV4), (c_assVR_AMB_X1_LV4_SedanH)); + M_MEMCOPY((g_assVR_AMB_X2_LV4), (c_assVR_AMB_X2_LV4_SedanH)); + M_MEMCOPY((g_assVR_SUN_Y1_LV4), (c_assVR_SUN_Y1_LV4_SedanH)); + M_MEMCOPY((g_assVR_SUN_Y2_LV4), (c_assVR_SUN_Y2_LV4_SedanH)); + M_MEMCOPY((g_assVR_SUN_X1_LV4), (c_assVR_SUN_X1_LV4_SedanH)); + M_MEMCOPY((g_assVR_SUN_X2_LV4), (c_assVR_SUN_X2_LV4_SedanH)); + M_MEMCOPY((g_assTG_RL_LV4), (c_assTG_RL_LV4_SedanH)); + M_MEMCOPY((g_assTG_RR_LV4), (c_assTG_RR_LV4_SedanH)); + M_MEMCOPY((g_assDTG_R_MIN_LV4), (c_assDTG_R_MIN_LV4_SedanH)); + M_MEMCOPY((g_assDTG_R_MAX_LV4), (c_assDTG_R_MAX_LV4_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_Y1_LV4), (c_assDTG_R_INC_Y1_LV4_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_Y2_LV4), (c_assDTG_R_INC_Y2_LV4_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_Y3_LV4), (c_assDTG_R_INC_Y3_LV4_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_Y4_LV4), (c_assDTG_R_INC_Y4_LV4_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_X1_LV4), (c_assDTG_R_INC_X1_LV4_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_X2_LV4), (c_assDTG_R_INC_X2_LV4_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_X3_LV4), (c_assDTG_R_INC_X3_LV4_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_X4_LV4), (c_assDTG_R_INC_X4_LV4_SedanH)); + M_MEMCOPY((g_assDTG_R_AMB_Y1_LV4), (c_assDTG_R_AMB_Y1_LV4_SedanH)); + M_MEMCOPY((g_assDTG_R_AMB_Y2_LV4), (c_assDTG_R_AMB_Y2_LV4_SedanH)); + M_MEMCOPY((g_assDTG_R_AMB_X1_LV4), (c_assDTG_R_AMB_X1_LV4_SedanH)); + M_MEMCOPY((g_assDTG_R_AMB_X2_LV4), (c_assDTG_R_AMB_X2_LV4_SedanH)); + M_MEMCOPY((g_assDTG_R_SUN_Y1_LV4), (c_assDTG_R_SUN_Y1_LV4_SedanH)); + M_MEMCOPY((g_assDTG_R_SUN_Y2_LV4), (c_assDTG_R_SUN_Y2_LV4_SedanH)); + M_MEMCOPY((g_assDTG_R_SUN_X1_LV4), (c_assDTG_R_SUN_X1_LV4_SedanH)); + M_MEMCOPY((g_assDTG_R_SUN_X2_LV4), (c_assDTG_R_SUN_X2_LV4_SedanH)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FR_LV4), (c_assCORRECT_DUCT_TIME_FR_LV4_SedanH)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FL_LV4), (c_assCORRECT_DUCT_TIME_FL_LV4_SedanH)); + M_MEMCOPY((g_assCORRECT_DUCT_RATE_LV4), (c_assCORRECT_DUCT_RATE_LV4_SedanH)); + M_MEMCOPY((g_assCORRECT_DUCT_MAX_LV4), (c_assCORRECT_DUCT_MAX_LV4_SedanH)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FR_LV4), (c_assCORRECT_AF_TIME_FR_LV4_SedanH)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FL_LV4), (c_assCORRECT_AF_TIME_FL_LV4_SedanH)); + M_MEMCOPY((g_assCORRECT_AF_RATE_LV4), (c_assCORRECT_AF_RATE_LV4_SedanH)); + M_MEMCOPY((g_assCORRECT_AF_MAX_LV4), (c_assCORRECT_AF_MAX_LV4_SedanH)); +/* ------------------------------------------Lv4 : End*/ + M_MEMCOPY((g_assINCAR_TG_FL_LV5), (c_assINCAR_TG_FL_LV5_SedanH)); + M_MEMCOPY((g_assINCAR_TG_FR_LV5), (c_assINCAR_TG_FR_LV5_SedanH)); + M_MEMCOPY((g_assVTG_FL_LV5), (c_assVTG_FL_LV5_SedanH)); + M_MEMCOPY((g_assVTG_FR_LV5), (c_assVTG_FR_LV5_SedanH)); + M_MEMCOPY((g_assVF_MIN_LV5), (c_assVF_MIN_LV5_SedanH)); + M_MEMCOPY((g_assVF_MAX_LV5), (c_assVF_MAX_LV5_SedanH)); + M_MEMCOPY((g_assVF_INC_Y1_LV5), (c_assVF_INC_Y1_LV5_SedanH)); + M_MEMCOPY((g_assVF_INC_Y2_LV5), (c_assVF_INC_Y2_LV5_SedanH)); + M_MEMCOPY((g_assVF_INC_Y3_LV5), (c_assVF_INC_Y3_LV5_SedanH)); + M_MEMCOPY((g_assVF_INC_Y4_LV5), (c_assVF_INC_Y4_LV5_SedanH)); + M_MEMCOPY((g_assVF_INC_X1_LV5), (c_assVF_INC_X1_LV5_SedanH)); + M_MEMCOPY((g_assVF_INC_X2_LV5), (c_assVF_INC_X2_LV5_SedanH)); + M_MEMCOPY((g_assVF_INC_X3_LV5), (c_assVF_INC_X3_LV5_SedanH)); + M_MEMCOPY((g_assVF_INC_X4_LV5), (c_assVF_INC_X4_LV5_SedanH)); + M_MEMCOPY((g_assVF_AMB_Y1_LV5), (c_assVF_AMB_Y1_LV5_SedanH)); + M_MEMCOPY((g_assVF_AMB_Y2_LV5), (c_assVF_AMB_Y2_LV5_SedanH)); + M_MEMCOPY((g_assVF_AMB_X1_LV5), (c_assVF_AMB_X1_LV5_SedanH)); + M_MEMCOPY((g_assVF_AMB_X2_LV5), (c_assVF_AMB_X2_LV5_SedanH)); + M_MEMCOPY((g_assVF_SUN_Y1_LV5), (c_assVF_SUN_Y1_LV5_SedanH)); + M_MEMCOPY((g_assVF_SUN_Y2_LV5), (c_assVF_SUN_Y2_LV5_SedanH)); + M_MEMCOPY((g_assVF_SUN_X1_LV5), (c_assVF_SUN_X1_LV5_SedanH)); + M_MEMCOPY((g_assVF_SUN_X2_LV5), (c_assVF_SUN_X2_LV5_SedanH)); + M_MEMCOPY((g_assTG_FLU_LV5), (c_assTG_FLU_LV5_SedanH)); + M_MEMCOPY((g_assTG_FRU_LV5), (c_assTG_FRU_LV5_SedanH)); + M_MEMCOPY((g_assDTG_FU_MIN_LV5), (c_assDTG_FU_MIN_LV5_SedanH)); + M_MEMCOPY((g_assDTG_FU_MAX_LV5), (c_assDTG_FU_MAX_LV5_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_Y1_LV5), (c_assDTG_FU_INC_Y1_LV5_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_Y2_LV5), (c_assDTG_FU_INC_Y2_LV5_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_Y3_LV5), (c_assDTG_FU_INC_Y3_LV5_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_Y4_LV5), (c_assDTG_FU_INC_Y4_LV5_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_X1_LV5), (c_assDTG_FU_INC_X1_LV5_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_X2_LV5), (c_assDTG_FU_INC_X2_LV5_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_X3_LV5), (c_assDTG_FU_INC_X3_LV5_SedanH)); + M_MEMCOPY((g_assDTG_FU_INC_X4_LV5), (c_assDTG_FU_INC_X4_LV5_SedanH)); + M_MEMCOPY((g_assDTG_FU_AMB_Y1_LV5), (c_assDTG_FU_AMB_Y1_LV5_SedanH)); + M_MEMCOPY((g_assDTG_FU_AMB_Y2_LV5), (c_assDTG_FU_AMB_Y2_LV5_SedanH)); + M_MEMCOPY((g_assDTG_FU_AMB_X1_LV5), (c_assDTG_FU_AMB_X1_LV5_SedanH)); + M_MEMCOPY((g_assDTG_FU_AMB_X2_LV5), (c_assDTG_FU_AMB_X2_LV5_SedanH)); + M_MEMCOPY((g_assDTG_FU_SUN_Y1_LV5), (c_assDTG_FU_SUN_Y1_LV5_SedanH)); + M_MEMCOPY((g_assDTG_FU_SUN_Y2_LV5), (c_assDTG_FU_SUN_Y2_LV5_SedanH)); + M_MEMCOPY((g_assDTG_FU_SUN_X1_LV5), (c_assDTG_FU_SUN_X1_LV5_SedanH)); + M_MEMCOPY((g_assDTG_FU_SUN_X2_LV5), (c_assDTG_FU_SUN_X2_LV5_SedanH)); + M_MEMCOPY((g_assTG_FLL_LV5), (c_assTG_FLL_LV5_SedanH)); + M_MEMCOPY((g_assTG_FRL_LV5), (c_assTG_FRL_LV5_SedanH)); + M_MEMCOPY((g_assDTG_FL_MIN_LV5), (c_assDTG_FL_MIN_LV5_SedanH)); + M_MEMCOPY((g_assDTG_FL_MAX_LV5), (c_assDTG_FL_MAX_LV5_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_Y1_LV5), (c_assDTG_FL_INC_Y1_LV5_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_Y2_LV5), (c_assDTG_FL_INC_Y2_LV5_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_Y3_LV5), (c_assDTG_FL_INC_Y3_LV5_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_Y4_LV5), (c_assDTG_FL_INC_Y4_LV5_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_X1_LV5), (c_assDTG_FL_INC_X1_LV5_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_X2_LV5), (c_assDTG_FL_INC_X2_LV5_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_X3_LV5), (c_assDTG_FL_INC_X3_LV5_SedanH)); + M_MEMCOPY((g_assDTG_FL_INC_X4_LV5), (c_assDTG_FL_INC_X4_LV5_SedanH)); + M_MEMCOPY((g_assDTG_FL_AMB_Y1_LV5), (c_assDTG_FL_AMB_Y1_LV5_SedanH)); + M_MEMCOPY((g_assDTG_FL_AMB_Y2_LV5), (c_assDTG_FL_AMB_Y2_LV5_SedanH)); + M_MEMCOPY((g_assDTG_FL_AMB_X1_LV5), (c_assDTG_FL_AMB_X1_LV5_SedanH)); + M_MEMCOPY((g_assDTG_FL_AMB_X2_LV5), (c_assDTG_FL_AMB_X2_LV5_SedanH)); + M_MEMCOPY((g_assDTG_FL_SUN_Y1_LV5), (c_assDTG_FL_SUN_Y1_LV5_SedanH)); + M_MEMCOPY((g_assDTG_FL_SUN_Y2_LV5), (c_assDTG_FL_SUN_Y2_LV5_SedanH)); + M_MEMCOPY((g_assDTG_FL_SUN_X1_LV5), (c_assDTG_FL_SUN_X1_LV5_SedanH)); + M_MEMCOPY((g_assDTG_FL_SUN_X2_LV5), (c_assDTG_FL_SUN_X2_LV5_SedanH)); + M_MEMCOPY((g_assINCAR_TG_RL_LV5), (c_assINCAR_TG_RL_LV5_SedanH)); + M_MEMCOPY((g_assINCAR_TG_RR_LV5), (c_assINCAR_TG_RR_LV5_SedanH)); + M_MEMCOPY((g_assVTG_RL_LV5), (c_assVTG_RL_LV5_SedanH)); + M_MEMCOPY((g_assVTG_RR_LV5), (c_assVTG_RR_LV5_SedanH)); + M_MEMCOPY((g_assVR_MIN_LV5), (c_assVR_MIN_LV5_SedanH)); + M_MEMCOPY((g_assVR_MAX_LV5), (c_assVR_MAX_LV5_SedanH)); + M_MEMCOPY((g_assVR_INC_Y1_LV5), (c_assVR_INC_Y1_LV5_SedanH)); + M_MEMCOPY((g_assVR_INC_Y2_LV5), (c_assVR_INC_Y2_LV5_SedanH)); + M_MEMCOPY((g_assVR_INC_Y3_LV5), (c_assVR_INC_Y3_LV5_SedanH)); + M_MEMCOPY((g_assVR_INC_Y4_LV5), (c_assVR_INC_Y4_LV5_SedanH)); + M_MEMCOPY((g_assVR_INC_X1_LV5), (c_assVR_INC_X1_LV5_SedanH)); + M_MEMCOPY((g_assVR_INC_X2_LV5), (c_assVR_INC_X2_LV5_SedanH)); + M_MEMCOPY((g_assVR_INC_X3_LV5), (c_assVR_INC_X3_LV5_SedanH)); + M_MEMCOPY((g_assVR_INC_X4_LV5), (c_assVR_INC_X4_LV5_SedanH)); + M_MEMCOPY((g_assVR_AMB_Y1_LV5), (c_assVR_AMB_Y1_LV5_SedanH)); + M_MEMCOPY((g_assVR_AMB_Y2_LV5), (c_assVR_AMB_Y2_LV5_SedanH)); + M_MEMCOPY((g_assVR_AMB_X1_LV5), (c_assVR_AMB_X1_LV5_SedanH)); + M_MEMCOPY((g_assVR_AMB_X2_LV5), (c_assVR_AMB_X2_LV5_SedanH)); + M_MEMCOPY((g_assVR_SUN_Y1_LV5), (c_assVR_SUN_Y1_LV5_SedanH)); + M_MEMCOPY((g_assVR_SUN_Y2_LV5), (c_assVR_SUN_Y2_LV5_SedanH)); + M_MEMCOPY((g_assVR_SUN_X1_LV5), (c_assVR_SUN_X1_LV5_SedanH)); + M_MEMCOPY((g_assVR_SUN_X2_LV5), (c_assVR_SUN_X2_LV5_SedanH)); + M_MEMCOPY((g_assTG_RL_LV5), (c_assTG_RL_LV5_SedanH)); + M_MEMCOPY((g_assTG_RR_LV5), (c_assTG_RR_LV5_SedanH)); + M_MEMCOPY((g_assDTG_R_MIN_LV5), (c_assDTG_R_MIN_LV5_SedanH)); + M_MEMCOPY((g_assDTG_R_MAX_LV5), (c_assDTG_R_MAX_LV5_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_Y1_LV5), (c_assDTG_R_INC_Y1_LV5_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_Y2_LV5), (c_assDTG_R_INC_Y2_LV5_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_Y3_LV5), (c_assDTG_R_INC_Y3_LV5_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_Y4_LV5), (c_assDTG_R_INC_Y4_LV5_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_X1_LV5), (c_assDTG_R_INC_X1_LV5_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_X2_LV5), (c_assDTG_R_INC_X2_LV5_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_X3_LV5), (c_assDTG_R_INC_X3_LV5_SedanH)); + M_MEMCOPY((g_assDTG_R_INC_X4_LV5), (c_assDTG_R_INC_X4_LV5_SedanH)); + M_MEMCOPY((g_assDTG_R_AMB_Y1_LV5), (c_assDTG_R_AMB_Y1_LV5_SedanH)); + M_MEMCOPY((g_assDTG_R_AMB_Y2_LV5), (c_assDTG_R_AMB_Y2_LV5_SedanH)); + M_MEMCOPY((g_assDTG_R_AMB_X1_LV5), (c_assDTG_R_AMB_X1_LV5_SedanH)); + M_MEMCOPY((g_assDTG_R_AMB_X2_LV5), (c_assDTG_R_AMB_X2_LV5_SedanH)); + M_MEMCOPY((g_assDTG_R_SUN_Y1_LV5), (c_assDTG_R_SUN_Y1_LV5_SedanH)); + M_MEMCOPY((g_assDTG_R_SUN_Y2_LV5), (c_assDTG_R_SUN_Y2_LV5_SedanH)); + M_MEMCOPY((g_assDTG_R_SUN_X1_LV5), (c_assDTG_R_SUN_X1_LV5_SedanH)); + M_MEMCOPY((g_assDTG_R_SUN_X2_LV5), (c_assDTG_R_SUN_X2_LV5_SedanH)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FR_LV5), (c_assCORRECT_DUCT_TIME_FR_LV5_SedanH)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FL_LV5), (c_assCORRECT_DUCT_TIME_FL_LV5_SedanH)); + M_MEMCOPY((g_assCORRECT_DUCT_RATE_LV5), (c_assCORRECT_DUCT_RATE_LV5_SedanH)); + M_MEMCOPY((g_assCORRECT_DUCT_MAX_LV5), (c_assCORRECT_DUCT_MAX_LV5_SedanH)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FR_LV5), (c_assCORRECT_AF_TIME_FR_LV5_SedanH)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FL_LV5), (c_assCORRECT_AF_TIME_FL_LV5_SedanH)); + M_MEMCOPY((g_assCORRECT_AF_RATE_LV5), (c_assCORRECT_AF_RATE_LV5_SedanH)); + M_MEMCOPY((g_assCORRECT_AF_MAX_LV5), (c_assCORRECT_AF_MAX_LV5_SedanH)); +/* ------------------------------------------Lv5 : End*/ + M_MEMCOPY((g_assDUCT_TGT_DEF_VALVE_L), (c_assDUCT_TGT_DEF_VALVE_L_SedanH)); + M_MEMCOPY((g_assDUCT_TGT_DEF_VALVE_R), (c_assDUCT_TGT_DEF_VALVE_R_SedanH)); +/* ------------------------------------------DuctTgt Increase : End*/ + M_MEMCOPY((g_assAMB_LV_UP), (c_assAMB_LV_UP_SedanH)); + M_MEMCOPY((g_assAMB_LV_DN), (c_assAMB_LV_DN_SedanH)); + M_MEMCOPY((g_assAMB_LV_TG), (c_assAMB_LV_TG_SedanH)); +/* ------------------------------------------Ambient LEVEL : End*/ + M_MEMCOPY((g_aucMODE_BY_SET_F_LV0), (c_aucMODE_BY_SET_F_LV0_SedanH)); + M_MEMCOPY((g_aucMODE_BY_SET_F_LV1), (c_aucMODE_BY_SET_F_LV1_SedanH)); + M_MEMCOPY((g_aucMODE_BY_SET_F_LV2), (c_aucMODE_BY_SET_F_LV2_SedanH)); + M_MEMCOPY((g_aucMODE_BY_SET_F_LV3), (c_aucMODE_BY_SET_F_LV3_SedanH)); + M_MEMCOPY((g_aucMODE_BY_SET_F_LV4), (c_aucMODE_BY_SET_F_LV4_SedanH)); + M_MEMCOPY((g_aucMODE_BY_SET_F_LV5), (c_aucMODE_BY_SET_F_LV5_SedanH)); + M_MEMCOPY((g_ausMODE_BY_DUCT_TG_R_LV0), (c_ausMODE_BY_DUCT_TG_R_LV0_SedanH)); + M_MEMCOPY((g_ausMODE_BY_DUCT_TG_R_LV1), (c_ausMODE_BY_DUCT_TG_R_LV1_SedanH)); + M_MEMCOPY((g_ausMODE_BY_DUCT_TG_R_LV2), (c_ausMODE_BY_DUCT_TG_R_LV2_SedanH)); + M_MEMCOPY((g_ausMODE_BY_DUCT_TG_R_LV3), (c_ausMODE_BY_DUCT_TG_R_LV3_SedanH)); + M_MEMCOPY((g_ausMODE_BY_DUCT_TG_R_LV4), (c_ausMODE_BY_DUCT_TG_R_LV4_SedanH)); + M_MEMCOPY((g_ausMODE_BY_DUCT_TG_R_LV5), (c_ausMODE_BY_DUCT_TG_R_LV5_SedanH)); +/* ------------------------------------------Mode depend on SET for each level : End*/ + g_ssPREC_REC_ON_AMB = c_ssPREC_REC_ON_AMB_SedanH; + g_ssPREC_REC_OFF_AMB = c_ssPREC_REC_OFF_AMB_SedanH; + M_MEMCOPY((g_aucPREC_VEH_SPD_OSA), (c_aucPREC_VEH_SPD_OSA_SedanH)); + M_MEMCOPY((g_assPRE_AMB_RANGE_WINTER), (c_assPRE_AMB_RANGE_WINTER_SedanH)); + M_MEMCOPY((g_aucPREC_OSA_WINTER), (c_aucPREC_OSA_WINTER_SedanH)); + M_MEMCOPY((g_aucPREC_REC_WINTER), (c_aucPREC_REC_WINTER_SedanH)); + M_MEMCOPY((g_ausPREC_HUMIDITY_NOK), (c_ausPREC_HUMIDITY_NOK_SedanH)); + M_MEMCOPY((g_ausPREC_HUMIDITY_OK), (c_ausPREC_HUMIDITY_OK_SedanH)); + M_MEMCOPY((g_ausPREC_ENTRY_RPM), (c_ausPREC_ENTRY_RPM_SedanH)); + M_MEMCOPY((g_ausPREC_EXIT_RPM), (c_ausPREC_EXIT_RPM_SedanH)); + M_MEMCOPY((g_ausPREC_COMP_SPD_1), (c_ausPREC_COMP_SPD_1_SedanH)); + M_MEMCOPY((g_aucPREC_OSA_SUMMER_1), (c_aucPREC_OSA_SUMMER_1_SedanH)); + M_MEMCOPY((g_aucPREC_REC_SUMMER_1), (c_aucPREC_REC_SUMMER_1_SedanH)); + M_MEMCOPY((g_assPREC_EVA_DIFF_FB_TG_F), (c_assPREC_EVA_DIFF_FB_TG_F_SedanH)); + M_MEMCOPY((g_aucPREC_OSA_SUMMER_2), (c_aucPREC_OSA_SUMMER_2_SedanH)); + M_MEMCOPY((g_aucPREC_REC_SUMMER_2), (c_aucPREC_REC_SUMMER_2_SedanH)); + M_MEMCOPY((g_aucPREC_EVA_DIFF), (c_aucPREC_EVA_DIFF_SedanH)); + g_ucPREC_OSA_SUMMER_3 = c_ucPREC_OSA_SUMMER_3_SedanH; + g_ucPREC_REC_SUMMER_3 = c_ucPREC_REC_SUMMER_3_SedanH; +/* ------------------------------------------AutoRec : End*/ + M_MEMCOPY((g_ausFLOW_FR_VE2VALVE), (c_ausFLOW_FR_VE2VALVE_SedanH)); + M_MEMCOPY((g_ausFLOW_FR_BIVALVE), (c_ausFLOW_FR_BIVALVE_SedanH)); + M_MEMCOPY((g_ausFLOW_FR_BI2VALVE), (c_ausFLOW_FR_BI2VALVE_SedanH)); + M_MEMCOPY((g_ausFLOW_FR_AF2VALVE), (c_ausFLOW_FR_AF2VALVE_SedanH)); + M_MEMCOPY((g_ausFLOW_FR_AF2VALVE_SUMMER), (c_ausFLOW_FR_AF2VALVE_SUMMER_SedanH)); + M_MEMCOPY((g_ausFLOW_FR_FO2VALVE), (c_ausFLOW_FR_FO2VALVE_SedanH)); + M_MEMCOPY((g_ausFLOW_FR_FD2VALVE), (c_ausFLOW_FR_FD2VALVE_SedanH)); + M_MEMCOPY((g_ausFLOW_FR_DE2VALVE), (c_ausFLOW_FR_DE2VALVE_SedanH)); + M_MEMCOPY((g_ausFLOW_FR_TR2VALVE), (c_ausFLOW_FR_TR2VALVE_SedanH)); + M_MEMCOPY((g_ausFLOW_FR_HI2VALVE), (c_ausFLOW_FR_HI2VALVE_SedanH)); + M_MEMCOPY((g_ausFLOW_FR_BIVALVE_MANUAL), (c_ausFLOW_FR_BIVALVE_MANUAL_SedanH)); + M_MEMCOPY((g_ausFLOW_RE_VENT), (c_ausFLOW_RE_VENT_SedanH)); + M_MEMCOPY((g_ausFLOW_RE_BI2VALVE), (c_ausFLOW_RE_BI2VALVE_SedanH)); + M_MEMCOPY((g_ausFLOW_RE_FO2VALVE), (c_ausFLOW_RE_FO2VALVE_SedanH)); + M_MEMCOPY((g_ausFLOW_RE_VENT_2), (c_ausFLOW_RE_VENT_2_SedanH)); + M_MEMCOPY((g_ausFLOW_RE_BI2VALVE_2), (c_ausFLOW_RE_BI2VALVE_2_SedanH)); + M_MEMCOPY((g_ausFLOW_RE_VENT_3), (c_ausFLOW_RE_VENT_3_SedanH)); + M_MEMCOPY((g_ausFLOW_RE_BI2VALVE_3), (c_ausFLOW_RE_BI2VALVE_3_SedanH)); + M_MEMCOPY((g_ausFLOW_RE_VENT_MANUAL), (c_ausFLOW_RE_VENT_MANUAL_SedanH)); + M_MEMCOPY((g_ausFLOW_RE_BI2VALVE_MANUAL), (c_ausFLOW_RE_BI2VALVE_MANUAL_SedanH)); +/* ------------------------------------------Flow Control Valve: End*/ + M_MEMCOPY((g_assFLOW_BI_AMB_TGT), (c_assFLOW_BI_AMB_TGT_SedanH)); + M_MEMCOPY((g_aucFLOW_BI_VENT_PLUS), (c_aucFLOW_BI_VENT_PLUS_SedanH)); + M_MEMCOPY((g_assFLOW_BI_TEMP_TGT), (c_assFLOW_BI_TEMP_TGT_SedanH)); + M_MEMCOPY((g_aucFLOW_BI_FOOT_PLUS), (c_aucFLOW_BI_FOOT_PLUS_SedanH)); + M_MEMCOPY((g_aucFLOW_BI_VENT_VALVE_MAX), (c_aucFLOW_BI_VENT_VALVE_MAX_SedanH)); + M_MEMCOPY((g_aucFLOW_BI_FOOT_VALVE_MAX), (c_aucFLOW_BI_FOOT_VALVE_MAX_SedanH)); + M_MEMCOPY((g_aucFLOW_BI_VENT_VALVE_MIN), (c_aucFLOW_BI_VENT_VALVE_MIN_SedanH)); + M_MEMCOPY((g_aucFLOW_BI_FOOT_VALVE_MIN), (c_aucFLOW_BI_FOOT_VALVE_MIN_SedanH)); +/* ------------------------------------------Bi 2 level conditions: End*/ + M_MEMCOPY((g_assFLOW_B2I_AMB_TGT), (c_assFLOW_B2I_AMB_TGT_SedanH)); + M_MEMCOPY((g_aucFLOW_BI2_VENT_PLUS), (c_aucFLOW_BI2_VENT_PLUS_SedanH)); + M_MEMCOPY((g_assFLOW_BI2_TEMP_TGT), (c_assFLOW_BI2_TEMP_TGT_SedanH)); + M_MEMCOPY((g_aucFLOW_BI2_FOOT_PLUS), (c_aucFLOW_BI2_FOOT_PLUS_SedanH)); + M_MEMCOPY((g_aucFLOW_BI2_VENT_VALVE_MAX), (c_aucFLOW_BI2_VENT_VALVE_MAX_SedanH)); + M_MEMCOPY((g_aucFLOW_BI2_FOOT_VALVE_MAX), (c_aucFLOW_BI2_FOOT_VALVE_MAX_SedanH)); + M_MEMCOPY((g_aucFLOW_BI2_VENT_VALVE_MIN), (c_aucFLOW_BI2_VENT_VALVE_MIN_SedanH)); + M_MEMCOPY((g_aucFLOW_BI2_FOOT_VALVE_MIN), (c_aucFLOW_BI2_FOOT_VALVE_MIN_SedanH)); +/* ------------------------------------------AF level conditions: End*/ + M_MEMCOPY((g_assFLOW_AF_AMB_TGT), (c_assFLOW_AF_AMB_TGT_SedanH)); + M_MEMCOPY((g_aucFLOW_AF_VENT_PLUS), (c_aucFLOW_AF_VENT_PLUS_SedanH)); + M_MEMCOPY((g_aucFLOW_AF_BLR_AF_TGT), (c_aucFLOW_AF_BLR_AF_TGT_SedanH)); + M_MEMCOPY((g_aucFLOW_AF_FOOT_PLUS), (c_aucFLOW_AF_FOOT_PLUS_SedanH)); + M_MEMCOPY((g_aucFLOW_AF_VENT_VALVE_MAX), (c_aucFLOW_AF_VENT_VALVE_MAX_SedanH)); + M_MEMCOPY((g_aucFLOW_AF_FOOT_VALVE_MAX), (c_aucFLOW_AF_FOOT_VALVE_MAX_SedanH)); +/* ------------------------------------------AF level conditions: End*/ + M_MEMCOPY((g_assFLOW_AFSM_AMB_TGT), (c_assFLOW_AFSM_AMB_TGT_SedanH)); + M_MEMCOPY((g_aucFLOW_AFSM_VENT_PLUS), (c_aucFLOW_AFSM_VENT_PLUS_SedanH)); + M_MEMCOPY((g_assFLOW_AFSM_TEMP_TGT), (c_assFLOW_AFSM_TEMP_TGT_SedanH)); + M_MEMCOPY((g_aucFLOW_AFSM_FOOT_PLUS), (c_aucFLOW_AFSM_FOOT_PLUS_SedanH)); + M_MEMCOPY((g_aucFLOW_AFSM_VENT_VALVE_MAX), (c_aucFLOW_AFSM_VENT_VALVE_MAX_SedanH)); + M_MEMCOPY((g_aucFLOW_AFSM_FOOT_VALVE_MAX), (c_aucFLOW_AFSM_FOOT_VALVE_MAX_SedanH)); +/* ------------------------------------------AF_summer level conditions: End*/ + M_MEMCOPY((g_aucMODE_INDEX), (c_aucMODE_INDEX_SedanH)); + M_MEMCOPY((g_assFOOT_STEP_DUCT_TGT), (c_assFOOT_STEP_DUCT_TGT_SedanH)); + M_MEMCOPY((g_assBLR_FOOT_IND), (c_assBLR_FOOT_IND_SedanH)); + M_MEMCOPY((g_ascFOOT_STEP_VALVE_P1), (c_ascFOOT_STEP_VALVE_P1_SedanH)); + M_MEMCOPY((g_ascFOOT_STEP_VALVE_P2), (c_ascFOOT_STEP_VALVE_P2_SedanH)); + M_MEMCOPY((g_ascFOOT_STEP_VALVE_P3), (c_ascFOOT_STEP_VALVE_P3_SedanH)); + M_MEMCOPY((g_ascFOOT_STEP_VALVE_M1), (c_ascFOOT_STEP_VALVE_M1_SedanH)); + M_MEMCOPY((g_ascFOOT_STEP_VALVE_M2), (c_ascFOOT_STEP_VALVE_M2_SedanH)); + M_MEMCOPY((g_ascFOOT_STEP_VALVE_M3), (c_ascFOOT_STEP_VALVE_M3_SedanH)); + M_MEMCOPY((g_assFOOT_STEP_BLR_P1), (c_assFOOT_STEP_BLR_P1_SedanH)); + M_MEMCOPY((g_assFOOT_STEP_BLR_P2), (c_assFOOT_STEP_BLR_P2_SedanH)); + M_MEMCOPY((g_assFOOT_STEP_BLR_P3), (c_assFOOT_STEP_BLR_P3_SedanH)); + M_MEMCOPY((g_assFOOT_STEP_BLR_M1), (c_assFOOT_STEP_BLR_M1_SedanH)); + M_MEMCOPY((g_assFOOT_STEP_BLR_M2), (c_assFOOT_STEP_BLR_M2_SedanH)); + M_MEMCOPY((g_assFOOT_STEP_BLR_M3), (c_assFOOT_STEP_BLR_M3_SedanH)); +/* ------------------------------------------Individual foot temperature: End*/ + M_MEMCOPY((g_aucREAR_FOOT_VALVE_AMB_LV2), (c_aucREAR_FOOT_VALVE_AMB_LV2_SedanH)); + M_MEMCOPY((g_aucREAR_FOOT_VALVE_AMB_LV3), (c_aucREAR_FOOT_VALVE_AMB_LV3_SedanH)); + M_MEMCOPY((g_aucREAR_FOOT_VALVE_AMB_LV4), (c_aucREAR_FOOT_VALVE_AMB_LV4_SedanH)); +/* ------------------------------------------Blowing foots from Rear HVAC: End*/ + M_MEMCOPY((g_ausFLOW_FR_VE2BLR_AF), (c_ausFLOW_FR_VE2BLR_AF_SedanH)); + M_MEMCOPY((g_ausFLOW_FR_BIVALVE_AF), (c_ausFLOW_FR_BIVALVE_AF_SedanH)); + M_MEMCOPY((g_ausFLOW_FR_BI2BLR_AF), (c_ausFLOW_FR_BI2BLR_AF_SedanH)); + M_MEMCOPY((g_ausFLOW_FR_FO2BLR_AF), (c_ausFLOW_FR_FO2BLR_AF_SedanH)); + M_MEMCOPY((g_ausFLOW_FR_AF2VALVE_AF), (c_ausFLOW_FR_AF2VALVE_AF_SedanH)); + M_MEMCOPY((g_ausFLOW_FR_AF2VALVE_SUMMER_AF), (c_ausFLOW_FR_AF2VALVE_SUMMER_AF_SedanH)); + M_MEMCOPY((g_ausFLOW_FR_FD2BLR_AF), (c_ausFLOW_FR_FD2BLR_AF_SedanH)); + M_MEMCOPY((g_ausFLOW_FR_DE2BLR_AF), (c_ausFLOW_FR_DE2BLR_AF_SedanH)); + M_MEMCOPY((g_ausFLOW_FR_TR2BLR_AF), (c_ausFLOW_FR_TR2BLR_AF_SedanH)); + M_MEMCOPY((g_ausFLOW_FR_HI2BLR_AF), (c_ausFLOW_FR_HI2BLR_AF_SedanH)); + M_MEMCOPY((g_ausFLOW_RE_VE2BLR_AF), (c_ausFLOW_RE_VE2BLR_AF_SedanH)); + M_MEMCOPY((g_ausFLOW_RE_BI2BLR_AF), (c_ausFLOW_RE_BI2BLR_AF_SedanH)); + M_MEMCOPY((g_ausFLOW_RE_FO2BLR_AF), (c_ausFLOW_RE_FO2BLR_AF_SedanH)); +/* ------------------------------------------Flow Control AF: End*/ + M_MEMCOPY((g_ascAUTO_STEP_AF_F), (c_ascAUTO_STEP_AF_F_SedanH)); + M_MEMCOPY((g_ascAUTO_STEP_AF_R), (c_ascAUTO_STEP_AF_R_SedanH)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_U_F_LV0_1), (c_assAUTO_STEP_DUCT_TG_U_F_LV0_1_SedanH)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_U_F_LV2_3), (c_assAUTO_STEP_DUCT_TG_U_F_LV2_3_SedanH)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_U_F_LV4_5), (c_assAUTO_STEP_DUCT_TG_U_F_LV4_5_SedanH)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_L_F_LV0_1), (c_assAUTO_STEP_DUCT_TG_L_F_LV0_1_SedanH)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_L_F_LV2_3), (c_assAUTO_STEP_DUCT_TG_L_F_LV2_3_SedanH)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_L_F_LV4_5), (c_assAUTO_STEP_DUCT_TG_L_F_LV4_5_SedanH)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_R_LV0_1), (c_assAUTO_STEP_DUCT_TG_R_LV0_1_SedanH)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_R_LV2_3), (c_assAUTO_STEP_DUCT_TG_R_LV2_3_SedanH)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_R_LV4_5), (c_assAUTO_STEP_DUCT_TG_R_LV4_5_SedanH)); +/* ------------------------------------------5 AUTO mode: End*/ + M_MEMCOPY((g_ausVALVE_SPACE), (c_ausVALVE_SPACE_SedanH)); + M_MEMCOPY((g_aucVALVE_SECTION_S1_F_SIDE_VENT), (c_aucVALVE_SECTION_S1_F_SIDE_VENT_SedanH)); + M_MEMCOPY((g_aucVALVE_SECTION_S1_F_CENT_VENT), (c_aucVALVE_SECTION_S1_F_CENT_VENT_SedanH)); + M_MEMCOPY((g_aucVALVE_SECTION_S1_F_DRIVER_FOOT), (c_aucVALVE_SECTION_S1_F_DRIVER_FOOT_SedanH)); + M_MEMCOPY((g_aucVALVE_SECTION_S1_F_RIGHT_PASS), (c_aucVALVE_SECTION_S1_F_RIGHT_PASS_SedanH)); + M_MEMCOPY((g_aucBLR_SPD_V1_1_F), (c_aucBLR_SPD_V1_1_F_SedanH)); + M_MEMCOPY((g_aucBLR_SPD_K2_1_F_SIDE_VENT), (c_aucBLR_SPD_K2_1_F_SIDE_VENT_SedanH)); + M_MEMCOPY((g_aucBLR_SPD_K2_2_F_CENT_VENT), (c_aucBLR_SPD_K2_2_F_CENT_VENT_SedanH)); + M_MEMCOPY((g_aucBLR_SPD_K2_3_F_DRIVER_FOOT), (c_aucBLR_SPD_K2_3_F_DRIVER_FOOT_SedanH)); + M_MEMCOPY((g_aucBLR_SPD_K2_4_F_RIGHT_PASS), (c_aucBLR_SPD_K2_4_F_RIGHT_PASS_SedanH)); + M_MEMCOPY((g_ausVALVE_VEH_SPD), (c_ausVALVE_VEH_SPD_SedanH)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_SIDE_VENT), (c_aucVALVE_VEH_SPD_SIDE_VENT_SedanH)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_SIDE_BI), (c_aucVALVE_VEH_SPD_SIDE_BI_SedanH)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_SIDE_AFOOT), (c_aucVALVE_VEH_SPD_SIDE_AFOOT_SedanH)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_CNET_VENT), (c_aucVALVE_VEH_SPD_CNET_VENT_SedanH)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_CENT_BI), (c_aucVALVE_VEH_SPD_CENT_BI_SedanH)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_CENT_AFOOT), (c_aucVALVE_VEH_SPD_CENT_AFOOT_SedanH)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_FOOT_BI), (c_aucVALVE_VEH_SPD_FOOT_BI_SedanH)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_FOOT_AFOOT), (c_aucVALVE_VEH_SPD_FOOT_AFOOT_SedanH)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_2FOOT), (c_aucVALVE_VEH_SPD_2FOOT_SedanH)); + M_MEMCOPY((g_aucBLR_SPD_VEH_SPD_V1_3), (c_aucBLR_SPD_VEH_SPD_V1_3_SedanH)); + M_MEMCOPY((g_aucFRONT_SIDE_DRS_PERCENT), (c_aucFRONT_SIDE_DRS_PERCENT_SedanH)); + M_MEMCOPY((g_aucFRONT_CENT_DRS_PERCENT), (c_aucFRONT_CENT_DRS_PERCENT_SedanH)); +/* ------------------------------------------Different blower speed FRONT MODE: End*/ + M_MEMCOPY((g_aucVALVE_S1_R_BIPILLAR), (c_aucVALVE_S1_R_BIPILLAR_SedanH)); + M_MEMCOPY((g_aucVALVE_S1_R_CENT_VENT), (c_aucVALVE_S1_R_CENT_VENT_SedanH)); + M_MEMCOPY((g_aucVALVE_S1_R_FOOT), (c_aucVALVE_S1_R_FOOT_SedanH)); + M_MEMCOPY((g_aucVALVE_PERC_R_BIPILLAR), (c_aucVALVE_PERC_R_BIPILLAR_SedanH)); + M_MEMCOPY((g_aucVALVE_PERC_R_CENT_VENT), (c_aucVALVE_PERC_R_CENT_VENT_SedanH)); + M_MEMCOPY((g_aucVALVE_PERC_R_FOOT), (c_aucVALVE_PERC_R_FOOT_SedanH)); + M_MEMCOPY((g_aucBLR_SPD_V1_1_R), (c_aucBLR_SPD_V1_1_R_SedanH)); + M_MEMCOPY((g_aucREAR_CEN_MIN_VALUE_BY_DRS_ZERO), (c_aucREAR_CEN_MIN_VALUE_BY_DRS_ZERO_SedanH)); + M_MEMCOPY((g_aucBLR_SPD_K2_1_R_BIPILLAR_MIN), (c_aucBLR_SPD_K2_1_R_BIPILLAR_MIN_SedanH)); + M_MEMCOPY((g_aucBLR_SPD_K2_2_R_CENT_VENT_MIN), (c_aucBLR_SPD_K2_2_R_CENT_VENT_MIN_SedanH)); + M_MEMCOPY((g_aucBLR_SPD_K2_3_R_FOOT_MIN), (c_aucBLR_SPD_K2_3_R_FOOT_MIN_SedanH)); + M_MEMCOPY((g_aucBLR_SPD_K2_1_R_BIPILLAR_MAX), (c_aucBLR_SPD_K2_1_R_BIPILLAR_MAX_SedanH)); + M_MEMCOPY((g_aucBLR_SPD_K2_2_R_CENT_VENTR_MAX), (c_aucBLR_SPD_K2_2_R_CENT_VENTR_MAX_SedanH)); + M_MEMCOPY((g_aucBLR_SPD_K2_3_R_FOOTR_MAX), (c_aucBLR_SPD_K2_3_R_FOOTR_MAX_SedanH)); + M_MEMCOPY((g_aucREAR_SIDE_DRS_PERCENT_VALVE), (c_aucREAR_SIDE_DRS_PERCENT_VALVE_SedanH)); + M_MEMCOPY((g_aucREAR_CENT_DRS_PERCENT_VALVE), (c_aucREAR_CENT_DRS_PERCENT_VALVE_SedanH)); + M_MEMCOPY((g_aucREAR_SIDE_DRS_PERCENT_AF), (c_aucREAR_SIDE_DRS_PERCENT_AF_SedanH)); + M_MEMCOPY((g_aucREAR_CENT_DRS_PERCENT_AF), (c_aucREAR_CENT_DRS_PERCENT_AF_SedanH)); +/* ------------------------------------------Different blower speed REAR MODE: End*/ + M_MEMCOPY((g_ausMIN_PWM), (c_ausMIN_PWM_SedanH)); +/* ------------------------------------------MinPWM: End*/ + M_MEMCOPY((g_assSTART_ENTER_COOLANT), (c_assSTART_ENTER_COOLANT_SedanH)); + M_MEMCOPY((g_assSTART_COOLANT_STEP0_TO_1), (c_assSTART_COOLANT_STEP0_TO_1_SedanH)); + M_MEMCOPY((g_assSTART_COOLANT_TO_STEP2), (c_assSTART_COOLANT_TO_STEP2_SedanH)); + M_MEMCOPY((g_assSTART_COOLANT_STEP1_BLR_F), (c_assSTART_COOLANT_STEP1_BLR_F_SedanH)); + M_MEMCOPY((g_assSTART_COOLANT_STEP1_BLR_R), (c_assSTART_COOLANT_STEP1_BLR_R_SedanH)); + M_MEMCOPY((g_assSTART_ENTER_INCAR), (c_assSTART_ENTER_INCAR_SedanH)); + M_MEMCOPY((g_ausSTART_ENTER_SETTEMP), (c_ausSTART_ENTER_SETTEMP_SedanH)); + M_MEMCOPY((g_aucSTART_INCAR_FLT_UP), (c_aucSTART_INCAR_FLT_UP_SedanH)); + M_MEMCOPY((g_aucSTART_INCAR_FLT_DN), (c_aucSTART_INCAR_FLT_DN_SedanH)); + M_MEMCOPY((g_aucSTART_VALVE_IDX_STEP1), (c_aucSTART_VALVE_IDX_STEP1_SedanH)); + M_MEMCOPY((g_aucSTART_AUTODEMIST2_STEP2), (c_aucSTART_AUTODEMIST2_STEP2_SedanH)); + M_MEMCOPY((g_aucSTART_ELEC_WINDOW), (c_aucSTART_ELEC_WINDOW_SedanH)); + M_MEMCOPY((g_ausSTART_BLR_AF_STEP12_F), (c_ausSTART_BLR_AF_STEP12_F_SedanH)); + M_MEMCOPY((g_ausSTART_BLR_AF_STEP12_R), (c_ausSTART_BLR_AF_STEP12_R_SedanH)); + M_MEMCOPY((g_ausSTART_BLR_SPD_STEP2_F), (c_ausSTART_BLR_SPD_STEP2_F_SedanH)); + M_MEMCOPY((g_ausSTART_BLR_SPD_STEP2_R), (c_ausSTART_BLR_SPD_STEP2_R_SedanH)); + M_MEMCOPY((g_aucSTART_DUCT_TGT_STEP2_FX_U), (c_aucSTART_DUCT_TGT_STEP2_FX_U_SedanH)); + M_MEMCOPY((g_aucSTART_DUCT_TGT_STEP2_FX_L), (c_aucSTART_DUCT_TGT_STEP2_FX_L_SedanH)); + M_MEMCOPY((g_aucSTART_DUCT_TGT_STEP2_RX), (c_aucSTART_DUCT_TGT_STEP2_RX_SedanH)); + M_MEMCOPY((g_aucSTART_VALVE_CHANGE_SPD_F), (c_aucSTART_VALVE_CHANGE_SPD_F_SedanH)); + M_MEMCOPY((g_aucSTART_VALVE_CHANGE_SPD_R), (c_aucSTART_VALVE_CHANGE_SPD_R_SedanH)); + M_MEMCOPY((g_ausSTART_TIME_STEP1_TO_2), (c_ausSTART_TIME_STEP1_TO_2_SedanH)); + M_MEMCOPY((g_ausSTART_TIME_STEP2_TO_3), (c_ausSTART_TIME_STEP2_TO_3_SedanH)); + M_MEMCOPY((g_assSTART_INCAR_STEP1_TO_2), (c_assSTART_INCAR_STEP1_TO_2_SedanH)); + M_MEMCOPY((g_assSTART_INCAR_STEP2_TO_3), (c_assSTART_INCAR_STEP2_TO_3_SedanH)); + M_MEMCOPY((g_aucSTART_3WAY_OPEN), (c_aucSTART_3WAY_OPEN_SedanH)); + M_MEMCOPY((g_aucSTART_2WAY_OPEN), (c_aucSTART_2WAY_OPEN_SedanH)); + M_MEMCOPY((g_aucSTART_TXV_F), (c_aucSTART_TXV_F_SedanH)); + M_MEMCOPY((g_aucSTART_TXV_R), (c_aucSTART_TXV_R_SedanH)); +/* ------------------------------------------Start control: End*/ + M_MEMCOPY((g_assFAILURE_AMB_TEMP), (c_assFAILURE_AMB_TEMP_SedanH)); + M_MEMCOPY((g_assAC_PRESSURE_LOW_HYS_UP), (c_assAC_PRESSURE_LOW_HYS_UP_SedanH)); + M_MEMCOPY((g_assAC_PRESSURE_LOW_HYS_DN), (c_assAC_PRESSURE_LOW_HYS_DN_SedanH)); + M_MEMCOPY((g_assAC_LOW_AMB_F), (c_assAC_LOW_AMB_F_SedanH)); + M_MEMCOPY((g_assAC_CUT_OFF_AMB_F), (c_assAC_CUT_OFF_AMB_F_SedanH)); + M_MEMCOPY((g_assAC_WINTER_TXV_DEWPOINT), (c_assAC_WINTER_TXV_DEWPOINT_SedanH)); + M_MEMCOPY((g_assAC_CUT_OFF_AMB_R), (c_assAC_CUT_OFF_AMB_R_SedanH)); + M_MEMCOPY((g_assEVA_TG_AMB_F), (c_assEVA_TG_AMB_F_SedanH)); + M_MEMCOPY((g_assEVA_TG_AMB_R), (c_assEVA_TG_AMB_R_SedanH)); + g_ucAC_EXTRA_RPM = c_ucAC_EXTRA_RPM_SedanH; + M_MEMCOPY((g_assAC_EVA_LV_SHUT_OFF), (c_assAC_EVA_LV_SHUT_OFF_SedanH)); + M_MEMCOPY((g_assAC_PRESSURE_HYS_HI_ENG_ON), (c_assAC_PRESSURE_HYS_HI_ENG_ON_SedanH)); + g_usCMP_MAX_ENG_OFF = c_usCMP_MAX_ENG_OFF_SedanH; + g_ucFAN_MAX_ENG_OFF = c_ucFAN_MAX_ENG_OFF_SedanH; + g_ssAC_WINTER_TXV_HYST = c_ssAC_WINTER_TXV_HYST_SedanH; + M_MEMCOPY((g_aucAC_PRESSURE_HYS_HI_ENG_OFF), (c_aucAC_PRESSURE_HYS_HI_ENG_OFF_SedanH)); + M_MEMCOPY((g_ausCMP_RPM_RESONANCE), (c_ausCMP_RPM_RESONANCE_SedanH)); +/* ------------------------------------------A/C Control Pressure : End*/ + M_MEMCOPY((g_assPRESSURE_TO_FAN_X), (c_assPRESSURE_TO_FAN_X_SedanH)); + M_MEMCOPY((g_aucPRESSURE_TO_FAN_Y), (c_aucPRESSURE_TO_FAN_Y_SedanH)); +/* ------------------------------------------CoolingFan: End*/ + g_ssREST_BATT = c_ssREST_BATT_SedanH; + g_ssRESTW_AMB = c_ssRESTW_AMB_SedanH; + M_MEMCOPY((g_assRESTW_WATER), (c_assRESTW_WATER_SedanH)); + g_usRESTW_READYEXPIRETIME = c_usRESTW_READYEXPIRETIME_SedanH; + M_MEMCOPY((g_aucRESTW_MODE), (c_aucRESTW_MODE_SedanH)); + g_usRESTW_TIMEOUTTIME = c_usRESTW_TIMEOUTTIME_SedanH; + g_ucRESTW_BLRSTEP = c_ucRESTW_BLRSTEP_SedanH; + g_ssRESTS_AMB = c_ssRESTS_AMB_SedanH; + g_uctRESTS_READYEXPIRETIME = c_uctRESTS_READYEXPIRETIME_SedanH; + M_MEMCOPY((g_aucRESTS_MODE), (c_aucRESTS_MODE_SedanH)); + g_usRESTS_TIMEOUTTIME = c_usRESTS_TIMEOUTTIME_SedanH; + g_ucRESTS_BLRSTEP = c_ucRESTS_BLRSTEP_SedanH; +/* ------------------------------------------Rest mode: End*/ + g_usFRESH_AIR_PURGE_ENTRY_TIME = c_usFRESH_AIR_PURGE_ENTRY_TIME_SedanH; + M_MEMCOPY((g_ausFRESH_AIR_PURGE_CHANGE_TIME), (c_ausFRESH_AIR_PURGE_CHANGE_TIME_SedanH)); +/* ------------------------------------------Purge Rec: End*/ + M_MEMCOPY((g_assMAX_DEF_U_DTG), (c_assMAX_DEF_U_DTG_SedanH)); + M_MEMCOPY((g_ausMAX_BLR_SPD), (c_ausMAX_BLR_SPD_SedanH)); +/* ------------------------------------------MAX DEF: End*/ + M_MEMCOPY((g_aucAQS_REC_LV_CO), (c_aucAQS_REC_LV_CO_SedanH)); + M_MEMCOPY((g_aucAQS_OSA_LV_CO), (c_aucAQS_OSA_LV_CO_SedanH)); + M_MEMCOPY((g_aucAQS_REC_LV_NOX), (c_aucAQS_REC_LV_NOX_SedanH)); + M_MEMCOPY((g_aucAQS_OSA_LV_NOX), (c_aucAQS_OSA_LV_NOX_SedanH)); + M_MEMCOPY((g_aucAQS_REC_LV_NH3), (c_aucAQS_REC_LV_NH3_SedanH)); + M_MEMCOPY((g_aucAQS_OSA_LV_NH3), (c_aucAQS_OSA_LV_NH3_SedanH)); + g_ucAQS_REC_ON_TIME = c_ucAQS_REC_ON_TIME_SedanH; + M_MEMCOPY((g_aucAQS_REC_ON_WAIT), (c_aucAQS_REC_ON_WAIT_SedanH)); +/* ------------------------------------------Aqs: End*/ + g_usAUTODEMIST_LV2_BLR_PLUS = c_usAUTODEMIST_LV2_BLR_PLUS_SedanH; + g_usAUTODEMIST_LV3_BLR_PLUS = c_usAUTODEMIST_LV3_BLR_PLUS_SedanH; + M_MEMCOPY((g_assAUTODEMIST_OFFSET_AMB_TEMP), (c_assAUTODEMIST_OFFSET_AMB_TEMP_SedanH)); + M_MEMCOPY((g_assAUTODEMIST_OFFSET_VENT_TEMP), (c_assAUTODEMIST_OFFSET_VENT_TEMP_SedanH)); + M_MEMCOPY((g_assAUTODEMIST_STEP_UP), (c_assAUTODEMIST_STEP_UP_SedanH)); + M_MEMCOPY((g_assAUTODEMIST_STEP_DN), (c_assAUTODEMIST_STEP_DN_SedanH)); + M_MEMCOPY((g_assAUTODEMIST_WINTER), (c_assAUTODEMIST_WINTER_SedanH)); +/* ------------------------------------------Auto Demist: End*/ + g_ssAUTODEMIST_ELEC_AMB_ENTRY = c_ssAUTODEMIST_ELEC_AMB_ENTRY_SedanH; + M_MEMCOPY((g_assAUTODEMIST_ELEC_WINDSHELD_TEMP), (c_assAUTODEMIST_ELEC_WINDSHELD_TEMP_SedanH)); +/* ------------------------------------------Electric AutoDemist: End*/ + g_ssAMBFILT_WATER = c_ssAMBFILT_WATER_SedanH; + M_MEMCOPY((g_aucAMBFILT_H_CNT), (c_aucAMBFILT_H_CNT_SedanH)); + g_ssAMB_FAILSAFE = c_ssAMB_FAILSAFE_SedanH; + g_ssAMBKEEP_KAT = c_ssAMBKEEP_KAT_SedanH; + g_ssAMBKEEP_KAT_PLUS = c_ssAMBKEEP_KAT_PLUS_SedanH; + g_ssAMBKEEP_WATER = c_ssAMBKEEP_WATER_SedanH; + M_MEMCOPY((g_aucAMBRATE_RISING), (c_aucAMBRATE_RISING_SedanH)); + M_MEMCOPY((g_aucAMBRATE_FALLING), (c_aucAMBRATE_FALLING_SedanH)); + M_MEMCOPY((g_aucAMBRATE_RISING_DIFF), (c_aucAMBRATE_RISING_DIFF_SedanH)); + M_MEMCOPY((g_aucAMBRATE_FALLING_DIFF), (c_aucAMBRATE_FALLING_DIFF_SedanH)); +/* ------------------------------------------Ambient: End*/ + M_MEMCOPY((g_ausINCARRATE_RISING_F), (c_ausINCARRATE_RISING_F_SedanH)); + M_MEMCOPY((g_ausINCARRATE_FALLING_F), (c_ausINCARRATE_FALLING_F_SedanH)); + M_MEMCOPY((g_ausINCARRATE_RISING_DIFF_F), (c_ausINCARRATE_RISING_DIFF_F_SedanH)); + M_MEMCOPY((g_ausINCARRATE_FALLING_DIFF_F), (c_ausINCARRATE_FALLING_DIFF_F_SedanH)); + M_MEMCOPY((g_ausINCARRATE_RISING_R), (c_ausINCARRATE_RISING_R_SedanH)); + M_MEMCOPY((g_ausINCARRATE_FALLING_R), (c_ausINCARRATE_FALLING_R_SedanH)); + M_MEMCOPY((g_ausINCARRATE_RISING_DIFF_R), (c_ausINCARRATE_RISING_DIFF_R_SedanH)); + M_MEMCOPY((g_ausINCARRATE_FALLING_DIFF_R), (c_ausINCARRATE_FALLING_DIFF_R_SedanH)); +/* ------------------------------------------Incar: End*/ + M_MEMCOPY((g_ausSUNRATE_RISING), (c_ausSUNRATE_RISING_SedanH)); + M_MEMCOPY((g_ausSUNRATE_FALLING), (c_ausSUNRATE_FALLING_SedanH)); +/* ------------------------------------------Sun: End*/ + M_MEMCOPY((g_ausAMB_LV_CHANGE_UNIT), (c_ausAMB_LV_CHANGE_UNIT_SedanH)); + M_MEMCOPY((g_aucAMB_LV_CHANGE_SEC), (c_aucAMB_LV_CHANGE_SEC_SedanH)); +/* ------------------------------------------Level Chage: End*/ + g_ssTHREEWAY_WATER = c_ssTHREEWAY_WATER_SedanH; + M_MEMCOPY((g_assTHREEWAY_DUCT_TGT_R), (c_assTHREEWAY_DUCT_TGT_R_SedanH)); + M_MEMCOPY((g_aucTHEREEWAY_EXPIRING), (c_aucTHEREEWAY_EXPIRING_SedanH)); +/* ------------------------------------------Three way: End*/ + M_MEMCOPY((g_assTWOWAY_REAR_DUCTTGT_R), (c_assTWOWAY_REAR_DUCTTGT_R_SedanH)); + M_MEMCOPY((g_aucTWOWAY_EXPIRING), (c_aucTWOWAY_EXPIRING_SedanH)); +/* ------------------------------------------two-way: End*/ + M_MEMCOPY((g_aucACT_HOM_SPD_FL_CH0), (c_aucACT_HOM_SPD_FL_CH0_SedanH)); + M_MEMCOPY((g_aucACT_HOM_SPD_FR_CH1), (c_aucACT_HOM_SPD_FR_CH1_SedanH)); + M_MEMCOPY((g_aucACT_HOM_SPD_R_CH2), (c_aucACT_HOM_SPD_R_CH2_SedanH)); + M_MEMCOPY((g_aucACT_HOM_SPD_R_EX_CH2), (c_aucACT_HOM_SPD_R_EX_CH2_SedanH)); + M_MEMCOPY((g_aucACT_MOV_SPD_FL_CH0), (c_aucACT_MOV_SPD_FL_CH0_SedanH)); + M_MEMCOPY((g_aucACT_MOV_SPD_FR_CH1), (c_aucACT_MOV_SPD_FR_CH1_SedanH)); + M_MEMCOPY((g_aucACT_MOV_SPD_R_CH2), (c_aucACT_MOV_SPD_R_CH2_SedanH)); + M_MEMCOPY((g_aucACT_MOV_SPD_R_EX_CH2), (c_aucACT_MOV_SPD_R_EX_CH2_SedanH)); +/* ------------------------------------------Actuator Homing: End*/ + M_MEMCOPY((g_assHI_MODE_ENG_TMEP), (c_assHI_MODE_ENG_TMEP_SedanH)); + M_MEMCOPY((g_aucHI_MODE_BLR_STEP_STS), (c_aucHI_MODE_BLR_STEP_STS_SedanH)); +/* ------------------------------------------Hi Mode: End*/ + M_MEMCOPY((g_ausMinusAF_GlassPos_L), (c_ausMinusAF_GlassPos_L_SedanH)); + M_MEMCOPY((g_ausMinusAF_GlassPos_R), (c_ausMinusAF_GlassPos_R_SedanH)); +/* ------------------------------------------GlassPosition: End*/ + M_MEMCOPY((g_assFoot2_Lv3_Amb), (c_assFoot2_Lv3_Amb_SedanH)); + M_MEMCOPY((g_assFoot2_Lv4_Amb), (c_assFoot2_Lv4_Amb_SedanH)); + M_MEMCOPY((g_assFoot2_Lv5_Amb), (c_assFoot2_Lv5_Amb_SedanH)); + M_MEMCOPY((g_assFoot2_Lv3_DuctTgt_Plus), (c_assFoot2_Lv3_DuctTgt_Plus_SedanH)); + M_MEMCOPY((g_assFoot2_Lv4_DuctTgt_Plus), (c_assFoot2_Lv4_DuctTgt_Plus_SedanH)); + M_MEMCOPY((g_assFoot2_Lv5_DuctTgt_Plus), (c_assFoot2_Lv5_DuctTgt_Plus_SedanH)); + M_MEMCOPY((g_ausFoot2_Lv1_FrontBlr_X), (c_ausFoot2_Lv1_FrontBlr_X_SedanH)); + M_MEMCOPY((g_ausFoot2_Lv1_Foot2Act_Y), (c_ausFoot2_Lv1_Foot2Act_Y_SedanH)); + M_MEMCOPY((g_assFoot2_Lv2_Threshold_Diff), (c_assFoot2_Lv2_Threshold_Diff_SedanH)); + M_MEMCOPY((g_assFoot2_Lv3_Threshold_Diff), (c_assFoot2_Lv3_Threshold_Diff_SedanH)); +/* ------------------------------------------Foot2 Ctrl: End*/ + M_MEMCOPY((g_ausDbF_Side_Af_Bi), (c_ausDbF_Side_Af_Bi_SedanH)); + M_MEMCOPY((g_ausDbF_Side_Af_Bi2), (c_ausDbF_Side_Af_Bi2_SedanH)); + M_MEMCOPY((g_ausDbF_Side_Af_Vent), (c_ausDbF_Side_Af_Vent_SedanH)); + M_MEMCOPY((g_ausDbF_Side_Bi_Bi2), (c_ausDbF_Side_Bi_Bi2_SedanH)); + M_MEMCOPY((g_ausDbF_Side_Bi_Vent), (c_ausDbF_Side_Bi_Vent_SedanH)); + M_MEMCOPY((g_ausDbF_Side_Bi2_Vent), (c_ausDbF_Side_Bi2_Vent_SedanH)); + M_MEMCOPY((g_ausDbF_Cen_Af_Bi), (c_ausDbF_Cen_Af_Bi_SedanH)); + M_MEMCOPY((g_ausDbF_Cen_Af_Bi2), (c_ausDbF_Cen_Af_Bi2_SedanH)); + M_MEMCOPY((g_ausDbF_Cen_Af_Vent), (c_ausDbF_Cen_Af_Vent_SedanH)); + M_MEMCOPY((g_ausDbF_Cen_Bi_Bi2), (c_ausDbF_Cen_Bi_Bi2_SedanH)); + M_MEMCOPY((g_ausDbF_Cen_Bi_Vent), (c_ausDbF_Cen_Bi_Vent_SedanH)); + M_MEMCOPY((g_ausDbF_Cen_Bi2_Vent), (c_ausDbF_Cen_Bi2_Vent_SedanH)); + M_MEMCOPY((g_ausDbF_Foot_Af_Bi), (c_ausDbF_Foot_Af_Bi_SedanH)); + M_MEMCOPY((g_ausDbF_Foot_Af_Bi2), (c_ausDbF_Foot_Af_Bi2_SedanH)); + M_MEMCOPY((g_ausDbF_Foot_Af_Vent), (c_ausDbF_Foot_Af_Vent_SedanH)); + M_MEMCOPY((g_ausDbF_Foot_Bi_Bi2), (c_ausDbF_Foot_Bi_Bi2_SedanH)); + M_MEMCOPY((g_ausDbF_Foot_Bi_Vent), (c_ausDbF_Foot_Bi_Vent_SedanH)); + M_MEMCOPY((g_ausDbF_Foot_Bi2_Vent), (c_ausDbF_Foot_Bi2_Vent_SedanH)); + M_MEMCOPY((g_ausDbF_AF_Af_Bi), (c_ausDbF_AF_Af_Bi_SedanH)); + M_MEMCOPY((g_ausDbF_AF_Af_Bi2), (c_ausDbF_AF_Af_Bi2_SedanH)); + M_MEMCOPY((g_ausDbF_AF_Af_Vent), (c_ausDbF_AF_Af_Vent_SedanH)); + M_MEMCOPY((g_ausDbF_AF_Bi_Bi2), (c_ausDbF_AF_Bi_Bi2_SedanH)); + M_MEMCOPY((g_ausDbF_AF_Bi_Vent), (c_ausDbF_AF_Bi_Vent_SedanH)); + M_MEMCOPY((g_ausDbF_AF_Bi2_Vent), (c_ausDbF_AF_Bi2_Vent_SedanH)); + M_MEMCOPY((g_ausDbF_Pwm_Af_Bi), (c_ausDbF_Pwm_Af_Bi_SedanH)); + M_MEMCOPY((g_ausDbF_Pwm_Af_Bi2), (c_ausDbF_Pwm_Af_Bi2_SedanH)); + M_MEMCOPY((g_ausDbF_Pwm_Af_Vent), (c_ausDbF_Pwm_Af_Vent_SedanH)); + M_MEMCOPY((g_ausDbF_Pwm_Bi_Bi2), (c_ausDbF_Pwm_Bi_Bi2_SedanH)); + M_MEMCOPY((g_ausDbF_Pwm_Bi_Vent), (c_ausDbF_Pwm_Bi_Vent_SedanH)); + M_MEMCOPY((g_ausDbF_Pwm_Bi2_Vent), (c_ausDbF_Pwm_Bi2_Vent_SedanH)); +/* ------------------------------------------Different blower Front: End*/ + g_usAromaPwm_Min = c_usAromaPwm_Min_SedanH; + g_usAromaPwm_Max = c_usAromaPwm_Max_SedanH; +/* ------------------------------------------Aroma Limit Pwm: End*/ +/*********************************************************Cal Table End*/ + +} +/****************************************************************************** + * LOCAL FUNCTIONS + *****************************************************************************/ +/* End of Excel line : 2159 */ +/****************************************************************************** + * EOF + *****************************************************************************/ diff --git a/MODULES/HVAC_M7_DataNonVolatile/calib/Rs_Cal_1_SedanH.h b/MODULES/HVAC_M7_DataNonVolatile/calib/Rs_Cal_1_SedanH.h new file mode 100644 index 0000000..25b705c --- /dev/null +++ b/MODULES/HVAC_M7_DataNonVolatile/calib/Rs_Cal_1_SedanH.h @@ -0,0 +1,38 @@ +/** Doxygen: File brief + ****************************************************************************** + * @file Rs_Cal_1_SedanH.h + * @brief No brief + * @remark Generated by C:\9999\Rs_Cal_R23_ver21_SedanL.xlsm + * Generated on yyyy-mm-dd hh:mm:ss + *****************************************************************************/ +#ifndef RS_CAL_1_SEDANH_H__ +#define RS_CAL_1_SEDANH_H__ + +/****************************************************************************** + * INCLUDE FILES +*****************************************************************************/ +#include "rtwtypes.h" +#include "common.h" +#include "HVAC_preDefine.h" +#include "Rs_Cal_Base.h" + +/****************************************************************************** + * MACRO DECLARATIONS + *****************************************************************************/ +/****************************************************************************** + * GLOBAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS) + *****************************************************************************/ +/****************************************************************************** + * GLOBAL VARIABLES DECLARATIONS + *****************************************************************************/ +extern SECT_VEH_CAL_1 const tU08 c_ucCalFromRelease_SedanH; +/****************************************************************************** + * GLOBAL FUNCTIONS DECLARATIONS + *****************************************************************************/ +extern void Rs_Cal_1_SedanH(void); + +/* End of Excel line : 34 */ +#endif /*RS_CAL_1_SEDANH_H__*/ +/****************************************************************************** + * EOF + *****************************************************************************/ diff --git a/MODULES/HVAC_M7_DataNonVolatile/calib/Rs_Cal_2_Limo.c b/MODULES/HVAC_M7_DataNonVolatile/calib/Rs_Cal_2_Limo.c new file mode 100644 index 0000000..9647c75 --- /dev/null +++ b/MODULES/HVAC_M7_DataNonVolatile/calib/Rs_Cal_2_Limo.c @@ -0,0 +1,2162 @@ +/** Doxygen: File brief + ****************************************************************************** + * @file Rs_Cal_2_Limo.c + * @brief No brief + * @remark Generated by C:\9999\Rs_Cal_R23_ver21_SedanL.xlsm + * Generated on yyyy-mm-dd hh:mm:ss + *****************************************************************************/ +/****************************************************************************** + * INCLUDE FILES + *****************************************************************************/ +#include "Rs_Cal_2_Limo.h" + +/****************************************************************************** + * MACRO DECLARATIONS + *****************************************************************************/ +/*PRQA S 0615 EOF #suppress : More than 511 block scope identifiers, from Calibration data table, No impact*/ +/*PRQA S 1514 EOF #suppress : In the same translation(used != defined), from Calibration data table, No impact*/ +/*PRQA S 3408 EOF #suppress : To manage Cal. data separately, from Calibration data table, No Impact*/ +/****************************************************************************** + * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS) + *****************************************************************************/ +/****************************************************************************** + * GLOBAL VARIABLES DECLARATIONS + *****************************************************************************/ +SECT_VEH_CAL_2 const tU08 c_ucCalFromRelease_Limo = ID_TRUE; +SECT_VEH_CAL_2 const tU08 c_aucCAL_FP_DATE_Limo[3] = { VERSION_LIMO_Y, VERSION_LIMO_M, VERSION_LIMO_D}; +SECT_VEH_CAL_2 const tU08 c_aucCAL_VERSION_Limo[2] = { 0, 20}; +SECT_VEH_CAL_2 const tU08 c_ucCAL_VARIANT_Limo = 3; +/* ------------------------------------------Cal Version : End*/ +SECT_VEH_CAL_2 const tU16 c_ausSET_TEMP_FULL_Limo[13] = { 170, 180, 190, 200, 210, 220, 230, 240, 250, 260, 270, 280, 290}; +SECT_VEH_CAL_2 const tU16 c_ausSET_TEMP_HALF_Limo[7] = { 170, 190, 210, 230, 250, 270, 290}; +/* ------------------------------------------Set Temp : End*/ +SECT_VEH_CAL_2 const tS16 c_assINCAR_TG_FL_LV0_Limo[13] = { 180, 190, 200, 210, 220, 230, 240, 250, 270, 280, 290, 300, 310}; +SECT_VEH_CAL_2 const tS16 c_assINCAR_TG_FR_LV0_Limo[13] = { 180, 190, 200, 210, 220, 230, 240, 250, 270, 280, 290, 300, 310}; +SECT_VEH_CAL_2 const tS16 c_assVTG_FL_LV0_Limo[13] = { 105, 105, 105, 105, 105, 105, 105, 105, 105, 105, 105, 105, 105}; +SECT_VEH_CAL_2 const tS16 c_assVTG_FR_LV0_Limo[13] = { 105, 105, 105, 105, 105, 105, 105, 105, 105, 105, 105, 105, 105}; +SECT_VEH_CAL_2 const tS16 c_assVF_MIN_LV0_Limo[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tS16 c_assVF_MAX_LV0_Limo[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_Y1_LV0_Limo[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_Y2_LV0_Limo[7] = { 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_Y3_LV0_Limo[7] = { -5, -5, -5, -5, -5, -5, -5}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_Y4_LV0_Limo[7] = { -10, -10, -10, -10, -10, -10, -10}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_X1_LV0_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_X2_LV0_Limo[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_X3_LV0_Limo[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_X4_LV0_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assVF_AMB_Y1_LV0_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVF_AMB_Y2_LV0_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVF_AMB_X1_LV0_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assVF_AMB_X2_LV0_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assVF_SUN_Y1_LV0_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVF_SUN_Y2_LV0_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVF_SUN_X1_LV0_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assVF_SUN_X2_LV0_Limo[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_2 const tS16 c_assTG_FLU_LV0_Limo[13] = { 20, 20, 50, 55, 60, 80, 120, 220, 260, 350, 390, 420, 450}; +SECT_VEH_CAL_2 const tS16 c_assTG_FRU_LV0_Limo[13] = { 20, 20, 50, 55, 60, 80, 120, 220, 260, 350, 390, 420, 450}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_MIN_LV0_Limo[7] = { 20, 20, 20, 50, 50, 50, 50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_MAX_LV0_Limo[7] = { 600, 600, 600, 600, 600, 600, 600}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_Y1_LV0_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_Y2_LV0_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_Y3_LV0_Limo[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_Y4_LV0_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_X1_LV0_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_X2_LV0_Limo[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_X3_LV0_Limo[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_X4_LV0_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_AMB_Y1_LV0_Limo[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_AMB_Y2_LV0_Limo[7] = { 50, 60, 80, 50, 50, 50, 50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_AMB_X1_LV0_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_AMB_X2_LV0_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_SUN_Y1_LV0_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_SUN_Y2_LV0_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_SUN_X1_LV0_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_SUN_X2_LV0_Limo[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_2 const tS16 c_assTG_FLL_LV0_Limo[13] = { 150, 200, 250, 265, 280, 290, 300, 400, 450, 500, 600, 650, 800}; +SECT_VEH_CAL_2 const tS16 c_assTG_FRL_LV0_Limo[13] = { 150, 200, 250, 265, 280, 290, 300, 400, 450, 500, 600, 650, 800}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_MIN_LV0_Limo[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_MAX_LV0_Limo[7] = { 400, 450, 500, 600, 600, 600, 600}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_Y1_LV0_Limo[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_Y2_LV0_Limo[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_Y3_LV0_Limo[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_Y4_LV0_Limo[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_X1_LV0_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_X2_LV0_Limo[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_X3_LV0_Limo[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_X4_LV0_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_AMB_Y1_LV0_Limo[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_AMB_Y2_LV0_Limo[7] = { 60, 60, 60, 60, 60, 60, 60}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_AMB_X1_LV0_Limo[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_AMB_X2_LV0_Limo[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_SUN_Y1_LV0_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_SUN_Y2_LV0_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_SUN_X1_LV0_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_SUN_X2_LV0_Limo[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_2 const tS16 c_assINCAR_TG_RL_LV0_Limo[13] = { 190, 195, 200, 215, 230, 240, 250, 270, 280, 290, 300, 310, 320}; +SECT_VEH_CAL_2 const tS16 c_assINCAR_TG_RR_LV0_Limo[13] = { 190, 195, 200, 215, 230, 240, 250, 270, 280, 290, 300, 310, 320}; +SECT_VEH_CAL_2 const tS16 c_assVTG_RL_LV0_Limo[13] = { 90, 85, 80, 75, 70, 65, 60, 62, 64, 66, 80, 85, 90}; +SECT_VEH_CAL_2 const tS16 c_assVTG_RR_LV0_Limo[13] = { 90, 85, 80, 75, 70, 65, 60, 62, 64, 66, 80, 85, 90}; +SECT_VEH_CAL_2 const tS16 c_assVR_MIN_LV0_Limo[7] = { 80, 80, 40, 40, 40, 30, 30}; +SECT_VEH_CAL_2 const tS16 c_assVR_MAX_LV0_Limo[7] = { 160, 160, 160, 160, 100, 80, 80}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_Y1_LV0_Limo[7] = { 10, 10, 10, 5, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_Y2_LV0_Limo[7] = { 5, 5, 5, 2, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_Y3_LV0_Limo[7] = { -5, -5, -5, -5, -5, -5, -5}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_Y4_LV0_Limo[7] = { -10, -10, -10, -10, -10, -10, -10}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_X1_LV0_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_X2_LV0_Limo[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_X3_LV0_Limo[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_X4_LV0_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assVR_AMB_Y1_LV0_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVR_AMB_Y2_LV0_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVR_AMB_X1_LV0_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assVR_AMB_X2_LV0_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assVR_SUN_Y1_LV0_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVR_SUN_Y2_LV0_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVR_SUN_X1_LV0_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assVR_SUN_X2_LV0_Limo[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_2 const tS16 c_assTG_RL_LV0_Limo[13] = { 30, 30, 30, 50, 90, 100, 120, 180, 240, 320, 400, 450, 500}; +SECT_VEH_CAL_2 const tS16 c_assTG_RR_LV0_Limo[13] = { 30, 30, 30, 50, 90, 100, 120, 180, 240, 320, 400, 450, 500}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_MIN_LV0_Limo[7] = { 20, 20, 20, 20, 50, 50, 50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_MAX_LV0_Limo[7] = { 200, 250, 300, 450, 600, 600, 600}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_Y1_LV0_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_Y2_LV0_Limo[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_Y3_LV0_Limo[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_Y4_LV0_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_X1_LV0_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_X2_LV0_Limo[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_X3_LV0_Limo[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_X4_LV0_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_AMB_Y1_LV0_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_AMB_Y2_LV0_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_AMB_X1_LV0_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_AMB_X2_LV0_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_SUN_Y1_LV0_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_SUN_Y2_LV0_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_SUN_X1_LV0_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_SUN_X2_LV0_Limo[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_DUCT_TIME_FR_LV0_Limo[7] = { 600, 600, 600, 600, 600, 600, 600}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_DUCT_TIME_FL_LV0_Limo[7] = { 600, 600, 600, 600, 600, 600, 600}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_DUCT_RATE_LV0_Limo[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_DUCT_MAX_LV0_Limo[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_AF_TIME_FR_LV0_Limo[7] = { 3000, 3000, 3000, 3000, 3000, 3000, 3000}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_AF_TIME_FL_LV0_Limo[7] = { 3000, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_AF_RATE_LV0_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_AF_MAX_LV0_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +/* ------------------------------------------Lv0 : End*/ +SECT_VEH_CAL_2 const tS16 c_assINCAR_TG_FL_LV1_Limo[13] = { 200, 220, 240, 250, 260, 270, 280, 290, 300, 310, 320, 330, 340}; +SECT_VEH_CAL_2 const tS16 c_assINCAR_TG_FR_LV1_Limo[13] = { 200, 220, 240, 250, 260, 270, 280, 290, 300, 310, 320, 330, 340}; +SECT_VEH_CAL_2 const tS16 c_assVTG_FL_LV1_Limo[13] = { 100, 95, 90, 85, 80, 75, 70, 70, 70, 70, 70, 70, 70}; +SECT_VEH_CAL_2 const tS16 c_assVTG_FR_LV1_Limo[13] = { 100, 95, 90, 85, 80, 75, 70, 70, 70, 70, 70, 70, 70}; +SECT_VEH_CAL_2 const tS16 c_assVF_MIN_LV1_Limo[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_2 const tS16 c_assVF_MAX_LV1_Limo[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_Y1_LV1_Limo[7] = { 10, 10, 10, 10, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_Y2_LV1_Limo[7] = { 5, 5, 5, 5, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_Y3_LV1_Limo[7] = { -5, -5, -5, -5, -5, -5, -5}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_Y4_LV1_Limo[7] = { -10, -10, -10, -10, -10, -10, -10}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_X1_LV1_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_X2_LV1_Limo[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_X3_LV1_Limo[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_X4_LV1_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assVF_AMB_Y1_LV1_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVF_AMB_Y2_LV1_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVF_AMB_X1_LV1_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assVF_AMB_X2_LV1_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assVF_SUN_Y1_LV1_Limo[7] = { 5, 5, 5, 5, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVF_SUN_Y2_LV1_Limo[7] = { 15, 15, 15, 15, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVF_SUN_X1_LV1_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assVF_SUN_X2_LV1_Limo[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_2 const tS16 c_assTG_FLU_LV1_Limo[13] = { 20, 20, 50, 55, 60, 80, 120, 150, 180, 210, 240, 270, 300}; +SECT_VEH_CAL_2 const tS16 c_assTG_FRU_LV1_Limo[13] = { 20, 20, 50, 55, 60, 80, 120, 150, 180, 210, 240, 270, 300}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_MIN_LV1_Limo[7] = { 20, 20, 20, 20, 50, 50, 50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_MAX_LV1_Limo[7] = { 400, 450, 450, 500, 600, 600, 600}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_Y1_LV1_Limo[7] = { 0, 0, 0, -80, -100, -150, -200}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_Y2_LV1_Limo[7] = { 0, 0, 0, -50, -60, -70, -100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_Y3_LV1_Limo[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_Y4_LV1_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_X1_LV1_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_X2_LV1_Limo[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_X3_LV1_Limo[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_X4_LV1_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_AMB_Y1_LV1_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_AMB_Y2_LV1_Limo[7] = { 15, 16, 43, 40, 52, 73, 95}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_AMB_X1_LV1_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_AMB_X2_LV1_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_SUN_Y1_LV1_Limo[7] = { -60, -60, -60, -60, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_SUN_Y2_LV1_Limo[7] = { -120, -120, -120, -120, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_SUN_X1_LV1_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_SUN_X2_LV1_Limo[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_2 const tS16 c_assTG_FLL_LV1_Limo[13] = { 150, 200, 250, 265, 280, 290, 300, 320, 340, 360, 380, 400, 400}; +SECT_VEH_CAL_2 const tS16 c_assTG_FRL_LV1_Limo[13] = { 150, 200, 250, 265, 280, 290, 300, 320, 340, 360, 380, 400, 400}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_MIN_LV1_Limo[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_MAX_LV1_Limo[7] = { 700, 700, 700, 700, 700, 700, 700}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_Y1_LV1_Limo[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_Y2_LV1_Limo[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_Y3_LV1_Limo[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_Y4_LV1_Limo[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_X1_LV1_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_X2_LV1_Limo[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_X3_LV1_Limo[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_X4_LV1_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_AMB_Y1_LV1_Limo[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_AMB_Y2_LV1_Limo[7] = { 105, 35, 50, 80, 140, 190, 225}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_AMB_X1_LV1_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_AMB_X2_LV1_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_SUN_Y1_LV1_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_SUN_Y2_LV1_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_SUN_X1_LV1_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_SUN_X2_LV1_Limo[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_2 const tS16 c_assINCAR_TG_RL_LV1_Limo[13] = { 190, 195, 200, 215, 230, 240, 250, 260, 270, 280, 290, 300, 310}; +SECT_VEH_CAL_2 const tS16 c_assINCAR_TG_RR_LV1_Limo[13] = { 190, 195, 200, 215, 230, 240, 250, 260, 270, 280, 290, 300, 310}; +SECT_VEH_CAL_2 const tS16 c_assVTG_RL_LV1_Limo[13] = { 90, 85, 75, 70, 62, 55, 50, 56, 64, 66, 68, 70, 70}; +SECT_VEH_CAL_2 const tS16 c_assVTG_RR_LV1_Limo[13] = { 90, 85, 75, 70, 62, 55, 50, 56, 64, 66, 68, 70, 70}; +SECT_VEH_CAL_2 const tS16 c_assVR_MIN_LV1_Limo[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_2 const tS16 c_assVR_MAX_LV1_Limo[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_Y1_LV1_Limo[7] = { 70, 70, 65, 60, 20, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_Y2_LV1_Limo[7] = { 30, 30, 30, 25, 15, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_Y3_LV1_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_Y4_LV1_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_X1_LV1_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_X2_LV1_Limo[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_X3_LV1_Limo[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_X4_LV1_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assVR_AMB_Y1_LV1_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVR_AMB_Y2_LV1_Limo[7] = { 0, 0, -2, 0, 0, -1, 2}; +SECT_VEH_CAL_2 const tS16 c_assVR_AMB_X1_LV1_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assVR_AMB_X2_LV1_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assVR_SUN_Y1_LV1_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVR_SUN_Y2_LV1_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVR_SUN_X1_LV1_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assVR_SUN_X2_LV1_Limo[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_2 const tS16 c_assTG_RL_LV1_Limo[13] = { 20, 20, 50, 80, 90, 100, 150, 160, 170, 185, 200, 220, 240}; +SECT_VEH_CAL_2 const tS16 c_assTG_RR_LV1_Limo[13] = { 20, 20, 50, 80, 90, 100, 150, 160, 170, 185, 200, 220, 240}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_MIN_LV1_Limo[7] = { 20, 20, 20, 50, 50, 50, 50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_MAX_LV1_Limo[7] = { 200, 250, 300, 450, 600, 600, 600}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_Y1_LV1_Limo[7] = { -100, -100, -80, -80, -80, -80, -80}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_Y2_LV1_Limo[7] = { -80, -80, -60, -50, -50, -50, -50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_Y3_LV1_Limo[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_Y4_LV1_Limo[7] = { 80, 80, 80, 80, 80, 80, 80}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_X1_LV1_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_X2_LV1_Limo[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_X3_LV1_Limo[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_X4_LV1_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_AMB_Y1_LV1_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_AMB_Y2_LV1_Limo[7] = { 0, 0, 10, 10, 15, 25, 25}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_AMB_X1_LV1_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_AMB_X2_LV1_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_SUN_Y1_LV1_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_SUN_Y2_LV1_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_SUN_X1_LV1_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_SUN_X2_LV1_Limo[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_DUCT_TIME_FR_LV1_Limo[7] = { 600, 600, 600, 600, 600, 600, 600}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_DUCT_TIME_FL_LV1_Limo[7] = { 600, 600, 600, 600, 600, 600, 600}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_DUCT_RATE_LV1_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_DUCT_MAX_LV1_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_AF_TIME_FR_LV1_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_AF_TIME_FL_LV1_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_AF_RATE_LV1_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_AF_MAX_LV1_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +/* ------------------------------------------Lv1 : End*/ +SECT_VEH_CAL_2 const tS16 c_assINCAR_TG_FL_LV2_Limo[13] = { 180, 190, 200, 210, 225, 235, 245, 255, 270, 280, 290, 300, 310}; +SECT_VEH_CAL_2 const tS16 c_assINCAR_TG_FR_LV2_Limo[13] = { 180, 190, 200, 210, 225, 235, 245, 255, 270, 280, 290, 300, 310}; +SECT_VEH_CAL_2 const tS16 c_assVTG_FL_LV2_Limo[13] = { 100, 95, 90, 85, 80, 75, 70, 70, 70, 70, 70, 70, 70}; +SECT_VEH_CAL_2 const tS16 c_assVTG_FR_LV2_Limo[13] = { 100, 95, 90, 85, 80, 75, 70, 70, 70, 70, 70, 70, 70}; +SECT_VEH_CAL_2 const tS16 c_assVF_MIN_LV2_Limo[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_2 const tS16 c_assVF_MAX_LV2_Limo[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_Y1_LV2_Limo[7] = { 10, 10, 10, 10, 10, 15, 15}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_Y2_LV2_Limo[7] = { 5, 5, 5, 5, 5, 8, 8}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_Y3_LV2_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_Y4_LV2_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_X1_LV2_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_X2_LV2_Limo[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_X3_LV2_Limo[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_X4_LV2_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assVF_AMB_Y1_LV2_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVF_AMB_Y2_LV2_Limo[7] = { -3, 0, 3, 10, 12, 16, 18}; +SECT_VEH_CAL_2 const tS16 c_assVF_AMB_X1_LV2_Limo[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_2 const tS16 c_assVF_AMB_X2_LV2_Limo[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_2 const tS16 c_assVF_SUN_Y1_LV2_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVF_SUN_Y2_LV2_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVF_SUN_X1_LV2_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assVF_SUN_X2_LV2_Limo[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_2 const tS16 c_assTG_FLU_LV2_Limo[13] = { 50, 50, 70, 100, 120, 150, 190, 230, 270, 300, 340, 380, 420}; +SECT_VEH_CAL_2 const tS16 c_assTG_FRU_LV2_Limo[13] = { 50, 50, 70, 100, 120, 150, 190, 230, 270, 300, 340, 380, 420}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_MIN_LV2_Limo[7] = { 20, 20, 20, 30, 40, 50, 50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_MAX_LV2_Limo[7] = { 450, 450, 550, 600, 600, 600, 600}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_Y1_LV2_Limo[7] = { -100, -100, -100, -100, -150, -150, -150}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_Y2_LV2_Limo[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_Y3_LV2_Limo[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_Y4_LV2_Limo[7] = { 150, 150, 150, 150, 150, 150, 150}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_X1_LV2_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_X2_LV2_Limo[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_X3_LV2_Limo[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_X4_LV2_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_AMB_Y1_LV2_Limo[7] = { -20, -10, -20, -30, -40, -30, -30}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_AMB_Y2_LV2_Limo[7] = { 0, 30, 30, 35, 20, 30, 30}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_AMB_X1_LV2_Limo[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_AMB_X2_LV2_Limo[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_SUN_Y1_LV2_Limo[7] = { -30, -30, -30, -30, -30, -30, -30}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_SUN_Y2_LV2_Limo[7] = { -80, -80, -80, -80, -80, -80, -80}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_SUN_X1_LV2_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_SUN_X2_LV2_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assTG_FLL_LV2_Limo[13] = { 250, 300, 335, 350, 360, 380, 400, 440, 480, 520, 570, 620, 680}; +SECT_VEH_CAL_2 const tS16 c_assTG_FRL_LV2_Limo[13] = { 250, 300, 335, 350, 360, 380, 400, 440, 480, 520, 570, 620, 680}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_MIN_LV2_Limo[7] = { 250, 250, 250, 250, 250, 400, 400}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_MAX_LV2_Limo[7] = { 450, 450, 500, 800, 800, 800, 800}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_Y1_LV2_Limo[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_Y2_LV2_Limo[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_Y3_LV2_Limo[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_Y4_LV2_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_X1_LV2_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_X2_LV2_Limo[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_X3_LV2_Limo[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_X4_LV2_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_AMB_Y1_LV2_Limo[7] = { -45, -50, -30, -20, 0, 0, -55}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_AMB_Y2_LV2_Limo[7] = { 70, 55, 50, 50, 100, 110, 120}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_AMB_X1_LV2_Limo[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_AMB_X2_LV2_Limo[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_SUN_Y1_LV2_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_SUN_Y2_LV2_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_SUN_X1_LV2_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_SUN_X2_LV2_Limo[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_2 const tS16 c_assINCAR_TG_RL_LV2_Limo[13] = { 190, 195, 200, 215, 230, 235, 240, 250, 260, 280, 290, 300, 310}; +SECT_VEH_CAL_2 const tS16 c_assINCAR_TG_RR_LV2_Limo[13] = { 190, 195, 200, 215, 230, 235, 240, 250, 260, 280, 290, 300, 310}; +SECT_VEH_CAL_2 const tS16 c_assVTG_RL_LV2_Limo[13] = { 100, 85, 72, 63, 58, 55, 55, 57, 59, 61, 65, 70, 75}; +SECT_VEH_CAL_2 const tS16 c_assVTG_RR_LV2_Limo[13] = { 100, 85, 72, 63, 58, 55, 55, 57, 59, 61, 65, 70, 75}; +SECT_VEH_CAL_2 const tS16 c_assVR_MIN_LV2_Limo[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_2 const tS16 c_assVR_MAX_LV2_Limo[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_Y1_LV2_Limo[7] = { 30, 30, 20, 20, 10, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_Y2_LV2_Limo[7] = { 30, 30, 30, 30, 10, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_Y3_LV2_Limo[7] = { 12, 10, 7, 5, 2, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_Y4_LV2_Limo[7] = { 25, 20, 15, 10, 5, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_X1_LV2_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_X2_LV2_Limo[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_X3_LV2_Limo[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_X4_LV2_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assVR_AMB_Y1_LV2_Limo[7] = { -10, 3, 2, -5, 5, 2, -3}; +SECT_VEH_CAL_2 const tS16 c_assVR_AMB_Y2_LV2_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVR_AMB_X1_LV2_Limo[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_2 const tS16 c_assVR_AMB_X2_LV2_Limo[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_2 const tS16 c_assVR_SUN_Y1_LV2_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVR_SUN_Y2_LV2_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVR_SUN_X1_LV2_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assVR_SUN_X2_LV2_Limo[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_2 const tS16 c_assTG_RL_LV2_Limo[13] = { 20, 20, 50, 80, 110, 130, 165, 180, 200, 220, 240, 260, 280}; +SECT_VEH_CAL_2 const tS16 c_assTG_RR_LV2_Limo[13] = { 20, 20, 50, 80, 110, 130, 165, 180, 200, 220, 240, 260, 280}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_MIN_LV2_Limo[7] = { 20, 20, 20, 20, 100, 200, 300}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_MAX_LV2_Limo[7] = { 400, 400, 450, 500, 600, 600, 800}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_Y1_LV2_Limo[7] = { -250, -250, -200, -150, -100, -50, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_Y2_LV2_Limo[7] = { -125, -125, -100, -80, -60, -40, -20}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_Y3_LV2_Limo[7] = { 100, 100, 100, 100, 125, 150, 200}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_Y4_LV2_Limo[7] = { 250, 250, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_X1_LV2_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_X2_LV2_Limo[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_X3_LV2_Limo[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_X4_LV2_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_AMB_Y1_LV2_Limo[7] = { 0, 0, -10, -5, -15, -25, -15}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_AMB_Y2_LV2_Limo[7] = { 0, 0, 0, 0, 10, 20, 20}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_AMB_X1_LV2_Limo[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_AMB_X2_LV2_Limo[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_SUN_Y1_LV2_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_SUN_Y2_LV2_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_SUN_X1_LV2_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_SUN_X2_LV2_Limo[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_DUCT_TIME_FR_LV2_Limo[7] = { 3600, 3600, 3600, 3600, 3600, 3600, 3600}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_DUCT_TIME_FL_LV2_Limo[7] = { 3600, 3600, 3600, 3600, 3600, 3600, 3600}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_DUCT_RATE_LV2_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_DUCT_MAX_LV2_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_AF_TIME_FR_LV2_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_AF_TIME_FL_LV2_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_AF_RATE_LV2_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_AF_MAX_LV2_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +/* ------------------------------------------Lv2 : End*/ +SECT_VEH_CAL_2 const tS16 c_assINCAR_TG_FL_LV3_Limo[13] = { 180, 190, 200, 210, 230, 240, 250, 260, 270, 280, 290, 300, 310}; +SECT_VEH_CAL_2 const tS16 c_assINCAR_TG_FR_LV3_Limo[13] = { 180, 190, 200, 210, 230, 240, 250, 260, 270, 280, 290, 300, 310}; +SECT_VEH_CAL_2 const tS16 c_assVTG_FL_LV3_Limo[13] = { 95, 95, 90, 85, 80, 80, 85, 85, 85, 85, 85, 87, 90}; +SECT_VEH_CAL_2 const tS16 c_assVTG_FR_LV3_Limo[13] = { 95, 95, 90, 85, 80, 80, 85, 85, 85, 85, 85, 87, 90}; +SECT_VEH_CAL_2 const tS16 c_assVF_MIN_LV3_Limo[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_2 const tS16 c_assVF_MAX_LV3_Limo[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_Y1_LV3_Limo[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_Y2_LV3_Limo[7] = { 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_Y3_LV3_Limo[7] = { 0, 0, 0, 5, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_Y4_LV3_Limo[7] = { 0, 0, 0, 10, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_X1_LV3_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_X2_LV3_Limo[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_X3_LV3_Limo[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_X4_LV3_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assVF_AMB_Y1_LV3_Limo[7] = { 2, 0, 3, -5, -3, 1, -2}; +SECT_VEH_CAL_2 const tS16 c_assVF_AMB_Y2_LV3_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVF_AMB_X1_LV3_Limo[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_2 const tS16 c_assVF_AMB_X2_LV3_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assVF_SUN_Y1_LV3_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVF_SUN_Y2_LV3_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVF_SUN_X1_LV3_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assVF_SUN_X2_LV3_Limo[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_2 const tS16 c_assTG_FLU_LV3_Limo[13] = { 50, 70, 100, 130, 170, 200, 230, 270, 320, 360, 400, 450, 500}; +SECT_VEH_CAL_2 const tS16 c_assTG_FRU_LV3_Limo[13] = { 50, 70, 100, 130, 170, 200, 230, 270, 320, 360, 400, 450, 500}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_MIN_LV3_Limo[7] = { 20, 20, 20, 30, 200, 200, 250}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_MAX_LV3_Limo[7] = { 450, 450, 550, 550, 600, 750, 700}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_Y1_LV3_Limo[7] = { -100, -100, -100, -150, -200, -250, -300}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_Y2_LV3_Limo[7] = { -30, -30, -70, -80, -50, -50, -100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_Y3_LV3_Limo[7] = { 50, 50, 50, 50, 50, 30, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_Y4_LV3_Limo[7] = { 100, 100, 100, 150, 80, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_X1_LV3_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_X2_LV3_Limo[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_X3_LV3_Limo[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_X4_LV3_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_AMB_Y1_LV3_Limo[7] = { 0, 0, -20, -5, -30, -30, -50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_AMB_Y2_LV3_Limo[7] = { 0, 10, 15, 20, 15, 25, 25}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_AMB_X1_LV3_Limo[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_AMB_X2_LV3_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_SUN_Y1_LV3_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_SUN_Y2_LV3_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_SUN_X1_LV3_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_SUN_X2_LV3_Limo[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_2 const tS16 c_assTG_FLL_LV3_Limo[13] = { 300, 300, 300, 330, 360, 390, 420, 460, 500, 540, 580, 640, 700}; +SECT_VEH_CAL_2 const tS16 c_assTG_FRL_LV3_Limo[13] = { 300, 300, 300, 330, 360, 390, 420, 460, 500, 540, 580, 640, 700}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_MIN_LV3_Limo[7] = { 200, 200, 200, 350, 370, 370, 370}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_MAX_LV3_Limo[7] = { 600, 600, 800, 800, 800, 800, 950}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_Y1_LV3_Limo[7] = { -80, -70, -60, -60, -60, -60, -60}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_Y2_LV3_Limo[7] = { -50, -45, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_Y3_LV3_Limo[7] = { 40, 40, 40, 50, 50, 60, 80}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_Y4_LV3_Limo[7] = { 100, 100, 125, 200, 200, 200, 200}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_X1_LV3_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_X2_LV3_Limo[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_X3_LV3_Limo[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_X4_LV3_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_AMB_Y1_LV3_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_AMB_Y2_LV3_Limo[7] = { 0, 0, 15, 25, 20, 10, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_AMB_X1_LV3_Limo[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_AMB_X2_LV3_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_SUN_Y1_LV3_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_SUN_Y2_LV3_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_SUN_X1_LV3_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_SUN_X2_LV3_Limo[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_2 const tS16 c_assINCAR_TG_RL_LV3_Limo[13] = { 190, 195, 200, 215, 230, 235, 240, 250, 260, 280, 290, 300, 310}; +SECT_VEH_CAL_2 const tS16 c_assINCAR_TG_RR_LV3_Limo[13] = { 190, 195, 200, 215, 230, 235, 240, 250, 260, 280, 290, 300, 310}; +SECT_VEH_CAL_2 const tS16 c_assVTG_RL_LV3_Limo[13] = { 110, 98, 85, 73, 65, 60, 57, 60, 64, 66, 68, 75, 80}; +SECT_VEH_CAL_2 const tS16 c_assVTG_RR_LV3_Limo[13] = { 110, 98, 85, 73, 65, 60, 57, 60, 64, 66, 68, 75, 80}; +SECT_VEH_CAL_2 const tS16 c_assVR_MIN_LV3_Limo[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_2 const tS16 c_assVR_MAX_LV3_Limo[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_Y1_LV3_Limo[7] = { 16, 14, 12, 8, 8, 8, 8}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_Y2_LV3_Limo[7] = { 10, 8, 6, 8, 4, 4, 4}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_Y3_LV3_Limo[7] = { 0, 2, 4, 5, 6, 8, 10}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_Y4_LV3_Limo[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_X1_LV3_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_X2_LV3_Limo[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_X3_LV3_Limo[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_X4_LV3_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assVR_AMB_Y1_LV3_Limo[7] = { -10, -13, -7, -2, -5, -3, -5}; +SECT_VEH_CAL_2 const tS16 c_assVR_AMB_Y2_LV3_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVR_AMB_X1_LV3_Limo[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_2 const tS16 c_assVR_AMB_X2_LV3_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assVR_SUN_Y1_LV3_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVR_SUN_Y2_LV3_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVR_SUN_X1_LV3_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assVR_SUN_X2_LV3_Limo[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_2 const tS16 c_assTG_RL_LV3_Limo[13] = { 20, 20, 50, 80, 110, 150, 180, 200, 220, 250, 290, 300, 330}; +SECT_VEH_CAL_2 const tS16 c_assTG_RR_LV3_Limo[13] = { 20, 20, 50, 80, 110, 150, 180, 200, 220, 250, 290, 300, 330}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_MIN_LV3_Limo[7] = { 20, 20, 20, 120, 180, 250, 300}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_MAX_LV3_Limo[7] = { 400, 400, 450, 650, 800, 800, 800}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_Y1_LV3_Limo[7] = { -30, -50, -60, -60, -60, -50, -30}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_Y2_LV3_Limo[7] = { -15, -30, -40, -50, -40, -30, -15}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_Y3_LV3_Limo[7] = { 50, 50, 50, 70, 75, 80, 80}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_Y4_LV3_Limo[7] = { 200, 200, 250, 300, 300, 350, 350}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_X1_LV3_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_X2_LV3_Limo[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_X3_LV3_Limo[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_X4_LV3_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_AMB_Y1_LV3_Limo[7] = { 0, 0, 0, -15, -10, -20, -30}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_AMB_Y2_LV3_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_AMB_X1_LV3_Limo[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_AMB_X2_LV3_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_SUN_Y1_LV3_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_SUN_Y2_LV3_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_SUN_X1_LV3_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_SUN_X2_LV3_Limo[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_DUCT_TIME_FR_LV3_Limo[7] = { 3600, 3600, 3600, 3600, 3600, 3600, 3600}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_DUCT_TIME_FL_LV3_Limo[7] = { 3600, 3600, 3600, 3600, 3600, 3600, 3600}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_DUCT_RATE_LV3_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_DUCT_MAX_LV3_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_AF_TIME_FR_LV3_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_AF_TIME_FL_LV3_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_AF_RATE_LV3_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_AF_MAX_LV3_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +/* ------------------------------------------Lv3 : End*/ +SECT_VEH_CAL_2 const tS16 c_assINCAR_TG_FL_LV4_Limo[13] = { 180, 190, 200, 210, 230, 250, 265, 270, 275, 285, 290, 295, 320}; +SECT_VEH_CAL_2 const tS16 c_assINCAR_TG_FR_LV4_Limo[13] = { 180, 190, 200, 210, 230, 250, 265, 270, 275, 285, 290, 295, 320}; +SECT_VEH_CAL_2 const tS16 c_assVTG_FL_LV4_Limo[13] = { 95, 95, 90, 85, 80, 80, 85, 85, 85, 85, 85, 87, 90}; +SECT_VEH_CAL_2 const tS16 c_assVTG_FR_LV4_Limo[13] = { 95, 95, 90, 85, 80, 80, 85, 85, 85, 85, 85, 87, 90}; +SECT_VEH_CAL_2 const tS16 c_assVF_MIN_LV4_Limo[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_2 const tS16 c_assVF_MAX_LV4_Limo[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_Y1_LV4_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_Y2_LV4_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_Y3_LV4_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_Y4_LV4_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_X1_LV4_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_X2_LV4_Limo[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_X3_LV4_Limo[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_X4_LV4_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assVF_AMB_Y1_LV4_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVF_AMB_Y2_LV4_Limo[7] = { -15, -8, 2, 10, 10, 10, 10}; +SECT_VEH_CAL_2 const tS16 c_assVF_AMB_X1_LV4_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVF_AMB_X2_LV4_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assVF_SUN_Y1_LV4_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVF_SUN_Y2_LV4_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVF_SUN_X1_LV4_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assVF_SUN_X2_LV4_Limo[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_2 const tS16 c_assTG_FLU_LV4_Limo[13] = { 50, 70, 120, 160, 200, 240, 270, 310, 350, 400, 450, 500, 550}; +SECT_VEH_CAL_2 const tS16 c_assTG_FRU_LV4_Limo[13] = { 50, 70, 120, 160, 200, 240, 270, 310, 350, 400, 450, 500, 550}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_MIN_LV4_Limo[7] = { 20, 20, 20, 30, 200, 200, 250}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_MAX_LV4_Limo[7] = { 450, 450, 550, 800, 800, 800, 800}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_Y1_LV4_Limo[7] = { -100, -100, -150, -180, -200, -300, -350}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_Y2_LV4_Limo[7] = { -30, -30, -70, -80, -65, -65, -65}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_Y3_LV4_Limo[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_Y4_LV4_Limo[7] = { 200, 200, 200, 100, 70, 60, 50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_X1_LV4_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_X2_LV4_Limo[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_X3_LV4_Limo[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_X4_LV4_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_AMB_Y1_LV4_Limo[7] = { 0, -10, -15, -20, -15, -25, -25}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_AMB_Y2_LV4_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_AMB_X1_LV4_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_AMB_X2_LV4_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_SUN_Y1_LV4_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_SUN_Y2_LV4_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_SUN_X1_LV4_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_SUN_X2_LV4_Limo[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_2 const tS16 c_assTG_FLL_LV4_Limo[13] = { 370, 380, 390, 400, 435, 470, 500, 560, 620, 660, 700, 750, 800}; +SECT_VEH_CAL_2 const tS16 c_assTG_FRL_LV4_Limo[13] = { 370, 380, 390, 400, 435, 470, 500, 560, 620, 660, 700, 750, 800}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_MIN_LV4_Limo[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_MAX_LV4_Limo[7] = { 600, 600, 800, 800, 800, 900, 900}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_Y1_LV4_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_Y2_LV4_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_Y3_LV4_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_Y4_LV4_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_X1_LV4_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_X2_LV4_Limo[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_X3_LV4_Limo[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_X4_LV4_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_AMB_Y1_LV4_Limo[7] = { 0, 0, -10, -25, -20, -10, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_AMB_Y2_LV4_Limo[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_AMB_X1_LV4_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_AMB_X2_LV4_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_SUN_Y1_LV4_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_SUN_Y2_LV4_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_SUN_X1_LV4_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_SUN_X2_LV4_Limo[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_2 const tS16 c_assINCAR_TG_RL_LV4_Limo[13] = { 190, 195, 200, 215, 230, 240, 250, 260, 270, 280, 290, 300, 310}; +SECT_VEH_CAL_2 const tS16 c_assINCAR_TG_RR_LV4_Limo[13] = { 190, 195, 200, 215, 230, 240, 250, 260, 270, 280, 290, 300, 310}; +SECT_VEH_CAL_2 const tS16 c_assVTG_RL_LV4_Limo[13] = { 110, 98, 85, 70, 65, 57, 57, 55, 55, 60, 68, 75, 80}; +SECT_VEH_CAL_2 const tS16 c_assVTG_RR_LV4_Limo[13] = { 110, 98, 85, 70, 65, 57, 57, 55, 55, 60, 68, 75, 80}; +SECT_VEH_CAL_2 const tS16 c_assVR_MIN_LV4_Limo[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_2 const tS16 c_assVR_MAX_LV4_Limo[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_Y1_LV4_Limo[7] = { 16, 14, 12, 8, 8, 8, 8}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_Y2_LV4_Limo[7] = { 10, 8, 6, 4, 4, 4, 4}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_Y3_LV4_Limo[7] = { 0, 2, 4, 5, 6, 8, 10}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_Y4_LV4_Limo[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_X1_LV4_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_X2_LV4_Limo[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_X3_LV4_Limo[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_X4_LV4_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assVR_AMB_Y1_LV4_Limo[7] = { 0, 0, 0, 0, 9, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVR_AMB_Y2_LV4_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVR_AMB_X1_LV4_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVR_AMB_X2_LV4_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assVR_SUN_Y1_LV4_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVR_SUN_Y2_LV4_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVR_SUN_X1_LV4_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assVR_SUN_X2_LV4_Limo[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_2 const tS16 c_assTG_RL_LV4_Limo[13] = { 20, 20, 50, 80, 140, 170, 200, 230, 260, 300, 340, 380, 420}; +SECT_VEH_CAL_2 const tS16 c_assTG_RR_LV4_Limo[13] = { 20, 20, 50, 80, 140, 170, 200, 230, 260, 300, 340, 380, 420}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_MIN_LV4_Limo[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_MAX_LV4_Limo[7] = { 400, 400, 450, 650, 800, 800, 800}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_Y1_LV4_Limo[7] = { -30, -60, -60, -60, -60, -60, -30}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_Y2_LV4_Limo[7] = { -15, -20, -20, -20, -20, -20, -15}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_Y3_LV4_Limo[7] = { 50, 50, 50, 60, 80, 80, 120}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_Y4_LV4_Limo[7] = { 300, 250, 250, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_X1_LV4_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_X2_LV4_Limo[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_X3_LV4_Limo[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_X4_LV4_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_AMB_Y1_LV4_Limo[7] = { -30, 0, 0, -20, -40, -50, -90}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_AMB_Y2_LV4_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_AMB_X1_LV4_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_AMB_X2_LV4_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_SUN_Y1_LV4_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_SUN_Y2_LV4_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_SUN_X1_LV4_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_SUN_X2_LV4_Limo[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_DUCT_TIME_FR_LV4_Limo[7] = { 3600, 3600, 3600, 3600, 3600, 3600, 3600}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_DUCT_TIME_FL_LV4_Limo[7] = { 3600, 3600, 3600, 3600, 3600, 3600, 3600}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_DUCT_RATE_LV4_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_DUCT_MAX_LV4_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_AF_TIME_FR_LV4_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_AF_TIME_FL_LV4_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_AF_RATE_LV4_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_AF_MAX_LV4_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +/* ------------------------------------------Lv4 : End*/ +SECT_VEH_CAL_2 const tS16 c_assINCAR_TG_FL_LV5_Limo[13] = { 180, 190, 200, 210, 230, 235, 240, 250, 270, 290, 310, 330, 350}; +SECT_VEH_CAL_2 const tS16 c_assINCAR_TG_FR_LV5_Limo[13] = { 180, 190, 200, 210, 230, 235, 240, 250, 270, 290, 310, 330, 350}; +SECT_VEH_CAL_2 const tS16 c_assVTG_FL_LV5_Limo[13] = { 80, 80, 80, 80, 80, 85, 90, 90, 95, 95, 95, 97, 100}; +SECT_VEH_CAL_2 const tS16 c_assVTG_FR_LV5_Limo[13] = { 80, 80, 80, 80, 80, 85, 90, 90, 95, 95, 95, 97, 100}; +SECT_VEH_CAL_2 const tS16 c_assVF_MIN_LV5_Limo[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_2 const tS16 c_assVF_MAX_LV5_Limo[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_Y1_LV5_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_Y2_LV5_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_Y3_LV5_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_Y4_LV5_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_X1_LV5_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_X2_LV5_Limo[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_X3_LV5_Limo[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tS16 c_assVF_INC_X4_LV5_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assVF_AMB_Y1_LV5_Limo[7] = { 15, 8, -2, -10, -10, -10, -10}; +SECT_VEH_CAL_2 const tS16 c_assVF_AMB_Y2_LV5_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVF_AMB_X1_LV5_Limo[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_2 const tS16 c_assVF_AMB_X2_LV5_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assVF_SUN_Y1_LV5_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVF_SUN_Y2_LV5_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVF_SUN_X1_LV5_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assVF_SUN_X2_LV5_Limo[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_2 const tS16 c_assTG_FLU_LV5_Limo[13] = { 50, 70, 120, 160, 210, 250, 280, 320, 360, 410, 460, 510, 560}; +SECT_VEH_CAL_2 const tS16 c_assTG_FRU_LV5_Limo[13] = { 50, 70, 120, 160, 210, 250, 280, 320, 360, 410, 460, 510, 560}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_MIN_LV5_Limo[7] = { 20, 20, 20, 30, 200, 200, 250}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_MAX_LV5_Limo[7] = { 450, 450, 550, 800, 800, 800, 800}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_Y1_LV5_Limo[7] = { -100, -100, -150, -180, -200, -300, -350}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_Y2_LV5_Limo[7] = { -30, -30, -70, -80, -65, -65, -65}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_Y3_LV5_Limo[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_Y4_LV5_Limo[7] = { 200, 200, 200, 100, 70, 60, 50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_X1_LV5_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_X2_LV5_Limo[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_X3_LV5_Limo[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_INC_X4_LV5_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_AMB_Y1_LV5_Limo[7] = { -10, -30, -50, -60, -50, -30, -10}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_AMB_Y2_LV5_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_AMB_X1_LV5_Limo[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_AMB_X2_LV5_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_SUN_Y1_LV5_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_SUN_Y2_LV5_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_SUN_X1_LV5_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FU_SUN_X2_LV5_Limo[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_2 const tS16 c_assTG_FLL_LV5_Limo[13] = { 380, 390, 400, 410, 445, 480, 510, 570, 630, 670, 710, 760, 810}; +SECT_VEH_CAL_2 const tS16 c_assTG_FRL_LV5_Limo[13] = { 380, 390, 400, 410, 445, 480, 510, 570, 630, 670, 710, 760, 810}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_MIN_LV5_Limo[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_MAX_LV5_Limo[7] = { 600, 600, 800, 800, 800, 800, 800}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_Y1_LV5_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_Y2_LV5_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_Y3_LV5_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_Y4_LV5_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_X1_LV5_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_X2_LV5_Limo[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_X3_LV5_Limo[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_INC_X4_LV5_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_AMB_Y1_LV5_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_AMB_Y2_LV5_Limo[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_AMB_X1_LV5_Limo[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_AMB_X2_LV5_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_SUN_Y1_LV5_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_SUN_Y2_LV5_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_SUN_X1_LV5_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assDTG_FL_SUN_X2_LV5_Limo[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_2 const tS16 c_assINCAR_TG_RL_LV5_Limo[13] = { 190, 195, 200, 215, 230, 240, 250, 260, 270, 280, 290, 300, 310}; +SECT_VEH_CAL_2 const tS16 c_assINCAR_TG_RR_LV5_Limo[13] = { 190, 195, 200, 215, 230, 240, 250, 260, 270, 280, 290, 300, 310}; +SECT_VEH_CAL_2 const tS16 c_assVTG_RL_LV5_Limo[13] = { 80, 75, 70, 65, 60, 55, 50, 52, 54, 56, 68, 75, 80}; +SECT_VEH_CAL_2 const tS16 c_assVTG_RR_LV5_Limo[13] = { 80, 75, 70, 65, 60, 55, 50, 52, 54, 56, 68, 75, 80}; +SECT_VEH_CAL_2 const tS16 c_assVR_MIN_LV5_Limo[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_2 const tS16 c_assVR_MAX_LV5_Limo[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_Y1_LV5_Limo[7] = { 16, 14, 12, 8, 8, 8, 8}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_Y2_LV5_Limo[7] = { 10, 8, 6, 4, 4, 4, 4}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_Y3_LV5_Limo[7] = { 0, 2, 4, 5, 6, 8, 10}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_Y4_LV5_Limo[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_X1_LV5_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_X2_LV5_Limo[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_X3_LV5_Limo[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tS16 c_assVR_INC_X4_LV5_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assVR_AMB_Y1_LV5_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVR_AMB_Y2_LV5_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVR_AMB_X1_LV5_Limo[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_2 const tS16 c_assVR_AMB_X2_LV5_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assVR_SUN_Y1_LV5_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVR_SUN_Y2_LV5_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assVR_SUN_X1_LV5_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assVR_SUN_X2_LV5_Limo[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_2 const tS16 c_assTG_RL_LV5_Limo[13] = { 20, 20, 50, 80, 150, 180, 210, 240, 270, 310, 350, 390, 430}; +SECT_VEH_CAL_2 const tS16 c_assTG_RR_LV5_Limo[13] = { 20, 20, 50, 80, 150, 180, 210, 240, 270, 310, 350, 390, 430}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_MIN_LV5_Limo[7] = { 20, 20, 20, 51, 51, 51, 51}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_MAX_LV5_Limo[7] = { 400, 400, 450, 650, 800, 800, 800}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_Y1_LV5_Limo[7] = { -30, -60, -60, -60, -60, -60, -30}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_Y2_LV5_Limo[7] = { -15, -20, -20, -20, -20, -20, -15}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_Y3_LV5_Limo[7] = { 50, 50, 50, 60, 80, 80, 120}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_Y4_LV5_Limo[7] = { 300, 250, 250, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_X1_LV5_Limo[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_X2_LV5_Limo[7] = { -40, -40, -40, -40, -40, -40, -40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_X3_LV5_Limo[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_INC_X4_LV5_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_AMB_Y1_LV5_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_AMB_Y2_LV5_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_AMB_X1_LV5_Limo[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_AMB_X2_LV5_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_SUN_Y1_LV5_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_SUN_Y2_LV5_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_SUN_X1_LV5_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assDTG_R_SUN_X2_LV5_Limo[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_DUCT_TIME_FR_LV5_Limo[7] = { 3600, 3600, 3600, 3600, 3600, 3600, 3600}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_DUCT_TIME_FL_LV5_Limo[7] = { 3600, 3600, 3600, 3600, 3600, 3600, 3600}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_DUCT_RATE_LV5_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_DUCT_MAX_LV5_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_AF_TIME_FR_LV5_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_AF_TIME_FL_LV5_Limo[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_AF_RATE_LV5_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assCORRECT_AF_MAX_LV5_Limo[7] = { 0, 0, 0, 0, 0, 0, 0}; +/* ------------------------------------------Lv5 : End*/ +SECT_VEH_CAL_2 const tS16 c_assDUCT_TGT_DEF_VALVE_L_Limo[11] = { 350, 300, 300, 250, 200, 150, 120, 100, 70, 50, 50}; +SECT_VEH_CAL_2 const tS16 c_assDUCT_TGT_DEF_VALVE_R_Limo[11] = { 350, 300, 300, 250, 200, 150, 120, 100, 70, 50, 50}; +/* ------------------------------------------DuctTgt Increase : End*/ +SECT_VEH_CAL_2 const tS16 c_assAMB_LV_UP_Limo[5] = { 650, 200, 50, -150, -300}; +SECT_VEH_CAL_2 const tS16 c_assAMB_LV_DN_Limo[5] = { 700, 250, 100, -100, -250}; +SECT_VEH_CAL_2 const tS16 c_assAMB_LV_TG_Limo[6] = { 600, 350, 150, 0, -150, -350}; +/* ------------------------------------------Ambient LEVEL : End*/ +SECT_VEH_CAL_2 const tU08 c_aucMODE_BY_SET_F_LV0_Limo[13] = { 30, 30, 30, 30, 20, 20, 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_2 const tU08 c_aucMODE_BY_SET_F_LV1_Limo[13] = { 30, 30, 30, 30, 20, 20, 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_2 const tU08 c_aucMODE_BY_SET_F_LV2_Limo[13] = { 30, 30, 30, 20, 20, 20, 20, 20, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tU08 c_aucMODE_BY_SET_F_LV3_Limo[13] = { 20, 20, 20, 20, 40, 40, 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tU08 c_aucMODE_BY_SET_F_LV4_Limo[13] = { 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tU08 c_aucMODE_BY_SET_F_LV5_Limo[13] = { 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tU16 c_ausMODE_BY_DUCT_TG_R_LV0_Limo[7] = { 250, 300, 450, 550, 120, 150, 180}; +SECT_VEH_CAL_2 const tU16 c_ausMODE_BY_DUCT_TG_R_LV1_Limo[7] = { 250, 300, 450, 550, 120, 150, 180}; +SECT_VEH_CAL_2 const tU16 c_ausMODE_BY_DUCT_TG_R_LV2_Limo[7] = { 350, 400, 500, 550, 120, 150, 180}; +SECT_VEH_CAL_2 const tU16 c_ausMODE_BY_DUCT_TG_R_LV3_Limo[7] = { 450, 500, 550, 600, 120, 180, 180}; +SECT_VEH_CAL_2 const tU16 c_ausMODE_BY_DUCT_TG_R_LV4_Limo[7] = { 400, 450, 500, 550, 120, 150, 180}; +SECT_VEH_CAL_2 const tU16 c_ausMODE_BY_DUCT_TG_R_LV5_Limo[7] = { 400, 450, 500, 550, 120, 150, 180}; +/* ------------------------------------------Mode depend on SET for each level : End*/ +SECT_VEH_CAL_2 const tS16 c_ssPREC_REC_ON_AMB_Limo = 300; +SECT_VEH_CAL_2 const tS16 c_ssPREC_REC_OFF_AMB_Limo = 280; +SECT_VEH_CAL_2 const tU08 c_aucPREC_VEH_SPD_OSA_Limo[13] = { 100, 70, 65, 60, 59, 58, 55, 53, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_2 const tS16 c_assPRE_AMB_RANGE_WINTER_Limo[7] = { -450, -300, -200, -150, -80, 0, 50}; +SECT_VEH_CAL_2 const tU08 c_aucPREC_OSA_WINTER_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tU08 c_aucPREC_REC_WINTER_Limo[7] = { 15, 13, 10, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tU16 c_ausPREC_HUMIDITY_NOK_Limo[7] = { 900, 900, 900, 900, 900, 900, 900}; +SECT_VEH_CAL_2 const tU16 c_ausPREC_HUMIDITY_OK_Limo[7] = { 700, 700, 700, 700, 700, 700, 700}; +SECT_VEH_CAL_2 const tU16 c_ausPREC_ENTRY_RPM_Limo[3] = { 450, 650, 800}; +SECT_VEH_CAL_2 const tU16 c_ausPREC_EXIT_RPM_Limo[3] = { 350, 550, 750}; +SECT_VEH_CAL_2 const tU16 c_ausPREC_COMP_SPD_1_Limo[3] = { 450, 500, 550}; +SECT_VEH_CAL_2 const tU08 c_aucPREC_OSA_SUMMER_1_Limo[3] = { 80, 60, 45}; +SECT_VEH_CAL_2 const tU08 c_aucPREC_REC_SUMMER_1_Limo[3] = { 20, 40, 60}; +SECT_VEH_CAL_2 const tS16 c_assPREC_EVA_DIFF_FB_TG_F_Limo[7] = { 0, 5, 10, 15, 20, 25, 30}; +SECT_VEH_CAL_2 const tU08 c_aucPREC_OSA_SUMMER_2_Limo[7] = { 50, 45, 40, 35, 30, 25, 20}; +SECT_VEH_CAL_2 const tU08 c_aucPREC_REC_SUMMER_2_Limo[7] = { 50, 55, 60, 65, 70, 75, 80}; +SECT_VEH_CAL_2 const tU08 c_aucPREC_EVA_DIFF_Limo[4] = { 80, 80, 50, 50}; +SECT_VEH_CAL_2 const tU08 c_ucPREC_OSA_SUMMER_3_Limo = 0; +SECT_VEH_CAL_2 const tU08 c_ucPREC_REC_SUMMER_3_Limo = 100; +/* ------------------------------------------AutoRec : End*/ +SECT_VEH_CAL_2 const tU16 c_ausFLOW_FR_VE2VALVE_Limo[9] = { 50, 50, 50, 50, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tU16 c_ausFLOW_FR_BIVALVE_Limo[9] = { 35, 35, 35, 35, 15, 0, 15, 0, 0}; +SECT_VEH_CAL_2 const tU16 c_ausFLOW_FR_BI2VALVE_Limo[9] = { 40, 35, 35, 40, 15, 0, 15, 0, 0}; +SECT_VEH_CAL_2 const tU16 c_ausFLOW_FR_AF2VALVE_Limo[9] = { 25, 20, 20, 25, 20, 0, 20, 0, 0}; +SECT_VEH_CAL_2 const tU16 c_ausFLOW_FR_AF2VALVE_SUMMER_Limo[9] = { 20, 15, 15, 20, 20, 0, 20, 0, 0}; +SECT_VEH_CAL_2 const tU16 c_ausFLOW_FR_FO2VALVE_Limo[9] = { 0, 0, 0, 0, 40, 0, 40, 0, 0}; +SECT_VEH_CAL_2 const tU16 c_ausFLOW_FR_FD2VALVE_Limo[9] = { 0, 0, 0, 0, 40, 0, 40, 0, 100}; +SECT_VEH_CAL_2 const tU16 c_ausFLOW_FR_DE2VALVE_Limo[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 100}; +SECT_VEH_CAL_2 const tU16 c_ausFLOW_FR_TR2VALVE_Limo[9] = { 33, 25, 25, 33, 15, 0, 15, 0, 50}; +SECT_VEH_CAL_2 const tU16 c_ausFLOW_FR_HI2VALVE_Limo[9] = { 33, 25, 25, 33, 15, 0, 15, 0, 100}; +SECT_VEH_CAL_2 const tU16 c_ausFLOW_FR_BIVALVE_MANUAL_Limo[9] = { 35, 35, 35, 35, 25, 0, 25, 0, 0}; +SECT_VEH_CAL_2 const tU16 c_ausFLOW_RE_VENT_Limo[6] = { 30, 100, 100, 30, 0, 0}; +SECT_VEH_CAL_2 const tU16 c_ausFLOW_RE_BI2VALVE_Limo[6] = { 30, 60, 60, 30, 100, 100}; +SECT_VEH_CAL_2 const tU16 c_ausFLOW_RE_FO2VALVE_Limo[6] = { 0, 20, 20, 0, 100, 100}; +SECT_VEH_CAL_2 const tU16 c_ausFLOW_RE_VENT_2_Limo[6] = { 25, 100, 100, 25, 30, 30}; +SECT_VEH_CAL_2 const tU16 c_ausFLOW_RE_BI2VALVE_2_Limo[6] = { 50, 30, 30, 50, 100, 100}; +SECT_VEH_CAL_2 const tU16 c_ausFLOW_RE_VENT_3_Limo[6] = { 30, 100, 100, 30, 0, 0}; +SECT_VEH_CAL_2 const tU16 c_ausFLOW_RE_BI2VALVE_3_Limo[6] = { 10, 20, 20, 10, 100, 100}; +SECT_VEH_CAL_2 const tU16 c_ausFLOW_RE_VENT_MANUAL_Limo[6] = { 30, 100, 100, 30, 0, 0}; +SECT_VEH_CAL_2 const tU16 c_ausFLOW_RE_BI2VALVE_MANUAL_Limo[6] = { 70, 40, 40, 70, 100, 100}; +/* ------------------------------------------Flow Control Valve: End*/ +SECT_VEH_CAL_2 const tS16 c_assFLOW_BI_AMB_TGT_Limo[6] = { 450, 330, 150, 0, -150, -350}; +SECT_VEH_CAL_2 const tU08 c_aucFLOW_BI_VENT_PLUS_Limo[12] = { 0, 6, 7, 0, 0, 0, 0, 6, 7, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assFLOW_BI_TEMP_TGT_Limo[12] = { 300, 350, 400, 450, 500, 550, 300, 350, 400, 450, 500, 550}; +SECT_VEH_CAL_2 const tU08 c_aucFLOW_BI_FOOT_PLUS_Limo[12] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tU08 c_aucFLOW_BI_VENT_VALVE_MAX_Limo[12] = { 100, 50, 50, 100, 100, 100, 100, 40, 20, 100, 100, 100}; +SECT_VEH_CAL_2 const tU08 c_aucFLOW_BI_FOOT_VALVE_MAX_Limo[12] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tU08 c_aucFLOW_BI_VENT_VALVE_MIN_Limo[12] = { 35, 35, 20, 20, 20, 20, 35, 35, 20, 20, 20, 20}; +SECT_VEH_CAL_2 const tU08 c_aucFLOW_BI_FOOT_VALVE_MIN_Limo[12] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +/* ------------------------------------------Bi 2 level conditions: End*/ +SECT_VEH_CAL_2 const tS16 c_assFLOW_B2I_AMB_TGT_Limo[6] = { 450, 350, 200, 0, -150, -350}; +SECT_VEH_CAL_2 const tU08 c_aucFLOW_BI2_VENT_PLUS_Limo[12] = { 0, 8, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assFLOW_BI2_TEMP_TGT_Limo[12] = { 300, 350, 400, 450, 500, 550, 300, 350, 400, 450, 500, 550}; +SECT_VEH_CAL_2 const tU08 c_aucFLOW_BI2_FOOT_PLUS_Limo[12] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tU08 c_aucFLOW_BI2_VENT_VALVE_MAX_Limo[12] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tU08 c_aucFLOW_BI2_FOOT_VALVE_MAX_Limo[12] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tU08 c_aucFLOW_BI2_VENT_VALVE_MIN_Limo[12] = { 40, 40, 20, 20, 20, 20, 35, 35, 20, 20, 20, 20}; +SECT_VEH_CAL_2 const tU08 c_aucFLOW_BI2_FOOT_VALVE_MIN_Limo[12] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +/* ------------------------------------------AF level conditions: End*/ +SECT_VEH_CAL_2 const tS16 c_assFLOW_AF_AMB_TGT_Limo[6] = { 450, 350, 200, 0, -150, -350}; +SECT_VEH_CAL_2 const tU08 c_aucFLOW_AF_VENT_PLUS_Limo[12] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tU08 c_aucFLOW_AF_BLR_AF_TGT_Limo[6] = { 60, 60, 60, 50, 65, 60}; +SECT_VEH_CAL_2 const tU08 c_aucFLOW_AF_FOOT_PLUS_Limo[12] = { 0, 0, 0, 15, 0, 0, 0, 0, 0, 15, 0, 0}; +SECT_VEH_CAL_2 const tU08 c_aucFLOW_AF_VENT_VALVE_MAX_Limo[12] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tU08 c_aucFLOW_AF_FOOT_VALVE_MAX_Limo[12] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +/* ------------------------------------------AF level conditions: End*/ +SECT_VEH_CAL_2 const tS16 c_assFLOW_AFSM_AMB_TGT_Limo[6] = { 450, 350, 200, 0, -150, -350}; +SECT_VEH_CAL_2 const tU08 c_aucFLOW_AFSM_VENT_PLUS_Limo[12] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assFLOW_AFSM_TEMP_TGT_Limo[12] = { 300, 350, 400, 450, 500, 550, 300, 350, 400, 450, 500, 550}; +SECT_VEH_CAL_2 const tU08 c_aucFLOW_AFSM_FOOT_PLUS_Limo[12] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tU08 c_aucFLOW_AFSM_VENT_VALVE_MAX_Limo[12] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tU08 c_aucFLOW_AFSM_FOOT_VALVE_MAX_Limo[12] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +/* ------------------------------------------AF_summer level conditions: End*/ +SECT_VEH_CAL_2 const tU08 c_aucMODE_INDEX_Limo[11] = { 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 110}; +SECT_VEH_CAL_2 const tS16 c_assFOOT_STEP_DUCT_TGT_Limo[7] = { -400, -250, -100, 0, 100, 250, 400}; +SECT_VEH_CAL_2 const tS16 c_assBLR_FOOT_IND_Limo[7] = { 25, 10, 5, 0, 5, 10, 25}; +SECT_VEH_CAL_2 const tS08 c_ascFOOT_STEP_VALVE_P1_Limo[11] = { 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_2 const tS08 c_ascFOOT_STEP_VALVE_P2_Limo[11] = { 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25}; +SECT_VEH_CAL_2 const tS08 c_ascFOOT_STEP_VALVE_P3_Limo[11] = { 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tS08 c_ascFOOT_STEP_VALVE_M1_Limo[11] = { 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_2 const tS08 c_ascFOOT_STEP_VALVE_M2_Limo[11] = { 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25}; +SECT_VEH_CAL_2 const tS08 c_ascFOOT_STEP_VALVE_M3_Limo[11] = { 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_2 const tS16 c_assFOOT_STEP_BLR_P1_Limo[11] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_2 const tS16 c_assFOOT_STEP_BLR_P2_Limo[11] = { 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_2 const tS16 c_assFOOT_STEP_BLR_P3_Limo[11] = { 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 10}; +SECT_VEH_CAL_2 const tS16 c_assFOOT_STEP_BLR_M1_Limo[11] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_2 const tS16 c_assFOOT_STEP_BLR_M2_Limo[11] = { 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_2 const tS16 c_assFOOT_STEP_BLR_M3_Limo[11] = { 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20}; +/* ------------------------------------------Individual foot temperature: End*/ +SECT_VEH_CAL_2 const tU08 c_aucREAR_FOOT_VALVE_AMB_LV2_Limo[13] = { 0, 0, 0, 0, 0, 0, 5, 10, 15, 20, 25, 30, 35}; +SECT_VEH_CAL_2 const tU08 c_aucREAR_FOOT_VALVE_AMB_LV3_Limo[13] = { 0, 0, 0, 0, 0, 0, 5, 10, 15, 20, 25, 30, 35}; +SECT_VEH_CAL_2 const tU08 c_aucREAR_FOOT_VALVE_AMB_LV4_Limo[13] = { 0, 0, 0, 0, 0, 0, 5, 10, 15, 20, 25, 30, 35}; +/* ------------------------------------------Blowing foots from Rear HVAC: End*/ +SECT_VEH_CAL_2 const tU16 c_ausFLOW_FR_VE2BLR_AF_Limo[8] = { 0, 30, 51, 64, 88, 114, 135, 160}; +SECT_VEH_CAL_2 const tU16 c_ausFLOW_FR_BIVALVE_AF_Limo[8] = { 0, 30, 51, 64, 88, 114, 135, 160}; +SECT_VEH_CAL_2 const tU16 c_ausFLOW_FR_BI2BLR_AF_Limo[8] = { 0, 30, 51, 64, 88, 114, 135, 160}; +SECT_VEH_CAL_2 const tU16 c_ausFLOW_FR_FO2BLR_AF_Limo[8] = { 0, 30, 51, 64, 88, 114, 135, 160}; +SECT_VEH_CAL_2 const tU16 c_ausFLOW_FR_AF2VALVE_AF_Limo[8] = { 0, 30, 51, 64, 88, 114, 135, 160}; +SECT_VEH_CAL_2 const tU16 c_ausFLOW_FR_AF2VALVE_SUMMER_AF_Limo[8] = { 0, 30, 51, 64, 88, 114, 135, 160}; +SECT_VEH_CAL_2 const tU16 c_ausFLOW_FR_FD2BLR_AF_Limo[8] = { 0, 30, 51, 64, 88, 114, 135, 160}; +SECT_VEH_CAL_2 const tU16 c_ausFLOW_FR_DE2BLR_AF_Limo[8] = { 0, 30, 51, 64, 88, 114, 135, 160}; +SECT_VEH_CAL_2 const tU16 c_ausFLOW_FR_TR2BLR_AF_Limo[8] = { 0, 30, 51, 64, 88, 114, 135, 160}; +SECT_VEH_CAL_2 const tU16 c_ausFLOW_FR_HI2BLR_AF_Limo[8] = { 0, 30, 51, 64, 88, 114, 135, 160}; +SECT_VEH_CAL_2 const tU16 c_ausFLOW_RE_VE2BLR_AF_Limo[8] = { 0, 30, 51, 64, 88, 114, 135, 160}; +SECT_VEH_CAL_2 const tU16 c_ausFLOW_RE_BI2BLR_AF_Limo[8] = { 0, 30, 51, 64, 88, 114, 135, 160}; +SECT_VEH_CAL_2 const tU16 c_ausFLOW_RE_FO2BLR_AF_Limo[8] = { 0, 30, 51, 64, 88, 114, 135, 160}; +/* ------------------------------------------Flow Control AF: End*/ +SECT_VEH_CAL_2 const tS08 c_ascAUTO_STEP_AF_F_Limo[5] = { -15, -7, 0, 15, 30}; +SECT_VEH_CAL_2 const tS08 c_ascAUTO_STEP_AF_R_Limo[5] = { -20, -10, 0, 20, 40}; +SECT_VEH_CAL_2 const tS16 c_assAUTO_STEP_DUCT_TG_U_F_LV0_1_Limo[10] = { -50, 0, 0, 0, 80, -50, 0, 0, 0, 80}; +SECT_VEH_CAL_2 const tS16 c_assAUTO_STEP_DUCT_TG_U_F_LV2_3_Limo[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assAUTO_STEP_DUCT_TG_U_F_LV4_5_Limo[10] = { -50, 0, 0, -50, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assAUTO_STEP_DUCT_TG_L_F_LV0_1_Limo[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assAUTO_STEP_DUCT_TG_L_F_LV2_3_Limo[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assAUTO_STEP_DUCT_TG_L_F_LV4_5_Limo[10] = { 50, 50, 0, -128, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assAUTO_STEP_DUCT_TG_R_LV0_1_Limo[10] = { -50, 0, 0, 0, 10, -50, 0, 0, 0, 10}; +SECT_VEH_CAL_2 const tS16 c_assAUTO_STEP_DUCT_TG_R_LV2_3_Limo[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tS16 c_assAUTO_STEP_DUCT_TG_R_LV4_5_Limo[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +/* ------------------------------------------5 AUTO mode: End*/ +SECT_VEH_CAL_2 const tU16 c_ausVALVE_SPACE_Limo[6] = { 300, 300, 300, 269, 275, 215}; +SECT_VEH_CAL_2 const tU08 c_aucVALVE_SECTION_S1_F_SIDE_VENT_Limo[9] = { 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_2 const tU08 c_aucVALVE_SECTION_S1_F_CENT_VENT_Limo[9] = { 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_2 const tU08 c_aucVALVE_SECTION_S1_F_DRIVER_FOOT_Limo[9] = { 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_2 const tU08 c_aucVALVE_SECTION_S1_F_RIGHT_PASS_Limo[9] = { 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_2 const tU08 c_aucBLR_SPD_V1_1_F_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tU08 c_aucBLR_SPD_K2_1_F_SIDE_VENT_Limo[10] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tU08 c_aucBLR_SPD_K2_2_F_CENT_VENT_Limo[10] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tU08 c_aucBLR_SPD_K2_3_F_DRIVER_FOOT_Limo[10] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tU08 c_aucBLR_SPD_K2_4_F_RIGHT_PASS_Limo[13] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tU16 c_ausVALVE_VEH_SPD_Limo[13] = { 0, 40, 60, 80, 90, 110, 130, 150, 170, 190, 220, 250, 300}; +SECT_VEH_CAL_2 const tU08 c_aucVALVE_VEH_SPD_SIDE_VENT_Limo[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_2 const tU08 c_aucVALVE_VEH_SPD_SIDE_BI_Limo[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_2 const tU08 c_aucVALVE_VEH_SPD_SIDE_AFOOT_Limo[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_2 const tU08 c_aucVALVE_VEH_SPD_CNET_VENT_Limo[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_2 const tU08 c_aucVALVE_VEH_SPD_CENT_BI_Limo[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_2 const tU08 c_aucVALVE_VEH_SPD_CENT_AFOOT_Limo[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_2 const tU08 c_aucVALVE_VEH_SPD_FOOT_BI_Limo[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_2 const tU08 c_aucVALVE_VEH_SPD_FOOT_AFOOT_Limo[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_2 const tU08 c_aucVALVE_VEH_SPD_2FOOT_Limo[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_2 const tU08 c_aucBLR_SPD_VEH_SPD_V1_3_Limo[12] = { 100, 70, 30, 100, 70, 30, 100, 70, 30, 100, 70, 30}; +SECT_VEH_CAL_2 const tU08 c_aucFRONT_SIDE_DRS_PERCENT_Limo[12] = { 100, 70, 30, 100, 70, 30, 100, 70, 30, 100, 70, 30}; +SECT_VEH_CAL_2 const tU08 c_aucFRONT_CENT_DRS_PERCENT_Limo[12] = { 100, 70, 30, 100, 70, 30, 100, 70, 30, 100, 70, 30}; +/* ------------------------------------------Different blower speed FRONT MODE: End*/ +SECT_VEH_CAL_2 const tU08 c_aucVALVE_S1_R_BIPILLAR_Limo[8] = { 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_2 const tU08 c_aucVALVE_S1_R_CENT_VENT_Limo[9] = { 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_2 const tU08 c_aucVALVE_S1_R_FOOT_Limo[5] = { 10, 10, 10, 10, 10}; +SECT_VEH_CAL_2 const tU08 c_aucVALVE_PERC_R_BIPILLAR_Limo[10] = { 10, 20, 30, 40, 50, 60, 70, 80, 90, 100}; +SECT_VEH_CAL_2 const tU08 c_aucVALVE_PERC_R_CENT_VENT_Limo[10] = { 10, 20, 30, 40, 50, 60, 70, 80, 90, 100}; +SECT_VEH_CAL_2 const tU08 c_aucVALVE_PERC_R_FOOT_Limo[10] = { 10, 20, 30, 40, 50, 60, 70, 80, 90, 100}; +SECT_VEH_CAL_2 const tU08 c_aucBLR_SPD_V1_1_R_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tU08 c_aucREAR_CEN_MIN_VALUE_BY_DRS_ZERO_Limo[7] = { 30, 29, 28, 27, 24, 22, 20}; +SECT_VEH_CAL_2 const tU08 c_aucBLR_SPD_K2_1_R_BIPILLAR_MIN_Limo[8] = { 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tU08 c_aucBLR_SPD_K2_2_R_CENT_VENT_MIN_Limo[9] = { 85, 85, 85, 85, 85, 85, 85, 85, 85}; +SECT_VEH_CAL_2 const tU08 c_aucBLR_SPD_K2_3_R_FOOT_MIN_Limo[5] = { 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tU08 c_aucBLR_SPD_K2_1_R_BIPILLAR_MAX_Limo[8] = { 120, 120, 120, 120, 120, 120, 120, 120}; +SECT_VEH_CAL_2 const tU08 c_aucBLR_SPD_K2_2_R_CENT_VENTR_MAX_Limo[9] = { 122, 122, 122, 122, 122, 122, 122, 122, 122}; +SECT_VEH_CAL_2 const tU08 c_aucBLR_SPD_K2_3_R_FOOTR_MAX_Limo[5] = { 130, 130, 130, 130, 130}; +SECT_VEH_CAL_2 const tU08 c_aucREAR_SIDE_DRS_PERCENT_VALVE_Limo[9] = { 100, 70, 30, 100, 70, 30, 100, 70, 30}; +SECT_VEH_CAL_2 const tU08 c_aucREAR_CENT_DRS_PERCENT_VALVE_Limo[9] = { 100, 70, 30, 100, 70, 30, 100, 70, 30}; +SECT_VEH_CAL_2 const tU08 c_aucREAR_SIDE_DRS_PERCENT_AF_Limo[9] = { 100, 70, 30, 100, 70, 30, 100, 70, 30}; +SECT_VEH_CAL_2 const tU08 c_aucREAR_CENT_DRS_PERCENT_AF_Limo[9] = { 100, 70, 30, 100, 70, 30, 100, 70, 30}; +/* ------------------------------------------Different blower speed REAR MODE: End*/ +SECT_VEH_CAL_2 const tU16 c_ausMIN_PWM_Limo[2] = { 151, 151}; +/* ------------------------------------------MinPWM: End*/ +SECT_VEH_CAL_2 const tS16 c_assSTART_ENTER_COOLANT_Limo[6] = { 300, 400, 400, 600, 600, 600}; +SECT_VEH_CAL_2 const tS16 c_assSTART_COOLANT_STEP0_TO_1_Limo[8] = { 0, 400, 400, 400, 300, 400, 400, 400}; +SECT_VEH_CAL_2 const tS16 c_assSTART_COOLANT_TO_STEP2_Limo[3] = { 950, 800, 850}; +SECT_VEH_CAL_2 const tS16 c_assSTART_COOLANT_STEP1_BLR_F_Limo[6] = { 0, 0, 0, 700, 650, 650}; +SECT_VEH_CAL_2 const tS16 c_assSTART_COOLANT_STEP1_BLR_R_Limo[6] = { 0, 0, 700, 600, 600, 600}; +SECT_VEH_CAL_2 const tS16 c_assSTART_ENTER_INCAR_Limo[12] = { 400, 400, 500, 200, 0, 0, 400, 360, 200, 50, 50, 50}; +SECT_VEH_CAL_2 const tU16 c_ausSTART_ENTER_SETTEMP_Limo[12] = { 260, 250, 0, 0, 0, 0, 260, 250, 200, 200, 0, 0}; +SECT_VEH_CAL_2 const tU08 c_aucSTART_INCAR_FLT_UP_Limo[12] = { 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_2 const tU08 c_aucSTART_INCAR_FLT_DN_Limo[12] = { 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_2 const tU08 c_aucSTART_VALVE_IDX_STEP1_Limo[12] = { 10, 10, 10, 70, 70, 70, 120, 120, 140, 140, 140, 140}; +SECT_VEH_CAL_2 const tU08 c_aucSTART_AUTODEMIST2_STEP2_Limo[6] = { 0, 0, 1, 1, 1, 1}; +SECT_VEH_CAL_2 const tU08 c_aucSTART_ELEC_WINDOW_Limo[12] = { 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 1, 1}; +SECT_VEH_CAL_2 const tU16 c_ausSTART_BLR_AF_STEP12_F_Limo[12] = { 160, 100, 120, 60, 60, 60, 140, 140, 100, 140, 140, 140}; +SECT_VEH_CAL_2 const tU16 c_ausSTART_BLR_AF_STEP12_R_Limo[12] = { 160, 140, 90, 90, 90, 90, 140, 140, 160, 160, 160, 160}; +SECT_VEH_CAL_2 const tU16 c_ausSTART_BLR_SPD_STEP2_F_Limo[12] = { 1, 1, 1, 1, 1, 1, 5, 5, 2, 3, 4, 4}; +SECT_VEH_CAL_2 const tU16 c_ausSTART_BLR_SPD_STEP2_R_Limo[12] = { 1, 1, 1, 1, 1, 1, 5, 5, 2, 3, 4, 4}; +SECT_VEH_CAL_2 const tU08 c_aucSTART_DUCT_TGT_STEP2_FX_U_Limo[12] = { 5, 5, 5, 50, 60, 60, 3, 3, 3, 3, 3, 3}; +SECT_VEH_CAL_2 const tU08 c_aucSTART_DUCT_TGT_STEP2_FX_L_Limo[12] = { 15, 15, 15, 80, 80, 80, 6, 6, 6, 20, 30, 30}; +SECT_VEH_CAL_2 const tU08 c_aucSTART_DUCT_TGT_STEP2_RX_Limo[12] = { 2, 2, 60, 80, 80, 80, 3, 3, 3, 6, 6, 6}; +SECT_VEH_CAL_2 const tU08 c_aucSTART_VALVE_CHANGE_SPD_F_Limo[12] = { 1, 1, 1, 1, 1, 1, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_2 const tU08 c_aucSTART_VALVE_CHANGE_SPD_R_Limo[12] = { 1, 1, 1, 1, 1, 1, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_2 const tU16 c_ausSTART_TIME_STEP1_TO_2_Limo[12] = { 600, 600, 180, 1200, 1200, 1800, 480, 480, 3600, 3600, 3600, 3600}; +SECT_VEH_CAL_2 const tU16 c_ausSTART_TIME_STEP2_TO_3_Limo[12] = { 180, 180, 180, 600, 600, 1200, 300, 180, 1800, 600, 1800, 1800}; +SECT_VEH_CAL_2 const tS16 c_assSTART_INCAR_STEP1_TO_2_Limo[12] = { 250, 250, 300, 220, 230, 250, 250, 250, 200, 230, 270, 270}; +SECT_VEH_CAL_2 const tS16 c_assSTART_INCAR_STEP2_TO_3_Limo[12] = { 300, 300, 250, 250, 250, 280, 220, 220, 220, 220, 250, 270}; +SECT_VEH_CAL_2 const tU08 c_aucSTART_3WAY_OPEN_Limo[12] = { 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}; +SECT_VEH_CAL_2 const tU08 c_aucSTART_2WAY_OPEN_Limo[12] = { 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1}; +SECT_VEH_CAL_2 const tU08 c_aucSTART_TXV_F_Limo[12] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}; +SECT_VEH_CAL_2 const tU08 c_aucSTART_TXV_R_Limo[12] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}; +/* ------------------------------------------Start control: End*/ +SECT_VEH_CAL_2 const tS16 c_assFAILURE_AMB_TEMP_Limo[13] = { -200, -150, -80, -50, 0, 100, 150, 200, 250, 300, 350, 400, 450}; +SECT_VEH_CAL_2 const tS16 c_assAC_PRESSURE_LOW_HYS_UP_Limo[13] = { 6, 8, 9, 10, 11, 15, 24, 30, 37, 55, 57, 60, 65}; +SECT_VEH_CAL_2 const tS16 c_assAC_PRESSURE_LOW_HYS_DN_Limo[13] = { 5, 7, 8, 9, 10, 12, 15, 25, 25, 30, 30, 30, 40}; +SECT_VEH_CAL_2 const tS16 c_assAC_LOW_AMB_F_Limo[2] = { 50, 70}; +SECT_VEH_CAL_2 const tS16 c_assAC_CUT_OFF_AMB_F_Limo[2] = { -50, -30}; +SECT_VEH_CAL_2 const tS16 c_assAC_WINTER_TXV_DEWPOINT_Limo[2] = { 40, 30}; +SECT_VEH_CAL_2 const tS16 c_assAC_CUT_OFF_AMB_R_Limo[2] = { -220, -210}; +SECT_VEH_CAL_2 const tS16 c_assEVA_TG_AMB_F_Limo[13] = { 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 25, 25, 25}; +SECT_VEH_CAL_2 const tS16 c_assEVA_TG_AMB_R_Limo[13] = { 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 25, 25, 25}; +SECT_VEH_CAL_2 const tU08 c_ucAC_EXTRA_RPM_Limo = 15; +SECT_VEH_CAL_2 const tS16 c_assAC_EVA_LV_SHUT_OFF_Limo[2] = { 150, 10}; +SECT_VEH_CAL_2 const tS16 c_assAC_PRESSURE_HYS_HI_ENG_ON_Limo[3] = { 331, 265, 186}; +SECT_VEH_CAL_2 const tU16 c_usCMP_MAX_ENG_OFF_Limo = 3000; +SECT_VEH_CAL_2 const tU08 c_ucFAN_MAX_ENG_OFF_Limo = 15; +SECT_VEH_CAL_2 const tS16 c_ssAC_WINTER_TXV_HYST_Limo = 15; +SECT_VEH_CAL_2 const tU08 c_aucAC_PRESSURE_HYS_HI_ENG_OFF_Limo[2] = { 186, 155}; +SECT_VEH_CAL_2 const tU16 c_ausCMP_RPM_RESONANCE_Limo[6] = { 1500, 1550, 2500, 2560, 7500, 7590}; +/* ------------------------------------------A/C Control Pressure : End*/ +SECT_VEH_CAL_2 const tS16 c_assPRESSURE_TO_FAN_X_Limo[7] = { 50, 70, 90, 100, 174, 184, 240}; +SECT_VEH_CAL_2 const tU08 c_aucPRESSURE_TO_FAN_Y_Limo[7] = { 8, 15, 30, 50, 70, 80, 100}; +/* ------------------------------------------CoolingFan: End*/ +SECT_VEH_CAL_2 const tS16 c_ssREST_BATT_Limo = 109; +SECT_VEH_CAL_2 const tS16 c_ssRESTW_AMB_Limo = 100; +SECT_VEH_CAL_2 const tS16 c_assRESTW_WATER_Limo[2] = { 550, 350}; +SECT_VEH_CAL_2 const tU16 c_usRESTW_READYEXPIRETIME_Limo = 120; +SECT_VEH_CAL_2 const tU08 c_aucRESTW_MODE_Limo[2] = { 70, 130}; +SECT_VEH_CAL_2 const tU16 c_usRESTW_TIMEOUTTIME_Limo = 900; +SECT_VEH_CAL_2 const tU08 c_ucRESTW_BLRSTEP_Limo = 2; +SECT_VEH_CAL_2 const tS16 c_ssRESTS_AMB_Limo = 100; +SECT_VEH_CAL_2 const tU08 c_uctRESTS_READYEXPIRETIME_Limo = 120; +SECT_VEH_CAL_2 const tU08 c_aucRESTS_MODE_Limo[2] = { 70, 130}; +SECT_VEH_CAL_2 const tU16 c_usRESTS_TIMEOUTTIME_Limo = 600; +SECT_VEH_CAL_2 const tU08 c_ucRESTS_BLRSTEP_Limo = 3; +/* ------------------------------------------Rest mode: End*/ +SECT_VEH_CAL_2 const tU16 c_usFRESH_AIR_PURGE_ENTRY_TIME_Limo = 900; +SECT_VEH_CAL_2 const tU16 c_ausFRESH_AIR_PURGE_CHANGE_TIME_Limo[7] = { 10, 10, 10, 50, 10, 10, 10}; +/* ------------------------------------------Purge Rec: End*/ +SECT_VEH_CAL_2 const tS16 c_assMAX_DEF_U_DTG_Limo[10] = { 850, 850, 700, 550, 400, 350, 100, 50, 50, 50}; +SECT_VEH_CAL_2 const tU16 c_ausMAX_BLR_SPD_Limo[6] = { 160, 160, 160, 160, 160, 160}; +/* ------------------------------------------MAX DEF: End*/ +SECT_VEH_CAL_2 const tU08 c_aucAQS_REC_LV_CO_Limo[8] = { 0, 0, 0, 0, 0, 0, 0, 4}; +SECT_VEH_CAL_2 const tU08 c_aucAQS_OSA_LV_CO_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tU08 c_aucAQS_REC_LV_NOX_Limo[8] = { 0, 0, 0, 0, 0, 0, 0, 2}; +SECT_VEH_CAL_2 const tU08 c_aucAQS_OSA_LV_NOX_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tU08 c_aucAQS_REC_LV_NH3_Limo[8] = { 0, 0, 0, 0, 0, 0, 0, 2}; +SECT_VEH_CAL_2 const tU08 c_aucAQS_OSA_LV_NH3_Limo[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_2 const tU08 c_ucAQS_REC_ON_TIME_Limo = 30; +SECT_VEH_CAL_2 const tU08 c_aucAQS_REC_ON_WAIT_Limo[2] = { 60, 10}; +/* ------------------------------------------Aqs: End*/ +SECT_VEH_CAL_2 const tU16 c_usAUTODEMIST_LV2_BLR_PLUS_Limo = 10; +SECT_VEH_CAL_2 const tU16 c_usAUTODEMIST_LV3_BLR_PLUS_Limo = 30; +SECT_VEH_CAL_2 const tS16 c_assAUTODEMIST_OFFSET_AMB_TEMP_Limo[9] = { -50, -30, -20, -10, 0, 10, 20, 30, 50}; +SECT_VEH_CAL_2 const tS16 c_assAUTODEMIST_OFFSET_VENT_TEMP_Limo[9] = { 30, 25, 18, 11, 8, 8, 7, 5, 5}; +SECT_VEH_CAL_2 const tS16 c_assAUTODEMIST_STEP_UP_Limo[4] = { 50, 30, 20, -10}; +SECT_VEH_CAL_2 const tS16 c_assAUTODEMIST_STEP_DN_Limo[4] = { 55, 35, 25, 0}; +SECT_VEH_CAL_2 const tS16 c_assAUTODEMIST_WINTER_Limo[2] = { -35, -30}; +/* ------------------------------------------Auto Demist: End*/ +SECT_VEH_CAL_2 const tS16 c_ssAUTODEMIST_ELEC_AMB_ENTRY_Limo = -300; +SECT_VEH_CAL_2 const tS16 c_assAUTODEMIST_ELEC_WINDSHELD_TEMP_Limo[2] = { -250, -230}; +/* ------------------------------------------Electric AutoDemist: End*/ +SECT_VEH_CAL_2 const tS16 c_ssAMBFILT_WATER_Limo = 500; +SECT_VEH_CAL_2 const tU08 c_aucAMBFILT_H_CNT_Limo[2] = { 200, 200}; +SECT_VEH_CAL_2 const tS16 c_ssAMB_FAILSAFE_Limo = 230; +SECT_VEH_CAL_2 const tS16 c_ssAMBKEEP_KAT_Limo = 200; +SECT_VEH_CAL_2 const tS16 c_ssAMBKEEP_KAT_PLUS_Limo = 350; +SECT_VEH_CAL_2 const tS16 c_ssAMBKEEP_WATER_Limo = 500; +SECT_VEH_CAL_2 const tU08 c_aucAMBRATE_RISING_Limo[6] = { 30, 30, 30, 30, 30, 30}; +SECT_VEH_CAL_2 const tU08 c_aucAMBRATE_FALLING_Limo[6] = { 30, 30, 30, 30, 30, 30}; +SECT_VEH_CAL_2 const tU08 c_aucAMBRATE_RISING_DIFF_Limo[8] = { 120, 120, 120, 120, 155, 155, 155, 50}; +SECT_VEH_CAL_2 const tU08 c_aucAMBRATE_FALLING_DIFF_Limo[8] = { 120, 120, 120, 255, 255, 255, 155, 50}; +/* ------------------------------------------Ambient: End*/ +SECT_VEH_CAL_2 const tU16 c_ausINCARRATE_RISING_F_Limo[6] = { 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_2 const tU16 c_ausINCARRATE_FALLING_F_Limo[6] = { 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_2 const tU16 c_ausINCARRATE_RISING_DIFF_F_Limo[8] = { 100, 100, 100, 100, 100, 100, 50, 5}; +SECT_VEH_CAL_2 const tU16 c_ausINCARRATE_FALLING_DIFF_F_Limo[8] = { 40, 40, 40, 40, 40, 40, 50, 5}; +SECT_VEH_CAL_2 const tU16 c_ausINCARRATE_RISING_R_Limo[6] = { 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_2 const tU16 c_ausINCARRATE_FALLING_R_Limo[6] = { 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_2 const tU16 c_ausINCARRATE_RISING_DIFF_R_Limo[8] = { 100, 100, 100, 100, 100, 100, 50, 5}; +SECT_VEH_CAL_2 const tU16 c_ausINCARRATE_FALLING_DIFF_R_Limo[8] = { 40, 40, 40, 40, 40, 40, 50, 5}; +/* ------------------------------------------Incar: End*/ +SECT_VEH_CAL_2 const tU16 c_ausSUNRATE_RISING_Limo[6] = { 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_2 const tU16 c_ausSUNRATE_FALLING_Limo[6] = { 50, 50, 50, 50, 50, 50}; +/* ------------------------------------------Sun: End*/ +SECT_VEH_CAL_2 const tU16 c_ausAMB_LV_CHANGE_UNIT_Limo[6] = { 1, 1, 1, 10, 10, 3}; +SECT_VEH_CAL_2 const tU08 c_aucAMB_LV_CHANGE_SEC_Limo[6] = { 1, 1, 1, 1, 1, 1}; +/* ------------------------------------------Level Chage: End*/ +SECT_VEH_CAL_2 const tS16 c_ssTHREEWAY_WATER_Limo = 40; +SECT_VEH_CAL_2 const tS16 c_assTHREEWAY_DUCT_TGT_R_Limo[2] = { 15, 10}; +SECT_VEH_CAL_2 const tU08 c_aucTHEREEWAY_EXPIRING_Limo[2] = { 60, 5}; +/* ------------------------------------------Three way: End*/ +SECT_VEH_CAL_2 const tS16 c_assTWOWAY_REAR_DUCTTGT_R_Limo[2] = { 60, 50}; +SECT_VEH_CAL_2 const tU08 c_aucTWOWAY_EXPIRING_Limo[2] = { 60, 5}; +/* ------------------------------------------two-way: End*/ +SECT_VEH_CAL_2 const tU08 c_aucACT_HOM_SPD_FL_CH0_Limo[9] = { 3, 3, 3, 3, 3, 3, 3, 3, 3}; +SECT_VEH_CAL_2 const tU08 c_aucACT_HOM_SPD_FR_CH1_Limo[6] = { 3, 3, 3, 3, 3, 3}; +SECT_VEH_CAL_2 const tU08 c_aucACT_HOM_SPD_R_CH2_Limo[9] = { 3, 3, 3, 3, 3, 3, 3, 3, 3}; +SECT_VEH_CAL_2 const tU08 c_aucACT_HOM_SPD_R_EX_CH2_Limo[4] = { 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tU08 c_aucACT_MOV_SPD_FL_CH0_Limo[9] = { 3, 3, 3, 3, 3, 3, 3, 3, 3}; +SECT_VEH_CAL_2 const tU08 c_aucACT_MOV_SPD_FR_CH1_Limo[6] = { 3, 3, 3, 3, 3, 3}; +SECT_VEH_CAL_2 const tU08 c_aucACT_MOV_SPD_R_CH2_Limo[9] = { 3, 3, 3, 3, 3, 3, 3, 3, 3}; +SECT_VEH_CAL_2 const tU08 c_aucACT_MOV_SPD_R_EX_CH2_Limo[4] = { 0, 0, 0, 0}; +/* ------------------------------------------Actuator Homing: End*/ +SECT_VEH_CAL_2 const tS16 c_assHI_MODE_ENG_TMEP_Limo[6] = { 35, 45, 60, 80, 100, 120}; +SECT_VEH_CAL_2 const tU08 c_aucHI_MODE_BLR_STEP_STS_Limo[6] = { 2, 3, 4, 5, 100, 100}; +/* ------------------------------------------Hi Mode: End*/ +SECT_VEH_CAL_2 const tU16 c_ausMinusAF_GlassPos_L_Limo[13] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tU16 c_ausMinusAF_GlassPos_R_Limo[13] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +/* ------------------------------------------GlassPosition: End*/ +SECT_VEH_CAL_2 const tS16 c_assFoot2_Lv3_Amb_Limo[6] = { -150, -100, -50, 0, 50, 100}; +SECT_VEH_CAL_2 const tS16 c_assFoot2_Lv4_Amb_Limo[6] = { -300, -250, -200, -150, -100, -50}; +SECT_VEH_CAL_2 const tS16 c_assFoot2_Lv5_Amb_Limo[6] = { -700, -650, -600, -550, -500, -450}; +SECT_VEH_CAL_2 const tS16 c_assFoot2_Lv3_DuctTgt_Plus_Limo[6] = { 500, 500, 450, 400, 350, 300}; +SECT_VEH_CAL_2 const tS16 c_assFoot2_Lv4_DuctTgt_Plus_Limo[6] = { 500, 500, 450, 400, 350, 300}; +SECT_VEH_CAL_2 const tS16 c_assFoot2_Lv5_DuctTgt_Plus_Limo[6] = { 500, 500, 450, 400, 350, 300}; +SECT_VEH_CAL_2 const tU16 c_ausFoot2_Lv1_FrontBlr_X_Limo[3] = { 250, 500, 750}; +SECT_VEH_CAL_2 const tU16 c_ausFoot2_Lv1_Foot2Act_Y_Limo[3] = { 250, 500, 750}; +SECT_VEH_CAL_2 const tS16 c_assFoot2_Lv2_Threshold_Diff_Limo[2] = { 50, 35}; +SECT_VEH_CAL_2 const tS16 c_assFoot2_Lv3_Threshold_Diff_Limo[2] = { 50, 35}; +/* ------------------------------------------Foot2 Ctrl: End*/ +SECT_VEH_CAL_2 const tU16 c_ausDbF_Side_Af_Bi_Limo[9] = { 90, 91, 92, 93, 94, 95, 96, 97, 98}; +SECT_VEH_CAL_2 const tU16 c_ausDbF_Side_Af_Bi2_Limo[9] = { 90, 91, 92, 93, 94, 95, 96, 97, 98}; +SECT_VEH_CAL_2 const tU16 c_ausDbF_Side_Af_Vent_Limo[9] = { 70, 70, 65, 65, 62, 60, 55, 50, 50}; +SECT_VEH_CAL_2 const tU16 c_ausDbF_Side_Bi_Bi2_Limo[9] = { 80, 80, 80, 80, 80, 80, 80, 80, 80}; +SECT_VEH_CAL_2 const tU16 c_ausDbF_Side_Bi_Vent_Limo[9] = { 65, 65, 65, 65, 65, 65, 65, 65, 65}; +SECT_VEH_CAL_2 const tU16 c_ausDbF_Side_Bi2_Vent_Limo[9] = { 80, 80, 80, 80, 80, 80, 80, 80, 80}; +SECT_VEH_CAL_2 const tU16 c_ausDbF_Cen_Af_Bi_Limo[9] = { 90, 91, 92, 93, 94, 95, 96, 97, 98}; +SECT_VEH_CAL_2 const tU16 c_ausDbF_Cen_Af_Bi2_Limo[9] = { 90, 91, 92, 93, 94, 95, 96, 97, 98}; +SECT_VEH_CAL_2 const tU16 c_ausDbF_Cen_Af_Vent_Limo[9] = { 70, 70, 70, 65, 62, 60, 55, 50, 50}; +SECT_VEH_CAL_2 const tU16 c_ausDbF_Cen_Bi_Bi2_Limo[9] = { 80, 80, 80, 80, 80, 80, 80, 80, 80}; +SECT_VEH_CAL_2 const tU16 c_ausDbF_Cen_Bi_Vent_Limo[9] = { 65, 65, 65, 65, 65, 65, 65, 65, 65}; +SECT_VEH_CAL_2 const tU16 c_ausDbF_Cen_Bi2_Vent_Limo[9] = { 80, 80, 80, 80, 80, 80, 80, 80, 80}; +SECT_VEH_CAL_2 const tU16 c_ausDbF_Foot_Af_Bi_Limo[9] = { 90, 91, 92, 93, 94, 95, 96, 97, 98}; +SECT_VEH_CAL_2 const tU16 c_ausDbF_Foot_Af_Bi2_Limo[9] = { 90, 91, 92, 93, 94, 95, 96, 97, 98}; +SECT_VEH_CAL_2 const tU16 c_ausDbF_Foot_Af_Vent_Limo[9] = { 70, 70, 70, 65, 62, 60, 55, 50, 50}; +SECT_VEH_CAL_2 const tU16 c_ausDbF_Foot_Bi_Bi2_Limo[9] = { 80, 80, 80, 80, 80, 80, 80, 80, 80}; +SECT_VEH_CAL_2 const tU16 c_ausDbF_Foot_Bi_Vent_Limo[9] = { 65, 65, 65, 65, 65, 65, 65, 65, 65}; +SECT_VEH_CAL_2 const tU16 c_ausDbF_Foot_Bi2_Vent_Limo[9] = { 80, 80, 80, 80, 80, 80, 80, 80, 80}; +SECT_VEH_CAL_2 const tU16 c_ausDbF_AF_Af_Bi_Limo[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tU16 c_ausDbF_AF_Af_Bi2_Limo[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tU16 c_ausDbF_AF_Af_Vent_Limo[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tU16 c_ausDbF_AF_Bi_Bi2_Limo[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tU16 c_ausDbF_AF_Bi_Vent_Limo[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tU16 c_ausDbF_AF_Bi2_Vent_Limo[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_2 const tU16 c_ausDbF_Pwm_Af_Bi_Limo[9] = { 120, 120, 120, 120, 120, 120, 120, 120, 120}; +SECT_VEH_CAL_2 const tU16 c_ausDbF_Pwm_Af_Bi2_Limo[9] = { 120, 120, 120, 120, 120, 120, 120, 120, 120}; +SECT_VEH_CAL_2 const tU16 c_ausDbF_Pwm_Af_Vent_Limo[9] = { 120, 120, 85, 120, 120, 120, 120, 120, 120}; +SECT_VEH_CAL_2 const tU16 c_ausDbF_Pwm_Bi_Bi2_Limo[9] = { 120, 120, 120, 120, 120, 120, 120, 120, 120}; +SECT_VEH_CAL_2 const tU16 c_ausDbF_Pwm_Bi_Vent_Limo[9] = { 120, 120, 120, 120, 120, 120, 120, 120, 120}; +SECT_VEH_CAL_2 const tU16 c_ausDbF_Pwm_Bi2_Vent_Limo[9] = { 105, 120, 120, 90, 120, 120, 120, 105, 90}; +/* ------------------------------------------Different blower Front: End*/ +SECT_VEH_CAL_2 const tU16 c_usAromaPwm_Min_Limo = 200; +SECT_VEH_CAL_2 const tU16 c_usAromaPwm_Max_Limo = 700; +/* ------------------------------------------Aroma Limit Pwm: End*/ +/*********************************************************Cal Table End*/ + +/****************************************************************************** + * LOCAL VARIABLES DECLARATIONS + *****************************************************************************/ +/****************************************************************************** + * LOCAL FUNCTIONS DECLARATIONS + *****************************************************************************/ +/****************************************************************************** + * GLOBAL FUNCTIONS + *****************************************************************************/ + +/** Doxygen: Function brief + ****************************************************************************** + * @fn Rs_Cal_2_Limo(void) + * @brief No brief + * @remark No description + * @param[in] (All of const data in this file) + * @param[out] All of global variable in Rs_Cal_Base.c + * @return None + *****************************************************************************/ +void Rs_Cal_2_Limo(void) +{ + M_MEMCOPY((g_aucCAL_FP_DATE), (c_aucCAL_FP_DATE_Limo)); + M_MEMCOPY((g_aucCAL_VERSION), (c_aucCAL_VERSION_Limo)); + g_ucCAL_VARIANT = c_ucCAL_VARIANT_Limo; +/* ------------------------------------------Cal Version : End*/ + M_MEMCOPY((g_ausSET_TEMP_FULL), (c_ausSET_TEMP_FULL_Limo)); + M_MEMCOPY((g_ausSET_TEMP_HALF), (c_ausSET_TEMP_HALF_Limo)); +/* ------------------------------------------Set Temp : End*/ + M_MEMCOPY((g_assINCAR_TG_FL_LV0), (c_assINCAR_TG_FL_LV0_Limo)); + M_MEMCOPY((g_assINCAR_TG_FR_LV0), (c_assINCAR_TG_FR_LV0_Limo)); + M_MEMCOPY((g_assVTG_FL_LV0), (c_assVTG_FL_LV0_Limo)); + M_MEMCOPY((g_assVTG_FR_LV0), (c_assVTG_FR_LV0_Limo)); + M_MEMCOPY((g_assVF_MIN_LV0), (c_assVF_MIN_LV0_Limo)); + M_MEMCOPY((g_assVF_MAX_LV0), (c_assVF_MAX_LV0_Limo)); + M_MEMCOPY((g_assVF_INC_Y1_LV0), (c_assVF_INC_Y1_LV0_Limo)); + M_MEMCOPY((g_assVF_INC_Y2_LV0), (c_assVF_INC_Y2_LV0_Limo)); + M_MEMCOPY((g_assVF_INC_Y3_LV0), (c_assVF_INC_Y3_LV0_Limo)); + M_MEMCOPY((g_assVF_INC_Y4_LV0), (c_assVF_INC_Y4_LV0_Limo)); + M_MEMCOPY((g_assVF_INC_X1_LV0), (c_assVF_INC_X1_LV0_Limo)); + M_MEMCOPY((g_assVF_INC_X2_LV0), (c_assVF_INC_X2_LV0_Limo)); + M_MEMCOPY((g_assVF_INC_X3_LV0), (c_assVF_INC_X3_LV0_Limo)); + M_MEMCOPY((g_assVF_INC_X4_LV0), (c_assVF_INC_X4_LV0_Limo)); + M_MEMCOPY((g_assVF_AMB_Y1_LV0), (c_assVF_AMB_Y1_LV0_Limo)); + M_MEMCOPY((g_assVF_AMB_Y2_LV0), (c_assVF_AMB_Y2_LV0_Limo)); + M_MEMCOPY((g_assVF_AMB_X1_LV0), (c_assVF_AMB_X1_LV0_Limo)); + M_MEMCOPY((g_assVF_AMB_X2_LV0), (c_assVF_AMB_X2_LV0_Limo)); + M_MEMCOPY((g_assVF_SUN_Y1_LV0), (c_assVF_SUN_Y1_LV0_Limo)); + M_MEMCOPY((g_assVF_SUN_Y2_LV0), (c_assVF_SUN_Y2_LV0_Limo)); + M_MEMCOPY((g_assVF_SUN_X1_LV0), (c_assVF_SUN_X1_LV0_Limo)); + M_MEMCOPY((g_assVF_SUN_X2_LV0), (c_assVF_SUN_X2_LV0_Limo)); + M_MEMCOPY((g_assTG_FLU_LV0), (c_assTG_FLU_LV0_Limo)); + M_MEMCOPY((g_assTG_FRU_LV0), (c_assTG_FRU_LV0_Limo)); + M_MEMCOPY((g_assDTG_FU_MIN_LV0), (c_assDTG_FU_MIN_LV0_Limo)); + M_MEMCOPY((g_assDTG_FU_MAX_LV0), (c_assDTG_FU_MAX_LV0_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_Y1_LV0), (c_assDTG_FU_INC_Y1_LV0_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_Y2_LV0), (c_assDTG_FU_INC_Y2_LV0_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_Y3_LV0), (c_assDTG_FU_INC_Y3_LV0_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_Y4_LV0), (c_assDTG_FU_INC_Y4_LV0_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_X1_LV0), (c_assDTG_FU_INC_X1_LV0_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_X2_LV0), (c_assDTG_FU_INC_X2_LV0_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_X3_LV0), (c_assDTG_FU_INC_X3_LV0_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_X4_LV0), (c_assDTG_FU_INC_X4_LV0_Limo)); + M_MEMCOPY((g_assDTG_FU_AMB_Y1_LV0), (c_assDTG_FU_AMB_Y1_LV0_Limo)); + M_MEMCOPY((g_assDTG_FU_AMB_Y2_LV0), (c_assDTG_FU_AMB_Y2_LV0_Limo)); + M_MEMCOPY((g_assDTG_FU_AMB_X1_LV0), (c_assDTG_FU_AMB_X1_LV0_Limo)); + M_MEMCOPY((g_assDTG_FU_AMB_X2_LV0), (c_assDTG_FU_AMB_X2_LV0_Limo)); + M_MEMCOPY((g_assDTG_FU_SUN_Y1_LV0), (c_assDTG_FU_SUN_Y1_LV0_Limo)); + M_MEMCOPY((g_assDTG_FU_SUN_Y2_LV0), (c_assDTG_FU_SUN_Y2_LV0_Limo)); + M_MEMCOPY((g_assDTG_FU_SUN_X1_LV0), (c_assDTG_FU_SUN_X1_LV0_Limo)); + M_MEMCOPY((g_assDTG_FU_SUN_X2_LV0), (c_assDTG_FU_SUN_X2_LV0_Limo)); + M_MEMCOPY((g_assTG_FLL_LV0), (c_assTG_FLL_LV0_Limo)); + M_MEMCOPY((g_assTG_FRL_LV0), (c_assTG_FRL_LV0_Limo)); + M_MEMCOPY((g_assDTG_FL_MIN_LV0), (c_assDTG_FL_MIN_LV0_Limo)); + M_MEMCOPY((g_assDTG_FL_MAX_LV0), (c_assDTG_FL_MAX_LV0_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_Y1_LV0), (c_assDTG_FL_INC_Y1_LV0_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_Y2_LV0), (c_assDTG_FL_INC_Y2_LV0_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_Y3_LV0), (c_assDTG_FL_INC_Y3_LV0_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_Y4_LV0), (c_assDTG_FL_INC_Y4_LV0_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_X1_LV0), (c_assDTG_FL_INC_X1_LV0_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_X2_LV0), (c_assDTG_FL_INC_X2_LV0_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_X3_LV0), (c_assDTG_FL_INC_X3_LV0_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_X4_LV0), (c_assDTG_FL_INC_X4_LV0_Limo)); + M_MEMCOPY((g_assDTG_FL_AMB_Y1_LV0), (c_assDTG_FL_AMB_Y1_LV0_Limo)); + M_MEMCOPY((g_assDTG_FL_AMB_Y2_LV0), (c_assDTG_FL_AMB_Y2_LV0_Limo)); + M_MEMCOPY((g_assDTG_FL_AMB_X1_LV0), (c_assDTG_FL_AMB_X1_LV0_Limo)); + M_MEMCOPY((g_assDTG_FL_AMB_X2_LV0), (c_assDTG_FL_AMB_X2_LV0_Limo)); + M_MEMCOPY((g_assDTG_FL_SUN_Y1_LV0), (c_assDTG_FL_SUN_Y1_LV0_Limo)); + M_MEMCOPY((g_assDTG_FL_SUN_Y2_LV0), (c_assDTG_FL_SUN_Y2_LV0_Limo)); + M_MEMCOPY((g_assDTG_FL_SUN_X1_LV0), (c_assDTG_FL_SUN_X1_LV0_Limo)); + M_MEMCOPY((g_assDTG_FL_SUN_X2_LV0), (c_assDTG_FL_SUN_X2_LV0_Limo)); + M_MEMCOPY((g_assINCAR_TG_RL_LV0), (c_assINCAR_TG_RL_LV0_Limo)); + M_MEMCOPY((g_assINCAR_TG_RR_LV0), (c_assINCAR_TG_RR_LV0_Limo)); + M_MEMCOPY((g_assVTG_RL_LV0), (c_assVTG_RL_LV0_Limo)); + M_MEMCOPY((g_assVTG_RR_LV0), (c_assVTG_RR_LV0_Limo)); + M_MEMCOPY((g_assVR_MIN_LV0), (c_assVR_MIN_LV0_Limo)); + M_MEMCOPY((g_assVR_MAX_LV0), (c_assVR_MAX_LV0_Limo)); + M_MEMCOPY((g_assVR_INC_Y1_LV0), (c_assVR_INC_Y1_LV0_Limo)); + M_MEMCOPY((g_assVR_INC_Y2_LV0), (c_assVR_INC_Y2_LV0_Limo)); + M_MEMCOPY((g_assVR_INC_Y3_LV0), (c_assVR_INC_Y3_LV0_Limo)); + M_MEMCOPY((g_assVR_INC_Y4_LV0), (c_assVR_INC_Y4_LV0_Limo)); + M_MEMCOPY((g_assVR_INC_X1_LV0), (c_assVR_INC_X1_LV0_Limo)); + M_MEMCOPY((g_assVR_INC_X2_LV0), (c_assVR_INC_X2_LV0_Limo)); + M_MEMCOPY((g_assVR_INC_X3_LV0), (c_assVR_INC_X3_LV0_Limo)); + M_MEMCOPY((g_assVR_INC_X4_LV0), (c_assVR_INC_X4_LV0_Limo)); + M_MEMCOPY((g_assVR_AMB_Y1_LV0), (c_assVR_AMB_Y1_LV0_Limo)); + M_MEMCOPY((g_assVR_AMB_Y2_LV0), (c_assVR_AMB_Y2_LV0_Limo)); + M_MEMCOPY((g_assVR_AMB_X1_LV0), (c_assVR_AMB_X1_LV0_Limo)); + M_MEMCOPY((g_assVR_AMB_X2_LV0), (c_assVR_AMB_X2_LV0_Limo)); + M_MEMCOPY((g_assVR_SUN_Y1_LV0), (c_assVR_SUN_Y1_LV0_Limo)); + M_MEMCOPY((g_assVR_SUN_Y2_LV0), (c_assVR_SUN_Y2_LV0_Limo)); + M_MEMCOPY((g_assVR_SUN_X1_LV0), (c_assVR_SUN_X1_LV0_Limo)); + M_MEMCOPY((g_assVR_SUN_X2_LV0), (c_assVR_SUN_X2_LV0_Limo)); + M_MEMCOPY((g_assTG_RL_LV0), (c_assTG_RL_LV0_Limo)); + M_MEMCOPY((g_assTG_RR_LV0), (c_assTG_RR_LV0_Limo)); + M_MEMCOPY((g_assDTG_R_MIN_LV0), (c_assDTG_R_MIN_LV0_Limo)); + M_MEMCOPY((g_assDTG_R_MAX_LV0), (c_assDTG_R_MAX_LV0_Limo)); + M_MEMCOPY((g_assDTG_R_INC_Y1_LV0), (c_assDTG_R_INC_Y1_LV0_Limo)); + M_MEMCOPY((g_assDTG_R_INC_Y2_LV0), (c_assDTG_R_INC_Y2_LV0_Limo)); + M_MEMCOPY((g_assDTG_R_INC_Y3_LV0), (c_assDTG_R_INC_Y3_LV0_Limo)); + M_MEMCOPY((g_assDTG_R_INC_Y4_LV0), (c_assDTG_R_INC_Y4_LV0_Limo)); + M_MEMCOPY((g_assDTG_R_INC_X1_LV0), (c_assDTG_R_INC_X1_LV0_Limo)); + M_MEMCOPY((g_assDTG_R_INC_X2_LV0), (c_assDTG_R_INC_X2_LV0_Limo)); + M_MEMCOPY((g_assDTG_R_INC_X3_LV0), (c_assDTG_R_INC_X3_LV0_Limo)); + M_MEMCOPY((g_assDTG_R_INC_X4_LV0), (c_assDTG_R_INC_X4_LV0_Limo)); + M_MEMCOPY((g_assDTG_R_AMB_Y1_LV0), (c_assDTG_R_AMB_Y1_LV0_Limo)); + M_MEMCOPY((g_assDTG_R_AMB_Y2_LV0), (c_assDTG_R_AMB_Y2_LV0_Limo)); + M_MEMCOPY((g_assDTG_R_AMB_X1_LV0), (c_assDTG_R_AMB_X1_LV0_Limo)); + M_MEMCOPY((g_assDTG_R_AMB_X2_LV0), (c_assDTG_R_AMB_X2_LV0_Limo)); + M_MEMCOPY((g_assDTG_R_SUN_Y1_LV0), (c_assDTG_R_SUN_Y1_LV0_Limo)); + M_MEMCOPY((g_assDTG_R_SUN_Y2_LV0), (c_assDTG_R_SUN_Y2_LV0_Limo)); + M_MEMCOPY((g_assDTG_R_SUN_X1_LV0), (c_assDTG_R_SUN_X1_LV0_Limo)); + M_MEMCOPY((g_assDTG_R_SUN_X2_LV0), (c_assDTG_R_SUN_X2_LV0_Limo)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FR_LV0), (c_assCORRECT_DUCT_TIME_FR_LV0_Limo)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FL_LV0), (c_assCORRECT_DUCT_TIME_FL_LV0_Limo)); + M_MEMCOPY((g_assCORRECT_DUCT_RATE_LV0), (c_assCORRECT_DUCT_RATE_LV0_Limo)); + M_MEMCOPY((g_assCORRECT_DUCT_MAX_LV0), (c_assCORRECT_DUCT_MAX_LV0_Limo)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FR_LV0), (c_assCORRECT_AF_TIME_FR_LV0_Limo)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FL_LV0), (c_assCORRECT_AF_TIME_FL_LV0_Limo)); + M_MEMCOPY((g_assCORRECT_AF_RATE_LV0), (c_assCORRECT_AF_RATE_LV0_Limo)); + M_MEMCOPY((g_assCORRECT_AF_MAX_LV0), (c_assCORRECT_AF_MAX_LV0_Limo)); +/* ------------------------------------------Lv0 : End*/ + M_MEMCOPY((g_assINCAR_TG_FL_LV1), (c_assINCAR_TG_FL_LV1_Limo)); + M_MEMCOPY((g_assINCAR_TG_FR_LV1), (c_assINCAR_TG_FR_LV1_Limo)); + M_MEMCOPY((g_assVTG_FL_LV1), (c_assVTG_FL_LV1_Limo)); + M_MEMCOPY((g_assVTG_FR_LV1), (c_assVTG_FR_LV1_Limo)); + M_MEMCOPY((g_assVF_MIN_LV1), (c_assVF_MIN_LV1_Limo)); + M_MEMCOPY((g_assVF_MAX_LV1), (c_assVF_MAX_LV1_Limo)); + M_MEMCOPY((g_assVF_INC_Y1_LV1), (c_assVF_INC_Y1_LV1_Limo)); + M_MEMCOPY((g_assVF_INC_Y2_LV1), (c_assVF_INC_Y2_LV1_Limo)); + M_MEMCOPY((g_assVF_INC_Y3_LV1), (c_assVF_INC_Y3_LV1_Limo)); + M_MEMCOPY((g_assVF_INC_Y4_LV1), (c_assVF_INC_Y4_LV1_Limo)); + M_MEMCOPY((g_assVF_INC_X1_LV1), (c_assVF_INC_X1_LV1_Limo)); + M_MEMCOPY((g_assVF_INC_X2_LV1), (c_assVF_INC_X2_LV1_Limo)); + M_MEMCOPY((g_assVF_INC_X3_LV1), (c_assVF_INC_X3_LV1_Limo)); + M_MEMCOPY((g_assVF_INC_X4_LV1), (c_assVF_INC_X4_LV1_Limo)); + M_MEMCOPY((g_assVF_AMB_Y1_LV1), (c_assVF_AMB_Y1_LV1_Limo)); + M_MEMCOPY((g_assVF_AMB_Y2_LV1), (c_assVF_AMB_Y2_LV1_Limo)); + M_MEMCOPY((g_assVF_AMB_X1_LV1), (c_assVF_AMB_X1_LV1_Limo)); + M_MEMCOPY((g_assVF_AMB_X2_LV1), (c_assVF_AMB_X2_LV1_Limo)); + M_MEMCOPY((g_assVF_SUN_Y1_LV1), (c_assVF_SUN_Y1_LV1_Limo)); + M_MEMCOPY((g_assVF_SUN_Y2_LV1), (c_assVF_SUN_Y2_LV1_Limo)); + M_MEMCOPY((g_assVF_SUN_X1_LV1), (c_assVF_SUN_X1_LV1_Limo)); + M_MEMCOPY((g_assVF_SUN_X2_LV1), (c_assVF_SUN_X2_LV1_Limo)); + M_MEMCOPY((g_assTG_FLU_LV1), (c_assTG_FLU_LV1_Limo)); + M_MEMCOPY((g_assTG_FRU_LV1), (c_assTG_FRU_LV1_Limo)); + M_MEMCOPY((g_assDTG_FU_MIN_LV1), (c_assDTG_FU_MIN_LV1_Limo)); + M_MEMCOPY((g_assDTG_FU_MAX_LV1), (c_assDTG_FU_MAX_LV1_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_Y1_LV1), (c_assDTG_FU_INC_Y1_LV1_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_Y2_LV1), (c_assDTG_FU_INC_Y2_LV1_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_Y3_LV1), (c_assDTG_FU_INC_Y3_LV1_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_Y4_LV1), (c_assDTG_FU_INC_Y4_LV1_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_X1_LV1), (c_assDTG_FU_INC_X1_LV1_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_X2_LV1), (c_assDTG_FU_INC_X2_LV1_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_X3_LV1), (c_assDTG_FU_INC_X3_LV1_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_X4_LV1), (c_assDTG_FU_INC_X4_LV1_Limo)); + M_MEMCOPY((g_assDTG_FU_AMB_Y1_LV1), (c_assDTG_FU_AMB_Y1_LV1_Limo)); + M_MEMCOPY((g_assDTG_FU_AMB_Y2_LV1), (c_assDTG_FU_AMB_Y2_LV1_Limo)); + M_MEMCOPY((g_assDTG_FU_AMB_X1_LV1), (c_assDTG_FU_AMB_X1_LV1_Limo)); + M_MEMCOPY((g_assDTG_FU_AMB_X2_LV1), (c_assDTG_FU_AMB_X2_LV1_Limo)); + M_MEMCOPY((g_assDTG_FU_SUN_Y1_LV1), (c_assDTG_FU_SUN_Y1_LV1_Limo)); + M_MEMCOPY((g_assDTG_FU_SUN_Y2_LV1), (c_assDTG_FU_SUN_Y2_LV1_Limo)); + M_MEMCOPY((g_assDTG_FU_SUN_X1_LV1), (c_assDTG_FU_SUN_X1_LV1_Limo)); + M_MEMCOPY((g_assDTG_FU_SUN_X2_LV1), (c_assDTG_FU_SUN_X2_LV1_Limo)); + M_MEMCOPY((g_assTG_FLL_LV1), (c_assTG_FLL_LV1_Limo)); + M_MEMCOPY((g_assTG_FRL_LV1), (c_assTG_FRL_LV1_Limo)); + M_MEMCOPY((g_assDTG_FL_MIN_LV1), (c_assDTG_FL_MIN_LV1_Limo)); + M_MEMCOPY((g_assDTG_FL_MAX_LV1), (c_assDTG_FL_MAX_LV1_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_Y1_LV1), (c_assDTG_FL_INC_Y1_LV1_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_Y2_LV1), (c_assDTG_FL_INC_Y2_LV1_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_Y3_LV1), (c_assDTG_FL_INC_Y3_LV1_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_Y4_LV1), (c_assDTG_FL_INC_Y4_LV1_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_X1_LV1), (c_assDTG_FL_INC_X1_LV1_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_X2_LV1), (c_assDTG_FL_INC_X2_LV1_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_X3_LV1), (c_assDTG_FL_INC_X3_LV1_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_X4_LV1), (c_assDTG_FL_INC_X4_LV1_Limo)); + M_MEMCOPY((g_assDTG_FL_AMB_Y1_LV1), (c_assDTG_FL_AMB_Y1_LV1_Limo)); + M_MEMCOPY((g_assDTG_FL_AMB_Y2_LV1), (c_assDTG_FL_AMB_Y2_LV1_Limo)); + M_MEMCOPY((g_assDTG_FL_AMB_X1_LV1), (c_assDTG_FL_AMB_X1_LV1_Limo)); + M_MEMCOPY((g_assDTG_FL_AMB_X2_LV1), (c_assDTG_FL_AMB_X2_LV1_Limo)); + M_MEMCOPY((g_assDTG_FL_SUN_Y1_LV1), (c_assDTG_FL_SUN_Y1_LV1_Limo)); + M_MEMCOPY((g_assDTG_FL_SUN_Y2_LV1), (c_assDTG_FL_SUN_Y2_LV1_Limo)); + M_MEMCOPY((g_assDTG_FL_SUN_X1_LV1), (c_assDTG_FL_SUN_X1_LV1_Limo)); + M_MEMCOPY((g_assDTG_FL_SUN_X2_LV1), (c_assDTG_FL_SUN_X2_LV1_Limo)); + M_MEMCOPY((g_assINCAR_TG_RL_LV1), (c_assINCAR_TG_RL_LV1_Limo)); + M_MEMCOPY((g_assINCAR_TG_RR_LV1), (c_assINCAR_TG_RR_LV1_Limo)); + M_MEMCOPY((g_assVTG_RL_LV1), (c_assVTG_RL_LV1_Limo)); + M_MEMCOPY((g_assVTG_RR_LV1), (c_assVTG_RR_LV1_Limo)); + M_MEMCOPY((g_assVR_MIN_LV1), (c_assVR_MIN_LV1_Limo)); + M_MEMCOPY((g_assVR_MAX_LV1), (c_assVR_MAX_LV1_Limo)); + M_MEMCOPY((g_assVR_INC_Y1_LV1), (c_assVR_INC_Y1_LV1_Limo)); + M_MEMCOPY((g_assVR_INC_Y2_LV1), (c_assVR_INC_Y2_LV1_Limo)); + M_MEMCOPY((g_assVR_INC_Y3_LV1), (c_assVR_INC_Y3_LV1_Limo)); + M_MEMCOPY((g_assVR_INC_Y4_LV1), (c_assVR_INC_Y4_LV1_Limo)); + M_MEMCOPY((g_assVR_INC_X1_LV1), (c_assVR_INC_X1_LV1_Limo)); + M_MEMCOPY((g_assVR_INC_X2_LV1), (c_assVR_INC_X2_LV1_Limo)); + M_MEMCOPY((g_assVR_INC_X3_LV1), (c_assVR_INC_X3_LV1_Limo)); + M_MEMCOPY((g_assVR_INC_X4_LV1), (c_assVR_INC_X4_LV1_Limo)); + M_MEMCOPY((g_assVR_AMB_Y1_LV1), (c_assVR_AMB_Y1_LV1_Limo)); + M_MEMCOPY((g_assVR_AMB_Y2_LV1), (c_assVR_AMB_Y2_LV1_Limo)); + M_MEMCOPY((g_assVR_AMB_X1_LV1), (c_assVR_AMB_X1_LV1_Limo)); + M_MEMCOPY((g_assVR_AMB_X2_LV1), (c_assVR_AMB_X2_LV1_Limo)); + M_MEMCOPY((g_assVR_SUN_Y1_LV1), (c_assVR_SUN_Y1_LV1_Limo)); + M_MEMCOPY((g_assVR_SUN_Y2_LV1), (c_assVR_SUN_Y2_LV1_Limo)); + M_MEMCOPY((g_assVR_SUN_X1_LV1), (c_assVR_SUN_X1_LV1_Limo)); + M_MEMCOPY((g_assVR_SUN_X2_LV1), (c_assVR_SUN_X2_LV1_Limo)); + M_MEMCOPY((g_assTG_RL_LV1), (c_assTG_RL_LV1_Limo)); + M_MEMCOPY((g_assTG_RR_LV1), (c_assTG_RR_LV1_Limo)); + M_MEMCOPY((g_assDTG_R_MIN_LV1), (c_assDTG_R_MIN_LV1_Limo)); + M_MEMCOPY((g_assDTG_R_MAX_LV1), (c_assDTG_R_MAX_LV1_Limo)); + M_MEMCOPY((g_assDTG_R_INC_Y1_LV1), (c_assDTG_R_INC_Y1_LV1_Limo)); + M_MEMCOPY((g_assDTG_R_INC_Y2_LV1), (c_assDTG_R_INC_Y2_LV1_Limo)); + M_MEMCOPY((g_assDTG_R_INC_Y3_LV1), (c_assDTG_R_INC_Y3_LV1_Limo)); + M_MEMCOPY((g_assDTG_R_INC_Y4_LV1), (c_assDTG_R_INC_Y4_LV1_Limo)); + M_MEMCOPY((g_assDTG_R_INC_X1_LV1), (c_assDTG_R_INC_X1_LV1_Limo)); + M_MEMCOPY((g_assDTG_R_INC_X2_LV1), (c_assDTG_R_INC_X2_LV1_Limo)); + M_MEMCOPY((g_assDTG_R_INC_X3_LV1), (c_assDTG_R_INC_X3_LV1_Limo)); + M_MEMCOPY((g_assDTG_R_INC_X4_LV1), (c_assDTG_R_INC_X4_LV1_Limo)); + M_MEMCOPY((g_assDTG_R_AMB_Y1_LV1), (c_assDTG_R_AMB_Y1_LV1_Limo)); + M_MEMCOPY((g_assDTG_R_AMB_Y2_LV1), (c_assDTG_R_AMB_Y2_LV1_Limo)); + M_MEMCOPY((g_assDTG_R_AMB_X1_LV1), (c_assDTG_R_AMB_X1_LV1_Limo)); + M_MEMCOPY((g_assDTG_R_AMB_X2_LV1), (c_assDTG_R_AMB_X2_LV1_Limo)); + M_MEMCOPY((g_assDTG_R_SUN_Y1_LV1), (c_assDTG_R_SUN_Y1_LV1_Limo)); + M_MEMCOPY((g_assDTG_R_SUN_Y2_LV1), (c_assDTG_R_SUN_Y2_LV1_Limo)); + M_MEMCOPY((g_assDTG_R_SUN_X1_LV1), (c_assDTG_R_SUN_X1_LV1_Limo)); + M_MEMCOPY((g_assDTG_R_SUN_X2_LV1), (c_assDTG_R_SUN_X2_LV1_Limo)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FR_LV1), (c_assCORRECT_DUCT_TIME_FR_LV1_Limo)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FL_LV1), (c_assCORRECT_DUCT_TIME_FL_LV1_Limo)); + M_MEMCOPY((g_assCORRECT_DUCT_RATE_LV1), (c_assCORRECT_DUCT_RATE_LV1_Limo)); + M_MEMCOPY((g_assCORRECT_DUCT_MAX_LV1), (c_assCORRECT_DUCT_MAX_LV1_Limo)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FR_LV1), (c_assCORRECT_AF_TIME_FR_LV1_Limo)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FL_LV1), (c_assCORRECT_AF_TIME_FL_LV1_Limo)); + M_MEMCOPY((g_assCORRECT_AF_RATE_LV1), (c_assCORRECT_AF_RATE_LV1_Limo)); + M_MEMCOPY((g_assCORRECT_AF_MAX_LV1), (c_assCORRECT_AF_MAX_LV1_Limo)); +/* ------------------------------------------Lv1 : End*/ + M_MEMCOPY((g_assINCAR_TG_FL_LV2), (c_assINCAR_TG_FL_LV2_Limo)); + M_MEMCOPY((g_assINCAR_TG_FR_LV2), (c_assINCAR_TG_FR_LV2_Limo)); + M_MEMCOPY((g_assVTG_FL_LV2), (c_assVTG_FL_LV2_Limo)); + M_MEMCOPY((g_assVTG_FR_LV2), (c_assVTG_FR_LV2_Limo)); + M_MEMCOPY((g_assVF_MIN_LV2), (c_assVF_MIN_LV2_Limo)); + M_MEMCOPY((g_assVF_MAX_LV2), (c_assVF_MAX_LV2_Limo)); + M_MEMCOPY((g_assVF_INC_Y1_LV2), (c_assVF_INC_Y1_LV2_Limo)); + M_MEMCOPY((g_assVF_INC_Y2_LV2), (c_assVF_INC_Y2_LV2_Limo)); + M_MEMCOPY((g_assVF_INC_Y3_LV2), (c_assVF_INC_Y3_LV2_Limo)); + M_MEMCOPY((g_assVF_INC_Y4_LV2), (c_assVF_INC_Y4_LV2_Limo)); + M_MEMCOPY((g_assVF_INC_X1_LV2), (c_assVF_INC_X1_LV2_Limo)); + M_MEMCOPY((g_assVF_INC_X2_LV2), (c_assVF_INC_X2_LV2_Limo)); + M_MEMCOPY((g_assVF_INC_X3_LV2), (c_assVF_INC_X3_LV2_Limo)); + M_MEMCOPY((g_assVF_INC_X4_LV2), (c_assVF_INC_X4_LV2_Limo)); + M_MEMCOPY((g_assVF_AMB_Y1_LV2), (c_assVF_AMB_Y1_LV2_Limo)); + M_MEMCOPY((g_assVF_AMB_Y2_LV2), (c_assVF_AMB_Y2_LV2_Limo)); + M_MEMCOPY((g_assVF_AMB_X1_LV2), (c_assVF_AMB_X1_LV2_Limo)); + M_MEMCOPY((g_assVF_AMB_X2_LV2), (c_assVF_AMB_X2_LV2_Limo)); + M_MEMCOPY((g_assVF_SUN_Y1_LV2), (c_assVF_SUN_Y1_LV2_Limo)); + M_MEMCOPY((g_assVF_SUN_Y2_LV2), (c_assVF_SUN_Y2_LV2_Limo)); + M_MEMCOPY((g_assVF_SUN_X1_LV2), (c_assVF_SUN_X1_LV2_Limo)); + M_MEMCOPY((g_assVF_SUN_X2_LV2), (c_assVF_SUN_X2_LV2_Limo)); + M_MEMCOPY((g_assTG_FLU_LV2), (c_assTG_FLU_LV2_Limo)); + M_MEMCOPY((g_assTG_FRU_LV2), (c_assTG_FRU_LV2_Limo)); + M_MEMCOPY((g_assDTG_FU_MIN_LV2), (c_assDTG_FU_MIN_LV2_Limo)); + M_MEMCOPY((g_assDTG_FU_MAX_LV2), (c_assDTG_FU_MAX_LV2_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_Y1_LV2), (c_assDTG_FU_INC_Y1_LV2_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_Y2_LV2), (c_assDTG_FU_INC_Y2_LV2_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_Y3_LV2), (c_assDTG_FU_INC_Y3_LV2_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_Y4_LV2), (c_assDTG_FU_INC_Y4_LV2_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_X1_LV2), (c_assDTG_FU_INC_X1_LV2_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_X2_LV2), (c_assDTG_FU_INC_X2_LV2_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_X3_LV2), (c_assDTG_FU_INC_X3_LV2_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_X4_LV2), (c_assDTG_FU_INC_X4_LV2_Limo)); + M_MEMCOPY((g_assDTG_FU_AMB_Y1_LV2), (c_assDTG_FU_AMB_Y1_LV2_Limo)); + M_MEMCOPY((g_assDTG_FU_AMB_Y2_LV2), (c_assDTG_FU_AMB_Y2_LV2_Limo)); + M_MEMCOPY((g_assDTG_FU_AMB_X1_LV2), (c_assDTG_FU_AMB_X1_LV2_Limo)); + M_MEMCOPY((g_assDTG_FU_AMB_X2_LV2), (c_assDTG_FU_AMB_X2_LV2_Limo)); + M_MEMCOPY((g_assDTG_FU_SUN_Y1_LV2), (c_assDTG_FU_SUN_Y1_LV2_Limo)); + M_MEMCOPY((g_assDTG_FU_SUN_Y2_LV2), (c_assDTG_FU_SUN_Y2_LV2_Limo)); + M_MEMCOPY((g_assDTG_FU_SUN_X1_LV2), (c_assDTG_FU_SUN_X1_LV2_Limo)); + M_MEMCOPY((g_assDTG_FU_SUN_X2_LV2), (c_assDTG_FU_SUN_X2_LV2_Limo)); + M_MEMCOPY((g_assTG_FLL_LV2), (c_assTG_FLL_LV2_Limo)); + M_MEMCOPY((g_assTG_FRL_LV2), (c_assTG_FRL_LV2_Limo)); + M_MEMCOPY((g_assDTG_FL_MIN_LV2), (c_assDTG_FL_MIN_LV2_Limo)); + M_MEMCOPY((g_assDTG_FL_MAX_LV2), (c_assDTG_FL_MAX_LV2_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_Y1_LV2), (c_assDTG_FL_INC_Y1_LV2_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_Y2_LV2), (c_assDTG_FL_INC_Y2_LV2_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_Y3_LV2), (c_assDTG_FL_INC_Y3_LV2_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_Y4_LV2), (c_assDTG_FL_INC_Y4_LV2_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_X1_LV2), (c_assDTG_FL_INC_X1_LV2_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_X2_LV2), (c_assDTG_FL_INC_X2_LV2_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_X3_LV2), (c_assDTG_FL_INC_X3_LV2_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_X4_LV2), (c_assDTG_FL_INC_X4_LV2_Limo)); + M_MEMCOPY((g_assDTG_FL_AMB_Y1_LV2), (c_assDTG_FL_AMB_Y1_LV2_Limo)); + M_MEMCOPY((g_assDTG_FL_AMB_Y2_LV2), (c_assDTG_FL_AMB_Y2_LV2_Limo)); + M_MEMCOPY((g_assDTG_FL_AMB_X1_LV2), (c_assDTG_FL_AMB_X1_LV2_Limo)); + M_MEMCOPY((g_assDTG_FL_AMB_X2_LV2), (c_assDTG_FL_AMB_X2_LV2_Limo)); + M_MEMCOPY((g_assDTG_FL_SUN_Y1_LV2), (c_assDTG_FL_SUN_Y1_LV2_Limo)); + M_MEMCOPY((g_assDTG_FL_SUN_Y2_LV2), (c_assDTG_FL_SUN_Y2_LV2_Limo)); + M_MEMCOPY((g_assDTG_FL_SUN_X1_LV2), (c_assDTG_FL_SUN_X1_LV2_Limo)); + M_MEMCOPY((g_assDTG_FL_SUN_X2_LV2), (c_assDTG_FL_SUN_X2_LV2_Limo)); + M_MEMCOPY((g_assINCAR_TG_RL_LV2), (c_assINCAR_TG_RL_LV2_Limo)); + M_MEMCOPY((g_assINCAR_TG_RR_LV2), (c_assINCAR_TG_RR_LV2_Limo)); + M_MEMCOPY((g_assVTG_RL_LV2), (c_assVTG_RL_LV2_Limo)); + M_MEMCOPY((g_assVTG_RR_LV2), (c_assVTG_RR_LV2_Limo)); + M_MEMCOPY((g_assVR_MIN_LV2), (c_assVR_MIN_LV2_Limo)); + M_MEMCOPY((g_assVR_MAX_LV2), (c_assVR_MAX_LV2_Limo)); + M_MEMCOPY((g_assVR_INC_Y1_LV2), (c_assVR_INC_Y1_LV2_Limo)); + M_MEMCOPY((g_assVR_INC_Y2_LV2), (c_assVR_INC_Y2_LV2_Limo)); + M_MEMCOPY((g_assVR_INC_Y3_LV2), (c_assVR_INC_Y3_LV2_Limo)); + M_MEMCOPY((g_assVR_INC_Y4_LV2), (c_assVR_INC_Y4_LV2_Limo)); + M_MEMCOPY((g_assVR_INC_X1_LV2), (c_assVR_INC_X1_LV2_Limo)); + M_MEMCOPY((g_assVR_INC_X2_LV2), (c_assVR_INC_X2_LV2_Limo)); + M_MEMCOPY((g_assVR_INC_X3_LV2), (c_assVR_INC_X3_LV2_Limo)); + M_MEMCOPY((g_assVR_INC_X4_LV2), (c_assVR_INC_X4_LV2_Limo)); + M_MEMCOPY((g_assVR_AMB_Y1_LV2), (c_assVR_AMB_Y1_LV2_Limo)); + M_MEMCOPY((g_assVR_AMB_Y2_LV2), (c_assVR_AMB_Y2_LV2_Limo)); + M_MEMCOPY((g_assVR_AMB_X1_LV2), (c_assVR_AMB_X1_LV2_Limo)); + M_MEMCOPY((g_assVR_AMB_X2_LV2), (c_assVR_AMB_X2_LV2_Limo)); + M_MEMCOPY((g_assVR_SUN_Y1_LV2), (c_assVR_SUN_Y1_LV2_Limo)); + M_MEMCOPY((g_assVR_SUN_Y2_LV2), (c_assVR_SUN_Y2_LV2_Limo)); + M_MEMCOPY((g_assVR_SUN_X1_LV2), (c_assVR_SUN_X1_LV2_Limo)); + M_MEMCOPY((g_assVR_SUN_X2_LV2), (c_assVR_SUN_X2_LV2_Limo)); + M_MEMCOPY((g_assTG_RL_LV2), (c_assTG_RL_LV2_Limo)); + M_MEMCOPY((g_assTG_RR_LV2), (c_assTG_RR_LV2_Limo)); + M_MEMCOPY((g_assDTG_R_MIN_LV2), (c_assDTG_R_MIN_LV2_Limo)); + M_MEMCOPY((g_assDTG_R_MAX_LV2), (c_assDTG_R_MAX_LV2_Limo)); + M_MEMCOPY((g_assDTG_R_INC_Y1_LV2), (c_assDTG_R_INC_Y1_LV2_Limo)); + M_MEMCOPY((g_assDTG_R_INC_Y2_LV2), (c_assDTG_R_INC_Y2_LV2_Limo)); + M_MEMCOPY((g_assDTG_R_INC_Y3_LV2), (c_assDTG_R_INC_Y3_LV2_Limo)); + M_MEMCOPY((g_assDTG_R_INC_Y4_LV2), (c_assDTG_R_INC_Y4_LV2_Limo)); + M_MEMCOPY((g_assDTG_R_INC_X1_LV2), (c_assDTG_R_INC_X1_LV2_Limo)); + M_MEMCOPY((g_assDTG_R_INC_X2_LV2), (c_assDTG_R_INC_X2_LV2_Limo)); + M_MEMCOPY((g_assDTG_R_INC_X3_LV2), (c_assDTG_R_INC_X3_LV2_Limo)); + M_MEMCOPY((g_assDTG_R_INC_X4_LV2), (c_assDTG_R_INC_X4_LV2_Limo)); + M_MEMCOPY((g_assDTG_R_AMB_Y1_LV2), (c_assDTG_R_AMB_Y1_LV2_Limo)); + M_MEMCOPY((g_assDTG_R_AMB_Y2_LV2), (c_assDTG_R_AMB_Y2_LV2_Limo)); + M_MEMCOPY((g_assDTG_R_AMB_X1_LV2), (c_assDTG_R_AMB_X1_LV2_Limo)); + M_MEMCOPY((g_assDTG_R_AMB_X2_LV2), (c_assDTG_R_AMB_X2_LV2_Limo)); + M_MEMCOPY((g_assDTG_R_SUN_Y1_LV2), (c_assDTG_R_SUN_Y1_LV2_Limo)); + M_MEMCOPY((g_assDTG_R_SUN_Y2_LV2), (c_assDTG_R_SUN_Y2_LV2_Limo)); + M_MEMCOPY((g_assDTG_R_SUN_X1_LV2), (c_assDTG_R_SUN_X1_LV2_Limo)); + M_MEMCOPY((g_assDTG_R_SUN_X2_LV2), (c_assDTG_R_SUN_X2_LV2_Limo)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FR_LV2), (c_assCORRECT_DUCT_TIME_FR_LV2_Limo)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FL_LV2), (c_assCORRECT_DUCT_TIME_FL_LV2_Limo)); + M_MEMCOPY((g_assCORRECT_DUCT_RATE_LV2), (c_assCORRECT_DUCT_RATE_LV2_Limo)); + M_MEMCOPY((g_assCORRECT_DUCT_MAX_LV2), (c_assCORRECT_DUCT_MAX_LV2_Limo)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FR_LV2), (c_assCORRECT_AF_TIME_FR_LV2_Limo)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FL_LV2), (c_assCORRECT_AF_TIME_FL_LV2_Limo)); + M_MEMCOPY((g_assCORRECT_AF_RATE_LV2), (c_assCORRECT_AF_RATE_LV2_Limo)); + M_MEMCOPY((g_assCORRECT_AF_MAX_LV2), (c_assCORRECT_AF_MAX_LV2_Limo)); +/* ------------------------------------------Lv2 : End*/ + M_MEMCOPY((g_assINCAR_TG_FL_LV3), (c_assINCAR_TG_FL_LV3_Limo)); + M_MEMCOPY((g_assINCAR_TG_FR_LV3), (c_assINCAR_TG_FR_LV3_Limo)); + M_MEMCOPY((g_assVTG_FL_LV3), (c_assVTG_FL_LV3_Limo)); + M_MEMCOPY((g_assVTG_FR_LV3), (c_assVTG_FR_LV3_Limo)); + M_MEMCOPY((g_assVF_MIN_LV3), (c_assVF_MIN_LV3_Limo)); + M_MEMCOPY((g_assVF_MAX_LV3), (c_assVF_MAX_LV3_Limo)); + M_MEMCOPY((g_assVF_INC_Y1_LV3), (c_assVF_INC_Y1_LV3_Limo)); + M_MEMCOPY((g_assVF_INC_Y2_LV3), (c_assVF_INC_Y2_LV3_Limo)); + M_MEMCOPY((g_assVF_INC_Y3_LV3), (c_assVF_INC_Y3_LV3_Limo)); + M_MEMCOPY((g_assVF_INC_Y4_LV3), (c_assVF_INC_Y4_LV3_Limo)); + M_MEMCOPY((g_assVF_INC_X1_LV3), (c_assVF_INC_X1_LV3_Limo)); + M_MEMCOPY((g_assVF_INC_X2_LV3), (c_assVF_INC_X2_LV3_Limo)); + M_MEMCOPY((g_assVF_INC_X3_LV3), (c_assVF_INC_X3_LV3_Limo)); + M_MEMCOPY((g_assVF_INC_X4_LV3), (c_assVF_INC_X4_LV3_Limo)); + M_MEMCOPY((g_assVF_AMB_Y1_LV3), (c_assVF_AMB_Y1_LV3_Limo)); + M_MEMCOPY((g_assVF_AMB_Y2_LV3), (c_assVF_AMB_Y2_LV3_Limo)); + M_MEMCOPY((g_assVF_AMB_X1_LV3), (c_assVF_AMB_X1_LV3_Limo)); + M_MEMCOPY((g_assVF_AMB_X2_LV3), (c_assVF_AMB_X2_LV3_Limo)); + M_MEMCOPY((g_assVF_SUN_Y1_LV3), (c_assVF_SUN_Y1_LV3_Limo)); + M_MEMCOPY((g_assVF_SUN_Y2_LV3), (c_assVF_SUN_Y2_LV3_Limo)); + M_MEMCOPY((g_assVF_SUN_X1_LV3), (c_assVF_SUN_X1_LV3_Limo)); + M_MEMCOPY((g_assVF_SUN_X2_LV3), (c_assVF_SUN_X2_LV3_Limo)); + M_MEMCOPY((g_assTG_FLU_LV3), (c_assTG_FLU_LV3_Limo)); + M_MEMCOPY((g_assTG_FRU_LV3), (c_assTG_FRU_LV3_Limo)); + M_MEMCOPY((g_assDTG_FU_MIN_LV3), (c_assDTG_FU_MIN_LV3_Limo)); + M_MEMCOPY((g_assDTG_FU_MAX_LV3), (c_assDTG_FU_MAX_LV3_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_Y1_LV3), (c_assDTG_FU_INC_Y1_LV3_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_Y2_LV3), (c_assDTG_FU_INC_Y2_LV3_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_Y3_LV3), (c_assDTG_FU_INC_Y3_LV3_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_Y4_LV3), (c_assDTG_FU_INC_Y4_LV3_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_X1_LV3), (c_assDTG_FU_INC_X1_LV3_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_X2_LV3), (c_assDTG_FU_INC_X2_LV3_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_X3_LV3), (c_assDTG_FU_INC_X3_LV3_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_X4_LV3), (c_assDTG_FU_INC_X4_LV3_Limo)); + M_MEMCOPY((g_assDTG_FU_AMB_Y1_LV3), (c_assDTG_FU_AMB_Y1_LV3_Limo)); + M_MEMCOPY((g_assDTG_FU_AMB_Y2_LV3), (c_assDTG_FU_AMB_Y2_LV3_Limo)); + M_MEMCOPY((g_assDTG_FU_AMB_X1_LV3), (c_assDTG_FU_AMB_X1_LV3_Limo)); + M_MEMCOPY((g_assDTG_FU_AMB_X2_LV3), (c_assDTG_FU_AMB_X2_LV3_Limo)); + M_MEMCOPY((g_assDTG_FU_SUN_Y1_LV3), (c_assDTG_FU_SUN_Y1_LV3_Limo)); + M_MEMCOPY((g_assDTG_FU_SUN_Y2_LV3), (c_assDTG_FU_SUN_Y2_LV3_Limo)); + M_MEMCOPY((g_assDTG_FU_SUN_X1_LV3), (c_assDTG_FU_SUN_X1_LV3_Limo)); + M_MEMCOPY((g_assDTG_FU_SUN_X2_LV3), (c_assDTG_FU_SUN_X2_LV3_Limo)); + M_MEMCOPY((g_assTG_FLL_LV3), (c_assTG_FLL_LV3_Limo)); + M_MEMCOPY((g_assTG_FRL_LV3), (c_assTG_FRL_LV3_Limo)); + M_MEMCOPY((g_assDTG_FL_MIN_LV3), (c_assDTG_FL_MIN_LV3_Limo)); + M_MEMCOPY((g_assDTG_FL_MAX_LV3), (c_assDTG_FL_MAX_LV3_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_Y1_LV3), (c_assDTG_FL_INC_Y1_LV3_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_Y2_LV3), (c_assDTG_FL_INC_Y2_LV3_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_Y3_LV3), (c_assDTG_FL_INC_Y3_LV3_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_Y4_LV3), (c_assDTG_FL_INC_Y4_LV3_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_X1_LV3), (c_assDTG_FL_INC_X1_LV3_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_X2_LV3), (c_assDTG_FL_INC_X2_LV3_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_X3_LV3), (c_assDTG_FL_INC_X3_LV3_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_X4_LV3), (c_assDTG_FL_INC_X4_LV3_Limo)); + M_MEMCOPY((g_assDTG_FL_AMB_Y1_LV3), (c_assDTG_FL_AMB_Y1_LV3_Limo)); + M_MEMCOPY((g_assDTG_FL_AMB_Y2_LV3), (c_assDTG_FL_AMB_Y2_LV3_Limo)); + M_MEMCOPY((g_assDTG_FL_AMB_X1_LV3), (c_assDTG_FL_AMB_X1_LV3_Limo)); + M_MEMCOPY((g_assDTG_FL_AMB_X2_LV3), (c_assDTG_FL_AMB_X2_LV3_Limo)); + M_MEMCOPY((g_assDTG_FL_SUN_Y1_LV3), (c_assDTG_FL_SUN_Y1_LV3_Limo)); + M_MEMCOPY((g_assDTG_FL_SUN_Y2_LV3), (c_assDTG_FL_SUN_Y2_LV3_Limo)); + M_MEMCOPY((g_assDTG_FL_SUN_X1_LV3), (c_assDTG_FL_SUN_X1_LV3_Limo)); + M_MEMCOPY((g_assDTG_FL_SUN_X2_LV3), (c_assDTG_FL_SUN_X2_LV3_Limo)); + M_MEMCOPY((g_assINCAR_TG_RL_LV3), (c_assINCAR_TG_RL_LV3_Limo)); + M_MEMCOPY((g_assINCAR_TG_RR_LV3), (c_assINCAR_TG_RR_LV3_Limo)); + M_MEMCOPY((g_assVTG_RL_LV3), (c_assVTG_RL_LV3_Limo)); + M_MEMCOPY((g_assVTG_RR_LV3), (c_assVTG_RR_LV3_Limo)); + M_MEMCOPY((g_assVR_MIN_LV3), (c_assVR_MIN_LV3_Limo)); + M_MEMCOPY((g_assVR_MAX_LV3), (c_assVR_MAX_LV3_Limo)); + M_MEMCOPY((g_assVR_INC_Y1_LV3), (c_assVR_INC_Y1_LV3_Limo)); + M_MEMCOPY((g_assVR_INC_Y2_LV3), (c_assVR_INC_Y2_LV3_Limo)); + M_MEMCOPY((g_assVR_INC_Y3_LV3), (c_assVR_INC_Y3_LV3_Limo)); + M_MEMCOPY((g_assVR_INC_Y4_LV3), (c_assVR_INC_Y4_LV3_Limo)); + M_MEMCOPY((g_assVR_INC_X1_LV3), (c_assVR_INC_X1_LV3_Limo)); + M_MEMCOPY((g_assVR_INC_X2_LV3), (c_assVR_INC_X2_LV3_Limo)); + M_MEMCOPY((g_assVR_INC_X3_LV3), (c_assVR_INC_X3_LV3_Limo)); + M_MEMCOPY((g_assVR_INC_X4_LV3), (c_assVR_INC_X4_LV3_Limo)); + M_MEMCOPY((g_assVR_AMB_Y1_LV3), (c_assVR_AMB_Y1_LV3_Limo)); + M_MEMCOPY((g_assVR_AMB_Y2_LV3), (c_assVR_AMB_Y2_LV3_Limo)); + M_MEMCOPY((g_assVR_AMB_X1_LV3), (c_assVR_AMB_X1_LV3_Limo)); + M_MEMCOPY((g_assVR_AMB_X2_LV3), (c_assVR_AMB_X2_LV3_Limo)); + M_MEMCOPY((g_assVR_SUN_Y1_LV3), (c_assVR_SUN_Y1_LV3_Limo)); + M_MEMCOPY((g_assVR_SUN_Y2_LV3), (c_assVR_SUN_Y2_LV3_Limo)); + M_MEMCOPY((g_assVR_SUN_X1_LV3), (c_assVR_SUN_X1_LV3_Limo)); + M_MEMCOPY((g_assVR_SUN_X2_LV3), (c_assVR_SUN_X2_LV3_Limo)); + M_MEMCOPY((g_assTG_RL_LV3), (c_assTG_RL_LV3_Limo)); + M_MEMCOPY((g_assTG_RR_LV3), (c_assTG_RR_LV3_Limo)); + M_MEMCOPY((g_assDTG_R_MIN_LV3), (c_assDTG_R_MIN_LV3_Limo)); + M_MEMCOPY((g_assDTG_R_MAX_LV3), (c_assDTG_R_MAX_LV3_Limo)); + M_MEMCOPY((g_assDTG_R_INC_Y1_LV3), (c_assDTG_R_INC_Y1_LV3_Limo)); + M_MEMCOPY((g_assDTG_R_INC_Y2_LV3), (c_assDTG_R_INC_Y2_LV3_Limo)); + M_MEMCOPY((g_assDTG_R_INC_Y3_LV3), (c_assDTG_R_INC_Y3_LV3_Limo)); + M_MEMCOPY((g_assDTG_R_INC_Y4_LV3), (c_assDTG_R_INC_Y4_LV3_Limo)); + M_MEMCOPY((g_assDTG_R_INC_X1_LV3), (c_assDTG_R_INC_X1_LV3_Limo)); + M_MEMCOPY((g_assDTG_R_INC_X2_LV3), (c_assDTG_R_INC_X2_LV3_Limo)); + M_MEMCOPY((g_assDTG_R_INC_X3_LV3), (c_assDTG_R_INC_X3_LV3_Limo)); + M_MEMCOPY((g_assDTG_R_INC_X4_LV3), (c_assDTG_R_INC_X4_LV3_Limo)); + M_MEMCOPY((g_assDTG_R_AMB_Y1_LV3), (c_assDTG_R_AMB_Y1_LV3_Limo)); + M_MEMCOPY((g_assDTG_R_AMB_Y2_LV3), (c_assDTG_R_AMB_Y2_LV3_Limo)); + M_MEMCOPY((g_assDTG_R_AMB_X1_LV3), (c_assDTG_R_AMB_X1_LV3_Limo)); + M_MEMCOPY((g_assDTG_R_AMB_X2_LV3), (c_assDTG_R_AMB_X2_LV3_Limo)); + M_MEMCOPY((g_assDTG_R_SUN_Y1_LV3), (c_assDTG_R_SUN_Y1_LV3_Limo)); + M_MEMCOPY((g_assDTG_R_SUN_Y2_LV3), (c_assDTG_R_SUN_Y2_LV3_Limo)); + M_MEMCOPY((g_assDTG_R_SUN_X1_LV3), (c_assDTG_R_SUN_X1_LV3_Limo)); + M_MEMCOPY((g_assDTG_R_SUN_X2_LV3), (c_assDTG_R_SUN_X2_LV3_Limo)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FR_LV3), (c_assCORRECT_DUCT_TIME_FR_LV3_Limo)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FL_LV3), (c_assCORRECT_DUCT_TIME_FL_LV3_Limo)); + M_MEMCOPY((g_assCORRECT_DUCT_RATE_LV3), (c_assCORRECT_DUCT_RATE_LV3_Limo)); + M_MEMCOPY((g_assCORRECT_DUCT_MAX_LV3), (c_assCORRECT_DUCT_MAX_LV3_Limo)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FR_LV3), (c_assCORRECT_AF_TIME_FR_LV3_Limo)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FL_LV3), (c_assCORRECT_AF_TIME_FL_LV3_Limo)); + M_MEMCOPY((g_assCORRECT_AF_RATE_LV3), (c_assCORRECT_AF_RATE_LV3_Limo)); + M_MEMCOPY((g_assCORRECT_AF_MAX_LV3), (c_assCORRECT_AF_MAX_LV3_Limo)); +/* ------------------------------------------Lv3 : End*/ + M_MEMCOPY((g_assINCAR_TG_FL_LV4), (c_assINCAR_TG_FL_LV4_Limo)); + M_MEMCOPY((g_assINCAR_TG_FR_LV4), (c_assINCAR_TG_FR_LV4_Limo)); + M_MEMCOPY((g_assVTG_FL_LV4), (c_assVTG_FL_LV4_Limo)); + M_MEMCOPY((g_assVTG_FR_LV4), (c_assVTG_FR_LV4_Limo)); + M_MEMCOPY((g_assVF_MIN_LV4), (c_assVF_MIN_LV4_Limo)); + M_MEMCOPY((g_assVF_MAX_LV4), (c_assVF_MAX_LV4_Limo)); + M_MEMCOPY((g_assVF_INC_Y1_LV4), (c_assVF_INC_Y1_LV4_Limo)); + M_MEMCOPY((g_assVF_INC_Y2_LV4), (c_assVF_INC_Y2_LV4_Limo)); + M_MEMCOPY((g_assVF_INC_Y3_LV4), (c_assVF_INC_Y3_LV4_Limo)); + M_MEMCOPY((g_assVF_INC_Y4_LV4), (c_assVF_INC_Y4_LV4_Limo)); + M_MEMCOPY((g_assVF_INC_X1_LV4), (c_assVF_INC_X1_LV4_Limo)); + M_MEMCOPY((g_assVF_INC_X2_LV4), (c_assVF_INC_X2_LV4_Limo)); + M_MEMCOPY((g_assVF_INC_X3_LV4), (c_assVF_INC_X3_LV4_Limo)); + M_MEMCOPY((g_assVF_INC_X4_LV4), (c_assVF_INC_X4_LV4_Limo)); + M_MEMCOPY((g_assVF_AMB_Y1_LV4), (c_assVF_AMB_Y1_LV4_Limo)); + M_MEMCOPY((g_assVF_AMB_Y2_LV4), (c_assVF_AMB_Y2_LV4_Limo)); + M_MEMCOPY((g_assVF_AMB_X1_LV4), (c_assVF_AMB_X1_LV4_Limo)); + M_MEMCOPY((g_assVF_AMB_X2_LV4), (c_assVF_AMB_X2_LV4_Limo)); + M_MEMCOPY((g_assVF_SUN_Y1_LV4), (c_assVF_SUN_Y1_LV4_Limo)); + M_MEMCOPY((g_assVF_SUN_Y2_LV4), (c_assVF_SUN_Y2_LV4_Limo)); + M_MEMCOPY((g_assVF_SUN_X1_LV4), (c_assVF_SUN_X1_LV4_Limo)); + M_MEMCOPY((g_assVF_SUN_X2_LV4), (c_assVF_SUN_X2_LV4_Limo)); + M_MEMCOPY((g_assTG_FLU_LV4), (c_assTG_FLU_LV4_Limo)); + M_MEMCOPY((g_assTG_FRU_LV4), (c_assTG_FRU_LV4_Limo)); + M_MEMCOPY((g_assDTG_FU_MIN_LV4), (c_assDTG_FU_MIN_LV4_Limo)); + M_MEMCOPY((g_assDTG_FU_MAX_LV4), (c_assDTG_FU_MAX_LV4_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_Y1_LV4), (c_assDTG_FU_INC_Y1_LV4_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_Y2_LV4), (c_assDTG_FU_INC_Y2_LV4_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_Y3_LV4), (c_assDTG_FU_INC_Y3_LV4_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_Y4_LV4), (c_assDTG_FU_INC_Y4_LV4_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_X1_LV4), (c_assDTG_FU_INC_X1_LV4_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_X2_LV4), (c_assDTG_FU_INC_X2_LV4_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_X3_LV4), (c_assDTG_FU_INC_X3_LV4_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_X4_LV4), (c_assDTG_FU_INC_X4_LV4_Limo)); + M_MEMCOPY((g_assDTG_FU_AMB_Y1_LV4), (c_assDTG_FU_AMB_Y1_LV4_Limo)); + M_MEMCOPY((g_assDTG_FU_AMB_Y2_LV4), (c_assDTG_FU_AMB_Y2_LV4_Limo)); + M_MEMCOPY((g_assDTG_FU_AMB_X1_LV4), (c_assDTG_FU_AMB_X1_LV4_Limo)); + M_MEMCOPY((g_assDTG_FU_AMB_X2_LV4), (c_assDTG_FU_AMB_X2_LV4_Limo)); + M_MEMCOPY((g_assDTG_FU_SUN_Y1_LV4), (c_assDTG_FU_SUN_Y1_LV4_Limo)); + M_MEMCOPY((g_assDTG_FU_SUN_Y2_LV4), (c_assDTG_FU_SUN_Y2_LV4_Limo)); + M_MEMCOPY((g_assDTG_FU_SUN_X1_LV4), (c_assDTG_FU_SUN_X1_LV4_Limo)); + M_MEMCOPY((g_assDTG_FU_SUN_X2_LV4), (c_assDTG_FU_SUN_X2_LV4_Limo)); + M_MEMCOPY((g_assTG_FLL_LV4), (c_assTG_FLL_LV4_Limo)); + M_MEMCOPY((g_assTG_FRL_LV4), (c_assTG_FRL_LV4_Limo)); + M_MEMCOPY((g_assDTG_FL_MIN_LV4), (c_assDTG_FL_MIN_LV4_Limo)); + M_MEMCOPY((g_assDTG_FL_MAX_LV4), (c_assDTG_FL_MAX_LV4_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_Y1_LV4), (c_assDTG_FL_INC_Y1_LV4_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_Y2_LV4), (c_assDTG_FL_INC_Y2_LV4_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_Y3_LV4), (c_assDTG_FL_INC_Y3_LV4_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_Y4_LV4), (c_assDTG_FL_INC_Y4_LV4_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_X1_LV4), (c_assDTG_FL_INC_X1_LV4_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_X2_LV4), (c_assDTG_FL_INC_X2_LV4_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_X3_LV4), (c_assDTG_FL_INC_X3_LV4_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_X4_LV4), (c_assDTG_FL_INC_X4_LV4_Limo)); + M_MEMCOPY((g_assDTG_FL_AMB_Y1_LV4), (c_assDTG_FL_AMB_Y1_LV4_Limo)); + M_MEMCOPY((g_assDTG_FL_AMB_Y2_LV4), (c_assDTG_FL_AMB_Y2_LV4_Limo)); + M_MEMCOPY((g_assDTG_FL_AMB_X1_LV4), (c_assDTG_FL_AMB_X1_LV4_Limo)); + M_MEMCOPY((g_assDTG_FL_AMB_X2_LV4), (c_assDTG_FL_AMB_X2_LV4_Limo)); + M_MEMCOPY((g_assDTG_FL_SUN_Y1_LV4), (c_assDTG_FL_SUN_Y1_LV4_Limo)); + M_MEMCOPY((g_assDTG_FL_SUN_Y2_LV4), (c_assDTG_FL_SUN_Y2_LV4_Limo)); + M_MEMCOPY((g_assDTG_FL_SUN_X1_LV4), (c_assDTG_FL_SUN_X1_LV4_Limo)); + M_MEMCOPY((g_assDTG_FL_SUN_X2_LV4), (c_assDTG_FL_SUN_X2_LV4_Limo)); + M_MEMCOPY((g_assINCAR_TG_RL_LV4), (c_assINCAR_TG_RL_LV4_Limo)); + M_MEMCOPY((g_assINCAR_TG_RR_LV4), (c_assINCAR_TG_RR_LV4_Limo)); + M_MEMCOPY((g_assVTG_RL_LV4), (c_assVTG_RL_LV4_Limo)); + M_MEMCOPY((g_assVTG_RR_LV4), (c_assVTG_RR_LV4_Limo)); + M_MEMCOPY((g_assVR_MIN_LV4), (c_assVR_MIN_LV4_Limo)); + M_MEMCOPY((g_assVR_MAX_LV4), (c_assVR_MAX_LV4_Limo)); + M_MEMCOPY((g_assVR_INC_Y1_LV4), (c_assVR_INC_Y1_LV4_Limo)); + M_MEMCOPY((g_assVR_INC_Y2_LV4), (c_assVR_INC_Y2_LV4_Limo)); + M_MEMCOPY((g_assVR_INC_Y3_LV4), (c_assVR_INC_Y3_LV4_Limo)); + M_MEMCOPY((g_assVR_INC_Y4_LV4), (c_assVR_INC_Y4_LV4_Limo)); + M_MEMCOPY((g_assVR_INC_X1_LV4), (c_assVR_INC_X1_LV4_Limo)); + M_MEMCOPY((g_assVR_INC_X2_LV4), (c_assVR_INC_X2_LV4_Limo)); + M_MEMCOPY((g_assVR_INC_X3_LV4), (c_assVR_INC_X3_LV4_Limo)); + M_MEMCOPY((g_assVR_INC_X4_LV4), (c_assVR_INC_X4_LV4_Limo)); + M_MEMCOPY((g_assVR_AMB_Y1_LV4), (c_assVR_AMB_Y1_LV4_Limo)); + M_MEMCOPY((g_assVR_AMB_Y2_LV4), (c_assVR_AMB_Y2_LV4_Limo)); + M_MEMCOPY((g_assVR_AMB_X1_LV4), (c_assVR_AMB_X1_LV4_Limo)); + M_MEMCOPY((g_assVR_AMB_X2_LV4), (c_assVR_AMB_X2_LV4_Limo)); + M_MEMCOPY((g_assVR_SUN_Y1_LV4), (c_assVR_SUN_Y1_LV4_Limo)); + M_MEMCOPY((g_assVR_SUN_Y2_LV4), (c_assVR_SUN_Y2_LV4_Limo)); + M_MEMCOPY((g_assVR_SUN_X1_LV4), (c_assVR_SUN_X1_LV4_Limo)); + M_MEMCOPY((g_assVR_SUN_X2_LV4), (c_assVR_SUN_X2_LV4_Limo)); + M_MEMCOPY((g_assTG_RL_LV4), (c_assTG_RL_LV4_Limo)); + M_MEMCOPY((g_assTG_RR_LV4), (c_assTG_RR_LV4_Limo)); + M_MEMCOPY((g_assDTG_R_MIN_LV4), (c_assDTG_R_MIN_LV4_Limo)); + M_MEMCOPY((g_assDTG_R_MAX_LV4), (c_assDTG_R_MAX_LV4_Limo)); + M_MEMCOPY((g_assDTG_R_INC_Y1_LV4), (c_assDTG_R_INC_Y1_LV4_Limo)); + M_MEMCOPY((g_assDTG_R_INC_Y2_LV4), (c_assDTG_R_INC_Y2_LV4_Limo)); + M_MEMCOPY((g_assDTG_R_INC_Y3_LV4), (c_assDTG_R_INC_Y3_LV4_Limo)); + M_MEMCOPY((g_assDTG_R_INC_Y4_LV4), (c_assDTG_R_INC_Y4_LV4_Limo)); + M_MEMCOPY((g_assDTG_R_INC_X1_LV4), (c_assDTG_R_INC_X1_LV4_Limo)); + M_MEMCOPY((g_assDTG_R_INC_X2_LV4), (c_assDTG_R_INC_X2_LV4_Limo)); + M_MEMCOPY((g_assDTG_R_INC_X3_LV4), (c_assDTG_R_INC_X3_LV4_Limo)); + M_MEMCOPY((g_assDTG_R_INC_X4_LV4), (c_assDTG_R_INC_X4_LV4_Limo)); + M_MEMCOPY((g_assDTG_R_AMB_Y1_LV4), (c_assDTG_R_AMB_Y1_LV4_Limo)); + M_MEMCOPY((g_assDTG_R_AMB_Y2_LV4), (c_assDTG_R_AMB_Y2_LV4_Limo)); + M_MEMCOPY((g_assDTG_R_AMB_X1_LV4), (c_assDTG_R_AMB_X1_LV4_Limo)); + M_MEMCOPY((g_assDTG_R_AMB_X2_LV4), (c_assDTG_R_AMB_X2_LV4_Limo)); + M_MEMCOPY((g_assDTG_R_SUN_Y1_LV4), (c_assDTG_R_SUN_Y1_LV4_Limo)); + M_MEMCOPY((g_assDTG_R_SUN_Y2_LV4), (c_assDTG_R_SUN_Y2_LV4_Limo)); + M_MEMCOPY((g_assDTG_R_SUN_X1_LV4), (c_assDTG_R_SUN_X1_LV4_Limo)); + M_MEMCOPY((g_assDTG_R_SUN_X2_LV4), (c_assDTG_R_SUN_X2_LV4_Limo)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FR_LV4), (c_assCORRECT_DUCT_TIME_FR_LV4_Limo)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FL_LV4), (c_assCORRECT_DUCT_TIME_FL_LV4_Limo)); + M_MEMCOPY((g_assCORRECT_DUCT_RATE_LV4), (c_assCORRECT_DUCT_RATE_LV4_Limo)); + M_MEMCOPY((g_assCORRECT_DUCT_MAX_LV4), (c_assCORRECT_DUCT_MAX_LV4_Limo)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FR_LV4), (c_assCORRECT_AF_TIME_FR_LV4_Limo)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FL_LV4), (c_assCORRECT_AF_TIME_FL_LV4_Limo)); + M_MEMCOPY((g_assCORRECT_AF_RATE_LV4), (c_assCORRECT_AF_RATE_LV4_Limo)); + M_MEMCOPY((g_assCORRECT_AF_MAX_LV4), (c_assCORRECT_AF_MAX_LV4_Limo)); +/* ------------------------------------------Lv4 : End*/ + M_MEMCOPY((g_assINCAR_TG_FL_LV5), (c_assINCAR_TG_FL_LV5_Limo)); + M_MEMCOPY((g_assINCAR_TG_FR_LV5), (c_assINCAR_TG_FR_LV5_Limo)); + M_MEMCOPY((g_assVTG_FL_LV5), (c_assVTG_FL_LV5_Limo)); + M_MEMCOPY((g_assVTG_FR_LV5), (c_assVTG_FR_LV5_Limo)); + M_MEMCOPY((g_assVF_MIN_LV5), (c_assVF_MIN_LV5_Limo)); + M_MEMCOPY((g_assVF_MAX_LV5), (c_assVF_MAX_LV5_Limo)); + M_MEMCOPY((g_assVF_INC_Y1_LV5), (c_assVF_INC_Y1_LV5_Limo)); + M_MEMCOPY((g_assVF_INC_Y2_LV5), (c_assVF_INC_Y2_LV5_Limo)); + M_MEMCOPY((g_assVF_INC_Y3_LV5), (c_assVF_INC_Y3_LV5_Limo)); + M_MEMCOPY((g_assVF_INC_Y4_LV5), (c_assVF_INC_Y4_LV5_Limo)); + M_MEMCOPY((g_assVF_INC_X1_LV5), (c_assVF_INC_X1_LV5_Limo)); + M_MEMCOPY((g_assVF_INC_X2_LV5), (c_assVF_INC_X2_LV5_Limo)); + M_MEMCOPY((g_assVF_INC_X3_LV5), (c_assVF_INC_X3_LV5_Limo)); + M_MEMCOPY((g_assVF_INC_X4_LV5), (c_assVF_INC_X4_LV5_Limo)); + M_MEMCOPY((g_assVF_AMB_Y1_LV5), (c_assVF_AMB_Y1_LV5_Limo)); + M_MEMCOPY((g_assVF_AMB_Y2_LV5), (c_assVF_AMB_Y2_LV5_Limo)); + M_MEMCOPY((g_assVF_AMB_X1_LV5), (c_assVF_AMB_X1_LV5_Limo)); + M_MEMCOPY((g_assVF_AMB_X2_LV5), (c_assVF_AMB_X2_LV5_Limo)); + M_MEMCOPY((g_assVF_SUN_Y1_LV5), (c_assVF_SUN_Y1_LV5_Limo)); + M_MEMCOPY((g_assVF_SUN_Y2_LV5), (c_assVF_SUN_Y2_LV5_Limo)); + M_MEMCOPY((g_assVF_SUN_X1_LV5), (c_assVF_SUN_X1_LV5_Limo)); + M_MEMCOPY((g_assVF_SUN_X2_LV5), (c_assVF_SUN_X2_LV5_Limo)); + M_MEMCOPY((g_assTG_FLU_LV5), (c_assTG_FLU_LV5_Limo)); + M_MEMCOPY((g_assTG_FRU_LV5), (c_assTG_FRU_LV5_Limo)); + M_MEMCOPY((g_assDTG_FU_MIN_LV5), (c_assDTG_FU_MIN_LV5_Limo)); + M_MEMCOPY((g_assDTG_FU_MAX_LV5), (c_assDTG_FU_MAX_LV5_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_Y1_LV5), (c_assDTG_FU_INC_Y1_LV5_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_Y2_LV5), (c_assDTG_FU_INC_Y2_LV5_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_Y3_LV5), (c_assDTG_FU_INC_Y3_LV5_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_Y4_LV5), (c_assDTG_FU_INC_Y4_LV5_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_X1_LV5), (c_assDTG_FU_INC_X1_LV5_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_X2_LV5), (c_assDTG_FU_INC_X2_LV5_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_X3_LV5), (c_assDTG_FU_INC_X3_LV5_Limo)); + M_MEMCOPY((g_assDTG_FU_INC_X4_LV5), (c_assDTG_FU_INC_X4_LV5_Limo)); + M_MEMCOPY((g_assDTG_FU_AMB_Y1_LV5), (c_assDTG_FU_AMB_Y1_LV5_Limo)); + M_MEMCOPY((g_assDTG_FU_AMB_Y2_LV5), (c_assDTG_FU_AMB_Y2_LV5_Limo)); + M_MEMCOPY((g_assDTG_FU_AMB_X1_LV5), (c_assDTG_FU_AMB_X1_LV5_Limo)); + M_MEMCOPY((g_assDTG_FU_AMB_X2_LV5), (c_assDTG_FU_AMB_X2_LV5_Limo)); + M_MEMCOPY((g_assDTG_FU_SUN_Y1_LV5), (c_assDTG_FU_SUN_Y1_LV5_Limo)); + M_MEMCOPY((g_assDTG_FU_SUN_Y2_LV5), (c_assDTG_FU_SUN_Y2_LV5_Limo)); + M_MEMCOPY((g_assDTG_FU_SUN_X1_LV5), (c_assDTG_FU_SUN_X1_LV5_Limo)); + M_MEMCOPY((g_assDTG_FU_SUN_X2_LV5), (c_assDTG_FU_SUN_X2_LV5_Limo)); + M_MEMCOPY((g_assTG_FLL_LV5), (c_assTG_FLL_LV5_Limo)); + M_MEMCOPY((g_assTG_FRL_LV5), (c_assTG_FRL_LV5_Limo)); + M_MEMCOPY((g_assDTG_FL_MIN_LV5), (c_assDTG_FL_MIN_LV5_Limo)); + M_MEMCOPY((g_assDTG_FL_MAX_LV5), (c_assDTG_FL_MAX_LV5_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_Y1_LV5), (c_assDTG_FL_INC_Y1_LV5_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_Y2_LV5), (c_assDTG_FL_INC_Y2_LV5_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_Y3_LV5), (c_assDTG_FL_INC_Y3_LV5_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_Y4_LV5), (c_assDTG_FL_INC_Y4_LV5_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_X1_LV5), (c_assDTG_FL_INC_X1_LV5_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_X2_LV5), (c_assDTG_FL_INC_X2_LV5_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_X3_LV5), (c_assDTG_FL_INC_X3_LV5_Limo)); + M_MEMCOPY((g_assDTG_FL_INC_X4_LV5), (c_assDTG_FL_INC_X4_LV5_Limo)); + M_MEMCOPY((g_assDTG_FL_AMB_Y1_LV5), (c_assDTG_FL_AMB_Y1_LV5_Limo)); + M_MEMCOPY((g_assDTG_FL_AMB_Y2_LV5), (c_assDTG_FL_AMB_Y2_LV5_Limo)); + M_MEMCOPY((g_assDTG_FL_AMB_X1_LV5), (c_assDTG_FL_AMB_X1_LV5_Limo)); + M_MEMCOPY((g_assDTG_FL_AMB_X2_LV5), (c_assDTG_FL_AMB_X2_LV5_Limo)); + M_MEMCOPY((g_assDTG_FL_SUN_Y1_LV5), (c_assDTG_FL_SUN_Y1_LV5_Limo)); + M_MEMCOPY((g_assDTG_FL_SUN_Y2_LV5), (c_assDTG_FL_SUN_Y2_LV5_Limo)); + M_MEMCOPY((g_assDTG_FL_SUN_X1_LV5), (c_assDTG_FL_SUN_X1_LV5_Limo)); + M_MEMCOPY((g_assDTG_FL_SUN_X2_LV5), (c_assDTG_FL_SUN_X2_LV5_Limo)); + M_MEMCOPY((g_assINCAR_TG_RL_LV5), (c_assINCAR_TG_RL_LV5_Limo)); + M_MEMCOPY((g_assINCAR_TG_RR_LV5), (c_assINCAR_TG_RR_LV5_Limo)); + M_MEMCOPY((g_assVTG_RL_LV5), (c_assVTG_RL_LV5_Limo)); + M_MEMCOPY((g_assVTG_RR_LV5), (c_assVTG_RR_LV5_Limo)); + M_MEMCOPY((g_assVR_MIN_LV5), (c_assVR_MIN_LV5_Limo)); + M_MEMCOPY((g_assVR_MAX_LV5), (c_assVR_MAX_LV5_Limo)); + M_MEMCOPY((g_assVR_INC_Y1_LV5), (c_assVR_INC_Y1_LV5_Limo)); + M_MEMCOPY((g_assVR_INC_Y2_LV5), (c_assVR_INC_Y2_LV5_Limo)); + M_MEMCOPY((g_assVR_INC_Y3_LV5), (c_assVR_INC_Y3_LV5_Limo)); + M_MEMCOPY((g_assVR_INC_Y4_LV5), (c_assVR_INC_Y4_LV5_Limo)); + M_MEMCOPY((g_assVR_INC_X1_LV5), (c_assVR_INC_X1_LV5_Limo)); + M_MEMCOPY((g_assVR_INC_X2_LV5), (c_assVR_INC_X2_LV5_Limo)); + M_MEMCOPY((g_assVR_INC_X3_LV5), (c_assVR_INC_X3_LV5_Limo)); + M_MEMCOPY((g_assVR_INC_X4_LV5), (c_assVR_INC_X4_LV5_Limo)); + M_MEMCOPY((g_assVR_AMB_Y1_LV5), (c_assVR_AMB_Y1_LV5_Limo)); + M_MEMCOPY((g_assVR_AMB_Y2_LV5), (c_assVR_AMB_Y2_LV5_Limo)); + M_MEMCOPY((g_assVR_AMB_X1_LV5), (c_assVR_AMB_X1_LV5_Limo)); + M_MEMCOPY((g_assVR_AMB_X2_LV5), (c_assVR_AMB_X2_LV5_Limo)); + M_MEMCOPY((g_assVR_SUN_Y1_LV5), (c_assVR_SUN_Y1_LV5_Limo)); + M_MEMCOPY((g_assVR_SUN_Y2_LV5), (c_assVR_SUN_Y2_LV5_Limo)); + M_MEMCOPY((g_assVR_SUN_X1_LV5), (c_assVR_SUN_X1_LV5_Limo)); + M_MEMCOPY((g_assVR_SUN_X2_LV5), (c_assVR_SUN_X2_LV5_Limo)); + M_MEMCOPY((g_assTG_RL_LV5), (c_assTG_RL_LV5_Limo)); + M_MEMCOPY((g_assTG_RR_LV5), (c_assTG_RR_LV5_Limo)); + M_MEMCOPY((g_assDTG_R_MIN_LV5), (c_assDTG_R_MIN_LV5_Limo)); + M_MEMCOPY((g_assDTG_R_MAX_LV5), (c_assDTG_R_MAX_LV5_Limo)); + M_MEMCOPY((g_assDTG_R_INC_Y1_LV5), (c_assDTG_R_INC_Y1_LV5_Limo)); + M_MEMCOPY((g_assDTG_R_INC_Y2_LV5), (c_assDTG_R_INC_Y2_LV5_Limo)); + M_MEMCOPY((g_assDTG_R_INC_Y3_LV5), (c_assDTG_R_INC_Y3_LV5_Limo)); + M_MEMCOPY((g_assDTG_R_INC_Y4_LV5), (c_assDTG_R_INC_Y4_LV5_Limo)); + M_MEMCOPY((g_assDTG_R_INC_X1_LV5), (c_assDTG_R_INC_X1_LV5_Limo)); + M_MEMCOPY((g_assDTG_R_INC_X2_LV5), (c_assDTG_R_INC_X2_LV5_Limo)); + M_MEMCOPY((g_assDTG_R_INC_X3_LV5), (c_assDTG_R_INC_X3_LV5_Limo)); + M_MEMCOPY((g_assDTG_R_INC_X4_LV5), (c_assDTG_R_INC_X4_LV5_Limo)); + M_MEMCOPY((g_assDTG_R_AMB_Y1_LV5), (c_assDTG_R_AMB_Y1_LV5_Limo)); + M_MEMCOPY((g_assDTG_R_AMB_Y2_LV5), (c_assDTG_R_AMB_Y2_LV5_Limo)); + M_MEMCOPY((g_assDTG_R_AMB_X1_LV5), (c_assDTG_R_AMB_X1_LV5_Limo)); + M_MEMCOPY((g_assDTG_R_AMB_X2_LV5), (c_assDTG_R_AMB_X2_LV5_Limo)); + M_MEMCOPY((g_assDTG_R_SUN_Y1_LV5), (c_assDTG_R_SUN_Y1_LV5_Limo)); + M_MEMCOPY((g_assDTG_R_SUN_Y2_LV5), (c_assDTG_R_SUN_Y2_LV5_Limo)); + M_MEMCOPY((g_assDTG_R_SUN_X1_LV5), (c_assDTG_R_SUN_X1_LV5_Limo)); + M_MEMCOPY((g_assDTG_R_SUN_X2_LV5), (c_assDTG_R_SUN_X2_LV5_Limo)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FR_LV5), (c_assCORRECT_DUCT_TIME_FR_LV5_Limo)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FL_LV5), (c_assCORRECT_DUCT_TIME_FL_LV5_Limo)); + M_MEMCOPY((g_assCORRECT_DUCT_RATE_LV5), (c_assCORRECT_DUCT_RATE_LV5_Limo)); + M_MEMCOPY((g_assCORRECT_DUCT_MAX_LV5), (c_assCORRECT_DUCT_MAX_LV5_Limo)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FR_LV5), (c_assCORRECT_AF_TIME_FR_LV5_Limo)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FL_LV5), (c_assCORRECT_AF_TIME_FL_LV5_Limo)); + M_MEMCOPY((g_assCORRECT_AF_RATE_LV5), (c_assCORRECT_AF_RATE_LV5_Limo)); + M_MEMCOPY((g_assCORRECT_AF_MAX_LV5), (c_assCORRECT_AF_MAX_LV5_Limo)); +/* ------------------------------------------Lv5 : End*/ + M_MEMCOPY((g_assDUCT_TGT_DEF_VALVE_L), (c_assDUCT_TGT_DEF_VALVE_L_Limo)); + M_MEMCOPY((g_assDUCT_TGT_DEF_VALVE_R), (c_assDUCT_TGT_DEF_VALVE_R_Limo)); +/* ------------------------------------------DuctTgt Increase : End*/ + M_MEMCOPY((g_assAMB_LV_UP), (c_assAMB_LV_UP_Limo)); + M_MEMCOPY((g_assAMB_LV_DN), (c_assAMB_LV_DN_Limo)); + M_MEMCOPY((g_assAMB_LV_TG), (c_assAMB_LV_TG_Limo)); +/* ------------------------------------------Ambient LEVEL : End*/ + M_MEMCOPY((g_aucMODE_BY_SET_F_LV0), (c_aucMODE_BY_SET_F_LV0_Limo)); + M_MEMCOPY((g_aucMODE_BY_SET_F_LV1), (c_aucMODE_BY_SET_F_LV1_Limo)); + M_MEMCOPY((g_aucMODE_BY_SET_F_LV2), (c_aucMODE_BY_SET_F_LV2_Limo)); + M_MEMCOPY((g_aucMODE_BY_SET_F_LV3), (c_aucMODE_BY_SET_F_LV3_Limo)); + M_MEMCOPY((g_aucMODE_BY_SET_F_LV4), (c_aucMODE_BY_SET_F_LV4_Limo)); + M_MEMCOPY((g_aucMODE_BY_SET_F_LV5), (c_aucMODE_BY_SET_F_LV5_Limo)); + M_MEMCOPY((g_ausMODE_BY_DUCT_TG_R_LV0), (c_ausMODE_BY_DUCT_TG_R_LV0_Limo)); + M_MEMCOPY((g_ausMODE_BY_DUCT_TG_R_LV1), (c_ausMODE_BY_DUCT_TG_R_LV1_Limo)); + M_MEMCOPY((g_ausMODE_BY_DUCT_TG_R_LV2), (c_ausMODE_BY_DUCT_TG_R_LV2_Limo)); + M_MEMCOPY((g_ausMODE_BY_DUCT_TG_R_LV3), (c_ausMODE_BY_DUCT_TG_R_LV3_Limo)); + M_MEMCOPY((g_ausMODE_BY_DUCT_TG_R_LV4), (c_ausMODE_BY_DUCT_TG_R_LV4_Limo)); + M_MEMCOPY((g_ausMODE_BY_DUCT_TG_R_LV5), (c_ausMODE_BY_DUCT_TG_R_LV5_Limo)); +/* ------------------------------------------Mode depend on SET for each level : End*/ + g_ssPREC_REC_ON_AMB = c_ssPREC_REC_ON_AMB_Limo; + g_ssPREC_REC_OFF_AMB = c_ssPREC_REC_OFF_AMB_Limo; + M_MEMCOPY((g_aucPREC_VEH_SPD_OSA), (c_aucPREC_VEH_SPD_OSA_Limo)); + M_MEMCOPY((g_assPRE_AMB_RANGE_WINTER), (c_assPRE_AMB_RANGE_WINTER_Limo)); + M_MEMCOPY((g_aucPREC_OSA_WINTER), (c_aucPREC_OSA_WINTER_Limo)); + M_MEMCOPY((g_aucPREC_REC_WINTER), (c_aucPREC_REC_WINTER_Limo)); + M_MEMCOPY((g_ausPREC_HUMIDITY_NOK), (c_ausPREC_HUMIDITY_NOK_Limo)); + M_MEMCOPY((g_ausPREC_HUMIDITY_OK), (c_ausPREC_HUMIDITY_OK_Limo)); + M_MEMCOPY((g_ausPREC_ENTRY_RPM), (c_ausPREC_ENTRY_RPM_Limo)); + M_MEMCOPY((g_ausPREC_EXIT_RPM), (c_ausPREC_EXIT_RPM_Limo)); + M_MEMCOPY((g_ausPREC_COMP_SPD_1), (c_ausPREC_COMP_SPD_1_Limo)); + M_MEMCOPY((g_aucPREC_OSA_SUMMER_1), (c_aucPREC_OSA_SUMMER_1_Limo)); + M_MEMCOPY((g_aucPREC_REC_SUMMER_1), (c_aucPREC_REC_SUMMER_1_Limo)); + M_MEMCOPY((g_assPREC_EVA_DIFF_FB_TG_F), (c_assPREC_EVA_DIFF_FB_TG_F_Limo)); + M_MEMCOPY((g_aucPREC_OSA_SUMMER_2), (c_aucPREC_OSA_SUMMER_2_Limo)); + M_MEMCOPY((g_aucPREC_REC_SUMMER_2), (c_aucPREC_REC_SUMMER_2_Limo)); + M_MEMCOPY((g_aucPREC_EVA_DIFF), (c_aucPREC_EVA_DIFF_Limo)); + g_ucPREC_OSA_SUMMER_3 = c_ucPREC_OSA_SUMMER_3_Limo; + g_ucPREC_REC_SUMMER_3 = c_ucPREC_REC_SUMMER_3_Limo; +/* ------------------------------------------AutoRec : End*/ + M_MEMCOPY((g_ausFLOW_FR_VE2VALVE), (c_ausFLOW_FR_VE2VALVE_Limo)); + M_MEMCOPY((g_ausFLOW_FR_BIVALVE), (c_ausFLOW_FR_BIVALVE_Limo)); + M_MEMCOPY((g_ausFLOW_FR_BI2VALVE), (c_ausFLOW_FR_BI2VALVE_Limo)); + M_MEMCOPY((g_ausFLOW_FR_AF2VALVE), (c_ausFLOW_FR_AF2VALVE_Limo)); + M_MEMCOPY((g_ausFLOW_FR_AF2VALVE_SUMMER), (c_ausFLOW_FR_AF2VALVE_SUMMER_Limo)); + M_MEMCOPY((g_ausFLOW_FR_FO2VALVE), (c_ausFLOW_FR_FO2VALVE_Limo)); + M_MEMCOPY((g_ausFLOW_FR_FD2VALVE), (c_ausFLOW_FR_FD2VALVE_Limo)); + M_MEMCOPY((g_ausFLOW_FR_DE2VALVE), (c_ausFLOW_FR_DE2VALVE_Limo)); + M_MEMCOPY((g_ausFLOW_FR_TR2VALVE), (c_ausFLOW_FR_TR2VALVE_Limo)); + M_MEMCOPY((g_ausFLOW_FR_HI2VALVE), (c_ausFLOW_FR_HI2VALVE_Limo)); + M_MEMCOPY((g_ausFLOW_FR_BIVALVE_MANUAL), (c_ausFLOW_FR_BIVALVE_MANUAL_Limo)); + M_MEMCOPY((g_ausFLOW_RE_VENT), (c_ausFLOW_RE_VENT_Limo)); + M_MEMCOPY((g_ausFLOW_RE_BI2VALVE), (c_ausFLOW_RE_BI2VALVE_Limo)); + M_MEMCOPY((g_ausFLOW_RE_FO2VALVE), (c_ausFLOW_RE_FO2VALVE_Limo)); + M_MEMCOPY((g_ausFLOW_RE_VENT_2), (c_ausFLOW_RE_VENT_2_Limo)); + M_MEMCOPY((g_ausFLOW_RE_BI2VALVE_2), (c_ausFLOW_RE_BI2VALVE_2_Limo)); + M_MEMCOPY((g_ausFLOW_RE_VENT_3), (c_ausFLOW_RE_VENT_3_Limo)); + M_MEMCOPY((g_ausFLOW_RE_BI2VALVE_3), (c_ausFLOW_RE_BI2VALVE_3_Limo)); + M_MEMCOPY((g_ausFLOW_RE_VENT_MANUAL), (c_ausFLOW_RE_VENT_MANUAL_Limo)); + M_MEMCOPY((g_ausFLOW_RE_BI2VALVE_MANUAL), (c_ausFLOW_RE_BI2VALVE_MANUAL_Limo)); +/* ------------------------------------------Flow Control Valve: End*/ + M_MEMCOPY((g_assFLOW_BI_AMB_TGT), (c_assFLOW_BI_AMB_TGT_Limo)); + M_MEMCOPY((g_aucFLOW_BI_VENT_PLUS), (c_aucFLOW_BI_VENT_PLUS_Limo)); + M_MEMCOPY((g_assFLOW_BI_TEMP_TGT), (c_assFLOW_BI_TEMP_TGT_Limo)); + M_MEMCOPY((g_aucFLOW_BI_FOOT_PLUS), (c_aucFLOW_BI_FOOT_PLUS_Limo)); + M_MEMCOPY((g_aucFLOW_BI_VENT_VALVE_MAX), (c_aucFLOW_BI_VENT_VALVE_MAX_Limo)); + M_MEMCOPY((g_aucFLOW_BI_FOOT_VALVE_MAX), (c_aucFLOW_BI_FOOT_VALVE_MAX_Limo)); + M_MEMCOPY((g_aucFLOW_BI_VENT_VALVE_MIN), (c_aucFLOW_BI_VENT_VALVE_MIN_Limo)); + M_MEMCOPY((g_aucFLOW_BI_FOOT_VALVE_MIN), (c_aucFLOW_BI_FOOT_VALVE_MIN_Limo)); +/* ------------------------------------------Bi 2 level conditions: End*/ + M_MEMCOPY((g_assFLOW_B2I_AMB_TGT), (c_assFLOW_B2I_AMB_TGT_Limo)); + M_MEMCOPY((g_aucFLOW_BI2_VENT_PLUS), (c_aucFLOW_BI2_VENT_PLUS_Limo)); + M_MEMCOPY((g_assFLOW_BI2_TEMP_TGT), (c_assFLOW_BI2_TEMP_TGT_Limo)); + M_MEMCOPY((g_aucFLOW_BI2_FOOT_PLUS), (c_aucFLOW_BI2_FOOT_PLUS_Limo)); + M_MEMCOPY((g_aucFLOW_BI2_VENT_VALVE_MAX), (c_aucFLOW_BI2_VENT_VALVE_MAX_Limo)); + M_MEMCOPY((g_aucFLOW_BI2_FOOT_VALVE_MAX), (c_aucFLOW_BI2_FOOT_VALVE_MAX_Limo)); + M_MEMCOPY((g_aucFLOW_BI2_VENT_VALVE_MIN), (c_aucFLOW_BI2_VENT_VALVE_MIN_Limo)); + M_MEMCOPY((g_aucFLOW_BI2_FOOT_VALVE_MIN), (c_aucFLOW_BI2_FOOT_VALVE_MIN_Limo)); +/* ------------------------------------------AF level conditions: End*/ + M_MEMCOPY((g_assFLOW_AF_AMB_TGT), (c_assFLOW_AF_AMB_TGT_Limo)); + M_MEMCOPY((g_aucFLOW_AF_VENT_PLUS), (c_aucFLOW_AF_VENT_PLUS_Limo)); + M_MEMCOPY((g_aucFLOW_AF_BLR_AF_TGT), (c_aucFLOW_AF_BLR_AF_TGT_Limo)); + M_MEMCOPY((g_aucFLOW_AF_FOOT_PLUS), (c_aucFLOW_AF_FOOT_PLUS_Limo)); + M_MEMCOPY((g_aucFLOW_AF_VENT_VALVE_MAX), (c_aucFLOW_AF_VENT_VALVE_MAX_Limo)); + M_MEMCOPY((g_aucFLOW_AF_FOOT_VALVE_MAX), (c_aucFLOW_AF_FOOT_VALVE_MAX_Limo)); +/* ------------------------------------------AF level conditions: End*/ + M_MEMCOPY((g_assFLOW_AFSM_AMB_TGT), (c_assFLOW_AFSM_AMB_TGT_Limo)); + M_MEMCOPY((g_aucFLOW_AFSM_VENT_PLUS), (c_aucFLOW_AFSM_VENT_PLUS_Limo)); + M_MEMCOPY((g_assFLOW_AFSM_TEMP_TGT), (c_assFLOW_AFSM_TEMP_TGT_Limo)); + M_MEMCOPY((g_aucFLOW_AFSM_FOOT_PLUS), (c_aucFLOW_AFSM_FOOT_PLUS_Limo)); + M_MEMCOPY((g_aucFLOW_AFSM_VENT_VALVE_MAX), (c_aucFLOW_AFSM_VENT_VALVE_MAX_Limo)); + M_MEMCOPY((g_aucFLOW_AFSM_FOOT_VALVE_MAX), (c_aucFLOW_AFSM_FOOT_VALVE_MAX_Limo)); +/* ------------------------------------------AF_summer level conditions: End*/ + M_MEMCOPY((g_aucMODE_INDEX), (c_aucMODE_INDEX_Limo)); + M_MEMCOPY((g_assFOOT_STEP_DUCT_TGT), (c_assFOOT_STEP_DUCT_TGT_Limo)); + M_MEMCOPY((g_assBLR_FOOT_IND), (c_assBLR_FOOT_IND_Limo)); + M_MEMCOPY((g_ascFOOT_STEP_VALVE_P1), (c_ascFOOT_STEP_VALVE_P1_Limo)); + M_MEMCOPY((g_ascFOOT_STEP_VALVE_P2), (c_ascFOOT_STEP_VALVE_P2_Limo)); + M_MEMCOPY((g_ascFOOT_STEP_VALVE_P3), (c_ascFOOT_STEP_VALVE_P3_Limo)); + M_MEMCOPY((g_ascFOOT_STEP_VALVE_M1), (c_ascFOOT_STEP_VALVE_M1_Limo)); + M_MEMCOPY((g_ascFOOT_STEP_VALVE_M2), (c_ascFOOT_STEP_VALVE_M2_Limo)); + M_MEMCOPY((g_ascFOOT_STEP_VALVE_M3), (c_ascFOOT_STEP_VALVE_M3_Limo)); + M_MEMCOPY((g_assFOOT_STEP_BLR_P1), (c_assFOOT_STEP_BLR_P1_Limo)); + M_MEMCOPY((g_assFOOT_STEP_BLR_P2), (c_assFOOT_STEP_BLR_P2_Limo)); + M_MEMCOPY((g_assFOOT_STEP_BLR_P3), (c_assFOOT_STEP_BLR_P3_Limo)); + M_MEMCOPY((g_assFOOT_STEP_BLR_M1), (c_assFOOT_STEP_BLR_M1_Limo)); + M_MEMCOPY((g_assFOOT_STEP_BLR_M2), (c_assFOOT_STEP_BLR_M2_Limo)); + M_MEMCOPY((g_assFOOT_STEP_BLR_M3), (c_assFOOT_STEP_BLR_M3_Limo)); +/* ------------------------------------------Individual foot temperature: End*/ + M_MEMCOPY((g_aucREAR_FOOT_VALVE_AMB_LV2), (c_aucREAR_FOOT_VALVE_AMB_LV2_Limo)); + M_MEMCOPY((g_aucREAR_FOOT_VALVE_AMB_LV3), (c_aucREAR_FOOT_VALVE_AMB_LV3_Limo)); + M_MEMCOPY((g_aucREAR_FOOT_VALVE_AMB_LV4), (c_aucREAR_FOOT_VALVE_AMB_LV4_Limo)); +/* ------------------------------------------Blowing foots from Rear HVAC: End*/ + M_MEMCOPY((g_ausFLOW_FR_VE2BLR_AF), (c_ausFLOW_FR_VE2BLR_AF_Limo)); + M_MEMCOPY((g_ausFLOW_FR_BIVALVE_AF), (c_ausFLOW_FR_BIVALVE_AF_Limo)); + M_MEMCOPY((g_ausFLOW_FR_BI2BLR_AF), (c_ausFLOW_FR_BI2BLR_AF_Limo)); + M_MEMCOPY((g_ausFLOW_FR_FO2BLR_AF), (c_ausFLOW_FR_FO2BLR_AF_Limo)); + M_MEMCOPY((g_ausFLOW_FR_AF2VALVE_AF), (c_ausFLOW_FR_AF2VALVE_AF_Limo)); + M_MEMCOPY((g_ausFLOW_FR_AF2VALVE_SUMMER_AF), (c_ausFLOW_FR_AF2VALVE_SUMMER_AF_Limo)); + M_MEMCOPY((g_ausFLOW_FR_FD2BLR_AF), (c_ausFLOW_FR_FD2BLR_AF_Limo)); + M_MEMCOPY((g_ausFLOW_FR_DE2BLR_AF), (c_ausFLOW_FR_DE2BLR_AF_Limo)); + M_MEMCOPY((g_ausFLOW_FR_TR2BLR_AF), (c_ausFLOW_FR_TR2BLR_AF_Limo)); + M_MEMCOPY((g_ausFLOW_FR_HI2BLR_AF), (c_ausFLOW_FR_HI2BLR_AF_Limo)); + M_MEMCOPY((g_ausFLOW_RE_VE2BLR_AF), (c_ausFLOW_RE_VE2BLR_AF_Limo)); + M_MEMCOPY((g_ausFLOW_RE_BI2BLR_AF), (c_ausFLOW_RE_BI2BLR_AF_Limo)); + M_MEMCOPY((g_ausFLOW_RE_FO2BLR_AF), (c_ausFLOW_RE_FO2BLR_AF_Limo)); +/* ------------------------------------------Flow Control AF: End*/ + M_MEMCOPY((g_ascAUTO_STEP_AF_F), (c_ascAUTO_STEP_AF_F_Limo)); + M_MEMCOPY((g_ascAUTO_STEP_AF_R), (c_ascAUTO_STEP_AF_R_Limo)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_U_F_LV0_1), (c_assAUTO_STEP_DUCT_TG_U_F_LV0_1_Limo)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_U_F_LV2_3), (c_assAUTO_STEP_DUCT_TG_U_F_LV2_3_Limo)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_U_F_LV4_5), (c_assAUTO_STEP_DUCT_TG_U_F_LV4_5_Limo)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_L_F_LV0_1), (c_assAUTO_STEP_DUCT_TG_L_F_LV0_1_Limo)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_L_F_LV2_3), (c_assAUTO_STEP_DUCT_TG_L_F_LV2_3_Limo)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_L_F_LV4_5), (c_assAUTO_STEP_DUCT_TG_L_F_LV4_5_Limo)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_R_LV0_1), (c_assAUTO_STEP_DUCT_TG_R_LV0_1_Limo)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_R_LV2_3), (c_assAUTO_STEP_DUCT_TG_R_LV2_3_Limo)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_R_LV4_5), (c_assAUTO_STEP_DUCT_TG_R_LV4_5_Limo)); +/* ------------------------------------------5 AUTO mode: End*/ + M_MEMCOPY((g_ausVALVE_SPACE), (c_ausVALVE_SPACE_Limo)); + M_MEMCOPY((g_aucVALVE_SECTION_S1_F_SIDE_VENT), (c_aucVALVE_SECTION_S1_F_SIDE_VENT_Limo)); + M_MEMCOPY((g_aucVALVE_SECTION_S1_F_CENT_VENT), (c_aucVALVE_SECTION_S1_F_CENT_VENT_Limo)); + M_MEMCOPY((g_aucVALVE_SECTION_S1_F_DRIVER_FOOT), (c_aucVALVE_SECTION_S1_F_DRIVER_FOOT_Limo)); + M_MEMCOPY((g_aucVALVE_SECTION_S1_F_RIGHT_PASS), (c_aucVALVE_SECTION_S1_F_RIGHT_PASS_Limo)); + M_MEMCOPY((g_aucBLR_SPD_V1_1_F), (c_aucBLR_SPD_V1_1_F_Limo)); + M_MEMCOPY((g_aucBLR_SPD_K2_1_F_SIDE_VENT), (c_aucBLR_SPD_K2_1_F_SIDE_VENT_Limo)); + M_MEMCOPY((g_aucBLR_SPD_K2_2_F_CENT_VENT), (c_aucBLR_SPD_K2_2_F_CENT_VENT_Limo)); + M_MEMCOPY((g_aucBLR_SPD_K2_3_F_DRIVER_FOOT), (c_aucBLR_SPD_K2_3_F_DRIVER_FOOT_Limo)); + M_MEMCOPY((g_aucBLR_SPD_K2_4_F_RIGHT_PASS), (c_aucBLR_SPD_K2_4_F_RIGHT_PASS_Limo)); + M_MEMCOPY((g_ausVALVE_VEH_SPD), (c_ausVALVE_VEH_SPD_Limo)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_SIDE_VENT), (c_aucVALVE_VEH_SPD_SIDE_VENT_Limo)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_SIDE_BI), (c_aucVALVE_VEH_SPD_SIDE_BI_Limo)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_SIDE_AFOOT), (c_aucVALVE_VEH_SPD_SIDE_AFOOT_Limo)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_CNET_VENT), (c_aucVALVE_VEH_SPD_CNET_VENT_Limo)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_CENT_BI), (c_aucVALVE_VEH_SPD_CENT_BI_Limo)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_CENT_AFOOT), (c_aucVALVE_VEH_SPD_CENT_AFOOT_Limo)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_FOOT_BI), (c_aucVALVE_VEH_SPD_FOOT_BI_Limo)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_FOOT_AFOOT), (c_aucVALVE_VEH_SPD_FOOT_AFOOT_Limo)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_2FOOT), (c_aucVALVE_VEH_SPD_2FOOT_Limo)); + M_MEMCOPY((g_aucBLR_SPD_VEH_SPD_V1_3), (c_aucBLR_SPD_VEH_SPD_V1_3_Limo)); + M_MEMCOPY((g_aucFRONT_SIDE_DRS_PERCENT), (c_aucFRONT_SIDE_DRS_PERCENT_Limo)); + M_MEMCOPY((g_aucFRONT_CENT_DRS_PERCENT), (c_aucFRONT_CENT_DRS_PERCENT_Limo)); +/* ------------------------------------------Different blower speed FRONT MODE: End*/ + M_MEMCOPY((g_aucVALVE_S1_R_BIPILLAR), (c_aucVALVE_S1_R_BIPILLAR_Limo)); + M_MEMCOPY((g_aucVALVE_S1_R_CENT_VENT), (c_aucVALVE_S1_R_CENT_VENT_Limo)); + M_MEMCOPY((g_aucVALVE_S1_R_FOOT), (c_aucVALVE_S1_R_FOOT_Limo)); + M_MEMCOPY((g_aucVALVE_PERC_R_BIPILLAR), (c_aucVALVE_PERC_R_BIPILLAR_Limo)); + M_MEMCOPY((g_aucVALVE_PERC_R_CENT_VENT), (c_aucVALVE_PERC_R_CENT_VENT_Limo)); + M_MEMCOPY((g_aucVALVE_PERC_R_FOOT), (c_aucVALVE_PERC_R_FOOT_Limo)); + M_MEMCOPY((g_aucBLR_SPD_V1_1_R), (c_aucBLR_SPD_V1_1_R_Limo)); + M_MEMCOPY((g_aucREAR_CEN_MIN_VALUE_BY_DRS_ZERO), (c_aucREAR_CEN_MIN_VALUE_BY_DRS_ZERO_Limo)); + M_MEMCOPY((g_aucBLR_SPD_K2_1_R_BIPILLAR_MIN), (c_aucBLR_SPD_K2_1_R_BIPILLAR_MIN_Limo)); + M_MEMCOPY((g_aucBLR_SPD_K2_2_R_CENT_VENT_MIN), (c_aucBLR_SPD_K2_2_R_CENT_VENT_MIN_Limo)); + M_MEMCOPY((g_aucBLR_SPD_K2_3_R_FOOT_MIN), (c_aucBLR_SPD_K2_3_R_FOOT_MIN_Limo)); + M_MEMCOPY((g_aucBLR_SPD_K2_1_R_BIPILLAR_MAX), (c_aucBLR_SPD_K2_1_R_BIPILLAR_MAX_Limo)); + M_MEMCOPY((g_aucBLR_SPD_K2_2_R_CENT_VENTR_MAX), (c_aucBLR_SPD_K2_2_R_CENT_VENTR_MAX_Limo)); + M_MEMCOPY((g_aucBLR_SPD_K2_3_R_FOOTR_MAX), (c_aucBLR_SPD_K2_3_R_FOOTR_MAX_Limo)); + M_MEMCOPY((g_aucREAR_SIDE_DRS_PERCENT_VALVE), (c_aucREAR_SIDE_DRS_PERCENT_VALVE_Limo)); + M_MEMCOPY((g_aucREAR_CENT_DRS_PERCENT_VALVE), (c_aucREAR_CENT_DRS_PERCENT_VALVE_Limo)); + M_MEMCOPY((g_aucREAR_SIDE_DRS_PERCENT_AF), (c_aucREAR_SIDE_DRS_PERCENT_AF_Limo)); + M_MEMCOPY((g_aucREAR_CENT_DRS_PERCENT_AF), (c_aucREAR_CENT_DRS_PERCENT_AF_Limo)); +/* ------------------------------------------Different blower speed REAR MODE: End*/ + M_MEMCOPY((g_ausMIN_PWM), (c_ausMIN_PWM_Limo)); +/* ------------------------------------------MinPWM: End*/ + M_MEMCOPY((g_assSTART_ENTER_COOLANT), (c_assSTART_ENTER_COOLANT_Limo)); + M_MEMCOPY((g_assSTART_COOLANT_STEP0_TO_1), (c_assSTART_COOLANT_STEP0_TO_1_Limo)); + M_MEMCOPY((g_assSTART_COOLANT_TO_STEP2), (c_assSTART_COOLANT_TO_STEP2_Limo)); + M_MEMCOPY((g_assSTART_COOLANT_STEP1_BLR_F), (c_assSTART_COOLANT_STEP1_BLR_F_Limo)); + M_MEMCOPY((g_assSTART_COOLANT_STEP1_BLR_R), (c_assSTART_COOLANT_STEP1_BLR_R_Limo)); + M_MEMCOPY((g_assSTART_ENTER_INCAR), (c_assSTART_ENTER_INCAR_Limo)); + M_MEMCOPY((g_ausSTART_ENTER_SETTEMP), (c_ausSTART_ENTER_SETTEMP_Limo)); + M_MEMCOPY((g_aucSTART_INCAR_FLT_UP), (c_aucSTART_INCAR_FLT_UP_Limo)); + M_MEMCOPY((g_aucSTART_INCAR_FLT_DN), (c_aucSTART_INCAR_FLT_DN_Limo)); + M_MEMCOPY((g_aucSTART_VALVE_IDX_STEP1), (c_aucSTART_VALVE_IDX_STEP1_Limo)); + M_MEMCOPY((g_aucSTART_AUTODEMIST2_STEP2), (c_aucSTART_AUTODEMIST2_STEP2_Limo)); + M_MEMCOPY((g_aucSTART_ELEC_WINDOW), (c_aucSTART_ELEC_WINDOW_Limo)); + M_MEMCOPY((g_ausSTART_BLR_AF_STEP12_F), (c_ausSTART_BLR_AF_STEP12_F_Limo)); + M_MEMCOPY((g_ausSTART_BLR_AF_STEP12_R), (c_ausSTART_BLR_AF_STEP12_R_Limo)); + M_MEMCOPY((g_ausSTART_BLR_SPD_STEP2_F), (c_ausSTART_BLR_SPD_STEP2_F_Limo)); + M_MEMCOPY((g_ausSTART_BLR_SPD_STEP2_R), (c_ausSTART_BLR_SPD_STEP2_R_Limo)); + M_MEMCOPY((g_aucSTART_DUCT_TGT_STEP2_FX_U), (c_aucSTART_DUCT_TGT_STEP2_FX_U_Limo)); + M_MEMCOPY((g_aucSTART_DUCT_TGT_STEP2_FX_L), (c_aucSTART_DUCT_TGT_STEP2_FX_L_Limo)); + M_MEMCOPY((g_aucSTART_DUCT_TGT_STEP2_RX), (c_aucSTART_DUCT_TGT_STEP2_RX_Limo)); + M_MEMCOPY((g_aucSTART_VALVE_CHANGE_SPD_F), (c_aucSTART_VALVE_CHANGE_SPD_F_Limo)); + M_MEMCOPY((g_aucSTART_VALVE_CHANGE_SPD_R), (c_aucSTART_VALVE_CHANGE_SPD_R_Limo)); + M_MEMCOPY((g_ausSTART_TIME_STEP1_TO_2), (c_ausSTART_TIME_STEP1_TO_2_Limo)); + M_MEMCOPY((g_ausSTART_TIME_STEP2_TO_3), (c_ausSTART_TIME_STEP2_TO_3_Limo)); + M_MEMCOPY((g_assSTART_INCAR_STEP1_TO_2), (c_assSTART_INCAR_STEP1_TO_2_Limo)); + M_MEMCOPY((g_assSTART_INCAR_STEP2_TO_3), (c_assSTART_INCAR_STEP2_TO_3_Limo)); + M_MEMCOPY((g_aucSTART_3WAY_OPEN), (c_aucSTART_3WAY_OPEN_Limo)); + M_MEMCOPY((g_aucSTART_2WAY_OPEN), (c_aucSTART_2WAY_OPEN_Limo)); + M_MEMCOPY((g_aucSTART_TXV_F), (c_aucSTART_TXV_F_Limo)); + M_MEMCOPY((g_aucSTART_TXV_R), (c_aucSTART_TXV_R_Limo)); +/* ------------------------------------------Start control: End*/ + M_MEMCOPY((g_assFAILURE_AMB_TEMP), (c_assFAILURE_AMB_TEMP_Limo)); + M_MEMCOPY((g_assAC_PRESSURE_LOW_HYS_UP), (c_assAC_PRESSURE_LOW_HYS_UP_Limo)); + M_MEMCOPY((g_assAC_PRESSURE_LOW_HYS_DN), (c_assAC_PRESSURE_LOW_HYS_DN_Limo)); + M_MEMCOPY((g_assAC_LOW_AMB_F), (c_assAC_LOW_AMB_F_Limo)); + M_MEMCOPY((g_assAC_CUT_OFF_AMB_F), (c_assAC_CUT_OFF_AMB_F_Limo)); + M_MEMCOPY((g_assAC_WINTER_TXV_DEWPOINT), (c_assAC_WINTER_TXV_DEWPOINT_Limo)); + M_MEMCOPY((g_assAC_CUT_OFF_AMB_R), (c_assAC_CUT_OFF_AMB_R_Limo)); + M_MEMCOPY((g_assEVA_TG_AMB_F), (c_assEVA_TG_AMB_F_Limo)); + M_MEMCOPY((g_assEVA_TG_AMB_R), (c_assEVA_TG_AMB_R_Limo)); + g_ucAC_EXTRA_RPM = c_ucAC_EXTRA_RPM_Limo; + M_MEMCOPY((g_assAC_EVA_LV_SHUT_OFF), (c_assAC_EVA_LV_SHUT_OFF_Limo)); + M_MEMCOPY((g_assAC_PRESSURE_HYS_HI_ENG_ON), (c_assAC_PRESSURE_HYS_HI_ENG_ON_Limo)); + g_usCMP_MAX_ENG_OFF = c_usCMP_MAX_ENG_OFF_Limo; + g_ucFAN_MAX_ENG_OFF = c_ucFAN_MAX_ENG_OFF_Limo; + g_ssAC_WINTER_TXV_HYST = c_ssAC_WINTER_TXV_HYST_Limo; + M_MEMCOPY((g_aucAC_PRESSURE_HYS_HI_ENG_OFF), (c_aucAC_PRESSURE_HYS_HI_ENG_OFF_Limo)); + M_MEMCOPY((g_ausCMP_RPM_RESONANCE), (c_ausCMP_RPM_RESONANCE_Limo)); +/* ------------------------------------------A/C Control Pressure : End*/ + M_MEMCOPY((g_assPRESSURE_TO_FAN_X), (c_assPRESSURE_TO_FAN_X_Limo)); + M_MEMCOPY((g_aucPRESSURE_TO_FAN_Y), (c_aucPRESSURE_TO_FAN_Y_Limo)); +/* ------------------------------------------CoolingFan: End*/ + g_ssREST_BATT = c_ssREST_BATT_Limo; + g_ssRESTW_AMB = c_ssRESTW_AMB_Limo; + M_MEMCOPY((g_assRESTW_WATER), (c_assRESTW_WATER_Limo)); + g_usRESTW_READYEXPIRETIME = c_usRESTW_READYEXPIRETIME_Limo; + M_MEMCOPY((g_aucRESTW_MODE), (c_aucRESTW_MODE_Limo)); + g_usRESTW_TIMEOUTTIME = c_usRESTW_TIMEOUTTIME_Limo; + g_ucRESTW_BLRSTEP = c_ucRESTW_BLRSTEP_Limo; + g_ssRESTS_AMB = c_ssRESTS_AMB_Limo; + g_uctRESTS_READYEXPIRETIME = c_uctRESTS_READYEXPIRETIME_Limo; + M_MEMCOPY((g_aucRESTS_MODE), (c_aucRESTS_MODE_Limo)); + g_usRESTS_TIMEOUTTIME = c_usRESTS_TIMEOUTTIME_Limo; + g_ucRESTS_BLRSTEP = c_ucRESTS_BLRSTEP_Limo; +/* ------------------------------------------Rest mode: End*/ + g_usFRESH_AIR_PURGE_ENTRY_TIME = c_usFRESH_AIR_PURGE_ENTRY_TIME_Limo; + M_MEMCOPY((g_ausFRESH_AIR_PURGE_CHANGE_TIME), (c_ausFRESH_AIR_PURGE_CHANGE_TIME_Limo)); +/* ------------------------------------------Purge Rec: End*/ + M_MEMCOPY((g_assMAX_DEF_U_DTG), (c_assMAX_DEF_U_DTG_Limo)); + M_MEMCOPY((g_ausMAX_BLR_SPD), (c_ausMAX_BLR_SPD_Limo)); +/* ------------------------------------------MAX DEF: End*/ + M_MEMCOPY((g_aucAQS_REC_LV_CO), (c_aucAQS_REC_LV_CO_Limo)); + M_MEMCOPY((g_aucAQS_OSA_LV_CO), (c_aucAQS_OSA_LV_CO_Limo)); + M_MEMCOPY((g_aucAQS_REC_LV_NOX), (c_aucAQS_REC_LV_NOX_Limo)); + M_MEMCOPY((g_aucAQS_OSA_LV_NOX), (c_aucAQS_OSA_LV_NOX_Limo)); + M_MEMCOPY((g_aucAQS_REC_LV_NH3), (c_aucAQS_REC_LV_NH3_Limo)); + M_MEMCOPY((g_aucAQS_OSA_LV_NH3), (c_aucAQS_OSA_LV_NH3_Limo)); + g_ucAQS_REC_ON_TIME = c_ucAQS_REC_ON_TIME_Limo; + M_MEMCOPY((g_aucAQS_REC_ON_WAIT), (c_aucAQS_REC_ON_WAIT_Limo)); +/* ------------------------------------------Aqs: End*/ + g_usAUTODEMIST_LV2_BLR_PLUS = c_usAUTODEMIST_LV2_BLR_PLUS_Limo; + g_usAUTODEMIST_LV3_BLR_PLUS = c_usAUTODEMIST_LV3_BLR_PLUS_Limo; + M_MEMCOPY((g_assAUTODEMIST_OFFSET_AMB_TEMP), (c_assAUTODEMIST_OFFSET_AMB_TEMP_Limo)); + M_MEMCOPY((g_assAUTODEMIST_OFFSET_VENT_TEMP), (c_assAUTODEMIST_OFFSET_VENT_TEMP_Limo)); + M_MEMCOPY((g_assAUTODEMIST_STEP_UP), (c_assAUTODEMIST_STEP_UP_Limo)); + M_MEMCOPY((g_assAUTODEMIST_STEP_DN), (c_assAUTODEMIST_STEP_DN_Limo)); + M_MEMCOPY((g_assAUTODEMIST_WINTER), (c_assAUTODEMIST_WINTER_Limo)); +/* ------------------------------------------Auto Demist: End*/ + g_ssAUTODEMIST_ELEC_AMB_ENTRY = c_ssAUTODEMIST_ELEC_AMB_ENTRY_Limo; + M_MEMCOPY((g_assAUTODEMIST_ELEC_WINDSHELD_TEMP), (c_assAUTODEMIST_ELEC_WINDSHELD_TEMP_Limo)); +/* ------------------------------------------Electric AutoDemist: End*/ + g_ssAMBFILT_WATER = c_ssAMBFILT_WATER_Limo; + M_MEMCOPY((g_aucAMBFILT_H_CNT), (c_aucAMBFILT_H_CNT_Limo)); + g_ssAMB_FAILSAFE = c_ssAMB_FAILSAFE_Limo; + g_ssAMBKEEP_KAT = c_ssAMBKEEP_KAT_Limo; + g_ssAMBKEEP_KAT_PLUS = c_ssAMBKEEP_KAT_PLUS_Limo; + g_ssAMBKEEP_WATER = c_ssAMBKEEP_WATER_Limo; + M_MEMCOPY((g_aucAMBRATE_RISING), (c_aucAMBRATE_RISING_Limo)); + M_MEMCOPY((g_aucAMBRATE_FALLING), (c_aucAMBRATE_FALLING_Limo)); + M_MEMCOPY((g_aucAMBRATE_RISING_DIFF), (c_aucAMBRATE_RISING_DIFF_Limo)); + M_MEMCOPY((g_aucAMBRATE_FALLING_DIFF), (c_aucAMBRATE_FALLING_DIFF_Limo)); +/* ------------------------------------------Ambient: End*/ + M_MEMCOPY((g_ausINCARRATE_RISING_F), (c_ausINCARRATE_RISING_F_Limo)); + M_MEMCOPY((g_ausINCARRATE_FALLING_F), (c_ausINCARRATE_FALLING_F_Limo)); + M_MEMCOPY((g_ausINCARRATE_RISING_DIFF_F), (c_ausINCARRATE_RISING_DIFF_F_Limo)); + M_MEMCOPY((g_ausINCARRATE_FALLING_DIFF_F), (c_ausINCARRATE_FALLING_DIFF_F_Limo)); + M_MEMCOPY((g_ausINCARRATE_RISING_R), (c_ausINCARRATE_RISING_R_Limo)); + M_MEMCOPY((g_ausINCARRATE_FALLING_R), (c_ausINCARRATE_FALLING_R_Limo)); + M_MEMCOPY((g_ausINCARRATE_RISING_DIFF_R), (c_ausINCARRATE_RISING_DIFF_R_Limo)); + M_MEMCOPY((g_ausINCARRATE_FALLING_DIFF_R), (c_ausINCARRATE_FALLING_DIFF_R_Limo)); +/* ------------------------------------------Incar: End*/ + M_MEMCOPY((g_ausSUNRATE_RISING), (c_ausSUNRATE_RISING_Limo)); + M_MEMCOPY((g_ausSUNRATE_FALLING), (c_ausSUNRATE_FALLING_Limo)); +/* ------------------------------------------Sun: End*/ + M_MEMCOPY((g_ausAMB_LV_CHANGE_UNIT), (c_ausAMB_LV_CHANGE_UNIT_Limo)); + M_MEMCOPY((g_aucAMB_LV_CHANGE_SEC), (c_aucAMB_LV_CHANGE_SEC_Limo)); +/* ------------------------------------------Level Chage: End*/ + g_ssTHREEWAY_WATER = c_ssTHREEWAY_WATER_Limo; + M_MEMCOPY((g_assTHREEWAY_DUCT_TGT_R), (c_assTHREEWAY_DUCT_TGT_R_Limo)); + M_MEMCOPY((g_aucTHEREEWAY_EXPIRING), (c_aucTHEREEWAY_EXPIRING_Limo)); +/* ------------------------------------------Three way: End*/ + M_MEMCOPY((g_assTWOWAY_REAR_DUCTTGT_R), (c_assTWOWAY_REAR_DUCTTGT_R_Limo)); + M_MEMCOPY((g_aucTWOWAY_EXPIRING), (c_aucTWOWAY_EXPIRING_Limo)); +/* ------------------------------------------two-way: End*/ + M_MEMCOPY((g_aucACT_HOM_SPD_FL_CH0), (c_aucACT_HOM_SPD_FL_CH0_Limo)); + M_MEMCOPY((g_aucACT_HOM_SPD_FR_CH1), (c_aucACT_HOM_SPD_FR_CH1_Limo)); + M_MEMCOPY((g_aucACT_HOM_SPD_R_CH2), (c_aucACT_HOM_SPD_R_CH2_Limo)); + M_MEMCOPY((g_aucACT_HOM_SPD_R_EX_CH2), (c_aucACT_HOM_SPD_R_EX_CH2_Limo)); + M_MEMCOPY((g_aucACT_MOV_SPD_FL_CH0), (c_aucACT_MOV_SPD_FL_CH0_Limo)); + M_MEMCOPY((g_aucACT_MOV_SPD_FR_CH1), (c_aucACT_MOV_SPD_FR_CH1_Limo)); + M_MEMCOPY((g_aucACT_MOV_SPD_R_CH2), (c_aucACT_MOV_SPD_R_CH2_Limo)); + M_MEMCOPY((g_aucACT_MOV_SPD_R_EX_CH2), (c_aucACT_MOV_SPD_R_EX_CH2_Limo)); +/* ------------------------------------------Actuator Homing: End*/ + M_MEMCOPY((g_assHI_MODE_ENG_TMEP), (c_assHI_MODE_ENG_TMEP_Limo)); + M_MEMCOPY((g_aucHI_MODE_BLR_STEP_STS), (c_aucHI_MODE_BLR_STEP_STS_Limo)); +/* ------------------------------------------Hi Mode: End*/ + M_MEMCOPY((g_ausMinusAF_GlassPos_L), (c_ausMinusAF_GlassPos_L_Limo)); + M_MEMCOPY((g_ausMinusAF_GlassPos_R), (c_ausMinusAF_GlassPos_R_Limo)); +/* ------------------------------------------GlassPosition: End*/ + M_MEMCOPY((g_assFoot2_Lv3_Amb), (c_assFoot2_Lv3_Amb_Limo)); + M_MEMCOPY((g_assFoot2_Lv4_Amb), (c_assFoot2_Lv4_Amb_Limo)); + M_MEMCOPY((g_assFoot2_Lv5_Amb), (c_assFoot2_Lv5_Amb_Limo)); + M_MEMCOPY((g_assFoot2_Lv3_DuctTgt_Plus), (c_assFoot2_Lv3_DuctTgt_Plus_Limo)); + M_MEMCOPY((g_assFoot2_Lv4_DuctTgt_Plus), (c_assFoot2_Lv4_DuctTgt_Plus_Limo)); + M_MEMCOPY((g_assFoot2_Lv5_DuctTgt_Plus), (c_assFoot2_Lv5_DuctTgt_Plus_Limo)); + M_MEMCOPY((g_ausFoot2_Lv1_FrontBlr_X), (c_ausFoot2_Lv1_FrontBlr_X_Limo)); + M_MEMCOPY((g_ausFoot2_Lv1_Foot2Act_Y), (c_ausFoot2_Lv1_Foot2Act_Y_Limo)); + M_MEMCOPY((g_assFoot2_Lv2_Threshold_Diff), (c_assFoot2_Lv2_Threshold_Diff_Limo)); + M_MEMCOPY((g_assFoot2_Lv3_Threshold_Diff), (c_assFoot2_Lv3_Threshold_Diff_Limo)); +/* ------------------------------------------Foot2 Ctrl: End*/ + M_MEMCOPY((g_ausDbF_Side_Af_Bi), (c_ausDbF_Side_Af_Bi_Limo)); + M_MEMCOPY((g_ausDbF_Side_Af_Bi2), (c_ausDbF_Side_Af_Bi2_Limo)); + M_MEMCOPY((g_ausDbF_Side_Af_Vent), (c_ausDbF_Side_Af_Vent_Limo)); + M_MEMCOPY((g_ausDbF_Side_Bi_Bi2), (c_ausDbF_Side_Bi_Bi2_Limo)); + M_MEMCOPY((g_ausDbF_Side_Bi_Vent), (c_ausDbF_Side_Bi_Vent_Limo)); + M_MEMCOPY((g_ausDbF_Side_Bi2_Vent), (c_ausDbF_Side_Bi2_Vent_Limo)); + M_MEMCOPY((g_ausDbF_Cen_Af_Bi), (c_ausDbF_Cen_Af_Bi_Limo)); + M_MEMCOPY((g_ausDbF_Cen_Af_Bi2), (c_ausDbF_Cen_Af_Bi2_Limo)); + M_MEMCOPY((g_ausDbF_Cen_Af_Vent), (c_ausDbF_Cen_Af_Vent_Limo)); + M_MEMCOPY((g_ausDbF_Cen_Bi_Bi2), (c_ausDbF_Cen_Bi_Bi2_Limo)); + M_MEMCOPY((g_ausDbF_Cen_Bi_Vent), (c_ausDbF_Cen_Bi_Vent_Limo)); + M_MEMCOPY((g_ausDbF_Cen_Bi2_Vent), (c_ausDbF_Cen_Bi2_Vent_Limo)); + M_MEMCOPY((g_ausDbF_Foot_Af_Bi), (c_ausDbF_Foot_Af_Bi_Limo)); + M_MEMCOPY((g_ausDbF_Foot_Af_Bi2), (c_ausDbF_Foot_Af_Bi2_Limo)); + M_MEMCOPY((g_ausDbF_Foot_Af_Vent), (c_ausDbF_Foot_Af_Vent_Limo)); + M_MEMCOPY((g_ausDbF_Foot_Bi_Bi2), (c_ausDbF_Foot_Bi_Bi2_Limo)); + M_MEMCOPY((g_ausDbF_Foot_Bi_Vent), (c_ausDbF_Foot_Bi_Vent_Limo)); + M_MEMCOPY((g_ausDbF_Foot_Bi2_Vent), (c_ausDbF_Foot_Bi2_Vent_Limo)); + M_MEMCOPY((g_ausDbF_AF_Af_Bi), (c_ausDbF_AF_Af_Bi_Limo)); + M_MEMCOPY((g_ausDbF_AF_Af_Bi2), (c_ausDbF_AF_Af_Bi2_Limo)); + M_MEMCOPY((g_ausDbF_AF_Af_Vent), (c_ausDbF_AF_Af_Vent_Limo)); + M_MEMCOPY((g_ausDbF_AF_Bi_Bi2), (c_ausDbF_AF_Bi_Bi2_Limo)); + M_MEMCOPY((g_ausDbF_AF_Bi_Vent), (c_ausDbF_AF_Bi_Vent_Limo)); + M_MEMCOPY((g_ausDbF_AF_Bi2_Vent), (c_ausDbF_AF_Bi2_Vent_Limo)); + M_MEMCOPY((g_ausDbF_Pwm_Af_Bi), (c_ausDbF_Pwm_Af_Bi_Limo)); + M_MEMCOPY((g_ausDbF_Pwm_Af_Bi2), (c_ausDbF_Pwm_Af_Bi2_Limo)); + M_MEMCOPY((g_ausDbF_Pwm_Af_Vent), (c_ausDbF_Pwm_Af_Vent_Limo)); + M_MEMCOPY((g_ausDbF_Pwm_Bi_Bi2), (c_ausDbF_Pwm_Bi_Bi2_Limo)); + M_MEMCOPY((g_ausDbF_Pwm_Bi_Vent), (c_ausDbF_Pwm_Bi_Vent_Limo)); + M_MEMCOPY((g_ausDbF_Pwm_Bi2_Vent), (c_ausDbF_Pwm_Bi2_Vent_Limo)); +/* ------------------------------------------Different blower Front: End*/ + g_usAromaPwm_Min = c_usAromaPwm_Min_Limo; + g_usAromaPwm_Max = c_usAromaPwm_Max_Limo; +/* ------------------------------------------Aroma Limit Pwm: End*/ +/*********************************************************Cal Table End*/ + +} +/****************************************************************************** + * LOCAL FUNCTIONS + *****************************************************************************/ +/* End of Excel line : 2159 */ +/****************************************************************************** + * EOF + *****************************************************************************/ diff --git a/MODULES/HVAC_M7_DataNonVolatile/calib/Rs_Cal_2_Limo.h b/MODULES/HVAC_M7_DataNonVolatile/calib/Rs_Cal_2_Limo.h new file mode 100644 index 0000000..fb52ec4 --- /dev/null +++ b/MODULES/HVAC_M7_DataNonVolatile/calib/Rs_Cal_2_Limo.h @@ -0,0 +1,38 @@ +/** Doxygen: File brief + ****************************************************************************** + * @file Rs_Cal_2_Limo.h + * @brief No brief + * @remark Generated by C:\9999\Rs_Cal_R23_ver21_SedanL.xlsm + * Generated on yyyy-mm-dd hh:mm:ss + *****************************************************************************/ +#ifndef RS_CAL_2_LIMO_H__ +#define RS_CAL_2_LIMO_H__ + +/****************************************************************************** + * INCLUDE FILES +*****************************************************************************/ +#include "rtwtypes.h" +#include "common.h" +#include "HVAC_preDefine.h" +#include "Rs_Cal_Base.h" + +/****************************************************************************** + * MACRO DECLARATIONS + *****************************************************************************/ +/****************************************************************************** + * GLOBAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS) + *****************************************************************************/ +/****************************************************************************** + * GLOBAL VARIABLES DECLARATIONS + *****************************************************************************/ +extern SECT_VEH_CAL_2 const tU08 c_ucCalFromRelease_Limo; +/****************************************************************************** + * GLOBAL FUNCTIONS DECLARATIONS + *****************************************************************************/ +extern void Rs_Cal_2_Limo(void); + +/* End of Excel line : 34 */ +#endif /*RS_CAL_2_LIMO_H__*/ +/****************************************************************************** + * EOF + *****************************************************************************/ diff --git a/MODULES/HVAC_M7_DataNonVolatile/calib/Rs_Cal_3_Suv.c b/MODULES/HVAC_M7_DataNonVolatile/calib/Rs_Cal_3_Suv.c new file mode 100644 index 0000000..40b8bb1 --- /dev/null +++ b/MODULES/HVAC_M7_DataNonVolatile/calib/Rs_Cal_3_Suv.c @@ -0,0 +1,2162 @@ +/** Doxygen: File brief + ****************************************************************************** + * @file Rs_Cal_3_Suv.c + * @brief No brief + * @remark Generated by C:\9999\Rs_Cal_R23_ver21_SedanL.xlsm + * Generated on yyyy-mm-dd hh:mm:ss + *****************************************************************************/ +/****************************************************************************** + * INCLUDE FILES + *****************************************************************************/ +#include "Rs_Cal_3_Suv.h" + +/****************************************************************************** + * MACRO DECLARATIONS + *****************************************************************************/ +/*PRQA S 0615 EOF #suppress : More than 511 block scope identifiers, from Calibration data table, No impact*/ +/*PRQA S 1514 EOF #suppress : In the same translation(used != defined), from Calibration data table, No impact*/ +/*PRQA S 3408 EOF #suppress : To manage Cal. data separately, from Calibration data table, No Impact*/ +/****************************************************************************** + * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS) + *****************************************************************************/ +/****************************************************************************** + * GLOBAL VARIABLES DECLARATIONS + *****************************************************************************/ +SECT_VEH_CAL_3 const tU08 c_ucCalFromRelease_Suv = ID_TRUE; +SECT_VEH_CAL_3 const tU08 c_aucCAL_FP_DATE_Suv[3] = { VERSION_SUV_Y, VERSION_SUV_M, VERSION_SUV_D}; +SECT_VEH_CAL_3 const tU08 c_aucCAL_VERSION_Suv[2] = { 0, 20}; +SECT_VEH_CAL_3 const tU08 c_ucCAL_VARIANT_Suv = 4; +/* ------------------------------------------Cal Version : End*/ +SECT_VEH_CAL_3 const tU16 c_ausSET_TEMP_FULL_Suv[13] = { 170, 180, 190, 200, 210, 220, 230, 240, 250, 260, 270, 280, 290}; +SECT_VEH_CAL_3 const tU16 c_ausSET_TEMP_HALF_Suv[7] = { 170, 190, 210, 230, 250, 270, 290}; +/* ------------------------------------------Set Temp : End*/ +SECT_VEH_CAL_3 const tS16 c_assINCAR_TG_FL_LV0_Suv[13] = { 180, 190, 200, 210, 220, 235, 245, 255, 270, 280, 290, 310, 330}; +SECT_VEH_CAL_3 const tS16 c_assINCAR_TG_FR_LV0_Suv[13] = { 180, 190, 200, 210, 220, 235, 245, 255, 270, 280, 290, 310, 330}; +SECT_VEH_CAL_3 const tS16 c_assVTG_FL_LV0_Suv[13] = { 120, 105, 100, 95, 90, 85, 80, 80, 70, 65, 60, 60, 60}; +SECT_VEH_CAL_3 const tS16 c_assVTG_FR_LV0_Suv[13] = { 120, 105, 100, 95, 90, 85, 80, 80, 70, 65, 60, 60, 60}; +SECT_VEH_CAL_3 const tS16 c_assVF_MIN_LV0_Suv[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_3 const tS16 c_assVF_MAX_LV0_Suv[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_Y1_LV0_Suv[7] = { 60, 60, 50, 50, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_Y2_LV0_Suv[7] = { 20, 20, 20, 20, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_Y3_LV0_Suv[7] = { -20, -20, -20, -10, 5, 5, 5}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_Y4_LV0_Suv[7] = { -50, -50, -50, -20, 10, 10, 10}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_X1_LV0_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_X2_LV0_Suv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_X3_LV0_Suv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_X4_LV0_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assVF_AMB_Y1_LV0_Suv[7] = { 10, 10, 10, 5, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVF_AMB_Y2_LV0_Suv[7] = { -10, -10, -10, -10, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVF_AMB_X1_LV0_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assVF_AMB_X2_LV0_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assVF_SUN_Y1_LV0_Suv[7] = { 20, 20, 20, 20, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVF_SUN_Y2_LV0_Suv[7] = { 50, 50, 50, 50, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVF_SUN_X1_LV0_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assVF_SUN_X2_LV0_Suv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_3 const tS16 c_assTG_FLU_LV0_Suv[13] = { 20, 20, 20, 50, 60, 80, 100, 125, 180, 250, 380, 500, 550}; +SECT_VEH_CAL_3 const tS16 c_assTG_FRU_LV0_Suv[13] = { 20, 20, 20, 50, 60, 80, 100, 125, 180, 250, 380, 500, 550}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_MIN_LV0_Suv[7] = { 20, 20, 20, 50, 50, 50, 50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_MAX_LV0_Suv[7] = { 600, 600, 600, 600, 600, 600, 600}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_Y1_LV0_Suv[7] = { 0, -20, -50, -50, -100, -150, -200}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_Y2_LV0_Suv[7] = { 0, -10, -30, -50, -50, -50, -50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_Y3_LV0_Suv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_Y4_LV0_Suv[7] = { 200, 200, 200, 150, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_X1_LV0_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_X2_LV0_Suv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_X3_LV0_Suv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_X4_LV0_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_AMB_Y1_LV0_Suv[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_AMB_Y2_LV0_Suv[7] = { 50, 50, 50, 50, 50, 25, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_AMB_X1_LV0_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_AMB_X2_LV0_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_SUN_Y1_LV0_Suv[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_SUN_Y2_LV0_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_SUN_X1_LV0_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_SUN_X2_LV0_Suv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_3 const tS16 c_assTG_FLL_LV0_Suv[13] = { 150, 150, 150, 150, 200, 250, 300, 400, 450, 500, 600, 650, 700}; +SECT_VEH_CAL_3 const tS16 c_assTG_FRL_LV0_Suv[13] = { 150, 150, 150, 150, 200, 250, 300, 400, 450, 500, 600, 650, 700}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_MIN_LV0_Suv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_MAX_LV0_Suv[7] = { 400, 450, 500, 600, 600, 600, 600}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_Y1_LV0_Suv[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_Y2_LV0_Suv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_Y3_LV0_Suv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_Y4_LV0_Suv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_X1_LV0_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_X2_LV0_Suv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_X3_LV0_Suv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_X4_LV0_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_AMB_Y1_LV0_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_AMB_Y2_LV0_Suv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_AMB_X1_LV0_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_AMB_X2_LV0_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_SUN_Y1_LV0_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_SUN_Y2_LV0_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_SUN_X1_LV0_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_SUN_X2_LV0_Suv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_3 const tS16 c_assINCAR_TG_RL_LV0_Suv[13] = { 190, 195, 200, 215, 230, 240, 250, 270, 280, 290, 300, 310, 320}; +SECT_VEH_CAL_3 const tS16 c_assINCAR_TG_RR_LV0_Suv[13] = { 190, 195, 200, 215, 230, 240, 250, 270, 280, 290, 300, 310, 320}; +SECT_VEH_CAL_3 const tS16 c_assVTG_RL_LV0_Suv[13] = { 110, 100, 92, 82, 75, 70, 65, 65, 60, 60, 60, 60, 60}; +SECT_VEH_CAL_3 const tS16 c_assVTG_RR_LV0_Suv[13] = { 110, 100, 92, 82, 75, 70, 65, 65, 60, 60, 60, 60, 60}; +SECT_VEH_CAL_3 const tS16 c_assVR_MIN_LV0_Suv[7] = { 80, 80, 40, 40, 40, 30, 30}; +SECT_VEH_CAL_3 const tS16 c_assVR_MAX_LV0_Suv[7] = { 160, 160, 160, 160, 100, 80, 80}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_Y1_LV0_Suv[7] = { 60, 60, 50, 50, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_Y2_LV0_Suv[7] = { 20, 20, 20, 20, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_Y3_LV0_Suv[7] = { -20, -20, -20, -10, 5, 5, 5}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_Y4_LV0_Suv[7] = { -50, -50, -50, -20, 10, 10, 10}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_X1_LV0_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_X2_LV0_Suv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_X3_LV0_Suv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_X4_LV0_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assVR_AMB_Y1_LV0_Suv[7] = { 20, 20, 20, 20, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVR_AMB_Y2_LV0_Suv[7] = { 0, 0, -50, -50, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVR_AMB_X1_LV0_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assVR_AMB_X2_LV0_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assVR_SUN_Y1_LV0_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVR_SUN_Y2_LV0_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVR_SUN_X1_LV0_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assVR_SUN_X2_LV0_Suv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_3 const tS16 c_assTG_RL_LV0_Suv[13] = { 30, 30, 30, 50, 90, 100, 120, 180, 240, 320, 400, 450, 500}; +SECT_VEH_CAL_3 const tS16 c_assTG_RR_LV0_Suv[13] = { 30, 30, 30, 50, 90, 100, 120, 180, 240, 320, 400, 450, 500}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_MIN_LV0_Suv[7] = { 20, 20, 20, 20, 50, 50, 50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_MAX_LV0_Suv[7] = { 400, 400, 450, 500, 600, 600, 600}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_Y1_LV0_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_Y2_LV0_Suv[7] = { -40, -40, -40, -40, -40, -50, -60}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_Y3_LV0_Suv[7] = { 40, 40, 40, 40, 20, 20, 20}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_Y4_LV0_Suv[7] = { 200, 200, 200, 100, 50, 50, 50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_X1_LV0_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_X2_LV0_Suv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_X3_LV0_Suv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_X4_LV0_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_AMB_Y1_LV0_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_AMB_Y2_LV0_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_AMB_X1_LV0_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_AMB_X2_LV0_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_SUN_Y1_LV0_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_SUN_Y2_LV0_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_SUN_X1_LV0_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_SUN_X2_LV0_Suv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_DUCT_TIME_FR_LV0_Suv[7] = { 600, 600, 600, 600, 600, 600, 600}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_DUCT_TIME_FL_LV0_Suv[7] = { 600, 600, 600, 600, 600, 600, 600}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_DUCT_RATE_LV0_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_DUCT_MAX_LV0_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_AF_TIME_FR_LV0_Suv[7] = { 3000, 3000, 3000, 3000, 3000, 3000, 3000}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_AF_TIME_FL_LV0_Suv[7] = { 3000, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_AF_RATE_LV0_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_AF_MAX_LV0_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +/* ------------------------------------------Lv0 : End*/ +SECT_VEH_CAL_3 const tS16 c_assINCAR_TG_FL_LV1_Suv[13] = { 180, 190, 200, 210, 220, 235, 245, 255, 265, 270, 280, 300, 310}; +SECT_VEH_CAL_3 const tS16 c_assINCAR_TG_FR_LV1_Suv[13] = { 180, 190, 200, 210, 220, 235, 245, 255, 265, 270, 280, 300, 310}; +SECT_VEH_CAL_3 const tS16 c_assVTG_FL_LV1_Suv[13] = { 110, 95, 90, 85, 80, 75, 70, 70, 65, 65, 60, 60, 60}; +SECT_VEH_CAL_3 const tS16 c_assVTG_FR_LV1_Suv[13] = { 110, 95, 90, 85, 80, 75, 70, 70, 65, 65, 60, 60, 60}; +SECT_VEH_CAL_3 const tS16 c_assVF_MIN_LV1_Suv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_3 const tS16 c_assVF_MAX_LV1_Suv[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_Y1_LV1_Suv[7] = { 40, 40, 45, 50, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_Y2_LV1_Suv[7] = { 10, 10, 10, 10, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_Y3_LV1_Suv[7] = { -10, -10, -10, -10, 5, 5, 5}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_Y4_LV1_Suv[7] = { -50, -40, -30, -30, 10, 10, 10}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_X1_LV1_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_X2_LV1_Suv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_X3_LV1_Suv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_X4_LV1_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assVF_AMB_Y1_LV1_Suv[7] = { 10, 10, 10, 10, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVF_AMB_Y2_LV1_Suv[7] = { -10, -10, -10, -10, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVF_AMB_X1_LV1_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assVF_AMB_X2_LV1_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assVF_SUN_Y1_LV1_Suv[7] = { 10, 10, 10, 10, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVF_SUN_Y2_LV1_Suv[7] = { 30, 30, 30, 30, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVF_SUN_X1_LV1_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assVF_SUN_X2_LV1_Suv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_3 const tS16 c_assTG_FLU_LV1_Suv[13] = { 50, 70, 90, 120, 130, 140, 150, 180, 250, 350, 450, 500, 550}; +SECT_VEH_CAL_3 const tS16 c_assTG_FRU_LV1_Suv[13] = { 50, 70, 90, 120, 130, 140, 150, 180, 250, 350, 450, 500, 550}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_MIN_LV1_Suv[7] = { 20, 20, 20, 20, 50, 50, 50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_MAX_LV1_Suv[7] = { 400, 450, 450, 500, 600, 600, 600}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_Y1_LV1_Suv[7] = { 0, -20, -50, -70, -100, -150, -200}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_Y2_LV1_Suv[7] = { 0, -10, -30, -50, -50, -50, -50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_Y3_LV1_Suv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_Y4_LV1_Suv[7] = { 200, 200, 200, 150, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_X1_LV1_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_X2_LV1_Suv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_X3_LV1_Suv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_X4_LV1_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_AMB_Y1_LV1_Suv[7] = { 0, 0, -30, -50, -30, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_AMB_Y2_LV1_Suv[7] = { 0, 30, 50, 100, 50, 50, 50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_AMB_X1_LV1_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_AMB_X2_LV1_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_SUN_Y1_LV1_Suv[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_SUN_Y2_LV1_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_SUN_X1_LV1_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_SUN_X2_LV1_Suv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_3 const tS16 c_assTG_FLL_LV1_Suv[13] = { 150, 200, 250, 250, 250, 250, 300, 400, 450, 500, 600, 650, 800}; +SECT_VEH_CAL_3 const tS16 c_assTG_FRL_LV1_Suv[13] = { 150, 200, 250, 250, 250, 250, 300, 400, 450, 500, 600, 650, 800}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_MIN_LV1_Suv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_MAX_LV1_Suv[7] = { 450, 450, 500, 600, 600, 600, 600}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_Y1_LV1_Suv[7] = { 0, 0, 0, 0, 0, -100, -200}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_Y2_LV1_Suv[7] = { 0, 0, 0, 0, -50, -50, -50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_Y3_LV1_Suv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_Y4_LV1_Suv[7] = { 100, 100, 100, 50, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_X1_LV1_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_X2_LV1_Suv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_X3_LV1_Suv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_X4_LV1_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_AMB_Y1_LV1_Suv[7] = { 0, 0, -30, -50, -50, -50, -50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_AMB_Y2_LV1_Suv[7] = { 0, 0, 30, 50, 50, 50, 50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_AMB_X1_LV1_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_AMB_X2_LV1_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_SUN_Y1_LV1_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_SUN_Y2_LV1_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_SUN_X1_LV1_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_SUN_X2_LV1_Suv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_3 const tS16 c_assINCAR_TG_RL_LV1_Suv[13] = { 190, 195, 200, 215, 230, 240, 250, 270, 280, 290, 300, 310, 320}; +SECT_VEH_CAL_3 const tS16 c_assINCAR_TG_RR_LV1_Suv[13] = { 190, 195, 200, 215, 230, 240, 250, 270, 280, 290, 300, 310, 320}; +SECT_VEH_CAL_3 const tS16 c_assVTG_RL_LV1_Suv[13] = { 110, 100, 90, 80, 70, 65, 65, 65, 70, 70, 70, 70, 70}; +SECT_VEH_CAL_3 const tS16 c_assVTG_RR_LV1_Suv[13] = { 110, 100, 90, 80, 70, 65, 65, 65, 70, 70, 70, 70, 70}; +SECT_VEH_CAL_3 const tS16 c_assVR_MIN_LV1_Suv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_3 const tS16 c_assVR_MAX_LV1_Suv[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_Y1_LV1_Suv[7] = { 60, 60, 50, 50, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_Y2_LV1_Suv[7] = { 20, 20, 20, 20, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_Y3_LV1_Suv[7] = { -20, -20, -20, -10, 5, 5, 5}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_Y4_LV1_Suv[7] = { -50, -50, -50, -20, 10, 10, 10}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_X1_LV1_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_X2_LV1_Suv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_X3_LV1_Suv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_X4_LV1_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assVR_AMB_Y1_LV1_Suv[7] = { 0, 0, 5, 0, -10, -10, -10}; +SECT_VEH_CAL_3 const tS16 c_assVR_AMB_Y2_LV1_Suv[7] = { 0, 0, -5, -5, 10, 15, 20}; +SECT_VEH_CAL_3 const tS16 c_assVR_AMB_X1_LV1_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assVR_AMB_X2_LV1_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assVR_SUN_Y1_LV1_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVR_SUN_Y2_LV1_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVR_SUN_X1_LV1_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assVR_SUN_X2_LV1_Suv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_3 const tS16 c_assTG_RL_LV1_Suv[13] = { 30, 30, 50, 80, 90, 100, 130, 160, 240, 320, 400, 450, 500}; +SECT_VEH_CAL_3 const tS16 c_assTG_RR_LV1_Suv[13] = { 30, 30, 50, 80, 90, 100, 130, 160, 240, 320, 400, 450, 500}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_MIN_LV1_Suv[7] = { 20, 20, 20, 20, 50, 50, 50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_MAX_LV1_Suv[7] = { 400, 400, 450, 500, 600, 600, 600}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_Y1_LV1_Suv[7] = { -100, -100, -100, -100, -100, -150, -200}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_Y2_LV1_Suv[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_Y3_LV1_Suv[7] = { 50, 50, 50, 50, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_Y4_LV1_Suv[7] = { 200, 200, 200, 200, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_X1_LV1_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_X2_LV1_Suv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_X3_LV1_Suv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_X4_LV1_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_AMB_Y1_LV1_Suv[7] = { 0, 0, -10, -10, -50, -50, -50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_AMB_Y2_LV1_Suv[7] = { 0, 0, 20, 20, 50, 50, 50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_AMB_X1_LV1_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_AMB_X2_LV1_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_SUN_Y1_LV1_Suv[7] = { 0, 0, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_SUN_Y2_LV1_Suv[7] = { 0, 0, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_SUN_X1_LV1_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_SUN_X2_LV1_Suv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_DUCT_TIME_FR_LV1_Suv[7] = { 600, 600, 600, 600, 600, 600, 600}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_DUCT_TIME_FL_LV1_Suv[7] = { 600, 600, 600, 600, 600, 600, 600}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_DUCT_RATE_LV1_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_DUCT_MAX_LV1_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_AF_TIME_FR_LV1_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_AF_TIME_FL_LV1_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_AF_RATE_LV1_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_AF_MAX_LV1_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +/* ------------------------------------------Lv1 : End*/ +SECT_VEH_CAL_3 const tS16 c_assINCAR_TG_FL_LV2_Suv[13] = { 180, 190, 200, 210, 230, 245, 255, 265, 270, 280, 290, 300, 310}; +SECT_VEH_CAL_3 const tS16 c_assINCAR_TG_FR_LV2_Suv[13] = { 180, 190, 200, 210, 230, 245, 255, 265, 270, 280, 290, 300, 310}; +SECT_VEH_CAL_3 const tS16 c_assVTG_FL_LV2_Suv[13] = { 90, 83, 75, 62, 50, 55, 60, 60, 65, 70, 70, 75, 80}; +SECT_VEH_CAL_3 const tS16 c_assVTG_FR_LV2_Suv[13] = { 90, 83, 75, 62, 50, 55, 60, 60, 65, 70, 70, 75, 80}; +SECT_VEH_CAL_3 const tS16 c_assVF_MIN_LV2_Suv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_3 const tS16 c_assVF_MAX_LV2_Suv[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_Y1_LV2_Suv[7] = { -10, -10, -10, 10, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_Y2_LV2_Suv[7] = { -5, -5, -5, 5, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_Y3_LV2_Suv[7] = { 0, 0, 0, 5, 5, 5, 5}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_Y4_LV2_Suv[7] = { 0, 0, 0, 10, 10, 10, 10}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_X1_LV2_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_X2_LV2_Suv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_X3_LV2_Suv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_X4_LV2_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assVF_AMB_Y1_LV2_Suv[7] = { 10, 12, 15, 10, -10, -10, -10}; +SECT_VEH_CAL_3 const tS16 c_assVF_AMB_Y2_LV2_Suv[7] = { 0, 0, 0, 5, 8, 10, 10}; +SECT_VEH_CAL_3 const tS16 c_assVF_AMB_X1_LV2_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assVF_AMB_X2_LV2_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assVF_SUN_Y1_LV2_Suv[7] = { 5, 5, 5, 5, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVF_SUN_Y2_LV2_Suv[7] = { 10, 10, 10, 10, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVF_SUN_X1_LV2_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assVF_SUN_X2_LV2_Suv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_3 const tS16 c_assTG_FLU_LV2_Suv[13] = { 50, 50, 90, 120, 150, 200, 250, 300, 335, 375, 450, 470, 480}; +SECT_VEH_CAL_3 const tS16 c_assTG_FRU_LV2_Suv[13] = { 50, 50, 90, 120, 150, 200, 250, 300, 335, 375, 450, 470, 480}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_MIN_LV2_Suv[7] = { 20, 20, 20, 30, 40, 50, 50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_MAX_LV2_Suv[7] = { 450, 450, 550, 600, 600, 600, 600}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_Y1_LV2_Suv[7] = { -100, -100, -150, -150, -150, -150, -150}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_Y2_LV2_Suv[7] = { -50, -50, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_Y3_LV2_Suv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_Y4_LV2_Suv[7] = { 200, 200, 200, 200, 200, 200, 200}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_X1_LV2_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_X2_LV2_Suv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_X3_LV2_Suv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_X4_LV2_Suv[7] = { 150, 150, 150, 150, 150, 150, 150}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_AMB_Y1_LV2_Suv[7] = { 0, 0, 0, -50, -50, -50, -50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_AMB_Y2_LV2_Suv[7] = { 0, 0, 50, 135, 120, 120, 120}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_AMB_X1_LV2_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_AMB_X2_LV2_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_SUN_Y1_LV2_Suv[7] = { 0, 0, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_SUN_Y2_LV2_Suv[7] = { 0, 0, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_SUN_X1_LV2_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_SUN_X2_LV2_Suv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_3 const tS16 c_assTG_FLL_LV2_Suv[13] = { 150, 200, 250, 250, 275, 300, 350, 400, 450, 525, 600, 700, 800}; +SECT_VEH_CAL_3 const tS16 c_assTG_FRL_LV2_Suv[13] = { 150, 200, 250, 250, 275, 300, 350, 400, 450, 525, 600, 700, 800}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_MIN_LV2_Suv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_MAX_LV2_Suv[7] = { 450, 450, 500, 800, 800, 800, 800}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_Y1_LV2_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_Y2_LV2_Suv[7] = { -50, -50, -20, -50, -50, -50, -50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_Y3_LV2_Suv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_Y4_LV2_Suv[7] = { 400, 400, 400, 400, 400, 400, 400}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_X1_LV2_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_X2_LV2_Suv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_X3_LV2_Suv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_X4_LV2_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_AMB_Y1_LV2_Suv[7] = { 0, 0, 0, -50, -50, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_AMB_Y2_LV2_Suv[7] = { 150, 200, 150, 200, 150, 100, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_AMB_X1_LV2_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_AMB_X2_LV2_Suv[7] = { 150, 150, 150, 150, 150, 150, 150}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_SUN_Y1_LV2_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_SUN_Y2_LV2_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_SUN_X1_LV2_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_SUN_X2_LV2_Suv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_3 const tS16 c_assINCAR_TG_RL_LV2_Suv[13] = { 190, 195, 200, 215, 230, 240, 250, 270, 280, 290, 300, 310, 320}; +SECT_VEH_CAL_3 const tS16 c_assINCAR_TG_RR_LV2_Suv[13] = { 190, 195, 200, 215, 230, 240, 250, 270, 280, 290, 300, 310, 320}; +SECT_VEH_CAL_3 const tS16 c_assVTG_RL_LV2_Suv[13] = { 90, 83, 75, 62, 55, 55, 60, 60, 65, 70, 70, 75, 80}; +SECT_VEH_CAL_3 const tS16 c_assVTG_RR_LV2_Suv[13] = { 90, 83, 75, 62, 55, 55, 60, 60, 65, 70, 70, 75, 80}; +SECT_VEH_CAL_3 const tS16 c_assVR_MIN_LV2_Suv[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_3 const tS16 c_assVR_MAX_LV2_Suv[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_Y1_LV2_Suv[7] = { 30, 30, 30, 30, -10, -20, -20}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_Y2_LV2_Suv[7] = { 5, 5, 5, 10, -5, -15, -20}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_Y3_LV2_Suv[7] = { -10, -10, -10, 25, 10, 10, 10}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_Y4_LV2_Suv[7] = { -30, -30, -30, 50, 30, 30, 30}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_X1_LV2_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_X2_LV2_Suv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_X3_LV2_Suv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_X4_LV2_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assVR_AMB_Y1_LV2_Suv[7] = { 20, 15, 15, 10, -5, -10, -20}; +SECT_VEH_CAL_3 const tS16 c_assVR_AMB_Y2_LV2_Suv[7] = { 0, 0, 0, 5, 5, 10, 10}; +SECT_VEH_CAL_3 const tS16 c_assVR_AMB_X1_LV2_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assVR_AMB_X2_LV2_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assVR_SUN_Y1_LV2_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVR_SUN_Y2_LV2_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVR_SUN_X1_LV2_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assVR_SUN_X2_LV2_Suv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_3 const tS16 c_assTG_RL_LV2_Suv[13] = { 50, 50, 50, 80, 90, 100, 150, 180, 240, 320, 400, 450, 500}; +SECT_VEH_CAL_3 const tS16 c_assTG_RR_LV2_Suv[13] = { 50, 50, 50, 80, 90, 100, 150, 180, 240, 320, 400, 500, 500}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_MIN_LV2_Suv[7] = { 20, 20, 20, 20, 380, 400, 400}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_MAX_LV2_Suv[7] = { 400, 400, 450, 500, 600, 600, 800}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_Y1_LV2_Suv[7] = { -100, -100, -100, -100, -100, -100, -250}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_Y2_LV2_Suv[7] = { -50, -50, -50, -50, -50, -80, -100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_Y3_LV2_Suv[7] = { 50, 50, 50, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_Y4_LV2_Suv[7] = { 200, 200, 200, 250, 250, 250, 300}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_X1_LV2_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_X2_LV2_Suv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_X3_LV2_Suv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_X4_LV2_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_AMB_Y1_LV2_Suv[7] = { 0, 0, 0, -20, -20, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_AMB_Y2_LV2_Suv[7] = { 0, 0, 10, 30, 50, 80, 100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_AMB_X1_LV2_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_AMB_X2_LV2_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_SUN_Y1_LV2_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_SUN_Y2_LV2_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_SUN_X1_LV2_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_SUN_X2_LV2_Suv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_DUCT_TIME_FR_LV2_Suv[7] = { 3600, 3600, 3600, 3600, 3600, 3600, 3600}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_DUCT_TIME_FL_LV2_Suv[7] = { 3600, 3600, 3600, 3600, 3600, 3600, 3600}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_DUCT_RATE_LV2_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_DUCT_MAX_LV2_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_AF_TIME_FR_LV2_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_AF_TIME_FL_LV2_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_AF_RATE_LV2_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_AF_MAX_LV2_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +/* ------------------------------------------Lv2 : End*/ +SECT_VEH_CAL_3 const tS16 c_assINCAR_TG_FL_LV3_Suv[13] = { 180, 190, 200, 210, 230, 245, 255, 265, 270, 280, 290, 300, 310}; +SECT_VEH_CAL_3 const tS16 c_assINCAR_TG_FR_LV3_Suv[13] = { 180, 190, 200, 210, 230, 245, 255, 265, 270, 280, 290, 300, 310}; +SECT_VEH_CAL_3 const tS16 c_assVTG_FL_LV3_Suv[13] = { 90, 83, 75, 62, 55, 55, 65, 65, 70, 73, 86, 88, 90}; +SECT_VEH_CAL_3 const tS16 c_assVTG_FR_LV3_Suv[13] = { 90, 83, 75, 62, 55, 55, 65, 65, 70, 73, 86, 88, 90}; +SECT_VEH_CAL_3 const tS16 c_assVF_MIN_LV3_Suv[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_3 const tS16 c_assVF_MAX_LV3_Suv[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_Y1_LV3_Suv[7] = { 15, 15, 15, 25, 15, -30, -60}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_Y2_LV3_Suv[7] = { 5, 5, 10, 5, 0, -10, -40}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_Y3_LV3_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_Y4_LV3_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_X1_LV3_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_X2_LV3_Suv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_X3_LV3_Suv[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_X4_LV3_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assVF_AMB_Y1_LV3_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVF_AMB_Y2_LV3_Suv[7] = { -30, 0, 0, 0, 0, 20, 40}; +SECT_VEH_CAL_3 const tS16 c_assVF_AMB_X1_LV3_Suv[7] = { -10, -10, -10, -10, -10, -10, -10}; +SECT_VEH_CAL_3 const tS16 c_assVF_AMB_X2_LV3_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assVF_SUN_Y1_LV3_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVF_SUN_Y2_LV3_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVF_SUN_X1_LV3_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assVF_SUN_X2_LV3_Suv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_3 const tS16 c_assTG_FLU_LV3_Suv[13] = { 50, 50, 140, 200, 300, 335, 370, 400, 420, 435, 460, 470, 480}; +SECT_VEH_CAL_3 const tS16 c_assTG_FRU_LV3_Suv[13] = { 50, 50, 140, 200, 280, 310, 330, 380, 390, 420, 450, 470, 480}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_MIN_LV3_Suv[7] = { 20, 20, 20, 30, 200, 200, 250}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_MAX_LV3_Suv[7] = { 450, 450, 550, 800, 800, 750, 700}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_Y1_LV3_Suv[7] = { -100, -100, -100, -150, -200, -250, -300}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_Y2_LV3_Suv[7] = { -30, -30, -70, -80, -50, -50, -100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_Y3_LV3_Suv[7] = { 50, 50, 50, 50, 50, 30, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_Y4_LV3_Suv[7] = { 100, 100, 100, 100, 80, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_X1_LV3_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_X2_LV3_Suv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_X3_LV3_Suv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_X4_LV3_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_AMB_Y1_LV3_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_AMB_Y2_LV3_Suv[7] = { 30, 30, 30, 60, 60, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_AMB_X1_LV3_Suv[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_AMB_X2_LV3_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_SUN_Y1_LV3_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_SUN_Y2_LV3_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_SUN_X1_LV3_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_SUN_X2_LV3_Suv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_3 const tS16 c_assTG_FLL_LV3_Suv[13] = { 300, 400, 400, 400, 400, 450, 520, 550, 600, 650, 700, 750, 800}; +SECT_VEH_CAL_3 const tS16 c_assTG_FRL_LV3_Suv[13] = { 300, 400, 400, 400, 400, 450, 550, 580, 630, 680, 730, 780, 830}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_MIN_LV3_Suv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_MAX_LV3_Suv[7] = { 600, 600, 800, 800, 800, 800, 950}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_Y1_LV3_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_Y2_LV3_Suv[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_Y3_LV3_Suv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_Y4_LV3_Suv[7] = { 250, 300, 400, 400, 400, 400, 400}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_X1_LV3_Suv[7] = { -100, -100, -100, -100, -120, -130, -150}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_X2_LV3_Suv[7] = { -20, -20, -20, -20, -50, -50, -50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_X3_LV3_Suv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_X4_LV3_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_AMB_Y1_LV3_Suv[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_AMB_Y2_LV3_Suv[7] = { 100, 100, 120, 150, 100, 50, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_AMB_X1_LV3_Suv[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_AMB_X2_LV3_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_SUN_Y1_LV3_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_SUN_Y2_LV3_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_SUN_X1_LV3_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_SUN_X2_LV3_Suv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_3 const tS16 c_assINCAR_TG_RL_LV3_Suv[13] = { 190, 195, 200, 215, 230, 235, 240, 255, 270, 280, 290, 300, 310}; +SECT_VEH_CAL_3 const tS16 c_assINCAR_TG_RR_LV3_Suv[13] = { 190, 195, 200, 215, 230, 235, 240, 255, 270, 280, 290, 300, 310}; +SECT_VEH_CAL_3 const tS16 c_assVTG_RL_LV3_Suv[13] = { 110, 100, 90, 80, 70, 65, 65, 65, 80, 90, 80, 90, 90}; +SECT_VEH_CAL_3 const tS16 c_assVTG_RR_LV3_Suv[13] = { 110, 100, 90, 80, 70, 65, 65, 65, 80, 90, 80, 90, 90}; +SECT_VEH_CAL_3 const tS16 c_assVR_MIN_LV3_Suv[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_3 const tS16 c_assVR_MAX_LV3_Suv[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_Y1_LV3_Suv[7] = { 80, 80, 80, 60, -30, -40, -40}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_Y2_LV3_Suv[7] = { 25, 25, 25, 30, 0, -20, -20}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_Y3_LV3_Suv[7] = { 10, 10, 10, 5, 0, 20, 25}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_Y4_LV3_Suv[7] = { 20, 20, 20, 30, 50, 50, 50}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_X1_LV3_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_X2_LV3_Suv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_X3_LV3_Suv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_X4_LV3_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assVR_AMB_Y1_LV3_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVR_AMB_Y2_LV3_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVR_AMB_X1_LV3_Suv[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_3 const tS16 c_assVR_AMB_X2_LV3_Suv[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_3 const tS16 c_assVR_SUN_Y1_LV3_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVR_SUN_Y2_LV3_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVR_SUN_X1_LV3_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assVR_SUN_X2_LV3_Suv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_3 const tS16 c_assTG_RL_LV3_Suv[13] = { 50, 50, 50, 80, 120, 150, 190, 250, 350, 370, 450, 500, 600}; +SECT_VEH_CAL_3 const tS16 c_assTG_RR_LV3_Suv[13] = { 50, 50, 50, 80, 120, 150, 190, 250, 350, 370, 450, 500, 600}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_MIN_LV3_Suv[7] = { 51, 51, 51, 51, 51, 51, 51}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_MAX_LV3_Suv[7] = { 400, 400, 450, 650, 800, 800, 800}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_Y1_LV3_Suv[7] = { -100, -100, -100, -100, -100, -100, -250}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_Y2_LV3_Suv[7] = { -50, -50, -50, -50, -50, -80, -100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_Y3_LV3_Suv[7] = { 50, 50, 50, 50, 80, 80, 80}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_Y4_LV3_Suv[7] = { 250, 250, 250, 350, 450, 450, 450}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_X1_LV3_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_X2_LV3_Suv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_X3_LV3_Suv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_X4_LV3_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_AMB_Y1_LV3_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_AMB_Y2_LV3_Suv[7] = { 10, 20, 30, 50, 60, 70, 80}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_AMB_X1_LV3_Suv[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_AMB_X2_LV3_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_SUN_Y1_LV3_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_SUN_Y2_LV3_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_SUN_X1_LV3_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_SUN_X2_LV3_Suv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_DUCT_TIME_FR_LV3_Suv[7] = { 3600, 3600, 3600, 3600, 3600, 3600, 3600}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_DUCT_TIME_FL_LV3_Suv[7] = { 3600, 3600, 3600, 3600, 3600, 3600, 3600}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_DUCT_RATE_LV3_Suv[7] = { 5, 5, 5, 1, 1, 1, 1}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_DUCT_MAX_LV3_Suv[7] = { 800, 800, 800, 800, 700, 600, 500}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_AF_TIME_FR_LV3_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_AF_TIME_FL_LV3_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_AF_RATE_LV3_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_AF_MAX_LV3_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +/* ------------------------------------------Lv3 : End*/ +SECT_VEH_CAL_3 const tS16 c_assINCAR_TG_FL_LV4_Suv[13] = { 180, 190, 200, 210, 230, 250, 265, 270, 275, 285, 290, 295, 320}; +SECT_VEH_CAL_3 const tS16 c_assINCAR_TG_FR_LV4_Suv[13] = { 180, 190, 200, 210, 230, 250, 265, 270, 275, 285, 290, 295, 320}; +SECT_VEH_CAL_3 const tS16 c_assVTG_FL_LV4_Suv[13] = { 90, 83, 75, 62, 55, 60, 70, 70, 75, 78, 91, 93, 100}; +SECT_VEH_CAL_3 const tS16 c_assVTG_FR_LV4_Suv[13] = { 90, 83, 75, 62, 55, 60, 70, 70, 75, 78, 91, 93, 100}; +SECT_VEH_CAL_3 const tS16 c_assVF_MIN_LV4_Suv[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_3 const tS16 c_assVF_MAX_LV4_Suv[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_Y1_LV4_Suv[7] = { 15, 15, 25, 25, 0, -15, -20}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_Y2_LV4_Suv[7] = { 5, 10, 15, 0, 0, -10, -15}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_Y3_LV4_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_Y4_LV4_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_X1_LV4_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_X2_LV4_Suv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_X3_LV4_Suv[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_X4_LV4_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assVF_AMB_Y1_LV4_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVF_AMB_Y2_LV4_Suv[7] = { 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_3 const tS16 c_assVF_AMB_X1_LV4_Suv[7] = { -10, -10, -10, -10, -10, -10, -10}; +SECT_VEH_CAL_3 const tS16 c_assVF_AMB_X2_LV4_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assVF_SUN_Y1_LV4_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVF_SUN_Y2_LV4_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVF_SUN_X1_LV4_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assVF_SUN_X2_LV4_Suv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_3 const tS16 c_assTG_FLU_LV4_Suv[13] = { 300, 50, 150, 200, 220, 330, 410, 420, 430, 450, 470, 490, 520}; +SECT_VEH_CAL_3 const tS16 c_assTG_FRU_LV4_Suv[13] = { 50, 50, 150, 200, 220, 325, 400, 410, 418, 425, 450, 475, 500}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_MIN_LV4_Suv[7] = { 20, 20, 20, 30, 200, 200, 250}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_MAX_LV4_Suv[7] = { 450, 450, 550, 800, 800, 800, 800}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_Y1_LV4_Suv[7] = { -100, -100, -150, -180, -200, -300, -350}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_Y2_LV4_Suv[7] = { -30, -30, -70, -80, -65, -65, -65}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_Y3_LV4_Suv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_Y4_LV4_Suv[7] = { 200, 200, 200, 100, 70, 60, 50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_X1_LV4_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_X2_LV4_Suv[7] = { -20, -20, -20, -30, -30, -20, -20}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_X3_LV4_Suv[7] = { 20, 20, 20, 35, 30, 30, 30}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_X4_LV4_Suv[7] = { 100, 100, 100, 100, 60, 30, 30}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_AMB_Y1_LV4_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_AMB_Y2_LV4_Suv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_AMB_X1_LV4_Suv[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_AMB_X2_LV4_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_SUN_Y1_LV4_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_SUN_Y2_LV4_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_SUN_X1_LV4_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_SUN_X2_LV4_Suv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_3 const tS16 c_assTG_FLL_LV4_Suv[13] = { 400, 450, 450, 500, 580, 625, 720, 750, 750, 750, 770, 800, 850}; +SECT_VEH_CAL_3 const tS16 c_assTG_FRL_LV4_Suv[13] = { 400, 450, 450, 500, 550, 625, 700, 720, 725, 730, 750, 780, 850}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_MIN_LV4_Suv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_MAX_LV4_Suv[7] = { 600, 600, 800, 800, 800, 900, 900}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_Y1_LV4_Suv[7] = { -100, -100, -100, -50, -60, -150, -200}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_Y2_LV4_Suv[7] = { -50, -50, -50, -20, -20, -50, -80}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_Y3_LV4_Suv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_Y4_LV4_Suv[7] = { 400, 400, 400, 400, 200, 200, 200}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_X1_LV4_Suv[7] = { -100, -100, -100, -100, -100, -200, -150}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_X2_LV4_Suv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_X3_LV4_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_X4_LV4_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_AMB_Y1_LV4_Suv[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_AMB_Y2_LV4_Suv[7] = { 50, 50, 50, 50, 60, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_AMB_X1_LV4_Suv[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_AMB_X2_LV4_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_SUN_Y1_LV4_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_SUN_Y2_LV4_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_SUN_X1_LV4_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_SUN_X2_LV4_Suv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_3 const tS16 c_assINCAR_TG_RL_LV4_Suv[13] = { 190, 195, 200, 215, 230, 240, 250, 255, 260, 265, 270, 280, 300}; +SECT_VEH_CAL_3 const tS16 c_assINCAR_TG_RR_LV4_Suv[13] = { 190, 195, 200, 215, 230, 240, 250, 255, 260, 265, 270, 280, 300}; +SECT_VEH_CAL_3 const tS16 c_assVTG_RL_LV4_Suv[13] = { 110, 100, 90, 85, 80, 75, 75, 75, 80, 85, 90, 90, 90}; +SECT_VEH_CAL_3 const tS16 c_assVTG_RR_LV4_Suv[13] = { 110, 100, 90, 85, 80, 75, 75, 75, 80, 85, 90, 90, 90}; +SECT_VEH_CAL_3 const tS16 c_assVR_MIN_LV4_Suv[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_3 const tS16 c_assVR_MAX_LV4_Suv[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_Y1_LV4_Suv[7] = { 60, 50, 40, -15, -40, -40, -40}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_Y2_LV4_Suv[7] = { 30, 40, 40, 0, -30, -20, -20}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_Y3_LV4_Suv[7] = { 10, 10, 10, 5, 30, 30, 30}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_Y4_LV4_Suv[7] = { 20, 50, 70, 100, 100, 80, 80}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_X1_LV4_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_X2_LV4_Suv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_X3_LV4_Suv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_X4_LV4_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assVR_AMB_Y1_LV4_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVR_AMB_Y2_LV4_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVR_AMB_X1_LV4_Suv[7] = { -10, -10, -10, -10, -10, -10, -10}; +SECT_VEH_CAL_3 const tS16 c_assVR_AMB_X2_LV4_Suv[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_3 const tS16 c_assVR_SUN_Y1_LV4_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVR_SUN_Y2_LV4_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVR_SUN_X1_LV4_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assVR_SUN_X2_LV4_Suv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_3 const tS16 c_assTG_RL_LV4_Suv[13] = { 50, 50, 50, 80, 90, 120, 170, 240, 320, 390, 430, 450, 500}; +SECT_VEH_CAL_3 const tS16 c_assTG_RR_LV4_Suv[13] = { 50, 50, 50, 80, 90, 120, 170, 240, 320, 390, 430, 450, 500}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_MIN_LV4_Suv[7] = { 51, 51, 51, 51, 51, 51, 51}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_MAX_LV4_Suv[7] = { 400, 400, 450, 650, 800, 800, 800}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_Y1_LV4_Suv[7] = { -100, -100, -100, -110, -250, -300, -350}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_Y2_LV4_Suv[7] = { -50, -50, -50, -80, -150, -150, -150}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_Y3_LV4_Suv[7] = { 50, 50, 50, 60, 80, 80, 120}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_Y4_LV4_Suv[7] = { 300, 250, 250, 350, 450, 500, 500}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_X1_LV4_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_X2_LV4_Suv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_X3_LV4_Suv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_X4_LV4_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_AMB_Y1_LV4_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_AMB_Y2_LV4_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_AMB_X1_LV4_Suv[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_AMB_X2_LV4_Suv[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_SUN_Y1_LV4_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_SUN_Y2_LV4_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_SUN_X1_LV4_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_SUN_X2_LV4_Suv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_DUCT_TIME_FR_LV4_Suv[7] = { 3600, 3600, 3600, 3600, 3600, 3600, 3600}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_DUCT_TIME_FL_LV4_Suv[7] = { 3600, 3600, 3600, 3600, 3600, 3600, 3600}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_DUCT_RATE_LV4_Suv[7] = { 5, 5, 5, 1, 1, 1, 1}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_DUCT_MAX_LV4_Suv[7] = { 500, 500, 500, 800, 700, 600, 500}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_AF_TIME_FR_LV4_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_AF_TIME_FL_LV4_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_AF_RATE_LV4_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_AF_MAX_LV4_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +/* ------------------------------------------Lv4 : End*/ +SECT_VEH_CAL_3 const tS16 c_assINCAR_TG_FL_LV5_Suv[13] = { 180, 190, 200, 210, 230, 235, 240, 250, 270, 290, 310, 330, 350}; +SECT_VEH_CAL_3 const tS16 c_assINCAR_TG_FR_LV5_Suv[13] = { 180, 190, 200, 210, 230, 235, 240, 250, 270, 290, 310, 330, 350}; +SECT_VEH_CAL_3 const tS16 c_assVTG_FL_LV5_Suv[13] = { 90, 83, 75, 62, 55, 55, 70, 70, 75, 78, 91, 93, 95}; +SECT_VEH_CAL_3 const tS16 c_assVTG_FR_LV5_Suv[13] = { 90, 83, 75, 62, 55, 55, 70, 70, 75, 78, 91, 93, 95}; +SECT_VEH_CAL_3 const tS16 c_assVF_MIN_LV5_Suv[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_3 const tS16 c_assVF_MAX_LV5_Suv[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_Y1_LV5_Suv[7] = { 15, 15, 25, 25, 0, -15, -20}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_Y2_LV5_Suv[7] = { 5, 10, 15, 0, 0, -10, -15}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_Y3_LV5_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_Y4_LV5_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_X1_LV5_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_X2_LV5_Suv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_X3_LV5_Suv[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_3 const tS16 c_assVF_INC_X4_LV5_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assVF_AMB_Y1_LV5_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVF_AMB_Y2_LV5_Suv[7] = { 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_3 const tS16 c_assVF_AMB_X1_LV5_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assVF_AMB_X2_LV5_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assVF_SUN_Y1_LV5_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVF_SUN_Y2_LV5_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVF_SUN_X1_LV5_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assVF_SUN_X2_LV5_Suv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_3 const tS16 c_assTG_FLU_LV5_Suv[13] = { 50, 70, 150, 220, 250, 350, 420, 450, 480, 500, 525, 550, 600}; +SECT_VEH_CAL_3 const tS16 c_assTG_FRU_LV5_Suv[13] = { 50, 70, 150, 220, 250, 350, 420, 450, 480, 500, 525, 550, 600}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_MIN_LV5_Suv[7] = { 20, 20, 20, 30, 200, 200, 250}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_MAX_LV5_Suv[7] = { 450, 450, 550, 800, 800, 800, 800}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_Y1_LV5_Suv[7] = { -100, -100, -150, -180, -200, -300, -350}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_Y2_LV5_Suv[7] = { -30, -30, -70, -80, -65, -65, -65}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_Y3_LV5_Suv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_Y4_LV5_Suv[7] = { 200, 200, 200, 100, 70, 60, 50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_X1_LV5_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_X2_LV5_Suv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_X3_LV5_Suv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_INC_X4_LV5_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_AMB_Y1_LV5_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_AMB_Y2_LV5_Suv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_AMB_X1_LV5_Suv[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_AMB_X2_LV5_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_SUN_Y1_LV5_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_SUN_Y2_LV5_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_SUN_X1_LV5_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FU_SUN_X2_LV5_Suv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_3 const tS16 c_assTG_FLL_LV5_Suv[13] = { 400, 450, 480, 500, 580, 625, 720, 750, 750, 750, 800, 850, 900}; +SECT_VEH_CAL_3 const tS16 c_assTG_FRL_LV5_Suv[13] = { 400, 450, 480, 500, 580, 625, 720, 750, 750, 750, 800, 850, 900}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_MIN_LV5_Suv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_MAX_LV5_Suv[7] = { 600, 600, 800, 800, 800, 800, 800}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_Y1_LV5_Suv[7] = { -100, -100, -100, -50, -60, -150, -200}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_Y2_LV5_Suv[7] = { -50, -50, -50, -20, -20, -50, -80}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_Y3_LV5_Suv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_Y4_LV5_Suv[7] = { 400, 400, 400, 400, 200, 200, 200}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_X1_LV5_Suv[7] = { -100, -100, -100, -100, -100, -200, -150}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_X2_LV5_Suv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_X3_LV5_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_INC_X4_LV5_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_AMB_Y1_LV5_Suv[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_AMB_Y2_LV5_Suv[7] = { 50, 50, 50, 50, 60, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_AMB_X1_LV5_Suv[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_AMB_X2_LV5_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_SUN_Y1_LV5_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_SUN_Y2_LV5_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_SUN_X1_LV5_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assDTG_FL_SUN_X2_LV5_Suv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_3 const tS16 c_assINCAR_TG_RL_LV5_Suv[13] = { 190, 195, 200, 215, 230, 235, 240, 260, 270, 285, 300, 310, 320}; +SECT_VEH_CAL_3 const tS16 c_assINCAR_TG_RR_LV5_Suv[13] = { 190, 195, 200, 215, 230, 235, 240, 260, 270, 285, 300, 310, 320}; +SECT_VEH_CAL_3 const tS16 c_assVTG_RL_LV5_Suv[13] = { 110, 100, 90, 80, 70, 65, 65, 65, 80, 90, 80, 90, 90}; +SECT_VEH_CAL_3 const tS16 c_assVTG_RR_LV5_Suv[13] = { 110, 100, 90, 80, 70, 65, 65, 65, 80, 90, 80, 90, 90}; +SECT_VEH_CAL_3 const tS16 c_assVR_MIN_LV5_Suv[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_3 const tS16 c_assVR_MAX_LV5_Suv[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_Y1_LV5_Suv[7] = { 80, 80, 80, 60, 60, 60, 60}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_Y2_LV5_Suv[7] = { 25, 25, 25, 30, 10, 10, 10}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_Y3_LV5_Suv[7] = { -10, -10, -10, 0, 0, 20, 25}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_Y4_LV5_Suv[7] = { 20, 20, 20, 30, 50, 50, 50}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_X1_LV5_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_X2_LV5_Suv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_X3_LV5_Suv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_3 const tS16 c_assVR_INC_X4_LV5_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assVR_AMB_Y1_LV5_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVR_AMB_Y2_LV5_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVR_AMB_X1_LV5_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assVR_AMB_X2_LV5_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assVR_SUN_Y1_LV5_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVR_SUN_Y2_LV5_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assVR_SUN_X1_LV5_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assVR_SUN_X2_LV5_Suv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_3 const tS16 c_assTG_RL_LV5_Suv[13] = { 50, 50, 50, 80, 120, 150, 170, 250, 350, 370, 450, 500, 500}; +SECT_VEH_CAL_3 const tS16 c_assTG_RR_LV5_Suv[13] = { 50, 50, 50, 80, 120, 150, 170, 250, 350, 370, 450, 500, 500}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_MIN_LV5_Suv[7] = { 51, 51, 51, 51, 51, 51, 51}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_MAX_LV5_Suv[7] = { 400, 400, 450, 650, 800, 800, 800}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_Y1_LV5_Suv[7] = { -100, -100, -100, -100, -100, -100, -250}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_Y2_LV5_Suv[7] = { -50, -50, -50, -50, -50, -80, -100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_Y3_LV5_Suv[7] = { 50, 50, 50, 50, 80, 80, 80}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_Y4_LV5_Suv[7] = { 250, 250, 250, 350, 450, 450, 450}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_X1_LV5_Suv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_X2_LV5_Suv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_X3_LV5_Suv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_INC_X4_LV5_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_AMB_Y1_LV5_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_AMB_Y2_LV5_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_AMB_X1_LV5_Suv[7] = { -10, -10, -10, -10, -10, -10, -10}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_AMB_X2_LV5_Suv[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_SUN_Y1_LV5_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_SUN_Y2_LV5_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_SUN_X1_LV5_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assDTG_R_SUN_X2_LV5_Suv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_DUCT_TIME_FR_LV5_Suv[7] = { 3600, 3600, 3600, 3600, 3600, 3600, 3600}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_DUCT_TIME_FL_LV5_Suv[7] = { 3600, 3600, 3600, 3600, 3600, 3600, 3600}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_DUCT_RATE_LV5_Suv[7] = { 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_DUCT_MAX_LV5_Suv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_AF_TIME_FR_LV5_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_AF_TIME_FL_LV5_Suv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_AF_RATE_LV5_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assCORRECT_AF_MAX_LV5_Suv[7] = { 0, 0, 0, 0, 0, 0, 0}; +/* ------------------------------------------Lv5 : End*/ +SECT_VEH_CAL_3 const tS16 c_assDUCT_TGT_DEF_VALVE_L_Suv[11] = { 350, 300, 300, 250, 200, 150, 120, 100, 70, 50, 50}; +SECT_VEH_CAL_3 const tS16 c_assDUCT_TGT_DEF_VALVE_R_Suv[11] = { 350, 300, 300, 250, 200, 150, 120, 100, 70, 50, 50}; +/* ------------------------------------------DuctTgt Increase : End*/ +SECT_VEH_CAL_3 const tS16 c_assAMB_LV_UP_Suv[5] = { 350, 200, 50, -150, -300}; +SECT_VEH_CAL_3 const tS16 c_assAMB_LV_DN_Suv[5] = { 400, 250, 100, -100, -250}; +SECT_VEH_CAL_3 const tS16 c_assAMB_LV_TG_Suv[6] = { 450, 350, 200, 0, -150, -350}; +/* ------------------------------------------Ambient LEVEL : End*/ +SECT_VEH_CAL_3 const tU08 c_aucMODE_BY_SET_F_LV0_Suv[13] = { 30, 30, 30, 30, 20, 20, 20, 20, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_3 const tU08 c_aucMODE_BY_SET_F_LV1_Suv[13] = { 30, 30, 30, 30, 20, 20, 20, 20, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_3 const tU08 c_aucMODE_BY_SET_F_LV2_Suv[13] = { 30, 30, 30, 20, 20, 20, 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_3 const tU08 c_aucMODE_BY_SET_F_LV3_Suv[13] = { 20, 20, 20, 20, 20, 20, 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_3 const tU08 c_aucMODE_BY_SET_F_LV4_Suv[13] = { 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_3 const tU08 c_aucMODE_BY_SET_F_LV5_Suv[13] = { 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_3 const tU16 c_ausMODE_BY_DUCT_TG_R_LV0_Suv[7] = { 250, 300, 450, 550, 120, 150, 180}; +SECT_VEH_CAL_3 const tU16 c_ausMODE_BY_DUCT_TG_R_LV1_Suv[7] = { 250, 300, 450, 550, 120, 150, 180}; +SECT_VEH_CAL_3 const tU16 c_ausMODE_BY_DUCT_TG_R_LV2_Suv[7] = { 250, 300, 450, 550, 120, 150, 180}; +SECT_VEH_CAL_3 const tU16 c_ausMODE_BY_DUCT_TG_R_LV3_Suv[7] = { 250, 300, 450, 550, 120, 150, 180}; +SECT_VEH_CAL_3 const tU16 c_ausMODE_BY_DUCT_TG_R_LV4_Suv[7] = { 250, 300, 450, 550, 120, 150, 180}; +SECT_VEH_CAL_3 const tU16 c_ausMODE_BY_DUCT_TG_R_LV5_Suv[7] = { 250, 300, 450, 550, 120, 150, 180}; +/* ------------------------------------------Mode depend on SET for each level : End*/ +SECT_VEH_CAL_3 const tS16 c_ssPREC_REC_ON_AMB_Suv = 340; +SECT_VEH_CAL_3 const tS16 c_ssPREC_REC_OFF_AMB_Suv = 320; +SECT_VEH_CAL_3 const tU08 c_aucPREC_VEH_SPD_OSA_Suv[13] = { 100, 95, 92, 86, 83, 80, 75, 70, 65, 60, 55, 52, 50}; +SECT_VEH_CAL_3 const tS16 c_assPRE_AMB_RANGE_WINTER_Suv[7] = { -450, -300, -200, -150, -80, 0, 50}; +SECT_VEH_CAL_3 const tU08 c_aucPREC_OSA_WINTER_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tU08 c_aucPREC_REC_WINTER_Suv[7] = { 15, 13, 10, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tU16 c_ausPREC_HUMIDITY_NOK_Suv[7] = { 900, 900, 900, 900, 900, 900, 900}; +SECT_VEH_CAL_3 const tU16 c_ausPREC_HUMIDITY_OK_Suv[7] = { 700, 700, 700, 700, 700, 700, 700}; +SECT_VEH_CAL_3 const tU16 c_ausPREC_ENTRY_RPM_Suv[3] = { 450, 650, 800}; +SECT_VEH_CAL_3 const tU16 c_ausPREC_EXIT_RPM_Suv[3] = { 450, 550, 800}; +SECT_VEH_CAL_3 const tU16 c_ausPREC_COMP_SPD_1_Suv[3] = { 450, 500, 550}; +SECT_VEH_CAL_3 const tU08 c_aucPREC_OSA_SUMMER_1_Suv[3] = { 80, 70, 60}; +SECT_VEH_CAL_3 const tU08 c_aucPREC_REC_SUMMER_1_Suv[3] = { 20, 30, 45}; +SECT_VEH_CAL_3 const tS16 c_assPREC_EVA_DIFF_FB_TG_F_Suv[7] = { 0, 5, 10, 15, 20, 25, 30}; +SECT_VEH_CAL_3 const tU08 c_aucPREC_OSA_SUMMER_2_Suv[7] = { 50, 45, 40, 35, 30, 25, 20}; +SECT_VEH_CAL_3 const tU08 c_aucPREC_REC_SUMMER_2_Suv[7] = { 50, 55, 60, 65, 70, 75, 80}; +SECT_VEH_CAL_3 const tU08 c_aucPREC_EVA_DIFF_Suv[4] = { 80, 80, 50, 50}; +SECT_VEH_CAL_3 const tU08 c_ucPREC_OSA_SUMMER_3_Suv = 0; +SECT_VEH_CAL_3 const tU08 c_ucPREC_REC_SUMMER_3_Suv = 100; +/* ------------------------------------------AutoRec : End*/ +SECT_VEH_CAL_3 const tU16 c_ausFLOW_FR_VE2VALVE_Suv[9] = { 100, 100, 100, 100, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tU16 c_ausFLOW_FR_BIVALVE_Suv[9] = { 40, 40, 40, 40, 30, 0, 30, 0, 0}; +SECT_VEH_CAL_3 const tU16 c_ausFLOW_FR_BI2VALVE_Suv[9] = { 70, 70, 70, 70, 30, 0, 30, 0, 0}; +SECT_VEH_CAL_3 const tU16 c_ausFLOW_FR_AF2VALVE_Suv[9] = { 30, 25, 25, 30, 30, 0, 30, 0, 0}; +SECT_VEH_CAL_3 const tU16 c_ausFLOW_FR_AF2VALVE_SUMMER_Suv[9] = { 25, 25, 25, 25, 30, 0, 30, 0, 10}; +SECT_VEH_CAL_3 const tU16 c_ausFLOW_FR_FO2VALVE_Suv[9] = { 0, 0, 0, 0, 100, 0, 100, 0, 0}; +SECT_VEH_CAL_3 const tU16 c_ausFLOW_FR_FD2VALVE_Suv[9] = { 0, 0, 0, 0, 100, 0, 100, 0, 100}; +SECT_VEH_CAL_3 const tU16 c_ausFLOW_FR_DE2VALVE_Suv[9] = { 0, 0, 0, 0, 10, 0, 10, 0, 100}; +SECT_VEH_CAL_3 const tU16 c_ausFLOW_FR_TR2VALVE_Suv[9] = { 55, 55, 55, 55, 100, 0, 100, 0, 100}; +SECT_VEH_CAL_3 const tU16 c_ausFLOW_FR_HI2VALVE_Suv[9] = { 50, 50, 50, 50, 0, 0, 0, 0, 100}; +SECT_VEH_CAL_3 const tU16 c_ausFLOW_FR_BIVALVE_MANUAL_Suv[9] = { 50, 50, 50, 50, 60, 0, 60, 0, 0}; +SECT_VEH_CAL_3 const tU16 c_ausFLOW_RE_VENT_Suv[6] = { 70, 80, 80, 70, 0, 0}; +SECT_VEH_CAL_3 const tU16 c_ausFLOW_RE_BI2VALVE_Suv[6] = { 70, 80, 80, 70, 100, 100}; +SECT_VEH_CAL_3 const tU16 c_ausFLOW_RE_FO2VALVE_Suv[6] = { 0, 20, 20, 0, 100, 100}; +SECT_VEH_CAL_3 const tU16 c_ausFLOW_RE_VENT_2_Suv[6] = { 30, 60, 60, 30, 50, 50}; +SECT_VEH_CAL_3 const tU16 c_ausFLOW_RE_BI2VALVE_2_Suv[6] = { 50, 30, 30, 50, 100, 100}; +SECT_VEH_CAL_3 const tU16 c_ausFLOW_RE_VENT_3_Suv[6] = { 70, 80, 80, 70, 0, 0}; +SECT_VEH_CAL_3 const tU16 c_ausFLOW_RE_BI2VALVE_3_Suv[6] = { 20, 20, 20, 20, 100, 100}; +SECT_VEH_CAL_3 const tU16 c_ausFLOW_RE_VENT_MANUAL_Suv[6] = { 70, 80, 80, 70, 0, 0}; +SECT_VEH_CAL_3 const tU16 c_ausFLOW_RE_BI2VALVE_MANUAL_Suv[6] = { 70, 40, 40, 70, 100, 100}; +/* ------------------------------------------Flow Control Valve: End*/ +SECT_VEH_CAL_3 const tS16 c_assFLOW_BI_AMB_TGT_Suv[6] = { 450, 350, 200, 0, -150, -350}; +SECT_VEH_CAL_3 const tU08 c_aucFLOW_BI_VENT_PLUS_Suv[12] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_3 const tS16 c_assFLOW_BI_TEMP_TGT_Suv[12] = { 300, 350, 400, 450, 500, 550, 300, 350, 400, 450, 500, 550}; +SECT_VEH_CAL_3 const tU08 c_aucFLOW_BI_FOOT_PLUS_Suv[12] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_3 const tU08 c_aucFLOW_BI_VENT_VALVE_MAX_Suv[12] = { 85, 85, 85, 85, 85, 85, 60, 60, 60, 60, 60, 60}; +SECT_VEH_CAL_3 const tU08 c_aucFLOW_BI_FOOT_VALVE_MAX_Suv[12] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tU08 c_aucFLOW_BI_VENT_VALVE_MIN_Suv[12] = { 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_3 const tU08 c_aucFLOW_BI_FOOT_VALVE_MIN_Suv[12] = { 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}; +/* ------------------------------------------Bi 2 level conditions: End*/ +SECT_VEH_CAL_3 const tS16 c_assFLOW_B2I_AMB_TGT_Suv[6] = { 450, 350, 200, 0, -150, -350}; +SECT_VEH_CAL_3 const tU08 c_aucFLOW_BI2_VENT_PLUS_Suv[12] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_3 const tS16 c_assFLOW_BI2_TEMP_TGT_Suv[12] = { 300, 350, 400, 450, 500, 550, 300, 350, 400, 450, 500, 550}; +SECT_VEH_CAL_3 const tU08 c_aucFLOW_BI2_FOOT_PLUS_Suv[12] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_3 const tU08 c_aucFLOW_BI2_VENT_VALVE_MAX_Suv[12] = { 85, 85, 85, 85, 85, 85, 80, 80, 80, 80, 80, 80}; +SECT_VEH_CAL_3 const tU08 c_aucFLOW_BI2_FOOT_VALVE_MAX_Suv[12] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tU08 c_aucFLOW_BI2_VENT_VALVE_MIN_Suv[12] = { 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_3 const tU08 c_aucFLOW_BI2_FOOT_VALVE_MIN_Suv[12] = { 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}; +/* ------------------------------------------AF level conditions: End*/ +SECT_VEH_CAL_3 const tS16 c_assFLOW_AF_AMB_TGT_Suv[6] = { 450, 350, 200, 0, -150, -350}; +SECT_VEH_CAL_3 const tU08 c_aucFLOW_AF_VENT_PLUS_Suv[12] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2}; +SECT_VEH_CAL_3 const tU08 c_aucFLOW_AF_BLR_AF_TGT_Suv[6] = { 60, 60, 60, 65, 65, 60}; +SECT_VEH_CAL_3 const tU08 c_aucFLOW_AF_FOOT_PLUS_Suv[12] = { 20, 20, 20, 100, 150, 150, 20, 20, 20, 100, 150, 150}; +SECT_VEH_CAL_3 const tU08 c_aucFLOW_AF_VENT_VALVE_MAX_Suv[12] = { 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_3 const tU08 c_aucFLOW_AF_FOOT_VALVE_MAX_Suv[12] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +/* ------------------------------------------AF level conditions: End*/ +SECT_VEH_CAL_3 const tS16 c_assFLOW_AFSM_AMB_TGT_Suv[6] = { 450, 350, 200, 0, -150, -350}; +SECT_VEH_CAL_3 const tU08 c_aucFLOW_AFSM_VENT_PLUS_Suv[12] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_3 const tS16 c_assFLOW_AFSM_TEMP_TGT_Suv[12] = { 300, 350, 400, 450, 500, 550, 300, 350, 400, 450, 500, 550}; +SECT_VEH_CAL_3 const tU08 c_aucFLOW_AFSM_FOOT_PLUS_Suv[12] = { 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_3 const tU08 c_aucFLOW_AFSM_VENT_VALVE_MAX_Suv[12] = { 50, 50, 50, 50, 50, 50, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_3 const tU08 c_aucFLOW_AFSM_FOOT_VALVE_MAX_Suv[12] = { 60, 60, 60, 60, 60, 60, 50, 50, 50, 50, 50, 50}; +/* ------------------------------------------AF_summer level conditions: End*/ +SECT_VEH_CAL_3 const tU08 c_aucMODE_INDEX_Suv[11] = { 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 110}; +SECT_VEH_CAL_3 const tS16 c_assFOOT_STEP_DUCT_TGT_Suv[7] = { -400, -250, -100, 0, 100, 250, 400}; +SECT_VEH_CAL_3 const tS16 c_assBLR_FOOT_IND_Suv[7] = { 25, 10, 5, 0, 5, 10, 25}; +SECT_VEH_CAL_3 const tS08 c_ascFOOT_STEP_VALVE_P1_Suv[11] = { 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_3 const tS08 c_ascFOOT_STEP_VALVE_P2_Suv[11] = { 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25}; +SECT_VEH_CAL_3 const tS08 c_ascFOOT_STEP_VALVE_P3_Suv[11] = { 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_3 const tS08 c_ascFOOT_STEP_VALVE_M1_Suv[11] = { 10, 0, 10, -10, -10, -10, -10, 10, -10, -10, -10}; +SECT_VEH_CAL_3 const tS08 c_ascFOOT_STEP_VALVE_M2_Suv[11] = { 25, 0, 10, -10, -10, -25, -25, 10, -25, -25, -25}; +SECT_VEH_CAL_3 const tS08 c_ascFOOT_STEP_VALVE_M3_Suv[11] = { 40, 0, 10, -15, -15, -40, -40, 10, -40, -40, -25}; +SECT_VEH_CAL_3 const tS16 c_assFOOT_STEP_BLR_P1_Suv[11] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_3 const tS16 c_assFOOT_STEP_BLR_P2_Suv[11] = { 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_3 const tS16 c_assFOOT_STEP_BLR_P3_Suv[11] = { 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 10}; +SECT_VEH_CAL_3 const tS16 c_assFOOT_STEP_BLR_M1_Suv[11] = { 5, 5, 5, -5, -5, -5, -5, 5, -5, -5, -5}; +SECT_VEH_CAL_3 const tS16 c_assFOOT_STEP_BLR_M2_Suv[11] = { 10, 10, 10, -5, -5, -5, -5, 5, -5, -5, -5}; +SECT_VEH_CAL_3 const tS16 c_assFOOT_STEP_BLR_M3_Suv[11] = { 20, 20, 10, -5, -5, -5, -5, 5, -5, -5, -5}; +/* ------------------------------------------Individual foot temperature: End*/ +SECT_VEH_CAL_3 const tU08 c_aucREAR_FOOT_VALVE_AMB_LV2_Suv[13] = { 0, 0, 0, 0, 0, 0, 5, 10, 15, 20, 25, 30, 35}; +SECT_VEH_CAL_3 const tU08 c_aucREAR_FOOT_VALVE_AMB_LV3_Suv[13] = { 0, 0, 0, 0, 0, 0, 5, 10, 15, 20, 25, 30, 35}; +SECT_VEH_CAL_3 const tU08 c_aucREAR_FOOT_VALVE_AMB_LV4_Suv[13] = { 0, 0, 0, 0, 0, 0, 5, 10, 15, 20, 25, 30, 35}; +/* ------------------------------------------Blowing foots from Rear HVAC: End*/ +SECT_VEH_CAL_3 const tU16 c_ausFLOW_FR_VE2BLR_AF_Suv[8] = { 0, 20, 40, 65, 90, 115, 140, 160}; +SECT_VEH_CAL_3 const tU16 c_ausFLOW_FR_BIVALVE_AF_Suv[8] = { 0, 20, 40, 65, 90, 115, 140, 160}; +SECT_VEH_CAL_3 const tU16 c_ausFLOW_FR_BI2BLR_AF_Suv[8] = { 0, 20, 40, 65, 90, 115, 140, 160}; +SECT_VEH_CAL_3 const tU16 c_ausFLOW_FR_FO2BLR_AF_Suv[8] = { 0, 20, 40, 65, 90, 115, 140, 160}; +SECT_VEH_CAL_3 const tU16 c_ausFLOW_FR_AF2VALVE_AF_Suv[8] = { 0, 20, 40, 65, 90, 115, 140, 160}; +SECT_VEH_CAL_3 const tU16 c_ausFLOW_FR_AF2VALVE_SUMMER_AF_Suv[8] = { 0, 20, 40, 65, 90, 115, 140, 160}; +SECT_VEH_CAL_3 const tU16 c_ausFLOW_FR_FD2BLR_AF_Suv[8] = { 0, 20, 40, 65, 90, 115, 140, 160}; +SECT_VEH_CAL_3 const tU16 c_ausFLOW_FR_DE2BLR_AF_Suv[8] = { 0, 20, 40, 65, 90, 115, 140, 160}; +SECT_VEH_CAL_3 const tU16 c_ausFLOW_FR_TR2BLR_AF_Suv[8] = { 0, 20, 40, 65, 90, 115, 140, 160}; +SECT_VEH_CAL_3 const tU16 c_ausFLOW_FR_HI2BLR_AF_Suv[8] = { 0, 20, 40, 65, 90, 115, 140, 160}; +SECT_VEH_CAL_3 const tU16 c_ausFLOW_RE_VE2BLR_AF_Suv[8] = { 0, 20, 40, 65, 90, 115, 140, 160}; +SECT_VEH_CAL_3 const tU16 c_ausFLOW_RE_BI2BLR_AF_Suv[8] = { 0, 20, 40, 65, 90, 115, 140, 160}; +SECT_VEH_CAL_3 const tU16 c_ausFLOW_RE_FO2BLR_AF_Suv[8] = { 0, 20, 40, 65, 90, 115, 140, 160}; +/* ------------------------------------------Flow Control AF: End*/ +SECT_VEH_CAL_3 const tS08 c_ascAUTO_STEP_AF_F_Suv[5] = { -35, -15, 0, 15, 30}; +SECT_VEH_CAL_3 const tS08 c_ascAUTO_STEP_AF_R_Suv[5] = { -35, -15, 0, 15, 30}; +SECT_VEH_CAL_3 const tS16 c_assAUTO_STEP_DUCT_TG_U_F_LV0_1_Suv[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assAUTO_STEP_DUCT_TG_U_F_LV2_3_Suv[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assAUTO_STEP_DUCT_TG_U_F_LV4_5_Suv[10] = { -50, 0, 0, -50, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assAUTO_STEP_DUCT_TG_L_F_LV0_1_Suv[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assAUTO_STEP_DUCT_TG_L_F_LV2_3_Suv[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assAUTO_STEP_DUCT_TG_L_F_LV4_5_Suv[10] = { 50, 50, 0, -128, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assAUTO_STEP_DUCT_TG_R_LV0_1_Suv[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assAUTO_STEP_DUCT_TG_R_LV2_3_Suv[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tS16 c_assAUTO_STEP_DUCT_TG_R_LV4_5_Suv[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +/* ------------------------------------------5 AUTO mode: End*/ +SECT_VEH_CAL_3 const tU16 c_ausVALVE_SPACE_Suv[6] = { 300, 300, 300, 269, 275, 215}; +SECT_VEH_CAL_3 const tU08 c_aucVALVE_SECTION_S1_F_SIDE_VENT_Suv[9] = { 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_3 const tU08 c_aucVALVE_SECTION_S1_F_CENT_VENT_Suv[9] = { 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_3 const tU08 c_aucVALVE_SECTION_S1_F_DRIVER_FOOT_Suv[9] = { 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_3 const tU08 c_aucVALVE_SECTION_S1_F_RIGHT_PASS_Suv[9] = { 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_3 const tU08 c_aucBLR_SPD_V1_1_F_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tU08 c_aucBLR_SPD_K2_1_F_SIDE_VENT_Suv[10] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tU08 c_aucBLR_SPD_K2_2_F_CENT_VENT_Suv[10] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tU08 c_aucBLR_SPD_K2_3_F_DRIVER_FOOT_Suv[10] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tU08 c_aucBLR_SPD_K2_4_F_RIGHT_PASS_Suv[13] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tU16 c_ausVALVE_VEH_SPD_Suv[13] = { 0, 40, 60, 80, 90, 110, 130, 150, 170, 190, 220, 250, 300}; +SECT_VEH_CAL_3 const tU08 c_aucVALVE_VEH_SPD_SIDE_VENT_Suv[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_3 const tU08 c_aucVALVE_VEH_SPD_SIDE_BI_Suv[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_3 const tU08 c_aucVALVE_VEH_SPD_SIDE_AFOOT_Suv[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_3 const tU08 c_aucVALVE_VEH_SPD_CNET_VENT_Suv[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_3 const tU08 c_aucVALVE_VEH_SPD_CENT_BI_Suv[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_3 const tU08 c_aucVALVE_VEH_SPD_CENT_AFOOT_Suv[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_3 const tU08 c_aucVALVE_VEH_SPD_FOOT_BI_Suv[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_3 const tU08 c_aucVALVE_VEH_SPD_FOOT_AFOOT_Suv[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_3 const tU08 c_aucVALVE_VEH_SPD_2FOOT_Suv[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_3 const tU08 c_aucBLR_SPD_VEH_SPD_V1_3_Suv[12] = { 100, 70, 30, 100, 70, 30, 100, 70, 30, 100, 70, 30}; +SECT_VEH_CAL_3 const tU08 c_aucFRONT_SIDE_DRS_PERCENT_Suv[12] = { 100, 70, 30, 100, 70, 30, 100, 70, 30, 100, 70, 30}; +SECT_VEH_CAL_3 const tU08 c_aucFRONT_CENT_DRS_PERCENT_Suv[12] = { 100, 70, 30, 100, 70, 30, 100, 70, 30, 100, 70, 30}; +/* ------------------------------------------Different blower speed FRONT MODE: End*/ +SECT_VEH_CAL_3 const tU08 c_aucVALVE_S1_R_BIPILLAR_Suv[8] = { 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_3 const tU08 c_aucVALVE_S1_R_CENT_VENT_Suv[9] = { 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_3 const tU08 c_aucVALVE_S1_R_FOOT_Suv[5] = { 10, 10, 10, 10, 10}; +SECT_VEH_CAL_3 const tU08 c_aucVALVE_PERC_R_BIPILLAR_Suv[10] = { 10, 20, 30, 40, 50, 60, 70, 80, 90, 100}; +SECT_VEH_CAL_3 const tU08 c_aucVALVE_PERC_R_CENT_VENT_Suv[10] = { 10, 20, 30, 40, 50, 60, 70, 80, 90, 100}; +SECT_VEH_CAL_3 const tU08 c_aucVALVE_PERC_R_FOOT_Suv[10] = { 10, 20, 30, 40, 50, 60, 70, 80, 90, 100}; +SECT_VEH_CAL_3 const tU08 c_aucBLR_SPD_V1_1_R_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tU08 c_aucREAR_CEN_MIN_VALUE_BY_DRS_ZERO_Suv[7] = { 30, 29, 28, 27, 24, 22, 20}; +SECT_VEH_CAL_3 const tU08 c_aucBLR_SPD_K2_1_R_BIPILLAR_MIN_Suv[8] = { 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tU08 c_aucBLR_SPD_K2_2_R_CENT_VENT_MIN_Suv[9] = { 85, 85, 85, 85, 85, 85, 85, 85, 85}; +SECT_VEH_CAL_3 const tU08 c_aucBLR_SPD_K2_3_R_FOOT_MIN_Suv[5] = { 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tU08 c_aucBLR_SPD_K2_1_R_BIPILLAR_MAX_Suv[8] = { 120, 120, 120, 120, 120, 120, 120, 120}; +SECT_VEH_CAL_3 const tU08 c_aucBLR_SPD_K2_2_R_CENT_VENTR_MAX_Suv[9] = { 122, 122, 122, 122, 122, 122, 122, 122, 122}; +SECT_VEH_CAL_3 const tU08 c_aucBLR_SPD_K2_3_R_FOOTR_MAX_Suv[5] = { 130, 130, 130, 130, 130}; +SECT_VEH_CAL_3 const tU08 c_aucREAR_SIDE_DRS_PERCENT_VALVE_Suv[9] = { 100, 70, 30, 100, 70, 30, 100, 70, 30}; +SECT_VEH_CAL_3 const tU08 c_aucREAR_CENT_DRS_PERCENT_VALVE_Suv[9] = { 100, 70, 30, 100, 70, 30, 100, 70, 30}; +SECT_VEH_CAL_3 const tU08 c_aucREAR_SIDE_DRS_PERCENT_AF_Suv[9] = { 100, 70, 30, 100, 70, 30, 100, 70, 30}; +SECT_VEH_CAL_3 const tU08 c_aucREAR_CENT_DRS_PERCENT_AF_Suv[9] = { 100, 70, 30, 100, 70, 30, 100, 70, 30}; +/* ------------------------------------------Different blower speed REAR MODE: End*/ +SECT_VEH_CAL_3 const tU16 c_ausMIN_PWM_Suv[2] = { 150, 150}; +/* ------------------------------------------MinPWM: End*/ +SECT_VEH_CAL_3 const tS16 c_assSTART_ENTER_COOLANT_Suv[6] = { 300, 400, 400, 300, 360, 360}; +SECT_VEH_CAL_3 const tS16 c_assSTART_COOLANT_STEP0_TO_1_Suv[8] = { 0, 400, 400, 400, 300, 400, 400, 400}; +SECT_VEH_CAL_3 const tS16 c_assSTART_COOLANT_TO_STEP2_Suv[3] = { 800, 800, 850}; +SECT_VEH_CAL_3 const tS16 c_assSTART_COOLANT_STEP1_BLR_F_Suv[6] = { 0, 0, 0, 700, 650, 650}; +SECT_VEH_CAL_3 const tS16 c_assSTART_COOLANT_STEP1_BLR_R_Suv[6] = { 0, 0, 700, 600, 600, 600}; +SECT_VEH_CAL_3 const tS16 c_assSTART_ENTER_INCAR_Suv[12] = { 500, 500, 500, 200, 0, 0, 500, 500, 200, 50, 50, 50}; +SECT_VEH_CAL_3 const tU16 c_ausSTART_ENTER_SETTEMP_Suv[12] = { 260, 250, 0, 0, 0, 0, 260, 250, 200, 200, 0, 0}; +SECT_VEH_CAL_3 const tU08 c_aucSTART_INCAR_FLT_UP_Suv[12] = { 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_3 const tU08 c_aucSTART_INCAR_FLT_DN_Suv[12] = { 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_3 const tU08 c_aucSTART_VALVE_IDX_STEP1_Suv[12] = { 10, 10, 10, 70, 70, 70, 120, 120, 140, 140, 140, 140}; +SECT_VEH_CAL_3 const tU08 c_aucSTART_AUTODEMIST2_STEP2_Suv[6] = { 0, 0, 1, 1, 1, 1}; +SECT_VEH_CAL_3 const tU08 c_aucSTART_ELEC_WINDOW_Suv[12] = { 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 1, 1}; +SECT_VEH_CAL_3 const tU16 c_ausSTART_BLR_AF_STEP12_F_Suv[12] = { 160, 160, 120, 60, 60, 60, 140, 140, 100, 140, 140, 140}; +SECT_VEH_CAL_3 const tU16 c_ausSTART_BLR_AF_STEP12_R_Suv[12] = { 160, 160, 60, 60, 60, 60, 140, 140, 100, 140, 140, 140}; +SECT_VEH_CAL_3 const tU16 c_ausSTART_BLR_SPD_STEP2_F_Suv[12] = { 5, 5, 1, 1, 1, 1, 2, 2, 2, 3, 4, 4}; +SECT_VEH_CAL_3 const tU16 c_ausSTART_BLR_SPD_STEP2_R_Suv[12] = { 5, 5, 1, 1, 1, 1, 2, 2, 2, 3, 4, 4}; +SECT_VEH_CAL_3 const tU08 c_aucSTART_DUCT_TGT_STEP2_FX_U_Suv[12] = { 5, 5, 5, 50, 60, 60, 3, 3, 3, 3, 3, 3}; +SECT_VEH_CAL_3 const tU08 c_aucSTART_DUCT_TGT_STEP2_FX_L_Suv[12] = { 15, 15, 15, 80, 80, 80, 6, 6, 6, 20, 30, 30}; +SECT_VEH_CAL_3 const tU08 c_aucSTART_DUCT_TGT_STEP2_RX_Suv[12] = { 5, 5, 30, 60, 60, 80, 3, 3, 3, 6, 6, 6}; +SECT_VEH_CAL_3 const tU08 c_aucSTART_VALVE_CHANGE_SPD_F_Suv[12] = { 1, 1, 1, 1, 1, 1, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_3 const tU08 c_aucSTART_VALVE_CHANGE_SPD_R_Suv[12] = { 1, 1, 1, 1, 1, 1, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_3 const tU16 c_ausSTART_TIME_STEP1_TO_2_Suv[12] = { 300, 180, 180, 1200, 1200, 1800, 300, 180, 1200, 1200, 1800, 1800}; +SECT_VEH_CAL_3 const tU16 c_ausSTART_TIME_STEP2_TO_3_Suv[12] = { 180, 180, 180, 600, 600, 1200, 300, 180, 1200, 1200, 1200, 1200}; +SECT_VEH_CAL_3 const tS16 c_assSTART_INCAR_STEP1_TO_2_Suv[12] = { 350, 350, 300, 200, 230, 250, 350, 350, 200, 230, 240, 250}; +SECT_VEH_CAL_3 const tS16 c_assSTART_INCAR_STEP2_TO_3_Suv[12] = { 300, 300, 250, 250, 250, 280, 220, 220, 220, 220, 250, 270}; +SECT_VEH_CAL_3 const tU08 c_aucSTART_3WAY_OPEN_Suv[12] = { 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1}; +SECT_VEH_CAL_3 const tU08 c_aucSTART_2WAY_OPEN_Suv[12] = { 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1}; +SECT_VEH_CAL_3 const tU08 c_aucSTART_TXV_F_Suv[12] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}; +SECT_VEH_CAL_3 const tU08 c_aucSTART_TXV_R_Suv[12] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}; +/* ------------------------------------------Start control: End*/ +SECT_VEH_CAL_3 const tS16 c_assFAILURE_AMB_TEMP_Suv[13] = { -200, -150, -80, -50, 0, 100, 150, 200, 250, 300, 350, 400, 450}; +SECT_VEH_CAL_3 const tS16 c_assAC_PRESSURE_LOW_HYS_UP_Suv[13] = { 6, 8, 9, 10, 11, 15, 24, 30, 37, 55, 57, 60, 65}; +SECT_VEH_CAL_3 const tS16 c_assAC_PRESSURE_LOW_HYS_DN_Suv[13] = { 5, 7, 8, 9, 10, 12, 15, 25, 25, 30, 30, 30, 40}; +SECT_VEH_CAL_3 const tS16 c_assAC_LOW_AMB_F_Suv[2] = { 50, 70}; +SECT_VEH_CAL_3 const tS16 c_assAC_CUT_OFF_AMB_F_Suv[2] = { -50, -30}; +SECT_VEH_CAL_3 const tS16 c_assAC_WINTER_TXV_DEWPOINT_Suv[2] = { 40, 30}; +SECT_VEH_CAL_3 const tS16 c_assAC_CUT_OFF_AMB_R_Suv[2] = { -220, -210}; +SECT_VEH_CAL_3 const tS16 c_assEVA_TG_AMB_F_Suv[13] = { 100, 100, 80, 80, 80, 60, 50, 40, 30, 30, 25, 25, 25}; +SECT_VEH_CAL_3 const tS16 c_assEVA_TG_AMB_R_Suv[13] = { 100, 100, 80, 80, 80, 60, 50, 40, 30, 30, 25, 25, 25}; +SECT_VEH_CAL_3 const tU08 c_ucAC_EXTRA_RPM_Suv = 15; +SECT_VEH_CAL_3 const tS16 c_assAC_EVA_LV_SHUT_OFF_Suv[2] = { 150, 10}; +SECT_VEH_CAL_3 const tS16 c_assAC_PRESSURE_HYS_HI_ENG_ON_Suv[3] = { 331, 265, 186}; +SECT_VEH_CAL_3 const tU16 c_usCMP_MAX_ENG_OFF_Suv = 3000; +SECT_VEH_CAL_3 const tU08 c_ucFAN_MAX_ENG_OFF_Suv = 15; +SECT_VEH_CAL_3 const tS16 c_ssAC_WINTER_TXV_HYST_Suv = 15; +SECT_VEH_CAL_3 const tU08 c_aucAC_PRESSURE_HYS_HI_ENG_OFF_Suv[2] = { 186, 155}; +SECT_VEH_CAL_3 const tU16 c_ausCMP_RPM_RESONANCE_Suv[6] = { 1500, 1550, 2500, 2560, 7500, 7590}; +/* ------------------------------------------A/C Control Pressure : End*/ +SECT_VEH_CAL_3 const tS16 c_assPRESSURE_TO_FAN_X_Suv[7] = { 50, 70, 90, 100, 174, 184, 240}; +SECT_VEH_CAL_3 const tU08 c_aucPRESSURE_TO_FAN_Y_Suv[7] = { 8, 15, 30, 50, 70, 80, 100}; +/* ------------------------------------------CoolingFan: End*/ +SECT_VEH_CAL_3 const tS16 c_ssREST_BATT_Suv = 109; +SECT_VEH_CAL_3 const tS16 c_ssRESTW_AMB_Suv = 100; +SECT_VEH_CAL_3 const tS16 c_assRESTW_WATER_Suv[2] = { 550, 350}; +SECT_VEH_CAL_3 const tU16 c_usRESTW_READYEXPIRETIME_Suv = 120; +SECT_VEH_CAL_3 const tU08 c_aucRESTW_MODE_Suv[2] = { 70, 130}; +SECT_VEH_CAL_3 const tU16 c_usRESTW_TIMEOUTTIME_Suv = 900; +SECT_VEH_CAL_3 const tU08 c_ucRESTW_BLRSTEP_Suv = 2; +SECT_VEH_CAL_3 const tS16 c_ssRESTS_AMB_Suv = 100; +SECT_VEH_CAL_3 const tU08 c_uctRESTS_READYEXPIRETIME_Suv = 120; +SECT_VEH_CAL_3 const tU08 c_aucRESTS_MODE_Suv[2] = { 70, 130}; +SECT_VEH_CAL_3 const tU16 c_usRESTS_TIMEOUTTIME_Suv = 600; +SECT_VEH_CAL_3 const tU08 c_ucRESTS_BLRSTEP_Suv = 3; +/* ------------------------------------------Rest mode: End*/ +SECT_VEH_CAL_3 const tU16 c_usFRESH_AIR_PURGE_ENTRY_TIME_Suv = 900; +SECT_VEH_CAL_3 const tU16 c_ausFRESH_AIR_PURGE_CHANGE_TIME_Suv[7] = { 10, 10, 10, 50, 10, 10, 10}; +/* ------------------------------------------Purge Rec: End*/ +SECT_VEH_CAL_3 const tS16 c_assMAX_DEF_U_DTG_Suv[10] = { 850, 800, 750, 600, 500, 400, 300, 300, 250, 200}; +SECT_VEH_CAL_3 const tU16 c_ausMAX_BLR_SPD_Suv[6] = { 20, 40, 50, 80, 120, 160}; +/* ------------------------------------------MAX DEF: End*/ +SECT_VEH_CAL_3 const tU08 c_aucAQS_REC_LV_CO_Suv[8] = { 0, 0, 0, 0, 0, 0, 0, 4}; +SECT_VEH_CAL_3 const tU08 c_aucAQS_OSA_LV_CO_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tU08 c_aucAQS_REC_LV_NOX_Suv[8] = { 0, 0, 0, 0, 0, 0, 0, 2}; +SECT_VEH_CAL_3 const tU08 c_aucAQS_OSA_LV_NOX_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tU08 c_aucAQS_REC_LV_NH3_Suv[8] = { 0, 0, 0, 0, 0, 0, 0, 2}; +SECT_VEH_CAL_3 const tU08 c_aucAQS_OSA_LV_NH3_Suv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_3 const tU08 c_ucAQS_REC_ON_TIME_Suv = 30; +SECT_VEH_CAL_3 const tU08 c_aucAQS_REC_ON_WAIT_Suv[2] = { 60, 10}; +/* ------------------------------------------Aqs: End*/ +SECT_VEH_CAL_3 const tU16 c_usAUTODEMIST_LV2_BLR_PLUS_Suv = 10; +SECT_VEH_CAL_3 const tU16 c_usAUTODEMIST_LV3_BLR_PLUS_Suv = 30; +SECT_VEH_CAL_3 const tS16 c_assAUTODEMIST_OFFSET_AMB_TEMP_Suv[9] = { -50, -30, -20, -10, 0, 10, 20, 30, 50}; +SECT_VEH_CAL_3 const tS16 c_assAUTODEMIST_OFFSET_VENT_TEMP_Suv[9] = { 30, 25, 18, 11, 8, 8, 7, 5, 5}; +SECT_VEH_CAL_3 const tS16 c_assAUTODEMIST_STEP_UP_Suv[4] = { 50, 30, 20, -10}; +SECT_VEH_CAL_3 const tS16 c_assAUTODEMIST_STEP_DN_Suv[4] = { 55, 35, 25, 0}; +SECT_VEH_CAL_3 const tS16 c_assAUTODEMIST_WINTER_Suv[2] = { -10, -5}; +/* ------------------------------------------Auto Demist: End*/ +SECT_VEH_CAL_3 const tS16 c_ssAUTODEMIST_ELEC_AMB_ENTRY_Suv = -120; +SECT_VEH_CAL_3 const tS16 c_assAUTODEMIST_ELEC_WINDSHELD_TEMP_Suv[2] = { -100, -60}; +/* ------------------------------------------Electric AutoDemist: End*/ +SECT_VEH_CAL_3 const tS16 c_ssAMBFILT_WATER_Suv = 500; +SECT_VEH_CAL_3 const tU08 c_aucAMBFILT_H_CNT_Suv[2] = { 200, 200}; +SECT_VEH_CAL_3 const tS16 c_ssAMB_FAILSAFE_Suv = 230; +SECT_VEH_CAL_3 const tS16 c_ssAMBKEEP_KAT_Suv = 200; +SECT_VEH_CAL_3 const tS16 c_ssAMBKEEP_KAT_PLUS_Suv = 350; +SECT_VEH_CAL_3 const tS16 c_ssAMBKEEP_WATER_Suv = 500; +SECT_VEH_CAL_3 const tU08 c_aucAMBRATE_RISING_Suv[6] = { 30, 30, 30, 30, 30, 30}; +SECT_VEH_CAL_3 const tU08 c_aucAMBRATE_FALLING_Suv[6] = { 30, 30, 30, 30, 30, 30}; +SECT_VEH_CAL_3 const tU08 c_aucAMBRATE_RISING_DIFF_Suv[8] = { 120, 120, 120, 120, 155, 155, 155, 50}; +SECT_VEH_CAL_3 const tU08 c_aucAMBRATE_FALLING_DIFF_Suv[8] = { 120, 120, 120, 255, 255, 255, 155, 50}; +/* ------------------------------------------Ambient: End*/ +SECT_VEH_CAL_3 const tU16 c_ausINCARRATE_RISING_F_Suv[6] = { 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_3 const tU16 c_ausINCARRATE_FALLING_F_Suv[6] = { 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_3 const tU16 c_ausINCARRATE_RISING_DIFF_F_Suv[8] = { 100, 100, 100, 300, 300, 300, 20, 5}; +SECT_VEH_CAL_3 const tU16 c_ausINCARRATE_FALLING_DIFF_F_Suv[8] = { 100, 100, 100, 300, 300, 300, 20, 5}; +SECT_VEH_CAL_3 const tU16 c_ausINCARRATE_RISING_R_Suv[6] = { 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_3 const tU16 c_ausINCARRATE_FALLING_R_Suv[6] = { 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_3 const tU16 c_ausINCARRATE_RISING_DIFF_R_Suv[8] = { 100, 100, 100, 300, 300, 300, 20, 5}; +SECT_VEH_CAL_3 const tU16 c_ausINCARRATE_FALLING_DIFF_R_Suv[8] = { 100, 100, 100, 300, 300, 300, 20, 5}; +/* ------------------------------------------Incar: End*/ +SECT_VEH_CAL_3 const tU16 c_ausSUNRATE_RISING_Suv[6] = { 2, 2, 2, 2, 2, 2}; +SECT_VEH_CAL_3 const tU16 c_ausSUNRATE_FALLING_Suv[6] = { 2, 2, 2, 2, 2, 2}; +/* ------------------------------------------Sun: End*/ +SECT_VEH_CAL_3 const tU16 c_ausAMB_LV_CHANGE_UNIT_Suv[6] = { 1, 1, 1, 10, 10, 3}; +SECT_VEH_CAL_3 const tU08 c_aucAMB_LV_CHANGE_SEC_Suv[6] = { 1, 1, 1, 1, 1, 1}; +/* ------------------------------------------Level Chage: End*/ +SECT_VEH_CAL_3 const tS16 c_ssTHREEWAY_WATER_Suv = 40; +SECT_VEH_CAL_3 const tS16 c_assTHREEWAY_DUCT_TGT_R_Suv[2] = { 60, 50}; +SECT_VEH_CAL_3 const tU08 c_aucTHEREEWAY_EXPIRING_Suv[2] = { 60, 5}; +/* ------------------------------------------Three way: End*/ +SECT_VEH_CAL_3 const tS16 c_assTWOWAY_REAR_DUCTTGT_R_Suv[2] = { 60, 50}; +SECT_VEH_CAL_3 const tU08 c_aucTWOWAY_EXPIRING_Suv[2] = { 60, 5}; +/* ------------------------------------------two-way: End*/ +SECT_VEH_CAL_3 const tU08 c_aucACT_HOM_SPD_FL_CH0_Suv[9] = { 3, 3, 3, 3, 3, 3, 3, 3, 3}; +SECT_VEH_CAL_3 const tU08 c_aucACT_HOM_SPD_FR_CH1_Suv[6] = { 3, 3, 3, 3, 3, 3}; +SECT_VEH_CAL_3 const tU08 c_aucACT_HOM_SPD_R_CH2_Suv[9] = { 3, 3, 3, 3, 3, 3, 3, 3, 3}; +SECT_VEH_CAL_3 const tU08 c_aucACT_HOM_SPD_R_EX_CH2_Suv[4] = { 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tU08 c_aucACT_MOV_SPD_FL_CH0_Suv[9] = { 3, 3, 3, 3, 3, 3, 3, 3, 3}; +SECT_VEH_CAL_3 const tU08 c_aucACT_MOV_SPD_FR_CH1_Suv[6] = { 3, 3, 3, 3, 3, 3}; +SECT_VEH_CAL_3 const tU08 c_aucACT_MOV_SPD_R_CH2_Suv[9] = { 3, 3, 3, 3, 3, 3, 3, 3, 3}; +SECT_VEH_CAL_3 const tU08 c_aucACT_MOV_SPD_R_EX_CH2_Suv[4] = { 0, 0, 0, 0}; +/* ------------------------------------------Actuator Homing: End*/ +SECT_VEH_CAL_3 const tS16 c_assHI_MODE_ENG_TMEP_Suv[6] = { 35, 45, 60, 80, 100, 120}; +SECT_VEH_CAL_3 const tU08 c_aucHI_MODE_BLR_STEP_STS_Suv[6] = { 2, 3, 4, 5, 100, 100}; +/* ------------------------------------------Hi Mode: End*/ +SECT_VEH_CAL_3 const tU16 c_ausMinusAF_GlassPos_L_Suv[13] = { 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_3 const tU16 c_ausMinusAF_GlassPos_R_Suv[13] = { 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}; +/* ------------------------------------------GlassPosition: End*/ +SECT_VEH_CAL_3 const tS16 c_assFoot2_Lv3_Amb_Suv[6] = { -150, -100, -50, 0, 50, 100}; +SECT_VEH_CAL_3 const tS16 c_assFoot2_Lv4_Amb_Suv[6] = { -150, -100, -50, 0, 50, 100}; +SECT_VEH_CAL_3 const tS16 c_assFoot2_Lv5_Amb_Suv[6] = { -150, -100, -50, 0, 50, 100}; +SECT_VEH_CAL_3 const tS16 c_assFoot2_Lv3_DuctTgt_Plus_Suv[6] = { 500, 500, 450, 400, 350, 300}; +SECT_VEH_CAL_3 const tS16 c_assFoot2_Lv4_DuctTgt_Plus_Suv[6] = { 500, 500, 450, 400, 350, 300}; +SECT_VEH_CAL_3 const tS16 c_assFoot2_Lv5_DuctTgt_Plus_Suv[6] = { 500, 500, 450, 400, 350, 300}; +SECT_VEH_CAL_3 const tU16 c_ausFoot2_Lv1_FrontBlr_X_Suv[3] = { 250, 500, 750}; +SECT_VEH_CAL_3 const tU16 c_ausFoot2_Lv1_Foot2Act_Y_Suv[3] = { 250, 500, 750}; +SECT_VEH_CAL_3 const tS16 c_assFoot2_Lv2_Threshold_Diff_Suv[2] = { 50, 35}; +SECT_VEH_CAL_3 const tS16 c_assFoot2_Lv3_Threshold_Diff_Suv[2] = { 50, 35}; +/* ------------------------------------------Foot2 Ctrl: End*/ +SECT_VEH_CAL_3 const tU16 c_ausDbF_Side_Af_Bi_Suv[9] = { 90, 91, 92, 93, 94, 95, 96, 97, 98}; +SECT_VEH_CAL_3 const tU16 c_ausDbF_Side_Af_Bi2_Suv[9] = { 90, 91, 92, 93, 94, 95, 96, 97, 98}; +SECT_VEH_CAL_3 const tU16 c_ausDbF_Side_Af_Vent_Suv[9] = { 70, 70, 65, 65, 62, 60, 55, 50, 50}; +SECT_VEH_CAL_3 const tU16 c_ausDbF_Side_Bi_Bi2_Suv[9] = { 80, 80, 80, 80, 80, 80, 80, 80, 80}; +SECT_VEH_CAL_3 const tU16 c_ausDbF_Side_Bi_Vent_Suv[9] = { 65, 65, 65, 65, 65, 65, 65, 65, 65}; +SECT_VEH_CAL_3 const tU16 c_ausDbF_Side_Bi2_Vent_Suv[9] = { 80, 80, 80, 80, 80, 80, 80, 80, 80}; +SECT_VEH_CAL_3 const tU16 c_ausDbF_Cen_Af_Bi_Suv[9] = { 90, 91, 92, 93, 94, 95, 96, 97, 98}; +SECT_VEH_CAL_3 const tU16 c_ausDbF_Cen_Af_Bi2_Suv[9] = { 90, 91, 92, 93, 94, 95, 96, 97, 98}; +SECT_VEH_CAL_3 const tU16 c_ausDbF_Cen_Af_Vent_Suv[9] = { 70, 70, 70, 65, 62, 60, 55, 50, 50}; +SECT_VEH_CAL_3 const tU16 c_ausDbF_Cen_Bi_Bi2_Suv[9] = { 80, 80, 80, 80, 80, 80, 80, 80, 80}; +SECT_VEH_CAL_3 const tU16 c_ausDbF_Cen_Bi_Vent_Suv[9] = { 65, 65, 65, 65, 65, 65, 65, 65, 65}; +SECT_VEH_CAL_3 const tU16 c_ausDbF_Cen_Bi2_Vent_Suv[9] = { 80, 80, 80, 80, 80, 80, 80, 80, 80}; +SECT_VEH_CAL_3 const tU16 c_ausDbF_Foot_Af_Bi_Suv[9] = { 90, 91, 92, 93, 94, 95, 96, 97, 98}; +SECT_VEH_CAL_3 const tU16 c_ausDbF_Foot_Af_Bi2_Suv[9] = { 90, 91, 92, 93, 94, 95, 96, 97, 98}; +SECT_VEH_CAL_3 const tU16 c_ausDbF_Foot_Af_Vent_Suv[9] = { 70, 70, 70, 65, 62, 60, 55, 50, 50}; +SECT_VEH_CAL_3 const tU16 c_ausDbF_Foot_Bi_Bi2_Suv[9] = { 80, 80, 80, 80, 80, 80, 80, 80, 80}; +SECT_VEH_CAL_3 const tU16 c_ausDbF_Foot_Bi_Vent_Suv[9] = { 65, 65, 65, 65, 65, 65, 65, 65, 65}; +SECT_VEH_CAL_3 const tU16 c_ausDbF_Foot_Bi2_Vent_Suv[9] = { 80, 80, 80, 80, 80, 80, 80, 80, 80}; +SECT_VEH_CAL_3 const tU16 c_ausDbF_AF_Af_Bi_Suv[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tU16 c_ausDbF_AF_Af_Bi2_Suv[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tU16 c_ausDbF_AF_Af_Vent_Suv[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tU16 c_ausDbF_AF_Bi_Bi2_Suv[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tU16 c_ausDbF_AF_Bi_Vent_Suv[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tU16 c_ausDbF_AF_Bi2_Vent_Suv[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_3 const tU16 c_ausDbF_Pwm_Af_Bi_Suv[9] = { 120, 120, 120, 120, 120, 120, 120, 120, 120}; +SECT_VEH_CAL_3 const tU16 c_ausDbF_Pwm_Af_Bi2_Suv[9] = { 120, 120, 120, 120, 120, 120, 120, 120, 120}; +SECT_VEH_CAL_3 const tU16 c_ausDbF_Pwm_Af_Vent_Suv[9] = { 120, 120, 85, 120, 120, 120, 120, 120, 120}; +SECT_VEH_CAL_3 const tU16 c_ausDbF_Pwm_Bi_Bi2_Suv[9] = { 120, 120, 120, 120, 120, 120, 120, 120, 120}; +SECT_VEH_CAL_3 const tU16 c_ausDbF_Pwm_Bi_Vent_Suv[9] = { 120, 120, 85, 90, 120, 120, 120, 120, 120}; +SECT_VEH_CAL_3 const tU16 c_ausDbF_Pwm_Bi2_Vent_Suv[9] = { 105, 120, 120, 90, 120, 120, 120, 105, 90}; +/* ------------------------------------------Different blower Front: End*/ +SECT_VEH_CAL_3 const tU16 c_usAromaPwm_Min_Suv = 200; +SECT_VEH_CAL_3 const tU16 c_usAromaPwm_Max_Suv = 700; +/* ------------------------------------------Aroma Limit Pwm: End*/ +/*********************************************************Cal Table End*/ + +/****************************************************************************** + * LOCAL VARIABLES DECLARATIONS + *****************************************************************************/ +/****************************************************************************** + * LOCAL FUNCTIONS DECLARATIONS + *****************************************************************************/ +/****************************************************************************** + * GLOBAL FUNCTIONS + *****************************************************************************/ + +/** Doxygen: Function brief + ****************************************************************************** + * @fn Rs_Cal_3_Suv(void) + * @brief No brief + * @remark No description + * @param[in] (All of const data in this file) + * @param[out] All of global variable in Rs_Cal_Base.c + * @return None + *****************************************************************************/ +void Rs_Cal_3_Suv(void) +{ + M_MEMCOPY((g_aucCAL_FP_DATE), (c_aucCAL_FP_DATE_Suv)); + M_MEMCOPY((g_aucCAL_VERSION), (c_aucCAL_VERSION_Suv)); + g_ucCAL_VARIANT = c_ucCAL_VARIANT_Suv; +/* ------------------------------------------Cal Version : End*/ + M_MEMCOPY((g_ausSET_TEMP_FULL), (c_ausSET_TEMP_FULL_Suv)); + M_MEMCOPY((g_ausSET_TEMP_HALF), (c_ausSET_TEMP_HALF_Suv)); +/* ------------------------------------------Set Temp : End*/ + M_MEMCOPY((g_assINCAR_TG_FL_LV0), (c_assINCAR_TG_FL_LV0_Suv)); + M_MEMCOPY((g_assINCAR_TG_FR_LV0), (c_assINCAR_TG_FR_LV0_Suv)); + M_MEMCOPY((g_assVTG_FL_LV0), (c_assVTG_FL_LV0_Suv)); + M_MEMCOPY((g_assVTG_FR_LV0), (c_assVTG_FR_LV0_Suv)); + M_MEMCOPY((g_assVF_MIN_LV0), (c_assVF_MIN_LV0_Suv)); + M_MEMCOPY((g_assVF_MAX_LV0), (c_assVF_MAX_LV0_Suv)); + M_MEMCOPY((g_assVF_INC_Y1_LV0), (c_assVF_INC_Y1_LV0_Suv)); + M_MEMCOPY((g_assVF_INC_Y2_LV0), (c_assVF_INC_Y2_LV0_Suv)); + M_MEMCOPY((g_assVF_INC_Y3_LV0), (c_assVF_INC_Y3_LV0_Suv)); + M_MEMCOPY((g_assVF_INC_Y4_LV0), (c_assVF_INC_Y4_LV0_Suv)); + M_MEMCOPY((g_assVF_INC_X1_LV0), (c_assVF_INC_X1_LV0_Suv)); + M_MEMCOPY((g_assVF_INC_X2_LV0), (c_assVF_INC_X2_LV0_Suv)); + M_MEMCOPY((g_assVF_INC_X3_LV0), (c_assVF_INC_X3_LV0_Suv)); + M_MEMCOPY((g_assVF_INC_X4_LV0), (c_assVF_INC_X4_LV0_Suv)); + M_MEMCOPY((g_assVF_AMB_Y1_LV0), (c_assVF_AMB_Y1_LV0_Suv)); + M_MEMCOPY((g_assVF_AMB_Y2_LV0), (c_assVF_AMB_Y2_LV0_Suv)); + M_MEMCOPY((g_assVF_AMB_X1_LV0), (c_assVF_AMB_X1_LV0_Suv)); + M_MEMCOPY((g_assVF_AMB_X2_LV0), (c_assVF_AMB_X2_LV0_Suv)); + M_MEMCOPY((g_assVF_SUN_Y1_LV0), (c_assVF_SUN_Y1_LV0_Suv)); + M_MEMCOPY((g_assVF_SUN_Y2_LV0), (c_assVF_SUN_Y2_LV0_Suv)); + M_MEMCOPY((g_assVF_SUN_X1_LV0), (c_assVF_SUN_X1_LV0_Suv)); + M_MEMCOPY((g_assVF_SUN_X2_LV0), (c_assVF_SUN_X2_LV0_Suv)); + M_MEMCOPY((g_assTG_FLU_LV0), (c_assTG_FLU_LV0_Suv)); + M_MEMCOPY((g_assTG_FRU_LV0), (c_assTG_FRU_LV0_Suv)); + M_MEMCOPY((g_assDTG_FU_MIN_LV0), (c_assDTG_FU_MIN_LV0_Suv)); + M_MEMCOPY((g_assDTG_FU_MAX_LV0), (c_assDTG_FU_MAX_LV0_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_Y1_LV0), (c_assDTG_FU_INC_Y1_LV0_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_Y2_LV0), (c_assDTG_FU_INC_Y2_LV0_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_Y3_LV0), (c_assDTG_FU_INC_Y3_LV0_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_Y4_LV0), (c_assDTG_FU_INC_Y4_LV0_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_X1_LV0), (c_assDTG_FU_INC_X1_LV0_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_X2_LV0), (c_assDTG_FU_INC_X2_LV0_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_X3_LV0), (c_assDTG_FU_INC_X3_LV0_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_X4_LV0), (c_assDTG_FU_INC_X4_LV0_Suv)); + M_MEMCOPY((g_assDTG_FU_AMB_Y1_LV0), (c_assDTG_FU_AMB_Y1_LV0_Suv)); + M_MEMCOPY((g_assDTG_FU_AMB_Y2_LV0), (c_assDTG_FU_AMB_Y2_LV0_Suv)); + M_MEMCOPY((g_assDTG_FU_AMB_X1_LV0), (c_assDTG_FU_AMB_X1_LV0_Suv)); + M_MEMCOPY((g_assDTG_FU_AMB_X2_LV0), (c_assDTG_FU_AMB_X2_LV0_Suv)); + M_MEMCOPY((g_assDTG_FU_SUN_Y1_LV0), (c_assDTG_FU_SUN_Y1_LV0_Suv)); + M_MEMCOPY((g_assDTG_FU_SUN_Y2_LV0), (c_assDTG_FU_SUN_Y2_LV0_Suv)); + M_MEMCOPY((g_assDTG_FU_SUN_X1_LV0), (c_assDTG_FU_SUN_X1_LV0_Suv)); + M_MEMCOPY((g_assDTG_FU_SUN_X2_LV0), (c_assDTG_FU_SUN_X2_LV0_Suv)); + M_MEMCOPY((g_assTG_FLL_LV0), (c_assTG_FLL_LV0_Suv)); + M_MEMCOPY((g_assTG_FRL_LV0), (c_assTG_FRL_LV0_Suv)); + M_MEMCOPY((g_assDTG_FL_MIN_LV0), (c_assDTG_FL_MIN_LV0_Suv)); + M_MEMCOPY((g_assDTG_FL_MAX_LV0), (c_assDTG_FL_MAX_LV0_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_Y1_LV0), (c_assDTG_FL_INC_Y1_LV0_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_Y2_LV0), (c_assDTG_FL_INC_Y2_LV0_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_Y3_LV0), (c_assDTG_FL_INC_Y3_LV0_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_Y4_LV0), (c_assDTG_FL_INC_Y4_LV0_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_X1_LV0), (c_assDTG_FL_INC_X1_LV0_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_X2_LV0), (c_assDTG_FL_INC_X2_LV0_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_X3_LV0), (c_assDTG_FL_INC_X3_LV0_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_X4_LV0), (c_assDTG_FL_INC_X4_LV0_Suv)); + M_MEMCOPY((g_assDTG_FL_AMB_Y1_LV0), (c_assDTG_FL_AMB_Y1_LV0_Suv)); + M_MEMCOPY((g_assDTG_FL_AMB_Y2_LV0), (c_assDTG_FL_AMB_Y2_LV0_Suv)); + M_MEMCOPY((g_assDTG_FL_AMB_X1_LV0), (c_assDTG_FL_AMB_X1_LV0_Suv)); + M_MEMCOPY((g_assDTG_FL_AMB_X2_LV0), (c_assDTG_FL_AMB_X2_LV0_Suv)); + M_MEMCOPY((g_assDTG_FL_SUN_Y1_LV0), (c_assDTG_FL_SUN_Y1_LV0_Suv)); + M_MEMCOPY((g_assDTG_FL_SUN_Y2_LV0), (c_assDTG_FL_SUN_Y2_LV0_Suv)); + M_MEMCOPY((g_assDTG_FL_SUN_X1_LV0), (c_assDTG_FL_SUN_X1_LV0_Suv)); + M_MEMCOPY((g_assDTG_FL_SUN_X2_LV0), (c_assDTG_FL_SUN_X2_LV0_Suv)); + M_MEMCOPY((g_assINCAR_TG_RL_LV0), (c_assINCAR_TG_RL_LV0_Suv)); + M_MEMCOPY((g_assINCAR_TG_RR_LV0), (c_assINCAR_TG_RR_LV0_Suv)); + M_MEMCOPY((g_assVTG_RL_LV0), (c_assVTG_RL_LV0_Suv)); + M_MEMCOPY((g_assVTG_RR_LV0), (c_assVTG_RR_LV0_Suv)); + M_MEMCOPY((g_assVR_MIN_LV0), (c_assVR_MIN_LV0_Suv)); + M_MEMCOPY((g_assVR_MAX_LV0), (c_assVR_MAX_LV0_Suv)); + M_MEMCOPY((g_assVR_INC_Y1_LV0), (c_assVR_INC_Y1_LV0_Suv)); + M_MEMCOPY((g_assVR_INC_Y2_LV0), (c_assVR_INC_Y2_LV0_Suv)); + M_MEMCOPY((g_assVR_INC_Y3_LV0), (c_assVR_INC_Y3_LV0_Suv)); + M_MEMCOPY((g_assVR_INC_Y4_LV0), (c_assVR_INC_Y4_LV0_Suv)); + M_MEMCOPY((g_assVR_INC_X1_LV0), (c_assVR_INC_X1_LV0_Suv)); + M_MEMCOPY((g_assVR_INC_X2_LV0), (c_assVR_INC_X2_LV0_Suv)); + M_MEMCOPY((g_assVR_INC_X3_LV0), (c_assVR_INC_X3_LV0_Suv)); + M_MEMCOPY((g_assVR_INC_X4_LV0), (c_assVR_INC_X4_LV0_Suv)); + M_MEMCOPY((g_assVR_AMB_Y1_LV0), (c_assVR_AMB_Y1_LV0_Suv)); + M_MEMCOPY((g_assVR_AMB_Y2_LV0), (c_assVR_AMB_Y2_LV0_Suv)); + M_MEMCOPY((g_assVR_AMB_X1_LV0), (c_assVR_AMB_X1_LV0_Suv)); + M_MEMCOPY((g_assVR_AMB_X2_LV0), (c_assVR_AMB_X2_LV0_Suv)); + M_MEMCOPY((g_assVR_SUN_Y1_LV0), (c_assVR_SUN_Y1_LV0_Suv)); + M_MEMCOPY((g_assVR_SUN_Y2_LV0), (c_assVR_SUN_Y2_LV0_Suv)); + M_MEMCOPY((g_assVR_SUN_X1_LV0), (c_assVR_SUN_X1_LV0_Suv)); + M_MEMCOPY((g_assVR_SUN_X2_LV0), (c_assVR_SUN_X2_LV0_Suv)); + M_MEMCOPY((g_assTG_RL_LV0), (c_assTG_RL_LV0_Suv)); + M_MEMCOPY((g_assTG_RR_LV0), (c_assTG_RR_LV0_Suv)); + M_MEMCOPY((g_assDTG_R_MIN_LV0), (c_assDTG_R_MIN_LV0_Suv)); + M_MEMCOPY((g_assDTG_R_MAX_LV0), (c_assDTG_R_MAX_LV0_Suv)); + M_MEMCOPY((g_assDTG_R_INC_Y1_LV0), (c_assDTG_R_INC_Y1_LV0_Suv)); + M_MEMCOPY((g_assDTG_R_INC_Y2_LV0), (c_assDTG_R_INC_Y2_LV0_Suv)); + M_MEMCOPY((g_assDTG_R_INC_Y3_LV0), (c_assDTG_R_INC_Y3_LV0_Suv)); + M_MEMCOPY((g_assDTG_R_INC_Y4_LV0), (c_assDTG_R_INC_Y4_LV0_Suv)); + M_MEMCOPY((g_assDTG_R_INC_X1_LV0), (c_assDTG_R_INC_X1_LV0_Suv)); + M_MEMCOPY((g_assDTG_R_INC_X2_LV0), (c_assDTG_R_INC_X2_LV0_Suv)); + M_MEMCOPY((g_assDTG_R_INC_X3_LV0), (c_assDTG_R_INC_X3_LV0_Suv)); + M_MEMCOPY((g_assDTG_R_INC_X4_LV0), (c_assDTG_R_INC_X4_LV0_Suv)); + M_MEMCOPY((g_assDTG_R_AMB_Y1_LV0), (c_assDTG_R_AMB_Y1_LV0_Suv)); + M_MEMCOPY((g_assDTG_R_AMB_Y2_LV0), (c_assDTG_R_AMB_Y2_LV0_Suv)); + M_MEMCOPY((g_assDTG_R_AMB_X1_LV0), (c_assDTG_R_AMB_X1_LV0_Suv)); + M_MEMCOPY((g_assDTG_R_AMB_X2_LV0), (c_assDTG_R_AMB_X2_LV0_Suv)); + M_MEMCOPY((g_assDTG_R_SUN_Y1_LV0), (c_assDTG_R_SUN_Y1_LV0_Suv)); + M_MEMCOPY((g_assDTG_R_SUN_Y2_LV0), (c_assDTG_R_SUN_Y2_LV0_Suv)); + M_MEMCOPY((g_assDTG_R_SUN_X1_LV0), (c_assDTG_R_SUN_X1_LV0_Suv)); + M_MEMCOPY((g_assDTG_R_SUN_X2_LV0), (c_assDTG_R_SUN_X2_LV0_Suv)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FR_LV0), (c_assCORRECT_DUCT_TIME_FR_LV0_Suv)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FL_LV0), (c_assCORRECT_DUCT_TIME_FL_LV0_Suv)); + M_MEMCOPY((g_assCORRECT_DUCT_RATE_LV0), (c_assCORRECT_DUCT_RATE_LV0_Suv)); + M_MEMCOPY((g_assCORRECT_DUCT_MAX_LV0), (c_assCORRECT_DUCT_MAX_LV0_Suv)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FR_LV0), (c_assCORRECT_AF_TIME_FR_LV0_Suv)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FL_LV0), (c_assCORRECT_AF_TIME_FL_LV0_Suv)); + M_MEMCOPY((g_assCORRECT_AF_RATE_LV0), (c_assCORRECT_AF_RATE_LV0_Suv)); + M_MEMCOPY((g_assCORRECT_AF_MAX_LV0), (c_assCORRECT_AF_MAX_LV0_Suv)); +/* ------------------------------------------Lv0 : End*/ + M_MEMCOPY((g_assINCAR_TG_FL_LV1), (c_assINCAR_TG_FL_LV1_Suv)); + M_MEMCOPY((g_assINCAR_TG_FR_LV1), (c_assINCAR_TG_FR_LV1_Suv)); + M_MEMCOPY((g_assVTG_FL_LV1), (c_assVTG_FL_LV1_Suv)); + M_MEMCOPY((g_assVTG_FR_LV1), (c_assVTG_FR_LV1_Suv)); + M_MEMCOPY((g_assVF_MIN_LV1), (c_assVF_MIN_LV1_Suv)); + M_MEMCOPY((g_assVF_MAX_LV1), (c_assVF_MAX_LV1_Suv)); + M_MEMCOPY((g_assVF_INC_Y1_LV1), (c_assVF_INC_Y1_LV1_Suv)); + M_MEMCOPY((g_assVF_INC_Y2_LV1), (c_assVF_INC_Y2_LV1_Suv)); + M_MEMCOPY((g_assVF_INC_Y3_LV1), (c_assVF_INC_Y3_LV1_Suv)); + M_MEMCOPY((g_assVF_INC_Y4_LV1), (c_assVF_INC_Y4_LV1_Suv)); + M_MEMCOPY((g_assVF_INC_X1_LV1), (c_assVF_INC_X1_LV1_Suv)); + M_MEMCOPY((g_assVF_INC_X2_LV1), (c_assVF_INC_X2_LV1_Suv)); + M_MEMCOPY((g_assVF_INC_X3_LV1), (c_assVF_INC_X3_LV1_Suv)); + M_MEMCOPY((g_assVF_INC_X4_LV1), (c_assVF_INC_X4_LV1_Suv)); + M_MEMCOPY((g_assVF_AMB_Y1_LV1), (c_assVF_AMB_Y1_LV1_Suv)); + M_MEMCOPY((g_assVF_AMB_Y2_LV1), (c_assVF_AMB_Y2_LV1_Suv)); + M_MEMCOPY((g_assVF_AMB_X1_LV1), (c_assVF_AMB_X1_LV1_Suv)); + M_MEMCOPY((g_assVF_AMB_X2_LV1), (c_assVF_AMB_X2_LV1_Suv)); + M_MEMCOPY((g_assVF_SUN_Y1_LV1), (c_assVF_SUN_Y1_LV1_Suv)); + M_MEMCOPY((g_assVF_SUN_Y2_LV1), (c_assVF_SUN_Y2_LV1_Suv)); + M_MEMCOPY((g_assVF_SUN_X1_LV1), (c_assVF_SUN_X1_LV1_Suv)); + M_MEMCOPY((g_assVF_SUN_X2_LV1), (c_assVF_SUN_X2_LV1_Suv)); + M_MEMCOPY((g_assTG_FLU_LV1), (c_assTG_FLU_LV1_Suv)); + M_MEMCOPY((g_assTG_FRU_LV1), (c_assTG_FRU_LV1_Suv)); + M_MEMCOPY((g_assDTG_FU_MIN_LV1), (c_assDTG_FU_MIN_LV1_Suv)); + M_MEMCOPY((g_assDTG_FU_MAX_LV1), (c_assDTG_FU_MAX_LV1_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_Y1_LV1), (c_assDTG_FU_INC_Y1_LV1_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_Y2_LV1), (c_assDTG_FU_INC_Y2_LV1_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_Y3_LV1), (c_assDTG_FU_INC_Y3_LV1_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_Y4_LV1), (c_assDTG_FU_INC_Y4_LV1_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_X1_LV1), (c_assDTG_FU_INC_X1_LV1_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_X2_LV1), (c_assDTG_FU_INC_X2_LV1_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_X3_LV1), (c_assDTG_FU_INC_X3_LV1_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_X4_LV1), (c_assDTG_FU_INC_X4_LV1_Suv)); + M_MEMCOPY((g_assDTG_FU_AMB_Y1_LV1), (c_assDTG_FU_AMB_Y1_LV1_Suv)); + M_MEMCOPY((g_assDTG_FU_AMB_Y2_LV1), (c_assDTG_FU_AMB_Y2_LV1_Suv)); + M_MEMCOPY((g_assDTG_FU_AMB_X1_LV1), (c_assDTG_FU_AMB_X1_LV1_Suv)); + M_MEMCOPY((g_assDTG_FU_AMB_X2_LV1), (c_assDTG_FU_AMB_X2_LV1_Suv)); + M_MEMCOPY((g_assDTG_FU_SUN_Y1_LV1), (c_assDTG_FU_SUN_Y1_LV1_Suv)); + M_MEMCOPY((g_assDTG_FU_SUN_Y2_LV1), (c_assDTG_FU_SUN_Y2_LV1_Suv)); + M_MEMCOPY((g_assDTG_FU_SUN_X1_LV1), (c_assDTG_FU_SUN_X1_LV1_Suv)); + M_MEMCOPY((g_assDTG_FU_SUN_X2_LV1), (c_assDTG_FU_SUN_X2_LV1_Suv)); + M_MEMCOPY((g_assTG_FLL_LV1), (c_assTG_FLL_LV1_Suv)); + M_MEMCOPY((g_assTG_FRL_LV1), (c_assTG_FRL_LV1_Suv)); + M_MEMCOPY((g_assDTG_FL_MIN_LV1), (c_assDTG_FL_MIN_LV1_Suv)); + M_MEMCOPY((g_assDTG_FL_MAX_LV1), (c_assDTG_FL_MAX_LV1_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_Y1_LV1), (c_assDTG_FL_INC_Y1_LV1_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_Y2_LV1), (c_assDTG_FL_INC_Y2_LV1_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_Y3_LV1), (c_assDTG_FL_INC_Y3_LV1_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_Y4_LV1), (c_assDTG_FL_INC_Y4_LV1_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_X1_LV1), (c_assDTG_FL_INC_X1_LV1_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_X2_LV1), (c_assDTG_FL_INC_X2_LV1_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_X3_LV1), (c_assDTG_FL_INC_X3_LV1_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_X4_LV1), (c_assDTG_FL_INC_X4_LV1_Suv)); + M_MEMCOPY((g_assDTG_FL_AMB_Y1_LV1), (c_assDTG_FL_AMB_Y1_LV1_Suv)); + M_MEMCOPY((g_assDTG_FL_AMB_Y2_LV1), (c_assDTG_FL_AMB_Y2_LV1_Suv)); + M_MEMCOPY((g_assDTG_FL_AMB_X1_LV1), (c_assDTG_FL_AMB_X1_LV1_Suv)); + M_MEMCOPY((g_assDTG_FL_AMB_X2_LV1), (c_assDTG_FL_AMB_X2_LV1_Suv)); + M_MEMCOPY((g_assDTG_FL_SUN_Y1_LV1), (c_assDTG_FL_SUN_Y1_LV1_Suv)); + M_MEMCOPY((g_assDTG_FL_SUN_Y2_LV1), (c_assDTG_FL_SUN_Y2_LV1_Suv)); + M_MEMCOPY((g_assDTG_FL_SUN_X1_LV1), (c_assDTG_FL_SUN_X1_LV1_Suv)); + M_MEMCOPY((g_assDTG_FL_SUN_X2_LV1), (c_assDTG_FL_SUN_X2_LV1_Suv)); + M_MEMCOPY((g_assINCAR_TG_RL_LV1), (c_assINCAR_TG_RL_LV1_Suv)); + M_MEMCOPY((g_assINCAR_TG_RR_LV1), (c_assINCAR_TG_RR_LV1_Suv)); + M_MEMCOPY((g_assVTG_RL_LV1), (c_assVTG_RL_LV1_Suv)); + M_MEMCOPY((g_assVTG_RR_LV1), (c_assVTG_RR_LV1_Suv)); + M_MEMCOPY((g_assVR_MIN_LV1), (c_assVR_MIN_LV1_Suv)); + M_MEMCOPY((g_assVR_MAX_LV1), (c_assVR_MAX_LV1_Suv)); + M_MEMCOPY((g_assVR_INC_Y1_LV1), (c_assVR_INC_Y1_LV1_Suv)); + M_MEMCOPY((g_assVR_INC_Y2_LV1), (c_assVR_INC_Y2_LV1_Suv)); + M_MEMCOPY((g_assVR_INC_Y3_LV1), (c_assVR_INC_Y3_LV1_Suv)); + M_MEMCOPY((g_assVR_INC_Y4_LV1), (c_assVR_INC_Y4_LV1_Suv)); + M_MEMCOPY((g_assVR_INC_X1_LV1), (c_assVR_INC_X1_LV1_Suv)); + M_MEMCOPY((g_assVR_INC_X2_LV1), (c_assVR_INC_X2_LV1_Suv)); + M_MEMCOPY((g_assVR_INC_X3_LV1), (c_assVR_INC_X3_LV1_Suv)); + M_MEMCOPY((g_assVR_INC_X4_LV1), (c_assVR_INC_X4_LV1_Suv)); + M_MEMCOPY((g_assVR_AMB_Y1_LV1), (c_assVR_AMB_Y1_LV1_Suv)); + M_MEMCOPY((g_assVR_AMB_Y2_LV1), (c_assVR_AMB_Y2_LV1_Suv)); + M_MEMCOPY((g_assVR_AMB_X1_LV1), (c_assVR_AMB_X1_LV1_Suv)); + M_MEMCOPY((g_assVR_AMB_X2_LV1), (c_assVR_AMB_X2_LV1_Suv)); + M_MEMCOPY((g_assVR_SUN_Y1_LV1), (c_assVR_SUN_Y1_LV1_Suv)); + M_MEMCOPY((g_assVR_SUN_Y2_LV1), (c_assVR_SUN_Y2_LV1_Suv)); + M_MEMCOPY((g_assVR_SUN_X1_LV1), (c_assVR_SUN_X1_LV1_Suv)); + M_MEMCOPY((g_assVR_SUN_X2_LV1), (c_assVR_SUN_X2_LV1_Suv)); + M_MEMCOPY((g_assTG_RL_LV1), (c_assTG_RL_LV1_Suv)); + M_MEMCOPY((g_assTG_RR_LV1), (c_assTG_RR_LV1_Suv)); + M_MEMCOPY((g_assDTG_R_MIN_LV1), (c_assDTG_R_MIN_LV1_Suv)); + M_MEMCOPY((g_assDTG_R_MAX_LV1), (c_assDTG_R_MAX_LV1_Suv)); + M_MEMCOPY((g_assDTG_R_INC_Y1_LV1), (c_assDTG_R_INC_Y1_LV1_Suv)); + M_MEMCOPY((g_assDTG_R_INC_Y2_LV1), (c_assDTG_R_INC_Y2_LV1_Suv)); + M_MEMCOPY((g_assDTG_R_INC_Y3_LV1), (c_assDTG_R_INC_Y3_LV1_Suv)); + M_MEMCOPY((g_assDTG_R_INC_Y4_LV1), (c_assDTG_R_INC_Y4_LV1_Suv)); + M_MEMCOPY((g_assDTG_R_INC_X1_LV1), (c_assDTG_R_INC_X1_LV1_Suv)); + M_MEMCOPY((g_assDTG_R_INC_X2_LV1), (c_assDTG_R_INC_X2_LV1_Suv)); + M_MEMCOPY((g_assDTG_R_INC_X3_LV1), (c_assDTG_R_INC_X3_LV1_Suv)); + M_MEMCOPY((g_assDTG_R_INC_X4_LV1), (c_assDTG_R_INC_X4_LV1_Suv)); + M_MEMCOPY((g_assDTG_R_AMB_Y1_LV1), (c_assDTG_R_AMB_Y1_LV1_Suv)); + M_MEMCOPY((g_assDTG_R_AMB_Y2_LV1), (c_assDTG_R_AMB_Y2_LV1_Suv)); + M_MEMCOPY((g_assDTG_R_AMB_X1_LV1), (c_assDTG_R_AMB_X1_LV1_Suv)); + M_MEMCOPY((g_assDTG_R_AMB_X2_LV1), (c_assDTG_R_AMB_X2_LV1_Suv)); + M_MEMCOPY((g_assDTG_R_SUN_Y1_LV1), (c_assDTG_R_SUN_Y1_LV1_Suv)); + M_MEMCOPY((g_assDTG_R_SUN_Y2_LV1), (c_assDTG_R_SUN_Y2_LV1_Suv)); + M_MEMCOPY((g_assDTG_R_SUN_X1_LV1), (c_assDTG_R_SUN_X1_LV1_Suv)); + M_MEMCOPY((g_assDTG_R_SUN_X2_LV1), (c_assDTG_R_SUN_X2_LV1_Suv)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FR_LV1), (c_assCORRECT_DUCT_TIME_FR_LV1_Suv)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FL_LV1), (c_assCORRECT_DUCT_TIME_FL_LV1_Suv)); + M_MEMCOPY((g_assCORRECT_DUCT_RATE_LV1), (c_assCORRECT_DUCT_RATE_LV1_Suv)); + M_MEMCOPY((g_assCORRECT_DUCT_MAX_LV1), (c_assCORRECT_DUCT_MAX_LV1_Suv)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FR_LV1), (c_assCORRECT_AF_TIME_FR_LV1_Suv)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FL_LV1), (c_assCORRECT_AF_TIME_FL_LV1_Suv)); + M_MEMCOPY((g_assCORRECT_AF_RATE_LV1), (c_assCORRECT_AF_RATE_LV1_Suv)); + M_MEMCOPY((g_assCORRECT_AF_MAX_LV1), (c_assCORRECT_AF_MAX_LV1_Suv)); +/* ------------------------------------------Lv1 : End*/ + M_MEMCOPY((g_assINCAR_TG_FL_LV2), (c_assINCAR_TG_FL_LV2_Suv)); + M_MEMCOPY((g_assINCAR_TG_FR_LV2), (c_assINCAR_TG_FR_LV2_Suv)); + M_MEMCOPY((g_assVTG_FL_LV2), (c_assVTG_FL_LV2_Suv)); + M_MEMCOPY((g_assVTG_FR_LV2), (c_assVTG_FR_LV2_Suv)); + M_MEMCOPY((g_assVF_MIN_LV2), (c_assVF_MIN_LV2_Suv)); + M_MEMCOPY((g_assVF_MAX_LV2), (c_assVF_MAX_LV2_Suv)); + M_MEMCOPY((g_assVF_INC_Y1_LV2), (c_assVF_INC_Y1_LV2_Suv)); + M_MEMCOPY((g_assVF_INC_Y2_LV2), (c_assVF_INC_Y2_LV2_Suv)); + M_MEMCOPY((g_assVF_INC_Y3_LV2), (c_assVF_INC_Y3_LV2_Suv)); + M_MEMCOPY((g_assVF_INC_Y4_LV2), (c_assVF_INC_Y4_LV2_Suv)); + M_MEMCOPY((g_assVF_INC_X1_LV2), (c_assVF_INC_X1_LV2_Suv)); + M_MEMCOPY((g_assVF_INC_X2_LV2), (c_assVF_INC_X2_LV2_Suv)); + M_MEMCOPY((g_assVF_INC_X3_LV2), (c_assVF_INC_X3_LV2_Suv)); + M_MEMCOPY((g_assVF_INC_X4_LV2), (c_assVF_INC_X4_LV2_Suv)); + M_MEMCOPY((g_assVF_AMB_Y1_LV2), (c_assVF_AMB_Y1_LV2_Suv)); + M_MEMCOPY((g_assVF_AMB_Y2_LV2), (c_assVF_AMB_Y2_LV2_Suv)); + M_MEMCOPY((g_assVF_AMB_X1_LV2), (c_assVF_AMB_X1_LV2_Suv)); + M_MEMCOPY((g_assVF_AMB_X2_LV2), (c_assVF_AMB_X2_LV2_Suv)); + M_MEMCOPY((g_assVF_SUN_Y1_LV2), (c_assVF_SUN_Y1_LV2_Suv)); + M_MEMCOPY((g_assVF_SUN_Y2_LV2), (c_assVF_SUN_Y2_LV2_Suv)); + M_MEMCOPY((g_assVF_SUN_X1_LV2), (c_assVF_SUN_X1_LV2_Suv)); + M_MEMCOPY((g_assVF_SUN_X2_LV2), (c_assVF_SUN_X2_LV2_Suv)); + M_MEMCOPY((g_assTG_FLU_LV2), (c_assTG_FLU_LV2_Suv)); + M_MEMCOPY((g_assTG_FRU_LV2), (c_assTG_FRU_LV2_Suv)); + M_MEMCOPY((g_assDTG_FU_MIN_LV2), (c_assDTG_FU_MIN_LV2_Suv)); + M_MEMCOPY((g_assDTG_FU_MAX_LV2), (c_assDTG_FU_MAX_LV2_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_Y1_LV2), (c_assDTG_FU_INC_Y1_LV2_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_Y2_LV2), (c_assDTG_FU_INC_Y2_LV2_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_Y3_LV2), (c_assDTG_FU_INC_Y3_LV2_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_Y4_LV2), (c_assDTG_FU_INC_Y4_LV2_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_X1_LV2), (c_assDTG_FU_INC_X1_LV2_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_X2_LV2), (c_assDTG_FU_INC_X2_LV2_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_X3_LV2), (c_assDTG_FU_INC_X3_LV2_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_X4_LV2), (c_assDTG_FU_INC_X4_LV2_Suv)); + M_MEMCOPY((g_assDTG_FU_AMB_Y1_LV2), (c_assDTG_FU_AMB_Y1_LV2_Suv)); + M_MEMCOPY((g_assDTG_FU_AMB_Y2_LV2), (c_assDTG_FU_AMB_Y2_LV2_Suv)); + M_MEMCOPY((g_assDTG_FU_AMB_X1_LV2), (c_assDTG_FU_AMB_X1_LV2_Suv)); + M_MEMCOPY((g_assDTG_FU_AMB_X2_LV2), (c_assDTG_FU_AMB_X2_LV2_Suv)); + M_MEMCOPY((g_assDTG_FU_SUN_Y1_LV2), (c_assDTG_FU_SUN_Y1_LV2_Suv)); + M_MEMCOPY((g_assDTG_FU_SUN_Y2_LV2), (c_assDTG_FU_SUN_Y2_LV2_Suv)); + M_MEMCOPY((g_assDTG_FU_SUN_X1_LV2), (c_assDTG_FU_SUN_X1_LV2_Suv)); + M_MEMCOPY((g_assDTG_FU_SUN_X2_LV2), (c_assDTG_FU_SUN_X2_LV2_Suv)); + M_MEMCOPY((g_assTG_FLL_LV2), (c_assTG_FLL_LV2_Suv)); + M_MEMCOPY((g_assTG_FRL_LV2), (c_assTG_FRL_LV2_Suv)); + M_MEMCOPY((g_assDTG_FL_MIN_LV2), (c_assDTG_FL_MIN_LV2_Suv)); + M_MEMCOPY((g_assDTG_FL_MAX_LV2), (c_assDTG_FL_MAX_LV2_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_Y1_LV2), (c_assDTG_FL_INC_Y1_LV2_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_Y2_LV2), (c_assDTG_FL_INC_Y2_LV2_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_Y3_LV2), (c_assDTG_FL_INC_Y3_LV2_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_Y4_LV2), (c_assDTG_FL_INC_Y4_LV2_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_X1_LV2), (c_assDTG_FL_INC_X1_LV2_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_X2_LV2), (c_assDTG_FL_INC_X2_LV2_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_X3_LV2), (c_assDTG_FL_INC_X3_LV2_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_X4_LV2), (c_assDTG_FL_INC_X4_LV2_Suv)); + M_MEMCOPY((g_assDTG_FL_AMB_Y1_LV2), (c_assDTG_FL_AMB_Y1_LV2_Suv)); + M_MEMCOPY((g_assDTG_FL_AMB_Y2_LV2), (c_assDTG_FL_AMB_Y2_LV2_Suv)); + M_MEMCOPY((g_assDTG_FL_AMB_X1_LV2), (c_assDTG_FL_AMB_X1_LV2_Suv)); + M_MEMCOPY((g_assDTG_FL_AMB_X2_LV2), (c_assDTG_FL_AMB_X2_LV2_Suv)); + M_MEMCOPY((g_assDTG_FL_SUN_Y1_LV2), (c_assDTG_FL_SUN_Y1_LV2_Suv)); + M_MEMCOPY((g_assDTG_FL_SUN_Y2_LV2), (c_assDTG_FL_SUN_Y2_LV2_Suv)); + M_MEMCOPY((g_assDTG_FL_SUN_X1_LV2), (c_assDTG_FL_SUN_X1_LV2_Suv)); + M_MEMCOPY((g_assDTG_FL_SUN_X2_LV2), (c_assDTG_FL_SUN_X2_LV2_Suv)); + M_MEMCOPY((g_assINCAR_TG_RL_LV2), (c_assINCAR_TG_RL_LV2_Suv)); + M_MEMCOPY((g_assINCAR_TG_RR_LV2), (c_assINCAR_TG_RR_LV2_Suv)); + M_MEMCOPY((g_assVTG_RL_LV2), (c_assVTG_RL_LV2_Suv)); + M_MEMCOPY((g_assVTG_RR_LV2), (c_assVTG_RR_LV2_Suv)); + M_MEMCOPY((g_assVR_MIN_LV2), (c_assVR_MIN_LV2_Suv)); + M_MEMCOPY((g_assVR_MAX_LV2), (c_assVR_MAX_LV2_Suv)); + M_MEMCOPY((g_assVR_INC_Y1_LV2), (c_assVR_INC_Y1_LV2_Suv)); + M_MEMCOPY((g_assVR_INC_Y2_LV2), (c_assVR_INC_Y2_LV2_Suv)); + M_MEMCOPY((g_assVR_INC_Y3_LV2), (c_assVR_INC_Y3_LV2_Suv)); + M_MEMCOPY((g_assVR_INC_Y4_LV2), (c_assVR_INC_Y4_LV2_Suv)); + M_MEMCOPY((g_assVR_INC_X1_LV2), (c_assVR_INC_X1_LV2_Suv)); + M_MEMCOPY((g_assVR_INC_X2_LV2), (c_assVR_INC_X2_LV2_Suv)); + M_MEMCOPY((g_assVR_INC_X3_LV2), (c_assVR_INC_X3_LV2_Suv)); + M_MEMCOPY((g_assVR_INC_X4_LV2), (c_assVR_INC_X4_LV2_Suv)); + M_MEMCOPY((g_assVR_AMB_Y1_LV2), (c_assVR_AMB_Y1_LV2_Suv)); + M_MEMCOPY((g_assVR_AMB_Y2_LV2), (c_assVR_AMB_Y2_LV2_Suv)); + M_MEMCOPY((g_assVR_AMB_X1_LV2), (c_assVR_AMB_X1_LV2_Suv)); + M_MEMCOPY((g_assVR_AMB_X2_LV2), (c_assVR_AMB_X2_LV2_Suv)); + M_MEMCOPY((g_assVR_SUN_Y1_LV2), (c_assVR_SUN_Y1_LV2_Suv)); + M_MEMCOPY((g_assVR_SUN_Y2_LV2), (c_assVR_SUN_Y2_LV2_Suv)); + M_MEMCOPY((g_assVR_SUN_X1_LV2), (c_assVR_SUN_X1_LV2_Suv)); + M_MEMCOPY((g_assVR_SUN_X2_LV2), (c_assVR_SUN_X2_LV2_Suv)); + M_MEMCOPY((g_assTG_RL_LV2), (c_assTG_RL_LV2_Suv)); + M_MEMCOPY((g_assTG_RR_LV2), (c_assTG_RR_LV2_Suv)); + M_MEMCOPY((g_assDTG_R_MIN_LV2), (c_assDTG_R_MIN_LV2_Suv)); + M_MEMCOPY((g_assDTG_R_MAX_LV2), (c_assDTG_R_MAX_LV2_Suv)); + M_MEMCOPY((g_assDTG_R_INC_Y1_LV2), (c_assDTG_R_INC_Y1_LV2_Suv)); + M_MEMCOPY((g_assDTG_R_INC_Y2_LV2), (c_assDTG_R_INC_Y2_LV2_Suv)); + M_MEMCOPY((g_assDTG_R_INC_Y3_LV2), (c_assDTG_R_INC_Y3_LV2_Suv)); + M_MEMCOPY((g_assDTG_R_INC_Y4_LV2), (c_assDTG_R_INC_Y4_LV2_Suv)); + M_MEMCOPY((g_assDTG_R_INC_X1_LV2), (c_assDTG_R_INC_X1_LV2_Suv)); + M_MEMCOPY((g_assDTG_R_INC_X2_LV2), (c_assDTG_R_INC_X2_LV2_Suv)); + M_MEMCOPY((g_assDTG_R_INC_X3_LV2), (c_assDTG_R_INC_X3_LV2_Suv)); + M_MEMCOPY((g_assDTG_R_INC_X4_LV2), (c_assDTG_R_INC_X4_LV2_Suv)); + M_MEMCOPY((g_assDTG_R_AMB_Y1_LV2), (c_assDTG_R_AMB_Y1_LV2_Suv)); + M_MEMCOPY((g_assDTG_R_AMB_Y2_LV2), (c_assDTG_R_AMB_Y2_LV2_Suv)); + M_MEMCOPY((g_assDTG_R_AMB_X1_LV2), (c_assDTG_R_AMB_X1_LV2_Suv)); + M_MEMCOPY((g_assDTG_R_AMB_X2_LV2), (c_assDTG_R_AMB_X2_LV2_Suv)); + M_MEMCOPY((g_assDTG_R_SUN_Y1_LV2), (c_assDTG_R_SUN_Y1_LV2_Suv)); + M_MEMCOPY((g_assDTG_R_SUN_Y2_LV2), (c_assDTG_R_SUN_Y2_LV2_Suv)); + M_MEMCOPY((g_assDTG_R_SUN_X1_LV2), (c_assDTG_R_SUN_X1_LV2_Suv)); + M_MEMCOPY((g_assDTG_R_SUN_X2_LV2), (c_assDTG_R_SUN_X2_LV2_Suv)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FR_LV2), (c_assCORRECT_DUCT_TIME_FR_LV2_Suv)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FL_LV2), (c_assCORRECT_DUCT_TIME_FL_LV2_Suv)); + M_MEMCOPY((g_assCORRECT_DUCT_RATE_LV2), (c_assCORRECT_DUCT_RATE_LV2_Suv)); + M_MEMCOPY((g_assCORRECT_DUCT_MAX_LV2), (c_assCORRECT_DUCT_MAX_LV2_Suv)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FR_LV2), (c_assCORRECT_AF_TIME_FR_LV2_Suv)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FL_LV2), (c_assCORRECT_AF_TIME_FL_LV2_Suv)); + M_MEMCOPY((g_assCORRECT_AF_RATE_LV2), (c_assCORRECT_AF_RATE_LV2_Suv)); + M_MEMCOPY((g_assCORRECT_AF_MAX_LV2), (c_assCORRECT_AF_MAX_LV2_Suv)); +/* ------------------------------------------Lv2 : End*/ + M_MEMCOPY((g_assINCAR_TG_FL_LV3), (c_assINCAR_TG_FL_LV3_Suv)); + M_MEMCOPY((g_assINCAR_TG_FR_LV3), (c_assINCAR_TG_FR_LV3_Suv)); + M_MEMCOPY((g_assVTG_FL_LV3), (c_assVTG_FL_LV3_Suv)); + M_MEMCOPY((g_assVTG_FR_LV3), (c_assVTG_FR_LV3_Suv)); + M_MEMCOPY((g_assVF_MIN_LV3), (c_assVF_MIN_LV3_Suv)); + M_MEMCOPY((g_assVF_MAX_LV3), (c_assVF_MAX_LV3_Suv)); + M_MEMCOPY((g_assVF_INC_Y1_LV3), (c_assVF_INC_Y1_LV3_Suv)); + M_MEMCOPY((g_assVF_INC_Y2_LV3), (c_assVF_INC_Y2_LV3_Suv)); + M_MEMCOPY((g_assVF_INC_Y3_LV3), (c_assVF_INC_Y3_LV3_Suv)); + M_MEMCOPY((g_assVF_INC_Y4_LV3), (c_assVF_INC_Y4_LV3_Suv)); + M_MEMCOPY((g_assVF_INC_X1_LV3), (c_assVF_INC_X1_LV3_Suv)); + M_MEMCOPY((g_assVF_INC_X2_LV3), (c_assVF_INC_X2_LV3_Suv)); + M_MEMCOPY((g_assVF_INC_X3_LV3), (c_assVF_INC_X3_LV3_Suv)); + M_MEMCOPY((g_assVF_INC_X4_LV3), (c_assVF_INC_X4_LV3_Suv)); + M_MEMCOPY((g_assVF_AMB_Y1_LV3), (c_assVF_AMB_Y1_LV3_Suv)); + M_MEMCOPY((g_assVF_AMB_Y2_LV3), (c_assVF_AMB_Y2_LV3_Suv)); + M_MEMCOPY((g_assVF_AMB_X1_LV3), (c_assVF_AMB_X1_LV3_Suv)); + M_MEMCOPY((g_assVF_AMB_X2_LV3), (c_assVF_AMB_X2_LV3_Suv)); + M_MEMCOPY((g_assVF_SUN_Y1_LV3), (c_assVF_SUN_Y1_LV3_Suv)); + M_MEMCOPY((g_assVF_SUN_Y2_LV3), (c_assVF_SUN_Y2_LV3_Suv)); + M_MEMCOPY((g_assVF_SUN_X1_LV3), (c_assVF_SUN_X1_LV3_Suv)); + M_MEMCOPY((g_assVF_SUN_X2_LV3), (c_assVF_SUN_X2_LV3_Suv)); + M_MEMCOPY((g_assTG_FLU_LV3), (c_assTG_FLU_LV3_Suv)); + M_MEMCOPY((g_assTG_FRU_LV3), (c_assTG_FRU_LV3_Suv)); + M_MEMCOPY((g_assDTG_FU_MIN_LV3), (c_assDTG_FU_MIN_LV3_Suv)); + M_MEMCOPY((g_assDTG_FU_MAX_LV3), (c_assDTG_FU_MAX_LV3_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_Y1_LV3), (c_assDTG_FU_INC_Y1_LV3_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_Y2_LV3), (c_assDTG_FU_INC_Y2_LV3_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_Y3_LV3), (c_assDTG_FU_INC_Y3_LV3_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_Y4_LV3), (c_assDTG_FU_INC_Y4_LV3_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_X1_LV3), (c_assDTG_FU_INC_X1_LV3_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_X2_LV3), (c_assDTG_FU_INC_X2_LV3_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_X3_LV3), (c_assDTG_FU_INC_X3_LV3_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_X4_LV3), (c_assDTG_FU_INC_X4_LV3_Suv)); + M_MEMCOPY((g_assDTG_FU_AMB_Y1_LV3), (c_assDTG_FU_AMB_Y1_LV3_Suv)); + M_MEMCOPY((g_assDTG_FU_AMB_Y2_LV3), (c_assDTG_FU_AMB_Y2_LV3_Suv)); + M_MEMCOPY((g_assDTG_FU_AMB_X1_LV3), (c_assDTG_FU_AMB_X1_LV3_Suv)); + M_MEMCOPY((g_assDTG_FU_AMB_X2_LV3), (c_assDTG_FU_AMB_X2_LV3_Suv)); + M_MEMCOPY((g_assDTG_FU_SUN_Y1_LV3), (c_assDTG_FU_SUN_Y1_LV3_Suv)); + M_MEMCOPY((g_assDTG_FU_SUN_Y2_LV3), (c_assDTG_FU_SUN_Y2_LV3_Suv)); + M_MEMCOPY((g_assDTG_FU_SUN_X1_LV3), (c_assDTG_FU_SUN_X1_LV3_Suv)); + M_MEMCOPY((g_assDTG_FU_SUN_X2_LV3), (c_assDTG_FU_SUN_X2_LV3_Suv)); + M_MEMCOPY((g_assTG_FLL_LV3), (c_assTG_FLL_LV3_Suv)); + M_MEMCOPY((g_assTG_FRL_LV3), (c_assTG_FRL_LV3_Suv)); + M_MEMCOPY((g_assDTG_FL_MIN_LV3), (c_assDTG_FL_MIN_LV3_Suv)); + M_MEMCOPY((g_assDTG_FL_MAX_LV3), (c_assDTG_FL_MAX_LV3_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_Y1_LV3), (c_assDTG_FL_INC_Y1_LV3_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_Y2_LV3), (c_assDTG_FL_INC_Y2_LV3_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_Y3_LV3), (c_assDTG_FL_INC_Y3_LV3_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_Y4_LV3), (c_assDTG_FL_INC_Y4_LV3_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_X1_LV3), (c_assDTG_FL_INC_X1_LV3_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_X2_LV3), (c_assDTG_FL_INC_X2_LV3_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_X3_LV3), (c_assDTG_FL_INC_X3_LV3_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_X4_LV3), (c_assDTG_FL_INC_X4_LV3_Suv)); + M_MEMCOPY((g_assDTG_FL_AMB_Y1_LV3), (c_assDTG_FL_AMB_Y1_LV3_Suv)); + M_MEMCOPY((g_assDTG_FL_AMB_Y2_LV3), (c_assDTG_FL_AMB_Y2_LV3_Suv)); + M_MEMCOPY((g_assDTG_FL_AMB_X1_LV3), (c_assDTG_FL_AMB_X1_LV3_Suv)); + M_MEMCOPY((g_assDTG_FL_AMB_X2_LV3), (c_assDTG_FL_AMB_X2_LV3_Suv)); + M_MEMCOPY((g_assDTG_FL_SUN_Y1_LV3), (c_assDTG_FL_SUN_Y1_LV3_Suv)); + M_MEMCOPY((g_assDTG_FL_SUN_Y2_LV3), (c_assDTG_FL_SUN_Y2_LV3_Suv)); + M_MEMCOPY((g_assDTG_FL_SUN_X1_LV3), (c_assDTG_FL_SUN_X1_LV3_Suv)); + M_MEMCOPY((g_assDTG_FL_SUN_X2_LV3), (c_assDTG_FL_SUN_X2_LV3_Suv)); + M_MEMCOPY((g_assINCAR_TG_RL_LV3), (c_assINCAR_TG_RL_LV3_Suv)); + M_MEMCOPY((g_assINCAR_TG_RR_LV3), (c_assINCAR_TG_RR_LV3_Suv)); + M_MEMCOPY((g_assVTG_RL_LV3), (c_assVTG_RL_LV3_Suv)); + M_MEMCOPY((g_assVTG_RR_LV3), (c_assVTG_RR_LV3_Suv)); + M_MEMCOPY((g_assVR_MIN_LV3), (c_assVR_MIN_LV3_Suv)); + M_MEMCOPY((g_assVR_MAX_LV3), (c_assVR_MAX_LV3_Suv)); + M_MEMCOPY((g_assVR_INC_Y1_LV3), (c_assVR_INC_Y1_LV3_Suv)); + M_MEMCOPY((g_assVR_INC_Y2_LV3), (c_assVR_INC_Y2_LV3_Suv)); + M_MEMCOPY((g_assVR_INC_Y3_LV3), (c_assVR_INC_Y3_LV3_Suv)); + M_MEMCOPY((g_assVR_INC_Y4_LV3), (c_assVR_INC_Y4_LV3_Suv)); + M_MEMCOPY((g_assVR_INC_X1_LV3), (c_assVR_INC_X1_LV3_Suv)); + M_MEMCOPY((g_assVR_INC_X2_LV3), (c_assVR_INC_X2_LV3_Suv)); + M_MEMCOPY((g_assVR_INC_X3_LV3), (c_assVR_INC_X3_LV3_Suv)); + M_MEMCOPY((g_assVR_INC_X4_LV3), (c_assVR_INC_X4_LV3_Suv)); + M_MEMCOPY((g_assVR_AMB_Y1_LV3), (c_assVR_AMB_Y1_LV3_Suv)); + M_MEMCOPY((g_assVR_AMB_Y2_LV3), (c_assVR_AMB_Y2_LV3_Suv)); + M_MEMCOPY((g_assVR_AMB_X1_LV3), (c_assVR_AMB_X1_LV3_Suv)); + M_MEMCOPY((g_assVR_AMB_X2_LV3), (c_assVR_AMB_X2_LV3_Suv)); + M_MEMCOPY((g_assVR_SUN_Y1_LV3), (c_assVR_SUN_Y1_LV3_Suv)); + M_MEMCOPY((g_assVR_SUN_Y2_LV3), (c_assVR_SUN_Y2_LV3_Suv)); + M_MEMCOPY((g_assVR_SUN_X1_LV3), (c_assVR_SUN_X1_LV3_Suv)); + M_MEMCOPY((g_assVR_SUN_X2_LV3), (c_assVR_SUN_X2_LV3_Suv)); + M_MEMCOPY((g_assTG_RL_LV3), (c_assTG_RL_LV3_Suv)); + M_MEMCOPY((g_assTG_RR_LV3), (c_assTG_RR_LV3_Suv)); + M_MEMCOPY((g_assDTG_R_MIN_LV3), (c_assDTG_R_MIN_LV3_Suv)); + M_MEMCOPY((g_assDTG_R_MAX_LV3), (c_assDTG_R_MAX_LV3_Suv)); + M_MEMCOPY((g_assDTG_R_INC_Y1_LV3), (c_assDTG_R_INC_Y1_LV3_Suv)); + M_MEMCOPY((g_assDTG_R_INC_Y2_LV3), (c_assDTG_R_INC_Y2_LV3_Suv)); + M_MEMCOPY((g_assDTG_R_INC_Y3_LV3), (c_assDTG_R_INC_Y3_LV3_Suv)); + M_MEMCOPY((g_assDTG_R_INC_Y4_LV3), (c_assDTG_R_INC_Y4_LV3_Suv)); + M_MEMCOPY((g_assDTG_R_INC_X1_LV3), (c_assDTG_R_INC_X1_LV3_Suv)); + M_MEMCOPY((g_assDTG_R_INC_X2_LV3), (c_assDTG_R_INC_X2_LV3_Suv)); + M_MEMCOPY((g_assDTG_R_INC_X3_LV3), (c_assDTG_R_INC_X3_LV3_Suv)); + M_MEMCOPY((g_assDTG_R_INC_X4_LV3), (c_assDTG_R_INC_X4_LV3_Suv)); + M_MEMCOPY((g_assDTG_R_AMB_Y1_LV3), (c_assDTG_R_AMB_Y1_LV3_Suv)); + M_MEMCOPY((g_assDTG_R_AMB_Y2_LV3), (c_assDTG_R_AMB_Y2_LV3_Suv)); + M_MEMCOPY((g_assDTG_R_AMB_X1_LV3), (c_assDTG_R_AMB_X1_LV3_Suv)); + M_MEMCOPY((g_assDTG_R_AMB_X2_LV3), (c_assDTG_R_AMB_X2_LV3_Suv)); + M_MEMCOPY((g_assDTG_R_SUN_Y1_LV3), (c_assDTG_R_SUN_Y1_LV3_Suv)); + M_MEMCOPY((g_assDTG_R_SUN_Y2_LV3), (c_assDTG_R_SUN_Y2_LV3_Suv)); + M_MEMCOPY((g_assDTG_R_SUN_X1_LV3), (c_assDTG_R_SUN_X1_LV3_Suv)); + M_MEMCOPY((g_assDTG_R_SUN_X2_LV3), (c_assDTG_R_SUN_X2_LV3_Suv)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FR_LV3), (c_assCORRECT_DUCT_TIME_FR_LV3_Suv)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FL_LV3), (c_assCORRECT_DUCT_TIME_FL_LV3_Suv)); + M_MEMCOPY((g_assCORRECT_DUCT_RATE_LV3), (c_assCORRECT_DUCT_RATE_LV3_Suv)); + M_MEMCOPY((g_assCORRECT_DUCT_MAX_LV3), (c_assCORRECT_DUCT_MAX_LV3_Suv)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FR_LV3), (c_assCORRECT_AF_TIME_FR_LV3_Suv)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FL_LV3), (c_assCORRECT_AF_TIME_FL_LV3_Suv)); + M_MEMCOPY((g_assCORRECT_AF_RATE_LV3), (c_assCORRECT_AF_RATE_LV3_Suv)); + M_MEMCOPY((g_assCORRECT_AF_MAX_LV3), (c_assCORRECT_AF_MAX_LV3_Suv)); +/* ------------------------------------------Lv3 : End*/ + M_MEMCOPY((g_assINCAR_TG_FL_LV4), (c_assINCAR_TG_FL_LV4_Suv)); + M_MEMCOPY((g_assINCAR_TG_FR_LV4), (c_assINCAR_TG_FR_LV4_Suv)); + M_MEMCOPY((g_assVTG_FL_LV4), (c_assVTG_FL_LV4_Suv)); + M_MEMCOPY((g_assVTG_FR_LV4), (c_assVTG_FR_LV4_Suv)); + M_MEMCOPY((g_assVF_MIN_LV4), (c_assVF_MIN_LV4_Suv)); + M_MEMCOPY((g_assVF_MAX_LV4), (c_assVF_MAX_LV4_Suv)); + M_MEMCOPY((g_assVF_INC_Y1_LV4), (c_assVF_INC_Y1_LV4_Suv)); + M_MEMCOPY((g_assVF_INC_Y2_LV4), (c_assVF_INC_Y2_LV4_Suv)); + M_MEMCOPY((g_assVF_INC_Y3_LV4), (c_assVF_INC_Y3_LV4_Suv)); + M_MEMCOPY((g_assVF_INC_Y4_LV4), (c_assVF_INC_Y4_LV4_Suv)); + M_MEMCOPY((g_assVF_INC_X1_LV4), (c_assVF_INC_X1_LV4_Suv)); + M_MEMCOPY((g_assVF_INC_X2_LV4), (c_assVF_INC_X2_LV4_Suv)); + M_MEMCOPY((g_assVF_INC_X3_LV4), (c_assVF_INC_X3_LV4_Suv)); + M_MEMCOPY((g_assVF_INC_X4_LV4), (c_assVF_INC_X4_LV4_Suv)); + M_MEMCOPY((g_assVF_AMB_Y1_LV4), (c_assVF_AMB_Y1_LV4_Suv)); + M_MEMCOPY((g_assVF_AMB_Y2_LV4), (c_assVF_AMB_Y2_LV4_Suv)); + M_MEMCOPY((g_assVF_AMB_X1_LV4), (c_assVF_AMB_X1_LV4_Suv)); + M_MEMCOPY((g_assVF_AMB_X2_LV4), (c_assVF_AMB_X2_LV4_Suv)); + M_MEMCOPY((g_assVF_SUN_Y1_LV4), (c_assVF_SUN_Y1_LV4_Suv)); + M_MEMCOPY((g_assVF_SUN_Y2_LV4), (c_assVF_SUN_Y2_LV4_Suv)); + M_MEMCOPY((g_assVF_SUN_X1_LV4), (c_assVF_SUN_X1_LV4_Suv)); + M_MEMCOPY((g_assVF_SUN_X2_LV4), (c_assVF_SUN_X2_LV4_Suv)); + M_MEMCOPY((g_assTG_FLU_LV4), (c_assTG_FLU_LV4_Suv)); + M_MEMCOPY((g_assTG_FRU_LV4), (c_assTG_FRU_LV4_Suv)); + M_MEMCOPY((g_assDTG_FU_MIN_LV4), (c_assDTG_FU_MIN_LV4_Suv)); + M_MEMCOPY((g_assDTG_FU_MAX_LV4), (c_assDTG_FU_MAX_LV4_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_Y1_LV4), (c_assDTG_FU_INC_Y1_LV4_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_Y2_LV4), (c_assDTG_FU_INC_Y2_LV4_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_Y3_LV4), (c_assDTG_FU_INC_Y3_LV4_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_Y4_LV4), (c_assDTG_FU_INC_Y4_LV4_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_X1_LV4), (c_assDTG_FU_INC_X1_LV4_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_X2_LV4), (c_assDTG_FU_INC_X2_LV4_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_X3_LV4), (c_assDTG_FU_INC_X3_LV4_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_X4_LV4), (c_assDTG_FU_INC_X4_LV4_Suv)); + M_MEMCOPY((g_assDTG_FU_AMB_Y1_LV4), (c_assDTG_FU_AMB_Y1_LV4_Suv)); + M_MEMCOPY((g_assDTG_FU_AMB_Y2_LV4), (c_assDTG_FU_AMB_Y2_LV4_Suv)); + M_MEMCOPY((g_assDTG_FU_AMB_X1_LV4), (c_assDTG_FU_AMB_X1_LV4_Suv)); + M_MEMCOPY((g_assDTG_FU_AMB_X2_LV4), (c_assDTG_FU_AMB_X2_LV4_Suv)); + M_MEMCOPY((g_assDTG_FU_SUN_Y1_LV4), (c_assDTG_FU_SUN_Y1_LV4_Suv)); + M_MEMCOPY((g_assDTG_FU_SUN_Y2_LV4), (c_assDTG_FU_SUN_Y2_LV4_Suv)); + M_MEMCOPY((g_assDTG_FU_SUN_X1_LV4), (c_assDTG_FU_SUN_X1_LV4_Suv)); + M_MEMCOPY((g_assDTG_FU_SUN_X2_LV4), (c_assDTG_FU_SUN_X2_LV4_Suv)); + M_MEMCOPY((g_assTG_FLL_LV4), (c_assTG_FLL_LV4_Suv)); + M_MEMCOPY((g_assTG_FRL_LV4), (c_assTG_FRL_LV4_Suv)); + M_MEMCOPY((g_assDTG_FL_MIN_LV4), (c_assDTG_FL_MIN_LV4_Suv)); + M_MEMCOPY((g_assDTG_FL_MAX_LV4), (c_assDTG_FL_MAX_LV4_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_Y1_LV4), (c_assDTG_FL_INC_Y1_LV4_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_Y2_LV4), (c_assDTG_FL_INC_Y2_LV4_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_Y3_LV4), (c_assDTG_FL_INC_Y3_LV4_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_Y4_LV4), (c_assDTG_FL_INC_Y4_LV4_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_X1_LV4), (c_assDTG_FL_INC_X1_LV4_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_X2_LV4), (c_assDTG_FL_INC_X2_LV4_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_X3_LV4), (c_assDTG_FL_INC_X3_LV4_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_X4_LV4), (c_assDTG_FL_INC_X4_LV4_Suv)); + M_MEMCOPY((g_assDTG_FL_AMB_Y1_LV4), (c_assDTG_FL_AMB_Y1_LV4_Suv)); + M_MEMCOPY((g_assDTG_FL_AMB_Y2_LV4), (c_assDTG_FL_AMB_Y2_LV4_Suv)); + M_MEMCOPY((g_assDTG_FL_AMB_X1_LV4), (c_assDTG_FL_AMB_X1_LV4_Suv)); + M_MEMCOPY((g_assDTG_FL_AMB_X2_LV4), (c_assDTG_FL_AMB_X2_LV4_Suv)); + M_MEMCOPY((g_assDTG_FL_SUN_Y1_LV4), (c_assDTG_FL_SUN_Y1_LV4_Suv)); + M_MEMCOPY((g_assDTG_FL_SUN_Y2_LV4), (c_assDTG_FL_SUN_Y2_LV4_Suv)); + M_MEMCOPY((g_assDTG_FL_SUN_X1_LV4), (c_assDTG_FL_SUN_X1_LV4_Suv)); + M_MEMCOPY((g_assDTG_FL_SUN_X2_LV4), (c_assDTG_FL_SUN_X2_LV4_Suv)); + M_MEMCOPY((g_assINCAR_TG_RL_LV4), (c_assINCAR_TG_RL_LV4_Suv)); + M_MEMCOPY((g_assINCAR_TG_RR_LV4), (c_assINCAR_TG_RR_LV4_Suv)); + M_MEMCOPY((g_assVTG_RL_LV4), (c_assVTG_RL_LV4_Suv)); + M_MEMCOPY((g_assVTG_RR_LV4), (c_assVTG_RR_LV4_Suv)); + M_MEMCOPY((g_assVR_MIN_LV4), (c_assVR_MIN_LV4_Suv)); + M_MEMCOPY((g_assVR_MAX_LV4), (c_assVR_MAX_LV4_Suv)); + M_MEMCOPY((g_assVR_INC_Y1_LV4), (c_assVR_INC_Y1_LV4_Suv)); + M_MEMCOPY((g_assVR_INC_Y2_LV4), (c_assVR_INC_Y2_LV4_Suv)); + M_MEMCOPY((g_assVR_INC_Y3_LV4), (c_assVR_INC_Y3_LV4_Suv)); + M_MEMCOPY((g_assVR_INC_Y4_LV4), (c_assVR_INC_Y4_LV4_Suv)); + M_MEMCOPY((g_assVR_INC_X1_LV4), (c_assVR_INC_X1_LV4_Suv)); + M_MEMCOPY((g_assVR_INC_X2_LV4), (c_assVR_INC_X2_LV4_Suv)); + M_MEMCOPY((g_assVR_INC_X3_LV4), (c_assVR_INC_X3_LV4_Suv)); + M_MEMCOPY((g_assVR_INC_X4_LV4), (c_assVR_INC_X4_LV4_Suv)); + M_MEMCOPY((g_assVR_AMB_Y1_LV4), (c_assVR_AMB_Y1_LV4_Suv)); + M_MEMCOPY((g_assVR_AMB_Y2_LV4), (c_assVR_AMB_Y2_LV4_Suv)); + M_MEMCOPY((g_assVR_AMB_X1_LV4), (c_assVR_AMB_X1_LV4_Suv)); + M_MEMCOPY((g_assVR_AMB_X2_LV4), (c_assVR_AMB_X2_LV4_Suv)); + M_MEMCOPY((g_assVR_SUN_Y1_LV4), (c_assVR_SUN_Y1_LV4_Suv)); + M_MEMCOPY((g_assVR_SUN_Y2_LV4), (c_assVR_SUN_Y2_LV4_Suv)); + M_MEMCOPY((g_assVR_SUN_X1_LV4), (c_assVR_SUN_X1_LV4_Suv)); + M_MEMCOPY((g_assVR_SUN_X2_LV4), (c_assVR_SUN_X2_LV4_Suv)); + M_MEMCOPY((g_assTG_RL_LV4), (c_assTG_RL_LV4_Suv)); + M_MEMCOPY((g_assTG_RR_LV4), (c_assTG_RR_LV4_Suv)); + M_MEMCOPY((g_assDTG_R_MIN_LV4), (c_assDTG_R_MIN_LV4_Suv)); + M_MEMCOPY((g_assDTG_R_MAX_LV4), (c_assDTG_R_MAX_LV4_Suv)); + M_MEMCOPY((g_assDTG_R_INC_Y1_LV4), (c_assDTG_R_INC_Y1_LV4_Suv)); + M_MEMCOPY((g_assDTG_R_INC_Y2_LV4), (c_assDTG_R_INC_Y2_LV4_Suv)); + M_MEMCOPY((g_assDTG_R_INC_Y3_LV4), (c_assDTG_R_INC_Y3_LV4_Suv)); + M_MEMCOPY((g_assDTG_R_INC_Y4_LV4), (c_assDTG_R_INC_Y4_LV4_Suv)); + M_MEMCOPY((g_assDTG_R_INC_X1_LV4), (c_assDTG_R_INC_X1_LV4_Suv)); + M_MEMCOPY((g_assDTG_R_INC_X2_LV4), (c_assDTG_R_INC_X2_LV4_Suv)); + M_MEMCOPY((g_assDTG_R_INC_X3_LV4), (c_assDTG_R_INC_X3_LV4_Suv)); + M_MEMCOPY((g_assDTG_R_INC_X4_LV4), (c_assDTG_R_INC_X4_LV4_Suv)); + M_MEMCOPY((g_assDTG_R_AMB_Y1_LV4), (c_assDTG_R_AMB_Y1_LV4_Suv)); + M_MEMCOPY((g_assDTG_R_AMB_Y2_LV4), (c_assDTG_R_AMB_Y2_LV4_Suv)); + M_MEMCOPY((g_assDTG_R_AMB_X1_LV4), (c_assDTG_R_AMB_X1_LV4_Suv)); + M_MEMCOPY((g_assDTG_R_AMB_X2_LV4), (c_assDTG_R_AMB_X2_LV4_Suv)); + M_MEMCOPY((g_assDTG_R_SUN_Y1_LV4), (c_assDTG_R_SUN_Y1_LV4_Suv)); + M_MEMCOPY((g_assDTG_R_SUN_Y2_LV4), (c_assDTG_R_SUN_Y2_LV4_Suv)); + M_MEMCOPY((g_assDTG_R_SUN_X1_LV4), (c_assDTG_R_SUN_X1_LV4_Suv)); + M_MEMCOPY((g_assDTG_R_SUN_X2_LV4), (c_assDTG_R_SUN_X2_LV4_Suv)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FR_LV4), (c_assCORRECT_DUCT_TIME_FR_LV4_Suv)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FL_LV4), (c_assCORRECT_DUCT_TIME_FL_LV4_Suv)); + M_MEMCOPY((g_assCORRECT_DUCT_RATE_LV4), (c_assCORRECT_DUCT_RATE_LV4_Suv)); + M_MEMCOPY((g_assCORRECT_DUCT_MAX_LV4), (c_assCORRECT_DUCT_MAX_LV4_Suv)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FR_LV4), (c_assCORRECT_AF_TIME_FR_LV4_Suv)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FL_LV4), (c_assCORRECT_AF_TIME_FL_LV4_Suv)); + M_MEMCOPY((g_assCORRECT_AF_RATE_LV4), (c_assCORRECT_AF_RATE_LV4_Suv)); + M_MEMCOPY((g_assCORRECT_AF_MAX_LV4), (c_assCORRECT_AF_MAX_LV4_Suv)); +/* ------------------------------------------Lv4 : End*/ + M_MEMCOPY((g_assINCAR_TG_FL_LV5), (c_assINCAR_TG_FL_LV5_Suv)); + M_MEMCOPY((g_assINCAR_TG_FR_LV5), (c_assINCAR_TG_FR_LV5_Suv)); + M_MEMCOPY((g_assVTG_FL_LV5), (c_assVTG_FL_LV5_Suv)); + M_MEMCOPY((g_assVTG_FR_LV5), (c_assVTG_FR_LV5_Suv)); + M_MEMCOPY((g_assVF_MIN_LV5), (c_assVF_MIN_LV5_Suv)); + M_MEMCOPY((g_assVF_MAX_LV5), (c_assVF_MAX_LV5_Suv)); + M_MEMCOPY((g_assVF_INC_Y1_LV5), (c_assVF_INC_Y1_LV5_Suv)); + M_MEMCOPY((g_assVF_INC_Y2_LV5), (c_assVF_INC_Y2_LV5_Suv)); + M_MEMCOPY((g_assVF_INC_Y3_LV5), (c_assVF_INC_Y3_LV5_Suv)); + M_MEMCOPY((g_assVF_INC_Y4_LV5), (c_assVF_INC_Y4_LV5_Suv)); + M_MEMCOPY((g_assVF_INC_X1_LV5), (c_assVF_INC_X1_LV5_Suv)); + M_MEMCOPY((g_assVF_INC_X2_LV5), (c_assVF_INC_X2_LV5_Suv)); + M_MEMCOPY((g_assVF_INC_X3_LV5), (c_assVF_INC_X3_LV5_Suv)); + M_MEMCOPY((g_assVF_INC_X4_LV5), (c_assVF_INC_X4_LV5_Suv)); + M_MEMCOPY((g_assVF_AMB_Y1_LV5), (c_assVF_AMB_Y1_LV5_Suv)); + M_MEMCOPY((g_assVF_AMB_Y2_LV5), (c_assVF_AMB_Y2_LV5_Suv)); + M_MEMCOPY((g_assVF_AMB_X1_LV5), (c_assVF_AMB_X1_LV5_Suv)); + M_MEMCOPY((g_assVF_AMB_X2_LV5), (c_assVF_AMB_X2_LV5_Suv)); + M_MEMCOPY((g_assVF_SUN_Y1_LV5), (c_assVF_SUN_Y1_LV5_Suv)); + M_MEMCOPY((g_assVF_SUN_Y2_LV5), (c_assVF_SUN_Y2_LV5_Suv)); + M_MEMCOPY((g_assVF_SUN_X1_LV5), (c_assVF_SUN_X1_LV5_Suv)); + M_MEMCOPY((g_assVF_SUN_X2_LV5), (c_assVF_SUN_X2_LV5_Suv)); + M_MEMCOPY((g_assTG_FLU_LV5), (c_assTG_FLU_LV5_Suv)); + M_MEMCOPY((g_assTG_FRU_LV5), (c_assTG_FRU_LV5_Suv)); + M_MEMCOPY((g_assDTG_FU_MIN_LV5), (c_assDTG_FU_MIN_LV5_Suv)); + M_MEMCOPY((g_assDTG_FU_MAX_LV5), (c_assDTG_FU_MAX_LV5_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_Y1_LV5), (c_assDTG_FU_INC_Y1_LV5_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_Y2_LV5), (c_assDTG_FU_INC_Y2_LV5_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_Y3_LV5), (c_assDTG_FU_INC_Y3_LV5_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_Y4_LV5), (c_assDTG_FU_INC_Y4_LV5_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_X1_LV5), (c_assDTG_FU_INC_X1_LV5_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_X2_LV5), (c_assDTG_FU_INC_X2_LV5_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_X3_LV5), (c_assDTG_FU_INC_X3_LV5_Suv)); + M_MEMCOPY((g_assDTG_FU_INC_X4_LV5), (c_assDTG_FU_INC_X4_LV5_Suv)); + M_MEMCOPY((g_assDTG_FU_AMB_Y1_LV5), (c_assDTG_FU_AMB_Y1_LV5_Suv)); + M_MEMCOPY((g_assDTG_FU_AMB_Y2_LV5), (c_assDTG_FU_AMB_Y2_LV5_Suv)); + M_MEMCOPY((g_assDTG_FU_AMB_X1_LV5), (c_assDTG_FU_AMB_X1_LV5_Suv)); + M_MEMCOPY((g_assDTG_FU_AMB_X2_LV5), (c_assDTG_FU_AMB_X2_LV5_Suv)); + M_MEMCOPY((g_assDTG_FU_SUN_Y1_LV5), (c_assDTG_FU_SUN_Y1_LV5_Suv)); + M_MEMCOPY((g_assDTG_FU_SUN_Y2_LV5), (c_assDTG_FU_SUN_Y2_LV5_Suv)); + M_MEMCOPY((g_assDTG_FU_SUN_X1_LV5), (c_assDTG_FU_SUN_X1_LV5_Suv)); + M_MEMCOPY((g_assDTG_FU_SUN_X2_LV5), (c_assDTG_FU_SUN_X2_LV5_Suv)); + M_MEMCOPY((g_assTG_FLL_LV5), (c_assTG_FLL_LV5_Suv)); + M_MEMCOPY((g_assTG_FRL_LV5), (c_assTG_FRL_LV5_Suv)); + M_MEMCOPY((g_assDTG_FL_MIN_LV5), (c_assDTG_FL_MIN_LV5_Suv)); + M_MEMCOPY((g_assDTG_FL_MAX_LV5), (c_assDTG_FL_MAX_LV5_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_Y1_LV5), (c_assDTG_FL_INC_Y1_LV5_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_Y2_LV5), (c_assDTG_FL_INC_Y2_LV5_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_Y3_LV5), (c_assDTG_FL_INC_Y3_LV5_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_Y4_LV5), (c_assDTG_FL_INC_Y4_LV5_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_X1_LV5), (c_assDTG_FL_INC_X1_LV5_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_X2_LV5), (c_assDTG_FL_INC_X2_LV5_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_X3_LV5), (c_assDTG_FL_INC_X3_LV5_Suv)); + M_MEMCOPY((g_assDTG_FL_INC_X4_LV5), (c_assDTG_FL_INC_X4_LV5_Suv)); + M_MEMCOPY((g_assDTG_FL_AMB_Y1_LV5), (c_assDTG_FL_AMB_Y1_LV5_Suv)); + M_MEMCOPY((g_assDTG_FL_AMB_Y2_LV5), (c_assDTG_FL_AMB_Y2_LV5_Suv)); + M_MEMCOPY((g_assDTG_FL_AMB_X1_LV5), (c_assDTG_FL_AMB_X1_LV5_Suv)); + M_MEMCOPY((g_assDTG_FL_AMB_X2_LV5), (c_assDTG_FL_AMB_X2_LV5_Suv)); + M_MEMCOPY((g_assDTG_FL_SUN_Y1_LV5), (c_assDTG_FL_SUN_Y1_LV5_Suv)); + M_MEMCOPY((g_assDTG_FL_SUN_Y2_LV5), (c_assDTG_FL_SUN_Y2_LV5_Suv)); + M_MEMCOPY((g_assDTG_FL_SUN_X1_LV5), (c_assDTG_FL_SUN_X1_LV5_Suv)); + M_MEMCOPY((g_assDTG_FL_SUN_X2_LV5), (c_assDTG_FL_SUN_X2_LV5_Suv)); + M_MEMCOPY((g_assINCAR_TG_RL_LV5), (c_assINCAR_TG_RL_LV5_Suv)); + M_MEMCOPY((g_assINCAR_TG_RR_LV5), (c_assINCAR_TG_RR_LV5_Suv)); + M_MEMCOPY((g_assVTG_RL_LV5), (c_assVTG_RL_LV5_Suv)); + M_MEMCOPY((g_assVTG_RR_LV5), (c_assVTG_RR_LV5_Suv)); + M_MEMCOPY((g_assVR_MIN_LV5), (c_assVR_MIN_LV5_Suv)); + M_MEMCOPY((g_assVR_MAX_LV5), (c_assVR_MAX_LV5_Suv)); + M_MEMCOPY((g_assVR_INC_Y1_LV5), (c_assVR_INC_Y1_LV5_Suv)); + M_MEMCOPY((g_assVR_INC_Y2_LV5), (c_assVR_INC_Y2_LV5_Suv)); + M_MEMCOPY((g_assVR_INC_Y3_LV5), (c_assVR_INC_Y3_LV5_Suv)); + M_MEMCOPY((g_assVR_INC_Y4_LV5), (c_assVR_INC_Y4_LV5_Suv)); + M_MEMCOPY((g_assVR_INC_X1_LV5), (c_assVR_INC_X1_LV5_Suv)); + M_MEMCOPY((g_assVR_INC_X2_LV5), (c_assVR_INC_X2_LV5_Suv)); + M_MEMCOPY((g_assVR_INC_X3_LV5), (c_assVR_INC_X3_LV5_Suv)); + M_MEMCOPY((g_assVR_INC_X4_LV5), (c_assVR_INC_X4_LV5_Suv)); + M_MEMCOPY((g_assVR_AMB_Y1_LV5), (c_assVR_AMB_Y1_LV5_Suv)); + M_MEMCOPY((g_assVR_AMB_Y2_LV5), (c_assVR_AMB_Y2_LV5_Suv)); + M_MEMCOPY((g_assVR_AMB_X1_LV5), (c_assVR_AMB_X1_LV5_Suv)); + M_MEMCOPY((g_assVR_AMB_X2_LV5), (c_assVR_AMB_X2_LV5_Suv)); + M_MEMCOPY((g_assVR_SUN_Y1_LV5), (c_assVR_SUN_Y1_LV5_Suv)); + M_MEMCOPY((g_assVR_SUN_Y2_LV5), (c_assVR_SUN_Y2_LV5_Suv)); + M_MEMCOPY((g_assVR_SUN_X1_LV5), (c_assVR_SUN_X1_LV5_Suv)); + M_MEMCOPY((g_assVR_SUN_X2_LV5), (c_assVR_SUN_X2_LV5_Suv)); + M_MEMCOPY((g_assTG_RL_LV5), (c_assTG_RL_LV5_Suv)); + M_MEMCOPY((g_assTG_RR_LV5), (c_assTG_RR_LV5_Suv)); + M_MEMCOPY((g_assDTG_R_MIN_LV5), (c_assDTG_R_MIN_LV5_Suv)); + M_MEMCOPY((g_assDTG_R_MAX_LV5), (c_assDTG_R_MAX_LV5_Suv)); + M_MEMCOPY((g_assDTG_R_INC_Y1_LV5), (c_assDTG_R_INC_Y1_LV5_Suv)); + M_MEMCOPY((g_assDTG_R_INC_Y2_LV5), (c_assDTG_R_INC_Y2_LV5_Suv)); + M_MEMCOPY((g_assDTG_R_INC_Y3_LV5), (c_assDTG_R_INC_Y3_LV5_Suv)); + M_MEMCOPY((g_assDTG_R_INC_Y4_LV5), (c_assDTG_R_INC_Y4_LV5_Suv)); + M_MEMCOPY((g_assDTG_R_INC_X1_LV5), (c_assDTG_R_INC_X1_LV5_Suv)); + M_MEMCOPY((g_assDTG_R_INC_X2_LV5), (c_assDTG_R_INC_X2_LV5_Suv)); + M_MEMCOPY((g_assDTG_R_INC_X3_LV5), (c_assDTG_R_INC_X3_LV5_Suv)); + M_MEMCOPY((g_assDTG_R_INC_X4_LV5), (c_assDTG_R_INC_X4_LV5_Suv)); + M_MEMCOPY((g_assDTG_R_AMB_Y1_LV5), (c_assDTG_R_AMB_Y1_LV5_Suv)); + M_MEMCOPY((g_assDTG_R_AMB_Y2_LV5), (c_assDTG_R_AMB_Y2_LV5_Suv)); + M_MEMCOPY((g_assDTG_R_AMB_X1_LV5), (c_assDTG_R_AMB_X1_LV5_Suv)); + M_MEMCOPY((g_assDTG_R_AMB_X2_LV5), (c_assDTG_R_AMB_X2_LV5_Suv)); + M_MEMCOPY((g_assDTG_R_SUN_Y1_LV5), (c_assDTG_R_SUN_Y1_LV5_Suv)); + M_MEMCOPY((g_assDTG_R_SUN_Y2_LV5), (c_assDTG_R_SUN_Y2_LV5_Suv)); + M_MEMCOPY((g_assDTG_R_SUN_X1_LV5), (c_assDTG_R_SUN_X1_LV5_Suv)); + M_MEMCOPY((g_assDTG_R_SUN_X2_LV5), (c_assDTG_R_SUN_X2_LV5_Suv)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FR_LV5), (c_assCORRECT_DUCT_TIME_FR_LV5_Suv)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FL_LV5), (c_assCORRECT_DUCT_TIME_FL_LV5_Suv)); + M_MEMCOPY((g_assCORRECT_DUCT_RATE_LV5), (c_assCORRECT_DUCT_RATE_LV5_Suv)); + M_MEMCOPY((g_assCORRECT_DUCT_MAX_LV5), (c_assCORRECT_DUCT_MAX_LV5_Suv)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FR_LV5), (c_assCORRECT_AF_TIME_FR_LV5_Suv)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FL_LV5), (c_assCORRECT_AF_TIME_FL_LV5_Suv)); + M_MEMCOPY((g_assCORRECT_AF_RATE_LV5), (c_assCORRECT_AF_RATE_LV5_Suv)); + M_MEMCOPY((g_assCORRECT_AF_MAX_LV5), (c_assCORRECT_AF_MAX_LV5_Suv)); +/* ------------------------------------------Lv5 : End*/ + M_MEMCOPY((g_assDUCT_TGT_DEF_VALVE_L), (c_assDUCT_TGT_DEF_VALVE_L_Suv)); + M_MEMCOPY((g_assDUCT_TGT_DEF_VALVE_R), (c_assDUCT_TGT_DEF_VALVE_R_Suv)); +/* ------------------------------------------DuctTgt Increase : End*/ + M_MEMCOPY((g_assAMB_LV_UP), (c_assAMB_LV_UP_Suv)); + M_MEMCOPY((g_assAMB_LV_DN), (c_assAMB_LV_DN_Suv)); + M_MEMCOPY((g_assAMB_LV_TG), (c_assAMB_LV_TG_Suv)); +/* ------------------------------------------Ambient LEVEL : End*/ + M_MEMCOPY((g_aucMODE_BY_SET_F_LV0), (c_aucMODE_BY_SET_F_LV0_Suv)); + M_MEMCOPY((g_aucMODE_BY_SET_F_LV1), (c_aucMODE_BY_SET_F_LV1_Suv)); + M_MEMCOPY((g_aucMODE_BY_SET_F_LV2), (c_aucMODE_BY_SET_F_LV2_Suv)); + M_MEMCOPY((g_aucMODE_BY_SET_F_LV3), (c_aucMODE_BY_SET_F_LV3_Suv)); + M_MEMCOPY((g_aucMODE_BY_SET_F_LV4), (c_aucMODE_BY_SET_F_LV4_Suv)); + M_MEMCOPY((g_aucMODE_BY_SET_F_LV5), (c_aucMODE_BY_SET_F_LV5_Suv)); + M_MEMCOPY((g_ausMODE_BY_DUCT_TG_R_LV0), (c_ausMODE_BY_DUCT_TG_R_LV0_Suv)); + M_MEMCOPY((g_ausMODE_BY_DUCT_TG_R_LV1), (c_ausMODE_BY_DUCT_TG_R_LV1_Suv)); + M_MEMCOPY((g_ausMODE_BY_DUCT_TG_R_LV2), (c_ausMODE_BY_DUCT_TG_R_LV2_Suv)); + M_MEMCOPY((g_ausMODE_BY_DUCT_TG_R_LV3), (c_ausMODE_BY_DUCT_TG_R_LV3_Suv)); + M_MEMCOPY((g_ausMODE_BY_DUCT_TG_R_LV4), (c_ausMODE_BY_DUCT_TG_R_LV4_Suv)); + M_MEMCOPY((g_ausMODE_BY_DUCT_TG_R_LV5), (c_ausMODE_BY_DUCT_TG_R_LV5_Suv)); +/* ------------------------------------------Mode depend on SET for each level : End*/ + g_ssPREC_REC_ON_AMB = c_ssPREC_REC_ON_AMB_Suv; + g_ssPREC_REC_OFF_AMB = c_ssPREC_REC_OFF_AMB_Suv; + M_MEMCOPY((g_aucPREC_VEH_SPD_OSA), (c_aucPREC_VEH_SPD_OSA_Suv)); + M_MEMCOPY((g_assPRE_AMB_RANGE_WINTER), (c_assPRE_AMB_RANGE_WINTER_Suv)); + M_MEMCOPY((g_aucPREC_OSA_WINTER), (c_aucPREC_OSA_WINTER_Suv)); + M_MEMCOPY((g_aucPREC_REC_WINTER), (c_aucPREC_REC_WINTER_Suv)); + M_MEMCOPY((g_ausPREC_HUMIDITY_NOK), (c_ausPREC_HUMIDITY_NOK_Suv)); + M_MEMCOPY((g_ausPREC_HUMIDITY_OK), (c_ausPREC_HUMIDITY_OK_Suv)); + M_MEMCOPY((g_ausPREC_ENTRY_RPM), (c_ausPREC_ENTRY_RPM_Suv)); + M_MEMCOPY((g_ausPREC_EXIT_RPM), (c_ausPREC_EXIT_RPM_Suv)); + M_MEMCOPY((g_ausPREC_COMP_SPD_1), (c_ausPREC_COMP_SPD_1_Suv)); + M_MEMCOPY((g_aucPREC_OSA_SUMMER_1), (c_aucPREC_OSA_SUMMER_1_Suv)); + M_MEMCOPY((g_aucPREC_REC_SUMMER_1), (c_aucPREC_REC_SUMMER_1_Suv)); + M_MEMCOPY((g_assPREC_EVA_DIFF_FB_TG_F), (c_assPREC_EVA_DIFF_FB_TG_F_Suv)); + M_MEMCOPY((g_aucPREC_OSA_SUMMER_2), (c_aucPREC_OSA_SUMMER_2_Suv)); + M_MEMCOPY((g_aucPREC_REC_SUMMER_2), (c_aucPREC_REC_SUMMER_2_Suv)); + M_MEMCOPY((g_aucPREC_EVA_DIFF), (c_aucPREC_EVA_DIFF_Suv)); + g_ucPREC_OSA_SUMMER_3 = c_ucPREC_OSA_SUMMER_3_Suv; + g_ucPREC_REC_SUMMER_3 = c_ucPREC_REC_SUMMER_3_Suv; +/* ------------------------------------------AutoRec : End*/ + M_MEMCOPY((g_ausFLOW_FR_VE2VALVE), (c_ausFLOW_FR_VE2VALVE_Suv)); + M_MEMCOPY((g_ausFLOW_FR_BIVALVE), (c_ausFLOW_FR_BIVALVE_Suv)); + M_MEMCOPY((g_ausFLOW_FR_BI2VALVE), (c_ausFLOW_FR_BI2VALVE_Suv)); + M_MEMCOPY((g_ausFLOW_FR_AF2VALVE), (c_ausFLOW_FR_AF2VALVE_Suv)); + M_MEMCOPY((g_ausFLOW_FR_AF2VALVE_SUMMER), (c_ausFLOW_FR_AF2VALVE_SUMMER_Suv)); + M_MEMCOPY((g_ausFLOW_FR_FO2VALVE), (c_ausFLOW_FR_FO2VALVE_Suv)); + M_MEMCOPY((g_ausFLOW_FR_FD2VALVE), (c_ausFLOW_FR_FD2VALVE_Suv)); + M_MEMCOPY((g_ausFLOW_FR_DE2VALVE), (c_ausFLOW_FR_DE2VALVE_Suv)); + M_MEMCOPY((g_ausFLOW_FR_TR2VALVE), (c_ausFLOW_FR_TR2VALVE_Suv)); + M_MEMCOPY((g_ausFLOW_FR_HI2VALVE), (c_ausFLOW_FR_HI2VALVE_Suv)); + M_MEMCOPY((g_ausFLOW_FR_BIVALVE_MANUAL), (c_ausFLOW_FR_BIVALVE_MANUAL_Suv)); + M_MEMCOPY((g_ausFLOW_RE_VENT), (c_ausFLOW_RE_VENT_Suv)); + M_MEMCOPY((g_ausFLOW_RE_BI2VALVE), (c_ausFLOW_RE_BI2VALVE_Suv)); + M_MEMCOPY((g_ausFLOW_RE_FO2VALVE), (c_ausFLOW_RE_FO2VALVE_Suv)); + M_MEMCOPY((g_ausFLOW_RE_VENT_2), (c_ausFLOW_RE_VENT_2_Suv)); + M_MEMCOPY((g_ausFLOW_RE_BI2VALVE_2), (c_ausFLOW_RE_BI2VALVE_2_Suv)); + M_MEMCOPY((g_ausFLOW_RE_VENT_3), (c_ausFLOW_RE_VENT_3_Suv)); + M_MEMCOPY((g_ausFLOW_RE_BI2VALVE_3), (c_ausFLOW_RE_BI2VALVE_3_Suv)); + M_MEMCOPY((g_ausFLOW_RE_VENT_MANUAL), (c_ausFLOW_RE_VENT_MANUAL_Suv)); + M_MEMCOPY((g_ausFLOW_RE_BI2VALVE_MANUAL), (c_ausFLOW_RE_BI2VALVE_MANUAL_Suv)); +/* ------------------------------------------Flow Control Valve: End*/ + M_MEMCOPY((g_assFLOW_BI_AMB_TGT), (c_assFLOW_BI_AMB_TGT_Suv)); + M_MEMCOPY((g_aucFLOW_BI_VENT_PLUS), (c_aucFLOW_BI_VENT_PLUS_Suv)); + M_MEMCOPY((g_assFLOW_BI_TEMP_TGT), (c_assFLOW_BI_TEMP_TGT_Suv)); + M_MEMCOPY((g_aucFLOW_BI_FOOT_PLUS), (c_aucFLOW_BI_FOOT_PLUS_Suv)); + M_MEMCOPY((g_aucFLOW_BI_VENT_VALVE_MAX), (c_aucFLOW_BI_VENT_VALVE_MAX_Suv)); + M_MEMCOPY((g_aucFLOW_BI_FOOT_VALVE_MAX), (c_aucFLOW_BI_FOOT_VALVE_MAX_Suv)); + M_MEMCOPY((g_aucFLOW_BI_VENT_VALVE_MIN), (c_aucFLOW_BI_VENT_VALVE_MIN_Suv)); + M_MEMCOPY((g_aucFLOW_BI_FOOT_VALVE_MIN), (c_aucFLOW_BI_FOOT_VALVE_MIN_Suv)); +/* ------------------------------------------Bi 2 level conditions: End*/ + M_MEMCOPY((g_assFLOW_B2I_AMB_TGT), (c_assFLOW_B2I_AMB_TGT_Suv)); + M_MEMCOPY((g_aucFLOW_BI2_VENT_PLUS), (c_aucFLOW_BI2_VENT_PLUS_Suv)); + M_MEMCOPY((g_assFLOW_BI2_TEMP_TGT), (c_assFLOW_BI2_TEMP_TGT_Suv)); + M_MEMCOPY((g_aucFLOW_BI2_FOOT_PLUS), (c_aucFLOW_BI2_FOOT_PLUS_Suv)); + M_MEMCOPY((g_aucFLOW_BI2_VENT_VALVE_MAX), (c_aucFLOW_BI2_VENT_VALVE_MAX_Suv)); + M_MEMCOPY((g_aucFLOW_BI2_FOOT_VALVE_MAX), (c_aucFLOW_BI2_FOOT_VALVE_MAX_Suv)); + M_MEMCOPY((g_aucFLOW_BI2_VENT_VALVE_MIN), (c_aucFLOW_BI2_VENT_VALVE_MIN_Suv)); + M_MEMCOPY((g_aucFLOW_BI2_FOOT_VALVE_MIN), (c_aucFLOW_BI2_FOOT_VALVE_MIN_Suv)); +/* ------------------------------------------AF level conditions: End*/ + M_MEMCOPY((g_assFLOW_AF_AMB_TGT), (c_assFLOW_AF_AMB_TGT_Suv)); + M_MEMCOPY((g_aucFLOW_AF_VENT_PLUS), (c_aucFLOW_AF_VENT_PLUS_Suv)); + M_MEMCOPY((g_aucFLOW_AF_BLR_AF_TGT), (c_aucFLOW_AF_BLR_AF_TGT_Suv)); + M_MEMCOPY((g_aucFLOW_AF_FOOT_PLUS), (c_aucFLOW_AF_FOOT_PLUS_Suv)); + M_MEMCOPY((g_aucFLOW_AF_VENT_VALVE_MAX), (c_aucFLOW_AF_VENT_VALVE_MAX_Suv)); + M_MEMCOPY((g_aucFLOW_AF_FOOT_VALVE_MAX), (c_aucFLOW_AF_FOOT_VALVE_MAX_Suv)); +/* ------------------------------------------AF level conditions: End*/ + M_MEMCOPY((g_assFLOW_AFSM_AMB_TGT), (c_assFLOW_AFSM_AMB_TGT_Suv)); + M_MEMCOPY((g_aucFLOW_AFSM_VENT_PLUS), (c_aucFLOW_AFSM_VENT_PLUS_Suv)); + M_MEMCOPY((g_assFLOW_AFSM_TEMP_TGT), (c_assFLOW_AFSM_TEMP_TGT_Suv)); + M_MEMCOPY((g_aucFLOW_AFSM_FOOT_PLUS), (c_aucFLOW_AFSM_FOOT_PLUS_Suv)); + M_MEMCOPY((g_aucFLOW_AFSM_VENT_VALVE_MAX), (c_aucFLOW_AFSM_VENT_VALVE_MAX_Suv)); + M_MEMCOPY((g_aucFLOW_AFSM_FOOT_VALVE_MAX), (c_aucFLOW_AFSM_FOOT_VALVE_MAX_Suv)); +/* ------------------------------------------AF_summer level conditions: End*/ + M_MEMCOPY((g_aucMODE_INDEX), (c_aucMODE_INDEX_Suv)); + M_MEMCOPY((g_assFOOT_STEP_DUCT_TGT), (c_assFOOT_STEP_DUCT_TGT_Suv)); + M_MEMCOPY((g_assBLR_FOOT_IND), (c_assBLR_FOOT_IND_Suv)); + M_MEMCOPY((g_ascFOOT_STEP_VALVE_P1), (c_ascFOOT_STEP_VALVE_P1_Suv)); + M_MEMCOPY((g_ascFOOT_STEP_VALVE_P2), (c_ascFOOT_STEP_VALVE_P2_Suv)); + M_MEMCOPY((g_ascFOOT_STEP_VALVE_P3), (c_ascFOOT_STEP_VALVE_P3_Suv)); + M_MEMCOPY((g_ascFOOT_STEP_VALVE_M1), (c_ascFOOT_STEP_VALVE_M1_Suv)); + M_MEMCOPY((g_ascFOOT_STEP_VALVE_M2), (c_ascFOOT_STEP_VALVE_M2_Suv)); + M_MEMCOPY((g_ascFOOT_STEP_VALVE_M3), (c_ascFOOT_STEP_VALVE_M3_Suv)); + M_MEMCOPY((g_assFOOT_STEP_BLR_P1), (c_assFOOT_STEP_BLR_P1_Suv)); + M_MEMCOPY((g_assFOOT_STEP_BLR_P2), (c_assFOOT_STEP_BLR_P2_Suv)); + M_MEMCOPY((g_assFOOT_STEP_BLR_P3), (c_assFOOT_STEP_BLR_P3_Suv)); + M_MEMCOPY((g_assFOOT_STEP_BLR_M1), (c_assFOOT_STEP_BLR_M1_Suv)); + M_MEMCOPY((g_assFOOT_STEP_BLR_M2), (c_assFOOT_STEP_BLR_M2_Suv)); + M_MEMCOPY((g_assFOOT_STEP_BLR_M3), (c_assFOOT_STEP_BLR_M3_Suv)); +/* ------------------------------------------Individual foot temperature: End*/ + M_MEMCOPY((g_aucREAR_FOOT_VALVE_AMB_LV2), (c_aucREAR_FOOT_VALVE_AMB_LV2_Suv)); + M_MEMCOPY((g_aucREAR_FOOT_VALVE_AMB_LV3), (c_aucREAR_FOOT_VALVE_AMB_LV3_Suv)); + M_MEMCOPY((g_aucREAR_FOOT_VALVE_AMB_LV4), (c_aucREAR_FOOT_VALVE_AMB_LV4_Suv)); +/* ------------------------------------------Blowing foots from Rear HVAC: End*/ + M_MEMCOPY((g_ausFLOW_FR_VE2BLR_AF), (c_ausFLOW_FR_VE2BLR_AF_Suv)); + M_MEMCOPY((g_ausFLOW_FR_BIVALVE_AF), (c_ausFLOW_FR_BIVALVE_AF_Suv)); + M_MEMCOPY((g_ausFLOW_FR_BI2BLR_AF), (c_ausFLOW_FR_BI2BLR_AF_Suv)); + M_MEMCOPY((g_ausFLOW_FR_FO2BLR_AF), (c_ausFLOW_FR_FO2BLR_AF_Suv)); + M_MEMCOPY((g_ausFLOW_FR_AF2VALVE_AF), (c_ausFLOW_FR_AF2VALVE_AF_Suv)); + M_MEMCOPY((g_ausFLOW_FR_AF2VALVE_SUMMER_AF), (c_ausFLOW_FR_AF2VALVE_SUMMER_AF_Suv)); + M_MEMCOPY((g_ausFLOW_FR_FD2BLR_AF), (c_ausFLOW_FR_FD2BLR_AF_Suv)); + M_MEMCOPY((g_ausFLOW_FR_DE2BLR_AF), (c_ausFLOW_FR_DE2BLR_AF_Suv)); + M_MEMCOPY((g_ausFLOW_FR_TR2BLR_AF), (c_ausFLOW_FR_TR2BLR_AF_Suv)); + M_MEMCOPY((g_ausFLOW_FR_HI2BLR_AF), (c_ausFLOW_FR_HI2BLR_AF_Suv)); + M_MEMCOPY((g_ausFLOW_RE_VE2BLR_AF), (c_ausFLOW_RE_VE2BLR_AF_Suv)); + M_MEMCOPY((g_ausFLOW_RE_BI2BLR_AF), (c_ausFLOW_RE_BI2BLR_AF_Suv)); + M_MEMCOPY((g_ausFLOW_RE_FO2BLR_AF), (c_ausFLOW_RE_FO2BLR_AF_Suv)); +/* ------------------------------------------Flow Control AF: End*/ + M_MEMCOPY((g_ascAUTO_STEP_AF_F), (c_ascAUTO_STEP_AF_F_Suv)); + M_MEMCOPY((g_ascAUTO_STEP_AF_R), (c_ascAUTO_STEP_AF_R_Suv)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_U_F_LV0_1), (c_assAUTO_STEP_DUCT_TG_U_F_LV0_1_Suv)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_U_F_LV2_3), (c_assAUTO_STEP_DUCT_TG_U_F_LV2_3_Suv)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_U_F_LV4_5), (c_assAUTO_STEP_DUCT_TG_U_F_LV4_5_Suv)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_L_F_LV0_1), (c_assAUTO_STEP_DUCT_TG_L_F_LV0_1_Suv)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_L_F_LV2_3), (c_assAUTO_STEP_DUCT_TG_L_F_LV2_3_Suv)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_L_F_LV4_5), (c_assAUTO_STEP_DUCT_TG_L_F_LV4_5_Suv)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_R_LV0_1), (c_assAUTO_STEP_DUCT_TG_R_LV0_1_Suv)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_R_LV2_3), (c_assAUTO_STEP_DUCT_TG_R_LV2_3_Suv)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_R_LV4_5), (c_assAUTO_STEP_DUCT_TG_R_LV4_5_Suv)); +/* ------------------------------------------5 AUTO mode: End*/ + M_MEMCOPY((g_ausVALVE_SPACE), (c_ausVALVE_SPACE_Suv)); + M_MEMCOPY((g_aucVALVE_SECTION_S1_F_SIDE_VENT), (c_aucVALVE_SECTION_S1_F_SIDE_VENT_Suv)); + M_MEMCOPY((g_aucVALVE_SECTION_S1_F_CENT_VENT), (c_aucVALVE_SECTION_S1_F_CENT_VENT_Suv)); + M_MEMCOPY((g_aucVALVE_SECTION_S1_F_DRIVER_FOOT), (c_aucVALVE_SECTION_S1_F_DRIVER_FOOT_Suv)); + M_MEMCOPY((g_aucVALVE_SECTION_S1_F_RIGHT_PASS), (c_aucVALVE_SECTION_S1_F_RIGHT_PASS_Suv)); + M_MEMCOPY((g_aucBLR_SPD_V1_1_F), (c_aucBLR_SPD_V1_1_F_Suv)); + M_MEMCOPY((g_aucBLR_SPD_K2_1_F_SIDE_VENT), (c_aucBLR_SPD_K2_1_F_SIDE_VENT_Suv)); + M_MEMCOPY((g_aucBLR_SPD_K2_2_F_CENT_VENT), (c_aucBLR_SPD_K2_2_F_CENT_VENT_Suv)); + M_MEMCOPY((g_aucBLR_SPD_K2_3_F_DRIVER_FOOT), (c_aucBLR_SPD_K2_3_F_DRIVER_FOOT_Suv)); + M_MEMCOPY((g_aucBLR_SPD_K2_4_F_RIGHT_PASS), (c_aucBLR_SPD_K2_4_F_RIGHT_PASS_Suv)); + M_MEMCOPY((g_ausVALVE_VEH_SPD), (c_ausVALVE_VEH_SPD_Suv)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_SIDE_VENT), (c_aucVALVE_VEH_SPD_SIDE_VENT_Suv)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_SIDE_BI), (c_aucVALVE_VEH_SPD_SIDE_BI_Suv)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_SIDE_AFOOT), (c_aucVALVE_VEH_SPD_SIDE_AFOOT_Suv)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_CNET_VENT), (c_aucVALVE_VEH_SPD_CNET_VENT_Suv)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_CENT_BI), (c_aucVALVE_VEH_SPD_CENT_BI_Suv)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_CENT_AFOOT), (c_aucVALVE_VEH_SPD_CENT_AFOOT_Suv)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_FOOT_BI), (c_aucVALVE_VEH_SPD_FOOT_BI_Suv)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_FOOT_AFOOT), (c_aucVALVE_VEH_SPD_FOOT_AFOOT_Suv)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_2FOOT), (c_aucVALVE_VEH_SPD_2FOOT_Suv)); + M_MEMCOPY((g_aucBLR_SPD_VEH_SPD_V1_3), (c_aucBLR_SPD_VEH_SPD_V1_3_Suv)); + M_MEMCOPY((g_aucFRONT_SIDE_DRS_PERCENT), (c_aucFRONT_SIDE_DRS_PERCENT_Suv)); + M_MEMCOPY((g_aucFRONT_CENT_DRS_PERCENT), (c_aucFRONT_CENT_DRS_PERCENT_Suv)); +/* ------------------------------------------Different blower speed FRONT MODE: End*/ + M_MEMCOPY((g_aucVALVE_S1_R_BIPILLAR), (c_aucVALVE_S1_R_BIPILLAR_Suv)); + M_MEMCOPY((g_aucVALVE_S1_R_CENT_VENT), (c_aucVALVE_S1_R_CENT_VENT_Suv)); + M_MEMCOPY((g_aucVALVE_S1_R_FOOT), (c_aucVALVE_S1_R_FOOT_Suv)); + M_MEMCOPY((g_aucVALVE_PERC_R_BIPILLAR), (c_aucVALVE_PERC_R_BIPILLAR_Suv)); + M_MEMCOPY((g_aucVALVE_PERC_R_CENT_VENT), (c_aucVALVE_PERC_R_CENT_VENT_Suv)); + M_MEMCOPY((g_aucVALVE_PERC_R_FOOT), (c_aucVALVE_PERC_R_FOOT_Suv)); + M_MEMCOPY((g_aucBLR_SPD_V1_1_R), (c_aucBLR_SPD_V1_1_R_Suv)); + M_MEMCOPY((g_aucREAR_CEN_MIN_VALUE_BY_DRS_ZERO), (c_aucREAR_CEN_MIN_VALUE_BY_DRS_ZERO_Suv)); + M_MEMCOPY((g_aucBLR_SPD_K2_1_R_BIPILLAR_MIN), (c_aucBLR_SPD_K2_1_R_BIPILLAR_MIN_Suv)); + M_MEMCOPY((g_aucBLR_SPD_K2_2_R_CENT_VENT_MIN), (c_aucBLR_SPD_K2_2_R_CENT_VENT_MIN_Suv)); + M_MEMCOPY((g_aucBLR_SPD_K2_3_R_FOOT_MIN), (c_aucBLR_SPD_K2_3_R_FOOT_MIN_Suv)); + M_MEMCOPY((g_aucBLR_SPD_K2_1_R_BIPILLAR_MAX), (c_aucBLR_SPD_K2_1_R_BIPILLAR_MAX_Suv)); + M_MEMCOPY((g_aucBLR_SPD_K2_2_R_CENT_VENTR_MAX), (c_aucBLR_SPD_K2_2_R_CENT_VENTR_MAX_Suv)); + M_MEMCOPY((g_aucBLR_SPD_K2_3_R_FOOTR_MAX), (c_aucBLR_SPD_K2_3_R_FOOTR_MAX_Suv)); + M_MEMCOPY((g_aucREAR_SIDE_DRS_PERCENT_VALVE), (c_aucREAR_SIDE_DRS_PERCENT_VALVE_Suv)); + M_MEMCOPY((g_aucREAR_CENT_DRS_PERCENT_VALVE), (c_aucREAR_CENT_DRS_PERCENT_VALVE_Suv)); + M_MEMCOPY((g_aucREAR_SIDE_DRS_PERCENT_AF), (c_aucREAR_SIDE_DRS_PERCENT_AF_Suv)); + M_MEMCOPY((g_aucREAR_CENT_DRS_PERCENT_AF), (c_aucREAR_CENT_DRS_PERCENT_AF_Suv)); +/* ------------------------------------------Different blower speed REAR MODE: End*/ + M_MEMCOPY((g_ausMIN_PWM), (c_ausMIN_PWM_Suv)); +/* ------------------------------------------MinPWM: End*/ + M_MEMCOPY((g_assSTART_ENTER_COOLANT), (c_assSTART_ENTER_COOLANT_Suv)); + M_MEMCOPY((g_assSTART_COOLANT_STEP0_TO_1), (c_assSTART_COOLANT_STEP0_TO_1_Suv)); + M_MEMCOPY((g_assSTART_COOLANT_TO_STEP2), (c_assSTART_COOLANT_TO_STEP2_Suv)); + M_MEMCOPY((g_assSTART_COOLANT_STEP1_BLR_F), (c_assSTART_COOLANT_STEP1_BLR_F_Suv)); + M_MEMCOPY((g_assSTART_COOLANT_STEP1_BLR_R), (c_assSTART_COOLANT_STEP1_BLR_R_Suv)); + M_MEMCOPY((g_assSTART_ENTER_INCAR), (c_assSTART_ENTER_INCAR_Suv)); + M_MEMCOPY((g_ausSTART_ENTER_SETTEMP), (c_ausSTART_ENTER_SETTEMP_Suv)); + M_MEMCOPY((g_aucSTART_INCAR_FLT_UP), (c_aucSTART_INCAR_FLT_UP_Suv)); + M_MEMCOPY((g_aucSTART_INCAR_FLT_DN), (c_aucSTART_INCAR_FLT_DN_Suv)); + M_MEMCOPY((g_aucSTART_VALVE_IDX_STEP1), (c_aucSTART_VALVE_IDX_STEP1_Suv)); + M_MEMCOPY((g_aucSTART_AUTODEMIST2_STEP2), (c_aucSTART_AUTODEMIST2_STEP2_Suv)); + M_MEMCOPY((g_aucSTART_ELEC_WINDOW), (c_aucSTART_ELEC_WINDOW_Suv)); + M_MEMCOPY((g_ausSTART_BLR_AF_STEP12_F), (c_ausSTART_BLR_AF_STEP12_F_Suv)); + M_MEMCOPY((g_ausSTART_BLR_AF_STEP12_R), (c_ausSTART_BLR_AF_STEP12_R_Suv)); + M_MEMCOPY((g_ausSTART_BLR_SPD_STEP2_F), (c_ausSTART_BLR_SPD_STEP2_F_Suv)); + M_MEMCOPY((g_ausSTART_BLR_SPD_STEP2_R), (c_ausSTART_BLR_SPD_STEP2_R_Suv)); + M_MEMCOPY((g_aucSTART_DUCT_TGT_STEP2_FX_U), (c_aucSTART_DUCT_TGT_STEP2_FX_U_Suv)); + M_MEMCOPY((g_aucSTART_DUCT_TGT_STEP2_FX_L), (c_aucSTART_DUCT_TGT_STEP2_FX_L_Suv)); + M_MEMCOPY((g_aucSTART_DUCT_TGT_STEP2_RX), (c_aucSTART_DUCT_TGT_STEP2_RX_Suv)); + M_MEMCOPY((g_aucSTART_VALVE_CHANGE_SPD_F), (c_aucSTART_VALVE_CHANGE_SPD_F_Suv)); + M_MEMCOPY((g_aucSTART_VALVE_CHANGE_SPD_R), (c_aucSTART_VALVE_CHANGE_SPD_R_Suv)); + M_MEMCOPY((g_ausSTART_TIME_STEP1_TO_2), (c_ausSTART_TIME_STEP1_TO_2_Suv)); + M_MEMCOPY((g_ausSTART_TIME_STEP2_TO_3), (c_ausSTART_TIME_STEP2_TO_3_Suv)); + M_MEMCOPY((g_assSTART_INCAR_STEP1_TO_2), (c_assSTART_INCAR_STEP1_TO_2_Suv)); + M_MEMCOPY((g_assSTART_INCAR_STEP2_TO_3), (c_assSTART_INCAR_STEP2_TO_3_Suv)); + M_MEMCOPY((g_aucSTART_3WAY_OPEN), (c_aucSTART_3WAY_OPEN_Suv)); + M_MEMCOPY((g_aucSTART_2WAY_OPEN), (c_aucSTART_2WAY_OPEN_Suv)); + M_MEMCOPY((g_aucSTART_TXV_F), (c_aucSTART_TXV_F_Suv)); + M_MEMCOPY((g_aucSTART_TXV_R), (c_aucSTART_TXV_R_Suv)); +/* ------------------------------------------Start control: End*/ + M_MEMCOPY((g_assFAILURE_AMB_TEMP), (c_assFAILURE_AMB_TEMP_Suv)); + M_MEMCOPY((g_assAC_PRESSURE_LOW_HYS_UP), (c_assAC_PRESSURE_LOW_HYS_UP_Suv)); + M_MEMCOPY((g_assAC_PRESSURE_LOW_HYS_DN), (c_assAC_PRESSURE_LOW_HYS_DN_Suv)); + M_MEMCOPY((g_assAC_LOW_AMB_F), (c_assAC_LOW_AMB_F_Suv)); + M_MEMCOPY((g_assAC_CUT_OFF_AMB_F), (c_assAC_CUT_OFF_AMB_F_Suv)); + M_MEMCOPY((g_assAC_WINTER_TXV_DEWPOINT), (c_assAC_WINTER_TXV_DEWPOINT_Suv)); + M_MEMCOPY((g_assAC_CUT_OFF_AMB_R), (c_assAC_CUT_OFF_AMB_R_Suv)); + M_MEMCOPY((g_assEVA_TG_AMB_F), (c_assEVA_TG_AMB_F_Suv)); + M_MEMCOPY((g_assEVA_TG_AMB_R), (c_assEVA_TG_AMB_R_Suv)); + g_ucAC_EXTRA_RPM = c_ucAC_EXTRA_RPM_Suv; + M_MEMCOPY((g_assAC_EVA_LV_SHUT_OFF), (c_assAC_EVA_LV_SHUT_OFF_Suv)); + M_MEMCOPY((g_assAC_PRESSURE_HYS_HI_ENG_ON), (c_assAC_PRESSURE_HYS_HI_ENG_ON_Suv)); + g_usCMP_MAX_ENG_OFF = c_usCMP_MAX_ENG_OFF_Suv; + g_ucFAN_MAX_ENG_OFF = c_ucFAN_MAX_ENG_OFF_Suv; + g_ssAC_WINTER_TXV_HYST = c_ssAC_WINTER_TXV_HYST_Suv; + M_MEMCOPY((g_aucAC_PRESSURE_HYS_HI_ENG_OFF), (c_aucAC_PRESSURE_HYS_HI_ENG_OFF_Suv)); + M_MEMCOPY((g_ausCMP_RPM_RESONANCE), (c_ausCMP_RPM_RESONANCE_Suv)); +/* ------------------------------------------A/C Control Pressure : End*/ + M_MEMCOPY((g_assPRESSURE_TO_FAN_X), (c_assPRESSURE_TO_FAN_X_Suv)); + M_MEMCOPY((g_aucPRESSURE_TO_FAN_Y), (c_aucPRESSURE_TO_FAN_Y_Suv)); +/* ------------------------------------------CoolingFan: End*/ + g_ssREST_BATT = c_ssREST_BATT_Suv; + g_ssRESTW_AMB = c_ssRESTW_AMB_Suv; + M_MEMCOPY((g_assRESTW_WATER), (c_assRESTW_WATER_Suv)); + g_usRESTW_READYEXPIRETIME = c_usRESTW_READYEXPIRETIME_Suv; + M_MEMCOPY((g_aucRESTW_MODE), (c_aucRESTW_MODE_Suv)); + g_usRESTW_TIMEOUTTIME = c_usRESTW_TIMEOUTTIME_Suv; + g_ucRESTW_BLRSTEP = c_ucRESTW_BLRSTEP_Suv; + g_ssRESTS_AMB = c_ssRESTS_AMB_Suv; + g_uctRESTS_READYEXPIRETIME = c_uctRESTS_READYEXPIRETIME_Suv; + M_MEMCOPY((g_aucRESTS_MODE), (c_aucRESTS_MODE_Suv)); + g_usRESTS_TIMEOUTTIME = c_usRESTS_TIMEOUTTIME_Suv; + g_ucRESTS_BLRSTEP = c_ucRESTS_BLRSTEP_Suv; +/* ------------------------------------------Rest mode: End*/ + g_usFRESH_AIR_PURGE_ENTRY_TIME = c_usFRESH_AIR_PURGE_ENTRY_TIME_Suv; + M_MEMCOPY((g_ausFRESH_AIR_PURGE_CHANGE_TIME), (c_ausFRESH_AIR_PURGE_CHANGE_TIME_Suv)); +/* ------------------------------------------Purge Rec: End*/ + M_MEMCOPY((g_assMAX_DEF_U_DTG), (c_assMAX_DEF_U_DTG_Suv)); + M_MEMCOPY((g_ausMAX_BLR_SPD), (c_ausMAX_BLR_SPD_Suv)); +/* ------------------------------------------MAX DEF: End*/ + M_MEMCOPY((g_aucAQS_REC_LV_CO), (c_aucAQS_REC_LV_CO_Suv)); + M_MEMCOPY((g_aucAQS_OSA_LV_CO), (c_aucAQS_OSA_LV_CO_Suv)); + M_MEMCOPY((g_aucAQS_REC_LV_NOX), (c_aucAQS_REC_LV_NOX_Suv)); + M_MEMCOPY((g_aucAQS_OSA_LV_NOX), (c_aucAQS_OSA_LV_NOX_Suv)); + M_MEMCOPY((g_aucAQS_REC_LV_NH3), (c_aucAQS_REC_LV_NH3_Suv)); + M_MEMCOPY((g_aucAQS_OSA_LV_NH3), (c_aucAQS_OSA_LV_NH3_Suv)); + g_ucAQS_REC_ON_TIME = c_ucAQS_REC_ON_TIME_Suv; + M_MEMCOPY((g_aucAQS_REC_ON_WAIT), (c_aucAQS_REC_ON_WAIT_Suv)); +/* ------------------------------------------Aqs: End*/ + g_usAUTODEMIST_LV2_BLR_PLUS = c_usAUTODEMIST_LV2_BLR_PLUS_Suv; + g_usAUTODEMIST_LV3_BLR_PLUS = c_usAUTODEMIST_LV3_BLR_PLUS_Suv; + M_MEMCOPY((g_assAUTODEMIST_OFFSET_AMB_TEMP), (c_assAUTODEMIST_OFFSET_AMB_TEMP_Suv)); + M_MEMCOPY((g_assAUTODEMIST_OFFSET_VENT_TEMP), (c_assAUTODEMIST_OFFSET_VENT_TEMP_Suv)); + M_MEMCOPY((g_assAUTODEMIST_STEP_UP), (c_assAUTODEMIST_STEP_UP_Suv)); + M_MEMCOPY((g_assAUTODEMIST_STEP_DN), (c_assAUTODEMIST_STEP_DN_Suv)); + M_MEMCOPY((g_assAUTODEMIST_WINTER), (c_assAUTODEMIST_WINTER_Suv)); +/* ------------------------------------------Auto Demist: End*/ + g_ssAUTODEMIST_ELEC_AMB_ENTRY = c_ssAUTODEMIST_ELEC_AMB_ENTRY_Suv; + M_MEMCOPY((g_assAUTODEMIST_ELEC_WINDSHELD_TEMP), (c_assAUTODEMIST_ELEC_WINDSHELD_TEMP_Suv)); +/* ------------------------------------------Electric AutoDemist: End*/ + g_ssAMBFILT_WATER = c_ssAMBFILT_WATER_Suv; + M_MEMCOPY((g_aucAMBFILT_H_CNT), (c_aucAMBFILT_H_CNT_Suv)); + g_ssAMB_FAILSAFE = c_ssAMB_FAILSAFE_Suv; + g_ssAMBKEEP_KAT = c_ssAMBKEEP_KAT_Suv; + g_ssAMBKEEP_KAT_PLUS = c_ssAMBKEEP_KAT_PLUS_Suv; + g_ssAMBKEEP_WATER = c_ssAMBKEEP_WATER_Suv; + M_MEMCOPY((g_aucAMBRATE_RISING), (c_aucAMBRATE_RISING_Suv)); + M_MEMCOPY((g_aucAMBRATE_FALLING), (c_aucAMBRATE_FALLING_Suv)); + M_MEMCOPY((g_aucAMBRATE_RISING_DIFF), (c_aucAMBRATE_RISING_DIFF_Suv)); + M_MEMCOPY((g_aucAMBRATE_FALLING_DIFF), (c_aucAMBRATE_FALLING_DIFF_Suv)); +/* ------------------------------------------Ambient: End*/ + M_MEMCOPY((g_ausINCARRATE_RISING_F), (c_ausINCARRATE_RISING_F_Suv)); + M_MEMCOPY((g_ausINCARRATE_FALLING_F), (c_ausINCARRATE_FALLING_F_Suv)); + M_MEMCOPY((g_ausINCARRATE_RISING_DIFF_F), (c_ausINCARRATE_RISING_DIFF_F_Suv)); + M_MEMCOPY((g_ausINCARRATE_FALLING_DIFF_F), (c_ausINCARRATE_FALLING_DIFF_F_Suv)); + M_MEMCOPY((g_ausINCARRATE_RISING_R), (c_ausINCARRATE_RISING_R_Suv)); + M_MEMCOPY((g_ausINCARRATE_FALLING_R), (c_ausINCARRATE_FALLING_R_Suv)); + M_MEMCOPY((g_ausINCARRATE_RISING_DIFF_R), (c_ausINCARRATE_RISING_DIFF_R_Suv)); + M_MEMCOPY((g_ausINCARRATE_FALLING_DIFF_R), (c_ausINCARRATE_FALLING_DIFF_R_Suv)); +/* ------------------------------------------Incar: End*/ + M_MEMCOPY((g_ausSUNRATE_RISING), (c_ausSUNRATE_RISING_Suv)); + M_MEMCOPY((g_ausSUNRATE_FALLING), (c_ausSUNRATE_FALLING_Suv)); +/* ------------------------------------------Sun: End*/ + M_MEMCOPY((g_ausAMB_LV_CHANGE_UNIT), (c_ausAMB_LV_CHANGE_UNIT_Suv)); + M_MEMCOPY((g_aucAMB_LV_CHANGE_SEC), (c_aucAMB_LV_CHANGE_SEC_Suv)); +/* ------------------------------------------Level Chage: End*/ + g_ssTHREEWAY_WATER = c_ssTHREEWAY_WATER_Suv; + M_MEMCOPY((g_assTHREEWAY_DUCT_TGT_R), (c_assTHREEWAY_DUCT_TGT_R_Suv)); + M_MEMCOPY((g_aucTHEREEWAY_EXPIRING), (c_aucTHEREEWAY_EXPIRING_Suv)); +/* ------------------------------------------Three way: End*/ + M_MEMCOPY((g_assTWOWAY_REAR_DUCTTGT_R), (c_assTWOWAY_REAR_DUCTTGT_R_Suv)); + M_MEMCOPY((g_aucTWOWAY_EXPIRING), (c_aucTWOWAY_EXPIRING_Suv)); +/* ------------------------------------------two-way: End*/ + M_MEMCOPY((g_aucACT_HOM_SPD_FL_CH0), (c_aucACT_HOM_SPD_FL_CH0_Suv)); + M_MEMCOPY((g_aucACT_HOM_SPD_FR_CH1), (c_aucACT_HOM_SPD_FR_CH1_Suv)); + M_MEMCOPY((g_aucACT_HOM_SPD_R_CH2), (c_aucACT_HOM_SPD_R_CH2_Suv)); + M_MEMCOPY((g_aucACT_HOM_SPD_R_EX_CH2), (c_aucACT_HOM_SPD_R_EX_CH2_Suv)); + M_MEMCOPY((g_aucACT_MOV_SPD_FL_CH0), (c_aucACT_MOV_SPD_FL_CH0_Suv)); + M_MEMCOPY((g_aucACT_MOV_SPD_FR_CH1), (c_aucACT_MOV_SPD_FR_CH1_Suv)); + M_MEMCOPY((g_aucACT_MOV_SPD_R_CH2), (c_aucACT_MOV_SPD_R_CH2_Suv)); + M_MEMCOPY((g_aucACT_MOV_SPD_R_EX_CH2), (c_aucACT_MOV_SPD_R_EX_CH2_Suv)); +/* ------------------------------------------Actuator Homing: End*/ + M_MEMCOPY((g_assHI_MODE_ENG_TMEP), (c_assHI_MODE_ENG_TMEP_Suv)); + M_MEMCOPY((g_aucHI_MODE_BLR_STEP_STS), (c_aucHI_MODE_BLR_STEP_STS_Suv)); +/* ------------------------------------------Hi Mode: End*/ + M_MEMCOPY((g_ausMinusAF_GlassPos_L), (c_ausMinusAF_GlassPos_L_Suv)); + M_MEMCOPY((g_ausMinusAF_GlassPos_R), (c_ausMinusAF_GlassPos_R_Suv)); +/* ------------------------------------------GlassPosition: End*/ + M_MEMCOPY((g_assFoot2_Lv3_Amb), (c_assFoot2_Lv3_Amb_Suv)); + M_MEMCOPY((g_assFoot2_Lv4_Amb), (c_assFoot2_Lv4_Amb_Suv)); + M_MEMCOPY((g_assFoot2_Lv5_Amb), (c_assFoot2_Lv5_Amb_Suv)); + M_MEMCOPY((g_assFoot2_Lv3_DuctTgt_Plus), (c_assFoot2_Lv3_DuctTgt_Plus_Suv)); + M_MEMCOPY((g_assFoot2_Lv4_DuctTgt_Plus), (c_assFoot2_Lv4_DuctTgt_Plus_Suv)); + M_MEMCOPY((g_assFoot2_Lv5_DuctTgt_Plus), (c_assFoot2_Lv5_DuctTgt_Plus_Suv)); + M_MEMCOPY((g_ausFoot2_Lv1_FrontBlr_X), (c_ausFoot2_Lv1_FrontBlr_X_Suv)); + M_MEMCOPY((g_ausFoot2_Lv1_Foot2Act_Y), (c_ausFoot2_Lv1_Foot2Act_Y_Suv)); + M_MEMCOPY((g_assFoot2_Lv2_Threshold_Diff), (c_assFoot2_Lv2_Threshold_Diff_Suv)); + M_MEMCOPY((g_assFoot2_Lv3_Threshold_Diff), (c_assFoot2_Lv3_Threshold_Diff_Suv)); +/* ------------------------------------------Foot2 Ctrl: End*/ + M_MEMCOPY((g_ausDbF_Side_Af_Bi), (c_ausDbF_Side_Af_Bi_Suv)); + M_MEMCOPY((g_ausDbF_Side_Af_Bi2), (c_ausDbF_Side_Af_Bi2_Suv)); + M_MEMCOPY((g_ausDbF_Side_Af_Vent), (c_ausDbF_Side_Af_Vent_Suv)); + M_MEMCOPY((g_ausDbF_Side_Bi_Bi2), (c_ausDbF_Side_Bi_Bi2_Suv)); + M_MEMCOPY((g_ausDbF_Side_Bi_Vent), (c_ausDbF_Side_Bi_Vent_Suv)); + M_MEMCOPY((g_ausDbF_Side_Bi2_Vent), (c_ausDbF_Side_Bi2_Vent_Suv)); + M_MEMCOPY((g_ausDbF_Cen_Af_Bi), (c_ausDbF_Cen_Af_Bi_Suv)); + M_MEMCOPY((g_ausDbF_Cen_Af_Bi2), (c_ausDbF_Cen_Af_Bi2_Suv)); + M_MEMCOPY((g_ausDbF_Cen_Af_Vent), (c_ausDbF_Cen_Af_Vent_Suv)); + M_MEMCOPY((g_ausDbF_Cen_Bi_Bi2), (c_ausDbF_Cen_Bi_Bi2_Suv)); + M_MEMCOPY((g_ausDbF_Cen_Bi_Vent), (c_ausDbF_Cen_Bi_Vent_Suv)); + M_MEMCOPY((g_ausDbF_Cen_Bi2_Vent), (c_ausDbF_Cen_Bi2_Vent_Suv)); + M_MEMCOPY((g_ausDbF_Foot_Af_Bi), (c_ausDbF_Foot_Af_Bi_Suv)); + M_MEMCOPY((g_ausDbF_Foot_Af_Bi2), (c_ausDbF_Foot_Af_Bi2_Suv)); + M_MEMCOPY((g_ausDbF_Foot_Af_Vent), (c_ausDbF_Foot_Af_Vent_Suv)); + M_MEMCOPY((g_ausDbF_Foot_Bi_Bi2), (c_ausDbF_Foot_Bi_Bi2_Suv)); + M_MEMCOPY((g_ausDbF_Foot_Bi_Vent), (c_ausDbF_Foot_Bi_Vent_Suv)); + M_MEMCOPY((g_ausDbF_Foot_Bi2_Vent), (c_ausDbF_Foot_Bi2_Vent_Suv)); + M_MEMCOPY((g_ausDbF_AF_Af_Bi), (c_ausDbF_AF_Af_Bi_Suv)); + M_MEMCOPY((g_ausDbF_AF_Af_Bi2), (c_ausDbF_AF_Af_Bi2_Suv)); + M_MEMCOPY((g_ausDbF_AF_Af_Vent), (c_ausDbF_AF_Af_Vent_Suv)); + M_MEMCOPY((g_ausDbF_AF_Bi_Bi2), (c_ausDbF_AF_Bi_Bi2_Suv)); + M_MEMCOPY((g_ausDbF_AF_Bi_Vent), (c_ausDbF_AF_Bi_Vent_Suv)); + M_MEMCOPY((g_ausDbF_AF_Bi2_Vent), (c_ausDbF_AF_Bi2_Vent_Suv)); + M_MEMCOPY((g_ausDbF_Pwm_Af_Bi), (c_ausDbF_Pwm_Af_Bi_Suv)); + M_MEMCOPY((g_ausDbF_Pwm_Af_Bi2), (c_ausDbF_Pwm_Af_Bi2_Suv)); + M_MEMCOPY((g_ausDbF_Pwm_Af_Vent), (c_ausDbF_Pwm_Af_Vent_Suv)); + M_MEMCOPY((g_ausDbF_Pwm_Bi_Bi2), (c_ausDbF_Pwm_Bi_Bi2_Suv)); + M_MEMCOPY((g_ausDbF_Pwm_Bi_Vent), (c_ausDbF_Pwm_Bi_Vent_Suv)); + M_MEMCOPY((g_ausDbF_Pwm_Bi2_Vent), (c_ausDbF_Pwm_Bi2_Vent_Suv)); +/* ------------------------------------------Different blower Front: End*/ + g_usAromaPwm_Min = c_usAromaPwm_Min_Suv; + g_usAromaPwm_Max = c_usAromaPwm_Max_Suv; +/* ------------------------------------------Aroma Limit Pwm: End*/ +/*********************************************************Cal Table End*/ + +} +/****************************************************************************** + * LOCAL FUNCTIONS + *****************************************************************************/ +/* End of Excel line : 2159 */ +/****************************************************************************** + * EOF + *****************************************************************************/ diff --git a/MODULES/HVAC_M7_DataNonVolatile/calib/Rs_Cal_3_Suv.h b/MODULES/HVAC_M7_DataNonVolatile/calib/Rs_Cal_3_Suv.h new file mode 100644 index 0000000..95b3567 --- /dev/null +++ b/MODULES/HVAC_M7_DataNonVolatile/calib/Rs_Cal_3_Suv.h @@ -0,0 +1,38 @@ +/** Doxygen: File brief + ****************************************************************************** + * @file Rs_Cal_3_Suv.h + * @brief No brief + * @remark Generated by C:\9999\Rs_Cal_R23_ver21_SedanL.xlsm + * Generated on yyyy-mm-dd hh:mm:ss + *****************************************************************************/ +#ifndef RS_CAL_3_SUV_H__ +#define RS_CAL_3_SUV_H__ + +/****************************************************************************** + * INCLUDE FILES +*****************************************************************************/ +#include "rtwtypes.h" +#include "common.h" +#include "HVAC_preDefine.h" +#include "Rs_Cal_Base.h" + +/****************************************************************************** + * MACRO DECLARATIONS + *****************************************************************************/ +/****************************************************************************** + * GLOBAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS) + *****************************************************************************/ +/****************************************************************************** + * GLOBAL VARIABLES DECLARATIONS + *****************************************************************************/ +extern SECT_VEH_CAL_3 const tU08 c_ucCalFromRelease_Suv; +/****************************************************************************** + * GLOBAL FUNCTIONS DECLARATIONS + *****************************************************************************/ +extern void Rs_Cal_3_Suv(void); + +/* End of Excel line : 34 */ +#endif /*RS_CAL_3_SUV_H__*/ +/****************************************************************************** + * EOF + *****************************************************************************/ diff --git a/MODULES/HVAC_M7_DataNonVolatile/calib/Rs_Cal_4_Mpv.c b/MODULES/HVAC_M7_DataNonVolatile/calib/Rs_Cal_4_Mpv.c new file mode 100644 index 0000000..ef0d6f9 --- /dev/null +++ b/MODULES/HVAC_M7_DataNonVolatile/calib/Rs_Cal_4_Mpv.c @@ -0,0 +1,2162 @@ +/** Doxygen: File brief + ****************************************************************************** + * @file Rs_Cal_4_Mpv.c + * @brief No brief + * @remark Generated by C:\9999\Rs_Cal_R23_ver21_SedanL.xlsm + * Generated on yyyy-mm-dd hh:mm:ss + *****************************************************************************/ +/****************************************************************************** + * INCLUDE FILES + *****************************************************************************/ +#include "Rs_Cal_4_Mpv.h" + +/****************************************************************************** + * MACRO DECLARATIONS + *****************************************************************************/ +/*PRQA S 0615 EOF #suppress : More than 511 block scope identifiers, from Calibration data table, No impact*/ +/*PRQA S 1514 EOF #suppress : In the same translation(used != defined), from Calibration data table, No impact*/ +/*PRQA S 3408 EOF #suppress : To manage Cal. data separately, from Calibration data table, No Impact*/ +/****************************************************************************** + * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS) + *****************************************************************************/ +/****************************************************************************** + * GLOBAL VARIABLES DECLARATIONS + *****************************************************************************/ +SECT_VEH_CAL_4 const tU08 c_ucCalFromRelease_Mpv = ID_TRUE; +SECT_VEH_CAL_4 const tU08 c_aucCAL_FP_DATE_Mpv[3] = { VERSION_MPV_Y, VERSION_MPV_M, VERSION_MPV_D}; +SECT_VEH_CAL_4 const tU08 c_aucCAL_VERSION_Mpv[2] = { 0, 20}; +SECT_VEH_CAL_4 const tU08 c_ucCAL_VARIANT_Mpv = 5; +/* ------------------------------------------Cal Version : End*/ +SECT_VEH_CAL_4 const tU16 c_ausSET_TEMP_FULL_Mpv[13] = { 170, 180, 190, 200, 210, 220, 230, 240, 250, 260, 270, 280, 290}; +SECT_VEH_CAL_4 const tU16 c_ausSET_TEMP_HALF_Mpv[7] = { 170, 190, 210, 230, 250, 270, 290}; +/* ------------------------------------------Set Temp : End*/ +SECT_VEH_CAL_4 const tS16 c_assINCAR_TG_FL_LV0_Mpv[13] = { 180, 190, 200, 210, 220, 235, 245, 255, 270, 280, 290, 310, 330}; +SECT_VEH_CAL_4 const tS16 c_assINCAR_TG_FR_LV0_Mpv[13] = { 180, 190, 200, 210, 220, 235, 245, 255, 270, 280, 290, 310, 330}; +SECT_VEH_CAL_4 const tS16 c_assVTG_FL_LV0_Mpv[13] = { 120, 105, 100, 95, 90, 85, 80, 80, 70, 65, 60, 60, 60}; +SECT_VEH_CAL_4 const tS16 c_assVTG_FR_LV0_Mpv[13] = { 120, 105, 100, 95, 90, 85, 80, 80, 70, 65, 60, 60, 60}; +SECT_VEH_CAL_4 const tS16 c_assVF_MIN_LV0_Mpv[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_4 const tS16 c_assVF_MAX_LV0_Mpv[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_Y1_LV0_Mpv[7] = { 60, 60, 50, 50, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_Y2_LV0_Mpv[7] = { 20, 20, 20, 20, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_Y3_LV0_Mpv[7] = { -20, -20, -20, -10, 5, 5, 5}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_Y4_LV0_Mpv[7] = { -50, -50, -50, -20, 10, 10, 10}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_X1_LV0_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_X2_LV0_Mpv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_X3_LV0_Mpv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_X4_LV0_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assVF_AMB_Y1_LV0_Mpv[7] = { 10, 10, 10, 5, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVF_AMB_Y2_LV0_Mpv[7] = { -10, -10, -10, -10, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVF_AMB_X1_LV0_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assVF_AMB_X2_LV0_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assVF_SUN_Y1_LV0_Mpv[7] = { 20, 20, 20, 20, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVF_SUN_Y2_LV0_Mpv[7] = { 50, 50, 50, 50, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVF_SUN_X1_LV0_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assVF_SUN_X2_LV0_Mpv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_4 const tS16 c_assTG_FLU_LV0_Mpv[13] = { 20, 20, 20, 50, 60, 80, 100, 125, 180, 250, 380, 500, 550}; +SECT_VEH_CAL_4 const tS16 c_assTG_FRU_LV0_Mpv[13] = { 20, 20, 20, 50, 60, 80, 100, 125, 180, 250, 380, 500, 550}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_MIN_LV0_Mpv[7] = { 20, 20, 20, 50, 50, 50, 50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_MAX_LV0_Mpv[7] = { 600, 600, 600, 600, 600, 600, 600}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_Y1_LV0_Mpv[7] = { 0, -20, -50, -50, -100, -150, -200}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_Y2_LV0_Mpv[7] = { 0, -10, -30, -50, -50, -50, -50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_Y3_LV0_Mpv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_Y4_LV0_Mpv[7] = { 200, 200, 200, 150, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_X1_LV0_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_X2_LV0_Mpv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_X3_LV0_Mpv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_X4_LV0_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_AMB_Y1_LV0_Mpv[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_AMB_Y2_LV0_Mpv[7] = { 50, 50, 50, 50, 50, 25, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_AMB_X1_LV0_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_AMB_X2_LV0_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_SUN_Y1_LV0_Mpv[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_SUN_Y2_LV0_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_SUN_X1_LV0_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_SUN_X2_LV0_Mpv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_4 const tS16 c_assTG_FLL_LV0_Mpv[13] = { 150, 150, 150, 150, 200, 250, 300, 400, 450, 500, 600, 650, 700}; +SECT_VEH_CAL_4 const tS16 c_assTG_FRL_LV0_Mpv[13] = { 150, 150, 150, 150, 200, 250, 300, 400, 450, 500, 600, 650, 700}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_MIN_LV0_Mpv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_MAX_LV0_Mpv[7] = { 400, 450, 500, 600, 600, 600, 600}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_Y1_LV0_Mpv[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_Y2_LV0_Mpv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_Y3_LV0_Mpv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_Y4_LV0_Mpv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_X1_LV0_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_X2_LV0_Mpv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_X3_LV0_Mpv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_X4_LV0_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_AMB_Y1_LV0_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_AMB_Y2_LV0_Mpv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_AMB_X1_LV0_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_AMB_X2_LV0_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_SUN_Y1_LV0_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_SUN_Y2_LV0_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_SUN_X1_LV0_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_SUN_X2_LV0_Mpv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_4 const tS16 c_assINCAR_TG_RL_LV0_Mpv[13] = { 190, 195, 200, 215, 230, 240, 250, 270, 280, 290, 300, 310, 320}; +SECT_VEH_CAL_4 const tS16 c_assINCAR_TG_RR_LV0_Mpv[13] = { 190, 195, 200, 215, 230, 240, 250, 270, 280, 290, 300, 310, 320}; +SECT_VEH_CAL_4 const tS16 c_assVTG_RL_LV0_Mpv[13] = { 110, 100, 92, 82, 75, 70, 65, 65, 60, 60, 60, 60, 60}; +SECT_VEH_CAL_4 const tS16 c_assVTG_RR_LV0_Mpv[13] = { 110, 100, 92, 82, 75, 70, 65, 65, 60, 60, 60, 60, 60}; +SECT_VEH_CAL_4 const tS16 c_assVR_MIN_LV0_Mpv[7] = { 80, 80, 40, 40, 40, 30, 30}; +SECT_VEH_CAL_4 const tS16 c_assVR_MAX_LV0_Mpv[7] = { 160, 160, 160, 160, 100, 80, 80}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_Y1_LV0_Mpv[7] = { 60, 60, 50, 50, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_Y2_LV0_Mpv[7] = { 20, 20, 20, 20, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_Y3_LV0_Mpv[7] = { -20, -20, -20, -10, 5, 5, 5}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_Y4_LV0_Mpv[7] = { -50, -50, -50, -20, 10, 10, 10}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_X1_LV0_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_X2_LV0_Mpv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_X3_LV0_Mpv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_X4_LV0_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assVR_AMB_Y1_LV0_Mpv[7] = { 20, 20, 20, 20, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVR_AMB_Y2_LV0_Mpv[7] = { 0, 0, -50, -50, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVR_AMB_X1_LV0_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assVR_AMB_X2_LV0_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assVR_SUN_Y1_LV0_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVR_SUN_Y2_LV0_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVR_SUN_X1_LV0_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assVR_SUN_X2_LV0_Mpv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_4 const tS16 c_assTG_RL_LV0_Mpv[13] = { 30, 30, 30, 50, 90, 100, 120, 180, 240, 320, 400, 450, 500}; +SECT_VEH_CAL_4 const tS16 c_assTG_RR_LV0_Mpv[13] = { 30, 30, 30, 50, 90, 100, 120, 180, 240, 320, 400, 450, 500}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_MIN_LV0_Mpv[7] = { 20, 20, 20, 20, 50, 50, 50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_MAX_LV0_Mpv[7] = { 400, 400, 450, 500, 600, 600, 600}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_Y1_LV0_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_Y2_LV0_Mpv[7] = { -40, -40, -40, -40, -40, -50, -60}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_Y3_LV0_Mpv[7] = { 40, 40, 40, 40, 20, 20, 20}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_Y4_LV0_Mpv[7] = { 200, 200, 200, 100, 50, 50, 50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_X1_LV0_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_X2_LV0_Mpv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_X3_LV0_Mpv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_X4_LV0_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_AMB_Y1_LV0_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_AMB_Y2_LV0_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_AMB_X1_LV0_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_AMB_X2_LV0_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_SUN_Y1_LV0_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_SUN_Y2_LV0_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_SUN_X1_LV0_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_SUN_X2_LV0_Mpv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_DUCT_TIME_FR_LV0_Mpv[7] = { 600, 600, 600, 600, 600, 600, 600}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_DUCT_TIME_FL_LV0_Mpv[7] = { 600, 600, 600, 600, 600, 600, 600}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_DUCT_RATE_LV0_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_DUCT_MAX_LV0_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_AF_TIME_FR_LV0_Mpv[7] = { 3000, 3000, 3000, 3000, 3000, 3000, 3000}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_AF_TIME_FL_LV0_Mpv[7] = { 3000, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_AF_RATE_LV0_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_AF_MAX_LV0_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +/* ------------------------------------------Lv0 : End*/ +SECT_VEH_CAL_4 const tS16 c_assINCAR_TG_FL_LV1_Mpv[13] = { 180, 190, 200, 210, 220, 235, 245, 255, 265, 270, 280, 300, 310}; +SECT_VEH_CAL_4 const tS16 c_assINCAR_TG_FR_LV1_Mpv[13] = { 180, 190, 200, 210, 220, 235, 245, 255, 265, 270, 280, 300, 310}; +SECT_VEH_CAL_4 const tS16 c_assVTG_FL_LV1_Mpv[13] = { 110, 95, 90, 85, 80, 75, 70, 70, 65, 65, 60, 60, 60}; +SECT_VEH_CAL_4 const tS16 c_assVTG_FR_LV1_Mpv[13] = { 110, 95, 90, 85, 80, 75, 70, 70, 65, 65, 60, 60, 60}; +SECT_VEH_CAL_4 const tS16 c_assVF_MIN_LV1_Mpv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_4 const tS16 c_assVF_MAX_LV1_Mpv[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_Y1_LV1_Mpv[7] = { 40, 40, 45, 50, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_Y2_LV1_Mpv[7] = { 10, 10, 10, 10, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_Y3_LV1_Mpv[7] = { -10, -10, -10, -10, 5, 5, 5}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_Y4_LV1_Mpv[7] = { -50, -40, -30, -30, 10, 10, 10}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_X1_LV1_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_X2_LV1_Mpv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_X3_LV1_Mpv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_X4_LV1_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assVF_AMB_Y1_LV1_Mpv[7] = { 10, 10, 10, 10, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVF_AMB_Y2_LV1_Mpv[7] = { -10, -10, -10, -10, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVF_AMB_X1_LV1_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assVF_AMB_X2_LV1_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assVF_SUN_Y1_LV1_Mpv[7] = { 10, 10, 10, 10, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVF_SUN_Y2_LV1_Mpv[7] = { 30, 30, 30, 30, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVF_SUN_X1_LV1_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assVF_SUN_X2_LV1_Mpv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_4 const tS16 c_assTG_FLU_LV1_Mpv[13] = { 50, 70, 90, 120, 130, 140, 150, 180, 250, 350, 450, 500, 550}; +SECT_VEH_CAL_4 const tS16 c_assTG_FRU_LV1_Mpv[13] = { 50, 70, 90, 120, 130, 140, 150, 180, 250, 350, 450, 500, 550}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_MIN_LV1_Mpv[7] = { 20, 20, 20, 20, 50, 50, 50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_MAX_LV1_Mpv[7] = { 400, 450, 450, 500, 600, 600, 600}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_Y1_LV1_Mpv[7] = { 0, -20, -50, -70, -100, -150, -200}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_Y2_LV1_Mpv[7] = { 0, -10, -30, -50, -50, -50, -50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_Y3_LV1_Mpv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_Y4_LV1_Mpv[7] = { 200, 200, 200, 150, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_X1_LV1_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_X2_LV1_Mpv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_X3_LV1_Mpv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_X4_LV1_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_AMB_Y1_LV1_Mpv[7] = { 0, 0, -30, -50, -30, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_AMB_Y2_LV1_Mpv[7] = { 0, 30, 50, 100, 50, 50, 50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_AMB_X1_LV1_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_AMB_X2_LV1_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_SUN_Y1_LV1_Mpv[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_SUN_Y2_LV1_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_SUN_X1_LV1_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_SUN_X2_LV1_Mpv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_4 const tS16 c_assTG_FLL_LV1_Mpv[13] = { 150, 200, 250, 250, 250, 250, 300, 400, 450, 500, 600, 650, 800}; +SECT_VEH_CAL_4 const tS16 c_assTG_FRL_LV1_Mpv[13] = { 150, 200, 250, 250, 250, 250, 300, 400, 450, 500, 600, 650, 800}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_MIN_LV1_Mpv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_MAX_LV1_Mpv[7] = { 450, 450, 500, 600, 600, 600, 600}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_Y1_LV1_Mpv[7] = { 0, 0, 0, 0, 0, -100, -200}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_Y2_LV1_Mpv[7] = { 0, 0, 0, 0, -50, -50, -50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_Y3_LV1_Mpv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_Y4_LV1_Mpv[7] = { 100, 100, 100, 50, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_X1_LV1_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_X2_LV1_Mpv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_X3_LV1_Mpv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_X4_LV1_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_AMB_Y1_LV1_Mpv[7] = { 0, 0, -30, -50, -50, -50, -50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_AMB_Y2_LV1_Mpv[7] = { 0, 0, 30, 50, 50, 50, 50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_AMB_X1_LV1_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_AMB_X2_LV1_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_SUN_Y1_LV1_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_SUN_Y2_LV1_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_SUN_X1_LV1_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_SUN_X2_LV1_Mpv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_4 const tS16 c_assINCAR_TG_RL_LV1_Mpv[13] = { 190, 195, 200, 215, 230, 240, 250, 270, 280, 290, 300, 310, 320}; +SECT_VEH_CAL_4 const tS16 c_assINCAR_TG_RR_LV1_Mpv[13] = { 190, 195, 200, 215, 230, 240, 250, 270, 280, 290, 300, 310, 320}; +SECT_VEH_CAL_4 const tS16 c_assVTG_RL_LV1_Mpv[13] = { 110, 100, 90, 80, 70, 65, 65, 65, 70, 70, 70, 70, 70}; +SECT_VEH_CAL_4 const tS16 c_assVTG_RR_LV1_Mpv[13] = { 110, 100, 90, 80, 70, 65, 65, 65, 70, 70, 70, 70, 70}; +SECT_VEH_CAL_4 const tS16 c_assVR_MIN_LV1_Mpv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_4 const tS16 c_assVR_MAX_LV1_Mpv[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_Y1_LV1_Mpv[7] = { 60, 60, 50, 50, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_Y2_LV1_Mpv[7] = { 20, 20, 20, 20, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_Y3_LV1_Mpv[7] = { -20, -20, -20, -10, 5, 5, 5}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_Y4_LV1_Mpv[7] = { -50, -50, -50, -20, 10, 10, 10}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_X1_LV1_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_X2_LV1_Mpv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_X3_LV1_Mpv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_X4_LV1_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assVR_AMB_Y1_LV1_Mpv[7] = { 0, 0, 5, 0, -10, -10, -10}; +SECT_VEH_CAL_4 const tS16 c_assVR_AMB_Y2_LV1_Mpv[7] = { 0, 0, -5, -5, 10, 15, 20}; +SECT_VEH_CAL_4 const tS16 c_assVR_AMB_X1_LV1_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assVR_AMB_X2_LV1_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assVR_SUN_Y1_LV1_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVR_SUN_Y2_LV1_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVR_SUN_X1_LV1_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assVR_SUN_X2_LV1_Mpv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_4 const tS16 c_assTG_RL_LV1_Mpv[13] = { 30, 30, 50, 80, 90, 100, 130, 160, 240, 320, 400, 450, 500}; +SECT_VEH_CAL_4 const tS16 c_assTG_RR_LV1_Mpv[13] = { 30, 30, 50, 80, 90, 100, 130, 160, 240, 320, 400, 450, 500}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_MIN_LV1_Mpv[7] = { 20, 20, 20, 20, 50, 50, 50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_MAX_LV1_Mpv[7] = { 400, 400, 450, 500, 600, 600, 600}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_Y1_LV1_Mpv[7] = { -100, -100, -100, -100, -100, -150, -200}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_Y2_LV1_Mpv[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_Y3_LV1_Mpv[7] = { 50, 50, 50, 50, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_Y4_LV1_Mpv[7] = { 200, 200, 200, 200, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_X1_LV1_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_X2_LV1_Mpv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_X3_LV1_Mpv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_X4_LV1_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_AMB_Y1_LV1_Mpv[7] = { 0, 0, -10, -10, -50, -50, -50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_AMB_Y2_LV1_Mpv[7] = { 0, 0, 20, 20, 50, 50, 50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_AMB_X1_LV1_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_AMB_X2_LV1_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_SUN_Y1_LV1_Mpv[7] = { 0, 0, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_SUN_Y2_LV1_Mpv[7] = { 0, 0, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_SUN_X1_LV1_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_SUN_X2_LV1_Mpv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_DUCT_TIME_FR_LV1_Mpv[7] = { 600, 600, 600, 600, 600, 600, 600}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_DUCT_TIME_FL_LV1_Mpv[7] = { 600, 600, 600, 600, 600, 600, 600}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_DUCT_RATE_LV1_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_DUCT_MAX_LV1_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_AF_TIME_FR_LV1_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_AF_TIME_FL_LV1_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_AF_RATE_LV1_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_AF_MAX_LV1_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +/* ------------------------------------------Lv1 : End*/ +SECT_VEH_CAL_4 const tS16 c_assINCAR_TG_FL_LV2_Mpv[13] = { 180, 190, 200, 210, 230, 245, 255, 265, 270, 280, 290, 300, 310}; +SECT_VEH_CAL_4 const tS16 c_assINCAR_TG_FR_LV2_Mpv[13] = { 180, 190, 200, 210, 230, 245, 255, 265, 270, 280, 290, 300, 310}; +SECT_VEH_CAL_4 const tS16 c_assVTG_FL_LV2_Mpv[13] = { 90, 83, 75, 62, 50, 55, 60, 60, 65, 70, 70, 75, 80}; +SECT_VEH_CAL_4 const tS16 c_assVTG_FR_LV2_Mpv[13] = { 90, 83, 75, 62, 50, 55, 60, 60, 65, 70, 70, 75, 80}; +SECT_VEH_CAL_4 const tS16 c_assVF_MIN_LV2_Mpv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_4 const tS16 c_assVF_MAX_LV2_Mpv[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_Y1_LV2_Mpv[7] = { -10, -10, -10, 10, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_Y2_LV2_Mpv[7] = { -5, -5, -5, 5, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_Y3_LV2_Mpv[7] = { 0, 0, 0, 5, 5, 5, 5}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_Y4_LV2_Mpv[7] = { 0, 0, 0, 10, 10, 10, 10}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_X1_LV2_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_X2_LV2_Mpv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_X3_LV2_Mpv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_X4_LV2_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assVF_AMB_Y1_LV2_Mpv[7] = { 10, 12, 15, 10, -10, -10, -10}; +SECT_VEH_CAL_4 const tS16 c_assVF_AMB_Y2_LV2_Mpv[7] = { 0, 0, 0, 5, 8, 10, 10}; +SECT_VEH_CAL_4 const tS16 c_assVF_AMB_X1_LV2_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assVF_AMB_X2_LV2_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assVF_SUN_Y1_LV2_Mpv[7] = { 5, 5, 5, 5, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVF_SUN_Y2_LV2_Mpv[7] = { 10, 10, 10, 10, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVF_SUN_X1_LV2_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assVF_SUN_X2_LV2_Mpv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_4 const tS16 c_assTG_FLU_LV2_Mpv[13] = { 50, 50, 90, 120, 150, 200, 250, 300, 335, 375, 450, 470, 480}; +SECT_VEH_CAL_4 const tS16 c_assTG_FRU_LV2_Mpv[13] = { 50, 50, 90, 120, 150, 200, 250, 300, 335, 375, 450, 470, 480}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_MIN_LV2_Mpv[7] = { 20, 20, 20, 30, 40, 50, 50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_MAX_LV2_Mpv[7] = { 450, 450, 550, 600, 600, 600, 600}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_Y1_LV2_Mpv[7] = { -100, -100, -150, -150, -150, -150, -150}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_Y2_LV2_Mpv[7] = { -50, -50, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_Y3_LV2_Mpv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_Y4_LV2_Mpv[7] = { 200, 200, 200, 200, 200, 200, 200}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_X1_LV2_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_X2_LV2_Mpv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_X3_LV2_Mpv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_X4_LV2_Mpv[7] = { 150, 150, 150, 150, 150, 150, 150}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_AMB_Y1_LV2_Mpv[7] = { 0, 0, 0, -50, -50, -50, -50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_AMB_Y2_LV2_Mpv[7] = { 0, 0, 50, 135, 120, 120, 120}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_AMB_X1_LV2_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_AMB_X2_LV2_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_SUN_Y1_LV2_Mpv[7] = { 0, 0, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_SUN_Y2_LV2_Mpv[7] = { 0, 0, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_SUN_X1_LV2_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_SUN_X2_LV2_Mpv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_4 const tS16 c_assTG_FLL_LV2_Mpv[13] = { 150, 200, 250, 250, 275, 300, 350, 400, 450, 525, 600, 700, 800}; +SECT_VEH_CAL_4 const tS16 c_assTG_FRL_LV2_Mpv[13] = { 150, 200, 250, 250, 275, 300, 350, 400, 450, 525, 600, 700, 800}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_MIN_LV2_Mpv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_MAX_LV2_Mpv[7] = { 450, 450, 500, 800, 800, 800, 800}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_Y1_LV2_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_Y2_LV2_Mpv[7] = { -50, -50, -20, -50, -50, -50, -50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_Y3_LV2_Mpv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_Y4_LV2_Mpv[7] = { 400, 400, 400, 400, 400, 400, 400}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_X1_LV2_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_X2_LV2_Mpv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_X3_LV2_Mpv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_X4_LV2_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_AMB_Y1_LV2_Mpv[7] = { 0, 0, 0, -50, -50, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_AMB_Y2_LV2_Mpv[7] = { 150, 200, 150, 200, 150, 100, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_AMB_X1_LV2_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_AMB_X2_LV2_Mpv[7] = { 150, 150, 150, 150, 150, 150, 150}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_SUN_Y1_LV2_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_SUN_Y2_LV2_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_SUN_X1_LV2_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_SUN_X2_LV2_Mpv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_4 const tS16 c_assINCAR_TG_RL_LV2_Mpv[13] = { 190, 195, 200, 215, 230, 240, 250, 270, 280, 290, 300, 310, 320}; +SECT_VEH_CAL_4 const tS16 c_assINCAR_TG_RR_LV2_Mpv[13] = { 190, 195, 200, 215, 230, 240, 250, 270, 280, 290, 300, 310, 320}; +SECT_VEH_CAL_4 const tS16 c_assVTG_RL_LV2_Mpv[13] = { 90, 83, 75, 62, 55, 55, 60, 60, 65, 70, 70, 75, 80}; +SECT_VEH_CAL_4 const tS16 c_assVTG_RR_LV2_Mpv[13] = { 90, 83, 75, 62, 55, 55, 60, 60, 65, 70, 70, 75, 80}; +SECT_VEH_CAL_4 const tS16 c_assVR_MIN_LV2_Mpv[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_4 const tS16 c_assVR_MAX_LV2_Mpv[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_Y1_LV2_Mpv[7] = { 30, 30, 30, 30, -10, -20, -20}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_Y2_LV2_Mpv[7] = { 5, 5, 5, 10, -5, -15, -20}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_Y3_LV2_Mpv[7] = { -10, -10, -10, 25, 10, 10, 10}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_Y4_LV2_Mpv[7] = { -30, -30, -30, 50, 30, 30, 30}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_X1_LV2_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_X2_LV2_Mpv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_X3_LV2_Mpv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_X4_LV2_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assVR_AMB_Y1_LV2_Mpv[7] = { 20, 15, 15, 10, -5, -10, -20}; +SECT_VEH_CAL_4 const tS16 c_assVR_AMB_Y2_LV2_Mpv[7] = { 0, 0, 0, 5, 5, 10, 10}; +SECT_VEH_CAL_4 const tS16 c_assVR_AMB_X1_LV2_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assVR_AMB_X2_LV2_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assVR_SUN_Y1_LV2_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVR_SUN_Y2_LV2_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVR_SUN_X1_LV2_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assVR_SUN_X2_LV2_Mpv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_4 const tS16 c_assTG_RL_LV2_Mpv[13] = { 50, 50, 50, 80, 90, 100, 150, 180, 240, 320, 400, 450, 500}; +SECT_VEH_CAL_4 const tS16 c_assTG_RR_LV2_Mpv[13] = { 50, 50, 50, 80, 90, 100, 150, 180, 240, 320, 400, 500, 500}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_MIN_LV2_Mpv[7] = { 20, 20, 20, 20, 380, 400, 400}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_MAX_LV2_Mpv[7] = { 400, 400, 450, 500, 600, 600, 800}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_Y1_LV2_Mpv[7] = { -100, -100, -100, -100, -100, -100, -250}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_Y2_LV2_Mpv[7] = { -50, -50, -50, -50, -50, -80, -100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_Y3_LV2_Mpv[7] = { 50, 50, 50, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_Y4_LV2_Mpv[7] = { 200, 200, 200, 250, 250, 250, 300}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_X1_LV2_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_X2_LV2_Mpv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_X3_LV2_Mpv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_X4_LV2_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_AMB_Y1_LV2_Mpv[7] = { 0, 0, 0, -20, -20, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_AMB_Y2_LV2_Mpv[7] = { 0, 0, 10, 30, 50, 80, 100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_AMB_X1_LV2_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_AMB_X2_LV2_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_SUN_Y1_LV2_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_SUN_Y2_LV2_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_SUN_X1_LV2_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_SUN_X2_LV2_Mpv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_DUCT_TIME_FR_LV2_Mpv[7] = { 3600, 3600, 3600, 3600, 3600, 3600, 3600}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_DUCT_TIME_FL_LV2_Mpv[7] = { 3600, 3600, 3600, 3600, 3600, 3600, 3600}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_DUCT_RATE_LV2_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_DUCT_MAX_LV2_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_AF_TIME_FR_LV2_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_AF_TIME_FL_LV2_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_AF_RATE_LV2_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_AF_MAX_LV2_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +/* ------------------------------------------Lv2 : End*/ +SECT_VEH_CAL_4 const tS16 c_assINCAR_TG_FL_LV3_Mpv[13] = { 180, 190, 200, 210, 230, 245, 255, 265, 270, 280, 290, 300, 310}; +SECT_VEH_CAL_4 const tS16 c_assINCAR_TG_FR_LV3_Mpv[13] = { 180, 190, 200, 210, 230, 245, 255, 265, 270, 280, 290, 300, 310}; +SECT_VEH_CAL_4 const tS16 c_assVTG_FL_LV3_Mpv[13] = { 90, 83, 75, 62, 55, 55, 65, 65, 70, 73, 86, 88, 90}; +SECT_VEH_CAL_4 const tS16 c_assVTG_FR_LV3_Mpv[13] = { 90, 83, 75, 62, 55, 55, 65, 65, 70, 73, 86, 88, 90}; +SECT_VEH_CAL_4 const tS16 c_assVF_MIN_LV3_Mpv[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_4 const tS16 c_assVF_MAX_LV3_Mpv[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_Y1_LV3_Mpv[7] = { 15, 15, 15, 25, 15, -30, -60}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_Y2_LV3_Mpv[7] = { 5, 5, 10, 5, 0, -10, -40}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_Y3_LV3_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_Y4_LV3_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_X1_LV3_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_X2_LV3_Mpv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_X3_LV3_Mpv[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_X4_LV3_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assVF_AMB_Y1_LV3_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVF_AMB_Y2_LV3_Mpv[7] = { -30, 0, 0, 0, 0, 20, 40}; +SECT_VEH_CAL_4 const tS16 c_assVF_AMB_X1_LV3_Mpv[7] = { -10, -10, -10, -10, -10, -10, -10}; +SECT_VEH_CAL_4 const tS16 c_assVF_AMB_X2_LV3_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assVF_SUN_Y1_LV3_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVF_SUN_Y2_LV3_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVF_SUN_X1_LV3_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assVF_SUN_X2_LV3_Mpv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_4 const tS16 c_assTG_FLU_LV3_Mpv[13] = { 50, 50, 140, 200, 300, 335, 370, 400, 420, 435, 460, 470, 480}; +SECT_VEH_CAL_4 const tS16 c_assTG_FRU_LV3_Mpv[13] = { 50, 50, 140, 200, 280, 310, 330, 380, 390, 420, 450, 470, 480}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_MIN_LV3_Mpv[7] = { 20, 20, 20, 30, 200, 200, 250}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_MAX_LV3_Mpv[7] = { 450, 450, 550, 800, 800, 750, 700}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_Y1_LV3_Mpv[7] = { -100, -100, -100, -150, -200, -250, -300}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_Y2_LV3_Mpv[7] = { -30, -30, -70, -80, -50, -50, -100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_Y3_LV3_Mpv[7] = { 50, 50, 50, 50, 50, 30, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_Y4_LV3_Mpv[7] = { 100, 100, 100, 100, 80, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_X1_LV3_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_X2_LV3_Mpv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_X3_LV3_Mpv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_X4_LV3_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_AMB_Y1_LV3_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_AMB_Y2_LV3_Mpv[7] = { 30, 30, 30, 60, 60, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_AMB_X1_LV3_Mpv[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_AMB_X2_LV3_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_SUN_Y1_LV3_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_SUN_Y2_LV3_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_SUN_X1_LV3_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_SUN_X2_LV3_Mpv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_4 const tS16 c_assTG_FLL_LV3_Mpv[13] = { 300, 400, 400, 400, 400, 450, 520, 550, 600, 650, 700, 750, 800}; +SECT_VEH_CAL_4 const tS16 c_assTG_FRL_LV3_Mpv[13] = { 300, 400, 400, 400, 400, 450, 550, 580, 630, 680, 730, 780, 830}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_MIN_LV3_Mpv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_MAX_LV3_Mpv[7] = { 600, 600, 800, 800, 800, 800, 950}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_Y1_LV3_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_Y2_LV3_Mpv[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_Y3_LV3_Mpv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_Y4_LV3_Mpv[7] = { 250, 300, 400, 400, 400, 400, 400}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_X1_LV3_Mpv[7] = { -100, -100, -100, -100, -120, -130, -150}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_X2_LV3_Mpv[7] = { -20, -20, -20, -20, -50, -50, -50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_X3_LV3_Mpv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_X4_LV3_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_AMB_Y1_LV3_Mpv[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_AMB_Y2_LV3_Mpv[7] = { 100, 100, 120, 150, 100, 50, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_AMB_X1_LV3_Mpv[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_AMB_X2_LV3_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_SUN_Y1_LV3_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_SUN_Y2_LV3_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_SUN_X1_LV3_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_SUN_X2_LV3_Mpv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_4 const tS16 c_assINCAR_TG_RL_LV3_Mpv[13] = { 190, 195, 200, 215, 230, 235, 240, 255, 270, 280, 290, 300, 310}; +SECT_VEH_CAL_4 const tS16 c_assINCAR_TG_RR_LV3_Mpv[13] = { 190, 195, 200, 215, 230, 235, 240, 255, 270, 280, 290, 300, 310}; +SECT_VEH_CAL_4 const tS16 c_assVTG_RL_LV3_Mpv[13] = { 110, 100, 90, 80, 70, 65, 65, 65, 80, 90, 80, 90, 90}; +SECT_VEH_CAL_4 const tS16 c_assVTG_RR_LV3_Mpv[13] = { 110, 100, 90, 80, 70, 65, 65, 65, 80, 90, 80, 90, 90}; +SECT_VEH_CAL_4 const tS16 c_assVR_MIN_LV3_Mpv[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_4 const tS16 c_assVR_MAX_LV3_Mpv[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_Y1_LV3_Mpv[7] = { 80, 80, 80, 60, -30, -40, -40}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_Y2_LV3_Mpv[7] = { 25, 25, 25, 30, 0, -20, -20}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_Y3_LV3_Mpv[7] = { 10, 10, 10, 5, 0, 20, 25}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_Y4_LV3_Mpv[7] = { 20, 20, 20, 30, 50, 50, 50}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_X1_LV3_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_X2_LV3_Mpv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_X3_LV3_Mpv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_X4_LV3_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assVR_AMB_Y1_LV3_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVR_AMB_Y2_LV3_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVR_AMB_X1_LV3_Mpv[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_4 const tS16 c_assVR_AMB_X2_LV3_Mpv[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_4 const tS16 c_assVR_SUN_Y1_LV3_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVR_SUN_Y2_LV3_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVR_SUN_X1_LV3_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assVR_SUN_X2_LV3_Mpv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_4 const tS16 c_assTG_RL_LV3_Mpv[13] = { 50, 50, 50, 80, 120, 150, 190, 250, 350, 370, 450, 500, 600}; +SECT_VEH_CAL_4 const tS16 c_assTG_RR_LV3_Mpv[13] = { 50, 50, 50, 80, 120, 150, 190, 250, 350, 370, 450, 500, 600}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_MIN_LV3_Mpv[7] = { 51, 51, 51, 51, 51, 51, 51}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_MAX_LV3_Mpv[7] = { 400, 400, 450, 650, 800, 800, 800}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_Y1_LV3_Mpv[7] = { -100, -100, -100, -100, -100, -100, -250}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_Y2_LV3_Mpv[7] = { -50, -50, -50, -50, -50, -80, -100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_Y3_LV3_Mpv[7] = { 50, 50, 50, 50, 80, 80, 80}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_Y4_LV3_Mpv[7] = { 250, 250, 250, 350, 450, 450, 450}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_X1_LV3_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_X2_LV3_Mpv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_X3_LV3_Mpv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_X4_LV3_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_AMB_Y1_LV3_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_AMB_Y2_LV3_Mpv[7] = { 10, 20, 30, 50, 60, 70, 80}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_AMB_X1_LV3_Mpv[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_AMB_X2_LV3_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_SUN_Y1_LV3_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_SUN_Y2_LV3_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_SUN_X1_LV3_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_SUN_X2_LV3_Mpv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_DUCT_TIME_FR_LV3_Mpv[7] = { 3600, 3600, 3600, 3600, 3600, 3600, 3600}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_DUCT_TIME_FL_LV3_Mpv[7] = { 3600, 3600, 3600, 3600, 3600, 3600, 3600}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_DUCT_RATE_LV3_Mpv[7] = { 5, 5, 5, 1, 1, 1, 1}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_DUCT_MAX_LV3_Mpv[7] = { 800, 800, 800, 800, 700, 600, 500}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_AF_TIME_FR_LV3_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_AF_TIME_FL_LV3_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_AF_RATE_LV3_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_AF_MAX_LV3_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +/* ------------------------------------------Lv3 : End*/ +SECT_VEH_CAL_4 const tS16 c_assINCAR_TG_FL_LV4_Mpv[13] = { 180, 190, 200, 210, 230, 250, 265, 270, 275, 285, 290, 295, 320}; +SECT_VEH_CAL_4 const tS16 c_assINCAR_TG_FR_LV4_Mpv[13] = { 180, 190, 200, 210, 230, 250, 265, 270, 275, 285, 290, 295, 320}; +SECT_VEH_CAL_4 const tS16 c_assVTG_FL_LV4_Mpv[13] = { 90, 83, 75, 62, 55, 60, 70, 70, 75, 78, 91, 93, 100}; +SECT_VEH_CAL_4 const tS16 c_assVTG_FR_LV4_Mpv[13] = { 90, 83, 75, 62, 55, 60, 70, 70, 75, 78, 91, 93, 100}; +SECT_VEH_CAL_4 const tS16 c_assVF_MIN_LV4_Mpv[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_4 const tS16 c_assVF_MAX_LV4_Mpv[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_Y1_LV4_Mpv[7] = { 15, 15, 25, 25, 0, -15, -20}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_Y2_LV4_Mpv[7] = { 5, 10, 15, 0, 0, -10, -15}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_Y3_LV4_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_Y4_LV4_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_X1_LV4_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_X2_LV4_Mpv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_X3_LV4_Mpv[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_X4_LV4_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assVF_AMB_Y1_LV4_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVF_AMB_Y2_LV4_Mpv[7] = { 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_4 const tS16 c_assVF_AMB_X1_LV4_Mpv[7] = { -10, -10, -10, -10, -10, -10, -10}; +SECT_VEH_CAL_4 const tS16 c_assVF_AMB_X2_LV4_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assVF_SUN_Y1_LV4_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVF_SUN_Y2_LV4_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVF_SUN_X1_LV4_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assVF_SUN_X2_LV4_Mpv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_4 const tS16 c_assTG_FLU_LV4_Mpv[13] = { 300, 50, 150, 200, 220, 330, 410, 420, 430, 450, 470, 490, 520}; +SECT_VEH_CAL_4 const tS16 c_assTG_FRU_LV4_Mpv[13] = { 50, 50, 150, 200, 220, 325, 400, 410, 418, 425, 450, 475, 500}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_MIN_LV4_Mpv[7] = { 20, 20, 20, 30, 200, 200, 250}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_MAX_LV4_Mpv[7] = { 450, 450, 550, 800, 800, 800, 800}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_Y1_LV4_Mpv[7] = { -100, -100, -150, -180, -200, -300, -350}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_Y2_LV4_Mpv[7] = { -30, -30, -70, -80, -65, -65, -65}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_Y3_LV4_Mpv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_Y4_LV4_Mpv[7] = { 200, 200, 200, 100, 70, 60, 50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_X1_LV4_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_X2_LV4_Mpv[7] = { -20, -20, -20, -30, -30, -20, -20}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_X3_LV4_Mpv[7] = { 20, 20, 20, 35, 30, 30, 30}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_X4_LV4_Mpv[7] = { 100, 100, 100, 100, 60, 30, 30}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_AMB_Y1_LV4_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_AMB_Y2_LV4_Mpv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_AMB_X1_LV4_Mpv[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_AMB_X2_LV4_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_SUN_Y1_LV4_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_SUN_Y2_LV4_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_SUN_X1_LV4_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_SUN_X2_LV4_Mpv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_4 const tS16 c_assTG_FLL_LV4_Mpv[13] = { 400, 450, 450, 500, 580, 625, 720, 750, 750, 750, 770, 800, 850}; +SECT_VEH_CAL_4 const tS16 c_assTG_FRL_LV4_Mpv[13] = { 400, 450, 450, 500, 550, 625, 700, 720, 725, 730, 750, 780, 850}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_MIN_LV4_Mpv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_MAX_LV4_Mpv[7] = { 600, 600, 800, 800, 800, 900, 900}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_Y1_LV4_Mpv[7] = { -100, -100, -100, -50, -60, -150, -200}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_Y2_LV4_Mpv[7] = { -50, -50, -50, -20, -20, -50, -80}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_Y3_LV4_Mpv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_Y4_LV4_Mpv[7] = { 400, 400, 400, 400, 200, 200, 200}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_X1_LV4_Mpv[7] = { -100, -100, -100, -100, -100, -200, -150}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_X2_LV4_Mpv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_X3_LV4_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_X4_LV4_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_AMB_Y1_LV4_Mpv[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_AMB_Y2_LV4_Mpv[7] = { 50, 50, 50, 50, 60, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_AMB_X1_LV4_Mpv[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_AMB_X2_LV4_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_SUN_Y1_LV4_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_SUN_Y2_LV4_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_SUN_X1_LV4_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_SUN_X2_LV4_Mpv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_4 const tS16 c_assINCAR_TG_RL_LV4_Mpv[13] = { 190, 195, 200, 215, 230, 240, 250, 255, 260, 265, 270, 280, 300}; +SECT_VEH_CAL_4 const tS16 c_assINCAR_TG_RR_LV4_Mpv[13] = { 190, 195, 200, 215, 230, 240, 250, 255, 260, 265, 270, 280, 300}; +SECT_VEH_CAL_4 const tS16 c_assVTG_RL_LV4_Mpv[13] = { 110, 100, 90, 85, 80, 75, 75, 75, 80, 85, 90, 90, 90}; +SECT_VEH_CAL_4 const tS16 c_assVTG_RR_LV4_Mpv[13] = { 110, 100, 90, 85, 80, 75, 75, 75, 80, 85, 90, 90, 90}; +SECT_VEH_CAL_4 const tS16 c_assVR_MIN_LV4_Mpv[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_4 const tS16 c_assVR_MAX_LV4_Mpv[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_Y1_LV4_Mpv[7] = { 60, 50, 40, -15, -40, -40, -40}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_Y2_LV4_Mpv[7] = { 30, 40, 40, 0, -30, -20, -20}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_Y3_LV4_Mpv[7] = { 10, 10, 10, 5, 30, 30, 30}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_Y4_LV4_Mpv[7] = { 20, 50, 70, 100, 100, 80, 80}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_X1_LV4_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_X2_LV4_Mpv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_X3_LV4_Mpv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_X4_LV4_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assVR_AMB_Y1_LV4_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVR_AMB_Y2_LV4_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVR_AMB_X1_LV4_Mpv[7] = { -10, -10, -10, -10, -10, -10, -10}; +SECT_VEH_CAL_4 const tS16 c_assVR_AMB_X2_LV4_Mpv[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_4 const tS16 c_assVR_SUN_Y1_LV4_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVR_SUN_Y2_LV4_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVR_SUN_X1_LV4_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assVR_SUN_X2_LV4_Mpv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_4 const tS16 c_assTG_RL_LV4_Mpv[13] = { 50, 50, 50, 80, 90, 120, 170, 240, 320, 390, 430, 450, 500}; +SECT_VEH_CAL_4 const tS16 c_assTG_RR_LV4_Mpv[13] = { 50, 50, 50, 80, 90, 120, 170, 240, 320, 390, 430, 450, 500}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_MIN_LV4_Mpv[7] = { 51, 51, 51, 51, 51, 51, 51}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_MAX_LV4_Mpv[7] = { 400, 400, 450, 650, 800, 800, 800}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_Y1_LV4_Mpv[7] = { -100, -100, -100, -110, -250, -300, -350}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_Y2_LV4_Mpv[7] = { -50, -50, -50, -80, -150, -150, -150}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_Y3_LV4_Mpv[7] = { 50, 50, 50, 60, 80, 80, 120}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_Y4_LV4_Mpv[7] = { 300, 250, 250, 350, 450, 500, 500}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_X1_LV4_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_X2_LV4_Mpv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_X3_LV4_Mpv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_X4_LV4_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_AMB_Y1_LV4_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_AMB_Y2_LV4_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_AMB_X1_LV4_Mpv[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_AMB_X2_LV4_Mpv[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_SUN_Y1_LV4_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_SUN_Y2_LV4_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_SUN_X1_LV4_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_SUN_X2_LV4_Mpv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_DUCT_TIME_FR_LV4_Mpv[7] = { 3600, 3600, 3600, 3600, 3600, 3600, 3600}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_DUCT_TIME_FL_LV4_Mpv[7] = { 3600, 3600, 3600, 3600, 3600, 3600, 3600}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_DUCT_RATE_LV4_Mpv[7] = { 5, 5, 5, 1, 1, 1, 1}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_DUCT_MAX_LV4_Mpv[7] = { 500, 500, 500, 800, 700, 600, 500}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_AF_TIME_FR_LV4_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_AF_TIME_FL_LV4_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_AF_RATE_LV4_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_AF_MAX_LV4_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +/* ------------------------------------------Lv4 : End*/ +SECT_VEH_CAL_4 const tS16 c_assINCAR_TG_FL_LV5_Mpv[13] = { 180, 190, 200, 210, 230, 235, 240, 250, 270, 290, 310, 330, 350}; +SECT_VEH_CAL_4 const tS16 c_assINCAR_TG_FR_LV5_Mpv[13] = { 180, 190, 200, 210, 230, 235, 240, 250, 270, 290, 310, 330, 350}; +SECT_VEH_CAL_4 const tS16 c_assVTG_FL_LV5_Mpv[13] = { 90, 83, 75, 62, 55, 55, 70, 70, 75, 78, 91, 93, 95}; +SECT_VEH_CAL_4 const tS16 c_assVTG_FR_LV5_Mpv[13] = { 90, 83, 75, 62, 55, 55, 70, 70, 75, 78, 91, 93, 95}; +SECT_VEH_CAL_4 const tS16 c_assVF_MIN_LV5_Mpv[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_4 const tS16 c_assVF_MAX_LV5_Mpv[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_Y1_LV5_Mpv[7] = { 15, 15, 25, 25, 0, -15, -20}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_Y2_LV5_Mpv[7] = { 5, 10, 15, 0, 0, -10, -15}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_Y3_LV5_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_Y4_LV5_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_X1_LV5_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_X2_LV5_Mpv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_X3_LV5_Mpv[7] = { 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_4 const tS16 c_assVF_INC_X4_LV5_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assVF_AMB_Y1_LV5_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVF_AMB_Y2_LV5_Mpv[7] = { 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_4 const tS16 c_assVF_AMB_X1_LV5_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assVF_AMB_X2_LV5_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assVF_SUN_Y1_LV5_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVF_SUN_Y2_LV5_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVF_SUN_X1_LV5_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assVF_SUN_X2_LV5_Mpv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_4 const tS16 c_assTG_FLU_LV5_Mpv[13] = { 50, 70, 150, 220, 250, 350, 420, 450, 480, 500, 525, 550, 600}; +SECT_VEH_CAL_4 const tS16 c_assTG_FRU_LV5_Mpv[13] = { 50, 70, 150, 220, 250, 350, 420, 450, 480, 500, 525, 550, 600}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_MIN_LV5_Mpv[7] = { 20, 20, 20, 30, 200, 200, 250}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_MAX_LV5_Mpv[7] = { 450, 450, 550, 800, 800, 800, 800}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_Y1_LV5_Mpv[7] = { -100, -100, -150, -180, -200, -300, -350}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_Y2_LV5_Mpv[7] = { -30, -30, -70, -80, -65, -65, -65}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_Y3_LV5_Mpv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_Y4_LV5_Mpv[7] = { 200, 200, 200, 100, 70, 60, 50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_X1_LV5_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_X2_LV5_Mpv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_X3_LV5_Mpv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_INC_X4_LV5_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_AMB_Y1_LV5_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_AMB_Y2_LV5_Mpv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_AMB_X1_LV5_Mpv[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_AMB_X2_LV5_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_SUN_Y1_LV5_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_SUN_Y2_LV5_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_SUN_X1_LV5_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FU_SUN_X2_LV5_Mpv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_4 const tS16 c_assTG_FLL_LV5_Mpv[13] = { 400, 450, 480, 500, 580, 625, 720, 750, 750, 750, 800, 850, 900}; +SECT_VEH_CAL_4 const tS16 c_assTG_FRL_LV5_Mpv[13] = { 400, 450, 480, 500, 580, 625, 720, 750, 750, 750, 800, 850, 900}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_MIN_LV5_Mpv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_MAX_LV5_Mpv[7] = { 600, 600, 800, 800, 800, 800, 800}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_Y1_LV5_Mpv[7] = { -100, -100, -100, -50, -60, -150, -200}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_Y2_LV5_Mpv[7] = { -50, -50, -50, -20, -20, -50, -80}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_Y3_LV5_Mpv[7] = { 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_Y4_LV5_Mpv[7] = { 400, 400, 400, 400, 200, 200, 200}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_X1_LV5_Mpv[7] = { -100, -100, -100, -100, -100, -200, -150}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_X2_LV5_Mpv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_X3_LV5_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_INC_X4_LV5_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_AMB_Y1_LV5_Mpv[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_AMB_Y2_LV5_Mpv[7] = { 50, 50, 50, 50, 60, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_AMB_X1_LV5_Mpv[7] = { -50, -50, -50, -50, -50, -50, -50}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_AMB_X2_LV5_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_SUN_Y1_LV5_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_SUN_Y2_LV5_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_SUN_X1_LV5_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assDTG_FL_SUN_X2_LV5_Mpv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_4 const tS16 c_assINCAR_TG_RL_LV5_Mpv[13] = { 190, 195, 200, 215, 230, 235, 240, 260, 270, 285, 300, 310, 320}; +SECT_VEH_CAL_4 const tS16 c_assINCAR_TG_RR_LV5_Mpv[13] = { 190, 195, 200, 215, 230, 235, 240, 260, 270, 285, 300, 310, 320}; +SECT_VEH_CAL_4 const tS16 c_assVTG_RL_LV5_Mpv[13] = { 110, 100, 90, 80, 70, 65, 65, 65, 80, 90, 80, 90, 90}; +SECT_VEH_CAL_4 const tS16 c_assVTG_RR_LV5_Mpv[13] = { 110, 100, 90, 80, 70, 65, 65, 65, 80, 90, 80, 90, 90}; +SECT_VEH_CAL_4 const tS16 c_assVR_MIN_LV5_Mpv[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_4 const tS16 c_assVR_MAX_LV5_Mpv[7] = { 160, 160, 160, 160, 160, 160, 160}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_Y1_LV5_Mpv[7] = { 80, 80, 80, 60, 60, 60, 60}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_Y2_LV5_Mpv[7] = { 25, 25, 25, 30, 10, 10, 10}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_Y3_LV5_Mpv[7] = { -10, -10, -10, 0, 0, 20, 25}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_Y4_LV5_Mpv[7] = { 20, 20, 20, 30, 50, 50, 50}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_X1_LV5_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_X2_LV5_Mpv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_X3_LV5_Mpv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_4 const tS16 c_assVR_INC_X4_LV5_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assVR_AMB_Y1_LV5_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVR_AMB_Y2_LV5_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVR_AMB_X1_LV5_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assVR_AMB_X2_LV5_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assVR_SUN_Y1_LV5_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVR_SUN_Y2_LV5_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assVR_SUN_X1_LV5_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assVR_SUN_X2_LV5_Mpv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_4 const tS16 c_assTG_RL_LV5_Mpv[13] = { 50, 50, 50, 80, 120, 150, 170, 250, 350, 370, 450, 500, 500}; +SECT_VEH_CAL_4 const tS16 c_assTG_RR_LV5_Mpv[13] = { 50, 50, 50, 80, 120, 150, 170, 250, 350, 370, 450, 500, 500}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_MIN_LV5_Mpv[7] = { 51, 51, 51, 51, 51, 51, 51}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_MAX_LV5_Mpv[7] = { 400, 400, 450, 650, 800, 800, 800}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_Y1_LV5_Mpv[7] = { -100, -100, -100, -100, -100, -100, -250}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_Y2_LV5_Mpv[7] = { -50, -50, -50, -50, -50, -80, -100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_Y3_LV5_Mpv[7] = { 50, 50, 50, 50, 80, 80, 80}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_Y4_LV5_Mpv[7] = { 250, 250, 250, 350, 450, 450, 450}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_X1_LV5_Mpv[7] = { -100, -100, -100, -100, -100, -100, -100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_X2_LV5_Mpv[7] = { -20, -20, -20, -20, -20, -20, -20}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_X3_LV5_Mpv[7] = { 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_INC_X4_LV5_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_AMB_Y1_LV5_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_AMB_Y2_LV5_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_AMB_X1_LV5_Mpv[7] = { -10, -10, -10, -10, -10, -10, -10}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_AMB_X2_LV5_Mpv[7] = { 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_SUN_Y1_LV5_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_SUN_Y2_LV5_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_SUN_X1_LV5_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assDTG_R_SUN_X2_LV5_Mpv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_DUCT_TIME_FR_LV5_Mpv[7] = { 3600, 3600, 3600, 3600, 3600, 3600, 3600}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_DUCT_TIME_FL_LV5_Mpv[7] = { 3600, 3600, 3600, 3600, 3600, 3600, 3600}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_DUCT_RATE_LV5_Mpv[7] = { 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_DUCT_MAX_LV5_Mpv[7] = { 1000, 1000, 1000, 1000, 1000, 1000, 1000}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_AF_TIME_FR_LV5_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_AF_TIME_FL_LV5_Mpv[7] = { 300, 300, 300, 300, 300, 300, 300}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_AF_RATE_LV5_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assCORRECT_AF_MAX_LV5_Mpv[7] = { 0, 0, 0, 0, 0, 0, 0}; +/* ------------------------------------------Lv5 : End*/ +SECT_VEH_CAL_4 const tS16 c_assDUCT_TGT_DEF_VALVE_L_Mpv[11] = { 350, 300, 300, 250, 200, 150, 120, 100, 70, 50, 50}; +SECT_VEH_CAL_4 const tS16 c_assDUCT_TGT_DEF_VALVE_R_Mpv[11] = { 350, 300, 300, 250, 200, 150, 120, 100, 70, 50, 50}; +/* ------------------------------------------DuctTgt Increase : End*/ +SECT_VEH_CAL_4 const tS16 c_assAMB_LV_UP_Mpv[5] = { 350, 200, 50, -150, -300}; +SECT_VEH_CAL_4 const tS16 c_assAMB_LV_DN_Mpv[5] = { 400, 250, 100, -100, -250}; +SECT_VEH_CAL_4 const tS16 c_assAMB_LV_TG_Mpv[6] = { 450, 350, 200, 0, -150, -350}; +/* ------------------------------------------Ambient LEVEL : End*/ +SECT_VEH_CAL_4 const tU08 c_aucMODE_BY_SET_F_LV0_Mpv[13] = { 30, 30, 30, 30, 20, 20, 20, 20, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_4 const tU08 c_aucMODE_BY_SET_F_LV1_Mpv[13] = { 30, 30, 30, 30, 20, 20, 20, 20, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_4 const tU08 c_aucMODE_BY_SET_F_LV2_Mpv[13] = { 30, 30, 30, 20, 20, 20, 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_4 const tU08 c_aucMODE_BY_SET_F_LV3_Mpv[13] = { 20, 20, 20, 20, 20, 20, 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_4 const tU08 c_aucMODE_BY_SET_F_LV4_Mpv[13] = { 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_4 const tU08 c_aucMODE_BY_SET_F_LV5_Mpv[13] = { 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_4 const tU16 c_ausMODE_BY_DUCT_TG_R_LV0_Mpv[7] = { 250, 300, 450, 550, 120, 150, 180}; +SECT_VEH_CAL_4 const tU16 c_ausMODE_BY_DUCT_TG_R_LV1_Mpv[7] = { 250, 300, 450, 550, 120, 150, 180}; +SECT_VEH_CAL_4 const tU16 c_ausMODE_BY_DUCT_TG_R_LV2_Mpv[7] = { 250, 300, 450, 550, 120, 150, 180}; +SECT_VEH_CAL_4 const tU16 c_ausMODE_BY_DUCT_TG_R_LV3_Mpv[7] = { 250, 300, 450, 550, 120, 150, 180}; +SECT_VEH_CAL_4 const tU16 c_ausMODE_BY_DUCT_TG_R_LV4_Mpv[7] = { 250, 300, 450, 550, 120, 150, 180}; +SECT_VEH_CAL_4 const tU16 c_ausMODE_BY_DUCT_TG_R_LV5_Mpv[7] = { 250, 300, 450, 550, 120, 150, 180}; +/* ------------------------------------------Mode depend on SET for each level : End*/ +SECT_VEH_CAL_4 const tS16 c_ssPREC_REC_ON_AMB_Mpv = 340; +SECT_VEH_CAL_4 const tS16 c_ssPREC_REC_OFF_AMB_Mpv = 320; +SECT_VEH_CAL_4 const tU08 c_aucPREC_VEH_SPD_OSA_Mpv[13] = { 100, 95, 92, 86, 83, 80, 75, 70, 65, 60, 55, 52, 50}; +SECT_VEH_CAL_4 const tS16 c_assPRE_AMB_RANGE_WINTER_Mpv[7] = { -450, -300, -200, -150, -80, 0, 50}; +SECT_VEH_CAL_4 const tU08 c_aucPREC_OSA_WINTER_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tU08 c_aucPREC_REC_WINTER_Mpv[7] = { 15, 13, 10, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tU16 c_ausPREC_HUMIDITY_NOK_Mpv[7] = { 900, 900, 900, 900, 900, 900, 900}; +SECT_VEH_CAL_4 const tU16 c_ausPREC_HUMIDITY_OK_Mpv[7] = { 700, 700, 700, 700, 700, 700, 700}; +SECT_VEH_CAL_4 const tU16 c_ausPREC_ENTRY_RPM_Mpv[3] = { 450, 650, 800}; +SECT_VEH_CAL_4 const tU16 c_ausPREC_EXIT_RPM_Mpv[3] = { 450, 550, 800}; +SECT_VEH_CAL_4 const tU16 c_ausPREC_COMP_SPD_1_Mpv[3] = { 450, 500, 550}; +SECT_VEH_CAL_4 const tU08 c_aucPREC_OSA_SUMMER_1_Mpv[3] = { 80, 70, 60}; +SECT_VEH_CAL_4 const tU08 c_aucPREC_REC_SUMMER_1_Mpv[3] = { 20, 30, 45}; +SECT_VEH_CAL_4 const tS16 c_assPREC_EVA_DIFF_FB_TG_F_Mpv[7] = { 0, 5, 10, 15, 20, 25, 30}; +SECT_VEH_CAL_4 const tU08 c_aucPREC_OSA_SUMMER_2_Mpv[7] = { 50, 45, 40, 35, 30, 25, 20}; +SECT_VEH_CAL_4 const tU08 c_aucPREC_REC_SUMMER_2_Mpv[7] = { 50, 55, 60, 65, 70, 75, 80}; +SECT_VEH_CAL_4 const tU08 c_aucPREC_EVA_DIFF_Mpv[4] = { 80, 80, 50, 50}; +SECT_VEH_CAL_4 const tU08 c_ucPREC_OSA_SUMMER_3_Mpv = 0; +SECT_VEH_CAL_4 const tU08 c_ucPREC_REC_SUMMER_3_Mpv = 100; +/* ------------------------------------------AutoRec : End*/ +SECT_VEH_CAL_4 const tU16 c_ausFLOW_FR_VE2VALVE_Mpv[9] = { 100, 100, 100, 100, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tU16 c_ausFLOW_FR_BIVALVE_Mpv[9] = { 40, 40, 40, 40, 30, 0, 30, 0, 0}; +SECT_VEH_CAL_4 const tU16 c_ausFLOW_FR_BI2VALVE_Mpv[9] = { 70, 70, 70, 70, 30, 0, 30, 0, 0}; +SECT_VEH_CAL_4 const tU16 c_ausFLOW_FR_AF2VALVE_Mpv[9] = { 30, 25, 25, 30, 30, 0, 30, 0, 0}; +SECT_VEH_CAL_4 const tU16 c_ausFLOW_FR_AF2VALVE_SUMMER_Mpv[9] = { 25, 25, 25, 25, 30, 0, 30, 0, 10}; +SECT_VEH_CAL_4 const tU16 c_ausFLOW_FR_FO2VALVE_Mpv[9] = { 0, 0, 0, 0, 100, 0, 100, 0, 0}; +SECT_VEH_CAL_4 const tU16 c_ausFLOW_FR_FD2VALVE_Mpv[9] = { 0, 0, 0, 0, 100, 0, 100, 0, 100}; +SECT_VEH_CAL_4 const tU16 c_ausFLOW_FR_DE2VALVE_Mpv[9] = { 0, 0, 0, 0, 10, 0, 10, 0, 100}; +SECT_VEH_CAL_4 const tU16 c_ausFLOW_FR_TR2VALVE_Mpv[9] = { 55, 55, 55, 55, 100, 0, 100, 0, 100}; +SECT_VEH_CAL_4 const tU16 c_ausFLOW_FR_HI2VALVE_Mpv[9] = { 50, 50, 50, 50, 0, 0, 0, 0, 100}; +SECT_VEH_CAL_4 const tU16 c_ausFLOW_FR_BIVALVE_MANUAL_Mpv[9] = { 50, 50, 50, 50, 60, 0, 60, 0, 0}; +SECT_VEH_CAL_4 const tU16 c_ausFLOW_RE_VENT_Mpv[6] = { 70, 80, 80, 70, 0, 0}; +SECT_VEH_CAL_4 const tU16 c_ausFLOW_RE_BI2VALVE_Mpv[6] = { 70, 80, 80, 70, 100, 100}; +SECT_VEH_CAL_4 const tU16 c_ausFLOW_RE_FO2VALVE_Mpv[6] = { 0, 20, 20, 0, 100, 100}; +SECT_VEH_CAL_4 const tU16 c_ausFLOW_RE_VENT_2_Mpv[6] = { 30, 60, 60, 30, 50, 50}; +SECT_VEH_CAL_4 const tU16 c_ausFLOW_RE_BI2VALVE_2_Mpv[6] = { 50, 30, 30, 50, 100, 100}; +SECT_VEH_CAL_4 const tU16 c_ausFLOW_RE_VENT_3_Mpv[6] = { 70, 80, 80, 70, 0, 0}; +SECT_VEH_CAL_4 const tU16 c_ausFLOW_RE_BI2VALVE_3_Mpv[6] = { 20, 20, 20, 20, 100, 100}; +SECT_VEH_CAL_4 const tU16 c_ausFLOW_RE_VENT_MANUAL_Mpv[6] = { 70, 80, 80, 70, 0, 0}; +SECT_VEH_CAL_4 const tU16 c_ausFLOW_RE_BI2VALVE_MANUAL_Mpv[6] = { 70, 40, 40, 70, 100, 100}; +/* ------------------------------------------Flow Control Valve: End*/ +SECT_VEH_CAL_4 const tS16 c_assFLOW_BI_AMB_TGT_Mpv[6] = { 450, 350, 200, 0, -150, -350}; +SECT_VEH_CAL_4 const tU08 c_aucFLOW_BI_VENT_PLUS_Mpv[12] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_4 const tS16 c_assFLOW_BI_TEMP_TGT_Mpv[12] = { 300, 350, 400, 450, 500, 550, 300, 350, 400, 450, 500, 550}; +SECT_VEH_CAL_4 const tU08 c_aucFLOW_BI_FOOT_PLUS_Mpv[12] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_4 const tU08 c_aucFLOW_BI_VENT_VALVE_MAX_Mpv[12] = { 85, 85, 85, 85, 85, 85, 60, 60, 60, 60, 60, 60}; +SECT_VEH_CAL_4 const tU08 c_aucFLOW_BI_FOOT_VALVE_MAX_Mpv[12] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tU08 c_aucFLOW_BI_VENT_VALVE_MIN_Mpv[12] = { 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_4 const tU08 c_aucFLOW_BI_FOOT_VALVE_MIN_Mpv[12] = { 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}; +/* ------------------------------------------Bi 2 level conditions: End*/ +SECT_VEH_CAL_4 const tS16 c_assFLOW_B2I_AMB_TGT_Mpv[6] = { 450, 350, 200, 0, -150, -350}; +SECT_VEH_CAL_4 const tU08 c_aucFLOW_BI2_VENT_PLUS_Mpv[12] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_4 const tS16 c_assFLOW_BI2_TEMP_TGT_Mpv[12] = { 300, 350, 400, 450, 500, 550, 300, 350, 400, 450, 500, 550}; +SECT_VEH_CAL_4 const tU08 c_aucFLOW_BI2_FOOT_PLUS_Mpv[12] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_4 const tU08 c_aucFLOW_BI2_VENT_VALVE_MAX_Mpv[12] = { 85, 85, 85, 85, 85, 85, 80, 80, 80, 80, 80, 80}; +SECT_VEH_CAL_4 const tU08 c_aucFLOW_BI2_FOOT_VALVE_MAX_Mpv[12] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tU08 c_aucFLOW_BI2_VENT_VALVE_MIN_Mpv[12] = { 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_4 const tU08 c_aucFLOW_BI2_FOOT_VALVE_MIN_Mpv[12] = { 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}; +/* ------------------------------------------AF level conditions: End*/ +SECT_VEH_CAL_4 const tS16 c_assFLOW_AF_AMB_TGT_Mpv[6] = { 450, 350, 200, 0, -150, -350}; +SECT_VEH_CAL_4 const tU08 c_aucFLOW_AF_VENT_PLUS_Mpv[12] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2}; +SECT_VEH_CAL_4 const tU08 c_aucFLOW_AF_BLR_AF_TGT_Mpv[6] = { 60, 60, 60, 65, 65, 60}; +SECT_VEH_CAL_4 const tU08 c_aucFLOW_AF_FOOT_PLUS_Mpv[12] = { 20, 20, 20, 100, 150, 150, 20, 20, 20, 100, 150, 150}; +SECT_VEH_CAL_4 const tU08 c_aucFLOW_AF_VENT_VALVE_MAX_Mpv[12] = { 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_4 const tU08 c_aucFLOW_AF_FOOT_VALVE_MAX_Mpv[12] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +/* ------------------------------------------AF level conditions: End*/ +SECT_VEH_CAL_4 const tS16 c_assFLOW_AFSM_AMB_TGT_Mpv[6] = { 450, 350, 200, 0, -150, -350}; +SECT_VEH_CAL_4 const tU08 c_aucFLOW_AFSM_VENT_PLUS_Mpv[12] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_4 const tS16 c_assFLOW_AFSM_TEMP_TGT_Mpv[12] = { 300, 350, 400, 450, 500, 550, 300, 350, 400, 450, 500, 550}; +SECT_VEH_CAL_4 const tU08 c_aucFLOW_AFSM_FOOT_PLUS_Mpv[12] = { 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_4 const tU08 c_aucFLOW_AFSM_VENT_VALVE_MAX_Mpv[12] = { 50, 50, 50, 50, 50, 50, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_4 const tU08 c_aucFLOW_AFSM_FOOT_VALVE_MAX_Mpv[12] = { 60, 60, 60, 60, 60, 60, 50, 50, 50, 50, 50, 50}; +/* ------------------------------------------AF_summer level conditions: End*/ +SECT_VEH_CAL_4 const tU08 c_aucMODE_INDEX_Mpv[11] = { 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 110}; +SECT_VEH_CAL_4 const tS16 c_assFOOT_STEP_DUCT_TGT_Mpv[7] = { -400, -250, -100, 0, 100, 250, 400}; +SECT_VEH_CAL_4 const tS16 c_assBLR_FOOT_IND_Mpv[7] = { 25, 10, 5, 0, 5, 10, 25}; +SECT_VEH_CAL_4 const tS08 c_ascFOOT_STEP_VALVE_P1_Mpv[11] = { 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_4 const tS08 c_ascFOOT_STEP_VALVE_P2_Mpv[11] = { 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25}; +SECT_VEH_CAL_4 const tS08 c_ascFOOT_STEP_VALVE_P3_Mpv[11] = { 40, 40, 40, 40, 40, 40, 40, 40, 40, 40, 40}; +SECT_VEH_CAL_4 const tS08 c_ascFOOT_STEP_VALVE_M1_Mpv[11] = { 10, 0, 10, -10, -10, -10, -10, 10, -10, -10, -10}; +SECT_VEH_CAL_4 const tS08 c_ascFOOT_STEP_VALVE_M2_Mpv[11] = { 25, 0, 10, -10, -10, -25, -25, 10, -25, -25, -25}; +SECT_VEH_CAL_4 const tS08 c_ascFOOT_STEP_VALVE_M3_Mpv[11] = { 40, 0, 10, -15, -15, -40, -40, 10, -40, -40, -25}; +SECT_VEH_CAL_4 const tS16 c_assFOOT_STEP_BLR_P1_Mpv[11] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_4 const tS16 c_assFOOT_STEP_BLR_P2_Mpv[11] = { 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_4 const tS16 c_assFOOT_STEP_BLR_P3_Mpv[11] = { 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 10}; +SECT_VEH_CAL_4 const tS16 c_assFOOT_STEP_BLR_M1_Mpv[11] = { 5, 5, 5, -5, -5, -5, -5, 5, -5, -5, -5}; +SECT_VEH_CAL_4 const tS16 c_assFOOT_STEP_BLR_M2_Mpv[11] = { 10, 10, 10, -5, -5, -5, -5, 5, -5, -5, -5}; +SECT_VEH_CAL_4 const tS16 c_assFOOT_STEP_BLR_M3_Mpv[11] = { 20, 20, 10, -5, -5, -5, -5, 5, -5, -5, -5}; +/* ------------------------------------------Individual foot temperature: End*/ +SECT_VEH_CAL_4 const tU08 c_aucREAR_FOOT_VALVE_AMB_LV2_Mpv[13] = { 0, 0, 0, 0, 0, 0, 5, 10, 15, 20, 25, 30, 35}; +SECT_VEH_CAL_4 const tU08 c_aucREAR_FOOT_VALVE_AMB_LV3_Mpv[13] = { 0, 0, 0, 0, 0, 0, 5, 10, 15, 20, 25, 30, 35}; +SECT_VEH_CAL_4 const tU08 c_aucREAR_FOOT_VALVE_AMB_LV4_Mpv[13] = { 0, 0, 0, 0, 0, 0, 5, 10, 15, 20, 25, 30, 35}; +/* ------------------------------------------Blowing foots from Rear HVAC: End*/ +SECT_VEH_CAL_4 const tU16 c_ausFLOW_FR_VE2BLR_AF_Mpv[8] = { 0, 20, 40, 65, 90, 115, 140, 160}; +SECT_VEH_CAL_4 const tU16 c_ausFLOW_FR_BIVALVE_AF_Mpv[8] = { 0, 20, 40, 65, 90, 115, 140, 160}; +SECT_VEH_CAL_4 const tU16 c_ausFLOW_FR_BI2BLR_AF_Mpv[8] = { 0, 20, 40, 65, 90, 115, 140, 160}; +SECT_VEH_CAL_4 const tU16 c_ausFLOW_FR_FO2BLR_AF_Mpv[8] = { 0, 20, 40, 65, 90, 115, 140, 160}; +SECT_VEH_CAL_4 const tU16 c_ausFLOW_FR_AF2VALVE_AF_Mpv[8] = { 0, 20, 40, 65, 90, 115, 140, 160}; +SECT_VEH_CAL_4 const tU16 c_ausFLOW_FR_AF2VALVE_SUMMER_AF_Mpv[8] = { 0, 20, 40, 65, 90, 115, 140, 160}; +SECT_VEH_CAL_4 const tU16 c_ausFLOW_FR_FD2BLR_AF_Mpv[8] = { 0, 20, 40, 65, 90, 115, 140, 160}; +SECT_VEH_CAL_4 const tU16 c_ausFLOW_FR_DE2BLR_AF_Mpv[8] = { 0, 20, 40, 65, 90, 115, 140, 160}; +SECT_VEH_CAL_4 const tU16 c_ausFLOW_FR_TR2BLR_AF_Mpv[8] = { 0, 20, 40, 65, 90, 115, 140, 160}; +SECT_VEH_CAL_4 const tU16 c_ausFLOW_FR_HI2BLR_AF_Mpv[8] = { 0, 20, 40, 65, 90, 115, 140, 160}; +SECT_VEH_CAL_4 const tU16 c_ausFLOW_RE_VE2BLR_AF_Mpv[8] = { 0, 20, 40, 65, 90, 115, 140, 160}; +SECT_VEH_CAL_4 const tU16 c_ausFLOW_RE_BI2BLR_AF_Mpv[8] = { 0, 20, 40, 65, 90, 115, 140, 160}; +SECT_VEH_CAL_4 const tU16 c_ausFLOW_RE_FO2BLR_AF_Mpv[8] = { 0, 20, 40, 65, 90, 115, 140, 160}; +/* ------------------------------------------Flow Control AF: End*/ +SECT_VEH_CAL_4 const tS08 c_ascAUTO_STEP_AF_F_Mpv[5] = { -35, -15, 0, 15, 30}; +SECT_VEH_CAL_4 const tS08 c_ascAUTO_STEP_AF_R_Mpv[5] = { -35, -15, 0, 15, 30}; +SECT_VEH_CAL_4 const tS16 c_assAUTO_STEP_DUCT_TG_U_F_LV0_1_Mpv[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assAUTO_STEP_DUCT_TG_U_F_LV2_3_Mpv[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assAUTO_STEP_DUCT_TG_U_F_LV4_5_Mpv[10] = { -50, 0, 0, -50, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assAUTO_STEP_DUCT_TG_L_F_LV0_1_Mpv[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assAUTO_STEP_DUCT_TG_L_F_LV2_3_Mpv[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assAUTO_STEP_DUCT_TG_L_F_LV4_5_Mpv[10] = { 50, 50, 0, -128, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assAUTO_STEP_DUCT_TG_R_LV0_1_Mpv[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assAUTO_STEP_DUCT_TG_R_LV2_3_Mpv[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tS16 c_assAUTO_STEP_DUCT_TG_R_LV4_5_Mpv[10] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +/* ------------------------------------------5 AUTO mode: End*/ +SECT_VEH_CAL_4 const tU16 c_ausVALVE_SPACE_Mpv[6] = { 300, 300, 300, 269, 275, 215}; +SECT_VEH_CAL_4 const tU08 c_aucVALVE_SECTION_S1_F_SIDE_VENT_Mpv[9] = { 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_4 const tU08 c_aucVALVE_SECTION_S1_F_CENT_VENT_Mpv[9] = { 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_4 const tU08 c_aucVALVE_SECTION_S1_F_DRIVER_FOOT_Mpv[9] = { 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_4 const tU08 c_aucVALVE_SECTION_S1_F_RIGHT_PASS_Mpv[9] = { 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_4 const tU08 c_aucBLR_SPD_V1_1_F_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tU08 c_aucBLR_SPD_K2_1_F_SIDE_VENT_Mpv[10] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tU08 c_aucBLR_SPD_K2_2_F_CENT_VENT_Mpv[10] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tU08 c_aucBLR_SPD_K2_3_F_DRIVER_FOOT_Mpv[10] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tU08 c_aucBLR_SPD_K2_4_F_RIGHT_PASS_Mpv[13] = { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tU16 c_ausVALVE_VEH_SPD_Mpv[13] = { 0, 40, 60, 80, 90, 110, 130, 150, 170, 190, 220, 250, 300}; +SECT_VEH_CAL_4 const tU08 c_aucVALVE_VEH_SPD_SIDE_VENT_Mpv[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_4 const tU08 c_aucVALVE_VEH_SPD_SIDE_BI_Mpv[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_4 const tU08 c_aucVALVE_VEH_SPD_SIDE_AFOOT_Mpv[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_4 const tU08 c_aucVALVE_VEH_SPD_CNET_VENT_Mpv[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_4 const tU08 c_aucVALVE_VEH_SPD_CENT_BI_Mpv[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_4 const tU08 c_aucVALVE_VEH_SPD_CENT_AFOOT_Mpv[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_4 const tU08 c_aucVALVE_VEH_SPD_FOOT_BI_Mpv[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_4 const tU08 c_aucVALVE_VEH_SPD_FOOT_AFOOT_Mpv[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_4 const tU08 c_aucVALVE_VEH_SPD_2FOOT_Mpv[13] = { 0, 15, 16, 18, 20, 22, 25, 26, 28, 30, 35, 36, 40}; +SECT_VEH_CAL_4 const tU08 c_aucBLR_SPD_VEH_SPD_V1_3_Mpv[12] = { 100, 70, 30, 100, 70, 30, 100, 70, 30, 100, 70, 30}; +SECT_VEH_CAL_4 const tU08 c_aucFRONT_SIDE_DRS_PERCENT_Mpv[12] = { 100, 70, 30, 100, 70, 30, 100, 70, 30, 100, 70, 30}; +SECT_VEH_CAL_4 const tU08 c_aucFRONT_CENT_DRS_PERCENT_Mpv[12] = { 100, 70, 30, 100, 70, 30, 100, 70, 30, 100, 70, 30}; +/* ------------------------------------------Different blower speed FRONT MODE: End*/ +SECT_VEH_CAL_4 const tU08 c_aucVALVE_S1_R_BIPILLAR_Mpv[8] = { 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_4 const tU08 c_aucVALVE_S1_R_CENT_VENT_Mpv[9] = { 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_4 const tU08 c_aucVALVE_S1_R_FOOT_Mpv[5] = { 10, 10, 10, 10, 10}; +SECT_VEH_CAL_4 const tU08 c_aucVALVE_PERC_R_BIPILLAR_Mpv[10] = { 10, 20, 30, 40, 50, 60, 70, 80, 90, 100}; +SECT_VEH_CAL_4 const tU08 c_aucVALVE_PERC_R_CENT_VENT_Mpv[10] = { 10, 20, 30, 40, 50, 60, 70, 80, 90, 100}; +SECT_VEH_CAL_4 const tU08 c_aucVALVE_PERC_R_FOOT_Mpv[10] = { 10, 20, 30, 40, 50, 60, 70, 80, 90, 100}; +SECT_VEH_CAL_4 const tU08 c_aucBLR_SPD_V1_1_R_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tU08 c_aucREAR_CEN_MIN_VALUE_BY_DRS_ZERO_Mpv[7] = { 30, 29, 28, 27, 24, 22, 20}; +SECT_VEH_CAL_4 const tU08 c_aucBLR_SPD_K2_1_R_BIPILLAR_MIN_Mpv[8] = { 100, 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tU08 c_aucBLR_SPD_K2_2_R_CENT_VENT_MIN_Mpv[9] = { 85, 85, 85, 85, 85, 85, 85, 85, 85}; +SECT_VEH_CAL_4 const tU08 c_aucBLR_SPD_K2_3_R_FOOT_MIN_Mpv[5] = { 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tU08 c_aucBLR_SPD_K2_1_R_BIPILLAR_MAX_Mpv[8] = { 120, 120, 120, 120, 120, 120, 120, 120}; +SECT_VEH_CAL_4 const tU08 c_aucBLR_SPD_K2_2_R_CENT_VENTR_MAX_Mpv[9] = { 122, 122, 122, 122, 122, 122, 122, 122, 122}; +SECT_VEH_CAL_4 const tU08 c_aucBLR_SPD_K2_3_R_FOOTR_MAX_Mpv[5] = { 130, 130, 130, 130, 130}; +SECT_VEH_CAL_4 const tU08 c_aucREAR_SIDE_DRS_PERCENT_VALVE_Mpv[9] = { 100, 70, 30, 100, 70, 30, 100, 70, 30}; +SECT_VEH_CAL_4 const tU08 c_aucREAR_CENT_DRS_PERCENT_VALVE_Mpv[9] = { 100, 70, 30, 100, 70, 30, 100, 70, 30}; +SECT_VEH_CAL_4 const tU08 c_aucREAR_SIDE_DRS_PERCENT_AF_Mpv[9] = { 100, 70, 30, 100, 70, 30, 100, 70, 30}; +SECT_VEH_CAL_4 const tU08 c_aucREAR_CENT_DRS_PERCENT_AF_Mpv[9] = { 100, 70, 30, 100, 70, 30, 100, 70, 30}; +/* ------------------------------------------Different blower speed REAR MODE: End*/ +SECT_VEH_CAL_4 const tU16 c_ausMIN_PWM_Mpv[2] = { 150, 150}; +/* ------------------------------------------MinPWM: End*/ +SECT_VEH_CAL_4 const tS16 c_assSTART_ENTER_COOLANT_Mpv[6] = { 300, 400, 400, 300, 360, 360}; +SECT_VEH_CAL_4 const tS16 c_assSTART_COOLANT_STEP0_TO_1_Mpv[8] = { 0, 400, 400, 400, 300, 400, 400, 400}; +SECT_VEH_CAL_4 const tS16 c_assSTART_COOLANT_TO_STEP2_Mpv[3] = { 800, 800, 850}; +SECT_VEH_CAL_4 const tS16 c_assSTART_COOLANT_STEP1_BLR_F_Mpv[6] = { 0, 0, 0, 700, 650, 650}; +SECT_VEH_CAL_4 const tS16 c_assSTART_COOLANT_STEP1_BLR_R_Mpv[6] = { 0, 0, 700, 600, 600, 600}; +SECT_VEH_CAL_4 const tS16 c_assSTART_ENTER_INCAR_Mpv[12] = { 500, 500, 500, 200, 0, 0, 500, 500, 200, 50, 50, 50}; +SECT_VEH_CAL_4 const tU16 c_ausSTART_ENTER_SETTEMP_Mpv[12] = { 260, 250, 0, 0, 0, 0, 260, 250, 200, 200, 0, 0}; +SECT_VEH_CAL_4 const tU08 c_aucSTART_INCAR_FLT_UP_Mpv[12] = { 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_4 const tU08 c_aucSTART_INCAR_FLT_DN_Mpv[12] = { 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_4 const tU08 c_aucSTART_VALVE_IDX_STEP1_Mpv[12] = { 10, 10, 10, 70, 70, 70, 120, 120, 140, 140, 140, 140}; +SECT_VEH_CAL_4 const tU08 c_aucSTART_AUTODEMIST2_STEP2_Mpv[6] = { 0, 0, 1, 1, 1, 1}; +SECT_VEH_CAL_4 const tU08 c_aucSTART_ELEC_WINDOW_Mpv[12] = { 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 1, 1}; +SECT_VEH_CAL_4 const tU16 c_ausSTART_BLR_AF_STEP12_F_Mpv[12] = { 160, 160, 120, 60, 60, 60, 140, 140, 100, 140, 140, 140}; +SECT_VEH_CAL_4 const tU16 c_ausSTART_BLR_AF_STEP12_R_Mpv[12] = { 160, 160, 60, 60, 60, 60, 140, 140, 100, 140, 140, 140}; +SECT_VEH_CAL_4 const tU16 c_ausSTART_BLR_SPD_STEP2_F_Mpv[12] = { 5, 5, 1, 1, 1, 1, 2, 2, 2, 3, 4, 4}; +SECT_VEH_CAL_4 const tU16 c_ausSTART_BLR_SPD_STEP2_R_Mpv[12] = { 5, 5, 1, 1, 1, 1, 2, 2, 2, 3, 4, 4}; +SECT_VEH_CAL_4 const tU08 c_aucSTART_DUCT_TGT_STEP2_FX_U_Mpv[12] = { 5, 5, 5, 50, 60, 60, 3, 3, 3, 3, 3, 3}; +SECT_VEH_CAL_4 const tU08 c_aucSTART_DUCT_TGT_STEP2_FX_L_Mpv[12] = { 15, 15, 15, 80, 80, 80, 6, 6, 6, 20, 30, 30}; +SECT_VEH_CAL_4 const tU08 c_aucSTART_DUCT_TGT_STEP2_RX_Mpv[12] = { 5, 5, 30, 60, 60, 80, 3, 3, 3, 6, 6, 6}; +SECT_VEH_CAL_4 const tU08 c_aucSTART_VALVE_CHANGE_SPD_F_Mpv[12] = { 1, 1, 1, 1, 1, 1, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_4 const tU08 c_aucSTART_VALVE_CHANGE_SPD_R_Mpv[12] = { 1, 1, 1, 1, 1, 1, 5, 5, 5, 5, 5, 5}; +SECT_VEH_CAL_4 const tU16 c_ausSTART_TIME_STEP1_TO_2_Mpv[12] = { 300, 180, 180, 1200, 1200, 1800, 300, 180, 1200, 1200, 1800, 1800}; +SECT_VEH_CAL_4 const tU16 c_ausSTART_TIME_STEP2_TO_3_Mpv[12] = { 180, 180, 180, 600, 600, 1200, 300, 180, 1200, 1200, 1200, 1200}; +SECT_VEH_CAL_4 const tS16 c_assSTART_INCAR_STEP1_TO_2_Mpv[12] = { 350, 350, 300, 200, 230, 250, 350, 350, 200, 230, 240, 250}; +SECT_VEH_CAL_4 const tS16 c_assSTART_INCAR_STEP2_TO_3_Mpv[12] = { 300, 300, 250, 250, 250, 280, 220, 220, 220, 220, 250, 270}; +SECT_VEH_CAL_4 const tU08 c_aucSTART_3WAY_OPEN_Mpv[12] = { 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1}; +SECT_VEH_CAL_4 const tU08 c_aucSTART_2WAY_OPEN_Mpv[12] = { 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1}; +SECT_VEH_CAL_4 const tU08 c_aucSTART_TXV_F_Mpv[12] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}; +SECT_VEH_CAL_4 const tU08 c_aucSTART_TXV_R_Mpv[12] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}; +/* ------------------------------------------Start control: End*/ +SECT_VEH_CAL_4 const tS16 c_assFAILURE_AMB_TEMP_Mpv[13] = { -200, -150, -80, -50, 0, 100, 150, 200, 250, 300, 350, 400, 450}; +SECT_VEH_CAL_4 const tS16 c_assAC_PRESSURE_LOW_HYS_UP_Mpv[13] = { 6, 8, 9, 10, 11, 15, 24, 30, 37, 55, 57, 60, 65}; +SECT_VEH_CAL_4 const tS16 c_assAC_PRESSURE_LOW_HYS_DN_Mpv[13] = { 5, 7, 8, 9, 10, 12, 15, 25, 25, 30, 30, 30, 40}; +SECT_VEH_CAL_4 const tS16 c_assAC_LOW_AMB_F_Mpv[2] = { 50, 70}; +SECT_VEH_CAL_4 const tS16 c_assAC_CUT_OFF_AMB_F_Mpv[2] = { -50, -30}; +SECT_VEH_CAL_4 const tS16 c_assAC_WINTER_TXV_DEWPOINT_Mpv[2] = { 40, 30}; +SECT_VEH_CAL_4 const tS16 c_assAC_CUT_OFF_AMB_R_Mpv[2] = { -220, -210}; +SECT_VEH_CAL_4 const tS16 c_assEVA_TG_AMB_F_Mpv[13] = { 100, 100, 80, 80, 80, 60, 50, 40, 30, 30, 25, 25, 25}; +SECT_VEH_CAL_4 const tS16 c_assEVA_TG_AMB_R_Mpv[13] = { 100, 100, 80, 80, 80, 60, 50, 40, 30, 30, 25, 25, 25}; +SECT_VEH_CAL_4 const tU08 c_ucAC_EXTRA_RPM_Mpv = 15; +SECT_VEH_CAL_4 const tS16 c_assAC_EVA_LV_SHUT_OFF_Mpv[2] = { 150, 10}; +SECT_VEH_CAL_4 const tS16 c_assAC_PRESSURE_HYS_HI_ENG_ON_Mpv[3] = { 331, 265, 186}; +SECT_VEH_CAL_4 const tU16 c_usCMP_MAX_ENG_OFF_Mpv = 3000; +SECT_VEH_CAL_4 const tU08 c_ucFAN_MAX_ENG_OFF_Mpv = 15; +SECT_VEH_CAL_4 const tS16 c_ssAC_WINTER_TXV_HYST_Mpv = 15; +SECT_VEH_CAL_4 const tU08 c_aucAC_PRESSURE_HYS_HI_ENG_OFF_Mpv[2] = { 186, 155}; +SECT_VEH_CAL_4 const tU16 c_ausCMP_RPM_RESONANCE_Mpv[6] = { 1500, 1550, 2500, 2560, 7500, 7590}; +/* ------------------------------------------A/C Control Pressure : End*/ +SECT_VEH_CAL_4 const tS16 c_assPRESSURE_TO_FAN_X_Mpv[7] = { 50, 70, 90, 100, 174, 184, 240}; +SECT_VEH_CAL_4 const tU08 c_aucPRESSURE_TO_FAN_Y_Mpv[7] = { 8, 15, 30, 50, 70, 80, 100}; +/* ------------------------------------------CoolingFan: End*/ +SECT_VEH_CAL_4 const tS16 c_ssREST_BATT_Mpv = 109; +SECT_VEH_CAL_4 const tS16 c_ssRESTW_AMB_Mpv = 100; +SECT_VEH_CAL_4 const tS16 c_assRESTW_WATER_Mpv[2] = { 550, 350}; +SECT_VEH_CAL_4 const tU16 c_usRESTW_READYEXPIRETIME_Mpv = 120; +SECT_VEH_CAL_4 const tU08 c_aucRESTW_MODE_Mpv[2] = { 70, 130}; +SECT_VEH_CAL_4 const tU16 c_usRESTW_TIMEOUTTIME_Mpv = 900; +SECT_VEH_CAL_4 const tU08 c_ucRESTW_BLRSTEP_Mpv = 2; +SECT_VEH_CAL_4 const tS16 c_ssRESTS_AMB_Mpv = 100; +SECT_VEH_CAL_4 const tU08 c_uctRESTS_READYEXPIRETIME_Mpv = 120; +SECT_VEH_CAL_4 const tU08 c_aucRESTS_MODE_Mpv[2] = { 70, 130}; +SECT_VEH_CAL_4 const tU16 c_usRESTS_TIMEOUTTIME_Mpv = 600; +SECT_VEH_CAL_4 const tU08 c_ucRESTS_BLRSTEP_Mpv = 3; +/* ------------------------------------------Rest mode: End*/ +SECT_VEH_CAL_4 const tU16 c_usFRESH_AIR_PURGE_ENTRY_TIME_Mpv = 900; +SECT_VEH_CAL_4 const tU16 c_ausFRESH_AIR_PURGE_CHANGE_TIME_Mpv[7] = { 10, 10, 10, 50, 10, 10, 10}; +/* ------------------------------------------Purge Rec: End*/ +SECT_VEH_CAL_4 const tS16 c_assMAX_DEF_U_DTG_Mpv[10] = { 850, 800, 750, 600, 500, 400, 300, 300, 250, 200}; +SECT_VEH_CAL_4 const tU16 c_ausMAX_BLR_SPD_Mpv[6] = { 20, 40, 50, 80, 120, 160}; +/* ------------------------------------------MAX DEF: End*/ +SECT_VEH_CAL_4 const tU08 c_aucAQS_REC_LV_CO_Mpv[8] = { 0, 0, 0, 0, 0, 0, 0, 4}; +SECT_VEH_CAL_4 const tU08 c_aucAQS_OSA_LV_CO_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tU08 c_aucAQS_REC_LV_NOX_Mpv[8] = { 0, 0, 0, 0, 0, 0, 0, 2}; +SECT_VEH_CAL_4 const tU08 c_aucAQS_OSA_LV_NOX_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tU08 c_aucAQS_REC_LV_NH3_Mpv[8] = { 0, 0, 0, 0, 0, 0, 0, 2}; +SECT_VEH_CAL_4 const tU08 c_aucAQS_OSA_LV_NH3_Mpv[7] = { 100, 100, 100, 100, 100, 100, 100}; +SECT_VEH_CAL_4 const tU08 c_ucAQS_REC_ON_TIME_Mpv = 30; +SECT_VEH_CAL_4 const tU08 c_aucAQS_REC_ON_WAIT_Mpv[2] = { 60, 10}; +/* ------------------------------------------Aqs: End*/ +SECT_VEH_CAL_4 const tU16 c_usAUTODEMIST_LV2_BLR_PLUS_Mpv = 10; +SECT_VEH_CAL_4 const tU16 c_usAUTODEMIST_LV3_BLR_PLUS_Mpv = 30; +SECT_VEH_CAL_4 const tS16 c_assAUTODEMIST_OFFSET_AMB_TEMP_Mpv[9] = { -50, -30, -20, -10, 0, 10, 20, 30, 50}; +SECT_VEH_CAL_4 const tS16 c_assAUTODEMIST_OFFSET_VENT_TEMP_Mpv[9] = { 30, 25, 18, 11, 8, 8, 7, 5, 5}; +SECT_VEH_CAL_4 const tS16 c_assAUTODEMIST_STEP_UP_Mpv[4] = { 50, 30, 20, -10}; +SECT_VEH_CAL_4 const tS16 c_assAUTODEMIST_STEP_DN_Mpv[4] = { 55, 35, 25, 0}; +SECT_VEH_CAL_4 const tS16 c_assAUTODEMIST_WINTER_Mpv[2] = { -10, -5}; +/* ------------------------------------------Auto Demist: End*/ +SECT_VEH_CAL_4 const tS16 c_ssAUTODEMIST_ELEC_AMB_ENTRY_Mpv = -120; +SECT_VEH_CAL_4 const tS16 c_assAUTODEMIST_ELEC_WINDSHELD_TEMP_Mpv[2] = { -100, -60}; +/* ------------------------------------------Electric AutoDemist: End*/ +SECT_VEH_CAL_4 const tS16 c_ssAMBFILT_WATER_Mpv = 500; +SECT_VEH_CAL_4 const tU08 c_aucAMBFILT_H_CNT_Mpv[2] = { 200, 200}; +SECT_VEH_CAL_4 const tS16 c_ssAMB_FAILSAFE_Mpv = 230; +SECT_VEH_CAL_4 const tS16 c_ssAMBKEEP_KAT_Mpv = 200; +SECT_VEH_CAL_4 const tS16 c_ssAMBKEEP_KAT_PLUS_Mpv = 350; +SECT_VEH_CAL_4 const tS16 c_ssAMBKEEP_WATER_Mpv = 500; +SECT_VEH_CAL_4 const tU08 c_aucAMBRATE_RISING_Mpv[6] = { 30, 30, 30, 30, 30, 30}; +SECT_VEH_CAL_4 const tU08 c_aucAMBRATE_FALLING_Mpv[6] = { 30, 30, 30, 30, 30, 30}; +SECT_VEH_CAL_4 const tU08 c_aucAMBRATE_RISING_DIFF_Mpv[8] = { 120, 120, 120, 120, 155, 155, 155, 50}; +SECT_VEH_CAL_4 const tU08 c_aucAMBRATE_FALLING_DIFF_Mpv[8] = { 120, 120, 120, 255, 255, 255, 155, 50}; +/* ------------------------------------------Ambient: End*/ +SECT_VEH_CAL_4 const tU16 c_ausINCARRATE_RISING_F_Mpv[6] = { 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_4 const tU16 c_ausINCARRATE_FALLING_F_Mpv[6] = { 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_4 const tU16 c_ausINCARRATE_RISING_DIFF_F_Mpv[8] = { 100, 100, 100, 300, 300, 300, 20, 5}; +SECT_VEH_CAL_4 const tU16 c_ausINCARRATE_FALLING_DIFF_F_Mpv[8] = { 100, 100, 100, 300, 300, 300, 20, 5}; +SECT_VEH_CAL_4 const tU16 c_ausINCARRATE_RISING_R_Mpv[6] = { 50, 50, 50, 50, 50, 50}; +SECT_VEH_CAL_4 const tU16 c_ausINCARRATE_FALLING_R_Mpv[6] = { 20, 20, 20, 20, 20, 20}; +SECT_VEH_CAL_4 const tU16 c_ausINCARRATE_RISING_DIFF_R_Mpv[8] = { 100, 100, 100, 300, 300, 300, 20, 5}; +SECT_VEH_CAL_4 const tU16 c_ausINCARRATE_FALLING_DIFF_R_Mpv[8] = { 100, 100, 100, 300, 300, 300, 20, 5}; +/* ------------------------------------------Incar: End*/ +SECT_VEH_CAL_4 const tU16 c_ausSUNRATE_RISING_Mpv[6] = { 2, 2, 2, 2, 2, 2}; +SECT_VEH_CAL_4 const tU16 c_ausSUNRATE_FALLING_Mpv[6] = { 2, 2, 2, 2, 2, 2}; +/* ------------------------------------------Sun: End*/ +SECT_VEH_CAL_4 const tU16 c_ausAMB_LV_CHANGE_UNIT_Mpv[6] = { 1, 1, 1, 10, 10, 3}; +SECT_VEH_CAL_4 const tU08 c_aucAMB_LV_CHANGE_SEC_Mpv[6] = { 1, 1, 1, 1, 1, 1}; +/* ------------------------------------------Level Chage: End*/ +SECT_VEH_CAL_4 const tS16 c_ssTHREEWAY_WATER_Mpv = 40; +SECT_VEH_CAL_4 const tS16 c_assTHREEWAY_DUCT_TGT_R_Mpv[2] = { 60, 50}; +SECT_VEH_CAL_4 const tU08 c_aucTHEREEWAY_EXPIRING_Mpv[2] = { 60, 5}; +/* ------------------------------------------Three way: End*/ +SECT_VEH_CAL_4 const tS16 c_assTWOWAY_REAR_DUCTTGT_R_Mpv[2] = { 60, 50}; +SECT_VEH_CAL_4 const tU08 c_aucTWOWAY_EXPIRING_Mpv[2] = { 60, 5}; +/* ------------------------------------------two-way: End*/ +SECT_VEH_CAL_4 const tU08 c_aucACT_HOM_SPD_FL_CH0_Mpv[9] = { 3, 3, 3, 3, 3, 3, 3, 3, 3}; +SECT_VEH_CAL_4 const tU08 c_aucACT_HOM_SPD_FR_CH1_Mpv[6] = { 3, 3, 3, 3, 3, 3}; +SECT_VEH_CAL_4 const tU08 c_aucACT_HOM_SPD_R_CH2_Mpv[9] = { 3, 3, 3, 3, 3, 3, 3, 3, 3}; +SECT_VEH_CAL_4 const tU08 c_aucACT_HOM_SPD_R_EX_CH2_Mpv[4] = { 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tU08 c_aucACT_MOV_SPD_FL_CH0_Mpv[9] = { 3, 3, 3, 3, 3, 3, 3, 3, 3}; +SECT_VEH_CAL_4 const tU08 c_aucACT_MOV_SPD_FR_CH1_Mpv[6] = { 3, 3, 3, 3, 3, 3}; +SECT_VEH_CAL_4 const tU08 c_aucACT_MOV_SPD_R_CH2_Mpv[9] = { 3, 3, 3, 3, 3, 3, 3, 3, 3}; +SECT_VEH_CAL_4 const tU08 c_aucACT_MOV_SPD_R_EX_CH2_Mpv[4] = { 0, 0, 0, 0}; +/* ------------------------------------------Actuator Homing: End*/ +SECT_VEH_CAL_4 const tS16 c_assHI_MODE_ENG_TMEP_Mpv[6] = { 35, 45, 60, 80, 100, 120}; +SECT_VEH_CAL_4 const tU08 c_aucHI_MODE_BLR_STEP_STS_Mpv[6] = { 2, 3, 4, 5, 100, 100}; +/* ------------------------------------------Hi Mode: End*/ +SECT_VEH_CAL_4 const tU16 c_ausMinusAF_GlassPos_L_Mpv[13] = { 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}; +SECT_VEH_CAL_4 const tU16 c_ausMinusAF_GlassPos_R_Mpv[13] = { 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10}; +/* ------------------------------------------GlassPosition: End*/ +SECT_VEH_CAL_4 const tS16 c_assFoot2_Lv3_Amb_Mpv[6] = { -150, -100, -50, 0, 50, 100}; +SECT_VEH_CAL_4 const tS16 c_assFoot2_Lv4_Amb_Mpv[6] = { -150, -100, -50, 0, 50, 100}; +SECT_VEH_CAL_4 const tS16 c_assFoot2_Lv5_Amb_Mpv[6] = { -150, -100, -50, 0, 50, 100}; +SECT_VEH_CAL_4 const tS16 c_assFoot2_Lv3_DuctTgt_Plus_Mpv[6] = { 500, 500, 450, 400, 350, 300}; +SECT_VEH_CAL_4 const tS16 c_assFoot2_Lv4_DuctTgt_Plus_Mpv[6] = { 500, 500, 450, 400, 350, 300}; +SECT_VEH_CAL_4 const tS16 c_assFoot2_Lv5_DuctTgt_Plus_Mpv[6] = { 500, 500, 450, 400, 350, 300}; +SECT_VEH_CAL_4 const tU16 c_ausFoot2_Lv1_FrontBlr_X_Mpv[3] = { 250, 500, 750}; +SECT_VEH_CAL_4 const tU16 c_ausFoot2_Lv1_Foot2Act_Y_Mpv[3] = { 250, 500, 750}; +SECT_VEH_CAL_4 const tS16 c_assFoot2_Lv2_Threshold_Diff_Mpv[2] = { 50, 35}; +SECT_VEH_CAL_4 const tS16 c_assFoot2_Lv3_Threshold_Diff_Mpv[2] = { 50, 35}; +/* ------------------------------------------Foot2 Ctrl: End*/ +SECT_VEH_CAL_4 const tU16 c_ausDbF_Side_Af_Bi_Mpv[9] = { 90, 91, 92, 93, 94, 95, 96, 97, 98}; +SECT_VEH_CAL_4 const tU16 c_ausDbF_Side_Af_Bi2_Mpv[9] = { 90, 91, 92, 93, 94, 95, 96, 97, 98}; +SECT_VEH_CAL_4 const tU16 c_ausDbF_Side_Af_Vent_Mpv[9] = { 70, 70, 65, 65, 62, 60, 55, 50, 50}; +SECT_VEH_CAL_4 const tU16 c_ausDbF_Side_Bi_Bi2_Mpv[9] = { 80, 80, 80, 80, 80, 80, 80, 80, 80}; +SECT_VEH_CAL_4 const tU16 c_ausDbF_Side_Bi_Vent_Mpv[9] = { 65, 65, 65, 65, 65, 65, 65, 65, 65}; +SECT_VEH_CAL_4 const tU16 c_ausDbF_Side_Bi2_Vent_Mpv[9] = { 80, 80, 80, 80, 80, 80, 80, 80, 80}; +SECT_VEH_CAL_4 const tU16 c_ausDbF_Cen_Af_Bi_Mpv[9] = { 90, 91, 92, 93, 94, 95, 96, 97, 98}; +SECT_VEH_CAL_4 const tU16 c_ausDbF_Cen_Af_Bi2_Mpv[9] = { 90, 91, 92, 93, 94, 95, 96, 97, 98}; +SECT_VEH_CAL_4 const tU16 c_ausDbF_Cen_Af_Vent_Mpv[9] = { 70, 70, 70, 65, 62, 60, 55, 50, 50}; +SECT_VEH_CAL_4 const tU16 c_ausDbF_Cen_Bi_Bi2_Mpv[9] = { 80, 80, 80, 80, 80, 80, 80, 80, 80}; +SECT_VEH_CAL_4 const tU16 c_ausDbF_Cen_Bi_Vent_Mpv[9] = { 65, 65, 65, 65, 65, 65, 65, 65, 65}; +SECT_VEH_CAL_4 const tU16 c_ausDbF_Cen_Bi2_Vent_Mpv[9] = { 80, 80, 80, 80, 80, 80, 80, 80, 80}; +SECT_VEH_CAL_4 const tU16 c_ausDbF_Foot_Af_Bi_Mpv[9] = { 90, 91, 92, 93, 94, 95, 96, 97, 98}; +SECT_VEH_CAL_4 const tU16 c_ausDbF_Foot_Af_Bi2_Mpv[9] = { 90, 91, 92, 93, 94, 95, 96, 97, 98}; +SECT_VEH_CAL_4 const tU16 c_ausDbF_Foot_Af_Vent_Mpv[9] = { 70, 70, 70, 65, 62, 60, 55, 50, 50}; +SECT_VEH_CAL_4 const tU16 c_ausDbF_Foot_Bi_Bi2_Mpv[9] = { 80, 80, 80, 80, 80, 80, 80, 80, 80}; +SECT_VEH_CAL_4 const tU16 c_ausDbF_Foot_Bi_Vent_Mpv[9] = { 65, 65, 65, 65, 65, 65, 65, 65, 65}; +SECT_VEH_CAL_4 const tU16 c_ausDbF_Foot_Bi2_Vent_Mpv[9] = { 80, 80, 80, 80, 80, 80, 80, 80, 80}; +SECT_VEH_CAL_4 const tU16 c_ausDbF_AF_Af_Bi_Mpv[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tU16 c_ausDbF_AF_Af_Bi2_Mpv[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tU16 c_ausDbF_AF_Af_Vent_Mpv[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tU16 c_ausDbF_AF_Bi_Bi2_Mpv[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tU16 c_ausDbF_AF_Bi_Vent_Mpv[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tU16 c_ausDbF_AF_Bi2_Vent_Mpv[9] = { 0, 0, 0, 0, 0, 0, 0, 0, 0}; +SECT_VEH_CAL_4 const tU16 c_ausDbF_Pwm_Af_Bi_Mpv[9] = { 120, 120, 120, 120, 120, 120, 120, 120, 120}; +SECT_VEH_CAL_4 const tU16 c_ausDbF_Pwm_Af_Bi2_Mpv[9] = { 120, 120, 120, 120, 120, 120, 120, 120, 120}; +SECT_VEH_CAL_4 const tU16 c_ausDbF_Pwm_Af_Vent_Mpv[9] = { 120, 120, 85, 120, 120, 120, 120, 120, 120}; +SECT_VEH_CAL_4 const tU16 c_ausDbF_Pwm_Bi_Bi2_Mpv[9] = { 120, 120, 120, 120, 120, 120, 120, 120, 120}; +SECT_VEH_CAL_4 const tU16 c_ausDbF_Pwm_Bi_Vent_Mpv[9] = { 120, 120, 85, 90, 120, 120, 120, 120, 120}; +SECT_VEH_CAL_4 const tU16 c_ausDbF_Pwm_Bi2_Vent_Mpv[9] = { 105, 120, 120, 90, 120, 120, 120, 105, 90}; +/* ------------------------------------------Different blower Front: End*/ +SECT_VEH_CAL_4 const tU16 c_usAromaPwm_Min_Mpv = 200; +SECT_VEH_CAL_4 const tU16 c_usAromaPwm_Max_Mpv = 700; +/* ------------------------------------------Aroma Limit Pwm: End*/ +/*********************************************************Cal Table End*/ + +/****************************************************************************** + * LOCAL VARIABLES DECLARATIONS + *****************************************************************************/ +/****************************************************************************** + * LOCAL FUNCTIONS DECLARATIONS + *****************************************************************************/ +/****************************************************************************** + * GLOBAL FUNCTIONS + *****************************************************************************/ + +/** Doxygen: Function brief + ****************************************************************************** + * @fn Rs_Cal_4_Mpv(void) + * @brief No brief + * @remark No description + * @param[in] (All of const data in this file) + * @param[out] All of global variable in Rs_Cal_Base.c + * @return None + *****************************************************************************/ +void Rs_Cal_4_Mpv(void) +{ + M_MEMCOPY((g_aucCAL_FP_DATE), (c_aucCAL_FP_DATE_Mpv)); + M_MEMCOPY((g_aucCAL_VERSION), (c_aucCAL_VERSION_Mpv)); + g_ucCAL_VARIANT = c_ucCAL_VARIANT_Mpv; +/* ------------------------------------------Cal Version : End*/ + M_MEMCOPY((g_ausSET_TEMP_FULL), (c_ausSET_TEMP_FULL_Mpv)); + M_MEMCOPY((g_ausSET_TEMP_HALF), (c_ausSET_TEMP_HALF_Mpv)); +/* ------------------------------------------Set Temp : End*/ + M_MEMCOPY((g_assINCAR_TG_FL_LV0), (c_assINCAR_TG_FL_LV0_Mpv)); + M_MEMCOPY((g_assINCAR_TG_FR_LV0), (c_assINCAR_TG_FR_LV0_Mpv)); + M_MEMCOPY((g_assVTG_FL_LV0), (c_assVTG_FL_LV0_Mpv)); + M_MEMCOPY((g_assVTG_FR_LV0), (c_assVTG_FR_LV0_Mpv)); + M_MEMCOPY((g_assVF_MIN_LV0), (c_assVF_MIN_LV0_Mpv)); + M_MEMCOPY((g_assVF_MAX_LV0), (c_assVF_MAX_LV0_Mpv)); + M_MEMCOPY((g_assVF_INC_Y1_LV0), (c_assVF_INC_Y1_LV0_Mpv)); + M_MEMCOPY((g_assVF_INC_Y2_LV0), (c_assVF_INC_Y2_LV0_Mpv)); + M_MEMCOPY((g_assVF_INC_Y3_LV0), (c_assVF_INC_Y3_LV0_Mpv)); + M_MEMCOPY((g_assVF_INC_Y4_LV0), (c_assVF_INC_Y4_LV0_Mpv)); + M_MEMCOPY((g_assVF_INC_X1_LV0), (c_assVF_INC_X1_LV0_Mpv)); + M_MEMCOPY((g_assVF_INC_X2_LV0), (c_assVF_INC_X2_LV0_Mpv)); + M_MEMCOPY((g_assVF_INC_X3_LV0), (c_assVF_INC_X3_LV0_Mpv)); + M_MEMCOPY((g_assVF_INC_X4_LV0), (c_assVF_INC_X4_LV0_Mpv)); + M_MEMCOPY((g_assVF_AMB_Y1_LV0), (c_assVF_AMB_Y1_LV0_Mpv)); + M_MEMCOPY((g_assVF_AMB_Y2_LV0), (c_assVF_AMB_Y2_LV0_Mpv)); + M_MEMCOPY((g_assVF_AMB_X1_LV0), (c_assVF_AMB_X1_LV0_Mpv)); + M_MEMCOPY((g_assVF_AMB_X2_LV0), (c_assVF_AMB_X2_LV0_Mpv)); + M_MEMCOPY((g_assVF_SUN_Y1_LV0), (c_assVF_SUN_Y1_LV0_Mpv)); + M_MEMCOPY((g_assVF_SUN_Y2_LV0), (c_assVF_SUN_Y2_LV0_Mpv)); + M_MEMCOPY((g_assVF_SUN_X1_LV0), (c_assVF_SUN_X1_LV0_Mpv)); + M_MEMCOPY((g_assVF_SUN_X2_LV0), (c_assVF_SUN_X2_LV0_Mpv)); + M_MEMCOPY((g_assTG_FLU_LV0), (c_assTG_FLU_LV0_Mpv)); + M_MEMCOPY((g_assTG_FRU_LV0), (c_assTG_FRU_LV0_Mpv)); + M_MEMCOPY((g_assDTG_FU_MIN_LV0), (c_assDTG_FU_MIN_LV0_Mpv)); + M_MEMCOPY((g_assDTG_FU_MAX_LV0), (c_assDTG_FU_MAX_LV0_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_Y1_LV0), (c_assDTG_FU_INC_Y1_LV0_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_Y2_LV0), (c_assDTG_FU_INC_Y2_LV0_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_Y3_LV0), (c_assDTG_FU_INC_Y3_LV0_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_Y4_LV0), (c_assDTG_FU_INC_Y4_LV0_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_X1_LV0), (c_assDTG_FU_INC_X1_LV0_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_X2_LV0), (c_assDTG_FU_INC_X2_LV0_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_X3_LV0), (c_assDTG_FU_INC_X3_LV0_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_X4_LV0), (c_assDTG_FU_INC_X4_LV0_Mpv)); + M_MEMCOPY((g_assDTG_FU_AMB_Y1_LV0), (c_assDTG_FU_AMB_Y1_LV0_Mpv)); + M_MEMCOPY((g_assDTG_FU_AMB_Y2_LV0), (c_assDTG_FU_AMB_Y2_LV0_Mpv)); + M_MEMCOPY((g_assDTG_FU_AMB_X1_LV0), (c_assDTG_FU_AMB_X1_LV0_Mpv)); + M_MEMCOPY((g_assDTG_FU_AMB_X2_LV0), (c_assDTG_FU_AMB_X2_LV0_Mpv)); + M_MEMCOPY((g_assDTG_FU_SUN_Y1_LV0), (c_assDTG_FU_SUN_Y1_LV0_Mpv)); + M_MEMCOPY((g_assDTG_FU_SUN_Y2_LV0), (c_assDTG_FU_SUN_Y2_LV0_Mpv)); + M_MEMCOPY((g_assDTG_FU_SUN_X1_LV0), (c_assDTG_FU_SUN_X1_LV0_Mpv)); + M_MEMCOPY((g_assDTG_FU_SUN_X2_LV0), (c_assDTG_FU_SUN_X2_LV0_Mpv)); + M_MEMCOPY((g_assTG_FLL_LV0), (c_assTG_FLL_LV0_Mpv)); + M_MEMCOPY((g_assTG_FRL_LV0), (c_assTG_FRL_LV0_Mpv)); + M_MEMCOPY((g_assDTG_FL_MIN_LV0), (c_assDTG_FL_MIN_LV0_Mpv)); + M_MEMCOPY((g_assDTG_FL_MAX_LV0), (c_assDTG_FL_MAX_LV0_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_Y1_LV0), (c_assDTG_FL_INC_Y1_LV0_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_Y2_LV0), (c_assDTG_FL_INC_Y2_LV0_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_Y3_LV0), (c_assDTG_FL_INC_Y3_LV0_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_Y4_LV0), (c_assDTG_FL_INC_Y4_LV0_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_X1_LV0), (c_assDTG_FL_INC_X1_LV0_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_X2_LV0), (c_assDTG_FL_INC_X2_LV0_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_X3_LV0), (c_assDTG_FL_INC_X3_LV0_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_X4_LV0), (c_assDTG_FL_INC_X4_LV0_Mpv)); + M_MEMCOPY((g_assDTG_FL_AMB_Y1_LV0), (c_assDTG_FL_AMB_Y1_LV0_Mpv)); + M_MEMCOPY((g_assDTG_FL_AMB_Y2_LV0), (c_assDTG_FL_AMB_Y2_LV0_Mpv)); + M_MEMCOPY((g_assDTG_FL_AMB_X1_LV0), (c_assDTG_FL_AMB_X1_LV0_Mpv)); + M_MEMCOPY((g_assDTG_FL_AMB_X2_LV0), (c_assDTG_FL_AMB_X2_LV0_Mpv)); + M_MEMCOPY((g_assDTG_FL_SUN_Y1_LV0), (c_assDTG_FL_SUN_Y1_LV0_Mpv)); + M_MEMCOPY((g_assDTG_FL_SUN_Y2_LV0), (c_assDTG_FL_SUN_Y2_LV0_Mpv)); + M_MEMCOPY((g_assDTG_FL_SUN_X1_LV0), (c_assDTG_FL_SUN_X1_LV0_Mpv)); + M_MEMCOPY((g_assDTG_FL_SUN_X2_LV0), (c_assDTG_FL_SUN_X2_LV0_Mpv)); + M_MEMCOPY((g_assINCAR_TG_RL_LV0), (c_assINCAR_TG_RL_LV0_Mpv)); + M_MEMCOPY((g_assINCAR_TG_RR_LV0), (c_assINCAR_TG_RR_LV0_Mpv)); + M_MEMCOPY((g_assVTG_RL_LV0), (c_assVTG_RL_LV0_Mpv)); + M_MEMCOPY((g_assVTG_RR_LV0), (c_assVTG_RR_LV0_Mpv)); + M_MEMCOPY((g_assVR_MIN_LV0), (c_assVR_MIN_LV0_Mpv)); + M_MEMCOPY((g_assVR_MAX_LV0), (c_assVR_MAX_LV0_Mpv)); + M_MEMCOPY((g_assVR_INC_Y1_LV0), (c_assVR_INC_Y1_LV0_Mpv)); + M_MEMCOPY((g_assVR_INC_Y2_LV0), (c_assVR_INC_Y2_LV0_Mpv)); + M_MEMCOPY((g_assVR_INC_Y3_LV0), (c_assVR_INC_Y3_LV0_Mpv)); + M_MEMCOPY((g_assVR_INC_Y4_LV0), (c_assVR_INC_Y4_LV0_Mpv)); + M_MEMCOPY((g_assVR_INC_X1_LV0), (c_assVR_INC_X1_LV0_Mpv)); + M_MEMCOPY((g_assVR_INC_X2_LV0), (c_assVR_INC_X2_LV0_Mpv)); + M_MEMCOPY((g_assVR_INC_X3_LV0), (c_assVR_INC_X3_LV0_Mpv)); + M_MEMCOPY((g_assVR_INC_X4_LV0), (c_assVR_INC_X4_LV0_Mpv)); + M_MEMCOPY((g_assVR_AMB_Y1_LV0), (c_assVR_AMB_Y1_LV0_Mpv)); + M_MEMCOPY((g_assVR_AMB_Y2_LV0), (c_assVR_AMB_Y2_LV0_Mpv)); + M_MEMCOPY((g_assVR_AMB_X1_LV0), (c_assVR_AMB_X1_LV0_Mpv)); + M_MEMCOPY((g_assVR_AMB_X2_LV0), (c_assVR_AMB_X2_LV0_Mpv)); + M_MEMCOPY((g_assVR_SUN_Y1_LV0), (c_assVR_SUN_Y1_LV0_Mpv)); + M_MEMCOPY((g_assVR_SUN_Y2_LV0), (c_assVR_SUN_Y2_LV0_Mpv)); + M_MEMCOPY((g_assVR_SUN_X1_LV0), (c_assVR_SUN_X1_LV0_Mpv)); + M_MEMCOPY((g_assVR_SUN_X2_LV0), (c_assVR_SUN_X2_LV0_Mpv)); + M_MEMCOPY((g_assTG_RL_LV0), (c_assTG_RL_LV0_Mpv)); + M_MEMCOPY((g_assTG_RR_LV0), (c_assTG_RR_LV0_Mpv)); + M_MEMCOPY((g_assDTG_R_MIN_LV0), (c_assDTG_R_MIN_LV0_Mpv)); + M_MEMCOPY((g_assDTG_R_MAX_LV0), (c_assDTG_R_MAX_LV0_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_Y1_LV0), (c_assDTG_R_INC_Y1_LV0_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_Y2_LV0), (c_assDTG_R_INC_Y2_LV0_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_Y3_LV0), (c_assDTG_R_INC_Y3_LV0_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_Y4_LV0), (c_assDTG_R_INC_Y4_LV0_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_X1_LV0), (c_assDTG_R_INC_X1_LV0_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_X2_LV0), (c_assDTG_R_INC_X2_LV0_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_X3_LV0), (c_assDTG_R_INC_X3_LV0_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_X4_LV0), (c_assDTG_R_INC_X4_LV0_Mpv)); + M_MEMCOPY((g_assDTG_R_AMB_Y1_LV0), (c_assDTG_R_AMB_Y1_LV0_Mpv)); + M_MEMCOPY((g_assDTG_R_AMB_Y2_LV0), (c_assDTG_R_AMB_Y2_LV0_Mpv)); + M_MEMCOPY((g_assDTG_R_AMB_X1_LV0), (c_assDTG_R_AMB_X1_LV0_Mpv)); + M_MEMCOPY((g_assDTG_R_AMB_X2_LV0), (c_assDTG_R_AMB_X2_LV0_Mpv)); + M_MEMCOPY((g_assDTG_R_SUN_Y1_LV0), (c_assDTG_R_SUN_Y1_LV0_Mpv)); + M_MEMCOPY((g_assDTG_R_SUN_Y2_LV0), (c_assDTG_R_SUN_Y2_LV0_Mpv)); + M_MEMCOPY((g_assDTG_R_SUN_X1_LV0), (c_assDTG_R_SUN_X1_LV0_Mpv)); + M_MEMCOPY((g_assDTG_R_SUN_X2_LV0), (c_assDTG_R_SUN_X2_LV0_Mpv)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FR_LV0), (c_assCORRECT_DUCT_TIME_FR_LV0_Mpv)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FL_LV0), (c_assCORRECT_DUCT_TIME_FL_LV0_Mpv)); + M_MEMCOPY((g_assCORRECT_DUCT_RATE_LV0), (c_assCORRECT_DUCT_RATE_LV0_Mpv)); + M_MEMCOPY((g_assCORRECT_DUCT_MAX_LV0), (c_assCORRECT_DUCT_MAX_LV0_Mpv)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FR_LV0), (c_assCORRECT_AF_TIME_FR_LV0_Mpv)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FL_LV0), (c_assCORRECT_AF_TIME_FL_LV0_Mpv)); + M_MEMCOPY((g_assCORRECT_AF_RATE_LV0), (c_assCORRECT_AF_RATE_LV0_Mpv)); + M_MEMCOPY((g_assCORRECT_AF_MAX_LV0), (c_assCORRECT_AF_MAX_LV0_Mpv)); +/* ------------------------------------------Lv0 : End*/ + M_MEMCOPY((g_assINCAR_TG_FL_LV1), (c_assINCAR_TG_FL_LV1_Mpv)); + M_MEMCOPY((g_assINCAR_TG_FR_LV1), (c_assINCAR_TG_FR_LV1_Mpv)); + M_MEMCOPY((g_assVTG_FL_LV1), (c_assVTG_FL_LV1_Mpv)); + M_MEMCOPY((g_assVTG_FR_LV1), (c_assVTG_FR_LV1_Mpv)); + M_MEMCOPY((g_assVF_MIN_LV1), (c_assVF_MIN_LV1_Mpv)); + M_MEMCOPY((g_assVF_MAX_LV1), (c_assVF_MAX_LV1_Mpv)); + M_MEMCOPY((g_assVF_INC_Y1_LV1), (c_assVF_INC_Y1_LV1_Mpv)); + M_MEMCOPY((g_assVF_INC_Y2_LV1), (c_assVF_INC_Y2_LV1_Mpv)); + M_MEMCOPY((g_assVF_INC_Y3_LV1), (c_assVF_INC_Y3_LV1_Mpv)); + M_MEMCOPY((g_assVF_INC_Y4_LV1), (c_assVF_INC_Y4_LV1_Mpv)); + M_MEMCOPY((g_assVF_INC_X1_LV1), (c_assVF_INC_X1_LV1_Mpv)); + M_MEMCOPY((g_assVF_INC_X2_LV1), (c_assVF_INC_X2_LV1_Mpv)); + M_MEMCOPY((g_assVF_INC_X3_LV1), (c_assVF_INC_X3_LV1_Mpv)); + M_MEMCOPY((g_assVF_INC_X4_LV1), (c_assVF_INC_X4_LV1_Mpv)); + M_MEMCOPY((g_assVF_AMB_Y1_LV1), (c_assVF_AMB_Y1_LV1_Mpv)); + M_MEMCOPY((g_assVF_AMB_Y2_LV1), (c_assVF_AMB_Y2_LV1_Mpv)); + M_MEMCOPY((g_assVF_AMB_X1_LV1), (c_assVF_AMB_X1_LV1_Mpv)); + M_MEMCOPY((g_assVF_AMB_X2_LV1), (c_assVF_AMB_X2_LV1_Mpv)); + M_MEMCOPY((g_assVF_SUN_Y1_LV1), (c_assVF_SUN_Y1_LV1_Mpv)); + M_MEMCOPY((g_assVF_SUN_Y2_LV1), (c_assVF_SUN_Y2_LV1_Mpv)); + M_MEMCOPY((g_assVF_SUN_X1_LV1), (c_assVF_SUN_X1_LV1_Mpv)); + M_MEMCOPY((g_assVF_SUN_X2_LV1), (c_assVF_SUN_X2_LV1_Mpv)); + M_MEMCOPY((g_assTG_FLU_LV1), (c_assTG_FLU_LV1_Mpv)); + M_MEMCOPY((g_assTG_FRU_LV1), (c_assTG_FRU_LV1_Mpv)); + M_MEMCOPY((g_assDTG_FU_MIN_LV1), (c_assDTG_FU_MIN_LV1_Mpv)); + M_MEMCOPY((g_assDTG_FU_MAX_LV1), (c_assDTG_FU_MAX_LV1_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_Y1_LV1), (c_assDTG_FU_INC_Y1_LV1_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_Y2_LV1), (c_assDTG_FU_INC_Y2_LV1_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_Y3_LV1), (c_assDTG_FU_INC_Y3_LV1_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_Y4_LV1), (c_assDTG_FU_INC_Y4_LV1_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_X1_LV1), (c_assDTG_FU_INC_X1_LV1_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_X2_LV1), (c_assDTG_FU_INC_X2_LV1_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_X3_LV1), (c_assDTG_FU_INC_X3_LV1_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_X4_LV1), (c_assDTG_FU_INC_X4_LV1_Mpv)); + M_MEMCOPY((g_assDTG_FU_AMB_Y1_LV1), (c_assDTG_FU_AMB_Y1_LV1_Mpv)); + M_MEMCOPY((g_assDTG_FU_AMB_Y2_LV1), (c_assDTG_FU_AMB_Y2_LV1_Mpv)); + M_MEMCOPY((g_assDTG_FU_AMB_X1_LV1), (c_assDTG_FU_AMB_X1_LV1_Mpv)); + M_MEMCOPY((g_assDTG_FU_AMB_X2_LV1), (c_assDTG_FU_AMB_X2_LV1_Mpv)); + M_MEMCOPY((g_assDTG_FU_SUN_Y1_LV1), (c_assDTG_FU_SUN_Y1_LV1_Mpv)); + M_MEMCOPY((g_assDTG_FU_SUN_Y2_LV1), (c_assDTG_FU_SUN_Y2_LV1_Mpv)); + M_MEMCOPY((g_assDTG_FU_SUN_X1_LV1), (c_assDTG_FU_SUN_X1_LV1_Mpv)); + M_MEMCOPY((g_assDTG_FU_SUN_X2_LV1), (c_assDTG_FU_SUN_X2_LV1_Mpv)); + M_MEMCOPY((g_assTG_FLL_LV1), (c_assTG_FLL_LV1_Mpv)); + M_MEMCOPY((g_assTG_FRL_LV1), (c_assTG_FRL_LV1_Mpv)); + M_MEMCOPY((g_assDTG_FL_MIN_LV1), (c_assDTG_FL_MIN_LV1_Mpv)); + M_MEMCOPY((g_assDTG_FL_MAX_LV1), (c_assDTG_FL_MAX_LV1_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_Y1_LV1), (c_assDTG_FL_INC_Y1_LV1_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_Y2_LV1), (c_assDTG_FL_INC_Y2_LV1_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_Y3_LV1), (c_assDTG_FL_INC_Y3_LV1_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_Y4_LV1), (c_assDTG_FL_INC_Y4_LV1_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_X1_LV1), (c_assDTG_FL_INC_X1_LV1_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_X2_LV1), (c_assDTG_FL_INC_X2_LV1_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_X3_LV1), (c_assDTG_FL_INC_X3_LV1_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_X4_LV1), (c_assDTG_FL_INC_X4_LV1_Mpv)); + M_MEMCOPY((g_assDTG_FL_AMB_Y1_LV1), (c_assDTG_FL_AMB_Y1_LV1_Mpv)); + M_MEMCOPY((g_assDTG_FL_AMB_Y2_LV1), (c_assDTG_FL_AMB_Y2_LV1_Mpv)); + M_MEMCOPY((g_assDTG_FL_AMB_X1_LV1), (c_assDTG_FL_AMB_X1_LV1_Mpv)); + M_MEMCOPY((g_assDTG_FL_AMB_X2_LV1), (c_assDTG_FL_AMB_X2_LV1_Mpv)); + M_MEMCOPY((g_assDTG_FL_SUN_Y1_LV1), (c_assDTG_FL_SUN_Y1_LV1_Mpv)); + M_MEMCOPY((g_assDTG_FL_SUN_Y2_LV1), (c_assDTG_FL_SUN_Y2_LV1_Mpv)); + M_MEMCOPY((g_assDTG_FL_SUN_X1_LV1), (c_assDTG_FL_SUN_X1_LV1_Mpv)); + M_MEMCOPY((g_assDTG_FL_SUN_X2_LV1), (c_assDTG_FL_SUN_X2_LV1_Mpv)); + M_MEMCOPY((g_assINCAR_TG_RL_LV1), (c_assINCAR_TG_RL_LV1_Mpv)); + M_MEMCOPY((g_assINCAR_TG_RR_LV1), (c_assINCAR_TG_RR_LV1_Mpv)); + M_MEMCOPY((g_assVTG_RL_LV1), (c_assVTG_RL_LV1_Mpv)); + M_MEMCOPY((g_assVTG_RR_LV1), (c_assVTG_RR_LV1_Mpv)); + M_MEMCOPY((g_assVR_MIN_LV1), (c_assVR_MIN_LV1_Mpv)); + M_MEMCOPY((g_assVR_MAX_LV1), (c_assVR_MAX_LV1_Mpv)); + M_MEMCOPY((g_assVR_INC_Y1_LV1), (c_assVR_INC_Y1_LV1_Mpv)); + M_MEMCOPY((g_assVR_INC_Y2_LV1), (c_assVR_INC_Y2_LV1_Mpv)); + M_MEMCOPY((g_assVR_INC_Y3_LV1), (c_assVR_INC_Y3_LV1_Mpv)); + M_MEMCOPY((g_assVR_INC_Y4_LV1), (c_assVR_INC_Y4_LV1_Mpv)); + M_MEMCOPY((g_assVR_INC_X1_LV1), (c_assVR_INC_X1_LV1_Mpv)); + M_MEMCOPY((g_assVR_INC_X2_LV1), (c_assVR_INC_X2_LV1_Mpv)); + M_MEMCOPY((g_assVR_INC_X3_LV1), (c_assVR_INC_X3_LV1_Mpv)); + M_MEMCOPY((g_assVR_INC_X4_LV1), (c_assVR_INC_X4_LV1_Mpv)); + M_MEMCOPY((g_assVR_AMB_Y1_LV1), (c_assVR_AMB_Y1_LV1_Mpv)); + M_MEMCOPY((g_assVR_AMB_Y2_LV1), (c_assVR_AMB_Y2_LV1_Mpv)); + M_MEMCOPY((g_assVR_AMB_X1_LV1), (c_assVR_AMB_X1_LV1_Mpv)); + M_MEMCOPY((g_assVR_AMB_X2_LV1), (c_assVR_AMB_X2_LV1_Mpv)); + M_MEMCOPY((g_assVR_SUN_Y1_LV1), (c_assVR_SUN_Y1_LV1_Mpv)); + M_MEMCOPY((g_assVR_SUN_Y2_LV1), (c_assVR_SUN_Y2_LV1_Mpv)); + M_MEMCOPY((g_assVR_SUN_X1_LV1), (c_assVR_SUN_X1_LV1_Mpv)); + M_MEMCOPY((g_assVR_SUN_X2_LV1), (c_assVR_SUN_X2_LV1_Mpv)); + M_MEMCOPY((g_assTG_RL_LV1), (c_assTG_RL_LV1_Mpv)); + M_MEMCOPY((g_assTG_RR_LV1), (c_assTG_RR_LV1_Mpv)); + M_MEMCOPY((g_assDTG_R_MIN_LV1), (c_assDTG_R_MIN_LV1_Mpv)); + M_MEMCOPY((g_assDTG_R_MAX_LV1), (c_assDTG_R_MAX_LV1_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_Y1_LV1), (c_assDTG_R_INC_Y1_LV1_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_Y2_LV1), (c_assDTG_R_INC_Y2_LV1_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_Y3_LV1), (c_assDTG_R_INC_Y3_LV1_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_Y4_LV1), (c_assDTG_R_INC_Y4_LV1_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_X1_LV1), (c_assDTG_R_INC_X1_LV1_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_X2_LV1), (c_assDTG_R_INC_X2_LV1_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_X3_LV1), (c_assDTG_R_INC_X3_LV1_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_X4_LV1), (c_assDTG_R_INC_X4_LV1_Mpv)); + M_MEMCOPY((g_assDTG_R_AMB_Y1_LV1), (c_assDTG_R_AMB_Y1_LV1_Mpv)); + M_MEMCOPY((g_assDTG_R_AMB_Y2_LV1), (c_assDTG_R_AMB_Y2_LV1_Mpv)); + M_MEMCOPY((g_assDTG_R_AMB_X1_LV1), (c_assDTG_R_AMB_X1_LV1_Mpv)); + M_MEMCOPY((g_assDTG_R_AMB_X2_LV1), (c_assDTG_R_AMB_X2_LV1_Mpv)); + M_MEMCOPY((g_assDTG_R_SUN_Y1_LV1), (c_assDTG_R_SUN_Y1_LV1_Mpv)); + M_MEMCOPY((g_assDTG_R_SUN_Y2_LV1), (c_assDTG_R_SUN_Y2_LV1_Mpv)); + M_MEMCOPY((g_assDTG_R_SUN_X1_LV1), (c_assDTG_R_SUN_X1_LV1_Mpv)); + M_MEMCOPY((g_assDTG_R_SUN_X2_LV1), (c_assDTG_R_SUN_X2_LV1_Mpv)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FR_LV1), (c_assCORRECT_DUCT_TIME_FR_LV1_Mpv)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FL_LV1), (c_assCORRECT_DUCT_TIME_FL_LV1_Mpv)); + M_MEMCOPY((g_assCORRECT_DUCT_RATE_LV1), (c_assCORRECT_DUCT_RATE_LV1_Mpv)); + M_MEMCOPY((g_assCORRECT_DUCT_MAX_LV1), (c_assCORRECT_DUCT_MAX_LV1_Mpv)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FR_LV1), (c_assCORRECT_AF_TIME_FR_LV1_Mpv)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FL_LV1), (c_assCORRECT_AF_TIME_FL_LV1_Mpv)); + M_MEMCOPY((g_assCORRECT_AF_RATE_LV1), (c_assCORRECT_AF_RATE_LV1_Mpv)); + M_MEMCOPY((g_assCORRECT_AF_MAX_LV1), (c_assCORRECT_AF_MAX_LV1_Mpv)); +/* ------------------------------------------Lv1 : End*/ + M_MEMCOPY((g_assINCAR_TG_FL_LV2), (c_assINCAR_TG_FL_LV2_Mpv)); + M_MEMCOPY((g_assINCAR_TG_FR_LV2), (c_assINCAR_TG_FR_LV2_Mpv)); + M_MEMCOPY((g_assVTG_FL_LV2), (c_assVTG_FL_LV2_Mpv)); + M_MEMCOPY((g_assVTG_FR_LV2), (c_assVTG_FR_LV2_Mpv)); + M_MEMCOPY((g_assVF_MIN_LV2), (c_assVF_MIN_LV2_Mpv)); + M_MEMCOPY((g_assVF_MAX_LV2), (c_assVF_MAX_LV2_Mpv)); + M_MEMCOPY((g_assVF_INC_Y1_LV2), (c_assVF_INC_Y1_LV2_Mpv)); + M_MEMCOPY((g_assVF_INC_Y2_LV2), (c_assVF_INC_Y2_LV2_Mpv)); + M_MEMCOPY((g_assVF_INC_Y3_LV2), (c_assVF_INC_Y3_LV2_Mpv)); + M_MEMCOPY((g_assVF_INC_Y4_LV2), (c_assVF_INC_Y4_LV2_Mpv)); + M_MEMCOPY((g_assVF_INC_X1_LV2), (c_assVF_INC_X1_LV2_Mpv)); + M_MEMCOPY((g_assVF_INC_X2_LV2), (c_assVF_INC_X2_LV2_Mpv)); + M_MEMCOPY((g_assVF_INC_X3_LV2), (c_assVF_INC_X3_LV2_Mpv)); + M_MEMCOPY((g_assVF_INC_X4_LV2), (c_assVF_INC_X4_LV2_Mpv)); + M_MEMCOPY((g_assVF_AMB_Y1_LV2), (c_assVF_AMB_Y1_LV2_Mpv)); + M_MEMCOPY((g_assVF_AMB_Y2_LV2), (c_assVF_AMB_Y2_LV2_Mpv)); + M_MEMCOPY((g_assVF_AMB_X1_LV2), (c_assVF_AMB_X1_LV2_Mpv)); + M_MEMCOPY((g_assVF_AMB_X2_LV2), (c_assVF_AMB_X2_LV2_Mpv)); + M_MEMCOPY((g_assVF_SUN_Y1_LV2), (c_assVF_SUN_Y1_LV2_Mpv)); + M_MEMCOPY((g_assVF_SUN_Y2_LV2), (c_assVF_SUN_Y2_LV2_Mpv)); + M_MEMCOPY((g_assVF_SUN_X1_LV2), (c_assVF_SUN_X1_LV2_Mpv)); + M_MEMCOPY((g_assVF_SUN_X2_LV2), (c_assVF_SUN_X2_LV2_Mpv)); + M_MEMCOPY((g_assTG_FLU_LV2), (c_assTG_FLU_LV2_Mpv)); + M_MEMCOPY((g_assTG_FRU_LV2), (c_assTG_FRU_LV2_Mpv)); + M_MEMCOPY((g_assDTG_FU_MIN_LV2), (c_assDTG_FU_MIN_LV2_Mpv)); + M_MEMCOPY((g_assDTG_FU_MAX_LV2), (c_assDTG_FU_MAX_LV2_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_Y1_LV2), (c_assDTG_FU_INC_Y1_LV2_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_Y2_LV2), (c_assDTG_FU_INC_Y2_LV2_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_Y3_LV2), (c_assDTG_FU_INC_Y3_LV2_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_Y4_LV2), (c_assDTG_FU_INC_Y4_LV2_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_X1_LV2), (c_assDTG_FU_INC_X1_LV2_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_X2_LV2), (c_assDTG_FU_INC_X2_LV2_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_X3_LV2), (c_assDTG_FU_INC_X3_LV2_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_X4_LV2), (c_assDTG_FU_INC_X4_LV2_Mpv)); + M_MEMCOPY((g_assDTG_FU_AMB_Y1_LV2), (c_assDTG_FU_AMB_Y1_LV2_Mpv)); + M_MEMCOPY((g_assDTG_FU_AMB_Y2_LV2), (c_assDTG_FU_AMB_Y2_LV2_Mpv)); + M_MEMCOPY((g_assDTG_FU_AMB_X1_LV2), (c_assDTG_FU_AMB_X1_LV2_Mpv)); + M_MEMCOPY((g_assDTG_FU_AMB_X2_LV2), (c_assDTG_FU_AMB_X2_LV2_Mpv)); + M_MEMCOPY((g_assDTG_FU_SUN_Y1_LV2), (c_assDTG_FU_SUN_Y1_LV2_Mpv)); + M_MEMCOPY((g_assDTG_FU_SUN_Y2_LV2), (c_assDTG_FU_SUN_Y2_LV2_Mpv)); + M_MEMCOPY((g_assDTG_FU_SUN_X1_LV2), (c_assDTG_FU_SUN_X1_LV2_Mpv)); + M_MEMCOPY((g_assDTG_FU_SUN_X2_LV2), (c_assDTG_FU_SUN_X2_LV2_Mpv)); + M_MEMCOPY((g_assTG_FLL_LV2), (c_assTG_FLL_LV2_Mpv)); + M_MEMCOPY((g_assTG_FRL_LV2), (c_assTG_FRL_LV2_Mpv)); + M_MEMCOPY((g_assDTG_FL_MIN_LV2), (c_assDTG_FL_MIN_LV2_Mpv)); + M_MEMCOPY((g_assDTG_FL_MAX_LV2), (c_assDTG_FL_MAX_LV2_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_Y1_LV2), (c_assDTG_FL_INC_Y1_LV2_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_Y2_LV2), (c_assDTG_FL_INC_Y2_LV2_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_Y3_LV2), (c_assDTG_FL_INC_Y3_LV2_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_Y4_LV2), (c_assDTG_FL_INC_Y4_LV2_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_X1_LV2), (c_assDTG_FL_INC_X1_LV2_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_X2_LV2), (c_assDTG_FL_INC_X2_LV2_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_X3_LV2), (c_assDTG_FL_INC_X3_LV2_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_X4_LV2), (c_assDTG_FL_INC_X4_LV2_Mpv)); + M_MEMCOPY((g_assDTG_FL_AMB_Y1_LV2), (c_assDTG_FL_AMB_Y1_LV2_Mpv)); + M_MEMCOPY((g_assDTG_FL_AMB_Y2_LV2), (c_assDTG_FL_AMB_Y2_LV2_Mpv)); + M_MEMCOPY((g_assDTG_FL_AMB_X1_LV2), (c_assDTG_FL_AMB_X1_LV2_Mpv)); + M_MEMCOPY((g_assDTG_FL_AMB_X2_LV2), (c_assDTG_FL_AMB_X2_LV2_Mpv)); + M_MEMCOPY((g_assDTG_FL_SUN_Y1_LV2), (c_assDTG_FL_SUN_Y1_LV2_Mpv)); + M_MEMCOPY((g_assDTG_FL_SUN_Y2_LV2), (c_assDTG_FL_SUN_Y2_LV2_Mpv)); + M_MEMCOPY((g_assDTG_FL_SUN_X1_LV2), (c_assDTG_FL_SUN_X1_LV2_Mpv)); + M_MEMCOPY((g_assDTG_FL_SUN_X2_LV2), (c_assDTG_FL_SUN_X2_LV2_Mpv)); + M_MEMCOPY((g_assINCAR_TG_RL_LV2), (c_assINCAR_TG_RL_LV2_Mpv)); + M_MEMCOPY((g_assINCAR_TG_RR_LV2), (c_assINCAR_TG_RR_LV2_Mpv)); + M_MEMCOPY((g_assVTG_RL_LV2), (c_assVTG_RL_LV2_Mpv)); + M_MEMCOPY((g_assVTG_RR_LV2), (c_assVTG_RR_LV2_Mpv)); + M_MEMCOPY((g_assVR_MIN_LV2), (c_assVR_MIN_LV2_Mpv)); + M_MEMCOPY((g_assVR_MAX_LV2), (c_assVR_MAX_LV2_Mpv)); + M_MEMCOPY((g_assVR_INC_Y1_LV2), (c_assVR_INC_Y1_LV2_Mpv)); + M_MEMCOPY((g_assVR_INC_Y2_LV2), (c_assVR_INC_Y2_LV2_Mpv)); + M_MEMCOPY((g_assVR_INC_Y3_LV2), (c_assVR_INC_Y3_LV2_Mpv)); + M_MEMCOPY((g_assVR_INC_Y4_LV2), (c_assVR_INC_Y4_LV2_Mpv)); + M_MEMCOPY((g_assVR_INC_X1_LV2), (c_assVR_INC_X1_LV2_Mpv)); + M_MEMCOPY((g_assVR_INC_X2_LV2), (c_assVR_INC_X2_LV2_Mpv)); + M_MEMCOPY((g_assVR_INC_X3_LV2), (c_assVR_INC_X3_LV2_Mpv)); + M_MEMCOPY((g_assVR_INC_X4_LV2), (c_assVR_INC_X4_LV2_Mpv)); + M_MEMCOPY((g_assVR_AMB_Y1_LV2), (c_assVR_AMB_Y1_LV2_Mpv)); + M_MEMCOPY((g_assVR_AMB_Y2_LV2), (c_assVR_AMB_Y2_LV2_Mpv)); + M_MEMCOPY((g_assVR_AMB_X1_LV2), (c_assVR_AMB_X1_LV2_Mpv)); + M_MEMCOPY((g_assVR_AMB_X2_LV2), (c_assVR_AMB_X2_LV2_Mpv)); + M_MEMCOPY((g_assVR_SUN_Y1_LV2), (c_assVR_SUN_Y1_LV2_Mpv)); + M_MEMCOPY((g_assVR_SUN_Y2_LV2), (c_assVR_SUN_Y2_LV2_Mpv)); + M_MEMCOPY((g_assVR_SUN_X1_LV2), (c_assVR_SUN_X1_LV2_Mpv)); + M_MEMCOPY((g_assVR_SUN_X2_LV2), (c_assVR_SUN_X2_LV2_Mpv)); + M_MEMCOPY((g_assTG_RL_LV2), (c_assTG_RL_LV2_Mpv)); + M_MEMCOPY((g_assTG_RR_LV2), (c_assTG_RR_LV2_Mpv)); + M_MEMCOPY((g_assDTG_R_MIN_LV2), (c_assDTG_R_MIN_LV2_Mpv)); + M_MEMCOPY((g_assDTG_R_MAX_LV2), (c_assDTG_R_MAX_LV2_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_Y1_LV2), (c_assDTG_R_INC_Y1_LV2_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_Y2_LV2), (c_assDTG_R_INC_Y2_LV2_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_Y3_LV2), (c_assDTG_R_INC_Y3_LV2_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_Y4_LV2), (c_assDTG_R_INC_Y4_LV2_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_X1_LV2), (c_assDTG_R_INC_X1_LV2_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_X2_LV2), (c_assDTG_R_INC_X2_LV2_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_X3_LV2), (c_assDTG_R_INC_X3_LV2_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_X4_LV2), (c_assDTG_R_INC_X4_LV2_Mpv)); + M_MEMCOPY((g_assDTG_R_AMB_Y1_LV2), (c_assDTG_R_AMB_Y1_LV2_Mpv)); + M_MEMCOPY((g_assDTG_R_AMB_Y2_LV2), (c_assDTG_R_AMB_Y2_LV2_Mpv)); + M_MEMCOPY((g_assDTG_R_AMB_X1_LV2), (c_assDTG_R_AMB_X1_LV2_Mpv)); + M_MEMCOPY((g_assDTG_R_AMB_X2_LV2), (c_assDTG_R_AMB_X2_LV2_Mpv)); + M_MEMCOPY((g_assDTG_R_SUN_Y1_LV2), (c_assDTG_R_SUN_Y1_LV2_Mpv)); + M_MEMCOPY((g_assDTG_R_SUN_Y2_LV2), (c_assDTG_R_SUN_Y2_LV2_Mpv)); + M_MEMCOPY((g_assDTG_R_SUN_X1_LV2), (c_assDTG_R_SUN_X1_LV2_Mpv)); + M_MEMCOPY((g_assDTG_R_SUN_X2_LV2), (c_assDTG_R_SUN_X2_LV2_Mpv)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FR_LV2), (c_assCORRECT_DUCT_TIME_FR_LV2_Mpv)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FL_LV2), (c_assCORRECT_DUCT_TIME_FL_LV2_Mpv)); + M_MEMCOPY((g_assCORRECT_DUCT_RATE_LV2), (c_assCORRECT_DUCT_RATE_LV2_Mpv)); + M_MEMCOPY((g_assCORRECT_DUCT_MAX_LV2), (c_assCORRECT_DUCT_MAX_LV2_Mpv)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FR_LV2), (c_assCORRECT_AF_TIME_FR_LV2_Mpv)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FL_LV2), (c_assCORRECT_AF_TIME_FL_LV2_Mpv)); + M_MEMCOPY((g_assCORRECT_AF_RATE_LV2), (c_assCORRECT_AF_RATE_LV2_Mpv)); + M_MEMCOPY((g_assCORRECT_AF_MAX_LV2), (c_assCORRECT_AF_MAX_LV2_Mpv)); +/* ------------------------------------------Lv2 : End*/ + M_MEMCOPY((g_assINCAR_TG_FL_LV3), (c_assINCAR_TG_FL_LV3_Mpv)); + M_MEMCOPY((g_assINCAR_TG_FR_LV3), (c_assINCAR_TG_FR_LV3_Mpv)); + M_MEMCOPY((g_assVTG_FL_LV3), (c_assVTG_FL_LV3_Mpv)); + M_MEMCOPY((g_assVTG_FR_LV3), (c_assVTG_FR_LV3_Mpv)); + M_MEMCOPY((g_assVF_MIN_LV3), (c_assVF_MIN_LV3_Mpv)); + M_MEMCOPY((g_assVF_MAX_LV3), (c_assVF_MAX_LV3_Mpv)); + M_MEMCOPY((g_assVF_INC_Y1_LV3), (c_assVF_INC_Y1_LV3_Mpv)); + M_MEMCOPY((g_assVF_INC_Y2_LV3), (c_assVF_INC_Y2_LV3_Mpv)); + M_MEMCOPY((g_assVF_INC_Y3_LV3), (c_assVF_INC_Y3_LV3_Mpv)); + M_MEMCOPY((g_assVF_INC_Y4_LV3), (c_assVF_INC_Y4_LV3_Mpv)); + M_MEMCOPY((g_assVF_INC_X1_LV3), (c_assVF_INC_X1_LV3_Mpv)); + M_MEMCOPY((g_assVF_INC_X2_LV3), (c_assVF_INC_X2_LV3_Mpv)); + M_MEMCOPY((g_assVF_INC_X3_LV3), (c_assVF_INC_X3_LV3_Mpv)); + M_MEMCOPY((g_assVF_INC_X4_LV3), (c_assVF_INC_X4_LV3_Mpv)); + M_MEMCOPY((g_assVF_AMB_Y1_LV3), (c_assVF_AMB_Y1_LV3_Mpv)); + M_MEMCOPY((g_assVF_AMB_Y2_LV3), (c_assVF_AMB_Y2_LV3_Mpv)); + M_MEMCOPY((g_assVF_AMB_X1_LV3), (c_assVF_AMB_X1_LV3_Mpv)); + M_MEMCOPY((g_assVF_AMB_X2_LV3), (c_assVF_AMB_X2_LV3_Mpv)); + M_MEMCOPY((g_assVF_SUN_Y1_LV3), (c_assVF_SUN_Y1_LV3_Mpv)); + M_MEMCOPY((g_assVF_SUN_Y2_LV3), (c_assVF_SUN_Y2_LV3_Mpv)); + M_MEMCOPY((g_assVF_SUN_X1_LV3), (c_assVF_SUN_X1_LV3_Mpv)); + M_MEMCOPY((g_assVF_SUN_X2_LV3), (c_assVF_SUN_X2_LV3_Mpv)); + M_MEMCOPY((g_assTG_FLU_LV3), (c_assTG_FLU_LV3_Mpv)); + M_MEMCOPY((g_assTG_FRU_LV3), (c_assTG_FRU_LV3_Mpv)); + M_MEMCOPY((g_assDTG_FU_MIN_LV3), (c_assDTG_FU_MIN_LV3_Mpv)); + M_MEMCOPY((g_assDTG_FU_MAX_LV3), (c_assDTG_FU_MAX_LV3_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_Y1_LV3), (c_assDTG_FU_INC_Y1_LV3_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_Y2_LV3), (c_assDTG_FU_INC_Y2_LV3_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_Y3_LV3), (c_assDTG_FU_INC_Y3_LV3_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_Y4_LV3), (c_assDTG_FU_INC_Y4_LV3_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_X1_LV3), (c_assDTG_FU_INC_X1_LV3_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_X2_LV3), (c_assDTG_FU_INC_X2_LV3_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_X3_LV3), (c_assDTG_FU_INC_X3_LV3_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_X4_LV3), (c_assDTG_FU_INC_X4_LV3_Mpv)); + M_MEMCOPY((g_assDTG_FU_AMB_Y1_LV3), (c_assDTG_FU_AMB_Y1_LV3_Mpv)); + M_MEMCOPY((g_assDTG_FU_AMB_Y2_LV3), (c_assDTG_FU_AMB_Y2_LV3_Mpv)); + M_MEMCOPY((g_assDTG_FU_AMB_X1_LV3), (c_assDTG_FU_AMB_X1_LV3_Mpv)); + M_MEMCOPY((g_assDTG_FU_AMB_X2_LV3), (c_assDTG_FU_AMB_X2_LV3_Mpv)); + M_MEMCOPY((g_assDTG_FU_SUN_Y1_LV3), (c_assDTG_FU_SUN_Y1_LV3_Mpv)); + M_MEMCOPY((g_assDTG_FU_SUN_Y2_LV3), (c_assDTG_FU_SUN_Y2_LV3_Mpv)); + M_MEMCOPY((g_assDTG_FU_SUN_X1_LV3), (c_assDTG_FU_SUN_X1_LV3_Mpv)); + M_MEMCOPY((g_assDTG_FU_SUN_X2_LV3), (c_assDTG_FU_SUN_X2_LV3_Mpv)); + M_MEMCOPY((g_assTG_FLL_LV3), (c_assTG_FLL_LV3_Mpv)); + M_MEMCOPY((g_assTG_FRL_LV3), (c_assTG_FRL_LV3_Mpv)); + M_MEMCOPY((g_assDTG_FL_MIN_LV3), (c_assDTG_FL_MIN_LV3_Mpv)); + M_MEMCOPY((g_assDTG_FL_MAX_LV3), (c_assDTG_FL_MAX_LV3_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_Y1_LV3), (c_assDTG_FL_INC_Y1_LV3_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_Y2_LV3), (c_assDTG_FL_INC_Y2_LV3_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_Y3_LV3), (c_assDTG_FL_INC_Y3_LV3_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_Y4_LV3), (c_assDTG_FL_INC_Y4_LV3_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_X1_LV3), (c_assDTG_FL_INC_X1_LV3_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_X2_LV3), (c_assDTG_FL_INC_X2_LV3_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_X3_LV3), (c_assDTG_FL_INC_X3_LV3_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_X4_LV3), (c_assDTG_FL_INC_X4_LV3_Mpv)); + M_MEMCOPY((g_assDTG_FL_AMB_Y1_LV3), (c_assDTG_FL_AMB_Y1_LV3_Mpv)); + M_MEMCOPY((g_assDTG_FL_AMB_Y2_LV3), (c_assDTG_FL_AMB_Y2_LV3_Mpv)); + M_MEMCOPY((g_assDTG_FL_AMB_X1_LV3), (c_assDTG_FL_AMB_X1_LV3_Mpv)); + M_MEMCOPY((g_assDTG_FL_AMB_X2_LV3), (c_assDTG_FL_AMB_X2_LV3_Mpv)); + M_MEMCOPY((g_assDTG_FL_SUN_Y1_LV3), (c_assDTG_FL_SUN_Y1_LV3_Mpv)); + M_MEMCOPY((g_assDTG_FL_SUN_Y2_LV3), (c_assDTG_FL_SUN_Y2_LV3_Mpv)); + M_MEMCOPY((g_assDTG_FL_SUN_X1_LV3), (c_assDTG_FL_SUN_X1_LV3_Mpv)); + M_MEMCOPY((g_assDTG_FL_SUN_X2_LV3), (c_assDTG_FL_SUN_X2_LV3_Mpv)); + M_MEMCOPY((g_assINCAR_TG_RL_LV3), (c_assINCAR_TG_RL_LV3_Mpv)); + M_MEMCOPY((g_assINCAR_TG_RR_LV3), (c_assINCAR_TG_RR_LV3_Mpv)); + M_MEMCOPY((g_assVTG_RL_LV3), (c_assVTG_RL_LV3_Mpv)); + M_MEMCOPY((g_assVTG_RR_LV3), (c_assVTG_RR_LV3_Mpv)); + M_MEMCOPY((g_assVR_MIN_LV3), (c_assVR_MIN_LV3_Mpv)); + M_MEMCOPY((g_assVR_MAX_LV3), (c_assVR_MAX_LV3_Mpv)); + M_MEMCOPY((g_assVR_INC_Y1_LV3), (c_assVR_INC_Y1_LV3_Mpv)); + M_MEMCOPY((g_assVR_INC_Y2_LV3), (c_assVR_INC_Y2_LV3_Mpv)); + M_MEMCOPY((g_assVR_INC_Y3_LV3), (c_assVR_INC_Y3_LV3_Mpv)); + M_MEMCOPY((g_assVR_INC_Y4_LV3), (c_assVR_INC_Y4_LV3_Mpv)); + M_MEMCOPY((g_assVR_INC_X1_LV3), (c_assVR_INC_X1_LV3_Mpv)); + M_MEMCOPY((g_assVR_INC_X2_LV3), (c_assVR_INC_X2_LV3_Mpv)); + M_MEMCOPY((g_assVR_INC_X3_LV3), (c_assVR_INC_X3_LV3_Mpv)); + M_MEMCOPY((g_assVR_INC_X4_LV3), (c_assVR_INC_X4_LV3_Mpv)); + M_MEMCOPY((g_assVR_AMB_Y1_LV3), (c_assVR_AMB_Y1_LV3_Mpv)); + M_MEMCOPY((g_assVR_AMB_Y2_LV3), (c_assVR_AMB_Y2_LV3_Mpv)); + M_MEMCOPY((g_assVR_AMB_X1_LV3), (c_assVR_AMB_X1_LV3_Mpv)); + M_MEMCOPY((g_assVR_AMB_X2_LV3), (c_assVR_AMB_X2_LV3_Mpv)); + M_MEMCOPY((g_assVR_SUN_Y1_LV3), (c_assVR_SUN_Y1_LV3_Mpv)); + M_MEMCOPY((g_assVR_SUN_Y2_LV3), (c_assVR_SUN_Y2_LV3_Mpv)); + M_MEMCOPY((g_assVR_SUN_X1_LV3), (c_assVR_SUN_X1_LV3_Mpv)); + M_MEMCOPY((g_assVR_SUN_X2_LV3), (c_assVR_SUN_X2_LV3_Mpv)); + M_MEMCOPY((g_assTG_RL_LV3), (c_assTG_RL_LV3_Mpv)); + M_MEMCOPY((g_assTG_RR_LV3), (c_assTG_RR_LV3_Mpv)); + M_MEMCOPY((g_assDTG_R_MIN_LV3), (c_assDTG_R_MIN_LV3_Mpv)); + M_MEMCOPY((g_assDTG_R_MAX_LV3), (c_assDTG_R_MAX_LV3_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_Y1_LV3), (c_assDTG_R_INC_Y1_LV3_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_Y2_LV3), (c_assDTG_R_INC_Y2_LV3_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_Y3_LV3), (c_assDTG_R_INC_Y3_LV3_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_Y4_LV3), (c_assDTG_R_INC_Y4_LV3_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_X1_LV3), (c_assDTG_R_INC_X1_LV3_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_X2_LV3), (c_assDTG_R_INC_X2_LV3_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_X3_LV3), (c_assDTG_R_INC_X3_LV3_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_X4_LV3), (c_assDTG_R_INC_X4_LV3_Mpv)); + M_MEMCOPY((g_assDTG_R_AMB_Y1_LV3), (c_assDTG_R_AMB_Y1_LV3_Mpv)); + M_MEMCOPY((g_assDTG_R_AMB_Y2_LV3), (c_assDTG_R_AMB_Y2_LV3_Mpv)); + M_MEMCOPY((g_assDTG_R_AMB_X1_LV3), (c_assDTG_R_AMB_X1_LV3_Mpv)); + M_MEMCOPY((g_assDTG_R_AMB_X2_LV3), (c_assDTG_R_AMB_X2_LV3_Mpv)); + M_MEMCOPY((g_assDTG_R_SUN_Y1_LV3), (c_assDTG_R_SUN_Y1_LV3_Mpv)); + M_MEMCOPY((g_assDTG_R_SUN_Y2_LV3), (c_assDTG_R_SUN_Y2_LV3_Mpv)); + M_MEMCOPY((g_assDTG_R_SUN_X1_LV3), (c_assDTG_R_SUN_X1_LV3_Mpv)); + M_MEMCOPY((g_assDTG_R_SUN_X2_LV3), (c_assDTG_R_SUN_X2_LV3_Mpv)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FR_LV3), (c_assCORRECT_DUCT_TIME_FR_LV3_Mpv)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FL_LV3), (c_assCORRECT_DUCT_TIME_FL_LV3_Mpv)); + M_MEMCOPY((g_assCORRECT_DUCT_RATE_LV3), (c_assCORRECT_DUCT_RATE_LV3_Mpv)); + M_MEMCOPY((g_assCORRECT_DUCT_MAX_LV3), (c_assCORRECT_DUCT_MAX_LV3_Mpv)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FR_LV3), (c_assCORRECT_AF_TIME_FR_LV3_Mpv)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FL_LV3), (c_assCORRECT_AF_TIME_FL_LV3_Mpv)); + M_MEMCOPY((g_assCORRECT_AF_RATE_LV3), (c_assCORRECT_AF_RATE_LV3_Mpv)); + M_MEMCOPY((g_assCORRECT_AF_MAX_LV3), (c_assCORRECT_AF_MAX_LV3_Mpv)); +/* ------------------------------------------Lv3 : End*/ + M_MEMCOPY((g_assINCAR_TG_FL_LV4), (c_assINCAR_TG_FL_LV4_Mpv)); + M_MEMCOPY((g_assINCAR_TG_FR_LV4), (c_assINCAR_TG_FR_LV4_Mpv)); + M_MEMCOPY((g_assVTG_FL_LV4), (c_assVTG_FL_LV4_Mpv)); + M_MEMCOPY((g_assVTG_FR_LV4), (c_assVTG_FR_LV4_Mpv)); + M_MEMCOPY((g_assVF_MIN_LV4), (c_assVF_MIN_LV4_Mpv)); + M_MEMCOPY((g_assVF_MAX_LV4), (c_assVF_MAX_LV4_Mpv)); + M_MEMCOPY((g_assVF_INC_Y1_LV4), (c_assVF_INC_Y1_LV4_Mpv)); + M_MEMCOPY((g_assVF_INC_Y2_LV4), (c_assVF_INC_Y2_LV4_Mpv)); + M_MEMCOPY((g_assVF_INC_Y3_LV4), (c_assVF_INC_Y3_LV4_Mpv)); + M_MEMCOPY((g_assVF_INC_Y4_LV4), (c_assVF_INC_Y4_LV4_Mpv)); + M_MEMCOPY((g_assVF_INC_X1_LV4), (c_assVF_INC_X1_LV4_Mpv)); + M_MEMCOPY((g_assVF_INC_X2_LV4), (c_assVF_INC_X2_LV4_Mpv)); + M_MEMCOPY((g_assVF_INC_X3_LV4), (c_assVF_INC_X3_LV4_Mpv)); + M_MEMCOPY((g_assVF_INC_X4_LV4), (c_assVF_INC_X4_LV4_Mpv)); + M_MEMCOPY((g_assVF_AMB_Y1_LV4), (c_assVF_AMB_Y1_LV4_Mpv)); + M_MEMCOPY((g_assVF_AMB_Y2_LV4), (c_assVF_AMB_Y2_LV4_Mpv)); + M_MEMCOPY((g_assVF_AMB_X1_LV4), (c_assVF_AMB_X1_LV4_Mpv)); + M_MEMCOPY((g_assVF_AMB_X2_LV4), (c_assVF_AMB_X2_LV4_Mpv)); + M_MEMCOPY((g_assVF_SUN_Y1_LV4), (c_assVF_SUN_Y1_LV4_Mpv)); + M_MEMCOPY((g_assVF_SUN_Y2_LV4), (c_assVF_SUN_Y2_LV4_Mpv)); + M_MEMCOPY((g_assVF_SUN_X1_LV4), (c_assVF_SUN_X1_LV4_Mpv)); + M_MEMCOPY((g_assVF_SUN_X2_LV4), (c_assVF_SUN_X2_LV4_Mpv)); + M_MEMCOPY((g_assTG_FLU_LV4), (c_assTG_FLU_LV4_Mpv)); + M_MEMCOPY((g_assTG_FRU_LV4), (c_assTG_FRU_LV4_Mpv)); + M_MEMCOPY((g_assDTG_FU_MIN_LV4), (c_assDTG_FU_MIN_LV4_Mpv)); + M_MEMCOPY((g_assDTG_FU_MAX_LV4), (c_assDTG_FU_MAX_LV4_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_Y1_LV4), (c_assDTG_FU_INC_Y1_LV4_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_Y2_LV4), (c_assDTG_FU_INC_Y2_LV4_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_Y3_LV4), (c_assDTG_FU_INC_Y3_LV4_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_Y4_LV4), (c_assDTG_FU_INC_Y4_LV4_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_X1_LV4), (c_assDTG_FU_INC_X1_LV4_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_X2_LV4), (c_assDTG_FU_INC_X2_LV4_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_X3_LV4), (c_assDTG_FU_INC_X3_LV4_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_X4_LV4), (c_assDTG_FU_INC_X4_LV4_Mpv)); + M_MEMCOPY((g_assDTG_FU_AMB_Y1_LV4), (c_assDTG_FU_AMB_Y1_LV4_Mpv)); + M_MEMCOPY((g_assDTG_FU_AMB_Y2_LV4), (c_assDTG_FU_AMB_Y2_LV4_Mpv)); + M_MEMCOPY((g_assDTG_FU_AMB_X1_LV4), (c_assDTG_FU_AMB_X1_LV4_Mpv)); + M_MEMCOPY((g_assDTG_FU_AMB_X2_LV4), (c_assDTG_FU_AMB_X2_LV4_Mpv)); + M_MEMCOPY((g_assDTG_FU_SUN_Y1_LV4), (c_assDTG_FU_SUN_Y1_LV4_Mpv)); + M_MEMCOPY((g_assDTG_FU_SUN_Y2_LV4), (c_assDTG_FU_SUN_Y2_LV4_Mpv)); + M_MEMCOPY((g_assDTG_FU_SUN_X1_LV4), (c_assDTG_FU_SUN_X1_LV4_Mpv)); + M_MEMCOPY((g_assDTG_FU_SUN_X2_LV4), (c_assDTG_FU_SUN_X2_LV4_Mpv)); + M_MEMCOPY((g_assTG_FLL_LV4), (c_assTG_FLL_LV4_Mpv)); + M_MEMCOPY((g_assTG_FRL_LV4), (c_assTG_FRL_LV4_Mpv)); + M_MEMCOPY((g_assDTG_FL_MIN_LV4), (c_assDTG_FL_MIN_LV4_Mpv)); + M_MEMCOPY((g_assDTG_FL_MAX_LV4), (c_assDTG_FL_MAX_LV4_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_Y1_LV4), (c_assDTG_FL_INC_Y1_LV4_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_Y2_LV4), (c_assDTG_FL_INC_Y2_LV4_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_Y3_LV4), (c_assDTG_FL_INC_Y3_LV4_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_Y4_LV4), (c_assDTG_FL_INC_Y4_LV4_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_X1_LV4), (c_assDTG_FL_INC_X1_LV4_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_X2_LV4), (c_assDTG_FL_INC_X2_LV4_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_X3_LV4), (c_assDTG_FL_INC_X3_LV4_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_X4_LV4), (c_assDTG_FL_INC_X4_LV4_Mpv)); + M_MEMCOPY((g_assDTG_FL_AMB_Y1_LV4), (c_assDTG_FL_AMB_Y1_LV4_Mpv)); + M_MEMCOPY((g_assDTG_FL_AMB_Y2_LV4), (c_assDTG_FL_AMB_Y2_LV4_Mpv)); + M_MEMCOPY((g_assDTG_FL_AMB_X1_LV4), (c_assDTG_FL_AMB_X1_LV4_Mpv)); + M_MEMCOPY((g_assDTG_FL_AMB_X2_LV4), (c_assDTG_FL_AMB_X2_LV4_Mpv)); + M_MEMCOPY((g_assDTG_FL_SUN_Y1_LV4), (c_assDTG_FL_SUN_Y1_LV4_Mpv)); + M_MEMCOPY((g_assDTG_FL_SUN_Y2_LV4), (c_assDTG_FL_SUN_Y2_LV4_Mpv)); + M_MEMCOPY((g_assDTG_FL_SUN_X1_LV4), (c_assDTG_FL_SUN_X1_LV4_Mpv)); + M_MEMCOPY((g_assDTG_FL_SUN_X2_LV4), (c_assDTG_FL_SUN_X2_LV4_Mpv)); + M_MEMCOPY((g_assINCAR_TG_RL_LV4), (c_assINCAR_TG_RL_LV4_Mpv)); + M_MEMCOPY((g_assINCAR_TG_RR_LV4), (c_assINCAR_TG_RR_LV4_Mpv)); + M_MEMCOPY((g_assVTG_RL_LV4), (c_assVTG_RL_LV4_Mpv)); + M_MEMCOPY((g_assVTG_RR_LV4), (c_assVTG_RR_LV4_Mpv)); + M_MEMCOPY((g_assVR_MIN_LV4), (c_assVR_MIN_LV4_Mpv)); + M_MEMCOPY((g_assVR_MAX_LV4), (c_assVR_MAX_LV4_Mpv)); + M_MEMCOPY((g_assVR_INC_Y1_LV4), (c_assVR_INC_Y1_LV4_Mpv)); + M_MEMCOPY((g_assVR_INC_Y2_LV4), (c_assVR_INC_Y2_LV4_Mpv)); + M_MEMCOPY((g_assVR_INC_Y3_LV4), (c_assVR_INC_Y3_LV4_Mpv)); + M_MEMCOPY((g_assVR_INC_Y4_LV4), (c_assVR_INC_Y4_LV4_Mpv)); + M_MEMCOPY((g_assVR_INC_X1_LV4), (c_assVR_INC_X1_LV4_Mpv)); + M_MEMCOPY((g_assVR_INC_X2_LV4), (c_assVR_INC_X2_LV4_Mpv)); + M_MEMCOPY((g_assVR_INC_X3_LV4), (c_assVR_INC_X3_LV4_Mpv)); + M_MEMCOPY((g_assVR_INC_X4_LV4), (c_assVR_INC_X4_LV4_Mpv)); + M_MEMCOPY((g_assVR_AMB_Y1_LV4), (c_assVR_AMB_Y1_LV4_Mpv)); + M_MEMCOPY((g_assVR_AMB_Y2_LV4), (c_assVR_AMB_Y2_LV4_Mpv)); + M_MEMCOPY((g_assVR_AMB_X1_LV4), (c_assVR_AMB_X1_LV4_Mpv)); + M_MEMCOPY((g_assVR_AMB_X2_LV4), (c_assVR_AMB_X2_LV4_Mpv)); + M_MEMCOPY((g_assVR_SUN_Y1_LV4), (c_assVR_SUN_Y1_LV4_Mpv)); + M_MEMCOPY((g_assVR_SUN_Y2_LV4), (c_assVR_SUN_Y2_LV4_Mpv)); + M_MEMCOPY((g_assVR_SUN_X1_LV4), (c_assVR_SUN_X1_LV4_Mpv)); + M_MEMCOPY((g_assVR_SUN_X2_LV4), (c_assVR_SUN_X2_LV4_Mpv)); + M_MEMCOPY((g_assTG_RL_LV4), (c_assTG_RL_LV4_Mpv)); + M_MEMCOPY((g_assTG_RR_LV4), (c_assTG_RR_LV4_Mpv)); + M_MEMCOPY((g_assDTG_R_MIN_LV4), (c_assDTG_R_MIN_LV4_Mpv)); + M_MEMCOPY((g_assDTG_R_MAX_LV4), (c_assDTG_R_MAX_LV4_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_Y1_LV4), (c_assDTG_R_INC_Y1_LV4_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_Y2_LV4), (c_assDTG_R_INC_Y2_LV4_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_Y3_LV4), (c_assDTG_R_INC_Y3_LV4_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_Y4_LV4), (c_assDTG_R_INC_Y4_LV4_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_X1_LV4), (c_assDTG_R_INC_X1_LV4_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_X2_LV4), (c_assDTG_R_INC_X2_LV4_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_X3_LV4), (c_assDTG_R_INC_X3_LV4_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_X4_LV4), (c_assDTG_R_INC_X4_LV4_Mpv)); + M_MEMCOPY((g_assDTG_R_AMB_Y1_LV4), (c_assDTG_R_AMB_Y1_LV4_Mpv)); + M_MEMCOPY((g_assDTG_R_AMB_Y2_LV4), (c_assDTG_R_AMB_Y2_LV4_Mpv)); + M_MEMCOPY((g_assDTG_R_AMB_X1_LV4), (c_assDTG_R_AMB_X1_LV4_Mpv)); + M_MEMCOPY((g_assDTG_R_AMB_X2_LV4), (c_assDTG_R_AMB_X2_LV4_Mpv)); + M_MEMCOPY((g_assDTG_R_SUN_Y1_LV4), (c_assDTG_R_SUN_Y1_LV4_Mpv)); + M_MEMCOPY((g_assDTG_R_SUN_Y2_LV4), (c_assDTG_R_SUN_Y2_LV4_Mpv)); + M_MEMCOPY((g_assDTG_R_SUN_X1_LV4), (c_assDTG_R_SUN_X1_LV4_Mpv)); + M_MEMCOPY((g_assDTG_R_SUN_X2_LV4), (c_assDTG_R_SUN_X2_LV4_Mpv)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FR_LV4), (c_assCORRECT_DUCT_TIME_FR_LV4_Mpv)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FL_LV4), (c_assCORRECT_DUCT_TIME_FL_LV4_Mpv)); + M_MEMCOPY((g_assCORRECT_DUCT_RATE_LV4), (c_assCORRECT_DUCT_RATE_LV4_Mpv)); + M_MEMCOPY((g_assCORRECT_DUCT_MAX_LV4), (c_assCORRECT_DUCT_MAX_LV4_Mpv)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FR_LV4), (c_assCORRECT_AF_TIME_FR_LV4_Mpv)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FL_LV4), (c_assCORRECT_AF_TIME_FL_LV4_Mpv)); + M_MEMCOPY((g_assCORRECT_AF_RATE_LV4), (c_assCORRECT_AF_RATE_LV4_Mpv)); + M_MEMCOPY((g_assCORRECT_AF_MAX_LV4), (c_assCORRECT_AF_MAX_LV4_Mpv)); +/* ------------------------------------------Lv4 : End*/ + M_MEMCOPY((g_assINCAR_TG_FL_LV5), (c_assINCAR_TG_FL_LV5_Mpv)); + M_MEMCOPY((g_assINCAR_TG_FR_LV5), (c_assINCAR_TG_FR_LV5_Mpv)); + M_MEMCOPY((g_assVTG_FL_LV5), (c_assVTG_FL_LV5_Mpv)); + M_MEMCOPY((g_assVTG_FR_LV5), (c_assVTG_FR_LV5_Mpv)); + M_MEMCOPY((g_assVF_MIN_LV5), (c_assVF_MIN_LV5_Mpv)); + M_MEMCOPY((g_assVF_MAX_LV5), (c_assVF_MAX_LV5_Mpv)); + M_MEMCOPY((g_assVF_INC_Y1_LV5), (c_assVF_INC_Y1_LV5_Mpv)); + M_MEMCOPY((g_assVF_INC_Y2_LV5), (c_assVF_INC_Y2_LV5_Mpv)); + M_MEMCOPY((g_assVF_INC_Y3_LV5), (c_assVF_INC_Y3_LV5_Mpv)); + M_MEMCOPY((g_assVF_INC_Y4_LV5), (c_assVF_INC_Y4_LV5_Mpv)); + M_MEMCOPY((g_assVF_INC_X1_LV5), (c_assVF_INC_X1_LV5_Mpv)); + M_MEMCOPY((g_assVF_INC_X2_LV5), (c_assVF_INC_X2_LV5_Mpv)); + M_MEMCOPY((g_assVF_INC_X3_LV5), (c_assVF_INC_X3_LV5_Mpv)); + M_MEMCOPY((g_assVF_INC_X4_LV5), (c_assVF_INC_X4_LV5_Mpv)); + M_MEMCOPY((g_assVF_AMB_Y1_LV5), (c_assVF_AMB_Y1_LV5_Mpv)); + M_MEMCOPY((g_assVF_AMB_Y2_LV5), (c_assVF_AMB_Y2_LV5_Mpv)); + M_MEMCOPY((g_assVF_AMB_X1_LV5), (c_assVF_AMB_X1_LV5_Mpv)); + M_MEMCOPY((g_assVF_AMB_X2_LV5), (c_assVF_AMB_X2_LV5_Mpv)); + M_MEMCOPY((g_assVF_SUN_Y1_LV5), (c_assVF_SUN_Y1_LV5_Mpv)); + M_MEMCOPY((g_assVF_SUN_Y2_LV5), (c_assVF_SUN_Y2_LV5_Mpv)); + M_MEMCOPY((g_assVF_SUN_X1_LV5), (c_assVF_SUN_X1_LV5_Mpv)); + M_MEMCOPY((g_assVF_SUN_X2_LV5), (c_assVF_SUN_X2_LV5_Mpv)); + M_MEMCOPY((g_assTG_FLU_LV5), (c_assTG_FLU_LV5_Mpv)); + M_MEMCOPY((g_assTG_FRU_LV5), (c_assTG_FRU_LV5_Mpv)); + M_MEMCOPY((g_assDTG_FU_MIN_LV5), (c_assDTG_FU_MIN_LV5_Mpv)); + M_MEMCOPY((g_assDTG_FU_MAX_LV5), (c_assDTG_FU_MAX_LV5_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_Y1_LV5), (c_assDTG_FU_INC_Y1_LV5_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_Y2_LV5), (c_assDTG_FU_INC_Y2_LV5_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_Y3_LV5), (c_assDTG_FU_INC_Y3_LV5_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_Y4_LV5), (c_assDTG_FU_INC_Y4_LV5_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_X1_LV5), (c_assDTG_FU_INC_X1_LV5_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_X2_LV5), (c_assDTG_FU_INC_X2_LV5_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_X3_LV5), (c_assDTG_FU_INC_X3_LV5_Mpv)); + M_MEMCOPY((g_assDTG_FU_INC_X4_LV5), (c_assDTG_FU_INC_X4_LV5_Mpv)); + M_MEMCOPY((g_assDTG_FU_AMB_Y1_LV5), (c_assDTG_FU_AMB_Y1_LV5_Mpv)); + M_MEMCOPY((g_assDTG_FU_AMB_Y2_LV5), (c_assDTG_FU_AMB_Y2_LV5_Mpv)); + M_MEMCOPY((g_assDTG_FU_AMB_X1_LV5), (c_assDTG_FU_AMB_X1_LV5_Mpv)); + M_MEMCOPY((g_assDTG_FU_AMB_X2_LV5), (c_assDTG_FU_AMB_X2_LV5_Mpv)); + M_MEMCOPY((g_assDTG_FU_SUN_Y1_LV5), (c_assDTG_FU_SUN_Y1_LV5_Mpv)); + M_MEMCOPY((g_assDTG_FU_SUN_Y2_LV5), (c_assDTG_FU_SUN_Y2_LV5_Mpv)); + M_MEMCOPY((g_assDTG_FU_SUN_X1_LV5), (c_assDTG_FU_SUN_X1_LV5_Mpv)); + M_MEMCOPY((g_assDTG_FU_SUN_X2_LV5), (c_assDTG_FU_SUN_X2_LV5_Mpv)); + M_MEMCOPY((g_assTG_FLL_LV5), (c_assTG_FLL_LV5_Mpv)); + M_MEMCOPY((g_assTG_FRL_LV5), (c_assTG_FRL_LV5_Mpv)); + M_MEMCOPY((g_assDTG_FL_MIN_LV5), (c_assDTG_FL_MIN_LV5_Mpv)); + M_MEMCOPY((g_assDTG_FL_MAX_LV5), (c_assDTG_FL_MAX_LV5_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_Y1_LV5), (c_assDTG_FL_INC_Y1_LV5_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_Y2_LV5), (c_assDTG_FL_INC_Y2_LV5_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_Y3_LV5), (c_assDTG_FL_INC_Y3_LV5_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_Y4_LV5), (c_assDTG_FL_INC_Y4_LV5_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_X1_LV5), (c_assDTG_FL_INC_X1_LV5_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_X2_LV5), (c_assDTG_FL_INC_X2_LV5_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_X3_LV5), (c_assDTG_FL_INC_X3_LV5_Mpv)); + M_MEMCOPY((g_assDTG_FL_INC_X4_LV5), (c_assDTG_FL_INC_X4_LV5_Mpv)); + M_MEMCOPY((g_assDTG_FL_AMB_Y1_LV5), (c_assDTG_FL_AMB_Y1_LV5_Mpv)); + M_MEMCOPY((g_assDTG_FL_AMB_Y2_LV5), (c_assDTG_FL_AMB_Y2_LV5_Mpv)); + M_MEMCOPY((g_assDTG_FL_AMB_X1_LV5), (c_assDTG_FL_AMB_X1_LV5_Mpv)); + M_MEMCOPY((g_assDTG_FL_AMB_X2_LV5), (c_assDTG_FL_AMB_X2_LV5_Mpv)); + M_MEMCOPY((g_assDTG_FL_SUN_Y1_LV5), (c_assDTG_FL_SUN_Y1_LV5_Mpv)); + M_MEMCOPY((g_assDTG_FL_SUN_Y2_LV5), (c_assDTG_FL_SUN_Y2_LV5_Mpv)); + M_MEMCOPY((g_assDTG_FL_SUN_X1_LV5), (c_assDTG_FL_SUN_X1_LV5_Mpv)); + M_MEMCOPY((g_assDTG_FL_SUN_X2_LV5), (c_assDTG_FL_SUN_X2_LV5_Mpv)); + M_MEMCOPY((g_assINCAR_TG_RL_LV5), (c_assINCAR_TG_RL_LV5_Mpv)); + M_MEMCOPY((g_assINCAR_TG_RR_LV5), (c_assINCAR_TG_RR_LV5_Mpv)); + M_MEMCOPY((g_assVTG_RL_LV5), (c_assVTG_RL_LV5_Mpv)); + M_MEMCOPY((g_assVTG_RR_LV5), (c_assVTG_RR_LV5_Mpv)); + M_MEMCOPY((g_assVR_MIN_LV5), (c_assVR_MIN_LV5_Mpv)); + M_MEMCOPY((g_assVR_MAX_LV5), (c_assVR_MAX_LV5_Mpv)); + M_MEMCOPY((g_assVR_INC_Y1_LV5), (c_assVR_INC_Y1_LV5_Mpv)); + M_MEMCOPY((g_assVR_INC_Y2_LV5), (c_assVR_INC_Y2_LV5_Mpv)); + M_MEMCOPY((g_assVR_INC_Y3_LV5), (c_assVR_INC_Y3_LV5_Mpv)); + M_MEMCOPY((g_assVR_INC_Y4_LV5), (c_assVR_INC_Y4_LV5_Mpv)); + M_MEMCOPY((g_assVR_INC_X1_LV5), (c_assVR_INC_X1_LV5_Mpv)); + M_MEMCOPY((g_assVR_INC_X2_LV5), (c_assVR_INC_X2_LV5_Mpv)); + M_MEMCOPY((g_assVR_INC_X3_LV5), (c_assVR_INC_X3_LV5_Mpv)); + M_MEMCOPY((g_assVR_INC_X4_LV5), (c_assVR_INC_X4_LV5_Mpv)); + M_MEMCOPY((g_assVR_AMB_Y1_LV5), (c_assVR_AMB_Y1_LV5_Mpv)); + M_MEMCOPY((g_assVR_AMB_Y2_LV5), (c_assVR_AMB_Y2_LV5_Mpv)); + M_MEMCOPY((g_assVR_AMB_X1_LV5), (c_assVR_AMB_X1_LV5_Mpv)); + M_MEMCOPY((g_assVR_AMB_X2_LV5), (c_assVR_AMB_X2_LV5_Mpv)); + M_MEMCOPY((g_assVR_SUN_Y1_LV5), (c_assVR_SUN_Y1_LV5_Mpv)); + M_MEMCOPY((g_assVR_SUN_Y2_LV5), (c_assVR_SUN_Y2_LV5_Mpv)); + M_MEMCOPY((g_assVR_SUN_X1_LV5), (c_assVR_SUN_X1_LV5_Mpv)); + M_MEMCOPY((g_assVR_SUN_X2_LV5), (c_assVR_SUN_X2_LV5_Mpv)); + M_MEMCOPY((g_assTG_RL_LV5), (c_assTG_RL_LV5_Mpv)); + M_MEMCOPY((g_assTG_RR_LV5), (c_assTG_RR_LV5_Mpv)); + M_MEMCOPY((g_assDTG_R_MIN_LV5), (c_assDTG_R_MIN_LV5_Mpv)); + M_MEMCOPY((g_assDTG_R_MAX_LV5), (c_assDTG_R_MAX_LV5_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_Y1_LV5), (c_assDTG_R_INC_Y1_LV5_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_Y2_LV5), (c_assDTG_R_INC_Y2_LV5_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_Y3_LV5), (c_assDTG_R_INC_Y3_LV5_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_Y4_LV5), (c_assDTG_R_INC_Y4_LV5_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_X1_LV5), (c_assDTG_R_INC_X1_LV5_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_X2_LV5), (c_assDTG_R_INC_X2_LV5_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_X3_LV5), (c_assDTG_R_INC_X3_LV5_Mpv)); + M_MEMCOPY((g_assDTG_R_INC_X4_LV5), (c_assDTG_R_INC_X4_LV5_Mpv)); + M_MEMCOPY((g_assDTG_R_AMB_Y1_LV5), (c_assDTG_R_AMB_Y1_LV5_Mpv)); + M_MEMCOPY((g_assDTG_R_AMB_Y2_LV5), (c_assDTG_R_AMB_Y2_LV5_Mpv)); + M_MEMCOPY((g_assDTG_R_AMB_X1_LV5), (c_assDTG_R_AMB_X1_LV5_Mpv)); + M_MEMCOPY((g_assDTG_R_AMB_X2_LV5), (c_assDTG_R_AMB_X2_LV5_Mpv)); + M_MEMCOPY((g_assDTG_R_SUN_Y1_LV5), (c_assDTG_R_SUN_Y1_LV5_Mpv)); + M_MEMCOPY((g_assDTG_R_SUN_Y2_LV5), (c_assDTG_R_SUN_Y2_LV5_Mpv)); + M_MEMCOPY((g_assDTG_R_SUN_X1_LV5), (c_assDTG_R_SUN_X1_LV5_Mpv)); + M_MEMCOPY((g_assDTG_R_SUN_X2_LV5), (c_assDTG_R_SUN_X2_LV5_Mpv)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FR_LV5), (c_assCORRECT_DUCT_TIME_FR_LV5_Mpv)); + M_MEMCOPY((g_assCORRECT_DUCT_TIME_FL_LV5), (c_assCORRECT_DUCT_TIME_FL_LV5_Mpv)); + M_MEMCOPY((g_assCORRECT_DUCT_RATE_LV5), (c_assCORRECT_DUCT_RATE_LV5_Mpv)); + M_MEMCOPY((g_assCORRECT_DUCT_MAX_LV5), (c_assCORRECT_DUCT_MAX_LV5_Mpv)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FR_LV5), (c_assCORRECT_AF_TIME_FR_LV5_Mpv)); + M_MEMCOPY((g_assCORRECT_AF_TIME_FL_LV5), (c_assCORRECT_AF_TIME_FL_LV5_Mpv)); + M_MEMCOPY((g_assCORRECT_AF_RATE_LV5), (c_assCORRECT_AF_RATE_LV5_Mpv)); + M_MEMCOPY((g_assCORRECT_AF_MAX_LV5), (c_assCORRECT_AF_MAX_LV5_Mpv)); +/* ------------------------------------------Lv5 : End*/ + M_MEMCOPY((g_assDUCT_TGT_DEF_VALVE_L), (c_assDUCT_TGT_DEF_VALVE_L_Mpv)); + M_MEMCOPY((g_assDUCT_TGT_DEF_VALVE_R), (c_assDUCT_TGT_DEF_VALVE_R_Mpv)); +/* ------------------------------------------DuctTgt Increase : End*/ + M_MEMCOPY((g_assAMB_LV_UP), (c_assAMB_LV_UP_Mpv)); + M_MEMCOPY((g_assAMB_LV_DN), (c_assAMB_LV_DN_Mpv)); + M_MEMCOPY((g_assAMB_LV_TG), (c_assAMB_LV_TG_Mpv)); +/* ------------------------------------------Ambient LEVEL : End*/ + M_MEMCOPY((g_aucMODE_BY_SET_F_LV0), (c_aucMODE_BY_SET_F_LV0_Mpv)); + M_MEMCOPY((g_aucMODE_BY_SET_F_LV1), (c_aucMODE_BY_SET_F_LV1_Mpv)); + M_MEMCOPY((g_aucMODE_BY_SET_F_LV2), (c_aucMODE_BY_SET_F_LV2_Mpv)); + M_MEMCOPY((g_aucMODE_BY_SET_F_LV3), (c_aucMODE_BY_SET_F_LV3_Mpv)); + M_MEMCOPY((g_aucMODE_BY_SET_F_LV4), (c_aucMODE_BY_SET_F_LV4_Mpv)); + M_MEMCOPY((g_aucMODE_BY_SET_F_LV5), (c_aucMODE_BY_SET_F_LV5_Mpv)); + M_MEMCOPY((g_ausMODE_BY_DUCT_TG_R_LV0), (c_ausMODE_BY_DUCT_TG_R_LV0_Mpv)); + M_MEMCOPY((g_ausMODE_BY_DUCT_TG_R_LV1), (c_ausMODE_BY_DUCT_TG_R_LV1_Mpv)); + M_MEMCOPY((g_ausMODE_BY_DUCT_TG_R_LV2), (c_ausMODE_BY_DUCT_TG_R_LV2_Mpv)); + M_MEMCOPY((g_ausMODE_BY_DUCT_TG_R_LV3), (c_ausMODE_BY_DUCT_TG_R_LV3_Mpv)); + M_MEMCOPY((g_ausMODE_BY_DUCT_TG_R_LV4), (c_ausMODE_BY_DUCT_TG_R_LV4_Mpv)); + M_MEMCOPY((g_ausMODE_BY_DUCT_TG_R_LV5), (c_ausMODE_BY_DUCT_TG_R_LV5_Mpv)); +/* ------------------------------------------Mode depend on SET for each level : End*/ + g_ssPREC_REC_ON_AMB = c_ssPREC_REC_ON_AMB_Mpv; + g_ssPREC_REC_OFF_AMB = c_ssPREC_REC_OFF_AMB_Mpv; + M_MEMCOPY((g_aucPREC_VEH_SPD_OSA), (c_aucPREC_VEH_SPD_OSA_Mpv)); + M_MEMCOPY((g_assPRE_AMB_RANGE_WINTER), (c_assPRE_AMB_RANGE_WINTER_Mpv)); + M_MEMCOPY((g_aucPREC_OSA_WINTER), (c_aucPREC_OSA_WINTER_Mpv)); + M_MEMCOPY((g_aucPREC_REC_WINTER), (c_aucPREC_REC_WINTER_Mpv)); + M_MEMCOPY((g_ausPREC_HUMIDITY_NOK), (c_ausPREC_HUMIDITY_NOK_Mpv)); + M_MEMCOPY((g_ausPREC_HUMIDITY_OK), (c_ausPREC_HUMIDITY_OK_Mpv)); + M_MEMCOPY((g_ausPREC_ENTRY_RPM), (c_ausPREC_ENTRY_RPM_Mpv)); + M_MEMCOPY((g_ausPREC_EXIT_RPM), (c_ausPREC_EXIT_RPM_Mpv)); + M_MEMCOPY((g_ausPREC_COMP_SPD_1), (c_ausPREC_COMP_SPD_1_Mpv)); + M_MEMCOPY((g_aucPREC_OSA_SUMMER_1), (c_aucPREC_OSA_SUMMER_1_Mpv)); + M_MEMCOPY((g_aucPREC_REC_SUMMER_1), (c_aucPREC_REC_SUMMER_1_Mpv)); + M_MEMCOPY((g_assPREC_EVA_DIFF_FB_TG_F), (c_assPREC_EVA_DIFF_FB_TG_F_Mpv)); + M_MEMCOPY((g_aucPREC_OSA_SUMMER_2), (c_aucPREC_OSA_SUMMER_2_Mpv)); + M_MEMCOPY((g_aucPREC_REC_SUMMER_2), (c_aucPREC_REC_SUMMER_2_Mpv)); + M_MEMCOPY((g_aucPREC_EVA_DIFF), (c_aucPREC_EVA_DIFF_Mpv)); + g_ucPREC_OSA_SUMMER_3 = c_ucPREC_OSA_SUMMER_3_Mpv; + g_ucPREC_REC_SUMMER_3 = c_ucPREC_REC_SUMMER_3_Mpv; +/* ------------------------------------------AutoRec : End*/ + M_MEMCOPY((g_ausFLOW_FR_VE2VALVE), (c_ausFLOW_FR_VE2VALVE_Mpv)); + M_MEMCOPY((g_ausFLOW_FR_BIVALVE), (c_ausFLOW_FR_BIVALVE_Mpv)); + M_MEMCOPY((g_ausFLOW_FR_BI2VALVE), (c_ausFLOW_FR_BI2VALVE_Mpv)); + M_MEMCOPY((g_ausFLOW_FR_AF2VALVE), (c_ausFLOW_FR_AF2VALVE_Mpv)); + M_MEMCOPY((g_ausFLOW_FR_AF2VALVE_SUMMER), (c_ausFLOW_FR_AF2VALVE_SUMMER_Mpv)); + M_MEMCOPY((g_ausFLOW_FR_FO2VALVE), (c_ausFLOW_FR_FO2VALVE_Mpv)); + M_MEMCOPY((g_ausFLOW_FR_FD2VALVE), (c_ausFLOW_FR_FD2VALVE_Mpv)); + M_MEMCOPY((g_ausFLOW_FR_DE2VALVE), (c_ausFLOW_FR_DE2VALVE_Mpv)); + M_MEMCOPY((g_ausFLOW_FR_TR2VALVE), (c_ausFLOW_FR_TR2VALVE_Mpv)); + M_MEMCOPY((g_ausFLOW_FR_HI2VALVE), (c_ausFLOW_FR_HI2VALVE_Mpv)); + M_MEMCOPY((g_ausFLOW_FR_BIVALVE_MANUAL), (c_ausFLOW_FR_BIVALVE_MANUAL_Mpv)); + M_MEMCOPY((g_ausFLOW_RE_VENT), (c_ausFLOW_RE_VENT_Mpv)); + M_MEMCOPY((g_ausFLOW_RE_BI2VALVE), (c_ausFLOW_RE_BI2VALVE_Mpv)); + M_MEMCOPY((g_ausFLOW_RE_FO2VALVE), (c_ausFLOW_RE_FO2VALVE_Mpv)); + M_MEMCOPY((g_ausFLOW_RE_VENT_2), (c_ausFLOW_RE_VENT_2_Mpv)); + M_MEMCOPY((g_ausFLOW_RE_BI2VALVE_2), (c_ausFLOW_RE_BI2VALVE_2_Mpv)); + M_MEMCOPY((g_ausFLOW_RE_VENT_3), (c_ausFLOW_RE_VENT_3_Mpv)); + M_MEMCOPY((g_ausFLOW_RE_BI2VALVE_3), (c_ausFLOW_RE_BI2VALVE_3_Mpv)); + M_MEMCOPY((g_ausFLOW_RE_VENT_MANUAL), (c_ausFLOW_RE_VENT_MANUAL_Mpv)); + M_MEMCOPY((g_ausFLOW_RE_BI2VALVE_MANUAL), (c_ausFLOW_RE_BI2VALVE_MANUAL_Mpv)); +/* ------------------------------------------Flow Control Valve: End*/ + M_MEMCOPY((g_assFLOW_BI_AMB_TGT), (c_assFLOW_BI_AMB_TGT_Mpv)); + M_MEMCOPY((g_aucFLOW_BI_VENT_PLUS), (c_aucFLOW_BI_VENT_PLUS_Mpv)); + M_MEMCOPY((g_assFLOW_BI_TEMP_TGT), (c_assFLOW_BI_TEMP_TGT_Mpv)); + M_MEMCOPY((g_aucFLOW_BI_FOOT_PLUS), (c_aucFLOW_BI_FOOT_PLUS_Mpv)); + M_MEMCOPY((g_aucFLOW_BI_VENT_VALVE_MAX), (c_aucFLOW_BI_VENT_VALVE_MAX_Mpv)); + M_MEMCOPY((g_aucFLOW_BI_FOOT_VALVE_MAX), (c_aucFLOW_BI_FOOT_VALVE_MAX_Mpv)); + M_MEMCOPY((g_aucFLOW_BI_VENT_VALVE_MIN), (c_aucFLOW_BI_VENT_VALVE_MIN_Mpv)); + M_MEMCOPY((g_aucFLOW_BI_FOOT_VALVE_MIN), (c_aucFLOW_BI_FOOT_VALVE_MIN_Mpv)); +/* ------------------------------------------Bi 2 level conditions: End*/ + M_MEMCOPY((g_assFLOW_B2I_AMB_TGT), (c_assFLOW_B2I_AMB_TGT_Mpv)); + M_MEMCOPY((g_aucFLOW_BI2_VENT_PLUS), (c_aucFLOW_BI2_VENT_PLUS_Mpv)); + M_MEMCOPY((g_assFLOW_BI2_TEMP_TGT), (c_assFLOW_BI2_TEMP_TGT_Mpv)); + M_MEMCOPY((g_aucFLOW_BI2_FOOT_PLUS), (c_aucFLOW_BI2_FOOT_PLUS_Mpv)); + M_MEMCOPY((g_aucFLOW_BI2_VENT_VALVE_MAX), (c_aucFLOW_BI2_VENT_VALVE_MAX_Mpv)); + M_MEMCOPY((g_aucFLOW_BI2_FOOT_VALVE_MAX), (c_aucFLOW_BI2_FOOT_VALVE_MAX_Mpv)); + M_MEMCOPY((g_aucFLOW_BI2_VENT_VALVE_MIN), (c_aucFLOW_BI2_VENT_VALVE_MIN_Mpv)); + M_MEMCOPY((g_aucFLOW_BI2_FOOT_VALVE_MIN), (c_aucFLOW_BI2_FOOT_VALVE_MIN_Mpv)); +/* ------------------------------------------AF level conditions: End*/ + M_MEMCOPY((g_assFLOW_AF_AMB_TGT), (c_assFLOW_AF_AMB_TGT_Mpv)); + M_MEMCOPY((g_aucFLOW_AF_VENT_PLUS), (c_aucFLOW_AF_VENT_PLUS_Mpv)); + M_MEMCOPY((g_aucFLOW_AF_BLR_AF_TGT), (c_aucFLOW_AF_BLR_AF_TGT_Mpv)); + M_MEMCOPY((g_aucFLOW_AF_FOOT_PLUS), (c_aucFLOW_AF_FOOT_PLUS_Mpv)); + M_MEMCOPY((g_aucFLOW_AF_VENT_VALVE_MAX), (c_aucFLOW_AF_VENT_VALVE_MAX_Mpv)); + M_MEMCOPY((g_aucFLOW_AF_FOOT_VALVE_MAX), (c_aucFLOW_AF_FOOT_VALVE_MAX_Mpv)); +/* ------------------------------------------AF level conditions: End*/ + M_MEMCOPY((g_assFLOW_AFSM_AMB_TGT), (c_assFLOW_AFSM_AMB_TGT_Mpv)); + M_MEMCOPY((g_aucFLOW_AFSM_VENT_PLUS), (c_aucFLOW_AFSM_VENT_PLUS_Mpv)); + M_MEMCOPY((g_assFLOW_AFSM_TEMP_TGT), (c_assFLOW_AFSM_TEMP_TGT_Mpv)); + M_MEMCOPY((g_aucFLOW_AFSM_FOOT_PLUS), (c_aucFLOW_AFSM_FOOT_PLUS_Mpv)); + M_MEMCOPY((g_aucFLOW_AFSM_VENT_VALVE_MAX), (c_aucFLOW_AFSM_VENT_VALVE_MAX_Mpv)); + M_MEMCOPY((g_aucFLOW_AFSM_FOOT_VALVE_MAX), (c_aucFLOW_AFSM_FOOT_VALVE_MAX_Mpv)); +/* ------------------------------------------AF_summer level conditions: End*/ + M_MEMCOPY((g_aucMODE_INDEX), (c_aucMODE_INDEX_Mpv)); + M_MEMCOPY((g_assFOOT_STEP_DUCT_TGT), (c_assFOOT_STEP_DUCT_TGT_Mpv)); + M_MEMCOPY((g_assBLR_FOOT_IND), (c_assBLR_FOOT_IND_Mpv)); + M_MEMCOPY((g_ascFOOT_STEP_VALVE_P1), (c_ascFOOT_STEP_VALVE_P1_Mpv)); + M_MEMCOPY((g_ascFOOT_STEP_VALVE_P2), (c_ascFOOT_STEP_VALVE_P2_Mpv)); + M_MEMCOPY((g_ascFOOT_STEP_VALVE_P3), (c_ascFOOT_STEP_VALVE_P3_Mpv)); + M_MEMCOPY((g_ascFOOT_STEP_VALVE_M1), (c_ascFOOT_STEP_VALVE_M1_Mpv)); + M_MEMCOPY((g_ascFOOT_STEP_VALVE_M2), (c_ascFOOT_STEP_VALVE_M2_Mpv)); + M_MEMCOPY((g_ascFOOT_STEP_VALVE_M3), (c_ascFOOT_STEP_VALVE_M3_Mpv)); + M_MEMCOPY((g_assFOOT_STEP_BLR_P1), (c_assFOOT_STEP_BLR_P1_Mpv)); + M_MEMCOPY((g_assFOOT_STEP_BLR_P2), (c_assFOOT_STEP_BLR_P2_Mpv)); + M_MEMCOPY((g_assFOOT_STEP_BLR_P3), (c_assFOOT_STEP_BLR_P3_Mpv)); + M_MEMCOPY((g_assFOOT_STEP_BLR_M1), (c_assFOOT_STEP_BLR_M1_Mpv)); + M_MEMCOPY((g_assFOOT_STEP_BLR_M2), (c_assFOOT_STEP_BLR_M2_Mpv)); + M_MEMCOPY((g_assFOOT_STEP_BLR_M3), (c_assFOOT_STEP_BLR_M3_Mpv)); +/* ------------------------------------------Individual foot temperature: End*/ + M_MEMCOPY((g_aucREAR_FOOT_VALVE_AMB_LV2), (c_aucREAR_FOOT_VALVE_AMB_LV2_Mpv)); + M_MEMCOPY((g_aucREAR_FOOT_VALVE_AMB_LV3), (c_aucREAR_FOOT_VALVE_AMB_LV3_Mpv)); + M_MEMCOPY((g_aucREAR_FOOT_VALVE_AMB_LV4), (c_aucREAR_FOOT_VALVE_AMB_LV4_Mpv)); +/* ------------------------------------------Blowing foots from Rear HVAC: End*/ + M_MEMCOPY((g_ausFLOW_FR_VE2BLR_AF), (c_ausFLOW_FR_VE2BLR_AF_Mpv)); + M_MEMCOPY((g_ausFLOW_FR_BIVALVE_AF), (c_ausFLOW_FR_BIVALVE_AF_Mpv)); + M_MEMCOPY((g_ausFLOW_FR_BI2BLR_AF), (c_ausFLOW_FR_BI2BLR_AF_Mpv)); + M_MEMCOPY((g_ausFLOW_FR_FO2BLR_AF), (c_ausFLOW_FR_FO2BLR_AF_Mpv)); + M_MEMCOPY((g_ausFLOW_FR_AF2VALVE_AF), (c_ausFLOW_FR_AF2VALVE_AF_Mpv)); + M_MEMCOPY((g_ausFLOW_FR_AF2VALVE_SUMMER_AF), (c_ausFLOW_FR_AF2VALVE_SUMMER_AF_Mpv)); + M_MEMCOPY((g_ausFLOW_FR_FD2BLR_AF), (c_ausFLOW_FR_FD2BLR_AF_Mpv)); + M_MEMCOPY((g_ausFLOW_FR_DE2BLR_AF), (c_ausFLOW_FR_DE2BLR_AF_Mpv)); + M_MEMCOPY((g_ausFLOW_FR_TR2BLR_AF), (c_ausFLOW_FR_TR2BLR_AF_Mpv)); + M_MEMCOPY((g_ausFLOW_FR_HI2BLR_AF), (c_ausFLOW_FR_HI2BLR_AF_Mpv)); + M_MEMCOPY((g_ausFLOW_RE_VE2BLR_AF), (c_ausFLOW_RE_VE2BLR_AF_Mpv)); + M_MEMCOPY((g_ausFLOW_RE_BI2BLR_AF), (c_ausFLOW_RE_BI2BLR_AF_Mpv)); + M_MEMCOPY((g_ausFLOW_RE_FO2BLR_AF), (c_ausFLOW_RE_FO2BLR_AF_Mpv)); +/* ------------------------------------------Flow Control AF: End*/ + M_MEMCOPY((g_ascAUTO_STEP_AF_F), (c_ascAUTO_STEP_AF_F_Mpv)); + M_MEMCOPY((g_ascAUTO_STEP_AF_R), (c_ascAUTO_STEP_AF_R_Mpv)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_U_F_LV0_1), (c_assAUTO_STEP_DUCT_TG_U_F_LV0_1_Mpv)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_U_F_LV2_3), (c_assAUTO_STEP_DUCT_TG_U_F_LV2_3_Mpv)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_U_F_LV4_5), (c_assAUTO_STEP_DUCT_TG_U_F_LV4_5_Mpv)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_L_F_LV0_1), (c_assAUTO_STEP_DUCT_TG_L_F_LV0_1_Mpv)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_L_F_LV2_3), (c_assAUTO_STEP_DUCT_TG_L_F_LV2_3_Mpv)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_L_F_LV4_5), (c_assAUTO_STEP_DUCT_TG_L_F_LV4_5_Mpv)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_R_LV0_1), (c_assAUTO_STEP_DUCT_TG_R_LV0_1_Mpv)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_R_LV2_3), (c_assAUTO_STEP_DUCT_TG_R_LV2_3_Mpv)); + M_MEMCOPY((g_assAUTO_STEP_DUCT_TG_R_LV4_5), (c_assAUTO_STEP_DUCT_TG_R_LV4_5_Mpv)); +/* ------------------------------------------5 AUTO mode: End*/ + M_MEMCOPY((g_ausVALVE_SPACE), (c_ausVALVE_SPACE_Mpv)); + M_MEMCOPY((g_aucVALVE_SECTION_S1_F_SIDE_VENT), (c_aucVALVE_SECTION_S1_F_SIDE_VENT_Mpv)); + M_MEMCOPY((g_aucVALVE_SECTION_S1_F_CENT_VENT), (c_aucVALVE_SECTION_S1_F_CENT_VENT_Mpv)); + M_MEMCOPY((g_aucVALVE_SECTION_S1_F_DRIVER_FOOT), (c_aucVALVE_SECTION_S1_F_DRIVER_FOOT_Mpv)); + M_MEMCOPY((g_aucVALVE_SECTION_S1_F_RIGHT_PASS), (c_aucVALVE_SECTION_S1_F_RIGHT_PASS_Mpv)); + M_MEMCOPY((g_aucBLR_SPD_V1_1_F), (c_aucBLR_SPD_V1_1_F_Mpv)); + M_MEMCOPY((g_aucBLR_SPD_K2_1_F_SIDE_VENT), (c_aucBLR_SPD_K2_1_F_SIDE_VENT_Mpv)); + M_MEMCOPY((g_aucBLR_SPD_K2_2_F_CENT_VENT), (c_aucBLR_SPD_K2_2_F_CENT_VENT_Mpv)); + M_MEMCOPY((g_aucBLR_SPD_K2_3_F_DRIVER_FOOT), (c_aucBLR_SPD_K2_3_F_DRIVER_FOOT_Mpv)); + M_MEMCOPY((g_aucBLR_SPD_K2_4_F_RIGHT_PASS), (c_aucBLR_SPD_K2_4_F_RIGHT_PASS_Mpv)); + M_MEMCOPY((g_ausVALVE_VEH_SPD), (c_ausVALVE_VEH_SPD_Mpv)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_SIDE_VENT), (c_aucVALVE_VEH_SPD_SIDE_VENT_Mpv)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_SIDE_BI), (c_aucVALVE_VEH_SPD_SIDE_BI_Mpv)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_SIDE_AFOOT), (c_aucVALVE_VEH_SPD_SIDE_AFOOT_Mpv)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_CNET_VENT), (c_aucVALVE_VEH_SPD_CNET_VENT_Mpv)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_CENT_BI), (c_aucVALVE_VEH_SPD_CENT_BI_Mpv)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_CENT_AFOOT), (c_aucVALVE_VEH_SPD_CENT_AFOOT_Mpv)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_FOOT_BI), (c_aucVALVE_VEH_SPD_FOOT_BI_Mpv)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_FOOT_AFOOT), (c_aucVALVE_VEH_SPD_FOOT_AFOOT_Mpv)); + M_MEMCOPY((g_aucVALVE_VEH_SPD_2FOOT), (c_aucVALVE_VEH_SPD_2FOOT_Mpv)); + M_MEMCOPY((g_aucBLR_SPD_VEH_SPD_V1_3), (c_aucBLR_SPD_VEH_SPD_V1_3_Mpv)); + M_MEMCOPY((g_aucFRONT_SIDE_DRS_PERCENT), (c_aucFRONT_SIDE_DRS_PERCENT_Mpv)); + M_MEMCOPY((g_aucFRONT_CENT_DRS_PERCENT), (c_aucFRONT_CENT_DRS_PERCENT_Mpv)); +/* ------------------------------------------Different blower speed FRONT MODE: End*/ + M_MEMCOPY((g_aucVALVE_S1_R_BIPILLAR), (c_aucVALVE_S1_R_BIPILLAR_Mpv)); + M_MEMCOPY((g_aucVALVE_S1_R_CENT_VENT), (c_aucVALVE_S1_R_CENT_VENT_Mpv)); + M_MEMCOPY((g_aucVALVE_S1_R_FOOT), (c_aucVALVE_S1_R_FOOT_Mpv)); + M_MEMCOPY((g_aucVALVE_PERC_R_BIPILLAR), (c_aucVALVE_PERC_R_BIPILLAR_Mpv)); + M_MEMCOPY((g_aucVALVE_PERC_R_CENT_VENT), (c_aucVALVE_PERC_R_CENT_VENT_Mpv)); + M_MEMCOPY((g_aucVALVE_PERC_R_FOOT), (c_aucVALVE_PERC_R_FOOT_Mpv)); + M_MEMCOPY((g_aucBLR_SPD_V1_1_R), (c_aucBLR_SPD_V1_1_R_Mpv)); + M_MEMCOPY((g_aucREAR_CEN_MIN_VALUE_BY_DRS_ZERO), (c_aucREAR_CEN_MIN_VALUE_BY_DRS_ZERO_Mpv)); + M_MEMCOPY((g_aucBLR_SPD_K2_1_R_BIPILLAR_MIN), (c_aucBLR_SPD_K2_1_R_BIPILLAR_MIN_Mpv)); + M_MEMCOPY((g_aucBLR_SPD_K2_2_R_CENT_VENT_MIN), (c_aucBLR_SPD_K2_2_R_CENT_VENT_MIN_Mpv)); + M_MEMCOPY((g_aucBLR_SPD_K2_3_R_FOOT_MIN), (c_aucBLR_SPD_K2_3_R_FOOT_MIN_Mpv)); + M_MEMCOPY((g_aucBLR_SPD_K2_1_R_BIPILLAR_MAX), (c_aucBLR_SPD_K2_1_R_BIPILLAR_MAX_Mpv)); + M_MEMCOPY((g_aucBLR_SPD_K2_2_R_CENT_VENTR_MAX), (c_aucBLR_SPD_K2_2_R_CENT_VENTR_MAX_Mpv)); + M_MEMCOPY((g_aucBLR_SPD_K2_3_R_FOOTR_MAX), (c_aucBLR_SPD_K2_3_R_FOOTR_MAX_Mpv)); + M_MEMCOPY((g_aucREAR_SIDE_DRS_PERCENT_VALVE), (c_aucREAR_SIDE_DRS_PERCENT_VALVE_Mpv)); + M_MEMCOPY((g_aucREAR_CENT_DRS_PERCENT_VALVE), (c_aucREAR_CENT_DRS_PERCENT_VALVE_Mpv)); + M_MEMCOPY((g_aucREAR_SIDE_DRS_PERCENT_AF), (c_aucREAR_SIDE_DRS_PERCENT_AF_Mpv)); + M_MEMCOPY((g_aucREAR_CENT_DRS_PERCENT_AF), (c_aucREAR_CENT_DRS_PERCENT_AF_Mpv)); +/* ------------------------------------------Different blower speed REAR MODE: End*/ + M_MEMCOPY((g_ausMIN_PWM), (c_ausMIN_PWM_Mpv)); +/* ------------------------------------------MinPWM: End*/ + M_MEMCOPY((g_assSTART_ENTER_COOLANT), (c_assSTART_ENTER_COOLANT_Mpv)); + M_MEMCOPY((g_assSTART_COOLANT_STEP0_TO_1), (c_assSTART_COOLANT_STEP0_TO_1_Mpv)); + M_MEMCOPY((g_assSTART_COOLANT_TO_STEP2), (c_assSTART_COOLANT_TO_STEP2_Mpv)); + M_MEMCOPY((g_assSTART_COOLANT_STEP1_BLR_F), (c_assSTART_COOLANT_STEP1_BLR_F_Mpv)); + M_MEMCOPY((g_assSTART_COOLANT_STEP1_BLR_R), (c_assSTART_COOLANT_STEP1_BLR_R_Mpv)); + M_MEMCOPY((g_assSTART_ENTER_INCAR), (c_assSTART_ENTER_INCAR_Mpv)); + M_MEMCOPY((g_ausSTART_ENTER_SETTEMP), (c_ausSTART_ENTER_SETTEMP_Mpv)); + M_MEMCOPY((g_aucSTART_INCAR_FLT_UP), (c_aucSTART_INCAR_FLT_UP_Mpv)); + M_MEMCOPY((g_aucSTART_INCAR_FLT_DN), (c_aucSTART_INCAR_FLT_DN_Mpv)); + M_MEMCOPY((g_aucSTART_VALVE_IDX_STEP1), (c_aucSTART_VALVE_IDX_STEP1_Mpv)); + M_MEMCOPY((g_aucSTART_AUTODEMIST2_STEP2), (c_aucSTART_AUTODEMIST2_STEP2_Mpv)); + M_MEMCOPY((g_aucSTART_ELEC_WINDOW), (c_aucSTART_ELEC_WINDOW_Mpv)); + M_MEMCOPY((g_ausSTART_BLR_AF_STEP12_F), (c_ausSTART_BLR_AF_STEP12_F_Mpv)); + M_MEMCOPY((g_ausSTART_BLR_AF_STEP12_R), (c_ausSTART_BLR_AF_STEP12_R_Mpv)); + M_MEMCOPY((g_ausSTART_BLR_SPD_STEP2_F), (c_ausSTART_BLR_SPD_STEP2_F_Mpv)); + M_MEMCOPY((g_ausSTART_BLR_SPD_STEP2_R), (c_ausSTART_BLR_SPD_STEP2_R_Mpv)); + M_MEMCOPY((g_aucSTART_DUCT_TGT_STEP2_FX_U), (c_aucSTART_DUCT_TGT_STEP2_FX_U_Mpv)); + M_MEMCOPY((g_aucSTART_DUCT_TGT_STEP2_FX_L), (c_aucSTART_DUCT_TGT_STEP2_FX_L_Mpv)); + M_MEMCOPY((g_aucSTART_DUCT_TGT_STEP2_RX), (c_aucSTART_DUCT_TGT_STEP2_RX_Mpv)); + M_MEMCOPY((g_aucSTART_VALVE_CHANGE_SPD_F), (c_aucSTART_VALVE_CHANGE_SPD_F_Mpv)); + M_MEMCOPY((g_aucSTART_VALVE_CHANGE_SPD_R), (c_aucSTART_VALVE_CHANGE_SPD_R_Mpv)); + M_MEMCOPY((g_ausSTART_TIME_STEP1_TO_2), (c_ausSTART_TIME_STEP1_TO_2_Mpv)); + M_MEMCOPY((g_ausSTART_TIME_STEP2_TO_3), (c_ausSTART_TIME_STEP2_TO_3_Mpv)); + M_MEMCOPY((g_assSTART_INCAR_STEP1_TO_2), (c_assSTART_INCAR_STEP1_TO_2_Mpv)); + M_MEMCOPY((g_assSTART_INCAR_STEP2_TO_3), (c_assSTART_INCAR_STEP2_TO_3_Mpv)); + M_MEMCOPY((g_aucSTART_3WAY_OPEN), (c_aucSTART_3WAY_OPEN_Mpv)); + M_MEMCOPY((g_aucSTART_2WAY_OPEN), (c_aucSTART_2WAY_OPEN_Mpv)); + M_MEMCOPY((g_aucSTART_TXV_F), (c_aucSTART_TXV_F_Mpv)); + M_MEMCOPY((g_aucSTART_TXV_R), (c_aucSTART_TXV_R_Mpv)); +/* ------------------------------------------Start control: End*/ + M_MEMCOPY((g_assFAILURE_AMB_TEMP), (c_assFAILURE_AMB_TEMP_Mpv)); + M_MEMCOPY((g_assAC_PRESSURE_LOW_HYS_UP), (c_assAC_PRESSURE_LOW_HYS_UP_Mpv)); + M_MEMCOPY((g_assAC_PRESSURE_LOW_HYS_DN), (c_assAC_PRESSURE_LOW_HYS_DN_Mpv)); + M_MEMCOPY((g_assAC_LOW_AMB_F), (c_assAC_LOW_AMB_F_Mpv)); + M_MEMCOPY((g_assAC_CUT_OFF_AMB_F), (c_assAC_CUT_OFF_AMB_F_Mpv)); + M_MEMCOPY((g_assAC_WINTER_TXV_DEWPOINT), (c_assAC_WINTER_TXV_DEWPOINT_Mpv)); + M_MEMCOPY((g_assAC_CUT_OFF_AMB_R), (c_assAC_CUT_OFF_AMB_R_Mpv)); + M_MEMCOPY((g_assEVA_TG_AMB_F), (c_assEVA_TG_AMB_F_Mpv)); + M_MEMCOPY((g_assEVA_TG_AMB_R), (c_assEVA_TG_AMB_R_Mpv)); + g_ucAC_EXTRA_RPM = c_ucAC_EXTRA_RPM_Mpv; + M_MEMCOPY((g_assAC_EVA_LV_SHUT_OFF), (c_assAC_EVA_LV_SHUT_OFF_Mpv)); + M_MEMCOPY((g_assAC_PRESSURE_HYS_HI_ENG_ON), (c_assAC_PRESSURE_HYS_HI_ENG_ON_Mpv)); + g_usCMP_MAX_ENG_OFF = c_usCMP_MAX_ENG_OFF_Mpv; + g_ucFAN_MAX_ENG_OFF = c_ucFAN_MAX_ENG_OFF_Mpv; + g_ssAC_WINTER_TXV_HYST = c_ssAC_WINTER_TXV_HYST_Mpv; + M_MEMCOPY((g_aucAC_PRESSURE_HYS_HI_ENG_OFF), (c_aucAC_PRESSURE_HYS_HI_ENG_OFF_Mpv)); + M_MEMCOPY((g_ausCMP_RPM_RESONANCE), (c_ausCMP_RPM_RESONANCE_Mpv)); +/* ------------------------------------------A/C Control Pressure : End*/ + M_MEMCOPY((g_assPRESSURE_TO_FAN_X), (c_assPRESSURE_TO_FAN_X_Mpv)); + M_MEMCOPY((g_aucPRESSURE_TO_FAN_Y), (c_aucPRESSURE_TO_FAN_Y_Mpv)); +/* ------------------------------------------CoolingFan: End*/ + g_ssREST_BATT = c_ssREST_BATT_Mpv; + g_ssRESTW_AMB = c_ssRESTW_AMB_Mpv; + M_MEMCOPY((g_assRESTW_WATER), (c_assRESTW_WATER_Mpv)); + g_usRESTW_READYEXPIRETIME = c_usRESTW_READYEXPIRETIME_Mpv; + M_MEMCOPY((g_aucRESTW_MODE), (c_aucRESTW_MODE_Mpv)); + g_usRESTW_TIMEOUTTIME = c_usRESTW_TIMEOUTTIME_Mpv; + g_ucRESTW_BLRSTEP = c_ucRESTW_BLRSTEP_Mpv; + g_ssRESTS_AMB = c_ssRESTS_AMB_Mpv; + g_uctRESTS_READYEXPIRETIME = c_uctRESTS_READYEXPIRETIME_Mpv; + M_MEMCOPY((g_aucRESTS_MODE), (c_aucRESTS_MODE_Mpv)); + g_usRESTS_TIMEOUTTIME = c_usRESTS_TIMEOUTTIME_Mpv; + g_ucRESTS_BLRSTEP = c_ucRESTS_BLRSTEP_Mpv; +/* ------------------------------------------Rest mode: End*/ + g_usFRESH_AIR_PURGE_ENTRY_TIME = c_usFRESH_AIR_PURGE_ENTRY_TIME_Mpv; + M_MEMCOPY((g_ausFRESH_AIR_PURGE_CHANGE_TIME), (c_ausFRESH_AIR_PURGE_CHANGE_TIME_Mpv)); +/* ------------------------------------------Purge Rec: End*/ + M_MEMCOPY((g_assMAX_DEF_U_DTG), (c_assMAX_DEF_U_DTG_Mpv)); + M_MEMCOPY((g_ausMAX_BLR_SPD), (c_ausMAX_BLR_SPD_Mpv)); +/* ------------------------------------------MAX DEF: End*/ + M_MEMCOPY((g_aucAQS_REC_LV_CO), (c_aucAQS_REC_LV_CO_Mpv)); + M_MEMCOPY((g_aucAQS_OSA_LV_CO), (c_aucAQS_OSA_LV_CO_Mpv)); + M_MEMCOPY((g_aucAQS_REC_LV_NOX), (c_aucAQS_REC_LV_NOX_Mpv)); + M_MEMCOPY((g_aucAQS_OSA_LV_NOX), (c_aucAQS_OSA_LV_NOX_Mpv)); + M_MEMCOPY((g_aucAQS_REC_LV_NH3), (c_aucAQS_REC_LV_NH3_Mpv)); + M_MEMCOPY((g_aucAQS_OSA_LV_NH3), (c_aucAQS_OSA_LV_NH3_Mpv)); + g_ucAQS_REC_ON_TIME = c_ucAQS_REC_ON_TIME_Mpv; + M_MEMCOPY((g_aucAQS_REC_ON_WAIT), (c_aucAQS_REC_ON_WAIT_Mpv)); +/* ------------------------------------------Aqs: End*/ + g_usAUTODEMIST_LV2_BLR_PLUS = c_usAUTODEMIST_LV2_BLR_PLUS_Mpv; + g_usAUTODEMIST_LV3_BLR_PLUS = c_usAUTODEMIST_LV3_BLR_PLUS_Mpv; + M_MEMCOPY((g_assAUTODEMIST_OFFSET_AMB_TEMP), (c_assAUTODEMIST_OFFSET_AMB_TEMP_Mpv)); + M_MEMCOPY((g_assAUTODEMIST_OFFSET_VENT_TEMP), (c_assAUTODEMIST_OFFSET_VENT_TEMP_Mpv)); + M_MEMCOPY((g_assAUTODEMIST_STEP_UP), (c_assAUTODEMIST_STEP_UP_Mpv)); + M_MEMCOPY((g_assAUTODEMIST_STEP_DN), (c_assAUTODEMIST_STEP_DN_Mpv)); + M_MEMCOPY((g_assAUTODEMIST_WINTER), (c_assAUTODEMIST_WINTER_Mpv)); +/* ------------------------------------------Auto Demist: End*/ + g_ssAUTODEMIST_ELEC_AMB_ENTRY = c_ssAUTODEMIST_ELEC_AMB_ENTRY_Mpv; + M_MEMCOPY((g_assAUTODEMIST_ELEC_WINDSHELD_TEMP), (c_assAUTODEMIST_ELEC_WINDSHELD_TEMP_Mpv)); +/* ------------------------------------------Electric AutoDemist: End*/ + g_ssAMBFILT_WATER = c_ssAMBFILT_WATER_Mpv; + M_MEMCOPY((g_aucAMBFILT_H_CNT), (c_aucAMBFILT_H_CNT_Mpv)); + g_ssAMB_FAILSAFE = c_ssAMB_FAILSAFE_Mpv; + g_ssAMBKEEP_KAT = c_ssAMBKEEP_KAT_Mpv; + g_ssAMBKEEP_KAT_PLUS = c_ssAMBKEEP_KAT_PLUS_Mpv; + g_ssAMBKEEP_WATER = c_ssAMBKEEP_WATER_Mpv; + M_MEMCOPY((g_aucAMBRATE_RISING), (c_aucAMBRATE_RISING_Mpv)); + M_MEMCOPY((g_aucAMBRATE_FALLING), (c_aucAMBRATE_FALLING_Mpv)); + M_MEMCOPY((g_aucAMBRATE_RISING_DIFF), (c_aucAMBRATE_RISING_DIFF_Mpv)); + M_MEMCOPY((g_aucAMBRATE_FALLING_DIFF), (c_aucAMBRATE_FALLING_DIFF_Mpv)); +/* ------------------------------------------Ambient: End*/ + M_MEMCOPY((g_ausINCARRATE_RISING_F), (c_ausINCARRATE_RISING_F_Mpv)); + M_MEMCOPY((g_ausINCARRATE_FALLING_F), (c_ausINCARRATE_FALLING_F_Mpv)); + M_MEMCOPY((g_ausINCARRATE_RISING_DIFF_F), (c_ausINCARRATE_RISING_DIFF_F_Mpv)); + M_MEMCOPY((g_ausINCARRATE_FALLING_DIFF_F), (c_ausINCARRATE_FALLING_DIFF_F_Mpv)); + M_MEMCOPY((g_ausINCARRATE_RISING_R), (c_ausINCARRATE_RISING_R_Mpv)); + M_MEMCOPY((g_ausINCARRATE_FALLING_R), (c_ausINCARRATE_FALLING_R_Mpv)); + M_MEMCOPY((g_ausINCARRATE_RISING_DIFF_R), (c_ausINCARRATE_RISING_DIFF_R_Mpv)); + M_MEMCOPY((g_ausINCARRATE_FALLING_DIFF_R), (c_ausINCARRATE_FALLING_DIFF_R_Mpv)); +/* ------------------------------------------Incar: End*/ + M_MEMCOPY((g_ausSUNRATE_RISING), (c_ausSUNRATE_RISING_Mpv)); + M_MEMCOPY((g_ausSUNRATE_FALLING), (c_ausSUNRATE_FALLING_Mpv)); +/* ------------------------------------------Sun: End*/ + M_MEMCOPY((g_ausAMB_LV_CHANGE_UNIT), (c_ausAMB_LV_CHANGE_UNIT_Mpv)); + M_MEMCOPY((g_aucAMB_LV_CHANGE_SEC), (c_aucAMB_LV_CHANGE_SEC_Mpv)); +/* ------------------------------------------Level Chage: End*/ + g_ssTHREEWAY_WATER = c_ssTHREEWAY_WATER_Mpv; + M_MEMCOPY((g_assTHREEWAY_DUCT_TGT_R), (c_assTHREEWAY_DUCT_TGT_R_Mpv)); + M_MEMCOPY((g_aucTHEREEWAY_EXPIRING), (c_aucTHEREEWAY_EXPIRING_Mpv)); +/* ------------------------------------------Three way: End*/ + M_MEMCOPY((g_assTWOWAY_REAR_DUCTTGT_R), (c_assTWOWAY_REAR_DUCTTGT_R_Mpv)); + M_MEMCOPY((g_aucTWOWAY_EXPIRING), (c_aucTWOWAY_EXPIRING_Mpv)); +/* ------------------------------------------two-way: End*/ + M_MEMCOPY((g_aucACT_HOM_SPD_FL_CH0), (c_aucACT_HOM_SPD_FL_CH0_Mpv)); + M_MEMCOPY((g_aucACT_HOM_SPD_FR_CH1), (c_aucACT_HOM_SPD_FR_CH1_Mpv)); + M_MEMCOPY((g_aucACT_HOM_SPD_R_CH2), (c_aucACT_HOM_SPD_R_CH2_Mpv)); + M_MEMCOPY((g_aucACT_HOM_SPD_R_EX_CH2), (c_aucACT_HOM_SPD_R_EX_CH2_Mpv)); + M_MEMCOPY((g_aucACT_MOV_SPD_FL_CH0), (c_aucACT_MOV_SPD_FL_CH0_Mpv)); + M_MEMCOPY((g_aucACT_MOV_SPD_FR_CH1), (c_aucACT_MOV_SPD_FR_CH1_Mpv)); + M_MEMCOPY((g_aucACT_MOV_SPD_R_CH2), (c_aucACT_MOV_SPD_R_CH2_Mpv)); + M_MEMCOPY((g_aucACT_MOV_SPD_R_EX_CH2), (c_aucACT_MOV_SPD_R_EX_CH2_Mpv)); +/* ------------------------------------------Actuator Homing: End*/ + M_MEMCOPY((g_assHI_MODE_ENG_TMEP), (c_assHI_MODE_ENG_TMEP_Mpv)); + M_MEMCOPY((g_aucHI_MODE_BLR_STEP_STS), (c_aucHI_MODE_BLR_STEP_STS_Mpv)); +/* ------------------------------------------Hi Mode: End*/ + M_MEMCOPY((g_ausMinusAF_GlassPos_L), (c_ausMinusAF_GlassPos_L_Mpv)); + M_MEMCOPY((g_ausMinusAF_GlassPos_R), (c_ausMinusAF_GlassPos_R_Mpv)); +/* ------------------------------------------GlassPosition: End*/ + M_MEMCOPY((g_assFoot2_Lv3_Amb), (c_assFoot2_Lv3_Amb_Mpv)); + M_MEMCOPY((g_assFoot2_Lv4_Amb), (c_assFoot2_Lv4_Amb_Mpv)); + M_MEMCOPY((g_assFoot2_Lv5_Amb), (c_assFoot2_Lv5_Amb_Mpv)); + M_MEMCOPY((g_assFoot2_Lv3_DuctTgt_Plus), (c_assFoot2_Lv3_DuctTgt_Plus_Mpv)); + M_MEMCOPY((g_assFoot2_Lv4_DuctTgt_Plus), (c_assFoot2_Lv4_DuctTgt_Plus_Mpv)); + M_MEMCOPY((g_assFoot2_Lv5_DuctTgt_Plus), (c_assFoot2_Lv5_DuctTgt_Plus_Mpv)); + M_MEMCOPY((g_ausFoot2_Lv1_FrontBlr_X), (c_ausFoot2_Lv1_FrontBlr_X_Mpv)); + M_MEMCOPY((g_ausFoot2_Lv1_Foot2Act_Y), (c_ausFoot2_Lv1_Foot2Act_Y_Mpv)); + M_MEMCOPY((g_assFoot2_Lv2_Threshold_Diff), (c_assFoot2_Lv2_Threshold_Diff_Mpv)); + M_MEMCOPY((g_assFoot2_Lv3_Threshold_Diff), (c_assFoot2_Lv3_Threshold_Diff_Mpv)); +/* ------------------------------------------Foot2 Ctrl: End*/ + M_MEMCOPY((g_ausDbF_Side_Af_Bi), (c_ausDbF_Side_Af_Bi_Mpv)); + M_MEMCOPY((g_ausDbF_Side_Af_Bi2), (c_ausDbF_Side_Af_Bi2_Mpv)); + M_MEMCOPY((g_ausDbF_Side_Af_Vent), (c_ausDbF_Side_Af_Vent_Mpv)); + M_MEMCOPY((g_ausDbF_Side_Bi_Bi2), (c_ausDbF_Side_Bi_Bi2_Mpv)); + M_MEMCOPY((g_ausDbF_Side_Bi_Vent), (c_ausDbF_Side_Bi_Vent_Mpv)); + M_MEMCOPY((g_ausDbF_Side_Bi2_Vent), (c_ausDbF_Side_Bi2_Vent_Mpv)); + M_MEMCOPY((g_ausDbF_Cen_Af_Bi), (c_ausDbF_Cen_Af_Bi_Mpv)); + M_MEMCOPY((g_ausDbF_Cen_Af_Bi2), (c_ausDbF_Cen_Af_Bi2_Mpv)); + M_MEMCOPY((g_ausDbF_Cen_Af_Vent), (c_ausDbF_Cen_Af_Vent_Mpv)); + M_MEMCOPY((g_ausDbF_Cen_Bi_Bi2), (c_ausDbF_Cen_Bi_Bi2_Mpv)); + M_MEMCOPY((g_ausDbF_Cen_Bi_Vent), (c_ausDbF_Cen_Bi_Vent_Mpv)); + M_MEMCOPY((g_ausDbF_Cen_Bi2_Vent), (c_ausDbF_Cen_Bi2_Vent_Mpv)); + M_MEMCOPY((g_ausDbF_Foot_Af_Bi), (c_ausDbF_Foot_Af_Bi_Mpv)); + M_MEMCOPY((g_ausDbF_Foot_Af_Bi2), (c_ausDbF_Foot_Af_Bi2_Mpv)); + M_MEMCOPY((g_ausDbF_Foot_Af_Vent), (c_ausDbF_Foot_Af_Vent_Mpv)); + M_MEMCOPY((g_ausDbF_Foot_Bi_Bi2), (c_ausDbF_Foot_Bi_Bi2_Mpv)); + M_MEMCOPY((g_ausDbF_Foot_Bi_Vent), (c_ausDbF_Foot_Bi_Vent_Mpv)); + M_MEMCOPY((g_ausDbF_Foot_Bi2_Vent), (c_ausDbF_Foot_Bi2_Vent_Mpv)); + M_MEMCOPY((g_ausDbF_AF_Af_Bi), (c_ausDbF_AF_Af_Bi_Mpv)); + M_MEMCOPY((g_ausDbF_AF_Af_Bi2), (c_ausDbF_AF_Af_Bi2_Mpv)); + M_MEMCOPY((g_ausDbF_AF_Af_Vent), (c_ausDbF_AF_Af_Vent_Mpv)); + M_MEMCOPY((g_ausDbF_AF_Bi_Bi2), (c_ausDbF_AF_Bi_Bi2_Mpv)); + M_MEMCOPY((g_ausDbF_AF_Bi_Vent), (c_ausDbF_AF_Bi_Vent_Mpv)); + M_MEMCOPY((g_ausDbF_AF_Bi2_Vent), (c_ausDbF_AF_Bi2_Vent_Mpv)); + M_MEMCOPY((g_ausDbF_Pwm_Af_Bi), (c_ausDbF_Pwm_Af_Bi_Mpv)); + M_MEMCOPY((g_ausDbF_Pwm_Af_Bi2), (c_ausDbF_Pwm_Af_Bi2_Mpv)); + M_MEMCOPY((g_ausDbF_Pwm_Af_Vent), (c_ausDbF_Pwm_Af_Vent_Mpv)); + M_MEMCOPY((g_ausDbF_Pwm_Bi_Bi2), (c_ausDbF_Pwm_Bi_Bi2_Mpv)); + M_MEMCOPY((g_ausDbF_Pwm_Bi_Vent), (c_ausDbF_Pwm_Bi_Vent_Mpv)); + M_MEMCOPY((g_ausDbF_Pwm_Bi2_Vent), (c_ausDbF_Pwm_Bi2_Vent_Mpv)); +/* ------------------------------------------Different blower Front: End*/ + g_usAromaPwm_Min = c_usAromaPwm_Min_Mpv; + g_usAromaPwm_Max = c_usAromaPwm_Max_Mpv; +/* ------------------------------------------Aroma Limit Pwm: End*/ +/*********************************************************Cal Table End*/ + +} +/****************************************************************************** + * LOCAL FUNCTIONS + *****************************************************************************/ +/* End of Excel line : 2159 */ +/****************************************************************************** + * EOF + *****************************************************************************/ diff --git a/MODULES/HVAC_M7_DataNonVolatile/calib/Rs_Cal_4_Mpv.h b/MODULES/HVAC_M7_DataNonVolatile/calib/Rs_Cal_4_Mpv.h new file mode 100644 index 0000000..b96acc1 --- /dev/null +++ b/MODULES/HVAC_M7_DataNonVolatile/calib/Rs_Cal_4_Mpv.h @@ -0,0 +1,38 @@ +/** Doxygen: File brief + ****************************************************************************** + * @file Rs_Cal_4_Mpv.h + * @brief No brief + * @remark Generated by C:\9999\Rs_Cal_R23_ver21_SedanL.xlsm + * Generated on yyyy-mm-dd hh:mm:ss + *****************************************************************************/ +#ifndef RS_CAL_4_MPV_H__ +#define RS_CAL_4_MPV_H__ + +/****************************************************************************** + * INCLUDE FILES +*****************************************************************************/ +#include "rtwtypes.h" +#include "common.h" +#include "HVAC_preDefine.h" +#include "Rs_Cal_Base.h" + +/****************************************************************************** + * MACRO DECLARATIONS + *****************************************************************************/ +/****************************************************************************** + * GLOBAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS) + *****************************************************************************/ +/****************************************************************************** + * GLOBAL VARIABLES DECLARATIONS + *****************************************************************************/ +extern SECT_VEH_CAL_4 const tU08 c_ucCalFromRelease_Mpv; +/****************************************************************************** + * GLOBAL FUNCTIONS DECLARATIONS + *****************************************************************************/ +extern void Rs_Cal_4_Mpv(void); + +/* End of Excel line : 34 */ +#endif /*RS_CAL_4_MPV_H__*/ +/****************************************************************************** + * EOF + *****************************************************************************/ diff --git a/MODULES/HVAC_M7_DataNonVolatile/common.h b/MODULES/HVAC_M7_DataNonVolatile/common.h new file mode 100644 index 0000000..91ed46a --- /dev/null +++ b/MODULES/HVAC_M7_DataNonVolatile/common.h @@ -0,0 +1,8 @@ +// +// Created by cfif on 08.08.2025. +// + +#ifndef SIMULINK_COMMON_H +#define SIMULINK_COMMON_H + +#endif //SIMULINK_COMMON_H diff --git a/MODULES/HVAC_M7_DataNonVolatile/modular.json b/MODULES/HVAC_M7_DataNonVolatile/modular.json new file mode 100644 index 0000000..393a9c7 --- /dev/null +++ b/MODULES/HVAC_M7_DataNonVolatile/modular.json @@ -0,0 +1,12 @@ +{ + "cmake": { + "inc_dirs": [ + "./calib", + "./" + ], + "srcs": [ + ".calib/**.c", + "./**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_DataNonVolatile/rtwtypes.h b/MODULES/HVAC_M7_DataNonVolatile/rtwtypes.h new file mode 100644 index 0000000..882dfce --- /dev/null +++ b/MODULES/HVAC_M7_DataNonVolatile/rtwtypes.h @@ -0,0 +1,8 @@ +// +// Created by cfif on 08.08.2025. +// + +#ifndef SIMULINK_RTWTYPES_H +#define SIMULINK_RTWTYPES_H + +#endif //SIMULINK_RTWTYPES_H diff --git a/MODULES/HVAC_M7_DataRuntime/DataRuntime.c b/MODULES/HVAC_M7_DataRuntime/DataRuntime.c new file mode 100644 index 0000000..abdd1b7 --- /dev/null +++ b/MODULES/HVAC_M7_DataRuntime/DataRuntime.c @@ -0,0 +1,10 @@ +// +// Created by CFIF on 10.10.25. +// + +#include "DataRuntime.h" +#include "FirmwareMetadataSection.h" + +void DeviceDataRuntime_InitDefaults(tDeviceDataRuntime *env) { + +} diff --git a/MODULES/HVAC_M7_DataRuntime/DataRuntime.h b/MODULES/HVAC_M7_DataRuntime/DataRuntime.h new file mode 100644 index 0000000..844cac6 --- /dev/null +++ b/MODULES/HVAC_M7_DataRuntime/DataRuntime.h @@ -0,0 +1,16 @@ +// +// Created by CFIF on 10.10.25. +// + +#ifndef HVAC_DEVICEDATARUNTIME_H +#define HVAC_DEVICEDATARUNTIME_H + +#include +#include + +typedef struct { +} tDeviceDataRuntime; + +void DeviceDataRuntime_InitDefaults(tDeviceDataRuntime *env); + +#endif //HVAC_DEVICEDATARUNTIME_H diff --git a/MODULES/HVAC_M7_DataRuntime/modular.json b/MODULES/HVAC_M7_DataRuntime/modular.json new file mode 100644 index 0000000..0dd1901 --- /dev/null +++ b/MODULES/HVAC_M7_DataRuntime/modular.json @@ -0,0 +1,10 @@ +{ + "cmake": { + "inc_dirs": [ + "./" + ], + "srcs": [ + "./**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_DebugTesting/MainModesArbiter.c b/MODULES/HVAC_M7_DebugTesting/MainModesArbiter.c new file mode 100644 index 0000000..817166f --- /dev/null +++ b/MODULES/HVAC_M7_DebugTesting/MainModesArbiter.c @@ -0,0 +1,127 @@ +// +// Created by cfif on 05.05.23. +// +#include "MainModesArbiter_Private.h" +#include "stdio.h" +#include "fc7xxx_driver_rgm.h" +#include "HVAC_model.h" +#include "LinActuatorWork.h" +#include "StatusError.h" +#include "ADC_Temp.h" + + +const char LOG_TASK_ARB[] = "Arb"; +#define LOGGER &env->slog.logger + +void Mma_Init( + tMma *env, + tGpios *gpios, + tAdcs *adcs, + tSerialPorts *serialPorts, + tLinPorts *linPorts, + tCanPorts *canPorts, + tStorageOnFlash *flash, + tPwms *pwms, + tRtcs *rtcs +) { + env->gpios = gpios; + env->serialPorts = serialPorts; + env->linPorts = linPorts; + env->canPorts = canPorts; + env->rtcs = rtcs; + env->adcs = adcs; + env->flash = flash; + env->pwms = pwms; + + InitThreadAtrStatic(&env->thread.attr, "Mma", env->thread.controlBlock, env->thread.stack, osPriorityNormal); + env->thread.id = 0; +} + + + +void GetCanErrors(tMma *env, uint8_t canIndex) { + FLEXCAN_ErrorInfoType errorInfo; + + // Получить информацию об ошибках + FLEXCAN_ErrorType result = FLEXCAN_GetErrorInfo(canIndex, &errorInfo); + + if (result == FLEXCAN_ERROR_OK) { + // Количество ошибок приёма + uint32_t rxErrors = errorInfo.u32RxErrCnt; + uint32_t rxErrorsFast = errorInfo.u32RxErrCnt_Fast; + + // Количество ошибок передачи + uint32_t txErrors = errorInfo.u32TxErrCnt; + uint32_t txErrorsFast = errorInfo.u32TxErrCnt_Fast; + + LoggerFormatInfo(LOGGER, LOG_TASK_ARB, "RX Errors: %lu (normal), %lu (fast)\n", rxErrors, rxErrorsFast); + LoggerFormatInfo(LOGGER, LOG_TASK_ARB, "TX Errors: %lu (normal), %lu (fast)\n", txErrors, txErrorsFast); + + // Общее количество ошибок + uint32_t totalErrors = rxErrors + rxErrorsFast + txErrors + txErrorsFast; + LoggerFormatInfo(LOGGER, LOG_TASK_ARB, "Total errors: %lu\n", totalErrors); + } +} + + + + +static _Noreturn void Mma_Thread(tMma *env) { + + // Запуск устройства + Mma_InitStage(env); + + env->pwms->pwmFrontIo.run(env->pwms->pwmFrontIo.env); + + env->pwms->pwmFrontIo.setActivePercent(env->pwms->pwmFrontIo.env, 0); + env->pwms->pwmRearIo.setActivePercent(env->pwms->pwmRearIo.env, 0); + env->pwms->pwmFrontReservedIo.setActivePercent(env->pwms->pwmFrontReservedIo.env, 0); + env->pwms->pwmRearReservedIo.setActivePercent(env->pwms->pwmRearReservedIo.env, 0); +/* + uint32_t timeoutPowerTrain = SystemGetMs() + 3000; + bool isNotNull = false; + while ((!isNotNull) && (timeoutPowerTrain > SystemGetMs())) { + isNotNull = get_is_NoNull_CanSpam_BCM_PowerTrain_Receiver(&env->canSpamReceiver); + SystemDelayMs(1); + } +*/ + + InitWakeupModel(&env->ModelTask); + + ModelTask_StartThread(&env->ModelTask); + + while (!env->ModelTask.isRunning) { + LoggerInfoStatic(LOGGER, LOG_TASK_ARB, "Waiting for the model to run...") + SystemDelayMs(1); + } + + + LoggerInfoStatic(LOGGER, LOG_TASK_ARB, "Model running...") + +// SMC_SetSystemMode(SMC_MODE_STANBY_3); + + for (;;) { + +// bool ST_PowerReserve = GpioPinGet(&env->gpios->power.BTS4175SGAXUMA1_PowerReserve.ST_PowerReserve); +// bool ST_ReservePower = GpioPinGet(&env->gpios->power.BTS4175SGAXUMA1_ReservePowerOutput.ST_ReservePower); + + +// GetCanErrors(env, 0); + + + SystemDelayMs(25); + GpioPinToggle(&env->gpios->led.LED_G); + SystemDelayMs(25); + + + } +} + + +void Mma_StartThread(tMma *env) { + if (!env->thread.id) { + env->thread.id = osThreadNew((osThreadFunc_t) (Mma_Thread), (void *) (env), &env->thread.attr); + } else { + osThreadResume(env->thread.id); + } +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_DebugTesting/MainModesArbiter.h b/MODULES/HVAC_M7_DebugTesting/MainModesArbiter.h new file mode 100644 index 0000000..838008d --- /dev/null +++ b/MODULES/HVAC_M7_DebugTesting/MainModesArbiter.h @@ -0,0 +1,107 @@ +// +// Created by cfif on 05.05.23. +// + +#ifndef WATER_BOX_BSD_MAINMODESARBITER_H +#define WATER_BOX_BSD_MAINMODESARBITER_H + +#include "CmsisRtosThreadUtils.h" + +//Железные интерфейсы +#include "PeripheralInterfaces.h" + +//Подсистемы +#include "PowerManagement.h" +#include "Rtcs.h" +#include "LoggerToSerialPort.h" +#include "Indication.h" +#include "CommandLines.h" +#include "DeviceStorage.h" +#include "SerialPortCan.h" +#include "CanSerialPortFrameXCP.h" +#include "CanSpamReceiver.h" +#include "CanSpamTransmitter.h" +#include "CanSpamDebugReceiver.h" +#include "CanSpamDebugTransmitter.h" +#include "Lins.h" +#include "LinActuatorTasks.h" +#include "AdcTasks.h" +#include "standby.h" +#include "Model_Task.h" +#include "HVAC_model.h" +#include "CanUds.h" +#include "DiagnosticTask.h" +#include "LinSensorTasks.h" + + +typedef struct { + // Преферийные интерфесы + tGpios *gpios; + tSerialPorts *serialPorts; + tLinPorts *linPorts; + tCanPorts *canPorts; + tLoggerToSerialPort slog; + tStorageOnFlash *flash; + tPwms *pwms; + + tCanUds canUds; + + tRtcs *rtcs; + tAdcs *adcs; + + tDeviceStorage storage; + + tPowerManagement power; + + tCommandLine cli; + + tIndication Indication; + + tCanSerialPortFrameXCP CanSerialPortFrameXCP; + + tCanSpamReceiver canSpamReceiver; + tCanSpamTransmitter canSpamTransmitter; + + tCanSpamDebugReceiver canSpamDebugReceiver; + tCanSpamDebugTransmitter canSpamDebugTransmitter; + + tLinTaskActuator linTaskActuator1; + tLinTaskActuator linTaskActuator2; + tLinTaskActuator linTaskActuator3; + + tLin4TaskSensor linTaskSensor4; + tLin5TaskSensor linTaskSensor5; + + + tAdc0Task adcTask0; + tAdc1Task adcTask1; + + tModelTask ModelTask; + + tDiagnostic Diagnostic; + + struct { + osThreadId_t id; + uint32_t stack[512]; + StaticTask_t controlBlock; + osThreadAttr_t attr; + } thread; + + +} tMma; + +void Mma_Init( + tMma *env, + tGpios *gpios, + tAdcs *adcs, + tSerialPorts *serialPorts, + tLinPorts *linPorts, + tCanPorts *canPorts, + tStorageOnFlash *flash, + tPwms *pwms, + tRtcs *rtcs +); + +void Mma_StartThread(tMma *env); + +#endif //WATER_BOX_BSD_MAINMODESARBITER_H diff --git a/MODULES/HVAC_M7_DebugTesting/MainModesArbiter_InitStage.c b/MODULES/HVAC_M7_DebugTesting/MainModesArbiter_InitStage.c new file mode 100644 index 0000000..a717e45 --- /dev/null +++ b/MODULES/HVAC_M7_DebugTesting/MainModesArbiter_InitStage.c @@ -0,0 +1,334 @@ +// +// Created by cfif on 05.05.23. +// + +#include "MainModesArbiter_Private.h" +#include "InternalFlashPage.h" +#include "StatusData.h" +#include "HardFault.h" +#include "FirmwareMetadataSection.h" +#include "HVAC_model.h" + +#define LOGGER &env->slog.logger + +const char LOG_TASK_MAIN[] = "Init"; + + +void Mma_InitComIntLog(tMma *env) { + + LoggerToSerialPort_Init( + &env->slog, + 3, + &SERIAL_PORTS.cliVirtualPortOut_Io, + &SERIAL_PORTS.SerialPortLog_IO, + &env->rtcs->rtcI0, + SERIAL_LOGGER_SHOW_TIME | SERIAL_LOGGER_SHOW_AUTHOR | SERIAL_LOGGER_SHOW_LOG_LEVEL, + 10 + ); + + LoggerInfoStatic(&env->slog.logger, LOG_TASK_MAIN, "Start logging") + +} + +const DMA_InitType dmaInitCfg = + { + .eArbitrationAlgorithm = DMA_ARBITRATION_ALGORITHM_FIXED_PRIORITY, + .bHaltOnError = false + }; + +#define CHECK_JTAG_DEBUG_ACTIVE ((CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) != 0) +#define CHECK_PARALLEL_ENABLE (((*(volatile uint32_t*)0x044000E8) & 0x0000000F) != 0x00000005) + + +static void Mma_InitSubSystems(tMma *env) { + + + DMA_Init(DMA_INSTANCE_0, &dmaInitCfg); + + // Настройка таймера реального времени + Rtcs_Init(); + time_t set_timestamp = 1768553105; + RtcSet(&env->rtcs->rtcI0, &set_timestamp); + + SerialPorts_Init(); + + Mma_InitComIntLog(env); + env->flash->nf_storage_param.logger = &env->slog.logger; + env->flash->nf_storage_calib.logger = &env->slog.logger; + + tFirmwareMetaMap *firmwareMetaMap_Boot = (tFirmwareMetaMap *) ADR_META_BOOT; + tFirmwareMetaMap *firmwareMetaMap_Main = (tFirmwareMetaMap *) ADR_META_MAIN; + + char dataTmp[10]; + memset(dataTmp, 0, sizeof(dataTmp)); + memcpy(dataTmp, firmwareMetaMap_Boot->fingerprint.testerCode, 9); + + LoggerFormatInfo(LOGGER, LOG_TASK_MAIN, "Boot: ModuleID: %d, testerCode: %s, year: 0x%02X, month: 0x%02X day: 0x%02X", + firmwareMetaMap_Boot->fingerprint.ModuleID, + dataTmp, + firmwareMetaMap_Boot->fingerprint.year, + firmwareMetaMap_Boot->fingerprint.month, + firmwareMetaMap_Boot->fingerprint.day); + + memcpy(dataTmp, firmwareMetaMap_Main->fingerprint.testerCode, 9); + + LoggerFormatInfo(LOGGER, LOG_TASK_MAIN, "Main: ModuleID: %d, testerCode: %s, year: 0x%02X, month: 0x%02X day: 0x%02X", + firmwareMetaMap_Main->fingerprint.ModuleID, + dataTmp, + firmwareMetaMap_Main->fingerprint.year, + firmwareMetaMap_Main->fingerprint.month, + firmwareMetaMap_Main->fingerprint.day); + + + + if (hardFault_magic == 0xDEADBEEF) { + hardFault_magic = 0; + + LoggerFormatError(LOGGER, LOG_TASK_MAIN, "HardFault addresses (%d):", hardFault_count); + + for (uint32 i = 0; i < hardFault_count; ++i) { + LoggerFormatError(LOGGER, LOG_TASK_MAIN, " [%d] 0x%08X", i, hardFault_addresses[i]); + } + + } + + if (CHECK_JTAG_DEBUG_ACTIVE) { + LoggerInfoStatic(LOGGER, LOG_TASK_MAIN, "Debug mode") + } else { + LoggerInfoStatic(LOGGER, LOG_TASK_MAIN, "Run mode") + } + + if (CHECK_PARALLEL_ENABLE) { + LoggerInfoStatic(LOGGER, LOG_TASK_MAIN, "Parallel memory access enabled (OTA update unavailable)") + } else { + LoggerInfoStatic(LOGGER, LOG_TASK_MAIN, "Parallel memory access disabled (OTA update available)") + } + + /* + if (RGM_SRS_WAKEUP_MASK == (RGM->SRS & RGM_SRS_WAKEUP_MASK)) { + LoggerInfoStatic(LOGGER, LOG_TASK_MAIN, "Wake up from standby (INIT)") + +// tGpioPin Ign_Wakeup = vInitGpioPinPull(GPIO_E, PORT_PIN_16, GPIO_IN, GPIO_PIN_NOREVERSE, GPIO_HIGH, +// GPIO_PUSH_PULL, +// PORT_PULL_UP); + + + } +*/ + + LoggerInfoStatic(LOGGER, LOG_TASK_MAIN, "Initialization of subsystems") + + // Инициализация периферийных интерфейсов + InitPeripheralInterfaces(&env->slog.logger); + + bool result = DeviceStorage_Init(&env->storage, true, &env->flash->interface_calib, &env->flash->interface_param, + &env->slog.logger); + + Rs_Cal_0_SedanL(); + + VarsTabDumpObserver_StartThread(&env->storage.dumpObserver); + + LoadFromStorageToStatusData(&env->storage, &statusData.ecu); + + + GpioPinSet(&env->gpios->power.SW5V_EN, true); +/* + // Включение 5V (0 - ВКЛ) + GpioPinSet(&env->gpios->power.SW5V_EN, true); + + // Контроль напряжения борт-сети (1 - ВКЛ) + GpioPinSet(&env->gpios->power.PBATT_CK_EN, true); + + GpioPinSet(&env->gpios->power.BTS5180_2EKA_FrontRearIncarMotor.Incar_Motor_Front_EN, true); + GpioPinSet(&env->gpios->power.BTS5180_2EKA_FrontRearIncarMotor.Incar_EN_Diag, true); + GpioPinSet(&env->gpios->power.BTS5180_2EKA_FrontRearIncarMotor.Incar_Motor_Rear_EN, true); + + GpioPinSet(&env->gpios->power.BTS5180_2EKA_TwoWayValveAndReservePowerSupply.TwoWayValve_EN, true); + GpioPinSet(&env->gpios->power.BTS5180_2EKA_TwoWayValveAndReservePowerSupply.TwoWayValve_EN_Diag, true); + GpioPinSet(&env->gpios->power.BTS5180_2EKA_TwoWayValveAndReservePowerSupply.ReservePower_EN, true); + + GpioPinSet(&env->gpios->power.BTS4175SGAXUMA1_ReservePowerOutput.EN_ReservePower, true); + GpioPinSet(&env->gpios->power.BTS4175SGAXUMA1_PowerReserve.EN_PowerReserve, true); + + GpioPinSet(&env->gpios->power.BTS5180_2EKA_2xChannelPTCPower.PtcRelayDriver1_EN, true); + GpioPinSet(&env->gpios->power.BTS5180_2EKA_2xChannelPTCPower.PtcRelayDriver_EN_Diag, true); + GpioPinSet(&env->gpios->power.BTS5180_2EKA_2xChannelPTCPower.PtcRelayDriver2_EN, true); + + GpioPinSet(&env->gpios->power.VN7008AJ_FrontLINActuatorPowerDriverAB.LIN_ActPower_AB, true); + GpioPinSet(&env->gpios->power.VN7008AJ_FrontLINActuatorPowerDriverAB.EN_CurrentSensing_AB, true); + + GpioPinSet(&env->gpios->power.VN7008AJ_RearLINActuatorPowerDriverC.LIN_ActPower_C, true); + GpioPinSet(&env->gpios->power.VN7008AJ_RearLINActuatorPowerDriverC.EN_CurrentSensing_C, true); + + GpioPinSet(&env->gpios->power.BTS4175SGAXUMA1_ShutOFFValveBatteryChiller.EN_BATTChiller, true); + + + GpioPinSet(&env->gpios->power.BTS5180_2EKA_ShutOFFValveFrontRear.ShutOffFront_EN, true); + GpioPinSet(&env->gpios->power.BTS5180_2EKA_ShutOFFValveFrontRear.ShutOff_EN_Diag, true); + GpioPinSet(&env->gpios->power.BTS5180_2EKA_ShutOFFValveFrontRear.ShutOffRear_EN, true); + + GpioPinSet(&env->gpios->power.BTS5120_2EKA_ShutoffValvePowerTXV.ShutOffTXV1_EN, true); + GpioPinSet(&env->gpios->power.BTS5120_2EKA_ShutoffValvePowerTXV.ShutOffTXV_EN_Diag, true); + GpioPinSet(&env->gpios->power.BTS5120_2EKA_ShutoffValvePowerTXV.ShutOffTXV2_EN, true); +*/ + +// Indication_Init(&env->Indication, HVAC_DEV_MODE_STARTUP); + + CommandLine_Init(&env->cli, &env->slog, &env->serialPorts->SerialPortLog_IO, + &env->serialPorts->cliVirtualPortOut_Io); + CommandLine_StartThread(&env->cli); + + Diagnostic_Init(&env->Diagnostic, &env->slog.logger); + + CanSerialPortFrameXcpInit( + &env->CanSerialPortFrameXCP, + &env->canPorts->Can1_IO, + &env->rtcs->rtcI0, + + 0x00000000, + nf_storage_calib_size, + + nf_storage_calib_mainFlashPageAddress, + nf_storage_calib_recoveryFlashPageAddress + nf_storage_calib_size, + &D_bInternalFlashPage_ClearRange, + &D_bInternalFlashPage_WriteFromRam, + &env->storage.dumpObserver, + &env->slog.logger + ); + + CanXcpProcessing_Listener_Start(&env->CanSerialPortFrameXCP); + + CanSpamReceiver_Init(&env->canSpamReceiver, &env->canPorts->Can0_IO, &env->slog.logger); + CanSpamReceiver_StartThread(&env->canSpamReceiver); + + CanSpamTransmitter_Init(&env->canSpamTransmitter, &env->canPorts->Can0_IO, &env->slog.logger); + CanSpamTransmitter_StartThread(&env->canSpamTransmitter); + + CanSpamDebugReceiver_Init(&env->canSpamDebugReceiver, &env->canPorts->Can1_IO, &env->slog.logger); + CanSpamDebugReceiver_StartThread(&env->canSpamDebugReceiver); + + CanSpamDebugTransmitter_Init(&env->canSpamDebugTransmitter, &env->canPorts->Can1_IO, &env->canSpamDebugReceiver, + &env->slog.logger); + CanSpamDebugTransmitter_StartThread(&env->canSpamDebugTransmitter); + + + tLinData *linData4 = Lin4_Init(GetLin123CallbackHandler); + Lin_4_Init(&env->linTaskSensor4, linData4, &env->linPorts->lin4_Io, &env->slog.logger); + Lin4_StartThread(&env->linTaskSensor4); + + tLinData *linData5 = Lin5_Init(GetLin123CallbackHandler); + Lin_5_Init(&env->linTaskSensor5, linData5, &env->linPorts->lin5_Io, &env->slog.logger); + Lin5_StartThread(&env->linTaskSensor5); + + +// tLinData *linData6 = Lin6_Init(GetLin123CallbackHandler); +// Lin_6_Init(&env->linTaskSensor6, linData6, &env->linPorts->lin6_Io, &env->slog.logger); +// Lin6_StartThread(&env->linTaskSensor6); + + Adc_0_Init(&env->adcTask0, &env->adcs->adc_0_IO, env->gpios, &env->slog.logger); + Adc_0_StartThread(&env->adcTask0); + + Adc_1_Init(&env->adcTask1, &env->adcs->adc_1_IO, env->gpios, &env->slog.logger); + Adc_1_StartThread(&env->adcTask1); + + CanUds_Init( + &env->canUds, + &env->Diagnostic, + &env->canPorts->Can0_IO, + &env->storage, + &env->canSpamTransmitter, + &env->canSpamDebugTransmitter, + &env->adcTask0, + &P_bInternalFlashPage_ClearRange, + &P_bInternalFlashPage_WriteFromRam, + &env->slog.logger); + + CanSerialPortCanUds_Start(&env->canUds); + + StandBy_Init(); + + + ModelTask_Init( + &env->ModelTask, + &env->linTaskActuator1, + &env->linTaskActuator2, + &env->linTaskActuator3, + + &env->linTaskSensor4, + &env->linTaskSensor5, + + env->pwms, + + env->gpios, + + &env->adcTask0, + &env->adcTask1, + + &env->canSpamReceiver, + &env->canSpamTransmitter, + &env->canSpamDebugTransmitter, + &env->Diagnostic, + + &env->canUds, + + &env->slog.logger + ); + + + tLinData *linData1 = Lin1_Init(GetLin123CallbackHandler); + Lin_1_Init(&env->linTaskActuator1, + linData1, &env->linPorts->lin1_Io, 9, + + env->ModelTask.access, + &env->ModelTask.triggerActuatorCmdBus_1, + &env->ModelTask.triggerCommand1, + + &env->slog.logger); + + + Lin1_StartThread(&env->linTaskActuator1); + + tLinData *linData2 = Lin2_Init(GetLin123CallbackHandler); + Lin_2_Init(&env->linTaskActuator2, + linData2, &env->linPorts->lin2_Io, 6, + + env->ModelTask.access, + &env->ModelTask.triggerActuatorCmdBus_2, + &env->ModelTask.triggerCommand2, + + &env->slog.logger); + + Lin2_StartThread(&env->linTaskActuator2); + + tLinData *linData3 = Lin3_Init(GetLin123CallbackHandler); + Lin_3_Init(&env->linTaskActuator3, + linData3, &env->linPorts->lin3_Io, 8, + + env->ModelTask.access, + &env->ModelTask.triggerActuatorCmdBus_3, + &env->ModelTask.triggerCommand3, + + &env->slog.logger); + + Lin3_StartThread(&env->linTaskActuator3); + + + LoggerInfoStatic(LOGGER, LOG_TASK_MAIN, "End of subsystem initialization") + +} + + +static void Mma_RunSubThreads(tMma *env) { + Indication_SetMode(&env->Indication, HVAC_DEV_MODE_RUN); +} + +static void Mma_InitPower(tMma *env) { + +} + +void Mma_InitStage(tMma *env) { + Mma_InitSubSystems(env); + Mma_InitPower(env); + Mma_RunSubThreads(env); +} + diff --git a/MODULES/HVAC_M7_DebugTesting/MainModesArbiter_Private.h b/MODULES/HVAC_M7_DebugTesting/MainModesArbiter_Private.h new file mode 100644 index 0000000..8e99d5f --- /dev/null +++ b/MODULES/HVAC_M7_DebugTesting/MainModesArbiter_Private.h @@ -0,0 +1,13 @@ +// +// Created by cfif on 05.05.23. +// + +#ifndef WATER_BOX_BSD_MAINMODESARBITER_PRIVATE_H +#define WATER_BOX_BSD_MAINMODESARBITER_PRIVATE_H + +#include "MainModesArbiter.h" + +extern const tMma MAIN_ENV; +void Mma_InitStage(tMma *env); + +#endif //WATER_BOX_BSD_MAINMODESARBITER_PRIVATE_H diff --git a/MODULES/HVAC_M7_DebugTesting/NAMI.c b/MODULES/HVAC_M7_DebugTesting/NAMI.c new file mode 100644 index 0000000..7a4b76f --- /dev/null +++ b/MODULES/HVAC_M7_DebugTesting/NAMI.c @@ -0,0 +1,136 @@ +// +// Created by cfif on 28.01.2026. +// +#include +#include + +/** + * CCU Secure Access Algorithm + * Реализация алгоритма генерации ключа по seed для диагностического доступа + * Согласно спецификации NAMI UMP vehicle, версия 1.1 + */ + +/* Позиции битов коэффициентов в seed */ +#define COEFF1_POS 20 /* Направление сдвига (0 - влево, 1 - вправо) */ +#define COEFF2_POS 7 /* Старший бит количества сдвигов */ +#define COEFF3_POS 11 /* */ +#define COEFF4_POS 5 /* */ +#define COEFF5_POS 8 /* Младший бит количества сдвигов */ +#define COEFF6_POS 22 /* Старший бит операции инверсии */ +#define COEFF7_POS 1 /* Младший бит операции инверсии */ +#define COEFF8_POS 21 /* Старший бит побитовой операции */ +#define COEFF9_POS 6 /* Младший бит побитовой операции */ + +/* Позиции битов для инверсии */ +#define INV_A_BITS ((1U << 6) | (1U << 15) | (1U << 17)) +#define INV_B_BITS ((1U << 11) | (1U << 9) | (1U << 16)) +#define INV_C_BITS ((1U << 7) | (1U << 10) | (1U << 13) | (1U << 4)) + +/** + * Извлечение бита из значения + * position: 0 = младший бит (LSB), 31 = старший бит (MSB) + */ +static inline uint32_t extract_bit(uint32_t value, int position) +{ + return (value >> position) & 1U; +} + +/** + * Циклический сдвиг вправо (rotation) + */ +static inline uint32_t rotate_right(uint32_t value, int bits) +{ + bits = bits % 32; + if (bits == 0) return value; + return (value >> bits) | (value << (32 - bits)); +} + +/** + * Циклический сдвиг влево (rotation) + */ +static inline uint32_t rotate_left(uint32_t value, int bits) +{ + bits = bits % 32; + if (bits == 0) return value; + return (value << bits) | (value >> (32 - bits)); +} + +/** + * Генерация 32-битного ключа из 32-битного seed + * + * Параметры: + * seed - случайное значение от ECU (32 бита) + * + * Возвращает: + * 32-битный ключ для ответа ECU + */ +uint32_t generate_key(uint32_t seed) +{ + /* Извлечение коэффициентов из seed */ + uint32_t coeff1 = extract_bit(seed, COEFF1_POS); /* Направление сдвига */ + + /* Коэффициенты 2-5: количество циклических сдвигов (coeff2 - старший бит) */ + uint32_t coeff2 = extract_bit(seed, COEFF2_POS); + uint32_t coeff3 = extract_bit(seed, COEFF3_POS); + uint32_t coeff4 = extract_bit(seed, COEFF4_POS); + uint32_t coeff5 = extract_bit(seed, COEFF5_POS); + uint32_t num_shifts = (coeff2 << 3) | (coeff3 << 2) | (coeff4 << 1) | coeff5; + + /* Коэффициенты 6-7: выбор операции инверсии (coeff6 - старший бит) */ + uint32_t coeff6 = extract_bit(seed, COEFF6_POS); + uint32_t coeff7 = extract_bit(seed, COEFF7_POS); + uint32_t inversion_op = (coeff6 << 1) | coeff7; + + /* Коэффициенты 8-9: побитовая операция (coeff8 - старший бит) */ + uint32_t coeff8 = extract_bit(seed, COEFF8_POS); + uint32_t coeff9 = extract_bit(seed, COEFF9_POS); + uint32_t bitwise_op = (coeff8 << 1) | coeff9; + + /* Шаг 1: Вычисление intermediate 1 (циклический сдвиг) */ + uint32_t intermediate1; + if (coeff1 == 0) { + intermediate1 = rotate_left(seed, num_shifts); + } else { + intermediate1 = rotate_right(seed, num_shifts); + } + + /* Шаг 2: Вычисление intermediate 2 (инверсия битов) */ + uint32_t intermediate2 = intermediate1; + + switch (inversion_op) { + case 1: /* Операция A: инвертировать биты 6, 15, 17 */ + intermediate2 ^= INV_A_BITS; + break; + case 2: /* Операция B: инвертировать биты 11, 9, 16 */ + intermediate2 ^= INV_B_BITS; + break; + case 3: /* Операция C: инвертировать биты 7, 10, 13, 4 */ + intermediate2 ^= INV_C_BITS; + break; + case 0: /* Нет инверсии */ + default: + break; + } + + /* Шаг 3: Вычисление финального ключа (побитовая операция) */ + uint32_t key; + switch (bitwise_op) { + case 0: /* Key = intermediate value */ + key = intermediate2; + break; + case 1: /* Key = seed AND intermediate value */ + key = seed & intermediate2; + break; + case 2: /* Key = seed XOR intermediate value */ + key = seed ^ intermediate2; + break; + case 3: /* Key = seed OR intermediate value */ + key = seed | intermediate2; + break; + default: + key = intermediate2; + break; + } + + return key; +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_DebugTesting/PeripheralInterfaces.c b/MODULES/HVAC_M7_DebugTesting/PeripheralInterfaces.c new file mode 100644 index 0000000..d4cc4ee --- /dev/null +++ b/MODULES/HVAC_M7_DebugTesting/PeripheralInterfaces.c @@ -0,0 +1,14 @@ +// +// Created by cfif on 05.05.23. +// + +#include "PeripheralInterfaces.h" + +void InitPeripheralInterfaces(tLoggerInterface *logger) { + Gpios_Init(); + CanPorts_Init(logger); + Adcs_Init(logger); + Pwms_Init(logger); + StorageOnFlash_Init(logger); + +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_DebugTesting/PeripheralInterfaces.h b/MODULES/HVAC_M7_DebugTesting/PeripheralInterfaces.h new file mode 100644 index 0000000..e52bb27 --- /dev/null +++ b/MODULES/HVAC_M7_DebugTesting/PeripheralInterfaces.h @@ -0,0 +1,18 @@ +// +// Created by cfif on 05.05.23. +// + +#ifndef WATER_BOX_BSD_PERIPHERALINTERFACES_H +#define WATER_BOX_BSD_PERIPHERALINTERFACES_H + +#include "Gpios.h" +#include "SerialPorts.h" +#include "CanPorts.h" +#include "Rtcs.h" +#include "Adcs.h" +#include "Pwms.h" +#include "StorageOnFlash.h" + +void InitPeripheralInterfaces(tLoggerInterface *logger); + +#endif //WATER_BOX_BSD_PERIPHERALINTERFACES_H diff --git a/MODULES/HVAC_M7_DebugTesting/modular.json b/MODULES/HVAC_M7_DebugTesting/modular.json new file mode 100644 index 0000000..0dd1901 --- /dev/null +++ b/MODULES/HVAC_M7_DebugTesting/modular.json @@ -0,0 +1,10 @@ +{ + "cmake": { + "inc_dirs": [ + "./" + ], + "srcs": [ + "./**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_DeviceStorage/DeviceStorage.c b/MODULES/HVAC_M7_DeviceStorage/DeviceStorage.c new file mode 100644 index 0000000..4244859 --- /dev/null +++ b/MODULES/HVAC_M7_DeviceStorage/DeviceStorage.c @@ -0,0 +1,169 @@ +// +// Created by cfif on 07.10.22. +// + +#include +#include +#include "DeviceStorage.h" +#include "DataNonVolatile.h" +#include "StorageOnFlashFlagchip.h" +#include "SystemDelayInterface.h" +#include "HVAC_preDefine.h" +#include "StorageOnFlash.h" +#include "FirmwareMetadataSection.h" + +#define LOGGER env->logger +#define LOG_SIGN "Storage" + +#define VARIABLE_GROUP_UNTRACKED 0 +#define VARIABLE_GROUP_FLASH (1 << 0) + +void DeviceStorage_InitVariablesTable(tDeviceStorage *env) { + env->trackableVarsTab = 0; + DeviceDataRuntime_InitDefaults(&env->runtime); +} + +bool DeviceStorage_LoadParam(tDeviceStorage *env) { + + bool isLoad = VarsTabDumpObserverParam_Load(&env->dumpObserver); + + tFirmwareMetaMap *firmwareMetaMap_Boot = (tFirmwareMetaMap *) ADR_META_BOOT; + tFirmwareMetaMap *firmwareMetaMap_Main = (tFirmwareMetaMap *) ADR_META_MAIN; + + memcpy(&env->dataParam->device.identification.Internal_SW_Version, &firmwareMetaMap_Main->internal_SW_Version, + sizeof(tInternal_SW_Version)); + + memcpy(&env->dataParam->device.identification.Boot_SW_Fingerprint, &firmwareMetaMap_Boot->fingerprint, sizeof(tFingerprintDev)); + memcpy(&env->dataParam->device.identification.Application_SW_Fingerprint, &firmwareMetaMap_Main->fingerprint, sizeof(tFingerprintDev)); + + + if (isLoad) { + if (env->dataParam->version_param == DEVICE_DATA_VERSION_PARAM) { + LoggerInfoStatic(LOGGER, LOG_SIGN, "Parameters loaded successfully"); + return true; + } + } + + LoggerInfoStatic(LOGGER, LOG_SIGN, "Parameters: Reset settings"); + + DeviceDataParam_InitDefaults(env->dataParam); + + return VarsTabDumpObserverParam_Dump(&env->dumpObserver); + +} + +bool DeviceStorage_LoadCalib(tDeviceStorage *env) { + + bool isLoad = VarsTabDumpObserverCalib_Load(&env->dumpObserver); + + if (isLoad) { + if (env->dataParam->version_calib == DEVICE_DATA_VERSION_CALIB) { + LoggerInfoStatic(LOGGER, LOG_SIGN, "Calibrations loaded successfully"); + return true; + } + } + + LoggerInfoStatic(LOGGER, LOG_SIGN, "Calibrations: Reset settings"); + + DeviceDataCalib_InitDefaults(env->dataParam); + + bool resultParam = VarsTabDumpObserverParam_Dump(&env->dumpObserver); + bool resultCalib = VarsTabDumpObserverCalib_Dump(&env->dumpObserver); + + if ((resultParam) || (resultCalib)) { + return true; + } + + return false; +} + + +void DeviceStorageCalib_ForceDump(tDeviceStorage *env) { + VarsTabDumpObserverCalib_Dump(&env->dumpObserver); +} + +void DeviceStorageParam_ForceDump(tDeviceStorage *env) { + VarsTabDumpObserverParam_Dump(&env->dumpObserver); +} + +void DeviceStorageParam_DelayedDump(tDeviceStorage *env) { + env->trackableVarsTab = 1; +} + +void DeviceStorage_InitCommon(tDeviceStorage *env, tStorageInterface *storageCalibInterface, size_t sizeCalib, + tStorageInterface *storageParamInterface, size_t sizeParam) { + VarsTabDumpObserver_Init( + &env->dumpObserver, + storageCalibInterface, + storageParamInterface, + 5000, + env->dataCalib, + env->dataParam, + sizeCalib, + sizeParam, + &env->trackableVarsTab, + VARIABLE_GROUP_FLASH, + env->logger + ); + + + DeviceStorage_InitVariablesTable(env); + +} + +SECT_SRAM_NVM uint8_t dataReservedParamStore[nf_storage_param_size]; + +bool DeviceStorage_Init(tDeviceStorage *env, bool loadParamOnly, tStorageInterface *storageCalibInterface, + tStorageInterface *storageParamInterface, + tLoggerInterface *logger) { + + extern uint32_t __itcm_start[]; + + env->logger = logger; + + env->dataParam = (tDeviceDataNonVolatile *) dataReservedParamStore; + env->dataCalib = (void *) __itcm_start + 4; + + DeviceStorage_InitCommon(env, storageCalibInterface, nf_storage_calib_size, + storageParamInterface, nf_storage_param_size); + + if (loadParamOnly) { + bool resultParam = DeviceStorage_LoadParam(env); + + if (resultParam) { + return true; + } + } else { + bool resultParam = DeviceStorage_LoadParam(env); + bool resultCalib = DeviceStorage_LoadCalib(env); + + if ((resultParam) && (resultCalib)) { + return true; + } + } + + return false; +} + +void LoadFromStorageToStatusData(tDeviceStorage *env, ecu_identification_t *ecu) { + if (osMutexAcquire(env->dumpObserver.accessDumper, 1000) == osOK) { + memcpy(ecu, &env->dataParam->device.identification, sizeof(ecu_identification_t)); + osMutexRelease(env->dumpObserver.accessDumper); + } else { + LoggerErrorStatic(LOGGER, LOG_SIGN, "Access error LoadFromStorageToStatusData"); + } +} + +void SaveToStorageFromStatusData(tDeviceStorage *env, ecu_identification_t *ecu) { + + if (osMutexAcquire(env->dumpObserver.accessDumper, 1000) == osOK) { + memcpy(&env->dataParam->device.identification, ecu, sizeof(ecu_identification_t)); + osMutexRelease(env->dumpObserver.accessDumper); + } else { + LoggerErrorStatic(LOGGER, LOG_SIGN, "Access error SaveToStorageFromStatusData"); + } + +// DeviceStorageParam_DelayedDump(env); + + DeviceStorageParam_ForceDump(env); +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_DeviceStorage/DeviceStorage.h b/MODULES/HVAC_M7_DeviceStorage/DeviceStorage.h new file mode 100644 index 0000000..8df8a1a --- /dev/null +++ b/MODULES/HVAC_M7_DeviceStorage/DeviceStorage.h @@ -0,0 +1,38 @@ +// +// Created by CFIF on 20.02.24. +// + +#ifndef HVAC_DEVICESTORAGE_H +#define HVAC_DEVICESTORAGE_H + +//#include "DeviceDataNonVolatile.h" +//#include "DeviceDataRuntime.h" +#include "LoggerInterface.h" +#include "DataRuntime.h" +#include "DataNonVolatile.h" +#include "StorageIO.h" +#include "VarsTabDumpObserver.h" + + +typedef struct { + tLoggerInterface *logger; + tDeviceDataRuntime runtime; + tDeviceDataNonVolatile *dataParam; + void *dataCalib; + tVarsTabDumpObserver dumpObserver; + uint8_t trackableVarsTab; +} tDeviceStorage; + +bool DeviceStorage_Init(tDeviceStorage *env, bool loadParamOnly, tStorageInterface *storageCalibInterface, + tStorageInterface *storageParamInterface, + tLoggerInterface *logger); + + +void DeviceStorageCalib_ForceDump(tDeviceStorage *env); +void DeviceStorageParam_ForceDump(tDeviceStorage *env); +void DeviceStorageParam_DelayedDump(tDeviceStorage *env); + +void LoadFromStorageToStatusData(tDeviceStorage *env, ecu_identification_t *ecu); +void SaveToStorageFromStatusData(tDeviceStorage *env, ecu_identification_t *ecu); + +#endif //HVAC_DEVICESTORAGE_H diff --git a/MODULES/HVAC_M7_DeviceStorage/modular.json b/MODULES/HVAC_M7_DeviceStorage/modular.json new file mode 100644 index 0000000..0dd1901 --- /dev/null +++ b/MODULES/HVAC_M7_DeviceStorage/modular.json @@ -0,0 +1,10 @@ +{ + "cmake": { + "inc_dirs": [ + "./" + ], + "srcs": [ + "./**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_GpioPins/Gpios.c b/MODULES/HVAC_M7_GpioPins/Gpios.c new file mode 100644 index 0000000..31b60db --- /dev/null +++ b/MODULES/HVAC_M7_GpioPins/Gpios.c @@ -0,0 +1,182 @@ +// +// Created by cfif on 05.05.23. +// +#include "Gpios.h" +#include "SystemDelayInterface.h" + +tGpios GPIOS; + + +void Gpios_Init() { + tGpios *env = &GPIOS; + + env->led.LED_R = vInitGpioPinPull(GPIO_A, PORT_PIN_1, GPIO_OUT, GPIO_PIN_NOREVERSE, GPIO_HIGH, GPIO_PUSH_PULL, PORT_PULL_DOWN); + env->led.LED_G = vInitGpioPinPull(GPIO_D, PORT_PIN_2, GPIO_OUT, GPIO_PIN_NOREVERSE, GPIO_HIGH, GPIO_PUSH_PULL, PORT_PULL_DOWN); + + env->power.TPS7B6850QPWPRQ1.WD_EN = vInitGpioPinPull(GPIO_C, PORT_PIN_12, GPIO_OUT, GPIO_PIN_NOREVERSE, GPIO_HIGH, GPIO_PUSH_PULL, PORT_PULL_DOWN); + env->power.TPS7B6850QPWPRQ1.WDO = vInitGpioPinPull(GPIO_C, PORT_PIN_13, GPIO_IN, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_OPEN, PORT_PULL_DOWN); + env->power.TPS7B6850QPWPRQ1.WD = vInitGpioPinPull(GPIO_C, PORT_PIN_14, GPIO_OUT, GPIO_PIN_NOREVERSE, GPIO_HIGH, GPIO_PUSH_PULL, PORT_PULL_DOWN); + + // Контроль напряжения борт-сети (1 - ВКЛ) + env->power.PBATT_CK_EN = vInitGpioPinPull(GPIO_C, PORT_PIN_17, GPIO_OUT, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_PUSH_PULL, PORT_PULL_DOWN); + // Включение 5V (0 - ВКЛ) + env->power.SW5V_EN = vInitGpioPinPull(GPIO_C, PORT_PIN_18, GPIO_OUT, GPIO_PIN_REVERSE, GPIO_HIGH, GPIO_PUSH_PULL, PORT_PULL_UP); + + // Канал 0 (1 - ВКЛ) + env->power.BTS5180_2EKA_FrontRearIncarMotor.Incar_Motor_Front_EN = vInitGpioPinPull(GPIO_A, PORT_PIN_9, GPIO_OUT, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_PUSH_PULL, PORT_PULL_DOWN); + // Разрешение диагностики (1 - ВКЛ) + env->power.BTS5180_2EKA_FrontRearIncarMotor.Incar_EN_Diag = vInitGpioPinPull(GPIO_A, PORT_PIN_10, GPIO_OUT, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_PUSH_PULL, PORT_PULL_DOWN); + // Вывод диагностики (0 - Канал 0; 1 - Канал 1) + env->power.BTS5180_2EKA_FrontRearIncarMotor.Incar_SEL_Diag = vInitGpioPinPull(GPIO_A, PORT_PIN_11, GPIO_OUT, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_PUSH_PULL, PORT_PULL_DOWN); + // Канал 1 (1 - ВКЛ) + env->power.BTS5180_2EKA_FrontRearIncarMotor.Incar_Motor_Rear_EN = vInitGpioPinPull(GPIO_A, PORT_PIN_17, GPIO_OUT, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_PUSH_PULL, PORT_PULL_DOWN); + + + // Канал 0 (1 - ВКЛ) + env->power.BTS5180_2EKA_TwoWayValveAndReservePowerSupply.TwoWayValve_EN = vInitGpioPinPull(GPIO_D, PORT_PIN_24, GPIO_OUT, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_PUSH_PULL, PORT_PULL_DOWN); + // Разрешение диагностики (1 - ВКЛ) Fix V2 + //env->power.BTS5180_2EKA_TwoWayValveAndReservePowerSupply.TwoWayValve_EN_Diag = vInitGpioPinPull(GPIO_D, PORT_PIN_25, GPIO_OUT, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_PUSH_PULL, PORT_PULL_DOWN); + env->power.BTS5180_2EKA_TwoWayValveAndReservePowerSupply.TwoWayValve_EN_Diag = vInitGpioPinPull(GPIO_B, PORT_PIN_12, GPIO_OUT, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_PUSH_PULL, PORT_PULL_DOWN); + // Вывод диагностики (0 - Канал 0; 1 - Канал 1) Fix V2 + //env->power.BTS5180_2EKA_TwoWayValveAndReservePowerSupply.TwoWayValve_SEL_Diag = vInitGpioPinPull(GPIO_D, PORT_PIN_26, GPIO_OUT, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_PUSH_PULL, PORT_PULL_DOWN); + env->power.BTS5180_2EKA_TwoWayValveAndReservePowerSupply.TwoWayValve_SEL_Diag = vInitGpioPinPull(GPIO_B, PORT_PIN_10, GPIO_OUT, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_PUSH_PULL, PORT_PULL_DOWN); + // Канал 1 (1 - ВКЛ) + env->power.BTS5180_2EKA_TwoWayValveAndReservePowerSupply.ReservePower_EN = vInitGpioPinPull(GPIO_D, PORT_PIN_27, GPIO_OUT, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_PUSH_PULL, PORT_PULL_DOWN); + + + // Канал 0 (1 - ВКЛ) + env->power.BTS5180_2EKA_2xChannelPTCPower.PtcRelayDriver1_EN = vInitGpioPinPull(GPIO_C, PORT_PIN_20, GPIO_OUT, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_PUSH_PULL, PORT_PULL_DOWN); + // Разрешение диагностики (1 - ВКЛ) + env->power.BTS5180_2EKA_2xChannelPTCPower.PtcRelayDriver_EN_Diag = vInitGpioPinPull(GPIO_C, PORT_PIN_23, GPIO_OUT, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_PUSH_PULL, PORT_PULL_DOWN); + // Вывод диагностики (0 - Канал 0; 1 - Канал 1) + env->power.BTS5180_2EKA_2xChannelPTCPower.PtcRelayDriver_SEL_Diag = vInitGpioPinPull(GPIO_C, PORT_PIN_24, GPIO_OUT, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_PUSH_PULL, PORT_PULL_DOWN); + // Канал 1 (1 - ВКЛ) + env->power.BTS5180_2EKA_2xChannelPTCPower.PtcRelayDriver2_EN = vInitGpioPinPull(GPIO_C, PORT_PIN_21, GPIO_OUT, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_PUSH_PULL, PORT_PULL_DOWN); + + + // Канал 0 (1 - ВКЛ) + env->power.BTS5180_2EKA_ShutOFFValveFrontRear.ShutOffFront_EN = vInitGpioPinPull(GPIO_A, PORT_PIN_20, GPIO_OUT, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_PUSH_PULL, PORT_PULL_DOWN); + // Разрешение диагностики (1 - ВКЛ) + env->power.BTS5180_2EKA_ShutOFFValveFrontRear.ShutOff_EN_Diag = vInitGpioPinPull(GPIO_A, PORT_PIN_21, GPIO_OUT, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_PUSH_PULL, PORT_PULL_DOWN); + // Вывод диагностики (0 - Канал 0; 1 - Канал 1) + env->power.BTS5180_2EKA_ShutOFFValveFrontRear.ShutSel_SEL_Diag = vInitGpioPinPull(GPIO_A, PORT_PIN_23, GPIO_OUT, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_PUSH_PULL, PORT_PULL_DOWN); + // Канал 1 (1 - ВКЛ) + env->power.BTS5180_2EKA_ShutOFFValveFrontRear.ShutOffRear_EN = vInitGpioPinPull(GPIO_A, PORT_PIN_24, GPIO_OUT, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_PUSH_PULL, PORT_PULL_DOWN); + + // Резервный источник разрешение (1 - ВКЛ) + env->power.BTS4175SGAXUMA1_ReservePowerOutput.EN_ReservePower = vInitGpioPinPull(GPIO_C, PORT_PIN_28, GPIO_OUT, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_PUSH_PULL, PORT_PULL_DOWN); + // Резервный источник состояния состояние (1 - ошибок нет) + // Когда устройство работает нормально (нет перегрузки, перегрева, обрыва нагрузки при выключенном состоянии), + // на выводе ST поддерживается высокий уровень напряжения (через внешний подтягивающий резистор) + env->power.BTS4175SGAXUMA1_ReservePowerOutput.ST_ReservePower = vInitGpioPinPull(GPIO_C, PORT_PIN_27, GPIO_IN, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_OPEN, PORT_PULL_DOWN); + + + // Резервный источник разрешение (1 - ВКЛ) + env->power.BTS4175SGAXUMA1_ShutOFFValveBatteryChiller.EN_BATTChiller = vInitGpioPinPull(GPIO_B, PORT_PIN_3, GPIO_OUT, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_PUSH_PULL, PORT_PULL_DOWN); + // Резервный источник состояния состояние (1 - ошибок нет) + // Когда устройство работает нормально (нет перегрузки, перегрева, обрыва нагрузки при выключенном состоянии), + // на выводе ST поддерживается высокий уровень напряжения (через внешний подтягивающий резистор) + env->power.BTS4175SGAXUMA1_ShutOFFValveBatteryChiller.ST_BATTChiller = vInitGpioPinPull(GPIO_B, PORT_PIN_4, GPIO_IN, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_OPEN, PORT_PULL_DOWN); + + + + + + // Резервный источник разрешение (1 - ВКЛ) + env->power.BTS4175SGAXUMA1_PowerReserve.EN_PowerReserve = vInitGpioPinPull(GPIO_C, PORT_PIN_22, GPIO_OUT, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_PUSH_PULL, PORT_PULL_DOWN); + // Резервный источник состояния состояние (1 - ошибок нет) + // Когда устройство работает нормально (нет перегрузки, перегрева, обрыва нагрузки при выключенном состоянии), + // на выводе ST поддерживается высокий уровень напряжения (через внешний подтягивающий резистор) + env->power.BTS4175SGAXUMA1_PowerReserve.ST_PowerReserve = vInitGpioPinPull(GPIO_C, PORT_PIN_19, GPIO_IN, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_OPEN, PORT_PULL_DOWN); + + + + + + + + + // Основной сигнал включения/выключения силового канала (выхода OUTPUT) (1 - ВКЛ) + env->power.VN7008AJ_FrontLINActuatorPowerDriverAB.LIN_ActPower_AB = vInitGpioPinPull(GPIO_B, PORT_PIN_22, GPIO_OUT, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_PUSH_PULL, PORT_PULL_DOWN); + + // 1. Нормальный режим (SEn=1, INPUT=1, нет ошибок): + // Вывод работает как источник тока. + // Выдает ток (ISENSE), строго пропорциональный току через нагрузку (IOUT). + // Коэффициент K = IOUT / ISENSE задан в даташите (например, ~5890 для IOUT=6А). + // Формула для ADC: VSENSE = ISENSE * RSENSE = (IOUT / K) * RSENSE. + //2. Режим индикации неисправности (SEn=1, произошла ошибка): + // Вывод переключается в режим напряжения с ограничением тока. + // Выдает фиксированное напряжение VSENSEH (около 5-6.6В) при ограниченном токе ISENSEH (около 7-30 мА). + // Это цифровой сигнал для контроллера: "Произошла ошибка!" Конкретный тип ошибки (перегрев, перегрузка) определяется дополнительно, например, по времени возникновения. + // 3. Диагностика в выключенном состоянии (SEn=1, INPUT=0): + // Обрыв нагрузки (Open-Load): Если при выключенном выходе на нем (через внешний pull-up резистор) есть напряжение > VOL (порог ~2-4В), CS выдает VSENSEH + // Короткое замыкание на VCC: Если выход притянут к питанию, CS также выдает VSENSEH + // Если нагрузки исправна и подключена, CS выдает низкий уровень (~0В) + + // VSENSE = N × (VREF / 4095) = N × (5 / 4095) ≈ N × 0.001221 В + // 1. VSENSE = N × 0.001221 В + // 2. ISENSE = VSENSE / RSENSE + // 3. IOUT = K × ISENSE = K × (VSENSE / RSENSE) = K × N × 0.001221 / RSENSE + + + /* + // Конфигурация +#define VREF 5.0f // Опорное напряжение АЦП +#define RSENSE 2490.0f // Сопротивление датчика, Ом +#define K_TYPICAL 5890.0f // Типичный коэффициент из даташита +#define ADC_MAX 4095 // Максимальный код АЦП + +// Порог ошибки (VSENSEH - 5.5В с запасом) +#define ERROR_THRESHOLD_V 4.5f +#define ERROR_THRESHOLD_CODE (uint16_t)(ERROR_THRESHOLD_V * 4095.0f / VREF) + +// Функция чтения тока +float VN7008AJ_ReadCurrent(uint16_t adc_value) { + // 1. Проверка на ошибку + if (adc_value >= ERROR_THRESHOLD_CODE) { + return -999.9f; // Код ошибки + } + + // 2. Преобразование в напряжение + float vsense = (float)adc_value * VREF / 4095.0f; + + // 3. Вычисление тока + float isense = vsense / RSENSE; + float iout = isense * K_TYPICAL; + + return iout; +} + */ + + + // Fault_RSTAB: Низкий уровень (0): режим автоматического перезапуска (autorestart). При срабатывании защиты (перегрев, перегрузка) выход отключится, а затем автоматически включится, когда причина срабатывания защиты устранится. + // Fault_RSTAB: Высокий уровень (1): режим фиксации (latch-off). При срабатывании защиты выход отключается и остается выключенным до тех пор, пока не будет подан сброс (импульс низкого уровня на FaultRST) или не будет перезапущено питание. + + env->power.VN7008AJ_FrontLINActuatorPowerDriverAB.Fault_RST_AB = vInitGpioPinPull(GPIO_B, PORT_PIN_23, GPIO_OUT, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_PUSH_PULL, PORT_PULL_DOWN); + // Разрешение диагностики + env->power.VN7008AJ_FrontLINActuatorPowerDriverAB.EN_CurrentSensing_AB = vInitGpioPinPull(GPIO_B, PORT_PIN_25, GPIO_OUT, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_PUSH_PULL, PORT_PULL_DOWN); + + + + // Основной сигнал включения/выключения силового канала (выхода OUTPUT) (1 - ВКЛ) + env->power.VN7008AJ_RearLINActuatorPowerDriverC.LIN_ActPower_C = vInitGpioPinPull(GPIO_B, PORT_PIN_27, GPIO_OUT, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_PUSH_PULL, PORT_PULL_DOWN); + + env->power.VN7008AJ_RearLINActuatorPowerDriverC.Fault_RST_C = vInitGpioPinPull(GPIO_B, PORT_PIN_28, GPIO_OUT, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_PUSH_PULL, PORT_PULL_DOWN); + // Разрешение диагностики + env->power.VN7008AJ_RearLINActuatorPowerDriverC.EN_CurrentSensing_C = vInitGpioPinPull(GPIO_B, PORT_PIN_29, GPIO_OUT, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_PUSH_PULL, PORT_PULL_DOWN); + + + // Канал 0 (1 - ВКЛ) + env->power.BTS5120_2EKA_ShutoffValvePowerTXV.ShutOffTXV1_EN = vInitGpioPinPull(GPIO_E, PORT_PIN_25, GPIO_OUT, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_PUSH_PULL, PORT_PULL_DOWN); + // Разрешение диагностики (1 - ВКЛ) + env->power.BTS5120_2EKA_ShutoffValvePowerTXV.ShutOffTXV_EN_Diag = vInitGpioPinPull(GPIO_E, PORT_PIN_26, GPIO_OUT, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_PUSH_PULL, PORT_PULL_DOWN); + // Вывод диагностики (0 - Канал 0; 1 - Канал 1) + env->power.BTS5120_2EKA_ShutoffValvePowerTXV.ShutSelTXV_SEL_Diag = vInitGpioPinPull(GPIO_E, PORT_PIN_27, GPIO_OUT, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_PUSH_PULL, PORT_PULL_DOWN); + // Канал 1 (1 - ВКЛ) + env->power.BTS5120_2EKA_ShutoffValvePowerTXV.ShutOffTXV2_EN = vInitGpioPinPull(GPIO_E, PORT_PIN_29, GPIO_OUT, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_PUSH_PULL, PORT_PULL_DOWN); + + env->EmergencyAirCleanSwitch = vInitGpioPinPull(GPIO_B, PORT_PIN_0, GPIO_IN, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_OPEN, PORT_PULL_DOWN); + env->FireExtinguishSwitch = vInitGpioPinPull(GPIO_B, PORT_PIN_1, GPIO_IN, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_OPEN, PORT_PULL_DOWN); + +// env->Ign_Wakeup = vInitGpioPinPull(GPIO_E, PORT_PIN_16, GPIO_IN, GPIO_PIN_NOREVERSE, GPIO_LOW, GPIO_OPEN, PORT_PULL_DOWN); +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_GpioPins/Gpios.h b/MODULES/HVAC_M7_GpioPins/Gpios.h new file mode 100644 index 0000000..dde3d68 --- /dev/null +++ b/MODULES/HVAC_M7_GpioPins/Gpios.h @@ -0,0 +1,155 @@ +// +// Created by cfif on 05.05.23. +// + +#ifndef HVAC_M7_GPIOS_H +#define HVAC_M7_GPIOS_H + +#include "GpioPin.h" +//#include "PowerManagement.h" + +typedef struct { + tGpioPin LED_R; + tGpioPin LED_G; +} tLed; + +typedef struct { + tGpioPin WD_EN; // Разрешение работы WD (0 - ВКЛ) + tGpioPin WDO; // При возникновении ошибки сторожевого таймера этот вывод подтягивается к низкому уровню напряжения (OpenDrain HIGH) + tGpioPin WD; // Watchdog service-signal (подавать меандр не менее 100 мкс) +} tTPS7B6850QPWPRQ1; + + +// Допустим, вы выбрали R_резистора = 1.2 кОм (1200 Ом). Микроконтроллер измерил U_на_резисторе = 1.1 В (U_на_резисторе = ADC_reading * (Vref / 4095)). +// Сначала находим ток диагностики: I_IS = U / R = 1.1 В / 1200 Ом ≈ 0.000917 А (0.917 мА). +// Затем находим ток нагрузки: I_мотора = I_IS * kILIS = 0.000917 А * 550 ≈ 0.504 А. +// kILIS = 550 (константа микросхемы из документации) +// Результат: ток через мотор составляет примерно 0.5 А. +// IL(NOM)1 - номинальный ток нагрузки при активном одном канале (2А) +// IL(NOM)2 - номинальный ток нагрузки при активных двух каналах (1.5А) + +// IL(SC) — ток нагрузки в режиме короткого замыкания (ограниченный схемой защиты) +// 5 В Минимум 8 А (типично ~10 А) +// 28 В Типично 4 А (IL28(SC)) + +// IL(OL) (5-30 mA) — пороговый ток для обнаружения обрыва нагрузки (Open Load), когда канал включен. Если IL < IL(OL), система диагностирует обрыв + + +typedef struct { + tGpioPin Incar_Motor_Front_EN; // Канал 0 (1 - ВКЛ) + tGpioPin Incar_EN_Diag; // Разрешение диагностики (1 - ВКЛ) + tGpioPin Incar_SEL_Diag; // Вывод диагностики (0 - Канал 0; 1 - Канал 1) + tGpioPin Incar_Motor_Rear_EN; // Канал 1 (1 - ВКЛ) +} tBTS5180_2EKA_FrontAndRearIncarMotor; + +typedef struct { + tGpioPin TwoWayValve_EN; // Канал 0 (1 - ВКЛ) + tGpioPin TwoWayValve_EN_Diag; // Разрешение диагностики (1 - ВКЛ) + tGpioPin TwoWayValve_SEL_Diag; // Вывод диагностики (0 - Канал 0; 1 - Канал 1) + tGpioPin ReservePower_EN; // Канал 1 (1 - ВКЛ) +} tBTS5180_2EKA_TwoWayValveAndReservePowerSupply; + +typedef struct { + tGpioPin PtcRelayDriver1_EN; // Канал 0 (1 - ВКЛ) + tGpioPin PtcRelayDriver_EN_Diag; // Разрешение диагностики (1 - ВКЛ) + tGpioPin PtcRelayDriver_SEL_Diag; // Вывод диагностики (0 - Канал 0; 1 - Канал 1) + tGpioPin PtcRelayDriver2_EN; // Канал 1 (1 - ВКЛ) +} tBTS5180_2EKA_2xChannelPTCPowerControl; + +typedef struct { + tGpioPin ShutOffFront_EN; // Канал 0 (1 - ВКЛ) + tGpioPin ShutOff_EN_Diag; // Разрешение диагностики (1 - ВКЛ) + tGpioPin ShutSel_SEL_Diag; // Вывод диагностики (0 - Канал 0; 1 - Канал 1) + tGpioPin ShutOffRear_EN; // Канал 1 (1 - ВКЛ) +} tBTS5180_2EKA_ShutOFFValveFrontRear; + +typedef struct { + tGpioPin EN_ReservePower; // Резервный источник разрешение (1 - ВКЛ) + tGpioPin ST_ReservePower; // Резервный источник состояния состояние (1 - ошибок нет) +} tBTS4175SGAXUMA1_ReservePowerOutput; + +typedef struct { + tGpioPin LIN_ActPower_AB; // Основной сигнал включения/выключения силового канала (выхода OUTPUT) (1 - ВКЛ) + tGpioPin Fault_RST_AB; + tGpioPin EN_CurrentSensing_AB; // Разрешение диагностики +} tVN7008AJ_FrontLINActuatorPowerDriverAB; + +typedef struct { + tGpioPin LIN_ActPower_C; // Основной сигнал включения/выключения силового канала (выхода OUTPUT) (1 - ВКЛ) + tGpioPin Fault_RST_C; + tGpioPin EN_CurrentSensing_C; // Разрешение диагностики +} tVN7008AJ_RearLINActuatorPowerDriverC; + +typedef struct { + tGpioPin ShutOffTXV1_EN; // Канал 0 (1 - ВКЛ) + tGpioPin ShutOffTXV_EN_Diag; // Разрешение диагностики (1 - ВКЛ) + tGpioPin ShutSelTXV_SEL_Diag; // Вывод диагностики (0 - Канал 0; 1 - Канал 1) + tGpioPin ShutOffTXV2_EN; // Канал 1 (1 - ВКЛ) +} tBTS5120_2EKA_ShutoffValvePowerTXV; + +typedef struct { + tGpioPin EN_BATTChiller; // Холодильник разрешение (1 - ВКЛ) + tGpioPin ST_BATTChiller; // Холодильник состояния (1 - ошибок нет) +} tBTS4175SGAXUMA1_ShutOFFValveBatteryChiller; + +typedef struct { + tGpioPin EN_PowerReserve; // (1 - ВКЛ) + tGpioPin ST_PowerReserve; // (1 - ошибок нет) +} tBTS4175SGAXUMA1_PowerReserve; + +/* +typedef struct { + uint8_t SW5V_EN; + uint8_t PBATT_CK_EN; + uint8_t Incar_Motor_Front_EN; + uint8_t Incar_Motor_Rear_EN; + uint8_t TwoWayValve_EN; + uint8_t ReservePower_EN; + uint8_t PtcRelayDriver1_EN; + uint8_t PtcRelayDriver2_EN; + uint8_t ShutOffFront_EN; + uint8_t ShutOffRear_EN; + uint8_t EN_ReservePower; + uint8_t LIN_ActPower_AB; + uint8_t LIN_ActPower_C; + uint8_t ShutOffTXV1_EN; + uint8_t ShutOffTXV2_EN; + uint8_t EN_BATTChiller; + uint8_t EN_PowerReserve; +} tPowerEnable; +*/ + + + + + + +typedef struct { + tTPS7B6850QPWPRQ1 TPS7B6850QPWPRQ1; + tGpioPin PBATT_CK_EN; // Контроль напряжения борт-сети (1 - ВКЛ) + tGpioPin SW5V_EN; // Включение 5V (0 - ВКЛ) + tBTS5180_2EKA_FrontAndRearIncarMotor BTS5180_2EKA_FrontRearIncarMotor; + tBTS5180_2EKA_TwoWayValveAndReservePowerSupply BTS5180_2EKA_TwoWayValveAndReservePowerSupply; + tBTS5180_2EKA_2xChannelPTCPowerControl BTS5180_2EKA_2xChannelPTCPower; + tBTS5180_2EKA_ShutOFFValveFrontRear BTS5180_2EKA_ShutOFFValveFrontRear; + tBTS4175SGAXUMA1_ReservePowerOutput BTS4175SGAXUMA1_ReservePowerOutput; + tBTS4175SGAXUMA1_ShutOFFValveBatteryChiller BTS4175SGAXUMA1_ShutOFFValveBatteryChiller; + tBTS4175SGAXUMA1_PowerReserve BTS4175SGAXUMA1_PowerReserve; + tVN7008AJ_FrontLINActuatorPowerDriverAB VN7008AJ_FrontLINActuatorPowerDriverAB; + tVN7008AJ_RearLINActuatorPowerDriverC VN7008AJ_RearLINActuatorPowerDriverC; + tBTS5120_2EKA_ShutoffValvePowerTXV BTS5120_2EKA_ShutoffValvePowerTXV; +} tPower; + +typedef struct { + tLed led; + tPower power; + tGpioPin EmergencyAirCleanSwitch; + tGpioPin FireExtinguishSwitch; +// tGpioPin Ign_Wakeup; +} tGpios; + +extern tGpios GPIOS; + +void Gpios_Init(); + +#endif //HVAC_M7_GPIOS_H diff --git a/MODULES/HVAC_M7_GpioPins/modular.json b/MODULES/HVAC_M7_GpioPins/modular.json new file mode 100644 index 0000000..478dd70 --- /dev/null +++ b/MODULES/HVAC_M7_GpioPins/modular.json @@ -0,0 +1,22 @@ +{ + "dep": [ + { + "type": "local", + + "dir": "./MODULES/GpioPin_Flagchip_FC7240" + }, + { + "type": "local", + + "dir": "./MODULES/SystemDelay_CMSIS_RTOS" + } + ], + "cmake": { + "inc_dirs": [ + "./" + ], + "srcs": [ + "Gpios.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_HardFault/HardFault.c b/MODULES/HVAC_M7_HardFault/HardFault.c new file mode 100644 index 0000000..3e826ac --- /dev/null +++ b/MODULES/HVAC_M7_HardFault/HardFault.c @@ -0,0 +1,54 @@ +// +// Created by cfif on 14.07.2026. +// +#include "HardFault.h" +#include CMSIS_device_header +#include "cmsis_os2.h" +#include "InternalFlashPage.h" + +extern uint32_t __StackTop; + +#define START_FLASH_ADR 0x04001000 + +#define CODE_START (0x01000000 + 64 * 1024) +#define CODE_END (CODE_START + 704 * 1024) // или используйте символ из линкера + +__attribute__((section(".save_data"))) volatile uint32_t hardFault_addresses[SIZE_BUF_HARD_FAULT]; // массив для адресов возврата (достаточно 32) +__attribute__((section(".save_data"))) volatile uint32_t hardFault_count; +__attribute__((section(".save_data"))) volatile uint32_t hardFault_magic; + +void vTaskGetCurrentTaskStackInfo(void **ppvStackStart, void **ppvStackEnd); + +void HardFault_C_Handler(uint32_t *sp, uint32_t stack_flag) { + + uint32_t *src = sp; + + const uint32_t max_ret = sizeof(hardFault_addresses) / sizeof(uint32_t) - 1; + uint32_t *stack_end = NULL; + + if (stack_flag == 0) { // Использовался MSP – стек ядра + //src += 8; // пропускаем контекст + stack_end = &__StackTop; + } else { // Использовался PSP – стек задачи + void *pvStackStart, *pvStackEnd; + vTaskGetCurrentTaskStackInfo(&pvStackStart, &pvStackEnd); + // uint32_t *stack_start = (uint32_t *) pvStackStart; + stack_end = (uint32_t *) pvStackEnd; + } + + hardFault_count = 0; + + while (src < stack_end && hardFault_count < max_ret) { + uint32_t val = *src; + // Проверяем, принадлежит ли значение области кода + if (val >= CODE_START && val < CODE_END) { + hardFault_addresses[hardFault_count++] = val & ~1; // убираем Thumb-бит + } + src++; + } + + hardFault_magic = 0xDEADBEEF; + + NVIC_SystemReset(); + +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_HardFault/HardFault.h b/MODULES/HVAC_M7_HardFault/HardFault.h new file mode 100644 index 0000000..0a11983 --- /dev/null +++ b/MODULES/HVAC_M7_HardFault/HardFault.h @@ -0,0 +1,16 @@ +// +// Created by cfif on 14.07.2026. +// + +#ifndef HVAC_M7_HARDFAULT_H +#define HVAC_M7_HARDFAULT_H + +#include "stdint.h" + +#define SIZE_BUF_HARD_FAULT 32 + +extern __attribute__((section(".ncache_bss"))) volatile uint32_t hardFault_addresses[32]; +extern __attribute__((section(".ncache_bss"))) volatile uint32_t hardFault_count; +extern __attribute__((section(".ncache_bss"))) volatile uint32_t hardFault_magic; + +#endif //HVAC_M7_HARDFAULT_H diff --git a/MODULES/HVAC_M7_HardFault/HardFault.s b/MODULES/HVAC_M7_HardFault/HardFault.s new file mode 100644 index 0000000..f1a61a3 --- /dev/null +++ b/MODULES/HVAC_M7_HardFault/HardFault.s @@ -0,0 +1,21 @@ +.syntax unified +.thumb +.section .text +.global HardFault_Handler +.type HardFault_Handler, %function + +HardFault_Handler: + // Проверяем бит 2 в LR: если 1, то использовался PSP, иначе MSP + TST LR, #4 + BNE UsePSP +UseMSP: + MRS R0, MSP // R0 = указатель MSP + MOVS R1, #0 // R1 = флаг 0 (MSP) + B CallHandler +UsePSP: + MRS R0, PSP // R0 = указатель PSP + MOVS R1, #1 // R1 = флаг 1 (PSP) +CallHandler: + LDR R2, =HardFault_C_Handler + BX R2 + .size HardFault_Handler, . - HardFault_Handler \ No newline at end of file diff --git a/MODULES/HVAC_M7_HardFault/modular.json b/MODULES/HVAC_M7_HardFault/modular.json new file mode 100644 index 0000000..388b3da --- /dev/null +++ b/MODULES/HVAC_M7_HardFault/modular.json @@ -0,0 +1,11 @@ +{ + "cmake": { + "inc_dirs": [ + "./" + ], + "srcs": [ + "./**.c", + "./**.s" + ] + } +} diff --git a/MODULES/HVAC_M7_Indication/Indication.c b/MODULES/HVAC_M7_Indication/Indication.c new file mode 100644 index 0000000..f719e98 --- /dev/null +++ b/MODULES/HVAC_M7_Indication/Indication.c @@ -0,0 +1,57 @@ +// +// Created by cfif on 11.10.23. +// +#include "Indication.h" +#include +#include + +tStringStatic eDeviceModesNames[] = { + StringStaticInit("Запуск"), + StringStaticInit("Работа") +}; + +static void Indication_Update(tIndication *env) { + env->currentModeName = StringStaticGetLink(&eDeviceModesNames[env->mode]); + + env->tick = ((env->tick + 1) % 10); +} + +void Indication_Init( + tIndication *env, + eHvacDevModes initMode +) { + + env->mode = initMode; + Indication_Update(env); + + InitThreadAtrStatic(&env->thread.attr, "Indication", env->thread.controlBlock, env->thread.stack, osPriorityNormal); + env->thread.id = 0; +} + +void Indication_SetMode(tIndication *env, eHvacDevModes mode) { + if (env->mode != mode) { + env->mode = mode; + Indication_Update(env); + } +} + +static _Noreturn void Indication_Thread(tIndication *env) { + for (;;) { + Indication_Update(env); + SystemDelayMs(100); + } +} + +void Indication_StartThread(tIndication *env) { + if (!env->thread.id) { + env->thread.id = osThreadNew((osThreadFunc_t) (Indication_Thread), (void *) (env), &env->thread.attr); + } else { + osThreadResume(env->thread.id); + } +} + +void Indication_StopThread(tIndication *env) { + if (env->thread.id) { + osThreadSuspend(env->thread.id); + } +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_Indication/Indication.h b/MODULES/HVAC_M7_Indication/Indication.h new file mode 100644 index 0000000..862b83a --- /dev/null +++ b/MODULES/HVAC_M7_Indication/Indication.h @@ -0,0 +1,35 @@ +// +// Created by cfif on 11.10.23. +// + +#ifndef ERA_ELEMENT_2_INDICATION_H +#define ERA_ELEMENT_2_INDICATION_H + +#include +#include + +typedef enum { + HVAC_DEV_MODE_STARTUP = 0, + HVAC_DEV_MODE_RUN = 1 +} eHvacDevModes; + +typedef struct { + eHvacDevModes mode; + tStringLink currentModeName; + + uint16_t tick; + + struct { + osThreadId_t id; + uint32_t stack[128]; + StaticTask_t controlBlock; + osThreadAttr_t attr; + } thread; +} tIndication; + +void Indication_Init(tIndication *env, eHvacDevModes initMode); +void Indication_SetMode(tIndication *env, eHvacDevModes mode); +void Indication_StartThread(tIndication *env); +void Indication_StopThread(tIndication *env); + +#endif //ERA_ELEMENT_2_INDICATION_H diff --git a/MODULES/HVAC_M7_Indication/modular.json b/MODULES/HVAC_M7_Indication/modular.json new file mode 100644 index 0000000..0dd1901 --- /dev/null +++ b/MODULES/HVAC_M7_Indication/modular.json @@ -0,0 +1,10 @@ +{ + "cmake": { + "inc_dirs": [ + "./" + ], + "srcs": [ + "./**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_LIN_TASKS/LinActuatorTasks.c b/MODULES/HVAC_M7_LIN_TASKS/LinActuatorTasks.c new file mode 100644 index 0000000..af420d1 --- /dev/null +++ b/MODULES/HVAC_M7_LIN_TASKS/LinActuatorTasks.c @@ -0,0 +1,1385 @@ +// +// Created by cfif on 05.04.2024. +// +#include +#include "LinActuatorTasks.h" +#include "CmsisRtosThreadUtils.h" +#include "CanPorts.h" +#include "fc7xxx_driver_lin.h" +#include "Lins.h" +#include "LoggerInterface.h" +#include "string.h" +#include "LinActuatorWork.h" +#include "HVAC_model.h" + +//#define LOG_SIGN "Lin0" +#define LOGGER env->logger + + +void GetLin123CallbackHandler(tLinData *env, uint8_t u8LinIndex, void *state) { + lin_xfer_state_t *pXferState = state; + //uint32_t s_countIndex = 0U; + //bool s_rxError = false; + + //LIN_DrvSetTimeOutCounter(u8LinIndex, 500); + + switch (pXferState->currentEventId) { + case LIN_PID_OK: + + if (env->direction == LIN_DIRECTION_SET) { + LIN_DrvSendFrameNonBlocking(u8LinIndex, env->g_aTxBuffer, env->g_aTxBufferLen); + return; + } else if (env->direction == LIN_DIRECTION_GET) { + LIN_DrvReceiveFrameNonBlocking(u8LinIndex, env->g_aRxBuffer, env->g_aRxBufferLen); + return; + } else { + // Misra check. + uint8_t data = LIN_TIMEOUT; + osMessageQueuePut(env->rxDataQueue, &data, 0x0, 0U); + return; + } + + break; + case LIN_PID_ERROR: + // Go to idle mode +// LIN_DrvGoToIdleMode(u8LinIndex); + // FCUART_Printf(DEBUG_FCUART_INSTANCE, "Receive PID error!\r\n"); + break; + case LIN_TX_COMPLETED: + // Go to IDLE state. +// LIN_DrvGoToIdleMode(u8LinIndex); + // FCUART_Printf(DEBUG_FCUART_INSTANCE, "This test case will send data to slave node. Send data: \r\n"); + // for (s_countIndex = 0U; s_countIndex < sizeof(g_aTxBuffer); s_countIndex++) { + // FCUART_Printf(DEBUG_FCUART_INSTANCE, " 0x%x ", g_aTxBuffer[s_countIndex]); + // } + // FCUART_Printf(DEBUG_FCUART_INSTANCE, "\r\nMaster node send complete! \r\n"); + break; + case LIN_RX_COMPLETED: + // Go to idle mode +// LIN_DrvGoToIdleMode(u8LinIndex); + + // FCUART_Printf(DEBUG_FCUART_INSTANCE, "Master node receive data:\r\n"); + //for (s_countIndex = 0U; s_countIndex < sizeof(env->g_aRxBuffer); s_countIndex++) { + // FCUART_Printf(DEBUG_FCUART_INSTANCE, " 0x%x ", g_aRxBuffer[s_countIndex]); + //if (env->g_aRxBuffer[s_countIndex] != (env->g_aTxBuffer[s_countIndex] + 1U)) { + // s_rxError = true; + //} + + //env->g_aRxBuffer[s_countIndex] = 0U; + //} + + //if (true == s_rxError) { + // FCUART_Printf(DEBUG_FCUART_INSTANCE, "\r\nReceived data Error\r\n"); + //} else { + // FCUART_Printf(DEBUG_FCUART_INSTANCE, "\r\nReveiced data matched!\r\n"); + //} + break; + case LIN_CHECKSUM_ERROR: + // FCUART_Printf(DEBUG_FCUART_INSTANCE, "Receive checksum byte error!\r\n"); + break; + case LIN_READBACK_ERROR: + // FCUART_Printf(DEBUG_FCUART_INSTANCE, "Read back error!\r\n"); + break; + case LIN_FRAME_ERROR: + break; + case LIN_RECV_BREAK_FIELD_OK: + break; + case LIN_WAKEUP_SIGNAL: + // FCUART_Printf(DEBUG_FCUART_INSTANCE, "Wake up signal received!\r\n"); + //LIN_DrvGoToIdleMode(u8LinIndex); + break; + case LIN_TIMEOUT: + // FCUART_Printf(DEBUG_FCUART_INSTANCE, "LIN transfer timeout occurred!\r\n"); + break; + case LIN_SYNC_ERROR: + break; + case LIN_BAUDRATE_ADJUSTED: + break; + case LIN_NO_EVENT: + break; + case LIN_SYNC_OK: + break; + default: + // do nothing + break; + } + + osMessageQueuePut(env->rxDataQueue, (uint8_t *) &pXferState->currentEventId, 0x0, 0U); +} + +static lin_event_id_t SEND_ACTUATOR_COM_x(tLinIO *linIo, uint8_t COM_ADR) { + lin_event_id_t res = linIo->runCommand(linIo->env, COM_ADR, 40); +// SystemDelayMs(30); + return res; +} + + +static lin_event_id_t DFR_PRG_x(tLinIO *linIo, tLinData *linData, + uint8_t BUS_ADR) { + lin_event_id_t res; + + linData->direction = LIN_DIRECTION_SET; + linData->g_aTxBufferLen = sizeof(ACT_DFR_PRG); + linData->g_aRxBufferLen = 0; + + ACT_DFR_PRG *ACT_DFR_PRG_ = (ACT_DFR_PRG *) linData->g_aTxBuffer; + ACT_DFR_PRG_->BUS_ADR = BUS_ADR; + ACT_DFR_PRG_->Data1_DFR_PRG = 0xFF; + + uint8_t retry = 1; + + while (retry) { + + res = SEND_ACTUATOR_COM_x(linIo, DFR_PRG); + + SystemDelayMs(50); + + if (res == LIN_TX_COMPLETED) { + break; + } + + --retry; + } + + return res; +} + +static lin_event_id_t RFR_PRG_x(tLinIO *linIo, tLinData *linData, uint8_t BUS_ADDRESS, + uint8_t *BUS_ADR, + uint8_t *BUS_NEW_ADR, + uint8_t *NOTL_DREH_Master, + uint8_t *NOTL_ENAB_Master, + uint8_t *DREH_Slave, + uint8_t *ParitySlave, + uint8_t *Version_CFR) { + lin_event_id_t res; + + ACT_RFR_PRG *ACT_RFR_PRG_ = (ACT_RFR_PRG *) linData->g_aRxBuffer; + + uint8_t retry = 3; + + while (retry) { + + res = DFR_PRG_x(linIo, linData, BUS_ADDRESS); + + if (res == LIN_TX_COMPLETED) { + + linData->direction = LIN_DIRECTION_GET; + + linData->g_aTxBufferLen = 0; + linData->g_aRxBufferLen = sizeof(ACT_RFR_PRG); + + res = SEND_ACTUATOR_COM_x(linIo, RFR_PRG); + + if (res == LIN_RX_COMPLETED) { + *BUS_ADR = ACT_RFR_PRG_->BUS_ADR; + *BUS_NEW_ADR = ACT_RFR_PRG_->BUS_NEW_ADR; + *NOTL_DREH_Master = ACT_RFR_PRG_->NOTL_DREH_Master; + *NOTL_ENAB_Master = ACT_RFR_PRG_->NOTL_ENAB_Master; + *DREH_Slave = ACT_RFR_PRG_->DREH_Slave; + *ParitySlave = ACT_RFR_PRG_->ParitySlave; + *Version_CFR = ACT_RFR_PRG_->Version_CFR; + + break; + } + + } + + --retry; + } + + return res; +} + + +static lin_event_id_t DFR_IDE_x(tLinIO *linIo, tLinData *linData, + uint8_t BUS_ADR) { + lin_event_id_t res; + + linData->direction = LIN_DIRECTION_SET; + linData->g_aTxBufferLen = sizeof(ACT_DFR_IDE); + linData->g_aRxBufferLen = 0; + + ACT_DFR_IDE *ACT_DFR_IDE_ = (ACT_DFR_IDE *) linData->g_aTxBuffer; + ACT_DFR_IDE_->BUS_ADR = BUS_ADR; + ACT_DFR_IDE_->Data1_DFR_IDE = 0xFF; + + uint8_t retry = 1; + + while (retry) { + + res = SEND_ACTUATOR_COM_x(linIo, DFR_IDE); + + if (res == LIN_TX_COMPLETED) { + break; + } + + --retry; + } + + return res; +} + +static lin_event_id_t RFR_IDE_x(tLinIO *linIo, tLinData *linData, uint8_t BUS_ADDRESS, + uint8_t *BUS_ADR, + uint8_t *IDE_ref, + uint8_t *IDE_Sup, + uint8_t *IDE_Har) { + lin_event_id_t res; + + ACT_RFR_IDE *ACT_RFR_IDE_ = (ACT_RFR_IDE *) linData->g_aRxBuffer; + + uint8_t retry = 3; + + while (retry) { + + res = DFR_IDE_x(linIo, linData, BUS_ADDRESS); + + if (res == LIN_TX_COMPLETED) { + + linData->direction = LIN_DIRECTION_GET; + + linData->g_aTxBufferLen = 0; + linData->g_aRxBufferLen = sizeof(ACT_RFR_IDE); + + res = SEND_ACTUATOR_COM_x(linIo, RFR_IDE); + + if (res == LIN_RX_COMPLETED) { + *BUS_ADR = ACT_RFR_IDE_->BUS_ADR; + *IDE_ref = ACT_RFR_IDE_->IDE_ref; + *IDE_Sup = ACT_RFR_IDE_->IDE_Sup; + *IDE_Har = ACT_RFR_IDE_->IDE_Har; + + break; + } + + } + + --retry; + } + + return res; +} + +static lin_event_id_t DFR_STA_x(tLinIO *linIo, tLinData *linData, uint8_t BUS_ADR) { + lin_event_id_t res; + + linData->direction = LIN_DIRECTION_SET; + linData->g_aTxBufferLen = sizeof(ACT_DFR_STA); + linData->g_aRxBufferLen = 0; + + ACT_DFR_STA *ACT_DFR_STA_ = (ACT_DFR_STA *) linData->g_aTxBuffer; + ACT_DFR_STA_->BUS_ADR = BUS_ADR; + ACT_DFR_STA_->Data1_DFR_STA = 0xFF; + + uint8_t retry = 1; + + while (retry) { + + res = SEND_ACTUATOR_COM_x(linIo, DFR_STA); + + if (res == LIN_TX_COMPLETED) { + break; + } + + --retry; + } + + return res; +} + +static lin_event_id_t RFR_STA_x(tLinIO *linIo, tLinData *linData, uint8_t BUS_ADDRESS, + uint8_t *BUS_ADR, + uint16_t *CPOS_ALL, + eEmrf_Slave_STA *Emrf_Slave, + eMode_Mod *Mode_Slave, + uint8_t *Error1_Supply_Slave, + uint8_t *Error2_Communication_Slave, + uint8_t *Error3_Temperature_Slave, + uint8_t *Error4_Permanent_Electrical_Slave, + eStall_STA *Stall_Slave, + eReset_STA *Reset_Slave) { + lin_event_id_t res; + + ACT_RFR_STA *ACT_RFR_STA_ = (ACT_RFR_STA *) linData->g_aRxBuffer; + + uint8_t retry = 1; + + while (retry) { + + res = DFR_STA_x(linIo, linData, BUS_ADDRESS); + + if (res == LIN_TX_COMPLETED) { + + linData->direction = LIN_DIRECTION_GET; + + linData->g_aTxBufferLen = 0; + linData->g_aRxBufferLen = sizeof(ACT_RFR_STA); + + res = SEND_ACTUATOR_COM_x(linIo, RFR_STA); + + if (res == LIN_RX_COMPLETED) { + + *BUS_ADR = ACT_RFR_STA_->BUS_ADR; + *CPOS_ALL = ACT_RFR_STA_->CPOS_ALL; + *Emrf_Slave = ACT_RFR_STA_->Emrf_Slave; + *Mode_Slave = ACT_RFR_STA_->Mode_Slave; + *Error1_Supply_Slave = ACT_RFR_STA_->Error1_Supply_Slave; + *Error2_Communication_Slave = ACT_RFR_STA_->Error2_Communication_Slave; + *Error3_Temperature_Slave = ACT_RFR_STA_->Error3_Temperature_Slave; + *Error4_Permanent_Electrical_Slave = ACT_RFR_STA_->Error4_Permanent_Electrical_Slave; + *Stall_Slave = ACT_RFR_STA_->Stall_Slave; + *Reset_Slave = ACT_RFR_STA_->Reset_Slave; + + break; + } + + + } + + --retry; + } + + return res; +} + +static lin_event_id_t ISSR_x(tLinIO *linIo, tLinData *linData, uint8_t COM, + uint8_t *BLOCK_MT, + uint16_t *CPOS_ALL, + uint8_t *DIAGNOSE_MT) { + lin_event_id_t res; + + linData->direction = LIN_DIRECTION_GET; + linData->g_aTxBufferLen = 0; + linData->g_aRxBufferLen = sizeof(ACT_RFR_ISSR); + + uint8_t retry = 3; + + while (retry) { + + res = SEND_ACTUATOR_COM_x(linIo, COM); + + if (res == LIN_RX_COMPLETED) { + + ACT_RFR_ISSR *ACT_RFR_ISSR_ = (ACT_RFR_ISSR *) linData->g_aRxBuffer; + + *BLOCK_MT = ACT_RFR_ISSR_->BLOCK_MT; + *CPOS_ALL = ACT_RFR_ISSR_->CPOS_1_LSB_MT | (ACT_RFR_ISSR_->CPOS_1_MSB_MT << 7); + *DIAGNOSE_MT = ACT_RFR_ISSR_->DIAGNOSE_MT; + + break; + } + + --retry; + } + + + return res; + +} + +static lin_event_id_t CFR_MOD_x(tLinIO *linIo, tLinData *linData, uint8_t BUS_ADDRESS, + eMode_Mod Mode_Slave) { + lin_event_id_t res; + + linData->direction = LIN_DIRECTION_SET; + linData->g_aTxBufferLen = sizeof(ACT_CFR_MOD); + linData->g_aRxBufferLen = 0; + + ACT_CFR_MOD *ACT_CFR_MOD_ = (ACT_CFR_MOD *) linData->g_aTxBuffer; + ACT_CFR_MOD_->BUS_ADR = BUS_ADDRESS; + ACT_CFR_MOD_->Mode_Slave = Mode_Slave; + ACT_CFR_MOD_->Unused = 0x3F; + ACT_CFR_MOD_->Data2_Mod = 0xFF; + ACT_CFR_MOD_->Data3_Mod = 0xFF; + + uint8_t retry = 3; + + while (retry) { + + res = SEND_ACTUATOR_COM_x(linIo, CFR_MOD); + + if (res == LIN_TX_COMPLETED) { + break; + } + + --retry; + } + + return res; +} + +static lin_event_id_t CFR_INI_x(tLinIO *linIo, tLinData *linData, uint8_t BUS_ADDRESS, + uint16 INI_CPOS) { + lin_event_id_t res; + + linData->direction = LIN_DIRECTION_SET; + linData->g_aTxBufferLen = sizeof(ACT_CFR_INI); + linData->g_aRxBufferLen = 0; + + ACT_CFR_INI *ACT_CFR_INI_ = (ACT_CFR_INI *) linData->g_aTxBuffer; + ACT_CFR_INI_->BUS_ADR = BUS_ADDRESS; + ACT_CFR_INI_->INI_CPOS = INI_CPOS; + ACT_CFR_INI_->unused = 0x1; + ACT_CFR_INI_->Not_Used_INI = 0xFF; + + uint8_t retry = 3; + + while (retry) { + + res = SEND_ACTUATOR_COM_x(linIo, CFR_INI); + + if (res == LIN_TX_COMPLETED) { + break; + } + + --retry; + } + + return res; +} + +static lin_event_id_t CFR_SET_x(tLinIO *linIo, tLinData *linData, uint8_t BUS_ADDRESS, + uint16 FINAL_POS, + eStall_SET Stall_SET, + eLnoise_SET Lnoise_SET, + eAutos_SET Autos_SET, + eSpeed_SET Speed_SET, + eCoils_Stop_SET Coils_Stop_SET) { + lin_event_id_t res; + + linData->direction = LIN_DIRECTION_SET; + linData->g_aTxBufferLen = sizeof(ACT_CFR_SET); + linData->g_aRxBufferLen = 0; + + ACT_CFR_SET *ACT_CFR_SET_ = (ACT_CFR_SET *) linData->g_aTxBuffer; + ACT_CFR_SET_->BUS_ADR = BUS_ADDRESS; + + ACT_CFR_SET_->FINAL_POS = FINAL_POS; + ACT_CFR_SET_->unused = 1; + + ACT_CFR_SET_->Unused_SET = 0; + ACT_CFR_SET_->Stall_SET = Stall_SET; + ACT_CFR_SET_->Lnoise_SET = Lnoise_SET; + ACT_CFR_SET_->Autos_SET = Autos_SET; + ACT_CFR_SET_->Speed_SET = Speed_SET; + ACT_CFR_SET_->Coils_Stop_SET = Coils_Stop_SET; + + + uint8_t retry = 3; + + while (retry) { + + res = SEND_ACTUATOR_COM_x(linIo, CFR_SET); + + if (res == LIN_TX_COMPLETED) { + break; + } + + --retry; + } + + return res; +} + +/* +static lin_event_id_t CFR_PRG_x(tLinIO *linIo, tLinData *linData, uint8_t BUS_ADDRESS, + uint16_t BUS_NEW_ADR, + uint8_t NOTL_DREH_Master, + uint8_t NOTL_ENAB_Master, + uint8_t DREH_Master, + uint8_t Motor, + uint8_t Baudrate, + uint8_t Version_CFR) { + lin_event_id_t res; + + linData->direction = LIN_DIRECTION_SET; + linData->g_aTxBufferLen = sizeof(ACT_CFR_SET); + linData->g_aRxBufferLen = 0; + + ACT_CFR_PRG *ACT_CFR_PRG_ = (ACT_CFR_PRG *) linData->g_aTxBuffer; + ACT_CFR_PRG_->BUS_ADR = BUS_ADDRESS; + ACT_CFR_PRG_->BUS_NEW_ADR = BUS_NEW_ADR; + ACT_CFR_PRG_->NOTL_DREH_Master = NOTL_DREH_Master; + ACT_CFR_PRG_->NOTL_ENAB_Master = NOTL_ENAB_Master; + ACT_CFR_PRG_->DREH_Master = DREH_Master; + ACT_CFR_PRG_->Motor = Motor; + ACT_CFR_PRG_->Baudrate = Baudrate; + ACT_CFR_PRG_->Free = 0xFF; + ACT_CFR_PRG_->Version_CFR = Version_CFR; + + uint8_t retry = 3; + + while (retry) { + + res = SEND_ACTUATOR_COM_x(linIo, CFR_PRG); + + if (res == LIN_TX_COMPLETED) { + break; + } + + --retry; + } + + return res; +} +*/ +static bool isBroadCast(tLinTaskActuator *env) { + + for (uint8_t j = 0; j < env->LIN_ISSR_ALL; ++j) { + if (env->linCommandActuator[j].BUS_ADR != 0) { + return false; + } + } + + return true; +} + +static bool setState20(tLinTaskActuator *env, bool isError, uint8_t index) { + + if (isError) { + env->linStateActuator[index].error_connect = 1; + } else { + env->linStateActuator[index].error_connect = 0; + } + + env->linCommandActuator[index].COM = LIN_ACT_CFR_SUCCESSFUL; + env->linCommandActuator[index].isRFR_STA = 1; + + env->linStateActuator[index].Stall_Slave = LIN_STALL_STA_OFF; + + if (env->linCommandActuator[index].BUS_ADR == 0) { + + if (isBroadCast(env)) { + + for (uint8_t j = 0; j < env->LIN_ISSR_ALL; ++j) { + + env->linCommandActuator[j].COM = LIN_ACT_CFR_SUCCESSFUL; + env->linCommandActuator[j].isRFR_STA = 1; + + env->linStateActuator[j].Stall_Slave = LIN_STALL_STA_OFF; + + if (isError) { + env->linStateActuator[j].error_connect = 1; + } else { + env->linStateActuator[j].error_connect = 0; + } + } + + return true; + } + } + + return false; +} + +#if (LOG_LIN_ACTUATOR == 1) +#define IS_LOGGING_ENABLED(numAct) \ + ( (numAct == 1 && LOG_LIN1_ACTUATOR == 1) || \ + (numAct == 2 && LOG_LIN2_ACTUATOR == 1) || \ + (numAct == 3 && LOG_LIN3_ACTUATOR == 1) ) +#endif + + +static lin_event_id_t Lin_Scheduler(tLinTaskActuator *env, uint8_t numAct) { + + lin_event_id_t ret = LIN_NO_EVENT; + + if (isBroadCast(env)) { + +//--------------------------------------BROADCAST--------------------------------------------------------- +//--------------------------------------BROADCAST--------------------------------------------------------- +//--------------------------------------BROADCAST--------------------------------------------------------- + if (env->linCommandActuator[0].COM == LIN_ACT_CFR_MOD) { + +#if (LOG_LIN_ACTUATOR == 1) + if (IS_LOGGING_ENABLED(numAct)) { + LoggerFormatTrace(LOGGER, env->SIGN_LOG, + "Sending a command (BROADCAST): LIN_ACT_CFR_MOD (ADR = %d MODE = %d)", + env->linCommandActuator[0].BUS_ADR, + env->linCommandActuator[0].MODE) + } +#endif + ret = CFR_MOD_x(env->linIo, env->linData, env->linCommandActuator[0].BUS_ADR | 0x20, + env->linCommandActuator[0].MODE); + + if (ret == LIN_TX_COMPLETED) { +#if (LOG_LIN_ACTUATOR == 1) + if (IS_LOGGING_ENABLED(numAct)) { + LoggerFormatTrace(LOGGER, env->SIGN_LOG, + "Command completed successfully (BROADCAST): LIN_ACT_CFR_MOD (ADR = %d MODE = %d)", + env->linCommandActuator[0].BUS_ADR, + env->linCommandActuator[0].MODE) + } +#endif + setState20(env, false, 0); + } else { +#if (LOG_LIN_ACTUATOR == 1) + if (IS_LOGGING_ENABLED(numAct)) { + + LoggerFormatError(LOGGER, env->SIGN_LOG, + "Command failed (BROADCAST): LIN_ACT_CFR_MOD (ADR = %d MODE = %d)", + env->linCommandActuator[0].BUS_ADR, + env->linCommandActuator[0].MODE) + } +#endif + setState20(env, true, 0); + } + + SystemDelayMs(30); + } + + + if (env->linCommandActuator[0].COM == LIN_ACT_CFR_INI) { +#if (LOG_LIN_ACTUATOR == 1) + if (IS_LOGGING_ENABLED(numAct)) { + LoggerFormatTrace(LOGGER, env->SIGN_LOG, + "Sending a command (BROADCAST): LIN_ACT_CFR_INI (ADR = %d POS = %d)", + env->linCommandActuator[0].BUS_ADR, + env->linCommandActuator[0].POS) + } +#endif + ret = CFR_INI_x(env->linIo, env->linData, + env->linCommandActuator[0].BUS_ADR | 0x20, + env->linCommandActuator[0].POS); + + if (ret == LIN_TX_COMPLETED) { +#if (LOG_LIN_ACTUATOR == 1) + if (IS_LOGGING_ENABLED(numAct)) { + LoggerFormatTrace(LOGGER, env->SIGN_LOG, + "Command completed successfully (BROADCAST): LIN_ACT_CFR_INI (ADR = %d POS = %d)", + env->linCommandActuator[0].BUS_ADR, env->linCommandActuator[0].POS) + } +#endif + setState20(env, false, 0); + + } else { +#if (LOG_LIN_ACTUATOR == 1) + if (IS_LOGGING_ENABLED(numAct)) { + LoggerFormatError(LOGGER, env->SIGN_LOG, + "Command failed (BROADCAST): LIN_ACT_CFR_INI (ADR = %d POS = %d)", + env->linCommandActuator[0].BUS_ADR, + env->linCommandActuator[0].POS) + } +#endif + setState20(env, true, 0); + } + + SystemDelayMs(30); + } + + + if (env->linCommandActuator[0].COM == LIN_ACT_CFR_SET) { +#if (LOG_LIN_ACTUATOR == 1) + if (IS_LOGGING_ENABLED(numAct)) { + LoggerFormatTrace(LOGGER, env->SIGN_LOG, + "Sending a command (BROADCAST): LIN_ACT_CFR_SET (ADR = %d POS = %d STALL= %d LNOISE = %d AUTOS = %d SPEED = %d COILS = %d)", + env->linCommandActuator[0].BUS_ADR, + env->linCommandActuator[0].POS, + env->linCommandActuator[0].Stall_SET, + env->linCommandActuator[0].Lnoise_SET, + env->linCommandActuator[0].Autos_SET, + env->linCommandActuator[0].Speed_SET, + env->linCommandActuator[0].Coils_Stop_SET + ) + } +#endif + ret = CFR_SET_x(env->linIo, env->linData, + env->linCommandActuator[0].BUS_ADR | 0x20, + env->linCommandActuator[0].POS, + env->linCommandActuator[0].Stall_SET, + env->linCommandActuator[0].Lnoise_SET, + env->linCommandActuator[0].Autos_SET, + env->linCommandActuator[0].Speed_SET, + env->linCommandActuator[0].Coils_Stop_SET); + + if (ret == LIN_TX_COMPLETED) { +#if (LOG_LIN_ACTUATOR == 1) + if (IS_LOGGING_ENABLED(numAct)) { + LoggerFormatTrace(LOGGER, env->SIGN_LOG, + "Command completed successfully (BROADCAST): LIN_ACT_CFR_SET (ADR = %d POS = %d STALL= %d LNOISE = %d AUTOS = %d SPEED = %d COILS = %d)", + env->linCommandActuator[0].BUS_ADR, + env->linCommandActuator[0].POS, + env->linCommandActuator[0].Stall_SET, + env->linCommandActuator[0].Lnoise_SET, + env->linCommandActuator[0].Autos_SET, + env->linCommandActuator[0].Speed_SET, + env->linCommandActuator[0].Coils_Stop_SET) + } +#endif + setState20(env, false, 0); + + } else { +#if (LOG_LIN_ACTUATOR == 1) + if (IS_LOGGING_ENABLED(numAct)) { + LoggerFormatError(LOGGER, env->SIGN_LOG, + "Command failed (BROADCAST): LIN_ACT_CFR_SET (ADR = %d POS = %d STALL= %d LNOISE = %d AUTOS = %d SPEED = %d COILS = %d)", + env->linCommandActuator[0].BUS_ADR, + env->linCommandActuator[0].POS, + env->linCommandActuator[0].Stall_SET, + env->linCommandActuator[0].Lnoise_SET, + env->linCommandActuator[0].Autos_SET, + env->linCommandActuator[0].Speed_SET, + env->linCommandActuator[0].Coils_Stop_SET + ) + } +#endif + setState20(env, true, 0); + + } + + SystemDelayMs(30); + } + + } else { + +//--------------------------------------NO BROADCAST--------------------------------------------------------- +//--------------------------------------NO BROADCAST--------------------------------------------------------- +//--------------------------------------NO BROADCAST--------------------------------------------------------- + + for (uint8_t i = 0; i < env->LIN_ISSR_ALL; ++i) { + + if (env->linCommandActuator[i].COM == LIN_ACT_CFR_MOD) { + + if (env->linCommandActuator[i].BUS_ADR == 0) { +#if (LOG_LIN_ACTUATOR == 1) + if (IS_LOGGING_ENABLED(numAct)) { + LoggerFormatTrace(LOGGER, env->SIGN_LOG, + "Let's skip the command: LIN_ACT_CFR_MOD (ADR = %d (%d) MODE = %d)", + env->linCommandActuator[i].BUS_ADR, i + 1, + env->linCommandActuator[i].MODE) + } +#endif + setState20(env, false, i); + continue; + } + +#if (LOG_LIN_ACTUATOR == 1) + if (IS_LOGGING_ENABLED(numAct)) { + LoggerFormatTrace(LOGGER, env->SIGN_LOG, + "Sending a command: LIN_ACT_CFR_MOD (ADR = %d (%d) MODE = %d)", + env->linCommandActuator[i].BUS_ADR, i, + env->linCommandActuator[i].MODE) + } +#endif + ret = CFR_MOD_x(env->linIo, env->linData, env->linCommandActuator[i].BUS_ADR | 0x20, + env->linCommandActuator[i].MODE); + + if (ret == LIN_TX_COMPLETED) { +#if (LOG_LIN_ACTUATOR == 1) + if (IS_LOGGING_ENABLED(numAct)) { + LoggerFormatTrace(LOGGER, env->SIGN_LOG, + "Command completed successfully: LIN_ACT_CFR_MOD (ADR = %d MODE = %d)", + env->linCommandActuator[i].BUS_ADR, + env->linCommandActuator[i].MODE) + } +#endif + setState20(env, false, i); + + + } else { +#if (LOG_LIN_ACTUATOR == 1) + if (IS_LOGGING_ENABLED(numAct)) { + LoggerFormatError(LOGGER, env->SIGN_LOG, + "Command failed [%d]: LIN_ACT_CFR_MOD (ADR = %d (%d) MODE = %d)", + env->linCommandActuator[i].BUS_ADR, i, + env->linCommandActuator[i].MODE) + } +#endif + setState20(env, true, i); + } + + SystemDelayMs(30); + } + + } + + for (uint8_t i = 0; i < env->LIN_ISSR_ALL; ++i) { + + if (env->linCommandActuator[i].COM == LIN_ACT_CFR_INI) { + + if (env->linCommandActuator[i].BUS_ADR == 0) { +#if (LOG_LIN_ACTUATOR == 1) + if (IS_LOGGING_ENABLED(numAct)) { + LoggerFormatTrace(LOGGER, env->SIGN_LOG, + "Let's skip the command: LIN_ACT_CFR_INI (ADR = %d (%d) POS = %d)", + env->linCommandActuator[i].BUS_ADR, i + 1, + env->linCommandActuator[i].POS) + } +#endif + setState20(env, false, i); + continue; + } + +#if (LOG_LIN_ACTUATOR == 1) + if (IS_LOGGING_ENABLED(numAct)) { + LoggerFormatTrace(LOGGER, env->SIGN_LOG, "Sending a command: LIN_ACT_CFR_INI (ADR = %d POS = %d)", + env->linCommandActuator[i].BUS_ADR, + env->linCommandActuator[i].POS) + } +#endif + ret = CFR_INI_x(env->linIo, env->linData, + env->linCommandActuator[i].BUS_ADR | 0x20, + env->linCommandActuator[i].POS); + + if (ret == LIN_TX_COMPLETED) { +#if (LOG_LIN_ACTUATOR == 1) + if (IS_LOGGING_ENABLED(numAct)) { + LoggerFormatTrace(LOGGER, env->SIGN_LOG, + "Command completed successfully: LIN_ACT_CFR_INI (ADR = %d POS = %d)", + env->linCommandActuator[i].BUS_ADR, env->linCommandActuator[i].POS) + } +#endif + setState20(env, false, i); + + } else { +#if (LOG_LIN_ACTUATOR == 1) + if (IS_LOGGING_ENABLED(numAct)) { + LoggerFormatError(LOGGER, env->SIGN_LOG, "Command failed: LIN_ACT_CFR_INI (ADR = %d POS = %d)", + env->linCommandActuator[i].BUS_ADR, + env->linCommandActuator[i].POS) + } +#endif + setState20(env, true, i); + + } + + SystemDelayMs(30); + } + } + + for (uint8_t i = 0; i < env->LIN_ISSR_ALL; ++i) { + + if (env->linCommandActuator[i].COM == LIN_ACT_CFR_SET) { + + if (env->linCommandActuator[i].BUS_ADR == 0) { +#if (LOG_LIN_ACTUATOR == 1) + if (IS_LOGGING_ENABLED(numAct)) { + LoggerFormatTrace(LOGGER, env->SIGN_LOG, + "Let's skip the command: LIN_ACT_CFR_SET (ADR = %d POS = %d (%d) STALL= %d LNOISE = %d AUTOS = %d SPEED = %d COILS = %d)", + env->linCommandActuator[i].BUS_ADR, i + 1, + env->linCommandActuator[i].POS, + env->linCommandActuator[i].Stall_SET, + env->linCommandActuator[i].Lnoise_SET, + env->linCommandActuator[i].Autos_SET, + env->linCommandActuator[i].Speed_SET, + env->linCommandActuator[i].Coils_Stop_SET) + } +#endif + setState20(env, false, i); + continue; + } + +#if (LOG_LIN_ACTUATOR == 1) + if (IS_LOGGING_ENABLED(numAct)) { + LoggerFormatTrace(LOGGER, env->SIGN_LOG, + "Sending a command: LIN_ACT_CFR_SET (ADR = %d POS = %d STALL= %d LNOISE = %d AUTOS = %d SPEED = %d COILS = %d)", + env->linCommandActuator[i].BUS_ADR, + env->linCommandActuator[i].POS, + env->linCommandActuator[i].Stall_SET, + env->linCommandActuator[i].Lnoise_SET, + env->linCommandActuator[i].Autos_SET, + env->linCommandActuator[i].Speed_SET, + env->linCommandActuator[i].Coils_Stop_SET) + } +#endif + ret = CFR_SET_x(env->linIo, env->linData, + env->linCommandActuator[i].BUS_ADR | 0x20, + env->linCommandActuator[i].POS, + env->linCommandActuator[i].Stall_SET, + env->linCommandActuator[i].Lnoise_SET, + env->linCommandActuator[i].Autos_SET, + env->linCommandActuator[i].Speed_SET, + env->linCommandActuator[i].Coils_Stop_SET); + + if (ret == LIN_TX_COMPLETED) { +#if (LOG_LIN_ACTUATOR == 1) + if (IS_LOGGING_ENABLED(numAct)) { + LoggerFormatTrace(LOGGER, env->SIGN_LOG, + "Command completed successfully: LIN_ACT_CFR_SET (ADR = %d POS = %d STALL= %d LNOISE = %d AUTOS = %d SPEED = %d COILS = %d)", + env->linCommandActuator[i].BUS_ADR, + env->linCommandActuator[i].POS, + env->linCommandActuator[i].Stall_SET, + env->linCommandActuator[i].Lnoise_SET, + env->linCommandActuator[i].Autos_SET, + env->linCommandActuator[i].Speed_SET, + env->linCommandActuator[i].Coils_Stop_SET + ) + } +#endif + setState20(env, false, i); + + } else { +#if (LOG_LIN_ACTUATOR == 1) + if (IS_LOGGING_ENABLED(numAct)) { + LoggerFormatError(LOGGER, env->SIGN_LOG, + "Command failed: LIN_ACT_CFR_SET (ADR = %d POS = %d STALL= %d LNOISE = %d AUTOS = %d SPEED = %d COILS = %d)", + env->linCommandActuator[i].BUS_ADR, + env->linCommandActuator[i].POS, + env->linCommandActuator[i].Stall_SET, + env->linCommandActuator[i].Lnoise_SET, + env->linCommandActuator[i].Autos_SET, + env->linCommandActuator[i].Speed_SET, + env->linCommandActuator[i].Coils_Stop_SET + ) + } +#endif + setState20(env, true, i); + + } + + SystemDelayMs(30); + } + } + + } // BroadCast + + + +/* + for (uint8_t i = 0; i < 255; ++i) { + + uint8_t BUS_ADR = 0; + uint16_t CPOS_ALL = 0; + eEmrf_Slave_STA Emrf_Slave = 0; + eMode_Mod Mode_Slave = 0; + uint8_t Error1_Supply_Slave = 0; + uint8_t Error2_Communication_Slave = 0; + uint8_t Error3_Temperature_Slave = 0; + uint8_t Error4_Permanent_Electrical_Slave = 0; + eStall_STA Stall_Slave = 0; + eReset_STA Reset_Slave = 0; + + ret = RFR_STA_x(env->linIo, env->linData, i | 0x20, + &BUS_ADR, + &CPOS_ALL, + &Emrf_Slave, + &Mode_Slave, + &Error1_Supply_Slave, + &Error2_Communication_Slave, + &Error3_Temperature_Slave, + &Error4_Permanent_Electrical_Slave, + &Stall_Slave, + &Reset_Slave); + + if (ret == LIN_RX_COMPLETED) { + LoggerFormatTrace(LOGGER, env->SIGN_LOG, "OK: State = %d", i) + } else { + + LoggerFormatTrace(LOGGER, env->SIGN_LOG, "ERROR: State = %d", i) + } + + } +*/ + + + + + + + + + + + for (uint8_t i = 0; i < env->LIN_ISSR_ALL; ++i) { +/* + uint8_t BLOCK_MT; + uint8_t DIAGNOSE_MT; + uint16_t CPOS_2_ALL; + + ret = ISSR_x(env->linIo, env->linData, + i, + &BLOCK_MT, + &CPOS_2_ALL, + &DIAGNOSE_MT); + + if (ret == LIN_RX_COMPLETED) { + env->linStateActuator[i].BLOCK_MT = BLOCK_MT; + env->linStateActuator[i].CPOS_2_ALL = CPOS_2_ALL << 1; + env->linStateActuator[i].DIAGNOSE_MT = DIAGNOSE_MT; + } +*/ + +// if ((env->linStateActuator[i].DIAGNOSE_MT) || (env->linCommandActuator[i].isRFR_STA)) { + if ((env->linCommandActuator[i].COM == LIN_ACT_CFR_NONE) || + (env->linCommandActuator[i].COM == LIN_ACT_CFR_SUCCESSFUL) || (env->linCommandActuator[i].isRFR_STA)) { + + env->linCommandActuator[i].isRFR_STA = 0; + + uint8_t BUS_ADR = 0; + uint16_t CPOS_ALL = 0; + eEmrf_Slave_STA Emrf_Slave = 0; + eMode_Mod Mode_Slave = 0; + uint8_t Error1_Supply_Slave = 0; + uint8_t Error2_Communication_Slave = 0; + uint8_t Error3_Temperature_Slave = 0; + uint8_t Error4_Permanent_Electrical_Slave = 0; + eStall_STA Stall_Slave = 0; + eReset_STA Reset_Slave = 0; + + ret = RFR_STA_x(env->linIo, env->linData, (i + 1) | 0x20, + &BUS_ADR, + &CPOS_ALL, + &Emrf_Slave, + &Mode_Slave, + &Error1_Supply_Slave, + &Error2_Communication_Slave, + &Error3_Temperature_Slave, + &Error4_Permanent_Electrical_Slave, + &Stall_Slave, + &Reset_Slave); + + if (ret == LIN_RX_COMPLETED) { + + BUS_ADR &= 0x1F; + + if (BUS_ADR > env->LIN_ISSR_ALL) { + asm("nop"); + } + + BUS_ADR = BUS_ADR - 1; + + + if (BUS_ADR != i) { + asm("nop"); + } + + if (BUS_ADR < env->LIN_ISSR_ALL) { + + if ((env->linStateActuator[BUS_ADR].CPOS_ALL != CPOS_ALL) || + (env->linStateActuator[BUS_ADR].Emrf_Slave != Emrf_Slave) || + (env->linStateActuator[BUS_ADR].Mode_Slave != Mode_Slave) || + + (env->linStateActuator[BUS_ADR].Reset_Slave != Reset_Slave) || + + (env->linStateActuator[BUS_ADR].Error1_Supply_Slave != Error1_Supply_Slave) || + (env->linStateActuator[BUS_ADR].Error2_Communication_Slave != Error2_Communication_Slave) || + (env->linStateActuator[BUS_ADR].Error3_Temperature_Slave != Error3_Temperature_Slave) || + (env->linStateActuator[BUS_ADR].Error4_Permanent_Electrical_Slave != + Error4_Permanent_Electrical_Slave) + ) { +#if (LOG_LIN_ACTUATOR == 1) + if (IS_LOGGING_ENABLED(numAct)) { + LoggerFormatTrace(LOGGER, env->SIGN_LOG, + "State: ADR = %d CPOS = %d Stall_Slave = %d Emrf = %d Mode = %d Reset = %d ErrSupply = %d ErrComm = %d ErrTemp = %d ErrElect = %d", + BUS_ADR + 1, + CPOS_ALL, + Stall_Slave, + Emrf_Slave, + Mode_Slave, + Reset_Slave, + Error1_Supply_Slave, + Error2_Communication_Slave, + Error3_Temperature_Slave, + Error4_Permanent_Electrical_Slave + ) + } +#endif + } + + env->linStateActuator[BUS_ADR].CPOS_ALL = CPOS_ALL; + env->linStateActuator[BUS_ADR].Emrf_Slave = Emrf_Slave; + env->linStateActuator[BUS_ADR].Mode_Slave = Mode_Slave; + env->linStateActuator[BUS_ADR].Error1_Supply_Slave = Error1_Supply_Slave; + env->linStateActuator[BUS_ADR].Error2_Communication_Slave = Error2_Communication_Slave; + env->linStateActuator[BUS_ADR].Error3_Temperature_Slave = Error3_Temperature_Slave; + env->linStateActuator[BUS_ADR].Error4_Permanent_Electrical_Slave = Error4_Permanent_Electrical_Slave; + + // Для защелкивания (после считывания Stall_Slave сбросится) + if (Stall_Slave == LIN_STALL_STA_ON) { + env->linStateActuator[BUS_ADR].Stall_Slave = Stall_Slave; +#if (LOG_LIN_ACTUATOR == 1) + if (IS_LOGGING_ENABLED(numAct)) { + LoggerFormatTrace(LOGGER, env->SIGN_LOG, "Detect STALL: (ADR = %d POS = %d)", + BUS_ADR + 1, + CPOS_ALL) + } +#endif + + } + + env->linStateActuator[BUS_ADR].Reset_Slave = Reset_Slave; + +// LoggerFormatTrace(LOGGER, env->SIGN_LOG, "BUS_ADR = %d, CPOS_ALL = %d, Stall_Slave = %d", BUS_ADR, +// env->linStateActuator[BUS_ADR].CPOS_ALL, +// env->linStateActuator[BUS_ADR].Stall_Slave) + + } else { + asm("nop"); + } + + + } else { + +//#if (LOG_LIN_ACTUATOR == 1) +// LoggerFormatTrace(LOGGER, env->SIGN_LOG, +// "Command READ - ERROR: ADR = %d ", +// i +// ) +//#endif + + + env->linStateActuator[i].error_connect = 1; + } + + + } + +// } else { +// env->linStateActuator[i].error_connect = 1; +// } + } + + if ((ret == LIN_TX_COMPLETED) || (ret == LIN_RX_COMPLETED)) { + + } else { + return ret; + } + + return LIN_NO_EVENT; +} + + +//начало----------------------------------------- LIN 1 ---------------------------------------------------------------- +//начало----------------------------------------- LIN 1 ---------------------------------------------------------------- +//начало----------------------------------------- LIN 1 ---------------------------------------------------------------- +//начало----------------------------------------- LIN 1 --------------------------------------------------------------- + +void Lin_1_Init(tLinTaskActuator *env, + tLinData *linData, + tLinIO *linIO, + uint8_t LIN_ISSR_ALL, + osMutexId_t modelTaskAccess, + + ActuatorCmdBus *actuator_Command_Model_trigger_local, + bool *triggerCommand, + + tLoggerInterface *logger) { + + env->linIo = linIO; + env->linData = linData; + env->logger = logger; + env->modelTaskAccess = modelTaskAccess; + env->actuator_Command_Model_trigger_local = actuator_Command_Model_trigger_local; + env->triggerCommand = triggerCommand; + env->LIN_ISSR_ALL = LIN_ISSR_ALL; + env->access = osMutexNew(NULL); + + memcpy(env->SIGN_LOG, "Ln1 ", sizeof("Ln1 ") - 1); + + InitThreadAtrStatic(&env->threadLin.attr, "Ln1", env->threadLin.controlBlock, env->threadLin.stack, + osPriorityNormal); +} + + +static _Noreturn void Lin1_Thread(tLinTaskActuator *env) { + for (;;) { + + if (osMutexAcquire(env->access, 5000) == osOK) { + + + LinActuatorWork(env, env->modelTaskAccess, 1, + &env->actuator_Ch012_Command_Model_local, + env->actuator_Command_Model_trigger_local, + &env->actuator_Ch012_Input_Model_local, + &Actuator_Ch0_Status_Model, env->triggerCommand, "Ln1 "); + + + lin_event_id_t res = Lin_Scheduler(env, 1); + + uint8_t isError = 0; + for (uint8_t i = 0; i < env->LIN_ISSR_ALL; ++i) { + if (env->linStateActuator[i].error_connect == 1) + ++isError; + } + + if (isError == env->LIN_ISSR_ALL) { + env->error_connect = 1; + } else { + env->error_connect = 0; + } + + env->busy = false; + + osMutexRelease(env->access); + } else { + LoggerInfoStatic(LOGGER, "Ln1 ", "Mutex acquisition error") + } + + SystemDelayMs(50); + } +} + +void Lin1_StartThread(tLinTaskActuator *env) { + if (!env->threadLin.id) { + env->threadLin.id = osThreadNew((osThreadFunc_t) (Lin1_Thread), (void *) (env), &env->threadLin.attr); + } +} + +//конец----------------------------------------- LIN 1 ---------------------------------------------------------------- +//конец----------------------------------------- LIN 1 ---------------------------------------------------------------- +//конец----------------------------------------- LIN 1 ---------------------------------------------------------------- +//конец----------------------------------------- LIN 1 ---------------------------------------------------------------- + + + +//начало----------------------------------------- LIN 2 ---------------------------------------------------------------- +//начало----------------------------------------- LIN 2 ---------------------------------------------------------------- +//начало----------------------------------------- LIN 2 ---------------------------------------------------------------- +//начало----------------------------------------- LIN 2 --------------------------------------------------------------- + +void Lin_2_Init(tLinTaskActuator *env, + tLinData *linData, + tLinIO *linIO, + uint8_t LIN_ISSR_ALL, + osMutexId_t modelTaskAccess, + ActuatorCmdBus *actuator_Command_Model_trigger_local, + bool *triggerCommand, + tLoggerInterface *logger) { + + env->linIo = linIO; + env->linData = linData; + env->logger = logger; + + env->modelTaskAccess = modelTaskAccess; + env->actuator_Command_Model_trigger_local = actuator_Command_Model_trigger_local; + env->triggerCommand = triggerCommand; + + + env->LIN_ISSR_ALL = LIN_ISSR_ALL; + env->access = osMutexNew(NULL); + + memcpy(env->SIGN_LOG, "Ln2 ", sizeof("Ln2 ") - 1); + + InitThreadAtrStatic(&env->threadLin.attr, "Ln2", env->threadLin.controlBlock, env->threadLin.stack, + osPriorityNormal); +} + + +static _Noreturn void Lin2_Thread(tLinTaskActuator *env) { + for (;;) { + + if (osMutexAcquire(env->access, 5000) == osOK) { + + LinActuatorWork(env, env->modelTaskAccess, 2, + &env->actuator_Ch012_Command_Model_local, + env->actuator_Command_Model_trigger_local, + &env->actuator_Ch012_Input_Model_local, + &Actuator_Ch1_Status_Model, env->triggerCommand, "Ln2 "); + + lin_event_id_t res = Lin_Scheduler(env, 2); + + uint8_t isError = 0; + for (uint8_t i = 0; i < env->LIN_ISSR_ALL; ++i) { + if (env->linStateActuator[i].error_connect == 1) + ++isError; + } + + if (isError == env->LIN_ISSR_ALL) { + env->error_connect = 1; + } else { + env->error_connect = 0; + } + + env->busy = false; + + osMutexRelease(env->access); + } else { + LoggerInfoStatic(LOGGER, "Ln2 ", "Mutex acquisition error") + } + + SystemDelayMs(50); + } +} + +void Lin2_StartThread(tLinTaskActuator *env) { + if (!env->threadLin.id) { + env->threadLin.id = osThreadNew((osThreadFunc_t) (Lin2_Thread), (void *) (env), &env->threadLin.attr); + } +} + +//конец----------------------------------------- LIN 2 ---------------------------------------------------------------- +//конец----------------------------------------- LIN 2 ---------------------------------------------------------------- +//конец----------------------------------------- LIN 2 ---------------------------------------------------------------- +//конец----------------------------------------- LIN 2 ---------------------------------------------------------------- + + + +//начало----------------------------------------- LIN 3 ---------------------------------------------------------------- +//начало----------------------------------------- LIN 3 ---------------------------------------------------------------- +//начало----------------------------------------- LIN 3 ---------------------------------------------------------------- +//начало----------------------------------------- LIN 3 --------------------------------------------------------------- + +void Lin_3_Init(tLinTaskActuator *env, + tLinData *linData, + tLinIO *linIO, + uint8_t LIN_ISSR_ALL, + osMutexId_t modelTaskAccess, + ActuatorCmdBus *actuator_Command_Model_trigger_local, + bool *triggerCommand, + tLoggerInterface *logger) { + + env->linIo = linIO; + env->linData = linData; + env->logger = logger; + + env->modelTaskAccess = modelTaskAccess; + env->actuator_Command_Model_trigger_local = actuator_Command_Model_trigger_local; + env->triggerCommand = triggerCommand; + + env->LIN_ISSR_ALL = LIN_ISSR_ALL; + env->access = osMutexNew(NULL); + + memcpy(env->SIGN_LOG, "Ln3 ", sizeof("Ln3 ") - 1); + + InitThreadAtrStatic(&env->threadLin.attr, "Ln3", env->threadLin.controlBlock, env->threadLin.stack, + osPriorityNormal); +} + + +static _Noreturn void Lin3_Thread(tLinTaskActuator *env) { + for (;;) { + + if (osMutexAcquire(env->access, 5000) == osOK) { + + LinActuatorWork(env, env->modelTaskAccess, 3, + &env->actuator_Ch012_Command_Model_local, + env->actuator_Command_Model_trigger_local, + &env->actuator_Ch012_Input_Model_local, + &Actuator_Ch2_Status_Model, env->triggerCommand, "Ln3 "); + + lin_event_id_t res = Lin_Scheduler(env, 3); + + uint8_t isError = 0; + for (uint8_t i = 0; i < env->LIN_ISSR_ALL; ++i) { + if (env->linStateActuator[i].error_connect == 1) + ++isError; + } + + if (isError == env->LIN_ISSR_ALL) { + env->error_connect = 1; + } else { + env->error_connect = 0; + } + + env->busy = false; + + osMutexRelease(env->access); + } else { + LoggerInfoStatic(LOGGER, "Ln3 ", "Mutex acquisition error") + } + + SystemDelayMs(50); + } +} + +void Lin3_StartThread(tLinTaskActuator *env) { + if (!env->threadLin.id) { + env->threadLin.id = osThreadNew((osThreadFunc_t) (Lin3_Thread), (void *) (env), &env->threadLin.attr); + } +} + +//конец----------------------------------------- LIN 3 ---------------------------------------------------------------- +//конец----------------------------------------- LIN 3 ---------------------------------------------------------------- +//конец----------------------------------------- LIN 3 ---------------------------------------------------------------- +//конец----------------------------------------- LIN 3 ---------------------------------------------------------------- \ No newline at end of file diff --git a/MODULES/HVAC_M7_LIN_TASKS/LinActuatorTasks.h b/MODULES/HVAC_M7_LIN_TASKS/LinActuatorTasks.h new file mode 100644 index 0000000..5bc5c6b --- /dev/null +++ b/MODULES/HVAC_M7_LIN_TASKS/LinActuatorTasks.h @@ -0,0 +1,521 @@ +// +// Created by cfif on 05.04.2024. +// + +#ifndef HVAC_LIN_TASKS_H +#define HVAC_LIN_TASKS_H + +#include +#include "stdbool.h" +#include "LinIO.h" +#include "HVAC_model_types.h" +#include "LoggerInterface.h" + +#define LOG_LIN_ACTUATOR 0 +#define LOG_LIN1_ACTUATOR 0 +#define LOG_LIN2_ACTUATOR 0 +#define LOG_LIN3_ACTUATOR 0 + +typedef struct __attribute__ ((packed)) { + uint8_t BUS_ADR; + uint16_t INI_CPOS: 15; + uint8_t unused: 1; + uint8_t Not_Used_INI; +} ACT_CFR_INI; + +// Stalldetection is active (LIN_STALL_SET_ON): +// Actuator stops at an Endstop +// Stalldetection is deactivated (LIN_STALL_SET_OFF): +// Actuator stop at an mechanical Endstop and tries to move further till its internal counter has reached FPOS. + +// Функция обнаружения заклинивания активна (LIN_STALL_SET_ON): +// Привод останавливается на концевом выключателе +// Функция обнаружения заклинивания деактивирована (LIN_STALL_SET_OFF): +// Привод останавливается на механическом концевом выключателе и пытается двигаться дальше, пока его внутренний счётчик не достигнет FPOS. + +typedef enum { + LIN_STALL_SET_ON = 1, + LIN_STALL_SET_OFF = 0, +} eStall_SET; + +// LIN_LNOISE_SET_ON: +// Actuator moves with reduced torque and thus with +// LIN_LNOISE_SET_OFF: +// reduced noise level Actuator moves with nominal full step + +// LIN_LNOISE_SET_ON: +// Привод движется с уменьшенным крутящим моментом и, следовательно, с пониженным уровнем шума. +// LIN_LNOISE_SET_OFF: +// Привод движется с номинальным полным шагом. + +typedef enum { + LIN_LNOISE_SET_ON = 1, + LIN_LNOISE_SET_OFF = 0, +} eLnoise_SET; + +// LIN_AUTOS_SET_ON: +// Actuator moves like a brushless DC actuator with maximum speed +// LIN_AUTOS_SET_OFF: +// Actuator moves in Steppmode + +// LIN_AUTOS_SET_ON: +// Актуатор движется как бесщёточный актуатор постоянного тока с максимальной скоростью +// LIN_AUTOS_SET_OFF: +// Актуатор движется в пошаговом режиме + +typedef enum { + LIN_AUTOS_SET_ON = 1, + LIN_AUTOS_SET_OFF = 0, +} eAutos_SET; + +// Definition of the step frequency, that refers to the following speed of the output shaft +// Определение шаговой частоты, которая относится к последующей скорости выходного вала + +typedef enum { + LIN_SPEED_SET_0 = 0, // 0 to 2,25 rpm + LIN_SPEED_SET_1 = 1, // > 2,25 to 3,0 rpm + LIN_SPEED_SET_2 = 2, // > 3,0 to 4,0 rpm + LIN_SPEED_SET_3 = 3 // > 4,0 to x rpm +} eSpeed_SET; + +// 0 +// short time coil supply 100ms (optional) кратковременное питание катушки 100 мс (опционально) +// no permanent coil supply (optional) нет постоянного питания катушки (опционально) + +// 1 +// long time coil supply 100ms (optional) длительное время питания катушки 100 мс (опционально) +// no permanent coil supply (optional) нет постоянного питания катушки (опционально) + +// 2 +// short time coil supply 100ms (optional) кратковременное питание катушки 100 мс (опционально) +// permanent coil supply for holding torque (optional) постоянное питание катушки для удерживающего момента (опционально) + +// 3 +// long time coil supply 100ms (optional) длительное время питания катушки 100 мс (опционально) +// permanent coil supply for holding torque (optional) постоянное питание катушки для удерживающего момента (опционально) + +typedef enum { + LIN_COILS_STOP_SET_0 = 0, // 0 to 2,25 rpm + LIN_COILS_STOP_SET_1 = 1, // > 2,25 to 3,0 rpm + LIN_COILS_STOP_SET_2 = 2, // > 3,0 to 4,0 rpm + LIN_COILS_STOP_SET_3 = 3 // > 4,0 to x rpm +} eCoils_Stop_SET; + +typedef struct __attribute__ ((packed)) { + uint8_t BUS_ADR; + + uint16_t FINAL_POS: 15; + uint8_t unused: 1; + + uint8_t Unused_SET: 1; + eStall_SET Stall_SET: 1; + eLnoise_SET Lnoise_SET: 1; + eAutos_SET Autos_SET: 1; + eSpeed_SET Speed_SET: 2; + eCoils_Stop_SET Coils_Stop_SET: 2; + + +} ACT_CFR_SET; + +// Using this service the master can switch an actuator to a needed functional mode. +// Используя эту услугу, мастер может переключить привод в необходимый режим работы. + +typedef enum { + LIN_MODE_NORMAL = 0, + LIN_MODE_SERVICE = 1, + LIN_MODE_STOP = 2 +} eMode_Mod; + + +typedef struct __attribute__ ((packed)) { + uint8_t BUS_ADR; + eMode_Mod Mode_Slave: 2; + uint8_t Unused: 6; // Установить в 0xFF + uint8_t Data2_Mod; // Установить в 0xFF + uint8_t Data3_Mod; // Установить в 0xFF +} ACT_CFR_MOD; + + +// The ACT_DFR_STA sent by the master selects the actuator which must prepare its status response. This service is a combined one and requires that the +// next command to be send by the master will be the ACT_RFR_STA; Identifier: 0x A3, to poll the slave response. Only the actuator selected by the +// ACT_DFR_STA must answer to the ACT_RFR_STA. + +// Сигнал ACT_DFR_STA, отправленный ведущим устройством, выбирает исполнительный механизм, который должен подготовить свой ответ о состоянии. +// Это комбинированная служба, требующая, чтобы следующей командой, отправленной ведущим устройством, была +// ACT_RFR_STA; Идентификатор: 0xA3, для опроса ответа ведомого устройства. Только исполнительный механизм, выбранный +// ACT_DFR_STA, должен ответить на сигнал ACT_RFR_STA. + +typedef struct __attribute__ ((packed)) { + uint8_t BUS_ADR; + uint8_t Data1_DFR_STA; // Установить в 0xFF +} ACT_DFR_STA; + +// Emergency Run Conditions have been detected and will be indicated with the bit set to 0. No Emergency Run Conditions have been detected and that’s indicated with the bit set to 1. +// The flag will be reset to 1 with the correct sending of this status response to the master. The master can read this information only one time. + +// Обнаружены условия аварийного запуска, что будет отображено битом, установленным в 0. Условия аварийного запуска не обнаружены, что будет отображено битом, установленным в 1. +// Флаг будет сброшен в 1 при корректной отправке этого ответа о состоянии ведущему устройству. Ведущее устройство может прочитать эту информацию только один раз. + +typedef enum { + LIN_EMERGENCY_RUN_YES = 0, + LIN_EMERGENCY_RUN_NO = 1, +} eEmrf_Slave_STA; + + +// The actuator will set this bit, when it has detected an endstop or a block during its movement (Stall). +//The StD flag can only be set if the stall detection is enabled. +//When a stall is detected (StD flag = 1) the FPOS is set to CPOS. Thus the actuator will not move automatically after erase of the StD flag from master. +//The master has to send a _SET command to restart it. +//As long the STALL flag is set all _SET commands are ignored. +//The set flag will be reset with the correct sending of this status response to the master. + +// Привод установит этот бит, когда обнаружит концевой упор или блокировку во время движения (остановку). +// Флаг StD может быть установлен только при включенном обнаружении остановки. +// При обнаружении остановки (флаг StD = 1) FPOS устанавливается в CPOS. Таким образом, привод не будет двигаться автоматически после стирания флага StD ведущим устройством. +// Для перезапуска ведущему устройству необходимо отправить команду _SET. +// Пока установлен флаг STALL, все команды _SET игнорируются. +// Флаг установки будет сброшен при корректной отправке этого ответа о состоянии ведущему устройству. + +typedef enum { + LIN_STALL_STA_ON = 1, + LIN_STALL_STA_OFF = 0, +} eStall_STA; + + +// POR occurred, new initialisation required +// (1) These flags do activate the Error flag in the ISSRx when they are set +// The ResetIntern flag has to be set with each internal power on reset. +// The set flag will be reset with a defined ACT_CFR_INI. With that command the correct position has to be transferred or an initialisation routine has to be started. + +// Произошла ошибка POR, требуется новая инициализация +// (1) Эти флаги активируют флаг ошибки в ISSRx, когда они установлены. +// Флаг ResetIntern должен быть установлен при каждом внутреннем сбросе при включении питания. +// Установленный флаг будет сброшен с помощью заданногоACT_CFR_INI. С помощью этой команды необходимо передать корректное положение или запустить процедуру инициализации. + +typedef enum { + LIN_RESET_STA_ON = 1, + LIN_RESET_STA_OFF = 0, +} eReset_STA; + +typedef struct __attribute__ ((packed)) { + uint8_t BUS_ADR; + uint16_t CPOS_ALL: 15; + eEmrf_Slave_STA Emrf_Slave: 1; + eMode_Mod Mode_Slave: 2; + uint8_t Error1_Supply_Slave: 1; + uint8_t Error2_Communication_Slave: 1; + uint8_t Error3_Temperature_Slave: 1; + uint8_t Error4_Permanent_Electrical_Slave: 1; + eStall_STA Stall_Slave: 1; + eReset_STA Reset_Slave: 1; +} ACT_RFR_STA; + +typedef struct __attribute__ ((packed)) { + uint8_t BUS_ADR; + uint8_t Data1_DFR_IDE; // Установить в 0xFF +} ACT_DFR_IDE; + +typedef struct __attribute__ ((packed)) { + uint8_t BUS_ADR; + uint8_t IDE_ref; + uint8_t IDE_Sup; + uint8_t IDE_Har; +} ACT_RFR_IDE; + +// This service is used to process the auto-addressing of the actuators. The process of current measurement will be done the ECU executes an extended Synch +// Break of more or equal of 18 Tbit, directly with the following command after this ACT_CFR_ADDR. +// A slaves participates in autoaddressing if the following conditions are fulfilled: +// The slave is in Service Mode +// The slave has not yet reseted its internal addressing flag during the current autoaddressing process. That means that the slaves has not yet detected himselve to be +// the last one in the chain and has not yet taken over a final address. +// The master must send the address 20h in data 0 of CFR_ADDR (Group, Item) as common address for both actuator groups during autoaddressing. +// The master has to make sure that the final address (data 1) is within the actuators address range (actuator group 1 and 2). + +// Эта служба используется для обработки автоадресации исполнительных механизмов. Процесс измерения тока будет выполнен, когда ЭБУ выполняет расширенный синхроразрыв +// на 18 Тбит или более, непосредственно со следующей командой после ACT_CFR_ADDR. +// Ведомое устройство участвует в автоадресации, если выполнены следующие условия: +// Ведомое устройство находится в сервисном режиме +// Ведомое устройство еще не сбросило свой внутренний флаг адресации во время текущего процесса автоадресации. Это означает, что ведомое устройство еще не определило себя +// как последнее в цепочке и еще не приняло конечный адрес. +// Ведущее устройство должно отправить адрес 20h в поле данных 0 CFR_ADDR (Группа, Элемент) в качестве общего адреса для +// обеих групп исполнительных механизмов во время автоадресации. +// Ведущее устройство должно убедиться, что конечный адрес (данные 1) находится в диапазоне адресов исполнительных устройств (группы исполнительных устройств 1 и 2). + +typedef struct __attribute__ ((packed)) { + uint8_t BUS_ADR; + uint8_t BUS_NEW_ADR; +} ACT_CFR_ADDR; + +// NOTL_DREH_Master: +// If enabled (see next paragraph), the Emergency Run (after general bus time out) has to be executed in direction to the high low end stop +// If enabled (see next paragraph), the Emergency Run (after general bus time out) has to be executed in direction to the low high end stop +// Thus the direction of turn of the output shaft during an emergency run depends on the ACT_CFR_PRG_Direction. + +// Если включено (см. следующий абзац), аварийный ход (после истечения времени ожидания общей шины) должен быть выполнен в направлении к верхнему нижнему концевому упору. +// Если включено (см. следующий абзац), аварийный ход (после истечения времени ожидания общей шины) должен быть выполнен в направлении к нижнему верхнему концевому упору. +// Таким образом, направление вращения выходного вала во время аварийного хода зависит от ACT_CFR_PRG_Direction. + +// NOTL_ENAB_Master: +// Аварийный запуск не требуется выполнять после истечения времени ожидания общей шины. +// Аварийный запуск должен выполняться после истечения времени ожидания общей шины. +// Во время аварийного запуска необходимо активировать функцию обнаружения опрокидывания, чтобы избежать механических повреждений и шума в концевом останове. + +// DREH_Master: +// Actuator has to move cw with CPos > FPos +// Actuator has to move ccw with CPos < FPos +// Actuator has to move cw with CPos < FPos +// Actuator has to move ccw with CPos > FPos + +// Актуатор должен двигаться по часовой стрелке с CPos > FPos +// Актуатор должен двигаться против часовой стрелки с CPos < FPos +// Актуатор должен двигаться по часовой стрелке с CPos < FPos +// Актуатор должен двигаться против часовой стрелки с CPos > FPos + +// Motor, Baudrate, Free: +// These bits are free for actuator specific use. The definition is included in the Implementation chapter. +// Эти биты доступны для использования с конкретными приводами. Определение приведено в главе «Реализация». + +// Version_CFR: +// ProductNumber +// This Reference of the product, has to be incremented each time major changes have been done on the hardware of the actuator (e.g. PCB, Mechanic, ASIC- HW, a.s.o. +// Этот артикул изделия необходимо увеличивать каждый раз после внесения существенных изменений в аппаратную часть привода (например, печатная плата, механика, ASIC-аппаратура и т.д.). + +typedef struct __attribute__ ((packed)) { + uint8_t BUS_ADR; + uint8_t BUS_NEW_ADR; + uint8_t NOTL_DREH_Master: 1; + uint8_t NOTL_ENAB_Master: 1; + uint8_t DREH_Master: 1; + uint8_t Motor: 3; + uint8_t Baudrate: 1; + uint8_t Free: 1; + uint8_t Version_CFR; +} ACT_CFR_PRG; + + +typedef struct __attribute__ ((packed)) { + uint8_t BUS_ADR; + uint8_t Data1_DFR_PRG; // Установить в 0xFF +} ACT_DFR_PRG; + +typedef struct __attribute__ ((packed)) { + uint8_t BUS_ADR; + uint8_t BUS_NEW_ADR; + uint8_t NOTL_DREH_Master: 1; + uint8_t NOTL_ENAB_Master: 1; + uint8_t DREH_Slave: 1; + uint8_t ParitySlave: 1; + uint8_t Free: 4; + uint8_t Version_CFR; +} ACT_RFR_PRG; + + +// With this service the master can request a demanded actuator for the actual current position of it. +// The master sends an header which contains the address of the demanded actuator in the identifier. +// The information on the CPos in the response will be coded into 14 bits located in Data 0 and Data 1, with a resolution of 2 steps per LSB. +// In the reponse frame an additional information is included, if stall detection StD has occurred and / or if errors in the actuator have occurred. + +// С помощью этой службы ведущее устройство может запросить требуемый исполнительный механизм для получения информации о его фактическом текущем положении. +// Ведущее устройство отправляет заголовок, содержащий адрес требуемого исполнительного механизма в идентификаторе. +// Информация о CPos в ответе будет закодирована в 14 бит, расположенных в Data 0 и Data 1, с разрешением 2 шага на младший значащий бит. +// В кадр ответа включается дополнительная информация, если произошло обнаружение срыва (StD) и/или произошли ошибки в исполнительном механизме. + +// Actuators address without group definition, located in bit[0:4] of the identifier in the header. Reserved addresses are ISSR1 to ISSR22 and ISSR31 (default address of actuators). +// Remark: Addresses 23 to 30 are accessible by the +// Status Service _STA only. + +// Адрес исполнительных устройств без определения группы, указанный в бите [0:4] идентификатора в заголовке. Зарезервированные адреса: ISSR1–ISSR22 и ISSR31 (адрес исполнительных устройств по умолчанию). +// Примечание: Адреса с 23 по 30 доступны только +// службе состояния _STA. + +// BLOCK_MT: +// The actuator will set this bit, when it has detected an endstop or a block during its movement. +// The STALL flag can only be set if the stall detection is enabled. +// When a stall is detected (STALL flag = 1) the FPOS is set to CPOS. Thus the actuator will not move automatically after erase of the STALL flag from master. The master has to send a _SET command to restart it. +// As long the STALL flag is set all _SET commands are ignored. + +// Привод установит этот бит, если обнаружит концевой упор или блокировку во время движения. +// Флаг STALL может быть установлен только при включенном обнаружении остановки. +// При обнаружении остановки (флаг STALL = 1) FPOS устанавливается в CPOS. Таким образом, привод не будет двигаться автоматически после стирания флага STALL ведущим устройством. Ведущее устройство должно отправить команду _SET для его перезапуска. +// Пока флаг STALL установлен, все команды _SET игнорируются. + +// CPOS_1_LSB_MT, CPOS_1_MSB_MT: +// For CPos, give the relation with accuracy: if the real position is even, CPos = real position / 2; if the real position is odd, CPos = (real position - 1) / 2. +// The default value for CPos after a POR is the middle position of the possible range: CPOS = 0x1FFF (0x3FFF/2). + +// Для CPos укажите отношение с точностью: если вещественная позиция чётная, CPos = вещественная позиция / 2; если вещественная позиция нечётная, CPos = (вещественная позиция - 1) / 2. +// Значение по умолчанию для CPos после POR — это средняя позиция возможного диапазона: CPOS = 0x1FFF (0x3FFF/2). + +// DIAGNOSE_MT: +// The actuator will set this bit, when it has detected any error inside. +// The actuator has to set the _Error with each of the following bits and when they occur in each possible combination: +// •Power On Reset +// •Supply Error (over- / undervoltage) +// •Over Temperature +// •Permanent Electrical Defect +// •Emergency Run occurred (general bus time out) + +// Привод установит этот бит при обнаружении любой внутренней ошибки. +// Привод должен установить _Error для каждого из следующих битов и при их возникновении в каждой возможной комбинации: +// •Сброс при включении питания +// •Ошибка питания (повышение/понижение напряжения) +// •Перегрев +// •Постоянная неисправность электрооборудования +// •Произошёл аварийный запуск (превышение времени ожидания на общей шине) + +typedef struct __attribute__ ((packed)) { + uint8_t BLOCK_MT: 1; + uint8_t CPOS_1_LSB_MT: 7; + uint8_t CPOS_1_MSB_MT: 7; + uint8_t DIAGNOSE_MT: 1; +} ACT_RFR_ISSR; + +typedef struct { + + uint8_t BLOCK_MT; + uint8_t DIAGNOSE_MT; + uint16_t CPOS_2_ALL; + + uint16_t CPOS_ALL; + eEmrf_Slave_STA Emrf_Slave; + eMode_Mod Mode_Slave; + uint8_t Error1_Supply_Slave; + uint8_t Error2_Communication_Slave; + uint8_t Error3_Temperature_Slave; + uint8_t Error4_Permanent_Electrical_Slave; + eStall_STA Stall_Slave; + eReset_STA Reset_Slave; + + uint8_t IDE_ref; + uint8_t IDE_Sup; + uint8_t IDE_Har; + + uint8_t BUS_NEW_ADR; + uint8_t NOTL_DREH_Master; + uint8_t NOTL_ENAB_Master; + uint8_t DREH_Slave; + uint8_t ParitySlave; + uint8_t Version_CFR; + + uint8_t error_connect; + +} tLinStateFullActuator; + +// POS - Позиция + +// BUS_ADR - (3 бита [7..5] - Группа; 5 бит [4..0] - Адрес) +// Пример Широковещательный адрес группа 1: 0x20, 0x20, 0x20 .. 0x20 +// Пример Обычный адрес: 0x01, 0x02, 0x03 .. 0x09 +// Смешанный тип адреса не допустим + +// COM - Команда + +typedef enum { + LIN_ACT_CFR_NONE = 0, + LIN_ACT_CFR_MOD = 1, + LIN_ACT_CFR_INI = 2, + LIN_ACT_CFR_SET = 3, + LIN_ACT_CFR_SUCCESSFUL = 0xFF +} eLinCOM; + +typedef struct { + uint16_t POS; + uint8_t BUS_ADR; + eMode_Mod MODE; + eLinCOM COM; // Является защелкой (триггером), которую контроллер сбросит, когда заберет данные + eStall_SET Stall_SET; + eLnoise_SET Lnoise_SET; + eAutos_SET Autos_SET; + eSpeed_SET Speed_SET; + eCoils_Stop_SET Coils_Stop_SET; + + uint16_t BUS_NEW_ADR; + uint8_t NOTL_DREH_Master; + uint8_t NOTL_ENAB_Master; + uint8_t DREH_Master; + uint8_t Motor; + uint8_t Baudrate; + uint8_t Version_CFR; + + uint8_t isRFR_STA; + +} tLinCommandActuator; + +typedef struct { + + tLinIO *linIo; + osMutexId_t access; + + bool busy; // Устройство занято + uint8_t error_connect; // Ошибка соединения (устройство не отвечает) + + char SIGN_LOG[5]; + + tLinStateFullActuator linStateActuator[9]; + tLinCommandActuator linCommandActuator[9]; + + tLinData *linData; + + uint8_t LIN_ISSR_ALL; + + tLoggerInterface *logger; + + + ActuatorCmdBus *actuator_Command_Model_trigger_local; + bool *triggerCommand; + osMutexId_t modelTaskAccess; + + // Входные данные (локальные) для модели + ActuatorCmdBus actuator_Ch012_Command_Model_local; + + // Выходные данные (локальные) для модели + ActuatorCmdBusInput actuator_Ch012_Input_Model_local; + + + struct { + osThreadId_t id; + uint32_t stack[384]; + StaticTask_t controlBlock; + osThreadAttr_t attr; + } threadLin; + +} tLinTaskActuator; + +void Lin_1_Init(tLinTaskActuator *env, + tLinData *linData, + tLinIO *linIO, + uint8_t LIN_ISSR_ALL, + osMutexId_t modelTaskAccess, + ActuatorCmdBus *actuator_Command_Model_trigger_local, + bool *triggerCommand, + tLoggerInterface *logger); + +void Lin1_StartThread(tLinTaskActuator *env); + +void Lin_2_Init(tLinTaskActuator *env, + tLinData *linData, + tLinIO *linIO, + uint8_t LIN_ISSR_ALL, + osMutexId_t modelTaskAccess, + ActuatorCmdBus *actuator_Command_Model_trigger_local, + bool *triggerCommand, + tLoggerInterface *logger); + +void Lin2_StartThread(tLinTaskActuator *env); + +void Lin_3_Init(tLinTaskActuator *env, + tLinData *linData, + tLinIO *linIO, + uint8_t LIN_ISSR_ALL, + osMutexId_t modelTaskAccess, + ActuatorCmdBus *actuator_Command_Model_trigger_local, + bool *triggerCommand, + tLoggerInterface *logger); + +void Lin3_StartThread(tLinTaskActuator *env); + + +void GetLin123CallbackHandler(tLinData *env, uint8_t u8LinIndex, void *state); + + +#endif //HVAC_LIN_TASKS_H diff --git a/MODULES/HVAC_M7_LIN_TASKS/LinActuatorWork.c b/MODULES/HVAC_M7_LIN_TASKS/LinActuatorWork.c new file mode 100644 index 0000000..a54a5f3 --- /dev/null +++ b/MODULES/HVAC_M7_LIN_TASKS/LinActuatorWork.c @@ -0,0 +1,181 @@ +// +// Created by cfif on 20.01.2026. +// +#include "LinActuatorWork.h" +#include "string.h" + + +//#define LOG_SIGN "Lin" +#define LOGGER linTaskActuator->logger + +static bool isBroadCastTriggered(tLinTaskActuator *env, ActuatorCmdBus *actuator_Command_Model_trigger_local) { + + for (uint8_t j = 0; j < env->LIN_ISSR_ALL; ++j) { + if (actuator_Command_Model_trigger_local->BUS_ADR[j] != 0) { + return false; + } + } + + return true; +} + +static void showLogCommand(tLinTaskActuator *linTaskActuator, char *LOG_SIGN, uint8_t BUS_ADR, uint8_t COM) { + switch (COM) { + case LIN_ACT_CFR_NONE: { + LoggerFormatTrace(LOGGER, LOG_SIGN, "BUS_ADR: %d - NO COMMAND", BUS_ADR) + break; + } + + case LIN_ACT_CFR_MOD: { + LoggerFormatTrace(LOGGER, LOG_SIGN, "BUS_ADR: %d - LIN_ACT_CFR_MOD", BUS_ADR) + break; + } + + case LIN_ACT_CFR_INI: { + LoggerFormatTrace(LOGGER, LOG_SIGN, "BUS_ADR: %d - LIN_ACT_CFR_INI", BUS_ADR) + break; + } + + case LIN_ACT_CFR_SET: { + LoggerFormatTrace(LOGGER, LOG_SIGN, "BUS_ADR: %d - LIN_ACT_CFR_SET", BUS_ADR) + break; + } + + default: { + LoggerFormatError(LOGGER, LOG_SIGN, "BUS_ADR: %d - UNKNOWN COMMAND", BUS_ADR) + break; + } + + } +} + +#if (LOG_LIN_ACTUATOR == 1) +#define IS_LOGGING_ENABLED(numAct) \ + ( (numAct == 1 && LOG_LIN1_ACTUATOR == 1) || \ + (numAct == 2 && LOG_LIN2_ACTUATOR == 1) || \ + (numAct == 3 && LOG_LIN3_ACTUATOR == 1) ) +#endif + +// actuator_Command_Model_local - Выход модели (команды для актуаторов) ЛОКАЛЬНО +// actuator_Command_Model_trigger_local - Выход модели (команды для актуаторов) ЗАХВАТ +// actuator_Output_Model_local - Вход модели (состояния актуаторов) ЛОКАЛЬНЫЙ +// actuator_Output_Model_model - Вход модели (состояния актуаторов) МОДЕЛИ + +void LinActuatorWork(tLinTaskActuator *linTaskActuator, osMutexId_t modelTaskAccess, uint8_t numAct, + ActuatorCmdBus *actuator_Command_Model_local, + ActuatorCmdBus *actuator_Command_Model_trigger_local, + ActuatorCmdBusInput *actuator_Output_Model_local, + ActuatorCmdBusInput *actuator_Output_Model_model, + bool *triggerCommand, + char *LOG_SIGN) { + + + for (uint8_t i = 0; i < linTaskActuator->LIN_ISSR_ALL; ++i) { + + linTaskActuator->linCommandActuator[i].POS = actuator_Command_Model_local->POS[i]; + linTaskActuator->linCommandActuator[i].BUS_ADR = actuator_Command_Model_local->BUS_ADR[i]; + linTaskActuator->linCommandActuator[i].MODE = actuator_Command_Model_local->MODE[i]; + + // Если команда выполнена + if (linTaskActuator->linCommandActuator[i].COM == LIN_ACT_CFR_SUCCESSFUL) { +#if (LOG_LIN_ACTUATOR == 1) + if (IS_LOGGING_ENABLED(numAct)) { + LoggerFormatTrace(LOGGER, LOG_SIGN, "BUS_ADR: %d - SUCCESSFUL COMMAND (UNSET BUSY)", i + 1) + } +#endif + // LoggerFormatTrace(LOGGER, LOG_SIGN, "ACTUATOR %d - SUCCESSFUL COMMAND (UNSET BUSY)", numAct) + + actuator_Output_Model_local->Busy = 0; + // Разрешение обработки новой команды + //env->isActuatorNoGetNextCommand[numAct - 1] = false; + + // Обнуляем команду в локальном буфере + actuator_Command_Model_local->COM[i] = LIN_ACT_CFR_NONE; + } + + // ТОЛЬКО если команда не SUCCESSFUL, копируем новые данные + linTaskActuator->linCommandActuator[i].COM = actuator_Command_Model_local->COM[i]; + linTaskActuator->linCommandActuator[i].Stall_SET = actuator_Command_Model_local->Stall_SET[i]; + linTaskActuator->linCommandActuator[i].Lnoise_SET = actuator_Command_Model_local->Lnoise_SET[i]; + linTaskActuator->linCommandActuator[i].Autos_SET = actuator_Command_Model_local->Autos_SET[i]; + linTaskActuator->linCommandActuator[i].Speed_SET = actuator_Command_Model_local->Speed_SET[i]; + linTaskActuator->linCommandActuator[i].Coils_Stop_SET = actuator_Command_Model_local->Coils_Stop_SET[i]; + + // Заполнение данных ВХОДЫ МОДЕЛИ + actuator_Output_Model_local->in_CPOS_ALL[i] = (int16_t) linTaskActuator->linStateActuator[i].CPOS_ALL; + actuator_Output_Model_local->in_Act_Emrf_Slave[i] = (int8_t) linTaskActuator->linStateActuator[i].Emrf_Slave; + actuator_Output_Model_local->in_Mode_Slave[i] = (int8_t) linTaskActuator->linStateActuator[i].Mode_Slave; + actuator_Output_Model_local->in_Act_Err1_Supply[i] = (int8_t) linTaskActuator->linStateActuator[i].Error1_Supply_Slave; + actuator_Output_Model_local->in_Act_Err2_Communication[i] = (int8_t) linTaskActuator->linStateActuator[i].Error2_Communication_Slave; + actuator_Output_Model_local->in_Act_Err3_Temperature[i] = (int8_t) linTaskActuator->linStateActuator[i].Error3_Temperature_Slave; + actuator_Output_Model_local->in_Act_Err4_Permanent_Electrical[i] = (int8_t) linTaskActuator->linStateActuator[i].Error4_Permanent_Electrical_Slave; + actuator_Output_Model_local->in_Act_Stall_Slave[i] = linTaskActuator->linStateActuator[i].Stall_Slave; + actuator_Output_Model_local->in_Act_Reset[i] = linTaskActuator->linStateActuator[i].Reset_Slave; + } + + // Заполнение данных ВХОДЫ МОДЕЛИ + actuator_Output_Model_local->Error_Connect = linTaskActuator->error_connect; + +// LoggerFormatTrace(LOGGER, LOG_SIGN, "Busy = %d Error_Connect = %d", actuator_Output_Model_local->Busy, actuator_Output_Model_local->Error_Connect) + + + + + + if (osMutexAcquire(modelTaskAccess, 5000) == osOK) { + + // Если прията команда и актуатор не занят (может принимать команды) +// if ((*triggerCommand == true) && (env->isActuatorNoGetNextCommand[numAct - 1] == false)) { + if (*triggerCommand == true) { + + *triggerCommand = false; + +#if (LOG_LIN_ACTUATOR == 1) + if (IS_LOGGING_ENABLED(numAct)) { + if (isBroadCastTriggered(linTaskActuator, actuator_Command_Model_trigger_local)) { + LoggerTraceStatic(LOGGER, LOG_SIGN, "DETECT COMMAND (BROADCAST):") + showLogCommand(linTaskActuator, LOG_SIGN, actuator_Command_Model_trigger_local->BUS_ADR[0], + actuator_Command_Model_trigger_local->COM[0]); + } else { + LoggerTraceStatic(LOGGER, LOG_SIGN, "DETECT COMMAND (NO BROADCAST):") + for (uint8_t i = 0; i < linTaskActuator->LIN_ISSR_ALL; ++i) { + showLogCommand(linTaskActuator, LOG_SIGN, actuator_Command_Model_trigger_local->BUS_ADR[i], + actuator_Command_Model_trigger_local->COM[i]); + } + } + } +#endif + // + actuator_Output_Model_local->Busy = 1; + + // Запрещение обработки новой команды + //env->isActuatorNoGetNextCommand[numAct - 1] = true; + + // начало --- ВЫХОД МОДЕЛИ ---------- + + // ВЫХОД МОДЕЛИ + memcpy(actuator_Command_Model_local, actuator_Command_Model_trigger_local, sizeof(ActuatorCmdBus)); + + // Сброс STALL в состоянии актуатор (локальном состоянии) + +#if (LOG_LIN_ACTUATOR == 1) + if (IS_LOGGING_ENABLED(numAct)) { + LoggerTraceStatic(LOGGER, linTaskActuator->SIGN_LOG, "Reset LOCAL STALL (DETECT STALL RESET)") + } +#endif + for (uint8_t i = 0; i < linTaskActuator->LIN_ISSR_ALL; ++i) { + actuator_Output_Model_local->in_Act_Stall_Slave[i] = LIN_STALL_STA_OFF; + } + + // конец --- ВЫХОД МОДЕЛИ ---------- + + } + + // ВХОДЫ МОДЕЛИ + memcpy(actuator_Output_Model_model, actuator_Output_Model_local, sizeof(ActuatorCmdBusInput)); + + osMutexRelease(modelTaskAccess); + } + + +} diff --git a/MODULES/HVAC_M7_LIN_TASKS/LinActuatorWork.h b/MODULES/HVAC_M7_LIN_TASKS/LinActuatorWork.h new file mode 100644 index 0000000..db77741 --- /dev/null +++ b/MODULES/HVAC_M7_LIN_TASKS/LinActuatorWork.h @@ -0,0 +1,18 @@ +// +// Created by cfif on 20.01.2026. +// + +#ifndef HVAC_M7_LINACTUATORWORK_H +#define HVAC_M7_LINACTUATORWORK_H + +#include "LinActuatorTasks.h" + +void LinActuatorWork(tLinTaskActuator *linTaskActuator, osMutexId_t modelTaskAccess, uint8_t numAct, + ActuatorCmdBus *actuator_Command_Model_local, + ActuatorCmdBus *actuator_Command_Model_trigger_local, + ActuatorCmdBusInput *actuator_Output_Model_local, + ActuatorCmdBusInput *actuator_Output_Model_model, + bool *triggerCommand, + char *LOG_SIGN); + +#endif //HVAC_M7_LINACTUATORWORK_H diff --git a/MODULES/HVAC_M7_LIN_TASKS/LinSensorTasks.c b/MODULES/HVAC_M7_LIN_TASKS/LinSensorTasks.c new file mode 100644 index 0000000..17b082d --- /dev/null +++ b/MODULES/HVAC_M7_LIN_TASKS/LinSensorTasks.c @@ -0,0 +1,914 @@ +// +// Created by cfif on 12.02.2026. +// +#include +#include "LinSensorTasks.h" +#include "CmsisRtosThreadUtils.h" +#include "CanPorts.h" +#include "fc7xxx_driver_lin.h" +#include "Lins.h" +#include "LoggerInterface.h" +#include "memory.h" + + +#define LOG_SIGN4 "Ln4" +#define LOG_SIGN5 "Ln5" +#define LOGGER env->logger + +const uint8_t LIN5_SENSON_ADR_Stat[LIN5_SENSOR_COUNT] = {DRS_DL_Stat, + DRS_DR_Stat, + DRS_FPL_Stat, + DRS_FPR_Stat, + DRS_RLB_Stat, + DRS_RRB_Stat, + DRS_FCL_Stat, + DRS_FCR_Stat}; + +const uint8_t LIN4_SENSON_ADR_Stat[LIN4_SENSOR_COUNT] = {AirQS_Stat, + Aroma_Stat, + Ionizer_Stat, + eTXV_fHVAC_Stat, + eTXV_rHVAC_Stat, + eTXV_batChiller_Stat, + eTXV_eeChiller_Stat}; + +const uint8_t LIN4_SENSON_LEN_Stat[LIN4_SENSOR_COUNT] = {sizeof(tAirQS_Stat), + sizeof(tAroma_Stat), + sizeof(tIonizer_Stat), + sizeof(teTXV_fHVAC_Stat), + sizeof(teTXV_rHVAC_Stat), + sizeof(teTXV_batChiller_Stat), + sizeof(teTXV_eeChiller_Stat)}; + +static lin_event_id_t SEND_SENSOR_COM_x(tLinIO *linIo, uint8_t COM_ADR) { + lin_event_id_t res = linIo->runCommand(linIo->env, COM_ADR, 30); +// SystemDelayMs(40); + return res; +} + +static lin_event_id_t Set_CCU_Req(tLinIO *linIo, tLinData *linData, tCCU_Req *p_CCU_Req) { + lin_event_id_t res; + + linData->direction = LIN_DIRECTION_SET; + + linData->g_aTxBufferLen = sizeof(tCCU_Req); + linData->g_aRxBufferLen = 0; + + memcpy(linData->g_aTxBuffer, p_CCU_Req, sizeof(tCCU_Req)); + + uint8_t retry = 1; + + while (retry) { + + res = SEND_SENSOR_COM_x(linIo, CCU_Req); + + if (res == LIN_TX_COMPLETED) { + break; + } + + --retry; + } + + return res; +} + + +static lin_event_id_t +Get_Sensor4_Stat(tLinIO *linIo, tLinData *linData, void *p_Stat, uint8_t p_Stat_Len, uint8_t ADR_stat) { + lin_event_id_t res; + + void *pStat_ = (void *) linData->g_aRxBuffer; + + uint8_t retry = 1; + + while (retry) { + + linData->direction = LIN_DIRECTION_GET; + + linData->g_aTxBufferLen = 0; + linData->g_aRxBufferLen = p_Stat_Len; + + res = SEND_SENSOR_COM_x(linIo, ADR_stat); + + if (res == LIN_RX_COMPLETED) { + memcpy(p_Stat, pStat_, p_Stat_Len); + break; + } + + --retry; + } + + return res; +} + + +//начало----------------------------------------- LIN 4 ---------------------------------------------------------------- +//начало----------------------------------------- LIN 4 ---------------------------------------------------------------- +//начало----------------------------------------- LIN 4 ---------------------------------------------------------------- +//начало----------------------------------------- LIN 4 --------------------------------------------------------------- + +// Это с выхода Lin4 +void Lin4_Output_Set_Model(tLin4TaskSensor *env) { + + tAirQS_Stat *pAirQS_Stat = (tAirQS_Stat *) &env->Stat[0]; + env->AirQS_Stat_For_Model.AirQS_LinRespErr_Stat = pAirQS_Stat->AirQS_LinRespErr_Stat; + env->AirQS_Stat_For_Model.AirQS_Sens_Stat = pAirQS_Stat->AirQS_Sens_Stat; + env->AirQS_Stat_For_Model.AirQS_Combined_Stat = pAirQS_Stat->AirQS_Combined_Stat; + env->AirQS_Stat_For_Model.AirQS_Err_Stat = pAirQS_Stat->AirQS_Err_Stat; + env->AirQS_Stat_For_Model.AirQS_COLvl_Stat = pAirQS_Stat->AirQS_COLvl_Stat; + env->AirQS_Stat_For_Model.AirQS_NOxLvl_Stat = pAirQS_Stat->AirQS_NOxLvl_Stat; + env->AirQS_Stat_For_Model.AirQS_NH3Lvl_Stat = pAirQS_Stat->AirQS_NH3Lvl_Stat; + + tAroma_Stat *pAroma_Stat = (tAroma_Stat *) &env->Stat[1]; + env->Aroma_Stat_For_Model.Aroma_LinRespErr_Stat = pAroma_Stat->Aroma_LinRespErr_Stat; + env->Aroma_Stat_For_Model.Aroma_CartridgeSw_Stat = pAroma_Stat->Aroma_CartridgeSw_Stat; + env->Aroma_Stat_For_Model.Aroma_Err_Stat = pAroma_Stat->Aroma_Err_Stat; + env->Aroma_Stat_For_Model.Aroma_Intens_Stat = pAroma_Stat->Aroma_Intens_Stat; + env->Aroma_Stat_For_Model.Aroma_CartridgeFlavor_Stat = pAroma_Stat->Aroma_CartridgeFlavor_Stat; + env->Aroma_Stat_For_Model.Aroma_CartridgeCapacity_Stat = pAroma_Stat->Aroma_CartridgeCapacity_Stat; + + + tIonizer_Stat *pIonizer_Stat = (tIonizer_Stat *) &env->Stat[2]; + env->Ionizer_Stat_For_Model.Ionizer_LinRespErr_Stat = pIonizer_Stat->Ionizer_LinRespErr_Stat; + env->Ionizer_Stat_For_Model.Ionizer_Err_Stat = pIonizer_Stat->Ionizer_Err_Stat; + env->Ionizer_Stat_For_Model.Ionizer_Ionization_Stat = pIonizer_Stat->Ionizer_Ionization_Stat; + + teTXV_fHVAC_Stat *p_teTXV_fHVAC_Stat = (teTXV_fHVAC_Stat *) &env->Stat[3]; + env->eTXV_fHVAC_Stat_For_Model.eTXV_fHVAC_Pos_Stat = p_teTXV_fHVAC_Stat->eTXV_fHVAC_Pos_Stat; + env->eTXV_fHVAC_Stat_For_Model.eTXV_fHVAC_LinRespErr_Stat = p_teTXV_fHVAC_Stat->eTXV_fHVAC_LinRespErr_Stat; + env->eTXV_fHVAC_Stat_For_Model.eTXV_fHVAC_Err_Stat = p_teTXV_fHVAC_Stat->eTXV_fHVAC_Err_Stat; + env->eTXV_fHVAC_Stat_For_Model.eTXV_fHVAC_Pressure_Val = p_teTXV_fHVAC_Stat->eTXV_fHVAC_Pressure_Val; + env->eTXV_fHVAC_Stat_For_Model.eTXV_fHVAC_Temp_Val = p_teTXV_fHVAC_Stat->eTXV_fHVAC_Temp_Val; + + + teTXV_rHVAC_Stat *p_teTXV_rHVAC_Stat = (teTXV_rHVAC_Stat *) &env->Stat[4]; + env->eTXV_rHVAC_Stat_For_Model.eTXV_rHVAC_Pos_Stat = p_teTXV_rHVAC_Stat->eTXV_rHVAC_Pos_Stat; + env->eTXV_rHVAC_Stat_For_Model.eTXV_rHVAC_LinRespErr_Stat = p_teTXV_rHVAC_Stat->eTXV_rHVAC_LinRespErr_Stat; + env->eTXV_rHVAC_Stat_For_Model.eTXV_rHVAC_Err_Stat = p_teTXV_rHVAC_Stat->eTXV_rHVAC_Err_Stat; + env->eTXV_rHVAC_Stat_For_Model.eTXV_rHVAC_Pressure_Val = p_teTXV_rHVAC_Stat->eTXV_rHVAC_Pressure_Val; + env->eTXV_rHVAC_Stat_For_Model.eTXV_rHVAC_Temp_Val = p_teTXV_rHVAC_Stat->eTXV_rHVAC_Temp_Val; + + teTXV_batChiller_Stat *p_teTXV_batChiller_Stat = (teTXV_batChiller_Stat *) &env->Stat[5]; + env->eTXV_batChiller_Stat_For_Model.eTXV_batChiller_Pos_Stat = p_teTXV_batChiller_Stat->eTXV_batChiller_Pos_Stat; + env->eTXV_batChiller_Stat_For_Model.eTXV_batChiller_LinRespErr_Stat = p_teTXV_batChiller_Stat->eTXV_batChiller_LinRespErr_Stat; + env->eTXV_batChiller_Stat_For_Model.eTXV_batChiller_Err_Stat = p_teTXV_batChiller_Stat->eTXV_batChiller_Err_Stat; + env->eTXV_batChiller_Stat_For_Model.eTXV_batChiller_Pressure_Val = p_teTXV_batChiller_Stat->eTXV_batChiller_Pressure_Val; + env->eTXV_batChiller_Stat_For_Model.eTXV_batChiller_Temp_Val = p_teTXV_batChiller_Stat->eTXV_batChiller_Temp_Val; + + teTXV_eeChiller_Stat *p_teTXV_eeChiller_Stat = (teTXV_eeChiller_Stat *) &env->Stat[6]; + env->eTXV_eeChiller_Stat_For_Model.eTXV_eeChiller_Pos_Stat = p_teTXV_eeChiller_Stat->eTXV_eeChiller_Pos_Stat; + env->eTXV_eeChiller_Stat_For_Model.eTXV_eeChiller_LinRespErr_Stat = p_teTXV_eeChiller_Stat->eTXV_eeChiller_LinRespErr_Stat; + env->eTXV_eeChiller_Stat_For_Model.eTXV_eeChiller_Err_Stat = p_teTXV_eeChiller_Stat->eTXV_eeChiller_Err_Stat; + env->eTXV_eeChiller_Stat_For_Model.eTXV_eeChiller_Pressure_Val = p_teTXV_eeChiller_Stat->eTXV_eeChiller_Pressure_Val; + env->eTXV_eeChiller_Stat_For_Model.eTXV_eeChiller_Temp_Val = p_teTXV_eeChiller_Stat->eTXV_eeChiller_Temp_Val; + + memcpy(env->sensorLin4CmdBusInput.in_error_connect, env->error_connect, LIN4_SENSOR_COUNT); + env->sensorLin4CmdBusInput.Error_Connect = env->error_all_connect; + + osStatus_t status = osOK; + + uint32_t countQueue_space = osMessageQueueGetSpace(env->queue_input_tAirQS); + if (countQueue_space) { + status = osMessageQueuePut(env->queue_input_tAirQS, &env->AirQS_Stat_For_Model, 0, 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_input_tAroma); + if (countQueue_space) { + status = osMessageQueuePut(env->queue_input_tAroma, &env->Aroma_Stat_For_Model, 0, 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_input_tIonizer); + if (countQueue_space) { + status = osMessageQueuePut(env->queue_input_tIonizer, &env->Ionizer_Stat_For_Model, 0, 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_input_teTXV_fHVAC); + if (countQueue_space) { + status = osMessageQueuePut(env->queue_input_teTXV_fHVAC, &env->eTXV_fHVAC_Stat_For_Model, 0, 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_input_teTXV_rHVAC); + if (countQueue_space) { + status = osMessageQueuePut(env->queue_input_teTXV_rHVAC, &env->eTXV_rHVAC_Stat_For_Model, 0, 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_input_teTXV_batChiller); + if (countQueue_space) { + status = osMessageQueuePut(env->queue_input_teTXV_batChiller, &env->eTXV_batChiller_Stat_For_Model, 0, 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_input_teTXV_eeChiller); + if (countQueue_space) { + status = osMessageQueuePut(env->queue_input_teTXV_eeChiller, &env->eTXV_eeChiller_Stat_For_Model, 0, 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_input_Lin4_Stat); + if (countQueue_space) { + status = osMessageQueuePut(env->queue_input_Lin4_Stat, &env->sensorLin4CmdBusInput, 0, 0); + } + +} + +// Это формирование выхода с модели с задачи Lin4 +void Lin4_Output_Get_From_Model(tLin4TaskSensor *env) { + osStatus_t status = osOK; + + uint32_t countQueue_space = osMessageQueueGetSpace(env->queue_input_tAirQS); + if (countQueue_space == 0) { + status = osMessageQueueGet(env->queue_input_tAirQS, &rtDW.LIN4_AirQS_Stat_Model, 0, 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_input_Lin4_Stat); + if (countQueue_space == 0) { + status = osMessageQueueGet(env->queue_input_Lin4_Stat, &env->sensorLin4CmdBusInput, 0, 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_input_tAroma); + if (countQueue_space == 0) { + status = osMessageQueueGet(env->queue_input_tAroma, &rtDW.LIN4_Aroma_Stat_Model, 0, 0); + } + + countQueue_space = osMessageQueueGetSpace(env->queue_input_tIonizer); + if (countQueue_space == 0) { + status = osMessageQueueGet(env->queue_input_tIonizer, &rtDW.LIN4_Ionizer_Stat_Model, 0, 0); + } + +} + +// Это формирование входа с модели на задачу Lin4 +void Lin4_Input_Set_From_Model(tLin4TaskSensor *env) { + uint32_t countQueue_space = osMessageQueueGetSpace(env->queue_input_tCCU); + + osStatus_t status = osOK; + + if (countQueue_space) { + status = osMessageQueuePut(env->queue_input_tCCU, &rtY.LIN4_CCU_Req_Model, 0, 0); + } +} + +// Это с входа Lin4 +void Lin4_Input_Set_Model(tLin4TaskSensor *env) { + + uint32_t countQueue_space = osMessageQueueGetSpace(env->queue_input_tCCU); + + if (countQueue_space == 0) { + + osStatus_t status = osMessageQueueGet(env->queue_input_tCCU, &env->CCU_Req_For_Model_For_Model, 0, 0); + + if (status == osOK) { + env->d_CCU_Req.CCU_Ionization_Req = env->CCU_Req_For_Model_For_Model.CCU_Ionization_Req; + env->d_CCU_Req.CCU_AromaIntens_Req = env->CCU_Req_For_Model_For_Model.CCU_AromaIntens_Req; + env->d_CCU_Req.CCU_AirQS_Req = env->CCU_Req_For_Model_For_Model.CCU_AirQS_Req; + env->d_CCU_Req.CCU_fHVAC_Pos_Val = env->CCU_Req_For_Model_For_Model.CCU_fHVAC_Pos_Val; + env->d_CCU_Req.CCU_rHVAC_Pos_Val = env->CCU_Req_For_Model_For_Model.CCU_rHVAC_Pos_Val; + env->d_CCU_Req.CCU_batChiller_Pos_Val = env->CCU_Req_For_Model_For_Model.CCU_batChiller_Pos_Val; + env->d_CCU_Req.CCU_eeChiller_Pos_Val = env->CCU_Req_For_Model_For_Model.CCU_eeChiller_Pos_Val; + } + } +} + +static lin_event_id_t Lin4_Scheduler(tLin4TaskSensor *env) { + lin_event_id_t ret = LIN_NO_EVENT; + + SystemDelayMs(40); + + ret = Set_CCU_Req(env->linIo, env->linData, &env->d_CCU_Req); + +#if (LOG_LIN4_SENSOR == 1) + if (ret == LIN_TX_COMPLETED) { + LoggerFormatInfo(LOGGER, LOG_SIGN4, "OK Set_CCU_Req = %d", ret) + } else { + LoggerFormatInfo(LOGGER, LOG_SIGN4, "ERROR Set_CCU_Req = %d", ret) + } +#endif + + SystemDelayMs(40); + + for (uint8_t i = 0; i < LIN4_SENSOR_COUNT; ++i) { + + ret = Get_Sensor4_Stat(env->linIo, env->linData, &env->Stat[i], LIN4_SENSON_LEN_Stat[i], + LIN4_SENSON_ADR_Stat[i]); + + if (ret == LIN_RX_COMPLETED) { + env->error_connect[i] = 0; +#if (LOG_LIN4_SENSOR == 1) + switch (i) { + + case eeAirQS_Stat: { + tAirQS_Stat *pAirQS_Stat = (tAirQS_Stat *) &env->Stat[i]; + + + LoggerFormatInfo(LOGGER, LOG_SIGN4, + "AirQS_LinRespErr_Stat = %d AirQS_Sens_Stat = %d AirQS_Combined_Stat = %d AirQS_Err_Stat = %d AirQS_COLvl_Stat = %d AirQS_NOxLvl_Stat = %d AirQS_NH3Lvl_Stat = %d", + pAirQS_Stat->AirQS_LinRespErr_Stat, + pAirQS_Stat->AirQS_Sens_Stat, + pAirQS_Stat->AirQS_Combined_Stat, + pAirQS_Stat->AirQS_Err_Stat, + pAirQS_Stat->AirQS_COLvl_Stat, + pAirQS_Stat->AirQS_NOxLvl_Stat, + pAirQS_Stat->AirQS_NH3Lvl_Stat) + + + break; + } + case eeAroma_Stat: { + tAroma_Stat *pAroma_Stat = (tAroma_Stat *) &env->Stat[i]; + + + LoggerFormatInfo(LOGGER, LOG_SIGN4, + "Aroma_LinRespErr_Stat = %d Aroma_CartridgeSw_Stat = %d Aroma_Err_Stat = %d Aroma_Intens_Stat = %d Aroma_CartridgeFlavor_Stat = %d Aroma_CartridgeCapacity_Stat = %d", + pAroma_Stat->Aroma_LinRespErr_Stat, + pAroma_Stat->Aroma_CartridgeSw_Stat, + pAroma_Stat->Aroma_Err_Stat, + pAroma_Stat->Aroma_Intens_Stat, + pAroma_Stat->Aroma_CartridgeFlavor_Stat, + pAroma_Stat->Aroma_CartridgeCapacity_Stat) + + break; + } + + case eeIonizer_Stat: { + tIonizer_Stat *pIonizer_Stat = (tIonizer_Stat *) &env->Stat[i]; + + + LoggerFormatInfo(LOGGER, LOG_SIGN4, + "Ionizer_LinRespErr_Stat = %d Ionizer_Err_Stat = %d Ionizer_Ionization_Stat = %d", + pIonizer_Stat->Ionizer_LinRespErr_Stat, + pIonizer_Stat->Ionizer_Err_Stat, + pIonizer_Stat->Ionizer_Ionization_Stat) + + + break; + } + case eeTXV_fHVAC_Stat: { + teTXV_fHVAC_Stat *p_teTXV_fHVAC_Stat = (teTXV_fHVAC_Stat *) &env->Stat[i]; + + + LoggerFormatInfo(LOGGER, LOG_SIGN4, + "eTXV_fHVAC_Pos_Stat = %d eTXV_fHVAC_LinRespErr_Stat = %d eTXV_fHVAC_Err_Stat = %d eTXV_fHVAC_Pressure_Val = %d eTXV_fHVAC_Temp_Val = %d", + p_teTXV_fHVAC_Stat->eTXV_fHVAC_Pos_Stat, + p_teTXV_fHVAC_Stat->eTXV_fHVAC_LinRespErr_Stat, + p_teTXV_fHVAC_Stat->eTXV_fHVAC_Err_Stat, + p_teTXV_fHVAC_Stat->eTXV_fHVAC_Pressure_Val, + p_teTXV_fHVAC_Stat->eTXV_fHVAC_Temp_Val) + + + break; + } + + case eeTXV_rHVAC_Stat: { + teTXV_rHVAC_Stat *p_teTXV_rHVAC_Stat = (teTXV_rHVAC_Stat *) &env->Stat[i]; + + + LoggerFormatInfo(LOGGER, LOG_SIGN4, + "eTXV_rHVAC_Pos_Stat = %d eTXV_rHVAC_LinRespErr_Stat = %d eTXV_rHVAC_Err_Stat = %d eTXV_fHVAC_Pressure_Val = %d eTXV_rHVAC_Temp_Val = %d", + p_teTXV_rHVAC_Stat->eTXV_rHVAC_Pos_Stat, + p_teTXV_rHVAC_Stat->eTXV_rHVAC_LinRespErr_Stat, + p_teTXV_rHVAC_Stat->eTXV_rHVAC_Err_Stat, + p_teTXV_rHVAC_Stat->eTXV_rHVAC_Pressure_Val, + p_teTXV_rHVAC_Stat->eTXV_rHVAC_Temp_Val) + + + break; + } + + case eeTXV_batChiller_Stat: { + teTXV_batChiller_Stat *p_teTXV_batChiller_Stat = (teTXV_batChiller_Stat *) &env->Stat[i]; + + + LoggerFormatInfo(LOGGER, LOG_SIGN4, + "eTXV_batChiller_Pos_Stat = %d eTXV_batChiller_LinRespErr_Stat = %d eTXV_batChiller_Err_Stat = %d eTXV_batChiller_Pressure_Val = %d eTXV_batChiller_Temp_Val = %d", + p_teTXV_batChiller_Stat->eTXV_batChiller_Pos_Stat, + p_teTXV_batChiller_Stat->eTXV_batChiller_LinRespErr_Stat, + p_teTXV_batChiller_Stat->eTXV_batChiller_Err_Stat, + p_teTXV_batChiller_Stat->eTXV_batChiller_Pressure_Val, + p_teTXV_batChiller_Stat->eTXV_batChiller_Temp_Val) + + + break; + } + + case eeTXV_eeChiller_Stat: { + teTXV_eeChiller_Stat *p_teTXV_eeChiller_Stat = (teTXV_eeChiller_Stat *) &env->Stat[i]; + + LoggerFormatInfo(LOGGER, LOG_SIGN4, + "eTXV_eeChiller_Stat_ = %d eTXV_eeChiller_LinRespErr_Stat = %d eTXV_eeChiller_Err_Stat = %d eTXV_eeChiller_Pressure_Val = %d eTXV_eeChiller_Temp_Val = %d", + p_teTXV_eeChiller_Stat->eTXV_eeChiller_Pos_Stat, + p_teTXV_eeChiller_Stat->eTXV_eeChiller_LinRespErr_Stat, + p_teTXV_eeChiller_Stat->eTXV_eeChiller_Err_Stat, + p_teTXV_eeChiller_Stat->eTXV_eeChiller_Pressure_Val, + p_teTXV_eeChiller_Stat->eTXV_eeChiller_Temp_Val) + + break; + } + } +#endif + } else { + env->error_connect[i] = 1; + +#if (LOG_LIN4_SENSOR == 1) + switch (i) { + + case eeAirQS_Stat: { + tAirQS_Stat *pAirQS_Stat = (tAirQS_Stat *) &env->Stat[i]; + + LoggerFormatInfo(LOGGER, LOG_SIGN4, "LIN4 ERROR (pAirQS_Stat) = %d", ret) + + break; + } + case eeAroma_Stat: { + tAroma_Stat *pAroma_Stat = (tAroma_Stat *) &env->Stat[i]; + + LoggerFormatInfo(LOGGER, LOG_SIGN4, "LIN4 ERROR (pAroma_Stat) = %d", ret) + + break; + } + + case eeIonizer_Stat: { + tIonizer_Stat *pIonizer_Stat = (tIonizer_Stat *) &env->Stat[i]; + + LoggerFormatInfo(LOGGER, LOG_SIGN4, "LIN4 ERROR (pIonizer_Stat) = %d", ret) + + break; + } + case eeTXV_fHVAC_Stat: { + teTXV_fHVAC_Stat *p_teTXV_fHVAC_Stat = (teTXV_fHVAC_Stat *) &env->Stat[i]; + + LoggerFormatInfo(LOGGER, LOG_SIGN4, "LIN4 ERROR (p_teTXV_fHVAC_Stat) = %d", ret) + + break; + } + + case eeTXV_rHVAC_Stat: { + teTXV_rHVAC_Stat *p_teTXV_rHVAC_Stat = (teTXV_rHVAC_Stat *) &env->Stat[i]; + + LoggerFormatInfo(LOGGER, LOG_SIGN4, "LIN4 ERROR (p_teTXV_rHVAC_Stat) = %d", ret) + + break; + } + + case eeTXV_batChiller_Stat: { + teTXV_batChiller_Stat *p_teTXV_batChiller_Stat = (teTXV_batChiller_Stat *) &env->Stat[i]; + + LoggerFormatInfo(LOGGER, LOG_SIGN4, "LIN4 ERROR (p_teTXV_batChiller_Stat) = %d", ret) + + break; + } + + case eeTXV_eeChiller_Stat: { + teTXV_eeChiller_Stat *p_teTXV_eeChiller_Stat = (teTXV_eeChiller_Stat *) &env->Stat[i]; + + LoggerFormatInfo(LOGGER, LOG_SIGN4, "LIN4 ERROR (p_teTXV_eeChiller_Stat) = %d", ret) + + break; + } + } +#endif + } + + } + + return LIN_NO_EVENT; +} + +void Lin_4_Init(tLin4TaskSensor *env, + tLinData *linData, + tLinIO *linIO, + tLoggerInterface *logger) { + + env->linIo = linIO; + env->linData = linData; + env->logger = logger; + env->access = osMutexNew(NULL); + + env->queue_input_tCCU = osMessageQueueNew(1, sizeof(LIN4_CCU_Req_Bus), NULL); + + env->queue_input_tAirQS = osMessageQueueNew(1, sizeof(LIN4_AirQS_Stat_Bus), NULL); + env->queue_input_tAroma = osMessageQueueNew(1, sizeof(LIN4_Aroma_Stat_Bus), NULL); + env->queue_input_tIonizer = osMessageQueueNew(1, sizeof(LIN4_Ionizer_Stat_Bus), NULL); + env->queue_input_teTXV_fHVAC = osMessageQueueNew(1, sizeof(LIN4_eTXV_fHVAC_Stat_Bus), NULL); + env->queue_input_teTXV_rHVAC = osMessageQueueNew(1, sizeof(LIN4_eTXV_rHVAC_Stat_Bus), NULL); + env->queue_input_teTXV_batChiller = osMessageQueueNew(1, sizeof(LIN4_eTXV_batChiller_Stat_Bus), NULL); + env->queue_input_teTXV_eeChiller = osMessageQueueNew(1, sizeof(LIN4_eTXV_eeChiller_Stat_Bus), NULL); + env->queue_input_Lin4_Stat = osMessageQueueNew(1, sizeof(SensorLin4CmdBusInput), NULL); + + + InitThreadAtrStatic(&env->threadLin.attr, "Ln4", env->threadLin.controlBlock, env->threadLin.stack, + osPriorityNormal); +} + + +static _Noreturn void Lin4_Thread(tLin4TaskSensor *env) { + for (;;) { + + if (osMutexAcquire(env->access, 1000) == osOK) { + + Lin4_Input_Set_Model(env); + + lin_event_id_t res = Lin4_Scheduler(env); + + uint8_t isError = 0; + for (uint8_t i = 0; i < LIN4_SENSOR_COUNT; ++i) { + if (env->error_connect[i] == 1) + ++isError; + } + + if (isError == LIN4_SENSOR_COUNT) { + env->error_all_connect = 1; + } else { + env->error_all_connect = 0; + } + + + Lin4_Output_Set_Model(env); + + osMutexRelease(env->access); + } + } +} + +void Lin4_StartThread(tLin4TaskSensor *env) { + if (!env->threadLin.id) { + env->threadLin.id = osThreadNew((osThreadFunc_t) (Lin4_Thread), (void *) (env), &env->threadLin.attr); + SystemDelayMs(10); + } +} + +//конец----------------------------------------- LIN 4 ---------------------------------------------------------------- +//конец----------------------------------------- LIN 4 ---------------------------------------------------------------- +//конец----------------------------------------- LIN 4 ---------------------------------------------------------------- +//конец----------------------------------------- LIN 4 ---------------------------------------------------------------- + +//начало----------------------------------------- LIN 5 ---------------------------------------------------------------- +//начало----------------------------------------- LIN 5 ---------------------------------------------------------------- +//начало----------------------------------------- LIN 5 ---------------------------------------------------------------- +//начало----------------------------------------- LIN 5 --------------------------------------------------------------- + +static lin_event_id_t Set_CCU_DRS_Req(tLinIO *linIo, tLinData *linData, tCCU_DRS_Req *p_CCU_DRS_Req) { + lin_event_id_t res; + + linData->direction = LIN_DIRECTION_SET; + + linData->g_aTxBufferLen = sizeof(tCCU_DRS_Req); + linData->g_aRxBufferLen = 0; + + memcpy(linData->g_aTxBuffer, p_CCU_DRS_Req, sizeof(tCCU_DRS_Req)); + + uint8_t retry = 1; + + while (retry) { + + res = SEND_SENSOR_COM_x(linIo, CCU_DRS_Req); + + if (res == LIN_TX_COMPLETED) { + break; + } + + --retry; + } + + return res; +} + +/* +static lin_event_id_t Get_DRS_DL_Stat(tLinIO *linIo, tLinData *linData, tDRS_DL_Stat *p_tDRS_DL_Stat) { + lin_event_id_t res; + + tDRS_DL_Stat *tDRS_DL_Stat_ = (tDRS_DL_Stat *) linData->g_aRxBuffer; + + uint8_t retry = 3; + + while (retry) { + + linData->direction = LIN_DIRECTION_GET; + + linData->g_aTxBufferLen = 0; + linData->g_aRxBufferLen = sizeof(tDRS_DL_Stat); + + res = SEND_SENSOR_COM_x(linIo, DRS_DL_Stat); + + if (res == LIN_RX_COMPLETED) { + memcpy(p_tDRS_DL_Stat, tDRS_DL_Stat_, sizeof(tDRS_DL_Stat)); + break; + } + + --retry; + } + + return res; +} +*/ +static lin_event_id_t Get_DRS_Stat(tLinIO *linIo, tLinData *linData, tDRS_Stat *p_tDRS_Stat, uint8_t DRS_stat) { + lin_event_id_t res; + + tDRS_Stat *tDRS_Stat_ = (tDRS_Stat *) linData->g_aRxBuffer; + + uint8_t retry = 3; + + while (retry) { + + linData->direction = LIN_DIRECTION_GET; + + linData->g_aTxBufferLen = 0; + linData->g_aRxBufferLen = sizeof(tDRS_Stat); + + res = SEND_SENSOR_COM_x(linIo, DRS_stat); + + if (res == LIN_RX_COMPLETED) { + memcpy(p_tDRS_Stat, tDRS_Stat_, sizeof(tDRS_Stat)); + break; + } + + --retry; + } + + return res; +} + +// Вспомогательная функция: устанавливает три бита для группы led_group +// в соответствии со значением count (0, 1, 2, 3) +static void set_led_group(tCCU_DRS_Req *req, uint8_t led_group, uint8_t count) { + // Определяем, какой из трёх битов должен быть установлен + + uint8_t b1 = 0; + uint8_t b2 = 0; + uint8_t b3 = 0; + + if (count == 1) { + b1 = 0; + b2 = 0; + b3 = 1; + } + + if (count == 2) { + b1 = 0; + b2 = 1; + b3 = 1; + } + + if (count == 3) { + b1 = 1; + b2 = 1; + b3 = 1; + } + + switch (led_group) { + case 0: + req->CCU_DLLed1_Req = b1; + req->CCU_DLLed2_Req = b2; + req->CCU_DLLed3_Req = b3; + break; + case 1: + req->CCU_DRLed1_Req = b1; + req->CCU_DRLed2_Req = b2; + req->CCU_DRLed3_Req = b3; + break; + case 2: + req->CCU_FPLLed1_Req = b1; + req->CCU_FPLLed2_Req = b2; + req->CCU_FPLLed3_Req = b3; + break; + case 3: + req->CCU_FPRLed1_Req = b1; + req->CCU_FPRLed2_Req = b2; + req->CCU_FPRLed3_Req = b3; + break; + case 4: + req->CCU_RLBLed1_Req = b1; + req->CCU_RLBLed2_Req = b2; + req->CCU_RLBLed3_Req = b3; + break; + case 5: + req->CCU_RRBLed1_Req = b1; + req->CCU_RRBLed2_Req = b2; + req->CCU_RRBLed3_Req = b3; + break; + case 6: + req->CCU_FCLLed1_Req = b1; + req->CCU_FCLLed2_Req = b2; + req->CCU_FCLLed3_Req = b3; + break; + case 7: + req->CCU_FCRLed1_Req = b1; + req->CCU_FCRLed2_Req = b2; + req->CCU_FCRLed3_Req = b3; + break; + default: + // Недопустимый индекс – можно ничего не делать или добавить assert + break; + } +} + + +void Lin5_Input_Set_From_Model(tLin5TaskSensor *env) { + + uint32_t countQueue_space = osMessageQueueGetSpace(env->queue_led_input_model_count); + + if (countQueue_space) { + osStatus_t status = osMessageQueuePut(env->queue_led_input_model_count, &rtY.DRS_output, 0, + 0); + } + +} + +static void Lin5_Input_Get_From_Model(tLin5TaskSensor *env) { + + uint32_t countQueue_space = osMessageQueueGetSpace(env->queue_led_input_model_count); + + if (countQueue_space == 0) { + osStatus_t status = osMessageQueueGet(env->queue_led_input_model_count, &env->linStateSensorModelOutput, 0, 0); + + memcpy(env->linStateSensor.LED_COUNT, env->linStateSensorModelOutput.LED_COUNT, LIN5_SENSOR_COUNT); + + for (uint8_t i = 0; i < LIN5_SENSOR_COUNT; ++i) { + set_led_group(&env->d_CCU_DRS_Req, i, env->linStateSensor.LED_COUNT[i]); + } + + } + +} + + +void Lin5_Output_Get_From_Model(tLin5TaskSensor *env) { + + uint32_t countQueue_space = osMessageQueueGetSpace(env->queue_led_count); + + if (countQueue_space == 0) { + osStatus_t status = osMessageQueueGet(env->queue_led_count, &rtDW.LIN5_SENSON_ADR_Stat_model, 0, 0); + } + +} + + +static lin_event_id_t Lin5_Scheduler(tLin5TaskSensor *env) { + lin_event_id_t ret = LIN_NO_EVENT; + + for (uint8_t i = 0; i < LIN5_SENSOR_COUNT; ++i) { + +// if (env->linStateSensor.error_connect[i] == 0) { + + ret = Get_DRS_Stat(env->linIo, env->linData, &env->linStateSensor.d_DRS_Stat[i], LIN5_SENSON_ADR_Stat[i]); + + uint8_t current_btn_state = env->linStateSensor.d_DRS_Stat[i].DRS_Btn_Stat; + + if (current_btn_state) { + env->linStateSensor.LED_COUNT[i] = 1; + } else { + env->linStateSensor.LED_COUNT[i] = 0; + } + + /* + if ((current_btn_state) && (!env->linStateSensor.prev_btn_state[i])) { + + env->linStateSensor.LED_COUNT[i] = 1; + + } + env->linStateSensor.prev_btn_state[i] = current_btn_state; +*/ + + env->linStateSensor.LinRespErr_Stat[i] = env->linStateSensor.d_DRS_Stat[i].DRS_LinRespErr_Stat; + env->linStateSensor.Err_Stat[i] = env->linStateSensor.d_DRS_Stat[i].DRS_Err_Stat; + + if (ret == LIN_RX_COMPLETED) { + env->linStateSensor.error_connect[i] = 0; +#if (LOG_LIN5_SENSOR == 1) + + if ((*((uint8_t *) &env->linStateSensor.d_DRS_Stat[i]) != + *((uint8_t *) &env->linStateSensor.d_old_DRS_Stat[i])) || + (env->linStateSensor.LED_COUNT[i] != env->linStateSensor.LED_OLD_COUNT[i])) { + + *((uint8_t *) &env->linStateSensor.d_old_DRS_Stat[i]) = *((uint8_t *) &env->linStateSensor.d_DRS_Stat[i]); + env->linStateSensor.LED_OLD_COUNT[i] = env->linStateSensor.LED_COUNT[i]; + + LoggerFormatInfo(LOGGER, LOG_SIGN5, + "Sensor number %d: COUNT = %d DRS_Btn_Stat = %d DRS_LinRespErr_Stat = %d DRS_Err_Stat = %d", + i, + env->linStateSensor.LED_COUNT[i], + env->linStateSensor.d_DRS_Stat[i].DRS_Btn_Stat, + env->linStateSensor.d_DRS_Stat[i].DRS_LinRespErr_Stat, + env->linStateSensor.d_DRS_Stat[i].DRS_Err_Stat + ) + } +#endif + } else { + env->linStateSensor.error_connect[i] = 1; +#if (LOG_LIN5_SENSOR == 1) + if (env->linStateSensor.error_connect[i] != env->linStateSensor.error_old_connect[i]) { + env->linStateSensor.error_old_connect[i] = env->linStateSensor.error_connect[i]; + LoggerFormatInfo(LOGGER, LOG_SIGN5, "Sensor number %d: ERROR Get_FPL_Stat = %d", i, ret) + } +#endif + } + +// } + + } + + uint32_t countQueue_led_count = osMessageQueueGetSpace(env->queue_led_count); + + osStatus_t status = osOK; + if (countQueue_led_count) { + + memcpy(env->sensorButtonCmdBusInput.in_COUNT, env->linStateSensor.LED_COUNT, LIN5_SENSOR_COUNT); + memcpy(env->sensorButtonCmdBusInput.in_error_connect, env->linStateSensor.error_connect, LIN5_SENSOR_COUNT); + memcpy(env->sensorButtonCmdBusInput.LinRespErr_Stat, env->linStateSensor.LinRespErr_Stat, LIN5_SENSOR_COUNT); + memcpy(env->sensorButtonCmdBusInput.Err_Stat, env->linStateSensor.Err_Stat, LIN5_SENSOR_COUNT); + env->sensorButtonCmdBusInput.Error_Connect = env->error_connect; + + status = osMessageQueuePut(env->queue_led_count, env->linStateSensor.LED_COUNT, 0, 0U); + } + + + Lin5_Input_Get_From_Model(env); + + if (*((uint32_t *) &env->d_CCU_DRS_Req) != *((uint32_t *) &env->d_old_CCU_DRS_Req)) { + + SystemDelayMs(40); + + ret = Set_CCU_DRS_Req(env->linIo, env->linData, &env->d_CCU_DRS_Req); + + if (ret == LIN_TX_COMPLETED) { + + env->d_CCU_DRS_Req.BCM_SwIndIntens_Stat = 0; + env->d_CCU_DRS_Req.BCM_IndFadingTime_Req = 0; + + if (*((uint32_t *) &env->d_CCU_DRS_Req) != *((uint32_t *) &env->d_old_CCU_DRS_Req)) { + *((uint32_t *) &env->d_old_CCU_DRS_Req) = *((uint32_t *) &env->d_CCU_DRS_Req); +#if (LOG_LIN5_SENSOR == 1) + LoggerInfoStatic(LOGGER, LOG_SIGN5, "Sensor Set_CCU_DRS_Req - OK") +#endif + + } + } else { + if (*((uint32_t *) &env->d_CCU_DRS_Req) != *((uint32_t *) &env->d_old_CCU_DRS_Req)) { + +#if (LOG_LIN5_SENSOR == 1) + LoggerFormatInfo(LOGGER, LOG_SIGN5, "Sensor Set_CCU_DRS_Req (ERROR %d)", ret) +#endif + } + } + + SystemDelayMs(40); + } + + + return LIN_NO_EVENT; +} + +void Lin_5_Init(tLin5TaskSensor *env, + tLinData *linData, + tLinIO *linIO, + tLoggerInterface *logger) { + + env->linIo = linIO; + env->linData = linData; + env->logger = logger; + env->access = osMutexNew(NULL); + + env->queue_led_count = osMessageQueueNew(1, sizeof(env->linStateSensor.LED_COUNT), NULL); + env->queue_led_input_model_count = osMessageQueueNew(1, sizeof(LinStateSensorModel), NULL); + + InitThreadAtrStatic(&env->threadLin.attr, "Ln5", env->threadLin.controlBlock, env->threadLin.stack, + osPriorityNormal); +} + + +static _Noreturn void Lin5_Thread(tLin5TaskSensor *env) { + for (;;) { + + if (osMutexAcquire(env->access, 2000) == osOK) { + + lin_event_id_t res = Lin5_Scheduler(env); + + uint8_t isError = 0; + for (uint8_t i = 0; i < LIN5_SENSOR_COUNT; ++i) { + if (env->linStateSensor.error_connect[i] == 1) + ++isError; + } + + if (isError == LIN5_SENSOR_COUNT) { + env->error_connect = 1; + } else { + env->error_connect = 0; + } + + + osMutexRelease(env->access); + } else { + LoggerErrorStatic(LOGGER, LOG_SIGN5, "Access error Lin5_Thread"); + } + + } +} + +void Lin5_StartThread(tLin5TaskSensor *env) { + if (!env->threadLin.id) { + env->threadLin.id = osThreadNew((osThreadFunc_t) (Lin5_Thread), (void *) (env), &env->threadLin.attr); + SystemDelayMs(10); + } +} + +//конец----------------------------------------- LIN 5 ---------------------------------------------------------------- +//конец----------------------------------------- LIN 5 ---------------------------------------------------------------- +//конец----------------------------------------- LIN 5 ---------------------------------------------------------------- +//конец----------------------------------------- LIN 5 ---------------------------------------------------------------- \ No newline at end of file diff --git a/MODULES/HVAC_M7_LIN_TASKS/LinSensorTasks.h b/MODULES/HVAC_M7_LIN_TASKS/LinSensorTasks.h new file mode 100644 index 0000000..11a5ebe --- /dev/null +++ b/MODULES/HVAC_M7_LIN_TASKS/LinSensorTasks.h @@ -0,0 +1,437 @@ +// +// Created by cfif on 12.02.2026. +// + +#ifndef HVAC_M7_LINSENSORTASKS_H +#define HVAC_M7_LINSENSORTASKS_H + +#include +#include "stdbool.h" +#include "LinIO.h" +#include "LoggerInterface.h" +#include "HVAC_model.h" + +#define LOG_LIN4_SENSOR 0 +#define LOG_LIN5_SENSOR 0 + + +#define LIN4_SENSOR_COUNT 7 + +typedef enum { + eeAirQS_Stat = 0, + eeAroma_Stat = 1, + eeIonizer_Stat = 2, + eeTXV_fHVAC_Stat = 3, + eeTXV_rHVAC_Stat = 4, + eeTXV_batChiller_Stat = 5, + eeTXV_eeChiller_Stat = 6 +} eSensorStat4; + +#define AirQS_Stat 0x14 +#define Aroma_Stat 0x5 +#define CCU_Req 0x1 +#define Ionizer_Stat 0x1C +#define eTXV_fHVAC_Stat 0x1E +#define eTXV_rHVAC_Stat 0x20 +#define eTXV_batChiller_Stat 0x22 +#define eTXV_eeChiller_Stat 0x24 + +#define LIN5_SENSOR_COUNT 8 + +#define CCU_DRS_Req 0x1 +#define DRS_DL_Stat 0xD +#define DRS_DR_Stat 0x12 +#define DRS_FPL_Stat 0x17 +#define DRS_FPR_Stat 0x1C +#define DRS_RLB_Stat 0x21 +#define DRS_RRB_Stat 0x26 +#define DRS_FCL_Stat 0x2B +#define DRS_FCR_Stat 0x30 + + +typedef struct __attribute__ ((packed)) { + uint8_t AirQS_LinRespErr_Stat: 1; // 0 + uint8_t AirQS_Sens_Stat: 2; // 1 + uint8_t AirQS_Combined_Stat: 3; // 3 + uint8_t unused1: 2; // 6 + uint8_t AirQS_Err_Stat: 3; // 8 + uint8_t AirQS_COLvl_Stat: 4; // 11 + uint8_t unused2: 1; // 15 + uint8_t AirQS_NOxLvl_Stat: 4; // 16 + uint8_t AirQS_NH3Lvl_Stat: 4; // 20 +} tAirQS_Stat; + +typedef struct __attribute__ ((packed)) { + uint8_t Aroma_LinRespErr_Stat: 1; // 0 + uint8_t Aroma_CartridgeSw_Stat: 1; // 1 + uint8_t unused1: 2; // 2 + uint8_t Aroma_Err_Stat: 2; // 4 + uint8_t Aroma_Intens_Stat: 2; // 6 + uint8_t unused2: 2; // 8 + uint8_t Aroma_CartridgeFlavor_Stat: 4; // 10 + uint16_t unused3: 10; // биты 14–23 + uint8_t Aroma_CartridgeCapacity_Stat: 4; // 24 + uint8_t unused4: 4; // биты 28–31 + uint8_t unused5: 8; // биты 32–39 +} tAroma_Stat; + +typedef struct __attribute__ ((packed)) { + uint8_t CCU_Ionization_Req: 1; // 0 + uint8_t unused1: 2; // 1 + uint8_t CCU_AromaIntens_Req: 2; // 3 + uint8_t unused2: 3; // биты 5–7 + uint8_t unused3: 8; // биты 8–15 + uint8_t unused4: 8; // биты 16–23 + uint8_t CCU_AirQS_Req: 1; // 24 + uint8_t CCU_fHVAC_Pos_Val: 7; // 25 + uint8_t CCU_rHVAC_Pos_Val: 7; // 32 + uint8_t unused5: 1; // 39 + uint8_t CCU_batChiller_Pos_Val: 7; // 40 + uint8_t unused6: 1; // 47 + uint8_t CCU_eeChiller_Pos_Val: 7; // 48 + uint8_t unused7: 1; // 55 – явное заполнение +} tCCU_Req; + +typedef struct __attribute__ ((packed)) { + uint8_t Ionizer_LinRespErr_Stat: 1; // 0 + uint8_t Ionizer_Err_Stat: 2; // 1 + uint8_t unused1: 5; // 3 + uint8_t Ionizer_Ionization_Stat: 1; // 8 +} tIonizer_Stat; + +typedef struct __attribute__ ((packed)) { + uint8_t eTXV_fHVAC_Pos_Stat: 7; // 0 + uint8_t eTXV_fHVAC_LinRespErr_Stat: 1; // 7 + uint8_t eTXV_fHVAC_Err_Stat: 2; // 8 + uint8_t eTXV_fHVAC_Pressure_Val: 6; // 10 + uint8_t eTXV_fHVAC_Temp_Val: 7; // 16 +} teTXV_fHVAC_Stat; + +typedef struct __attribute__ ((packed)) { + uint8_t eTXV_rHVAC_Pos_Stat: 7; // 0 + uint8_t eTXV_rHVAC_LinRespErr_Stat: 1; // 7 + uint8_t eTXV_rHVAC_Err_Stat: 2; // 8 + uint8_t eTXV_rHVAC_Pressure_Val: 6; // 10 + uint8_t eTXV_rHVAC_Temp_Val: 7; // 16 +} teTXV_rHVAC_Stat; + +typedef struct __attribute__ ((packed)) { + uint8_t eTXV_batChiller_Pos_Stat: 7; // 0 + uint8_t eTXV_batChiller_LinRespErr_Stat: 1; // 7 + uint8_t eTXV_batChiller_Err_Stat: 2; // 8 + uint8_t eTXV_batChiller_Pressure_Val: 6; // 10 + uint8_t eTXV_batChiller_Temp_Val: 7; // 16 +} teTXV_batChiller_Stat; + +typedef struct __attribute__ ((packed)) { + uint8_t eTXV_eeChiller_Pos_Stat: 7; // 0 + uint8_t eTXV_eeChiller_LinRespErr_Stat: 1; // 7 + uint8_t eTXV_eeChiller_Err_Stat: 2; // 8 + uint8_t eTXV_eeChiller_Pressure_Val: 6; // 10 + uint8_t eTXV_eeChiller_Temp_Val: 7; // 16 +} teTXV_eeChiller_Stat; + + +typedef struct { + uint8_t CCU_Ionization_Req; + uint8_t CCU_AromaIntens_Req; + uint8_t CCU_AirQS_Req; + uint8_t CCU_fHVAC_Pos_Val; + uint8_t CCU_rHVAC_Pos_Val; + uint8_t CCU_batChiller_Pos_Val; + uint8_t CCU_eeChiller_Pos_Val; +} tCCU_Req_For_Model; + +typedef struct { + uint8_t AirQS_LinRespErr_Stat; + uint8_t AirQS_Sens_Stat; + uint8_t AirQS_Combined_Stat; + uint8_t AirQS_Err_Stat; + uint8_t AirQS_COLvl_Stat; + uint8_t AirQS_NOxLvl_Stat; + uint8_t AirQS_NH3Lvl_Stat; +} tAirQS_Stat_For_Model; + +typedef struct { + uint8_t Aroma_LinRespErr_Stat; + uint8_t Aroma_CartridgeSw_Stat; + uint8_t Aroma_Err_Stat; + uint8_t Aroma_Intens_Stat; + uint8_t Aroma_CartridgeFlavor_Stat; + uint8_t Aroma_CartridgeCapacity_Stat; +} tAroma_Stat_For_Model; + +typedef struct { + uint8_t Ionizer_LinRespErr_Stat; + uint8_t Ionizer_Err_Stat; + uint8_t Ionizer_Ionization_Stat; +} tIonizer_Stat_For_Model; + +typedef struct { + uint8_t eTXV_fHVAC_Pos_Stat; + uint8_t eTXV_fHVAC_LinRespErr_Stat; + uint8_t eTXV_fHVAC_Err_Stat; + uint8_t eTXV_fHVAC_Pressure_Val; + uint8_t eTXV_fHVAC_Temp_Val; +} teTXV_fHVAC_Stat_For_Model; + +typedef struct { + uint8_t eTXV_rHVAC_Pos_Stat; + uint8_t eTXV_rHVAC_LinRespErr_Stat; + uint8_t eTXV_rHVAC_Err_Stat; + uint8_t eTXV_rHVAC_Pressure_Val; + uint8_t eTXV_rHVAC_Temp_Val; +} teTXV_rHVAC_Stat_For_Model; + +typedef struct { + uint8_t eTXV_batChiller_Pos_Stat; + uint8_t eTXV_batChiller_LinRespErr_Stat; + uint8_t eTXV_batChiller_Err_Stat; + uint8_t eTXV_batChiller_Pressure_Val; + uint8_t eTXV_batChiller_Temp_Val; +} teTXV_batChiller_Stat_For_Model; + +typedef struct { + uint8_t eTXV_eeChiller_Pos_Stat; + uint8_t eTXV_eeChiller_LinRespErr_Stat; + uint8_t eTXV_eeChiller_Err_Stat; + uint8_t eTXV_eeChiller_Pressure_Val; + uint8_t eTXV_eeChiller_Temp_Val; +} teTXV_eeChiller_Stat_For_Model; + + +typedef struct __attribute__ ((packed)) { + uint8_t CCU_DLLed1_Req: 1; // 0 + uint8_t CCU_DLLed2_Req: 1; // 1 + uint8_t CCU_DLLed3_Req: 1; // 2 + + uint8_t CCU_DRLed1_Req: 1; // 3 + uint8_t CCU_DRLed2_Req: 1; // 4 + uint8_t CCU_DRLed3_Req: 1; // 5 + + uint8_t CCU_FPLLed1_Req: 1; // 6 + uint8_t CCU_FPLLed2_Req: 1; // 7 + uint8_t CCU_FPLLed3_Req: 1; // 8 + + uint8_t CCU_FPRLed1_Req: 1; // 9 + uint8_t CCU_FPRLed2_Req: 1; // 10 + uint8_t CCU_FPRLed3_Req: 1; // 11 + + uint8_t CCU_RLBLed1_Req: 1; // 12 + uint8_t CCU_RLBLed2_Req: 1; // 13 + uint8_t CCU_RLBLed3_Req: 1; // 14 + + uint8_t CCU_RRBLed1_Req: 1; // 15 + uint8_t CCU_RRBLed2_Req: 1; // 16 + uint8_t CCU_RRBLed3_Req: 1; // 17 + + uint8_t CCU_FCLLed1_Req: 1; // 18 + uint8_t CCU_FCLLed2_Req: 1; // 19 + uint8_t CCU_FCLLed3_Req: 1; // 20 + + uint8_t CCU_FCRLed1_Req: 1; // 21 + uint8_t CCU_FCRLed2_Req: 1; // 22 + uint8_t CCU_FCRLed3_Req: 1; // 23 + + uint8_t BCM_SwIndIntens_Stat: 1; // 24 + uint8_t BCM_IndFadingTime_Req: 5; // 25 +} tCCU_DRS_Req; + +typedef struct __attribute__ ((packed)) { + uint8_t DRS_Btn_Stat: 1; // 0 + uint8_t DRS_LinRespErr_Stat: 1; // 1 + uint8_t DRS_Err_Stat: 1; // 2 +} tDRS_Stat; + +typedef struct __attribute__ ((packed)) { + uint8_t DRS_DL_Btn_Stat: 1; // 0 + uint8_t DRS_DL_LinRespErr_Stat: 1; // 1 + uint8_t DRS_DL_Err_Stat: 1; // 2 +} tDRS_DL_Stat; + +typedef struct __attribute__ ((packed)) { + uint8_t DRS_DR_Btn_Stat: 1; // 0 + uint8_t DRS_DR_LinRespErr_Stat: 1; // 1 + uint8_t DRS_DR_Err_Stat: 1; // 2 +} tDRS_DR_Stat; + +typedef struct __attribute__ ((packed)) { + uint8_t DRS_FCL_Btn_Stat: 1; // 0 + uint8_t DRS_FCL_LinRespErr_Stat: 1; // 1 + uint8_t DRS_FCL_Err_Stat: 1; // 2 +} tDRS_FCL_Stat; + +typedef struct __attribute__ ((packed)) { + uint8_t DRS_FCR_Btn_Stat: 1; // 0 + uint8_t DRS_FCR_LinRespErr_Stat: 1; // 1 + uint8_t DRS_FCR_Err_Stat: 1; // 2 +} tDRS_FCR_Stat; + +typedef struct __attribute__ ((packed)) { + uint8_t DRS_FPL_Btn_Stat: 1; // 0 + uint8_t DRS_FPL_LinRespErr_Stat: 1; // 1 + uint8_t DRS_FPL_Err_Stat: 1; // 2 +} tDRS_FPL_Stat; + +typedef struct __attribute__ ((packed)) { + uint8_t DRS_FPR_Btn_Stat: 1; // 0 + uint8_t DRS_FPR_LinRespErr_Stat: 1; // 1 + uint8_t DRS_FPR_Err_Stat: 1; // 2 +} tDRS_FPR_Stat; + +typedef struct __attribute__ ((packed)) { + uint8_t DRS_RLB_Btn_Stat: 1; // 0 + uint8_t DRS_RLB_LinRespErr_Stat: 1; // 1 + uint8_t DRS_RLB_Err_Stat: 1; // 2 +} tDRS_RLB_Stat; + +typedef struct __attribute__ ((packed)) { + uint8_t DRS_RRB_Btn_Stat: 1; // 0 + uint8_t DRS_RRB_LinRespErr_Stat: 1; // 1 + uint8_t DRS_RRB_Err_Stat: 1; // 2 +} tDRS_RRB_Stat; + +typedef struct { + uint8_t in_error_connect[LIN4_SENSOR_COUNT]; // Конкретное устройство не ответило + uint8_t Error_Connect; // Ошибка LIN шины (ни одно устройство не отвечает) +} SensorLin4CmdBusInput; + +typedef struct { + + tLinIO *linIo; + osMutexId_t access; + + tLinData *linData; + + tLoggerInterface *logger; + + tCCU_Req d_CCU_Req; + uint64_t Stat[LIN4_SENSOR_COUNT]; + + //tCCU_Req_For_Model CCU_Req_For_Model_For_Model; + LIN4_CCU_Req_Bus CCU_Req_For_Model_For_Model; + //tAirQS_Stat_For_Model AirQS_Stat_For_Model; + LIN4_AirQS_Stat_Bus AirQS_Stat_For_Model; + //tAroma_Stat_For_Model Aroma_Stat_For_Model; + LIN4_Aroma_Stat_Bus Aroma_Stat_For_Model; + //tIonizer_Stat_For_Model Ionizer_Stat_For_Model; + LIN4_Ionizer_Stat_Bus Ionizer_Stat_For_Model; + //teTXV_fHVAC_Stat_For_Model eTXV_fHVAC_Stat_For_Model; + LIN4_eTXV_fHVAC_Stat_Bus eTXV_fHVAC_Stat_For_Model; + //teTXV_rHVAC_Stat_For_Model eTXV_rHVAC_Stat_For_Model; + LIN4_eTXV_rHVAC_Stat_Bus eTXV_rHVAC_Stat_For_Model; + //teTXV_batChiller_Stat_For_Model eTXV_batChiller_Stat_For_Model; + LIN4_eTXV_batChiller_Stat_Bus eTXV_batChiller_Stat_For_Model; + //teTXV_eeChiller_Stat_For_Model eTXV_eeChiller_Stat_For_Model; + LIN4_eTXV_eeChiller_Stat_Bus eTXV_eeChiller_Stat_For_Model; + + SensorLin4CmdBusInput sensorLin4CmdBusInput; + + + osMessageQueueId_t queue_input_tCCU; + + osMessageQueueId_t queue_input_tAirQS; + osMessageQueueId_t queue_input_tAroma; + osMessageQueueId_t queue_input_tIonizer; + osMessageQueueId_t queue_input_teTXV_fHVAC; + osMessageQueueId_t queue_input_teTXV_rHVAC; + osMessageQueueId_t queue_input_teTXV_batChiller; + osMessageQueueId_t queue_input_teTXV_eeChiller; + osMessageQueueId_t queue_input_Lin4_Stat; + + uint8_t error_connect[LIN4_SENSOR_COUNT]; + uint8_t error_all_connect; + + struct { + osThreadId_t id; + uint32_t stack[384]; + StaticTask_t controlBlock; + osThreadAttr_t attr; + } threadLin; + + +} tLin4TaskSensor; + + +typedef struct { + uint8_t in_COUNT[LIN5_SENSOR_COUNT]; // Уровень (0,1,2,3) + uint8_t in_error_connect[LIN5_SENSOR_COUNT]; // Конкретное устройство не ответило + uint8_t LinRespErr_Stat[LIN5_SENSOR_COUNT]; // Внутренняя ошибка устройства (ошибка коммутации) + uint8_t Err_Stat[LIN5_SENSOR_COUNT]; // Внутренняя ошибка устройства + uint8_t Error_Connect; // Ошибка LIN шины (ни одно устройство не отвечает) +} SensorLin5ButtonCmdBusInput; + +typedef struct { + uint8_t LED_COUNT[LIN5_SENSOR_COUNT]; +} LinStateSensorModel; + +typedef struct { + + tLinIO *linIo; + osMutexId_t access; + + tLinData *linData; + + tLoggerInterface *logger; + + SensorLin5ButtonCmdBusInput sensorButtonCmdBusInput; + +// LinStateSensorModel linStateSensorModelInput; + LinStateSensorModel linStateSensorModelOutput; + + osMessageQueueId_t queue_led_count; + osMessageQueueId_t queue_led_input_model_count; + + struct { + tDRS_Stat d_DRS_Stat[LIN5_SENSOR_COUNT]; + tDRS_Stat d_old_DRS_Stat[LIN5_SENSOR_COUNT]; + uint8_t LED_COUNT[LIN5_SENSOR_COUNT]; + + uint8_t LED_OLD_COUNT[LIN5_SENSOR_COUNT]; + uint8_t error_connect[LIN5_SENSOR_COUNT]; + uint8_t error_old_connect[LIN5_SENSOR_COUNT]; + +// uint8_t prev_btn_state[LIN5_SENSOR_COUNT]; + + uint8_t LinRespErr_Stat[LIN5_SENSOR_COUNT]; + uint8_t Err_Stat[LIN5_SENSOR_COUNT]; + } linStateSensor; + + uint8_t error_connect; + + tCCU_DRS_Req d_CCU_DRS_Req; + tCCU_DRS_Req d_old_CCU_DRS_Req; + + struct { + osThreadId_t id; + uint32_t stack[384]; + StaticTask_t controlBlock; + osThreadAttr_t attr; + } threadLin; + + +} tLin5TaskSensor; + + +void Lin_4_Init(tLin4TaskSensor *env, + tLinData *linData, + tLinIO *linIO, + tLoggerInterface *logger); + +void Lin4_StartThread(tLin4TaskSensor *env); + +void Lin4_Input_Set_From_Model(tLin4TaskSensor *env); +void Lin4_Output_Get_From_Model(tLin4TaskSensor *env); + +void Lin_5_Init(tLin5TaskSensor *env, + tLinData *linData, + tLinIO *linIO, + tLoggerInterface *logger); + +void Lin5_StartThread(tLin5TaskSensor *env); + +void Lin5_Output_Get_From_Model(tLin5TaskSensor *env); + +void Lin5_Input_Set_From_Model(tLin5TaskSensor *env); + +#endif //HVAC_M7_LINSENSORTASKS_H diff --git a/MODULES/HVAC_M7_LIN_TASKS/modular.json b/MODULES/HVAC_M7_LIN_TASKS/modular.json new file mode 100644 index 0000000..99df025 --- /dev/null +++ b/MODULES/HVAC_M7_LIN_TASKS/modular.json @@ -0,0 +1,10 @@ +{ + "cmake": { + "inc_dirs": [ + "./" + ], + "srcs": [ + "./**.c" + ] + } +} diff --git a/MODULES/HVAC_M7_Lins/Lins.c b/MODULES/HVAC_M7_Lins/Lins.c new file mode 100644 index 0000000..d97b850 --- /dev/null +++ b/MODULES/HVAC_M7_Lins/Lins.c @@ -0,0 +1,515 @@ +// +// Created by Cfif on 14.12.23. +// +#include +#include "fc7xxx_driver_port.h" +#include "fc7xxx_driver_gpio.h" +#include "Lins.h" + +tLinPorts LIN_PORTS; + + + +//начало--------------------------LIN 1------------------------------------------------- +//начало--------------------------LIN 1------------------------------------------------- +//начало--------------------------LIN 1------------------------------------------------- + +#define numOfClassicPID 20 + +const uint8_t classicPID[numOfClassicPID] = { + CFR_INI, + CFR_SET, + CFR_MOD, + CFR_ADR, + CFR_PRG, + DFR_PRG, + RFR_PRG, + RFR_ISSR1, + RFR_ISSR2, + RFR_ISSR3, + RFR_ISSR4, + RFR_ISSR5, + RFR_ISSR6, + RFR_ISSR7, + RFR_ISSR8, + RFR_ISSR9, + DFR_STA, + RFR_STA, + DFR_IDE, + RFR_IDE +}; + +static void Lin1CallbackHandler(uint8_t u8LinIndex, void *state) { + LIN_PORTS.lin1.LinExtCallbackHandler(LIN_PORTS.lin1.envCallExtBack, u8LinIndex, state); +} + +void FCUART4_RxTx_IRQHandler(void) { + LIN_DrvIRQHandler(LIN_PORTS.lin1.UART_INDEX); +} + +tLinData *Lin1_Init(lin_callback_ext_t Lin_ExtCallbackHandler) { + + tLinPorts *env = &LIN_PORTS; + + PORT_InitType tInitStruct = {0}; + GPIO_InitType tGpioInitStruct = {0}; + + // Port D12: MUX = ALT3, UART4_RX + tInitStruct.u32PortPins = PORT_PIN_12; + tInitStruct.uPortPinMux.u32PortPinMode = PORTD_12_FCUART4_RX; + tInitStruct.bPullEn = true; + tInitStruct.ePullSel = PORT_PULL_UP; + PORT_InitPins(PORT_D, &tInitStruct); + + tGpioInitStruct.u32GpioPins = GPIO_PIN_12; + tGpioInitStruct.ePinDirection = GPIO_IN; + GPIO_InitPins(GPIO_D, &tGpioInitStruct); + + // Port D5: MUX = ALT3, UART4_TX + tInitStruct.u32PortPins = PORT_PIN_5; + tInitStruct.uPortPinMux.u32PortPinMode = PORTD_5_FCUART4_TX; + PORT_InitPins(PORT_D, &tInitStruct); + + tGpioInitStruct.u32GpioPins = GPIO_PIN_5; + tGpioInitStruct.ePinDirection = GPIO_OUT; + tGpioInitStruct.ePinLevel = GPIO_HIGH; + GPIO_InitPins(GPIO_D, &tGpioInitStruct); + + // Port D18: MUX = GPIO output ENABLE + tInitStruct.u32PortPins = PORT_PIN_18; + tInitStruct.uPortPinMux.u32PortPinMode = PORT_GPIO_MODE; + PORT_InitPins(PORT_D, &tInitStruct); + + tGpioInitStruct.u32GpioPins = GPIO_PIN_18; + tGpioInitStruct.ePinDirection = GPIO_OUT; + tGpioInitStruct.ePinLevel = GPIO_HIGH; + GPIO_InitPins(GPIO_D, &tGpioInitStruct); + + LIN_Initial( + &env->lin1, + FCUART4, + 9600, + + 4, // UART0 = 0 ... UART7 = 7 + FCUART4_IRQn, // FCUART0_IRQn ... FCUART7_IRQn + 0xFF, + + NULL, + Lin1CallbackHandler, + Lin_ExtCallbackHandler, + &env->lin1.linData, + + classicPID, + numOfClassicPID + + ); + + env->lin1_Io = vLinGetIo(&env->lin1); + + return &env->lin1.linData; +} + +//конец--------------------------LIN 1------------------------------------------------- +//конец--------------------------LIN 1------------------------------------------------- +//конец--------------------------LIN 1------------------------------------------------- + + +//начало--------------------------LIN 2------------------------------------------------- +//начало--------------------------LIN 2------------------------------------------------- +//начало--------------------------LIN 2------------------------------------------------- +static void Lin2CallbackHandler(uint8_t u8LinIndex, void *state) { + LIN_PORTS.lin2.LinExtCallbackHandler(LIN_PORTS.lin2.envCallExtBack, u8LinIndex, state); +} + +void FCUART5_RxTx_IRQHandler(void) { + LIN_DrvIRQHandler(LIN_PORTS.lin2.UART_INDEX); +} + +tLinData *Lin2_Init(lin_callback_ext_t Lin_ExtCallbackHandler) { + + tLinPorts *env = &LIN_PORTS; + + PORT_InitType tInitStruct = {0}; + GPIO_InitType tGpioInitStruct = {0}; + + // Port C16: MUX = ALT7, UART5_RX + tInitStruct.u32PortPins = PORT_PIN_16; + tInitStruct.uPortPinMux.u32PortPinMode = PORTC_16_FCUART5_RX; + tInitStruct.bPullEn = true; + tInitStruct.ePullSel = PORT_PULL_UP; + PORT_InitPins(PORT_C, &tInitStruct); + + tGpioInitStruct.u32GpioPins = GPIO_PIN_16; + tGpioInitStruct.ePinDirection = GPIO_IN; + GPIO_InitPins(GPIO_C, &tGpioInitStruct); + + // Port C15: MUX = ALT7, UART5_TX + tInitStruct.u32PortPins = PORT_PIN_15; + tInitStruct.uPortPinMux.u32PortPinMode = PORTC_15_FCUART5_TX; + PORT_InitPins(PORT_C, &tInitStruct); + + tGpioInitStruct.u32GpioPins = GPIO_PIN_15; + tGpioInitStruct.ePinDirection = GPIO_OUT; + tGpioInitStruct.ePinLevel = GPIO_HIGH; + GPIO_InitPins(GPIO_C, &tGpioInitStruct); + + // Port D19: MUX = GPIO output ENABLE + tInitStruct.u32PortPins = PORT_PIN_19; + tInitStruct.uPortPinMux.u32PortPinMode = PORT_GPIO_MODE; + PORT_InitPins(PORT_D, &tInitStruct); + + tGpioInitStruct.u32GpioPins = GPIO_PIN_19; + tGpioInitStruct.ePinDirection = GPIO_OUT; + tGpioInitStruct.ePinLevel = GPIO_HIGH; + GPIO_InitPins(GPIO_D, &tGpioInitStruct); + + LIN_Initial( + &env->lin2, + FCUART5, + 9600, + + 5, // UART0 = 0 ... UART7 = 7 + FCUART5_IRQn, // FCUART0_IRQn ... FCUART7_IRQn + 0xFF, + + NULL, + Lin2CallbackHandler, + Lin_ExtCallbackHandler, + &env->lin2.linData, + + classicPID, + numOfClassicPID + + ); + + env->lin2_Io = vLinGetIo(&env->lin2); + + return &env->lin2.linData; +} + +//конец--------------------------LIN 2------------------------------------------------- +//конец--------------------------LIN 2------------------------------------------------- +//конец--------------------------LIN 2------------------------------------------------- + + +//начало--------------------------LIN 3------------------------------------------------- +//начало--------------------------LIN 3------------------------------------------------- +//начало--------------------------LIN 3------------------------------------------------- +static void Lin3CallbackHandler(uint8_t u8LinIndex, void *state) { + LIN_PORTS.lin3.LinExtCallbackHandler(LIN_PORTS.lin3.envCallExtBack, u8LinIndex, state); +} + +void FCUART3_RxTx_IRQHandler(void) { + LIN_DrvIRQHandler(LIN_PORTS.lin3.UART_INDEX); +} + +tLinData *Lin3_Init(lin_callback_ext_t Lin_ExtCallbackHandler) { + + tLinPorts *env = &LIN_PORTS; + + PORT_InitType tInitStruct = {0}; + GPIO_InitType tGpioInitStruct = {0}; + + // Port D9: MUX = ALT7, UART3_RX + tInitStruct.u32PortPins = PORT_PIN_9; + tInitStruct.uPortPinMux.u32PortPinMode = PORTD_9_FCUART3_RX; + tInitStruct.bPullEn = true; + tInitStruct.ePullSel = PORT_PULL_UP; + PORT_InitPins(PORT_D, &tInitStruct); + + tGpioInitStruct.u32GpioPins = GPIO_PIN_9; + tGpioInitStruct.ePinDirection = GPIO_IN; + GPIO_InitPins(GPIO_D, &tGpioInitStruct); + + // Port C1: MUX = ALT7, UART3_TX + tInitStruct.u32PortPins = PORT_PIN_1; + tInitStruct.uPortPinMux.u32PortPinMode = PORTC_1_FCUART3_TX; + PORT_InitPins(PORT_C, &tInitStruct); + + tGpioInitStruct.u32GpioPins = GPIO_PIN_1; + tGpioInitStruct.ePinDirection = GPIO_OUT; + tGpioInitStruct.ePinLevel = GPIO_HIGH; + GPIO_InitPins(GPIO_C, &tGpioInitStruct); + + // Port D20: MUX = GPIO output ENABLE + tInitStruct.u32PortPins = PORT_PIN_20; + tInitStruct.uPortPinMux.u32PortPinMode = PORT_GPIO_MODE; + PORT_InitPins(PORT_D, &tInitStruct); + + tGpioInitStruct.u32GpioPins = GPIO_PIN_20; + tGpioInitStruct.ePinDirection = GPIO_OUT; + tGpioInitStruct.ePinLevel = GPIO_HIGH; + GPIO_InitPins(GPIO_D, &tGpioInitStruct); + + LIN_Initial( + &env->lin3, + FCUART3, + 9600, + + 3, // UART0 = 0 ... UART7 = 7 + FCUART3_IRQn, // FCUART0_IRQn ... FCUART7_IRQn + 0xFF, + + NULL, + Lin3CallbackHandler, + Lin_ExtCallbackHandler, + &env->lin3.linData, + + classicPID, + numOfClassicPID + + ); + + env->lin3_Io = vLinGetIo(&env->lin3); + + return &env->lin3.linData; +} + +//конец--------------------------LIN 3------------------------------------------------- +//конец--------------------------LIN 3------------------------------------------------- +//конец--------------------------LIN 3------------------------------------------------- + +//начало--------------------------LIN 4------------------------------------------------- +//начало--------------------------LIN 4------------------------------------------------- +//начало--------------------------LIN 4------------------------------------------------- +static void Lin4CallbackHandler(uint8_t u8LinIndex, void *state) { + LIN_PORTS.lin4.LinExtCallbackHandler(LIN_PORTS.lin4.envCallExtBack, u8LinIndex, state); +} + +void FCUART2_RxTx_IRQHandler(void) { + LIN_DrvIRQHandler(LIN_PORTS.lin4.UART_INDEX); +} + +tLinData *Lin4_Init(lin_callback_ext_t Lin_ExtCallbackHandler) { + + tLinPorts *env = &LIN_PORTS; + + PORT_InitType tInitStruct = {0}; + GPIO_InitType tGpioInitStruct = {0}; + + // Port D6: MUX = ALT2, UART2_RX + tInitStruct.u32PortPins = PORT_PIN_6; + tInitStruct.uPortPinMux.u32PortPinMode = PORTD_6_FCUART2_RX; + tInitStruct.bPullEn = true; + tInitStruct.ePullSel = PORT_PULL_UP; + PORT_InitPins(PORT_D, &tInitStruct); + + tGpioInitStruct.u32GpioPins = GPIO_PIN_6; + tGpioInitStruct.ePinDirection = GPIO_IN; + GPIO_InitPins(GPIO_D, &tGpioInitStruct); + + // Port D7: MUX = ALT2, UART2_TX + tInitStruct.u32PortPins = PORT_PIN_7; + tInitStruct.uPortPinMux.u32PortPinMode = PORTD_7_FCUART2_TX; + PORT_InitPins(PORT_D, &tInitStruct); + + tGpioInitStruct.u32GpioPins = GPIO_PIN_7; + tGpioInitStruct.ePinDirection = GPIO_OUT; + tGpioInitStruct.ePinLevel = GPIO_HIGH; + GPIO_InitPins(GPIO_D, &tGpioInitStruct); + + // Port D8: MUX = GPIO output ENABLE + tInitStruct.u32PortPins = PORT_PIN_8; + tInitStruct.uPortPinMux.u32PortPinMode = PORT_GPIO_MODE; + PORT_InitPins(PORT_D, &tInitStruct); + + tGpioInitStruct.u32GpioPins = GPIO_PIN_8; + tGpioInitStruct.ePinDirection = GPIO_OUT; + tGpioInitStruct.ePinLevel = GPIO_HIGH; + GPIO_InitPins(GPIO_D, &tGpioInitStruct); + + LIN_Initial( + &env->lin4, + FCUART2, + 9600, + + 2, // UART0 = 0 ... UART7 = 7 + FCUART2_IRQn, // FCUART0_IRQn ... FCUART7_IRQn + 0xFF, + + NULL, + Lin4CallbackHandler, + Lin_ExtCallbackHandler, + &env->lin4.linData, + + NULL, + 0 + + ); + + env->lin4_Io = vLinGetIo(&env->lin4); + + return &env->lin4.linData; +} + +//конец--------------------------LIN 4------------------------------------------------- +//конец--------------------------LIN 4------------------------------------------------- +//конец--------------------------LIN 4------------------------------------------------- + +//начало--------------------------LIN 5------------------------------------------------- +//начало--------------------------LIN 5------------------------------------------------- +//начало--------------------------LIN 5------------------------------------------------- +static void Lin5CallbackHandler(uint8_t u8LinIndex, void *state) { + LIN_PORTS.lin5.LinExtCallbackHandler(LIN_PORTS.lin5.envCallExtBack, u8LinIndex, state); +} + +void FCUART0_RxTx_IRQHandler(void) { + LIN_DrvIRQHandler(LIN_PORTS.lin5.UART_INDEX); +} + +tLinData *Lin5_Init(lin_callback_ext_t Lin_ExtCallbackHandler) { + + tLinPorts *env = &LIN_PORTS; + + PORT_InitType tInitStruct = {0}; + GPIO_InitType tGpioInitStruct = {0}; + + // Port A2: MUX = ALT6, UART0_RX + tInitStruct.u32PortPins = PORT_PIN_2; + tInitStruct.uPortPinMux.u32PortPinMode = PORTA_2_FCUART0_RX; + tInitStruct.bPullEn = true; + tInitStruct.ePullSel = PORT_PULL_UP; + PORT_InitPins(PORT_A, &tInitStruct); + + tGpioInitStruct.u32GpioPins = GPIO_PIN_2; + tGpioInitStruct.ePinDirection = GPIO_IN; + GPIO_InitPins(GPIO_A, &tGpioInitStruct); + + // Port A3: MUX = ALT6, UART0_TX + tInitStruct.u32PortPins = PORT_PIN_3; + tInitStruct.uPortPinMux.u32PortPinMode = PORTA_3_FCUART0_TX; + PORT_InitPins(PORT_A, &tInitStruct); + + tGpioInitStruct.u32GpioPins = GPIO_PIN_3; + tGpioInitStruct.ePinDirection = GPIO_OUT; + tGpioInitStruct.ePinLevel = GPIO_HIGH; + GPIO_InitPins(GPIO_A, &tGpioInitStruct); +/* + // Port A6: MUX = GPIO output ENABLE Fix V2 + tInitStruct.u32PortPins = PORT_PIN_6; + tInitStruct.uPortPinMux.u32PortPinMode = PORT_GPIO_MODE; + PORT_InitPins(PORT_A, &tInitStruct); + + tGpioInitStruct.u32GpioPins = GPIO_PIN_6; + tGpioInitStruct.ePinDirection = GPIO_OUT; + tGpioInitStruct.ePinLevel = GPIO_HIGH; + GPIO_InitPins(GPIO_A, &tGpioInitStruct); +*/ + + // Port A7: MUX = GPIO output ENABLE + tInitStruct.u32PortPins = PORT_PIN_7; + tInitStruct.uPortPinMux.u32PortPinMode = PORT_GPIO_MODE; + PORT_InitPins(PORT_A, &tInitStruct); + + tGpioInitStruct.u32GpioPins = GPIO_PIN_7; + tGpioInitStruct.ePinDirection = GPIO_OUT; + tGpioInitStruct.ePinLevel = GPIO_HIGH; + GPIO_InitPins(GPIO_A, &tGpioInitStruct); + + + LIN_Initial( + &env->lin5, + FCUART0, + 9600, + + 0, // UART0 = 0 ... UART7 = 7 + FCUART0_IRQn, // FCUART0_IRQn ... FCUART7_IRQn + 0xFF, + + NULL, + Lin5CallbackHandler, + Lin_ExtCallbackHandler, + &env->lin5.linData, + + NULL, + 0 + + ); + + env->lin5_Io = vLinGetIo(&env->lin5); + + return &env->lin5.linData; +} + +//конец--------------------------LIN 5------------------------------------------------- +//конец--------------------------LIN 5------------------------------------------------- +//конец--------------------------LIN 5------------------------------------------------- + + +//начало--------------------------LIN 6------------------------------------------------- +//начало--------------------------LIN 6------------------------------------------------- +//начало--------------------------LIN 6------------------------------------------------- +static void Lin6CallbackHandler(uint8_t u8LinIndex, void *state) { + LIN_PORTS.lin6.LinExtCallbackHandler(LIN_PORTS.lin6.envCallExtBack, u8LinIndex, state); +} + +void FCUART6_RxTx_IRQHandler(void) { + LIN_DrvIRQHandler(LIN_PORTS.lin6.UART_INDEX); +} + +tLinData *Lin6_Init(lin_callback_ext_t Lin_ExtCallbackHandler) { + + tLinPorts *env = &LIN_PORTS; + + PORT_InitType tInitStruct = {0}; + GPIO_InitType tGpioInitStruct = {0}; + + // Port C10: MUX = ALT4, UART6_RX + tInitStruct.u32PortPins = PORT_PIN_10; + tInitStruct.uPortPinMux.u32PortPinMode = PORTC_10_FCUART6_RX; + tInitStruct.bPullEn = true; + tInitStruct.ePullSel = PORT_PULL_UP; + PORT_InitPins(PORT_C, &tInitStruct); + + tGpioInitStruct.u32GpioPins = GPIO_PIN_10; + tGpioInitStruct.ePinDirection = GPIO_IN; + GPIO_InitPins(GPIO_C, &tGpioInitStruct); + + // Port C11: MUX = ALT4, UART6_TX + tInitStruct.u32PortPins = PORT_PIN_11; + tInitStruct.uPortPinMux.u32PortPinMode = PORTC_11_FCUART6_TX; + PORT_InitPins(PORT_C, &tInitStruct); + + tGpioInitStruct.u32GpioPins = GPIO_PIN_11; + tGpioInitStruct.ePinDirection = GPIO_OUT; + tGpioInitStruct.ePinLevel = GPIO_HIGH; + GPIO_InitPins(GPIO_C, &tGpioInitStruct); + + // Port C9: MUX = GPIO output ENABLE + tInitStruct.u32PortPins = PORT_PIN_9; + tInitStruct.uPortPinMux.u32PortPinMode = PORT_GPIO_MODE; + PORT_InitPins(PORT_C, &tInitStruct); + + tGpioInitStruct.u32GpioPins = GPIO_PIN_9; + tGpioInitStruct.ePinDirection = GPIO_OUT; + tGpioInitStruct.ePinLevel = GPIO_HIGH; + GPIO_InitPins(GPIO_C, &tGpioInitStruct); + + + LIN_Initial( + &env->lin6, + FCUART6, + 9600, + + 0, // UART0 = 0 ... UART7 = 7 + FCUART6_IRQn, // FCUART0_IRQn ... FCUART7_IRQn + 0xFF, + + NULL, + Lin6CallbackHandler, + Lin_ExtCallbackHandler, + &env->lin6.linData, + + NULL, + 0 + + ); + + env->lin6_Io = vLinGetIo(&env->lin6); + + return &env->lin6.linData; +} + +//конец--------------------------LIN 6------------------------------------------------- +//конец--------------------------LIN 6------------------------------------------------- +//конец--------------------------LIN 6--------------------------------------------- \ No newline at end of file diff --git a/MODULES/HVAC_M7_Lins/Lins.h b/MODULES/HVAC_M7_Lins/Lins.h new file mode 100644 index 0000000..bf11f87 --- /dev/null +++ b/MODULES/HVAC_M7_Lins/Lins.h @@ -0,0 +1,61 @@ +// +// Created by CFIF on 14.12.23. +// + +#ifndef FLAG_LINS_H +#define FLAG_LINS_H + +#include "LinFlagchip.h" + +#define CFR_INI 0x2C +#define CFR_SET 0x2F +#define CFR_MOD 0x2E +#define CFR_ADR 0x17 +#define CFR_PRG 0x28 +#define DFR_PRG 0x18 +#define RFR_PRG 0x20 +#define RFR_ISSR1 0x01 +#define RFR_ISSR2 0x02 +#define RFR_ISSR3 0x03 +#define RFR_ISSR4 0x04 +#define RFR_ISSR5 0x05 +#define RFR_ISSR6 0x06 +#define RFR_ISSR7 0x07 +#define RFR_ISSR8 0x08 +#define RFR_ISSR9 0x09 +#define DFR_STA 0x1B +#define RFR_STA 0x23 +#define DFR_IDE 0x1A +#define RFR_IDE 0x22 + +typedef struct { + tLinFlagchip lin1; + tLinIO lin1_Io; + + tLinFlagchip lin2; + tLinIO lin2_Io; + + tLinFlagchip lin3; + tLinIO lin3_Io; + + tLinFlagchip lin4; + tLinIO lin4_Io; + + tLinFlagchip lin5; + tLinIO lin5_Io; + + tLinFlagchip lin6; + tLinIO lin6_Io; + +} tLinPorts; + +extern tLinPorts LIN_PORTS; + +tLinData *Lin1_Init(lin_callback_ext_t Lin_ExtCallbackHandler); +tLinData *Lin2_Init(lin_callback_ext_t Lin_ExtCallbackHandler); +tLinData *Lin3_Init(lin_callback_ext_t Lin_ExtCallbackHandler); +tLinData *Lin4_Init(lin_callback_ext_t Lin_ExtCallbackHandler); +tLinData *Lin5_Init(lin_callback_ext_t Lin_ExtCallbackHandler); +tLinData *Lin6_Init(lin_callback_ext_t Lin_ExtCallbackHandler); + +#endif //FLAG_LINS_H diff --git a/MODULES/HVAC_M7_Lins/modular.json b/MODULES/HVAC_M7_Lins/modular.json new file mode 100644 index 0000000..9589ff8 --- /dev/null +++ b/MODULES/HVAC_M7_Lins/modular.json @@ -0,0 +1,13 @@ +{ + "dep": [ + + ], + "cmake": { + "inc_dirs": [ + "./" + ], + "srcs": [ + "./**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_MODEL/HVAC_model.c b/MODULES/HVAC_M7_MODEL/HVAC_model.c new file mode 100644 index 0000000..0f7227b --- /dev/null +++ b/MODULES/HVAC_M7_MODEL/HVAC_model.c @@ -0,0 +1,46211 @@ +/* + * File: HVAC_model.c + * + * Code generated for Simulink model 'HVAC_model'. + * + * Model version : 1.1466 + * Simulink Coder version : 24.1 (R2024a) 19-Nov-2023 + * C/C++ source code generated on : Fri Jul 31 15:00:33 2026 + * + * Target selection: ert.tlc + * Embedded hardware selection: ARM Compatible->ARM Cortex-M + * Emulation hardware selection: + * Differs from embedded hardware (MATLAB Host) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#include "HVAC_model.h" +#include +#include +#include "HVAC_model_private.h" +#include +#include +#include "HVAC_model_types.h" +#include "Rs_Cal_Base.h" + +/* Named constants for Chart: '/Zone_Climate_Logic_Auto_FL2' */ +#define IN_AC_Off ((uint8_t)1U) +#define IN_AC_On ((uint8_t)2U) +#define IN_AUTO_MODE ((uint8_t)1U) +#define IN_Def_Off ((uint8_t)1U) +#define IN_Def_On ((uint8_t)2U) +#define IN_Face_Off ((uint8_t)1U) +#define IN_Face_On ((uint8_t)2U) +#define IN_Foot_Off ((uint8_t)1U) +#define IN_Foot_On ((uint8_t)2U) +#define IN_MANUAL_MODE ((uint8_t)2U) +#define IN_NO_ACTIVE_CHILD ((uint8_t)0U) + +/* Named constants for Chart: '/13,1,3,15 Valve control' */ +#define IN_Entry_2W ((uint8_t)1U) +#define IN_Entry_3W ((uint8_t)1U) +#define IN_NO_ACTIVE_CHILD_c ((uint8_t)0U) +#define IN_Wait_2W ((uint8_t)2U) +#define IN_Wait_3W ((uint8_t)2U) + +/* Named constants for Chart: '/Partial REC' */ +#define IN_COND_1 ((uint8_t)1U) +#define IN_COND_2 ((uint8_t)2U) +#define IN_COND_3 ((uint8_t)3U) +#define IN_HOLDING ((uint8_t)1U) +#define IN_PARTIAL_REC_OFF ((uint8_t)1U) +#define IN_PARTIAL_REC_ON ((uint8_t)2U) +#define IN_TRACKING ((uint8_t)2U) + +/* Named constants for Chart: '/Spd_OSA_Trigger' */ +#define IN_OSA_OFF ((uint8_t)1U) +#define IN_OSA_ON ((uint8_t)2U) + +/* Named constants for Chart: '/A//C Control' */ +#define IN_COMP_OFF ((uint8_t)1U) +#define IN_COMP_ON ((uint8_t)2U) +#define IN_Chiller_OFF ((uint8_t)1U) +#define IN_Chiller_ON ((uint8_t)2U) +#define IN_FAULT_HIGH_PRESS ((uint8_t)1U) +#define IN_FAULT_LOW_PRESS ((uint8_t)2U) +#define IN_Front_A_C_OFF ((uint8_t)1U) +#define IN_Front_A_C_ON ((uint8_t)2U) +#define IN_PRESSURE_OK ((uint8_t)3U) +#define IN_PROT_LEVEL_0 ((uint8_t)1U) +#define IN_PROT_LEVEL_1 ((uint8_t)2U) +#define IN_PROT_LEVEL_2 ((uint8_t)3U) +#define IN_Rear_A_C_OFF ((uint8_t)1U) +#define IN_Rear_A_C_ON ((uint8_t)2U) + +/* Named constants for Chart: '/Zone_Climate_Logic_Auto_FL1' */ +#define IN_AC_Off_m ((uint8_t)1U) +#define IN_AC_On_d ((uint8_t)2U) +#define IN_AUTO_MODE_p ((uint8_t)1U) +#define IN_Def_Off_p ((uint8_t)1U) +#define IN_Def_On_c ((uint8_t)2U) +#define IN_Face_Off_i ((uint8_t)1U) +#define IN_Face_On_k ((uint8_t)2U) +#define IN_Foot_Off_n ((uint8_t)1U) +#define IN_Foot_On_m ((uint8_t)2U) +#define IN_MANUAL_MODE_k ((uint8_t)2U) + +/* Named constants for Chart: '/AC_Max_Active' */ +#define IN_AC_MAX_OFF ((uint8_t)1U) +#define IN_AC_MAX_ON ((uint8_t)2U) + +/* Named constants for Chart: '/Defrost_Active' */ +#define IN_REC_OFF ((uint8_t)1U) +#define IN_REC_ON ((uint8_t)2U) + +/* Named constants for Chart: '/Chart' */ +#define IN_MAX_AC_OFF ((uint8_t)1U) +#define IN_MAX_AC_ON ((uint8_t)2U) + +/* Named constants for Chart: '/Synchronization stateflow chart' */ +#define IN_FRONT_ONLY ((uint8_t)1U) +#define IN_FULL_SYNC ((uint8_t)2U) +#define IN_NO_SYNC ((uint8_t)3U) +#define IN_REAR_ONLY ((uint8_t)4U) +#define IN_SEPARATE_FRONT_AND_REAR ((uint8_t)5U) + +const CmdBusPWMGet HVAC_model_rtZCmdBusPWMGet = { + 0U, /* pwmPercentFront */ + 0U, /* pwmPercentRear */ + 0U, /* pwmPercentFrontReserved */ + 0U /* pwmPercentRearReserved */ +}; /* CmdBusPWMGet ground */ + +const CmdBusStatus HVAC_model_rtZCmdBusStatus = { + 0, /* Battery */ + 0, /* AMB */ + 0, /* Incar_FL */ + 0, /* Incar_FR */ + 0, /* Incar_RL */ + 0, /* Incar_RR */ + 0, /* Eva_F */ + 0, /* Eva_R */ + 0, /* Pressure */ + 0, /* Duct_FL_Upper */ + 0, /* Duct_FL_Lower */ + 0, /* Duct_FR_Upper */ + 0, /* Duct_FR_Lower */ + 0, /* Duct_RL */ + 0, /* Duct_RR */ + 0, /* Duct_Side_FL */ + 0, /* Duct_Side_FR */ + 0, /* Duct_Side_RL */ + 0, /* Duct_Side_RR */ + 0 /* AQS */ +}; /* CmdBusStatus ground */ + +const ActuatorCmdBus HVAC_model_rtZActuatorCmdBus = { + { + 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U } + , /* POS */ + + { + 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U } + , /* BUS_ADR */ + + { + 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U } + , /* MODE */ + + { + 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U } + , /* COM */ + + { + 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U } + , /* Stall_SET */ + + { + 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U } + , /* Lnoise_SET */ + + { + 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U } + , /* Autos_SET */ + + { + 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U } + , /* Speed_SET */ + + { + 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U } + /* Coils_Stop_SET */ +}; /* ActuatorCmdBus ground */ + +const CmdBusError HVAC_model_rtZCmdBusError = { + 0U, /* CCU_IncarTempErrF_Stat */ + 0U, /* CCU_IncarTempErrR_Stat */ + 0U, /* CCU_DuctTempSenErrF_Stat */ + 0U, /* CCU_DuctTempSenErrR_Stat */ + 0U, /* CCU_EvaTempSenErrF_Stat */ + 0U, /* CCU_EvaTempSenErrR_Stat */ + 0U, /* CCU_DeflectorSwErrF_Stat */ + 0U, /* CCU_DeflectorSwErrR_Stat */ + 0U, /* CCU_PressSenErr_Stat */ + 0U, /* CCU_AmbienTemptSenErr_Stat */ + 0U, /* CCU_SealingValveErr_Stat */ + 0U, /* CCU_ETXVerr_Stat */ + 0U, /* CCU_HVACfanOrTXVerrF_Stat */ + 0U, /* CCU_HVACfanOrTXVerrR_Stat */ + 0U, /* CCU_ActuatorErrF_Stat */ + 0U, /* CCU_ActuatorErrR_Stat */ + 0U, /* CCU_UltravioletErr_Stat */ + 0U, /* CCU_VinRecordErr_Stat */ + 0U, /* CCU_AirQualSenErr_Stat */ + 0U, /* CCU_CommErr_Stat */ + 0U, /* CCU_TWVerr_Stat */ + 0U, /* CCU_IonizationErr_Stat */ + 0U /* CCU_AromaErr_Stat */ +}; /* CmdBusError ground */ + +const ActuatorCmdBusInput HVAC_model_rtZActuatorCmdBusInput = { + { + 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U } + , /* in_CPOS_ALL */ + + { + 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U } + , /* in_Act_Emrf_Slave */ + + { + 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U } + , /* in_Mode_Slave */ + + { + 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U } + , /* in_Act_Err1_Supply */ + + { + 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U } + , /* in_Act_Err2_Communication */ + + { + 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U } + , /* in_Act_Err3_Temperature */ + + { + 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U } + , /* in_Act_Err4_Permanent_Electrical */ + + { + 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U } + , /* in_Act_Stall_Slave */ + + { + 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U } + , /* in_Act_Reset */ + 0U, /* Busy */ + 0U /* Error_Connect */ +}; /* ActuatorCmdBusInput ground */ + +/* Exported block states */ +ActuatorCmdBus Actuator_Ch0_Command_Model;/* '/Data Store Memory272' */ +ActuatorCmdBus Actuator_Ch1_Command_Model;/* '/Data Store Memory273' */ +ActuatorCmdBus Actuator_Ch2_Command_Model;/* '/Data Store Memory274' */ +ActuatorCmdBusInput Actuator_Ch0_Status_Model;/* '/Data Store Memory61' */ +ActuatorCmdBusInput Actuator_Ch1_Status_Model;/* '/Data Store Memory62' */ +ActuatorCmdBusInput Actuator_Ch2_Status_Model;/* '/Data Store Memory63' */ +CmdBusStatus Status_Sensor_Model; /* '/Data Store Memory197' */ +CmdBusError CCU_Errors_Model; /* '/Data Store Memory3' */ +CmdBusPWMGet PWM_Get; /* '/Data Store Memory128' */ + +/* Block signals (default storage) */ +B rtB; + +/* Block states (default storage) */ +DW rtDW; + +/* External outputs (root outports fed by signals with default storage) */ +ExtY rtY; + +/* Real-time model */ +static RT_MODEL rtM_; +RT_MODEL *const rtM = &rtM_; + +/* Forward declaration for local functions */ +static void E_COMP_MANAGER(bool *Enable_Comp_PID, const int16_t *Eva_F_tg, const + int16_t *Eva_R_tg); +static void enter_atomic_REAR_ONLY(void); +static void enter_atomic_FRONT_ONLY(void); +static void enter_atomic_FULL_SYNC(void); +static void enter_atomic_SEPARATE_FRONT_AND_REAR(void); +static void enter_atomic_NO_SYNC(void); +static double find_index(int16_t delta); +int8_t look1_iu8lu64n56ts8Ds16_binlcs(uint8_t u0, const uint8_t bp0[], const + int8_t table[], uint32_t maxIndex) +{ + uint64_t frac; + uint32_t iLeft; + int8_t yL_0d0; + + /* Column-major Lookup 1-D + Search method: 'binary' + Use previous index: 'off' + Interpolation method: 'Linear point-slope' + Extrapolation method: 'Clip' + Use last breakpoint for index at or above upper limit: 'off' + Remove protection against out-of-range input in generated code: 'off' + Rounding mode: 'simplest' + */ + /* Prelookup - Index and Fraction + Index Search method: 'binary' + Extrapolation method: 'Clip' + Use previous index: 'off' + Use last breakpoint for index at or above upper limit: 'off' + Remove protection against out-of-range input in generated code: 'off' + Rounding mode: 'simplest' + */ + if (u0 <= bp0[0U]) { + iLeft = 0U; + frac = 0ULL; + } else if (u0 < bp0[maxIndex]) { + uint32_t bpIdx; + uint32_t iRght; + + /* Binary Search */ + bpIdx = maxIndex >> 1U; + iLeft = 0U; + iRght = maxIndex; + while (iRght - iLeft > 1U) { + if (u0 < bp0[bpIdx]) { + iRght = bpIdx; + } else { + iLeft = bpIdx; + } + + bpIdx = (iRght + iLeft) >> 1U; + } + + uint8_t bpLeftVar; + bpLeftVar = bp0[iLeft]; + frac = ((uint64_t)((uint32_t)u0 - bpLeftVar) << 56) / ((uint32_t)bp0[iLeft + + 1U] - bpLeftVar); + } else { + iLeft = maxIndex - 1U; + frac = 72057594037927936ULL; + } + + /* Column-major Interpolation 1-D + Interpolation method: 'Linear point-slope' + Use last breakpoint for index at or above upper limit: 'off' + Rounding mode: 'simplest' + Overflow mode: 'wrapping' + */ + yL_0d0 = table[iLeft]; + return (int8_t)((int8_t)(((int16_t)(table[iLeft + 1U] - yL_0d0) * (int64_t) + frac) >> 56) + yL_0d0); +} + +int16_t look1_iu8lu64n48ts16Ds32_binlcs(uint8_t u0, const uint8_t bp0[], const + int16_t table[], uint32_t maxIndex) +{ + uint64_t frac; + uint32_t iLeft; + int16_t yL_0d0; + + /* Column-major Lookup 1-D + Search method: 'binary' + Use previous index: 'off' + Interpolation method: 'Linear point-slope' + Extrapolation method: 'Clip' + Use last breakpoint for index at or above upper limit: 'off' + Remove protection against out-of-range input in generated code: 'off' + Rounding mode: 'simplest' + */ + /* Prelookup - Index and Fraction + Index Search method: 'binary' + Extrapolation method: 'Clip' + Use previous index: 'off' + Use last breakpoint for index at or above upper limit: 'off' + Remove protection against out-of-range input in generated code: 'off' + Rounding mode: 'simplest' + */ + if (u0 <= bp0[0U]) { + iLeft = 0U; + frac = 0ULL; + } else if (u0 < bp0[maxIndex]) { + uint32_t bpIdx; + uint32_t iRght; + + /* Binary Search */ + bpIdx = maxIndex >> 1U; + iLeft = 0U; + iRght = maxIndex; + while (iRght - iLeft > 1U) { + if (u0 < bp0[bpIdx]) { + iRght = bpIdx; + } else { + iLeft = bpIdx; + } + + bpIdx = (iRght + iLeft) >> 1U; + } + + uint8_t bpLeftVar; + bpLeftVar = bp0[iLeft]; + frac = ((uint64_t)((uint32_t)u0 - bpLeftVar) << 48) / ((uint32_t)bp0[iLeft + + 1U] - bpLeftVar); + } else { + iLeft = maxIndex - 1U; + frac = 281474976710656ULL; + } + + /* Column-major Interpolation 1-D + Interpolation method: 'Linear point-slope' + Use last breakpoint for index at or above upper limit: 'off' + Rounding mode: 'simplest' + Overflow mode: 'wrapping' + */ + yL_0d0 = table[iLeft]; + return (int16_t)((int16_t)(((table[iLeft + 1U] - yL_0d0) * (int64_t)frac) >> + 48) + yL_0d0); +} + +int16_t look1_is16lu64n32tu16Ds32Is16_binlcs(int16_t u0, const int16_t bp0[], + const uint16_t table[], uint32_t maxIndex) +{ + uint64_t frac; + uint32_t iLeft; + uint16_t yL_0d0; + + /* Column-major Lookup 1-D + Search method: 'binary' + Use previous index: 'off' + Interpolation method: 'Linear point-slope' + Extrapolation method: 'Clip' + Use last breakpoint for index at or above upper limit: 'off' + Remove protection against out-of-range input in generated code: 'off' + Rounding mode: 'simplest' + */ + /* Prelookup - Index and Fraction + Index Search method: 'binary' + Extrapolation method: 'Clip' + Use previous index: 'off' + Use last breakpoint for index at or above upper limit: 'off' + Remove protection against out-of-range input in generated code: 'off' + Rounding mode: 'simplest' + */ + if (u0 <= bp0[0U]) { + iLeft = 0U; + frac = 0ULL; + } else if (u0 < bp0[maxIndex]) { + uint32_t bpIdx; + uint32_t iRght; + + /* Binary Search */ + bpIdx = maxIndex >> 1U; + iLeft = 0U; + iRght = maxIndex; + while (iRght - iLeft > 1U) { + if (u0 < bp0[bpIdx]) { + iRght = bpIdx; + } else { + iLeft = bpIdx; + } + + bpIdx = (iRght + iLeft) >> 1U; + } + + int16_t bpLeftVar; + bpLeftVar = bp0[iLeft]; + frac = ((uint64_t)(uint32_t)(u0 - bpLeftVar) << 32) / (uint32_t)(bp0[iLeft + + 1U] - bpLeftVar); + } else { + iLeft = maxIndex - 1U; + frac = 4294967296ULL; + } + + /* Column-major Interpolation 1-D + Interpolation method: 'Linear point-slope' + Use last breakpoint for index at or above upper limit: 'off' + Rounding mode: 'simplest' + Overflow mode: 'wrapping' + */ + yL_0d0 = table[iLeft]; + return (int16_t)((int16_t)(((table[iLeft + 1U] - yL_0d0) * (int64_t)frac) >> + 32) + (int16_t)yL_0d0); +} + +uint32_t binsearch_u32s16(int16_t u_5, const int16_t bp[], uint32_t startIndex, + uint32_t maxIndex) +{ + uint32_t bpIdx; + uint32_t bpIndex; + uint32_t iRght; + + /* Binary Search */ + bpIdx = startIndex; + bpIndex = 0U; + iRght = maxIndex; + while (iRght - bpIndex > 1U) { + if (u_5 < bp[bpIdx]) { + iRght = bpIdx; + } else { + bpIndex = bpIdx; + } + + bpIdx = (iRght + bpIndex) >> 1U; + } + + return bpIndex; +} + +int16_t look1_is16lu64n32Ds32_binlcs(int16_t u0, const int16_t bp0[], const + int16_t table[], uint32_t maxIndex) +{ + uint64_t frac; + uint32_t iLeft; + int16_t bpLeftVar; + + /* Column-major Lookup 1-D + Search method: 'binary' + Use previous index: 'off' + Interpolation method: 'Linear point-slope' + Extrapolation method: 'Clip' + Use last breakpoint for index at or above upper limit: 'off' + Remove protection against out-of-range input in generated code: 'off' + Rounding mode: 'simplest' + */ + /* Prelookup - Index and Fraction + Index Search method: 'binary' + Extrapolation method: 'Clip' + Use previous index: 'off' + Use last breakpoint for index at or above upper limit: 'off' + Remove protection against out-of-range input in generated code: 'off' + Rounding mode: 'simplest' + */ + if (u0 <= bp0[0U]) { + iLeft = 0U; + frac = 0ULL; + } else if (u0 < bp0[maxIndex]) { + uint32_t bpIdx; + uint32_t iRght; + + /* Binary Search */ + bpIdx = maxIndex >> 1U; + iLeft = 0U; + iRght = maxIndex; + while (iRght - iLeft > 1U) { + if (u0 < bp0[bpIdx]) { + iRght = bpIdx; + } else { + iLeft = bpIdx; + } + + bpIdx = (iRght + iLeft) >> 1U; + } + + bpLeftVar = bp0[iLeft]; + frac = ((uint64_t)(uint32_t)(u0 - bpLeftVar) << 32) / (uint32_t)(bp0[iLeft + + 1U] - bpLeftVar); + } else { + iLeft = maxIndex - 1U; + frac = 4294967296ULL; + } + + /* Column-major Interpolation 1-D + Interpolation method: 'Linear point-slope' + Use last breakpoint for index at or above upper limit: 'off' + Rounding mode: 'simplest' + Overflow mode: 'wrapping' + */ + bpLeftVar = table[iLeft]; + return (int16_t)((int16_t)(((table[iLeft + 1U] - bpLeftVar) * (int64_t)frac) >> + 32) + bpLeftVar); +} + +int16_t look1_is16lu64n32tu8Ds16Is16_binlcs(int16_t u0, const int16_t bp0[], + const uint8_t table[], uint32_t maxIndex) +{ + uint64_t frac; + uint32_t iLeft; + uint8_t yL_0d0; + + /* Column-major Lookup 1-D + Search method: 'binary' + Use previous index: 'off' + Interpolation method: 'Linear point-slope' + Extrapolation method: 'Clip' + Use last breakpoint for index at or above upper limit: 'off' + Remove protection against out-of-range input in generated code: 'off' + Rounding mode: 'simplest' + */ + /* Prelookup - Index and Fraction + Index Search method: 'binary' + Extrapolation method: 'Clip' + Use previous index: 'off' + Use last breakpoint for index at or above upper limit: 'off' + Remove protection against out-of-range input in generated code: 'off' + Rounding mode: 'simplest' + */ + if (u0 <= bp0[0U]) { + iLeft = 0U; + frac = 0ULL; + } else if (u0 < bp0[maxIndex]) { + uint32_t bpIdx; + uint32_t iRght; + + /* Binary Search */ + bpIdx = maxIndex >> 1U; + iLeft = 0U; + iRght = maxIndex; + while (iRght - iLeft > 1U) { + if (u0 < bp0[bpIdx]) { + iRght = bpIdx; + } else { + iLeft = bpIdx; + } + + bpIdx = (iRght + iLeft) >> 1U; + } + + int16_t bpLeftVar; + bpLeftVar = bp0[iLeft]; + frac = ((uint64_t)(uint32_t)(u0 - bpLeftVar) << 32) / (uint32_t)(bp0[iLeft + + 1U] - bpLeftVar); + } else { + iLeft = maxIndex - 1U; + frac = 4294967296ULL; + } + + /* Column-major Interpolation 1-D + Interpolation method: 'Linear point-slope' + Use last breakpoint for index at or above upper limit: 'off' + Rounding mode: 'simplest' + Overflow mode: 'wrapping' + */ + yL_0d0 = table[iLeft]; + return (int16_t)((int16_t)(((int16_t)(table[iLeft + 1U] - yL_0d0) * (int64_t) + frac) >> 32) + yL_0d0); +} + +int16_t look1_is16lu64n32Ds32_binlcn(int16_t u0, const int16_t bp0[], const + int16_t table[], uint32_t maxIndex) +{ + uint64_t frac; + uint32_t iLeft; + int16_t bpLeftVar; + + /* Column-major Lookup 1-D + Search method: 'binary' + Use previous index: 'off' + Interpolation method: 'Linear point-slope' + Extrapolation method: 'Clip' + Use last breakpoint for index at or above upper limit: 'off' + Remove protection against out-of-range input in generated code: 'off' + Rounding mode: 'nearest' + */ + /* Prelookup - Index and Fraction + Index Search method: 'binary' + Extrapolation method: 'Clip' + Use previous index: 'off' + Use last breakpoint for index at or above upper limit: 'off' + Remove protection against out-of-range input in generated code: 'off' + Rounding mode: 'nearest' + */ + if (u0 <= bp0[0U]) { + iLeft = 0U; + frac = 0ULL; + } else if (u0 < bp0[maxIndex]) { + uint32_t bpIdx; + uint32_t iRght; + + /* Binary Search */ + bpIdx = maxIndex >> 1U; + iLeft = 0U; + iRght = maxIndex; + while (iRght - iLeft > 1U) { + if (u0 < bp0[bpIdx]) { + iRght = bpIdx; + } else { + iLeft = bpIdx; + } + + bpIdx = (iRght + iLeft) >> 1U; + } + + bpLeftVar = bp0[iLeft]; + bpIdx = (uint32_t)(bp0[iLeft + 1U] - bpLeftVar); + frac = (((uint64_t)(uint32_t)(u0 - bpLeftVar) << 32) + ((uint64_t)bpIdx >> 1)) + / bpIdx; + } else { + iLeft = maxIndex - 1U; + frac = 4294967296ULL; + } + + /* Column-major Interpolation 1-D + Interpolation method: 'Linear point-slope' + Use last breakpoint for index at or above upper limit: 'off' + Rounding mode: 'nearest' + Overflow mode: 'wrapping' + */ + bpLeftVar = table[iLeft]; + return (int16_t)((int16_t)(((table[iLeft + 1U] - bpLeftVar) * (int64_t)frac + + 2147483648LL) >> 32) + bpLeftVar); +} + +int16_t look1_bs16ts16Dd_binlc(double u0, const int16_t bp0[], const int16_t + table[], uint32_t maxIndex) +{ + double frac; + double v; + uint32_t iLeft; + int16_t uCast; + + /* Column-major Lookup 1-D + Search method: 'binary' + Use previous index: 'off' + Interpolation method: 'Linear point-slope' + Extrapolation method: 'Clip' + Use last breakpoint for index at or above upper limit: 'off' + Remove protection against out-of-range input in generated code: 'off' + */ + /* Prelookup - Index and Fraction + Index Search method: 'binary' + Extrapolation method: 'Clip' + Use previous index: 'off' + Use last breakpoint for index at or above upper limit: 'off' + Remove protection against out-of-range input in generated code: 'off' + */ + frac = floor(u0); + if (frac < 32768.0) { + if (frac >= -32768.0) { + uCast = (int16_t)frac; + } else { + uCast = INT16_MIN; + } + } else { + uCast = INT16_MAX; + } + + if (u0 < bp0[0U]) { + iLeft = 0U; + frac = 0.0; + } else if (u0 < bp0[maxIndex]) { + uint32_t bpIdx; + uint32_t iRght; + + /* Binary Search */ + bpIdx = maxIndex >> 1U; + iLeft = 0U; + iRght = maxIndex; + while (iRght - iLeft > 1U) { + if (uCast < bp0[bpIdx]) { + iRght = bpIdx; + } else { + iLeft = bpIdx; + } + + bpIdx = (iRght + iLeft) >> 1U; + } + + frac = (u0 - (double)bp0[iLeft]) / (double)(uint32_t)(bp0[iLeft + 1U] - + bp0[iLeft]); + } else { + iLeft = maxIndex - 1U; + frac = 1.0; + } + + /* Column-major Interpolation 1-D + Interpolation method: 'Linear point-slope' + Use last breakpoint for index at or above upper limit: 'off' + Overflow mode: 'wrapping' + */ + uCast = table[iLeft]; + frac *= (double)table[iLeft + 1U] - (double)uCast; + v = fabs(frac); + if (v < 4.503599627370496E+15) { + if (v >= 0.5) { + frac = floor(frac + 0.5); + } else { + frac = 0.0; + } + } + + return (int16_t)(uCast + (int16_t)frac); +} + +uint8_t look2_iu8bu8s16lu64n32_binlcse(uint8_t u0, uint8_t u1, const uint8_t + bp0[], const int16_t bp1[], const uint8_t table[], const uint32_t maxIndex[], + uint32_t stride) +{ + uint64_t fractions[2]; + uint64_t frac; + uint32_t bpIndices[2]; + uint32_t bpIdx; + uint32_t iLeft; + uint32_t iRght; + uint8_t bpLeftVar; + uint8_t y; + uint8_t yL_0d0; + uint8_t yL_1d; + + /* Column-major Lookup 2-D + Search method: 'binary' + Use previous index: 'off' + Interpolation method: 'Linear point-slope' + Extrapolation method: 'Clip' + Use last breakpoint for index at or above upper limit: 'off' + Remove protection against out-of-range input in generated code: 'off' + Rounding mode: 'simplest' + */ + /* Prelookup - Index and Fraction + Index Search method: 'binary' + Extrapolation method: 'Clip' + Use previous index: 'off' + Use last breakpoint for index at or above upper limit: 'off' + Remove protection against out-of-range input in generated code: 'off' + Rounding mode: 'simplest' + */ + if (u0 <= bp0[0U]) { + iLeft = 0U; + frac = 0ULL; + } else if (u0 < bp0[maxIndex[0U]]) { + /* Binary Search */ + bpIdx = maxIndex[0U] >> 1U; + iLeft = 0U; + iRght = maxIndex[0U]; + while (iRght - iLeft > 1U) { + if (u0 < bp0[bpIdx]) { + iRght = bpIdx; + } else { + iLeft = bpIdx; + } + + bpIdx = (iRght + iLeft) >> 1U; + } + + bpLeftVar = bp0[iLeft]; + frac = ((uint64_t)((uint32_t)u0 - bpLeftVar) << 32) / ((uint32_t)bp0[iLeft + + 1U] - bpLeftVar); + } else { + iLeft = maxIndex[0U] - 1U; + frac = 4294967296ULL; + } + + fractions[0U] = frac; + bpIndices[0U] = iLeft; + + /* Prelookup - Index and Fraction + Index Search method: 'binary' + Extrapolation method: 'Clip' + Use previous index: 'off' + Use last breakpoint for index at or above upper limit: 'off' + Remove protection against out-of-range input in generated code: 'off' + Rounding mode: 'simplest' + */ + if (u1 < bp1[0U]) { + iLeft = 0U; + frac = 0ULL; + } else if (u1 < bp1[maxIndex[1U]]) { + /* Binary Search */ + bpIdx = maxIndex[1U] >> 1U; + iLeft = 0U; + iRght = maxIndex[1U]; + while (iRght - iLeft > 1U) { + if (u1 < bp1[bpIdx]) { + iRght = bpIdx; + } else { + iLeft = bpIdx; + } + + bpIdx = (iRght + iLeft) >> 1U; + } + + frac = ((uint64_t)(u1 - (uint32_t)bp1[iLeft]) << 32) / (uint32_t)(bp1[iLeft + + 1U] - bp1[iLeft]); + } else { + iLeft = maxIndex[1U] - 1U; + frac = 4294967296ULL; + } + + /* Column-major Interpolation 2-D + Interpolation method: 'Linear point-slope' + Use last breakpoint for index at or above upper limit: 'off' + Rounding mode: 'simplest' + Overflow mode: 'wrapping' + */ + bpIdx = iLeft * stride + bpIndices[0U]; + bpLeftVar = table[bpIdx + 1U]; + yL_0d0 = table[bpIdx]; + if (bpLeftVar >= yL_0d0) { + yL_1d = (uint8_t)((uint32_t)(uint8_t)(((uint8_t)((uint32_t)bpLeftVar - + yL_0d0) * fractions[0U]) >> 32) + yL_0d0); + } else { + yL_1d = (uint8_t)((uint32_t)yL_0d0 - (uint8_t)(((uint8_t)((uint32_t)yL_0d0 - + bpLeftVar) * fractions[0U]) >> 32)); + } + + bpIdx += stride; + bpLeftVar = table[bpIdx + 1U]; + yL_0d0 = table[bpIdx]; + if (bpLeftVar >= yL_0d0) { + bpLeftVar = (uint8_t)((uint32_t)(uint8_t)(((uint8_t)((uint32_t)bpLeftVar - + yL_0d0) * fractions[0U]) >> 32) + yL_0d0); + } else { + bpLeftVar = (uint8_t)((uint32_t)yL_0d0 - (uint8_t)(((uint8_t)((uint32_t) + yL_0d0 - bpLeftVar) * fractions[0U]) >> 32)); + } + + if (bpLeftVar >= yL_1d) { + y = (uint8_t)((uint32_t)(uint8_t)(((uint8_t)((uint32_t)bpLeftVar - yL_1d) * + frac) >> 32) + yL_1d); + } else { + y = (uint8_t)((uint32_t)yL_1d - (uint8_t)(((uint8_t)((uint32_t)yL_1d - + bpLeftVar) * frac) >> 32)); + } + + return y; +} + +uint8_t look1_iu16lu64n48tu8_binlcse(uint16_t u0, const uint16_t bp0[], const + uint8_t table[], uint32_t maxIndex) +{ + uint64_t frac; + uint32_t iLeft; + uint8_t y; + uint8_t yL_0d0; + uint8_t yR_0d0; + + /* Column-major Lookup 1-D + Search method: 'binary' + Use previous index: 'off' + Interpolation method: 'Linear point-slope' + Extrapolation method: 'Clip' + Use last breakpoint for index at or above upper limit: 'off' + Remove protection against out-of-range input in generated code: 'off' + Rounding mode: 'simplest' + */ + /* Prelookup - Index and Fraction + Index Search method: 'binary' + Extrapolation method: 'Clip' + Use previous index: 'off' + Use last breakpoint for index at or above upper limit: 'off' + Remove protection against out-of-range input in generated code: 'off' + Rounding mode: 'simplest' + */ + if (u0 <= bp0[0U]) { + iLeft = 0U; + frac = 0ULL; + } else if (u0 < bp0[maxIndex]) { + uint32_t bpIdx; + uint32_t iRght; + + /* Binary Search */ + bpIdx = maxIndex >> 1U; + iLeft = 0U; + iRght = maxIndex; + while (iRght - iLeft > 1U) { + if (u0 < bp0[bpIdx]) { + iRght = bpIdx; + } else { + iLeft = bpIdx; + } + + bpIdx = (iRght + iLeft) >> 1U; + } + + uint16_t bpLeftVar; + bpLeftVar = bp0[iLeft]; + frac = ((uint64_t)((uint32_t)u0 - bpLeftVar) << 48) / ((uint32_t)bp0[iLeft + + 1U] - bpLeftVar); + } else { + iLeft = maxIndex - 1U; + frac = 281474976710656ULL; + } + + /* Column-major Interpolation 1-D + Interpolation method: 'Linear point-slope' + Use last breakpoint for index at or above upper limit: 'off' + Rounding mode: 'simplest' + Overflow mode: 'wrapping' + */ + yR_0d0 = table[iLeft + 1U]; + yL_0d0 = table[iLeft]; + if (yR_0d0 >= yL_0d0) { + y = (uint8_t)((uint32_t)(uint8_t)(((uint8_t)((uint32_t)yR_0d0 - yL_0d0) * + frac) >> 48) + yL_0d0); + } else { + y = (uint8_t)((uint32_t)yL_0d0 - (uint8_t)(((uint8_t)((uint32_t)yL_0d0 - + yR_0d0) * frac) >> 48)); + } + + return y; +} + +int16_t look1_iu16tdIs16_binlcs(uint16_t u0, const uint16_t bp0[], const double + table[], uint32_t maxIndex) +{ + double frac; + double yL_0d0; + int32_t tmp_1; + uint32_t iLeft; + int16_t tmp; + int16_t tmp_0; + + /* Column-major Lookup 1-D + Search method: 'binary' + Use previous index: 'off' + Interpolation method: 'Linear point-slope' + Extrapolation method: 'Clip' + Use last breakpoint for index at or above upper limit: 'off' + Remove protection against out-of-range input in generated code: 'off' + */ + /* Prelookup - Index and Fraction + Index Search method: 'binary' + Extrapolation method: 'Clip' + Use previous index: 'off' + Use last breakpoint for index at or above upper limit: 'off' + Remove protection against out-of-range input in generated code: 'off' + */ + if (u0 <= bp0[0U]) { + iLeft = 0U; + frac = 0.0; + } else if (u0 < bp0[maxIndex]) { + uint32_t bpIdx; + uint32_t iRght; + + /* Binary Search */ + bpIdx = maxIndex >> 1U; + iLeft = 0U; + iRght = maxIndex; + while (iRght - iLeft > 1U) { + if (u0 < bp0[bpIdx]) { + iRght = bpIdx; + } else { + iLeft = bpIdx; + } + + bpIdx = (iRght + iLeft) >> 1U; + } + + uint16_t bpLeftVar; + bpLeftVar = bp0[iLeft]; + frac = (double)((uint32_t)u0 - bpLeftVar) / (double)((uint32_t)bp0[iLeft + + 1U] - bpLeftVar); + } else { + iLeft = maxIndex - 1U; + frac = 1.0; + } + + /* Column-major Interpolation 1-D + Interpolation method: 'Linear point-slope' + Use last breakpoint for index at or above upper limit: 'off' + Overflow mode: 'saturate' + */ + yL_0d0 = table[iLeft]; + if (yL_0d0 < 32768.0) { + if (yL_0d0 >= -32768.0) { + tmp = (int16_t)yL_0d0; + } else { + tmp = INT16_MIN; + } + } else { + tmp = INT16_MAX; + } + + frac *= table[iLeft + 1U] - yL_0d0; + if (frac < 32768.0) { + if (frac >= -32768.0) { + tmp_0 = (int16_t)frac; + } else { + tmp_0 = INT16_MIN; + } + } else { + tmp_0 = INT16_MAX; + } + + tmp_1 = tmp + tmp_0; + if (tmp_1 > 32767) { + tmp_1 = 32767; + } else if (tmp_1 < -32768) { + tmp_1 = -32768; + } + + return (int16_t)tmp_1; +} + +int16_t look1_iu16lu64n48ts16Ds32_binlcs(uint16_t u0, const uint16_t bp0[], + const int16_t table[], uint32_t maxIndex) +{ + uint64_t frac; + uint32_t iLeft; + int16_t yL_0d0; + + /* Column-major Lookup 1-D + Search method: 'binary' + Use previous index: 'off' + Interpolation method: 'Linear point-slope' + Extrapolation method: 'Clip' + Use last breakpoint for index at or above upper limit: 'off' + Remove protection against out-of-range input in generated code: 'off' + Rounding mode: 'simplest' + */ + /* Prelookup - Index and Fraction + Index Search method: 'binary' + Extrapolation method: 'Clip' + Use previous index: 'off' + Use last breakpoint for index at or above upper limit: 'off' + Remove protection against out-of-range input in generated code: 'off' + Rounding mode: 'simplest' + */ + if (u0 <= bp0[0U]) { + iLeft = 0U; + frac = 0ULL; + } else if (u0 < bp0[maxIndex]) { + uint32_t bpIdx; + uint32_t iRght; + + /* Binary Search */ + bpIdx = maxIndex >> 1U; + iLeft = 0U; + iRght = maxIndex; + while (iRght - iLeft > 1U) { + if (u0 < bp0[bpIdx]) { + iRght = bpIdx; + } else { + iLeft = bpIdx; + } + + bpIdx = (iRght + iLeft) >> 1U; + } + + uint16_t bpLeftVar; + bpLeftVar = bp0[iLeft]; + frac = ((uint64_t)((uint32_t)u0 - bpLeftVar) << 48) / ((uint32_t)bp0[iLeft + + 1U] - bpLeftVar); + } else { + iLeft = maxIndex - 1U; + frac = 281474976710656ULL; + } + + /* Column-major Interpolation 1-D + Interpolation method: 'Linear point-slope' + Use last breakpoint for index at or above upper limit: 'off' + Rounding mode: 'simplest' + Overflow mode: 'wrapping' + */ + yL_0d0 = table[iLeft]; + return (int16_t)((int16_t)(((table[iLeft + 1U] - yL_0d0) * (int64_t)frac) >> + 48) + yL_0d0); +} + +int16_t look1_iu16bs16lu64n32ts16Ds32_binlcs(uint16_t u0, const int16_t bp0[], + const int16_t table[], uint32_t maxIndex) +{ + uint64_t frac; + uint32_t iLeft; + int16_t yL_0d0; + uint16_t tmp; + + /* Column-major Lookup 1-D + Search method: 'binary' + Use previous index: 'off' + Interpolation method: 'Linear point-slope' + Extrapolation method: 'Clip' + Use last breakpoint for index at or above upper limit: 'off' + Remove protection against out-of-range input in generated code: 'off' + Rounding mode: 'simplest' + */ + /* Prelookup - Index and Fraction + Index Search method: 'binary' + Extrapolation method: 'Clip' + Use previous index: 'off' + Use last breakpoint for index at or above upper limit: 'off' + Remove protection against out-of-range input in generated code: 'off' + Rounding mode: 'simplest' + */ + tmp = u0; + if (u0 > 32767) { + tmp = 32767U; + } + + if (u0 < bp0[0U]) { + iLeft = 0U; + frac = 0ULL; + } else if ((int16_t)tmp < bp0[maxIndex]) { + uint32_t bpIdx; + uint32_t iRght; + + /* Binary Search */ + bpIdx = maxIndex >> 1U; + iLeft = 0U; + iRght = maxIndex; + while (iRght - iLeft > 1U) { + if ((int16_t)tmp < bp0[bpIdx]) { + iRght = bpIdx; + } else { + iLeft = bpIdx; + } + + bpIdx = (iRght + iLeft) >> 1U; + } + + frac = ((uint64_t)(u0 - (uint32_t)bp0[iLeft]) << 32) / (uint32_t)(bp0[iLeft + + 1U] - bp0[iLeft]); + } else { + iLeft = maxIndex - 1U; + frac = 4294967296ULL; + } + + /* Column-major Interpolation 1-D + Interpolation method: 'Linear point-slope' + Use last breakpoint for index at or above upper limit: 'off' + Rounding mode: 'simplest' + Overflow mode: 'wrapping' + */ + yL_0d0 = table[iLeft]; + return (int16_t)((int16_t)(((table[iLeft + 1U] - yL_0d0) * (int64_t)frac) >> + 32) + yL_0d0); +} + +double look1_bs16ts16DdId_binlc(double u0, const int16_t bp0[], const int16_t + table[], uint32_t maxIndex) +{ + double frac; + uint32_t iLeft; + int16_t uCast; + + /* Column-major Lookup 1-D + Search method: 'binary' + Use previous index: 'off' + Interpolation method: 'Linear point-slope' + Extrapolation method: 'Clip' + Use last breakpoint for index at or above upper limit: 'off' + Remove protection against out-of-range input in generated code: 'off' + */ + /* Prelookup - Index and Fraction + Index Search method: 'binary' + Extrapolation method: 'Clip' + Use previous index: 'off' + Use last breakpoint for index at or above upper limit: 'off' + Remove protection against out-of-range input in generated code: 'off' + */ + frac = floor(u0); + if (frac < 32768.0) { + if (frac >= -32768.0) { + uCast = (int16_t)frac; + } else { + uCast = INT16_MIN; + } + } else { + uCast = INT16_MAX; + } + + if (u0 < bp0[0U]) { + iLeft = 0U; + frac = 0.0; + } else if (u0 < bp0[maxIndex]) { + uint32_t bpIdx; + uint32_t iRght; + + /* Binary Search */ + bpIdx = maxIndex >> 1U; + iLeft = 0U; + iRght = maxIndex; + while (iRght - iLeft > 1U) { + if (uCast < bp0[bpIdx]) { + iRght = bpIdx; + } else { + iLeft = bpIdx; + } + + bpIdx = (iRght + iLeft) >> 1U; + } + + frac = (u0 - (double)bp0[iLeft]) / (double)(uint32_t)(bp0[iLeft + 1U] - + bp0[iLeft]); + } else { + iLeft = maxIndex - 1U; + frac = 1.0; + } + + /* Column-major Interpolation 1-D + Interpolation method: 'Linear point-slope' + Use last breakpoint for index at or above upper limit: 'off' + Overflow mode: 'wrapping' + */ + uCast = table[iLeft]; + return ((double)table[iLeft + 1U] - (double)uCast) * frac + (double)uCast; +} + +uint8_t look1_iu8lu64n56_binlcse(uint8_t u0, const uint8_t bp0[], const uint8_t + table[], uint32_t maxIndex) +{ + uint64_t frac; + uint32_t iLeft; + uint8_t bpLeftVar; + uint8_t y; + uint8_t yL_0d0; + + /* Column-major Lookup 1-D + Search method: 'binary' + Use previous index: 'off' + Interpolation method: 'Linear point-slope' + Extrapolation method: 'Clip' + Use last breakpoint for index at or above upper limit: 'off' + Remove protection against out-of-range input in generated code: 'off' + Rounding mode: 'simplest' + */ + /* Prelookup - Index and Fraction + Index Search method: 'binary' + Extrapolation method: 'Clip' + Use previous index: 'off' + Use last breakpoint for index at or above upper limit: 'off' + Remove protection against out-of-range input in generated code: 'off' + Rounding mode: 'simplest' + */ + if (u0 <= bp0[0U]) { + iLeft = 0U; + frac = 0ULL; + } else if (u0 < bp0[maxIndex]) { + uint32_t bpIdx; + uint32_t iRght; + + /* Binary Search */ + bpIdx = maxIndex >> 1U; + iLeft = 0U; + iRght = maxIndex; + while (iRght - iLeft > 1U) { + if (u0 < bp0[bpIdx]) { + iRght = bpIdx; + } else { + iLeft = bpIdx; + } + + bpIdx = (iRght + iLeft) >> 1U; + } + + bpLeftVar = bp0[iLeft]; + frac = ((uint64_t)((uint32_t)u0 - bpLeftVar) << 56) / ((uint32_t)bp0[iLeft + + 1U] - bpLeftVar); + } else { + iLeft = maxIndex - 1U; + frac = 72057594037927936ULL; + } + + /* Column-major Interpolation 1-D + Interpolation method: 'Linear point-slope' + Use last breakpoint for index at or above upper limit: 'off' + Rounding mode: 'simplest' + Overflow mode: 'wrapping' + */ + bpLeftVar = table[iLeft + 1U]; + yL_0d0 = table[iLeft]; + if (bpLeftVar >= yL_0d0) { + y = (uint8_t)((uint32_t)(uint8_t)(((uint8_t)((uint32_t)bpLeftVar - yL_0d0) * + frac) >> 56) + yL_0d0); + } else { + y = (uint8_t)((uint32_t)yL_0d0 - (uint8_t)(((uint8_t)((uint32_t)yL_0d0 - + bpLeftVar) * frac) >> 56)); + } + + return y; +} + +double look1_iu16td_binlc(uint16_t u0, const uint16_t bp0[], const double table[], + uint32_t maxIndex) +{ + double frac; + double yL_0d0; + uint32_t iLeft; + + /* Column-major Lookup 1-D + Search method: 'binary' + Use previous index: 'off' + Interpolation method: 'Linear point-slope' + Extrapolation method: 'Clip' + Use last breakpoint for index at or above upper limit: 'off' + Remove protection against out-of-range input in generated code: 'off' + */ + /* Prelookup - Index and Fraction + Index Search method: 'binary' + Extrapolation method: 'Clip' + Use previous index: 'off' + Use last breakpoint for index at or above upper limit: 'off' + Remove protection against out-of-range input in generated code: 'off' + */ + if (u0 <= bp0[0U]) { + iLeft = 0U; + frac = 0.0; + } else if (u0 < bp0[maxIndex]) { + uint32_t bpIdx; + uint32_t iRght; + + /* Binary Search */ + bpIdx = maxIndex >> 1U; + iLeft = 0U; + iRght = maxIndex; + while (iRght - iLeft > 1U) { + if (u0 < bp0[bpIdx]) { + iRght = bpIdx; + } else { + iLeft = bpIdx; + } + + bpIdx = (iRght + iLeft) >> 1U; + } + + uint16_t bpLeftVar; + bpLeftVar = bp0[iLeft]; + frac = (double)((uint32_t)u0 - bpLeftVar) / (double)((uint32_t)bp0[iLeft + + 1U] - bpLeftVar); + } else { + iLeft = maxIndex - 1U; + frac = 1.0; + } + + /* Column-major Interpolation 1-D + Interpolation method: 'Linear point-slope' + Use last breakpoint for index at or above upper limit: 'off' + Overflow mode: 'wrapping' + */ + yL_0d0 = table[iLeft]; + return (table[iLeft + 1U] - yL_0d0) * frac + yL_0d0; +} + +uint32_t plook_u32s16_bincka(int16_t u_6, const int16_t bp[], uint32_t maxIndex) +{ + uint32_t bpIndex; + + /* Prelookup - Index only + Index Search method: 'binary' + Extrapolation method: 'Clip' + Use previous index: 'off' + Use last breakpoint for index at or above upper limit: 'on' + Remove protection against out-of-range input in generated code: 'off' + */ + if (u_6 <= bp[0U]) { + bpIndex = 0U; + } else if (u_6 < bp[maxIndex]) { + bpIndex = binsearch_u32s16(u_6, bp, maxIndex >> 1U, maxIndex); + } else { + bpIndex = maxIndex; + } + + return bpIndex; +} + +int32_t div_nzp_s32_round(int32_t numerator, int32_t denominator) +{ + uint32_t absDenominator; + uint32_t absNumerator; + uint32_t tempAbsQuotient; + absNumerator = numerator < 0 ? ~(uint32_t)numerator + 1U : (uint32_t)numerator; + absDenominator = denominator < 0 ? ~(uint32_t)denominator + 1U : (uint32_t) + denominator; + tempAbsQuotient = absNumerator / absDenominator; + absNumerator %= absDenominator; + absNumerator <<= 1U; + if (absNumerator >= absDenominator) { + tempAbsQuotient++; + } + + return (numerator < 0) != (denominator < 0) ? -(int32_t)tempAbsQuotient : + (int32_t)tempAbsQuotient; +} + +/* + * Output and update for atomic system: + * '/get_tg_FLL_for_LVL' + * '/get_tg_FLL_for_LVL' + * '/get_tg_for_LVL' + * '/get_tg_FLL_for_LVL' + * '/get_tg_FLL_for_LVL' + * '/get_tg_for_LVL' + */ +void get_tg_FLL_for_LVL(uint8_t rtu_ambient_Lvl, uint8_t rtu_set_tmp, int16_t + *rty_vals) +{ + int32_t i; + uint32_t qY; + int16_t tmp[78]; + + /* : table = [ */ + /* : g_assTG_FLL_LV0; */ + /* : g_assTG_FLL_LV1; */ + /* : g_assTG_FLL_LV2; */ + /* : g_assTG_FLL_LV3; */ + /* : g_assTG_FLL_LV4; */ + /* : g_assTG_FLL_LV5 */ + /* : ]; */ + /* : vals = table(ambient_Lvl + 1, set_tmp - 16); */ + for (i = 0; i < 13; i++) { + tmp[6 * i] = g_assTG_FLL_LV0[i]; + tmp[6 * i + 1] = g_assTG_FLL_LV1[i]; + tmp[6 * i + 2] = g_assTG_FLL_LV2[i]; + tmp[6 * i + 3] = g_assTG_FLL_LV3[i]; + tmp[6 * i + 4] = g_assTG_FLL_LV4[i]; + tmp[6 * i + 5] = g_assTG_FLL_LV5[i]; + } + + i = (int32_t)(rtu_ambient_Lvl + 1U); + if (rtu_ambient_Lvl + 1U > 255U) { + i = 255; + } + + /* MW:begin MISRA2012:D4.1 CERT-C:INT30-C 'Justifying MISRA CPP rule violation' */ + qY = rtu_set_tmp - 16U; + + /* MW:end MISRA2012:D4.1 CERT-C:INT30-C */ + if (rtu_set_tmp - 16U > rtu_set_tmp) { + qY = 0U; + } + + *rty_vals = tmp[(((int32_t)qY - 1) * 6 + i) - 1]; +} + +/* + * Output and update for atomic system: + * '/get_tg_FLL_for_LVL' + * '/get_tg_FLL_for_LVL' + * '/get_tg_FLL_for_LVL' + * '/get_tg_FLL_for_LVL' + * '/get_tg_FLL_for_LVL' + * '/get_tg_FLL_for_LVL' + */ +void get_tg_FLL_for_LVL_j(uint8_t rtu_ambient_Lvl, uint8_t rtu_set_tmp, int16_t * + rty_vals) +{ + int32_t i; + uint32_t qY; + int16_t tmp[78]; + + /* : table = [ */ + /* : g_assTG_FRL_LV0; */ + /* : g_assTG_FRL_LV1; */ + /* : g_assTG_FRL_LV2; */ + /* : g_assTG_FRL_LV3; */ + /* : g_assTG_FRL_LV4; */ + /* : g_assTG_FRL_LV5 */ + /* : ]; */ + /* : vals = table(ambient_Lvl + 1, set_tmp - 16); */ + for (i = 0; i < 13; i++) { + tmp[6 * i] = g_assTG_FRL_LV0[i]; + tmp[6 * i + 1] = g_assTG_FRL_LV1[i]; + tmp[6 * i + 2] = g_assTG_FRL_LV2[i]; + tmp[6 * i + 3] = g_assTG_FRL_LV3[i]; + tmp[6 * i + 4] = g_assTG_FRL_LV4[i]; + tmp[6 * i + 5] = g_assTG_FRL_LV5[i]; + } + + i = (int32_t)(rtu_ambient_Lvl + 1U); + if (rtu_ambient_Lvl + 1U > 255U) { + i = 255; + } + + /* MW:begin MISRA2012:D4.1 CERT-C:INT30-C 'Justifying MISRA CPP rule violation' */ + qY = rtu_set_tmp - 16U; + + /* MW:end MISRA2012:D4.1 CERT-C:INT30-C */ + if (rtu_set_tmp - 16U > rtu_set_tmp) { + qY = 0U; + } + + *rty_vals = tmp[(((int32_t)qY - 1) * 6 + i) - 1]; +} + +/* + * Output and update for atomic system: + * '/g_assFLOW_BI_AMB_TGT' + * '/g_assFLOW_BI_AMB_TGT' + * '/g_assFLOW_BI_AMB_TGT' + * '/g_assFLOW_BI_AMB_TGT' + */ +void g_assFLOW_BI_AMB_TGT_n(uint8_t rtu_LVL, int16_t *rty_c_g_assFLOW_BI_AMB_TGT) +{ + int32_t tmp; + + /* : c_g_assFLOW_BI_AMB_TGT = g_assFLOW_BI_AMB_TGT(LVL + 1); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + *rty_c_g_assFLOW_BI_AMB_TGT = g_assFLOW_BI_AMB_TGT[tmp - 1]; +} + +/* + * Output and update for action system: + * '/Bilevel' + * '/Bilevel' + */ +void Bilevel(int16_t rtu_Amb_Fb, uint8_t rtu_LVL, uint16_t rty_Out1[9], uint8_t + rtu_setTempFL, uint8_t rtu_setTempFR) +{ + int32_t tmp; + int32_t tmp_0; + int16_t rtb_u_eg; + uint16_t rtb_FLF_NEW; + uint16_t rtb_FRF_NEW; + uint16_t rtb_Switch2_a5_idx_0; + uint16_t rtb_Switch2_a5_idx_1; + uint16_t rtb_Switch2_cd_0; + int8_t rtb_X_l; + uint8_t rtb_c_g_aucFLOW_BI2_FOOT_VALVE_MIN; + uint8_t rtb_c_g_aucFLOW_BI_FOOT_VALVE_MAX; + uint8_t rtb_c_g_aucFLOW_BI_FOOT_VALVE_MAX_n; + uint8_t rtb_c_g_aucFLOW_BI_FOOT_VALVE_MIN; + uint8_t rtb_c_g_aucFLOW_BI_VENT_VALVE_MAX; + uint8_t rtb_c_g_aucFLOW_BI_VENT_VALVE_MAX_h; + uint8_t rtb_c_g_aucFLOW_BI_VENT_VALVE_MIN; + uint8_t rtb_c_g_aucFLOW_BI_VENT_VALVE_MIN_a; + + /* MATLAB Function: '/get_tg_FLL_for_LVL' */ + /* : c_g_assFLOW_BI_TEMP_TGT = g_assFLOW_BI_TEMP_TGT(LVL + 1); */ + get_tg_FLL_for_LVL(rtu_LVL, rtu_setTempFL, &rtb_u_eg); + + /* MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + /* Sum: '/ 1' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + */ + rtb_u_eg = (int16_t)(g_assFLOW_BI_TEMP_TGT[tmp_0 - 1] - rtb_u_eg); + + /* Gain: '/Gain6' */ + tmp_0 = 13107 * rtb_u_eg; + rtb_X_l = (int8_t)(((((uint32_t)tmp_0 & 65536U) != 0U) && ((((uint32_t)tmp_0 & + 65535U) != 0U) || (tmp_0 > 0))) + (tmp_0 >> 17)); + + /* Switch: '/Switch1' incorporates: + * Gain: '/Gain6' + * Sum: '/Add' + */ + /* : c_g_aucFLOW_BI_FOOT_PLUS = g_aucFLOW_BI_FOOT_PLUS(LVL + 1); */ + if (rtb_X_l >= 0) { + rtb_FLF_NEW = rty_Out1[4]; + } else { + /* MATLAB Function: '/g_aucFLOW_BI_FOOT_PLUS_LEFT' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + /* Gain: '/Gain6' incorporates: + * MATLAB Function: '/g_aucFLOW_BI_FOOT_PLUS_LEFT' + * Product: '/Product3' + */ + tmp_0 = g_aucFLOW_BI_FOOT_PLUS[tmp_0 - 1] * rtb_X_l * 13107; + rtb_FLF_NEW = (uint16_t)((int16_t)rty_Out1[4] - (int8_t)(((((uint32_t)tmp_0 + & 65536U) != 0U) && (((uint32_t)tmp_0 & 65535U) != 0U)) + (tmp_0 >> 17))); + } + + /* End of Switch: '/Switch1' */ + + /* MATLAB Function: '/g_aucFLOW_BI_FOOT_VALVE_MAX1' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + */ + /* : c_g_aucFLOW_BI_FOOT_VALVE_MAX = g_aucFLOW_BI_FOOT_VALVE_MAX(LVL + 1); */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + rtb_c_g_aucFLOW_BI_FOOT_VALVE_MAX_n = g_aucFLOW_BI_FOOT_VALVE_MAX[tmp_0 - 1]; + + /* End of MATLAB Function: '/g_aucFLOW_BI_FOOT_VALVE_MAX1' */ + + /* MATLAB Function: '/g_aucFLOW_BI_FOOT_VALVE_MIN1' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + */ + /* : c_g_aucFLOW_BI2_FOOT_VALVE_MIN = g_aucFLOW_BI_FOOT_VALVE_MIN(LVL +1); */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + rtb_c_g_aucFLOW_BI2_FOOT_VALVE_MIN = g_aucFLOW_BI_FOOT_VALVE_MIN[tmp_0 - 1]; + + /* End of MATLAB Function: '/g_aucFLOW_BI_FOOT_VALVE_MIN1' */ + + /* MATLAB Function: '/get_tg_FLL_for_LVL' */ + /* : c_g_assFLOW_BI_TEMP_TGT = g_assFLOW_BI_TEMP_TGT(LVL + 1 + 6); */ + get_tg_FLL_for_LVL_j(rtu_LVL, rtu_setTempFR, &rtb_u_eg); + + /* MATLAB Function: '/g_assFLOW_BI_TEMP_TGT_RIGHT' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + tmp = (int32_t)((uint32_t)tmp_0 + 6U); + if ((uint32_t)tmp_0 + 6U > 255U) { + tmp = 255; + } + + /* Sum: '/ 1' incorporates: + * MATLAB Function: '/g_assFLOW_BI_TEMP_TGT_RIGHT' + */ + rtb_u_eg = (int16_t)(g_assFLOW_BI_TEMP_TGT[tmp - 1] - rtb_u_eg); + + /* Gain: '/Gain6' */ + tmp_0 = 13107 * rtb_u_eg; + rtb_X_l = (int8_t)(((((uint32_t)tmp_0 & 65536U) != 0U) && ((((uint32_t)tmp_0 & + 65535U) != 0U) || (tmp_0 > 0))) + (tmp_0 >> 17)); + + /* Switch: '/Switch3' incorporates: + * Gain: '/Gain7' + * Sum: '/Add1' + */ + /* : c_g_aucFLOW_BI_FOOT_PLUS = g_aucFLOW_BI_FOOT_PLUS(LVL + 1 + 6); */ + if (rtb_X_l >= 0) { + rtb_FRF_NEW = rty_Out1[6]; + } else { + /* MATLAB Function: '/g_aucFLOW_BI_FOOT_PLUS_RIGHT' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + tmp = (int32_t)((uint32_t)tmp_0 + 6U); + if ((uint32_t)tmp_0 + 6U > 255U) { + tmp = 255; + } + + /* Gain: '/Gain7' incorporates: + * MATLAB Function: '/g_aucFLOW_BI_FOOT_PLUS_RIGHT' + * Product: '/Product4' + */ + tmp_0 = g_aucFLOW_BI_FOOT_PLUS[tmp - 1] * rtb_X_l * 13107; + rtb_FRF_NEW = (uint16_t)((int16_t)rty_Out1[6] - (int8_t)(((((uint32_t)tmp_0 + & 65536U) != 0U) && (((uint32_t)tmp_0 & 65535U) != 0U)) + (tmp_0 >> 17))); + } + + /* End of Switch: '/Switch3' */ + + /* MATLAB Function: '/g_aucFLOW_BI_FOOT_VALVE_MAX2' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + */ + /* : c_g_aucFLOW_BI_FOOT_VALVE_MAX = g_aucFLOW_BI_FOOT_VALVE_MAX(LVL + 1 + 6); */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + tmp = (int32_t)((uint32_t)tmp_0 + 6U); + if ((uint32_t)tmp_0 + 6U > 255U) { + tmp = 255; + } + + rtb_c_g_aucFLOW_BI_FOOT_VALVE_MAX = g_aucFLOW_BI_FOOT_VALVE_MAX[tmp - 1]; + + /* End of MATLAB Function: '/g_aucFLOW_BI_FOOT_VALVE_MAX2' */ + + /* MATLAB Function: '/g_aucFLOW_BI_FOOT_VALVE_MIN2' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + */ + /* : c_g_aucFLOW_BI_FOOT_VALVE_MIN = g_aucFLOW_BI_FOOT_VALVE_MIN(LVL + 1 + 6); */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + tmp = (int32_t)((uint32_t)tmp_0 + 6U); + if ((uint32_t)tmp_0 + 6U > 255U) { + tmp = 255; + } + + rtb_c_g_aucFLOW_BI_FOOT_VALVE_MIN = g_aucFLOW_BI_FOOT_VALVE_MIN[tmp - 1]; + + /* End of MATLAB Function: '/g_aucFLOW_BI_FOOT_VALVE_MIN2' */ + + /* MATLAB Function: '/g_assFLOW_BI_AMB_TGT' */ + /* : c_g_aucFLOW_BI_VENT_PLUS = g_aucFLOW_BI_VENT_PLUS(LVL + 1); */ + g_assFLOW_BI_AMB_TGT_n(rtu_LVL, &rtb_u_eg); + + /* MATLAB Function: '/g_aucFLOW_BI_VENT_PLUS' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + /* Gain: '/Gain2' incorporates: + * Sum: '/deg' + */ + tmp = (int16_t)(rtb_u_eg - rtu_Amb_Fb) * 13107; + + /* Product: '/' incorporates: + * Gain: '/Gain' + * Gain: '/Gain2' + * MATLAB Function: '/g_aucFLOW_BI_VENT_PLUS' + */ + rtb_u_eg = (int16_t)((int8_t)(((((uint32_t)tmp & 65536U) != 0U) && + ((((uint32_t)tmp & 65535U) != 0U) || (tmp > 0))) + (tmp >> 17)) * (int32_t) + ((g_aucFLOW_BI_VENT_PLUS[tmp_0 - 1] * 205U + 1024U) >> 11)); + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * Sum: '/ ' + * Switch: '/Switch2' + */ + rtb_Switch2_a5_idx_0 = (uint16_t)((uint16_t)((rty_Out1[0] - rtb_u_eg) >> 1) << + 1); + rtb_Switch2_a5_idx_1 = (uint16_t)((uint16_t)((rty_Out1[1] - rtb_u_eg) >> 1) << + 1); + + /* MATLAB Function: '/g_aucFLOW_BI_VENT_VALVE_MAX' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + */ + /* : c_g_aucFLOW_BI_VENT_VALVE_MAX = g_aucFLOW_BI_VENT_VALVE_MAX(LVL + 1); */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + rtb_c_g_aucFLOW_BI_VENT_VALVE_MAX_h = g_aucFLOW_BI_VENT_VALVE_MAX[tmp_0 - 1]; + + /* End of MATLAB Function: '/g_aucFLOW_BI_VENT_VALVE_MAX' */ + + /* MATLAB Function: '/g_aucFLOW_BI_VENT_VALVE_MIN' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + */ + /* : c_g_aucFLOW_BI_VENT_VALVE_MIN = g_aucFLOW_BI_VENT_VALVE_MIN(LVL + 1); */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + rtb_c_g_aucFLOW_BI_VENT_VALVE_MIN_a = g_aucFLOW_BI_VENT_VALVE_MIN[tmp_0 - 1]; + + /* End of MATLAB Function: '/g_aucFLOW_BI_VENT_VALVE_MIN' */ + + /* MATLAB Function: '/g_assFLOW_BI_AMB_TGT' */ + /* : c_g_aucFLOW_BI_VENT_PLUS = g_aucFLOW_BI_VENT_PLUS(LVL + 1 + 6); */ + g_assFLOW_BI_AMB_TGT_n(rtu_LVL, &rtb_u_eg); + + /* MATLAB Function: '/g_aucFLOW_BI_VENT_PLUS' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + tmp = (int32_t)((uint32_t)tmp_0 + 6U); + if ((uint32_t)tmp_0 + 6U > 255U) { + tmp = 255; + } + + /* Gain: '/Gain2' incorporates: + * Sum: '/deg' + */ + tmp_0 = (int16_t)(rtb_u_eg - rtu_Amb_Fb) * 13107; + + /* Product: '/' incorporates: + * Gain: '/Gain' + * Gain: '/Gain2' + * MATLAB Function: '/g_aucFLOW_BI_VENT_PLUS' + */ + rtb_u_eg = (int16_t)((int8_t)(((((uint32_t)tmp_0 & 65536U) != 0U) && + ((((uint32_t)tmp_0 & 65535U) != 0U) || (tmp_0 > 0))) + (tmp_0 >> 17)) * + (int32_t)((g_aucFLOW_BI_VENT_PLUS[tmp - 1] * 205U + 1024U) + >> 11)); + + /* MATLAB Function: '/g_aucFLOW_BI_VENT_VALVE_MAX' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + */ + /* : c_g_aucFLOW_BI_VENT_VALVE_MAX = g_aucFLOW_BI_VENT_VALVE_MAX(LVL + 1 + 6); */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + tmp = (int32_t)((uint32_t)tmp_0 + 6U); + if ((uint32_t)tmp_0 + 6U > 255U) { + tmp = 255; + } + + rtb_c_g_aucFLOW_BI_VENT_VALVE_MAX = g_aucFLOW_BI_VENT_VALVE_MAX[tmp - 1]; + + /* End of MATLAB Function: '/g_aucFLOW_BI_VENT_VALVE_MAX' */ + + /* MATLAB Function: '/g_aucFLOW_BI_VENT_VALVE_MIN' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + */ + /* : c_g_aucFLOW_BI_VENT_VALVE_MIN = g_aucFLOW_BI_VENT_VALVE_MIN(LVL + 1 + 6); */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + tmp = (int32_t)((uint32_t)tmp_0 + 6U); + if ((uint32_t)tmp_0 + 6U > 255U) { + tmp = 255; + } + + rtb_c_g_aucFLOW_BI_VENT_VALVE_MIN = g_aucFLOW_BI_VENT_VALVE_MIN[tmp - 1]; + + /* End of MATLAB Function: '/g_aucFLOW_BI_VENT_VALVE_MIN' */ + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * Sum: '/ ' + * Switch: '/Switch2' + */ + rtb_Switch2_cd_0 = (uint16_t)((uint16_t)((rty_Out1[0] - rtb_u_eg) >> 1) << 1); + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + * RelationalOperator: '/UpperRelop' + * Switch: '/Switch' + */ + if (rtb_Switch2_a5_idx_0 > rtb_c_g_aucFLOW_BI_VENT_VALVE_MAX_h) { + /* Assignment: '/ [1-2]' incorporates: + * SignalConversion generated from: '/Out1' + */ + rty_Out1[0] = rtb_c_g_aucFLOW_BI_VENT_VALVE_MAX_h; + } else if (rtb_Switch2_a5_idx_0 < rtb_c_g_aucFLOW_BI_VENT_VALVE_MIN_a) { + /* Switch: '/Switch' incorporates: + * Assignment: '/ [1-2]' + * SignalConversion generated from: '/Out1' + */ + rty_Out1[0] = rtb_c_g_aucFLOW_BI_VENT_VALVE_MIN_a; + } else { + /* Assignment: '/ [1-2]' incorporates: + * SignalConversion generated from: '/Out1' + * Switch: '/Switch' + */ + rty_Out1[0] = rtb_Switch2_a5_idx_0; + } + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + * RelationalOperator: '/UpperRelop' + * Switch: '/Switch' + */ + if (rtb_Switch2_cd_0 > rtb_c_g_aucFLOW_BI_VENT_VALVE_MAX) { + /* Assignment: '/ [3-4]' incorporates: + * SignalConversion generated from: '/Out1' + */ + rty_Out1[2] = rtb_c_g_aucFLOW_BI_VENT_VALVE_MAX; + } else if (rtb_Switch2_cd_0 < rtb_c_g_aucFLOW_BI_VENT_VALVE_MIN) { + /* Switch: '/Switch' incorporates: + * Assignment: '/ [3-4]' + * SignalConversion generated from: '/Out1' + */ + rty_Out1[2] = rtb_c_g_aucFLOW_BI_VENT_VALVE_MIN; + } else { + /* Assignment: '/ [3-4]' incorporates: + * SignalConversion generated from: '/Out1' + * Switch: '/Switch' + */ + rty_Out1[2] = rtb_Switch2_cd_0; + } + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * Sum: '/ ' + * Switch: '/Switch2' + */ + rtb_Switch2_cd_0 = (uint16_t)((uint16_t)((rty_Out1[1] - rtb_u_eg) >> 1) << 1); + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + * RelationalOperator: '/UpperRelop' + * Switch: '/Switch' + */ + if (rtb_Switch2_a5_idx_1 > rtb_c_g_aucFLOW_BI_VENT_VALVE_MAX_h) { + /* Assignment: '/ [1-2]' incorporates: + * SignalConversion generated from: '/Out1' + */ + rty_Out1[1] = rtb_c_g_aucFLOW_BI_VENT_VALVE_MAX_h; + } else if (rtb_Switch2_a5_idx_1 < rtb_c_g_aucFLOW_BI_VENT_VALVE_MIN_a) { + /* Switch: '/Switch' incorporates: + * Assignment: '/ [1-2]' + * SignalConversion generated from: '/Out1' + */ + rty_Out1[1] = rtb_c_g_aucFLOW_BI_VENT_VALVE_MIN_a; + } else { + /* Assignment: '/ [1-2]' incorporates: + * SignalConversion generated from: '/Out1' + * Switch: '/Switch' + */ + rty_Out1[1] = rtb_Switch2_a5_idx_1; + } + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + * RelationalOperator: '/UpperRelop' + * Switch: '/Switch' + */ + if (rtb_Switch2_cd_0 > rtb_c_g_aucFLOW_BI_VENT_VALVE_MAX) { + /* Assignment: '/ [3-4]' incorporates: + * SignalConversion generated from: '/Out1' + */ + rty_Out1[3] = rtb_c_g_aucFLOW_BI_VENT_VALVE_MAX; + } else if (rtb_Switch2_cd_0 < rtb_c_g_aucFLOW_BI_VENT_VALVE_MIN) { + /* Switch: '/Switch' incorporates: + * Assignment: '/ [3-4]' + * SignalConversion generated from: '/Out1' + */ + rty_Out1[3] = rtb_c_g_aucFLOW_BI_VENT_VALVE_MIN; + } else { + /* Assignment: '/ [3-4]' incorporates: + * SignalConversion generated from: '/Out1' + * Switch: '/Switch' + */ + rty_Out1[3] = rtb_Switch2_cd_0; + } + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + * RelationalOperator: '/UpperRelop' + * Switch: '/Switch' + */ + if (rtb_FLF_NEW > rtb_c_g_aucFLOW_BI_FOOT_VALVE_MAX_n) { + /* Assignment: '/ [5]' incorporates: + * SignalConversion generated from: '/Out1' + */ + rty_Out1[4] = rtb_c_g_aucFLOW_BI_FOOT_VALVE_MAX_n; + } else if (rtb_FLF_NEW < rtb_c_g_aucFLOW_BI2_FOOT_VALVE_MIN) { + /* Switch: '/Switch' incorporates: + * Assignment: '/ [5]' + * SignalConversion generated from: '/Out1' + */ + rty_Out1[4] = rtb_c_g_aucFLOW_BI2_FOOT_VALVE_MIN; + } else { + /* Assignment: '/ [5]' incorporates: + * SignalConversion generated from: '/Out1' + * Switch: '/Switch' + */ + rty_Out1[4] = rtb_FLF_NEW; + } + + /* End of Switch: '/Switch2' */ + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + * RelationalOperator: '/UpperRelop' + * Switch: '/Switch' + */ + if (rtb_FRF_NEW > rtb_c_g_aucFLOW_BI_FOOT_VALVE_MAX) { + /* Assignment: '/ [7]' incorporates: + * SignalConversion generated from: '/Out1' + */ + rty_Out1[6] = rtb_c_g_aucFLOW_BI_FOOT_VALVE_MAX; + } else if (rtb_FRF_NEW < rtb_c_g_aucFLOW_BI_FOOT_VALVE_MIN) { + /* Switch: '/Switch' incorporates: + * Assignment: '/ [7]' + * SignalConversion generated from: '/Out1' + */ + rty_Out1[6] = rtb_c_g_aucFLOW_BI_FOOT_VALVE_MIN; + } else { + /* Assignment: '/ [7]' incorporates: + * SignalConversion generated from: '/Out1' + * Switch: '/Switch' + */ + rty_Out1[6] = rtb_FRF_NEW; + } + + /* End of Switch: '/Switch2' */ +} + +/* + * Output and update for atomic system: + * '/g_assFLOW_BI_AMB_TGT' + * '/g_assFLOW_BI_AMB_TGT' + * '/g_assFLOW_BI_AMB_TGT' + * '/g_assFLOW_BI_AMB_TGT' + */ +void g_assFLOW_BI_AMB_TGT_e(uint8_t rtu_LVL, int16_t + *rty_c_g_assFLOW_BI2_AMB_TGT) +{ + int32_t tmp; + + /* : c_g_assFLOW_BI2_AMB_TGT = g_assFLOW_B2I_AMB_TGT(LVL + 1); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + *rty_c_g_assFLOW_BI2_AMB_TGT = g_assFLOW_B2I_AMB_TGT[tmp - 1]; +} + +/* + * Output and update for action system: + * '/Bilevel2' + * '/Bilevel2' + */ +void Bilevel2(int16_t rtu_Amb_Fb, uint8_t rtu_LVL, uint16_t rty_Out1[9], uint8_t + rtu_setTempFL, uint8_t rtu_setTempFR) +{ + int32_t tmp; + int32_t tmp_0; + int16_t rtb_u_jo; + uint16_t rtb_FLF_NEW; + uint16_t rtb_FRF_NEW; + uint16_t rtb_Switch2_if_idx_0; + uint16_t rtb_Switch2_if_idx_1; + uint16_t rtb_Switch2_p4_0; + int8_t rtb_X_b; + uint8_t rtb_c_g_aucFLOW_BI2_FOOT_VALVE_MAX; + uint8_t rtb_c_g_aucFLOW_BI2_FOOT_VALVE_MAX_l; + uint8_t rtb_c_g_aucFLOW_BI2_FOOT_VALVE_MIN; + uint8_t rtb_c_g_aucFLOW_BI2_FOOT_VALVE_MIN_l; + uint8_t rtb_c_g_aucFLOW_BI2_VENT_VALVE_MAX; + uint8_t rtb_c_g_aucFLOW_BI2_VENT_VALVE_MAX_k; + uint8_t rtb_c_g_aucFLOW_BI2_VENT_VALVE_MIN; + uint8_t rtb_c_g_aucFLOW_BI2_VENT_VALVE_MIN_f; + + /* MATLAB Function: '/get_tg_FLL_for_LVL' */ + /* : c_g_assFLOW_BI2_TEMP_TGT = g_assFLOW_BI2_TEMP_TGT(LVL + 1); */ + get_tg_FLL_for_LVL(rtu_LVL, rtu_setTempFL, &rtb_u_jo); + + /* MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + /* Sum: '/ 1' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + */ + rtb_u_jo = (int16_t)(g_assFLOW_BI2_TEMP_TGT[tmp_0 - 1] - rtb_u_jo); + + /* Gain: '/Gain6' */ + tmp_0 = 13107 * rtb_u_jo; + rtb_X_b = (int8_t)(((((uint32_t)tmp_0 & 65536U) != 0U) && ((((uint32_t)tmp_0 & + 65535U) != 0U) || (tmp_0 > 0))) + (tmp_0 >> 17)); + + /* Switch: '/Switch1' incorporates: + * Gain: '/Gain6' + * Sum: '/Add' + */ + /* : c_g_aucFLOW_BI2_FOOT_PLUS = g_aucFLOW_BI2_FOOT_PLUS(LVL + 1); */ + if (rtb_X_b >= 0) { + rtb_FLF_NEW = rty_Out1[4]; + } else { + /* MATLAB Function: '/g_aucFLOW_BI_FOOT_PLUS_LEFT' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + /* Gain: '/Gain6' incorporates: + * MATLAB Function: '/g_aucFLOW_BI_FOOT_PLUS_LEFT' + * Product: '/Product3' + */ + tmp_0 = g_aucFLOW_BI2_FOOT_PLUS[tmp_0 - 1] * rtb_X_b * 13107; + rtb_FLF_NEW = (uint16_t)((int16_t)rty_Out1[4] - (int8_t)(((((uint32_t)tmp_0 + & 65536U) != 0U) && (((uint32_t)tmp_0 & 65535U) != 0U)) + (tmp_0 >> 17))); + } + + /* End of Switch: '/Switch1' */ + + /* MATLAB Function: '/g_aucFLOW_BI_FOOT_VALVE_MAX1' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + */ + /* : c_g_aucFLOW_BI2_FOOT_VALVE_MAX = g_aucFLOW_BI2_FOOT_VALVE_MAX(LVL + 1); */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + rtb_c_g_aucFLOW_BI2_FOOT_VALVE_MAX_l = g_aucFLOW_BI2_FOOT_VALVE_MAX[tmp_0 - 1]; + + /* End of MATLAB Function: '/g_aucFLOW_BI_FOOT_VALVE_MAX1' */ + + /* MATLAB Function: '/g_aucFLOW_BI_FOOT_VALVE_MIN1' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + */ + /* : c_g_aucFLOW_BI2_FOOT_VALVE_MIN = g_aucFLOW_BI2_FOOT_VALVE_MIN(LVL + 1); */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + rtb_c_g_aucFLOW_BI2_FOOT_VALVE_MIN = g_aucFLOW_BI2_FOOT_VALVE_MIN[tmp_0 - 1]; + + /* End of MATLAB Function: '/g_aucFLOW_BI_FOOT_VALVE_MIN1' */ + + /* MATLAB Function: '/get_tg_FLL_for_LVL' */ + /* : c_g_assFLOW_BI2_TEMP_TGT = g_assFLOW_BI2_TEMP_TGT(LVL + 1 + 6); */ + get_tg_FLL_for_LVL_j(rtu_LVL, rtu_setTempFR, &rtb_u_jo); + + /* MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_RIGHT' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + tmp = (int32_t)((uint32_t)tmp_0 + 6U); + if ((uint32_t)tmp_0 + 6U > 255U) { + tmp = 255; + } + + /* Sum: '/ 1' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_RIGHT' + */ + rtb_u_jo = (int16_t)(g_assFLOW_BI2_TEMP_TGT[tmp - 1] - rtb_u_jo); + + /* Gain: '/Gain6' */ + tmp_0 = 13107 * rtb_u_jo; + rtb_X_b = (int8_t)(((((uint32_t)tmp_0 & 65536U) != 0U) && ((((uint32_t)tmp_0 & + 65535U) != 0U) || (tmp_0 > 0))) + (tmp_0 >> 17)); + + /* Switch: '/Switch3' incorporates: + * Gain: '/Gain7' + * Sum: '/Add1' + */ + /* : c_g_aucFLOW_BI2_FOOT_PLUS = g_aucFLOW_BI2_FOOT_PLUS(LVL + 1 + 6); */ + if (rtb_X_b >= 0) { + rtb_FRF_NEW = rty_Out1[6]; + } else { + /* MATLAB Function: '/g_aucFLOW_BI_FOOT_PLUS_RIGHT' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + tmp = (int32_t)((uint32_t)tmp_0 + 6U); + if ((uint32_t)tmp_0 + 6U > 255U) { + tmp = 255; + } + + /* Gain: '/Gain7' incorporates: + * MATLAB Function: '/g_aucFLOW_BI_FOOT_PLUS_RIGHT' + * Product: '/Product4' + */ + tmp_0 = g_aucFLOW_BI2_FOOT_PLUS[tmp - 1] * rtb_X_b * 13107; + rtb_FRF_NEW = (uint16_t)((int16_t)rty_Out1[6] - (int8_t)(((((uint32_t)tmp_0 + & 65536U) != 0U) && (((uint32_t)tmp_0 & 65535U) != 0U)) + (tmp_0 >> 17))); + } + + /* End of Switch: '/Switch3' */ + + /* MATLAB Function: '/g_aucFLOW_BI_FOOT_VALVE_MAX2' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + */ + /* : c_g_aucFLOW_BI2_FOOT_VALVE_MAX = g_aucFLOW_BI2_FOOT_VALVE_MAX(LVL + 1 + 6); */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + tmp = (int32_t)((uint32_t)tmp_0 + 6U); + if ((uint32_t)tmp_0 + 6U > 255U) { + tmp = 255; + } + + rtb_c_g_aucFLOW_BI2_FOOT_VALVE_MAX = g_aucFLOW_BI2_FOOT_VALVE_MAX[tmp - 1]; + + /* End of MATLAB Function: '/g_aucFLOW_BI_FOOT_VALVE_MAX2' */ + + /* MATLAB Function: '/g_aucFLOW_BI_FOOT_VALVE_MIN2' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + */ + /* : c_g_aucFLOW_BI2_FOOT_VALVE_MIN = g_aucFLOW_BI2_FOOT_VALVE_MIN(LVL + 1 + 6); */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + tmp = (int32_t)((uint32_t)tmp_0 + 6U); + if ((uint32_t)tmp_0 + 6U > 255U) { + tmp = 255; + } + + rtb_c_g_aucFLOW_BI2_FOOT_VALVE_MIN_l = g_aucFLOW_BI2_FOOT_VALVE_MIN[tmp - 1]; + + /* End of MATLAB Function: '/g_aucFLOW_BI_FOOT_VALVE_MIN2' */ + + /* MATLAB Function: '/g_assFLOW_BI_AMB_TGT' */ + /* : c_g_aucFLOW_BI2_VENT_PLUS = g_aucFLOW_BI2_VENT_PLUS(LVL + 1); */ + g_assFLOW_BI_AMB_TGT_e(rtu_LVL, &rtb_u_jo); + + /* MATLAB Function: '/g_aucFLOW_BI_VENT_PLUS' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + /* Gain: '/Gain2' incorporates: + * Sum: '/deg' + */ + tmp = (int16_t)(rtb_u_jo - rtu_Amb_Fb) * 13107; + + /* Product: '/' incorporates: + * Gain: '/Gain' + * Gain: '/Gain2' + * MATLAB Function: '/g_aucFLOW_BI_VENT_PLUS' + */ + rtb_u_jo = (int16_t)((int8_t)(((((uint32_t)tmp & 65536U) != 0U) && + ((((uint32_t)tmp & 65535U) != 0U) || (tmp > 0))) + (tmp >> 17)) * (int32_t) + ((g_aucFLOW_BI2_VENT_PLUS[tmp_0 - 1] * 205U + 1024U) >> + 11)); + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * Sum: '/ ' + * Switch: '/Switch2' + */ + rtb_Switch2_if_idx_0 = (uint16_t)((uint16_t)((rty_Out1[0] - rtb_u_jo) >> 1) << + 1); + rtb_Switch2_if_idx_1 = (uint16_t)((uint16_t)((rty_Out1[1] - rtb_u_jo) >> 1) << + 1); + + /* MATLAB Function: '/g_aucFLOW_BI_VENT_VALVE_MAX' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + */ + /* : c_g_aucFLOW_BI2_VENT_VALVE_MAX = g_aucFLOW_BI2_VENT_VALVE_MAX(LVL + 1); */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + rtb_c_g_aucFLOW_BI2_VENT_VALVE_MAX_k = g_aucFLOW_BI2_VENT_VALVE_MAX[tmp_0 - 1]; + + /* End of MATLAB Function: '/g_aucFLOW_BI_VENT_VALVE_MAX' */ + + /* MATLAB Function: '/g_aucFLOW_BI_VENT_VALVE_MIN' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + */ + /* : c_g_aucFLOW_BI2_VENT_VALVE_MIN = g_aucFLOW_BI2_VENT_VALVE_MIN(LVL + 1); */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + rtb_c_g_aucFLOW_BI2_VENT_VALVE_MIN_f = g_aucFLOW_BI2_VENT_VALVE_MIN[tmp_0 - 1]; + + /* End of MATLAB Function: '/g_aucFLOW_BI_VENT_VALVE_MIN' */ + + /* MATLAB Function: '/g_assFLOW_BI_AMB_TGT' */ + /* : c_g_aucFLOW_BI2_VENT_PLUS = g_aucFLOW_BI2_VENT_PLUS(LVL + 1 + 6); */ + g_assFLOW_BI_AMB_TGT_e(rtu_LVL, &rtb_u_jo); + + /* MATLAB Function: '/g_aucFLOW_BI_VENT_PLUS' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + tmp = (int32_t)((uint32_t)tmp_0 + 6U); + if ((uint32_t)tmp_0 + 6U > 255U) { + tmp = 255; + } + + /* Gain: '/Gain2' incorporates: + * Sum: '/deg' + */ + tmp_0 = (int16_t)(rtb_u_jo - rtu_Amb_Fb) * 13107; + + /* Product: '/' incorporates: + * Gain: '/Gain' + * Gain: '/Gain2' + * MATLAB Function: '/g_aucFLOW_BI_VENT_PLUS' + */ + rtb_u_jo = (int16_t)((int8_t)(((((uint32_t)tmp_0 & 65536U) != 0U) && + ((((uint32_t)tmp_0 & 65535U) != 0U) || (tmp_0 > 0))) + (tmp_0 >> 17)) * + (int32_t)((g_aucFLOW_BI2_VENT_PLUS[tmp - 1] * 205U + + 1024U) >> 11)); + + /* MATLAB Function: '/g_aucFLOW_BI_VENT_VALVE_MAX' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + */ + /* : c_g_aucFLOW_BI2_VENT_VALVE_MAX = g_aucFLOW_BI2_VENT_VALVE_MAX(LVL + 1 + 6); */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + tmp = (int32_t)((uint32_t)tmp_0 + 6U); + if ((uint32_t)tmp_0 + 6U > 255U) { + tmp = 255; + } + + rtb_c_g_aucFLOW_BI2_VENT_VALVE_MAX = g_aucFLOW_BI2_VENT_VALVE_MAX[tmp - 1]; + + /* End of MATLAB Function: '/g_aucFLOW_BI_VENT_VALVE_MAX' */ + + /* MATLAB Function: '/g_aucFLOW_BI_VENT_VALVE_MIN' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + */ + /* : c_g_aucFLOW_BI2_VENT_VALVE_MIN = g_aucFLOW_BI2_VENT_VALVE_MIN(LVL + 1 + 6); */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + tmp = (int32_t)((uint32_t)tmp_0 + 6U); + if ((uint32_t)tmp_0 + 6U > 255U) { + tmp = 255; + } + + rtb_c_g_aucFLOW_BI2_VENT_VALVE_MIN = g_aucFLOW_BI2_VENT_VALVE_MIN[tmp - 1]; + + /* End of MATLAB Function: '/g_aucFLOW_BI_VENT_VALVE_MIN' */ + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * Sum: '/ ' + * Switch: '/Switch2' + */ + rtb_Switch2_p4_0 = (uint16_t)((uint16_t)((rty_Out1[0] - rtb_u_jo) >> 1) << 1); + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + * RelationalOperator: '/UpperRelop' + * Switch: '/Switch' + */ + if (rtb_Switch2_if_idx_0 > rtb_c_g_aucFLOW_BI2_VENT_VALVE_MAX_k) { + /* Assignment: '/ [1-2]' incorporates: + * SignalConversion generated from: '/Out1' + */ + rty_Out1[0] = rtb_c_g_aucFLOW_BI2_VENT_VALVE_MAX_k; + } else if (rtb_Switch2_if_idx_0 < rtb_c_g_aucFLOW_BI2_VENT_VALVE_MIN_f) { + /* Switch: '/Switch' incorporates: + * Assignment: '/ [1-2]' + * SignalConversion generated from: '/Out1' + */ + rty_Out1[0] = rtb_c_g_aucFLOW_BI2_VENT_VALVE_MIN_f; + } else { + /* Assignment: '/ [1-2]' incorporates: + * SignalConversion generated from: '/Out1' + * Switch: '/Switch' + */ + rty_Out1[0] = rtb_Switch2_if_idx_0; + } + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + * RelationalOperator: '/UpperRelop' + * Switch: '/Switch' + */ + if (rtb_Switch2_p4_0 > rtb_c_g_aucFLOW_BI2_VENT_VALVE_MAX) { + /* Assignment: '/ [3-4]' incorporates: + * SignalConversion generated from: '/Out1' + */ + rty_Out1[2] = rtb_c_g_aucFLOW_BI2_VENT_VALVE_MAX; + } else if (rtb_Switch2_p4_0 < rtb_c_g_aucFLOW_BI2_VENT_VALVE_MIN) { + /* Switch: '/Switch' incorporates: + * Assignment: '/ [3-4]' + * SignalConversion generated from: '/Out1' + */ + rty_Out1[2] = rtb_c_g_aucFLOW_BI2_VENT_VALVE_MIN; + } else { + /* Assignment: '/ [3-4]' incorporates: + * SignalConversion generated from: '/Out1' + * Switch: '/Switch' + */ + rty_Out1[2] = rtb_Switch2_p4_0; + } + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * Sum: '/ ' + * Switch: '/Switch2' + */ + rtb_Switch2_p4_0 = (uint16_t)((uint16_t)((rty_Out1[1] - rtb_u_jo) >> 1) << 1); + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + * RelationalOperator: '/UpperRelop' + * Switch: '/Switch' + */ + if (rtb_Switch2_if_idx_1 > rtb_c_g_aucFLOW_BI2_VENT_VALVE_MAX_k) { + /* Assignment: '/ [1-2]' incorporates: + * SignalConversion generated from: '/Out1' + */ + rty_Out1[1] = rtb_c_g_aucFLOW_BI2_VENT_VALVE_MAX_k; + } else if (rtb_Switch2_if_idx_1 < rtb_c_g_aucFLOW_BI2_VENT_VALVE_MIN_f) { + /* Switch: '/Switch' incorporates: + * Assignment: '/ [1-2]' + * SignalConversion generated from: '/Out1' + */ + rty_Out1[1] = rtb_c_g_aucFLOW_BI2_VENT_VALVE_MIN_f; + } else { + /* Assignment: '/ [1-2]' incorporates: + * SignalConversion generated from: '/Out1' + * Switch: '/Switch' + */ + rty_Out1[1] = rtb_Switch2_if_idx_1; + } + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + * RelationalOperator: '/UpperRelop' + * Switch: '/Switch' + */ + if (rtb_Switch2_p4_0 > rtb_c_g_aucFLOW_BI2_VENT_VALVE_MAX) { + /* Assignment: '/ [3-4]' incorporates: + * SignalConversion generated from: '/Out1' + */ + rty_Out1[3] = rtb_c_g_aucFLOW_BI2_VENT_VALVE_MAX; + } else if (rtb_Switch2_p4_0 < rtb_c_g_aucFLOW_BI2_VENT_VALVE_MIN) { + /* Switch: '/Switch' incorporates: + * Assignment: '/ [3-4]' + * SignalConversion generated from: '/Out1' + */ + rty_Out1[3] = rtb_c_g_aucFLOW_BI2_VENT_VALVE_MIN; + } else { + /* Assignment: '/ [3-4]' incorporates: + * SignalConversion generated from: '/Out1' + * Switch: '/Switch' + */ + rty_Out1[3] = rtb_Switch2_p4_0; + } + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + * RelationalOperator: '/UpperRelop' + * Switch: '/Switch' + */ + if (rtb_FLF_NEW > rtb_c_g_aucFLOW_BI2_FOOT_VALVE_MAX_l) { + /* Assignment: '/ [5]' incorporates: + * SignalConversion generated from: '/Out1' + */ + rty_Out1[4] = rtb_c_g_aucFLOW_BI2_FOOT_VALVE_MAX_l; + } else if (rtb_FLF_NEW < rtb_c_g_aucFLOW_BI2_FOOT_VALVE_MIN) { + /* Switch: '/Switch' incorporates: + * Assignment: '/ [5]' + * SignalConversion generated from: '/Out1' + */ + rty_Out1[4] = rtb_c_g_aucFLOW_BI2_FOOT_VALVE_MIN; + } else { + /* Assignment: '/ [5]' incorporates: + * SignalConversion generated from: '/Out1' + * Switch: '/Switch' + */ + rty_Out1[4] = rtb_FLF_NEW; + } + + /* End of Switch: '/Switch2' */ + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + * RelationalOperator: '/UpperRelop' + * Switch: '/Switch' + */ + if (rtb_FRF_NEW > rtb_c_g_aucFLOW_BI2_FOOT_VALVE_MAX) { + /* Assignment: '/ [7]' incorporates: + * SignalConversion generated from: '/Out1' + */ + rty_Out1[6] = rtb_c_g_aucFLOW_BI2_FOOT_VALVE_MAX; + } else if (rtb_FRF_NEW < rtb_c_g_aucFLOW_BI2_FOOT_VALVE_MIN_l) { + /* Switch: '/Switch' incorporates: + * Assignment: '/ [7]' + * SignalConversion generated from: '/Out1' + */ + rty_Out1[6] = rtb_c_g_aucFLOW_BI2_FOOT_VALVE_MIN_l; + } else { + /* Assignment: '/ [7]' incorporates: + * SignalConversion generated from: '/Out1' + * Switch: '/Switch' + */ + rty_Out1[6] = rtb_FRF_NEW; + } + + /* End of Switch: '/Switch2' */ +} + +/* + * Output and update for atomic system: + * '/g_aucFLOW_AF_FOOT_VALVE_MAX' + * '/g_aucFLOW_AF_FOOT_VALVE_MAX' + * '/g_aucFLOW_AF_FOOT_VALVE_MAX' + * '/g_aucFLOW_AF_FOOT_VALVE_MAX' + */ +void g_aucFLOW_AF_FOOT_VALVE_MAX_e(uint8_t rtu_LVL, uint8_t + *rty_c_g_aucFLOW_AF_FOOT_VALVE_MAX) +{ + int32_t tmp; + + /* : c_g_aucFLOW_AF_FOOT_VALVE_MAX = g_aucFLOW_AF_FOOT_VALVE_MAX(LVL + 1); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + *rty_c_g_aucFLOW_AF_FOOT_VALVE_MAX = g_aucFLOW_AF_FOOT_VALVE_MAX[tmp - 1]; +} + +/* + * Output and update for atomic system: + * '/g_assFLOW_AF_AMB_TGT' + * '/g_assFLOW_AF_AMB_TGT' + * '/g_assFLOW_AF_AMB_TGT' + * '/g_assFLOW_AF_AMB_TGT' + * '/g_assFLOW_AF_AMB_TGT' + * '/g_assFLOW_AF_AMB_TGT' + */ +void g_assFLOW_AF_AMB_TGT_g(uint8_t rtu_LVL, int16_t *rty_c_g_assFLOW_AF_AMB_TGT) +{ + int32_t tmp; + + /* : c_g_assFLOW_AF_AMB_TGT = g_assFLOW_AF_AMB_TGT(LVL + 1); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + *rty_c_g_assFLOW_AF_AMB_TGT = g_assFLOW_AF_AMB_TGT[tmp - 1]; +} + +/* + * Output and update for action system: + * '/Afoot' + * '/Afoot' + */ +void Afoot(int16_t rtu_Amb_Fb, uint8_t rtu_LVL, uint16_t rty_Out1[9], uint8_t + rtu_setTempFL, uint8_t rtu_setTempFR) +{ + int32_t i; + int32_t tmp_0; + uint32_t qY; + int16_t tmp[78]; + int16_t rtb_deg_en; + uint16_t rtb_FLF_NEW; + uint16_t rtb_FRF_NEW; + uint16_t rtb_Switch2_ar_idx_0; + uint16_t rtb_Switch2_ar_idx_1; + uint16_t rtb_Switch2_j_idx_0; + uint16_t rtb_Switch2_j_idx_1; + int8_t rtb_X_c; + uint8_t rtb_c_g_aucFLOW_AF_FOOT_VALVE_MAX; + uint8_t rtb_c_g_aucFLOW_AF_VENT_VALVE_MAX_k; + + /* MATLAB Function: '/get_tg_for_LVL' */ + /* : c_g_aucFLOW_AF_BLR_AF_TGT = g_aucFLOW_AF_BLR_AF_TGT(LVL + 1); */ + /* : table = [ */ + /* : g_assVTG_FL_LV0; */ + /* : g_assVTG_FL_LV1; */ + /* : g_assVTG_FL_LV2; */ + /* : g_assVTG_FL_LV3; */ + /* : g_assVTG_FL_LV4; */ + /* : g_assVTG_FL_LV5 */ + /* : ]; */ + /* : vals = table(ambient_Lvl + 1, set_tmp - 16); */ + for (i = 0; i < 13; i++) { + tmp[6 * i] = g_assVTG_FL_LV0[i]; + tmp[6 * i + 1] = g_assVTG_FL_LV1[i]; + tmp[6 * i + 2] = g_assVTG_FL_LV2[i]; + tmp[6 * i + 3] = g_assVTG_FL_LV3[i]; + tmp[6 * i + 4] = g_assVTG_FL_LV4[i]; + tmp[6 * i + 5] = g_assVTG_FL_LV5[i]; + } + + /* MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' */ + i = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + i = 255; + } + + /* MATLAB Function: '/get_tg_for_LVL' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + /* MW:begin MISRA2012:D4.1 CERT-C:INT30-C 'Justifying MISRA CPP rule violation' */ + qY = rtu_setTempFL - 16U; + + /* MW:end MISRA2012:D4.1 CERT-C:INT30-C */ + if (rtu_setTempFL - 16U > rtu_setTempFL) { + qY = 0U; + } + + /* Gain: '/Gain6' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + * MATLAB Function: '/get_tg_for_LVL' + * Sum: '/ 1' + */ + i = (int16_t)(g_aucFLOW_AF_BLR_AF_TGT[i - 1] - tmp[(((int32_t)qY - 1) * 6 + + tmp_0) - 1]) * 13107; + rtb_X_c = (int8_t)(((((uint32_t)i & 65536U) != 0U) && ((((uint32_t)i & 65535U) + != 0U) || (i > 0))) + (i >> 17)); + + /* Switch: '/Switch1' incorporates: + * Gain: '/Gain6' + * Sum: '/Add' + */ + /* : c_g_aucFLOW_AF_FOOT_PLUS = g_aucFLOW_AF_FOOT_PLUS(LVL + 1); */ + if (rtb_X_c >= 0) { + rtb_FLF_NEW = rty_Out1[4]; + } else { + /* MATLAB Function: '/g_aucFLOW_AF_FOOT_PLUS' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + */ + i = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + i = 255; + } + + /* Gain: '/Gain6' incorporates: + * MATLAB Function: '/g_aucFLOW_AF_FOOT_PLUS' + * Product: '/Product3' + */ + i = g_aucFLOW_AF_FOOT_PLUS[i - 1] * rtb_X_c * 13107; + rtb_FLF_NEW = (uint16_t)((int16_t)rty_Out1[4] - (int8_t)(((((uint32_t)i & + 65536U) != 0U) && (((uint32_t)i & 65535U) != 0U)) + (i >> 17))); + } + + /* End of Switch: '/Switch1' */ + + /* MATLAB Function: '/g_aucFLOW_AF_FOOT_VALVE_MAX' */ + g_aucFLOW_AF_FOOT_VALVE_MAX_e(rtu_LVL, &rtb_c_g_aucFLOW_AF_FOOT_VALVE_MAX); + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + */ + if (rtb_FLF_NEW > rtb_c_g_aucFLOW_AF_FOOT_VALVE_MAX) { + rtb_FLF_NEW = rtb_c_g_aucFLOW_AF_FOOT_VALVE_MAX; + } + + /* End of Switch: '/Switch2' */ + + /* MATLAB Function: '/get_vtg_for_LVL' */ + /* : c_g_aucFLOW_AF_BLR_AF_TGT = g_aucFLOW_AF_BLR_AF_TGT(LVL + 1); */ + /* : table = [ */ + /* : g_assVTG_FR_LV0; */ + /* : g_assVTG_FR_LV1; */ + /* : g_assVTG_FR_LV2; */ + /* : g_assVTG_FR_LV3; */ + /* : g_assVTG_FR_LV4; */ + /* : g_assVTG_FR_LV5 */ + /* : ]; */ + /* : vals = table(ambient_Lvl + 1, set_tmp - 16); */ + for (i = 0; i < 13; i++) { + tmp[6 * i] = g_assVTG_FR_LV0[i]; + tmp[6 * i + 1] = g_assVTG_FR_LV1[i]; + tmp[6 * i + 2] = g_assVTG_FR_LV2[i]; + tmp[6 * i + 3] = g_assVTG_FR_LV3[i]; + tmp[6 * i + 4] = g_assVTG_FR_LV4[i]; + tmp[6 * i + 5] = g_assVTG_FR_LV5[i]; + } + + /* MATLAB Function: '/g_aucFLOW_AF_BLR_AF_TGT' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + */ + i = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + i = 255; + } + + /* MATLAB Function: '/get_vtg_for_LVL' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + qY = rtu_setTempFR - 16U; + if (rtu_setTempFR - 16U > rtu_setTempFR) { + qY = 0U; + } + + /* Sum: '/ 1' incorporates: + * MATLAB Function: '/g_aucFLOW_AF_BLR_AF_TGT' + * MATLAB Function: '/get_vtg_for_LVL' + */ + rtb_deg_en = (int16_t)(g_aucFLOW_AF_BLR_AF_TGT[i - 1] - tmp[(((int32_t)qY - 1) + * 6 + tmp_0) - 1]); + + /* Gain: '/Gain6' */ + i = 13107 * rtb_deg_en; + rtb_X_c = (int8_t)(((((uint32_t)i & 65536U) != 0U) && ((((uint32_t)i & 65535U) + != 0U) || (i > 0))) + (i >> 17)); + + /* Switch: '/Switch3' incorporates: + * Gain: '/Gain7' + * Sum: '/Add1' + */ + /* : c_g_aucFLOW_AF_FOOT_PLUS = g_aucFLOW_AF_FOOT_PLUS(LVL + 1 + 6); */ + if (rtb_X_c >= 0) { + rtb_FRF_NEW = rty_Out1[6]; + } else { + /* MATLAB Function: '/g_aucFLOW_AF_FOOT_PLUS' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + */ + i = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + i = 255; + } + + tmp_0 = (int32_t)((uint32_t)i + 6U); + if ((uint32_t)i + 6U > 255U) { + tmp_0 = 255; + } + + /* Gain: '/Gain7' incorporates: + * MATLAB Function: '/g_aucFLOW_AF_FOOT_PLUS' + * Product: '/Product4' + */ + i = g_aucFLOW_AF_FOOT_PLUS[tmp_0 - 1] * rtb_X_c * 13107; + rtb_FRF_NEW = (uint16_t)((int16_t)rty_Out1[6] - (int8_t)(((((uint32_t)i & + 65536U) != 0U) && (((uint32_t)i & 65535U) != 0U)) + (i >> 17))); + } + + /* End of Switch: '/Switch3' */ + + /* MATLAB Function: '/g_aucFLOW_AF_FOOT_VALVE_MAX' */ + g_aucFLOW_AF_FOOT_VALVE_MAX_e(rtu_LVL, &rtb_c_g_aucFLOW_AF_FOOT_VALVE_MAX); + + /* MATLAB Function: '/g_assFLOW_AF_AMB_TGT' */ + /* : c_g_aucFLOW_AF_VENT_PLUS = g_aucFLOW_AF_VENT_PLUS(LVL + 1); */ + g_assFLOW_AF_AMB_TGT_g(rtu_LVL, &rtb_deg_en); + + /* Sum: '/deg' */ + rtb_deg_en -= rtu_Amb_Fb; + + /* Gain: '/Gain2' */ + i = 13107 * rtb_deg_en; + rtb_X_c = (int8_t)(((((uint32_t)i & 65536U) != 0U) && ((((uint32_t)i & 65535U) + != 0U) || (i > 0))) + (i >> 17)); + + /* Switch: '/if (deg < 0)' incorporates: + * Sum: '/ ' + * Switch: '/Switch2' + */ + if (rtb_X_c >= 0) { + rtb_Switch2_ar_idx_0 = rty_Out1[0]; + rtb_Switch2_ar_idx_1 = rty_Out1[1]; + } else { + /* MATLAB Function: '/g_aucFLOW_AF_VENT_PLUS' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + */ + i = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + i = 255; + } + + /* Product: '/' incorporates: + * Gain: '/Gain' + * MATLAB Function: '/g_aucFLOW_AF_VENT_PLUS' + */ + rtb_deg_en = (int16_t)((int32_t)((g_aucFLOW_AF_VENT_PLUS[i - 1] * 205U + + 1024U) >> 11) * rtb_X_c); + rtb_Switch2_ar_idx_0 = (uint16_t)(rty_Out1[0] - rtb_deg_en); + rtb_Switch2_ar_idx_1 = (uint16_t)(rty_Out1[1] - rtb_deg_en); + } + + /* End of Switch: '/if (deg < 0)' */ + + /* MATLAB Function: '/g_aucFLOW_AF_VENT_VALVE_MAX' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + */ + /* : c_g_aucFLOW_AF_VENT_VALVE_MAX = g_aucFLOW_AF_VENT_VALVE_MAX(LVL + 1); */ + i = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + i = 255; + } + + rtb_c_g_aucFLOW_AF_VENT_VALVE_MAX_k = g_aucFLOW_AF_VENT_VALVE_MAX[i - 1]; + + /* End of MATLAB Function: '/g_aucFLOW_AF_VENT_VALVE_MAX' */ + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + */ + if (rtb_Switch2_ar_idx_0 > rtb_c_g_aucFLOW_AF_VENT_VALVE_MAX_k) { + rtb_Switch2_ar_idx_0 = rtb_c_g_aucFLOW_AF_VENT_VALVE_MAX_k; + } + + if (rtb_Switch2_ar_idx_1 > rtb_c_g_aucFLOW_AF_VENT_VALVE_MAX_k) { + rtb_Switch2_ar_idx_1 = rtb_c_g_aucFLOW_AF_VENT_VALVE_MAX_k; + } + + /* End of Switch: '/Switch2' */ + + /* MATLAB Function: '/g_assFLOW_AF_AMB_TGT' */ + /* : c_g_aucFLOW_AF_VENT_PLUS = g_aucFLOW_AF_VENT_PLUS(LVL + 1 + 6); */ + g_assFLOW_AF_AMB_TGT_g(rtu_LVL, &rtb_deg_en); + + /* Gain: '/Gain2' incorporates: + * Sum: '/deg' + */ + i = (int16_t)(rtb_deg_en - rtu_Amb_Fb) * 13107; + rtb_X_c = (int8_t)(((((uint32_t)i & 65536U) != 0U) && ((((uint32_t)i & 65535U) + != 0U) || (i > 0))) + (i >> 17)); + + /* Switch: '/if (deg < 0)' incorporates: + * DataTypeConversion: '/Data Type Conversion' + * Sum: '/ ' + * Switch: '/Switch2' + */ + if (rtb_X_c >= 0) { + rtb_Switch2_j_idx_0 = rty_Out1[0]; + rtb_Switch2_j_idx_1 = rty_Out1[1]; + } else { + /* MATLAB Function: '/g_aucFLOW_AF_VENT_PLUS' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + */ + i = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + i = 255; + } + + tmp_0 = (int32_t)((uint32_t)i + 6U); + if ((uint32_t)i + 6U > 255U) { + tmp_0 = 255; + } + + /* Product: '/' incorporates: + * Gain: '/Gain' + * MATLAB Function: '/g_aucFLOW_AF_VENT_PLUS' + */ + rtb_deg_en = (int16_t)((int32_t)((g_aucFLOW_AF_VENT_PLUS[tmp_0 - 1] * 205U + + 1024U) >> 11) * rtb_X_c); + rtb_Switch2_j_idx_0 = (uint16_t)((int16_t)rty_Out1[0] - rtb_deg_en); + rtb_Switch2_j_idx_1 = (uint16_t)((int16_t)rty_Out1[1] - rtb_deg_en); + } + + /* End of Switch: '/if (deg < 0)' */ + + /* MATLAB Function: '/g_aucFLOW_AF_VENT_VALVE_MAX' incorporates: + * MATLAB Function: '/g_assFLOW_BI2_TEMP_TGT_LEFT' + */ + /* : c_g_aucFLOW_AF_VENT_VALVE_MAX = g_aucFLOW_AF_VENT_VALVE_MAX(LVL + 1 + 6); */ + i = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + i = 255; + } + + tmp_0 = (int32_t)((uint32_t)i + 6U); + if ((uint32_t)i + 6U > 255U) { + tmp_0 = 255; + } + + rtb_c_g_aucFLOW_AF_VENT_VALVE_MAX_k = g_aucFLOW_AF_VENT_VALVE_MAX[tmp_0 - 1]; + + /* End of MATLAB Function: '/g_aucFLOW_AF_VENT_VALVE_MAX' */ + + /* Assignment: '/ [1-2]' incorporates: + * SignalConversion generated from: '/Out1' + * Switch: '/Switch2' + */ + rty_Out1[0] = rtb_Switch2_ar_idx_0; + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + */ + if (rtb_Switch2_j_idx_0 > rtb_c_g_aucFLOW_AF_VENT_VALVE_MAX_k) { + /* Assignment: '/ [3-4]' incorporates: + * SignalConversion generated from: '/Out1' + */ + rty_Out1[2] = rtb_c_g_aucFLOW_AF_VENT_VALVE_MAX_k; + } else { + /* Assignment: '/ [3-4]' incorporates: + * SignalConversion generated from: '/Out1' + */ + rty_Out1[2] = rtb_Switch2_j_idx_0; + } + + /* Assignment: '/ [1-2]' incorporates: + * SignalConversion generated from: '/Out1' + * Switch: '/Switch2' + */ + rty_Out1[1] = rtb_Switch2_ar_idx_1; + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + */ + if (rtb_Switch2_j_idx_1 > rtb_c_g_aucFLOW_AF_VENT_VALVE_MAX_k) { + /* Assignment: '/ [3-4]' incorporates: + * SignalConversion generated from: '/Out1' + */ + rty_Out1[3] = rtb_c_g_aucFLOW_AF_VENT_VALVE_MAX_k; + } else { + /* Assignment: '/ [3-4]' incorporates: + * SignalConversion generated from: '/Out1' + */ + rty_Out1[3] = rtb_Switch2_j_idx_1; + } + + /* Assignment: '/ [5]' incorporates: + * SignalConversion generated from: '/Out1' + */ + rty_Out1[4] = rtb_FLF_NEW; + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + */ + if (rtb_FRF_NEW > rtb_c_g_aucFLOW_AF_FOOT_VALVE_MAX) { + /* Assignment: '/ [7]' incorporates: + * SignalConversion generated from: '/Out1' + */ + rty_Out1[6] = rtb_c_g_aucFLOW_AF_FOOT_VALVE_MAX; + } else { + /* Assignment: '/ [7]' incorporates: + * SignalConversion generated from: '/Out1' + * Switch: '/Switch' + */ + rty_Out1[6] = rtb_FRF_NEW; + } + + /* End of Switch: '/Switch2' */ +} + +/* + * Output and update for atomic system: + * '/g_aucFLOW_AFSM_FOOT_VALVE_MAX' + * '/g_aucFLOW_AF_FOOT_VALVE_MAX' + * '/g_aucFLOW_AFSM_FOOT_VALVE_MAX' + * '/g_aucFLOW_AF_FOOT_VALVE_MAX' + */ +void g_aucFLOW_AFSM_FOOT_VALVE_MAX_f(uint8_t rtu_LVL, uint8_t + *rty_c_g_aucFLOW_AFSM_FOOT_VALVE_MAX) +{ + int32_t tmp; + + /* : c_g_aucFLOW_AFSM_FOOT_VALVE_MAX = g_aucFLOW_AFSM_FOOT_VALVE_MAX(LVL + 1); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + *rty_c_g_aucFLOW_AFSM_FOOT_VALVE_MAX = g_aucFLOW_AFSM_FOOT_VALVE_MAX[tmp - 1]; +} + +/* + * Output and update for action system: + * '/Afoot_Summer' + * '/Afoot_Summer' + */ +void Afoot_Summer(int16_t rtu_Amb_Fb, uint8_t rtu_LVL, uint16_t rty_Out1[9], + uint8_t rtu_setTempFL, uint8_t rtu_setTempFR) +{ + int32_t tmp; + int32_t tmp_0; + int16_t rtb_deg_c; + uint16_t rtb_FLF_NEW; + uint16_t rtb_FRF_NEW; + uint16_t rtb_Switch2_j1_idx_0; + uint16_t rtb_Switch2_j1_idx_1; + uint16_t rtb_Switch2_lt_idx_0; + uint16_t rtb_Switch2_lt_idx_1; + int8_t rtb_X_m; + uint8_t rtb_c_g_aucFLOW_AFSM_FOOT_VALVE_MAX; + uint8_t rtb_c_g_aucFLOW_AFSM_VENT_VALVE_MAX_g; + + /* MATLAB Function: '/get_tg_for_LVL' */ + /* : c_g_assFLOW_AFSM_TEMP_TGT = g_assFLOW_AFSM_TEMP_TGT(LVL + 1); */ + get_tg_FLL_for_LVL(rtu_LVL, rtu_setTempFL, &rtb_deg_c); + + /* MATLAB Function: '/g_assFLOW_AFSM_TEMP_TGT_LEFT' */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + /* Sum: '/ 1' incorporates: + * MATLAB Function: '/g_assFLOW_AFSM_TEMP_TGT_LEFT' + */ + rtb_deg_c = (int16_t)(g_assFLOW_AFSM_TEMP_TGT[tmp_0 - 1] - rtb_deg_c); + + /* Gain: '/Gain6' */ + tmp_0 = 13107 * rtb_deg_c; + rtb_X_m = (int8_t)(((((uint32_t)tmp_0 & 65536U) != 0U) && ((((uint32_t)tmp_0 & + 65535U) != 0U) || (tmp_0 > 0))) + (tmp_0 >> 17)); + + /* Switch: '/Switch1' incorporates: + * Gain: '/Gain6' + * Sum: '/Add' + */ + /* : c_g_aucFLOW_AFSM_FOOT_PLUS = g_aucFLOW_AFSM_FOOT_PLUS(LVL + 1); */ + if (rtb_X_m >= 0) { + rtb_FLF_NEW = rty_Out1[4]; + } else { + /* MATLAB Function: '/g_aucFLOW_AFSM_FOOT_PLUS' incorporates: + * MATLAB Function: '/g_assFLOW_AFSM_TEMP_TGT_LEFT' + */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + /* Gain: '/Gain6' incorporates: + * MATLAB Function: '/g_aucFLOW_AFSM_FOOT_PLUS' + * Product: '/Product3' + */ + tmp_0 = g_aucFLOW_AFSM_FOOT_PLUS[tmp_0 - 1] * rtb_X_m * 13107; + rtb_FLF_NEW = (uint16_t)((int16_t)rty_Out1[4] - (int8_t)(((((uint32_t)tmp_0 + & 65536U) != 0U) && (((uint32_t)tmp_0 & 65535U) != 0U)) + (tmp_0 >> 17))); + } + + /* End of Switch: '/Switch1' */ + + /* MATLAB Function: '/g_aucFLOW_AFSM_FOOT_VALVE_MAX' */ + g_aucFLOW_AFSM_FOOT_VALVE_MAX_f(rtu_LVL, &rtb_c_g_aucFLOW_AFSM_FOOT_VALVE_MAX); + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + */ + if (rtb_FLF_NEW > rtb_c_g_aucFLOW_AFSM_FOOT_VALVE_MAX) { + rtb_FLF_NEW = rtb_c_g_aucFLOW_AFSM_FOOT_VALVE_MAX; + } + + /* End of Switch: '/Switch2' */ + + /* MATLAB Function: '/get_tg_FLL_for_LVL' */ + /* : c_g_assFLOW_AFSM_TEMP_TGT = g_assFLOW_AFSM_TEMP_TGT(LVL + 1 + 6); */ + get_tg_FLL_for_LVL_j(rtu_LVL, rtu_setTempFR, &rtb_deg_c); + + /* MATLAB Function: '/g_assFLOW_AFSM_TEMP_TGT' incorporates: + * MATLAB Function: '/g_assFLOW_AFSM_TEMP_TGT_LEFT' + */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + tmp = (int32_t)((uint32_t)tmp_0 + 6U); + if ((uint32_t)tmp_0 + 6U > 255U) { + tmp = 255; + } + + /* Gain: '/Gain6' incorporates: + * MATLAB Function: '/g_assFLOW_AFSM_TEMP_TGT' + * Sum: '/ 1' + */ + tmp_0 = (int16_t)(g_assFLOW_AFSM_TEMP_TGT[tmp - 1] - rtb_deg_c) * 13107; + rtb_X_m = (int8_t)(((((uint32_t)tmp_0 & 65536U) != 0U) && ((((uint32_t)tmp_0 & + 65535U) != 0U) || (tmp_0 > 0))) + (tmp_0 >> 17)); + + /* Switch: '/Switch3' incorporates: + * Gain: '/Gain7' + * Sum: '/Add1' + */ + /* : c_g_aucFLOW_AFSM_FOOT_PLUS = g_aucFLOW_AFSM_FOOT_PLUS(LVL + 1 + 6); */ + if (rtb_X_m >= 0) { + rtb_FRF_NEW = rty_Out1[6]; + } else { + /* MATLAB Function: '/g_aucFLOW_AFSM_FOOT_PLUS' incorporates: + * MATLAB Function: '/g_assFLOW_AFSM_TEMP_TGT_LEFT' + */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + tmp = (int32_t)((uint32_t)tmp_0 + 6U); + if ((uint32_t)tmp_0 + 6U > 255U) { + tmp = 255; + } + + /* Gain: '/Gain7' incorporates: + * MATLAB Function: '/g_aucFLOW_AFSM_FOOT_PLUS' + * Product: '/Product4' + */ + tmp_0 = g_aucFLOW_AFSM_FOOT_PLUS[tmp - 1] * rtb_X_m * 13107; + rtb_FRF_NEW = (uint16_t)((int16_t)rty_Out1[6] - (int8_t)(((((uint32_t)tmp_0 + & 65536U) != 0U) && (((uint32_t)tmp_0 & 65535U) != 0U)) + (tmp_0 >> 17))); + } + + /* End of Switch: '/Switch3' */ + + /* MATLAB Function: '/g_aucFLOW_AF_FOOT_VALVE_MAX' */ + g_aucFLOW_AFSM_FOOT_VALVE_MAX_f(rtu_LVL, &rtb_c_g_aucFLOW_AFSM_FOOT_VALVE_MAX); + + /* MATLAB Function: '/g_assFLOW_AFSM_AMB_TGT' incorporates: + * MATLAB Function: '/g_assFLOW_AFSM_TEMP_TGT_LEFT' + */ + /* : c_g_aucFLOW_AFSM_VENT_PLUS = g_aucFLOW_AFSM_VENT_PLUS(LVL + 1); */ + /* : c_g_assFLOW_AFSM_AMB_TGT = g_assFLOW_AFSM_AMB_TGT(LVL + 1); */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + /* Sum: '/deg' incorporates: + * MATLAB Function: '/g_assFLOW_AFSM_AMB_TGT' + */ + rtb_deg_c = (int16_t)(g_assFLOW_AFSM_AMB_TGT[tmp_0 - 1] - rtu_Amb_Fb); + + /* Gain: '/Gain2' */ + tmp_0 = 13107 * rtb_deg_c; + rtb_X_m = (int8_t)(((((uint32_t)tmp_0 & 65536U) != 0U) && ((((uint32_t)tmp_0 & + 65535U) != 0U) || (tmp_0 > 0))) + (tmp_0 >> 17)); + + /* Switch: '/if (deg < 0)' incorporates: + * Sum: '/ ' + * Switch: '/Switch2' + */ + if (rtb_X_m >= 0) { + rtb_Switch2_lt_idx_0 = rty_Out1[0]; + rtb_Switch2_lt_idx_1 = rty_Out1[1]; + } else { + /* MATLAB Function: '/g_aucFLOW_AFSM_VENT_PLUS' incorporates: + * MATLAB Function: '/g_assFLOW_AFSM_TEMP_TGT_LEFT' + */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + /* Product: '/' incorporates: + * Gain: '/Gain' + * MATLAB Function: '/g_aucFLOW_AFSM_VENT_PLUS' + */ + rtb_deg_c = (int16_t)((int32_t)((g_aucFLOW_AFSM_VENT_PLUS[tmp_0 - 1] * 205U + + 1024U) >> 11) * rtb_X_m); + rtb_Switch2_lt_idx_0 = (uint16_t)(rty_Out1[0] - rtb_deg_c); + rtb_Switch2_lt_idx_1 = (uint16_t)(rty_Out1[1] - rtb_deg_c); + } + + /* End of Switch: '/if (deg < 0)' */ + + /* MATLAB Function: '/g_aucFLOW_AF_VENT_VALVE_MAX' incorporates: + * MATLAB Function: '/g_assFLOW_AFSM_TEMP_TGT_LEFT' + */ + /* : c_g_aucFLOW_AFSM_VENT_VALVE_MAX = g_aucFLOW_AFSM_VENT_VALVE_MAX(LVL + 1); */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + rtb_c_g_aucFLOW_AFSM_VENT_VALVE_MAX_g = g_aucFLOW_AFSM_VENT_VALVE_MAX[tmp_0 - + 1]; + + /* End of MATLAB Function: '/g_aucFLOW_AF_VENT_VALVE_MAX' */ + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + */ + if (rtb_Switch2_lt_idx_0 > rtb_c_g_aucFLOW_AFSM_VENT_VALVE_MAX_g) { + rtb_Switch2_lt_idx_0 = rtb_c_g_aucFLOW_AFSM_VENT_VALVE_MAX_g; + } + + if (rtb_Switch2_lt_idx_1 > rtb_c_g_aucFLOW_AFSM_VENT_VALVE_MAX_g) { + rtb_Switch2_lt_idx_1 = rtb_c_g_aucFLOW_AFSM_VENT_VALVE_MAX_g; + } + + /* End of Switch: '/Switch2' */ + + /* MATLAB Function: '/g_assFLOW_AF_AMB_TGT' */ + /* : c_g_aucFLOW_AFSM_VENT_PLUS = g_aucFLOW_AFSM_VENT_PLUS(LVL + 1 + 6); */ + g_assFLOW_AF_AMB_TGT_g(rtu_LVL, &rtb_deg_c); + + /* Gain: '/Gain2' incorporates: + * Sum: '/deg' + */ + tmp_0 = (int16_t)(rtb_deg_c - rtu_Amb_Fb) * 13107; + rtb_X_m = (int8_t)(((((uint32_t)tmp_0 & 65536U) != 0U) && ((((uint32_t)tmp_0 & + 65535U) != 0U) || (tmp_0 > 0))) + (tmp_0 >> 17)); + + /* Switch: '/if (deg < 0)' incorporates: + * DataTypeConversion: '/Data Type Conversion' + * Sum: '/ ' + * Switch: '/Switch2' + */ + if (rtb_X_m >= 0) { + rtb_Switch2_j1_idx_0 = rty_Out1[0]; + rtb_Switch2_j1_idx_1 = rty_Out1[1]; + } else { + /* MATLAB Function: '/g_aucFLOW_AF_VENT_PLUS' incorporates: + * MATLAB Function: '/g_assFLOW_AFSM_TEMP_TGT_LEFT' + */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + tmp = (int32_t)((uint32_t)tmp_0 + 6U); + if ((uint32_t)tmp_0 + 6U > 255U) { + tmp = 255; + } + + /* Product: '/' incorporates: + * Gain: '/Gain' + * MATLAB Function: '/g_aucFLOW_AF_VENT_PLUS' + */ + rtb_deg_c = (int16_t)((int32_t)((g_aucFLOW_AFSM_VENT_PLUS[tmp - 1] * 205U + + 1024U) >> 11) * rtb_X_m); + rtb_Switch2_j1_idx_0 = (uint16_t)((int16_t)rty_Out1[0] - rtb_deg_c); + rtb_Switch2_j1_idx_1 = (uint16_t)((int16_t)rty_Out1[1] - rtb_deg_c); + } + + /* End of Switch: '/if (deg < 0)' */ + + /* MATLAB Function: '/g_aucFLOW_AF_VENT_VALVE_MAX' incorporates: + * MATLAB Function: '/g_assFLOW_AFSM_TEMP_TGT_LEFT' + */ + /* : c_g_aucFLOW_AFSM_VENT_VALVE_MAX = g_aucFLOW_AFSM_VENT_VALVE_MAX(LVL + 1 + 6); */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + tmp = (int32_t)((uint32_t)tmp_0 + 6U); + if ((uint32_t)tmp_0 + 6U > 255U) { + tmp = 255; + } + + rtb_c_g_aucFLOW_AFSM_VENT_VALVE_MAX_g = g_aucFLOW_AFSM_VENT_VALVE_MAX[tmp - 1]; + + /* End of MATLAB Function: '/g_aucFLOW_AF_VENT_VALVE_MAX' */ + + /* Assignment: '/ [1-2]' incorporates: + * SignalConversion generated from: '/Out1' + * Switch: '/Switch2' + */ + rty_Out1[0] = rtb_Switch2_lt_idx_0; + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + */ + if (rtb_Switch2_j1_idx_0 > rtb_c_g_aucFLOW_AFSM_VENT_VALVE_MAX_g) { + /* Assignment: '/ [3-4]' incorporates: + * SignalConversion generated from: '/Out1' + */ + rty_Out1[2] = rtb_c_g_aucFLOW_AFSM_VENT_VALVE_MAX_g; + } else { + /* Assignment: '/ [3-4]' incorporates: + * SignalConversion generated from: '/Out1' + */ + rty_Out1[2] = rtb_Switch2_j1_idx_0; + } + + /* Assignment: '/ [1-2]' incorporates: + * SignalConversion generated from: '/Out1' + * Switch: '/Switch2' + */ + rty_Out1[1] = rtb_Switch2_lt_idx_1; + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + */ + if (rtb_Switch2_j1_idx_1 > rtb_c_g_aucFLOW_AFSM_VENT_VALVE_MAX_g) { + /* Assignment: '/ [3-4]' incorporates: + * SignalConversion generated from: '/Out1' + */ + rty_Out1[3] = rtb_c_g_aucFLOW_AFSM_VENT_VALVE_MAX_g; + } else { + /* Assignment: '/ [3-4]' incorporates: + * SignalConversion generated from: '/Out1' + */ + rty_Out1[3] = rtb_Switch2_j1_idx_1; + } + + /* Assignment: '/ [5]' incorporates: + * SignalConversion generated from: '/Out1' + */ + rty_Out1[4] = rtb_FLF_NEW; + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + */ + if (rtb_FRF_NEW > rtb_c_g_aucFLOW_AFSM_FOOT_VALVE_MAX) { + /* Assignment: '/ [7]' incorporates: + * SignalConversion generated from: '/Out1' + */ + rty_Out1[6] = rtb_c_g_aucFLOW_AFSM_FOOT_VALVE_MAX; + } else { + /* Assignment: '/ [7]' incorporates: + * SignalConversion generated from: '/Out1' + * Switch: '/Switch' + */ + rty_Out1[6] = rtb_FRF_NEW; + } + + /* End of Switch: '/Switch2' */ +} + +double rt_roundd(double u_0) +{ + double y; + if (fabs(u_0) < 4.503599627370496E+15) { + if (u_0 >= 0.5) { + y = floor(u_0 + 0.5); + } else if (u_0 > -0.5) { + y = 0.0; + } else { + y = ceil(u_0 - 0.5); + } + } else { + y = u_0; + } + + return y; +} + +/* + * Output and update for atomic system: + * '/ left' + * '/ right' + */ +void left(uint8_t rtu_idx, uint16_t rty_vals[9]) +{ + int32_t i; + int32_t rtu_idx_0; + uint16_t tmp[45]; + + /* : table = [ */ + /* : g_ausFLOW_FR_VE2VALVE; */ + /* : g_ausFLOW_FR_BIVALVE; */ + /* : g_ausFLOW_FR_BI2VALVE; */ + /* : g_ausFLOW_FR_AF2VALVE; */ + /* : g_ausFLOW_FR_AF2VALVE_SUMMER */ + /* : ]; */ + /* : idx = idx / 10; */ + /* : vals = table(idx, :); */ + rtu_idx_0 = (int32_t)rt_roundd((double)rtu_idx / 10.0); + for (i = 0; i < 9; i++) { + tmp[5 * i] = g_ausFLOW_FR_VE2VALVE[i]; + tmp[5 * i + 1] = g_ausFLOW_FR_BIVALVE[i]; + tmp[5 * i + 2] = g_ausFLOW_FR_BI2VALVE[i]; + tmp[5 * i + 3] = g_ausFLOW_FR_AF2VALVE[i]; + tmp[5 * i + 4] = g_ausFLOW_FR_AF2VALVE_SUMMER[i]; + rty_vals[i] = tmp[(5 * i + rtu_idx_0) - 1]; + } +} + +/* + * Output and update for action system: + * '/If Action Subsystem' + * '/If Action Subsystem' + */ +void IfActionSubsystem(uint8_t rtu_In1, int8_t *rty_Out1, int16_t *rty_Out2) +{ + /* Lookup_n-D: '/1-D Lookup Table1' */ + *rty_Out1 = look1_iu8lu64n56ts8Ds16_binlcs(rtu_In1, rtConstP.pooled111, + &g_ascFOOT_STEP_VALVE_M1[0], 10U); + + /* Lookup_n-D: '/1-D Lookup Table2' */ + *rty_Out2 = look1_iu8lu64n48ts16Ds32_binlcs(rtu_In1, rtConstP.pooled111, + &g_assFOOT_STEP_BLR_M1[0], 10U); +} + +/* + * Output and update for action system: + * '/If Action Subsystem1' + * '/If Action Subsystem1' + * '/If Action Subsystem1' + * '/If Action Subsystem1' + * '/If Action Subsystem1' + * '/If Action Subsystem1' + */ +void IfActionSubsystem1(int8_t *rty_Out1, int16_t *rty_Out2) +{ + /* SignalConversion generated from: '/Out1' incorporates: + * Constant: '/Constant' + */ + *rty_Out1 = 0; + + /* SignalConversion generated from: '/Out2' incorporates: + * Constant: '/Constant1' + */ + *rty_Out2 = 0; +} + +/* + * Output and update for action system: + * '/If Action Subsystem2' + * '/If Action Subsystem2' + */ +void IfActionSubsystem2(uint8_t rtu_In1, int8_t *rty_Out1, int16_t *rty_Out2) +{ + /* Lookup_n-D: '/1-D Lookup Table' */ + *rty_Out1 = look1_iu8lu64n56ts8Ds16_binlcs(rtu_In1, rtConstP.pooled111, + &g_ascFOOT_STEP_VALVE_P1[0], 10U); + + /* Lookup_n-D: '/1-D Lookup Table2' */ + *rty_Out2 = look1_iu8lu64n48ts16Ds32_binlcs(rtu_In1, rtConstP.pooled111, + &g_assFOOT_STEP_BLR_P1[0], 10U); +} + +/* + * Output and update for action system: + * '/If Action Subsystem' + * '/If Action Subsystem' + */ +void IfActionSubsystem_b(uint8_t rtu_In1, int8_t *rty_Out1, int16_t *rty_Out2) +{ + /* Lookup_n-D: '/1-D Lookup Table1' */ + *rty_Out1 = look1_iu8lu64n56ts8Ds16_binlcs(rtu_In1, rtConstP.pooled111, + &g_ascFOOT_STEP_VALVE_M2[0], 10U); + + /* Lookup_n-D: '/1-D Lookup Table2' */ + *rty_Out2 = look1_iu8lu64n48ts16Ds32_binlcs(rtu_In1, rtConstP.pooled111, + &g_assFOOT_STEP_BLR_M2[0], 10U); +} + +/* + * Output and update for action system: + * '/If Action Subsystem2' + * '/If Action Subsystem2' + */ +void IfActionSubsystem2_o(uint8_t rtu_In1, int8_t *rty_Out1, int16_t *rty_Out2) +{ + /* Lookup_n-D: '/1-D Lookup Table' */ + *rty_Out1 = look1_iu8lu64n56ts8Ds16_binlcs(rtu_In1, rtConstP.pooled111, + &g_ascFOOT_STEP_VALVE_P2[0], 10U); + + /* Lookup_n-D: '/1-D Lookup Table2' */ + *rty_Out2 = look1_iu8lu64n48ts16Ds32_binlcs(rtu_In1, rtConstP.pooled111, + &g_assFOOT_STEP_BLR_P2[0], 10U); +} + +/* + * Output and update for action system: + * '/If Action Subsystem' + * '/If Action Subsystem' + */ +void IfActionSubsystem_n(uint8_t rtu_In1, int8_t *rty_Out1, int16_t *rty_Out2) +{ + /* Lookup_n-D: '/1-D Lookup Table1' */ + *rty_Out1 = look1_iu8lu64n56ts8Ds16_binlcs(rtu_In1, rtConstP.pooled111, + &g_ascFOOT_STEP_VALVE_M3[0], 10U); + + /* Lookup_n-D: '/1-D Lookup Table2' */ + *rty_Out2 = look1_iu8lu64n48ts16Ds32_binlcs(rtu_In1, rtConstP.pooled111, + &g_assFOOT_STEP_BLR_M3[0], 10U); +} + +/* + * Output and update for action system: + * '/If Action Subsystem2' + * '/If Action Subsystem2' + */ +void IfActionSubsystem2_c(uint8_t rtu_In1, int8_t *rty_Out1, int16_t *rty_Out2) +{ + /* Lookup_n-D: '/1-D Lookup Table' */ + *rty_Out1 = look1_iu8lu64n56ts8Ds16_binlcs(rtu_In1, rtConstP.pooled111, + &g_ascFOOT_STEP_VALVE_P3[0], 10U); + + /* Lookup_n-D: '/1-D Lookup Table2' */ + *rty_Out2 = look1_iu8lu64n48ts16Ds32_binlcs(rtu_In1, rtConstP.pooled111, + &g_assFOOT_STEP_BLR_P3[0], 10U); +} + +/* + * Output and update for atomic system: + * '/g_assSTART_ENTER_INCAR' + * '/g_assSTART_ENTER_INCAR' + */ +void g_assSTART_ENTER_INCAR_n(uint8_t rtu_LVL, int16_t *rty_out) +{ + int32_t tmp; + + /* : out = int16(g_assSTART_ENTER_INCAR(LVL+1)); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + *rty_out = g_assSTART_ENTER_INCAR[tmp - 1]; +} + +/* + * Output and update for action system: + * '/Level 2' + * '/Level 2' + */ +void Level2(int8_t *rty_step) +{ + /* SignalConversion generated from: '/step' incorporates: + * Constant: '/Constant' + */ + *rty_step = 3; +} + +/* + * Output and update for atomic system: + * '/g_assSTART_ENTER_COOLANT ' + * '/g_assSTART_ENTER_COOLANT ' + * '/g_assSTART_ENTER_COOLANT ' + */ +void g_assSTART_ENTER_COOLANT_m(uint8_t rtu_LVL, int16_t *rty_out) +{ + int32_t q0; + uint32_t qY; + + /* : out = int16(g_assSTART_ENTER_COOLANT(LVL + 1 - 3)); */ + q0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + q0 = 255; + } + + /* MW:begin MISRA2012:D4.1 CERT-C:INT30-C 'Justifying MISRA CPP rule violation' */ + qY = (uint32_t)q0 - 3U; + + /* MW:end MISRA2012:D4.1 CERT-C:INT30-C */ + if ((uint32_t)q0 - 3U > (uint32_t)q0) { + qY = 0U; + } + + *rty_out = g_assSTART_ENTER_COOLANT[(int32_t)qY - 1]; +} + +/* + * Output and update for action system: + * '/Level 4' + * '/Level 5' + */ +void Level4(int8_t *rty_step1, const uint8_t *rtd_CCU_MODE_FL, const int16_t + *rtd_ECT, const uint8_t *rtd_LEVEL, const uint8_t *rtd_LO_HI_MODE_FL) +{ + int16_t rtb_out_hi; + + /* MATLAB Function: '/g_assSTART_ENTER_COOLANT ' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + g_assSTART_ENTER_COOLANT_m(*rtd_LEVEL, &rtb_out_hi); + + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * Constant: '/LOW' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read5' + * DataStoreRead: '/mode driver' + * Logic: '/AND' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator2' + * RelationalOperator: '/Relational Operator3' + */ + if ((*rtd_ECT < rtb_out_hi) && (*rtd_CCU_MODE_FL == 1) && (*rtd_LO_HI_MODE_FL + != 1)) { + *rty_step1 = 0; + } else { + *rty_step1 = -1; + } + + /* End of Switch: '/Switch' */ +} + +/* + * Output and update for action system: + * '/Level 0' + * '/Level 1' + * '/Level 2' + * '/Level 0' + * '/Level 1' + */ +void Level0(int8_t *rty_step) +{ + /* SignalConversion generated from: '/step' incorporates: + * Constant: '/Constant' + */ + *rty_step = 1; +} + +/* + * Output and update for atomic system: + * '/incar filter down' + * '/incar filter down' + * '/incar filter down' + * '/incar filter down' + * '/incar filter down' + * '/incar filter down' + * '/incar filter down' + * '/incar filter down' + * '/incar filter down' + * '/incar filter down' + * ... + */ +void incarfilterdown(uint8_t rtu_LVL, uint8_t *rty_out) +{ + int32_t tmp; + + /* : out = g_aucSTART_INCAR_FLT_DN(LVL + 1); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + *rty_out = g_aucSTART_INCAR_FLT_DN[tmp - 1]; +} + +/* + * Output and update for atomic system: + * '/incar filter up' + * '/incar filter up' + * '/incar filter up' + * '/incar filter up' + * '/incar filter up' + * '/incar filter up' + * '/incar filter up' + * '/incar filter up' + * '/incar filter up' + * '/incar filter up' + * ... + */ +void incarfilterup(uint8_t rtu_LVL, uint8_t *rty_out) +{ + int32_t tmp; + + /* : out = g_aucSTART_INCAR_FLT_UP(LVL + 1); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + *rty_out = g_aucSTART_INCAR_FLT_UP[tmp - 1]; +} + +/* + * Output and update for atomic system: + * '/g_assSTART_COOLANT_STEP0_TO_1 ' + * '/g_assSTART_COOLANT_STEP0_TO_1 ' + */ +void g_assSTART_COOLANT_STEP0_TO_1_c(uint8_t rtu_LVL, int16_t *rty_out) +{ + int32_t q0; + uint32_t qY; + + /* : out = int16(g_assSTART_COOLANT_STEP0_TO_1(LVL + 1 - 2)); */ + q0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + q0 = 255; + } + + /* MW:begin MISRA2012:D4.1 CERT-C:INT30-C 'Justifying MISRA CPP rule violation' */ + qY = (uint32_t)q0 - 2U; + + /* MW:end MISRA2012:D4.1 CERT-C:INT30-C */ + if ((uint32_t)q0 - 2U > (uint32_t)q0) { + qY = 0U; + } + + *rty_out = g_assSTART_COOLANT_STEP0_TO_1[(int32_t)qY - 1]; +} + +/* + * Output and update for atomic system: + * '/3 way valve status' + * '/3 way valve status' + * '/3 way valve status' + * '/3 way valve status' + * '/3 way valve status' + */ +void uwayvalvestatus(uint8_t rtu_LVL, uint8_t *rty_out) +{ + int32_t tmp; + + /* : out = g_aucSTART_3WAY_OPEN(LVL + 1); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + *rty_out = g_aucSTART_3WAY_OPEN[tmp - 1]; +} + +/* + * Output and update for atomic system: + * '/Dtg_FrontLower_X' + * '/Dtg_FrontLower_X' + * '/Dtg_FrontLower_X' + */ +void Dtg_FrontLower_X(uint8_t rtu_LVL, uint8_t *rty_out) +{ + int32_t tmp; + + /* : out = g_aucSTART_DUCT_TGT_STEP2_FX_L(LVL + 1); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + *rty_out = g_aucSTART_DUCT_TGT_STEP2_FX_L[tmp - 1]; +} + +/* + * Output and update for atomic system: + * '/Dtg_FrontUpper_X' + * '/Dtg_FrontUpper_X' + * '/Dtg_FrontUpper_X' + */ +void Dtg_FrontUpper_X(uint8_t rtu_LVL, uint8_t *rty_out) +{ + int32_t tmp; + + /* : out = g_aucSTART_DUCT_TGT_STEP2_FX_U(LVL + 1); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + *rty_out = g_aucSTART_DUCT_TGT_STEP2_FX_U[tmp - 1]; +} + +/* + * Output and update for atomic system: + * '/Incar temp goto from step 1 to step 2 ' + * '/Incar temp goto from step 1 to step 2 ' + * '/Incar temp goto from step 1 to step 2 ' + * '/Incar temp goto from step 1 to step 2 ' + * '/Incar temp goto from step 1 to step 2 ' + */ +void Incartempgotofromstep1tostep2(uint8_t rtu_LVL, int16_t *rty_out) +{ + int32_t tmp; + + /* : out = int16(g_assSTART_INCAR_STEP1_TO_2(LVL + 1)); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + *rty_out = g_assSTART_INCAR_STEP1_TO_2[tmp - 1]; +} + +/* + * System initialize for atomic system: + * '/MATLAB Function1' + * '/MATLAB Function1' + * '/MATLAB Function1' + * '/MATLAB Function1' + * '/MATLAB Function1' + * '/MATLAB Function1' + * '/MATLAB Function1' + * '/MATLAB Function1' + * '/MATLAB Function1' + * '/MATLAB Function1' + * ... + */ +void MATLABFunction1_Init(DW_MATLABFunction1 *localDW) +{ + localDW->t_start_not_empty = false; +} + +/* + * Output and update for atomic system: + * '/MATLAB Function1' + * '/MATLAB Function1' + * '/MATLAB Function1' + * '/MATLAB Function1' + * '/MATLAB Function1' + * '/MATLAB Function1' + * '/MATLAB Function1' + * '/MATLAB Function1' + * '/MATLAB Function1' + * '/MATLAB Function1' + * ... + */ +void MATLABFunction1(uint32_t rtu_t_now, uint16_t rtu_time_delta, bool + *rty_timer_out, DW_MATLABFunction1 *localDW) +{ + uint32_t qY; + + /* : if isempty(t_start) */ + if (!localDW->t_start_not_empty) { + /* : t_start = t_now; */ + localDW->t_start = rtu_t_now; + localDW->t_start_not_empty = true; + } + + /* : timer_out = (t_now - t_start) >= time_delta; */ + /* MW:begin MISRA2012:D4.1 CERT-C:INT30-C 'Justifying MISRA CPP rule violation' */ + qY = rtu_t_now - /*MW:OvSatOk*/ localDW->t_start; + + /* MW:end MISRA2012:D4.1 CERT-C:INT30-C */ + if (qY > rtu_t_now) { + qY = 0U; + } + + *rty_timer_out = (qY >= rtu_time_delta); +} + +/* + * Output and update for atomic system: + * '/blower FR' + * '/blower FR' + */ +void blowerFR(uint8_t rtu_LVL, uint16_t *rty_out) +{ + int32_t tmp; + + /* : out = g_ausSTART_BLR_AF_STEP12_F(LVL + 1); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + *rty_out = g_ausSTART_BLR_AF_STEP12_F[tmp - 1]; +} + +/* + * Output and update for atomic system: + * '/mode FR step 1' + * '/mode FR step 1' + * '/mode FR step 1' + * '/mode FR step 1' + * '/mode FR step 1' + */ +void modeFRstep1(uint8_t rtu_LVL, uint8_t *rty_out) +{ + int32_t tmp; + + /* : out = g_aucSTART_VALVE_IDX_STEP1(LVL + 1); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + *rty_out = g_aucSTART_VALVE_IDX_STEP1[tmp - 1]; +} + +/* + * Output and update for atomic system: + * '/window heating' + * '/window heating' + * '/window heating' + * '/window heating' + * '/window heating' + */ +void windowheating(uint8_t rtu_LVL, uint8_t *rty_out) +{ + int32_t tmp; + + /* : out = g_aucSTART_ELEC_WINDOW(LVL + 1); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + *rty_out = g_aucSTART_ELEC_WINDOW[tmp - 1]; +} + +/* + * System initialize for atomic system: + * '/MATLAB Function1' + * '/MATLAB Function1' + * '/MATLAB Function1' + * '/MATLAB Function1' + * '/MATLAB Function1' + * '/MATLAB Function1' + * '/MATLAB Function1' + * '/MATLAB Function1' + * '/MATLAB Function1' + */ +void MATLABFunction1_a_Init(DW_MATLABFunction1_f *localDW) +{ + localDW->t_start_not_empty = false; +} + +/* + * Output and update for atomic system: + * '/MATLAB Function1' + * '/MATLAB Function1' + * '/MATLAB Function1' + * '/MATLAB Function1' + * '/MATLAB Function1' + * '/MATLAB Function1' + * '/MATLAB Function1' + * '/MATLAB Function1' + * '/MATLAB Function1' + */ +void MATLABFunction1_j(uint32_t rtu_t_now, uint32_t rtu_time_delta, bool + *rty_timer_out, DW_MATLABFunction1_f *localDW) +{ + uint32_t qY; + + /* : if isempty(t_start) */ + if (!localDW->t_start_not_empty) { + /* : t_start = t_now; */ + localDW->t_start = rtu_t_now; + localDW->t_start_not_empty = true; + } + + /* : timer_out = (t_now - t_start) >= time_delta; */ + /* MW:begin MISRA2012:D4.1 CERT-C:INT30-C 'Justifying MISRA CPP rule violation' */ + qY = rtu_t_now - /*MW:OvSatOk*/ localDW->t_start; + + /* MW:end MISRA2012:D4.1 CERT-C:INT30-C */ + if (qY > rtu_t_now) { + qY = 0U; + } + + *rty_timer_out = (qY >= rtu_time_delta); +} + +/* + * Output and update for atomic system: + * '/Time goto from step 1 to step 2 ' + * '/Time goto from step 1 to step 2 ' + * '/Time goto from step 1 to step 2 ' + * '/Time goto from step 1 to step 2 ' + */ +void Timegotofromstep1tostep2(uint8_t rtu_LVL, int16_t *rty_out) +{ + int32_t tmp; + uint16_t tmp_0; + + /* : out = int16(g_ausSTART_TIME_STEP1_TO_2(LVL + 1)); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + tmp_0 = g_ausSTART_TIME_STEP1_TO_2[tmp - 1]; + if (tmp_0 > 32767) { + tmp_0 = 32767U; + } + + *rty_out = (int16_t)tmp_0; +} + +/* + * Output and update for atomic system: + * '/ECT min max' + * '/ECT min max' + * '/ECT min max' + */ +void ECTminmax(uint8_t rtu_LVL, int16_t rty_out[2]) +{ + int32_t q0; + uint32_t qY; + + /* : min = int16(g_assSTART_COOLANT_STEP0_TO_1(LVL + 1 - 2)); */ + /* : max = int16(g_assSTART_COOLANT_TO_STEP2(1)); */ + /* : out = [min, max]; */ + q0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + q0 = 255; + } + + /* MW:begin MISRA2012:D4.1 CERT-C:INT30-C 'Justifying MISRA CPP rule violation' */ + qY = (uint32_t)q0 - 2U; + + /* MW:end MISRA2012:D4.1 CERT-C:INT30-C */ + if ((uint32_t)q0 - 2U > (uint32_t)q0) { + qY = 0U; + } + + rty_out[0] = g_assSTART_COOLANT_STEP0_TO_1[(int32_t)qY - 1]; + rty_out[1] = g_assSTART_COOLANT_TO_STEP2[0]; +} + +/* + * Output and update for atomic system: + * '/blower min max' + * '/blower min max' + * '/blower min max' + */ +void blowerminmax(uint8_t rtu_LVL, uint16_t rty_out[2]) +{ + int32_t tmp; + + /* : min = 20; */ + /* : max = g_ausSTART_BLR_AF_STEP12_F(LVL + 1); */ + /* : out = [min, max]; */ + rty_out[0] = 20U; + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + rty_out[1] = g_ausSTART_BLR_AF_STEP12_F[tmp - 1]; +} + +/* + * Output and update for atomic system: + * '/3 way valve status' + * '/3 way valve status' + * '/3 way valve status' + * '/3 way valve status' + * '/3 way valve status' + */ +void uwayvalvestatus_m(uint8_t rtu_LVL, uint8_t *rty_out) +{ + int32_t tmp; + int32_t tmp_0; + + /* : out = g_aucSTART_3WAY_OPEN(LVL + 1 + 6); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + tmp_0 = (int32_t)((uint32_t)tmp + 6U); + if ((uint32_t)tmp + 6U > 255U) { + tmp_0 = 255; + } + + *rty_out = g_aucSTART_3WAY_OPEN[tmp_0 - 1]; +} + +/* + * Output and update for atomic system: + * '/time for step' + * '/time for step' + * '/time for step' + * '/time for step' + * '/time for step' + */ +void timeforstep(uint8_t rtu_LVL, uint8_t *rty_out) +{ + int32_t tmp; + int32_t tmp_0; + + /* : out = g_aucSTART_DUCT_TGT_STEP2_FX_L(LVL + 1 + 6); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + tmp_0 = (int32_t)((uint32_t)tmp + 6U); + if ((uint32_t)tmp + 6U > 255U) { + tmp_0 = 255; + } + + *rty_out = g_aucSTART_DUCT_TGT_STEP2_FX_L[tmp_0 - 1]; +} + +/* + * Output and update for atomic system: + * '/time for step' + * '/time for step' + * '/time for step' + * '/time for step' + * '/time for step' + */ +void timeforstep_d(uint8_t rtu_LVL, uint8_t *rty_out) +{ + int32_t tmp; + int32_t tmp_0; + + /* : out = g_aucSTART_DUCT_TGT_STEP2_FX_U(LVL + 1 + 6); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + tmp_0 = (int32_t)((uint32_t)tmp + 6U); + if ((uint32_t)tmp + 6U > 255U) { + tmp_0 = 255; + } + + *rty_out = g_aucSTART_DUCT_TGT_STEP2_FX_U[tmp_0 - 1]; +} + +/* + * Output and update for atomic system: + * '/Time goto from step 2 to step 3 ' + * '/Time goto from step 2 to step 3 ' + * '/Time goto from step 2 to step 3 ' + * '/Time goto from step 2 to step 3 ' + * '/Time goto from step 2 to step 3 ' + */ +void Timegotofromstep2tostep3(uint8_t rtu_LVL, int16_t *rty_out) +{ + int32_t tmp; + uint16_t tmp_0; + + /* : out = int16(g_ausSTART_TIME_STEP2_TO_3(LVL + 1)); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + tmp_0 = g_ausSTART_TIME_STEP2_TO_3[tmp - 1]; + if (tmp_0 > 32767) { + tmp_0 = 32767U; + } + + *rty_out = (int16_t)tmp_0; +} + +/* + * Output and update for atomic system: + * '/blower step' + * '/blower step' + * '/blower step' + * '/blower step' + * '/blower step' + */ +void blowerstep(uint8_t rtu_LVL, uint16_t *rty_out) +{ + int32_t tmp; + + /* : out = g_ausSTART_BLR_SPD_STEP2_F(LVL + 1); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + *rty_out = g_ausSTART_BLR_SPD_STEP2_F[tmp - 1]; +} + +/* + * Output and update for atomic system: + * '/blower time for step' + * '/blower time for step' + * '/blower time for step' + * '/blower time for step' + * '/blower time for step' + */ +void blowertimeforstep(uint8_t rtu_LVL, uint16_t *rty_out) +{ + int32_t tmp; + int32_t tmp_0; + + /* : out = g_ausSTART_BLR_SPD_STEP2_F(LVL + 1 + 6); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + tmp_0 = (int32_t)((uint32_t)tmp + 6U); + if ((uint32_t)tmp + 6U > 255U) { + tmp_0 = 255; + } + + *rty_out = g_ausSTART_BLR_SPD_STEP2_F[tmp_0 - 1]; +} + +/* + * Output and update for atomic system: + * '/step' + * '/step' + * '/step' + * '/step' + * '/step' + */ +void step_g(uint8_t rtu_LVL, uint8_t *rty_out) +{ + int32_t tmp; + + /* : out = g_aucSTART_VALVE_CHANGE_SPD_F(LVL + 1); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + *rty_out = g_aucSTART_VALVE_CHANGE_SPD_F[tmp - 1]; +} + +/* + * Output and update for atomic system: + * '/time for step' + * '/time for step' + * '/time for step' + * '/time for step' + * '/time for step' + */ +void timeforstep_f(uint8_t rtu_LVL, uint8_t *rty_out) +{ + int32_t tmp; + int32_t tmp_0; + + /* : out = g_aucSTART_VALVE_CHANGE_SPD_F(LVL + 1 + 6); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + tmp_0 = (int32_t)((uint32_t)tmp + 6U); + if ((uint32_t)tmp + 6U > 255U) { + tmp_0 = 255; + } + + *rty_out = g_aucSTART_VALVE_CHANGE_SPD_F[tmp_0 - 1]; +} + +/* + * Output and update for atomic system: + * '/window heating' + * '/window heating' + * '/window heating' + * '/window heating' + */ +void windowheating_o(uint8_t rtu_LVL, uint8_t *rty_out) +{ + int32_t tmp; + int32_t tmp_0; + + /* : out = g_aucSTART_ELEC_WINDOW(LVL + 1 + 6); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + tmp_0 = (int32_t)((uint32_t)tmp + 6U); + if ((uint32_t)tmp + 6U > 255U) { + tmp_0 = 255; + } + + *rty_out = g_aucSTART_ELEC_WINDOW[tmp_0 - 1]; +} + +/* + * Output and update for atomic system: + * '/autodemist (autodefog)' + * '/autodemist (autodefog)' + * '/autodemist (autodefog)' + */ +void autodemistautodefog(uint8_t rtu_LVL, uint8_t *rty_out) +{ + int32_t tmp; + + /* : out = g_aucSTART_AUTODEMIST2_STEP2(LVL + 1); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + *rty_out = g_aucSTART_AUTODEMIST2_STEP2[tmp - 1]; +} + +/* + * System initialize for action system: + * '/Level 3' + * '/Level 4' + */ +void Level3_Init(DW_Level3 *localDW) +{ + /* SystemInitialize for MATLAB Function: '/MATLAB Function1' */ + MATLABFunction1_a_Init(&localDW->sf_MATLABFunction1); +} + +/* + * Output and update for action system: + * '/Level 3' + * '/Level 4' + */ +void Level3(int8_t *rty_step, uint8_t *rtd_Autodefog, uint8_t *rtd_Blower_FL, + uint8_t *rtd_Blower_FR, const uint8_t *rtd_Blower_logic_FL, const + uint8_t *rtd_CCU_MODE_FL, uint16_t *rtd_Dtg_FLL, uint16_t + *rtd_Dtg_FLR, uint16_t *rtd_Dtg_FUL, uint16_t *rtd_Dtg_FUR, const + int16_t *rtd_Dtg_logic_FLL, const int16_t *rtd_Dtg_logic_FUL, + uint8_t *rtd_El_window_heating, const bool *rtd_HI_logic_on, uint8_t + *rtd_Incar_filter_down_value, uint8_t *rtd_Incar_filter_up_value, + const uint8_t *rtd_LEVEL, const uint8_t *rtd_LO_HI_MODE_FL, uint8_t * + rtd_Mode_FL, uint8_t *rtd_Mode_FR, const uint8_t *rtd_Mode_logic_FL, + double *rtd_Recirculation, uint8_t *rtd_Valve_3_way, const uint32_t * + rtd_t_now, DW_Level3 *localDW) +{ + double rtb_Switch_hz; + int32_t tmp; + int16_t rtb_out_lgm; + uint16_t rtb_out_bo; + uint16_t rtb_out_ja; + uint8_t rtb_out_bdu; + uint8_t rtb_out_ea; + uint8_t rtb_out_o2; + bool rtb_timer_out_k; + + /* DataStoreWrite: '/Data Store Write8' incorporates: + * DataStoreRead: '/Data Store Read10' + * MATLAB Function: '/3 way valve status' + */ + uwayvalvestatus_m(*rtd_LEVEL, rtd_Valve_3_way); + + /* Sum: '/Add' incorporates: + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + */ + rtb_out_lgm = (int16_t)((*rtd_Dtg_FLL - *rtd_Dtg_logic_FLL) >> 1); + + /* MATLAB Function: '/step' incorporates: + * DataStoreRead: '/Data Store Read9' + */ + Dtg_FrontLower_X(*rtd_LEVEL, &rtb_out_o2); + + /* MATLAB Function: '/time for step' incorporates: + * DataStoreRead: '/Data Store Read9' + */ + timeforstep(*rtd_LEVEL, &rtb_out_bdu); + + /* Abs: '/Abs' */ + if (rtb_out_lgm < 0) { + rtb_out_lgm = (int16_t)-rtb_out_lgm; + } + + /* Switch: '/Switch' incorporates: + * Abs: '/Abs' + * Constant: '/Constant' + * Constant: '/epsilon' + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + * DataStoreRead: '/ ' + * DataStoreWrite: '/Data Store Write12' + * Gain: '/Gain1' + * Product: '/Product1' + * Product: '/change rate (dtg//sec)' + * Product: '/ ' + * Product: '/ ' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + * Sum: '/Subtract' + * Switch: '/Switch' + * UnitDelay: '/Unit Delay' + */ + if ((double)rtb_out_lgm * 2.0 <= 0.01) { + *rtd_Dtg_FLR = (uint16_t)*rtd_Dtg_logic_FLL; + } else { + if (*rtd_Dtg_FLL <= *rtd_Dtg_logic_FLL) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + */ + tmp = 1; + } else { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant1' + */ + tmp = -1; + } + + *rtd_Dtg_FLR = (uint16_t)rt_roundd(10.0 * (double)rtb_out_o2 / (double) + rtb_out_bdu / 1000.0 * (double)(*rtd_t_now - localDW->UnitDelay_DSTATE) * + (double)tmp + (double)*rtd_Dtg_FLL); + } + + /* End of Switch: '/Switch' */ + + /* DataStoreWrite: '/Data Store Write13' incorporates: + * DataStoreWrite: '/Data Store Write12' + */ + *rtd_Dtg_FLL = *rtd_Dtg_FLR; + + /* Sum: '/Add' incorporates: + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + */ + rtb_out_lgm = (int16_t)((*rtd_Dtg_FUL - *rtd_Dtg_logic_FUL) >> 1); + + /* Abs: '/Abs' */ + if (rtb_out_lgm < 0) { + rtb_out_lgm = (int16_t)-rtb_out_lgm; + } + + /* End of Abs: '/Abs' */ + + /* MATLAB Function: '/step' incorporates: + * DataStoreRead: '/Data Store Read8' + */ + Dtg_FrontUpper_X(*rtd_LEVEL, &rtb_out_o2); + + /* MATLAB Function: '/time for step' incorporates: + * DataStoreRead: '/Data Store Read8' + */ + timeforstep_d(*rtd_LEVEL, &rtb_out_bdu); + + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + * Constant: '/epsilon' + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + * DataStoreRead: '/ ' + * DataStoreWrite: '/Data Store Write10' + * Gain: '/Gain1' + * Product: '/Product1' + * Product: '/change rate (dtg//sec)' + * Product: '/ ' + * Product: '/ ' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + * Sum: '/Subtract' + * Switch: '/Switch' + * UnitDelay: '/Unit Delay' + */ + if ((double)rtb_out_lgm * 2.0 <= 0.01) { + *rtd_Dtg_FUR = (uint16_t)*rtd_Dtg_logic_FUL; + } else { + if (*rtd_Dtg_FUL <= *rtd_Dtg_logic_FUL) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + */ + tmp = 1; + } else { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant1' + */ + tmp = -1; + } + + *rtd_Dtg_FUR = (uint16_t)rt_roundd(10.0 * (double)rtb_out_o2 / (double) + rtb_out_bdu / 1000.0 * (double)(*rtd_t_now - localDW->UnitDelay_DSTATE_c) * + (double)tmp + (double)*rtd_Dtg_FUL); + } + + /* End of Switch: '/Switch' */ + + /* DataStoreWrite: '/Data Store Write11' incorporates: + * DataStoreWrite: '/Data Store Write10' + */ + *rtd_Dtg_FUL = *rtd_Dtg_FUR; + + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataStoreRead: '/Data Store Read1' + * MATLAB Function: '/incar filter up' + */ + incarfilterup(*rtd_LEVEL, rtd_Incar_filter_up_value); + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataStoreRead: '/Data Store Read2' + * MATLAB Function: '/incar filter down' + */ + incarfilterdown(*rtd_LEVEL, rtd_Incar_filter_down_value); + + /* DataStoreWrite: '/Data Store Write14' incorporates: + * DataStoreRead: '/Data Store Read3' + * MATLAB Function: '/autodemist (autodefog)' + */ + autodemistautodefog(*rtd_LEVEL, rtd_Autodefog); + + /* Sum: '/Add' incorporates: + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + */ + rtb_out_o2 = (uint8_t)(*rtd_Mode_FL - *rtd_Mode_logic_FL); + + /* MATLAB Function: '/step' incorporates: + * DataStoreRead: '/Data Store Read5' + */ + step_g(*rtd_LEVEL, &rtb_out_bdu); + + /* MATLAB Function: '/time for step' incorporates: + * DataStoreRead: '/Data Store Read5' + */ + timeforstep_f(*rtd_LEVEL, &rtb_out_ea); + + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + * Constant: '/epsilon' + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + * DataStoreRead: '/ ' + * DataStoreWrite: '/Data Store Write2' + * Product: '/Product1' + * Product: '/change rate (step//sec)' + * Product: '/ ' + * Product: '/ ' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + * Sum: '/Subtract' + * Switch: '/Switch' + * UnitDelay: '/Unit Delay' + */ + if (rtb_out_o2 <= 0.01) { + *rtd_Mode_FR = *rtd_Mode_logic_FL; + } else { + if (*rtd_Mode_FL <= *rtd_Mode_logic_FL) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + */ + tmp = 1; + } else { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant1' + */ + tmp = -1; + } + + *rtd_Mode_FR = (uint8_t)((double)rtb_out_bdu / (double)rtb_out_ea / 1000.0 * + (double)(*rtd_t_now - localDW->UnitDelay_DSTATE_f) * (double)tmp + (double)* + rtd_Mode_FL); + } + + /* End of Switch: '/Switch' */ + + /* DataStoreWrite: '/Data Store Write3' incorporates: + * DataStoreWrite: '/Data Store Write2' + */ + *rtd_Mode_FL = *rtd_Mode_FR; + + /* MATLAB Function: '/window heating' incorporates: + * DataStoreRead: '/Data Store Read6' + */ + windowheating_o(*rtd_LEVEL, &rtb_out_o2); + + /* DataStoreWrite: '/Data Store Write4' */ + *rtd_El_window_heating = rtb_out_o2; + + /* MATLAB Function: '/blower step' incorporates: + * DataStoreRead: '/Data Store Read7' + */ + blowerstep(*rtd_LEVEL, &rtb_out_bo); + + /* MATLAB Function: '/blower time for step' incorporates: + * DataStoreRead: '/Data Store Read7' + */ + blowertimeforstep(*rtd_LEVEL, &rtb_out_ja); + + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + * Constant: '/epsilon' + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + * DataStoreRead: '/ ' + * Product: '/Product1' + * Product: '/change rate (step//sec)' + * Product: '/ ' + * Product: '/ ' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + * Sum: '/Add' + * Sum: '/Subtract' + * Switch: '/Switch' + * UnitDelay: '/Unit Delay' + */ + if ((uint8_t)(*rtd_Blower_FL - *rtd_Blower_logic_FL) <= 0.01) { + rtb_Switch_hz = *rtd_Blower_logic_FL; + } else { + if (*rtd_Blower_FL <= *rtd_Blower_logic_FL) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + */ + tmp = 1; + } else { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant1' + */ + tmp = -1; + } + + rtb_Switch_hz = (double)rtb_out_bo / (double)rtb_out_ja / 1000.0 * (double)(* + rtd_t_now - localDW->UnitDelay_DSTATE_l) * (double)tmp + (double)* + rtd_Blower_FL; + } + + /* End of Switch: '/Switch' */ + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * DataStoreWrite: '/Data Store Write5' + */ + *rtd_Blower_FR = (uint8_t)rtb_Switch_hz; + + /* DataStoreWrite: '/Data Store Write6' incorporates: + * DataStoreWrite: '/Data Store Write5' + */ + *rtd_Blower_FL = *rtd_Blower_FR; + + /* DataStoreWrite: '/Data Store Write7' incorporates: + * Constant: '/Recirc logic Partial REC' + */ + *rtd_Recirculation = 1.0; + + /* MATLAB Function: '/Time goto from step 2 to step 3 ' incorporates: + * DataStoreRead: '/Data Store Read4' + */ + Timegotofromstep2tostep3(*rtd_LEVEL, &rtb_out_lgm); + + /* MATLAB Function: '/MATLAB Function1' incorporates: + * DataStoreRead: '/Data Store Read13' + * Gain: '/ ' + */ + MATLABFunction1_j(*rtd_t_now, (uint32_t)(1000 * rtb_out_lgm), &rtb_timer_out_k, + &localDW->sf_MATLABFunction1); + + /* Switch: '/Switch1' incorporates: + * Constant: '/exit algorithm' + * Constant: '/not LO or HI' + * Constant: '/stay at step' + * DataStoreRead: '/Data Store Read11' + * DataStoreRead: '/Data Store Read12' + * Logic: '/Logical Operator' + * Logic: '/Logical Operator1' + * RelationalOperator: '/Relational Operator2' + * RelationalOperator: '/Relational Operator3' + * Switch: '/Switch' + */ + if ((*rtd_CCU_MODE_FL != 1) || (*rtd_LO_HI_MODE_FL != 0)) { + *rty_step = 3; + } else if (rtb_timer_out_k || (*rtd_HI_logic_on)) { + /* Switch: '/Switch' incorporates: + * Constant: '/go to next step' + */ + *rty_step = 3; + } else { + *rty_step = 2; + } + + /* End of Switch: '/Switch1' */ + + /* Update for UnitDelay: '/Unit Delay' incorporates: + * DataStoreRead: '/ ' + */ + localDW->UnitDelay_DSTATE = *rtd_t_now; + + /* Update for UnitDelay: '/Unit Delay' incorporates: + * DataStoreRead: '/ ' + */ + localDW->UnitDelay_DSTATE_c = *rtd_t_now; + + /* Update for UnitDelay: '/Unit Delay' incorporates: + * DataStoreRead: '/ ' + */ + localDW->UnitDelay_DSTATE_f = *rtd_t_now; + + /* Update for UnitDelay: '/Unit Delay' incorporates: + * DataStoreRead: '/ ' + */ + localDW->UnitDelay_DSTATE_l = *rtd_t_now; +} + +/* + * Output and update for action system: + * '/Step 3 F' + * '/Step 3 R' + */ +void Step3F(int8_t *rty_step, int8_t *rtd_start_control_finished_front) +{ + /* DataStoreWrite: '/Data Store Write10' incorporates: + * Constant: '/True' + */ + *rtd_start_control_finished_front = 1; + + /* SignalConversion generated from: '/step' incorporates: + * Constant: '/Constant1' + */ + *rty_step = 3; +} + +/* + * Output and update for atomic system: + * '/g_ausSTART_ENTER_SETTEMP' + * '/g_ausSTART_ENTER_SETTEMP' + * '/g_ausSTART_ENTER_SETTEMP' + */ +void g_ausSTART_ENTER_SETTEMP_i(uint8_t rtu_LVL, int16_t *rty_out) +{ + int32_t tmp; + int32_t tmp_0; + uint16_t tmp_1; + + /* : out = int16(g_ausSTART_ENTER_SETTEMP(LVL+1+6)); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + tmp_0 = (int32_t)((uint32_t)tmp + 6U); + if ((uint32_t)tmp + 6U > 255U) { + tmp_0 = 255; + } + + tmp_1 = g_ausSTART_ENTER_SETTEMP[tmp_0 - 1]; + if (tmp_1 > 32767) { + tmp_1 = 32767U; + } + + *rty_out = (int16_t)tmp_1; +} + +/* + * Output and update for atomic system: + * '/g_assSTART_ENTER_INCAR' + * '/g_assSTART_ENTER_INCAR' + * '/g_assSTART_ENTER_INCAR' + * '/g_assSTART_ENTER_INCAR' + * '/g_assSTART_ENTER_INCAR' + */ +void g_assSTART_ENTER_INCAR_f(uint8_t rtu_LVL, int16_t *rty_out) +{ + int32_t tmp; + int32_t tmp_0; + + /* : out = int16(g_assSTART_ENTER_INCAR(LVL+1+6)); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + tmp_0 = (int32_t)((uint32_t)tmp + 6U); + if ((uint32_t)tmp + 6U > 255U) { + tmp_0 = 255; + } + + *rty_out = g_assSTART_ENTER_INCAR[tmp_0 - 1]; +} + +/* + * Output and update for atomic system: + * '/g_assSTART_ENTER_COOLANT ' + * '/g_assSTART_ENTER_COOLANT ' + * '/g_assSTART_ENTER_COOLANT ' + */ +void g_assSTART_ENTER_COOLANT_m1(uint8_t rtu_LVL, int16_t *rty_out) +{ + int32_t tmp; + + /* : out = int16(g_assSTART_ENTER_COOLANT(LVL + 1)); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + *rty_out = g_assSTART_ENTER_COOLANT[tmp - 1]; +} + +/* + * Output and update for action system: + * '/Level 4' + * '/Level 5' + */ +void Level4_j(int8_t *rty_step1, const uint8_t *rtd_CCU_MODE_RR, const int16_t + *rtd_ECT, const int16_t *rtd_Incar_RR, const uint8_t *rtd_LEVEL, + const uint8_t *rtd_LO_HI_MODE_RR) +{ + int16_t rtb_out_lx; + int16_t rtb_out_mm; + + /* MATLAB Function: '/g_assSTART_ENTER_INCAR' incorporates: + * DataStoreRead: '/Data Store Read4' + */ + g_assSTART_ENTER_INCAR_f(*rtd_LEVEL, &rtb_out_mm); + + /* MATLAB Function: '/g_assSTART_ENTER_COOLANT ' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + g_assSTART_ENTER_COOLANT_m1(*rtd_LEVEL, &rtb_out_lx); + + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * Constant: '/LOW' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read5' + * Logic: '/AND' + * Logic: '/AND1' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator1' + * RelationalOperator: '/Relational Operator2' + * RelationalOperator: '/Relational Operator3' + */ + if (((*rtd_Incar_RR < rtb_out_mm) || (*rtd_ECT < rtb_out_lx)) && + (*rtd_CCU_MODE_RR == 1) && (*rtd_LO_HI_MODE_RR != 1)) { + *rty_step1 = 0; + } else { + *rty_step1 = -1; + } + + /* End of Switch: '/Switch' */ +} + +/* + * Output and update for atomic system: + * '/incar filter down' + * '/incar filter down' + * '/incar filter down' + * '/incar filter down' + */ +void incarfilterdown_m(uint8_t rtu_LVL, uint8_t *rty_out) +{ + int32_t tmp; + int32_t tmp_0; + + /* : out = g_aucSTART_INCAR_FLT_DN(LVL + 1 + 6); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + tmp_0 = (int32_t)((uint32_t)tmp + 6U); + if ((uint32_t)tmp + 6U > 255U) { + tmp_0 = 255; + } + + *rty_out = g_aucSTART_INCAR_FLT_DN[tmp_0 - 1]; +} + +/* + * Output and update for atomic system: + * '/incar filter up' + * '/incar filter up' + * '/incar filter up' + * '/incar filter up' + */ +void incarfilterup_j(uint8_t rtu_LVL, uint8_t *rty_out) +{ + int32_t tmp; + int32_t tmp_0; + + /* : out = g_aucSTART_INCAR_FLT_UP(LVL + 1 + 6); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + tmp_0 = (int32_t)((uint32_t)tmp + 6U); + if ((uint32_t)tmp + 6U > 255U) { + tmp_0 = 255; + } + + *rty_out = g_aucSTART_INCAR_FLT_UP[tmp_0 - 1]; +} + +/* + * Output and update for atomic system: + * '/g_assSTART_COOLANT_STEP0_TO_1 ' + * '/g_assSTART_COOLANT_STEP0_TO_1 ' + * '/g_assSTART_COOLANT_STEP0_TO_1 ' + */ +void g_assSTART_COOLANT_STEP0_TO_1_j(uint8_t rtu_LVL, int16_t *rty_out) +{ + int32_t tmp; + + /* : out = int16(g_assSTART_COOLANT_STEP0_TO_1(LVL + 3)); */ + tmp = (int32_t)(rtu_LVL + 3U); + if (rtu_LVL + 3U > 255U) { + tmp = 255; + } + + *rty_out = g_assSTART_COOLANT_STEP0_TO_1[tmp - 1]; +} + +/* + * Output and update for action system: + * '/Level 4' + * '/Level 5' + */ +void Level4_h(int8_t *rty_step1, uint8_t *rtd_Blower_RL, uint8_t *rtd_Blower_RR, + const uint8_t *rtd_CCU_MODE_RR, uint16_t *rtd_Dtg_RL, uint16_t + *rtd_Dtg_RR, const int16_t *rtd_ECT, uint8_t + *rtd_Incar_filter_down_value, uint8_t *rtd_Incar_filter_up_value, + const uint8_t *rtd_LEVEL, const uint8_t *rtd_LO_HI_MODE_RR, + uint8_t *rtd_Mode_RL, uint8_t *rtd_Mode_RR, uint8_t + *rtd_Valve_2_way, uint8_t *rtd_Valve_3_way) +{ + int16_t rtb_out_nl; + + /* DataStoreWrite: '/Data Store Write5' incorporates: + * Constant: '/Constant2' + */ + *rtd_Blower_RR = 10U; + + /* DataStoreWrite: '/Data Store Write6' incorporates: + * Constant: '/Constant3' + */ + *rtd_Blower_RL = 10U; + + /* DataStoreWrite: '/Data Store Write10' incorporates: + * Constant: '/Constant4' + */ + *rtd_Dtg_RR = 800U; + + /* DataStoreWrite: '/Data Store Write11' incorporates: + * Constant: '/Constant4' + */ + *rtd_Dtg_RL = 800U; + + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataStoreRead: '/Data Store Read1' + * MATLAB Function: '/incar filter up' + */ + incarfilterup_j(*rtd_LEVEL, rtd_Incar_filter_up_value); + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataStoreRead: '/Data Store Read2' + * MATLAB Function: '/incar filter down' + */ + incarfilterdown_m(*rtd_LEVEL, rtd_Incar_filter_down_value); + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/Mode - foot' + */ + *rtd_Mode_RR = 60U; + + /* DataStoreWrite: '/Data Store Write3' incorporates: + * Constant: '/Mode - foot' + */ + *rtd_Mode_RL = 60U; + + /* DataStoreWrite: '/Data Store Write8' incorporates: + * Constant: '/Valve open' + */ + *rtd_Valve_3_way = 1U; + + /* DataStoreWrite: '/Data Store Write9' incorporates: + * Constant: '/Valve open' + */ + *rtd_Valve_2_way = 1U; + + /* MATLAB Function: '/g_assSTART_COOLANT_STEP0_TO_1 ' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + g_assSTART_COOLANT_STEP0_TO_1_j(*rtd_LEVEL, &rtb_out_nl); + + /* Switch: '/Switch1' incorporates: + * Constant: '/LO' + * Constant: '/exit algorithm' + * DataStoreRead: '/Data Store Read11' + * DataStoreRead: '/Data Store Read12' + * Logic: '/Logical Operator1' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator2' + * RelationalOperator: '/Relational Operator3' + */ + if ((*rtd_CCU_MODE_RR != 1) || (*rtd_LO_HI_MODE_RR == 1)) { + *rty_step1 = 3; + } else { + *rty_step1 = (int8_t)(*rtd_ECT > rtb_out_nl); + } + + /* End of Switch: '/Switch1' */ +} + +/* + * Output and update for atomic system: + * '/2 way valve' + * '/2 way valve' + * '/2 way valve' + * '/2 way valve' + * '/2 way valve' + * '/2 way valve' + * '/2 way valve' + * '/2 way valve' + * '/2 way valve' + * '/2 way valve' + * ... + */ +void uwayvalve(uint8_t rtu_LVL, uint8_t *rty_out) +{ + int32_t tmp; + + /* : out = g_aucSTART_2WAY_OPEN(LVL + 1); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + *rty_out = g_aucSTART_2WAY_OPEN[tmp - 1]; +} + +/* + * Output and update for atomic system: + * '/Dtg_rear' + * '/Dtg_rear' + * '/Dtg_rear' + * '/Dtg_rear' + * '/Dtg_rear' + * '/Dtg_rear' + */ +void Dtg_rear(uint8_t rtu_LVL, uint8_t *rty_out) +{ + int32_t tmp; + + /* : out = g_aucSTART_DUCT_TGT_STEP2_RX(LVL + 1); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + *rty_out = g_aucSTART_DUCT_TGT_STEP2_RX[tmp - 1]; +} + +/* + * Output and update for atomic system: + * '/Incar temp goto from step 1 to step 2 ' + * '/Incar temp goto from step 1 to step 2 ' + * '/Incar temp goto from step 1 to step 2 ' + * '/Incar temp goto from step 1 to step 2 ' + * '/Incar temp goto from step 1 to step 2 ' + * '/Incar temp goto from step 1 to step 2 ' + */ +void Incartempgotofromstep1tostep2_m(uint8_t rtu_LVL, int16_t *rty_out) +{ + int32_t tmp; + int32_t tmp_0; + + /* : out = int16(g_assSTART_INCAR_STEP1_TO_2(LVL + 1 + 6)); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + tmp_0 = (int32_t)((uint32_t)tmp + 6U); + if ((uint32_t)tmp + 6U > 255U) { + tmp_0 = 255; + } + + *rty_out = g_assSTART_INCAR_STEP1_TO_2[tmp_0 - 1]; +} + +/* + * Output and update for atomic system: + * '/Time goto from step 1 to step 2 ' + * '/Time goto from step 1 to step 2 ' + * '/Time goto from step 1 to step 2 ' + * '/Time goto from step 1 to step 2 ' + * '/Time goto from step 1 to step 2 ' + * '/Time goto from step 1 to step 2 ' + * '/Time goto from step 1 to step 2 ' + * '/Time goto from step 1 to step 2 ' + * '/Time goto from step 1 to step 2 ' + * '/Time goto from step 1 to step 2 ' + * ... + */ +void Timegotofromstep1tostep2_n(uint8_t rtu_LVL, int16_t *rty_out) +{ + int32_t tmp; + int32_t tmp_0; + uint16_t tmp_1; + + /* : out = int16(g_ausSTART_TIME_STEP1_TO_2(LVL + 1 + 6)); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + tmp_0 = (int32_t)((uint32_t)tmp + 6U); + if ((uint32_t)tmp + 6U > 255U) { + tmp_0 = 255; + } + + tmp_1 = g_ausSTART_TIME_STEP1_TO_2[tmp_0 - 1]; + if (tmp_1 > 32767) { + tmp_1 = 32767U; + } + + *rty_out = (int16_t)tmp_1; +} + +/* + * Output and update for atomic system: + * '/mode rear step 1' + * '/mode rear step 1' + * '/mode rear step 1' + * '/mode rear step 1' + * '/mode rear step 1' + * '/mode rear step 1' + */ +void moderearstep1(uint8_t rtu_LVL, uint8_t *rty_out) +{ + int32_t tmp; + int32_t tmp_0; + + /* : out = g_aucSTART_VALVE_IDX_STEP1(LVL + 1 + 6); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + tmp_0 = (int32_t)((uint32_t)tmp + 6U); + if ((uint32_t)tmp + 6U > 255U) { + tmp_0 = 255; + } + + *rty_out = g_aucSTART_VALVE_IDX_STEP1[tmp_0 - 1]; +} + +/* + * System initialize for action system: + * '/Level 0' + * '/Level 1' + */ +void Level0_c_Init(DW_Level0_h *localDW) +{ + /* SystemInitialize for MATLAB Function: '/MATLAB Function1' */ + MATLABFunction1_Init(&localDW->sf_MATLABFunction1); +} + +/* + * Output and update for action system: + * '/Level 0' + * '/Level 1' + */ +void Level0_g(int8_t *rty_step, uint8_t *rtd_Blower_RL, uint8_t *rtd_Blower_RR, + const uint8_t *rtd_CCU_MODE_RR, uint16_t *rtd_Dtg_RL, uint16_t + *rtd_Dtg_RR, const int16_t *rtd_Incar_RR, uint8_t + *rtd_Incar_filter_down_value, uint8_t *rtd_Incar_filter_up_value, + const uint8_t *rtd_LEVEL, const uint8_t *rtd_LO_HI_MODE_RR, + uint8_t *rtd_Mode_RL, uint8_t *rtd_Mode_RR, double + *rtd_Recirculation, uint8_t *rtd_Valve_2_way, const uint32_t + *rtd_t_now, DW_Level0_h *localDW) +{ + int32_t tmp; + int16_t rtb_out_a1k; + int16_t rtb_out_pb; + uint8_t rtb_out_ng; + bool rtb_timer_out_b; + + /* DataStoreWrite: '/Data Store Write9' incorporates: + * DataStoreRead: '/Data Store Read6' + * MATLAB Function: '/2 way valve' + */ + uwayvalve(*rtd_LEVEL, rtd_Valve_2_way); + + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataStoreRead: '/Data Store Read1' + * MATLAB Function: '/incar filter up' + */ + incarfilterup_j(*rtd_LEVEL, rtd_Incar_filter_up_value); + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataStoreRead: '/Data Store Read2' + * MATLAB Function: '/incar filter down' + */ + incarfilterdown_m(*rtd_LEVEL, rtd_Incar_filter_down_value); + + /* MATLAB Function: '/mode rear step 1' incorporates: + * DataStoreRead: '/Data Store Read5' + */ + moderearstep1(*rtd_LEVEL, &rtb_out_ng); + + /* DataStoreWrite: '/Data Store Write2' */ + *rtd_Mode_RR = rtb_out_ng; + + /* DataStoreWrite: '/Data Store Write3' */ + *rtd_Mode_RL = rtb_out_ng; + + /* MATLAB Function: '/blower rear' incorporates: + * DataStoreRead: '/Data Store Read7' + */ + /* : out = g_ausSTART_BLR_AF_STEP12_R(LVL + 1); */ + tmp = (int32_t)(*rtd_LEVEL + 1U); + if (*rtd_LEVEL + 1U > 255U) { + tmp = 255; + } + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * DataStoreWrite: '/Data Store Write5' + * MATLAB Function: '/blower rear' + */ + *rtd_Blower_RR = (uint8_t)g_ausSTART_BLR_AF_STEP12_R[tmp - 1]; + + /* DataStoreWrite: '/Data Store Write6' incorporates: + * DataStoreWrite: '/Data Store Write5' + */ + *rtd_Blower_RL = *rtd_Blower_RR; + + /* MATLAB Function: '/Dtg_rear' incorporates: + * DataStoreRead: '/Data Store Read8' + */ + Dtg_rear(*rtd_LEVEL, &rtb_out_ng); + + /* Gain: '/Gain' incorporates: + * DataStoreWrite: '/Data Store Write10' + */ + *rtd_Dtg_RR = (uint16_t)(10U * rtb_out_ng); + + /* DataStoreWrite: '/Data Store Write11' incorporates: + * DataStoreWrite: '/Data Store Write10' + */ + *rtd_Dtg_RL = *rtd_Dtg_RR; + + /* DataStoreWrite: '/Data Store Write7' incorporates: + * Constant: '/Recirc logic Partial REC' + */ + *rtd_Recirculation = 1.0; + + /* MATLAB Function: '/Incar temp goto from step 1 to step 2 ' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + Incartempgotofromstep1tostep2_m(*rtd_LEVEL, &rtb_out_pb); + + /* MATLAB Function: '/Time goto from step 1 to step 2 ' incorporates: + * DataStoreRead: '/Data Store Read4' + */ + Timegotofromstep1tostep2_n(*rtd_LEVEL, &rtb_out_a1k); + + /* MATLAB Function: '/MATLAB Function1' incorporates: + * DataStoreRead: '/Data Store Read9' + * Gain: '/ ' + */ + MATLABFunction1(*rtd_t_now, (uint16_t)(1000 * rtb_out_a1k), &rtb_timer_out_b, + &localDW->sf_MATLABFunction1); + + /* Switch: '/Switch1' incorporates: + * Constant: '/exit algorithm' + * Constant: '/not LO or HI' + * Constant: '/stay at step 1' + * DataStoreRead: '/Data Store Read11' + * DataStoreRead: '/Data Store Read12' + * Logic: '/Logical Operator' + * Logic: '/Logical Operator1' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator2' + * RelationalOperator: '/Relational Operator3' + * Switch: '/Switch' + */ + if ((*rtd_CCU_MODE_RR != 1) || (*rtd_LO_HI_MODE_RR != 0)) { + *rty_step = 3; + } else if ((*rtd_Incar_RR < rtb_out_pb) || rtb_timer_out_b) { + /* Switch: '/Switch' incorporates: + * Constant: '/go to next step' + */ + *rty_step = 2; + } else { + *rty_step = 1; + } + + /* End of Switch: '/Switch1' */ +} + +/* + * Output and update for atomic system: + * '/blower start finish' + * '/blower start finish' + * '/blower start finish' + * '/blower start finish' + */ +void blowerstartfinish(uint8_t rtu_LVL, uint16_t rty_out[2]) +{ + int32_t tmp; + int32_t tmp_0; + + /* : start = g_ausSTART_BLR_AF_STEP12_R(LVL + 1); */ + /* : finish = g_ausSTART_BLR_AF_STEP12_R(LVL + 1 + 6); */ + /* : out = [start, finish]; */ + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + rty_out[0] = g_ausSTART_BLR_AF_STEP12_R[tmp_0 - 1]; + tmp_0 = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp_0 = 255; + } + + tmp = (int32_t)((uint32_t)tmp_0 + 6U); + if ((uint32_t)tmp_0 + 6U > 255U) { + tmp = 255; + } + + rty_out[1] = g_ausSTART_BLR_AF_STEP12_R[tmp - 1]; +} + +/* + * Output and update for atomic system: + * '/ECT min max' + * '/ECT min max' + * '/ECT min max' + */ +void ECTminmax_j(uint8_t rtu_LVL, int16_t rty_out[2]) +{ + int32_t tmp; + + /* : min = int16(g_assSTART_COOLANT_STEP0_TO_1(LVL + 3)); */ + /* : max = int16(g_assSTART_COOLANT_TO_STEP2(3)); */ + /* : out = [min, max]; */ + tmp = (int32_t)(rtu_LVL + 3U); + if (rtu_LVL + 3U > 255U) { + tmp = 255; + } + + rty_out[0] = g_assSTART_COOLANT_STEP0_TO_1[tmp - 1]; + rty_out[1] = g_assSTART_COOLANT_TO_STEP2[2]; +} + +/* + * System initialize for action system: + * '/Level 4' + * '/Level 5' + */ +void Level4_b_Init(DW_Level4_h *localDW) +{ + /* SystemInitialize for MATLAB Function: '/MATLAB Function1' */ + MATLABFunction1_Init(&localDW->sf_MATLABFunction1); +} + +/* + * Output and update for action system: + * '/Level 4' + * '/Level 5' + */ +void Level4_m(int8_t *rty_step, uint8_t *rtd_Blower_RL, uint8_t *rtd_Blower_RR, + const uint8_t *rtd_CCU_MODE_RR, uint16_t *rtd_Dtg_RL, uint16_t + *rtd_Dtg_RR, const int16_t *rtd_ECT, const int16_t *rtd_Incar_RR, + uint8_t *rtd_Incar_filter_down_value, uint8_t + *rtd_Incar_filter_up_value, const uint8_t *rtd_LEVEL, const + uint8_t *rtd_LO_HI_MODE_RR, uint8_t *rtd_Mode_RL, uint8_t + *rtd_Mode_RR, double *rtd_Recirculation, uint8_t *rtd_Valve_2_way, + const uint32_t *rtd_t_now, DW_Level4_h *localDW) +{ + int16_t rtb_out_fe[2]; + int16_t rtb_out_ip; + int16_t rtb_out_kx; + uint16_t rtb_out_kn[2]; + uint8_t rtb_out_f5; + bool rtb_timer_out_b; + + /* DataStoreWrite: '/Data Store Write9' incorporates: + * DataStoreRead: '/Data Store Read6' + * MATLAB Function: '/2 way valve' + */ + uwayvalve(*rtd_LEVEL, rtd_Valve_2_way); + + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataStoreRead: '/Data Store Read1' + * MATLAB Function: '/incar filter up' + */ + incarfilterup_j(*rtd_LEVEL, rtd_Incar_filter_up_value); + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataStoreRead: '/Data Store Read2' + * MATLAB Function: '/incar filter down' + */ + incarfilterdown_m(*rtd_LEVEL, rtd_Incar_filter_down_value); + + /* MATLAB Function: '/mode rear step 1' incorporates: + * DataStoreRead: '/Data Store Read5' + */ + moderearstep1(*rtd_LEVEL, &rtb_out_f5); + + /* DataStoreWrite: '/Data Store Write2' */ + *rtd_Mode_RR = rtb_out_f5; + + /* DataStoreWrite: '/Data Store Write3' */ + *rtd_Mode_RL = rtb_out_f5; + + /* MATLAB Function: '/blower start finish' incorporates: + * DataStoreRead: '/Data Store Read7' + */ + blowerstartfinish(*rtd_LEVEL, rtb_out_kn); + + /* MATLAB Function: '/ECT min max' incorporates: + * DataStoreRead: '/Data Store Read7' + */ + ECTminmax_j(*rtd_LEVEL, rtb_out_fe); + + /* Lookup_n-D: '/blower ECT' incorporates: + * DataStoreRead: '/engine coolant temp' + */ + rtb_out_kx = look1_is16lu64n32tu16Ds32Is16_binlcs(*rtd_ECT, rtb_out_fe, + rtb_out_kn, 1U); + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * DataStoreWrite: '/Data Store Write5' + * DataTypeConversion: '/Data Type Conversion1' + */ + *rtd_Blower_RR = (uint8_t)rtb_out_kx; + + /* DataStoreWrite: '/Data Store Write6' incorporates: + * DataStoreWrite: '/Data Store Write5' + */ + *rtd_Blower_RL = *rtd_Blower_RR; + + /* MATLAB Function: '/Dtg_rear' incorporates: + * DataStoreRead: '/Data Store Read8' + */ + Dtg_rear(*rtd_LEVEL, &rtb_out_f5); + + /* Gain: '/Gain' incorporates: + * DataStoreWrite: '/Data Store Write10' + */ + *rtd_Dtg_RR = (uint16_t)(10U * rtb_out_f5); + + /* DataStoreWrite: '/Data Store Write11' incorporates: + * DataStoreWrite: '/Data Store Write10' + */ + *rtd_Dtg_RL = *rtd_Dtg_RR; + + /* DataStoreWrite: '/Data Store Write7' incorporates: + * Constant: '/Recirc logic Partial REC' + */ + *rtd_Recirculation = 1.0; + + /* MATLAB Function: '/Incar temp goto from step 1 to step 2 ' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + Incartempgotofromstep1tostep2_m(*rtd_LEVEL, &rtb_out_ip); + + /* MATLAB Function: '/Time goto from step 1 to step 2 ' incorporates: + * DataStoreRead: '/Data Store Read4' + */ + Timegotofromstep1tostep2_n(*rtd_LEVEL, &rtb_out_kx); + + /* MATLAB Function: '/MATLAB Function1' incorporates: + * DataStoreRead: '/Data Store Read9' + * Gain: '/ ' + */ + MATLABFunction1(*rtd_t_now, (uint16_t)(1000 * rtb_out_kx), &rtb_timer_out_b, + &localDW->sf_MATLABFunction1); + + /* Switch: '/Switch1' incorporates: + * Constant: '/LO' + * Constant: '/exit algorithm' + * Constant: '/stay at step 1' + * DataStoreRead: '/Data Store Read11' + * DataStoreRead: '/Data Store Read12' + * Logic: '/Logical Operator' + * Logic: '/Logical Operator1' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator3' + * RelationalOperator: '/Relational Operator4' + * Switch: '/Switch' + */ + if ((*rtd_CCU_MODE_RR != 1) || (*rtd_LO_HI_MODE_RR == 1)) { + *rty_step = 3; + } else if ((*rtd_Incar_RR > rtb_out_ip) || rtb_timer_out_b) { + /* Switch: '/Switch' incorporates: + * Constant: '/go to next step' + */ + *rty_step = 2; + } else { + *rty_step = 1; + } + + /* End of Switch: '/Switch1' */ +} + +/* + * Output and update for atomic system: + * '/time for step' + * '/time for step' + * '/time for step' + * '/time for step' + * '/time for step' + * '/time for step' + */ +void timeforstep_k(uint8_t rtu_LVL, uint8_t *rty_out) +{ + int32_t tmp; + int32_t tmp_0; + + /* : out = g_aucSTART_DUCT_TGT_STEP2_RX(LVL + 1 + 6); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + tmp_0 = (int32_t)((uint32_t)tmp + 6U); + if ((uint32_t)tmp + 6U > 255U) { + tmp_0 = 255; + } + + *rty_out = g_aucSTART_DUCT_TGT_STEP2_RX[tmp_0 - 1]; +} + +/* + * Output and update for atomic system: + * '/blower step' + * '/blower step' + * '/blower step' + * '/blower step' + * '/blower step' + * '/blower step' + */ +void blowerstep_c(uint8_t rtu_LVL, uint16_t *rty_out) +{ + int32_t tmp; + + /* : out = g_ausSTART_BLR_SPD_STEP2_R(LVL + 1); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + *rty_out = g_ausSTART_BLR_SPD_STEP2_R[tmp - 1]; +} + +/* + * Output and update for atomic system: + * '/blower time for step' + * '/blower time for step' + * '/blower time for step' + * '/blower time for step' + * '/blower time for step' + * '/blower time for step' + */ +void blowertimeforstep_k(uint8_t rtu_LVL, uint16_t *rty_out) +{ + int32_t tmp; + int32_t tmp_0; + + /* : out = g_ausSTART_BLR_SPD_STEP2_R(LVL + 1 + 6); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + tmp_0 = (int32_t)((uint32_t)tmp + 6U); + if ((uint32_t)tmp + 6U > 255U) { + tmp_0 = 255; + } + + *rty_out = g_ausSTART_BLR_SPD_STEP2_R[tmp_0 - 1]; +} + +/* + * Output and update for atomic system: + * '/step' + * '/step' + * '/step' + * '/step' + * '/step' + * '/step' + */ +void step_a(uint8_t rtu_LVL, uint8_t *rty_out) +{ + int32_t tmp; + + /* : out = g_aucSTART_VALVE_CHANGE_SPD_R(LVL + 1); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + *rty_out = g_aucSTART_VALVE_CHANGE_SPD_R[tmp - 1]; +} + +/* + * Output and update for atomic system: + * '/time for step' + * '/time for step' + * '/time for step' + * '/time for step' + * '/time for step' + * '/time for step' + */ +void timeforstep_dm(uint8_t rtu_LVL, uint8_t *rty_out) +{ + int32_t tmp; + int32_t tmp_0; + + /* : out = g_aucSTART_VALVE_CHANGE_SPD_R(LVL + 1 + 6); */ + tmp = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + tmp = 255; + } + + tmp_0 = (int32_t)((uint32_t)tmp + 6U); + if ((uint32_t)tmp + 6U > 255U) { + tmp_0 = 255; + } + + *rty_out = g_aucSTART_VALVE_CHANGE_SPD_R[tmp_0 - 1]; +} + +/* + * System initialize for action system: + * '/Level 0' + * '/Level 1' + */ +void Level0_h_Init(DW_Level0_hr *localDW) +{ + /* SystemInitialize for MATLAB Function: '/MATLAB Function1' */ + MATLABFunction1_Init(&localDW->sf_MATLABFunction1); +} + +/* + * Output and update for action system: + * '/Level 0' + * '/Level 1' + */ +void Level0_a(int8_t *rty_step, uint8_t *rtd_Blower_RL, uint8_t *rtd_Blower_RR, + const uint16_t *rtd_Blower_logic_RR, const uint8_t + *rtd_CCU_MODE_FL, uint16_t *rtd_Dtg_RL, uint16_t *rtd_Dtg_RR, + const int16_t *rtd_Dtg_logic_RR, uint8_t + *rtd_Incar_filter_down_value, uint8_t *rtd_Incar_filter_up_value, + const uint8_t *rtd_LEVEL, const uint8_t *rtd_LO_HI_MODE_FL, + uint8_t *rtd_Mode_RL, uint8_t *rtd_Mode_RR, const uint8_t + *rtd_Mode_logic_RR, double *rtd_Recirculation, uint8_t + *rtd_Valve_2_way, const uint32_t *rtd_t_now, DW_Level0_hr *localDW) +{ + int32_t tmp; + int16_t rtb_out_nx; + uint16_t rtb_out_fc; + uint16_t rtb_out_ijy; + uint8_t rtb_out_csf; + uint8_t rtb_out_pe; + bool rtb_LogicalOperator1_e4; + bool rtb_timer_out_p; + + /* DataStoreWrite: '/Data Store Write9' incorporates: + * DataStoreRead: '/Data Store Read6' + * MATLAB Function: '/2 way valve' + */ + uwayvalve(*rtd_LEVEL, rtd_Valve_2_way); + + /* Sum: '/Add' incorporates: + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + */ + rtb_out_nx = (int16_t)((*rtd_Dtg_RR - *rtd_Dtg_logic_RR) >> 1); + + /* Abs: '/Abs' */ + if (rtb_out_nx < 0) { + rtb_out_nx = (int16_t)-rtb_out_nx; + } + + /* End of Abs: '/Abs' */ + + /* MATLAB Function: '/step' incorporates: + * DataStoreRead: '/Data Store Read8' + */ + Dtg_rear(*rtd_LEVEL, &rtb_out_pe); + + /* MATLAB Function: '/time for step' incorporates: + * DataStoreRead: '/Data Store Read8' + */ + timeforstep_k(*rtd_LEVEL, &rtb_out_csf); + + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + * Constant: '/epsilon' + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + * DataStoreRead: '/ ' + * DataStoreWrite: '/Data Store Write10' + * Gain: '/Gain' + * Product: '/Product1' + * Product: '/change rate (dtg//sec)' + * Product: '/ ' + * Product: '/ ' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + * Sum: '/Subtract' + * Switch: '/Switch' + * UnitDelay: '/Unit Delay' + */ + if ((double)rtb_out_nx * 2.0 <= 0.01) { + *rtd_Dtg_RR = (uint16_t)*rtd_Dtg_logic_RR; + } else { + if (*rtd_Dtg_RR <= *rtd_Dtg_logic_RR) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + */ + tmp = 1; + } else { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant1' + */ + tmp = -1; + } + + *rtd_Dtg_RR = (uint16_t)rt_roundd(10.0 * (double)rtb_out_pe / (double) + rtb_out_csf / 1000.0 * (double)(*rtd_t_now - localDW->UnitDelay_DSTATE) * + (double)tmp + (double)*rtd_Dtg_RR); + } + + /* End of Switch: '/Switch' */ + + /* DataStoreWrite: '/Data Store Write11' incorporates: + * DataStoreWrite: '/Data Store Write10' + */ + *rtd_Dtg_RL = *rtd_Dtg_RR; + + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataStoreRead: '/Data Store Read1' + * MATLAB Function: '/incar filter up' + */ + incarfilterup_j(*rtd_LEVEL, rtd_Incar_filter_up_value); + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataStoreRead: '/Data Store Read2' + * MATLAB Function: '/incar filter down' + */ + incarfilterdown_m(*rtd_LEVEL, rtd_Incar_filter_down_value); + + /* Sum: '/Add' incorporates: + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + */ + rtb_out_pe = (uint8_t)(*rtd_Mode_RR - *rtd_Mode_logic_RR); + + /* RelationalOperator: '/Relational Operator' incorporates: + * Constant: '/epsilon' + */ + rtb_timer_out_p = (rtb_out_pe <= 0.01); + + /* MATLAB Function: '/step' incorporates: + * DataStoreRead: '/Data Store Read5' + */ + step_a(*rtd_LEVEL, &rtb_out_csf); + + /* MATLAB Function: '/time for step' incorporates: + * DataStoreRead: '/Data Store Read5' + */ + timeforstep_dm(*rtd_LEVEL, &rtb_out_pe); + + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + * DataStoreRead: '/ ' + * DataStoreWrite: '/Data Store Write2' + * Product: '/Product1' + * Product: '/change rate (step//sec)' + * Product: '/ ' + * Product: '/ ' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + * Sum: '/Subtract' + * Switch: '/Switch' + * UnitDelay: '/Unit Delay' + */ + if (rtb_timer_out_p) { + *rtd_Mode_RR = *rtd_Mode_logic_RR; + } else { + if (*rtd_Mode_RR <= *rtd_Mode_logic_RR) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + */ + tmp = 1; + } else { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant1' + */ + tmp = -1; + } + + *rtd_Mode_RR = (uint8_t)((double)rtb_out_csf / (double)rtb_out_pe / 1000.0 * + (double)(*rtd_t_now - localDW->UnitDelay_DSTATE_k) * (double)tmp + (double)* + rtd_Mode_RR); + } + + /* End of Switch: '/Switch' */ + + /* DataStoreWrite: '/Data Store Write3' incorporates: + * DataStoreWrite: '/Data Store Write2' + */ + *rtd_Mode_RL = *rtd_Mode_RR; + + /* Sum: '/Add' incorporates: + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + */ + rtb_out_ijy = (uint16_t)(*rtd_Blower_RR - *rtd_Blower_logic_RR); + + /* RelationalOperator: '/Relational Operator' incorporates: + * Constant: '/epsilon' + */ + rtb_timer_out_p = (rtb_out_ijy <= 0.01); + + /* MATLAB Function: '/blower step' incorporates: + * DataStoreRead: '/Data Store Read7' + */ + blowerstep_c(*rtd_LEVEL, &rtb_out_fc); + + /* MATLAB Function: '/blower time for step' incorporates: + * DataStoreRead: '/Data Store Read7' + */ + blowertimeforstep_k(*rtd_LEVEL, &rtb_out_ijy); + + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + * DataStoreRead: '/ ' + * DataStoreWrite: '/Data Store Write5' + * Product: '/Product1' + * Product: '/change rate (step//sec)' + * Product: '/ ' + * Product: '/ ' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + * Sum: '/Subtract' + * Switch: '/Switch' + * UnitDelay: '/Unit Delay' + */ + if (rtb_timer_out_p) { + *rtd_Blower_RR = (uint8_t)*rtd_Blower_logic_RR; + } else { + if (*rtd_Blower_RR <= *rtd_Blower_logic_RR) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + */ + tmp = 1; + } else { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant1' + */ + tmp = -1; + } + + *rtd_Blower_RR = (uint8_t)((double)rtb_out_fc / (double)rtb_out_ijy / 1000.0 + * (double)(*rtd_t_now - localDW->UnitDelay_DSTATE_n) * (double)tmp + + (double)*rtd_Blower_RR); + } + + /* End of Switch: '/Switch' */ + + /* DataStoreWrite: '/Data Store Write6' incorporates: + * DataStoreWrite: '/Data Store Write5' + */ + *rtd_Blower_RL = *rtd_Blower_RR; + + /* DataStoreWrite: '/Data Store Write7' incorporates: + * Constant: '/Recirc logic Partial REC' + */ + *rtd_Recirculation = 1.0; + + /* RelationalOperator: '/Relational Operator2' incorporates: + * DataStoreRead: '/Data Store Read11' + */ + rtb_timer_out_p = (*rtd_CCU_MODE_FL != 1); + + /* Logic: '/Logical Operator1' incorporates: + * Constant: '/not LO or HI' + * DataStoreRead: '/Data Store Read12' + * RelationalOperator: '/Relational Operator3' + */ + rtb_LogicalOperator1_e4 = (rtb_timer_out_p || (*rtd_LO_HI_MODE_FL != 0)); + + /* MATLAB Function: '/Time goto from step 1 to step 2 ' incorporates: + * DataStoreRead: '/Data Store Read4' + */ + Timegotofromstep1tostep2_n(*rtd_LEVEL, &rtb_out_nx); + + /* MATLAB Function: '/MATLAB Function1' incorporates: + * DataStoreRead: '/Data Store Read3' + * Gain: '/ ' + */ + MATLABFunction1(*rtd_t_now, (uint16_t)(1000 * rtb_out_nx), &rtb_timer_out_p, + &localDW->sf_MATLABFunction1); + + /* Switch: '/Switch1' incorporates: + * Constant: '/exit algorithm' + * Constant: '/stay at step' + * Switch: '/Switch' + */ + if (rtb_LogicalOperator1_e4) { + *rty_step = 3; + } else if (rtb_timer_out_p) { + /* Switch: '/Switch' incorporates: + * Constant: '/go to next step' + */ + *rty_step = 3; + } else { + *rty_step = 2; + } + + /* End of Switch: '/Switch1' */ + + /* Update for UnitDelay: '/Unit Delay' incorporates: + * DataStoreRead: '/ ' + */ + localDW->UnitDelay_DSTATE = *rtd_t_now; + + /* Update for UnitDelay: '/Unit Delay' incorporates: + * DataStoreRead: '/ ' + */ + localDW->UnitDelay_DSTATE_k = *rtd_t_now; + + /* Update for UnitDelay: '/Unit Delay' incorporates: + * DataStoreRead: '/ ' + */ + localDW->UnitDelay_DSTATE_n = *rtd_t_now; +} + +/* + * System initialize for action system: + * '/Level 2' + * '/Level 3' + * '/Level 4' + * '/Level 5' + */ +void Level2_j_Init(DW_Level2_j *localDW) +{ + /* SystemInitialize for MATLAB Function: '/MATLAB Function1' */ + MATLABFunction1_Init(&localDW->sf_MATLABFunction1); +} + +/* + * Output and update for action system: + * '/Level 2' + * '/Level 3' + * '/Level 4' + * '/Level 5' + */ +void Level2_f(int8_t *rty_step, uint8_t *rtd_Blower_RL, uint8_t *rtd_Blower_RR, + const uint16_t *rtd_Blower_logic_RR, const uint8_t + *rtd_CCU_MODE_FL, uint16_t *rtd_Dtg_RL, uint16_t *rtd_Dtg_RR, + const int16_t *rtd_Dtg_logic_RR, const bool *rtd_HI_logic_on, + uint8_t *rtd_Incar_filter_down_value, uint8_t + *rtd_Incar_filter_up_value, const uint8_t *rtd_LEVEL, const + uint8_t *rtd_LO_HI_MODE_FL, uint8_t *rtd_Mode_RL, uint8_t + *rtd_Mode_RR, const uint8_t *rtd_Mode_logic_RR, double + *rtd_Recirculation, uint8_t *rtd_Valve_2_way, const uint32_t + *rtd_t_now, DW_Level2_j *localDW) +{ + int32_t tmp; + int16_t rtb_out_en; + uint16_t rtb_out_be2; + uint16_t rtb_out_lf5; + uint8_t rtb_out_fs; + uint8_t rtb_out_in; + bool rtb_RelationalOperator2_ib; + + /* DataStoreWrite: '/Data Store Write9' incorporates: + * DataStoreRead: '/Data Store Read6' + * MATLAB Function: '/2 way valve' + */ + uwayvalve(*rtd_LEVEL, rtd_Valve_2_way); + + /* Sum: '/Add' incorporates: + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + */ + rtb_out_en = (int16_t)((*rtd_Dtg_RR - *rtd_Dtg_logic_RR) >> 1); + + /* Abs: '/Abs' */ + if (rtb_out_en < 0) { + rtb_out_en = (int16_t)-rtb_out_en; + } + + /* End of Abs: '/Abs' */ + + /* MATLAB Function: '/step' incorporates: + * DataStoreRead: '/Data Store Read8' + */ + Dtg_rear(*rtd_LEVEL, &rtb_out_fs); + + /* MATLAB Function: '/time for step' incorporates: + * DataStoreRead: '/Data Store Read8' + */ + timeforstep_k(*rtd_LEVEL, &rtb_out_in); + + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + * Constant: '/epsilon' + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + * DataStoreRead: '/ ' + * DataStoreWrite: '/Data Store Write10' + * Gain: '/Gain' + * Product: '/Product1' + * Product: '/change rate (dtg//sec)' + * Product: '/ ' + * Product: '/ ' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + * Sum: '/Subtract' + * Switch: '/Switch' + * UnitDelay: '/Unit Delay' + */ + if ((double)rtb_out_en * 2.0 <= 0.01) { + *rtd_Dtg_RR = (uint16_t)*rtd_Dtg_logic_RR; + } else { + if (*rtd_Dtg_RR <= *rtd_Dtg_logic_RR) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + */ + tmp = 1; + } else { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant1' + */ + tmp = -1; + } + + *rtd_Dtg_RR = (uint16_t)rt_roundd(10.0 * (double)rtb_out_fs / (double) + rtb_out_in / 1000.0 * (double)(*rtd_t_now - localDW->UnitDelay_DSTATE) * + (double)tmp + (double)*rtd_Dtg_RR); + } + + /* End of Switch: '/Switch' */ + + /* DataStoreWrite: '/Data Store Write11' incorporates: + * DataStoreWrite: '/Data Store Write10' + */ + *rtd_Dtg_RL = *rtd_Dtg_RR; + + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataStoreRead: '/Data Store Read1' + * MATLAB Function: '/incar filter up' + */ + incarfilterup_j(*rtd_LEVEL, rtd_Incar_filter_up_value); + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataStoreRead: '/Data Store Read2' + * MATLAB Function: '/incar filter down' + */ + incarfilterdown_m(*rtd_LEVEL, rtd_Incar_filter_down_value); + + /* Sum: '/Add' incorporates: + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + */ + rtb_out_fs = (uint8_t)(*rtd_Mode_RR - *rtd_Mode_logic_RR); + + /* RelationalOperator: '/Relational Operator' incorporates: + * Constant: '/epsilon' + */ + rtb_RelationalOperator2_ib = (rtb_out_fs <= 0.01); + + /* MATLAB Function: '/step' incorporates: + * DataStoreRead: '/Data Store Read5' + */ + step_a(*rtd_LEVEL, &rtb_out_in); + + /* MATLAB Function: '/time for step' incorporates: + * DataStoreRead: '/Data Store Read5' + */ + timeforstep_dm(*rtd_LEVEL, &rtb_out_fs); + + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + * DataStoreRead: '/ ' + * DataStoreWrite: '/Data Store Write2' + * Product: '/Product1' + * Product: '/change rate (step//sec)' + * Product: '/ ' + * Product: '/ ' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + * Sum: '/Subtract' + * Switch: '/Switch' + * UnitDelay: '/Unit Delay' + */ + if (rtb_RelationalOperator2_ib) { + *rtd_Mode_RR = *rtd_Mode_logic_RR; + } else { + if (*rtd_Mode_RR <= *rtd_Mode_logic_RR) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + */ + tmp = 1; + } else { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant1' + */ + tmp = -1; + } + + *rtd_Mode_RR = (uint8_t)((double)rtb_out_in / (double)rtb_out_fs / 1000.0 * + (double)(*rtd_t_now - localDW->UnitDelay_DSTATE_n) * (double)tmp + (double)* + rtd_Mode_RR); + } + + /* End of Switch: '/Switch' */ + + /* DataStoreWrite: '/Data Store Write3' incorporates: + * DataStoreWrite: '/Data Store Write2' + */ + *rtd_Mode_RL = *rtd_Mode_RR; + + /* Sum: '/Add' incorporates: + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + */ + rtb_out_be2 = (uint16_t)(*rtd_Blower_RR - *rtd_Blower_logic_RR); + + /* RelationalOperator: '/Relational Operator' incorporates: + * Constant: '/epsilon' + */ + rtb_RelationalOperator2_ib = (rtb_out_be2 <= 0.01); + + /* MATLAB Function: '/blower step' incorporates: + * DataStoreRead: '/Data Store Read7' + */ + blowerstep_c(*rtd_LEVEL, &rtb_out_lf5); + + /* MATLAB Function: '/blower time for step' incorporates: + * DataStoreRead: '/Data Store Read7' + */ + blowertimeforstep_k(*rtd_LEVEL, &rtb_out_be2); + + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + * DataStoreRead: '/ ' + * DataStoreWrite: '/Data Store Write5' + * Product: '/Product1' + * Product: '/change rate (step//sec)' + * Product: '/ ' + * Product: '/ ' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + * Sum: '/Subtract' + * Switch: '/Switch' + * UnitDelay: '/Unit Delay' + */ + if (rtb_RelationalOperator2_ib) { + *rtd_Blower_RR = (uint8_t)*rtd_Blower_logic_RR; + } else { + if (*rtd_Blower_RR <= *rtd_Blower_logic_RR) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + */ + tmp = 1; + } else { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant1' + */ + tmp = -1; + } + + *rtd_Blower_RR = (uint8_t)((double)rtb_out_lf5 / (double)rtb_out_be2 / + 1000.0 * (double)(*rtd_t_now - localDW->UnitDelay_DSTATE_p) * (double)tmp + + (double)*rtd_Blower_RR); + } + + /* End of Switch: '/Switch' */ + + /* DataStoreWrite: '/Data Store Write6' incorporates: + * DataStoreWrite: '/Data Store Write5' + */ + *rtd_Blower_RL = *rtd_Blower_RR; + + /* DataStoreWrite: '/Data Store Write7' incorporates: + * Constant: '/Recirc logic Partial REC' + */ + *rtd_Recirculation = 1.0; + + /* MATLAB Function: '/Time goto from step 1 to step 2 ' incorporates: + * DataStoreRead: '/Data Store Read4' + */ + Timegotofromstep1tostep2_n(*rtd_LEVEL, &rtb_out_en); + + /* MATLAB Function: '/MATLAB Function1' incorporates: + * DataStoreRead: '/Data Store Read3' + * Gain: '/ ' + */ + MATLABFunction1(*rtd_t_now, (uint16_t)(1000 * rtb_out_en), + &rtb_RelationalOperator2_ib, &localDW->sf_MATLABFunction1); + + /* Switch: '/Switch1' incorporates: + * Constant: '/exit algorithm' + * Constant: '/not LO or HI' + * Constant: '/stay at step' + * DataStoreRead: '/Data Store Read11' + * DataStoreRead: '/Data Store Read12' + * Logic: '/Logical Operator' + * Logic: '/Logical Operator1' + * RelationalOperator: '/Relational Operator2' + * RelationalOperator: '/Relational Operator3' + * Switch: '/Switch' + */ + if ((*rtd_CCU_MODE_FL != 1) || (*rtd_LO_HI_MODE_FL != 0)) { + *rty_step = 3; + } else if (rtb_RelationalOperator2_ib || (*rtd_HI_logic_on)) { + /* Switch: '/Switch' incorporates: + * Constant: '/go to next step' + */ + *rty_step = 3; + } else { + *rty_step = 2; + } + + /* End of Switch: '/Switch1' */ + + /* Update for UnitDelay: '/Unit Delay' incorporates: + * DataStoreRead: '/ ' + */ + localDW->UnitDelay_DSTATE = *rtd_t_now; + + /* Update for UnitDelay: '/Unit Delay' incorporates: + * DataStoreRead: '/ ' + */ + localDW->UnitDelay_DSTATE_n = *rtd_t_now; + + /* Update for UnitDelay: '/Unit Delay' incorporates: + * DataStoreRead: '/ ' + */ + localDW->UnitDelay_DSTATE_p = *rtd_t_now; +} + +/* + * Output and update for atomic system: + * '/func g_assAUTO_STEP_DUCT_TG_U' + * '/func g_assAUTO_STEP_DUCT_TG_U' + */ +void funcg_assAUTO_STEP_DUCT_TG_U(uint8_t rtu_LVL, double rtu_AF_STEP, int16_t + *rty_y) +{ + int32_t i; + int16_t selected_vector[5]; + + /* : switch LVL */ + switch (rtu_LVL) { + case 0U: + /* : case 0 */ + /* : selected_vector = g_assAUTO_STEP_DUCT_TG_U_F_LV0_1(1:5); */ + for (i = 0; i < 5; i++) { + selected_vector[i] = g_assAUTO_STEP_DUCT_TG_U_F_LV0_1[i]; + } + break; + + case 1U: + /* : case 1 */ + /* : selected_vector = g_assAUTO_STEP_DUCT_TG_U_F_LV0_1(6:10); */ + for (i = 0; i < 5; i++) { + selected_vector[i] = g_assAUTO_STEP_DUCT_TG_U_F_LV0_1[i + 5]; + } + break; + + case 2U: + /* : case 2 */ + /* : selected_vector = g_assAUTO_STEP_DUCT_TG_U_F_LV2_3(1:5); */ + for (i = 0; i < 5; i++) { + selected_vector[i] = g_assAUTO_STEP_DUCT_TG_U_F_LV2_3[i]; + } + break; + + case 3U: + /* : case 3 */ + /* : selected_vector = g_assAUTO_STEP_DUCT_TG_U_F_LV2_3(6:10); */ + for (i = 0; i < 5; i++) { + selected_vector[i] = g_assAUTO_STEP_DUCT_TG_U_F_LV2_3[i + 5]; + } + break; + + case 4U: + /* : case 4 */ + /* : selected_vector = g_assAUTO_STEP_DUCT_TG_U_F_LV4_5(1:5); */ + for (i = 0; i < 5; i++) { + selected_vector[i] = g_assAUTO_STEP_DUCT_TG_U_F_LV4_5[i]; + } + break; + + case 5U: + /* : case 5 */ + /* : selected_vector = g_assAUTO_STEP_DUCT_TG_U_F_LV4_5(6:10); */ + for (i = 0; i < 5; i++) { + selected_vector[i] = g_assAUTO_STEP_DUCT_TG_U_F_LV4_5[i + 5]; + } + break; + + default: + /* : otherwise */ + /* : selected_vector = int16(zeros(1,5)); */ + for (i = 0; i < 5; i++) { + selected_vector[i] = 0; + } + break; + } + + /* : y = selected_vector(AF_STEP); */ + *rty_y = selected_vector[(int32_t)rtu_AF_STEP - 1]; +} + +/* + * Output and update for atomic system: + * '/func g_assAUTO_STEP_DUCT_TG_L' + * '/func g_assAUTO_STEP_DUCT_TG_L' + */ +void funcg_assAUTO_STEP_DUCT_TG_L(uint8_t rtu_LVL, double rtu_AF_STEP, int16_t + *rty_y) +{ + int32_t i; + int16_t selected_vector[5]; + + /* : switch LVL */ + switch (rtu_LVL) { + case 0U: + /* : case 0 */ + /* : selected_vector = g_assAUTO_STEP_DUCT_TG_L_F_LV0_1(1:5); */ + for (i = 0; i < 5; i++) { + selected_vector[i] = g_assAUTO_STEP_DUCT_TG_L_F_LV0_1[i]; + } + break; + + case 1U: + /* : case 1 */ + /* : selected_vector = g_assAUTO_STEP_DUCT_TG_L_F_LV0_1(6:10); */ + for (i = 0; i < 5; i++) { + selected_vector[i] = g_assAUTO_STEP_DUCT_TG_L_F_LV0_1[i + 5]; + } + break; + + case 2U: + /* : case 2 */ + /* : selected_vector = g_assAUTO_STEP_DUCT_TG_L_F_LV2_3(1:5); */ + for (i = 0; i < 5; i++) { + selected_vector[i] = g_assAUTO_STEP_DUCT_TG_L_F_LV2_3[i]; + } + break; + + case 3U: + /* : case 3 */ + /* : selected_vector = g_assAUTO_STEP_DUCT_TG_L_F_LV2_3(6:10); */ + for (i = 0; i < 5; i++) { + selected_vector[i] = g_assAUTO_STEP_DUCT_TG_L_F_LV2_3[i + 5]; + } + break; + + case 4U: + /* : case 4 */ + /* : selected_vector = g_assAUTO_STEP_DUCT_TG_L_F_LV4_5(1:5); */ + for (i = 0; i < 5; i++) { + selected_vector[i] = g_assAUTO_STEP_DUCT_TG_L_F_LV4_5[i]; + } + break; + + case 5U: + /* : case 5 */ + /* : selected_vector = g_assAUTO_STEP_DUCT_TG_L_F_LV4_5(6:10); */ + for (i = 0; i < 5; i++) { + selected_vector[i] = g_assAUTO_STEP_DUCT_TG_L_F_LV4_5[i + 5]; + } + break; + + default: + /* : otherwise */ + /* : selected_vector = int16(zeros(1,5)); */ + for (i = 0; i < 5; i++) { + selected_vector[i] = 0; + } + break; + } + + /* : y = selected_vector(AF_STEP); */ + *rty_y = selected_vector[(int32_t)rtu_AF_STEP - 1]; +} + +/* + * Output and update for atomic system: + * '/func g_assAUTO_STEP_DUCT_TG_R' + * '/func g_assAUTO_STEP_DUCT_TG_R' + */ +void funcg_assAUTO_STEP_DUCT_TG_R(uint8_t rtu_LVL, double rtu_AF_STEP, int16_t + *rty_y) +{ + int32_t i; + int16_t selected_vector[5]; + + /* : switch LVL */ + switch (rtu_LVL) { + case 0U: + /* : case 0 */ + /* : selected_vector = g_assAUTO_STEP_DUCT_TG_R_LV0_1(1:5); */ + for (i = 0; i < 5; i++) { + selected_vector[i] = g_assAUTO_STEP_DUCT_TG_R_LV0_1[i]; + } + break; + + case 1U: + /* : case 1 */ + /* : selected_vector = g_assAUTO_STEP_DUCT_TG_R_LV0_1(6:10); */ + for (i = 0; i < 5; i++) { + selected_vector[i] = g_assAUTO_STEP_DUCT_TG_R_LV0_1[i + 5]; + } + break; + + case 2U: + /* : case 2 */ + /* : selected_vector = g_assAUTO_STEP_DUCT_TG_R_LV2_3(1:5); */ + for (i = 0; i < 5; i++) { + selected_vector[i] = g_assAUTO_STEP_DUCT_TG_R_LV2_3[i]; + } + break; + + case 3U: + /* : case 3 */ + /* : selected_vector = g_assAUTO_STEP_DUCT_TG_R_LV2_3(6:10); */ + for (i = 0; i < 5; i++) { + selected_vector[i] = g_assAUTO_STEP_DUCT_TG_R_LV2_3[i + 5]; + } + break; + + case 4U: + /* : case 4 */ + /* : selected_vector = g_assAUTO_STEP_DUCT_TG_R_LV4_5(1:5); */ + for (i = 0; i < 5; i++) { + selected_vector[i] = g_assAUTO_STEP_DUCT_TG_R_LV4_5[i]; + } + break; + + case 5U: + /* : case 5 */ + /* : selected_vector = g_assAUTO_STEP_DUCT_TG_R_LV4_5(6:10); */ + for (i = 0; i < 5; i++) { + selected_vector[i] = g_assAUTO_STEP_DUCT_TG_R_LV4_5[i + 5]; + } + break; + + default: + /* : otherwise */ + /* : selected_vector = int16(zeros(1,5)); */ + for (i = 0; i < 5; i++) { + selected_vector[i] = 0; + } + break; + } + + /* : y = selected_vector(AF_STEP); */ + *rty_y = selected_vector[(int32_t)rtu_AF_STEP - 1]; +} + +/* + * Output and update for atomic system: + * '/correction rate' + * '/correction rate' + */ +void correctionrate(int16_t rtu_SET, uint8_t rtu_LVL, int16_t *rty_y) +{ + int32_t i; + int32_t tmp_0; + int16_t tmp[42]; + + /* : correct_rate = [g_assCORRECT_DUCT_RATE_LV0; g_assCORRECT_DUCT_RATE_LV1; g_assCORRECT_DUCT_RATE_LV2; g_assCORRECT_DUCT_RATE_LV3; g_assCORRECT_DUCT_RATE_LV4; g_assCORRECT_DUCT_RATE_LV5]; */ + /* : y = correct_rate(LVL + 1, idivide(SET - 16 + 1, 2)); */ + for (i = 0; i < 7; i++) { + tmp[6 * i] = g_assCORRECT_DUCT_RATE_LV0[i]; + tmp[6 * i + 1] = g_assCORRECT_DUCT_RATE_LV1[i]; + tmp[6 * i + 2] = g_assCORRECT_DUCT_RATE_LV2[i]; + tmp[6 * i + 3] = g_assCORRECT_DUCT_RATE_LV3[i]; + tmp[6 * i + 4] = g_assCORRECT_DUCT_RATE_LV4[i]; + tmp[6 * i + 5] = g_assCORRECT_DUCT_RATE_LV5[i]; + } + + i = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + i = 255; + } + + tmp_0 = rtu_SET - 16; + if (rtu_SET - 16 < -32768) { + tmp_0 = -32768; + } + + *rty_y = tmp[(((int32_t)trunc(((double)tmp_0 + 1.0) / 2.0) - 1) * 6 + i) - 1]; +} + +/* + * Output and update for atomic system: + * '/is_ending_with_5' + * '/is_ending_with_5' + * '/is_ending_with_5' + * '/is_ending_with_5' + */ +void is_ending_with_5(uint16_t rtu_SET, bool *rty_is_ending_with_5) +{ + /* : is_ending_with_5 = (mod(SET, 10) == 5); */ + *rty_is_ending_with_5 = ((uint16_t)(rtu_SET - (uint32_t)((int32_t)(rtu_SET / + 10U) * 10)) == 5); +} + +/* + * Output and update for atomic system: + * '/ .' + * '/ .' + * '/ .' + * '/ .' + */ +void u(uint8_t rtu_lvl, uint16_t *rty_f_g_ausINCARRATE_FALLING_F) +{ + int32_t tmp; + + /* : f_g_ausINCARRATE_FALLING_F = g_ausINCARRATE_FALLING_F(lvl + 1); */ + tmp = (int32_t)(rtu_lvl + 1U); + if (rtu_lvl + 1U > 255U) { + tmp = 255; + } + + *rty_f_g_ausINCARRATE_FALLING_F = g_ausINCARRATE_FALLING_F[tmp - 1]; +} + +/* + * Output and update for atomic system: + * '/ .' + * '/ .' + * '/ .' + * '/ .' + */ +void u_j(uint8_t rtu_lvl, uint16_t *rty_f_g_ausINCARRATE_FALLING_DIFF_F) +{ + int32_t tmp; + + /* : f_g_ausINCARRATE_FALLING_DIFF_F = g_ausINCARRATE_FALLING_DIFF_F(lvl + 1); */ + tmp = (int32_t)(rtu_lvl + 1U); + if (rtu_lvl + 1U > 255U) { + tmp = 255; + } + + *rty_f_g_ausINCARRATE_FALLING_DIFF_F = g_ausINCARRATE_FALLING_DIFF_F[tmp - 1]; +} + +/* + * Output and update for action system: + * '/ ' + * '/ ' + */ +void u_c(int16_t rtu_temp_raw, uint8_t rtu_lvl, uint16_t *rty_out, double + *rtd_KEEP_FALLING_FL_UNTIL_LIMIT, const double *rtd_Temp_FL_store) +{ + /* If: '/If' incorporates: + * Abs: '/ABS(AMBraw - AMB)' + * DataStoreRead: '/Read temp' + * MATLAB Function: '/AMBRATE_RISING_DIFF[8]' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + */ + /* : f_g_ausINCARRATE_FALLING_DIFF_F = g_ausINCARRATE_FALLING_DIFF_F(8); */ + if (fabs((double)rtu_temp_raw - *rtd_Temp_FL_store) <= + g_ausINCARRATE_FALLING_DIFF_F[7]) { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + *rtd_KEEP_FALLING_FL_UNTIL_LIMIT = 0.0; + + /* SignalConversion generated from: '/out' incorporates: + * MATLAB Function: '/ .' + * Merge: '/Merge' + */ + u(rtu_lvl, rty_out); + + /* End of Outputs for SubSystem: '/ ' */ + } else { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* SignalConversion generated from: '/out' incorporates: + * MATLAB Function: '/ .' + * Merge: '/Merge' + */ + u_j(rtu_lvl, rty_out); + + /* End of Outputs for SubSystem: '/ ' */ + } + + /* End of If: '/If' */ +} + +/* + * Output and update for action system: + * '/ ' + * '/ ' + */ +void u_l(int16_t rtu_temp_raw, uint8_t rtu_lvl, uint16_t *rty_riseperminute, + double *rtd_KEEP_FALLING_FL_UNTIL_LIMIT, const double + *rtd_Temp_FL_store) +{ + /* If: '/If' incorporates: + * Abs: '/ABS(AMBraw - AMB)' + * DataStoreRead: '/Read Amb' + * MATLAB Function: '/AMBRATE_FALLING_DIFF[7]' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + */ + /* : f_g_ausINCARRATE_FALLING_DIFF_F = g_ausINCARRATE_FALLING_DIFF_F(7); */ + if (fabs((double)rtu_temp_raw - *rtd_Temp_FL_store) > + g_ausINCARRATE_FALLING_DIFF_F[6]) { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + *rtd_KEEP_FALLING_FL_UNTIL_LIMIT = 1.0; + + /* SignalConversion generated from: '/rise per minute' incorporates: + * MATLAB Function: '/ .' + * Merge: '/Merge' + */ + u_j(rtu_lvl, rty_riseperminute); + + /* End of Outputs for SubSystem: '/ ' */ + } else { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* SignalConversion generated from: '/rise per minute' incorporates: + * MATLAB Function: '/ .' + * Merge: '/Merge' + */ + u(rtu_lvl, rty_riseperminute); + + /* End of Outputs for SubSystem: '/ ' */ + } + + /* End of If: '/If' */ +} + +/* + * Output and update for atomic system: + * '/ .' + * '/ .' + * '/ .' + * '/ .' + */ +void u_h(uint8_t rtu_lvl, uint16_t *rty_f_g_ausINCARRATE_RISING_F) +{ + int32_t tmp; + + /* : f_g_ausINCARRATE_RISING_F = g_ausINCARRATE_RISING_F(lvl + 1); */ + tmp = (int32_t)(rtu_lvl + 1U); + if (rtu_lvl + 1U > 255U) { + tmp = 255; + } + + *rty_f_g_ausINCARRATE_RISING_F = g_ausINCARRATE_RISING_F[tmp - 1]; +} + +/* + * Output and update for atomic system: + * '/ .' + * '/ .' + * '/ .' + * '/ .' + */ +void u_k(uint8_t rtu_lvl, uint16_t *rty_f_g_ausINCARRATE_RISING_DIFF_F) +{ + int32_t tmp; + + /* : f_g_ausINCARRATE_RISING_DIFF_F = g_ausINCARRATE_RISING_DIFF_F(lvl + 1); */ + tmp = (int32_t)(rtu_lvl + 1U); + if (rtu_lvl + 1U > 255U) { + tmp = 255; + } + + *rty_f_g_ausINCARRATE_RISING_DIFF_F = g_ausINCARRATE_RISING_DIFF_F[tmp - 1]; +} + +/* + * Output and update for action system: + * '/ ' + * '/ ' + */ +void u_lz(uint8_t rtu_lvl, uint16_t *rty_out) +{ + /* SignalConversion generated from: '/out' incorporates: + * MATLAB Function: '/ .' + */ + u_k(rtu_lvl, rty_out); +} + +/* + * Output and update for atomic system: + * '/g_ausINCARRATE_RISING_DIFF_F[8]' + * '/g_ausINCARRATE_RISING_DIFF_F[8]' + */ +void g_ausINCARRATE_RISING_DIFF_F8(uint16_t *rty_f_g_ausINCARRATE_RISING_DIFF_F) +{ + /* : f_g_ausINCARRATE_RISING_DIFF_F = g_ausINCARRATE_RISING_DIFF_F(8); */ + *rty_f_g_ausINCARRATE_RISING_DIFF_F = g_ausINCARRATE_RISING_DIFF_F[7]; +} + +/* + * Output and update for atomic system: + * '/INCARRATE_RISING_DIFF_F[7]' + * '/INCARRATE_RISING_DIFF_F[7]' + */ +void INCARRATE_RISING_DIFF_F7(uint16_t *rty_f_g_ausINCARRATE_RISING_DIFF_F) +{ + /* : f_g_ausINCARRATE_RISING_DIFF_F = g_ausINCARRATE_RISING_DIFF_F(7); */ + *rty_f_g_ausINCARRATE_RISING_DIFF_F = g_ausINCARRATE_RISING_DIFF_F[6]; +} + +/* + * Output and update for action system: + * '/ ' + * '/ ' + */ +void u_f(uint8_t rtu_lvl, uint16_t *rty_out) +{ + /* SignalConversion generated from: '/out' incorporates: + * MATLAB Function: '/ .' + */ + u_h(rtu_lvl, rty_out); +} + +/* + * Output and update for action system: + * '/ RL' + * '/ RR' + */ +void RL(int16_t rtu_temp_in, double *rty_temp_out) +{ + /* DataTypeConversion: '/Data Type Conversion' */ + *rty_temp_out = rtu_temp_in; +} + +/* + * Output and update for atomic system: + * '/AMBRATE_RISING_DIFF[8]' + * '/AMBRATE_RISING_DIFF[8]' + */ +void AMBRATE_RISING_DIFF8(uint16_t *rty_f_g_ausINCARRATE_FALLING_DIFF_R) +{ + /* : f_g_ausINCARRATE_FALLING_DIFF_R = g_ausINCARRATE_FALLING_DIFF_R(8); */ + *rty_f_g_ausINCARRATE_FALLING_DIFF_R = g_ausINCARRATE_FALLING_DIFF_R[7]; +} + +/* + * Output and update for atomic system: + * '/ .' + * '/ .' + * '/ .' + * '/ .' + */ +void u_kk(uint8_t rtu_lvl, uint16_t *rty_f_g_ausINCARRATE_FALLING_R) +{ + int32_t tmp; + + /* : f_g_ausINCARRATE_FALLING_R = g_ausINCARRATE_FALLING_R(lvl + 1); */ + tmp = (int32_t)(rtu_lvl + 1U); + if (rtu_lvl + 1U > 255U) { + tmp = 255; + } + + *rty_f_g_ausINCARRATE_FALLING_R = g_ausINCARRATE_FALLING_R[tmp - 1]; +} + +/* + * Output and update for atomic system: + * '/ .' + * '/ .' + * '/ .' + * '/ .' + */ +void u_b(uint8_t rtu_lvl, uint16_t *rty_f_g_ausINCARRATE_FALLING_DIFF_R) +{ + int32_t tmp; + + /* : f_g_ausINCARRATE_FALLING_DIFF_R = g_ausINCARRATE_FALLING_DIFF_R(lvl + 1); */ + tmp = (int32_t)(rtu_lvl + 1U); + if (rtu_lvl + 1U > 255U) { + tmp = 255; + } + + *rty_f_g_ausINCARRATE_FALLING_DIFF_R = g_ausINCARRATE_FALLING_DIFF_R[tmp - 1]; +} + +/* + * Output and update for action system: + * '/ ' + * '/ ' + */ +void u_hr(uint8_t rtu_lvl, uint16_t *rty_out) +{ + /* SignalConversion generated from: '/out' incorporates: + * MATLAB Function: '/ .' + */ + u_b(rtu_lvl, rty_out); +} + +/* + * Output and update for atomic system: + * '/AMBRATE_FALLING_DIFF[7]' + * '/AMBRATE_FALLING_DIFF[7]' + */ +void AMBRATE_FALLING_DIFF7(uint16_t *rty_f_g_ausINCARRATE_FALLING_DIFF_R) +{ + /* : f_g_ausINCARRATE_FALLING_DIFF_R = g_ausINCARRATE_FALLING_DIFF_R(7); */ + *rty_f_g_ausINCARRATE_FALLING_DIFF_R = g_ausINCARRATE_FALLING_DIFF_R[6]; +} + +/* + * Output and update for action system: + * '/ ' + * '/ ' + */ +void u_g(uint8_t rtu_lvl, uint16_t *rty_out) +{ + /* SignalConversion generated from: '/out' incorporates: + * MATLAB Function: '/ .' + */ + u_kk(rtu_lvl, rty_out); +} + +/* + * Output and update for atomic system: + * '/ .' + * '/ .' + * '/ .' + * '/ .' + */ +void u_m(uint8_t rtu_lvl, uint16_t *rty_f_g_ausINCARRATE_RISING_R) +{ + int32_t tmp; + + /* : f_g_ausINCARRATE_RISING_R = g_ausINCARRATE_RISING_R(lvl + 1); */ + tmp = (int32_t)(rtu_lvl + 1U); + if (rtu_lvl + 1U > 255U) { + tmp = 255; + } + + *rty_f_g_ausINCARRATE_RISING_R = g_ausINCARRATE_RISING_R[tmp - 1]; +} + +/* + * Output and update for atomic system: + * '/ .' + * '/ .' + * '/ .' + * '/ .' + */ +void u_o(uint8_t rtu_lvl, uint16_t *rty_f_g_ausINCARRATE_RISING_DIFF_R) +{ + int32_t tmp; + + /* : f_g_ausINCARRATE_RISING_DIFF_R = g_ausINCARRATE_RISING_DIFF_R(lvl + 1); */ + tmp = (int32_t)(rtu_lvl + 1U); + if (rtu_lvl + 1U > 255U) { + tmp = 255; + } + + *rty_f_g_ausINCARRATE_RISING_DIFF_R = g_ausINCARRATE_RISING_DIFF_R[tmp - 1]; +} + +/* + * Output and update for action system: + * '/ ' + * '/ ' + */ +void u_gq(uint8_t rtu_lvl, uint16_t *rty_out) +{ + /* SignalConversion generated from: '/out' incorporates: + * MATLAB Function: '/ .' + */ + u_o(rtu_lvl, rty_out); +} + +/* + * Output and update for atomic system: + * '/g_ausINCARRATE_RISING_DIFF_R[8]' + * '/g_ausINCARRATE_RISING_DIFF_R[8]' + */ +void g_ausINCARRATE_RISING_DIFF_R8(uint16_t *rty_f_g_ausINCARRATE_RISING_DIFF_R) +{ + /* : f_g_ausINCARRATE_RISING_DIFF_R = g_ausINCARRATE_RISING_DIFF_R(8); */ + *rty_f_g_ausINCARRATE_RISING_DIFF_R = g_ausINCARRATE_RISING_DIFF_R[7]; +} + +/* + * Output and update for atomic system: + * '/INCARRATE_RISING_DIFF_R[7]' + * '/INCARRATE_RISING_DIFF_R[7]' + */ +void INCARRATE_RISING_DIFF_R7(uint16_t *rty_f_g_ausINCARRATE_RISING_DIFF_R) +{ + /* : f_g_ausINCARRATE_RISING_DIFF_R = g_ausINCARRATE_RISING_DIFF_R(7); */ + *rty_f_g_ausINCARRATE_RISING_DIFF_R = g_ausINCARRATE_RISING_DIFF_R[6]; +} + +/* + * Output and update for action system: + * '/ ' + * '/ ' + */ +void u_b3(uint8_t rtu_lvl, uint16_t *rty_out) +{ + /* SignalConversion generated from: '/out' incorporates: + * MATLAB Function: '/ .' + */ + u_m(rtu_lvl, rty_out); +} + +/* + * Output and update for atomic system: + * '/AF AutoFoot' + * '/AF AutoFoot' + */ +void AFAutoFoot(uint16_t rty_out[8]) +{ + int32_t i; + for (i = 0; i < 8; i++) { + rty_out[i] = g_ausFLOW_FR_AF2VALVE_AF[i]; + } + + /* : out = g_ausFLOW_FR_AF2VALVE_AF; */ +} + +/* + * Output and update for atomic system: + * '/AF AutoFoot summer' + * '/AF AutoFoot summer' + */ +void AFAutoFootsummer(uint16_t rty_out[8]) +{ + int32_t i; + for (i = 0; i < 8; i++) { + rty_out[i] = g_ausFLOW_FR_AF2VALVE_SUMMER_AF[i]; + } + + /* : out = g_ausFLOW_FR_AF2VALVE_SUMMER_AF; */ +} + +/* + * Output and update for atomic system: + * '/AF Bi level' + * '/AF Bi level' + */ +void AFBilevel(uint16_t rty_out[8]) +{ + int32_t i; + for (i = 0; i < 8; i++) { + rty_out[i] = g_ausFLOW_FR_BIVALVE_AF[i]; + } + + /* : out = g_ausFLOW_FR_BIVALVE_AF; */ +} + +/* + * Output and update for atomic system: + * '/AF Bi level 2' + * '/AF Bi level 2' + */ +void AFBilevel2(uint16_t rty_out[8]) +{ + int32_t i; + for (i = 0; i < 8; i++) { + rty_out[i] = g_ausFLOW_FR_BI2BLR_AF[i]; + } + + /* : out = g_ausFLOW_FR_BI2BLR_AF; */ +} + +/* + * Output and update for atomic system: + * '/AF Defrost' + * '/AF Defrost' + */ +void AFDefrost(uint16_t rty_out[8]) +{ + int32_t i; + for (i = 0; i < 8; i++) { + rty_out[i] = g_ausFLOW_FR_DE2BLR_AF[i]; + } + + /* : out = g_ausFLOW_FR_DE2BLR_AF; */ +} + +/* + * Output and update for atomic system: + * '/AF Foot' + * '/AF Foot' + */ +void AFFoot(uint16_t rty_out[8]) +{ + int32_t i; + for (i = 0; i < 8; i++) { + rty_out[i] = g_ausFLOW_FR_FO2BLR_AF[i]; + } + + /* : out = g_ausFLOW_FR_FO2BLR_AF; */ +} + +/* + * Output and update for atomic system: + * '/AF Foot + Def' + * '/AF Foot + Def' + */ +void AFFootDef(uint16_t rty_out[8]) +{ + int32_t i; + for (i = 0; i < 8; i++) { + rty_out[i] = g_ausFLOW_FR_FD2BLR_AF[i]; + } + + /* : out = g_ausFLOW_FR_FD2BLR_AF; */ +} + +/* + * Output and update for atomic system: + * '/AF Hi (def + vent)' + * '/AF Hi (def + vent)' + */ +void AFHidefvent(uint16_t rty_out[8]) +{ + int32_t i; + for (i = 0; i < 8; i++) { + rty_out[i] = g_ausFLOW_FR_HI2BLR_AF[i]; + } + + /* : out = g_ausFLOW_FR_HI2BLR_AF; */ +} + +/* + * Output and update for atomic system: + * '/AF Tri mode' + * '/AF Tri mode' + */ +void AFTrimode(uint16_t rty_out[8]) +{ + int32_t i; + for (i = 0; i < 8; i++) { + rty_out[i] = g_ausFLOW_FR_TR2BLR_AF[i]; + } + + /* : out = g_ausFLOW_FR_TR2BLR_AF; */ +} + +/* + * Output and update for atomic system: + * '/AF VENT' + * '/AF VENT (fail safe)' + * '/AF VENT' + * '/AF VENT (fail safe)' + */ +void AFVENT(uint16_t rty_out[8]) +{ + int32_t i; + for (i = 0; i < 8; i++) { + rty_out[i] = g_ausFLOW_FR_VE2BLR_AF[i]; + } + + /* : out = g_ausFLOW_FR_VE2BLR_AF; */ +} + +/* + * Output and update for atomic system: + * '/closest speed' + * '/closest speed' + * '/closest speed' + * '/closest speed' + */ +void closestspeed(const uint16_t rtu_AF_for_speed[8], uint16_t rtu_AF_value, + uint8_t *rty_idx) +{ + int32_t i; + uint16_t min_diff; + + /* : min_diff = uint16(9999); */ + min_diff = 9999U; + + /* : idx = uint8(0); */ + *rty_idx = 0U; + + /* : for i = 1:length(AF_for_speed) */ + for (i = 0; i < 8; i++) { + int32_t diff; + + /* : diff = abs(int32(AF_for_speed(i)) - int32(AF_value)); */ + diff = rtu_AF_for_speed[i] - rtu_AF_value; + if (diff < 0) { + diff = -diff; + } + + /* : if diff < min_diff */ + if (diff < min_diff) { + /* : min_diff = uint16(diff); */ + min_diff = (uint16_t)diff; + + /* : idx = uint8(i - 1); */ + *rty_idx = (uint8_t)i; + } + } +} + +/* + * Output and update for atomic system: + * '/AF REAR Bi Level' + * '/AF REAR Bi Level' + */ +void AFREARBiLevel(uint16_t rty_out[8]) +{ + int32_t i; + for (i = 0; i < 8; i++) { + rty_out[i] = g_ausFLOW_RE_BI2BLR_AF[i]; + } + + /* : out = g_ausFLOW_RE_BI2BLR_AF; */ +} + +/* + * Output and update for atomic system: + * '/AF REAR Foot' + * '/AF REAR Foot' + */ +void AFREARFoot(uint16_t rty_out[8]) +{ + int32_t i; + for (i = 0; i < 8; i++) { + rty_out[i] = g_ausFLOW_RE_FO2BLR_AF[i]; + } + + /* : out = g_ausFLOW_RE_FO2BLR_AF; */ +} + +/* + * Output and update for atomic system: + * '/AF REAR VENT AUTO' + * '/AF REAR VENT AUTO1' + * '/AF REAR VENT AUTO' + * '/AF REAR VENT AUTO1' + */ +void AFREARVENTAUTO(uint16_t rty_out[8]) +{ + int32_t i; + for (i = 0; i < 8; i++) { + rty_out[i] = g_ausFLOW_RE_VE2BLR_AF[i]; + } + + /* : out = g_ausFLOW_RE_VE2BLR_AF; */ +} + +/* + * Output and update for atomic system: + * '/direction for REAR index mode' + * '/direction for REAR index mode1' + */ +void directionforREARindexmode(uint16_t rtu_index_mode, double rty_Y[4]) +{ + /* : switch index_mode */ + switch (rtu_index_mode) { + case 0U: + /* : case 0 */ + /* : Y = [0; 0; 0; 0]; */ + rty_Y[0] = 0.0; + rty_Y[1] = 0.0; + rty_Y[2] = 0.0; + rty_Y[3] = 0.0; + break; + + case 120U: + /* : case 120 */ + /* : Y = [0; 1; 0; 190]; */ + rty_Y[0] = 0.0; + rty_Y[1] = 1.0; + rty_Y[2] = 0.0; + rty_Y[3] = 190.0; + break; + + case 130U: + /* : case 130 */ + /* : Y = [0; 1; 1; 200]; */ + rty_Y[0] = 0.0; + rty_Y[1] = 1.0; + rty_Y[2] = 1.0; + rty_Y[3] = 200.0; + break; + + case 140U: + /* : case 140 */ + /* : Y = [0; 0; 1; 140]; */ + rty_Y[0] = 0.0; + rty_Y[1] = 0.0; + rty_Y[2] = 1.0; + rty_Y[3] = 140.0; + break; + + case 150U: + /* : case 150 */ + /* : Y = [0; 1; 0; 200]; */ + rty_Y[0] = 0.0; + rty_Y[1] = 1.0; + rty_Y[2] = 0.0; + rty_Y[3] = 200.0; + break; + + case 160U: + /* : case 160 */ + /* : Y = [0; 1; 1; 200]; */ + rty_Y[0] = 0.0; + rty_Y[1] = 1.0; + rty_Y[2] = 1.0; + rty_Y[3] = 200.0; + break; + + case 170U: + /* : case 170 */ + /* : Y = [0; 1; 0; 190]; */ + rty_Y[0] = 0.0; + rty_Y[1] = 1.0; + rty_Y[2] = 0.0; + rty_Y[3] = 190.0; + break; + + case 180U: + /* : case 180 */ + /* : Y = [0; 1; 1; 200]; */ + rty_Y[0] = 0.0; + rty_Y[1] = 1.0; + rty_Y[2] = 1.0; + rty_Y[3] = 200.0; + break; + + case 190U: + /* : case 190 */ + /* : Y = [0; 1; 0; 190]; */ + rty_Y[0] = 0.0; + rty_Y[1] = 1.0; + rty_Y[2] = 0.0; + rty_Y[3] = 190.0; + break; + + case 200U: + /* : case 200 */ + /* : Y = [0; 1; 1; 200]; */ + rty_Y[0] = 0.0; + rty_Y[1] = 1.0; + rty_Y[2] = 1.0; + rty_Y[3] = 200.0; + break; + + default: + /* : otherwise */ + /* : Y = [0; 0; 0; 0]; */ + rty_Y[0] = 0.0; + rty_Y[1] = 0.0; + rty_Y[2] = 0.0; + rty_Y[3] = 0.0; + break; + } +} + +/* + * System initialize for atomic system: + * '/Zone_Climate_Logic_Auto_FL2' + * '/Zone_Climate_Logic_Auto_FL3' + */ +void Zone_Climate_Logic_Auto_FL2_Init(uint8_t *rty_out_def, uint8_t + *rty_out_face, uint8_t *rty_out_foot, uint8_t *rty_out_auto, double + *rty_out_ac, DW_Zone_Climate_Logic_Auto_FL2 *localDW) +{ + *rty_out_def = 0U; + *rty_out_face = 0U; + *rty_out_foot = 0U; + *rty_out_auto = 0U; + *rty_out_ac = 0.0; + localDW->is_active_c783_HVAC_model = 0U; + localDW->is_c783_HVAC_model = IN_NO_ACTIVE_CHILD; + localDW->is_AC_SUB = IN_NO_ACTIVE_CHILD; + localDW->is_DEF_SUB = IN_NO_ACTIVE_CHILD; + localDW->is_FACE_SUB = IN_NO_ACTIVE_CHILD; + localDW->is_FOOT_SUB = IN_NO_ACTIVE_CHILD; + localDW->is_AC_SUB_f = IN_NO_ACTIVE_CHILD; +} + +/* + * Output and update for atomic system: + * '/Zone_Climate_Logic_Auto_FL2' + * '/Zone_Climate_Logic_Auto_FL3' + */ +void Zone_Climate_Logic_Auto_FL2(double rtu_btn_def, uint8_t rtu_btn_face, + uint8_t rtu_btn_foot, uint8_t rtu_btn_auto, uint8_t rtu_btn_ac, uint8_t + *rty_out_def, uint8_t *rty_out_face, uint8_t *rty_out_foot, uint8_t + *rty_out_auto, double *rty_out_ac, DW_Zone_Climate_Logic_Auto_FL2 *localDW) +{ + /* Chart: '/Zone_Climate_Logic_Auto_FL2' */ + if (localDW->is_active_c783_HVAC_model == 0U) { + localDW->is_active_c783_HVAC_model = 1U; + localDW->is_c783_HVAC_model = IN_MANUAL_MODE; + + /* : out_def = 0; */ + *rty_out_def = 0U; + + /* : out_face = 1; */ + *rty_out_face = 1U; + + /* : out_foot = 1; */ + *rty_out_foot = 1U; + + /* : mem_def = 0; */ + /* : mem_face = 0; */ + /* : mem_foot = 0; */ + localDW->is_DEF_SUB = IN_Def_Off; + localDW->is_FACE_SUB = IN_Face_Off; + localDW->is_FOOT_SUB = IN_Foot_Off; + localDW->is_AC_SUB_f = IN_AC_Off; + } else if (localDW->is_c783_HVAC_model == IN_AUTO_MODE) { + /* : sf_internal_predicateOutput = btn_auto == 0 || btn_def == 1 || btn_face == 1 || btn_foot == 1; */ + if ((rtu_btn_auto == 0) || (rtu_btn_def == 1.0) || (rtu_btn_face == 1) || + (rtu_btn_foot == 1)) { + /* : out_auto=0; */ + *rty_out_auto = 0U; + localDW->is_AC_SUB = IN_NO_ACTIVE_CHILD; + localDW->is_c783_HVAC_model = IN_MANUAL_MODE; + + /* : out_def = 0; */ + *rty_out_def = 0U; + + /* : out_face = 1; */ + *rty_out_face = 1U; + + /* : out_foot = 1; */ + *rty_out_foot = 1U; + + /* : mem_def = 0; */ + /* : mem_face = 0; */ + /* : mem_foot = 0; */ + localDW->is_DEF_SUB = IN_Def_Off; + localDW->is_FACE_SUB = IN_Face_Off; + localDW->is_FOOT_SUB = IN_Foot_Off; + localDW->is_AC_SUB_f = IN_AC_Off; + } else if (localDW->is_AC_SUB == IN_AC_Off) { + /* : sf_internal_predicateOutput = btn_ac == 1; */ + if (rtu_btn_ac == 1) { + /* : out_ac=1 */ + localDW->is_AC_SUB = IN_AC_On; + + /* : out_ac = 1; */ + *rty_out_ac = 1.0; + } + + /* case IN_AC_On: */ + /* : sf_internal_predicateOutput = btn_ac == 0; */ + } else if (rtu_btn_ac == 0) { + /* : out_ac=0 */ + *rty_out_ac = 0.0; + localDW->is_AC_SUB = IN_AC_Off; + } + + /* case IN_MANUAL_MODE: */ + /* : sf_internal_predicateOutput = btn_auto == 1 || (out_def == 0 && out_face == 0 && out_foot == 0); */ + } else if ((rtu_btn_auto == 1) || ((*rty_out_def == 0) && (*rty_out_face == 0) + && (*rty_out_foot == 0))) { + /* : out_auto=1; */ + localDW->is_AC_SUB_f = IN_NO_ACTIVE_CHILD; + localDW->is_FOOT_SUB = IN_NO_ACTIVE_CHILD; + localDW->is_FACE_SUB = IN_NO_ACTIVE_CHILD; + localDW->is_DEF_SUB = IN_NO_ACTIVE_CHILD; + localDW->is_c783_HVAC_model = IN_AUTO_MODE; + + /* : out_auto = 1; */ + *rty_out_auto = 1U; + + /* : out_def = 0; */ + *rty_out_def = 0U; + + /* : out_face = 0; */ + *rty_out_face = 0U; + + /* : out_foot = 0; */ + *rty_out_foot = 0U; + localDW->is_AC_SUB = IN_AC_On; + + /* : out_ac = 1; */ + *rty_out_ac = 1.0; + } else { + if (localDW->is_DEF_SUB == IN_Def_Off) { + /* : sf_internal_predicateOutput = btn_def == 1; */ + if (rtu_btn_def == 1.0) { + /* : out_def=1 */ + *rty_out_def = 1U; + localDW->is_DEF_SUB = IN_Def_On; + } + + /* case IN_Def_On: */ + /* : sf_internal_predicateOutput = btn_def == 0; */ + } else if (rtu_btn_def == 0.0) { + /* : out_def=0 */ + *rty_out_def = 0U; + localDW->is_DEF_SUB = IN_Def_Off; + } + + if (localDW->is_FACE_SUB == IN_Face_Off) { + /* : sf_internal_predicateOutput = btn_face == 1; */ + if (rtu_btn_face == 1) { + /* : out_face=1 */ + *rty_out_face = 1U; + localDW->is_FACE_SUB = IN_Face_On; + } + + /* case IN_Face_On: */ + /* : sf_internal_predicateOutput = btn_face == 0; */ + } else if (rtu_btn_face == 0) { + /* : out_face=0 */ + *rty_out_face = 0U; + localDW->is_FACE_SUB = IN_Face_Off; + } + + if (localDW->is_FOOT_SUB == IN_Foot_Off) { + /* : sf_internal_predicateOutput = btn_foot == 1; */ + if (rtu_btn_foot == 1) { + /* : out_foot=1 */ + *rty_out_foot = 1U; + localDW->is_FOOT_SUB = IN_Foot_On; + } + + /* case IN_Foot_On: */ + /* : sf_internal_predicateOutput = btn_foot == 0; */ + } else if (rtu_btn_foot == 0) { + /* : out_foot=0 */ + *rty_out_foot = 0U; + localDW->is_FOOT_SUB = IN_Foot_Off; + } + + if (localDW->is_AC_SUB_f == IN_AC_Off) { + /* : sf_internal_predicateOutput = btn_ac == 1; */ + if (rtu_btn_ac == 1) { + /* : out_ac=1 */ + *rty_out_ac = 1.0; + localDW->is_AC_SUB_f = IN_AC_On; + } + + /* case IN_AC_On: */ + /* : sf_internal_predicateOutput = btn_ac == 0; */ + } else if (rtu_btn_ac == 0) { + /* : out_ac=0 */ + *rty_out_ac = 0.0; + localDW->is_AC_SUB_f = IN_AC_Off; + } + } + + /* End of Chart: '/Zone_Climate_Logic_Auto_FL2' */ +} + +/* + * Output and update for atomic system: + * '/AF for Bi Level' + * '/AF for Bi Level' + */ +void AFforBiLevel(uint8_t rtu_blower_speed, uint16_t *rty_out) +{ + int32_t tmp; + + /* : out = uint16(g_ausFLOW_FR_BI2BLR_AF(blower_speed + 1)); */ + tmp = (int32_t)(rtu_blower_speed + 1U); + if (rtu_blower_speed + 1U > 255U) { + tmp = 255; + } + + *rty_out = g_ausFLOW_FR_BI2BLR_AF[tmp - 1]; +} + +/* + * Output and update for atomic system: + * '/AF for Def' + * '/AF for Def' + */ +void AFforDef(uint8_t rtu_blower_speed, uint16_t *rty_out) +{ + int32_t tmp; + + /* : out = uint16(g_ausFLOW_FR_DE2BLR_AF(blower_speed + 1)); */ + tmp = (int32_t)(rtu_blower_speed + 1U); + if (rtu_blower_speed + 1U > 255U) { + tmp = 255; + } + + *rty_out = g_ausFLOW_FR_DE2BLR_AF[tmp - 1]; +} + +/* + * Output and update for atomic system: + * '/AF for Foor + Def' + * '/AF for Foor + Def' + */ +void AFforFoorDef(uint8_t rtu_blower_speed, uint16_t *rty_out) +{ + int32_t tmp; + + /* : out = uint16(g_ausFLOW_FR_FD2BLR_AF(blower_speed + 1)); */ + tmp = (int32_t)(rtu_blower_speed + 1U); + if (rtu_blower_speed + 1U > 255U) { + tmp = 255; + } + + *rty_out = g_ausFLOW_FR_FD2BLR_AF[tmp - 1]; +} + +/* + * Output and update for atomic system: + * '/AF for Foot' + * '/AF for Foot' + */ +void AFforFoot(uint8_t rtu_blower_speed, uint16_t *rty_out) +{ + int32_t tmp; + + /* : out = uint16(g_ausFLOW_FR_FO2BLR_AF(blower_speed + 1)); */ + tmp = (int32_t)(rtu_blower_speed + 1U); + if (rtu_blower_speed + 1U > 255U) { + tmp = 255; + } + + *rty_out = g_ausFLOW_FR_FO2BLR_AF[tmp - 1]; +} + +/* + * Output and update for atomic system: + * '/AF for Hi_Level' + * '/AF for Hi_Level' + */ +void AFforHi_Level(uint8_t rtu_blower_speed, uint16_t *rty_out) +{ + int32_t tmp; + + /* : out = uint16(g_ausFLOW_FR_HI2BLR_AF(blower_speed + 1)); */ + tmp = (int32_t)(rtu_blower_speed + 1U); + if (rtu_blower_speed + 1U > 255U) { + tmp = 255; + } + + *rty_out = g_ausFLOW_FR_HI2BLR_AF[tmp - 1]; +} + +/* + * Output and update for atomic system: + * '/AF for Tri-Level' + * '/AF for Tri-Level' + */ +void AFforTriLevel(uint8_t rtu_blower_speed, uint16_t *rty_out) +{ + int32_t tmp; + + /* : out = uint16(g_ausFLOW_FR_TR2BLR_AF(blower_speed + 1)); */ + tmp = (int32_t)(rtu_blower_speed + 1U); + if (rtu_blower_speed + 1U > 255U) { + tmp = 255; + } + + *rty_out = g_ausFLOW_FR_TR2BLR_AF[tmp - 1]; +} + +/* + * Output and update for atomic system: + * '/AF for Vent mode' + * '/AF for Vent mode' + */ +void AFforVentmode(uint8_t rtu_blower_speed, uint16_t *rty_out) +{ + int32_t tmp; + + /* : out = uint16(g_ausFLOW_FR_VE2BLR_AF(blower_speed + 1)); */ + tmp = (int32_t)(rtu_blower_speed + 1U); + if (rtu_blower_speed + 1U > 255U) { + tmp = 255; + } + + *rty_out = g_ausFLOW_FR_VE2BLR_AF[tmp - 1]; +} + +/* + * Output and update for enable system: + * '/Rear Left AF - manual directions' + * '/Rear Right AF - manual directions' + */ +void RearLeftAFmanualdirections(bool rtu_Enable, uint8_t rtu_blowerspeed, + uint8_t rtu_faceison, uint8_t rtu_footison, uint16_t *rty_AFout) +{ + int32_t tmp; + + /* Outputs for Enabled SubSystem: '/Rear Left AF - manual directions' incorporates: + * EnablePort: '/Enable' + */ + if (rtu_Enable) { + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Constant: '/Constant1' + * Constant: '/Constant2' + * Constant: '/Constant3' + * Gain: '/Gain2' + * MATLAB Function: '/AF for Bi Level R' + * MATLAB Function: '/AF for Foot R' + * MATLAB Function: '/AF for Vent mode R' + * RelationalOperator: '/Relational Operator1' + * RelationalOperator: '/Relational Operator2' + * Sum: '/Add' + */ + /* : out = uint16(g_ausFLOW_RE_BI2BLR_AF(blower_speed + 1)); */ + /* : out = uint16(g_ausFLOW_RE_FO2BLR_AF(blower_speed + 1)); */ + /* : out = uint16(g_ausFLOW_RE_VE2BLR_AF(blower_speed + 1)); */ + switch ((int32_t)((uint32_t)((rtu_footison == 1) << 1) + (uint32_t) + (rtu_faceison == 1))) { + case 0: + *rty_AFout = 0U; + break; + + case 1: + /* MATLAB Function: '/AF for Vent mode R' */ + tmp = (int32_t)(rtu_blowerspeed + 1U); + if (rtu_blowerspeed + 1U > 255U) { + tmp = 255; + } + + *rty_AFout = g_ausFLOW_RE_VE2BLR_AF[tmp - 1]; + break; + + case 2: + /* MATLAB Function: '/AF for Foot R' */ + tmp = (int32_t)(rtu_blowerspeed + 1U); + if (rtu_blowerspeed + 1U > 255U) { + tmp = 255; + } + + *rty_AFout = g_ausFLOW_RE_FO2BLR_AF[tmp - 1]; + break; + + default: + /* MATLAB Function: '/AF for Bi Level R' */ + tmp = (int32_t)(rtu_blowerspeed + 1U); + if (rtu_blowerspeed + 1U > 255U) { + tmp = 255; + } + + *rty_AFout = g_ausFLOW_RE_BI2BLR_AF[tmp - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch' */ + } + + /* End of Outputs for SubSystem: '/Rear Left AF - manual directions' */ +} + +/* + * Output and update for atomic system: + * '/func g_ascAUTO_STEP_AF_F' + * '/func g_ascAUTO_STEP_AF_F' + */ +void funcg_ascAUTO_STEP_AF_F(double rtu_AF_STEP, int8_t *rty_y) +{ + /* : y = g_ascAUTO_STEP_AF_F(AF_STEP); */ + *rty_y = g_ascAUTO_STEP_AF_F[(int32_t)rtu_AF_STEP - 1]; +} + +/* + * Output and update for atomic system: + * '/ .' + * '/ .' + * '/ .' + * '/ .' + * '/ .' + * '/ .' + */ +void u_m2(int16_t rtu_lvl, uint8_t *rty_f_g_aucAMBRATE_FALLING) +{ + int32_t tmp; + + /* : f_g_aucAMBRATE_FALLING = g_aucAMBRATE_FALLING(lvl + 1); */ + tmp = rtu_lvl + 1; + if (rtu_lvl + 1 > 32767) { + tmp = 32767; + } + + *rty_f_g_aucAMBRATE_FALLING = g_aucAMBRATE_FALLING[tmp - 1]; +} + +/* + * Output and update for action system: + * '/ ' + * '/ ' + * '/ ' + */ +void u_kb(int16_t rtu_amb_raw, int16_t rtu_lvl, uint8_t *rty_out, const double + *rtd_AMB_store, double *rtd_KEEP_FALLING_UNTIL_LIMIT) +{ + int32_t tmp; + + /* If: '/If' incorporates: + * Abs: '/ABS(AMBraw - AMB)' + * DataStoreRead: '/Read Amb' + * MATLAB Function: '/AMBRATE_RISING_DIFF[8]' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + */ + /* : f_g_aucAMBRATE_FALLING_DIFF = g_aucAMBRATE_FALLING_DIFF(8); */ + if (fabs((double)rtu_amb_raw - *rtd_AMB_store) <= g_aucAMBRATE_FALLING_DIFF[7]) + { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + *rtd_KEEP_FALLING_UNTIL_LIMIT = 0.0; + + /* SignalConversion generated from: '/out' incorporates: + * MATLAB Function: '/ .' + * Merge: '/Merge' + */ + u_m2(rtu_lvl, rty_out); + + /* End of Outputs for SubSystem: '/ ' */ + } else { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* MATLAB Function: '/ .' */ + /* : f_g_aucAMBRATE_FALLING_DIFF = g_aucAMBRATE_FALLING_DIFF(lvl + 1); */ + tmp = rtu_lvl + 1; + if (rtu_lvl + 1 > 32767) { + tmp = 32767; + } + + /* SignalConversion generated from: '/out' incorporates: + * MATLAB Function: '/ .' + * Merge: '/Merge' + */ + *rty_out = g_aucAMBRATE_FALLING_DIFF[tmp - 1]; + + /* End of Outputs for SubSystem: '/ ' */ + } + + /* End of If: '/If' */ +} + +/* + * Output and update for action system: + * '/ ' + * '/ ' + * '/ ' + */ +void u_my(int16_t rtu_amb_raw, int16_t rtu_lvl, uint8_t *rty_riseperminute, + const double *rtd_AMB_store, double *rtd_KEEP_FALLING_UNTIL_LIMIT) +{ + int32_t tmp; + + /* If: '/If' incorporates: + * Abs: '/ABS(AMBraw - AMB)' + * DataStoreRead: '/Read Amb' + * MATLAB Function: '/AMBRATE_FALLING_DIFF[7]' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + */ + /* : f_g_aucAMBRATE_FALLING_DIFF = g_aucAMBRATE_FALLING_DIFF(7); */ + if (fabs((double)rtu_amb_raw - *rtd_AMB_store) > g_aucAMBRATE_FALLING_DIFF[6]) + { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + *rtd_KEEP_FALLING_UNTIL_LIMIT = 1.0; + + /* MATLAB Function: '/ .' */ + /* : f_g_aucAMBRATE_FALLING_DIFF_LVL = g_aucAMBRATE_FALLING_DIFF(lvl + 1); */ + tmp = rtu_lvl + 1; + if (rtu_lvl + 1 > 32767) { + tmp = 32767; + } + + /* SignalConversion generated from: '/rise per minute' incorporates: + * MATLAB Function: '/ .' + * Merge: '/Merge' + */ + *rty_riseperminute = g_aucAMBRATE_FALLING_DIFF[tmp - 1]; + + /* End of Outputs for SubSystem: '/ ' */ + } else { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* SignalConversion generated from: '/rise per minute' incorporates: + * MATLAB Function: '/ .' + * Merge: '/Merge' + */ + u_m2(rtu_lvl, rty_riseperminute); + + /* End of Outputs for SubSystem: '/ ' */ + } + + /* End of If: '/If' */ +} + +/* + * Output and update for atomic system: + * '/ .' + * '/ .' + * '/ .' + * '/ .' + * '/ .' + * '/ .' + */ +void u_h3(int16_t rtu_lvl, uint8_t *rty_f_g_aucAMBRATE_RISING) +{ + int32_t tmp; + + /* : f_g_aucAMBRATE_RISING = g_aucAMBRATE_RISING(lvl + 1); */ + tmp = rtu_lvl + 1; + if (rtu_lvl + 1 > 32767) { + tmp = 32767; + } + + *rty_f_g_aucAMBRATE_RISING = g_aucAMBRATE_RISING[tmp - 1]; +} + +/* + * Output and update for atomic system: + * '/ .' + * '/ .' + * '/ .' + * '/ .' + * '/ .' + * '/ .' + */ +void u_fr(int16_t rtu_lvl, uint8_t *rty_f_g_aucAMBRATE_RISING_DIFF_LVL) +{ + int32_t tmp; + + /* : f_g_aucAMBRATE_RISING_DIFF_LVL = g_aucAMBRATE_RISING_DIFF(lvl + 1); */ + tmp = rtu_lvl + 1; + if (rtu_lvl + 1 > 32767) { + tmp = 32767; + } + + *rty_f_g_aucAMBRATE_RISING_DIFF_LVL = g_aucAMBRATE_RISING_DIFF[tmp - 1]; +} + +/* + * Output and update for action system: + * '/ ' + * '/ ' + * '/ ' + */ +void u_p(int16_t rtu_amb_raw, int16_t rtu_lvl, uint8_t *rty_out, const double + *rtd_AMB_store, double *rtd_KEEP_RISING_UNTIL_LIMIT) +{ + /* If: '/If' incorporates: + * Abs: '/ABS(AMBraw - AMB)' + * DataStoreRead: '/Read Amb' + * MATLAB Function: '/AMBRATE_RISING_DIFF[8]' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + */ + /* : f_g_aucAMBRATE_RISING_DIFF = g_aucAMBRATE_RISING_DIFF(8); */ + if (fabs((double)rtu_amb_raw - *rtd_AMB_store) <= g_aucAMBRATE_RISING_DIFF[7]) + { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + *rtd_KEEP_RISING_UNTIL_LIMIT = 0.0; + + /* SignalConversion generated from: '/out' incorporates: + * MATLAB Function: '/ .' + */ + u_h3(rtu_lvl, rty_out); + + /* End of Outputs for SubSystem: '/ ' */ + } else { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* SignalConversion generated from: '/out' incorporates: + * MATLAB Function: '/ .' + */ + u_fr(rtu_lvl, rty_out); + + /* End of Outputs for SubSystem: '/ ' */ + } + + /* End of If: '/If' */ +} + +/* + * Output and update for action system: + * '/ ' + * '/ ' + * '/ ' + */ +void u_g2(int16_t rtu_amb_raw, int16_t rtu_lvl, uint8_t *rty_riseperminute, + const double *rtd_AMB_store, double *rtd_KEEP_RISING_UNTIL_LIMIT) +{ + /* If: '/If' incorporates: + * Abs: '/ABS(AMBraw - AMB)' + * DataStoreRead: '/Read Amb' + * MATLAB Function: '/AMBRATE_RISING_DIFF[7]' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + */ + /* : f_g_aucAMBRATE_RISING_DIFF = g_aucAMBRATE_RISING_DIFF(7); */ + if (fabs((double)rtu_amb_raw - *rtd_AMB_store) > g_aucAMBRATE_RISING_DIFF[6]) + { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + *rtd_KEEP_RISING_UNTIL_LIMIT = 1.0; + + /* SignalConversion generated from: '/out' incorporates: + * MATLAB Function: '/ .' + */ + u_fr(rtu_lvl, rty_riseperminute); + + /* End of Outputs for SubSystem: '/ ' */ + } else { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* SignalConversion generated from: '/out' incorporates: + * MATLAB Function: '/ .' + */ + u_h3(rtu_lvl, rty_riseperminute); + + /* End of Outputs for SubSystem: '/ ' */ + } + + /* End of If: '/If' */ +} + +/* + * Output and update for action system: + * '/If Action Subsystem' + * '/If Action Subsystem' + * '/If Action Subsystem' + */ +void IfActionSubsystem_h(int8_t *rty_Out1, double *rtd_ErrorHomming_private, + double *rtd_Start_timer_n, int8_t *rtd_stepSig_private) +{ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + *rtd_stepSig_private = 1; + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * Constant: '/Constant2' + * DataStoreRead: '/Data Store Read1' + * Sum: '/step inc' + */ + (*rtd_ErrorHomming_private)++; + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/Constant3' + */ + *rtd_Start_timer_n = 0.0; + + /* SignalConversion generated from: '/Out1' incorporates: + * Constant: '/Constant1' + */ + *rty_Out1 = 2; +} + +/* + * System initialize for atomic system: + * '/MATLAB Function' + * '/MATLAB Function' + * '/MATLAB Function' + */ +void MATLABFunction_Init(DW_MATLABFunction *localDW) +{ + localDW->t_start_not_empty = false; + localDW->cond_prev = 0.0; +} + +/* + * Output and update for atomic system: + * '/MATLAB Function' + * '/MATLAB Function' + * '/MATLAB Function' + */ +void MATLABFunction(double rtu_cond, uint32_t rtu_t_now, uint32_t *rty_dt, + DW_MATLABFunction *localDW) +{ + /* : dt = uint32(0); */ + /* : if isempty(t_start) */ + if (!localDW->t_start_not_empty) { + /* : t_start = t_now; */ + localDW->t_start = rtu_t_now; + localDW->t_start_not_empty = true; + + /* : cond_prev = 0; */ + } + + /* : if cond > 0.5 && cond_prev <= 0.5 */ + if ((rtu_cond > 0.5) && (localDW->cond_prev <= 0.5)) { + /* : t_start = t_now; */ + localDW->t_start = rtu_t_now; + } + + /* : if cond > 0.5 */ + if (rtu_cond > 0.5) { + uint32_t qY; + + /* : dt = uint32(t_now - t_start); */ + /* MW:begin MISRA2012:D4.1 CERT-C:INT30-C 'Justifying MISRA CPP rule violation' */ + qY = rtu_t_now - /*MW:OvSatOk*/ localDW->t_start; + + /* MW:end MISRA2012:D4.1 CERT-C:INT30-C */ + if (qY > rtu_t_now) { + qY = 0U; + } + + *rty_dt = qY; + } else { + /* : else */ + /* : dt = uint32(0); */ + *rty_dt = 0U; + } + + /* : cond_prev = cond; */ + localDW->cond_prev = rtu_cond; +} + +/* + * Output and update for action system: + * '/If Action Subsystem1' + * '/If Action Subsystem1' + * '/If Action Subsystem1' + */ +void IfActionSubsystem1_h(int8_t *rty_Output, uint8_t + *rtd_CCU_ActuatorErrF_Stat_private, uint8_t rtd_COM_private[9], uint8_t + rtd_ErrorActuator[9], uint8_t rtd_ErrorCalibration_private[9], const double + *rtd_LOGGER_LIN, uint8_t rtd_MODE_private[9], uint8_t + rtd_dtc_state_error_model[127]) +{ + int32_t i; + bool tmp; + + /* Logic: '/Logical Operator' incorporates: + * DataStoreRead: '/Data Store Read' + */ + tmp = (rtd_ErrorCalibration_private[0] != 0); + for (i = 0; i < 8; i++) { + tmp = (tmp || (rtd_ErrorCalibration_private[i + 1] != 0)); + } + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * DataStoreWrite: '/Data Store Write1' + * Logic: '/Logical Operator' + */ + *rtd_CCU_ActuatorErrF_Stat_private = tmp; + for (i = 0; i < 9; i++) { + /* DataStoreWrite: '/Data Store Write2' incorporates: + * DataStoreRead: '/Data Store Read' + */ + rtd_COM_private[i] = rtd_ErrorCalibration_private[i]; + + /* DataStoreWrite: '/Data Store Write' */ + rtd_MODE_private[i] = 2U; + } + + /* MATLAB Function: '/Write ERROR' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read6' + */ + /* : if(LOGGER==1) */ + if (*rtd_LOGGER_LIN == 1.0) { + /* : for i = 1:numel(ErrCallibration) */ + for (i = 0; i < 9; i++) { + /* : if ErrCallibration(i) == 1 */ + if (rtd_ErrorCalibration_private[i] == 1) { + /* : fprintf('LIN1 Failure with actuator #%d\n', int16(i)); */ + printf("LIN1 Failure with actuator #%d\n", (int16_t)(i + 1)); + fflush(stdout); + } + } + } + + /* End of MATLAB Function: '/Write ERROR' */ + for (i = 0; i < 9; i++) { + uint8_t rtd_ErrorCalibration_private_0; + + /* Logic: '/Logical Operator1' incorporates: + * DataStoreRead: '/Data Store Read' + */ + rtd_ErrorCalibration_private_0 = rtd_ErrorCalibration_private[i]; + + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write3' + * Logic: '/Logical Operator1' + */ + rtd_ErrorActuator[i] = (uint8_t)((rtd_ErrorCalibration_private_0 != 0) || + (rtd_ErrorActuator[i] != 0)); + + /* DataStoreWrite: '/Data Store Write' */ + rtd_dtc_state_error_model[i + 54] = rtd_ErrorCalibration_private_0; + + /* DataStoreWrite: '/Data Store Write' */ + rtd_ErrorCalibration_private[i] = 0U; + } + + /* SignalConversion generated from: '/Output' incorporates: + * Constant: '/Constant' + */ + *rty_Output = 4; +} + +/* + * Output and update for atomic system: + * '/param index for mode' + * '/param index for mode' + */ +void paramindexformode(uint8_t rtu_index_mode, double *rty_Y) +{ + /* : switch index_mode */ + switch (rtu_index_mode) { + case 0U: + /* : case 0 */ + /* : Y = 1; */ + *rty_Y = 1.0; + break; + + case 10U: + /* : case 10 */ + /* : Y = 1; */ + *rty_Y = 1.0; + break; + + case 20U: + /* : case 20 */ + /* : Y = 2; */ + *rty_Y = 2.0; + break; + + case 30U: + /* : case 30 */ + /* : Y = 2; */ + *rty_Y = 2.0; + break; + + case 40U: + /* : case 40 */ + /* : Y = 3; */ + *rty_Y = 3.0; + break; + + case 50U: + /* : case 50 */ + /* : Y = 3; */ + *rty_Y = 3.0; + break; + + case 60U: + /* : case 60 */ + /* : Y = 3; */ + *rty_Y = 3.0; + break; + + case 70U: + /* : case 70 */ + /* : Y = 4; */ + *rty_Y = 4.0; + break; + + case 80U: + /* : case 80 */ + /* : Y = 4; */ + *rty_Y = 4.0; + break; + + case 90U: + /* : case 90 */ + /* : Y = 4; */ + *rty_Y = 4.0; + break; + + case 100U: + /* : case 100 */ + /* : Y = 4; */ + *rty_Y = 4.0; + break; + + case 110U: + /* : case 110 */ + /* : Y = 2; */ + *rty_Y = 2.0; + break; + + default: + /* : otherwise */ + /* : Y = 1; */ + *rty_Y = 1.0; + break; + } +} + +/* + * Output and update for atomic system: + * '/valves for mode' + * '/valves_front_right' + */ +void valvesformode(uint8_t rtu_MODE, uint16_t rty_get_valves[9]) +{ + int32_t i; + int32_t tmp_0; + uint16_t tmp[45]; + + /* : modes_array = [ */ + /* : g_ausFLOW_FR_VE2VALVE; */ + /* : g_ausFLOW_FR_BIVALVE; */ + /* : g_ausFLOW_FR_BI2VALVE; */ + /* : g_ausFLOW_FR_AF2VALVE; */ + /* : g_ausFLOW_FR_AF2VALVE_SUMMER]; */ + /* : index = idivide(MODE, 10); */ + /* : get_valves = modes_array(index, :); */ + tmp_0 = (int32_t)trunc((double)rtu_MODE / 10.0); + for (i = 0; i < 9; i++) { + tmp[5 * i] = g_ausFLOW_FR_VE2VALVE[i]; + tmp[5 * i + 1] = g_ausFLOW_FR_BIVALVE[i]; + tmp[5 * i + 2] = g_ausFLOW_FR_BI2VALVE[i]; + tmp[5 * i + 3] = g_ausFLOW_FR_AF2VALVE[i]; + tmp[5 * i + 4] = g_ausFLOW_FR_AF2VALVE_SUMMER[i]; + rty_get_valves[i] = tmp[(5 * i + tmp_0) - 1]; + } +} + +/* + * Output and update for atomic system: + * '/valves_rear_left' + * '/valves_rear_right' + */ +void valves_rear_left(uint8_t rtu_MODE, uint16_t rty_get_valves[6]) +{ + int32_t q0; + uint32_t qY; + uint16_t tmp[54]; + + /* : modes_array = [ */ + /* : g_ausFLOW_RE_VENT; */ + /* : g_ausFLOW_RE_BI2VALVE; */ + /* : g_ausFLOW_RE_FO2VALVE; */ + /* : g_ausFLOW_RE_VENT_2; */ + /* : g_ausFLOW_RE_BI2VALVE_2; */ + /* : g_ausFLOW_RE_VENT_3; */ + /* : g_ausFLOW_RE_BI2VALVE_3; */ + /* : g_ausFLOW_RE_VENT_MANUAL; */ + /* : g_ausFLOW_RE_BI2VALVE_MANUAL; */ + /* : ]; */ + /* : index = idivide(MODE, 10) - 11; */ + /* : get_valves = modes_array(index, :); */ + q0 = (int32_t)trunc((double)rtu_MODE / 10.0); + + /* MW:begin MISRA2012:D4.1 CERT-C:INT30-C 'Justifying MISRA CPP rule violation' */ + qY = (uint32_t)q0 - 11U; + + /* MW:end MISRA2012:D4.1 CERT-C:INT30-C */ + if ((uint32_t)q0 - 11U > (uint32_t)q0) { + qY = 0U; + } + + for (q0 = 0; q0 < 6; q0++) { + tmp[9 * q0] = g_ausFLOW_RE_VENT[q0]; + tmp[9 * q0 + 1] = g_ausFLOW_RE_BI2VALVE[q0]; + tmp[9 * q0 + 2] = g_ausFLOW_RE_FO2VALVE[q0]; + tmp[9 * q0 + 3] = g_ausFLOW_RE_VENT_2[q0]; + tmp[9 * q0 + 4] = g_ausFLOW_RE_BI2VALVE_2[q0]; + tmp[9 * q0 + 5] = g_ausFLOW_RE_VENT_3[q0]; + tmp[9 * q0 + 6] = g_ausFLOW_RE_BI2VALVE_3[q0]; + tmp[9 * q0 + 7] = g_ausFLOW_RE_VENT_MANUAL[q0]; + tmp[9 * q0 + 8] = g_ausFLOW_RE_BI2VALVE_MANUAL[q0]; + rty_get_valves[q0] = tmp[(9 * q0 + (int32_t)qY) - 1]; + } +} + +/* + * Output and update for atomic system: + * '/MODE_for_set_and_lvl' + * '/MODE_for_set_and_lvl1' + */ +void MODE_for_set_and_lvl(uint8_t rtu_LVL, int16_t rtu_SET, uint8_t + *rty_get_mode) +{ + int32_t i; + int32_t tmp_0; + uint8_t tmp[78]; + + /* : modes_array = [ */ + /* : g_aucMODE_BY_SET_F_LV0; */ + /* : g_aucMODE_BY_SET_F_LV1; */ + /* : g_aucMODE_BY_SET_F_LV2; */ + /* : g_aucMODE_BY_SET_F_LV3; */ + /* : g_aucMODE_BY_SET_F_LV4; */ + /* : g_aucMODE_BY_SET_F_LV5]; */ + /* : get_mode = modes_array(LVL + 1, SET - 16); */ + for (i = 0; i < 13; i++) { + tmp[6 * i] = g_aucMODE_BY_SET_F_LV0[i]; + tmp[6 * i + 1] = g_aucMODE_BY_SET_F_LV1[i]; + tmp[6 * i + 2] = g_aucMODE_BY_SET_F_LV2[i]; + tmp[6 * i + 3] = g_aucMODE_BY_SET_F_LV3[i]; + tmp[6 * i + 4] = g_aucMODE_BY_SET_F_LV4[i]; + tmp[6 * i + 5] = g_aucMODE_BY_SET_F_LV5[i]; + } + + i = (int32_t)(rtu_LVL + 1U); + if (rtu_LVL + 1U > 255U) { + i = 255; + } + + tmp_0 = rtu_SET - 16; + if (rtu_SET - 16 < -32768) { + tmp_0 = -32768; + } + + *rty_get_mode = tmp[((tmp_0 - 1) * 6 + i) - 1]; +} + +/* + * Output and update for atomic system: + * '/increase' + * '/increase' + */ +void increase(int16_t rtu_duct_tg, const uint16_t rtu_mode_array[7], uint16_t + *rty_y) +{ + /* : threshold_low = mode_array(2); */ + /* : threshold_high = mode_array(4); */ + /* : value_low = mode_array(5); */ + /* : value_mid = mode_array(6); */ + /* : value_high = mode_array(7); */ + /* : if duct_tg < threshold_low */ + if (rtu_duct_tg < rtu_mode_array[1]) { + /* : y = value_low; */ + *rty_y = rtu_mode_array[4]; + } else if (rtu_duct_tg < rtu_mode_array[3]) { + /* : elseif duct_tg < threshold_high */ + /* : y = value_mid; */ + *rty_y = rtu_mode_array[5]; + } else { + /* : else */ + /* : y = value_high; */ + *rty_y = rtu_mode_array[6]; + } +} + +/* + * Output and update for atomic system: + * '/decrease' + * '/decrease' + */ +void decrease(int16_t rtu_duct_tg, const uint16_t rtu_mode_array[7], uint16_t + *rty_y) +{ + /* : threshold_low = mode_array(1); */ + /* : threshold_high = mode_array(3); */ + /* : value_low = mode_array(5); */ + /* : value_mid = mode_array(6); */ + /* : value_high = mode_array(7); */ + /* : if duct_tg < threshold_low */ + if (rtu_duct_tg < rtu_mode_array[0]) { + /* : y = value_low; */ + *rty_y = rtu_mode_array[4]; + } else if (rtu_duct_tg < rtu_mode_array[2]) { + /* : elseif duct_tg < threshold_high */ + /* : y = value_mid; */ + *rty_y = rtu_mode_array[5]; + } else { + /* : else */ + /* : y = value_high; */ + *rty_y = rtu_mode_array[6]; + } +} + +/* + * Output and update for atomic system: + * '/valves_rear_left' + * '/valves_rear_right' + */ +void valves_rear_left_e(uint16_t rtu_MODE, uint16_t rty_get_valves[6]) +{ + int32_t q0; + uint32_t qY; + uint16_t tmp[54]; + + /* : modes_array = [ */ + /* : g_ausFLOW_RE_VENT; */ + /* : g_ausFLOW_RE_BI2VALVE; */ + /* : g_ausFLOW_RE_FO2VALVE; */ + /* : g_ausFLOW_RE_VENT_2; */ + /* : g_ausFLOW_RE_BI2VALVE_2; */ + /* : g_ausFLOW_RE_VENT_3; */ + /* : g_ausFLOW_RE_BI2VALVE_3; */ + /* : g_ausFLOW_RE_VENT_MANUAL; */ + /* : g_ausFLOW_RE_BI2VALVE_MANUAL; */ + /* : ]; */ + /* : index = idivide(MODE, 10) - 11; */ + /* : get_valves = modes_array(index, :); */ + q0 = (int32_t)trunc((double)rtu_MODE / 10.0); + + /* MW:begin MISRA2012:D4.1 CERT-C:INT30-C 'Justifying MISRA CPP rule violation' */ + qY = (uint32_t)q0 - 11U; + + /* MW:end MISRA2012:D4.1 CERT-C:INT30-C */ + if ((uint32_t)q0 - 11U > (uint32_t)q0) { + qY = 0U; + } + + for (q0 = 0; q0 < 6; q0++) { + tmp[9 * q0] = g_ausFLOW_RE_VENT[q0]; + tmp[9 * q0 + 1] = g_ausFLOW_RE_BI2VALVE[q0]; + tmp[9 * q0 + 2] = g_ausFLOW_RE_FO2VALVE[q0]; + tmp[9 * q0 + 3] = g_ausFLOW_RE_VENT_2[q0]; + tmp[9 * q0 + 4] = g_ausFLOW_RE_BI2VALVE_2[q0]; + tmp[9 * q0 + 5] = g_ausFLOW_RE_VENT_3[q0]; + tmp[9 * q0 + 6] = g_ausFLOW_RE_BI2VALVE_3[q0]; + tmp[9 * q0 + 7] = g_ausFLOW_RE_VENT_MANUAL[q0]; + tmp[9 * q0 + 8] = g_ausFLOW_RE_BI2VALVE_MANUAL[q0]; + rty_get_valves[q0] = tmp[(9 * q0 + (int32_t)qY) - 1]; + } +} + +/* + * Output and update for atomic system: + * '/Valves for Bi Level' + * '/Valves for Bi Level' + */ +void ValvesforBiLevel(uint16_t rty_out[9]) +{ + int32_t i; + for (i = 0; i < 9; i++) { + rty_out[i] = g_ausFLOW_FR_BIVALVE_MANUAL[i]; + } + + /* : out = g_ausFLOW_FR_BIVALVE_MANUAL; */ +} + +/* + * Output and update for atomic system: + * '/Valves for Foot + Def' + * '/Valves for Foot + Def' + */ +void ValvesforFootDef(uint16_t rty_out[9]) +{ + int32_t i; + for (i = 0; i < 9; i++) { + rty_out[i] = g_ausFLOW_FR_FD2VALVE[i]; + } + + /* : out = g_ausFLOW_FR_FD2VALVE; */ +} + +/* + * Output and update for atomic system: + * '/Valves for Hi_Level' + * '/Valves for Hi_Level' + */ +void ValvesforHi_Level(uint16_t rty_out[9]) +{ + int32_t i; + for (i = 0; i < 9; i++) { + rty_out[i] = g_ausFLOW_FR_HI2VALVE[i]; + } + + /* : out = g_ausFLOW_FR_HI2VALVE; */ +} + +/* + * Output and update for atomic system: + * '/Valves for Tri-Level' + * '/Valves for Tri-Level' + */ +void ValvesforTriLevel(uint16_t rty_out[9]) +{ + int32_t i; + for (i = 0; i < 9; i++) { + rty_out[i] = g_ausFLOW_FR_TR2VALVE[i]; + } + + /* : out = g_ausFLOW_FR_TR2VALVE; */ +} + +/* + * Output and update for atomic system: + * '/AF for Bi Level' + * '/AF for Bi Level' + */ +void AFforBiLevel_i(uint16_t rty_out[6]) +{ + int32_t i; + for (i = 0; i < 6; i++) { + rty_out[i] = g_ausFLOW_RE_BI2VALVE_MANUAL[i]; + } + + /* : out = g_ausFLOW_RE_BI2VALVE_MANUAL; */ +} + +/* + * Output and update for atomic system: + * '/valves for Vent mode' + * '/valves for Vent mode' + */ +void valvesforVentmode(uint16_t rty_out[6]) +{ + int32_t i; + for (i = 0; i < 6; i++) { + rty_out[i] = g_ausFLOW_RE_VENT_MANUAL[i]; + } + + /* : out = g_ausFLOW_RE_VENT_MANUAL; */ +} + +/* Function for Chart: '/A//C Control' */ +static void E_COMP_MANAGER(bool *Enable_Comp_PID, const int16_t *Eva_F_tg, const + int16_t *Eva_R_tg) +{ + if (rtDW.is_E_COMP_MANAGER == IN_COMP_OFF) { + *Enable_Comp_PID = false; + + /* DataStoreRead: '/Data Store Read55' incorporates: + * DataStoreRead: '/Data Store Read37' + */ + /* : sf_internal_predicateOutput = (FRONT_Start_request ==1 || REAR_Start_request == 1 || Chiller_Start_request ==1) && Pressure_Hi_Fault == 0 && Pressure_Condition_table_OK == 1 && eCompChiller_Err==false && BCM_T15_Stat == 1; */ + if ((rtDW.FRONT_Start_request || rtDW.REAR_Start_request || + rtDW.Chiller_Start_request) && (!rtDW.Pressure_Hi_Fault) && + rtDW.Pressure_Condition_table_OK && (rtDW.eCompChiller_Err == 0.0) && + (rtDW.BCM_T15_Stat == 1)) { + rtDW.is_E_COMP_MANAGER = IN_COMP_ON; + + /* : Enable_Comp_PID = true; */ + *Enable_Comp_PID = true; + } + } else { + bool tmp; + bool tmp_0; + + /* case IN_COMP_ON: */ + *Enable_Comp_PID = true; + + /* : sf_internal_predicateOutput = [(FRONT_Start_request ==0 && REAR_Start_request == 0 && Chiller_Start_request ==0) || Pressure_Hi_Fault == 1 || Pressure_Condition_table_OK == 0 || eCompChiller_Err==true || BCM_T15_Stat == 0]; */ + tmp = !rtDW.FRONT_Start_request; + tmp_0 = !rtDW.REAR_Start_request; + + /* DataStoreRead: '/Data Store Read55' incorporates: + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read37' + * DataStoreRead: '/Data Store Read52' + * DataStoreRead: '/Data Store Read54' + * DataStoreWrite: '/Data Store Write35' + * DataStoreWrite: '/Data Store Write36' + */ + if ((tmp && tmp_0 && (!rtDW.Chiller_Start_request)) || + rtDW.Pressure_Hi_Fault || (!rtDW.Pressure_Condition_table_OK) || + (rtDW.eCompChiller_Err == 1.0) || (rtDW.BCM_T15_Stat == 0)) { + rtDW.is_E_COMP_MANAGER = IN_COMP_OFF; + + /* : Enable_Comp_PID = false; */ + *Enable_Comp_PID = false; + + /* : Chiller_Only_Flag = 0; */ + rtB.Chiller_Only_Flag = 0.0; + + /* : Comp_Feedback_Temp = 0; */ + rtB.Comp_Feedback_Temp = 0; + + /* : FRONT_eTXV = true; */ + rtB.FRONT_eTXV = true; + + /* : REAR_eTXV = true; */ + rtB.REAR_eTXV = true; + + /* : Chiller_eTXV = true; */ + rtB.Chiller_eTXV = true; + + /* : Eva_Ctrl = 0; */ + rtB.Eva_Ctrl = 0U; + } else { + bool tmp_1; + bool tmp_2; + + /* : FRONT_eTXV = (FRONT_Start_request == 1); */ + rtB.FRONT_eTXV = rtDW.FRONT_Start_request; + + /* : REAR_eTXV = (REAR_Start_request == 1); */ + rtB.REAR_eTXV = rtDW.REAR_Start_request; + + /* : Chiller_eTXV = (Chiller_Start_request == 1); */ + rtB.Chiller_eTXV = rtDW.Chiller_Start_request; + + /* : if FRONT_Start_request == 1 && REAR_Start_request == 1 */ + tmp_1 = (rtDW.FRONT_Start_request && rtDW.REAR_Start_request); + if (tmp_1) { + /* : if Eva_R < Eva_F */ + if (rtDW.Eva_R < rtDW.Eva_F) { + /* : Comp_Feedback_Temp = Eva_R; */ + rtB.Comp_Feedback_Temp = rtDW.Eva_R; + + /* : Comp_Target_Temp = Target_Rear; */ + rtB.Comp_Target_Temp = *Eva_R_tg; + } else { + /* : else */ + /* : Comp_Feedback_Temp = Eva_F; */ + rtB.Comp_Feedback_Temp = rtDW.Eva_F; + + /* : Comp_Target_Temp = Target_Front; */ + rtB.Comp_Target_Temp = *Eva_F_tg; + } + } else if (rtDW.FRONT_Start_request) { + /* : elseif FRONT_Start_request == 1 */ + /* : Comp_Feedback_Temp = Eva_F; */ + rtB.Comp_Feedback_Temp = rtDW.Eva_F; + + /* : Comp_Target_Temp = Target_Front; */ + rtB.Comp_Target_Temp = *Eva_F_tg; + } else if (rtDW.REAR_Start_request) { + /* : elseif REAR_Start_request == 1 */ + /* : Comp_Feedback_Temp = Eva_R; */ + rtB.Comp_Feedback_Temp = rtDW.Eva_R; + + /* : Comp_Target_Temp = Target_Rear; */ + rtB.Comp_Target_Temp = *Eva_R_tg; + } else { + /* : else */ + /* : Comp_Feedback_Temp = Eva_F; */ + rtB.Comp_Feedback_Temp = rtDW.Eva_F; + + /* : Comp_Target_Temp = Target_Front; */ + rtB.Comp_Target_Temp = *Eva_F_tg; + } + + /* : if Comp_Feedback_Temp == Eva_R */ + if ((rtB.Comp_Feedback_Temp == rtDW.Eva_R) && (rtDW.CCU_SET_RL < 200)) { + /* : if Rear_set_temp < 200 */ + /* : Comp_Target_Temp = int16(30); */ + rtB.Comp_Target_Temp = 30; + } + + /* : if Chiller_Start_request == 1 && FRONT_Start_request == 0 && REAR_Start_request == 0 */ + tmp_2 = (rtDW.Chiller_Start_request && tmp && tmp_0); + if (tmp_2) { + /* : Chiller_Only_Flag = 1; */ + rtB.Chiller_Only_Flag = 1.0; + } else { + /* : else */ + /* : Chiller_Only_Flag = 0; */ + rtB.Chiller_Only_Flag = 0.0; + } + + /* : if FRONT_Start_request == 1 && REAR_Start_request == 1 */ + if (tmp_1) { + /* : if Eva_R < Eva_F */ + if (rtDW.Eva_R < rtDW.Eva_F) { + /* : Eva_Ctrl = 5; */ + rtB.Eva_Ctrl = 5U; + } else { + /* : else */ + /* : Eva_Ctrl = 4; */ + rtB.Eva_Ctrl = 4U; + } + } else if (rtDW.FRONT_Start_request && tmp_0) { + /* : elseif FRONT_Start_request == 1 && REAR_Start_request == 0 */ + /* : Eva_Ctrl = 2; */ + rtB.Eva_Ctrl = 2U; + } else if (tmp && rtDW.REAR_Start_request) { + /* : elseif FRONT_Start_request == 0 && REAR_Start_request == 1 */ + /* : Eva_Ctrl = 3; */ + rtB.Eva_Ctrl = 3U; + } else if (tmp_2) { + /* : elseif Chiller_Start_request == 1 && FRONT_Start_request == 0 && REAR_Start_request == 0 */ + /* : Eva_Ctrl = 1; */ + rtB.Eva_Ctrl = 1U; + } else { + /* : else */ + /* : Eva_Ctrl = 0; */ + rtB.Eva_Ctrl = 0U; + } + } + } +} + +/* Function for Chart: '/Synchronization stateflow chart' */ +static void enter_atomic_REAR_ONLY(void) +{ + /* : sync_state = 3; */ + /* : sync_front = 0; */ + rtB.sync_front = 0U; + + /* : sync_rear = 1; */ + rtB.sync_rear = 1U; + + /* : sync_all = 0; */ + rtB.sync_all = 0U; + + /* : enable_full_sync=0; */ + rtDW.enable_full_sync = 0U; + + /* : enable_rear_sync = 0; */ + rtDW.enable_rear_sync = 0U; + + /* : enable_front_sync = 0; */ + rtDW.enable_front_sync = 0U; + + /* : disable_front_sync = 0; */ + rtDW.disable_front_sync = 0U; + + /* : disable_rear_sync = 0; */ + rtDW.disable_rear_sync = 0U; + + /* : changed_FR_params = 0; */ + rtDW.changed_FR_params = 0U; + + /* : changed_RL_params = 0; */ + rtDW.changed_RL_params = 0U; + + /* : changed_RR_params = 0 */ + rtDW.changed_RR_params = 0U; +} + +/* Function for Chart: '/Synchronization stateflow chart' */ +static void enter_atomic_FRONT_ONLY(void) +{ + /* : sync_state = 1; */ + /* : sync_front = 1; */ + rtB.sync_front = 1U; + + /* : sync_rear = 0; */ + rtB.sync_rear = 0U; + + /* : sync_all = 0; */ + rtB.sync_all = 0U; + + /* : enable_full_sync=0; */ + rtDW.enable_full_sync = 0U; + + /* : enable_rear_sync = 0; */ + rtDW.enable_rear_sync = 0U; + + /* : enable_front_sync = 0; */ + rtDW.enable_front_sync = 0U; + + /* : disable_front_sync = 0; */ + rtDW.disable_front_sync = 0U; + + /* : disable_rear_sync = 0; */ + rtDW.disable_rear_sync = 0U; + + /* : changed_FR_params = 0; */ + rtDW.changed_FR_params = 0U; + + /* : changed_RL_params = 0; */ + rtDW.changed_RL_params = 0U; + + /* : changed_RR_params = 0 */ + rtDW.changed_RR_params = 0U; +} + +/* Function for Chart: '/Synchronization stateflow chart' */ +static void enter_atomic_FULL_SYNC(void) +{ + /* : sync_state = 2; */ + /* : sync_front = 0; */ + rtB.sync_front = 0U; + + /* : sync_rear = 0; */ + rtB.sync_rear = 0U; + + /* : sync_all = 1; */ + rtB.sync_all = 1U; + + /* : enable_full_sync=0; */ + rtDW.enable_full_sync = 0U; + + /* : enable_rear_sync = 0; */ + rtDW.enable_rear_sync = 0U; + + /* : enable_front_sync = 0; */ + rtDW.enable_front_sync = 0U; + + /* : disable_front_sync = 0; */ + rtDW.disable_front_sync = 0U; + + /* : disable_rear_sync = 0; */ + rtDW.disable_rear_sync = 0U; + + /* : changed_FR_params = 0; */ + rtDW.changed_FR_params = 0U; + + /* : changed_RL_params = 0; */ + rtDW.changed_RL_params = 0U; + + /* : changed_RR_params = 0 */ + rtDW.changed_RR_params = 0U; +} + +/* Function for Chart: '/Synchronization stateflow chart' */ +static void enter_atomic_SEPARATE_FRONT_AND_REAR(void) +{ + /* : sync_state = 4; */ + /* : sync_front = 1; */ + rtB.sync_front = 1U; + + /* : sync_rear = 1; */ + rtB.sync_rear = 1U; + + /* : sync_all = 0; */ + rtB.sync_all = 0U; + + /* : enable_full_sync=0; */ + rtDW.enable_full_sync = 0U; + + /* : enable_rear_sync = 0; */ + rtDW.enable_rear_sync = 0U; + + /* : enable_front_sync = 0; */ + rtDW.enable_front_sync = 0U; + + /* : disable_front_sync = 0; */ + rtDW.disable_front_sync = 0U; + + /* : disable_rear_sync = 0; */ + rtDW.disable_rear_sync = 0U; + + /* : changed_FR_params = 0; */ + rtDW.changed_FR_params = 0U; + + /* : changed_RL_params = 0; */ + rtDW.changed_RL_params = 0U; + + /* : changed_RR_params = 0 */ + rtDW.changed_RR_params = 0U; +} + +/* Function for Chart: '/Synchronization stateflow chart' */ +static void enter_atomic_NO_SYNC(void) +{ + /* : sync_state = 0; */ + /* : sync_front = 0; */ + rtB.sync_front = 0U; + + /* : sync_rear = 0; */ + rtB.sync_rear = 0U; + + /* : sync_all = 0; */ + rtB.sync_all = 0U; + + /* : enable_full_sync=0; */ + rtDW.enable_full_sync = 0U; + + /* : enable_rear_sync = 0; */ + rtDW.enable_rear_sync = 0U; + + /* : enable_front_sync = 0; */ + rtDW.enable_front_sync = 0U; + + /* : disable_front_sync = 0; */ + rtDW.disable_front_sync = 0U; + + /* : disable_rear_sync = 0; */ + rtDW.disable_rear_sync = 0U; + + /* : changed_FR_params = 0; */ + rtDW.changed_FR_params = 0U; + + /* : changed_RL_params = 0; */ + rtDW.changed_RL_params = 0U; + + /* : changed_RR_params = 0; */ + rtDW.changed_RR_params = 0U; +} + +/* + * Function for Chart: '/Partial REC' + * function idx = find_index(delta) + */ +static double find_index(int16_t delta) +{ + double idx; + int32_t i; + + /* : idx = 1; */ + idx = 1.0; + + /* : for i = 1:7 */ + i = 0; + while ((i < 7) && (delta >= g_assPREC_EVA_DIFF_FB_TG_F[i])) { + /* : if delta >= g_assPREC_EVA_DIFF_FB_TG_F(i) */ + /* : idx = i; */ + idx = (double)i + 1.0; + i++; + } + + /* : else */ + return idx; +} + +/* Model step function */ +void HVAC_model_step(void) +{ + double rtb_Divide1_a4[9]; + double rtb_Saturation_m0[8]; + double rtb_f_lower_upper_bounds[2]; + double index_start; + double rtb_Add_be; + double rtb_Add_p4; + double rtb_Divide10; + double rtb_Divide11; + double rtb_Divide3; + double rtb_Divide4; + double rtb_Divide6; + double rtb_Divide7; + double rtb_Divide8; + int64_t tmp_3; + int32_t i; + int32_t index_start_0; + int32_t rtb_Gain1_f; + int32_t rtb_Y_l_idx_2; + int32_t rtb_Y_l_idx_3; + uint32_t rtb_Divide4_n_tmp_tmp; + uint32_t rtb_Divide4_n_tmp_tmp_0; + uint32_t rtb_Subtract; + uint32_t rtb_dt_nx; + int16_t rtb_MultiportSwitch1_d[7]; + int16_t rtb_uDLookupTable7_g[7]; + int16_t tmp_2[6]; + int16_t Duct_FRU_Tg_DBG[5]; + int16_t Duct_RR_Tg_DBG[5]; + int16_t rtb_VectorConcatenate_by[5]; + int16_t rtb_VectorConcatenate_jn[5]; + int16_t rtb_VectorConcatenate_kz[5]; + int16_t rtb_VectorConcatenate_lb[5]; + int16_t rtb_VectorConcatenate_dw[3]; + int16_t rtb_VectorConcatenate_gn[3]; + int16_t rtb_VectorConcatenate_np[3]; + int16_t rtb_VectorConcatenate_pg[3]; + int16_t rtb_out_knd[2]; + int16_t Duct1_R; + int16_t Duct2_R; + int16_t Duct3_R; + int16_t Duct4_F; + int16_t Duct4_R; + int16_t Duct5_F; + int16_t Duct6_F; + int16_t Eva_F_tg; + int16_t Eva_R_tg; + int16_t Eva_Target; + int16_t Evap_Target_Offset; + int16_t rtb_Bias1_h; + int16_t rtb_Bias2_n; + int16_t rtb_Bias3; + int16_t rtb_Bias4; + int16_t rtb_Bias5; + int16_t rtb_Bias_ct; + int16_t rtb_FLU_tg_correct; + int16_t rtb_FLU_tg_correct1; + int16_t rtb_FLU_tg_correct_aa; + int16_t rtb_FLU_tg_correct_ot; + int16_t rtb_Merge_b; + int16_t rtb_MultiportSwitch1_g; + int16_t rtb_MultiportSwitch_ci; + int16_t rtb_MultiportSwitch_d; + int16_t rtb_MultiportSwitch_ev; + int16_t rtb_MultiportSwitch_fu; + int16_t rtb_MultiportSwitch_gp; + int16_t rtb_MultiportSwitch_gq; + int16_t rtb_MultiportSwitch_j2; + int16_t rtb_MultiportSwitch_jq; + int16_t rtb_MultiportSwitch_oh; + int16_t rtb_MultiportSwitch_pa; + int16_t rtb_X; + int16_t rtb_u5FLU_tg_incar_b; + int16_t rtb_u5FLU_tg_incar_i; + int16_t rtb_u5FRU_tg_incar; + int16_t rtb_u5R_tg_incar; + int16_t rtb_u6FLU_tg_amb_a3; + int16_t rtb_u6FLU_tg_amb_d; + int16_t rtb_u6FLU_tg_amb_g; + int16_t rtb_u6FLU_tg_amb_h; + int16_t rtb_u6FLU_tg_amb_n; + int16_t rtb_u6FLU_tg_amb_o; + int16_t rtb_u6FRU_tg_amb; + int16_t rtb_u6FRU_tg_amb_f; + int16_t rtb_y_co; + int16_t rtb_y_he; + int16_t rtb_y_jh; + int16_t rtb_y_ki; + int16_t rtb_y_mz; + uint16_t tmp_0[99]; + uint16_t tmp[45]; + uint16_t tmp_1[42]; + uint16_t rtb_out_ea[9]; + uint16_t rtb_out_il[9]; + uint16_t rtb_out_iy[9]; + uint16_t rtb_out_n[9]; + uint16_t rtb_out_p3[9]; + uint16_t rtb_out_pw[9]; + uint16_t rtb_out_ai[8]; + uint16_t rtb_out_c[8]; + uint16_t rtb_out_f[8]; + uint16_t rtb_out_if[8]; + uint16_t rtb_out_ixa[8]; + uint16_t rtb_out_ju[8]; + uint16_t rtb_out_k1[8]; + uint16_t rtb_out_ky[8]; + uint16_t rtb_out_l[8]; + uint16_t rtb_out_pq2[8]; + uint16_t rtb_out_pv[8]; + uint16_t rtb_get_mode[7]; + uint16_t rtb_Gain1_o3[6]; + uint16_t rtb_TmpSignalConversionAt1DLookupTable7Inport1[6]; + uint16_t rtb_out_gx[2]; + uint16_t Gain; + uint16_t Gain1; + uint16_t rtb_Saturation2_a; + uint16_t rtb_out_e; + uint16_t rtb_out_ew; + uint16_t rtb_out_h0; + uint16_t rtb_out_nc; + uint16_t rtb_out_nj; + int8_t rtb_y_eo; + uint8_t rtb_get_modes_for_levels[78]; + uint8_t Actuator_pos_percent_Ch1[9]; + uint8_t rtb_DataTypeConversion_b4q[9]; + uint8_t rtb_DataTypeConversion_kl[9]; + uint8_t rtb_DataTypeConversion_mo[9]; + uint8_t rtb_DataTypeConversion2_ie[6]; + uint8_t CCU_FRONT_SYNC; + uint8_t Comp_Max_RPM_Allowed; + uint8_t EN_BATTChiller; + uint8_t El_window_heating; + uint8_t ShutOffFront_EN; + uint8_t ShutOffRear_EN; + uint8_t fan_speed_out; + uint8_t rtb_Cmd_3Way; + uint8_t rtb_DataTypeConversion1_lq; + uint8_t rtb_DataTypeConversion1_nc; + uint8_t rtb_DataTypeConversion3_gf; + uint8_t rtb_DataTypeConversion3_gz; + uint8_t rtb_DataTypeConversion3_i; + uint8_t rtb_Merge_c5; + uint8_t rtb_Merge_m4; + uint8_t rtb_Saturation4_f; + uint8_t rtb_timer_out; + bool rtb_LogicalOperator3_nq[9]; + bool rtb_Compare_le[8]; + bool rtb_LogicalOperator3_k[6]; + bool Enable_Comp_PID; + bool eComp_stop; + bool guard1; + bool guard2; + bool rtb_Compare_a; + bool rtb_Compare_cc; + bool rtb_Compare_df; + bool rtb_Compare_e1; + bool rtb_Compare_e3; + bool rtb_Compare_edx; + bool rtb_Compare_fh; + bool rtb_Compare_g1; + bool rtb_Compare_g2; + bool rtb_Compare_gk; + bool rtb_Compare_hg; + bool rtb_Compare_hv; + bool rtb_Compare_i5; + bool rtb_Compare_il; + bool rtb_Compare_ipf; + bool rtb_Compare_ja; + bool rtb_Compare_jl3; + bool rtb_Compare_jz; + bool rtb_Compare_k3; + bool rtb_Compare_kb; + bool rtb_Compare_kbl; + bool rtb_Compare_l; + bool rtb_Compare_ls; + bool rtb_Compare_m1; + bool rtb_Compare_ne; + bool rtb_Compare_ok; + bool rtb_Compare_pb; + bool rtb_FailCond_a; + bool rtb_FailCond_ad; + bool rtb_FailCond_d; + bool rtb_FailCond_e; + bool rtb_FailCond_jb; + bool rtb_FailCond_kd; + bool rtb_FailCond_l; + bool rtb_LogicalOperator1; + bool rtb_LogicalOperator10; + bool rtb_LogicalOperator11; + bool rtb_LogicalOperator1_dv; + bool rtb_LogicalOperator1_n; + bool rtb_LogicalOperator3; + bool rtb_LogicalOperator3_cz; + bool rtb_LogicalOperator4_fo; + bool rtb_LogicalOperator6; + bool rtb_LogicalOperator6_m; + bool rtb_LogicalOperator8; + bool rtb_LogicalOperator8_i; + bool rtb_err; + + /* Gain: '/Gain' incorporates: + * DataStoreRead: '/Data Store Read' + */ + Gain = (uint16_t)(10U * rtDW.PWM_front); + + /* Gain: '/Gain1' incorporates: + * DataStoreRead: '/Data Store Read47' + */ + Gain1 = (uint16_t)(10U * rtDW.PWM_rear); + + /* Switch: '/Switch4' incorporates: + * Constant: '/Constant8' + * DataStoreRead: '/Data Store Read44' + * DataStoreRead: '/Data Store Read77' + * RelationalOperator: '/Relational Operator2' + */ + if (rtDW.condition_ac_max == 1.0) { + rtb_y_he = 1; + } else { + rtb_y_he = rtDW.CCU_AC_FRONT; + } + + /* End of Switch: '/Switch4' */ + + /* Switch: '/Switch2' incorporates: + * Constant: '/Constant12' + * DataStoreRead: '/Data Store Read45' + * DataStoreRead: '/Data Store Read76' + * DataStoreWrite: '/Data Store Write35' + * DataStoreWrite: '/Data Store Write36' + * Lookup_n-D: '/g_assEVA_TG_AMB_F' + * Lookup_n-D: '/g_assEVA_TG_AMB_R' + * Switch: '/Switch3' + */ + if (rtDW.CCU_AC_MAX > 0) { + Eva_F_tg = 2; + Eva_R_tg = 2; + } else { + Eva_F_tg = look1_is16lu64n32Ds32_binlcs(rtDW.AMB, &g_assFAILURE_AMB_TEMP[0], + &g_assEVA_TG_AMB_F[0], 12U); + Eva_R_tg = look1_is16lu64n32Ds32_binlcs(rtDW.AMB, &g_assFAILURE_AMB_TEMP[0], + &g_assEVA_TG_AMB_R[0], 12U); + } + + /* End of Switch: '/Switch2' */ + + /* Chart: '/A//C Control' incorporates: + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read37' + * DataStoreRead: '/Data Store Read45' + * DataStoreRead: '/Data Store Read50' + * DataStoreRead: '/Data Store Read51' + * DataStoreRead: '/Data Store Read52' + * DataStoreRead: '/Data Store Read53' + * DataStoreRead: '/Data Store Read58' + * DataStoreRead: '/Data Store Read59' + * DataStoreRead: '/Data Store Read74' + * DataStoreRead: '/Data Store Read79' + * DataStoreRead: '/Data Store Read80' + * DataTypeConversion: '/Data Type Conversion' + * DataTypeConversion: '/Data Type Conversion3' + * Gain: '/Gain2' + * Gain: '/Gain3' + * Lookup_n-D: '/1-D Lookup Table' + * Lookup_n-D: '/1-D Lookup Table1' + */ + if (rtDW.is_active_c621_HVAC_model == 0U) { + rtDW.is_active_c621_HVAC_model = 1U; + rtDW.is_PRESSURE_MONITOR = IN_PRESSURE_OK; + + /* : Pressure_Condition_table_OK = true; */ + rtDW.Pressure_Condition_table_OK = true; + + /* : Pressure_Hi_Fault = false; */ + rtDW.Pressure_Hi_Fault = false; + rtDW.is_FRONT_CONTOUR = IN_Front_A_C_OFF; + + /* : FRONT_Start_request = false; */ + rtDW.FRONT_Start_request = false; + rtDW.is_REAR_CONTOUR = IN_Rear_A_C_OFF; + + /* : REAR_Start_request = false; */ + rtDW.REAR_Start_request = false; + rtDW.is_CHILLER_CONTOUR = IN_Chiller_OFF; + + /* : Chiller_Start_request = false; */ + rtDW.Chiller_Start_request = false; + rtDW.is_E_COMP_MANAGER = IN_COMP_OFF; + + /* : Enable_Comp_PID = false; */ + Enable_Comp_PID = false; + + /* : Chiller_Only_Flag = 0; */ + rtB.Chiller_Only_Flag = 0.0; + + /* : Comp_Feedback_Temp = 0; */ + rtB.Comp_Feedback_Temp = 0; + + /* : FRONT_eTXV = true; */ + rtB.FRONT_eTXV = true; + + /* : REAR_eTXV = true; */ + rtB.REAR_eTXV = true; + + /* : Chiller_eTXV = true; */ + rtB.Chiller_eTXV = true; + + /* : Eva_Ctrl = 0; */ + rtB.Eva_Ctrl = 0U; + rtDW.is_COMP_PROTECTION = IN_PROT_LEVEL_0; + + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + /* : Logic_Ac_Comp_Protection_Level = 0; */ + rtDW.dbg_Logic_Ac_model.Logic_Ac_Comp_Protection_Level = 0U; + + /* : Comp_Max_RPM_Allowed = 170; */ + Comp_Max_RPM_Allowed = 170U; + + /* : Evap_Target_Offset = 0; */ + Evap_Target_Offset = 0; + } else { + switch (rtDW.is_PRESSURE_MONITOR) { + case IN_FAULT_HIGH_PRESS: + /* Switch: '/Switch' incorporates: + * Constant: '/Constant3' + * Constant: '/Constant4' + * DataStoreRead: '/Data Store Read45' + */ + /* : sf_internal_predicateOutput = Pressure_sen < P_Hi_CutOff; */ + if (rtDW.AMB > 400) { + rtb_FLU_tg_correct_aa = g_assAC_PRESSURE_HYS_HI_ENG_ON[0]; + } else { + rtb_FLU_tg_correct_aa = g_assAC_PRESSURE_HYS_HI_ENG_ON[2]; + } + + /* Gain: '/Gain2' incorporates: + * Switch: '/Switch' + */ + i = 15857 * rtb_FLU_tg_correct_aa; + if (rtDW.Pressure < ((((uint32_t)i & 8192U) != 0U) && ((((uint32_t)i & + 8191U) != 0U) || (i > 0))) + (i >> 14)) { + rtDW.is_PRESSURE_MONITOR = IN_PRESSURE_OK; + + /* : Pressure_Condition_table_OK = true; */ + rtDW.Pressure_Condition_table_OK = true; + + /* : Pressure_Hi_Fault = false; */ + rtDW.Pressure_Hi_Fault = false; + } + break; + + case IN_FAULT_LOW_PRESS: + /* : sf_internal_predicateOutput = Pressure_sen > P_threshold_UP; */ + if (rtDW.Pressure > look1_is16lu64n32Ds32_binlcs(rtDW.AMB, + &g_assFAILURE_AMB_TEMP[0], &g_assAC_PRESSURE_LOW_HYS_UP[0], 12U)) { + rtDW.is_PRESSURE_MONITOR = IN_PRESSURE_OK; + + /* : Pressure_Condition_table_OK = true; */ + rtDW.Pressure_Condition_table_OK = true; + + /* : Pressure_Hi_Fault = false; */ + rtDW.Pressure_Hi_Fault = false; + } + break; + + default: + /* case IN_PRESSURE_OK: */ + /* : sf_internal_predicateOutput = Pressure_sen < P_threshold_DN; */ + if (rtDW.Pressure < look1_is16lu64n32Ds32_binlcs(rtDW.AMB, + &g_assFAILURE_AMB_TEMP[0], &g_assAC_PRESSURE_LOW_HYS_DN[0], 12U)) { + rtDW.is_PRESSURE_MONITOR = IN_FAULT_LOW_PRESS; + + /* : Pressure_Condition_table_OK = false; */ + rtDW.Pressure_Condition_table_OK = false; + } else { + /* Gain: '/Gain3' incorporates: + * Constant: '/Constant5' + */ + /* : sf_internal_predicateOutput = Pressure_sen > P_Hi_Return; */ + i = 15857 * g_assAC_PRESSURE_HYS_HI_ENG_ON[1]; + if (rtDW.Pressure > ((((uint32_t)i & 8192U) != 0U) && ((((uint32_t)i & + 8191U) != 0U) || (i > 0))) + (i >> 14)) { + rtDW.is_PRESSURE_MONITOR = IN_FAULT_HIGH_PRESS; + + /* : Pressure_Hi_Fault = true; */ + rtDW.Pressure_Hi_Fault = true; + } + } + break; + } + + if (rtDW.is_FRONT_CONTOUR == IN_Front_A_C_OFF) { + /* : sf_internal_predicateOutput = AC_Req_MMS == 1 && pwm_front>= (g_ausMIN_PWM(1)-1) && Error_PressSen == 0 && Error_Eva_F == 0 && Eva_F > 0 && amb_temp>g_assAC_CUT_OFF_AMB_F(1) && Pressure_Condition_table_OK == 1; */ + rtb_Subtract = g_ausMIN_PWM[0] - 1U; + if (g_ausMIN_PWM[0] - 1U > g_ausMIN_PWM[0]) { + rtb_Subtract = 0U; + } + + if ((rtb_y_he != 0) && ((Gain >= (int32_t)rtb_Subtract) && + ((rtDW.CCU_PressSenErr_Stat == 0) && + (rtDW.CCU_EvaTempSenErrF_Stat == 0) && (rtDW.Eva_F > 0) && + ((rtDW.AMB > g_assAC_CUT_OFF_AMB_F[0]) && + rtDW.Pressure_Condition_table_OK)))) { + rtDW.is_FRONT_CONTOUR = IN_Front_A_C_ON; + + /* : FRONT_Start_request = true; */ + rtDW.FRONT_Start_request = true; + } + } else { + /* case IN_Front_A_C_ON: */ + /* : sf_internal_predicateOutput = AC_Req_MMS == 0 || pwm_front < (g_ausMIN_PWM(1)-1) || Error_PressSen == 1 || Error_Eva_F == 1 || Eva_F <= 0 || amb_temp<=g_assAC_CUT_OFF_AMB_F(2) || Pressure_Condition_table_OK == 0; */ + rtb_Subtract = g_ausMIN_PWM[0] - 1U; + if (g_ausMIN_PWM[0] - 1U > g_ausMIN_PWM[0]) { + rtb_Subtract = 0U; + } + + if ((rtb_y_he == 0) || ((Gain < (int32_t)rtb_Subtract) || + ((rtDW.CCU_PressSenErr_Stat == 1) || + (rtDW.CCU_EvaTempSenErrF_Stat == 1) || (rtDW.Eva_F <= 0) || + ((rtDW.AMB <= g_assAC_CUT_OFF_AMB_F[1]) || ((rtDW.AMB > + g_assAC_CUT_OFF_AMB_F[1]) && (!rtDW.Pressure_Condition_table_OK)))))) + { + rtDW.is_FRONT_CONTOUR = IN_Front_A_C_OFF; + + /* : FRONT_Start_request = false; */ + rtDW.FRONT_Start_request = false; + } + } + + if (rtDW.is_REAR_CONTOUR == IN_Rear_A_C_OFF) { + /* : sf_internal_predicateOutput = AC_Req_MMS_Rear == 1 && pwm_rear >= (g_ausMIN_PWM(2)-1) && Error_PressSen == 0 && Error_Eva_R == 0 && Eva_R > 0 && amb_temp>g_assAC_CUT_OFF_AMB_R(2) && Pressure_Condition_table_OK == 1; */ + rtb_Subtract = g_ausMIN_PWM[1] - 1U; + if (g_ausMIN_PWM[1] - 1U > g_ausMIN_PWM[1]) { + rtb_Subtract = 0U; + } + + if ((rtDW.CCU_AC_REAR != 0) && ((Gain1 >= (int32_t)rtb_Subtract) && + ((rtDW.CCU_PressSenErr_Stat == 0) && (rtDW.CCU_EvaTempSenErrR_Stat == + 0) && (rtDW.Eva_R > 0) && ((rtDW.AMB > g_assAC_CUT_OFF_AMB_R[1]) && + rtDW.Pressure_Condition_table_OK)))) { + rtDW.is_REAR_CONTOUR = IN_Rear_A_C_ON; + + /* : REAR_Start_request = true; */ + rtDW.REAR_Start_request = true; + } + } else { + /* case IN_Rear_A_C_ON: */ + /* : sf_internal_predicateOutput = [AC_Req_MMS_Rear == 0 || pwm_rear < (g_ausMIN_PWM(2)-1) || Error_PressSen == 1 || Error_Eva_R == 1 || Eva_R <= 0 || amb_temp<=g_assAC_CUT_OFF_AMB_R(1) || Pressure_Condition_table_OK == 0]; */ + rtb_Subtract = g_ausMIN_PWM[1] - 1U; + if (g_ausMIN_PWM[1] - 1U > g_ausMIN_PWM[1]) { + rtb_Subtract = 0U; + } + + if ((rtDW.CCU_AC_REAR == 0) || ((Gain1 < (int32_t)rtb_Subtract) || + ((rtDW.CCU_PressSenErr_Stat == 1) || (rtDW.CCU_EvaTempSenErrR_Stat == + 1) || (rtDW.Eva_R <= 0) || ((rtDW.AMB <= g_assAC_CUT_OFF_AMB_R[0]) || + ((rtDW.AMB > g_assAC_CUT_OFF_AMB_R[0]) && + (!rtDW.Pressure_Condition_table_OK)))))) { + rtDW.is_REAR_CONTOUR = IN_Rear_A_C_OFF; + + /* : REAR_Start_request = false; */ + rtDW.REAR_Start_request = false; + } + } + + if (rtDW.is_CHILLER_CONTOUR == IN_Chiller_OFF) { + /* : sf_internal_predicateOutput = eCompChiller_Req==1 && Pressure_Condition_table_OK == 1 && Error_PressSen == 0 && BCM_T15_Stat==1; */ + if ((rtDW.eCompChiller_Req == 1) && rtDW.Pressure_Condition_table_OK && + (rtDW.CCU_PressSenErr_Stat == 0) && (rtDW.BCM_T15_Stat == 1)) { + rtDW.is_CHILLER_CONTOUR = IN_Chiller_ON; + + /* : Chiller_Start_request = true; */ + rtDW.Chiller_Start_request = true; + } + + /* case IN_Chiller_ON: */ + /* : sf_internal_predicateOutput = eCompChiller_Req==0 || Pressure_Condition_table_OK == 0 || Error_PressSen == 1; */ + } else if ((rtDW.eCompChiller_Req == 0) || + (!rtDW.Pressure_Condition_table_OK) || (rtDW.CCU_PressSenErr_Stat + == 1)) { + rtDW.is_CHILLER_CONTOUR = IN_Chiller_OFF; + + /* : Chiller_Start_request = false; */ + rtDW.Chiller_Start_request = false; + } + + E_COMP_MANAGER(&Enable_Comp_PID, &Eva_F_tg, &Eva_R_tg); + switch (rtDW.is_COMP_PROTECTION) { + case IN_PROT_LEVEL_0: + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + rtDW.dbg_Logic_Ac_model.Logic_Ac_Comp_Protection_Level = 0U; + Comp_Max_RPM_Allowed = 170U; + Evap_Target_Offset = 0; + + /* : sf_internal_predicateOutput = HVC_CompInputC_Val >= 160 || HVC_CompInvTemp_Val >= 1100; */ + if ((rtDW.eComp_InputC >= 40960) || (rtDW.eComp_Temp >= 1100)) { + rtDW.is_COMP_PROTECTION = IN_PROT_LEVEL_1; + + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + /* : Logic_Ac_Comp_Protection_Level = 1; */ + rtDW.dbg_Logic_Ac_model.Logic_Ac_Comp_Protection_Level = 1U; + + /* : Comp_Max_RPM_Allowed = 140; */ + Comp_Max_RPM_Allowed = 140U; + + /* : Evap_Target_Offset = 10; */ + Evap_Target_Offset = 10; + } + break; + + case IN_PROT_LEVEL_1: + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + rtDW.dbg_Logic_Ac_model.Logic_Ac_Comp_Protection_Level = 1U; + Comp_Max_RPM_Allowed = 140U; + Evap_Target_Offset = 10; + + /* : sf_internal_predicateOutput = HVC_CompInputC_Val < 155 && HVC_CompInvTemp_Val < 1090; */ + if ((rtDW.eComp_InputC < 39680) && (rtDW.eComp_Temp < 1090)) { + rtDW.is_COMP_PROTECTION = IN_PROT_LEVEL_0; + + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + /* : Logic_Ac_Comp_Protection_Level = 0; */ + rtDW.dbg_Logic_Ac_model.Logic_Ac_Comp_Protection_Level = 0U; + + /* : Comp_Max_RPM_Allowed = 170; */ + Comp_Max_RPM_Allowed = 170U; + + /* : Evap_Target_Offset = 0; */ + Evap_Target_Offset = 0; + + /* : sf_internal_predicateOutput = HVC_CompInputC_Val >= 180 || HVC_CompInvTemp_Val >= 1200; */ + } else if ((rtDW.eComp_InputC >= 46080) || (rtDW.eComp_Temp >= 1200)) { + rtDW.is_COMP_PROTECTION = IN_PROT_LEVEL_2; + + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + /* : Logic_Ac_Comp_Protection_Level = 2; */ + rtDW.dbg_Logic_Ac_model.Logic_Ac_Comp_Protection_Level = 2U; + + /* : Comp_Max_RPM_Allowed = 120; */ + Comp_Max_RPM_Allowed = 120U; + + /* : Evap_Target_Offset = 20; */ + Evap_Target_Offset = 20; + } + break; + + default: + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + /* case IN_PROT_LEVEL_2: */ + rtDW.dbg_Logic_Ac_model.Logic_Ac_Comp_Protection_Level = 2U; + Comp_Max_RPM_Allowed = 120U; + Evap_Target_Offset = 20; + + /* : sf_internal_predicateOutput = HVC_CompInputC_Val < 175 && HVC_CompInvTemp_Val < 1190; */ + if ((rtDW.eComp_InputC < 44800) && (rtDW.eComp_Temp < 1190)) { + rtDW.is_COMP_PROTECTION = IN_PROT_LEVEL_1; + + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + /* : Logic_Ac_Comp_Protection_Level = 1; */ + rtDW.dbg_Logic_Ac_model.Logic_Ac_Comp_Protection_Level = 1U; + + /* : Comp_Max_RPM_Allowed = 140; */ + Comp_Max_RPM_Allowed = 140U; + + /* : Evap_Target_Offset = 10; */ + Evap_Target_Offset = 10; + } + break; + } + } + + /* End of Chart: '/A//C Control' */ + + /* DataTypeConversion: '/Data Type Conversion6' incorporates: + * DataStoreWrite: '/Data Store Write11' + */ + EN_BATTChiller = rtB.Chiller_eTXV; + + /* MATLAB Function: '/MATLAB Function1' incorporates: + * DataStoreRead: '/Data Store Read' + * MATLAB Function: '/external fan' + */ + /* : if isempty(t_start) */ + if (!rtDW.t_start_not_empty) { + /* : t_start = t_now; */ + rtDW.t_start = rtDW.t_now; + rtDW.t_start_not_empty = true; + + /* : is_running = uint8(0); */ + } + + /* : if Enable_Comp_PID == 0 */ + rtb_err = !Enable_Comp_PID; + if (rtb_err) { + /* : t_start = t_now; */ + rtDW.t_start = rtDW.t_now; + + /* : is_running = uint8(0); */ + rtDW.is_running = 0U; + + /* : timer_out = uint8(0); */ + rtb_timer_out = 0U; + } else { + /* : else */ + /* : if is_running == 0 */ + if (rtDW.is_running == 0) { + /* : t_start = t_now; */ + rtDW.t_start = rtDW.t_now; + + /* : is_running = uint8(1); */ + rtDW.is_running = 1U; + } + + /* : if (t_now - t_start) >= 60000.0 */ + rtb_Subtract = rtDW.t_now - /*MW:OvSatOk*/ rtDW.t_start; + if (rtb_Subtract > rtDW.t_now) { + rtb_Subtract = 0U; + } + + if (rtb_Subtract >= 60000U) { + /* : timer_out = uint8(1); */ + rtb_timer_out = 1U; + } else { + /* : else */ + /* : timer_out = uint8(0); */ + rtb_timer_out = 0U; + } + } + + /* End of MATLAB Function: '/MATLAB Function1' */ + + /* Switch: '/Switch2' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read32' + * Gain: '/Gain2' + * RelationalOperator: '/Compare' + */ + if (rtDW.Engine_speed > 500.0) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant1' + */ + if (rtb_timer_out <= 0) { + Comp_Max_RPM_Allowed = 120U; + } + + /* End of Switch: '/Switch' */ + } else { + /* Gain: '/Gain2' incorporates: + * Constant: '/Constant4' + */ + rtb_Subtract = 41943U * g_usCMP_MAX_ENG_OFF; + Comp_Max_RPM_Allowed = (uint8_t)((uint32_t)((rtb_Subtract & 1048576U) != 0U) + + (rtb_Subtract >> 21)); + } + + /* End of Switch: '/Switch2' */ + + /* Sum: '/Sum' incorporates: + * DataStoreWrite: '/Data Store Write14' + */ + Eva_Target = (int16_t)(rtB.Comp_Target_Temp + Evap_Target_Offset); + + /* Sum: '/Sum' incorporates: + * DataStoreWrite: '/Data Store Write14' + */ + rtb_y_he = (int16_t)(rtB.Comp_Feedback_Temp - Eva_Target); + + /* DeadZone: '/Dead Zone' */ + if (rtb_y_he > g_assPID_COMPRESSOR[4]) { + i = rtb_y_he - g_assPID_COMPRESSOR[4]; + if (i > 32767) { + i = 32767; + } else if (i < -32768) { + i = -32768; + } + + Evap_Target_Offset = (int16_t)i; + } else if (rtb_y_he >= (int16_t)-g_assPID_COMPRESSOR[4]) { + Evap_Target_Offset = 0; + } else { + i = rtb_y_he - (int16_t)-g_assPID_COMPRESSOR[4]; + if (i > 32767) { + i = 32767; + } else if (i < -32768) { + i = -32768; + } + + Evap_Target_Offset = (int16_t)i; + } + + /* End of DeadZone: '/Dead Zone' */ + + /* Gain: '/Gain1' */ + rtb_Gain1_f = (int32_t)(10000U * Comp_Max_RPM_Allowed); + + /* Sum: '/Sum' incorporates: + * Constant: '/Constant7' + * Memory: '/Memory1' + * Product: '/Divide4' + */ + tmp_3 = (int64_t)floor((double)g_assPID_COMPRESSOR[1] / 100.0 * (double) + Evap_Target_Offset) + rtDW.MemComp_I_Value; + if (tmp_3 > 2147483647LL) { + tmp_3 = 2147483647LL; + } else if (tmp_3 < -2147483648LL) { + tmp_3 = -2147483648LL; + } + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + * Sum: '/Sum' + */ + if ((int32_t)tmp_3 <= rtb_Gain1_f) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant3' + * RelationalOperator: '/UpperRelop' + */ + if ((int32_t)tmp_3 < 0) { + rtb_Gain1_f = 0; + } else { + rtb_Gain1_f = (int32_t)tmp_3; + } + + /* End of Switch: '/Switch' */ + } + + /* End of Switch: '/Switch2' */ + + /* Switch: '/Switch' incorporates: + * Constant: '/Constant12' + */ + if (Enable_Comp_PID) { + /* Sum: '/Sum2' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * Constant: '/Constant2' + * Constant: '/Constant6' + * Constant: '/Constant8' + * Memory: '/pError' + * Product: '/Divide1' + * Product: '/Divide2' + * Product: '/Divide3' + * Product: '/Divide5' + * Product: '/Divide6' + * Sum: '/Sum1' + * + * Block description for '/Divide1': + * Round + * + * Block description for '/Divide3': + * Round + * + * Block description for '/Divide6': + * Round + */ + i = ((int16_t)div_nzp_s32_round((int16_t)(Evap_Target_Offset * + g_assPID_COMPRESSOR[0]), 10) + (int16_t)div_nzp_s32_round(rtb_Gain1_f, + 10000)) + (int16_t)div_nzp_s32_round((int16_t)(Evap_Target_Offset - + rtDW.pError_PreviousInput) * g_assPID_COMPRESSOR[2], 100); + if (i < 0) { + i = 0; + } else if (i > 255) { + i = 255; + } + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + * RelationalOperator: '/UpperRelop' + * Sum: '/Sum2' + * Switch: '/Switch' + */ + if (i > Comp_Max_RPM_Allowed) { + rtb_DataTypeConversion3_gz = Comp_Max_RPM_Allowed; + } else if (i < 16) { + /* Switch: '/Switch' */ + rtb_DataTypeConversion3_gz = 16U; + } else { + rtb_DataTypeConversion3_gz = (uint8_t)i; + } + + /* End of Switch: '/Switch2' */ + } else { + rtb_DataTypeConversion3_gz = 0U; + } + + /* End of Switch: '/Switch' */ + + /* RateLimiter: '/Rate Limiter' incorporates: + * DataTypeConversion: '/Data Type Conversion1' + */ + rtb_Add_be = (double)rtb_DataTypeConversion3_gz - rtDW.PrevY; + if (rtb_Add_be > 5.0) { + rtb_Add_p4 = rtDW.PrevY + 5.0; + } else if (rtb_Add_be < -5.0) { + rtb_Add_p4 = rtDW.PrevY - 5.0; + } else { + rtb_Add_p4 = rtb_DataTypeConversion3_gz; + } + + rtDW.PrevY = rtb_Add_p4; + + /* End of RateLimiter: '/Rate Limiter' */ + + /* Switch: '/Switch1' incorporates: + * Constant: '/Constant' + */ + if (rtB.Chiller_Only_Flag > 0.0) { + rtb_Add_p4 = g_ucAC_EXTRA_RPM; + } + + /* End of Switch: '/Switch1' */ + + /* Gain: '/Gain1' incorporates: + * Constant: '/Constant2' + */ + for (i = 0; i < 6; i++) { + rtb_Gain1_o3[i] = (uint16_t)((41943U * g_ausCMP_RPM_RESONANCE[i]) >> 21); + } + + /* End of Gain: '/Gain1' */ + + /* MATLAB Function: '/MATLAB Function' */ + /* : rpm_phys = double(rpm_in); */ + /* : low1 = double(res_cal(1)); */ + /* : high1 = double(res_cal(2)); */ + /* : low2 = double(res_cal(3)); */ + /* : high2 = double(res_cal(4)); */ + /* : low3 = double(res_cal(5)); */ + /* : high3 = double(res_cal(6)); */ + /* : if (rpm_phys >= low1) && (rpm_phys <= high1) */ + if ((rtb_Add_p4 >= rtb_Gain1_o3[0]) && (rtb_Add_p4 <= rtb_Gain1_o3[1])) { + /* : if (rpm_phys - low1) < (high1 - rpm_phys) */ + if (rtb_Add_p4 - (double)rtb_Gain1_o3[0] < (double)rtb_Gain1_o3[1] - + rtb_Add_p4) { + /* : rpm_phys = low1; */ + rtb_Add_p4 = rtb_Gain1_o3[0]; + } else { + /* : else */ + /* : rpm_phys = high1; */ + rtb_Add_p4 = rtb_Gain1_o3[1]; + } + } + + /* : if (rpm_phys >= low2) && (rpm_phys <= high2) */ + if ((rtb_Add_p4 >= rtb_Gain1_o3[2]) && (rtb_Add_p4 <= rtb_Gain1_o3[3])) { + /* : if (rpm_phys - low2) < (high2 - rpm_phys) */ + if (rtb_Add_p4 - (double)rtb_Gain1_o3[2] < (double)rtb_Gain1_o3[3] - + rtb_Add_p4) { + /* : rpm_phys = low2; */ + rtb_Add_p4 = rtb_Gain1_o3[2]; + } else { + /* : else */ + /* : rpm_phys = high2; */ + rtb_Add_p4 = rtb_Gain1_o3[3]; + } + } + + /* : if (rpm_phys >= low3) && (rpm_phys <= high3) */ + if ((rtb_Add_p4 >= rtb_Gain1_o3[4]) && (rtb_Add_p4 <= rtb_Gain1_o3[5])) { + /* : if (rpm_phys - low3) < (high3 - rpm_phys) */ + if (rtb_Add_p4 - (double)rtb_Gain1_o3[4] < (double)rtb_Gain1_o3[5] - + rtb_Add_p4) { + /* : rpm_phys = low3; */ + rtb_Add_p4 = rtb_Gain1_o3[4]; + } else { + /* : else */ + /* : rpm_phys = high3; */ + rtb_Add_p4 = rtb_Gain1_o3[5]; + } + } + + /* : rpm_can = uint8(rpm_phys); */ + rtb_Add_be = rt_roundd(rtb_Add_p4); + if (rtb_Add_be < 256.0) { + if (rtb_Add_be >= 0.0) { + El_window_heating = (uint8_t)rtb_Add_be; + } else { + El_window_heating = 0U; + } + } else { + El_window_heating = UINT8_MAX; + } + + /* MATLAB Function: '/external fan' incorporates: + * Constant: '/Constant1' + * Constant: '/Constant6' + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read31' + * DataStoreRead: '/Data Store Read32' + * DataStoreRead: '/Data Store Read81' + * DataStoreWrite: '/Data Store Write25' + * Lookup_n-D: '/Fan_Speed_By_Pressure' + * RelationalOperator: '/Compare' + */ + /* : fan_speed_out = uint8(0); */ + fan_speed_out = 0U; + + /* : comp_emergency_stop = false; */ + eComp_stop = false; + + /* : if (comp_state ~= 1) */ + if (!rtb_err) { + /* : if pressure_failed */ + if (rtDW.CCU_PressSenErr_Stat != 0) { + /* : fan_speed_out = uint8(100); */ + fan_speed_out = 100U; + + /* : comp_emergency_stop = true; */ + eComp_stop = true; + + /* : if pressure_val <= g_assPRESSURE_TO_FAN_X */ + } else if (rtDW.Pressure > g_assPRESSURE_TO_FAN_X[0]) { + /* : fan_speed_out = uint8(fan_speed_table); */ + rtb_FLU_tg_correct_aa = look1_is16lu64n32tu8Ds16Is16_binlcs(rtDW.Pressure, + &g_assPRESSURE_TO_FAN_X[0], &g_aucPRESSURE_TO_FAN_Y[0], 6U); + if (rtb_FLU_tg_correct_aa < 0) { + rtb_FLU_tg_correct_aa = 0; + } else if (rtb_FLU_tg_correct_aa > 255) { + rtb_FLU_tg_correct_aa = 255; + } + + fan_speed_out = (uint8_t)rtb_FLU_tg_correct_aa; + + /* : if engine_on == false */ + if ((rtDW.Engine_speed <= 500.0) && (rtb_FLU_tg_correct_aa > + g_ucFAN_MAX_ENG_OFF)) { + /* : if(fan_speed_out>g_ucFAN_MAX_ENG_OFF) */ + /* : fan_speed_out = uint8(g_ucFAN_MAX_ENG_OFF); */ + fan_speed_out = g_ucFAN_MAX_ENG_OFF; + } + } else { + /* : fan_speed_out = uint8(0); */ + } + } + + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * DataStoreWrite: '/Data Store Write8' + */ + ShutOffFront_EN = rtB.FRONT_eTXV; + + /* DataTypeConversion: '/Data Type Conversion4' incorporates: + * DataStoreWrite: '/Data Store Write9' + */ + ShutOffRear_EN = rtB.REAR_eTXV; + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read12' + */ + rtb_Compare_i5 = (rtDW.CAN_LoHi_Front == 11); + + /* Chart: '/13,1,3,15 Valve control' incorporates: + * DataStoreRead: '/Data Store Read15' + * DataStoreRead: '/Data Store Read34' + * DataStoreRead: '/Data Store Read36' + */ + if (rtDW.is_active_c775_HVAC_model == 0U) { + rtDW.is_active_c775_HVAC_model = 1U; + rtDW.is_ThreeWay_Logic = IN_Wait_3W; + + /* : Cmd_3Way = 2; */ + rtb_Cmd_3Way = 2U; + + /* : Cmd_FrontTemp = -1; */ + /* : Cmd_RearTemp_3W = -1; */ + rtDW.Cmd_RearTemp_3W = -1.0; + rtDW.is_TwoWay_Logic = IN_Wait_2W; + + /* : Cmd_2Way = 1; */ + rtB.Cmd_2Way = 1U; + + /* : Cmd_RearTemp_2W = -1; */ + rtDW.Cmd_RearTemp_2W = -1.0; + } else { + if (rtDW.is_ThreeWay_Logic == IN_Entry_3W) { + rtb_Cmd_3Way = 1U; + + /* : sf_internal_predicateOutput = D_tg_RR > g_assTHREEWAY_DUCT_TGT_R(1) && LO_MODE_FULL == false && ECT>g_ssTHREEWAY_WATER; */ + if ((rtDW.Duct_RR_Tg > g_assTHREEWAY_DUCT_TGT_R[0]) && ((!rtb_Compare_i5) && + (rtDW.ECT > g_ssTHREEWAY_WATER))) { + rtDW.is_ThreeWay_Logic = IN_Wait_3W; + + /* : Cmd_3Way = 2; */ + rtb_Cmd_3Way = 2U; + + /* : Cmd_FrontTemp = -1; */ + /* : Cmd_RearTemp_3W = -1; */ + rtDW.Cmd_RearTemp_3W = -1.0; + } + } else { + /* case IN_Wait_3W: */ + rtb_Cmd_3Way = 2U; + + /* : sf_internal_predicateOutput = D_tg_RR <= g_assTHREEWAY_DUCT_TGT_R(2) || LO_MODE_FULL == true || ECT<=g_ssTHREEWAY_WATER; */ + if ((rtDW.Duct_RR_Tg <= g_assTHREEWAY_DUCT_TGT_R[1]) || (rtb_Compare_i5 || + (rtDW.ECT <= g_ssTHREEWAY_WATER))) { + rtDW.is_ThreeWay_Logic = IN_Entry_3W; + + /* : Cmd_3Way = 1; */ + rtb_Cmd_3Way = 1U; + + /* : t_start_1 = t_now; */ + } + } + + if (rtDW.is_TwoWay_Logic == IN_Entry_2W) { + /* : sf_internal_predicateOutput = D_tg_RR > g_assTWOWAY_REAR_DUCTTGT_R(1); */ + if (rtDW.Duct_RR_Tg > g_assTWOWAY_REAR_DUCTTGT_R[0]) { + /* : Cmd_RearTemp_2W = -1; */ + rtDW.is_TwoWay_Logic = IN_Wait_2W; + + /* : Cmd_2Way = 1; */ + rtB.Cmd_2Way = 1U; + + /* : Cmd_RearTemp_2W = -1; */ + rtDW.Cmd_RearTemp_2W = -1.0; + } + + /* case IN_Wait_2W: */ + /* : sf_internal_predicateOutput = D_tg_RR <= g_assTWOWAY_REAR_DUCTTGT_R(2); */ + } else if (rtDW.Duct_RR_Tg <= g_assTWOWAY_REAR_DUCTTGT_R[1]) { + rtDW.is_TwoWay_Logic = IN_Entry_2W; + + /* : Cmd_2Way = 0; */ + rtB.Cmd_2Way = 0U; + + /* : t_start_3 = t_now; */ + /* : if RL_Seat_Occupied == 0 */ + if (rtDW.SeatOccupiedRL == 0) { + /* : Cmd_RearTemp_2W = 10; */ + rtDW.Cmd_RearTemp_2W = 10.0; + } else { + /* : else */ + /* : Cmd_RearTemp_2W = 10; */ + rtDW.Cmd_RearTemp_2W = 10.0; + } + } else { + /* : Cmd_2Way = 1; */ + rtB.Cmd_2Way = 1U; + + /* : Cmd_RearTemp_2W = -1; */ + rtDW.Cmd_RearTemp_2W = -1.0; + } + + /* : if Cmd_RearTemp_3W == 0 || Cmd_RearTemp_2W == 0 */ + } + + /* End of Chart: '/13,1,3,15 Valve control' */ + + /* Switch: '/Switch5' incorporates: + * Constant: '/Constant2' + * Constant: '/Constant1' + * Constant: '/Constant2' + * Constant: '/Constant3' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read74' + * DataStoreWrite: '/Data Store Write1' + * Logic: '/AND' + * RelationalOperator: '/Relational Operator1' + * RelationalOperator: '/Relational Operator2' + * RelationalOperator: '/Relational Operator3' + */ + if ((rtDW.condition_ac_max == 1.0) && (rtDW.SeatOccupiedRL == 0) && + (rtDW.SeatOccupiedRL == 0)) { + rtb_Cmd_3Way = 1U; + } + + /* End of Switch: '/Switch5' */ + + /* Saturate: '/Saturation4' incorporates: + * DataStoreRead: '/Data Store Read28' + */ + if (rtDW.LEVEL <= 5) { + rtb_timer_out = rtDW.LEVEL; + } else { + rtb_timer_out = 5U; + } + + /* End of Saturate: '/Saturation4' */ + + /* Saturate: '/Saturation' incorporates: + * DataStoreRead: '/Data Store Read16' + */ + if (rtDW.CCU_SET_FL > 290) { + Gain = 290U; + } else if (rtDW.CCU_SET_FL < 170) { + Gain = 170U; + } else { + Gain = rtDW.CCU_SET_FL; + } + + /* End of Saturate: '/Saturation' */ + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * Constant: '/Constant2' + * Constant: '/Constant3' + * Constant: '/Constant4' + * Constant: '/Constant5' + */ + switch (rtb_timer_out) { + case 0: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MAX_LV0[i]; + } + break; + + case 1: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MAX_LV1[i]; + } + break; + + case 2: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MAX_LV2[i]; + } + break; + + case 3: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MAX_LV3[i]; + } + break; + + case 4: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MAX_LV4[i]; + } + break; + + default: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MAX_LV5[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* Gain: '/Gain' incorporates: + * Gain: '/Gain' + * Gain: '/Gain' + * Gain: '/Gain' + * Gain: '/Gain' + * Gain: '/Gain2' + * Switch: '/Switch15' + * Switch: '/Switch15' + * Switch: '/Switch15' + * Switch: '/Switch15' + */ + rtb_Subtract = 52429U * Gain; + + /* DataTypeConversion: '/Data Type Conversion2' incorporates: + * Gain: '/Gain' + * Gain: '/Gain2' + */ + rtb_dt_nx = rtb_Subtract >> 19; + + /* Gain: '/Gain1' incorporates: + * Bias: '/Bias' + * DataTypeConversion: '/Data Type Conversion2' + * Gain: '/Gain3' + */ + i = ((int32_t)rtb_dt_nx + -15) << 14; + + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * DataTypeConversion: '/Data Type Conversion3' + * Gain: '/Gain1' + */ + rtb_DataTypeConversion3_i = (uint8_t)((((uint32_t)i & 16384U) != 0U) + (i >> + 15)); + + /* Selector: '/Selector' incorporates: + * DataTypeConversion: '/Data Type Conversion1' + */ + rtb_y_he = rtb_uDLookupTable7_g[rtb_DataTypeConversion3_i - 1]; + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table' + * Lookup_n-D: '/1-D Lookup Table1' + * Lookup_n-D: '/1-D Lookup Table2' + * Lookup_n-D: '/1-D Lookup Table3' + * Lookup_n-D: '/1-D Lookup Table4' + * Lookup_n-D: '/1-D Lookup Table5' + * Saturate: '/Saturation' + */ + switch (rtb_timer_out) { + case 0: + rtb_MultiportSwitch_gp = look1_iu16lu64n48ts16Ds32_binlcs(Gain, + rtConstP.pooled79, &g_assTG_FLU_LV0[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table' + * Lookup_n-D: '/1-D Lookup Table' + * Saturate: '/Saturation' + */ + rtb_MultiportSwitch_j2 = look1_iu16bs16lu64n32ts16Ds32_binlcs(Gain, + rtConstP.pooled51, &g_assINCAR_TG_FL_LV0[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant' + */ + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_INC_Y1_LV0[i]; + } + break; + + case 1: + rtb_MultiportSwitch_gp = look1_iu16lu64n48ts16Ds32_binlcs(Gain, + rtConstP.pooled79, &g_assTG_FLU_LV1[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table1' + * Lookup_n-D: '/1-D Lookup Table1' + * Saturate: '/Saturation' + */ + rtb_MultiportSwitch_j2 = look1_iu16bs16lu64n32ts16Ds32_binlcs(Gain, + rtConstP.pooled51, &g_assINCAR_TG_FL_LV1[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant1' + */ + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_INC_Y1_LV1[i]; + } + break; + + case 2: + rtb_MultiportSwitch_gp = look1_iu16lu64n48ts16Ds32_binlcs(Gain, + rtConstP.pooled79, &g_assTG_FLU_LV2[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table2' + * Lookup_n-D: '/1-D Lookup Table2' + * Saturate: '/Saturation' + */ + rtb_MultiportSwitch_j2 = look1_iu16bs16lu64n32ts16Ds32_binlcs(Gain, + rtConstP.pooled51, &g_assINCAR_TG_FL_LV2[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant2' + */ + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_INC_Y1_LV2[i]; + } + break; + + case 3: + rtb_MultiportSwitch_gp = look1_iu16lu64n48ts16Ds32_binlcs(Gain, + rtConstP.pooled79, &g_assTG_FLU_LV3[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table3' + * Lookup_n-D: '/1-D Lookup Table3' + * Saturate: '/Saturation' + */ + rtb_MultiportSwitch_j2 = look1_iu16bs16lu64n32ts16Ds32_binlcs(Gain, + rtConstP.pooled51, &g_assINCAR_TG_FL_LV3[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant3' + */ + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_INC_Y1_LV3[i]; + } + break; + + case 4: + rtb_MultiportSwitch_gp = look1_iu16lu64n48ts16Ds32_binlcs(Gain, + rtConstP.pooled79, &g_assTG_FLU_LV4[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table4' + * Lookup_n-D: '/1-D Lookup Table4' + * Saturate: '/Saturation' + */ + rtb_MultiportSwitch_j2 = look1_iu16bs16lu64n32ts16Ds32_binlcs(Gain, + rtConstP.pooled51, &g_assINCAR_TG_FL_LV4[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant4' + */ + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_INC_Y1_LV4[i]; + } + break; + + default: + rtb_MultiportSwitch_gp = look1_iu16lu64n48ts16Ds32_binlcs(Gain, + rtConstP.pooled79, &g_assTG_FLU_LV5[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table5' + * Lookup_n-D: '/1-D Lookup Table5' + * Saturate: '/Saturation' + */ + rtb_MultiportSwitch_j2 = look1_iu16bs16lu64n32ts16Ds32_binlcs(Gain, + rtConstP.pooled51, &g_assINCAR_TG_FL_LV5[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant5' + */ + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_INC_Y1_LV5[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch' */ + + /* Selector: '/Selector' incorporates: + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[0] = rtb_uDLookupTable7_g[rtb_DataTypeConversion3_i - + 1]; + + /* MultiPortSwitch: '/Multiport Switch2' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[1] = + g_assDTG_FU_INC_Y2_LV0[rtb_DataTypeConversion3_i - 1]; + break; + + case 1: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[1] = + g_assDTG_FU_INC_Y2_LV1[rtb_DataTypeConversion3_i - 1]; + break; + + case 2: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[1] = + g_assDTG_FU_INC_Y2_LV2[rtb_DataTypeConversion3_i - 1]; + break; + + case 3: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[1] = + g_assDTG_FU_INC_Y2_LV3[rtb_DataTypeConversion3_i - 1]; + break; + + case 4: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[1] = + g_assDTG_FU_INC_Y2_LV4[rtb_DataTypeConversion3_i - 1]; + break; + + default: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[1] = + g_assDTG_FU_INC_Y2_LV5[rtb_DataTypeConversion3_i - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch2' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_kz[2] = 0; + + /* MultiPortSwitch: '/Multiport Switch3' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant14' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[3] = + g_assDTG_FU_INC_Y3_LV0[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant20' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[4] = + g_assDTG_FU_INC_Y4_LV0[rtb_DataTypeConversion3_i - 1]; + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant' + */ + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_INC_X1_LV0[i]; + } + break; + + case 1: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant15' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[3] = + g_assDTG_FU_INC_Y3_LV1[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant21' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[4] = + g_assDTG_FU_INC_Y4_LV1[rtb_DataTypeConversion3_i - 1]; + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant1' + */ + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_INC_X1_LV1[i]; + } + break; + + case 2: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant16' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[3] = + g_assDTG_FU_INC_Y3_LV2[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant22' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[4] = + g_assDTG_FU_INC_Y4_LV2[rtb_DataTypeConversion3_i - 1]; + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant2' + */ + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_INC_X1_LV2[i]; + } + break; + + case 3: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant17' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[3] = + g_assDTG_FU_INC_Y3_LV3[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant23' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[4] = + g_assDTG_FU_INC_Y4_LV3[rtb_DataTypeConversion3_i - 1]; + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant3' + */ + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_INC_X1_LV3[i]; + } + break; + + case 4: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant12' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[3] = + g_assDTG_FU_INC_Y3_LV4[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant18' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[4] = + g_assDTG_FU_INC_Y4_LV4[rtb_DataTypeConversion3_i - 1]; + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant4' + */ + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_INC_X1_LV4[i]; + } + break; + + default: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant13' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[3] = + g_assDTG_FU_INC_Y3_LV5[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant19' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[4] = + g_assDTG_FU_INC_Y4_LV5[rtb_DataTypeConversion3_i - 1]; + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant5' + */ + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_INC_X1_LV5[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch3' */ + + /* Selector: '/Selector' incorporates: + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[0] = rtb_uDLookupTable7_g[rtb_DataTypeConversion3_i - + 1]; + + /* MultiPortSwitch: '/Multiport Switch2' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[1] = + g_assDTG_FU_INC_X2_LV0[rtb_DataTypeConversion3_i - 1]; + break; + + case 1: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[1] = + g_assDTG_FU_INC_X2_LV1[rtb_DataTypeConversion3_i - 1]; + break; + + case 2: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[1] = + g_assDTG_FU_INC_X2_LV2[rtb_DataTypeConversion3_i - 1]; + break; + + case 3: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[1] = + g_assDTG_FU_INC_X2_LV3[rtb_DataTypeConversion3_i - 1]; + break; + + case 4: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[1] = + g_assDTG_FU_INC_X2_LV4[rtb_DataTypeConversion3_i - 1]; + break; + + default: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[1] = + g_assDTG_FU_INC_X2_LV5[rtb_DataTypeConversion3_i - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch2' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_by[2] = 0; + + /* MultiPortSwitch: '/Multiport Switch3' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant14' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[3] = + g_assDTG_FU_INC_X3_LV0[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant20' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[4] = + g_assDTG_FU_INC_X4_LV0[rtb_DataTypeConversion3_i - 1]; + break; + + case 1: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant15' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[3] = + g_assDTG_FU_INC_X3_LV1[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant21' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[4] = + g_assDTG_FU_INC_X4_LV1[rtb_DataTypeConversion3_i - 1]; + break; + + case 2: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant16' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[3] = + g_assDTG_FU_INC_X3_LV2[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant22' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[4] = + g_assDTG_FU_INC_X4_LV2[rtb_DataTypeConversion3_i - 1]; + break; + + case 3: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant17' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[3] = + g_assDTG_FU_INC_X3_LV3[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant23' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[4] = + g_assDTG_FU_INC_X4_LV3[rtb_DataTypeConversion3_i - 1]; + break; + + case 4: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant12' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[3] = + g_assDTG_FU_INC_X3_LV4[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant18' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[4] = + g_assDTG_FU_INC_X4_LV4[rtb_DataTypeConversion3_i - 1]; + break; + + default: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant13' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[3] = + g_assDTG_FU_INC_X3_LV5[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant19' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[4] = + g_assDTG_FU_INC_X4_LV5[rtb_DataTypeConversion3_i - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch3' */ + + /* Lookup_n-D: '/2.5 FLU_tg_incar' incorporates: + * DataStoreRead: '/Data Store Read21' + * Sum: '/2.5. X = Inc_Tg - Incar_fb' + */ + rtb_u5FLU_tg_incar_b = look1_is16lu64n32Ds32_binlcn((int16_t) + (rtb_MultiportSwitch_j2 - rtDW.Incar_FL), rtb_VectorConcatenate_by, + rtb_VectorConcatenate_kz, 4U); + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * Constant: '/Constant2' + * Constant: '/Constant3' + * Constant: '/Constant4' + * Constant: '/Constant5' + */ + switch (rtb_timer_out) { + case 0: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_AMB_Y1_LV0[i]; + } + break; + + case 1: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_AMB_Y1_LV1[i]; + } + break; + + case 2: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_AMB_Y1_LV2[i]; + } + break; + + case 3: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_AMB_Y1_LV3[i]; + } + break; + + case 4: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_AMB_Y1_LV4[i]; + } + break; + + default: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_AMB_Y1_LV5[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* Selector: '/Selector' incorporates: + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[0] = rtb_uDLookupTable7_g[rtb_DataTypeConversion3_i - + 1]; + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_pg[1] = 0; + + /* MultiPortSwitch: '/Multiport Switch2' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[2] = + g_assDTG_FU_AMB_Y2_LV0[rtb_DataTypeConversion3_i - 1]; + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant' + */ + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_AMB_X1_LV0[i]; + } + break; + + case 1: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[2] = + g_assDTG_FU_AMB_Y2_LV1[rtb_DataTypeConversion3_i - 1]; + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant1' + */ + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_AMB_X1_LV1[i]; + } + break; + + case 2: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[2] = + g_assDTG_FU_AMB_Y2_LV2[rtb_DataTypeConversion3_i - 1]; + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant2' + */ + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_AMB_X1_LV2[i]; + } + break; + + case 3: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[2] = + g_assDTG_FU_AMB_Y2_LV3[rtb_DataTypeConversion3_i - 1]; + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant3' + */ + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_AMB_X1_LV3[i]; + } + break; + + case 4: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[2] = + g_assDTG_FU_AMB_Y2_LV4[rtb_DataTypeConversion3_i - 1]; + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant4' + */ + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_AMB_X1_LV4[i]; + } + break; + + default: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[2] = + g_assDTG_FU_AMB_Y2_LV5[rtb_DataTypeConversion3_i - 1]; + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant5' + */ + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_AMB_X1_LV5[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch2' */ + + /* Selector: '/Selector' incorporates: + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[0] = rtb_uDLookupTable7_g[rtb_DataTypeConversion3_i - + 1]; + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_dw[1] = 0; + + /* MultiPortSwitch: '/Multiport Switch2' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[2] = + g_assDTG_FU_AMB_X2_LV0[rtb_DataTypeConversion3_i - 1]; + break; + + case 1: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[2] = + g_assDTG_FU_AMB_X2_LV1[rtb_DataTypeConversion3_i - 1]; + break; + + case 2: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[2] = + g_assDTG_FU_AMB_X2_LV2[rtb_DataTypeConversion3_i - 1]; + break; + + case 3: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[2] = + g_assDTG_FU_AMB_X2_LV3[rtb_DataTypeConversion3_i - 1]; + break; + + case 4: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[2] = + g_assDTG_FU_AMB_X2_LV4[rtb_DataTypeConversion3_i - 1]; + break; + + default: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[2] = + g_assDTG_FU_AMB_X2_LV5[rtb_DataTypeConversion3_i - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch2' */ + + /* Sum: '/2.6. X = Amb_Tg - Amb_Fb' incorporates: + * Bias: '/Bias' + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read20' + * Selector: '/Selector1' + * Sum: '/2.6. X = Amb_Tg - Amb_Fb' + * Sum: '/2.6. X = Amb_Tg - Amb_Fb' + * Sum: '/2.6. X = Amb_Tg - Amb_Fb' + * Sum: '/2.6. X = Amb_Tg - Amb_Fb' + * Sum: '/2.6. X = Amb_Tg - Amb_Fb' + */ + rtb_Bias5 = (int16_t)(g_assAMB_LV_TG[rtb_timer_out] - rtDW.AMB); + + /* Lookup_n-D: '/2.6 FLU_tg_amb' incorporates: + * Sum: '/2.6. X = Amb_Tg - Amb_Fb' + */ + rtb_u6FLU_tg_amb_h = look1_is16lu64n32Ds32_binlcn(rtb_Bias5, + rtb_VectorConcatenate_dw, rtb_VectorConcatenate_pg, 2U); + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_gn[0] = 0; + + /* MultiPortSwitch: '/Multiport Switch1' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[1] = + g_assDTG_FU_SUN_Y1_LV0[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = + g_assDTG_FU_SUN_Y2_LV0[rtb_DataTypeConversion3_i - 1]; + break; + + case 1: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[1] = + g_assDTG_FU_SUN_Y1_LV1[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = + g_assDTG_FU_SUN_Y2_LV1[rtb_DataTypeConversion3_i - 1]; + break; + + case 2: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[1] = + g_assDTG_FU_SUN_Y1_LV2[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = + g_assDTG_FU_SUN_Y2_LV2[rtb_DataTypeConversion3_i - 1]; + break; + + case 3: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[1] = + g_assDTG_FU_SUN_Y1_LV3[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = + g_assDTG_FU_SUN_Y2_LV3[rtb_DataTypeConversion3_i - 1]; + break; + + case 4: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[1] = + g_assDTG_FU_SUN_Y1_LV4[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = + g_assDTG_FU_SUN_Y2_LV4[rtb_DataTypeConversion3_i - 1]; + break; + + default: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[1] = + g_assDTG_FU_SUN_Y1_LV5[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = + g_assDTG_FU_SUN_Y2_LV5[rtb_DataTypeConversion3_i - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_np[0] = 0; + + /* MultiPortSwitch: '/Multiport Switch1' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[1] = + g_assDTG_FU_SUN_X1_LV0[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = + g_assDTG_FU_SUN_X2_LV0[rtb_DataTypeConversion3_i - 1]; + break; + + case 1: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[1] = + g_assDTG_FU_SUN_X1_LV1[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = + g_assDTG_FU_SUN_X2_LV1[rtb_DataTypeConversion3_i - 1]; + break; + + case 2: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[1] = + g_assDTG_FU_SUN_X1_LV2[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = + g_assDTG_FU_SUN_X2_LV2[rtb_DataTypeConversion3_i - 1]; + break; + + case 3: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[1] = + g_assDTG_FU_SUN_X1_LV3[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = + g_assDTG_FU_SUN_X2_LV3[rtb_DataTypeConversion3_i - 1]; + break; + + case 4: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[1] = + g_assDTG_FU_SUN_X1_LV4[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = + g_assDTG_FU_SUN_X2_LV4[rtb_DataTypeConversion3_i - 1]; + break; + + default: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[1] = + g_assDTG_FU_SUN_X1_LV5[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = + g_assDTG_FU_SUN_X2_LV5[rtb_DataTypeConversion3_i - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* Lookup_n-D: '/2.6 FLU_tg_amb' incorporates: + * DataStoreRead: '/Data Store Read26' + */ + rtb_u6FLU_tg_amb_o = look1_bs16ts16Dd_binlc(rtDW.Sun_L, + rtb_VectorConcatenate_np, rtb_VectorConcatenate_gn, 2U); + + /* Sum: '/FLU_tg_correct' */ + rtb_FLU_tg_correct = (int16_t)((int16_t)((int16_t)(rtb_MultiportSwitch_gp + + rtb_u5FLU_tg_incar_b) + rtb_u6FLU_tg_amb_h) + rtb_u6FLU_tg_amb_o); + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + */ + if (rtb_FLU_tg_correct > rtb_y_he) { + rtb_FLU_tg_correct = rtb_y_he; + } else { + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * Constant: '/Constant2' + * Constant: '/Constant3' + * Constant: '/Constant4' + * Constant: '/Constant5' + */ + switch (rtb_timer_out) { + case 0: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MIN_LV0[i]; + } + break; + + case 1: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MIN_LV1[i]; + } + break; + + case 2: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MIN_LV2[i]; + } + break; + + case 3: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MIN_LV3[i]; + } + break; + + case 4: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MIN_LV4[i]; + } + break; + + default: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MIN_LV5[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* Selector: '/Selector' incorporates: + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_FLU_tg_correct_aa = rtb_uDLookupTable7_g[rtb_DataTypeConversion3_i - 1]; + + /* Switch: '/Switch' incorporates: + * RelationalOperator: '/UpperRelop' + * Selector: '/Selector' + */ + if (rtb_FLU_tg_correct < rtb_FLU_tg_correct_aa) { + rtb_FLU_tg_correct = rtb_FLU_tg_correct_aa; + } + + /* End of Switch: '/Switch' */ + } + + /* End of Switch: '/Switch2' */ + + /* Switch: '/Switch2' incorporates: + * Constant: '/Constant12' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read76' + */ + if (rtDW.CCU_AC_MAX > 0) { + i = 5; + } else { + i = rtDW.CCU_AUTOMODE_FL; + } + + /* MATLAB Function: '/func g_assAUTO_STEP_DUCT_TG_U' incorporates: + * DataStoreRead: '/Data Store Read20' + * Switch: '/Switch2' + */ + funcg_assAUTO_STEP_DUCT_TG_U(rtDW.LEVEL, (double)i, &rtb_y_jh); + + /* Switch: '/Switch' incorporates: + * Constant: '/manual' + * DataStoreRead: '/Data Store Read46' + * DataStoreWrite: '/Data Store Write' + * RelationalOperator: '/Equal1' + * Sum: '/Add' + */ + if (rtDW.CCU_MODE_FL != 0) { + rtb_FLU_tg_correct += rtb_y_jh; + } + + /* End of Switch: '/Switch' */ + + /* If: '/If' incorporates: + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read' + * Logic: '/Logical Operator' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + */ + if ((rtDW.step_start_controle_front == 0) || (rtDW.step_start_controle_front == + 1) || (rtDW.step_start_controle_front == 2)) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem' incorporates: + * ActionPort: '/Action Port' + */ + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * DataStoreRead: '/dtg from Start Control' + */ + rtb_Merge_b = (int16_t)rtDW.Dtg_FUL; + + /* End of Outputs for SubSystem: '/If Action Subsystem' */ + } else { + /* Outputs for IfAction SubSystem: '/If Action Subsystem1' incorporates: + * ActionPort: '/Action Port' + */ + /* SignalConversion generated from: '/FXU' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + rtb_Merge_b = rtb_FLU_tg_correct; + + /* End of Outputs for SubSystem: '/If Action Subsystem1' */ + } + + /* End of If: '/If' */ + + /* Switch: '/Switch15' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read44' + * DataStoreWrite: '/Data Store Write2' + */ + if (rtDW.LO_HI_MODE_FL > 1) { + rtb_Merge_b = 600; + } else { + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Gain: '/Gain' + * Gain: '/Gain1' + */ + index_start_0 = (int32_t)floor(((double)((int32_t)rtb_Subtract >> 19) - 15.0) + * 0.5 + 0.5); + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant10' + * Constant: '/Constant11' + * Constant: '/Constant12' + * Constant: '/Constant7' + * Constant: '/Constant8' + * Constant: '/Constant9' + */ + switch (rtb_timer_out) { + case 0: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MAX_LV0[i]; + } + break; + + case 1: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MAX_LV1[i]; + } + break; + + case 2: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MAX_LV2[i]; + } + break; + + case 3: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MAX_LV3[i]; + } + break; + + case 4: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MAX_LV4[i]; + } + break; + + default: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MAX_LV5[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* Selector: '/Selector' incorporates: + * DataTypeConversion: '/Data Type Conversion1' + */ + rtb_FLU_tg_correct_aa = rtb_uDLookupTable7_g[(uint8_t)index_start_0 - 1]; + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + * Selector: '/Selector' + */ + if (rtb_Merge_b > rtb_FLU_tg_correct_aa) { + /* DataStoreWrite: '/Data Store Write2' */ + rtb_Merge_b = rtb_FLU_tg_correct_aa; + } else { + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Constant: '/Constant' + * Constant: '/Constant2' + * Constant: '/Constant3' + * Constant: '/Constant4' + * Constant: '/Constant5' + * Constant: '/Constant6' + */ + switch (rtb_timer_out) { + case 0: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MIN_LV0[i]; + } + break; + + case 1: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MIN_LV1[i]; + } + break; + + case 2: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MIN_LV2[i]; + } + break; + + case 3: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MIN_LV3[i]; + } + break; + + case 4: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MIN_LV4[i]; + } + break; + + default: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MIN_LV5[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch' */ + + /* Selector: '/Selector1' incorporates: + * DataTypeConversion: '/Data Type Conversion1' + */ + rtb_FLU_tg_correct_aa = rtb_uDLookupTable7_g[(uint8_t)index_start_0 - 1]; + + /* Switch: '/Switch' incorporates: + * RelationalOperator: '/UpperRelop' + * Selector: '/Selector1' + */ + if (rtb_Merge_b < rtb_FLU_tg_correct_aa) { + /* DataStoreWrite: '/Data Store Write2' */ + rtb_Merge_b = rtb_FLU_tg_correct_aa; + } + + /* End of Switch: '/Switch' */ + } + + /* End of Switch: '/Switch2' */ + } + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * Constant: '/Constant2' + * Constant: '/Constant3' + * Constant: '/Constant4' + * Constant: '/Constant5' + */ + switch (rtb_timer_out) { + case 0: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MAX_LV0[i]; + } + break; + + case 1: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MAX_LV1[i]; + } + break; + + case 2: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MAX_LV2[i]; + } + break; + + case 3: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MAX_LV3[i]; + } + break; + + case 4: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MAX_LV4[i]; + } + break; + + default: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MAX_LV5[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* Saturate: '/Saturation1' incorporates: + * DataStoreRead: '/Data Store Read17' + */ + if (rtDW.CCU_SET_FR > 290) { + Gain1 = 290U; + } else if (rtDW.CCU_SET_FR < 170) { + Gain1 = 170U; + } else { + Gain1 = rtDW.CCU_SET_FR; + } + + /* End of Saturate: '/Saturation1' */ + + /* Gain: '/Gain' incorporates: + * Gain: '/Gain2' + */ + rtb_Divide4_n_tmp_tmp = 52429U * Gain1; + + /* DataTypeConversion: '/Data Type Conversion3' incorporates: + * Gain: '/Gain' + * Gain: '/Gain2' + */ + rtb_Divide4_n_tmp_tmp_0 = rtb_Divide4_n_tmp_tmp >> 19; + + /* Gain: '/Gain1' incorporates: + * Bias: '/Bias' + * DataTypeConversion: '/Data Type Conversion3' + * Gain: '/Gain3' + */ + i = ((int32_t)rtb_Divide4_n_tmp_tmp_0 + -15) << 14; + + /* DataTypeConversion: '/Data Type Conversion2' incorporates: + * DataTypeConversion: '/Data Type Conversion3' + * Gain: '/Gain1' + */ + CCU_FRONT_SYNC = (uint8_t)((((uint32_t)i & 16384U) != 0U) + (i >> 15)); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table' + * Lookup_n-D: '/1-D Lookup Table1' + * Lookup_n-D: '/1-D Lookup Table2' + * Lookup_n-D: '/1-D Lookup Table3' + * Lookup_n-D: '/1-D Lookup Table4' + * Lookup_n-D: '/1-D Lookup Table5' + * Saturate: '/Saturation1' + */ + switch (rtb_timer_out) { + case 0: + rtb_MultiportSwitch_fu = look1_iu16lu64n48ts16Ds32_binlcs(Gain1, + rtConstP.pooled79, &g_assTG_FRU_LV0[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table' + * Lookup_n-D: '/1-D Lookup Table' + * Saturate: '/Saturation1' + */ + rtb_MultiportSwitch_ev = look1_iu16bs16lu64n32ts16Ds32_binlcs(Gain1, + rtConstP.pooled51, &g_assINCAR_TG_FR_LV0[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch1' + */ + rtb_VectorConcatenate_by[0] = g_assDTG_FU_INC_Y1_LV0[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[1] = g_assDTG_FU_INC_Y2_LV0[CCU_FRONT_SYNC - 1]; + break; + + case 1: + rtb_MultiportSwitch_fu = look1_iu16lu64n48ts16Ds32_binlcs(Gain1, + rtConstP.pooled79, &g_assTG_FRU_LV1[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table1' + * Lookup_n-D: '/1-D Lookup Table1' + * Saturate: '/Saturation1' + */ + rtb_MultiportSwitch_ev = look1_iu16bs16lu64n32ts16Ds32_binlcs(Gain1, + rtConstP.pooled51, &g_assINCAR_TG_FR_LV1[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch1' + */ + rtb_VectorConcatenate_by[0] = g_assDTG_FU_INC_Y1_LV1[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[1] = g_assDTG_FU_INC_Y2_LV1[CCU_FRONT_SYNC - 1]; + break; + + case 2: + rtb_MultiportSwitch_fu = look1_iu16lu64n48ts16Ds32_binlcs(Gain1, + rtConstP.pooled79, &g_assTG_FRU_LV2[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table2' + * Lookup_n-D: '/1-D Lookup Table2' + * Saturate: '/Saturation1' + */ + rtb_MultiportSwitch_ev = look1_iu16bs16lu64n32ts16Ds32_binlcs(Gain1, + rtConstP.pooled51, &g_assINCAR_TG_FR_LV2[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch1' + */ + rtb_VectorConcatenate_by[0] = g_assDTG_FU_INC_Y1_LV2[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[1] = g_assDTG_FU_INC_Y2_LV2[CCU_FRONT_SYNC - 1]; + break; + + case 3: + rtb_MultiportSwitch_fu = look1_iu16lu64n48ts16Ds32_binlcs(Gain1, + rtConstP.pooled79, &g_assTG_FRU_LV3[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table3' + * Lookup_n-D: '/1-D Lookup Table3' + * Saturate: '/Saturation1' + */ + rtb_MultiportSwitch_ev = look1_iu16bs16lu64n32ts16Ds32_binlcs(Gain1, + rtConstP.pooled51, &g_assINCAR_TG_FR_LV3[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch1' + */ + rtb_VectorConcatenate_by[0] = g_assDTG_FU_INC_Y1_LV3[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[1] = g_assDTG_FU_INC_Y2_LV3[CCU_FRONT_SYNC - 1]; + break; + + case 4: + rtb_MultiportSwitch_fu = look1_iu16lu64n48ts16Ds32_binlcs(Gain1, + rtConstP.pooled79, &g_assTG_FRU_LV4[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table4' + * Lookup_n-D: '/1-D Lookup Table4' + * Saturate: '/Saturation1' + */ + rtb_MultiportSwitch_ev = look1_iu16bs16lu64n32ts16Ds32_binlcs(Gain1, + rtConstP.pooled51, &g_assINCAR_TG_FR_LV4[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch1' + */ + rtb_VectorConcatenate_by[0] = g_assDTG_FU_INC_Y1_LV4[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[1] = g_assDTG_FU_INC_Y2_LV4[CCU_FRONT_SYNC - 1]; + break; + + default: + rtb_MultiportSwitch_fu = look1_iu16lu64n48ts16Ds32_binlcs(Gain1, + rtConstP.pooled79, &g_assTG_FRU_LV5[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table5' + * Lookup_n-D: '/1-D Lookup Table5' + * Saturate: '/Saturation1' + */ + rtb_MultiportSwitch_ev = look1_iu16bs16lu64n32ts16Ds32_binlcs(Gain1, + rtConstP.pooled51, &g_assINCAR_TG_FR_LV5[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch1' + */ + rtb_VectorConcatenate_by[0] = g_assDTG_FU_INC_Y1_LV5[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[1] = g_assDTG_FU_INC_Y2_LV5[CCU_FRONT_SYNC - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_by[2] = 0; + + /* MultiPortSwitch: '/Multiport Switch3' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant14' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_by[3] = g_assDTG_FU_INC_Y3_LV0[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant20' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_by[4] = g_assDTG_FU_INC_Y4_LV0[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[0] = g_assDTG_FU_INC_X1_LV0[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[1] = g_assDTG_FU_INC_X2_LV0[CCU_FRONT_SYNC - 1]; + break; + + case 1: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant15' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_by[3] = g_assDTG_FU_INC_Y3_LV1[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant21' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_by[4] = g_assDTG_FU_INC_Y4_LV1[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[0] = g_assDTG_FU_INC_X1_LV1[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[1] = g_assDTG_FU_INC_X2_LV1[CCU_FRONT_SYNC - 1]; + break; + + case 2: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant16' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_by[3] = g_assDTG_FU_INC_Y3_LV2[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant22' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_by[4] = g_assDTG_FU_INC_Y4_LV2[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[0] = g_assDTG_FU_INC_X1_LV2[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[1] = g_assDTG_FU_INC_X2_LV2[CCU_FRONT_SYNC - 1]; + break; + + case 3: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant17' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_by[3] = g_assDTG_FU_INC_Y3_LV3[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant23' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_by[4] = g_assDTG_FU_INC_Y4_LV3[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[0] = g_assDTG_FU_INC_X1_LV3[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[1] = g_assDTG_FU_INC_X2_LV3[CCU_FRONT_SYNC - 1]; + break; + + case 4: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant12' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_by[3] = g_assDTG_FU_INC_Y3_LV4[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant18' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_by[4] = g_assDTG_FU_INC_Y4_LV4[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[0] = g_assDTG_FU_INC_X1_LV4[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[1] = g_assDTG_FU_INC_X2_LV4[CCU_FRONT_SYNC - 1]; + break; + + default: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant13' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_by[3] = g_assDTG_FU_INC_Y3_LV5[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant19' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_by[4] = g_assDTG_FU_INC_Y4_LV5[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[0] = g_assDTG_FU_INC_X1_LV5[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[1] = g_assDTG_FU_INC_X2_LV5[CCU_FRONT_SYNC - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch3' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_kz[2] = 0; + + /* MultiPortSwitch: '/Multiport Switch3' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant14' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_kz[3] = g_assDTG_FU_INC_X3_LV0[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant20' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[4] = g_assDTG_FU_INC_X4_LV0[CCU_FRONT_SYNC - 1]; + break; + + case 1: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant15' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_kz[3] = g_assDTG_FU_INC_X3_LV1[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant21' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[4] = g_assDTG_FU_INC_X4_LV1[CCU_FRONT_SYNC - 1]; + break; + + case 2: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant16' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_kz[3] = g_assDTG_FU_INC_X3_LV2[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant22' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[4] = g_assDTG_FU_INC_X4_LV2[CCU_FRONT_SYNC - 1]; + break; + + case 3: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant17' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_kz[3] = g_assDTG_FU_INC_X3_LV3[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant23' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[4] = g_assDTG_FU_INC_X4_LV3[CCU_FRONT_SYNC - 1]; + break; + + case 4: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant12' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_kz[3] = g_assDTG_FU_INC_X3_LV4[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant18' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[4] = g_assDTG_FU_INC_X4_LV4[CCU_FRONT_SYNC - 1]; + break; + + default: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant13' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_kz[3] = g_assDTG_FU_INC_X3_LV5[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant19' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[4] = g_assDTG_FU_INC_X4_LV5[CCU_FRONT_SYNC - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch3' */ + + /* Lookup_n-D: '/2.5 FRU_tg_incar' incorporates: + * DataStoreRead: '/Data Store Read22' + * Sum: '/2.5. X = Inc_Tg - Incar_fb' + */ + rtb_u5FRU_tg_incar = look1_is16lu64n32Ds32_binlcn((int16_t) + (rtb_MultiportSwitch_ev - rtDW.Incar_FR), rtb_VectorConcatenate_kz, + rtb_VectorConcatenate_by, 4U); + + /* MultiPortSwitch: '/Multiport Switch1' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_dw[0] = g_assDTG_FU_AMB_Y1_LV0[CCU_FRONT_SYNC - 1]; + break; + + case 1: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_dw[0] = g_assDTG_FU_AMB_Y1_LV1[CCU_FRONT_SYNC - 1]; + break; + + case 2: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_dw[0] = g_assDTG_FU_AMB_Y1_LV2[CCU_FRONT_SYNC - 1]; + break; + + case 3: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_dw[0] = g_assDTG_FU_AMB_Y1_LV3[CCU_FRONT_SYNC - 1]; + break; + + case 4: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_dw[0] = g_assDTG_FU_AMB_Y1_LV4[CCU_FRONT_SYNC - 1]; + break; + + default: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_dw[0] = g_assDTG_FU_AMB_Y1_LV5[CCU_FRONT_SYNC - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_dw[1] = 0; + + /* MultiPortSwitch: '/Multiport Switch2' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_dw[2] = g_assDTG_FU_AMB_Y2_LV0[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_pg[0] = g_assDTG_FU_AMB_X1_LV0[CCU_FRONT_SYNC - 1]; + break; + + case 1: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_dw[2] = g_assDTG_FU_AMB_Y2_LV1[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_pg[0] = g_assDTG_FU_AMB_X1_LV1[CCU_FRONT_SYNC - 1]; + break; + + case 2: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_dw[2] = g_assDTG_FU_AMB_Y2_LV2[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_pg[0] = g_assDTG_FU_AMB_X1_LV2[CCU_FRONT_SYNC - 1]; + break; + + case 3: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_dw[2] = g_assDTG_FU_AMB_Y2_LV3[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_pg[0] = g_assDTG_FU_AMB_X1_LV3[CCU_FRONT_SYNC - 1]; + break; + + case 4: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_dw[2] = g_assDTG_FU_AMB_Y2_LV4[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_pg[0] = g_assDTG_FU_AMB_X1_LV4[CCU_FRONT_SYNC - 1]; + break; + + default: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_dw[2] = g_assDTG_FU_AMB_Y2_LV5[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_pg[0] = g_assDTG_FU_AMB_X1_LV5[CCU_FRONT_SYNC - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch2' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_pg[1] = 0; + + /* MultiPortSwitch: '/Multiport Switch2' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_pg[2] = g_assDTG_FU_AMB_X2_LV0[CCU_FRONT_SYNC - 1]; + break; + + case 1: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_pg[2] = g_assDTG_FU_AMB_X2_LV1[CCU_FRONT_SYNC - 1]; + break; + + case 2: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_pg[2] = g_assDTG_FU_AMB_X2_LV2[CCU_FRONT_SYNC - 1]; + break; + + case 3: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_pg[2] = g_assDTG_FU_AMB_X2_LV3[CCU_FRONT_SYNC - 1]; + break; + + case 4: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_pg[2] = g_assDTG_FU_AMB_X2_LV4[CCU_FRONT_SYNC - 1]; + break; + + default: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_pg[2] = g_assDTG_FU_AMB_X2_LV5[CCU_FRONT_SYNC - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch2' */ + + /* Lookup_n-D: '/2.6 FRU_tg_amb' */ + rtb_u6FRU_tg_amb_f = look1_is16lu64n32Ds32_binlcn(rtb_Bias5, + rtb_VectorConcatenate_pg, rtb_VectorConcatenate_dw, 2U); + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_gn[0] = 0; + + /* MultiPortSwitch: '/Multiport Switch1' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_gn[1] = g_assDTG_FU_SUN_Y1_LV0[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = g_assDTG_FU_SUN_Y2_LV0[CCU_FRONT_SYNC - 1]; + break; + + case 1: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_gn[1] = g_assDTG_FU_SUN_Y1_LV1[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = g_assDTG_FU_SUN_Y2_LV1[CCU_FRONT_SYNC - 1]; + break; + + case 2: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_gn[1] = g_assDTG_FU_SUN_Y1_LV2[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = g_assDTG_FU_SUN_Y2_LV2[CCU_FRONT_SYNC - 1]; + break; + + case 3: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_gn[1] = g_assDTG_FU_SUN_Y1_LV3[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = g_assDTG_FU_SUN_Y2_LV3[CCU_FRONT_SYNC - 1]; + break; + + case 4: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_gn[1] = g_assDTG_FU_SUN_Y1_LV4[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = g_assDTG_FU_SUN_Y2_LV4[CCU_FRONT_SYNC - 1]; + break; + + default: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_gn[1] = g_assDTG_FU_SUN_Y1_LV5[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = g_assDTG_FU_SUN_Y2_LV5[CCU_FRONT_SYNC - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_np[0] = 0; + + /* MultiPortSwitch: '/Multiport Switch1' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_np[1] = g_assDTG_FU_SUN_X1_LV0[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = g_assDTG_FU_SUN_X2_LV0[CCU_FRONT_SYNC - 1]; + break; + + case 1: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_np[1] = g_assDTG_FU_SUN_X1_LV1[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = g_assDTG_FU_SUN_X2_LV1[CCU_FRONT_SYNC - 1]; + break; + + case 2: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_np[1] = g_assDTG_FU_SUN_X1_LV2[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = g_assDTG_FU_SUN_X2_LV2[CCU_FRONT_SYNC - 1]; + break; + + case 3: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_np[1] = g_assDTG_FU_SUN_X1_LV3[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = g_assDTG_FU_SUN_X2_LV3[CCU_FRONT_SYNC - 1]; + break; + + case 4: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_np[1] = g_assDTG_FU_SUN_X1_LV4[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = g_assDTG_FU_SUN_X2_LV4[CCU_FRONT_SYNC - 1]; + break; + + default: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtb_VectorConcatenate_np[1] = g_assDTG_FU_SUN_X1_LV5[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = g_assDTG_FU_SUN_X2_LV5[CCU_FRONT_SYNC - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* Lookup_n-D: '/2.6 FRU_tg_amb' incorporates: + * DataStoreRead: '/Data Store Read27' + */ + rtb_u6FRU_tg_amb = look1_bs16ts16Dd_binlc(rtDW.Sun_R, rtb_VectorConcatenate_np, + rtb_VectorConcatenate_gn, 2U); + + /* Sum: '/FLU_tg_correct1' */ + rtb_FLU_tg_correct1 = (int16_t)((int16_t)((int16_t)(rtb_MultiportSwitch_fu + + rtb_u5FRU_tg_incar) + rtb_u6FRU_tg_amb_f) + rtb_u6FRU_tg_amb); + + /* Switch: '/Switch2' incorporates: + * DataTypeConversion: '/Data Type Conversion2' + * RelationalOperator: '/LowerRelop1' + * Selector: '/Selector' + */ + if (rtb_FLU_tg_correct1 > rtb_uDLookupTable7_g[CCU_FRONT_SYNC - 1]) { + rtb_FLU_tg_correct1 = rtb_uDLookupTable7_g[CCU_FRONT_SYNC - 1]; + } else { + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * Constant: '/Constant2' + * Constant: '/Constant3' + * Constant: '/Constant4' + * Constant: '/Constant5' + */ + switch (rtb_timer_out) { + case 0: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MIN_LV0[i]; + } + break; + + case 1: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MIN_LV1[i]; + } + break; + + case 2: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MIN_LV2[i]; + } + break; + + case 3: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MIN_LV3[i]; + } + break; + + case 4: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MIN_LV4[i]; + } + break; + + default: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MIN_LV5[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* Selector: '/Selector' */ + rtb_FLU_tg_correct_aa = rtb_uDLookupTable7_g[CCU_FRONT_SYNC - 1]; + + /* Switch: '/Switch' incorporates: + * RelationalOperator: '/UpperRelop' + * Selector: '/Selector' + */ + if (rtb_FLU_tg_correct1 < rtb_FLU_tg_correct_aa) { + rtb_FLU_tg_correct1 = rtb_FLU_tg_correct_aa; + } + + /* End of Switch: '/Switch' */ + } + + /* End of Switch: '/Switch2' */ + + /* Switch: '/Switch2' incorporates: + * Constant: '/Constant12' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read76' + */ + if (rtDW.CCU_AC_MAX > 0) { + i = 5; + } else { + i = rtDW.CCU_AUTOMODE_FR; + } + + /* MATLAB Function: '/func g_assAUTO_STEP_DUCT_TG_U' incorporates: + * DataStoreRead: '/Data Store Read20' + * Switch: '/Switch2' + */ + funcg_assAUTO_STEP_DUCT_TG_U(rtDW.LEVEL, (double)i, &rtb_y_jh); + + /* If: '/If' incorporates: + * Constant: '/manual' + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read46' + * DataStoreRead: '/Data Store Read' + * Logic: '/Logical Operator' + * RelationalOperator: '/Equal1' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * Switch: '/Switch' + */ + if ((rtDW.step_start_controle_front == 0) || (rtDW.step_start_controle_front == + 1) || (rtDW.step_start_controle_front == 2)) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem' incorporates: + * ActionPort: '/Action Port' + */ + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * DataStoreRead: '/dtg from Start Control' + */ + rtb_FLU_tg_correct1 = (int16_t)rtDW.Dtg_FUR; + + /* End of Outputs for SubSystem: '/If Action Subsystem' */ + } else if (rtDW.CCU_MODE_FR != 0) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem1' incorporates: + * ActionPort: '/Action Port' + */ + /* SignalConversion generated from: '/FXU' incorporates: + * Sum: '/Add' + * Switch: '/Switch' + */ + rtb_FLU_tg_correct1 += rtb_y_jh; + + /* End of Outputs for SubSystem: '/If Action Subsystem1' */ + } + + /* End of If: '/If' */ + + /* Switch: '/Switch15' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read44' + * DataStoreWrite: '/Data Store Write3' + */ + if (rtDW.LO_HI_MODE_FR > 1) { + rtb_FLU_tg_correct1 = 600; + } else { + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Gain: '/Gain' + * Gain: '/Gain1' + */ + index_start_0 = (int32_t)floor(((double)((int32_t)rtb_Subtract >> 19) - 15.0) + * 0.5 + 0.5); + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant10' + * Constant: '/Constant11' + * Constant: '/Constant12' + * Constant: '/Constant7' + * Constant: '/Constant8' + * Constant: '/Constant9' + */ + switch (rtb_timer_out) { + case 0: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MAX_LV0[i]; + } + break; + + case 1: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MAX_LV1[i]; + } + break; + + case 2: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MAX_LV2[i]; + } + break; + + case 3: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MAX_LV3[i]; + } + break; + + case 4: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MAX_LV4[i]; + } + break; + + default: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MAX_LV5[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* Selector: '/Selector' incorporates: + * DataTypeConversion: '/Data Type Conversion1' + */ + rtb_FLU_tg_correct_aa = rtb_uDLookupTable7_g[(uint8_t)index_start_0 - 1]; + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + * Selector: '/Selector' + */ + if (rtb_FLU_tg_correct1 > rtb_FLU_tg_correct_aa) { + /* DataStoreWrite: '/Data Store Write3' */ + rtb_FLU_tg_correct1 = rtb_FLU_tg_correct_aa; + } else { + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Constant: '/Constant' + * Constant: '/Constant2' + * Constant: '/Constant3' + * Constant: '/Constant4' + * Constant: '/Constant5' + * Constant: '/Constant6' + */ + switch (rtb_timer_out) { + case 0: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MIN_LV0[i]; + } + break; + + case 1: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MIN_LV1[i]; + } + break; + + case 2: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MIN_LV2[i]; + } + break; + + case 3: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MIN_LV3[i]; + } + break; + + case 4: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MIN_LV4[i]; + } + break; + + default: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FU_MIN_LV5[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch' */ + + /* Selector: '/Selector1' incorporates: + * DataTypeConversion: '/Data Type Conversion1' + */ + rtb_FLU_tg_correct_aa = rtb_uDLookupTable7_g[(uint8_t)index_start_0 - 1]; + + /* Switch: '/Switch' incorporates: + * RelationalOperator: '/UpperRelop' + * Selector: '/Selector1' + */ + if (rtb_FLU_tg_correct1 < rtb_FLU_tg_correct_aa) { + /* DataStoreWrite: '/Data Store Write3' */ + rtb_FLU_tg_correct1 = rtb_FLU_tg_correct_aa; + } + + /* End of Switch: '/Switch' */ + } + + /* End of Switch: '/Switch2' */ + } + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * Constant: '/Constant2' + * Constant: '/Constant3' + * Constant: '/Constant4' + * Constant: '/Constant5' + */ + switch (rtb_timer_out) { + case 0: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_R_MAX_LV0[i]; + } + break; + + case 1: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_R_MAX_LV1[i]; + } + break; + + case 2: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_R_MAX_LV2[i]; + } + break; + + case 3: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_R_MAX_LV3[i]; + } + break; + + case 4: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_R_MAX_LV4[i]; + } + break; + + default: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_R_MAX_LV5[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* Saturate: '/Saturation2' incorporates: + * DataStoreRead: '/Data Store Read18' + */ + if (rtDW.CCU_SET_RL > 290) { + rtb_Saturation2_a = 290U; + } else if (rtDW.CCU_SET_RL < 170) { + rtb_Saturation2_a = 170U; + } else { + rtb_Saturation2_a = rtDW.CCU_SET_RL; + } + + /* End of Saturate: '/Saturation2' */ + + /* Gain: '/Gain1' incorporates: + * Bias: '/Bias' + * DataTypeConversion: '/Data Type Conversion2' + * Gain: '/Gain' + * Product: '/Divide4' + */ + i = ((int32_t)((52429U * rtb_Saturation2_a) >> 19) + -15) << 14; + + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Product: '/Divide4' + * Saturate: '/Saturation' + */ + rtb_DataTypeConversion1_nc = (uint8_t)((((uint32_t)i & 16384U) != 0U) + (i >> + 15)); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table' + * Lookup_n-D: '/1-D Lookup Table1' + * Lookup_n-D: '/1-D Lookup Table2' + * Lookup_n-D: '/1-D Lookup Table3' + * Lookup_n-D: '/1-D Lookup Table4' + * Lookup_n-D: '/1-D Lookup Table5' + * Saturate: '/Saturation2' + */ + switch (rtb_timer_out) { + case 0: + rtb_MultiportSwitch_d = look1_iu16lu64n48ts16Ds32_binlcs(rtb_Saturation2_a, + rtConstP.pooled79, &g_assTG_RL_LV0[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table' + * Lookup_n-D: '/1-D Lookup Table' + * Saturate: '/Saturation2' + */ + rtb_MultiportSwitch_oh = look1_iu16bs16lu64n32ts16Ds32_binlcs + (rtb_Saturation2_a, rtConstP.pooled51, &g_assINCAR_TG_RL_LV0[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * MultiPortSwitch: '/Multiport Switch1' + */ + rtb_VectorConcatenate_by[0] = + g_assDTG_R_INC_Y1_LV0[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[1] = + g_assDTG_R_INC_Y2_LV0[rtb_DataTypeConversion1_nc - 1]; + break; + + case 1: + rtb_MultiportSwitch_d = look1_iu16lu64n48ts16Ds32_binlcs(rtb_Saturation2_a, + rtConstP.pooled79, &g_assTG_RL_LV1[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table1' + * Lookup_n-D: '/1-D Lookup Table1' + * Saturate: '/Saturation2' + */ + rtb_MultiportSwitch_oh = look1_iu16bs16lu64n32ts16Ds32_binlcs + (rtb_Saturation2_a, rtConstP.pooled51, &g_assINCAR_TG_RL_LV1[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * MultiPortSwitch: '/Multiport Switch1' + */ + rtb_VectorConcatenate_by[0] = + g_assDTG_R_INC_Y1_LV1[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[1] = + g_assDTG_R_INC_Y2_LV1[rtb_DataTypeConversion1_nc - 1]; + break; + + case 2: + rtb_MultiportSwitch_d = look1_iu16lu64n48ts16Ds32_binlcs(rtb_Saturation2_a, + rtConstP.pooled79, &g_assTG_RL_LV2[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table2' + * Lookup_n-D: '/1-D Lookup Table2' + * Saturate: '/Saturation2' + */ + rtb_MultiportSwitch_oh = look1_iu16bs16lu64n32ts16Ds32_binlcs + (rtb_Saturation2_a, rtConstP.pooled51, &g_assINCAR_TG_RL_LV2[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * MultiPortSwitch: '/Multiport Switch1' + */ + rtb_VectorConcatenate_by[0] = + g_assDTG_R_INC_Y1_LV2[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[1] = + g_assDTG_R_INC_Y2_LV2[rtb_DataTypeConversion1_nc - 1]; + break; + + case 3: + rtb_MultiportSwitch_d = look1_iu16lu64n48ts16Ds32_binlcs(rtb_Saturation2_a, + rtConstP.pooled79, &g_assTG_RL_LV3[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table3' + * Lookup_n-D: '/1-D Lookup Table3' + * Saturate: '/Saturation2' + */ + rtb_MultiportSwitch_oh = look1_iu16bs16lu64n32ts16Ds32_binlcs + (rtb_Saturation2_a, rtConstP.pooled51, &g_assINCAR_TG_RL_LV3[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * MultiPortSwitch: '/Multiport Switch1' + */ + rtb_VectorConcatenate_by[0] = + g_assDTG_R_INC_Y1_LV3[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[1] = + g_assDTG_R_INC_Y2_LV3[rtb_DataTypeConversion1_nc - 1]; + break; + + case 4: + rtb_MultiportSwitch_d = look1_iu16lu64n48ts16Ds32_binlcs(rtb_Saturation2_a, + rtConstP.pooled79, &g_assTG_RL_LV4[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table4' + * Lookup_n-D: '/1-D Lookup Table4' + * Saturate: '/Saturation2' + */ + rtb_MultiportSwitch_oh = look1_iu16bs16lu64n32ts16Ds32_binlcs + (rtb_Saturation2_a, rtConstP.pooled51, &g_assINCAR_TG_RL_LV4[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * MultiPortSwitch: '/Multiport Switch1' + */ + rtb_VectorConcatenate_by[0] = + g_assDTG_R_INC_Y1_LV4[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[1] = + g_assDTG_R_INC_Y2_LV4[rtb_DataTypeConversion1_nc - 1]; + break; + + default: + rtb_MultiportSwitch_d = look1_iu16lu64n48ts16Ds32_binlcs(rtb_Saturation2_a, + rtConstP.pooled79, &g_assTG_RL_LV5[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table5' + * Lookup_n-D: '/1-D Lookup Table5' + * Saturate: '/Saturation2' + */ + rtb_MultiportSwitch_oh = look1_iu16bs16lu64n32ts16Ds32_binlcs + (rtb_Saturation2_a, rtConstP.pooled51, &g_assINCAR_TG_RL_LV5[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * MultiPortSwitch: '/Multiport Switch1' + */ + rtb_VectorConcatenate_by[0] = + g_assDTG_R_INC_Y1_LV5[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[1] = + g_assDTG_R_INC_Y2_LV5[rtb_DataTypeConversion1_nc - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_by[2] = 0; + + /* MultiPortSwitch: '/Multiport Switch3' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant14' + */ + rtb_VectorConcatenate_by[3] = + g_assDTG_R_INC_Y3_LV0[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant20' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_by[4] = + g_assDTG_R_INC_Y4_LV0[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[0] = + g_assDTG_R_INC_X1_LV0[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[1] = + g_assDTG_R_INC_X2_LV0[rtb_DataTypeConversion1_nc - 1]; + break; + + case 1: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant15' + */ + rtb_VectorConcatenate_by[3] = + g_assDTG_R_INC_Y3_LV1[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant21' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_by[4] = + g_assDTG_R_INC_Y4_LV1[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[0] = + g_assDTG_R_INC_X1_LV1[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[1] = + g_assDTG_R_INC_X2_LV1[rtb_DataTypeConversion1_nc - 1]; + break; + + case 2: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant16' + */ + rtb_VectorConcatenate_by[3] = + g_assDTG_R_INC_Y3_LV2[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant22' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_by[4] = + g_assDTG_R_INC_Y4_LV2[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[0] = + g_assDTG_R_INC_X1_LV2[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[1] = + g_assDTG_R_INC_X2_LV2[rtb_DataTypeConversion1_nc - 1]; + break; + + case 3: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant17' + */ + rtb_VectorConcatenate_by[3] = + g_assDTG_R_INC_Y3_LV3[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant23' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_by[4] = + g_assDTG_R_INC_Y4_LV3[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[0] = + g_assDTG_R_INC_X1_LV3[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[1] = + g_assDTG_R_INC_X2_LV3[rtb_DataTypeConversion1_nc - 1]; + break; + + case 4: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant12' + */ + rtb_VectorConcatenate_by[3] = + g_assDTG_R_INC_Y3_LV4[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant18' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_by[4] = + g_assDTG_R_INC_Y4_LV4[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[0] = + g_assDTG_R_INC_X1_LV4[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[1] = + g_assDTG_R_INC_X2_LV4[rtb_DataTypeConversion1_nc - 1]; + break; + + default: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant13' + */ + rtb_VectorConcatenate_by[3] = + g_assDTG_R_INC_Y3_LV5[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant19' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_by[4] = + g_assDTG_R_INC_Y4_LV5[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[0] = + g_assDTG_R_INC_X1_LV5[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[1] = + g_assDTG_R_INC_X2_LV5[rtb_DataTypeConversion1_nc - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch3' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_kz[2] = 0; + + /* MultiPortSwitch: '/Multiport Switch3' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant14' + */ + rtb_VectorConcatenate_kz[3] = + g_assDTG_R_INC_X3_LV0[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant20' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[4] = + g_assDTG_R_INC_X4_LV0[rtb_DataTypeConversion1_nc - 1]; + break; + + case 1: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant15' + */ + rtb_VectorConcatenate_kz[3] = + g_assDTG_R_INC_X3_LV1[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant21' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[4] = + g_assDTG_R_INC_X4_LV1[rtb_DataTypeConversion1_nc - 1]; + break; + + case 2: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant16' + */ + rtb_VectorConcatenate_kz[3] = + g_assDTG_R_INC_X3_LV2[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant22' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[4] = + g_assDTG_R_INC_X4_LV2[rtb_DataTypeConversion1_nc - 1]; + break; + + case 3: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant17' + */ + rtb_VectorConcatenate_kz[3] = + g_assDTG_R_INC_X3_LV3[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant23' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[4] = + g_assDTG_R_INC_X4_LV3[rtb_DataTypeConversion1_nc - 1]; + break; + + case 4: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant12' + */ + rtb_VectorConcatenate_kz[3] = + g_assDTG_R_INC_X3_LV4[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant18' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[4] = + g_assDTG_R_INC_X4_LV4[rtb_DataTypeConversion1_nc - 1]; + break; + + default: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant13' + */ + rtb_VectorConcatenate_kz[3] = + g_assDTG_R_INC_X3_LV5[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant19' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[4] = + g_assDTG_R_INC_X4_LV5[rtb_DataTypeConversion1_nc - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch3' */ + + /* Lookup_n-D: '/2.5 R_tg_incar' incorporates: + * DataStoreRead: '/Data Store Read23' + * Sum: '/2.5. X = Inc_Tg - Incar_fb' + */ + rtb_u5R_tg_incar = look1_is16lu64n32Ds32_binlcn((int16_t) + (rtb_MultiportSwitch_oh - rtDW.Incar_RL), rtb_VectorConcatenate_kz, + rtb_VectorConcatenate_by, 4U); + + /* MultiPortSwitch: '/Multiport Switch1' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + */ + rtb_VectorConcatenate_dw[0] = + g_assDTG_R_AMB_Y1_LV0[rtb_DataTypeConversion1_nc - 1]; + break; + + case 1: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + */ + rtb_VectorConcatenate_dw[0] = + g_assDTG_R_AMB_Y1_LV1[rtb_DataTypeConversion1_nc - 1]; + break; + + case 2: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + */ + rtb_VectorConcatenate_dw[0] = + g_assDTG_R_AMB_Y1_LV2[rtb_DataTypeConversion1_nc - 1]; + break; + + case 3: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + */ + rtb_VectorConcatenate_dw[0] = + g_assDTG_R_AMB_Y1_LV3[rtb_DataTypeConversion1_nc - 1]; + break; + + case 4: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + */ + rtb_VectorConcatenate_dw[0] = + g_assDTG_R_AMB_Y1_LV4[rtb_DataTypeConversion1_nc - 1]; + break; + + default: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + */ + rtb_VectorConcatenate_dw[0] = + g_assDTG_R_AMB_Y1_LV5[rtb_DataTypeConversion1_nc - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_dw[1] = 0; + + /* MultiPortSwitch: '/Multiport Switch2' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + */ + rtb_VectorConcatenate_dw[2] = + g_assDTG_R_AMB_Y2_LV0[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_pg[0] = + g_assDTG_R_AMB_X1_LV0[rtb_DataTypeConversion1_nc - 1]; + break; + + case 1: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + */ + rtb_VectorConcatenate_dw[2] = + g_assDTG_R_AMB_Y2_LV1[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_pg[0] = + g_assDTG_R_AMB_X1_LV1[rtb_DataTypeConversion1_nc - 1]; + break; + + case 2: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + */ + rtb_VectorConcatenate_dw[2] = + g_assDTG_R_AMB_Y2_LV2[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_pg[0] = + g_assDTG_R_AMB_X1_LV2[rtb_DataTypeConversion1_nc - 1]; + break; + + case 3: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + */ + rtb_VectorConcatenate_dw[2] = + g_assDTG_R_AMB_Y2_LV3[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_pg[0] = + g_assDTG_R_AMB_X1_LV3[rtb_DataTypeConversion1_nc - 1]; + break; + + case 4: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + */ + rtb_VectorConcatenate_dw[2] = + g_assDTG_R_AMB_Y2_LV4[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_pg[0] = + g_assDTG_R_AMB_X1_LV4[rtb_DataTypeConversion1_nc - 1]; + break; + + default: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + */ + rtb_VectorConcatenate_dw[2] = + g_assDTG_R_AMB_Y2_LV5[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_pg[0] = + g_assDTG_R_AMB_X1_LV5[rtb_DataTypeConversion1_nc - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch2' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_pg[1] = 0; + + /* MultiPortSwitch: '/Multiport Switch2' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + */ + rtb_VectorConcatenate_pg[2] = + g_assDTG_R_AMB_X2_LV0[rtb_DataTypeConversion1_nc - 1]; + break; + + case 1: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + */ + rtb_VectorConcatenate_pg[2] = + g_assDTG_R_AMB_X2_LV1[rtb_DataTypeConversion1_nc - 1]; + break; + + case 2: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + */ + rtb_VectorConcatenate_pg[2] = + g_assDTG_R_AMB_X2_LV2[rtb_DataTypeConversion1_nc - 1]; + break; + + case 3: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + */ + rtb_VectorConcatenate_pg[2] = + g_assDTG_R_AMB_X2_LV3[rtb_DataTypeConversion1_nc - 1]; + break; + + case 4: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + */ + rtb_VectorConcatenate_pg[2] = + g_assDTG_R_AMB_X2_LV4[rtb_DataTypeConversion1_nc - 1]; + break; + + default: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + */ + rtb_VectorConcatenate_pg[2] = + g_assDTG_R_AMB_X2_LV5[rtb_DataTypeConversion1_nc - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch2' */ + + /* Lookup_n-D: '/2.6 FLU_tg_amb' */ + rtb_u6FLU_tg_amb_d = look1_is16lu64n32Ds32_binlcn(rtb_Bias5, + rtb_VectorConcatenate_pg, rtb_VectorConcatenate_dw, 2U); + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_gn[0] = 0; + + /* MultiPortSwitch: '/Multiport Switch1' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + */ + rtb_VectorConcatenate_gn[1] = + g_assDTG_R_SUN_Y1_LV0[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = + g_assDTG_R_SUN_Y2_LV0[rtb_DataTypeConversion1_nc - 1]; + break; + + case 1: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + */ + rtb_VectorConcatenate_gn[1] = + g_assDTG_R_SUN_Y1_LV1[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = + g_assDTG_R_SUN_Y2_LV1[rtb_DataTypeConversion1_nc - 1]; + break; + + case 2: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + */ + rtb_VectorConcatenate_gn[1] = + g_assDTG_R_SUN_Y1_LV2[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = + g_assDTG_R_SUN_Y2_LV2[rtb_DataTypeConversion1_nc - 1]; + break; + + case 3: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + */ + rtb_VectorConcatenate_gn[1] = + g_assDTG_R_SUN_Y1_LV3[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = + g_assDTG_R_SUN_Y2_LV3[rtb_DataTypeConversion1_nc - 1]; + break; + + case 4: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + */ + rtb_VectorConcatenate_gn[1] = + g_assDTG_R_SUN_Y1_LV4[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = + g_assDTG_R_SUN_Y2_LV4[rtb_DataTypeConversion1_nc - 1]; + break; + + default: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + */ + rtb_VectorConcatenate_gn[1] = + g_assDTG_R_SUN_Y1_LV5[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = + g_assDTG_R_SUN_Y2_LV5[rtb_DataTypeConversion1_nc - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_np[0] = 0; + + /* MultiPortSwitch: '/Multiport Switch1' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + */ + rtb_VectorConcatenate_np[1] = + g_assDTG_FU_SUN_X1_LV0[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = + g_assDTG_FU_SUN_X2_LV0[rtb_DataTypeConversion1_nc - 1]; + break; + + case 1: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + */ + rtb_VectorConcatenate_np[1] = + g_assDTG_FU_SUN_X1_LV1[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = + g_assDTG_FU_SUN_X2_LV1[rtb_DataTypeConversion1_nc - 1]; + break; + + case 2: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + */ + rtb_VectorConcatenate_np[1] = + g_assDTG_FU_SUN_X1_LV2[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = + g_assDTG_FU_SUN_X2_LV2[rtb_DataTypeConversion1_nc - 1]; + break; + + case 3: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + */ + rtb_VectorConcatenate_np[1] = + g_assDTG_FU_SUN_X1_LV3[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = + g_assDTG_FU_SUN_X2_LV3[rtb_DataTypeConversion1_nc - 1]; + break; + + case 4: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + */ + rtb_VectorConcatenate_np[1] = + g_assDTG_FU_SUN_X1_LV4[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = + g_assDTG_FU_SUN_X2_LV4[rtb_DataTypeConversion1_nc - 1]; + break; + + default: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + */ + rtb_VectorConcatenate_np[1] = + g_assDTG_FU_SUN_X1_LV5[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = + g_assDTG_FU_SUN_X2_LV5[rtb_DataTypeConversion1_nc - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* Lookup_n-D: '/2.6 FLU_tg_amb' incorporates: + * DataStoreRead: '/Data Store Read26' + */ + rtb_u6FLU_tg_amb_n = look1_bs16ts16Dd_binlc(rtDW.Sun_L, + rtb_VectorConcatenate_np, rtb_VectorConcatenate_gn, 2U); + + /* Sum: '/FLU_tg_correct' */ + rtb_y_jh = (int16_t)((int16_t)((int16_t)(rtb_MultiportSwitch_d + + rtb_u5R_tg_incar) + rtb_u6FLU_tg_amb_d) + rtb_u6FLU_tg_amb_n); + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + * Selector: '/Selector' + */ + if (rtb_y_jh > rtb_uDLookupTable7_g[rtb_DataTypeConversion1_nc - 1]) { + rtb_y_jh = rtb_uDLookupTable7_g[rtb_DataTypeConversion1_nc - 1]; + } else { + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * Constant: '/Constant2' + * Constant: '/Constant3' + * Constant: '/Constant4' + * Constant: '/Constant5' + */ + switch (rtb_timer_out) { + case 0: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_R_MIN_LV0[i]; + } + break; + + case 1: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_R_MIN_LV1[i]; + } + break; + + case 2: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_R_MIN_LV2[i]; + } + break; + + case 3: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_R_MIN_LV3[i]; + } + break; + + case 4: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_R_MIN_LV4[i]; + } + break; + + default: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_R_MIN_LV5[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* Selector: '/Selector' */ + rtb_FLU_tg_correct_aa = rtb_uDLookupTable7_g[rtb_DataTypeConversion1_nc - 1]; + + /* Switch: '/Switch' incorporates: + * RelationalOperator: '/UpperRelop' + * Selector: '/Selector' + */ + if (rtb_y_jh < rtb_FLU_tg_correct_aa) { + rtb_y_jh = rtb_FLU_tg_correct_aa; + } + + /* End of Switch: '/Switch' */ + } + + /* End of Switch: '/Switch2' */ + + /* Switch: '/Switch2' incorporates: + * Constant: '/Constant12' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read76' + */ + if (rtDW.CCU_AC_MAX > 0) { + i = 5; + } else { + i = rtDW.CCU_AUTOMODE_RL; + } + + /* MATLAB Function: '/func g_assAUTO_STEP_DUCT_TG_R' incorporates: + * DataStoreRead: '/Data Store Read20' + * Switch: '/Switch2' + */ + funcg_assAUTO_STEP_DUCT_TG_R(rtDW.LEVEL, (double)i, &rtb_y_mz); + + /* Switch: '/Switch15' incorporates: + * Constant: '/manual' + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read46' + * DataStoreRead: '/Data Store Read44' + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write4' + * If: '/If' + * Logic: '/Logical Operator' + * RelationalOperator: '/Equal1' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * Sum: '/Add' + * Switch: '/Switch' + */ + if (rtDW.LO_HI_MODE_RL > 1) { + rtb_y_jh = 800; + } else if ((rtDW.step_start_controle_rear == 0) || + (rtDW.step_start_controle_rear == 1) || + (rtDW.step_start_controle_rear == 2)) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem' incorporates: + * ActionPort: '/Action Port' + */ + /* If: '/If' incorporates: + * DataStoreRead: '/dtg from Start Control' + * DataStoreWrite: '/Data Store Write4' + * DataTypeConversion: '/Data Type Conversion' + */ + rtb_y_jh = (int16_t)rtDW.Dtg_RL; + + /* End of Outputs for SubSystem: '/If Action Subsystem' */ + } else if (rtDW.CCU_MODE_RL != 0) { + rtb_y_jh += rtb_y_mz; + } + + /* End of Switch: '/Switch15' */ + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * Constant: '/Constant2' + * Constant: '/Constant3' + * Constant: '/Constant4' + * Constant: '/Constant5' + */ + switch (rtb_timer_out) { + case 0: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_R_MAX_LV0[i]; + } + break; + + case 1: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_R_MAX_LV1[i]; + } + break; + + case 2: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_R_MAX_LV2[i]; + } + break; + + case 3: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_R_MAX_LV3[i]; + } + break; + + case 4: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_R_MAX_LV4[i]; + } + break; + + default: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_R_MAX_LV5[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* Saturate: '/Saturation3' incorporates: + * DataStoreRead: '/Data Store Read19' + */ + if (rtDW.CCU_SET_RR > 290) { + rtb_Saturation2_a = 290U; + } else if (rtDW.CCU_SET_RR < 170) { + rtb_Saturation2_a = 170U; + } else { + rtb_Saturation2_a = rtDW.CCU_SET_RR; + } + + /* End of Saturate: '/Saturation3' */ + + /* Gain: '/Gain1' incorporates: + * Bias: '/Bias' + * DataTypeConversion: '/Data Type Conversion2' + * Gain: '/Gain' + * Product: '/Divide4' + */ + i = ((int32_t)((52429U * rtb_Saturation2_a) >> 19) + -15) << 14; + + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Product: '/Divide4' + * Saturate: '/Saturation' + */ + rtb_DataTypeConversion1_nc = (uint8_t)((((uint32_t)i & 16384U) != 0U) + (i >> + 15)); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table' + * Lookup_n-D: '/1-D Lookup Table1' + * Lookup_n-D: '/1-D Lookup Table2' + * Lookup_n-D: '/1-D Lookup Table3' + * Lookup_n-D: '/1-D Lookup Table4' + * Lookup_n-D: '/1-D Lookup Table5' + * Saturate: '/Saturation3' + */ + switch (rtb_timer_out) { + case 0: + rtb_MultiportSwitch_gq = look1_iu16lu64n48ts16Ds32_binlcs(rtb_Saturation2_a, + rtConstP.pooled79, &g_assTG_RR_LV0[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table' + * Lookup_n-D: '/1-D Lookup Table' + * Saturate: '/Saturation3' + */ + rtb_MultiportSwitch_ci = look1_iu16bs16lu64n32ts16Ds32_binlcs + (rtb_Saturation2_a, rtConstP.pooled51, &g_assINCAR_TG_RR_LV0[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * MultiPortSwitch: '/Multiport Switch1' + */ + rtb_VectorConcatenate_by[0] = + g_assDTG_R_INC_Y1_LV0[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[1] = + g_assDTG_R_INC_Y2_LV0[rtb_DataTypeConversion1_nc - 1]; + break; + + case 1: + rtb_MultiportSwitch_gq = look1_iu16lu64n48ts16Ds32_binlcs(rtb_Saturation2_a, + rtConstP.pooled79, &g_assTG_RR_LV1[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table1' + * Lookup_n-D: '/1-D Lookup Table1' + * Saturate: '/Saturation3' + */ + rtb_MultiportSwitch_ci = look1_iu16bs16lu64n32ts16Ds32_binlcs + (rtb_Saturation2_a, rtConstP.pooled51, &g_assINCAR_TG_RR_LV1[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * MultiPortSwitch: '/Multiport Switch1' + */ + rtb_VectorConcatenate_by[0] = + g_assDTG_R_INC_Y1_LV1[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[1] = + g_assDTG_R_INC_Y2_LV1[rtb_DataTypeConversion1_nc - 1]; + break; + + case 2: + rtb_MultiportSwitch_gq = look1_iu16lu64n48ts16Ds32_binlcs(rtb_Saturation2_a, + rtConstP.pooled79, &g_assTG_RR_LV2[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table2' + * Lookup_n-D: '/1-D Lookup Table2' + * Saturate: '/Saturation3' + */ + rtb_MultiportSwitch_ci = look1_iu16bs16lu64n32ts16Ds32_binlcs + (rtb_Saturation2_a, rtConstP.pooled51, &g_assINCAR_TG_RR_LV2[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * MultiPortSwitch: '/Multiport Switch1' + */ + rtb_VectorConcatenate_by[0] = + g_assDTG_R_INC_Y1_LV2[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[1] = + g_assDTG_R_INC_Y2_LV2[rtb_DataTypeConversion1_nc - 1]; + break; + + case 3: + rtb_MultiportSwitch_gq = look1_iu16lu64n48ts16Ds32_binlcs(rtb_Saturation2_a, + rtConstP.pooled79, &g_assTG_RR_LV3[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table3' + * Lookup_n-D: '/1-D Lookup Table3' + * Saturate: '/Saturation3' + */ + rtb_MultiportSwitch_ci = look1_iu16bs16lu64n32ts16Ds32_binlcs + (rtb_Saturation2_a, rtConstP.pooled51, &g_assINCAR_TG_RR_LV3[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * MultiPortSwitch: '/Multiport Switch1' + */ + rtb_VectorConcatenate_by[0] = + g_assDTG_R_INC_Y1_LV3[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[1] = + g_assDTG_R_INC_Y2_LV3[rtb_DataTypeConversion1_nc - 1]; + break; + + case 4: + rtb_MultiportSwitch_gq = look1_iu16lu64n48ts16Ds32_binlcs(rtb_Saturation2_a, + rtConstP.pooled79, &g_assTG_RR_LV4[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table4' + * Lookup_n-D: '/1-D Lookup Table4' + * Saturate: '/Saturation3' + */ + rtb_MultiportSwitch_ci = look1_iu16bs16lu64n32ts16Ds32_binlcs + (rtb_Saturation2_a, rtConstP.pooled51, &g_assINCAR_TG_RR_LV4[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * MultiPortSwitch: '/Multiport Switch1' + */ + rtb_VectorConcatenate_by[0] = + g_assDTG_R_INC_Y1_LV4[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[1] = + g_assDTG_R_INC_Y2_LV4[rtb_DataTypeConversion1_nc - 1]; + break; + + default: + rtb_MultiportSwitch_gq = look1_iu16lu64n48ts16Ds32_binlcs(rtb_Saturation2_a, + rtConstP.pooled79, &g_assTG_RR_LV5[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table5' + * Lookup_n-D: '/1-D Lookup Table5' + * Saturate: '/Saturation3' + */ + rtb_MultiportSwitch_ci = look1_iu16bs16lu64n32ts16Ds32_binlcs + (rtb_Saturation2_a, rtConstP.pooled51, &g_assINCAR_TG_RR_LV5[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * MultiPortSwitch: '/Multiport Switch1' + */ + rtb_VectorConcatenate_by[0] = + g_assDTG_R_INC_Y1_LV5[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[1] = + g_assDTG_R_INC_Y2_LV5[rtb_DataTypeConversion1_nc - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_by[2] = 0; + + /* MultiPortSwitch: '/Multiport Switch3' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant14' + */ + rtb_VectorConcatenate_by[3] = + g_assDTG_R_INC_Y3_LV0[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant20' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_by[4] = + g_assDTG_R_INC_Y4_LV0[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[0] = + g_assDTG_R_INC_X1_LV0[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[1] = + g_assDTG_R_INC_X2_LV0[rtb_DataTypeConversion1_nc - 1]; + break; + + case 1: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant15' + */ + rtb_VectorConcatenate_by[3] = + g_assDTG_R_INC_Y3_LV1[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant21' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_by[4] = + g_assDTG_R_INC_Y4_LV1[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[0] = + g_assDTG_R_INC_X1_LV1[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[1] = + g_assDTG_R_INC_X2_LV1[rtb_DataTypeConversion1_nc - 1]; + break; + + case 2: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant16' + */ + rtb_VectorConcatenate_by[3] = + g_assDTG_R_INC_Y3_LV2[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant22' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_by[4] = + g_assDTG_R_INC_Y4_LV2[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[0] = + g_assDTG_R_INC_X1_LV2[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[1] = + g_assDTG_R_INC_X2_LV2[rtb_DataTypeConversion1_nc - 1]; + break; + + case 3: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant17' + */ + rtb_VectorConcatenate_by[3] = + g_assDTG_R_INC_Y3_LV3[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant23' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_by[4] = + g_assDTG_R_INC_Y4_LV3[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[0] = + g_assDTG_R_INC_X1_LV3[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[1] = + g_assDTG_R_INC_X2_LV3[rtb_DataTypeConversion1_nc - 1]; + break; + + case 4: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant12' + */ + rtb_VectorConcatenate_by[3] = + g_assDTG_R_INC_Y3_LV4[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant18' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_by[4] = + g_assDTG_R_INC_Y4_LV4[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[0] = + g_assDTG_R_INC_X1_LV4[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[1] = + g_assDTG_R_INC_X2_LV4[rtb_DataTypeConversion1_nc - 1]; + break; + + default: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant13' + */ + rtb_VectorConcatenate_by[3] = + g_assDTG_R_INC_Y3_LV5[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant19' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_by[4] = + g_assDTG_R_INC_Y4_LV5[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[0] = + g_assDTG_R_INC_X1_LV5[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[1] = + g_assDTG_R_INC_X2_LV5[rtb_DataTypeConversion1_nc - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch3' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_kz[2] = 0; + + /* MultiPortSwitch: '/Multiport Switch3' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant14' + */ + rtb_VectorConcatenate_kz[3] = + g_assDTG_R_INC_X3_LV0[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant20' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[4] = + g_assDTG_R_INC_X4_LV0[rtb_DataTypeConversion1_nc - 1]; + break; + + case 1: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant15' + */ + rtb_VectorConcatenate_kz[3] = + g_assDTG_R_INC_X3_LV1[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant21' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[4] = + g_assDTG_R_INC_X4_LV1[rtb_DataTypeConversion1_nc - 1]; + break; + + case 2: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant16' + */ + rtb_VectorConcatenate_kz[3] = + g_assDTG_R_INC_X3_LV2[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant22' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[4] = + g_assDTG_R_INC_X4_LV2[rtb_DataTypeConversion1_nc - 1]; + break; + + case 3: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant17' + */ + rtb_VectorConcatenate_kz[3] = + g_assDTG_R_INC_X3_LV3[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant23' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[4] = + g_assDTG_R_INC_X4_LV3[rtb_DataTypeConversion1_nc - 1]; + break; + + case 4: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant12' + */ + rtb_VectorConcatenate_kz[3] = + g_assDTG_R_INC_X3_LV4[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant18' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[4] = + g_assDTG_R_INC_X4_LV4[rtb_DataTypeConversion1_nc - 1]; + break; + + default: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant13' + */ + rtb_VectorConcatenate_kz[3] = + g_assDTG_R_INC_X3_LV5[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant19' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_kz[4] = + g_assDTG_R_INC_X4_LV5[rtb_DataTypeConversion1_nc - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch3' */ + + /* Lookup_n-D: '/2.5 FLU_tg_incar' incorporates: + * DataStoreRead: '/Data Store Read24' + * Sum: '/2.5. X = Inc_Tg - Incar_fb' + */ + rtb_X = look1_is16lu64n32Ds32_binlcn((int16_t)(rtb_MultiportSwitch_ci - + rtDW.Incar_RR), rtb_VectorConcatenate_kz, rtb_VectorConcatenate_by, 4U); + + /* MultiPortSwitch: '/Multiport Switch1' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + */ + rtb_VectorConcatenate_dw[0] = + g_assDTG_R_AMB_Y1_LV0[rtb_DataTypeConversion1_nc - 1]; + break; + + case 1: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + */ + rtb_VectorConcatenate_dw[0] = + g_assDTG_R_AMB_Y1_LV1[rtb_DataTypeConversion1_nc - 1]; + break; + + case 2: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + */ + rtb_VectorConcatenate_dw[0] = + g_assDTG_R_AMB_Y1_LV2[rtb_DataTypeConversion1_nc - 1]; + break; + + case 3: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + */ + rtb_VectorConcatenate_dw[0] = + g_assDTG_R_AMB_Y1_LV3[rtb_DataTypeConversion1_nc - 1]; + break; + + case 4: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + */ + rtb_VectorConcatenate_dw[0] = + g_assDTG_R_AMB_Y1_LV4[rtb_DataTypeConversion1_nc - 1]; + break; + + default: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + */ + rtb_VectorConcatenate_dw[0] = + g_assDTG_R_AMB_Y1_LV5[rtb_DataTypeConversion1_nc - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_dw[1] = 0; + + /* MultiPortSwitch: '/Multiport Switch2' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + */ + rtb_VectorConcatenate_dw[2] = + g_assDTG_R_AMB_Y2_LV0[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_pg[0] = + g_assDTG_R_AMB_X1_LV0[rtb_DataTypeConversion1_nc - 1]; + break; + + case 1: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + */ + rtb_VectorConcatenate_dw[2] = + g_assDTG_R_AMB_Y2_LV1[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_pg[0] = + g_assDTG_R_AMB_X1_LV1[rtb_DataTypeConversion1_nc - 1]; + break; + + case 2: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + */ + rtb_VectorConcatenate_dw[2] = + g_assDTG_R_AMB_Y2_LV2[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_pg[0] = + g_assDTG_R_AMB_X1_LV2[rtb_DataTypeConversion1_nc - 1]; + break; + + case 3: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + */ + rtb_VectorConcatenate_dw[2] = + g_assDTG_R_AMB_Y2_LV3[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_pg[0] = + g_assDTG_R_AMB_X1_LV3[rtb_DataTypeConversion1_nc - 1]; + break; + + case 4: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + */ + rtb_VectorConcatenate_dw[2] = + g_assDTG_R_AMB_Y2_LV4[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_pg[0] = + g_assDTG_R_AMB_X1_LV4[rtb_DataTypeConversion1_nc - 1]; + break; + + default: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + */ + rtb_VectorConcatenate_dw[2] = + g_assDTG_R_AMB_Y2_LV5[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_pg[0] = + g_assDTG_R_AMB_X1_LV5[rtb_DataTypeConversion1_nc - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch2' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_pg[1] = 0; + + /* MultiPortSwitch: '/Multiport Switch2' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + */ + rtb_VectorConcatenate_pg[2] = + g_assDTG_R_AMB_X2_LV0[rtb_DataTypeConversion1_nc - 1]; + break; + + case 1: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + */ + rtb_VectorConcatenate_pg[2] = + g_assDTG_R_AMB_X2_LV1[rtb_DataTypeConversion1_nc - 1]; + break; + + case 2: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + */ + rtb_VectorConcatenate_pg[2] = + g_assDTG_R_AMB_X2_LV2[rtb_DataTypeConversion1_nc - 1]; + break; + + case 3: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + */ + rtb_VectorConcatenate_pg[2] = + g_assDTG_R_AMB_X2_LV3[rtb_DataTypeConversion1_nc - 1]; + break; + + case 4: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + */ + rtb_VectorConcatenate_pg[2] = + g_assDTG_R_AMB_X2_LV4[rtb_DataTypeConversion1_nc - 1]; + break; + + default: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + */ + rtb_VectorConcatenate_pg[2] = + g_assDTG_R_AMB_X2_LV5[rtb_DataTypeConversion1_nc - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch2' */ + + /* Lookup_n-D: '/2.6 FLU_tg_amb' */ + rtb_MultiportSwitch_jq = look1_is16lu64n32Ds32_binlcn(rtb_Bias5, + rtb_VectorConcatenate_pg, rtb_VectorConcatenate_dw, 2U); + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_gn[0] = 0; + + /* MultiPortSwitch: '/Multiport Switch1' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + */ + rtb_VectorConcatenate_gn[1] = + g_assDTG_R_SUN_Y1_LV0[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = + g_assDTG_R_SUN_Y2_LV0[rtb_DataTypeConversion1_nc - 1]; + break; + + case 1: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + */ + rtb_VectorConcatenate_gn[1] = + g_assDTG_R_SUN_Y1_LV1[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = + g_assDTG_R_SUN_Y2_LV1[rtb_DataTypeConversion1_nc - 1]; + break; + + case 2: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + */ + rtb_VectorConcatenate_gn[1] = + g_assDTG_R_SUN_Y1_LV2[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = + g_assDTG_R_SUN_Y2_LV2[rtb_DataTypeConversion1_nc - 1]; + break; + + case 3: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + */ + rtb_VectorConcatenate_gn[1] = + g_assDTG_R_SUN_Y1_LV3[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = + g_assDTG_R_SUN_Y2_LV3[rtb_DataTypeConversion1_nc - 1]; + break; + + case 4: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + */ + rtb_VectorConcatenate_gn[1] = + g_assDTG_R_SUN_Y1_LV4[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = + g_assDTG_R_SUN_Y2_LV4[rtb_DataTypeConversion1_nc - 1]; + break; + + default: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + */ + rtb_VectorConcatenate_gn[1] = + g_assDTG_R_SUN_Y1_LV5[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = + g_assDTG_R_SUN_Y2_LV5[rtb_DataTypeConversion1_nc - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_np[0] = 0; + + /* MultiPortSwitch: '/Multiport Switch1' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + */ + rtb_VectorConcatenate_np[1] = + g_assDTG_FU_SUN_X1_LV0[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = + g_assDTG_FU_SUN_X2_LV0[rtb_DataTypeConversion1_nc - 1]; + break; + + case 1: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + */ + rtb_VectorConcatenate_np[1] = + g_assDTG_FU_SUN_X1_LV1[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = + g_assDTG_FU_SUN_X2_LV1[rtb_DataTypeConversion1_nc - 1]; + break; + + case 2: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + */ + rtb_VectorConcatenate_np[1] = + g_assDTG_FU_SUN_X1_LV2[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = + g_assDTG_FU_SUN_X2_LV2[rtb_DataTypeConversion1_nc - 1]; + break; + + case 3: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + */ + rtb_VectorConcatenate_np[1] = + g_assDTG_FU_SUN_X1_LV3[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = + g_assDTG_FU_SUN_X2_LV3[rtb_DataTypeConversion1_nc - 1]; + break; + + case 4: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + */ + rtb_VectorConcatenate_np[1] = + g_assDTG_FU_SUN_X1_LV4[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = + g_assDTG_FU_SUN_X2_LV4[rtb_DataTypeConversion1_nc - 1]; + break; + + default: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + */ + rtb_VectorConcatenate_np[1] = + g_assDTG_FU_SUN_X1_LV5[rtb_DataTypeConversion1_nc - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = + g_assDTG_FU_SUN_X2_LV5[rtb_DataTypeConversion1_nc - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* Lookup_n-D: '/2.6 FLU_tg_amb' incorporates: + * DataStoreRead: '/Data Store Read27' + */ + rtb_u6FLU_tg_amb_a3 = look1_bs16ts16Dd_binlc(rtDW.Sun_R, + rtb_VectorConcatenate_np, rtb_VectorConcatenate_gn, 2U); + + /* Sum: '/FLU_tg_correct' */ + rtb_y_mz = (int16_t)((int16_t)((int16_t)(rtb_MultiportSwitch_gq + rtb_X) + + rtb_MultiportSwitch_jq) + rtb_u6FLU_tg_amb_a3); + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + * Selector: '/Selector' + */ + if (rtb_y_mz > rtb_uDLookupTable7_g[rtb_DataTypeConversion1_nc - 1]) { + rtb_y_mz = rtb_uDLookupTable7_g[rtb_DataTypeConversion1_nc - 1]; + } else { + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * Constant: '/Constant2' + * Constant: '/Constant3' + * Constant: '/Constant4' + * Constant: '/Constant5' + */ + switch (rtb_timer_out) { + case 0: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_R_MIN_LV0[i]; + } + break; + + case 1: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_R_MIN_LV1[i]; + } + break; + + case 2: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_R_MIN_LV2[i]; + } + break; + + case 3: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_R_MIN_LV3[i]; + } + break; + + case 4: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_R_MIN_LV4[i]; + } + break; + + default: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_R_MIN_LV5[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* Selector: '/Selector' */ + rtb_FLU_tg_correct_aa = rtb_uDLookupTable7_g[rtb_DataTypeConversion1_nc - 1]; + + /* Switch: '/Switch' incorporates: + * RelationalOperator: '/UpperRelop' + * Selector: '/Selector' + */ + if (rtb_y_mz < rtb_FLU_tg_correct_aa) { + rtb_y_mz = rtb_FLU_tg_correct_aa; + } + + /* End of Switch: '/Switch' */ + } + + /* End of Switch: '/Switch2' */ + + /* Switch: '/Switch2' incorporates: + * Constant: '/Constant12' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read76' + */ + if (rtDW.CCU_AC_MAX > 0) { + i = 5; + } else { + i = rtDW.CCU_AUTOMODE_RR; + } + + /* MATLAB Function: '/func g_assAUTO_STEP_DUCT_TG_R' incorporates: + * DataStoreRead: '/Data Store Read20' + * Switch: '/Switch2' + */ + funcg_assAUTO_STEP_DUCT_TG_R(rtDW.LEVEL, (double)i, &rtb_y_co); + + /* Switch: '/Switch' incorporates: + * Constant: '/manual' + * DataStoreRead: '/Data Store Read46' + * DataStoreWrite: '/Data Store Write3' + * RelationalOperator: '/Equal1' + * Sum: '/Add' + */ + if (rtDW.CCU_MODE_RR != 0) { + rtb_y_mz += rtb_y_co; + } + + /* End of Switch: '/Switch' */ + + /* Switch: '/Switch15' incorporates: + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read44' + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write5' + * DataStoreWrite: '/Data Store Write3' + * If: '/If' + * Logic: '/Logical Operator' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * SignalConversion generated from: '/dtg' + */ + if (rtDW.LO_HI_MODE_RR > 1) { + rtDW.Duct_RR_Tg = 800; + } else if ((rtDW.step_start_controle_rear == 0) || + (rtDW.step_start_controle_rear == 1) || + (rtDW.step_start_controle_rear == 2)) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem' incorporates: + * ActionPort: '/Action Port' + */ + /* If: '/If' incorporates: + * DataStoreRead: '/dtg from Start Control' + * DataStoreWrite: '/Data Store Write5' + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.Duct_RR_Tg = (int16_t)rtDW.Dtg_RR; + + /* End of Outputs for SubSystem: '/If Action Subsystem' */ + } else { + /* Outputs for IfAction SubSystem: '/If Action Subsystem1' incorporates: + * ActionPort: '/Action Port' + */ + rtDW.Duct_RR_Tg = rtb_y_mz; + + /* End of Outputs for SubSystem: '/If Action Subsystem1' */ + } + + /* End of Switch: '/Switch15' */ + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * Constant: '/Constant2' + * Constant: '/Constant3' + * Constant: '/Constant4' + * Constant: '/Constant5' + */ + switch (rtb_timer_out) { + case 0: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MAX_LV0[i]; + } + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Constant: '/Constant' + * Lookup_n-D: '/1-D Lookup Table' + * Saturate: '/Saturation' + */ + rtb_u6FLU_tg_amb_g = look1_iu16bs16lu64n32ts16Ds32_binlcs(Gain, + rtConstP.pooled51, &g_assTG_FLL_LV0[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table' + * Saturate: '/Saturation' + */ + rtb_u5FLU_tg_incar_i = look1_iu16bs16lu64n32ts16Ds32_binlcs(Gain, + rtConstP.pooled51, &g_assINCAR_TG_FL_LV0[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[0] = + g_assDTG_FL_INC_Y1_LV0[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[1] = + g_assDTG_FL_INC_Y2_LV0[rtb_DataTypeConversion3_i - 1]; + break; + + case 1: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MAX_LV1[i]; + } + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Constant: '/Constant1' + * Lookup_n-D: '/1-D Lookup Table1' + * Saturate: '/Saturation' + */ + rtb_u6FLU_tg_amb_g = look1_iu16bs16lu64n32ts16Ds32_binlcs(Gain, + rtConstP.pooled51, &g_assTG_FLL_LV1[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table1' + * Saturate: '/Saturation' + */ + rtb_u5FLU_tg_incar_i = look1_iu16bs16lu64n32ts16Ds32_binlcs(Gain, + rtConstP.pooled51, &g_assINCAR_TG_FL_LV1[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[0] = + g_assDTG_FL_INC_Y1_LV1[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[1] = + g_assDTG_FL_INC_Y2_LV1[rtb_DataTypeConversion3_i - 1]; + break; + + case 2: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MAX_LV2[i]; + } + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Constant: '/Constant2' + * Lookup_n-D: '/1-D Lookup Table2' + * Saturate: '/Saturation' + */ + rtb_u6FLU_tg_amb_g = look1_iu16bs16lu64n32ts16Ds32_binlcs(Gain, + rtConstP.pooled51, &g_assTG_FLL_LV2[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table2' + * Saturate: '/Saturation' + */ + rtb_u5FLU_tg_incar_i = look1_iu16bs16lu64n32ts16Ds32_binlcs(Gain, + rtConstP.pooled51, &g_assINCAR_TG_FL_LV2[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[0] = + g_assDTG_FL_INC_Y1_LV2[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[1] = + g_assDTG_FL_INC_Y2_LV2[rtb_DataTypeConversion3_i - 1]; + break; + + case 3: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MAX_LV3[i]; + } + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Constant: '/Constant3' + * Lookup_n-D: '/1-D Lookup Table3' + * Saturate: '/Saturation' + */ + rtb_u6FLU_tg_amb_g = look1_iu16bs16lu64n32ts16Ds32_binlcs(Gain, + rtConstP.pooled51, &g_assTG_FLL_LV3[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table3' + * Saturate: '/Saturation' + */ + rtb_u5FLU_tg_incar_i = look1_iu16bs16lu64n32ts16Ds32_binlcs(Gain, + rtConstP.pooled51, &g_assINCAR_TG_FL_LV3[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[0] = + g_assDTG_FL_INC_Y1_LV3[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[1] = + g_assDTG_FL_INC_Y2_LV3[rtb_DataTypeConversion3_i - 1]; + break; + + case 4: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MAX_LV4[i]; + } + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Constant: '/Constant4' + * Lookup_n-D: '/1-D Lookup Table4' + * Saturate: '/Saturation' + */ + rtb_u6FLU_tg_amb_g = look1_iu16bs16lu64n32ts16Ds32_binlcs(Gain, + rtConstP.pooled51, &g_assTG_FLL_LV4[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table4' + * Saturate: '/Saturation' + */ + rtb_u5FLU_tg_incar_i = look1_iu16bs16lu64n32ts16Ds32_binlcs(Gain, + rtConstP.pooled51, &g_assINCAR_TG_FL_LV4[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[0] = + g_assDTG_FL_INC_Y1_LV4[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[1] = + g_assDTG_FL_INC_Y2_LV4[rtb_DataTypeConversion3_i - 1]; + break; + + default: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MAX_LV5[i]; + } + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Constant: '/Constant5' + * Lookup_n-D: '/1-D Lookup Table5' + * Saturate: '/Saturation' + */ + rtb_u6FLU_tg_amb_g = look1_iu16bs16lu64n32ts16Ds32_binlcs(Gain, + rtConstP.pooled51, &g_assTG_FLL_LV5[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table5' + * Saturate: '/Saturation' + */ + rtb_u5FLU_tg_incar_i = look1_iu16bs16lu64n32ts16Ds32_binlcs(Gain, + rtConstP.pooled51, &g_assINCAR_TG_FL_LV5[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[0] = + g_assDTG_FL_INC_Y1_LV5[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[1] = + g_assDTG_FL_INC_Y2_LV5[rtb_DataTypeConversion3_i - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_by[2] = 0; + + /* MultiPortSwitch: '/Multiport Switch3' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant14' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[3] = + g_assDTG_FL_INC_Y3_LV0[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant20' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[4] = + g_assDTG_FL_INC_Y4_LV0[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[0] = + g_assDTG_FU_INC_X1_LV0[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[1] = + g_assDTG_FU_INC_X2_LV0[rtb_DataTypeConversion3_i - 1]; + break; + + case 1: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant15' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[3] = + g_assDTG_FL_INC_Y3_LV1[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant21' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[4] = + g_assDTG_FL_INC_Y4_LV1[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[0] = + g_assDTG_FU_INC_X1_LV1[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[1] = + g_assDTG_FU_INC_X2_LV1[rtb_DataTypeConversion3_i - 1]; + break; + + case 2: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant16' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[3] = + g_assDTG_FL_INC_Y3_LV2[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant22' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[4] = + g_assDTG_FL_INC_Y4_LV2[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[0] = + g_assDTG_FU_INC_X1_LV2[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[1] = + g_assDTG_FU_INC_X2_LV2[rtb_DataTypeConversion3_i - 1]; + break; + + case 3: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant17' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[3] = + g_assDTG_FL_INC_Y3_LV3[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant23' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[4] = + g_assDTG_FL_INC_Y4_LV3[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[0] = + g_assDTG_FU_INC_X1_LV3[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[1] = + g_assDTG_FU_INC_X2_LV3[rtb_DataTypeConversion3_i - 1]; + break; + + case 4: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant12' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[3] = + g_assDTG_FL_INC_Y3_LV4[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant18' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[4] = + g_assDTG_FL_INC_Y4_LV4[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[0] = + g_assDTG_FU_INC_X1_LV4[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[1] = + g_assDTG_FU_INC_X2_LV4[rtb_DataTypeConversion3_i - 1]; + break; + + default: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant13' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[3] = + g_assDTG_FL_INC_Y3_LV5[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant19' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[4] = + g_assDTG_FL_INC_Y4_LV5[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[0] = + g_assDTG_FU_INC_X1_LV5[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[1] = + g_assDTG_FU_INC_X2_LV5[rtb_DataTypeConversion3_i - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch3' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_kz[2] = 0; + + /* MultiPortSwitch: '/Multiport Switch3' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant14' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[3] = + g_assDTG_FU_INC_X3_LV0[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant20' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[4] = + g_assDTG_FU_INC_X4_LV0[rtb_DataTypeConversion3_i - 1]; + break; + + case 1: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant15' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[3] = + g_assDTG_FU_INC_X3_LV1[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant21' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[4] = + g_assDTG_FU_INC_X4_LV1[rtb_DataTypeConversion3_i - 1]; + break; + + case 2: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant16' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[3] = + g_assDTG_FU_INC_X3_LV2[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant22' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[4] = + g_assDTG_FU_INC_X4_LV2[rtb_DataTypeConversion3_i - 1]; + break; + + case 3: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant17' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[3] = + g_assDTG_FU_INC_X3_LV3[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant23' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[4] = + g_assDTG_FU_INC_X4_LV3[rtb_DataTypeConversion3_i - 1]; + break; + + case 4: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant12' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[3] = + g_assDTG_FU_INC_X3_LV4[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant18' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[4] = + g_assDTG_FU_INC_X4_LV4[rtb_DataTypeConversion3_i - 1]; + break; + + default: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant13' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[3] = + g_assDTG_FU_INC_X3_LV5[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant19' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[4] = + g_assDTG_FU_INC_X4_LV5[rtb_DataTypeConversion3_i - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch3' */ + + /* Lookup_n-D: '/2.5 FLL_tg_incar' incorporates: + * DataStoreRead: '/Data Store Read21' + * Sum: '/2.5. X = Inc_Tg - Incar_fb' + */ + rtb_MultiportSwitch_pa = look1_is16lu64n32Ds32_binlcn((int16_t) + (rtb_u5FLU_tg_incar_i - rtDW.Incar_FL), rtb_VectorConcatenate_kz, + rtb_VectorConcatenate_by, 4U); + + /* MultiPortSwitch: '/Multiport Switch1' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[0] = + g_assDTG_FL_AMB_Y1_LV0[rtb_DataTypeConversion3_i - 1]; + break; + + case 1: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[0] = + g_assDTG_FL_AMB_Y1_LV1[rtb_DataTypeConversion3_i - 1]; + break; + + case 2: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[0] = + g_assDTG_FL_AMB_Y1_LV2[rtb_DataTypeConversion3_i - 1]; + break; + + case 3: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[0] = + g_assDTG_FL_AMB_Y1_LV3[rtb_DataTypeConversion3_i - 1]; + break; + + case 4: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[0] = + g_assDTG_FL_AMB_Y1_LV4[rtb_DataTypeConversion3_i - 1]; + break; + + default: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[0] = + g_assDTG_FL_AMB_Y1_LV5[rtb_DataTypeConversion3_i - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_dw[1] = 0; + + /* MultiPortSwitch: '/Multiport Switch2' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[2] = + g_assDTG_FL_AMB_Y2_LV0[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[0] = + g_assDTG_FL_AMB_X1_LV0[rtb_DataTypeConversion3_i - 1]; + break; + + case 1: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[2] = + g_assDTG_FL_AMB_Y2_LV1[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[0] = + g_assDTG_FL_AMB_X1_LV1[rtb_DataTypeConversion3_i - 1]; + break; + + case 2: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[2] = + g_assDTG_FL_AMB_Y2_LV2[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[0] = + g_assDTG_FL_AMB_X1_LV2[rtb_DataTypeConversion3_i - 1]; + break; + + case 3: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[2] = + g_assDTG_FL_AMB_Y2_LV3[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[0] = + g_assDTG_FL_AMB_X1_LV3[rtb_DataTypeConversion3_i - 1]; + break; + + case 4: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[2] = + g_assDTG_FL_AMB_Y2_LV4[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[0] = + g_assDTG_FL_AMB_X1_LV4[rtb_DataTypeConversion3_i - 1]; + break; + + default: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[2] = + g_assDTG_FL_AMB_Y2_LV5[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[0] = + g_assDTG_FL_AMB_X1_LV5[rtb_DataTypeConversion3_i - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch2' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_pg[1] = 0; + + /* MultiPortSwitch: '/Multiport Switch2' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[2] = + g_assDTG_FL_AMB_X2_LV0[rtb_DataTypeConversion3_i - 1]; + break; + + case 1: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[2] = + g_assDTG_FL_AMB_X2_LV1[rtb_DataTypeConversion3_i - 1]; + break; + + case 2: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[2] = + g_assDTG_FL_AMB_X2_LV2[rtb_DataTypeConversion3_i - 1]; + break; + + case 3: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[2] = + g_assDTG_FL_AMB_X2_LV3[rtb_DataTypeConversion3_i - 1]; + break; + + case 4: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[2] = + g_assDTG_FL_AMB_X2_LV4[rtb_DataTypeConversion3_i - 1]; + break; + + default: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[2] = + g_assDTG_FL_AMB_X2_LV5[rtb_DataTypeConversion3_i - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch2' */ + + /* Lookup_n-D: '/2.6 FLL_tg_amb' */ + rtb_MultiportSwitch1_g = look1_is16lu64n32Ds32_binlcn(rtb_Bias5, + rtb_VectorConcatenate_pg, rtb_VectorConcatenate_dw, 2U); + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_gn[0] = 0; + + /* MultiPortSwitch: '/Multiport Switch1' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[1] = + g_assDTG_FL_SUN_Y1_LV0[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = + g_assDTG_FL_SUN_Y2_LV0[rtb_DataTypeConversion3_i - 1]; + break; + + case 1: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[1] = + g_assDTG_FL_SUN_Y1_LV1[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = + g_assDTG_FL_SUN_Y2_LV1[rtb_DataTypeConversion3_i - 1]; + break; + + case 2: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[1] = + g_assDTG_FL_SUN_Y1_LV2[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = + g_assDTG_FL_SUN_Y2_LV2[rtb_DataTypeConversion3_i - 1]; + break; + + case 3: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[1] = + g_assDTG_FL_SUN_Y1_LV3[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = + g_assDTG_FL_SUN_Y2_LV3[rtb_DataTypeConversion3_i - 1]; + break; + + case 4: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[1] = + g_assDTG_FL_SUN_Y1_LV4[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = + g_assDTG_FL_SUN_Y2_LV4[rtb_DataTypeConversion3_i - 1]; + break; + + default: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[1] = + g_assDTG_FL_SUN_Y1_LV5[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = + g_assDTG_FL_SUN_Y2_LV5[rtb_DataTypeConversion3_i - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_np[0] = 0; + + /* MultiPortSwitch: '/Multiport Switch1' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[1] = + g_assDTG_FL_SUN_X1_LV0[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = + g_assDTG_FL_SUN_X2_LV0[rtb_DataTypeConversion3_i - 1]; + break; + + case 1: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[1] = + g_assDTG_FL_SUN_X1_LV1[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = + g_assDTG_FL_SUN_X2_LV1[rtb_DataTypeConversion3_i - 1]; + break; + + case 2: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[1] = + g_assDTG_FL_SUN_X1_LV2[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = + g_assDTG_FL_SUN_X2_LV2[rtb_DataTypeConversion3_i - 1]; + break; + + case 3: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[1] = + g_assDTG_FL_SUN_X1_LV3[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = + g_assDTG_FL_SUN_X2_LV3[rtb_DataTypeConversion3_i - 1]; + break; + + case 4: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[1] = + g_assDTG_FL_SUN_X1_LV4[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = + g_assDTG_FL_SUN_X2_LV4[rtb_DataTypeConversion3_i - 1]; + break; + + default: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * DataTypeConversion: '/Data Type Conversion1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[1] = + g_assDTG_FL_SUN_X1_LV5[rtb_DataTypeConversion3_i - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * DataTypeConversion: '/Data Type Conversion1' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = + g_assDTG_FL_SUN_X2_LV5[rtb_DataTypeConversion3_i - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* Lookup_n-D: '/2.6 FLL_tg_amb' incorporates: + * DataStoreRead: '/Data Store Read26' + */ + rtb_Bias3 = look1_bs16ts16Dd_binlc(rtDW.Sun_L, rtb_VectorConcatenate_np, + rtb_VectorConcatenate_gn, 2U); + + /* Sum: '/FLU_tg_correct' */ + rtb_y_co = (int16_t)((int16_t)((int16_t)(rtb_u6FLU_tg_amb_g + + rtb_MultiportSwitch_pa) + rtb_MultiportSwitch1_g) + rtb_Bias3); + + /* Switch: '/Switch2' incorporates: + * DataTypeConversion: '/Data Type Conversion1' + * RelationalOperator: '/LowerRelop1' + * Selector: '/Selector' + * Selector: '/Selector' + */ + if (rtb_y_co > rtb_uDLookupTable7_g[rtb_DataTypeConversion3_i - 1]) { + rtb_y_co = rtb_uDLookupTable7_g[rtb_DataTypeConversion3_i - 1]; + } else { + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * Constant: '/Constant2' + * Constant: '/Constant3' + * Constant: '/Constant4' + * Constant: '/Constant5' + */ + switch (rtb_timer_out) { + case 0: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MIN_LV0[i]; + } + break; + + case 1: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MIN_LV1[i]; + } + break; + + case 2: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MIN_LV2[i]; + } + break; + + case 3: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MIN_LV3[i]; + } + break; + + case 4: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MIN_LV4[i]; + } + break; + + default: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MIN_LV5[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* Selector: '/Selector' */ + rtb_FLU_tg_correct_aa = rtb_uDLookupTable7_g[rtb_DataTypeConversion3_i - 1]; + + /* Switch: '/Switch' incorporates: + * RelationalOperator: '/UpperRelop' + * Selector: '/Selector' + */ + if (rtb_y_co < rtb_FLU_tg_correct_aa) { + rtb_y_co = rtb_FLU_tg_correct_aa; + } + + /* End of Switch: '/Switch' */ + } + + /* End of Switch: '/Switch2' */ + + /* Switch: '/Switch2' incorporates: + * Constant: '/Constant12' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read76' + */ + if (rtDW.CCU_AC_MAX > 0) { + i = 5; + } else { + i = rtDW.CCU_AUTOMODE_FL; + } + + /* MATLAB Function: '/func g_assAUTO_STEP_DUCT_TG_L' incorporates: + * DataStoreRead: '/Data Store Read20' + * Switch: '/Switch2' + */ + funcg_assAUTO_STEP_DUCT_TG_L(rtDW.LEVEL, (double)i, &rtb_y_ki); + + /* Switch: '/Switch' incorporates: + * Constant: '/manual' + * DataStoreRead: '/Data Store Read46' + * DataStoreWrite: '/Data Store Write4' + * RelationalOperator: '/Equal1' + * Sum: '/Add' + */ + if (rtDW.CCU_MODE_FL != 0) { + rtb_y_co += rtb_y_ki; + } + + /* End of Switch: '/Switch' */ + + /* Switch: '/Switch15' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read44' + * DataStoreWrite: '/Data Store Write6' + */ + if (rtDW.LO_HI_MODE_FL > 1) { + rtb_y_ki = 800; + } else { + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Gain: '/Gain' + * Gain: '/Gain1' + */ + index_start_0 = (int32_t)floor(((double)((int32_t)rtb_Subtract >> 19) - 15.0) + * 0.5 + 0.5); + + /* If: '/If' incorporates: + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/mode from Start Control' + * DataStoreWrite: '/Data Store Write4' + * DataTypeConversion: '/Data Type Conversion' + * Logic: '/Logical Operator' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * SignalConversion generated from: '/FXU' + * Sum: '/Sum' + */ + if ((rtDW.step_start_controle_front == 0) || (rtDW.step_start_controle_front + == 1) || (rtDW.step_start_controle_front == 2)) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem' incorporates: + * ActionPort: '/Action Port' + */ + rtb_FLU_tg_correct_aa = (int16_t)rtDW.Dtg_FLL; + + /* End of Outputs for SubSystem: '/If Action Subsystem' */ + } else { + /* Outputs for IfAction SubSystem: '/If Action Subsystem1' incorporates: + * ActionPort: '/Action Port' + */ + rtb_FLU_tg_correct_aa = rtb_y_co; + + /* End of Outputs for SubSystem: '/If Action Subsystem1' */ + } + + rtb_y_ki = (int16_t)(rtb_FLU_tg_correct_aa + rtDW.Dtg_individual_foot_FL); + + /* End of If: '/If' */ + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant1' + * Constant: '/Constant13' + * Constant: '/Constant14' + * Constant: '/Constant15' + * Constant: '/Constant16' + * Constant: '/Constant17' + */ + switch (rtb_timer_out) { + case 0: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MAX_LV0[i]; + } + break; + + case 1: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MAX_LV1[i]; + } + break; + + case 2: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MAX_LV2[i]; + } + break; + + case 3: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MAX_LV3[i]; + } + break; + + case 4: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MAX_LV4[i]; + } + break; + + default: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MAX_LV5[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* Selector: '/Selector' incorporates: + * DataTypeConversion: '/Data Type Conversion1' + */ + rtb_FLU_tg_correct_aa = rtb_uDLookupTable7_g[(uint8_t)index_start_0 - 1]; + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + * Selector: '/Selector' + */ + if (rtb_y_ki > rtb_FLU_tg_correct_aa) { + /* DataStoreWrite: '/Data Store Write6' */ + rtb_y_ki = rtb_FLU_tg_correct_aa; + } else { + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Constant: '/Constant' + * Constant: '/Constant2' + * Constant: '/Constant3' + * Constant: '/Constant4' + * Constant: '/Constant5' + * Constant: '/Constant6' + */ + switch (rtb_timer_out) { + case 0: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MIN_LV0[i]; + } + break; + + case 1: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MIN_LV1[i]; + } + break; + + case 2: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MIN_LV2[i]; + } + break; + + case 3: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MIN_LV3[i]; + } + break; + + case 4: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MIN_LV4[i]; + } + break; + + default: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MIN_LV5[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch' */ + + /* Selector: '/Selector1' incorporates: + * DataTypeConversion: '/Data Type Conversion1' + */ + rtb_FLU_tg_correct_aa = rtb_uDLookupTable7_g[(uint8_t)index_start_0 - 1]; + + /* Switch: '/Switch' incorporates: + * RelationalOperator: '/UpperRelop' + * Selector: '/Selector1' + */ + if (rtb_y_ki < rtb_FLU_tg_correct_aa) { + /* DataStoreWrite: '/Data Store Write6' */ + rtb_y_ki = rtb_FLU_tg_correct_aa; + } + + /* End of Switch: '/Switch' */ + } + + /* End of Switch: '/Switch2' */ + } + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * Constant: '/Constant2' + * Constant: '/Constant3' + * Constant: '/Constant4' + * Constant: '/Constant5' + */ + switch (rtb_timer_out) { + case 0: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MAX_LV0[i]; + } + break; + + case 1: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MAX_LV1[i]; + } + break; + + case 2: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MAX_LV2[i]; + } + break; + + case 3: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MAX_LV3[i]; + } + break; + + case 4: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MAX_LV4[i]; + } + break; + + default: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MAX_LV5[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* Selector: '/Selector' incorporates: + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_y_he = rtb_uDLookupTable7_g[CCU_FRONT_SYNC - 1]; + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table' + * Lookup_n-D: '/1-D Lookup Table1' + * Lookup_n-D: '/1-D Lookup Table2' + * Lookup_n-D: '/1-D Lookup Table3' + * Lookup_n-D: '/1-D Lookup Table4' + * Lookup_n-D: '/1-D Lookup Table5' + * Saturate: '/Saturation1' + */ + switch (rtb_timer_out) { + case 0: + rtb_Bias2_n = look1_iu16bs16lu64n32ts16Ds32_binlcs(Gain1, rtConstP.pooled51, + &g_assTG_FRL_LV0[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table' + * Lookup_n-D: '/1-D Lookup Table' + * Saturate: '/Saturation1' + */ + rtb_Bias4 = look1_iu16bs16lu64n32ts16Ds32_binlcs(Gain1, rtConstP.pooled51, + &g_assINCAR_TG_FR_LV0[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[0] = g_assDTG_FL_INC_Y1_LV0[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[1] = g_assDTG_FL_INC_Y2_LV0[CCU_FRONT_SYNC - 1]; + break; + + case 1: + rtb_Bias2_n = look1_iu16bs16lu64n32ts16Ds32_binlcs(Gain1, rtConstP.pooled51, + &g_assTG_FRL_LV1[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table1' + * Lookup_n-D: '/1-D Lookup Table1' + * Saturate: '/Saturation1' + */ + rtb_Bias4 = look1_iu16bs16lu64n32ts16Ds32_binlcs(Gain1, rtConstP.pooled51, + &g_assINCAR_TG_FR_LV1[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[0] = g_assDTG_FL_INC_Y1_LV1[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[1] = g_assDTG_FL_INC_Y2_LV1[CCU_FRONT_SYNC - 1]; + break; + + case 2: + rtb_Bias2_n = look1_iu16bs16lu64n32ts16Ds32_binlcs(Gain1, rtConstP.pooled51, + &g_assTG_FRL_LV2[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table2' + * Lookup_n-D: '/1-D Lookup Table2' + * Saturate: '/Saturation1' + */ + rtb_Bias4 = look1_iu16bs16lu64n32ts16Ds32_binlcs(Gain1, rtConstP.pooled51, + &g_assINCAR_TG_FR_LV2[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[0] = g_assDTG_FL_INC_Y1_LV2[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[1] = g_assDTG_FL_INC_Y2_LV2[CCU_FRONT_SYNC - 1]; + break; + + case 3: + rtb_Bias2_n = look1_iu16bs16lu64n32ts16Ds32_binlcs(Gain1, rtConstP.pooled51, + &g_assTG_FRL_LV3[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table3' + * Lookup_n-D: '/1-D Lookup Table3' + * Saturate: '/Saturation1' + */ + rtb_Bias4 = look1_iu16bs16lu64n32ts16Ds32_binlcs(Gain1, rtConstP.pooled51, + &g_assINCAR_TG_FR_LV3[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[0] = g_assDTG_FL_INC_Y1_LV3[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[1] = g_assDTG_FL_INC_Y2_LV3[CCU_FRONT_SYNC - 1]; + break; + + case 4: + rtb_Bias2_n = look1_iu16bs16lu64n32ts16Ds32_binlcs(Gain1, rtConstP.pooled51, + &g_assTG_FRL_LV4[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table4' + * Lookup_n-D: '/1-D Lookup Table4' + * Saturate: '/Saturation1' + */ + rtb_Bias4 = look1_iu16bs16lu64n32ts16Ds32_binlcs(Gain1, rtConstP.pooled51, + &g_assINCAR_TG_FR_LV4[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[0] = g_assDTG_FL_INC_Y1_LV4[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[1] = g_assDTG_FL_INC_Y2_LV4[CCU_FRONT_SYNC - 1]; + break; + + default: + rtb_Bias2_n = look1_iu16bs16lu64n32ts16Ds32_binlcs(Gain1, rtConstP.pooled51, + &g_assTG_FRL_LV5[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table5' + * Lookup_n-D: '/1-D Lookup Table5' + * Saturate: '/Saturation1' + */ + rtb_Bias4 = look1_iu16bs16lu64n32ts16Ds32_binlcs(Gain1, rtConstP.pooled51, + &g_assINCAR_TG_FR_LV5[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[0] = g_assDTG_FL_INC_Y1_LV5[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[1] = g_assDTG_FL_INC_Y2_LV5[CCU_FRONT_SYNC - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_by[2] = 0; + + /* MultiPortSwitch: '/Multiport Switch3' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant14' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[3] = g_assDTG_FL_INC_Y3_LV0[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant20' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[4] = g_assDTG_FL_INC_Y4_LV0[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[0] = g_assDTG_FU_INC_X1_LV0[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[1] = g_assDTG_FU_INC_X2_LV0[CCU_FRONT_SYNC - 1]; + break; + + case 1: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant15' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[3] = g_assDTG_FL_INC_Y3_LV1[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant21' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[4] = g_assDTG_FL_INC_Y4_LV1[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[0] = g_assDTG_FU_INC_X1_LV1[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[1] = g_assDTG_FU_INC_X2_LV1[CCU_FRONT_SYNC - 1]; + break; + + case 2: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant16' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[3] = g_assDTG_FL_INC_Y3_LV2[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant22' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[4] = g_assDTG_FL_INC_Y4_LV2[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[0] = g_assDTG_FU_INC_X1_LV2[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[1] = g_assDTG_FU_INC_X2_LV2[CCU_FRONT_SYNC - 1]; + break; + + case 3: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant17' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[3] = g_assDTG_FL_INC_Y3_LV3[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant23' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[4] = g_assDTG_FL_INC_Y4_LV3[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[0] = g_assDTG_FU_INC_X1_LV3[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[1] = g_assDTG_FU_INC_X2_LV3[CCU_FRONT_SYNC - 1]; + break; + + case 4: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant12' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[3] = g_assDTG_FL_INC_Y3_LV4[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant18' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[4] = g_assDTG_FL_INC_Y4_LV4[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[0] = g_assDTG_FU_INC_X1_LV4[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[1] = g_assDTG_FU_INC_X2_LV4[CCU_FRONT_SYNC - 1]; + break; + + default: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant13' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[3] = g_assDTG_FL_INC_Y3_LV5[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant19' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_by[4] = g_assDTG_FL_INC_Y4_LV5[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[0] = g_assDTG_FU_INC_X1_LV5[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[1] = g_assDTG_FU_INC_X2_LV5[CCU_FRONT_SYNC - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch3' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_kz[2] = 0; + + /* MultiPortSwitch: '/Multiport Switch3' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant14' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[3] = g_assDTG_FU_INC_X3_LV0[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant20' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[4] = g_assDTG_FU_INC_X4_LV0[CCU_FRONT_SYNC - 1]; + break; + + case 1: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant15' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[3] = g_assDTG_FU_INC_X3_LV1[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant21' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[4] = g_assDTG_FU_INC_X4_LV1[CCU_FRONT_SYNC - 1]; + break; + + case 2: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant16' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[3] = g_assDTG_FU_INC_X3_LV2[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant22' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[4] = g_assDTG_FU_INC_X4_LV2[CCU_FRONT_SYNC - 1]; + break; + + case 3: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant17' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[3] = g_assDTG_FU_INC_X3_LV3[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant23' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[4] = g_assDTG_FU_INC_X4_LV3[CCU_FRONT_SYNC - 1]; + break; + + case 4: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant12' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[3] = g_assDTG_FU_INC_X3_LV4[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant18' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[4] = g_assDTG_FU_INC_X4_LV4[CCU_FRONT_SYNC - 1]; + break; + + default: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant13' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[3] = g_assDTG_FU_INC_X3_LV5[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant19' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_kz[4] = g_assDTG_FU_INC_X4_LV5[CCU_FRONT_SYNC - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch3' */ + + /* Lookup_n-D: '/2.5 FRL_tg_incar' incorporates: + * DataStoreRead: '/Data Store Read22' + * Sum: '/2.5. X = Inc_Tg - Incar_fb' + */ + rtb_Bias1_h = look1_is16lu64n32Ds32_binlcn((int16_t)(rtb_Bias4 - rtDW.Incar_FR), + rtb_VectorConcatenate_kz, rtb_VectorConcatenate_by, 4U); + + /* MultiPortSwitch: '/Multiport Switch1' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[0] = g_assDTG_FL_AMB_Y1_LV0[CCU_FRONT_SYNC - 1]; + break; + + case 1: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[0] = g_assDTG_FL_AMB_Y1_LV1[CCU_FRONT_SYNC - 1]; + break; + + case 2: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[0] = g_assDTG_FL_AMB_Y1_LV2[CCU_FRONT_SYNC - 1]; + break; + + case 3: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[0] = g_assDTG_FL_AMB_Y1_LV3[CCU_FRONT_SYNC - 1]; + break; + + case 4: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[0] = g_assDTG_FL_AMB_Y1_LV4[CCU_FRONT_SYNC - 1]; + break; + + default: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[0] = g_assDTG_FL_AMB_Y1_LV5[CCU_FRONT_SYNC - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_dw[1] = 0; + + /* MultiPortSwitch: '/Multiport Switch2' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[2] = g_assDTG_FL_AMB_Y2_LV0[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[0] = g_assDTG_FL_AMB_X1_LV0[CCU_FRONT_SYNC - 1]; + break; + + case 1: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[2] = g_assDTG_FL_AMB_Y2_LV1[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[0] = g_assDTG_FL_AMB_X1_LV1[CCU_FRONT_SYNC - 1]; + break; + + case 2: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[2] = g_assDTG_FL_AMB_Y2_LV2[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[0] = g_assDTG_FL_AMB_X1_LV2[CCU_FRONT_SYNC - 1]; + break; + + case 3: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[2] = g_assDTG_FL_AMB_Y2_LV3[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[0] = g_assDTG_FL_AMB_X1_LV3[CCU_FRONT_SYNC - 1]; + break; + + case 4: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[2] = g_assDTG_FL_AMB_Y2_LV4[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[0] = g_assDTG_FL_AMB_X1_LV4[CCU_FRONT_SYNC - 1]; + break; + + default: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[2] = g_assDTG_FL_AMB_Y2_LV5[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[0] = g_assDTG_FL_AMB_X1_LV5[CCU_FRONT_SYNC - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch2' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_pg[1] = 0; + + /* MultiPortSwitch: '/Multiport Switch2' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[2] = g_assDTG_FL_AMB_X2_LV0[CCU_FRONT_SYNC - 1]; + break; + + case 1: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[2] = g_assDTG_FL_AMB_X2_LV1[CCU_FRONT_SYNC - 1]; + break; + + case 2: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[2] = g_assDTG_FL_AMB_X2_LV2[CCU_FRONT_SYNC - 1]; + break; + + case 3: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[2] = g_assDTG_FL_AMB_X2_LV3[CCU_FRONT_SYNC - 1]; + break; + + case 4: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[2] = g_assDTG_FL_AMB_X2_LV4[CCU_FRONT_SYNC - 1]; + break; + + default: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[2] = g_assDTG_FL_AMB_X2_LV5[CCU_FRONT_SYNC - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch2' */ + + /* Lookup_n-D: '/2.6 FLL_tg_amb' */ + rtb_Bias_ct = look1_is16lu64n32Ds32_binlcn(rtb_Bias5, rtb_VectorConcatenate_pg, + rtb_VectorConcatenate_dw, 2U); + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_gn[0] = 0; + + /* MultiPortSwitch: '/Multiport Switch1' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[1] = g_assDTG_FL_SUN_Y1_LV0[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = g_assDTG_FL_SUN_Y2_LV0[CCU_FRONT_SYNC - 1]; + break; + + case 1: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[1] = g_assDTG_FL_SUN_Y1_LV1[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = g_assDTG_FL_SUN_Y2_LV1[CCU_FRONT_SYNC - 1]; + break; + + case 2: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[1] = g_assDTG_FL_SUN_Y1_LV2[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = g_assDTG_FL_SUN_Y2_LV2[CCU_FRONT_SYNC - 1]; + break; + + case 3: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[1] = g_assDTG_FL_SUN_Y1_LV3[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = g_assDTG_FL_SUN_Y2_LV3[CCU_FRONT_SYNC - 1]; + break; + + case 4: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[1] = g_assDTG_FL_SUN_Y1_LV4[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = g_assDTG_FL_SUN_Y2_LV4[CCU_FRONT_SYNC - 1]; + break; + + default: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[1] = g_assDTG_FL_SUN_Y1_LV5[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = g_assDTG_FL_SUN_Y2_LV5[CCU_FRONT_SYNC - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_np[0] = 0; + + /* MultiPortSwitch: '/Multiport Switch1' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[1] = g_assDTG_FL_SUN_X1_LV0[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = g_assDTG_FL_SUN_X2_LV0[CCU_FRONT_SYNC - 1]; + break; + + case 1: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[1] = g_assDTG_FL_SUN_X1_LV1[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = g_assDTG_FL_SUN_X2_LV1[CCU_FRONT_SYNC - 1]; + break; + + case 2: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[1] = g_assDTG_FL_SUN_X1_LV2[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = g_assDTG_FL_SUN_X2_LV2[CCU_FRONT_SYNC - 1]; + break; + + case 3: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[1] = g_assDTG_FL_SUN_X1_LV3[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = g_assDTG_FL_SUN_X2_LV3[CCU_FRONT_SYNC - 1]; + break; + + case 4: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[1] = g_assDTG_FL_SUN_X1_LV4[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = g_assDTG_FL_SUN_X2_LV4[CCU_FRONT_SYNC - 1]; + break; + + default: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[1] = g_assDTG_FL_SUN_X1_LV5[CCU_FRONT_SYNC - 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * DataTypeConversion: '/Data Type Conversion2' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = g_assDTG_FL_SUN_X2_LV5[CCU_FRONT_SYNC - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* Lookup_n-D: '/2.6 FLL_tg_amb' incorporates: + * DataStoreRead: '/Data Store Read27' + */ + rtb_Bias5 = look1_bs16ts16Dd_binlc(rtDW.Sun_R, rtb_VectorConcatenate_np, + rtb_VectorConcatenate_gn, 2U); + + /* Sum: '/FLU_tg_correct' */ + rtb_FLU_tg_correct_ot = (int16_t)((int16_t)((int16_t)(rtb_Bias2_n + + rtb_Bias1_h) + rtb_Bias_ct) + rtb_Bias5); + + /* Switch: '/Switch2' incorporates: + * DataTypeConversion: '/Data Type Conversion2' + * RelationalOperator: '/LowerRelop1' + * Selector: '/Selector' + * Selector: '/Selector' + */ + if (rtb_FLU_tg_correct_ot > rtb_y_he) { + rtb_FLU_tg_correct_ot = rtb_uDLookupTable7_g[CCU_FRONT_SYNC - 1]; + } else { + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * Constant: '/Constant2' + * Constant: '/Constant3' + * Constant: '/Constant4' + * Constant: '/Constant5' + */ + switch (rtb_timer_out) { + case 0: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MIN_LV0[i]; + } + break; + + case 1: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MIN_LV1[i]; + } + break; + + case 2: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MIN_LV2[i]; + } + break; + + case 3: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MIN_LV3[i]; + } + break; + + case 4: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MIN_LV4[i]; + } + break; + + default: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MIN_LV5[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* Selector: '/Selector' incorporates: + * DataTypeConversion: '/Data Type Conversion2' + * Selector: '/Selector' + */ + rtb_FLU_tg_correct_aa = rtb_uDLookupTable7_g[CCU_FRONT_SYNC - 1]; + + /* Switch: '/Switch' incorporates: + * RelationalOperator: '/UpperRelop' + * Selector: '/Selector' + */ + if (rtb_FLU_tg_correct_ot < rtb_FLU_tg_correct_aa) { + rtb_FLU_tg_correct_ot = rtb_FLU_tg_correct_aa; + } + + /* End of Switch: '/Switch' */ + } + + /* End of Switch: '/Switch2' */ + + /* Switch: '/Switch2' incorporates: + * Constant: '/Constant12' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read76' + */ + if (rtDW.CCU_AC_MAX > 0) { + i = 5; + } else { + i = rtDW.CCU_AUTOMODE_FR; + } + + /* MATLAB Function: '/func g_assAUTO_STEP_DUCT_TG_L' incorporates: + * DataStoreRead: '/Data Store Read20' + * Switch: '/Switch2' + */ + funcg_assAUTO_STEP_DUCT_TG_L(rtDW.LEVEL, (double)i, &rtb_y_he); + + /* Switch: '/Switch15' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read44' + * DataStoreWrite: '/Data Store Write7' + */ + if (rtDW.LO_HI_MODE_FR > 1) { + rtb_y_he = 800; + } else { + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Gain: '/Gain' + * Gain: '/Gain1' + */ + index_start_0 = (int32_t)floor(((double)((int32_t)rtb_Subtract >> 19) - 15.0) + * 0.5 + 0.5); + + /* If: '/If' incorporates: + * Constant: '/manual' + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read46' + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/mode from Start Control' + * DataTypeConversion: '/Data Type Conversion' + * Logic: '/Logical Operator' + * RelationalOperator: '/Equal1' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * Sum: '/Sum' + * Sum: '/Add' + * Switch: '/Switch' + */ + if ((rtDW.step_start_controle_front == 0) || (rtDW.step_start_controle_front + == 1) || (rtDW.step_start_controle_front == 2)) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem' incorporates: + * ActionPort: '/Action Port' + */ + rtb_FLU_tg_correct_ot = (int16_t)rtDW.Dtg_FLR; + + /* End of Outputs for SubSystem: '/If Action Subsystem' */ + } else if (rtDW.CCU_MODE_FR != 0) { + rtb_FLU_tg_correct_ot += rtb_y_he; + } + + rtb_y_he = (int16_t)(rtb_FLU_tg_correct_ot + rtDW.Dtg_individual_foot_FR); + + /* End of If: '/If' */ + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant1' + * Constant: '/Constant13' + * Constant: '/Constant14' + * Constant: '/Constant15' + * Constant: '/Constant16' + * Constant: '/Constant17' + */ + switch (rtb_timer_out) { + case 0: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MAX_LV0[i]; + } + break; + + case 1: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MAX_LV1[i]; + } + break; + + case 2: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MAX_LV2[i]; + } + break; + + case 3: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MAX_LV3[i]; + } + break; + + case 4: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MAX_LV4[i]; + } + break; + + default: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MAX_LV5[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* Selector: '/Selector' incorporates: + * DataTypeConversion: '/Data Type Conversion1' + */ + rtb_FLU_tg_correct_aa = rtb_uDLookupTable7_g[(uint8_t)index_start_0 - 1]; + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + * Selector: '/Selector' + */ + if (rtb_y_he > rtb_FLU_tg_correct_aa) { + /* DataStoreWrite: '/Data Store Write7' */ + rtb_y_he = rtb_FLU_tg_correct_aa; + } else { + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Constant: '/Constant' + * Constant: '/Constant2' + * Constant: '/Constant3' + * Constant: '/Constant4' + * Constant: '/Constant5' + * Constant: '/Constant6' + */ + switch (rtb_timer_out) { + case 0: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MIN_LV0[i]; + } + break; + + case 1: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MIN_LV1[i]; + } + break; + + case 2: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MIN_LV2[i]; + } + break; + + case 3: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MIN_LV3[i]; + } + break; + + case 4: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MIN_LV4[i]; + } + break; + + default: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assDTG_FL_MIN_LV5[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch' */ + + /* Selector: '/Selector1' incorporates: + * DataTypeConversion: '/Data Type Conversion1' + */ + rtb_FLU_tg_correct_aa = rtb_uDLookupTable7_g[(uint8_t)index_start_0 - 1]; + + /* Switch: '/Switch' incorporates: + * RelationalOperator: '/UpperRelop' + * Selector: '/Selector1' + */ + if (rtb_y_he < rtb_FLU_tg_correct_aa) { + /* DataStoreWrite: '/Data Store Write7' */ + rtb_y_he = rtb_FLU_tg_correct_aa; + } + + /* End of Switch: '/Switch' */ + } + + /* End of Switch: '/Switch2' */ + } + + /* SignalConversion generated from: '/Vector Concatenate' */ + rtb_VectorConcatenate_kz[0] = rtb_u6FLU_tg_amb_g; + + /* SignalConversion generated from: '/Vector Concatenate' */ + rtb_VectorConcatenate_kz[1] = rtb_MultiportSwitch_pa; + + /* SignalConversion generated from: '/Vector Concatenate' */ + rtb_VectorConcatenate_kz[2] = rtb_MultiportSwitch1_g; + + /* SignalConversion generated from: '/Vector Concatenate' */ + rtb_VectorConcatenate_kz[3] = rtb_Bias3; + + /* SignalConversion generated from: '/Vector Concatenate' */ + rtb_VectorConcatenate_kz[4] = rtb_u5FLU_tg_incar_i; + + /* SignalConversion generated from: '/Vector Concatenate' */ + rtb_VectorConcatenate_by[0] = rtb_Bias2_n; + + /* SignalConversion generated from: '/Vector Concatenate' */ + rtb_VectorConcatenate_by[1] = rtb_Bias1_h; + + /* SignalConversion generated from: '/Vector Concatenate' */ + rtb_VectorConcatenate_by[2] = rtb_Bias_ct; + + /* SignalConversion generated from: '/Vector Concatenate' */ + rtb_VectorConcatenate_by[3] = rtb_Bias5; + + /* SignalConversion generated from: '/Vector Concatenate' */ + rtb_VectorConcatenate_by[4] = rtb_Bias4; + + /* SignalConversion generated from: '/Vector Concatenate' */ + rtb_VectorConcatenate_jn[0] = rtb_MultiportSwitch_gq; + + /* SignalConversion generated from: '/Vector Concatenate' */ + rtb_VectorConcatenate_jn[1] = rtb_X; + + /* SignalConversion generated from: '/Vector Concatenate' */ + rtb_VectorConcatenate_jn[2] = rtb_MultiportSwitch_jq; + + /* SignalConversion generated from: '/Vector Concatenate' */ + rtb_VectorConcatenate_jn[3] = rtb_u6FLU_tg_amb_a3; + + /* SignalConversion generated from: '/Vector Concatenate' */ + rtb_VectorConcatenate_jn[4] = rtb_MultiportSwitch_ci; + + /* SignalConversion generated from: '/Vector Concatenate' */ + rtb_VectorConcatenate_lb[0] = rtb_MultiportSwitch_fu; + + /* SignalConversion generated from: '/Vector Concatenate' */ + rtb_VectorConcatenate_lb[1] = rtb_u5FRU_tg_incar; + + /* SignalConversion generated from: '/Vector Concatenate' */ + rtb_VectorConcatenate_lb[2] = rtb_u6FRU_tg_amb_f; + + /* SignalConversion generated from: '/Vector Concatenate' */ + rtb_VectorConcatenate_lb[3] = rtb_u6FRU_tg_amb; + + /* SignalConversion generated from: '/Vector Concatenate' */ + rtb_VectorConcatenate_lb[4] = rtb_MultiportSwitch_ev; + for (i = 0; i < 5; i++) { + /* DataStoreWrite: '/Data Store Write' */ + Duct_RR_Tg_DBG[i] = rtb_VectorConcatenate_jn[i]; + + /* DataStoreWrite: '/Data Store Write' */ + Duct_FRU_Tg_DBG[i] = rtb_VectorConcatenate_lb[i]; + } + + /* MATLAB Function: '/is_ending_with_5' */ + is_ending_with_5(Gain, &rtb_Compare_i5); + + /* MATLAB Function: '/correction rate' incorporates: + * Gain: '/Gain2' + */ + /* : correct_after_time = [g_assCORRECT_DUCT_MAX_LV0; g_assCORRECT_DUCT_MAX_LV1; g_assCORRECT_DUCT_MAX_LV2; g_assCORRECT_DUCT_MAX_LV3; g_assCORRECT_DUCT_MAX_LV4; g_assCORRECT_DUCT_MAX_LV5]; */ + /* : y = correct_after_time(LVL + 1, idivide(SET - 16 + 1, 2)); */ + correctionrate((int16_t)(rtb_dt_nx + (uint32_t)((rtb_Subtract & 262144U) != 0U)), + rtb_timer_out, &rtb_u6FLU_tg_amb_a3); + + /* MATLAB Function: '/is_ending_with_5' */ + /* : correct_after_time = [g_assCORRECT_DUCT_TIME_FL_LV0; g_assCORRECT_DUCT_TIME_FL_LV1; g_assCORRECT_DUCT_TIME_FL_LV2; g_assCORRECT_DUCT_TIME_FL_LV3; g_assCORRECT_DUCT_TIME_FL_LV4; g_assCORRECT_DUCT_TIME_FL_LV5]; */ + /* : y = correct_after_time(LVL + 1, idivide(SET - 16 + 1, 2)); */ + is_ending_with_5(Gain1, &rtb_Compare_i5); + + /* MATLAB Function: '/correction rate' incorporates: + * Gain: '/Gain2' + */ + /* : correct_after_time = [g_assCORRECT_DUCT_MAX_LV0; g_assCORRECT_DUCT_MAX_LV1; g_assCORRECT_DUCT_MAX_LV2; g_assCORRECT_DUCT_MAX_LV3; g_assCORRECT_DUCT_MAX_LV4; g_assCORRECT_DUCT_MAX_LV5]; */ + /* : y = correct_after_time(LVL + 1, idivide(SET - 16 + 1, 2)); */ + correctionrate((int16_t)(rtb_Divide4_n_tmp_tmp_0 + (uint32_t) + ((rtb_Divide4_n_tmp_tmp & 262144U) != 0U)), rtb_timer_out, + &rtb_u6FLU_tg_amb_a3); + + /* Switch: '/Switch5' incorporates: + * Constant: '/Constant12' + * DataStoreRead: '/Data Store Read11' + * DataStoreRead: '/Data Store Read76' + */ + /* : correct_after_time = [g_assCORRECT_DUCT_TIME_FR_LV0; g_assCORRECT_DUCT_TIME_FR_LV1; g_assCORRECT_DUCT_TIME_FR_LV2; g_assCORRECT_DUCT_TIME_FR_LV3; g_assCORRECT_DUCT_TIME_FR_LV4; g_assCORRECT_DUCT_TIME_FR_LV5]; */ + /* : y = correct_after_time(LVL + 1, idivide(SET - 16 + 1, 2)); */ + if (rtDW.CCU_AC_MAX > 0) { + i = 7; + } else { + i = rtDW.CCU_BLOWERS_FL; + } + + /* End of Switch: '/Switch5' */ + + /* Outputs for Enabled SubSystem: '/Front Left AF - manual directions' incorporates: + * EnablePort: '/Enable' + */ + /* RelationalOperator: '/Equal2' incorporates: + * Constant: '/Constant2' + * DataStoreRead: '/Data Store Read44' + */ + if (rtDW.CCU_MODE_FL == 0) { + /* MATLAB Function: '/AF for Bi Level' incorporates: + * DataTypeConversion: '/Data Type Conversion6' + */ + AFforBiLevel((uint8_t)i, &Gain); + + /* MATLAB Function: '/AF for Def' incorporates: + * DataTypeConversion: '/Data Type Conversion6' + */ + AFforDef((uint8_t)i, &Gain1); + + /* MATLAB Function: '/AF for Foor + Def' incorporates: + * DataTypeConversion: '/Data Type Conversion6' + */ + AFforFoorDef((uint8_t)i, &rtb_Saturation2_a); + + /* MATLAB Function: '/AF for Foot' incorporates: + * DataTypeConversion: '/Data Type Conversion6' + */ + AFforFoot((uint8_t)i, &rtb_out_ew); + + /* MATLAB Function: '/AF for Hi_Level' incorporates: + * DataTypeConversion: '/Data Type Conversion6' + */ + AFforHi_Level((uint8_t)i, &rtb_out_nc); + + /* MATLAB Function: '/AF for Tri-Level' incorporates: + * DataTypeConversion: '/Data Type Conversion6' + */ + AFforTriLevel((uint8_t)i, &rtB.MultiportSwitch_cy); + + /* MATLAB Function: '/AF for Vent mode' incorporates: + * DataTypeConversion: '/Data Type Conversion6' + */ + AFforVentmode((uint8_t)i, &rtb_out_h0); + + /* RelationalOperator: '/Relational Operator2' incorporates: + * Constant: '/Constant2' + * DataStoreRead: '/Data Store Read9' + */ + rtb_Compare_i5 = (rtDW.CCU_FOOT_FL == 1); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read6' + * DataStoreRead: '/Data Store Read8' + * DataTypeConversion: '/Data Type Conversion5' + * Gain: '/Gain1' + * Gain: '/Gain2' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator1' + * Sum: '/Add' + */ + switch ((int32_t)(((uint32_t)((rtDW.CCU_FACE_FL == 1) << 1) + (uint32_t) + (rtDW.CCU_DEF_FL == 1)) + (uint32_t)(rtb_Compare_i5 << 2))) + { + case 0: + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Constant: '/Constant3' + */ + rtB.MultiportSwitch_cy = 0U; + break; + + case 1: + /* MultiPortSwitch: '/Multiport Switch' */ + rtB.MultiportSwitch_cy = Gain1; + break; + + case 2: + /* MultiPortSwitch: '/Multiport Switch' */ + rtB.MultiportSwitch_cy = rtb_out_h0; + break; + + case 3: + /* MultiPortSwitch: '/Multiport Switch' */ + rtB.MultiportSwitch_cy = rtb_out_nc; + break; + + case 4: + /* MultiPortSwitch: '/Multiport Switch' */ + rtB.MultiportSwitch_cy = rtb_out_ew; + break; + + case 5: + /* MultiPortSwitch: '/Multiport Switch' */ + rtB.MultiportSwitch_cy = rtb_Saturation2_a; + break; + + case 6: + /* MultiPortSwitch: '/Multiport Switch' */ + rtB.MultiportSwitch_cy = Gain; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch' */ + } + + /* End of RelationalOperator: '/Equal2' */ + /* End of Outputs for SubSystem: '/Front Left AF - manual directions' */ + + /* Switch: '/Switch2' incorporates: + * Constant: '/Constant12' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read76' + */ + if (rtDW.CCU_AC_MAX > 0) { + i = 5; + } else { + i = rtDW.CCU_AUTOMODE_FL; + } + + /* MATLAB Function: '/func g_ascAUTO_STEP_AF_F' incorporates: + * Switch: '/Switch2' + */ + funcg_ascAUTO_STEP_AF_F((double)i, &rtb_y_eo); + + /* Saturate: '/Saturation9' incorporates: + * DataStoreRead: '/Data Store Read42' + */ + if (rtDW.LEVEL <= 5) { + rtb_timer_out = rtDW.LEVEL; + } else { + rtb_timer_out = 5U; + } + + /* End of Saturate: '/Saturation9' */ + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * Constant: '/Constant2' + * Constant: '/Constant3' + * Constant: '/Constant4' + * Constant: '/Constant5' + */ + switch (rtb_timer_out) { + case 0: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVF_MAX_LV0[i]; + } + break; + + case 1: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVF_MAX_LV1[i]; + } + break; + + case 2: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVF_MAX_LV2[i]; + } + break; + + case 3: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVF_MAX_LV3[i]; + } + break; + + case 4: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVF_MAX_LV4[i]; + } + break; + + default: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVF_MAX_LV5[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* Saturate: '/Saturation5' incorporates: + * DataStoreRead: '/Data Store Read30' + */ + if (rtDW.CCU_SET_FL > 290) { + rtb_out_nc = 290U; + } else if (rtDW.CCU_SET_FL < 170) { + rtb_out_nc = 170U; + } else { + rtb_out_nc = rtDW.CCU_SET_FL; + } + + /* End of Saturate: '/Saturation5' */ + + /* Gain: '/Gain4' incorporates: + * Bias: '/Bias1' + * DataTypeConversion: '/Data Type Conversion4' + * Gain: '/Gain3' + * Product: '/Divide4' + */ + i = ((int32_t)((52429U * rtb_out_nc) >> 19) + -15) << 14; + + /* DataTypeConversion: '/Data Type Conversion3' incorporates: + * Product: '/Divide4' + * Saturate: '/Saturation1' + */ + rtb_DataTypeConversion3_i = (uint8_t)((((uint32_t)i & 16384U) != 0U) + (i >> + 15)); + + /* Selector: '/Selector' */ + rtb_Bias5 = rtb_uDLookupTable7_g[rtb_DataTypeConversion3_i - 1]; + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Lookup_n-D: '/1-D Lookup Table10' + * Lookup_n-D: '/1-D Lookup Table11' + * Lookup_n-D: '/1-D Lookup Table6' + * Lookup_n-D: '/1-D Lookup Table7' + * Lookup_n-D: '/1-D Lookup Table8' + * Lookup_n-D: '/1-D Lookup Table9' + * Saturate: '/Saturation5' + */ + switch (rtb_timer_out) { + case 0: + rtb_Bias_ct = look1_iu16lu64n48ts16Ds32_binlcs(rtb_out_nc, rtConstP.pooled79, + &g_assVTG_FL_LV0[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table6' + * Lookup_n-D: '/1-D Lookup Table' + * Saturate: '/Saturation5' + */ + rtb_Bias1_h = look1_iu16bs16lu64n32ts16Ds32_binlcs(rtb_out_nc, + rtConstP.pooled51, &g_assINCAR_TG_FL_LV0[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[0] = g_assVF_INC_Y1_LV0[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[1] = g_assVF_INC_Y2_LV0[rtb_DataTypeConversion3_i - + 1]; + break; + + case 1: + rtb_Bias_ct = look1_iu16lu64n48ts16Ds32_binlcs(rtb_out_nc, rtConstP.pooled79, + &g_assVTG_FL_LV1[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table7' + * Lookup_n-D: '/1-D Lookup Table1' + * Saturate: '/Saturation5' + */ + rtb_Bias1_h = look1_iu16bs16lu64n32ts16Ds32_binlcs(rtb_out_nc, + rtConstP.pooled51, &g_assINCAR_TG_FL_LV1[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[0] = g_assVF_INC_Y1_LV1[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[1] = g_assVF_INC_Y2_LV1[rtb_DataTypeConversion3_i - + 1]; + break; + + case 2: + rtb_Bias_ct = look1_iu16lu64n48ts16Ds32_binlcs(rtb_out_nc, rtConstP.pooled79, + &g_assVTG_FL_LV1[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table8' + * Lookup_n-D: '/1-D Lookup Table2' + * Saturate: '/Saturation5' + */ + rtb_Bias1_h = look1_iu16bs16lu64n32ts16Ds32_binlcs(rtb_out_nc, + rtConstP.pooled51, &g_assINCAR_TG_FL_LV2[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[0] = g_assVF_INC_Y1_LV2[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[1] = g_assVF_INC_Y2_LV2[rtb_DataTypeConversion3_i - + 1]; + break; + + case 3: + rtb_Bias_ct = look1_iu16lu64n48ts16Ds32_binlcs(rtb_out_nc, rtConstP.pooled79, + &g_assVTG_FL_LV3[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table9' + * Lookup_n-D: '/1-D Lookup Table3' + * Saturate: '/Saturation5' + */ + rtb_Bias1_h = look1_iu16bs16lu64n32ts16Ds32_binlcs(rtb_out_nc, + rtConstP.pooled51, &g_assINCAR_TG_FL_LV3[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[0] = g_assVF_INC_Y1_LV3[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[1] = g_assVF_INC_Y2_LV3[rtb_DataTypeConversion3_i - + 1]; + break; + + case 4: + rtb_Bias_ct = look1_iu16lu64n48ts16Ds32_binlcs(rtb_out_nc, rtConstP.pooled79, + &g_assVTG_FL_LV4[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table10' + * Lookup_n-D: '/1-D Lookup Table4' + * Saturate: '/Saturation5' + */ + rtb_Bias1_h = look1_iu16bs16lu64n32ts16Ds32_binlcs(rtb_out_nc, + rtConstP.pooled51, &g_assINCAR_TG_FL_LV4[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[0] = g_assVF_INC_Y1_LV4[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[1] = g_assVF_INC_Y2_LV4[rtb_DataTypeConversion3_i - + 1]; + break; + + default: + rtb_Bias_ct = look1_iu16lu64n48ts16Ds32_binlcs(rtb_out_nc, rtConstP.pooled79, + &g_assVTG_FL_LV5[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table11' + * Lookup_n-D: '/1-D Lookup Table5' + * Saturate: '/Saturation5' + */ + rtb_Bias1_h = look1_iu16bs16lu64n32ts16Ds32_binlcs(rtb_out_nc, + rtConstP.pooled51, &g_assINCAR_TG_FL_LV5[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[0] = g_assVF_INC_Y1_LV5[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[1] = g_assVF_INC_Y2_LV5[rtb_DataTypeConversion3_i - + 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_lb[2] = 0; + + /* MultiPortSwitch: '/Multiport Switch3' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant14' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[3] = g_assVF_INC_Y3_LV0[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant20' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[4] = g_assVF_INC_Y4_LV0[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[0] = g_assVF_INC_X1_LV0[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[1] = g_assVF_INC_X2_LV0[rtb_DataTypeConversion3_i - + 1]; + break; + + case 1: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant15' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[3] = g_assVF_INC_Y3_LV1[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant21' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[4] = g_assVF_INC_Y4_LV1[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[0] = g_assVF_INC_X1_LV1[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[1] = g_assVF_INC_X2_LV1[rtb_DataTypeConversion3_i - + 1]; + break; + + case 2: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant16' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[3] = g_assVF_INC_Y3_LV2[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant22' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[4] = g_assVF_INC_Y4_LV2[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[0] = g_assVF_INC_X1_LV2[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[1] = g_assVF_INC_X2_LV2[rtb_DataTypeConversion3_i - + 1]; + break; + + case 3: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant17' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[3] = g_assVF_INC_Y3_LV3[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant23' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[4] = g_assVF_INC_Y4_LV3[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[0] = g_assVF_INC_X1_LV3[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[1] = g_assVF_INC_X2_LV3[rtb_DataTypeConversion3_i - + 1]; + break; + + case 4: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant12' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[3] = g_assVF_INC_Y3_LV4[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant18' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[4] = g_assVF_INC_Y4_LV4[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[0] = g_assVF_INC_X1_LV4[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[1] = g_assVF_INC_X2_LV4[rtb_DataTypeConversion3_i - + 1]; + break; + + default: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant13' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[3] = g_assVF_INC_Y3_LV5[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant19' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[4] = g_assVF_INC_Y4_LV5[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[0] = g_assVF_INC_X1_LV5[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[1] = g_assVF_INC_X2_LV5[rtb_DataTypeConversion3_i - + 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch3' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_jn[2] = 0; + + /* MultiPortSwitch: '/Multiport Switch3' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant14' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[3] = g_assVF_INC_X3_LV0[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant20' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[4] = g_assVF_INC_X4_LV0[rtb_DataTypeConversion3_i - + 1]; + break; + + case 1: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant15' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[3] = g_assVF_INC_X3_LV1[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant21' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[4] = g_assVF_INC_X4_LV1[rtb_DataTypeConversion3_i - + 1]; + break; + + case 2: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant16' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[3] = g_assVF_INC_X3_LV2[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant22' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[4] = g_assVF_INC_X4_LV2[rtb_DataTypeConversion3_i - + 1]; + break; + + case 3: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant17' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[3] = g_assVF_INC_X3_LV3[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant23' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[4] = g_assVF_INC_X4_LV3[rtb_DataTypeConversion3_i - + 1]; + break; + + case 4: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant12' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[3] = g_assVF_INC_X3_LV4[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant18' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[4] = g_assVF_INC_X4_LV4[rtb_DataTypeConversion3_i - + 1]; + break; + + default: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant13' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[3] = g_assVF_INC_X3_LV5[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant19' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[4] = g_assVF_INC_X4_LV5[rtb_DataTypeConversion3_i - + 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch3' */ + + /* Lookup_n-D: '/2.5 Vtg_Fx_tg_incar' incorporates: + * DataStoreRead: '/Data Store Read35' + * Sum: '/2.5. X = Incar_Tg - Incar_fb' + */ + rtb_Bias4 = look1_is16lu64n32Ds32_binlcn((int16_t)(rtb_Bias1_h - rtDW.Incar_FL), + rtb_VectorConcatenate_jn, rtb_VectorConcatenate_lb, 4U); + + /* MultiPortSwitch: '/Multiport Switch1' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[0] = g_assVF_AMB_Y1_LV0[rtb_DataTypeConversion3_i - + 1]; + break; + + case 1: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[0] = g_assVF_AMB_Y1_LV1[rtb_DataTypeConversion3_i - + 1]; + break; + + case 2: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[0] = g_assVF_AMB_Y1_LV2[rtb_DataTypeConversion3_i - + 1]; + break; + + case 3: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[0] = g_assVF_AMB_Y1_LV3[rtb_DataTypeConversion3_i - + 1]; + break; + + case 4: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[0] = g_assVF_AMB_Y1_LV4[rtb_DataTypeConversion3_i - + 1]; + break; + + default: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[0] = g_assVF_AMB_Y1_LV5[rtb_DataTypeConversion3_i - + 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_dw[1] = 0; + + /* MultiPortSwitch: '/Multiport Switch2' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[2] = g_assVF_AMB_Y2_LV0[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[0] = g_assVF_AMB_X1_LV0[rtb_DataTypeConversion3_i - + 1]; + break; + + case 1: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[2] = g_assVF_AMB_Y2_LV1[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[0] = g_assVF_AMB_X1_LV1[rtb_DataTypeConversion3_i - + 1]; + break; + + case 2: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[2] = g_assVF_AMB_Y2_LV2[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[0] = g_assVF_AMB_X1_LV2[rtb_DataTypeConversion3_i - + 1]; + break; + + case 3: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[2] = g_assVF_AMB_Y2_LV3[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[0] = g_assVF_AMB_X1_LV3[rtb_DataTypeConversion3_i - + 1]; + break; + + case 4: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[2] = g_assVF_AMB_Y2_LV4[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[0] = g_assVF_AMB_X1_LV4[rtb_DataTypeConversion3_i - + 1]; + break; + + default: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[2] = g_assVF_AMB_Y2_LV5[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[0] = g_assVF_AMB_X1_LV5[rtb_DataTypeConversion3_i - + 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch2' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_pg[1] = 0; + + /* MultiPortSwitch: '/Multiport Switch2' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[2] = g_assVF_AMB_X2_LV0[rtb_DataTypeConversion3_i - + 1]; + break; + + case 1: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[2] = g_assVF_AMB_X2_LV1[rtb_DataTypeConversion3_i - + 1]; + break; + + case 2: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[2] = g_assVF_AMB_X2_LV2[rtb_DataTypeConversion3_i - + 1]; + break; + + case 3: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[2] = g_assVF_AMB_X2_LV3[rtb_DataTypeConversion3_i - + 1]; + break; + + case 4: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[2] = g_assVF_AMB_X2_LV4[rtb_DataTypeConversion3_i - + 1]; + break; + + default: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[2] = g_assVF_AMB_X2_LV5[rtb_DataTypeConversion3_i - + 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch2' */ + + /* Sum: '/2.6. X = Amb_Tg - Amb_Fb' incorporates: + * Bias: '/Bias1' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read34' + * Selector: '/Selector2' + * Sum: '/2.6. X = Amb_Tg - Amb_Fb' + * Sum: '/2.6. X = Amb_Tg - Amb_Fb' + * Sum: '/2.6. X = Amb_Tg - Amb_Fb' + */ + rtb_FLU_tg_correct_aa = (int16_t)(g_assAMB_LV_TG[rtb_timer_out] - rtDW.AMB); + + /* Lookup_n-D: '/2.6 Vtg_Fx_tg_amb' incorporates: + * Sum: '/2.6. X = Amb_Tg - Amb_Fb' + */ + rtb_Bias2_n = look1_is16lu64n32Ds32_binlcn(rtb_FLU_tg_correct_aa, + rtb_VectorConcatenate_pg, rtb_VectorConcatenate_dw, 2U); + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_gn[0] = 0; + + /* MultiPortSwitch: '/Multiport Switch1' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[1] = g_assVF_SUN_Y1_LV0[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = g_assVF_SUN_Y2_LV0[rtb_DataTypeConversion3_i - + 1]; + break; + + case 1: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[1] = g_assVF_SUN_Y1_LV1[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = g_assVF_SUN_Y2_LV1[rtb_DataTypeConversion3_i - + 1]; + break; + + case 2: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[1] = g_assVF_SUN_Y1_LV2[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = g_assVF_SUN_Y2_LV2[rtb_DataTypeConversion3_i - + 1]; + break; + + case 3: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[1] = g_assVF_SUN_Y1_LV3[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = g_assVF_SUN_Y2_LV3[rtb_DataTypeConversion3_i - + 1]; + break; + + case 4: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[1] = g_assVF_SUN_Y1_LV4[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = g_assVF_SUN_Y2_LV4[rtb_DataTypeConversion3_i - + 1]; + break; + + default: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[1] = g_assVF_SUN_Y1_LV5[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = g_assVF_SUN_Y2_LV5[rtb_DataTypeConversion3_i - + 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_np[0] = 0; + + /* MultiPortSwitch: '/Multiport Switch1' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[1] = g_assVF_SUN_X1_LV0[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = g_assVF_SUN_X2_LV0[rtb_DataTypeConversion3_i - + 1]; + break; + + case 1: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[1] = g_assVF_SUN_X1_LV1[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = g_assVF_SUN_X2_LV1[rtb_DataTypeConversion3_i - + 1]; + break; + + case 2: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[1] = g_assVF_SUN_X1_LV2[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = g_assVF_SUN_X2_LV2[rtb_DataTypeConversion3_i - + 1]; + break; + + case 3: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[1] = g_assVF_SUN_X1_LV3[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = g_assVF_SUN_X2_LV3[rtb_DataTypeConversion3_i - + 1]; + break; + + case 4: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[1] = g_assVF_SUN_X1_LV4[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = g_assVF_SUN_X2_LV4[rtb_DataTypeConversion3_i - + 1]; + break; + + default: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[1] = g_assVF_SUN_X1_LV5[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = g_assVF_SUN_X2_LV5[rtb_DataTypeConversion3_i - + 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* Lookup_n-D: '/2.6 Vtg_Fx_tg_amb' incorporates: + * DataStoreRead: '/Data Store Read39' + */ + rtb_Bias3 = look1_bs16ts16Dd_binlc(rtDW.Sun_L, rtb_VectorConcatenate_np, + rtb_VectorConcatenate_gn, 2U); + + /* Sum: '/2.8. Vtg_FX_plus' */ + rtb_u6FLU_tg_amb_a3 = (int16_t)((int16_t)((int16_t)(rtb_Bias_ct + rtb_Bias4) + + rtb_Bias2_n) + rtb_Bias3); + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + */ + if (rtb_u6FLU_tg_amb_a3 <= rtb_Bias5) { + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * Constant: '/Constant2' + * Constant: '/Constant3' + * Constant: '/Constant4' + * Constant: '/Constant5' + */ + switch (rtb_timer_out) { + case 0: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVF_MIN_LV0[i]; + } + break; + + case 1: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVF_MIN_LV1[i]; + } + break; + + case 2: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVF_MIN_LV2[i]; + } + break; + + case 3: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVF_MIN_LV3[i]; + } + break; + + case 4: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVF_MIN_LV4[i]; + } + break; + + default: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVF_MIN_LV5[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* Selector: '/Selector' incorporates: + * Selector: '/Selector' + */ + rtb_Bias5 = rtb_uDLookupTable7_g[rtb_DataTypeConversion3_i - 1]; + + /* Switch: '/Switch' incorporates: + * RelationalOperator: '/UpperRelop' + * Selector: '/Selector' + */ + if (rtb_u6FLU_tg_amb_a3 >= rtb_Bias5) { + rtb_Bias5 = rtb_u6FLU_tg_amb_a3; + } + + /* End of Switch: '/Switch' */ + } + + /* End of Switch: '/Switch2' */ + + /* Switch: '/Switch' incorporates: + * Constant: '/manual' + * RelationalOperator: '/Equal1' + * UnitDelay: '/Unit Delay' + */ + if (rtDW.UnitDelay_DSTATE_ne == 0) { + Gain = rtB.MultiportSwitch_cy; + } else { + /* Sum: '/Add' incorporates: + * DataTypeConversion: '/Data Type Conversion' + * DataTypeConversion: '/Data Type Conversion3' + * Gain: '/Gain' + * Product: '/Product' + */ + rtb_Add_be = 0.01 * (double)rtb_y_eo * (double)(uint16_t)rtb_Bias5 + (double) + (uint16_t)rtb_Bias5; + + /* DataTypeConversion: '/Data Type Conversion1' */ + if (fabs(rtb_Add_be) >= 0.5) { + Gain = (uint16_t)floor(rtb_Add_be + 0.5); + } else { + Gain = 0U; + } + + /* End of DataTypeConversion: '/Data Type Conversion1' */ + } + + /* End of Switch: '/Switch' */ + + /* Switch: '/Switch6' incorporates: + * Constant: '/Constant12' + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read4' + * DataStoreRead: '/Data Store Read7' + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write19' + * Logic: '/Logical Operator' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * Sum: '/Sum' + * Switch: '/Switch4' + * Switch: '/Switch' + */ + if (rtDW.CCU_AC_MAX > 0) { + i = 7; + } else { + if ((rtDW.step_start_controle_front == 0) || (rtDW.step_start_controle_front + == 1) || (rtDW.step_start_controle_front == 2)) { + /* Switch: '/Switch' incorporates: + * DataStoreRead: '/AF from Start Control' + */ + rtb_DataTypeConversion1_nc = rtDW.Blower_FL; + } else { + /* Switch: '/Switch' */ + rtb_DataTypeConversion1_nc = (uint8_t)Gain; + } + + Gain = (uint16_t)(rtb_DataTypeConversion1_nc + + rtDW.Blower_individual_foot_FL); + i = rtDW.CCU_BLOWERS_FR; + } + + /* End of Switch: '/Switch6' */ + + /* Outputs for Enabled SubSystem: '/Front Right AF - manual directions' incorporates: + * EnablePort: '/Enable' + */ + /* RelationalOperator: '/Equal3' incorporates: + * Constant: '/Constant3' + * DataStoreRead: '/Data Store Read45' + */ + if (rtDW.CCU_MODE_FR == 0) { + /* MATLAB Function: '/AF for Bi Level' incorporates: + * DataTypeConversion: '/Data Type Conversion6' + */ + AFforBiLevel((uint8_t)i, &Gain1); + + /* MATLAB Function: '/AF for Def' incorporates: + * DataTypeConversion: '/Data Type Conversion6' + */ + AFforDef((uint8_t)i, &rtb_Saturation2_a); + + /* MATLAB Function: '/AF for Foor + Def' incorporates: + * DataTypeConversion: '/Data Type Conversion6' + */ + AFforFoorDef((uint8_t)i, &rtb_out_ew); + + /* MATLAB Function: '/AF for Foot' incorporates: + * DataTypeConversion: '/Data Type Conversion6' + */ + AFforFoot((uint8_t)i, &rtb_out_h0); + + /* MATLAB Function: '/AF for Hi_Level' incorporates: + * DataTypeConversion: '/Data Type Conversion6' + */ + AFforHi_Level((uint8_t)i, &rtb_out_nj); + + /* MATLAB Function: '/AF for Tri-Level' incorporates: + * DataTypeConversion: '/Data Type Conversion6' + */ + AFforTriLevel((uint8_t)i, &rtB.MultiportSwitch_a); + + /* MATLAB Function: '/AF for Vent mode' incorporates: + * DataTypeConversion: '/Data Type Conversion6' + */ + AFforVentmode((uint8_t)i, &rtb_out_e); + + /* RelationalOperator: '/Relational Operator2' incorporates: + * Constant: '/Constant2' + * DataStoreRead: '/Data Store Read14' + */ + rtb_Compare_i5 = (rtDW.CCU_FOOT_FR == 1); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read12' + * DataStoreRead: '/Data Store Read13' + * DataTypeConversion: '/Data Type Conversion5' + * Gain: '/Gain1' + * Gain: '/Gain2' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator1' + * Sum: '/Add' + */ + switch ((int32_t)(((uint32_t)((rtDW.CCU_FACE_FR == 1) << 1) + (uint32_t) + (rtDW.CCU_DEF_FR == 1)) + (uint32_t)(rtb_Compare_i5 << 2))) + { + case 0: + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Constant: '/Constant3' + */ + rtB.MultiportSwitch_a = 0U; + break; + + case 1: + /* MultiPortSwitch: '/Multiport Switch' */ + rtB.MultiportSwitch_a = rtb_Saturation2_a; + break; + + case 2: + /* MultiPortSwitch: '/Multiport Switch' */ + rtB.MultiportSwitch_a = rtb_out_e; + break; + + case 3: + /* MultiPortSwitch: '/Multiport Switch' */ + rtB.MultiportSwitch_a = rtb_out_nj; + break; + + case 4: + /* MultiPortSwitch: '/Multiport Switch' */ + rtB.MultiportSwitch_a = rtb_out_h0; + break; + + case 5: + /* MultiPortSwitch: '/Multiport Switch' */ + rtB.MultiportSwitch_a = rtb_out_ew; + break; + + case 6: + /* MultiPortSwitch: '/Multiport Switch' */ + rtB.MultiportSwitch_a = Gain1; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch' */ + } + + /* End of RelationalOperator: '/Equal3' */ + /* End of Outputs for SubSystem: '/Front Right AF - manual directions' */ + + /* Switch: '/Switch2' incorporates: + * Constant: '/Constant12' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read76' + */ + if (rtDW.CCU_AC_MAX > 0) { + i = 5; + } else { + i = rtDW.CCU_AUTOMODE_FR; + } + + /* MATLAB Function: '/func g_ascAUTO_STEP_AF_F' incorporates: + * Switch: '/Switch2' + */ + funcg_ascAUTO_STEP_AF_F((double)i, &rtb_y_eo); + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * Constant: '/Constant2' + * Constant: '/Constant3' + * Constant: '/Constant4' + * Constant: '/Constant5' + */ + switch (rtb_timer_out) { + case 0: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVF_MAX_LV0[i]; + } + break; + + case 1: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVF_MAX_LV1[i]; + } + break; + + case 2: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVF_MAX_LV2[i]; + } + break; + + case 3: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVF_MAX_LV3[i]; + } + break; + + case 4: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVF_MAX_LV4[i]; + } + break; + + default: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVF_MAX_LV5[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* Saturate: '/Saturation6' incorporates: + * DataStoreRead: '/Data Store Read31' + */ + if (rtDW.CCU_SET_FR > 290) { + rtb_out_h0 = 290U; + } else if (rtDW.CCU_SET_FR < 170) { + rtb_out_h0 = 170U; + } else { + rtb_out_h0 = rtDW.CCU_SET_FR; + } + + /* End of Saturate: '/Saturation6' */ + + /* Gain: '/Gain4' incorporates: + * Bias: '/Bias1' + * DataTypeConversion: '/Data Type Conversion4' + * Gain: '/Gain3' + * Product: '/Divide4' + */ + i = ((int32_t)((52429U * rtb_out_h0) >> 19) + -15) << 14; + + /* DataTypeConversion: '/Data Type Conversion3' incorporates: + * Product: '/Divide4' + * Saturate: '/Saturation1' + */ + rtb_DataTypeConversion3_i = (uint8_t)((((uint32_t)i & 16384U) != 0U) + (i >> + 15)); + + /* Selector: '/Selector' */ + rtb_Bias5 = rtb_uDLookupTable7_g[rtb_DataTypeConversion3_i - 1]; + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Lookup_n-D: '/1-D Lookup Table10' + * Lookup_n-D: '/1-D Lookup Table11' + * Lookup_n-D: '/1-D Lookup Table6' + * Lookup_n-D: '/1-D Lookup Table7' + * Lookup_n-D: '/1-D Lookup Table8' + * Lookup_n-D: '/1-D Lookup Table9' + * Saturate: '/Saturation6' + */ + switch (rtb_timer_out) { + case 0: + rtb_MultiportSwitch1_g = look1_iu16lu64n48ts16Ds32_binlcs(rtb_out_h0, + rtConstP.pooled79, &g_assVTG_FR_LV0[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table6' + * Lookup_n-D: '/1-D Lookup Table' + * Saturate: '/Saturation6' + */ + rtb_MultiportSwitch_pa = look1_iu16bs16lu64n32ts16Ds32_binlcs(rtb_out_h0, + rtConstP.pooled51, &g_assINCAR_TG_FR_LV0[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[0] = g_assVF_INC_Y1_LV0[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[1] = g_assVF_INC_Y2_LV0[rtb_DataTypeConversion3_i - + 1]; + break; + + case 1: + rtb_MultiportSwitch1_g = look1_iu16lu64n48ts16Ds32_binlcs(rtb_out_h0, + rtConstP.pooled79, &g_assVTG_FR_LV1[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table7' + * Lookup_n-D: '/1-D Lookup Table1' + * Saturate: '/Saturation6' + */ + rtb_MultiportSwitch_pa = look1_iu16bs16lu64n32ts16Ds32_binlcs(rtb_out_h0, + rtConstP.pooled51, &g_assINCAR_TG_FR_LV1[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[0] = g_assVF_INC_Y1_LV1[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[1] = g_assVF_INC_Y2_LV1[rtb_DataTypeConversion3_i - + 1]; + break; + + case 2: + rtb_MultiportSwitch1_g = look1_iu16lu64n48ts16Ds32_binlcs(rtb_out_h0, + rtConstP.pooled79, &g_assVTG_FR_LV1[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table8' + * Lookup_n-D: '/1-D Lookup Table2' + * Saturate: '/Saturation6' + */ + rtb_MultiportSwitch_pa = look1_iu16bs16lu64n32ts16Ds32_binlcs(rtb_out_h0, + rtConstP.pooled51, &g_assINCAR_TG_FR_LV2[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[0] = g_assVF_INC_Y1_LV2[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[1] = g_assVF_INC_Y2_LV2[rtb_DataTypeConversion3_i - + 1]; + break; + + case 3: + rtb_MultiportSwitch1_g = look1_iu16lu64n48ts16Ds32_binlcs(rtb_out_h0, + rtConstP.pooled79, &g_assVTG_FR_LV3[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table9' + * Lookup_n-D: '/1-D Lookup Table3' + * Saturate: '/Saturation6' + */ + rtb_MultiportSwitch_pa = look1_iu16bs16lu64n32ts16Ds32_binlcs(rtb_out_h0, + rtConstP.pooled51, &g_assINCAR_TG_FR_LV3[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[0] = g_assVF_INC_Y1_LV3[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[1] = g_assVF_INC_Y2_LV3[rtb_DataTypeConversion3_i - + 1]; + break; + + case 4: + rtb_MultiportSwitch1_g = look1_iu16lu64n48ts16Ds32_binlcs(rtb_out_h0, + rtConstP.pooled79, &g_assVTG_FR_LV4[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table10' + * Lookup_n-D: '/1-D Lookup Table4' + * Saturate: '/Saturation6' + */ + rtb_MultiportSwitch_pa = look1_iu16bs16lu64n32ts16Ds32_binlcs(rtb_out_h0, + rtConstP.pooled51, &g_assINCAR_TG_FR_LV4[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[0] = g_assVF_INC_Y1_LV4[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[1] = g_assVF_INC_Y2_LV4[rtb_DataTypeConversion3_i - + 1]; + break; + + default: + rtb_MultiportSwitch1_g = look1_iu16lu64n48ts16Ds32_binlcs(rtb_out_h0, + rtConstP.pooled79, &g_assVTG_FR_LV5[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table11' + * Lookup_n-D: '/1-D Lookup Table5' + * Saturate: '/Saturation6' + */ + rtb_MultiportSwitch_pa = look1_iu16bs16lu64n32ts16Ds32_binlcs(rtb_out_h0, + rtConstP.pooled51, &g_assINCAR_TG_FR_LV5[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[0] = g_assVF_INC_Y1_LV5[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[1] = g_assVF_INC_Y2_LV5[rtb_DataTypeConversion3_i - + 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_lb[2] = 0; + + /* MultiPortSwitch: '/Multiport Switch3' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant14' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[3] = g_assVF_INC_Y3_LV0[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant20' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[4] = g_assVF_INC_Y4_LV0[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[0] = g_assVF_INC_X1_LV0[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[1] = g_assVF_INC_X2_LV0[rtb_DataTypeConversion3_i - + 1]; + break; + + case 1: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant15' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[3] = g_assVF_INC_Y3_LV1[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant21' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[4] = g_assVF_INC_Y4_LV1[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[0] = g_assVF_INC_X1_LV1[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[1] = g_assVF_INC_X2_LV1[rtb_DataTypeConversion3_i - + 1]; + break; + + case 2: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant16' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[3] = g_assVF_INC_Y3_LV2[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant22' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[4] = g_assVF_INC_Y4_LV2[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[0] = g_assVF_INC_X1_LV2[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[1] = g_assVF_INC_X2_LV2[rtb_DataTypeConversion3_i - + 1]; + break; + + case 3: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant17' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[3] = g_assVF_INC_Y3_LV3[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant23' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[4] = g_assVF_INC_Y4_LV3[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[0] = g_assVF_INC_X1_LV3[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[1] = g_assVF_INC_X2_LV3[rtb_DataTypeConversion3_i - + 1]; + break; + + case 4: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant12' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[3] = g_assVF_INC_Y3_LV4[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant18' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[4] = g_assVF_INC_Y4_LV4[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[0] = g_assVF_INC_X1_LV4[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[1] = g_assVF_INC_X2_LV4[rtb_DataTypeConversion3_i - + 1]; + break; + + default: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant13' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[3] = g_assVF_INC_Y3_LV5[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant19' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[4] = g_assVF_INC_Y4_LV5[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[0] = g_assVF_INC_X1_LV5[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[1] = g_assVF_INC_X2_LV5[rtb_DataTypeConversion3_i - + 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch3' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_jn[2] = 0; + + /* MultiPortSwitch: '/Multiport Switch3' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant14' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[3] = g_assVF_INC_X3_LV0[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant20' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[4] = g_assVF_INC_X4_LV0[rtb_DataTypeConversion3_i - + 1]; + break; + + case 1: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant15' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[3] = g_assVF_INC_X3_LV1[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant21' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[4] = g_assVF_INC_X4_LV1[rtb_DataTypeConversion3_i - + 1]; + break; + + case 2: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant16' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[3] = g_assVF_INC_X3_LV2[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant22' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[4] = g_assVF_INC_X4_LV2[rtb_DataTypeConversion3_i - + 1]; + break; + + case 3: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant17' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[3] = g_assVF_INC_X3_LV3[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant23' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[4] = g_assVF_INC_X4_LV3[rtb_DataTypeConversion3_i - + 1]; + break; + + case 4: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant12' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[3] = g_assVF_INC_X3_LV4[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant18' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[4] = g_assVF_INC_X4_LV4[rtb_DataTypeConversion3_i - + 1]; + break; + + default: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant13' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[3] = g_assVF_INC_X3_LV5[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant19' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_jn[4] = g_assVF_INC_X4_LV5[rtb_DataTypeConversion3_i - + 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch3' */ + + /* Lookup_n-D: '/2.5 FLU_tg_incar' incorporates: + * DataStoreRead: '/Data Store Read36' + * Sum: '/2.5. X = Inc_Tg - Incar_fb' + */ + rtb_u5FLU_tg_incar_i = look1_is16lu64n32Ds32_binlcn((int16_t) + (rtb_MultiportSwitch_pa - rtDW.Incar_FR), rtb_VectorConcatenate_jn, + rtb_VectorConcatenate_lb, 4U); + + /* MultiPortSwitch: '/Multiport Switch1' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[0] = g_assVF_AMB_Y1_LV0[rtb_DataTypeConversion3_i - + 1]; + break; + + case 1: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[0] = g_assVF_AMB_Y1_LV1[rtb_DataTypeConversion3_i - + 1]; + break; + + case 2: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[0] = g_assVF_AMB_Y1_LV2[rtb_DataTypeConversion3_i - + 1]; + break; + + case 3: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[0] = g_assVF_AMB_Y1_LV3[rtb_DataTypeConversion3_i - + 1]; + break; + + case 4: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[0] = g_assVF_AMB_Y1_LV4[rtb_DataTypeConversion3_i - + 1]; + break; + + default: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[0] = g_assVF_AMB_Y1_LV5[rtb_DataTypeConversion3_i - + 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_dw[1] = 0; + + /* MultiPortSwitch: '/Multiport Switch2' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[2] = g_assVF_AMB_Y2_LV0[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[0] = g_assVF_AMB_X1_LV0[rtb_DataTypeConversion3_i - + 1]; + break; + + case 1: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[2] = g_assVF_AMB_Y2_LV1[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[0] = g_assVF_AMB_X1_LV1[rtb_DataTypeConversion3_i - + 1]; + break; + + case 2: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[2] = g_assVF_AMB_Y2_LV2[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[0] = g_assVF_AMB_X1_LV2[rtb_DataTypeConversion3_i - + 1]; + break; + + case 3: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[2] = g_assVF_AMB_Y2_LV3[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[0] = g_assVF_AMB_X1_LV3[rtb_DataTypeConversion3_i - + 1]; + break; + + case 4: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[2] = g_assVF_AMB_Y2_LV4[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[0] = g_assVF_AMB_X1_LV4[rtb_DataTypeConversion3_i - + 1]; + break; + + default: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_dw[2] = g_assVF_AMB_Y2_LV5[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[0] = g_assVF_AMB_X1_LV5[rtb_DataTypeConversion3_i - + 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch2' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_pg[1] = 0; + + /* MultiPortSwitch: '/Multiport Switch2' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[2] = g_assVF_AMB_X2_LV0[rtb_DataTypeConversion3_i - + 1]; + break; + + case 1: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[2] = g_assVF_AMB_X2_LV1[rtb_DataTypeConversion3_i - + 1]; + break; + + case 2: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[2] = g_assVF_AMB_X2_LV2[rtb_DataTypeConversion3_i - + 1]; + break; + + case 3: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[2] = g_assVF_AMB_X2_LV3[rtb_DataTypeConversion3_i - + 1]; + break; + + case 4: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[2] = g_assVF_AMB_X2_LV4[rtb_DataTypeConversion3_i - + 1]; + break; + + default: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_pg[2] = g_assVF_AMB_X2_LV5[rtb_DataTypeConversion3_i - + 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch2' */ + + /* Lookup_n-D: '/2.6 FLU_tg_amb' */ + rtb_u6FLU_tg_amb_g = look1_is16lu64n32Ds32_binlcn(rtb_FLU_tg_correct_aa, + rtb_VectorConcatenate_pg, rtb_VectorConcatenate_dw, 2U); + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_gn[0] = 0; + + /* MultiPortSwitch: '/Multiport Switch1' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[1] = g_assVF_SUN_Y1_LV0[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = g_assVF_SUN_Y2_LV0[rtb_DataTypeConversion3_i - + 1]; + break; + + case 1: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[1] = g_assVF_SUN_Y1_LV1[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = g_assVF_SUN_Y2_LV1[rtb_DataTypeConversion3_i - + 1]; + break; + + case 2: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[1] = g_assVF_SUN_Y1_LV2[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = g_assVF_SUN_Y2_LV2[rtb_DataTypeConversion3_i - + 1]; + break; + + case 3: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[1] = g_assVF_SUN_Y1_LV3[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = g_assVF_SUN_Y2_LV3[rtb_DataTypeConversion3_i - + 1]; + break; + + case 4: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[1] = g_assVF_SUN_Y1_LV4[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = g_assVF_SUN_Y2_LV4[rtb_DataTypeConversion3_i - + 1]; + break; + + default: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[1] = g_assVF_SUN_Y1_LV5[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = g_assVF_SUN_Y2_LV5[rtb_DataTypeConversion3_i - + 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_np[0] = 0; + + /* MultiPortSwitch: '/Multiport Switch1' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[1] = g_assVF_SUN_X1_LV0[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = g_assVF_SUN_X2_LV0[rtb_DataTypeConversion3_i - + 1]; + break; + + case 1: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[1] = g_assVF_SUN_X1_LV1[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = g_assVF_SUN_X2_LV1[rtb_DataTypeConversion3_i - + 1]; + break; + + case 2: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[1] = g_assVF_SUN_X1_LV2[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = g_assVF_SUN_X2_LV2[rtb_DataTypeConversion3_i - + 1]; + break; + + case 3: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[1] = g_assVF_SUN_X1_LV3[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = g_assVF_SUN_X2_LV3[rtb_DataTypeConversion3_i - + 1]; + break; + + case 4: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[1] = g_assVF_SUN_X1_LV4[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = g_assVF_SUN_X2_LV4[rtb_DataTypeConversion3_i - + 1]; + break; + + default: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[1] = g_assVF_SUN_X1_LV5[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = g_assVF_SUN_X2_LV5[rtb_DataTypeConversion3_i - + 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* Lookup_n-D: '/2.6 FLU_tg_amb' incorporates: + * DataStoreRead: '/Data Store Read41' + */ + rtb_u6FLU_tg_amb_a3 = look1_bs16ts16Dd_binlc(rtDW.Sun_R, + rtb_VectorConcatenate_np, rtb_VectorConcatenate_gn, 2U); + + /* Sum: '/FLU_tg_correct' */ + rtb_MultiportSwitch_jq = (int16_t)((int16_t)((int16_t)(rtb_MultiportSwitch1_g + + rtb_u5FLU_tg_incar_i) + rtb_u6FLU_tg_amb_g) + rtb_u6FLU_tg_amb_a3); + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + */ + if (rtb_MultiportSwitch_jq <= rtb_Bias5) { + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * Constant: '/Constant2' + * Constant: '/Constant3' + * Constant: '/Constant4' + * Constant: '/Constant5' + */ + switch (rtb_timer_out) { + case 0: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVF_MIN_LV0[i]; + } + break; + + case 1: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVF_MIN_LV1[i]; + } + break; + + case 2: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVF_MIN_LV2[i]; + } + break; + + case 3: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVF_MIN_LV3[i]; + } + break; + + case 4: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVF_MIN_LV4[i]; + } + break; + + default: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVF_MIN_LV5[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* Selector: '/Selector' incorporates: + * Selector: '/Selector' + */ + rtb_Bias5 = rtb_uDLookupTable7_g[rtb_DataTypeConversion3_i - 1]; + + /* Switch: '/Switch' incorporates: + * RelationalOperator: '/UpperRelop' + * Selector: '/Selector' + */ + if (rtb_MultiportSwitch_jq >= rtb_Bias5) { + rtb_Bias5 = rtb_MultiportSwitch_jq; + } + + /* End of Switch: '/Switch' */ + } + + /* End of Switch: '/Switch2' */ + + /* Switch: '/Switch1' incorporates: + * Constant: '/manual1' + * RelationalOperator: '/Equal2' + * UnitDelay: '/Unit Delay1' + */ + if (rtDW.UnitDelay1_DSTATE_j == 0) { + Gain1 = rtB.MultiportSwitch_a; + } else { + /* Sum: '/Add' incorporates: + * DataTypeConversion: '/Data Type Conversion' + * DataTypeConversion: '/Data Type Conversion' + * Gain: '/Gain' + * Product: '/Product' + */ + rtb_Add_be = 0.01 * (double)rtb_y_eo * (double)(uint16_t)rtb_Bias5 + (double) + (uint16_t)rtb_Bias5; + + /* DataTypeConversion: '/Data Type Conversion1' */ + if (fabs(rtb_Add_be) >= 0.5) { + Gain1 = (uint16_t)floor(rtb_Add_be + 0.5); + } else { + Gain1 = 0U; + } + + /* End of DataTypeConversion: '/Data Type Conversion1' */ + } + + /* End of Switch: '/Switch1' */ + + /* Switch: '/Switch7' incorporates: + * DataStoreRead: '/Data Store Read5' + * DataStoreRead: '/Data Store Read2' + * DataStoreWrite: '/Data Store Write20' + * Sum: '/Sum' + * Switch: '/Switch' + */ + if (rtDW.CCU_AC_MAX <= 0) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * DataStoreRead: '/AF from Start Control' + * DataStoreRead: '/Data Store Read' + * Logic: '/Logical Operator' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + */ + if ((rtDW.step_start_controle_front == 0) || (rtDW.step_start_controle_front + == 1) || (rtDW.step_start_controle_front == 2)) { + rtb_DataTypeConversion1_nc = rtDW.Blower_FR; + } else { + rtb_DataTypeConversion1_nc = (uint8_t)Gain1; + } + + Gain1 = (uint16_t)(rtb_DataTypeConversion1_nc + + rtDW.Blower_individual_foot_FR); + } + + /* End of Switch: '/Switch7' */ + + /* Outputs for Enabled SubSystem: '/Rear Left AF - manual directions' */ + /* RelationalOperator: '/Equal2' incorporates: + * Constant: '/Constant2' + * DataStoreRead: '/Data Store Read18' + * DataStoreRead: '/Data Store Read19' + * DataStoreRead: '/Data Store Read20' + * DataStoreRead: '/Data Store Read44' + */ + RearLeftAFmanualdirections((rtDW.CCU_MODE_RL == 0), rtDW.CCU_BLOWERS_RL, + rtDW.CCU_FACE_RL, rtDW.CCU_FOOT_RL, &rtB.MultiportSwitch_m); + + /* End of Outputs for SubSystem: '/Rear Left AF - manual directions' */ + + /* Saturate: '/Saturation7' incorporates: + * DataStoreRead: '/Data Store Read32' + */ + /* : y = g_ascAUTO_STEP_AF_R(AF_STEP); */ + if (rtDW.CCU_SET_RL > 290) { + rtb_Saturation2_a = 290U; + } else if (rtDW.CCU_SET_RL < 170) { + rtb_Saturation2_a = 170U; + } else { + rtb_Saturation2_a = rtDW.CCU_SET_RL; + } + + /* End of Saturate: '/Saturation7' */ + + /* Gain: '/Gain2' incorporates: + * Bias: '/Bias2' + * DataTypeConversion: '/Data Type Conversion2' + * Gain: '/Gain1' + * Product: '/Divide4' + */ + i = ((int32_t)((52429U * rtb_Saturation2_a) >> 19) + -15) << 14; + + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Product: '/Divide4' + * Saturate: '/Saturation2' + */ + rtb_DataTypeConversion3_i = (uint8_t)((((uint32_t)i & 16384U) != 0U) + (i >> + 15)); + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Lookup_n-D: '/1-D Lookup Table10' + * Lookup_n-D: '/1-D Lookup Table11' + * Lookup_n-D: '/1-D Lookup Table6' + * Lookup_n-D: '/1-D Lookup Table7' + * Lookup_n-D: '/1-D Lookup Table8' + * Lookup_n-D: '/1-D Lookup Table9' + * Saturate: '/Saturation7' + */ + switch (rtb_timer_out) { + case 0: + rtb_MultiportSwitch_ev = look1_iu16lu64n48ts16Ds32_binlcs(rtb_Saturation2_a, + rtConstP.pooled79, &g_assVTG_RL_LV0[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table6' + * Lookup_n-D: '/1-D Lookup Table' + * Saturate: '/Saturation7' + */ + rtb_Bias5 = look1_iu16bs16lu64n32ts16Ds32_binlcs(rtb_Saturation2_a, + rtConstP.pooled51, &g_assINCAR_TG_RL_LV0[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * MultiPortSwitch: '/Multiport Switch1' + */ + rtb_VectorConcatenate_lb[0] = g_assVR_INC_Y1_LV0[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[1] = g_assVR_INC_Y2_LV0[rtb_DataTypeConversion3_i - + 1]; + break; + + case 1: + rtb_MultiportSwitch_ev = look1_iu16lu64n48ts16Ds32_binlcs(rtb_Saturation2_a, + rtConstP.pooled79, &g_assVTG_RL_LV1[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table7' + * Lookup_n-D: '/1-D Lookup Table1' + * Saturate: '/Saturation7' + */ + rtb_Bias5 = look1_iu16bs16lu64n32ts16Ds32_binlcs(rtb_Saturation2_a, + rtConstP.pooled51, &g_assINCAR_TG_RL_LV1[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * MultiPortSwitch: '/Multiport Switch1' + */ + rtb_VectorConcatenate_lb[0] = g_assVR_INC_Y1_LV1[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[1] = g_assVR_INC_Y2_LV1[rtb_DataTypeConversion3_i - + 1]; + break; + + case 2: + rtb_MultiportSwitch_ev = look1_iu16lu64n48ts16Ds32_binlcs(rtb_Saturation2_a, + rtConstP.pooled79, &g_assVTG_RL_LV1[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table8' + * Lookup_n-D: '/1-D Lookup Table2' + * Saturate: '/Saturation7' + */ + rtb_Bias5 = look1_iu16bs16lu64n32ts16Ds32_binlcs(rtb_Saturation2_a, + rtConstP.pooled51, &g_assINCAR_TG_RL_LV2[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * MultiPortSwitch: '/Multiport Switch1' + */ + rtb_VectorConcatenate_lb[0] = g_assVR_INC_Y1_LV2[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[1] = g_assVR_INC_Y2_LV2[rtb_DataTypeConversion3_i - + 1]; + break; + + case 3: + rtb_MultiportSwitch_ev = look1_iu16lu64n48ts16Ds32_binlcs(rtb_Saturation2_a, + rtConstP.pooled79, &g_assVTG_RL_LV3[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table9' + * Lookup_n-D: '/1-D Lookup Table3' + * Saturate: '/Saturation7' + */ + rtb_Bias5 = look1_iu16bs16lu64n32ts16Ds32_binlcs(rtb_Saturation2_a, + rtConstP.pooled51, &g_assINCAR_TG_RL_LV3[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * MultiPortSwitch: '/Multiport Switch1' + */ + rtb_VectorConcatenate_lb[0] = g_assVR_INC_Y1_LV3[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[1] = g_assVR_INC_Y2_LV3[rtb_DataTypeConversion3_i - + 1]; + break; + + case 4: + rtb_MultiportSwitch_ev = look1_iu16lu64n48ts16Ds32_binlcs(rtb_Saturation2_a, + rtConstP.pooled79, &g_assVTG_RL_LV4[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table10' + * Lookup_n-D: '/1-D Lookup Table4' + * Saturate: '/Saturation7' + */ + rtb_Bias5 = look1_iu16bs16lu64n32ts16Ds32_binlcs(rtb_Saturation2_a, + rtConstP.pooled51, &g_assINCAR_TG_RL_LV4[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * MultiPortSwitch: '/Multiport Switch1' + */ + rtb_VectorConcatenate_lb[0] = g_assVR_INC_Y1_LV4[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[1] = g_assVR_INC_Y2_LV4[rtb_DataTypeConversion3_i - + 1]; + break; + + default: + rtb_MultiportSwitch_ev = look1_iu16lu64n48ts16Ds32_binlcs(rtb_Saturation2_a, + rtConstP.pooled79, &g_assVTG_RL_LV5[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table11' + * Lookup_n-D: '/1-D Lookup Table5' + * Saturate: '/Saturation7' + */ + rtb_Bias5 = look1_iu16bs16lu64n32ts16Ds32_binlcs(rtb_Saturation2_a, + rtConstP.pooled51, &g_assINCAR_TG_RL_LV5[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * MultiPortSwitch: '/Multiport Switch1' + */ + rtb_VectorConcatenate_lb[0] = g_assVR_INC_Y1_LV5[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[1] = g_assVR_INC_Y2_LV5[rtb_DataTypeConversion3_i - + 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_lb[2] = 0; + + /* MultiPortSwitch: '/Multiport Switch3' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant14' + */ + rtb_VectorConcatenate_lb[3] = g_assVR_INC_Y3_LV0[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant20' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_lb[4] = g_assVR_INC_Y4_LV0[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_jn[0] = g_assVR_INC_X1_LV0[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_jn[1] = g_assVR_INC_X2_LV0[rtb_DataTypeConversion3_i - + 1]; + break; + + case 1: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant15' + */ + rtb_VectorConcatenate_lb[3] = g_assVR_INC_Y3_LV1[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant21' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_lb[4] = g_assVR_INC_Y4_LV1[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_jn[0] = g_assVR_INC_X1_LV1[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_jn[1] = g_assVR_INC_X2_LV1[rtb_DataTypeConversion3_i - + 1]; + break; + + case 2: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant16' + */ + rtb_VectorConcatenate_lb[3] = g_assVR_INC_Y3_LV2[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant22' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_lb[4] = g_assVR_INC_Y4_LV2[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_jn[0] = g_assVR_INC_X1_LV2[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_jn[1] = g_assVR_INC_X2_LV2[rtb_DataTypeConversion3_i - + 1]; + break; + + case 3: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant17' + */ + rtb_VectorConcatenate_lb[3] = g_assVR_INC_Y3_LV3[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant23' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_lb[4] = g_assVR_INC_Y4_LV3[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_jn[0] = g_assVR_INC_X1_LV3[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_jn[1] = g_assVR_INC_X2_LV3[rtb_DataTypeConversion3_i - + 1]; + break; + + case 4: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant12' + */ + rtb_VectorConcatenate_lb[3] = g_assVR_INC_Y3_LV4[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant18' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_lb[4] = g_assVR_INC_Y4_LV4[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_jn[0] = g_assVR_INC_X1_LV4[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_jn[1] = g_assVR_INC_X2_LV4[rtb_DataTypeConversion3_i - + 1]; + break; + + default: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant13' + */ + rtb_VectorConcatenate_lb[3] = g_assVR_INC_Y3_LV5[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant19' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_lb[4] = g_assVR_INC_Y4_LV5[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_jn[0] = g_assVR_INC_X1_LV5[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_jn[1] = g_assVR_INC_X2_LV5[rtb_DataTypeConversion3_i - + 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch3' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_jn[2] = 0; + + /* MultiPortSwitch: '/Multiport Switch3' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant14' + */ + rtb_VectorConcatenate_jn[3] = g_assVR_INC_X3_LV0[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant20' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_jn[4] = g_assVR_INC_X4_LV0[rtb_DataTypeConversion3_i - + 1]; + break; + + case 1: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant15' + */ + rtb_VectorConcatenate_jn[3] = g_assVR_INC_X3_LV1[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant21' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_jn[4] = g_assVR_INC_X4_LV1[rtb_DataTypeConversion3_i - + 1]; + break; + + case 2: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant16' + */ + rtb_VectorConcatenate_jn[3] = g_assVR_INC_X3_LV2[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant22' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_jn[4] = g_assVR_INC_X4_LV2[rtb_DataTypeConversion3_i - + 1]; + break; + + case 3: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant17' + */ + rtb_VectorConcatenate_jn[3] = g_assVR_INC_X3_LV3[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant23' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_jn[4] = g_assVR_INC_X4_LV3[rtb_DataTypeConversion3_i - + 1]; + break; + + case 4: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant12' + */ + rtb_VectorConcatenate_jn[3] = g_assVR_INC_X3_LV4[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant18' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_jn[4] = g_assVR_INC_X4_LV4[rtb_DataTypeConversion3_i - + 1]; + break; + + default: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant13' + */ + rtb_VectorConcatenate_jn[3] = g_assVR_INC_X3_LV5[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant19' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_jn[4] = g_assVR_INC_X4_LV5[rtb_DataTypeConversion3_i - + 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch3' */ + + /* Lookup_n-D: '/2.5 FLU_tg_incar' incorporates: + * DataStoreRead: '/Data Store Read37' + * Sum: '/2.5. X = Incar_Tg - Incar_fb' + */ + rtb_u5FRU_tg_incar = look1_is16lu64n32Ds32_binlcn((int16_t)(rtb_Bias5 - + rtDW.Incar_RL), rtb_VectorConcatenate_jn, rtb_VectorConcatenate_lb, 4U); + + /* MultiPortSwitch: '/Multiport Switch1' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + */ + rtb_VectorConcatenate_dw[0] = g_assVR_AMB_Y1_LV0[rtb_DataTypeConversion3_i - + 1]; + break; + + case 1: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + */ + rtb_VectorConcatenate_dw[0] = g_assVR_AMB_Y1_LV1[rtb_DataTypeConversion3_i - + 1]; + break; + + case 2: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + */ + rtb_VectorConcatenate_dw[0] = g_assVR_AMB_Y1_LV2[rtb_DataTypeConversion3_i - + 1]; + break; + + case 3: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + */ + rtb_VectorConcatenate_dw[0] = g_assVR_AMB_Y1_LV3[rtb_DataTypeConversion3_i - + 1]; + break; + + case 4: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + */ + rtb_VectorConcatenate_dw[0] = g_assVR_AMB_Y1_LV4[rtb_DataTypeConversion3_i - + 1]; + break; + + default: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + */ + rtb_VectorConcatenate_dw[0] = g_assVR_AMB_Y1_LV5[rtb_DataTypeConversion3_i - + 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_dw[1] = 0; + + /* MultiPortSwitch: '/Multiport Switch2' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + */ + rtb_VectorConcatenate_dw[2] = g_assVR_AMB_Y2_LV0[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_pg[0] = g_assVR_AMB_X1_LV0[rtb_DataTypeConversion3_i - + 1]; + break; + + case 1: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + */ + rtb_VectorConcatenate_dw[2] = g_assVR_AMB_Y2_LV1[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_pg[0] = g_assVR_AMB_X1_LV1[rtb_DataTypeConversion3_i - + 1]; + break; + + case 2: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + */ + rtb_VectorConcatenate_dw[2] = g_assVR_AMB_Y2_LV2[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_pg[0] = g_assVR_AMB_X1_LV2[rtb_DataTypeConversion3_i - + 1]; + break; + + case 3: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + */ + rtb_VectorConcatenate_dw[2] = g_assVR_AMB_Y2_LV3[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_pg[0] = g_assVR_AMB_X1_LV3[rtb_DataTypeConversion3_i - + 1]; + break; + + case 4: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + */ + rtb_VectorConcatenate_dw[2] = g_assVR_AMB_Y2_LV4[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_pg[0] = g_assVR_AMB_X1_LV4[rtb_DataTypeConversion3_i - + 1]; + break; + + default: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + */ + rtb_VectorConcatenate_dw[2] = g_assVR_AMB_Y2_LV5[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_pg[0] = g_assVR_AMB_X1_LV5[rtb_DataTypeConversion3_i - + 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch2' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_pg[1] = 0; + + /* MultiPortSwitch: '/Multiport Switch2' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + */ + rtb_VectorConcatenate_pg[2] = g_assVR_AMB_X2_LV0[rtb_DataTypeConversion3_i - + 1]; + break; + + case 1: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + */ + rtb_VectorConcatenate_pg[2] = g_assVR_AMB_X2_LV1[rtb_DataTypeConversion3_i - + 1]; + break; + + case 2: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + */ + rtb_VectorConcatenate_pg[2] = g_assVR_AMB_X2_LV2[rtb_DataTypeConversion3_i - + 1]; + break; + + case 3: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + */ + rtb_VectorConcatenate_pg[2] = g_assVR_AMB_X2_LV3[rtb_DataTypeConversion3_i - + 1]; + break; + + case 4: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + */ + rtb_VectorConcatenate_pg[2] = g_assVR_AMB_X2_LV4[rtb_DataTypeConversion3_i - + 1]; + break; + + default: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + */ + rtb_VectorConcatenate_pg[2] = g_assVR_AMB_X2_LV5[rtb_DataTypeConversion3_i - + 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch2' */ + + /* Lookup_n-D: '/2.6 FLU_tg_amb' */ + rtb_u6FRU_tg_amb_f = look1_is16lu64n32Ds32_binlcn(rtb_FLU_tg_correct_aa, + rtb_VectorConcatenate_pg, rtb_VectorConcatenate_dw, 2U); + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_gn[0] = 0; + + /* MultiPortSwitch: '/Multiport Switch1' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + */ + rtb_VectorConcatenate_gn[1] = g_assVR_SUN_Y1_LV0[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = g_assVR_SUN_Y2_LV0[rtb_DataTypeConversion3_i - + 1]; + break; + + case 1: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + */ + rtb_VectorConcatenate_gn[1] = g_assVR_SUN_Y1_LV1[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = g_assVR_SUN_Y2_LV1[rtb_DataTypeConversion3_i - + 1]; + break; + + case 2: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + */ + rtb_VectorConcatenate_gn[1] = g_assVR_SUN_Y1_LV2[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = g_assVR_SUN_Y2_LV2[rtb_DataTypeConversion3_i - + 1]; + break; + + case 3: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + */ + rtb_VectorConcatenate_gn[1] = g_assVR_SUN_Y1_LV3[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = g_assVR_SUN_Y2_LV3[rtb_DataTypeConversion3_i - + 1]; + break; + + case 4: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + */ + rtb_VectorConcatenate_gn[1] = g_assVR_SUN_Y1_LV4[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = g_assVR_SUN_Y2_LV4[rtb_DataTypeConversion3_i - + 1]; + break; + + default: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + */ + rtb_VectorConcatenate_gn[1] = g_assVR_SUN_Y1_LV5[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_gn[2] = g_assVR_SUN_Y2_LV5[rtb_DataTypeConversion3_i - + 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_np[0] = 0; + + /* MultiPortSwitch: '/Multiport Switch1' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + */ + rtb_VectorConcatenate_np[1] = g_assVR_SUN_X1_LV0[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = g_assVR_SUN_X2_LV0[rtb_DataTypeConversion3_i - + 1]; + break; + + case 1: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + */ + rtb_VectorConcatenate_np[1] = g_assVR_SUN_X1_LV1[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = g_assVR_SUN_X2_LV1[rtb_DataTypeConversion3_i - + 1]; + break; + + case 2: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + */ + rtb_VectorConcatenate_np[1] = g_assVR_SUN_X1_LV2[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = g_assVR_SUN_X2_LV2[rtb_DataTypeConversion3_i - + 1]; + break; + + case 3: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + */ + rtb_VectorConcatenate_np[1] = g_assVR_SUN_X1_LV3[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = g_assVR_SUN_X2_LV3[rtb_DataTypeConversion3_i - + 1]; + break; + + case 4: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + */ + rtb_VectorConcatenate_np[1] = g_assVR_SUN_X1_LV4[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = g_assVR_SUN_X2_LV4[rtb_DataTypeConversion3_i - + 1]; + break; + + default: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + */ + rtb_VectorConcatenate_np[1] = g_assVR_SUN_X1_LV5[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_np[2] = g_assVR_SUN_X2_LV5[rtb_DataTypeConversion3_i - + 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* Lookup_n-D: '/2.6 FLU_tg_amb' incorporates: + * DataStoreRead: '/Data Store Read39' + */ + rtb_u6FRU_tg_amb = look1_bs16ts16Dd_binlc(rtDW.Sun_L, rtb_VectorConcatenate_np, + rtb_VectorConcatenate_gn, 2U); + + /* Switch: '/Switch' incorporates: + * Constant: '/manual2' + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * DataStoreRead: '/AF from Start Control' + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write21' + * Logic: '/Logical Operator' + * RelationalOperator: '/Equal3' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * Switch: '/Switch2' + * UnitDelay: '/Unit Delay2' + */ + if ((rtDW.step_start_controle_rear == 0) || (rtDW.step_start_controle_rear == + 1) || (rtDW.step_start_controle_rear == 2)) { + rtb_Saturation2_a = rtDW.Blower_RL; + } else if (rtDW.UnitDelay2_DSTATE == 0) { + /* DataStoreWrite: '/Data Store Write21' incorporates: + * Switch: '/Switch2' + */ + rtb_Saturation2_a = rtB.MultiportSwitch_m; + } else { + /* Sum: '/2.8. Vtg_FX_plus' incorporates: + * Switch: '/Switch2' + */ + rtb_MultiportSwitch_jq = (int16_t)((int16_t)((int16_t) + (rtb_MultiportSwitch_ev + rtb_u5FRU_tg_incar) + rtb_u6FRU_tg_amb_f) + + rtb_u6FRU_tg_amb); + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * Constant: '/Constant2' + * Constant: '/Constant3' + * Constant: '/Constant4' + * Constant: '/Constant5' + * Switch: '/Switch2' + */ + switch (rtb_timer_out) { + case 0: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVR_MAX_LV0[i]; + } + break; + + case 1: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVR_MAX_LV1[i]; + } + break; + + case 2: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVR_MAX_LV2[i]; + } + break; + + case 3: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVR_MAX_LV3[i]; + } + break; + + case 4: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVR_MAX_LV4[i]; + } + break; + + default: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVR_MAX_LV5[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* Selector: '/Selector' incorporates: + * Switch: '/Switch2' + */ + rtb_MultiportSwitch_fu = rtb_uDLookupTable7_g[rtb_DataTypeConversion3_i - 1]; + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + * Switch: '/Switch2' + */ + if (rtb_MultiportSwitch_jq <= rtb_MultiportSwitch_fu) { + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * Constant: '/Constant2' + * Constant: '/Constant3' + * Constant: '/Constant4' + * Constant: '/Constant5' + */ + switch (rtb_timer_out) { + case 0: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVR_MIN_LV0[i]; + } + break; + + case 1: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVR_MIN_LV1[i]; + } + break; + + case 2: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVR_MIN_LV2[i]; + } + break; + + case 3: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVR_MIN_LV3[i]; + } + break; + + case 4: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVR_MIN_LV4[i]; + } + break; + + default: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVR_MIN_LV5[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* Selector: '/Selector' incorporates: + * Selector: '/Selector' + */ + rtb_MultiportSwitch_fu = rtb_uDLookupTable7_g[rtb_DataTypeConversion3_i - + 1]; + + /* Switch: '/Switch' incorporates: + * RelationalOperator: '/UpperRelop' + * Selector: '/Selector' + */ + if (rtb_MultiportSwitch_jq >= rtb_MultiportSwitch_fu) { + rtb_MultiportSwitch_fu = rtb_MultiportSwitch_jq; + } + + /* End of Switch: '/Switch' */ + } + + /* End of Switch: '/Switch2' */ + + /* Sum: '/Add' incorporates: + * DataStoreRead: '/Data Store Read' + * DataTypeConversion: '/Data Type Conversion' + * DataTypeConversion: '/Data Type Conversion1' + * DataTypeConversion: '/Data Type Conversion2' + * Gain: '/Gain' + * MATLAB Function: '/func g_ascAUTO_STEP_AF_F' + * Product: '/Product' + * Switch: '/Switch2' + */ + rtb_Add_be = (double)g_ascAUTO_STEP_AF_R[(int8_t)rtDW.CCU_AUTOMODE_RL - 1] * + 0.01 * (double)(uint16_t)rtb_MultiportSwitch_fu + (double)(uint16_t) + rtb_MultiportSwitch_fu; + + /* DataTypeConversion: '/Data Type Conversion2' incorporates: + * Switch: '/Switch2' + */ + if (fabs(rtb_Add_be) >= 0.5) { + /* DataStoreWrite: '/Data Store Write21' */ + rtb_Saturation2_a = (uint16_t)floor(rtb_Add_be + 0.5); + } else { + /* DataStoreWrite: '/Data Store Write21' */ + rtb_Saturation2_a = 0U; + } + + /* End of DataTypeConversion: '/Data Type Conversion2' */ + } + + /* End of Switch: '/Switch' */ + + /* Outputs for Enabled SubSystem: '/Rear Right AF - manual directions' */ + /* RelationalOperator: '/Equal1' incorporates: + * Constant: '/Constant3' + * DataStoreRead: '/Data Store Read15' + * DataStoreRead: '/Data Store Read16' + * DataStoreRead: '/Data Store Read17' + * DataStoreRead: '/Data Store Read45' + */ + RearLeftAFmanualdirections((rtDW.CCU_MODE_RR == 0), rtDW.CCU_BLOWERS_RR, + rtDW.CCU_FACE_RR, rtDW.CCU_FOOT_RR, &rtB.MultiportSwitch_c); + + /* End of Outputs for SubSystem: '/Rear Right AF - manual directions' */ + + /* Saturate: '/Saturation8' incorporates: + * DataStoreRead: '/Data Store Read33' + */ + /* : y = g_ascAUTO_STEP_AF_F(AF_STEP); */ + if (rtDW.CCU_SET_RR > 290) { + rtb_out_ew = 290U; + } else if (rtDW.CCU_SET_RR < 170) { + rtb_out_ew = 170U; + } else { + rtb_out_ew = rtDW.CCU_SET_RR; + } + + /* End of Saturate: '/Saturation8' */ + + /* Gain: '/Gain4' incorporates: + * Bias: '/Bias1' + * DataTypeConversion: '/Data Type Conversion4' + * Gain: '/Gain2' + * Product: '/Divide4' + */ + i = ((int32_t)((52429U * rtb_out_ew) >> 19) + -15) << 14; + + /* DataTypeConversion: '/Data Type Conversion3' incorporates: + * Product: '/Divide4' + * Saturate: '/Saturation1' + */ + rtb_DataTypeConversion3_i = (uint8_t)((((uint32_t)i & 16384U) != 0U) + (i >> + 15)); + + /* MultiPortSwitch: '/Multiport Switch2' incorporates: + * Lookup_n-D: '/1-D Lookup Table1' + * Lookup_n-D: '/1-D Lookup Table12' + * Lookup_n-D: '/1-D Lookup Table2' + * Lookup_n-D: '/1-D Lookup Table3' + * Lookup_n-D: '/1-D Lookup Table4' + * Lookup_n-D: '/1-D Lookup Table5' + * Saturate: '/Saturation8' + */ + switch (rtb_timer_out) { + case 0: + rtb_MultiportSwitch_gq = look1_iu16lu64n48ts16Ds32_binlcs(rtb_out_ew, + rtConstP.pooled79, &g_assVTG_RR_LV0[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table3' + * Lookup_n-D: '/1-D Lookup Table' + * Saturate: '/Saturation8' + */ + rtb_MultiportSwitch_jq = look1_iu16bs16lu64n32ts16Ds32_binlcs(rtb_out_ew, + rtConstP.pooled51, &g_assINCAR_TG_RR_LV0[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * MultiPortSwitch: '/Multiport Switch1' + */ + rtb_VectorConcatenate_lb[0] = g_assVR_INC_Y1_LV0[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[1] = g_assVR_INC_Y2_LV0[rtb_DataTypeConversion3_i - + 1]; + break; + + case 1: + rtb_MultiportSwitch_gq = look1_iu16lu64n48ts16Ds32_binlcs(rtb_out_ew, + rtConstP.pooled79, &g_assVTG_RR_LV1[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table4' + * Lookup_n-D: '/1-D Lookup Table1' + * Saturate: '/Saturation8' + */ + rtb_MultiportSwitch_jq = look1_iu16bs16lu64n32ts16Ds32_binlcs(rtb_out_ew, + rtConstP.pooled51, &g_assINCAR_TG_RR_LV1[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * MultiPortSwitch: '/Multiport Switch1' + */ + rtb_VectorConcatenate_lb[0] = g_assVR_INC_Y1_LV1[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[1] = g_assVR_INC_Y2_LV1[rtb_DataTypeConversion3_i - + 1]; + break; + + case 2: + rtb_MultiportSwitch_gq = look1_iu16lu64n48ts16Ds32_binlcs(rtb_out_ew, + rtConstP.pooled79, &g_assVTG_RR_LV1[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table5' + * Lookup_n-D: '/1-D Lookup Table2' + * Saturate: '/Saturation8' + */ + rtb_MultiportSwitch_jq = look1_iu16bs16lu64n32ts16Ds32_binlcs(rtb_out_ew, + rtConstP.pooled51, &g_assINCAR_TG_RR_LV2[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * MultiPortSwitch: '/Multiport Switch1' + */ + rtb_VectorConcatenate_lb[0] = g_assVR_INC_Y1_LV2[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[1] = g_assVR_INC_Y2_LV2[rtb_DataTypeConversion3_i - + 1]; + break; + + case 3: + rtb_MultiportSwitch_gq = look1_iu16lu64n48ts16Ds32_binlcs(rtb_out_ew, + rtConstP.pooled79, &g_assVTG_RR_LV3[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table12' + * Lookup_n-D: '/1-D Lookup Table3' + * Saturate: '/Saturation8' + */ + rtb_MultiportSwitch_jq = look1_iu16bs16lu64n32ts16Ds32_binlcs(rtb_out_ew, + rtConstP.pooled51, &g_assINCAR_TG_RR_LV3[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * MultiPortSwitch: '/Multiport Switch1' + */ + rtb_VectorConcatenate_lb[0] = g_assVR_INC_Y1_LV3[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[1] = g_assVR_INC_Y2_LV3[rtb_DataTypeConversion3_i - + 1]; + break; + + case 4: + rtb_MultiportSwitch_gq = look1_iu16lu64n48ts16Ds32_binlcs(rtb_out_ew, + rtConstP.pooled79, &g_assVTG_RR_LV4[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table1' + * Lookup_n-D: '/1-D Lookup Table4' + * Saturate: '/Saturation8' + */ + rtb_MultiportSwitch_jq = look1_iu16bs16lu64n32ts16Ds32_binlcs(rtb_out_ew, + rtConstP.pooled51, &g_assINCAR_TG_RR_LV4[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * MultiPortSwitch: '/Multiport Switch1' + */ + rtb_VectorConcatenate_lb[0] = g_assVR_INC_Y1_LV4[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[1] = g_assVR_INC_Y2_LV4[rtb_DataTypeConversion3_i - + 1]; + break; + + default: + rtb_MultiportSwitch_gq = look1_iu16lu64n48ts16Ds32_binlcs(rtb_out_ew, + rtConstP.pooled79, &g_assVTG_RR_LV5[0], 12U); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Lookup_n-D: '/1-D Lookup Table2' + * Lookup_n-D: '/1-D Lookup Table5' + * Saturate: '/Saturation8' + */ + rtb_MultiportSwitch_jq = look1_iu16bs16lu64n32ts16Ds32_binlcs(rtb_out_ew, + rtConstP.pooled51, &g_assINCAR_TG_RR_LV5[0], 12U); + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * MultiPortSwitch: '/Multiport Switch1' + */ + rtb_VectorConcatenate_lb[0] = g_assVR_INC_Y1_LV5[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector' + */ + rtb_VectorConcatenate_lb[1] = g_assVR_INC_Y2_LV5[rtb_DataTypeConversion3_i - + 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch2' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_lb[2] = 0; + + /* MultiPortSwitch: '/Multiport Switch3' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant14' + */ + rtb_VectorConcatenate_lb[3] = g_assVR_INC_Y3_LV0[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant20' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_lb[4] = g_assVR_INC_Y4_LV0[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_jn[0] = g_assVR_INC_X1_LV0[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_jn[1] = g_assVR_INC_X2_LV0[rtb_DataTypeConversion3_i - + 1]; + break; + + case 1: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant15' + */ + rtb_VectorConcatenate_lb[3] = g_assVR_INC_Y3_LV1[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant21' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_lb[4] = g_assVR_INC_Y4_LV1[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_jn[0] = g_assVR_INC_X1_LV1[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_jn[1] = g_assVR_INC_X2_LV1[rtb_DataTypeConversion3_i - + 1]; + break; + + case 2: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant16' + */ + rtb_VectorConcatenate_lb[3] = g_assVR_INC_Y3_LV2[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant22' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_lb[4] = g_assVR_INC_Y4_LV2[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_jn[0] = g_assVR_INC_X1_LV2[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_jn[1] = g_assVR_INC_X2_LV2[rtb_DataTypeConversion3_i - + 1]; + break; + + case 3: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant17' + */ + rtb_VectorConcatenate_lb[3] = g_assVR_INC_Y3_LV3[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant23' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_lb[4] = g_assVR_INC_Y4_LV3[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_jn[0] = g_assVR_INC_X1_LV3[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_jn[1] = g_assVR_INC_X2_LV3[rtb_DataTypeConversion3_i - + 1]; + break; + + case 4: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant12' + */ + rtb_VectorConcatenate_lb[3] = g_assVR_INC_Y3_LV4[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant18' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_lb[4] = g_assVR_INC_Y4_LV4[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_jn[0] = g_assVR_INC_X1_LV4[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_jn[1] = g_assVR_INC_X2_LV4[rtb_DataTypeConversion3_i - + 1]; + break; + + default: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant13' + */ + rtb_VectorConcatenate_lb[3] = g_assVR_INC_Y3_LV5[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant19' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_lb[4] = g_assVR_INC_Y4_LV5[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_jn[0] = g_assVR_INC_X1_LV5[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + * MultiPortSwitch: '/Multiport Switch2' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_jn[1] = g_assVR_INC_X2_LV5[rtb_DataTypeConversion3_i - + 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch3' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_jn[2] = 0; + + /* MultiPortSwitch: '/Multiport Switch3' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant14' + */ + rtb_VectorConcatenate_jn[3] = g_assVR_INC_X3_LV0[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant20' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_jn[4] = g_assVR_INC_X4_LV0[rtb_DataTypeConversion3_i - + 1]; + break; + + case 1: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant15' + */ + rtb_VectorConcatenate_jn[3] = g_assVR_INC_X3_LV1[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant21' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_jn[4] = g_assVR_INC_X4_LV1[rtb_DataTypeConversion3_i - + 1]; + break; + + case 2: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant16' + */ + rtb_VectorConcatenate_jn[3] = g_assVR_INC_X3_LV2[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant22' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_jn[4] = g_assVR_INC_X4_LV2[rtb_DataTypeConversion3_i - + 1]; + break; + + case 3: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant17' + */ + rtb_VectorConcatenate_jn[3] = g_assVR_INC_X3_LV3[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant23' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_jn[4] = g_assVR_INC_X4_LV3[rtb_DataTypeConversion3_i - + 1]; + break; + + case 4: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant12' + */ + rtb_VectorConcatenate_jn[3] = g_assVR_INC_X3_LV4[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant18' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_jn[4] = g_assVR_INC_X4_LV4[rtb_DataTypeConversion3_i - + 1]; + break; + + default: + /* Selector: '/Selector2' incorporates: + * Constant: '/Constant13' + */ + rtb_VectorConcatenate_jn[3] = g_assVR_INC_X3_LV5[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector3' incorporates: + * Constant: '/Constant19' + * MultiPortSwitch: '/Multiport Switch4' + * Selector: '/Selector2' + */ + rtb_VectorConcatenate_jn[4] = g_assVR_INC_X4_LV5[rtb_DataTypeConversion3_i - + 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch3' */ + + /* Lookup_n-D: '/2.5 FLU_tg_incar' incorporates: + * DataStoreRead: '/Data Store Read38' + * Sum: '/2.5. X = Inc_Tg - Incar_fb' + */ + rtb_MultiportSwitch_ci = look1_is16lu64n32Ds32_binlcn((int16_t) + (rtb_MultiportSwitch_jq - rtDW.Incar_RR), rtb_VectorConcatenate_jn, + rtb_VectorConcatenate_lb, 4U); + + /* MultiPortSwitch: '/Multiport Switch1' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + */ + rtb_VectorConcatenate_dw[0] = g_assVR_AMB_Y1_LV0[rtb_DataTypeConversion3_i - + 1]; + break; + + case 1: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + */ + rtb_VectorConcatenate_dw[0] = g_assVR_AMB_Y1_LV1[rtb_DataTypeConversion3_i - + 1]; + break; + + case 2: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + */ + rtb_VectorConcatenate_dw[0] = g_assVR_AMB_Y1_LV2[rtb_DataTypeConversion3_i - + 1]; + break; + + case 3: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + */ + rtb_VectorConcatenate_dw[0] = g_assVR_AMB_Y1_LV3[rtb_DataTypeConversion3_i - + 1]; + break; + + case 4: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + */ + rtb_VectorConcatenate_dw[0] = g_assVR_AMB_Y1_LV4[rtb_DataTypeConversion3_i - + 1]; + break; + + default: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + */ + rtb_VectorConcatenate_dw[0] = g_assVR_AMB_Y1_LV5[rtb_DataTypeConversion3_i - + 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_dw[1] = 0; + + /* MultiPortSwitch: '/Multiport Switch2' */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + */ + rtb_VectorConcatenate_dw[2] = g_assVR_AMB_Y2_LV0[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_pg[0] = g_assVR_AMB_X1_LV0[rtb_DataTypeConversion3_i - + 1]; + break; + + case 1: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + */ + rtb_VectorConcatenate_dw[2] = g_assVR_AMB_Y2_LV1[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_pg[0] = g_assVR_AMB_X1_LV1[rtb_DataTypeConversion3_i - + 1]; + break; + + case 2: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + */ + rtb_VectorConcatenate_dw[2] = g_assVR_AMB_Y2_LV2[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_pg[0] = g_assVR_AMB_X1_LV2[rtb_DataTypeConversion3_i - + 1]; + break; + + case 3: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + */ + rtb_VectorConcatenate_dw[2] = g_assVR_AMB_Y2_LV3[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_pg[0] = g_assVR_AMB_X1_LV3[rtb_DataTypeConversion3_i - + 1]; + break; + + case 4: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + */ + rtb_VectorConcatenate_dw[2] = g_assVR_AMB_Y2_LV4[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_pg[0] = g_assVR_AMB_X1_LV4[rtb_DataTypeConversion3_i - + 1]; + break; + + default: + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + */ + rtb_VectorConcatenate_dw[2] = g_assVR_AMB_Y2_LV5[rtb_DataTypeConversion3_i - + 1]; + + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * MultiPortSwitch: '/Multiport Switch1' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_pg[0] = g_assVR_AMB_X1_LV5[rtb_DataTypeConversion3_i - + 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch2' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + */ + rtb_VectorConcatenate_pg[1] = 0; + + /* MultiPortSwitch: '/Multiport Switch2' incorporates: + * Constant: '/Constant10' + * Constant: '/Constant11' + * Constant: '/Constant6' + * Constant: '/Constant7' + * Constant: '/Constant8' + * Constant: '/Constant9' + */ + switch (rtb_timer_out) { + case 0: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVR_AMB_X2_LV0[i]; + } + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant6' + */ + rtb_VectorConcatenate_pg[2] = g_assVR_AMB_X2_LV0[rtb_DataTypeConversion3_i - + 1]; + break; + + case 1: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVR_AMB_X2_LV1[i]; + } + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant7' + */ + rtb_VectorConcatenate_pg[2] = g_assVR_AMB_X2_LV1[rtb_DataTypeConversion3_i - + 1]; + break; + + case 2: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVR_AMB_X2_LV2[i]; + } + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant8' + */ + rtb_VectorConcatenate_pg[2] = g_assVR_AMB_X2_LV2[rtb_DataTypeConversion3_i - + 1]; + break; + + case 3: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVR_AMB_X2_LV3[i]; + } + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant9' + */ + rtb_VectorConcatenate_pg[2] = g_assVR_AMB_X2_LV3[rtb_DataTypeConversion3_i - + 1]; + break; + + case 4: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVR_AMB_X2_LV4[i]; + } + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant10' + */ + rtb_VectorConcatenate_pg[2] = g_assVR_AMB_X2_LV4[rtb_DataTypeConversion3_i - + 1]; + break; + + default: + for (i = 0; i < 7; i++) { + rtb_uDLookupTable7_g[i] = g_assVR_AMB_X2_LV5[i]; + } + + /* Selector: '/Selector1' incorporates: + * Constant: '/Constant11' + */ + rtb_VectorConcatenate_pg[2] = g_assVR_AMB_X2_LV5[rtb_DataTypeConversion3_i - + 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch2' */ + + /* Lookup_n-D: '/2.6 FLU_tg_amb' */ + rtb_X = look1_is16lu64n32Ds32_binlcn(rtb_FLU_tg_correct_aa, + rtb_VectorConcatenate_pg, rtb_VectorConcatenate_dw, 2U); + + /* Switch: '/Switch' incorporates: + * Constant: '/manual3' + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * DataStoreRead: '/AF from Start Control' + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write22' + * Logic: '/Logical Operator' + * RelationalOperator: '/Equal4' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * Switch: '/Switch3' + * UnitDelay: '/Unit Delay3' + */ + if ((rtDW.step_start_controle_rear == 0) || (rtDW.step_start_controle_rear == + 1) || (rtDW.step_start_controle_rear == 2)) { + rtb_out_ew = rtDW.Blower_RR; + } else if (rtDW.UnitDelay3_DSTATE == 0) { + /* DataStoreWrite: '/Data Store Write22' incorporates: + * Switch: '/Switch3' + */ + rtb_out_ew = rtB.MultiportSwitch_c; + } else { + /* MultiPortSwitch: '/Multiport Switch2' incorporates: + * Constant: '/Constant10' + * Constant: '/Constant11' + * Constant: '/Constant6' + * Constant: '/Constant7' + * Constant: '/Constant8' + * Constant: '/Constant9' + * Switch: '/Switch3' + */ + switch (rtb_timer_out) { + case 0: + for (i = 0; i < 7; i++) { + rtb_MultiportSwitch1_d[i] = g_assVR_SUN_X2_LV0[i]; + } + break; + + case 1: + for (i = 0; i < 7; i++) { + rtb_MultiportSwitch1_d[i] = g_assVR_SUN_X2_LV1[i]; + } + break; + + case 2: + for (i = 0; i < 7; i++) { + rtb_MultiportSwitch1_d[i] = g_assVR_SUN_X2_LV2[i]; + } + break; + + case 3: + for (i = 0; i < 7; i++) { + rtb_MultiportSwitch1_d[i] = g_assVR_SUN_X2_LV3[i]; + } + break; + + case 4: + for (i = 0; i < 7; i++) { + rtb_MultiportSwitch1_d[i] = g_assVR_SUN_X2_LV4[i]; + } + break; + + default: + for (i = 0; i < 7; i++) { + rtb_MultiportSwitch1_d[i] = g_assVR_SUN_X2_LV5[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch2' */ + + /* Selector: '/Selector1' incorporates: + * Switch: '/Switch3' + */ + rtb_VectorConcatenate_pg[2] = + rtb_MultiportSwitch1_d[rtb_DataTypeConversion3_i - 1]; + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Switch: '/Switch3' + */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_pg[1] = g_assVR_SUN_X1_LV0[rtb_DataTypeConversion3_i + - 1]; + break; + + case 1: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_pg[1] = g_assVR_SUN_X1_LV1[rtb_DataTypeConversion3_i + - 1]; + break; + + case 2: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_pg[1] = g_assVR_SUN_X1_LV2[rtb_DataTypeConversion3_i + - 1]; + break; + + case 3: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_pg[1] = g_assVR_SUN_X1_LV3[rtb_DataTypeConversion3_i + - 1]; + break; + + case 4: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_pg[1] = g_assVR_SUN_X1_LV4[rtb_DataTypeConversion3_i + - 1]; + break; + + default: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_pg[1] = g_assVR_SUN_X1_LV5[rtb_DataTypeConversion3_i + - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + * Switch: '/Switch3' + */ + rtb_VectorConcatenate_pg[0] = 0; + + /* MultiPortSwitch: '/Multiport Switch2' incorporates: + * Constant: '/Constant10' + * Constant: '/Constant11' + * Constant: '/Constant6' + * Constant: '/Constant7' + * Constant: '/Constant8' + * Constant: '/Constant9' + * Switch: '/Switch3' + */ + switch (rtb_timer_out) { + case 0: + for (i = 0; i < 7; i++) { + rtb_MultiportSwitch1_d[i] = g_assVR_SUN_Y2_LV0[i]; + } + break; + + case 1: + for (i = 0; i < 7; i++) { + rtb_MultiportSwitch1_d[i] = g_assVR_SUN_Y2_LV1[i]; + } + break; + + case 2: + for (i = 0; i < 7; i++) { + rtb_MultiportSwitch1_d[i] = g_assVR_SUN_Y2_LV2[i]; + } + break; + + case 3: + for (i = 0; i < 7; i++) { + rtb_MultiportSwitch1_d[i] = g_assVR_SUN_Y2_LV3[i]; + } + break; + + case 4: + for (i = 0; i < 7; i++) { + rtb_MultiportSwitch1_d[i] = g_assVR_SUN_Y2_LV4[i]; + } + break; + + default: + for (i = 0; i < 7; i++) { + rtb_MultiportSwitch1_d[i] = g_assVR_SUN_Y2_LV5[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch2' */ + + /* Selector: '/Selector1' incorporates: + * Selector: '/Selector1' + * Switch: '/Switch3' + */ + rtb_VectorConcatenate_dw[2] = + rtb_MultiportSwitch1_d[rtb_DataTypeConversion3_i - 1]; + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Switch: '/Switch3' + */ + switch (rtb_timer_out) { + case 0: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_dw[1] = g_assVR_SUN_Y1_LV0[rtb_DataTypeConversion3_i + - 1]; + break; + + case 1: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant1' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_dw[1] = g_assVR_SUN_Y1_LV1[rtb_DataTypeConversion3_i + - 1]; + break; + + case 2: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant2' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_dw[1] = g_assVR_SUN_Y1_LV2[rtb_DataTypeConversion3_i + - 1]; + break; + + case 3: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant3' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_dw[1] = g_assVR_SUN_Y1_LV3[rtb_DataTypeConversion3_i + - 1]; + break; + + case 4: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant4' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_dw[1] = g_assVR_SUN_Y1_LV4[rtb_DataTypeConversion3_i + - 1]; + break; + + default: + /* Selector: '/Selector' incorporates: + * Constant: '/Constant5' + * Selector: '/Selector1' + */ + rtb_VectorConcatenate_dw[1] = g_assVR_SUN_Y1_LV5[rtb_DataTypeConversion3_i + - 1]; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant24' + * Switch: '/Switch3' + */ + rtb_VectorConcatenate_dw[0] = 0; + + /* Lookup_n-D: '/2.6 FLU_tg_amb' incorporates: + * DataStoreRead: '/Data Store Read41' + * Switch: '/Switch3' + */ + rtb_Add_be = look1_bs16ts16DdId_binlc(rtDW.Sun_R, rtb_VectorConcatenate_pg, + rtb_VectorConcatenate_dw, 2U); + + /* Sum: '/FLU_tg_correct' incorporates: + * Switch: '/Switch3' + */ + rtb_FLU_tg_correct_aa = (int16_t)floor((double)((rtb_MultiportSwitch_gq + + rtb_MultiportSwitch_ci) + rtb_X) + rtb_Add_be); + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * Constant: '/Constant2' + * Constant: '/Constant3' + * Constant: '/Constant4' + * Constant: '/Constant5' + * Switch: '/Switch3' + */ + switch (rtb_timer_out) { + case 0: + for (i = 0; i < 7; i++) { + rtb_MultiportSwitch1_d[i] = g_assVR_MAX_LV0[i]; + } + break; + + case 1: + for (i = 0; i < 7; i++) { + rtb_MultiportSwitch1_d[i] = g_assVR_MAX_LV1[i]; + } + break; + + case 2: + for (i = 0; i < 7; i++) { + rtb_MultiportSwitch1_d[i] = g_assVR_MAX_LV2[i]; + } + break; + + case 3: + for (i = 0; i < 7; i++) { + rtb_MultiportSwitch1_d[i] = g_assVR_MAX_LV3[i]; + } + break; + + case 4: + for (i = 0; i < 7; i++) { + rtb_MultiportSwitch1_d[i] = g_assVR_MAX_LV4[i]; + } + break; + + default: + for (i = 0; i < 7; i++) { + rtb_MultiportSwitch1_d[i] = g_assVR_MAX_LV5[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* Selector: '/Selector' incorporates: + * Selector: '/Selector1' + * Switch: '/Switch3' + */ + rtb_MultiportSwitch_jq = rtb_MultiportSwitch1_d[rtb_DataTypeConversion3_i - + 1]; + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + * Switch: '/Switch3' + */ + if (rtb_FLU_tg_correct_aa <= rtb_MultiportSwitch_jq) { + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * Constant: '/Constant2' + * Constant: '/Constant3' + * Constant: '/Constant4' + * Constant: '/Constant5' + */ + switch (rtb_timer_out) { + case 0: + for (i = 0; i < 7; i++) { + rtb_MultiportSwitch1_d[i] = g_assVR_MIN_LV0[i]; + } + break; + + case 1: + for (i = 0; i < 7; i++) { + rtb_MultiportSwitch1_d[i] = g_assVR_MIN_LV1[i]; + } + break; + + case 2: + for (i = 0; i < 7; i++) { + rtb_MultiportSwitch1_d[i] = g_assVR_MIN_LV2[i]; + } + break; + + case 3: + for (i = 0; i < 7; i++) { + rtb_MultiportSwitch1_d[i] = g_assVR_MIN_LV3[i]; + } + break; + + case 4: + for (i = 0; i < 7; i++) { + rtb_MultiportSwitch1_d[i] = g_assVR_MIN_LV4[i]; + } + break; + + default: + for (i = 0; i < 7; i++) { + rtb_MultiportSwitch1_d[i] = g_assVR_MIN_LV5[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* Selector: '/Selector' incorporates: + * Selector: '/Selector1' + */ + rtb_MultiportSwitch_jq = rtb_MultiportSwitch1_d[rtb_DataTypeConversion3_i + - 1]; + + /* Switch: '/Switch' incorporates: + * RelationalOperator: '/UpperRelop' + * Selector: '/Selector' + */ + if (rtb_FLU_tg_correct_aa >= rtb_MultiportSwitch_jq) { + rtb_MultiportSwitch_jq = rtb_FLU_tg_correct_aa; + } + + /* End of Switch: '/Switch' */ + } + + /* End of Switch: '/Switch2' */ + + /* Sum: '/Add' incorporates: + * DataStoreRead: '/Data Store Read' + * DataTypeConversion: '/Data Type Conversion' + * DataTypeConversion: '/Data Type Conversion1' + * DataTypeConversion: '/Data Type Conversion1' + * Gain: '/Gain' + * MATLAB Function: '/func g_ascAUTO_STEP_AF_F' + * Product: '/Product' + * Switch: '/Switch3' + */ + rtb_Add_be = (double)g_ascAUTO_STEP_AF_F[(int8_t)rtDW.CCU_AUTOMODE_RR - 1] * + 0.01 * (double)(uint16_t)rtb_MultiportSwitch_jq + (double)(uint16_t) + rtb_MultiportSwitch_jq; + + /* DataTypeConversion: '/Data Type Conversion2' incorporates: + * Switch: '/Switch3' + */ + if (fabs(rtb_Add_be) >= 0.5) { + /* DataStoreWrite: '/Data Store Write22' */ + rtb_out_ew = (uint16_t)floor(rtb_Add_be + 0.5); + } else { + /* DataStoreWrite: '/Data Store Write22' */ + rtb_out_ew = 0U; + } + + /* End of DataTypeConversion: '/Data Type Conversion2' */ + } + + /* End of Switch: '/Switch' */ + + /* MATLAB Function: '/is_ending_with_5' */ + is_ending_with_5(rtb_out_nc, &rtb_Compare_i5); + + /* MATLAB Function: '/is_ending_with_5' */ + /* : correct_after_time = [g_assCORRECT_AF_MAX_LV0; g_assCORRECT_AF_MAX_LV1; g_assCORRECT_AF_MAX_LV2; g_assCORRECT_AF_MAX_LV3; g_assCORRECT_AF_MAX_LV4; g_assCORRECT_AF_MAX_LV5]; */ + /* : y = correct_after_time(LVL + 1, idivide(SET - 16 + 1, 2)); */ + /* : correct_rate = [g_assCORRECT_AF_RATE_LV0; g_assCORRECT_AF_RATE_LV1; g_assCORRECT_AF_RATE_LV2; g_assCORRECT_AF_RATE_LV3; g_assCORRECT_AF_RATE_LV4; g_assCORRECT_AF_RATE_LV5]; */ + /* : disp('all correction rate:') */ + /* : disp(correct_rate) */ + /* : y = correct_rate(LVL + 1, idivide(SET - 16 + 1, 2)); */ + /* : disp('correction rate:') */ + /* : disp(y) */ + /* : correct_after_time = [g_assCORRECT_AF_TIME_FL_LV0; g_assCORRECT_AF_TIME_FL_LV1; g_assCORRECT_AF_TIME_FL_LV2; g_assCORRECT_AF_TIME_FL_LV3; g_assCORRECT_AF_TIME_FL_LV4; g_assCORRECT_AF_TIME_FL_LV5]; */ + /* : y = correct_after_time(LVL + 1, idivide(SET - 16 + 1, 2)); */ + is_ending_with_5(rtb_out_h0, &rtb_Compare_i5); + + /* DataStoreRead: '/Data Store Read1' incorporates: + * UnitDelay: '/Unit Delay1' + */ + /* : correct_after_time = [g_assCORRECT_AF_MAX_LV0; g_assCORRECT_AF_MAX_LV1; g_assCORRECT_AF_MAX_LV2; g_assCORRECT_AF_MAX_LV3; g_assCORRECT_AF_MAX_LV4; g_assCORRECT_AF_MAX_LV5]; */ + /* : y = correct_after_time(LVL + 1, idivide(SET - 16 + 1, 2)); */ + /* : correct_rate = [g_assCORRECT_AF_RATE_LV0; g_assCORRECT_AF_RATE_LV1; g_assCORRECT_AF_RATE_LV2; g_assCORRECT_AF_RATE_LV3; g_assCORRECT_AF_RATE_LV4; g_assCORRECT_AF_RATE_LV5]; */ + /* : y = correct_rate(LVL + 1, idivide(SET - 16 + 1, 2)); */ + /* : correct_after_time = [g_assCORRECT_AF_TIME_FR_LV0; g_assCORRECT_AF_TIME_FR_LV1; g_assCORRECT_AF_TIME_FR_LV2; g_assCORRECT_AF_TIME_FR_LV3; g_assCORRECT_AF_TIME_FR_LV4; g_assCORRECT_AF_TIME_FR_LV5]; */ + /* : y = correct_after_time(LVL + 1, idivide(SET - 16 + 1, 2)); */ + rtDW.UnitDelay1_DSTATE_j = rtDW.CCU_MODE_FR; + + /* DataStoreRead: '/Data Store Read2' incorporates: + * UnitDelay: '/Unit Delay2' + */ + rtDW.UnitDelay2_DSTATE = rtDW.CCU_MODE_RL; + + /* DataStoreRead: '/Data Store Read3' incorporates: + * UnitDelay: '/Unit Delay3' + */ + rtDW.UnitDelay3_DSTATE = rtDW.CCU_MODE_RR; + + /* DataStoreRead: '/Data Store Read46' incorporates: + * UnitDelay: '/Unit Delay' + */ + rtDW.UnitDelay_DSTATE_ne = rtDW.CCU_MODE_FL; + + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreRead: '/Data Store Read73' + * DataStoreRead: '/Data Store Read82' + * DataStoreRead: '/Data Store Read83' + * DataStoreWrite: '/Data Store Write32' + */ + rtDW.LIN4_CCU_Req_Model.CCU_Ionization_Req = rtDW.CCU_Ionization; + rtDW.LIN4_CCU_Req_Model.CCU_AromaIntens_Req = rtDW.Aroma_status; + rtDW.LIN4_CCU_Req_Model.CCU_AirQS_Req = rtDW.Air_status; + rtDW.LIN4_CCU_Req_Model.CCU_fHVAC_Pos_Val = 0U; + rtDW.LIN4_CCU_Req_Model.CCU_rHVAC_Pos_Val = 0U; + rtDW.LIN4_CCU_Req_Model.CCU_batChiller_Pos_Val = 0U; + rtDW.LIN4_CCU_Req_Model.CCU_eeChiller_Pos_Val = 0U; + + /* Chart: '/Chart' incorporates: + * DataStoreRead: '/Data Store Read75' + * DataStoreRead: '/Data Store Read78' + */ + if (rtDW.is_active_c248_HVAC_model == 0U) { + rtDW.is_active_c248_HVAC_model = 1U; + rtDW.is_c248_HVAC_model = IN_MAX_AC_OFF; + + /* : MaxAC_Active = false; */ + /* : condition=0; */ + rtB.condition = 0.0; + } else if (rtDW.is_c248_HVAC_model == IN_MAX_AC_OFF) { + /* : sf_internal_predicateOutput = CCU_AC_MAX==1; */ + if (rtDW.CCU_AC_MAX == 1) { + rtDW.is_c248_HVAC_model = IN_MAX_AC_ON; + } + + /* case IN_MAX_AC_ON: */ + /* : sf_internal_predicateOutput = CCU_AC_MAX==0; */ + } else if (rtDW.CCU_AC_MAX == 0) { + rtDW.is_c248_HVAC_model = IN_MAX_AC_OFF; + + /* : MaxAC_Active = false; */ + /* : condition=0; */ + rtB.condition = 0.0; + + /* : if amb > g_assAC_CUT_OFF_AMB_F(1) */ + } else if (rtDW.AMB > g_assAC_CUT_OFF_AMB_F[0]) { + /* : condition = 1; */ + rtB.condition = 1.0; + } else { + /* : else */ + /* : condition = 2; */ + rtB.condition = 2.0; + } + + /* End of Chart: '/Chart' */ + + /* DataStoreWrite: '/Data Store Write34' */ + rtDW.condition_ac_max = rtB.condition; + + /* MATLAB Function: '/MATLAB Function1' incorporates: + * DataStoreWrite: '/Data Store Write29' + */ + /* : IDLE = uint8(0); */ + /* : LO_RIGHT = uint8(1); */ + /* : HI_RIGHT = uint8(8); */ + /* : LO_LEFT = uint8(10); */ + /* : LO_BOTH = uint8(11); */ + /* : LO_4ZONE = uint8(22); */ + /* : HI_LEFT = uint8(80); */ + /* : HI_BOTH = uint8(88); */ + /* : HI_4ZONE = uint8(99); */ + /* : CAN_LoHi_Front = IDLE; */ + rtDW.CAN_LoHi_Front = 0U; + + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreWrite: '/Data Store Write' + * MATLAB Function: '/MATLAB Function1' + */ + /* : CAN_LoHi_Rear = IDLE; */ + rtDW.dbgCAN_Logic_State_model.Logic_LoHi_Rear = 0U; + + /* MATLAB Function: '/MATLAB Function1' incorporates: + * DataStoreRead: '/Data Store Read40' + * DataStoreRead: '/Data Store Read41' + * DataStoreRead: '/Data Store Read42' + * DataStoreRead: '/Data Store Read61' + * DataStoreWrite: '/Data Store Write29' + */ + /* : is_HI_4zone = (FL == 2 && FR == 2 && RL == 2 && RR == 2); */ + /* : is_LO_4zone = (FL == 1 && FR == 1 && RL == 1 && RR == 1); */ + rtb_FailCond_jb = ((rtDW.LO_HI_MODE_FL == 1) && (rtDW.LO_HI_MODE_FR == 1) && + (rtDW.LO_HI_MODE_RL == 1) && (rtDW.LO_HI_MODE_RR == 1)); + + /* : if is_HI_4zone */ + if ((rtDW.LO_HI_MODE_FL == 2) && (rtDW.LO_HI_MODE_FR == 2) && + (rtDW.LO_HI_MODE_RL == 2) && (rtDW.LO_HI_MODE_RR == 2)) { + /* : CAN_LoHi_Front = HI_4ZONE; */ + rtDW.CAN_LoHi_Front = 99U; + + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreWrite: '/Data Store Write29' + * DataStoreWrite: '/Data Store Write' + */ + /* : CAN_LoHi_Rear = HI_4ZONE; */ + rtDW.dbgCAN_Logic_State_model.Logic_LoHi_Rear = 99U; + } else { + if ((rtDW.LO_HI_MODE_FL == 2) && (rtDW.LO_HI_MODE_FR == 2)) { + /* : elseif FL == 2 && FR == 2 */ + /* : CAN_LoHi_Front = HI_BOTH; */ + rtDW.CAN_LoHi_Front = 88U; + } else if (rtDW.LO_HI_MODE_FL == 2) { + /* : elseif FL == 2 */ + /* : CAN_LoHi_Front = HI_LEFT; */ + rtDW.CAN_LoHi_Front = 80U; + } else if (rtDW.LO_HI_MODE_FR == 2) { + /* : elseif FR == 2 */ + /* : CAN_LoHi_Front = HI_RIGHT; */ + rtDW.CAN_LoHi_Front = 8U; + } else if (rtb_FailCond_jb) { + /* : elseif is_LO_4zone */ + /* : CAN_LoHi_Front = LO_4ZONE; */ + rtDW.CAN_LoHi_Front = 22U; + } else if ((rtDW.LO_HI_MODE_FL == 1) && (rtDW.LO_HI_MODE_FR == 1)) { + /* : elseif FL == 1 && FR == 1 */ + /* : CAN_LoHi_Front = LO_BOTH; */ + rtDW.CAN_LoHi_Front = 11U; + } else if (rtDW.LO_HI_MODE_FL == 1) { + /* : elseif FL == 1 */ + /* : CAN_LoHi_Front = LO_LEFT; */ + rtDW.CAN_LoHi_Front = 10U; + } else if (rtDW.LO_HI_MODE_FR == 1) { + /* : elseif FR == 1 */ + /* : CAN_LoHi_Front = LO_RIGHT; */ + rtDW.CAN_LoHi_Front = 1U; + } + + if ((rtDW.LO_HI_MODE_RL == 2) && (rtDW.LO_HI_MODE_RR == 2)) { + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + /* : elseif RL == 2 && RR == 2 */ + /* : CAN_LoHi_Rear = HI_BOTH; */ + rtDW.dbgCAN_Logic_State_model.Logic_LoHi_Rear = 88U; + } else if (rtDW.LO_HI_MODE_RL == 2) { + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + /* : elseif RL == 2 */ + /* : CAN_LoHi_Rear = HI_LEFT; */ + rtDW.dbgCAN_Logic_State_model.Logic_LoHi_Rear = 80U; + } else if (rtDW.LO_HI_MODE_RR == 2) { + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + /* : elseif RR == 2 */ + /* : CAN_LoHi_Rear = HI_RIGHT; */ + rtDW.dbgCAN_Logic_State_model.Logic_LoHi_Rear = 8U; + } else if (rtb_FailCond_jb) { + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + /* : elseif is_LO_4zone */ + /* : CAN_LoHi_Rear = LO_4ZONE; */ + rtDW.dbgCAN_Logic_State_model.Logic_LoHi_Rear = 22U; + } else if ((rtDW.LO_HI_MODE_RL == 1) && (rtDW.LO_HI_MODE_RR == 1)) { + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + /* : elseif RL == 1 && RR == 1 */ + /* : CAN_LoHi_Rear = LO_BOTH; */ + rtDW.dbgCAN_Logic_State_model.Logic_LoHi_Rear = 11U; + } else if (rtDW.LO_HI_MODE_RL == 1) { + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + /* : elseif RL == 1 */ + /* : CAN_LoHi_Rear = LO_LEFT; */ + rtDW.dbgCAN_Logic_State_model.Logic_LoHi_Rear = 10U; + } else if (rtDW.LO_HI_MODE_RR == 1) { + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + /* : elseif RR == 1 */ + /* : CAN_LoHi_Rear = LO_RIGHT; */ + rtDW.dbgCAN_Logic_State_model.Logic_LoHi_Rear = 1U; + } + } + + /* DataStoreRead: '/Data Store Read87' incorporates: + * Outport: '/DRS_output' + */ + /* : if is_HI_4zone */ + rtY.DRS_output[0] = rtDW.DRS_SFL; + + /* DataStoreRead: '/Data Store Read88' incorporates: + * Outport: '/DRS_output' + */ + rtY.DRS_output[1] = rtDW.DRS_SFR; + + /* DataStoreRead: '/Data Store Read89' incorporates: + * Outport: '/DRS_output' + */ + rtY.DRS_output[2] = rtDW.DRS_CFL; + + /* DataStoreRead: '/Data Store Read90' incorporates: + * Outport: '/DRS_output' + */ + rtY.DRS_output[3] = rtDW.DRS_CFR; + + /* DataStoreRead: '/Data Store Read91' incorporates: + * Outport: '/DRS_output' + */ + rtY.DRS_output[4] = rtDW.DRS_CRL; + + /* DataStoreRead: '/Data Store Read92' incorporates: + * Outport: '/DRS_output' + */ + rtY.DRS_output[5] = rtDW.DRS_CRR; + + /* DataStoreRead: '/Data Store Read93' incorporates: + * Outport: '/DRS_output' + */ + rtY.DRS_output[6] = rtDW.DRS_SRL; + + /* DataStoreRead: '/Data Store Read94' incorporates: + * Outport: '/DRS_output' + */ + rtY.DRS_output[7] = rtDW.DRS_SRR; + + /* Chart: '/Synchronization stateflow chart' */ + if (rtDW.is_active_c618_HVAC_model == 0U) { + rtDW.is_active_c618_HVAC_model = 1U; + rtDW.is_c618_HVAC_model = IN_NO_SYNC; + enter_atomic_NO_SYNC(); + } else { + guard1 = false; + guard2 = false; + switch (rtDW.is_c618_HVAC_model) { + case IN_FRONT_ONLY: + rtB.sync_front = 1U; + rtB.sync_rear = 0U; + rtB.sync_all = 0U; + + /* : sf_internal_predicateOutput = enable_full_sync; */ + if (rtDW.enable_full_sync != 0) { + rtDW.is_c618_HVAC_model = IN_FULL_SYNC; + enter_atomic_FULL_SYNC(); + + /* : sf_internal_predicateOutput = disable_front_sync; */ + } else if (rtDW.disable_front_sync != 0) { + guard1 = true; + + /* : sf_internal_predicateOutput = enable_rear_sync; */ + } else if (rtDW.enable_rear_sync != 0) { + rtDW.is_c618_HVAC_model = IN_SEPARATE_FRONT_AND_REAR; + enter_atomic_SEPARATE_FRONT_AND_REAR(); + + /* : sf_internal_predicateOutput = changed_FR_params; */ + } else if (rtDW.changed_FR_params != 0) { + guard1 = true; + } + break; + + case IN_FULL_SYNC: + rtB.sync_front = 0U; + rtB.sync_rear = 0U; + rtB.sync_all = 1U; + + /* : sf_internal_predicateOutput = disable_front_sync; */ + if (rtDW.disable_front_sync != 0) { + guard2 = true; + + /* : sf_internal_predicateOutput = enable_front_sync; */ + } else if ((rtDW.enable_front_sync != 0) || (rtDW.enable_rear_sync != 0)) + { + rtDW.is_c618_HVAC_model = IN_SEPARATE_FRONT_AND_REAR; + enter_atomic_SEPARATE_FRONT_AND_REAR(); + + /* : sf_internal_predicateOutput = enable_rear_sync; */ + /* : sf_internal_predicateOutput = changed_FR_params; */ + } else if (rtDW.changed_FR_params != 0) { + guard2 = true; + + /* : sf_internal_predicateOutput = changed_RL_params || changed_RR_params; */ + } else if ((rtDW.changed_RL_params != 0) || (rtDW.changed_RR_params != 0)) + { + rtDW.is_c618_HVAC_model = IN_FRONT_ONLY; + enter_atomic_FRONT_ONLY(); + } + break; + + case IN_NO_SYNC: + rtB.sync_front = 0U; + rtB.sync_rear = 0U; + rtB.sync_all = 0U; + + /* : sf_internal_predicateOutput = enable_front_sync; */ + if (rtDW.enable_front_sync != 0) { + rtDW.is_c618_HVAC_model = IN_FRONT_ONLY; + enter_atomic_FRONT_ONLY(); + + /* : sf_internal_predicateOutput = enable_full_sync; */ + } else if (rtDW.enable_full_sync != 0) { + rtDW.is_c618_HVAC_model = IN_FULL_SYNC; + enter_atomic_FULL_SYNC(); + + /* : sf_internal_predicateOutput = enable_rear_sync; */ + } else if (rtDW.enable_rear_sync != 0) { + rtDW.is_c618_HVAC_model = IN_REAR_ONLY; + enter_atomic_REAR_ONLY(); + } + break; + + case IN_REAR_ONLY: + rtB.sync_front = 0U; + rtB.sync_rear = 1U; + rtB.sync_all = 0U; + + /* : sf_internal_predicateOutput = enable_full_sync; */ + if (rtDW.enable_full_sync != 0) { + rtDW.is_c618_HVAC_model = IN_FULL_SYNC; + enter_atomic_FULL_SYNC(); + + /* : sf_internal_predicateOutput = enable_front_sync; */ + } else if (rtDW.enable_front_sync != 0) { + rtDW.is_c618_HVAC_model = IN_SEPARATE_FRONT_AND_REAR; + enter_atomic_SEPARATE_FRONT_AND_REAR(); + + /* : sf_internal_predicateOutput = disable_rear_sync || changed_RL_params; */ + } else if ((rtDW.disable_rear_sync != 0) || (rtDW.changed_RL_params != 0)) + { + rtDW.is_c618_HVAC_model = IN_NO_SYNC; + enter_atomic_NO_SYNC(); + } + break; + + default: + /* case IN_SEPARATE_FRONT_AND_REAR: */ + rtB.sync_front = 1U; + rtB.sync_rear = 1U; + rtB.sync_all = 0U; + + /* : sf_internal_predicateOutput = enable_full_sync; */ + if (rtDW.enable_full_sync != 0) { + rtDW.is_c618_HVAC_model = IN_FULL_SYNC; + enter_atomic_FULL_SYNC(); + + /* : sf_internal_predicateOutput = disable_rear_sync || changed_RL_params; */ + } else if ((rtDW.disable_rear_sync != 0) || (rtDW.changed_RL_params != 0)) + { + rtDW.is_c618_HVAC_model = IN_FRONT_ONLY; + enter_atomic_FRONT_ONLY(); + + /* : sf_internal_predicateOutput = disable_front_sync; */ + } else if ((rtDW.disable_front_sync != 0) || (rtDW.changed_FR_params != 0)) + { + rtDW.is_c618_HVAC_model = IN_REAR_ONLY; + enter_atomic_REAR_ONLY(); + } else { + /* : sf_internal_predicateOutput = changed_FR_params; */ + } + break; + } + + if (guard2) { + rtDW.is_c618_HVAC_model = IN_REAR_ONLY; + enter_atomic_REAR_ONLY(); + } + + if (guard1) { + rtDW.is_c618_HVAC_model = IN_NO_SYNC; + enter_atomic_NO_SYNC(); + } + } + + /* End of Chart: '/Synchronization stateflow chart' */ + + /* DataStoreWrite: '/Data Store Write15' */ + rtb_timer_out = rtB.sync_rear; + + /* DataStoreWrite: '/Data Store Write16' */ + rtb_DataTypeConversion3_i = rtB.sync_all; + + /* DataStoreWrite: '/Data Store Write17' */ + CCU_FRONT_SYNC = rtB.sync_front; + + /* Outputs for Enabled SubSystem: '/Front Left Valves - manual directions' incorporates: + * EnablePort: '/Enable' + */ + /* RelationalOperator: '/Equal2' incorporates: + * Constant: '/Constant2' + * DataStoreRead: '/Data Store Read44' + */ + if (rtDW.CCU_MODE_FL == 0) { + /* Sum: '/Add' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * Constant: '/Constant2' + * DataStoreRead: '/Data Store Read10' + * DataStoreRead: '/Data Store Read4' + * DataStoreRead: '/Data Store Read5' + * Gain: '/Gain1' + * Gain: '/Gain2' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator1' + * RelationalOperator: '/Relational Operator2' + */ + rtb_out_nc = (uint16_t)(((uint32_t)((rtDW.CCU_FACE_FL == 1) << 1) + + (uint32_t)(rtDW.CCU_DEF_FL == 1)) + (uint32_t)((rtDW.CCU_FOOT_FL == 1) << + 2)); + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant10' + * Constant: '/Constant11' + * Constant: '/Constant4' + * Constant: '/Constant5' + * Constant: '/Constant6' + * Constant: '/Constant7' + * Constant: '/Constant8' + * Constant: '/Constant9' + * DataStoreWrite: '/Data Store Write' + */ + switch (rtb_out_nc) { + case 0: + rtDW.Index_mode_FL_manual = 0U; + break; + + case 1: + rtDW.Index_mode_FL_manual = 80U; + break; + + case 2: + rtDW.Index_mode_FL_manual = 10U; + break; + + case 3: + rtDW.Index_mode_FL_manual = 100U; + break; + + case 4: + rtDW.Index_mode_FL_manual = 60U; + break; + + case 5: + rtDW.Index_mode_FL_manual = 70U; + break; + + case 6: + rtDW.Index_mode_FL_manual = 20U; + break; + + default: + rtDW.Index_mode_FL_manual = 90U; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* MATLAB Function: '/Valves for Hi_Level' */ + /* : out = g_ausFLOW_FR_DE2VALVE; */ + /* : out = g_ausFLOW_FR_VE2VALVE; */ + ValvesforHi_Level(rtb_out_ea); + + /* MATLAB Function: '/Valves for Foot + Def' */ + /* : out = g_ausFLOW_FR_FO2VALVE; */ + ValvesforFootDef(rtb_out_iy); + + /* MATLAB Function: '/Valves for Bi Level' */ + ValvesforBiLevel(rtb_out_il); + + /* MATLAB Function: '/Valves for Tri-Level' */ + ValvesforTriLevel(rtB.MultiportSwitch_j); + + /* MultiPortSwitch: '/Multiport Switch' */ + switch (rtb_out_nc) { + case 0: + /* MultiPortSwitch: '/Multiport Switch' */ + for (i = 0; i < 9; i++) { + rtB.MultiportSwitch_j[i] = 0U; + } + break; + + case 1: + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * MATLAB Function: '/Valves for Def' + */ + for (i = 0; i < 9; i++) { + rtB.MultiportSwitch_j[i] = g_ausFLOW_FR_DE2VALVE[i]; + } + break; + + case 2: + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * MATLAB Function: '/Valves for Vent mode' + */ + for (i = 0; i < 9; i++) { + rtB.MultiportSwitch_j[i] = g_ausFLOW_FR_VE2VALVE[i]; + } + break; + + case 3: + /* MultiPortSwitch: '/Multiport Switch' */ + for (i = 0; i < 9; i++) { + rtB.MultiportSwitch_j[i] = rtb_out_ea[i]; + } + break; + + case 4: + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * MATLAB Function: '/Valves for Foot' + */ + for (i = 0; i < 9; i++) { + rtB.MultiportSwitch_j[i] = g_ausFLOW_FR_FO2VALVE[i]; + } + break; + + case 5: + /* MultiPortSwitch: '/Multiport Switch' */ + for (i = 0; i < 9; i++) { + rtB.MultiportSwitch_j[i] = rtb_out_iy[i]; + } + break; + + case 6: + /* MultiPortSwitch: '/Multiport Switch' */ + for (i = 0; i < 9; i++) { + rtB.MultiportSwitch_j[i] = rtb_out_il[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch' */ + } + + /* End of RelationalOperator: '/Equal2' */ + /* End of Outputs for SubSystem: '/Front Left Valves - manual directions' */ + + /* RelationalOperator: '/Equal1' incorporates: + * Constant: '/manual' + * DataStoreRead: '/Data Store Read46' + */ + rtb_Compare_i5 = (rtDW.CCU_MODE_FL == 0); + + /* Saturate: '/Saturation4' incorporates: + * DataStoreRead: '/Data Store Read' + */ + if (rtDW.LEVEL <= 5) { + rtb_Saturation4_f = rtDW.LEVEL; + } else { + rtb_Saturation4_f = 5U; + } + + /* End of Saturate: '/Saturation4' */ + + /* Saturate: '/Saturation' incorporates: + * DataStoreRead: '/Data Store Read16' + */ + if (rtDW.CCU_SET_FL > 290) { + rtb_out_h0 = 290U; + } else if (rtDW.CCU_SET_FL < 170) { + rtb_out_h0 = 170U; + } else { + rtb_out_h0 = rtDW.CCU_SET_FL; + } + + /* MATLAB Function: '/MODE_for_set_and_lvl' incorporates: + * Gain: '/Gain2' + * Saturate: '/Saturation' + */ + MODE_for_set_and_lvl(rtb_Saturation4_f, (int16_t)((52429U * rtb_out_h0) >> 19), + &rtb_DataTypeConversion3_gz); + + /* MATLAB Function: '/valves_front_left' */ + /* : modes_array = [ */ + /* : g_ausFLOW_FR_VE2VALVE; */ + /* : g_ausFLOW_FR_BIVALVE; */ + /* : g_ausFLOW_FR_BI2VALVE; */ + /* : g_ausFLOW_FR_AF2VALVE; */ + /* : g_ausFLOW_FR_AF2VALVE_SUMMER]; */ + /* : index = idivide(MODE, 10); */ + /* : get_valves = modes_array(index, :); */ + i = (int32_t)trunc((double)rtb_DataTypeConversion3_gz / 10.0); + for (index_start_0 = 0; index_start_0 < 9; index_start_0++) { + tmp[5 * index_start_0] = g_ausFLOW_FR_VE2VALVE[index_start_0]; + tmp[5 * index_start_0 + 1] = g_ausFLOW_FR_BIVALVE[index_start_0]; + tmp[5 * index_start_0 + 2] = g_ausFLOW_FR_BI2VALVE[index_start_0]; + tmp[5 * index_start_0 + 3] = g_ausFLOW_FR_AF2VALVE[index_start_0]; + tmp[5 * index_start_0 + 4] = g_ausFLOW_FR_AF2VALVE_SUMMER[index_start_0]; + + /* Switch: '/Switch' incorporates: + * MultiPortSwitch: '/Multiport Switch' + */ + if (rtb_Compare_i5) { + rtb_out_ea[index_start_0] = rtB.MultiportSwitch_j[index_start_0]; + } else { + rtb_out_ea[index_start_0] = tmp[(5 * index_start_0 + i) - 1]; + } + + /* End of Switch: '/Switch' */ + } + + /* End of MATLAB Function: '/valves_front_left' */ + + /* If: '/If' incorporates: + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/mode from Start Control' + * Logic: '/Logical Operator' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + */ + if (((rtDW.step_start_controle_front == 0) || (rtDW.step_start_controle_front == + 1) || (rtDW.step_start_controle_front == 2)) && (rtDW.Mode_FL > 0)) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem' incorporates: + * ActionPort: '/Action Port' + */ + /* MATLAB Function: '/valves for mode' incorporates: + * DataStoreRead: '/mode from Start Control' + */ + /* : modes_array = [ */ + /* : g_ausFLOW_FR_VE2VALVE; */ + /* : g_ausFLOW_FR_BIVALVE; */ + /* : g_ausFLOW_FR_BI2VALVE; */ + /* : g_ausFLOW_FR_AF2VALVE; */ + /* : g_ausFLOW_FR_AF2VALVE_SUMMER; */ + /* : g_ausFLOW_FR_FO2VALVE; */ + /* : g_ausFLOW_FR_FD2VALVE; */ + /* : g_ausFLOW_FR_DE2VALVE; */ + /* : g_ausFLOW_FR_TR2VALVE; */ + /* : g_ausFLOW_FR_HI2VALVE; */ + /* : g_ausFLOW_FR_BIVALVE_MANUAL */ + /* : ]; */ + /* : index = idivide(MODE, 10); */ + /* : get_valves = modes_array(index, :); */ + i = (int32_t)trunc((double)rtDW.Mode_FL / 10.0); + for (index_start_0 = 0; index_start_0 < 9; index_start_0++) { + tmp_0[11 * index_start_0] = g_ausFLOW_FR_VE2VALVE[index_start_0]; + tmp_0[11 * index_start_0 + 1] = g_ausFLOW_FR_BIVALVE[index_start_0]; + tmp_0[11 * index_start_0 + 2] = g_ausFLOW_FR_BI2VALVE[index_start_0]; + tmp_0[11 * index_start_0 + 3] = g_ausFLOW_FR_AF2VALVE[index_start_0]; + tmp_0[11 * index_start_0 + 4] = g_ausFLOW_FR_AF2VALVE_SUMMER[index_start_0]; + tmp_0[11 * index_start_0 + 5] = g_ausFLOW_FR_FO2VALVE[index_start_0]; + tmp_0[11 * index_start_0 + 6] = g_ausFLOW_FR_FD2VALVE[index_start_0]; + tmp_0[11 * index_start_0 + 7] = g_ausFLOW_FR_DE2VALVE[index_start_0]; + tmp_0[11 * index_start_0 + 8] = g_ausFLOW_FR_TR2VALVE[index_start_0]; + tmp_0[11 * index_start_0 + 9] = g_ausFLOW_FR_HI2VALVE[index_start_0]; + tmp_0[11 * index_start_0 + 10] = g_ausFLOW_FR_BIVALVE_MANUAL[index_start_0]; + + /* SignalConversion generated from: '/get_valves' incorporates: + * Merge: '/Merge' + */ + rtb_out_iy[index_start_0] = tmp_0[(11 * index_start_0 + i) - 1]; + } + + /* End of MATLAB Function: '/valves for mode' */ + /* End of Outputs for SubSystem: '/If Action Subsystem' */ + } else { + /* Outputs for IfAction SubSystem: '/If Action Subsystem1' incorporates: + * ActionPort: '/Action Port' + */ + /* SignalConversion generated from: '/valves_in' incorporates: + * Merge: '/Merge' + * Switch: '/Switch' + */ + for (i = 0; i < 9; i++) { + rtb_out_iy[i] = rtb_out_ea[i]; + } + + /* End of SignalConversion generated from: '/valves_in' */ + /* End of Outputs for SubSystem: '/If Action Subsystem1' */ + } + + /* End of If: '/If' */ + + /* Switch: '/Switch' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read4' + */ + if (rtDW.CCU_MODE_FL <= 0) { + rtDW.Index_mode_FL_auto = rtDW.Index_mode_FL_manual; + } + + /* MATLAB Function: '/param index for mode' incorporates: + * Switch: '/Switch' + */ + paramindexformode(rtDW.Index_mode_FL_auto, &rtb_Add_p4); + for (i = 0; i < 5; i++) { + /* SignalConversion generated from: '/ SFunction ' incorporates: + * MATLAB Function: '/FL valves * percent DRS' + */ + rtb_out_il[i] = rtb_out_iy[i]; + } + + /* SignalConversion generated from: '/ SFunction ' incorporates: + * DataStoreRead: '/Data Store Read2' + * MATLAB Function: '/FL valves * percent DRS' + * Sum: '/Sum' + */ + rtb_out_il[5] = (uint16_t)(rtb_out_iy[5] + rtDW.Valve_individual_foot_FL); + rtb_out_il[7] = rtb_out_iy[7]; + rtb_out_il[6] = (uint16_t)(rtb_out_iy[6] + rtDW.Valve_individual_foot_FL); + rtb_out_il[8] = rtb_out_iy[8]; + + /* MATLAB Function: '/FL valves * percent DRS' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read2' + * DataTypeConversion: '/Data Type Conversion' + */ + /* : index_start = (param_index - 1) * 3 + 1; */ + /* MW:begin MISRA2012:D4.1 CERT-C:INT30-C 'Justifying MISRA CPP rule violation' */ + rtb_Subtract = (uint8_t)rtb_Add_p4 - 1U; + + /* MW:end MISRA2012:D4.1 CERT-C:INT30-C */ + if ((uint8_t)rtb_Add_p4 - 1U > (uint8_t)rtb_Add_p4) { + rtb_Subtract = 0U; + } + + i = (int32_t)(rtb_Subtract * 3U); + if ((uint32_t)i > 255U) { + i = 255; + } + + index_start_0 = (int32_t)((uint32_t)i + 1U); + if ((uint32_t)i + 1U > 255U) { + index_start_0 = 255; + } + + /* : if DRS_FLS == 0 */ + if (rtDW.DRS_SFL == 0) { + /* : side_percent = uint8(0); */ + rtb_DataTypeConversion1_lq = 0U; + } else { + /* : else */ + /* : side_percent = g_aucFRONT_SIDE_DRS_PERCENT(index_start + 3 - DRS_FLS); */ + i = (int32_t)((uint8_t)index_start_0 + 3U); + if ((uint8_t)index_start_0 + 3U > 255U) { + i = 255; + } + + rtb_Subtract = (uint32_t)i - /*MW:OvSatOk*/ rtDW.DRS_SFL; + if (rtb_Subtract > (uint32_t)i) { + rtb_Subtract = 0U; + } + + rtb_DataTypeConversion1_lq = g_aucFRONT_SIDE_DRS_PERCENT[(int32_t) + rtb_Subtract - 1]; + } + + /* : if DRS_FLC == 0 */ + if (rtDW.DRS_CFL == 0) { + /* : center_percent = uint8(0); */ + rtb_DataTypeConversion1_nc = 0U; + } else { + /* : else */ + /* : center_percent = g_aucFRONT_CENT_DRS_PERCENT(index_start + 3 - DRS_FLC); */ + i = (int32_t)((uint8_t)index_start_0 + 3U); + if ((uint8_t)index_start_0 + 3U > 255U) { + i = 255; + } + + rtb_Subtract = (uint32_t)i - /*MW:OvSatOk*/ rtDW.DRS_CFL; + if (rtb_Subtract > (uint32_t)i) { + rtb_Subtract = 0U; + } + + rtb_DataTypeConversion1_nc = g_aucFRONT_CENT_DRS_PERCENT[(int32_t) + rtb_Subtract - 1]; + } + + /* : y = uint16(valves); */ + /* : y(1) = uint8(double(valves(1)) * (double(side_percent) / 100)); */ + i = (int32_t)rt_roundd((double)rtb_DataTypeConversion1_lq / 100.0 * (double) + rtb_out_il[0]); + if (i < 256) { + rtb_out_il[0] = (uint16_t)i; + } else { + rtb_out_il[0] = 255U; + } + + /* : y(2) = uint8(double(valves(2)) * (double(center_percent) / 100)); */ + i = (int32_t)rt_roundd((double)rtb_DataTypeConversion1_nc / 100.0 * (double) + rtb_out_il[1]); + if (i < 256) { + rtb_out_il[1] = (uint16_t)i; + } else { + rtb_out_il[1] = 255U; + } + + /* Switch: '/Switch' incorporates: + * Constant: '/manual' + * DataStoreRead: '/Data Store Read46' + * RelationalOperator: '/Equal1' + */ + if (rtDW.CCU_MODE_FL == 0) { + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Constant: '/LOW1' + * Constant: '/LOW2' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read3' + * Gain: '/Gain1' + * RelationalOperator: '/Relational Operator1' + * RelationalOperator: '/Relational Operator2' + * Sum: '/Add' + */ + switch ((int32_t)((uint32_t)((rtDW.LO_HI_MODE_FR == 1) << 1) + (uint32_t) + (rtDW.LO_HI_MODE_FL == 1))) { + case 1: + /* Assignment: '/valves[6]' incorporates: + * Constant: '/Constant' + * Switch: '/Switch' + */ + rtb_out_il[5] = 0U; + break; + + case 2: + /* Assignment: '/valves[8]' incorporates: + * Constant: '/Constant' + * Switch: '/Switch' + */ + rtb_out_il[7] = 0U; + break; + + case 3: + /* Assignment: '/valves[6]' incorporates: + * Assignment: '/valves[8]' + * Constant: '/Constant' + * Switch: '/Switch' + */ + rtb_out_il[5] = 0U; + + /* Assignment: '/valves[8]' incorporates: + * Constant: '/Constant' + * Switch: '/Switch' + */ + rtb_out_il[7] = 0U; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch' */ + } + + /* End of Switch: '/Switch' */ + + /* Switch: '/Switch1' incorporates: + * Constant: '/manual1' + * DataStoreRead: '/Data Store Read1' + * RelationalOperator: '/Equal2' + */ + if (rtDW.CCU_MODE_FR == 0) { + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Constant: '/LOW' + * Constant: '/LOW3' + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read4' + * Gain: '/Gain1' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator3' + * Sum: '/Add' + */ + switch ((int32_t)((uint32_t)((rtDW.LO_HI_MODE_RR == 1) << 1) + (uint32_t) + (rtDW.LO_HI_MODE_RL == 1))) { + case 1: + /* Assignment: '/valves[6]' incorporates: + * Constant: '/Constant' + * Switch: '/Switch1' + */ + rtb_out_il[5] = 0U; + break; + + case 2: + /* Assignment: '/valves[8]' incorporates: + * Constant: '/Constant' + * Switch: '/Switch1' + */ + rtb_out_il[7] = 0U; + break; + + case 3: + /* Assignment: '/valves[6]' incorporates: + * Assignment: '/valves[8]' + * Constant: '/Constant' + * Switch: '/Switch1' + */ + rtb_out_il[5] = 0U; + + /* Assignment: '/valves[8]' incorporates: + * Constant: '/Constant' + * Switch: '/Switch1' + */ + rtb_out_il[7] = 0U; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch' */ + } + + /* End of Switch: '/Switch1' */ + + /* Switch: '/Switch' incorporates: + * Constant: '/manual' + * DataStoreRead: '/Data Store Read46' + * RelationalOperator: '/Equal1' + * Switch: '/Switch1' + */ + if (rtDW.CCU_MODE_RL == 0) { + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Constant: '/HI' + * Constant: '/HI1' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read3' + * Gain: '/Gain1' + * RelationalOperator: '/Relational Operator1' + * RelationalOperator: '/Relational Operator2' + * Sum: '/Add' + */ + switch ((int32_t)((uint32_t)((rtDW.LO_HI_MODE_FR == 2) << 1) + (uint32_t) + (rtDW.LO_HI_MODE_FL == 2))) { + case 1: + for (i = 0; i < 9; i++) { + /* Switch: '/Switch' incorporates: + * Assignment: '/valves[8]' + * SignalConversion generated from: '/valves[6]' + * Switch: '/Switch1' + */ + rtb_out_iy[i] = rtb_out_il[i]; + } + + /* Assignment: '/valves[6]' incorporates: + * Assignment: '/valves[8]' + * Constant: '/Constant' + * Switch: '/Switch' + */ + rtb_out_iy[5] = 0U; + + /* Assignment: '/valves[8]' incorporates: + * Constant: '/Constant' + * Switch: '/Switch' + */ + rtb_out_iy[7] = 0U; + break; + + case 2: + for (i = 0; i < 9; i++) { + /* Switch: '/Switch' incorporates: + * Assignment: '/valves[8]' + * SignalConversion generated from: '/valves[6]' + * Switch: '/Switch1' + */ + rtb_out_iy[i] = rtb_out_il[i]; + } + + /* Assignment: '/valves[6]' incorporates: + * Assignment: '/valves[8]' + * Constant: '/Constant' + * Switch: '/Switch' + */ + rtb_out_iy[5] = 0U; + + /* Assignment: '/valves[8]' incorporates: + * Constant: '/Constant' + * Switch: '/Switch' + */ + rtb_out_iy[7] = 0U; + break; + + case 3: + for (i = 0; i < 9; i++) { + /* Switch: '/Switch' incorporates: + * Assignment: '/valves[8]' + * SignalConversion generated from: '/valves[6]' + * Switch: '/Switch1' + */ + rtb_out_iy[i] = rtb_out_il[i]; + } + + /* Assignment: '/valves[6]' incorporates: + * Assignment: '/valves[8]' + * Constant: '/Constant' + * Switch: '/Switch' + */ + rtb_out_iy[5] = 0U; + + /* Assignment: '/valves[8]' incorporates: + * Constant: '/Constant' + * Switch: '/Switch' + */ + rtb_out_iy[7] = 0U; + break; + + default: + /* Switch: '/Switch' incorporates: + * Switch: '/Switch1' + */ + for (i = 0; i < 9; i++) { + rtb_out_iy[i] = rtb_out_il[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch' */ + } else { + for (i = 0; i < 9; i++) { + rtb_out_iy[i] = rtb_out_il[i]; + } + } + + /* End of Switch: '/Switch' */ + + /* Switch: '/Switch6' incorporates: + * DataStoreRead: '/Data Store Read12' + */ + if (rtDW.CCU_AC_MAX <= 0) { + /* Switch: '/Switch2' incorporates: + * Constant: '/manual1' + * Constant: '/HI' + * Constant: '/HI1' + * Constant: '/HI2' + * Constant: '/HI3' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read3' + * DataStoreRead: '/Data Store Read4' + * Logic: '/Logical Operator' + * RelationalOperator: '/Equal2' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator1' + * RelationalOperator: '/Relational Operator2' + * RelationalOperator: '/Relational Operator3' + * Switch: '/Switch1' + */ + if ((rtDW.LO_HI_MODE_FL == 2) || (rtDW.LO_HI_MODE_FR == 2) || + (rtDW.LO_HI_MODE_RL == 2) || (rtDW.LO_HI_MODE_RR == 2)) { + /* DataStoreWrite: '/Data Store Write23' incorporates: + * Switch: '/Switch1' + */ + for (i = 0; i < 9; i++) { + rtb_out_ea[i] = rtb_out_il[i]; + } + } else if (rtDW.CCU_MODE_FR == 0) { + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Constant: '/HI' + * Constant: '/HI1' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read3' + * Gain: '/Gain1' + * RelationalOperator: '/Relational Operator1' + * RelationalOperator: '/Relational Operator2' + * Sum: '/Add' + * Switch: '/Switch1' + */ + switch ((int32_t)((uint32_t)((rtDW.LO_HI_MODE_FR == 2) << 1) + (uint32_t) + (rtDW.LO_HI_MODE_FL == 2))) { + case 1: + for (i = 0; i < 9; i++) { + /* DataStoreWrite: '/Data Store Write23' incorporates: + * Assignment: '/valves[6]' + * SignalConversion generated from: '/valves[6]' + * Switch: '/Switch' + */ + rtb_out_ea[i] = rtb_out_iy[i]; + } + + /* Assignment: '/valves[6]' incorporates: + * Constant: '/Constant' + * DataStoreWrite: '/Data Store Write23' + */ + rtb_out_ea[5] = 0U; + break; + + case 2: + for (i = 0; i < 9; i++) { + /* DataStoreWrite: '/Data Store Write23' incorporates: + * Assignment: '/valves[8]' + * SignalConversion generated from: '/valves[8]' + * Switch: '/Switch' + */ + rtb_out_ea[i] = rtb_out_iy[i]; + } + break; + + case 3: + for (i = 0; i < 9; i++) { + /* DataStoreWrite: '/Data Store Write23' incorporates: + * Assignment: '/valves[8]' + * SignalConversion generated from: '/valves[8]' + * Switch: '/Switch' + */ + rtb_out_ea[i] = rtb_out_iy[i]; + } + break; + + default: + for (i = 0; i < 9; i++) { + /* DataStoreWrite: '/Data Store Write23' incorporates: + * Switch: '/Switch' + * Switch: '/Switch1' + */ + rtb_out_ea[i] = rtb_out_iy[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch' */ + } else { + for (i = 0; i < 9; i++) { + /* DataStoreWrite: '/Data Store Write23' incorporates: + * Switch: '/Switch' + * Switch: '/Switch1' + */ + rtb_out_ea[i] = rtb_out_iy[i]; + } + } + + /* End of Switch: '/Switch2' */ + } + + /* End of Switch: '/Switch6' */ + + /* Sum: '/Add' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * Constant: '/Constant2' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read3' + * Gain: '/Gain1' + * Gain: '/Gain2' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator1' + * RelationalOperator: '/Relational Operator2' + */ + rtb_out_nc = (uint16_t)(((uint32_t)((rtDW.CCU_FACE_FR == 1) << 1) + (uint32_t) + (rtDW.CCU_DEF_FR == 1)) + (uint32_t)((rtDW.CCU_FOOT_FR == 1) << 2)); + + /* MATLAB Function: '/Valves for Hi_Level' */ + /* : out = g_ausFLOW_FR_DE2VALVE; */ + /* : out = g_ausFLOW_FR_VE2VALVE; */ + ValvesforHi_Level(rtb_out_il); + + /* MATLAB Function: '/Valves for Foot + Def' */ + /* : out = g_ausFLOW_FR_FO2VALVE; */ + ValvesforFootDef(rtb_out_p3); + + /* MATLAB Function: '/Valves for Bi Level' */ + ValvesforBiLevel(rtb_out_n); + + /* MATLAB Function: '/Valves for Tri-Level' */ + ValvesforTriLevel(rtb_out_pw); + + /* Saturate: '/Saturation1' incorporates: + * DataStoreRead: '/Data Store Read17' + */ + if (rtDW.CCU_SET_FR > 290) { + rtb_out_h0 = 290U; + } else if (rtDW.CCU_SET_FR < 170) { + rtb_out_h0 = 170U; + } else { + rtb_out_h0 = rtDW.CCU_SET_FR; + } + + /* MATLAB Function: '/MODE_for_set_and_lvl1' incorporates: + * Gain: '/Gain1' + * Saturate: '/Saturation1' + */ + MODE_for_set_and_lvl(rtb_Saturation4_f, (int16_t)((52429U * rtb_out_h0) >> 19), + &rtb_DataTypeConversion3_gf); + + /* MATLAB Function: '/valves_front_right' */ + valvesformode(rtb_DataTypeConversion3_gf, rtb_out_iy); + + /* Switch: '/Switch1' incorporates: + * Constant: '/manual1' + * DataStoreRead: '/Data Store Read8' + * RelationalOperator: '/Equal2' + */ + if (rtDW.CCU_MODE_FR == 0) { + /* MultiPortSwitch: '/Multiport Switch' */ + switch (rtb_out_nc) { + case 0: + /* Switch: '/Switch1' */ + for (i = 0; i < 9; i++) { + rtb_out_iy[i] = 0U; + } + break; + + case 1: + /* Switch: '/Switch1' incorporates: + * MATLAB Function: '/Valves for Def' + */ + for (i = 0; i < 9; i++) { + rtb_out_iy[i] = g_ausFLOW_FR_DE2VALVE[i]; + } + break; + + case 2: + /* Switch: '/Switch1' incorporates: + * MATLAB Function: '/Valves for Vent mode' + */ + for (i = 0; i < 9; i++) { + rtb_out_iy[i] = g_ausFLOW_FR_VE2VALVE[i]; + } + break; + + case 3: + /* Switch: '/Switch1' */ + for (i = 0; i < 9; i++) { + rtb_out_iy[i] = rtb_out_il[i]; + } + break; + + case 4: + /* Switch: '/Switch1' incorporates: + * MATLAB Function: '/Valves for Foot' + */ + for (i = 0; i < 9; i++) { + rtb_out_iy[i] = g_ausFLOW_FR_FO2VALVE[i]; + } + break; + + case 5: + /* Switch: '/Switch1' */ + for (i = 0; i < 9; i++) { + rtb_out_iy[i] = rtb_out_p3[i]; + } + break; + + case 6: + /* Switch: '/Switch1' */ + for (i = 0; i < 9; i++) { + rtb_out_iy[i] = rtb_out_n[i]; + } + break; + + default: + /* Switch: '/Switch1' */ + for (i = 0; i < 9; i++) { + rtb_out_iy[i] = rtb_out_pw[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch' */ + } + + /* End of Switch: '/Switch1' */ + + /* If: '/If1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/mode from Start Control' + * Logic: '/Logical Operator' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + */ + if (((rtDW.step_start_controle_front == 0) || (rtDW.step_start_controle_front == + 1) || (rtDW.step_start_controle_front == 2)) && (rtDW.Mode_FR > 0)) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem' incorporates: + * ActionPort: '/Action Port' + */ + /* SignalConversion generated from: '/get_valves' incorporates: + * DataStoreRead: '/mode from Start Control' + * MATLAB Function: '/valves for mode' + * Merge: '/Merge' + */ + valvesformode(rtDW.Mode_FR, rtb_out_p3); + + /* End of Outputs for SubSystem: '/If Action Subsystem' */ + } else { + /* Outputs for IfAction SubSystem: '/If Action Subsystem1' incorporates: + * ActionPort: '/Action Port' + */ + /* SignalConversion generated from: '/In1' incorporates: + * Merge: '/Merge' + * Switch: '/Switch1' + */ + for (i = 0; i < 9; i++) { + rtb_out_p3[i] = rtb_out_iy[i]; + } + + /* End of SignalConversion generated from: '/In1' */ + /* End of Outputs for SubSystem: '/If Action Subsystem1' */ + } + + /* End of If: '/If1' */ + + /* Switch: '/Switch' incorporates: + * DataStoreRead: '/Data Store Read4' + * DataStoreRead: '/Data Store Read5' + */ + if (rtDW.CCU_MODE_FR > 0) { + rtDW.Index_mode_FR_manual = rtDW.Index_mode_FR_auto; + } + + /* MATLAB Function: '/param index for mode' incorporates: + * Switch: '/Switch' + */ + paramindexformode(rtDW.Index_mode_FR_manual, &rtb_Add_p4); + for (i = 0; i < 5; i++) { + /* SignalConversion generated from: '/ SFunction ' incorporates: + * MATLAB Function: '/FR valves * percent DRS' + */ + rtb_out_il[i] = rtb_out_p3[i]; + } + + /* SignalConversion generated from: '/ SFunction ' incorporates: + * DataStoreRead: '/Data Store Read2' + * MATLAB Function: '/FR valves * percent DRS' + * Sum: '/Sum' + */ + rtb_out_il[5] = (uint16_t)(rtb_out_p3[5] + rtDW.Valve_individual_foot_FR); + rtb_out_il[7] = rtb_out_p3[7]; + rtb_out_il[6] = (uint16_t)(rtb_out_p3[6] + rtDW.Valve_individual_foot_FR); + rtb_out_il[8] = rtb_out_p3[8]; + + /* MATLAB Function: '/FR valves * percent DRS' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read2' + */ + /* : index_start = (param_index - 1) * 3 + 1; */ + index_start = (rtb_Add_p4 - 1.0) * 3.0 + 1.0; + + /* : if DRS_FRS == 0 */ + if (rtDW.DRS_SFR == 0) { + /* : side_percent = uint8(0); */ + rtb_DataTypeConversion1_lq = 0U; + } else { + /* : else */ + /* : side_percent = g_aucFRONT_SIDE_DRS_PERCENT(index_start + 3 - DRS_FRS); */ + rtb_Add_be = rt_roundd((index_start + 3.0) - (double)rtDW.DRS_SFR); + if (rtb_Add_be < 256.0) { + if (rtb_Add_be >= 0.0) { + rtb_DataTypeConversion1_nc = (uint8_t)rtb_Add_be; + } else { + rtb_DataTypeConversion1_nc = 0U; + } + } else { + rtb_DataTypeConversion1_nc = UINT8_MAX; + } + + rtb_DataTypeConversion1_lq = + g_aucFRONT_SIDE_DRS_PERCENT[rtb_DataTypeConversion1_nc - 1]; + } + + /* : if DRS_FRC == 0 */ + if (rtDW.DRS_CFR == 0) { + /* : center_percent = uint8(0); */ + rtb_DataTypeConversion1_nc = 0U; + } else { + /* : else */ + /* : center_percent = g_aucFRONT_CENT_DRS_PERCENT(index_start + 3 - DRS_FRC); */ + rtb_Add_be = rt_roundd((index_start + 3.0) - (double)rtDW.DRS_CFR); + if (rtb_Add_be < 256.0) { + if (rtb_Add_be >= 0.0) { + rtb_DataTypeConversion1_nc = (uint8_t)rtb_Add_be; + } else { + rtb_DataTypeConversion1_nc = 0U; + } + } else { + rtb_DataTypeConversion1_nc = UINT8_MAX; + } + + rtb_DataTypeConversion1_nc = + g_aucFRONT_CENT_DRS_PERCENT[rtb_DataTypeConversion1_nc - 1]; + } + + /* : y = valves; */ + for (i = 0; i < 9; i++) { + rtb_out_p3[i] = rtb_out_il[i]; + } + + /* : y(3) = uint8(double(valves(3)) * (double(center_percent) / 100)); */ + i = (int32_t)rt_roundd((double)rtb_DataTypeConversion1_nc / 100.0 * (double) + rtb_out_il[2]); + if (i < 256) { + rtb_out_p3[2] = (uint16_t)i; + } else { + rtb_out_p3[2] = 255U; + } + + /* : y(4) = uint8(double(valves(4)) * (double(side_percent) / 100)); */ + i = (int32_t)rt_roundd((double)rtb_DataTypeConversion1_lq / 100.0 * (double) + rtb_out_il[3]); + if (i < 256) { + rtb_out_p3[3] = (uint16_t)i; + } else { + rtb_out_p3[3] = 255U; + } + + /* Switch: '/Switch' incorporates: + * Constant: '/manual' + * DataStoreRead: '/Data Store Read46' + * RelationalOperator: '/Equal1' + */ + if (rtDW.CCU_MODE_FL == 0) { + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Constant: '/LOW1' + * Constant: '/LOW2' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read3' + * Gain: '/Gain1' + * RelationalOperator: '/Relational Operator1' + * RelationalOperator: '/Relational Operator2' + * Sum: '/Add' + */ + switch ((int32_t)((uint32_t)((rtDW.LO_HI_MODE_FR == 1) << 1) + (uint32_t) + (rtDW.LO_HI_MODE_FL == 1))) { + case 1: + /* Assignment: '/valves[6]' incorporates: + * Constant: '/Constant' + * Switch: '/Switch' + */ + rtb_out_p3[5] = 0U; + break; + + case 2: + /* Assignment: '/valves[8]' incorporates: + * Constant: '/Constant' + * Switch: '/Switch' + */ + rtb_out_p3[7] = 0U; + break; + + case 3: + /* Assignment: '/valves[6]' incorporates: + * Assignment: '/valves[8]' + * Constant: '/Constant' + * Switch: '/Switch' + */ + rtb_out_p3[5] = 0U; + + /* Assignment: '/valves[8]' incorporates: + * Constant: '/Constant' + * Switch: '/Switch' + */ + rtb_out_p3[7] = 0U; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch' */ + } + + /* End of Switch: '/Switch' */ + + /* Switch: '/Switch1' incorporates: + * Constant: '/manual1' + * DataStoreRead: '/Data Store Read1' + * RelationalOperator: '/Equal2' + */ + if (rtDW.CCU_MODE_FR == 0) { + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Constant: '/LOW' + * Constant: '/LOW3' + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read4' + * Gain: '/Gain1' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator3' + * Sum: '/Add' + */ + switch ((int32_t)((uint32_t)((rtDW.LO_HI_MODE_RR == 1) << 1) + (uint32_t) + (rtDW.LO_HI_MODE_RL == 1))) { + case 1: + /* Assignment: '/valves[6]' incorporates: + * Constant: '/Constant' + * Switch: '/Switch1' + */ + rtb_out_p3[5] = 0U; + break; + + case 2: + /* Assignment: '/valves[8]' incorporates: + * Constant: '/Constant' + * Switch: '/Switch1' + */ + rtb_out_p3[7] = 0U; + break; + + case 3: + /* Assignment: '/valves[6]' incorporates: + * Assignment: '/valves[8]' + * Constant: '/Constant' + * Switch: '/Switch1' + */ + rtb_out_p3[5] = 0U; + + /* Assignment: '/valves[8]' incorporates: + * Constant: '/Constant' + * Switch: '/Switch1' + */ + rtb_out_p3[7] = 0U; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch' */ + } + + /* End of Switch: '/Switch1' */ + + /* Switch: '/Switch' incorporates: + * Constant: '/manual' + * DataStoreRead: '/Data Store Read46' + * RelationalOperator: '/Equal1' + * Switch: '/Switch1' + */ + if (rtDW.CCU_MODE_RL == 0) { + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Constant: '/HI' + * Constant: '/HI1' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read3' + * Gain: '/Gain1' + * RelationalOperator: '/Relational Operator1' + * RelationalOperator: '/Relational Operator2' + * Sum: '/Add' + */ + switch ((int32_t)((uint32_t)((rtDW.LO_HI_MODE_FR == 2) << 1) + (uint32_t) + (rtDW.LO_HI_MODE_FL == 2))) { + case 1: + for (i = 0; i < 9; i++) { + /* Switch: '/Switch' incorporates: + * Assignment: '/valves[8]' + * SignalConversion generated from: '/valves[6]' + * Switch: '/Switch1' + */ + rtb_out_il[i] = rtb_out_p3[i]; + } + + /* Assignment: '/valves[6]' incorporates: + * Assignment: '/valves[8]' + * Constant: '/Constant' + * Switch: '/Switch' + */ + rtb_out_il[5] = 0U; + + /* Assignment: '/valves[8]' incorporates: + * Constant: '/Constant' + * Switch: '/Switch' + */ + rtb_out_il[7] = 0U; + break; + + case 2: + for (i = 0; i < 9; i++) { + /* Switch: '/Switch' incorporates: + * Assignment: '/valves[8]' + * SignalConversion generated from: '/valves[6]' + * Switch: '/Switch1' + */ + rtb_out_il[i] = rtb_out_p3[i]; + } + + /* Assignment: '/valves[6]' incorporates: + * Assignment: '/valves[8]' + * Constant: '/Constant' + * Switch: '/Switch' + */ + rtb_out_il[5] = 0U; + + /* Assignment: '/valves[8]' incorporates: + * Constant: '/Constant' + * Switch: '/Switch' + */ + rtb_out_il[7] = 0U; + break; + + case 3: + for (i = 0; i < 9; i++) { + /* Switch: '/Switch' incorporates: + * Assignment: '/valves[8]' + * SignalConversion generated from: '/valves[6]' + * Switch: '/Switch1' + */ + rtb_out_il[i] = rtb_out_p3[i]; + } + + /* Assignment: '/valves[6]' incorporates: + * Assignment: '/valves[8]' + * Constant: '/Constant' + * Switch: '/Switch' + */ + rtb_out_il[5] = 0U; + + /* Assignment: '/valves[8]' incorporates: + * Constant: '/Constant' + * Switch: '/Switch' + */ + rtb_out_il[7] = 0U; + break; + + default: + /* Switch: '/Switch' incorporates: + * Switch: '/Switch1' + */ + for (i = 0; i < 9; i++) { + rtb_out_il[i] = rtb_out_p3[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch' */ + } else { + for (i = 0; i < 9; i++) { + rtb_out_il[i] = rtb_out_p3[i]; + } + } + + /* End of Switch: '/Switch' */ + + /* Switch: '/Switch4' incorporates: + * DataStoreRead: '/Data Store Read13' + */ + if (rtDW.CCU_AC_MAX <= 0) { + /* Switch: '/Switch2' incorporates: + * Constant: '/manual1' + * Constant: '/HI' + * Constant: '/HI1' + * Constant: '/HI2' + * Constant: '/HI3' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read3' + * DataStoreRead: '/Data Store Read4' + * Logic: '/Logical Operator' + * RelationalOperator: '/Equal2' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator1' + * RelationalOperator: '/Relational Operator2' + * RelationalOperator: '/Relational Operator3' + * Switch: '/Switch1' + */ + if ((rtDW.LO_HI_MODE_FL == 2) || (rtDW.LO_HI_MODE_FR == 2) || + (rtDW.LO_HI_MODE_RL == 2) || (rtDW.LO_HI_MODE_RR == 2)) { + /* Switch: '/Switch4' incorporates: + * Switch: '/Switch1' + */ + for (i = 0; i < 9; i++) { + rtb_out_iy[i] = rtb_out_p3[i]; + } + } else if (rtDW.CCU_MODE_FR == 0) { + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Constant: '/HI' + * Constant: '/HI1' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read3' + * Gain: '/Gain1' + * RelationalOperator: '/Relational Operator1' + * RelationalOperator: '/Relational Operator2' + * Sum: '/Add' + * Switch: '/Switch1' + */ + switch ((int32_t)((uint32_t)((rtDW.LO_HI_MODE_FR == 2) << 1) + (uint32_t) + (rtDW.LO_HI_MODE_FL == 2))) { + case 1: + for (i = 0; i < 9; i++) { + /* Switch: '/Switch4' incorporates: + * Assignment: '/valves[6]' + * SignalConversion generated from: '/valves[6]' + * Switch: '/Switch' + */ + rtb_out_iy[i] = rtb_out_il[i]; + } + + /* Assignment: '/valves[6]' incorporates: + * Constant: '/Constant' + * Switch: '/Switch4' + */ + rtb_out_iy[5] = 0U; + break; + + case 2: + for (i = 0; i < 9; i++) { + /* Switch: '/Switch4' incorporates: + * Assignment: '/valves[8]' + * SignalConversion generated from: '/valves[8]' + * Switch: '/Switch' + */ + rtb_out_iy[i] = rtb_out_il[i]; + } + + /* Assignment: '/valves[8]' incorporates: + * Constant: '/Constant' + * Switch: '/Switch4' + */ + rtb_out_iy[7] = 0U; + break; + + case 3: + for (i = 0; i < 9; i++) { + /* Switch: '/Switch4' incorporates: + * Assignment: '/valves[8]' + * SignalConversion generated from: '/valves[8]' + * Switch: '/Switch' + */ + rtb_out_iy[i] = rtb_out_il[i]; + } + + /* Assignment: '/valves[8]' incorporates: + * Constant: '/Constant' + * Switch: '/Switch4' + */ + rtb_out_iy[7] = 0U; + break; + + default: + for (i = 0; i < 9; i++) { + /* Switch: '/Switch4' incorporates: + * Switch: '/Switch' + * Switch: '/Switch1' + */ + rtb_out_iy[i] = rtb_out_il[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch' */ + } else { + for (i = 0; i < 9; i++) { + /* Switch: '/Switch4' incorporates: + * Switch: '/Switch' + * Switch: '/Switch1' + */ + rtb_out_iy[i] = rtb_out_il[i]; + } + } + + /* End of Switch: '/Switch2' */ + } + + /* End of Switch: '/Switch4' */ + + /* Assignment: '/ [3-4]' incorporates: + * DataStoreWrite: '/Data Store Write23' + */ + rtb_out_ea[2] = rtb_out_iy[2]; + + /* Assignment: '/ [7-8]' incorporates: + * DataStoreWrite: '/Data Store Write23' + */ + rtb_out_ea[6] = rtb_out_iy[6]; + + /* Assignment: '/ [3-4]' incorporates: + * DataStoreWrite: '/Data Store Write23' + */ + rtb_out_ea[3] = rtb_out_iy[3]; + + /* Assignment: '/ [7-8]' incorporates: + * DataStoreWrite: '/Data Store Write23' + */ + rtb_out_ea[7] = rtb_out_iy[7]; + + /* Outputs for Enabled SubSystem: '/Rear valves left - manual directions' incorporates: + * EnablePort: '/Enable' + */ + /* RelationalOperator: '/Equal2' incorporates: + * Constant: '/Constant2' + * DataStoreRead: '/Data Store Read44' + */ + if (rtDW.CCU_MODE_RL == 0) { + /* Sum: '/Add' incorporates: + * Constant: '/Constant1' + * Constant: '/Constant2' + * DataStoreRead: '/Data Store Read23' + * DataStoreRead: '/Data Store Read24' + * Gain: '/Gain2' + * RelationalOperator: '/Relational Operator1' + * RelationalOperator: '/Relational Operator2' + */ + rtb_out_h0 = (uint16_t)((uint32_t)((rtDW.CCU_FOOT_RL == 1) << 1) + (uint32_t) + (rtDW.CCU_FACE_RL == 1)); + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant4' + * Constant: '/Constant5' + * Constant: '/Constant6' + * Constant: '/Constant7' + * DataStoreWrite: '/Data Store Write' + */ + switch (rtb_out_h0) { + case 0: + rtDW.Index_mode_RL_manual = 0U; + break; + + case 1: + rtDW.Index_mode_RL_manual = 120U; + break; + + case 2: + rtDW.Index_mode_RL_manual = 140U; + break; + + default: + rtDW.Index_mode_RL_manual = 130U; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* MATLAB Function: '/AF for Bi Level' */ + AFforBiLevel_i(rtB.MultiportSwitch_h); + + /* MATLAB Function: '/valves for Vent mode' */ + /* : out = g_ausFLOW_RE_FO2VALVE; */ + valvesforVentmode(rtb_Gain1_o3); + + /* MultiPortSwitch: '/Multiport Switch' */ + switch (rtb_out_h0) { + case 0: + /* MultiPortSwitch: '/Multiport Switch' */ + for (i = 0; i < 6; i++) { + rtB.MultiportSwitch_h[i] = 0U; + } + break; + + case 1: + /* MultiPortSwitch: '/Multiport Switch' */ + for (i = 0; i < 6; i++) { + rtB.MultiportSwitch_h[i] = rtb_Gain1_o3[i]; + } + break; + + case 2: + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * MATLAB Function: '/AF for Foot' + */ + for (i = 0; i < 6; i++) { + rtB.MultiportSwitch_h[i] = g_ausFLOW_RE_FO2VALVE[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch' */ + } + + /* End of RelationalOperator: '/Equal2' */ + /* End of Outputs for SubSystem: '/Rear valves left - manual directions' */ + + /* RelationalOperator: '/Equal3' incorporates: + * Constant: '/manual2' + * DataStoreRead: '/Data Store Read9' + */ + rtb_Compare_i5 = (rtDW.CCU_MODE_RL == 0); + + /* MATLAB Function: '/MODE_by_duct_tg_R_for_LVL' */ + /* : modes_array = [ */ + /* : g_ausMODE_BY_DUCT_TG_R_LV0; */ + /* : g_ausMODE_BY_DUCT_TG_R_LV1; */ + /* : g_ausMODE_BY_DUCT_TG_R_LV2; */ + /* : g_ausMODE_BY_DUCT_TG_R_LV3; */ + /* : g_ausMODE_BY_DUCT_TG_R_LV4; */ + /* : g_ausMODE_BY_DUCT_TG_R_LV5]; */ + /* : get_mode = modes_array(LVL + 1, :); */ + for (i = 0; i < 7; i++) { + tmp_1[6 * i] = g_ausMODE_BY_DUCT_TG_R_LV0[i]; + tmp_1[6 * i + 1] = g_ausMODE_BY_DUCT_TG_R_LV1[i]; + tmp_1[6 * i + 2] = g_ausMODE_BY_DUCT_TG_R_LV2[i]; + tmp_1[6 * i + 3] = g_ausMODE_BY_DUCT_TG_R_LV3[i]; + tmp_1[6 * i + 4] = g_ausMODE_BY_DUCT_TG_R_LV4[i]; + tmp_1[6 * i + 5] = g_ausMODE_BY_DUCT_TG_R_LV5[i]; + rtb_get_mode[i] = tmp_1[6 * i + rtb_Saturation4_f]; + } + + /* End of MATLAB Function: '/MODE_by_duct_tg_R_for_LVL' */ + + /* If: '/If' incorporates: + * DataStoreRead: '/Data Store Read6' + * Sum: '/Subtract' + * UnitDelay: '/Unit Delay' + */ + if ((int16_t)(rtb_y_jh - rtDW.UnitDelay_DSTATE_fq) >= 0) { + /* Outputs for IfAction SubSystem: '/duct_tg RL' incorporates: + * ActionPort: '/Action Port' + */ + /* SignalConversion generated from: '/rear_mode_index' incorporates: + * MATLAB Function: '/increase' + */ + increase(rtb_y_jh, rtb_get_mode, &rtb_out_h0); + + /* End of Outputs for SubSystem: '/duct_tg RL' */ + } else { + /* Outputs for IfAction SubSystem: '/duct_tg RL' incorporates: + * ActionPort: '/Action Port' + */ + /* SignalConversion generated from: '/y' incorporates: + * MATLAB Function: '/decrease' + */ + decrease(rtb_y_jh, rtb_get_mode, &rtb_out_h0); + + /* End of Outputs for SubSystem: '/duct_tg RL' */ + } + + /* End of If: '/If' */ + + /* MATLAB Function: '/valves_rear_left' */ + valves_rear_left_e(rtb_out_h0, rtb_TmpSignalConversionAt1DLookupTable7Inport1); + + /* If: '/If1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/mode from Start Control' + * Logic: '/Logical Operator' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + */ + if (((rtDW.step_start_controle_rear == 0) || (rtDW.step_start_controle_rear == + 1) || (rtDW.step_start_controle_rear == 2)) && (rtDW.Mode_RL > 0)) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem' incorporates: + * ActionPort: '/Action Port' + */ + /* SignalConversion generated from: '/get_valves' incorporates: + * DataStoreRead: '/mode from Start Control' + * MATLAB Function: '/valves_rear_left' + * Merge: '/Merge' + */ + valves_rear_left(rtDW.Mode_RL, rtb_Gain1_o3); + + /* End of Outputs for SubSystem: '/If Action Subsystem' */ + } else { + /* Outputs for IfAction SubSystem: '/If Action Subsystem1' incorporates: + * ActionPort: '/Action Port' + */ + /* SignalConversion generated from: '/In1' */ + for (i = 0; i < 6; i++) { + /* Switch: '/Switch2' incorporates: + * Merge: '/Merge' + * MultiPortSwitch: '/Multiport Switch' + * SignalConversion generated from: '/1-D Lookup Table7' + */ + if (rtb_Compare_i5) { + rtb_Gain1_o3[i] = rtB.MultiportSwitch_h[i]; + } else { + rtb_Gain1_o3[i] = rtb_TmpSignalConversionAt1DLookupTable7Inport1[i]; + } + + /* End of Switch: '/Switch2' */ + } + + /* End of SignalConversion generated from: '/In1' */ + /* End of Outputs for SubSystem: '/If Action Subsystem1' */ + } + + /* End of If: '/If1' */ + + /* Switch: '/Switch' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read4' + */ + /* : switch index_mode */ + if (rtDW.CCU_MODE_RL <= 0) { + rtDW.Index_mode_RL_auto = rtDW.Index_mode_RL_manual; + } + + /* MATLAB Function: '/param index for mode' incorporates: + * Switch: '/Switch' + */ + switch (rtDW.Index_mode_RL_auto) { + case 0U: + /* : case 0 */ + /* : Y = 1; */ + i = 1; + break; + + case 120U: + /* : case 120 */ + /* : Y = 1; */ + i = 1; + break; + + case 130U: + /* : case 130 */ + /* : Y = 2; */ + i = 2; + break; + + case 140U: + /* : case 140 */ + /* : Y = 2; */ + i = 2; + break; + + case 150U: + /* : case 150 */ + /* : Y = 1; */ + i = 1; + break; + + case 160U: + /* : case 160 */ + /* : Y = 3; */ + i = 3; + break; + + case 170U: + /* : case 170 */ + /* : Y = 1; */ + i = 1; + break; + + case 180U: + /* : case 180 */ + /* : Y = 3; */ + i = 3; + break; + + case 190U: + /* : case 190 */ + /* : Y = 1; */ + i = 1; + break; + + case 200U: + /* : case 200 */ + /* : Y = 2; */ + i = 2; + break; + + default: + /* : otherwise */ + /* : Y = 1; */ + i = 1; + break; + } + + /* End of MATLAB Function: '/param index for mode' */ + + /* MATLAB Function: '/RL valves * percent DRS' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read2' + * DataStoreWrite: '/Data Store Write24' + * Merge: '/Merge' + */ + /* : index_start = (param_index - 1) * 3 + 1; */ + index_start_0 = (i - 1) * 3 + 1; + + /* : if DRS_RLS == 0 */ + if (rtDW.DRS_SRL == 0) { + /* : side_percent = uint8(0); */ + rtb_DataTypeConversion1_lq = 0U; + } else { + /* : else */ + /* : side_percent = g_aucREAR_SIDE_DRS_PERCENT_VALVE(index_start + 3 - DRS_RLS); */ + i = (index_start_0 - rtDW.DRS_SRL) + 3; + if (i >= 0) { + rtb_DataTypeConversion1_nc = (uint8_t)i; + } else { + rtb_DataTypeConversion1_nc = 0U; + } + + rtb_DataTypeConversion1_lq = + g_aucREAR_SIDE_DRS_PERCENT_VALVE[rtb_DataTypeConversion1_nc - 1]; + } + + /* : if DRS_RLC == 0 */ + if (rtDW.DRS_CRL == 0) { + /* : center_percent = uint8(0); */ + rtb_DataTypeConversion1_nc = 0U; + } else { + /* : else */ + /* : center_percent = g_aucREAR_CENT_DRS_PERCENT_VALVE(index_start + 3 - DRS_RLC); */ + i = (index_start_0 - rtDW.DRS_CRL) + 3; + if (i >= 0) { + rtb_DataTypeConversion1_nc = (uint8_t)i; + } else { + rtb_DataTypeConversion1_nc = 0U; + } + + rtb_DataTypeConversion1_nc = + g_aucREAR_CENT_DRS_PERCENT_VALVE[rtb_DataTypeConversion1_nc - 1]; + } + + /* : y = valves; */ + /* : y(1) = uint8(double(valves(1)) * (double(side_percent) / 100)); */ + i = (int32_t)rt_roundd((double)rtb_DataTypeConversion1_lq / 100.0 * (double) + rtb_Gain1_o3[0]); + if (i < 256) { + rtb_Gain1_o3[0] = (uint16_t)i; + } else { + rtb_Gain1_o3[0] = 255U; + } + + /* : y(2) = uint8(double(valves(2)) * (double(center_percent) / 100)); */ + i = (int32_t)rt_roundd((double)rtb_DataTypeConversion1_nc / 100.0 * (double) + rtb_Gain1_o3[1]); + if (i < 256) { + rtb_Gain1_o3[1] = (uint16_t)i; + } else { + rtb_Gain1_o3[1] = 255U; + } + + /* End of MATLAB Function: '/RL valves * percent DRS' */ + + /* Outputs for Enabled SubSystem: '/Rear valves right - manual directions' incorporates: + * EnablePort: '/Enable' + */ + /* RelationalOperator: '/Equal3' incorporates: + * Constant: '/Constant3' + * DataStoreRead: '/Data Store Read45' + */ + if (rtDW.CCU_MODE_RR == 0) { + /* Sum: '/Add' incorporates: + * Constant: '/Constant1' + * Constant: '/Constant2' + * DataStoreRead: '/Data Store Read21' + * DataStoreRead: '/Data Store Read22' + * Gain: '/Gain2' + * RelationalOperator: '/Relational Operator1' + * RelationalOperator: '/Relational Operator2' + */ + rtb_out_nj = (uint16_t)((uint32_t)((rtDW.CCU_FOOT_RR == 1) << 1) + (uint32_t) + (rtDW.CCU_FACE_RR == 1)); + + /* MultiPortSwitch: '/Multiport Switch1' incorporates: + * Constant: '/Constant4' + * Constant: '/Constant5' + * Constant: '/Constant6' + * Constant: '/Constant7' + * DataStoreWrite: '/Data Store Write' + */ + switch (rtb_out_nj) { + case 0: + rtDW.Index_mode_RR_manual = 0U; + break; + + case 1: + rtDW.Index_mode_RR_manual = 120U; + break; + + case 2: + rtDW.Index_mode_RR_manual = 140U; + break; + + default: + rtDW.Index_mode_RR_manual = 130U; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* MATLAB Function: '/AF for Bi Level' */ + AFforBiLevel_i(rtB.MultiportSwitch); + + /* MATLAB Function: '/valves for Vent mode' */ + /* : out = g_ausFLOW_RE_FO2VALVE; */ + valvesforVentmode(rtb_TmpSignalConversionAt1DLookupTable7Inport1); + + /* MultiPortSwitch: '/Multiport Switch' */ + switch (rtb_out_nj) { + case 0: + /* MultiPortSwitch: '/Multiport Switch' */ + for (i = 0; i < 6; i++) { + rtB.MultiportSwitch[i] = 0U; + } + break; + + case 1: + /* MultiPortSwitch: '/Multiport Switch' */ + for (i = 0; i < 6; i++) { + rtB.MultiportSwitch[i] = + rtb_TmpSignalConversionAt1DLookupTable7Inport1[i]; + } + break; + + case 2: + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * MATLAB Function: '/AF for Foot' + */ + for (i = 0; i < 6; i++) { + rtB.MultiportSwitch[i] = g_ausFLOW_RE_FO2VALVE[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch' */ + } + + /* End of RelationalOperator: '/Equal3' */ + /* End of Outputs for SubSystem: '/Rear valves right - manual directions' */ + + /* If: '/If1' incorporates: + * DataStoreRead: '/Data Store Read7' + * Sum: '/Subtract1' + * UnitDelay: '/Unit Delay1' + */ + if ((int16_t)(rtDW.Duct_RR_Tg - rtDW.UnitDelay1_DSTATE) >= 0) { + /* Outputs for IfAction SubSystem: '/duct_tg RR' incorporates: + * ActionPort: '/Action Port' + */ + /* SignalConversion generated from: '/y' incorporates: + * MATLAB Function: '/increase' + */ + increase(rtDW.Duct_RR_Tg, rtb_get_mode, &rtb_out_nj); + + /* End of Outputs for SubSystem: '/duct_tg RR' */ + } else { + /* Outputs for IfAction SubSystem: '/duct_tg RR' incorporates: + * ActionPort: '/Action Port' + */ + /* SignalConversion generated from: '/y' incorporates: + * MATLAB Function: '/decrease' + */ + decrease(rtDW.Duct_RR_Tg, rtb_get_mode, &rtb_out_nj); + + /* End of Outputs for SubSystem: '/duct_tg RR' */ + } + + /* End of If: '/If1' */ + + /* MATLAB Function: '/valves_rear_right' */ + valves_rear_left_e(rtb_out_nj, rtb_TmpSignalConversionAt1DLookupTable7Inport1); + + /* If: '/If1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/manual3' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/mode from Start Control' + * DataStoreRead: '/Data Store Read11' + * Logic: '/Logical Operator' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Equal4' + * Switch: '/Switch3' + */ + if (((rtDW.step_start_controle_rear == 0) || (rtDW.step_start_controle_rear == + 1) || (rtDW.step_start_controle_rear == 2)) && (rtDW.Mode_RR > 0)) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem' incorporates: + * ActionPort: '/Action Port' + */ + /* SignalConversion generated from: '/get_valves' incorporates: + * DataStoreRead: '/mode from Start Control' + * MATLAB Function: '/valves_rear_right' + * Merge: '/Merge' + */ + valves_rear_left(rtDW.Mode_RR, + rtb_TmpSignalConversionAt1DLookupTable7Inport1); + + /* End of Outputs for SubSystem: '/If Action Subsystem' */ + } else if (rtDW.CCU_MODE_RR == 0) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem1' incorporates: + * ActionPort: '/Action Port' + */ + /* SignalConversion generated from: '/In1' */ + for (i = 0; i < 6; i++) { + /* Switch: '/Switch3' incorporates: + * Merge: '/Merge' + * MultiPortSwitch: '/Multiport Switch' + */ + rtb_TmpSignalConversionAt1DLookupTable7Inport1[i] = rtB.MultiportSwitch[i]; + } + + /* End of SignalConversion generated from: '/In1' */ + /* End of Outputs for SubSystem: '/If Action Subsystem1' */ + } + + /* End of If: '/If1' */ + + /* Switch: '/Switch' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read4' + */ + /* : switch index_mode */ + if (rtDW.CCU_MODE_RR <= 0) { + rtDW.Index_mode_RR_auto = rtDW.Index_mode_RR_manual; + } + + /* MATLAB Function: '/param index for mode' incorporates: + * Switch: '/Switch' + */ + switch (rtDW.Index_mode_RR_auto) { + case 0U: + /* : case 0 */ + /* : Y = 1; */ + i = 1; + break; + + case 120U: + /* : case 120 */ + /* : Y = 1; */ + i = 1; + break; + + case 130U: + /* : case 130 */ + /* : Y = 2; */ + i = 2; + break; + + case 140U: + /* : case 140 */ + /* : Y = 2; */ + i = 2; + break; + + case 150U: + /* : case 150 */ + /* : Y = 1; */ + i = 1; + break; + + case 160U: + /* : case 160 */ + /* : Y = 3; */ + i = 3; + break; + + case 170U: + /* : case 170 */ + /* : Y = 1; */ + i = 1; + break; + + case 180U: + /* : case 180 */ + /* : Y = 3; */ + i = 3; + break; + + case 190U: + /* : case 190 */ + /* : Y = 1; */ + i = 1; + break; + + case 200U: + /* : case 200 */ + /* : Y = 2; */ + i = 2; + break; + + default: + /* : otherwise */ + /* : Y = 1; */ + i = 1; + break; + } + + /* End of MATLAB Function: '/param index for mode' */ + + /* MATLAB Function: '/RR valves * percent DRS' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read2' + * Merge: '/Merge' + */ + /* : index_start = (param_index - 1) * 3 + 1; */ + index_start_0 = (i - 1) * 3 + 1; + + /* : disp("index_start (rear):") */ + printf("%s\n", "index_start (rear):"); + fflush(stdout); + + /* : disp(index_start) */ + /* : if DRS_RRS == 0 */ + if (rtDW.DRS_SRR == 0) { + /* : side_percent = uint8(0); */ + rtb_DataTypeConversion1_lq = 0U; + } else { + /* : else */ + /* : side_percent = g_aucREAR_SIDE_DRS_PERCENT_VALVE(index_start + 3 - DRS_RRS); */ + i = (index_start_0 - rtDW.DRS_SRR) + 3; + if (i >= 0) { + rtb_DataTypeConversion1_nc = (uint8_t)i; + } else { + rtb_DataTypeConversion1_nc = 0U; + } + + rtb_DataTypeConversion1_lq = + g_aucREAR_SIDE_DRS_PERCENT_VALVE[rtb_DataTypeConversion1_nc - 1]; + } + + /* : if DRS_RRC == 0 */ + if (rtDW.DRS_CRR == 0) { + /* : center_percent = uint8(0); */ + rtb_DataTypeConversion1_nc = 0U; + } else { + /* : else */ + /* : center_percent = g_aucREAR_CENT_DRS_PERCENT_VALVE(index_start + 3 - DRS_RRC); */ + i = (index_start_0 - rtDW.DRS_CRR) + 3; + if (i >= 0) { + rtb_DataTypeConversion1_nc = (uint8_t)i; + } else { + rtb_DataTypeConversion1_nc = 0U; + } + + rtb_DataTypeConversion1_nc = + g_aucREAR_CENT_DRS_PERCENT_VALVE[rtb_DataTypeConversion1_nc - 1]; + } + + /* : disp("side_percent (rear):") */ + printf("%s\n", "side_percent (rear):"); + fflush(stdout); + + /* : disp(side_percent) */ + /* : disp("center_percent (rear):") */ + printf("%s\n", "center_percent (rear):"); + fflush(stdout); + + /* : disp(center_percent) */ + /* : y = valves; */ + /* : y(3) = uint8(double(valves(3)) * (double(center_percent) / 100)); */ + i = (int32_t)rt_roundd((double)rtb_DataTypeConversion1_nc / 100.0 * (double) + rtb_TmpSignalConversionAt1DLookupTable7Inport1[2]); + + /* : y(4) = uint8(double(valves(4)) * (double(side_percent) / 100)); */ + index_start_0 = (int32_t)rt_roundd((double)rtb_DataTypeConversion1_lq / 100.0 * + (double)rtb_TmpSignalConversionAt1DLookupTable7Inport1[3]); + if (i < 256) { + /* Assignment: '/ [3-4] rear' incorporates: + * DataStoreWrite: '/Data Store Write24' + */ + rtb_Gain1_o3[2] = (uint16_t)i; + } else { + /* Assignment: '/ [3-4] rear' incorporates: + * DataStoreWrite: '/Data Store Write24' + */ + rtb_Gain1_o3[2] = 255U; + } + + if (index_start_0 < 256) { + /* Assignment: '/ [3-4] rear' incorporates: + * DataStoreWrite: '/Data Store Write24' + */ + rtb_Gain1_o3[3] = (uint16_t)index_start_0; + } else { + /* Assignment: '/ [3-4] rear' incorporates: + * DataStoreWrite: '/Data Store Write24' + */ + rtb_Gain1_o3[3] = 255U; + } + + /* Assignment: '/ [6] rear' incorporates: + * DataStoreWrite: '/Data Store Write24' + * MATLAB Function: '/RR valves * percent DRS' + * Merge: '/Merge' + */ + rtb_Gain1_o3[5] = rtb_TmpSignalConversionAt1DLookupTable7Inport1[5]; + + /* Switch: '/Switch' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + rtDW.Index_mode_FL_auto = rtb_DataTypeConversion3_gz; + + /* DataStoreWrite: '/Data Store Write1' */ + rtDW.Index_mode_FR_auto = rtb_DataTypeConversion3_gf; + + /* Switch: '/Switch' incorporates: + * DataStoreWrite: '/Data Store Write1' + */ + rtDW.Index_mode_RL_auto = rtb_out_h0; + + /* Switch: '/Switch' incorporates: + * DataStoreWrite: '/Data Store Write2' + */ + rtDW.Index_mode_RR_auto = rtb_out_nj; + + /* MultiPortSwitch: '/Multiport Switch1' */ + switch (rtb_out_nc) { + case 0: + /* Switch: '/Switch' incorporates: + * Constant: '/Constant4' + */ + rtDW.Index_mode_FR_manual = 0U; + break; + + case 1: + /* Switch: '/Switch' incorporates: + * Constant: '/Constant5' + */ + rtDW.Index_mode_FR_manual = 80U; + break; + + case 2: + /* Switch: '/Switch' incorporates: + * Constant: '/Constant6' + */ + rtDW.Index_mode_FR_manual = 10U; + break; + + case 3: + /* Switch: '/Switch' incorporates: + * Constant: '/Constant7' + */ + rtDW.Index_mode_FR_manual = 100U; + break; + + case 4: + /* Switch: '/Switch' incorporates: + * Constant: '/Constant8' + */ + rtDW.Index_mode_FR_manual = 60U; + break; + + case 5: + /* Switch: '/Switch' incorporates: + * Constant: '/Constant9' + */ + rtDW.Index_mode_FR_manual = 70U; + break; + + case 6: + /* Switch: '/Switch' incorporates: + * Constant: '/Constant10' + */ + rtDW.Index_mode_FR_manual = 20U; + break; + + default: + /* Switch: '/Switch' incorporates: + * Constant: '/Constant11' + */ + rtDW.Index_mode_FR_manual = 90U; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch1' */ + + /* DataStoreWrite: '/Data Store Write31' */ + rtDW.enable_rear_sync = 0U; + + /* Saturate: '/Saturation' incorporates: + * DataStoreRead: '/Data Store Read' + */ + if (rtDW.AMB > 1000) { + rtb_FLU_tg_correct_aa = 1000; + } else if (rtDW.AMB < -1000) { + rtb_FLU_tg_correct_aa = -1000; + } else { + rtb_FLU_tg_correct_aa = rtDW.AMB; + } + + /* End of Saturate: '/Saturation' */ + + /* MATLAB Function: '/Convert_g_assAMB_LV_UP' */ + /* : c_g_assAMB_LV_UP = [-1000, g_assAMB_LV_UP(5), g_assAMB_LV_UP(4), g_assAMB_LV_UP(3), g_assAMB_LV_UP(2), g_assAMB_LV_UP(1)]; */ + tmp_2[0] = -1000; + tmp_2[1] = g_assAMB_LV_UP[4]; + tmp_2[2] = g_assAMB_LV_UP[3]; + tmp_2[3] = g_assAMB_LV_UP[2]; + tmp_2[4] = g_assAMB_LV_UP[1]; + tmp_2[5] = g_assAMB_LV_UP[0]; + + /* SwitchCase: '/Switch Case' incorporates: + * Lookup_n-D: '/1-D Lookup Table' + * Saturate: '/Saturation' + */ + switch ((int8_t)rtConstP.pooled53[plook_u32s16_bincka(rtb_FLU_tg_correct_aa, + tmp_2, 5U)]) { + case 0: + /* Outputs for IfAction SubSystem: '/Switch Case Action Subsystem' incorporates: + * ActionPort: '/Action Port' + */ + /* Merge: '/Merge' incorporates: + * Constant: '/Constant' + * RelationalOperator: '/Relational Operator' + * Switch: '/Switch' + */ + rtB.Merge_b = (uint8_t)(rtb_FLU_tg_correct_aa <= g_assAMB_LV_UP[0]); + + /* End of Outputs for SubSystem: '/Switch Case Action Subsystem' */ + break; + + case 1: + /* Outputs for IfAction SubSystem: '/Switch Case Action Subsystem1' incorporates: + * ActionPort: '/Action Port' + */ + /* Switch: '/Switch' incorporates: + * MATLAB Function: '/Convert_g_assAMB_LV_UP_2' + * RelationalOperator: '/Relational Operator' + */ + /* : c_g_assAMB_LV_DN_1 = g_assAMB_LV_DN(1); */ + /* : c_g_assAMB_LV_UP_2 = g_assAMB_LV_UP(2); */ + if (rtb_FLU_tg_correct_aa > g_assAMB_LV_UP[1]) { + /* Merge: '/Merge' incorporates: + * MATLAB Function: '/Convert_g_assAMB_LV_DN_1' + * RelationalOperator: '/Relational Operator1' + */ + rtB.Merge_b = (uint8_t)(rtb_FLU_tg_correct_aa <= g_assAMB_LV_DN[0]); + } else { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant_Lv2' + */ + rtB.Merge_b = 2U; + } + + /* End of Switch: '/Switch' */ + /* End of Outputs for SubSystem: '/Switch Case Action Subsystem1' */ + break; + + case 2: + /* Outputs for IfAction SubSystem: '/Switch Case Action Subsystem2' incorporates: + * ActionPort: '/Action Port' + */ + /* Switch: '/Switch2' incorporates: + * MATLAB Function: '/Convert_g_assAMB_LV_UP_3' + * RelationalOperator: '/Relational Operator' + */ + /* : c_g_assAMB_LV_DN_2 = g_assAMB_LV_DN(2); */ + /* : c_g_assAMB_LV_UP_3 = g_assAMB_LV_UP(3); */ + if (rtb_FLU_tg_correct_aa > g_assAMB_LV_UP[2]) { + /* Switch: '/Switch3' incorporates: + * MATLAB Function: '/Convert_g_assAMB_LV_DN_2' + * RelationalOperator: '/Relational Operator1' + */ + if (rtb_FLU_tg_correct_aa > g_assAMB_LV_DN[1]) { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant_Lv1' + */ + rtB.Merge_b = 1U; + } else { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant_Lv2' + */ + rtB.Merge_b = 2U; + } + + /* End of Switch: '/Switch3' */ + } else { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant_Lv3' + */ + rtB.Merge_b = 3U; + } + + /* End of Switch: '/Switch2' */ + /* End of Outputs for SubSystem: '/Switch Case Action Subsystem2' */ + break; + + case 3: + /* Outputs for IfAction SubSystem: '/Switch Case Action Subsystem3' incorporates: + * ActionPort: '/Action Port' + */ + /* Switch: '/Switch2' incorporates: + * MATLAB Function: '/Convert_g_assAMB_LV_UP_4' + * RelationalOperator: '/Relational Operator' + */ + /* : c_g_assAMB_LV_DN_3 = g_assAMB_LV_DN(3); */ + /* : c_g_assAMB_LV_UP_4 = g_assAMB_LV_UP(4); */ + if (rtb_FLU_tg_correct_aa > g_assAMB_LV_UP[3]) { + /* Switch: '/Switch3' incorporates: + * MATLAB Function: '/Convert_g_assAMB_LV_DN_3' + * RelationalOperator: '/Relational Operator1' + */ + if (rtb_FLU_tg_correct_aa > g_assAMB_LV_DN[2]) { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant_Lv2' + */ + rtB.Merge_b = 2U; + } else { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant_Lv3' + */ + rtB.Merge_b = 3U; + } + + /* End of Switch: '/Switch3' */ + } else { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant_Lv4' + */ + rtB.Merge_b = 4U; + } + + /* End of Switch: '/Switch2' */ + /* End of Outputs for SubSystem: '/Switch Case Action Subsystem3' */ + break; + + case 4: + /* Outputs for IfAction SubSystem: '/Switch Case Action Subsystem4' incorporates: + * ActionPort: '/Action Port' + */ + /* Switch: '/Switch2' incorporates: + * MATLAB Function: '/Convert_g_assAMB_LV_UP_5' + * RelationalOperator: '/Relational Operator' + */ + /* : c_g_assAMB_LV_DN_4 = g_assAMB_LV_DN(4); */ + /* : c_g_assAMB_LV_UP_5 = g_assAMB_LV_UP(5); */ + if (rtb_FLU_tg_correct_aa > g_assAMB_LV_UP[4]) { + /* Switch: '/Switch3' incorporates: + * MATLAB Function: '/Convert_g_assAMB_LV_DN_4' + * RelationalOperator: '/Relational Operator1' + */ + if (rtb_FLU_tg_correct_aa > g_assAMB_LV_DN[3]) { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant_Lv3' + */ + rtB.Merge_b = 3U; + } else { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant_Lv4' + */ + rtB.Merge_b = 4U; + } + + /* End of Switch: '/Switch3' */ + } else { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant_Lv5' + */ + rtB.Merge_b = 5U; + } + + /* End of Switch: '/Switch2' */ + /* End of Outputs for SubSystem: '/Switch Case Action Subsystem4' */ + break; + + case 5: + /* Outputs for IfAction SubSystem: '/Switch Case Action Subsystem5' incorporates: + * ActionPort: '/Action Port' + */ + /* Switch: '/Switch1' incorporates: + * MATLAB Function: '/Convert_g_assAMB_LV_DN_5' + * RelationalOperator: '/Relational Operator' + */ + /* : c_g_assAMB_LV_DN_5 = g_assAMB_LV_DN(5); */ + if (rtb_FLU_tg_correct_aa > g_assAMB_LV_DN[4]) { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant_Lv4' + */ + rtB.Merge_b = 4U; + } else { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant_Lv5' + */ + rtB.Merge_b = 5U; + } + + /* End of Switch: '/Switch1' */ + /* End of Outputs for SubSystem: '/Switch Case Action Subsystem5' */ + break; + } + + /* End of SwitchCase: '/Switch Case' */ + + /* Saturate: '/Saturation' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + if (rtDW.CCU_SET_FL > 290) { + i = 290; + } else if (rtDW.CCU_SET_FL < 170) { + i = 170; + } else { + i = rtDW.CCU_SET_FL; + } + + /* Gain: '/Gain' incorporates: + * Saturate: '/Saturation' + */ + i *= 13107; + rtb_DataTypeConversion1_nc = (uint8_t)((((uint32_t)i & 65536U) != 0U) + (i >> + 17)); + + /* MATLAB Function: '/Modes for levels' */ + /* : get_modes_for_levels = [g_aucMODE_BY_SET_F_LV0; */ + /* : g_aucMODE_BY_SET_F_LV1; */ + /* : g_aucMODE_BY_SET_F_LV2; */ + /* : g_aucMODE_BY_SET_F_LV3; */ + /* : g_aucMODE_BY_SET_F_LV4; */ + /* : g_aucMODE_BY_SET_F_LV5; */ + /* : ]; */ + for (i = 0; i < 13; i++) { + rtb_get_modes_for_levels[6 * i] = g_aucMODE_BY_SET_F_LV0[i]; + rtb_get_modes_for_levels[6 * i + 1] = g_aucMODE_BY_SET_F_LV1[i]; + rtb_get_modes_for_levels[6 * i + 2] = g_aucMODE_BY_SET_F_LV2[i]; + rtb_get_modes_for_levels[6 * i + 3] = g_aucMODE_BY_SET_F_LV3[i]; + rtb_get_modes_for_levels[6 * i + 4] = g_aucMODE_BY_SET_F_LV4[i]; + rtb_get_modes_for_levels[6 * i + 5] = g_aucMODE_BY_SET_F_LV5[i]; + } + + /* End of MATLAB Function: '/Modes for levels' */ + + /* Lookup_n-D: '/ Left' incorporates: + * Gain: '/Gain' + * Merge: '/Merge' + */ + rtb_DataTypeConversion3_gz = look2_iu8bu8s16lu64n32_binlcse(rtB.Merge_b, + rtb_DataTypeConversion1_nc, rtConstP.pooled129, rtConstP.pooled65, + rtb_get_modes_for_levels, rtConstP.pooled48, 6U); + + /* MATLAB Function: '/ left' */ + left(rtb_DataTypeConversion3_gz, rtb_out_iy); + + /* Saturate: '/Saturation1' incorporates: + * DataStoreRead: '/Data Store Read2' + */ + if (rtDW.CCU_SET_FR > 290) { + i = 290; + } else if (rtDW.CCU_SET_FR < 170) { + i = 170; + } else { + i = rtDW.CCU_SET_FR; + } + + /* Gain: '/Gain2' incorporates: + * Saturate: '/Saturation1' + */ + i *= 13107; + rtb_Saturation4_f = (uint8_t)((((uint32_t)i & 65536U) != 0U) + (i >> 17)); + + /* SwitchCase: '/Switch for Left ' incorporates: + * DataStoreRead: '/Data Store Read' + */ + switch (rtb_DataTypeConversion3_gz) { + case 10: + break; + + case 20: + for (i = 0; i < 9; i++) { + /* Outputs for IfAction SubSystem: '/Bilevel' incorporates: + * ActionPort: '/Action Port' + */ + rtb_out_il[i] = rtb_out_iy[i]; + + /* End of Outputs for SubSystem: '/Bilevel' */ + } + + /* Outputs for IfAction SubSystem: '/Bilevel' incorporates: + * ActionPort: '/Action Port' + */ + Bilevel(rtDW.AMB, rtB.Merge_b, rtb_out_il, rtb_DataTypeConversion1_nc, + rtb_Saturation4_f); + + /* End of Outputs for SubSystem: '/Bilevel' */ + break; + + case 30: + for (i = 0; i < 9; i++) { + /* Outputs for IfAction SubSystem: '/Bilevel2' incorporates: + * ActionPort: '/Action Port' + */ + rtb_out_il[i] = rtb_out_iy[i]; + + /* End of Outputs for SubSystem: '/Bilevel2' */ + } + + /* Outputs for IfAction SubSystem: '/Bilevel2' incorporates: + * ActionPort: '/Action Port' + */ + Bilevel2(rtDW.AMB, rtB.Merge_b, rtb_out_il, rtb_DataTypeConversion1_nc, + rtb_Saturation4_f); + + /* End of Outputs for SubSystem: '/Bilevel2' */ + break; + + case 40: + for (i = 0; i < 9; i++) { + /* Outputs for IfAction SubSystem: '/Afoot' incorporates: + * ActionPort: '/Action Port' + */ + rtb_out_il[i] = rtb_out_iy[i]; + + /* End of Outputs for SubSystem: '/Afoot' */ + } + + /* Outputs for IfAction SubSystem: '/Afoot' incorporates: + * ActionPort: '/Action Port' + */ + Afoot(rtDW.AMB, rtB.Merge_b, rtb_out_il, rtb_DataTypeConversion1_nc, + rtb_Saturation4_f); + + /* End of Outputs for SubSystem: '/Afoot' */ + break; + + case 50: + for (i = 0; i < 9; i++) { + /* Outputs for IfAction SubSystem: '/Afoot_Summer' incorporates: + * ActionPort: '/Action Port' + */ + rtb_out_il[i] = rtb_out_iy[i]; + + /* End of Outputs for SubSystem: '/Afoot_Summer' */ + } + + /* Outputs for IfAction SubSystem: '/Afoot_Summer' incorporates: + * ActionPort: '/Action Port' + */ + Afoot_Summer(rtDW.AMB, rtB.Merge_b, rtb_out_il, rtb_DataTypeConversion1_nc, + rtb_Saturation4_f); + + /* End of Outputs for SubSystem: '/Afoot_Summer' */ + break; + } + + /* End of SwitchCase: '/Switch for Left ' */ + + /* Lookup_n-D: '/ Right' incorporates: + * Gain: '/Gain2' + * Merge: '/Merge' + */ + rtb_DataTypeConversion3_gz = look2_iu8bu8s16lu64n32_binlcse(rtB.Merge_b, + rtb_Saturation4_f, rtConstP.pooled129, rtConstP.pooled65, + rtb_get_modes_for_levels, rtConstP.pooled48, 6U); + + /* MATLAB Function: '/ right' */ + left(rtb_DataTypeConversion3_gz, rtb_out_il); + + /* SwitchCase: '/Switch for Left ' incorporates: + * DataStoreRead: '/Data Store Read' + */ + switch (rtb_DataTypeConversion3_gz) { + case 10: + break; + + case 20: + for (i = 0; i < 9; i++) { + /* Outputs for IfAction SubSystem: '/Bilevel' incorporates: + * ActionPort: '/Action Port' + */ + rtb_out_iy[i] = rtb_out_il[i]; + + /* End of Outputs for SubSystem: '/Bilevel' */ + } + + /* Outputs for IfAction SubSystem: '/Bilevel' incorporates: + * ActionPort: '/Action Port' + */ + Bilevel(rtDW.AMB, rtB.Merge_b, rtb_out_iy, rtb_DataTypeConversion1_nc, + rtb_Saturation4_f); + + /* End of Outputs for SubSystem: '/Bilevel' */ + break; + + case 30: + for (i = 0; i < 9; i++) { + /* Outputs for IfAction SubSystem: '/Bilevel2' incorporates: + * ActionPort: '/Action Port' + */ + rtb_out_iy[i] = rtb_out_il[i]; + + /* End of Outputs for SubSystem: '/Bilevel2' */ + } + + /* Outputs for IfAction SubSystem: '/Bilevel2' incorporates: + * ActionPort: '/Action Port' + */ + Bilevel2(rtDW.AMB, rtB.Merge_b, rtb_out_iy, rtb_DataTypeConversion1_nc, + rtb_Saturation4_f); + + /* End of Outputs for SubSystem: '/Bilevel2' */ + break; + + case 40: + for (i = 0; i < 9; i++) { + /* Outputs for IfAction SubSystem: '/Afoot' incorporates: + * ActionPort: '/Action Port' + */ + rtb_out_iy[i] = rtb_out_il[i]; + + /* End of Outputs for SubSystem: '/Afoot' */ + } + + /* Outputs for IfAction SubSystem: '/Afoot' incorporates: + * ActionPort: '/Action Port' + */ + Afoot(rtDW.AMB, rtB.Merge_b, rtb_out_iy, rtb_DataTypeConversion1_nc, + rtb_Saturation4_f); + + /* End of Outputs for SubSystem: '/Afoot' */ + break; + + case 50: + for (i = 0; i < 9; i++) { + /* Outputs for IfAction SubSystem: '/Afoot_Summer' incorporates: + * ActionPort: '/Action Port' + */ + rtb_out_iy[i] = rtb_out_il[i]; + + /* End of Outputs for SubSystem: '/Afoot_Summer' */ + } + + /* Outputs for IfAction SubSystem: '/Afoot_Summer' incorporates: + * ActionPort: '/Action Port' + */ + Afoot_Summer(rtDW.AMB, rtB.Merge_b, rtb_out_iy, rtb_DataTypeConversion1_nc, + rtb_Saturation4_f); + + /* End of Outputs for SubSystem: '/Afoot_Summer' */ + break; + } + + /* End of SwitchCase: '/Switch for Left ' */ + + /* DataStoreWrite: '/Data Store Write' */ + rtDW.LEVEL = rtB.Merge_b; + + /* MATLAB Function: '/Log Ambient Lv' */ + /* : if (isempty(current_Ambient_Lv)) */ + if (!rtDW.current_Ambient_Lv_not_empty) { + /* : current_Ambient_Lv = Ambient_Lv; */ + rtDW.current_Ambient_Lv = rtB.Merge_b; + rtDW.current_Ambient_Lv_not_empty = true; + + /* : fprintf("13.1.3.1 Ambient level: in_Amb_Fb = %d; Set Ambient lvl (init) = %u \n", in_Amb_Fb, Ambient_Lv); */ + printf("13.1.3.1 Ambient level: in_Amb_Fb = %d; Set Ambient lvl (init) = %u \n", + rtb_FLU_tg_correct_aa, rtB.Merge_b); + fflush(stdout); + + /* : else */ + /* : if (current_Ambient_Lv ~= Ambient_Lv) */ + } else if (rtDW.current_Ambient_Lv != rtB.Merge_b) { + /* : current_Ambient_Lv = Ambient_Lv; */ + rtDW.current_Ambient_Lv = rtB.Merge_b; + + /* : fprintf("13.1.3.1 Ambient level: in_Amb_Fb = %d; Set Ambient lvl = %u \n", in_Amb_Fb, Ambient_Lv); */ + printf("13.1.3.1 Ambient level: in_Amb_Fb = %d; Set Ambient lvl = %u \n", + rtb_FLU_tg_correct_aa, rtB.Merge_b); + fflush(stdout); + } + + /* End of MATLAB Function: '/Log Ambient Lv' */ + + /* Chart: '/Spd_OSA_Trigger' */ + if (rtDW.is_active_c834_HVAC_model == 0U) { + rtDW.is_active_c834_HVAC_model = 1U; + rtDW.is_c834_HVAC_model = IN_OSA_OFF; + + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + /* : is_OSA_Active = 0; */ + rtDW.dbgCAN_Logic_Rec_model.Logic_Rec_Partial_Spd_Sts = 0U; + + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + */ + rtb_DataTypeConversion3_gz = 100U; + } else if (rtDW.is_c834_HVAC_model == IN_OSA_OFF) { + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + rtDW.dbgCAN_Logic_Rec_model.Logic_Rec_Partial_Spd_Sts = 0U; + + /* : sf_internal_predicateOutput = VehicleSpeed > 20 && Full_Rec_Active == 0; */ + if ((rtDW.VehicleSpeed > 20) && (rtDW.Full_Rec == 0)) { + rtDW.is_c834_HVAC_model = IN_OSA_ON; + + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + /* : is_OSA_Active = 1; */ + rtDW.dbgCAN_Logic_Rec_model.Logic_Rec_Partial_Spd_Sts = 1U; + + /* Switch: '/Switch' incorporates: + * DataStoreRead: '/Data Store Read6' + * Lookup_n-D: '/1-D Lookup Table2' + */ + rtb_DataTypeConversion3_gz = look1_iu16lu64n48tu8_binlcse + (rtDW.VehicleSpeed, &g_ausVALVE_VEH_SPD[0], &g_aucPREC_VEH_SPD_OSA[0], + 12U); + } else { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + */ + rtb_DataTypeConversion3_gz = 100U; + } + } else { + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + /* case IN_OSA_ON: */ + rtDW.dbgCAN_Logic_Rec_model.Logic_Rec_Partial_Spd_Sts = 1U; + + /* : sf_internal_predicateOutput = VehicleSpeed == 0 || Full_Rec_Active == 1; */ + if ((rtDW.VehicleSpeed == 0) || (rtDW.Full_Rec == 1)) { + rtDW.is_c834_HVAC_model = IN_OSA_OFF; + + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + /* : is_OSA_Active = 0; */ + rtDW.dbgCAN_Logic_Rec_model.Logic_Rec_Partial_Spd_Sts = 0U; + + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + */ + rtb_DataTypeConversion3_gz = 100U; + } else { + /* Switch: '/Switch' incorporates: + * DataStoreRead: '/Data Store Read6' + * Lookup_n-D: '/1-D Lookup Table2' + */ + rtb_DataTypeConversion3_gz = look1_iu16lu64n48tu8_binlcse + (rtDW.VehicleSpeed, &g_ausVALVE_VEH_SPD[0], &g_aucPREC_VEH_SPD_OSA[0], + 12U); + } + } + + /* End of Chart: '/Spd_OSA_Trigger' */ + + /* Chart: '/Partial REC' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read3' + * DataStoreRead: '/Data Store Read4' + * Gain: '/Gain' + * Lookup_n-D: '/1-D Lookup Table' + * Lookup_n-D: '/1-D Lookup Table1' + * MATLAB Function: '/MATLAB Function' + */ + if (rtDW.is_active_c776_HVAC_model == 0U) { + rtDW.is_active_c776_HVAC_model = 1U; + rtDW.is_c776_HVAC_model = IN_PARTIAL_REC_OFF; + + /* : Comp_Active = 0; */ + rtb_DataTypeConversion1_nc = 0U; + } else if (rtDW.is_c776_HVAC_model == IN_PARTIAL_REC_OFF) { + rtb_DataTypeConversion1_nc = 0U; + + /* : sf_internal_predicateOutput = Amb_temp >= g_ssPREC_REC_ON_AMB && Full_Rec_Active == 0; */ + if ((rtDW.AMB >= g_ssPREC_REC_ON_AMB) && (rtDW.Full_Rec == 0)) { + rtDW.is_c776_HVAC_model = IN_PARTIAL_REC_ON; + + /* : sf_internal_predicateOutput = Evap_F_Fb >= g_aucPREC_EVA_DIFF(1) && Evap_R_Fb >= g_aucPREC_EVA_DIFF(3) &&E_comp_speed >= g_ausPREC_ENTRY_RPM(3); */ + if ((rtDW.Eva_F >= g_aucPREC_EVA_DIFF[0]) && ((rtDW.Eva_R >= + g_aucPREC_EVA_DIFF[2]) && (El_window_heating >= g_ausPREC_ENTRY_RPM + [2]))) { + rtDW.is_PARTIAL_REC_ON = IN_COND_3; + + /* : Comp_Active = 3; */ + rtb_DataTypeConversion1_nc = 3U; + + /* : sf_internal_predicateOutput = E_comp_speed >= g_ausPREC_ENTRY_RPM(2); */ + } else if (El_window_heating >= g_ausPREC_ENTRY_RPM[1]) { + rtDW.is_PARTIAL_REC_ON = IN_COND_2; + + /* : Comp_Active = 2; */ + rtb_DataTypeConversion1_nc = 2U; + rtDW.is_COND_2 = IN_TRACKING; + } else { + rtDW.is_PARTIAL_REC_ON = IN_COND_1; + + /* : Comp_Active = 1; */ + rtb_DataTypeConversion1_nc = 1U; + } + } + + /* case IN_PARTIAL_REC_ON: */ + /* : sf_internal_predicateOutput = Amb_temp < g_ssPREC_REC_ON_AMB || Full_Rec_Active == 1; */ + } else if ((rtDW.AMB < g_ssPREC_REC_ON_AMB) || (rtDW.Full_Rec == 1)) { + rtDW.is_COND_2 = IN_NO_ACTIVE_CHILD_c; + rtDW.is_PARTIAL_REC_ON = IN_NO_ACTIVE_CHILD_c; + rtDW.is_c776_HVAC_model = IN_PARTIAL_REC_OFF; + + /* : Comp_Active = 0; */ + rtb_DataTypeConversion1_nc = 0U; + } else { + switch (rtDW.is_PARTIAL_REC_ON) { + case IN_COND_1: + rtb_DataTypeConversion1_nc = 1U; + + /* Gain: '/Gain' incorporates: + * Gain: '/Gain1' + * MATLAB Function: '/MATLAB Function' + */ + /* : req_OSA =PREC_OSA_SUMMER_1; */ + rtb_out_nc = (uint16_t)(5U * El_window_heating); + rtB.req_OSA = look1_iu16lu64n48tu8_binlcse(rtb_out_nc, + &g_ausPREC_COMP_SPD_1[0], &g_aucPREC_OSA_SUMMER_1[0], 2U); + + /* : req_REC =PREC_REC_SUMMER_1; */ + rtB.req_REC = look1_iu16lu64n48tu8_binlcse(rtb_out_nc, + &g_ausPREC_COMP_SPD_1[0], &g_aucPREC_REC_SUMMER_1[0], 2U); + break; + + case IN_COND_2: + rtb_DataTypeConversion1_nc = 2U; + + /* : sf_internal_predicateOutput = E_comp_speed 32767) { + i = 32767; + } else if (i < -32768) { + i = -32768; + } + + rtb_Add_be = find_index((int16_t)i); + + /* : X=g_assPREC_EVA_DIFF_FB_TG_F(x_idx); */ + if (rtDW.is_COND_2 == IN_HOLDING) { + /* : sf_internal_predicateOutput = X <= 0; */ + rtb_FLU_tg_correct_aa = g_assPREC_EVA_DIFF_FB_TG_F[(int32_t)rtb_Add_be + - 1]; + if (rtb_FLU_tg_correct_aa <= 0) { + rtDW.is_COND_2 = IN_TRACKING; + + /* : sf_internal_predicateOutput = X > X_prev; */ + } else if (rtb_FLU_tg_correct_aa > rtDW.X_prev) { + rtDW.is_COND_2 = IN_TRACKING; + } else { + /* : X_prev = X; */ + rtDW.X_prev = rtb_FLU_tg_correct_aa; + } + } else { + /* case IN_TRACKING: */ + /* : sf_internal_predicateOutput = X < X_prev && X > 0; */ + i = g_assPREC_EVA_DIFF_FB_TG_F[(int32_t)rtb_Add_be - 1]; + if ((i < rtDW.X_prev) && (i > 0)) { + rtDW.is_COND_2 = IN_HOLDING; + } else { + /* : req_OSA = g_aucPREC_OSA_SUMMER_2(x_idx); */ + rtB.req_OSA = g_aucPREC_OSA_SUMMER_2[(int32_t)rtb_Add_be - 1]; + + /* : req_REC = g_aucPREC_REC_SUMMER_2(x_idx); */ + rtB.req_REC = g_aucPREC_REC_SUMMER_2[(int32_t)rtb_Add_be - 1]; + + /* : X_prev = X; */ + rtDW.X_prev = g_assPREC_EVA_DIFF_FB_TG_F[(int32_t)rtb_Add_be - 1]; + } + } + } + break; + + default: + /* case IN_COND_3: */ + rtb_DataTypeConversion1_nc = 3U; + + /* : sf_internal_predicateOutput = Evap_F_Fb < g_aucPREC_EVA_DIFF(2) && Evap_R_Fb < g_aucPREC_EVA_DIFF(4)&&E_comp_speed < g_ausPREC_EXIT_RPM(3); */ + if ((rtDW.Eva_F < g_aucPREC_EVA_DIFF[1]) && ((rtDW.Eva_R < + g_aucPREC_EVA_DIFF[3]) && (El_window_heating < g_ausPREC_EXIT_RPM[2]))) + { + rtDW.is_PARTIAL_REC_ON = IN_COND_2; + + /* : Comp_Active = 2; */ + rtb_DataTypeConversion1_nc = 2U; + rtDW.is_COND_2 = IN_TRACKING; + } else { + /* : req_OSA = g_ucPREC_OSA_SUMMER_3; */ + rtB.req_OSA = g_ucPREC_OSA_SUMMER_3; + + /* : req_REC = g_ucPREC_REC_SUMMER_3; */ + rtB.req_REC = g_ucPREC_REC_SUMMER_3; + } + break; + } + } + + /* End of Chart: '/Partial REC' */ + + /* Logic: '/OR1' incorporates: + * Constant: '/Constant6' + * Constant: '/Constant8' + * DataStoreRead: '/Data Store Read10' + * DataStoreRead: '/Data Store Read74' + * RelationalOperator: '/Relational Operator1' + * RelationalOperator: '/Relational Operator3' + */ + rtb_Compare_i5 = ((rtDW.condition_ac_max == 1.0) || (rtDW.CCU_RECIRC == 2)); + + /* Switch: '/Switch3' incorporates: + * Constant: '/Constant4' + * DataStoreRead: '/Data Store Read7' + * DataStoreWrite: '/Data Store Write' + * Switch: '/Switch1' + * Switch: '/Switch5' + */ + if (rtDW.Full_Rec > 0) { + rtb_Saturation4_f = 0U; + } else if (rtb_Compare_i5) { + /* Switch: '/Switch1' incorporates: + * Constant: '/Constant1' + */ + if (rtb_DataTypeConversion1_nc > 0) { + rtb_Saturation4_f = rtB.req_OSA; + } else { + rtb_Saturation4_f = 100U; + } + + /* Lookup_n-D: '/1-D Lookup Table3' incorporates: + * DataStoreRead: '/Data Store Read3' + * Switch: '/Switch5' + */ + rtb_DataTypeConversion3_gf = look1_iu8lu64n56_binlcse(rtDW.AirQS_COLvl, + rtConstP.pooled109, &g_aucAQS_OSA_LV_CO[0], 6U); + + /* Lookup_n-D: '/1-D Lookup Table4' incorporates: + * DataStoreRead: '/Data Store Read4' + * Switch: '/Switch5' + */ + rtb_DataTypeConversion1_lq = look1_iu8lu64n56_binlcse(rtDW.AirQS_NOxLvl, + rtConstP.pooled109, &g_aucAQS_OSA_LV_NOX[0], 6U); + + /* MinMax: '/MinMax1' incorporates: + * Switch: '/Switch5' + */ + if (rtb_DataTypeConversion3_gf >= rtb_DataTypeConversion1_lq) { + rtb_DataTypeConversion1_lq = rtb_DataTypeConversion3_gf; + } + + /* Lookup_n-D: '/1-D Lookup Table5' incorporates: + * DataStoreRead: '/Data Store Read5' + * Switch: '/Switch5' + */ + rtb_DataTypeConversion3_gf = look1_iu8lu64n56_binlcse(rtDW.AirQS_NH3Lvl, + rtConstP.pooled109, &g_aucAQS_OSA_LV_NH3[0], 6U); + + /* MinMax: '/MinMax1' incorporates: + * Switch: '/Switch5' + */ + if (rtb_DataTypeConversion1_lq >= rtb_DataTypeConversion3_gf) { + rtb_DataTypeConversion3_gf = rtb_DataTypeConversion1_lq; + } + + /* MinMax: '/MinMax' incorporates: + * Switch: '/Switch1' + */ + if (rtb_DataTypeConversion3_gz <= rtb_Saturation4_f) { + rtb_Saturation4_f = rtb_DataTypeConversion3_gz; + } + + /* MinMax: '/MinMax1' incorporates: + * Switch: '/Switch5' + */ + if (rtb_DataTypeConversion3_gf <= rtb_Saturation4_f) { + /* DataStoreWrite: '/Data Store Write' */ + rtb_Saturation4_f = rtb_DataTypeConversion3_gf; + } + + /* End of MinMax: '/MinMax1' */ + } else { + if (rtb_DataTypeConversion1_nc > 0) { + /* Switch: '/Switch1' */ + rtb_Saturation4_f = rtB.req_OSA; + } else { + /* Switch: '/Switch1' incorporates: + * Constant: '/Constant1' + */ + rtb_Saturation4_f = 100U; + } + + /* MinMax: '/MinMax' incorporates: + * Switch: '/Switch1' + */ + if (rtb_DataTypeConversion3_gz <= rtb_Saturation4_f) { + /* DataStoreWrite: '/Data Store Write' incorporates: + * Switch: '/Switch5' + */ + rtb_Saturation4_f = rtb_DataTypeConversion3_gz; + } + } + + /* End of Switch: '/Switch3' */ + + /* Switch: '/Switch4' incorporates: + * Constant: '/Constant5' + * Constant: '/Constant7' + * DataStoreRead: '/Data Store Read8' + * DataStoreRead: '/Data Store Read9' + * DataStoreWrite: '/Data Store Write1' + * Logic: '/OR' + * RelationalOperator: '/Relational Operator2' + * Switch: '/Switch2' + * Switch: '/Switch6' + */ + if ((rtDW.Full_Rec != 0) || (rtDW.condition_ac_max == 2.0)) { + rtb_DataTypeConversion3_gz = 100U; + } else if (rtb_Compare_i5) { + /* Switch: '/Switch2' incorporates: + * Constant: '/Constant2' + */ + if (rtb_DataTypeConversion1_nc > 0) { + rtb_DataTypeConversion3_gz = rtB.req_REC; + } else { + rtb_DataTypeConversion3_gz = 0U; + } + + /* Lookup_n-D: '/1-D Lookup Table' incorporates: + * DataStoreRead: '/Data Store Read' + * Switch: '/Switch6' + */ + rtb_DataTypeConversion3_gf = look1_iu8lu64n56_binlcse(rtDW.AirQS_COLvl, + rtConstP.pooled110, &g_aucAQS_REC_LV_CO[0], 7U); + + /* Lookup_n-D: '/1-D Lookup Table1' incorporates: + * DataStoreRead: '/Data Store Read1' + * Switch: '/Switch6' + */ + rtb_DataTypeConversion1_lq = look1_iu8lu64n56_binlcse(rtDW.AirQS_NOxLvl, + rtConstP.pooled110, &g_aucAQS_REC_LV_NOX[0], 7U); + + /* MinMax: '/MinMax' incorporates: + * Switch: '/Switch6' + */ + if (rtb_DataTypeConversion3_gf >= rtb_DataTypeConversion1_lq) { + rtb_DataTypeConversion1_lq = rtb_DataTypeConversion3_gf; + } + + /* Lookup_n-D: '/1-D Lookup Table2' incorporates: + * DataStoreRead: '/Data Store Read2' + * Switch: '/Switch6' + */ + rtb_DataTypeConversion3_gf = look1_iu8lu64n56_binlcse(rtDW.AirQS_NH3Lvl, + rtConstP.pooled110, &g_aucAQS_REC_LV_NH3[0], 7U); + + /* MinMax: '/MinMax' incorporates: + * Switch: '/Switch6' + */ + if (rtb_DataTypeConversion1_lq >= rtb_DataTypeConversion3_gf) { + rtb_DataTypeConversion3_gf = rtb_DataTypeConversion1_lq; + } + + /* MinMax: '/MinMax2' incorporates: + * Switch: '/Switch2' + * Switch: '/Switch6' + */ + if (rtb_DataTypeConversion3_gf <= rtb_DataTypeConversion3_gz) { + /* DataStoreWrite: '/Data Store Write1' */ + rtb_DataTypeConversion3_gz = rtb_DataTypeConversion3_gf; + } + + /* End of MinMax: '/MinMax2' */ + } else if (rtb_DataTypeConversion1_nc > 0) { + /* Switch: '/Switch2' incorporates: + * DataStoreWrite: '/Data Store Write1' + * Switch: '/Switch6' + */ + rtb_DataTypeConversion3_gz = rtB.req_REC; + } else { + /* DataStoreWrite: '/Data Store Write1' incorporates: + * Constant: '/Constant2' + * Switch: '/Switch2' + * Switch: '/Switch6' + */ + rtb_DataTypeConversion3_gz = 0U; + } + + /* End of Switch: '/Switch4' */ + + /* DataTypeConversion: '/Data Type Conversion2' incorporates: + * Constant: '/Constant7' + * Constant: '/Constant8' + * DataStoreRead: '/Data Store Read10' + * DataStoreRead: '/Data Store Read9' + * DataStoreWrite: '/Data Store Write33' + * Logic: '/OR' + * RelationalOperator: '/Relational Operator2' + * RelationalOperator: '/Relational Operator3' + */ + rtDW.Air_status = (uint8_t)((rtDW.condition_ac_max == 1.0) || (rtDW.CCU_RECIRC + == 2)); + + /* Lookup_n-D: '/1-D Lookup Table' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write' + */ + rtDW.Dtg_individual_foot_FL = look1_iu8lu64n48ts16Ds32_binlcs + (rtDW.CCU_SET_FOOT_FL, rtConstP.pooled130, &g_assFOOT_STEP_DUCT_TGT[0], 6U); + + /* SwitchCase: '/Switch Case' incorporates: + * DataStoreRead: '/Data Store Read' + */ + switch (rtDW.LEVEL) { + case 1: + /* Outputs for IfAction SubSystem: '/If Action Subsystem' incorporates: + * ActionPort: '/Action Port' + */ + /* SwitchCase: '/Switch Case' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read' + */ + switch (rtDW.CCU_SET_FOOT_FL) { + case 0: + case 1: + case 2: + /* Outputs for IfAction SubSystem: '/If Action Subsystem' incorporates: + * ActionPort: '/Action Port' + */ + IfActionSubsystem(rtDW.ModeIndex[0], &rtB.Merge_j, &rtB.Merge1_j); + + /* End of Outputs for SubSystem: '/If Action Subsystem' */ + break; + + case 3: + /* Outputs for IfAction SubSystem: '/If Action Subsystem1' incorporates: + * ActionPort: '/Action Port' + */ + IfActionSubsystem1(&rtB.Merge_j, &rtB.Merge1_j); + + /* End of Outputs for SubSystem: '/If Action Subsystem1' */ + break; + + case 4: + case 5: + case 6: + /* Outputs for IfAction SubSystem: '/If Action Subsystem2' incorporates: + * ActionPort: '/Action Port' + */ + IfActionSubsystem2(rtDW.ModeIndex[0], &rtB.Merge_j, &rtB.Merge1_j); + + /* End of Outputs for SubSystem: '/If Action Subsystem2' */ + break; + } + + /* End of SwitchCase: '/Switch Case' */ + + /* DataStoreWrite: '/Data Store Write' */ + rtDW.Valve_individual_foot_FL = rtB.Merge_j; + + /* DataStoreWrite: '/Data Store Write1' */ + rtDW.Blower_individual_foot_FL = rtB.Merge1_j; + + /* End of Outputs for SubSystem: '/If Action Subsystem' */ + break; + + case 2: + /* Outputs for IfAction SubSystem: '/If Action Subsystem1' incorporates: + * ActionPort: '/Action Port' + */ + /* SwitchCase: '/Switch Case' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read' + */ + switch (rtDW.CCU_SET_FOOT_FL) { + case 0: + case 1: + case 2: + /* Outputs for IfAction SubSystem: '/If Action Subsystem' incorporates: + * ActionPort: '/Action Port' + */ + IfActionSubsystem_b(rtDW.ModeIndex[0], &rtB.Merge_i2, &rtB.Merge1_h); + + /* End of Outputs for SubSystem: '/If Action Subsystem' */ + break; + + case 3: + /* Outputs for IfAction SubSystem: '/If Action Subsystem1' incorporates: + * ActionPort: '/Action Port' + */ + IfActionSubsystem1(&rtB.Merge_i2, &rtB.Merge1_h); + + /* End of Outputs for SubSystem: '/If Action Subsystem1' */ + break; + + case 4: + case 5: + case 6: + /* Outputs for IfAction SubSystem: '/If Action Subsystem2' incorporates: + * ActionPort: '/Action Port' + */ + IfActionSubsystem2_o(rtDW.ModeIndex[0], &rtB.Merge_i2, &rtB.Merge1_h); + + /* End of Outputs for SubSystem: '/If Action Subsystem2' */ + break; + } + + /* End of SwitchCase: '/Switch Case' */ + + /* DataStoreWrite: '/Data Store Write' */ + rtDW.Valve_individual_foot_FL = rtB.Merge_i2; + + /* DataStoreWrite: '/Data Store Write1' */ + rtDW.Blower_individual_foot_FL = rtB.Merge1_h; + + /* End of Outputs for SubSystem: '/If Action Subsystem1' */ + break; + + case 3: + /* Outputs for IfAction SubSystem: '/If Action Subsystem2' incorporates: + * ActionPort: '/Action Port' + */ + /* SwitchCase: '/Switch Case' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read' + */ + switch (rtDW.CCU_SET_FOOT_FL) { + case 0: + case 1: + case 2: + /* Outputs for IfAction SubSystem: '/If Action Subsystem' incorporates: + * ActionPort: '/Action Port' + */ + IfActionSubsystem_n(rtDW.ModeIndex[0], &rtB.Merge_he, &rtB.Merge1_c); + + /* End of Outputs for SubSystem: '/If Action Subsystem' */ + break; + + case 3: + /* Outputs for IfAction SubSystem: '/If Action Subsystem1' incorporates: + * ActionPort: '/Action Port' + */ + IfActionSubsystem1(&rtB.Merge_he, &rtB.Merge1_c); + + /* End of Outputs for SubSystem: '/If Action Subsystem1' */ + break; + + case 4: + case 5: + case 6: + /* Outputs for IfAction SubSystem: '/If Action Subsystem2' incorporates: + * ActionPort: '/Action Port' + */ + IfActionSubsystem2_c(rtDW.ModeIndex[0], &rtB.Merge_he, &rtB.Merge1_c); + + /* End of Outputs for SubSystem: '/If Action Subsystem2' */ + break; + } + + /* End of SwitchCase: '/Switch Case' */ + + /* DataStoreWrite: '/Data Store Write' */ + rtDW.Valve_individual_foot_FL = rtB.Merge_he; + + /* DataStoreWrite: '/Data Store Write1' */ + rtDW.Blower_individual_foot_FL = rtB.Merge1_c; + + /* End of Outputs for SubSystem: '/If Action Subsystem2' */ + break; + } + + /* End of SwitchCase: '/Switch Case' */ + + /* Lookup_n-D: '/1-D Lookup Table' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write' + */ + rtDW.Dtg_individual_foot_FR = look1_iu8lu64n48ts16Ds32_binlcs + (rtDW.CCU_SET_FOOT_FR, rtConstP.pooled130, &g_assFOOT_STEP_DUCT_TGT[0], 6U); + + /* SwitchCase: '/Switch Case' incorporates: + * DataStoreRead: '/Data Store Read' + */ + switch (rtDW.LEVEL) { + case 1: + /* Outputs for IfAction SubSystem: '/If Action Subsystem' incorporates: + * ActionPort: '/Action Port' + */ + /* SwitchCase: '/Switch Case' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read' + */ + switch (rtDW.CCU_SET_FOOT_FR) { + case 0: + case 1: + case 2: + /* Outputs for IfAction SubSystem: '/If Action Subsystem' incorporates: + * ActionPort: '/Action Port' + */ + IfActionSubsystem(rtDW.ModeIndex[1], &rtB.Merge_on, &rtB.Merge1_g); + + /* End of Outputs for SubSystem: '/If Action Subsystem' */ + break; + + case 3: + /* Outputs for IfAction SubSystem: '/If Action Subsystem1' incorporates: + * ActionPort: '/Action Port' + */ + IfActionSubsystem1(&rtB.Merge_on, &rtB.Merge1_g); + + /* End of Outputs for SubSystem: '/If Action Subsystem1' */ + break; + + case 4: + case 5: + case 6: + /* Outputs for IfAction SubSystem: '/If Action Subsystem2' incorporates: + * ActionPort: '/Action Port' + */ + IfActionSubsystem2(rtDW.ModeIndex[1], &rtB.Merge_on, &rtB.Merge1_g); + + /* End of Outputs for SubSystem: '/If Action Subsystem2' */ + break; + } + + /* End of SwitchCase: '/Switch Case' */ + + /* DataStoreWrite: '/Data Store Write' */ + rtDW.Valve_individual_foot_FR = rtB.Merge_on; + + /* DataStoreWrite: '/Data Store Write1' */ + rtDW.Blower_individual_foot_FR = rtB.Merge1_g; + + /* End of Outputs for SubSystem: '/If Action Subsystem' */ + break; + + case 2: + /* Outputs for IfAction SubSystem: '/If Action Subsystem1' incorporates: + * ActionPort: '/Action Port' + */ + /* SwitchCase: '/Switch Case' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read' + */ + switch (rtDW.CCU_SET_FOOT_FR) { + case 0: + case 1: + case 2: + /* Outputs for IfAction SubSystem: '/If Action Subsystem' incorporates: + * ActionPort: '/Action Port' + */ + IfActionSubsystem_b(rtDW.ModeIndex[1], &rtB.Merge_o, &rtB.Merge1_e); + + /* End of Outputs for SubSystem: '/If Action Subsystem' */ + break; + + case 3: + /* Outputs for IfAction SubSystem: '/If Action Subsystem1' incorporates: + * ActionPort: '/Action Port' + */ + IfActionSubsystem1(&rtB.Merge_o, &rtB.Merge1_e); + + /* End of Outputs for SubSystem: '/If Action Subsystem1' */ + break; + + case 4: + case 5: + case 6: + /* Outputs for IfAction SubSystem: '/If Action Subsystem2' incorporates: + * ActionPort: '/Action Port' + */ + IfActionSubsystem2_o(rtDW.ModeIndex[1], &rtB.Merge_o, &rtB.Merge1_e); + + /* End of Outputs for SubSystem: '/If Action Subsystem2' */ + break; + } + + /* End of SwitchCase: '/Switch Case' */ + + /* DataStoreWrite: '/Data Store Write' */ + rtDW.Valve_individual_foot_FR = rtB.Merge_o; + + /* DataStoreWrite: '/Data Store Write1' */ + rtDW.Blower_individual_foot_FR = rtB.Merge1_e; + + /* End of Outputs for SubSystem: '/If Action Subsystem1' */ + break; + + case 3: + /* Outputs for IfAction SubSystem: '/If Action Subsystem2' incorporates: + * ActionPort: '/Action Port' + */ + /* SwitchCase: '/Switch Case' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read' + */ + switch (rtDW.CCU_SET_FOOT_FR) { + case 0: + case 1: + case 2: + /* Outputs for IfAction SubSystem: '/If Action Subsystem' incorporates: + * ActionPort: '/Action Port' + */ + IfActionSubsystem_n(rtDW.ModeIndex[1], &rtB.Merge_p5, &rtB.Merge1); + + /* End of Outputs for SubSystem: '/If Action Subsystem' */ + break; + + case 3: + /* Outputs for IfAction SubSystem: '/If Action Subsystem1' incorporates: + * ActionPort: '/Action Port' + */ + IfActionSubsystem1(&rtB.Merge_p5, &rtB.Merge1); + + /* End of Outputs for SubSystem: '/If Action Subsystem1' */ + break; + + case 4: + case 5: + case 6: + /* Outputs for IfAction SubSystem: '/If Action Subsystem2' incorporates: + * ActionPort: '/Action Port' + */ + IfActionSubsystem2_c(rtDW.ModeIndex[1], &rtB.Merge_p5, &rtB.Merge1); + + /* End of Outputs for SubSystem: '/If Action Subsystem2' */ + break; + } + + /* End of SwitchCase: '/Switch Case' */ + + /* DataStoreWrite: '/Data Store Write' */ + rtDW.Valve_individual_foot_FR = rtB.Merge_p5; + + /* DataStoreWrite: '/Data Store Write1' */ + rtDW.Blower_individual_foot_FR = rtB.Merge1; + + /* End of Outputs for SubSystem: '/If Action Subsystem2' */ + break; + } + + /* End of SwitchCase: '/Switch Case' */ + + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreRead: '/Data Store Read10' + * DataStoreRead: '/Data Store Read11' + * DataStoreRead: '/Data Store Read4' + * DataStoreRead: '/Data Store Read5' + * DataStoreRead: '/Data Store Read6' + * DataStoreRead: '/Data Store Read7' + * DataStoreRead: '/Data Store Read8' + * DataStoreRead: '/Data Store Read9' + * DataStoreWrite: '/Data Store Write2' + */ + Status_Sensor_Model.Battery = 0; + Status_Sensor_Model.AMB = rtDW.AMB; + Status_Sensor_Model.Incar_FL = rtDW.Incar_FL; + Status_Sensor_Model.Incar_FR = rtDW.Incar_FR; + Status_Sensor_Model.Incar_RL = rtDW.Incar_RL; + Status_Sensor_Model.Incar_RR = rtDW.Incar_RR; + Status_Sensor_Model.Eva_F = rtDW.Eva_F; + Status_Sensor_Model.Eva_R = rtDW.Eva_R; + Status_Sensor_Model.Pressure = rtDW.Pressure; + Status_Sensor_Model.Duct_FL_Upper = 0; + Status_Sensor_Model.Duct_FL_Lower = 0; + Status_Sensor_Model.Duct_FR_Upper = 0; + Status_Sensor_Model.Duct_FR_Lower = 0; + Status_Sensor_Model.Duct_RL = 0; + Status_Sensor_Model.Duct_RR = 0; + Status_Sensor_Model.Duct_Side_FL = 0; + Status_Sensor_Model.Duct_Side_FR = 0; + Status_Sensor_Model.Duct_Side_RL = 0; + Status_Sensor_Model.Duct_Side_RR = 0; + Status_Sensor_Model.AQS = 0; + + /* Product: '/Divide1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide' + */ + rtb_Add_be = (double)rtDW.ADC_Data_Model.Sensor_Incar_Temp_FL / 4095.0 * 5.0; + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + rtb_Compare_hv = (rtb_Add_be < 0.05); + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + rtb_Compare_df = (rtb_Add_be > 4.8); + + /* Logic: '/Logical Operator' */ + rtb_Compare_i5 = (rtb_Compare_hv || rtb_Compare_df); + + /* Logic: '/Logical Operator1' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read4' + * RelationalOperator: '/Compare' + * Sum: '/Subtract' + * UnitDelay: '/t_start_delay_private ' + */ + rtb_err = (rtb_Compare_i5 && (rtDW.t_now - rtDW.t_start_delay_private_DSTATE >= + 3000U)); + + /* Product: '/Divide5' incorporates: + * Constant: '/Constant6' + * Constant: '/Constant7' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide4' + */ + index_start = (double)rtDW.ADC_Data_Model.Sensor_Incar_Temp_FR / 4095.0 * 5.0; + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + rtb_Compare_ls = (index_start < 0.05); + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + rtb_Compare_ne = (index_start > 4.8); + + /* Logic: '/Logical Operator5' */ + rtb_FailCond_jb = (rtb_Compare_ls || rtb_Compare_ne); + + /* Logic: '/Logical Operator6' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read4' + * RelationalOperator: '/Compare' + * Sum: '/Subtract' + * UnitDelay: '/t_start_delay_private ' + */ + rtb_LogicalOperator6 = (rtb_FailCond_jb && (rtDW.t_now - + rtDW.t_start_delay_private_DSTATE_i >= 3000U)); + + /* Lookup_n-D: '/1-D Lookup Table4' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + rtDW.Incar_FR = look1_iu16tdIs16_binlcs + (rtDW.ADC_Data_Model.Sensor_Incar_Temp_FR, rtConstP.pooled80, + rtConstP.pooled37, 1023U); + + /* Lookup_n-D: '/1-D Lookup Table2' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + rtb_FLU_tg_correct_aa = look1_iu16tdIs16_binlcs + (rtDW.ADC_Data_Model.Sensor_Incar_Temp_FL, rtConstP.pooled80, + rtConstP.pooled37, 1023U); + + /* Switch: '/Switch' incorporates: + * Constant: '/ ' + * DataStoreWrite: '/Data Store Write1' + * Logic: '/Logical Operator1' + * Switch: '/Switch1' + * Switch: '/Switch2' + */ + if (rtb_err && rtb_LogicalOperator6) { + rtDW.Incar_FL = 200; + + /* Lookup_n-D: '/1-D Lookup Table4' incorporates: + * Constant: '/ ' + * Constant: '/ 1' + * DataStoreWrite: '/Data Store Write1' + */ + rtDW.Incar_FR = 200; + } else { + if (rtb_err) { + /* Switch: '/Switch1' incorporates: + * DataStoreWrite: '/Data Store Write1' + */ + rtDW.Incar_FL = rtDW.Incar_FR; + } else { + rtDW.Incar_FL = rtb_FLU_tg_correct_aa; + } + + /* Switch: '/Switch3' incorporates: + * DataStoreWrite: '/Data Store Write1' + * Switch: '/Switch1' + */ + if (rtb_LogicalOperator6) { + /* Lookup_n-D: '/1-D Lookup Table4' */ + rtDW.Incar_FR = rtb_FLU_tg_correct_aa; + } + + /* End of Switch: '/Switch3' */ + } + + /* End of Switch: '/Switch' */ + + /* Product: '/Divide3' incorporates: + * Constant: '/Constant3' + * Constant: '/Constant4' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide2' + */ + rtb_Divide3 = (double)rtDW.ADC_Data_Model.Sensor_Incar_Temp_RL / 4095.0 * 5.0; + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + rtb_Compare_kb = (rtb_Divide3 < 0.05); + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + rtb_Compare_l = (rtb_Divide3 > 4.8); + + /* Logic: '/Logical Operator2' */ + rtb_FailCond_e = (rtb_Compare_kb || rtb_Compare_l); + + /* Logic: '/Logical Operator3' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read4' + * RelationalOperator: '/Compare' + * Sum: '/Subtract' + * UnitDelay: '/t_start_delay_private ' + */ + rtb_LogicalOperator3 = (rtb_FailCond_e && (rtDW.t_now - + rtDW.t_start_delay_private_DSTATE_k >= 3000U)); + + /* Product: '/Divide7' incorporates: + * Constant: '/Constant10' + * Constant: '/Constant9' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide6' + */ + rtb_Divide7 = (double)rtDW.ADC_Data_Model.Sensor_Incar_Temp_RR / 4095.0 * 5.0; + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + rtb_Compare_g1 = (rtb_Divide7 < 0.05); + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + rtb_Compare_il = (rtb_Divide7 > 4.8); + + /* Logic: '/Logical Operator7' */ + rtb_FailCond_l = (rtb_Compare_g1 || rtb_Compare_il); + + /* Logic: '/Logical Operator8' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read4' + * RelationalOperator: '/Compare' + * Sum: '/Subtract' + * UnitDelay: '/t_start_delay_private ' + */ + rtb_LogicalOperator8 = (rtb_FailCond_l && (rtDW.t_now - + rtDW.t_start_delay_private_DSTATE_p >= 3000U)); + + /* Lookup_n-D: '/1-D Lookup Table3' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + rtDW.Incar_RR = look1_iu16tdIs16_binlcs + (rtDW.ADC_Data_Model.Sensor_Incar_Temp_RR, rtConstP.pooled80, + rtConstP.pooled37, 1023U); + + /* Lookup_n-D: '/1-D Lookup Table1' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + rtb_FLU_tg_correct_aa = look1_iu16tdIs16_binlcs + (rtDW.ADC_Data_Model.Sensor_Incar_Temp_RL, rtConstP.pooled80, + rtConstP.pooled37, 1023U); + + /* Switch: '/Switch' incorporates: + * Constant: '/ ' + * DataStoreWrite: '/Data Store Write4' + * Logic: '/Logical Operator1' + * Switch: '/Switch1' + */ + if (rtb_LogicalOperator3 && rtb_LogicalOperator8) { + rtDW.Incar_RL = 200; + } else if (rtb_LogicalOperator3) { + /* Switch: '/Switch1' incorporates: + * DataStoreWrite: '/Data Store Write4' + */ + rtDW.Incar_RL = rtDW.Incar_RR; + } else { + rtDW.Incar_RL = rtb_FLU_tg_correct_aa; + } + + /* End of Switch: '/Switch' */ + + /* Switch: '/Switch2' incorporates: + * Logic: '/Logical Operator2' + * Switch: '/Switch3' + */ + if (rtb_LogicalOperator3 && (rtDW.Incar_RR != 0)) { + /* Lookup_n-D: '/1-D Lookup Table3' incorporates: + * Constant: '/ 1' + */ + rtDW.Incar_RR = 200; + } else if (rtb_LogicalOperator8) { + /* Lookup_n-D: '/1-D Lookup Table3' incorporates: + * Switch: '/Switch3' + */ + rtDW.Incar_RR = rtb_FLU_tg_correct_aa; + } + + /* End of Switch: '/Switch2' */ + + /* Product: '/Divide1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide' + */ + rtb_Add_p4 = (double)rtDW.ADC_Data_Model.Sensor_Evap_Temp / 4095.0 * 5.0; + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + rtb_Compare_edx = (rtb_Add_p4 < 0.1); + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + rtb_Compare_e1 = (rtb_Add_p4 > 4.9); + + /* Logic: '/Logical Operator' */ + rtb_FailCond_a = (rtb_Compare_edx || rtb_Compare_e1); + + /* Logic: '/Logical Operator1' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read4' + * RelationalOperator: '/Compare' + * Sum: '/Subtract' + * UnitDelay: '/t_start_delay_private ' + */ + rtb_LogicalOperator1 = (rtb_FailCond_a && (rtDW.t_now - + rtDW.t_start_delay_private_DSTATE_g >= 3000U)); + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + rtDW.CCU_EvaTempSenErrF_Stat = rtb_LogicalOperator1; + + /* Switch: '/Switch' incorporates: + * Constant: '/Constant2' + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write1' + * Lookup_n-D: '/1-D Lookup Table' + */ + if (rtb_LogicalOperator1) { + rtDW.Eva_F = -100; + } else { + rtDW.Eva_F = look1_iu16tdIs16_binlcs(rtDW.ADC_Data_Model.Sensor_Evap_Temp, + rtConstP.pooled80, rtConstP.pooled8, 1023U); + } + + /* End of Switch: '/Switch' */ + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataTypeConversion: '/Data Type Conversion' + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.dtc_state_error_model[12] = rtb_LogicalOperator1; + + /* Switch: '/Switch' incorporates: + * DataTypeConversion: '/Data Type Conversion' + * Switch: '/Switch1' + */ + if (rtb_LogicalOperator1) { + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataTypeConversion: '/Data Type Conversion1' + */ + rtDW.dtc_state_error_model[13] = rtb_Compare_edx; + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataTypeConversion: '/Data Type Conversion2' + */ + rtDW.dtc_state_error_model[12] = rtb_Compare_e1; + } else { + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.dtc_state_error_model[13] = 0U; + } + + /* End of Switch: '/Switch' */ + + /* MATLAB Function: '/Write ERROR' incorporates: + * DataStoreRead: '/Data Store Read' + */ + /* : if(LOGGER) */ + if ((rtDW.LOGGER_ACP != 0.0) && rtb_LogicalOperator1) { + /* : if(EvapFErr) */ + /* : fprintf('CCU_Body_Err.CCU_EvaTempSenErrF_Stat = 0x1 (Failure), Sensor_Evap_Temp = %f V\n',Sensor_Evap_Temp); */ + printf("CCU_Body_Err.CCU_EvaTempSenErrF_Stat = 0x1 (Failure), Sensor_Evap_Temp = %f V\n", + rtb_Add_p4); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write ERROR' */ + + /* MATLAB Function: '/Write Eva_F' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write1' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('Eva_F = %d * 0.1 C\n',Eva_F); */ + printf("Eva_F = %d * 0.1 C\n", rtDW.Eva_F); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write Eva_F' */ + + /* Switch: '/Switch' incorporates: + * DataStoreRead: '/Data Store Read4' + * Logic: '/Logical Operator3' + * Logic: '/Logical Operator4' + * UnitDelay: '/Cond_prev_private ' + * UnitDelay: '/t_start_delay_private ' + */ + if (rtb_FailCond_a && (!rtDW.Cond_prev_private_DSTATE)) { + rtDW.t_start_delay_private_DSTATE_g = rtDW.t_now; + } + + /* End of Switch: '/Switch' */ + + /* Product: '/Divide1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide' + */ + rtb_Add_p4 = (double)rtDW.ADC_Data_Model.Sensor_Rear_Evap_Temp / 4095.0 * 5.0; + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + rtb_Compare_e1 = (rtb_Add_p4 < 0.1); + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + rtb_LogicalOperator1 = (rtb_Add_p4 > 4.9); + + /* Logic: '/Logical Operator' */ + rtb_Compare_edx = (rtb_Compare_e1 || rtb_LogicalOperator1); + + /* Logic: '/Logical Operator1' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read4' + * RelationalOperator: '/Compare' + * Sum: '/Subtract' + * UnitDelay: '/t_start_delay_private ' + */ + rtb_LogicalOperator1_dv = (rtb_Compare_edx && (rtDW.t_now - + rtDW.t_start_delay_private_DSTATE_c >= 3000U)); + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + rtDW.CCU_EvaTempSenErrR_Stat = rtb_LogicalOperator1_dv; + + /* Switch: '/Switch' incorporates: + * Constant: '/Constant2' + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write1' + * Lookup_n-D: '/1-D Lookup Table' + */ + if (rtb_LogicalOperator1_dv) { + rtDW.Eva_R = -100; + } else { + rtDW.Eva_R = look1_iu16tdIs16_binlcs + (rtDW.ADC_Data_Model.Sensor_Rear_Evap_Temp, rtConstP.pooled80, + rtConstP.pooled8, 1023U); + } + + /* End of Switch: '/Switch' */ + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataTypeConversion: '/Data Type Conversion' + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.dtc_state_error_model[14] = rtb_LogicalOperator1_dv; + + /* Switch: '/Switch' incorporates: + * DataTypeConversion: '/Data Type Conversion' + * Switch: '/Switch1' + */ + if (rtb_LogicalOperator1_dv) { + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataTypeConversion: '/Data Type Conversion1' + */ + rtDW.dtc_state_error_model[15] = rtb_Compare_e1; + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataTypeConversion: '/Data Type Conversion2' + */ + rtDW.dtc_state_error_model[14] = rtb_LogicalOperator1; + } else { + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.dtc_state_error_model[15] = 0U; + } + + /* End of Switch: '/Switch' */ + + /* MATLAB Function: '/Write ERROR' incorporates: + * DataStoreRead: '/Data Store Read' + */ + /* : if(LOGGER) */ + if ((rtDW.LOGGER_ACP != 0.0) && rtb_LogicalOperator1_dv) { + /* : if(EvapRErr) */ + /* : fprintf('CCU_Body_Err.CCU_EvaTempSenErrR_Stat = 0x1 (Failure), Sensor_Rear_Evap_Temp = %f V\n',Sensor_Rear_Evap_Temp); */ + printf("CCU_Body_Err.CCU_EvaTempSenErrR_Stat = 0x1 (Failure), Sensor_Rear_Evap_Temp = %f V\n", + rtb_Add_p4); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write ERROR' */ + + /* MATLAB Function: '/Write Eva_F' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write1' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('Eva_R = %d * 0.1 C\n',Eva_R); */ + printf("Eva_R = %d * 0.1 C\n", rtDW.Eva_R); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write Eva_F' */ + + /* Switch: '/Switch' incorporates: + * DataStoreRead: '/Data Store Read4' + * Logic: '/Logical Operator3' + * Logic: '/Logical Operator4' + * UnitDelay: '/Cond_prev_private ' + * UnitDelay: '/t_start_delay_private ' + */ + if (rtb_Compare_edx && (!rtDW.Cond_prev_private_DSTATE_p)) { + rtDW.t_start_delay_private_DSTATE_c = rtDW.t_now; + } + + /* End of Switch: '/Switch' */ + + /* Product: '/Divide1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide' + */ + rtb_Add_p4 = (double)rtDW.ADC_Data_Model.Sensor_AC_Pressure / 4095.0 * 5.0; + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + rtb_LogicalOperator1 = (rtb_Add_p4 < 0.1); + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + rtb_LogicalOperator1_dv = (rtb_Add_p4 > 4.9); + + /* Logic: '/Logical Operator' */ + rtb_Compare_e1 = (rtb_LogicalOperator1 || rtb_LogicalOperator1_dv); + + /* Logic: '/Logical Operator1' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read4' + * RelationalOperator: '/Compare' + * Sum: '/Subtract' + * UnitDelay: '/t_start_delay_private ' + */ + rtb_LogicalOperator1_n = (rtb_Compare_e1 && (rtDW.t_now - + rtDW.t_start_delay_private_DSTATE_h >= 3000U)); + + /* Switch: '/Switch' incorporates: + * Constant: '/Constant2' + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write' + * Lookup_n-D: '/1-D Lookup Table' + */ + if (rtb_LogicalOperator1_n) { + rtDW.Pressure = 320; + } else { + rtDW.Pressure = look1_iu16tdIs16_binlcs + (rtDW.ADC_Data_Model.Sensor_AC_Pressure, rtConstP.pooled80, + rtConstP.uDLookupTable_tableData, 1023U); + } + + /* End of Switch: '/Switch' */ + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * DataStoreWrite: '/Data Store Write1' + */ + rtDW.CCU_PressSenErr_Stat = rtb_LogicalOperator1_n; + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataTypeConversion: '/Data Type Conversion' + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.dtc_state_error_model[51] = rtb_LogicalOperator1_n; + + /* Switch: '/Switch' incorporates: + * DataTypeConversion: '/Data Type Conversion' + * Switch: '/Switch1' + */ + if (rtb_LogicalOperator1_n) { + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataTypeConversion: '/Data Type Conversion1' + */ + rtDW.dtc_state_error_model[50] = rtb_LogicalOperator1; + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataTypeConversion: '/Data Type Conversion2' + */ + rtDW.dtc_state_error_model[51] = rtb_LogicalOperator1_dv; + } else { + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.dtc_state_error_model[50] = 0U; + } + + /* End of Switch: '/Switch' */ + + /* MATLAB Function: '/Write' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('AC_Pressure = %d ATM\n',AC_Pressure); */ + printf("AC_Pressure = %d ATM\n", rtDW.Pressure); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + + /* MATLAB Function: '/Write ERROR' incorporates: + * DataStoreRead: '/Data Store Read' + */ + /* : if(LOGGER) */ + if ((rtDW.LOGGER_ACP != 0.0) && rtb_LogicalOperator1_n) { + /* : if(AC_PressureErr) */ + /* : fprintf('CCU_Body_Err.CCU_PressSenErr_Stat = 0x1 (Failure), Sensor_AC_Pressure = %f V\n',Sensor_AC_Pressure); */ + printf("CCU_Body_Err.CCU_PressSenErr_Stat = 0x1 (Failure), Sensor_AC_Pressure = %f V\n", + rtb_Add_p4); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write ERROR' */ + + /* Switch: '/Switch' incorporates: + * DataStoreRead: '/Data Store Read4' + * Logic: '/Logical Operator3' + * Logic: '/Logical Operator4' + * UnitDelay: '/Cond_prev_private ' + * UnitDelay: '/t_start_delay_private ' + */ + if (rtb_Compare_e1 && (!rtDW.Cond_prev_private_DSTATE_a)) { + rtDW.t_start_delay_private_DSTATE_h = rtDW.t_now; + } + + /* End of Switch: '/Switch' */ + + /* Product: '/Divide3' incorporates: + * Constant: '/Constant3' + * Constant: '/Constant4' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide2' + */ + rtb_Add_p4 = (double)rtDW.ADC_Data_Model.Sensor_Front_Duct1 / 4095.0 * 5.0; + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + rtb_Compare_g2 = (rtb_Add_p4 < 0.15); + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + rtb_Compare_fh = (rtb_Add_p4 > 4.9); + + /* Logic: '/Logical Operator2' */ + rtb_LogicalOperator1 = (rtb_Compare_g2 || rtb_Compare_fh); + + /* Logic: '/Logical Operator3' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read4' + * RelationalOperator: '/Compare' + * Sum: '/Subtract' + * UnitDelay: '/t_start_delay_private ' + */ + rtb_LogicalOperator3_cz = (rtb_LogicalOperator1 && (rtDW.t_now - + rtDW.t_start_delay_private_DSTATE_kc >= 3000U)); + + /* Product: '/Divide4' incorporates: + * Constant: '/Constant1' + * Constant: '/Constant2' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide1' + */ + rtb_Divide4 = (double)rtDW.ADC_Data_Model.Sensor_Front_Duct2 / 4095.0 * 5.0; + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + rtb_Compare_ipf = (rtb_Divide4 < 0.15); + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + rtb_Compare_pb = (rtb_Divide4 > 4.9); + + /* Logic: '/Logical Operator1' */ + rtb_LogicalOperator1_dv = (rtb_Compare_ipf || rtb_Compare_pb); + + /* Logic: '/Logical Operator4' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read4' + * RelationalOperator: '/Compare' + * Sum: '/Subtract' + * UnitDelay: '/t_start_delay_private ' + */ + rtb_LogicalOperator4_fo = (rtb_LogicalOperator1_dv && (rtDW.t_now - + rtDW.t_start_delay_private_DSTATE_m >= 3000U)); + + /* Product: '/Divide6' incorporates: + * Constant: '/Constant7' + * Constant: '/Constant8' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide5' + */ + rtb_Divide6 = (double)rtDW.ADC_Data_Model.Sensor_Front_Duct3 / 4095.0 * 5.0; + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + rtb_Compare_gk = (rtb_Divide6 < 0.15); + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + rtb_Compare_jl3 = (rtb_Divide6 > 4.9); + + /* Logic: '/Logical Operator5' */ + rtb_LogicalOperator1_n = (rtb_Compare_gk || rtb_Compare_jl3); + + /* Logic: '/Logical Operator6' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read4' + * RelationalOperator: '/Compare' + * Sum: '/Subtract' + * UnitDelay: '/t_start_delay_private ' + */ + rtb_LogicalOperator6_m = (rtb_LogicalOperator1_n && (rtDW.t_now - + rtDW.t_start_delay_private_DSTATE_pn >= 3000U)); + + /* Product: '/Divide8' incorporates: + * Constant: '/Constant10' + * Constant: '/Constant11' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide7' + */ + rtb_Divide8 = (double)rtDW.ADC_Data_Model.Sensor_Front_Duct4 / 4095.0 * 5.0; + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + rtb_Compare_jz = (rtb_Divide8 < 0.15); + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + rtb_Compare_e3 = (rtb_Divide8 > 4.9); + + /* Logic: '/Logical Operator7' */ + rtb_FailCond_kd = (rtb_Compare_jz || rtb_Compare_e3); + + /* Logic: '/Logical Operator8' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read4' + * RelationalOperator: '/Compare' + * Sum: '/Subtract' + * UnitDelay: '/t_start_delay_private ' + */ + rtb_LogicalOperator8_i = (rtb_FailCond_kd && (rtDW.t_now - + rtDW.t_start_delay_private_DSTATE_hb >= 3000U)); + + /* Product: '/Divide10' incorporates: + * Constant: '/Constant13' + * Constant: '/Constant14' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide9' + */ + rtb_Divide10 = (double)rtDW.ADC_Data_Model.Sensor_Front_Duct5 / 4095.0 * 5.0; + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + rtb_Compare_ok = (rtb_Divide10 < 0.15); + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + rtb_Compare_ja = (rtb_Divide10 > 4.9); + + /* Logic: '/Logical Operator9' */ + rtb_FailCond_d = (rtb_Compare_ok || rtb_Compare_ja); + + /* Logic: '/Logical Operator10' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read4' + * RelationalOperator: '/Compare' + * Sum: '/Subtract' + * UnitDelay: '/t_start_delay_private ' + */ + rtb_LogicalOperator10 = (rtb_FailCond_d && (rtDW.t_now - + rtDW.t_start_delay_private_DSTATE_i3 >= 3000U)); + + /* Product: '/Divide11' incorporates: + * Constant: '/Constant16' + * Constant: '/Constant17' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide12' + */ + rtb_Divide11 = (double)rtDW.ADC_Data_Model.Sensor_Front_Duct6 / 4095.0 * 5.0; + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + rtb_Compare_cc = (rtb_Divide11 < 0.15); + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + rtb_Compare_kbl = (rtb_Divide11 > 4.9); + + /* Logic: '/Logical Operator12' */ + rtb_FailCond_ad = (rtb_Compare_cc || rtb_Compare_kbl); + + /* Logic: '/Logical Operator11' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read4' + * RelationalOperator: '/Compare' + * Sum: '/Subtract' + * UnitDelay: '/t_start_delay_private ' + */ + rtb_LogicalOperator11 = (rtb_FailCond_ad && (rtDW.t_now - + rtDW.t_start_delay_private_DSTATE_cc >= 3000U)); + + /* SignalConversion generated from: '/1-D Lookup Table7' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + rtb_TmpSignalConversionAt1DLookupTable7Inport1[0] = + rtDW.ADC_Data_Model.Sensor_Front_Duct1; + rtb_TmpSignalConversionAt1DLookupTable7Inport1[1] = + rtDW.ADC_Data_Model.Sensor_Front_Duct2; + rtb_TmpSignalConversionAt1DLookupTable7Inport1[2] = + rtDW.ADC_Data_Model.Sensor_Front_Duct3; + rtb_TmpSignalConversionAt1DLookupTable7Inport1[3] = + rtDW.ADC_Data_Model.Sensor_Front_Duct4; + rtb_TmpSignalConversionAt1DLookupTable7Inport1[4] = + rtDW.ADC_Data_Model.Sensor_Front_Duct5; + rtb_TmpSignalConversionAt1DLookupTable7Inport1[5] = + rtDW.ADC_Data_Model.Sensor_Front_Duct6; + + /* Lookup_n-D: '/1-D Lookup Table7' */ + for (i = 0; i < 6; i++) { + rtb_uDLookupTable7_g[i] = look1_iu16bs16lu64n32ts16Ds32_binlcs + (rtb_TmpSignalConversionAt1DLookupTable7Inport1[i], rtConstP.pooled67, + rtConstP.pooled66, 1023U); + } + + /* End of Lookup_n-D: '/1-D Lookup Table7' */ + + /* Switch: '/Switch2' incorporates: + * Constant: '/Constant6' + * DataStoreWrite: '/Data Store Write1' + */ + if (rtb_LogicalOperator4_fo) { + rtb_MultiportSwitch_pa = 230; + } else { + rtb_MultiportSwitch_pa = rtb_uDLookupTable7_g[1]; + } + + /* End of Switch: '/Switch2' */ + + /* Switch: '/Switch1' incorporates: + * Constant: '/Constant5' + * DataStoreWrite: '/Data Store Write2' + */ + if (rtb_LogicalOperator3_cz) { + rtb_Bias1_h = 230; + } else { + rtb_Bias1_h = rtb_uDLookupTable7_g[0]; + } + + /* End of Switch: '/Switch1' */ + + /* Switch: '/Switch3' incorporates: + * Constant: '/Constant9' + * DataStoreWrite: '/Data Store Write3' + */ + if (rtb_LogicalOperator6_m) { + rtb_FLU_tg_correct_ot = 230; + } else { + rtb_FLU_tg_correct_ot = rtb_uDLookupTable7_g[2]; + } + + /* End of Switch: '/Switch3' */ + + /* Switch: '/Switch4' incorporates: + * Constant: '/Constant12' + * DataStoreWrite: '/Data Store Write4' + */ + if (rtb_LogicalOperator8_i) { + Duct4_F = 230; + } else { + Duct4_F = rtb_uDLookupTable7_g[3]; + } + + /* End of Switch: '/Switch4' */ + + /* Switch: '/Switch5' incorporates: + * Constant: '/Constant15' + * DataStoreWrite: '/Data Store Write5' + */ + if (rtb_LogicalOperator10) { + Duct5_F = 230; + } else { + Duct5_F = rtb_uDLookupTable7_g[4]; + } + + /* End of Switch: '/Switch5' */ + + /* Switch: '/Switch6' incorporates: + * Constant: '/Constant18' + * DataStoreWrite: '/Data Store Write6' + */ + if (rtb_LogicalOperator11) { + Duct6_F = 230; + } else { + Duct6_F = rtb_uDLookupTable7_g[5]; + } + + /* End of Switch: '/Switch6' */ + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.dtc_state_error_model[17] = rtb_LogicalOperator3_cz; + + /* Switch: '/Switch' incorporates: + * DataTypeConversion: '/Data Type Conversion' + * Switch: '/Switch1' + */ + if (rtb_LogicalOperator3_cz) { + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataTypeConversion: '/Data Type Conversion1' + */ + rtDW.dtc_state_error_model[18] = rtb_Compare_g2; + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataTypeConversion: '/Data Type Conversion2' + */ + rtDW.dtc_state_error_model[17] = rtb_Compare_fh; + } else { + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.dtc_state_error_model[18] = 0U; + } + + /* End of Switch: '/Switch' */ + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.dtc_state_error_model[19] = rtb_LogicalOperator4_fo; + + /* Switch: '/Switch' incorporates: + * DataTypeConversion: '/Data Type Conversion' + * Switch: '/Switch1' + */ + if (rtb_LogicalOperator4_fo) { + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataTypeConversion: '/Data Type Conversion1' + */ + rtDW.dtc_state_error_model[20] = rtb_Compare_ipf; + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataTypeConversion: '/Data Type Conversion2' + */ + rtDW.dtc_state_error_model[19] = rtb_Compare_pb; + } else { + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.dtc_state_error_model[20] = 0U; + } + + /* End of Switch: '/Switch' */ + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.dtc_state_error_model[21] = rtb_LogicalOperator6_m; + + /* Switch: '/Switch' incorporates: + * DataTypeConversion: '/Data Type Conversion' + * Switch: '/Switch1' + */ + if (rtb_LogicalOperator6_m) { + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataTypeConversion: '/Data Type Conversion1' + */ + rtDW.dtc_state_error_model[22] = rtb_Compare_gk; + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataTypeConversion: '/Data Type Conversion2' + */ + rtDW.dtc_state_error_model[21] = rtb_Compare_jl3; + } else { + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.dtc_state_error_model[22] = 0U; + } + + /* End of Switch: '/Switch' */ + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.dtc_state_error_model[23] = rtb_LogicalOperator8_i; + + /* Switch: '/Switch' incorporates: + * DataTypeConversion: '/Data Type Conversion' + * Switch: '/Switch1' + */ + if (rtb_LogicalOperator8_i) { + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataTypeConversion: '/Data Type Conversion1' + */ + rtDW.dtc_state_error_model[24] = rtb_Compare_jz; + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataTypeConversion: '/Data Type Conversion2' + */ + rtDW.dtc_state_error_model[23] = rtb_Compare_e3; + } else { + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.dtc_state_error_model[24] = 0U; + } + + /* End of Switch: '/Switch' */ + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.dtc_state_error_model[25] = rtb_LogicalOperator10; + + /* Switch: '/Switch' incorporates: + * DataTypeConversion: '/Data Type Conversion' + * Switch: '/Switch1' + */ + if (rtb_LogicalOperator10) { + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataTypeConversion: '/Data Type Conversion1' + */ + rtDW.dtc_state_error_model[26] = rtb_Compare_ok; + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataTypeConversion: '/Data Type Conversion2' + */ + rtDW.dtc_state_error_model[25] = rtb_Compare_ja; + } else { + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.dtc_state_error_model[26] = 0U; + } + + /* End of Switch: '/Switch' */ + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.dtc_state_error_model[27] = rtb_LogicalOperator11; + + /* Switch: '/Switch' incorporates: + * DataTypeConversion: '/Data Type Conversion' + * Switch: '/Switch1' + */ + if (rtb_LogicalOperator11) { + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataTypeConversion: '/Data Type Conversion1' + */ + rtDW.dtc_state_error_model[28] = rtb_Compare_cc; + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataTypeConversion: '/Data Type Conversion2' + */ + rtDW.dtc_state_error_model[27] = rtb_Compare_kbl; + } else { + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.dtc_state_error_model[28] = 0U; + } + + /* End of Switch: '/Switch' */ + + /* MATLAB Function: '/Write 1' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write2' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('Duct1_F = %d * 0.1 C\n',Sensor); */ + printf("Duct1_F = %d * 0.1 C\n", rtb_Bias1_h); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write 1' */ + + /* MATLAB Function: '/Write 2' incorporates: + * DataStoreRead: '/Data Store Read2' + * DataStoreWrite: '/Data Store Write1' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('Duct2_F = %d * 0.1 C\n',Sensor); */ + printf("Duct2_F = %d * 0.1 C\n", rtb_MultiportSwitch_pa); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write 2' */ + + /* MATLAB Function: '/Write 3' incorporates: + * DataStoreRead: '/Data Store Read3' + * DataStoreWrite: '/Data Store Write3' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('Duct3_F = %d * 0.1 C\n',Sensor); */ + printf("Duct3_F = %d * 0.1 C\n", rtb_FLU_tg_correct_ot); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write 3' */ + + /* MATLAB Function: '/Write 4' incorporates: + * DataStoreRead: '/Data Store Read4' + * DataStoreWrite: '/Data Store Write4' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('Duct4_F = %d * 0.1 C\n',Sensor); */ + printf("Duct4_F = %d * 0.1 C\n", Duct4_F); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write 4' */ + + /* MATLAB Function: '/Write 5' incorporates: + * DataStoreRead: '/Data Store Read5' + * DataStoreWrite: '/Data Store Write5' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('Duct5_F = %d * 0.1 C\n',Sensor); */ + printf("Duct5_F = %d * 0.1 C\n", Duct5_F); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write 5' */ + + /* MATLAB Function: '/Write 6' incorporates: + * DataStoreRead: '/Data Store Read6' + * DataStoreWrite: '/Data Store Write6' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('Duct6_F = %d * 0.1 C\n',Sensor); */ + printf("Duct6_F = %d * 0.1 C\n", Duct6_F); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write 6' */ + + /* MATLAB Function: '/Write ERROR1' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + /* : if(LOGGER) */ + if ((rtDW.LOGGER_ACP != 0.0) && rtb_LogicalOperator3_cz) { + /* : if(Err) */ + /* : fprintf('CCU_Body_Err.CCU_DuctTempSenErrF_Stat = 0x1 (Failure), Sensor_Duct1_F = %f V\n',Sensor); */ + printf("CCU_Body_Err.CCU_DuctTempSenErrF_Stat = 0x1 (Failure), Sensor_Duct1_F = %f V\n", + rtb_Add_p4); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write ERROR1' */ + + /* MATLAB Function: '/Write ERROR2' incorporates: + * DataStoreRead: '/Data Store Read2' + */ + /* : if(LOGGER) */ + if ((rtDW.LOGGER_ACP != 0.0) && rtb_LogicalOperator4_fo) { + /* : if(Err) */ + /* : fprintf('CCU_Body_Err.CCU_DuctTempSenErrF_Stat = 0x1 (Failure), Sensor_Duct2_F = %f V\n',Sensor); */ + printf("CCU_Body_Err.CCU_DuctTempSenErrF_Stat = 0x1 (Failure), Sensor_Duct2_F = %f V\n", + rtb_Divide4); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write ERROR2' */ + + /* MATLAB Function: '/Write ERROR3' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + /* : if(LOGGER) */ + if ((rtDW.LOGGER_ACP != 0.0) && rtb_LogicalOperator6_m) { + /* : if(Err) */ + /* : fprintf('CCU_Body_Err.CCU_DuctTempSenErrF_Stat = 0x1 (Failure), Sensor_Duct3_F = %f V\n',Sensor); */ + printf("CCU_Body_Err.CCU_DuctTempSenErrF_Stat = 0x1 (Failure), Sensor_Duct3_F = %f V\n", + rtb_Divide6); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write ERROR3' */ + + /* MATLAB Function: '/Write ERROR4' incorporates: + * DataStoreRead: '/Data Store Read4' + */ + /* : if(LOGGER) */ + if ((rtDW.LOGGER_ACP != 0.0) && rtb_LogicalOperator8_i) { + /* : if(Err) */ + /* : fprintf('CCU_Body_Err.CCU_DuctTempSenErrF_Stat = 0x1 (Failure), Sensor_Duct4_F = %f V\n',Sensor); */ + printf("CCU_Body_Err.CCU_DuctTempSenErrF_Stat = 0x1 (Failure), Sensor_Duct4_F = %f V\n", + rtb_Divide8); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write ERROR4' */ + + /* MATLAB Function: '/Write ERROR5' incorporates: + * DataStoreRead: '/Data Store Read5' + */ + /* : if(LOGGER) */ + if ((rtDW.LOGGER_ACP != 0.0) && rtb_LogicalOperator10) { + /* : if(Err) */ + /* : fprintf('CCU_Body_Err.CCU_DuctTempSenErrF_Stat = 0x1 (Failure), Sensor_Duct5_F = %f V\n',Sensor); */ + printf("CCU_Body_Err.CCU_DuctTempSenErrF_Stat = 0x1 (Failure), Sensor_Duct5_F = %f V\n", + rtb_Divide10); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write ERROR5' */ + + /* MATLAB Function: '/Write ERROR6' incorporates: + * DataStoreRead: '/Data Store Read6' + */ + /* : if(LOGGER) */ + if ((rtDW.LOGGER_ACP != 0.0) && rtb_LogicalOperator11) { + /* : if(Err) */ + /* : fprintf('CCU_Body_Err.CCU_DuctTempSenErrF_Stat = 0x1 (Failure), Sensor_Duct6_F = %f V\n',Sensor); */ + printf("CCU_Body_Err.CCU_DuctTempSenErrF_Stat = 0x1 (Failure), Sensor_Duct6_F = %f V\n", + rtb_Divide11); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write ERROR6' */ + + /* Switch: '/Switch' incorporates: + * DataStoreRead: '/Data Store Read4' + * Logic: '/Logical Operator3' + * Logic: '/Logical Operator4' + * UnitDelay: '/Cond_prev_private ' + * UnitDelay: '/t_start_delay_private ' + */ + if (rtb_LogicalOperator1 && (!rtDW.Cond_prev_private_DSTATE_h)) { + rtDW.t_start_delay_private_DSTATE_kc = rtDW.t_now; + } + + /* End of Switch: '/Switch' */ + + /* Switch: '/Switch' incorporates: + * DataStoreRead: '/Data Store Read4' + * Logic: '/Logical Operator3' + * Logic: '/Logical Operator4' + * UnitDelay: '/Cond_prev_private ' + * UnitDelay: '/t_start_delay_private ' + */ + if (rtb_LogicalOperator1_dv && (!rtDW.Cond_prev_private_DSTATE_c)) { + rtDW.t_start_delay_private_DSTATE_m = rtDW.t_now; + } + + /* End of Switch: '/Switch' */ + + /* Switch: '/Switch' incorporates: + * DataStoreRead: '/Data Store Read4' + * Logic: '/Logical Operator3' + * Logic: '/Logical Operator4' + * UnitDelay: '/Cond_prev_private ' + * UnitDelay: '/t_start_delay_private ' + */ + if (rtb_LogicalOperator1_n && (!rtDW.Cond_prev_private_DSTATE_m)) { + rtDW.t_start_delay_private_DSTATE_pn = rtDW.t_now; + } + + /* End of Switch: '/Switch' */ + + /* Switch: '/Switch' incorporates: + * DataStoreRead: '/Data Store Read4' + * Logic: '/Logical Operator3' + * Logic: '/Logical Operator4' + * UnitDelay: '/Cond_prev_private ' + * UnitDelay: '/t_start_delay_private ' + */ + if (rtb_FailCond_kd && (!rtDW.Cond_prev_private_DSTATE_j)) { + rtDW.t_start_delay_private_DSTATE_hb = rtDW.t_now; + } + + /* End of Switch: '/Switch' */ + + /* Switch: '/Switch' incorporates: + * DataStoreRead: '/Data Store Read4' + * Logic: '/Logical Operator3' + * Logic: '/Logical Operator4' + * UnitDelay: '/Cond_prev_private ' + * UnitDelay: '/t_start_delay_private ' + */ + if (rtb_FailCond_d && (!rtDW.Cond_prev_private_DSTATE_f)) { + rtDW.t_start_delay_private_DSTATE_i3 = rtDW.t_now; + } + + /* End of Switch: '/Switch' */ + + /* Switch: '/Switch' incorporates: + * DataStoreRead: '/Data Store Read4' + * Logic: '/Logical Operator3' + * Logic: '/Logical Operator4' + * UnitDelay: '/Cond_prev_private ' + * UnitDelay: '/t_start_delay_private ' + */ + if (rtb_FailCond_ad && (!rtDW.Cond_prev_private_DSTATE_cn)) { + rtDW.t_start_delay_private_DSTATE_cc = rtDW.t_now; + } + + /* End of Switch: '/Switch' */ + + /* Product: '/Divide1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide' + */ + rtb_Add_p4 = (double)rtDW.ADC_Data_Model.Sensor_Rear_Duct1 / 4095.0 * 5.0; + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + rtb_Compare_ok = (rtb_Add_p4 < 0.15); + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + rtb_Compare_ja = (rtb_Add_p4 > 4.9); + + /* Logic: '/Logical Operator' */ + rtb_Compare_g2 = (rtb_Compare_ok || rtb_Compare_ja); + + /* Logic: '/Logical Operator1' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read4' + * RelationalOperator: '/Compare' + * Sum: '/Subtract' + * UnitDelay: '/t_start_delay_private ' + */ + rtb_Compare_gk = (rtb_Compare_g2 && (rtDW.t_now - + rtDW.t_start_delay_private_DSTATE_o >= 3000U)); + + /* Product: '/Divide3' incorporates: + * Constant: '/Constant3' + * Constant: '/Constant4' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide2' + */ + rtb_Divide4 = (double)rtDW.ADC_Data_Model.Sensor_Rear_Duct2 / 4095.0 * 5.0; + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + rtb_Compare_cc = (rtb_Divide4 < 0.15); + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + rtb_Compare_kbl = (rtb_Divide4 > 4.9); + + /* Logic: '/Logical Operator2' */ + rtb_Compare_fh = (rtb_Compare_cc || rtb_Compare_kbl); + + /* Logic: '/Logical Operator3' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read4' + * RelationalOperator: '/Compare' + * Sum: '/Subtract' + * UnitDelay: '/t_start_delay_private ' + */ + rtb_Compare_jl3 = (rtb_Compare_fh && (rtDW.t_now - + rtDW.t_start_delay_private_DSTATE_oy >= 3000U)); + + /* Product: '/Divide5' incorporates: + * Constant: '/Constant6' + * Constant: '/Constant7' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide4' + */ + rtb_Divide6 = (double)rtDW.ADC_Data_Model.Sensor_Rear_Duct3 / 4095.0 * 5.0; + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + rtb_Compare_m1 = (rtb_Divide6 < 0.15); + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + rtb_Compare_hg = (rtb_Divide6 > 4.9); + + /* Logic: '/Logical Operator5' */ + rtb_Compare_ipf = (rtb_Compare_m1 || rtb_Compare_hg); + + /* Logic: '/Logical Operator6' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read4' + * RelationalOperator: '/Compare' + * Sum: '/Subtract' + * UnitDelay: '/t_start_delay_private ' + */ + rtb_Compare_jz = (rtb_Compare_ipf && (rtDW.t_now - + rtDW.t_start_delay_private_DSTATE_cd >= 3000U)); + + /* Product: '/Divide7' incorporates: + * Constant: '/Constant10' + * Constant: '/Constant9' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide6' + */ + rtb_Divide8 = (double)rtDW.ADC_Data_Model.Sensor_Rear_Duct4 / 4095.0 * 5.0; + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + rtb_Compare_k3 = (rtb_Divide8 < 0.15); + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + rtb_Compare_a = (rtb_Divide8 > 4.9); + + /* Logic: '/Logical Operator7' */ + rtb_Compare_pb = (rtb_Compare_k3 || rtb_Compare_a); + + /* Logic: '/Logical Operator8' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read4' + * RelationalOperator: '/Compare' + * Sum: '/Subtract' + * UnitDelay: '/t_start_delay_private ' + */ + rtb_Compare_e3 = (rtb_Compare_pb && (rtDW.t_now - + rtDW.t_start_delay_private_DSTATE_or >= 3000U)); + + /* Switch: '/Switch' incorporates: + * Constant: '/Constant2' + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write1' + * Lookup_n-D: '/1-D Lookup Table4' + * SignalConversion generated from: '/1-D Lookup Table4' + */ + if (rtb_Compare_gk) { + Duct1_R = 230; + } else { + Duct1_R = look1_iu16bs16lu64n32ts16Ds32_binlcs + (rtDW.ADC_Data_Model.Sensor_Rear_Duct1, rtConstP.pooled67, + rtConstP.pooled66, 1023U); + } + + /* End of Switch: '/Switch' */ + + /* Switch: '/Switch1' incorporates: + * Constant: '/Constant5' + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write2' + * Lookup_n-D: '/1-D Lookup Table4' + * SignalConversion generated from: '/1-D Lookup Table4' + */ + if (rtb_Compare_jl3) { + Duct2_R = 230; + } else { + Duct2_R = look1_iu16bs16lu64n32ts16Ds32_binlcs + (rtDW.ADC_Data_Model.Sensor_Rear_Duct2, rtConstP.pooled67, + rtConstP.pooled66, 1023U); + } + + /* End of Switch: '/Switch1' */ + + /* Switch: '/Switch2' incorporates: + * Constant: '/Constant8' + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write3' + * Lookup_n-D: '/1-D Lookup Table4' + * SignalConversion generated from: '/1-D Lookup Table4' + */ + if (rtb_Compare_jz) { + Duct3_R = 230; + } else { + Duct3_R = look1_iu16bs16lu64n32ts16Ds32_binlcs + (rtDW.ADC_Data_Model.Sensor_Rear_Duct3, rtConstP.pooled67, + rtConstP.pooled66, 1023U); + } + + /* End of Switch: '/Switch2' */ + + /* Switch: '/Switch3' incorporates: + * Constant: '/Constant11' + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write4' + * Lookup_n-D: '/1-D Lookup Table4' + * SignalConversion generated from: '/1-D Lookup Table4' + */ + if (rtb_Compare_e3) { + Duct4_R = 230; + } else { + Duct4_R = look1_iu16bs16lu64n32ts16Ds32_binlcs + (rtDW.ADC_Data_Model.Sensor_Rear_Duct4, rtConstP.pooled67, + rtConstP.pooled66, 1023U); + } + + /* End of Switch: '/Switch3' */ + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.dtc_state_error_model[29] = rtb_Compare_gk; + + /* Switch: '/Switch' incorporates: + * DataTypeConversion: '/Data Type Conversion' + * Switch: '/Switch1' + */ + if (rtb_Compare_gk) { + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataTypeConversion: '/Data Type Conversion1' + */ + rtDW.dtc_state_error_model[30] = rtb_Compare_ok; + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataTypeConversion: '/Data Type Conversion2' + */ + rtDW.dtc_state_error_model[29] = rtb_Compare_ja; + } else { + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.dtc_state_error_model[30] = 0U; + } + + /* End of Switch: '/Switch' */ + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.dtc_state_error_model[31] = rtb_Compare_jl3; + + /* Switch: '/Switch' incorporates: + * DataTypeConversion: '/Data Type Conversion' + * Switch: '/Switch1' + */ + if (rtb_Compare_jl3) { + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataTypeConversion: '/Data Type Conversion1' + */ + rtDW.dtc_state_error_model[32] = rtb_Compare_cc; + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataTypeConversion: '/Data Type Conversion2' + */ + rtDW.dtc_state_error_model[31] = rtb_Compare_kbl; + } else { + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.dtc_state_error_model[32] = 0U; + } + + /* End of Switch: '/Switch' */ + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.dtc_state_error_model[33] = rtb_Compare_jz; + + /* Switch: '/Switch' incorporates: + * DataTypeConversion: '/Data Type Conversion' + * Switch: '/Switch1' + */ + if (rtb_Compare_jz) { + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataTypeConversion: '/Data Type Conversion1' + */ + rtDW.dtc_state_error_model[34] = rtb_Compare_m1; + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataTypeConversion: '/Data Type Conversion2' + */ + rtDW.dtc_state_error_model[33] = rtb_Compare_hg; + } else { + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.dtc_state_error_model[34] = 0U; + } + + /* End of Switch: '/Switch' */ + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.dtc_state_error_model[35] = rtb_Compare_e3; + + /* Switch: '/Switch' incorporates: + * DataTypeConversion: '/Data Type Conversion' + * Switch: '/Switch1' + */ + if (rtb_Compare_e3) { + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataTypeConversion: '/Data Type Conversion1' + */ + rtDW.dtc_state_error_model[36] = rtb_Compare_k3; + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataTypeConversion: '/Data Type Conversion2' + */ + rtDW.dtc_state_error_model[35] = rtb_Compare_a; + } else { + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.dtc_state_error_model[36] = 0U; + } + + /* End of Switch: '/Switch' */ + + /* MATLAB Function: '/Write ' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write1' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('Duct1_R = %d * 0.1 C %d V\n',Sensor, int16(V)); */ + rtb_out_h0 = rtDW.ADC_Data_Model.Sensor_Rear_Duct1; + if (rtDW.ADC_Data_Model.Sensor_Rear_Duct1 > 32767) { + rtb_out_h0 = 32767U; + } + + printf("Duct1_R = %d * 0.1 C %d V\n", Duct1_R, (int16_t)rtb_out_h0); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write ' */ + + /* MATLAB Function: '/Write 1' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write2' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('Duct2_R = %d * 0.1 C %d V\n',Sensor, int16(V)); */ + rtb_out_h0 = rtDW.ADC_Data_Model.Sensor_Rear_Duct2; + if (rtDW.ADC_Data_Model.Sensor_Rear_Duct2 > 32767) { + rtb_out_h0 = 32767U; + } + + printf("Duct2_R = %d * 0.1 C %d V\n", Duct2_R, (int16_t)rtb_out_h0); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write 1' */ + + /* MATLAB Function: '/Write 2' incorporates: + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write3' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('Duct3_R = %d * 0.1 C %d V\n',Sensor, int16(V)); */ + rtb_out_h0 = rtDW.ADC_Data_Model.Sensor_Rear_Duct3; + if (rtDW.ADC_Data_Model.Sensor_Rear_Duct3 > 32767) { + rtb_out_h0 = 32767U; + } + + printf("Duct3_R = %d * 0.1 C %d V\n", Duct3_R, (int16_t)rtb_out_h0); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write 2' */ + + /* MATLAB Function: '/Write 3' incorporates: + * DataStoreRead: '/Data Store Read3' + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write4' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('Duct4_R = %d * 0.1 C %d V\n',Sensor, int16(V)); */ + rtb_out_h0 = rtDW.ADC_Data_Model.Sensor_Rear_Duct4; + if (rtDW.ADC_Data_Model.Sensor_Rear_Duct4 > 32767) { + rtb_out_h0 = 32767U; + } + + printf("Duct4_R = %d * 0.1 C %d V\n", Duct4_R, (int16_t)rtb_out_h0); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write 3' */ + + /* MATLAB Function: '/Write ERROR' incorporates: + * DataStoreRead: '/Data Store Read' + */ + /* : if(LOGGER) */ + if ((rtDW.LOGGER_ACP != 0.0) && rtb_Compare_gk) { + /* : if(Err) */ + /* : fprintf('CCU_Body_Err.CCU_DuctTempSenErrR_Stat = 0x1 (Failure), Sensor_Duct1_R = %f V\n',Sensor); */ + printf("CCU_Body_Err.CCU_DuctTempSenErrR_Stat = 0x1 (Failure), Sensor_Duct1_R = %f V\n", + rtb_Add_p4); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write ERROR' */ + + /* MATLAB Function: '/Write ERROR1' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + /* : if(LOGGER) */ + if ((rtDW.LOGGER_ACP != 0.0) && rtb_Compare_jl3) { + /* : if(Err) */ + /* : fprintf('CCU_Body_Err.CCU_DuctTempSenErrR_Stat = 0x1 (Failure), Sensor_Duct2_R = %f V\n',Sensor); */ + printf("CCU_Body_Err.CCU_DuctTempSenErrR_Stat = 0x1 (Failure), Sensor_Duct2_R = %f V\n", + rtb_Divide4); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write ERROR1' */ + + /* MATLAB Function: '/Write ERROR2' incorporates: + * DataStoreRead: '/Data Store Read2' + */ + /* : if(LOGGER) */ + if ((rtDW.LOGGER_ACP != 0.0) && rtb_Compare_jz) { + /* : if(Err) */ + /* : fprintf('CCU_Body_Err.CCU_DuctTempSenErrR_Stat = 0x1 (Failure), Sensor_Duct3_R = %f V\n',Sensor); */ + printf("CCU_Body_Err.CCU_DuctTempSenErrR_Stat = 0x1 (Failure), Sensor_Duct3_R = %f V\n", + rtb_Divide6); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write ERROR2' */ + + /* MATLAB Function: '/Write ERROR3' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + /* : if(LOGGER) */ + if ((rtDW.LOGGER_ACP != 0.0) && rtb_Compare_e3) { + /* : if(Err) */ + /* : fprintf('CCU_Body_Err.CCU_DuctTempSenErrR_Stat = 0x1 (Failure), Sensor_Duct4_R = %f V\n',Sensor); */ + printf("CCU_Body_Err.CCU_DuctTempSenErrR_Stat = 0x1 (Failure), Sensor_Duct4_R = %f V\n", + rtb_Divide8); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write ERROR3' */ + + /* Switch: '/Switch' incorporates: + * DataStoreRead: '/Data Store Read4' + * Logic: '/Logical Operator3' + * Logic: '/Logical Operator4' + * UnitDelay: '/Cond_prev_private ' + * UnitDelay: '/t_start_delay_private ' + */ + if (rtb_Compare_g2 && (!rtDW.Cond_prev_private_DSTATE_l)) { + rtDW.t_start_delay_private_DSTATE_o = rtDW.t_now; + } + + /* End of Switch: '/Switch' */ + + /* Switch: '/Switch' incorporates: + * DataStoreRead: '/Data Store Read4' + * Logic: '/Logical Operator3' + * Logic: '/Logical Operator4' + * UnitDelay: '/Cond_prev_private ' + * UnitDelay: '/t_start_delay_private ' + */ + if (rtb_Compare_fh && (!rtDW.Cond_prev_private_DSTATE_ja)) { + rtDW.t_start_delay_private_DSTATE_oy = rtDW.t_now; + } + + /* End of Switch: '/Switch' */ + + /* Switch: '/Switch' incorporates: + * DataStoreRead: '/Data Store Read4' + * Logic: '/Logical Operator3' + * Logic: '/Logical Operator4' + * UnitDelay: '/Cond_prev_private ' + * UnitDelay: '/t_start_delay_private ' + */ + if (rtb_Compare_ipf && (!rtDW.Cond_prev_private_DSTATE_g)) { + rtDW.t_start_delay_private_DSTATE_cd = rtDW.t_now; + } + + /* End of Switch: '/Switch' */ + + /* Switch: '/Switch' incorporates: + * DataStoreRead: '/Data Store Read4' + * Logic: '/Logical Operator3' + * Logic: '/Logical Operator4' + * UnitDelay: '/Cond_prev_private ' + * UnitDelay: '/t_start_delay_private ' + */ + if (rtb_Compare_pb && (!rtDW.Cond_prev_private_DSTATE_cd)) { + rtDW.t_start_delay_private_DSTATE_or = rtDW.t_now; + } + + /* End of Switch: '/Switch' */ + + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read3' + * DataStoreWrite: '/Data Store Write' + * DataStoreWrite: '/Data Store Write1' + * DataStoreWrite: '/Data Store Write3' + * DataStoreWrite: '/Data Store Write4' + * DataStoreWrite: '/Data Store Write5' + */ + rtDW.dbgCAN_dbg_Sen_Incar_model.dbg_Sen_Incar_MultMsg_Idx = 0U; + rtDW.dbgCAN_dbg_Sen_Incar_model.dbg_Sen_Incar_Raw_FL_ro = rtDW.Incar_FL; + rtDW.dbgCAN_dbg_Sen_Incar_model.dbg_Sen_Incar_FL_ro = rtDW.Incar_FL; + rtDW.dbgCAN_dbg_Sen_Incar_model.dbg_Sen_Incar_Raw_FR_ro = rtDW.Incar_FR; + rtDW.dbgCAN_dbg_Sen_Incar_model.dbg_Sen_Incar_FR_ro = rtDW.Incar_FR; + rtDW.dbgCAN_dbg_Sen_Incar_model.dbg_Sen_Incar_Raw_RL_ro = rtDW.Incar_RL; + rtDW.dbgCAN_dbg_Sen_Incar_model.dbg_Sen_Incar_RL_ro = rtDW.Incar_RL; + rtDW.dbgCAN_dbg_Sen_Incar_model.dbg_Sen_Incar_Raw_RR_ro = rtDW.Incar_RR; + rtDW.dbgCAN_dbg_Sen_Incar_model.dbg_Sen_Incar_RR_ro = rtDW.Incar_RR; + + /* If: '/If' incorporates: + * DataStoreRead: '/Data Store Read' + * If: '/If1' + * RelationalOperator: '/Relational Operator1' + * UnitDelay: '/Unit Delay' + */ + if (rtDW.UnitDelay_DSTATE_cbr < -9000) { + /* Outputs for IfAction SubSystem: '/ FL' incorporates: + * ActionPort: '/Action Port' + */ + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * DataStoreWrite: '/Data Store Write1' + */ + rtb_Add_p4 = rtDW.Incar_FL; + + /* End of Outputs for SubSystem: '/ FL' */ + } else { + /* Outputs for IfAction SubSystem: '/ FL ' incorporates: + * ActionPort: '/Action Port' + */ + if (rtDW.KEEP_RISING_FL_UNTIL_LIMIT > 0.0) { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* If: '/If1' incorporates: + * Abs: '/ABS(AMBraw - AMB)' + * DataStoreRead: '/Read Amb' + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write1' + * If: '/If' + * MATLAB Function: '/g_ausINCARRATE_RISING_DIFF_F[8]' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + */ + g_ausINCARRATE_RISING_DIFF_F8(&rtb_out_nc); + if (fabs((double)rtDW.Incar_FL - rtDW.Temp_FL_store) <= rtb_out_nc) { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.KEEP_RISING_FL_UNTIL_LIMIT = 0.0; + + /* SignalConversion generated from: '/out' incorporates: + * DataStoreRead: '/Data Store Read' + * MATLAB Function: '/ .' + */ + u_h(rtDW.LEVEL, &rtb_out_nc); + + /* End of Outputs for SubSystem: '/ ' */ + } else { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + u_lz(rtDW.LEVEL, &rtb_out_nc); + + /* End of Outputs for SubSystem: '/ ' */ + } + + /* End of Outputs for SubSystem: '/ ' */ + } else { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* If: '/If1' incorporates: + * Abs: '/ABS(AMBraw - AMB)' + * DataStoreRead: '/Read Amb' + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write1' + * If: '/If' + * MATLAB Function: '/INCARRATE_RISING_DIFF_F[7]' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + */ + INCARRATE_RISING_DIFF_F7(&rtb_out_nc); + if (fabs((double)rtDW.Incar_FL - rtDW.Temp_FL_store) > rtb_out_nc) { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.KEEP_RISING_FL_UNTIL_LIMIT = 1.0; + + /* SignalConversion generated from: '/out' incorporates: + * DataStoreRead: '/Data Store Read' + * MATLAB Function: '/ .' + */ + u_k(rtDW.LEVEL, &rtb_out_nc); + + /* End of Outputs for SubSystem: '/ ' */ + } else { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + u_f(rtDW.LEVEL, &rtb_out_nc); + + /* End of Outputs for SubSystem: '/ ' */ + } + + /* End of Outputs for SubSystem: '/ ' */ + } + + /* If: '/If1' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write1' + */ + if (rtDW.KEEP_FALLING_FL_UNTIL_LIMIT > 0.0) { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + u_c(rtDW.Incar_FL, rtDW.LEVEL, &rtb_out_h0, + &rtDW.KEEP_FALLING_FL_UNTIL_LIMIT, &rtDW.Temp_FL_store); + + /* End of Outputs for SubSystem: '/ ' */ + } else { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + u_l(rtDW.Incar_FL, rtDW.LEVEL, &rtb_out_h0, + &rtDW.KEEP_FALLING_FL_UNTIL_LIMIT, &rtDW.Temp_FL_store); + + /* End of Outputs for SubSystem: '/ ' */ + } + + /* End of If: '/If1' */ + + /* Switch: '/Switch1' incorporates: + * Abs: '/Abs' + * Constant: '/epsilon' + * DataStoreRead: '/Read Amb' + * DataStoreWrite: '/Data Store Write1' + * RelationalOperator: '/AMBraw > AMB' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + * Switch: '/Switch' + */ + if (fabs((double)rtDW.Incar_FL - rtDW.Temp_FL_store) <= 0.01) { + /* SignalConversion generated from: '/temp_out' */ + rtb_Add_p4 = rtDW.Temp_FL_store; + } else { + if (rtDW.Incar_FL > rtDW.Temp_FL_store) { + /* Switch: '/Switch' incorporates: + * DataTypeConversion: '/Data Type Conversion' + */ + rtb_FLU_tg_correct_aa = (int16_t)rtb_out_nc; + } else { + /* Switch: '/Switch' incorporates: + * DataTypeConversion: '/Data Type Conversion' + * UnaryMinus: '/Unary Minus' + */ + rtb_FLU_tg_correct_aa = (int16_t)-(int16_t)rtb_out_h0; + } + + /* SignalConversion generated from: '/temp_out' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read12' + * Product: '/Divide' + * Product: '/Product' + * Sum: '/Add' + * Sum: '/Subtract' + * Switch: '/Switch' + * UnitDelay: '/Unit Delay' + */ + rtb_Add_p4 = (double)(rtDW.t_now - rtDW.UnitDelay_DSTATE_o) / 60000.0 * + (double)rtb_FLU_tg_correct_aa + rtDW.Temp_FL_store; + } + + /* End of Switch: '/Switch1' */ + + /* Update for UnitDelay: '/Unit Delay' incorporates: + * DataStoreRead: '/Data Store Read12' + */ + rtDW.UnitDelay_DSTATE_o = rtDW.t_now; + + /* End of Outputs for SubSystem: '/ FL ' */ + } + + /* End of If: '/If' */ + + /* DataStoreWrite: '/Write new FL' */ + rtDW.Temp_FL_store = rtb_Add_p4; + + /* If: '/If' incorporates: + * DataStoreRead: '/Data Store Read' + * If: '/If1' + * RelationalOperator: '/Relational Operator1' + * UnitDelay: '/Unit Delay' + */ + if (rtDW.UnitDelay_DSTATE_j < -9000) { + /* Outputs for IfAction SubSystem: '/ FR' incorporates: + * ActionPort: '/Action Port' + */ + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * DataStoreWrite: '/Data Store Write3' + */ + rtb_Add_p4 = rtDW.Incar_FR; + + /* End of Outputs for SubSystem: '/ FR' */ + } else { + /* Outputs for IfAction SubSystem: '/ FR ' incorporates: + * ActionPort: '/Action Port' + */ + if (rtDW.KEEP_RISING_FR_UNTIL_LIMIT > 0.0) { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* If: '/If1' incorporates: + * Abs: '/ABS(AMBraw - AMB)' + * DataStoreRead: '/Read Amb' + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write3' + * If: '/If' + * MATLAB Function: '/g_ausINCARRATE_RISING_DIFF_F[8]' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + */ + g_ausINCARRATE_RISING_DIFF_F8(&rtb_out_nc); + if (fabs((double)rtDW.Incar_FR - rtDW.Temp_FR_store) <= rtb_out_nc) { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.KEEP_RISING_FR_UNTIL_LIMIT = 0.0; + + /* SignalConversion generated from: '/out' incorporates: + * DataStoreRead: '/Data Store Read' + * MATLAB Function: '/ .' + */ + u_h(rtDW.LEVEL, &rtb_out_nc); + + /* End of Outputs for SubSystem: '/ ' */ + } else { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + u_lz(rtDW.LEVEL, &rtb_out_nc); + + /* End of Outputs for SubSystem: '/ ' */ + } + + /* End of Outputs for SubSystem: '/ ' */ + } else { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* If: '/If1' incorporates: + * Abs: '/ABS(AMBraw - AMB)' + * DataStoreRead: '/Read Amb' + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write3' + * If: '/If' + * MATLAB Function: '/INCARRATE_RISING_DIFF_F[7]' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + */ + INCARRATE_RISING_DIFF_F7(&rtb_out_nc); + if (fabs((double)rtDW.Incar_FR - rtDW.Temp_FR_store) > rtb_out_nc) { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.KEEP_RISING_FR_UNTIL_LIMIT = 1.0; + + /* SignalConversion generated from: '/out' incorporates: + * DataStoreRead: '/Data Store Read' + * MATLAB Function: '/ .' + */ + u_k(rtDW.LEVEL, &rtb_out_nc); + + /* End of Outputs for SubSystem: '/ ' */ + } else { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + u_f(rtDW.LEVEL, &rtb_out_nc); + + /* End of Outputs for SubSystem: '/ ' */ + } + + /* End of Outputs for SubSystem: '/ ' */ + } + + /* If: '/If1' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write3' + */ + if (rtDW.KEEP_FALLING_FL_UNTIL_LIMIT > 0.0) { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + u_c(rtDW.Incar_FR, rtDW.LEVEL, &rtb_out_h0, + &rtDW.KEEP_FALLING_FL_UNTIL_LIMIT, &rtDW.Temp_FL_store); + + /* End of Outputs for SubSystem: '/ ' */ + } else { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + u_l(rtDW.Incar_FR, rtDW.LEVEL, &rtb_out_h0, + &rtDW.KEEP_FALLING_FL_UNTIL_LIMIT, &rtDW.Temp_FL_store); + + /* End of Outputs for SubSystem: '/ ' */ + } + + /* End of If: '/If1' */ + + /* Switch: '/Switch1' incorporates: + * Abs: '/Abs' + * Constant: '/epsilon' + * DataStoreRead: '/Read Amb' + * DataStoreWrite: '/Data Store Write3' + * RelationalOperator: '/AMBraw > AMB' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + * Switch: '/Switch' + */ + if (fabs((double)rtDW.Incar_FR - rtDW.Temp_FR_store) <= 0.01) { + /* SignalConversion generated from: '/temp_out' */ + rtb_Add_p4 = rtDW.Temp_FR_store; + } else { + if (rtDW.Incar_FR > rtDW.Temp_FR_store) { + /* Switch: '/Switch' incorporates: + * DataTypeConversion: '/Data Type Conversion' + */ + rtb_FLU_tg_correct_aa = (int16_t)rtb_out_nc; + } else { + /* Switch: '/Switch' incorporates: + * DataTypeConversion: '/Data Type Conversion' + * UnaryMinus: '/Unary Minus' + */ + rtb_FLU_tg_correct_aa = (int16_t)-(int16_t)rtb_out_h0; + } + + /* SignalConversion generated from: '/temp_out' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read12' + * Product: '/Divide' + * Product: '/Product' + * Sum: '/Add' + * Sum: '/Subtract' + * Switch: '/Switch' + * UnitDelay: '/Unit Delay' + */ + rtb_Add_p4 = (double)(rtDW.t_now - rtDW.UnitDelay_DSTATE_cr) / 60000.0 * + (double)rtb_FLU_tg_correct_aa + rtDW.Temp_FR_store; + } + + /* End of Switch: '/Switch1' */ + + /* Update for UnitDelay: '/Unit Delay' incorporates: + * DataStoreRead: '/Data Store Read12' + */ + rtDW.UnitDelay_DSTATE_cr = rtDW.t_now; + + /* End of Outputs for SubSystem: '/ FR ' */ + } + + /* End of If: '/If' */ + + /* DataStoreWrite: '/Write new FR' */ + rtDW.Temp_FR_store = rtb_Add_p4; + + /* If: '/If' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write4' + * If: '/If1' + * RelationalOperator: '/Relational Operator1' + * UnitDelay: '/Unit Delay' + */ + if (rtDW.UnitDelay_DSTATE_cs < -9000) { + /* Outputs for IfAction SubSystem: '/ RL' incorporates: + * ActionPort: '/Action Port' + */ + RL(rtDW.Incar_RL, &rtb_Add_p4); + + /* End of Outputs for SubSystem: '/ RL' */ + } else { + /* Outputs for IfAction SubSystem: '/ RL ' incorporates: + * ActionPort: '/Action Port' + */ + if (rtDW.KEEP_RISING_RL_UNTIL_LIMIT > 0.0) { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* If: '/If1' incorporates: + * Abs: '/ABS(AMBraw - AMB)' + * DataStoreRead: '/Read Amb' + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write4' + * If: '/If' + * MATLAB Function: '/g_ausINCARRATE_RISING_DIFF_R[8]' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + */ + g_ausINCARRATE_RISING_DIFF_R8(&rtb_out_nc); + if (fabs((double)rtDW.Incar_RL - rtDW.Temp_RL_store) <= rtb_out_nc) { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.KEEP_RISING_RL_UNTIL_LIMIT = 0.0; + + /* SignalConversion generated from: '/out' incorporates: + * DataStoreRead: '/Data Store Read' + * MATLAB Function: '/ .' + */ + u_m(rtDW.LEVEL, &rtb_out_nc); + + /* End of Outputs for SubSystem: '/ ' */ + } else { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + u_gq(rtDW.LEVEL, &rtb_out_nc); + + /* End of Outputs for SubSystem: '/ ' */ + } + + /* End of Outputs for SubSystem: '/ ' */ + } else { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* If: '/If1' incorporates: + * Abs: '/ABS(AMBraw - AMB)' + * DataStoreRead: '/Read Amb' + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write4' + * If: '/If' + * MATLAB Function: '/INCARRATE_RISING_DIFF_R[7]' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + */ + INCARRATE_RISING_DIFF_R7(&rtb_out_nc); + if (fabs((double)rtDW.Incar_RL - rtDW.Temp_RL_store) > rtb_out_nc) { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.KEEP_RISING_RL_UNTIL_LIMIT = 1.0; + + /* SignalConversion generated from: '/out' incorporates: + * DataStoreRead: '/Data Store Read' + * MATLAB Function: '/ .' + */ + u_o(rtDW.LEVEL, &rtb_out_nc); + + /* End of Outputs for SubSystem: '/ ' */ + } else { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + u_b3(rtDW.LEVEL, &rtb_out_nc); + + /* End of Outputs for SubSystem: '/ ' */ + } + + /* End of Outputs for SubSystem: '/ ' */ + } + + /* If: '/If1' incorporates: + * DataStoreRead: '/Data Store Read' + */ + if (rtDW.KEEP_FALLING_RL_UNTIL_LIMIT > 0.0) { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* MATLAB Function: '/AMBRATE_RISING_DIFF[8]' */ + AMBRATE_RISING_DIFF8(&rtb_out_h0); + + /* If: '/If' incorporates: + * Abs: '/ABS(AMBraw - AMB)' + * DataStoreRead: '/Read temp' + * DataStoreWrite: '/Data Store Write4' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + */ + if (fabs((double)rtDW.Incar_RL - rtDW.Temp_RL_store) <= rtb_out_h0) { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.KEEP_FALLING_RL_UNTIL_LIMIT = 0.0; + + /* SignalConversion generated from: '/out' incorporates: + * DataStoreRead: '/Data Store Read' + * MATLAB Function: '/ .' + */ + u_kk(rtDW.LEVEL, &rtb_out_h0); + + /* End of Outputs for SubSystem: '/ ' */ + } else { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* SignalConversion generated from: '/out' incorporates: + * DataStoreRead: '/Data Store Read' + */ + u_hr(rtDW.LEVEL, &rtb_out_h0); + + /* End of Outputs for SubSystem: '/ ' */ + } + + /* End of If: '/If' */ + /* End of Outputs for SubSystem: '/ ' */ + } else { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* MATLAB Function: '/AMBRATE_FALLING_DIFF[7]' */ + AMBRATE_FALLING_DIFF7(&rtb_out_h0); + + /* If: '/If' incorporates: + * Abs: '/ABS(AMBraw - AMB)' + * DataStoreRead: '/Read Amb' + * DataStoreWrite: '/Data Store Write4' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + */ + if (fabs((double)rtDW.Incar_RL - rtDW.Temp_RL_store) > rtb_out_h0) { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.KEEP_FALLING_RL_UNTIL_LIMIT = 1.0; + + /* SignalConversion generated from: '/rise per minute' incorporates: + * DataStoreRead: '/Data Store Read' + * MATLAB Function: '/ .' + */ + u_b(rtDW.LEVEL, &rtb_out_h0); + + /* End of Outputs for SubSystem: '/ ' */ + } else { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* SignalConversion generated from: '/rise per minute' incorporates: + * DataStoreRead: '/Data Store Read' + */ + u_g(rtDW.LEVEL, &rtb_out_h0); + + /* End of Outputs for SubSystem: '/ ' */ + } + + /* End of If: '/If' */ + /* End of Outputs for SubSystem: '/ ' */ + } + + /* End of If: '/If1' */ + + /* Switch: '/Switch1' incorporates: + * Abs: '/Abs' + * Constant: '/epsilon' + * DataStoreRead: '/Read Amb' + * DataStoreWrite: '/Data Store Write4' + * RelationalOperator: '/AMBraw > AMB' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + * Switch: '/Switch' + */ + if (fabs((double)rtDW.Incar_RL - rtDW.Temp_RL_store) <= 0.01) { + /* SignalConversion generated from: '/temp_out' */ + rtb_Add_p4 = rtDW.Temp_RL_store; + } else { + if (rtDW.Incar_RL > rtDW.Temp_RL_store) { + /* Switch: '/Switch' incorporates: + * DataTypeConversion: '/Data Type Conversion' + */ + rtb_FLU_tg_correct_aa = (int16_t)rtb_out_nc; + } else { + /* Switch: '/Switch' incorporates: + * DataTypeConversion: '/Data Type Conversion' + * UnaryMinus: '/Unary Minus' + */ + rtb_FLU_tg_correct_aa = (int16_t)-(int16_t)rtb_out_h0; + } + + /* SignalConversion generated from: '/temp_out' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read12' + * Product: '/Divide' + * Product: '/Product' + * Sum: '/Add' + * Sum: '/Subtract' + * Switch: '/Switch' + * UnitDelay: '/Unit Delay' + */ + rtb_Add_p4 = (double)(rtDW.t_now - rtDW.UnitDelay_DSTATE_l) / 60000.0 * + (double)rtb_FLU_tg_correct_aa + rtDW.Temp_RL_store; + } + + /* End of Switch: '/Switch1' */ + + /* Update for UnitDelay: '/Unit Delay' incorporates: + * DataStoreRead: '/Data Store Read12' + */ + rtDW.UnitDelay_DSTATE_l = rtDW.t_now; + + /* End of Outputs for SubSystem: '/ RL ' */ + } + + /* End of If: '/If' */ + + /* DataStoreWrite: '/Write new FL' */ + rtDW.Temp_RL_store = rtb_Add_p4; + + /* If: '/If' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write5' + * If: '/If1' + * RelationalOperator: '/Relational Operator1' + * UnitDelay: '/Unit Delay' + */ + if (rtDW.UnitDelay_DSTATE_k2 < -9000) { + /* Outputs for IfAction SubSystem: '/ RR' incorporates: + * ActionPort: '/Action Port' + */ + RL(rtDW.Incar_RR, &rtb_Add_p4); + + /* End of Outputs for SubSystem: '/ RR' */ + } else { + /* Outputs for IfAction SubSystem: '/ RR ' incorporates: + * ActionPort: '/Action Port' + */ + if (rtDW.KEEP_RISING_RR_UNTIL_LIMIT > 0.0) { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* If: '/If1' incorporates: + * Abs: '/ABS(AMBraw - AMB)' + * DataStoreRead: '/Read Amb' + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write5' + * If: '/If' + * MATLAB Function: '/g_ausINCARRATE_RISING_DIFF_R[8]' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + */ + g_ausINCARRATE_RISING_DIFF_R8(&rtb_out_nc); + if (fabs((double)rtDW.Incar_RR - rtDW.Temp_RR_store) <= rtb_out_nc) { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.KEEP_RISING_RR_UNTIL_LIMIT = 0.0; + + /* SignalConversion generated from: '/out' incorporates: + * DataStoreRead: '/Data Store Read' + * MATLAB Function: '/ .' + */ + u_m(rtDW.LEVEL, &rtb_out_nc); + + /* End of Outputs for SubSystem: '/ ' */ + } else { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + u_gq(rtDW.LEVEL, &rtb_out_nc); + + /* End of Outputs for SubSystem: '/ ' */ + } + + /* End of Outputs for SubSystem: '/ ' */ + } else { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* If: '/If1' incorporates: + * Abs: '/ABS(AMBraw - AMB)' + * DataStoreRead: '/Read Amb' + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write5' + * If: '/If' + * MATLAB Function: '/INCARRATE_RISING_DIFF_R[7]' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + */ + INCARRATE_RISING_DIFF_R7(&rtb_out_nc); + if (fabs((double)rtDW.Incar_RR - rtDW.Temp_RR_store) > rtb_out_nc) { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.KEEP_RISING_RR_UNTIL_LIMIT = 1.0; + + /* SignalConversion generated from: '/out' incorporates: + * DataStoreRead: '/Data Store Read' + * MATLAB Function: '/ .' + */ + u_o(rtDW.LEVEL, &rtb_out_nc); + + /* End of Outputs for SubSystem: '/ ' */ + } else { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + u_b3(rtDW.LEVEL, &rtb_out_nc); + + /* End of Outputs for SubSystem: '/ ' */ + } + + /* End of Outputs for SubSystem: '/ ' */ + } + + /* If: '/If1' incorporates: + * DataStoreRead: '/Data Store Read' + */ + if (rtDW.KEEP_FALLING_RR_UNTIL_LIMIT > 0.0) { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* MATLAB Function: '/AMBRATE_RISING_DIFF[8]' */ + AMBRATE_RISING_DIFF8(&rtb_out_h0); + + /* If: '/If' incorporates: + * Abs: '/ABS(AMBraw - AMB)' + * DataStoreRead: '/Read temp' + * DataStoreWrite: '/Data Store Write5' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + */ + if (fabs((double)rtDW.Incar_RR - rtDW.Temp_RR_store) <= rtb_out_h0) { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.KEEP_FALLING_RR_UNTIL_LIMIT = 0.0; + + /* SignalConversion generated from: '/out' incorporates: + * DataStoreRead: '/Data Store Read' + * MATLAB Function: '/ .' + */ + u_kk(rtDW.LEVEL, &rtb_out_h0); + + /* End of Outputs for SubSystem: '/ ' */ + } else { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* SignalConversion generated from: '/out' incorporates: + * DataStoreRead: '/Data Store Read' + */ + u_hr(rtDW.LEVEL, &rtb_out_h0); + + /* End of Outputs for SubSystem: '/ ' */ + } + + /* End of If: '/If' */ + /* End of Outputs for SubSystem: '/ ' */ + } else { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* MATLAB Function: '/AMBRATE_FALLING_DIFF[7]' */ + AMBRATE_FALLING_DIFF7(&rtb_out_h0); + + /* If: '/If' incorporates: + * Abs: '/ABS(AMBraw - AMB)' + * DataStoreRead: '/Read Amb' + * DataStoreWrite: '/Data Store Write5' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + */ + if (fabs((double)rtDW.Incar_RR - rtDW.Temp_RR_store) > rtb_out_h0) { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.KEEP_FALLING_RR_UNTIL_LIMIT = 1.0; + + /* SignalConversion generated from: '/rise per minute' incorporates: + * DataStoreRead: '/Data Store Read' + * MATLAB Function: '/ .' + */ + u_b(rtDW.LEVEL, &rtb_out_h0); + + /* End of Outputs for SubSystem: '/ ' */ + } else { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* SignalConversion generated from: '/rise per minute' incorporates: + * DataStoreRead: '/Data Store Read' + */ + u_g(rtDW.LEVEL, &rtb_out_h0); + + /* End of Outputs for SubSystem: '/ ' */ + } + + /* End of If: '/If' */ + /* End of Outputs for SubSystem: '/ ' */ + } + + /* End of If: '/If1' */ + + /* Switch: '/Switch1' incorporates: + * Abs: '/Abs' + * Constant: '/epsilon' + * DataStoreRead: '/Read Amb' + * DataStoreWrite: '/Data Store Write5' + * RelationalOperator: '/AMBraw > AMB' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + * Switch: '/Switch' + */ + if (fabs((double)rtDW.Incar_RR - rtDW.Temp_RR_store) <= 0.01) { + /* SignalConversion generated from: '/temp_out' */ + rtb_Add_p4 = rtDW.Temp_RR_store; + } else { + if (rtDW.Incar_RR > rtDW.Temp_RR_store) { + /* Switch: '/Switch' incorporates: + * DataTypeConversion: '/Data Type Conversion' + */ + rtb_FLU_tg_correct_aa = (int16_t)rtb_out_nc; + } else { + /* Switch: '/Switch' incorporates: + * DataTypeConversion: '/Data Type Conversion' + * UnaryMinus: '/Unary Minus' + */ + rtb_FLU_tg_correct_aa = (int16_t)-(int16_t)rtb_out_h0; + } + + /* SignalConversion generated from: '/temp_out' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read12' + * Product: '/Divide' + * Product: '/Product' + * Sum: '/Add' + * Sum: '/Subtract' + * Switch: '/Switch' + * UnitDelay: '/Unit Delay' + */ + rtb_Add_p4 = (double)(rtDW.t_now - rtDW.UnitDelay_DSTATE_m) / 60000.0 * + (double)rtb_FLU_tg_correct_aa + rtDW.Temp_RR_store; + } + + /* End of Switch: '/Switch1' */ + + /* Update for UnitDelay: '/Unit Delay' incorporates: + * DataStoreRead: '/Data Store Read12' + */ + rtDW.UnitDelay_DSTATE_m = rtDW.t_now; + + /* End of Outputs for SubSystem: '/ RR ' */ + } + + /* End of If: '/If' */ + + /* DataStoreWrite: '/Write new FL' */ + rtDW.Temp_RR_store = rtb_Add_p4; + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.dtc_state_error_model[2] = rtb_err; + + /* Switch: '/Switch' incorporates: + * DataTypeConversion: '/Data Type Conversion' + * Switch: '/Switch1' + */ + if (rtb_err) { + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataTypeConversion: '/Data Type Conversion1' + */ + rtDW.dtc_state_error_model[3] = rtb_Compare_hv; + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataTypeConversion: '/Data Type Conversion2' + */ + rtDW.dtc_state_error_model[2] = rtb_Compare_df; + } else { + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.dtc_state_error_model[3] = 0U; + } + + /* End of Switch: '/Switch' */ + + /* MATLAB Function: '/Write ERROR' incorporates: + * DataStoreRead: '/Data Store Read' + */ + /* : if(LOGGER) */ + if ((rtDW.LOGGER_ACP != 0.0) && rtb_err) { + /* : if(IncarFLErr) */ + /* : fprintf('CCU_Body_Err.CCU_IncarTempErrF_Stat = 0x1 (Failure), Sensor_Incar_Temp_FL = %f V\n',Sensor_Incar_Temp_FL); */ + printf("CCU_Body_Err.CCU_IncarTempErrF_Stat = 0x1 (Failure), Sensor_Incar_Temp_FL = %f V\n", + rtb_Add_be); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write ERROR' */ + + /* Switch: '/Switch' incorporates: + * DataStoreRead: '/Data Store Read4' + * Logic: '/Logical Operator3' + * Logic: '/Logical Operator4' + * UnitDelay: '/Cond_prev_private ' + * UnitDelay: '/t_start_delay_private ' + */ + if (rtb_Compare_i5 && (!rtDW.Cond_prev_private_DSTATE_k)) { + rtDW.t_start_delay_private_DSTATE = rtDW.t_now; + } + + /* End of Switch: '/Switch' */ + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.dtc_state_error_model[4] = rtb_LogicalOperator6; + + /* Switch: '/Switch' incorporates: + * DataTypeConversion: '/Data Type Conversion' + * Switch: '/Switch1' + */ + if (rtb_LogicalOperator6) { + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataTypeConversion: '/Data Type Conversion1' + */ + rtDW.dtc_state_error_model[5] = rtb_Compare_ls; + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataTypeConversion: '/Data Type Conversion2' + */ + rtDW.dtc_state_error_model[4] = rtb_Compare_ne; + } else { + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.dtc_state_error_model[5] = 0U; + } + + /* End of Switch: '/Switch' */ + + /* MATLAB Function: '/Write ERROR2' incorporates: + * DataStoreRead: '/Data Store Read2' + */ + /* : if(LOGGER) */ + if ((rtDW.LOGGER_ACP != 0.0) && rtb_LogicalOperator6) { + /* : if(IncarRLErr) */ + /* : fprintf('CCU_Body_Err.CCU_IncarTempErrR_Stat = 0x1 (Failure), Sensor_Incar_Temp_FR = %f V\n',Sensor_Incar_Temp_FR); */ + printf("CCU_Body_Err.CCU_IncarTempErrR_Stat = 0x1 (Failure), Sensor_Incar_Temp_FR = %f V\n", + index_start); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write ERROR2' */ + + /* Switch: '/Switch' incorporates: + * DataStoreRead: '/Data Store Read4' + * Logic: '/Logical Operator3' + * Logic: '/Logical Operator4' + * UnitDelay: '/Cond_prev_private ' + * UnitDelay: '/t_start_delay_private ' + */ + if (rtb_FailCond_jb && (!rtDW.Cond_prev_private_DSTATE_d)) { + rtDW.t_start_delay_private_DSTATE_i = rtDW.t_now; + } + + /* End of Switch: '/Switch' */ + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.dtc_state_error_model[6] = rtb_LogicalOperator3; + + /* Switch: '/Switch' incorporates: + * DataTypeConversion: '/Data Type Conversion' + * Switch: '/Switch1' + */ + if (rtb_LogicalOperator3) { + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataTypeConversion: '/Data Type Conversion1' + */ + rtDW.dtc_state_error_model[7] = rtb_Compare_kb; + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataTypeConversion: '/Data Type Conversion2' + */ + rtDW.dtc_state_error_model[6] = rtb_Compare_l; + } else { + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.dtc_state_error_model[7] = 0U; + } + + /* End of Switch: '/Switch' */ + + /* MATLAB Function: '/Write ERROR1' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + /* : if(LOGGER) */ + if ((rtDW.LOGGER_ACP != 0.0) && rtb_LogicalOperator3) { + /* : if(IncarRLErr) */ + /* : fprintf('CCU_Body_Err.CCU_IncarTempErrF_Stat = 0x1 (Failure), Sensor_Incar_Temp_RL = %f V\n',Sensor_Incar_Temp_RL); */ + printf("CCU_Body_Err.CCU_IncarTempErrF_Stat = 0x1 (Failure), Sensor_Incar_Temp_RL = %f V\n", + rtb_Divide3); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write ERROR1' */ + + /* Switch: '/Switch' incorporates: + * DataStoreRead: '/Data Store Read4' + * Logic: '/Logical Operator3' + * Logic: '/Logical Operator4' + * UnitDelay: '/Cond_prev_private ' + * UnitDelay: '/t_start_delay_private ' + */ + if (rtb_FailCond_e && (!rtDW.Cond_prev_private_DSTATE_hw)) { + rtDW.t_start_delay_private_DSTATE_k = rtDW.t_now; + } + + /* End of Switch: '/Switch' */ + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.dtc_state_error_model[8] = rtb_LogicalOperator8; + + /* Switch: '/Switch' incorporates: + * DataTypeConversion: '/Data Type Conversion' + * Switch: '/Switch1' + */ + if (rtb_LogicalOperator8) { + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataTypeConversion: '/Data Type Conversion1' + */ + rtDW.dtc_state_error_model[9] = rtb_Compare_g1; + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataTypeConversion: '/Data Type Conversion2' + */ + rtDW.dtc_state_error_model[8] = rtb_Compare_il; + } else { + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.dtc_state_error_model[9] = 0U; + } + + /* End of Switch: '/Switch' */ + + /* MATLAB Function: '/Write ERROR3' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + /* : if(LOGGER) */ + if ((rtDW.LOGGER_ACP != 0.0) && rtb_LogicalOperator8) { + /* : if(IncarRLErr) */ + /* : fprintf('CCU_Body_Err.CCU_IncarTempErrR_Stat = 0x1 (Failure), Sensor_Incar_Temp_RR = %f V\n',Sensor_Incar_Temp_RR); */ + printf("CCU_Body_Err.CCU_IncarTempErrR_Stat = 0x1 (Failure), Sensor_Incar_Temp_RR = %f V\n", + rtb_Divide7); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write ERROR3' */ + + /* Switch: '/Switch' incorporates: + * DataStoreRead: '/Data Store Read4' + * Logic: '/Logical Operator3' + * Logic: '/Logical Operator4' + * UnitDelay: '/Cond_prev_private ' + * UnitDelay: '/t_start_delay_private ' + */ + if (rtb_FailCond_l && (!rtDW.Cond_prev_private_DSTATE_i)) { + rtDW.t_start_delay_private_DSTATE_p = rtDW.t_now; + } + + /* End of Switch: '/Switch' */ + + /* MATLAB Function: '/Write IncarFL' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write1' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('IncarFL = %d * 0.1 C\n',IncarFL); */ + printf("IncarFL = %d * 0.1 C\n", rtDW.Incar_FL); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write IncarFL' */ + + /* MATLAB Function: '/Write IncarFR' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write3' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('IncarFR = %d * 0.1 C\n',IncarFR); */ + printf("IncarFR = %d * 0.1 C\n", rtDW.Incar_FR); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write IncarFR' */ + + /* MATLAB Function: '/Write IncarRL' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write4' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('IncarRL = %d * 0.1 C\n',IncarRL); */ + printf("IncarRL = %d * 0.1 C\n", rtDW.Incar_RL); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write IncarRL' */ + + /* MATLAB Function: '/Write IncarRR' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write5' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('IncarRR = %d * 0.1 C\n',IncarRR); */ + printf("IncarRR = %d * 0.1 C\n", rtDW.Incar_RR); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write IncarRR' */ + + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.LOGGER_ACP = 0.0; + + /* Product: '/Divide1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide' + */ + rtb_Add_be = (double)rtDW.ADC_Data_Model.BTS5120_2EKA_ShutoffValvePowerTXV1 / + 4095.0 * 5.0; + + /* MATLAB Function: '/Write' incorporates: + * Constant: '/Constant2' + * Constant: '/Constant3' + * DataStoreRead: '/Data Store Read' + * Product: '/Divide2' + * Product: '/Divide3' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('BTS5120_2EKA_ShutoffValvePowerTXV1 V = %f Iout = %f\n',U,I); */ + printf("BTS5120_2EKA_ShutoffValvePowerTXV1 V = %f Iout = %f\n", rtb_Add_be, + rtb_Add_be / 1200.0 * 550.0); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + + /* Product: '/Divide1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide' + */ + rtb_Add_be = (double)rtDW.ADC_Data_Model.BTS5120_2EKA_ShutoffValvePowerTXV2 / + 4095.0 * 5.0; + + /* MATLAB Function: '/Write' incorporates: + * Constant: '/Constant2' + * Constant: '/Constant3' + * DataStoreRead: '/Data Store Read' + * Product: '/Divide2' + * Product: '/Divide3' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('BTS5120_2EKA_ShutoffValvePowerTXV2 V = %f Iout = %f\n',U,I); */ + printf("BTS5120_2EKA_ShutoffValvePowerTXV2 V = %f Iout = %f\n", rtb_Add_be, + rtb_Add_be / 1200.0 * 550.0); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + + /* Product: '/Divide1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide' + */ + rtb_Add_be = (double)rtDW.ADC_Data_Model.BTS5180_2EKA_ChannelPTCPower1 / + 4095.0 * 5.0; + + /* MATLAB Function: '/Write' incorporates: + * Constant: '/Constant2' + * Constant: '/Constant3' + * DataStoreRead: '/Data Store Read' + * Product: '/Divide2' + * Product: '/Divide3' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('BTS5180_2EKA_ChannelPTCPower1 V = %f Iout = %f\n',U,I); */ + printf("BTS5180_2EKA_ChannelPTCPower1 V = %f Iout = %f\n", rtb_Add_be, + rtb_Add_be / 1200.0 * 550.0); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + + /* Product: '/Divide1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide' + */ + rtb_Add_be = (double)rtDW.ADC_Data_Model.BTS5180_2EKA_ChannelPTCPower2 / + 4095.0 * 5.0; + + /* MATLAB Function: '/Write' incorporates: + * Constant: '/Constant2' + * Constant: '/Constant3' + * DataStoreRead: '/Data Store Read' + * Product: '/Divide2' + * Product: '/Divide3' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('BTS5180_2EKA_ChannelPTCPower2 V = %f Iout = %f\n',U,I); */ + printf("BTS5180_2EKA_ChannelPTCPower2 V = %f Iout = %f\n", rtb_Add_be, + rtb_Add_be / 1200.0 * 550.0); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + + /* Product: '/Divide1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide' + */ + rtb_Add_be = (double)rtDW.ADC_Data_Model.BTS5180_2EKA_FrontIncarMotor / 4095.0 + * 5.0; + + /* MATLAB Function: '/Write' incorporates: + * Constant: '/Constant2' + * Constant: '/Constant3' + * DataStoreRead: '/Data Store Read' + * Product: '/Divide2' + * Product: '/Divide3' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('BTS5180_2EKA_FrontIncarMotor V = %f Iout = %f\n',U,I); */ + printf("BTS5180_2EKA_FrontIncarMotor V = %f Iout = %f\n", rtb_Add_be, + rtb_Add_be / 1200.0 * 550.0); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + + /* Product: '/Divide1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide' + */ + rtb_Add_be = (double)rtDW.ADC_Data_Model.BTS5180_2EKA_RearIncarMotor / 4095.0 * + 5.0; + + /* MATLAB Function: '/Write' incorporates: + * Constant: '/Constant2' + * Constant: '/Constant3' + * DataStoreRead: '/Data Store Read' + * Product: '/Divide2' + * Product: '/Divide3' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('BTS5180_2EKA_RearIncarMotor V = %f Iout = %f\n',U,I); */ + printf("BTS5180_2EKA_RearIncarMotor V = %f Iout = %f\n", rtb_Add_be, + rtb_Add_be / 1200.0 * 550.0); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + + /* Product: '/Divide1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide' + */ + rtb_Add_be = (double)rtDW.ADC_Data_Model.BTS5180_2EKA_ReservePowerSupply / + 4095.0 * 5.0; + + /* MATLAB Function: '/Write' incorporates: + * Constant: '/Constant2' + * Constant: '/Constant3' + * DataStoreRead: '/Data Store Read' + * Product: '/Divide2' + * Product: '/Divide3' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('BTS5180_2EKA_ReservePowerSupply V = %f Iout = %f\n',U,I); */ + printf("BTS5180_2EKA_ReservePowerSupply V = %f Iout = %f\n", rtb_Add_be, + rtb_Add_be / 1200.0 * 550.0); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + + /* Product: '/Divide1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide' + */ + rtb_Add_be = (double)rtDW.ADC_Data_Model.BTS5180_2EKA_ShutOFFValveFront / + 4095.0 * 5.0; + + /* MATLAB Function: '/Write' incorporates: + * Constant: '/Constant2' + * Constant: '/Constant3' + * DataStoreRead: '/Data Store Read' + * Product: '/Divide2' + * Product: '/Divide3' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('BTS5180_2EKA_ShutOFFValveFront V = %f Iout = %f\n',U,I); */ + printf("BTS5180_2EKA_ShutOFFValveFront V = %f Iout = %f\n", rtb_Add_be, + rtb_Add_be / 1200.0 * 550.0); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + + /* Product: '/Divide1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide' + */ + rtb_Add_be = (double)rtDW.ADC_Data_Model.BTS5180_2EKA_ShutOFFValveRear / + 4095.0 * 5.0; + + /* MATLAB Function: '/Write' incorporates: + * Constant: '/Constant2' + * Constant: '/Constant3' + * DataStoreRead: '/Data Store Read' + * Product: '/Divide2' + * Product: '/Divide3' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('BTS5180_2EKA_ShutOFFValveRear V = %f Iout = %f\n',U,I); */ + printf("BTS5180_2EKA_ShutOFFValveRear V = %f Iout = %f\n", rtb_Add_be, + rtb_Add_be / 1200.0 * 550.0); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + + /* Product: '/Divide1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide' + */ + rtb_Add_be = (double)rtDW.ADC_Data_Model.BTS5180_2EKA_TwoWayValve / 4095.0 * + 5.0; + + /* MATLAB Function: '/Write' incorporates: + * Constant: '/Constant2' + * Constant: '/Constant3' + * DataStoreRead: '/Data Store Read' + * Product: '/Divide2' + * Product: '/Divide3' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('BTS5180_2EKA_TwoWayValve V = %f Iout = %f\n',U,I); */ + printf("BTS5180_2EKA_TwoWayValve V = %f Iout = %f\n", rtb_Add_be, rtb_Add_be + / 1200.0 * 550.0); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + + /* MATLAB Function: '/Write' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide' + * Product: '/Divide1' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('IGN_ANS = %f V\n',data); */ + printf("IGN_ANS = %f V\n", (double)rtDW.ADC_Data_Model.IGN_ANS / 4095.0 * + 27.75); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + + /* MATLAB Function: '/Write' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide' + * Product: '/Divide1' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('PBATT_CHECK V = %f\n',U); */ + printf("PBATT_CHECK V = %f\n", (double)rtDW.ADC_Data_Model.PBATT_CHECK / + 4095.0 * 33.4375); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + + /* MATLAB Function: '/Write' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide' + * Product: '/Divide1' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('Pressure_DIAG V = %f\n',U); */ + printf("Pressure_DIAG V = %f\n", (double)rtDW.ADC_Data_Model.Pressure_DIAG / + 4095.0 * 6.0638); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + + /* MATLAB Function: '/Write' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide' + * Product: '/Divide1' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('Reserve_Sensor_Duct_Temp_1 V = %f\n',U); */ + printf("Reserve_Sensor_Duct_Temp_1 V = %f\n", (double) + rtDW.ADC_Data_Model.Reserve_Sensor_Duct_Temp_1 / 4095.0 * 5.0); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + + /* MATLAB Function: '/Write' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide' + * Product: '/Divide1' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('Reserve_Sensor_Duct_Temp_2 V = %f\n',U); */ + printf("Reserve_Sensor_Duct_Temp_2 V = %f\n", (double) + rtDW.ADC_Data_Model.Reserve_Sensor_Duct_Temp_2 / 4095.0 * 5.0); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + + /* MATLAB Function: '/Write' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide' + * Product: '/Divide1' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('Sensor_Front_Duct5 V = %f\n',U); */ + printf("Sensor_Front_Duct5 V = %f\n", (double) + rtDW.ADC_Data_Model.Sensor_Rear_Duct5 / 4095.0 * 5.0); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + + /* MATLAB Function: '/Write' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide' + * Product: '/Divide1' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('Sensor_Front_Duct V = %f\n',U); */ + printf("Sensor_Front_Duct V = %f\n", (double) + rtDW.ADC_Data_Model.Sensor_Rear_Duct6 / 4095.0 * 5.0); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + + /* MATLAB Function: '/Write' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide' + * Product: '/Divide1' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('VN7008AJ_DIAG_FrontLINActuatorPowerDriverAB V = %f\n',U); */ + printf("VN7008AJ_DIAG_FrontLINActuatorPowerDriverAB V = %f\n", (double) + rtDW.ADC_Data_Model.VN7008AJ_DIAG_FrontLINActuatorPowerDriverAB / + 4095.0 * 17.5); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + + /* MATLAB Function: '/Write' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide' + * Product: '/Divide1' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('VN7008AJ_DIAG_RearLINActuatorPowerDriverC V = %f\n',U); */ + printf("VN7008AJ_DIAG_RearLINActuatorPowerDriverC V = %f\n", (double) + rtDW.ADC_Data_Model.VN7008AJ_DIAG_RearLINActuatorPowerDriverC / + 4095.0 * 17.5); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + + /* Product: '/Divide1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide' + */ + rtb_Add_be = (double) + rtDW.ADC_Data_Model.VN7008AJ_FrontLINActuatorPowerDriverAB / 4095.0 * 5.0; + + /* MATLAB Function: '/Write' incorporates: + * Constant: '/Constant2' + * Constant: '/Constant3' + * DataStoreRead: '/Data Store Read' + * Product: '/Divide2' + * Product: '/Divide3' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('VN7008AJ_FrontLINActuatorPowerDriverAB V = %f Iout = %f\n',U,I); */ + printf("VN7008AJ_FrontLINActuatorPowerDriverAB V = %f Iout = %f\n", + rtb_Add_be, rtb_Add_be / 2490.0 * 5890.0); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + + /* Product: '/Divide1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read1' + * Product: '/Divide' + */ + rtb_Add_be = (double)rtDW.ADC_Data_Model.VN7008AJ_RearLINActuatorPowerDriverC / + 4095.0 * 5.0; + + /* MATLAB Function: '/Write' incorporates: + * Constant: '/Constant2' + * Constant: '/Constant3' + * DataStoreRead: '/Data Store Read' + * Product: '/Divide2' + * Product: '/Divide3' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('VN7008AJ_RearLINActuatorPowerDriverC V = %f Iout = %f\n',U,I); */ + printf("VN7008AJ_RearLINActuatorPowerDriverC V = %f Iout = %f\n", rtb_Add_be, + rtb_Add_be / 2490.0 * 5890.0); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + + /* MATLAB Function: '/Write' incorporates: + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read3' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('ST_ReservePower = %u \n',data); */ + printf("ST_ReservePower = %u \n", rtDW.ADC_Key_Data_Model.ST_ReservePower); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + + /* MATLAB Function: '/Write1' incorporates: + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read3' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('ST_BATTChiller = %u \n',data); */ + printf("ST_BATTChiller = %u \n", rtDW.ADC_Key_Data_Model.ST_BATTChiller); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write1' */ + + /* MATLAB Function: '/Write2' incorporates: + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read3' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('EmergencyAirCleanSwitch = %u \n',data); */ + printf("EmergencyAirCleanSwitch = %u \n", + rtDW.ADC_Key_Data_Model.EmergencyAirCleanSwitch); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write2' */ + + /* MATLAB Function: '/Write3' incorporates: + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read3' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('FireExtinguishSwitch = %u \n',data); */ + printf("FireExtinguishSwitch = %u \n", + rtDW.ADC_Key_Data_Model.FireExtinguishSwitch); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write3' */ + + /* MATLAB Function: '/Write4' incorporates: + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read3' + */ + /* : if(LOGGER) */ + if (rtDW.LOGGER_ACP != 0.0) { + /* : fprintf('Ign_Wakeup = %u \n',data); */ + printf("Ign_Wakeup = %u \n", rtDW.ADC_Key_Data_Model.Ign_Wakeup); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write4' */ + + /* Chart: '/Zone_Climate_Logic_Auto_FL2' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read8' + */ + Zone_Climate_Logic_Auto_FL2(0.0, rtDW.CCU_FACE_RL, rtDW.CCU_FOOT_RL, + rtDW.CCU_MODE_RL, rtDW.CCU_AC_REAR, &rtB.out_def_i, &rtB.out_face_c, + &rtB.out_foot_f, &rtB.out_auto_h, &rtB.out_ac_ed, + &rtDW.sf_Zone_Climate_Logic_Auto_FL2); + + /* DataStoreWrite: '/Data Store Write1' */ + rtDW.CCU_FACE_RL = rtB.out_face_c; + + /* DataStoreWrite: '/Data Store Write2' */ + rtDW.CCU_FOOT_RL = rtB.out_foot_f; + + /* DataStoreWrite: '/Data Store Write3' */ + rtDW.CCU_MODE_RL = rtB.out_auto_h; + + /* Chart: '/Zone_Climate_Logic_Auto_FL3' incorporates: + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read3' + * DataStoreRead: '/Data Store Read4' + * DataStoreRead: '/Data Store Read5' + * DataStoreRead: '/Data Store Read9' + */ + Zone_Climate_Logic_Auto_FL2(0.0, rtDW.CCU_FACE_RR, rtDW.CCU_FOOT_RR, + rtDW.CCU_MODE_RR, rtDW.CCU_AC_REAR, &rtB.out_def_n, &rtB.out_face_f, + &rtB.out_foot_p, &rtB.out_auto_e, &rtB.out_ac_e, + &rtDW.sf_Zone_Climate_Logic_Auto_FL3); + + /* DataStoreWrite: '/Data Store Write4' */ + rtDW.CCU_FACE_RR = rtB.out_face_f; + + /* DataStoreWrite: '/Data Store Write5' */ + rtDW.CCU_FOOT_RR = rtB.out_foot_p; + + /* DataStoreWrite: '/Data Store Write6' */ + rtDW.CCU_MODE_RR = rtB.out_auto_e; + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * DataStoreWrite: '/Data Store Write7' + * Logic: '/Logical Operator1' + */ + rtDW.CCU_AC_REAR = (uint8_t)((rtB.out_ac_ed != 0.0) || (rtB.out_ac_e != 0.0)); + + /* Chart: '/Zone_Climate_Logic_Auto_FL1' incorporates: + * DataStoreRead: '/Data Store Read38' + * DataStoreRead: '/Data Store Read39' + * DataStoreRead: '/Data Store Read40' + * DataStoreRead: '/Data Store Read41' + * DataStoreRead: '/Data Store Read6' + */ + if (rtDW.is_active_c681_HVAC_model == 0U) { + rtDW.is_active_c681_HVAC_model = 1U; + rtDW.is_c681_HVAC_model = IN_MANUAL_MODE_k; + + /* : out_def = 0; */ + rtB.out_def_m = 0U; + + /* : out_face = 1; */ + rtB.out_face_m = 1U; + + /* : out_foot = 1; */ + rtB.out_foot_ps = 1U; + + /* : mem_def = 0; */ + /* : mem_face = 0; */ + /* : mem_foot = 0; */ + rtDW.is_DEF_SUB_i = IN_Def_Off_p; + rtDW.is_FACE_SUB_o = IN_Face_Off_i; + rtDW.is_FOOT_SUB_f = IN_Foot_Off_n; + rtDW.is_AC_SUB_co = IN_AC_Off_m; + } else if (rtDW.is_c681_HVAC_model == IN_AUTO_MODE_p) { + /* : sf_internal_predicateOutput = btn_auto == 0 || btn_def == 1 || btn_face == 1 || btn_foot == 1; */ + if ((rtDW.CCU_MODE_FL == 0) || (rtDW.CCU_DEF_FL == 1) || (rtDW.CCU_FACE_FL == + 1) || (rtDW.CCU_FOOT_FL == 1)) { + /* : out_auto=0; */ + rtB.out_auto_hx = 0U; + rtDW.is_AC_SUB_c = IN_NO_ACTIVE_CHILD_c; + rtDW.is_c681_HVAC_model = IN_MANUAL_MODE_k; + + /* : out_def = 0; */ + rtB.out_def_m = 0U; + + /* : out_face = 1; */ + rtB.out_face_m = 1U; + + /* : out_foot = 1; */ + rtB.out_foot_ps = 1U; + + /* : mem_def = 0; */ + /* : mem_face = 0; */ + /* : mem_foot = 0; */ + rtDW.is_DEF_SUB_i = IN_Def_Off_p; + rtDW.is_FACE_SUB_o = IN_Face_Off_i; + rtDW.is_FOOT_SUB_f = IN_Foot_Off_n; + rtDW.is_AC_SUB_co = IN_AC_Off_m; + } else if (rtDW.is_AC_SUB_c == IN_AC_Off_m) { + /* : sf_internal_predicateOutput = btn_ac == 1; */ + if (rtDW.CCU_AC_FRONT == 1) { + /* : out_ac=1 */ + rtDW.is_AC_SUB_c = IN_AC_On_d; + + /* : out_ac = 1; */ + rtB.out_ac_m = 1.0; + } + + /* case IN_AC_On: */ + /* : sf_internal_predicateOutput = btn_ac == 0; */ + } else if (rtDW.CCU_AC_FRONT == 0) { + /* : out_ac=0 */ + rtB.out_ac_m = 0.0; + rtDW.is_AC_SUB_c = IN_AC_Off_m; + } + + /* case IN_MANUAL_MODE: */ + /* : sf_internal_predicateOutput = btn_auto == 1 || (out_def == 0 && out_face == 0 && out_foot == 0); */ + } else if ((rtDW.CCU_MODE_FL == 1) || ((rtB.out_def_m == 0) && (rtB.out_face_m + == 0) && (rtB.out_foot_ps == 0))) { + /* : out_auto=1; */ + rtDW.is_AC_SUB_co = IN_NO_ACTIVE_CHILD_c; + rtDW.is_FOOT_SUB_f = IN_NO_ACTIVE_CHILD_c; + rtDW.is_FACE_SUB_o = IN_NO_ACTIVE_CHILD_c; + rtDW.is_DEF_SUB_i = IN_NO_ACTIVE_CHILD_c; + rtDW.is_c681_HVAC_model = IN_AUTO_MODE_p; + + /* : out_auto = 1; */ + rtB.out_auto_hx = 1U; + + /* : out_def = 0; */ + rtB.out_def_m = 0U; + + /* : out_face = 0; */ + rtB.out_face_m = 0U; + + /* : out_foot = 0; */ + rtB.out_foot_ps = 0U; + rtDW.is_AC_SUB_c = IN_AC_On_d; + + /* : out_ac = 1; */ + rtB.out_ac_m = 1.0; + } else { + if (rtDW.is_DEF_SUB_i == IN_Def_Off_p) { + /* : sf_internal_predicateOutput = btn_def == 1; */ + if (rtDW.CCU_DEF_FL == 1) { + /* : out_def=1 */ + rtB.out_def_m = 1U; + rtDW.is_DEF_SUB_i = IN_Def_On_c; + } + + /* case IN_Def_On: */ + /* : sf_internal_predicateOutput = btn_def == 0; */ + } else if (rtDW.CCU_DEF_FL == 0) { + /* : out_def=0 */ + rtB.out_def_m = 0U; + rtDW.is_DEF_SUB_i = IN_Def_Off_p; + } + + if (rtDW.is_FACE_SUB_o == IN_Face_Off_i) { + /* : sf_internal_predicateOutput = btn_face == 1; */ + if (rtDW.CCU_FACE_FL == 1) { + /* : out_face=1 */ + rtB.out_face_m = 1U; + rtDW.is_FACE_SUB_o = IN_Face_On_k; + } + + /* case IN_Face_On: */ + /* : sf_internal_predicateOutput = btn_face == 0; */ + } else if (rtDW.CCU_FACE_FL == 0) { + /* : out_face=0 */ + rtB.out_face_m = 0U; + rtDW.is_FACE_SUB_o = IN_Face_Off_i; + } + + if (rtDW.is_FOOT_SUB_f == IN_Foot_Off_n) { + /* : sf_internal_predicateOutput = btn_foot == 1; */ + if (rtDW.CCU_FOOT_FL == 1) { + /* : out_foot=1 */ + rtB.out_foot_ps = 1U; + rtDW.is_FOOT_SUB_f = IN_Foot_On_m; + } + + /* case IN_Foot_On: */ + /* : sf_internal_predicateOutput = btn_foot == 0; */ + } else if (rtDW.CCU_FOOT_FL == 0) { + /* : out_foot=0 */ + rtB.out_foot_ps = 0U; + rtDW.is_FOOT_SUB_f = IN_Foot_Off_n; + } + + if (rtDW.is_AC_SUB_co == IN_AC_Off_m) { + /* : sf_internal_predicateOutput = btn_ac == 1; */ + if (rtDW.CCU_AC_FRONT == 1) { + /* : out_ac=1 */ + rtB.out_ac_m = 1.0; + rtDW.is_AC_SUB_co = IN_AC_On_d; + } + + /* case IN_AC_On: */ + /* : sf_internal_predicateOutput = btn_ac == 0; */ + } else if (rtDW.CCU_AC_FRONT == 0) { + /* : out_ac=0 */ + rtB.out_ac_m = 0.0; + rtDW.is_AC_SUB_co = IN_AC_Off_m; + } + } + + /* End of Chart: '/Zone_Climate_Logic_Auto_FL1' */ + + /* Chart: '/Zone_Climate_Logic_Auto_FL4' incorporates: + * DataStoreRead: '/Data Store Read42' + * DataStoreRead: '/Data Store Read61' + * DataStoreRead: '/Data Store Read62' + * DataStoreRead: '/Data Store Read63' + * DataStoreRead: '/Data Store Read7' + */ + if (rtDW.is_active_c777_HVAC_model == 0U) { + rtDW.is_active_c777_HVAC_model = 1U; + rtDW.is_c777_HVAC_model = IN_MANUAL_MODE_k; + + /* : out_def = 0; */ + rtB.out_def = 0U; + + /* : out_face = 1; */ + rtB.out_face = 1U; + + /* : out_foot = 1; */ + rtB.out_foot = 1U; + + /* : mem_def = 0; */ + /* : mem_face = 0; */ + /* : mem_foot = 0; */ + rtDW.is_DEF_SUB = IN_Def_Off_p; + rtDW.is_FACE_SUB = IN_Face_Off_i; + rtDW.is_FOOT_SUB = IN_Foot_Off_n; + rtDW.is_AC_SUB_a = IN_AC_Off_m; + } else if (rtDW.is_c777_HVAC_model == IN_AUTO_MODE_p) { + /* : sf_internal_predicateOutput = btn_auto == 0 || btn_def == 1 || btn_face == 1 || btn_foot == 1; */ + if ((rtDW.CCU_MODE_FR == 0) || (rtDW.CCU_DEF_FR == 1) || (rtDW.CCU_FACE_FR == + 1) || (rtDW.CCU_FOOT_FR == 1)) { + /* : out_auto=0; */ + rtB.out_auto = 0U; + rtDW.is_AC_SUB = IN_NO_ACTIVE_CHILD_c; + rtDW.is_c777_HVAC_model = IN_MANUAL_MODE_k; + + /* : out_def = 0; */ + rtB.out_def = 0U; + + /* : out_face = 1; */ + rtB.out_face = 1U; + + /* : out_foot = 1; */ + rtB.out_foot = 1U; + + /* : mem_def = 0; */ + /* : mem_face = 0; */ + /* : mem_foot = 0; */ + rtDW.is_DEF_SUB = IN_Def_Off_p; + rtDW.is_FACE_SUB = IN_Face_Off_i; + rtDW.is_FOOT_SUB = IN_Foot_Off_n; + rtDW.is_AC_SUB_a = IN_AC_Off_m; + } else if (rtDW.is_AC_SUB == IN_AC_Off_m) { + /* : sf_internal_predicateOutput = btn_ac == 1; */ + if (rtDW.CCU_AC_FRONT == 1) { + /* : out_ac=1 */ + rtDW.is_AC_SUB = IN_AC_On_d; + + /* : out_ac = 1; */ + rtB.out_ac = 1.0; + } + + /* case IN_AC_On: */ + /* : sf_internal_predicateOutput = btn_ac == 0; */ + } else if (rtDW.CCU_AC_FRONT == 0) { + /* : out_ac=0 */ + rtB.out_ac = 0.0; + rtDW.is_AC_SUB = IN_AC_Off_m; + } + + /* case IN_MANUAL_MODE: */ + /* : sf_internal_predicateOutput = btn_auto == 1 || (out_def == 0 && out_face == 0 && out_foot == 0); */ + } else if ((rtDW.CCU_MODE_FR == 1) || ((rtB.out_def == 0) && (rtB.out_face == + 0) && (rtB.out_foot == 0))) { + /* : out_auto=1; */ + rtDW.is_AC_SUB_a = IN_NO_ACTIVE_CHILD_c; + rtDW.is_FOOT_SUB = IN_NO_ACTIVE_CHILD_c; + rtDW.is_FACE_SUB = IN_NO_ACTIVE_CHILD_c; + rtDW.is_DEF_SUB = IN_NO_ACTIVE_CHILD_c; + rtDW.is_c777_HVAC_model = IN_AUTO_MODE_p; + + /* : out_auto = 1; */ + rtB.out_auto = 1U; + + /* : out_def = 0; */ + rtB.out_def = 0U; + + /* : out_face = 0; */ + rtB.out_face = 0U; + + /* : out_foot = 0; */ + rtB.out_foot = 0U; + rtDW.is_AC_SUB = IN_AC_On_d; + + /* : out_ac = 1; */ + rtB.out_ac = 1.0; + } else { + if (rtDW.is_DEF_SUB == IN_Def_Off_p) { + /* : sf_internal_predicateOutput = btn_def == 1; */ + if (rtDW.CCU_DEF_FR == 1) { + /* : out_def=1 */ + rtB.out_def = 1U; + rtDW.is_DEF_SUB = IN_Def_On_c; + } + + /* case IN_Def_On: */ + /* : sf_internal_predicateOutput = btn_def == 0; */ + } else if (rtDW.CCU_DEF_FR == 0) { + /* : out_def=0 */ + rtB.out_def = 0U; + rtDW.is_DEF_SUB = IN_Def_Off_p; + } + + if (rtDW.is_FACE_SUB == IN_Face_Off_i) { + /* : sf_internal_predicateOutput = btn_face == 1; */ + if (rtDW.CCU_FACE_FR == 1) { + /* : out_face=1 */ + rtB.out_face = 1U; + rtDW.is_FACE_SUB = IN_Face_On_k; + } + + /* case IN_Face_On: */ + /* : sf_internal_predicateOutput = btn_face == 0; */ + } else if (rtDW.CCU_FACE_FR == 0) { + /* : out_face=0 */ + rtB.out_face = 0U; + rtDW.is_FACE_SUB = IN_Face_Off_i; + } + + if (rtDW.is_FOOT_SUB == IN_Foot_Off_n) { + /* : sf_internal_predicateOutput = btn_foot == 1; */ + if (rtDW.CCU_FOOT_FR == 1) { + /* : out_foot=1 */ + rtB.out_foot = 1U; + rtDW.is_FOOT_SUB = IN_Foot_On_m; + } + + /* case IN_Foot_On: */ + /* : sf_internal_predicateOutput = btn_foot == 0; */ + } else if (rtDW.CCU_FOOT_FR == 0) { + /* : out_foot=0 */ + rtB.out_foot = 0U; + rtDW.is_FOOT_SUB = IN_Foot_Off_n; + } + + if (rtDW.is_AC_SUB_a == IN_AC_Off_m) { + /* : sf_internal_predicateOutput = btn_ac == 1; */ + if (rtDW.CCU_AC_FRONT == 1) { + /* : out_ac=1 */ + rtB.out_ac = 1.0; + rtDW.is_AC_SUB_a = IN_AC_On_d; + } + + /* case IN_AC_On: */ + /* : sf_internal_predicateOutput = btn_ac == 0; */ + } else if (rtDW.CCU_AC_FRONT == 0) { + /* : out_ac=0 */ + rtB.out_ac = 0.0; + rtDW.is_AC_SUB_a = IN_AC_Off_m; + } + } + + /* End of Chart: '/Zone_Climate_Logic_Auto_FL4' */ + + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * DataStoreWrite: '/Data Store Write' + * Logic: '/Logical Operator' + */ + rtDW.CCU_AC_FRONT = (uint8_t)((rtB.out_ac_m != 0.0) || (rtB.out_ac != 0.0)); + + /* DataStoreWrite: '/Data Store Write28' */ + rtDW.CCU_FACE_FL = rtB.out_face_m; + + /* DataStoreWrite: '/Data Store Write29' */ + rtDW.CCU_FOOT_FL = rtB.out_foot_ps; + + /* DataStoreWrite: '/Data Store Write30' */ + rtDW.CCU_MODE_FL = rtB.out_auto_hx; + + /* DataStoreWrite: '/Data Store Write32' */ + rtDW.CCU_FACE_FR = rtB.out_face; + + /* DataStoreWrite: '/Data Store Write33' */ + rtDW.CCU_FOOT_FR = rtB.out_foot; + + /* DataStoreWrite: '/Data Store Write34' */ + rtDW.CCU_MODE_FR = rtB.out_auto; + + /* DataStoreWrite: '/Data Store Write35' */ + rtDW.CCU_DEF_FR = rtB.out_def; + + /* DataStoreWrite: '/Data Store Write37' */ + rtDW.CCU_DEF_FL = rtB.out_def_m; + + /* Outputs for Enabled SubSystem: '/Determine directions RL' incorporates: + * EnablePort: '/Enable' + */ + /* RelationalOperator: '/FixPt Relational Operator' incorporates: + * UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + if (rtB.out_auto_h < rtDW.DelayInput1_DSTATE) { + /* MATLAB Function: '/direction for REAR index mode' incorporates: + * DataStoreRead: '/Data Store Read' + */ + directionforREARindexmode(rtDW.Index_mode_RL_auto, &rtb_Saturation_m0[0]); + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.CCU_FACE_RL = (uint8_t)rtb_Saturation_m0[1]; + + /* DataStoreWrite: '/Data Store Write3' incorporates: + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.CCU_FOOT_RL = (uint8_t)rtb_Saturation_m0[2]; + + /* DataStoreWrite: '/Data Store Write4' incorporates: + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.Index_mode_RL_manual = (uint8_t)rtb_Saturation_m0[3]; + + /* MATLAB Function: '/AF REAR VENT AUTO' */ + AFREARVENTAUTO(rtb_out_ixa); + + /* MATLAB Function: '/AF REAR Bi Level' */ + AFREARBiLevel(rtb_out_f); + + /* MATLAB Function: '/AF REAR Foot' */ + AFREARFoot(rtb_out_ju); + + /* MATLAB Function: '/AF REAR VENT AUTO1' */ + AFREARVENTAUTO(rtb_out_k1); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * DataStoreRead: '/Data Store Read' + */ + switch (rtDW.Index_mode_RL_auto) { + case 120: + case 150: + case 170: + for (i = 0; i < 8; i++) { + rtb_out_k1[i] = rtb_out_ixa[i]; + } + break; + + case 130: + case 160: + case 180: + for (i = 0; i < 8; i++) { + rtb_out_k1[i] = rtb_out_f[i]; + } + break; + + case 140: + for (i = 0; i < 8; i++) { + rtb_out_k1[i] = rtb_out_ju[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch' */ + + /* MATLAB Function: '/closest speed' incorporates: + * DataStoreRead: '/Data Store Read2' + */ + closestspeed(rtb_out_k1, rtb_Saturation2_a, &rtb_DataTypeConversion1_lq); + + /* DataStoreWrite: '/Data Store Write5' */ + rtDW.CCU_BLOWERS_RL = rtb_DataTypeConversion1_lq; + } + + /* End of RelationalOperator: '/FixPt Relational Operator' */ + /* End of Outputs for SubSystem: '/Determine directions RL' */ + + /* Outputs for Enabled SubSystem: '/Determine directions RR' incorporates: + * EnablePort: '/Enable' + */ + /* RelationalOperator: '/FixPt Relational Operator' incorporates: + * UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + if (rtB.out_auto_e < rtDW.DelayInput1_DSTATE_e) { + /* MATLAB Function: '/direction for REAR index mode1' incorporates: + * DataStoreRead: '/Data Store Read' + */ + directionforREARindexmode(rtDW.Index_mode_RR_auto, &rtb_Saturation_m0[0]); + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.CCU_FACE_RR = (uint8_t)rtb_Saturation_m0[1]; + + /* DataStoreWrite: '/Data Store Write3' incorporates: + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.CCU_FOOT_RR = (uint8_t)rtb_Saturation_m0[2]; + + /* DataStoreWrite: '/Data Store Write4' incorporates: + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.Index_mode_RR_manual = (uint8_t)rtb_Saturation_m0[3]; + + /* MATLAB Function: '/AF REAR VENT AUTO' */ + AFREARVENTAUTO(rtb_out_ixa); + + /* MATLAB Function: '/AF REAR Bi Level' */ + AFREARBiLevel(rtb_out_f); + + /* MATLAB Function: '/AF REAR Foot' */ + AFREARFoot(rtb_out_ju); + + /* MATLAB Function: '/AF REAR VENT AUTO1' */ + AFREARVENTAUTO(rtb_out_k1); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * DataStoreRead: '/Data Store Read' + */ + switch (rtDW.Index_mode_RR_auto) { + case 120: + case 150: + case 170: + for (i = 0; i < 8; i++) { + rtb_out_k1[i] = rtb_out_ixa[i]; + } + break; + + case 130: + case 160: + case 180: + for (i = 0; i < 8; i++) { + rtb_out_k1[i] = rtb_out_f[i]; + } + break; + + case 140: + for (i = 0; i < 8; i++) { + rtb_out_k1[i] = rtb_out_ju[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch' */ + + /* MATLAB Function: '/closest speed' incorporates: + * DataStoreRead: '/Data Store Read2' + */ + closestspeed(rtb_out_k1, rtb_out_ew, &rtb_DataTypeConversion1_lq); + + /* DataStoreWrite: '/Data Store Write5' */ + rtDW.CCU_BLOWERS_RR = rtb_DataTypeConversion1_lq; + } + + /* End of RelationalOperator: '/FixPt Relational Operator' */ + /* End of Outputs for SubSystem: '/Determine directions RR' */ + + /* Outputs for Enabled SubSystem: '/Determine directions FL' incorporates: + * EnablePort: '/Enable' + */ + /* RelationalOperator: '/FixPt Relational Operator' incorporates: + * UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + if (rtB.out_auto_hx < rtDW.DelayInput1_DSTATE_d) { + /* MATLAB Function: '/direction for front index mode' incorporates: + * DataStoreRead: '/Data Store Read' + */ + /* : switch index_mode */ + switch (rtDW.Index_mode_FL_auto) { + case 0U: + /* : case 0 */ + /* : Y = [0; 0; 0; 0]; */ + i = 0; + index_start_0 = 0; + rtb_Y_l_idx_2 = 0; + rtb_Y_l_idx_3 = 0; + break; + + case 10U: + /* : case 10 */ + /* : Y = [0; 1; 0; 10]; */ + i = 0; + index_start_0 = 1; + rtb_Y_l_idx_2 = 0; + rtb_Y_l_idx_3 = 10; + break; + + case 20U: + /* : case 20 */ + /* : Y = [0; 1; 1; 110]; */ + i = 0; + index_start_0 = 1; + rtb_Y_l_idx_2 = 1; + rtb_Y_l_idx_3 = 110; + break; + + case 30U: + /* : case 30 */ + /* : Y = [0; 1; 1; 110]; */ + i = 0; + index_start_0 = 1; + rtb_Y_l_idx_2 = 1; + rtb_Y_l_idx_3 = 110; + break; + + case 40U: + /* : case 40 */ + /* : Y = [0; 1; 1; 110]; */ + i = 0; + index_start_0 = 1; + rtb_Y_l_idx_2 = 1; + rtb_Y_l_idx_3 = 110; + break; + + case 50U: + /* : case 50 */ + /* : Y = [0; 1; 1; 110]; */ + i = 0; + index_start_0 = 1; + rtb_Y_l_idx_2 = 1; + rtb_Y_l_idx_3 = 110; + break; + + case 60U: + /* : case 60 */ + /* : Y = [0; 0; 1; 60]; */ + i = 0; + index_start_0 = 0; + rtb_Y_l_idx_2 = 1; + rtb_Y_l_idx_3 = 60; + break; + + case 70U: + /* : case 70 */ + /* : Y = [1; 0; 1; 70]; */ + i = 1; + index_start_0 = 0; + rtb_Y_l_idx_2 = 1; + rtb_Y_l_idx_3 = 70; + break; + + case 80U: + /* : case 80 */ + /* : Y = [1; 0; 0; 80]; */ + i = 1; + index_start_0 = 0; + rtb_Y_l_idx_2 = 0; + rtb_Y_l_idx_3 = 80; + break; + + case 90U: + /* : case 90 */ + /* : Y = [1; 1; 1; 90]; */ + i = 1; + index_start_0 = 1; + rtb_Y_l_idx_2 = 1; + rtb_Y_l_idx_3 = 90; + break; + + case 100U: + /* : case 100 */ + /* : Y = [1; 1; 0; 100]; */ + i = 1; + index_start_0 = 1; + rtb_Y_l_idx_2 = 0; + rtb_Y_l_idx_3 = 100; + break; + + case 110U: + /* : case 110 */ + /* : Y = [0; 1; 1; 110]; */ + i = 0; + index_start_0 = 1; + rtb_Y_l_idx_2 = 1; + rtb_Y_l_idx_3 = 110; + break; + + default: + /* : otherwise */ + /* : Y = [0; 0; 0; 0]; */ + i = 0; + index_start_0 = 0; + rtb_Y_l_idx_2 = 0; + rtb_Y_l_idx_3 = 0; + break; + } + + /* End of MATLAB Function: '/direction for front index mode' */ + + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.CCU_DEF_FL = (uint8_t)i; + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataStoreWrite: '/Data Store Write' + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.CCU_DEF_FR = (uint8_t)i; + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.CCU_FACE_FL = (uint8_t)index_start_0; + + /* DataStoreWrite: '/Data Store Write3' incorporates: + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.CCU_FOOT_FL = (uint8_t)rtb_Y_l_idx_2; + + /* DataStoreWrite: '/Data Store Write4' incorporates: + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.Index_mode_FL_manual = (uint8_t)rtb_Y_l_idx_3; + + /* MATLAB Function: '/AF VENT' */ + AFVENT(rtb_out_ixa); + + /* MATLAB Function: '/AF Bi level' */ + AFBilevel(rtb_out_f); + + /* MATLAB Function: '/AF Bi level 2' */ + AFBilevel2(rtb_out_ju); + + /* MATLAB Function: '/AF AutoFoot' */ + AFAutoFoot(rtb_out_k1); + + /* MATLAB Function: '/AF AutoFoot summer' */ + AFAutoFootsummer(rtb_out_l); + + /* MATLAB Function: '/AF Foot' */ + AFFoot(rtb_out_ai); + + /* MATLAB Function: '/AF Foot + Def' */ + AFFootDef(rtb_out_pv); + + /* MATLAB Function: '/AF Defrost' */ + AFDefrost(rtb_out_ky); + + /* MATLAB Function: '/AF Tri mode' */ + AFTrimode(rtb_out_pq2); + + /* MATLAB Function: '/AF Hi (def + vent)' */ + AFHidefvent(rtb_out_if); + + /* MATLAB Function: '/AF VENT (fail safe)' */ + AFVENT(rtb_out_c); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * DataStoreRead: '/Data Store Read' + */ + switch (rtDW.Index_mode_FL_auto) { + case 10: + for (i = 0; i < 8; i++) { + rtb_out_c[i] = rtb_out_ixa[i]; + } + break; + + case 20: + for (i = 0; i < 8; i++) { + rtb_out_c[i] = rtb_out_f[i]; + } + break; + + case 30: + for (i = 0; i < 8; i++) { + rtb_out_c[i] = rtb_out_ju[i]; + } + break; + + case 40: + for (i = 0; i < 8; i++) { + rtb_out_c[i] = rtb_out_k1[i]; + } + break; + + case 50: + for (i = 0; i < 8; i++) { + rtb_out_c[i] = rtb_out_l[i]; + } + break; + + case 60: + for (i = 0; i < 8; i++) { + rtb_out_c[i] = rtb_out_ai[i]; + } + break; + + case 70: + for (i = 0; i < 8; i++) { + rtb_out_c[i] = rtb_out_pv[i]; + } + break; + + case 80: + for (i = 0; i < 8; i++) { + rtb_out_c[i] = rtb_out_ky[i]; + } + break; + + case 90: + for (i = 0; i < 8; i++) { + rtb_out_c[i] = rtb_out_pq2[i]; + } + break; + + case 100: + for (i = 0; i < 8; i++) { + rtb_out_c[i] = rtb_out_if[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch' */ + + /* MATLAB Function: '/closest speed' incorporates: + * DataStoreRead: '/Data Store Read2' + */ + closestspeed(rtb_out_c, Gain, &rtb_DataTypeConversion1_lq); + + /* DataStoreWrite: '/Data Store Write5' */ + rtDW.CCU_BLOWERS_FL = rtb_DataTypeConversion1_lq; + } + + /* End of RelationalOperator: '/FixPt Relational Operator' */ + /* End of Outputs for SubSystem: '/Determine directions FL' */ + + /* Outputs for Enabled SubSystem: '/Determine directions FR' incorporates: + * EnablePort: '/Enable' + */ + /* RelationalOperator: '/FixPt Relational Operator' incorporates: + * UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + if (rtB.out_auto < rtDW.DelayInput1_DSTATE_d3) { + /* MATLAB Function: '/direction for front index mode' incorporates: + * DataStoreRead: '/Data Store Read' + */ + /* : switch index_mode */ + switch (rtDW.Index_mode_FR_auto) { + case 0U: + /* : case 0 */ + /* : Y = [0; 0; 0; 0]; */ + i = 0; + index_start_0 = 0; + rtb_Y_l_idx_2 = 0; + rtb_Y_l_idx_3 = 0; + break; + + case 10U: + /* : case 10 */ + /* : Y = [0; 1; 0; 10]; */ + i = 0; + index_start_0 = 1; + rtb_Y_l_idx_2 = 0; + rtb_Y_l_idx_3 = 10; + break; + + case 20U: + /* : case 20 */ + /* : Y = [0; 1; 1; 110]; */ + i = 0; + index_start_0 = 1; + rtb_Y_l_idx_2 = 1; + rtb_Y_l_idx_3 = 110; + break; + + case 30U: + /* : case 30 */ + /* : Y = [0; 1; 1; 110]; */ + i = 0; + index_start_0 = 1; + rtb_Y_l_idx_2 = 1; + rtb_Y_l_idx_3 = 110; + break; + + case 40U: + /* : case 40 */ + /* : Y = [0; 1; 1; 110]; */ + i = 0; + index_start_0 = 1; + rtb_Y_l_idx_2 = 1; + rtb_Y_l_idx_3 = 110; + break; + + case 50U: + /* : case 50 */ + /* : Y = [0; 1; 1; 110]; */ + i = 0; + index_start_0 = 1; + rtb_Y_l_idx_2 = 1; + rtb_Y_l_idx_3 = 110; + break; + + case 60U: + /* : case 60 */ + /* : Y = [0; 0; 1; 60]; */ + i = 0; + index_start_0 = 0; + rtb_Y_l_idx_2 = 1; + rtb_Y_l_idx_3 = 60; + break; + + case 70U: + /* : case 70 */ + /* : Y = [1; 0; 1; 70]; */ + i = 1; + index_start_0 = 0; + rtb_Y_l_idx_2 = 1; + rtb_Y_l_idx_3 = 70; + break; + + case 80U: + /* : case 80 */ + /* : Y = [1; 0; 0; 80]; */ + i = 1; + index_start_0 = 0; + rtb_Y_l_idx_2 = 0; + rtb_Y_l_idx_3 = 80; + break; + + case 90U: + /* : case 90 */ + /* : Y = [1; 1; 1; 90]; */ + i = 1; + index_start_0 = 1; + rtb_Y_l_idx_2 = 1; + rtb_Y_l_idx_3 = 90; + break; + + case 100U: + /* : case 100 */ + /* : Y = [1; 1; 0; 100]; */ + i = 1; + index_start_0 = 1; + rtb_Y_l_idx_2 = 0; + rtb_Y_l_idx_3 = 100; + break; + + case 110U: + /* : case 110 */ + /* : Y = [0; 1; 1; 110]; */ + i = 0; + index_start_0 = 1; + rtb_Y_l_idx_2 = 1; + rtb_Y_l_idx_3 = 110; + break; + + default: + /* : otherwise */ + /* : Y = [0; 0; 0; 0]; */ + i = 0; + index_start_0 = 0; + rtb_Y_l_idx_2 = 0; + rtb_Y_l_idx_3 = 0; + break; + } + + /* End of MATLAB Function: '/direction for front index mode' */ + + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.CCU_DEF_FL = (uint8_t)i; + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataStoreWrite: '/Data Store Write' + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.CCU_DEF_FR = (uint8_t)i; + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.CCU_FACE_FR = (uint8_t)index_start_0; + + /* DataStoreWrite: '/Data Store Write3' incorporates: + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.CCU_FOOT_FR = (uint8_t)rtb_Y_l_idx_2; + + /* Switch: '/Switch' incorporates: + * DataStoreWrite: '/Data Store Write4' + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.Index_mode_FR_manual = (uint8_t)rtb_Y_l_idx_3; + + /* MATLAB Function: '/AF VENT' */ + AFVENT(rtb_out_ixa); + + /* MATLAB Function: '/AF Bi level' */ + AFBilevel(rtb_out_f); + + /* MATLAB Function: '/AF Bi level 2' */ + AFBilevel2(rtb_out_ju); + + /* MATLAB Function: '/AF AutoFoot' */ + AFAutoFoot(rtb_out_k1); + + /* MATLAB Function: '/AF AutoFoot summer' */ + AFAutoFootsummer(rtb_out_l); + + /* MATLAB Function: '/AF Foot' */ + AFFoot(rtb_out_ai); + + /* MATLAB Function: '/AF Foot + Def' */ + AFFootDef(rtb_out_pv); + + /* MATLAB Function: '/AF Defrost' */ + AFDefrost(rtb_out_ky); + + /* MATLAB Function: '/AF Tri mode' */ + AFTrimode(rtb_out_pq2); + + /* MATLAB Function: '/AF Hi (def + vent)' */ + AFHidefvent(rtb_out_if); + + /* MATLAB Function: '/AF VENT (fail safe)' */ + AFVENT(rtb_out_c); + + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * DataStoreRead: '/Data Store Read' + */ + switch (rtDW.Index_mode_FR_auto) { + case 10: + for (i = 0; i < 8; i++) { + rtb_out_c[i] = rtb_out_ixa[i]; + } + break; + + case 20: + for (i = 0; i < 8; i++) { + rtb_out_c[i] = rtb_out_f[i]; + } + break; + + case 30: + for (i = 0; i < 8; i++) { + rtb_out_c[i] = rtb_out_ju[i]; + } + break; + + case 40: + for (i = 0; i < 8; i++) { + rtb_out_c[i] = rtb_out_k1[i]; + } + break; + + case 50: + for (i = 0; i < 8; i++) { + rtb_out_c[i] = rtb_out_l[i]; + } + break; + + case 60: + for (i = 0; i < 8; i++) { + rtb_out_c[i] = rtb_out_ai[i]; + } + break; + + case 70: + for (i = 0; i < 8; i++) { + rtb_out_c[i] = rtb_out_pv[i]; + } + break; + + case 80: + for (i = 0; i < 8; i++) { + rtb_out_c[i] = rtb_out_ky[i]; + } + break; + + case 90: + for (i = 0; i < 8; i++) { + rtb_out_c[i] = rtb_out_pq2[i]; + } + break; + + case 100: + for (i = 0; i < 8; i++) { + rtb_out_c[i] = rtb_out_if[i]; + } + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch' */ + + /* MATLAB Function: '/closest speed' incorporates: + * DataStoreRead: '/Data Store Read2' + */ + closestspeed(rtb_out_c, Gain1, &rtb_DataTypeConversion1_lq); + + /* DataStoreWrite: '/Data Store Write5' */ + rtDW.CCU_BLOWERS_FR = rtb_DataTypeConversion1_lq; + } + + /* End of RelationalOperator: '/FixPt Relational Operator' */ + /* End of Outputs for SubSystem: '/Determine directions FR' */ + + /* DataStoreWrite: '/Data Store Write' */ + rtDW.eCompChiller_Err = 0.0; + + /* Gain: '/Gain' incorporates: + * DataStoreRead: '/Data Store Read10' + * DataStoreWrite: '/Data Store Write' + */ + rtDW.eComp_InputC = (uint16_t) + (rtDW.HVC_ERR_STATUS_MSG_MODEL.HVC_CompInputC_Val_ro << 7); + + /* Bias: '/Bias' incorporates: + * DataStoreRead: '/Data Store Read10' + * DataStoreWrite: '/Data Store Write' + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.eComp_Temp = (int16_t) + (rtDW.HVC_ERR_STATUS_MSG_MODEL.HVC_CompInvTemp_Val_ro - 50); + + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Bias: '/Bias' + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write' + * DataTypeConversion: '/Data Type Conversion' + * Gain: '/Gain1' + * Gain: '/Gain2' + */ + rtDW.AMB = (int16_t)floor((0.01 * (double) + rtDW.CCUCAN_BCM_Powertrain_model.BCM_AmbTempRaw_ro - 40.0) * 10.0); + + /* If: '/If' incorporates: + * RelationalOperator: '/Relational Operator1' + * UnitDelay: '/Unit Delay' + */ + if (rtDW.UnitDelay_DSTATE_cu == -9999) { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* Switch: '/Switch1' incorporates: + * DataStoreWrite: '/Data Store Write' + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.AMB_store = rtDW.AMB; + + /* End of Outputs for SubSystem: '/ ' */ + } else { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + /* Lookup_n-D: '/Get LVL for temp' incorporates: + * DataStoreWrite: '/Data Store Write' + * DataTypeConversion: '/Data Type Conversion1' + */ + rtb_FLU_tg_correct_aa = rtConstP.pooled53[plook_u32s16_bincka(rtDW.AMB, + rtConstP.GetLVLfortemp_bp01Data, 5U)]; + + /* If: '/If1' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write' + */ + if (rtDW.KEEP_RISING_UNTIL_LIMIT > 0.0) { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + u_p(rtDW.AMB, rtb_FLU_tg_correct_aa, &rtb_DataTypeConversion1_lq, + &rtDW.AMB_store, &rtDW.KEEP_RISING_UNTIL_LIMIT); + + /* End of Outputs for SubSystem: '/ ' */ + } else { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + u_g2(rtDW.AMB, rtb_FLU_tg_correct_aa, &rtb_DataTypeConversion1_lq, + &rtDW.AMB_store, &rtDW.KEEP_RISING_UNTIL_LIMIT); + + /* End of Outputs for SubSystem: '/ ' */ + } + + /* End of If: '/If1' */ + + /* If: '/If1' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write' + */ + if (rtDW.KEEP_FALLING_UNTIL_LIMIT > 0.0) { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + u_kb(rtDW.AMB, rtb_FLU_tg_correct_aa, &rtb_DataTypeConversion3_gf, + &rtDW.AMB_store, &rtDW.KEEP_FALLING_UNTIL_LIMIT); + + /* End of Outputs for SubSystem: '/ ' */ + } else { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + u_my(rtDW.AMB, rtb_FLU_tg_correct_aa, &rtb_DataTypeConversion3_gf, + &rtDW.AMB_store, &rtDW.KEEP_FALLING_UNTIL_LIMIT); + + /* End of Outputs for SubSystem: '/ ' */ + } + + /* End of If: '/If1' */ + + /* Sum: '/Subtract' incorporates: + * DataStoreRead: '/Data Store Read15' + * UnitDelay: '/Unit Delay' + */ + rtb_Subtract = rtDW.t_now - rtDW.UnitDelay_DSTATE_c; + + /* If: '/If' incorporates: + * DataStoreRead: '/Data Store Read12' + * DataStoreRead: '/Data Store Read' + */ + /* : f_g_ssAMBFILT_WATER = g_ssAMBFILT_WATER; */ + if ((rtDW.VehicleSpeed > 45) && (rtDW.KEEP_UNTIL_SPEED_DROPS > 0)) { + /* Outputs for IfAction SubSystem: '/ - ' incorporates: + * ActionPort: '/Action Port' + */ + /* If: '/If1' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write' + */ + if (rtDW.KEEP_RISING_UNTIL_LIMIT > 0.0) { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + u_p(rtDW.AMB, rtb_FLU_tg_correct_aa, &rtb_Merge_c5, &rtDW.AMB_store, + &rtDW.KEEP_RISING_UNTIL_LIMIT); + + /* End of Outputs for SubSystem: '/ ' */ + } else { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + u_g2(rtDW.AMB, rtb_FLU_tg_correct_aa, &rtb_Merge_c5, &rtDW.AMB_store, + &rtDW.KEEP_RISING_UNTIL_LIMIT); + + /* End of Outputs for SubSystem: '/ ' */ + } + + /* End of If: '/If1' */ + + /* If: '/If1' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write' + */ + if (rtDW.KEEP_FALLING_UNTIL_LIMIT > 0.0) { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + u_kb(rtDW.AMB, rtb_FLU_tg_correct_aa, &rtb_Merge_m4, &rtDW.AMB_store, + &rtDW.KEEP_FALLING_UNTIL_LIMIT); + + /* End of Outputs for SubSystem: '/ ' */ + } else { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + u_my(rtDW.AMB, rtb_FLU_tg_correct_aa, &rtb_Merge_m4, &rtDW.AMB_store, + &rtDW.KEEP_FALLING_UNTIL_LIMIT); + + /* End of Outputs for SubSystem: '/ ' */ + } + + /* End of If: '/If1' */ + + /* Switch: '/Switch1' incorporates: + * Abs: '/Abs' + * Constant: '/epsilon' + * DataStoreRead: '/Read Amb' + * DataStoreWrite: '/Data Store Write' + * RelationalOperator: '/AMBraw > AMB' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + * Switch: '/Switch' + */ + if (fabs((double)rtDW.AMB - rtDW.AMB_store) <= 0.01) { + /* SignalConversion generated from: '/AMB_new' */ + rtb_Add_be = rtDW.AMB_store; + } else { + if (rtDW.AMB > rtDW.AMB_store) { + /* Switch: '/Switch' incorporates: + * DataTypeConversion: '/Data Type Conversion' + */ + rtb_FLU_tg_correct_aa = rtb_Merge_c5; + } else { + /* Switch: '/Switch' incorporates: + * DataTypeConversion: '/Data Type Conversion' + * UnaryMinus: '/Unary Minus' + */ + rtb_FLU_tg_correct_aa = (int16_t)-rtb_Merge_m4; + } + + /* SignalConversion generated from: '/AMB_new' incorporates: + * Constant: '/Constant' + * Product: '/Divide' + * Product: '/Product' + * Sum: '/Add' + * Switch: '/Switch' + */ + rtb_Add_be = (double)rtb_Subtract / 60000.0 * (double) + rtb_FLU_tg_correct_aa + rtDW.AMB_store; + } + + /* End of Switch: '/Switch1' */ + /* End of Outputs for SubSystem: '/ - ' */ + } else if (rtDW.VehicleSpeed > 50) { + /* Outputs for IfAction SubSystem: '/ - ' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.KEEP_UNTIL_SPEED_DROPS = 1U; + + /* If: '/If1' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write' + */ + if (rtDW.KEEP_RISING_UNTIL_LIMIT > 0.0) { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + u_p(rtDW.AMB, rtb_FLU_tg_correct_aa, &rtb_Merge_c5, &rtDW.AMB_store, + &rtDW.KEEP_RISING_UNTIL_LIMIT); + + /* End of Outputs for SubSystem: '/ ' */ + } else { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + u_g2(rtDW.AMB, rtb_FLU_tg_correct_aa, &rtb_Merge_c5, &rtDW.AMB_store, + &rtDW.KEEP_RISING_UNTIL_LIMIT); + + /* End of Outputs for SubSystem: '/ ' */ + } + + /* End of If: '/If1' */ + + /* If: '/If1' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write' + */ + if (rtDW.KEEP_FALLING_UNTIL_LIMIT > 0.0) { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + u_kb(rtDW.AMB, rtb_FLU_tg_correct_aa, &rtb_Merge_m4, &rtDW.AMB_store, + &rtDW.KEEP_FALLING_UNTIL_LIMIT); + + /* End of Outputs for SubSystem: '/ ' */ + } else { + /* Outputs for IfAction SubSystem: '/ ' incorporates: + * ActionPort: '/Action Port' + */ + u_my(rtDW.AMB, rtb_FLU_tg_correct_aa, &rtb_Merge_m4, &rtDW.AMB_store, + &rtDW.KEEP_FALLING_UNTIL_LIMIT); + + /* End of Outputs for SubSystem: '/ ' */ + } + + /* End of If: '/If1' */ + + /* Switch: '/Switch1' incorporates: + * Abs: '/Abs' + * Constant: '/epsilon' + * DataStoreRead: '/Read Amb' + * DataStoreWrite: '/Data Store Write' + * RelationalOperator: '/AMBraw > AMB' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + * Switch: '/Switch' + */ + if (fabs((double)rtDW.AMB - rtDW.AMB_store) <= 0.01) { + /* SignalConversion generated from: '/AMB_new' */ + rtb_Add_be = rtDW.AMB_store; + } else { + if (rtDW.AMB > rtDW.AMB_store) { + /* Switch: '/Switch' incorporates: + * DataTypeConversion: '/Data Type Conversion' + */ + rtb_FLU_tg_correct_aa = rtb_Merge_c5; + } else { + /* Switch: '/Switch' incorporates: + * DataTypeConversion: '/Data Type Conversion' + * UnaryMinus: '/Unary Minus' + */ + rtb_FLU_tg_correct_aa = (int16_t)-rtb_Merge_m4; + } + + /* SignalConversion generated from: '/AMB_new' incorporates: + * Constant: '/Constant' + * Product: '/Divide' + * Product: '/Product' + * Sum: '/Add' + * Switch: '/Switch' + */ + rtb_Add_be = (double)rtb_Subtract / 60000.0 * (double) + rtb_FLU_tg_correct_aa + rtDW.AMB_store; + } + + /* End of Switch: '/Switch1' */ + /* End of Outputs for SubSystem: '/ - ' */ + } else { + /* Outputs for IfAction SubSystem: '/' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant1' + */ + rtDW.KEEP_UNTIL_SPEED_DROPS = 0U; + + /* MATLAB Function: '/' */ + /* : rate_at_10 = 0.5; */ + /* : rate_at_50 = double(g_aucAMBRATE_RISING(lvl + 1)) ; */ + /* : f_lower_upper_bounds = [rate_at_10, rate_at_50]; */ + rtb_f_lower_upper_bounds[0] = 0.5; + i = rtb_FLU_tg_correct_aa + 1; + if (rtb_FLU_tg_correct_aa + 1 > 32767) { + i = 32767; + } + + rtb_f_lower_upper_bounds[1] = g_aucAMBRATE_RISING[i - 1]; + + /* MATLAB Function: '/ .' */ + /* : fprintf("lvl = %d\n", lvl); */ + printf("lvl = %d\n", rtb_FLU_tg_correct_aa); + fflush(stdout); + + /* Switch: '/Switch1' incorporates: + * Abs: '/Abs' + * Constant: '/Constant' + * Constant: '/epsilon' + * DataStoreRead: '/Read Amb' + * DataStoreWrite: '/Data Store Write' + * Product: '/Divide' + * Product: '/Product' + * RelationalOperator: '/AMBraw > AMB' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + * Sum: '/Add' + * Switch: '/Switch' + */ + /* : f_g_aucAMBRATE_FALLING = g_aucAMBRATE_FALLING(lvl + 1); */ + if (fabs((double)rtDW.AMB - rtDW.AMB_store) <= 0.01) { + rtb_Add_be = rtDW.AMB; + } else { + if (rtDW.AMB > rtDW.AMB_store) { + /* Switch: '/ >10' incorporates: + * Constant: '/Constant' + * Switch: '/Switch' + */ + if (rtDW.VehicleSpeed > 10) { + /* Lookup_n-D: '/1-D Lookup Table1' incorporates: + * DataStoreRead: '/Data Store Read12' + */ + rtb_Add_be = look1_iu16td_binlc(rtDW.VehicleSpeed, + rtConstP.uDLookupTable1_bp01Data, rtb_f_lower_upper_bounds, 1U); + } else { + rtb_Add_be = 0.5; + } + + /* End of Switch: '/ >10' */ + } else { + /* MATLAB Function: '/ .' incorporates: + * MATLAB Function: '/' + */ + i = rtb_FLU_tg_correct_aa + 1; + if (rtb_FLU_tg_correct_aa + 1 > 32767) { + i = 32767; + } + + /* Switch: '/Switch' incorporates: + * DataTypeConversion: '/Data Type Conversion' + * MATLAB Function: '/ .' + * UnaryMinus: '/Unary Minus' + */ + rtb_Add_be = -(double)g_aucAMBRATE_FALLING[i - 1]; + } + + rtb_Add_be = (double)rtb_Subtract / 60000.0 * rtb_Add_be + + rtDW.AMB_store; + } + + /* End of Switch: '/Switch1' */ + /* End of Outputs for SubSystem: '/' */ + } + + /* End of If: '/If' */ + + /* Switch: '/Switch' incorporates: + * DataStoreRead: '/Data Store Read11' + * DataStoreRead: '/Data Store Read12' + * MATLAB Function: '/Coolant temp threshold' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator' + * Switch: '/Switch' + */ + if (rtDW.ECT <= g_ssAMBFILT_WATER) { + /* Switch: '/Switch1' incorporates: + * Abs: '/Abs' + * Constant: '/epsilon' + * DataStoreRead: '/Read Amb' + * DataStoreWrite: '/Data Store Write' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + */ + if (fabs((double)rtDW.AMB - rtDW.AMB_store) > 0.01) { + /* Switch: '/Switch' incorporates: + * DataTypeConversion: '/Data Type Conversion' + * DataTypeConversion: '/Data Type Conversion' + * RelationalOperator: '/AMBraw > AMB' + * UnaryMinus: '/Unary Minus' + */ + if (rtDW.AMB > rtDW.AMB_store) { + rtb_FLU_tg_correct_aa = rtb_DataTypeConversion1_lq; + } else { + rtb_FLU_tg_correct_aa = (int16_t)-rtb_DataTypeConversion3_gf; + } + + /* Switch: '/Switch1' incorporates: + * Constant: '/Constant' + * Product: '/Divide' + * Product: '/Product' + * Sum: '/Add' + * Switch: '/Switch' + */ + rtDW.AMB_store += (double)rtb_Subtract / 60000.0 * (double) + rtb_FLU_tg_correct_aa; + } + + /* End of Switch: '/Switch1' */ + } else if (rtDW.VehicleSpeed != 0) { + /* Switch: '/Switch1' incorporates: + * DataStoreWrite: '/Write new AMB' + * Switch: '/Switch' + */ + rtDW.AMB_store = rtb_Add_be; + } + + /* End of Switch: '/Switch' */ + + /* Update for UnitDelay: '/Unit Delay' incorporates: + * DataStoreRead: '/Data Store Read15' + */ + rtDW.UnitDelay_DSTATE_c = rtDW.t_now; + + /* End of Outputs for SubSystem: '/ ' */ + } + + /* End of If: '/If' */ + + /* Gain: '/Gain' incorporates: + * DataStoreRead: '/Data Store Read4' + * DataStoreWrite: '/Data Store Write' + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.Sun_R = 4.01575 * (double) + rtDW.CCUCAN_BCM_Climatic_model.SolarSensRightVal_ro; + + /* Gain: '/Gain' incorporates: + * DataStoreRead: '/Data Store Read4' + * DataStoreWrite: '/Data Store Write' + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.Sun_L = 4.01575 * (double) + rtDW.CCUCAN_BCM_Climatic_model.SolarSensLeftVal_ro; + + /* Bias: '/Bias' incorporates: + * DataStoreRead: '/Data Store Read5' + * DataStoreWrite: '/Data Store Write1' + * DataTypeConversion: '/Data Type Conversion1' + */ + rtDW.ECT = (int16_t)(rtDW.CCUCAN_EMS_Veh_model.EMS_EngCoolTemp_Val_ro - 40); + + /* Gain: '/Gain' incorporates: + * DataStoreRead: '/Data Store Read5' + * DataStoreWrite: '/Data Store Write1' + * DataTypeConversion: '/Data Type Conversion1' + */ + rtDW.Engine_speed = 0.25 * (double) + rtDW.CCUCAN_EMS_Veh_model.EMS_nICEngineSpeed3_Val_ro; + + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * DataStoreRead: '/Data Store Read6' + * DataStoreWrite: '/Data Store Write2' + * DataTypeConversion: '/Data Type Conversion' + * Gain: '/Gain' + */ + rtDW.VehicleSpeed = (uint16_t)(0.01 * (double) + rtDW.CCUCAN_ESC_04_model.ESC_VehicleSpeed_ro); + + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataStoreRead: '/Data Store Read7' + */ + rtDW.BCM_T15_Stat = rtDW.CCUCAN_BCM_VEH_STATE_model.BCM_T15_Stat; + + /* DataStoreWrite: '/Data Store Write7' incorporates: + * DataStoreRead: '/Data Store Read8' + */ + rtDW.eCompChiller_Req = rtDW.CCUCAN_EMS_HVC_REQ_MSG_MODEL.EMS_eCompChiller_Req; + + /* DataStoreWrite: '/Data Store Write8' incorporates: + * DataStoreRead: '/Data Store Read9' + */ + rtDW.SeatOccupiedRL = rtDW.CCUCAN_OCURL_MSG_model.OCURL_SeatOccupied_Stat; + + /* Outputs for Enabled SubSystem: '/Subsystem53' incorporates: + * EnablePort: '/Enable' + */ + /* DataStoreRead: '/Data Store Read1' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read3' + */ + if (rtDW.BCM_T15_Stat > 0) { + /* Outputs for Enabled SubSystem: '/Subsystem' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU1_MODEL.FIU_FootTempCorFL_Req > 0) { + /* Sum: '/Plus' incorporates: + * Constant: '/Constant' + * DataStoreWrite: '/Data Store Write4' + */ + rtDW.CCU_SET_FOOT_FL = (uint8_t)(rtDW.FIU_CCU1_MODEL.FIU_FootTempCorFL_Req + - 1); + + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant1' + */ + rtDW.CCU_AC_MAX = 0U; + } + + /* End of Outputs for SubSystem: '/Subsystem' */ + + /* Outputs for Enabled SubSystem: '/Subsystem1' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU1_MODEL.FIU_CCmodeFL_Req > 0) { + /* Switch: '/Switch' incorporates: + * DataStoreWrite: '/Data Store Write6' + */ + rtDW.CCU_MODE_FL = (uint8_t)(rtDW.FIU_CCU1_MODEL.FIU_CCmodeFL_Req > 1); + + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.CCU_AC_MAX = 0U; + + /* If: '/If' incorporates: + * Constant: '/Constant2' + * DataStoreWrite: '/Data Store Write6' + * RelationalOperator: '/Relational Operator1' + */ + if (rtDW.CCU_MODE_FL == 1) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.CCU_RECIRC = 2U; + + /* End of Outputs for SubSystem: '/If Action Subsystem' */ + } + + /* End of If: '/If' */ + } + + /* End of Outputs for SubSystem: '/Subsystem1' */ + + /* Outputs for Enabled SubSystem: '/Subsystem10' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU1_MODEL.FIU_CCmodeFR_Req > 0) { + /* Switch: '/Switch' incorporates: + * DataStoreWrite: '/Data Store Write10' + */ + rtDW.CCU_MODE_FR = (uint8_t)(rtDW.FIU_CCU1_MODEL.FIU_CCmodeFR_Req > 1); + + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.CCU_AC_MAX = 0U; + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * Constant: '/true' + */ + rtDW.changed_FR_params = 1U; + } + + /* End of Outputs for SubSystem: '/Subsystem10' */ + + /* Outputs for Enabled SubSystem: '/Subsystem11' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU1_MODEL.FIU_AirDirectionFR_Def_Req > 0) { + /* Switch: '/Switch' incorporates: + * DataStoreWrite: '/Data Store Write1' + */ + rtDW.CCU_DEF_FL = (uint8_t)(rtDW.FIU_CCU1_MODEL.FIU_AirDirectionFR_Def_Req + <= 1); + + /* DataStoreWrite: '/Data Store Write11' incorporates: + * DataStoreWrite: '/Data Store Write1' + */ + rtDW.CCU_DEF_FR = rtDW.CCU_DEF_FL; + + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.CCU_AC_MAX = 0U; + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/true' + */ + rtDW.changed_FR_params = 1U; + } + + /* End of Outputs for SubSystem: '/Subsystem11' */ + + /* Outputs for Enabled SubSystem: '/Subsystem12' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU1_MODEL.FIU_AirDirectionFR_Face_Req > 0) { + /* Switch: '/Switch' incorporates: + * DataStoreWrite: '/Data Store Write12' + */ + rtDW.CCU_FACE_FR = (uint8_t) + (rtDW.FIU_CCU1_MODEL.FIU_AirDirectionFR_Face_Req <= 1); + + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.CCU_AC_MAX = 0U; + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * Constant: '/true' + */ + rtDW.changed_FR_params = 1U; + } + + /* End of Outputs for SubSystem: '/Subsystem12' */ + + /* Outputs for Enabled SubSystem: '/Subsystem13' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU1_MODEL.FIU_AirDirectionFR_Foot_Req > 0) { + /* Switch: '/Switch' incorporates: + * DataStoreWrite: '/Data Store Write13' + */ + rtDW.CCU_FOOT_FR = (uint8_t) + (rtDW.FIU_CCU1_MODEL.FIU_AirDirectionFR_Foot_Req <= 1); + + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.CCU_AC_MAX = 0U; + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * Constant: '/true' + */ + rtDW.changed_FR_params = 1U; + } + + /* End of Outputs for SubSystem: '/Subsystem13' */ + + /* Outputs for Enabled SubSystem: '/Subsystem14' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU1_MODEL.FIU_BlowerSpeedFL_Req > 0) { + /* Switch: '/Switch5' incorporates: + * Constant: '/blower off' + * DataStoreWrite: '/Data Store Write14' + */ + if (rtDW.FIU_CCU1_MODEL.FIU_BlowerSpeedFL_Req > 7) { + rtDW.CCU_BLOWERS_FL = 0U; + } else { + rtDW.CCU_BLOWERS_FL = rtDW.FIU_CCU1_MODEL.FIU_BlowerSpeedFL_Req; + } + + /* End of Switch: '/Switch5' */ + + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.CCU_AC_MAX = 0U; + } + + /* End of Outputs for SubSystem: '/Subsystem14' */ + + /* Outputs for Enabled SubSystem: '/Subsystem15' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU1_MODEL.FIU_BlowerSpeedFR_Req > 0) { + /* Switch: '/Switch5' incorporates: + * Constant: '/blower off' + * DataStoreWrite: '/Data Store Write15' + */ + if (rtDW.FIU_CCU1_MODEL.FIU_BlowerSpeedFR_Req > 7) { + rtDW.CCU_BLOWERS_FR = 0U; + } else { + rtDW.CCU_BLOWERS_FR = rtDW.FIU_CCU1_MODEL.FIU_BlowerSpeedFR_Req; + } + + /* End of Switch: '/Switch5' */ + + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.CCU_AC_MAX = 0U; + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * Constant: '/true' + */ + rtDW.changed_FR_params = 1U; + } + + /* End of Outputs for SubSystem: '/Subsystem15' */ + + /* Outputs for Enabled SubSystem: '/Subsystem16' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU1_MODEL.FIU_CCautoModeFL_Req > 0) { + /* DataStoreWrite: '/Data Store Write16' */ + rtDW.CCU_AUTOMODE_FL = rtDW.FIU_CCU1_MODEL.FIU_CCautoModeFL_Req; + + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.CCU_AC_MAX = 0U; + } + + /* End of Outputs for SubSystem: '/Subsystem16' */ + + /* Outputs for Enabled SubSystem: '/Subsystem17' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU1_MODEL.FIU_CCautoModeFR_Req > 0) { + /* DataStoreWrite: '/Data Store Write17' */ + rtDW.CCU_AUTOMODE_FR = rtDW.FIU_CCU1_MODEL.FIU_CCautoModeFR_Req; + + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.CCU_AC_MAX = 0U; + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * Constant: '/true' + */ + rtDW.changed_FR_params = 1U; + } + + /* End of Outputs for SubSystem: '/Subsystem17' */ + + /* Outputs for Enabled SubSystem: '/Subsystem18' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU1_MODEL.FIU_Recirculation_Req > 0) { + /* MultiPortSwitch: '/Multiport Switch' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * Constant: '/Constant2' + * DataStoreWrite: '/Data Store Write19' + */ + switch (rtDW.FIU_CCU1_MODEL.FIU_Recirculation_Req) { + case 1: + rtDW.CCU_RECIRC = 1U; + break; + + case 2: + rtDW.CCU_RECIRC = 0U; + break; + + default: + rtDW.CCU_RECIRC = 2U; + break; + } + + /* End of MultiPortSwitch: '/Multiport Switch' */ + + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant3' + */ + rtDW.CCU_AC_MAX = 0U; + } + + /* End of Outputs for SubSystem: '/Subsystem18' */ + + /* Outputs for Enabled SubSystem: '/Subsystem19' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU1_MODEL.FIU_DeflectorSwDL_Req > 0) { + /* Switch: '/Switch' incorporates: + * Constant: '/no LED' + * DataStoreWrite: '/Data Store Write1' + */ + if (rtDW.FIU_CCU1_MODEL.FIU_DeflectorSwDL_Req > 3) { + rtDW.DRS_SFL = 0U; + } else { + rtDW.DRS_SFL = rtDW.FIU_CCU1_MODEL.FIU_DeflectorSwDL_Req; + } + + /* End of Switch: '/Switch' */ + + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.CCU_AC_MAX = 0U; + } + + /* End of Outputs for SubSystem: '/Subsystem19' */ + + /* Outputs for Enabled SubSystem: '/Subsystem20' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU1_MODEL.FIU_DeflectorSwDR_Req > 0) { + /* Switch: '/Switch' incorporates: + * Constant: '/no LED' + * DataStoreWrite: '/Data Store Write1' + */ + if (rtDW.FIU_CCU1_MODEL.FIU_DeflectorSwDR_Req > 3) { + rtDW.DRS_SFR = 0U; + } else { + rtDW.DRS_SFR = rtDW.FIU_CCU1_MODEL.FIU_DeflectorSwDR_Req; + } + + /* End of Switch: '/Switch' */ + + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.CCU_AC_MAX = 0U; + } + + /* End of Outputs for SubSystem: '/Subsystem20' */ + + /* Outputs for Enabled SubSystem: '/Subsystem21' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU1_MODEL.FIU_ACfrontOFF_Req > 0) { + /* Switch: '/Switch' incorporates: + * DataStoreWrite: '/Data Store Write22' + */ + rtDW.CCU_AC_FRONT = (uint8_t)(rtDW.FIU_CCU1_MODEL.FIU_ACfrontOFF_Req <= 1); + + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.CCU_AC_MAX = 0U; + } + + /* End of Outputs for SubSystem: '/Subsystem21' */ + + /* Outputs for Enabled SubSystem: '/Subsystem22' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU1_MODEL.FIU_DeflectorSwFPL_Req > 0) { + /* Switch: '/Switch' incorporates: + * Constant: '/no LED' + * DataStoreWrite: '/Data Store Write23' + */ + if (rtDW.FIU_CCU1_MODEL.FIU_DeflectorSwFPL_Req > 3) { + rtDW.DRS_CFL = 0U; + } else { + rtDW.DRS_CFL = rtDW.FIU_CCU1_MODEL.FIU_DeflectorSwFPL_Req; + } + + /* End of Switch: '/Switch' */ + + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.CCU_AC_MAX = 0U; + } + + /* End of Outputs for SubSystem: '/Subsystem22' */ + + /* Outputs for Enabled SubSystem: '/Subsystem23' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU1_MODEL.FIU_DeflectorSwFPR_Req > 0) { + /* Switch: '/Switch' incorporates: + * Constant: '/no LED' + * DataStoreWrite: '/Data Store Write24' + */ + if (rtDW.FIU_CCU1_MODEL.FIU_DeflectorSwFPR_Req > 3) { + rtDW.DRS_CFR = 0U; + } else { + rtDW.DRS_CFR = rtDW.FIU_CCU1_MODEL.FIU_DeflectorSwFPR_Req; + } + + /* End of Switch: '/Switch' */ + + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.CCU_AC_MAX = 0U; + } + + /* End of Outputs for SubSystem: '/Subsystem23' */ + + /* Outputs for Enabled SubSystem: '/Subsystem24' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU1_MODEL.FIU_FrontZoneSync_Req > 0) { + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.CCU_AC_MAX = 0U; + + /* If: '/If' */ + if (rtDW.FIU_CCU1_MODEL.FIU_FrontZoneSync_Req == 1) { + /* Outputs for IfAction SubSystem: '/sync front action' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write18' incorporates: + * Constant: '/on' + */ + rtDW.enable_front_sync = 1U; + + /* End of Outputs for SubSystem: '/sync front action' */ + } else if (rtDW.FIU_CCU1_MODEL.FIU_FrontZoneSync_Req == 2) { + /* Outputs for IfAction SubSystem: '/full sync action' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.enable_full_sync = 1U; + + /* End of Outputs for SubSystem: '/full sync action' */ + } else if (rtDW.FIU_CCU1_MODEL.FIU_FrontZoneSync_Req == 3) { + /* Outputs for IfAction SubSystem: '/sync off action' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write18' incorporates: + * Constant: '/on' + */ + rtDW.disable_front_sync = 1U; + + /* End of Outputs for SubSystem: '/sync off action' */ + } + + /* End of If: '/If' */ + } + + /* End of Outputs for SubSystem: '/Subsystem24' */ + + /* Outputs for Enabled SubSystem: '/Subsystem4' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU1_MODEL.FIU_FootTempCorFR_Req > 0) { + /* Sum: '/Plus' incorporates: + * Constant: '/Constant' + * DataStoreWrite: '/Data Store Write5' + */ + rtDW.CCU_SET_FOOT_FR = (uint8_t)(rtDW.FIU_CCU1_MODEL.FIU_FootTempCorFR_Req + - 1); + + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant1' + */ + rtDW.CCU_AC_MAX = 0U; + } + + /* End of Outputs for SubSystem: '/Subsystem4' */ + + /* Outputs for Enabled SubSystem: '/Subsystem5' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU1_MODEL.FIU_TargetTempFL_Val_ro > 0) { + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Bias: '/Bias' + * DataTypeConversion: '/Data Type Conversion' + * Gain: '/Gain' + * Gain: '/Gain1' + */ + rtDW.CCU_SET_FL = (uint16_t)((0.5 * (double) + rtDW.FIU_CCU1_MODEL.FIU_TargetTempFL_Val_ro + 15.5) * 10.0); + + /* Saturate: '/Saturation' */ + if (rtDW.CCU_SET_FL > 305) { + /* DataTypeConversion: '/Data Type Conversion1' */ + rtDW.CCU_SET_FL = 305U; + } + + /* End of Saturate: '/Saturation' */ + + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.CCU_AC_MAX = 0U; + + /* If: '/If' incorporates: + * DataStoreWrite: '/Data Store Write1' + */ + if (rtDW.CCU_SET_FL < 165) { + /* Outputs for IfAction SubSystem: '/LO mode' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/LOW' + */ + rtDW.LO_HI_MODE_FL = 1U; + + /* End of Outputs for SubSystem: '/LO mode' */ + } else if (rtDW.CCU_SET_FL > 295) { + /* Outputs for IfAction SubSystem: '/HI mode' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/HI' + */ + rtDW.LO_HI_MODE_FL = 2U; + + /* End of Outputs for SubSystem: '/HI mode' */ + } else { + /* Outputs for IfAction SubSystem: '/not LO or HI' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/not LO or HI' + */ + rtDW.LO_HI_MODE_FL = 0U; + + /* End of Outputs for SubSystem: '/not LO or HI' */ + } + + /* End of If: '/If' */ + } + + /* End of Outputs for SubSystem: '/Subsystem5' */ + + /* Outputs for Enabled SubSystem: '/Subsystem6' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU1_MODEL.FIU_TargetTempFR_Val_ro > 0) { + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Bias: '/Bias' + * DataTypeConversion: '/Data Type Conversion' + * Gain: '/Gain' + * Gain: '/Gain1' + */ + rtDW.CCU_SET_FR = (uint16_t)((0.5 * (double) + rtDW.FIU_CCU1_MODEL.FIU_TargetTempFR_Val_ro + 15.5) * 10.0); + + /* Saturate: '/Saturation' */ + if (rtDW.CCU_SET_FR > 305) { + /* DataTypeConversion: '/Data Type Conversion1' */ + rtDW.CCU_SET_FR = 305U; + } + + /* End of Saturate: '/Saturation' */ + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/Constant' + */ + rtDW.CCU_AC_MAX = 0U; + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * Constant: '/true' + */ + rtDW.changed_FR_params = 1U; + + /* If: '/If' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + if (rtDW.CCU_SET_FR < 165) { + /* Outputs for IfAction SubSystem: '/LO mode' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/LOW' + */ + rtDW.LO_HI_MODE_FR = 1U; + + /* End of Outputs for SubSystem: '/LO mode' */ + } else if (rtDW.CCU_SET_FR > 295) { + /* Outputs for IfAction SubSystem: '/HI mode' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/HI' + */ + rtDW.LO_HI_MODE_FR = 2U; + + /* End of Outputs for SubSystem: '/HI mode' */ + } else { + /* Outputs for IfAction SubSystem: '/not LO or HI' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/not LO or HI' + */ + rtDW.LO_HI_MODE_FR = 0U; + + /* End of Outputs for SubSystem: '/not LO or HI' */ + } + + /* End of If: '/If' */ + } + + /* End of Outputs for SubSystem: '/Subsystem6' */ + + /* Outputs for Enabled SubSystem: '/Subsystem7' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU1_MODEL.FIU_AirDirectionFL_Def_Req > 0) { + /* Switch: '/Switch' incorporates: + * DataStoreWrite: '/Data Store Write1' + */ + rtDW.CCU_DEF_FR = (uint8_t)(rtDW.FIU_CCU1_MODEL.FIU_AirDirectionFL_Def_Req + <= 1); + + /* DataStoreWrite: '/Data Store Write7' incorporates: + * DataStoreWrite: '/Data Store Write1' + */ + rtDW.CCU_DEF_FL = rtDW.CCU_DEF_FR; + + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.CCU_AC_MAX = 0U; + } + + /* End of Outputs for SubSystem: '/Subsystem7' */ + + /* Outputs for Enabled SubSystem: '/Subsystem8' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU1_MODEL.FIU_AirDirectionFL_Face_Req > 0) { + /* Switch: '/Switch' incorporates: + * DataStoreWrite: '/Data Store Write8' + */ + rtDW.CCU_FACE_FL = (uint8_t) + (rtDW.FIU_CCU1_MODEL.FIU_AirDirectionFL_Face_Req <= 1); + + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.CCU_AC_MAX = 0U; + } + + /* End of Outputs for SubSystem: '/Subsystem8' */ + + /* Outputs for Enabled SubSystem: '/Subsystem9' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU1_MODEL.FIU_AirDirectionFL_Foot_Req > 0) { + /* Switch: '/Switch' incorporates: + * DataStoreWrite: '/Data Store Write9' + */ + rtDW.CCU_FOOT_FL = (uint8_t) + (rtDW.FIU_CCU1_MODEL.FIU_AirDirectionFL_Foot_Req <= 1); + + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.CCU_AC_MAX = 0U; + } + + /* End of Outputs for SubSystem: '/Subsystem9' */ + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read11' + */ + rtb_Compare_hv = (rtDW.TM_CP_model.CCPF_AcMaxButton_Stat > 0); + + /* RelationalOperator: '/FixPt Relational Operator' incorporates: + * UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + rtb_Compare_df = ((int32_t)rtb_Compare_hv > (int32_t) + rtDW.DelayInput1_DSTATE_c); + + /* Chart: '/AC_Max_Active' incorporates: + * DataStoreRead: '/Data Store Read' + */ + if (rtDW.is_active_c782_HVAC_model == 0U) { + rtDW.is_active_c782_HVAC_model = 1U; + + /* : sf_internal_predicateOutput = AC_MAX==1; */ + if (rtDW.CCU_AC_MAX == 1) { + rtDW.is_c782_HVAC_model = IN_AC_MAX_ON; + + /* : AC_Max_Active = 1; */ + rtDW.CCU_AC_MAX = 1U; + } else { + rtDW.is_c782_HVAC_model = IN_AC_MAX_OFF; + + /* : AC_Max_Active = 0; */ + rtDW.CCU_AC_MAX = 0U; + } + } else if (rtDW.is_c782_HVAC_model == IN_AC_MAX_OFF) { + rtDW.CCU_AC_MAX = 0U; + + /* : sf_internal_predicateOutput = Btn_Pulse==1; */ + if (rtb_Compare_df) { + rtDW.is_c782_HVAC_model = IN_AC_MAX_ON; + + /* : AC_Max_Active = 1; */ + rtDW.CCU_AC_MAX = 1U; + } + } else { + /* case IN_AC_MAX_ON: */ + rtDW.CCU_AC_MAX = 1U; + + /* : sf_internal_predicateOutput = Btn_Pulse==1; */ + if (rtb_Compare_df) { + rtDW.is_c782_HVAC_model = IN_AC_MAX_OFF; + + /* : AC_Max_Active = 0; */ + rtDW.CCU_AC_MAX = 0U; + } + } + + /* End of Chart: '/AC_Max_Active' */ + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read11' + */ + rtb_Compare_df = (rtDW.TM_CP_model.CCPF_DefButton_Stat > 0); + + /* RelationalOperator: '/FixPt Relational Operator' incorporates: + * UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + rtb_Compare_ls = ((int32_t)rtb_Compare_df > (int32_t) + rtDW.DelayInput1_DSTATE_m); + + /* Chart: '/Defrost_Active' */ + if (rtDW.is_active_c837_HVAC_model == 0U) { + rtDW.is_active_c837_HVAC_model = 1U; + rtDW.is_c837_HVAC_model = IN_REC_OFF; + + /* DataStoreWrite: '/Data Store Write11' */ + /* : Defrost_Active = 0; */ + rtDW.CCU_Defrost = 0U; + } else if (rtDW.is_c837_HVAC_model == IN_REC_OFF) { + /* DataStoreWrite: '/Data Store Write11' */ + rtDW.CCU_Defrost = 0U; + + /* : sf_internal_predicateOutput = Btn_Pulse==1; */ + if (rtb_Compare_ls) { + rtDW.is_c837_HVAC_model = IN_REC_ON; + + /* DataStoreWrite: '/Data Store Write11' */ + /* : Defrost_Active = 1; */ + rtDW.CCU_Defrost = 1U; + } + } else { + /* DataStoreWrite: '/Data Store Write11' */ + /* case IN_REC_ON: */ + rtDW.CCU_Defrost = 1U; + + /* : sf_internal_predicateOutput = Btn_Pulse==1; */ + if (rtb_Compare_ls) { + rtDW.is_c837_HVAC_model = IN_REC_OFF; + + /* DataStoreWrite: '/Data Store Write11' */ + /* : Defrost_Active = 0; */ + rtDW.CCU_Defrost = 0U; + } + } + + /* End of Chart: '/Defrost_Active' */ + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read11' + */ + rtb_Compare_ls = (rtDW.TM_CP_model.CCPF_RecButton_Stat > 0); + + /* RelationalOperator: '/FixPt Relational Operator' incorporates: + * UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + rtb_Compare_ne = ((int32_t)rtb_Compare_ls > (int32_t) + rtDW.DelayInput1_DSTATE_ic); + + /* Chart: '/Full_Rec_Active' */ + if (rtDW.is_active_c836_HVAC_model == 0U) { + rtDW.is_active_c836_HVAC_model = 1U; + rtDW.is_c836_HVAC_model = IN_REC_OFF; + + /* DataStoreWrite: '/Data Store Write9' */ + /* : Full_Rec_Active = 0; */ + rtDW.Full_Rec = 0U; + } else if (rtDW.is_c836_HVAC_model == IN_REC_OFF) { + /* DataStoreWrite: '/Data Store Write9' */ + rtDW.Full_Rec = 0U; + + /* : sf_internal_predicateOutput = Btn_Pulse==1; */ + if (rtb_Compare_ne) { + rtDW.is_c836_HVAC_model = IN_REC_ON; + + /* DataStoreWrite: '/Data Store Write9' */ + /* : Full_Rec_Active = 1; */ + rtDW.Full_Rec = 1U; + } + } else { + /* DataStoreWrite: '/Data Store Write9' */ + /* case IN_REC_ON: */ + rtDW.Full_Rec = 1U; + + /* : sf_internal_predicateOutput = Btn_Pulse==1; */ + if (rtb_Compare_ne) { + rtDW.is_c836_HVAC_model = IN_REC_OFF; + + /* DataStoreWrite: '/Data Store Write9' */ + /* : Full_Rec_Active = 0; */ + rtDW.Full_Rec = 0U; + } + } + + /* End of Chart: '/Full_Rec_Active' */ + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read11' + */ + rtb_Compare_ne = (rtDW.TM_CP_model.CCPF_AutoButtonL_Stat > 0); + + /* If: '/If' incorporates: + * RelationalOperator: '/FixPt Relational Operator' + * UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + if ((int32_t)rtb_Compare_ne > (int32_t)rtDW.DelayInput1_DSTATE_n) { + /* Outputs for IfAction SubSystem: '/if action' incorporates: + * ActionPort: '/Action Port' + */ + /* Outputs for IfAction SubSystem: '/sync front action1' incorporates: + * ActionPort: '/Action Port' + */ + /* Outputs for IfAction SubSystem: '/sync front action3' incorporates: + * ActionPort: '/Action Port' + */ + /* If: '/If2' incorporates: + * DataStoreRead: '/Data Store Read12' + * DataStoreWrite: '/Data Store Write13' + * DataStoreWrite: '/Data Store Write13' + */ + rtDW.CCU_MODE_FL = (uint8_t)(rtDW.CCU_MODE_FL == 0); + + /* End of Outputs for SubSystem: '/sync front action3' */ + /* End of Outputs for SubSystem: '/sync front action1' */ + /* End of Outputs for SubSystem: '/if action' */ + } + + /* End of If: '/If' */ + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read11' + */ + rtb_Compare_kb = (rtDW.TM_CP_model.CCPF_AutoButtonR_Stat > 0); + + /* If: '/If1' incorporates: + * RelationalOperator: '/FixPt Relational Operator' + * UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + if ((int32_t)rtb_Compare_kb > (int32_t)rtDW.DelayInput1_DSTATE_my) { + /* Outputs for IfAction SubSystem: '/if action1' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write1' incorporates: + * Constant: '/true' + */ + rtDW.changed_FR_params = 1U; + + /* Outputs for IfAction SubSystem: '/sync front action1' incorporates: + * ActionPort: '/Action Port' + */ + /* Outputs for IfAction SubSystem: '/sync front action3' incorporates: + * ActionPort: '/Action Port' + */ + /* If: '/If2' incorporates: + * DataStoreRead: '/Data Store Read12' + * DataStoreWrite: '/Data Store Write13' + * DataStoreWrite: '/Data Store Write13' + */ + rtDW.CCU_MODE_FR = (uint8_t)(rtDW.CCU_MODE_FR == 0); + + /* End of Outputs for SubSystem: '/sync front action3' */ + /* End of Outputs for SubSystem: '/sync front action1' */ + /* End of Outputs for SubSystem: '/if action1' */ + } + + /* End of If: '/If1' */ + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read11' + */ + rtb_Compare_l = (rtDW.TM_CP_model.CCPR_AutoButtonL_Stat > 0); + + /* If: '/If2' incorporates: + * RelationalOperator: '/FixPt Relational Operator' + * UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + if ((int32_t)rtb_Compare_l > (int32_t)rtDW.DelayInput1_DSTATE_a) { + /* Outputs for IfAction SubSystem: '/if action2' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/true' + */ + rtDW.changed_RL_params = 1U; + + /* Outputs for IfAction SubSystem: '/sync front action1' incorporates: + * ActionPort: '/Action Port' + */ + /* Outputs for IfAction SubSystem: '/sync front action3' incorporates: + * ActionPort: '/Action Port' + */ + /* If: '/If2' incorporates: + * DataStoreRead: '/Data Store Read12' + * DataStoreWrite: '/Data Store Write13' + * DataStoreWrite: '/Data Store Write13' + */ + rtDW.CCU_MODE_RL = (uint8_t)(rtDW.CCU_MODE_RL == 0); + + /* End of Outputs for SubSystem: '/sync front action3' */ + /* End of Outputs for SubSystem: '/sync front action1' */ + /* End of Outputs for SubSystem: '/if action2' */ + } + + /* End of If: '/If2' */ + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read11' + */ + rtb_Compare_g1 = (rtDW.TM_CP_model.CCPR_AutoButtonR_Stat > 0); + + /* If: '/If4' incorporates: + * RelationalOperator: '/FixPt Relational Operator' + * UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + if ((int32_t)rtb_Compare_g1 > (int32_t)rtDW.DelayInput1_DSTATE_o) { + /* Outputs for IfAction SubSystem: '/if action4' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/true' + */ + rtDW.changed_RR_params = 1U; + + /* Outputs for IfAction SubSystem: '/sync front action1' incorporates: + * ActionPort: '/Action Port' + */ + /* Outputs for IfAction SubSystem: '/sync front action3' incorporates: + * ActionPort: '/Action Port' + */ + /* If: '/If2' incorporates: + * DataStoreRead: '/Data Store Read12' + * DataStoreWrite: '/Data Store Write13' + * DataStoreWrite: '/Data Store Write13' + */ + rtDW.CCU_MODE_RR = (uint8_t)(rtDW.CCU_MODE_RR == 0); + + /* End of Outputs for SubSystem: '/sync front action3' */ + /* End of Outputs for SubSystem: '/sync front action1' */ + /* End of Outputs for SubSystem: '/if action4' */ + } + + /* End of If: '/If4' */ + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read11' + */ + rtb_Compare_il = (rtDW.TM_CP_model.CCPF_TempToggleL_Stat > 0); + + /* If: '/If1' incorporates: + * RelationalOperator: '/FixPt Relational Operator' + * UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + if ((int32_t)rtb_Compare_il > (int32_t)rtDW.DelayInput1_DSTATE_od) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem' incorporates: + * ActionPort: '/Action Port' + */ + /* If: '/If5' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read11' + * DataStoreRead: '/Data Store Read12' + * Saturate: '/Saturation1' + * Sum: '/Sum' + */ + if ((rtDW.TM_CP_model.CCPF_TempToggleL_Stat == 1) || + (rtDW.TM_CP_model.CCPF_TempToggleL_Stat == 3)) { + /* Outputs for IfAction SubSystem: '/temp up' incorporates: + * ActionPort: '/Action Port' + */ + /* Saturate: '/Saturation1' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read12' + * Sum: '/Add' + */ + if ((uint16_t)(rtDW.CCU_SET_FL + 5U) > 305) { + /* DataTypeConversion: '/Data Type Conversion1' */ + rtDW.CCU_SET_FL = 305U; + } else if ((uint16_t)(rtDW.CCU_SET_FL + 5U) < 155) { + /* DataTypeConversion: '/Data Type Conversion1' */ + rtDW.CCU_SET_FL = 155U; + } else { + /* DataTypeConversion: '/Data Type Conversion1' */ + rtDW.CCU_SET_FL = (uint16_t)(rtDW.CCU_SET_FL + 5U); + } + + /* End of Saturate: '/Saturation1' */ + + /* If: '/If' incorporates: + * DataStoreWrite: '/Data Store Write13' + */ + if (rtDW.CCU_SET_FL < 160) { + /* Outputs for IfAction SubSystem: '/LO mode' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/LOW' + */ + rtDW.LO_HI_MODE_FL = 1U; + + /* End of Outputs for SubSystem: '/LO mode' */ + } else if (rtDW.CCU_SET_FL > 290) { + /* Outputs for IfAction SubSystem: '/HI mode' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/HI' + */ + rtDW.LO_HI_MODE_FL = 2U; + + /* End of Outputs for SubSystem: '/HI mode' */ + } else { + /* Outputs for IfAction SubSystem: '/not LO or HI' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/not LO or HI' + */ + rtDW.LO_HI_MODE_FL = 0U; + + /* End of Outputs for SubSystem: '/not LO or HI' */ + } + + /* End of If: '/If' */ + /* End of Outputs for SubSystem: '/temp up' */ + } else { + /* Outputs for IfAction SubSystem: '/temp down' incorporates: + * ActionPort: '/Action Port' + */ + if ((uint16_t)(rtDW.CCU_SET_FL - 5) > 305) { + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Saturate: '/Saturation1' + */ + rtDW.CCU_SET_FL = 305U; + } else if ((uint16_t)(rtDW.CCU_SET_FL - 5) < 155) { + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Saturate: '/Saturation1' + */ + rtDW.CCU_SET_FL = 155U; + } else { + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read12' + * Saturate: '/Saturation1' + * Sum: '/Sum' + */ + rtDW.CCU_SET_FL = (uint16_t)(rtDW.CCU_SET_FL - 5); + } + + /* If: '/If' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read12' + * DataStoreWrite: '/Data Store Write13' + * Saturate: '/Saturation1' + * Sum: '/Sum' + */ + if (rtDW.CCU_SET_FL < 160) { + /* Outputs for IfAction SubSystem: '/LO mode' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/LOW' + */ + rtDW.LO_HI_MODE_FL = 1U; + + /* End of Outputs for SubSystem: '/LO mode' */ + } else if (rtDW.CCU_SET_FL > 290) { + /* Outputs for IfAction SubSystem: '/HI mode' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/HI' + */ + rtDW.LO_HI_MODE_FL = 2U; + + /* End of Outputs for SubSystem: '/HI mode' */ + } else { + /* Outputs for IfAction SubSystem: '/not LO or HI' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/not LO or HI' + */ + rtDW.LO_HI_MODE_FL = 0U; + + /* End of Outputs for SubSystem: '/not LO or HI' */ + } + + /* End of If: '/If' */ + /* End of Outputs for SubSystem: '/temp down' */ + } + + /* End of If: '/If5' */ + /* End of Outputs for SubSystem: '/If Action Subsystem' */ + } + + /* End of If: '/If1' */ + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read11' + */ + rtb_Compare_ok = (rtDW.TM_CP_model.CCPF_TempToggleR_Stat > 0); + + /* If: '/If1' incorporates: + * RelationalOperator: '/FixPt Relational Operator' + * UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + if ((int32_t)rtb_Compare_ok > (int32_t)rtDW.DelayInput1_DSTATE_j) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write1' incorporates: + * Constant: '/true' + */ + rtDW.changed_FR_params = 1U; + + /* If: '/If5' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read11' + * DataStoreRead: '/Data Store Read12' + * Saturate: '/Saturation1' + * Sum: '/Sum' + */ + if ((rtDW.TM_CP_model.CCPF_TempToggleR_Stat == 1) || + (rtDW.TM_CP_model.CCPF_TempToggleR_Stat == 3)) { + /* Outputs for IfAction SubSystem: '/temp up' incorporates: + * ActionPort: '/Action Port' + */ + /* Saturate: '/Saturation1' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read12' + * Sum: '/Add' + */ + if ((uint16_t)(rtDW.CCU_SET_FR + 5U) > 305) { + /* DataTypeConversion: '/Data Type Conversion1' */ + rtDW.CCU_SET_FR = 305U; + } else if ((uint16_t)(rtDW.CCU_SET_FR + 5U) < 155) { + /* DataTypeConversion: '/Data Type Conversion1' */ + rtDW.CCU_SET_FR = 155U; + } else { + /* DataTypeConversion: '/Data Type Conversion1' */ + rtDW.CCU_SET_FR = (uint16_t)(rtDW.CCU_SET_FR + 5U); + } + + /* End of Saturate: '/Saturation1' */ + + /* If: '/If' incorporates: + * DataStoreWrite: '/Data Store Write13' + */ + if (rtDW.CCU_SET_FR < 160) { + /* Outputs for IfAction SubSystem: '/LO mode' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/LOW' + */ + rtDW.LO_HI_MODE_FR = 1U; + + /* End of Outputs for SubSystem: '/LO mode' */ + } else if (rtDW.CCU_SET_FR > 290) { + /* Outputs for IfAction SubSystem: '/HI mode' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/HI' + */ + rtDW.LO_HI_MODE_FR = 2U; + + /* End of Outputs for SubSystem: '/HI mode' */ + } else { + /* Outputs for IfAction SubSystem: '/not LO or HI' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/not LO or HI' + */ + rtDW.LO_HI_MODE_FR = 0U; + + /* End of Outputs for SubSystem: '/not LO or HI' */ + } + + /* End of If: '/If' */ + /* End of Outputs for SubSystem: '/temp up' */ + } else { + /* Outputs for IfAction SubSystem: '/temp down' incorporates: + * ActionPort: '/Action Port' + */ + if ((uint16_t)(rtDW.CCU_SET_FR - 5) > 305) { + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Saturate: '/Saturation1' + */ + rtDW.CCU_SET_FR = 305U; + } else if ((uint16_t)(rtDW.CCU_SET_FR - 5) < 155) { + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Saturate: '/Saturation1' + */ + rtDW.CCU_SET_FR = 155U; + } else { + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read12' + * Saturate: '/Saturation1' + * Sum: '/Sum' + */ + rtDW.CCU_SET_FR = (uint16_t)(rtDW.CCU_SET_FR - 5); + } + + /* If: '/If' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read12' + * DataStoreWrite: '/Data Store Write13' + * Saturate: '/Saturation1' + * Sum: '/Sum' + */ + if (rtDW.CCU_SET_FR < 160) { + /* Outputs for IfAction SubSystem: '/LO mode' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/LOW' + */ + rtDW.LO_HI_MODE_FR = 1U; + + /* End of Outputs for SubSystem: '/LO mode' */ + } else if (rtDW.CCU_SET_FR > 290) { + /* Outputs for IfAction SubSystem: '/HI mode' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/HI' + */ + rtDW.LO_HI_MODE_FR = 2U; + + /* End of Outputs for SubSystem: '/HI mode' */ + } else { + /* Outputs for IfAction SubSystem: '/not LO or HI' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/not LO or HI' + */ + rtDW.LO_HI_MODE_FR = 0U; + + /* End of Outputs for SubSystem: '/not LO or HI' */ + } + + /* End of If: '/If' */ + /* End of Outputs for SubSystem: '/temp down' */ + } + + /* End of If: '/If5' */ + /* End of Outputs for SubSystem: '/If Action Subsystem' */ + } + + /* End of If: '/If1' */ + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read11' + */ + rtb_Compare_ja = (rtDW.TM_CP_model.CCPR_TempToggleL_Stat > 0); + + /* If: '/If1' incorporates: + * RelationalOperator: '/FixPt Relational Operator' + * UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + if ((int32_t)rtb_Compare_ja > (int32_t)rtDW.DelayInput1_DSTATE_f) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/true' + */ + rtDW.changed_RL_params = 1U; + + /* If: '/If5' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read11' + * DataStoreRead: '/Data Store Read12' + * Saturate: '/Saturation1' + * Sum: '/Sum' + */ + if ((rtDW.TM_CP_model.CCPR_TempToggleL_Stat == 1) || + (rtDW.TM_CP_model.CCPR_TempToggleL_Stat == 3)) { + /* Outputs for IfAction SubSystem: '/temp up' incorporates: + * ActionPort: '/Action Port' + */ + /* Saturate: '/Saturation1' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read12' + * Sum: '/Add' + */ + if ((uint16_t)(rtDW.CCU_SET_RL + 5U) > 305) { + /* DataTypeConversion: '/Data Type Conversion1' */ + rtDW.CCU_SET_RL = 305U; + } else if ((uint16_t)(rtDW.CCU_SET_RL + 5U) < 155) { + /* DataTypeConversion: '/Data Type Conversion1' */ + rtDW.CCU_SET_RL = 155U; + } else { + /* DataTypeConversion: '/Data Type Conversion1' */ + rtDW.CCU_SET_RL = (uint16_t)(rtDW.CCU_SET_RL + 5U); + } + + /* End of Saturate: '/Saturation1' */ + + /* If: '/If' incorporates: + * DataStoreWrite: '/Data Store Write13' + */ + if (rtDW.CCU_SET_RL < 160) { + /* Outputs for IfAction SubSystem: '/LO mode' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/LOW' + */ + rtDW.LO_HI_MODE_RL = 1U; + + /* End of Outputs for SubSystem: '/LO mode' */ + } else if (rtDW.CCU_SET_RL > 290) { + /* Outputs for IfAction SubSystem: '/HI mode' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/HI' + */ + rtDW.LO_HI_MODE_RL = 2U; + + /* End of Outputs for SubSystem: '/HI mode' */ + } else { + /* Outputs for IfAction SubSystem: '/not LO or HI' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/not LO or HI' + */ + rtDW.LO_HI_MODE_RL = 0U; + + /* End of Outputs for SubSystem: '/not LO or HI' */ + } + + /* End of If: '/If' */ + /* End of Outputs for SubSystem: '/temp up' */ + } else { + /* Outputs for IfAction SubSystem: '/temp down' incorporates: + * ActionPort: '/Action Port' + */ + if ((uint16_t)(rtDW.CCU_SET_RL - 5) > 305) { + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Saturate: '/Saturation1' + */ + rtDW.CCU_SET_RL = 305U; + } else if ((uint16_t)(rtDW.CCU_SET_RL - 5) < 155) { + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Saturate: '/Saturation1' + */ + rtDW.CCU_SET_RL = 155U; + } else { + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read12' + * Saturate: '/Saturation1' + * Sum: '/Sum' + */ + rtDW.CCU_SET_RL = (uint16_t)(rtDW.CCU_SET_RL - 5); + } + + /* If: '/If' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read12' + * DataStoreWrite: '/Data Store Write13' + * Saturate: '/Saturation1' + * Sum: '/Sum' + */ + if (rtDW.CCU_SET_RL < 160) { + /* Outputs for IfAction SubSystem: '/LO mode' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/LOW' + */ + rtDW.LO_HI_MODE_RL = 1U; + + /* End of Outputs for SubSystem: '/LO mode' */ + } else if (rtDW.CCU_SET_RL > 290) { + /* Outputs for IfAction SubSystem: '/HI mode' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/HI' + */ + rtDW.LO_HI_MODE_RL = 2U; + + /* End of Outputs for SubSystem: '/HI mode' */ + } else { + /* Outputs for IfAction SubSystem: '/not LO or HI' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/not LO or HI' + */ + rtDW.LO_HI_MODE_RL = 0U; + + /* End of Outputs for SubSystem: '/not LO or HI' */ + } + + /* End of If: '/If' */ + /* End of Outputs for SubSystem: '/temp down' */ + } + + /* End of If: '/If5' */ + /* End of Outputs for SubSystem: '/If Action Subsystem' */ + } + + /* End of If: '/If1' */ + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read11' + */ + rtb_Compare_cc = (rtDW.TM_CP_model.CCPR_TempToggleR_Stat > 0); + + /* If: '/If1' incorporates: + * RelationalOperator: '/FixPt Relational Operator' + * UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + if ((int32_t)rtb_Compare_cc > (int32_t)rtDW.DelayInput1_DSTATE_kz) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/true' + */ + rtDW.changed_RR_params = 1U; + + /* If: '/If5' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read11' + * DataStoreRead: '/Data Store Read12' + * Saturate: '/Saturation1' + * Sum: '/Sum' + */ + if ((rtDW.TM_CP_model.CCPR_TempToggleR_Stat == 1) || + (rtDW.TM_CP_model.CCPR_TempToggleR_Stat == 3)) { + /* Outputs for IfAction SubSystem: '/temp up' incorporates: + * ActionPort: '/Action Port' + */ + /* Saturate: '/Saturation1' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read12' + * Sum: '/Add' + */ + if ((uint16_t)(rtDW.CCU_SET_RR + 5U) > 305) { + /* DataTypeConversion: '/Data Type Conversion1' */ + rtDW.CCU_SET_RR = 305U; + } else if ((uint16_t)(rtDW.CCU_SET_RR + 5U) < 155) { + /* DataTypeConversion: '/Data Type Conversion1' */ + rtDW.CCU_SET_RR = 155U; + } else { + /* DataTypeConversion: '/Data Type Conversion1' */ + rtDW.CCU_SET_RR = (uint16_t)(rtDW.CCU_SET_RR + 5U); + } + + /* End of Saturate: '/Saturation1' */ + + /* If: '/If' incorporates: + * DataStoreWrite: '/Data Store Write13' + */ + if (rtDW.CCU_SET_RR < 160) { + /* Outputs for IfAction SubSystem: '/LO mode' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/LOW' + */ + rtDW.LO_HI_MODE_RR = 1U; + + /* End of Outputs for SubSystem: '/LO mode' */ + } else if (rtDW.CCU_SET_RR > 290) { + /* Outputs for IfAction SubSystem: '/HI mode' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/HI' + */ + rtDW.LO_HI_MODE_RR = 2U; + + /* End of Outputs for SubSystem: '/HI mode' */ + } else { + /* Outputs for IfAction SubSystem: '/not LO or HI' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/not LO or HI' + */ + rtDW.LO_HI_MODE_RR = 0U; + + /* End of Outputs for SubSystem: '/not LO or HI' */ + } + + /* End of If: '/If' */ + /* End of Outputs for SubSystem: '/temp up' */ + } else { + /* Outputs for IfAction SubSystem: '/temp down' incorporates: + * ActionPort: '/Action Port' + */ + if ((uint16_t)(rtDW.CCU_SET_RR - 5) > 305) { + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Saturate: '/Saturation1' + */ + rtDW.CCU_SET_RR = 305U; + } else if ((uint16_t)(rtDW.CCU_SET_RR - 5) < 155) { + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Saturate: '/Saturation1' + */ + rtDW.CCU_SET_RR = 155U; + } else { + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read12' + * Saturate: '/Saturation1' + * Sum: '/Sum' + */ + rtDW.CCU_SET_RR = (uint16_t)(rtDW.CCU_SET_RR - 5); + } + + /* If: '/If' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read12' + * DataStoreWrite: '/Data Store Write13' + * Saturate: '/Saturation1' + * Sum: '/Sum' + */ + if (rtDW.CCU_SET_RR < 160) { + /* Outputs for IfAction SubSystem: '/LO mode' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/LOW' + */ + rtDW.LO_HI_MODE_RR = 1U; + + /* End of Outputs for SubSystem: '/LO mode' */ + } else if (rtDW.CCU_SET_RR > 290) { + /* Outputs for IfAction SubSystem: '/HI mode' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/HI' + */ + rtDW.LO_HI_MODE_RR = 2U; + + /* End of Outputs for SubSystem: '/HI mode' */ + } else { + /* Outputs for IfAction SubSystem: '/not LO or HI' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/not LO or HI' + */ + rtDW.LO_HI_MODE_RR = 0U; + + /* End of Outputs for SubSystem: '/not LO or HI' */ + } + + /* End of If: '/If' */ + /* End of Outputs for SubSystem: '/temp down' */ + } + + /* End of If: '/If5' */ + /* End of Outputs for SubSystem: '/If Action Subsystem' */ + } + + /* End of If: '/If1' */ + + /* Outputs for Enabled SubSystem: '/Subsystem2' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU2_MODEL.FIU_TargetTempRL_Val_ro > 0) { + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Bias: '/Bias' + * DataTypeConversion: '/Data Type Conversion' + * Gain: '/Gain' + * Gain: '/Gain1' + */ + rtDW.CCU_SET_RL = (uint16_t)((0.5 * (double) + rtDW.FIU_CCU2_MODEL.FIU_TargetTempRL_Val_ro + 15.5) * 10.0); + + /* Saturate: '/Saturation' */ + if (rtDW.CCU_SET_RL > 305) { + /* DataTypeConversion: '/Data Type Conversion1' */ + rtDW.CCU_SET_RL = 305U; + } + + /* End of Saturate: '/Saturation' */ + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/true' + */ + rtDW.changed_RL_params = 1U; + + /* If: '/If' incorporates: + * DataStoreWrite: '/Data Store Write1' + */ + if (rtDW.CCU_SET_RL < 165) { + /* Outputs for IfAction SubSystem: '/LO mode' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/LOW' + */ + rtDW.LO_HI_MODE_RL = 1U; + + /* End of Outputs for SubSystem: '/LO mode' */ + } else if (rtDW.CCU_SET_RL > 295) { + /* Outputs for IfAction SubSystem: '/HI mode' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/HI' + */ + rtDW.LO_HI_MODE_RL = 2U; + + /* End of Outputs for SubSystem: '/HI mode' */ + } else { + /* Outputs for IfAction SubSystem: '/not LO or HI' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/not LO or HI' + */ + rtDW.LO_HI_MODE_RL = 0U; + + /* End of Outputs for SubSystem: '/not LO or HI' */ + } + + /* End of If: '/If' */ + } + + /* End of Outputs for SubSystem: '/Subsystem2' */ + + /* Outputs for Enabled SubSystem: '/Subsystem25' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU2_MODEL.FIU_FootTempCorRL_Req > 0) { + /* Sum: '/Plus' incorporates: + * Constant: '/Constant' + * DataStoreWrite: '/Data Store Write1' + */ + rtDW.CCU_SET_FOOT_FR = (uint8_t)(rtDW.FIU_CCU2_MODEL.FIU_FootTempCorRL_Req + - 1); + } + + /* End of Outputs for SubSystem: '/Subsystem25' */ + + /* Outputs for Enabled SubSystem: '/Subsystem26' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU2_MODEL.FIU_FootTempCorRR_Req > 0) { + /* Sum: '/Plus' incorporates: + * Constant: '/Constant' + * DataStoreWrite: '/Data Store Write1' + */ + rtDW.CCU_SET_FOOT_RR = (uint8_t)(rtDW.FIU_CCU2_MODEL.FIU_FootTempCorRR_Req + - 1); + } + + /* End of Outputs for SubSystem: '/Subsystem26' */ + + /* Outputs for Enabled SubSystem: '/Subsystem27' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU2_MODEL.FIU_CCmodeRL_Req > 0) { + /* Switch: '/Switch' incorporates: + * DataStoreWrite: '/Data Store Write1' + */ + rtDW.CCU_MODE_RL = (uint8_t)(rtDW.FIU_CCU2_MODEL.FIU_CCmodeRL_Req > 1); + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/true' + */ + rtDW.changed_RL_params = 1U; + } + + /* End of Outputs for SubSystem: '/Subsystem27' */ + + /* Outputs for Enabled SubSystem: '/Subsystem28' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU2_MODEL.FIU_AirDirectionRL_Def_Req > 0) { + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/true' + */ + rtDW.changed_RL_params = 1U; + } + + /* End of Outputs for SubSystem: '/Subsystem28' */ + + /* Outputs for Enabled SubSystem: '/Subsystem29' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU2_MODEL.FIU_AirDirectionRL_Face_Req > 0) { + /* Switch: '/Switch' incorporates: + * DataStoreWrite: '/Data Store Write1' + */ + rtDW.CCU_FACE_RL = (uint8_t) + (rtDW.FIU_CCU2_MODEL.FIU_AirDirectionRL_Face_Req <= 1); + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/true' + */ + rtDW.changed_RL_params = 1U; + } + + /* End of Outputs for SubSystem: '/Subsystem29' */ + + /* Outputs for Enabled SubSystem: '/Subsystem3' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU2_MODEL.FIU_TargetTempRR_Val_ro > 0) { + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Bias: '/Bias' + * DataTypeConversion: '/Data Type Conversion' + * Gain: '/Gain' + * Gain: '/Gain1' + */ + rtDW.CCU_SET_RR = (uint16_t)((0.5 * (double) + rtDW.FIU_CCU2_MODEL.FIU_TargetTempRR_Val_ro + 15.5) * 10.0); + + /* Saturate: '/Saturation' */ + if (rtDW.CCU_SET_RR > 305) { + /* DataTypeConversion: '/Data Type Conversion1' */ + rtDW.CCU_SET_RR = 305U; + } + + /* End of Saturate: '/Saturation' */ + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/true' + */ + rtDW.changed_RR_params = 1U; + + /* If: '/If' incorporates: + * DataStoreWrite: '/Data Store Write1' + */ + if (rtDW.CCU_SET_RR < 165) { + /* Outputs for IfAction SubSystem: '/LO mode' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/LOW' + */ + rtDW.LO_HI_MODE_RR = 1U; + + /* End of Outputs for SubSystem: '/LO mode' */ + } else if (rtDW.CCU_SET_RR > 295) { + /* Outputs for IfAction SubSystem: '/HI mode' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/HI' + */ + rtDW.LO_HI_MODE_RR = 2U; + + /* End of Outputs for SubSystem: '/HI mode' */ + } else { + /* Outputs for IfAction SubSystem: '/not LO or HI' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/not LO or HI' + */ + rtDW.LO_HI_MODE_RR = 0U; + + /* End of Outputs for SubSystem: '/not LO or HI' */ + } + + /* End of If: '/If' */ + } + + /* End of Outputs for SubSystem: '/Subsystem3' */ + + /* Outputs for Enabled SubSystem: '/Subsystem30' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU2_MODEL.FIU_AirDirectionRL_Foot_Req > 0) { + /* Switch: '/Switch' incorporates: + * DataStoreWrite: '/Data Store Write1' + */ + rtDW.CCU_FOOT_RL = (uint8_t) + (rtDW.FIU_CCU2_MODEL.FIU_AirDirectionRL_Foot_Req <= 1); + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/true' + */ + rtDW.changed_RL_params = 1U; + } + + /* End of Outputs for SubSystem: '/Subsystem30' */ + + /* Outputs for Enabled SubSystem: '/Subsystem31' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU2_MODEL.FIU_CCmodeRR_Req > 0) { + /* Switch: '/Switch' incorporates: + * DataStoreWrite: '/Data Store Write1' + */ + rtDW.CCU_MODE_RR = (uint8_t)(rtDW.FIU_CCU2_MODEL.FIU_CCmodeRR_Req > 1); + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/true' + */ + rtDW.changed_RR_params = 1U; + } + + /* End of Outputs for SubSystem: '/Subsystem31' */ + + /* Outputs for Enabled SubSystem: '/Subsystem32' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU2_MODEL.FIU_AirDirectionRR_Def_Req > 0) { + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/true' + */ + rtDW.changed_RR_params = 1U; + } + + /* End of Outputs for SubSystem: '/Subsystem32' */ + + /* Outputs for Enabled SubSystem: '/Subsystem33' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU2_MODEL.FIU_AirDirectionRR_Face_Req > 0) { + /* Switch: '/Switch' incorporates: + * DataStoreWrite: '/Data Store Write1' + */ + rtDW.CCU_FACE_RR = (uint8_t) + (rtDW.FIU_CCU2_MODEL.FIU_AirDirectionRR_Face_Req <= 1); + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/true' + */ + rtDW.changed_RR_params = 1U; + } + + /* End of Outputs for SubSystem: '/Subsystem33' */ + + /* Outputs for Enabled SubSystem: '/Subsystem34' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU2_MODEL.FIU_AirDirectionRR_Foot_Req > 0) { + /* Switch: '/Switch' incorporates: + * DataStoreWrite: '/Data Store Write1' + */ + rtDW.CCU_FOOT_RR = (uint8_t) + (rtDW.FIU_CCU2_MODEL.FIU_AirDirectionRR_Foot_Req <= 1); + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/true' + */ + rtDW.changed_RR_params = 1U; + } + + /* End of Outputs for SubSystem: '/Subsystem34' */ + + /* Outputs for Enabled SubSystem: '/Subsystem35' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU2_MODEL.FIU_BlowerSpeedRL_Req > 0) { + /* Switch: '/Switch5' incorporates: + * Constant: '/blower off' + * DataStoreWrite: '/Data Store Write1' + */ + if (rtDW.FIU_CCU2_MODEL.FIU_BlowerSpeedRL_Req > 7) { + rtDW.CCU_BLOWERS_RL = 0U; + } else { + rtDW.CCU_BLOWERS_RL = rtDW.FIU_CCU2_MODEL.FIU_BlowerSpeedRL_Req; + } + + /* End of Switch: '/Switch5' */ + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/true' + */ + rtDW.changed_RL_params = 1U; + } + + /* End of Outputs for SubSystem: '/Subsystem35' */ + + /* Outputs for Enabled SubSystem: '/Subsystem36' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU2_MODEL.FIU_BlowerSpeedRR_Req > 0) { + /* Switch: '/Switch5' incorporates: + * Constant: '/blower off' + * DataStoreWrite: '/Data Store Write1' + */ + if (rtDW.FIU_CCU2_MODEL.FIU_BlowerSpeedRR_Req > 7) { + rtDW.CCU_BLOWERS_RR = 0U; + } else { + rtDW.CCU_BLOWERS_RR = rtDW.FIU_CCU2_MODEL.FIU_BlowerSpeedRR_Req; + } + + /* End of Switch: '/Switch5' */ + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/true' + */ + rtDW.changed_RR_params = 1U; + } + + /* End of Outputs for SubSystem: '/Subsystem36' */ + + /* Outputs for Enabled SubSystem: '/Subsystem37' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU2_MODEL.FIU_CCautoModeRL_Req > 0) { + /* DataStoreWrite: '/Data Store Write1' */ + rtDW.CCU_AUTOMODE_RL = rtDW.FIU_CCU2_MODEL.FIU_CCautoModeRL_Req; + } + + /* End of Outputs for SubSystem: '/Subsystem37' */ + + /* Outputs for Enabled SubSystem: '/Subsystem38' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU2_MODEL.FIU_CCautoModeRR_Req > 0) { + /* DataStoreWrite: '/Data Store Write1' */ + rtDW.CCU_AUTOMODE_RR = rtDW.FIU_CCU2_MODEL.FIU_CCautoModeRR_Req; + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/true' + */ + rtDW.changed_RR_params = 1U; + } + + /* End of Outputs for SubSystem: '/Subsystem38' */ + + /* Outputs for Enabled SubSystem: '/Subsystem39' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU2_MODEL.FIU_DeflectorSwRLB_Req > 0) { + /* Switch: '/Switch' incorporates: + * Constant: '/no LED' + * DataStoreWrite: '/Data Store Write1' + */ + if (rtDW.FIU_CCU2_MODEL.FIU_DeflectorSwRLB_Req > 3) { + rtDW.DRS_SRL = 0U; + } else { + rtDW.DRS_SRL = rtDW.FIU_CCU2_MODEL.FIU_DeflectorSwRLB_Req; + } + + /* End of Switch: '/Switch' */ + } + + /* End of Outputs for SubSystem: '/Subsystem39' */ + + /* Outputs for Enabled SubSystem: '/Subsystem40' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU2_MODEL.FIU_DeflectorSwFCL_Req > 0) { + /* Switch: '/Switch' incorporates: + * Constant: '/no LED' + * DataStoreWrite: '/Data Store Write1' + */ + if (rtDW.FIU_CCU2_MODEL.FIU_DeflectorSwFCL_Req > 3) { + rtDW.DRS_CRL = 0U; + } else { + rtDW.DRS_CRL = rtDW.FIU_CCU2_MODEL.FIU_DeflectorSwFCL_Req; + } + + /* End of Switch: '/Switch' */ + } + + /* End of Outputs for SubSystem: '/Subsystem40' */ + + /* Outputs for Enabled SubSystem: '/Subsystem41' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU2_MODEL.FIU_ACrearOFF_Req > 0) { + /* Switch: '/Switch' incorporates: + * DataStoreWrite: '/Data Store Write1' + */ + rtDW.CCU_AC_REAR = (uint8_t)(rtDW.FIU_CCU2_MODEL.FIU_ACrearOFF_Req <= 1); + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/true' + */ + rtDW.changed_RL_params = 1U; + } + + /* End of Outputs for SubSystem: '/Subsystem41' */ + + /* Outputs for Enabled SubSystem: '/Subsystem42' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU2_MODEL.FIU_DeflectorSwFCR_Req > 0) { + /* Switch: '/Switch' incorporates: + * Constant: '/no LED' + * DataStoreWrite: '/Data Store Write1' + */ + if (rtDW.FIU_CCU2_MODEL.FIU_DeflectorSwFCR_Req > 3) { + rtDW.DRS_CRR = 0U; + } else { + rtDW.DRS_CRR = rtDW.FIU_CCU2_MODEL.FIU_DeflectorSwFCR_Req; + } + + /* End of Switch: '/Switch' */ + } + + /* End of Outputs for SubSystem: '/Subsystem42' */ + + /* Outputs for Enabled SubSystem: '/Subsystem43' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU2_MODEL.FIU_DeflectorSwRRB_Req > 0) { + /* Switch: '/Switch' incorporates: + * Constant: '/no LED' + * DataStoreWrite: '/Data Store Write1' + */ + if (rtDW.FIU_CCU2_MODEL.FIU_DeflectorSwRRB_Req > 3) { + rtDW.DRS_SRR = 0U; + } else { + rtDW.DRS_SRR = rtDW.FIU_CCU2_MODEL.FIU_DeflectorSwRRB_Req; + } + + /* End of Switch: '/Switch' */ + } + + /* End of Outputs for SubSystem: '/Subsystem43' */ + + /* Outputs for Enabled SubSystem: '/Subsystem44' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU2_MODEL.FIU_RearZoneSync_Req > 0) { + /* If: '/If' */ + if (rtDW.FIU_CCU2_MODEL.FIU_RearZoneSync_Req == 1) { + /* Outputs for IfAction SubSystem: '/sync rear action' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write18' incorporates: + * Constant: '/on' + */ + rtDW.enable_rear_sync = 1U; + + /* MATLAB Function: '/logger' */ + /* : fprintf('Logger CAN INPUT -> sync rear ON') */ + printf("Logger CAN INPUT -> sync rear ON"); + fflush(stdout); + + /* End of Outputs for SubSystem: '/sync rear action' */ + } else if (rtDW.FIU_CCU2_MODEL.FIU_RearZoneSync_Req == 2) { + /* Outputs for IfAction SubSystem: '/sync off rear action' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write18' incorporates: + * Constant: '/on' + */ + rtDW.disable_rear_sync = 1U; + + /* MATLAB Function: '/logger' */ + /* : fprintf('Logger CAN INPUT -> sync rear OFF') */ + printf("Logger CAN INPUT -> sync rear OFF"); + fflush(stdout); + + /* End of Outputs for SubSystem: '/sync off rear action' */ + } + + /* End of If: '/If' */ + } + + /* End of Outputs for SubSystem: '/Subsystem44' */ + + /* Outputs for Enabled SubSystem: '/Subsystem52' incorporates: + * EnablePort: '/Enable' + */ + if (rtDW.FIU_CCU3_MODEL.FIU_Ionization_Req > 0) { + /* Switch: '/Switch' incorporates: + * DataStoreWrite: '/Data Store Write1' + */ + rtDW.CCU_Ionization = (uint8_t)(rtDW.FIU_CCU3_MODEL.FIU_Ionization_Req <= + 1); + } + + /* End of Outputs for SubSystem: '/Subsystem52' */ + + /* Update for UnitDelay: '/Delay Input1' incorporates: + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read3' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + rtDW.DelayInput1_DSTATE_c = rtb_Compare_hv; + + /* Update for UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + rtDW.DelayInput1_DSTATE_m = rtb_Compare_df; + + /* Update for UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + rtDW.DelayInput1_DSTATE_ic = rtb_Compare_ls; + + /* Update for UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + rtDW.DelayInput1_DSTATE_n = rtb_Compare_ne; + + /* Update for UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + rtDW.DelayInput1_DSTATE_my = rtb_Compare_kb; + + /* Update for UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + rtDW.DelayInput1_DSTATE_a = rtb_Compare_l; + + /* Update for UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + rtDW.DelayInput1_DSTATE_o = rtb_Compare_g1; + + /* Update for UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + rtDW.DelayInput1_DSTATE_od = rtb_Compare_il; + + /* Update for UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + rtDW.DelayInput1_DSTATE_j = rtb_Compare_ok; + + /* Update for UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + rtDW.DelayInput1_DSTATE_f = rtb_Compare_ja; + + /* Update for UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + rtDW.DelayInput1_DSTATE_kz = rtb_Compare_cc; + } + + /* End of DataStoreRead: '/Data Store Read1' */ + /* End of Outputs for SubSystem: '/Subsystem53' */ + + /* Outputs for Enabled SubSystem: '/Sleep_mode' incorporates: + * EnablePort: '/Enable' + */ + /* DataStoreRead: '/Data Store Read13' */ + if (rtDW.sleep_model > 0) { + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataStoreRead: '/Data Store Read' + */ + rtDW.CCU_MODE_FL = rtDW.CCU_STAT1_WAKEUP_MODEL.CCU_ModeFL_Stat; + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataStoreRead: '/Data Store Read' + */ + rtDW.CCU_MODE_FR = rtDW.CCU_STAT1_WAKEUP_MODEL.CCU_ModeFR_Stat; + + /* DataStoreWrite: '/Data Store Write10' incorporates: + * DataStoreRead: '/Data Store Read' + */ + rtDW.CCU_FACE_RR = rtDW.CCU_STAT1_WAKEUP_MODEL.CCU_AirDirectionRR_Face_Stat; + + /* DataStoreWrite: '/Data Store Write11' incorporates: + * DataStoreRead: '/Data Store Read' + */ + rtDW.CCU_FOOT_RR = rtDW.CCU_STAT1_WAKEUP_MODEL.CCU_AirDirectionRR_Foot_Stat; + + /* DataStoreWrite: '/Data Store Write12' incorporates: + * DataStoreRead: '/Data Store Read' + */ + rtDW.CCU_DEF_FL = rtDW.CCU_STAT1_WAKEUP_MODEL.CCU_AirDirectionFL_Def_Stat; + + /* DataStoreWrite: '/Data Store Write13' incorporates: + * DataStoreRead: '/Data Store Read' + */ + rtDW.CCU_FACE_FL = rtDW.CCU_STAT1_WAKEUP_MODEL.CCU_AirDirectionFL_Face_Stat; + + /* DataStoreWrite: '/Data Store Write14' incorporates: + * DataStoreRead: '/Data Store Read' + */ + rtDW.CCU_FOOT_FL = rtDW.CCU_STAT1_WAKEUP_MODEL.CCU_AirDirectionFL_Foot_Stat; + + /* DataStoreWrite: '/Data Store Write15' incorporates: + * DataStoreRead: '/Data Store Read' + */ + rtDW.CCU_DEF_FR = rtDW.CCU_STAT1_WAKEUP_MODEL.CCU_AirDirectionFR_Def_Stat; + + /* DataStoreWrite: '/Data Store Write16' incorporates: + * DataStoreRead: '/Data Store Read' + */ + rtDW.CCU_FACE_FR = rtDW.CCU_STAT1_WAKEUP_MODEL.CCU_AirDirectionFR_Face_Stat; + + /* DataStoreWrite: '/Data Store Write17' incorporates: + * DataStoreRead: '/Data Store Read' + */ + rtDW.CCU_FOOT_FR = rtDW.CCU_STAT1_WAKEUP_MODEL.CCU_AirDirectionFR_Foot_Stat; + + /* DataStoreWrite: '/Data Store Write18' incorporates: + * DataStoreRead: '/Data Store Read' + */ + rtDW.CCU_RECIRC = rtDW.CCU_STAT1_WAKEUP_MODEL.CCU_Recirculation_Stat; + + /* DataStoreWrite: '/Data Store Write19' incorporates: + * DataStoreRead: '/Data Store Read' + */ + rtDW.CCU_BLOWERS_FL = rtDW.CCU_STAT1_WAKEUP_MODEL.CCU_BlowerSpeedFL_Stat; + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * DataStoreRead: '/Data Store Read' + */ + rtDW.CCU_MODE_RL = rtDW.CCU_STAT1_WAKEUP_MODEL.CCU_ModeRL_Stat; + + /* DataStoreWrite: '/Data Store Write21' incorporates: + * DataStoreRead: '/Data Store Read' + */ + rtDW.CCU_BLOWERS_FR = rtDW.CCU_STAT1_WAKEUP_MODEL.CCU_BlowerSpeedFR_Stat; + + /* DataStoreWrite: '/Data Store Write23' incorporates: + * DataStoreRead: '/Data Store Read' + */ + rtDW.CCU_BLOWERS_RL = rtDW.CCU_STAT1_WAKEUP_MODEL.CCU_BlowerSpeedRL_Stat; + + /* DataStoreWrite: '/Data Store Write25' incorporates: + * DataStoreRead: '/Data Store Read' + */ + rtDW.CCU_BLOWERS_RR = rtDW.CCU_STAT1_WAKEUP_MODEL.CCU_BlowerSpeedRR_Stat; + + /* DataStoreWrite: '/Data Store Write3' incorporates: + * DataStoreRead: '/Data Store Read' + */ + rtDW.CCU_MODE_RR = rtDW.CCU_STAT1_WAKEUP_MODEL.CCU_ModeRR_Stat; + + /* DataStoreWrite: '/Data Store Write4' incorporates: + * DataStoreRead: '/Data Store Read' + */ + rtDW.CCU_AUTOMODE_FL = rtDW.CCU_STAT1_WAKEUP_MODEL.CCU_AutoModeFL_Stat; + + /* DataStoreWrite: '/Data Store Write5' incorporates: + * DataStoreRead: '/Data Store Read' + */ + rtDW.CCU_AUTOMODE_FR = rtDW.CCU_STAT1_WAKEUP_MODEL.CCU_AutoModeFR_Stat; + + /* DataStoreWrite: '/Data Store Write6' incorporates: + * DataStoreRead: '/Data Store Read' + */ + rtDW.CCU_FACE_RL = rtDW.CCU_STAT1_WAKEUP_MODEL.CCU_AirDirectionRL_Face_Stat; + + /* DataStoreWrite: '/Data Store Write7' incorporates: + * DataStoreRead: '/Data Store Read' + */ + rtDW.CCU_FOOT_RL = rtDW.CCU_STAT1_WAKEUP_MODEL.CCU_AirDirectionRL_Foot_Stat; + + /* DataStoreWrite: '/Data Store Write8' incorporates: + * DataStoreRead: '/Data Store Read' + */ + rtDW.CCU_AUTOMODE_RL = rtDW.CCU_STAT1_WAKEUP_MODEL.CCU_AutoModeRL_Stat; + + /* DataStoreWrite: '/Data Store Write9' incorporates: + * DataStoreRead: '/Data Store Read' + */ + rtDW.CCU_AUTOMODE_RR = rtDW.CCU_STAT1_WAKEUP_MODEL.CCU_AutoModeRR_Stat; + + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Bias: '/Bias' + * DataStoreRead: '/Data Store Read' + * DataTypeConversion: '/Data Type Conversion' + * DataTypeConversion: '/Data Type Conversion1' + * Gain: '/Gain' + * Gain: '/Gain1' + */ + rtDW.CCU_SET_RL = (uint16_t)((0.5 * (double) + rtDW.CCU_STAT1_WAKEUP_MODEL.CCU_TargetTempRL_Stat_ro + 15.5) * 10.0); + + /* Saturate: '/Saturation' */ + if (rtDW.CCU_SET_RL > 305) { + /* DataTypeConversion: '/Data Type Conversion1' */ + rtDW.CCU_SET_RL = 305U; + } + + /* End of Saturate: '/Saturation' */ + + /* If: '/If' incorporates: + * DataStoreWrite: '/Data Store Write1' + */ + if (rtDW.CCU_SET_RL < 165) { + /* Outputs for IfAction SubSystem: '/LO mode' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/LOW' + */ + rtDW.LO_HI_MODE_RL = 1U; + + /* End of Outputs for SubSystem: '/LO mode' */ + } else if (rtDW.CCU_SET_RL > 295) { + /* Outputs for IfAction SubSystem: '/HI mode' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/HI' + */ + rtDW.LO_HI_MODE_RL = 2U; + + /* End of Outputs for SubSystem: '/HI mode' */ + } else { + /* Outputs for IfAction SubSystem: '/not LO or HI' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/not LO or HI' + */ + rtDW.LO_HI_MODE_RL = 0U; + + /* End of Outputs for SubSystem: '/not LO or HI' */ + } + + /* End of If: '/If' */ + + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Bias: '/Bias' + * DataStoreRead: '/Data Store Read' + * DataTypeConversion: '/Data Type Conversion' + * DataTypeConversion: '/Data Type Conversion1' + * Gain: '/Gain' + * Gain: '/Gain1' + */ + rtDW.CCU_SET_RR = (uint16_t)((0.5 * (double) + rtDW.CCU_STAT1_WAKEUP_MODEL.CCU_TargetTempRR_Stat_ro + 15.5) * 10.0); + + /* Saturate: '/Saturation' */ + if (rtDW.CCU_SET_RR > 305) { + /* DataTypeConversion: '/Data Type Conversion1' */ + rtDW.CCU_SET_RR = 305U; + } + + /* End of Saturate: '/Saturation' */ + + /* If: '/If' incorporates: + * DataStoreWrite: '/Data Store Write1' + */ + if (rtDW.CCU_SET_RR < 165) { + /* Outputs for IfAction SubSystem: '/LO mode' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/LOW' + */ + rtDW.LO_HI_MODE_RR = 1U; + + /* End of Outputs for SubSystem: '/LO mode' */ + } else if (rtDW.CCU_SET_RR > 295) { + /* Outputs for IfAction SubSystem: '/HI mode' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/HI' + */ + rtDW.LO_HI_MODE_RR = 2U; + + /* End of Outputs for SubSystem: '/HI mode' */ + } else { + /* Outputs for IfAction SubSystem: '/not LO or HI' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/not LO or HI' + */ + rtDW.LO_HI_MODE_RR = 0U; + + /* End of Outputs for SubSystem: '/not LO or HI' */ + } + + /* End of If: '/If' */ + + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Bias: '/Bias' + * DataStoreRead: '/Data Store Read' + * DataTypeConversion: '/Data Type Conversion' + * DataTypeConversion: '/Data Type Conversion1' + * Gain: '/Gain' + * Gain: '/Gain1' + */ + rtDW.CCU_SET_FL = (uint16_t)((0.5 * (double) + rtDW.CCU_STAT1_WAKEUP_MODEL.CCU_TargetTempFL_Stat_ro + 15.5) * 10.0); + + /* Saturate: '/Saturation' */ + if (rtDW.CCU_SET_FL > 305) { + /* DataTypeConversion: '/Data Type Conversion1' */ + rtDW.CCU_SET_FL = 305U; + } + + /* End of Saturate: '/Saturation' */ + + /* If: '/If' incorporates: + * DataStoreWrite: '/Data Store Write1' + */ + if (rtDW.CCU_SET_FL < 165) { + /* Outputs for IfAction SubSystem: '/LO mode' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/LOW' + */ + rtDW.LO_HI_MODE_FL = 1U; + + /* End of Outputs for SubSystem: '/LO mode' */ + } else if (rtDW.CCU_SET_FL > 295) { + /* Outputs for IfAction SubSystem: '/HI mode' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/HI' + */ + rtDW.LO_HI_MODE_FL = 2U; + + /* End of Outputs for SubSystem: '/HI mode' */ + } else { + /* Outputs for IfAction SubSystem: '/not LO or HI' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/not LO or HI' + */ + rtDW.LO_HI_MODE_FL = 0U; + + /* End of Outputs for SubSystem: '/not LO or HI' */ + } + + /* End of If: '/If' */ + + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Bias: '/Bias' + * DataStoreRead: '/Data Store Read' + * DataTypeConversion: '/Data Type Conversion' + * DataTypeConversion: '/Data Type Conversion1' + * Gain: '/Gain' + * Gain: '/Gain1' + */ + rtDW.CCU_SET_FR = (uint16_t)((0.5 * (double) + rtDW.CCU_STAT1_WAKEUP_MODEL.CCU_TargetTempFR_Stat_ro + 15.5) * 10.0); + + /* Saturate: '/Saturation' */ + if (rtDW.CCU_SET_FR > 305) { + /* DataTypeConversion: '/Data Type Conversion1' */ + rtDW.CCU_SET_FR = 305U; + } + + /* End of Saturate: '/Saturation' */ + + /* If: '/If' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + if (rtDW.CCU_SET_FR < 165) { + /* Outputs for IfAction SubSystem: '/LO mode' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/LOW' + */ + rtDW.LO_HI_MODE_FR = 1U; + + /* End of Outputs for SubSystem: '/LO mode' */ + } else if (rtDW.CCU_SET_FR > 295) { + /* Outputs for IfAction SubSystem: '/HI mode' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/HI' + */ + rtDW.LO_HI_MODE_FR = 2U; + + /* End of Outputs for SubSystem: '/HI mode' */ + } else { + /* Outputs for IfAction SubSystem: '/not LO or HI' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/not LO or HI' + */ + rtDW.LO_HI_MODE_FR = 0U; + + /* End of Outputs for SubSystem: '/not LO or HI' */ + } + + /* End of If: '/If' */ + + /* DataStoreWrite: '/Data Store Write27' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + CCU_FRONT_SYNC = rtDW.CCU_STAT2_WAKEUP_MODEL.CCU_FrontZoneSync_Stat; + + /* DataStoreWrite: '/Data Store Write28' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + rtb_timer_out = rtDW.CCU_STAT2_WAKEUP_MODEL.CCU_RearZoneSync_Stat; + + /* DataStoreWrite: '/Data Store Write29' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + rtb_DataTypeConversion3_i = rtDW.CCU_STAT2_WAKEUP_MODEL.CCU_AllZoneSync_Stat; + + /* DataStoreWrite: '/Data Store Write30' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + rtDW.CCU_AC_FRONT = rtDW.CCU_STAT2_WAKEUP_MODEL.CCU_ACfront_Stat; + + /* DataStoreWrite: '/Data Store Write31' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + rtDW.CCU_AC_REAR = rtDW.CCU_STAT2_WAKEUP_MODEL.CCU_ACrear_Stat; + + /* DataStoreWrite: '/Data Store Write32' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + rtDW.CCU_SET_FOOT_FL = rtDW.CCU_STAT2_WAKEUP_MODEL.CCU_FootTempCorFL_Stat; + + /* DataStoreWrite: '/Data Store Write33' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + rtDW.CCU_SET_FOOT_FR = rtDW.CCU_STAT2_WAKEUP_MODEL.CCU_FootTempCorFR_Stat; + + /* DataStoreWrite: '/Data Store Write34' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + rtDW.DRS_SFL = rtDW.CCU_STAT2_WAKEUP_MODEL.CCU_DeflectorSwDL_Stat; + + /* DataStoreWrite: '/Data Store Write35' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + rtDW.DRS_SFR = rtDW.CCU_STAT2_WAKEUP_MODEL.CCU_DeflectorSwDR_Stat; + + /* DataStoreWrite: '/Data Store Write36' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + rtDW.DRS_CFL = rtDW.CCU_STAT2_WAKEUP_MODEL.CCU_DeflectorSwFPL_Stat; + + /* DataStoreWrite: '/Data Store Write37' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + rtDW.DRS_CFR = rtDW.CCU_STAT2_WAKEUP_MODEL.CCU_DeflectorSwFPR_Stat; + + /* DataStoreWrite: '/Data Store Write38' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + rtDW.DRS_CRL = rtDW.CCU_STAT2_WAKEUP_MODEL.CCU_DeflectorSwFCL_Stat; + + /* DataStoreWrite: '/Data Store Write39' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + rtDW.DRS_CRR = rtDW.CCU_STAT2_WAKEUP_MODEL.CCU_DeflectorSwFCR_Stat; + + /* DataStoreWrite: '/Data Store Write40' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + rtDW.DRS_SRL = rtDW.CCU_STAT2_WAKEUP_MODEL.CCU_DeflectorSwRLB_Stat; + + /* DataStoreWrite: '/Data Store Write41' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + rtDW.DRS_SRR = rtDW.CCU_STAT2_WAKEUP_MODEL.CCU_DeflectorSwRRB_Stat; + + /* DataStoreWrite: '/Data Store Write42' incorporates: + * DataStoreRead: '/Data Store Read2' + */ + rtDW.CCU_Rest = rtDW.CCU_STAT3_WAKEUP_MODEL.CCU_RestMode2_Stat; + + /* DataStoreWrite: '/Data Store Write20' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + rtDW.CCU_Defrost = rtDW.CCU_Msg1_WakeUp_model.CCU_DefrostLed_Req; + + /* DataStoreWrite: '/Data Store Write22' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + rtDW.Full_Rec = rtDW.CCU_Msg1_WakeUp_model.CCU_RecirculationLed_Cmd; + + /* DataStoreWrite: '/Data Store Write24' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + rtDW.CCU_AC_MAX = rtDW.CCU_Msg1_WakeUp_model.CCU_AC_MaxLed_Cmd; + } + + /* End of DataStoreRead: '/Data Store Read13' */ + /* End of Outputs for SubSystem: '/Sleep_mode' */ + + /* Switch: '/Switch2' incorporates: + * BusCreator: '/Bus Creator2' + * BusCreator: '/Bus Creator8' + * Constant: '/Constant2' + * DataStoreRead: '/Data Store Read49' + * DataStoreRead: '/Data Store Read50' + * DataStoreRead: '/Data Store Read51' + * DataStoreRead: '/Data Store Read57' + * DataStoreRead: '/Data Store Read58' + * DataStoreRead: '/Data Store Read59' + * DataStoreRead: '/Data Store Read60' + * DataStoreRead: '/Data Store Read61' + * DataStoreRead: '/Data Store Read64' + * DataStoreRead: '/Data Store Read65' + * DataStoreRead: '/Data Store Read66' + * DataStoreWrite: '/Data Store Write31' + * DataTypeConversion: '/Data Type Conversion' + * DataTypeConversion: '/Data Type Conversion' + * DataTypeConversion: '/Data Type Conversion' + * DataTypeConversion: '/Data Type Conversion1' + * Logic: '/Logical Operator13' + * Logic: '/Logical Operator4' + * Logic: '/Logical Operator4' + * Logic: '/Logical Operator9' + * Switch: '/Switch1' + * Switch: '/Switch3' + * Switch: '/Switch4' + * Switch: '/Switch5' + * Switch: '/Switch6' + * Switch: '/Switch7' + */ + if (rtDW.BCM_T15_Stat > 0) { + /* Outport: '/CCU_Stat1_model' incorporates: + * BusCreator: '/Bus Creator' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read10' + * DataStoreRead: '/Data Store Read11' + * DataStoreRead: '/Data Store Read17' + * DataStoreRead: '/Data Store Read18' + * DataStoreRead: '/Data Store Read19' + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read20' + * DataStoreRead: '/Data Store Read21' + * DataStoreRead: '/Data Store Read22' + * DataStoreRead: '/Data Store Read23' + * DataStoreRead: '/Data Store Read24' + * DataStoreRead: '/Data Store Read3' + * DataStoreRead: '/Data Store Read4' + * DataStoreRead: '/Data Store Read5' + * DataStoreRead: '/Data Store Read6' + * DataStoreRead: '/Data Store Read7' + * DataStoreRead: '/Data Store Read8' + * DataStoreRead: '/Data Store Read9' + */ + rtY.CCU_Stat1_model.CCU_ModeFL_Stat = rtDW.CCU_MODE_FL; + rtY.CCU_Stat1_model.CCU_ModeFR_Stat = rtDW.CCU_MODE_FR; + rtY.CCU_Stat1_model.CCU_ModeRL_Stat = rtDW.CCU_MODE_RL; + rtY.CCU_Stat1_model.CCU_ModeRR_Stat = rtDW.CCU_MODE_RR; + rtY.CCU_Stat1_model.CCU_AutoModeFL_Stat = rtDW.CCU_AUTOMODE_FL; + rtY.CCU_Stat1_model.CCU_AutoModeFR_Stat = rtDW.CCU_AUTOMODE_FR; + rtY.CCU_Stat1_model.CCU_AirDirectionRL_Face_Stat = rtDW.CCU_FACE_RL; + rtY.CCU_Stat1_model.CCU_AirDirectionRL_Foot_Stat = rtDW.CCU_FOOT_RL; + rtY.CCU_Stat1_model.CCU_AutoModeRL_Stat = rtDW.CCU_AUTOMODE_RL; + rtY.CCU_Stat1_model.CCU_AutoModeRR_Stat = rtDW.CCU_AUTOMODE_RR; + rtY.CCU_Stat1_model.CCU_AirDirectionRR_Face_Stat = rtDW.CCU_FACE_RR; + rtY.CCU_Stat1_model.CCU_AirDirectionRR_Foot_Stat = rtDW.CCU_FOOT_RR; + rtY.CCU_Stat1_model.CCU_AirDirectionFL_Def_Stat = rtDW.CCU_DEF_FL; + rtY.CCU_Stat1_model.CCU_AirDirectionFL_Face_Stat = rtDW.CCU_FACE_FL; + rtY.CCU_Stat1_model.CCU_AirDirectionFL_Foot_Stat = rtDW.CCU_FOOT_FL; + rtY.CCU_Stat1_model.CCU_AirDirectionFR_Def_Stat = rtDW.CCU_DEF_FR; + rtY.CCU_Stat1_model.CCU_AirDirectionFR_Face_Stat = rtDW.CCU_FACE_FR; + rtY.CCU_Stat1_model.CCU_AirDirectionFR_Foot_Stat = rtDW.CCU_FOOT_FR; + rtY.CCU_Stat1_model.CCU_Recirculation_Stat = rtDW.CCU_RECIRC; + rtY.CCU_Stat1_model.CCU_BlowerSpeedFL_Stat = rtDW.CCU_BLOWERS_FL; + + /* Saturate: '/Saturation' incorporates: + * DataStoreRead: '/Data Store Read13' + */ + if (rtDW.CCU_SET_FL > 310) { + rtb_out_h0 = 310U; + } else if (rtDW.CCU_SET_FL < 155) { + rtb_out_h0 = 155U; + } else { + rtb_out_h0 = rtDW.CCU_SET_FL; + } + + /* Outport: '/CCU_Stat1_model' incorporates: + * Bias: '/Bias' + * BusCreator: '/Bus Creator' + * DataStoreRead: '/Data Store Read12' + * DataTypeConversion: '/Data Type Conversion' + * Gain: '/Gain' + * Gain: '/Gain1' + * Saturate: '/Saturation' + */ + rtY.CCU_Stat1_model.CCU_TargetTempFL_Stat_ro = (uint8_t) + ((0.10000038146972656 * (double)rtb_out_h0 - 16.0) * 2.0); + rtY.CCU_Stat1_model.CCU_BlowerSpeedFR_Stat = rtDW.CCU_BLOWERS_FR; + + /* Saturate: '/Saturation' incorporates: + * DataStoreRead: '/Data Store Read14' + */ + if (rtDW.CCU_SET_FR > 310) { + rtb_out_h0 = 310U; + } else if (rtDW.CCU_SET_FR < 155) { + rtb_out_h0 = 155U; + } else { + rtb_out_h0 = rtDW.CCU_SET_FR; + } + + /* Outport: '/CCU_Stat1_model' incorporates: + * Bias: '/Bias1' + * BusCreator: '/Bus Creator' + * DataStoreRead: '/Data Store Read26' + * DataTypeConversion: '/Data Type Conversion' + * Gain: '/Gain' + * Gain: '/Gain1' + * Saturate: '/Saturation' + */ + rtY.CCU_Stat1_model.CCU_TargetTempFR_Stat_ro = (uint8_t) + ((0.10000038146972656 * (double)rtb_out_h0 - 16.0) * 2.0); + rtY.CCU_Stat1_model.CCU_BlowerSpeedRL_Stat = rtDW.CCU_BLOWERS_RL; + + /* Saturate: '/Saturation' incorporates: + * DataStoreRead: '/Data Store Read15' + */ + if (rtDW.CCU_SET_RR > 310) { + rtb_out_h0 = 310U; + } else if (rtDW.CCU_SET_RR < 155) { + rtb_out_h0 = 155U; + } else { + rtb_out_h0 = rtDW.CCU_SET_RR; + } + + /* Outport: '/CCU_Stat1_model' incorporates: + * Bias: '/Bias' + * BusCreator: '/Bus Creator' + * DataStoreRead: '/Data Store Read25' + * DataTypeConversion: '/Data Type Conversion' + * Gain: '/Gain' + * Gain: '/Gain1' + * Saturate: '/Saturation' + */ + rtY.CCU_Stat1_model.CCU_TargetTempRR_Stat_ro = (uint8_t) + ((0.10000038146972656 * (double)rtb_out_h0 - 16.0) * 2.0); + rtY.CCU_Stat1_model.CCU_BlowerSpeedRR_Stat = rtDW.CCU_BLOWERS_RR; + + /* Saturate: '/Saturation' incorporates: + * DataStoreRead: '/Data Store Read16' + */ + if (rtDW.CCU_SET_RL > 310) { + rtb_out_h0 = 310U; + } else if (rtDW.CCU_SET_RL < 155) { + rtb_out_h0 = 155U; + } else { + rtb_out_h0 = rtDW.CCU_SET_RL; + } + + /* Outport: '/CCU_Stat1_model' incorporates: + * Bias: '/Bias' + * DataTypeConversion: '/Data Type Conversion' + * Gain: '/Gain' + * Gain: '/Gain1' + * Saturate: '/Saturation' + */ + rtY.CCU_Stat1_model.CCU_TargetTempRL_Stat_ro = (uint8_t) + ((0.10000038146972656 * (double)rtb_out_h0 - 16.0) * 2.0); + + /* Outport: '/CCU_Stat2_model' incorporates: + * BusCreator: '/Bus Creator1' + * DataStoreRead: '/Data Store Read27' + * DataStoreRead: '/Data Store Read28' + * DataStoreRead: '/Data Store Read29' + * DataStoreRead: '/Data Store Read34' + * DataStoreRead: '/Data Store Read35' + * DataStoreRead: '/Data Store Read55' + * DataStoreRead: '/Data Store Read56' + * DataStoreRead: '/Data Store Read62' + * DataStoreRead: '/Data Store Read63' + * DataStoreRead: '/Data Store Read67' + * DataStoreRead: '/Data Store Read68' + * DataStoreRead: '/Data Store Read69' + * DataStoreRead: '/Data Store Read70' + * DataStoreRead: '/Data Store Read71' + * DataStoreRead: '/Data Store Read72' + * DataStoreRead: '/Data Store Read73' + * DataStoreRead: '/Data Store Read74' + * DataStoreRead: '/Data Store Read77' + */ + rtY.CCU_Stat2_model.CCU_AromaCartridgeSw_Stat = rtDW.Aroma_CartridgeSw; + rtY.CCU_Stat2_model.CCU_FrontZoneSync_Stat = CCU_FRONT_SYNC; + rtY.CCU_Stat2_model.CCU_RearZoneSync_Stat = rtb_timer_out; + rtY.CCU_Stat2_model.CCU_AllZoneSync_Stat = rtb_DataTypeConversion3_i; + rtY.CCU_Stat2_model.CCU_ACfront_Stat = rtDW.CCU_AC_FRONT; + rtY.CCU_Stat2_model.CCU_ACrear_Stat = rtDW.CCU_AC_REAR; + rtY.CCU_Stat2_model.CCU_ACmaxF_Stat = 0U; + rtY.CCU_Stat2_model.CCU_ACmaxR_Stat = 0U; + rtY.CCU_Stat2_model.CCU_Defrost_Stat = 0U; + rtY.CCU_Stat2_model.CCU_Ionization_Stat = 0U; + rtY.CCU_Stat2_model.CCU_FootTempCorFL_Stat = rtDW.CCU_SET_FOOT_FL; + rtY.CCU_Stat2_model.CCU_FootTempCorFR_Stat = rtDW.CCU_SET_FOOT_FR; + rtY.CCU_Stat2_model.CCU_AromaIntens_Stat = 0U; + rtY.CCU_Stat2_model.CCU_FootTempCorRL_Stat = rtDW.CCU_SET_FOOT_RL; + rtY.CCU_Stat2_model.CCU_FootTempCorRR_Stat = rtDW.CCU_SET_FOOT_RR; + rtY.CCU_Stat2_model.CCU_DeflectorSwDL_Stat = rtDW.DRS_SFL; + rtY.CCU_Stat2_model.CCU_DeflectorSwDR_Stat = rtDW.DRS_SFR; + rtY.CCU_Stat2_model.CCU_DeflectorSwFPL_Stat = rtDW.DRS_CFL; + rtY.CCU_Stat2_model.CCU_DeflectorSwFPR_Stat = rtDW.DRS_CFR; + rtY.CCU_Stat2_model.CCU_DeflectorSwFCL_Stat = rtDW.DRS_CRL; + rtY.CCU_Stat2_model.CCU_DeflectorSwFCR_Stat = rtDW.DRS_CRR; + rtY.CCU_Stat2_model.CCU_DeflectorSwRLB_Stat = rtDW.DRS_SRL; + rtY.CCU_Stat2_model.CCU_DeflectorSwRRB_Stat = rtDW.DRS_SRR; + + /* Saturate: '/Saturation' incorporates: + * MATLAB Function: '/MATLAB Function' + */ + if (El_window_heating <= 160) { + /* Outport: '/CCUCAN_HVC_REQ_MSG_MODEL' */ + rtY.CCUCAN_HVC_REQ_MSG_MODEL.CCU_eCompSpeedReq_Val_ro = El_window_heating; + } else { + /* Outport: '/CCUCAN_HVC_REQ_MSG_MODEL' */ + rtY.CCUCAN_HVC_REQ_MSG_MODEL.CCU_eCompSpeedReq_Val_ro = 160U; + } + + /* End of Saturate: '/Saturation' */ + + /* Outport: '/CCUCAN_HVC_REQ_MSG_MODEL' incorporates: + * BusCreator: '/Bus Creator3' + * DataStoreRead: '/Data Store Read37' + * DataStoreWrite: '/Data Store Write13' + * DataTypeConversion: '/Data Type Conversion' + */ + rtY.CCUCAN_HVC_REQ_MSG_MODEL.CCU_eCompReq_Stat = Enable_Comp_PID; + rtY.CCUCAN_HVC_REQ_MSG_MODEL.CCU_LowTempValve_Req = rtb_Cmd_3Way; + rtY.CCUCAN_HVC_REQ_MSG_MODEL.CCU_HVC_Req_RC = 0U; + rtY.CCUCAN_HVC_REQ_MSG_MODEL.CCU_HVC_Req_CS = 0U; + + /* Switch: '/Switch1' incorporates: + * Constant: '/Constant7' + */ + if (!Enable_Comp_PID) { + fan_speed_out = 0U; + } + + /* Saturate: '/Saturation5' incorporates: + * Switch: '/Switch1' + */ + if (fan_speed_out <= 100) { + /* Outport: '/CCU_Msg3_model' */ + rtY.CCU_Msg3_model.CCU_FAN_Req = fan_speed_out; + } else { + /* Outport: '/CCU_Msg3_model' */ + rtY.CCU_Msg3_model.CCU_FAN_Req = 100U; + } + + /* End of Saturate: '/Saturation5' */ + + /* Outport: '/CCU_Msg3_model' incorporates: + * BusCreator: '/Bus Creator4' + */ + rtY.CCU_Msg3_model.CCU_RestMode_Stat = 0U; + rtY.CCU_Msg3_model.CCU_IncarTempSum_Val_ro = 0U; + rtY.CCU_Msg3_model.CCU_MSG3_RC = 0U; + rtY.CCU_Msg3_model.CCU_MSG3_CS = 0U; + + /* Outport: '/CCU_Stat3_model' incorporates: + * BusCreator: '/Bus Creator12' + * DataStoreRead: '/Data Store Read75' + * DataStoreRead: '/Data Store Read76' + * DataStoreRead: '/Data Store Read79' + */ + rtY.CCU_Stat3_model.CCU_AromaCartridgeCapacity_Stat_ro = + rtDW.Aroma_CartridgeCapacity; + rtY.CCU_Stat3_model.CCU_AromaCartridgeFlavor_Stat = + rtDW.Aroma_CartridgeFlavor; + rtY.CCU_Stat3_model.CCU_AromaFaultReason_Stat = 0U; + rtY.CCU_Stat3_model.CCU_RLfootBlowDis_Stat = 0U; + rtY.CCU_Stat3_model.CCU_RRfootBlowDis_Stat = 0U; + rtY.CCU_Stat3_model.CCU_RestMode2_Stat = rtDW.CCU_Rest; + CCU_Errors_Model.CCU_IncarTempErrF_Stat = (uint8_t)(rtb_err || + rtb_LogicalOperator6); + CCU_Errors_Model.CCU_IncarTempErrR_Stat = (uint8_t)(rtb_LogicalOperator3 || + rtb_LogicalOperator8); + CCU_Errors_Model.CCU_DuctTempSenErrF_Stat = (uint8_t) + (rtb_LogicalOperator3_cz || rtb_LogicalOperator4_fo || + rtb_LogicalOperator6_m || rtb_LogicalOperator8_i || rtb_LogicalOperator10 + || rtb_LogicalOperator11); + CCU_Errors_Model.CCU_DuctTempSenErrR_Stat = (uint8_t)(rtb_Compare_gk || + rtb_Compare_jl3 || rtb_Compare_jz || rtb_Compare_e3); + CCU_Errors_Model.CCU_EvaTempSenErrF_Stat = rtDW.CCU_EvaTempSenErrF_Stat; + CCU_Errors_Model.CCU_EvaTempSenErrR_Stat = rtDW.CCU_EvaTempSenErrR_Stat; + CCU_Errors_Model.CCU_DeflectorSwErrF_Stat = rtDW.CCU_DeflectorSwErrF_Stat; + CCU_Errors_Model.CCU_DeflectorSwErrR_Stat = rtDW.CCU_DeflectorSwErrR_Stat; + CCU_Errors_Model.CCU_PressSenErr_Stat = rtDW.CCU_PressSenErr_Stat; + CCU_Errors_Model.CCU_AmbienTemptSenErr_Stat = 0U; + CCU_Errors_Model.CCU_SealingValveErr_Stat = 0U; + CCU_Errors_Model.CCU_ETXVerr_Stat = 0U; + CCU_Errors_Model.CCU_HVACfanOrTXVerrF_Stat = 0U; + CCU_Errors_Model.CCU_HVACfanOrTXVerrR_Stat = 0U; + CCU_Errors_Model.CCU_ActuatorErrF_Stat = rtDW.CCU_ActuatorErrF_Stat_private; + CCU_Errors_Model.CCU_ActuatorErrR_Stat = rtDW.CCU_ActuatorErrR_Stat_private; + CCU_Errors_Model.CCU_UltravioletErr_Stat = 0U; + CCU_Errors_Model.CCU_VinRecordErr_Stat = 0U; + CCU_Errors_Model.CCU_AirQualSenErr_Stat = rtDW.CCU_AirQualSenErr_Stat; + CCU_Errors_Model.CCU_CommErr_Stat = 0U; + CCU_Errors_Model.CCU_TWVerr_Stat = 0U; + CCU_Errors_Model.CCU_IonizationErr_Stat = rtDW.CCU_IonizationErr_Stat; + CCU_Errors_Model.CCU_AromaErr_Stat = rtDW.CCU_AromaErr_Stat; + + /* Outport: '/CCU_Msg1_model' incorporates: + * BusCreator: '/Bus Creator2' + * BusCreator: '/Bus Creator5' + * DataStoreRead: '/Data Store Read38' + * DataStoreRead: '/Data Store Read39' + * DataStoreRead: '/Data Store Read40' + * DataStoreRead: '/Data Store Read41' + * DataStoreRead: '/Data Store Read42' + * DataStoreRead: '/Data Store Read43' + * DataStoreRead: '/Data Store Read44' + * DataStoreRead: '/Data Store Read49' + * DataStoreRead: '/Data Store Read50' + * DataStoreRead: '/Data Store Read51' + * DataStoreRead: '/Data Store Read57' + * DataStoreRead: '/Data Store Read58' + * DataStoreRead: '/Data Store Read59' + * DataStoreRead: '/Data Store Read60' + * DataStoreRead: '/Data Store Read61' + * DataStoreRead: '/Data Store Read65' + * DataStoreRead: '/Data Store Read66' + * DataStoreWrite: '/Data Store Write31' + * DataTypeConversion: '/Data Type Conversion' + * DataTypeConversion: '/Data Type Conversion' + * DataTypeConversion: '/Data Type Conversion' + * DataTypeConversion: '/Data Type Conversion1' + * Logic: '/Logical Operator13' + * Logic: '/Logical Operator4' + * Logic: '/Logical Operator4' + * Logic: '/Logical Operator9' + */ + rtY.CCU_Msg1_model.CCU_MirrorHeating_Req = 0U; + rtY.CCU_Msg1_model.CCU_RecirculationLed_Cmd = rtDW.Full_Rec; + rtY.CCU_Msg1_model.CCU_DefrostLed_Req = rtDW.CCU_Defrost; + rtY.CCU_Msg1_model.CCU_SideWindowHeating_Req = 0U; + rtY.CCU_Msg1_model.CCU_RearWindowHeating_Req = 0U; + rtY.CCU_Msg1_model.CCU_FrontWindowHeating_Req = 0U; + rtY.CCU_Msg1_model.CCU_EmergAirCleaning_Stat = 0U; + rtY.CCU_Msg1_model.CCU_FireExtinguishSys_Stat = 0U; + rtY.CCU_Msg1_model.CCU_FLAutoPsngrLed_Cmd = rtDW.CCU_MODE_FL; + rtY.CCU_Msg1_model.CCU_FRAutoPsngrLed_Cmd = rtDW.CCU_MODE_FR; + rtY.CCU_Msg1_model.CCU_RLAutoPsngrLed_Cmd = rtDW.CCU_MODE_RL; + rtY.CCU_Msg1_model.CCU_RRAutoPsngrLed_Cmd = rtDW.CCU_MODE_RR; + rtY.CCU_Msg1_model.CCU_AC_MaxLed_Cmd = rtDW.CCU_AC_MAX; + rtY.CCU_Msg1_model.CCU_MSG1_RC = 0U; + rtY.CCU_Msg1_model.CCU_MSG1_CS = 0U; + } else { + /* Outport: '/CCU_Stat1_model' incorporates: + * BusCreator: '/Bus Creator6' + * Constant: '/Constant' + */ + rtY.CCU_Stat1_model.CCU_ModeFL_Stat = 0U; + rtY.CCU_Stat1_model.CCU_ModeFR_Stat = 0U; + rtY.CCU_Stat1_model.CCU_ModeRL_Stat = 0U; + rtY.CCU_Stat1_model.CCU_ModeRR_Stat = 0U; + rtY.CCU_Stat1_model.CCU_AutoModeFL_Stat = 0U; + rtY.CCU_Stat1_model.CCU_AutoModeFR_Stat = 0U; + rtY.CCU_Stat1_model.CCU_AirDirectionRL_Face_Stat = 0U; + rtY.CCU_Stat1_model.CCU_AirDirectionRL_Foot_Stat = 0U; + rtY.CCU_Stat1_model.CCU_AutoModeRL_Stat = 0U; + rtY.CCU_Stat1_model.CCU_AutoModeRR_Stat = 0U; + rtY.CCU_Stat1_model.CCU_AirDirectionRR_Face_Stat = 0U; + rtY.CCU_Stat1_model.CCU_AirDirectionRR_Foot_Stat = 0U; + rtY.CCU_Stat1_model.CCU_AirDirectionFL_Def_Stat = 0U; + rtY.CCU_Stat1_model.CCU_AirDirectionFL_Face_Stat = 0U; + rtY.CCU_Stat1_model.CCU_AirDirectionFL_Foot_Stat = 0U; + rtY.CCU_Stat1_model.CCU_AirDirectionFR_Def_Stat = 0U; + rtY.CCU_Stat1_model.CCU_AirDirectionFR_Face_Stat = 0U; + rtY.CCU_Stat1_model.CCU_AirDirectionFR_Foot_Stat = 0U; + rtY.CCU_Stat1_model.CCU_Recirculation_Stat = 0U; + rtY.CCU_Stat1_model.CCU_BlowerSpeedFL_Stat = 0U; + rtY.CCU_Stat1_model.CCU_TargetTempFL_Stat_ro = 0U; + rtY.CCU_Stat1_model.CCU_BlowerSpeedFR_Stat = 0U; + rtY.CCU_Stat1_model.CCU_TargetTempFR_Stat_ro = 0U; + rtY.CCU_Stat1_model.CCU_BlowerSpeedRL_Stat = 0U; + rtY.CCU_Stat1_model.CCU_TargetTempRR_Stat_ro = 0U; + rtY.CCU_Stat1_model.CCU_BlowerSpeedRR_Stat = 0U; + rtY.CCU_Stat1_model.CCU_TargetTempRL_Stat_ro = 0U; + + /* Outport: '/CCU_Stat2_model' incorporates: + * BusCreator: '/Bus Creator7' + * Constant: '/Constant1' + */ + rtY.CCU_Stat2_model.CCU_AromaCartridgeSw_Stat = 0U; + rtY.CCU_Stat2_model.CCU_FrontZoneSync_Stat = 0U; + rtY.CCU_Stat2_model.CCU_RearZoneSync_Stat = 0U; + rtY.CCU_Stat2_model.CCU_AllZoneSync_Stat = 0U; + rtY.CCU_Stat2_model.CCU_ACfront_Stat = 0U; + rtY.CCU_Stat2_model.CCU_ACrear_Stat = 0U; + rtY.CCU_Stat2_model.CCU_ACmaxF_Stat = 0U; + rtY.CCU_Stat2_model.CCU_ACmaxR_Stat = 0U; + rtY.CCU_Stat2_model.CCU_Defrost_Stat = 0U; + rtY.CCU_Stat2_model.CCU_Ionization_Stat = 0U; + rtY.CCU_Stat2_model.CCU_FootTempCorFL_Stat = 0U; + rtY.CCU_Stat2_model.CCU_FootTempCorFR_Stat = 0U; + rtY.CCU_Stat2_model.CCU_AromaIntens_Stat = 0U; + rtY.CCU_Stat2_model.CCU_FootTempCorRL_Stat = 0U; + rtY.CCU_Stat2_model.CCU_FootTempCorRR_Stat = 0U; + rtY.CCU_Stat2_model.CCU_DeflectorSwDL_Stat = 0U; + rtY.CCU_Stat2_model.CCU_DeflectorSwDR_Stat = 0U; + rtY.CCU_Stat2_model.CCU_DeflectorSwFPL_Stat = 0U; + rtY.CCU_Stat2_model.CCU_DeflectorSwFPR_Stat = 0U; + rtY.CCU_Stat2_model.CCU_DeflectorSwFCL_Stat = 0U; + rtY.CCU_Stat2_model.CCU_DeflectorSwFCR_Stat = 0U; + rtY.CCU_Stat2_model.CCU_DeflectorSwRLB_Stat = 0U; + rtY.CCU_Stat2_model.CCU_DeflectorSwRRB_Stat = 0U; + + /* Outport: '/CCUCAN_HVC_REQ_MSG_MODEL' incorporates: + * BusCreator: '/Bus Creator10' + * Constant: '/Constant4' + */ + rtY.CCUCAN_HVC_REQ_MSG_MODEL.CCU_eCompSpeedReq_Val_ro = 0U; + rtY.CCUCAN_HVC_REQ_MSG_MODEL.CCU_eCompReq_Stat = 0U; + rtY.CCUCAN_HVC_REQ_MSG_MODEL.CCU_LowTempValve_Req = 0U; + rtY.CCUCAN_HVC_REQ_MSG_MODEL.CCU_HVC_Req_RC = 0U; + rtY.CCUCAN_HVC_REQ_MSG_MODEL.CCU_HVC_Req_CS = 0U; + + /* Outport: '/CCU_Msg3_model' incorporates: + * BusCreator: '/Bus Creator11' + * Constant: '/Constant5' + */ + rtY.CCU_Msg3_model.CCU_FAN_Req = 0U; + rtY.CCU_Msg3_model.CCU_RestMode_Stat = 0U; + rtY.CCU_Msg3_model.CCU_IncarTempSum_Val_ro = 0U; + rtY.CCU_Msg3_model.CCU_MSG3_RC = 0U; + rtY.CCU_Msg3_model.CCU_MSG3_CS = 0U; + + /* Outport: '/CCU_Stat3_model' incorporates: + * BusCreator: '/Bus Creator13' + * Constant: '/Constant6' + */ + rtY.CCU_Stat3_model.CCU_AromaCartridgeCapacity_Stat_ro = 0U; + rtY.CCU_Stat3_model.CCU_AromaCartridgeFlavor_Stat = 0U; + rtY.CCU_Stat3_model.CCU_AromaFaultReason_Stat = 0U; + rtY.CCU_Stat3_model.CCU_RLfootBlowDis_Stat = 0U; + rtY.CCU_Stat3_model.CCU_RRfootBlowDis_Stat = 0U; + rtY.CCU_Stat3_model.CCU_RestMode2_Stat = 0U; + CCU_Errors_Model.CCU_IncarTempErrF_Stat = 0U; + CCU_Errors_Model.CCU_IncarTempErrR_Stat = 0U; + CCU_Errors_Model.CCU_DuctTempSenErrF_Stat = 0U; + CCU_Errors_Model.CCU_DuctTempSenErrR_Stat = 0U; + CCU_Errors_Model.CCU_EvaTempSenErrF_Stat = 0U; + CCU_Errors_Model.CCU_EvaTempSenErrR_Stat = 0U; + CCU_Errors_Model.CCU_DeflectorSwErrF_Stat = 0U; + CCU_Errors_Model.CCU_DeflectorSwErrR_Stat = 0U; + CCU_Errors_Model.CCU_PressSenErr_Stat = 0U; + CCU_Errors_Model.CCU_AmbienTemptSenErr_Stat = 0U; + CCU_Errors_Model.CCU_SealingValveErr_Stat = 0U; + CCU_Errors_Model.CCU_ETXVerr_Stat = 0U; + CCU_Errors_Model.CCU_HVACfanOrTXVerrF_Stat = 0U; + CCU_Errors_Model.CCU_HVACfanOrTXVerrR_Stat = 0U; + CCU_Errors_Model.CCU_ActuatorErrF_Stat = 0U; + CCU_Errors_Model.CCU_ActuatorErrR_Stat = 0U; + CCU_Errors_Model.CCU_UltravioletErr_Stat = 0U; + CCU_Errors_Model.CCU_VinRecordErr_Stat = 0U; + CCU_Errors_Model.CCU_AirQualSenErr_Stat = 0U; + CCU_Errors_Model.CCU_CommErr_Stat = 0U; + CCU_Errors_Model.CCU_TWVerr_Stat = 0U; + CCU_Errors_Model.CCU_IonizationErr_Stat = 0U; + CCU_Errors_Model.CCU_AromaErr_Stat = 0U; + + /* Outport: '/CCU_Msg1_model' incorporates: + * BusCreator: '/Bus Creator8' + * BusCreator: '/Bus Creator9' + * Constant: '/Constant2' + * Constant: '/Constant3' + * DataStoreWrite: '/Data Store Write31' + */ + rtY.CCU_Msg1_model.CCU_MirrorHeating_Req = 0U; + rtY.CCU_Msg1_model.CCU_RecirculationLed_Cmd = 0U; + rtY.CCU_Msg1_model.CCU_DefrostLed_Req = 0U; + rtY.CCU_Msg1_model.CCU_SideWindowHeating_Req = 0U; + rtY.CCU_Msg1_model.CCU_RearWindowHeating_Req = 0U; + rtY.CCU_Msg1_model.CCU_FrontWindowHeating_Req = 0U; + rtY.CCU_Msg1_model.CCU_EmergAirCleaning_Stat = 0U; + rtY.CCU_Msg1_model.CCU_FireExtinguishSys_Stat = 0U; + rtY.CCU_Msg1_model.CCU_FLAutoPsngrLed_Cmd = 0U; + rtY.CCU_Msg1_model.CCU_FRAutoPsngrLed_Cmd = 0U; + rtY.CCU_Msg1_model.CCU_RLAutoPsngrLed_Cmd = 0U; + rtY.CCU_Msg1_model.CCU_RRAutoPsngrLed_Cmd = 0U; + rtY.CCU_Msg1_model.CCU_AC_MaxLed_Cmd = 0U; + rtY.CCU_Msg1_model.CCU_MSG1_RC = 0U; + rtY.CCU_Msg1_model.CCU_MSG1_CS = 0U; + } + + /* End of Switch: '/Switch2' */ + + /* BusCreator: '/Bus Creator2' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read10' + * DataStoreRead: '/Data Store Read11' + * DataStoreRead: '/Data Store Read12' + * DataStoreRead: '/Data Store Read13' + * DataStoreRead: '/Data Store Read14' + * DataStoreRead: '/Data Store Read15' + * DataStoreRead: '/Data Store Read16' + * DataStoreRead: '/Data Store Read17' + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read3' + * DataStoreRead: '/Data Store Read4' + * DataStoreRead: '/Data Store Read5' + * DataStoreRead: '/Data Store Read6' + * DataStoreRead: '/Data Store Read7' + * DataStoreRead: '/Data Store Read8' + * DataStoreRead: '/Data Store Read9' + * DataStoreWrite: '/Data Store Write2' + * Sum: '/Add' + * Sum: '/Add1' + * Sum: '/Add10' + * Sum: '/Add11' + * Sum: '/Add12' + * Sum: '/Add13' + * Sum: '/Add14' + * Sum: '/Add15' + * Sum: '/Add16' + * Sum: '/Add17' + * Sum: '/Add2' + * Sum: '/Add3' + * Sum: '/Add4' + * Sum: '/Add5' + * Sum: '/Add6' + * Sum: '/Add7' + * Sum: '/Add8' + * Sum: '/Add9' + */ + rtDW.Status_Sensor_model_IO.Ignition = 0U; + rtDW.Status_Sensor_model_IO.Battery = 0U; + rtDW.Status_Sensor_model_IO.AMB = (uint16_t)(rtDW.AMB + 400); + rtDW.Status_Sensor_model_IO.Incar_FL = (uint16_t)(rtDW.Incar_FL + 400); + rtDW.Status_Sensor_model_IO.Incar_FR = (uint16_t)(rtDW.Incar_FR + 400); + rtDW.Status_Sensor_model_IO.Incar_RL = (uint16_t)(rtDW.Incar_RL + 400); + rtDW.Status_Sensor_model_IO.Incar_RR = (uint16_t)(rtDW.Incar_RR + 400); + rtDW.Status_Sensor_model_IO.Eva_F = (uint16_t)(rtDW.Eva_F + 400); + rtDW.Status_Sensor_model_IO.Eva_R = (uint16_t)(rtDW.Eva_R + 400); + rtDW.Status_Sensor_model_IO.Pressure = (uint16_t)(rtDW.Pressure + 400); + rtDW.Status_Sensor_model_IO.Duct_FL_Upper = (uint16_t)(rtb_Bias1_h + 400); + rtDW.Status_Sensor_model_IO.Duct_FL_Lower = (uint16_t)(rtb_FLU_tg_correct_ot + + 400); + rtDW.Status_Sensor_model_IO.Duct_FR_Upper = (uint16_t)(rtb_MultiportSwitch_pa + + 400); + rtDW.Status_Sensor_model_IO.Duct_FR_Lower = (uint16_t)(Duct4_F + 400); + rtDW.Status_Sensor_model_IO.Duct_RL = (uint16_t)(Duct1_R + 400); + rtDW.Status_Sensor_model_IO.Duct_RR = (uint16_t)(Duct2_R + 400); + rtDW.Status_Sensor_model_IO.Duct_Side_FL = (uint16_t)(Duct5_F + 400); + rtDW.Status_Sensor_model_IO.Duct_Side_FR = (uint16_t)(Duct6_F + 400); + rtDW.Status_Sensor_model_IO.Duct_Side_RL = (uint16_t)(Duct3_R + 400); + rtDW.Status_Sensor_model_IO.Duct_Side_RR = (uint16_t)(Duct4_R + 400); + rtDW.Status_Sensor_model_IO.AQS = 0U; + + /* BusCreator: '/Bus Creator4' incorporates: + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read21' + * DataStoreRead: '/Data Store Read22' + * DataStoreRead: '/Data Store Read23' + * DataStoreRead: '/Data Store Read24' + * DataStoreRead: '/Data Store Read25' + * DataStoreRead: '/Data Store Read26' + * DataStoreWrite: '/Data Store Write4' + * Sum: '/Add18' + * Sum: '/Add19' + * Sum: '/Add20' + * Sum: '/Add21' + * Sum: '/Add22' + * Sum: '/Add23' + */ + rtDW.Status_Duct_Tgt_model_IO.DuctTgt_Vent_FL = (uint16_t)(rtb_Merge_b + 400); + rtDW.Status_Duct_Tgt_model_IO.DuctTgt_Foot_FL = (uint16_t)(rtb_y_ki + 400); + rtDW.Status_Duct_Tgt_model_IO.DuctTgt_Vent_FR = (uint16_t)(rtb_FLU_tg_correct1 + + 400); + rtDW.Status_Duct_Tgt_model_IO.DuctTgt_Foot_FR = (uint16_t)(rtb_y_he + 400); + rtDW.Status_Duct_Tgt_model_IO.DuctTgt_RL = (uint16_t)(rtb_y_jh + 400); + rtDW.Status_Duct_Tgt_model_IO.DuctTgt_RR = (uint16_t)(rtDW.Duct_RR_Tg + 400); + + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + rtDW.Status_Duct_Select_model_IO.Duct_FL = 0U; + rtDW.Status_Duct_Select_model_IO.Duct_FR = 0U; + rtDW.Status_Duct_Select_model_IO.Duct_RL = 0U; + rtDW.Status_Duct_Select_model_IO.Duct_RR = 0U; + + /* BusCreator: '/Bus Creator1' incorporates: + * DataStoreRead: '/Data Store Read27' + * DataStoreRead: '/Data Store Read28' + * DataStoreWrite: '/Data Store Write1' + * DataTypeConversion: '/Data Type Conversion6' + * DataTypeConversion: '/Data Type Conversion7' + */ + rtDW.Status_Eva_Tgt_model_IO.EvaTgt_F = (uint16_t)Eva_F_tg; + rtDW.Status_Eva_Tgt_model_IO.EvaTgt_R = (uint16_t)Eva_R_tg; + + /* BusCreator: '/Bus Creator3' incorporates: + * DataStoreRead: '/Data Store Read18' + * DataStoreRead: '/Data Store Read19' + * DataStoreRead: '/Data Store Read20' + * DataStoreWrite: '/Data Store Write3' + */ + rtDW.Status_Actuator_model_IO.Motor_Def = rtDW.MaxPositionCh0_private[0]; + rtDW.Status_Actuator_model_IO.Motor_Vent_SFL = rtDW.MaxPositionCh0_private[4]; + rtDW.Status_Actuator_model_IO.Motor_Vent_CFL = rtDW.MaxPositionCh0_private[5]; + rtDW.Status_Actuator_model_IO.Motor_Foot_1FL = rtDW.MaxPositionCh0_private[7]; + rtDW.Status_Actuator_model_IO.Motor_Foot_2FL = rtDW.MaxPositionCh0_private[8]; + rtDW.Status_Actuator_model_IO.Motor_Vent_CFR = rtDW.MaxPositionCh1_private[1]; + rtDW.Status_Actuator_model_IO.Motor_Vent_SFR = rtDW.MaxPositionCh1_private[2]; + rtDW.Status_Actuator_model_IO.Motor_Foot_1FR = rtDW.MaxPositionCh1_private[4]; + rtDW.Status_Actuator_model_IO.Motor_Foot_2FR = rtDW.MaxPositionCh1_private[5]; + rtDW.Status_Actuator_model_IO.Motor_Vent_SRL = rtDW.MaxPositionCh2_private[2]; + rtDW.Status_Actuator_model_IO.Motor_Vent_CRL = rtDW.MaxPositionCh2_private[4]; + rtDW.Status_Actuator_model_IO.Motor_Foot_RL = rtDW.MaxPositionCh2_private[3]; + rtDW.Status_Actuator_model_IO.Motor_Vent_CRR = rtDW.MaxPositionCh2_private[5]; + rtDW.Status_Actuator_model_IO.Motor_Vent_SRR = rtDW.MaxPositionCh2_private[7]; + rtDW.Status_Actuator_model_IO.Motor_Foot_RR = rtDW.MaxPositionCh2_private[6]; + rtDW.Status_Actuator_model_IO.Motor_Temp1_FL = rtDW.MaxPositionCh0_private[3]; + rtDW.Status_Actuator_model_IO.Motor_Temp2_FL = rtDW.MaxPositionCh0_private[6]; + rtDW.Status_Actuator_model_IO.Motor_Temp1_FR = rtDW.MaxPositionCh1_private[0]; + rtDW.Status_Actuator_model_IO.Motor_Temp2_FR = rtDW.MaxPositionCh1_private[3]; + rtDW.Status_Actuator_model_IO.Motor_Temp_RL = rtDW.MaxPositionCh2_private[0]; + rtDW.Status_Actuator_model_IO.Motor_Temp_RR = rtDW.MaxPositionCh2_private[1]; + rtDW.Status_Actuator_model_IO.Motor_REC = rtDW.MaxPositionCh0_private[1]; + rtDW.Status_Actuator_model_IO.Motor_OSA = rtDW.MaxPositionCh0_private[2]; + rtDW.Status_Actuator_model_IO.Motor_SealingValve = + rtDW.MaxPositionCh2_private[8]; + + /* Switch: '/Switch' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read4' + * DataStoreRead: '/Data Store Read5' + * DataStoreWrite: '/Data Store Write' + */ + if (rtDW.CCU_MODE_FL > 0) { + rtDW.ModeIndex[0] = rtDW.Index_mode_FL_auto; + } else { + rtDW.ModeIndex[0] = rtDW.Index_mode_FL_manual; + } + + /* End of Switch: '/Switch' */ + + /* Switch: '/Switch1' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read6' + * DataStoreRead: '/Data Store Read7' + * DataStoreWrite: '/Data Store Write' + */ + if (rtDW.CCU_MODE_FR > 0) { + rtDW.ModeIndex[1] = rtDW.Index_mode_FR_auto; + } else { + rtDW.ModeIndex[1] = rtDW.Index_mode_FR_manual; + } + + /* End of Switch: '/Switch1' */ + + /* Switch: '/Switch2' incorporates: + * DataStoreRead: '/Data Store Read10' + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read9' + * DataStoreWrite: '/Data Store Write' + */ + if (rtDW.CCU_MODE_RL > 0) { + rtDW.ModeIndex[2] = (uint8_t)rtDW.Index_mode_RL_auto; + } else { + rtDW.ModeIndex[2] = rtDW.Index_mode_RL_manual; + } + + /* End of Switch: '/Switch2' */ + + /* Switch: '/Switch3' incorporates: + * DataStoreRead: '/Data Store Read12' + * DataStoreRead: '/Data Store Read3' + * DataStoreRead: '/Data Store Read8' + * DataStoreWrite: '/Data Store Write' + */ + if (rtDW.CCU_MODE_RR > 0) { + rtDW.ModeIndex[3] = (uint8_t)rtDW.Index_mode_RR_auto; + } else { + rtDW.ModeIndex[3] = rtDW.Index_mode_RR_manual; + } + + /* End of Switch: '/Switch3' */ + + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + index_start = 0.0; + + /* DataTypeConversion: '/Data Type Conversion' */ + for (i = 0; i < 9; i++) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read' + * Gain: '/Gain' + * Product: '/Divide' + */ + rtb_out_nc = rtDW.MaxPositionCh0_private[i]; + if (rtb_out_nc != 0) { + rtb_Add_be = (double)Actuator_Ch0_Status_Model.in_CPOS_ALL[i] / (double) + rtb_out_nc * 100.0; + } else { + rtb_Add_be = 0.0; + } + + /* End of Switch: '/Switch' */ + + /* Saturate: '/Saturation' incorporates: + * DataTypeConversion: '/Data Type Conversion' + */ + if (rtb_Add_be > 100.0) { + rtb_DataTypeConversion_b4q[i] = 100U; + } else { + rtb_DataTypeConversion_b4q[i] = (uint8_t)rtb_Add_be; + } + + /* End of Saturate: '/Saturation' */ + } + + /* End of DataTypeConversion: '/Data Type Conversion' */ + + /* Switch: '/Switch' incorporates: + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read2' + */ + if (rtDW.stepSig_private > 0) { + rtb_y_eo = rtDW.stepSig_private; + } else { + rtb_y_eo = 1; + } + + /* End of Switch: '/Switch' */ + + /* SwitchCase: '/Switch Case' */ + switch (rtb_y_eo) { + case 1: + /* Outputs for IfAction SubSystem: '/Stop Mode' incorporates: + * ActionPort: '/Action Port' + */ + /* If: '/If1' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write1' + * SignalConversion generated from: '/Bus Selector' + */ + if ((Actuator_Ch0_Status_Model.Busy == 0) && + (Actuator_Ch0_Status_Model.Error_Connect == 0)) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem2' incorporates: + * ActionPort: '/Action Port' + */ + for (i = 0; i < 9; i++) { + /* DataStoreWrite: '/Data Store Write1' */ + rtDW.COM_private[i] = 1U; + + /* DataStoreWrite: '/Data Store Write' */ + rtDW.MODE_private[i] = 2U; + } + + /* Merge: '/Merge' incorporates: + * Constant: '/Constant' + * Sum: '/step inc' + */ + rtB.Merge_f1 = (int8_t)(rtb_y_eo + 1); + + /* End of Outputs for SubSystem: '/If Action Subsystem2' */ + /* : if(LOGGER == 2) */ + } else { + /* Outputs for IfAction SubSystem: '/If Action Subsystem3' incorporates: + * ActionPort: '/Action Port' + */ + /* Merge: '/Merge' incorporates: + * SignalConversion generated from: '/stepIn' + */ + rtB.Merge_f1 = rtb_y_eo; + + /* End of Outputs for SubSystem: '/If Action Subsystem3' */ + } + + /* End of If: '/If1' */ + /* End of Outputs for SubSystem: '/Stop Mode' */ + break; + + case 2: + /* Outputs for IfAction SubSystem: '/Initial CPOS Min' incorporates: + * ActionPort: '/Action Port' + */ + /* If: '/If' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write1' + * SignalConversion generated from: '/Bus Selector' + */ + if ((Actuator_Ch0_Status_Model.Busy == 0) && + (Actuator_Ch0_Status_Model.Error_Connect == 0)) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem' incorporates: + * ActionPort: '/Action Port' + */ + for (i = 0; i < 9; i++) { + /* DataStoreWrite: '/Data Store Write' */ + rtDW.POS_private[i] = 6000U; + + /* DataStoreWrite: '/Data Store Write1' */ + rtDW.COM_private[i] = 2U; + } + + /* Merge: '/Merge' incorporates: + * Constant: '/Constant' + * Merge: '/Merge' + * Sum: '/step inc' + */ + rtB.Merge_f1 = (int8_t)(rtb_y_eo + 1); + + /* End of Outputs for SubSystem: '/If Action Subsystem' */ + /* : if(LOGGER == 2) */ + } else { + /* Outputs for IfAction SubSystem: '/If Action Subsystem3' incorporates: + * ActionPort: '/Action Port' + */ + /* Merge: '/Merge' incorporates: + * Merge: '/Merge' + * SignalConversion generated from: '/stepIn1' + */ + rtB.Merge_f1 = rtb_y_eo; + + /* End of Outputs for SubSystem: '/If Action Subsystem3' */ + } + + /* End of If: '/If' */ + /* End of Outputs for SubSystem: '/Initial CPOS Min' */ + break; + + case 3: + /* Outputs for IfAction SubSystem: '/Normal Mode' incorporates: + * ActionPort: '/Action Port' + */ + /* If: '/If1' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write1' + * SignalConversion generated from: '/Bus Selector' + */ + if ((Actuator_Ch0_Status_Model.Busy == 0) && + (Actuator_Ch0_Status_Model.Error_Connect == 0)) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem2' incorporates: + * ActionPort: '/Action Port' + */ + for (i = 0; i < 9; i++) { + /* DataStoreWrite: '/Data Store Write' */ + rtDW.MODE_private[i] = 0U; + + /* DataStoreWrite: '/Data Store Write1' */ + rtDW.COM_private[i] = 1U; + } + + /* Merge: '/Merge' incorporates: + * Constant: '/Constant' + * Sum: '/step inc' + */ + rtB.Merge_f1 = (int8_t)(rtb_y_eo + 1); + + /* End of Outputs for SubSystem: '/If Action Subsystem2' */ + /* : if(LOGGER == 2) */ + } else { + /* Outputs for IfAction SubSystem: '/If Action Subsystem3' incorporates: + * ActionPort: '/Action Port' + */ + /* Merge: '/Merge' incorporates: + * SignalConversion generated from: '/stepIn' + */ + rtB.Merge_f1 = rtb_y_eo; + + /* End of Outputs for SubSystem: '/If Action Subsystem3' */ + } + + /* End of If: '/If1' */ + /* End of Outputs for SubSystem: '/Normal Mode' */ + break; + + case 4: + /* Outputs for IfAction SubSystem: '/Move to position Min' incorporates: + * ActionPort: '/Action Port' + */ + /* If: '/If1' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write1' + * SignalConversion generated from: '/Bus Selector' + */ + if ((Actuator_Ch0_Status_Model.Busy == 0) && + (Actuator_Ch0_Status_Model.Error_Connect == 0)) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem2' incorporates: + * ActionPort: '/Action Port' + */ + for (i = 0; i < 9; i++) { + /* DataStoreWrite: '/Data Store Write4' incorporates: + * Constant: '/Constant1' + */ + rtDW.Autos_private[i] = 1U; + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/Constant10' + */ + rtDW.Stall_private[i] = 1U; + + /* DataStoreWrite: '/Data Store Write3' */ + rtDW.Lnoise_private[i] = 0U; + + /* DataStoreWrite: '/Data Store Write5' incorporates: + * Constant: '/Constant2' + */ + rtDW.Speed_private[i] = 3U; + + /* DataStoreWrite: '/Data Store Write6' incorporates: + * Constant: '/Constant3' + */ + rtDW.Coils_private[i] = 3U; + + /* DataStoreWrite: '/Data Store Write' */ + rtDW.POS_private[i] = 0U; + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * Constant: '/Constant9' + */ + rtDW.COM_private[i] = 3U; + } + + /* Merge: '/Merge' incorporates: + * Constant: '/Constant' + * Sum: '/step inc' + */ + rtB.Merge_f1 = (int8_t)(rtb_y_eo + 1); + + /* End of Outputs for SubSystem: '/If Action Subsystem2' */ + /* : if(LOGGER == 2) */ + } else { + /* Outputs for IfAction SubSystem: '/If Action Subsystem3' incorporates: + * ActionPort: '/Action Port' + */ + /* Merge: '/Merge' incorporates: + * SignalConversion generated from: '/stepIn' + */ + rtB.Merge_f1 = rtb_y_eo; + + /* End of Outputs for SubSystem: '/If Action Subsystem3' */ + } + + /* End of If: '/If1' */ + /* End of Outputs for SubSystem: '/Move to position Min' */ + break; + + case 5: + /* Outputs for IfAction SubSystem: '/Check Stall Min' incorporates: + * ActionPort: '/Action Port' + */ + /* Logic: '/Logical Operator3' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read' + * Logic: '/Logical Operator1' + * Logic: '/Logical Operator2' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator1' + */ + for (i = 0; i < 9; i++) { + rtb_LogicalOperator3_nq[i] = + ((Actuator_Ch0_Status_Model.in_Act_Stall_Slave[i] == 1) || + (Actuator_Ch0_Status_Model.in_CPOS_ALL[i] == 0) || + (rtDW.ErrorCalibration_private[i] == 0)); + } + + /* End of Logic: '/Logical Operator3' */ + + /* Logic: '/Logical Operator' incorporates: + * Logic: '/Logical Operator3' + */ + rtb_err = rtb_LogicalOperator3_nq[0]; + for (i = 0; i < 8; i++) { + rtb_err = (rtb_err && rtb_LogicalOperator3_nq[i + 1]); + } + + /* If: '/If2' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write1' + * DataTypeConversion: '/Data Type Conversion' + * DataTypeConversion: '/Data Type Conversion1' + * Logic: '/Logical Operator' + * SignalConversion generated from: '/Bus Selector' + */ + if ((Actuator_Ch0_Status_Model.Busy == 0) && + (Actuator_Ch0_Status_Model.Error_Connect == 0) && rtb_err) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem2' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write1' */ + for (i = 0; i < 9; i++) { + /* Switch: '/Switch' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + if (rtDW.ErrorCalibration_private[i] != 0) { + rtDW.MinPositionCh0_private[i] = + Actuator_Ch0_Status_Model.in_CPOS_ALL[i]; + } + + /* End of Switch: '/Switch' */ + } + + /* End of DataStoreWrite: '/Data Store Write1' */ + + /* Merge: '/Merge' incorporates: + * Constant: '/Constant' + * Sum: '/step inc' + */ + rtB.Merge_f1 = (int8_t)(rtb_y_eo + 1); + + /* End of Outputs for SubSystem: '/If Action Subsystem2' */ + /* : if(LOGGER == 2) */ + } else { + /* Outputs for IfAction SubSystem: '/If Action Subsystem3' incorporates: + * ActionPort: '/Action Port' + */ + /* Merge: '/Merge' incorporates: + * SignalConversion generated from: '/stepIn' + */ + rtB.Merge_f1 = rtb_y_eo; + + /* End of Outputs for SubSystem: '/If Action Subsystem3' */ + } + + /* End of If: '/If2' */ + /* End of Outputs for SubSystem: '/Check Stall Min' */ + break; + + case 6: + /* Outputs for IfAction SubSystem: '/Initial CPOS Max' incorporates: + * ActionPort: '/Action Port' + */ + /* If: '/If1' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write1' + * SignalConversion generated from: '/Bus Selector' + */ + if ((Actuator_Ch0_Status_Model.Busy == 0) && + (Actuator_Ch0_Status_Model.Error_Connect == 0)) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem2' incorporates: + * ActionPort: '/Action Port' + */ + for (i = 0; i < 9; i++) { + /* DataStoreWrite: '/Data Store Write1' */ + rtDW.COM_private[i] = 2U; + + /* DataStoreWrite: '/Data Store Write' */ + rtDW.POS_private[i] = 0U; + } + + /* Merge: '/Merge' incorporates: + * Constant: '/Constant' + * Sum: '/step inc' + */ + rtB.Merge_f1 = (int8_t)(rtb_y_eo + 1); + + /* End of Outputs for SubSystem: '/If Action Subsystem2' */ + /* : if(LOGGER == 2) */ + } else { + /* Outputs for IfAction SubSystem: '/If Action Subsystem3' incorporates: + * ActionPort: '/Action Port' + */ + /* Merge: '/Merge' incorporates: + * SignalConversion generated from: '/stepIn' + */ + rtB.Merge_f1 = rtb_y_eo; + + /* End of Outputs for SubSystem: '/If Action Subsystem3' */ + } + + /* End of If: '/If1' */ + /* End of Outputs for SubSystem: '/Initial CPOS Max' */ + break; + + case 7: + /* Outputs for IfAction SubSystem: '/Move to position Max' incorporates: + * ActionPort: '/Action Port' + */ + /* If: '/If1' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write1' + * SignalConversion generated from: '/Bus Selector' + */ + if ((Actuator_Ch0_Status_Model.Busy == 0) && + (Actuator_Ch0_Status_Model.Error_Connect == 0)) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem2' incorporates: + * ActionPort: '/Action Port' + */ + for (i = 0; i < 9; i++) { + /* DataStoreWrite: '/Data Store Write4' incorporates: + * Constant: '/Constant1' + */ + rtDW.Autos_private[i] = 1U; + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/Constant10' + */ + rtDW.Stall_private[i] = 1U; + + /* DataStoreWrite: '/Data Store Write3' */ + rtDW.Lnoise_private[i] = 0U; + + /* DataStoreWrite: '/Data Store Write5' incorporates: + * Constant: '/Constant2' + */ + rtDW.Speed_private[i] = 3U; + + /* DataStoreWrite: '/Data Store Write' */ + rtDW.POS_private[i] = 6000U; + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * Constant: '/Constant9' + */ + rtDW.COM_private[i] = 3U; + + /* DataStoreWrite: '/Data Store Write6' */ + rtDW.Coils_private[i] = 0U; + } + + /* Merge: '/Merge' incorporates: + * Constant: '/Constant' + * Sum: '/step inc' + */ + rtB.Merge_f1 = (int8_t)(rtb_y_eo + 1); + + /* End of Outputs for SubSystem: '/If Action Subsystem2' */ + /* : if(LOGGER == 2) */ + } else { + /* Outputs for IfAction SubSystem: '/If Action Subsystem3' incorporates: + * ActionPort: '/Action Port' + */ + /* Merge: '/Merge' incorporates: + * SignalConversion generated from: '/stepIn' + */ + rtB.Merge_f1 = rtb_y_eo; + + /* End of Outputs for SubSystem: '/If Action Subsystem3' */ + } + + /* End of If: '/If1' */ + /* End of Outputs for SubSystem: '/Move to position Max' */ + break; + + case 8: + /* Outputs for IfAction SubSystem: '/Check Stall Max' incorporates: + * ActionPort: '/Action Port' + */ + /* Logic: '/Logical Operator3' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read' + * Logic: '/Logical Operator' + * Logic: '/Logical Operator2' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator1' + */ + for (i = 0; i < 9; i++) { + rtb_LogicalOperator3_nq[i] = + ((Actuator_Ch0_Status_Model.in_Act_Stall_Slave[i] == 1) || + (Actuator_Ch0_Status_Model.in_CPOS_ALL[i] == 6000) || + (rtDW.ErrorCalibration_private[i] == 0)); + } + + /* End of Logic: '/Logical Operator3' */ + + /* Logic: '/Logical Operator1' incorporates: + * Logic: '/Logical Operator3' + */ + rtb_err = rtb_LogicalOperator3_nq[0]; + for (i = 0; i < 8; i++) { + rtb_err = (rtb_err && rtb_LogicalOperator3_nq[i + 1]); + } + + /* If: '/If2' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write1' + * DataTypeConversion: '/Data Type Conversion' + * DataTypeConversion: '/Data Type Conversion1' + * Logic: '/Logical Operator1' + * SignalConversion generated from: '/Bus Selector' + */ + if ((Actuator_Ch0_Status_Model.Busy == 0) && + (Actuator_Ch0_Status_Model.Error_Connect == 0) && rtb_err) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem2' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write1' */ + for (i = 0; i < 9; i++) { + /* Switch: '/Switch' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + if (rtDW.ErrorCalibration_private[i] != 0) { + rtDW.MaxPositionCh0_private[i] = + Actuator_Ch0_Status_Model.in_CPOS_ALL[i]; + } + + /* End of Switch: '/Switch' */ + } + + /* End of DataStoreWrite: '/Data Store Write1' */ + + /* Merge: '/Merge' incorporates: + * Constant: '/Constant' + * Sum: '/step inc' + */ + rtB.Merge_f1 = (int8_t)(rtb_y_eo + 1); + + /* End of Outputs for SubSystem: '/If Action Subsystem2' */ + /* : if(LOGGER == 2) */ + } else { + /* Outputs for IfAction SubSystem: '/If Action Subsystem3' incorporates: + * ActionPort: '/Action Port' + */ + /* Merge: '/Merge' incorporates: + * SignalConversion generated from: '/stepIn' + */ + rtB.Merge_f1 = rtb_y_eo; + + /* End of Outputs for SubSystem: '/If Action Subsystem3' */ + } + + /* End of If: '/If2' */ + /* End of Outputs for SubSystem: '/Check Stall Max' */ + break; + + case 9: + /* Outputs for IfAction SubSystem: '/Homing' incorporates: + * ActionPort: '/Action Port' + */ + /* Product: '/Divide1' incorporates: + * Constant: '/ACT1' + * DataStoreRead: '/MAX ACT1T ' + */ + for (i = 0; i < 9; i++) { + rtb_Divide1_a4[i] = (double)rtDW.MaxPositionCh0_private[i] / (double) + rtConstP.pooled87[i]; + } + + /* End of Product: '/Divide1' */ + + /* SwitchCase: '/Switch Case' incorporates: + * DataStoreRead: '/Data Store Read4' + */ + switch (rtDW.stepHoming_private) { + case 0: + /* Outputs for IfAction SubSystem: '/Switch Case Action Subsystem' incorporates: + * ActionPort: '/Action Port' + */ + for (i = 0; i < 9; i++) { + /* RelationalOperator: '/Compare' */ + rtb_Add_be = rtb_Divide1_a4[i]; + + /* Logic: '/Logical Operator' incorporates: + * Constant: '/Constant' + * Constant: '/Constant' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + */ + Enable_Comp_PID = ((rtb_Add_be >= 0.6) && (rtb_Add_be <= 1.5)); + rtb_LogicalOperator3_nq[i] = Enable_Comp_PID; + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write' + * Logic: '/Logical Operator' + * Logic: '/Logical Operator1' + */ + rtDW.ErrorCalibration_private[i] = (uint8_t)((!Enable_Comp_PID) && + (rtDW.ErrorCalibration_private[i] != 0)); + } + + /* Logic: '/Logical Operator1' */ + /* : if(LOGGER>0) */ + rtb_err = rtb_LogicalOperator3_nq[0]; + for (i = 0; i < 8; i++) { + rtb_err = (rtb_err && rtb_LogicalOperator3_nq[i + 1]); + } + + /* Switch: '/Switch' incorporates: + * Logic: '/Logical Operator1' + */ + if (rtb_err) { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant1' + */ + rtB.Merge_a = 4; + } else { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant' + */ + rtB.Merge_a = 1; + } + + /* End of Switch: '/Switch' */ + /* End of Outputs for SubSystem: '/Switch Case Action Subsystem' */ + break; + + case 1: + /* Outputs for IfAction SubSystem: '/Switch Case Action Subsystem1' incorporates: + * ActionPort: '/Action Port' + */ + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + for (i = 0; i < 9; i++) { + rtb_LogicalOperator3_nq[i] = (rtb_Divide1_a4[i] > 1.5); + } + + /* End of RelationalOperator: '/Compare' */ + + /* Logic: '/Logical Operator' */ + rtb_err = rtb_LogicalOperator3_nq[0]; + for (i = 0; i < 8; i++) { + rtb_err = (rtb_err || rtb_LogicalOperator3_nq[i + 1]); + } + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * DataStoreWrite: '/Data Store Write1' + * Logic: '/Logical Operator' + */ + rtDW.CCU_ActuatorErrF_Stat_private = rtb_err; + for (i = 0; i < 9; i++) { + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * DataStoreWrite: '/Data Store Write2' + */ + Enable_Comp_PID = rtb_LogicalOperator3_nq[i]; + rtDW.COM_private[i] = Enable_Comp_PID; + + /* DataTypeConversion: '/Data Type Conversion2' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write3' + * Logic: '/Logical Operator1' + */ + rtDW.ErrorActuator[i] = (uint8_t)(Enable_Comp_PID || + (rtDW.ErrorActuator[i] != 0)); + + /* DataStoreWrite: '/Data Store Write' */ + rtDW.MODE_private[i] = 2U; + } + + /* MATLAB Function: '/Write ERROR' */ + /* : if(LOGGER>=0) */ + /* : for i = 1:numel(ErrCallibration) */ + for (i = 0; i < 9; i++) { + /* : if ErrCallibration(i) == 1 */ + if (rtb_LogicalOperator3_nq[i]) { + /* : fprintf('[LIN 1] Failure with actuator #%d\n', int16(i)); */ + printf("[LIN 1] Failure with actuator #%d\n", (int16_t)(i + 1)); + fflush(stdout); + } + } + + /* End of MATLAB Function: '/Write ERROR' */ + for (i = 0; i < 9; i++) { + /* Logic: '/Logical Operator1' */ + Enable_Comp_PID = rtb_LogicalOperator3_nq[i]; + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write' + * Logic: '/Logical Operator' + * Logic: '/Logical Operator1' + */ + rtDW.ErrorCalibration_private[i] = (uint8_t)((!Enable_Comp_PID) && + (rtDW.ErrorCalibration_private[i] != 0)); + + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.dtc_state_error_model[i + 54] = Enable_Comp_PID; + } + + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.stepSig_private = 1; + + /* Logic: '/Logical Operator2' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + /* : if(LOGGER>0) */ + rtb_err = (rtDW.ErrorCalibration_private[0] != 0); + for (i = 0; i < 8; i++) { + rtb_err = (rtb_err || (rtDW.ErrorCalibration_private[i + 1] != 0)); + } + + /* Switch: '/Switch' incorporates: + * Logic: '/Logical Operator2' + */ + if (rtb_err) { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant1' + */ + rtB.Merge_a = 2; + } else { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant1' + */ + rtB.Merge_a = 4; + } + + /* End of Switch: '/Switch' */ + /* End of Outputs for SubSystem: '/Switch Case Action Subsystem1' */ + break; + + case 2: + /* Outputs for IfAction SubSystem: '/Switch Case Action Subsystem2' incorporates: + * ActionPort: '/Action Port' + */ + for (i = 0; i < 9; i++) { + /* RelationalOperator: '/Compare' */ + rtb_Add_be = rtb_Divide1_a4[i]; + + /* Logic: '/Logical Operator3' incorporates: + * Constant: '/Constant' + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read' + * Logic: '/Logical Operator1' + * Logic: '/Logical Operator4' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + */ + Enable_Comp_PID = (((rtb_Add_be < 0.97) || (rtb_Add_be > 1.03)) && + (rtDW.ErrorCalibration_private[i] != 0)); + rtb_LogicalOperator3_nq[i] = Enable_Comp_PID; + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * DataStoreWrite: '/Data Store Write1' + */ + rtDW.ErrorCalibration_private[i] = Enable_Comp_PID; + } + + /* Logic: '/Logical Operator2' */ + /* : if(LOGGER>0) */ + rtb_err = rtb_LogicalOperator3_nq[0]; + for (i = 0; i < 8; i++) { + rtb_err = (rtb_err || rtb_LogicalOperator3_nq[i + 1]); + } + + /* Switch: '/Switch' incorporates: + * Logic: '/Logical Operator2' + */ + if (rtb_err) { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant3' + */ + rtB.Merge_a = 3; + } else { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant1' + */ + rtB.Merge_a = 4; + } + + /* End of Switch: '/Switch' */ + /* End of Outputs for SubSystem: '/Switch Case Action Subsystem2' */ + break; + + case 3: + /* Outputs for IfAction SubSystem: '/Switch Case Action Subsystem3' incorporates: + * ActionPort: '/Action Port' + */ + /* If: '/If' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + /* : if(LOGGER>1) */ + if (rtDW.ErrorHomming_private < 10.0) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem' incorporates: + * ActionPort: '/Action Port' + */ + /* MATLAB Function: '/MATLAB Function' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read1' + */ + MATLABFunction(rtDW.Start_timer_n, rtDW.t_now, &rtb_Subtract, + &rtDW.sf_MATLABFunction_h); + + /* If: '/If' */ + /* : if(LOGGER>1) */ + if (rtb_Subtract > 3600000U) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem' incorporates: + * ActionPort: '/Action Port' + */ + /* Merge: '/Merge' */ + IfActionSubsystem_h(&rtB.Merge_a, &rtDW.ErrorHomming_private, + &rtDW.Start_timer_n, &rtDW.stepSig_private); + + /* End of Outputs for SubSystem: '/If Action Subsystem' */ + } else { + /* Outputs for IfAction SubSystem: '/If Action Subsystem1' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/Constant3' + */ + rtDW.Start_timer_n = 1.0; + + /* DataTypeConversion: '/Data Type Conversion2' */ + for (i = 0; i < 9; i++) { + rtb_DataTypeConversion_mo[i] = (uint8_t)rtb_out_ea[i]; + } + + /* End of DataTypeConversion: '/Data Type Conversion2' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Concatenate: '/Vector Concatenate' + */ + rtDW.BUS_ADR_private[0] = rtb_DataTypeConversion_mo[8]; + + /* DataStoreRead: '/Data Store Read4' incorporates: + * Concatenate: '/Vector Concatenate' + */ + rtDW.BUS_ADR_private[1] = rtb_DataTypeConversion3_gz; + + /* DataStoreRead: '/Data Store Read3' incorporates: + * Concatenate: '/Vector Concatenate' + */ + rtDW.BUS_ADR_private[2] = rtb_Saturation4_f; + + /* DataStoreRead: '/Data Store Read' incorporates: + * Concatenate: '/Vector Concatenate' + */ + rtDW.BUS_ADR_private[3] = rtDW.PID_TempFUL; + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Concatenate: '/Vector Concatenate' + */ + rtDW.BUS_ADR_private[4] = rtb_DataTypeConversion_mo[1]; + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Concatenate: '/Vector Concatenate' + */ + rtDW.BUS_ADR_private[5] = rtb_DataTypeConversion_mo[0]; + + /* DataStoreRead: '/Data Store Read6' incorporates: + * Concatenate: '/Vector Concatenate' + */ + rtDW.BUS_ADR_private[6] = rtDW.PID_TempFLL; + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Concatenate: '/Vector Concatenate' + */ + rtDW.BUS_ADR_private[7] = rtb_DataTypeConversion_mo[4]; + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Concatenate: '/Vector Concatenate' + */ + rtDW.BUS_ADR_private[8] = rtb_DataTypeConversion_mo[5]; + for (i = 0; i < 9; i++) { + /* Product: '/Product' */ + El_window_heating = rtDW.BUS_ADR_private[i]; + + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write' + * Product: '/Divide1' + * Product: '/Product' + */ + rtDW.POS_private[i] = (uint16_t)((double)(El_window_heating * + rtDW.MaxPositionCh0_private[i]) / 100.0); + + /* RelationalOperator: '/Relational Operator1' incorporates: + * DataStoreWrite: '/Data Store Write2' + */ + rtb_LogicalOperator3_nq[i] = (rtb_DataTypeConversion_b4q[i] == + El_window_heating); + } + + /* Logic: '/Logical Operator' */ + rtb_err = rtb_LogicalOperator3_nq[0]; + for (i = 0; i < 8; i++) { + rtb_err = (rtb_err && rtb_LogicalOperator3_nq[i + 1]); + } + + for (i = 0; i < 9; i++) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant4' + * Constant: '/Constant9' + * DataStoreWrite: '/Data Store Write1' + * Logic: '/Logical Operator' + */ + if (rtb_err) { + rtDW.COM_private[i] = 0U; + } else { + rtDW.COM_private[i] = 3U; + } + + /* End of Switch: '/Switch' */ + + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Concatenate: '/Vector Concatenate' + * Constant: '/Constant5' + * DataStoreWrite: '/Data Store Write2' + * DataStoreWrite: '/Data Store Write7' + * Product: '/Product' + * RelationalOperator: '/Relational Operator' + */ + rtDW.BUS_ADR_private[i] = (uint8_t)((uint32_t) + (rtb_DataTypeConversion_b4q[i] != rtDW.BUS_ADR_private[i]) * + rtConstP.pooled119[i]); + + /* DataStoreWrite: '/Data Store Write4' incorporates: + * Constant: '/Constant1' + */ + rtDW.Autos_private[i] = 1U; + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/Constant10' + */ + rtDW.Stall_private[i] = 1U; + + /* DataStoreWrite: '/Data Store Write3' incorporates: + * Constant: '/Constant11' + */ + rtDW.Lnoise_private[i] = 0U; + + /* DataStoreWrite: '/Data Store Write5' incorporates: + * Constant: '/Constant2' + */ + rtDW.Speed_private[i] = 3U; + + /* DataStoreWrite: '/Data Store Write6' incorporates: + * Constant: '/Constant3' + */ + rtDW.Coils_private[i] = 3U; + } + + /* Merge: '/Merge' incorporates: + * Constant: '/Constant1' + * Merge: '/Merge' + * SignalConversion generated from: '/Out1' + */ + rtB.Merge_a = 3; + + /* End of Outputs for SubSystem: '/If Action Subsystem1' */ + } + + /* End of If: '/If' */ + /* End of Outputs for SubSystem: '/If Action Subsystem' */ + } else { + /* Outputs for IfAction SubSystem: '/If Action Subsystem1' incorporates: + * ActionPort: '/Action Port' + */ + IfActionSubsystem1_h(&rtB.Merge_a, &rtDW.CCU_ActuatorErrF_Stat_private, + rtDW.COM_private, rtDW.ErrorActuator, + rtDW.ErrorCalibration_private, &index_start, + rtDW.MODE_private, rtDW.dtc_state_error_model); + + /* End of Outputs for SubSystem: '/If Action Subsystem1' */ + } + + /* End of If: '/If' */ + /* End of Outputs for SubSystem: '/Switch Case Action Subsystem3' */ + break; + + case 4: + /* Outputs for IfAction SubSystem: '/Switch Case Action Subsystem4' incorporates: + * ActionPort: '/Action Port' + */ + /* DataTypeConversion: '/Data Type Conversion2' */ + for (i = 0; i < 9; i++) { + rtb_DataTypeConversion_mo[i] = (uint8_t)rtb_out_ea[i]; + } + + /* End of DataTypeConversion: '/Data Type Conversion2' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Concatenate: '/Vector Concatenate' + */ + rtDW.BUS_ADR_private[0] = rtb_DataTypeConversion_mo[8]; + + /* DataStoreRead: '/Data Store Read4' incorporates: + * Concatenate: '/Vector Concatenate' + */ + rtDW.BUS_ADR_private[1] = rtb_DataTypeConversion3_gz; + + /* DataStoreRead: '/Data Store Read2' incorporates: + * Concatenate: '/Vector Concatenate' + */ + rtDW.BUS_ADR_private[2] = rtb_Saturation4_f; + + /* DataStoreRead: '/Data Store Read' incorporates: + * Concatenate: '/Vector Concatenate' + */ + rtDW.BUS_ADR_private[3] = rtDW.PID_TempFUL; + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Concatenate: '/Vector Concatenate' + */ + rtDW.BUS_ADR_private[4] = rtb_DataTypeConversion_mo[1]; + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Concatenate: '/Vector Concatenate' + */ + rtDW.BUS_ADR_private[5] = rtb_DataTypeConversion_mo[0]; + + /* DataStoreRead: '/Data Store Read6' incorporates: + * Concatenate: '/Vector Concatenate' + */ + rtDW.BUS_ADR_private[6] = rtDW.PID_TempFLL; + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Concatenate: '/Vector Concatenate' + */ + rtDW.BUS_ADR_private[7] = rtb_DataTypeConversion_mo[4]; + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Concatenate: '/Vector Concatenate' + */ + rtDW.BUS_ADR_private[8] = rtb_DataTypeConversion_mo[5]; + for (i = 0; i < 9; i++) { + /* Product: '/Product' */ + El_window_heating = rtDW.BUS_ADR_private[i]; + + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write' + * Product: '/Divide1' + * Product: '/Product' + */ + rtDW.POS_private[i] = (uint16_t)((double)(El_window_heating * + rtDW.MaxPositionCh0_private[i]) / 100.0); + + /* RelationalOperator: '/Relational Operator1' incorporates: + * DataStoreWrite: '/Data Store Write2' + */ + rtb_LogicalOperator3_nq[i] = (rtb_DataTypeConversion_b4q[i] == + El_window_heating); + } + + /* Logic: '/Logical Operator' */ + rtb_err = rtb_LogicalOperator3_nq[0]; + for (i = 0; i < 8; i++) { + rtb_err = (rtb_err && rtb_LogicalOperator3_nq[i + 1]); + } + + for (i = 0; i < 9; i++) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant4' + * Constant: '/Constant9' + * DataStoreWrite: '/Data Store Write1' + * Logic: '/Logical Operator' + */ + if (rtb_err) { + rtDW.COM_private[i] = 0U; + } else { + rtDW.COM_private[i] = 3U; + } + + /* End of Switch: '/Switch' */ + + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Concatenate: '/Vector Concatenate' + * Constant: '/Constant5' + * DataStoreWrite: '/Data Store Write2' + * DataStoreWrite: '/Data Store Write7' + * Product: '/Product' + * RelationalOperator: '/Relational Operator' + */ + rtDW.BUS_ADR_private[i] = (uint8_t)((uint32_t) + (rtb_DataTypeConversion_b4q[i] != rtDW.BUS_ADR_private[i]) * + rtConstP.pooled119[i]); + + /* DataStoreWrite: '/Data Store Write4' incorporates: + * Constant: '/Constant1' + */ + rtDW.Autos_private[i] = 1U; + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/Constant10' + */ + rtDW.Stall_private[i] = 1U; + + /* DataStoreWrite: '/Data Store Write3' incorporates: + * Constant: '/Constant11' + */ + rtDW.Lnoise_private[i] = 0U; + + /* DataStoreWrite: '/Data Store Write5' incorporates: + * Constant: '/Constant2' + */ + rtDW.Speed_private[i] = 3U; + + /* DataStoreWrite: '/Data Store Write6' incorporates: + * Constant: '/Constant3' + */ + rtDW.Coils_private[i] = 3U; + } + + /* Merge: '/Merge' incorporates: + * Constant: '/Constant1' + * SignalConversion generated from: '/step' + */ + rtB.Merge_a = 4; + + /* End of Outputs for SubSystem: '/Switch Case Action Subsystem4' */ + break; + } + + /* End of SwitchCase: '/Switch Case' */ + + /* DataStoreWrite: '/Data Store Write2' */ + rtDW.stepHoming_private = rtB.Merge_a; + + /* Merge: '/Merge' incorporates: + * DataStoreRead: '/Data Store Read7' + */ + rtB.Merge_f1 = rtDW.stepSig_private; + + /* End of Outputs for SubSystem: '/Homing' */ + break; + } + + /* End of SwitchCase: '/Switch Case' */ + + /* DataStoreWrite: '/Finish write stepSig' */ + rtDW.stepSig_private = rtB.Merge_f1; + for (i = 0; i < 9; i++) { + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read3' + * DataStoreRead: '/Data Store Read4' + * DataStoreRead: '/Data Store Read5' + * DataStoreRead: '/Data Store Read6' + * DataStoreRead: '/Data Store Read7' + * DataStoreRead: '/Data Store Read8' + * DataStoreWrite: '/Data Store Write' + */ + Actuator_Ch0_Command_Model.POS[i] = rtDW.POS_private[i]; + Actuator_Ch0_Command_Model.BUS_ADR[i] = rtDW.BUS_ADR_private[i]; + Actuator_Ch0_Command_Model.MODE[i] = rtDW.MODE_private[i]; + Actuator_Ch0_Command_Model.COM[i] = rtDW.COM_private[i]; + Actuator_Ch0_Command_Model.Stall_SET[i] = rtDW.Stall_private[i]; + Actuator_Ch0_Command_Model.Lnoise_SET[i] = rtDW.Lnoise_private[i]; + Actuator_Ch0_Command_Model.Autos_SET[i] = rtDW.Autos_private[i]; + Actuator_Ch0_Command_Model.Speed_SET[i] = rtDW.Speed_private[i]; + Actuator_Ch0_Command_Model.Coils_Stop_SET[i] = rtDW.Coils_private[i]; + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read2' + */ + rtb_LogicalOperator3_nq[i] = (rtDW.ErrorCalibration_private[i] == 0); + } + + /* Logic: '/Logical Operator' */ + rtb_err = rtb_LogicalOperator3_nq[0]; + for (i = 0; i < 8; i++) { + rtb_err = (rtb_err || rtb_LogicalOperator3_nq[i + 1]); + } + + for (i = 0; i < 9; i++) { + /* Switch: '/Switch1' incorporates: + * Concatenate: '/Vector Concatenate' + * Constant: '/Constant' + * Constant: '/Constant3' + * DataStoreRead: '/Data Store Read2' + * DataStoreWrite: '/Data Store Write7' + * Logic: '/Logical Operator' + * Product: '/Product' + */ + if (rtb_err) { + rtDW.BUS_ADR_private[i] = (uint8_t)((uint32_t) + rtDW.ErrorCalibration_private[i] * rtConstP.pooled119[i]); + } else { + rtDW.BUS_ADR_private[i] = 0U; + } + + /* End of Switch: '/Switch1' */ + + /* DataStoreWrite: '/Data Store Write' */ + rtDW.COM_private[i] = 0U; + } + + /* DataTypeConversion: '/Data Type Conversion' */ + for (i = 0; i < 6; i++) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read' + * Gain: '/Gain' + * Product: '/Divide' + */ + rtb_out_nc = rtDW.MaxPositionCh1_private[i]; + if (rtb_out_nc != 0) { + rtb_Add_be = (double)Actuator_Ch1_Status_Model.in_CPOS_ALL[i] / (double) + rtb_out_nc * 100.0; + } else { + rtb_Add_be = 0.0; + } + + /* End of Switch: '/Switch' */ + + /* Saturate: '/Saturation' */ + if (rtb_Add_be > 100.0) { + rtb_DataTypeConversion_mo[i] = 100U; + } else { + rtb_DataTypeConversion_mo[i] = (uint8_t)rtb_Add_be; + } + + /* End of Saturate: '/Saturation' */ + } + + /* End of DataTypeConversion: '/Data Type Conversion' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant1' + */ + rtb_DataTypeConversion_mo[6] = 0U; + rtb_DataTypeConversion_mo[7] = 0U; + rtb_DataTypeConversion_mo[8] = 0U; + + /* DataStoreWrite: '/Data Store Write2' */ + for (i = 0; i < 9; i++) { + Actuator_pos_percent_Ch1[i] = rtb_DataTypeConversion_mo[i]; + } + + /* Switch: '/Switch' incorporates: + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read2' + */ + if (rtDW.stepSig_private_h > 0) { + rtb_y_eo = rtDW.stepSig_private_h; + } else { + rtb_y_eo = 1; + } + + /* End of Switch: '/Switch' */ + + /* SwitchCase: '/Switch Case' */ + switch (rtb_y_eo) { + case 1: + /* Outputs for IfAction SubSystem: '/Stop Mode' incorporates: + * ActionPort: '/Action Port' + */ + /* If: '/If1' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write1' + * SignalConversion generated from: '/Bus Selector' + */ + if ((Actuator_Ch1_Status_Model.Busy == 0) && + (Actuator_Ch1_Status_Model.Error_Connect == 0)) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem2' incorporates: + * ActionPort: '/Action Port' + */ + for (i = 0; i < 9; i++) { + /* DataStoreWrite: '/Data Store Write1' */ + rtDW.COM_private_g[i] = 1U; + + /* DataStoreWrite: '/Data Store Write' */ + rtDW.MODE_private_b[i] = 2U; + } + + /* Merge: '/Merge' incorporates: + * Constant: '/Constant' + * Sum: '/step inc' + */ + rtB.Merge_e = (int8_t)(rtb_y_eo + 1); + + /* MATLAB Function: '/Write' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + /* : if(LOGGER == 2) */ + if (index_start == 2.0) { + /* : fprintf('[LIN 2] Stop Mode\n'); */ + printf("[LIN 2] Stop Mode\n"); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + /* End of Outputs for SubSystem: '/If Action Subsystem2' */ + } else { + /* Outputs for IfAction SubSystem: '/If Action Subsystem3' incorporates: + * ActionPort: '/Action Port' + */ + /* Merge: '/Merge' incorporates: + * SignalConversion generated from: '/stepIn' + */ + rtB.Merge_e = rtb_y_eo; + + /* End of Outputs for SubSystem: '/If Action Subsystem3' */ + } + + /* End of If: '/If1' */ + /* End of Outputs for SubSystem: '/Stop Mode' */ + break; + + case 2: + /* Outputs for IfAction SubSystem: '/Initial CPOS Min' incorporates: + * ActionPort: '/Action Port' + */ + /* If: '/If' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write1' + * SignalConversion generated from: '/Bus Selector' + */ + if ((Actuator_Ch1_Status_Model.Busy == 0) && + (Actuator_Ch1_Status_Model.Error_Connect == 0)) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem' incorporates: + * ActionPort: '/Action Port' + */ + for (i = 0; i < 9; i++) { + /* DataStoreWrite: '/Data Store Write' */ + rtDW.POS_private_m[i] = 6000U; + + /* DataStoreWrite: '/Data Store Write1' */ + rtDW.COM_private_g[i] = 2U; + } + + /* Merge: '/Merge' incorporates: + * Constant: '/Constant' + * Merge: '/Merge' + * Sum: '/step inc' + */ + rtB.Merge_e = (int8_t)(rtb_y_eo + 1); + + /* MATLAB Function: '/Write' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + /* : if(LOGGER == 2) */ + if (index_start == 2.0) { + /* : fprintf('[LIN 2] Initial CPOS Min\n'); */ + printf("[LIN 2] Initial CPOS Min\n"); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + /* End of Outputs for SubSystem: '/If Action Subsystem' */ + } else { + /* Outputs for IfAction SubSystem: '/If Action Subsystem3' incorporates: + * ActionPort: '/Action Port' + */ + /* Merge: '/Merge' incorporates: + * Merge: '/Merge' + * SignalConversion generated from: '/stepIn1' + */ + rtB.Merge_e = rtb_y_eo; + + /* End of Outputs for SubSystem: '/If Action Subsystem3' */ + } + + /* End of If: '/If' */ + /* End of Outputs for SubSystem: '/Initial CPOS Min' */ + break; + + case 3: + /* Outputs for IfAction SubSystem: '/Normal Mode' incorporates: + * ActionPort: '/Action Port' + */ + /* If: '/If1' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write1' + * SignalConversion generated from: '/Bus Selector' + */ + if ((Actuator_Ch1_Status_Model.Busy == 0) && + (Actuator_Ch1_Status_Model.Error_Connect == 0)) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem2' incorporates: + * ActionPort: '/Action Port' + */ + for (i = 0; i < 9; i++) { + /* DataStoreWrite: '/Data Store Write' */ + rtDW.MODE_private_b[i] = 0U; + + /* DataStoreWrite: '/Data Store Write1' */ + rtDW.COM_private_g[i] = 1U; + } + + /* Merge: '/Merge' incorporates: + * Constant: '/Constant' + * Sum: '/step inc' + */ + rtB.Merge_e = (int8_t)(rtb_y_eo + 1); + + /* MATLAB Function: '/Write' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + /* : if(LOGGER == 2) */ + if (index_start == 2.0) { + /* : fprintf('LIN 2] Normal Mode\n'); */ + printf("LIN 2] Normal Mode\n"); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + /* End of Outputs for SubSystem: '/If Action Subsystem2' */ + } else { + /* Outputs for IfAction SubSystem: '/If Action Subsystem3' incorporates: + * ActionPort: '/Action Port' + */ + /* Merge: '/Merge' incorporates: + * SignalConversion generated from: '/stepIn' + */ + rtB.Merge_e = rtb_y_eo; + + /* End of Outputs for SubSystem: '/If Action Subsystem3' */ + } + + /* End of If: '/If1' */ + /* End of Outputs for SubSystem: '/Normal Mode' */ + break; + + case 4: + /* Outputs for IfAction SubSystem: '/Move to position Min' incorporates: + * ActionPort: '/Action Port' + */ + /* If: '/If1' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write1' + * SignalConversion generated from: '/Bus Selector' + */ + if ((Actuator_Ch1_Status_Model.Busy == 0) && + (Actuator_Ch1_Status_Model.Error_Connect == 0)) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem2' incorporates: + * ActionPort: '/Action Port' + */ + for (i = 0; i < 9; i++) { + /* DataStoreWrite: '/Data Store Write4' incorporates: + * Constant: '/Constant1' + */ + rtDW.Autos_private_n[i] = 1U; + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/Constant10' + */ + rtDW.Stall_private_l[i] = 1U; + + /* DataStoreWrite: '/Data Store Write3' */ + rtDW.Lnoise_private_n[i] = 0U; + + /* DataStoreWrite: '/Data Store Write5' incorporates: + * Constant: '/Constant2' + */ + rtDW.Speed_private_j[i] = 3U; + + /* DataStoreWrite: '/Data Store Write6' incorporates: + * Constant: '/Constant3' + */ + rtDW.Coils_private_c[i] = 3U; + + /* DataStoreWrite: '/Data Store Write' */ + rtDW.POS_private_m[i] = 0U; + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * Constant: '/Constant9' + */ + rtDW.COM_private_g[i] = 3U; + } + + /* Merge: '/Merge' incorporates: + * Constant: '/Constant' + * Sum: '/step inc' + */ + rtB.Merge_e = (int8_t)(rtb_y_eo + 1); + + /* MATLAB Function: '/Write' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + /* : if(LOGGER == 2) */ + if (index_start == 2.0) { + /* : fprintf('[LIN 2] Move to position Min\n'); */ + printf("[LIN 2] Move to position Min\n"); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + /* End of Outputs for SubSystem: '/If Action Subsystem2' */ + } else { + /* Outputs for IfAction SubSystem: '/If Action Subsystem3' incorporates: + * ActionPort: '/Action Port' + */ + /* Merge: '/Merge' incorporates: + * SignalConversion generated from: '/stepIn' + */ + rtB.Merge_e = rtb_y_eo; + + /* End of Outputs for SubSystem: '/If Action Subsystem3' */ + } + + /* End of If: '/If1' */ + /* End of Outputs for SubSystem: '/Move to position Min' */ + break; + + case 5: + /* Outputs for IfAction SubSystem: '/Check Stall Min' incorporates: + * ActionPort: '/Action Port' + */ + /* Logic: '/Logical Operator3' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read' + * Logic: '/Logical Operator1' + * Logic: '/Logical Operator2' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator1' + */ + for (i = 0; i < 6; i++) { + rtb_LogicalOperator3_k[i] = + ((Actuator_Ch1_Status_Model.in_Act_Stall_Slave[i] == 1) || + (Actuator_Ch1_Status_Model.in_CPOS_ALL[i] == 0) || + (rtDW.ErrorCalibration_private_p[i] == 0)); + } + + /* End of Logic: '/Logical Operator3' */ + + /* Logic: '/Logical Operator' incorporates: + * Logic: '/Logical Operator3' + */ + rtb_err = rtb_LogicalOperator3_k[0]; + for (i = 0; i < 5; i++) { + rtb_err = (rtb_err && rtb_LogicalOperator3_k[i + 1]); + } + + /* If: '/If2' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write1' + * DataTypeConversion: '/Data Type Conversion' + * DataTypeConversion: '/Data Type Conversion1' + * Logic: '/Logical Operator' + * SignalConversion generated from: '/Bus Selector' + */ + if ((Actuator_Ch1_Status_Model.Busy == 0) && + (Actuator_Ch1_Status_Model.Error_Connect == 0) && rtb_err) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem2' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write1' */ + for (i = 0; i < 9; i++) { + /* Switch: '/Switch' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + if (rtDW.ErrorCalibration_private_p[i] != 0) { + rtDW.MinPositionCh1_private[i] = + Actuator_Ch1_Status_Model.in_CPOS_ALL[i]; + } + + /* End of Switch: '/Switch' */ + } + + /* End of DataStoreWrite: '/Data Store Write1' */ + + /* Merge: '/Merge' incorporates: + * Constant: '/Constant' + * Sum: '/step inc' + */ + rtB.Merge_e = (int8_t)(rtb_y_eo + 1); + + /* MATLAB Function: '/Write' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + /* : if(LOGGER == 2) */ + if (index_start == 2.0) { + /* : fprintf('[LIN 2] Check Stall Min\n'); */ + printf("[LIN 2] Check Stall Min\n"); + fflush(stdout); + + /* : for i = 1:numel(data) */ + for (i = 0; i < 9; i++) { + /* : fprintf('[LIN 2] MIN = %d ', int16(data(i))); */ + rtb_out_h0 = Actuator_Ch1_Status_Model.in_CPOS_ALL[i]; + if (rtb_out_h0 > 32767) { + rtb_out_h0 = 32767U; + } + + printf("[LIN 2] MIN = %d ", (int16_t)rtb_out_h0); + fflush(stdout); + } + + /* : fprintf('\n'); */ + printf("\n"); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + /* End of Outputs for SubSystem: '/If Action Subsystem2' */ + } else { + /* Outputs for IfAction SubSystem: '/If Action Subsystem3' incorporates: + * ActionPort: '/Action Port' + */ + /* Merge: '/Merge' incorporates: + * SignalConversion generated from: '/stepIn' + */ + rtB.Merge_e = rtb_y_eo; + + /* End of Outputs for SubSystem: '/If Action Subsystem3' */ + } + + /* End of If: '/If2' */ + /* End of Outputs for SubSystem: '/Check Stall Min' */ + break; + + case 6: + /* Outputs for IfAction SubSystem: '/Initial CPOS Max' incorporates: + * ActionPort: '/Action Port' + */ + /* If: '/If1' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write1' + * SignalConversion generated from: '/Bus Selector' + */ + if ((Actuator_Ch1_Status_Model.Busy == 0) && + (Actuator_Ch1_Status_Model.Error_Connect == 0)) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem2' incorporates: + * ActionPort: '/Action Port' + */ + for (i = 0; i < 9; i++) { + /* DataStoreWrite: '/Data Store Write1' */ + rtDW.COM_private_g[i] = 2U; + + /* DataStoreWrite: '/Data Store Write' */ + rtDW.POS_private_m[i] = 0U; + } + + /* Merge: '/Merge' incorporates: + * Constant: '/Constant' + * Sum: '/step inc' + */ + rtB.Merge_e = (int8_t)(rtb_y_eo + 1); + + /* MATLAB Function: '/Write' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + /* : if(LOGGER == 2) */ + if (index_start == 2.0) { + /* : fprintf('[LIN 2] Initial CPOS Max\n'); */ + printf("[LIN 2] Initial CPOS Max\n"); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + /* End of Outputs for SubSystem: '/If Action Subsystem2' */ + } else { + /* Outputs for IfAction SubSystem: '/If Action Subsystem3' incorporates: + * ActionPort: '/Action Port' + */ + /* Merge: '/Merge' incorporates: + * SignalConversion generated from: '/stepIn' + */ + rtB.Merge_e = rtb_y_eo; + + /* End of Outputs for SubSystem: '/If Action Subsystem3' */ + } + + /* End of If: '/If1' */ + /* End of Outputs for SubSystem: '/Initial CPOS Max' */ + break; + + case 7: + /* Outputs for IfAction SubSystem: '/Move to position Max' incorporates: + * ActionPort: '/Action Port' + */ + /* If: '/If1' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write1' + * SignalConversion generated from: '/Bus Selector' + */ + if ((Actuator_Ch1_Status_Model.Busy == 0) && + (Actuator_Ch1_Status_Model.Error_Connect == 0)) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem2' incorporates: + * ActionPort: '/Action Port' + */ + for (i = 0; i < 9; i++) { + /* DataStoreWrite: '/Data Store Write4' incorporates: + * Constant: '/Constant1' + */ + rtDW.Autos_private_n[i] = 1U; + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/Constant10' + */ + rtDW.Stall_private_l[i] = 1U; + + /* DataStoreWrite: '/Data Store Write3' */ + rtDW.Lnoise_private_n[i] = 0U; + + /* DataStoreWrite: '/Data Store Write5' incorporates: + * Constant: '/Constant2' + */ + rtDW.Speed_private_j[i] = 3U; + + /* DataStoreWrite: '/Data Store Write6' incorporates: + * Constant: '/Constant3' + */ + rtDW.Coils_private_c[i] = 3U; + + /* DataStoreWrite: '/Data Store Write' */ + rtDW.POS_private_m[i] = 6000U; + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * Constant: '/Constant9' + */ + rtDW.COM_private_g[i] = 3U; + } + + /* Merge: '/Merge' incorporates: + * Constant: '/Constant' + * Sum: '/step inc' + */ + rtB.Merge_e = (int8_t)(rtb_y_eo + 1); + + /* MATLAB Function: '/Write' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + /* : if(LOGGER == 2) */ + if (index_start == 2.0) { + /* : fprintf('[LIN 2] Move to position Max\n'); */ + printf("[LIN 2] Move to position Max\n"); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + /* End of Outputs for SubSystem: '/If Action Subsystem2' */ + } else { + /* Outputs for IfAction SubSystem: '/If Action Subsystem3' incorporates: + * ActionPort: '/Action Port' + */ + /* Merge: '/Merge' incorporates: + * SignalConversion generated from: '/stepIn' + */ + rtB.Merge_e = rtb_y_eo; + + /* End of Outputs for SubSystem: '/If Action Subsystem3' */ + } + + /* End of If: '/If1' */ + /* End of Outputs for SubSystem: '/Move to position Max' */ + break; + + case 8: + /* Outputs for IfAction SubSystem: '/Check Stall Max' incorporates: + * ActionPort: '/Action Port' + */ + /* Logic: '/Logical Operator3' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read' + * Logic: '/Logical Operator' + * Logic: '/Logical Operator2' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator1' + */ + for (i = 0; i < 6; i++) { + rtb_LogicalOperator3_k[i] = + ((Actuator_Ch1_Status_Model.in_Act_Stall_Slave[i] == 1) || + (Actuator_Ch1_Status_Model.in_CPOS_ALL[i] == 6000) || + (rtDW.ErrorCalibration_private_p[i] == 0)); + } + + /* End of Logic: '/Logical Operator3' */ + + /* Logic: '/Logical Operator1' incorporates: + * Logic: '/Logical Operator3' + */ + rtb_err = rtb_LogicalOperator3_k[0]; + for (i = 0; i < 5; i++) { + rtb_err = (rtb_err && rtb_LogicalOperator3_k[i + 1]); + } + + /* If: '/If2' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write1' + * DataTypeConversion: '/Data Type Conversion' + * DataTypeConversion: '/Data Type Conversion1' + * Logic: '/Logical Operator1' + * SignalConversion generated from: '/Bus Selector' + */ + if ((Actuator_Ch1_Status_Model.Busy == 0) && + (Actuator_Ch1_Status_Model.Error_Connect == 0) && rtb_err) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem2' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write1' */ + for (i = 0; i < 9; i++) { + /* Switch: '/Switch' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + if (rtDW.ErrorCalibration_private_p[i] != 0) { + rtDW.MaxPositionCh1_private[i] = + Actuator_Ch1_Status_Model.in_CPOS_ALL[i]; + } else { + rtDW.MaxPositionCh1_private[i] = 0U; + } + + /* End of Switch: '/Switch' */ + } + + /* End of DataStoreWrite: '/Data Store Write1' */ + + /* Merge: '/Merge' incorporates: + * Constant: '/Constant' + * Sum: '/step inc' + */ + rtB.Merge_e = (int8_t)(rtb_y_eo + 1); + + /* MATLAB Function: '/Write' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + /* : if(LOGGER == 2) */ + if (index_start == 2.0) { + /* : fprintf('[LIN 2] Check Stall MAX\n'); */ + printf("[LIN 2] Check Stall MAX\n"); + fflush(stdout); + + /* : for i = 1:numel(data) */ + for (i = 0; i < 9; i++) { + /* : fprintf('[LIN 2] MAX = %d ', int16(data(i))); */ + rtb_out_h0 = Actuator_Ch1_Status_Model.in_CPOS_ALL[i]; + if (rtb_out_h0 > 32767) { + rtb_out_h0 = 32767U; + } + + printf("[LIN 2] MAX = %d ", (int16_t)rtb_out_h0); + fflush(stdout); + } + + /* : fprintf('\n'); */ + printf("\n"); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + /* End of Outputs for SubSystem: '/If Action Subsystem2' */ + } else { + /* Outputs for IfAction SubSystem: '/If Action Subsystem3' incorporates: + * ActionPort: '/Action Port' + */ + /* Merge: '/Merge' incorporates: + * SignalConversion generated from: '/stepIn' + */ + rtB.Merge_e = rtb_y_eo; + + /* End of Outputs for SubSystem: '/If Action Subsystem3' */ + } + + /* End of If: '/If2' */ + /* End of Outputs for SubSystem: '/Check Stall Max' */ + break; + + case 9: + /* Outputs for IfAction SubSystem: '/Homing' incorporates: + * ActionPort: '/Action Port' + */ + /* Product: '/Divide1' incorporates: + * Constant: '/ACT1' + * DataStoreRead: '/MAX ACT1T ' + */ + for (i = 0; i < 6; i++) { + rtb_Divide1_a4[i] = (double)rtDW.MaxPositionCh1_private[i] / (double) + rtConstP.ACT1_Value[i]; + } + + /* End of Product: '/Divide1' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant' + */ + rtb_Divide1_a4[6] = 1.0; + rtb_Divide1_a4[7] = 1.0; + rtb_Divide1_a4[8] = 1.0; + + /* SwitchCase: '/Switch Case' incorporates: + * DataStoreRead: '/Data Store Read4' + */ + switch (rtDW.stepHoming_private_f) { + case 0: + /* Outputs for IfAction SubSystem: '/Switch Case Action Subsystem' incorporates: + * ActionPort: '/Action Port' + */ + for (i = 0; i < 9; i++) { + /* RelationalOperator: '/Compare' */ + rtb_Add_be = rtb_Divide1_a4[i]; + + /* Logic: '/Logical Operator' incorporates: + * Constant: '/Constant' + * Constant: '/Constant' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + */ + Enable_Comp_PID = ((rtb_Add_be >= 0.6) && (rtb_Add_be <= 1.5)); + rtb_LogicalOperator3_nq[i] = Enable_Comp_PID; + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write' + * Logic: '/Logical Operator' + * Logic: '/Logical Operator1' + */ + rtDW.ErrorCalibration_private_p[i] = (uint8_t)((!Enable_Comp_PID) && + (rtDW.ErrorCalibration_private_p[i] != 0)); + } + + /* MATLAB Function: '/MAX POSITION' incorporates: + * DataStoreRead: '/Data Store Read5' + * DataStoreRead: '/MIN ACT1T 1' + * Logic: '/Logical Operator2' + */ + /* : if(LOGGER>0) */ + if (index_start > 0.0) { + /* : fprintf("[LIN 2] Homing 0\n"); */ + printf("[LIN 2] Homing 0\n"); + fflush(stdout); + + /* : for i = 1:numel(MAX) */ + for (i = 0; i < 6; i++) { + /* : fprintf('[LIN 2] ACT%d MAX = %d KOEF = %f Callibration = %d \n', int16(i), int16(MAX(i)), KOEF(i), int16(ERRORS(i))); */ + rtb_out_h0 = rtDW.MaxPositionCh1_private[i]; + if (rtb_out_h0 > 32767) { + rtb_out_h0 = 32767U; + } + + printf("[LIN 2] ACT%d MAX = %d KOEF = %f Callibration = %d \n", + (int16_t)(i + 1), (int16_t)rtb_out_h0, rtb_Divide1_a4[i], + (int16_t)!rtb_LogicalOperator3_nq[i]); + fflush(stdout); + } + } + + /* End of MATLAB Function: '/MAX POSITION' */ + + /* Logic: '/Logical Operator1' */ + rtb_err = rtb_LogicalOperator3_nq[0]; + for (i = 0; i < 8; i++) { + rtb_err = (rtb_err && rtb_LogicalOperator3_nq[i + 1]); + } + + /* Switch: '/Switch' incorporates: + * Logic: '/Logical Operator1' + */ + if (rtb_err) { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant1' + */ + rtB.Merge_p = 4; + } else { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant' + */ + rtB.Merge_p = 1; + } + + /* End of Switch: '/Switch' */ + /* End of Outputs for SubSystem: '/Switch Case Action Subsystem' */ + break; + + case 1: + /* Outputs for IfAction SubSystem: '/Switch Case Action Subsystem1' incorporates: + * ActionPort: '/Action Port' + */ + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + for (i = 0; i < 9; i++) { + rtb_LogicalOperator3_nq[i] = (rtb_Divide1_a4[i] > 1.5); + } + + /* End of RelationalOperator: '/Compare' */ + + /* Logic: '/Logical Operator' */ + rtb_err = rtb_LogicalOperator3_nq[0]; + for (i = 0; i < 8; i++) { + rtb_err = (rtb_err || rtb_LogicalOperator3_nq[i + 1]); + } + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * DataStoreWrite: '/Data Store Write1' + * Logic: '/Logical Operator' + */ + rtDW.CCU_ActuatorErrF_Stat_private = rtb_err; + for (i = 0; i < 9; i++) { + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * DataStoreWrite: '/Data Store Write2' + */ + Enable_Comp_PID = rtb_LogicalOperator3_nq[i]; + rtDW.COM_private_g[i] = Enable_Comp_PID; + + /* DataTypeConversion: '/Data Type Conversion2' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write3' + * Logic: '/Logical Operator1' + */ + rtDW.ErrorActuator_o[i] = (uint8_t)(Enable_Comp_PID || + (rtDW.ErrorActuator_o[i] != 0)); + + /* DataStoreWrite: '/Data Store Write' */ + rtDW.MODE_private_b[i] = 2U; + } + + /* MATLAB Function: '/Write ERROR' incorporates: + * DataStoreRead: '/Data Store Read6' + */ + /* : if(LOGGER>=0) */ + if (index_start >= 0.0) { + /* : for i = 1:numel(ErrCallibration) */ + for (i = 0; i < 9; i++) { + /* : if ErrCallibration(i) == 1 */ + if (rtb_LogicalOperator3_nq[i]) { + /* : fprintf('[LIN 2] Failure with actuator #%d\n', int16(i)); */ + printf("[LIN 2] Failure with actuator #%d\n", (int16_t)(i + 1)); + fflush(stdout); + } + } + } + + /* End of MATLAB Function: '/Write ERROR' */ + for (i = 0; i < 9; i++) { + /* Logic: '/Logical Operator1' */ + Enable_Comp_PID = rtb_LogicalOperator3_nq[i]; + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write' + * Logic: '/Logical Operator' + * Logic: '/Logical Operator1' + */ + rtDW.ErrorCalibration_private_p[i] = (uint8_t)((!Enable_Comp_PID) && + (rtDW.ErrorCalibration_private_p[i] != 0)); + + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.dtc_state_error_model[i + 54] = Enable_Comp_PID; + } + + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.stepSig_private_h = 1; + + /* MATLAB Function: '/MAX POSITION' incorporates: + * DataStoreRead: '/Data Store Read5' + * DataStoreRead: '/MIN ACT1T 1' + * DataStoreWrite: '/Data Store Write' + */ + /* : if(LOGGER>0) */ + if (index_start > 0.0) { + /* : fprintf("[LIN 2] Homing 1. Start Callibration \n"); */ + printf("[LIN 2] Homing 1. Start Callibration \n"); + fflush(stdout); + + /* : for i = 1:numel(MAX) */ + for (i = 0; i < 6; i++) { + /* : if(ERRORS(i)==1) */ + if (rtDW.ErrorCalibration_private_p[i] == 1) { + /* : fprintf('[LIN 2] ACT%d MAX = %d KOEF = %f Callibration = %d \n', int16(i), int16(MAX(i)), KOEF(i), int16(ERRORS(i))); */ + rtb_out_h0 = rtDW.MaxPositionCh1_private[i]; + if (rtb_out_h0 > 32767) { + rtb_out_h0 = 32767U; + } + + printf("[LIN 2] ACT%d MAX = %d KOEF = %f Callibration = %d \n", + (int16_t)(i + 1), (int16_t)rtb_out_h0, rtb_Divide1_a4[i], + (int16_t)rtDW.ErrorCalibration_private_p[i]); + fflush(stdout); + } + } + } + + /* End of MATLAB Function: '/MAX POSITION' */ + + /* Logic: '/Logical Operator2' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + rtb_err = (rtDW.ErrorCalibration_private_p[0] != 0); + for (i = 0; i < 8; i++) { + rtb_err = (rtb_err || (rtDW.ErrorCalibration_private_p[i + 1] != 0)); + } + + /* Switch: '/Switch' incorporates: + * Logic: '/Logical Operator2' + */ + if (rtb_err) { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant1' + */ + rtB.Merge_p = 2; + } else { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant1' + */ + rtB.Merge_p = 4; + } + + /* End of Switch: '/Switch' */ + /* End of Outputs for SubSystem: '/Switch Case Action Subsystem1' */ + break; + + case 2: + /* Outputs for IfAction SubSystem: '/Switch Case Action Subsystem2' incorporates: + * ActionPort: '/Action Port' + */ + for (i = 0; i < 9; i++) { + /* RelationalOperator: '/Compare' */ + rtb_Add_be = rtb_Divide1_a4[i]; + + /* Logic: '/Logical Operator3' incorporates: + * Constant: '/Constant' + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read' + * Logic: '/Logical Operator1' + * Logic: '/Logical Operator4' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + */ + Enable_Comp_PID = (((rtb_Add_be < 0.97) || (rtb_Add_be > 1.03)) && + (rtDW.ErrorCalibration_private_p[i] != 0)); + rtb_LogicalOperator3_nq[i] = Enable_Comp_PID; + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * DataStoreWrite: '/Data Store Write1' + */ + rtDW.ErrorCalibration_private_p[i] = Enable_Comp_PID; + } + + /* MATLAB Function: '/MAX POSITION' incorporates: + * DataStoreRead: '/Data Store Read5' + * DataStoreRead: '/MIN ACT1T 1' + */ + /* : if(LOGGER>0) */ + if (index_start > 0.0) { + /* : fprintf("[LIN 2] Homing 3. Callibration \n"); */ + printf("[LIN 2] Homing 3. Callibration \n"); + fflush(stdout); + + /* : for i = 1:numel(MAX) */ + for (i = 0; i < 6; i++) { + /* : if(ERRORS(i)==1) */ + if (rtb_LogicalOperator3_nq[i]) { + /* : fprintf('[LIN 2] ACT%d MAX = %d KOEF = %f Callibration = %d \n', int16(i), int16(MAX(i)), KOEF(i), int16(ERRORS(i))); */ + rtb_out_h0 = rtDW.MaxPositionCh1_private[i]; + if (rtb_out_h0 > 32767) { + rtb_out_h0 = 32767U; + } + + printf("[LIN 2] ACT%d MAX = %d KOEF = %f Callibration = %d \n", + (int16_t)(i + 1), (int16_t)rtb_out_h0, rtb_Divide1_a4[i], 1); + fflush(stdout); + } + } + } + + /* End of MATLAB Function: '/MAX POSITION' */ + + /* Logic: '/Logical Operator2' */ + rtb_err = rtb_LogicalOperator3_nq[0]; + for (i = 0; i < 8; i++) { + rtb_err = (rtb_err || rtb_LogicalOperator3_nq[i + 1]); + } + + /* Switch: '/Switch' incorporates: + * Logic: '/Logical Operator2' + */ + if (rtb_err) { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant3' + */ + rtB.Merge_p = 3; + } else { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant1' + */ + rtB.Merge_p = 4; + } + + /* End of Switch: '/Switch' */ + /* End of Outputs for SubSystem: '/Switch Case Action Subsystem2' */ + break; + + case 3: + /* Outputs for IfAction SubSystem: '/Switch Case Action Subsystem3' incorporates: + * ActionPort: '/Action Port' + */ + /* MATLAB Function: '/MAX POSITION' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read5' + */ + /* : if(LOGGER>1) */ + if (index_start > 1.0) { + /* : fprintf("[LIN 2] Homing 3. Start Time on step %d\n",int16(step)); */ + rtb_Add_be = rt_roundd(rtDW.ErrorHomming_private_h); + if (rtb_Add_be < 32768.0) { + if (rtb_Add_be >= -32768.0) { + rtb_FLU_tg_correct_aa = (int16_t)rtb_Add_be; + } else { + rtb_FLU_tg_correct_aa = INT16_MIN; + } + } else { + rtb_FLU_tg_correct_aa = INT16_MAX; + } + + printf("[LIN 2] Homing 3. Start Time on step %d\n", + rtb_FLU_tg_correct_aa); + fflush(stdout); + } + + /* End of MATLAB Function: '/MAX POSITION' */ + + /* If: '/If' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + if (rtDW.ErrorHomming_private_h < 10.0) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem' incorporates: + * ActionPort: '/Action Port' + */ + /* MATLAB Function: '/MATLAB Function' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read1' + */ + MATLABFunction(rtDW.Start_timer_j, rtDW.t_now, &rtb_dt_nx, + &rtDW.sf_MATLABFunction_hk); + + /* MATLAB Function: '/MAX POSITION' incorporates: + * DataStoreRead: '/Data Store Read5' + */ + /* : if(LOGGER>1) */ + if (index_start > 1.0) { + /* : fprintf("[LIN 2] Homing 3. Start TIme dt = %d \n",int32(data)); */ + rtb_Subtract = rtb_dt_nx; + if (rtb_dt_nx > 2147483647U) { + rtb_Subtract = 2147483647U; + } + + printf("[LIN 2] Homing 3. Start TIme dt = %d \n", (int32_t) + rtb_Subtract); + fflush(stdout); + } + + /* End of MATLAB Function: '/MAX POSITION' */ + + /* If: '/If' */ + if (rtb_dt_nx > 3600000U) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem' incorporates: + * ActionPort: '/Action Port' + */ + /* Merge: '/Merge' */ + IfActionSubsystem_h(&rtB.Merge_p, &rtDW.ErrorHomming_private_h, + &rtDW.Start_timer_j, &rtDW.stepSig_private_h); + + /* End of Outputs for SubSystem: '/If Action Subsystem' */ + } else { + /* Outputs for IfAction SubSystem: '/If Action Subsystem1' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/Constant3' + */ + rtDW.Start_timer_j = 1.0; + + /* DataStoreRead: '/Data Store Read' incorporates: + * Concatenate: '/LIN1' + */ + rtDW.BUS_ADR_private_j[0] = rtDW.PID_TempFUR; + + /* DataTypeConversion: '/Data Type Conversion2' */ + for (i = 0; i < 9; i++) { + rtb_DataTypeConversion_kl[i] = (uint8_t)rtb_out_ea[i]; + } + + /* End of DataTypeConversion: '/Data Type Conversion2' */ + + /* SignalConversion generated from: '/LIN1' incorporates: + * Concatenate: '/LIN1' + */ + rtDW.BUS_ADR_private_j[1] = rtb_DataTypeConversion_kl[2]; + + /* SignalConversion generated from: '/LIN1' incorporates: + * Concatenate: '/LIN1' + */ + rtDW.BUS_ADR_private_j[2] = rtb_DataTypeConversion_kl[3]; + + /* DataStoreRead: '/Data Store Read2' incorporates: + * Concatenate: '/LIN1' + */ + rtDW.BUS_ADR_private_j[3] = rtDW.PID_TempFRL; + + /* SignalConversion generated from: '/LIN1' incorporates: + * Concatenate: '/LIN1' + */ + rtDW.BUS_ADR_private_j[4] = rtb_DataTypeConversion_kl[6]; + + /* SignalConversion generated from: '/LIN1' incorporates: + * Concatenate: '/LIN1' + */ + rtDW.BUS_ADR_private_j[5] = rtb_DataTypeConversion_kl[7]; + + /* SignalConversion generated from: '/LIN1' incorporates: + * Concatenate: '/LIN1' + * DataStoreWrite: '/Data Store Write2' + */ + rtDW.BUS_ADR_private_j[6] = 0U; + + /* SignalConversion generated from: '/LIN1' incorporates: + * Concatenate: '/LIN1' + * DataStoreWrite: '/Data Store Write2' + */ + rtDW.BUS_ADR_private_j[7] = 0U; + + /* SignalConversion generated from: '/LIN1' incorporates: + * Concatenate: '/LIN1' + * DataStoreWrite: '/Data Store Write2' + */ + rtDW.BUS_ADR_private_j[8] = 0U; + for (i = 0; i < 9; i++) { + /* Product: '/Product' */ + El_window_heating = rtDW.BUS_ADR_private_j[i]; + + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write' + * Product: '/Divide1' + * Product: '/Product' + */ + rtDW.POS_private_m[i] = (uint16_t)((double)(El_window_heating * + rtDW.MaxPositionCh1_private[i]) / 100.0); + + /* RelationalOperator: '/Relational Operator1' incorporates: + * DataStoreWrite: '/Data Store Write2' + */ + rtb_LogicalOperator3_nq[i] = (rtb_DataTypeConversion_mo[i] == + El_window_heating); + } + + /* Logic: '/Logical Operator' */ + rtb_err = rtb_LogicalOperator3_nq[0]; + for (i = 0; i < 8; i++) { + rtb_err = (rtb_err && rtb_LogicalOperator3_nq[i + 1]); + } + + for (i = 0; i < 9; i++) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant4' + * Constant: '/Constant9' + * DataStoreWrite: '/Data Store Write1' + * Logic: '/Logical Operator' + */ + if (rtb_err) { + rtDW.COM_private_g[i] = 0U; + } else { + rtDW.COM_private_g[i] = 3U; + } + + /* End of Switch: '/Switch' */ + + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Concatenate: '/LIN1' + * Constant: '/Constant5' + * DataStoreWrite: '/Data Store Write2' + * DataStoreWrite: '/Data Store Write7' + * Product: '/Product' + * RelationalOperator: '/Relational Operator' + */ + rtDW.BUS_ADR_private_j[i] = (uint8_t)((uint32_t) + (rtb_DataTypeConversion_mo[i] != rtDW.BUS_ADR_private_j[i]) * + rtConstP.pooled119[i]); + + /* DataStoreWrite: '/Data Store Write4' incorporates: + * Constant: '/Constant1' + */ + rtDW.Autos_private_n[i] = 1U; + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/Constant10' + */ + rtDW.Stall_private_l[i] = 1U; + + /* DataStoreWrite: '/Data Store Write3' incorporates: + * Constant: '/Constant11' + */ + rtDW.Lnoise_private_n[i] = 0U; + + /* DataStoreWrite: '/Data Store Write5' incorporates: + * Constant: '/Constant2' + */ + rtDW.Speed_private_j[i] = 3U; + + /* DataStoreWrite: '/Data Store Write6' incorporates: + * Constant: '/Constant3' + */ + rtDW.Coils_private_c[i] = 3U; + } + + /* Merge: '/Merge' incorporates: + * Constant: '/Constant1' + * Merge: '/Merge' + * SignalConversion generated from: '/Out1' + */ + rtB.Merge_p = 3; + + /* End of Outputs for SubSystem: '/If Action Subsystem1' */ + } + + /* End of If: '/If' */ + /* End of Outputs for SubSystem: '/If Action Subsystem' */ + } else { + /* Outputs for IfAction SubSystem: '/If Action Subsystem1' incorporates: + * ActionPort: '/Action Port' + */ + IfActionSubsystem1_h(&rtB.Merge_p, &rtDW.CCU_ActuatorErrF_Stat_private, + rtDW.COM_private_g, rtDW.ErrorActuator_o, + rtDW.ErrorCalibration_private_p, &index_start, + rtDW.MODE_private_b, rtDW.dtc_state_error_model); + + /* End of Outputs for SubSystem: '/If Action Subsystem1' */ + } + + /* End of If: '/If' */ + /* End of Outputs for SubSystem: '/Switch Case Action Subsystem3' */ + break; + + case 4: + /* Outputs for IfAction SubSystem: '/Switch Case Action Subsystem4' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreRead: '/Data Store Read' incorporates: + * Concatenate: '/LIN1' + */ + rtDW.BUS_ADR_private_j[0] = rtDW.PID_TempFUR; + + /* DataTypeConversion: '/Data Type Conversion2' */ + for (i = 0; i < 9; i++) { + rtb_DataTypeConversion_kl[i] = (uint8_t)rtb_out_ea[i]; + } + + /* End of DataTypeConversion: '/Data Type Conversion2' */ + + /* SignalConversion generated from: '/LIN1' incorporates: + * Concatenate: '/LIN1' + */ + rtDW.BUS_ADR_private_j[1] = rtb_DataTypeConversion_kl[2]; + + /* SignalConversion generated from: '/LIN1' incorporates: + * Concatenate: '/LIN1' + */ + rtDW.BUS_ADR_private_j[2] = rtb_DataTypeConversion_kl[3]; + + /* DataStoreRead: '/Data Store Read2' incorporates: + * Concatenate: '/LIN1' + */ + rtDW.BUS_ADR_private_j[3] = rtDW.PID_TempFRL; + + /* SignalConversion generated from: '/LIN1' incorporates: + * Concatenate: '/LIN1' + */ + rtDW.BUS_ADR_private_j[4] = rtb_DataTypeConversion_kl[6]; + + /* SignalConversion generated from: '/LIN1' incorporates: + * Concatenate: '/LIN1' + */ + rtDW.BUS_ADR_private_j[5] = rtb_DataTypeConversion_kl[7]; + + /* SignalConversion generated from: '/LIN1' incorporates: + * Concatenate: '/LIN1' + * DataStoreWrite: '/Data Store Write2' + */ + rtDW.BUS_ADR_private_j[6] = 0U; + + /* SignalConversion generated from: '/LIN1' incorporates: + * Concatenate: '/LIN1' + * DataStoreWrite: '/Data Store Write2' + */ + rtDW.BUS_ADR_private_j[7] = 0U; + + /* SignalConversion generated from: '/LIN1' incorporates: + * Concatenate: '/LIN1' + * DataStoreWrite: '/Data Store Write2' + */ + rtDW.BUS_ADR_private_j[8] = 0U; + for (i = 0; i < 9; i++) { + /* Product: '/Product' */ + El_window_heating = rtDW.BUS_ADR_private_j[i]; + + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write' + * Product: '/Divide1' + * Product: '/Product' + */ + rtDW.POS_private_m[i] = (uint16_t)((double)(El_window_heating * + rtDW.MaxPositionCh1_private[i]) / 100.0); + + /* RelationalOperator: '/Relational Operator1' incorporates: + * DataStoreWrite: '/Data Store Write2' + */ + rtb_LogicalOperator3_nq[i] = (rtb_DataTypeConversion_mo[i] == + El_window_heating); + } + + /* Logic: '/Logical Operator' */ + rtb_err = rtb_LogicalOperator3_nq[0]; + for (i = 0; i < 8; i++) { + rtb_err = (rtb_err && rtb_LogicalOperator3_nq[i + 1]); + } + + for (i = 0; i < 9; i++) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant4' + * Constant: '/Constant9' + * DataStoreWrite: '/Data Store Write1' + * Logic: '/Logical Operator' + */ + if (rtb_err) { + rtDW.COM_private_g[i] = 0U; + } else { + rtDW.COM_private_g[i] = 3U; + } + + /* End of Switch: '/Switch' */ + + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Concatenate: '/LIN1' + * Constant: '/Constant5' + * DataStoreWrite: '/Data Store Write2' + * DataStoreWrite: '/Data Store Write7' + * Product: '/Product' + * RelationalOperator: '/Relational Operator' + */ + rtDW.BUS_ADR_private_j[i] = (uint8_t)((uint32_t) + (rtb_DataTypeConversion_mo[i] != rtDW.BUS_ADR_private_j[i]) * + rtConstP.pooled119[i]); + + /* DataStoreWrite: '/Data Store Write4' incorporates: + * Constant: '/Constant1' + */ + rtDW.Autos_private_n[i] = 1U; + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/Constant10' + */ + rtDW.Stall_private_l[i] = 1U; + + /* DataStoreWrite: '/Data Store Write3' incorporates: + * Constant: '/Constant11' + */ + rtDW.Lnoise_private_n[i] = 0U; + + /* DataStoreWrite: '/Data Store Write5' incorporates: + * Constant: '/Constant2' + */ + rtDW.Speed_private_j[i] = 3U; + + /* DataStoreWrite: '/Data Store Write6' incorporates: + * Constant: '/Constant3' + */ + rtDW.Coils_private_c[i] = 3U; + } + + /* Merge: '/Merge' incorporates: + * Constant: '/Constant1' + * SignalConversion generated from: '/step' + */ + rtB.Merge_p = 4; + + /* MATLAB Function: '/MAX POSITION' incorporates: + * DataStoreRead: '/Data Store Read5' + */ + /* : if(LOGGER>0) */ + if (index_start > 0.0) { + /* : fprintf("[LIN 2] Homing. Callibration successful \n"); */ + printf("[LIN 2] Homing. Callibration successful \n"); + fflush(stdout); + } + + /* End of MATLAB Function: '/MAX POSITION' */ + /* End of Outputs for SubSystem: '/Switch Case Action Subsystem4' */ + break; + } + + /* End of SwitchCase: '/Switch Case' */ + + /* DataStoreWrite: '/Data Store Write2' */ + rtDW.stepHoming_private_f = rtB.Merge_p; + + /* Merge: '/Merge' incorporates: + * DataStoreRead: '/Data Store Read7' + */ + rtB.Merge_e = rtDW.stepSig_private_h; + + /* End of Outputs for SubSystem: '/Homing' */ + break; + } + + /* End of SwitchCase: '/Switch Case' */ + + /* DataStoreWrite: '/Finish write stepSig' */ + rtDW.stepSig_private_h = rtB.Merge_e; + + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read3' + * DataStoreRead: '/Data Store Read4' + * DataStoreRead: '/Data Store Read5' + * DataStoreRead: '/Data Store Read6' + * DataStoreRead: '/Data Store Read7' + * DataStoreRead: '/Data Store Read8' + * DataStoreWrite: '/Data Store Write' + */ + for (i = 0; i < 9; i++) { + Actuator_Ch1_Command_Model.POS[i] = rtDW.POS_private_m[i]; + Actuator_Ch1_Command_Model.BUS_ADR[i] = rtDW.BUS_ADR_private_j[i]; + Actuator_Ch1_Command_Model.MODE[i] = rtDW.MODE_private_b[i]; + Actuator_Ch1_Command_Model.COM[i] = rtDW.COM_private_g[i]; + Actuator_Ch1_Command_Model.Stall_SET[i] = rtDW.Stall_private_l[i]; + Actuator_Ch1_Command_Model.Lnoise_SET[i] = rtDW.Lnoise_private_n[i]; + Actuator_Ch1_Command_Model.Autos_SET[i] = rtDW.Autos_private_n[i]; + Actuator_Ch1_Command_Model.Speed_SET[i] = rtDW.Speed_private_j[i]; + Actuator_Ch1_Command_Model.Coils_Stop_SET[i] = rtDW.Coils_private_c[i]; + } + + /* End of BusCreator: '/Bus Creator' */ + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read2' + */ + for (i = 0; i < 6; i++) { + rtb_Compare_le[i] = (rtDW.ErrorCalibration_private_p[i] == 0); + } + + /* End of RelationalOperator: '/Compare' */ + + /* Logic: '/Logical Operator' */ + rtb_err = rtb_Compare_le[0]; + for (i = 0; i < 5; i++) { + rtb_err = (rtb_err || rtb_Compare_le[i + 1]); + } + + /* Switch: '/Switch1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant3' + * DataStoreRead: '/Data Store Read2' + * Logic: '/Logical Operator' + * Product: '/Product' + */ + for (i = 0; i < 6; i++) { + if (rtb_err) { + rtb_DataTypeConversion_mo[i] = (uint8_t)((uint32_t) + rtDW.ErrorCalibration_private_p[i] * rtConstP.Constant3_Value[i]); + } else { + rtb_DataTypeConversion_mo[i] = 0U; + } + } + + /* End of Switch: '/Switch1' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant1' + */ + rtb_DataTypeConversion_mo[6] = 0U; + rtb_DataTypeConversion_mo[7] = 0U; + rtb_DataTypeConversion_mo[8] = 0U; + for (i = 0; i < 9; i++) { + /* DataStoreWrite: '/Data Store Write7' incorporates: + * Concatenate: '/LIN1' + */ + rtDW.BUS_ADR_private_j[i] = rtb_DataTypeConversion_mo[i]; + + /* DataStoreWrite: '/Data Store Write' */ + rtDW.COM_private_g[i] = 0U; + } + + /* DataTypeConversion: '/Data Type Conversion' */ + for (i = 0; i < 8; i++) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read' + * Gain: '/Gain' + * Product: '/Divide' + */ + rtb_out_nc = rtDW.MaxPositionCh2_private[i]; + if (rtb_out_nc != 0) { + rtb_Add_be = (double)Actuator_Ch2_Status_Model.in_CPOS_ALL[i] / (double) + rtb_out_nc * 100.0; + } else { + rtb_Add_be = 0.0; + } + + /* End of Switch: '/Switch' */ + + /* Saturate: '/Saturation' */ + if (rtb_Add_be > 100.0) { + rtb_DataTypeConversion_mo[i] = 100U; + } else { + rtb_DataTypeConversion_mo[i] = (uint8_t)rtb_Add_be; + } + + /* End of Saturate: '/Saturation' */ + } + + /* End of DataTypeConversion: '/Data Type Conversion' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant1' + */ + rtb_DataTypeConversion_mo[8] = 0U; + + /* DataStoreWrite: '/Data Store Write2' */ + for (i = 0; i < 9; i++) { + rtb_DataTypeConversion_kl[i] = rtb_DataTypeConversion_mo[i]; + } + + /* Switch: '/Switch' incorporates: + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read2' + */ + if (rtDW.stepSig_private_g > 0) { + rtb_y_eo = rtDW.stepSig_private_g; + } else { + rtb_y_eo = 1; + } + + /* End of Switch: '/Switch' */ + + /* SwitchCase: '/Switch Case' */ + switch (rtb_y_eo) { + case 1: + /* Outputs for IfAction SubSystem: '/Stop Mode' incorporates: + * ActionPort: '/Action Port' + */ + /* If: '/If1' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write1' + * SignalConversion generated from: '/Bus Selector' + */ + if ((Actuator_Ch2_Status_Model.Busy == 0) && + (Actuator_Ch2_Status_Model.Error_Connect == 0)) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem2' incorporates: + * ActionPort: '/Action Port' + */ + for (i = 0; i < 9; i++) { + /* DataStoreWrite: '/Data Store Write1' */ + rtDW.COM_private_k[i] = 1U; + + /* DataStoreWrite: '/Data Store Write' */ + rtDW.MODE_private_c[i] = 2U; + } + + /* Merge: '/Merge' incorporates: + * Constant: '/Constant' + * Sum: '/step inc' + */ + rtB.Merge_b4 = (int8_t)(rtb_y_eo + 1); + + /* MATLAB Function: '/Write' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + /* : if(LOGGER == 2) */ + if (index_start == 2.0) { + /* : fprintf('[LIN 3] Stop Mode\n'); */ + printf("[LIN 3] Stop Mode\n"); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + /* End of Outputs for SubSystem: '/If Action Subsystem2' */ + } else { + /* Outputs for IfAction SubSystem: '/If Action Subsystem3' incorporates: + * ActionPort: '/Action Port' + */ + /* Merge: '/Merge' incorporates: + * SignalConversion generated from: '/stepIn' + */ + rtB.Merge_b4 = rtb_y_eo; + + /* End of Outputs for SubSystem: '/If Action Subsystem3' */ + } + + /* End of If: '/If1' */ + /* End of Outputs for SubSystem: '/Stop Mode' */ + break; + + case 2: + /* Outputs for IfAction SubSystem: '/Initial CPOS Min' incorporates: + * ActionPort: '/Action Port' + */ + /* If: '/If' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write1' + * SignalConversion generated from: '/Bus Selector' + */ + if ((Actuator_Ch2_Status_Model.Busy == 0) && + (Actuator_Ch2_Status_Model.Error_Connect == 0)) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem' incorporates: + * ActionPort: '/Action Port' + */ + for (i = 0; i < 9; i++) { + /* DataStoreWrite: '/Data Store Write' */ + rtDW.POS_private_h[i] = 6000U; + + /* DataStoreWrite: '/Data Store Write1' */ + rtDW.COM_private_k[i] = 2U; + } + + /* Merge: '/Merge' incorporates: + * Constant: '/Constant' + * Merge: '/Merge' + * Sum: '/step inc' + */ + rtB.Merge_b4 = (int8_t)(rtb_y_eo + 1); + + /* MATLAB Function: '/Write' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + /* : if(LOGGER == 2) */ + if (index_start == 2.0) { + /* : fprintf('[LIN 3] Initial CPOS Min\n'); */ + printf("[LIN 3] Initial CPOS Min\n"); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + /* End of Outputs for SubSystem: '/If Action Subsystem' */ + } else { + /* Outputs for IfAction SubSystem: '/If Action Subsystem3' incorporates: + * ActionPort: '/Action Port' + */ + /* Merge: '/Merge' incorporates: + * Merge: '/Merge' + * SignalConversion generated from: '/stepIn1' + */ + rtB.Merge_b4 = rtb_y_eo; + + /* End of Outputs for SubSystem: '/If Action Subsystem3' */ + } + + /* End of If: '/If' */ + /* End of Outputs for SubSystem: '/Initial CPOS Min' */ + break; + + case 3: + /* Outputs for IfAction SubSystem: '/Normal Mode' incorporates: + * ActionPort: '/Action Port' + */ + /* If: '/If1' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write1' + * SignalConversion generated from: '/Bus Selector' + */ + if ((Actuator_Ch2_Status_Model.Busy == 0) && + (Actuator_Ch2_Status_Model.Error_Connect == 0)) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem2' incorporates: + * ActionPort: '/Action Port' + */ + for (i = 0; i < 9; i++) { + /* DataStoreWrite: '/Data Store Write' */ + rtDW.MODE_private_c[i] = 0U; + + /* DataStoreWrite: '/Data Store Write1' */ + rtDW.COM_private_k[i] = 1U; + } + + /* Merge: '/Merge' incorporates: + * Constant: '/Constant' + * Sum: '/step inc' + */ + rtB.Merge_b4 = (int8_t)(rtb_y_eo + 1); + + /* MATLAB Function: '/Write' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + /* : if(LOGGER == 2) */ + if (index_start == 2.0) { + /* : fprintf('[LIN 3] Normal Mode\n'); */ + printf("[LIN 3] Normal Mode\n"); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + /* End of Outputs for SubSystem: '/If Action Subsystem2' */ + } else { + /* Outputs for IfAction SubSystem: '/If Action Subsystem3' incorporates: + * ActionPort: '/Action Port' + */ + /* Merge: '/Merge' incorporates: + * SignalConversion generated from: '/stepIn' + */ + rtB.Merge_b4 = rtb_y_eo; + + /* End of Outputs for SubSystem: '/If Action Subsystem3' */ + } + + /* End of If: '/If1' */ + /* End of Outputs for SubSystem: '/Normal Mode' */ + break; + + case 4: + /* Outputs for IfAction SubSystem: '/Move to position Min' incorporates: + * ActionPort: '/Action Port' + */ + /* If: '/If1' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write1' + * SignalConversion generated from: '/Bus Selector' + */ + if ((Actuator_Ch2_Status_Model.Busy == 0) && + (Actuator_Ch2_Status_Model.Error_Connect == 0)) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem2' incorporates: + * ActionPort: '/Action Port' + */ + for (i = 0; i < 9; i++) { + /* DataStoreWrite: '/Data Store Write4' incorporates: + * Constant: '/Constant1' + */ + rtDW.Autos_private_g[i] = 1U; + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/Constant10' + */ + rtDW.Stall_private_f[i] = 1U; + + /* DataStoreWrite: '/Data Store Write3' */ + rtDW.Lnoise_private_g[i] = 0U; + + /* DataStoreWrite: '/Data Store Write5' incorporates: + * Constant: '/Constant2' + */ + rtDW.Speed_private_b[i] = 3U; + + /* DataStoreWrite: '/Data Store Write6' incorporates: + * Constant: '/Constant3' + */ + rtDW.Coils_private_l[i] = 3U; + + /* DataStoreWrite: '/Data Store Write' */ + rtDW.POS_private_h[i] = 0U; + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * Constant: '/Constant9' + */ + rtDW.COM_private_k[i] = 3U; + } + + /* Merge: '/Merge' incorporates: + * Constant: '/Constant' + * Sum: '/step inc' + */ + rtB.Merge_b4 = (int8_t)(rtb_y_eo + 1); + + /* MATLAB Function: '/Write' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + /* : if(LOGGER == 2) */ + if (index_start == 2.0) { + /* : fprintf('[LIN 3] Move to position Min\n'); */ + printf("[LIN 3] Move to position Min\n"); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + /* End of Outputs for SubSystem: '/If Action Subsystem2' */ + } else { + /* Outputs for IfAction SubSystem: '/If Action Subsystem3' incorporates: + * ActionPort: '/Action Port' + */ + /* Merge: '/Merge' incorporates: + * SignalConversion generated from: '/stepIn' + */ + rtB.Merge_b4 = rtb_y_eo; + + /* End of Outputs for SubSystem: '/If Action Subsystem3' */ + } + + /* End of If: '/If1' */ + /* End of Outputs for SubSystem: '/Move to position Min' */ + break; + + case 5: + /* Outputs for IfAction SubSystem: '/Check Stall Min' incorporates: + * ActionPort: '/Action Port' + */ + /* Logic: '/Logical Operator3' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read' + * Logic: '/Logical Operator1' + * Logic: '/Logical Operator2' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator1' + */ + for (i = 0; i < 8; i++) { + rtb_Compare_le[i] = ((Actuator_Ch2_Status_Model.in_Act_Stall_Slave[i] == 1) + || (Actuator_Ch2_Status_Model.in_CPOS_ALL[i] == 0) || + (rtDW.ErrorCalibration_private_b[i] == 0)); + } + + /* End of Logic: '/Logical Operator3' */ + + /* Logic: '/Logical Operator' incorporates: + * Logic: '/Logical Operator3' + */ + rtb_err = rtb_Compare_le[0]; + for (i = 0; i < 7; i++) { + rtb_err = (rtb_err && rtb_Compare_le[i + 1]); + } + + /* If: '/If2' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write1' + * DataTypeConversion: '/Data Type Conversion' + * DataTypeConversion: '/Data Type Conversion1' + * Logic: '/Logical Operator' + * SignalConversion generated from: '/Bus Selector' + */ + if ((Actuator_Ch2_Status_Model.Busy == 0) && + (Actuator_Ch2_Status_Model.Error_Connect == 0) && rtb_err) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem2' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write1' */ + for (i = 0; i < 9; i++) { + /* Switch: '/Switch' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + if (rtDW.ErrorCalibration_private_b[i] != 0) { + rtDW.MinPositionCh2_private[i] = + Actuator_Ch2_Status_Model.in_CPOS_ALL[i]; + } + + /* End of Switch: '/Switch' */ + } + + /* End of DataStoreWrite: '/Data Store Write1' */ + + /* Merge: '/Merge' incorporates: + * Constant: '/Constant' + * Sum: '/step inc' + */ + rtB.Merge_b4 = (int8_t)(rtb_y_eo + 1); + + /* MATLAB Function: '/Write' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + /* : if(LOGGER == 2) */ + if (index_start == 2.0) { + /* : fprintf('[LIN 3] Check Stall Min\n'); */ + printf("[LIN 3] Check Stall Min\n"); + fflush(stdout); + + /* : for i = 1:numel(data) */ + for (i = 0; i < 9; i++) { + /* : fprintf('[LIN 3] MIN = %d ', int16(data(i))); */ + rtb_out_h0 = Actuator_Ch2_Status_Model.in_CPOS_ALL[i]; + if (rtb_out_h0 > 32767) { + rtb_out_h0 = 32767U; + } + + printf("[LIN 3] MIN = %d ", (int16_t)rtb_out_h0); + fflush(stdout); + } + + /* : fprintf('\n'); */ + printf("\n"); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + /* End of Outputs for SubSystem: '/If Action Subsystem2' */ + } else { + /* Outputs for IfAction SubSystem: '/If Action Subsystem3' incorporates: + * ActionPort: '/Action Port' + */ + /* Merge: '/Merge' incorporates: + * SignalConversion generated from: '/stepIn' + */ + rtB.Merge_b4 = rtb_y_eo; + + /* End of Outputs for SubSystem: '/If Action Subsystem3' */ + } + + /* End of If: '/If2' */ + /* End of Outputs for SubSystem: '/Check Stall Min' */ + break; + + case 6: + /* Outputs for IfAction SubSystem: '/Initial CPOS Max' incorporates: + * ActionPort: '/Action Port' + */ + /* If: '/If1' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write1' + * SignalConversion generated from: '/Bus Selector' + */ + if ((Actuator_Ch2_Status_Model.Busy == 0) && + (Actuator_Ch2_Status_Model.Error_Connect == 0)) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem2' incorporates: + * ActionPort: '/Action Port' + */ + for (i = 0; i < 9; i++) { + /* DataStoreWrite: '/Data Store Write1' */ + rtDW.COM_private_k[i] = 2U; + + /* DataStoreWrite: '/Data Store Write' */ + rtDW.POS_private_h[i] = 0U; + } + + /* Merge: '/Merge' incorporates: + * Constant: '/Constant' + * Sum: '/step inc' + */ + rtB.Merge_b4 = (int8_t)(rtb_y_eo + 1); + + /* MATLAB Function: '/Write' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + /* : if(LOGGER == 2) */ + if (index_start == 2.0) { + /* : fprintf('[LIN 3] Initial CPOS Max\n'); */ + printf("[LIN 3] Initial CPOS Max\n"); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + /* End of Outputs for SubSystem: '/If Action Subsystem2' */ + } else { + /* Outputs for IfAction SubSystem: '/If Action Subsystem3' incorporates: + * ActionPort: '/Action Port' + */ + /* Merge: '/Merge' incorporates: + * SignalConversion generated from: '/stepIn' + */ + rtB.Merge_b4 = rtb_y_eo; + + /* End of Outputs for SubSystem: '/If Action Subsystem3' */ + } + + /* End of If: '/If1' */ + /* End of Outputs for SubSystem: '/Initial CPOS Max' */ + break; + + case 7: + /* Outputs for IfAction SubSystem: '/Move to position Max' incorporates: + * ActionPort: '/Action Port' + */ + /* If: '/If1' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write1' + * SignalConversion generated from: '/Bus Selector' + */ + if ((Actuator_Ch2_Status_Model.Busy == 0) && + (Actuator_Ch2_Status_Model.Error_Connect == 0)) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem2' incorporates: + * ActionPort: '/Action Port' + */ + for (i = 0; i < 9; i++) { + /* DataStoreWrite: '/Data Store Write4' incorporates: + * Constant: '/Constant1' + */ + rtDW.Autos_private_g[i] = 1U; + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/Constant10' + */ + rtDW.Stall_private_f[i] = 1U; + + /* DataStoreWrite: '/Data Store Write3' */ + rtDW.Lnoise_private_g[i] = 0U; + + /* DataStoreWrite: '/Data Store Write5' incorporates: + * Constant: '/Constant2' + */ + rtDW.Speed_private_b[i] = 3U; + + /* DataStoreWrite: '/Data Store Write6' incorporates: + * Constant: '/Constant3' + */ + rtDW.Coils_private_l[i] = 3U; + + /* DataStoreWrite: '/Data Store Write' */ + rtDW.POS_private_h[i] = 6000U; + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * Constant: '/Constant9' + */ + rtDW.COM_private_k[i] = 3U; + } + + /* Merge: '/Merge' incorporates: + * Constant: '/Constant' + * Sum: '/step inc' + */ + rtB.Merge_b4 = (int8_t)(rtb_y_eo + 1); + + /* MATLAB Function: '/Write' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + /* : if(LOGGER == 2) */ + if (index_start == 2.0) { + /* : fprintf('[LIN 3] Move to position Max\n'); */ + printf("[LIN 3] Move to position Max\n"); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + /* End of Outputs for SubSystem: '/If Action Subsystem2' */ + } else { + /* Outputs for IfAction SubSystem: '/If Action Subsystem3' incorporates: + * ActionPort: '/Action Port' + */ + /* Merge: '/Merge' incorporates: + * SignalConversion generated from: '/stepIn' + */ + rtB.Merge_b4 = rtb_y_eo; + + /* End of Outputs for SubSystem: '/If Action Subsystem3' */ + } + + /* End of If: '/If1' */ + /* End of Outputs for SubSystem: '/Move to position Max' */ + break; + + case 8: + /* Outputs for IfAction SubSystem: '/Check Stall Max' incorporates: + * ActionPort: '/Action Port' + */ + /* Logic: '/Logical Operator3' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read' + * Logic: '/Logical Operator' + * Logic: '/Logical Operator2' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator1' + */ + for (i = 0; i < 8; i++) { + rtb_Compare_le[i] = ((Actuator_Ch2_Status_Model.in_Act_Stall_Slave[i] == 1) + || (Actuator_Ch2_Status_Model.in_CPOS_ALL[i] == 6000) + || (rtDW.ErrorCalibration_private_b[i] == 0)); + } + + /* End of Logic: '/Logical Operator3' */ + + /* Logic: '/Logical Operator1' incorporates: + * Logic: '/Logical Operator3' + */ + rtb_err = rtb_Compare_le[0]; + for (i = 0; i < 7; i++) { + rtb_err = (rtb_err && rtb_Compare_le[i + 1]); + } + + /* If: '/If2' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write1' + * DataTypeConversion: '/Data Type Conversion' + * DataTypeConversion: '/Data Type Conversion1' + * Logic: '/Logical Operator1' + * SignalConversion generated from: '/Bus Selector' + */ + if ((Actuator_Ch2_Status_Model.Busy == 0) && + (Actuator_Ch2_Status_Model.Error_Connect == 0) && rtb_err) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem2' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write1' */ + for (i = 0; i < 9; i++) { + /* Switch: '/Switch' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + if (rtDW.ErrorCalibration_private_b[i] != 0) { + rtDW.MaxPositionCh2_private[i] = + Actuator_Ch2_Status_Model.in_CPOS_ALL[i]; + } else { + rtDW.MaxPositionCh2_private[i] = 0U; + } + + /* End of Switch: '/Switch' */ + } + + /* End of DataStoreWrite: '/Data Store Write1' */ + + /* Merge: '/Merge' incorporates: + * Constant: '/Constant' + * Sum: '/step inc' + */ + rtB.Merge_b4 = (int8_t)(rtb_y_eo + 1); + + /* MATLAB Function: '/Write' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + /* : if(LOGGER == 2) */ + if (index_start == 2.0) { + /* : fprintf('[LIN 3] Check Stall MAX\n'); */ + printf("[LIN 3] Check Stall MAX\n"); + fflush(stdout); + + /* : for i = 1:numel(data) */ + for (i = 0; i < 9; i++) { + /* : fprintf('[LIN 3] MAX = %d ', int16(data(i))); */ + rtb_out_h0 = Actuator_Ch2_Status_Model.in_CPOS_ALL[i]; + if (rtb_out_h0 > 32767) { + rtb_out_h0 = 32767U; + } + + printf("[LIN 3] MAX = %d ", (int16_t)rtb_out_h0); + fflush(stdout); + } + + /* : fprintf('\n'); */ + printf("\n"); + fflush(stdout); + } + + /* End of MATLAB Function: '/Write' */ + /* End of Outputs for SubSystem: '/If Action Subsystem2' */ + } else { + /* Outputs for IfAction SubSystem: '/If Action Subsystem3' incorporates: + * ActionPort: '/Action Port' + */ + /* Merge: '/Merge' incorporates: + * SignalConversion generated from: '/stepIn' + */ + rtB.Merge_b4 = rtb_y_eo; + + /* End of Outputs for SubSystem: '/If Action Subsystem3' */ + } + + /* End of If: '/If2' */ + /* End of Outputs for SubSystem: '/Check Stall Max' */ + break; + + case 9: + /* Outputs for IfAction SubSystem: '/Homing' incorporates: + * ActionPort: '/Action Port' + */ + /* Product: '/Divide1' incorporates: + * Constant: '/ACT1' + * DataStoreRead: '/MAX ACT1T ' + */ + for (i = 0; i < 8; i++) { + rtb_Divide1_a4[i] = (double)rtDW.MaxPositionCh2_private[i] / (double) + rtConstP.ACT1_Value_m[i]; + } + + /* End of Product: '/Divide1' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant' + */ + rtb_Divide1_a4[8] = 1.0; + + /* SwitchCase: '/Switch Case' incorporates: + * DataStoreRead: '/Data Store Read4' + */ + switch (rtDW.stepHoming_private_a) { + case 0: + /* Outputs for IfAction SubSystem: '/Switch Case Action Subsystem' incorporates: + * ActionPort: '/Action Port' + */ + for (i = 0; i < 9; i++) { + /* RelationalOperator: '/Compare' */ + rtb_Add_be = rtb_Divide1_a4[i]; + + /* Logic: '/Logical Operator' incorporates: + * Constant: '/Constant' + * Constant: '/Constant' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + */ + Enable_Comp_PID = ((rtb_Add_be >= 0.6) && (rtb_Add_be <= 1.5)); + rtb_LogicalOperator3_nq[i] = Enable_Comp_PID; + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write' + * Logic: '/Logical Operator' + * Logic: '/Logical Operator1' + */ + rtDW.ErrorCalibration_private_b[i] = (uint8_t)((!Enable_Comp_PID) && + (rtDW.ErrorCalibration_private_b[i] != 0)); + } + + /* MATLAB Function: '/MAX POSITION' incorporates: + * DataStoreRead: '/Data Store Read5' + * DataStoreRead: '/MIN ACT1T 1' + * Logic: '/Logical Operator2' + */ + /* : if(LOGGER>0) */ + if (index_start > 0.0) { + /* : fprintf("[LIN 3] Homing 0\n"); */ + printf("[LIN 3] Homing 0\n"); + fflush(stdout); + + /* : for i = 1:numel(MAX) */ + for (i = 0; i < 6; i++) { + /* : fprintf('[LIN 3] ACT%d MAX = %d KOEF = %f Callibration = %d \n', int16(i), int16(MAX(i)), KOEF(i), int16(ERRORS(i))); */ + rtb_out_h0 = rtDW.MaxPositionCh2_private[i]; + if (rtb_out_h0 > 32767) { + rtb_out_h0 = 32767U; + } + + printf("[LIN 3] ACT%d MAX = %d KOEF = %f Callibration = %d \n", + (int16_t)(i + 1), (int16_t)rtb_out_h0, rtb_Divide1_a4[i], + (int16_t)!rtb_LogicalOperator3_nq[i]); + fflush(stdout); + } + } + + /* End of MATLAB Function: '/MAX POSITION' */ + + /* Logic: '/Logical Operator1' */ + rtb_err = rtb_LogicalOperator3_nq[0]; + for (i = 0; i < 8; i++) { + rtb_err = (rtb_err && rtb_LogicalOperator3_nq[i + 1]); + } + + /* Switch: '/Switch' incorporates: + * Logic: '/Logical Operator1' + */ + if (rtb_err) { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant1' + */ + rtB.Merge_h3 = 4; + } else { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant' + */ + rtB.Merge_h3 = 1; + } + + /* End of Switch: '/Switch' */ + /* End of Outputs for SubSystem: '/Switch Case Action Subsystem' */ + break; + + case 1: + /* Outputs for IfAction SubSystem: '/Switch Case Action Subsystem1' incorporates: + * ActionPort: '/Action Port' + */ + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + */ + for (i = 0; i < 9; i++) { + rtb_LogicalOperator3_nq[i] = (rtb_Divide1_a4[i] > 1.5); + } + + /* End of RelationalOperator: '/Compare' */ + + /* Logic: '/Logical Operator' */ + rtb_err = rtb_LogicalOperator3_nq[0]; + for (i = 0; i < 8; i++) { + rtb_err = (rtb_err || rtb_LogicalOperator3_nq[i + 1]); + } + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * DataStoreWrite: '/Data Store Write1' + * Logic: '/Logical Operator' + */ + rtDW.CCU_ActuatorErrF_Stat_private = rtb_err; + for (i = 0; i < 9; i++) { + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * DataStoreWrite: '/Data Store Write2' + */ + Enable_Comp_PID = rtb_LogicalOperator3_nq[i]; + rtDW.COM_private_k[i] = Enable_Comp_PID; + + /* DataTypeConversion: '/Data Type Conversion2' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write3' + * Logic: '/Logical Operator1' + */ + rtDW.ErrorActuator_a[i] = (uint8_t)(Enable_Comp_PID || + (rtDW.ErrorActuator_a[i] != 0)); + + /* DataStoreWrite: '/Data Store Write' */ + rtDW.MODE_private_c[i] = 2U; + } + + /* MATLAB Function: '/Write ERROR' incorporates: + * DataStoreRead: '/Data Store Read6' + */ + /* : if(LOGGER>=0) */ + if (index_start >= 0.0) { + /* : for i = 1:numel(ErrCallibration) */ + for (i = 0; i < 9; i++) { + /* : if ErrCallibration(i) == 1 */ + if (rtb_LogicalOperator3_nq[i]) { + /* : fprintf('[LIN 3] Failure with actuator #%d\n', int16(i)); */ + printf("[LIN 3] Failure with actuator #%d\n", (int16_t)(i + 1)); + fflush(stdout); + } + } + } + + /* End of MATLAB Function: '/Write ERROR' */ + for (i = 0; i < 9; i++) { + /* Logic: '/Logical Operator1' */ + Enable_Comp_PID = rtb_LogicalOperator3_nq[i]; + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write' + * Logic: '/Logical Operator' + * Logic: '/Logical Operator1' + */ + rtDW.ErrorCalibration_private_b[i] = (uint8_t)((!Enable_Comp_PID) && + (rtDW.ErrorCalibration_private_b[i] != 0)); + + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.dtc_state_error_model[i + 54] = Enable_Comp_PID; + } + + /* DataStoreWrite: '/Data Store Write' incorporates: + * Constant: '/Constant' + */ + rtDW.stepSig_private_g = 1; + + /* MATLAB Function: '/MAX POSITION' incorporates: + * DataStoreRead: '/Data Store Read5' + * DataStoreRead: '/MIN ACT1T 1' + * DataStoreWrite: '/Data Store Write' + */ + /* : if(LOGGER>0) */ + if (index_start > 0.0) { + /* : fprintf("[LIN 3] Homing 1. Start Callibration \n"); */ + printf("[LIN 3] Homing 1. Start Callibration \n"); + fflush(stdout); + + /* : for i = 1:numel(MAX) */ + for (i = 0; i < 6; i++) { + /* : if(ERRORS(i)==1) */ + if (rtDW.ErrorCalibration_private_b[i] == 1) { + /* : fprintf('[LIN 3] ACT%d MAX = %d KOEF = %f Callibration = %d \n', int16(i), int16(MAX(i)), KOEF(i), int16(ERRORS(i))); */ + rtb_out_h0 = rtDW.MaxPositionCh2_private[i]; + if (rtb_out_h0 > 32767) { + rtb_out_h0 = 32767U; + } + + printf("[LIN 3] ACT%d MAX = %d KOEF = %f Callibration = %d \n", + (int16_t)(i + 1), (int16_t)rtb_out_h0, rtb_Divide1_a4[i], + (int16_t)rtDW.ErrorCalibration_private_b[i]); + fflush(stdout); + } + } + } + + /* End of MATLAB Function: '/MAX POSITION' */ + + /* Logic: '/Logical Operator2' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + rtb_err = (rtDW.ErrorCalibration_private_b[0] != 0); + for (i = 0; i < 8; i++) { + rtb_err = (rtb_err || (rtDW.ErrorCalibration_private_b[i + 1] != 0)); + } + + /* Switch: '/Switch' incorporates: + * Logic: '/Logical Operator2' + */ + if (rtb_err) { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant1' + */ + rtB.Merge_h3 = 2; + } else { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant1' + */ + rtB.Merge_h3 = 4; + } + + /* End of Switch: '/Switch' */ + /* End of Outputs for SubSystem: '/Switch Case Action Subsystem1' */ + break; + + case 2: + /* Outputs for IfAction SubSystem: '/Switch Case Action Subsystem2' incorporates: + * ActionPort: '/Action Port' + */ + for (i = 0; i < 9; i++) { + /* RelationalOperator: '/Compare' */ + rtb_Add_be = rtb_Divide1_a4[i]; + + /* Logic: '/Logical Operator3' incorporates: + * Constant: '/Constant' + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read' + * Logic: '/Logical Operator1' + * Logic: '/Logical Operator4' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + */ + Enable_Comp_PID = (((rtb_Add_be < 0.97) || (rtb_Add_be > 1.03)) && + (rtDW.ErrorCalibration_private_b[i] != 0)); + rtb_LogicalOperator3_nq[i] = Enable_Comp_PID; + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * DataStoreWrite: '/Data Store Write1' + */ + rtDW.ErrorCalibration_private_b[i] = Enable_Comp_PID; + } + + /* MATLAB Function: '/MAX POSITION' incorporates: + * DataStoreRead: '/Data Store Read5' + * DataStoreRead: '/MIN ACT1T 1' + */ + /* : if(LOGGER>0) */ + if (index_start > 0.0) { + /* : fprintf("[LIN 3] Homing 3. Callibration \n"); */ + printf("[LIN 3] Homing 3. Callibration \n"); + fflush(stdout); + + /* : for i = 1:numel(MAX) */ + for (i = 0; i < 6; i++) { + /* : if(ERRORS(i)==1) */ + if (rtb_LogicalOperator3_nq[i]) { + /* : fprintf('[LIN 3] ACT%d MAX = %d KOEF = %f Callibration = %d \n', int16(i), int16(MAX(i)), KOEF(i), int16(ERRORS(i))); */ + rtb_out_h0 = rtDW.MaxPositionCh2_private[i]; + if (rtb_out_h0 > 32767) { + rtb_out_h0 = 32767U; + } + + printf("[LIN 3] ACT%d MAX = %d KOEF = %f Callibration = %d \n", + (int16_t)(i + 1), (int16_t)rtb_out_h0, rtb_Divide1_a4[i], 1); + fflush(stdout); + } + } + } + + /* End of MATLAB Function: '/MAX POSITION' */ + + /* Logic: '/Logical Operator2' */ + rtb_err = rtb_LogicalOperator3_nq[0]; + for (i = 0; i < 8; i++) { + rtb_err = (rtb_err || rtb_LogicalOperator3_nq[i + 1]); + } + + /* Switch: '/Switch' incorporates: + * Logic: '/Logical Operator2' + */ + if (rtb_err) { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant3' + */ + rtB.Merge_h3 = 3; + } else { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant1' + */ + rtB.Merge_h3 = 4; + } + + /* End of Switch: '/Switch' */ + /* End of Outputs for SubSystem: '/Switch Case Action Subsystem2' */ + break; + + case 3: + /* Outputs for IfAction SubSystem: '/Switch Case Action Subsystem3' incorporates: + * ActionPort: '/Action Port' + */ + /* MATLAB Function: '/MAX POSITION' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read5' + */ + /* : if(LOGGER>1) */ + if (index_start > 1.0) { + /* : fprintf("[LIN 3] Homing 3. Start Time on step %d\n",int16(step)); */ + rtb_Add_be = rt_roundd(rtDW.ErrorHomming_private_m); + if (rtb_Add_be < 32768.0) { + if (rtb_Add_be >= -32768.0) { + rtb_FLU_tg_correct_aa = (int16_t)rtb_Add_be; + } else { + rtb_FLU_tg_correct_aa = INT16_MIN; + } + } else { + rtb_FLU_tg_correct_aa = INT16_MAX; + } + + printf("[LIN 3] Homing 3. Start Time on step %d\n", + rtb_FLU_tg_correct_aa); + fflush(stdout); + } + + /* End of MATLAB Function: '/MAX POSITION' */ + + /* If: '/If' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + if (rtDW.ErrorHomming_private_m < 10.0) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem' incorporates: + * ActionPort: '/Action Port' + */ + /* MATLAB Function: '/MATLAB Function' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read1' + */ + MATLABFunction(rtDW.Start_timer, rtDW.t_now, &rtb_dt_nx, + &rtDW.sf_MATLABFunction_g); + + /* MATLAB Function: '/MAX POSITION' incorporates: + * DataStoreRead: '/Data Store Read5' + */ + /* : if(LOGGER>1) */ + if (index_start > 1.0) { + /* : fprintf("[LIN 3] Homing 3. Start TIme dt = %d \n",int32(data)); */ + rtb_Subtract = rtb_dt_nx; + if (rtb_dt_nx > 2147483647U) { + rtb_Subtract = 2147483647U; + } + + printf("[LIN 3] Homing 3. Start TIme dt = %d \n", (int32_t) + rtb_Subtract); + fflush(stdout); + } + + /* End of MATLAB Function: '/MAX POSITION' */ + + /* If: '/If' */ + if (rtb_dt_nx > 3600000U) { + /* Outputs for IfAction SubSystem: '/If Action Subsystem' incorporates: + * ActionPort: '/Action Port' + */ + /* Merge: '/Merge' */ + IfActionSubsystem_h(&rtB.Merge_h3, &rtDW.ErrorHomming_private_m, + &rtDW.Start_timer, &rtDW.stepSig_private_g); + + /* End of Outputs for SubSystem: '/If Action Subsystem' */ + } else { + /* Outputs for IfAction SubSystem: '/If Action Subsystem1' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/Constant3' + */ + rtDW.Start_timer = 1.0; + + /* DataStoreRead: '/Data Store Read2' incorporates: + * Concatenate: '/Vector Concatenate' + */ + rtDW.BUS_ADR_private_a[0] = rtDW.PID_TempRR; + + /* DataStoreRead: '/Data Store Read' incorporates: + * Concatenate: '/Vector Concatenate' + */ + rtDW.BUS_ADR_private_a[1] = rtDW.PID_TempRL; + + /* DataTypeConversion: '/Data Type Conversion2' */ + for (i = 0; i < 6; i++) { + rtb_DataTypeConversion2_ie[i] = (uint8_t)rtb_Gain1_o3[i]; + } + + /* End of DataTypeConversion: '/Data Type Conversion2' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Concatenate: '/Vector Concatenate' + */ + rtDW.BUS_ADR_private_a[2] = rtb_DataTypeConversion2_ie[0]; + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Concatenate: '/Vector Concatenate' + */ + rtDW.BUS_ADR_private_a[3] = rtb_DataTypeConversion2_ie[4]; + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Concatenate: '/Vector Concatenate' + */ + rtDW.BUS_ADR_private_a[4] = rtb_DataTypeConversion2_ie[1]; + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Concatenate: '/Vector Concatenate' + */ + rtDW.BUS_ADR_private_a[5] = rtb_DataTypeConversion2_ie[2]; + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Concatenate: '/Vector Concatenate' + */ + rtDW.BUS_ADR_private_a[6] = rtb_DataTypeConversion2_ie[5]; + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Concatenate: '/Vector Concatenate' + */ + rtDW.BUS_ADR_private_a[7] = rtb_DataTypeConversion2_ie[3]; + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Concatenate: '/Vector Concatenate' + * Constant: '/Constant1' + * SignalConversion generated from: '/Vector Concatenate' + */ + rtDW.BUS_ADR_private_a[8] = 0U; + for (i = 0; i < 9; i++) { + /* Product: '/Product' */ + El_window_heating = rtDW.BUS_ADR_private_a[i]; + + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write' + * Product: '/Divide1' + * Product: '/Product' + */ + rtDW.POS_private_h[i] = (uint16_t)((double)(El_window_heating * + rtDW.MaxPositionCh2_private[i]) / 100.0); + + /* RelationalOperator: '/Relational Operator1' incorporates: + * DataStoreWrite: '/Data Store Write2' + */ + rtb_LogicalOperator3_nq[i] = (rtb_DataTypeConversion_mo[i] == + El_window_heating); + } + + /* Logic: '/Logical Operator' */ + rtb_err = rtb_LogicalOperator3_nq[0]; + for (i = 0; i < 8; i++) { + rtb_err = (rtb_err && rtb_LogicalOperator3_nq[i + 1]); + } + + for (i = 0; i < 9; i++) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant4' + * Constant: '/Constant9' + * DataStoreWrite: '/Data Store Write1' + * Logic: '/Logical Operator' + */ + if (rtb_err) { + rtDW.COM_private_k[i] = 0U; + } else { + rtDW.COM_private_k[i] = 3U; + } + + /* End of Switch: '/Switch' */ + + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Concatenate: '/Vector Concatenate' + * Constant: '/Constant5' + * DataStoreWrite: '/Data Store Write2' + * DataStoreWrite: '/Data Store Write7' + * Product: '/Product' + * RelationalOperator: '/Relational Operator' + */ + rtDW.BUS_ADR_private_a[i] = (uint8_t)((uint32_t) + (rtb_DataTypeConversion_mo[i] != rtDW.BUS_ADR_private_a[i]) * + rtConstP.pooled119[i]); + + /* DataStoreWrite: '/Data Store Write4' incorporates: + * Constant: '/Constant1' + */ + rtDW.Autos_private_g[i] = 1U; + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/Constant10' + */ + rtDW.Stall_private_f[i] = 1U; + + /* DataStoreWrite: '/Data Store Write3' incorporates: + * Constant: '/Constant11' + */ + rtDW.Lnoise_private_g[i] = 0U; + + /* DataStoreWrite: '/Data Store Write5' incorporates: + * Constant: '/Constant2' + */ + rtDW.Speed_private_b[i] = 3U; + + /* DataStoreWrite: '/Data Store Write6' incorporates: + * Constant: '/Constant3' + */ + rtDW.Coils_private_l[i] = 3U; + } + + /* Merge: '/Merge' incorporates: + * Constant: '/Constant1' + * Merge: '/Merge' + * SignalConversion generated from: '/Out1' + */ + rtB.Merge_h3 = 3; + + /* End of Outputs for SubSystem: '/If Action Subsystem1' */ + } + + /* End of If: '/If' */ + /* End of Outputs for SubSystem: '/If Action Subsystem' */ + } else { + /* Outputs for IfAction SubSystem: '/If Action Subsystem1' incorporates: + * ActionPort: '/Action Port' + */ + IfActionSubsystem1_h(&rtB.Merge_h3, &rtDW.CCU_ActuatorErrF_Stat_private, + rtDW.COM_private_k, rtDW.ErrorActuator_a, + rtDW.ErrorCalibration_private_b, &index_start, + rtDW.MODE_private_c, rtDW.dtc_state_error_model); + + /* End of Outputs for SubSystem: '/If Action Subsystem1' */ + } + + /* End of If: '/If' */ + /* End of Outputs for SubSystem: '/Switch Case Action Subsystem3' */ + break; + + case 4: + /* Outputs for IfAction SubSystem: '/Switch Case Action Subsystem4' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreRead: '/Data Store Read2' incorporates: + * Concatenate: '/Vector Concatenate' + */ + rtDW.BUS_ADR_private_a[0] = rtDW.PID_TempRR; + + /* DataStoreRead: '/Data Store Read' incorporates: + * Concatenate: '/Vector Concatenate' + */ + rtDW.BUS_ADR_private_a[1] = rtDW.PID_TempRL; + + /* DataTypeConversion: '/Data Type Conversion2' */ + for (i = 0; i < 6; i++) { + rtb_DataTypeConversion2_ie[i] = (uint8_t)rtb_Gain1_o3[i]; + } + + /* End of DataTypeConversion: '/Data Type Conversion2' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Concatenate: '/Vector Concatenate' + */ + rtDW.BUS_ADR_private_a[2] = rtb_DataTypeConversion2_ie[0]; + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Concatenate: '/Vector Concatenate' + */ + rtDW.BUS_ADR_private_a[3] = rtb_DataTypeConversion2_ie[4]; + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Concatenate: '/Vector Concatenate' + */ + rtDW.BUS_ADR_private_a[4] = rtb_DataTypeConversion2_ie[1]; + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Concatenate: '/Vector Concatenate' + */ + rtDW.BUS_ADR_private_a[5] = rtb_DataTypeConversion2_ie[2]; + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Concatenate: '/Vector Concatenate' + */ + rtDW.BUS_ADR_private_a[6] = rtb_DataTypeConversion2_ie[5]; + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Concatenate: '/Vector Concatenate' + */ + rtDW.BUS_ADR_private_a[7] = rtb_DataTypeConversion2_ie[3]; + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Concatenate: '/Vector Concatenate' + * Constant: '/Constant1' + * SignalConversion generated from: '/Vector Concatenate' + */ + rtDW.BUS_ADR_private_a[8] = 0U; + for (i = 0; i < 9; i++) { + /* Product: '/Product' */ + El_window_heating = rtDW.BUS_ADR_private_a[i]; + + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write' + * Product: '/Divide1' + * Product: '/Product' + */ + rtDW.POS_private_h[i] = (uint16_t)((double)(El_window_heating * + rtDW.MaxPositionCh2_private[i]) / 100.0); + + /* RelationalOperator: '/Relational Operator1' incorporates: + * DataStoreWrite: '/Data Store Write2' + */ + rtb_LogicalOperator3_nq[i] = (rtb_DataTypeConversion_mo[i] == + El_window_heating); + } + + /* Logic: '/Logical Operator' */ + rtb_err = rtb_LogicalOperator3_nq[0]; + for (i = 0; i < 8; i++) { + rtb_err = (rtb_err && rtb_LogicalOperator3_nq[i + 1]); + } + + for (i = 0; i < 9; i++) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant4' + * Constant: '/Constant9' + * DataStoreWrite: '/Data Store Write1' + * Logic: '/Logical Operator' + */ + if (rtb_err) { + rtDW.COM_private_k[i] = 0U; + } else { + rtDW.COM_private_k[i] = 3U; + } + + /* End of Switch: '/Switch' */ + + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Concatenate: '/Vector Concatenate' + * Constant: '/Constant5' + * DataStoreWrite: '/Data Store Write2' + * DataStoreWrite: '/Data Store Write7' + * Product: '/Product' + * RelationalOperator: '/Relational Operator' + */ + rtDW.BUS_ADR_private_a[i] = (uint8_t)((uint32_t) + (rtb_DataTypeConversion_mo[i] != rtDW.BUS_ADR_private_a[i]) * + rtConstP.pooled119[i]); + + /* DataStoreWrite: '/Data Store Write4' incorporates: + * Constant: '/Constant1' + */ + rtDW.Autos_private_g[i] = 1U; + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/Constant10' + */ + rtDW.Stall_private_f[i] = 1U; + + /* DataStoreWrite: '/Data Store Write3' incorporates: + * Constant: '/Constant11' + */ + rtDW.Lnoise_private_g[i] = 0U; + + /* DataStoreWrite: '/Data Store Write5' incorporates: + * Constant: '/Constant2' + */ + rtDW.Speed_private_b[i] = 3U; + + /* DataStoreWrite: '/Data Store Write6' incorporates: + * Constant: '/Constant3' + */ + rtDW.Coils_private_l[i] = 3U; + } + + /* Merge: '/Merge' incorporates: + * Constant: '/Constant1' + * SignalConversion generated from: '/step' + */ + rtB.Merge_h3 = 4; + + /* MATLAB Function: '/MAX POSITION' incorporates: + * DataStoreRead: '/Data Store Read5' + */ + /* : if(LOGGER>0) */ + if (index_start > 0.0) { + /* : fprintf("[LIN 3] Homing. Callibration successful \n"); */ + printf("[LIN 3] Homing. Callibration successful \n"); + fflush(stdout); + } + + /* End of MATLAB Function: '/MAX POSITION' */ + /* End of Outputs for SubSystem: '/Switch Case Action Subsystem4' */ + break; + } + + /* End of SwitchCase: '/Switch Case' */ + + /* DataStoreWrite: '/Data Store Write2' */ + rtDW.stepHoming_private_a = rtB.Merge_h3; + + /* Merge: '/Merge' incorporates: + * DataStoreRead: '/Data Store Read7' + */ + rtB.Merge_b4 = rtDW.stepSig_private_g; + + /* End of Outputs for SubSystem: '/Homing' */ + break; + } + + /* End of SwitchCase: '/Switch Case' */ + + /* Outport: '/CCU_Errors_model' incorporates: + * DataStoreRead: '/Data Store Read10' + */ + rtY.CCU_Errors_model = CCU_Errors_Model; + + /* Outport: '/Actuator_Ch0_Command_Model_out' incorporates: + * DataStoreRead: '/Data Store Read66' + */ + rtY.Actuator_Ch0_Command_Model_out = Actuator_Ch0_Command_Model; + + /* Outport: '/Actuator_Ch1_Command_Mode_out' incorporates: + * DataStoreRead: '/Data Store Read67' + */ + rtY.Actuator_Ch1_Command_Mode_out = Actuator_Ch1_Command_Model; + + /* DataStoreWrite: '/Finish write stepSig' */ + rtDW.stepSig_private_g = rtB.Merge_b4; + + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read3' + * DataStoreRead: '/Data Store Read4' + * DataStoreRead: '/Data Store Read5' + * DataStoreRead: '/Data Store Read6' + * DataStoreRead: '/Data Store Read7' + * DataStoreRead: '/Data Store Read8' + * DataStoreWrite: '/Data Store Write' + */ + for (i = 0; i < 9; i++) { + Actuator_Ch2_Command_Model.POS[i] = rtDW.POS_private_h[i]; + Actuator_Ch2_Command_Model.BUS_ADR[i] = rtDW.BUS_ADR_private_a[i]; + Actuator_Ch2_Command_Model.MODE[i] = rtDW.MODE_private_c[i]; + Actuator_Ch2_Command_Model.COM[i] = rtDW.COM_private_k[i]; + Actuator_Ch2_Command_Model.Stall_SET[i] = rtDW.Stall_private_f[i]; + Actuator_Ch2_Command_Model.Lnoise_SET[i] = rtDW.Lnoise_private_g[i]; + Actuator_Ch2_Command_Model.Autos_SET[i] = rtDW.Autos_private_g[i]; + Actuator_Ch2_Command_Model.Speed_SET[i] = rtDW.Speed_private_b[i]; + Actuator_Ch2_Command_Model.Coils_Stop_SET[i] = rtDW.Coils_private_l[i]; + } + + /* End of BusCreator: '/Bus Creator' */ + + /* Outport: '/Actuator_Ch2_Command_Model_out' incorporates: + * DataStoreRead: '/Data Store Read68' + */ + rtY.Actuator_Ch2_Command_Model_out = Actuator_Ch2_Command_Model; + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read2' + */ + for (i = 0; i < 8; i++) { + rtb_Compare_le[i] = (rtDW.ErrorCalibration_private_b[i] == 0); + } + + /* End of RelationalOperator: '/Compare' */ + + /* Logic: '/Logical Operator' */ + rtb_err = rtb_Compare_le[0]; + for (i = 0; i < 7; i++) { + rtb_err = (rtb_err || rtb_Compare_le[i + 1]); + } + + /* Switch: '/Switch1' incorporates: + * Constant: '/Constant' + * Constant: '/Constant3' + * DataStoreRead: '/Data Store Read2' + * Logic: '/Logical Operator' + * Product: '/Product' + */ + for (i = 0; i < 8; i++) { + if (rtb_err) { + rtb_DataTypeConversion_mo[i] = (uint8_t)((uint32_t) + rtDW.ErrorCalibration_private_b[i] * rtConstP.Constant3_Value_d[i]); + } else { + rtb_DataTypeConversion_mo[i] = 0U; + } + } + + /* End of Switch: '/Switch1' */ + + /* SignalConversion generated from: '/Vector Concatenate' incorporates: + * Constant: '/Constant1' + */ + rtb_DataTypeConversion_mo[8] = 0U; + for (i = 0; i < 9; i++) { + /* DataStoreWrite: '/Data Store Write7' incorporates: + * Concatenate: '/Vector Concatenate' + */ + rtDW.BUS_ADR_private_a[i] = rtb_DataTypeConversion_mo[i]; + + /* DataStoreWrite: '/Data Store Write' */ + rtDW.COM_private_k[i] = 0U; + } + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write1' + * Logic: '/OR2' + */ + rtDW.CCU_AirQualSenErr_Stat = (uint8_t) + ((rtDW.LIN4_ERROR_model.in_error_connect[0] != 0) || + (rtDW.LIN4_ERROR_model.Error_Connect != 0) || + (rtDW.LIN4_AirQS_Stat_Model.AirQS_LinRespErr_Stat != 0) || + (rtDW.LIN4_AirQS_Stat_Model.AirQS_Err_Stat != 0)); + + /* DataStoreWrite: '/Data Store Write11' incorporates: + * DataStoreRead: '/Data Store Read2' + */ + rtDW.Aroma_CartridgeFlavor = + rtDW.LIN4_Aroma_Stat_Model.Aroma_CartridgeFlavor_Stat; + + /* DataStoreWrite: '/Data Store Write12' incorporates: + * DataStoreRead: '/Data Store Read2' + */ + rtDW.Aroma_CartridgeCapacity = + rtDW.LIN4_Aroma_Stat_Model.Aroma_CartridgeCapacity_Stat; + + /* DataTypeConversion: '/Data Type Conversion2' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read3' + * DataStoreWrite: '/Data Store Write13' + * Logic: '/OR' + */ + rtDW.CCU_IonizationErr_Stat = (uint8_t) + ((rtDW.LIN4_ERROR_model.in_error_connect[2] != 0) || + (rtDW.LIN4_ERROR_model.Error_Connect != 0) || + (rtDW.LIN4_Ionizer_Stat_Model.Ionizer_LinRespErr_Stat != 0) || + (rtDW.LIN4_Ionizer_Stat_Model.Ionizer_Err_Stat != 0)); + + /* DataStoreWrite: '/Data Store Write14' incorporates: + * DataStoreRead: '/Data Store Read' + */ + rtDW.dtc_state_error_model[41] = rtDW.LIN4_ERROR_model.Error_Connect; + + /* DataStoreWrite: '/Data Store Write16' incorporates: + * DataStoreRead: '/Data Store Read' + */ + rtDW.dtc_state_error_model[44] = rtDW.LIN4_ERROR_model.Error_Connect; + + /* DataStoreWrite: '/Data Store Write17' incorporates: + * DataStoreWrite: '/Data Store Write13' + */ + rtDW.dtc_state_error_model[42] = rtDW.CCU_IonizationErr_Stat; + + /* DataStoreWrite: '/Data Store Write18' incorporates: + * DataStoreWrite: '/Data Store Write13' + */ + rtDW.dtc_state_error_model[43] = rtDW.CCU_IonizationErr_Stat; + + /* DataStoreWrite: '/Data Store Write19' incorporates: + * DataStoreRead: '/Data Store Read' + */ + rtDW.dtc_state_error_model[49] = rtDW.LIN4_ERROR_model.Error_Connect; + + /* DataStoreWrite: '/Data Store Write20' incorporates: + * DataStoreWrite: '/Data Store Write1' + */ + rtDW.dtc_state_error_model[47] = rtDW.CCU_AirQualSenErr_Stat; + + /* DataStoreWrite: '/Data Store Write21' incorporates: + * DataStoreWrite: '/Data Store Write1' + */ + rtDW.dtc_state_error_model[48] = rtDW.CCU_AirQualSenErr_Stat; + + /* DataStoreWrite: '/Data Store Write22' incorporates: + * DataStoreWrite: '/Data Store Write1' + */ + rtDW.dtc_state_error_model[117] = rtDW.CCU_AirQualSenErr_Stat; + + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read2' + * DataStoreWrite: '/Data Store Write7' + * Logic: '/OR1' + */ + rtDW.CCU_AromaErr_Stat = (uint8_t)((rtDW.LIN4_ERROR_model.in_error_connect[1] + != 0) || (rtDW.LIN4_ERROR_model.Error_Connect != 0) || + (rtDW.LIN4_Aroma_Stat_Model.Aroma_LinRespErr_Stat != 0) || + (rtDW.LIN4_Aroma_Stat_Model.Aroma_Err_Stat != 0)); + + /* DataStoreWrite: '/Data Store Write23' incorporates: + * DataStoreWrite: '/Data Store Write7' + */ + rtDW.dtc_state_error_model[119] = rtDW.CCU_AromaErr_Stat; + + /* DataStoreWrite: '/Data Store Write24' incorporates: + * DataStoreWrite: '/Data Store Write13' + */ + rtDW.dtc_state_error_model[118] = rtDW.CCU_IonizationErr_Stat; + + /* DataStoreWrite: '/Data Store Write3' incorporates: + * DataStoreWrite: '/Data Store Write7' + */ + rtDW.dtc_state_error_model[39] = rtDW.CCU_AromaErr_Stat; + + /* DataStoreWrite: '/Data Store Write4' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + rtDW.AirQS_COLvl = rtDW.LIN4_AirQS_Stat_Model.AirQS_COLvl_Stat; + + /* DataStoreWrite: '/Data Store Write5' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + rtDW.AirQS_NOxLvl = rtDW.LIN4_AirQS_Stat_Model.AirQS_NOxLvl_Stat; + + /* DataStoreWrite: '/Data Store Write6' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + rtDW.AirQS_NH3Lvl = rtDW.LIN4_AirQS_Stat_Model.AirQS_NH3Lvl_Stat; + + /* DataStoreWrite: '/Data Store Write8' incorporates: + * DataStoreRead: '/Data Store Read2' + */ + rtDW.Aroma_CartridgeSw = rtDW.LIN4_Aroma_Stat_Model.Aroma_CartridgeSw_Stat; + + /* DataStoreWrite: '/Data Store Write9' incorporates: + * DataStoreWrite: '/Data Store Write7' + */ + rtDW.dtc_state_error_model[40] = rtDW.CCU_AromaErr_Stat; + + /* Outputs for Enabled SubSystem: '/CHANEL4' incorporates: + * EnablePort: '/Enable' + */ + /* DataStoreRead: '/Data Store Read1' incorporates: + * RelationalOperator: '/FixPt Relational Operator' + * RelationalOperator: '/FixPt Relational Operator' + * RelationalOperator: '/FixPt Relational Operator' + * RelationalOperator: '/FixPt Relational Operator' + * RelationalOperator: '/FixPt Relational Operator' + * RelationalOperator: '/FixPt Relational Operator' + * RelationalOperator: '/FixPt Relational Operator' + * RelationalOperator: '/FixPt Relational Operator' + * UnitDelay: '/Delay Input1' + * UnitDelay: '/Delay Input1' + * UnitDelay: '/Delay Input1' + * UnitDelay: '/Delay Input1' + * UnitDelay: '/Delay Input1' + * UnitDelay: '/Delay Input1' + * UnitDelay: '/Delay Input1' + * UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + if (rtDW.BCM_T15_Stat > 0) { + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * DataStoreRead: '/Data Store Read7' + * DataStoreWrite: '/Data Store Write8' + * Logic: '/OR' + * Logic: '/OR2' + * Logic: '/OR4' + * Logic: '/OR6' + */ + rtDW.CCU_DeflectorSwErrF_Stat = (uint8_t) + ((rtDW.LIN5_SENSON_ADR_Stat_model.in_error_connect[0] != 0) || + (rtDW.LIN5_SENSON_ADR_Stat_model.in_error_connect[1] != 0) || + (rtDW.LIN5_SENSON_ADR_Stat_model.in_error_connect[2] != 0) || + (rtDW.LIN5_SENSON_ADR_Stat_model.in_error_connect[3] != 0) || + ((rtDW.LIN5_SENSON_ADR_Stat_model.LinRespErr_Stat[0] != 0) || + (rtDW.LIN5_SENSON_ADR_Stat_model.LinRespErr_Stat[1] != 0) || + (rtDW.LIN5_SENSON_ADR_Stat_model.LinRespErr_Stat[2] != 0) || + (rtDW.LIN5_SENSON_ADR_Stat_model.LinRespErr_Stat[3] != 0)) || + ((rtDW.LIN5_SENSON_ADR_Stat_model.Err_Stat[0] != 0) || + (rtDW.LIN5_SENSON_ADR_Stat_model.Err_Stat[1] != 0) || + (rtDW.LIN5_SENSON_ADR_Stat_model.Err_Stat[2] != 0) || + (rtDW.LIN5_SENSON_ADR_Stat_model.Err_Stat[3] != 0)) || + (rtDW.LIN5_SENSON_ADR_Stat_model.Error_Connect != 0)); + + /* DataStoreWrite: '/Data Store Write10' incorporates: + * DataStoreWrite: '/Data Store Write8' + */ + rtDW.dtc_state_error_model[45] = rtDW.CCU_DeflectorSwErrF_Stat; + + /* DataStoreWrite: '/Data Store Write11' incorporates: + * DataStoreRead: '/Data Store Read7' + */ + rtDW.dtc_state_error_model[125] = + rtDW.LIN5_SENSON_ADR_Stat_model.Error_Connect; + + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * DataStoreRead: '/Data Store Read7' + * DataStoreWrite: '/Data Store Write9' + * Logic: '/OR1' + * Logic: '/OR3' + * Logic: '/OR5' + * Logic: '/OR7' + */ + rtDW.CCU_DeflectorSwErrR_Stat = (uint8_t) + ((rtDW.LIN5_SENSON_ADR_Stat_model.in_error_connect[4] != 0) || + (rtDW.LIN5_SENSON_ADR_Stat_model.in_error_connect[5] != 0) || + (rtDW.LIN5_SENSON_ADR_Stat_model.in_error_connect[6] != 0) || + (rtDW.LIN5_SENSON_ADR_Stat_model.in_error_connect[7] != 0) || + ((rtDW.LIN5_SENSON_ADR_Stat_model.LinRespErr_Stat[4] != 0) || + (rtDW.LIN5_SENSON_ADR_Stat_model.LinRespErr_Stat[5] != 0) || + (rtDW.LIN5_SENSON_ADR_Stat_model.LinRespErr_Stat[6] != 0) || + (rtDW.LIN5_SENSON_ADR_Stat_model.LinRespErr_Stat[7] != 0)) || + ((rtDW.LIN5_SENSON_ADR_Stat_model.Err_Stat[4] != 0) || + (rtDW.LIN5_SENSON_ADR_Stat_model.Err_Stat[5] != 0) || + (rtDW.LIN5_SENSON_ADR_Stat_model.Err_Stat[6] != 0) || + (rtDW.LIN5_SENSON_ADR_Stat_model.Err_Stat[7] != 0)) || + (rtDW.LIN5_SENSON_ADR_Stat_model.Error_Connect != 0)); + + /* DataStoreWrite: '/Data Store Write12' incorporates: + * DataStoreWrite: '/Data Store Write9' + */ + rtDW.dtc_state_error_model[46] = rtDW.CCU_DeflectorSwErrR_Stat; + + /* DataStoreWrite: '/Data Store Write23' incorporates: + * DataStoreRead: '/Data Store Read7' + */ + rtDW.dtc_state_error_model[119] = + rtDW.LIN5_SENSON_ADR_Stat_model.Error_Connect; + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read7' + */ + Enable_Comp_PID = (rtDW.LIN5_SENSON_ADR_Stat_model.in_COUNT[0] > 0); + + /* Outputs for Enabled SubSystem: '/Subsystem' incorporates: + * EnablePort: '/Enable' + */ + if ((int32_t)Enable_Comp_PID > (int32_t)rtDW.DelayInput1_DSTATE_e5) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write' + * Sum: '/Add' + */ + if ((int8_t)((int8_t)rtDW.DRS_SFL - 1) >= 0) { + rtDW.DRS_SFL = (uint8_t)((int8_t)rtDW.DRS_SFL - 1); + } else { + rtDW.DRS_SFL = 3U; + } + + /* End of Switch: '/Switch' */ + } + + /* End of Outputs for SubSystem: '/Subsystem' */ + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read7' + * RelationalOperator: '/FixPt Relational Operator' + * UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + rtb_err = (rtDW.LIN5_SENSON_ADR_Stat_model.in_COUNT[1] > 0); + + /* Outputs for Enabled SubSystem: '/Subsystem1' incorporates: + * EnablePort: '/Enable' + */ + if ((int32_t)rtb_err > (int32_t)rtDW.DelayInput1_DSTATE_k) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write' + * Sum: '/Add' + */ + if ((int8_t)((int8_t)rtDW.DRS_SFR - 1) >= 0) { + rtDW.DRS_SFR = (uint8_t)((int8_t)rtDW.DRS_SFR - 1); + } else { + rtDW.DRS_SFR = 3U; + } + + /* End of Switch: '/Switch' */ + } + + /* End of Outputs for SubSystem: '/Subsystem1' */ + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read7' + * RelationalOperator: '/FixPt Relational Operator' + * UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + rtb_LogicalOperator6 = (rtDW.LIN5_SENSON_ADR_Stat_model.in_COUNT[2] > 0); + + /* Outputs for Enabled SubSystem: '/Subsystem2' incorporates: + * EnablePort: '/Enable' + */ + if ((int32_t)rtb_LogicalOperator6 > (int32_t)rtDW.DelayInput1_DSTATE_l) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write' + * Sum: '/Add' + */ + if ((int8_t)((int8_t)rtDW.DRS_CFL - 1) >= 0) { + rtDW.DRS_CFL = (uint8_t)((int8_t)rtDW.DRS_CFL - 1); + } else { + rtDW.DRS_CFL = 3U; + } + + /* End of Switch: '/Switch' */ + } + + /* End of Outputs for SubSystem: '/Subsystem2' */ + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read7' + * RelationalOperator: '/FixPt Relational Operator' + * UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + rtb_LogicalOperator3 = (rtDW.LIN5_SENSON_ADR_Stat_model.in_COUNT[3] > 0); + + /* Outputs for Enabled SubSystem: '/Subsystem3' incorporates: + * EnablePort: '/Enable' + */ + if ((int32_t)rtb_LogicalOperator3 > (int32_t)rtDW.DelayInput1_DSTATE_kb) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write' + * Sum: '/Add' + */ + if ((int8_t)((int8_t)rtDW.DRS_CFR - 1) >= 0) { + rtDW.DRS_CFR = (uint8_t)((int8_t)rtDW.DRS_CFR - 1); + } else { + rtDW.DRS_CFR = 3U; + } + + /* End of Switch: '/Switch' */ + } + + /* End of Outputs for SubSystem: '/Subsystem3' */ + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read7' + * RelationalOperator: '/FixPt Relational Operator' + * UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + rtb_LogicalOperator8 = (rtDW.LIN5_SENSON_ADR_Stat_model.in_COUNT[4] > 0); + + /* Outputs for Enabled SubSystem: '/Subsystem4' incorporates: + * EnablePort: '/Enable' + */ + if ((int32_t)rtb_LogicalOperator8 > (int32_t)rtDW.DelayInput1_DSTATE_kk) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write' + * Sum: '/Add' + */ + if ((int8_t)((int8_t)rtDW.DRS_SRL - 1) >= 0) { + rtDW.DRS_SRL = (uint8_t)((int8_t)rtDW.DRS_SRL - 1); + } else { + rtDW.DRS_SRL = 3U; + } + + /* End of Switch: '/Switch' */ + } + + /* End of Outputs for SubSystem: '/Subsystem4' */ + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read7' + * RelationalOperator: '/FixPt Relational Operator' + * UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + rtb_LogicalOperator3_cz = (rtDW.LIN5_SENSON_ADR_Stat_model.in_COUNT[5] > 0); + + /* Outputs for Enabled SubSystem: '/Subsystem5' incorporates: + * EnablePort: '/Enable' + */ + if ((int32_t)rtb_LogicalOperator3_cz > (int32_t)rtDW.DelayInput1_DSTATE_d1) + { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write' + * Sum: '/Add' + */ + if ((int8_t)((int8_t)rtDW.DRS_SRR - 1) >= 0) { + rtDW.DRS_SRR = (uint8_t)((int8_t)rtDW.DRS_SRR - 1); + } else { + rtDW.DRS_SRR = 3U; + } + + /* End of Switch: '/Switch' */ + } + + /* End of Outputs for SubSystem: '/Subsystem5' */ + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read7' + * RelationalOperator: '/FixPt Relational Operator' + * UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + rtb_LogicalOperator4_fo = (rtDW.LIN5_SENSON_ADR_Stat_model.in_COUNT[6] > 0); + + /* Outputs for Enabled SubSystem: '/Subsystem6' incorporates: + * EnablePort: '/Enable' + */ + if ((int32_t)rtb_LogicalOperator4_fo > (int32_t)rtDW.DelayInput1_DSTATE_b) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write' + * Sum: '/Add' + */ + if ((int8_t)((int8_t)rtDW.DRS_CRL - 1) >= 0) { + rtDW.DRS_CRL = (uint8_t)((int8_t)rtDW.DRS_CRL - 1); + } else { + rtDW.DRS_CRL = 3U; + } + + /* End of Switch: '/Switch' */ + } + + /* End of Outputs for SubSystem: '/Subsystem6' */ + + /* RelationalOperator: '/Compare' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read7' + * RelationalOperator: '/FixPt Relational Operator' + * UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + rtb_LogicalOperator6_m = (rtDW.LIN5_SENSON_ADR_Stat_model.in_COUNT[7] > 0); + + /* Outputs for Enabled SubSystem: '/Subsystem7' incorporates: + * EnablePort: '/Enable' + */ + if ((int32_t)rtb_LogicalOperator6_m > (int32_t)rtDW.DelayInput1_DSTATE_i) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write' + * Sum: '/Add' + */ + if ((int8_t)((int8_t)rtDW.DRS_CRR - 1) >= 0) { + rtDW.DRS_CRR = (uint8_t)((int8_t)rtDW.DRS_CRR - 1); + } else { + rtDW.DRS_CRR = 3U; + } + + /* End of Switch: '/Switch' */ + } + + /* End of Outputs for SubSystem: '/Subsystem7' */ + + /* Update for UnitDelay: '/Delay Input1' incorporates: + * RelationalOperator: '/FixPt Relational Operator' + * UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + rtDW.DelayInput1_DSTATE_e5 = Enable_Comp_PID; + + /* Update for UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + rtDW.DelayInput1_DSTATE_k = rtb_err; + + /* Update for UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + rtDW.DelayInput1_DSTATE_l = rtb_LogicalOperator6; + + /* Update for UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + rtDW.DelayInput1_DSTATE_kb = rtb_LogicalOperator3; + + /* Update for UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + rtDW.DelayInput1_DSTATE_kk = rtb_LogicalOperator8; + + /* Update for UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + rtDW.DelayInput1_DSTATE_d1 = rtb_LogicalOperator3_cz; + + /* Update for UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + rtDW.DelayInput1_DSTATE_b = rtb_LogicalOperator4_fo; + + /* Update for UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + rtDW.DelayInput1_DSTATE_i = rtb_LogicalOperator6_m; + } + + /* End of DataStoreRead: '/Data Store Read1' */ + /* End of Outputs for SubSystem: '/CHANEL4' */ + + /* Sum: '/Subtract13' incorporates: + * DataStoreRead: '/Data Store Read17' + * DataStoreRead: '/Data Store Read33' + */ + rtb_Bias5 = (int16_t)(rtb_Merge_b - rtb_Bias1_h); + + /* DeadZone: '/Dead Zone6' */ + if (rtb_Bias5 > 5) { + Eva_F_tg = (int16_t)(rtb_Bias5 - 5); + } else if (rtb_Bias5 >= -5) { + Eva_F_tg = 0; + } else { + Eva_F_tg = (int16_t)(rtb_Bias5 - -5); + } + + /* End of DeadZone: '/Dead Zone6' */ + + /* Product: '/Divide4' incorporates: + * Constant: '/Constant36' + * Constant: '/Constant95' + * Product: '/Divide4' + */ + rtb_Add_be = (double)g_assPID_VALVE_FRONT_UP[1] / 1000.0; + + /* Sum: '/Sum' incorporates: + * Constant: '/Constant36' + * Memory: '/Memory1' + * Product: '/Divide4' + */ + tmp_3 = (int64_t)floor(rtb_Add_be * (double)Eva_F_tg) + rtDW.MemComp_I_Value_c; + if (tmp_3 > 2147483647LL) { + tmp_3 = 2147483647LL; + } else if (tmp_3 < -2147483648LL) { + tmp_3 = -2147483648LL; + } + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + * RelationalOperator: '/UpperRelop' + * Sum: '/Sum' + * Switch: '/Switch' + */ + if ((int32_t)tmp_3 > 10000) { + /* Switch: '/Switch2' incorporates: + * Constant: '/Constant4' + */ + rtDW.MemComp_I_Value_c = 10000; + } else if ((int32_t)tmp_3 < 0) { + /* Switch: '/Switch2' incorporates: + * Constant: '/Constant3' + * Switch: '/Switch' + */ + rtDW.MemComp_I_Value_c = 0; + } else { + /* Switch: '/Switch2' */ + rtDW.MemComp_I_Value_c = (int32_t)tmp_3; + } + + /* End of Switch: '/Switch2' */ + + /* Switch: '/Switch12' incorporates: + * Constant: '/Constant1' + * Constant: '/Constant97' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read76' + * DataStoreWrite: '/Data Store Write12' + * RelationalOperator: '/Relational Operator2' + * Switch: '/Switch' + */ + if (rtDW.CCU_AC_MAX > 0) { + rtDW.PID_TempFUL = 0U; + } else if (rtDW.LO_HI_MODE_FL == 1) { + /* DataStoreWrite: '/Data Store Write12' incorporates: + * Constant: '/Constant' + * Switch: '/Switch' + */ + rtDW.PID_TempFUL = 0U; + } else { + /* Sum: '/Sum2' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * Constant: '/Constant2' + * Constant: '/Constant26' + * Constant: '/Constant41' + * Memory: '/pError' + * Product: '/Divide1' + * Product: '/Divide2' + * Product: '/Divide3' + * Product: '/Divide5' + * Product: '/Divide6' + * Sum: '/Sum1' + * Switch: '/Switch' + * + * Block description for '/Divide1': + * Round + * + * Block description for '/Divide3': + * Round + * + * Block description for '/Divide6': + * Round + */ + i = ((int16_t)div_nzp_s32_round((int16_t)floor((double) + g_assPID_VALVE_FRONT_UP[0] / 100.0 * (double)Eva_F_tg), 10) + + (int16_t)div_nzp_s32_round(rtDW.MemComp_I_Value_c, 100)) + (int16_t) + div_nzp_s32_round((int32_t)floor((double)(int16_t)(Eva_F_tg - + rtDW.pError_PreviousInput_g) * ((double)g_assPID_VALVE_FRONT_UP[2] / 100.0)), + 100); + if (i < 0) { + i = 0; + } else if (i > 255) { + i = 255; + } + + /* Saturate: '/Saturation9' incorporates: + * Sum: '/Sum2' + * Switch: '/Switch' + */ + if (i <= 100) { + /* DataStoreWrite: '/Data Store Write12' */ + rtDW.PID_TempFUL = (uint8_t)i; + } else { + /* DataStoreWrite: '/Data Store Write12' */ + rtDW.PID_TempFUL = 100U; + } + + /* End of Saturate: '/Saturation9' */ + } + + /* End of Switch: '/Switch12' */ + + /* Sum: '/Subtract14' incorporates: + * DataStoreRead: '/Data Store Read34' + * DataStoreRead: '/Data Store Read37' + */ + rtb_Bias5 = (int16_t)(rtb_y_he - Duct4_F); + + /* DeadZone: '/Dead Zone8' */ + if (rtb_Bias5 > 5) { + Eva_R_tg = (int16_t)(rtb_Bias5 - 5); + } else if (rtb_Bias5 >= -5) { + Eva_R_tg = 0; + } else { + Eva_R_tg = (int16_t)(rtb_Bias5 - -5); + } + + /* End of DeadZone: '/Dead Zone8' */ + + /* Product: '/Divide4' incorporates: + * Constant: '/Constant55' + * Constant: '/Constant86' + * Product: '/Divide4' + */ + index_start = (double)g_assPID_VALVE_FRONT_LOW[1] / 1000.0; + + /* Sum: '/Sum' incorporates: + * Constant: '/Constant86' + * Memory: '/Memory1' + * Product: '/Divide4' + */ + tmp_3 = (int64_t)floor(index_start * (double)Eva_R_tg) + + rtDW.MemComp_I_Value_m; + if (tmp_3 > 2147483647LL) { + tmp_3 = 2147483647LL; + } else if (tmp_3 < -2147483648LL) { + tmp_3 = -2147483648LL; + } + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + * RelationalOperator: '/UpperRelop' + * Sum: '/Sum' + * Switch: '/Switch' + */ + if ((int32_t)tmp_3 > 10000) { + /* Switch: '/Switch2' incorporates: + * Constant: '/Constant4' + */ + rtDW.MemComp_I_Value_m = 10000; + } else if ((int32_t)tmp_3 < 0) { + /* Switch: '/Switch2' incorporates: + * Constant: '/Constant3' + * Switch: '/Switch' + */ + rtDW.MemComp_I_Value_m = 0; + } else { + /* Switch: '/Switch2' */ + rtDW.MemComp_I_Value_m = (int32_t)tmp_3; + } + + /* End of Switch: '/Switch2' */ + + /* Switch: '/Switch14' incorporates: + * Constant: '/Constant1' + * Constant: '/Constant97' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read76' + * DataStoreWrite: '/Data Store Write13' + * RelationalOperator: '/Relational Operator2' + * Switch: '/Switch' + */ + if (rtDW.CCU_AC_MAX > 0) { + rtDW.PID_TempFRL = 0U; + } else if (rtDW.LO_HI_MODE_FR == 1) { + /* DataStoreWrite: '/Data Store Write13' incorporates: + * Constant: '/Constant' + * Switch: '/Switch' + */ + rtDW.PID_TempFRL = 0U; + } else { + /* Sum: '/Sum2' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * Constant: '/Constant2' + * Constant: '/Constant42' + * Constant: '/Constant87' + * Memory: '/pError' + * Product: '/Divide1' + * Product: '/Divide2' + * Product: '/Divide3' + * Product: '/Divide5' + * Product: '/Divide6' + * Sum: '/Sum1' + * Switch: '/Switch' + * + * Block description for '/Divide1': + * Round + * + * Block description for '/Divide3': + * Round + * + * Block description for '/Divide6': + * Round + */ + i = ((int16_t)div_nzp_s32_round((int16_t)floor((double) + g_assPID_VALVE_FRONT_LOW[0] / 100.0 * (double)Eva_R_tg), 10) + + (int16_t)div_nzp_s32_round(rtDW.MemComp_I_Value_m, 100)) + (int16_t) + div_nzp_s32_round((int32_t)floor((double)(int16_t)(Eva_R_tg - + rtDW.pError_PreviousInput_p) * ((double)g_assPID_VALVE_FRONT_LOW[2] / + 100.0)), 100); + if (i < 0) { + i = 0; + } else if (i > 255) { + i = 255; + } + + /* Saturate: '/Saturation11' incorporates: + * Sum: '/Sum2' + * Switch: '/Switch' + */ + if (i <= 100) { + /* DataStoreWrite: '/Data Store Write13' */ + rtDW.PID_TempFRL = (uint8_t)i; + } else { + /* DataStoreWrite: '/Data Store Write13' */ + rtDW.PID_TempFRL = 100U; + } + + /* End of Saturate: '/Saturation11' */ + } + + /* End of Switch: '/Switch14' */ + + /* Sum: '/Subtract15' incorporates: + * DataStoreRead: '/Data Store Read35' + * DataStoreRead: '/Data Store Read36' + */ + rtb_Bias5 = (int16_t)(rtb_y_ki - rtb_FLU_tg_correct_ot); + + /* DeadZone: '/Dead Zone7' */ + if (rtb_Bias5 > 5) { + rtb_FLU_tg_correct_aa = (int16_t)(rtb_Bias5 - 5); + } else if (rtb_Bias5 >= -5) { + rtb_FLU_tg_correct_aa = 0; + } else { + rtb_FLU_tg_correct_aa = (int16_t)(rtb_Bias5 - -5); + } + + /* End of DeadZone: '/Dead Zone7' */ + + /* Sum: '/Sum' incorporates: + * Memory: '/Memory1' + * Product: '/Divide4' + */ + tmp_3 = (int64_t)floor(index_start * (double)rtb_FLU_tg_correct_aa) + + rtDW.MemComp_I_Value_p; + if (tmp_3 > 2147483647LL) { + tmp_3 = 2147483647LL; + } else if (tmp_3 < -2147483648LL) { + tmp_3 = -2147483648LL; + } + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + * RelationalOperator: '/UpperRelop' + * Sum: '/Sum' + * Switch: '/Switch' + */ + if ((int32_t)tmp_3 > 10000) { + /* Switch: '/Switch2' incorporates: + * Constant: '/Constant4' + */ + rtDW.MemComp_I_Value_p = 10000; + } else if ((int32_t)tmp_3 < 0) { + /* Switch: '/Switch2' incorporates: + * Constant: '/Constant3' + * Switch: '/Switch' + */ + rtDW.MemComp_I_Value_p = 0; + } else { + /* Switch: '/Switch2' */ + rtDW.MemComp_I_Value_p = (int32_t)tmp_3; + } + + /* End of Switch: '/Switch2' */ + + /* Switch: '/Switch13' incorporates: + * Constant: '/Constant1' + * Constant: '/Constant97' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read76' + * DataStoreWrite: '/Data Store Write14' + * RelationalOperator: '/Relational Operator2' + * Switch: '/Switch' + */ + if (rtDW.CCU_AC_MAX > 0) { + rtDW.PID_TempFLL = 0U; + } else if (rtDW.LO_HI_MODE_FL == 1) { + /* DataStoreWrite: '/Data Store Write14' incorporates: + * Constant: '/Constant' + * Switch: '/Switch' + */ + rtDW.PID_TempFLL = 0U; + } else { + /* Sum: '/Sum2' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * Constant: '/Constant2' + * Constant: '/Constant43' + * Constant: '/Constant85' + * Memory: '/pError' + * Product: '/Divide1' + * Product: '/Divide2' + * Product: '/Divide3' + * Product: '/Divide5' + * Product: '/Divide6' + * Sum: '/Sum1' + * Switch: '/Switch' + * + * Block description for '/Divide1': + * Round + * + * Block description for '/Divide3': + * Round + * + * Block description for '/Divide6': + * Round + */ + i = ((int16_t)div_nzp_s32_round((int16_t)floor((double) + g_assPID_VALVE_FRONT_LOW[0] / 100.0 * (double)rtb_FLU_tg_correct_aa), + 10) + (int16_t)div_nzp_s32_round(rtDW.MemComp_I_Value_p, 100)) + + (int16_t)div_nzp_s32_round((int32_t)floor((double)(int16_t) + (rtb_FLU_tg_correct_aa - rtDW.pError_PreviousInput_pe) * ((double) + g_assPID_VALVE_FRONT_LOW[2] / 100.0)), 100); + if (i < 0) { + i = 0; + } else if (i > 255) { + i = 255; + } + + /* Saturate: '/Saturation10' incorporates: + * Sum: '/Sum2' + * Switch: '/Switch' + */ + if (i <= 100) { + /* DataStoreWrite: '/Data Store Write14' */ + rtDW.PID_TempFLL = (uint8_t)i; + } else { + /* DataStoreWrite: '/Data Store Write14' */ + rtDW.PID_TempFLL = 100U; + } + + /* End of Saturate: '/Saturation10' */ + } + + /* End of Switch: '/Switch13' */ + + /* Sum: '/Subtract18' incorporates: + * DataStoreRead: '/Data Store Read42' + * DataStoreRead: '/Data Store Read43' + */ + rtb_Bias5 = (int16_t)(rtb_FLU_tg_correct1 - rtb_MultiportSwitch_pa); + + /* DeadZone: '/Dead Zone11' */ + if (rtb_Bias5 > 5) { + rtb_MultiportSwitch_jq = (int16_t)(rtb_Bias5 - 5); + } else if (rtb_Bias5 >= -5) { + rtb_MultiportSwitch_jq = 0; + } else { + rtb_MultiportSwitch_jq = (int16_t)(rtb_Bias5 - -5); + } + + /* End of DeadZone: '/Dead Zone11' */ + + /* Sum: '/Sum' incorporates: + * Memory: '/Memory1' + * Product: '/Divide4' + */ + tmp_3 = (int64_t)floor(rtb_Add_be * (double)rtb_MultiportSwitch_jq) + + rtDW.MemComp_I_Value_f; + if (tmp_3 > 2147483647LL) { + tmp_3 = 2147483647LL; + } else if (tmp_3 < -2147483648LL) { + tmp_3 = -2147483648LL; + } + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + * RelationalOperator: '/UpperRelop' + * Sum: '/Sum' + * Switch: '/Switch' + */ + if ((int32_t)tmp_3 > 10000) { + /* Switch: '/Switch2' incorporates: + * Constant: '/Constant4' + */ + rtDW.MemComp_I_Value_f = 10000; + } else if ((int32_t)tmp_3 < 0) { + /* Switch: '/Switch2' incorporates: + * Constant: '/Constant3' + * Switch: '/Switch' + */ + rtDW.MemComp_I_Value_f = 0; + } else { + /* Switch: '/Switch2' */ + rtDW.MemComp_I_Value_f = (int32_t)tmp_3; + } + + /* End of Switch: '/Switch2' */ + + /* Switch: '/Switch11' incorporates: + * Constant: '/Constant1' + * Constant: '/Constant97' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read76' + * DataStoreWrite: '/Data Store Write17' + * RelationalOperator: '/Relational Operator2' + * Switch: '/Switch' + */ + if (rtDW.CCU_AC_MAX > 0) { + rtDW.PID_TempFUR = 0U; + } else if (rtDW.LO_HI_MODE_FR == 1) { + /* DataStoreWrite: '/Data Store Write17' incorporates: + * Constant: '/Constant' + * Switch: '/Switch' + */ + rtDW.PID_TempFUR = 0U; + } else { + /* Sum: '/Sum2' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * Constant: '/Constant2' + * Constant: '/Constant94' + * Constant: '/Constant96' + * Memory: '/pError' + * Product: '/Divide1' + * Product: '/Divide2' + * Product: '/Divide3' + * Product: '/Divide5' + * Product: '/Divide6' + * Sum: '/Sum1' + * Switch: '/Switch' + * + * Block description for '/Divide1': + * Round + * + * Block description for '/Divide3': + * Round + * + * Block description for '/Divide6': + * Round + */ + i = ((int16_t)div_nzp_s32_round((int16_t)floor((double) + g_assPID_VALVE_FRONT_UP[0] / 100.0 * (double)rtb_MultiportSwitch_jq), + 10) + (int16_t)div_nzp_s32_round(rtDW.MemComp_I_Value_f, 100)) + + (int16_t)div_nzp_s32_round((int32_t)floor((double)(int16_t) + (rtb_MultiportSwitch_jq - rtDW.pError_PreviousInput_i) * ((double) + g_assPID_VALVE_FRONT_UP[2] / 100.0)), 100); + if (i < 0) { + i = 0; + } else if (i > 255) { + i = 255; + } + + /* Saturate: '/Saturation14' incorporates: + * Sum: '/Sum2' + * Switch: '/Switch' + */ + if (i <= 100) { + /* DataStoreWrite: '/Data Store Write17' */ + rtDW.PID_TempFUR = (uint8_t)i; + } else { + /* DataStoreWrite: '/Data Store Write17' */ + rtDW.PID_TempFUR = 100U; + } + + /* End of Saturate: '/Saturation14' */ + } + + /* End of Switch: '/Switch11' */ + + /* Sum: '/Subtract16' incorporates: + * DataStoreRead: '/Data Store Read38' + * DataStoreRead: '/Data Store Read41' + */ + rtb_Bias5 = (int16_t)(rtDW.Duct_RR_Tg - Duct2_R); + + /* DeadZone: '/Dead Zone10' */ + if (rtb_Bias5 > 5) { + rtb_MultiportSwitch_fu = (int16_t)(rtb_Bias5 - 5); + } else if (rtb_Bias5 >= -5) { + rtb_MultiportSwitch_fu = 0; + } else { + rtb_MultiportSwitch_fu = (int16_t)(rtb_Bias5 - -5); + } + + /* End of DeadZone: '/Dead Zone10' */ + + /* Product: '/Divide4' incorporates: + * Constant: '/Constant90' + * Constant: '/Constant92' + * Product: '/Divide4' + */ + rtb_Add_be = (double)g_assPID_VALVE_REAR[1] / 1000.0; + + /* Sum: '/Sum' incorporates: + * Constant: '/Constant92' + * Memory: '/Memory1' + * Product: '/Divide4' + */ + tmp_3 = (int64_t)floor(rtb_Add_be * (double)rtb_MultiportSwitch_fu) + + rtDW.MemComp_I_Value_n; + if (tmp_3 > 2147483647LL) { + tmp_3 = 2147483647LL; + } else if (tmp_3 < -2147483648LL) { + tmp_3 = -2147483648LL; + } + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + * RelationalOperator: '/UpperRelop' + * Sum: '/Sum' + * Switch: '/Switch' + */ + if ((int32_t)tmp_3 > 10000) { + /* Switch: '/Switch2' incorporates: + * Constant: '/Constant4' + */ + rtDW.MemComp_I_Value_n = 10000; + } else if ((int32_t)tmp_3 < 0) { + /* Switch: '/Switch2' incorporates: + * Constant: '/Constant3' + * Switch: '/Switch' + */ + rtDW.MemComp_I_Value_n = 0; + } else { + /* Switch: '/Switch2' */ + rtDW.MemComp_I_Value_n = (int32_t)tmp_3; + } + + /* End of Switch: '/Switch2' */ + + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write15' + * RelationalOperator: '/Relational Operator2' + */ + if (rtDW.LO_HI_MODE_RR == 1) { + rtDW.PID_TempRR = 0U; + } else { + /* Sum: '/Sum2' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * Constant: '/Constant2' + * Constant: '/Constant88' + * Constant: '/Constant93' + * Memory: '/pError' + * Product: '/Divide1' + * Product: '/Divide2' + * Product: '/Divide3' + * Product: '/Divide5' + * Product: '/Divide6' + * Sum: '/Sum1' + * + * Block description for '/Divide1': + * Round + * + * Block description for '/Divide3': + * Round + * + * Block description for '/Divide6': + * Round + */ + i = ((int16_t)div_nzp_s32_round((int16_t)floor((double)g_assPID_VALVE_REAR[0] + / 100.0 * (double)rtb_MultiportSwitch_fu), 10) + (int16_t) + div_nzp_s32_round(rtDW.MemComp_I_Value_n, 100)) + (int16_t) + div_nzp_s32_round((int32_t)floor((double)(int16_t)(rtb_MultiportSwitch_fu + - rtDW.pError_PreviousInput_b) * ((double)g_assPID_VALVE_REAR[2] / 100.0)), + 100); + if (i < 0) { + i = 0; + } else if (i > 255) { + i = 255; + } + + /* Saturate: '/Saturation13' incorporates: + * Sum: '/Sum2' + */ + if (i <= 100) { + rtDW.PID_TempRR = (uint8_t)i; + } else { + rtDW.PID_TempRR = 100U; + } + + /* End of Saturate: '/Saturation13' */ + } + + /* End of Switch: '/Switch' */ + + /* Sum: '/Subtract17' incorporates: + * DataStoreRead: '/Data Store Read39' + * DataStoreRead: '/Data Store Read40' + */ + rtb_Bias5 = (int16_t)(rtb_y_jh - Duct1_R); + + /* DeadZone: '/Dead Zone9' */ + if (rtb_Bias5 > 5) { + rtb_Bias5 = (int16_t)(rtb_Bias5 - 5); + } else if (rtb_Bias5 >= -5) { + rtb_Bias5 = 0; + } else { + rtb_Bias5 = (int16_t)(rtb_Bias5 - -5); + } + + /* End of DeadZone: '/Dead Zone9' */ + + /* Sum: '/Sum' incorporates: + * Memory: '/Memory1' + * Product: '/Divide4' + */ + tmp_3 = (int64_t)floor(rtb_Add_be * (double)rtb_Bias5) + + rtDW.MemComp_I_Value_m0; + if (tmp_3 > 2147483647LL) { + tmp_3 = 2147483647LL; + } else if (tmp_3 < -2147483648LL) { + tmp_3 = -2147483648LL; + } + + /* Switch: '/Switch2' incorporates: + * RelationalOperator: '/LowerRelop1' + * RelationalOperator: '/UpperRelop' + * Sum: '/Sum' + * Switch: '/Switch' + */ + if ((int32_t)tmp_3 > 10000) { + /* Switch: '/Switch2' incorporates: + * Constant: '/Constant4' + */ + rtDW.MemComp_I_Value_m0 = 10000; + } else if ((int32_t)tmp_3 < 0) { + /* Switch: '/Switch2' incorporates: + * Constant: '/Constant3' + * Switch: '/Switch' + */ + rtDW.MemComp_I_Value_m0 = 0; + } else { + /* Switch: '/Switch2' */ + rtDW.MemComp_I_Value_m0 = (int32_t)tmp_3; + } + + /* End of Switch: '/Switch2' */ + + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write16' + * RelationalOperator: '/Relational Operator2' + */ + if (rtDW.LO_HI_MODE_RL == 1) { + rtDW.PID_TempRL = 0U; + } else { + /* Sum: '/Sum2' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * Constant: '/Constant2' + * Constant: '/Constant89' + * Constant: '/Constant91' + * Memory: '/pError' + * Product: '/Divide1' + * Product: '/Divide2' + * Product: '/Divide3' + * Product: '/Divide5' + * Product: '/Divide6' + * Sum: '/Sum1' + * + * Block description for '/Divide1': + * Round + * + * Block description for '/Divide3': + * Round + * + * Block description for '/Divide6': + * Round + */ + i = ((int16_t)div_nzp_s32_round((int16_t)floor((double)g_assPID_VALVE_REAR[0] + / 100.0 * (double)rtb_Bias5), 10) + (int16_t)div_nzp_s32_round + (rtDW.MemComp_I_Value_m0, 100)) + (int16_t)div_nzp_s32_round((int32_t) + floor((double)(int16_t)(rtb_Bias5 - rtDW.pError_PreviousInput_d) * + ((double)g_assPID_VALVE_REAR[2] / 100.0)), 100); + if (i < 0) { + i = 0; + } else if (i > 255) { + i = 255; + } + + /* Saturate: '/Saturation12' incorporates: + * Sum: '/Sum2' + */ + if (i <= 100) { + rtDW.PID_TempRL = (uint8_t)i; + } else { + rtDW.PID_TempRL = 100U; + } + + /* End of Saturate: '/Saturation12' */ + } + + /* End of Switch: '/Switch' */ + + /* Product: '/Divide' incorporates: + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read6' + * DataStoreRead: '/Data Store Read7' + * Sum: '/Add' + */ + rtb_Add_be = (double)(int16_t)((uint32_t)Gain + Gain1) / 4.0; + + /* Switch: '/Switch' */ + if (rtb_Add_be > 0.0) { + /* Saturate: '/Saturation2' */ + if (rtb_Add_be > 80.0) { + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * DataStoreWrite: '/Data Store Write2' + */ + rtDW.PWM_front = 80U; + } else if (rtb_Add_be < 15.0) { + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * DataStoreWrite: '/Data Store Write2' + */ + rtDW.PWM_front = 15U; + } else { + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * DataStoreWrite: '/Data Store Write2' + */ + rtDW.PWM_front = (uint8_t)rtb_Add_be; + } + + /* End of Saturate: '/Saturation2' */ + } else { + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * Constant: '/Constant1' + * DataStoreWrite: '/Data Store Write2' + */ + rtDW.PWM_front = 0U; + } + + /* End of Switch: '/Switch' */ + + /* Product: '/Divide1' incorporates: + * Constant: '/Constant2' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read3' + * Sum: '/Add1' + */ + rtb_Add_be = (double)(int16_t)((uint32_t)rtb_Saturation2_a + rtb_out_ew) / 4.0; + + /* Switch: '/Switch1' */ + if (rtb_Add_be > 0.0) { + /* Saturate: '/Saturation1' */ + if (rtb_Add_be > 80.0) { + /* DataTypeConversion: '/Data Type Conversion2' incorporates: + * DataStoreWrite: '/Data Store Write3' + */ + rtDW.PWM_rear = 80U; + } else if (rtb_Add_be < 15.0) { + /* DataTypeConversion: '/Data Type Conversion2' incorporates: + * DataStoreWrite: '/Data Store Write3' + */ + rtDW.PWM_rear = 15U; + } else { + /* DataTypeConversion: '/Data Type Conversion2' incorporates: + * DataStoreWrite: '/Data Store Write3' + */ + rtDW.PWM_rear = (uint8_t)rtb_Add_be; + } + + /* End of Saturate: '/Saturation1' */ + } else { + /* DataTypeConversion: '/Data Type Conversion2' incorporates: + * Constant: '/Constant3' + * DataStoreWrite: '/Data Store Write3' + */ + rtDW.PWM_rear = 0U; + } + + /* End of Switch: '/Switch1' */ + + /* Switch: '/Switch2' incorporates: + * DataStoreRead: '/Data Store Read64' + * Switch: '/Switch3' + */ + if (rtDW.BCM_T15_Stat > 0) { + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreWrite: '/Data Store Write' + * DataStoreWrite: '/Data Store Write2' + * DataStoreWrite: '/Data Store Write3' + */ + PWM_Get.pwmPercentFront = rtDW.PWM_front; + PWM_Get.pwmPercentRear = rtDW.PWM_rear; + } else { + /* BusCreator: '/Bus Creator' incorporates: + * Constant: '/Constant5' + * Constant: '/Constant6' + * DataStoreWrite: '/Data Store Write' + */ + PWM_Get.pwmPercentFront = 0U; + PWM_Get.pwmPercentRear = 0U; + } + + /* End of Switch: '/Switch2' */ + + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + PWM_Get.pwmPercentFrontReserved = 0U; + PWM_Get.pwmPercentRearReserved = 0U; + + /* BusCreator: '/Bus Creator1' incorporates: + * DataStoreRead: '/Data Store Read51' + * DataStoreRead: '/Data Store Read52' + * DataStoreRead: '/Data Store Read53' + * DataStoreRead: '/Data Store Read54' + * DataStoreRead: '/Data Store Read56' + * DataStoreRead: '/Data Store Read57' + * DataStoreRead: '/Data Store Read58' + * DataStoreRead: '/Data Store Read59' + * DataStoreRead: '/Data Store Read60' + * DataStoreRead: '/Data Store Read61' + * DataStoreRead: '/Data Store Read62' + * DataStoreRead: '/Data Store Read63' + * DataStoreRead: '/Data Store Read64' + * DataStoreRead: '/Data Store Read65' + * DataStoreRead: '/Data Store Read66' + * DataStoreRead: '/Data Store Read67' + * DataStoreWrite: '/Data Store Write27' + * DataStoreWrite: '/Data Store Write8' + * DataTypeConversion: '/Data Type Conversion1' + * DataTypeConversion: '/Data Type Conversion2' + * DataTypeConversion: '/Data Type Conversion3' + * DataTypeConversion: '/Data Type Conversion4' + * Logic: '/Logical Operator2' + * Logic: '/Logical Operator3' + * Logic: '/Logical Operator4' + * Logic: '/Logical Operator5' + */ + /* : if(LOGGER) */ + rtDW.PowerEnable_Model.SW5V_EN = rtDW.SW5V_EN; + rtDW.PowerEnable_Model.PBATT_CK_EN = rtDW.PBATT_CK_EN; + rtDW.PowerEnable_Model.Incar_Motor_Front_EN = rtDW.Incar_Motor_Front_EN; + rtDW.PowerEnable_Model.Incar_Motor_Rear_EN = rtDW.Incar_Motor_Rear_EN; + rtDW.PowerEnable_Model.TwoWayValve_EN = (uint8_t)(rtB.Cmd_2Way == 0); + rtDW.PowerEnable_Model.ReservePower_EN = rtDW.ReservePower_EN; + rtDW.PowerEnable_Model.PtcRelayDriver1_EN = rtDW.PtcRelayDriver1_EN; + rtDW.PowerEnable_Model.PtcRelayDriver2_EN = rtDW.PtcRelayDriver2_EN; + rtDW.PowerEnable_Model.ShutOffFront_EN = (uint8_t)(ShutOffFront_EN == 0); + rtDW.PowerEnable_Model.ShutOffRear_EN = (uint8_t)(ShutOffRear_EN == 0); + rtDW.PowerEnable_Model.EN_ReservePower = rtDW.EN_ReservePower; + rtDW.PowerEnable_Model.LIN_ActPower_AB = rtDW.LIN_ActPower_AB; + rtDW.PowerEnable_Model.LIN_ActPower_C = rtDW.LIN_ActPower_C; + rtDW.PowerEnable_Model.ShutOffTXV1_EN = rtDW.ShutOffTXV1_EN; + rtDW.PowerEnable_Model.ShutOffTXV2_EN = rtDW.ShutOffTXV2_EN; + rtDW.PowerEnable_Model.EN_BATTChiller = (uint8_t)(EN_BATTChiller == 0); + rtDW.PowerEnable_Model.EN_PowerReserve = rtDW.EN_PowerReserve; + + /* Outport: '/PWM_Get' incorporates: + * DataStoreRead: '/Data Store Read7' + */ + rtY.PWM_Get_f = PWM_Get; + + /* SwitchCase: '/Incar Motors' incorporates: + * Constant: '/Constant' + * Constant: '/Constant' + * Constant: '/Constant' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read2' + * Logic: '/Logical Operator' + * Logic: '/Logical Operator1' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + * RelationalOperator: '/Compare' + */ + if ((rtDW.BCM_T15_Stat != 0) && ((rtDW.CCU_BLOWERS_RL != 0) || + (rtDW.CCU_BLOWERS_RR != 0))) { + /* Outputs for IfAction SubSystem: '/Subsystem2' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/Constant' + */ + rtDW.Incar_Motor_Front_EN = 1U; + + /* DataStoreWrite: '/Data Store Write3' incorporates: + * Constant: '/Constant' + */ + rtDW.Incar_Motor_Rear_EN = 1U; + + /* End of Outputs for SubSystem: '/Subsystem2' */ + } else { + /* Outputs for IfAction SubSystem: '/Subsystem' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/Constant' + */ + rtDW.Incar_Motor_Front_EN = 0U; + + /* DataStoreWrite: '/Data Store Write3' incorporates: + * Constant: '/Constant' + */ + rtDW.Incar_Motor_Rear_EN = 0U; + + /* End of Outputs for SubSystem: '/Subsystem' */ + } + + /* End of SwitchCase: '/Incar Motors' */ + + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreRead: '/Data Store Read2' + * DataStoreWrite: '/Data Store Write' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtDW.dbgCAN_dbg_Sen_0_model.dbg_Sen_BattVolt_ro = 0U; + rtDW.dbgCAN_dbg_Sen_0_model.dbg_Sen_Pressure_ro = (uint16_t)rtDW.Pressure; + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * DataStoreRead: '/Data Store Read' + */ + rtb_Add_be = fabs(rtDW.Sun_L); + if (rtb_Add_be < 4.503599627370496E+15) { + if (rtb_Add_be >= 0.5) { + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + rtDW.dbgCAN_dbg_Sen_0_model.dbg_Sen_Sun_L = (uint16_t)floor(rtDW.Sun_L + + 0.5); + } else { + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + rtDW.dbgCAN_dbg_Sen_0_model.dbg_Sen_Sun_L = 0U; + } + } else { + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + rtDW.dbgCAN_dbg_Sen_0_model.dbg_Sen_Sun_L = (uint16_t)rtDW.Sun_L; + } + + /* End of DataTypeConversion: '/Data Type Conversion' */ + + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + rtb_Add_be = fabs(rtDW.Sun_R); + if (rtb_Add_be < 4.503599627370496E+15) { + if (rtb_Add_be >= 0.5) { + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + rtDW.dbgCAN_dbg_Sen_0_model.dbg_Sen_Sun_R = (uint16_t)floor(rtDW.Sun_R + + 0.5); + } else { + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + rtDW.dbgCAN_dbg_Sen_0_model.dbg_Sen_Sun_R = 0U; + } + } else { + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + rtDW.dbgCAN_dbg_Sen_0_model.dbg_Sen_Sun_R = (uint16_t)rtDW.Sun_R; + } + + /* End of DataTypeConversion: '/Data Type Conversion1' */ + + /* BusCreator: '/Bus Creator1' incorporates: + * Constant: '/Constant10' + * Constant: '/Constant6' + * Constant: '/Constant7' + * Constant: '/Constant8' + * Constant: '/Constant9' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read10' + * DataStoreRead: '/Data Store Read11' + * DataStoreRead: '/Data Store Read12' + * DataStoreRead: '/Data Store Read13' + * DataStoreRead: '/Data Store Read15' + * DataStoreRead: '/Data Store Read17' + * DataStoreRead: '/Data Store Read19' + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read3' + * DataStoreRead: '/Data Store Read4' + * DataStoreRead: '/Data Store Read5' + * DataStoreRead: '/Data Store Read6' + * DataStoreRead: '/Data Store Read7' + * DataStoreRead: '/Data Store Read8' + * DataStoreRead: '/Data Store Read9' + * DataStoreWrite: '/Data Store Write1' + */ + rtDW.dbgCAN_dbg_Sen_Duct_model.dbg_Sen_Duct_MultMsg_Idx = 0U; + rtDW.dbgCAN_dbg_Sen_Duct_model.dbg_Sen_Duct_FL_Fb_Select = 0U; + rtDW.dbgCAN_dbg_Sen_Duct_model.dbg_Sen_Duct_RR_Fb_Select = 0U; + rtDW.dbgCAN_dbg_Sen_Duct_model.dbg_Sen_Duct_RL_Fb_Select = 0U; + rtDW.dbgCAN_dbg_Sen_Duct_model.dbg_Sen_Duct_FR_Fb_Select = 0U; + rtDW.dbgCAN_dbg_Sen_Duct_model.dbg_Sen_Duct_RL_Tgt_ro = rtb_y_jh; + rtDW.dbgCAN_dbg_Sen_Duct_model.dbg_Sen_Duct_FR_Upper_Tgt_ro = + rtb_FLU_tg_correct1; + rtDW.dbgCAN_dbg_Sen_Duct_model.dbg_Sen_Duct_RR_Tgt_ro = rtDW.Duct_RR_Tg; + rtDW.dbgCAN_dbg_Sen_Duct_model.dbg_Sen_Duct_FL_Upper_Tgt_ro = rtb_Merge_b; + rtDW.dbgCAN_dbg_Sen_Duct_model.dbg_Sen_Duct_RR_Fb_ro = Duct2_R; + rtDW.dbgCAN_dbg_Sen_Duct_model.dbg_Sen_Duct_RL_Fb_ro = Duct1_R; + rtDW.dbgCAN_dbg_Sen_Duct_model.dbg_Sen_Duct_FR_Upper_Fb_ro = + rtb_MultiportSwitch_pa; + rtDW.dbgCAN_dbg_Sen_Duct_model.dbg_Sen_Duct_FL_Upper_Fb_ro = rtb_Bias1_h; + rtDW.dbgCAN_dbg_Sen_Duct_model.dbg_Sen_Duct_FR_Side_Fb_ro = Duct6_F; + rtDW.dbgCAN_dbg_Sen_Duct_model.dbg_Sen_Duct_FL_Side_Fb_ro = Duct5_F; + rtDW.dbgCAN_dbg_Sen_Duct_model.dbg_Sen_Duct_RL_Side_Fb_ro = Duct3_R; + rtDW.dbgCAN_dbg_Sen_Duct_model.dbg_Sen_Duct_RR_Side_Fb_ro = Duct4_R; + rtDW.dbgCAN_dbg_Sen_Duct_model.dbg_Sen_Duct_FR_Lower_Tgt_ro = rtb_y_he; + rtDW.dbgCAN_dbg_Sen_Duct_model.dbg_Sen_Duct_FL_Lower_Tgt_ro = rtb_y_ki; + rtDW.dbgCAN_dbg_Sen_Duct_model.dbg_Sen_Duct_FR_Lower_Fb_ro = Duct4_F; + rtDW.dbgCAN_dbg_Sen_Duct_model.dbg_Sen_Duct_FL_Lower_Fb_ro = + rtb_FLU_tg_correct_ot; + + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + rtDW.dbg_Logic_Valve_Plus_model.dbg_Auto_Valve_Plus_Vent_SFL_ro = 0; + rtDW.dbg_Logic_Valve_Plus_model.dbg_Auto_Valve_Plus_Vent_CFL_ro = 0; + rtDW.dbg_Logic_Valve_Plus_model.dbg_Auto_Valve_Plus_Foot_FL_ro = 0; + rtDW.dbg_Logic_Valve_Plus_model.dbg_Auto_Valve_Plus_Vent_SFR_ro = 0; + rtDW.dbg_Logic_Valve_Plus_model.dbg_Auto_Valve_Plus_Vent_CFR_ro = 0; + rtDW.dbg_Logic_Valve_Plus_model.dbg_Auto_Valve_Plus_Foot_FR_ro = 0; + + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read53' + * DataStoreRead: '/Data Store Read54' + * DataStoreRead: '/Data Store Read6' + * DataStoreWrite: '/Data Store Write27' + * DataStoreWrite: '/Data Store Write' + */ + rtDW.dbgCAN_CCU_IO_model.dbg_IO_Txv_F = ShutOffFront_EN; + rtDW.dbgCAN_CCU_IO_model.dbg_IO_Txv_R = ShutOffRear_EN; + rtDW.dbgCAN_CCU_IO_model.dbg_IO_Txv_Ch = EN_BATTChiller; + rtDW.dbgCAN_CCU_IO_model.dbg_IO_2WayValve = rtB.Cmd_2Way; + rtDW.dbgCAN_CCU_IO_model.dbg_IO_IncarMotor_F = rtDW.Incar_Motor_Front_EN; + rtDW.dbgCAN_CCU_IO_model.dbg_IO_IncarMotor_R = rtDW.Incar_Motor_Rear_EN; + + /* Saturate: '/Saturation' incorporates: + * DataStoreRead: '/Data Store Read2' + */ + if (rtDW.CCU_SET_FL > 310) { + rtb_out_h0 = 310U; + } else if (rtDW.CCU_SET_FL < 155) { + rtb_out_h0 = 155U; + } else { + rtb_out_h0 = rtDW.CCU_SET_FL; + } + + /* BusCreator: '/Bus Creator' incorporates: + * Bias: '/Bias' + * DataStoreWrite: '/Data Store Write' + * DataTypeConversion: '/Data Type Conversion' + * Gain: '/Gain' + * Gain: '/Gain1' + * Saturate: '/Saturation' + */ + rtDW.dbgCAN_CCU_IO_model.dbg_SetTemp_FL_ro = (uint8_t)((0.10000038146972656 * + (double)rtb_out_h0 - 16.0) * 2.0); + + /* Saturate: '/Saturation' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + if (rtDW.CCU_SET_FR > 310) { + rtb_out_h0 = 310U; + } else if (rtDW.CCU_SET_FR < 155) { + rtb_out_h0 = 155U; + } else { + rtb_out_h0 = rtDW.CCU_SET_FR; + } + + /* BusCreator: '/Bus Creator' incorporates: + * Bias: '/Bias' + * DataStoreWrite: '/Data Store Write' + * DataTypeConversion: '/Data Type Conversion' + * Gain: '/Gain' + * Gain: '/Gain1' + * Saturate: '/Saturation' + */ + rtDW.dbgCAN_CCU_IO_model.dbg_SetTemp_FR_ro = (uint8_t)((0.10000038146972656 * + (double)rtb_out_h0 - 16.0) * 2.0); + + /* Saturate: '/Saturation' incorporates: + * DataStoreRead: '/Data Store Read4' + */ + if (rtDW.CCU_SET_RL > 310) { + rtb_out_h0 = 310U; + } else if (rtDW.CCU_SET_RL < 155) { + rtb_out_h0 = 155U; + } else { + rtb_out_h0 = rtDW.CCU_SET_RL; + } + + /* BusCreator: '/Bus Creator' incorporates: + * Bias: '/Bias' + * DataStoreWrite: '/Data Store Write' + * DataTypeConversion: '/Data Type Conversion' + * Gain: '/Gain' + * Gain: '/Gain1' + * Saturate: '/Saturation' + */ + rtDW.dbgCAN_CCU_IO_model.dbg_SetTemp_RL_ro = (uint8_t)((0.10000038146972656 * + (double)rtb_out_h0 - 16.0) * 2.0); + + /* Saturate: '/Saturation' incorporates: + * DataStoreRead: '/Data Store Read5' + */ + if (rtDW.CCU_SET_RR > 310) { + rtb_out_h0 = 310U; + } else if (rtDW.CCU_SET_RR < 155) { + rtb_out_h0 = 155U; + } else { + rtb_out_h0 = rtDW.CCU_SET_RR; + } + + /* BusCreator: '/Bus Creator' incorporates: + * Bias: '/Bias' + * DataStoreWrite: '/Data Store Write' + * DataTypeConversion: '/Data Type Conversion' + * Gain: '/Gain' + * Gain: '/Gain1' + * Saturate: '/Saturation' + */ + rtDW.dbgCAN_CCU_IO_model.dbg_SetTemp_RR_ro = (uint8_t)((0.10000038146972656 * + (double)rtb_out_h0 - 16.0) * 2.0); + rtDW.dbgCAN_CCU_IO_model.dbg_IO_Input_Emergency = 0U; + rtDW.dbgCAN_CCU_IO_model.dbg_IO_Input_FireExtinguisher = 0U; + rtDW.dbgCAN_CCU_IO_model.dbg_IO_Install_Sealing_Valve = 0U; + + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read3' + * DataStoreRead: '/Data Store Read4' + * DataStoreRead: '/Data Store Read5' + * DataStoreRead: '/Data Store Read6' + * DataStoreRead: '/Data Store Read7' + * DataStoreWrite: '/Data Store Write' + */ + rtDW.dbg_Drs_t_model.dbg_Drs_0_SFL_DL = rtDW.DRS_SFL; + rtDW.dbg_Drs_t_model.dbg_Drs_1_CFL_FPL = rtDW.DRS_CFL; + rtDW.dbg_Drs_t_model.dbg_Drs_2_CFR_FPR = rtDW.DRS_CFR; + rtDW.dbg_Drs_t_model.dbg_Drs_3_SFR_DR = rtDW.DRS_SFR; + rtDW.dbg_Drs_t_model.dbg_Drs_4_SRL_RLB = rtDW.DRS_SRL; + rtDW.dbg_Drs_t_model.dbg_Drs_5_CRL_FCL = rtDW.DRS_CRL; + rtDW.dbg_Drs_t_model.dbg_Drs_6_CRR_FCR = rtDW.DRS_CRR; + rtDW.dbg_Drs_t_model.dbg_Drs_7_SRR_RRB = rtDW.DRS_SRR; + + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read5' + * DataStoreRead: '/Data Store Read6' + * DataStoreRead: '/Data Store Read7' + * DataStoreWrite: '/Data Store Write' + * DataStoreWrite: '/Data Store Write2' + * DataStoreWrite: '/Data Store Write25' + * DataStoreWrite: '/Data Store Write26' + * DataStoreWrite: '/Data Store Write' + */ + rtDW.dbg_LIN_AirQS_Stat_t_model.LIN_AirQS_LinRespErr_Stat = + rtDW.LIN4_AirQS_Stat_Model.AirQS_LinRespErr_Stat; + rtDW.dbg_LIN_AirQS_Stat_t_model.LIN_AirQualSen_Stat = + rtDW.LIN4_AirQS_Stat_Model.AirQS_Sens_Stat; + rtDW.dbg_LIN_AirQS_Stat_t_model.LIN_AirQualSenCombined_Val = + rtDW.LIN4_AirQS_Stat_Model.AirQS_Combined_Stat; + rtDW.dbg_LIN_AirQS_Stat_t_model.LIN_AirQualSen_Error_Stat = + rtDW.LIN4_AirQS_Stat_Model.AirQS_Err_Stat; + rtDW.dbg_LIN_AirQS_Stat_t_model.LIN_AirQualSenCOlvl_Val = rtDW.AirQS_COLvl; + rtDW.dbg_LIN_AirQS_Stat_t_model.LIN_AirQualSenNOxlvl_Val = rtDW.AirQS_NOxLvl; + rtDW.dbg_LIN_AirQS_Stat_t_model.LIN_AirQualSenNH3lvl_Val = rtDW.AirQS_NH3Lvl; + + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreRead: '/Data Store Read2' + * DataStoreWrite: '/Data Store Write27' + * DataStoreWrite: '/Data Store Write28' + * DataStoreWrite: '/Data Store Write' + */ + rtDW.dbg_LIN_Aroma_Stat_t_model.LIN_AromaLinRespErr_Stat = + rtDW.LIN4_Aroma_Stat_Model.Aroma_LinRespErr_Stat; + rtDW.dbg_LIN_Aroma_Stat_t_model.LIN_Aroma_1CartridgeSw = 0U; + rtDW.dbg_LIN_Aroma_Stat_t_model.LIN_Aroma_2CartridgeSw = 0U; + rtDW.dbg_LIN_Aroma_Stat_t_model.LIN_Aroma_3CartridgeSw = 0U; + rtDW.dbg_LIN_Aroma_Stat_t_model.LIN_Aroma_Error_Stat = + rtDW.LIN4_Aroma_Stat_Model.Aroma_Err_Stat; + rtDW.dbg_LIN_Aroma_Stat_t_model.LIN_Aroma_Intens = 0U; + rtDW.dbg_LIN_Aroma_Stat_t_model.LIN_Aroma_CartridgeSel = 0U; + rtDW.dbg_LIN_Aroma_Stat_t_model.LIN_Aroma_1CartridgeFlavor = 0U; + rtDW.dbg_LIN_Aroma_Stat_t_model.LIN_Aroma_2CartridgeFlavor = 0U; + rtDW.dbg_LIN_Aroma_Stat_t_model.LIN_Aroma_3CartridgeFlavor = 0U; + rtDW.dbg_LIN_Aroma_Stat_t_model.LIN_Aroma_1CartridgeCapacity = 0U; + rtDW.dbg_LIN_Aroma_Stat_t_model.LIN_Aroma_2CartridgeCapacity = 0U; + rtDW.dbg_LIN_Aroma_Stat_t_model.LIN_Aroma_3CartridgeCapacity = 0U; + + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreRead: '/Data Store Read3' + * DataStoreWrite: '/Data Store Write15' + * DataStoreWrite: '/Data Store Write29' + * DataStoreWrite: '/Data Store Write30' + * DataStoreWrite: '/Data Store Write' + */ + rtDW.dbg_LIN_Ionizer_Stat_t_model.LIN_Ionizer_Err_Stat = + rtDW.LIN4_Ionizer_Stat_Model.Ionizer_LinRespErr_Stat; + rtDW.dbg_LIN_Ionizer_Stat_t_model.LIN_Ionizer_LinRespErr = + rtDW.LIN4_Ionizer_Stat_Model.Ionizer_Err_Stat; + rtDW.dbg_LIN_Ionizer_Stat_t_model.LIN_Ionizer_Ionization = + rtDW.LIN4_Ionizer_Stat_Model.Ionizer_Ionization_Stat; + + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read3' + * DataStoreRead: '/Data Store Read4' + * DataStoreRead: '/Data Store Read55' + * DataStoreRead: '/Data Store Read7' + * DataStoreWrite: '/Data Store Write' + * DataStoreWrite: '/Data Store Write' + * DataTypeConversion: '/Data Type Conversion2' + */ + rtDW.dbg_Logic_Ac_model.Logic_Ac_Req_Front = rtDW.CCU_AC_FRONT; + rtDW.dbg_Logic_Ac_model.Logic_Ac_Txv_Front = ShutOffFront_EN; + rtDW.dbg_Logic_Ac_model.Logic_Ac_Txv_Rear = ShutOffRear_EN; + rtDW.dbg_Logic_Ac_model.Logic_Ac_Req_Rear = rtDW.CCU_AC_REAR; + rtDW.dbg_Logic_Ac_model.Logic_Ac_Req_Chiller = rtDW.eCompChiller_Req; + rtDW.dbg_Logic_Ac_model.Logic_Ac_Txv_Chiller = EN_BATTChiller; + rtDW.dbg_Logic_Ac_model.Logic_Ac_EvaCtrl = rtB.Eva_Ctrl; + rtDW.dbg_Logic_Ac_model.Logic_Ac_Comp_EmrStop_Reason = eComp_stop; + + /* Switch: '/Switch4' */ + if (rtB.Chiller_Only_Flag > 0.0) { + /* BusCreator: '/Bus Creator' incorporates: + * Constant: '/Constant' + * DataStoreWrite: '/Data Store Write' + */ + rtDW.dbg_Logic_Ac_model.Logic_Ac_Comp_LimitRpm_ro = g_ucAC_EXTRA_RPM; + } else { + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + rtDW.dbg_Logic_Ac_model.Logic_Ac_Comp_LimitRpm_ro = Comp_Max_RPM_Allowed; + } + + /* End of Switch: '/Switch4' */ + + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + rtDW.dbg_Logic_Ac_model.Logic_Ac_Txv_Closed_bySen = 0U; + rtDW.dbg_Logic_Ac_model.Logic_Ac_WinterSts_Front = 0U; + rtDW.dbg_Logic_Ac_model.Logic_Ac_WinterSts_Rear = 0U; + + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreRead: '/Data Store Read2' + * DataStoreWrite: '/Data Store Write' + * DataStoreWrite: '/Data Store Write3' + */ + rtDW.dbgCAN_Logic_Rec_model.Logic_Rec_Idx = rtDW.Full_Rec; + rtDW.dbgCAN_Logic_Rec_model.Logic_Rec_Partial_Winter = 0U; + rtDW.dbgCAN_Logic_Rec_model.Logic_Rec_Partial_Summer = + rtb_DataTypeConversion1_nc; + rtDW.dbgCAN_Logic_Rec_model.Logic_Rec_FreshAirPurge_Sts = 0U; + + /* BusCreator: '/Bus Creator' incorporates: + * Constant: '/Constant' + * Constant: '/Constant1' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read3' + * DataStoreRead: '/Data Store Read4' + * DataStoreWrite: '/Data Store Write' + * Sum: '/Sum' + * Sum: '/Sum1' + */ + rtDW.dbgCAN_Logic_State_model.Logic_Operation_Mode = 0U; + rtDW.dbgCAN_Logic_State_model.Logic_Amb_Level = rtDW.LEVEL; + rtDW.dbgCAN_Logic_State_model.Logic_AutoDemist_Electric = 0U; + rtDW.dbgCAN_Logic_State_model.Logic_AutoDemist_Garage = 0U; + rtDW.dbgCAN_Logic_State_model.Logic_AutoDemist_Lv_Summer = 0U; + rtDW.dbgCAN_Logic_State_model.Logic_RemoteStart = 0U; + rtDW.dbgCAN_Logic_State_model.Logic_Rest_Mode = 0U; + rtDW.dbgCAN_Logic_State_model.Logic_LoHi_Front = rtDW.CAN_LoHi_Front; + rtDW.dbgCAN_Logic_State_model.Logic_2WayValve_Status = 0U; + rtDW.dbgCAN_Logic_State_model.Logic_Full_Auto_FL = 0U; + rtDW.dbgCAN_Logic_State_model.Logic_Full_Auto_FR = 0U; + rtDW.dbgCAN_Logic_State_model.Logic_Full_Auto_RL = 0U; + rtDW.dbgCAN_Logic_State_model.Logic_Full_Auto_RR = 0U; + rtDW.dbgCAN_Logic_State_model.Logic_Full_MaxAc = 0U; + rtDW.dbgCAN_Logic_State_model.Logic_Full_MaxDef = 0U; + rtDW.dbgCAN_Logic_State_model.Logic_Start_Ctrl_Front = (uint8_t) + (rtDW.step_start_controle_front + 1); + rtDW.dbgCAN_Logic_State_model.Logic_Start_Ctrl_Rear = (uint8_t) + (rtDW.step_start_controle_rear + 1); + rtDW.dbgCAN_Logic_State_model.Logic_Valve_Use_DiffBlr_R2 = 0U; + rtDW.dbgCAN_Logic_State_model.Logic_Duct_WaitCorrection_FRL = 0U; + rtDW.dbgCAN_Logic_State_model.Logic_Duct_WaitCorrection_FLL = 0U; + rtDW.dbgCAN_Logic_State_model.Logic_AutoDemist_Lv_Winter = 0U; + rtDW.dbgCAN_Logic_State_model.Logic_AF_WaitCorrection_FL = 0U; + rtDW.dbgCAN_Logic_State_model.Logic_AF_WaitCorrection_FR = 0U; + + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write' + */ + rtDW.dbg_Logic_Valve_model.Logic_Valve_Index_FL = rtDW.ModeIndex[0]; + rtDW.dbg_Logic_Valve_model.Logic_Valve_Index_FR = rtDW.ModeIndex[1]; + rtDW.dbg_Logic_Valve_model.Logic_Valve_Index_RL = rtDW.ModeIndex[2]; + rtDW.dbg_Logic_Valve_model.Logic_Valve_Index_RR = rtDW.ModeIndex[3]; + rtDW.dbg_Logic_Valve_model.Logic_Valve_Direction_FL = 0U; + rtDW.dbg_Logic_Valve_model.Logic_Valve_Direction_FR = 0U; + rtDW.dbg_Logic_Valve_model.Logic_Valve_Direction_RL = 0U; + rtDW.dbg_Logic_Valve_model.Logic_Valve_Direction_RR = 0U; + + /* BusCreator: '/Bus Creator1' incorporates: + * DataStoreRead: '/Data Store Read4' + * DataStoreWrite: '/Data Store Write2' + * DataStoreWrite: '/Data Store Write1' + */ + rtDW.dbgCAN_dbg_Act0_model.dbg_Act00_Def = rtb_DataTypeConversion_b4q[0]; + rtDW.dbgCAN_dbg_Act0_model.dbg_Act01_Vent_SFL = rtb_DataTypeConversion_b4q[5]; + rtDW.dbgCAN_dbg_Act0_model.dbg_Act02_Vent_CFL = rtb_DataTypeConversion_b4q[4]; + rtDW.dbgCAN_dbg_Act0_model.dbg_Act03_Foot_1FL = rtb_DataTypeConversion_b4q[7]; + rtDW.dbgCAN_dbg_Act0_model.dbg_Act04_Foot_2FL = rtb_DataTypeConversion_b4q[8]; + rtDW.dbgCAN_dbg_Act0_model.dbg_Act05_Vent_CFR = Actuator_pos_percent_Ch1[1]; + rtDW.dbgCAN_dbg_Act0_model.dbg_Act06_Vent_SFR = Actuator_pos_percent_Ch1[2]; + rtDW.dbgCAN_dbg_Act0_model.dbg_Act07_Foot_1FR = Actuator_pos_percent_Ch1[4]; + + /* BusCreator: '/Bus Creator3' incorporates: + * DataStoreRead: '/Data Store Read4' + * DataStoreRead: '/Data Store Read5' + * DataStoreWrite: '/Data Store Write2' + * DataStoreWrite: '/Data Store Write2' + */ + rtDW.dbgCAN_dbg_Act2_model.dbg_Act16_TempL_FL = rtb_DataTypeConversion_b4q[6]; + rtDW.dbgCAN_dbg_Act2_model.dbg_Act17_TempU_FR = Actuator_pos_percent_Ch1[0]; + rtDW.dbgCAN_dbg_Act2_model.dbg_Act18_TempL_FR = Actuator_pos_percent_Ch1[3]; + rtDW.dbgCAN_dbg_Act2_model.dbg_Act19_Temp_RL = rtb_DataTypeConversion_kl[1]; + rtDW.dbgCAN_dbg_Act2_model.dbg_Act20_Temp_RR = rtb_DataTypeConversion_kl[0]; + rtDW.dbgCAN_dbg_Act2_model.dbg_Act21_Rec = rtb_DataTypeConversion_b4q[1]; + rtDW.dbgCAN_dbg_Act2_model.dbg_Act22_OSA = rtb_DataTypeConversion_b4q[2]; + rtDW.dbgCAN_dbg_Act2_model.dbg_Act23_SealingValve = rtb_DataTypeConversion_kl + [8]; + + /* BusCreator: '/Bus Creator2' incorporates: + * DataStoreRead: '/Data Store Read4' + * DataStoreRead: '/Data Store Read5' + * DataStoreWrite: '/Data Store Write2' + * DataStoreWrite: '/Data Store Write3' + */ + rtDW.dbgCAN_dbg_Act1_model.dbg_Act08_Foot_2FR = Actuator_pos_percent_Ch1[5]; + rtDW.dbgCAN_dbg_Act1_model.dbg_Act09_Vent_SRL = rtb_DataTypeConversion_kl[2]; + rtDW.dbgCAN_dbg_Act1_model.dbg_Act10_Vent_CRL = rtb_DataTypeConversion_kl[4]; + rtDW.dbgCAN_dbg_Act1_model.dbg_Act11_Foot_RL = rtb_DataTypeConversion_kl[3]; + rtDW.dbgCAN_dbg_Act1_model.dbg_Act12_Vent_CRR = rtb_DataTypeConversion_kl[5]; + rtDW.dbgCAN_dbg_Act1_model.dbg_Act13_Vent_SRR = rtb_DataTypeConversion_kl[7]; + rtDW.dbgCAN_dbg_Act1_model.dbg_Act14_Foot_RR = rtb_DataTypeConversion_kl[6]; + rtDW.dbgCAN_dbg_Act1_model.dbg_Act15_TempU_FL = rtb_DataTypeConversion_b4q[3]; + + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read1' + * DataStoreWrite: '/Data Store Write' + */ + rtDW.dbgCAN_dbg_Sen_Amb_model.dbg_Sen_Amb_ro = rtDW.AMB; + rtDW.dbgCAN_dbg_Sen_Amb_model.dbg_Sen_Amb_Raw_ro = rtDW.AMB; + rtDW.dbgCAN_dbg_Sen_Amb_model.dbg_Amb_Tg_ro = 0; + + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreWrite: '/Data Store Write' + * SignalConversion generated from: '/Vector Concatenate' + * SignalConversion generated from: '/Vector Concatenate' + * SignalConversion generated from: '/Vector Concatenate' + * SignalConversion generated from: '/Vector Concatenate' + * */ + rtDW.dbg_Auto_AF_model.dbg_Auto_AF_MultMsg_Idx = 0U; + rtDW.dbg_Auto_AF_model.dbg_Auto_AF_Correct_FL = 0; + rtDW.dbg_Auto_AF_model.dbg_Auto_AF_Correct_FR = 0; + rtDW.dbg_Auto_AF_model.dbg_Auto_AF_Correct_RL = 0; + rtDW.dbg_Auto_AF_model.dbg_Auto_AF_Correct_RR = 0; + rtDW.dbg_Auto_AF_model.dbg_Auto_AF_Vtg_RL = rtb_MultiportSwitch_ev; + rtDW.dbg_Auto_AF_model.dbg_Auto_AF_Vtg_FL = rtb_Bias_ct; + rtDW.dbg_Auto_AF_model.dbg_Auto_AF_Vtg_FR = rtb_MultiportSwitch1_g; + rtDW.dbg_Auto_AF_model.dbg_Auto_AF_Vtg_RR = rtb_MultiportSwitch_gq; + rtDW.dbg_Auto_AF_model.dbg_Auto_AF_Incar_RL = rtb_u5FRU_tg_incar; + rtDW.dbg_Auto_AF_model.dbg_Auto_AF_Incar_FR = rtb_u5FLU_tg_incar_i; + rtDW.dbg_Auto_AF_model.dbg_Auto_AF_Incar_RR = rtb_MultiportSwitch_ci; + rtDW.dbg_Auto_AF_model.dbg_Auto_AF_Incar_FL = rtb_Bias4; + rtDW.dbg_Auto_AF_model.dbg_Auto_AF_Amb_RL = rtb_u6FRU_tg_amb_f; + rtDW.dbg_Auto_AF_model.dbg_Auto_AF_Amb_FR = rtb_u6FLU_tg_amb_g; + rtDW.dbg_Auto_AF_model.dbg_Auto_AF_Sun_RR = rtb_MultiportSwitch_ci; + rtDW.dbg_Auto_AF_model.dbg_Auto_AF_Amb_FL = rtb_Bias2_n; + rtDW.dbg_Auto_AF_model.dbg_Auto_AF_Sun_FR = rtb_u6FLU_tg_amb_a3; + rtDW.dbg_Auto_AF_model.dbg_Auto_AF_Sun_RL = rtb_u6FRU_tg_amb; + rtDW.dbg_Auto_AF_model.dbg_Auto_AF_Amb_RR = rtb_X; + rtDW.dbg_Auto_AF_model.dbg_Auto_AF_Sun_FL = rtb_Bias3; + + /* BusCreator: '/Bus Creator' incorporates: + * Bias: '/Bias1' + * Bias: '/Bias3' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read11' + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read3' + * DataStoreRead: '/Data Store Read4' + * DataStoreRead: '/Data Store Read5' + * DataStoreRead: '/Data Store Read6' + * DataStoreRead: '/Data Store Read9' + * DataStoreWrite: '/Data Store Write' + * DataStoreWrite: '/Data Store Write' + * DataStoreWrite: '/Data Store Write' + * SignalConversion generated from: '/Vector Concatenate' + * SignalConversion generated from: '/Vector Concatenate' + * */ + rtDW.dbg_Auto_Duct_model.dbg_Auto_Duct_MultMsg_Idx = 0U; + rtDW.dbg_Auto_Duct_model.dbg_Auto_Duct_Tgt_FL_Upper_ro = rtb_Merge_b; + rtDW.dbg_Auto_Duct_model.dbg_Auto_Duct_Tg_Incar_FL_Upper_ro = (int16_t) + (rtb_MultiportSwitch_j2 - 200); + rtDW.dbg_Auto_Duct_model.dbg_Auto_Duct_Tgt_RR_ro = rtDW.Duct_RR_Tg; + rtDW.dbg_Auto_Duct_model.dbg_Auto_Duct_Tgt_RL_ro = rtb_y_jh; + rtDW.dbg_Auto_Duct_model.dbg_Auto_Duct_Tgt_FR_Upper_ro = rtb_FLU_tg_correct1; + rtDW.dbg_Auto_Duct_model.dbg_Auto_Duct_Tgt_FR_Lower_ro = rtb_y_he; + rtDW.dbg_Auto_Duct_model.dbg_Auto_Duct_Tgt_FL_Lower_ro = rtb_y_ki; + rtDW.dbg_Auto_Duct_model.dbg_Auto_Duct_Tg_Incar_FR_Upper_ro = (int16_t) + (rtb_VectorConcatenate_kz[4] - 200); + rtDW.dbg_Auto_Duct_model.dbg_Auto_Duct_Tg_FL_Upper_ro = rtb_MultiportSwitch_gp; + rtDW.dbg_Auto_Duct_model.dbg_Auto_Duct_Tg_FL_Lower_ro = Duct_FRU_Tg_DBG[0]; + rtDW.dbg_Auto_Duct_model.dbg_Auto_Duct_Tg_FR_Lower_ro = + rtb_VectorConcatenate_by[0]; + rtDW.dbg_Auto_Duct_model.dbg_Auto_Duct_Tg_FR_Upper_ro = + rtb_VectorConcatenate_kz[0]; + rtDW.dbg_Auto_Duct_model.dbg_Auto_Duct_Tg_RL_ro = rtb_MultiportSwitch_d; + rtDW.dbg_Auto_Duct_model.dbg_Auto_Duct_Tg_RR_ro = Duct_RR_Tg_DBG[0]; + rtDW.dbg_Auto_Duct_model.dbg_Auto_Duct_Tg_Incar_FL_Lower_ro = (int16_t) + (Duct_FRU_Tg_DBG[4] - 200); + rtDW.dbg_Auto_Duct_model.dbg_Auto_Duct_Incar_FL_Lower_ro = Duct_FRU_Tg_DBG[1]; + rtDW.dbg_Auto_Duct_model.dbg_Auto_Duct_Incar_RR_ro = Duct_RR_Tg_DBG[1]; + rtDW.dbg_Auto_Duct_model.dbg_Auto_Duct_Incar_RL_ro = rtb_u5R_tg_incar; + rtDW.dbg_Auto_Duct_model.dbg_Auto_Duct_Incar_FR_Upper_ro = + rtb_VectorConcatenate_kz[1]; + rtDW.dbg_Auto_Duct_model.dbg_Auto_Duct_Incar_FR_Lower_ro = + rtb_VectorConcatenate_by[1]; + rtDW.dbg_Auto_Duct_model.dbg_Auto_Duct_Incar_FL_Upper_ro = + rtb_u5FLU_tg_incar_b; + rtDW.dbg_Auto_Duct_model.dbg_Auto_Duct_Tg_Incar_FR_Lower_ro = (int16_t) + (rtb_VectorConcatenate_by[4] - 200); + rtDW.dbg_Auto_Duct_model.dbg_Auto_Duct_Amb_RL_ro = rtb_u6FLU_tg_amb_d; + rtDW.dbg_Auto_Duct_model.dbg_Auto_Duct_Amb_FR_Upper_ro = + rtb_VectorConcatenate_kz[2]; + rtDW.dbg_Auto_Duct_model.dbg_Auto_Duct_Amb_FR_Lower_ro = + rtb_VectorConcatenate_by[2]; + rtDW.dbg_Auto_Duct_model.dbg_Auto_Duct_Amb_RR_ro = Duct_RR_Tg_DBG[2]; + rtDW.dbg_Auto_Duct_model.dbg_Auto_Duct_Amb_FL_Lower_ro = Duct_FRU_Tg_DBG[2]; + rtDW.dbg_Auto_Duct_model.dbg_Auto_Duct_Amb_FL_Upper_ro = rtb_u6FLU_tg_amb_h; + rtDW.dbg_Auto_Duct_model.dbg_Auto_Duct_Tg_Incar_RL_ro = (int16_t) + (rtb_MultiportSwitch_oh - 200); + rtDW.dbg_Auto_Duct_model.dbg_Auto_Duct_Sun_FL_Lower_ro = Duct_FRU_Tg_DBG[3]; + rtDW.dbg_Auto_Duct_model.dbg_Auto_Duct_Sun_FR_Lower_ro = + rtb_VectorConcatenate_by[3]; + rtDW.dbg_Auto_Duct_model.dbg_Auto_Duct_Sun_FR_Upper_ro = + rtb_VectorConcatenate_kz[3]; + rtDW.dbg_Auto_Duct_model.dbg_Auto_Duct_Sun_RL_ro = rtb_u6FLU_tg_amb_n; + rtDW.dbg_Auto_Duct_model.dbg_Auto_Duct_Sun_FL_Upper_ro = rtb_u6FLU_tg_amb_o; + rtDW.dbg_Auto_Duct_model.dbg_Auto_Duct_Sun_RR_ro = Duct_RR_Tg_DBG[3]; + rtDW.dbg_Auto_Duct_model.dbg_Auto_Duct_Tg_Incar_RR_ro = (int16_t) + (Duct_RR_Tg_DBG[4] - 200); + + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read3' + * DataStoreRead: '/Data Store Read4' + * DataStoreRead: '/Data Store Read5' + * DataStoreRead: '/Data Store Read6' + * DataStoreRead: '/Data Store Read7' + * DataStoreRead: '/Data Store Read8' + * DataStoreRead: '/Data Store Read9' + * DataStoreWrite: '/Data Store Write' + * DataTypeConversion: '/Data Type Conversion' + * DataTypeConversion: '/Data Type Conversion1' + * DataTypeConversion: '/Data Type Conversion2' + * DataTypeConversion: '/Data Type Conversion3' + */ + rtDW.dbgCAN_dbg_Logic_Blower_model.Logic_Blower_Step_FL = rtDW.CCU_BLOWERS_FL; + rtDW.dbgCAN_dbg_Logic_Blower_model.Logic_Blower_Step_FR = rtDW.CCU_BLOWERS_FR; + rtDW.dbgCAN_dbg_Logic_Blower_model.Logic_Blower_Step_RL = rtDW.CCU_BLOWERS_RL; + rtDW.dbgCAN_dbg_Logic_Blower_model.Logic_Blower_Step_RR = rtDW.CCU_BLOWERS_RR; + rtDW.dbgCAN_dbg_Logic_Blower_model.Logic_Blower_Pwm_Front = rtDW.PWM_front; + rtDW.dbgCAN_dbg_Logic_Blower_model.Logic_Blower_Pwm_Rear = rtDW.PWM_rear; + rtDW.dbgCAN_dbg_Logic_Blower_model.Logic_Blower_AF_FL = (uint8_t)Gain; + rtDW.dbgCAN_dbg_Logic_Blower_model.Logic_Blower_AF_FR = (uint8_t)Gain1; + rtDW.dbgCAN_dbg_Logic_Blower_model.Logic_Blower_AF_RL = (uint8_t) + rtb_Saturation2_a; + rtDW.dbgCAN_dbg_Logic_Blower_model.Logic_Blower_AF_RR = (uint8_t)rtb_out_ew; + + /* BusCreator: '/Bus Creator' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read2' + * DataStoreWrite: '/Data Store Write' + */ + rtDW.dbgCAN_dbg_Sen_Eva_model.dbg_Sen_Eva_F = Eva_Target; + rtDW.dbgCAN_dbg_Sen_Eva_model.dbg_Sen_Eva_R = 0; + rtDW.dbgCAN_dbg_Sen_Eva_model.dbg_Sen_Eva_Target = rtDW.Eva_F; + rtDW.dbgCAN_dbg_Sen_Eva_model.dbg_Sen_Eva_Diff_FrontRear = rtDW.Eva_R; + + /* Outport: '/dtc_state_error_model' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + memcpy(&rtY.dtc_state_error_model[0], &rtDW.dtc_state_error_model[0], 127U * + sizeof(uint8_t)); + + /* Outport: '/dbgCAN_dbg_Act0_model' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + rtY.dbgCAN_dbg_Act0_model = rtDW.dbgCAN_dbg_Act0_model; + + /* Outport: '/dbgCAN_dbg_Act1_model' incorporates: + * DataStoreRead: '/Data Store Read4' + */ + rtY.dbgCAN_dbg_Act1_model = rtDW.dbgCAN_dbg_Act1_model; + + /* Outport: '/dbgCAN_dbg_Act2_model' incorporates: + * DataStoreRead: '/Data Store Read5' + */ + rtY.dbgCAN_dbg_Act2_model = rtDW.dbgCAN_dbg_Act2_model; + + /* Outport: '/dbgCAN_dbg_Sen_Duct_model' incorporates: + * DataStoreRead: '/Data Store Read8' + */ + rtY.dbgCAN_dbg_Sen_Duct_model = rtDW.dbgCAN_dbg_Sen_Duct_model; + + /* Outport: '/dbgCAN_dbg_Sen_Eva_model' incorporates: + * DataStoreRead: '/Data Store Read9' + */ + rtY.dbgCAN_dbg_Sen_Eva_model = rtDW.dbgCAN_dbg_Sen_Eva_model; + + /* Outport: '/dbgCAN_dbg_Logic_Blower_model' incorporates: + * DataStoreRead: '/Data Store Read13' + */ + rtY.dbgCAN_dbg_Logic_Blower_model = rtDW.dbgCAN_dbg_Logic_Blower_model; + + /* Outport: '/dbgCAN_dbg_Sen_Amb_model' incorporates: + * DataStoreRead: '/Data Store Read29' + */ + rtY.dbgCAN_dbg_Sen_Amb_model = rtDW.dbgCAN_dbg_Sen_Amb_model; + + /* Outport: '/dbgCAN_dbg_Sen_Incar_model' incorporates: + * DataStoreRead: '/Data Store Read48' + */ + rtY.dbgCAN_dbg_Sen_Incar_model = rtDW.dbgCAN_dbg_Sen_Incar_model; + + /* Outport: '/dbgCAN_dbg_Sen_0_model' incorporates: + * DataStoreRead: '/Data Store Read49' + */ + rtY.dbgCAN_dbg_Sen_0_model = rtDW.dbgCAN_dbg_Sen_0_model; + + /* Outport: '/PowerEnable_Model' incorporates: + * DataStoreRead: '/Data Store Read46' + */ + rtY.PowerEnable_Model = rtDW.PowerEnable_Model; + + /* Outport: '/dbg_Logic_Ac_model' incorporates: + * DataStoreRead: '/Data Store Read56' + */ + rtY.dbg_Logic_Ac_model = rtDW.dbg_Logic_Ac_model; + + /* Outport: '/dbgCAN_CCU_IO_model' incorporates: + * DataStoreRead: '/Data Store Read60' + */ + rtY.dbgCAN_CCU_IO_model = rtDW.dbgCAN_CCU_IO_model; + + /* Outport: '/dbgCAN_Logic_Rec_model' incorporates: + * DataStoreRead: '/Data Store Read38' + */ + rtY.dbgCAN_Logic_Rec_model = rtDW.dbgCAN_Logic_Rec_model; + + /* Outport: '/dbgCAN_Logic_State_model' incorporates: + * DataStoreRead: '/Data Store Read39' + */ + rtY.dbgCAN_Logic_State_model = rtDW.dbgCAN_Logic_State_model; + + /* Outport: '/dbgCAN_Auto_Duct_model' incorporates: + * DataStoreRead: '/Data Store Read62' + */ + rtY.dbgCAN_Auto_Duct_model = rtDW.dbg_Auto_Duct_model; + + /* Outport: '/dbgCAN_Auto_AF_model' incorporates: + * DataStoreRead: '/Data Store Read63' + */ + rtY.dbgCAN_Auto_AF_model = rtDW.dbg_Auto_AF_model; + + /* Outport: '/LIN4_CCU_Req_Model' incorporates: + * DataStoreRead: '/Data Store Read64' + */ + rtY.LIN4_CCU_Req_Model = rtDW.LIN4_CCU_Req_Model; + + /* Outport: '/dbg_Logic_Valve_model' incorporates: + * DataStoreRead: '/Data Store Read65' + */ + rtY.dbg_Logic_Valve_model = rtDW.dbg_Logic_Valve_model; + + /* Outport: '/dbg_LIN_AirQS_Stat_t_model' incorporates: + * DataStoreRead: '/Data Store Read70' + */ + rtY.dbg_LIN_AirQS_Stat_t_model = rtDW.dbg_LIN_AirQS_Stat_t_model; + + /* Outport: '/dbg_LIN_DRS_Stat_t_model' incorporates: + * DataStoreRead: '/Data Store Read71' + */ + rtY.dbg_LIN_DRS_Stat_t_model = rtDW.dbg_LIN_DRS_Stat_t_model; + + /* Outport: '/dbg_Drs_t_model' incorporates: + * DataStoreRead: '/Data Store Read72' + */ + rtY.dbg_Drs_t_model = rtDW.dbg_Drs_t_model; + + /* Outport: '/dbg_Logic_Valve_Plus_model' incorporates: + * DataStoreRead: '/Data Store Read69' + */ + rtY.dbg_Logic_Valve_Plus_model = rtDW.dbg_Logic_Valve_Plus_model; + + /* Outport: '/dbg_LIN_Aroma_Stat_t_model' incorporates: + * DataStoreRead: '/Data Store Read85' + */ + rtY.dbg_LIN_Aroma_Stat_t_model = rtDW.dbg_LIN_Aroma_Stat_t_model; + + /* Outport: '/dbg_LIN_Ionizer_Stat_t_model' incorporates: + * DataStoreRead: '/Data Store Read86' + */ + rtY.dbg_LIN_Ionizer_Stat_t_model = rtDW.dbg_LIN_Ionizer_Stat_t_model; + + /* Outport: '/Status_Duct_Select_model_IO' incorporates: + * DataStoreRead: '/Data Store Read96' + */ + rtY.Status_Duct_Select_model_IO = rtDW.Status_Duct_Select_model_IO; + + /* Outport: '/Status_Eva_Tgt_model_IO' incorporates: + * DataStoreRead: '/Data Store Read97' + */ + rtY.Status_Eva_Tgt_model_IO = rtDW.Status_Eva_Tgt_model_IO; + + /* Outport: '/Status_Sensort_model_IO' incorporates: + * DataStoreRead: '/Data Store Read98' + */ + rtY.Status_Sensort_model_IO = rtDW.Status_Sensor_model_IO; + + /* Outport: '/Status_Actuator_model_IO' incorporates: + * DataStoreRead: '/Data Store Read99' + */ + rtY.Status_Actuator_model_IO = rtDW.Status_Actuator_model_IO; + + /* Outport: '/Status_Duct_Tgt_model_IO' incorporates: + * DataStoreRead: '/Data Store Read100' + */ + rtY.Status_Duct_Tgt_model_IO = rtDW.Status_Duct_Tgt_model_IO; + + /* Saturate: '/from 0 to 3' incorporates: + * Constant: '/Constant' + * Sum: '/Add' + * UnitDelay: '/Unit Delay' + */ + if (rtDW.UnitDelay_DSTATE + 1.0 > 3.0) { + rtDW.UnitDelay_DSTATE = 3.0; + } else if (rtDW.UnitDelay_DSTATE + 1.0 < 0.0) { + rtDW.UnitDelay_DSTATE = 0.0; + } else { + rtDW.UnitDelay_DSTATE++; + } + + /* End of Saturate: '/from 0 to 3' */ + + /* If: '/ SC front 2' incorporates: + * DataStoreRead: '/Data Store Read1' + * DataTypeConversion: '/Data Type Conversion' + * DataTypeConversion: '/Data Type Conversion2' + * UnitDelay: '/Unit Delay' + */ + if (((uint8_t)rtDW.start_control_finished_front == 0) && ((uint8_t) + rtDW.UnitDelay_DSTATE >= 3)) { + /* Outputs for IfAction SubSystem: '/Start Control Front' incorporates: + * ActionPort: '/Action Port' + */ + /* SwitchCase: '/Switch Case' incorporates: + * DataStoreRead: '/Data Store Read' + */ + switch (rtDW.step_start_controle_front) { + case -1: + /* Outputs for IfAction SubSystem: '/Step -1 F (Entry Condition)' incorporates: + * ActionPort: '/Action Port' + */ + /* SwitchCase: '/Switch Case' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + switch (rtDW.LEVEL) { + case 0: + /* Outputs for IfAction SubSystem: '/Level 0' incorporates: + * ActionPort: '/Action Port' + */ + /* MATLAB Function: '/g_assSTART_ENTER_INCAR' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + g_assSTART_ENTER_INCAR_n(rtDW.LEVEL, &rtb_FLU_tg_correct); + + /* MATLAB Function: '/g_ausSTART_ENTER_SETTEMP' incorporates: + * DataStoreRead: '/Data Store Read4' + */ + /* : out = g_ausSTART_ENTER_SETTEMP(LVL+1); */ + i = (int32_t)(rtDW.LEVEL + 1U); + if (rtDW.LEVEL + 1U > 255U) { + i = 255; + } + + /* Switch: '/Switch' incorporates: + * Constant: '/not LO or HI' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read5' + * Logic: '/AND' + * MATLAB Function: '/g_ausSTART_ENTER_SETTEMP' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator1' + * RelationalOperator: '/Relational Operator2' + * RelationalOperator: '/Relational Operator3' + */ + if ((rtDW.Incar_FL > rtb_FLU_tg_correct) && (rtDW.CCU_MODE_FL == 1) && + (rtDW.CCU_SET_FL < g_ausSTART_ENTER_SETTEMP[i - 1]) && + (rtDW.LO_HI_MODE_FL == 0)) { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant1' + */ + rtB.Merge_pe = 1; + } else { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant' + */ + rtB.Merge_pe = -1; + } + + /* End of Switch: '/Switch' */ + /* End of Outputs for SubSystem: '/Level 0' */ + break; + + case 1: + /* Outputs for IfAction SubSystem: '/Level 1' incorporates: + * ActionPort: '/Action Port' + */ + /* MATLAB Function: '/g_assSTART_ENTER_INCAR' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + g_assSTART_ENTER_INCAR_n(rtDW.LEVEL, &rtb_FLU_tg_correct); + + /* MATLAB Function: '/g_ausSTART_ENTER_SETTEMP' incorporates: + * DataStoreRead: '/Data Store Read4' + */ + /* : out = int16(g_ausSTART_ENTER_SETTEMP(LVL+1)); */ + i = (int32_t)(rtDW.LEVEL + 1U); + if (rtDW.LEVEL + 1U > 255U) { + i = 255; + } + + rtb_out_h0 = g_ausSTART_ENTER_SETTEMP[i - 1]; + if (rtb_out_h0 > 32767) { + rtb_out_h0 = 32767U; + } + + /* Switch: '/Switch' incorporates: + * Constant: '/not LO or HI' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read5' + * Logic: '/AND' + * MATLAB Function: '/g_ausSTART_ENTER_SETTEMP' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator1' + * RelationalOperator: '/Relational Operator2' + * RelationalOperator: '/Relational Operator3' + */ + if ((rtDW.Incar_FL > rtb_FLU_tg_correct) && (rtDW.CCU_MODE_FL == 1) && + (rtDW.CCU_SET_FL < rtb_out_h0) && (rtDW.LO_HI_MODE_FL == 0)) { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant1' + */ + rtB.Merge_pe = 1; + } else { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant' + */ + rtB.Merge_pe = -1; + } + + /* End of Switch: '/Switch' */ + /* End of Outputs for SubSystem: '/Level 1' */ + break; + + case 2: + /* Outputs for IfAction SubSystem: '/Level 2' incorporates: + * ActionPort: '/Action Port' + */ + Level2(&rtB.Merge_pe); + + /* End of Outputs for SubSystem: '/Level 2' */ + break; + + case 3: + /* Outputs for IfAction SubSystem: '/Level 3' incorporates: + * ActionPort: '/Action Port' + */ + /* MATLAB Function: '/g_assSTART_ENTER_COOLANT ' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + g_assSTART_ENTER_COOLANT_m(rtDW.LEVEL, &rtb_FLU_tg_correct); + + /* Switch: '/Switch' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/mode driver' + * Logic: '/AND' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator2' + */ + if ((rtDW.ECT < rtb_FLU_tg_correct) && (rtDW.CCU_MODE_FL == 1)) { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant1' + */ + rtB.Merge_pe = 0; + } else { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant' + */ + rtB.Merge_pe = -1; + } + + /* End of Switch: '/Switch' */ + /* End of Outputs for SubSystem: '/Level 3' */ + break; + + case 4: + /* Outputs for IfAction SubSystem: '/Level 4' incorporates: + * ActionPort: '/Action Port' + */ + Level4(&rtB.Merge_pe, &rtDW.CCU_MODE_FL, &rtDW.ECT, &rtDW.LEVEL, + &rtDW.LO_HI_MODE_FL); + + /* End of Outputs for SubSystem: '/Level 4' */ + break; + + case 5: + /* Outputs for IfAction SubSystem: '/Level 5' incorporates: + * ActionPort: '/Action Port' + */ + Level4(&rtB.Merge_pe, &rtDW.CCU_MODE_FL, &rtDW.ECT, &rtDW.LEVEL, + &rtDW.LO_HI_MODE_FL); + + /* End of Outputs for SubSystem: '/Level 5' */ + break; + } + + /* End of SwitchCase: '/Switch Case' */ + /* End of Outputs for SubSystem: '/Step -1 F (Entry Condition)' */ + break; + + case 0: + /* Outputs for IfAction SubSystem: '/Step 0 F' incorporates: + * ActionPort: '/Action Port' + */ + /* SwitchCase: '/Switch Case' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + switch (rtDW.LEVEL) { + case 0: + /* Outputs for IfAction SubSystem: '/Level 0' incorporates: + * ActionPort: '/Action Port' + */ + Level0(&rtB.Merge_pe); + + /* End of Outputs for SubSystem: '/Level 0' */ + break; + + case 1: + /* Outputs for IfAction SubSystem: '/Level 1' incorporates: + * ActionPort: '/Action Port' + */ + Level0(&rtB.Merge_pe); + + /* End of Outputs for SubSystem: '/Level 1' */ + break; + + case 2: + /* Outputs for IfAction SubSystem: '/Level 2' incorporates: + * ActionPort: '/Action Port' + */ + Level0(&rtB.Merge_pe); + + /* End of Outputs for SubSystem: '/Level 2' */ + break; + + case 3: + /* Outputs for IfAction SubSystem: '/Level 3' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write5' incorporates: + * Constant: '/Constant2' + */ + rtDW.Blower_FR = 20U; + + /* DataStoreWrite: '/Data Store Write6' incorporates: + * Constant: '/Constant3' + */ + rtDW.Blower_FL = 20U; + + /* DataStoreWrite: '/Data Store Write10' incorporates: + * Constant: '/Constant4' + */ + rtDW.Dtg_FUR = 600U; + + /* DataStoreWrite: '/Data Store Write11' incorporates: + * Constant: '/Constant4' + */ + rtDW.Dtg_FUL = 600U; + + /* DataStoreWrite: '/Data Store Write12' incorporates: + * Constant: '/Constant6' + */ + rtDW.Dtg_FLR = 800U; + + /* DataStoreWrite: '/Data Store Write13' incorporates: + * Constant: '/Constant6' + */ + rtDW.Dtg_FLL = 800U; + + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataStoreRead: '/Data Store Read1' + * MATLAB Function: '/incar filter up' + */ + incarfilterup(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataStoreRead: '/Data Store Read2' + * MATLAB Function: '/incar filter down' + */ + incarfilterdown(rtDW.LEVEL, &EN_BATTChiller); + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/Mode - def' + */ + rtDW.Mode_FR = 80U; + + /* DataStoreWrite: '/Data Store Write3' incorporates: + * Constant: '/Mode - def' + */ + rtDW.Mode_FL = 80U; + + /* DataStoreWrite: '/Data Store Write7' incorporates: + * Constant: '/Recirc logic Partial REC' + */ + rtb_Add_be = 1.0; + + /* DataStoreWrite: '/Data Store Write8' incorporates: + * Constant: '/Valve open' + */ + ShutOffFront_EN = 1U; + + /* DataStoreWrite: '/Data Store Write9' incorporates: + * Constant: '/Valve open' + */ + ShutOffRear_EN = 1U; + + /* Switch: '/Switch1' incorporates: + * Constant: '/LO' + * DataStoreRead: '/Data Store Read11' + * DataStoreRead: '/Data Store Read12' + * Logic: '/Logical Operator1' + * RelationalOperator: '/Relational Operator2' + * RelationalOperator: '/Relational Operator3' + */ + /* : out = int16(g_assSTART_COOLANT_STEP0_TO_1(LVL + 1 - 2)); */ + if ((rtDW.CCU_MODE_FL != 1) || (rtDW.LO_HI_MODE_FL == 1)) { + /* Merge: '/Merge' incorporates: + * Constant: '/exit algorithm' + */ + rtB.Merge_pe = 3; + } else { + /* MATLAB Function: '/g_assSTART_COOLANT_STEP0_TO_1 ' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + i = (int32_t)(rtDW.LEVEL + 1U); + if (rtDW.LEVEL + 1U > 255U) { + i = 255; + } + + rtb_Subtract = (uint32_t)i - 2U; + if ((uint32_t)i - 2U > (uint32_t)i) { + rtb_Subtract = 0U; + } + + /* Merge: '/Merge' incorporates: + * DataStoreRead: '/Engine coolant temp' + * MATLAB Function: '/g_assSTART_COOLANT_STEP0_TO_1 ' + * RelationalOperator: '/Relational Operator' + */ + rtB.Merge_pe = (int8_t)(rtDW.ECT > g_assSTART_COOLANT_STEP0_TO_1 + [(int32_t)rtb_Subtract - 1]); + } + + /* End of Switch: '/Switch1' */ + /* End of Outputs for SubSystem: '/Level 3' */ + break; + + case 4: + /* Outputs for IfAction SubSystem: '/Level 4' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write5' incorporates: + * Constant: '/Constant2' + */ + rtDW.Blower_FR = 20U; + + /* DataStoreWrite: '/Data Store Write6' incorporates: + * Constant: '/Constant3' + */ + rtDW.Blower_FL = 20U; + + /* DataStoreWrite: '/Data Store Write10' incorporates: + * Constant: '/Constant4' + */ + rtDW.Dtg_FUR = 600U; + + /* DataStoreWrite: '/Data Store Write11' incorporates: + * Constant: '/Constant4' + */ + rtDW.Dtg_FUL = 600U; + + /* DataStoreWrite: '/Data Store Write12' incorporates: + * Constant: '/Constant6' + */ + rtDW.Dtg_FLR = 800U; + + /* DataStoreWrite: '/Data Store Write13' incorporates: + * Constant: '/Constant6' + */ + rtDW.Dtg_FLL = 800U; + + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataStoreRead: '/Data Store Read1' + * MATLAB Function: '/incar filter up' + */ + incarfilterup(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataStoreRead: '/Data Store Read2' + * MATLAB Function: '/incar filter down' + */ + incarfilterdown(rtDW.LEVEL, &EN_BATTChiller); + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/Mode - def' + */ + rtDW.Mode_FR = 80U; + + /* DataStoreWrite: '/Data Store Write3' incorporates: + * Constant: '/Mode - def' + */ + rtDW.Mode_FL = 80U; + + /* DataStoreWrite: '/Data Store Write7' incorporates: + * Constant: '/Recirc logic Partial REC' + */ + rtb_Add_be = 1.0; + + /* DataStoreWrite: '/Data Store Write8' incorporates: + * Constant: '/Valve open' + */ + ShutOffFront_EN = 1U; + + /* DataStoreWrite: '/Data Store Write9' incorporates: + * Constant: '/Valve open' + */ + ShutOffRear_EN = 1U; + + /* MATLAB Function: '/g_assSTART_COOLANT_STEP0_TO_1 ' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + g_assSTART_COOLANT_STEP0_TO_1_c(rtDW.LEVEL, &rtb_FLU_tg_correct); + + /* Switch: '/Switch1' incorporates: + * Constant: '/LO' + * DataStoreRead: '/Data Store Read11' + * DataStoreRead: '/Data Store Read12' + * Logic: '/Logical Operator1' + * RelationalOperator: '/Relational Operator2' + * RelationalOperator: '/Relational Operator3' + */ + if ((rtDW.CCU_MODE_FL != 1) || (rtDW.LO_HI_MODE_FL == 1)) { + /* Merge: '/Merge' incorporates: + * Constant: '/exit algorithm' + */ + rtB.Merge_pe = 3; + } else { + /* Merge: '/Merge' incorporates: + * DataStoreRead: '/Engine coolant temp' + * RelationalOperator: '/Relational Operator' + */ + rtB.Merge_pe = (int8_t)(rtDW.ECT > rtb_FLU_tg_correct); + } + + /* End of Switch: '/Switch1' */ + /* End of Outputs for SubSystem: '/Level 4' */ + break; + + case 5: + /* Outputs for IfAction SubSystem: '/Level 5' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write5' incorporates: + * Constant: '/Constant2' + */ + rtDW.Blower_FR = 20U; + + /* DataStoreWrite: '/Data Store Write6' incorporates: + * Constant: '/Constant3' + */ + rtDW.Blower_FL = 20U; + + /* DataStoreWrite: '/Data Store Write10' incorporates: + * Constant: '/Constant4' + */ + rtDW.Dtg_FUR = 800U; + + /* DataStoreWrite: '/Data Store Write11' incorporates: + * Constant: '/Constant4' + */ + rtDW.Dtg_FUL = 800U; + + /* DataStoreWrite: '/Data Store Write12' incorporates: + * Constant: '/Constant6' + */ + rtDW.Dtg_FLR = 800U; + + /* DataStoreWrite: '/Data Store Write13' incorporates: + * Constant: '/Constant6' + */ + rtDW.Dtg_FLL = 800U; + + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataStoreRead: '/Data Store Read1' + * MATLAB Function: '/incar filter up' + */ + incarfilterup(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataStoreRead: '/Data Store Read2' + * MATLAB Function: '/incar filter down' + */ + incarfilterdown(rtDW.LEVEL, &EN_BATTChiller); + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/Mode - def' + */ + rtDW.Mode_FR = 80U; + + /* DataStoreWrite: '/Data Store Write3' incorporates: + * Constant: '/Mode - def' + */ + rtDW.Mode_FL = 80U; + + /* DataStoreWrite: '/Data Store Write7' incorporates: + * Constant: '/Recirc logic Partial REC' + */ + rtb_Add_be = 1.0; + + /* DataStoreWrite: '/Data Store Write8' incorporates: + * Constant: '/Valve open' + */ + ShutOffFront_EN = 1U; + + /* DataStoreWrite: '/Data Store Write9' incorporates: + * Constant: '/Valve open' + */ + ShutOffRear_EN = 1U; + + /* MATLAB Function: '/g_assSTART_COOLANT_STEP0_TO_1 ' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + g_assSTART_COOLANT_STEP0_TO_1_c(rtDW.LEVEL, &rtb_FLU_tg_correct); + + /* Switch: '/Switch1' incorporates: + * Constant: '/LO' + * DataStoreRead: '/Data Store Read11' + * DataStoreRead: '/Data Store Read12' + * Logic: '/Logical Operator1' + * RelationalOperator: '/Relational Operator2' + * RelationalOperator: '/Relational Operator3' + */ + if ((rtDW.CCU_MODE_FL != 1) || (rtDW.LO_HI_MODE_FL == 1)) { + /* Merge: '/Merge' incorporates: + * Constant: '/exit algorithm' + */ + rtB.Merge_pe = 3; + } else { + /* Merge: '/Merge' incorporates: + * DataStoreRead: '/Engine coolant temp' + * RelationalOperator: '/Relational Operator' + */ + rtB.Merge_pe = (int8_t)(rtDW.ECT > rtb_FLU_tg_correct); + } + + /* End of Switch: '/Switch1' */ + /* End of Outputs for SubSystem: '/Level 5' */ + break; + } + + /* End of SwitchCase: '/Switch Case' */ + /* End of Outputs for SubSystem: '/Step 0 F' */ + break; + + case 1: + /* Outputs for IfAction SubSystem: '/Step 1 F' incorporates: + * ActionPort: '/Action Port' + */ + /* SwitchCase: '/Switch Case' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + switch (rtDW.LEVEL) { + case 0: + /* Outputs for IfAction SubSystem: '/Level 0' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write8' incorporates: + * DataStoreRead: '/Data Store Read10' + * MATLAB Function: '/3 way valve status' + */ + uwayvalvestatus(rtDW.LEVEL, &ShutOffFront_EN); + + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataStoreRead: '/Data Store Read1' + * MATLAB Function: '/incar filter up' + */ + incarfilterup(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataStoreRead: '/Data Store Read2' + * MATLAB Function: '/incar filter down' + */ + incarfilterdown(rtDW.LEVEL, &EN_BATTChiller); + + /* MATLAB Function: '/mode FR step 1' incorporates: + * DataStoreRead: '/Data Store Read5' + */ + modeFRstep1(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* DataStoreWrite: '/Data Store Write2' */ + rtDW.Mode_FR = Comp_Max_RPM_Allowed; + + /* DataStoreWrite: '/Data Store Write3' */ + rtDW.Mode_FL = Comp_Max_RPM_Allowed; + + /* MATLAB Function: '/window heating' incorporates: + * DataStoreRead: '/Data Store Read6' + */ + windowheating(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* MATLAB Function: '/blower FR' incorporates: + * DataStoreRead: '/Data Store Read7' + */ + blowerFR(rtDW.LEVEL, &Gain); + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * DataStoreWrite: '/Data Store Write5' + */ + rtDW.Blower_FR = (uint8_t)Gain; + + /* DataStoreWrite: '/Data Store Write6' incorporates: + * DataStoreWrite: '/Data Store Write5' + */ + rtDW.Blower_FL = rtDW.Blower_FR; + + /* MATLAB Function: '/Dtg_FrontUpper_X' incorporates: + * DataStoreRead: '/Data Store Read8' + */ + Dtg_FrontUpper_X(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* Gain: '/Gain' incorporates: + * DataStoreWrite: '/Data Store Write10' + */ + rtDW.Dtg_FUR = (uint16_t)(10U * Comp_Max_RPM_Allowed); + + /* DataStoreWrite: '/Data Store Write11' incorporates: + * DataStoreWrite: '/Data Store Write10' + */ + rtDW.Dtg_FUL = rtDW.Dtg_FUR; + + /* MATLAB Function: '/Dtg_FrontLower_X' incorporates: + * DataStoreRead: '/Data Store Read9' + */ + Dtg_FrontLower_X(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* Gain: '/Gain1' incorporates: + * DataStoreWrite: '/Data Store Write12' + */ + rtDW.Dtg_FLR = (uint16_t)(10U * Comp_Max_RPM_Allowed); + + /* DataStoreWrite: '/Data Store Write13' incorporates: + * DataStoreWrite: '/Data Store Write12' + */ + rtDW.Dtg_FLL = rtDW.Dtg_FLR; + + /* DataStoreWrite: '/Data Store Write7' incorporates: + * Constant: '/Recirc logic Partial REC' + */ + rtb_Add_be = 1.0; + + /* MATLAB Function: '/Incar temp goto from step 1 to step 2 ' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + Incartempgotofromstep1tostep2(rtDW.LEVEL, &rtb_FLU_tg_correct); + + /* MATLAB Function: '/Time goto from step 1 to step 2 ' incorporates: + * DataStoreRead: '/Data Store Read4' + */ + /* : out = int16(g_ausSTART_TIME_STEP1_TO_2(LVL + 1)); */ + i = (int32_t)(rtDW.LEVEL + 1U); + if (rtDW.LEVEL + 1U > 255U) { + i = 255; + } + + rtb_out_h0 = g_ausSTART_TIME_STEP1_TO_2[i - 1]; + if (rtb_out_h0 > 32767) { + rtb_out_h0 = 32767U; + } + + /* MATLAB Function: '/MATLAB Function1' incorporates: + * DataStoreRead: '/Data Store Read13' + * Gain: '/ ' + * MATLAB Function: '/Time goto from step 1 to step 2 ' + */ + MATLABFunction1(rtDW.t_now, (uint16_t)(1000 * rtb_out_h0), &eComp_stop, + &rtDW.sf_MATLABFunction1_n); + + /* Switch: '/Switch1' incorporates: + * Constant: '/not LO or HI' + * DataStoreRead: '/Data Store Read11' + * DataStoreRead: '/Data Store Read12' + * DataStoreRead: '/incar temp' + * Logic: '/Logical Operator' + * Logic: '/Logical Operator1' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator2' + * RelationalOperator: '/Relational Operator3' + * Switch: '/Switch' + */ + if ((rtDW.CCU_MODE_FL != 1) || (rtDW.LO_HI_MODE_FL != 0)) { + /* Merge: '/Merge' incorporates: + * Constant: '/exit algorithm' + */ + rtB.Merge_pe = 3; + } else if ((rtDW.Incar_FL < rtb_FLU_tg_correct) || eComp_stop) { + /* Switch: '/Switch' incorporates: + * Constant: '/go to next step' + * Merge: '/Merge' + */ + rtB.Merge_pe = 2; + } else { + /* Merge: '/Merge' incorporates: + * Constant: '/stay at step 1' + * Switch: '/Switch' + */ + rtB.Merge_pe = 1; + } + + /* End of Switch: '/Switch1' */ + /* End of Outputs for SubSystem: '/Level 0' */ + break; + + case 1: + /* Outputs for IfAction SubSystem: '/Level 1' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write8' incorporates: + * DataStoreRead: '/Data Store Read10' + * MATLAB Function: '/3 way valve status' + */ + uwayvalvestatus(rtDW.LEVEL, &ShutOffFront_EN); + + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataStoreRead: '/Data Store Read1' + * MATLAB Function: '/incar filter up' + */ + incarfilterup(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataStoreRead: '/Data Store Read2' + * MATLAB Function: '/incar filter down' + */ + incarfilterdown(rtDW.LEVEL, &EN_BATTChiller); + + /* MATLAB Function: '/mode FR step 1' incorporates: + * DataStoreRead: '/Data Store Read5' + */ + modeFRstep1(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* DataStoreWrite: '/Data Store Write2' */ + rtDW.Mode_FR = Comp_Max_RPM_Allowed; + + /* DataStoreWrite: '/Data Store Write3' */ + rtDW.Mode_FL = Comp_Max_RPM_Allowed; + + /* MATLAB Function: '/window heating' incorporates: + * DataStoreRead: '/Data Store Read6' + */ + windowheating(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* MATLAB Function: '/blower FR' incorporates: + * DataStoreRead: '/Data Store Read7' + */ + blowerFR(rtDW.LEVEL, &Gain); + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * DataStoreWrite: '/Data Store Write5' + */ + rtDW.Blower_FR = (uint8_t)Gain; + + /* DataStoreWrite: '/Data Store Write6' incorporates: + * DataStoreWrite: '/Data Store Write5' + */ + rtDW.Blower_FL = rtDW.Blower_FR; + + /* MATLAB Function: '/Dtg_FrontUpper_X' incorporates: + * DataStoreRead: '/Data Store Read8' + */ + Dtg_FrontUpper_X(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* Gain: '/Gain1' incorporates: + * DataStoreWrite: '/Data Store Write10' + */ + rtDW.Dtg_FUR = (uint16_t)(10U * Comp_Max_RPM_Allowed); + + /* DataStoreWrite: '/Data Store Write11' incorporates: + * DataStoreWrite: '/Data Store Write10' + */ + rtDW.Dtg_FUL = rtDW.Dtg_FUR; + + /* MATLAB Function: '/Dtg_FrontLower_X' incorporates: + * DataStoreRead: '/Data Store Read9' + */ + Dtg_FrontLower_X(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* Gain: '/Gain2' incorporates: + * DataStoreWrite: '/Data Store Write12' + */ + rtDW.Dtg_FLR = (uint16_t)(10U * Comp_Max_RPM_Allowed); + + /* DataStoreWrite: '/Data Store Write13' incorporates: + * DataStoreWrite: '/Data Store Write12' + */ + rtDW.Dtg_FLL = rtDW.Dtg_FLR; + + /* DataStoreWrite: '/Data Store Write7' incorporates: + * Constant: '/Recirc logic Partial REC' + */ + rtb_Add_be = 1.0; + + /* MATLAB Function: '/Incar temp goto from step 1 to step 2 ' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + Incartempgotofromstep1tostep2(rtDW.LEVEL, &rtb_FLU_tg_correct); + + /* MATLAB Function: '/Time goto from step 1 to step 2 ' incorporates: + * DataStoreRead: '/Data Store Read4' + */ + Timegotofromstep1tostep2(rtDW.LEVEL, &Eva_Target); + + /* MATLAB Function: '/MATLAB Function1' incorporates: + * DataStoreRead: '/Data Store Read13' + * Gain: '/ ' + */ + MATLABFunction1_j(rtDW.t_now, (uint32_t)(1000 * Eva_Target), &eComp_stop, + &rtDW.sf_MATLABFunction1_j); + + /* Switch: '/Switch1' incorporates: + * Constant: '/not LO or HI' + * DataStoreRead: '/Data Store Read11' + * DataStoreRead: '/Data Store Read12' + * DataStoreRead: '/incar temp' + * Logic: '/Logical Operator' + * Logic: '/Logical Operator1' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator2' + * RelationalOperator: '/Relational Operator3' + * Switch: '/Switch' + */ + if ((rtDW.CCU_MODE_FL != 1) || (rtDW.LO_HI_MODE_FL != 0)) { + /* Merge: '/Merge' incorporates: + * Constant: '/exit algorithm' + */ + rtB.Merge_pe = 3; + } else if ((rtDW.Incar_FL < rtb_FLU_tg_correct) || eComp_stop) { + /* Switch: '/Switch' incorporates: + * Constant: '/go to next step' + * Merge: '/Merge' + */ + rtB.Merge_pe = 2; + } else { + /* Merge: '/Merge' incorporates: + * Constant: '/stay at step 1' + * Switch: '/Switch' + */ + rtB.Merge_pe = 1; + } + + /* End of Switch: '/Switch1' */ + /* End of Outputs for SubSystem: '/Level 1' */ + break; + + case 2: + /* Outputs for IfAction SubSystem: '/Level 2' incorporates: + * ActionPort: '/Action Port' + */ + /* Merge: '/Merge' incorporates: + * Constant: '/Constant' + * SignalConversion generated from: '/step' + */ + rtB.Merge_pe = 2; + + /* End of Outputs for SubSystem: '/Level 2' */ + break; + + case 3: + /* Outputs for IfAction SubSystem: '/Level 3' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write8' incorporates: + * DataStoreRead: '/Data Store Read11' + * MATLAB Function: '/3 way valve status' + */ + uwayvalvestatus(rtDW.LEVEL, &ShutOffFront_EN); + + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataStoreRead: '/Data Store Read1' + * MATLAB Function: '/incar filter up' + */ + incarfilterup(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataStoreRead: '/Data Store Read2' + * MATLAB Function: '/incar filter down' + */ + incarfilterdown(rtDW.LEVEL, &EN_BATTChiller); + + /* MATLAB Function: '/mode FR step 1' incorporates: + * DataStoreRead: '/Data Store Read5' + */ + modeFRstep1(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* DataStoreWrite: '/Data Store Write2' */ + rtDW.Mode_FR = Comp_Max_RPM_Allowed; + + /* DataStoreWrite: '/Data Store Write3' */ + rtDW.Mode_FL = Comp_Max_RPM_Allowed; + + /* MATLAB Function: '/window heating' incorporates: + * DataStoreRead: '/Data Store Read6' + */ + windowheating(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* MATLAB Function: '/blower min max' incorporates: + * DataStoreRead: '/Data Store Read7' + */ + blowerminmax(rtDW.LEVEL, rtb_out_gx); + + /* MATLAB Function: '/ECT min max' incorporates: + * DataStoreRead: '/Data Store Read7' + */ + ECTminmax(rtDW.LEVEL, rtb_out_knd); + + /* Lookup_n-D: '/blower ECT' incorporates: + * DataStoreRead: '/engine coolant temp' + */ + rtb_FLU_tg_correct = look1_is16lu64n32tu16Ds32Is16_binlcs(rtDW.ECT, + rtb_out_knd, rtb_out_gx, 1U); + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * DataStoreWrite: '/Data Store Write5' + * DataTypeConversion: '/Data Type Conversion' + */ + rtDW.Blower_FR = (uint8_t)rtb_FLU_tg_correct; + + /* DataStoreWrite: '/Data Store Write6' incorporates: + * DataStoreWrite: '/Data Store Write5' + */ + rtDW.Blower_FL = rtDW.Blower_FR; + + /* MATLAB Function: '/Dtg_FrontUpper_X' incorporates: + * DataStoreRead: '/Data Store Read8' + */ + Dtg_FrontUpper_X(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* Gain: '/Gain1' incorporates: + * DataStoreWrite: '/Data Store Write10' + */ + rtDW.Dtg_FUR = (uint16_t)(10U * Comp_Max_RPM_Allowed); + + /* DataStoreWrite: '/Data Store Write11' incorporates: + * DataStoreWrite: '/Data Store Write10' + */ + rtDW.Dtg_FUL = rtDW.Dtg_FUR; + + /* MATLAB Function: '/Dtg_FrontLower_X' incorporates: + * DataStoreRead: '/Data Store Read9' + */ + Dtg_FrontLower_X(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* Gain: '/Gain2' incorporates: + * DataStoreWrite: '/Data Store Write12' + */ + rtDW.Dtg_FLR = (uint16_t)(10U * Comp_Max_RPM_Allowed); + + /* DataStoreWrite: '/Data Store Write13' incorporates: + * DataStoreWrite: '/Data Store Write12' + */ + rtDW.Dtg_FLL = rtDW.Dtg_FLR; + + /* DataStoreWrite: '/Data Store Write7' incorporates: + * Constant: '/Recirc logic Partial REC' + */ + rtb_Add_be = 1.0; + + /* MATLAB Function: '/Incar temp goto from step 1 to step 2 ' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + Incartempgotofromstep1tostep2(rtDW.LEVEL, &Eva_Target); + + /* MATLAB Function: '/Time goto from step 1 to step 2 ' incorporates: + * DataStoreRead: '/Data Store Read4' + */ + Timegotofromstep1tostep2(rtDW.LEVEL, &rtb_FLU_tg_correct); + + /* MATLAB Function: '/MATLAB Function1' incorporates: + * DataStoreRead: '/Data Store Read14' + * Gain: '/ ' + */ + MATLABFunction1_j(rtDW.t_now, (uint32_t)(1000 * rtb_FLU_tg_correct), + &eComp_stop, &rtDW.sf_MATLABFunction1_d); + + /* Switch: '/Switch1' incorporates: + * Constant: '/LO' + * DataStoreRead: '/Data Store Read12' + * DataStoreRead: '/Data Store Read13' + * Logic: '/Logical Operator1' + * RelationalOperator: '/Relational Operator3' + * RelationalOperator: '/Relational Operator4' + */ + /* : out = int16(g_assSTART_COOLANT_TO_STEP2(LVL + 1 - 3)); */ + if ((rtDW.CCU_MODE_FL != 1) || (rtDW.LO_HI_MODE_FL == 1)) { + /* Merge: '/Merge' incorporates: + * Constant: '/exit algorithm' + */ + rtB.Merge_pe = 3; + } else { + /* MATLAB Function: '/g_assSTART_COOLANT_TO_STEP2 ' incorporates: + * DataStoreRead: '/Data Store Read10' + */ + i = (int32_t)(rtDW.LEVEL + 1U); + if (rtDW.LEVEL + 1U > 255U) { + i = 255; + } + + rtb_Subtract = (uint32_t)i - 3U; + if ((uint32_t)i - 3U > (uint32_t)i) { + rtb_Subtract = 0U; + } + + /* Switch: '/Switch' incorporates: + * DataStoreRead: '/engine coolant temp' + * DataStoreRead: '/incar temp' + * Logic: '/Logical Operator' + * MATLAB Function: '/g_assSTART_COOLANT_TO_STEP2 ' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator2' + */ + if ((rtDW.Incar_FL < Eva_Target) || eComp_stop || (rtDW.ECT > + g_assSTART_COOLANT_TO_STEP2[(int32_t)rtb_Subtract - 1])) { + /* Merge: '/Merge' incorporates: + * Constant: '/go to next step 2' + */ + rtB.Merge_pe = 2; + } else { + /* Merge: '/Merge' incorporates: + * Constant: '/stay at step 1' + */ + rtB.Merge_pe = 1; + } + + /* End of Switch: '/Switch' */ + } + + /* End of Switch: '/Switch1' */ + /* End of Outputs for SubSystem: '/Level 3' */ + break; + + case 4: + /* Outputs for IfAction SubSystem: '/Level 4' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write8' incorporates: + * DataStoreRead: '/Data Store Read10' + * MATLAB Function: '/3 way valve status' + */ + uwayvalvestatus(rtDW.LEVEL, &ShutOffFront_EN); + + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataStoreRead: '/Data Store Read1' + * MATLAB Function: '/incar filter up' + */ + incarfilterup(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataStoreRead: '/Data Store Read2' + * MATLAB Function: '/incar filter down' + */ + incarfilterdown(rtDW.LEVEL, &EN_BATTChiller); + + /* MATLAB Function: '/mode FR step 1' incorporates: + * DataStoreRead: '/Data Store Read5' + */ + modeFRstep1(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* DataStoreWrite: '/Data Store Write2' */ + rtDW.Mode_FR = Comp_Max_RPM_Allowed; + + /* DataStoreWrite: '/Data Store Write3' */ + rtDW.Mode_FL = Comp_Max_RPM_Allowed; + + /* MATLAB Function: '/window heating' incorporates: + * DataStoreRead: '/Data Store Read6' + */ + windowheating(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* MATLAB Function: '/blower min max' incorporates: + * DataStoreRead: '/Data Store Read7' + */ + blowerminmax(rtDW.LEVEL, rtb_out_gx); + + /* MATLAB Function: '/ECT min max' incorporates: + * DataStoreRead: '/Data Store Read7' + */ + ECTminmax(rtDW.LEVEL, rtb_out_knd); + + /* Lookup_n-D: '/blower ECT' incorporates: + * DataStoreRead: '/engine coolant temp' + */ + rtb_FLU_tg_correct = look1_is16lu64n32tu16Ds32Is16_binlcs(rtDW.ECT, + rtb_out_knd, rtb_out_gx, 1U); + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * DataStoreWrite: '/Data Store Write5' + * DataTypeConversion: '/Data Type Conversion1' + */ + rtDW.Blower_FR = (uint8_t)rtb_FLU_tg_correct; + + /* DataStoreWrite: '/Data Store Write6' incorporates: + * DataStoreWrite: '/Data Store Write5' + */ + rtDW.Blower_FL = rtDW.Blower_FR; + + /* MATLAB Function: '/Dtg_FrontUpper_X' incorporates: + * DataStoreRead: '/Data Store Read8' + */ + Dtg_FrontUpper_X(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* Gain: '/Gain1' incorporates: + * DataStoreWrite: '/Data Store Write10' + */ + rtDW.Dtg_FUR = (uint16_t)(10U * Comp_Max_RPM_Allowed); + + /* DataStoreWrite: '/Data Store Write11' incorporates: + * DataStoreWrite: '/Data Store Write10' + */ + rtDW.Dtg_FUL = rtDW.Dtg_FUR; + + /* MATLAB Function: '/Dtg_FrontLower_X' incorporates: + * DataStoreRead: '/Data Store Read9' + */ + Dtg_FrontLower_X(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* Gain: '/Gain2' incorporates: + * DataStoreWrite: '/Data Store Write12' + */ + rtDW.Dtg_FLR = (uint16_t)(10U * Comp_Max_RPM_Allowed); + + /* DataStoreWrite: '/Data Store Write13' incorporates: + * DataStoreWrite: '/Data Store Write12' + */ + rtDW.Dtg_FLL = rtDW.Dtg_FLR; + + /* DataStoreWrite: '/Data Store Write7' incorporates: + * Constant: '/Recirc logic Partial REC' + */ + rtb_Add_be = 1.0; + + /* MATLAB Function: '/Incar temp goto from step 1 to step 2 ' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + Incartempgotofromstep1tostep2(rtDW.LEVEL, &Eva_Target); + + /* MATLAB Function: '/Time goto from step 1 to step 2 ' incorporates: + * DataStoreRead: '/Data Store Read4' + */ + Timegotofromstep1tostep2(rtDW.LEVEL, &rtb_FLU_tg_correct); + + /* MATLAB Function: '/MATLAB Function1' incorporates: + * DataStoreRead: '/Data Store Read13' + * Gain: '/ ' + */ + MATLABFunction1_j(rtDW.t_now, (uint32_t)(1000 * rtb_FLU_tg_correct), + &eComp_stop, &rtDW.sf_MATLABFunction1_h); + + /* Switch: '/Switch1' incorporates: + * Constant: '/LO' + * DataStoreRead: '/Data Store Read11' + * DataStoreRead: '/Data Store Read12' + * DataStoreRead: '/incar temp' + * Logic: '/Logical Operator' + * Logic: '/Logical Operator1' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator2' + * RelationalOperator: '/Relational Operator3' + * Switch: '/Switch' + */ + if ((rtDW.CCU_MODE_FL != 1) || (rtDW.LO_HI_MODE_FL == 1)) { + /* Merge: '/Merge' incorporates: + * Constant: '/exit algorithm' + */ + rtB.Merge_pe = 3; + } else if ((rtDW.Incar_FL > Eva_Target) || eComp_stop) { + /* Switch: '/Switch' incorporates: + * Constant: '/go to next step' + * Merge: '/Merge' + */ + rtB.Merge_pe = 2; + } else { + /* Merge: '/Merge' incorporates: + * Constant: '/stay at step 1' + * Switch: '/Switch' + */ + rtB.Merge_pe = 1; + } + + /* End of Switch: '/Switch1' */ + /* End of Outputs for SubSystem: '/Level 4' */ + break; + + case 5: + /* Outputs for IfAction SubSystem: '/Level 5' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write8' incorporates: + * DataStoreRead: '/Data Store Read10' + * MATLAB Function: '/3 way valve status' + */ + uwayvalvestatus(rtDW.LEVEL, &ShutOffFront_EN); + + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataStoreRead: '/Data Store Read1' + * MATLAB Function: '/incar filter up' + */ + incarfilterup(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataStoreRead: '/Data Store Read2' + * MATLAB Function: '/incar filter down' + */ + incarfilterdown(rtDW.LEVEL, &EN_BATTChiller); + + /* MATLAB Function: '/mode FR step 1' incorporates: + * DataStoreRead: '/Data Store Read5' + */ + modeFRstep1(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* DataStoreWrite: '/Data Store Write2' */ + rtDW.Mode_FR = Comp_Max_RPM_Allowed; + + /* DataStoreWrite: '/Data Store Write3' */ + rtDW.Mode_FL = Comp_Max_RPM_Allowed; + + /* MATLAB Function: '/window heating' incorporates: + * DataStoreRead: '/Data Store Read6' + */ + windowheating(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* MATLAB Function: '/blower min max' incorporates: + * DataStoreRead: '/Data Store Read7' + */ + blowerminmax(rtDW.LEVEL, rtb_out_gx); + + /* MATLAB Function: '/ECT min max' incorporates: + * DataStoreRead: '/Data Store Read7' + */ + ECTminmax(rtDW.LEVEL, rtb_out_knd); + + /* Lookup_n-D: '/blower ECT' incorporates: + * DataStoreRead: '/engine coolant temp' + */ + rtb_FLU_tg_correct = look1_is16lu64n32tu16Ds32Is16_binlcs(rtDW.ECT, + rtb_out_knd, rtb_out_gx, 1U); + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * DataStoreWrite: '/Data Store Write5' + * DataTypeConversion: '/Data Type Conversion1' + */ + rtDW.Blower_FR = (uint8_t)rtb_FLU_tg_correct; + + /* DataStoreWrite: '/Data Store Write6' incorporates: + * DataStoreWrite: '/Data Store Write5' + */ + rtDW.Blower_FL = rtDW.Blower_FR; + + /* MATLAB Function: '/Dtg_FrontUpper_X' incorporates: + * DataStoreRead: '/Data Store Read8' + */ + Dtg_FrontUpper_X(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* Gain: '/Gain2' incorporates: + * DataStoreWrite: '/Data Store Write10' + */ + rtDW.Dtg_FUR = (uint16_t)(10U * Comp_Max_RPM_Allowed); + + /* DataStoreWrite: '/Data Store Write11' incorporates: + * DataStoreWrite: '/Data Store Write10' + */ + rtDW.Dtg_FUL = rtDW.Dtg_FUR; + + /* MATLAB Function: '/Dtg_FrontLower_X' incorporates: + * DataStoreRead: '/Data Store Read9' + */ + Dtg_FrontLower_X(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* Gain: '/Gain1' incorporates: + * DataStoreWrite: '/Data Store Write12' + */ + rtDW.Dtg_FLR = (uint16_t)(10U * Comp_Max_RPM_Allowed); + + /* DataStoreWrite: '/Data Store Write13' incorporates: + * DataStoreWrite: '/Data Store Write12' + */ + rtDW.Dtg_FLL = rtDW.Dtg_FLR; + + /* DataStoreWrite: '/Data Store Write7' incorporates: + * Constant: '/Recirc logic Partial REC' + */ + rtb_Add_be = 1.0; + + /* MATLAB Function: '/Incar temp goto from step 1 to step 2 ' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + Incartempgotofromstep1tostep2(rtDW.LEVEL, &Eva_Target); + + /* MATLAB Function: '/Time goto from step 1 to step 2 ' incorporates: + * DataStoreRead: '/Data Store Read4' + */ + Timegotofromstep1tostep2(rtDW.LEVEL, &rtb_FLU_tg_correct); + + /* MATLAB Function: '/MATLAB Function1' incorporates: + * DataStoreRead: '/Data Store Read13' + * Gain: '/ ' + */ + MATLABFunction1_j(rtDW.t_now, (uint32_t)(1000 * rtb_FLU_tg_correct), + &eComp_stop, &rtDW.sf_MATLABFunction1_p); + + /* Switch: '/Switch1' incorporates: + * Constant: '/LO' + * DataStoreRead: '/Data Store Read11' + * DataStoreRead: '/Data Store Read12' + * DataStoreRead: '/incar temp' + * Logic: '/Logical Operator' + * Logic: '/Logical Operator1' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator2' + * RelationalOperator: '/Relational Operator3' + * Switch: '/Switch' + */ + if ((rtDW.CCU_MODE_FL != 1) || (rtDW.LO_HI_MODE_FL == 1)) { + /* Merge: '/Merge' incorporates: + * Constant: '/exit algorithm' + */ + rtB.Merge_pe = 3; + } else if ((rtDW.Incar_FL > Eva_Target) || eComp_stop) { + /* Switch: '/Switch' incorporates: + * Constant: '/go to next step' + * Merge: '/Merge' + */ + rtB.Merge_pe = 2; + } else { + /* Merge: '/Merge' incorporates: + * Constant: '/stay at step 1' + * Switch: '/Switch' + */ + rtB.Merge_pe = 1; + } + + /* End of Switch: '/Switch1' */ + /* End of Outputs for SubSystem: '/Level 5' */ + break; + } + + /* End of SwitchCase: '/Switch Case' */ + /* End of Outputs for SubSystem: '/Step 1 F' */ + break; + + case 2: + /* Outputs for IfAction SubSystem: '/Step 2 F' incorporates: + * ActionPort: '/Action Port' + */ + /* SwitchCase: '/Switch Case' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + switch (rtDW.LEVEL) { + case 0: + /* Outputs for IfAction SubSystem: '/Level 0' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write8' incorporates: + * DataStoreRead: '/Data Store Read10' + * MATLAB Function: '/3 way valve status' + */ + uwayvalvestatus_m(rtDW.LEVEL, &ShutOffFront_EN); + + /* Sum: '/Add' incorporates: + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + */ + Eva_Target = (int16_t)((rtDW.Dtg_FLL - rtb_y_co) >> 1); + + /* MATLAB Function: '/step' incorporates: + * DataStoreRead: '/Data Store Read9' + */ + Dtg_FrontLower_X(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* MATLAB Function: '/time for step' incorporates: + * DataStoreRead: '/Data Store Read9' + */ + timeforstep(rtDW.LEVEL, &EN_BATTChiller); + + /* Abs: '/Abs' */ + if (Eva_Target < 0) { + Eva_Target = (int16_t)-Eva_Target; + } + + /* Switch: '/Switch' incorporates: + * Abs: '/Abs' + * Constant: '/Constant' + * Constant: '/epsilon' + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + * DataStoreRead: '/ ' + * DataStoreWrite: '/Data Store Write12' + * Gain: '/Gain1' + * Product: '/Product1' + * Product: '/change rate (dtg//sec)' + * Product: '/ ' + * Product: '/ ' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + * Sum: '/Subtract' + * Switch: '/Switch' + * UnitDelay: '/Unit Delay' + */ + if ((double)Eva_Target * 2.0 <= 0.01) { + rtDW.Dtg_FLR = (uint16_t)rtb_y_co; + } else { + if (rtDW.Dtg_FLL <= rtb_y_co) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + */ + i = 1; + } else { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant1' + */ + i = -1; + } + + rtDW.Dtg_FLR = (uint16_t)rt_roundd(10.0 * (double)Comp_Max_RPM_Allowed + / (double)EN_BATTChiller / 1000.0 * (double)(rtDW.t_now - + rtDW.UnitDelay_DSTATE_k) * (double)i + (double)rtDW.Dtg_FLL); + } + + /* End of Switch: '/Switch' */ + + /* DataStoreWrite: '/Data Store Write13' incorporates: + * DataStoreWrite: '/Data Store Write12' + */ + rtDW.Dtg_FLL = rtDW.Dtg_FLR; + + /* Sum: '/Add' incorporates: + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + */ + Eva_Target = (int16_t)((rtDW.Dtg_FUL - rtb_FLU_tg_correct) >> 1); + + /* Abs: '/Abs' */ + if (Eva_Target < 0) { + Eva_Target = (int16_t)-Eva_Target; + } + + /* End of Abs: '/Abs' */ + + /* MATLAB Function: '/step' incorporates: + * DataStoreRead: '/Data Store Read8' + */ + Dtg_FrontUpper_X(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* MATLAB Function: '/time for step' incorporates: + * DataStoreRead: '/Data Store Read8' + */ + timeforstep_d(rtDW.LEVEL, &EN_BATTChiller); + + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + * Constant: '/epsilon' + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + * DataStoreRead: '/ ' + * DataStoreWrite: '/Data Store Write10' + * Gain: '/Gain1' + * Product: '/Product1' + * Product: '/change rate (dtg//sec)' + * Product: '/ ' + * Product: '/ ' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + * Sum: '/Subtract' + * Switch: '/Switch' + * UnitDelay: '/Unit Delay' + */ + if ((double)Eva_Target * 2.0 <= 0.01) { + rtDW.Dtg_FUR = (uint16_t)rtb_FLU_tg_correct; + } else { + if (rtDW.Dtg_FUL <= rtb_FLU_tg_correct) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + */ + i = 1; + } else { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant1' + */ + i = -1; + } + + rtDW.Dtg_FUR = (uint16_t)rt_roundd(10.0 * (double)Comp_Max_RPM_Allowed + / (double)EN_BATTChiller / 1000.0 * (double)(rtDW.t_now - + rtDW.UnitDelay_DSTATE_cm) * (double)i + (double)rtDW.Dtg_FUL); + } + + /* End of Switch: '/Switch' */ + + /* DataStoreWrite: '/Data Store Write11' incorporates: + * DataStoreWrite: '/Data Store Write10' + */ + rtDW.Dtg_FUL = rtDW.Dtg_FUR; + + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataStoreRead: '/Data Store Read1' + * MATLAB Function: '/incar filter up' + */ + incarfilterup(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataStoreRead: '/Data Store Read2' + * MATLAB Function: '/incar filter down' + */ + incarfilterdown(rtDW.LEVEL, &EN_BATTChiller); + + /* MATLAB Function: '/step' incorporates: + * DataStoreRead: '/Data Store Read5' + */ + step_g(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* MATLAB Function: '/time for step' incorporates: + * DataStoreRead: '/Data Store Read5' + */ + timeforstep_f(rtDW.LEVEL, &EN_BATTChiller); + + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + * Constant: '/epsilon' + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + * DataStoreRead: '/ ' + * DataStoreWrite: '/Data Store Write2' + * Product: '/Product1' + * Product: '/change rate (step//sec)' + * Product: '/ ' + * Product: '/ ' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + * Sum: '/Add' + * Sum: '/Subtract' + * Switch: '/Switch' + * UnitDelay: '/Unit Delay' + */ + if ((uint8_t)(rtDW.Mode_FL - rtDW.Mode_logic_FL) <= 0.01) { + rtDW.Mode_FR = rtDW.Mode_logic_FL; + } else { + if (rtDW.Mode_FL <= rtDW.Mode_logic_FL) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + */ + i = 1; + } else { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant1' + */ + i = -1; + } + + rtDW.Mode_FR = (uint8_t)((double)Comp_Max_RPM_Allowed / (double) + EN_BATTChiller / 1000.0 * (double)(rtDW.t_now - + rtDW.UnitDelay_DSTATE_f) * (double)i + (double)rtDW.Mode_FL); + } + + /* End of Switch: '/Switch' */ + + /* DataStoreWrite: '/Data Store Write3' incorporates: + * DataStoreWrite: '/Data Store Write2' + */ + rtDW.Mode_FL = rtDW.Mode_FR; + + /* MATLAB Function: '/blower step' incorporates: + * DataStoreRead: '/Data Store Read7' + */ + /* : out = g_aucSTART_ELEC_WINDOW(LVL + 1 + 6); */ + blowerstep(rtDW.LEVEL, &Gain); + + /* MATLAB Function: '/blower time for step' incorporates: + * DataStoreRead: '/Data Store Read7' + */ + blowertimeforstep(rtDW.LEVEL, &Gain1); + + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + * Constant: '/epsilon' + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + * DataStoreRead: '/ ' + * Product: '/Product1' + * Product: '/change rate (AF//sec)' + * Product: '/ ' + * Product: '/ ' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + * Sum: '/Add' + * Sum: '/Subtract' + * Switch: '/Switch' + * UnitDelay: '/Unit Delay' + */ + if ((uint8_t)(rtDW.Blower_FL - rtDW.Blower_logic_FL) <= 0.01) { + rtb_Add_be = rtDW.Blower_logic_FL; + } else { + if (rtDW.Blower_FL <= rtDW.Blower_logic_FL) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + */ + i = 1; + } else { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant1' + */ + i = -1; + } + + rtb_Add_be = (double)Gain / (double)Gain1 / 1000.0 * (double) + (rtDW.t_now - rtDW.UnitDelay_DSTATE_gc) * (double)i + (double) + rtDW.Blower_FL; + } + + /* End of Switch: '/Switch' */ + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * DataStoreWrite: '/Data Store Write5' + */ + rtDW.Blower_FR = (uint8_t)rtb_Add_be; + + /* DataStoreWrite: '/Data Store Write6' incorporates: + * DataStoreWrite: '/Data Store Write5' + */ + rtDW.Blower_FL = rtDW.Blower_FR; + + /* DataStoreWrite: '/Data Store Write7' incorporates: + * Constant: '/Recirc logic Partial REC' + */ + rtb_Add_be = 1.0; + + /* RelationalOperator: '/Relational Operator2' incorporates: + * DataStoreRead: '/Data Store Read11' + */ + eComp_stop = (rtDW.CCU_MODE_FL != 1); + + /* Logic: '/Logical Operator1' incorporates: + * Constant: '/not LO or HI' + * DataStoreRead: '/Data Store Read12' + * RelationalOperator: '/Relational Operator3' + */ + Enable_Comp_PID = (eComp_stop || (rtDW.LO_HI_MODE_FL != 0)); + + /* MATLAB Function: '/Time goto from step 2 to step 3 ' incorporates: + * DataStoreRead: '/Data Store Read4' + */ + Timegotofromstep2tostep3(rtDW.LEVEL, &Eva_Target); + + /* MATLAB Function: '/MATLAB Function1' incorporates: + * DataStoreRead: '/Data Store Read3' + * Gain: '/ ' + */ + MATLABFunction1_j(rtDW.t_now, (uint32_t)(1000 * Eva_Target), &eComp_stop, + &rtDW.sf_MATLABFunction1_m); + + /* Switch: '/Switch1' incorporates: + * Switch: '/Switch' + */ + if (Enable_Comp_PID) { + /* Merge: '/Merge' incorporates: + * Constant: '/exit algorithm' + */ + rtB.Merge_pe = 3; + } else if (eComp_stop) { + /* Switch: '/Switch' incorporates: + * Constant: '/go to next step' + * Merge: '/Merge' + */ + rtB.Merge_pe = 3; + } else { + /* Merge: '/Merge' incorporates: + * Constant: '/stay at step' + * Switch: '/Switch' + */ + rtB.Merge_pe = 2; + } + + /* End of Switch: '/Switch1' */ + + /* Update for UnitDelay: '/Unit Delay' incorporates: + * DataStoreRead: '/ ' + */ + rtDW.UnitDelay_DSTATE_k = rtDW.t_now; + + /* Update for UnitDelay: '/Unit Delay' incorporates: + * DataStoreRead: '/ ' + */ + rtDW.UnitDelay_DSTATE_cm = rtDW.t_now; + + /* Update for UnitDelay: '/Unit Delay' incorporates: + * DataStoreRead: '/ ' + */ + rtDW.UnitDelay_DSTATE_f = rtDW.t_now; + + /* Update for UnitDelay: '/Unit Delay' incorporates: + * DataStoreRead: '/ ' + */ + rtDW.UnitDelay_DSTATE_gc = rtDW.t_now; + + /* End of Outputs for SubSystem: '/Level 0' */ + break; + + case 1: + /* Outputs for IfAction SubSystem: '/Level 1' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write8' incorporates: + * DataStoreRead: '/Data Store Read10' + * MATLAB Function: '/3 way valve status' + */ + uwayvalvestatus_m(rtDW.LEVEL, &ShutOffFront_EN); + + /* Sum: '/Add' incorporates: + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + */ + Eva_Target = (int16_t)((rtDW.Dtg_FLL - rtb_y_co) >> 1); + + /* MATLAB Function: '/step' incorporates: + * DataStoreRead: '/Data Store Read9' + */ + Dtg_FrontLower_X(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* MATLAB Function: '/time for step' incorporates: + * DataStoreRead: '/Data Store Read9' + */ + timeforstep(rtDW.LEVEL, &EN_BATTChiller); + + /* Abs: '/Abs' */ + if (Eva_Target < 0) { + Eva_Target = (int16_t)-Eva_Target; + } + + /* Switch: '/Switch' incorporates: + * Abs: '/Abs' + * Constant: '/Constant' + * Constant: '/epsilon' + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + * DataStoreRead: '/ ' + * DataStoreWrite: '/Data Store Write12' + * Gain: '/Gain1' + * Product: '/Product1' + * Product: '/change rate (dtg//sec)' + * Product: '/ ' + * Product: '/ ' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + * Sum: '/Subtract' + * Switch: '/Switch' + * UnitDelay: '/Unit Delay' + */ + if ((double)Eva_Target * 2.0 <= 0.01) { + rtDW.Dtg_FLR = (uint16_t)rtb_y_co; + } else { + if (rtDW.Dtg_FLL <= rtb_y_co) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + */ + i = 1; + } else { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant1' + */ + i = -1; + } + + rtDW.Dtg_FLR = (uint16_t)rt_roundd(10.0 * (double)Comp_Max_RPM_Allowed + / (double)EN_BATTChiller / 1000.0 * (double)(rtDW.t_now - + rtDW.UnitDelay_DSTATE_mz) * (double)i + (double)rtDW.Dtg_FLL); + } + + /* End of Switch: '/Switch' */ + + /* DataStoreWrite: '/Data Store Write13' incorporates: + * DataStoreWrite: '/Data Store Write12' + */ + rtDW.Dtg_FLL = rtDW.Dtg_FLR; + + /* Sum: '/Add' incorporates: + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + */ + Eva_Target = (int16_t)((rtDW.Dtg_FUL - rtb_FLU_tg_correct) >> 1); + + /* Abs: '/Abs' */ + if (Eva_Target < 0) { + Eva_Target = (int16_t)-Eva_Target; + } + + /* End of Abs: '/Abs' */ + + /* MATLAB Function: '/step' incorporates: + * DataStoreRead: '/Data Store Read8' + */ + Dtg_FrontUpper_X(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* MATLAB Function: '/time for step' incorporates: + * DataStoreRead: '/Data Store Read8' + */ + timeforstep_d(rtDW.LEVEL, &EN_BATTChiller); + + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + * Constant: '/epsilon' + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + * DataStoreRead: '/ ' + * DataStoreWrite: '/Data Store Write10' + * Gain: '/Gain1' + * Product: '/Product1' + * Product: '/change rate (dtg//sec)' + * Product: '/ ' + * Product: '/ ' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + * Sum: '/Subtract' + * Switch: '/Switch' + * UnitDelay: '/Unit Delay' + */ + if ((double)Eva_Target * 2.0 <= 0.01) { + rtDW.Dtg_FUR = (uint16_t)rtb_FLU_tg_correct; + } else { + if (rtDW.Dtg_FUL <= rtb_FLU_tg_correct) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + */ + i = 1; + } else { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant1' + */ + i = -1; + } + + rtDW.Dtg_FUR = (uint16_t)rt_roundd(10.0 * (double)Comp_Max_RPM_Allowed + / (double)EN_BATTChiller / 1000.0 * (double)(rtDW.t_now - + rtDW.UnitDelay_DSTATE_n) * (double)i + (double)rtDW.Dtg_FUL); + } + + /* End of Switch: '/Switch' */ + + /* DataStoreWrite: '/Data Store Write11' incorporates: + * DataStoreWrite: '/Data Store Write10' + */ + rtDW.Dtg_FUL = rtDW.Dtg_FUR; + + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataStoreRead: '/Data Store Read1' + * MATLAB Function: '/incar filter up' + */ + incarfilterup(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataStoreRead: '/Data Store Read2' + * MATLAB Function: '/incar filter down' + */ + incarfilterdown(rtDW.LEVEL, &EN_BATTChiller); + + /* Sum: '/Add' incorporates: + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + */ + Comp_Max_RPM_Allowed = (uint8_t)(rtDW.Mode_FL - rtDW.Mode_logic_FL); + + /* MATLAB Function: '/step' incorporates: + * DataStoreRead: '/Data Store Read5' + */ + step_g(rtDW.LEVEL, &EN_BATTChiller); + + /* MATLAB Function: '/time for step' incorporates: + * DataStoreRead: '/Data Store Read5' + */ + timeforstep_f(rtDW.LEVEL, &ShutOffFront_EN); + + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + * Constant: '/epsilon' + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + * DataStoreRead: '/ ' + * DataStoreWrite: '/Data Store Write2' + * Product: '/Product1' + * Product: '/change rate (step//sec)' + * Product: '/ ' + * Product: '/ ' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + * Sum: '/Subtract' + * Switch: '/Switch' + * UnitDelay: '/Unit Delay' + */ + if (Comp_Max_RPM_Allowed <= 0.01) { + rtDW.Mode_FR = rtDW.Mode_logic_FL; + } else { + if (rtDW.Mode_FL <= rtDW.Mode_logic_FL) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + */ + i = 1; + } else { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant1' + */ + i = -1; + } + + rtDW.Mode_FR = (uint8_t)((double)EN_BATTChiller / (double) + ShutOffFront_EN / 1000.0 * (double)(rtDW.t_now - + rtDW.UnitDelay_DSTATE_le) * (double)i + (double)rtDW.Mode_FL); + } + + /* End of Switch: '/Switch' */ + + /* DataStoreWrite: '/Data Store Write3' incorporates: + * DataStoreWrite: '/Data Store Write2' + */ + rtDW.Mode_FL = rtDW.Mode_FR; + + /* MATLAB Function: '/window heating' incorporates: + * DataStoreRead: '/Data Store Read6' + */ + windowheating_o(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* MATLAB Function: '/blower step' incorporates: + * DataStoreRead: '/Data Store Read7' + */ + blowerstep(rtDW.LEVEL, &Gain); + + /* MATLAB Function: '/blower time for step' incorporates: + * DataStoreRead: '/Data Store Read7' + */ + blowertimeforstep(rtDW.LEVEL, &Gain1); + + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + * Constant: '/epsilon' + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + * DataStoreRead: '/ ' + * Product: '/Product1' + * Product: '/change rate (step//sec)' + * Product: '/ ' + * Product: '/ ' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + * Sum: '/Add' + * Sum: '/Subtract' + * Switch: '/Switch' + * UnitDelay: '/Unit Delay' + */ + if ((uint8_t)(rtDW.Blower_FL - rtDW.Blower_logic_FL) <= 0.01) { + rtb_Add_be = rtDW.Blower_logic_FL; + } else { + if (rtDW.Blower_FL <= rtDW.Blower_logic_FL) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + */ + i = 1; + } else { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant1' + */ + i = -1; + } + + rtb_Add_be = (double)Gain / (double)Gain1 / 1000.0 * (double) + (rtDW.t_now - rtDW.UnitDelay_DSTATE_cb) * (double)i + (double) + rtDW.Blower_FL; + } + + /* End of Switch: '/Switch' */ + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * DataStoreWrite: '/Data Store Write5' + */ + rtDW.Blower_FR = (uint8_t)rtb_Add_be; + + /* DataStoreWrite: '/Data Store Write6' incorporates: + * DataStoreWrite: '/Data Store Write5' + */ + rtDW.Blower_FL = rtDW.Blower_FR; + + /* DataStoreWrite: '/Data Store Write7' incorporates: + * Constant: '/Recirc logic Partial REC' + */ + rtb_Add_be = 1.0; + + /* RelationalOperator: '/Relational Operator2' incorporates: + * DataStoreRead: '/Data Store Read11' + */ + eComp_stop = (rtDW.CCU_MODE_FL != 1); + + /* Logic: '/Logical Operator1' incorporates: + * Constant: '/not LO or HI' + * DataStoreRead: '/Data Store Read12' + * RelationalOperator: '/Relational Operator3' + */ + Enable_Comp_PID = (eComp_stop || (rtDW.LO_HI_MODE_FL != 0)); + + /* MATLAB Function: '/Time goto from step 2 to step 3 ' incorporates: + * DataStoreRead: '/Data Store Read4' + */ + Timegotofromstep2tostep3(rtDW.LEVEL, &Eva_Target); + + /* MATLAB Function: '/MATLAB Function1' incorporates: + * DataStoreRead: '/Data Store Read3' + * Gain: '/ ' + */ + MATLABFunction1_j(rtDW.t_now, (uint32_t)(1000 * Eva_Target), &eComp_stop, + &rtDW.sf_MATLABFunction1_i2); + + /* Switch: '/Switch1' incorporates: + * Switch: '/Switch' + */ + if (Enable_Comp_PID) { + /* Merge: '/Merge' incorporates: + * Constant: '/exit algorithm' + */ + rtB.Merge_pe = 3; + } else if (eComp_stop) { + /* Switch: '/Switch' incorporates: + * Constant: '/go to next step' + * Merge: '/Merge' + */ + rtB.Merge_pe = 3; + } else { + /* Merge: '/Merge' incorporates: + * Constant: '/stay at step' + * Switch: '/Switch' + */ + rtB.Merge_pe = 2; + } + + /* End of Switch: '/Switch1' */ + + /* Update for UnitDelay: '/Unit Delay' incorporates: + * DataStoreRead: '/ ' + */ + rtDW.UnitDelay_DSTATE_mz = rtDW.t_now; + + /* Update for UnitDelay: '/Unit Delay' incorporates: + * DataStoreRead: '/ ' + */ + rtDW.UnitDelay_DSTATE_n = rtDW.t_now; + + /* Update for UnitDelay: '/Unit Delay' incorporates: + * DataStoreRead: '/ ' + */ + rtDW.UnitDelay_DSTATE_le = rtDW.t_now; + + /* Update for UnitDelay: '/Unit Delay' incorporates: + * DataStoreRead: '/ ' + */ + rtDW.UnitDelay_DSTATE_cb = rtDW.t_now; + + /* End of Outputs for SubSystem: '/Level 1' */ + break; + + case 2: + /* Outputs for IfAction SubSystem: '/Level 2' incorporates: + * ActionPort: '/Action Port' + */ + Level2(&rtB.Merge_pe); + + /* End of Outputs for SubSystem: '/Level 2' */ + break; + + case 3: + /* Outputs for IfAction SubSystem: '/Level 3' incorporates: + * ActionPort: '/Action Port' + */ + Level3(&rtB.Merge_pe, &ShutOffRear_EN, &rtDW.Blower_FL, &rtDW.Blower_FR, + &rtDW.Blower_logic_FL, &rtDW.CCU_MODE_FL, &rtDW.Dtg_FLL, + &rtDW.Dtg_FLR, &rtDW.Dtg_FUL, &rtDW.Dtg_FUR, &rtb_y_co, + &rtb_FLU_tg_correct, &El_window_heating, &rtDW.HI_logic_on, + &EN_BATTChiller, &Comp_Max_RPM_Allowed, &rtDW.LEVEL, + &rtDW.LO_HI_MODE_FL, &rtDW.Mode_FL, &rtDW.Mode_FR, + &rtDW.Mode_logic_FL, &rtb_Add_be, &ShutOffFront_EN, &rtDW.t_now, + &rtDW.Level3_d); + + /* End of Outputs for SubSystem: '/Level 3' */ + break; + + case 4: + /* Outputs for IfAction SubSystem: '/Level 4' incorporates: + * ActionPort: '/Action Port' + */ + Level3(&rtB.Merge_pe, &ShutOffRear_EN, &rtDW.Blower_FL, &rtDW.Blower_FR, + &rtDW.Blower_logic_FL, &rtDW.CCU_MODE_FL, &rtDW.Dtg_FLL, + &rtDW.Dtg_FLR, &rtDW.Dtg_FUL, &rtDW.Dtg_FUR, &rtb_y_co, + &rtb_FLU_tg_correct, &El_window_heating, &rtDW.HI_logic_on, + &EN_BATTChiller, &Comp_Max_RPM_Allowed, &rtDW.LEVEL, + &rtDW.LO_HI_MODE_FL, &rtDW.Mode_FL, &rtDW.Mode_FR, + &rtDW.Mode_logic_FL, &rtb_Add_be, &ShutOffFront_EN, &rtDW.t_now, + &rtDW.Level4_l); + + /* End of Outputs for SubSystem: '/Level 4' */ + break; + + case 5: + /* Outputs for IfAction SubSystem: '/Level 5' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write8' incorporates: + * DataStoreRead: '/Data Store Read10' + * MATLAB Function: '/3 way valve status' + */ + uwayvalvestatus_m(rtDW.LEVEL, &ShutOffFront_EN); + + /* Sum: '/Add' incorporates: + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + */ + Eva_Target = (int16_t)((rtDW.Dtg_FLL - rtb_y_co) >> 1); + + /* MATLAB Function: '/step' incorporates: + * DataStoreRead: '/Data Store Read9' + */ + Dtg_FrontLower_X(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* MATLAB Function: '/time for step' incorporates: + * DataStoreRead: '/Data Store Read9' + */ + timeforstep(rtDW.LEVEL, &EN_BATTChiller); + + /* Abs: '/Abs' */ + if (Eva_Target < 0) { + Eva_Target = (int16_t)-Eva_Target; + } + + /* Switch: '/Switch' incorporates: + * Abs: '/Abs' + * Constant: '/Constant' + * Constant: '/epsilon' + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + * DataStoreRead: '/ ' + * DataStoreWrite: '/Data Store Write12' + * Gain: '/Gain1' + * Product: '/Product1' + * Product: '/change rate (dtg//sec)' + * Product: '/ ' + * Product: '/ ' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + * Sum: '/Subtract' + * Switch: '/Switch' + * UnitDelay: '/Unit Delay' + */ + if ((double)Eva_Target * 2.0 <= 0.01) { + rtDW.Dtg_FLR = (uint16_t)rtb_y_co; + } else { + if (rtDW.Dtg_FLL <= rtb_y_co) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + */ + i = 1; + } else { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant1' + */ + i = -1; + } + + rtDW.Dtg_FLR = (uint16_t)rt_roundd(10.0 * (double)Comp_Max_RPM_Allowed + / (double)EN_BATTChiller / 1000.0 * (double)(rtDW.t_now - + rtDW.UnitDelay_DSTATE_g) * (double)i + (double)rtDW.Dtg_FLL); + } + + /* End of Switch: '/Switch' */ + + /* DataStoreWrite: '/Data Store Write13' incorporates: + * DataStoreWrite: '/Data Store Write12' + */ + rtDW.Dtg_FLL = rtDW.Dtg_FLR; + + /* Sum: '/Add' incorporates: + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + */ + Eva_Target = (int16_t)((rtDW.Dtg_FUL - rtb_FLU_tg_correct) >> 1); + + /* Abs: '/Abs' */ + if (Eva_Target < 0) { + Eva_Target = (int16_t)-Eva_Target; + } + + /* End of Abs: '/Abs' */ + + /* MATLAB Function: '/step' incorporates: + * DataStoreRead: '/Data Store Read8' + */ + Dtg_FrontUpper_X(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* MATLAB Function: '/time for step' incorporates: + * DataStoreRead: '/Data Store Read8' + */ + timeforstep_d(rtDW.LEVEL, &EN_BATTChiller); + + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + * Constant: '/epsilon' + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + * DataStoreRead: '/ ' + * DataStoreWrite: '/Data Store Write10' + * Gain: '/Gain1' + * Product: '/Product1' + * Product: '/change rate (dtg//sec)' + * Product: '/ ' + * Product: '/ ' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + * Sum: '/Subtract' + * Switch: '/Switch' + * UnitDelay: '/Unit Delay' + */ + if ((double)Eva_Target * 2.0 <= 0.01) { + rtDW.Dtg_FUR = (uint16_t)rtb_FLU_tg_correct; + } else { + if (rtDW.Dtg_FUL <= rtb_FLU_tg_correct) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + */ + i = 1; + } else { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant1' + */ + i = -1; + } + + rtDW.Dtg_FUR = (uint16_t)rt_roundd(10.0 * (double)Comp_Max_RPM_Allowed + / (double)EN_BATTChiller / 1000.0 * (double)(rtDW.t_now - + rtDW.UnitDelay_DSTATE_h) * (double)i + (double)rtDW.Dtg_FUL); + } + + /* End of Switch: '/Switch' */ + + /* DataStoreWrite: '/Data Store Write11' incorporates: + * DataStoreWrite: '/Data Store Write10' + */ + rtDW.Dtg_FUL = rtDW.Dtg_FUR; + + /* DataStoreWrite: '/Data Store Write' incorporates: + * DataStoreRead: '/Data Store Read1' + * MATLAB Function: '/incar filter up' + */ + incarfilterup(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* DataStoreWrite: '/Data Store Write1' incorporates: + * DataStoreRead: '/Data Store Read2' + * MATLAB Function: '/incar filter down' + */ + incarfilterdown(rtDW.LEVEL, &EN_BATTChiller); + + /* MATLAB Function: '/autodemist (autodefog)' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + autodemistautodefog(rtDW.LEVEL, &EN_BATTChiller); + + /* Sum: '/Add' incorporates: + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + */ + Comp_Max_RPM_Allowed = (uint8_t)(rtDW.Mode_FL - rtDW.Mode_logic_FL); + + /* MATLAB Function: '/step' incorporates: + * DataStoreRead: '/Data Store Read5' + */ + step_g(rtDW.LEVEL, &EN_BATTChiller); + + /* MATLAB Function: '/time for step' incorporates: + * DataStoreRead: '/Data Store Read5' + */ + timeforstep_f(rtDW.LEVEL, &ShutOffFront_EN); + + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + * Constant: '/epsilon' + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + * DataStoreRead: '/ ' + * DataStoreWrite: '/Data Store Write2' + * Product: '/Product1' + * Product: '/change rate (step//sec)' + * Product: '/ ' + * Product: '/ ' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + * Sum: '/Subtract' + * Switch: '/Switch' + * UnitDelay: '/Unit Delay' + */ + if (Comp_Max_RPM_Allowed <= 0.01) { + rtDW.Mode_FR = rtDW.Mode_logic_FL; + } else { + if (rtDW.Mode_FL <= rtDW.Mode_logic_FL) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + */ + i = 1; + } else { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant1' + */ + i = -1; + } + + rtDW.Mode_FR = (uint8_t)((double)EN_BATTChiller / (double) + ShutOffFront_EN / 1000.0 * (double)(rtDW.t_now - + rtDW.UnitDelay_DSTATE_ly) * (double)i + (double)rtDW.Mode_FL); + } + + /* End of Switch: '/Switch' */ + + /* DataStoreWrite: '/Data Store Write3' incorporates: + * DataStoreWrite: '/Data Store Write2' + */ + rtDW.Mode_FL = rtDW.Mode_FR; + + /* MATLAB Function: '/window heating' incorporates: + * DataStoreRead: '/Data Store Read6' + */ + windowheating_o(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* MATLAB Function: '/blower step' incorporates: + * DataStoreRead: '/Data Store Read7' + */ + blowerstep(rtDW.LEVEL, &Gain); + + /* MATLAB Function: '/blower time for step' incorporates: + * DataStoreRead: '/Data Store Read7' + */ + blowertimeforstep(rtDW.LEVEL, &Gain1); + + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + * Constant: '/epsilon' + * DataStoreRead: '/ blower ' + * DataStoreRead: '/ auto ( )' + * DataStoreRead: '/ ' + * Product: '/Product1' + * Product: '/change rate (step//sec)' + * Product: '/ ' + * Product: '/ ' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator' + * Sum: '/Add' + * Sum: '/Add' + * Sum: '/Subtract' + * Switch: '/Switch' + * UnitDelay: '/Unit Delay' + */ + if ((uint8_t)(rtDW.Blower_FL - rtDW.Blower_logic_FL) <= 0.01) { + rtb_Add_be = rtDW.Blower_logic_FL; + } else { + if (rtDW.Blower_FL <= rtDW.Blower_logic_FL) { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant' + */ + i = 1; + } else { + /* Switch: '/Switch' incorporates: + * Constant: '/Constant1' + */ + i = -1; + } + + rtb_Add_be = (double)Gain / (double)Gain1 / 1000.0 * (double) + (rtDW.t_now - rtDW.UnitDelay_DSTATE_gu) * (double)i + (double) + rtDW.Blower_FL; + } + + /* End of Switch: '/Switch' */ + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * DataStoreWrite: '/Data Store Write5' + */ + rtDW.Blower_FR = (uint8_t)rtb_Add_be; + + /* DataStoreWrite: '/Data Store Write6' incorporates: + * DataStoreWrite: '/Data Store Write5' + */ + rtDW.Blower_FL = rtDW.Blower_FR; + + /* DataStoreWrite: '/Data Store Write7' incorporates: + * Constant: '/Recirc logic Partial REC' + */ + rtb_Add_be = 1.0; + + /* MATLAB Function: '/Time goto from step 2 to step 3 ' incorporates: + * DataStoreRead: '/Data Store Read4' + */ + Timegotofromstep2tostep3(rtDW.LEVEL, &Eva_Target); + + /* MATLAB Function: '/MATLAB Function1' incorporates: + * DataStoreRead: '/Data Store Read13' + * Gain: '/ ' + */ + MATLABFunction1_j(rtDW.t_now, (uint32_t)(1000 * Eva_Target), &eComp_stop, + &rtDW.sf_MATLABFunction1_j2); + + /* Switch: '/Switch1' incorporates: + * Constant: '/not LO or HI' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read11' + * DataStoreRead: '/Data Store Read12' + * Logic: '/Logical Operator' + * Logic: '/Logical Operator1' + * RelationalOperator: '/Relational Operator2' + * RelationalOperator: '/Relational Operator3' + * Switch: '/Switch' + */ + if ((rtDW.CCU_MODE_FL != 1) || (rtDW.LO_HI_MODE_FL != 0)) { + /* Merge: '/Merge' incorporates: + * Constant: '/exit algorithm' + */ + rtB.Merge_pe = 3; + } else if (eComp_stop || rtDW.HI_logic_on) { + /* Switch: '/Switch' incorporates: + * Constant: '/go to next step' + * Merge: '/Merge' + */ + rtB.Merge_pe = 3; + } else { + /* Merge: '/Merge' incorporates: + * Constant: '/stay at step' + * Switch: '/Switch' + */ + rtB.Merge_pe = 2; + } + + /* End of Switch: '/Switch1' */ + + /* Update for UnitDelay: '/Unit Delay' incorporates: + * DataStoreRead: '/ ' + */ + rtDW.UnitDelay_DSTATE_g = rtDW.t_now; + + /* Update for UnitDelay: '/Unit Delay' incorporates: + * DataStoreRead: '/ ' + */ + rtDW.UnitDelay_DSTATE_h = rtDW.t_now; + + /* Update for UnitDelay: '/Unit Delay' incorporates: + * DataStoreRead: '/ ' + */ + rtDW.UnitDelay_DSTATE_ly = rtDW.t_now; + + /* Update for UnitDelay: '/Unit Delay' incorporates: + * DataStoreRead: '/ ' + */ + rtDW.UnitDelay_DSTATE_gu = rtDW.t_now; + + /* End of Outputs for SubSystem: '/Level 5' */ + break; + } + + /* End of SwitchCase: '/Switch Case' */ + /* End of Outputs for SubSystem: '/Step 2 F' */ + break; + + case 3: + /* Outputs for IfAction SubSystem: '/Step 3 F' incorporates: + * ActionPort: '/Action Port' + */ + Step3F(&rtB.Merge_pe, &rtDW.start_control_finished_front); + + /* End of Outputs for SubSystem: '/Step 3 F' */ + break; + } + + /* End of SwitchCase: '/Switch Case' */ + + /* DataStoreWrite: '/Data Store Write' */ + rtDW.step_start_controle_front = rtB.Merge_pe; + + /* End of Outputs for SubSystem: '/Start Control Front' */ + } + + /* End of If: '/ SC front 2' */ + + /* Saturate: '/from 0 to 3' incorporates: + * Constant: '/Constant' + * Sum: '/Add' + * UnitDelay: '/Unit Delay' + */ + if (rtDW.UnitDelay_DSTATE_b + 1.0 > 3.0) { + rtDW.UnitDelay_DSTATE_b = 3.0; + } else if (rtDW.UnitDelay_DSTATE_b + 1.0 < 0.0) { + rtDW.UnitDelay_DSTATE_b = 0.0; + } else { + rtDW.UnitDelay_DSTATE_b++; + } + + /* End of Saturate: '/from 0 to 3' */ + + /* If: '/ SC front 3' incorporates: + * DataStoreRead: '/Data Store Read3' + * DataTypeConversion: '/Data Type Conversion1' + * DataTypeConversion: '/Data Type Conversion3' + * UnitDelay: '/Unit Delay' + */ + if (((uint8_t)rtDW.start_control_finished_rear == 0) && ((uint8_t) + rtDW.UnitDelay_DSTATE_b >= 2)) { + /* Outputs for IfAction SubSystem: '/Start Control Rear' incorporates: + * ActionPort: '/Action Port' + */ + /* SwitchCase: '/Switch Case' incorporates: + * DataStoreRead: '/Data Store Read' + */ + switch (rtDW.step_start_controle_rear) { + case -1: + /* Outputs for IfAction SubSystem: '/Step -1 R (Entry Condition)' incorporates: + * ActionPort: '/Action Port' + */ + /* SwitchCase: '/Switch Case' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + switch (rtDW.LEVEL) { + case 0: + /* Outputs for IfAction SubSystem: '/Level 0' incorporates: + * ActionPort: '/Action Port' + */ + /* MATLAB Function: '/g_ausSTART_ENTER_SETTEMP' incorporates: + * DataStoreRead: '/Data Store Read4' + */ + /* : out = int16(g_assSTART_ENTER_INCAR(LVL + 1 + 6)); */ + g_ausSTART_ENTER_SETTEMP_i(rtDW.LEVEL, &rtb_y_mz); + + /* MATLAB Function: '/g_assSTART_ENTER_INCAR' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + i = (int32_t)(rtDW.LEVEL + 1U); + if (rtDW.LEVEL + 1U > 255U) { + i = 255; + } + + index_start_0 = (int32_t)((uint32_t)i + 6U); + if ((uint32_t)i + 6U > 255U) { + index_start_0 = 255; + } + + /* Switch: '/Switch' incorporates: + * Constant: '/not LO or HI' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read5' + * Logic: '/AND' + * MATLAB Function: '/g_assSTART_ENTER_INCAR' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator1' + * RelationalOperator: '/Relational Operator2' + * RelationalOperator: '/Relational Operator3' + */ + if ((rtDW.Incar_RR > g_assSTART_ENTER_INCAR[index_start_0 - 1]) && + (rtDW.CCU_MODE_RR == 1) && (rtDW.CCU_SET_RR < rtb_y_mz) && + (rtDW.LO_HI_MODE_RR == 0)) { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant1' + */ + rtB.Merge_a0 = 1; + } else { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant' + */ + rtB.Merge_a0 = -1; + } + + /* End of Switch: '/Switch' */ + /* End of Outputs for SubSystem: '/Level 0' */ + break; + + case 1: + /* Outputs for IfAction SubSystem: '/Level 1' incorporates: + * ActionPort: '/Action Port' + */ + /* MATLAB Function: '/g_assSTART_ENTER_INCAR' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + g_assSTART_ENTER_INCAR_f(rtDW.LEVEL, &rtb_y_mz); + + /* MATLAB Function: '/g_ausSTART_ENTER_SETTEMP' incorporates: + * DataStoreRead: '/Data Store Read4' + */ + g_ausSTART_ENTER_SETTEMP_i(rtDW.LEVEL, &rtb_FLU_tg_correct); + + /* Switch: '/Switch' incorporates: + * Constant: '/not LO or HI' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read5' + * Logic: '/AND' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator1' + * RelationalOperator: '/Relational Operator2' + * RelationalOperator: '/Relational Operator3' + */ + if ((rtDW.Incar_RR > rtb_y_mz) && (rtDW.CCU_MODE_RR == 1) && + (rtDW.CCU_SET_RR < rtb_FLU_tg_correct) && (rtDW.LO_HI_MODE_RR == 0)) + { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant1' + */ + rtB.Merge_a0 = 1; + } else { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant' + */ + rtB.Merge_a0 = -1; + } + + /* End of Switch: '/Switch' */ + /* End of Outputs for SubSystem: '/Level 1' */ + break; + + case 2: + /* Outputs for IfAction SubSystem: '/Level 2' incorporates: + * ActionPort: '/Action Port' + */ + /* MATLAB Function: '/g_assSTART_ENTER_INCAR' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + g_assSTART_ENTER_INCAR_f(rtDW.LEVEL, &rtb_y_mz); + + /* MATLAB Function: '/g_ausSTART_ENTER_SETTEMP' incorporates: + * DataStoreRead: '/Data Store Read4' + */ + g_ausSTART_ENTER_SETTEMP_i(rtDW.LEVEL, &rtb_FLU_tg_correct); + + /* Switch: '/Switch' incorporates: + * Constant: '/LOW' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read5' + * Logic: '/AND' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator1' + * RelationalOperator: '/Relational Operator2' + * RelationalOperator: '/Relational Operator3' + */ + if ((rtDW.Incar_RR < rtb_y_mz) && (rtDW.CCU_MODE_RR == 1) && + (rtDW.CCU_SET_RR > rtb_FLU_tg_correct) && (rtDW.LO_HI_MODE_RR != 1)) + { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant1' + */ + rtB.Merge_a0 = 0; + } else { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant' + */ + rtB.Merge_a0 = -1; + } + + /* End of Switch: '/Switch' */ + /* End of Outputs for SubSystem: '/Level 2' */ + break; + + case 3: + /* Outputs for IfAction SubSystem: '/Level 3' incorporates: + * ActionPort: '/Action Port' + */ + /* MATLAB Function: '/g_assSTART_ENTER_INCAR' incorporates: + * DataStoreRead: '/Data Store Read4' + */ + g_assSTART_ENTER_INCAR_f(rtDW.LEVEL, &rtb_y_mz); + + /* MATLAB Function: '/g_assSTART_ENTER_COOLANT ' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + g_assSTART_ENTER_COOLANT_m1(rtDW.LEVEL, &rtb_FLU_tg_correct); + + /* MATLAB Function: '/g_ausSTART_ENTER_SETTEMP' incorporates: + * DataStoreRead: '/Data Store Read6' + */ + /* : out = int16(g_ausSTART_ENTER_SETTEMP(LVL+1+6)); */ + i = (int32_t)(rtDW.LEVEL + 1U); + if (rtDW.LEVEL + 1U > 255U) { + i = 255; + } + + index_start_0 = (int32_t)((uint32_t)i + 6U); + if ((uint32_t)i + 6U > 255U) { + index_start_0 = 255; + } + + rtb_out_h0 = g_ausSTART_ENTER_SETTEMP[index_start_0 - 1]; + if (rtb_out_h0 > 32767) { + rtb_out_h0 = 32767U; + } + + /* Switch: '/Switch' incorporates: + * Constant: '/LOW' + * DataStoreRead: '/Data Store Read' + * DataStoreRead: '/Data Store Read1' + * DataStoreRead: '/Data Store Read2' + * DataStoreRead: '/Data Store Read5' + * DataStoreRead: '/Data Store Read7' + * Logic: '/AND' + * Logic: '/AND1' + * MATLAB Function: '/g_ausSTART_ENTER_SETTEMP' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator1' + * RelationalOperator: '/Relational Operator2' + * RelationalOperator: '/Relational Operator3' + * RelationalOperator: '/Relational Operator4' + */ + if (((rtDW.Incar_RR < rtb_y_mz) || (rtDW.ECT < rtb_FLU_tg_correct)) && + (rtDW.CCU_MODE_RR == 1) && (rtDW.CCU_SET_RR > rtb_out_h0) && + (rtDW.LO_HI_MODE_RR != 1)) { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant1' + */ + rtB.Merge_a0 = 0; + } else { + /* Merge: '/Merge' incorporates: + * Constant: '/Constant' + */ + rtB.Merge_a0 = -1; + } + + /* End of Switch: '/Switch' */ + /* End of Outputs for SubSystem: '/Level 3' */ + break; + + case 4: + /* Outputs for IfAction SubSystem: '/Level 4' incorporates: + * ActionPort: '/Action Port' + */ + Level4_j(&rtB.Merge_a0, &rtDW.CCU_MODE_RR, &rtDW.ECT, &rtDW.Incar_RR, + &rtDW.LEVEL, &rtDW.LO_HI_MODE_RR); + + /* End of Outputs for SubSystem: '/Level 4' */ + break; + + case 5: + /* Outputs for IfAction SubSystem: '/Level 5' incorporates: + * ActionPort: '/Action Port' + */ + Level4_j(&rtB.Merge_a0, &rtDW.CCU_MODE_RR, &rtDW.ECT, &rtDW.Incar_RR, + &rtDW.LEVEL, &rtDW.LO_HI_MODE_RR); + + /* End of Outputs for SubSystem: '/Level 5' */ + break; + } + + /* End of SwitchCase: '/Switch Case' */ + /* End of Outputs for SubSystem: '/Step -1 R (Entry Condition)' */ + break; + + case 0: + /* Outputs for IfAction SubSystem: '/Step 0 R' incorporates: + * ActionPort: '/Action Port' + */ + /* SwitchCase: '/Switch Case' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + switch (rtDW.LEVEL) { + case 0: + /* Outputs for IfAction SubSystem: '/Level 0' incorporates: + * ActionPort: '/Action Port' + */ + Level0(&rtB.Merge_a0); + + /* End of Outputs for SubSystem: '/Level 0' */ + break; + + case 1: + /* Outputs for IfAction SubSystem: '/Level 1' incorporates: + * ActionPort: '/Action Port' + */ + Level0(&rtB.Merge_a0); + + /* End of Outputs for SubSystem: '/Level 1' */ + break; + + case 2: + /* Outputs for IfAction SubSystem: '/Level 2' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write5' incorporates: + * Constant: '/Constant2' + */ + rtDW.Blower_RR = 10U; + + /* DataStoreWrite: '/Data Store Write6' incorporates: + * Constant: '/Constant3' + */ + rtDW.Blower_RL = 10U; + + /* DataStoreWrite: '/Data Store Write10' incorporates: + * Constant: '/Constant4' + */ + rtDW.Dtg_RR = 650U; + + /* DataStoreWrite: '/Data Store Write11' incorporates: + * Constant: '/Constant4' + */ + rtDW.Dtg_RL = 650U; + + /* MATLAB Function: '/incar filter up' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + incarfilterup_j(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* MATLAB Function: '/incar filter down' incorporates: + * DataStoreRead: '/Data Store Read2' + */ + incarfilterdown_m(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/Mode - foot' + */ + rtDW.Mode_RR = 60U; + + /* DataStoreWrite: '/Data Store Write3' incorporates: + * Constant: '/Mode - foot' + */ + rtDW.Mode_RL = 60U; + + /* Switch: '/Switch1' incorporates: + * Constant: '/LO' + * DataStoreRead: '/Data Store Read11' + * DataStoreRead: '/Data Store Read12' + * Logic: '/Logical Operator1' + * RelationalOperator: '/Relational Operator2' + * RelationalOperator: '/Relational Operator3' + */ + /* : out = int16(g_assSTART_COOLANT_STEP0_TO_1(LVL + 3)); */ + if ((rtDW.CCU_MODE_RR != 1) || (rtDW.LO_HI_MODE_RR == 1)) { + /* Merge: '/Merge' incorporates: + * Constant: '/exit algorithm' + */ + rtB.Merge_a0 = 3; + } else { + /* MATLAB Function: '/g_assSTART_COOLANT_STEP0_TO_1 ' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + i = (int32_t)(rtDW.LEVEL + 3U); + if (rtDW.LEVEL + 3U > 255U) { + i = 255; + } + + /* Merge: '/Merge' incorporates: + * DataStoreRead: '/Engine coolant temp' + * MATLAB Function: '/g_assSTART_COOLANT_STEP0_TO_1 ' + * RelationalOperator: '/Relational Operator' + */ + rtB.Merge_a0 = (int8_t)(rtDW.ECT > g_assSTART_COOLANT_STEP0_TO_1[i - 1]); + } + + /* End of Switch: '/Switch1' */ + /* End of Outputs for SubSystem: '/Level 2' */ + break; + + case 3: + /* Outputs for IfAction SubSystem: '/Level 3' incorporates: + * ActionPort: '/Action Port' + */ + /* DataStoreWrite: '/Data Store Write5' incorporates: + * Constant: '/Constant2' + */ + rtDW.Blower_RR = 10U; + + /* DataStoreWrite: '/Data Store Write6' incorporates: + * Constant: '/Constant3' + */ + rtDW.Blower_RL = 10U; + + /* DataStoreWrite: '/Data Store Write10' incorporates: + * Constant: '/Constant4' + */ + rtDW.Dtg_RR = 650U; + + /* DataStoreWrite: '/Data Store Write11' incorporates: + * Constant: '/Constant4' + */ + rtDW.Dtg_RL = 650U; + + /* MATLAB Function: '/incar filter up' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + incarfilterup_j(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* MATLAB Function: '/incar filter down' incorporates: + * DataStoreRead: '/Data Store Read2' + */ + incarfilterdown_m(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* DataStoreWrite: '/Data Store Write2' incorporates: + * Constant: '/Mode - foot' + */ + rtDW.Mode_RR = 60U; + + /* DataStoreWrite: '/Data Store Write3' incorporates: + * Constant: '/Mode - foot' + */ + rtDW.Mode_RL = 60U; + + /* Merge: '/Merge' incorporates: + * SignalConversion generated from: '/step1' + */ + rtB.Merge_a0 = 0; + + /* MATLAB Function: '/g_assSTART_COOLANT_STEP0_TO_1 ' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + g_assSTART_COOLANT_STEP0_TO_1_j(rtDW.LEVEL, &rtb_y_mz); + + /* End of Outputs for SubSystem: '/Level 3' */ + break; + + case 4: + /* Outputs for IfAction SubSystem: '/Level 4' incorporates: + * ActionPort: '/Action Port' + */ + Level4_h(&rtB.Merge_a0, &rtDW.Blower_RL, &rtDW.Blower_RR, + &rtDW.CCU_MODE_RR, &rtDW.Dtg_RL, &rtDW.Dtg_RR, &rtDW.ECT, + &EN_BATTChiller, &Comp_Max_RPM_Allowed, &rtDW.LEVEL, + &rtDW.LO_HI_MODE_RR, &rtDW.Mode_RL, &rtDW.Mode_RR, + &ShutOffRear_EN, &ShutOffFront_EN); + + /* End of Outputs for SubSystem: '/Level 4' */ + break; + + case 5: + /* Outputs for IfAction SubSystem: '/Level 5' incorporates: + * ActionPort: '/Action Port' + */ + Level4_h(&rtB.Merge_a0, &rtDW.Blower_RL, &rtDW.Blower_RR, + &rtDW.CCU_MODE_RR, &rtDW.Dtg_RL, &rtDW.Dtg_RR, &rtDW.ECT, + &EN_BATTChiller, &Comp_Max_RPM_Allowed, &rtDW.LEVEL, + &rtDW.LO_HI_MODE_RR, &rtDW.Mode_RL, &rtDW.Mode_RR, + &ShutOffRear_EN, &ShutOffFront_EN); + + /* End of Outputs for SubSystem: '/Level 5' */ + break; + } + + /* End of SwitchCase: '/Switch Case' */ + /* End of Outputs for SubSystem: '/Step 0 R' */ + break; + + case 1: + /* Outputs for IfAction SubSystem: '/Step 1 R' incorporates: + * ActionPort: '/Action Port' + */ + /* SwitchCase: '/Switch Case' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + switch (rtDW.LEVEL) { + case 0: + /* Outputs for IfAction SubSystem: '/Level 0' incorporates: + * ActionPort: '/Action Port' + */ + Level0_g(&rtB.Merge_a0, &rtDW.Blower_RL, &rtDW.Blower_RR, + &rtDW.CCU_MODE_RR, &rtDW.Dtg_RL, &rtDW.Dtg_RR, &rtDW.Incar_RR, + &EN_BATTChiller, &Comp_Max_RPM_Allowed, &rtDW.LEVEL, + &rtDW.LO_HI_MODE_RR, &rtDW.Mode_RL, &rtDW.Mode_RR, &rtb_Add_be, + &ShutOffRear_EN, &rtDW.t_now, &rtDW.Level0_gj); + + /* End of Outputs for SubSystem: '/Level 0' */ + break; + + case 1: + /* Outputs for IfAction SubSystem: '/Level 1' incorporates: + * ActionPort: '/Action Port' + */ + Level0_g(&rtB.Merge_a0, &rtDW.Blower_RL, &rtDW.Blower_RR, + &rtDW.CCU_MODE_RR, &rtDW.Dtg_RL, &rtDW.Dtg_RR, &rtDW.Incar_RR, + &EN_BATTChiller, &Comp_Max_RPM_Allowed, &rtDW.LEVEL, + &rtDW.LO_HI_MODE_RR, &rtDW.Mode_RL, &rtDW.Mode_RR, &rtb_Add_be, + &ShutOffRear_EN, &rtDW.t_now, &rtDW.Level1_l); + + /* End of Outputs for SubSystem: '/Level 1' */ + break; + + case 2: + /* Outputs for IfAction SubSystem: '/Level 2' incorporates: + * ActionPort: '/Action Port' + */ + /* MATLAB Function: '/2 way valve' incorporates: + * DataStoreRead: '/Data Store Read6' + */ + uwayvalve(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* MATLAB Function: '/incar filter up' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + incarfilterup_j(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* MATLAB Function: '/incar filter down' incorporates: + * DataStoreRead: '/Data Store Read2' + */ + incarfilterdown_m(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* MATLAB Function: '/mode rear step 1' incorporates: + * DataStoreRead: '/Data Store Read5' + */ + moderearstep1(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* DataStoreWrite: '/Data Store Write2' */ + rtDW.Mode_RR = Comp_Max_RPM_Allowed; + + /* DataStoreWrite: '/Data Store Write3' */ + rtDW.Mode_RL = Comp_Max_RPM_Allowed; + + /* MATLAB Function: '/blower start finish' incorporates: + * DataStoreRead: '/Data Store Read7' + */ + blowerstartfinish(rtDW.LEVEL, rtb_out_gx); + + /* MATLAB Function: '/ECT min max' */ + /* : min = int16(g_assSTART_COOLANT_STEP0_TO_1(5)); */ + /* : max = int16(g_assSTART_COOLANT_TO_STEP2(2)); */ + /* : out = [min, max]; */ + rtb_out_knd[0] = g_assSTART_COOLANT_STEP0_TO_1[4]; + rtb_out_knd[1] = g_assSTART_COOLANT_TO_STEP2[1]; + + /* Lookup_n-D: '/blower ECT' incorporates: + * DataStoreRead: '/engine coolant temp' + */ + rtb_y_mz = look1_is16lu64n32tu16Ds32Is16_binlcs(rtDW.ECT, rtb_out_knd, + rtb_out_gx, 1U); + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * DataStoreWrite: '/Data Store Write5' + * DataTypeConversion: '/Data Type Conversion1' + */ + rtDW.Blower_RR = (uint8_t)rtb_y_mz; + + /* DataStoreWrite: '/Data Store Write6' incorporates: + * DataStoreWrite: '/Data Store Write5' + */ + rtDW.Blower_RL = rtDW.Blower_RR; + + /* MATLAB Function: '/Dtg_rear' incorporates: + * DataStoreRead: '/Data Store Read8' + */ + Dtg_rear(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* Gain: '/Gain' incorporates: + * DataStoreWrite: '/Data Store Write10' + */ + rtDW.Dtg_RR = (uint16_t)(10U * Comp_Max_RPM_Allowed); + + /* DataStoreWrite: '/Data Store Write11' incorporates: + * DataStoreWrite: '/Data Store Write10' + */ + rtDW.Dtg_RL = rtDW.Dtg_RR; + + /* MATLAB Function: '/Incar temp goto from step 1 to step 2 ' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + Incartempgotofromstep1tostep2_m(rtDW.LEVEL, &rtb_FLU_tg_correct); + + /* MATLAB Function: '/Time goto from step 1 to step 2 ' incorporates: + * DataStoreRead: '/Data Store Read4' + */ + Timegotofromstep1tostep2_n(rtDW.LEVEL, &rtb_y_mz); + + /* MATLAB Function: '/MATLAB Function1' incorporates: + * DataStoreRead: '/Data Store Read9' + * Gain: '/ ' + */ + MATLABFunction1(rtDW.t_now, (uint16_t)(1000 * rtb_y_mz), &eComp_stop, + &rtDW.sf_MATLABFunction1_m3); + + /* Switch: '/Switch1' incorporates: + * Constant: '/LO' + * DataStoreRead: '/Data Store Read11' + * DataStoreRead: '/Data Store Read12' + * DataStoreRead: '/engine coolant temp' + * DataStoreRead: '/incar temp' + * Logic: '/Logical Operator' + * Logic: '/Logical Operator1' + * MATLAB Function: '/g_assSTART_COOLANT_TO_STEP2 ' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator2' + * RelationalOperator: '/Relational Operator3' + * RelationalOperator: '/Relational Operator4' + * Switch: '/Switch' + */ + /* : out = int16(g_assSTART_COOLANT_TO_STEP2(2)); */ + if ((rtDW.CCU_MODE_RR != 1) || (rtDW.LO_HI_MODE_RR == 1)) { + /* Merge: '/Merge' incorporates: + * Constant: '/exit algorithm' + */ + rtB.Merge_a0 = 3; + } else if ((rtDW.Incar_RR > rtb_FLU_tg_correct) || eComp_stop || + (rtDW.ECT > g_assSTART_COOLANT_TO_STEP2[1])) { + /* Switch: '/Switch' incorporates: + * Constant: '/go to next step' + * Merge: '/Merge' + */ + rtB.Merge_a0 = 2; + } else { + /* Merge: '/Merge' incorporates: + * Constant: '/stay at step 1' + * Switch: '/Switch' + */ + rtB.Merge_a0 = 1; + } + + /* End of Switch: '/Switch1' */ + /* End of Outputs for SubSystem: '/Level 2' */ + break; + + case 3: + /* Outputs for IfAction SubSystem: '/Level 3' incorporates: + * ActionPort: '/Action Port' + */ + /* MATLAB Function: '/2 way valve' incorporates: + * DataStoreRead: '/Data Store Read6' + */ + uwayvalve(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* MATLAB Function: '/incar filter up' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + incarfilterup_j(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* MATLAB Function: '/incar filter down' incorporates: + * DataStoreRead: '/Data Store Read2' + */ + incarfilterdown_m(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* MATLAB Function: '/mode rear step 1' incorporates: + * DataStoreRead: '/Data Store Read5' + */ + moderearstep1(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* DataStoreWrite: '/Data Store Write2' */ + rtDW.Mode_RR = Comp_Max_RPM_Allowed; + + /* DataStoreWrite: '/Data Store Write3' */ + rtDW.Mode_RL = Comp_Max_RPM_Allowed; + + /* MATLAB Function: '/blower start finish' incorporates: + * DataStoreRead: '/Data Store Read7' + */ + blowerstartfinish(rtDW.LEVEL, rtb_out_gx); + + /* MATLAB Function: '/ECT min max' incorporates: + * DataStoreRead: '/Data Store Read7' + */ + ECTminmax_j(rtDW.LEVEL, rtb_out_knd); + + /* Lookup_n-D: '/blower ECT' incorporates: + * DataStoreRead: '/engine coolant temp' + */ + rtb_y_mz = look1_is16lu64n32tu16Ds32Is16_binlcs(rtDW.ECT, rtb_out_knd, + rtb_out_gx, 1U); + + /* DataTypeConversion: '/Data Type Conversion' incorporates: + * DataStoreWrite: '/Data Store Write5' + * DataTypeConversion: '/Data Type Conversion1' + */ + rtDW.Blower_RR = (uint8_t)rtb_y_mz; + + /* DataStoreWrite: '/Data Store Write6' incorporates: + * DataStoreWrite: '/Data Store Write5' + */ + rtDW.Blower_RL = rtDW.Blower_RR; + + /* MATLAB Function: '/Dtg_rear' incorporates: + * DataStoreRead: '/Data Store Read8' + */ + Dtg_rear(rtDW.LEVEL, &Comp_Max_RPM_Allowed); + + /* Gain: '/Gain' incorporates: + * DataStoreWrite: '/Data Store Write10' + */ + rtDW.Dtg_RR = (uint16_t)(10U * Comp_Max_RPM_Allowed); + + /* DataStoreWrite: '/Data Store Write11' incorporates: + * DataStoreWrite: '/Data Store Write10' + */ + rtDW.Dtg_RL = rtDW.Dtg_RR; + + /* MATLAB Function: '/Incar temp goto from step 1 to step 2 ' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + Incartempgotofromstep1tostep2_m(rtDW.LEVEL, &rtb_FLU_tg_correct); + + /* MATLAB Function: '/Time goto from step 1 to step 2 ' incorporates: + * DataStoreRead: '/Data Store Read4' + */ + Timegotofromstep1tostep2_n(rtDW.LEVEL, &rtb_y_mz); + + /* MATLAB Function: '/MATLAB Function1' incorporates: + * DataStoreRead: '/Data Store Read9' + * Gain: '/ ' + */ + MATLABFunction1(rtDW.t_now, (uint16_t)(1000 * rtb_y_mz), &eComp_stop, + &rtDW.sf_MATLABFunction1_c); + + /* Switch: '/Switch1' incorporates: + * Constant: '/LO' + * DataStoreRead: '/Data Store Read11' + * DataStoreRead: '/Data Store Read12' + * DataStoreRead: '/engine coolant temp' + * DataStoreRead: '/incar temp' + * Logic: '/Logical Operator' + * Logic: '/Logical Operator1' + * MATLAB Function: '/g_assSTART_COOLANT_TO_STEP2 ' + * RelationalOperator: '/Relational Operator' + * RelationalOperator: '/Relational Operator2' + * RelationalOperator: '/Relational Operator3' + * RelationalOperator: '/Relational Operator4' + * Switch: '/Switch' + */ + /* : out = int16(g_assSTART_COOLANT_TO_STEP2(3)); */ + if ((rtDW.CCU_MODE_RR != 1) || (rtDW.LO_HI_MODE_RR == 1)) { + /* Merge: '/Merge' incorporates: + * Constant: '/exit algorithm' + */ + rtB.Merge_a0 = 3; + } else if ((rtDW.Incar_RR > rtb_FLU_tg_correct) || eComp_stop || + (rtDW.ECT > g_assSTART_COOLANT_TO_STEP2[2])) { + /* Switch: '/Switch' incorporates: + * Constant: '/go to next step' + * Merge: '/Merge' + */ + rtB.Merge_a0 = 2; + } else { + /* Merge: '/Merge' incorporates: + * Constant: '/stay at step 1' + * Switch: '/Switch' + */ + rtB.Merge_a0 = 1; + } + + /* End of Switch: '/Switch1' */ + /* End of Outputs for SubSystem: '/Level 3' */ + break; + + case 4: + /* Outputs for IfAction SubSystem: '/Level 4' incorporates: + * ActionPort: '/Action Port' + */ + Level4_m(&rtB.Merge_a0, &rtDW.Blower_RL, &rtDW.Blower_RR, + &rtDW.CCU_MODE_RR, &rtDW.Dtg_RL, &rtDW.Dtg_RR, &rtDW.ECT, + &rtDW.Incar_RR, &EN_BATTChiller, &Comp_Max_RPM_Allowed, + &rtDW.LEVEL, &rtDW.LO_HI_MODE_RR, &rtDW.Mode_RL, &rtDW.Mode_RR, + &rtb_Add_be, &ShutOffRear_EN, &rtDW.t_now, &rtDW.Level4_m5); + + /* End of Outputs for SubSystem: '/Level 4' */ + break; + + case 5: + /* Outputs for IfAction SubSystem: '/Level 5' incorporates: + * ActionPort: '/Action Port' + */ + Level4_m(&rtB.Merge_a0, &rtDW.Blower_RL, &rtDW.Blower_RR, + &rtDW.CCU_MODE_RR, &rtDW.Dtg_RL, &rtDW.Dtg_RR, &rtDW.ECT, + &rtDW.Incar_RR, &EN_BATTChiller, &Comp_Max_RPM_Allowed, + &rtDW.LEVEL, &rtDW.LO_HI_MODE_RR, &rtDW.Mode_RL, &rtDW.Mode_RR, + &rtb_Add_be, &ShutOffRear_EN, &rtDW.t_now, &rtDW.Level5_i); + + /* End of Outputs for SubSystem: '/Level 5' */ + break; + } + + /* End of SwitchCase: '/Switch Case' */ + /* End of Outputs for SubSystem: '/Step 1 R' */ + break; + + case 2: + /* Outputs for IfAction SubSystem: '/Step 2 R' incorporates: + * ActionPort: '/Action Port' + */ + /* SwitchCase: '/Switch Case' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + switch (rtDW.LEVEL) { + case 0: + /* Outputs for IfAction SubSystem: '/Level 0' incorporates: + * ActionPort: '/Action Port' + */ + Level0_a(&rtB.Merge_a0, &rtDW.Blower_RL, &rtDW.Blower_RR, + &rtDW.Blower_logic_RR, &rtDW.CCU_MODE_FL, &rtDW.Dtg_RL, + &rtDW.Dtg_RR, &rtb_y_mz, &EN_BATTChiller, &Comp_Max_RPM_Allowed, + &rtDW.LEVEL, &rtDW.LO_HI_MODE_FL, &rtDW.Mode_RL, &rtDW.Mode_RR, + &rtDW.Mode_logic_RR, &rtb_Add_be, &ShutOffRear_EN, &rtDW.t_now, + &rtDW.Level0_ad); + + /* End of Outputs for SubSystem: '/Level 0' */ + break; + + case 1: + /* Outputs for IfAction SubSystem: '/Level 1' incorporates: + * ActionPort: '/Action Port' + */ + Level0_a(&rtB.Merge_a0, &rtDW.Blower_RL, &rtDW.Blower_RR, + &rtDW.Blower_logic_RR, &rtDW.CCU_MODE_FL, &rtDW.Dtg_RL, + &rtDW.Dtg_RR, &rtb_y_mz, &EN_BATTChiller, &Comp_Max_RPM_Allowed, + &rtDW.LEVEL, &rtDW.LO_HI_MODE_FL, &rtDW.Mode_RL, &rtDW.Mode_RR, + &rtDW.Mode_logic_RR, &rtb_Add_be, &ShutOffRear_EN, &rtDW.t_now, + &rtDW.Level1_hm); + + /* End of Outputs for SubSystem: '/Level 1' */ + break; + + case 2: + /* Outputs for IfAction SubSystem: '/Level 2' incorporates: + * ActionPort: '/Action Port' + */ + Level2_f(&rtB.Merge_a0, &rtDW.Blower_RL, &rtDW.Blower_RR, + &rtDW.Blower_logic_RR, &rtDW.CCU_MODE_FL, &rtDW.Dtg_RL, + &rtDW.Dtg_RR, &rtb_y_mz, &rtDW.HI_logic_on, &EN_BATTChiller, + &Comp_Max_RPM_Allowed, &rtDW.LEVEL, &rtDW.LO_HI_MODE_FL, + &rtDW.Mode_RL, &rtDW.Mode_RR, &rtDW.Mode_logic_RR, &rtb_Add_be, + &ShutOffRear_EN, &rtDW.t_now, &rtDW.Level2_f0); + + /* End of Outputs for SubSystem: '/Level 2' */ + break; + + case 3: + /* Outputs for IfAction SubSystem: '/Level 3' incorporates: + * ActionPort: '/Action Port' + */ + Level2_f(&rtB.Merge_a0, &rtDW.Blower_RL, &rtDW.Blower_RR, + &rtDW.Blower_logic_RR, &rtDW.CCU_MODE_FL, &rtDW.Dtg_RL, + &rtDW.Dtg_RR, &rtb_y_mz, &rtDW.HI_logic_on, &EN_BATTChiller, + &Comp_Max_RPM_Allowed, &rtDW.LEVEL, &rtDW.LO_HI_MODE_FL, + &rtDW.Mode_RL, &rtDW.Mode_RR, &rtDW.Mode_logic_RR, &rtb_Add_be, + &ShutOffRear_EN, &rtDW.t_now, &rtDW.Level3_p); + + /* End of Outputs for SubSystem: '/Level 3' */ + break; + + case 4: + /* Outputs for IfAction SubSystem: '/Level 4' incorporates: + * ActionPort: '/Action Port' + */ + Level2_f(&rtB.Merge_a0, &rtDW.Blower_RL, &rtDW.Blower_RR, + &rtDW.Blower_logic_RR, &rtDW.CCU_MODE_FL, &rtDW.Dtg_RL, + &rtDW.Dtg_RR, &rtb_y_mz, &rtDW.HI_logic_on, &EN_BATTChiller, + &Comp_Max_RPM_Allowed, &rtDW.LEVEL, &rtDW.LO_HI_MODE_FL, + &rtDW.Mode_RL, &rtDW.Mode_RR, &rtDW.Mode_logic_RR, &rtb_Add_be, + &ShutOffRear_EN, &rtDW.t_now, &rtDW.Level4_b); + + /* End of Outputs for SubSystem: '/Level 4' */ + break; + + case 5: + /* Outputs for IfAction SubSystem: '/Level 5' incorporates: + * ActionPort: '/Action Port' + */ + Level2_f(&rtB.Merge_a0, &rtDW.Blower_RL, &rtDW.Blower_RR, + &rtDW.Blower_logic_RR, &rtDW.CCU_MODE_FL, &rtDW.Dtg_RL, + &rtDW.Dtg_RR, &rtb_y_mz, &rtDW.HI_logic_on, &EN_BATTChiller, + &Comp_Max_RPM_Allowed, &rtDW.LEVEL, &rtDW.LO_HI_MODE_FL, + &rtDW.Mode_RL, &rtDW.Mode_RR, &rtDW.Mode_logic_RR, &rtb_Add_be, + &ShutOffRear_EN, &rtDW.t_now, &rtDW.Level5_ph); + + /* End of Outputs for SubSystem: '/Level 5' */ + break; + } + + /* End of SwitchCase: '/Switch Case' */ + /* End of Outputs for SubSystem: '/Step 2 R' */ + break; + + case 3: + /* Outputs for IfAction SubSystem: '/Step 3 R' incorporates: + * ActionPort: '/Action Port' + */ + Step3F(&rtB.Merge_a0, &rtDW.start_control_finished_front); + + /* End of Outputs for SubSystem: '/Step 3 R' */ + break; + } + + /* End of SwitchCase: '/Switch Case' */ + + /* DataStoreWrite: '/Data Store Write' */ + rtDW.step_start_controle_rear = rtB.Merge_a0; + + /* End of Outputs for SubSystem: '/Start Control Rear' */ + } + + /* End of If: '/ SC front 3' */ + + /* If: '/If' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + if (rtb_DataTypeConversion3_i > 0) { + /* Outputs for IfAction SubSystem: '/all zone sync' incorporates: + * ActionPort: '/Action Port' + */ + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write' + */ + rtDW.CCU_SET_FR = rtDW.CCU_SET_FL; + + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write1' + */ + rtDW.CCU_SET_RL = rtDW.CCU_SET_FL; + + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write2' + */ + rtDW.CCU_SET_RR = rtDW.CCU_SET_FL; + + /* DataStoreWrite: '/Data Store Write3' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + rtDW.CCU_BLOWERS_FR = rtDW.CCU_BLOWERS_FL; + + /* DataStoreWrite: '/Data Store Write4' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + rtDW.CCU_BLOWERS_RL = rtDW.CCU_BLOWERS_FL; + + /* DataStoreWrite: '/Data Store Write5' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + rtDW.CCU_BLOWERS_RR = rtDW.CCU_BLOWERS_FL; + + /* DataStoreWrite: '/Data Store Write6' incorporates: + * DataStoreRead: '/Data Store Read2' + */ + rtDW.CCU_DEF_FR = rtDW.CCU_DEF_FL; + + /* DataStoreWrite: '/Data Store Write10' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + rtDW.CCU_FACE_RL = rtDW.CCU_FACE_FL; + + /* DataStoreWrite: '/Data Store Write11' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + rtDW.CCU_FACE_RR = rtDW.CCU_FACE_FL; + + /* DataStoreWrite: '/Data Store Write9' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + rtDW.CCU_FACE_FR = rtDW.CCU_FACE_FL; + + /* DataStoreWrite: '/Data Store Write12' incorporates: + * DataStoreRead: '/Data Store Read4' + */ + rtDW.CCU_FOOT_FR = rtDW.CCU_FOOT_FL; + + /* DataStoreWrite: '/Data Store Write13' incorporates: + * DataStoreRead: '/Data Store Read4' + */ + rtDW.CCU_FOOT_RL = rtDW.CCU_FOOT_FL; + + /* DataStoreWrite: '/Data Store Write14' incorporates: + * DataStoreRead: '/Data Store Read4' + */ + rtDW.CCU_FOOT_RR = rtDW.CCU_FOOT_FL; + + /* DataStoreWrite: '/Data Store Write15' incorporates: + * DataStoreRead: '/Data Store Read5' + */ + rtDW.CCU_MODE_RR = rtDW.CCU_MODE_FL; + + /* DataStoreWrite: '/Data Store Write7' incorporates: + * DataStoreRead: '/Data Store Read5' + */ + rtDW.CCU_MODE_FR = rtDW.CCU_MODE_FL; + + /* DataStoreWrite: '/Data Store Write8' incorporates: + * DataStoreRead: '/Data Store Read5' + */ + rtDW.CCU_MODE_RL = rtDW.CCU_MODE_FL; + + /* DataStoreWrite: '/Data Store Write16' incorporates: + * DataStoreRead: '/Data Store Read6' + */ + rtDW.CCU_AUTOMODE_FR = rtDW.CCU_AUTOMODE_FL; + + /* DataStoreWrite: '/Data Store Write17' incorporates: + * DataStoreRead: '/Data Store Read6' + */ + rtDW.CCU_AUTOMODE_RL = rtDW.CCU_AUTOMODE_FL; + + /* DataStoreWrite: '/Data Store Write18' incorporates: + * DataStoreRead: '/Data Store Read6' + */ + rtDW.CCU_AUTOMODE_RR = rtDW.CCU_AUTOMODE_FL; + + /* DataStoreWrite: '/Data Store Write19' incorporates: + * DataStoreRead: '/Data Store Read7' + */ + rtDW.CCU_AC_REAR = rtDW.CCU_AC_FRONT; + + /* End of Outputs for SubSystem: '/all zone sync' */ + } + + /* End of If: '/If' */ + + /* If: '/If1' incorporates: + * DataStoreRead: '/Data Store Read2' + */ + if (CCU_FRONT_SYNC > 0) { + /* Outputs for IfAction SubSystem: '/front sync' incorporates: + * ActionPort: '/Action Port' + */ + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write' + */ + rtDW.CCU_SET_FR = rtDW.CCU_SET_FL; + + /* DataStoreWrite: '/Data Store Write3' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + rtDW.CCU_BLOWERS_FR = rtDW.CCU_BLOWERS_FL; + + /* DataStoreWrite: '/Data Store Write6' incorporates: + * DataStoreRead: '/Data Store Read2' + */ + rtDW.CCU_DEF_FR = rtDW.CCU_DEF_FL; + + /* DataStoreWrite: '/Data Store Write9' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + rtDW.CCU_FACE_FR = rtDW.CCU_FACE_FL; + + /* DataStoreWrite: '/Data Store Write12' incorporates: + * DataStoreRead: '/Data Store Read4' + */ + rtDW.CCU_FOOT_FR = rtDW.CCU_FOOT_FL; + + /* DataStoreWrite: '/Data Store Write7' incorporates: + * DataStoreRead: '/Data Store Read5' + */ + rtDW.CCU_MODE_FR = rtDW.CCU_MODE_FL; + + /* DataStoreWrite: '/Data Store Write16' incorporates: + * DataStoreRead: '/Data Store Read6' + */ + rtDW.CCU_AUTOMODE_FR = rtDW.CCU_AUTOMODE_FL; + + /* End of Outputs for SubSystem: '/front sync' */ + } + + /* End of If: '/If1' */ + + /* If: '/If2' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + if (rtb_timer_out > 0) { + /* Outputs for IfAction SubSystem: '/rear sync' incorporates: + * ActionPort: '/Action Port' + */ + /* DataTypeConversion: '/Data Type Conversion1' incorporates: + * DataStoreRead: '/Data Store Read' + * DataStoreWrite: '/Data Store Write2' + */ + rtDW.CCU_SET_RL = rtDW.CCU_SET_RR; + + /* DataStoreWrite: '/Data Store Write4' incorporates: + * DataStoreRead: '/Data Store Read1' + */ + rtDW.CCU_BLOWERS_RL = rtDW.CCU_BLOWERS_RR; + + /* DataStoreWrite: '/Data Store Write17' incorporates: + * DataStoreRead: '/Data Store Read2' + */ + rtDW.CCU_AUTOMODE_RL = rtDW.CCU_AUTOMODE_RR; + + /* DataStoreWrite: '/Data Store Write10' incorporates: + * DataStoreRead: '/Data Store Read3' + */ + rtDW.CCU_FACE_RL = rtDW.CCU_FACE_RR; + + /* DataStoreWrite: '/Data Store Write13' incorporates: + * DataStoreRead: '/Data Store Read4' + */ + rtDW.CCU_FOOT_RL = rtDW.CCU_FOOT_RR; + + /* DataStoreWrite: '/Data Store Write15' incorporates: + * DataStoreRead: '/Data Store Read5' + */ + rtDW.CCU_MODE_RL = rtDW.CCU_MODE_RR; + + /* End of Outputs for SubSystem: '/rear sync' */ + } + + /* End of If: '/If2' */ + + /* Update for Memory: '/Memory1' */ + rtDW.MemComp_I_Value = rtb_Gain1_f; + + /* Update for Memory: '/pError' */ + rtDW.pError_PreviousInput = Evap_Target_Offset; + + /* Update for UnitDelay: '/Unit Delay' incorporates: + * DataStoreRead: '/Data Store Read6' + */ + rtDW.UnitDelay_DSTATE_fq = rtb_y_jh; + + /* Update for UnitDelay: '/Unit Delay1' incorporates: + * DataStoreRead: '/Data Store Read7' + */ + rtDW.UnitDelay1_DSTATE = rtDW.Duct_RR_Tg; + + /* Update for UnitDelay: '/Cond_prev_private ' */ + rtDW.Cond_prev_private_DSTATE = rtb_FailCond_a; + + /* Update for UnitDelay: '/Cond_prev_private ' */ + rtDW.Cond_prev_private_DSTATE_p = rtb_Compare_edx; + + /* Update for UnitDelay: '/Cond_prev_private ' */ + rtDW.Cond_prev_private_DSTATE_a = rtb_Compare_e1; + + /* Update for UnitDelay: '/Cond_prev_private ' */ + rtDW.Cond_prev_private_DSTATE_h = rtb_LogicalOperator1; + + /* Update for UnitDelay: '/Cond_prev_private ' */ + rtDW.Cond_prev_private_DSTATE_c = rtb_LogicalOperator1_dv; + + /* Update for UnitDelay: '/Cond_prev_private ' */ + rtDW.Cond_prev_private_DSTATE_m = rtb_LogicalOperator1_n; + + /* Update for UnitDelay: '/Cond_prev_private ' */ + rtDW.Cond_prev_private_DSTATE_j = rtb_FailCond_kd; + + /* Update for UnitDelay: '/Cond_prev_private ' */ + rtDW.Cond_prev_private_DSTATE_f = rtb_FailCond_d; + + /* Update for UnitDelay: '/Cond_prev_private ' */ + rtDW.Cond_prev_private_DSTATE_cn = rtb_FailCond_ad; + + /* Update for UnitDelay: '/Cond_prev_private ' */ + rtDW.Cond_prev_private_DSTATE_l = rtb_Compare_g2; + + /* Update for UnitDelay: '/Cond_prev_private ' */ + rtDW.Cond_prev_private_DSTATE_ja = rtb_Compare_fh; + + /* Update for UnitDelay: '/Cond_prev_private ' */ + rtDW.Cond_prev_private_DSTATE_g = rtb_Compare_ipf; + + /* Update for UnitDelay: '/Cond_prev_private ' */ + rtDW.Cond_prev_private_DSTATE_cd = rtb_Compare_pb; + + /* Update for UnitDelay: '/Unit Delay' incorporates: + * DataStoreWrite: '/Data Store Write1' + */ + rtDW.UnitDelay_DSTATE_cbr = rtDW.Incar_FL; + + /* Update for UnitDelay: '/Unit Delay' incorporates: + * DataStoreWrite: '/Data Store Write3' + */ + rtDW.UnitDelay_DSTATE_j = rtDW.Incar_FR; + + /* Update for UnitDelay: '/Unit Delay' incorporates: + * DataStoreWrite: '/Data Store Write4' + */ + rtDW.UnitDelay_DSTATE_cs = rtDW.Incar_RL; + + /* Update for UnitDelay: '/Unit Delay' incorporates: + * DataStoreWrite: '/Data Store Write5' + */ + rtDW.UnitDelay_DSTATE_k2 = rtDW.Incar_RR; + + /* Update for UnitDelay: '/Cond_prev_private ' */ + rtDW.Cond_prev_private_DSTATE_k = rtb_Compare_i5; + + /* Update for UnitDelay: '/Cond_prev_private ' */ + rtDW.Cond_prev_private_DSTATE_d = rtb_FailCond_jb; + + /* Update for UnitDelay: '/Cond_prev_private ' */ + rtDW.Cond_prev_private_DSTATE_hw = rtb_FailCond_e; + + /* Update for UnitDelay: '/Cond_prev_private ' */ + rtDW.Cond_prev_private_DSTATE_i = rtb_FailCond_l; + + /* Update for UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + rtDW.DelayInput1_DSTATE = rtB.out_auto_h; + + /* Update for UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + rtDW.DelayInput1_DSTATE_e = rtB.out_auto_e; + + /* Update for UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + rtDW.DelayInput1_DSTATE_d = rtB.out_auto_hx; + + /* Update for UnitDelay: '/Delay Input1' + * + * Block description for '/Delay Input1': + * + * Store in Global RAM + */ + rtDW.DelayInput1_DSTATE_d3 = rtB.out_auto; + + /* Update for UnitDelay: '/Unit Delay' incorporates: + * DataStoreWrite: '/Data Store Write' + */ + rtDW.UnitDelay_DSTATE_cu = rtDW.AMB; + + /* Update for Memory: '/pError' */ + rtDW.pError_PreviousInput_g = Eva_F_tg; + + /* Update for Memory: '/pError' */ + rtDW.pError_PreviousInput_p = Eva_R_tg; + + /* Update for Memory: '/pError' */ + rtDW.pError_PreviousInput_pe = rtb_FLU_tg_correct_aa; + + /* Update for Memory: '/pError' */ + rtDW.pError_PreviousInput_i = rtb_MultiportSwitch_jq; + + /* Update for Memory: '/pError' */ + rtDW.pError_PreviousInput_b = rtb_MultiportSwitch_fu; + + /* Update for Memory: '/pError' */ + rtDW.pError_PreviousInput_d = rtb_Bias5; +} + +/* Model initialize function */ +void HVAC_model_initialize(void) +{ + /* Registration code */ + + /* initialize error status */ + rtmSetErrorStatus(rtM, (NULL)); + + /* block I/O */ + (void) memset(((void *) &rtB), 0, + sizeof(B)); + + /* states (dwork) */ + (void) memset((void *)&rtDW, 0, + sizeof(DW)); + + /* exported global states */ + Actuator_Ch0_Command_Model = HVAC_model_rtZActuatorCmdBus; + Actuator_Ch1_Command_Model = HVAC_model_rtZActuatorCmdBus; + Actuator_Ch2_Command_Model = HVAC_model_rtZActuatorCmdBus; + Actuator_Ch0_Status_Model = HVAC_model_rtZActuatorCmdBusInput; + Actuator_Ch1_Status_Model = HVAC_model_rtZActuatorCmdBusInput; + Actuator_Ch2_Status_Model = HVAC_model_rtZActuatorCmdBusInput; + Status_Sensor_Model = HVAC_model_rtZCmdBusStatus; + CCU_Errors_Model = HVAC_model_rtZCmdBusError; + PWM_Get = HVAC_model_rtZCmdBusPWMGet; + + { + int32_t i; + + /* Start for DataStoreMemory: '/Data Store Memory' */ + rtDW.Temp_FL_store = -9999.0; + + /* Start for DataStoreMemory: '/Data Store Memory10' */ + rtDW.Temp_RR_store = -9999.0; + + /* Start for DataStoreMemory: '/Data Store Memory4' */ + rtDW.Temp_FR_store = -9999.0; + + /* Start for DataStoreMemory: '/Data Store Memory6' */ + rtDW.Temp_RL_store = -9999.0; + + /* Start for Switch: '/Switch1' incorporates: + * DataStoreMemory: '/Data Store Memory' + */ + rtDW.AMB_store = -9999.0; + + /* Start for DataStoreMemory: '/Data Store Memory110' */ + rtDW.CCU_FACE_RL = 1U; + + /* Start for DataStoreMemory: '/Data Store Memory113' */ + rtDW.CCU_AUTOMODE_RL = 3U; + + /* Start for DataStoreMemory: '/Data Store Memory116' */ + rtDW.CCU_FACE_RR = 1U; + + /* Start for DataStoreMemory: '/Data Store Memory119' */ + rtDW.CCU_AUTOMODE_RR = 3U; + for (i = 0; i < 9; i++) { + /* Start for DataStoreMemory: '/Data Store Memory1' */ + rtDW.ErrorCalibration_private[i] = 1U; + + /* Start for DataStoreMemory: '/Data Store Memory1' */ + rtDW.ErrorCalibration_private_p[i] = 1U; + + /* Start for DataStoreMemory: '/Data Store Memory1' */ + rtDW.ErrorCalibration_private_b[i] = 1U; + + /* Start for DataStoreMemory: '/Data Store Memory121' */ + rtDW.MaxPositionCh0_private[i] = rtConstP.pooled87[i]; + + /* Start for DataStoreMemory: '/Data Store Memory123' */ + rtDW.MaxPositionCh1_private[i] = + rtConstP.DataStoreMemory123_InitialValue[i]; + + /* Start for DataStoreMemory: '/Data Store Memory124' */ + rtDW.MaxPositionCh2_private[i] = + rtConstP.DataStoreMemory124_InitialValue[i]; + } + + /* Start for DataTypeConversion: '/Data Type Conversion1' incorporates: + * DataStoreMemory: '/Data Store Memory14' + */ + rtDW.CCU_SET_FR = 230U; + + /* Start for DataTypeConversion: '/Data Type Conversion1' incorporates: + * DataStoreMemory: '/Data Store Memory15' + */ + rtDW.CCU_SET_FL = 230U; + + /* Start for DataTypeConversion: '/Data Type Conversion1' incorporates: + * DataStoreMemory: '/Data Store Memory16' + */ + rtDW.CCU_SET_RR = 230U; + + /* Start for DataStoreMemory: '/Data Store Memory160' */ + rtDW.SW5V_EN = 1U; + + /* Start for DataStoreMemory: '/Data Store Memory161' */ + rtDW.PBATT_CK_EN = 1U; + + /* Start for DataStoreMemory: '/Data Store Memory165' */ + rtDW.ReservePower_EN = 1U; + + /* Start for DataStoreMemory: '/Data Store Memory166' */ + rtDW.PtcRelayDriver1_EN = 1U; + + /* Start for DataStoreMemory: '/Data Store Memory167' */ + rtDW.PtcRelayDriver2_EN = 1U; + + /* Start for DataTypeConversion: '/Data Type Conversion1' incorporates: + * DataStoreMemory: '/Data Store Memory17' + */ + rtDW.CCU_SET_RL = 230U; + + /* Start for DataStoreMemory: '/Data Store Memory170' */ + rtDW.EN_ReservePower = 1U; + + /* Start for DataStoreMemory: '/Data Store Memory171' */ + rtDW.LIN_ActPower_AB = 1U; + + /* Start for DataStoreMemory: '/Data Store Memory172' */ + rtDW.LIN_ActPower_C = 1U; + + /* Start for DataStoreMemory: '/Data Store Memory173' */ + rtDW.ShutOffTXV1_EN = 1U; + + /* Start for DataStoreMemory: '/Data Store Memory174' */ + rtDW.ShutOffTXV2_EN = 1U; + + /* Start for DataStoreMemory: '/Data Store Memory176' */ + rtDW.EN_PowerReserve = 1U; + + /* Start for DataStoreMemory: '/Data Store Memory231' */ + rtDW.step_start_controle_front = -1; + + /* Start for DataStoreMemory: '/Data Store Memory232' */ + rtDW.step_start_controle_rear = -1; + + /* Start for DataStoreMemory: '/Data Store Memory279' */ + rtDW.DRS_CFL = 3U; + + /* Start for DataStoreMemory: '/Data Store Memory282' */ + rtDW.DRS_CFR = 3U; + + /* Start for DataStoreMemory: '/Data Store Memory286' */ + rtDW.DRS_SFR = 3U; + + /* Start for DataStoreMemory: '/Data Store Memory287' */ + rtDW.DRS_SFL = 3U; + + /* Start for DataStoreMemory: '/Data Store Memory288' */ + rtDW.DRS_CRL = 3U; + + /* Start for DataStoreMemory: '/Data Store Memory289' */ + rtDW.DRS_CRR = 3U; + + /* Start for DataStoreMemory: '/Data Store Memory290' */ + rtDW.DRS_SRL = 3U; + + /* Start for DataStoreMemory: '/Data Store Memory291' */ + rtDW.DRS_SRR = 3U; + + /* Start for DataStoreMemory: '/Data Store Memory42' */ + rtDW.ADC_Data_Model = rtConstP.DataStoreMemory42_InitialValue; + + /* Start for DataStoreMemory: '/Data Store Memory5' */ + rtDW.t_now = 10U; + + /* Start for DataStoreMemory: '/Data Store Memory76' */ + rtDW.CCU_SET_FOOT_FL = 3U; + + /* Start for DataStoreMemory: '/Data Store Memory77' */ + rtDW.CCU_SET_FOOT_FR = 3U; + + /* Start for DataStoreMemory: '/Data Store Memory85' */ + rtDW.CCU_FACE_FL = 1U; + + /* Start for DataStoreMemory: '/Data Store Memory86' */ + rtDW.CCU_FOOT_FL = 1U; + + /* Start for DataStoreMemory: '/Data Store Memory89' */ + rtDW.CCU_FACE_FR = 1U; + + /* Start for DataStoreMemory: '/Data Store Memory90' */ + rtDW.CCU_FOOT_FR = 1U; + + /* Start for DataStoreMemory: '/Data Store Memory93' */ + rtDW.CCU_AUTOMODE_FR = 3U; + + /* Start for DataStoreMemory: '/Data Store Memory94' */ + rtDW.CCU_AUTOMODE_FL = 3U; + + /* Start for DataStoreMemory: '/Data Store Memory95' */ + rtDW.CCU_RECIRC = 2U; + + /* InitializeConditions for RateLimiter: '/Rate Limiter' */ + rtDW.PrevY = 0.0; + + /* InitializeConditions for UnitDelay: '/Unit Delay' */ + rtDW.UnitDelay_DSTATE_fq = -9999; + + /* InitializeConditions for UnitDelay: '/Unit Delay1' */ + rtDW.UnitDelay1_DSTATE = -9999; + + /* InitializeConditions for UnitDelay: '/Unit Delay' */ + rtDW.UnitDelay_DSTATE_cbr = -9999; + + /* InitializeConditions for UnitDelay: '/Unit Delay' */ + rtDW.UnitDelay_DSTATE_j = -9999; + + /* InitializeConditions for UnitDelay: '/Unit Delay' */ + rtDW.UnitDelay_DSTATE_cs = -9999; + + /* InitializeConditions for UnitDelay: '/Unit Delay' */ + rtDW.UnitDelay_DSTATE_k2 = -9999; + + /* InitializeConditions for UnitDelay: '/Unit Delay' */ + rtDW.UnitDelay_DSTATE_cu = -9999; + + /* SystemInitialize for Chart: '/A//C Control' */ + rtB.FRONT_eTXV = false; + rtB.REAR_eTXV = false; + rtB.Chiller_eTXV = false; + rtDW.Pressure_Condition_table_OK = false; + rtDW.Chiller_Start_request = false; + rtDW.Pressure_Hi_Fault = false; + rtB.Comp_Feedback_Temp = 0; + rtB.Comp_Target_Temp = 0; + rtB.Chiller_Only_Flag = 0.0; + rtDW.FRONT_Start_request = false; + rtDW.REAR_Start_request = false; + rtB.Eva_Ctrl = 0U; + rtDW.is_active_c621_HVAC_model = 0U; + rtDW.is_PRESSURE_MONITOR = IN_NO_ACTIVE_CHILD_c; + rtDW.is_FRONT_CONTOUR = IN_NO_ACTIVE_CHILD_c; + rtDW.is_REAR_CONTOUR = IN_NO_ACTIVE_CHILD_c; + rtDW.is_CHILLER_CONTOUR = IN_NO_ACTIVE_CHILD_c; + rtDW.is_E_COMP_MANAGER = IN_NO_ACTIVE_CHILD_c; + rtDW.is_COMP_PROTECTION = IN_NO_ACTIVE_CHILD_c; + + /* SystemInitialize for MATLAB Function: '/MATLAB Function1' */ + rtDW.t_start_not_empty = false; + rtDW.is_running = 0U; + + /* SystemInitialize for Chart: '/13,1,3,15 Valve control' */ + rtDW.Cmd_RearTemp_3W = 0.0; + rtB.Cmd_2Way = 0U; + rtDW.Cmd_RearTemp_2W = 0.0; + rtDW.is_active_c775_HVAC_model = 0U; + rtDW.is_ThreeWay_Logic = IN_NO_ACTIVE_CHILD_c; + rtDW.is_TwoWay_Logic = IN_NO_ACTIVE_CHILD_c; + + /* SystemInitialize for Chart: '/Chart' */ + rtB.condition = 0.0; + rtDW.is_active_c248_HVAC_model = 0U; + rtDW.is_c248_HVAC_model = IN_NO_ACTIVE_CHILD_c; + + /* SystemInitialize for Chart: '/Synchronization stateflow chart' */ + rtB.sync_all = 0U; + rtB.sync_front = 0U; + rtB.sync_rear = 0U; + rtDW.is_active_c618_HVAC_model = 0U; + rtDW.is_c618_HVAC_model = IN_NO_ACTIVE_CHILD_c; + + /* SystemInitialize for Merge: '/Merge' */ + rtB.Merge_b = 0U; + + /* SystemInitialize for MATLAB Function: '/Log Ambient Lv' */ + rtDW.current_Ambient_Lv_not_empty = false; + + /* SystemInitialize for Chart: '/Spd_OSA_Trigger' */ + rtDW.is_active_c834_HVAC_model = 0U; + rtDW.is_c834_HVAC_model = IN_NO_ACTIVE_CHILD_c; + + /* SystemInitialize for Chart: '/Partial REC' */ + rtB.req_OSA = 0U; + rtB.req_REC = 0U; + rtDW.X_prev = 0; + rtDW.is_active_c776_HVAC_model = 0U; + rtDW.is_c776_HVAC_model = IN_NO_ACTIVE_CHILD_c; + rtDW.is_PARTIAL_REC_ON = IN_NO_ACTIVE_CHILD_c; + rtDW.is_COND_2 = IN_NO_ACTIVE_CHILD_c; + + /* SystemInitialize for IfAction SubSystem: '/If Action Subsystem' */ + /* SystemInitialize for Merge: '/Merge' */ + rtB.Merge_j = 0; + + /* SystemInitialize for Merge: '/Merge1' */ + rtB.Merge1_j = 0; + + /* End of SystemInitialize for SubSystem: '/If Action Subsystem' */ + + /* SystemInitialize for IfAction SubSystem: '/If Action Subsystem1' */ + /* SystemInitialize for Merge: '/Merge' */ + rtB.Merge_i2 = 0; + + /* SystemInitialize for Merge: '/Merge1' */ + rtB.Merge1_h = 0; + + /* End of SystemInitialize for SubSystem: '/If Action Subsystem1' */ + + /* SystemInitialize for IfAction SubSystem: '/If Action Subsystem2' */ + /* SystemInitialize for Merge: '/Merge' */ + rtB.Merge_he = 0; + + /* SystemInitialize for Merge: '/Merge1' */ + rtB.Merge1_c = 0; + + /* End of SystemInitialize for SubSystem: '/If Action Subsystem2' */ + + /* SystemInitialize for IfAction SubSystem: '/If Action Subsystem' */ + /* SystemInitialize for Merge: '/Merge' */ + rtB.Merge_on = 0; + + /* SystemInitialize for Merge: '/Merge1' */ + rtB.Merge1_g = 0; + + /* End of SystemInitialize for SubSystem: '/If Action Subsystem' */ + + /* SystemInitialize for IfAction SubSystem: '/If Action Subsystem1' */ + /* SystemInitialize for Merge: '/Merge' */ + rtB.Merge_o = 0; + + /* SystemInitialize for Merge: '/Merge1' */ + rtB.Merge1_e = 0; + + /* End of SystemInitialize for SubSystem: '/If Action Subsystem1' */ + + /* SystemInitialize for IfAction SubSystem: '/If Action Subsystem2' */ + /* SystemInitialize for Merge: '/Merge' */ + rtB.Merge_p5 = 0; + + /* SystemInitialize for Merge: '/Merge1' */ + rtB.Merge1 = 0; + + /* End of SystemInitialize for SubSystem: '/If Action Subsystem2' */ + + /* SystemInitialize for Chart: '/Zone_Climate_Logic_Auto_FL2' */ + Zone_Climate_Logic_Auto_FL2_Init(&rtB.out_def_i, &rtB.out_face_c, + &rtB.out_foot_f, &rtB.out_auto_h, &rtB.out_ac_ed, + &rtDW.sf_Zone_Climate_Logic_Auto_FL2); + + /* SystemInitialize for Chart: '/Zone_Climate_Logic_Auto_FL3' */ + Zone_Climate_Logic_Auto_FL2_Init(&rtB.out_def_n, &rtB.out_face_f, + &rtB.out_foot_p, &rtB.out_auto_e, &rtB.out_ac_e, + &rtDW.sf_Zone_Climate_Logic_Auto_FL3); + + /* SystemInitialize for Chart: '/Zone_Climate_Logic_Auto_FL1' */ + rtB.out_def_m = 0U; + rtB.out_face_m = 0U; + rtB.out_foot_ps = 0U; + rtB.out_auto_hx = 0U; + rtB.out_ac_m = 0.0; + rtDW.is_active_c681_HVAC_model = 0U; + rtDW.is_c681_HVAC_model = IN_NO_ACTIVE_CHILD_c; + rtDW.is_AC_SUB_c = IN_NO_ACTIVE_CHILD_c; + rtDW.is_DEF_SUB_i = IN_NO_ACTIVE_CHILD_c; + rtDW.is_FACE_SUB_o = IN_NO_ACTIVE_CHILD_c; + rtDW.is_FOOT_SUB_f = IN_NO_ACTIVE_CHILD_c; + rtDW.is_AC_SUB_co = IN_NO_ACTIVE_CHILD_c; + + /* SystemInitialize for Chart: '/Zone_Climate_Logic_Auto_FL4' */ + rtB.out_def = 0U; + rtB.out_face = 0U; + rtB.out_foot = 0U; + rtB.out_auto = 0U; + rtB.out_ac = 0.0; + rtDW.is_active_c777_HVAC_model = 0U; + rtDW.is_c777_HVAC_model = IN_NO_ACTIVE_CHILD_c; + rtDW.is_AC_SUB = IN_NO_ACTIVE_CHILD_c; + rtDW.is_DEF_SUB = IN_NO_ACTIVE_CHILD_c; + rtDW.is_FACE_SUB = IN_NO_ACTIVE_CHILD_c; + rtDW.is_FOOT_SUB = IN_NO_ACTIVE_CHILD_c; + rtDW.is_AC_SUB_a = IN_NO_ACTIVE_CHILD_c; + + /* SystemInitialize for Enabled SubSystem: '/Subsystem53' */ + /* SystemInitialize for Chart: '/AC_Max_Active' */ + rtDW.is_active_c782_HVAC_model = 0U; + rtDW.is_c782_HVAC_model = IN_NO_ACTIVE_CHILD_c; + + /* SystemInitialize for Chart: '/Defrost_Active' */ + rtDW.is_active_c837_HVAC_model = 0U; + rtDW.is_c837_HVAC_model = IN_NO_ACTIVE_CHILD_c; + + /* SystemInitialize for Chart: '/Full_Rec_Active' */ + rtDW.is_active_c836_HVAC_model = 0U; + rtDW.is_c836_HVAC_model = IN_NO_ACTIVE_CHILD_c; + + /* End of SystemInitialize for SubSystem: '/Subsystem53' */ + + /* SystemInitialize for IfAction SubSystem: '/Homing' */ + /* SystemInitialize for IfAction SubSystem: '/Switch Case Action Subsystem3' */ + /* SystemInitialize for IfAction SubSystem: '/If Action Subsystem' */ + /* Start for DataStoreMemory: '/Data Store Memory' */ + rtDW.Start_timer_n = 1.0; + + /* SystemInitialize for MATLAB Function: '/MATLAB Function' */ + MATLABFunction_Init(&rtDW.sf_MATLABFunction_h); + + /* End of SystemInitialize for SubSystem: '/If Action Subsystem' */ + /* End of SystemInitialize for SubSystem: '/Switch Case Action Subsystem3' */ + + /* SystemInitialize for Merge: '/Merge' */ + rtB.Merge_a = 0; + + /* End of SystemInitialize for SubSystem: '/Homing' */ + + /* SystemInitialize for Merge: '/Merge' */ + rtB.Merge_f1 = 0; + + /* SystemInitialize for IfAction SubSystem: '/Homing' */ + /* SystemInitialize for IfAction SubSystem: '/Switch Case Action Subsystem3' */ + /* SystemInitialize for IfAction SubSystem: '/If Action Subsystem' */ + /* Start for DataStoreMemory: '/Data Store Memory' */ + rtDW.Start_timer_j = 1.0; + + /* SystemInitialize for MATLAB Function: '/MATLAB Function' */ + MATLABFunction_Init(&rtDW.sf_MATLABFunction_hk); + + /* End of SystemInitialize for SubSystem: '/If Action Subsystem' */ + /* End of SystemInitialize for SubSystem: '/Switch Case Action Subsystem3' */ + + /* SystemInitialize for Merge: '/Merge' */ + rtB.Merge_p = 0; + + /* End of SystemInitialize for SubSystem: '/Homing' */ + + /* SystemInitialize for Merge: '/Merge' */ + rtB.Merge_e = 0; + + /* SystemInitialize for IfAction SubSystem: '/Homing' */ + /* SystemInitialize for IfAction SubSystem: '/Switch Case Action Subsystem3' */ + /* SystemInitialize for IfAction SubSystem: '/If Action Subsystem' */ + /* Start for DataStoreMemory: '/Data Store Memory' */ + rtDW.Start_timer = 1.0; + + /* SystemInitialize for MATLAB Function: '/MATLAB Function' */ + MATLABFunction_Init(&rtDW.sf_MATLABFunction_g); + + /* End of SystemInitialize for SubSystem: '/If Action Subsystem' */ + /* End of SystemInitialize for SubSystem: '/Switch Case Action Subsystem3' */ + + /* SystemInitialize for Merge: '/Merge' */ + rtB.Merge_h3 = 0; + + /* End of SystemInitialize for SubSystem: '/Homing' */ + + /* SystemInitialize for Merge: '/Merge' */ + rtB.Merge_b4 = 0; + + /* SystemInitialize for IfAction SubSystem: '/Start Control Front' */ + /* SystemInitialize for IfAction SubSystem: '/Step 1 F' */ + /* SystemInitialize for IfAction SubSystem: '/Level 0' */ + /* SystemInitialize for MATLAB Function: '/MATLAB Function1' */ + MATLABFunction1_Init(&rtDW.sf_MATLABFunction1_n); + + /* End of SystemInitialize for SubSystem: '/Level 0' */ + + /* SystemInitialize for IfAction SubSystem: '/Level 1' */ + /* SystemInitialize for MATLAB Function: '/MATLAB Function1' */ + MATLABFunction1_a_Init(&rtDW.sf_MATLABFunction1_j); + + /* End of SystemInitialize for SubSystem: '/Level 1' */ + + /* SystemInitialize for IfAction SubSystem: '/Level 3' */ + /* SystemInitialize for MATLAB Function: '/MATLAB Function1' */ + MATLABFunction1_a_Init(&rtDW.sf_MATLABFunction1_d); + + /* End of SystemInitialize for SubSystem: '/Level 3' */ + + /* SystemInitialize for IfAction SubSystem: '/Level 4' */ + /* SystemInitialize for MATLAB Function: '/MATLAB Function1' */ + MATLABFunction1_a_Init(&rtDW.sf_MATLABFunction1_h); + + /* End of SystemInitialize for SubSystem: '/Level 4' */ + + /* SystemInitialize for IfAction SubSystem: '/Level 5' */ + /* SystemInitialize for MATLAB Function: '/MATLAB Function1' */ + MATLABFunction1_a_Init(&rtDW.sf_MATLABFunction1_p); + + /* End of SystemInitialize for SubSystem: '/Level 5' */ + /* End of SystemInitialize for SubSystem: '/Step 1 F' */ + + /* SystemInitialize for IfAction SubSystem: '/Step 2 F' */ + /* SystemInitialize for IfAction SubSystem: '/Level 0' */ + /* SystemInitialize for MATLAB Function: '/MATLAB Function1' */ + MATLABFunction1_a_Init(&rtDW.sf_MATLABFunction1_m); + + /* End of SystemInitialize for SubSystem: '/Level 0' */ + + /* SystemInitialize for IfAction SubSystem: '/Level 1' */ + /* SystemInitialize for MATLAB Function: '/MATLAB Function1' */ + MATLABFunction1_a_Init(&rtDW.sf_MATLABFunction1_i2); + + /* End of SystemInitialize for SubSystem: '/Level 1' */ + + /* SystemInitialize for IfAction SubSystem: '/Level 3' */ + Level3_Init(&rtDW.Level3_d); + + /* End of SystemInitialize for SubSystem: '/Level 3' */ + + /* SystemInitialize for IfAction SubSystem: '/Level 4' */ + Level3_Init(&rtDW.Level4_l); + + /* End of SystemInitialize for SubSystem: '/Level 4' */ + + /* SystemInitialize for IfAction SubSystem: '/Level 5' */ + /* SystemInitialize for MATLAB Function: '/MATLAB Function1' */ + MATLABFunction1_a_Init(&rtDW.sf_MATLABFunction1_j2); + + /* End of SystemInitialize for SubSystem: '/Level 5' */ + /* End of SystemInitialize for SubSystem: '/Step 2 F' */ + + /* SystemInitialize for Merge: '/Merge' */ + rtB.Merge_pe = 0; + + /* End of SystemInitialize for SubSystem: '/Start Control Front' */ + + /* SystemInitialize for IfAction SubSystem: '/Start Control Rear' */ + /* SystemInitialize for IfAction SubSystem: '/Step 1 R' */ + /* SystemInitialize for IfAction SubSystem: '/Level 0' */ + Level0_c_Init(&rtDW.Level0_gj); + + /* End of SystemInitialize for SubSystem: '/Level 0' */ + + /* SystemInitialize for IfAction SubSystem: '/Level 1' */ + Level0_c_Init(&rtDW.Level1_l); + + /* End of SystemInitialize for SubSystem: '/Level 1' */ + + /* SystemInitialize for IfAction SubSystem: '/Level 2' */ + /* SystemInitialize for MATLAB Function: '/MATLAB Function1' */ + MATLABFunction1_Init(&rtDW.sf_MATLABFunction1_m3); + + /* End of SystemInitialize for SubSystem: '/Level 2' */ + + /* SystemInitialize for IfAction SubSystem: '/Level 3' */ + /* SystemInitialize for MATLAB Function: '/MATLAB Function1' */ + MATLABFunction1_Init(&rtDW.sf_MATLABFunction1_c); + + /* End of SystemInitialize for SubSystem: '/Level 3' */ + + /* SystemInitialize for IfAction SubSystem: '/Level 4' */ + Level4_b_Init(&rtDW.Level4_m5); + + /* End of SystemInitialize for SubSystem: '/Level 4' */ + + /* SystemInitialize for IfAction SubSystem: '/Level 5' */ + Level4_b_Init(&rtDW.Level5_i); + + /* End of SystemInitialize for SubSystem: '/Level 5' */ + /* End of SystemInitialize for SubSystem: '/Step 1 R' */ + + /* SystemInitialize for IfAction SubSystem: '/Step 2 R' */ + /* SystemInitialize for IfAction SubSystem: '/Level 0' */ + Level0_h_Init(&rtDW.Level0_ad); + + /* End of SystemInitialize for SubSystem: '/Level 0' */ + + /* SystemInitialize for IfAction SubSystem: '/Level 1' */ + Level0_h_Init(&rtDW.Level1_hm); + + /* End of SystemInitialize for SubSystem: '/Level 1' */ + + /* SystemInitialize for IfAction SubSystem: '/Level 2' */ + Level2_j_Init(&rtDW.Level2_f0); + + /* End of SystemInitialize for SubSystem: '/Level 2' */ + + /* SystemInitialize for IfAction SubSystem: '/Level 3' */ + Level2_j_Init(&rtDW.Level3_p); + + /* End of SystemInitialize for SubSystem: '/Level 3' */ + + /* SystemInitialize for IfAction SubSystem: '/Level 4' */ + Level2_j_Init(&rtDW.Level4_b); + + /* End of SystemInitialize for SubSystem: '/Level 4' */ + + /* SystemInitialize for IfAction SubSystem: '/Level 5' */ + Level2_j_Init(&rtDW.Level5_ph); + + /* End of SystemInitialize for SubSystem: '/Level 5' */ + /* End of SystemInitialize for SubSystem: '/Step 2 R' */ + + /* SystemInitialize for Merge: '/Merge' */ + rtB.Merge_a0 = 0; + + /* End of SystemInitialize for SubSystem: '/Start Control Rear' */ + } +} + +/* Model terminate function */ +void HVAC_model_terminate(void) +{ + /* (no terminate code required) */ +} + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/MODULES/HVAC_M7_MODEL/HVAC_model.h b/MODULES/HVAC_M7_MODEL/HVAC_model.h new file mode 100644 index 0000000..2ba2209 --- /dev/null +++ b/MODULES/HVAC_M7_MODEL/HVAC_model.h @@ -0,0 +1,5066 @@ +/* + * File: HVAC_model.h + * + * Code generated for Simulink model 'HVAC_model'. + * + * Model version : 1.1466 + * Simulink Coder version : 24.1 (R2024a) 19-Nov-2023 + * C/C++ source code generated on : Fri Jul 31 15:00:33 2026 + * + * Target selection: ert.tlc + * Embedded hardware selection: ARM Compatible->ARM Cortex-M + * Emulation hardware selection: + * Differs from embedded hardware (MATLAB Host) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#ifndef HVAC_model_h_ +#define HVAC_model_h_ +#ifndef HVAC_model_COMMON_INCLUDES_ +#define HVAC_model_COMMON_INCLUDES_ +#include +#include +#include +#endif /* HVAC_model_COMMON_INCLUDES_ */ + +#include "HVAC_model_types.h" +#include +#include +#include + +/* Macros for accessing real-time model data structure */ +#ifndef rtmGetErrorStatus +#define rtmGetErrorStatus(rtm) ((rtm)->errorStatus) +#endif + +#ifndef rtmSetErrorStatus +#define rtmSetErrorStatus(rtm, val) ((rtm)->errorStatus = (val)) +#endif + +/* user code (top of header file) */ +#include + +/* Block states (default storage) for system '/MATLAB Function1' */ +typedef struct { + uint32_t t_start; /* '/MATLAB Function1' */ + bool t_start_not_empty; /* '/MATLAB Function1' */ +} DW_MATLABFunction1; + +/* Block states (default storage) for system '/MATLAB Function1' */ +typedef struct { + uint32_t t_start; /* '/MATLAB Function1' */ + bool t_start_not_empty; /* '/MATLAB Function1' */ +} DW_MATLABFunction1_f; + +/* Block states (default storage) for system '/Level 3' */ +typedef struct { + uint32_t UnitDelay_DSTATE; /* '/Unit Delay' */ + uint32_t UnitDelay_DSTATE_c; /* '/Unit Delay' */ + uint32_t UnitDelay_DSTATE_f; /* '/Unit Delay' */ + uint32_t UnitDelay_DSTATE_l; /* '/Unit Delay' */ + DW_MATLABFunction1_f sf_MATLABFunction1;/* '/MATLAB Function1' */ +} DW_Level3; + +/* Block states (default storage) for system '/Level 0' */ +typedef struct { + DW_MATLABFunction1 sf_MATLABFunction1;/* '/MATLAB Function1' */ +} DW_Level0_h; + +/* Block states (default storage) for system '/Level 4' */ +typedef struct { + DW_MATLABFunction1 sf_MATLABFunction1;/* '/MATLAB Function1' */ +} DW_Level4_h; + +/* Block states (default storage) for system '/Level 0' */ +typedef struct { + uint32_t UnitDelay_DSTATE; /* '/Unit Delay' */ + uint32_t UnitDelay_DSTATE_k; /* '/Unit Delay' */ + uint32_t UnitDelay_DSTATE_n; /* '/Unit Delay' */ + DW_MATLABFunction1 sf_MATLABFunction1;/* '/MATLAB Function1' */ +} DW_Level0_hr; + +/* Block states (default storage) for system '/Level 2' */ +typedef struct { + uint32_t UnitDelay_DSTATE; /* '/Unit Delay' */ + uint32_t UnitDelay_DSTATE_n; /* '/Unit Delay' */ + uint32_t UnitDelay_DSTATE_p; /* '/Unit Delay' */ + DW_MATLABFunction1 sf_MATLABFunction1;/* '/MATLAB Function1' */ +} DW_Level2_j; + +/* Block states (default storage) for system '/Zone_Climate_Logic_Auto_FL2' */ +typedef struct { + uint8_t is_active_c783_HVAC_model; /* '/Zone_Climate_Logic_Auto_FL2' */ + uint8_t is_c783_HVAC_model; /* '/Zone_Climate_Logic_Auto_FL2' */ + uint8_t is_AC_SUB; /* '/Zone_Climate_Logic_Auto_FL2' */ + uint8_t is_DEF_SUB; /* '/Zone_Climate_Logic_Auto_FL2' */ + uint8_t is_FACE_SUB; /* '/Zone_Climate_Logic_Auto_FL2' */ + uint8_t is_FOOT_SUB; /* '/Zone_Climate_Logic_Auto_FL2' */ + uint8_t is_AC_SUB_f; /* '/Zone_Climate_Logic_Auto_FL2' */ +} DW_Zone_Climate_Logic_Auto_FL2; + +/* Block states (default storage) for system '/MATLAB Function' */ +typedef struct { + double cond_prev; /* '/MATLAB Function' */ + uint32_t t_start; /* '/MATLAB Function' */ + bool t_start_not_empty; /* '/MATLAB Function' */ +} DW_MATLABFunction; + +/* Block signals (default storage) */ +typedef struct { + double condition; /* '/Chart' */ + double out_ac; /* '/Zone_Climate_Logic_Auto_FL4' */ + double out_ac_e; /* '/Zone_Climate_Logic_Auto_FL3' */ + double out_ac_ed; /* '/Zone_Climate_Logic_Auto_FL2' */ + double out_ac_m; /* '/Zone_Climate_Logic_Auto_FL1' */ + double Chiller_Only_Flag; /* '/A//C Control' */ + uint16_t MultiportSwitch[6]; /* '/Multiport Switch' */ + uint16_t MultiportSwitch_h[6]; /* '/Multiport Switch' */ + uint16_t MultiportSwitch_j[9]; /* '/Multiport Switch' */ + uint16_t MultiportSwitch_c; /* '/Multiport Switch' */ + uint16_t MultiportSwitch_m; /* '/Multiport Switch' */ + uint16_t MultiportSwitch_a; /* '/Multiport Switch' */ + uint16_t MultiportSwitch_cy; /* '/Multiport Switch' */ + int16_t Comp_Feedback_Temp; /* '/A//C Control' */ + int16_t Comp_Target_Temp; /* '/A//C Control' */ + int16_t Merge1; /* '/Merge1' */ + int16_t Merge1_e; /* '/Merge1' */ + int16_t Merge1_g; /* '/Merge1' */ + int16_t Merge1_c; /* '/Merge1' */ + int16_t Merge1_h; /* '/Merge1' */ + int16_t Merge1_j; /* '/Merge1' */ + uint8_t Merge_b; /* '/Merge' */ + uint8_t sync_all; /* '/Synchronization stateflow chart' */ + uint8_t sync_front; /* '/Synchronization stateflow chart' */ + uint8_t sync_rear; /* '/Synchronization stateflow chart' */ + uint8_t out_def; /* '/Zone_Climate_Logic_Auto_FL4' */ + uint8_t out_face; /* '/Zone_Climate_Logic_Auto_FL4' */ + uint8_t out_foot; /* '/Zone_Climate_Logic_Auto_FL4' */ + uint8_t out_auto; /* '/Zone_Climate_Logic_Auto_FL4' */ + uint8_t out_def_n; /* '/Zone_Climate_Logic_Auto_FL3' */ + uint8_t out_face_f; /* '/Zone_Climate_Logic_Auto_FL3' */ + uint8_t out_foot_p; /* '/Zone_Climate_Logic_Auto_FL3' */ + uint8_t out_auto_e; /* '/Zone_Climate_Logic_Auto_FL3' */ + uint8_t out_def_i; /* '/Zone_Climate_Logic_Auto_FL2' */ + uint8_t out_face_c; /* '/Zone_Climate_Logic_Auto_FL2' */ + uint8_t out_foot_f; /* '/Zone_Climate_Logic_Auto_FL2' */ + uint8_t out_auto_h; /* '/Zone_Climate_Logic_Auto_FL2' */ + uint8_t out_def_m; /* '/Zone_Climate_Logic_Auto_FL1' */ + uint8_t out_face_m; /* '/Zone_Climate_Logic_Auto_FL1' */ + uint8_t out_foot_ps; /* '/Zone_Climate_Logic_Auto_FL1' */ + uint8_t out_auto_hx; /* '/Zone_Climate_Logic_Auto_FL1' */ + uint8_t Eva_Ctrl; /* '/A//C Control' */ + uint8_t req_OSA; /* '/Partial REC' */ + uint8_t req_REC; /* '/Partial REC' */ + uint8_t Cmd_2Way; /* '/13,1,3,15 Valve control' */ + int8_t Merge_f1; /* '/Merge' */ + int8_t Merge_e; /* '/Merge' */ + int8_t Merge_b4; /* '/Merge' */ + int8_t Merge_h3; /* '/Merge' */ + int8_t Merge_p; /* '/Merge' */ + int8_t Merge_a; /* '/Merge' */ + int8_t Merge_a0; /* '/Merge' */ + int8_t Merge_pe; /* '/Merge' */ + int8_t Merge_p5; /* '/Merge' */ + int8_t Merge_o; /* '/Merge' */ + int8_t Merge_on; /* '/Merge' */ + int8_t Merge_he; /* '/Merge' */ + int8_t Merge_i2; /* '/Merge' */ + int8_t Merge_j; /* '/Merge' */ + bool FRONT_eTXV; /* '/A//C Control' */ + bool REAR_eTXV; /* '/A//C Control' */ + bool Chiller_eTXV; /* '/A//C Control' */ +} B; + +/* Block states (default storage) for system '' */ +typedef struct { + dbg_Auto_Duct_Bus dbg_Auto_Duct_model;/* '/Data Store Memory234' */ + CmdBusADCData ADC_Data_Model; /* '/Data Store Memory42' */ + dbg_Auto_AF_Bus dbg_Auto_AF_model; /* '/Data Store Memory233' */ + Status_Actuator_Bus Status_Actuator_model_IO;/* '/Data Store Memory97' */ + LIN5_SENSON_ADR_Stat_Bus LIN5_SENSON_ADR_Stat_model;/* '/Data Store Memory262' */ + dbgCAN_dbg_Sen_Duct_Bus dbgCAN_dbg_Sen_Duct_model;/* '/Data Store Memory82' */ + Status_Sensor_Bus Status_Sensor_model_IO;/* '/Data Store Memory99' */ + CCUCAN_ESC_04_Bus CCUCAN_ESC_04_model;/* '/Data Store Memory141' */ + CmdCAN_CCU_STAT1_WakeUp_Bus CCU_STAT1_WAKEUP_MODEL;/* '/Data Store Memory257' */ + dbg_LIN_DRS_Stat_t_Bus dbg_LIN_DRS_Stat_t_model;/* '/Data Store Memory283' */ + CCUCAN_BCM_Climatic_Bus CCUCAN_BCM_Climatic_model;/* '/Data Store Memory138' */ + dbgCAN_dbg_Sen_Incar_Bus dbgCAN_dbg_Sen_Incar_model;/* '/Data Store Memory157' */ + tPowerEnable_Bus PowerEnable_Model; /* '/Data Store Memory159' */ + BCM_VEH_STATE_Bus CCUCAN_BCM_VEH_STATE_model;/* '/Data Store Memory177' */ + CCUCAN_TM_CP_Bus TM_CP_model; /* '/Data Store Memory209' */ + HVC_Err_Status_Msg_Bus HVC_ERR_STATUS_MSG_MODEL;/* '/Data Store Memory210' */ + dbgCAN_Logic_State_Bus dbgCAN_Logic_State_model;/* '/Data Store Memory227' */ + CmdCAN_CCU_STAT2_WakeUp_Bus CCU_STAT2_WAKEUP_MODEL;/* '/Data Store Memory339' */ + CmdCAN_FIU_CCU1_Bus FIU_CCU1_MODEL; /* '/Data Store Memory43' */ + CmdCAN_FIU_CCU2_Bus FIU_CCU2_MODEL; /* '/Data Store Memory44' */ + CCUCAN_BCM_Powertrain_Bus CCUCAN_BCM_Powertrain_model;/* '/Data Store Memory137' */ + CCUCAN_EMS_Veh_Bus CCUCAN_EMS_Veh_model;/* '/Data Store Memory140' */ + dbg_Logic_Ac_Bus dbg_Logic_Ac_model; /* '/Data Store Memory193' */ + dbgCAN_CCU_IO_Bus dbgCAN_CCU_IO_model;/* '/Data Store Memory211' */ + dbg_Logic_Valve_Plus_Bus dbg_Logic_Valve_Plus_model;/* '/Data Store Memory297' */ + dbg_LIN_Aroma_Stat_t_Bus dbg_LIN_Aroma_Stat_t_model;/* '/Data Store Memory337' */ + CCU_Msg1_WakeUp_Bus CCU_Msg1_WakeUp_model;/* '/Data Store Memory341' */ + CmdCAN_FIU_CCU3_Bus FIU_CCU3_MODEL; /* '/Data Store Memory45' */ + dbgCAN_dbg_Logic_Blower_Bus dbgCAN_dbg_Logic_Blower_model;/* '/Data Store Memory64' */ + Status_Duct_Tgt_Bus Status_Duct_Tgt_model_IO;/* '/Data Store Memory96' */ + double UnitDelay_DSTATE; /* '/Unit Delay' */ + double UnitDelay_DSTATE_b; /* '/Unit Delay' */ + double PrevY; /* '/Rate Limiter' */ + double Temp_FL_store; /* '/Data Store Memory' */ + double KEEP_RISING_FL_UNTIL_LIMIT; /* '/Data Store Memory1' */ + double Temp_RR_store; /* '/Data Store Memory10' */ + double KEEP_FALLING_RR_UNTIL_LIMIT; /* '/Data Store Memory11' */ + double KEEP_FALLING_FL_UNTIL_LIMIT; /* '/Data Store Memory2' */ + double KEEP_RISING_FR_UNTIL_LIMIT; /* '/Data Store Memory3' */ + double Temp_FR_store; /* '/Data Store Memory4' */ + double Temp_RL_store; /* '/Data Store Memory6' */ + double KEEP_RISING_RL_UNTIL_LIMIT; /* '/Data Store Memory7' */ + double KEEP_FALLING_RL_UNTIL_LIMIT; /* '/Data Store Memory8' */ + double KEEP_RISING_RR_UNTIL_LIMIT; /* '/Data Store Memory9' */ + double LOGGER_ACP; /* '/Data Store Memory1' */ + double AMB_store; /* '/Data Store Memory' */ + double KEEP_RISING_UNTIL_LIMIT; /* '/Data Store Memory1' */ + double KEEP_FALLING_UNTIL_LIMIT; /* '/Data Store Memory2' */ + double ErrorHomming_private; /* '/Data Store Memory2' */ + double ErrorHomming_private_h; /* '/Data Store Memory2' */ + double ErrorHomming_private_m; /* '/Data Store Memory2' */ + double eCompChiller_Err; /* '/Can_Chiller1' */ + double Sun_L; /* '/Data Store Memory143' */ + double Sun_R; /* '/Data Store Memory144' */ + double condition_ac_max; /* '/Data Store Memory298' */ + double Engine_speed; /* '/EMS_nICEngineSpeed3' */ + double start_control_finished_rear; /* '/SC Rear' */ + double Start_timer; /* '/Data Store Memory' */ + double Start_timer_j; /* '/Data Store Memory' */ + double Start_timer_n; /* '/Data Store Memory' */ + double Cmd_RearTemp_3W; /* '/13,1,3,15 Valve control' */ + double Cmd_RearTemp_2W; /* '/13,1,3,15 Valve control' */ + Status_Eva_Tgt_Bus Status_Eva_Tgt_model_IO;/* '/Data Store Memory100' */ + Status_Duct_Select_Bus Status_Duct_Select_model_IO;/* '/Data Store Memory120' */ + dbgCAN_dbg_Sen_Amb_Bus dbgCAN_dbg_Sen_Amb_model;/* '/Data Store Memory142' */ + dbgCAN_dbg_Sen_0_Bus dbgCAN_dbg_Sen_0_model;/* '/Data Store Memory158' */ + CCUCAN_EMS_HVC_Req_Msg_Bus CCUCAN_EMS_HVC_REQ_MSG_MODEL;/* '/Data Store Memory191' */ + CmdBusADCDataKey ADC_Key_Data_Model; /* '/Data Store Memory198' */ + CCUCAN_OCURL_MSG_Bus CCUCAN_OCURL_MSG_model;/* '/Data Store Memory213' */ + dbgCAN_Logic_Rec_Bus dbgCAN_Logic_Rec_model;/* '/Data Store Memory220' */ + LIN4_AirQS_Stat_Bus LIN4_AirQS_Stat_Model;/* '/Data Store Memory263' */ + LIN4_Aroma_Stat_Bus LIN4_Aroma_Stat_Model;/* '/Data Store Memory264' */ + LIN4_Ionizer_Stat_Bus LIN4_Ionizer_Stat_Model;/* '/Data Store Memory265' */ + LIN4_CCU_Req_Bus LIN4_CCU_Req_Model; /* '/Data Store Memory269' */ + dbg_Logic_Valve_Bus dbg_Logic_Valve_model;/* '/Data Store Memory270' */ + dbg_LIN_AirQS_Stat_t_Bus dbg_LIN_AirQS_Stat_t_model;/* '/Data Store Memory284' */ + dbg_Drs_t_Bus dbg_Drs_t_model; /* '/Data Store Memory285' */ + LIN4_ERROR_Bus LIN4_ERROR_model; /* '/Data Store Memory329' */ + dbg_LIN_Ionizer_Stat_t_Bus dbg_LIN_Ionizer_Stat_t_model;/* '/Data Store Memory336' */ + CmdCAN_CCU_STAT3_WakeUp_Bus CCU_STAT3_WAKEUP_MODEL;/* '/Data Store Memory340' */ + dbgCAN_dbg_Act0_Bus dbgCAN_dbg_Act0_model;/* '/Data Store Memory79' */ + dbgCAN_dbg_Act1_Bus dbgCAN_dbg_Act1_model;/* '/Data Store Memory80' */ + dbgCAN_dbg_Act2_Bus dbgCAN_dbg_Act2_model;/* '/Data Store Memory81' */ + dbgCAN_dbg_dbg_Sen_Eva_Bus dbgCAN_dbg_Sen_Eva_model;/* '/Data Store Memory83' */ + uint32_t t_start_delay_private_DSTATE;/* '/t_start_delay_private ' */ + uint32_t t_start_delay_private_DSTATE_i;/* '/t_start_delay_private ' */ + uint32_t t_start_delay_private_DSTATE_k;/* '/t_start_delay_private ' */ + uint32_t t_start_delay_private_DSTATE_p;/* '/t_start_delay_private ' */ + uint32_t t_start_delay_private_DSTATE_g;/* '/t_start_delay_private ' */ + uint32_t t_start_delay_private_DSTATE_c;/* '/t_start_delay_private ' */ + uint32_t t_start_delay_private_DSTATE_h;/* '/t_start_delay_private ' */ + uint32_t t_start_delay_private_DSTATE_kc;/* '/t_start_delay_private ' */ + uint32_t t_start_delay_private_DSTATE_m;/* '/t_start_delay_private ' */ + uint32_t t_start_delay_private_DSTATE_pn;/* '/t_start_delay_private ' */ + uint32_t t_start_delay_private_DSTATE_hb;/* '/t_start_delay_private ' */ + uint32_t t_start_delay_private_DSTATE_i3;/* '/t_start_delay_private ' */ + uint32_t t_start_delay_private_DSTATE_cc;/* '/t_start_delay_private ' */ + uint32_t t_start_delay_private_DSTATE_o;/* '/t_start_delay_private ' */ + uint32_t t_start_delay_private_DSTATE_oy;/* '/t_start_delay_private ' */ + uint32_t t_start_delay_private_DSTATE_cd;/* '/t_start_delay_private ' */ + uint32_t t_start_delay_private_DSTATE_or;/* '/t_start_delay_private ' */ + uint32_t UnitDelay_DSTATE_c; /* '/Unit Delay' */ + uint32_t UnitDelay_DSTATE_m; /* '/Unit Delay' */ + uint32_t UnitDelay_DSTATE_l; /* '/Unit Delay' */ + uint32_t UnitDelay_DSTATE_cr; /* '/Unit Delay' */ + uint32_t UnitDelay_DSTATE_o; /* '/Unit Delay' */ + uint32_t UnitDelay_DSTATE_g; /* '/Unit Delay' */ + uint32_t UnitDelay_DSTATE_h; /* '/Unit Delay' */ + uint32_t UnitDelay_DSTATE_ly; /* '/Unit Delay' */ + uint32_t UnitDelay_DSTATE_gu; /* '/Unit Delay' */ + uint32_t UnitDelay_DSTATE_mz; /* '/Unit Delay' */ + uint32_t UnitDelay_DSTATE_n; /* '/Unit Delay' */ + uint32_t UnitDelay_DSTATE_le; /* '/Unit Delay' */ + uint32_t UnitDelay_DSTATE_cb; /* '/Unit Delay' */ + uint32_t UnitDelay_DSTATE_k; /* '/Unit Delay' */ + uint32_t UnitDelay_DSTATE_cm; /* '/Unit Delay' */ + uint32_t UnitDelay_DSTATE_f; /* '/Unit Delay' */ + uint32_t UnitDelay_DSTATE_gc; /* '/Unit Delay' */ + int32_t MemComp_I_Value; /* '/Memory1' */ + int32_t MemComp_I_Value_c; /* '/Memory1' */ + int32_t MemComp_I_Value_m; /* '/Memory1' */ + int32_t MemComp_I_Value_p; /* '/Memory1' */ + int32_t MemComp_I_Value_f; /* '/Memory1' */ + int32_t MemComp_I_Value_n; /* '/Memory1' */ + int32_t MemComp_I_Value_m0; /* '/Memory1' */ + uint32_t t_now; /* '/Data Store Memory5' */ + uint32_t t_start; /* '/MATLAB Function1' */ + int16_t UnitDelay_DSTATE_fq; /* '/Unit Delay' */ + int16_t UnitDelay1_DSTATE; /* '/Unit Delay1' */ + int16_t UnitDelay_DSTATE_cbr; /* '/Unit Delay' */ + int16_t UnitDelay_DSTATE_j; /* '/Unit Delay' */ + int16_t UnitDelay_DSTATE_cs; /* '/Unit Delay' */ + int16_t UnitDelay_DSTATE_k2; /* '/Unit Delay' */ + int16_t UnitDelay_DSTATE_cu; /* '/Unit Delay' */ + int16_t pError_PreviousInput; /* '/pError' */ + int16_t pError_PreviousInput_g; /* '/pError' */ + int16_t pError_PreviousInput_p; /* '/pError' */ + int16_t pError_PreviousInput_pe; /* '/pError' */ + int16_t pError_PreviousInput_i; /* '/pError' */ + int16_t pError_PreviousInput_b; /* '/pError' */ + int16_t pError_PreviousInput_d; /* '/pError' */ + int16_t eComp_Temp; /* '/Can_Chiller2' */ + int16_t Eva_F; /* '/Data Store Memory10' */ + int16_t Incar_FR; /* '/Data Store Memory11' */ + int16_t Incar_RR; /* '/Data Store Memory12' */ + int16_t Duct_RR_Tg; /* '/Data Store Memory148' */ + int16_t Blower_individual_foot_FL; /* '/Data Store Memory305' */ + int16_t Blower_individual_foot_FR; /* '/Data Store Memory306' */ + int16_t Dtg_individual_foot_FL; /* '/Data Store Memory309' */ + int16_t Dtg_individual_foot_FR; /* '/Data Store Memory310' */ + int16_t AMB; /* '/Data Store Memory4' */ + int16_t Pressure; /* '/Data Store Memory6' */ + int16_t Incar_FL; /* '/Data Store Memory7' */ + int16_t Incar_RL; /* '/Data Store Memory8' */ + int16_t Eva_R; /* '/Data Store Memory9' */ + int16_t ECT; /* '/engine coolant temp' */ + int16_t X_prev; /* '/Partial REC' */ + uint16_t KEEP_UNTIL_SPEED_DROPS; /* '/Data Store Memory3' */ + uint16_t MinPositionCh0_private[9]; /* '/Data Store Memory12' */ + uint16_t POS_private[9]; /* '/Data Store Memory3' */ + uint16_t MinPositionCh1_private[9]; /* '/Data Store Memory12' */ + uint16_t POS_private_m[9]; /* '/Data Store Memory3' */ + uint16_t MinPositionCh2_private[9]; /* '/Data Store Memory12' */ + uint16_t POS_private_h[9]; /* '/Data Store Memory3' */ + uint16_t MaxPositionCh0_private[9]; /* '/Data Store Memory121' */ + uint16_t MaxPositionCh1_private[9]; /* '/Data Store Memory123' */ + uint16_t MaxPositionCh2_private[9]; /* '/Data Store Memory124' */ + uint16_t CCU_SET_FR; /* '/Data Store Memory14' */ + uint16_t CCU_SET_FL; /* '/Data Store Memory15' */ + uint16_t CCU_SET_RR; /* '/Data Store Memory16' */ + uint16_t CCU_SET_RL; /* '/Data Store Memory17' */ + uint16_t Index_mode_RL_auto; /* '/Data Store Memory277' */ + uint16_t Index_mode_RR_auto; /* '/Data Store Memory278' */ + uint16_t Dtg_FUR; /* '/Data Store Memory30' */ + uint16_t Dtg_FUL; /* '/Data Store Memory31' */ + uint16_t Dtg_FLR; /* '/Data Store Memory33' */ + uint16_t Dtg_FLL; /* '/Data Store Memory34' */ + uint16_t Dtg_RR; /* '/Data Store Memory52' */ + uint16_t Dtg_RL; /* '/Data Store Memory53' */ + uint16_t Blower_logic_RR; /* '/Data Store Memory56' */ + uint16_t VehicleSpeed; /* '/VehicleSpeed' */ + uint16_t eComp_InputC; /* '/Can_Chiller3' */ + uint8_t UnitDelay_DSTATE_ne; /* '/Unit Delay' */ + uint8_t UnitDelay1_DSTATE_j; /* '/Unit Delay1' */ + uint8_t UnitDelay2_DSTATE; /* '/Unit Delay2' */ + uint8_t UnitDelay3_DSTATE; /* '/Unit Delay3' */ + uint8_t DelayInput1_DSTATE; /* '/Delay Input1' */ + uint8_t DelayInput1_DSTATE_e; /* '/Delay Input1' */ + uint8_t DelayInput1_DSTATE_d; /* '/Delay Input1' */ + uint8_t DelayInput1_DSTATE_d3; /* '/Delay Input1' */ + bool Cond_prev_private_DSTATE; /* '/Cond_prev_private ' */ + bool Cond_prev_private_DSTATE_p; /* '/Cond_prev_private ' */ + bool Cond_prev_private_DSTATE_a; /* '/Cond_prev_private ' */ + bool Cond_prev_private_DSTATE_h; /* '/Cond_prev_private ' */ + bool Cond_prev_private_DSTATE_c; /* '/Cond_prev_private ' */ + bool Cond_prev_private_DSTATE_m; /* '/Cond_prev_private ' */ + bool Cond_prev_private_DSTATE_j; /* '/Cond_prev_private ' */ + bool Cond_prev_private_DSTATE_f; /* '/Cond_prev_private ' */ + bool Cond_prev_private_DSTATE_cn; /* '/Cond_prev_private ' */ + bool Cond_prev_private_DSTATE_l; /* '/Cond_prev_private ' */ + bool Cond_prev_private_DSTATE_ja; /* '/Cond_prev_private ' */ + bool Cond_prev_private_DSTATE_g; /* '/Cond_prev_private ' */ + bool Cond_prev_private_DSTATE_cd; /* '/Cond_prev_private ' */ + bool Cond_prev_private_DSTATE_k; /* '/Cond_prev_private ' */ + bool Cond_prev_private_DSTATE_d; /* '/Cond_prev_private ' */ + bool Cond_prev_private_DSTATE_hw; /* '/Cond_prev_private ' */ + bool Cond_prev_private_DSTATE_i; /* '/Cond_prev_private ' */ + bool DelayInput1_DSTATE_e5; /* '/Delay Input1' */ + bool DelayInput1_DSTATE_k; /* '/Delay Input1' */ + bool DelayInput1_DSTATE_l; /* '/Delay Input1' */ + bool DelayInput1_DSTATE_kb; /* '/Delay Input1' */ + bool DelayInput1_DSTATE_kk; /* '/Delay Input1' */ + bool DelayInput1_DSTATE_d1; /* '/Delay Input1' */ + bool DelayInput1_DSTATE_b; /* '/Delay Input1' */ + bool DelayInput1_DSTATE_i; /* '/Delay Input1' */ + bool DelayInput1_DSTATE_c; /* '/Delay Input1' */ + bool DelayInput1_DSTATE_m; /* '/Delay Input1' */ + bool DelayInput1_DSTATE_ic; /* '/Delay Input1' */ + bool DelayInput1_DSTATE_n; /* '/Delay Input1' */ + bool DelayInput1_DSTATE_my; /* '/Delay Input1' */ + bool DelayInput1_DSTATE_a; /* '/Delay Input1' */ + bool DelayInput1_DSTATE_o; /* '/Delay Input1' */ + bool DelayInput1_DSTATE_od; /* '/Delay Input1' */ + bool DelayInput1_DSTATE_j; /* '/Delay Input1' */ + bool DelayInput1_DSTATE_f; /* '/Delay Input1' */ + bool DelayInput1_DSTATE_kz; /* '/Delay Input1' */ + int8_t stepSig_private; /* '/Data Store Memory' */ + int8_t stepHoming_private; /* '/Data Store Memory17' */ + int8_t stepSig_private_h; /* '/Data Store Memory' */ + int8_t stepHoming_private_f; /* '/Data Store Memory17' */ + int8_t stepSig_private_g; /* '/Data Store Memory' */ + int8_t stepHoming_private_a; /* '/Data Store Memory17' */ + int8_t step_start_controle_front; /* '/Data Store Memory231' */ + int8_t step_start_controle_rear; /* '/Data Store Memory232' */ + int8_t Valve_individual_foot_FL; /* '/Data Store Memory300' */ + int8_t Valve_individual_foot_FR; /* '/Data Store Memory301' */ + int8_t start_control_finished_front; /* '/SC Front' */ + uint8_t ErrorCalibration_private[9]; /* '/Data Store Memory1' */ + uint8_t Speed_private[9]; /* '/Data Store Memory11' */ + uint8_t Coils_private[9]; /* '/Data Store Memory16' */ + uint8_t ErrorActuator[9]; /* '/Data Store Memory18' */ + uint8_t BUS_ADR_private[9]; /* '/Data Store Memory4' */ + uint8_t MODE_private[9]; /* '/Data Store Memory5' */ + uint8_t COM_private[9]; /* '/Data Store Memory6' */ + uint8_t Stall_private[9]; /* '/Data Store Memory7' */ + uint8_t Lnoise_private[9]; /* '/Data Store Memory8' */ + uint8_t Autos_private[9]; /* '/Data Store Memory9' */ + uint8_t ErrorCalibration_private_p[9];/* '/Data Store Memory1' */ + uint8_t Speed_private_j[9]; /* '/Data Store Memory11' */ + uint8_t Coils_private_c[9]; /* '/Data Store Memory16' */ + uint8_t ErrorActuator_o[9]; /* '/Data Store Memory18' */ + uint8_t BUS_ADR_private_j[9]; /* '/Data Store Memory4' */ + uint8_t MODE_private_b[9]; /* '/Data Store Memory5' */ + uint8_t COM_private_g[9]; /* '/Data Store Memory6' */ + uint8_t Stall_private_l[9]; /* '/Data Store Memory7' */ + uint8_t Lnoise_private_n[9]; /* '/Data Store Memory8' */ + uint8_t Autos_private_n[9]; /* '/Data Store Memory9' */ + uint8_t ErrorCalibration_private_b[9];/* '/Data Store Memory1' */ + uint8_t Speed_private_b[9]; /* '/Data Store Memory11' */ + uint8_t Coils_private_l[9]; /* '/Data Store Memory16' */ + uint8_t ErrorActuator_a[9]; /* '/Data Store Memory18' */ + uint8_t BUS_ADR_private_a[9]; /* '/Data Store Memory4' */ + uint8_t MODE_private_c[9]; /* '/Data Store Memory5' */ + uint8_t COM_private_k[9]; /* '/Data Store Memory6' */ + uint8_t Stall_private_f[9]; /* '/Data Store Memory7' */ + uint8_t Lnoise_private_g[9]; /* '/Data Store Memory8' */ + uint8_t Autos_private_g[9]; /* '/Data Store Memory9' */ + uint8_t eCompChiller_Req; /* '/Can_Chiller' */ + uint8_t CCU_ActuatorErrF_Stat_private;/* '/Data Store Memory' */ + uint8_t dtc_state_error_model[127]; /* '/Data Store Memory1' */ + uint8_t CCU_SET_FOOT_RL; /* '/Data Store Memory106' */ + uint8_t CCU_SET_FOOT_RR; /* '/Data Store Memory107' */ + uint8_t CCU_MODE_RL; /* '/Data Store Memory108' */ + uint8_t CCU_FACE_RL; /* '/Data Store Memory110' */ + uint8_t CCU_FOOT_RL; /* '/Data Store Memory111' */ + uint8_t CCU_BLOWERS_RL; /* '/Data Store Memory112' */ + uint8_t CCU_AUTOMODE_RL; /* '/Data Store Memory113' */ + uint8_t CCU_MODE_RR; /* '/Data Store Memory114' */ + uint8_t CCU_FACE_RR; /* '/Data Store Memory116' */ + uint8_t CCU_FOOT_RR; /* '/Data Store Memory117' */ + uint8_t CCU_BLOWERS_RR; /* '/Data Store Memory118' */ + uint8_t CCU_AUTOMODE_RR; /* '/Data Store Memory119' */ + uint8_t CCU_AC_REAR; /* '/Data Store Memory122' */ + uint8_t PWM_rear; /* '/Data Store Memory132' */ + uint8_t PWM_front; /* '/Data Store Memory135' */ + uint8_t SW5V_EN; /* '/Data Store Memory160' */ + uint8_t PBATT_CK_EN; /* '/Data Store Memory161' */ + uint8_t Incar_Motor_Front_EN; /* '/Data Store Memory162' */ + uint8_t Incar_Motor_Rear_EN; /* '/Data Store Memory163' */ + uint8_t ReservePower_EN; /* '/Data Store Memory165' */ + uint8_t PtcRelayDriver1_EN; /* '/Data Store Memory166' */ + uint8_t PtcRelayDriver2_EN; /* '/Data Store Memory167' */ + uint8_t EN_ReservePower; /* '/Data Store Memory170' */ + uint8_t LIN_ActPower_AB; /* '/Data Store Memory171' */ + uint8_t LIN_ActPower_C; /* '/Data Store Memory172' */ + uint8_t ShutOffTXV1_EN; /* '/Data Store Memory173' */ + uint8_t ShutOffTXV2_EN; /* '/Data Store Memory174' */ + uint8_t EN_PowerReserve; /* '/Data Store Memory176' */ + uint8_t BCM_T15_Stat; /* '/Data Store Memory178' */ + uint8_t PID_TempFUL; /* '/Data Store Memory185' */ + uint8_t PID_TempFUR; /* '/Data Store Memory186' */ + uint8_t PID_TempRL; /* '/Data Store Memory187' */ + uint8_t PID_TempRR; /* '/Data Store Memory188' */ + uint8_t PID_TempFLL; /* '/Data Store Memory189' */ + uint8_t PID_TempFRL; /* '/Data Store Memory190' */ + uint8_t enable_full_sync; /* '/Data Store Memory199' */ + uint8_t LEVEL; /* '/Data Store Memory2' */ + uint8_t enable_front_sync; /* '/Data Store Memory200' */ + uint8_t disable_front_sync; /* '/Data Store Memory201' */ + uint8_t enable_rear_sync; /* '/Data Store Memory202' */ + uint8_t disable_rear_sync; /* '/Data Store Memory203' */ + uint8_t changed_FR_params; /* '/Data Store Memory204' */ + uint8_t changed_RL_params; /* '/Data Store Memory205' */ + uint8_t changed_RR_params; /* '/Data Store Memory206' */ + uint8_t CCU_Defrost; /* '/Data Store Memory207' */ + uint8_t CCU_AC_MAX; /* '/Data Store Memory208' */ + uint8_t SeatOccupiedRL; /* '/Data Store Memory214' */ + uint8_t Full_Rec; /* '/Data Store Memory216' */ + uint8_t LO_HI_MODE_FR; /* '/Data Store Memory217' */ + uint8_t LO_HI_MODE_RR; /* '/Data Store Memory218' */ + uint8_t Mode_FR; /* '/Data Store Memory22' */ + uint8_t LO_HI_MODE_FL; /* '/Data Store Memory223' */ + uint8_t LO_HI_MODE_RL; /* '/Data Store Memory224' */ + uint8_t CAN_LoHi_Front; /* '/Data Store Memory228' */ + uint8_t Mode_FL; /* '/Data Store Memory23' */ + uint8_t CCU_EvaTempSenErrR_Stat; /* '/Data Store Memory254' */ + uint8_t CCU_EvaTempSenErrF_Stat; /* '/Data Store Memory255' */ + uint8_t CCU_PressSenErr_Stat; /* '/Data Store Memory256' */ + uint8_t Index_mode_FL_manual; /* '/Data Store Memory258' */ + uint8_t Index_mode_FR_manual; /* '/Data Store Memory259' */ + uint8_t Blower_FR; /* '/Data Store Memory26' */ + uint8_t Index_mode_RL_manual; /* '/Data Store Memory260' */ + uint8_t Index_mode_RR_manual; /* '/Data Store Memory261' */ + uint8_t Blower_FL; /* '/Data Store Memory27' */ + uint8_t Index_mode_FL_auto; /* '/Data Store Memory275' */ + uint8_t Index_mode_FR_auto; /* '/Data Store Memory276' */ + uint8_t DRS_CFL; /* '/Data Store Memory279' */ + uint8_t DRS_CFR; /* '/Data Store Memory282' */ + uint8_t DRS_SFR; /* '/Data Store Memory286' */ + uint8_t DRS_SFL; /* '/Data Store Memory287' */ + uint8_t DRS_CRL; /* '/Data Store Memory288' */ + uint8_t DRS_CRR; /* '/Data Store Memory289' */ + uint8_t DRS_SRL; /* '/Data Store Memory290' */ + uint8_t DRS_SRR; /* '/Data Store Memory291' */ + uint8_t AirQS_NH3Lvl; /* '/Data Store Memory294' */ + uint8_t AirQS_NOxLvl; /* '/Data Store Memory295' */ + uint8_t AirQS_COLvl; /* '/Data Store Memory296' */ + uint8_t ModeIndex[4]; /* '/Data Store Memory304' */ + uint8_t Air_status; /* '/Data Store Memory313' */ + uint8_t Aroma_CartridgeFlavor; /* '/Data Store Memory314' */ + uint8_t Aroma_CartridgeCapacity; /* '/Data Store Memory317' */ + uint8_t Blower_RR; /* '/Data Store Memory32' */ + uint8_t Aroma_CartridgeSw; /* '/Data Store Memory320' */ + uint8_t Aroma_status; /* '/Data Store Memory321' */ + uint8_t CCU_AirQualSenErr_Stat; /* '/Data Store Memory326' */ + uint8_t CCU_AromaErr_Stat; /* '/Data Store Memory327' */ + uint8_t CCU_IonizationErr_Stat; /* '/Data Store Memory328' */ + uint8_t CCU_DeflectorSwErrR_Stat; /* '/Data Store Memory330' */ + uint8_t CCU_DeflectorSwErrF_Stat; /* '/Data Store Memory331' */ + uint8_t CCU_Rest; /* '/Data Store Memory334' */ + uint8_t CCU_Ionization; /* '/Data Store Memory335' */ + uint8_t sleep_model; /* '/Data Store Memory338' */ + uint8_t Blower_logic_FL; /* '/Data Store Memory37' */ + uint8_t Mode_logic_FL; /* '/Data Store Memory39' */ + uint8_t Blower_RL; /* '/Data Store Memory49' */ + uint8_t Mode_RR; /* '/Data Store Memory50' */ + uint8_t Mode_RL; /* '/Data Store Memory51' */ + uint8_t Mode_logic_RR; /* '/Data Store Memory54' */ + uint8_t CCU_ActuatorErrR_Stat_private;/* '/Data Store Memory67' */ + uint8_t CCU_SET_FOOT_FL; /* '/Data Store Memory76' */ + uint8_t CCU_SET_FOOT_FR; /* '/Data Store Memory77' */ + uint8_t CCU_MODE_FL; /* '/Data Store Memory78' */ + uint8_t CCU_DEF_FL; /* '/Data Store Memory84' */ + uint8_t CCU_FACE_FL; /* '/Data Store Memory85' */ + uint8_t CCU_FOOT_FL; /* '/Data Store Memory86' */ + uint8_t CCU_MODE_FR; /* '/Data Store Memory87' */ + uint8_t CCU_DEF_FR; /* '/Data Store Memory88' */ + uint8_t CCU_FACE_FR; /* '/Data Store Memory89' */ + uint8_t CCU_FOOT_FR; /* '/Data Store Memory90' */ + uint8_t CCU_BLOWERS_FL; /* '/Data Store Memory91' */ + uint8_t CCU_BLOWERS_FR; /* '/Data Store Memory92' */ + uint8_t CCU_AUTOMODE_FR; /* '/Data Store Memory93' */ + uint8_t CCU_AUTOMODE_FL; /* '/Data Store Memory94' */ + uint8_t CCU_RECIRC; /* '/Data Store Memory95' */ + uint8_t CCU_AC_FRONT; /* '/Data Store Memory98' */ + uint8_t is_active_c618_HVAC_model; + /* '/Synchronization stateflow chart' */ + uint8_t is_c618_HVAC_model; /* '/Synchronization stateflow chart' */ + uint8_t is_running; /* '/MATLAB Function1' */ + uint8_t is_active_c248_HVAC_model; /* '/Chart' */ + uint8_t is_c248_HVAC_model; /* '/Chart' */ + uint8_t is_active_c836_HVAC_model; /* '/Full_Rec_Active' */ + uint8_t is_c836_HVAC_model; /* '/Full_Rec_Active' */ + uint8_t is_active_c837_HVAC_model; /* '/Defrost_Active' */ + uint8_t is_c837_HVAC_model; /* '/Defrost_Active' */ + uint8_t is_active_c782_HVAC_model; /* '/AC_Max_Active' */ + uint8_t is_c782_HVAC_model; /* '/AC_Max_Active' */ + uint8_t is_active_c777_HVAC_model; /* '/Zone_Climate_Logic_Auto_FL4' */ + uint8_t is_c777_HVAC_model; /* '/Zone_Climate_Logic_Auto_FL4' */ + uint8_t is_AC_SUB; /* '/Zone_Climate_Logic_Auto_FL4' */ + uint8_t is_DEF_SUB; /* '/Zone_Climate_Logic_Auto_FL4' */ + uint8_t is_FACE_SUB; /* '/Zone_Climate_Logic_Auto_FL4' */ + uint8_t is_FOOT_SUB; /* '/Zone_Climate_Logic_Auto_FL4' */ + uint8_t is_AC_SUB_a; /* '/Zone_Climate_Logic_Auto_FL4' */ + uint8_t is_active_c681_HVAC_model; /* '/Zone_Climate_Logic_Auto_FL1' */ + uint8_t is_c681_HVAC_model; /* '/Zone_Climate_Logic_Auto_FL1' */ + uint8_t is_AC_SUB_c; /* '/Zone_Climate_Logic_Auto_FL1' */ + uint8_t is_DEF_SUB_i; /* '/Zone_Climate_Logic_Auto_FL1' */ + uint8_t is_FACE_SUB_o; /* '/Zone_Climate_Logic_Auto_FL1' */ + uint8_t is_FOOT_SUB_f; /* '/Zone_Climate_Logic_Auto_FL1' */ + uint8_t is_AC_SUB_co; /* '/Zone_Climate_Logic_Auto_FL1' */ + uint8_t is_active_c621_HVAC_model; /* '/A//C Control' */ + uint8_t is_PRESSURE_MONITOR; /* '/A//C Control' */ + uint8_t is_FRONT_CONTOUR; /* '/A//C Control' */ + uint8_t is_REAR_CONTOUR; /* '/A//C Control' */ + uint8_t is_CHILLER_CONTOUR; /* '/A//C Control' */ + uint8_t is_E_COMP_MANAGER; /* '/A//C Control' */ + uint8_t is_COMP_PROTECTION; /* '/A//C Control' */ + uint8_t is_active_c834_HVAC_model; /* '/Spd_OSA_Trigger' */ + uint8_t is_c834_HVAC_model; /* '/Spd_OSA_Trigger' */ + uint8_t is_active_c776_HVAC_model; /* '/Partial REC' */ + uint8_t is_c776_HVAC_model; /* '/Partial REC' */ + uint8_t is_PARTIAL_REC_ON; /* '/Partial REC' */ + uint8_t is_COND_2; /* '/Partial REC' */ + uint8_t is_active_c775_HVAC_model; /* '/13,1,3,15 Valve control' */ + uint8_t is_ThreeWay_Logic; /* '/13,1,3,15 Valve control' */ + uint8_t is_TwoWay_Logic; /* '/13,1,3,15 Valve control' */ + uint8_t current_Ambient_Lv; /* '/Log Ambient Lv' */ + bool HI_logic_on; /* '/Data Store Memory48' */ + bool t_start_not_empty; /* '/MATLAB Function1' */ + bool Pressure_Condition_table_OK; /* '/A//C Control' */ + bool Chiller_Start_request; /* '/A//C Control' */ + bool Pressure_Hi_Fault; /* '/A//C Control' */ + bool FRONT_Start_request; /* '/A//C Control' */ + bool REAR_Start_request; /* '/A//C Control' */ + bool current_Ambient_Lv_not_empty; /* '/Log Ambient Lv' */ + DW_MATLABFunction sf_MATLABFunction_g;/* '/MATLAB Function' */ + DW_MATLABFunction sf_MATLABFunction_hk;/* '/MATLAB Function' */ + DW_MATLABFunction sf_MATLABFunction_h;/* '/MATLAB Function' */ + DW_Zone_Climate_Logic_Auto_FL2 sf_Zone_Climate_Logic_Auto_FL3;/* '/Zone_Climate_Logic_Auto_FL3' */ + DW_Zone_Climate_Logic_Auto_FL2 sf_Zone_Climate_Logic_Auto_FL2;/* '/Zone_Climate_Logic_Auto_FL2' */ + DW_Level2_j Level5_ph; /* '/Level 5' */ + DW_Level2_j Level4_b; /* '/Level 4' */ + DW_Level2_j Level3_p; /* '/Level 3' */ + DW_Level2_j Level2_f0; /* '/Level 2' */ + DW_Level0_hr Level1_hm; /* '/Level 1' */ + DW_Level0_hr Level0_ad; /* '/Level 0' */ + DW_Level4_h Level5_i; /* '/Level 5' */ + DW_Level4_h Level4_m5; /* '/Level 4' */ + DW_MATLABFunction1 sf_MATLABFunction1_c;/* '/MATLAB Function1' */ + DW_MATLABFunction1 sf_MATLABFunction1_m3;/* '/MATLAB Function1' */ + DW_Level0_h Level1_l; /* '/Level 1' */ + DW_Level0_h Level0_gj; /* '/Level 0' */ + DW_MATLABFunction1_f sf_MATLABFunction1_j2;/* '/MATLAB Function1' */ + DW_Level3 Level4_l; /* '/Level 4' */ + DW_Level3 Level3_d; /* '/Level 3' */ + DW_MATLABFunction1_f sf_MATLABFunction1_i2;/* '/MATLAB Function1' */ + DW_MATLABFunction1_f sf_MATLABFunction1_m;/* '/MATLAB Function1' */ + DW_MATLABFunction1_f sf_MATLABFunction1_p;/* '/MATLAB Function1' */ + DW_MATLABFunction1_f sf_MATLABFunction1_h;/* '/MATLAB Function1' */ + DW_MATLABFunction1_f sf_MATLABFunction1_d;/* '/MATLAB Function1' */ + DW_MATLABFunction1_f sf_MATLABFunction1_j;/* '/MATLAB Function1' */ + DW_MATLABFunction1 sf_MATLABFunction1_n;/* '/MATLAB Function1' */ +} DW; + +/* Invariant block signals for system '/If Action Subsystem1' */ +typedef struct { + const uint8_t DataTypeConversion[9]; /* '/Data Type Conversion' */ +} ConstB_IfActionSubsystem1_j; + +/* Invariant block signals (default storage) */ +typedef struct { + ConstB_IfActionSubsystem1_j IfActionSubsystem1_fn;/* '/If Action Subsystem1' */ + ConstB_IfActionSubsystem1_j IfActionSubsystem1_c1;/* '/If Action Subsystem1' */ + ConstB_IfActionSubsystem1_j IfActionSubsystem1_hm;/* '/If Action Subsystem1' */ +} ConstB; + +/* Constant parameters (default storage) */ +typedef struct { + /* Expression: ADC_Data_Initial + * Referenced by: '/Data Store Memory42' + */ + CmdBusADCData DataStoreMemory42_InitialValue; + + /* Pooled Parameter (Expression: [850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 836 818 800 784 769 754 740 727 714 702 691 680 670 659 650 640 631 622 614 606 598 590 583 575 568 561 555 548 542 536 530 524 518 512 507 501 496 491 486 481 476 471 466 462 457 453 448 444 440 436 431 427 423 420 416 412 408 405 401 397 394 390 387 384 380 377 374 370 367 364 361 358 355 352 349 346 343 340 338 335 332 329 327 324 321 319 316 314 311 309 306 304 301 299 297 294 292 289 287 285 283 280 278 276 274 272 269 267 265 263 261 259 257 255 253 251 249 247 245 243 241 239 237 235 234 232 230 228 226 224 223 221 219 217 216 214 212 210 209 207 205 204 202 200 199 197 195 194 192 191 189 187 186 184 183 181 180 178 177 175 174 172 171 169 168 166 165 163 162 161 159 158 156 155 153 152 151 149 148 147 145 144 143 141 140 139 137 136 135 133 132 131 129 128 127 126 124 123 122 121 119 118 117 116 115 113 112 111 110 109 107 106 105 104 103 101 100 99 98 97 96 95 93 92 91 90 89 88 87 86 84 83 82 81 80 79 78 77 76 75 74 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 29 28 27 26 25 24 23 22 21 20 19 18 17 17 16 15 14 13 12 11 10 9 8 8 7 6 5 4 3 2 1 0 0 0 -1 -2 -3 -4 -5 -5 -6 -7 -8 -9 -10 -11 -11 -12 -13 -14 -15 -16 -17 -17 -18 -19 -20 -21 -22 -22 -23 -24 -25 -26 -27 -27 -28 -29 -30 -31 -31 -32 -33 -34 -35 -36 -36 -37 -38 -39 -40 -40 -41 -42 -43 -44 -44 -45 -46 -47 -47 -48 -49 -50 -51 -51 -52 -53 -54 -55 -55 -56 -57 -58 -58 -59 -60 -61 -62 -62 -63 -64 -65 -65 -66 -67 -68 -68 -69 -70 -71 -71 -72 -73 -74 -74 -75 -76 -77 -77 -78 -79 -80 -80 -81 -82 -83 -83 -84 -85 -86 -86 -87 -88 -89 -89 -90 -91 -92 -92 -93 -94 -95 -95 -96 -97 -97 -98 -99 -100 -100 -101 -102 -103 -103 -104 -105 -105 -106 -107 -108 -108 -109 -110 -111 -111 -112 -113 -113 -114 -115 -116 -116 -117 -118 -118 -119 -120 -121 -121 -122 -123 -123 -124 -125 -126 -126 -127 -128 -128 -129 -130 -131 -131 -132 -133 -133 -134 -135 -136 -136 -137 -138 -138 -139 -140 -140 -141 -142 -143 -143 -144 -145 -145 -146 -147 -148 -148 -149 -150 -150 -151 -152 -152 -153 -154 -155 -155 -156 -157 -157 -158 -159 -159 -160 -161 -162 -162 -163 -164 -164 -165 -166 -166 -167 -168 -169 -169 -170 -171 -171 -172 -173 -173 -174 -175 -176 -176 -177 -178 -178 -179 -180 -180 -181 -182 -183 -183 -184 -185 -185 -186 -187 -187 -188 -189 -189 -190 -191 -192 -192 -193 -194 -194 -195 -196 -196 -197 -198 -199 -199 -200 -201 -201 -202 -203 -204 -204 -205 -206 -206 -207 -208 -208 -209 -210 -211 -211 -212 -213 -213 -214 -215 -216 -216 -217 -218 -218 -219 -220 -221 -221 -222 -223 -223 -224 -225 -226 -226 -227 -228 -228 -229 -230 -231 -231 -232 -233 -233 -234 -235 -236 -236 -237 -238 -238 -239 -240 -241 -241 -242 -243 -244 -244 -245 -246 -246 -247 -248 -249 -249 -250 -251 -252 -252 -253 -254 -255 -255 -256 -257 -257 -258 -259 -260 -260 -261 -262 -263 -263 -264 -265 -266 -266 -267 -268 -269 -269 -270 -271 -272 -272 -273 -274 -275 -275 -276 -277 -278 -279 -279 -280 -281 -282 -282 -283 -284 -285 -285 -286 -287 -288 -289 -289 -290 -291 -292 -292 -293 -294 -295 -296 -296 -297 -298 -299 -300 -300 -301 -302 -303 -304 -304 -305 -306 -307 -308 -308 -309 -310 -311 -312 -313 -313 -314 -315 -316 -317 -318 -318 -319 -320 -321 -322 -323 -323 -324 -325 -326 -327 -328 -329 -329 -330 -331 -332 -333 -334 -335 -335 -336 -337 -338 -339 -340 -341 -342 -342 -343 -344 -345 -346 -347 -348 -349 -350 -351 -351 -352 -353 -354 -355 -356 -357 -358 -359 -360 -361 -362 -363 -364 -364 -365 -366 -367 -368 -369 -370 -371 -372 -373 -374 -375 -376 -377 -378 -379 -380 -381 -382 -383 -384 -385 -386 -387 -388 -389 -390 -391 -392 -393 -394 -395 -396 -398 -399 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 + ]) + * Referenced by: + * '/1-D Lookup Table' + * '/1-D Lookup Table' + */ + double pooled8[1024]; + + /* Expression: [zeros(1, 85), linspace(0.268534, 390.3364, 1024-85)] + * Referenced by: '/1-D Lookup Table' + */ + double uDLookupTable_tableData[1024]; + + /* Pooled Parameter (Expression: Incar_Temp_Table) + * Referenced by: + * '/1-D Lookup Table2' + * '/1-D Lookup Table4' + * '/1-D Lookup Table1' + * '/1-D Lookup Table3' + */ + double pooled37[1024]; + + /* Pooled Parameter (Expression: [17 18 19 20 21 22 23 24 25 26 27 28 29]) + * Referenced by: + * '/ Left' + * '/ Right' + */ + uint32_t pooled48[2]; + + /* Pooled Parameter (Expression: [170:10:290]) + * Referenced by: + * '/1-D Lookup Table' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table3' + * '/1-D Lookup Table4' + * '/1-D Lookup Table5' + * '/1-D Lookup Table' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table3' + * '/1-D Lookup Table4' + * '/1-D Lookup Table5' + * '/1-D Lookup Table' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table3' + * '/1-D Lookup Table4' + * '/1-D Lookup Table5' + * '/1-D Lookup Table' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table3' + * '/1-D Lookup Table4' + * '/1-D Lookup Table5' + * '/1-D Lookup Table' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table3' + * '/1-D Lookup Table4' + * '/1-D Lookup Table5' + * '/1-D Lookup Table' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table3' + * '/1-D Lookup Table4' + * '/1-D Lookup Table5' + * '/1-D Lookup Table' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table3' + * '/1-D Lookup Table4' + * '/1-D Lookup Table5' + * '/1-D Lookup Table' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table3' + * '/1-D Lookup Table4' + * '/1-D Lookup Table5' + * '/1-D Lookup Table' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table3' + * '/1-D Lookup Table4' + * '/1-D Lookup Table5' + * '/1-D Lookup Table' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table3' + * '/1-D Lookup Table4' + * '/1-D Lookup Table5' + * '/1-D Lookup Table' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table3' + * '/1-D Lookup Table4' + * '/1-D Lookup Table5' + * '/1-D Lookup Table' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table3' + * '/1-D Lookup Table4' + * '/1-D Lookup Table5' + */ + int16_t pooled51[13]; + + /* Pooled Parameter (Expression: [5, 4, 3, 2, 1, 0]) + * Referenced by: + * '/1-D Lookup Table' + * '/Get LVL for temp' + */ + int16_t pooled53[6]; + + /* Computed Parameter: GetLVLfortemp_bp01Data + * Referenced by: '/Get LVL for temp' + */ + int16_t GetLVLfortemp_bp01Data[6]; + + /* Pooled Parameter (Expression: [0;1;2;3;4;5]) + * Referenced by: + * '/ Left' + * '/ Right' + */ + int16_t pooled65[13]; + + /* Pooled Parameter (Expression: [850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 848 845 841 838 834 831 827 824 821 818 814 811 808 805 802 799 796 793 790 787 784 781 778 775 772 769 767 764 761 758 756 753 750 748 745 742 740 737 735 732 730 727 725 722 720 717 715 713 710 708 706 703 701 699 696 694 692 690 688 685 683 681 679 677 675 673 670 668 666 664 662 660 658 656 654 652 650 648 646 644 642 640 638 637 635 633 631 629 627 625 624 622 620 618 616 614 613 611 609 607 606 604 602 600 599 597 595 594 592 590 589 587 585 584 582 580 579 577 576 574 572 571 569 568 566 564 563 561 560 558 557 555 554 552 551 549 548 546 545 543 542 540 539 537 536 534 533 532 530 529 527 526 524 523 522 520 519 517 516 515 513 512 511 509 508 507 505 504 503 501 500 499 497 496 495 493 492 491 489 488 487 485 484 483 482 480 479 478 477 475 474 473 472 470 469 468 467 465 464 463 462 460 459 458 457 456 454 453 452 451 450 448 447 446 445 444 442 441 440 439 438 437 435 434 433 432 431 430 429 427 426 425 424 423 422 421 420 418 417 416 415 414 413 412 411 410 408 407 406 405 404 403 402 401 400 399 398 396 395 394 393 392 391 390 389 388 387 386 385 384 383 382 381 380 378 377 376 375 374 373 372 371 370 369 368 367 366 365 364 363 362 361 360 359 358 357 356 355 354 353 352 351 350 349 348 347 346 345 344 343 342 341 340 339 338 337 336 335 334 333 332 331 330 329 328 327 326 325 324 324 323 322 321 320 319 318 317 316 315 314 313 312 311 310 309 308 307 306 305 305 304 303 302 301 300 299 298 297 296 295 294 293 292 291 291 290 289 288 287 286 285 284 283 282 281 280 279 279 278 277 276 275 274 273 272 271 270 269 268 268 267 266 265 264 263 262 261 260 259 259 258 257 256 255 254 253 252 251 250 250 249 248 247 246 245 244 243 242 241 241 240 239 238 237 236 235 234 233 233 232 231 230 229 228 227 226 225 224 224 223 222 221 220 219 218 217 217 216 215 214 213 212 211 210 209 209 208 207 206 205 204 203 202 201 201 200 199 198 197 196 195 194 194 193 192 191 190 189 188 187 186 186 185 184 183 182 181 180 179 179 178 177 176 175 174 173 172 171 171 170 169 168 167 166 165 164 163 163 162 161 160 159 158 157 156 155 155 154 153 152 151 150 149 148 147 147 146 145 144 143 142 141 140 139 139 138 137 136 135 134 133 132 131 130 130 129 128 127 126 125 124 123 122 121 121 120 119 118 117 116 115 114 113 112 112 111 110 109 108 107 106 105 104 103 102 101 101 100 99 98 97 96 95 94 93 92 91 90 89 88 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 3 2 1 0 0 -1 -2 -3 -4 -5 -6 -7 -9 -10 -11 -12 -13 -14 -15 -16 -17 -19 -20 -21 -22 -23 -24 -25 -26 -28 -29 -30 -31 -32 -33 -34 -36 -37 -38 -39 -40 -42 -43 -44 -45 -46 -47 -49 -50 -51 -52 -54 -55 -56 -57 -58 -60 -61 -62 -63 -65 -66 -67 -68 -70 -71 -72 -74 -75 -76 -77 -79 -80 -81 -83 -84 -85 -87 -88 -89 -91 -92 -93 -95 -96 -98 -99 -100 -102 -103 -105 -106 -108 -109 -110 -112 -113 -115 -116 -118 -119 -121 -122 -124 -125 -127 -128 -130 -131 -133 -134 -136 -138 -139 -141 -142 -144 -146 -147 -149 -151 -152 -154 -156 -157 -159 -161 -162 -164 -166 -168 -169 -171 -173 -175 -177 -179 -180 -182 -184 -186 -188 -190 -192 -194 -196 -198 -200 -202 -204 -206 -208 -210 -212 -214 -216 -218 -221 -223 -225 -227 -229 -232 -234 -236 -239 -241 -243 -246 -248 -251 -253 -256 -258 -261 -264 -266 -269 -272 -275 -277 -280 -283 -286 -289 -292 -295 -298 -301 -304 -308 -311 -314 -318 -321 -325 -328 -332 -336 -339 -343 -347 -351 -355 -359 -364 -368 -373 -377 -382 -387 -392 -397 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400]) + * Referenced by: + * '/1-D Lookup Table7' + * '/1-D Lookup Table4' + */ + int16_t pooled66[1024]; + + /* Pooled Parameter (Expression: [0:4:4095]) + * Referenced by: + * '/1-D Lookup Table7' + * '/1-D Lookup Table4' + */ + int16_t pooled67[1024]; + + /* Pooled Parameter (Expression: [170:10:290]) + * Referenced by: + * '/1-D Lookup Table' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table3' + * '/1-D Lookup Table4' + * '/1-D Lookup Table5' + * '/1-D Lookup Table' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table3' + * '/1-D Lookup Table4' + * '/1-D Lookup Table5' + * '/1-D Lookup Table' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table3' + * '/1-D Lookup Table4' + * '/1-D Lookup Table5' + * '/1-D Lookup Table' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table3' + * '/1-D Lookup Table4' + * '/1-D Lookup Table5' + * '/1-D Lookup Table10' + * '/1-D Lookup Table11' + * '/1-D Lookup Table6' + * '/1-D Lookup Table7' + * '/1-D Lookup Table8' + * '/1-D Lookup Table9' + * '/1-D Lookup Table10' + * '/1-D Lookup Table11' + * '/1-D Lookup Table6' + * '/1-D Lookup Table7' + * '/1-D Lookup Table8' + * '/1-D Lookup Table9' + * '/1-D Lookup Table10' + * '/1-D Lookup Table11' + * '/1-D Lookup Table6' + * '/1-D Lookup Table7' + * '/1-D Lookup Table8' + * '/1-D Lookup Table9' + * '/1-D Lookup Table1' + * '/1-D Lookup Table12' + * '/1-D Lookup Table2' + * '/1-D Lookup Table3' + * '/1-D Lookup Table4' + * '/1-D Lookup Table5' + */ + uint16_t pooled79[13]; + + /* Pooled Parameter (Expression: [0:4:4092]) + * Referenced by: + * '/1-D Lookup Table' + * '/1-D Lookup Table' + * '/1-D Lookup Table' + * '/1-D Lookup Table2' + * '/1-D Lookup Table4' + * '/1-D Lookup Table1' + * '/1-D Lookup Table3' + */ + uint16_t pooled80[1024]; + + /* Computed Parameter: uDLookupTable1_bp01Data + * Referenced by: '/1-D Lookup Table1' + */ + uint16_t uDLookupTable1_bp01Data[2]; + + /* Pooled Parameter (Expression: [1050 1250 1175 1195 1315 1300 1485 1440 1195]) + * Referenced by: + * '/Data Store Memory121' + * '/ACT1' + */ + uint16_t pooled87[9]; + + /* Computed Parameter: ACT1_Value + * Referenced by: '/ACT1' + */ + uint16_t ACT1_Value[6]; + + /* Computed Parameter: ACT1_Value_m + * Referenced by: '/ACT1' + */ + uint16_t ACT1_Value_m[8]; + + /* Computed Parameter: DataStoreMemory123_InitialValue + * Referenced by: '/Data Store Memory123' + */ + uint16_t DataStoreMemory123_InitialValue[9]; + + /* Computed Parameter: DataStoreMemory124_InitialValue + * Referenced by: '/Data Store Memory124' + */ + uint16_t DataStoreMemory124_InitialValue[9]; + + /* Pooled Parameter (Expression: [1:7]) + * Referenced by: + * '/1-D Lookup Table3' + * '/1-D Lookup Table4' + * '/1-D Lookup Table5' + */ + uint8_t pooled109[7]; + + /* Pooled Parameter (Expression: [0:7]) + * Referenced by: + * '/1-D Lookup Table' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + */ + uint8_t pooled110[8]; + + /* Pooled Parameter (Expression: [10:10:110]) + * Referenced by: + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table' + * '/1-D Lookup Table2' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table' + * '/1-D Lookup Table2' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table' + * '/1-D Lookup Table2' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table' + * '/1-D Lookup Table2' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table' + * '/1-D Lookup Table2' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table' + * '/1-D Lookup Table2' + */ + uint8_t pooled111[11]; + + /* Pooled Parameter (Expression: [1 2 3 4 5 6 7 8 9]) + * Referenced by: + * '/Constant3' + * '/Constant5' + * '/Constant5' + * '/Constant5' + * '/Constant5' + * '/Constant5' + * '/Constant5' + */ + uint8_t pooled119[9]; + + /* Computed Parameter: Constant3_Value + * Referenced by: '/Constant3' + */ + uint8_t Constant3_Value[6]; + + /* Computed Parameter: Constant3_Value_d + * Referenced by: '/Constant3' + */ + uint8_t Constant3_Value_d[8]; + + /* Pooled Parameter (Expression: ) + * Referenced by: + * '/ Left' + * '/ Right' + */ + uint8_t pooled129[6]; + + /* Pooled Parameter (Expression: [0:6]) + * Referenced by: + * '/1-D Lookup Table' + * '/1-D Lookup Table' + */ + uint8_t pooled130[7]; +} ConstP; + +/* External outputs (root outports fed by signals with default storage) */ +typedef struct { + CmdBusError CCU_Errors_model; /* '/CCU_Errors_model' */ + uint8_t dtc_state_error_model[127]; /* '/dtc_state_error_model' */ + dbgCAN_dbg_Act0_Bus dbgCAN_dbg_Act0_model;/* '/dbgCAN_dbg_Act0_model' */ + dbgCAN_dbg_Act1_Bus dbgCAN_dbg_Act1_model;/* '/dbgCAN_dbg_Act1_model' */ + dbgCAN_dbg_Act2_Bus dbgCAN_dbg_Act2_model;/* '/dbgCAN_dbg_Act2_model' */ + CmdCAN_CCU_STAT1_Bus CCU_Stat1_model;/* '/CCU_Stat1_model' */ + CmdBusPWMGet PWM_Get_f; /* '/PWM_Get' */ + dbgCAN_dbg_Sen_Duct_Bus dbgCAN_dbg_Sen_Duct_model;/* '/dbgCAN_dbg_Sen_Duct_model' */ + dbgCAN_dbg_dbg_Sen_Eva_Bus dbgCAN_dbg_Sen_Eva_model;/* '/dbgCAN_dbg_Sen_Eva_model' */ + dbgCAN_dbg_Logic_Blower_Bus dbgCAN_dbg_Logic_Blower_model; + /* '/dbgCAN_dbg_Logic_Blower_model' */ + dbgCAN_dbg_Sen_Amb_Bus dbgCAN_dbg_Sen_Amb_model;/* '/dbgCAN_dbg_Sen_Amb_model' */ + CmdCAN_CCU_STAT2_Bus CCU_Stat2_model;/* '/CCU_Stat2_model' */ + dbgCAN_dbg_Sen_Incar_Bus dbgCAN_dbg_Sen_Incar_model;/* '/dbgCAN_dbg_Sen_Incar_model' */ + dbgCAN_dbg_Sen_0_Bus dbgCAN_dbg_Sen_0_model;/* '/dbgCAN_dbg_Sen_0_model' */ + tPowerEnable_Bus PowerEnable_Model; /* '/PowerEnable_Model' */ + dbg_Logic_Ac_Bus dbg_Logic_Ac_model; /* '/dbg_Logic_Ac_model' */ + CCU_HVC_Req_Msg_Bus CCUCAN_HVC_REQ_MSG_MODEL;/* '/CCUCAN_HVC_REQ_MSG_MODEL' */ + dbgCAN_CCU_IO_Bus dbgCAN_CCU_IO_model;/* '/dbgCAN_CCU_IO_model' */ + CCU_Msg3_Bus CCU_Msg3_model; /* '/CCU_Msg3_model' */ + dbgCAN_Logic_Rec_Bus dbgCAN_Logic_Rec_model;/* '/dbgCAN_Logic_Rec_model' */ + dbgCAN_Logic_State_Bus dbgCAN_Logic_State_model;/* '/dbgCAN_Logic_State_model' */ + CCU_Msg1_Bus CCU_Msg1_model; /* '/CCU_Msg1_model' */ + dbg_Auto_Duct_Bus dbgCAN_Auto_Duct_model;/* '/dbgCAN_Auto_Duct_model' */ + dbg_Auto_AF_Bus dbgCAN_Auto_AF_model;/* '/dbgCAN_Auto_AF_model' */ + LIN4_CCU_Req_Bus LIN4_CCU_Req_Model; /* '/LIN4_CCU_Req_Model' */ + dbg_Logic_Valve_Bus dbg_Logic_Valve_model;/* '/dbg_Logic_Valve_model' */ + ActuatorCmdBus Actuator_Ch0_Command_Model_out; + /* '/Actuator_Ch0_Command_Model_out' */ + ActuatorCmdBus Actuator_Ch1_Command_Mode_out; + /* '/Actuator_Ch1_Command_Mode_out' */ + ActuatorCmdBus Actuator_Ch2_Command_Model_out; + /* '/Actuator_Ch2_Command_Model_out' */ + dbg_LIN_AirQS_Stat_t_Bus dbg_LIN_AirQS_Stat_t_model;/* '/dbg_LIN_AirQS_Stat_t_model' */ + dbg_LIN_DRS_Stat_t_Bus dbg_LIN_DRS_Stat_t_model;/* '/dbg_LIN_DRS_Stat_t_model' */ + dbg_Drs_t_Bus dbg_Drs_t_model; /* '/dbg_Drs_t_model' */ + dbg_Logic_Valve_Plus_Bus dbg_Logic_Valve_Plus_model;/* '/dbg_Logic_Valve_Plus_model' */ + CmdCAN_CCU_STAT3_Bus CCU_Stat3_model;/* '/CCU_Stat3_model' */ + dbg_LIN_Aroma_Stat_t_Bus dbg_LIN_Aroma_Stat_t_model;/* '/dbg_LIN_Aroma_Stat_t_model' */ + dbg_LIN_Ionizer_Stat_t_Bus dbg_LIN_Ionizer_Stat_t_model; + /* '/dbg_LIN_Ionizer_Stat_t_model' */ + uint8_t DRS_output[8]; /* '/DRS_output' */ + Status_Duct_Select_Bus Status_Duct_Select_model_IO; + /* '/Status_Duct_Select_model_IO' */ + Status_Eva_Tgt_Bus Status_Eva_Tgt_model_IO;/* '/Status_Eva_Tgt_model_IO' */ + Status_Sensor_Bus Status_Sensort_model_IO;/* '/Status_Sensort_model_IO' */ + Status_Actuator_Bus Status_Actuator_model_IO;/* '/Status_Actuator_model_IO' */ + Status_Duct_Tgt_Bus Status_Duct_Tgt_model_IO;/* '/Status_Duct_Tgt_model_IO' */ +} ExtY; + +/* Real-time Model Data Structure */ +struct tag_RTM { + const char * volatile errorStatus; +}; + +/* Block signals (default storage) */ +extern B rtB; + +/* Block states (default storage) */ +extern DW rtDW; + +/* External outputs (root outports fed by signals with default storage) */ +extern ExtY rtY; + +/* External data declarations for dependent source files */ +extern const CmdBusPWMGet HVAC_model_rtZCmdBusPWMGet;/* CmdBusPWMGet ground */ +extern const CmdBusStatus HVAC_model_rtZCmdBusStatus;/* CmdBusStatus ground */ +extern const ActuatorCmdBus HVAC_model_rtZActuatorCmdBus;/* ActuatorCmdBus ground */ +extern const CmdBusError HVAC_model_rtZCmdBusError;/* CmdBusError ground */ +extern const ActuatorCmdBusInput HVAC_model_rtZActuatorCmdBusInput;/* ActuatorCmdBusInput ground */ +extern const ConstB rtConstB; /* constant block i/o */ + +/* Constant parameters (default storage) */ +extern const ConstP rtConstP; + +/* + * Exported States + * + * Note: Exported states are block states with an exported global + * storage class designation. Code generation will declare the memory for these + * states and exports their symbols. + * + */ +extern ActuatorCmdBus Actuator_Ch0_Command_Model;/* '/Data Store Memory272' */ +extern ActuatorCmdBus Actuator_Ch1_Command_Model;/* '/Data Store Memory273' */ +extern ActuatorCmdBus Actuator_Ch2_Command_Model;/* '/Data Store Memory274' */ +extern ActuatorCmdBusInput Actuator_Ch0_Status_Model;/* '/Data Store Memory61' */ +extern ActuatorCmdBusInput Actuator_Ch1_Status_Model;/* '/Data Store Memory62' */ +extern ActuatorCmdBusInput Actuator_Ch2_Status_Model;/* '/Data Store Memory63' */ +extern CmdBusStatus Status_Sensor_Model;/* '/Data Store Memory197' */ +extern CmdBusError CCU_Errors_Model; /* '/Data Store Memory3' */ +extern CmdBusPWMGet PWM_Get; /* '/Data Store Memory128' */ + +/* Model entry point functions */ +extern void HVAC_model_initialize(void); +extern void HVAC_model_step(void); +extern void HVAC_model_terminate(void); + +/* Real-time Model object */ +extern RT_MODEL *const rtM; + +/*- + * These blocks were eliminated from the model due to optimizations: + * + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Scope' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Gain1' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display13' : Unused code path elimination + * Block '/Display14' : Unused code path elimination + * Block '/Display15' : Unused code path elimination + * Block '/Display16' : Unused code path elimination + * Block '/Display18' : Unused code path elimination + * Block '/Display19' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display13' : Unused code path elimination + * Block '/Display14' : Unused code path elimination + * Block '/Display15' : Unused code path elimination + * Block '/Display16' : Unused code path elimination + * Block '/Display18' : Unused code path elimination + * Block '/Display19' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display13' : Unused code path elimination + * Block '/Display14' : Unused code path elimination + * Block '/Display15' : Unused code path elimination + * Block '/Display16' : Unused code path elimination + * Block '/Display17' : Unused code path elimination + * Block '/Display18' : Unused code path elimination + * Block '/Display19' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display13' : Unused code path elimination + * Block '/Display14' : Unused code path elimination + * Block '/Display15' : Unused code path elimination + * Block '/Display16' : Unused code path elimination + * Block '/Display17' : Unused code path elimination + * Block '/Display18' : Unused code path elimination + * Block '/Display19' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display13' : Unused code path elimination + * Block '/Display14' : Unused code path elimination + * Block '/Display15' : Unused code path elimination + * Block '/Display16' : Unused code path elimination + * Block '/Display18' : Unused code path elimination + * Block '/Display19' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display13' : Unused code path elimination + * Block '/Display14' : Unused code path elimination + * Block '/Display15' : Unused code path elimination + * Block '/Display16' : Unused code path elimination + * Block '/Display18' : Unused code path elimination + * Block '/Display19' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display13' : Unused code path elimination + * Block '/Display14' : Unused code path elimination + * Block '/Display15' : Unused code path elimination + * Block '/Display16' : Unused code path elimination + * Block '/Display17' : Unused code path elimination + * Block '/Display18' : Unused code path elimination + * Block '/Display19' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display13' : Unused code path elimination + * Block '/Display14' : Unused code path elimination + * Block '/Display15' : Unused code path elimination + * Block '/Display16' : Unused code path elimination + * Block '/Display17' : Unused code path elimination + * Block '/Display18' : Unused code path elimination + * Block '/Display19' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/t . ' : Unused code path elimination + * Block '/ t ' : Unused code path elimination + * Block '/ t ' : Unused code path elimination + * Block '/ Left' : Unused code path elimination + * Block '/ Right' : Unused code path elimination + * Block '/ ' : Unused code path elimination + * Block '/ L' : Unused code path elimination + * Block '/ R' : Unused code path elimination + * Block '/' : Unused code path elimination + * Block '/Constant3' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display13' : Unused code path elimination + * Block '/Display14' : Unused code path elimination + * Block '/Display15' : Unused code path elimination + * Block '/Display16' : Unused code path elimination + * Block '/Display17' : Unused code path elimination + * Block '/Display18' : Unused code path elimination + * Block '/Display19' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display20' : Unused code path elimination + * Block '/Display21' : Unused code path elimination + * Block '/Display22' : Unused code path elimination + * Block '/Display23' : Unused code path elimination + * Block '/Display24' : Unused code path elimination + * Block '/Display25' : Unused code path elimination + * Block '/Display26' : Unused code path elimination + * Block '/Display27' : Unused code path elimination + * Block '/Display28' : Unused code path elimination + * Block '/Display29' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display30' : Unused code path elimination + * Block '/Display31' : Unused code path elimination + * Block '/Display32' : Unused code path elimination + * Block '/Display33' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Relational Operator3' : Unused code path elimination + * Block '/not LO or HI' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/AUTO' : Unused code path elimination + * Block '/Constant' : Unused code path elimination + * Block '/Constant1' : Unused code path elimination + * Block '/LO' : Unused code path elimination + * Block '/Logical Operator1' : Unused code path elimination + * Block '/Relational Operator' : Unused code path elimination + * Block '/Relational Operator2' : Unused code path elimination + * Block '/Relational Operator3' : Unused code path elimination + * Block '/Switch' : Unused code path elimination + * Block '/Switch1' : Unused code path elimination + * Block '/exit algorithm' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/step start control front' : Unused code path elimination + * Block '/step start control rear' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display13' : Unused code path elimination + * Block '/Display14' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display13' : Unused code path elimination + * Block '/Display14' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display13' : Unused code path elimination + * Block '/Display14' : Unused code path elimination + * Block '/Display15' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display13' : Unused code path elimination + * Block '/Display14' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display13' : Unused code path elimination + * Block '/Display14' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Add' : Unused code path elimination + * Block '/Add1' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display13' : Unused code path elimination + * Block '/Display14' : Unused code path elimination + * Block '/Display15' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display15' : Unused code path elimination + * Block '/Display16' : Unused code path elimination + * Block '/Display17' : Unused code path elimination + * Block '/Display18' : Unused code path elimination + * Block '/Display19' : Unused code path elimination + * Block '/Display20' : Unused code path elimination + * Block '/Display21' : Unused code path elimination + * Block '/Display22' : Unused code path elimination + * Block '/Display23' : Unused code path elimination + * Block '/Display24' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Gain' : Unused code path elimination + * Block '/Gain1' : Unused code path elimination + * Block '/Gain2' : Unused code path elimination + * Block '/Gain3' : Unused code path elimination + * Block '/Gain4' : Unused code path elimination + * Block '/Gain5' : Unused code path elimination + * Block '/Gain6' : Unused code path elimination + * Block '/Gain7' : Unused code path elimination + * Block '/Gain8' : Unused code path elimination + * Block '/LVL t . ' : Unused code path elimination + * Block '/SET ' : Unused code path elimination + * Block '/SET ' : Unused code path elimination + * Block '/SET ' : Unused code path elimination + * Block '/SET ' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/t - ' : Unused code path elimination + * Block '/t - ' : Unused code path elimination + * Block '/t - ' : Unused code path elimination + * Block '/t - ' : Unused code path elimination + * Block '/t . ' : Unused code path elimination + * Block '/ After start control system works X sec' : Unused code path elimination + * Block '/Constant' : Unused code path elimination + * Block '/Constant1' : Unused code path elimination + * Block '/Constant2' : Unused code path elimination + * Block '/Data Type Conversion' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display13' : Unused code path elimination + * Block '/Display14' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Divide' : Unused code path elimination + * Block '/Product' : Unused code path elimination + * Block '/Delay Input1' : Unused code path elimination + * Block '/FixPt Relational Operator' : Unused code path elimination + * Block '/Compare' : Unused code path elimination + * Block '/Constant' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Subtract' : Unused code path elimination + * Block '/Switch' : Unused code path elimination + * Block '/t_start_delay_private ' : Unused code path elimination + * Block '/Relational Operator' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/LowerRelop1' : Unused code path elimination + * Block '/Switch' : Unused code path elimination + * Block '/Switch2' : Unused code path elimination + * Block '/UpperRelop' : Unused code path elimination + * Block '/Switch' : Unused code path elimination + * Block '/Unit Delay' : Unused code path elimination + * Block '/ 0.01 0.1 ' : Unused code path elimination + * Block '/ ' : Unused code path elimination + * Block '/ After start control system works X sec' : Unused code path elimination + * Block '/Constant' : Unused code path elimination + * Block '/Constant1' : Unused code path elimination + * Block '/Constant2' : Unused code path elimination + * Block '/Data Type Conversion' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display13' : Unused code path elimination + * Block '/Display14' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Divide' : Unused code path elimination + * Block '/Product' : Unused code path elimination + * Block '/Delay Input1' : Unused code path elimination + * Block '/FixPt Relational Operator' : Unused code path elimination + * Block '/Compare' : Unused code path elimination + * Block '/Constant' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Subtract' : Unused code path elimination + * Block '/Switch' : Unused code path elimination + * Block '/t_start_delay_private ' : Unused code path elimination + * Block '/Relational Operator' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/LowerRelop1' : Unused code path elimination + * Block '/Switch' : Unused code path elimination + * Block '/Switch2' : Unused code path elimination + * Block '/UpperRelop' : Unused code path elimination + * Block '/Switch' : Unused code path elimination + * Block '/Unit Delay' : Unused code path elimination + * Block '/ 0.01 0.1 ' : Unused code path elimination + * Block '/ ' : Unused code path elimination + * Block '/ ' : Unused code path elimination + * Block '/ ' : Unused code path elimination + * Block '/ ' : Unused code path elimination + * Block '/ ' : Unused code path elimination + * Block '/ ' : Unused code path elimination + * Block '/ ()' : Unused code path elimination + * Block '/ ' : Unused code path elimination + * Block '/ ' : Unused code path elimination + * Block '/ ' : Unused code path elimination + * Block '/ ()' : Unused code path elimination + * Block '/Gain1' : Unused code path elimination + * Block '/Gain2' : Unused code path elimination + * Block '/Gain3' : Unused code path elimination + * Block '/Gain4' : Unused code path elimination + * Block '/Gain5' : Unused code path elimination + * Block '/Gain6' : Unused code path elimination + * Block '/Gain7' : Unused code path elimination + * Block '/Gain8' : Unused code path elimination + * Block '/RAW t incar front left' : Unused code path elimination + * Block '/RAW t incar front right' : Unused code path elimination + * Block '/RAW t incar rear left' : Unused code path elimination + * Block '/RAW t incar rear right' : Unused code path elimination + * Block '/Data Type Conversion' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/level' : Unused code path elimination + * Block '/temp raw' : Unused code path elimination + * Block '/time passed ms' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/level' : Unused code path elimination + * Block '/temp new (C * 10)' : Unused code path elimination + * Block '/temp old' : Unused code path elimination + * Block '/temp raw' : Unused code path elimination + * Block '/time passed ms' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Data Type Conversion' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/level' : Unused code path elimination + * Block '/temp raw' : Unused code path elimination + * Block '/time passed ms' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/level' : Unused code path elimination + * Block '/temp new (C * 10)' : Unused code path elimination + * Block '/temp old' : Unused code path elimination + * Block '/temp raw' : Unused code path elimination + * Block '/time passed ms' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Data Type Conversion' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/level' : Unused code path elimination + * Block '/temp raw' : Unused code path elimination + * Block '/time passed ms' : Unused code path elimination + * Block '/AMB (C * 10)' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/level' : Unused code path elimination + * Block '/temp old' : Unused code path elimination + * Block '/temp raw' : Unused code path elimination + * Block '/time passed ms' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Data Type Conversion' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/level' : Unused code path elimination + * Block '/temp raw' : Unused code path elimination + * Block '/time passed ms' : Unused code path elimination + * Block '/AMB (C * 10)' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/level' : Unused code path elimination + * Block '/temp old' : Unused code path elimination + * Block '/temp raw' : Unused code path elimination + * Block '/time passed ms' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/t ' : Unused code path elimination + * Block '/t ' : Unused code path elimination + * Block '/t ' : Unused code path elimination + * Block '/t ' : Unused code path elimination + * Block '/ ' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display15' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display13' : Unused code path elimination + * Block '/Display14' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display13' : Unused code path elimination + * Block '/Display14' : Unused code path elimination + * Block '/Display16' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display24' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display13' : Unused code path elimination + * Block '/Display14' : Unused code path elimination + * Block '/Vtg_FL_correct L display' : Unused code path elimination + * Block '/Vtg_FL_correct ' : Unused code path elimination + * Block '/Vtg_FR_correct ' : Unused code path elimination + * Block '/Vtg_FX_correct R display' : Unused code path elimination + * Block '/ After start control system works X sec' : Unused code path elimination + * Block '/Constant' : Unused code path elimination + * Block '/Constant1' : Unused code path elimination + * Block '/Constant2' : Unused code path elimination + * Block '/Data Type Conversion' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display13' : Unused code path elimination + * Block '/Display14' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Divide' : Unused code path elimination + * Block '/Product' : Unused code path elimination + * Block '/Delay Input1' : Unused code path elimination + * Block '/FixPt Relational Operator' : Unused code path elimination + * Block '/Compare' : Unused code path elimination + * Block '/Constant' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Subtract' : Unused code path elimination + * Block '/Switch' : Unused code path elimination + * Block '/t_start_delay_private ' : Unused code path elimination + * Block '/Relational Operator' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/LowerRelop1' : Unused code path elimination + * Block '/Switch' : Unused code path elimination + * Block '/Switch2' : Unused code path elimination + * Block '/UpperRelop' : Unused code path elimination + * Block '/Switch' : Unused code path elimination + * Block '/Unit Delay' : Unused code path elimination + * Block '/ 0.01 0.1 ' : Unused code path elimination + * Block '/ ' : Unused code path elimination + * Block '/ After start control system works X sec' : Unused code path elimination + * Block '/Constant' : Unused code path elimination + * Block '/Constant1' : Unused code path elimination + * Block '/Constant2' : Unused code path elimination + * Block '/Data Type Conversion' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display13' : Unused code path elimination + * Block '/Display14' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Divide' : Unused code path elimination + * Block '/Product' : Unused code path elimination + * Block '/Delay Input1' : Unused code path elimination + * Block '/FixPt Relational Operator' : Unused code path elimination + * Block '/Compare' : Unused code path elimination + * Block '/Constant' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Subtract' : Unused code path elimination + * Block '/Switch' : Unused code path elimination + * Block '/t_start_delay_private ' : Unused code path elimination + * Block '/Relational Operator' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/LowerRelop1' : Unused code path elimination + * Block '/Switch' : Unused code path elimination + * Block '/Switch2' : Unused code path elimination + * Block '/UpperRelop' : Unused code path elimination + * Block '/Switch' : Unused code path elimination + * Block '/Unit Delay' : Unused code path elimination + * Block '/ 0.01 0.1' : Unused code path elimination + * Block '/ ' : Unused code path elimination + * Block '/Gain' : Unused code path elimination + * Block '/Gain1' : Unused code path elimination + * Block '/Gain2' : Unused code path elimination + * Block '/Gain3' : Unused code path elimination + * Block '/Gain4' : Unused code path elimination + * Block '/Gain5' : Unused code path elimination + * Block '/Gain6' : Unused code path elimination + * Block '/Gain7' : Unused code path elimination + * Block '/Gain8' : Unused code path elimination + * Block '/LVL t . ' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display13' : Unused code path elimination + * Block '/Display14' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display13' : Unused code path elimination + * Block '/Display14' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Vtg_RL_correct display' : Unused code path elimination + * Block '/Vtg_RR_correct display' : Unused code path elimination + * Block '/SET ' : Unused code path elimination + * Block '/SET ' : Unused code path elimination + * Block '/SET ' : Unused code path elimination + * Block '/SET ' : Unused code path elimination + * Block '/t - ' : Unused code path elimination + * Block '/t - ' : Unused code path elimination + * Block '/t - ' : Unused code path elimination + * Block '/t - ' : Unused code path elimination + * Block '/t . ' : Unused code path elimination + * Block '/ ' : Unused code path elimination + * Block '/ ' : Unused code path elimination + * Block '/Constant1' : Unused code path elimination + * Block '/Data Type Conversion' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Gain' : Unused code path elimination + * Block '/Gain1' : Unused code path elimination + * Block '/Gain2' : Unused code path elimination + * Block '/t . .' : Unused code path elimination + * Block '/t . .' : Unused code path elimination + * Block '/ ' : Unused code path elimination + * Block '/ t . ' : Unused code path elimination + * Block '/ ' : Unused code path elimination + * Block '/AMB (C * 10)' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/lvl' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/ABM from read' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/ABM from read' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display10' : Unused code path elimination + * Block '/Display11' : Unused code path elimination + * Block '/Display12' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display9' : Unused code path elimination + * Block '/1-D Lookup Table' : Unused code path elimination + * Block '/Constant1' : Unused code path elimination + * Block '/Constant2' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/ABM from read' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Display8' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Logical Operator' : Unused code path elimination + * Block '/Compare' : Unused code path elimination + * Block '/Constant' : Unused code path elimination + * Block '/Constant' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Constant' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Constant3' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Constant' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Constant' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Constant' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Constant9' : Unused code path elimination + * Block '/Compare' : Unused code path elimination + * Block '/Constant' : Unused code path elimination + * Block '/Compare' : Unused code path elimination + * Block '/Constant' : Unused code path elimination + * Block '/Compare' : Unused code path elimination + * Block '/Constant' : Unused code path elimination + * Block '/Multiport Switch' : Unused code path elimination + * Block '/Multiport Switch3' : Unused code path elimination + * Block '/Multiport Switch4' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Compare' : Unused code path elimination + * Block '/Constant' : Unused code path elimination + * Block '/Compare' : Unused code path elimination + * Block '/Constant' : Unused code path elimination + * Block '/Compare' : Unused code path elimination + * Block '/Constant' : Unused code path elimination + * Block '/Multiport Switch' : Unused code path elimination + * Block '/Multiport Switch3' : Unused code path elimination + * Block '/Multiport Switch4' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Compare' : Unused code path elimination + * Block '/Constant' : Unused code path elimination + * Block '/Compare' : Unused code path elimination + * Block '/Constant' : Unused code path elimination + * Block '/Compare' : Unused code path elimination + * Block '/Constant' : Unused code path elimination + * Block '/Multiport Switch' : Unused code path elimination + * Block '/Multiport Switch3' : Unused code path elimination + * Block '/Multiport Switch4' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Compare' : Unused code path elimination + * Block '/Constant' : Unused code path elimination + * Block '/Compare' : Unused code path elimination + * Block '/Constant' : Unused code path elimination + * Block '/Compare' : Unused code path elimination + * Block '/Constant' : Unused code path elimination + * Block '/Multiport Switch' : Unused code path elimination + * Block '/Multiport Switch3' : Unused code path elimination + * Block '/Multiport Switch4' : Unused code path elimination + * Block '/Delay Input2' : Unused code path elimination + * Block '/Difference Inputs1' : Unused code path elimination + * Block '/Difference Inputs2' : Unused code path elimination + * Block '/FixPt Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/LowerRelop1' : Unused code path elimination + * Block '/Switch' : Unused code path elimination + * Block '/Switch2' : Unused code path elimination + * Block '/UpperRelop' : Unused code path elimination + * Block '/Zero-Order Hold' : Unused code path elimination + * Block '/delta fall limit' : Unused code path elimination + * Block '/delta rise limit' : Unused code path elimination + * Block '/sample time' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Compare' : Unused code path elimination + * Block '/Constant' : Unused code path elimination + * Block '/Compare' : Unused code path elimination + * Block '/Constant' : Unused code path elimination + * Block '/Compare' : Unused code path elimination + * Block '/Constant' : Unused code path elimination + * Block '/Multiport Switch' : Unused code path elimination + * Block '/Multiport Switch3' : Unused code path elimination + * Block '/Multiport Switch4' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Compare' : Unused code path elimination + * Block '/Constant' : Unused code path elimination + * Block '/Compare' : Unused code path elimination + * Block '/Constant' : Unused code path elimination + * Block '/Compare' : Unused code path elimination + * Block '/Constant' : Unused code path elimination + * Block '/Multiport Switch' : Unused code path elimination + * Block '/Multiport Switch3' : Unused code path elimination + * Block '/Multiport Switch4' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Compare' : Unused code path elimination + * Block '/Constant' : Unused code path elimination + * Block '/Compare' : Unused code path elimination + * Block '/Constant' : Unused code path elimination + * Block '/Compare' : Unused code path elimination + * Block '/Constant' : Unused code path elimination + * Block '/Multiport Switch' : Unused code path elimination + * Block '/Multiport Switch3' : Unused code path elimination + * Block '/Multiport Switch4' : Unused code path elimination + * Block '/Data Type Duplicate' : Unused code path elimination + * Block '/Data Type Propagation' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Saturation2' : Unused code path elimination + * Block '/Saturation3' : Unused code path elimination + * Block '/Data Type Conversion' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Gain3' : Unused code path elimination + * Block '/Gain4' : Unused code path elimination + * Block '/Constant3' : Unused code path elimination + * Block '/Equal3' : Unused code path elimination + * Block '/Display' : Unused code path elimination + * Block '/Display1' : Unused code path elimination + * Block '/Display2' : Unused code path elimination + * Block '/Display3' : Unused code path elimination + * Block '/Display4' : Unused code path elimination + * Block '/Display5' : Unused code path elimination + * Block '/Display6' : Unused code path elimination + * Block '/Display7' : Unused code path elimination + * Block '/Data Type Conversion' : Eliminate redundant data type conversion + * Block '/Data Type Conversion' : Eliminate redundant data type conversion + * Block '/Data Type Conversion' : Eliminate redundant data type conversion + * Block '/Data Type Conversion' : Eliminate redundant data type conversion + * Block '/Data Type Conversion' : Eliminate redundant data type conversion + * Block '/Abs' : Eliminated since data is unsigned + * Block '/Abs' : Eliminated since data is unsigned + * Block '/Abs' : Eliminated since data is unsigned + * Block '/Abs' : Eliminated since data is unsigned + * Block '/Abs' : Eliminated since data is unsigned + * Block '/Abs' : Eliminated since data is unsigned + * Block '/Abs' : Eliminated since data is unsigned + * Block '/Abs' : Eliminated since data is unsigned + * Block '/Abs' : Eliminated since data is unsigned + * Block '/Abs' : Eliminated since data is unsigned + * Block '/Data Type Conversion' : Eliminate redundant data type conversion + * Block '/Data Type Conversion' : Eliminate redundant data type conversion + * Block '/Data Type Conversion' : Eliminate redundant data type conversion + * Block '/Data Type Conversion' : Eliminate redundant data type conversion + * Block '/Abs' : Eliminated since data is unsigned + * Block '/Abs' : Eliminated since data is unsigned + * Block '/Abs' : Eliminated since data is unsigned + * Block '/Abs' : Eliminated since data is unsigned + * Block '/Abs' : Eliminated since data is unsigned + * Block '/Abs' : Eliminated since data is unsigned + * Block '/Abs' : Eliminated since data is unsigned + * Block '/Abs' : Eliminated since data is unsigned + * Block '/Abs' : Eliminated since data is unsigned + * Block '/Abs' : Eliminated since data is unsigned + * Block '/Abs' : Eliminated since data is unsigned + * Block '/Abs' : Eliminated since data is unsigned + * Block '/Data Type Conversion' : Eliminate redundant data type conversion + * Block '/Data Type Conversion' : Eliminate redundant data type conversion + * Block '/Data Type Conversion' : Eliminate redundant data type conversion + * Block '/Data Type Conversion' : Eliminate redundant data type conversion + * Block '/Data Type Conversion1' : Eliminate redundant data type conversion + * Block '/Data Type Conversion1' : Eliminate redundant data type conversion + * Block '/Data Type Conversion2' : Eliminate redundant data type conversion + * Block '/Data Type Conversion3' : Eliminate redundant data type conversion + * Block '/Data Type Conversion' : Eliminate redundant data type conversion + * Block '/Data Type Conversion1' : Eliminate redundant data type conversion + * Block '/Data Type Conversion2' : Eliminate redundant data type conversion + * Block '/Data Type Conversion' : Eliminate redundant data type conversion + * Block '/Data Type Conversion1' : Eliminate redundant data type conversion + * Block '/Data Type Conversion2' : Eliminate redundant data type conversion + * Block '/Data Type Conversion4' : Eliminate redundant data type conversion + * Block '/Data Type Conversion5' : Eliminate redundant data type conversion + * Block '/Data Type Conversion1' : Eliminate redundant data type conversion + * Block '/Data Type Conversion2' : Eliminate redundant data type conversion + * Block '/Data Type Conversion3' : Eliminate redundant data type conversion + * Block '/Data Type Conversion1' : Eliminate redundant data type conversion + * Block '/Data Type Conversion2' : Eliminate redundant data type conversion + * Block '/Data Type Conversion3' : Eliminate redundant data type conversion + * Block '/Data Type Conversion1' : Eliminate redundant data type conversion + * Block '/Data Type Conversion' : Eliminate redundant data type conversion + * Block '/Data Type Conversion1' : Eliminate redundant data type conversion + * Block '/Data Type Conversion' : Eliminate redundant data type conversion + * Block '/Data Type Conversion1' : Eliminate redundant data type conversion + * Block '/Data Type Conversion' : Eliminate redundant data type conversion + * Block '/Data Type Conversion' : Eliminate redundant data type conversion + * Block '/Data Type Conversion' : Eliminate redundant data type conversion + * Block '/Data Type Conversion' : Eliminate redundant data type conversion + * Block '/Data Type Conversion' : Eliminate redundant data type conversion + * Block '/Data Type Conversion' : Eliminate redundant data type conversion + * Block '/Data Type Conversion' : Eliminate redundant data type conversion + * Block '/Data Type Conversion' : Eliminate redundant data type conversion + * Block '/Data Type Conversion' : Eliminate redundant data type conversion + * Block '/Data Type Conversion26' : Eliminate redundant data type conversion + * Block '/Data Type Conversion27' : Eliminate redundant data type conversion + * Block '/Data Type Conversion28' : Eliminate redundant data type conversion + * Block '/Data Type Conversion30' : Eliminate redundant data type conversion + * Block '/Data Type Conversion31' : Eliminate redundant data type conversion + * Block '/Data Type Conversion34' : Eliminate redundant data type conversion + * Block '/Data Type Conversion1' : Eliminate redundant data type conversion + * Block '/Data Type Conversion2' : Eliminate redundant data type conversion + * Block '/Data Type Conversion' : Eliminate redundant data type conversion + * Block '/Data Type Conversion2' : Eliminate redundant data type conversion + * Block '/Data Type Conversion3' : Eliminate redundant data type conversion + * Block '/Data Type Conversion5' : Eliminate redundant data type conversion + * Block '/Data Type Conversion1' : Eliminate redundant data type conversion + * Block '/Data Type Conversion2' : Eliminate redundant data type conversion + * Block '/Data Type Conversion1' : Eliminate redundant data type conversion + * Block '/Data Type Conversion2' : Eliminate redundant data type conversion + * Block '/Data Type Conversion' : Eliminate redundant data type conversion + * Block '/Data Type Conversion5' : Eliminate redundant data type conversion + * Block '/Data Type Conversion1' : Eliminate redundant data type conversion + * Block '/Data Type Conversion2' : Eliminate redundant data type conversion + * Block '/Data Type Conversion' : Eliminate redundant data type conversion + * Block '/Data Type Conversion2' : Eliminate redundant data type conversion + * Block '/Data Type Conversion3' : Eliminate redundant data type conversion + * Block '/Data Type Conversion5' : Eliminate redundant data type conversion + * Block '/Data Type Conversion1' : Eliminate redundant data type conversion + * Block '/Data Type Conversion2' : Eliminate redundant data type conversion + * Block '/Data Type Conversion1' : Eliminate redundant data type conversion + * Block '/Data Type Conversion2' : Eliminate redundant data type conversion + * Block '/Data Type Conversion' : Eliminate redundant data type conversion + * Block '/Data Type Conversion5' : Eliminate redundant data type conversion + * Block '/Data Type Conversion' : Eliminate redundant data type conversion + * Block '/Data Type Conversion1' : Eliminate redundant data type conversion + * Block '/Data Type Conversion2' : Eliminate redundant data type conversion + * Block '/Data Type Conversion' : Eliminate redundant data type conversion + * Block '/Data Type Conversion1' : Eliminate redundant data type conversion + * Block '/Data Type Conversion2' : Eliminate redundant data type conversion + * Block '/Data Type Conversion1' : Eliminate redundant data type conversion + * Block '/Data Type Conversion2' : Eliminate redundant data type conversion + * Block '/Data Type Conversion1' : Eliminate redundant data type conversion + * Block '/Data Type Conversion2' : Eliminate redundant data type conversion + */ + +/*- + * The generated code includes comments that allow you to trace directly + * back to the appropriate location in the model. The basic format + * is /block_name, where system is the system number (uniquely + * assigned by Simulink) and block_name is the name of the block. + * + * Use the MATLAB hilite_system command to trace the generated code back + * to the model. For example, + * + * hilite_system('') - opens system 3 + * hilite_system('/Kp') - opens and selects block Kp which resides in S3 + * + * Here is the system hierarchy for this model + * + * '' : 'HVAC_model' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode' + * '' : 'HVAC_model/13,1,3,15 Valve control' + * '' : 'HVAC_model/13,1,3,16 Partial REC auto rec?' + * '' : 'HVAC_model/13,1,3,6 Individual foots' + * '' : 'HVAC_model/13,1,3,7 Start control' + * '' : 'HVAC_model/13.1.3.3 Dtg model' + * '' : 'HVAC_model/A//C Control' + * '' : 'HVAC_model/ACP' + * '' : 'HVAC_model/ACmax' + * '' : 'HVAC_model/AUTO' + * '' : 'HVAC_model/Blower speed (AF) auto or manual' + * '' : 'HVAC_model/CAN INPUT' + * '' : 'HVAC_model/CAN OUTPUT' + * '' : 'HVAC_model/Chart' + * '' : 'HVAC_model/Compare To Constant' + * '' : 'HVAC_model/Compare To Constant1' + * '' : 'HVAC_model/Compare To Constant2' + * '' : 'HVAC_model/Compare To Constant3' + * '' : 'HVAC_model/DRS' + * '' : 'HVAC_model/IO' + * '' : 'HVAC_model/IndexMode' + * '' : 'HVAC_model/LIN' + * '' : 'HVAC_model/MATLAB Function1' + * '' : 'HVAC_model/PID Compressor' + * '' : 'HVAC_model/PID DUCT' + * '' : 'HVAC_model/PWN' + * '' : 'HVAC_model/Power' + * '' : 'HVAC_model/Synchronization (SYNC)' + * '' : 'HVAC_model/Synchronization stateflow chart' + * '' : 'HVAC_model/Valves auto or manual ()' + * '' : 'HVAC_model/dbg CAN' + * '' : 'HVAC_model/debug stateflow chart' + * '' : 'HVAC_model/external fan' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13,1,3,1 Ambien level' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13,1,3,1 Ambien level/Convert_g_assAMB_LV_UP' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13,1,3,1 Ambien level/Log Ambient Lv' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13,1,3,1 Ambien level/Switch Case Action Subsystem' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13,1,3,1 Ambien level/Switch Case Action Subsystem1' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13,1,3,1 Ambien level/Switch Case Action Subsystem2' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13,1,3,1 Ambien level/Switch Case Action Subsystem3' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13,1,3,1 Ambien level/Switch Case Action Subsystem4' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13,1,3,1 Ambien level/Switch Case Action Subsystem5' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13,1,3,1 Ambien level/Switch Case Action Subsystem1/Convert_g_assAMB_LV_DN_1' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13,1,3,1 Ambien level/Switch Case Action Subsystem1/Convert_g_assAMB_LV_UP_2' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13,1,3,1 Ambien level/Switch Case Action Subsystem2/Convert_g_assAMB_LV_DN_2' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13,1,3,1 Ambien level/Switch Case Action Subsystem2/Convert_g_assAMB_LV_UP_3' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13,1,3,1 Ambien level/Switch Case Action Subsystem3/Convert_g_assAMB_LV_DN_3' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13,1,3,1 Ambien level/Switch Case Action Subsystem3/Convert_g_assAMB_LV_UP_4' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13,1,3,1 Ambien level/Switch Case Action Subsystem4/Convert_g_assAMB_LV_DN_4' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13,1,3,1 Ambien level/Switch Case Action Subsystem4/Convert_g_assAMB_LV_UP_5' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13,1,3,1 Ambien level/Switch Case Action Subsystem5/Convert_g_assAMB_LV_DN_5' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/Modes for levels' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_left' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/ left' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/ right' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_left/Afoot' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_left/Afoot_Summer' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_left/Bilevel' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_left/Bilevel2' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_left/VENT+' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_left/Afoot/FLF (Front Left Foot)' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_left/Afoot/FRF (Front Right Foot)' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_left/Afoot/Front Left' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_left/Afoot/Front Right' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_left/Afoot/FLF (Front Left Foot)/Saturation Dynamic3' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_left/Afoot/FLF (Front Left Foot)/X_LEFT' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_left/Afoot/FLF (Front Left Foot)/g_aucFLOW_AF_FOOT_PLUS' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_left/Afoot/FLF (Front Left Foot)/g_aucFLOW_AF_FOOT_VALVE_MAX' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_left/Afoot/FLF (Front Left Foot)/X_LEFT/g_assFLOW_BI2_TEMP_TGT_LEFT' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_left/Afoot/FLF (Front Left Foot)/X_LEFT/get_tg_for_LVL' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_left/Afoot/FRF (Front Right Foot)/Saturation Dynamic4' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_left/Afoot/FRF (Front Right Foot)/X_RIGHT' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_left/Afoot/FRF (Front Right Foot)/g_aucFLOW_AF_FOOT_PLUS' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_left/Afoot/FRF (Front Right Foot)/g_aucFLOW_AF_FOOT_VALVE_MAX' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_left/Afoot/FRF (Front Right Foot)/X_RIGHT/g_aucFLOW_AF_BLR_AF_TGT' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_left/Afoot/FRF (Front Right Foot)/X_RIGHT/get_vtg_for_LVL' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_left/Afoot/Front Left/Saturation Dynamic' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_left/Afoot/Front Left/g_assFLOW_AF_AMB_TGT' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_left/Afoot/Front Left/g_aucFLOW_AF_VENT_PLUS' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_left/Afoot/Front Left/g_aucFLOW_AF_VENT_VALVE_MAX' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_left/Afoot/Front Right/Saturation Dynamic' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_left/Afoot/Front Right/g_assFLOW_AF_AMB_TGT' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_left/Afoot/Front Right/g_aucFLOW_AF_VENT_PLUS' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_left/Afoot/Front Right/g_aucFLOW_AF_VENT_VALVE_MAX' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_left/Afoot_Summer/FLF (Front Left Foot)' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 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(Front Right Foot)/g_aucFLOW_AF_FOOT_PLUS' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Afoot/FRF (Front Right Foot)/g_aucFLOW_AF_FOOT_VALVE_MAX' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Afoot/FRF (Front Right Foot)/X_RIGHT/g_aucFLOW_AF_BLR_AF_TGT' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Afoot/FRF (Front Right Foot)/X_RIGHT/get_vtg_for_LVL' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Afoot/Front Left/Saturation Dynamic' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Afoot/Front Left/g_assFLOW_AF_AMB_TGT' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Afoot/Front Left/g_aucFLOW_AF_VENT_PLUS' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Afoot/Front Left/g_aucFLOW_AF_VENT_VALVE_MAX' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Afoot/Front Right/Saturation Dynamic' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Afoot/Front Right/g_assFLOW_AF_AMB_TGT' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Afoot/Front Right/g_aucFLOW_AF_VENT_PLUS' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Afoot/Front Right/g_aucFLOW_AF_VENT_VALVE_MAX' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Afoot_Summer/FLF (Front Left Foot)' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Afoot_Summer/FRF (Front Right Foot)' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Afoot_Summer/Front Left' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Afoot_Summer/Front Right' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Afoot_Summer/FLF (Front Left Foot)/Saturation Dynamic3' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Afoot_Summer/FLF (Front Left Foot)/X_LEFT' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Afoot_Summer/FLF (Front Left Foot)/g_aucFLOW_AFSM_FOOT_PLUS' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Afoot_Summer/FLF (Front Left Foot)/g_aucFLOW_AFSM_FOOT_VALVE_MAX' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Afoot_Summer/FLF (Front Left Foot)/X_LEFT/g_assFLOW_AFSM_TEMP_TGT_LEFT' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Afoot_Summer/FLF (Front Left Foot)/X_LEFT/get_tg_for_LVL' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Afoot_Summer/FRF (Front Right Foot)/Saturation Dynamic4' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Afoot_Summer/FRF (Front Right Foot)/X_RIGHT' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Afoot_Summer/FRF (Front Right Foot)/g_aucFLOW_AFSM_FOOT_PLUS' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Afoot_Summer/FRF (Front Right Foot)/g_aucFLOW_AF_FOOT_VALVE_MAX' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Afoot_Summer/FRF (Front Right Foot)/X_RIGHT/g_assFLOW_AFSM_TEMP_TGT' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Afoot_Summer/FRF (Front Right Foot)/X_RIGHT/get_tg_FLL_for_LVL' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Afoot_Summer/Front Left/Saturation Dynamic' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Afoot_Summer/Front Left/g_assFLOW_AFSM_AMB_TGT' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Afoot_Summer/Front Left/g_aucFLOW_AFSM_VENT_PLUS' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Afoot_Summer/Front Left/g_aucFLOW_AF_VENT_VALVE_MAX' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Afoot_Summer/Front Right/Saturation Dynamic' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Afoot_Summer/Front Right/g_assFLOW_AF_AMB_TGT' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Afoot_Summer/Front Right/g_aucFLOW_AF_VENT_PLUS' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Afoot_Summer/Front Right/g_aucFLOW_AF_VENT_VALVE_MAX' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel/FLF (Front Left Foot)' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel/FRF (Front Right Foot)' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel/Front Left' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel/Front Right' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel/FLF (Front Left Foot)/Saturation Dynamic3' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel/FLF (Front Left Foot)/X_LEFT' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel/FLF (Front Left Foot)/g_aucFLOW_BI_FOOT_PLUS_LEFT' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel/FLF (Front Left Foot)/g_aucFLOW_BI_FOOT_VALVE_MAX1' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel/FLF (Front Left Foot)/g_aucFLOW_BI_FOOT_VALVE_MIN1' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel/FLF (Front Left Foot)/X_LEFT/g_assFLOW_BI2_TEMP_TGT_LEFT' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel/FLF (Front Left Foot)/X_LEFT/get_tg_FLL_for_LVL' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel/FRF (Front Right Foot)/Saturation Dynamic4' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel/FRF (Front Right Foot)/X_RIGHT' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel/FRF (Front Right Foot)/g_aucFLOW_BI_FOOT_PLUS_RIGHT' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel/FRF (Front Right Foot)/g_aucFLOW_BI_FOOT_VALVE_MAX2' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel/FRF (Front Right Foot)/g_aucFLOW_BI_FOOT_VALVE_MIN2' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel/FRF (Front Right Foot)/X_RIGHT/g_assFLOW_BI_TEMP_TGT_RIGHT' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel/FRF (Front Right Foot)/X_RIGHT/get_tg_FLL_for_LVL' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel/Front Left/Saturation Dynamic' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel/Front Left/g_assFLOW_BI_AMB_TGT' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel/Front Left/g_aucFLOW_BI_VENT_PLUS' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel/Front Left/g_aucFLOW_BI_VENT_VALVE_MAX' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel/Front Left/g_aucFLOW_BI_VENT_VALVE_MIN' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel/Front Right/Saturation Dynamic' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel/Front Right/g_assFLOW_BI_AMB_TGT' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel/Front Right/g_aucFLOW_BI_VENT_PLUS' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel/Front Right/g_aucFLOW_BI_VENT_VALVE_MAX' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel/Front Right/g_aucFLOW_BI_VENT_VALVE_MIN' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel2/FLF (Front Left Foot)' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel2/FRF (Front Right Foot)' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel2/Front Left' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel2/Front Right' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel2/FLF (Front Left Foot)/Saturation Dynamic3' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel2/FLF (Front Left Foot)/X_LEFT' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel2/FLF (Front Left Foot)/g_aucFLOW_BI_FOOT_PLUS_LEFT' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel2/FLF (Front Left Foot)/g_aucFLOW_BI_FOOT_VALVE_MAX1' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel2/FLF (Front Left Foot)/g_aucFLOW_BI_FOOT_VALVE_MIN1' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel2/FLF (Front Left Foot)/X_LEFT/g_assFLOW_BI2_TEMP_TGT_LEFT' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel2/FLF (Front Left Foot)/X_LEFT/get_tg_FLL_for_LVL' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel2/FRF (Front Right Foot)/Saturation Dynamic4' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel2/FRF (Front Right Foot)/X_RIGHT' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel2/FRF (Front Right Foot)/g_aucFLOW_BI_FOOT_PLUS_RIGHT' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel2/FRF (Front Right Foot)/g_aucFLOW_BI_FOOT_VALVE_MAX2' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel2/FRF (Front Right Foot)/g_aucFLOW_BI_FOOT_VALVE_MIN2' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel2/FRF (Front Right Foot)/X_RIGHT/g_assFLOW_BI2_TEMP_TGT_RIGHT' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel2/FRF (Front Right Foot)/X_RIGHT/get_tg_FLL_for_LVL' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel2/Front Left/Saturation Dynamic' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel2/Front Left/g_assFLOW_BI_AMB_TGT' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel2/Front Left/g_aucFLOW_BI_VENT_PLUS' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel2/Front Left/g_aucFLOW_BI_VENT_VALVE_MAX' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel2/Front Left/g_aucFLOW_BI_VENT_VALVE_MIN' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel2/Front Right/Saturation Dynamic' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel2/Front Right/g_assFLOW_BI_AMB_TGT' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel2/Front Right/g_aucFLOW_BI_VENT_PLUS' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel2/Front Right/g_aucFLOW_BI_VENT_VALVE_MAX' + * '' : 'HVAC_model/13,1,3,1 Ambien level 13.1.3.2 Mode/13.1.3.2 Mode/set_valves_right/Bilevel2/Front Right/g_aucFLOW_BI_VENT_VALVE_MIN' + * '' : 'HVAC_model/13,1,3,16 Partial REC auto rec?/13,1,3,14 air quality' + * '' : 'HVAC_model/13,1,3,16 Partial REC auto rec?/Partial REC' + * '' : 'HVAC_model/13,1,3,16 Partial REC auto rec?/Spd_OSA_Trigger' + * '' : 'HVAC_model/13,1,3,6 Individual foots/FL' + * '' : 'HVAC_model/13,1,3,6 Individual foots/FR' + * '' : 'HVAC_model/13,1,3,6 Individual foots/FL/Valve and blower' + * '' : 'HVAC_model/13,1,3,6 Individual foots/FL/Valve and blower/If Action Subsystem' + * '' : 'HVAC_model/13,1,3,6 Individual foots/FL/Valve and blower/If Action Subsystem1' + * '' : 'HVAC_model/13,1,3,6 Individual foots/FL/Valve and blower/If Action Subsystem2' + * '' : 'HVAC_model/13,1,3,6 Individual foots/FL/Valve and blower/If Action Subsystem/If Action Subsystem' + * '' : 'HVAC_model/13,1,3,6 Individual foots/FL/Valve and blower/If Action Subsystem/If Action Subsystem1' + * '' : 'HVAC_model/13,1,3,6 Individual foots/FL/Valve and blower/If Action Subsystem/If Action Subsystem2' + * '' : 'HVAC_model/13,1,3,6 Individual foots/FL/Valve and blower/If Action Subsystem1/If Action Subsystem' + * '' : 'HVAC_model/13,1,3,6 Individual foots/FL/Valve and blower/If Action Subsystem1/If Action Subsystem1' + * '' : 'HVAC_model/13,1,3,6 Individual foots/FL/Valve and blower/If Action Subsystem1/If Action Subsystem2' + * '' : 'HVAC_model/13,1,3,6 Individual foots/FL/Valve and blower/If Action Subsystem2/If Action Subsystem' + * '' : 'HVAC_model/13,1,3,6 Individual foots/FL/Valve and blower/If Action Subsystem2/If Action Subsystem1' + * '' : 'HVAC_model/13,1,3,6 Individual foots/FL/Valve and blower/If Action Subsystem2/If Action Subsystem2' + * '' : 'HVAC_model/13,1,3,6 Individual foots/FR/Valve and blower' + * '' : 'HVAC_model/13,1,3,6 Individual foots/FR/Valve and blower/If Action Subsystem' + * '' : 'HVAC_model/13,1,3,6 Individual foots/FR/Valve and blower/If Action Subsystem1' + * '' : 'HVAC_model/13,1,3,6 Individual foots/FR/Valve and blower/If Action Subsystem2' + * '' : 'HVAC_model/13,1,3,6 Individual foots/FR/Valve and blower/If Action Subsystem/If Action Subsystem' + * '' : 'HVAC_model/13,1,3,6 Individual foots/FR/Valve and blower/If Action Subsystem/If Action Subsystem1' + * '' : 'HVAC_model/13,1,3,6 Individual foots/FR/Valve and blower/If Action Subsystem/If Action Subsystem2' + * '' : 'HVAC_model/13,1,3,6 Individual foots/FR/Valve and blower/If Action Subsystem1/If Action Subsystem' + * '' : 'HVAC_model/13,1,3,6 Individual foots/FR/Valve and blower/If Action Subsystem1/If Action Subsystem1' + * '' : 'HVAC_model/13,1,3,6 Individual foots/FR/Valve and blower/If Action Subsystem1/If Action Subsystem2' + * '' : 'HVAC_model/13,1,3,6 Individual foots/FR/Valve and blower/If Action Subsystem2/If Action Subsystem' + * '' : 'HVAC_model/13,1,3,6 Individual foots/FR/Valve and blower/If Action Subsystem2/If Action Subsystem1' + * '' : 'HVAC_model/13,1,3,6 Individual foots/FR/Valve and blower/If Action Subsystem2/If Action Subsystem2' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear' + * '' : 'HVAC_model/13,1,3,7 Start control/count from 0 to 3' + * '' : 'HVAC_model/13,1,3,7 Start control/count from 0 to 3 rear' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step -1 F (Entry Condition)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 0 F' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 3 F' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step -1 F (Entry Condition)/Level 0' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step -1 F (Entry Condition)/Level 1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step -1 F (Entry Condition)/Level 2' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step -1 F (Entry Condition)/Level 3' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step -1 F (Entry Condition)/Level 4' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step -1 F (Entry Condition)/Level 5' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step -1 F (Entry Condition)/Level 0/g_assSTART_ENTER_INCAR' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step -1 F (Entry Condition)/Level 0/g_ausSTART_ENTER_SETTEMP' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step -1 F (Entry Condition)/Level 1/g_assSTART_ENTER_INCAR' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step -1 F (Entry Condition)/Level 1/g_ausSTART_ENTER_SETTEMP' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step -1 F (Entry Condition)/Level 3/g_assSTART_ENTER_COOLANT ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step -1 F (Entry Condition)/Level 4/g_assSTART_ENTER_COOLANT ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step -1 F (Entry Condition)/Level 5/g_assSTART_ENTER_COOLANT ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 0 F/Level 0' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 0 F/Level 1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 0 F/Level 2' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 0 F/Level 3' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 0 F/Level 4' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 0 F/Level 5' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 0 F/Level 3/g_assSTART_COOLANT_STEP0_TO_1 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 0 F/Level 3/incar filter down' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 0 F/Level 3/incar filter up' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 0 F/Level 4/g_assSTART_COOLANT_STEP0_TO_1 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 0 F/Level 4/incar filter down' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 0 F/Level 4/incar filter up' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 0 F/Level 5/g_assSTART_COOLANT_STEP0_TO_1 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 0 F/Level 5/incar filter down' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 0 F/Level 5/incar filter up' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 0' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 2' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 3' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 4' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 5' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 0/3 way valve status' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 0/Dtg_FrontLower_X' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 0/Dtg_FrontUpper_X' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 0/Incar temp goto from step 1 to step 2 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 0/MATLAB Function1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 0/Time goto from step 1 to step 2 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 0/blower FR' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 0/incar filter down' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 0/incar filter up' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 0/mode FR step 1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 0/window heating' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 1/3 way valve status' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 1/Dtg_FrontLower_X' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 1/Dtg_FrontUpper_X' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 1/Incar temp goto from step 1 to step 2 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 1/MATLAB Function1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 1/Time goto from step 1 to step 2 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 1/blower FR' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 1/incar filter down' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 1/incar filter up' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 1/mode FR step 1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 1/window heating' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 3/3 way valve status' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 3/Dtg_FrontLower_X' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 3/Dtg_FrontUpper_X' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 3/Incar temp goto from step 1 to step 2 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 3/MATLAB Function1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 3/Time goto from step 1 to step 2 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 3/blower ECT' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 3/g_assSTART_COOLANT_TO_STEP2 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 3/incar filter down' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 3/incar filter up' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 3/mode FR step 1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 3/window heating' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 3/blower ECT/ECT min max' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 3/blower ECT/blower min max' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 4/3 way valve status' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 4/Dtg_FrontLower_X' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 4/Dtg_FrontUpper_X' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 4/Incar temp goto from step 1 to step 2 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 4/MATLAB Function1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 4/Time goto from step 1 to step 2 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 4/blower ECT' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 4/incar filter down' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 4/incar filter up' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 4/mode FR step 1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 4/window heating' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 4/blower ECT/ECT min max' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 4/blower ECT/blower min max' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 5/3 way valve status' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 5/Dtg_FrontLower_X' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 5/Dtg_FrontUpper_X' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 5/Incar temp goto from step 1 to step 2 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 5/MATLAB Function1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 5/Time goto from step 1 to step 2 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 5/blower ECT' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 5/incar filter down' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 5/incar filter up' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 5/mode FR step 1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 5/window heating' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 5/blower ECT/ECT min max' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 1 F/Level 5/blower ECT/blower min max' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 0' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 2' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 3' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 4' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 5' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 0/3 way valve status' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 0/DTG F Lower, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 0/DTG F Upper, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 0/MATLAB Function1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 0/Time goto from step 2 to step 3 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 0/blower, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 0/incar filter down' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 0/incar filter up' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 0/mode, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 0/window heating' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 0/DTG F Lower, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 0/DTG F Lower, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 0/DTG F Lower, AUTO/step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 0/DTG F Lower, AUTO/time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 0/DTG F Lower, AUTO/ (+//-)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 0/DTG F Upper, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 0/DTG F Upper, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 0/DTG F Upper, AUTO/step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 0/DTG F Upper, AUTO/time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 0/DTG F Upper, AUTO/ (+//-)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 0/blower, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 0/blower, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 0/blower, AUTO/blower step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 0/blower, AUTO/blower time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 0/blower, AUTO/ (+//-)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 0/mode, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 0/mode, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 0/mode, AUTO/step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 0/mode, AUTO/time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 0/mode, AUTO/ (+//-)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 1/3 way valve status' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 1/DTG F Lower, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 1/DTG F Upper, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 1/MATLAB Function1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 1/Time goto from step 2 to step 3 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 1/blower, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 1/incar filter down' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 1/incar filter up' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 1/mode, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 1/window heating' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 1/DTG F Lower, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 1/DTG F Lower, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 1/DTG F Lower, AUTO/step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 1/DTG F Lower, AUTO/time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 1/DTG F Lower, AUTO/ (+//-)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 1/DTG F Upper, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 1/DTG F Upper, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 1/DTG F Upper, AUTO/step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 1/DTG F Upper, AUTO/time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 1/DTG F Upper, AUTO/ (+//-)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 1/blower, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 1/blower, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 1/blower, AUTO/blower step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 1/blower, AUTO/blower time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 1/blower, AUTO/ (+//-)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 1/mode, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 1/mode, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 1/mode, AUTO/step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 1/mode, AUTO/time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 1/mode, AUTO/ (+//-)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 3/3 way valve status' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 3/DTG F Lower, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 3/DTG F Upper, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 3/MATLAB Function1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 3/Time goto from step 2 to step 3 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 3/autodemist (autodefog)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 3/blower, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 3/incar filter down' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 3/incar filter up' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 3/mode, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 3/window heating' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 3/DTG F Lower, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 3/DTG F Lower, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 3/DTG F Lower, AUTO/step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 3/DTG F Lower, AUTO/time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 3/DTG F Lower, AUTO/ (+//-)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 3/DTG F Upper, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 3/DTG F Upper, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 3/DTG F Upper, AUTO/step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 3/DTG F Upper, AUTO/time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 3/DTG F Upper, AUTO/ (+//-)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 3/blower, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 3/blower, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 3/blower, AUTO/blower step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 3/blower, AUTO/blower time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 3/blower, AUTO/ (+//-)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 3/mode, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 3/mode, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 3/mode, AUTO/step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 3/mode, AUTO/time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 3/mode, AUTO/ (+//-)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 4/3 way valve status' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 4/DTG F Lower, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 4/DTG F Upper, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 4/MATLAB Function1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 4/Time goto from step 2 to step 3 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 4/autodemist (autodefog)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 4/blower, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 4/incar filter down' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 4/incar filter up' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 4/mode, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 4/window heating' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 4/DTG F Lower, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 4/DTG F Lower, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 4/DTG F Lower, AUTO/step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 4/DTG F Lower, AUTO/time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 4/DTG F Lower, AUTO/ (+//-)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 4/DTG F Upper, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 4/DTG F Upper, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 4/DTG F Upper, AUTO/step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 4/DTG F Upper, AUTO/time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 4/DTG F Upper, AUTO/ (+//-)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 4/blower, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 4/blower, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 4/blower, AUTO/blower step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 4/blower, AUTO/blower time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 4/blower, AUTO/ (+//-)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 4/mode, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 4/mode, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 4/mode, AUTO/step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 4/mode, AUTO/time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 4/mode, AUTO/ (+//-)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 5/3 way valve status' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 5/DTG F Lower, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 5/DTG F Upper, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 5/MATLAB Function1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 5/Time goto from step 2 to step 3 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 5/autodemist (autodefog)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 5/blower, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 5/incar filter down' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 5/incar filter up' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 5/mode, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 5/window heating' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 5/DTG F Lower, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 5/DTG F Lower, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 5/DTG F Lower, AUTO/step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 5/DTG F Lower, AUTO/time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 5/DTG F Lower, AUTO/ (+//-)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 5/DTG F Upper, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 5/DTG F Upper, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 5/DTG F Upper, AUTO/step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 5/DTG F Upper, AUTO/time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 5/DTG F Upper, AUTO/ (+//-)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 5/blower, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 5/blower, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 5/blower, AUTO/blower step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 5/blower, AUTO/blower time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 5/blower, AUTO/ (+//-)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 5/mode, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 5/mode, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 5/mode, AUTO/step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 5/mode, AUTO/time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Front/Step 2 F/Level 5/mode, AUTO/ (+//-)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step -1 R (Entry Condition)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 0 R' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 3 R' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step -1 R (Entry Condition)/Level 0' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step -1 R (Entry Condition)/Level 1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step -1 R (Entry Condition)/Level 2' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step -1 R (Entry Condition)/Level 3' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step -1 R (Entry Condition)/Level 4' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step -1 R (Entry Condition)/Level 5' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step -1 R (Entry Condition)/Level 0/g_assSTART_ENTER_INCAR' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step -1 R (Entry Condition)/Level 0/g_ausSTART_ENTER_SETTEMP' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step -1 R (Entry Condition)/Level 1/g_assSTART_ENTER_INCAR' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step -1 R (Entry Condition)/Level 1/g_ausSTART_ENTER_SETTEMP' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step -1 R (Entry Condition)/Level 2/g_assSTART_ENTER_INCAR' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step -1 R (Entry Condition)/Level 2/g_ausSTART_ENTER_SETTEMP' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step -1 R (Entry Condition)/Level 3/g_assSTART_ENTER_COOLANT ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step -1 R (Entry Condition)/Level 3/g_assSTART_ENTER_INCAR' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step -1 R (Entry Condition)/Level 3/g_ausSTART_ENTER_SETTEMP' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step -1 R (Entry Condition)/Level 4/g_assSTART_ENTER_COOLANT ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step -1 R (Entry Condition)/Level 4/g_assSTART_ENTER_INCAR' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step -1 R (Entry Condition)/Level 5/g_assSTART_ENTER_COOLANT ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step -1 R (Entry Condition)/Level 5/g_assSTART_ENTER_INCAR' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 0 R/Level 0' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 0 R/Level 1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 0 R/Level 2' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 0 R/Level 3' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 0 R/Level 4' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 0 R/Level 5' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 0 R/Level 2/g_assSTART_COOLANT_STEP0_TO_1 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 0 R/Level 2/incar filter down' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 0 R/Level 2/incar filter up' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 0 R/Level 3/g_assSTART_COOLANT_STEP0_TO_1 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 0 R/Level 3/incar filter down' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 0 R/Level 3/incar filter up' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 0 R/Level 4/g_assSTART_COOLANT_STEP0_TO_1 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 0 R/Level 4/incar filter down' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 0 R/Level 4/incar filter up' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 0 R/Level 5/g_assSTART_COOLANT_STEP0_TO_1 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 0 R/Level 5/incar filter down' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 0 R/Level 5/incar filter up' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 0' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 2' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 3' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 4' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 5' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 0/2 way valve' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 0/Dtg_rear' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 0/Incar temp goto from step 1 to step 2 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 0/MATLAB Function1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 0/Time goto from step 1 to step 2 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 0/blower rear' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 0/incar filter down' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 0/incar filter up' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 0/mode rear step 1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 1/2 way valve' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 1/Dtg_rear' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 1/Incar temp goto from step 1 to step 2 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 1/MATLAB Function1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 1/Time goto from step 1 to step 2 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 1/blower rear' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 1/incar filter down' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 1/incar filter up' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 1/mode rear step 1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 2/2 way valve' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 2/Dtg_rear' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 2/Incar temp goto from step 1 to step 2 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 2/MATLAB Function1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 2/Time goto from step 1 to step 2 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 2/blower ECT' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 2/g_assSTART_COOLANT_TO_STEP2 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 2/incar filter down' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 2/incar filter up' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 2/mode rear step 1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 2/blower ECT/ECT min max' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 2/blower ECT/blower start finish' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 3/2 way valve' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 3/Dtg_rear' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 3/Incar temp goto from step 1 to step 2 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 3/MATLAB Function1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 3/Time goto from step 1 to step 2 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 3/blower ECT' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 3/g_assSTART_COOLANT_TO_STEP2 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 3/incar filter down' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 3/incar filter up' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 3/mode rear step 1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 3/blower ECT/ECT min max' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 3/blower ECT/blower start finish' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 4/2 way valve' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 4/Dtg_rear' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 4/Incar temp goto from step 1 to step 2 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 4/MATLAB Function1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 4/Time goto from step 1 to step 2 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 4/blower ECT' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 4/incar filter down' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 4/incar filter up' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 4/mode rear step 1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 4/blower ECT/ECT min max' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 4/blower ECT/blower start finish' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 5/2 way valve' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 5/Dtg_rear' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 5/Incar temp goto from step 1 to step 2 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 5/MATLAB Function1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 5/Time goto from step 1 to step 2 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 5/blower ECT' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 5/incar filter down' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 5/incar filter up' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 5/mode rear step 1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 5/blower ECT/ECT min max' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 1 R/Level 5/blower ECT/blower start finish' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 0' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 2' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 3' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 4' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 5' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 0/2 way valve' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 0/DTG Rear, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 0/MATLAB Function1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 0/Time goto from step 1 to step 2 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 0/blower, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 0/incar filter down' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 0/incar filter up' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 0/mode, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 0/DTG Rear, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 0/DTG Rear, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 0/DTG Rear, AUTO/step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 0/DTG Rear, AUTO/time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 0/DTG Rear, AUTO/ (+//-)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 0/blower, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 0/blower, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 0/blower, AUTO/blower step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 0/blower, AUTO/blower time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 0/blower, AUTO/ (+//-)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 0/mode, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 0/mode, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 0/mode, AUTO/step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 0/mode, AUTO/time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 0/mode, AUTO/ (+//-)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 1/2 way valve' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 1/DTG Rear, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 1/MATLAB Function1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 1/Time goto from step 1 to step 2 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 1/blower, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 1/incar filter down' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 1/incar filter up' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 1/mode, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 1/DTG Rear, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 1/DTG Rear, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 1/DTG Rear, AUTO/step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 1/DTG Rear, AUTO/time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 1/DTG Rear, AUTO/ (+//-)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 1/blower, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 1/blower, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 1/blower, AUTO/blower step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 1/blower, AUTO/blower time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 1/blower, AUTO/ (+//-)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 1/mode, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 1/mode, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 1/mode, AUTO/step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 1/mode, AUTO/time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 1/mode, AUTO/ (+//-)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 2/2 way valve' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 2/DTG Rear, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 2/MATLAB Function1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 2/Time goto from step 1 to step 2 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 2/blower, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 2/incar filter down' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 2/incar filter up' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 2/mode, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 2/DTG Rear, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 2/DTG Rear, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 2/DTG Rear, AUTO/step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 2/DTG Rear, AUTO/time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 2/DTG Rear, AUTO/ (+//-)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 2/blower, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 2/blower, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 2/blower, AUTO/blower step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 2/blower, AUTO/blower time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 2/blower, AUTO/ (+//-)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 2/mode, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 2/mode, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 2/mode, AUTO/step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 2/mode, AUTO/time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 2/mode, AUTO/ (+//-)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 3/2 way valve' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 3/DTG Rear, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 3/MATLAB Function1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 3/Time goto from step 1 to step 2 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 3/blower, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 3/incar filter down' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 3/incar filter up' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 3/mode, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 3/DTG Rear, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 3/DTG Rear, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 3/DTG Rear, AUTO/step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 3/DTG Rear, AUTO/time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 3/DTG Rear, AUTO/ (+//-)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 3/blower, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 3/blower, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 3/blower, AUTO/blower step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 3/blower, AUTO/blower time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 3/blower, AUTO/ (+//-)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 3/mode, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 3/mode, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 3/mode, AUTO/step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 3/mode, AUTO/time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 3/mode, AUTO/ (+//-)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 4/2 way valve' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 4/DTG Rear, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 4/MATLAB Function1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 4/Time goto from step 1 to step 2 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 4/blower, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 4/incar filter down' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 4/incar filter up' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 4/mode, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 4/DTG Rear, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 4/DTG Rear, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 4/DTG Rear, AUTO/step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 4/DTG Rear, AUTO/time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 4/DTG Rear, AUTO/ (+//-)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 4/blower, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 4/blower, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 4/blower, AUTO/blower step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 4/blower, AUTO/blower time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 4/blower, AUTO/ (+//-)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 4/mode, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 4/mode, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 4/mode, AUTO/step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 4/mode, AUTO/time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 4/mode, AUTO/ (+//-)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 5/2 way valve' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 5/DTG Rear, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 5/MATLAB Function1' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 5/Time goto from step 1 to step 2 ' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 5/blower, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 5/incar filter down' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 5/incar filter up' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 5/mode, AUTO' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 5/DTG Rear, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 5/DTG Rear, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 5/DTG Rear, AUTO/step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 5/DTG Rear, AUTO/time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 5/DTG Rear, AUTO/ (+//-)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 5/blower, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 5/blower, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 5/blower, AUTO/blower step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 5/blower, AUTO/blower time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 5/blower, AUTO/ (+//-)' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 5/mode, AUTO/Almost equal' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 5/mode, AUTO/Calculate delta time' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 5/mode, AUTO/step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 5/mode, AUTO/time for step' + * '' : 'HVAC_model/13,1,3,7 Start control/Start Control Rear/Step 2 R/Level 5/mode, AUTO/ (+//-)' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FLL_tg_correct (Front Left Lower (Legs))' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FLU_tg_correct (Front Left)' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FRL_tg_correct (Front Right Lower (Legs))' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ RL_tg_correct (Rear Left)' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ RR_tg_correct (Rear Right)' + * '' : 'HVAC_model/13.1.3.3 Dtg model/13,1,3,11 _5 AUTO mode FL' + * '' : 'HVAC_model/13.1.3.3 Dtg model/13,1,3,11 _5 AUTO mode FLL' + * '' : 'HVAC_model/13.1.3.3 Dtg model/13,1,3,11 _5 AUTO mode FR' + * '' : 'HVAC_model/13.1.3.3 Dtg model/13,1,3,11 _5 AUTO mode FRL' + * '' : 'HVAC_model/13.1.3.3 Dtg model/13,1,3,11 _5 AUTO mode RL' + * '' : 'HVAC_model/13.1.3.3 Dtg model/13,1,3,11 _5 AUTO mode RR' + * '' : 'HVAC_model/13.1.3.3 Dtg model/FRU_tg_correct (Front Right)' + * '' : 'HVAC_model/13.1.3.3 Dtg model/HI_FLL' + * '' : 'HVAC_model/13.1.3.3 Dtg model/HI_FLU' + * '' : 'HVAC_model/13.1.3.3 Dtg model/HI_FRL' + * '' : 'HVAC_model/13.1.3.3 Dtg model/HI_FRU' + * '' : 'HVAC_model/13.1.3.3 Dtg model/HI_RL' + * '' : 'HVAC_model/13.1.3.3 Dtg model/HI_RR' + * '' : 'HVAC_model/13.1.3.3 Dtg model/Individual foot' + * '' : 'HVAC_model/13.1.3.3 Dtg model/Individual foot1' + * '' : 'HVAC_model/13.1.3.3 Dtg model/Saturation Front lower' + * '' : 'HVAC_model/13.1.3.3 Dtg model/Saturation Front lower1' + * '' : 'HVAC_model/13.1.3.3 Dtg model/Saturation Front upper' + * '' : 'HVAC_model/13.1.3.3 Dtg model/Saturation Front upper1' + * '' : 'HVAC_model/13.1.3.3 Dtg model/if StartControl - FLL' + * '' : 'HVAC_model/13.1.3.3 Dtg model/if StartControl - FLU' + * '' : 'HVAC_model/13.1.3.3 Dtg model/if StartControl - FRL' + * '' : 'HVAC_model/13.1.3.3 Dtg model/if StartControl - FRU' + * '' : 'HVAC_model/13.1.3.3 Dtg model/if StartControl - RL' + * '' : 'HVAC_model/13.1.3.3 Dtg model/if StartControl - RR' + * '' : 'HVAC_model/13.1.3.3 Dtg model/wait_correction_left' + * '' : 'HVAC_model/13.1.3.3 Dtg model/wait_correction_right' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FLL_tg_correct (Front Left Lower (Legs))/2.5 FLL_tg_incar' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FLL_tg_correct (Front Left Lower (Legs))/2.6 FLL_tg_amb' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FLL_tg_correct (Front Left Lower (Legs))/2.7 FLL_tg_sun' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FLL_tg_correct (Front Left Lower (Legs))/MAX' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FLL_tg_correct (Front Left Lower (Legs))/MIN' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FLL_tg_correct (Front Left Lower (Legs))/Saturation Dynamic' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FLL_tg_correct (Front Left Lower (Legs))/2.5 FLL_tg_incar/X' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FLL_tg_correct (Front Left Lower (Legs))/2.5 FLL_tg_incar/Y' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FLL_tg_correct (Front Left Lower (Legs))/2.6 FLL_tg_amb/X' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FLL_tg_correct (Front Left Lower (Legs))/2.6 FLL_tg_amb/Y' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FLL_tg_correct (Front Left Lower (Legs))/2.7 FLL_tg_sun/X' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FLL_tg_correct (Front Left Lower (Legs))/2.7 FLL_tg_sun/Y' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FLU_tg_correct (Front Left)/2.5 FLU_tg_incar' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FLU_tg_correct (Front Left)/2.6 FLU_tg_amb' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FLU_tg_correct (Front Left)/2.7 FLU_tg_sun' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FLU_tg_correct (Front Left)/MAX' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FLU_tg_correct (Front Left)/MIN' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FLU_tg_correct (Front Left)/Saturation Dynamic' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FLU_tg_correct (Front Left)/2.5 FLU_tg_incar/X' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FLU_tg_correct (Front Left)/2.5 FLU_tg_incar/Y' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FLU_tg_correct (Front Left)/2.6 FLU_tg_amb/X' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FLU_tg_correct (Front Left)/2.6 FLU_tg_amb/Y' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FLU_tg_correct (Front Left)/2.7 FLU_tg_sun/X' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FLU_tg_correct (Front Left)/2.7 FLU_tg_sun/Y' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FRL_tg_correct (Front Right Lower (Legs))/2.5 FRL_tg_incar' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FRL_tg_correct (Front Right Lower (Legs))/2.6 FRL_tg_amb' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FRL_tg_correct (Front Right Lower (Legs))/2.7 FRL_tg_sun' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FRL_tg_correct (Front Right Lower (Legs))/MAX' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FRL_tg_correct (Front Right Lower (Legs))/MIN' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FRL_tg_correct (Front Right Lower (Legs))/Saturation Dynamic' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FRL_tg_correct (Front Right Lower (Legs))/2.5 FRL_tg_incar/X' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FRL_tg_correct (Front Right Lower (Legs))/2.5 FRL_tg_incar/Y' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FRL_tg_correct (Front Right Lower (Legs))/2.6 FRL_tg_amb/X' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FRL_tg_correct (Front Right Lower (Legs))/2.6 FRL_tg_amb/Y' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FRL_tg_correct (Front Right Lower (Legs))/2.7 FRL_tg_sun/X' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ FRL_tg_correct (Front Right Lower (Legs))/2.7 FRL_tg_sun/Y' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ RL_tg_correct (Rear Left)/2.5 RL_tg_incar' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ RL_tg_correct (Rear Left)/2.6 R_tg_amb' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ RL_tg_correct (Rear Left)/2.7 RL_tg_sun1' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ RL_tg_correct (Rear Left)/MAX' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ RL_tg_correct (Rear Left)/MIN' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ RL_tg_correct (Rear Left)/Saturation Dynamic' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ RL_tg_correct (Rear Left)/2.5 RL_tg_incar/X' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ RL_tg_correct (Rear Left)/2.5 RL_tg_incar/Y' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ RL_tg_correct (Rear Left)/2.6 R_tg_amb/X' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ RL_tg_correct (Rear Left)/2.6 R_tg_amb/Y' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ RL_tg_correct (Rear Left)/2.7 RL_tg_sun1/X' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ RL_tg_correct (Rear Left)/2.7 RL_tg_sun1/Y' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ RR_tg_correct (Rear Right)/2.5 RR_tg_incar' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ RR_tg_correct (Rear Right)/2.6 RR_tg_amb1' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ RR_tg_correct (Rear Right)/2.7 RR_tg_sun1' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ RR_tg_correct (Rear Right)/MAX' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ RR_tg_correct (Rear Right)/MIN' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ RR_tg_correct (Rear Right)/Saturation Dynamic' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ RR_tg_correct (Rear Right)/2.5 RR_tg_incar/X' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ RR_tg_correct (Rear Right)/2.5 RR_tg_incar/Y' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ RR_tg_correct (Rear Right)/2.6 RR_tg_amb1/X' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ RR_tg_correct (Rear Right)/2.6 RR_tg_amb1/Y' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ RR_tg_correct (Rear Right)/2.7 RR_tg_sun1/X' + * '' : 'HVAC_model/13.1.3.3 Dtg model/ RR_tg_correct (Rear Right)/2.7 RR_tg_sun1/Y' + * '' : 'HVAC_model/13.1.3.3 Dtg model/13,1,3,11 _5 AUTO mode FL/ ' + * '' : 'HVAC_model/13.1.3.3 Dtg model/13,1,3,11 _5 AUTO mode FL/ /func g_assAUTO_STEP_DUCT_TG_U' + * '' : 'HVAC_model/13.1.3.3 Dtg model/13,1,3,11 _5 AUTO mode FLL/ ' + * '' : 'HVAC_model/13.1.3.3 Dtg model/13,1,3,11 _5 AUTO mode FLL/ /func g_assAUTO_STEP_DUCT_TG_L' + * '' : 'HVAC_model/13.1.3.3 Dtg model/13,1,3,11 _5 AUTO mode FR/ ' + * '' : 'HVAC_model/13.1.3.3 Dtg model/13,1,3,11 _5 AUTO mode FR/ /func g_assAUTO_STEP_DUCT_TG_U' + * '' : 'HVAC_model/13.1.3.3 Dtg model/13,1,3,11 _5 AUTO mode FRL/ ' + * '' : 'HVAC_model/13.1.3.3 Dtg model/13,1,3,11 _5 AUTO mode FRL/ /func g_assAUTO_STEP_DUCT_TG_L' + * '' : 'HVAC_model/13.1.3.3 Dtg model/13,1,3,11 _5 AUTO mode RL/ ' + * '' : 'HVAC_model/13.1.3.3 Dtg model/13,1,3,11 _5 AUTO mode RL/ /func g_assAUTO_STEP_DUCT_TG_R' + * '' : 'HVAC_model/13.1.3.3 Dtg model/13,1,3,11 _5 AUTO mode RR/ ' + * '' : 'HVAC_model/13.1.3.3 Dtg model/13,1,3,11 _5 AUTO mode RR/ /func g_assAUTO_STEP_DUCT_TG_R' + * '' : 'HVAC_model/13.1.3.3 Dtg model/FRU_tg_correct (Front Right)/2.5 FRU_tg_incar' + * '' : 'HVAC_model/13.1.3.3 Dtg model/FRU_tg_correct (Front Right)/2.6 FRU_tg_amb' + * '' : 'HVAC_model/13.1.3.3 Dtg model/FRU_tg_correct (Front Right)/2.7 FRU_tg_sun' + * '' : 'HVAC_model/13.1.3.3 Dtg model/FRU_tg_correct (Front Right)/MAX' + * '' : 'HVAC_model/13.1.3.3 Dtg model/FRU_tg_correct (Front Right)/MIN' + * '' : 'HVAC_model/13.1.3.3 Dtg model/FRU_tg_correct (Front Right)/Saturation Dynamic1' + * '' : 'HVAC_model/13.1.3.3 Dtg model/FRU_tg_correct (Front Right)/2.5 FRU_tg_incar/X' + * '' : 'HVAC_model/13.1.3.3 Dtg model/FRU_tg_correct (Front Right)/2.5 FRU_tg_incar/Y' + * '' : 'HVAC_model/13.1.3.3 Dtg model/FRU_tg_correct (Front Right)/2.6 FRU_tg_amb/X' + * '' : 'HVAC_model/13.1.3.3 Dtg model/FRU_tg_correct (Front Right)/2.6 FRU_tg_amb/Y' + * '' : 'HVAC_model/13.1.3.3 Dtg model/FRU_tg_correct (Front Right)/2.7 FRU_tg_sun/X' + * '' : 'HVAC_model/13.1.3.3 Dtg model/FRU_tg_correct (Front Right)/2.7 FRU_tg_sun/Y' + * '' : 'HVAC_model/13.1.3.3 Dtg model/Saturation Front lower/Saturation Dynamic' + * '' : 'HVAC_model/13.1.3.3 Dtg model/Saturation Front lower1/Saturation Dynamic' + * '' : 'HVAC_model/13.1.3.3 Dtg model/Saturation Front upper/Saturation Dynamic' + * '' : 'HVAC_model/13.1.3.3 Dtg model/Saturation Front upper1/Saturation Dynamic' + * '' : 'HVAC_model/13.1.3.3 Dtg model/if StartControl - FLL/Compare To Constant' + * '' : 'HVAC_model/13.1.3.3 Dtg model/if StartControl - FLL/Compare To Constant1' + * '' : 'HVAC_model/13.1.3.3 Dtg model/if StartControl - FLL/Compare To Constant2' + * '' : 'HVAC_model/13.1.3.3 Dtg model/if StartControl - FLL/If Action Subsystem' + * '' : 'HVAC_model/13.1.3.3 Dtg model/if StartControl - FLL/If Action Subsystem1' + * '' : 'HVAC_model/13.1.3.3 Dtg model/if StartControl - FLU/Compare To Constant' + * '' : 'HVAC_model/13.1.3.3 Dtg model/if StartControl - FLU/Compare To Constant1' + * '' : 'HVAC_model/13.1.3.3 Dtg model/if StartControl - FLU/Compare To Constant2' + * '' : 'HVAC_model/13.1.3.3 Dtg model/if StartControl - FLU/If Action Subsystem' + * '' : 'HVAC_model/13.1.3.3 Dtg model/if StartControl - FLU/If Action Subsystem1' + * '' : 'HVAC_model/13.1.3.3 Dtg model/if StartControl - FRL/Compare To Constant' + * '' : 'HVAC_model/13.1.3.3 Dtg model/if StartControl - FRL/Compare To Constant1' + * '' : 'HVAC_model/13.1.3.3 Dtg model/if StartControl - FRL/Compare To Constant2' + * '' : 'HVAC_model/13.1.3.3 Dtg model/if StartControl - FRL/If Action Subsystem' + * '' : 'HVAC_model/13.1.3.3 Dtg model/if StartControl - FRL/If Action Subsystem1' + * '' : 'HVAC_model/13.1.3.3 Dtg model/if StartControl - FRU/Compare To Constant' + * '' : 'HVAC_model/13.1.3.3 Dtg model/if StartControl - FRU/Compare To Constant1' + * '' : 'HVAC_model/13.1.3.3 Dtg model/if StartControl - FRU/Compare To Constant2' + * '' : 'HVAC_model/13.1.3.3 Dtg model/if StartControl - FRU/If Action Subsystem' + * '' : 'HVAC_model/13.1.3.3 Dtg model/if StartControl - FRU/If Action Subsystem1' + * '' : 'HVAC_model/13.1.3.3 Dtg model/if StartControl - RL/Compare To Constant' + * '' : 'HVAC_model/13.1.3.3 Dtg model/if StartControl - RL/Compare To Constant1' + * '' : 'HVAC_model/13.1.3.3 Dtg model/if StartControl - RL/Compare To Constant2' + * '' : 'HVAC_model/13.1.3.3 Dtg model/if StartControl - RL/If Action Subsystem' + * '' : 'HVAC_model/13.1.3.3 Dtg model/if StartControl - RL/If Action Subsystem1' + * '' : 'HVAC_model/13.1.3.3 Dtg model/if StartControl - RR/Compare To Constant' + * '' : 'HVAC_model/13.1.3.3 Dtg model/if StartControl - RR/Compare To Constant1' + * '' : 'HVAC_model/13.1.3.3 Dtg model/if StartControl - RR/Compare To Constant2' + * '' : 'HVAC_model/13.1.3.3 Dtg model/if StartControl - RR/If Action Subsystem' + * '' : 'HVAC_model/13.1.3.3 Dtg model/if StartControl - RR/If Action Subsystem1' + * '' : 'HVAC_model/13.1.3.3 Dtg model/wait_correction_left/RealTime_Timer' + * '' : 'HVAC_model/13.1.3.3 Dtg model/wait_correction_left/Saturation Dynamic' + * '' : 'HVAC_model/13.1.3.3 Dtg model/wait_correction_left/correction max' + * '' : 'HVAC_model/13.1.3.3 Dtg model/wait_correction_left/correction rate' + * '' : 'HVAC_model/13.1.3.3 Dtg model/wait_correction_left/correction_start_time' + * '' : 'HVAC_model/13.1.3.3 Dtg model/wait_correction_left/is_ending_with_5' + * '' : 'HVAC_model/13.1.3.3 Dtg model/wait_correction_left/RealTime_Timer/Detect Rise Positive' + * '' : 'HVAC_model/13.1.3.3 Dtg model/wait_correction_left/RealTime_Timer/Detect Rise Positive/Positive' + * '' : 'HVAC_model/13.1.3.3 Dtg model/wait_correction_right/RealTime_Timer' + * '' : 'HVAC_model/13.1.3.3 Dtg model/wait_correction_right/Saturation Dynamic' + * '' : 'HVAC_model/13.1.3.3 Dtg model/wait_correction_right/correction max' + * '' : 'HVAC_model/13.1.3.3 Dtg model/wait_correction_right/correction rate' + * '' : 'HVAC_model/13.1.3.3 Dtg model/wait_correction_right/correction_start_time' + * '' : 'HVAC_model/13.1.3.3 Dtg model/wait_correction_right/is_ending_with_5' + * '' : 'HVAC_model/13.1.3.3 Dtg model/wait_correction_right/RealTime_Timer/Detect Rise Positive' + * '' : 'HVAC_model/13.1.3.3 Dtg model/wait_correction_right/RealTime_Timer/Detect Rise Positive/Positive' + * '' : 'HVAC_model/ACP/EvapF' + * '' : 'HVAC_model/ACP/EvapR' + * '' : 'HVAC_model/ACP/PRINT BTS5120_2EKA_ShutoffValvePowerTXV1' + * '' : 'HVAC_model/ACP/PRINT BTS5120_2EKA_ShutoffValvePowerTXV2' + * '' : 'HVAC_model/ACP/PRINT BTS5180_2EKA_ChannelPTCPower1' + * '' : 'HVAC_model/ACP/PRINT BTS5180_2EKA_ChannelPTCPower2' + * '' : 'HVAC_model/ACP/PRINT BTS5180_2EKA_FrontIncarMotor' + * '' : 'HVAC_model/ACP/PRINT BTS5180_2EKA_RearIncarMotor' + * '' : 'HVAC_model/ACP/PRINT BTS5180_2EKA_ReservePowerSupply' + * '' : 'HVAC_model/ACP/PRINT BTS5180_2EKA_ShutOFFValveFront' + * '' : 'HVAC_model/ACP/PRINT BTS5180_2EKA_ShutOFFValveRear' + * '' : 'HVAC_model/ACP/PRINT BTS5180_2EKA_TwoWayValve' + * '' : 'HVAC_model/ACP/PRINT IGN_ANS' + * '' : 'HVAC_model/ACP/PRINT PBATT_CHECK' + * '' : 'HVAC_model/ACP/PRINT Pressure_DIAG' + * '' : 'HVAC_model/ACP/PRINT Reserve_Sensor_Duct_Temp_1' + * '' : 'HVAC_model/ACP/PRINT Reserve_Sensor_Duct_Temp_2' + * '' : 'HVAC_model/ACP/PRINT Sensor_AC_Pressure' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct5' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct6' + * '' : 'HVAC_model/ACP/PRINT VN7008AJ_DIAG_FrontLINActuatorPowerDriverAB' + * '' : 'HVAC_model/ACP/PRINT VN7008AJ_DIAG_RearLINActuatorPowerDriverC' + * '' : 'HVAC_model/ACP/PRINT VN7008AJ_FrontLINActuatorPowerDriverAB' + * '' : 'HVAC_model/ACP/PRINT VN7008AJ_RearLINActuatorPowerDriverC' + * '' : 'HVAC_model/ACP/Rear_Duct' + * '' : 'HVAC_model/ACP/Write' + * '' : 'HVAC_model/ACP/Write1' + * '' : 'HVAC_model/ACP/Write2' + * '' : 'HVAC_model/ACP/Write3' + * '' : 'HVAC_model/ACP/Write4' + * '' : 'HVAC_model/ACP/filter incar' + * '' : 'HVAC_model/ACP/incar sensors' + * '' : 'HVAC_model/ACP/incar to dtg' + * '' : 'HVAC_model/ACP/EvapF/Compare To Constant' + * '' : 'HVAC_model/ACP/EvapF/Compare To Constant1' + * '' : 'HVAC_model/ACP/EvapF/Compare To Constant2' + * '' : 'HVAC_model/ACP/EvapF/RealTime_Timer' + * '' : 'HVAC_model/ACP/EvapF/UDS ERROR' + * '' : 'HVAC_model/ACP/EvapF/Write ERROR' + * '' : 'HVAC_model/ACP/EvapF/Write Eva_F' + * '' : 'HVAC_model/ACP/EvapR/Compare To Constant' + * '' : 'HVAC_model/ACP/EvapR/Compare To Constant1' + * '' : 'HVAC_model/ACP/EvapR/Compare To Constant2' + * '' : 'HVAC_model/ACP/EvapR/RealTime_Timer' + * '' : 'HVAC_model/ACP/EvapR/UDS ERROR' + * '' : 'HVAC_model/ACP/EvapR/Write ERROR' + * '' : 'HVAC_model/ACP/EvapR/Write Eva_F' + * '' : 'HVAC_model/ACP/PRINT BTS5120_2EKA_ShutoffValvePowerTXV1/Write' + * '' : 'HVAC_model/ACP/PRINT BTS5120_2EKA_ShutoffValvePowerTXV2/Write' + * '' : 'HVAC_model/ACP/PRINT BTS5180_2EKA_ChannelPTCPower1/Write' + * '' : 'HVAC_model/ACP/PRINT BTS5180_2EKA_ChannelPTCPower2/Write' + * '' : 'HVAC_model/ACP/PRINT BTS5180_2EKA_FrontIncarMotor/Write' + * '' : 'HVAC_model/ACP/PRINT BTS5180_2EKA_RearIncarMotor/Write' + * '' : 'HVAC_model/ACP/PRINT BTS5180_2EKA_ReservePowerSupply/Write' + * '' : 'HVAC_model/ACP/PRINT BTS5180_2EKA_ShutOFFValveFront/Write' + * '' : 'HVAC_model/ACP/PRINT BTS5180_2EKA_ShutOFFValveRear/Write' + * '' : 'HVAC_model/ACP/PRINT BTS5180_2EKA_TwoWayValve/Write' + * '' : 'HVAC_model/ACP/PRINT IGN_ANS/Write' + * '' : 'HVAC_model/ACP/PRINT PBATT_CHECK/Write' + * '' : 'HVAC_model/ACP/PRINT Pressure_DIAG/Write' + * '' : 'HVAC_model/ACP/PRINT Reserve_Sensor_Duct_Temp_1/Write' + * '' : 'HVAC_model/ACP/PRINT Reserve_Sensor_Duct_Temp_2/Write' + * '' : 'HVAC_model/ACP/PRINT Sensor_AC_Pressure/Compare To Constant' + * '' : 'HVAC_model/ACP/PRINT Sensor_AC_Pressure/Compare To Constant1' + * '' : 'HVAC_model/ACP/PRINT Sensor_AC_Pressure/Compare To Constant2' + * '' : 'HVAC_model/ACP/PRINT Sensor_AC_Pressure/RealTime_Timer' + * '' : 'HVAC_model/ACP/PRINT Sensor_AC_Pressure/UDS ERROR' + * '' : 'HVAC_model/ACP/PRINT Sensor_AC_Pressure/Write' + * '' : 'HVAC_model/ACP/PRINT Sensor_AC_Pressure/Write ERROR' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/Compare To Constant1' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/Compare To Constant10' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/Compare To Constant11' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/Compare To Constant12' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/Compare To Constant13' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/Compare To Constant14' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/Compare To Constant15' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/Compare To Constant16' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/Compare To Constant17' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/Compare To Constant18' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/Compare To Constant2' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/Compare To Constant3' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/Compare To Constant4' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/Compare To Constant5' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/Compare To Constant6' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/Compare To Constant7' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/Compare To Constant8' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/Compare To Constant9' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/RealTime_Timer1' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/RealTime_Timer2' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/RealTime_Timer3' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/RealTime_Timer4' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/RealTime_Timer5' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/RealTime_Timer6' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/UDS ERROR1' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/UDS ERROR2' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/UDS ERROR3' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/UDS ERROR4' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/UDS ERROR5' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/UDS ERROR6' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/Write 1' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/Write 2' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/Write 3' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/Write 4' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/Write 5' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/Write 6' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/Write ERROR1' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/Write ERROR2' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/Write ERROR3' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/Write ERROR4' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/Write ERROR5' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct1/Write ERROR6' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct5/Write' + * '' : 'HVAC_model/ACP/PRINT Sensor_Front_Duct6/Write' + * '' : 'HVAC_model/ACP/PRINT VN7008AJ_DIAG_FrontLINActuatorPowerDriverAB/Write' + * '' : 'HVAC_model/ACP/PRINT VN7008AJ_DIAG_RearLINActuatorPowerDriverC/Write' + * '' : 'HVAC_model/ACP/PRINT VN7008AJ_FrontLINActuatorPowerDriverAB/Write' + * '' : 'HVAC_model/ACP/PRINT VN7008AJ_RearLINActuatorPowerDriverC/Write' + * '' : 'HVAC_model/ACP/Rear_Duct/Compare To Constant' + * '' : 'HVAC_model/ACP/Rear_Duct/Compare To Constant1' + * '' : 'HVAC_model/ACP/Rear_Duct/Compare To Constant10' + * '' : 'HVAC_model/ACP/Rear_Duct/Compare To Constant11' + * '' : 'HVAC_model/ACP/Rear_Duct/Compare To Constant2' + * '' : 'HVAC_model/ACP/Rear_Duct/Compare To Constant3' + * '' : 'HVAC_model/ACP/Rear_Duct/Compare To Constant4' + * '' : 'HVAC_model/ACP/Rear_Duct/Compare To Constant5' + * '' : 'HVAC_model/ACP/Rear_Duct/Compare To Constant6' + * '' : 'HVAC_model/ACP/Rear_Duct/Compare To Constant7' + * '' : 'HVAC_model/ACP/Rear_Duct/Compare To Constant8' + * '' : 'HVAC_model/ACP/Rear_Duct/Compare To Constant9' + * '' : 'HVAC_model/ACP/Rear_Duct/RealTime_Timer' + * '' : 'HVAC_model/ACP/Rear_Duct/RealTime_Timer1' + * '' : 'HVAC_model/ACP/Rear_Duct/RealTime_Timer2' + * '' : 'HVAC_model/ACP/Rear_Duct/RealTime_Timer3' + * '' : 'HVAC_model/ACP/Rear_Duct/UDS ERROR' + * '' : 'HVAC_model/ACP/Rear_Duct/UDS ERROR1' + * '' : 'HVAC_model/ACP/Rear_Duct/UDS ERROR2' + * '' : 'HVAC_model/ACP/Rear_Duct/UDS ERROR3' + * '' : 'HVAC_model/ACP/Rear_Duct/Write ' + * '' : 'HVAC_model/ACP/Rear_Duct/Write 1' + * '' : 'HVAC_model/ACP/Rear_Duct/Write 2' + * '' : 'HVAC_model/ACP/Rear_Duct/Write 3' + * '' : 'HVAC_model/ACP/Rear_Duct/Write ERROR' + * '' : 'HVAC_model/ACP/Rear_Duct/Write ERROR1' + * '' : 'HVAC_model/ACP/Rear_Duct/Write ERROR2' + * '' : 'HVAC_model/ACP/Rear_Duct/Write ERROR3' + * '' : 'HVAC_model/ACP/filter incar/filter incar FL' + * '' : 'HVAC_model/ACP/filter incar/filter incar FR' + * '' : 'HVAC_model/ACP/filter incar/filter incar RL' + * '' : 'HVAC_model/ACP/filter incar/filter incar RR' + * '' : 'HVAC_model/ACP/filter incar/filter incar FL/ FL' + * '' : 'HVAC_model/ACP/filter incar/filter incar FL/ FL ' + * '' : 'HVAC_model/ACP/filter incar/filter incar FL/ FL /Almost equal' + * '' : 'HVAC_model/ACP/filter incar/filter incar FL/ FL /Calculate delta time' + * '' : 'HVAC_model/ACP/filter incar/filter incar FL/ FL / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar FL/ FL / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar FL/ FL / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar FL/ FL / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar FL/ FL / / /AMBRATE_RISING_DIFF[8]' + * '' : 'HVAC_model/ACP/filter incar/filter incar FL/ FL / / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar FL/ FL / / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar FL/ FL / / / / .' + * '' : 'HVAC_model/ACP/filter incar/filter incar FL/ FL / / / / .' + * '' : 'HVAC_model/ACP/filter incar/filter incar FL/ FL / / /AMBRATE_FALLING_DIFF[7]' + * '' : 'HVAC_model/ACP/filter incar/filter incar FL/ FL / / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar FL/ FL / / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar FL/ FL / / / / .' + * '' : 'HVAC_model/ACP/filter incar/filter incar FL/ FL / / / / .' + * '' : 'HVAC_model/ACP/filter incar/filter incar FL/ FL / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar FL/ FL / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar FL/ FL / / /g_ausINCARRATE_RISING_DIFF_F[8]' + * '' : 'HVAC_model/ACP/filter incar/filter incar FL/ FL / / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar FL/ FL / / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar FL/ FL / / / / .' + * '' : 'HVAC_model/ACP/filter incar/filter incar FL/ FL / / / / .' + * '' : 'HVAC_model/ACP/filter incar/filter incar FL/ FL / / /INCARRATE_RISING_DIFF_F[7]' + * '' : 'HVAC_model/ACP/filter incar/filter incar FL/ FL / / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar FL/ FL / / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar FL/ FL / / / / .' + * '' : 'HVAC_model/ACP/filter incar/filter incar FL/ FL / / / / .' + * '' : 'HVAC_model/ACP/filter incar/filter incar FR/ FR' + * '' : 'HVAC_model/ACP/filter incar/filter incar FR/ FR ' + * '' : 'HVAC_model/ACP/filter incar/filter incar FR/ FR /Almost equal' + * '' : 'HVAC_model/ACP/filter incar/filter incar FR/ FR /Calculate delta time' + * '' : 'HVAC_model/ACP/filter incar/filter incar FR/ FR / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar FR/ FR / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar FR/ FR / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar FR/ FR / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar FR/ FR / / /AMBRATE_RISING_DIFF[8]' + * '' : 'HVAC_model/ACP/filter incar/filter incar FR/ FR / / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar FR/ FR / / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar FR/ FR / / / / .' + * '' : 'HVAC_model/ACP/filter incar/filter incar FR/ FR / / / / .' + * '' : 'HVAC_model/ACP/filter incar/filter incar FR/ FR / / /AMBRATE_FALLING_DIFF[7]' + * '' : 'HVAC_model/ACP/filter incar/filter incar FR/ FR / / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar FR/ FR / / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar FR/ FR / / / / .' + * '' : 'HVAC_model/ACP/filter incar/filter incar FR/ FR / / / / .' + * '' : 'HVAC_model/ACP/filter incar/filter incar FR/ FR / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar FR/ FR / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar FR/ FR / / /g_ausINCARRATE_RISING_DIFF_F[8]' + * '' : 'HVAC_model/ACP/filter incar/filter incar FR/ FR / / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar FR/ FR / / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar FR/ FR / / / / .' + * '' : 'HVAC_model/ACP/filter incar/filter incar FR/ FR / / / / .' + * '' : 'HVAC_model/ACP/filter incar/filter incar FR/ FR / / /INCARRATE_RISING_DIFF_F[7]' + * '' : 'HVAC_model/ACP/filter incar/filter incar FR/ FR / / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar FR/ FR / / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar FR/ FR / / / / .' + * '' : 'HVAC_model/ACP/filter incar/filter incar FR/ FR / / / / .' + * '' : 'HVAC_model/ACP/filter incar/filter incar RL/ RL' + * '' : 'HVAC_model/ACP/filter incar/filter incar RL/ RL ' + * '' : 'HVAC_model/ACP/filter incar/filter incar RL/ RL /Almost equal' + * '' : 'HVAC_model/ACP/filter incar/filter incar RL/ RL /Calculate delta time' + * '' : 'HVAC_model/ACP/filter incar/filter incar RL/ RL / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar RL/ RL / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar RL/ RL / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar RL/ RL / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar RL/ RL / / /AMBRATE_RISING_DIFF[8]' + * '' : 'HVAC_model/ACP/filter incar/filter incar RL/ RL / / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar RL/ RL / / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar RL/ RL / / / / .' + * '' : 'HVAC_model/ACP/filter incar/filter incar RL/ RL / / / / .' + * '' : 'HVAC_model/ACP/filter incar/filter incar RL/ RL / / /AMBRATE_FALLING_DIFF[7]' + * '' : 'HVAC_model/ACP/filter incar/filter incar RL/ RL / / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar RL/ RL / / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar RL/ RL / / / / .' + * '' : 'HVAC_model/ACP/filter incar/filter incar RL/ RL / / / / .' + * '' : 'HVAC_model/ACP/filter incar/filter incar RL/ RL / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar RL/ RL / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar RL/ RL / / /g_ausINCARRATE_RISING_DIFF_R[8]' + * '' : 'HVAC_model/ACP/filter incar/filter incar RL/ RL / / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar RL/ RL / / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar RL/ RL / / / / .' + * '' : 'HVAC_model/ACP/filter incar/filter incar RL/ RL / / / / .' + * '' : 'HVAC_model/ACP/filter incar/filter incar RL/ RL / / /INCARRATE_RISING_DIFF_R[7]' + * '' : 'HVAC_model/ACP/filter incar/filter incar RL/ RL / / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar RL/ RL / / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar RL/ RL / / / / .' + * '' : 'HVAC_model/ACP/filter incar/filter incar RL/ RL / / / / .' + * '' : 'HVAC_model/ACP/filter incar/filter incar RR/ RR' + * '' : 'HVAC_model/ACP/filter incar/filter incar RR/ RR ' + * '' : 'HVAC_model/ACP/filter incar/filter incar RR/ RR /Almost equal' + * '' : 'HVAC_model/ACP/filter incar/filter incar RR/ RR /Calculate delta time' + * '' : 'HVAC_model/ACP/filter incar/filter incar RR/ RR / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar RR/ RR / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar RR/ RR / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar RR/ RR / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar RR/ RR / / /AMBRATE_RISING_DIFF[8]' + * '' : 'HVAC_model/ACP/filter incar/filter incar RR/ RR / / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar RR/ RR / / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar RR/ RR / / / / .' + * '' : 'HVAC_model/ACP/filter incar/filter incar RR/ RR / / / / .' + * '' : 'HVAC_model/ACP/filter incar/filter incar RR/ RR / / /AMBRATE_FALLING_DIFF[7]' + * '' : 'HVAC_model/ACP/filter incar/filter incar RR/ RR / / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar RR/ RR / / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar RR/ RR / / / / .' + * '' : 'HVAC_model/ACP/filter incar/filter incar RR/ RR / / / / .' + * '' : 'HVAC_model/ACP/filter incar/filter incar RR/ RR / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar RR/ RR / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar RR/ RR / / /g_ausINCARRATE_RISING_DIFF_R[8]' + * '' : 'HVAC_model/ACP/filter incar/filter incar RR/ RR / / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar RR/ RR / / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar RR/ RR / / / / .' + * '' : 'HVAC_model/ACP/filter incar/filter incar RR/ RR / / / / .' + * '' : 'HVAC_model/ACP/filter incar/filter incar RR/ RR / / /INCARRATE_RISING_DIFF_R[7]' + * '' : 'HVAC_model/ACP/filter incar/filter incar RR/ RR / / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar RR/ RR / / / ' + * '' : 'HVAC_model/ACP/filter incar/filter incar RR/ RR / / / / .' + * '' : 'HVAC_model/ACP/filter incar/filter incar RR/ RR / / / / .' + * '' : 'HVAC_model/ACP/incar sensors/incar FL' + * '' : 'HVAC_model/ACP/incar sensors/incar FR' + * '' : 'HVAC_model/ACP/incar sensors/incar RL' + * '' : 'HVAC_model/ACP/incar sensors/incar RR' + * '' : 'HVAC_model/ACP/incar sensors/process error F' + * '' : 'HVAC_model/ACP/incar sensors/process error R' + * '' : 'HVAC_model/ACP/incar sensors/incar FL/Compare To Constant' + * '' : 'HVAC_model/ACP/incar sensors/incar FL/Compare To Constant1' + * '' : 'HVAC_model/ACP/incar sensors/incar FL/Compare To Constant2' + * '' : 'HVAC_model/ACP/incar sensors/incar FL/RealTime_Timer' + * '' : 'HVAC_model/ACP/incar sensors/incar FL/UDS ERROR' + * '' : 'HVAC_model/ACP/incar sensors/incar FL/Write ERROR' + * '' : 'HVAC_model/ACP/incar sensors/incar FR/Compare To Constant6' + * '' : 'HVAC_model/ACP/incar sensors/incar FR/Compare To Constant7' + * '' : 'HVAC_model/ACP/incar sensors/incar FR/Compare To Constant8' + * '' : 'HVAC_model/ACP/incar sensors/incar FR/RealTime_Timer2' + * '' : 'HVAC_model/ACP/incar sensors/incar FR/UDS ERROR2' + * '' : 'HVAC_model/ACP/incar sensors/incar FR/Write ERROR2' + * '' : 'HVAC_model/ACP/incar sensors/incar RL/Compare To Constant3' + * '' : 'HVAC_model/ACP/incar sensors/incar RL/Compare To Constant4' + * '' : 'HVAC_model/ACP/incar sensors/incar RL/Compare To Constant5' + * '' : 'HVAC_model/ACP/incar sensors/incar RL/RealTime_Timer1' + * '' : 'HVAC_model/ACP/incar sensors/incar RL/UDS ERROR1' + * '' : 'HVAC_model/ACP/incar sensors/incar RL/Write ERROR1' + * '' : 'HVAC_model/ACP/incar sensors/incar RR/Compare To Constant10' + * '' : 'HVAC_model/ACP/incar sensors/incar RR/Compare To Constant11' + * '' : 'HVAC_model/ACP/incar sensors/incar RR/Compare To Constant9' + * '' : 'HVAC_model/ACP/incar sensors/incar RR/RealTime_Timer3' + * '' : 'HVAC_model/ACP/incar sensors/incar RR/UDS ERROR3' + * '' : 'HVAC_model/ACP/incar sensors/incar RR/Write ERROR3' + * '' : 'HVAC_model/ACP/incar sensors/process error F/Write IncarFL' + * '' : 'HVAC_model/ACP/incar sensors/process error F/Write IncarFR' + * '' : 'HVAC_model/ACP/incar sensors/process error R/Write IncarRL' + * '' : 'HVAC_model/ACP/incar sensors/process error R/Write IncarRR' + * '' : 'HVAC_model/AUTO/Determine directions FL' + * '' : 'HVAC_model/AUTO/Determine directions FR' + * '' : 'HVAC_model/AUTO/Determine directions RL' + * '' : 'HVAC_model/AUTO/Determine directions RR' + * '' : 'HVAC_model/AUTO/Zone_Climate_Logic_Auto_FL1' + * '' : 'HVAC_model/AUTO/Zone_Climate_Logic_Auto_FL2' + * '' : 'HVAC_model/AUTO/Zone_Climate_Logic_Auto_FL3' + * '' : 'HVAC_model/AUTO/Zone_Climate_Logic_Auto_FL4' + * '' : 'HVAC_model/AUTO/ ' + * '' : 'HVAC_model/AUTO/ 1' + * '' : 'HVAC_model/AUTO/ 2' + * '' : 'HVAC_model/AUTO/ 3' + * '' : 'HVAC_model/AUTO/Determine directions FL/AF AutoFoot' + * '' : 'HVAC_model/AUTO/Determine directions FL/AF AutoFoot summer' + * '' : 'HVAC_model/AUTO/Determine directions FL/AF Bi level' + * '' : 'HVAC_model/AUTO/Determine directions FL/AF Bi level 2' + * '' : 'HVAC_model/AUTO/Determine directions FL/AF Defrost' + * '' : 'HVAC_model/AUTO/Determine directions FL/AF Foot' + * '' : 'HVAC_model/AUTO/Determine directions FL/AF Foot + Def' + * '' : 'HVAC_model/AUTO/Determine directions FL/AF Hi (def + vent)' + * '' : 'HVAC_model/AUTO/Determine directions FL/AF Tri mode' + * '' : 'HVAC_model/AUTO/Determine directions FL/AF VENT' + * '' : 'HVAC_model/AUTO/Determine directions FL/AF VENT (fail safe)' + * '' : 'HVAC_model/AUTO/Determine directions FL/closest speed' + * '' : 'HVAC_model/AUTO/Determine directions FL/direction for front index mode' + * '' : 'HVAC_model/AUTO/Determine directions FR/AF AutoFoot' + * '' : 'HVAC_model/AUTO/Determine directions FR/AF AutoFoot summer' + * '' : 'HVAC_model/AUTO/Determine directions FR/AF Bi level' + * '' : 'HVAC_model/AUTO/Determine directions FR/AF Bi level 2' + * '' : 'HVAC_model/AUTO/Determine directions FR/AF Defrost' + * '' : 'HVAC_model/AUTO/Determine directions FR/AF Foot' + * '' : 'HVAC_model/AUTO/Determine directions FR/AF Foot + Def' + * '' : 'HVAC_model/AUTO/Determine directions FR/AF Hi (def + vent)' + * '' : 'HVAC_model/AUTO/Determine directions FR/AF Tri mode' + * '' : 'HVAC_model/AUTO/Determine directions FR/AF VENT' + * '' : 'HVAC_model/AUTO/Determine directions FR/AF VENT (fail safe)' + * '' : 'HVAC_model/AUTO/Determine directions FR/closest speed' + * '' : 'HVAC_model/AUTO/Determine directions FR/direction for front index mode' + * '' : 'HVAC_model/AUTO/Determine directions RL/AF REAR Bi Level' + * '' : 'HVAC_model/AUTO/Determine directions RL/AF REAR Foot' + * '' : 'HVAC_model/AUTO/Determine directions RL/AF REAR VENT AUTO' + * '' : 'HVAC_model/AUTO/Determine directions RL/AF REAR VENT AUTO1' + * '' : 'HVAC_model/AUTO/Determine directions RL/closest speed' + * '' : 'HVAC_model/AUTO/Determine directions RL/direction for REAR index mode' + * '' : 'HVAC_model/AUTO/Determine directions RR/AF REAR Bi Level' + * '' : 'HVAC_model/AUTO/Determine directions RR/AF REAR Foot' + * '' : 'HVAC_model/AUTO/Determine directions RR/AF REAR VENT AUTO' + * '' : 'HVAC_model/AUTO/Determine directions RR/AF REAR VENT AUTO1' + * '' : 'HVAC_model/AUTO/Determine directions RR/closest speed' + * '' : 'HVAC_model/AUTO/Determine directions RR/direction for REAR index mode1' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower (PWM) in manual mode' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Individual foot' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Individual foot1' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/if start control FL' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/if start control FR' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/if start control RL' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/if start control RR' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower (PWM) in manual mode/Front zone PWM' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower (PWM) in manual mode/Rear zone PWM' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower (PWM) in manual mode/Front zone PWM/Front Left AF - manual directions' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower (PWM) in manual mode/Front zone PWM/Front Right AF - manual directions' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower (PWM) in manual mode/Front zone PWM/Front Left AF - manual directions/AF for Bi Level' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower (PWM) in manual mode/Front zone PWM/Front Left AF - manual directions/AF for Def' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower (PWM) in manual mode/Front zone PWM/Front Left AF - manual directions/AF for Foor + Def' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower (PWM) in manual mode/Front zone PWM/Front Left AF - manual directions/AF for Foot' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower (PWM) in manual mode/Front zone PWM/Front Left AF - manual directions/AF for Hi_Level' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower (PWM) in manual mode/Front zone PWM/Front Left AF - manual directions/AF for Tri-Level' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower (PWM) in manual mode/Front zone PWM/Front Left AF - manual directions/AF for Vent mode' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower (PWM) in manual mode/Front zone PWM/Front Right AF - manual directions/AF for Bi Level' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower (PWM) in manual mode/Front zone PWM/Front Right AF - manual directions/AF for Def' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower (PWM) in manual mode/Front zone PWM/Front Right AF - manual directions/AF for Foor + Def' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower (PWM) in manual mode/Front zone PWM/Front Right AF - manual directions/AF for Foot' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower (PWM) in manual mode/Front zone PWM/Front Right AF - manual directions/AF for Hi_Level' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower (PWM) in manual mode/Front zone PWM/Front Right AF - manual directions/AF for Tri-Level' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower (PWM) in manual mode/Front zone PWM/Front Right AF - manual directions/AF for Vent mode' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower (PWM) in manual mode/Rear zone PWM/Rear Left AF - manual directions' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower (PWM) in manual mode/Rear zone PWM/Rear Right AF - manual directions' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower (PWM) in manual mode/Rear zone PWM/Rear Left AF - manual directions/AF for Bi Level R' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower (PWM) in manual mode/Rear zone PWM/Rear Left AF - manual directions/AF for Foot R' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower (PWM) in manual mode/Rear zone PWM/Rear Left AF - manual directions/AF for Vent mode R' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower (PWM) in manual mode/Rear zone PWM/Rear Right AF - manual directions/AF for Bi Level R' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower (PWM) in manual mode/Rear zone PWM/Rear Right AF - manual directions/AF for Foot R' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower (PWM) in manual mode/Rear zone PWM/Rear Right AF - manual directions/AF for Vent mode R' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/13,1,3,11 _5 AUTO mode AF_FL' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/13,1,3,11 _5 AUTO mode AF_FR' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/13,1,3,11 _5 AUTO mode AF_RL' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/13,1,3,11 _5 AUTO mode AF_RR' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Rear' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/13,1,3,11 _5 AUTO mode AF_FL/func g_ascAUTO_STEP_AF_F' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/13,1,3,11 _5 AUTO mode AF_FR/func g_ascAUTO_STEP_AF_F' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/13,1,3,11 _5 AUTO mode AF_RL/func g_ascAUTO_STEP_AF_F' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/13,1,3,11 _5 AUTO mode AF_RR/func g_ascAUTO_STEP_AF_F' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/Calc Vtg_FL_correct (Front Left)' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/Calc Vtg_FR_correct (Front Right)' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/wait_correction_left' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/wait_correction_right' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/Calc Vtg_FL_correct (Front Left)/2.5 Vtg_FL_incar' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/Calc Vtg_FL_correct (Front Left)/2.6 Vtg_FX_amb' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/Calc Vtg_FL_correct (Front Left)/2.7 Vtg_FX_sun' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/Calc Vtg_FL_correct (Front Left)/MAX1' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/Calc Vtg_FL_correct (Front Left)/MIN1' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/Calc Vtg_FL_correct (Front Left)/Saturation Dynamic' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/Calc Vtg_FL_correct (Front Left)/2.5 Vtg_FL_incar/X' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/Calc Vtg_FL_correct (Front Left)/2.5 Vtg_FL_incar/Y' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/Calc Vtg_FL_correct (Front Left)/2.6 Vtg_FX_amb/X' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/Calc Vtg_FL_correct (Front Left)/2.6 Vtg_FX_amb/Y' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/Calc Vtg_FL_correct (Front Left)/2.7 Vtg_FX_sun/X' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/Calc Vtg_FL_correct (Front Left)/2.7 Vtg_FX_sun/Y' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/Calc Vtg_FR_correct (Front Right)/2.5 Vtg_FR_incar' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/Calc Vtg_FR_correct (Front Right)/2.6 Vtg_FX_amb' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/Calc Vtg_FR_correct (Front Right)/2.7 Vtg_FR_sun' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/Calc Vtg_FR_correct (Front Right)/MAX1' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/Calc Vtg_FR_correct (Front Right)/MIN1' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/Calc Vtg_FR_correct (Front Right)/Saturation Dynamic' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/Calc Vtg_FR_correct (Front Right)/2.5 Vtg_FR_incar/X' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/Calc Vtg_FR_correct (Front Right)/2.5 Vtg_FR_incar/Y' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/Calc Vtg_FR_correct (Front Right)/2.6 Vtg_FX_amb/X' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/Calc Vtg_FR_correct (Front Right)/2.6 Vtg_FX_amb/Y' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/Calc Vtg_FR_correct (Front Right)/2.7 Vtg_FR_sun/X' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/Calc Vtg_FR_correct (Front Right)/2.7 Vtg_FR_sun/Y' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/wait_correction_left/RealTime_Timer' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/wait_correction_left/Saturation Dynamic' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/wait_correction_left/correction max' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/wait_correction_left/correction rate' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/wait_correction_left/correction_start_time' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/wait_correction_left/is_ending_with_5' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/wait_correction_left/RealTime_Timer/Detect Rise Positive' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/wait_correction_left/RealTime_Timer/Detect Rise Positive/Positive' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/wait_correction_right/RealTime_Timer' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/wait_correction_right/Saturation Dynamic' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/wait_correction_right/correction max' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/wait_correction_right/correction rate' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/wait_correction_right/correction_start_time' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/wait_correction_right/is_ending_with_5' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/wait_correction_right/RealTime_Timer/Detect Rise Positive' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Front/wait_correction_right/RealTime_Timer/Detect Rise Positive/Positive' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Rear/Calc Vtg_RL_correct (Rear Left)' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Rear/Calc Vtg_RR_correct (Rear Right)1' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Rear/Calc Vtg_RL_correct (Rear Left)/2.5 Vtg_RL_incar' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Rear/Calc Vtg_RL_correct (Rear Left)/2.6 Vtg_RX_amb' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Rear/Calc Vtg_RL_correct (Rear Left)/2.7 Vtg_RX_sun' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Rear/Calc Vtg_RL_correct (Rear Left)/MAX' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Rear/Calc Vtg_RL_correct (Rear Left)/MIN' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Rear/Calc Vtg_RL_correct (Rear Left)/Saturation Dynamic' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Rear/Calc Vtg_RL_correct (Rear Left)/2.5 Vtg_RL_incar/X' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Rear/Calc Vtg_RL_correct (Rear Left)/2.5 Vtg_RL_incar/Y' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Rear/Calc Vtg_RL_correct (Rear Left)/2.6 Vtg_RX_amb/X' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Rear/Calc Vtg_RL_correct (Rear Left)/2.6 Vtg_RX_amb/Y' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Rear/Calc Vtg_RL_correct (Rear Left)/2.7 Vtg_RX_sun/X' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Rear/Calc Vtg_RL_correct (Rear Left)/2.7 Vtg_RX_sun/Y' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Rear/Calc Vtg_RR_correct (Rear Right)1/2.5 Vtg_RR_incar' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Rear/Calc Vtg_RR_correct (Rear Right)1/2.6 Vtg_RX_amb' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Rear/Calc Vtg_RR_correct (Rear Right)1/2.7 Vtg_RX_sun' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Rear/Calc Vtg_RR_correct (Rear Right)1/MAX' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Rear/Calc Vtg_RR_correct (Rear Right)1/MIN' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Rear/Calc Vtg_RR_correct (Rear Right)1/Saturation Dynamic' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Rear/Calc Vtg_RR_correct (Rear Right)1/2.5 Vtg_RR_incar/X' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Rear/Calc Vtg_RR_correct (Rear Right)1/2.5 Vtg_RR_incar/Y' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Rear/Calc Vtg_RR_correct (Rear Right)1/2.6 Vtg_RX_amb/X' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Rear/Calc Vtg_RR_correct (Rear Right)1/2.6 Vtg_RX_amb/Y' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Rear/Calc Vtg_RR_correct (Rear Right)1/2.7 Vtg_RX_sun/X' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/Blower speed (auto mode)/Rear/Calc Vtg_RR_correct (Rear Right)1/2.7 Vtg_RX_sun/Y' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/if start control FL/Compare To Constant' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/if start control FL/Compare To Constant1' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/if start control FL/Compare To Constant2' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/if start control FR/Compare To Constant' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/if start control FR/Compare To Constant1' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/if start control FR/Compare To Constant2' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/if start control RL/Compare To Constant' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/if start control RL/Compare To Constant1' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/if start control RL/Compare To Constant2' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/if start control RR/Compare To Constant' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/if start control RR/Compare To Constant1' + * '' : 'HVAC_model/Blower speed (AF) auto or manual/if start control RR/Compare To Constant2' + * '' : 'HVAC_model/CAN INPUT/Sleep_mode' + * '' : 'HVAC_model/CAN INPUT/Subsystem45' + * '' : 'HVAC_model/CAN INPUT/Subsystem46' + * '' : 'HVAC_model/CAN INPUT/Subsystem47' + * '' : 'HVAC_model/CAN INPUT/Subsystem48' + * '' : 'HVAC_model/CAN INPUT/Subsystem49' + * '' : 'HVAC_model/CAN INPUT/Subsystem50' + * '' : 'HVAC_model/CAN INPUT/Subsystem53' + * '' : 'HVAC_model/CAN INPUT/Subsystem62' + * '' : 'HVAC_model/CAN INPUT/Subsystem63' + * '' : 'HVAC_model/CAN INPUT/Subsystem64' + * '' : 'HVAC_model/CAN INPUT/Sleep_mode/Subsystem2' + * '' : 'HVAC_model/CAN INPUT/Sleep_mode/Subsystem3' + * '' : 'HVAC_model/CAN INPUT/Sleep_mode/Subsystem5' + * '' : 'HVAC_model/CAN INPUT/Sleep_mode/Subsystem6' + * '' : 'HVAC_model/CAN INPUT/Sleep_mode/Subsystem2/LO HI mode' + * '' : 'HVAC_model/CAN INPUT/Sleep_mode/Subsystem2/LO HI mode/HI mode' + * '' : 'HVAC_model/CAN INPUT/Sleep_mode/Subsystem2/LO HI mode/LO mode' + * '' : 'HVAC_model/CAN INPUT/Sleep_mode/Subsystem2/LO HI mode/not LO or HI' + * '' : 'HVAC_model/CAN INPUT/Sleep_mode/Subsystem3/LO HI mode' + * '' : 'HVAC_model/CAN INPUT/Sleep_mode/Subsystem3/LO HI mode/HI mode' + * '' : 'HVAC_model/CAN INPUT/Sleep_mode/Subsystem3/LO HI mode/LO mode' + * '' : 'HVAC_model/CAN INPUT/Sleep_mode/Subsystem3/LO HI mode/not LO or HI' + * '' : 'HVAC_model/CAN INPUT/Sleep_mode/Subsystem5/LO HI mode' + * '' : 'HVAC_model/CAN INPUT/Sleep_mode/Subsystem5/LO HI mode/HI mode' + * '' : 'HVAC_model/CAN INPUT/Sleep_mode/Subsystem5/LO HI mode/LO mode' + * '' : 'HVAC_model/CAN INPUT/Sleep_mode/Subsystem5/LO HI mode/not LO or HI' + * '' : 'HVAC_model/CAN INPUT/Sleep_mode/Subsystem6/LO HI mode' + * '' : 'HVAC_model/CAN INPUT/Sleep_mode/Subsystem6/LO HI mode/HI mode' + * '' : 'HVAC_model/CAN INPUT/Sleep_mode/Subsystem6/LO HI mode/LO mode' + * '' : 'HVAC_model/CAN INPUT/Sleep_mode/Subsystem6/LO HI mode/not LO or HI' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ /Calculate delta time' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ /Coolant temp threshold' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / /' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/Almost equal' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / /AMBRATE_RISING_DIFF[8]' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / / / .' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / / / .' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / /AMBRATE_FALLING_DIFF[7]' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / / / .' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / / / .' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / /AMBRATE_RISING_DIFF[8]' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / / / .' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / / / .' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / /AMBRATE_RISING_DIFF[7]' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / / / .' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / / / .' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/Almost equal' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / /AMBRATE_RISING_DIFF[8]' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / / / .' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / / / .' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / /AMBRATE_FALLING_DIFF[7]' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / / / .' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / / / .' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / /AMBRATE_RISING_DIFF[8]' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / / / .' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / / / .' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / /AMBRATE_RISING_DIFF[7]' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / / / .' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / - /Subsystem Reference/ / / / .' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / //Almost equal' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / // ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / // ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / // / .' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / // /' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" /Almost equal' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / /AMBRATE_RISING_DIFF[8]' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / / / .' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / / / .' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / /AMBRATE_FALLING_DIFF[7]' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / / / .' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / / / .' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / /AMBRATE_RISING_DIFF[8]' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / / / .' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / / / .' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / /AMBRATE_RISING_DIFF[7]' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / / ' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / / / .' + * '' : 'HVAC_model/CAN INPUT/Subsystem45/10.2 filter_sensor_ambient/ / "" / / / / .' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/AC_Max_Active' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Compare To Constant' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Compare To Constant1' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Compare To Constant2' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Compare To Constant3' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Compare To Constant4' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Compare To Constant5' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Compare To Constant7' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Defrost_Active' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Detect Increase' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Detect Increase1' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Detect Increase2' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Detect Increase3' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Detect Increase4' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Detect Increase5' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Detect Increase7' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Full_Rec_Active' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem1' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem10' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem11' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem12' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem13' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem14' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem15' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem16' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem17' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem18' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem19' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem2' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem20' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem21' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem22' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem23' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem24' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem25' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem26' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem27' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem28' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem29' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem3' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem30' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem31' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem32' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem33' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem34' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem35' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem36' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem37' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem38' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem39' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem4' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem40' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem41' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem42' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem43' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem44' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem5' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem51' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem52' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem6' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem7' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem8' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem9' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/if action' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/if action1' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/if action2' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/if action4' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleFL' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleFR' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleRL' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleRR' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem1/If Action Subsystem' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem2/LO HI mode' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem2/LO HI mode/HI mode' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem2/LO HI mode/LO mode' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem2/LO HI mode/not LO or HI' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem24/full sync action' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem24/sync front action' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem24/sync off action' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem3/LO HI mode' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem3/LO HI mode/HI mode' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem3/LO HI mode/LO mode' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem3/LO HI mode/not LO or HI' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem44/sync off rear action' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem44/sync rear action' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem44/sync off rear action/logger' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem44/sync rear action/logger' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem5/LO HI mode' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem5/LO HI mode/HI mode' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem5/LO HI mode/LO mode' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem5/LO HI mode/not LO or HI' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem6/LO HI mode' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem6/LO HI mode/HI mode' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem6/LO HI mode/LO mode' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/Subsystem6/LO HI mode/not LO or HI' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/if action/sync front action1' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/if action/sync front action3' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/if action1/sync front action1' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/if action1/sync front action3' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/if action2/sync front action1' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/if action2/sync front action3' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/if action4/sync front action1' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/if action4/sync front action3' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleFL/Compare To Constant3' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleFL/Detect Increase3' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleFL/If Action Subsystem' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleFL/If Action Subsystem/temp down' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleFL/If Action Subsystem/temp up' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleFL/If Action Subsystem/temp down/LO HI mode R' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleFL/If Action Subsystem/temp down/LO HI mode R/HI mode' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleFL/If Action Subsystem/temp down/LO HI mode R/LO mode' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleFL/If Action Subsystem/temp down/LO HI mode R/not LO or HI' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleFL/If Action Subsystem/temp up/LO HI mode R' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleFL/If Action Subsystem/temp up/LO HI mode R/HI mode' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleFL/If Action Subsystem/temp up/LO HI mode R/LO mode' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleFL/If Action Subsystem/temp up/LO HI mode R/not LO or HI' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleFR/Compare To Constant3' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleFR/Detect Increase3' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleFR/If Action Subsystem' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleFR/If Action Subsystem/temp down' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleFR/If Action Subsystem/temp up' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleFR/If Action Subsystem/temp down/LO HI mode R' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleFR/If Action Subsystem/temp down/LO HI mode R/HI mode' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleFR/If Action Subsystem/temp down/LO HI mode R/LO mode' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleFR/If Action Subsystem/temp down/LO HI mode R/not LO or HI' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleFR/If Action Subsystem/temp up/LO HI mode R' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleFR/If Action Subsystem/temp up/LO HI mode R/HI mode' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleFR/If Action Subsystem/temp up/LO HI mode R/LO mode' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleFR/If Action Subsystem/temp up/LO HI mode R/not LO or HI' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleRL/Compare To Constant3' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleRL/Detect Increase3' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleRL/If Action Subsystem' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleRL/If Action Subsystem/temp down' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleRL/If Action Subsystem/temp up' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleRL/If Action Subsystem/temp down/LO HI mode R' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleRL/If Action Subsystem/temp down/LO HI mode R/HI mode' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleRL/If Action Subsystem/temp down/LO HI mode R/LO mode' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleRL/If Action Subsystem/temp down/LO HI mode R/not LO or HI' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleRL/If Action Subsystem/temp up/LO HI mode R' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleRL/If Action Subsystem/temp up/LO HI mode R/HI mode' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleRL/If Action Subsystem/temp up/LO HI mode R/LO mode' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleRL/If Action Subsystem/temp up/LO HI mode R/not LO or HI' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleRR/Compare To Constant3' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleRR/Detect Increase3' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleRR/If Action Subsystem' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleRR/If Action Subsystem/temp down' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleRR/If Action Subsystem/temp up' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleRR/If Action Subsystem/temp down/LO HI mode R' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleRR/If Action Subsystem/temp down/LO HI mode R/HI mode' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleRR/If Action Subsystem/temp down/LO HI mode R/LO mode' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleRR/If Action Subsystem/temp down/LO HI mode R/not LO or HI' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleRR/If Action Subsystem/temp up/LO HI mode R' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleRR/If Action Subsystem/temp up/LO HI mode R/HI mode' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleRR/If Action Subsystem/temp up/LO HI mode R/LO mode' + * '' : 'HVAC_model/CAN INPUT/Subsystem53/tempToggleRR/If Action Subsystem/temp up/LO HI mode R/not LO or HI' + * '' : 'HVAC_model/CAN OUTPUT/Subsystem' + * '' : 'HVAC_model/CAN OUTPUT/Subsystem1' + * '' : 'HVAC_model/CAN OUTPUT/Subsystem2' + * '' : 'HVAC_model/CAN OUTPUT/Subsystem3' + * '' : 'HVAC_model/LIN/CHANEL0' + * '' : 'HVAC_model/LIN/CHANEL1' + * '' : 'HVAC_model/LIN/CHANEL2' + * '' : 'HVAC_model/LIN/CHANEL3' + * '' : 'HVAC_model/LIN/CHANEL4' + * '' : 'HVAC_model/LIN/Chart' + * '' : 'HVAC_model/LIN/CHANEL0/Actuator_Ch0_Command_Model' + * '' : 'HVAC_model/LIN/CHANEL0/COM = 0' + * '' : 'HVAC_model/LIN/CHANEL0/Check Stall Max' + * '' : 'HVAC_model/LIN/CHANEL0/Check Stall Min' + * '' : 'HVAC_model/LIN/CHANEL0/Homing' + * '' : 'HVAC_model/LIN/CHANEL0/Initial CPOS Max' + * '' : 'HVAC_model/LIN/CHANEL0/Initial CPOS Min' + * '' : 'HVAC_model/LIN/CHANEL0/Move to position Max' + * '' : 'HVAC_model/LIN/CHANEL0/Move to position Min' + * '' : 'HVAC_model/LIN/CHANEL0/Normal Mode' + * '' : 'HVAC_model/LIN/CHANEL0/Stop Mode' + * '' : 'HVAC_model/LIN/CHANEL0/steps to percents' + * '' : 'HVAC_model/LIN/CHANEL0/COM = 0/Compare To Constant' + * '' : 'HVAC_model/LIN/CHANEL0/Check Stall Max/If Action Subsystem2' + * '' : 'HVAC_model/LIN/CHANEL0/Check Stall Max/If Action Subsystem3' + * '' : 'HVAC_model/LIN/CHANEL0/Check Stall Max/If Action Subsystem2/Write' + * '' : 'HVAC_model/LIN/CHANEL0/Check Stall Min/If Action Subsystem2' + * '' : 'HVAC_model/LIN/CHANEL0/Check Stall Min/If Action Subsystem3' + * '' : 'HVAC_model/LIN/CHANEL0/Check Stall Min/If Action Subsystem2/Write' + * '' : 'HVAC_model/LIN/CHANEL0/Homing/Count step actuator' + * '' : 'HVAC_model/LIN/CHANEL0/Homing/Switch Case Action Subsystem' + * '' : 'HVAC_model/LIN/CHANEL0/Homing/Switch Case Action Subsystem1' + * '' : 'HVAC_model/LIN/CHANEL0/Homing/Switch Case Action Subsystem2' + * '' : 'HVAC_model/LIN/CHANEL0/Homing/Switch Case Action Subsystem3' + * '' : 'HVAC_model/LIN/CHANEL0/Homing/Switch Case Action Subsystem4' + * '' : 'HVAC_model/LIN/CHANEL0/Homing/Switch Case Action Subsystem/Compare To Constant' + * '' : 'HVAC_model/LIN/CHANEL0/Homing/Switch Case Action Subsystem/Compare To Constant1' + * '' : 'HVAC_model/LIN/CHANEL0/Homing/Switch Case Action Subsystem/MAX POSITION' + * '' : 'HVAC_model/LIN/CHANEL0/Homing/Switch Case Action Subsystem/Subsystem' + * '' : 'HVAC_model/LIN/CHANEL0/Homing/Switch Case Action Subsystem1/CAN ERROR' + * '' : 'HVAC_model/LIN/CHANEL0/Homing/Switch Case Action Subsystem1/Compare To Constant' + * '' : 'HVAC_model/LIN/CHANEL0/Homing/Switch Case Action Subsystem1/MAX POSITION' + * '' : 'HVAC_model/LIN/CHANEL0/Homing/Switch Case Action Subsystem1/Subsystem' + * '' : 'HVAC_model/LIN/CHANEL0/Homing/Switch Case Action Subsystem1/UDS ERROR' + * '' : 'HVAC_model/LIN/CHANEL0/Homing/Switch Case Action Subsystem1/CAN ERROR/Write ERROR' + * '' : 'HVAC_model/LIN/CHANEL0/Homing/Switch Case Action Subsystem2/Compare To Constant3' + * '' : 'HVAC_model/LIN/CHANEL0/Homing/Switch Case Action Subsystem2/Compare To Constant4' + * '' : 'HVAC_model/LIN/CHANEL0/Homing/Switch Case Action Subsystem2/MAX POSITION' + * '' : 'HVAC_model/LIN/CHANEL0/Homing/Switch Case Action Subsystem3/If Action Subsystem' + * '' : 'HVAC_model/LIN/CHANEL0/Homing/Switch Case Action Subsystem3/If Action Subsystem1' + * '' : 'HVAC_model/LIN/CHANEL0/Homing/Switch Case Action Subsystem3/MAX POSITION' + * '' : 'HVAC_model/LIN/CHANEL0/Homing/Switch Case Action Subsystem3/If Action Subsystem/If Action Subsystem' + * '' : 'HVAC_model/LIN/CHANEL0/Homing/Switch Case Action Subsystem3/If Action Subsystem/If Action Subsystem1' + * '' : 'HVAC_model/LIN/CHANEL0/Homing/Switch Case Action Subsystem3/If Action Subsystem/MATLAB Function' + * '' : 'HVAC_model/LIN/CHANEL0/Homing/Switch Case Action Subsystem3/If Action Subsystem/MAX POSITION' + * '' : 'HVAC_model/LIN/CHANEL0/Homing/Switch Case Action Subsystem3/If Action Subsystem/If Action Subsystem1/Send position' + * '' : 'HVAC_model/LIN/CHANEL0/Homing/Switch Case Action Subsystem3/If Action Subsystem/If Action Subsystem1/Send position/percents to steps' + * '' : 'HVAC_model/LIN/CHANEL0/Homing/Switch Case Action Subsystem3/If Action Subsystem1/CAN ERROR' + * '' : 'HVAC_model/LIN/CHANEL0/Homing/Switch Case Action Subsystem3/If Action Subsystem1/UDS ERROR' + * '' : 'HVAC_model/LIN/CHANEL0/Homing/Switch Case Action Subsystem3/If Action Subsystem1/CAN ERROR/Write ERROR' + * '' : 'HVAC_model/LIN/CHANEL0/Homing/Switch Case Action Subsystem4/Send position' + * '' : 'HVAC_model/LIN/CHANEL0/Homing/Switch Case Action Subsystem4/Send position/percents to steps' + * '' : 'HVAC_model/LIN/CHANEL0/Initial CPOS Max/If Action Subsystem2' + * '' : 'HVAC_model/LIN/CHANEL0/Initial CPOS Max/If Action Subsystem3' + * '' : 'HVAC_model/LIN/CHANEL0/Initial CPOS Max/If Action Subsystem2/Write' + * '' : 'HVAC_model/LIN/CHANEL0/Initial CPOS Min/If Action Subsystem' + * '' : 'HVAC_model/LIN/CHANEL0/Initial CPOS Min/If Action Subsystem3' + * '' : 'HVAC_model/LIN/CHANEL0/Initial CPOS Min/If Action Subsystem/Write' + * '' : 'HVAC_model/LIN/CHANEL0/Move to position Max/If Action Subsystem2' + * '' : 'HVAC_model/LIN/CHANEL0/Move to position Max/If Action Subsystem3' + * '' : 'HVAC_model/LIN/CHANEL0/Move to position Max/If Action Subsystem2/Write' + * '' : 'HVAC_model/LIN/CHANEL0/Move to position Min/If Action Subsystem2' + * '' : 'HVAC_model/LIN/CHANEL0/Move to position Min/If Action Subsystem3' + * '' : 'HVAC_model/LIN/CHANEL0/Move to position Min/If Action Subsystem2/Write' + * '' : 'HVAC_model/LIN/CHANEL0/Normal Mode/If Action Subsystem2' + * '' : 'HVAC_model/LIN/CHANEL0/Normal Mode/If Action Subsystem3' + * '' : 'HVAC_model/LIN/CHANEL0/Normal Mode/If Action Subsystem2/Write' + * '' : 'HVAC_model/LIN/CHANEL0/Stop Mode/If Action Subsystem2' + * '' : 'HVAC_model/LIN/CHANEL0/Stop Mode/If Action Subsystem3' + * '' : 'HVAC_model/LIN/CHANEL0/Stop Mode/If Action Subsystem2/Write' + * '' : 'HVAC_model/LIN/CHANEL1/Actuator_Ch1_Command_Model' + * '' : 'HVAC_model/LIN/CHANEL1/COM = 0' + * '' : 'HVAC_model/LIN/CHANEL1/Check Stall Max' + * '' : 'HVAC_model/LIN/CHANEL1/Check Stall Min' + * '' : 'HVAC_model/LIN/CHANEL1/Homing' + * '' : 'HVAC_model/LIN/CHANEL1/Initial CPOS Max' + * '' : 'HVAC_model/LIN/CHANEL1/Initial CPOS Min' + * '' : 'HVAC_model/LIN/CHANEL1/Move to position Max' + * '' : 'HVAC_model/LIN/CHANEL1/Move to position Min' + * '' : 'HVAC_model/LIN/CHANEL1/Normal Mode' + * '' : 'HVAC_model/LIN/CHANEL1/Stop Mode' + * '' : 'HVAC_model/LIN/CHANEL1/stepr to percents' + * '' : 'HVAC_model/LIN/CHANEL1/COM = 0/Compare To Constant' + * '' : 'HVAC_model/LIN/CHANEL1/Check Stall Max/If Action Subsystem2' + * '' : 'HVAC_model/LIN/CHANEL1/Check Stall Max/If Action Subsystem3' + * '' : 'HVAC_model/LIN/CHANEL1/Check Stall Max/If Action Subsystem2/Write' + * '' : 'HVAC_model/LIN/CHANEL1/Check Stall Min/If Action Subsystem2' + * '' : 'HVAC_model/LIN/CHANEL1/Check Stall Min/If Action Subsystem3' + * '' : 'HVAC_model/LIN/CHANEL1/Check Stall Min/If Action Subsystem2/Write' + * '' : 'HVAC_model/LIN/CHANEL1/Homing/Count step actuator' + * '' : 'HVAC_model/LIN/CHANEL1/Homing/Switch Case Action Subsystem' + * '' : 'HVAC_model/LIN/CHANEL1/Homing/Switch Case Action Subsystem1' + * '' : 'HVAC_model/LIN/CHANEL1/Homing/Switch Case Action Subsystem2' + * '' : 'HVAC_model/LIN/CHANEL1/Homing/Switch Case Action Subsystem3' + * '' : 'HVAC_model/LIN/CHANEL1/Homing/Switch Case Action Subsystem4' + * '' : 'HVAC_model/LIN/CHANEL1/Homing/Switch Case Action Subsystem/Compare To Constant' + * '' : 'HVAC_model/LIN/CHANEL1/Homing/Switch Case Action Subsystem/Compare To Constant1' + * '' : 'HVAC_model/LIN/CHANEL1/Homing/Switch Case Action Subsystem/MAX POSITION' + * '' : 'HVAC_model/LIN/CHANEL1/Homing/Switch Case Action Subsystem/Subsystem' + * '' : 'HVAC_model/LIN/CHANEL1/Homing/Switch Case Action Subsystem1/CAN ERROR' + * '' : 'HVAC_model/LIN/CHANEL1/Homing/Switch Case Action Subsystem1/Compare To Constant' + * '' : 'HVAC_model/LIN/CHANEL1/Homing/Switch Case Action Subsystem1/MAX POSITION' + * '' : 'HVAC_model/LIN/CHANEL1/Homing/Switch Case Action Subsystem1/Subsystem' + * '' : 'HVAC_model/LIN/CHANEL1/Homing/Switch Case Action Subsystem1/UDS ERROR' + * '' : 'HVAC_model/LIN/CHANEL1/Homing/Switch Case Action Subsystem1/CAN ERROR/Write ERROR' + * '' : 'HVAC_model/LIN/CHANEL1/Homing/Switch Case Action Subsystem2/Compare To Constant3' + * '' : 'HVAC_model/LIN/CHANEL1/Homing/Switch Case Action Subsystem2/Compare To Constant4' + * '' : 'HVAC_model/LIN/CHANEL1/Homing/Switch Case Action Subsystem2/MAX POSITION' + * '' : 'HVAC_model/LIN/CHANEL1/Homing/Switch Case Action Subsystem3/If Action Subsystem' + * '' : 'HVAC_model/LIN/CHANEL1/Homing/Switch Case Action Subsystem3/If Action Subsystem1' + * '' : 'HVAC_model/LIN/CHANEL1/Homing/Switch Case Action Subsystem3/MAX POSITION' + * '' : 'HVAC_model/LIN/CHANEL1/Homing/Switch Case Action Subsystem3/If Action Subsystem/If Action Subsystem' + * '' : 'HVAC_model/LIN/CHANEL1/Homing/Switch Case Action Subsystem3/If Action Subsystem/If Action Subsystem1' + * '' : 'HVAC_model/LIN/CHANEL1/Homing/Switch Case Action Subsystem3/If Action Subsystem/MATLAB Function' + * '' : 'HVAC_model/LIN/CHANEL1/Homing/Switch Case Action Subsystem3/If Action Subsystem/MAX POSITION' + * '' : 'HVAC_model/LIN/CHANEL1/Homing/Switch Case Action Subsystem3/If Action Subsystem/If Action Subsystem1/Send position' + * '' : 'HVAC_model/LIN/CHANEL1/Homing/Switch Case Action Subsystem3/If Action Subsystem/If Action Subsystem1/Send position/percents to steps' + * '' : 'HVAC_model/LIN/CHANEL1/Homing/Switch Case Action Subsystem3/If Action Subsystem1/CAN ERROR' + * '' : 'HVAC_model/LIN/CHANEL1/Homing/Switch Case Action Subsystem3/If Action Subsystem1/UDS ERROR' + * '' : 'HVAC_model/LIN/CHANEL1/Homing/Switch Case Action Subsystem3/If Action Subsystem1/CAN ERROR/Write ERROR' + * '' : 'HVAC_model/LIN/CHANEL1/Homing/Switch Case Action Subsystem4/MAX POSITION' + * '' : 'HVAC_model/LIN/CHANEL1/Homing/Switch Case Action Subsystem4/Send position' + * '' : 'HVAC_model/LIN/CHANEL1/Homing/Switch Case Action Subsystem4/Send position/percents to steps' + * '' : 'HVAC_model/LIN/CHANEL1/Initial CPOS Max/If Action Subsystem2' + * '' : 'HVAC_model/LIN/CHANEL1/Initial CPOS Max/If Action Subsystem3' + * '' : 'HVAC_model/LIN/CHANEL1/Initial CPOS Max/If Action Subsystem2/Write' + * '' : 'HVAC_model/LIN/CHANEL1/Initial CPOS Min/If Action Subsystem' + * '' : 'HVAC_model/LIN/CHANEL1/Initial CPOS Min/If Action Subsystem3' + * '' : 'HVAC_model/LIN/CHANEL1/Initial CPOS Min/If Action Subsystem/Write' + * '' : 'HVAC_model/LIN/CHANEL1/Move to position Max/If Action Subsystem2' + * '' : 'HVAC_model/LIN/CHANEL1/Move to position Max/If Action Subsystem3' + * '' : 'HVAC_model/LIN/CHANEL1/Move to position Max/If Action Subsystem2/Write' + * '' : 'HVAC_model/LIN/CHANEL1/Move to position Min/If Action Subsystem2' + * '' : 'HVAC_model/LIN/CHANEL1/Move to position Min/If Action Subsystem3' + * '' : 'HVAC_model/LIN/CHANEL1/Move to position Min/If Action Subsystem2/Write' + * '' : 'HVAC_model/LIN/CHANEL1/Normal Mode/If Action Subsystem2' + * '' : 'HVAC_model/LIN/CHANEL1/Normal Mode/If Action Subsystem3' + * '' : 'HVAC_model/LIN/CHANEL1/Normal Mode/If Action Subsystem2/Write' + * '' : 'HVAC_model/LIN/CHANEL1/Stop Mode/If Action Subsystem2' + * '' : 'HVAC_model/LIN/CHANEL1/Stop Mode/If Action Subsystem3' + * '' : 'HVAC_model/LIN/CHANEL1/Stop Mode/If Action Subsystem2/Write' + * '' : 'HVAC_model/LIN/CHANEL2/Actuator_Ch1_Command_Model' + * '' : 'HVAC_model/LIN/CHANEL2/COM = 0' + * '' : 'HVAC_model/LIN/CHANEL2/Check Stall Max' + * '' : 'HVAC_model/LIN/CHANEL2/Check Stall Min' + * '' : 'HVAC_model/LIN/CHANEL2/Homing' + * '' : 'HVAC_model/LIN/CHANEL2/Initial CPOS Max' + * '' : 'HVAC_model/LIN/CHANEL2/Initial CPOS Min' + * '' : 'HVAC_model/LIN/CHANEL2/Move to position Max' + * '' : 'HVAC_model/LIN/CHANEL2/Move to position Min' + * '' : 'HVAC_model/LIN/CHANEL2/Normal Mode' + * '' : 'HVAC_model/LIN/CHANEL2/Stop Mode' + * '' : 'HVAC_model/LIN/CHANEL2/stepr to percents' + * '' : 'HVAC_model/LIN/CHANEL2/COM = 0/Compare To Constant' + * '' : 'HVAC_model/LIN/CHANEL2/Check Stall Max/If Action Subsystem2' + * '' : 'HVAC_model/LIN/CHANEL2/Check Stall Max/If Action Subsystem3' + * '' : 'HVAC_model/LIN/CHANEL2/Check Stall Max/If Action Subsystem2/Write' + * '' : 'HVAC_model/LIN/CHANEL2/Check Stall Min/If Action Subsystem2' + * '' : 'HVAC_model/LIN/CHANEL2/Check Stall Min/If Action Subsystem3' + * '' : 'HVAC_model/LIN/CHANEL2/Check Stall Min/If Action Subsystem2/Write' + * '' : 'HVAC_model/LIN/CHANEL2/Homing/Count step actuator' + * '' : 'HVAC_model/LIN/CHANEL2/Homing/Switch Case Action Subsystem' + * '' : 'HVAC_model/LIN/CHANEL2/Homing/Switch Case Action Subsystem1' + * '' : 'HVAC_model/LIN/CHANEL2/Homing/Switch Case Action Subsystem2' + * '' : 'HVAC_model/LIN/CHANEL2/Homing/Switch Case Action Subsystem3' + * '' : 'HVAC_model/LIN/CHANEL2/Homing/Switch Case Action Subsystem4' + * '' : 'HVAC_model/LIN/CHANEL2/Homing/Switch Case Action Subsystem/Compare To Constant' + * '' : 'HVAC_model/LIN/CHANEL2/Homing/Switch Case Action Subsystem/Compare To Constant1' + * '' : 'HVAC_model/LIN/CHANEL2/Homing/Switch Case Action Subsystem/MAX POSITION' + * '' : 'HVAC_model/LIN/CHANEL2/Homing/Switch Case Action Subsystem/Subsystem' + * '' : 'HVAC_model/LIN/CHANEL2/Homing/Switch Case Action Subsystem1/CAN ERROR' + * '' : 'HVAC_model/LIN/CHANEL2/Homing/Switch Case Action Subsystem1/Compare To Constant' + * '' : 'HVAC_model/LIN/CHANEL2/Homing/Switch Case Action Subsystem1/MAX POSITION' + * '' : 'HVAC_model/LIN/CHANEL2/Homing/Switch Case Action Subsystem1/Subsystem' + * '' : 'HVAC_model/LIN/CHANEL2/Homing/Switch Case Action Subsystem1/UDS ERROR' + * '' : 'HVAC_model/LIN/CHANEL2/Homing/Switch Case Action Subsystem1/CAN ERROR/Write ERROR' + * '' : 'HVAC_model/LIN/CHANEL2/Homing/Switch Case Action Subsystem2/Compare To Constant3' + * '' : 'HVAC_model/LIN/CHANEL2/Homing/Switch Case Action Subsystem2/Compare To Constant4' + * '' : 'HVAC_model/LIN/CHANEL2/Homing/Switch Case Action Subsystem2/MAX POSITION' + * '' : 'HVAC_model/LIN/CHANEL2/Homing/Switch Case Action Subsystem3/If Action Subsystem' + * '' : 'HVAC_model/LIN/CHANEL2/Homing/Switch Case Action Subsystem3/If Action Subsystem1' + * '' : 'HVAC_model/LIN/CHANEL2/Homing/Switch Case Action Subsystem3/MAX POSITION' + * '' : 'HVAC_model/LIN/CHANEL2/Homing/Switch Case Action Subsystem3/If Action Subsystem/If Action Subsystem' + * '' : 'HVAC_model/LIN/CHANEL2/Homing/Switch Case Action Subsystem3/If Action Subsystem/If Action Subsystem1' + * '' : 'HVAC_model/LIN/CHANEL2/Homing/Switch Case Action Subsystem3/If Action Subsystem/MATLAB Function' + * '' : 'HVAC_model/LIN/CHANEL2/Homing/Switch Case Action Subsystem3/If Action Subsystem/MAX POSITION' + * '' : 'HVAC_model/LIN/CHANEL2/Homing/Switch Case Action Subsystem3/If Action Subsystem/If Action Subsystem1/Send position' + * '' : 'HVAC_model/LIN/CHANEL2/Homing/Switch Case Action Subsystem3/If Action Subsystem/If Action Subsystem1/Send position/percents to steps' + * '' : 'HVAC_model/LIN/CHANEL2/Homing/Switch Case Action Subsystem3/If Action Subsystem1/CAN ERROR' + * '' : 'HVAC_model/LIN/CHANEL2/Homing/Switch Case Action Subsystem3/If Action Subsystem1/UDS ERROR' + * '' : 'HVAC_model/LIN/CHANEL2/Homing/Switch Case Action Subsystem3/If Action Subsystem1/CAN ERROR/Write ERROR' + * '' : 'HVAC_model/LIN/CHANEL2/Homing/Switch Case Action Subsystem4/MAX POSITION' + * '' : 'HVAC_model/LIN/CHANEL2/Homing/Switch Case Action Subsystem4/Send position' + * '' : 'HVAC_model/LIN/CHANEL2/Homing/Switch Case Action Subsystem4/Send position/percents to steps' + * '' : 'HVAC_model/LIN/CHANEL2/Initial CPOS Max/If Action Subsystem2' + * '' : 'HVAC_model/LIN/CHANEL2/Initial CPOS Max/If Action Subsystem3' + * '' : 'HVAC_model/LIN/CHANEL2/Initial CPOS Max/If Action Subsystem2/Write' + * '' : 'HVAC_model/LIN/CHANEL2/Initial CPOS Min/If Action Subsystem' + * '' : 'HVAC_model/LIN/CHANEL2/Initial CPOS Min/If Action Subsystem3' + * '' : 'HVAC_model/LIN/CHANEL2/Initial CPOS Min/If Action Subsystem/Write' + * '' : 'HVAC_model/LIN/CHANEL2/Move to position Max/If Action Subsystem2' + * '' : 'HVAC_model/LIN/CHANEL2/Move to position Max/If Action Subsystem3' + * '' : 'HVAC_model/LIN/CHANEL2/Move to position Max/If Action Subsystem2/Write' + * '' : 'HVAC_model/LIN/CHANEL2/Move to position Min/If Action Subsystem2' + * '' : 'HVAC_model/LIN/CHANEL2/Move to position Min/If Action Subsystem3' + * '' : 'HVAC_model/LIN/CHANEL2/Move to position Min/If Action Subsystem2/Write' + * '' : 'HVAC_model/LIN/CHANEL2/Normal Mode/If Action Subsystem2' + * '' : 'HVAC_model/LIN/CHANEL2/Normal Mode/If Action Subsystem3' + * '' : 'HVAC_model/LIN/CHANEL2/Normal Mode/If Action Subsystem2/Write' + * '' : 'HVAC_model/LIN/CHANEL2/Stop Mode/If Action Subsystem2' + * '' : 'HVAC_model/LIN/CHANEL2/Stop Mode/If Action Subsystem3' + * '' : 'HVAC_model/LIN/CHANEL2/Stop Mode/If Action Subsystem2/Write' + * '' : 'HVAC_model/LIN/CHANEL4/Detect Rise Positive' + * '' : 'HVAC_model/LIN/CHANEL4/Detect Rise Positive1' + * '' : 'HVAC_model/LIN/CHANEL4/Detect Rise Positive2' + * '' : 'HVAC_model/LIN/CHANEL4/Detect Rise Positive3' + * '' : 'HVAC_model/LIN/CHANEL4/Detect Rise Positive4' + * '' : 'HVAC_model/LIN/CHANEL4/Detect Rise Positive5' + * '' : 'HVAC_model/LIN/CHANEL4/Detect Rise Positive6' + * '' : 'HVAC_model/LIN/CHANEL4/Detect Rise Positive7' + * '' : 'HVAC_model/LIN/CHANEL4/Subsystem' + * '' : 'HVAC_model/LIN/CHANEL4/Subsystem1' + * '' : 'HVAC_model/LIN/CHANEL4/Subsystem2' + * '' : 'HVAC_model/LIN/CHANEL4/Subsystem3' + * '' : 'HVAC_model/LIN/CHANEL4/Subsystem4' + * '' : 'HVAC_model/LIN/CHANEL4/Subsystem5' + * '' : 'HVAC_model/LIN/CHANEL4/Subsystem6' + * '' : 'HVAC_model/LIN/CHANEL4/Subsystem7' + * '' : 'HVAC_model/LIN/CHANEL4/Detect Rise Positive/Positive' + * '' : 'HVAC_model/LIN/CHANEL4/Detect Rise Positive1/Positive' + * '' : 'HVAC_model/LIN/CHANEL4/Detect Rise Positive2/Positive' + * '' : 'HVAC_model/LIN/CHANEL4/Detect Rise Positive3/Positive' + * '' : 'HVAC_model/LIN/CHANEL4/Detect Rise Positive4/Positive' + * '' : 'HVAC_model/LIN/CHANEL4/Detect Rise Positive5/Positive' + * '' : 'HVAC_model/LIN/CHANEL4/Detect Rise Positive6/Positive' + * '' : 'HVAC_model/LIN/CHANEL4/Detect Rise Positive7/Positive' + * '' : 'HVAC_model/PID Compressor/Compare To Constant1' + * '' : 'HVAC_model/PID Compressor/MATLAB Function' + * '' : 'HVAC_model/PID Compressor/MATLAB Function1' + * '' : 'HVAC_model/PID Compressor/Subsystem4' + * '' : 'HVAC_model/PID Compressor/Subsystem4/Compare To Zero1' + * '' : 'HVAC_model/PID Compressor/Subsystem4/Compare To Zero2' + * '' : 'HVAC_model/PID Compressor/Subsystem4/Compare To Zero3' + * '' : 'HVAC_model/PID Compressor/Subsystem4/Saturation Dynamic' + * '' : 'HVAC_model/PID Compressor/Subsystem4/Saturation Dynamic3' + * '' : 'HVAC_model/PID DUCT/LO_FLL' + * '' : 'HVAC_model/PID DUCT/LO_FLU' + * '' : 'HVAC_model/PID DUCT/LO_FRL' + * '' : 'HVAC_model/PID DUCT/LO_FRU' + * '' : 'HVAC_model/PID DUCT/LO_RL' + * '' : 'HVAC_model/PID DUCT/LO_RR' + * '' : 'HVAC_model/PID DUCT/Subsystem1' + * '' : 'HVAC_model/PID DUCT/Subsystem2' + * '' : 'HVAC_model/PID DUCT/Subsystem3' + * '' : 'HVAC_model/PID DUCT/Subsystem4' + * '' : 'HVAC_model/PID DUCT/Subsystem5' + * '' : 'HVAC_model/PID DUCT/Subsystem6' + * '' : 'HVAC_model/PID DUCT/Subsystem1/Compare To Zero1' + * '' : 'HVAC_model/PID DUCT/Subsystem1/Compare To Zero2' + * '' : 'HVAC_model/PID DUCT/Subsystem1/Compare To Zero3' + * '' : 'HVAC_model/PID DUCT/Subsystem1/Saturation Dynamic' + * '' : 'HVAC_model/PID DUCT/Subsystem2/Compare To Zero1' + * '' : 'HVAC_model/PID DUCT/Subsystem2/Compare To Zero2' + * '' : 'HVAC_model/PID DUCT/Subsystem2/Compare To Zero3' + * '' : 'HVAC_model/PID DUCT/Subsystem2/Saturation Dynamic' + * '' : 'HVAC_model/PID DUCT/Subsystem3/Compare To Zero1' + * '' : 'HVAC_model/PID DUCT/Subsystem3/Compare To Zero2' + * '' : 'HVAC_model/PID DUCT/Subsystem3/Compare To Zero3' + * '' : 'HVAC_model/PID DUCT/Subsystem3/Rate Limiter Dynamic' + * '' : 'HVAC_model/PID DUCT/Subsystem3/Saturation Dynamic' + * '' : 'HVAC_model/PID DUCT/Subsystem3/Rate Limiter Dynamic/Saturation Dynamic' + * '' : 'HVAC_model/PID DUCT/Subsystem4/Compare To Zero1' + * '' : 'HVAC_model/PID DUCT/Subsystem4/Compare To Zero2' + * '' : 'HVAC_model/PID DUCT/Subsystem4/Compare To Zero3' + * '' : 'HVAC_model/PID DUCT/Subsystem4/Saturation Dynamic' + * '' : 'HVAC_model/PID DUCT/Subsystem5/Compare To Zero1' + * '' : 'HVAC_model/PID DUCT/Subsystem5/Compare To Zero2' + * '' : 'HVAC_model/PID DUCT/Subsystem5/Compare To Zero3' + * '' : 'HVAC_model/PID DUCT/Subsystem5/Saturation Dynamic' + * '' : 'HVAC_model/PID DUCT/Subsystem6/Compare To Zero1' + * '' : 'HVAC_model/PID DUCT/Subsystem6/Compare To Zero2' + * '' : 'HVAC_model/PID DUCT/Subsystem6/Compare To Zero3' + * '' : 'HVAC_model/PID DUCT/Subsystem6/Saturation Dynamic' + * '' : 'HVAC_model/PWN/Write' + * '' : 'HVAC_model/PWN/Write1' + * '' : 'HVAC_model/PWN/Write2' + * '' : 'HVAC_model/PWN/Write3' + * '' : 'HVAC_model/Power/Compare To Zero' + * '' : 'HVAC_model/Power/Compare To Zero1' + * '' : 'HVAC_model/Power/Compare To Zero2' + * '' : 'HVAC_model/Power/Subsystem' + * '' : 'HVAC_model/Power/Subsystem2' + * '' : 'HVAC_model/Synchronization (SYNC)/all zone sync' + * '' : 'HVAC_model/Synchronization (SYNC)/front sync' + * '' : 'HVAC_model/Synchronization (SYNC)/rear sync' + * '' : 'HVAC_model/Valves auto or manual ()/DRS Valves FL' + * '' : 'HVAC_model/Valves auto or manual ()/DRS Valves FR' + * '' : 'HVAC_model/Valves auto or manual ()/DRS Valves RL' + * '' : 'HVAC_model/Valves auto or manual ()/DRS Valves RR' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FL' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FR' + * '' : 'HVAC_model/Valves auto or manual ()/Individual foot' + * '' : 'HVAC_model/Valves auto or manual ()/Individual foot1' + * '' : 'HVAC_model/Valves auto or manual ()/if start control FL' + * '' : 'HVAC_model/Valves auto or manual ()/if start control FR' + * '' : 'HVAC_model/Valves auto or manual ()/if start control RL' + * '' : 'HVAC_model/Valves auto or manual ()/if start control RR' + * '' : 'HVAC_model/Valves auto or manual ()/join left and right front' + * '' : 'HVAC_model/Valves auto or manual ()/join left and right rear' + * '' : 'HVAC_model/Valves auto or manual ()/valves in auto mode' + * '' : 'HVAC_model/Valves auto or manual ()/valves in manual mode ' + * '' : 'HVAC_model/Valves auto or manual ()/DRS Valves FL/FL valves * percent DRS' + * '' : 'HVAC_model/Valves auto or manual ()/DRS Valves FL/param index for mode' + * '' : 'HVAC_model/Valves auto or manual ()/DRS Valves FR/FR valves * percent DRS' + * '' : 'HVAC_model/Valves auto or manual ()/DRS Valves FR/param index for mode' + * '' : 'HVAC_model/Valves auto or manual ()/DRS Valves RL/RL valves * percent DRS' + * '' : 'HVAC_model/Valves auto or manual ()/DRS Valves RL/param index for mode' + * '' : 'HVAC_model/Valves auto or manual ()/DRS Valves RR/RR valves * percent DRS' + * '' : 'HVAC_model/Valves auto or manual ()/DRS Valves RR/param index for mode' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FL/HI logic manual' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FL/LO logic manual' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FL/HI logic manual/HI' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FL/HI logic manual/HI full 4 zones' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FL/HI logic manual/HI1' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FL/HI logic manual/HI/HI Both left and right' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FL/HI logic manual/HI/HI Left only' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FL/HI logic manual/HI/HI Right only' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FL/HI logic manual/HI/ HI' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FL/HI logic manual/HI1/HI Both left and right' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FL/HI logic manual/HI1/HI Left only' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FL/HI logic manual/HI1/HI Right only' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FL/HI logic manual/HI1/ HI' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FL/LO logic manual/LO' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FL/LO logic manual/LO1' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FL/LO logic manual/LO/LO Both left and right' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FL/LO logic manual/LO/LO Left only' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FL/LO logic manual/LO/LO Right only' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FL/LO logic manual/LO/ LO' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FL/LO logic manual/LO1/LO Both left and right' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FL/LO logic manual/LO1/LO Left only' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FL/LO logic manual/LO1/LO Right only' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FL/LO logic manual/LO1/ LO' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FR/HI logic manual' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FR/LO logic manual' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FR/HI logic manual/HI' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FR/HI logic manual/HI full 4 zones' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FR/HI logic manual/HI1' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FR/HI logic manual/HI/HI Both left and right' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FR/HI logic manual/HI/HI Left only' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FR/HI logic manual/HI/HI Right only' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FR/HI logic manual/HI/ HI' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FR/HI logic manual/HI1/HI Both left and right' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FR/HI logic manual/HI1/HI Left only' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FR/HI logic manual/HI1/HI Right only' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FR/HI logic manual/HI1/ HI' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FR/LO logic manual/LO' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FR/LO logic manual/LO1' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FR/LO logic manual/LO/LO Both left and right' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FR/LO logic manual/LO/LO Left only' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FR/LO logic manual/LO/LO Right only' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FR/LO logic manual/LO/ LO' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FR/LO logic manual/LO1/LO Both left and right' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FR/LO logic manual/LO1/LO Left only' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FR/LO logic manual/LO1/LO Right only' + * '' : 'HVAC_model/Valves auto or manual ()/HI-LO mode FR/LO logic manual/LO1/ LO' + * '' : 'HVAC_model/Valves auto or manual ()/if start control FL/Compare To Constant' + * '' : 'HVAC_model/Valves auto or manual ()/if start control FL/Compare To Constant1' + * '' : 'HVAC_model/Valves auto or manual ()/if start control FL/Compare To Constant2' + * '' : 'HVAC_model/Valves auto or manual ()/if start control FL/Compare To Constant3' + * '' : 'HVAC_model/Valves auto or manual ()/if start control FL/If Action Subsystem' + * '' : 'HVAC_model/Valves auto or manual ()/if start control FL/If Action Subsystem1' + * '' : 'HVAC_model/Valves auto or manual ()/if start control FL/If Action Subsystem/valves for mode' + * '' : 'HVAC_model/Valves auto or manual ()/if start control FR/Compare To Constant' + * '' : 'HVAC_model/Valves auto or manual ()/if start control FR/Compare To Constant1' + * '' : 'HVAC_model/Valves auto or manual ()/if start control FR/Compare To Constant2' + * '' : 'HVAC_model/Valves auto or manual ()/if start control FR/Compare To Constant3' + * '' : 'HVAC_model/Valves auto or manual ()/if start control FR/If Action Subsystem' + * '' : 'HVAC_model/Valves auto or manual ()/if start control FR/If Action Subsystem1' + * '' : 'HVAC_model/Valves auto or manual ()/if start control FR/If Action Subsystem/valves for mode' + * '' : 'HVAC_model/Valves auto or manual ()/if start control RL/Compare To Constant' + * '' : 'HVAC_model/Valves auto or manual ()/if start control RL/Compare To Constant1' + * '' : 'HVAC_model/Valves auto or manual ()/if start control RL/Compare To Constant2' + * '' : 'HVAC_model/Valves auto or manual ()/if start control RL/Compare To Constant3' + * '' : 'HVAC_model/Valves auto or manual ()/if start control RL/If Action Subsystem' + * '' : 'HVAC_model/Valves auto or manual ()/if start control RL/If Action Subsystem1' + * '' : 'HVAC_model/Valves auto or manual ()/if start control RL/If Action Subsystem/valves_rear_left' + * '' : 'HVAC_model/Valves auto or manual ()/if start control RR/Compare To Constant' + * '' : 'HVAC_model/Valves auto or manual ()/if start control RR/Compare To Constant1' + * '' : 'HVAC_model/Valves auto or manual ()/if start control RR/Compare To Constant2' + * '' : 'HVAC_model/Valves auto or manual ()/if start control RR/Compare To Constant3' + * '' : 'HVAC_model/Valves auto or manual ()/if start control RR/If Action Subsystem' + * '' : 'HVAC_model/Valves auto or manual ()/if start control RR/If Action Subsystem1' + * '' : 'HVAC_model/Valves auto or manual ()/if start control RR/If Action Subsystem/valves_rear_right' + * '' : 'HVAC_model/Valves auto or manual ()/valves in auto mode/front' + * '' : 'HVAC_model/Valves auto or manual ()/valves in auto mode/rear' + * '' : 'HVAC_model/Valves auto or manual ()/valves in auto mode/front/MODE_for_set_and_lvl' + * '' : 'HVAC_model/Valves auto or manual ()/valves in auto mode/front/MODE_for_set_and_lvl1' + * '' : 'HVAC_model/Valves auto or manual ()/valves in auto mode/front/valves_front_left' + * '' : 'HVAC_model/Valves auto or manual ()/valves in auto mode/front/valves_front_right' + * '' : 'HVAC_model/Valves auto or manual ()/valves in auto mode/rear/MODE_by_duct_tg_R_for_LVL' + * '' : 'HVAC_model/Valves auto or manual ()/valves in auto mode/rear/duct_tg RL' + * '' : 'HVAC_model/Valves auto or manual ()/valves in auto mode/rear/duct_tg RR' + * '' : 'HVAC_model/Valves auto or manual ()/valves in auto mode/rear/duct_tg RL' + * '' : 'HVAC_model/Valves auto or manual ()/valves in auto mode/rear/duct_tg RR' + * '' : 'HVAC_model/Valves auto or manual ()/valves in auto mode/rear/valves_rear_left' + * '' : 'HVAC_model/Valves auto or manual ()/valves in auto mode/rear/valves_rear_right' + * '' : 'HVAC_model/Valves auto or manual ()/valves in auto mode/rear/duct_tg RL/increase' + * '' : 'HVAC_model/Valves auto or manual ()/valves in auto mode/rear/duct_tg RR/increase' + * '' : 'HVAC_model/Valves auto or manual ()/valves in auto mode/rear/duct_tg RL/decrease' + * '' : 'HVAC_model/Valves auto or manual ()/valves in auto mode/rear/duct_tg RR/decrease' + * '' : 'HVAC_model/Valves auto or manual ()/valves in manual mode /Front zone valves' + * '' : 'HVAC_model/Valves auto or manual ()/valves in manual mode /Rear zone valves' + * '' : 'HVAC_model/Valves auto or manual ()/valves in manual mode /Front zone valves/Front Left Valves - manual directions' + * '' : 'HVAC_model/Valves auto or manual ()/valves in manual mode /Front zone valves/Front Right Valves - manual directions' + * '' : 'HVAC_model/Valves auto or manual ()/valves in manual mode /Front zone valves/Front Left Valves - manual directions/Valves for Bi Level' + * '' : 'HVAC_model/Valves auto or manual ()/valves in manual mode /Front zone valves/Front Left Valves - manual directions/Valves for Def' + * '' : 'HVAC_model/Valves auto or manual ()/valves in manual mode /Front zone valves/Front Left Valves - manual directions/Valves for Foot' + * '' : 'HVAC_model/Valves auto or manual ()/valves in manual mode /Front zone valves/Front Left Valves - manual directions/Valves for Foot + Def' + * '' : 'HVAC_model/Valves auto or manual ()/valves in manual mode /Front zone valves/Front Left Valves - manual directions/Valves for Hi_Level' + * '' : 'HVAC_model/Valves auto or manual ()/valves in manual mode /Front zone valves/Front Left Valves - manual directions/Valves for Tri-Level' + * '' : 'HVAC_model/Valves auto or manual ()/valves in manual mode /Front zone valves/Front Left Valves - manual directions/Valves for Vent mode' + * '' : 'HVAC_model/Valves auto or manual ()/valves in manual mode /Front zone valves/Front Right Valves - manual directions/Valves for Bi Level' + * '' : 'HVAC_model/Valves auto or manual ()/valves in manual mode /Front zone valves/Front Right Valves - manual directions/Valves for Def' + * '' : 'HVAC_model/Valves auto or manual ()/valves in manual mode /Front zone valves/Front Right Valves - manual directions/Valves for Foot' + * '' : 'HVAC_model/Valves auto or manual ()/valves in manual mode /Front zone valves/Front Right Valves - manual directions/Valves for Foot + Def' + * '' : 'HVAC_model/Valves auto or manual ()/valves in manual mode /Front zone valves/Front Right Valves - manual directions/Valves for Hi_Level' + * '' : 'HVAC_model/Valves auto or manual ()/valves in manual mode /Front zone valves/Front Right Valves - manual directions/Valves for Tri-Level' + * '' : 'HVAC_model/Valves auto or manual ()/valves in manual mode /Front zone valves/Front Right Valves - manual directions/Valves for Vent mode' + * '' : 'HVAC_model/Valves auto or manual ()/valves in manual mode /Rear zone valves/Rear valves left - manual directions' + * '' : 'HVAC_model/Valves auto or manual ()/valves in manual mode /Rear zone valves/Rear valves right - manual directions' + * '' : 'HVAC_model/Valves auto or manual ()/valves in manual mode /Rear zone valves/Rear valves left - manual directions/AF for Bi Level' + * '' : 'HVAC_model/Valves auto or manual ()/valves in manual mode /Rear zone valves/Rear valves left - manual directions/AF for Foot' + * '' : 'HVAC_model/Valves auto or manual ()/valves in manual mode /Rear zone valves/Rear valves left - manual directions/valves for Vent mode' + * '' : 'HVAC_model/Valves auto or manual ()/valves in manual mode /Rear zone valves/Rear valves right - manual directions/AF for Bi Level' + * '' : 'HVAC_model/Valves auto or manual ()/valves in manual mode /Rear zone valves/Rear valves right - manual directions/AF for Foot' + * '' : 'HVAC_model/Valves auto or manual ()/valves in manual mode /Rear zone valves/Rear valves right - manual directions/valves for Vent mode' + * '' : 'HVAC_model/dbg CAN/0 to dbg' + * '' : 'HVAC_model/dbg CAN/ACP (duct sensors) to dbg' + * '' : 'HVAC_model/dbg CAN/Auto_Valve_Plus to dbg' + * '' : 'HVAC_model/dbg CAN/CCU_IO to dbg' + * '' : 'HVAC_model/dbg CAN/DRS to dbg' + * '' : 'HVAC_model/dbg CAN/LIN_AirQS to dbg' + * '' : 'HVAC_model/dbg CAN/LIN_Aroma to dbg' + * '' : 'HVAC_model/dbg CAN/LIN_Ionizer to dbg' + * '' : 'HVAC_model/dbg CAN/Logic_Acl to dbg' + * '' : 'HVAC_model/dbg CAN/Logic_Rec to dbg' + * '' : 'HVAC_model/dbg CAN/Logic_State to dbg' + * '' : 'HVAC_model/dbg CAN/Logic_Valve to dbg' + * '' : 'HVAC_model/dbg CAN/actuators to dbg' + * '' : 'HVAC_model/dbg CAN/ambient to dbg' + * '' : 'HVAC_model/dbg CAN/autoAF dbg' + * '' : 'HVAC_model/dbg CAN/autoduct dbg' + * '' : 'HVAC_model/dbg CAN/blower to dbg' + * '' : 'HVAC_model/dbg CAN/sen_eva (evaporator) to dbg' + * '' : 'HVAC_model/dbg CAN/CCU_IO to dbg/Subsystem' + * '' : 'HVAC_model/dbg CAN/CCU_IO to dbg/Subsystem1' + * '' : 'HVAC_model/dbg CAN/CCU_IO to dbg/Subsystem2' + * '' : 'HVAC_model/dbg CAN/CCU_IO to dbg/Subsystem3' + */ +#endif /* HVAC_model_h_ */ + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/MODULES/HVAC_M7_MODEL/HVAC_model_data.c b/MODULES/HVAC_M7_MODEL/HVAC_model_data.c new file mode 100644 index 0000000..6b9f7d4 --- /dev/null +++ b/MODULES/HVAC_M7_MODEL/HVAC_model_data.c @@ -0,0 +1,1152 @@ +/* + * File: HVAC_model_data.c + * + * Code generated for Simulink model 'HVAC_model'. + * + * Model version : 1.1466 + * Simulink Coder version : 24.1 (R2024a) 19-Nov-2023 + * C/C++ source code generated on : Fri Jul 31 15:00:33 2026 + * + * Target selection: ert.tlc + * Embedded hardware selection: ARM Compatible->ARM Cortex-M + * Emulation hardware selection: + * Differs from embedded hardware (MATLAB Host) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#include "HVAC_model.h" + +/* Invariant block signals (default storage) */ +const ConstB rtConstB = { + /* Start of '/If Action Subsystem1' */ + { + { 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U }/* '/Data Type Conversion' */ + } + , + + /* End of '/If Action Subsystem1' */ + + /* Start of '/If Action Subsystem1' */ + { + { 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U }/* '/Data Type Conversion' */ + } + , + + /* End of '/If Action Subsystem1' */ + + /* Start of '/If Action Subsystem1' */ + { + { 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U }/* '/Data Type Conversion' */ + } + /* End of '/If Action Subsystem1' */ +}; + +/* Constant parameters (default storage) */ +const ConstP rtConstP = { + /* Expression: ADC_Data_Initial + * Referenced by: '/Data Store Memory42' + */ + { + 5U, + 15U, + 0U, + 0U, + 0U, + 0U, + 0U, + 0U, + 0U, + 0U, + 0U, + 0U, + 0U, + 0U, + 0U, + 0U, + 0U, + 0U, + 0U, + 0U, + 0U, + 0U, + 0U, + 0U, + 0U, + 0U, + 0U, + 0U, + 0U, + 0U, + 0U, + 0U, + 0U, + 0U, + 0U, + 0U, + 0U, + 0U, + 0U + }, + + /* Pooled Parameter (Expression: [850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 836 818 800 784 769 754 740 727 714 702 691 680 670 659 650 640 631 622 614 606 598 590 583 575 568 561 555 548 542 536 530 524 518 512 507 501 496 491 486 481 476 471 466 462 457 453 448 444 440 436 431 427 423 420 416 412 408 405 401 397 394 390 387 384 380 377 374 370 367 364 361 358 355 352 349 346 343 340 338 335 332 329 327 324 321 319 316 314 311 309 306 304 301 299 297 294 292 289 287 285 283 280 278 276 274 272 269 267 265 263 261 259 257 255 253 251 249 247 245 243 241 239 237 235 234 232 230 228 226 224 223 221 219 217 216 214 212 210 209 207 205 204 202 200 199 197 195 194 192 191 189 187 186 184 183 181 180 178 177 175 174 172 171 169 168 166 165 163 162 161 159 158 156 155 153 152 151 149 148 147 145 144 143 141 140 139 137 136 135 133 132 131 129 128 127 126 124 123 122 121 119 118 117 116 115 113 112 111 110 109 107 106 105 104 103 101 100 99 98 97 96 95 93 92 91 90 89 88 87 86 84 83 82 81 80 79 78 77 76 75 74 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 29 28 27 26 25 24 23 22 21 20 19 18 17 17 16 15 14 13 12 11 10 9 8 8 7 6 5 4 3 2 1 0 0 0 -1 -2 -3 -4 -5 -5 -6 -7 -8 -9 -10 -11 -11 -12 -13 -14 -15 -16 -17 -17 -18 -19 -20 -21 -22 -22 -23 -24 -25 -26 -27 -27 -28 -29 -30 -31 -31 -32 -33 -34 -35 -36 -36 -37 -38 -39 -40 -40 -41 -42 -43 -44 -44 -45 -46 -47 -47 -48 -49 -50 -51 -51 -52 -53 -54 -55 -55 -56 -57 -58 -58 -59 -60 -61 -62 -62 -63 -64 -65 -65 -66 -67 -68 -68 -69 -70 -71 -71 -72 -73 -74 -74 -75 -76 -77 -77 -78 -79 -80 -80 -81 -82 -83 -83 -84 -85 -86 -86 -87 -88 -89 -89 -90 -91 -92 -92 -93 -94 -95 -95 -96 -97 -97 -98 -99 -100 -100 -101 -102 -103 -103 -104 -105 -105 -106 -107 -108 -108 -109 -110 -111 -111 -112 -113 -113 -114 -115 -116 -116 -117 -118 -118 -119 -120 -121 -121 -122 -123 -123 -124 -125 -126 -126 -127 -128 -128 -129 -130 -131 -131 -132 -133 -133 -134 -135 -136 -136 -137 -138 -138 -139 -140 -140 -141 -142 -143 -143 -144 -145 -145 -146 -147 -148 -148 -149 -150 -150 -151 -152 -152 -153 -154 -155 -155 -156 -157 -157 -158 -159 -159 -160 -161 -162 -162 -163 -164 -164 -165 -166 -166 -167 -168 -169 -169 -170 -171 -171 -172 -173 -173 -174 -175 -176 -176 -177 -178 -178 -179 -180 -180 -181 -182 -183 -183 -184 -185 -185 -186 -187 -187 -188 -189 -189 -190 -191 -192 -192 -193 -194 -194 -195 -196 -196 -197 -198 -199 -199 -200 -201 -201 -202 -203 -204 -204 -205 -206 -206 -207 -208 -208 -209 -210 -211 -211 -212 -213 -213 -214 -215 -216 -216 -217 -218 -218 -219 -220 -221 -221 -222 -223 -223 -224 -225 -226 -226 -227 -228 -228 -229 -230 -231 -231 -232 -233 -233 -234 -235 -236 -236 -237 -238 -238 -239 -240 -241 -241 -242 -243 -244 -244 -245 -246 -246 -247 -248 -249 -249 -250 -251 -252 -252 -253 -254 -255 -255 -256 -257 -257 -258 -259 -260 -260 -261 -262 -263 -263 -264 -265 -266 -266 -267 -268 -269 -269 -270 -271 -272 -272 -273 -274 -275 -275 -276 -277 -278 -279 -279 -280 -281 -282 -282 -283 -284 -285 -285 -286 -287 -288 -289 -289 -290 -291 -292 -292 -293 -294 -295 -296 -296 -297 -298 -299 -300 -300 -301 -302 -303 -304 -304 -305 -306 -307 -308 -308 -309 -310 -311 -312 -313 -313 -314 -315 -316 -317 -318 -318 -319 -320 -321 -322 -323 -323 -324 -325 -326 -327 -328 -329 -329 -330 -331 -332 -333 -334 -335 -335 -336 -337 -338 -339 -340 -341 -342 -342 -343 -344 -345 -346 -347 -348 -349 -350 -351 -351 -352 -353 -354 -355 -356 -357 -358 -359 -360 -361 -362 -363 -364 -364 -365 -366 -367 -368 -369 -370 -371 -372 -373 -374 -375 -376 -377 -378 -379 -380 -381 -382 -383 -384 -385 -386 -387 -388 -389 -390 -391 -392 -393 -394 -395 -396 -398 -399 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 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387.84129637953095, + 388.25714698294246, 388.672997586354, 389.08884818976549, 389.504698793177, + 389.92054939658851, 390.3364 }, + + /* Pooled Parameter (Expression: Incar_Temp_Table) + * Referenced by: + * '/1-D Lookup Table2' + * '/1-D Lookup Table4' + * '/1-D Lookup Table1' + * '/1-D Lookup Table3' + */ + { 850.0, 850.0, 850.0, 850.0, 850.0, 850.0, 850.0, 850.0, 850.0, 850.0, 850.0, + 850.0, 850.0, 850.0, 850.0, 837.0, 816.0, 797.0, 780.0, 763.0, 748.0, 733.0, + 719.0, 706.0, 693.0, 681.0, 670.0, 659.0, 648.0, 638.0, 628.0, 619.0, 610.0, + 601.0, 593.0, 584.0, 577.0, 569.0, 562.0, 555.0, 548.0, 541.0, 534.0, 528.0, + 521.0, 515.0, 509.0, 503.0, 498.0, 492.0, 487.0, 481.0, 476.0, 471.0, 466.0, + 461.0, 457.0, 452.0, 447.0, 443.0, 438.0, 434.0, 430.0, 425.0, 421.0, 417.0, + 413.0, 409.0, 405.0, 401.0, 398.0, 394.0, 390.0, 387.0, 383.0, 380.0, 376.0, + 373.0, 370.0, 366.0, 363.0, 360.0, 357.0, 354.0, 351.0, 348.0, 345.0, 342.0, + 339.0, 336.0, 333.0, 330.0, 327.0, 324.0, 322.0, 319.0, 316.0, 314.0, 311.0, + 308.0, 306.0, 303.0, 301.0, 298.0, 296.0, 293.0, 291.0, 289.0, 286.0, 284.0, + 281.0, 279.0, 277.0, 275.0, 272.0, 270.0, 268.0, 266.0, 264.0, 262.0, 259.0, + 257.0, 255.0, 253.0, 251.0, 249.0, 247.0, 245.0, 243.0, 241.0, 239.0, 237.0, + 235.0, 233.0, 231.0, 229.0, 228.0, 226.0, 224.0, 222.0, 220.0, 218.0, 217.0, + 215.0, 213.0, 211.0, 210.0, 208.0, 206.0, 204.0, 203.0, 201.0, 199.0, 198.0, + 196.0, 194.0, 193.0, 191.0, 190.0, 188.0, 186.0, 185.0, 183.0, 182.0, 180.0, + 178.0, 177.0, 175.0, 174.0, 172.0, 171.0, 169.0, 168.0, 166.0, 165.0, 163.0, + 162.0, 161.0, 159.0, 158.0, 156.0, 155.0, 153.0, 152.0, 151.0, 149.0, 148.0, + 146.0, 145.0, 144.0, 142.0, 141.0, 140.0, 138.0, 137.0, 136.0, 134.0, 133.0, + 132.0, 130.0, 129.0, 128.0, 127.0, 125.0, 124.0, 123.0, 122.0, 120.0, 119.0, + 118.0, 117.0, 115.0, 114.0, 113.0, 112.0, 110.0, 109.0, 108.0, 107.0, 106.0, + 105.0, 103.0, 102.0, 101.0, 100.0, 99.0, 98.0, 96.0, 95.0, 94.0, 93.0, 92.0, + 91.0, 90.0, 88.0, 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-320.0, + -321.0, -322.0, -323.0, -323.0, -324.0, -325.0, -326.0, -327.0, -328.0, + -328.0, -329.0, -330.0, -331.0, -332.0, -333.0, -333.0, -334.0, -335.0, + -336.0, -337.0, -338.0, -339.0, -339.0, -340.0, -341.0, -342.0, -343.0, + -344.0, -345.0, -346.0, -346.0, -347.0, -348.0, -349.0, -350.0, -351.0, + -352.0, -353.0, -354.0, -355.0, -355.0, -356.0, -357.0, -358.0, -359.0, + -360.0, -361.0, -362.0, -363.0, -364.0, -365.0, -366.0, -367.0, -368.0, + -368.0, -369.0, -370.0, -371.0, -372.0, -373.0, -374.0, -375.0, -376.0, + -377.0, -378.0, -379.0, -380.0, -381.0, -382.0, -383.0, -384.0, -385.0, + -386.0, -387.0, -388.0, -389.0, -390.0, -391.0, -392.0, -393.0, -394.0, + -395.0, -396.0, -397.0, -398.0, -400.0, -400.0, -400.0, -400.0, -400.0, + -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, + -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, + -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, + -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, + -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, + -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, + -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, + -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, + -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, + -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, + -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, + -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, + -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, + -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, + -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, + -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, + -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, + -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, + -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0, -400.0 }, + + /* Pooled Parameter (Expression: [17 18 19 20 21 22 23 24 25 26 27 28 29]) + * Referenced by: + * '/ Left' + * '/ Right' + */ + { 5U, 12U }, + + /* Pooled Parameter (Expression: [170:10:290]) + * Referenced by: + * '/1-D Lookup Table' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table3' + * '/1-D Lookup Table4' + * '/1-D Lookup Table5' + * '/1-D Lookup Table' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table3' + * '/1-D Lookup Table4' + * '/1-D Lookup Table5' + * '/1-D Lookup Table' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table3' + * '/1-D Lookup Table4' + * '/1-D Lookup Table5' + * '/1-D Lookup Table' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table3' + * '/1-D Lookup Table4' + * '/1-D Lookup Table5' + * '/1-D Lookup Table' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table3' + * '/1-D Lookup Table4' + * '/1-D Lookup Table5' + * '/1-D Lookup Table' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table3' + * '/1-D Lookup Table4' + * '/1-D Lookup Table5' + * '/1-D Lookup Table' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table3' + * '/1-D Lookup Table4' + * '/1-D Lookup Table5' + * '/1-D Lookup Table' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table3' + * '/1-D Lookup Table4' + * '/1-D Lookup Table5' + * '/1-D Lookup Table' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table3' + * '/1-D Lookup Table4' + * '/1-D Lookup Table5' + * '/1-D Lookup Table' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table3' + * '/1-D Lookup Table4' + * '/1-D Lookup Table5' + * '/1-D Lookup Table' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table3' + * '/1-D Lookup Table4' + * '/1-D Lookup Table5' + * '/1-D Lookup Table' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table3' + * '/1-D Lookup Table4' + * '/1-D Lookup Table5' + */ + { 170, 180, 190, 200, 210, 220, 230, 240, 250, 260, 270, 280, 290 }, + + /* Pooled Parameter (Expression: [5, 4, 3, 2, 1, 0]) + * Referenced by: + * '/1-D Lookup Table' + * '/Get LVL for temp' + */ + { 5, 4, 3, 2, 1, 0 }, + + /* Computed Parameter: GetLVLfortemp_bp01Data + * Referenced by: '/Get LVL for temp' + */ + { -1000, -50, -10, 5, 20, 65 }, + + /* Pooled Parameter (Expression: [0;1;2;3;4;5]) + * Referenced by: + * '/ Left' + * '/ Right' + */ + { 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29 }, + + /* Pooled Parameter (Expression: [850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 850 848 845 841 838 834 831 827 824 821 818 814 811 808 805 802 799 796 793 790 787 784 781 778 775 772 769 767 764 761 758 756 753 750 748 745 742 740 737 735 732 730 727 725 722 720 717 715 713 710 708 706 703 701 699 696 694 692 690 688 685 683 681 679 677 675 673 670 668 666 664 662 660 658 656 654 652 650 648 646 644 642 640 638 637 635 633 631 629 627 625 624 622 620 618 616 614 613 611 609 607 606 604 602 600 599 597 595 594 592 590 589 587 585 584 582 580 579 577 576 574 572 571 569 568 566 564 563 561 560 558 557 555 554 552 551 549 548 546 545 543 542 540 539 537 536 534 533 532 530 529 527 526 524 523 522 520 519 517 516 515 513 512 511 509 508 507 505 504 503 501 500 499 497 496 495 493 492 491 489 488 487 485 484 483 482 480 479 478 477 475 474 473 472 470 469 468 467 465 464 463 462 460 459 458 457 456 454 453 452 451 450 448 447 446 445 444 442 441 440 439 438 437 435 434 433 432 431 430 429 427 426 425 424 423 422 421 420 418 417 416 415 414 413 412 411 410 408 407 406 405 404 403 402 401 400 399 398 396 395 394 393 392 391 390 389 388 387 386 385 384 383 382 381 380 378 377 376 375 374 373 372 371 370 369 368 367 366 365 364 363 362 361 360 359 358 357 356 355 354 353 352 351 350 349 348 347 346 345 344 343 342 341 340 339 338 337 336 335 334 333 332 331 330 329 328 327 326 325 324 324 323 322 321 320 319 318 317 316 315 314 313 312 311 310 309 308 307 306 305 305 304 303 302 301 300 299 298 297 296 295 294 293 292 291 291 290 289 288 287 286 285 284 283 282 281 280 279 279 278 277 276 275 274 273 272 271 270 269 268 268 267 266 265 264 263 262 261 260 259 259 258 257 256 255 254 253 252 251 250 250 249 248 247 246 245 244 243 242 241 241 240 239 238 237 236 235 234 233 233 232 231 230 229 228 227 226 225 224 224 223 222 221 220 219 218 217 217 216 215 214 213 212 211 210 209 209 208 207 206 205 204 203 202 201 201 200 199 198 197 196 195 194 194 193 192 191 190 189 188 187 186 186 185 184 183 182 181 180 179 179 178 177 176 175 174 173 172 171 171 170 169 168 167 166 165 164 163 163 162 161 160 159 158 157 156 155 155 154 153 152 151 150 149 148 147 147 146 145 144 143 142 141 140 139 139 138 137 136 135 134 133 132 131 130 130 129 128 127 126 125 124 123 122 121 121 120 119 118 117 116 115 114 113 112 112 111 110 109 108 107 106 105 104 103 102 101 101 100 99 98 97 96 95 94 93 92 91 90 89 88 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 3 2 1 0 0 -1 -2 -3 -4 -5 -6 -7 -9 -10 -11 -12 -13 -14 -15 -16 -17 -19 -20 -21 -22 -23 -24 -25 -26 -28 -29 -30 -31 -32 -33 -34 -36 -37 -38 -39 -40 -42 -43 -44 -45 -46 -47 -49 -50 -51 -52 -54 -55 -56 -57 -58 -60 -61 -62 -63 -65 -66 -67 -68 -70 -71 -72 -74 -75 -76 -77 -79 -80 -81 -83 -84 -85 -87 -88 -89 -91 -92 -93 -95 -96 -98 -99 -100 -102 -103 -105 -106 -108 -109 -110 -112 -113 -115 -116 -118 -119 -121 -122 -124 -125 -127 -128 -130 -131 -133 -134 -136 -138 -139 -141 -142 -144 -146 -147 -149 -151 -152 -154 -156 -157 -159 -161 -162 -164 -166 -168 -169 -171 -173 -175 -177 -179 -180 -182 -184 -186 -188 -190 -192 -194 -196 -198 -200 -202 -204 -206 -208 -210 -212 -214 -216 -218 -221 -223 -225 -227 -229 -232 -234 -236 -239 -241 -243 -246 -248 -251 -253 -256 -258 -261 -264 -266 -269 -272 -275 -277 -280 -283 -286 -289 -292 -295 -298 -301 -304 -308 -311 -314 -318 -321 -325 -328 -332 -336 -339 -343 -347 -351 -355 -359 -364 -368 -373 -377 -382 -387 -392 -397 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400 -400]) + * Referenced by: + * '/1-D Lookup Table7' + * '/1-D Lookup Table4' + */ + { 850, 850, 850, 850, 850, 850, 850, 850, 850, 850, 850, 850, 850, 850, 850, + 850, 850, 850, 850, 850, 850, 850, 850, 850, 850, 850, 850, 850, 850, 850, + 850, 850, 850, 850, 850, 850, 850, 850, 850, 850, 850, 850, 850, 850, 850, + 850, 850, 850, 850, 850, 850, 850, 850, 850, 850, 850, 850, 850, 850, 850, + 850, 850, 850, 850, 850, 850, 850, 850, 850, 850, 850, 850, 850, 850, 850, + 850, 850, 850, 850, 850, 850, 850, 850, 850, 850, 850, 850, 850, 850, 850, + 850, 850, 850, 850, 850, 850, 850, 850, 850, 848, 845, 841, 838, 834, 831, + 827, 824, 821, 818, 814, 811, 808, 805, 802, 799, 796, 793, 790, 787, 784, + 781, 778, 775, 772, 769, 767, 764, 761, 758, 756, 753, 750, 748, 745, 742, + 740, 737, 735, 732, 730, 727, 725, 722, 720, 717, 715, 713, 710, 708, 706, + 703, 701, 699, 696, 694, 692, 690, 688, 685, 683, 681, 679, 677, 675, 673, + 670, 668, 666, 664, 662, 660, 658, 656, 654, 652, 650, 648, 646, 644, 642, + 640, 638, 637, 635, 633, 631, 629, 627, 625, 624, 622, 620, 618, 616, 614, + 613, 611, 609, 607, 606, 604, 602, 600, 599, 597, 595, 594, 592, 590, 589, + 587, 585, 584, 582, 580, 579, 577, 576, 574, 572, 571, 569, 568, 566, 564, + 563, 561, 560, 558, 557, 555, 554, 552, 551, 549, 548, 546, 545, 543, 542, + 540, 539, 537, 536, 534, 533, 532, 530, 529, 527, 526, 524, 523, 522, 520, + 519, 517, 516, 515, 513, 512, 511, 509, 508, 507, 505, 504, 503, 501, 500, + 499, 497, 496, 495, 493, 492, 491, 489, 488, 487, 485, 484, 483, 482, 480, + 479, 478, 477, 475, 474, 473, 472, 470, 469, 468, 467, 465, 464, 463, 462, + 460, 459, 458, 457, 456, 454, 453, 452, 451, 450, 448, 447, 446, 445, 444, + 442, 441, 440, 439, 438, 437, 435, 434, 433, 432, 431, 430, 429, 427, 426, + 425, 424, 423, 422, 421, 420, 418, 417, 416, 415, 414, 413, 412, 411, 410, + 408, 407, 406, 405, 404, 403, 402, 401, 400, 399, 398, 396, 395, 394, 393, + 392, 391, 390, 389, 388, 387, 386, 385, 384, 383, 382, 381, 380, 378, 377, + 376, 375, 374, 373, 372, 371, 370, 369, 368, 367, 366, 365, 364, 363, 362, + 361, 360, 359, 358, 357, 356, 355, 354, 353, 352, 351, 350, 349, 348, 347, + 346, 345, 344, 343, 342, 341, 340, 339, 338, 337, 336, 335, 334, 333, 332, + 331, 330, 329, 328, 327, 326, 325, 324, 324, 323, 322, 321, 320, 319, 318, + 317, 316, 315, 314, 313, 312, 311, 310, 309, 308, 307, 306, 305, 305, 304, + 303, 302, 301, 300, 299, 298, 297, 296, 295, 294, 293, 292, 291, 291, 290, + 289, 288, 287, 286, 285, 284, 283, 282, 281, 280, 279, 279, 278, 277, 276, + 275, 274, 273, 272, 271, 270, 269, 268, 268, 267, 266, 265, 264, 263, 262, + 261, 260, 259, 259, 258, 257, 256, 255, 254, 253, 252, 251, 250, 250, 249, + 248, 247, 246, 245, 244, 243, 242, 241, 241, 240, 239, 238, 237, 236, 235, + 234, 233, 233, 232, 231, 230, 229, 228, 227, 226, 225, 224, 224, 223, 222, + 221, 220, 219, 218, 217, 217, 216, 215, 214, 213, 212, 211, 210, 209, 209, + 208, 207, 206, 205, 204, 203, 202, 201, 201, 200, 199, 198, 197, 196, 195, + 194, 194, 193, 192, 191, 190, 189, 188, 187, 186, 186, 185, 184, 183, 182, + 181, 180, 179, 179, 178, 177, 176, 175, 174, 173, 172, 171, 171, 170, 169, + 168, 167, 166, 165, 164, 163, 163, 162, 161, 160, 159, 158, 157, 156, 155, + 155, 154, 153, 152, 151, 150, 149, 148, 147, 147, 146, 145, 144, 143, 142, + 141, 140, 139, 139, 138, 137, 136, 135, 134, 133, 132, 131, 130, 130, 129, + 128, 127, 126, 125, 124, 123, 122, 121, 121, 120, 119, 118, 117, 116, 115, + 114, 113, 112, 112, 111, 110, 109, 108, 107, 106, 105, 104, 103, 102, 101, + 101, 100, 99, 98, 97, 96, 95, 94, 93, 92, 91, 90, 89, 88, 88, 87, 86, 85, 84, + 83, 82, 81, 80, 79, 78, 77, 76, 75, 74, 73, 72, 72, 71, 70, 69, 68, 67, 66, + 65, 64, 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, 50, 49, 48, 47, + 46, 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 33, 32, 31, 30, 29, 28, + 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, + 7, 6, 5, 3, 2, 1, 0, 0, -1, -2, -3, -4, -5, -6, -7, -9, -10, -11, -12, -13, + -14, -15, -16, -17, -19, -20, -21, -22, -23, -24, -25, -26, -28, -29, -30, + -31, -32, -33, -34, -36, -37, -38, -39, -40, -42, -43, -44, -45, -46, -47, + -49, -50, -51, -52, -54, -55, -56, -57, -58, -60, -61, -62, -63, -65, -66, + -67, -68, -70, -71, -72, -74, -75, -76, -77, -79, -80, -81, -83, -84, -85, + -87, -88, -89, -91, -92, -93, -95, -96, -98, -99, -100, -102, -103, -105, + -106, -108, -109, -110, -112, -113, -115, -116, -118, -119, -121, -122, -124, + -125, -127, -128, -130, -131, -133, -134, -136, -138, -139, -141, -142, -144, + -146, -147, -149, -151, -152, -154, -156, -157, -159, -161, -162, -164, -166, + -168, -169, -171, -173, -175, -177, -179, -180, -182, -184, -186, -188, -190, + -192, -194, -196, -198, -200, -202, -204, -206, -208, -210, -212, -214, -216, + -218, -221, -223, -225, -227, -229, -232, -234, -236, -239, -241, -243, -246, + -248, -251, -253, -256, -258, -261, -264, -266, -269, -272, -275, -277, -280, + -283, -286, -289, -292, -295, -298, -301, -304, -308, -311, -314, -318, -321, + -325, -328, -332, -336, -339, -343, -347, -351, -355, -359, -364, -368, -373, + -377, -382, -387, -392, -397, -400, -400, -400, -400, -400, -400, -400, -400, + -400, -400, -400, -400, -400, -400, -400, -400, -400, -400, -400, -400, -400, + -400, -400, -400, -400, -400, -400, -400, -400, -400, -400, -400, -400, -400, + -400, -400, -400 }, + + /* Pooled Parameter (Expression: [0:4:4095]) + * Referenced by: + * '/1-D Lookup Table7' + * '/1-D Lookup Table4' + */ + { 0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, + 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, + 144, 148, 152, 156, 160, 164, 168, 172, 176, 180, 184, 188, 192, 196, 200, + 204, 208, 212, 216, 220, 224, 228, 232, 236, 240, 244, 248, 252, 256, 260, + 264, 268, 272, 276, 280, 284, 288, 292, 296, 300, 304, 308, 312, 316, 320, + 324, 328, 332, 336, 340, 344, 348, 352, 356, 360, 364, 368, 372, 376, 380, + 384, 388, 392, 396, 400, 404, 408, 412, 416, 420, 424, 428, 432, 436, 440, + 444, 448, 452, 456, 460, 464, 468, 472, 476, 480, 484, 488, 492, 496, 500, + 504, 508, 512, 516, 520, 524, 528, 532, 536, 540, 544, 548, 552, 556, 560, + 564, 568, 572, 576, 580, 584, 588, 592, 596, 600, 604, 608, 612, 616, 620, + 624, 628, 632, 636, 640, 644, 648, 652, 656, 660, 664, 668, 672, 676, 680, + 684, 688, 692, 696, 700, 704, 708, 712, 716, 720, 724, 728, 732, 736, 740, + 744, 748, 752, 756, 760, 764, 768, 772, 776, 780, 784, 788, 792, 796, 800, + 804, 808, 812, 816, 820, 824, 828, 832, 836, 840, 844, 848, 852, 856, 860, + 864, 868, 872, 876, 880, 884, 888, 892, 896, 900, 904, 908, 912, 916, 920, + 924, 928, 932, 936, 940, 944, 948, 952, 956, 960, 964, 968, 972, 976, 980, + 984, 988, 992, 996, 1000, 1004, 1008, 1012, 1016, 1020, 1024, 1028, 1032, + 1036, 1040, 1044, 1048, 1052, 1056, 1060, 1064, 1068, 1072, 1076, 1080, 1084, + 1088, 1092, 1096, 1100, 1104, 1108, 1112, 1116, 1120, 1124, 1128, 1132, 1136, + 1140, 1144, 1148, 1152, 1156, 1160, 1164, 1168, 1172, 1176, 1180, 1184, 1188, + 1192, 1196, 1200, 1204, 1208, 1212, 1216, 1220, 1224, 1228, 1232, 1236, 1240, + 1244, 1248, 1252, 1256, 1260, 1264, 1268, 1272, 1276, 1280, 1284, 1288, 1292, + 1296, 1300, 1304, 1308, 1312, 1316, 1320, 1324, 1328, 1332, 1336, 1340, 1344, + 1348, 1352, 1356, 1360, 1364, 1368, 1372, 1376, 1380, 1384, 1388, 1392, 1396, + 1400, 1404, 1408, 1412, 1416, 1420, 1424, 1428, 1432, 1436, 1440, 1444, 1448, + 1452, 1456, 1460, 1464, 1468, 1472, 1476, 1480, 1484, 1488, 1492, 1496, 1500, + 1504, 1508, 1512, 1516, 1520, 1524, 1528, 1532, 1536, 1540, 1544, 1548, 1552, + 1556, 1560, 1564, 1568, 1572, 1576, 1580, 1584, 1588, 1592, 1596, 1600, 1604, + 1608, 1612, 1616, 1620, 1624, 1628, 1632, 1636, 1640, 1644, 1648, 1652, 1656, + 1660, 1664, 1668, 1672, 1676, 1680, 1684, 1688, 1692, 1696, 1700, 1704, 1708, + 1712, 1716, 1720, 1724, 1728, 1732, 1736, 1740, 1744, 1748, 1752, 1756, 1760, + 1764, 1768, 1772, 1776, 1780, 1784, 1788, 1792, 1796, 1800, 1804, 1808, 1812, + 1816, 1820, 1824, 1828, 1832, 1836, 1840, 1844, 1848, 1852, 1856, 1860, 1864, + 1868, 1872, 1876, 1880, 1884, 1888, 1892, 1896, 1900, 1904, 1908, 1912, 1916, + 1920, 1924, 1928, 1932, 1936, 1940, 1944, 1948, 1952, 1956, 1960, 1964, 1968, + 1972, 1976, 1980, 1984, 1988, 1992, 1996, 2000, 2004, 2008, 2012, 2016, 2020, + 2024, 2028, 2032, 2036, 2040, 2044, 2048, 2052, 2056, 2060, 2064, 2068, 2072, + 2076, 2080, 2084, 2088, 2092, 2096, 2100, 2104, 2108, 2112, 2116, 2120, 2124, + 2128, 2132, 2136, 2140, 2144, 2148, 2152, 2156, 2160, 2164, 2168, 2172, 2176, + 2180, 2184, 2188, 2192, 2196, 2200, 2204, 2208, 2212, 2216, 2220, 2224, 2228, + 2232, 2236, 2240, 2244, 2248, 2252, 2256, 2260, 2264, 2268, 2272, 2276, 2280, + 2284, 2288, 2292, 2296, 2300, 2304, 2308, 2312, 2316, 2320, 2324, 2328, 2332, + 2336, 2340, 2344, 2348, 2352, 2356, 2360, 2364, 2368, 2372, 2376, 2380, 2384, + 2388, 2392, 2396, 2400, 2404, 2408, 2412, 2416, 2420, 2424, 2428, 2432, 2436, + 2440, 2444, 2448, 2452, 2456, 2460, 2464, 2468, 2472, 2476, 2480, 2484, 2488, + 2492, 2496, 2500, 2504, 2508, 2512, 2516, 2520, 2524, 2528, 2532, 2536, 2540, + 2544, 2548, 2552, 2556, 2560, 2564, 2568, 2572, 2576, 2580, 2584, 2588, 2592, + 2596, 2600, 2604, 2608, 2612, 2616, 2620, 2624, 2628, 2632, 2636, 2640, 2644, + 2648, 2652, 2656, 2660, 2664, 2668, 2672, 2676, 2680, 2684, 2688, 2692, 2696, + 2700, 2704, 2708, 2712, 2716, 2720, 2724, 2728, 2732, 2736, 2740, 2744, 2748, + 2752, 2756, 2760, 2764, 2768, 2772, 2776, 2780, 2784, 2788, 2792, 2796, 2800, + 2804, 2808, 2812, 2816, 2820, 2824, 2828, 2832, 2836, 2840, 2844, 2848, 2852, + 2856, 2860, 2864, 2868, 2872, 2876, 2880, 2884, 2888, 2892, 2896, 2900, 2904, + 2908, 2912, 2916, 2920, 2924, 2928, 2932, 2936, 2940, 2944, 2948, 2952, 2956, + 2960, 2964, 2968, 2972, 2976, 2980, 2984, 2988, 2992, 2996, 3000, 3004, 3008, + 3012, 3016, 3020, 3024, 3028, 3032, 3036, 3040, 3044, 3048, 3052, 3056, 3060, + 3064, 3068, 3072, 3076, 3080, 3084, 3088, 3092, 3096, 3100, 3104, 3108, 3112, + 3116, 3120, 3124, 3128, 3132, 3136, 3140, 3144, 3148, 3152, 3156, 3160, 3164, + 3168, 3172, 3176, 3180, 3184, 3188, 3192, 3196, 3200, 3204, 3208, 3212, 3216, + 3220, 3224, 3228, 3232, 3236, 3240, 3244, 3248, 3252, 3256, 3260, 3264, 3268, + 3272, 3276, 3280, 3284, 3288, 3292, 3296, 3300, 3304, 3308, 3312, 3316, 3320, + 3324, 3328, 3332, 3336, 3340, 3344, 3348, 3352, 3356, 3360, 3364, 3368, 3372, + 3376, 3380, 3384, 3388, 3392, 3396, 3400, 3404, 3408, 3412, 3416, 3420, 3424, + 3428, 3432, 3436, 3440, 3444, 3448, 3452, 3456, 3460, 3464, 3468, 3472, 3476, + 3480, 3484, 3488, 3492, 3496, 3500, 3504, 3508, 3512, 3516, 3520, 3524, 3528, + 3532, 3536, 3540, 3544, 3548, 3552, 3556, 3560, 3564, 3568, 3572, 3576, 3580, + 3584, 3588, 3592, 3596, 3600, 3604, 3608, 3612, 3616, 3620, 3624, 3628, 3632, + 3636, 3640, 3644, 3648, 3652, 3656, 3660, 3664, 3668, 3672, 3676, 3680, 3684, + 3688, 3692, 3696, 3700, 3704, 3708, 3712, 3716, 3720, 3724, 3728, 3732, 3736, + 3740, 3744, 3748, 3752, 3756, 3760, 3764, 3768, 3772, 3776, 3780, 3784, 3788, + 3792, 3796, 3800, 3804, 3808, 3812, 3816, 3820, 3824, 3828, 3832, 3836, 3840, + 3844, 3848, 3852, 3856, 3860, 3864, 3868, 3872, 3876, 3880, 3884, 3888, 3892, + 3896, 3900, 3904, 3908, 3912, 3916, 3920, 3924, 3928, 3932, 3936, 3940, 3944, + 3948, 3952, 3956, 3960, 3964, 3968, 3972, 3976, 3980, 3984, 3988, 3992, 3996, + 4000, 4004, 4008, 4012, 4016, 4020, 4024, 4028, 4032, 4036, 4040, 4044, 4048, + 4052, 4056, 4060, 4064, 4068, 4072, 4076, 4080, 4084, 4088, 4092 }, + + /* Pooled Parameter (Expression: [170:10:290]) + * Referenced by: + * '/1-D Lookup Table' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table3' + * '/1-D Lookup Table4' + * '/1-D Lookup Table5' + * '/1-D Lookup Table' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table3' + * '/1-D Lookup Table4' + * '/1-D Lookup Table5' + * '/1-D Lookup Table' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table3' + * '/1-D Lookup Table4' + * '/1-D Lookup Table5' + * '/1-D Lookup Table' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table3' + * '/1-D Lookup Table4' + * '/1-D Lookup Table5' + * '/1-D Lookup Table10' + * '/1-D Lookup Table11' + * '/1-D Lookup Table6' + * '/1-D Lookup Table7' + * '/1-D Lookup Table8' + * '/1-D Lookup Table9' + * '/1-D Lookup Table10' + * '/1-D Lookup Table11' + * '/1-D Lookup Table6' + * '/1-D Lookup Table7' + * '/1-D Lookup Table8' + * '/1-D Lookup Table9' + * '/1-D Lookup Table10' + * '/1-D Lookup Table11' + * '/1-D Lookup Table6' + * '/1-D Lookup Table7' + * '/1-D Lookup Table8' + * '/1-D Lookup Table9' + * '/1-D Lookup Table1' + * '/1-D Lookup Table12' + * '/1-D Lookup Table2' + * '/1-D Lookup Table3' + * '/1-D Lookup Table4' + * '/1-D Lookup Table5' + */ + { 170U, 180U, 190U, 200U, 210U, 220U, 230U, 240U, 250U, 260U, 270U, 280U, 290U + }, + + /* Pooled Parameter (Expression: [0:4:4092]) + * Referenced by: + * '/1-D Lookup Table' + * '/1-D Lookup Table' + * '/1-D Lookup Table' + * '/1-D Lookup Table2' + * '/1-D Lookup Table4' + * '/1-D Lookup Table1' + * '/1-D Lookup Table3' + */ + { 0U, 4U, 8U, 12U, 16U, 20U, 24U, 28U, 32U, 36U, 40U, 44U, 48U, 52U, 56U, 60U, + 64U, 68U, 72U, 76U, 80U, 84U, 88U, 92U, 96U, 100U, 104U, 108U, 112U, 116U, + 120U, 124U, 128U, 132U, 136U, 140U, 144U, 148U, 152U, 156U, 160U, 164U, 168U, + 172U, 176U, 180U, 184U, 188U, 192U, 196U, 200U, 204U, 208U, 212U, 216U, 220U, + 224U, 228U, 232U, 236U, 240U, 244U, 248U, 252U, 256U, 260U, 264U, 268U, 272U, + 276U, 280U, 284U, 288U, 292U, 296U, 300U, 304U, 308U, 312U, 316U, 320U, 324U, + 328U, 332U, 336U, 340U, 344U, 348U, 352U, 356U, 360U, 364U, 368U, 372U, 376U, + 380U, 384U, 388U, 392U, 396U, 400U, 404U, 408U, 412U, 416U, 420U, 424U, 428U, + 432U, 436U, 440U, 444U, 448U, 452U, 456U, 460U, 464U, 468U, 472U, 476U, 480U, + 484U, 488U, 492U, 496U, 500U, 504U, 508U, 512U, 516U, 520U, 524U, 528U, 532U, + 536U, 540U, 544U, 548U, 552U, 556U, 560U, 564U, 568U, 572U, 576U, 580U, 584U, + 588U, 592U, 596U, 600U, 604U, 608U, 612U, 616U, 620U, 624U, 628U, 632U, 636U, + 640U, 644U, 648U, 652U, 656U, 660U, 664U, 668U, 672U, 676U, 680U, 684U, 688U, + 692U, 696U, 700U, 704U, 708U, 712U, 716U, 720U, 724U, 728U, 732U, 736U, 740U, + 744U, 748U, 752U, 756U, 760U, 764U, 768U, 772U, 776U, 780U, 784U, 788U, 792U, + 796U, 800U, 804U, 808U, 812U, 816U, 820U, 824U, 828U, 832U, 836U, 840U, 844U, + 848U, 852U, 856U, 860U, 864U, 868U, 872U, 876U, 880U, 884U, 888U, 892U, 896U, + 900U, 904U, 908U, 912U, 916U, 920U, 924U, 928U, 932U, 936U, 940U, 944U, 948U, + 952U, 956U, 960U, 964U, 968U, 972U, 976U, 980U, 984U, 988U, 992U, 996U, + 1000U, 1004U, 1008U, 1012U, 1016U, 1020U, 1024U, 1028U, 1032U, 1036U, 1040U, + 1044U, 1048U, 1052U, 1056U, 1060U, 1064U, 1068U, 1072U, 1076U, 1080U, 1084U, + 1088U, 1092U, 1096U, 1100U, 1104U, 1108U, 1112U, 1116U, 1120U, 1124U, 1128U, + 1132U, 1136U, 1140U, 1144U, 1148U, 1152U, 1156U, 1160U, 1164U, 1168U, 1172U, + 1176U, 1180U, 1184U, 1188U, 1192U, 1196U, 1200U, 1204U, 1208U, 1212U, 1216U, + 1220U, 1224U, 1228U, 1232U, 1236U, 1240U, 1244U, 1248U, 1252U, 1256U, 1260U, + 1264U, 1268U, 1272U, 1276U, 1280U, 1284U, 1288U, 1292U, 1296U, 1300U, 1304U, + 1308U, 1312U, 1316U, 1320U, 1324U, 1328U, 1332U, 1336U, 1340U, 1344U, 1348U, + 1352U, 1356U, 1360U, 1364U, 1368U, 1372U, 1376U, 1380U, 1384U, 1388U, 1392U, + 1396U, 1400U, 1404U, 1408U, 1412U, 1416U, 1420U, 1424U, 1428U, 1432U, 1436U, + 1440U, 1444U, 1448U, 1452U, 1456U, 1460U, 1464U, 1468U, 1472U, 1476U, 1480U, + 1484U, 1488U, 1492U, 1496U, 1500U, 1504U, 1508U, 1512U, 1516U, 1520U, 1524U, + 1528U, 1532U, 1536U, 1540U, 1544U, 1548U, 1552U, 1556U, 1560U, 1564U, 1568U, + 1572U, 1576U, 1580U, 1584U, 1588U, 1592U, 1596U, 1600U, 1604U, 1608U, 1612U, + 1616U, 1620U, 1624U, 1628U, 1632U, 1636U, 1640U, 1644U, 1648U, 1652U, 1656U, + 1660U, 1664U, 1668U, 1672U, 1676U, 1680U, 1684U, 1688U, 1692U, 1696U, 1700U, + 1704U, 1708U, 1712U, 1716U, 1720U, 1724U, 1728U, 1732U, 1736U, 1740U, 1744U, + 1748U, 1752U, 1756U, 1760U, 1764U, 1768U, 1772U, 1776U, 1780U, 1784U, 1788U, + 1792U, 1796U, 1800U, 1804U, 1808U, 1812U, 1816U, 1820U, 1824U, 1828U, 1832U, + 1836U, 1840U, 1844U, 1848U, 1852U, 1856U, 1860U, 1864U, 1868U, 1872U, 1876U, + 1880U, 1884U, 1888U, 1892U, 1896U, 1900U, 1904U, 1908U, 1912U, 1916U, 1920U, + 1924U, 1928U, 1932U, 1936U, 1940U, 1944U, 1948U, 1952U, 1956U, 1960U, 1964U, + 1968U, 1972U, 1976U, 1980U, 1984U, 1988U, 1992U, 1996U, 2000U, 2004U, 2008U, + 2012U, 2016U, 2020U, 2024U, 2028U, 2032U, 2036U, 2040U, 2044U, 2048U, 2052U, + 2056U, 2060U, 2064U, 2068U, 2072U, 2076U, 2080U, 2084U, 2088U, 2092U, 2096U, + 2100U, 2104U, 2108U, 2112U, 2116U, 2120U, 2124U, 2128U, 2132U, 2136U, 2140U, + 2144U, 2148U, 2152U, 2156U, 2160U, 2164U, 2168U, 2172U, 2176U, 2180U, 2184U, + 2188U, 2192U, 2196U, 2200U, 2204U, 2208U, 2212U, 2216U, 2220U, 2224U, 2228U, + 2232U, 2236U, 2240U, 2244U, 2248U, 2252U, 2256U, 2260U, 2264U, 2268U, 2272U, + 2276U, 2280U, 2284U, 2288U, 2292U, 2296U, 2300U, 2304U, 2308U, 2312U, 2316U, + 2320U, 2324U, 2328U, 2332U, 2336U, 2340U, 2344U, 2348U, 2352U, 2356U, 2360U, + 2364U, 2368U, 2372U, 2376U, 2380U, 2384U, 2388U, 2392U, 2396U, 2400U, 2404U, + 2408U, 2412U, 2416U, 2420U, 2424U, 2428U, 2432U, 2436U, 2440U, 2444U, 2448U, + 2452U, 2456U, 2460U, 2464U, 2468U, 2472U, 2476U, 2480U, 2484U, 2488U, 2492U, + 2496U, 2500U, 2504U, 2508U, 2512U, 2516U, 2520U, 2524U, 2528U, 2532U, 2536U, + 2540U, 2544U, 2548U, 2552U, 2556U, 2560U, 2564U, 2568U, 2572U, 2576U, 2580U, + 2584U, 2588U, 2592U, 2596U, 2600U, 2604U, 2608U, 2612U, 2616U, 2620U, 2624U, + 2628U, 2632U, 2636U, 2640U, 2644U, 2648U, 2652U, 2656U, 2660U, 2664U, 2668U, + 2672U, 2676U, 2680U, 2684U, 2688U, 2692U, 2696U, 2700U, 2704U, 2708U, 2712U, + 2716U, 2720U, 2724U, 2728U, 2732U, 2736U, 2740U, 2744U, 2748U, 2752U, 2756U, + 2760U, 2764U, 2768U, 2772U, 2776U, 2780U, 2784U, 2788U, 2792U, 2796U, 2800U, + 2804U, 2808U, 2812U, 2816U, 2820U, 2824U, 2828U, 2832U, 2836U, 2840U, 2844U, + 2848U, 2852U, 2856U, 2860U, 2864U, 2868U, 2872U, 2876U, 2880U, 2884U, 2888U, + 2892U, 2896U, 2900U, 2904U, 2908U, 2912U, 2916U, 2920U, 2924U, 2928U, 2932U, + 2936U, 2940U, 2944U, 2948U, 2952U, 2956U, 2960U, 2964U, 2968U, 2972U, 2976U, + 2980U, 2984U, 2988U, 2992U, 2996U, 3000U, 3004U, 3008U, 3012U, 3016U, 3020U, + 3024U, 3028U, 3032U, 3036U, 3040U, 3044U, 3048U, 3052U, 3056U, 3060U, 3064U, + 3068U, 3072U, 3076U, 3080U, 3084U, 3088U, 3092U, 3096U, 3100U, 3104U, 3108U, + 3112U, 3116U, 3120U, 3124U, 3128U, 3132U, 3136U, 3140U, 3144U, 3148U, 3152U, + 3156U, 3160U, 3164U, 3168U, 3172U, 3176U, 3180U, 3184U, 3188U, 3192U, 3196U, + 3200U, 3204U, 3208U, 3212U, 3216U, 3220U, 3224U, 3228U, 3232U, 3236U, 3240U, + 3244U, 3248U, 3252U, 3256U, 3260U, 3264U, 3268U, 3272U, 3276U, 3280U, 3284U, + 3288U, 3292U, 3296U, 3300U, 3304U, 3308U, 3312U, 3316U, 3320U, 3324U, 3328U, + 3332U, 3336U, 3340U, 3344U, 3348U, 3352U, 3356U, 3360U, 3364U, 3368U, 3372U, + 3376U, 3380U, 3384U, 3388U, 3392U, 3396U, 3400U, 3404U, 3408U, 3412U, 3416U, + 3420U, 3424U, 3428U, 3432U, 3436U, 3440U, 3444U, 3448U, 3452U, 3456U, 3460U, + 3464U, 3468U, 3472U, 3476U, 3480U, 3484U, 3488U, 3492U, 3496U, 3500U, 3504U, + 3508U, 3512U, 3516U, 3520U, 3524U, 3528U, 3532U, 3536U, 3540U, 3544U, 3548U, + 3552U, 3556U, 3560U, 3564U, 3568U, 3572U, 3576U, 3580U, 3584U, 3588U, 3592U, + 3596U, 3600U, 3604U, 3608U, 3612U, 3616U, 3620U, 3624U, 3628U, 3632U, 3636U, + 3640U, 3644U, 3648U, 3652U, 3656U, 3660U, 3664U, 3668U, 3672U, 3676U, 3680U, + 3684U, 3688U, 3692U, 3696U, 3700U, 3704U, 3708U, 3712U, 3716U, 3720U, 3724U, + 3728U, 3732U, 3736U, 3740U, 3744U, 3748U, 3752U, 3756U, 3760U, 3764U, 3768U, + 3772U, 3776U, 3780U, 3784U, 3788U, 3792U, 3796U, 3800U, 3804U, 3808U, 3812U, + 3816U, 3820U, 3824U, 3828U, 3832U, 3836U, 3840U, 3844U, 3848U, 3852U, 3856U, + 3860U, 3864U, 3868U, 3872U, 3876U, 3880U, 3884U, 3888U, 3892U, 3896U, 3900U, + 3904U, 3908U, 3912U, 3916U, 3920U, 3924U, 3928U, 3932U, 3936U, 3940U, 3944U, + 3948U, 3952U, 3956U, 3960U, 3964U, 3968U, 3972U, 3976U, 3980U, 3984U, 3988U, + 3992U, 3996U, 4000U, 4004U, 4008U, 4012U, 4016U, 4020U, 4024U, 4028U, 4032U, + 4036U, 4040U, 4044U, 4048U, 4052U, 4056U, 4060U, 4064U, 4068U, 4072U, 4076U, + 4080U, 4084U, 4088U, 4092U }, + + /* Computed Parameter: uDLookupTable1_bp01Data + * Referenced by: '/1-D Lookup Table1' + */ + { 10U, 50U }, + + /* Pooled Parameter (Expression: [1050 1250 1175 1195 1315 1300 1485 1440 1195]) + * Referenced by: + * '/Data Store Memory121' + * '/ACT1' + */ + { 1050U, 1250U, 1175U, 1195U, 1315U, 1300U, 1485U, 1440U, 1195U }, + + /* Computed Parameter: ACT1_Value + * Referenced by: '/ACT1' + */ + { 1225U, 1320U, 1270U, 1540U, 1480U, 1175U }, + + /* Computed Parameter: ACT1_Value_m + * Referenced by: '/ACT1' + */ + { 3075U, 3075U, 1605U, 1840U, 1650U, 1635U, 1820U, 1650U }, + + /* Computed Parameter: DataStoreMemory123_InitialValue + * Referenced by: '/Data Store Memory123' + */ + { 1225U, 1320U, 1270U, 1540U, 1480U, 1175U, 0U, 0U, 0U }, + + /* Computed Parameter: DataStoreMemory124_InitialValue + * Referenced by: '/Data Store Memory124' + */ + { 3075U, 3075U, 1605U, 1840U, 1650U, 1635U, 1820U, 1650U, 0U }, + + /* Pooled Parameter (Expression: [1:7]) + * Referenced by: + * '/1-D Lookup Table3' + * '/1-D Lookup Table4' + * '/1-D Lookup Table5' + */ + { 1U, 2U, 3U, 4U, 5U, 6U, 7U }, + + /* Pooled Parameter (Expression: [0:7]) + * Referenced by: + * '/1-D Lookup Table' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + */ + { 0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U }, + + /* Pooled Parameter (Expression: [10:10:110]) + * Referenced by: + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table' + * '/1-D Lookup Table2' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table' + * '/1-D Lookup Table2' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table' + * '/1-D Lookup Table2' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table' + * '/1-D Lookup Table2' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table' + * '/1-D Lookup Table2' + * '/1-D Lookup Table1' + * '/1-D Lookup Table2' + * '/1-D Lookup Table' + * '/1-D Lookup Table2' + */ + { 10U, 20U, 30U, 40U, 50U, 60U, 70U, 80U, 90U, 100U, 110U }, + + /* Pooled Parameter (Expression: [1 2 3 4 5 6 7 8 9]) + * Referenced by: + * '/Constant3' + * '/Constant5' + * '/Constant5' + * '/Constant5' + * '/Constant5' + * '/Constant5' + * '/Constant5' + */ + { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U }, + + /* Computed Parameter: Constant3_Value + * Referenced by: '/Constant3' + */ + { 1U, 2U, 3U, 4U, 5U, 6U }, + + /* Computed Parameter: Constant3_Value_d + * Referenced by: '/Constant3' + */ + { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U }, + + /* Pooled Parameter (Expression: ) + * Referenced by: + * '/ Left' + * '/ Right' + */ + { 0U, 1U, 2U, 3U, 4U, 5U }, + + /* Pooled Parameter (Expression: [0:6]) + * Referenced by: + * '/1-D Lookup Table' + * '/1-D Lookup Table' + */ + { 0U, 1U, 2U, 3U, 4U, 5U, 6U } +}; + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/MODULES/HVAC_M7_MODEL/HVAC_model_private.h b/MODULES/HVAC_M7_MODEL/HVAC_model_private.h new file mode 100644 index 0000000..f555f0c --- /dev/null +++ b/MODULES/HVAC_M7_MODEL/HVAC_model_private.h @@ -0,0 +1,392 @@ +/* + * File: HVAC_model_private.h + * + * Code generated for Simulink model 'HVAC_model'. + * + * Model version : 1.1466 + * Simulink Coder version : 24.1 (R2024a) 19-Nov-2023 + * C/C++ source code generated on : Fri Jul 31 15:00:33 2026 + * + * Target selection: ert.tlc + * Embedded hardware selection: ARM Compatible->ARM Cortex-M + * Emulation hardware selection: + * Differs from embedded hardware (MATLAB Host) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#ifndef HVAC_model_private_h_ +#define HVAC_model_private_h_ +#include +#include +#include "HVAC_model.h" +#include "HVAC_model_types.h" + +/* Includes for objects with custom storage classes */ +#include "Rs_Cal_Base.h" +#ifndef UCHAR_MAX +#include +#endif + +#if ( UCHAR_MAX != (0xFFU) ) || ( SCHAR_MAX != (0x7F) ) +#error Code was generated for compiler with different sized uchar/char. \ +Consider adjusting Test hardware word size settings on the \ +Hardware Implementation pane to match your compiler word sizes as \ +defined in limits.h of the compiler. Alternatively, you can \ +select the Test hardware is the same as production hardware option and \ +select the Enable portable word sizes option on the Code Generation > \ +Verification pane for ERT based targets, which will disable the \ +preprocessor word size checks. +#endif + +#if ( USHRT_MAX != (0xFFFFU) ) || ( SHRT_MAX != (0x7FFF) ) +#error Code was generated for compiler with different sized ushort/short. \ +Consider adjusting Test hardware word size settings on the \ +Hardware Implementation pane to match your compiler word sizes as \ +defined in limits.h of the compiler. Alternatively, you can \ +select the Test hardware is the same as production hardware option and \ +select the Enable portable word sizes option on the Code Generation > \ +Verification pane for ERT based targets, which will disable the \ +preprocessor word size checks. +#endif + +#if ( UINT_MAX != (0xFFFFFFFFU) ) || ( INT_MAX != (0x7FFFFFFF) ) +#error Code was generated for compiler with different sized uint/int. \ +Consider adjusting Test hardware word size settings on the \ +Hardware Implementation pane to match your compiler word sizes as \ +defined in limits.h of the compiler. Alternatively, you can \ +select the Test hardware is the same as production hardware option and \ +select the Enable portable word sizes option on the Code Generation > \ +Verification pane for ERT based targets, which will disable the \ +preprocessor word size checks. +#endif + +#if ( ULONG_MAX != (0xFFFFFFFFU) ) || ( LONG_MAX != (0x7FFFFFFF) ) +#error Code was generated for compiler with different sized ulong/long. \ +Consider adjusting Test hardware word size settings on the \ +Hardware Implementation pane to match your compiler word sizes as \ +defined in limits.h of the compiler. Alternatively, you can \ +select the Test hardware is the same as production hardware option and \ +select the Enable portable word sizes option on the Code Generation > \ +Verification pane for ERT based targets, which will disable the \ +preprocessor word size checks. +#endif + +/* Skipping ulong_long/long_long check: insufficient preprocessor integer range. */ +extern double rt_roundd(double u_0); +extern int8_t look1_iu8lu64n56ts8Ds16_binlcs(uint8_t u0, const uint8_t bp0[], + const int8_t table[], uint32_t maxIndex); +extern int16_t look1_iu8lu64n48ts16Ds32_binlcs(uint8_t u0, const uint8_t bp0[], + const int16_t table[], uint32_t maxIndex); +extern int16_t look1_is16lu64n32tu16Ds32Is16_binlcs(int16_t u0, const int16_t + bp0[], const uint16_t table[], uint32_t maxIndex); +extern uint32_t binsearch_u32s16(int16_t u_5, const int16_t bp[], uint32_t + startIndex, uint32_t maxIndex); +extern int16_t look1_is16lu64n32Ds32_binlcs(int16_t u0, const int16_t bp0[], + const int16_t table[], uint32_t maxIndex); +extern int16_t look1_is16lu64n32tu8Ds16Is16_binlcs(int16_t u0, const int16_t + bp0[], const uint8_t table[], uint32_t maxIndex); +extern int16_t look1_is16lu64n32Ds32_binlcn(int16_t u0, const int16_t bp0[], + const int16_t table[], uint32_t maxIndex); +extern int16_t look1_bs16ts16Dd_binlc(double u0, const int16_t bp0[], const + int16_t table[], uint32_t maxIndex); +extern uint8_t look2_iu8bu8s16lu64n32_binlcse(uint8_t u0, uint8_t u1, const + uint8_t bp0[], const int16_t bp1[], const uint8_t table[], const uint32_t + maxIndex[], uint32_t stride); +extern uint8_t look1_iu16lu64n48tu8_binlcse(uint16_t u0, const uint16_t bp0[], + const uint8_t table[], uint32_t maxIndex); +extern int16_t look1_iu16tdIs16_binlcs(uint16_t u0, const uint16_t bp0[], const + double table[], uint32_t maxIndex); +extern int16_t look1_iu16lu64n48ts16Ds32_binlcs(uint16_t u0, const uint16_t bp0[], + const int16_t table[], uint32_t maxIndex); +extern int16_t look1_iu16bs16lu64n32ts16Ds32_binlcs(uint16_t u0, const int16_t + bp0[], const int16_t table[], uint32_t maxIndex); +extern double look1_bs16ts16DdId_binlc(double u0, const int16_t bp0[], const + int16_t table[], uint32_t maxIndex); +extern uint8_t look1_iu8lu64n56_binlcse(uint8_t u0, const uint8_t bp0[], const + uint8_t table[], uint32_t maxIndex); +extern double look1_iu16td_binlc(uint16_t u0, const uint16_t bp0[], const double + table[], uint32_t maxIndex); +extern uint32_t plook_u32s16_bincka(int16_t u_6, const int16_t bp[], uint32_t + maxIndex); +extern int32_t div_nzp_s32_round(int32_t numerator, int32_t denominator); +extern void get_tg_FLL_for_LVL(uint8_t rtu_ambient_Lvl, uint8_t rtu_set_tmp, + int16_t *rty_vals); +extern void get_tg_FLL_for_LVL_j(uint8_t rtu_ambient_Lvl, uint8_t rtu_set_tmp, + int16_t *rty_vals); +extern void g_assFLOW_BI_AMB_TGT_n(uint8_t rtu_LVL, int16_t + *rty_c_g_assFLOW_BI_AMB_TGT); +extern void Bilevel(int16_t rtu_Amb_Fb, uint8_t rtu_LVL, uint16_t rty_Out1[9], + uint8_t rtu_setTempFL, uint8_t rtu_setTempFR); +extern void g_assFLOW_BI_AMB_TGT_e(uint8_t rtu_LVL, int16_t + *rty_c_g_assFLOW_BI2_AMB_TGT); +extern void Bilevel2(int16_t rtu_Amb_Fb, uint8_t rtu_LVL, uint16_t rty_Out1[9], + uint8_t rtu_setTempFL, uint8_t rtu_setTempFR); +extern void g_aucFLOW_AF_FOOT_VALVE_MAX_e(uint8_t rtu_LVL, uint8_t + *rty_c_g_aucFLOW_AF_FOOT_VALVE_MAX); +extern void g_assFLOW_AF_AMB_TGT_g(uint8_t rtu_LVL, int16_t + *rty_c_g_assFLOW_AF_AMB_TGT); +extern void Afoot(int16_t rtu_Amb_Fb, uint8_t rtu_LVL, uint16_t rty_Out1[9], + uint8_t rtu_setTempFL, uint8_t rtu_setTempFR); +extern void g_aucFLOW_AFSM_FOOT_VALVE_MAX_f(uint8_t rtu_LVL, uint8_t + *rty_c_g_aucFLOW_AFSM_FOOT_VALVE_MAX); +extern void Afoot_Summer(int16_t rtu_Amb_Fb, uint8_t rtu_LVL, uint16_t rty_Out1 + [9], uint8_t rtu_setTempFL, uint8_t rtu_setTempFR); +extern void left(uint8_t rtu_idx, uint16_t rty_vals[9]); +extern void IfActionSubsystem(uint8_t rtu_In1, int8_t *rty_Out1, int16_t + *rty_Out2); +extern void IfActionSubsystem1(int8_t *rty_Out1, int16_t *rty_Out2); +extern void IfActionSubsystem2(uint8_t rtu_In1, int8_t *rty_Out1, int16_t + *rty_Out2); +extern void IfActionSubsystem_b(uint8_t rtu_In1, int8_t *rty_Out1, int16_t + *rty_Out2); +extern void IfActionSubsystem2_o(uint8_t rtu_In1, int8_t *rty_Out1, int16_t + *rty_Out2); +extern void IfActionSubsystem_n(uint8_t rtu_In1, int8_t *rty_Out1, int16_t + *rty_Out2); +extern void IfActionSubsystem2_c(uint8_t rtu_In1, int8_t *rty_Out1, int16_t + *rty_Out2); +extern void g_assSTART_ENTER_INCAR_n(uint8_t rtu_LVL, int16_t *rty_out); +extern void Level2(int8_t *rty_step); +extern void g_assSTART_ENTER_COOLANT_m(uint8_t rtu_LVL, int16_t *rty_out); +extern void Level4(int8_t *rty_step1, const uint8_t *rtd_CCU_MODE_FL, const + int16_t *rtd_ECT, const uint8_t *rtd_LEVEL, const uint8_t + *rtd_LO_HI_MODE_FL); +extern void Level0(int8_t *rty_step); +extern void incarfilterdown(uint8_t rtu_LVL, uint8_t *rty_out); +extern void incarfilterup(uint8_t rtu_LVL, uint8_t *rty_out); +extern void g_assSTART_COOLANT_STEP0_TO_1_c(uint8_t rtu_LVL, int16_t *rty_out); +extern void uwayvalvestatus(uint8_t rtu_LVL, uint8_t *rty_out); +extern void Dtg_FrontLower_X(uint8_t rtu_LVL, uint8_t *rty_out); +extern void Dtg_FrontUpper_X(uint8_t rtu_LVL, uint8_t *rty_out); +extern void Incartempgotofromstep1tostep2(uint8_t rtu_LVL, int16_t *rty_out); +extern void MATLABFunction1_Init(DW_MATLABFunction1 *localDW); +extern void MATLABFunction1(uint32_t rtu_t_now, uint16_t rtu_time_delta, bool + *rty_timer_out, DW_MATLABFunction1 *localDW); +extern void blowerFR(uint8_t rtu_LVL, uint16_t *rty_out); +extern void modeFRstep1(uint8_t rtu_LVL, uint8_t *rty_out); +extern void windowheating(uint8_t rtu_LVL, uint8_t *rty_out); +extern void MATLABFunction1_a_Init(DW_MATLABFunction1_f *localDW); +extern void MATLABFunction1_j(uint32_t rtu_t_now, uint32_t rtu_time_delta, bool * + rty_timer_out, DW_MATLABFunction1_f *localDW); +extern void Timegotofromstep1tostep2(uint8_t rtu_LVL, int16_t *rty_out); +extern void ECTminmax(uint8_t rtu_LVL, int16_t rty_out[2]); +extern void blowerminmax(uint8_t rtu_LVL, uint16_t rty_out[2]); +extern void uwayvalvestatus_m(uint8_t rtu_LVL, uint8_t *rty_out); +extern void timeforstep(uint8_t rtu_LVL, uint8_t *rty_out); +extern void timeforstep_d(uint8_t rtu_LVL, uint8_t *rty_out); +extern void Timegotofromstep2tostep3(uint8_t rtu_LVL, int16_t *rty_out); +extern void blowerstep(uint8_t rtu_LVL, uint16_t *rty_out); +extern void blowertimeforstep(uint8_t rtu_LVL, uint16_t *rty_out); +extern void step_g(uint8_t rtu_LVL, uint8_t *rty_out); +extern void timeforstep_f(uint8_t rtu_LVL, uint8_t *rty_out); +extern void windowheating_o(uint8_t rtu_LVL, uint8_t *rty_out); +extern void autodemistautodefog(uint8_t rtu_LVL, uint8_t *rty_out); +extern void Level3_Init(DW_Level3 *localDW); +extern void Level3(int8_t *rty_step, uint8_t *rtd_Autodefog, uint8_t + *rtd_Blower_FL, uint8_t *rtd_Blower_FR, const uint8_t + *rtd_Blower_logic_FL, const uint8_t *rtd_CCU_MODE_FL, + uint16_t *rtd_Dtg_FLL, uint16_t *rtd_Dtg_FLR, uint16_t + *rtd_Dtg_FUL, uint16_t *rtd_Dtg_FUR, const int16_t + *rtd_Dtg_logic_FLL, const int16_t *rtd_Dtg_logic_FUL, uint8_t + *rtd_El_window_heating, const bool *rtd_HI_logic_on, uint8_t * + rtd_Incar_filter_down_value, uint8_t + *rtd_Incar_filter_up_value, const uint8_t *rtd_LEVEL, const + uint8_t *rtd_LO_HI_MODE_FL, uint8_t *rtd_Mode_FL, uint8_t + *rtd_Mode_FR, const uint8_t *rtd_Mode_logic_FL, double + *rtd_Recirculation, uint8_t *rtd_Valve_3_way, const uint32_t * + rtd_t_now, DW_Level3 *localDW); +extern void Step3F(int8_t *rty_step, int8_t *rtd_start_control_finished_front); +extern void g_ausSTART_ENTER_SETTEMP_i(uint8_t rtu_LVL, int16_t *rty_out); +extern void g_assSTART_ENTER_INCAR_f(uint8_t rtu_LVL, int16_t *rty_out); +extern void g_assSTART_ENTER_COOLANT_m1(uint8_t rtu_LVL, int16_t *rty_out); +extern void Level4_j(int8_t *rty_step1, const uint8_t *rtd_CCU_MODE_RR, const + int16_t *rtd_ECT, const int16_t *rtd_Incar_RR, const + uint8_t *rtd_LEVEL, const uint8_t *rtd_LO_HI_MODE_RR); +extern void incarfilterdown_m(uint8_t rtu_LVL, uint8_t *rty_out); +extern void incarfilterup_j(uint8_t rtu_LVL, uint8_t *rty_out); +extern void g_assSTART_COOLANT_STEP0_TO_1_j(uint8_t rtu_LVL, int16_t *rty_out); +extern void Level4_h(int8_t *rty_step1, uint8_t *rtd_Blower_RL, uint8_t + *rtd_Blower_RR, const uint8_t *rtd_CCU_MODE_RR, uint16_t + *rtd_Dtg_RL, uint16_t *rtd_Dtg_RR, const int16_t *rtd_ECT, + uint8_t *rtd_Incar_filter_down_value, uint8_t + *rtd_Incar_filter_up_value, const uint8_t *rtd_LEVEL, const + uint8_t *rtd_LO_HI_MODE_RR, uint8_t *rtd_Mode_RL, uint8_t + *rtd_Mode_RR, uint8_t *rtd_Valve_2_way, uint8_t + *rtd_Valve_3_way); +extern void uwayvalve(uint8_t rtu_LVL, uint8_t *rty_out); +extern void Dtg_rear(uint8_t rtu_LVL, uint8_t *rty_out); +extern void Incartempgotofromstep1tostep2_m(uint8_t rtu_LVL, int16_t *rty_out); +extern void Timegotofromstep1tostep2_n(uint8_t rtu_LVL, int16_t *rty_out); +extern void moderearstep1(uint8_t rtu_LVL, uint8_t *rty_out); +extern void Level0_c_Init(DW_Level0_h *localDW); +extern void Level0_g(int8_t *rty_step, uint8_t *rtd_Blower_RL, uint8_t + *rtd_Blower_RR, const uint8_t *rtd_CCU_MODE_RR, uint16_t + *rtd_Dtg_RL, uint16_t *rtd_Dtg_RR, const int16_t + *rtd_Incar_RR, uint8_t *rtd_Incar_filter_down_value, + uint8_t *rtd_Incar_filter_up_value, const uint8_t + *rtd_LEVEL, const uint8_t *rtd_LO_HI_MODE_RR, uint8_t + *rtd_Mode_RL, uint8_t *rtd_Mode_RR, double + *rtd_Recirculation, uint8_t *rtd_Valve_2_way, const + uint32_t *rtd_t_now, DW_Level0_h *localDW); +extern void blowerstartfinish(uint8_t rtu_LVL, uint16_t rty_out[2]); +extern void ECTminmax_j(uint8_t rtu_LVL, int16_t rty_out[2]); +extern void Level4_b_Init(DW_Level4_h *localDW); +extern void Level4_m(int8_t *rty_step, uint8_t *rtd_Blower_RL, uint8_t + *rtd_Blower_RR, const uint8_t *rtd_CCU_MODE_RR, uint16_t + *rtd_Dtg_RL, uint16_t *rtd_Dtg_RR, const int16_t *rtd_ECT, + const int16_t *rtd_Incar_RR, uint8_t + *rtd_Incar_filter_down_value, uint8_t + *rtd_Incar_filter_up_value, const uint8_t *rtd_LEVEL, const + uint8_t *rtd_LO_HI_MODE_RR, uint8_t *rtd_Mode_RL, uint8_t + *rtd_Mode_RR, double *rtd_Recirculation, uint8_t + *rtd_Valve_2_way, const uint32_t *rtd_t_now, DW_Level4_h + *localDW); +extern void timeforstep_k(uint8_t rtu_LVL, uint8_t *rty_out); +extern void blowerstep_c(uint8_t rtu_LVL, uint16_t *rty_out); +extern void blowertimeforstep_k(uint8_t rtu_LVL, uint16_t *rty_out); +extern void step_a(uint8_t rtu_LVL, uint8_t *rty_out); +extern void timeforstep_dm(uint8_t rtu_LVL, uint8_t *rty_out); +extern void Level0_h_Init(DW_Level0_hr *localDW); +extern void Level0_a(int8_t *rty_step, uint8_t *rtd_Blower_RL, uint8_t + *rtd_Blower_RR, const uint16_t *rtd_Blower_logic_RR, const + uint8_t *rtd_CCU_MODE_FL, uint16_t *rtd_Dtg_RL, uint16_t + *rtd_Dtg_RR, const int16_t *rtd_Dtg_logic_RR, uint8_t + *rtd_Incar_filter_down_value, uint8_t + *rtd_Incar_filter_up_value, const uint8_t *rtd_LEVEL, const + uint8_t *rtd_LO_HI_MODE_FL, uint8_t *rtd_Mode_RL, uint8_t + *rtd_Mode_RR, const uint8_t *rtd_Mode_logic_RR, double + *rtd_Recirculation, uint8_t *rtd_Valve_2_way, const + uint32_t *rtd_t_now, DW_Level0_hr *localDW); +extern void Level2_j_Init(DW_Level2_j *localDW); +extern void Level2_f(int8_t *rty_step, uint8_t *rtd_Blower_RL, uint8_t + *rtd_Blower_RR, const uint16_t *rtd_Blower_logic_RR, const + uint8_t *rtd_CCU_MODE_FL, uint16_t *rtd_Dtg_RL, uint16_t + *rtd_Dtg_RR, const int16_t *rtd_Dtg_logic_RR, const bool + *rtd_HI_logic_on, uint8_t *rtd_Incar_filter_down_value, + uint8_t *rtd_Incar_filter_up_value, const uint8_t + *rtd_LEVEL, const uint8_t *rtd_LO_HI_MODE_FL, uint8_t + *rtd_Mode_RL, uint8_t *rtd_Mode_RR, const uint8_t + *rtd_Mode_logic_RR, double *rtd_Recirculation, uint8_t + *rtd_Valve_2_way, const uint32_t *rtd_t_now, DW_Level2_j + *localDW); +extern void funcg_assAUTO_STEP_DUCT_TG_U(uint8_t rtu_LVL, double rtu_AF_STEP, + int16_t *rty_y); +extern void funcg_assAUTO_STEP_DUCT_TG_L(uint8_t rtu_LVL, double rtu_AF_STEP, + int16_t *rty_y); +extern void funcg_assAUTO_STEP_DUCT_TG_R(uint8_t rtu_LVL, double rtu_AF_STEP, + int16_t *rty_y); +extern void correctionrate(int16_t rtu_SET, uint8_t rtu_LVL, int16_t *rty_y); +extern void is_ending_with_5(uint16_t rtu_SET, bool *rty_is_ending_with_5); +extern void u(uint8_t rtu_lvl, uint16_t *rty_f_g_ausINCARRATE_FALLING_F); +extern void u_j(uint8_t rtu_lvl, uint16_t *rty_f_g_ausINCARRATE_FALLING_DIFF_F); +extern void u_c(int16_t rtu_temp_raw, uint8_t rtu_lvl, uint16_t *rty_out, double + *rtd_KEEP_FALLING_FL_UNTIL_LIMIT, const double + *rtd_Temp_FL_store); +extern void u_l(int16_t rtu_temp_raw, uint8_t rtu_lvl, uint16_t + *rty_riseperminute, double *rtd_KEEP_FALLING_FL_UNTIL_LIMIT, + const double *rtd_Temp_FL_store); +extern void u_h(uint8_t rtu_lvl, uint16_t *rty_f_g_ausINCARRATE_RISING_F); +extern void u_k(uint8_t rtu_lvl, uint16_t *rty_f_g_ausINCARRATE_RISING_DIFF_F); +extern void u_lz(uint8_t rtu_lvl, uint16_t *rty_out); +extern void g_ausINCARRATE_RISING_DIFF_F8(uint16_t + *rty_f_g_ausINCARRATE_RISING_DIFF_F); +extern void INCARRATE_RISING_DIFF_F7(uint16_t + *rty_f_g_ausINCARRATE_RISING_DIFF_F); +extern void u_f(uint8_t rtu_lvl, uint16_t *rty_out); +extern void RL(int16_t rtu_temp_in, double *rty_temp_out); +extern void AMBRATE_RISING_DIFF8(uint16_t *rty_f_g_ausINCARRATE_FALLING_DIFF_R); +extern void u_kk(uint8_t rtu_lvl, uint16_t *rty_f_g_ausINCARRATE_FALLING_R); +extern void u_b(uint8_t rtu_lvl, uint16_t *rty_f_g_ausINCARRATE_FALLING_DIFF_R); +extern void u_hr(uint8_t rtu_lvl, uint16_t *rty_out); +extern void AMBRATE_FALLING_DIFF7(uint16_t *rty_f_g_ausINCARRATE_FALLING_DIFF_R); +extern void u_g(uint8_t rtu_lvl, uint16_t *rty_out); +extern void u_m(uint8_t rtu_lvl, uint16_t *rty_f_g_ausINCARRATE_RISING_R); +extern void u_o(uint8_t rtu_lvl, uint16_t *rty_f_g_ausINCARRATE_RISING_DIFF_R); +extern void u_gq(uint8_t rtu_lvl, uint16_t *rty_out); +extern void g_ausINCARRATE_RISING_DIFF_R8(uint16_t + *rty_f_g_ausINCARRATE_RISING_DIFF_R); +extern void INCARRATE_RISING_DIFF_R7(uint16_t + *rty_f_g_ausINCARRATE_RISING_DIFF_R); +extern void u_b3(uint8_t rtu_lvl, uint16_t *rty_out); +extern void AFAutoFoot(uint16_t rty_out[8]); +extern void AFAutoFootsummer(uint16_t rty_out[8]); +extern void AFBilevel(uint16_t rty_out[8]); +extern void AFBilevel2(uint16_t rty_out[8]); +extern void AFDefrost(uint16_t rty_out[8]); +extern void AFFoot(uint16_t rty_out[8]); +extern void AFFootDef(uint16_t rty_out[8]); +extern void AFHidefvent(uint16_t rty_out[8]); +extern void AFTrimode(uint16_t rty_out[8]); +extern void AFVENT(uint16_t rty_out[8]); +extern void closestspeed(const uint16_t rtu_AF_for_speed[8], uint16_t + rtu_AF_value, uint8_t *rty_idx); +extern void AFREARBiLevel(uint16_t rty_out[8]); +extern void AFREARFoot(uint16_t rty_out[8]); +extern void AFREARVENTAUTO(uint16_t rty_out[8]); +extern void directionforREARindexmode(uint16_t rtu_index_mode, double rty_Y[4]); +extern void Zone_Climate_Logic_Auto_FL2_Init(uint8_t *rty_out_def, uint8_t + *rty_out_face, uint8_t *rty_out_foot, uint8_t *rty_out_auto, double + *rty_out_ac, DW_Zone_Climate_Logic_Auto_FL2 *localDW); +extern void Zone_Climate_Logic_Auto_FL2(double rtu_btn_def, uint8_t rtu_btn_face, + uint8_t rtu_btn_foot, uint8_t rtu_btn_auto, uint8_t rtu_btn_ac, uint8_t + *rty_out_def, uint8_t *rty_out_face, uint8_t *rty_out_foot, uint8_t + *rty_out_auto, double *rty_out_ac, DW_Zone_Climate_Logic_Auto_FL2 *localDW); +extern void AFforBiLevel(uint8_t rtu_blower_speed, uint16_t *rty_out); +extern void AFforDef(uint8_t rtu_blower_speed, uint16_t *rty_out); +extern void AFforFoorDef(uint8_t rtu_blower_speed, uint16_t *rty_out); +extern void AFforFoot(uint8_t rtu_blower_speed, uint16_t *rty_out); +extern void AFforHi_Level(uint8_t rtu_blower_speed, uint16_t *rty_out); +extern void AFforTriLevel(uint8_t rtu_blower_speed, uint16_t *rty_out); +extern void AFforVentmode(uint8_t rtu_blower_speed, uint16_t *rty_out); +extern void RearLeftAFmanualdirections(bool rtu_Enable, uint8_t rtu_blowerspeed, + uint8_t rtu_faceison, uint8_t rtu_footison, uint16_t *rty_AFout); +extern void funcg_ascAUTO_STEP_AF_F(double rtu_AF_STEP, int8_t *rty_y); +extern void u_m2(int16_t rtu_lvl, uint8_t *rty_f_g_aucAMBRATE_FALLING); +extern void u_kb(int16_t rtu_amb_raw, int16_t rtu_lvl, uint8_t *rty_out, const + double *rtd_AMB_store, double *rtd_KEEP_FALLING_UNTIL_LIMIT); +extern void u_my(int16_t rtu_amb_raw, int16_t rtu_lvl, uint8_t + *rty_riseperminute, const double *rtd_AMB_store, double + *rtd_KEEP_FALLING_UNTIL_LIMIT); +extern void u_h3(int16_t rtu_lvl, uint8_t *rty_f_g_aucAMBRATE_RISING); +extern void u_fr(int16_t rtu_lvl, uint8_t *rty_f_g_aucAMBRATE_RISING_DIFF_LVL); +extern void u_p(int16_t rtu_amb_raw, int16_t rtu_lvl, uint8_t *rty_out, const + double *rtd_AMB_store, double *rtd_KEEP_RISING_UNTIL_LIMIT); +extern void u_g2(int16_t rtu_amb_raw, int16_t rtu_lvl, uint8_t + *rty_riseperminute, const double *rtd_AMB_store, double + *rtd_KEEP_RISING_UNTIL_LIMIT); +extern void IfActionSubsystem_h(int8_t *rty_Out1, double + *rtd_ErrorHomming_private, double *rtd_Start_timer_n, int8_t + *rtd_stepSig_private); +extern void MATLABFunction_Init(DW_MATLABFunction *localDW); +extern void MATLABFunction(double rtu_cond, uint32_t rtu_t_now, uint32_t *rty_dt, + DW_MATLABFunction *localDW); +extern void IfActionSubsystem1_h(int8_t *rty_Output, uint8_t + *rtd_CCU_ActuatorErrF_Stat_private, uint8_t rtd_COM_private[9], uint8_t + rtd_ErrorActuator[9], uint8_t rtd_ErrorCalibration_private[9], const double + *rtd_LOGGER_LIN, uint8_t rtd_MODE_private[9], uint8_t + rtd_dtc_state_error_model[127]); +extern void paramindexformode(uint8_t rtu_index_mode, double *rty_Y); +extern void valvesformode(uint8_t rtu_MODE, uint16_t rty_get_valves[9]); +extern void valves_rear_left(uint8_t rtu_MODE, uint16_t rty_get_valves[6]); +extern void MODE_for_set_and_lvl(uint8_t rtu_LVL, int16_t rtu_SET, uint8_t + *rty_get_mode); +extern void increase(int16_t rtu_duct_tg, const uint16_t rtu_mode_array[7], + uint16_t *rty_y); +extern void decrease(int16_t rtu_duct_tg, const uint16_t rtu_mode_array[7], + uint16_t *rty_y); +extern void valves_rear_left_e(uint16_t rtu_MODE, uint16_t rty_get_valves[6]); +extern void ValvesforBiLevel(uint16_t rty_out[9]); +extern void ValvesforFootDef(uint16_t rty_out[9]); +extern void ValvesforHi_Level(uint16_t rty_out[9]); +extern void ValvesforTriLevel(uint16_t rty_out[9]); +extern void AFforBiLevel_i(uint16_t rty_out[6]); +extern void valvesforVentmode(uint16_t rty_out[6]); + +#endif /* HVAC_model_private_h_ */ + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/MODULES/HVAC_M7_MODEL/HVAC_model_types.h b/MODULES/HVAC_M7_MODEL/HVAC_model_types.h new file mode 100644 index 0000000..f620d4b --- /dev/null +++ b/MODULES/HVAC_M7_MODEL/HVAC_model_types.h @@ -0,0 +1,1432 @@ +/* + * File: HVAC_model_types.h + * + * Code generated for Simulink model 'HVAC_model'. + * + * Model version : 1.1466 + * Simulink Coder version : 24.1 (R2024a) 19-Nov-2023 + * C/C++ source code generated on : Fri Jul 31 15:00:33 2026 + * + * Target selection: ert.tlc + * Embedded hardware selection: ARM Compatible->ARM Cortex-M + * Emulation hardware selection: + * Differs from embedded hardware (MATLAB Host) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#ifndef HVAC_model_types_h_ +#define HVAC_model_types_h_ +#include +#ifndef DEFINED_TYPEDEF_FOR_Status_Eva_Tgt_Bus_ +#define DEFINED_TYPEDEF_FOR_Status_Eva_Tgt_Bus_ + +typedef struct { + uint16_t EvaTgt_F; + uint16_t EvaTgt_R; +} Status_Eva_Tgt_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_CmdCAN_CCU_STAT1_Bus_ +#define DEFINED_TYPEDEF_FOR_CmdCAN_CCU_STAT1_Bus_ + +typedef struct { + uint8_t CCU_ModeFL_Stat; + uint8_t CCU_ModeFR_Stat; + uint8_t CCU_ModeRL_Stat; + uint8_t CCU_ModeRR_Stat; + uint8_t CCU_AutoModeFL_Stat; + uint8_t CCU_AutoModeFR_Stat; + uint8_t CCU_AirDirectionRL_Face_Stat; + uint8_t CCU_AirDirectionRL_Foot_Stat; + uint8_t CCU_AutoModeRL_Stat; + uint8_t CCU_AutoModeRR_Stat; + uint8_t CCU_AirDirectionRR_Face_Stat; + uint8_t CCU_AirDirectionRR_Foot_Stat; + uint8_t CCU_AirDirectionFL_Def_Stat; + uint8_t CCU_AirDirectionFL_Face_Stat; + uint8_t CCU_AirDirectionFL_Foot_Stat; + uint8_t CCU_AirDirectionFR_Def_Stat; + uint8_t CCU_AirDirectionFR_Face_Stat; + uint8_t CCU_AirDirectionFR_Foot_Stat; + uint8_t CCU_Recirculation_Stat; + uint8_t CCU_BlowerSpeedFL_Stat; + uint8_t CCU_TargetTempFL_Stat_ro; + uint8_t CCU_BlowerSpeedFR_Stat; + uint8_t CCU_TargetTempFR_Stat_ro; + uint8_t CCU_BlowerSpeedRL_Stat; + uint8_t CCU_TargetTempRR_Stat_ro; + uint8_t CCU_BlowerSpeedRR_Stat; + uint8_t CCU_TargetTempRL_Stat_ro; +} CmdCAN_CCU_STAT1_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_Status_Duct_Select_Bus_ +#define DEFINED_TYPEDEF_FOR_Status_Duct_Select_Bus_ + +typedef struct { + uint8_t Duct_FL; + uint8_t Duct_FR; + uint8_t Duct_RL; + uint8_t Duct_RR; +} Status_Duct_Select_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_CmdBusPWMGet_ +#define DEFINED_TYPEDEF_FOR_CmdBusPWMGet_ + +typedef struct { + uint8_t pwmPercentFront; + uint8_t pwmPercentRear; + uint8_t pwmPercentFrontReserved; + uint8_t pwmPercentRearReserved; +} CmdBusPWMGet; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_CmdBusPwm_ +#define DEFINED_TYPEDEF_FOR_CmdBusPwm_ + +typedef struct { + uint8_t pwmPercentFront; + uint8_t pwmPercentRear; + uint8_t pwmPercentFrontReserved; + uint8_t pwmPercentRearReserved; +} CmdBusPwm; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_CCUCAN_BCM_Powertrain_Bus_ +#define DEFINED_TYPEDEF_FOR_CCUCAN_BCM_Powertrain_Bus_ + +typedef struct { + uint16_t BCM_AmbTempRaw_ro; + uint16_t AvgFuelLvl_ro; + uint8_t BCM_T50_Request; + uint8_t RemoteICEStartReq; + uint8_t BCM_HVAC_Pump_Req; + uint8_t BCM_Powertrain_RC; + uint8_t BCM_VAU_Authorization_Req; + uint8_t BCM_Powertrain_CS; +} CCUCAN_BCM_Powertrain_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_CCUCAN_BCM_Climatic_Bus_ +#define DEFINED_TYPEDEF_FOR_CCUCAN_BCM_Climatic_Bus_ + +typedef struct { + uint8_t SolarSensRightVal_ro; + uint8_t BCM_WipeLowTempWarn_Req; + uint8_t FrontWindowHeating_Status; + uint8_t RearWindowHeating_Status; + uint8_t SWM_Heating_Req; + uint8_t BCM_RearWindowHeating_Cmd; + uint8_t BCM_SteerWheelHeating_Stat; + uint8_t RainDetected; + uint8_t SolarSensLeftVal_ro; + uint8_t SideWindowHeating_Status; + uint8_t BCM_Wiper_Stat; + uint8_t BCM_SideWindowType_Stat; + uint8_t BCM_MirrorHeating_Cmd; + uint8_t BCM_WindowWashingSt; + uint8_t BCM_GloveBox_Stat; + uint8_t RainDensity; + uint8_t WindshieldTemp_ro; + uint8_t WindshieldHumidity_ro; +} CCUCAN_BCM_Climatic_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_CCUCAN_EMS_Veh_Bus_ +#define DEFINED_TYPEDEF_FOR_CCUCAN_EMS_Veh_Bus_ + +typedef struct { + uint16_t EMS_nICEngineSpeed3_Val_ro; + uint8_t EMS_EngCoolTemp_Val_ro; + uint8_t EMS_BARO_ENG_Val; + uint8_t EMS_AccelPdlPosnOBD_Val; + uint16_t EMS_EngTrqStatic_Val_ro; + uint8_t EMS_HvSystemFailure; + uint8_t EMS_CoolLiquidLowWarning; + uint8_t EMS_InstFuelConsumption; +} CCUCAN_EMS_Veh_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_CCUCAN_ESC_04_Bus_ +#define DEFINED_TYPEDEF_FOR_CCUCAN_ESC_04_Bus_ + +typedef struct { + uint16_t ESC_VehicleSpeed_ro; + uint8_t ESC_VehicleSpeed_ValueError; + uint8_t ESC_Lamp; + uint8_t ESC_AVH_Active; + uint8_t ESC_Bls_Out; + uint8_t ESC_Bla; + uint8_t ESC_ABS_Lamp; + uint8_t ESC_EBD_Lamp; + uint8_t ESC_TCS_Fault; + uint8_t ESC_CDPDecelActive; + uint8_t ESC_BLS_Fault; + uint8_t ESC_CtlActiveAbs; + uint8_t ESC_CtlActiveEbd; + uint8_t ESC_CtlActiveTcs; + uint8_t ESC_CtlActiveVdc; + uint8_t ESC_Passive_Lamp; + uint8_t ESC_Gearshift_Inhibit; + uint8_t ESC_HDC_Activated; + uint8_t ESC_CtlActiveHDC; + uint8_t ESC_HDC_rejected; + uint8_t ESC_EmergencyBraking; + uint8_t ESC_RequestToEPB; + uint8_t ESC_CDPDecelAvailable; + uint8_t ESC_PEBWarningLampReq; + uint8_t ESC_HDC_SpeedLimit; + uint8_t CddActive_2; + uint8_t ESC_04_RC; + uint8_t ESC_04_CS; +} CCUCAN_ESC_04_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_dbgCAN_dbg_Sen_Amb_Bus_ +#define DEFINED_TYPEDEF_FOR_dbgCAN_dbg_Sen_Amb_Bus_ + +typedef struct { + int16_t dbg_Sen_Amb_ro; + int16_t dbg_Sen_Amb_Raw_ro; + int16_t dbg_Amb_Tg_ro; +} dbgCAN_dbg_Sen_Amb_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_CmdCAN_CCU_STAT2_Bus_ +#define DEFINED_TYPEDEF_FOR_CmdCAN_CCU_STAT2_Bus_ + +typedef struct { + uint8_t CCU_AromaCartridgeSw_Stat; + uint8_t CCU_FrontZoneSync_Stat; + uint8_t CCU_RearZoneSync_Stat; + uint8_t CCU_AllZoneSync_Stat; + uint8_t CCU_ACfront_Stat; + uint8_t CCU_ACrear_Stat; + uint8_t CCU_ACmaxF_Stat; + uint8_t CCU_ACmaxR_Stat; + uint8_t CCU_Defrost_Stat; + uint8_t CCU_Ionization_Stat; + uint8_t CCU_FootTempCorFL_Stat; + uint8_t CCU_FootTempCorFR_Stat; + uint8_t CCU_AromaIntens_Stat; + uint8_t CCU_FootTempCorRL_Stat; + uint8_t CCU_FootTempCorRR_Stat; + uint8_t CCU_DeflectorSwDL_Stat; + uint8_t CCU_DeflectorSwDR_Stat; + uint8_t CCU_DeflectorSwFPL_Stat; + uint8_t CCU_DeflectorSwFPR_Stat; + uint8_t CCU_DeflectorSwFCL_Stat; + uint8_t CCU_DeflectorSwFCR_Stat; + uint8_t CCU_DeflectorSwRLB_Stat; + uint8_t CCU_DeflectorSwRRB_Stat; +} CmdCAN_CCU_STAT2_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_dbgCAN_dbg_Sen_Incar_Bus_ +#define DEFINED_TYPEDEF_FOR_dbgCAN_dbg_Sen_Incar_Bus_ + +typedef struct { + uint8_t dbg_Sen_Incar_MultMsg_Idx; + int16_t dbg_Sen_Incar_Raw_FL_ro; + int16_t dbg_Sen_Incar_FL_ro; + int16_t dbg_Sen_Incar_Raw_FR_ro; + int16_t dbg_Sen_Incar_FR_ro; + int16_t dbg_Sen_Incar_Raw_RL_ro; + int16_t dbg_Sen_Incar_RL_ro; + int16_t dbg_Sen_Incar_Raw_RR_ro; + int16_t dbg_Sen_Incar_RR_ro; +} dbgCAN_dbg_Sen_Incar_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_dbgCAN_dbg_Sen_0_Bus_ +#define DEFINED_TYPEDEF_FOR_dbgCAN_dbg_Sen_0_Bus_ + +typedef struct { + uint8_t dbg_Sen_BattVolt_ro; + uint16_t dbg_Sen_Pressure_ro; + uint16_t dbg_Sen_Sun_L; + uint16_t dbg_Sen_Sun_R; +} dbgCAN_dbg_Sen_0_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_tPowerEnable_Bus_ +#define DEFINED_TYPEDEF_FOR_tPowerEnable_Bus_ + +typedef struct { + uint8_t SW5V_EN; + uint8_t PBATT_CK_EN; + uint8_t Incar_Motor_Front_EN; + uint8_t Incar_Motor_Rear_EN; + uint8_t TwoWayValve_EN; + uint8_t ReservePower_EN; + uint8_t PtcRelayDriver1_EN; + uint8_t PtcRelayDriver2_EN; + uint8_t ShutOffFront_EN; + uint8_t ShutOffRear_EN; + uint8_t EN_ReservePower; + uint8_t LIN_ActPower_AB; + uint8_t LIN_ActPower_C; + uint8_t ShutOffTXV1_EN; + uint8_t ShutOffTXV2_EN; + uint8_t EN_BATTChiller; + uint8_t EN_PowerReserve; +} tPowerEnable_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_BCM_VEH_STATE_Bus_ +#define DEFINED_TYPEDEF_FOR_BCM_VEH_STATE_Bus_ + +typedef struct { + uint8_t BCM_T15_Stat; + uint8_t BCM_T30d_Stat; + uint8_t BCM_T30i_Stat; + uint8_t BCM_T15h_Stat; + uint8_t BCM_SPV_Feature_Stat; + uint8_t StealthModeEn; + uint8_t BCM_VehicleType_Stat; + uint8_t BCM_VehicleBody_Stat; + uint8_t BCM_ADASTerm_Stat; + uint8_t BCM_CCTerm_Stat; + uint8_t BCM_T30i_DisableWarning; + uint8_t BCM_LightBCM_Stat; + uint8_t HUD_IntensityRequest; + uint8_t BCM_T30d_DisableWarning; + uint8_t BCM_Light_Stat; + uint8_t BCM_IndFadingTime_Req_ro; + uint8_t BCM_CCTermDisableWarning; + uint8_t BCM_PreheatFunction_Stat; + uint8_t BCM_VehiclePowertrain_Stat; + uint8_t BCM_SwBackIntens_Val_ro; + uint8_t BCM_VehicleMode_Stat; + uint8_t BCM_SwIndIntens_Stat; + uint8_t BCM_Vehicle_DrvMode; + uint8_t BCM_LVBatteryVoltage_ro; +} BCM_VEH_STATE_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_CCUCAN_EMS_HVC_Req_Msg_Bus_ +#define DEFINED_TYPEDEF_FOR_CCUCAN_EMS_HVC_Req_Msg_Bus_ + +typedef struct { + uint8_t EMS_eCompHVRequest_Stat; + uint8_t EMS_eCompOnPerm; + uint8_t EMS_eCompChiller_Req; + uint16_t EMS_eCompHVCurLimit_Val_ro; + uint8_t EMS_HVC_Req_RC; + uint8_t EMS_HVC_Req_CS; +} CCUCAN_EMS_HVC_Req_Msg_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_dbg_Logic_Ac_Bus_ +#define DEFINED_TYPEDEF_FOR_dbg_Logic_Ac_Bus_ + +typedef struct { + uint8_t Logic_Ac_Req_Front; + uint8_t Logic_Ac_Txv_Front; + uint8_t Logic_Ac_Txv_Rear; + uint8_t Logic_Ac_Req_Rear; + uint8_t Logic_Ac_Req_Chiller; + uint8_t Logic_Ac_Txv_Chiller; + uint8_t Logic_Ac_EvaCtrl; + uint8_t Logic_Ac_Comp_EmrStop_Reason; + uint8_t Logic_Ac_Comp_LimitRpm_ro; + uint8_t Logic_Ac_Txv_Closed_bySen; + uint8_t Logic_Ac_Comp_Protection_Level; + uint8_t Logic_Ac_WinterSts_Front; + uint8_t Logic_Ac_WinterSts_Rear; +} dbg_Logic_Ac_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_CCU_HVC_Req_Msg_Bus_ +#define DEFINED_TYPEDEF_FOR_CCU_HVC_Req_Msg_Bus_ + +typedef struct { + uint8_t CCU_eCompSpeedReq_Val_ro; + uint8_t CCU_eCompReq_Stat; + uint8_t CCU_LowTempValve_Req; + uint8_t CCU_HVC_Req_RC; + uint8_t CCU_HVC_Req_CS; +} CCU_HVC_Req_Msg_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_CmdBusStatus_ +#define DEFINED_TYPEDEF_FOR_CmdBusStatus_ + +typedef struct { + int8_t Battery; + int16_t AMB; + int16_t Incar_FL; + int16_t Incar_FR; + int16_t Incar_RL; + int16_t Incar_RR; + int16_t Eva_F; + int16_t Eva_R; + int16_t Pressure; + int16_t Duct_FL_Upper; + int16_t Duct_FL_Lower; + int16_t Duct_FR_Upper; + int16_t Duct_FR_Lower; + int16_t Duct_RL; + int16_t Duct_RR; + int16_t Duct_Side_FL; + int16_t Duct_Side_FR; + int16_t Duct_Side_RL; + int16_t Duct_Side_RR; + int8_t AQS; +} CmdBusStatus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_CmdBusADCDataKey_ +#define DEFINED_TYPEDEF_FOR_CmdBusADCDataKey_ + +typedef struct { + uint8_t ST_ReservePower; + uint8_t ST_BATTChiller; + uint8_t EmergencyAirCleanSwitch; + uint8_t FireExtinguishSwitch; + uint8_t Ign_Wakeup; +} CmdBusADCDataKey; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_CCUCAN_TM_CP_Bus_ +#define DEFINED_TYPEDEF_FOR_CCUCAN_TM_CP_Bus_ + +typedef struct { + uint8_t CCPR_TVPowerSw_Stat; + uint8_t CCPF_RWindowHeatSw_Stat; + uint8_t CCPF_FWindowHeatSw_Stat; + uint8_t CCPR_SrcChgSw_Stat; + uint8_t CCPR_DWClaritySw_Stat; + uint8_t CCPR_IntercomSw_Stat; + uint8_t CCPR_DWCntrlSw_Stat; + uint8_t CCPF_MuteSw_Stat; + uint8_t CCPF_VolAjustSw_Stat; + uint8_t CCPR_PanoramicViewSw_Stat; + uint8_t CCPF_AutoButtonR_Stat; + uint8_t CCPR_AutoButtonL_Stat; + uint8_t CCPR_AutoButtonR_Stat; + uint8_t CCPF_DefButton_Stat; + uint8_t CCPF_TempToggleR_Stat; + uint8_t CCPF_TempToggleL_Stat; + uint8_t CCPF_AutoButtonL_Stat; + uint8_t CCPR_TempToggleR_Stat; + uint8_t CCPR_TempToggleL_Stat; + uint8_t CCPF_RecButton_Stat; + uint8_t CCPF_AcMaxButton_Stat; + uint8_t CCPR_TabletOffSw_Stat; + uint8_t CCPR_TabletExtractSw_Stat; +} CCUCAN_TM_CP_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_HVC_Err_Status_Msg_Bus_ +#define DEFINED_TYPEDEF_FOR_HVC_Err_Status_Msg_Bus_ + +typedef struct { + uint8_t HVC_CompSpeed_Val_ro; + uint8_t HVC_Comp_Stat; + uint8_t HVC_Reserved01; + uint8_t HVC_CompInputV_Val_ro; + uint8_t HVC_CompInputC_Val_ro; + uint8_t HVC_CompInvTemp_Val_ro; + uint8_t HVC_CompPhaseC_Val_ro; + uint8_t HVC_CompUV_Stat; + uint8_t HVC_CompOV_Stat; + uint8_t HVC_CompOvHeat_Stat; + uint8_t HVC_CompOvTorque_Stat; + uint8_t HVC_CompLowVoltErr_Stat; + uint8_t HVC_CompComErr_Stat; + uint8_t HVC_Reserved02; + uint8_t HVC_CompTempSensErr_Stat; + uint8_t HVC_CompCurrSensErr_Stat; + uint8_t HVC_CompCurrShortCirc_Stat; + uint8_t HVC_CompInPowSupply_Stat; + uint8_t HVC_CompTorqueStallErr_Stat; + uint8_t HVC_CompVoltSensErr_Stat; + uint8_t HVC_Reserved03; +} HVC_Err_Status_Msg_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_dbgCAN_CCU_IO_Bus_ +#define DEFINED_TYPEDEF_FOR_dbgCAN_CCU_IO_Bus_ + +typedef struct { + uint8_t dbg_IO_Txv_F; + uint8_t dbg_IO_Txv_R; + uint8_t dbg_IO_Txv_Ch; + uint8_t dbg_IO_2WayValve; + uint8_t dbg_IO_IncarMotor_F; + uint8_t dbg_IO_IncarMotor_R; + uint8_t dbg_SetTemp_FL_ro; + uint8_t dbg_SetTemp_FR_ro; + uint8_t dbg_SetTemp_RL_ro; + uint8_t dbg_SetTemp_RR_ro; + uint8_t dbg_IO_Input_Emergency; + uint8_t dbg_IO_Input_FireExtinguisher; + uint8_t dbg_IO_Install_Sealing_Valve; +} dbgCAN_CCU_IO_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_CCU_Msg3_Bus_ +#define DEFINED_TYPEDEF_FOR_CCU_Msg3_Bus_ + +typedef struct { + uint8_t CCU_FAN_Req; + uint8_t CCU_RestMode_Stat; + uint8_t CCU_IncarTempSum_Val_ro; + uint8_t CCU_MSG3_RC; + uint8_t CCU_MSG3_CS; +} CCU_Msg3_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_CCUCAN_OCURL_MSG_Bus_ +#define DEFINED_TYPEDEF_FOR_CCUCAN_OCURL_MSG_Bus_ + +typedef struct { + uint8_t OCURL_OccupantWeight_Stat; + uint8_t OCURL_SeatOccupied_Stat; + uint8_t OCURL_SensorError_Stat; + uint8_t OCURL_MSG_RC; + uint8_t OCURL_MSG_CS; +} CCUCAN_OCURL_MSG_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_dbgCAN_Logic_Rec_Bus_ +#define DEFINED_TYPEDEF_FOR_dbgCAN_Logic_Rec_Bus_ + +typedef struct { + uint8_t Logic_Rec_Idx; + uint8_t Logic_Rec_Partial_Spd_Sts; + uint8_t Logic_Rec_Partial_Winter; + uint8_t Logic_Rec_Partial_Summer; + uint8_t Logic_Rec_FreshAirPurge_Sts; +} dbgCAN_Logic_Rec_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_dbgCAN_Logic_State_Bus_ +#define DEFINED_TYPEDEF_FOR_dbgCAN_Logic_State_Bus_ + +typedef struct { + uint8_t Logic_Operation_Mode; + uint8_t Logic_Amb_Level; + uint8_t Logic_AutoDemist_Electric; + uint8_t Logic_AutoDemist_Garage; + uint8_t Logic_AutoDemist_Lv_Summer; + uint8_t Logic_RemoteStart; + uint8_t Logic_Rest_Mode; + uint8_t Logic_LoHi_Front; + uint8_t Logic_LoHi_Rear; + uint8_t Logic_2WayValve_Status; + uint8_t Logic_Full_Auto_FL; + uint8_t Logic_Full_Auto_FR; + uint8_t Logic_Full_Auto_RL; + uint8_t Logic_Full_Auto_RR; + uint8_t Logic_Full_MaxAc; + uint8_t Logic_Full_MaxDef; + uint8_t Logic_Start_Ctrl_Front; + uint8_t Logic_Start_Ctrl_Rear; + uint8_t Logic_Valve_Use_DiffBlr_R2; + uint8_t Logic_Duct_WaitCorrection_FRL; + uint8_t Logic_Duct_WaitCorrection_FLL; + uint8_t Logic_AutoDemist_Lv_Winter; + uint8_t Logic_AF_WaitCorrection_FL; + uint8_t Logic_AF_WaitCorrection_FR; +} dbgCAN_Logic_State_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_CCU_Msg1_Bus_ +#define DEFINED_TYPEDEF_FOR_CCU_Msg1_Bus_ + +typedef struct { + uint8_t CCU_MirrorHeating_Req; + uint8_t CCU_RecirculationLed_Cmd; + uint8_t CCU_DefrostLed_Req; + uint8_t CCU_SideWindowHeating_Req; + uint8_t CCU_RearWindowHeating_Req; + uint8_t CCU_FrontWindowHeating_Req; + uint8_t CCU_EmergAirCleaning_Stat; + uint8_t CCU_FireExtinguishSys_Stat; + uint8_t CCU_FLAutoPsngrLed_Cmd; + uint8_t CCU_FRAutoPsngrLed_Cmd; + uint8_t CCU_RLAutoPsngrLed_Cmd; + uint8_t CCU_RRAutoPsngrLed_Cmd; + uint8_t CCU_AC_MaxLed_Cmd; + uint8_t CCU_MSG1_RC; + uint8_t CCU_MSG1_CS; +} CCU_Msg1_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_dbg_Auto_AF_Bus_ +#define DEFINED_TYPEDEF_FOR_dbg_Auto_AF_Bus_ + +typedef struct { + uint8_t dbg_Auto_AF_MultMsg_Idx; + int16_t dbg_Auto_AF_Correct_FL; + int16_t dbg_Auto_AF_Correct_FR; + int16_t dbg_Auto_AF_Correct_RL; + int16_t dbg_Auto_AF_Correct_RR; + int16_t dbg_Auto_AF_Vtg_RL; + int16_t dbg_Auto_AF_Vtg_FL; + int16_t dbg_Auto_AF_Vtg_FR; + int16_t dbg_Auto_AF_Vtg_RR; + int16_t dbg_Auto_AF_Incar_RL; + int16_t dbg_Auto_AF_Incar_FR; + int16_t dbg_Auto_AF_Incar_RR; + int16_t dbg_Auto_AF_Incar_FL; + int16_t dbg_Auto_AF_Amb_RL; + int16_t dbg_Auto_AF_Amb_FR; + int16_t dbg_Auto_AF_Sun_RR; + int16_t dbg_Auto_AF_Amb_FL; + int16_t dbg_Auto_AF_Sun_FR; + int16_t dbg_Auto_AF_Sun_RL; + int16_t dbg_Auto_AF_Amb_RR; + int16_t dbg_Auto_AF_Sun_FL; +} dbg_Auto_AF_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_dbg_Auto_Duct_Bus_ +#define DEFINED_TYPEDEF_FOR_dbg_Auto_Duct_Bus_ + +typedef struct { + uint8_t dbg_Auto_Duct_MultMsg_Idx; + int16_t dbg_Auto_Duct_Tgt_FL_Upper_ro; + int16_t dbg_Auto_Duct_Tg_Incar_FL_Upper_ro; + int16_t dbg_Auto_Duct_Tgt_RR_ro; + int16_t dbg_Auto_Duct_Tgt_RL_ro; + int16_t dbg_Auto_Duct_Tgt_FR_Upper_ro; + int16_t dbg_Auto_Duct_Tgt_FR_Lower_ro; + int16_t dbg_Auto_Duct_Tgt_FL_Lower_ro; + int16_t dbg_Auto_Duct_Tg_Incar_FR_Upper_ro; + int16_t dbg_Auto_Duct_Tg_FL_Upper_ro; + int16_t dbg_Auto_Duct_Tg_FL_Lower_ro; + int16_t dbg_Auto_Duct_Tg_FR_Lower_ro; + int16_t dbg_Auto_Duct_Tg_FR_Upper_ro; + int16_t dbg_Auto_Duct_Tg_RL_ro; + int16_t dbg_Auto_Duct_Tg_RR_ro; + int16_t dbg_Auto_Duct_Tg_Incar_FL_Lower_ro; + int16_t dbg_Auto_Duct_Incar_FL_Lower_ro; + int16_t dbg_Auto_Duct_Incar_RR_ro; + int16_t dbg_Auto_Duct_Incar_RL_ro; + int16_t dbg_Auto_Duct_Incar_FR_Upper_ro; + int16_t dbg_Auto_Duct_Incar_FR_Lower_ro; + int16_t dbg_Auto_Duct_Incar_FL_Upper_ro; + int16_t dbg_Auto_Duct_Tg_Incar_FR_Lower_ro; + int16_t dbg_Auto_Duct_Amb_RL_ro; + int16_t dbg_Auto_Duct_Amb_FR_Upper_ro; + int16_t dbg_Auto_Duct_Amb_FR_Lower_ro; + int16_t dbg_Auto_Duct_Amb_RR_ro; + int16_t dbg_Auto_Duct_Amb_FL_Lower_ro; + int16_t dbg_Auto_Duct_Amb_FL_Upper_ro; + int16_t dbg_Auto_Duct_Tg_Incar_RL_ro; + int16_t dbg_Auto_Duct_Sun_FL_Lower_ro; + int16_t dbg_Auto_Duct_Sun_FR_Lower_ro; + int16_t dbg_Auto_Duct_Sun_FR_Upper_ro; + int16_t dbg_Auto_Duct_Sun_RL_ro; + int16_t dbg_Auto_Duct_Sun_FL_Upper_ro; + int16_t dbg_Auto_Duct_Sun_RR_ro; + int16_t dbg_Auto_Duct_Tg_Incar_RR_ro; +} dbg_Auto_Duct_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_CmdCAN_CCU_STAT1_WakeUp_Bus_ +#define DEFINED_TYPEDEF_FOR_CmdCAN_CCU_STAT1_WakeUp_Bus_ + +typedef struct { + uint8_t CCU_ModeFL_Stat; + uint8_t CCU_ModeFR_Stat; + uint8_t CCU_ModeRL_Stat; + uint8_t CCU_ModeRR_Stat; + uint8_t CCU_AutoModeFL_Stat; + uint8_t CCU_AutoModeFR_Stat; + uint8_t CCU_AirDirectionRL_Face_Stat; + uint8_t CCU_AirDirectionRL_Foot_Stat; + uint8_t CCU_AutoModeRL_Stat; + uint8_t CCU_AutoModeRR_Stat; + uint8_t CCU_AirDirectionRR_Face_Stat; + uint8_t CCU_AirDirectionRR_Foot_Stat; + uint8_t CCU_AirDirectionFL_Def_Stat; + uint8_t CCU_AirDirectionFL_Face_Stat; + uint8_t CCU_AirDirectionFL_Foot_Stat; + uint8_t CCU_AirDirectionFR_Def_Stat; + uint8_t CCU_AirDirectionFR_Face_Stat; + uint8_t CCU_AirDirectionFR_Foot_Stat; + uint8_t CCU_Recirculation_Stat; + uint8_t CCU_BlowerSpeedFL_Stat; + uint8_t CCU_TargetTempFL_Stat_ro; + uint8_t CCU_BlowerSpeedFR_Stat; + uint8_t CCU_TargetTempFR_Stat_ro; + uint8_t CCU_BlowerSpeedRL_Stat; + uint8_t CCU_TargetTempRR_Stat_ro; + uint8_t CCU_BlowerSpeedRR_Stat; + uint8_t CCU_TargetTempRL_Stat_ro; +} CmdCAN_CCU_STAT1_WakeUp_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_LIN5_SENSON_ADR_Stat_Bus_ +#define DEFINED_TYPEDEF_FOR_LIN5_SENSON_ADR_Stat_Bus_ + +typedef struct { + uint8_t in_COUNT[8]; + uint8_t in_error_connect[8]; + uint8_t LinRespErr_Stat[8]; + uint8_t Err_Stat[8]; + uint8_t Error_Connect; +} LIN5_SENSON_ADR_Stat_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_LIN4_AirQS_Stat_Bus_ +#define DEFINED_TYPEDEF_FOR_LIN4_AirQS_Stat_Bus_ + +typedef struct { + uint8_t AirQS_LinRespErr_Stat; + uint8_t AirQS_Sens_Stat; + uint8_t AirQS_Combined_Stat; + uint8_t AirQS_Err_Stat; + uint8_t AirQS_COLvl_Stat; + uint8_t AirQS_NOxLvl_Stat; + uint8_t AirQS_NH3Lvl_Stat; +} LIN4_AirQS_Stat_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_LIN4_Aroma_Stat_Bus_ +#define DEFINED_TYPEDEF_FOR_LIN4_Aroma_Stat_Bus_ + +typedef struct { + uint8_t Aroma_LinRespErr_Stat; + uint8_t Aroma_CartridgeSw_Stat; + uint8_t Aroma_Err_Stat; + uint8_t Aroma_Intens_Stat; + uint8_t Aroma_CartridgeFlavor_Stat; + uint8_t Aroma_CartridgeCapacity_Stat; +} LIN4_Aroma_Stat_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_LIN4_Ionizer_Stat_Bus_ +#define DEFINED_TYPEDEF_FOR_LIN4_Ionizer_Stat_Bus_ + +typedef struct { + uint8_t Ionizer_LinRespErr_Stat; + uint8_t Ionizer_Err_Stat; + uint8_t Ionizer_Ionization_Stat; +} LIN4_Ionizer_Stat_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_LIN4_eTXV_fHVAC_Stat_Bus_ +#define DEFINED_TYPEDEF_FOR_LIN4_eTXV_fHVAC_Stat_Bus_ + +typedef struct { + uint8_t eTXV_fHVAC_Pos_Stat; + uint8_t eTXV_fHVAC_LinRespErr_Stat; + uint8_t eTXV_fHVAC_Err_Stat; + uint8_t eTXV_fHVAC_Pressure_Val; + uint8_t eTXV_fHVAC_Temp_Val; +} LIN4_eTXV_fHVAC_Stat_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_LIN4_eTXV_rHVAC_Stat_Bus_ +#define DEFINED_TYPEDEF_FOR_LIN4_eTXV_rHVAC_Stat_Bus_ + +typedef struct { + uint8_t eTXV_rHVAC_Pos_Stat; + uint8_t eTXV_rHVAC_LinRespErr_Stat; + uint8_t eTXV_rHVAC_Err_Stat; + uint8_t eTXV_rHVAC_Pressure_Val; + uint8_t eTXV_rHVAC_Temp_Val; +} LIN4_eTXV_rHVAC_Stat_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_LIN4_eTXV_batChiller_Stat_Bus_ +#define DEFINED_TYPEDEF_FOR_LIN4_eTXV_batChiller_Stat_Bus_ + +typedef struct { + uint8_t eTXV_batChiller_Pos_Stat; + uint8_t eTXV_batChiller_LinRespErr_Stat; + uint8_t eTXV_batChiller_Err_Stat; + uint8_t eTXV_batChiller_Pressure_Val; + uint8_t eTXV_batChiller_Temp_Val; +} LIN4_eTXV_batChiller_Stat_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_LIN4_CCU_Req_Bus_ +#define DEFINED_TYPEDEF_FOR_LIN4_CCU_Req_Bus_ + +typedef struct { + uint8_t CCU_Ionization_Req; + uint8_t CCU_AromaIntens_Req; + uint8_t CCU_AirQS_Req; + uint8_t CCU_fHVAC_Pos_Val; + uint8_t CCU_rHVAC_Pos_Val; + uint8_t CCU_batChiller_Pos_Val; + uint8_t CCU_eeChiller_Pos_Val; +} LIN4_CCU_Req_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_dbg_Logic_Valve_Bus_ +#define DEFINED_TYPEDEF_FOR_dbg_Logic_Valve_Bus_ + +typedef struct { + uint8_t Logic_Valve_Index_FL; + uint8_t Logic_Valve_Index_FR; + uint8_t Logic_Valve_Index_RL; + uint8_t Logic_Valve_Index_RR; + uint8_t Logic_Valve_Direction_FL; + uint8_t Logic_Valve_Direction_FR; + uint8_t Logic_Valve_Direction_RL; + uint8_t Logic_Valve_Direction_RR; +} dbg_Logic_Valve_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_LIN4_eTXV_eeChiller_Stat_Bus_ +#define DEFINED_TYPEDEF_FOR_LIN4_eTXV_eeChiller_Stat_Bus_ + +typedef struct { + uint8_t eTXV_eeChiller_Pos_Stat; + uint8_t eTXV_eeChiller_LinRespErr_Stat; + uint8_t eTXV_eeChiller_Err_Stat; + uint8_t eTXV_eeChiller_Pressure_Val; + uint8_t eTXV_eeChiller_Temp_Val; +} LIN4_eTXV_eeChiller_Stat_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_ActuatorCmdBus_ +#define DEFINED_TYPEDEF_FOR_ActuatorCmdBus_ + +typedef struct { + uint16_t POS[9]; + uint8_t BUS_ADR[9]; + uint8_t MODE[9]; + uint8_t COM[9]; + uint8_t Stall_SET[9]; + uint8_t Lnoise_SET[9]; + uint8_t Autos_SET[9]; + uint8_t Speed_SET[9]; + uint8_t Coils_Stop_SET[9]; +} ActuatorCmdBus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_dbg_LIN_DRS_Stat_t_Bus_ +#define DEFINED_TYPEDEF_FOR_dbg_LIN_DRS_Stat_t_Bus_ + +typedef struct { + uint8_t LIN_DRS_DLLed1; + uint8_t LIN_DRS_DLLed2; + uint8_t LIN_DRS_DLLed3; + uint8_t LIN_DRS_DRLed1; + uint8_t LIN_DRS_DRLed2; + uint8_t LIN_DRS_DRLed3; + uint8_t LIN_DRS_FPLLed1; + uint8_t LIN_DRS_FPLLed2; + uint8_t LIN_DRS_FPLLed3; + uint8_t LIN_DRS_FPRLed1; + uint8_t LIN_DRS_FPRLed2; + uint8_t LIN_DRS_FPRLed3; + uint8_t LIN_DRS_RLBLed1; + uint8_t LIN_DRS_RLBLed2; + uint8_t LIN_DRS_RLBLed3; + uint8_t LIN_DRS_RRBLed1; + uint8_t LIN_DRS_RRBLed2; + uint8_t LIN_DRS_RRBLed3; + uint8_t LIN_DRS_FCLLed1; + uint8_t LIN_DRS_FCLLed2; + uint8_t LIN_DRS_FCLLed3; + uint8_t LIN_DRS_FCRLed1; + uint8_t LIN_DRS_FCRLed2; + uint8_t LIN_DRS_FCRLed3; + uint8_t LIN_DRS_BCM_IndFadingTime_ro; + uint8_t LIN_DRS_BCM_SwIndIntens; +} dbg_LIN_DRS_Stat_t_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_dbg_LIN_AirQS_Stat_t_Bus_ +#define DEFINED_TYPEDEF_FOR_dbg_LIN_AirQS_Stat_t_Bus_ + +typedef struct { + uint8_t LIN_AirQS_LinRespErr_Stat; + uint8_t LIN_AirQualSen_Stat; + uint8_t LIN_AirQualSenCombined_Val; + uint8_t LIN_AirQualSen_Error_Stat; + uint8_t LIN_AirQualSenCOlvl_Val; + uint8_t LIN_AirQualSenNOxlvl_Val; + uint8_t LIN_AirQualSenNH3lvl_Val; +} dbg_LIN_AirQS_Stat_t_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_dbg_Drs_t_Bus_ +#define DEFINED_TYPEDEF_FOR_dbg_Drs_t_Bus_ + +typedef struct { + uint8_t dbg_Drs_0_SFL_DL; + uint8_t dbg_Drs_1_CFL_FPL; + uint8_t dbg_Drs_2_CFR_FPR; + uint8_t dbg_Drs_3_SFR_DR; + uint8_t dbg_Drs_4_SRL_RLB; + uint8_t dbg_Drs_5_CRL_FCL; + uint8_t dbg_Drs_6_CRR_FCR; + uint8_t dbg_Drs_7_SRR_RRB; +} dbg_Drs_t_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_dbg_Logic_Valve_Plus_Bus_ +#define DEFINED_TYPEDEF_FOR_dbg_Logic_Valve_Plus_Bus_ + +typedef struct { + int16_t dbg_Auto_Valve_Plus_Vent_SFL_ro; + int16_t dbg_Auto_Valve_Plus_Vent_CFL_ro; + int16_t dbg_Auto_Valve_Plus_Foot_FL_ro; + int16_t dbg_Auto_Valve_Plus_Vent_SFR_ro; + int16_t dbg_Auto_Valve_Plus_Vent_CFR_ro; + int16_t dbg_Auto_Valve_Plus_Foot_FR_ro; +} dbg_Logic_Valve_Plus_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_CmdBusError_ +#define DEFINED_TYPEDEF_FOR_CmdBusError_ + +typedef struct { + uint8_t CCU_IncarTempErrF_Stat; + uint8_t CCU_IncarTempErrR_Stat; + uint8_t CCU_DuctTempSenErrF_Stat; + uint8_t CCU_DuctTempSenErrR_Stat; + uint8_t CCU_EvaTempSenErrF_Stat; + uint8_t CCU_EvaTempSenErrR_Stat; + uint8_t CCU_DeflectorSwErrF_Stat; + uint8_t CCU_DeflectorSwErrR_Stat; + uint8_t CCU_PressSenErr_Stat; + uint8_t CCU_AmbienTemptSenErr_Stat; + uint8_t CCU_SealingValveErr_Stat; + uint8_t CCU_ETXVerr_Stat; + uint8_t CCU_HVACfanOrTXVerrF_Stat; + uint8_t CCU_HVACfanOrTXVerrR_Stat; + uint8_t CCU_ActuatorErrF_Stat; + uint8_t CCU_ActuatorErrR_Stat; + uint8_t CCU_UltravioletErr_Stat; + uint8_t CCU_VinRecordErr_Stat; + uint8_t CCU_AirQualSenErr_Stat; + uint8_t CCU_CommErr_Stat; + uint8_t CCU_TWVerr_Stat; + uint8_t CCU_IonizationErr_Stat; + uint8_t CCU_AromaErr_Stat; +} CmdBusError; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_CCUCAN_OCURR_MSG_Bus_ +#define DEFINED_TYPEDEF_FOR_CCUCAN_OCURR_MSG_Bus_ + +typedef struct { + uint8_t OCURR_OccupantWeight_Stat; + uint8_t OCURR_SeatOccupied_Stat; + uint8_t OCURR_SensorError_Stat; + uint8_t OCURR_MSG_RC; + uint8_t OCURR_MSG_CS; +} CCUCAN_OCURR_MSG_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_LIN4_ERROR_Bus_ +#define DEFINED_TYPEDEF_FOR_LIN4_ERROR_Bus_ + +typedef struct { + uint8_t in_error_connect[7]; + uint8_t Error_Connect; +} LIN4_ERROR_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_CmdCAN_CCU_STAT3_Bus_ +#define DEFINED_TYPEDEF_FOR_CmdCAN_CCU_STAT3_Bus_ + +typedef struct { + uint8_t CCU_AromaCartridgeCapacity_Stat_ro; + uint8_t CCU_AromaCartridgeFlavor_Stat; + uint8_t CCU_AromaFaultReason_Stat; + uint8_t CCU_RLfootBlowDis_Stat; + uint8_t CCU_RRfootBlowDis_Stat; + uint8_t CCU_RestMode2_Stat; +} CmdCAN_CCU_STAT3_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_dbg_LIN_Ionizer_Stat_t_Bus_ +#define DEFINED_TYPEDEF_FOR_dbg_LIN_Ionizer_Stat_t_Bus_ + +typedef struct { + uint8_t LIN_Ionizer_Err_Stat; + uint8_t LIN_Ionizer_LinRespErr; + uint8_t LIN_Ionizer_Ionization; +} dbg_LIN_Ionizer_Stat_t_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_dbg_LIN_Aroma_Stat_t_Bus_ +#define DEFINED_TYPEDEF_FOR_dbg_LIN_Aroma_Stat_t_Bus_ + +typedef struct { + uint8_t LIN_AromaLinRespErr_Stat; + uint8_t LIN_Aroma_1CartridgeSw; + uint8_t LIN_Aroma_2CartridgeSw; + uint8_t LIN_Aroma_3CartridgeSw; + uint8_t LIN_Aroma_Error_Stat; + uint8_t LIN_Aroma_Intens; + uint8_t LIN_Aroma_CartridgeSel; + uint8_t LIN_Aroma_1CartridgeFlavor; + uint8_t LIN_Aroma_2CartridgeFlavor; + uint8_t LIN_Aroma_3CartridgeFlavor; + uint8_t LIN_Aroma_1CartridgeCapacity; + uint8_t LIN_Aroma_2CartridgeCapacity; + uint8_t LIN_Aroma_3CartridgeCapacity; +} dbg_LIN_Aroma_Stat_t_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_CmdCAN_CCU_STAT2_WakeUp_Bus_ +#define DEFINED_TYPEDEF_FOR_CmdCAN_CCU_STAT2_WakeUp_Bus_ + +typedef struct { + uint8_t CCU_AromaCartridgeSw_Stat; + uint8_t CCU_FrontZoneSync_Stat; + uint8_t CCU_RearZoneSync_Stat; + uint8_t CCU_AllZoneSync_Stat; + uint8_t CCU_ACfront_Stat; + uint8_t CCU_ACrear_Stat; + uint8_t CCU_ACmaxF_Stat; + uint8_t CCU_ACmaxR_Stat; + uint8_t CCU_Defrost_Stat; + uint8_t CCU_Ionization_Stat; + uint8_t CCU_FootTempCorFL_Stat; + uint8_t CCU_FootTempCorFR_Stat; + uint8_t CCU_AromaIntens_Stat; + uint8_t CCU_FootTempCorRL_Stat; + uint8_t CCU_FootTempCorRR_Stat; + uint8_t CCU_DeflectorSwDL_Stat; + uint8_t CCU_DeflectorSwDR_Stat; + uint8_t CCU_DeflectorSwFPL_Stat; + uint8_t CCU_DeflectorSwFPR_Stat; + uint8_t CCU_DeflectorSwFCL_Stat; + uint8_t CCU_DeflectorSwFCR_Stat; + uint8_t CCU_DeflectorSwRLB_Stat; + uint8_t CCU_DeflectorSwRRB_Stat; +} CmdCAN_CCU_STAT2_WakeUp_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_CmdCAN_CCU_STAT3_WakeUp_Bus_ +#define DEFINED_TYPEDEF_FOR_CmdCAN_CCU_STAT3_WakeUp_Bus_ + +typedef struct { + uint8_t CCU_AromaCartridgeCapacity_Stat_ro; + uint8_t CCU_AromaCartridgeFlavor_Stat; + uint8_t CCU_AromaFaultReason_Stat; + uint8_t CCU_RLfootBlowDis_Stat; + uint8_t CCU_RRfootBlowDis_Stat; + uint8_t CCU_RestMode2_Stat; +} CmdCAN_CCU_STAT3_WakeUp_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_CCU_Msg1_WakeUp_Bus_ +#define DEFINED_TYPEDEF_FOR_CCU_Msg1_WakeUp_Bus_ + +typedef struct { + uint8_t CCU_MirrorHeating_Req; + uint8_t CCU_RecirculationLed_Cmd; + uint8_t CCU_DefrostLed_Req; + uint8_t CCU_SideWindowHeating_Req; + uint8_t CCU_RearWindowHeating_Req; + uint8_t CCU_FrontWindowHeating_Req; + uint8_t CCU_EmergAirCleaning_Stat; + uint8_t CCU_FireExtinguishSys_Stat; + uint8_t CCU_FLAutoPsngrLed_Cmd; + uint8_t CCU_FRAutoPsngrLed_Cmd; + uint8_t CCU_RLAutoPsngrLed_Cmd; + uint8_t CCU_RRAutoPsngrLed_Cmd; + uint8_t CCU_AC_MaxLed_Cmd; + uint8_t CCU_MSG1_RC; + uint8_t CCU_MSG1_CS; +} CCU_Msg1_WakeUp_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_CmdBusADCData_ +#define DEFINED_TYPEDEF_FOR_CmdBusADCData_ + +typedef struct { + uint16_t Sensor_Ambient_Temp; + uint16_t IGN_ANS; + uint16_t Sensor_AC_Pressure; + uint16_t Sensor_Incar_Temp_FL; + uint16_t Sensor_Incar_Temp_RL; + uint16_t Sensor_Rear_Evap_Temp; + uint16_t Sensor_Evap_Temp; + uint16_t Sensor_Rear_Duct1; + uint16_t Sensor_Rear_Duct2; + uint16_t Sensor_Front_Duct1; + uint16_t Sensor_Front_Duct2; + uint16_t Sensor_Front_Duct3; + uint16_t Sensor_Front_Duct4; + uint16_t Sensor_Rear_Duct3; + uint16_t Sensor_Rear_Duct4; + uint16_t Sensor_Incar_Temp_FR; + uint16_t Sensor_Incar_Temp_RR; + uint16_t Sensor_Rear_Duct5; + uint16_t Sensor_Rear_Duct6; + uint16_t Reserve_Sensor_Duct_Temp_1; + uint16_t Sensor_Front_Duct5; + uint16_t Sensor_Front_Duct6; + uint16_t BTS5120_2EKA_ShutoffValvePowerTXV1; + uint16_t BTS5120_2EKA_ShutoffValvePowerTXV2; + uint16_t Pressure_DIAG; + uint16_t BTS5180_2EKA_ShutOFFValveFront; + uint16_t BTS5180_2EKA_ShutOFFValveRear; + uint16_t BTS5180_2EKA_TwoWayValve; + uint16_t BTS5180_2EKA_ReservePowerSupply; + uint16_t BTS5180_2EKA_FrontIncarMotor; + uint16_t BTS5180_2EKA_RearIncarMotor; + uint16_t BTS5180_2EKA_ChannelPTCPower1; + uint16_t BTS5180_2EKA_ChannelPTCPower2; + uint16_t Reserve_Sensor_Duct_Temp_2; + uint16_t VN7008AJ_DIAG_FrontLINActuatorPowerDriverAB; + uint16_t VN7008AJ_DIAG_RearLINActuatorPowerDriverC; + uint16_t PBATT_CHECK; + uint16_t VN7008AJ_FrontLINActuatorPowerDriverAB; + uint16_t VN7008AJ_RearLINActuatorPowerDriverC; +} CmdBusADCData; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_CmdCAN_FIU_CCU1_Bus_ +#define DEFINED_TYPEDEF_FOR_CmdCAN_FIU_CCU1_Bus_ + +typedef struct { + uint8_t FIU_TargetTempFL_Val_ro; + uint8_t FIU_FootTempCorFL_Req; + uint8_t FIU_TargetTempFR_Val_ro; + uint8_t FIU_FootTempCorFR_Req; + uint8_t FIU_CCmodeFL_Req; + uint8_t FIU_AirDirectionFL_Def_Req; + uint8_t FIU_AirDirectionFL_Face_Req; + uint8_t FIU_AirDirectionFL_Foot_Req; + uint8_t FIU_CCmodeFR_Req; + uint8_t FIU_AirDirectionFR_Def_Req; + uint8_t FIU_AirDirectionFR_Face_Req; + uint8_t FIU_AirDirectionFR_Foot_Req; + uint8_t FIU_BlowerSpeedFL_Req; + uint8_t FIU_BlowerSpeedFR_Req; + uint8_t FIU_CCautoModeFL_Req; + uint8_t FIU_CCautoModeFR_Req; + uint8_t FIU_Recirculation_Req; + uint8_t FIU_DeflectorSwDL_Req; + uint8_t FIU_DeflectorSwDR_Req; + uint8_t FIU_ACfrontOFF_Req; + uint8_t FIU_DeflectorSwFPL_Req; + uint8_t FIU_DeflectorSwFPR_Req; + uint8_t FIU_FrontZoneSync_Req; +} CmdCAN_FIU_CCU1_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_CmdCAN_FIU_CCU2_Bus_ +#define DEFINED_TYPEDEF_FOR_CmdCAN_FIU_CCU2_Bus_ + +typedef struct { + uint8_t FIU_TargetTempRL_Val_ro; + uint8_t FIU_FootTempCorRL_Req; + uint8_t FIU_TargetTempRR_Val_ro; + uint8_t FIU_FootTempCorRR_Req; + uint8_t FIU_CCmodeRL_Req; + uint8_t FIU_AirDirectionRL_Def_Req; + uint8_t FIU_AirDirectionRL_Face_Req; + uint8_t FIU_AirDirectionRL_Foot_Req; + uint8_t FIU_CCmodeRR_Req; + uint8_t FIU_AirDirectionRR_Def_Req; + uint8_t FIU_AirDirectionRR_Face_Req; + uint8_t FIU_AirDirectionRR_Foot_Req; + uint8_t FIU_BlowerSpeedRL_Req; + uint8_t FIU_BlowerSpeedRR_Req; + uint8_t FIU_CCautoModeRL_Req; + uint8_t FIU_CCautoModeRR_Req; + uint8_t FIU_DeflectorSwRLB_Req; + uint8_t FIU_DeflectorSwFCL_Req; + uint8_t FIU_ACrearOFF_Req; + uint8_t FIU_DeflectorSwFCR_Req; + uint8_t FIU_DeflectorSwRRB_Req; + uint8_t FIU_RearZoneSync_Req; +} CmdCAN_FIU_CCU2_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_CmdCAN_FIU_CCU3_Bus_ +#define DEFINED_TYPEDEF_FOR_CmdCAN_FIU_CCU3_Bus_ + +typedef struct { + uint8_t FIU_Aroma_Req; + uint8_t FIU_AromaIntens_Req; + uint8_t FIU_Rest_Req; + uint8_t FIU_Ionization_Req; + uint8_t FIU_RLfootBlowDis_Req; + uint8_t FIU_RRfootBlowDis_Req; + uint8_t FIU_ACmax_Req; + uint8_t FIU_Defrost_Req; + uint8_t FIU_Ultraviolet_Req; +} CmdCAN_FIU_CCU3_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_ActuatorCmdBusInput_ +#define DEFINED_TYPEDEF_FOR_ActuatorCmdBusInput_ + +typedef struct { + uint16_t in_CPOS_ALL[9]; + uint8_t in_Act_Emrf_Slave[9]; + uint8_t in_Mode_Slave[9]; + uint8_t in_Act_Err1_Supply[9]; + uint8_t in_Act_Err2_Communication[9]; + uint8_t in_Act_Err3_Temperature[9]; + uint8_t in_Act_Err4_Permanent_Electrical[9]; + uint8_t in_Act_Stall_Slave[9]; + uint8_t in_Act_Reset[9]; + uint8_t Busy; + uint8_t Error_Connect; +} ActuatorCmdBusInput; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_dbgCAN_dbg_Logic_Blower_Bus_ +#define DEFINED_TYPEDEF_FOR_dbgCAN_dbg_Logic_Blower_Bus_ + +typedef struct { + uint8_t Logic_Blower_Step_FL; + uint8_t Logic_Blower_Step_FR; + uint8_t Logic_Blower_Step_RL; + uint8_t Logic_Blower_Step_RR; + uint8_t Logic_Blower_Pwm_Front; + uint8_t Logic_Blower_Pwm_Rear; + uint8_t Logic_Blower_AF_FL; + uint8_t Logic_Blower_AF_FR; + uint8_t Logic_Blower_AF_RL; + uint8_t Logic_Blower_AF_RR; +} dbgCAN_dbg_Logic_Blower_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_dbgCAN_dbg_Act0_Bus_ +#define DEFINED_TYPEDEF_FOR_dbgCAN_dbg_Act0_Bus_ + +typedef struct { + uint8_t dbg_Act00_Def; + uint8_t dbg_Act01_Vent_SFL; + uint8_t dbg_Act02_Vent_CFL; + uint8_t dbg_Act03_Foot_1FL; + uint8_t dbg_Act04_Foot_2FL; + uint8_t dbg_Act05_Vent_CFR; + uint8_t dbg_Act06_Vent_SFR; + uint8_t dbg_Act07_Foot_1FR; +} dbgCAN_dbg_Act0_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_dbgCAN_dbg_Act1_Bus_ +#define DEFINED_TYPEDEF_FOR_dbgCAN_dbg_Act1_Bus_ + +typedef struct { + uint8_t dbg_Act08_Foot_2FR; + uint8_t dbg_Act09_Vent_SRL; + uint8_t dbg_Act10_Vent_CRL; + uint8_t dbg_Act11_Foot_RL; + uint8_t dbg_Act12_Vent_CRR; + uint8_t dbg_Act13_Vent_SRR; + uint8_t dbg_Act14_Foot_RR; + uint8_t dbg_Act15_TempU_FL; +} dbgCAN_dbg_Act1_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_dbgCAN_dbg_Act2_Bus_ +#define DEFINED_TYPEDEF_FOR_dbgCAN_dbg_Act2_Bus_ + +typedef struct { + uint8_t dbg_Act16_TempL_FL; + uint8_t dbg_Act17_TempU_FR; + uint8_t dbg_Act18_TempL_FR; + uint8_t dbg_Act19_Temp_RL; + uint8_t dbg_Act20_Temp_RR; + uint8_t dbg_Act21_Rec; + uint8_t dbg_Act22_OSA; + uint8_t dbg_Act23_SealingValve; +} dbgCAN_dbg_Act2_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_dbgCAN_dbg_Sen_Duct_Bus_ +#define DEFINED_TYPEDEF_FOR_dbgCAN_dbg_Sen_Duct_Bus_ + +typedef struct { + uint8_t dbg_Sen_Duct_MultMsg_Idx; + uint8_t dbg_Sen_Duct_FL_Fb_Select; + uint8_t dbg_Sen_Duct_RR_Fb_Select; + uint8_t dbg_Sen_Duct_RL_Fb_Select; + uint8_t dbg_Sen_Duct_FR_Fb_Select; + int16_t dbg_Sen_Duct_RL_Tgt_ro; + int16_t dbg_Sen_Duct_FR_Upper_Tgt_ro; + int16_t dbg_Sen_Duct_RR_Tgt_ro; + int16_t dbg_Sen_Duct_FL_Upper_Tgt_ro; + int16_t dbg_Sen_Duct_RR_Fb_ro; + int16_t dbg_Sen_Duct_RL_Fb_ro; + int16_t dbg_Sen_Duct_FR_Upper_Fb_ro; + int16_t dbg_Sen_Duct_FL_Upper_Fb_ro; + int16_t dbg_Sen_Duct_FR_Side_Fb_ro; + int16_t dbg_Sen_Duct_FL_Side_Fb_ro; + int16_t dbg_Sen_Duct_RL_Side_Fb_ro; + int16_t dbg_Sen_Duct_RR_Side_Fb_ro; + int16_t dbg_Sen_Duct_FR_Lower_Tgt_ro; + int16_t dbg_Sen_Duct_FL_Lower_Tgt_ro; + int16_t dbg_Sen_Duct_FR_Lower_Fb_ro; + int16_t dbg_Sen_Duct_FL_Lower_Fb_ro; +} dbgCAN_dbg_Sen_Duct_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_dbgCAN_dbg_dbg_Sen_Eva_Bus_ +#define DEFINED_TYPEDEF_FOR_dbgCAN_dbg_dbg_Sen_Eva_Bus_ + +typedef struct { + int16_t dbg_Sen_Eva_F; + int16_t dbg_Sen_Eva_R; + int16_t dbg_Sen_Eva_Target; + int16_t dbg_Sen_Eva_Diff_FrontRear; +} dbgCAN_dbg_dbg_Sen_Eva_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_Status_Duct_Tgt_Bus_ +#define DEFINED_TYPEDEF_FOR_Status_Duct_Tgt_Bus_ + +typedef struct { + uint16_t DuctTgt_Vent_FL; + uint16_t DuctTgt_Foot_FL; + uint16_t DuctTgt_Vent_FR; + uint16_t DuctTgt_Foot_FR; + uint16_t DuctTgt_RL; + uint16_t DuctTgt_RR; +} Status_Duct_Tgt_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_Status_Actuator_Bus_ +#define DEFINED_TYPEDEF_FOR_Status_Actuator_Bus_ + +typedef struct { + uint16_t Motor_Def; + uint16_t Motor_Vent_SFL; + uint16_t Motor_Vent_CFL; + uint16_t Motor_Foot_1FL; + uint16_t Motor_Foot_2FL; + uint16_t Motor_Vent_CFR; + uint16_t Motor_Vent_SFR; + uint16_t Motor_Foot_1FR; + uint16_t Motor_Foot_2FR; + uint16_t Motor_Vent_SRL; + uint16_t Motor_Vent_CRL; + uint16_t Motor_Foot_RL; + uint16_t Motor_Vent_CRR; + uint16_t Motor_Vent_SRR; + uint16_t Motor_Foot_RR; + uint16_t Motor_Temp1_FL; + uint16_t Motor_Temp2_FL; + uint16_t Motor_Temp1_FR; + uint16_t Motor_Temp2_FR; + uint16_t Motor_Temp_RL; + uint16_t Motor_Temp_RR; + uint16_t Motor_REC; + uint16_t Motor_OSA; + uint16_t Motor_SealingValve; +} Status_Actuator_Bus; + +#endif + +#ifndef DEFINED_TYPEDEF_FOR_Status_Sensor_Bus_ +#define DEFINED_TYPEDEF_FOR_Status_Sensor_Bus_ + +typedef struct { + uint8_t Ignition; + uint8_t Battery; + uint16_t AMB; + uint16_t Incar_FL; + uint16_t Incar_FR; + uint16_t Incar_RL; + uint16_t Incar_RR; + uint16_t Eva_F; + uint16_t Eva_R; + uint16_t Pressure; + uint16_t Duct_FL_Upper; + uint16_t Duct_FL_Lower; + uint16_t Duct_FR_Upper; + uint16_t Duct_FR_Lower; + uint16_t Duct_RL; + uint16_t Duct_RR; + uint16_t Duct_Side_FL; + uint16_t Duct_Side_FR; + uint16_t Duct_Side_RL; + uint16_t Duct_Side_RR; + uint8_t AQS; +} Status_Sensor_Bus; + +#endif + +/* Forward declaration for rtModel */ +typedef struct tag_RTM RT_MODEL; + +#endif /* HVAC_model_types_h_ */ + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/MODULES/HVAC_M7_MODEL/Model_Task.c b/MODULES/HVAC_M7_MODEL/Model_Task.c new file mode 100644 index 0000000..d18aa0d --- /dev/null +++ b/MODULES/HVAC_M7_MODEL/Model_Task.c @@ -0,0 +1,1026 @@ +// +// Created by cfif on 19.12.2025. +// +#include "Model_Task.h" +#include +#include +#include "HVAC_model.h" +#include "memory.h" +#include "SystemDelayInterface.h" +#include "fc7xxx_driver_smc.h" + +#define LOG_SIGN "ModelTask" +#define LOGGER env->logger + +//tStatus_Sensor_For_Model model_Status_Sensor_For_Model_input; +tStatus_Actuator_For_Model model_Status_Actuator_DoorsActuator_For_Model_input; +//tStatus_Duct_Tgt_For_Model model_Status_Duct_Tgt_For_Model_input; +//tStatus_Eva_Tgt_For_Model model_Status_Eva_Tgt_For_Model_input; +tStatus_IO_For_Model model_Status_IO_For_Model_input; +tStatus_Pwm_For_Model model_Status_Pwm_For_Model_input; +tStatus_eComp_For_Model model_Status_eComp_For_Model_input; +tStatus_External_For_Model model_Status_External_For_Model_input; +tStatus_EMS_For_Model model_Status_EMS_For_Model_input; +tStatus_Ionizer_Aroma_For_Model model_Status_Ionizer_Aroma_For_Model_input; +//tStatus_Duct_Select_For_Model model_Status_Duct_Select_For_Model_input; + +tStatus_Set_For_Model model_Status_Set_For_Model_output; +tStatus_Actuator_For_Model model_Status_Actuator_DoorsActuator_For_Model_output; +tStatus_Duct_Tgt_For_Model model_Status_Duct_Tgt_For_Model_output; +tStatus_Eva_Tgt_For_Model model_Status_Eva_Tgt_For_Model_output; +tStatus_IO_For_Model model_Status_IO_For_Model_output; +tStatus_Pwm_For_Model model_Status_Pwm_For_Model_output; +tStatus_eComp_For_Model model_Status_eComp_For_Model_output; +tStatus_External_For_Model model_Status_External_For_Model_output; +tStatus_EMS_For_Model model_Status_EMS_For_Model_output; +tStatus_Ionizer_Aroma_For_Model model_Status_Ionizer_Aroma_For_Model_output; +tStatus_Duct_Select_For_Model model_Status_Duct_Select_For_Model_output; + + +//uint32_t __attribute__((section(".stack_data"))) tModelTask_stack[1024]; + +void ModelTask_Init( + tModelTask *env, + tLinTaskActuator *linTaskActuator1, + tLinTaskActuator *linTaskActuator2, + tLinTaskActuator *linTaskActuator3, + + tLin4TaskSensor *lin4TaskSensor, + tLin5TaskSensor *lin5TaskSensor, + + tPwms *pwms, + + tGpios *gpios, + + tAdc0Task *adc0Task, + tAdc1Task *adc1Task, + + tCanSpamReceiver *canSpamReceiver, + tCanSpamTransmitter *canSpamTransmitter, + tCanSpamDebugTransmitter *canSpamDebugTransmitter, + tDiagnostic *diagnostic, + + tCanUds *canUds, + + tLoggerInterface *logger +) { + env->linTaskActuator1 = linTaskActuator1; + env->linTaskActuator2 = linTaskActuator2; + env->linTaskActuator3 = linTaskActuator3; + + env->lin4TaskSensor = lin4TaskSensor; + env->lin5TaskSensor = lin5TaskSensor; + + env->pwms = pwms; + env->gpios = gpios; + + env->canUds = canUds; + + env->adc0Task = adc0Task; + env->adc1Task = adc1Task; + + env->canSpamReceiver = canSpamReceiver; + env->canSpamTransmitter = canSpamTransmitter; + env->canSpamDebugTransmitter = canSpamDebugTransmitter; + + env->diagnostic = diagnostic; + + env->access = osMutexNew(NULL); + env->logger = logger; + InitThreadAtrStatic(&env->thread.attr, "ModelTask", env->thread.controlBlock, env->thread.stack, osPriorityNormal); + +// env->thread.stack = tModelTask_stack; +// InitThreadAtr(&env->thread.attr,"ModelTask",&env->thread.controlBlock,sizeof(env->thread.controlBlock),env->thread.stack,sizeof(env->thread.stack),osPriorityNormal); + env->thread.id = 0; + +} + + +static bool getActProc(tModelTask *env, uint8_t numAct, uint8_t numIndex, uint16_t maxPos, uint16_t proc) { + uint16_t pos = (maxPos * proc) / 1000; + + if (numAct == 1) { + + env->triggerActuatorCmdBus_1.BUS_ADR[numIndex] = numIndex + 1; + env->triggerActuatorCmdBus_1.POS[numIndex] = pos; + env->triggerActuatorCmdBus_1.MODE[numIndex] = 0; + env->triggerActuatorCmdBus_1.COM[numIndex] = 3; + env->triggerActuatorCmdBus_1.Stall_SET[numIndex] = 0; + env->triggerActuatorCmdBus_1.Lnoise_SET[numIndex] = 0; + env->triggerActuatorCmdBus_1.Autos_SET[numIndex] = 3; + env->triggerActuatorCmdBus_1.Speed_SET[numIndex] = 3; + env->triggerActuatorCmdBus_1.Coils_Stop_SET[numIndex] = 3; + + + return true; + } + + if (numAct == 2) { + env->triggerActuatorCmdBus_2.BUS_ADR[numIndex] = numIndex + 1; + env->triggerActuatorCmdBus_2.POS[numIndex] = pos; + env->triggerActuatorCmdBus_2.MODE[numIndex] = 0; + env->triggerActuatorCmdBus_2.COM[numIndex] = 3; + env->triggerActuatorCmdBus_2.Stall_SET[numIndex] = 0; + env->triggerActuatorCmdBus_2.Lnoise_SET[numIndex] = 0; + env->triggerActuatorCmdBus_2.Autos_SET[numIndex] = 3; + env->triggerActuatorCmdBus_2.Speed_SET[numIndex] = 3; + env->triggerActuatorCmdBus_2.Coils_Stop_SET[numIndex] = 3; + + return true; + } + + if (numAct == 3) { + env->triggerActuatorCmdBus_3.BUS_ADR[numIndex] = numIndex + 1; + env->triggerActuatorCmdBus_3.POS[numIndex] = pos; + env->triggerActuatorCmdBus_3.MODE[numIndex] = 0; + env->triggerActuatorCmdBus_3.COM[numIndex] = 3; + env->triggerActuatorCmdBus_3.Stall_SET[numIndex] = 0; + env->triggerActuatorCmdBus_3.Lnoise_SET[numIndex] = 0; + env->triggerActuatorCmdBus_3.Autos_SET[numIndex] = 3; + env->triggerActuatorCmdBus_3.Speed_SET[numIndex] = 3; + env->triggerActuatorCmdBus_3.Coils_Stop_SET[numIndex] = 3; + + return true; + } + + return false; +} + +static bool isUDS_Captured(tModelTask *env, uint8_t index, uint8_t numAct) { + + + if (numAct == 1) { + + + if ((index == 0) && (model_Status_Set_For_Model_output.Motor_Def)) { + getActProc(env, numAct, 0, rtY.Status_Actuator_model_IO.Motor_Def, + model_Status_Actuator_DoorsActuator_For_Model_output.Motor_Def); + return true; + } + + if ((index == 1) && (model_Status_Set_For_Model_output.Motor_REC)) { + getActProc(env, numAct, 1, rtY.Status_Actuator_model_IO.Motor_REC, + model_Status_Actuator_DoorsActuator_For_Model_output.Motor_REC); + return true; + } + + if ((index == 2) && (model_Status_Set_For_Model_output.Motor_OSA)) { + getActProc(env, numAct, 2, rtY.Status_Actuator_model_IO.Motor_OSA, + model_Status_Actuator_DoorsActuator_For_Model_output.Motor_OSA); + return true; + } + + if ((index == 3) && (model_Status_Set_For_Model_output.Motor_Temp1_FL)) { + getActProc(env, numAct, 3, rtY.Status_Actuator_model_IO.Motor_Temp1_FL, + model_Status_Actuator_DoorsActuator_For_Model_output.Motor_Temp1_FL); + return true; + } + + if ((index == 4) && (model_Status_Set_For_Model_output.Motor_Vent_CFL)) { + getActProc(env, numAct, 4, rtY.Status_Actuator_model_IO.Motor_Vent_CFL, + model_Status_Actuator_DoorsActuator_For_Model_output.Motor_Vent_CFL); + return true; + } + + + if ((index == 5) && (model_Status_Set_For_Model_output.Motor_Vent_SFL)) { + getActProc(env, numAct, 5, rtY.Status_Actuator_model_IO.Motor_Vent_SFL, + model_Status_Actuator_DoorsActuator_For_Model_output.Motor_Vent_SFL); + return true; + } + + if ((index == 6) && (model_Status_Set_For_Model_output.Motor_Temp2_FL)) { + getActProc(env, numAct, 6, rtY.Status_Actuator_model_IO.Motor_Temp2_FL, + model_Status_Actuator_DoorsActuator_For_Model_output.Motor_Temp2_FL); + return true; + } + + if ((index == 7) && (model_Status_Set_For_Model_output.Motor_Foot_1FL)) { + getActProc(env, numAct, 7, rtY.Status_Actuator_model_IO.Motor_Foot_1FL, + model_Status_Actuator_DoorsActuator_For_Model_output.Motor_Foot_1FL); + return true; + } + + if ((index == 8) && (model_Status_Set_For_Model_output.Motor_Foot_2FL)) { + getActProc(env, numAct, 8, rtY.Status_Actuator_model_IO.Motor_Foot_2FL, + model_Status_Actuator_DoorsActuator_For_Model_output.Motor_Foot_2FL); + return true; + } + + } + + + if (numAct == 2) { + + + if ((index == 0) && (model_Status_Set_For_Model_output.Motor_Temp1_FR)) { + getActProc(env, numAct, 0, rtY.Status_Actuator_model_IO.Motor_Temp1_FR, + model_Status_Actuator_DoorsActuator_For_Model_output.Motor_Temp1_FR); + return true; + } + + if ((index == 1) && (model_Status_Set_For_Model_output.Motor_Vent_CFR)) { + getActProc(env, numAct, 1, rtY.Status_Actuator_model_IO.Motor_Vent_CFR, + model_Status_Actuator_DoorsActuator_For_Model_output.Motor_Vent_CFR); + return true; + } + + if ((index == 2) && (model_Status_Set_For_Model_output.Motor_Vent_SFR)) { + getActProc(env, numAct, 2, rtY.Status_Actuator_model_IO.Motor_Vent_SFR, + model_Status_Actuator_DoorsActuator_For_Model_output.Motor_Vent_SFR); + return true; + } + + if ((index == 3) && (model_Status_Set_For_Model_output.Motor_Temp2_FR)) { + getActProc(env, numAct, 3, rtY.Status_Actuator_model_IO.Motor_Temp2_FR, + model_Status_Actuator_DoorsActuator_For_Model_output.Motor_Temp2_FR); + return true; + } + + if ((index == 4) && (model_Status_Set_For_Model_output.Motor_Foot_1FR)) { + getActProc(env, numAct, 4, rtY.Status_Actuator_model_IO.Motor_Foot_1FR, + model_Status_Actuator_DoorsActuator_For_Model_output.Motor_Foot_1FR); + return true; + } + + if ((index == 5) && (model_Status_Set_For_Model_output.Motor_Foot_2FR)) { + getActProc(env, numAct, 5, rtY.Status_Actuator_model_IO.Motor_Foot_2FR, + model_Status_Actuator_DoorsActuator_For_Model_output.Motor_Foot_2FR); + return true; + } + + } + + + if (numAct == 3) { + + + if ((index == 0) && (model_Status_Set_For_Model_output.Motor_Temp_RR)) { + getActProc(env, numAct, 0, rtY.Status_Actuator_model_IO.Motor_Temp_RR, + model_Status_Actuator_DoorsActuator_For_Model_output.Motor_Temp_RR); + return true; + } + + if ((index == 1) && (model_Status_Set_For_Model_output.Motor_Temp_RL)) { + getActProc(env, numAct, 1, rtY.Status_Actuator_model_IO.Motor_Temp_RL, + model_Status_Actuator_DoorsActuator_For_Model_output.Motor_Temp_RL); + return true; + } + + if ((index == 2) && (model_Status_Set_For_Model_output.Motor_Vent_SRL)) { + getActProc(env, numAct, 2, rtY.Status_Actuator_model_IO.Motor_Vent_SRL, + model_Status_Actuator_DoorsActuator_For_Model_output.Motor_Vent_SRL); + return true; + } + + if ((index == 3) && (model_Status_Set_For_Model_output.Motor_Foot_RL)) { + getActProc(env, numAct, 3, rtY.Status_Actuator_model_IO.Motor_Foot_RL, + model_Status_Actuator_DoorsActuator_For_Model_output.Motor_Foot_RL); + return true; + } + + if ((index == 4) && (model_Status_Set_For_Model_output.Motor_Vent_CRL)) { + getActProc(env, numAct, 4, rtY.Status_Actuator_model_IO.Motor_Vent_CRL, + model_Status_Actuator_DoorsActuator_For_Model_output.Motor_Vent_CRL); + return true; + } + + if ((index == 5) && (model_Status_Set_For_Model_output.Motor_Vent_CRR)) { + getActProc(env, numAct, 5, rtY.Status_Actuator_model_IO.Motor_Vent_CRR, + model_Status_Actuator_DoorsActuator_For_Model_output.Motor_Vent_CRR); + return true; + } + + if ((index == 6) && (model_Status_Set_For_Model_output.Motor_Foot_RR)) { + getActProc(env, numAct, 6, rtY.Status_Actuator_model_IO.Motor_Foot_RR, + model_Status_Actuator_DoorsActuator_For_Model_output.Motor_Foot_RR); + return true; + } + + if ((index == 7) && (model_Status_Set_For_Model_output.Motor_Vent_SRR)) { + getActProc(env, numAct, 7, rtY.Status_Actuator_model_IO.Motor_Vent_SRR, + model_Status_Actuator_DoorsActuator_For_Model_output.Motor_Vent_SRR); + return true; + } + + if ((index == 8) && (model_Status_Set_For_Model_output.Motor_SealingValve)) { + getActProc(env, numAct, 8, rtY.Status_Actuator_model_IO.Motor_SealingValve, + model_Status_Actuator_DoorsActuator_For_Model_output.Motor_SealingValve); + return true; + } + + } + + + return false; +} + +static bool setActuatorBusy(tModelTask *env) { + + + if (env->triggerCommand1 == false) { + + + for (uint8_t i = 0; i < env->linTaskActuator1->LIN_ISSR_ALL; ++i) { + bool isCaptured = isUDS_Captured(env, i, 1); + + + if (isCaptured) { + asm("nop"); + } + + if ((rtY.Actuator_Ch0_Command_Model_out.COM[i] != 0) || isCaptured) { + + env->triggerCommand1 = true; + + if (isCaptured) { + +#if (LOG_LIN_ACTUATOR == 1) + #if (LOG_LIN1_ACTUATOR == 1) + + LoggerFormatTrace(LOGGER, LOG_SIGN, + "LIN1 (ADR[%d] = %d): UDS CAPTURED", i, + env->triggerActuatorCmdBus_1.BUS_ADR[i]) +#endif +#endif + + } else { + + env->triggerActuatorCmdBus_1.BUS_ADR[i] = rtY.Actuator_Ch0_Command_Model_out.BUS_ADR[i]; + env->triggerActuatorCmdBus_1.POS[i] = rtY.Actuator_Ch0_Command_Model_out.POS[i]; + env->triggerActuatorCmdBus_1.MODE[i] = rtY.Actuator_Ch0_Command_Model_out.MODE[i]; + env->triggerActuatorCmdBus_1.COM[i] = rtY.Actuator_Ch0_Command_Model_out.COM[i]; + env->triggerActuatorCmdBus_1.Stall_SET[i] = rtY.Actuator_Ch0_Command_Model_out.Stall_SET[i]; + env->triggerActuatorCmdBus_1.Lnoise_SET[i] = rtY.Actuator_Ch0_Command_Model_out.Lnoise_SET[i]; + env->triggerActuatorCmdBus_1.Autos_SET[i] = rtY.Actuator_Ch0_Command_Model_out.Autos_SET[i]; + env->triggerActuatorCmdBus_1.Speed_SET[i] = rtY.Actuator_Ch0_Command_Model_out.Speed_SET[i]; + env->triggerActuatorCmdBus_1.Coils_Stop_SET[i] = rtY.Actuator_Ch0_Command_Model_out.Coils_Stop_SET[i]; + +// memcpy(&env->triggerActuatorCmdBus_1, &rtY.Actuator_Ch0_Command_Model_out, sizeof(ActuatorCmdBus)); + } + +#if (LOG_LIN_ACTUATOR == 1) + #if (LOG_LIN1_ACTUATOR == 1) + + switch (env->triggerActuatorCmdBus_1.COM[i]) { + case LIN_ACT_CFR_MOD: { + LoggerFormatTrace(LOGGER, LOG_SIGN, + "LIN1 (ADR[%d] = %d): TRIGGERED COMMAND LIN_ACT_CFR_MOD (SET BUSY)", i, + env->triggerActuatorCmdBus_1.BUS_ADR[i]) + break; + } + case LIN_ACT_CFR_INI: { + LoggerFormatTrace(LOGGER, LOG_SIGN, + "LIN1 (ADR[%d] = %d): TRIGGERED COMMAND LIN_ACT_CFR_INI (SET BUSY)", i, + env->triggerActuatorCmdBus_1.BUS_ADR[i]) + break; + } + + case LIN_ACT_CFR_SET: { + LoggerFormatTrace(LOGGER, LOG_SIGN, + "LIN1 (ADR[%d] = %d): TRIGGERED COMMAND LIN_ACT_CFR_SET (SET BUSY)", i, + env->triggerActuatorCmdBus_1.BUS_ADR[i]) + break; + } + + case LIN_ACT_CFR_NONE: { + + break; + } + + default: { + LoggerFormatError(LOGGER, LOG_SIGN, + "LIN1 (ADR[%d] = %d): TRIGGERED COMMAND = %d UNKNOWN !!! (SET BUSY)", + i, + env->triggerActuatorCmdBus_1.BUS_ADR[i], + env->triggerActuatorCmdBus_1.COM[i]) + } + } + +#endif +#endif + + + Actuator_Ch0_Status_Model.Busy = 1; +// break; + } + } + } + + + if (env->triggerCommand2 == false) { + + for (uint8_t i = 0; i < env->linTaskActuator2->LIN_ISSR_ALL; ++i) { + bool isCaptured = isUDS_Captured(env, i, 2); + if ((rtY.Actuator_Ch1_Command_Mode_out.COM[i] != 0) || isCaptured) { + + env->triggerCommand2 = true; + + if (isCaptured) { + +#if (LOG_LIN_ACTUATOR == 1) + #if (LOG_LIN2_ACTUATOR == 1) + + LoggerFormatTrace(LOGGER, LOG_SIGN, + "LIN2 (ADR[%d] = %d): UDS CAPTURED", i, + env->triggerActuatorCmdBus_2.BUS_ADR[i]) +#endif +#endif + + } else { + env->triggerActuatorCmdBus_2.BUS_ADR[i] = rtY.Actuator_Ch1_Command_Mode_out.BUS_ADR[i]; + env->triggerActuatorCmdBus_2.POS[i] = rtY.Actuator_Ch1_Command_Mode_out.POS[i]; + env->triggerActuatorCmdBus_2.MODE[i] = rtY.Actuator_Ch1_Command_Mode_out.MODE[i]; + env->triggerActuatorCmdBus_2.COM[i] = rtY.Actuator_Ch1_Command_Mode_out.COM[i]; + env->triggerActuatorCmdBus_2.Stall_SET[i] = rtY.Actuator_Ch1_Command_Mode_out.Stall_SET[i]; + env->triggerActuatorCmdBus_2.Lnoise_SET[i] = rtY.Actuator_Ch1_Command_Mode_out.Lnoise_SET[i]; + env->triggerActuatorCmdBus_2.Autos_SET[i] = rtY.Actuator_Ch1_Command_Mode_out.Autos_SET[i]; + env->triggerActuatorCmdBus_2.Speed_SET[i] = rtY.Actuator_Ch1_Command_Mode_out.Speed_SET[i]; + env->triggerActuatorCmdBus_2.Coils_Stop_SET[i] = rtY.Actuator_Ch1_Command_Mode_out.Coils_Stop_SET[i]; + +// memcpy(&env->triggerActuatorCmdBus_2, &rtY.Actuator_Ch1_Command_Mode_out, sizeof(ActuatorCmdBus)); + } + +#if (LOG_LIN_ACTUATOR == 1) + #if (LOG_LIN2_ACTUATOR == 1) + + + switch (env->triggerActuatorCmdBus_2.COM[i]) { + case LIN_ACT_CFR_MOD: { + LoggerFormatTrace(LOGGER, LOG_SIGN, + "LIN2 (ADR[%d] = %d): TRIGGERED COMMAND LIN_ACT_CFR_MOD (SET BUSY)", i, + env->triggerActuatorCmdBus_2.BUS_ADR[i]) + break; + } + case LIN_ACT_CFR_INI: { + LoggerFormatTrace(LOGGER, LOG_SIGN, + "LIN2 (ADR[%d] = %d): TRIGGERED COMMAND LIN_ACT_CFR_INI (SET BUSY)", i, + env->triggerActuatorCmdBus_2.BUS_ADR[i]) + break; + } + + case LIN_ACT_CFR_SET: { + LoggerFormatTrace(LOGGER, LOG_SIGN, + "LIN2 (ADR[%d] = %d): TRIGGERED COMMAND LIN_ACT_CFR_SET (SET BUSY)", i, + env->triggerActuatorCmdBus_2.BUS_ADR[i]) + break; + } + + case LIN_ACT_CFR_NONE: { + + break; + } + + default: { + LoggerFormatError(LOGGER, LOG_SIGN, + "LIN2 (ADR[%d] = %d): TRIGGERED COMMAND = %d UNKNOWN !!! (SET BUSY)", + i, + env->triggerActuatorCmdBus_2.BUS_ADR[i], + env->triggerActuatorCmdBus_2.COM[i]) + } + } + +#endif +#endif + + + Actuator_Ch1_Status_Model.Busy = 1; +// break; + } + } + } + + + if (env->triggerCommand3 == false) { + + for (uint8_t i = 0; i < env->linTaskActuator3->LIN_ISSR_ALL; ++i) { + bool isCaptured = isUDS_Captured(env, i, 3); + if ((rtY.Actuator_Ch2_Command_Model_out.COM[i] != 0) || isCaptured) { + + env->triggerCommand3 = true; + + if (isCaptured) { + +#if (LOG_LIN_ACTUATOR == 1) + #if (LOG_LIN3_ACTUATOR == 1) + + LoggerFormatTrace(LOGGER, LOG_SIGN, + "LIN3 (ADR[%d] = %d): UDS CAPTURED", i, + env->triggerActuatorCmdBus_3.BUS_ADR[i]) +#endif +#endif + + } else { + env->triggerActuatorCmdBus_3.BUS_ADR[i] = rtY.Actuator_Ch2_Command_Model_out.BUS_ADR[i]; + env->triggerActuatorCmdBus_3.POS[i] = rtY.Actuator_Ch2_Command_Model_out.POS[i]; + env->triggerActuatorCmdBus_3.MODE[i] = rtY.Actuator_Ch2_Command_Model_out.MODE[i]; + env->triggerActuatorCmdBus_3.COM[i] = rtY.Actuator_Ch2_Command_Model_out.COM[i]; + env->triggerActuatorCmdBus_3.Stall_SET[i] = rtY.Actuator_Ch2_Command_Model_out.Stall_SET[i]; + env->triggerActuatorCmdBus_3.Lnoise_SET[i] = rtY.Actuator_Ch2_Command_Model_out.Lnoise_SET[i]; + env->triggerActuatorCmdBus_3.Autos_SET[i] = rtY.Actuator_Ch2_Command_Model_out.Autos_SET[i]; + env->triggerActuatorCmdBus_3.Speed_SET[i] = rtY.Actuator_Ch2_Command_Model_out.Speed_SET[i]; + env->triggerActuatorCmdBus_3.Coils_Stop_SET[i] = rtY.Actuator_Ch2_Command_Model_out.Coils_Stop_SET[i]; + +// memcpy(&env->triggerActuatorCmdBus_3, &rtY.Actuator_Ch2_Command_Model_out, sizeof(ActuatorCmdBus)); + } + +#if (LOG_LIN_ACTUATOR == 1) + #if (LOG_LIN3_ACTUATOR == 1) + + + switch (env->triggerActuatorCmdBus_3.COM[i]) { + case LIN_ACT_CFR_MOD: { + LoggerFormatTrace(LOGGER, LOG_SIGN, + "LIN3 (ADR[%d] = %d): TRIGGERED COMMAND LIN_ACT_CFR_MOD (SET BUSY)", i, + env->triggerActuatorCmdBus_3.BUS_ADR[i]) + break; + } + case LIN_ACT_CFR_INI: { + LoggerFormatTrace(LOGGER, LOG_SIGN, + "LIN3 (ADR[%d] = %d): TRIGGERED COMMAND LIN_ACT_CFR_INI (SET BUSY)", i, + env->triggerActuatorCmdBus_3.BUS_ADR[i]) + break; + } + + case LIN_ACT_CFR_SET: { + LoggerFormatTrace(LOGGER, LOG_SIGN, + "LIN3 (ADR[%d] = %d): TRIGGERED COMMAND LIN_ACT_CFR_SET (SET BUSY)", i, + env->triggerActuatorCmdBus_3.BUS_ADR[i]) + break; + } + + case LIN_ACT_CFR_NONE: { + + break; + } + + default: { + LoggerFormatError(LOGGER, LOG_SIGN, + "LIN3 (ADR[%d] = %d): TRIGGERED COMMAND = %d UNKNOWN !!! (SET BUSY)", + i, + env->triggerActuatorCmdBus_3.BUS_ADR[i], + env->triggerActuatorCmdBus_3.COM[i]) + } + } + + +#endif +#endif + + Actuator_Ch2_Status_Model.Busy = 1; +// break; + } + } + } + + + return false; +} + +__attribute__((section(".save_data"))) volatile CmdCAN_CCU_STAT1_Bus CCU_STAT1_MODEL_SAVE; +__attribute__((section(".save_data"))) volatile CmdCAN_CCU_STAT2_Bus CCU_STAT2_MODEL_SAVE; +__attribute__((section(".save_data"))) volatile CmdCAN_CCU_STAT3_Bus CCU_STAT3_MODEL_SAVE; +__attribute__((section(".save_data"))) volatile CCU_Msg1_Bus CCU_MSG1_MODEL_SAVE; + + +void InitWakeupModel(tModelTask *env) { + + HVAC_model_initialize(); + + if (RGM_SRS_WAKEUP_MASK == (RGM->SRS & RGM_SRS_WAKEUP_MASK)) { + LoggerInfoStatic(LOGGER, LOG_SIGN, "Wake up from standby") + rtDW.sleep_model = 1; + } else { + + memset((void *) &CCU_STAT1_MODEL_SAVE, 0, sizeof(env->ccu_candb_tx.CCU_Stat1)); + memset((void *) &CCU_STAT2_MODEL_SAVE, 0, sizeof(env->ccu_candb_tx.CCU_Stat2)); + memset((void *) &CCU_STAT3_MODEL_SAVE, 0, sizeof(env->ccu_candb_tx.CCU_Stat3)); + memset((void *) &CCU_MSG1_MODEL_SAVE, 0, sizeof(env->ccu_candb_tx.CCU_Msg1)); + + LoggerInfoStatic(LOGGER, LOG_SIGN, "Cold boot (power-on reset)") + + + rtDW.sleep_model = 0; + } +} + + +#define SLEEP_TIME 3000 + +static _Noreturn void ModelTask_Thread(tModelTask *env) { + + for (;;) { + + if (GPIO_ReadPins((uint8_t) PORT_E, PORT_PIN_16)) { + if (env->sleep_time == 0) { + env->sleep_time = SystemGetMs() + SLEEP_TIME; + } + } else { + env->sleep_time = 0; + } + + if ((env->sleep_time > 0) && (env->sleep_time < SystemGetMs())) { +// SMC_SetSystemMode(SMC_MODE_STANBY_3); + } + + if (osMutexAcquire(env->access, 1000) == osOK) { + + //LoggerFormatError(LOGGER, LOG_SIGN, "Step END = %d", SystemGetMs()) + + rtDW.t_now = SystemGetMs(); + + getCmdBusADCData(env->adc0Task, &rtDW.ADC_Data_Model); + + + getCmdBusADC2Data(env->adc1Task, + (CmdBusADC2Data *) &rtDW.ADC_Data_Model.VN7008AJ_DIAG_FrontLINActuatorPowerDriverAB); + + +//начало--------------------------------------------------PWM----------------------------------------------------------- +// PWM_Get.pwmPercentFront = env->pwms->pwmFrontCaptureIO.getPwm(env->pwms->pwmFrontCaptureIO.env); +// PWM_Get.pwmPercentRear = env->pwms->pwmRearCaptureIO.getPwm(env->pwms->pwmRearCaptureIO.env); +// PWM_Get.pwmPercentFrontReserved = env->pwms->pwmFrontCaptureIO.getPwm( +// env->pwms->pwmFrontReservedCaptureIO.env); +// PWM_Get.pwmPercentRearReserved = env->pwms->pwmRearCaptureIO.getPwm( +// env->pwms->pwmRearReservedCaptureIO.env); + +// model_Status_Pwm_For_Model_input.Pwm_Front = PWM_Get.pwmPercentFront * 10; +// model_Status_Pwm_For_Model_input.Pwm_Rear = PWM_Get.pwmPercentRear * 10; +//конец--------------------------------------------------PWM------------------------------------------------------------ + + +//начало--------------------------------------------------CAN----------------------------------------------------------- + get_CanSpamReceiver(env->canSpamReceiver); + + if (model_Status_Set_For_Model_output.EMS == 1) { + rtDW.CCUCAN_EMS_HVC_REQ_MSG_MODEL.EMS_eCompChiller_Req = model_Status_EMS_For_Model_output.EMS_Chiller_Req; + } + + model_Status_EMS_For_Model_input.EMS_Chiller_Req = rtDW.CCUCAN_EMS_HVC_REQ_MSG_MODEL.EMS_eCompChiller_Req; + + + bool isT15 = rtDW.CCUCAN_BCM_VEH_STATE_model.BCM_T15_Stat; +//конец--------------------------------------------------CAN------------------------------------------------------------ + + +//начало-------------------------------------------------SlEEP---------------------------------------------------------- + + memcpy((void *) &rtDW.CCU_STAT1_WAKEUP_MODEL, (void *) &CCU_STAT1_MODEL_SAVE, + sizeof(CmdCAN_CCU_STAT1_WakeUp_Bus)); + memcpy((void *) &rtDW.CCU_STAT2_WAKEUP_MODEL, (void *) &CCU_STAT2_MODEL_SAVE, + sizeof(CmdCAN_CCU_STAT2_WakeUp_Bus)); + memcpy((void *) &rtDW.CCU_STAT3_WAKEUP_MODEL, (void *) &CCU_STAT3_MODEL_SAVE, + sizeof(CmdCAN_CCU_STAT3_WakeUp_Bus)); + memcpy((void *) &rtDW.CCU_Msg1_WakeUp_model, (void *) &CCU_MSG1_MODEL_SAVE, sizeof(CCU_Msg1_WakeUp_Bus)); + + +//конец--------------------------------------------------SLEEP---------------------------------------------------------- + + Lin4_Output_Get_From_Model(env->lin4TaskSensor); + Lin5_Output_Get_From_Model(env->lin5TaskSensor); + + + HVAC_model_step(); + + + rtDW.sleep_model = 0; + + Lin5_Input_Set_From_Model(env->lin5TaskSensor); + + CanUdsOutput_Get_Model(env->canUds); + + + setActuatorBusy(env); + + +//начало--------------------------------------------------GPIO---------------------------------------------------------- + // Включение 5V (1 - ВКЛ) + GpioPinSet(&env->gpios->power.SW5V_EN, rtY.PowerEnable_Model.SW5V_EN); + // Контроль напряжения борт-сети (1 - ВКЛ) + GpioPinSet(&env->gpios->power.PBATT_CK_EN, rtY.PowerEnable_Model.PBATT_CK_EN); + + env->TwoWayValve_EN = rtY.PowerEnable_Model.TwoWayValve_EN; + env->EN_BATTChiller = rtY.PowerEnable_Model.EN_BATTChiller; + env->Incar_Motor_Front_EN = rtY.PowerEnable_Model.Incar_Motor_Front_EN; + env->Incar_Motor_Rear_EN = rtY.PowerEnable_Model.Incar_Motor_Rear_EN; + env->ShutOffFront_EN = rtY.PowerEnable_Model.ShutOffFront_EN; + env->ShutOffRear_EN = rtY.PowerEnable_Model.ShutOffRear_EN; + env->PtcRelayDriver1_EN = rtY.PowerEnable_Model.PtcRelayDriver1_EN; + env->PtcRelayDriver2_EN = rtY.PowerEnable_Model.PtcRelayDriver2_EN; + + if (model_Status_Set_For_Model_output.IO == 1) { + + if (model_Status_IO_For_Model_output._2_Way_Valve == 0) { + env->TwoWayValve_EN = false; + } else { + env->TwoWayValve_EN = true; + } + + if (model_Status_IO_For_Model_output.IncarMotor_Front == 0) { + env->Incar_Motor_Front_EN = false; + } else { + env->Incar_Motor_Front_EN = true; + } + + if (model_Status_IO_For_Model_output.IncarMotor_Rear == 0) { + env->Incar_Motor_Rear_EN = false; + } else { + env->Incar_Motor_Rear_EN = true; + } + + if (model_Status_IO_For_Model_output.ShutOff_Chiller == 0) { + env->EN_BATTChiller = false; + } else { + env->EN_BATTChiller = true; + } + + if (model_Status_IO_For_Model_output.ShutOff_Front == 0) { + env->ShutOffFront_EN = false; + } else { + env->ShutOffFront_EN = true; + } + + if (model_Status_IO_For_Model_output.IncarMotor_Rear == 0) { + env->ShutOffRear_EN = false; + } else { + env->ShutOffRear_EN = true; + } + + if (model_Status_IO_For_Model_output.PTC_1 == 0) { + env->PtcRelayDriver1_EN = false; + } else { + env->PtcRelayDriver1_EN = true; + } + + if (model_Status_IO_For_Model_output.PTC_2 == 0) { + env->PtcRelayDriver2_EN = false; + } else { + env->PtcRelayDriver2_EN = true; + } + + } else { + + GpioPinSet(&env->gpios->power.BTS5180_2EKA_TwoWayValveAndReservePowerSupply.TwoWayValve_EN, + env->TwoWayValve_EN); + GpioPinSet(&env->gpios->power.BTS5180_2EKA_TwoWayValveAndReservePowerSupply.TwoWayValve_EN_Diag, true); + GpioPinSet(&env->gpios->power.BTS5180_2EKA_TwoWayValveAndReservePowerSupply.ReservePower_EN, + rtY.PowerEnable_Model.ReservePower_EN); + + GpioPinSet(&env->gpios->power.BTS4175SGAXUMA1_ShutOFFValveBatteryChiller.EN_BATTChiller, + env->EN_BATTChiller); + + GpioPinSet(&env->gpios->power.BTS5180_2EKA_FrontRearIncarMotor.Incar_Motor_Front_EN, + env->Incar_Motor_Front_EN); + GpioPinSet(&env->gpios->power.BTS5180_2EKA_FrontRearIncarMotor.Incar_EN_Diag, true); + GpioPinSet(&env->gpios->power.BTS5180_2EKA_FrontRearIncarMotor.Incar_Motor_Rear_EN, + env->Incar_Motor_Rear_EN); + + GpioPinSet(&env->gpios->power.BTS5180_2EKA_ShutOFFValveFrontRear.ShutOffFront_EN, env->ShutOffFront_EN); + GpioPinSet(&env->gpios->power.BTS5180_2EKA_ShutOFFValveFrontRear.ShutOff_EN_Diag, true); + GpioPinSet(&env->gpios->power.BTS5180_2EKA_ShutOFFValveFrontRear.ShutOffRear_EN, env->ShutOffRear_EN); + + GpioPinSet(&env->gpios->power.BTS5180_2EKA_2xChannelPTCPower.PtcRelayDriver1_EN, + env->PtcRelayDriver1_EN); + GpioPinSet(&env->gpios->power.BTS5180_2EKA_2xChannelPTCPower.PtcRelayDriver_EN_Diag, true); + GpioPinSet(&env->gpios->power.BTS5180_2EKA_2xChannelPTCPower.PtcRelayDriver2_EN, + env->PtcRelayDriver2_EN); + } + + model_Status_IO_For_Model_input._2_Way_Valve = env->TwoWayValve_EN; + model_Status_IO_For_Model_input.IncarMotor_Front = env->Incar_Motor_Front_EN; + model_Status_IO_For_Model_input.IncarMotor_Rear = env->Incar_Motor_Rear_EN; + model_Status_IO_For_Model_input.ShutOff_Chiller = env->EN_BATTChiller; + model_Status_IO_For_Model_input.ShutOff_Front = env->ShutOffFront_EN; + model_Status_IO_For_Model_input.ShutOff_Rear = env->ShutOffRear_EN; + model_Status_IO_For_Model_input.PTC_1 = env->PtcRelayDriver1_EN; + model_Status_IO_For_Model_input.PTC_2 = env->PtcRelayDriver2_EN; + + + +// GpioPinSet(&env->gpios->power.BTS4175SGAXUMA1_ReservePowerOutput.EN_ReservePower, rtY.PowerEnable_Model.EN_ReservePower); + GpioPinSet(&env->gpios->power.BTS4175SGAXUMA1_PowerReserve.EN_PowerReserve, + rtY.PowerEnable_Model.EN_PowerReserve); + + GpioPinSet(&env->gpios->power.VN7008AJ_FrontLINActuatorPowerDriverAB.LIN_ActPower_AB, + rtY.PowerEnable_Model.LIN_ActPower_AB); + GpioPinSet(&env->gpios->power.VN7008AJ_FrontLINActuatorPowerDriverAB.EN_CurrentSensing_AB, true); + + GpioPinSet(&env->gpios->power.VN7008AJ_RearLINActuatorPowerDriverC.LIN_ActPower_C, + rtY.PowerEnable_Model.LIN_ActPower_C); + GpioPinSet(&env->gpios->power.VN7008AJ_RearLINActuatorPowerDriverC.EN_CurrentSensing_C, true); + + GpioPinSet(&env->gpios->power.BTS5120_2EKA_ShutoffValvePowerTXV.ShutOffTXV1_EN, + rtY.PowerEnable_Model.ShutOffTXV1_EN); + GpioPinSet(&env->gpios->power.BTS5120_2EKA_ShutoffValvePowerTXV.ShutOffTXV_EN_Diag, true); + GpioPinSet(&env->gpios->power.BTS5120_2EKA_ShutoffValvePowerTXV.ShutOffTXV2_EN, + rtY.PowerEnable_Model.ShutOffTXV2_EN); +//конец--------------------------------------------------GPIO----------------------------------------------------------- + + + +//начало--------------------------------------------------PWM----------------------------------------------------------- + if (model_Status_Set_For_Model_output.Pwm == 1) { + + env->pwms->pwmFrontIo.setActivePercent(env->pwms->pwmFrontIo.env, model_Status_Pwm_For_Model_output.Pwm_Front / 10); + env->pwms->pwmRearIo.setActivePercent(env->pwms->pwmRearIo.env, model_Status_Pwm_For_Model_output.Pwm_Rear / 10); + env->pwms->pwmFrontReservedIo.setActivePercent(env->pwms->pwmFrontReservedIo.env, + rtY.PWM_Get_f.pwmPercentFrontReserved); + env->pwms->pwmRearReservedIo.setActivePercent(env->pwms->pwmRearReservedIo.env, + rtY.PWM_Get_f.pwmPercentRearReserved); + + } else { + + env->pwms->pwmFrontIo.setActivePercent(env->pwms->pwmFrontIo.env, rtY.PWM_Get_f.pwmPercentFront); + env->pwms->pwmRearIo.setActivePercent(env->pwms->pwmRearIo.env, rtY.PWM_Get_f.pwmPercentRear); + env->pwms->pwmFrontReservedIo.setActivePercent(env->pwms->pwmFrontReservedIo.env, + rtY.PWM_Get_f.pwmPercentFrontReserved); + env->pwms->pwmRearReservedIo.setActivePercent(env->pwms->pwmRearReservedIo.env, + rtY.PWM_Get_f.pwmPercentRearReserved); + } +//конец--------------------------------------------------PWM------------------------------------------------------------ + +//начало-------------------------------------------------SlEEP---------------------------------------------------------- + if (isT15) { + memcpy((void *) &CCU_STAT1_MODEL_SAVE, &rtY.CCU_Stat1_model, sizeof(CmdCAN_CCU_STAT1_Bus)); + memcpy((void *) &CCU_STAT2_MODEL_SAVE, &rtY.CCU_Stat2_model, sizeof(CmdCAN_CCU_STAT2_Bus)); + memcpy((void *) &CCU_STAT3_MODEL_SAVE, &rtY.CCU_Stat3_model, sizeof(CmdCAN_CCU_STAT3_Bus)); + memcpy((void *) &CCU_MSG1_MODEL_SAVE, &rtY.CCU_Msg1_model, sizeof(CCU_Msg1_Bus)); + } +//конец--------------------------------------------------SLEEP---------------------------------------------------------- + +//начало--------------------------------------------------CAN----------------------------------------------------------- + memcpy(&env->ccu_candb_tx.CCU_Errors, &rtY.CCU_Errors_model, sizeof(env->ccu_candb_tx.CCU_Errors)); + memcpy(&env->ccu_candb_tx.CCU_Stat1, &rtY.CCU_Stat1_model, sizeof(env->ccu_candb_tx.CCU_Stat1)); + memcpy(&env->ccu_candb_tx.CCU_Stat2, &rtY.CCU_Stat2_model, sizeof(env->ccu_candb_tx.CCU_Stat2)); + memcpy(&env->ccu_candb_tx.CCU_HVC_Req_Msg, &rtY.CCUCAN_HVC_REQ_MSG_MODEL, + sizeof(env->ccu_candb_tx.CCU_HVC_Req_Msg)); + memcpy(&env->ccu_candb_tx.CCU_Msg3, &rtY.CCU_Msg3_model, sizeof(env->ccu_candb_tx.CCU_Msg3)); + memcpy(&env->ccu_candb_tx.CCU_Msg1, &rtY.CCU_Msg1_model, sizeof(env->ccu_candb_tx.CCU_Msg1)); + + + if (model_Status_Set_For_Model_output.eComp == 1) { + env->ccu_candb_tx.CCU_HVC_Req_Msg.CCU_eCompSpeedReq_Val_ro = model_Status_eComp_For_Model_output.Pwm_Front; + + // request to EMS for closing the low temperature circuit valve + // 2 : "Open Valve request" + // 1 : "Close Valve request" + // 0 : "No request" + if (model_Status_eComp_For_Model_output.LowTempValve == 0) { + env->ccu_candb_tx.CCU_HVC_Req_Msg.CCU_LowTempValve_Req = 1; + } else { + env->ccu_candb_tx.CCU_HVC_Req_Msg.CCU_LowTempValve_Req = 2; + } + + // 0 = Off!0 = On + //1 Byte + //[0x00] Off + //[0x01..0xFF] On; Inverse value: 0x01 + if (model_Status_eComp_For_Model_output.eComp_Statue_Request == 0) { + env->ccu_candb_tx.CCU_HVC_Req_Msg.CCU_eCompReq_Stat = 0; + } else { + env->ccu_candb_tx.CCU_HVC_Req_Msg.CCU_eCompReq_Stat = 1; + } + + } + model_Status_eComp_For_Model_input.Pwm_Front = env->ccu_candb_tx.CCU_HVC_Req_Msg.CCU_eCompSpeedReq_Val_ro; + + if (env->ccu_candb_tx.CCU_HVC_Req_Msg.CCU_LowTempValve_Req == 2) { + model_Status_eComp_For_Model_input.LowTempValve = 1; + } else { + model_Status_eComp_For_Model_input.LowTempValve = 0; + } + + + model_Status_eComp_For_Model_input.eComp_Statue_Request = env->ccu_candb_tx.CCU_HVC_Req_Msg.CCU_eCompReq_Stat; + + + if (model_Status_Set_For_Model_output.External == 1) { + env->ccu_candb_tx.CCU_Msg3.CCU_FAN_Req = model_Status_External_For_Model_output.CoolingFan / 10; + } + model_Status_External_For_Model_input.CoolingFan = env->ccu_candb_tx.CCU_Msg3.CCU_FAN_Req * 10; + + + set_CanSpamTransmitter(env->canSpamTransmitter, &env->ccu_candb_tx); + + + memcpy(&env->ccu_candb_dbg_tx.dbg_Act0, &rtY.dbgCAN_dbg_Act0_model, sizeof(env->ccu_candb_dbg_tx.dbg_Act0)); + memcpy(&env->ccu_candb_dbg_tx.dbg_Act1, &rtY.dbgCAN_dbg_Act1_model, sizeof(env->ccu_candb_dbg_tx.dbg_Act1)); + memcpy(&env->ccu_candb_dbg_tx.dbg_Act2, &rtY.dbgCAN_dbg_Act2_model, sizeof(env->ccu_candb_dbg_tx.dbg_Act2)); + memcpy(&env->ccu_candb_dbg_tx.dbg_Sen_Duct, &rtY.dbgCAN_dbg_Sen_Duct_model, + sizeof(env->ccu_candb_dbg_tx.dbg_Sen_Duct)); + memcpy(&env->ccu_candb_dbg_tx.dbg_Sen_Eva, &rtY.dbgCAN_dbg_Sen_Eva_model, + sizeof(env->ccu_candb_dbg_tx.dbg_Sen_Eva)); + + + memcpy(&env->ccu_candb_dbg_tx.dbg_Logic_Blower, &rtY.dbgCAN_dbg_Logic_Blower_model, + sizeof(env->ccu_candb_dbg_tx.dbg_Logic_Blower)); + + + if (model_Status_Set_For_Model_output.Pwm == 1) { + + + env->ccu_candb_dbg_tx.dbg_Logic_Blower.Logic_Blower_Pwm_Front = model_Status_Pwm_For_Model_output.Pwm_Front / 10; + env->ccu_candb_dbg_tx.dbg_Logic_Blower.Logic_Blower_Pwm_Rear = model_Status_Pwm_For_Model_output.Pwm_Rear / 10; + + } + + model_Status_Pwm_For_Model_input.Pwm_Front = env->ccu_candb_dbg_tx.dbg_Logic_Blower.Logic_Blower_Pwm_Front * 10; + model_Status_Pwm_For_Model_input.Pwm_Rear = env->ccu_candb_dbg_tx.dbg_Logic_Blower.Logic_Blower_Pwm_Rear * 10; + + + memcpy(&env->ccu_candb_dbg_tx.dbg_Sen_Amb, &rtY.dbgCAN_dbg_Sen_Amb_model, + sizeof(env->ccu_candb_dbg_tx.dbg_Sen_Amb)); + memcpy(&env->ccu_candb_dbg_tx.dbg_Sen_Incar, &rtY.dbgCAN_dbg_Sen_Incar_model, + sizeof(env->ccu_candb_dbg_tx.dbg_Sen_Incar)); + memcpy(&env->ccu_candb_dbg_tx.dbg_Sen_0, &rtY.dbgCAN_dbg_Sen_0_model, + sizeof(env->ccu_candb_dbg_tx.dbg_Sen_0)); + memcpy(&env->ccu_candb_dbg_tx.dbg_Logic_Ac, &rtY.dbg_Logic_Ac_model, + sizeof(env->ccu_candb_dbg_tx.dbg_Logic_Ac)); + memcpy(&env->ccu_candb_dbg_tx.dbg_CCU_IO, &rtY.dbgCAN_CCU_IO_model, + sizeof(env->ccu_candb_dbg_tx.dbg_CCU_IO)); + memcpy(&env->ccu_candb_dbg_tx.dbg_Logic_Rec, &rtY.dbgCAN_Logic_Rec_model, + sizeof(env->ccu_candb_dbg_tx.dbg_Logic_Rec)); + memcpy(&env->ccu_candb_dbg_tx.dbg_Logic_State, &rtY.dbgCAN_Logic_State_model, + sizeof(env->ccu_candb_dbg_tx.dbg_Logic_State)); + + memcpy(&env->ccu_candb_dbg_tx.dbg_Auto_AF, &rtY.dbgCAN_Auto_AF_model, + sizeof(env->ccu_candb_dbg_tx.dbg_Auto_AF)); + memcpy(&env->ccu_candb_dbg_tx.dbg_Auto_Duct, &rtY.dbgCAN_Auto_Duct_model, + sizeof(env->ccu_candb_dbg_tx.dbg_Auto_Duct)); + + memcpy(&env->ccu_candb_dbg_tx.dbg_Logic_Valve, &rtY.dbg_Logic_Valve_model, + sizeof(env->ccu_candb_dbg_tx.dbg_Logic_Valve)); + +/* + env->ccu_candb_dbg_tx.dbg_stat_PID.P_FUL = 501 + 2048; + env->ccu_candb_dbg_tx.dbg_stat_PID.I_FUL = 502 + 2048; + env->ccu_candb_dbg_tx.dbg_stat_PID.D_FUL = 503 + 2048; + + env->ccu_candb_dbg_tx.dbg_stat_PID.P_FUR = 504 + 2048; + env->ccu_candb_dbg_tx.dbg_stat_PID.I_FUR = 505 + 2048; + env->ccu_candb_dbg_tx.dbg_stat_PID.D_FUR = 506 + 2048; + + env->ccu_candb_dbg_tx.dbg_stat_PID.P_FLL = 507 + 2048; + env->ccu_candb_dbg_tx.dbg_stat_PID.I_FLL = 508 + 2048; + env->ccu_candb_dbg_tx.dbg_stat_PID.D_FLL = 509 + 2048; + + + env->ccu_candb_dbg_tx.dbg_stat_PID.P_FRL = -501 + 2048; + env->ccu_candb_dbg_tx.dbg_stat_PID.I_FRL = -502 + 2048; + env->ccu_candb_dbg_tx.dbg_stat_PID.D_FRL = -503 + 2048; + + env->ccu_candb_dbg_tx.dbg_stat_PID.P_RL = -504 + 2048; + env->ccu_candb_dbg_tx.dbg_stat_PID.I_RL = -505 + 2048; + env->ccu_candb_dbg_tx.dbg_stat_PID.D_RL = -506 + 2048; + + env->ccu_candb_dbg_tx.dbg_stat_PID.P_RR = -507 + 2048; + env->ccu_candb_dbg_tx.dbg_stat_PID.I_RR = -508 + 2048; + env->ccu_candb_dbg_tx.dbg_stat_PID.D_RR = -509 + 2048; +*/ + + + +// memcpy(&env->ccu_candb_dbg_tx.dbg_stat_PID, &rtY.dbg_stat_PID_model, +// sizeof(env->ccu_candb_dbg_tx.dbg_stat_PID)); + + + +//конец--------------------------------------------------CAN------------------------------------------------------------ + + memcpy(&env->ccu_candb_dbg_tx.dbg_Drs, &rtY.dbg_Drs_t_model, sizeof(env->ccu_candb_dbg_tx.dbg_Drs)); + memcpy(&env->ccu_candb_dbg_tx.dbg_LIN_AirQS_Stat, &rtY.dbg_LIN_AirQS_Stat_t_model, + sizeof(env->ccu_candb_dbg_tx.dbg_Logic_Valve)); + + Lin4_Input_Set_From_Model(env->lin4TaskSensor); + + set_CanDebugSpamTransmitter(env->canSpamDebugTransmitter, &env->ccu_candb_dbg_tx); + + set_Dtc_state(env->diagnostic); + + CanUdsInput_Set_Model(env->canUds); + + env->isRunning = true; + osMutexRelease(env->access); + } else { + LoggerErrorStatic(LOGGER, LOG_SIGN, "Access error ModelTask_Thread"); + } + + SystemDelayMs(10); + + + } +} + +void ModelTask_StartThread(tModelTask *env) { + if (!env->thread.id) { + env->thread.id = osThreadNew((osThreadFunc_t) (ModelTask_Thread), (void *) (env), &env->thread.attr); + } else { + osThreadResume(env->thread.id); + } +} + +void ModelTask_StopThread(tModelTask *env) { + if (env->thread.id) { + osThreadSuspend(env->thread.id); + } +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_MODEL/Model_Task.h b/MODULES/HVAC_M7_MODEL/Model_Task.h new file mode 100644 index 0000000..fa44bd4 --- /dev/null +++ b/MODULES/HVAC_M7_MODEL/Model_Task.h @@ -0,0 +1,111 @@ +// +// Created by cfif on 19.12.2025. +// + +#ifndef HVAC_M7_MODEL_TASK_H +#define HVAC_M7_MODEL_TASK_H + +#include +#include "stdbool.h" +#include "LoggerInterface.h" +#include "HVAC_model.h" +#include "LinActuatorTasks.h" +#include "AdcTasks.h" +#include "ccu_candb-binutil.h" +#include "ccu_candb_dbg-binutil.h" +#include "CanSpamTransmitter.h" +#include "CanSpamDebugTransmitter.h" +#include "Pwms.h" +#include "CanSpamReceiver.h" +#include "DiagnosticTask.h" +#include "LinSensorTasks.h" +#include "CanUds.h" + +typedef struct { + + + tAdc0Task *adc0Task; + tAdc1Task *adc1Task; + tCanSpamReceiver *canSpamReceiver; + tCanSpamTransmitter *canSpamTransmitter; + tCanSpamDebugTransmitter *canSpamDebugTransmitter; + tGpios *gpios; + tPwms *pwms; + tDiagnostic *diagnostic; + + ccu_candb_tx_t ccu_candb_tx; + ccu_candb_dbg_tx_t ccu_candb_dbg_tx; + + + osMutexId_t access; + + + tLoggerInterface *logger; + + tLinTaskActuator *linTaskActuator1; + tLinTaskActuator *linTaskActuator2; + tLinTaskActuator *linTaskActuator3; + + tLin4TaskSensor *lin4TaskSensor; + tLin5TaskSensor *lin5TaskSensor; + + tCanUds *canUds; + + bool triggerCommand1; + bool triggerCommand2; + bool triggerCommand3; + ActuatorCmdBus triggerActuatorCmdBus_1; + ActuatorCmdBus triggerActuatorCmdBus_2; + ActuatorCmdBus triggerActuatorCmdBus_3; + + + bool TwoWayValve_EN; + bool EN_BATTChiller; + bool Incar_Motor_Front_EN ; + bool Incar_Motor_Rear_EN; + bool ShutOffFront_EN; + bool ShutOffRear_EN ; + bool PtcRelayDriver1_EN; + bool PtcRelayDriver2_EN; + + + uint32_t sleep_time; + + bool isRunning; + + struct { + osThreadId_t id; + uint32_t stack[1024]; + //uint32_t *stack; + StaticTask_t controlBlock; + osThreadAttr_t attr; + } thread; +} tModelTask; + + +void ModelTask_Init( + tModelTask *env, + tLinTaskActuator *linTaskActuator1, + tLinTaskActuator *linTaskActuator2, + tLinTaskActuator *linTaskActuator3, + tLin4TaskSensor *lin4TaskSensor, + tLin5TaskSensor *lin5TaskSensor, + tPwms *pwms, + tGpios *gpios, + tAdc0Task *adc0Task, + tAdc1Task *adc1Task, + tCanSpamReceiver *canSpamReceiver, + tCanSpamTransmitter *canSpamTransmitter, + tCanSpamDebugTransmitter *canSpamDebugTransmitter, + tDiagnostic *diagnostic, + tCanUds *canUds, + tLoggerInterface *logger +); + +void ModelTask_StartThread(tModelTask *env); + +void ModelTask_StopThread(tModelTask *env); + +void InitWakeupModel(tModelTask *env); + +#endif //HVAC_M7_MODEL_TASK_H diff --git a/MODULES/HVAC_M7_MODEL/modular.json b/MODULES/HVAC_M7_MODEL/modular.json new file mode 100644 index 0000000..9589ff8 --- /dev/null +++ b/MODULES/HVAC_M7_MODEL/modular.json @@ -0,0 +1,13 @@ +{ + "dep": [ + + ], + "cmake": { + "inc_dirs": [ + "./" + ], + "srcs": [ + "./**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_PowerManagement/PowerManagement.c b/MODULES/HVAC_M7_PowerManagement/PowerManagement.c new file mode 100644 index 0000000..e58e553 --- /dev/null +++ b/MODULES/HVAC_M7_PowerManagement/PowerManagement.c @@ -0,0 +1,11 @@ +// +// Created by cfif on 05.05.23. +// +#include +#include "PowerManagement.h" + +void Pwm_Init( + tPowerManagement *env +) { + +} diff --git a/MODULES/HVAC_M7_PowerManagement/PowerManagement.h b/MODULES/HVAC_M7_PowerManagement/PowerManagement.h new file mode 100644 index 0000000..990c37e --- /dev/null +++ b/MODULES/HVAC_M7_PowerManagement/PowerManagement.h @@ -0,0 +1,18 @@ +// +// Created by cfif on 05.05.23. +// + +#ifndef WATER_BOX_BSD_POWERMANAGEMENT_H +#define WATER_BOX_BSD_POWERMANAGEMENT_H + +#include "GpioPin.h" + +typedef struct { + +} tPowerManagement; + +void Pwm_Init( + tPowerManagement *env +); + +#endif //WATER_BOX_BSD_POWERMANAGEMENT_H diff --git a/MODULES/HVAC_M7_PowerManagement/modular.json b/MODULES/HVAC_M7_PowerManagement/modular.json new file mode 100644 index 0000000..0dd1901 --- /dev/null +++ b/MODULES/HVAC_M7_PowerManagement/modular.json @@ -0,0 +1,10 @@ +{ + "cmake": { + "inc_dirs": [ + "./" + ], + "srcs": [ + "./**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_Pwms/Pwms.c b/MODULES/HVAC_M7_Pwms/Pwms.c new file mode 100644 index 0000000..4f18557 --- /dev/null +++ b/MODULES/HVAC_M7_Pwms/Pwms.c @@ -0,0 +1,284 @@ +// +// Created by Cfif on 14.12.23. +// +#include +#include "fc7xxx_driver_port.h" +#include "Pwms.h" + +#define LOG_SIGN "INIT" +#define LOGGER logger + +tPwms PWMS; + + +//начало--------------------------PwmFront------------------------------------------------- +//начало--------------------------PwmFront------------------------------------------------- +//начало--------------------------PwmFront------------------------------------------------- +void Bsp_Tpu_PwmFrontCallback(void) { + Get_Set_Tpu_PwmCallback(&PWMS.pwmFront); +} + +void Bsp_Tpu_PwmFrontOverflowCallBack(void) { + asm("nop"); +} + +void Bsp_Tpu_PwmFrontCaptureCallback(void) { + Get_Set_Tpu_PwmCaptureCallback(&PWMS.pwmFrontCapture); +} + +void Bsp_Tpu_PwmFrontCapture_OverflowCallBack(void) { + asm("nop"); +} +//конец--------------------------PwmFront------------------------------------------------- +//конец--------------------------PwmFront------------------------------------------------- +//конец--------------------------PwmFront------------------------------------------------- + + +//начало--------------------------PwmRear------------------------------------------------- +//начало--------------------------PwmRear------------------------------------------------- +//начало--------------------------PwmRear------------------------------------------------- +void Bsp_Tpu_PwmRearCallback(void) { + Get_Set_Tpu_PwmCallback(&PWMS.pwmRear); +} + +void Bsp_Tpu_PwmRearOverflowCallBack(void) { + asm("nop"); +} + +void Bsp_Tpu_PwmRearCaptureCallback(void) { + Get_Set_Tpu_PwmCaptureCallback(&PWMS.pwmRearCapture); +} + +void Bsp_Tpu_PwmRearCapture_OverflowCallBack(void) { + asm("nop"); +} +//конец--------------------------PwmRear------------------------------------------------- +//конец--------------------------PwmRear------------------------------------------------- +//конец--------------------------PwmRear------------------------------------------------- + +//начало--------------------------PwmFrontReserve------------------------------------------------- +//начало--------------------------PwmFrontReserve------------------------------------------------- +//начало--------------------------PwmFrontReserve------------------------------------------------- +void Bsp_Tpu_PwmFrontReserveCallback(void) { + Get_Set_Tpu_PwmCallback(&PWMS.pwmFrontReserved); +} + +void Bsp_Tpu_PwmFrontReserveOverflowCallBack(void) { + asm("nop"); +} + +void Bsp_Tpu_PwmFrontReserveCaptureCallback(void) { + Get_Set_Tpu_PwmCaptureCallback(&PWMS.pwmFrontReservedCapture); +} + +void Bsp_Tpu_PwmFrontReserveCapture_OverflowCallBack(void) { + asm("nop"); +} +//конец--------------------------PwmFrontReserve------------------------------------------------- +//конец--------------------------PwmFrontReserve------------------------------------------------- +//конец--------------------------PwmFrontReserve------------------------------------------------- + +//начало--------------------------PwmRearReserve------------------------------------------------- +//начало--------------------------PwmRearReserve------------------------------------------------- +//начало--------------------------PwmRearReserve------------------------------------------------- +void Bsp_Tpu_PwmRearReserveCallback(void) { + Get_Set_Tpu_PwmCallback(&PWMS.pwmRearReserved); +} + +void Bsp_Tpu_PwmRearReserveOverflowCallBack(void) { + asm("nop"); +} + +void Bsp_Tpu_PwmRearReserveCaptureCallback(void) { + Get_Set_Tpu_PwmCaptureCallback(&PWMS.pwmRearReservedCapture); +} + +void Bsp_Tpu_PwmRearReserveCapture_OverflowCallBack(void) { + asm("nop"); +} +//конец--------------------------PwmRearReserve------------------------------------------------- +//конец--------------------------PwmRearReserve------------------------------------------------- +//конец--------------------------PwmRearReserve------------------------------------------------- + +void Pwms_Init(tLoggerInterface *logger) { + tPwms *env = &PWMS; + + PORT_InitType tInitStruct = {0}; + +//начало--------------------------PwmFront------------------------------------------------- +//начало--------------------------PwmFront------------------------------------------------- +//начало--------------------------PwmFront------------------------------------------------- + + // TPU_CH4: PortD 4: ALT7 + tInitStruct.u32PortPins = PORT_PIN_4; + tInitStruct.uPortPinMux.u32PortPinMode = PORT_ALT7_FUNC_MODE; + PORT_InitPins(PORT_D, &tInitStruct); + + PWM_Initial( + &env->pwmFront, + true, + PERIOD_TICKS, + PERIOD_TICKS * PERCENT_OFF_PWM / 100, + 4U, + 0xFF, + Bsp_Tpu_PwmFrontCallback, + Bsp_Tpu_PwmFrontOverflowCallBack + ); + + env->pwmFrontIo = vPwmGetIo(&env->pwmFront); + + + // TPU_CH3: PortD 3: ALT7 + tInitStruct.u32PortPins = PORT_PIN_3; + tInitStruct.uPortPinMux.u32PortPinMode = PORT_ALT7_FUNC_MODE; + PORT_InitPins(PORT_D, &tInitStruct); + + PWM_Capture_Initial( + &env->pwmFrontCapture, + false, + 3U, + 0xFF, + Bsp_Tpu_PwmFrontCaptureCallback, + NULL + ); + + env->pwmFrontCaptureIO = vPwmCaptureGetIo(&env->pwmFrontCapture); +//конец--------------------------PwmFront------------------------------------------------- +//конец--------------------------PwmFront------------------------------------------------- +//конец--------------------------PwmFront------------------------------------------------- + + +//начало--------------------------PwmRear------------------------------------------------- +//начало--------------------------PwmRear------------------------------------------------- +//начало--------------------------PwmRear------------------------------------------------- + + // TPU_CH27: PortD 23: ALT5 + tInitStruct.u32PortPins = PORT_PIN_23; + tInitStruct.uPortPinMux.u32PortPinMode = PORT_ALT5_FUNC_MODE; + PORT_InitPins(PORT_D, &tInitStruct); + + PWM_Initial( + &env->pwmRear, + false, + PERIOD_TICKS, + PERIOD_TICKS * PERCENT_OFF_PWM / 100, + 27U, + 0xFF, + Bsp_Tpu_PwmRearCallback, + NULL + ); + + env->pwmRearIo = vPwmGetIo(&env->pwmRear); + + + // TPU_CH17: PortD 21: ALT4 + tInitStruct.u32PortPins = PORT_PIN_21; + tInitStruct.uPortPinMux.u32PortPinMode = PORT_ALT4_FUNC_MODE; + PORT_InitPins(PORT_D, &tInitStruct); + + PWM_Capture_Initial( + &env->pwmRearCapture, + false, + 17U, + 0xFF, + Bsp_Tpu_PwmRearCaptureCallback, + NULL + ); + + + env->pwmRearCaptureIO = vPwmCaptureGetIo(&env->pwmRearCapture); + +//конец--------------------------PwmRear------------------------------------------------- +//конец--------------------------PwmRear------------------------------------------------- +//конец--------------------------PwmRear------------------------------------------------- + +//начало--------------------------PwmFrontReserve------------------------------------------------- +//начало--------------------------PwmFrontReserve------------------------------------------------- +//начало--------------------------PwmFrontReserve------------------------------------------------- + + // TPU_CH15: PortD 30: ALT6 + tInitStruct.u32PortPins = PORT_PIN_30; + tInitStruct.uPortPinMux.u32PortPinMode = PORT_ALT6_FUNC_MODE; + PORT_InitPins(PORT_D, &tInitStruct); + + PWM_Initial( + &env->pwmFrontReserved, + false, + PERIOD_TICKS, + PERIOD_TICKS * PERCENT_OFF_PWM / 100, + 15U, + 0xFF, + Bsp_Tpu_PwmFrontReserveCallback, + NULL + ); + + env->pwmFrontReservedIo = vPwmGetIo(&env->pwmFrontReserved); + + + // TPU_CH14: PortD 29: ALT6 + tInitStruct.u32PortPins = PORT_PIN_29; + tInitStruct.uPortPinMux.u32PortPinMode = PORT_ALT6_FUNC_MODE; + PORT_InitPins(PORT_D, &tInitStruct); + + PWM_Capture_Initial( + &env->pwmFrontReservedCapture, + false, + 14U, + 0xFF, + Bsp_Tpu_PwmFrontReserveCaptureCallback, + NULL + ); + + env->pwmFrontReservedCaptureIO = vPwmCaptureGetIo(&env->pwmFrontReservedCapture); +//конец--------------------------PwmFrontReserve------------------------------------------------- +//конец--------------------------PwmFrontReserve------------------------------------------------- +//конец--------------------------PwmFrontReserve------------------------------------------------- + + +//начало--------------------------PwmRearReserve------------------------------------------------- +//начало--------------------------PwmRearReserve------------------------------------------------- +//начало--------------------------PwmRearReserve------------------------------------------------- + + // TPU_CH23: PortC 31: ALT6 + tInitStruct.u32PortPins = PORT_PIN_31; + tInitStruct.uPortPinMux.u32PortPinMode = PORT_ALT6_FUNC_MODE; + PORT_InitPins(PORT_C, &tInitStruct); + + PWM_Initial( + &env->pwmRearReserved, + false, + PERIOD_TICKS, + PERIOD_TICKS * PERCENT_OFF_PWM / 100, + 23U, + 0xFF, + Bsp_Tpu_PwmRearReserveCallback, + NULL + ); + + env->pwmRearReservedIo = vPwmGetIo(&env->pwmRearReserved); + + + // TPU_CH21: PortC 29: ALT6 + tInitStruct.u32PortPins = PORT_PIN_29; + tInitStruct.uPortPinMux.u32PortPinMode = PORT_ALT6_FUNC_MODE; + PORT_InitPins(PORT_C, &tInitStruct); + + PWM_Capture_Initial( + &env->pwmRearReservedCapture, + false, + 21U, + 0xFF, + Bsp_Tpu_PwmRearReserveCaptureCallback, + NULL + ); + + env->pwmRearReservedCaptureIO = vPwmCaptureGetIo(&env->pwmRearReservedCapture); +//конец--------------------------PwmRearReserve------------------------------------------------- +//конец--------------------------PwmRearReserve------------------------------------------------- +//конец--------------------------PwmRearReserve------------------------------------------------- + + + LoggerInfoStatic(LOGGER, LOG_SIGN, "Initialization PWM - OK") + + +} diff --git a/MODULES/HVAC_M7_Pwms/Pwms.h b/MODULES/HVAC_M7_Pwms/Pwms.h new file mode 100644 index 0000000..3d3ad8d --- /dev/null +++ b/MODULES/HVAC_M7_Pwms/Pwms.h @@ -0,0 +1,47 @@ +// +// Created by CFIF on 14.12.23. +// + +#ifndef FLAG_PWMS_H +#define FLAG_PWMS_H + +#include "PwmFlagchip.h" +#include "PwmCaptureFlagchip.h" +#include "LoggerInterface.h" + +#define PERCENT_OFF_PWM 15 + +typedef struct { + tPwmFlagchip pwmFront; + tPwmIO pwmFrontIo; + tPwmCaptureFlagchip pwmFrontCapture; + tPwmCaptureIO pwmFrontCaptureIO; + + tPwmFlagchip pwmRear; + tPwmIO pwmRearIo; + tPwmCaptureFlagchip pwmRearCapture; + tPwmCaptureIO pwmRearCaptureIO; + + tPwmFlagchip pwmFrontReserved; + tPwmIO pwmFrontReservedIo; + tPwmCaptureFlagchip pwmFrontReservedCapture; + tPwmCaptureIO pwmFrontReservedCaptureIO; + + tPwmFlagchip pwmRearReserved; + tPwmIO pwmRearReservedIo; + tPwmCaptureFlagchip pwmRearReservedCapture; + tPwmCaptureIO pwmRearReservedCaptureIO; + +/* + tPwmFlagchip pwm; + tPwmIO pwmIo; + tPwmCaptureFlagchip pwmCapture; + tPwmCaptureIO pwmCaptureIO; +*/ +} tPwms; + +extern tPwms PWMS; + +void Pwms_Init(tLoggerInterface *logger); + +#endif //FLAG_PWMS_H diff --git a/MODULES/HVAC_M7_Pwms/modular.json b/MODULES/HVAC_M7_Pwms/modular.json new file mode 100644 index 0000000..9589ff8 --- /dev/null +++ b/MODULES/HVAC_M7_Pwms/modular.json @@ -0,0 +1,13 @@ +{ + "dep": [ + + ], + "cmake": { + "inc_dirs": [ + "./" + ], + "srcs": [ + "./**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_Rtcs/Rtcs.c b/MODULES/HVAC_M7_Rtcs/Rtcs.c new file mode 100644 index 0000000..93ca4c5 --- /dev/null +++ b/MODULES/HVAC_M7_Rtcs/Rtcs.c @@ -0,0 +1,11 @@ +// +// Created by cfif on 27.09.22. +// +#include "Rtcs.h" + +tRtcs RTCS; + +void Rtcs_Init() { + RTCS.rtc = vRtcInit(); + RTCS.rtcI0 = vRtcGetIo(&RTCS.rtc); +} diff --git a/MODULES/HVAC_M7_Rtcs/Rtcs.h b/MODULES/HVAC_M7_Rtcs/Rtcs.h new file mode 100644 index 0000000..93d8194 --- /dev/null +++ b/MODULES/HVAC_M7_Rtcs/Rtcs.h @@ -0,0 +1,20 @@ +// +// Created by cfif on 28.09.22. +// + +#ifndef RTCS_H +#define RTCS_H + +#include "RtcFC7240.h" +#include "LoggerInterface.h" + +typedef struct { + tRtcFlagchip rtc; + tRtcIO rtcI0; +} tRtcs; + +extern tRtcs RTCS; + +void Rtcs_Init(); + +#endif //RTCS_H diff --git a/MODULES/HVAC_M7_Rtcs/modular.json b/MODULES/HVAC_M7_Rtcs/modular.json new file mode 100644 index 0000000..0dd1901 --- /dev/null +++ b/MODULES/HVAC_M7_Rtcs/modular.json @@ -0,0 +1,10 @@ +{ + "cmake": { + "inc_dirs": [ + "./" + ], + "srcs": [ + "./**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_SMC/modular.json b/MODULES/HVAC_M7_SMC/modular.json new file mode 100644 index 0000000..9589ff8 --- /dev/null +++ b/MODULES/HVAC_M7_SMC/modular.json @@ -0,0 +1,13 @@ +{ + "dep": [ + + ], + "cmake": { + "inc_dirs": [ + "./" + ], + "srcs": [ + "./**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_SMC/standby.c b/MODULES/HVAC_M7_SMC/standby.c new file mode 100644 index 0000000..b372d57 --- /dev/null +++ b/MODULES/HVAC_M7_SMC/standby.c @@ -0,0 +1,46 @@ +// +// Created by cfif on 17.12.2025. +// + +#include "standby.h" + + +static void Bsp_GpioFInt_CallbackFunction(void) { + + bool value; + if (GPIO_ReadPins((uint8_t)PORT_E, PORT_PIN_16)) { + value = true; + } else { + value = false; + } + + if (value) { + + } + + __asm volatile ("nop"); +} + +void StandBy_Init() { + PORT_InitType tInitStruct = {0}; + PORT_InterruptType tIntStruct = {0}; + + // wakeup source: Key1/PortE16; MUX = GPIO input + tInitStruct.u32PortPins = PORT_PIN_16; + tInitStruct.uPortPinMux.u32PortPinMode = PORT_GPIO_MODE; + tInitStruct.bPullEn = true; + tInitStruct.ePullSel = PORT_PULL_UP; + PORT_InitPins(PORT_E, &tInitStruct); + + // enable PortE16 interrupt + tIntStruct.u32PortPins = PORT_PIN_16; + tIntStruct.ePortIsrMode = PORT_IRQ_BOTH_EDGE; + tIntStruct.pIsrNotify = Bsp_GpioFInt_CallbackFunction; + PORT_InitInterrupt(PORT_E, &tIntStruct); + + WKU_EnableWakeupSource(WKU_INPUT_GPIOE); + + NVIC_SetPriority(PORTE_IRQn, 0xFF); + NVIC_EnableIRQ(PORTE_IRQn); + +} diff --git a/MODULES/HVAC_M7_SMC/standby.h b/MODULES/HVAC_M7_SMC/standby.h new file mode 100644 index 0000000..b1da96a --- /dev/null +++ b/MODULES/HVAC_M7_SMC/standby.h @@ -0,0 +1,17 @@ +// +// Created by cfif on 17.12.2025. +// + +#ifndef HVAC_M7_STANDBY_H +#define HVAC_M7_STANDBY_H + +#include "fc7xxx_driver_scm.h" +#include "fc7xxx_driver_port.h" +#include "fc7xxx_driver_wku.h" +#include "fc7xxx_driver_smc.h" +#include "fc7xxx_driver_gpio.h" +#include "fc7xxx_driver_tstmp.h" + +void StandBy_Init(); + +#endif //HVAC_M7_STANDBY_H diff --git a/MODULES/HVAC_M7_SerialPorts/SerialPorts.c b/MODULES/HVAC_M7_SerialPorts/SerialPorts.c new file mode 100644 index 0000000..e12fbb9 --- /dev/null +++ b/MODULES/HVAC_M7_SerialPorts/SerialPorts.c @@ -0,0 +1,279 @@ +// +// Created by CFIF on 25.03.24. +// +#include "SerialPorts.h" +/* +tSerialPorts SERIAL_PORTS; + + +uint8_t buf_USART2_TRANSMITTED[256]; +ALIGN(256) uint8_t buf_USART2_DMA[128]; + + +static void DMA_USART2_TransferCompleteCallbackTx() { + SerialPort_TxEndTransmitted(SERIAL_PORTS.SerialPortLog_IO.env, 1); + asm("nop"); +} + +static void DMA_USART2_TransferCompleteCallbackRx() { + SerialPort_RxDmaBufToQueue(SERIAL_PORTS.SerialPortLog_IO.env, true,buf_USART2_DMA); +} + +static void FCUART_IldeInterrupt_CallBack(uint8_t u8UartIndex) { + SerialPort_RxDmaBufToQueue(SERIAL_PORTS.SerialPortLog_IO.env, false,buf_USART2_DMA); + PROCESS_UNUSED_VAR(u8UartIndex) +} + +static void FCUART_ErrorInterrupt_CallBack(uint8_t u8UartIndex, uint32_t u32Error) { + asm("nop"); + PROCESS_UNUSED_VAR(u8UartIndex) + PROCESS_UNUSED_VAR(u32Error) +} + +static void FCUART_TxEmptyInterrupt_CallBack(uint8_t u8UartIndex, FCUART_DataType *pTxData) { + asm("nop"); + PROCESS_UNUSED_VAR(u8UartIndex) + PROCESS_UNUSED_VAR(pTxData) +} + +static void FCUART_TxCompleteInterrupt_CallBack(uint8_t u8UartIndex, FCUART_DataType *pTxData) { + + if (u8UartIndex == SERIAL_PORTS.SerialPortLog.UART_INDEX) { + SerialPort_TxEndTransmitted(SERIAL_PORTS.SerialPortLog_IO.env, 1); + } + + PROCESS_UNUSED_VAR(pTxData) +} + +void FCUART2_RxTx_IRQHandler(void) { + FCUARTN_RxTx_IRQHandler(SERIAL_PORTS.SerialPortLog.UART_INDEX); +} + +// Настройка порта +static void vSerialPort_InitUSART2(tSerialPortFlagchip *env) { + PORT_InitType tInitStruct = {0}; + GPIO_InitType tGpioInitStruct = {0}; + + // Port D6: MUX = ALT2, UART2_RX + tInitStruct.u32PortPins = PORT_PIN_6; + tInitStruct.uPortPinMux.u32PortPinMode = PORTD_6_FCUART2_RX; + PORT_InitPins(PORT_D, &tInitStruct); + + tGpioInitStruct.u32GpioPins = GPIO_PIN_6; + tGpioInitStruct.ePinDirection = GPIO_IN; + GPIO_InitPins(GPIO_D, &tGpioInitStruct); + + // Port D7: MUX = ALT2, UART2_TX + tInitStruct.u32PortPins = PORT_PIN_7; + tInitStruct.uPortPinMux.u32PortPinMode = PORTD_7_FCUART2_TX; + PORT_InitPins(PORT_D, &tInitStruct); + + tGpioInitStruct.u32GpioPins = GPIO_PIN_7; + tGpioInitStruct.ePinDirection = GPIO_OUT; + tGpioInitStruct.ePinLevel = GPIO_HIGH; + GPIO_InitPins(GPIO_D, &tGpioInitStruct); + + vSerialPortInitDMA( + env, + + FCUART2, + 921600,//115200, + + 2, // UART0 = 0 ... UART7 = 7 + FCUART2_IRQn, // FCUART0_IRQn ... FCUART7_IRQn + 0xFF, + + buf_USART2_TRANSMITTED, + sizeof(buf_USART2_TRANSMITTED), + + DMA_CHANNEL_5, + DMA_REQ_FCUART2_RX, + buf_USART2_DMA, + sizeof(buf_USART2_DMA), + DMA5_IRQn, + 0xFF, // IRQ_DMA_PRIORITY + DMA5_IRQn, // IRQ_DMA_CHANNEL_PRIORITY + + DMA_CHANNEL_6, + DMA_REQ_FCUART2_TX, + buf_USART2_DMA, + sizeof(buf_USART2_DMA), + DMA6_IRQn, + 0xFF, // IRQ_DMA_PRIORITY + DMA6_IRQn, // IRQ_DMA_CHANNEL_PRIORITY + + + 1024, + 1024, + + DMA_USART2_TransferCompleteCallbackRx, + NULL, + + DMA_USART2_TransferCompleteCallbackTx, + NULL, + + + FCUART_IldeInterrupt_CallBack, + FCUART_ErrorInterrupt_CallBack, + + FCUART_TxEmptyInterrupt_CallBack, + FCUART_TxCompleteInterrupt_CallBack + + + ); + + +} +*/ + + +tSerialPorts SERIAL_PORTS; + + +uint8_t buf_USART1_TRANSMITTED[32]; +ALIGN(256) uint8_t buf_USART1_DMA[128]; + + +static void DMA_USART1_TransferCompleteCallbackTx() { + SerialPort_TxEndTransmitted(SERIAL_PORTS.SerialPortLog_IO.env, 1); + asm("nop"); +} + +static void DMA_USART1_TransferCompleteCallbackRx() { + SerialPort_RxDmaBufToQueue(SERIAL_PORTS.SerialPortLog_IO.env, true,buf_USART1_DMA); +} + +static void FCUART_IldeInterrupt_CallBack(uint8_t u8UartIndex) { + SerialPort_RxDmaBufToQueue(SERIAL_PORTS.SerialPortLog_IO.env, false,buf_USART1_DMA); + PROCESS_UNUSED_VAR(u8UartIndex) +} + +static void FCUART_ErrorInterrupt_CallBack(uint8_t u8UartIndex, uint32_t u32Error) { + asm("nop"); + PROCESS_UNUSED_VAR(u8UartIndex) + PROCESS_UNUSED_VAR(u32Error) +} + +static void FCUART_TxEmptyInterrupt_CallBack(uint8_t u8UartIndex, FCUART_DataType *pTxData) { + asm("nop"); + PROCESS_UNUSED_VAR(u8UartIndex) + PROCESS_UNUSED_VAR(pTxData) +} + +static void FCUART_TxCompleteInterrupt_CallBack(uint8_t u8UartIndex, FCUART_DataType *pTxData) { + + if (u8UartIndex == SERIAL_PORTS.SerialPortLog.UART_INDEX) { + SerialPort_TxEndTransmitted(SERIAL_PORTS.SerialPortLog_IO.env, 1); + } + + PROCESS_UNUSED_VAR(pTxData) +} + +void FCUART1_RxTx_IRQHandler(void) { + FCUARTN_RxTx_IRQHandler(SERIAL_PORTS.SerialPortLog.UART_INDEX); +} + +// Настройка порта +static void vSerialPort_InitUSART1(tSerialPortFlagchip *env) { + PORT_InitType tInitStruct = {0}; + GPIO_InitType tGpioInitStruct = {0}; + + // Port A19: MUX = ALT3, UART1_RX + tInitStruct.u32PortPins = PORT_PIN_19; + tInitStruct.uPortPinMux.u32PortPinMode = PORTA_19_FCUART1_RX; + PORT_InitPins(PORT_A, &tInitStruct); + + tGpioInitStruct.u32GpioPins = GPIO_PIN_19; + tGpioInitStruct.ePinDirection = GPIO_IN; + GPIO_InitPins(GPIO_A, &tGpioInitStruct); + + // Port A18: MUX = ALT3, UART1_TX + tInitStruct.u32PortPins = PORT_PIN_18; + tInitStruct.uPortPinMux.u32PortPinMode = PORTA_18_FCUART1_TX; + PORT_InitPins(PORT_A, &tInitStruct); + + tGpioInitStruct.u32GpioPins = GPIO_PIN_18; + tGpioInitStruct.ePinDirection = GPIO_OUT; + tGpioInitStruct.ePinLevel = GPIO_HIGH; + GPIO_InitPins(GPIO_A, &tGpioInitStruct); + + vSerialPortInitDMA( + env, + + FCUART1, + 921600,//115200, + + 1, // UART0 = 0 ... UART7 = 7 + FCUART1_IRQn, // FCUART0_IRQn ... FCUART7_IRQn + 0xFF, + + buf_USART1_TRANSMITTED, + sizeof(buf_USART1_TRANSMITTED), + + DMA_CHANNEL_5, + DMA_REQ_FCUART1_RX, + buf_USART1_DMA, + sizeof(buf_USART1_DMA), + DMA5_IRQn, + 0xFF, // IRQ_DMA_PRIORITY + DMA5_IRQn, // IRQ_DMA_CHANNEL_PRIORITY + + DMA_CHANNEL_6, + DMA_REQ_FCUART1_TX, + buf_USART1_DMA, + sizeof(buf_USART1_DMA), + DMA6_IRQn, + 0xFF, // IRQ_DMA_PRIORITY + DMA6_IRQn, // IRQ_DMA_CHANNEL_PRIORITY + + + 256, + 0, + + DMA_USART1_TransferCompleteCallbackRx, + NULL, + + DMA_USART1_TransferCompleteCallbackTx, + NULL, + + + FCUART_IldeInterrupt_CallBack, + FCUART_ErrorInterrupt_CallBack, + + FCUART_TxEmptyInterrupt_CallBack, + FCUART_TxCompleteInterrupt_CallBack + + + ); + + +} + + +void SerialPorts_Init() { + + tSerialPorts *env = &SERIAL_PORTS; + + //// Виртуальный сериал порт + + SerialPortVirt_Init(&env->cliVirtualPortOut, 4096); + env->cliVirtualPortOut_Io = SerialPortVirt_GetIo(&env->cliVirtualPortOut); + +// SerialPortVirt_Init(&env->cliVirtualPortIn, 128); +// env->cliVirtualPortIn_Io = SerialPortVirt_GetIo(&env->cliVirtualPortIn); +// SerialPortP2p_Init(&env->cliVirtualPort, 4 * 1024, 1024); +// env->cliVirtualInIo = SerialPortP2p_GetIoFirst(&env->cliVirtualPort); +// env->cliVirtualOutIo = SerialPortP2p_GetIoSecond(&env->cliVirtualPort); + + + + + vSerialPort_InitUSART1(&env->SerialPortLog); +// vSerialPort_InitUSART2(&env->SerialPortLog); + + SERIAL_PORTS.SerialPortLog_IO = vSerialPortGetIo(&env->SerialPortLog); + SERIAL_PORTS.SerialPortLog_Sniffer_IO = vSerialPortGetSnifferIo(&env->SerialPortLog); +} + + + diff --git a/MODULES/HVAC_M7_SerialPorts/SerialPorts.h b/MODULES/HVAC_M7_SerialPorts/SerialPorts.h new file mode 100644 index 0000000..03d841e --- /dev/null +++ b/MODULES/HVAC_M7_SerialPorts/SerialPorts.h @@ -0,0 +1,27 @@ +// +// Created by CFIF on 25.03.24. +// + +#ifndef HVAC_M7_SERIALPORTS_H +#define HVAC_M7_SERIALPORTS_H + +#include "SerialPortFlagchip.h" +#include "SerialPortVirt.h" +#include "LoggerInterface.h" + +typedef struct { + tSerialPortFlagchip SerialPortLog; + tSerialPortIO SerialPortLog_IO; + tSerialPortIO SerialPortLog_Sniffer_IO; + + + tSerialPortVirt cliVirtualPortOut; + tSerialPortIO cliVirtualPortOut_Io; + +} tSerialPorts; + +extern tSerialPorts SERIAL_PORTS; + +void SerialPorts_Init(); + +#endif //HVAC_M7_SERIALPORTS_H diff --git a/MODULES/HVAC_M7_SerialPorts/modular.json b/MODULES/HVAC_M7_SerialPorts/modular.json new file mode 100644 index 0000000..0dd1901 --- /dev/null +++ b/MODULES/HVAC_M7_SerialPorts/modular.json @@ -0,0 +1,10 @@ +{ + "cmake": { + "inc_dirs": [ + "./" + ], + "srcs": [ + "./**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_StatusData/DiagnosticTask.c b/MODULES/HVAC_M7_StatusData/DiagnosticTask.c new file mode 100644 index 0000000..c667285 --- /dev/null +++ b/MODULES/HVAC_M7_StatusData/DiagnosticTask.c @@ -0,0 +1,158 @@ +// +// Created by cfif on 23.01.2026. +// +#include "DiagnosticTask.h" +#include "CmsisRtosThreadUtils.h" +#include "StatusData.h" +#include "StatusError.h" +#include "HVAC_model.h" + +#define LOG_SIGN "DIAGNOSTIC" +#define LOGGER env->logger + +void Diagnostic_Init(tDiagnostic *env, tLoggerInterface *logger) { + + env->logger = logger; + + env->access = osMutexNew(NULL); + +// for (uint8_t i = 0; i < COUNT_DTC_CODE_ERROR; ++i) { + + // Тест DTC не был выполнен в текущем цикле работы +// dtc_state_error[i] = UDS_dtc_mask_testNotCompletedThisOperationCycle; +// } + +// InitThreadAtrStatic(&env->thread.attr, "Diagnostic", env->thread.controlBlock, env->thread.stack, +// osPriorityNormal); +} + +uint32_t diagnostic_ClearDiagnosticInformation_14(tDiagnostic *env) { + + if (osMutexAcquire(env->access, 5000) == osOK) { + + // for (uint8_t i = 0; i < COUNT_DTC_CODE_ERROR; ++i) { + // Тест DTC не был выполнен с момента последней очистки +// dtc_state_error[i] |= UDS_dtc_mask_testNotCompletedSinceLastClear; +// dtc_state_FIX_error[i] |= UDS_dtc_mask_testNotCompletedSinceLastClear; +// } + + osMutexRelease(env->access); + } else { + LoggerInfoStatic(LOGGER, LOG_SIGN, "Access error diagnostic_ClearDiagnosticInformation_14"); + } + + + return 0; +} + +uint32_t diagnostic_UDS_ReadDTCInformation_19_count(tDiagnostic *env, tDiagnosticDTC *diagnosticDTC) { + + uint32_t countDTC = 0; + + if (osMutexAcquire(env->access, 5000) == osOK) { + + for (uint8_t i = 0; i < COUNT_DTC_CODE_ERROR; ++i) { + + if (env->isNoBitsDTC) { + if (dtc_state_FIX_error[i] & (diagnosticDTC->mask)) { + ++countDTC; + } + } else { + if (dtc_state_error[i] & (diagnosticDTC->mask)) { + ++countDTC; + } + } + + } + + osMutexRelease(env->access); + } else { + LoggerInfoStatic(LOGGER, LOG_SIGN, "Access error diagnostic_ClearDiagnosticInformation_14"); + } + + + return countDTC; +} + +uint32_t diagnostic_UDS_ReadDTCInformation_19_dtc(tDiagnostic *env, tDiagnosticDTC *diagnosticDTC) { + + uint32_t size = 0; + + if (osMutexAcquire(env->access, 5000) == osOK) { + + for (uint8_t i = 0; i < COUNT_DTC_CODE_ERROR; ++i) { + + if (env->isNoBitsDTC) { + if (dtc_state_FIX_error[i] & (diagnosticDTC->mask)) { + diagnosticDTC->dataResponse[size] = dtc_codes[i].DTCHighByte; + diagnosticDTC->dataResponse[size + 1] = dtc_codes[i].DTCMiddleByte; + diagnosticDTC->dataResponse[size + 2] = dtc_codes[i].DTCLowByte; + diagnosticDTC->dataResponse[size + 3] = dtc_state_error[i] & (diagnosticDTC->mask); + size += 4; + } + } else { + if (dtc_state_error[i] & (diagnosticDTC->mask)) { + diagnosticDTC->dataResponse[size] = dtc_codes[i].DTCHighByte; + diagnosticDTC->dataResponse[size + 1] = dtc_codes[i].DTCMiddleByte; + diagnosticDTC->dataResponse[size + 2] = dtc_codes[i].DTCLowByte; + diagnosticDTC->dataResponse[size + 3] = dtc_state_error[i] & (diagnosticDTC->mask); + size += 4; + } + } + } + + + osMutexRelease(env->access); + } else { + LoggerInfoStatic(LOGGER, LOG_SIGN, "Access error diagnostic_UDS_ReadDTCInformation_19_dtc"); + } + + return size; +} + + +uint32_t diagnostic_UDS_ReadDTCSupportDTC_19_dtc(tDiagnostic *env, tDiagnosticDTC *diagnosticDTC) { + + uint32_t size = 0; + + if (osMutexAcquire(env->access, 5000) == osOK) { + + for (uint8_t i = 0; i < COUNT_DTC_CODE_ERROR; ++i) { + + diagnosticDTC->dataResponse[size] = dtc_codes[i].DTCHighByte; + diagnosticDTC->dataResponse[size + 1] = dtc_codes[i].DTCMiddleByte; + diagnosticDTC->dataResponse[size + 2] = dtc_codes[i].DTCLowByte; + diagnosticDTC->dataResponse[size + 3] = 0; + size += 4; + } + + osMutexRelease(env->access); + } else { + LoggerInfoStatic(LOGGER, LOG_SIGN, "Access error diagnostic_UDS_ReadDTCSupportDTC_19_dtc"); + } + + return size; +} + + +void set_NoBitsDTC(tDiagnostic *env, bool noBitsDTC) { + if (osMutexAcquire(env->access, 5000) == osOK) { + + env->isNoBitsDTC = noBitsDTC; + memcpy(dtc_state_FIX_error, dtc_state_error, sizeof(dtc_state_error)); + + osMutexRelease(env->access); + } else { + LoggerInfoStatic(LOGGER, LOG_SIGN, "Access error setBitsDTC"); + } +} + +void set_Dtc_state(tDiagnostic *env) { + if (osMutexAcquire(env->access, 5000) == osOK) { + memcpy(&dtc_state_error, &rtY.dtc_state_error_model, sizeof(dtc_state_error)); + osMutexRelease(env->access); + } else { + LoggerErrorStatic(LOGGER, LOG_SIGN, "Access error set_Dtc_state_error"); + } +} + diff --git a/MODULES/HVAC_M7_StatusData/DiagnosticTask.h b/MODULES/HVAC_M7_StatusData/DiagnosticTask.h new file mode 100644 index 0000000..1a2632f --- /dev/null +++ b/MODULES/HVAC_M7_StatusData/DiagnosticTask.h @@ -0,0 +1,35 @@ +// +// Created by cfif on 23.01.2026. +// + +#ifndef HVAC_M7_DIAGNOSTICTASK_H +#define HVAC_M7_DIAGNOSTICTASK_H + +#include +#include "LoggerInterface.h" + + +typedef struct { + uint8_t mask; + uint8_t *dataResponse; +} tDiagnosticDTC; + +typedef struct { + osMutexId_t access; + tLoggerInterface *logger; + + bool isNoBitsDTC; + +} tDiagnostic; + +void Diagnostic_Init(tDiagnostic *env, tLoggerInterface *logger); + +void set_NoBitsDTC(tDiagnostic *env, bool noBitsDTC); +void set_Dtc_state(tDiagnostic *env); + +uint32_t diagnostic_ClearDiagnosticInformation_14(tDiagnostic *env); +uint32_t diagnostic_UDS_ReadDTCInformation_19_count(tDiagnostic *env, tDiagnosticDTC *diagnosticDTC); +uint32_t diagnostic_UDS_ReadDTCInformation_19_dtc(tDiagnostic *env, tDiagnosticDTC *diagnosticDTC); +uint32_t diagnostic_UDS_ReadDTCSupportDTC_19_dtc(tDiagnostic *env, tDiagnosticDTC *diagnosticDTC); + +#endif //HVAC_M7_DIAGNOSTICTASK_H diff --git a/MODULES/HVAC_M7_StatusData/StatusData.c b/MODULES/HVAC_M7_StatusData/StatusData.c new file mode 100644 index 0000000..ea1e720 --- /dev/null +++ b/MODULES/HVAC_M7_StatusData/StatusData.c @@ -0,0 +1,1667 @@ +// +// Created by cfif on 03.12.2025. +// +#include "StatusData.h" + +tStatusData statusData; + +//------------------------------------------------------------READ-------------------------------------------------------------------------------------------- +//------------------------------------------------------------READ-------------------------------------------------------------------------------------------- +//------------------------------------------------------------READ-------------------------------------------------------------------------------------------- +//------------------------------------------------------------READ-------------------------------------------------------------------------------------------- +//------------------------------------------------------------READ-------------------------------------------------------------------------------------------- +//------------------------------------------------------------READ-------------------------------------------------------------------------------------------- + +const eUds_ReadDataByIdentifier_22_com uds_ReadDataByIdentifier_22_com_CF[256] = { + {&statusData.ecu.Status_CCU_Configuration, sizeof(statusData.ecu.Status_CCU_Configuration), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCF00 : Status_CCU_Configuration"}, + {&statusData.Status_Sensor, sizeof(statusData.Status_Sensor), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCF01 : Status_Sensor"}, + {&statusData.Status_Actuator_DoorsActuator_FB, sizeof(statusData.Status_Actuator_DoorsActuator_FB), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCF02 : Status_Actuator_DoorsActuator_FB"}, + {&statusData.Status_Duct_Tgt_FB, sizeof(statusData.Status_Duct_Tgt_FB), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCF03 : Status_Duct_Tgt"}, + {&statusData.Status_Eva_Tgt_FB, sizeof(statusData.Status_Eva_Tgt_FB), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCF04 : Status_Eva_Tgt"}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {&statusData.Status_Actuator_DoorsActuator_FB, sizeof(statusData.Status_Actuator_DoorsActuator_FB), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCF50 : Status_Actuator_DoorsActuator"}, + {&statusData.Status_IO_FB, sizeof(statusData.Status_IO_FB), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCF51 : Status_IO"}, + {&statusData.Status_Pwm_FB, sizeof(statusData.Status_Pwm_FB), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCF52 : Status_Pwm"}, + {&statusData.Status_eComp_FB, sizeof(statusData.Status_eComp_FB), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCF53 : Status_eComp"}, + {&statusData.Status_External_FB, sizeof(statusData.Status_External_FB), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCF54 : Status_External"}, + {&statusData.Status_EMS_FB, sizeof(statusData.Status_EMS_FB), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCF55 : Status_EMS"}, + {&statusData.Status_Ionizer_Aroma_FB, sizeof(statusData.Status_Ionizer_Aroma_FB), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCF56 : Status_Ionizer_Aroma"}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {&statusData.Status_Actuator_DoorsActuator_FB, sizeof(statusData.Status_Actuator_DoorsActuator_FB.Motor_Def), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCF60 : Status_Actuator_DoorsActuator.Motor_Def"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator_FB + + 2, sizeof(statusData.Status_Actuator_DoorsActuator_FB.Motor_Vent_SFL), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCF61 : Status_Actuator_DoorsActuator.Motor_Vent_SFL"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator_FB + + 4, sizeof(statusData.Status_Actuator_DoorsActuator_FB.Motor_Vent_CFL), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCF62 : Status_Actuator_DoorsActuator.Motor_Vent_CFL"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator_FB + + 6, sizeof(statusData.Status_Actuator_DoorsActuator_FB.Motor_Foot_1FL), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCF63 : Status_Actuator_DoorsActuator.Motor_Foot_1FL"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator_FB + + 8, sizeof(statusData.Status_Actuator_DoorsActuator_FB.Motor_Foot_2FL), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCF64 : Status_Actuator_DoorsActuator.Motor_Foot_2FL"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator_FB + + 10, sizeof(statusData.Status_Actuator_DoorsActuator_FB.Motor_Vent_CFR), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCF65 : Status_Actuator_DoorsActuator.Motor_Vent_CFR"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator_FB + + 12, sizeof(statusData.Status_Actuator_DoorsActuator_FB.Motor_Vent_SFR), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCF66 : Status_Actuator_DoorsActuator.Motor_Vent_SFR"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator_FB + + 14, sizeof(statusData.Status_Actuator_DoorsActuator_FB.Motor_Foot_1FR), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCF67 : Status_Actuator_DoorsActuator.Motor_Foot_1FR"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator_FB + + 16, sizeof(statusData.Status_Actuator_DoorsActuator_FB.Motor_Foot_2FR), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCF68 : Status_Actuator_DoorsActuator.Motor_Foot_2FR"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator_FB + + 18, sizeof(statusData.Status_Actuator_DoorsActuator_FB.Motor_Vent_SRL), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCF69 : Status_Actuator_DoorsActuator.Motor_Vent_SRL"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator_FB + + 20, sizeof(statusData.Status_Actuator_DoorsActuator_FB.Motor_Vent_CRL), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCF6A : Status_Actuator_DoorsActuator.Motor_Vent_CRL"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator_FB + + 22, sizeof(statusData.Status_Actuator_DoorsActuator_FB.Motor_Foot_RL), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCF6B : Status_Actuator_DoorsActuator.Motor_Foot_RL"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator_FB + + 24, sizeof(statusData.Status_Actuator_DoorsActuator_FB.Motor_Vent_CRR), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCF6C : Status_Actuator_DoorsActuator.Motor_Vent_CRR"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator_FB + + 26, sizeof(statusData.Status_Actuator_DoorsActuator_FB.Motor_Vent_SRR), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCF6D : Status_Actuator_DoorsActuator.Motor_Vent_SRR"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator_FB + + 28, sizeof(statusData.Status_Actuator_DoorsActuator_FB.Motor_Foot_RR), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCF6E : Status_Actuator_DoorsActuator.Motor_Foot_RR"}, + {NULL, 0, 0, 0, ""}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator_FB + + 30, sizeof(statusData.Status_Actuator_DoorsActuator_FB.Motor_Temp1_FL), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCF70 : Status_Actuator_DoorsActuator.Motor_Temp1_FL"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator_FB + + 32, sizeof(statusData.Status_Actuator_DoorsActuator_FB.Motor_Temp2_FL), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCF71 : Status_Actuator_DoorsActuator.Motor_Temp2_FL"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator_FB + + 34, sizeof(statusData.Status_Actuator_DoorsActuator_FB.Motor_Temp1_FR), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCF72 : Status_Actuator_DoorsActuator.Motor_Temp1_FR"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator_FB + + 36, sizeof(statusData.Status_Actuator_DoorsActuator_FB.Motor_Temp2_FR), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCF73 : Status_Actuator_DoorsActuator.Motor_Temp2_FR"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator_FB + + 38, sizeof(statusData.Status_Actuator_DoorsActuator_FB.Motor_Temp_RL), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCF74 : Status_Actuator_DoorsActuator.Motor_Temp_RL"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator_FB + + 40, sizeof(statusData.Status_Actuator_DoorsActuator_FB.Motor_Temp_RR), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCF75 : Status_Actuator_DoorsActuator.Motor_Temp_RR"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator_FB + + 42, sizeof(statusData.Status_Actuator_DoorsActuator_FB.Motor_REC), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCF76 : Status_Actuator_DoorsActuator.Motor_REC"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator_FB + + 44, sizeof(statusData.Status_Actuator_DoorsActuator_FB.Motor_OSA), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCF77 : Status_Actuator_DoorsActuator.Motor_OSA"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator_FB + + 46, sizeof(statusData.Status_Actuator_DoorsActuator_FB.Motor_SealingValve), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCF78 : Status_Actuator_DoorsActuator.Motor_SealingValve"}, + {&statusData.Status_Duct_Select_FB, sizeof(statusData.Status_Duct_Select_FB), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCF79 : Status_Duct_Select"}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {&statusData.Status_Activated_Cal_Num, sizeof(statusData.Status_Activated_Cal_Num), perm_session_defaultSession_extendedDiagnosticSession, false, "0xCFFE : Status_Activated_Cal_Num"}, + {&statusData.ecu.Internal_SW_Version, sizeof(statusData.ecu.Internal_SW_Version), perm_session_defaultSession_extendedDiagnosticSession, false, "Internal_SW_Version"} +}; + + +const eUds_ReadDataByIdentifier_22_com uds_ReadDataByIdentifier_22_com_F1[256] = { + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {statusData.ecu.Software_classification_identification, sizeof(statusData.ecu.Software_classification_identification), perm_session_all, false, "0xF151 : Software classification identification"}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {&statusData.ecu.Tester_Fingerprint, sizeof(statusData.ecu.Tester_Fingerprint), perm_session_all, false, "0xF15A : Tester_Fingerprint"}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {&statusData.ecu.Boot_SW_Fingerprint, sizeof(statusData.ecu.Boot_SW_Fingerprint), perm_session_all, false, "0xF183 : Boot SW Fingerprint"}, + {&statusData.ecu.Application_SW_Fingerprint, sizeof(statusData.ecu.Application_SW_Fingerprint), perm_session_all, false, "0xF184 : Application SW Fingerprint"}, + {NULL, 0, 0, 0, ""}, + {&statusData.Status_Active_Diagnostic_Session, sizeof(statusData.Status_Active_Diagnostic_Session), perm_session_all, false, "0xF186 : Active Diagnostic Session"}, + {&statusData.ecu.Spare_Part_Number, sizeof(statusData.ecu.Spare_Part_Number), perm_session_all, false, "0xF187 : Spare Part Number"}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {statusData.ecu.Serial_Number, sizeof(statusData.ecu.Serial_Number), perm_session_all, false, "0xF18C : Serial Number"}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {statusData.ecu.Vehicle_Identification, sizeof(statusData.ecu.Vehicle_Identification), perm_session_all, false, "0xF190 : Vehicle Identification"}, + {statusData.ecu.ECU_hardware_number_NAMI, sizeof(statusData.ecu.ECU_hardware_number_NAMI), perm_session_all, false, "0xF191 : ECU hardware number (NAMI)"}, + {statusData.ecu.ECU_hardware_number_ECU_supplier, sizeof(statusData.ecu.ECU_hardware_number_ECU_supplier), perm_session_all, false, "0xF192 : ECU hardware number (ECU supplier)"}, + {NULL, 0, 0, 0, ""}, + {statusData.ecu.ECU_software_number_ECU_supplier, sizeof(statusData.ecu.ECU_software_number_ECU_supplier), perm_session_all, false, "0xF194 : ECU software number (ECU supplier)"}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {statusData.ecu.ECU_boot_software_identification_ECU_supplier, sizeof(statusData.ecu.ECU_boot_software_identification_ECU_supplier), perm_session_all, false, "0xF1F4 : ECU boot software identification (ECU supplier)"}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""} +}; + +//------------------------------------------------------------WRITE-------------------------------------------------------------------------------------------- +//------------------------------------------------------------WRITE-------------------------------------------------------------------------------------------- +//------------------------------------------------------------WRITE-------------------------------------------------------------------------------------------- +//------------------------------------------------------------WRITE-------------------------------------------------------------------------------------------- +//------------------------------------------------------------WRITE-------------------------------------------------------------------------------------------- +//------------------------------------------------------------WRITE-------------------------------------------------------------------------------------------- + + +const eUds_WriteDataByIdentifier_2E_com uds_WriteDataByIdentifier_2E_com_CF[256] = { + {&statusData.ecu.Status_CCU_Configuration, sizeof(statusData.ecu.Status_CCU_Configuration), perm_session_extendedDiagnosticSession, true, "0xCF00 : Status_CCU_Configuration"}, + {NULL, sizeof(statusData.Status_Sensor), 0, 0, "0xCF01 : Status_Sensor"}, + {NULL, sizeof(statusData.Status_Actuator_DoorsActuator), 0, 0, "0xCF02 : Status_Actuator_DoorsActuator_FB"}, + {NULL, sizeof(statusData.Status_Duct_Tgt), 0, 0, "0xCF03 : Status_Duct_Tgt"}, + {NULL, sizeof(statusData.Status_Eva_Tgt), 0, 0, "0xCF04 : Status_Eva_Tgt"}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, sizeof(statusData.Status_Actuator_DoorsActuator), 0, 0, "0xCF50 : Status_Actuator_DoorsActuator"}, + {NULL, sizeof(statusData.Status_IO), 0, 0, "0xCF51 : Status_IO"}, + {NULL, sizeof(statusData.Status_Pwm), 0, 0, "0xCF52 : Status_Pwm"}, + {NULL, sizeof(statusData.Status_eComp), 0, 0, "0xCF53 : Status_eComp"}, + {NULL, sizeof(statusData.Status_External), 0, 0, "0xCF54 : Status_External"}, + {NULL, sizeof(statusData.Status_EMS), 0, 0, "0xCF55 : Status_EMS"}, + {NULL, sizeof(statusData.Status_Ionizer_Aroma), 0, 0, "0xCF56 : Status_Ionizer_Aroma"}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Def), 0, 0, "0xCF60 : Status_Actuator_DoorsActuator.Motor_Def"}, + {NULL, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Vent_SFL), 0, 0, "0xCF61 : Status_Actuator_DoorsActuator.Motor_Vent_SFL"}, + {NULL, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Vent_CFL), 0, 0, "0xCF62 : Status_Actuator_DoorsActuator.Motor_Vent_CFL"}, + {NULL, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Foot_1FL), 0, 0, "0xCF63 : Status_Actuator_DoorsActuator.Motor_Foot_1FL"}, + {NULL, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Foot_2FL), 0, 0, "0xCF64 : Status_Actuator_DoorsActuator.Motor_Foot_2FL"}, + {NULL, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Vent_CFR), 0, 0, "0xCF65 : Status_Actuator_DoorsActuator.Motor_Vent_CFR"}, + {NULL, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Vent_SFR), 0, 0, "0xCF66 : Status_Actuator_DoorsActuator.Motor_Vent_SFR"}, + {NULL, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Foot_1FR), 0, 0, "0xCF67 : Status_Actuator_DoorsActuator.Motor_Foot_1FR"}, + {NULL, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Foot_2FR), 0, 0, "0xCF68 : Status_Actuator_DoorsActuator.Motor_Foot_2FR"}, + {NULL, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Vent_SRL), 0, 0, "0xCF69 : Status_Actuator_DoorsActuator.Motor_Vent_SRL"}, + {NULL, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Vent_CRL), 0, 0, "0xCF6A : Status_Actuator_DoorsActuator.Motor_Vent_CRL"}, + {NULL, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Foot_RL), 0, 0, "0xCF6B : Status_Actuator_DoorsActuator.Motor_Foot_RL"}, + {NULL, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Vent_CRR), 0, 0, "0xCF6C : Status_Actuator_DoorsActuator.Motor_Vent_CRR"}, + {NULL, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Vent_SRR), 0, 0, "0xCF6D : Status_Actuator_DoorsActuator.Motor_Vent_SRR"}, + {NULL, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Foot_RR), 0, 0, "0xCF6E : Status_Actuator_DoorsActuator.Motor_Foot_RR"}, + {NULL, 0, 0, 0, ""}, + {NULL, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Temp1_FL), 0, 0, "0xCF70 : Status_Actuator_DoorsActuator.Motor_Temp1_FL"}, + {NULL, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Temp2_FL), 0, 0, "0xCF71 : Status_Actuator_DoorsActuator.Motor_Temp2_FL"}, + {NULL, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Temp1_FR), 0, 0, "0xCF72 : Status_Actuator_DoorsActuator.Motor_Temp1_FR"}, + {NULL, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Temp2_FR), 0, 0, "0xCF73 : Status_Actuator_DoorsActuator.Motor_Temp2_FR"}, + {NULL, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Temp_RL), 0, 0, "0xCF74 : Status_Actuator_DoorsActuator.Motor_Temp_RL"}, + {NULL, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Temp_RR), 0, 0, "0xCF75 : Status_Actuator_DoorsActuator.Motor_Temp_RR"}, + {NULL, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_REC), 0, 0, "0xCF76 : Status_Actuator_DoorsActuator.Motor_REC"}, + {NULL, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_OSA), 0, 0, "0xCF77 : Status_Actuator_DoorsActuator.Motor_OSA"}, + {NULL, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_SealingValve), 0, 0, "0xCF78 : Status_Actuator_DoorsActuator.Motor_SealingValve"}, + {NULL, sizeof(statusData.Status_Duct_Select), 0, 0, "0xCF79 : Status_Duct_Select"}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, sizeof(statusData.Status_Activated_Cal_Num), 0, 0, "0xCFFE : Status_Activated_Cal_Num"}, + {NULL, sizeof(statusData.ecu.Internal_SW_Version), 0, 0, "Internal_SW_Version"} +}; + +const eUds_WriteDataByIdentifier_2E_com uds_WriteDataByIdentifier_2E_com_F1[256] = { + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, sizeof(statusData.ecu.Software_classification_identification), 0, 0, "0xF151 : Software classification identification"}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {&statusData.ecu.Tester_Fingerprint, sizeof(statusData.ecu.Tester_Fingerprint), perm_session_programmingSession, true, "0xF15A : Tester_Fingerprint"}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, sizeof(statusData.ecu.Boot_SW_Fingerprint), 0, 0, "0xF183 : Boot SW Fingerprint"}, + {NULL, sizeof(statusData.ecu.Application_SW_Fingerprint), 0, 0, "0xF184 : Application SW Fingerprint"}, + {NULL, 0, 0, 0, ""}, + {NULL, sizeof(statusData.Status_Active_Diagnostic_Session), 0, 0, "0xF186 : Active Diagnostic Session"}, + {NULL, 0, 0, 0, "0xF187 : Spare Part Number"}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {statusData.ecu.Serial_Number, sizeof(statusData.ecu.Serial_Number), perm_session_extendedDiagnosticSession, true, "0xF18C : Serial Number"}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, sizeof(statusData.ecu.Vehicle_Identification), 0, 0, "0xF190 : Vehicle Identification"}, + {NULL, sizeof(statusData.ecu.ECU_hardware_number_NAMI), 0, 0, "0xF191 : ECU hardware number (NAMI)"}, + {NULL, sizeof(statusData.ecu.ECU_hardware_number_ECU_supplier), 0, 0, "0xF192 : ECU hardware number (ECU supplier)"}, + {NULL, 0, 0, 0, ""}, + {NULL, sizeof(statusData.ecu.ECU_software_number_ECU_supplier), 0, 0, "0xF194 : ECU software number (ECU supplier)"}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, sizeof(statusData.ecu.ECU_boot_software_identification_ECU_supplier), 0, 0, "0xF1F4 : ECU boot software identification (ECU supplier)"}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""} +}; + + +//------------------------------------------------------------IO-------------------------------------------------------------------------------------------- +//------------------------------------------------------------IO-------------------------------------------------------------------------------------------- +//------------------------------------------------------------IO-------------------------------------------------------------------------------------------- +//------------------------------------------------------------IO-------------------------------------------------------------------------------------------- +//------------------------------------------------------------IO-------------------------------------------------------------------------------------------- +//------------------------------------------------------------IO-------------------------------------------------------------------------------------------- + +const eUds_IoDataByIdentifier_2F_com uds_IoDataByIdentifier_2F_com_CF[256] = { + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {&statusData.Status_Actuator_DoorsActuator, sizeof(statusData.Status_Actuator_DoorsActuator), perm_session_extendedDiagnosticSession, true, "0xCF50 : Status_Actuator_DoorsActuator"}, + {&statusData.Status_IO, sizeof(statusData.Status_IO), perm_session_extendedDiagnosticSession, true, "0xCF51 : Status_IO"}, + {&statusData.Status_Pwm, sizeof(statusData.Status_Pwm), perm_session_extendedDiagnosticSession, true, "0xCF52 : Status_Pwm"}, + {&statusData.Status_eComp, sizeof(statusData.Status_eComp), perm_session_extendedDiagnosticSession, true, "0xCF53 : Status_eComp"}, + {&statusData.Status_External, sizeof(statusData.Status_External), perm_session_extendedDiagnosticSession, true, "0xCF54 : Status_External"}, + {&statusData.Status_EMS, sizeof(statusData.Status_EMS), perm_session_extendedDiagnosticSession, true, "0xCF55 : Status_EMS"}, + {&statusData.Status_Ionizer_Aroma, sizeof(statusData.Status_Ionizer_Aroma), perm_session_extendedDiagnosticSession, true, "0xCF56 : Status_Ionizer_Aroma"}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {&statusData.Status_Actuator_DoorsActuator, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Def), perm_session_extendedDiagnosticSession, true, "0xCF60 : Status_Actuator_DoorsActuator.Motor_Def"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator + + 2, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Vent_SFL), perm_session_extendedDiagnosticSession, true, "0xCF61 : Status_Actuator_DoorsActuator.Motor_Vent_SFL"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator + + 4, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Vent_CFL), perm_session_extendedDiagnosticSession, true, "0xCF62 : Status_Actuator_DoorsActuator.Motor_Vent_CFL"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator + + 6, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Foot_1FL), perm_session_extendedDiagnosticSession, true, "0xCF63 : Status_Actuator_DoorsActuator.Motor_Foot_1FL"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator + + 8, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Foot_2FL), perm_session_extendedDiagnosticSession, true, "0xCF64 : Status_Actuator_DoorsActuator.Motor_Foot_2FL"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator + + 10, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Vent_CFR), perm_session_extendedDiagnosticSession, true, "0xCF65 : Status_Actuator_DoorsActuator.Motor_Vent_CFR"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator + + 12, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Vent_SFR), perm_session_extendedDiagnosticSession, true, "0xCF66 : Status_Actuator_DoorsActuator.Motor_Vent_SFR"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator + + 14, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Foot_1FR), perm_session_extendedDiagnosticSession, true, "0xCF67 : Status_Actuator_DoorsActuator.Motor_Foot_1FR"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator + + 16, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Foot_2FR), perm_session_extendedDiagnosticSession, true, "0xCF68 : Status_Actuator_DoorsActuator.Motor_Foot_2FR"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator + + 18, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Vent_SRL), perm_session_extendedDiagnosticSession, true, "0xCF69 : Status_Actuator_DoorsActuator.Motor_Vent_SRL"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator + + 20, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Vent_CRL), perm_session_extendedDiagnosticSession, true, "0xCF6A : Status_Actuator_DoorsActuator.Motor_Vent_CRL"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator + + 22, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Foot_RL), perm_session_extendedDiagnosticSession, true, "0xCF6B : Status_Actuator_DoorsActuator.Motor_Foot_RL"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator + + 24, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Vent_CRR), perm_session_extendedDiagnosticSession, true, "0xCF6C : Status_Actuator_DoorsActuator.Motor_Vent_CRR"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator + + 26, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Vent_SRR), perm_session_extendedDiagnosticSession, true, "0xCF6D : Status_Actuator_DoorsActuator.Motor_Vent_SRR"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator + + 28, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Foot_RR), perm_session_extendedDiagnosticSession, true, "0xCF6E : Status_Actuator_DoorsActuator.Motor_Foot_RR"}, + {NULL, 0, 0, 0, ""}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator + + 30, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Temp1_FL), perm_session_extendedDiagnosticSession, true, "0xCF70 : Status_Actuator_DoorsActuator.Motor_Temp1_FL"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator + + 32, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Temp2_FL), perm_session_extendedDiagnosticSession, true, "0xCF71 : Status_Actuator_DoorsActuator.Motor_Temp2_FL"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator + + 34, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Temp1_FR), perm_session_extendedDiagnosticSession, true, "0xCF72 : Status_Actuator_DoorsActuator.Motor_Temp1_FR"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator + + 36, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Temp2_FR), perm_session_extendedDiagnosticSession, true, "0xCF73 : Status_Actuator_DoorsActuator.Motor_Temp2_FR"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator + + 38, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Temp_RL), perm_session_extendedDiagnosticSession, true, "0xCF74 : Status_Actuator_DoorsActuator.Motor_Temp_RL"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator + + 40, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_Temp_RR), perm_session_extendedDiagnosticSession, true, "0xCF75 : Status_Actuator_DoorsActuator.Motor_Temp_RR"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator + + 42, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_REC), perm_session_extendedDiagnosticSession, true, "0xCF76 : Status_Actuator_DoorsActuator.Motor_REC"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator + + 44, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_OSA), perm_session_extendedDiagnosticSession, true, "0xCF77 : Status_Actuator_DoorsActuator.Motor_OSA"}, + {(uint8_t *) &statusData.Status_Actuator_DoorsActuator + + 46, sizeof(statusData.Status_Actuator_DoorsActuator.Motor_SealingValve), perm_session_extendedDiagnosticSession, true, "0xCF78 : Status_Actuator_DoorsActuator.Motor_SealingValve"}, + {&statusData.Status_Duct_Select, sizeof(statusData.Status_Duct_Select), perm_session_extendedDiagnosticSession, true, "0xCF79 : Status_Duct_Select"}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""} +}; + +const eUds_IoDataByIdentifier_2F_com uds_IoDataByIdentifier_2F_com_F1[256] = { + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 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+ {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""}, + {NULL, 0, 0, 0, ""} +}; + +static void reverse_copy(void *dst, const void *src, size_t size) { + + memcpy(dst, src, size); +// const unsigned char *s = (const unsigned char*)src; +// unsigned char *d = (unsigned char*)dst; +// for (size_t i = 0; i < size; i++) { +// d[i] = s[size - 1 - i]; +// } +} + +void setDefaultStatus() { + reverse_copy(statusData.ecu.Software_classification_identification, "1100-100-30-UCC", sizeof(statusData.ecu.Software_classification_identification)); + reverse_copy(statusData.ecu.Spare_Part_Number, "440003281 \0DD412300-386 ", sizeof(statusData.ecu.Spare_Part_Number)); +// memset(statusData.ecu.Serial_Number, 0xFF, sizeof(statusData.ecu.Serial_Number)); + memset(statusData.ecu.Vehicle_Identification, 0x20, sizeof(statusData.ecu.Vehicle_Identification)); + reverse_copy(statusData.ecu.ECU_hardware_number_ECU_supplier, "170400 ", sizeof(statusData.ecu.ECU_hardware_number_ECU_supplier)); + reverse_copy(statusData.ecu.ECU_software_number_ECU_supplier, "11", sizeof(statusData.ecu.ECU_software_number_ECU_supplier)); + reverse_copy(statusData.ecu.ECU_boot_software_identification_ECU_supplier, "11", sizeof(statusData.ecu.ECU_boot_software_identification_ECU_supplier)); + reverse_copy(statusData.ecu.ECU_hardware_number_NAMI, "412300-3868100-30-011-0-00 ", sizeof(statusData.ecu.ECU_hardware_number_NAMI)); + + + memset(&statusData.Status_Sensor, 0xFF, sizeof(tStatus_Sensor)); +// memset(&statusData.Status_Actuator_DoorsActuator_FB, 0xFF, sizeof(tStatus_Actuator)); + memset(&statusData.Status_Actuator_DoorsActuator, 0xFF, sizeof(tStatus_Actuator)); + memset(&statusData.Status_Duct_Tgt, 0xFF, sizeof(tStatus_Duct_Tgt)); + memset(&statusData.Status_Eva_Tgt, 0xFF, sizeof(tStatus_Eva_Tgt)); + memset(&statusData.Status_Activated_Cal_Num, 0xFF, sizeof(tStatus_Activated_Cal_Num)); + memset(&statusData.Status_IO, 0xFF, sizeof(tStatus_IO)); + memset(&statusData.Status_Pwm, 0xFF, sizeof(tStatus_Pwm)); + memset(&statusData.Status_eComp, 0xFF, sizeof(tStatus_eComp)); + memset(&statusData.Status_External, 0xFF, sizeof(tStatus_External)); + memset(&statusData.Status_EMS, 0xFF, sizeof(tStatus_EMS)); + memset(&statusData.Status_Ionizer_Aroma, 0xFF, sizeof(tStatus_Ionizer_Aroma)); + + statusData.Status_Active_Diagnostic_Session.Active_Diagnostic_Session = 1; +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_StatusData/StatusData.h b/MODULES/HVAC_M7_StatusData/StatusData.h new file mode 100644 index 0000000..66b9b95 --- /dev/null +++ b/MODULES/HVAC_M7_StatusData/StatusData.h @@ -0,0 +1,500 @@ +// +// Created by cfif on 03.12.2025. +// + +#ifndef HVAC_M7_STATUSDATA_H +#define HVAC_M7_STATUSDATA_H + +#include "stdint.h" +#include "DataNonVolatile.h" + +typedef enum { + AQS_CLEAR_AIR_LEVEL = 0, + AQS_LEVEL_1_LOW = 1, + AQS_LEVEL_2_MIDL = 2, + AQS_LEVEL_3_SIGNIFICANT = 3, + AQS_LEVEL_4_HIGH = 4, + AQS_LEVEL_5_VERY = 5, + AQS_ERROR = 0xFF +} eAQS; + +typedef enum { + AROMA_OFF = 0, + AROMA_MODE1 = 1, + AROMA_MODE2 = 2, + AROMA_MODE3 = 3 +} eAromatizationIntensivity; + +typedef enum { + perm_session_defaultSession = 0x1, + perm_session_programmingSession = 0x2, + perm_session_extendedDiagnosticSession = 0x3, + perm_session_defaultSession_programmingSession = 0x4, + perm_session_defaultSession_extendedDiagnosticSession = 0x5, + perm_session_extendedDiagnosticSession_programmingSession = 0x6, + perm_session_all = 0x7 +} tPermissionSession; + +#pragma scalar_storage_order big-endian + +// 1 Byte; Float; 2 significant digits y = (1/10)x V; Lower limit (phys): 0 V; Upper limit (phys): 25.5 V; +// 2 Byte; Float; 1 significant digits; HighLow (Motorola) y = (1/10)x -40 °C; Lower limit (phys): -40 °C; Upper limit (phys): 6513.5 °C; + +typedef struct __attribute__ ((packed)) { + uint8_t Ignition; + uint8_t Battery; + uint16_t AMB; + uint16_t Incar_FL; + uint16_t Incar_FR; + uint16_t Incar_RL; + uint16_t Incar_RR; + uint16_t Eva_F; + uint16_t Eva_R; + uint16_t Pressure; + uint16_t Duct_FL_Upper; + uint16_t Duct_FL_Lower; + uint16_t Duct_FR_Upper; + uint16_t Duct_FR_Lower; + uint16_t Duct_RL; + uint16_t Duct_RR; + uint16_t Duct_Side_FL; + uint16_t Duct_Side_FR; + uint16_t Duct_Side_RL; + uint16_t Duct_Side_RR; + eAQS AQS; +} tStatus_Sensor; + + +// 2 Byte; Float; 1 significant digits; HighLow (Motorola) [0x00..0x03E8] ; y = (1/10)x %; +// Lower limit (phys): 0 %; Upper limit (phys): 100 %; Invalid values: [0x03E9..0xFFFE] Invalid signal (Invalid) [0xFFFF] Not implemented (Not implemented) + + +typedef struct __attribute__ ((packed)) { + uint16_t Motor_Def; + uint16_t Motor_Vent_SFL; + uint16_t Motor_Vent_CFL; + uint16_t Motor_Foot_1FL; + uint16_t Motor_Foot_2FL; + uint16_t Motor_Vent_CFR; + uint16_t Motor_Vent_SFR; + uint16_t Motor_Foot_1FR; + uint16_t Motor_Foot_2FR; + uint16_t Motor_Vent_SRL; + uint16_t Motor_Vent_CRL; + uint16_t Motor_Foot_RL; + uint16_t Motor_Vent_CRR; + uint16_t Motor_Vent_SRR; + uint16_t Motor_Foot_RR; + + uint16_t Motor_Temp1_FL; + uint16_t Motor_Temp2_FL; + uint16_t Motor_Temp1_FR; + uint16_t Motor_Temp2_FR; + uint16_t Motor_Temp_RL; + uint16_t Motor_Temp_RR; + uint16_t Motor_REC; + uint16_t Motor_OSA; + uint16_t Motor_SealingValve; +} tStatus_Actuator; + + +// 2 Byte; Float; 1 significant digits; HighLow (Motorola) y = (1/10)x -40 °C; Lower limit (phys): -40 °C; Upper limit (phys): 6513.5 °C; + +typedef struct __attribute__ ((packed)) { + uint16_t DuctTgt_Vent_FL; + uint16_t DuctTgt_Foot_FL; + uint16_t DuctTgt_Vent_FR; + uint16_t DuctTgt_Foot_FR; + uint16_t DuctTgt_RL; + uint16_t DuctTgt_RR; +} tStatus_Duct_Tgt; + + +// 2 Byte; Float; 1 significant digits; HighLow (Motorola) y = (1/10)x -40 °C; Lower limit (phys): -40 °C; Upper limit (phys): 6513.5 °C; + +typedef struct __attribute__ ((packed)) { + uint16_t EvaTgt_F; + uint16_t EvaTgt_R; +} tStatus_Eva_Tgt; + + +// 0 = Off!0 = On 1 Byte [0x00] Off [0x01..0xFF] On; Inverse value: 0x01 + +typedef struct __attribute__ ((packed)) { + uint8_t _2_Way_Valve; + uint8_t IncarMotor_Front; + uint8_t IncarMotor_Rear; + uint8_t ShutOff_Chiller; + uint8_t ShutOff_Front; + uint8_t ShutOff_Rear; + uint8_t PTC_1; + uint8_t PTC_2; +} tStatus_IO; + + +// 2 Byte; Float; 1 significant digits; HighLow (Motorola) [0x00..0x03E8] ; y = (1/10)x %; Lower limit (phys): 0 %; Upper limit (phys): 100 %; Invalid values: [0x03E9..0xFFFE] Invalid signal (Invalid) [0xFFFF] Not implemented (Not implemented) + +typedef struct __attribute__ ((packed)) { + uint16_t Pwm_Front; + uint16_t Pwm_Rear; +} tStatus_Pwm; + +typedef struct __attribute__ ((packed)) { + // 0 = Off!0 = On + //1 Byte + //[0x00] Off + //[0x01..0xFF] On; Inverse value: 0x01 + uint8_t eComp_Statue_Request; + //1 Byte + //y = 50x ; Lower limit (phys): 0; Upper limit (phys): 12750; + uint8_t Pwm_Front; + // 0 = Off!0 = On + //1 Byte + //[0x00] Off + //[0x01..0xFF] On; Inverse value: 0x01 + uint8_t LowTempValve; +} tStatus_eComp; + + +// 2 Byte; Float; 1 significant digits; HighLow (Motorola) +//[0x00..0x03E8] ; y = (1/10)x %; Lower limit (phys): 0 %; Upper limit (phys): 100 %; +//Invalid values: +//[0x03E9..0xFFFE] Invalid signal (Invalid) +//[0xFFFF] Not implemented (Not implemented) + +typedef struct __attribute__ ((packed)) { + uint16_t CoolingFan; +} tStatus_External; + + +// 0 = Off!0 = On +//1 Byte +//[0x00] Off +//[0x01..0xFF] On; Inverse value: 0x01 + +typedef struct __attribute__ ((packed)) { + uint8_t EMS_Chiller_Req; +} tStatus_EMS; + + + +typedef struct __attribute__ ((packed)) { + // 0 = Off!0 = On + //1 Byte + //[0x00] Off + //[0x01..0xFF] On; Inverse value: 0x01 + uint8_t Ionizer; + eAromatizationIntensivity AromatizationIntensivity; +} tStatus_Ionizer_Aroma; + + +// 1 Byte [0x00] Central [0x01..0xFF] Side; Inverse value: 0x01 + +typedef struct __attribute__ ((packed)) { + uint8_t Duct_FL; + uint8_t Duct_FR; + uint8_t Duct_RL; + uint8_t Duct_RR; +} tStatus_Duct_Select; + +typedef struct __attribute__ ((packed)) { + // 2 Byte; HighLow (Motorola) + uint16_t Calibration_Num; + // Packet [4] Byte + //Data Objects: + //[0:0] Date year (yy), Unsigned (1Byte) + // - 02 – 99 + //[1:0] Date month (mm), Unsigned (1Byte) + // - 01 – 12 + //[2:0] Date day (dd), Unsigned (1Byte) + // - 01-31 + //[3:0] Revision, Unsigned (1Byte) + uint8_t Internal_Cal_Ver[4]; +} tStatus_Activated_Cal_Num; + +// 1 Byte +//[0x01] defaultSession +//[0x02] programmingSession +//[0x03] extendedDiagnosticSession +//Invalid values: +//[0x00] No signal (Not supported) +//[0x04..0x80] No signal (Not supported) +//[0x81..0x83] Undefined +//[0x84..0xFF] No signal (Not supported) + +typedef struct __attribute__ ((packed)) { + uint8_t Active_Diagnostic_Session; +} tStatus_Active_Diagnostic_Session; +#pragma scalar_storage_order little-endian + + + + + + + + + + +// 1 Byte; Float; 2 significant digits y = (1/10)x V; Lower limit (phys): 0 V; Upper limit (phys): 25.5 V; +// 2 Byte; Float; 1 significant digits; HighLow (Motorola) y = (1/10)x -40 °C; Lower limit (phys): -40 °C; Upper limit (phys): 6513.5 °C; + +typedef struct { + uint8_t Ignition; + uint8_t Battery; + uint16_t AMB; + uint16_t Incar_FL; + uint16_t Incar_FR; + uint16_t Incar_RL; + uint16_t Incar_RR; + uint16_t Eva_F; + uint16_t Eva_R; + uint16_t Pressure; + uint16_t Duct_FL_Upper; + uint16_t Duct_FL_Lower; + uint16_t Duct_FR_Upper; + uint16_t Duct_FR_Lower; + uint16_t Duct_RL; + uint16_t Duct_RR; + uint16_t Duct_Side_FL; + uint16_t Duct_Side_FR; + uint16_t Duct_Side_RL; + uint16_t Duct_Side_RR; + eAQS AQS; +} tStatus_Sensor_For_Model; + + +// 2 Byte; Float; 1 significant digits; HighLow (Motorola) [0x00..0x03E8] ; y = (1/10)x %; +// Lower limit (phys): 0 %; Upper limit (phys): 100 %; Invalid values: [0x03E9..0xFFFE] Invalid signal (Invalid) [0xFFFF] Not implemented (Not implemented) + + +typedef struct { + uint16_t Motor_Def; + uint16_t Motor_Vent_SFL; + uint16_t Motor_Vent_CFL; + uint16_t Motor_Foot_1FL; + uint16_t Motor_Foot_2FL; + uint16_t Motor_Vent_CFR; + uint16_t Motor_Vent_SFR; + uint16_t Motor_Foot_1FR; + uint16_t Motor_Foot_2FR; + uint16_t Motor_Vent_SRL; + uint16_t Motor_Vent_CRL; + uint16_t Motor_Foot_RL; + uint16_t Motor_Vent_CRR; + uint16_t Motor_Vent_SRR; + uint16_t Motor_Foot_RR; + + uint16_t Motor_Temp1_FL; + uint16_t Motor_Temp2_FL; + uint16_t Motor_Temp1_FR; + uint16_t Motor_Temp2_FR; + uint16_t Motor_Temp_RL; + uint16_t Motor_Temp_RR; + uint16_t Motor_REC; + uint16_t Motor_OSA; + uint16_t Motor_SealingValve; +} tStatus_Actuator_For_Model; + + +// 2 Byte; Float; 1 significant digits; HighLow (Motorola) y = (1/10)x -40 °C; Lower limit (phys): -40 °C; Upper limit (phys): 6513.5 °C; + +typedef struct { + uint16_t DuctTgt_Vent_FL; + uint16_t DuctTgt_Foot_FL; + uint16_t DuctTgt_Vent_FR; + uint16_t DuctTgt_Foot_FR; + uint16_t DuctTgt_RL; + uint16_t DuctTgt_RR; +} tStatus_Duct_Tgt_For_Model; + + +// 2 Byte; Float; 1 significant digits; HighLow (Motorola) y = (1/10)x -40 °C; Lower limit (phys): -40 °C; Upper limit (phys): 6513.5 °C; + +typedef struct { + uint16_t EvaTgt_F; + uint16_t EvaTgt_R; +} tStatus_Eva_Tgt_For_Model; + + +// 0 = Off!0 = On 1 Byte [0x00] Off [0x01..0xFF] On; Inverse value: 0x01 + +typedef struct { + uint8_t _2_Way_Valve; + uint8_t IncarMotor_Front; + uint8_t IncarMotor_Rear; + uint8_t ShutOff_Chiller; + uint8_t ShutOff_Front; + uint8_t ShutOff_Rear; + uint8_t PTC_1; + uint8_t PTC_2; +} tStatus_IO_For_Model; + + +// 2 Byte; Float; 1 significant digits; HighLow (Motorola) [0x00..0x03E8] ; y = (1/10)x %; Lower limit (phys): 0 %; Upper limit (phys): 100 %; Invalid values: [0x03E9..0xFFFE] Invalid signal (Invalid) [0xFFFF] Not implemented (Not implemented) + +typedef struct { + uint16_t Pwm_Front; + uint16_t Pwm_Rear; +} tStatus_Pwm_For_Model; + +typedef struct { + // 0 = Off!0 = On + //1 Byte + //[0x00] Off + //[0x01..0xFF] On; Inverse value: 0x01 + uint8_t eComp_Statue_Request; + //1 Byte + //y = 50x ; Lower limit (phys): 0; Upper limit (phys): 12750; + uint8_t Pwm_Front; + // 0 = Off!0 = On + //1 Byte + //[0x00] Off + //[0x01..0xFF] On; Inverse value: 0x01 + uint8_t LowTempValve; +} tStatus_eComp_For_Model; + + +// 2 Byte; Float; 1 significant digits; HighLow (Motorola) +//[0x00..0x03E8] ; y = (1/10)x %; Lower limit (phys): 0 %; Upper limit (phys): 100 %; +//Invalid values: +//[0x03E9..0xFFFE] Invalid signal (Invalid) +//[0xFFFF] Not implemented (Not implemented) + +typedef struct { + uint16_t CoolingFan; +} tStatus_External_For_Model; + + +// 0 = Off!0 = On +//1 Byte +//[0x00] Off +//[0x01..0xFF] On; Inverse value: 0x01 + +typedef struct { + uint8_t EMS_Chiller_Req; +} tStatus_EMS_For_Model; + + + +typedef struct { + // 0 = Off!0 = On + //1 Byte + //[0x00] Off + //[0x01..0xFF] On; Inverse value: 0x01 + uint8_t Ionizer; + eAromatizationIntensivity AromatizationIntensivity; +} tStatus_Ionizer_Aroma_For_Model; + + +// 1 Byte [0x00] Central [0x01..0xFF] Side; Inverse value: 0x01 + +typedef struct { + uint8_t Duct_FL; + uint8_t Duct_FR; + uint8_t Duct_RL; + uint8_t Duct_RR; +} tStatus_Duct_Select_For_Model; + +typedef struct { + uint8_t Motor_Def; + uint8_t Motor_Vent_SFL; + uint8_t Motor_Vent_CFL; + uint8_t Motor_Foot_1FL; + uint8_t Motor_Foot_2FL; + uint8_t Motor_Vent_CFR; + uint8_t Motor_Vent_SFR; + uint8_t Motor_Foot_1FR; + uint8_t Motor_Foot_2FR; + uint8_t Motor_Vent_SRL; + uint8_t Motor_Vent_CRL; + uint8_t Motor_Foot_RL; + uint8_t Motor_Vent_CRR; + uint8_t Motor_Vent_SRR; + uint8_t Motor_Foot_RR; + uint8_t Motor_Temp1_FL; + uint8_t Motor_Temp2_FL; + uint8_t Motor_Temp1_FR; + uint8_t Motor_Temp2_FR; + uint8_t Motor_Temp_RL; + uint8_t Motor_Temp_RR; + uint8_t Motor_REC; + uint8_t Motor_OSA; + uint8_t Motor_SealingValve; + uint8_t IO; + uint8_t Pwm; + uint8_t eComp; + uint8_t External; + uint8_t EMS; + uint8_t Ionizer_Aroma; + uint8_t Duct_Select; +} tStatus_Set_For_Model; + +typedef struct { + tStatus_Sensor Status_Sensor; + tStatus_Actuator Status_Actuator_DoorsActuator; + tStatus_Duct_Tgt Status_Duct_Tgt; + tStatus_Eva_Tgt Status_Eva_Tgt; + tStatus_IO Status_IO; + tStatus_Pwm Status_Pwm; + tStatus_eComp Status_eComp; + tStatus_External Status_External; + tStatus_EMS Status_EMS; + tStatus_Ionizer_Aroma Status_Ionizer_Aroma; + tStatus_Duct_Select Status_Duct_Select; + + tStatus_Actuator Status_Actuator_DoorsActuator_FB; + tStatus_Duct_Tgt Status_Duct_Tgt_FB; + tStatus_Eva_Tgt Status_Eva_Tgt_FB; + tStatus_IO Status_IO_FB; + tStatus_Pwm Status_Pwm_FB; + tStatus_eComp Status_eComp_FB; + tStatus_External Status_External_FB; + tStatus_EMS Status_EMS_FB; + tStatus_Ionizer_Aroma Status_Ionizer_Aroma_FB; + tStatus_Duct_Select Status_Duct_Select_FB; + + tStatus_Activated_Cal_Num Status_Activated_Cal_Num; + tStatus_Active_Diagnostic_Session Status_Active_Diagnostic_Session; + ecu_identification_t ecu; + +} tStatusData; + +typedef struct { + void *data; + uint8_t size; + tPermissionSession isPermissionSession; + bool isSecurity; + char *desc; +} eUds_ReadDataByIdentifier_22_com; + +typedef struct { + void *data; + uint8_t size; + tPermissionSession isPermissionSession; + bool isSecurity; + char *desc; +} eUds_WriteDataByIdentifier_2E_com; + +typedef struct { + void *data; + uint8_t size; + tPermissionSession isPermissionSession; + bool isSecurity; + char *desc; +} eUds_IoDataByIdentifier_2F_com; + +extern const eUds_ReadDataByIdentifier_22_com uds_ReadDataByIdentifier_22_com_CF[256]; +extern const eUds_ReadDataByIdentifier_22_com uds_ReadDataByIdentifier_22_com_F1[256]; + +extern const eUds_WriteDataByIdentifier_2E_com uds_WriteDataByIdentifier_2E_com_CF[256]; +extern const eUds_WriteDataByIdentifier_2E_com uds_WriteDataByIdentifier_2E_com_F1[256]; + +extern const eUds_IoDataByIdentifier_2F_com uds_IoDataByIdentifier_2F_com_CF[256]; +extern const eUds_IoDataByIdentifier_2F_com uds_IoDataByIdentifier_2F_com_F1[256]; + +extern tStatusData statusData; + +void setDefaultStatus(); + +#endif //HVAC_M7_STATUSDATA_H diff --git a/MODULES/HVAC_M7_StatusData/StatusError.c b/MODULES/HVAC_M7_StatusData/StatusError.c new file mode 100644 index 0000000..4287756 --- /dev/null +++ b/MODULES/HVAC_M7_StatusData/StatusError.c @@ -0,0 +1,153 @@ +// +// Created by cfif on 05.12.2025. +// +#include "StatusError.h" + + +// Бит Имя 0 1 +// 0 testFailed Не активно сейчас Активно сейчас +// 1 testFailedThisOperationCycle Не было в текущем цикле Было в текущем цикле +// 2 pendingDTC Не было в текущем/предыдущем цикле Было в текущем/предыдущем цикле +// 3 confirmedDTC Не подтверждено Подтверждено +// 4 testNotCompletedSinceLastClear Тест Выполнен с момента СБРОСА Тест НЕ выполнен с момента СБРОСА +// 5 testFailedSinceLastClear Не было с момента СБРОСА Было с момента СБРОСА обнаруживал неисправность (хотя бы один раз) с момента последнего сброса +// 6 testNotCompletedThisOperationCycle Тест Выполнен в текущем цикле Тест НЕ выполнен в текущем цикле +// 7 warningIndicatorRequested MIL не требуется MIL требуется + +// Массив DTC ошибок +//uint8_t dtc_state_active_error[COUNT_DTC_CODE_ERROR]; +//uint8_t dtc_state_confirmed_error[COUNT_DTC_CODE_ERROR]; +uint8_t dtc_state_error[COUNT_DTC_CODE_ERROR]; +uint8_t dtc_state_FIX_error[COUNT_DTC_CODE_ERROR]; +uint8_t dtc_state_FIX_error[COUNT_DTC_CODE_ERROR]; + +// Структура DTC кодов +const tDTC_Entry dtc_codes[COUNT_DTC_CODE_ERROR] = { + {0xA0, 0x10, 0x1C, "CCU Power supply (BATTERY) - circuit voltage out of range"}, + {0xA0, 0x11, 0x1C, "Ignition(T30d) - circuit voltage out of range"}, + {0xA0, 0x20, 0x56, "Rear HVAC configuration - invalid / incompatible configuration; Aroma CCU configuration - invalid / incompatible configuration"}, + {0xA0, 0x30, 0x15, "Incar temperature sensor front left - circuit short to battery or open"}, + {0xA0, 0x30, 0x11, "Incar temperature sensor front left - circuit short to ground"}, + {0xA0, 0x31, 0x15, "Incar temperature sensor front right - circuit short to battery or open (reserve)"}, + {0xA0, 0x31, 0x11, "Incar temperature sensor front right - circuit short to ground (reserve)"}, + {0xA0, 0x54, 0x15, "Incar temperature sensor rear left - circuit short to battery or open"}, + {0xA0, 0x54, 0x11, "Incar temperature sensor rear left - circuit short to ground"}, + {0xA0, 0x55, 0x15, "Incar temperature sensor rear right - circuit short to battery or open"}, + {0xA0, 0x55, 0x11, "Incar temperature sensor rear right - circuit short to ground"}, + {0xA0, 0x32, 0x15, "Ambient Temperature Sensor - circuit short to battery or open"}, + {0xA0, 0x32, 0x11, "Ambient Temperature Sensor - circuit short to ground"}, + {0xA0, 0x33, 0x15, "Front Evaporator Temperature Sensor - circuit short to battery or open"}, + {0xA0, 0x33, 0x11, "Front Evaporator Temperature Sensor - circuit short to ground"}, + {0xA0, 0x34, 0x15, "Rear Evaporator Temperature Sensor - circuit short to battery or open"}, + {0xA0, 0x34, 0x11, "Rear Evaporator Temperature Sensor - circuit short to ground"}, + {0xA0, 0x35, 0x15, "Duct temperature sensor_VENT_FL - circuit short to battery or open"}, + {0xA0, 0x35, 0x11, "Duct temperature sensor_VENT_FL - circuit short to ground"}, + {0xA0, 0x36, 0x15, "Duct temperature sensor_VENT_FR - circuit short to battery or open"}, + {0xA0, 0x36, 0x11, "Duct temperature sensor_VENT_FR - circuit short to ground"}, + {0xA0, 0x37, 0x15, "Duct temperature sensor_FOOT_FL - circuit short to battery or open"}, + {0xA0, 0x37, 0x11, "Duct temperature sensor_FOOT_FL - circuit short to ground"}, + {0xA0, 0x38, 0x15, "Duct temperature sensor_FOOT_FR - circuit short to battery or open"}, + {0xA0, 0x38, 0x11, "Duct temperature sensor_FOOT_FR - circuit short to ground"}, + {0xA0, 0x41, 0x15, "Duct temperature sensor_VENT_SIDE_FL - circuit short to battery or open"}, + {0xA0, 0x41, 0x11, "Duct temperature sensor_VENT_SIDE_FL - circuit short to ground"}, + {0xA0, 0x42, 0x15, "Duct temperature sensor_VENT_SIDE_FR - circuit short to battery or open"}, + {0xA0, 0x42, 0x11, "Duct temperature sensor_VENT_SIDE_FR - circuit short to ground"}, + {0xA0, 0x39, 0x15, "Duct temperature sensor_VENT_RL - circuit short to battery or open"}, + {0xA0, 0x39, 0x11, "Duct temperature sensor_VENT_RL - circuit short to ground"}, + {0xA0, 0x40, 0x15, "Duct temperature sensor_VENT_RR - circuit short to battery or open"}, + {0xA0, 0x40, 0x11, "Duct temperature sensor_VENT_RR - circuit short to ground"}, + {0xA0, 0x45, 0x15, "Duct temperature sensor_FOOT_RL - circuit short to battery or open"}, + {0xA0, 0x45, 0x11, "Duct temperature sensor_FOOT_RL - circuit short to ground"}, + {0xA0, 0x46, 0x15, "Duct temperature sensor_FOOT_RR - circuit short to battery or open"}, + {0xA0, 0x46, 0x11, "Duct temperature sensor_FOOT_RR - circuit short to ground"}, + {0xA0, 0x47, 0x13, "Ultraviolet lamp - circuit open short to battery or open"}, + {0xA0, 0x47, 0x11, "Ultraviolet lamp - circuit short to ground"}, + {0xA0, 0x48, 0x13, "Aromatization - circuit open"}, + {0xA0, 0x48, 0x11, "Aromatization - circuit short to ground"}, + {0xA0, 0x48, 0x96, "Aromatization - component malfunction"}, + {0xA0, 0x49, 0x13, "Ionizer - circuit open"}, + {0xA0, 0x49, 0x11, "Ionizer - circuit short to ground"}, + {0xA0, 0x49, 0x96, "Ionizer - component malfunction"}, + {0xA0, 0x50, 0x96, "DRS for front zone - component malfunction"}, + {0xA0, 0x51, 0x96, "DRS for rear zone - component malfunction"}, + {0xA0, 0x43, 0x15, "Air Quality Sensor - circuit open"}, + {0xA0, 0x43, 0x11, "Air Quality Sensor - circuit short to ground"}, + {0xA0, 0x43, 0x96, "Air Quality Sensor - component malfunction"}, + {0xA0, 0x44, 0x12, "A/C Pressure sensor - circuit short to battery"}, + {0xA0, 0x44, 0x14, "A/C Pressure sensor - circuit short to ground or open"}, + {0xA0, 0x44, 0x84, "A/C Pressure sensor - signal below allowable range"}, + {0xA0, 0x56, 0x92, "Failure with front blower or thermal expansion valve - Performance or Incorrect Operation"}, + {0xA0, 0x58, 0x92, "Failure with rear blower or thermal expansion valve - Performance or Incorrect Operation"}, + {0xA0, 0x70, 0x04, "Defroster Gate Actuator(LIN 0::0) Position Not Reached"}, + {0xA0, 0x71, 0x04, "Recirculation Gate Actuator (LIN0::1) Position Not Reached"}, + {0xA0, 0x93, 0x04, "Recirculation OSA Gate Actuator (LIN0::2) Position Not Reached"}, + {0xA0, 0x72, 0x04, "Temp_Up_FL Gate Actuator (LIN0::3) Position Not Reached"}, + {0xA0, 0x73, 0x04, "Vent_CFL Gate Actuator (LIN0::4) Position Not Reached"}, + {0xA0, 0x74, 0x04, "Vent_SFL Gate Actuator (LIN0::5) Position Not Reached"}, + {0xA0, 0x75, 0x04, "Temp_Dn_FL Gate Actuator (LIN0::6) Position Not Reached"}, + {0xA0, 0x76, 0x04, "Foot_FL Gate Actuator (LIN0::7) Position Not Reached"}, + {0xA0, 0x77, 0x04, "Rear_Foot_FL Gate Actuator (LIN0::8) Position Not Reached"}, + {0xA0, 0x78, 0x04, "Temp_Up_FR Gate Actuator (LIN1::0) Position Not Reached"}, + {0xA0, 0x79, 0x04, "Vent_CFR Gate Actuator (LIN1::1) Position Not Reached"}, + {0xA0, 0x80, 0x04, "Vent_SFR Gate Actuator (LIN1::2) Position Not Reached"}, + {0xA0, 0x81, 0x04, "Temp_Dn_FR Gate Actuator (LIN1::3) Position Not Reached"}, + {0xA0, 0x82, 0x04, "Foot_FR Gate Actuator (LIN1::4) Position Not Reached"}, + {0xA0, 0x83, 0x04, "Rear_Foot_FR Gate Actuator (LIN1::5) Position Not Reached"}, + {0xA0, 0x84, 0x04, "Temp_RR Gate Actuator (LIN2::0) Position Not Reached"}, + {0xA0, 0x85, 0x04, "Temp_RL Gate Actuator (LIN2::1) Position Not Reached"}, + {0xA0, 0x86, 0x04, "Vent_SRL Gate Actuator (LIN2::3) Position Not Reached"}, + {0xA0, 0x87, 0x04, "Foot_RL Gate Actuator (LIN2::4) Position Not Reached"}, + {0xA0, 0x88, 0x04, "Vent_CRL Gate Actuator (LIN2::5) Position Not Reached"}, + {0xA0, 0x89, 0x04, "Vent_CRR Gate Actuator (LIN2::6) Position Not Reached"}, + {0xA0, 0x90, 0x04, "Foot_RR Gate Actuator (LIN2::7) Position Not Reached"}, + {0xA0, 0x91, 0x04, "Vent_SRR Gate Actuator (LIN2::8) Position Not Reached"}, + {0xA0, 0x92, 0x04, "Sealing Valve Gate Actuator (LIN2::9) Position Not Reached"}, + {0xC0, 0x28, 0x88, "Body CAN – bus off"}, + {0xC0, 0x37, 0x88, "HVAC CAN – bus off"}, + {0xC1, 0x00, 0x87, "Lost Communication With ECM/PCM \"A\" (EMS/VCU) - missing message"}, + {0xC1, 0x22, 0x87, "Lost Communication With Vehicle Dynamics Control Module (ESP) - missing message"}, + {0xC1, 0x41, 0x87, "Lost Communication With Body Control Module \"A\" - missing message"}, + {0xC1, 0x6B, 0x87, "Lost Communication With A/C Compressor Control Module - missing message"}, + {0xC1, 0x99, 0x87, "Lost Communication With \"Door Control Module A\" (DMFL) - missing message"}, + {0xC2, 0x00, 0x87, "Lost Communication With \"Door Control Module B\" (DMFR) - missing message"}, + {0xC2, 0x08, 0x87, "Lost Communication With \"Seat Control Module A\" (SMFL) - missing message"}, + {0xC2, 0x09, 0x87, "Lost Communication With \"Seat Control Module B\" (SMFR) - missing message"}, + {0xC2, 0x10, 0x87, "Lost Communication With \"Seat Control Module C\" (SMRL) - missing message"}, + {0xC2, 0x11, 0x87, "Lost Communication With \"Seat Control Module D\" (SMRR) - missing message"}, + {0xE2, 0xA1, 0x87, "Lost Communication With Trunk Module (TM) or Climate Control Panels Front&Rear (CCPF/CCPR) - missing message"}, + {0xE2, 0xA2, 0x87, "Lost Communication With Central Gateway (CGW) - missing message"}, + {0xE2, 0x30, 0x87, "Defroster Gate Actuator(LIN 0::0) - Missing Message"}, + {0xE2, 0x31, 0x87, "Recirculation Gate Actuator (LIN0::1) - Missing Message"}, + {0xE2, 0x62, 0x87, "Recirculation OSA Gate Actuator (LIN0::2) - Missing Message"}, + {0xE2, 0x32, 0x87, "Temp_Up_FL Gate Actuator (LIN0::3) - Missing Message"}, + {0xE2, 0x33, 0x87, "Vent_CFL Gate Actuator (LIN0::4) - Missing Message"}, + {0xE2, 0x34, 0x87, "Foot_FR Gate Actuator (LIN1::5) - Missing Message"}, + {0xE2, 0x35, 0x87, "Temp_Dn_FL Gate Actuator (LIN0::6) - Missing Message"}, + {0xE2, 0x36, 0x87, "Foot_FL Gate Actuator (LIN0::7) - Missing Message"}, + {0xE2, 0x37, 0x87, "Rear_Foot_FL Gate Actuator (LIN0::8) - Missing Message"}, + {0xE2, 0x38, 0x87, "Temp_Up_FR Gate Actuator (LIN1::1) - Missing Message"}, + {0xE2, 0x39, 0x87, "Vent_CFR Gate Actuator (LIN1::2) - Missing Message"}, + {0xE2, 0x40, 0x87, "Vent_SFR Gate Actuator (LIN1::3) - Missing Message"}, + {0xE2, 0x41, 0x87, "Temp_Dn_FR Gate Actuator (LIN1::4) - Missing Message"}, + {0xE2, 0x42, 0x87, "Foot_FR Gate Actuator (LIN1::5) - Missing Message"}, + {0xE2, 0x43, 0x87, "Rear_Foot_FR Gate Actuator (LIN1::6) - Missing Message"}, + {0xE2, 0x44, 0x87, "Temp_RR Gate Actuator (LIN2::1) - Missing Message"}, + {0xE2, 0x45, 0x87, "Temp_RL Gate Actuator (LIN2::2) - Missing Message"}, + {0xE2, 0x46, 0x87, "Vent_SRL Gate Actuator (LIN2::3) - Missing Message"}, + {0xE2, 0x47, 0x87, "Temp_RL Gate Actuator (LIN2::4) - Missing Message"}, + {0xE2, 0x48, 0x87, "Vent_CRL Gate Actuator (LIN2::5) - Missing Message"}, + {0xE2, 0x49, 0x87, "Vent_CRR Gate Actuator (LIN2::6) - Missing Message"}, + {0xE2, 0x50, 0x87, "Foot_RR Gate Actuator (LIN2::7) - Missing Message"}, + {0xE2, 0x51, 0x87, "Vent_SRR Gate Actuator (LIN2::8) - Missing Message"}, + {0xE2, 0x52, 0x87, "Sealing Valve Gate Actuator (LIN2::9) - Missing Message"}, + {0xE2, 0x53, 0x87, "Air quality sensor (LIN3) - Missing Message"}, + {0xE2, 0x54, 0x87, "Ionizer (LIN3) - Missing Message"}, + {0xE2, 0x55, 0x87, "Aromatization (LIN3) - Missing Message"}, + {0xE2, 0x56, 0x87, "Front TXV (LIN3) - Missing Message"}, + {0xE2, 0x57, 0x87, "Rear TXV (LIN3) - Missing Message"}, + {0xE2, 0x58, 0x87, "High voltage battery chiller TXV (LIN3) - Missing Message"}, + {0xE2, 0x59, 0x87, "Heat pump chiller TXV (LIN3) - Missing Message"}, + {0xE2, 0x60, 0x87, "DRS for front zone (LIN4) - Missing Message"}, + {0xE2, 0x61, 0x87, "DRS for rear zone (LIN4) - Missing Message"}, + {0xF0, 0x02, 0x56, "Vehicle Identification Number - invalid / incompatible configuration"} +}; \ No newline at end of file diff --git a/MODULES/HVAC_M7_StatusData/StatusError.h b/MODULES/HVAC_M7_StatusData/StatusError.h new file mode 100644 index 0000000..165a468 --- /dev/null +++ b/MODULES/HVAC_M7_StatusData/StatusError.h @@ -0,0 +1,176 @@ +// +// Created by cfif on 05.12.2025. +// + +#ifndef HVAC_M7_STATUSERROR_H +#define HVAC_M7_STATUSERROR_H +#include "stdint.h" + + +typedef struct { + uint8_t DTCHighByte; // Старший байт DTC кода (первые 2 символа) + uint8_t DTCMiddleByte; // Средний байт DTC кода (следующие 2 символа) + uint8_t DTCLowByte; // Младший байт DTC кода (последние 2 символа) + char *description; // Описание ошибки +} tDTC_Entry; + +typedef struct { + uint8_t testFailed : 1; // DTC является активным на момент запроса (Временное) + uint8_t testFailedThisOperationCycle; // DTC был активным в текущем цикле работы (Временное) + uint8_t pendingDTC : 1; // DTC был активным в текущем или предыдущем цикле (Временное) + uint8_t confirmedDTC : 1; // DTC подтвержден (Постоянное) + uint8_t testNotCompletedSinceLastClear : 1; // Тест DTC не был выполнен с момента последней очистки (Временное) + uint8_t testFailedSinceLastClear : 1; // Тест DTC обнаруживал неисправность хотя бы раз с момента последней очистки (Временное) + uint8_t testNotCompletedThisOperationCycle : 1; // Тест DTC не был выполнен в текущем цикле работы (Временное) + uint8_t warningIndicatorRequested : 1; // Сервер запрашивает включение индикатора предупреждения (Временное) +} tUdsDTCStatusMask; + +typedef enum { + UDS_dtc_mask_testFailed = 0x1, // DTC является активным на момент запроса (Временное) + UDS_dtc_mask_testFailedThisOperationCycle = 0x2, // DTC был активным в текущем цикле работы (Временное) + UDS_dtc_mask_pendingDTC = 0x4, // DTC был активным в текущем или предыдущем цикле (Временное) + UDS_dtc_mask_confirmedDTC = 0x8, // DTC подтвержден (Постоянное) + UDS_dtc_mask_testNotCompletedSinceLastClear = 0x10, // Тест DTC не был выполнен с момента последней очистки (Временное) + UDS_dtc_mask_testFailedSinceLastClear = 0x20, // Тест DTC обнаруживал неисправность хотя бы раз с момента последней очистки (Постоянное) + UDS_dtc_mask_testNotCompletedThisOperationCycle = 0x40, // Тест DTC не был выполнен в текущем цикле работы (Временное) + UDS_dtc_mask_warningIndicatorRequested = 0x80 // Сервер запрашивает включение индикатора предупреждения (Зависит) +} eUdsDTCMask; + +#define COUNT_DTC_CODE_ERROR 127 + +extern const tDTC_Entry dtc_codes[COUNT_DTC_CODE_ERROR]; +extern uint8_t dtc_state_error[COUNT_DTC_CODE_ERROR]; +extern uint8_t dtc_state_FIX_error[COUNT_DTC_CODE_ERROR]; + +//# ErrorCode HexCode FTB SAE J2012 Symptom Description DTC description HW Comment Pre-Condtion Maturation Failure Threshold Maturation Time De-Maturation Failure Threshold De-Maturation Time Degrade mode / Fail-safe action Malfunction Indicator Remark Comment SW progress +//1 B20101C A0101C 0x1C Voltage Out of Range CCU Power supply (BATTERY) - circuit voltage out of range Possible T30d_state = "1" and T15_state = "1" 6.0v > VIN or VIN > 18.0V t > 3sec 6.0v < VIN and VIN < 18.0V t > 1 sec Only DTC Set * If voltage of battery is under 7.0v/7.5v or over 17.5v/18.0v, 1) Actuator Stop 2) Blower Stop 3) Seat Module Stop Request None Condition * If voltage of battery is under 7.0v/7.5v or over 17.5v/18.0v, --> * If voltage of battery is under 7.5v/8.0v or over 17.0v/17.5v OK : DTC / Fail-Safe +//2 B20111C A0111C 0x1C Voltage Out of Range Ignition(T30d) - circuit voltage out of range Possible T30d_state = "1" and T15_state = "1" 6.0v > VIN or VIN > 18.0V t > 3sec 6.0v < VIN and VIN < 18.0V t > 1 sec Only DTC Set None OK : DTC +//3 B202056 A02056 0x56 Invalid / incompatible configuration Rear HVAC configuration - invalid / incompatible configuration Aroma CCU configuration - invalid / incompatible configuration Unrelated to HW T30d_state = "1" and T15_state = "1" Configuration invalid / incomplete: DID 0xCF00 invalid/default value set Immediately Configuration complete: DID 0xCF00 != default AND value is valid Immediately Only DTC set Assume Rear HVAC fitted -> Assume aromatization system is not present, standart variant algorithm None suppress as SW, Rear is always present (temporary solution) If aromatization system is not present A04813, A04811, A04896, E25587 DTCs shall be disabled OK : Negative response of diagnostic service / Suppress +//4 B203015 A03015 0x15 Circuit Short To Battery or Open Incar temperature sensor front left - circuit short to battery or open Possible T30d_state = "1" and T15_state = "1" VIN > 4.9V t > 3sec VIN < 4.9V t > 1 sec Incar : 20.0 ℃ CCU_Body_Err.CCU_IncarTempErrF_Stat = 0x1 (Failure) +//5 B203011 A03011 0x11 Circuit Short To Ground Incar temperature sensor front left - circuit short to ground Possible T30d_state = "1" and T15_state = "1" VIN < 0.15V t > 3sec VIN > 0.15V t > 1 sec +//6 B203115 A03115 0x15 Circuit Short To Battery or Open Incar temperature sensor front right - circuit short to battery or open (reserve) Possible T30d_state = "1" and T15_state = "1" VIN > 4.9V t > 3sec VIN < 4.9V t > 1 sec Activation by VIN suppress as SW +//7 B203111 A03111 0x11 Circuit Short To Ground Incar temperature sensor front right - circuit short to ground (reserve) Possible T30d_state = "1" and T15_state = "1" VIN < 0.15V t > 3sec VIN > 0.15V t > 1 sec Activation by VIN +//8 B205415 A05415 0x15 Circuit Short To Battery or Open Incar temperature sensor rear left - circuit short to battery or open Possible T30d_state = "1" and T15_state = "1" VIN > 4.9V t > 3sec VIN < 4.9V t > 1 sec Incar : 20.0 ℃ CCU_Body_Err.CCU_IncarTempErrR_Stat = 0x1 (Failure) Activation by VIN OK : DTC / Fail-Safe / CAN signal / VIN control +//9 B205411 A05411 0x11 Circuit Short To Ground Incar temperature sensor rear left - circuit short to ground Possible T30d_state = "1" and T15_state = "1" VIN < 0.15V t > 3sec VIN > 0.15V t > 1 sec Activation by VIN +//10 B205515 A05515 0x15 Circuit Short To Battery or Open Incar temperature sensor rear right - circuit short to battery or open Possible T30d_state = "1" and T15_state = "1" VIN > 4.9V t > 3sec VIN < 4.9V t > 1 sec Activation by VIN +//11 B205511 A05511 0x11 Circuit Short To Ground Incar temperature sensor rear right - circuit short to ground Possible T30d_state = "1" and T15_state = "1" VIN < 0.15V t > 3sec VIN > 0.15V t > 1 sec Activation by VIN +//12 B203215 A03215 0x15 Circuit Short To Battery or Open Ambient Temperature Sensor - circuit short to battery or open Possible T30d_state = "1" and T15_state = "1" VIN > 4.9V t > 3sec VIN < 4.9V t > 1 sec Ambient : 10.0 ℃ CCU_Body_Err.CCU_AmbienTemptSenErr_Stat = 0x1 (Failure) OK : DTC / Fail-Safe / CAN signal +//13 B203211 A03211 0x11 Circuit Short To Ground Ambient Temperature Sensor - circuit short to ground Possible T30d_state = "1" and T15_state = "1" VIN < 0.1V t > 3sec VIN > 0.1V t > 1 sec +//14 B203315 A03315 0x15 Circuit Short To Battery or Open Front Evaporator Temperature Sensor - circuit short to battery or open Possible T30d_state = "1" and T15_state = "1" VIN > 4.9V t > 3sec VIN < 4.9V t > 1 sec Front Eva : -10.0 ℃ Ecomp. Off CCU_Body_Err.CCU_EvaTempSenErrF_Stat = 0x1 (Failure) OK : DTC / Fail-Safe / CAN signal +//15 B203311 A03311 0x11 Circuit Short To Ground Front Evaporator Temperature Sensor - circuit short to ground Possible T30d_state = "1" and T15_state = "1" VIN < 0.1V t > 3sec VIN > 0.1V t > 1 sec +//16 B203415 A03415 0x15 Circuit Short To Battery or Open Rear Evaporator Temperature Sensor - circuit short to battery or open Possible T30d_state = "1" and T15_state = "1" VIN > 4.9V t > 3sec VIN < 4.9V t > 1 sec Rear Eva : -10.0 ℃ Ecomp. Off CCU_Body_Err.CCU_EvaTempSenErrR_Stat = 0x1 (Failure) Activation by VIN Don't need VIN control because Rear is always present. (temporary solution) Rear HVAC always present - serial solution for Phase 1 OK : DTC / Fail-Safe / CAN signal +//17 B203411 A03411 0x11 Circuit Short To Ground Rear Evaporator Temperature Sensor - circuit short to ground Possible T30d_state = "1" and T15_state = "1" VIN < 0.1V t > 3sec VIN > 0.1V t > 1 sec Activation by VIN +//18 B203515 A03515 0x15 Circuit Short To Battery or Open Duct temperature sensor_VENT_FL - circuit short to battery or open Possible T30d_state = "1" and T15_state = "1" VIN > 4.9V t > 3sec VIN < 4.9V t > 1 sec Duct : 23.0 ℃ Temp. Door Actuators move with fixed position by Set-Temp. CCU_Body_Err.CCU_DuctTempSenErrF_Stat = 0x1 (Failure) OK : DTC / Fail-Safe / CAN signal +//19 B203511 A03511 0x11 Circuit Short To Ground Duct temperature sensor_VENT_FL - circuit short to ground Possible T30d_state = "1" and T15_state = "1" VIN < 0.15V t > 3sec VIN > 0.15V t > 1 sec +//20 B203615 A03615 0x15 Circuit Short To Battery or Open Duct temperature sensor_VENT_FR - circuit short to battery or open Possible T30d_state = "1" and T15_state = "1" VIN > 4.9V t > 3sec VIN < 4.9V t > 1 sec +//21 B203611 A03611 0x11 Circuit Short To Ground Duct temperature sensor_VENT_FR - circuit short to ground Possible T30d_state = "1" and T15_state = "1" VIN < 0.15V t > 3sec VIN > 0.15V t > 1 sec +//22 B203715 A03715 0x15 Circuit Short To Battery or Open Duct temperature sensor_FOOT_FL - circuit short to battery or open Possible T30d_state = "1" and T15_state = "1" VIN > 4.9V t > 3sec VIN < 4.9V t > 1 sec +//23 B203711 A03711 0x11 Circuit Short To Ground Duct temperature sensor_FOOT_FL - circuit short to ground Possible T30d_state = "1" and T15_state = "1" VIN < 0.15V t > 3sec VIN > 0.15V t > 1 sec +//24 B203815 A03815 0x15 Circuit Short To Battery or Open Duct temperature sensor_FOOT_FR - circuit short to battery or open Possible T30d_state = "1" and T15_state = "1" VIN > 4.9V t > 3sec VIN < 4.9V t > 1 sec +//25 B203811 A03811 0x11 Circuit Short To Ground Duct temperature sensor_FOOT_FR - circuit short to ground Possible T30d_state = "1" and T15_state = "1" VIN < 0.15V t > 3sec VIN > 0.15V t > 1 sec +//26 B204115 A04115 0x15 Circuit Short To Battery or Open Duct temperature sensor_VENT_SIDE_FL - circuit short to battery or open Possible T30d_state = "1" and T15_state = "1" VIN > 4.9V t > 3sec VIN < 4.9V t > 1 sec +//27 B204111 A04111 0x11 Circuit Short To Ground Duct temperature sensor_VENT_SIDE_FL - circuit short to ground Possible T30d_state = "1" and T15_state = "1" VIN < 0.15V t > 3sec VIN > 0.15V t > 1 sec +//28 B204215 A04215 0x15 Circuit Short To Battery or Open Duct temperature sensor_VENT_SIDE_FR - circuit short to battery or open Possible T30d_state = "1" and T15_state = "1" VIN > 4.9V t > 3sec VIN < 4.9V t > 1 sec +//29 B204211 A04211 0x11 Circuit Short To Ground Duct temperature sensor_VENT_SIDE_FR - circuit short to ground Possible T30d_state = "1" and T15_state = "1" VIN < 0.15V t > 3sec VIN > 0.15V t > 1 sec +//30 B203915 A03915 0x15 Circuit Short To Battery or Open Duct temperature sensor_VENT_RL - circuit short to battery or open Possible T30d_state = "1" and T15_state = "1" VIN > 4.9V t > 3sec VIN < 4.9V t > 1 sec CCU_Body_Err.CCU_DuctTempSenErrR_Stat = 0x1 (Failure) Activation by VIN Don't need VIN control because Rear is always present. (temporary solution) Rear HVAC always present - serial solution for Phase 1 OK : DTC / Fail-Safe / CAN signal +//31 B203911 A03911 0x11 Circuit Short To Ground Duct temperature sensor_VENT_RL - circuit short to ground Possible T30d_state = "1" and T15_state = "1" VIN < 0.15V t > 3sec VIN > 0.15V t > 1 sec Activation by VIN +//32 B204015 A04015 0x15 Circuit Short To Battery or Open Duct temperature sensor_VENT_RR - circuit short to battery or open Possible T30d_state = "1" and T15_state = "1" VIN > 4.9V t > 3sec VIN < 4.9V t > 1 sec Activation by VIN +//33 B204011 A04011 0x11 Circuit Short To Ground Duct temperature sensor_VENT_RR - circuit short to ground Possible T30d_state = "1" and T15_state = "1" VIN < 0.15V t > 3sec VIN > 0.15V t > 1 sec Activation by VIN +//34 B204515 A04515 0x15 Circuit Short To Battery or Open Duct temperature sensor_FOOT_RL - circuit short to battery or open Possible T30d_state = "1" and T15_state = "1" VIN > 4.9V t > 3sec VIN < 4.9V t > 1 sec Activation by VIN +//35 B204511 A04511 0x11 Circuit Short To Ground Duct temperature sensor_FOOT_RL - circuit short to ground Possible T30d_state = "1" and T15_state = "1" VIN < 0.15V t > 3sec VIN > 0.15V t > 1 sec Activation by VIN +//36 B204615 A04615 0x15 Circuit Short To Battery or Open Duct temperature sensor_FOOT_RR - circuit short to battery or open Possible T30d_state = "1" and T15_state = "1" VIN > 4.9V t > 3sec VIN < 4.9V t > 1 sec Activation by VIN +//37 B204611 A04611 0x11 Circuit Short To Ground Duct temperature sensor_FOOT_RR - circuit short to ground Possible T30d_state = "1" and T15_state = "1" VIN < 0.15V t > 3sec VIN > 0.15V t > 1 sec Activation by VIN +//38 B204713 A04713 0x13 Circuit Open Ultraviolet lamp - circuit open short to battery or open Impossible. Need to change "Circuit short to battery" or "open" T30d_state = "1" and T15_state = "1" tbd tbd tbd tbd tbd CCU_Body_Err.CCU_UltravioletErr_Stat = 0x1 (Supply chain break) We need to hide/mask this DTC (temporary solution) --> suppress as SW OK : Suppress +//39 B204711 A04711 0x11 Circuit Short To Ground Ultraviolet lamp - circuit short to ground Possible T30d_state = "1" and T15_state = "1" tbd tbd tbd tbd tbd CCU_Body_Err.CCU_UltravioletErr_Stat = 0x2 (Supply chain short circuit) +//40 B204813 A04813 0x13 Circuit Open Aromatization - circuit open Unrelated to HW T30d_state = "1" and T15_state = "1" CCU LIN4: Aroma_Stat. AromaErr_Func_Stat = 0x1 (Supply chain break) Immediately CCU LIN4: Aroma_Stat. AromaErr_Func_Stat = 0x0 (No error) Immediately Aromatization off CCU_Body_Err.CCU_AromaErr_Stat = 0x1 (Supply chain break) We need to hide/mask this DTC (temporary solution) --> suppress as SW Related to 0xCF00 DID OK : Suppress +//41 B204811 A04811 0x11 Circuit Short To Ground Aromatization - circuit short to ground Unrelated to HW T30d_state = "1" and T15_state = "1" CCU LIN4: Aroma_Stat. AromaErr_Func_Stat = 0x2 (Supply chain short circuit) Immediately CCU LIN4: Aroma_Stat. AromaErr_Func_Stat = 0x0 (No error) Immediately CCU_Body_Err.CCU_AromaErr_Stat = 0x2 (Supply chain short circuit) +//42 B204896 A04896 0x96 Component Internal Failure Aromatization - component malfunction Unrelated to HW T30d_state = "1" and T15_state = "1" CCU LIN4: Aroma_Stat. AromaErr_Func_Stat = 0x3 (Aroma malfunction) Immediately CCU LIN4: Aroma_Stat. AromaErr_Func_Stat = 0x0 (No error) Immediately CCU_Body_Err.CCU_AromaErr_Stat = 0x4 (Component malfunction) +//43 B204913 A04913 0x13 Circuit Open Ionizer - circuit open Unrelated to HW T30d_state = "1" and T15_state = "1" CCU LIN4: Ionizer_Stat. IonizerErr_Func_Stat = 0x1 (Supply chain break) Immediately CCU LIN4: Ionizer_Stat. IonizerErr_Func_Stat = 0x0 (No error) Immediately Ionizer off CCU_Body_Err.CCU_IonizationErr_Stat = 0x1 (Supply chain break) OK : DTC / CAN signal NOK : Fail-Safe +//44 B204911 A04911 0x11 Circuit Short To Ground Ionizer - circuit short to ground Unrelated to HW T30d_state = "1" and T15_state = "1" CCU LIN4: Ionizer_Stat. IonizerErr_Func_Stat = 0x2 (Supply chain short circuit) Immediately CCU LIN4: Ionizer_Stat. IonizerErr_Func_Stat = 0x0 (No error) Immediately CCU_Body_Err.CCU_IonizationErr_Stat = 0x2 (Supply chain short circuit) +//45 B204996 A04996 0x96 Component Internal Failure Ionizer - component malfunction Unrelated to HW T30d_state = "1" and T15_state = "1" CCU LIN4: Ionizer_Stat. IonizerErr_Func_Stat = 0x3 (Component malfunctiont) Immediately CCU LIN4: Ionizer_Stat. IonizerErr_Func_Stat = 0x0 (No error) Immediately CCU_Body_Err.CCU_IonizationErr_Stat = 0x4 (Component malfunction) +//46 B205096 A05096 0x96 Component Internal Failure DRS for front zone - component malfunction Unrelated to HW T30d_state = "1" and T15_state = "1" CCU LIN5: - DRS_DL_Stat. DRS_DLErr_Func_Stat = 0x1 (Error) or - DRS_DR_Stat. DRS_DRErr_Func_Stat = 0x1 (Error) or - DRS_FPL_Stat. DRS_FPLErr_Func_Stat = 0x1 (Error) or - DRS_FPR_Stat. DRS_FPRErr_Func_Stat = 0x1 (Error) Immediately CCU LIN5: - DRS_DL_Stat. DRS_DLErr_Func_Stat = 0x0 (No error) and - DRS_DR_Stat. DRS_DRErr_Func_Stat = 0x0 (No error) and - DRS_FPL_Stat. DRS_FPLErr_Func_Stat = 0x0 (No error) and - DRS_FPR_Stat. DRS_FPRErr_Func_Stat = 0x0 (No error) Immediately If signal is error, CCU change 100%(Step3) CCU_Body_Err.CCU_DRSerrF_Stat = 0x1 (Failure) Added to Fail-Safe : if signal is error, CCU change 100%(Step3) OK : DTC / Fail-Safe / CAN signal +//47 B205196 A05196 0x96 Component Internal Failure DRS for rear zone - component malfunction Unrelated to HW T30d_state = "1" and T15_state = "1" CCU LIN5: - DRS_FCL_Stat. DRS_FCLErr_Func_Stat = 0x1 (Error) or - DRS_FCR_Stat. DRS_FCRErr_Func_Stat = 0x1 (Error) or - DRS_RBL_Stat. DRS_RBLErr_Func_Stat = 0x1 (Error) or - DRS_RBR_Stat. DRS_RBRErr_Func_Stat = 0x1 (Error) Immediately CCU LIN5: - DRS_FCL_Stat. DRS_FCLErr_Func_Stat = 0x0 (No error) and - DRS_FCR_Stat. DRS_FCRErr_Func_Stat = 0x0 (No error) and - DRS_RBL_Stat. DRS_RBLErr_Func_Stat = 0x0 (No error) and - DRS_RBR_Stat. DRS_RBRErr_Func_Stat = 0x0 (No error) Immediately If signal is error, CCU change 100%(Step3) CCU_Body_Err.CCU_DRSerrR_Stat = 0x1 (Failure) Added to Fail-Safe : if signal is error, CCU change 100%(Step3) Activation by VIN (temporary solution) 01/30 Estra : need Activation by VIN OK : DTC / Fail-Safe /CAN signal / VIN control +//48 B204315 A04315 0x13 Circuit Open Air Quality Sensor - circuit open Unrelated to HW T30d_state = "1" and T15_state = "1" CCU LIN4: AirQS_Stat. SensorErr_Func_Stat = 0x1 (Supply chain break) Immediately CCU LIN4: AirQS_Stat. SensorErr_Func_Stat = 0x0 (No error) Immediately Air Quality Sensor off CCU_Body_Err.CCU_AirQualSenErr_Stat = 0x1 (Supply chain break) OK : DTC / CAN signal NOK : Fail-Safe +//49 B204311 A04311 0x11 Circuit Short To Ground Air Quality Sensor - circuit short to ground Unrelated to HW T30d_state = "1" and T15_state = "1" CCU LIN4: AirQS_Stat. SensorErr_Func_Stat = 0x2 (Supply chain short circuit) Immediately CCU LIN4: AirQS_Stat. SensorErr_Func_Stat = 0x0 (No error) Immediately CCU_Body_Err.CCU_AirQualSenErr_Stat = 0x2 (Supply chain short circuit) +//50 B204396 A04396 0x96 Component Internal Failure Air Quality Sensor - component malfunction Unrelated to HW T30d_state = "1" and T15_state = "1" - CCU LIN4: AirQS_Stat. SensorErr_Func_Stat = 0x3 (Component malfunctiont) or - DID 0xCF01: AQS, Pollution Level = 0xFF (Error) Immediately CCU LIN4: AirQS_Stat. SensorErr_Func_Stat = 0x0 (No error) Immediately CCU_Body_Err.CCU_AirQualSenErr_Stat = 0x4 (Component malfunction) +//51 B204412 A04412 0x12 Circuit Short To Battery A/C Pressure sensor - circuit short to battery Possible T30d_state = "1" and T15_state = "1" VIN > 4.9V t > 3sec VIN < 4.9V t > 1 sec A/C Pressure : 50.0 ATM 32.0 ATM Ecomp. Off CCU_Body_Err.CCU_PressSenErr_Stat = 0x1 (Failure) A/C Pressure : 50.0 ATM 32.0 ATM because of max range of Pressure sensor OK : DTC / Fail-Safe /CAN signal +//52 B204414 A04414 0x14 Circuit Short To Ground or Open A/C Pressure sensor - circuit short to ground or open Possible T30d_state = "1" and T15_state = "1" VIN < 0.15V t > 3sec VIN > 0.15V t > 1 sec +//53 B204484 A04484 0x84 Signal Below Allowable Range A/C Pressure sensor - signal below allowable range Unrelated to HW Coolant temperature < 45°C ECompressor state = Off Cooling fan request = Off Entry Condition : - Coolant temperature < 45C - Ecomp. = OFF - A/C refrigerant pressure < threshold (see table) 'Entry Action : - CCU remembers Ambient temp (AnbStart) - Vehicle Speed >= 50 km/h - If AmbStart - AmbRaw < 10C - CCU sends Failure Immediately Exit Condition : - Coolant temperature > 45C - Ecomp. = ON - A/C refrigerant pressure > threshold (see table) Immediately Ecomp. Off OK : NOK : DTC / Fail-Safe / CAN signal +//54 B205692 A05692 0x92 Performance or Incorrect Operation Failure with front blower or thermal expansion valve - Performance or Incorrect Operation Unrelated to HW Diagnostic monitor performed once per engine start (i.e. BCM_VEH_STATE::VehicleModeState = 4 or 5) Front A/C system state = On ECompressor state = On Evaporator temperature > threshold (see table) t > 120 sec Evaporator temperature < threshold (see table) Immediately Ecomp. Off CCU_Body_Err.CCU_HVACfanOrTXVerrF_Stat = 0x1 (Failure) NOK : DTC / Fail-Safe / CAN signal +//55 B205892 A05892 0x92 Performance or Incorrect Operation Failure with rear blower or thermal expansion valve - Performance or Incorrect Operation Unrelated to HW Diagnostic monitor performed once per engine start (i.e. BCM_VEH_STATE::VehicleModeState = 4 or 5) Rear A/C system state = On ECompressor state = On Evaporator temperature > threshold (see table) t > 120 sec Evaporator temperature < threshold (see table) Immediately Ecomp. Off CCU_Body_Err.CCU_HVACfanOrTXVerrR_Stat = 0x1 (Failure) +//56 B207004 A07004 0x04 System Internal Failure Defroster Gate Actuator(LIN 0::0) Position Not Reached Unrelated to HW Target position is not reached when target position is updated t > 10sec Target position is reached when re-Start Immediately Actuator Stop CCU_Body_Err.CCU_ActuatorErrF_Stat = 0x1 (Failure) LIN Ch0 Num0_DEF Status Homing Range Fail or Moving Range Fail OK : DTC / Fail-Safe / CAN signal +//57 B207104 A07104 0x04 System Internal Failure Recirculation Gate Actuator (LIN0::1) Position Not Reached Actuator Stop LIN Ch0 Num1_REC Status +//58 B209304 A09304 0x04 System Internal Failure Recirculation OSA Gate Actuator (LIN0::2) Position Not Reached Actuator Stop LIN Ch0 Num2_OSA Status +//59 B207204 A07204 0x04 System Internal Failure Temp_Up_FL Gate Actuator (LIN0::3) Position Not Reached Actuator Stop LIN Ch0 Num3_Temp_Up_FL Status +//60 B207304 A07304 0x04 System Internal Failure Vent_CFL Gate Actuator (LIN0::4) Position Not Reached Actuator Stop LIN Ch0 Num4_Vent_CFL Status +//61 B207404 A07404 0x04 System Internal Failure Vent_SFL Gate Actuator (LIN0::5) Position Not Reached Actuator Stop LIN Ch0 Num5_Vent_SFL Status +//62 B207504 A07504 0x04 System Internal Failure Temp_Dn_FL Gate Actuator (LIN0::6) Position Not Reached Actuator Stop LIN Ch0 Num6_Vemp_Dn_FL Status +//63 B207604 A07604 0x04 System Internal Failure Foot_FL Gate Actuator (LIN0::7) Position Not Reached Actuator Stop LIN Ch0 Num7_Foot_FL Status +//64 B207704 A07704 0x04 System Internal Failure Rear_Foot_FL Gate Actuator (LIN0::8) Position Not Reached Actuator Stop LIN Ch0 Num8_Rear_Foot_FL Status +//65 B207804 A07804 0x04 System Internal Failure Temp_Up_FR Gate Actuator (LIN1::0) Position Not Reached Actuator Stop LIN Ch1 Num0_Temp_Up_FR Status Homing Range Fail or Moving Range Fail OK : DTC / Fail-Safe / CAN signal +//66 B207904 A07904 0x04 System Internal Failure Vent_CFR Gate Actuator (LIN1::1) Position Not Reached Actuator Stop LIN Ch1 Num1_Vent_CFR Status +//67 B208004 A08004 0x04 System Internal Failure Vent_SFR Gate Actuator (LIN1::2) Position Not Reached Actuator Stop LIN Ch1 Num2_Vent_SFR Status +//68 B208104 A08104 0x04 System Internal Failure Temp_Dn_FR Gate Actuator (LIN1::3) Position Not Reached Actuator Stop LIN Ch1 Num3_Temp_Dn_FR Status +//69 B208204 A08204 0x04 System Internal Failure Foot_FR Gate Actuator (LIN1::4) Position Not Reached Actuator Stop LIN Ch1 Num4_Foot_FR Status +//70 B208304 A08304 0x04 System Internal Failure Rear_Foot_FR Gate Actuator (LIN1::5) Position Not Reached Actuator Stop LIN Ch1 Num5_Rear_Foot_FR Status +//71 B208404 A08404 0x04 System Internal Failure Temp_RR Gate Actuator (LIN2::0) Position Not Reached Actuator Stop CCU_Body_Err.CCU_ActuatorErrR_Stat = 0x1 (Failure) LIN Ch2 Num0_Temp_RR Status Homing Range Fail or Moving Range Fail OK : DTC / Fail-Safe / CAN signal +//72 B208504 A08504 0x04 System Internal Failure Temp_RL Gate Actuator (LIN2::1) Position Not Reached Actuator Stop LIN Ch2 Num1_Temp_RL Status +//73 B208604 A08604 0x04 System Internal Failure Vent_SRL Gate Actuator (LIN2::3) Position Not Reached Actuator Stop LIN Ch2 Num2_Vent_SRL Status +//74 B208704 A08704 0x04 System Internal Failure Foot_RL Gate Actuator (LIN2::4) Position Not Reached Actuator Stop LIN Ch2 Num3_Temp_RL Status +//75 B208804 A08804 0x04 System Internal Failure Vent_CRL Gate Actuator (LIN2::5) Position Not Reached Actuator Stop LIN Ch2 Num4_Vent_CRL Status +//76 B208904 A08904 0x04 System Internal Failure Vent_CRR Gate Actuator (LIN2::6) Position Not Reached Actuator Stop LIN Ch2 Num5_Vent_CRR Status +//77 B209004 A09004 0x04 System Internal Failure Foot_RR Gate Actuator (LIN2::7) Position Not Reached Actuator Stop LIN Ch2 Num6_Foot_RR Status +//78 B209104 A09104 0x04 System Internal Failure Vent_SRR Gate Actuator (LIN2::8) Position Not Reached Actuator Stop LIN Ch2 Num7_Vent_SRR Status +//79 B209204 A09204 0x04 System Internal Failure Sealing Valve Gate Actuator (LIN2::9) Position Not Reached Actuator Stop CCU_Body_Err.CCU_SealingValveErr_Stat = 0x1 (Failure) LIN Ch3 Num0_Sealing Valve Status Activation by VIN OK : DTC / Fail-Safe / CAN signal / VIN control +//80 U002888 C02888 0x88 Bus Off Body CAN – bus off Unrelated to HW Bus Off t > 3sec No Bus Off Immediately Init Value CCU_Failure_Stat.CCU_CommFailure_Stat = 0x1 (Failure) Fail-Safe: Init Value --> Previous value OK : DTC / CAN signal NOK : Fail-Safe +//81 U003788 C03788 0x88 Bus Off HVAC CAN – bus off Bus Off t > 3sec No Bus Off t > 1 sec Init Value CCU_Failure_Stat.CCU_CommFailure_Stat = 0x1 (Failure) Fail-Safe: Init Value --> Previous value OK : DTC / CAN signal NOK : Fail-Safe +//82 U010087 C10087 0x87 Missing Message Lost Communication With ECM/PCM "A" (EMS/VCU) - missing message Missing Message t > 3sec No Missing Message t > 1 sec Init Value CCU_Failure_Stat.CCU_CommFailure_Stat = 0x1 (Failure) Fail-Safe: Init Value --> Previous value OK : DTC / CAN signal NOK : Fail-Safe +//83 U012287 C12287 0x87 Missing Message Lost Communication With Vehicle Dynamics Control Module (ESP) - missing message Missing Message t > 3sec No Missing Message t > 1 sec Init Value CCU_Failure_Stat.CCU_CommFailure_Stat = 0x1 (Failure) Fail-Safe: Init Value --> Previous value OK : DTC / CAN signal NOK : Fail-Safe +//84 U014187 C14187 0x87 Missing Message Lost Communication With Body Control Module "A" - missing message Missing Message t > 3sec No Missing Message t > 1 sec Init Value CCU_Failure_Stat.CCU_CommFailure_Stat = 0x1 (Failure) Fail-Safe: Init Value --> Previous value OK : DTC / CAN signal NOK : Fail-Safe +//85 U016B87 C16B87 0x87 Missing Message Lost Communication With A/C Compressor Control Module - missing message Missing Message t > 3sec No Missing Message t > 1 sec Init Value CCU_Failure_Stat.CCU_CommFailure_Stat = 0x1 (Failure) Fail-Safe: Init Value --> Previous value OK : DTC / CAN signal NOK : Fail-Safe +//86 U019987 C19987 0x87 Missing Message Lost Communication With "Door Control Module A" (DMFL) - missing message Missing Message t > 3sec No Missing Message t > 1 sec Init Value CCU_Failure_Stat.CCU_CommFailure_Stat = 0x1 (Failure) Fail-Safe: Init Value --> Previous value OK : DTC / CAN signal NOK : Fail-Safe +//87 U020087 C20087 0x87 Missing Message Lost Communication With "Door Control Module B" (DMFR) - missing message Missing Message t > 3sec No Missing Message t > 1 sec Init Value CCU_Failure_Stat.CCU_CommFailure_Stat = 0x1 (Failure) Fail-Safe: Init Value --> Previous value OK : DTC / CAN signal NOK : Fail-Safe +//88 U020887 C20887 0x87 Missing Message Lost Communication With "Seat Control Module A" (SMFL) - missing message Missing Message t > 3sec No Missing Message t > 1 sec Init Value CCU_Failure_Stat.CCU_CommFailure_Stat = 0x1 (Failure) Fail-Safe: Init Value --> Previous value Activation by VIN OK : DTC / CAN signal / VIN control NOK : Fail-Safe +//89 U020987 C20987 0x87 Missing Message Lost Communication With "Seat Control Module B" (SMFR) - missing message Missing Message t > 3sec No Missing Message t > 1 sec Init Value CCU_Failure_Stat.CCU_CommFailure_Stat = 0x1 (Failure) Fail-Safe: Init Value --> Previous value Activation by VIN OK : DTC / CAN signal / VIN control NOK : Fail-Safe +//90 U021087 C21087 0x87 Missing Message Lost Communication With "Seat Control Module C" (SMRL) - missing message Missing Message t > 3sec No Missing Message t > 1 sec Init Value CCU_Failure_Stat.CCU_CommFailure_Stat = 0x1 (Failure) Fail-Safe: Init Value --> Previous value Activation by VIN OK : DTC / CAN signal / VIN control NOK : Fail-Safe +//91 U021187 C21187 0x87 Missing Message Lost Communication With "Seat Control Module D" (SMRR) - missing message Missing Message t > 3sec No Missing Message t > 1 sec Init Value CCU_Failure_Stat.CCU_CommFailure_Stat = 0x1 (Failure) Fail-Safe: Init Value --> Previous value Activation by VIN OK : DTC / CAN signal / VIN control NOK : Fail-Safe +//92 U22A187 E2A187 0x87 Missing Message Lost Communication With Trunk Module (TM) or Climate Control Panels Front&Rear (CCPF/CCPR) - missing message Missing Message t > 3sec No Missing Message t > 1 sec Init Value CCU_Failure_Stat.CCU_CommFailure_Stat = 0x1 (Failure) Fail-Safe: Init Value --> Previous value OK : DTC / CAN signal NOK : Fail-Safe +//93 U22A287 E2A287 0x87 Missing Message Lost Communication With Central Gateway (CGW) - missing message Missing Message t > 3sec No Missing Message t > 1 sec Init Value CCU_Failure_Stat.CCU_CommFailure_Stat = 0x1 (Failure) Fail-Safe: Init Value --> Previous value EMS, ESC and HVC OK : DTC / CAN signal NOK : Fail-Safe +//94 U223087 E23087 0x87 Missing Message Defroster Gate Actuator(LIN 0::0) - Missing Message Unrelated to HW - Fail "Auto-Addressing" After Ign on - Communication Fail when normal operation t > 4sec LIN Comm. is re-started Immediately Actuator Stop CCU_Body_Err.CCU_ActuatorErrF_Stat = 0x1 (Failure) OK : DTC / CAN signal NOK : Fail-Safe +//95 U223187 E23187 0x87 Missing Message Recirculation Gate Actuator (LIN0::1) - Missing Message +//96 U226287 E26287 0x87 Missing Message Recirculation OSA Gate Actuator (LIN0::2) - Missing Message +//97 U223287 E23287 0x87 Missing Message Temp_Up_FL Gate Actuator (LIN0::3) - Missing Message +//98 U223387 E23387 0x87 Missing Message Vent_CFL Gate Actuator (LIN0::4) - Missing Message +//99 U223487 E23487 0x87 Missing Message Foot_FR Gate Actuator (LIN1::5) - Missing Message +//100 U223587 E23587 0x87 Missing Message Temp_Dn_FL Gate Actuator (LIN0::6) - Missing Message +//101 U223687 E23687 0x87 Missing Message Foot_FL Gate Actuator (LIN0::7) - Missing Message +//102 U223787 E23787 0x87 Missing Message Rear_Foot_FL Gate Actuator (LIN0::8) - Missing Message +//103 U223887 E23887 0x87 Missing Message Temp_Up_FR Gate Actuator (LIN1::1) - Missing Message - Fail "Auto-Addressing" After Ign on - Communication Fail when normal operation t > 4sec LIN Comm. is re-started Immediately Actuator Stop CCU_Body_Err.CCU_ActuatorErrF_Stat = 0x1 (Failure) OK : DTC / CAN signal NOK : Fail-Safe +//104 U223987 E23987 0x87 Missing Message Vent_CFR Gate Actuator (LIN1::2) - Missing Message +//105 U224087 E24087 0x87 Missing Message Vent_SFR Gate Actuator (LIN1::3) - Missing Message +//106 U224187 E24187 0x87 Missing Message Temp_Dn_FR Gate Actuator (LIN1::4) - Missing Message +//107 U224287 E24287 0x87 Missing Message Foot_FR Gate Actuator (LIN1::5) - Missing Message +//108 U224387 E24387 0x87 Missing Message Rear_Foot_FR Gate Actuator (LIN1::6) - Missing Message +//109 U224487 E24487 0x87 Missing Message Temp_RR Gate Actuator (LIN2::1) - Missing Message - Fail "Auto-Addressing" After Ign on - Communication Fail when normal operation t > 4sec LIN Comm. is re-started Immediately Actuator Stop CCU_Body_Err.CCU_ActuatorErrR_Stat = 0x1 (Failure) Activation by VIN Don't need VIN control because Rear is always present. (temporary solution) Rear HVAC always present - serial solution for Phase 1 OK : DTC / CAN signal NOK : Fail-Safe +//110 U224587 E24587 0x87 Missing Message Temp_RL Gate Actuator (LIN2::2) - Missing Message +//111 U224687 E24687 0x87 Missing Message Vent_SRL Gate Actuator (LIN2::3) - Missing Message +//112 U224787 E24787 0x87 Missing Message Temp_RL Gate Actuator (LIN2::4) - Missing Message +//113 U224887 E24887 0x87 Missing Message Vent_CRL Gate Actuator (LIN2::5) - Missing Message +//114 U224987 E24987 0x87 Missing Message Vent_CRR Gate Actuator (LIN2::6) - Missing Message +//115 U225087 E25087 0x87 Missing Message Foot_RR Gate Actuator (LIN2::7) - Missing Message +//116 U225187 E25187 0x87 Missing Message Vent_SRR Gate Actuator (LIN2::8) - Missing Message +//117 U225287 E25287 0x87 Missing Message Sealing Valve Gate Actuator (LIN2::9) - Missing Message - Fail "Auto-Addressing" After Ign on - Communication Fail when normal operation t > 4sec LIN Comm. is re-started Immediately Actuator Stop CCU_Body_Err.CCU_SealingValveErr_Stat = 0x1 (Failure) Activation by VIN (reserved for future use) Activation by VIN If it doesn't match physical sealing valve actuator and VIN, Added to U300256 maturation failure threshold OK : DTC /CAN signal / VIN control NOK : Fail-Safe +//118 U225387 E25387 0x87 Missing Message Air quality sensor (LIN3) - Missing Message - Communication Fail when normal operation t > 4sec LIN Comm. is re-started Immediately tbd CCU_Body_Err.CCU_AirQualSenErr_Stat = 0x3 (Communication error) OK : DTC / CAN signal NOK : re-satrt +//119 U225487 E25487 0x87 Missing Message Ionizer (LIN3) - Missing Message - Communication Fail when normal operation t > 4sec LIN Comm. is re-started Immediately tbd CCU_Body_Err.CCU_IonizationErr_Stat = 0x3 (Communication error) +//120 U225587 E25587 0x87 Missing Message Aromatization (LIN3) - Missing Message - Communication Fail when normal operation t > 4sec LIN Comm. is re-started Immediately tbd CCU_Body_Err.CCU_AromaErr_Stat = 0x3 (Communication error) Related to 0xCF00 DID +//121 U225687 E25687 0x87 Missing Message Front TXV (LIN3) - Missing Message - Communication Fail when normal operation t > 4sec LIN Comm. is re-started Immediately tbd CCU_Body_Err.CCU_ETXVerr_Stat = 0x1 (Failure) suppress as SW, not used in Phase 1 +//122 U225787 E25787 0x87 Missing Message Rear TXV (LIN3) - Missing Message - Communication Fail when normal operation t > 4sec LIN Comm. is re-started Immediately tbd CCU_Body_Err.CCU_ETXVerr_Stat = 0x1 (Failure) +//123 U225887 E25887 0x87 Missing Message High voltage battery chiller TXV (LIN3) - Missing Message - Communication Fail when normal operation t > 4sec LIN Comm. is re-started Immediately tbd CCU_Body_Err.CCU_ETXVerr_Stat = 0x1 (Failure) +//124 U225987 E25987 0x87 Missing Message Heat pump chiller TXV (LIN3) - Missing Message - Communication Fail when normal operation t > 4sec LIN Comm. is re-started Immediately tbd CCU_Body_Err.CCU_ETXVerr_Stat = 0x1 (Failure) +//125 U226087 E26087 0x87 Missing Message DRS for front zone (LIN4) - Missing Message - Communication Fail when normal operation t > 4sec LIN Comm. is re-started Immediately tbd CCU_Body_Err.CCU_DRSerrF_Stat = 0x1 (Failure) OK : DTC / CAN signal NOK : re-satrt +//126 U226187 E26187 0x87 Missing Message DRS for rear zone (LIN4) - Missing Message - Communication Fail when normal operation t > 4sec LIN Comm. is re-started Immediately tbd CCU_Body_Err.CCU_DRSerrF_Stat = 0x1 (Failure) Activation by VIN OK : DTC / CAN signal / VIN control NOK : re-satrt +//127 U300256 F00256 0x56 Invalid / incompatible configuration Vehicle Identification Number - invalid / incompatible configuration Unrelated to HW The VIN check should be performed once per power cycle Failure if any of the following conditions are true: - VIN has not been written yet - VIN has not been fully received (all frames of multiplexed message) within 45 s after T15 on - VIN has been fully received (all frames of multiplexed message) BUT received VIN is not identical to stored VIN - VIN is not corresponding with system configuration - Immediately - t > 45sec - Immediately Receive proper VIN message Immediately Default VIN: - Value : Null - Sedan/NonArmored CCU_Failure_Stat.CCU_VinRecordFailure_Stat = 0x1 (Failure) OK : DTC / Fail-Safe / CAN signal / VIN control + + + +#endif //HVAC_M7_STATUSERROR_H diff --git a/MODULES/HVAC_M7_StatusData/modular.json b/MODULES/HVAC_M7_StatusData/modular.json new file mode 100644 index 0000000..9589ff8 --- /dev/null +++ b/MODULES/HVAC_M7_StatusData/modular.json @@ -0,0 +1,13 @@ +{ + "dep": [ + + ], + "cmake": { + "inc_dirs": [ + "./" + ], + "srcs": [ + "./**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_StorageOnFlash/StorageOnFlash.c b/MODULES/HVAC_M7_StorageOnFlash/StorageOnFlash.c new file mode 100644 index 0000000..170a670 --- /dev/null +++ b/MODULES/HVAC_M7_StorageOnFlash/StorageOnFlash.c @@ -0,0 +1,24 @@ +// +// Created by CFIF on 05.04.24. +// +#include "StorageOnFlash.h" + +#define LOG_SIGN "INIT" +#define LOGGER logger + +tStorageOnFlash NVM_STORAGE; + +void StorageOnFlash_Init(tLoggerInterface *logger) { + tStorageOnFlash *env = &NVM_STORAGE; + + vStorageOnFlashFlagchip_Init(&env->nf_storage_calib, STORAGE_TYPE_D_DATA, nf_storage_calib_mainFlashPageAddress,nf_storage_calib_recoveryFlashPageAddress); + env->interface_calib = xStorageOnFlashFlagchip_GetInterface(&env->nf_storage_calib); + + LoggerFormatInfo(LOGGER, LOG_SIGN, "Initialization calibrations STORE, Main adr: 0x%08X Recovery adr: 0x%08X", env->nf_storage_calib.mainFlashPageAddress, env->nf_storage_calib.recoveryFlashPageAddress) + + vStorageOnFlashFlagchip_Init(&env->nf_storage_param, STORAGE_TYPE_D_DATA, nf_storage_param_mainFlashPageAddress,nf_storage_param_recoveryFlashPageAddress); + env->interface_param = xStorageOnFlashFlagchip_GetInterface(&env->nf_storage_param); + + LoggerFormatInfo(LOGGER, LOG_SIGN, "Initialization parameters STORE, Main adr: 0x%08X Recovery adr: 0x%08X", env->nf_storage_param.mainFlashPageAddress, env->nf_storage_param.recoveryFlashPageAddress) + +} \ No newline at end of file diff --git a/MODULES/HVAC_M7_StorageOnFlash/StorageOnFlash.h b/MODULES/HVAC_M7_StorageOnFlash/StorageOnFlash.h new file mode 100644 index 0000000..77ed223 --- /dev/null +++ b/MODULES/HVAC_M7_StorageOnFlash/StorageOnFlash.h @@ -0,0 +1,31 @@ +// +// Created by CFIF on 05.04.24. +// + +#ifndef HVAC_STORAGEONFLASH_H +#define HVAC_STORAGEONFLASH_H + +#include "StorageOnFlashFlagchip.h" + +#define nf_storage_param_size (2 * FLASH_PAGE_D_SIZE) +#define nf_storage_param_mainFlashPageAddress 0x04001000 +#define nf_storage_param_recoveryFlashPageAddress 0x04002000 + +#define nf_storage_calib_size (10 * FLASH_PAGE_D_SIZE) +#define nf_storage_calib_mainFlashPageAddress 0x0400A000 +#define nf_storage_calib_recoveryFlashPageAddress 0x0400F000 + +typedef struct { + tStorageOnFlashFlagchip nf_storage_calib; + tStorageInterface interface_calib; + + tStorageOnFlashFlagchip nf_storage_param; + tStorageInterface interface_param; +} tStorageOnFlash; + + +extern tStorageOnFlash NVM_STORAGE; + +void StorageOnFlash_Init(tLoggerInterface *logger); + +#endif //HVAC_STORAGEONFLASH_H diff --git a/MODULES/HVAC_M7_StorageOnFlash/modular.json b/MODULES/HVAC_M7_StorageOnFlash/modular.json new file mode 100644 index 0000000..0dd1901 --- /dev/null +++ b/MODULES/HVAC_M7_StorageOnFlash/modular.json @@ -0,0 +1,10 @@ +{ + "cmake": { + "inc_dirs": [ + "./" + ], + "srcs": [ + "./**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_adc.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_adc.h new file mode 100644 index 0000000..328e643 --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_adc.h @@ -0,0 +1,1537 @@ +/** + * @file HwA_adc.h + * @author Flagchip0126 + * @brief Hardware access layer for ADC + * @version 0.1.0 + * @date 2024-01-15 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-15 Flagchip0126 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef _HWA_ADC_H_ +#define _HWA_ADC_H_ + +#include "device_header.h" + +/** + * @defgroup HwA_adc + * @ingroup fc7xxx_driver_adc + * @{ + */ + +/** + * @brief Select the ADC Resolution + * + */ +typedef enum +{ + ADC_RESOLUTION_12_BIT = 0U, /*!< 12 bit resolution */ + ADC_RESOLUTION_10_BIT = 1U, /*!< 10 bit resolution */ + ADC_RESOLUTION_8_BIT = 2U /*!< 8 bit resolution */ +} ADC_ResolutionType; + +/** + * @brief Select the ADC result alignment + * + */ +typedef enum +{ + ADC_ALIGN_RIGHT = 0U, /*!< ADC result is aligned in right */ + ADC_ALIGN_LEFT = 1U /*!< ADC result is aligned in left */ +} ADC_AlignType; + +/** + * @brief Select the ADC trigger mode + * + * @note This option is only valid in ADC single sequence mode and ADC continuous mode. + * In ADC discontinuous mode, the ADC trigger mode is fixed as ADC_TRIGMODE_RISING_EDGE + * + */ +typedef enum +{ + ADC_TRIGMODE_SW = 0U, /*!< ADC is triggered by software */ + ADC_TRIGMODE_RISING_EDGE = 1U, /*!< ADC is triggered by hardware trigger on rising edge */ + ADC_TRIGMODE_FALLING_EDGE = 2U, /*!< ADC is triggered by hardware trigger on falling edge */ + ADC_TRIGMODE_BOTH_EDGE = 3U, /*!< ADC is triggered by hardware trigger on both edges */ + ADC_TRIGMODE_HIGH_VOLTAGE = 4U, /*!< ADC is triggered when hardware trigger is high voltage */ + ADC_TRIGMODE_LOW_VOLTAGE = 5U /*!< ADC is triggered when hardware trigger is low voltage */ +} ADC_TrigModeType; + +/** + * @brief Select the ADC sequence mode + * + */ +typedef enum +{ + ADC_SEQMODE_SINGLE = 0U, /*!< ADC single sequence mode */ + ADC_SEQMODE_CONTINUOUS = 1U, /*!< ADC continuous mode */ + ADC_SEQMODE_DISCONTINUOUS_0 = 2U, /*!< ADC discontinuous 0 mode */ + ADC_SEQMODE_DISCONTINUOUS_1 = 3U /*!< ADC discontinuous 1 mode */ +} ADC_SeqModeType; + +/** + * @brief Select the ADC overrun management mode + * + * To select whether the old data are preserved or overwritten by the new data when ADC + * is overrun (The FIFO is full when new convertion result comes) + * + */ +typedef enum +{ + ADC_OVERRUN_MODE_PRESERVE = 0U, /*!< old data are preserved when ADC is overrun */ + ADC_OVERRUN_MODE_OVERWRITE = 1U /*!< old data are overwritten when ADC is overrun */ +} ADC_OvrModeType; + +/** + * @brief Select the ADC voltage reference source + * + */ +typedef enum +{ + ADC_REF_INTERNAL = 0U, /*!< select the internal voltage reference */ + ADC_REF_EXTERNAL = 1U /*!< select the external voltage reference */ +} ADC_RefType; + +/** + * @brief Select the priority of Trigger Latch Unit + * + */ +typedef enum +{ + TRG_LATCH_UNIT_PRI_ROUND_ROBIN = 0U, /*!< select the round robin scheduling priority */ + TRG_LATCH_UNIT_PRI_FIX = 1U /*!< select the fixed priority(0>1>2>3) */ +} ADC_TrgLatchUnitPri; + +/** + * @brief Select the ADC hardware average samples + * + */ +typedef enum +{ + ADC_AVERAGE_4 = 0U, /*!< result average by 4 samples */ + ADC_AVERAGE_8 = 1U, /*!< result average by 8 samples */ + ADC_AVERAGE_16 = 2U, /*!< result average by 16 samples */ + ADC_AVERAGE_32 = 3U /*!< result average by 32 samples */ +} ADC_AverageType; + +/** + * @brief Set the ADC clock divider + * + * @note ADC clock divider is not available in FC4150F512K + * + */ +typedef enum +{ + ADC_CLOCK_DIV_1 = 0U, + ADC_CLOCK_DIV_2 = 1U, + ADC_CLOCK_DIV_4 = 2U, + ADC_CLOCK_DIV_8 = 3U +} ADC_ClockDivideType; + +/** + * @brief The trigger source of the ADC instance + * + * @note In ADC discontinuous 1 mode, the trigger source is from Ptimer + * In ADC single and continuous mode, if hardware trigger is enabled, the trigger + * source is from TRGSEL + * + */ +typedef enum +{ + ADC_TRIGSRC_PTIMER = 0U, /* Trigger source from PTIMER/TRGSEL with Ptimer */ + ADC_TRIGSRC_TRGSEL = 2U, /* Trigger source from TRGSEL */ + ADC_TRIGSRC_TRIG_LATCH_UNIT = 3U /* Trigger source from LATCH UNIT */ +} ADC_TrigSrcType; + +/** + * @brief Select the channel compare mode + * + * Select whether the channel compare is enabled on all channels or on the single + * selected channel + * + */ +typedef enum +{ + ADC_CMP_CHANNEL_ALL = 0U, /*!< Compare enabled in all channels */ + ADC_CMP_CHANNEL_SINGLE = 1U /*!< Compare enabled in the specified channel */ +} ADC_CmpChannelType; + +/** + * @brief Check whether the conversion result is in the comparing range + * + * @param pAdc the base address of the ADC instance + * @return true the conversion result is in the comparing range + * @return false the conversion result is not in the comparing range + */ +LOCAL_INLINE bool ADC_HWA_GetCompareFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->INT_STATUS; + u32TmpVal = (u32TmpVal & ADC_INT_STATUS_ACMP_MASK) >> ADC_INT_STATUS_ACMP_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the compare flag + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_ClearCompareFlag(ADC_Type *const pAdc) +{ + pAdc->INT_STATUS = ADC_INT_STATUS_ACMP(1U); +} + +/** + * @brief Get the overrrun status of the ADC instance + * + * @param pAdc the base address of the ADC instance + * @return true the ADC is in overrun status + * @return false the ADC is not overrun + */ +LOCAL_INLINE bool ADC_HWA_GetOverRun(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->INT_STATUS; + u32TmpVal = (u32TmpVal & ADC_INT_STATUS_OVR_MASK) >> ADC_INT_STATUS_OVR_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the overrun flag of the ADC instance + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_ClearOverRun(ADC_Type *const pAdc) +{ + pAdc->INT_STATUS = ADC_INT_STATUS_OVR(1U); +} + +/** + * @brief Check whether the ADC conversion sequence is finished + * + * @param pAdc the base address of the ADC instance + * @return true the ADC conversion sequence is finished + * @return false the ADC conversion sequence is unfinished + */ +LOCAL_INLINE bool ADC_HWA_GetEndOfSequence(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->INT_STATUS; + u32TmpVal = (u32TmpVal & ADC_INT_STATUS_EOSEQ_MASK) >> ADC_INT_STATUS_EOSEQ_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the ADC conversion sequence complete flag + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_ClearEndOfSequence(ADC_Type *const pAdc) +{ + pAdc->INT_STATUS = ADC_INT_STATUS_EOSEQ(1U); +} + +/** + * @brief Check whether the current ADC conversion is finished + * + * @param pAdc the base address of the ADC instance + * @return true the current ADC conversion is finished + * @return false the current ADC conversion is unfinished + */ +LOCAL_INLINE bool ADC_HWA_GetEndOfConversion(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->INT_STATUS; + u32TmpVal = (u32TmpVal & ADC_INT_STATUS_EOC_MASK) >> ADC_INT_STATUS_EOC_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the ADC single conversion complete flag + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_ClearEndOfConversion(ADC_Type *const pAdc) +{ + pAdc->INT_STATUS = ADC_INT_STATUS_EOC(1U); +} + +/** + * @brief Check whether the sampling phase of the current ADC conversion is finished + * + * @param pAdc the base address of the ADC instance + * @return true the sampling phase of the ADC conversion is finished + * @return false the sampling phase of the ADC conversion is unfinished + */ +LOCAL_INLINE bool ADC_HWA_GetEndOfSample(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->INT_STATUS; + u32TmpVal = (u32TmpVal & ADC_INT_STATUS_EOSMP_MASK) >> ADC_INT_STATUS_EOSMP_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the ADC sampling complete flag + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_ClearEndOfSample(ADC_Type *const pAdc) +{ + pAdc->INT_STATUS = ADC_INT_STATUS_EOSMP(1U); +} + +/** + * @brief Check whether the data quantity in the FIFO is greater than watermark + * + * @param pAdc the base address of the ADC instance + * @return true the ADC FIFO is ready + * @return false the ADC FIFO is unready + */ +LOCAL_INLINE bool ADC_HWA_GetFIFOReady(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->INT_STATUS; + u32TmpVal = (u32TmpVal & ADC_INT_STATUS_FIFO_RDY_MASK) >> ADC_INT_STATUS_FIFO_RDY_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the FIFO ready flag + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_ClearFIFOReady(ADC_Type *const pAdc) +{ + pAdc->INT_STATUS = ADC_INT_STATUS_FIFO_RDY(1U); +} + +/** + * @brief Check whether the ADC FIFO is full + * + * @param pAdc the base address of the ADC instance + * @return true the ADC FIFO is full + * @return false the ADC FIFO is not full + */ +LOCAL_INLINE bool ADC_HWA_GetFull(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->INT_STATUS; + u32TmpVal = (u32TmpVal & ADC_INT_STATUS_FULL_MASK) >> ADC_INT_STATUS_FULL_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Check whether the ADC FIFO is empty + * + * @param pAdc the base address of the ADC instance + * @return true the ADC FIFO is empty + * @return false the ADC FIFO is not empty + */ +LOCAL_INLINE bool ADC_HWA_GetEmpty(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->INT_STATUS; + u32TmpVal = (u32TmpVal & ADC_INT_STATUS_EMPTY_MASK) >> ADC_INT_STATUS_EMPTY_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Check whether the ADC instance is ready to operate + * + * @param pAdc the base address of the ADC instance + * @return true the ADC instance is ready for a new conversion + * @return false the ADC instance is unready + */ +LOCAL_INLINE bool ADC_HWA_GetReady(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->INT_STATUS; + u32TmpVal = (u32TmpVal & ADC_INT_STATUS_ADRDY_MASK) >> ADC_INT_STATUS_ADRDY_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the ready flag of the ADC instance + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_ClearReady(ADC_Type *const pAdc) +{ + pAdc->INT_STATUS = ADC_INT_STATUS_ADRDY(1U); +} + +/** + * @brief Get the FIFO Ready interrupt flag + * If enabled, ADC interrupt is generated when the FIFO water mark is greater than FWMARK + * @param pAdc the base address of the ADC instance + * @return true ADC FIFO Ready interrupt is enabled + * @return false ADC FIFO Ready interrupt is disabled + */ +LOCAL_INLINE bool ADC_HWA_GetFIFOReadyInterruptFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->INT_ENABLE & ADC_INT_ENABLE_FIFO_RDY_IE_MASK) >> ADC_INT_ENABLE_FIFO_RDY_IE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the FIFO Ready interrupt flag + * If enabled, ADC interrupt is generated when the FIFO water mark is greater than FWMARK + * @param pAdc the base address of the ADC instance + * @param bEnable whether to enable the ADC FIFO Ready interrupt + */ +LOCAL_INLINE void ADC_HWA_SetFIFOReadyInterruptFlag(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->INT_ENABLE = (pAdc->INT_ENABLE & ~ADC_INT_ENABLE_FIFO_RDY_IE_MASK) | ADC_INT_ENABLE_FIFO_RDY_IE(bEnable); +} + +/** + * @brief Get the Compare interrupt flag + * If enabled, ADC interrupt is generated when the ADC conversion result is not within the compare threshold + * @param pAdc the base address of the ADC instance + * @return true ADC Compare interrupt is enabled + * @return false ADC Compare interrupt is disabled + */ +LOCAL_INLINE bool ADC_HWA_GetCompareInterruptFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->INT_ENABLE & ADC_INT_ENABLE_ACMP_IE_MASK) >> ADC_INT_ENABLE_ACMP_IE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the Compare interrupt flag + * If enabled, ADC interrupt is generated when the ADC conversion result is not within the compare threshold + * @param pAdc the base address of the ADC instance + * @param bEnable whether to enable the ADC Compare interrupt + */ +LOCAL_INLINE void ADC_HWA_SetCompareInterruptFlag(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->INT_ENABLE = (pAdc->INT_ENABLE & ~ADC_INT_ENABLE_ACMP_IE_MASK) | ADC_INT_ENABLE_ACMP_IE(bEnable); +} + +/** + * @brief Get the Overrun interrupt flag + * If enabled, ADC interrupt is generated when the ADC instance is overrun + * @param pAdc the base address of the ADC instance + * @return true ADC Overrun interrupt is enabled + * @return false ADC Overrun interrupt is disabled + */ +LOCAL_INLINE bool ADC_HWA_GetOverrunInterruptFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->INT_ENABLE & ADC_INT_ENABLE_OVRIE_MASK) >> ADC_INT_ENABLE_OVRIE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the Overrun interrupt flag + * If enabled, ADC interrupt is generated when the ADC instance is overrun + * @param pAdc the base address of the ADC instance + * @param bEnable whether to enable the ADC Overrun interrupt + */ +LOCAL_INLINE void ADC_HWA_SetOverrunInterruptFlag(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->INT_ENABLE = (pAdc->INT_ENABLE & ~ADC_INT_ENABLE_OVRIE_MASK) | ADC_INT_ENABLE_OVRIE(bEnable); +} + +/** + * @brief Get the End of Sequence interrupt enable flag + * If enabled, ADC interrupt is generated when the ADC sequence conversion is completed + * @param pAdc the base address of the ADC instance + * @return true ADC End of Sequence interrupt is enabled + * @return false ADC End of Sequence interrupt is disabled + */ +LOCAL_INLINE bool ADC_HWA_GetEndOfSequenceInterruptFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->INT_ENABLE & ADC_INT_ENABLE_EOSEQIE_MASK) >> ADC_INT_ENABLE_EOSEQIE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the End of Sequence interrupt enable flag + * If enabled, ADC interrupt is generated when the ADC sequence conversion is completed + * @param pAdc the base address of the ADC instance + * @param bEnable whether to enable the ADC End of Sequence interrupt + */ +LOCAL_INLINE void ADC_HWA_SetEndOfSequenceInterruptFlag(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->INT_ENABLE = (pAdc->INT_ENABLE & ~ADC_INT_ENABLE_EOSEQIE_MASK) | ADC_INT_ENABLE_EOSEQIE(bEnable); +} + +/** + * @brief Get the conversion complete interrupt enable flag + * If enabled, ADC interrupt is generated when each ADC conversion is completed + * @param pAdc the base address of the ADC instance + * @return true the ADC End of Conversion interrupt is enabled + * @return false the ADC End of Conversion interrupt is disabled + */ +LOCAL_INLINE bool ADC_HWAGetEndOfConversionInterruptFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->INT_ENABLE & ADC_INT_ENABLE_EOCIE_MASK) >> ADC_INT_ENABLE_EOCIE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the conversion complete interrupt enable flag + * If enabled, ADC interrupt is generated when each ADC conversion is completed + * @param pAdc the base address of the ADC instance + * @param bEnable whether to enable the conversion complete interrupt + */ +LOCAL_INLINE void ADC_HWA_SetEndOfConversionInterruptFlag(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->INT_ENABLE = (pAdc->INT_ENABLE & ~ADC_INT_ENABLE_EOCIE_MASK) | ADC_INT_ENABLE_EOCIE(bEnable); +} + +/** + * @brief Get the sample complete interrupt enable flag + * If enabled, ADC interrupt is generated when each ADC conversion finished the sampling phase + * @param pAdc the base address of the ADC instance + * @return true the sample complete interrupt is enabled + * @return false the sample complete interrupt is disabled + */ +LOCAL_INLINE bool ADC_HWA_GetEndOfSampleInterruptFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->INT_ENABLE & ADC_INT_ENABLE_EOSMPIE_MASK) >> ADC_INT_ENABLE_EOSMPIE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the sample complete interrupt enable flag + * If enabled, ADC interrupt is generated when each ADC conversion finished the sampling phase + * @param pAdc the base address of the ADC instance + * @param bEnable whether to enable the sample complete interrupt + */ +LOCAL_INLINE void ADC_HWA_SetEndOfSampleInterruptFlag(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->INT_ENABLE = (pAdc->INT_ENABLE & ~ADC_INT_ENABLE_EOSMPIE_MASK) | ADC_INT_ENABLE_EOSMPIE(bEnable); +} + +/** + * @brief Get the ADC ready interrupt enable flag + * If enabled, ADC interrupt is generated when the ADC module is ready for conversion + * @param pAdc the base address of the ADC instance + * @return true the ADC ready interrupt is enabled + * @return false the ADC ready interrupt is disabled + */ +LOCAL_INLINE bool ADC_HWA_GetADCReadyInterruptFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->INT_ENABLE & ADC_INT_ENABLE_ADRDYIE_MASK) >> ADC_INT_ENABLE_ADRDYIE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the ADC ready interrupt enable flag + * If enabled, ADC interrupt is generated when the ADC module is ready for conversion + * @param pAdc the base address of the ADC instance + * @param bEnable Whether to enable the ADC ready interrupt + */ +LOCAL_INLINE void ADC_HWA_SetADCReadyInterruptFlag(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->INT_ENABLE = (pAdc->INT_ENABLE & ~ADC_INT_ENABLE_ADRDYIE_MASK) | ADC_INT_ENABLE_ADRDYIE(bEnable); +} + +/** + * @brief Get the interrupt enable config + * + * @param pAdc the base address of the ADC instance + * @return uint32_t the interrupt enable config + */ +LOCAL_INLINE uint32_t ADC_HWA_GetInterruptEnable(const ADC_Type *const pAdc) +{ + return pAdc->INT_ENABLE; +} + +/** + * @brief Set the interrupt enable + * + * @param u32InterruptCfg the interrupt enable config + */ +LOCAL_INLINE void ADC_HWA_SetInterruptEnable(ADC_Type *const pAdc, uint32_t u32InterruptCfg) +{ + pAdc->INT_ENABLE = u32InterruptCfg; +} + +/** + * @brief Reset the ADC hardware + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_Reset(ADC_Type *const pAdc) +{ + pAdc->CONTROL = ADC_CONTROL_ADRST(1U); + pAdc->CONTROL = 0U; +} + +/** + * @brief Get the enable status of the ADC instance + * + * @param pAdc the base address of the ADC instance + * @return true the ADC instance is enabled + * @return false the ADC instance has not been enabled + */ +LOCAL_INLINE bool ADC_HWA_GetEnable(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->CONTROL; + u32TmpVal = (u32TmpVal & ADC_CONTROL_ADEN_MASK) >> ADC_CONTROL_ADEN_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Enable the ADC instance + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_Enable(ADC_Type *const pAdc) +{ + pAdc->CONTROL = ADC_CONTROL_ADEN(1U); +} + +/** + * @brief Get whether the ADC instance is in disable status + * + * @param pAdc the base address of the ADC instance + * @return true the ADC instance is in disable status + * @return false the ADC instance is not in disable status + */ +LOCAL_INLINE bool ADC_HWA_GetDisable(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->CONTROL; + u32TmpVal = (u32TmpVal & ADC_CONTROL_ADDIS_MASK) >> ADC_CONTROL_ADDIS_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Disable the ADC instance + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_Disable(ADC_Type *const pAdc) +{ + pAdc->CONTROL = ADC_CONTROL_ADDIS(1U); +} + +/** + * @brief Get the conversion start status of the ADC instance + * + * @param pAdc the base address of the ADC instance + * @return true the conversion of the ADC instance is started + * @return false the conversion of the ADC instance has not been started + */ +LOCAL_INLINE bool ADC_HWA_GetStart(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->CONTROL; + u32TmpVal = (u32TmpVal & ADC_CONTROL_ADSTART_MASK) >> ADC_CONTROL_ADSTART_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Start the ADC conversion + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_Start(ADC_Type *const pAdc) +{ + pAdc->CONTROL = ADC_CONTROL_ADSTART(1U); +} + +/** + * @brief Get whether ADC is in stopping status + * + * @param pAdc the base address of the ADC instance + * @return true the ADC instance is stopping + * @return false the ADC instance is not in stopping status + */ +LOCAL_INLINE bool ADC_HWA_GetStop(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->CONTROL; + u32TmpVal = (u32TmpVal & ADC_CONTROL_ADSTP_MASK) >> ADC_CONTROL_ADSTP_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Stop the ADC conversion + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_Stop(ADC_Type *const pAdc) +{ + pAdc->CONTROL = ADC_CONTROL_ADSTP(1U); +} + +/** + * @brief Get the overrun management mode + * + * @param pAdc the base address of the ADC instance + * @return ADC_OVERRUN_MODE_PRESERVE the conversion data is preserved when ADC is overrun + * @return ADC_OVERRUN_MODE_OVERWRITE the conversion data is overwritten when ADC is overrun + */ +LOCAL_INLINE ADC_OvrModeType ADC_HWA_GetOverrunManagementMode(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG1 & ADC_CFG1_OVRMOD_MASK) >> ADC_CFG1_OVRMOD_SHIFT; + return (ADC_OvrModeType)u32TmpVal; +} + +/** + * @brief Set the overrun management mode + * + * @param pAdc the base address of the ADC instance + * @param eOvrMode the overrun management for the ADC instance + */ +LOCAL_INLINE void ADC_HWA_SetOverrunManagementMode(ADC_Type *const pAdc, ADC_OvrModeType eOvrMode) +{ + pAdc->CFG1 = (pAdc->CFG1 & ~ADC_CFG1_OVRMOD_MASK) | ADC_CFG1_OVRMOD(eOvrMode); +} + +/** + * @brief Get the sequence group mode state + * + * @param pAdc the base address of the ADC instance + * @return the sequence group mode state + */ +LOCAL_INLINE bool ADC_HWA_GetSeqGpEn(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG1 & ADC_CFG1_SEQGP_EN_MASK) >> ADC_CFG1_SEQ_LEN_SHIFT; + return u32TmpVal ? true : false; +} + +/** + * @brief Set the sequence group mode state + * + * @param pAdc the base address of the ADC instance + * @param the sequence group mode state + */ +LOCAL_INLINE void ADC_HWA_SetSeqGpEn(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->CFG1 = (pAdc->CFG1 & ~ADC_CFG1_SEQGP_EN_MASK) | ADC_CFG1_SEQGP_EN(bEnable); +} + +/** + * @brief Get the sequence length of the ADC conversion sequence + * + * @param pAdc the base address of the ADC instance + * @return uint8_t the sequence length of the ADC conversion sequence + */ +LOCAL_INLINE uint8_t ADC_HWA_GetSequenceLength(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->CFG1; + u32TmpVal = (u32TmpVal & ADC_CFG1_SEQ_LEN_MASK) >> ADC_CFG1_SEQ_LEN_SHIFT; + + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set the sequence length of the ADC conversion sequence + * + * @param pAdc the base address of the ADC instance + * @param u8SequenceLength the sequence length of the ADC conversion sequence + */ +LOCAL_INLINE void ADC_HWA_SetSequenceLength(ADC_Type *const pAdc, uint8_t u8SequenceLength) +{ + pAdc->CFG1 = (pAdc->CFG1 & ~ADC_CFG1_SEQ_LEN_MASK) | ADC_CFG1_SEQ_LEN(u8SequenceLength); +} + +/** + * @brief Get the ADC sequence mode + * + * @param pAdc the base address of the ADC instance + * @return ADC_SeqModeType the sequence mode the the ADC instance + */ +LOCAL_INLINE ADC_SeqModeType ADC_HWA_GetSequenceMode(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->CFG1; + u32TmpVal = (u32TmpVal & ADC_CFG1_SEQ_MOD_MASK) >> ADC_CFG1_SEQ_MOD_SHIFT; + + return (ADC_SeqModeType)u32TmpVal; +} + +/** + * @brief Set the ADC sequence mode + * + * @param pAdc the base address of the ADC instance + * @param eSequenceMode the sequence mode the the ADC instance + */ +LOCAL_INLINE void ADC_HWA_SetSequenceMode(ADC_Type *const pAdc, ADC_SeqModeType eSequenceMode) +{ + pAdc->CFG1 = (pAdc->CFG1 & ~ADC_CFG1_SEQ_MOD_MASK) | ADC_CFG1_SEQ_MOD(eSequenceMode); +} + +/** + * @brief Get whether auto disable is enabled + * + * @note Auto disable mode is only available in FC4150F2M + * + * @param pAdc the base address of the ADC instance + * @return true auto disable mode is enabled + * @return false auto disable mode is disabled + */ +LOCAL_INLINE bool ADC_HWA_GetAutoDisableModeEnableFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->CFG1; + u32TmpVal = (u32TmpVal & ADC_CFG1_AUTO_DIS_MASK) >> ADC_CFG1_AUTO_DIS_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable auto disable mode + * + * @note Auto disable mode is only available in FC4150F2M + * + * @param pAdc the base address of the ADC instance + * @param bEnable whether to enable auto disable mode + */ +LOCAL_INLINE void ADC_HWA_SetAutoDisableModeEnableFlag(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->CFG1 = (pAdc->CFG1 & ~ADC_CFG1_AUTO_DIS_MASK) | ADC_CFG1_AUTO_DIS(bEnable); +} + +/** + * @brief Get whether the wait conversion mode is enabled + * + * @param pAdc the base address of the ADC instance + * @return true the wait conversion mode is enabled + * @return false the wait conversion mode is disabled + */ +LOCAL_INLINE bool ADC_HWA_GetWaitConversionModeFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG1 & ADC_CFG1_WAIT_MASK) >> ADC_CFG1_WAIT_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the wait conversion mode + * + * @param pAdc the base address of the ADC instance + * @param bEnable whether to enable the wait conversion mode + */ +LOCAL_INLINE void ADC_HWA_SetWaitConversionModeFlag(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->CFG1 = (pAdc->CFG1 & ~ADC_CFG1_WAIT_MASK) | ADC_CFG1_WAIT(bEnable); +} + +/** + * @brief Get the trigger source the the ADC instance + * + * @param pAdc the base address of the ADC instance + * @return ADC_TrigSrcType the trigger source of the ADC instance + */ +LOCAL_INLINE ADC_TrigSrcType ADC_HWA_GetTriggerSource(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->CFG1; + u32TmpVal = (u32TmpVal & ADC_CFG1_TRIGSRC_MASK) >> ADC_CFG1_TRIGSRC_SHIFT; + + return (ADC_TrigSrcType)u32TmpVal; +} + +/** + * @brief Set the trigger source the the ADC instance + * + * @param pAdc the base address of the ADC instance + * @param eTriggerSource the trigger source of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_SetTriggerSource(ADC_Type *const pAdc, ADC_TrigSrcType eTriggerSource) +{ + pAdc->CFG1 = (pAdc->CFG1 & ~ADC_CFG1_TRIGSRC_MASK) | ADC_CFG1_TRIGSRC(eTriggerSource); +} + +/** + * @brief Get the trigger mode of the ADC instance + * + * @param pAdc the base address of the ADC instance + * @return ADC_TrigModeType the trigger mode if the ADC instance + */ +LOCAL_INLINE ADC_TrigModeType ADC_HWA_GetTriggerMode(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->CFG1; + u32TmpVal = (u32TmpVal & ADC_CFG1_TRIGMODE_MASK) >> ADC_CFG1_TRIGMODE_SHIFT; + + return (ADC_TrigModeType)u32TmpVal; +} + +/** + * @brief Set the trigger mode of the ADC instance + * + * @param pAdc the base address of the ADC instance + * @param eTriggerMode the trigger mode if the ADC instance + */ +LOCAL_INLINE void ADC_HWA_SetTriggerMode(ADC_Type *const pAdc, ADC_TrigModeType eTriggerMode) +{ + pAdc->CFG1 = (pAdc->CFG1 & ~ADC_CFG1_TRIGMODE_MASK) | ADC_CFG1_TRIGMODE(eTriggerMode); +} + +/** + * @brief Get the data align mode + * + * @param pAdc the base address of the ADC instance + * @return ADC_ALIGN_RIGHT the conversion data is aligned right + * @return ADC_ALIGN_LEFT the conversion is aligned left + */ +LOCAL_INLINE ADC_AlignType ADC_HWA_GetDataAlignment(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG1 & ADC_CFG1_ALIGN_MASK) >> ADC_CFG1_ALIGN_SHIFT; + return (ADC_AlignType)u32TmpVal; +} + +/** + * @brief Set the data align mode + * + * @param pAdc the base address of the ADC instance + * @param eAlign the data align mode + */ +LOCAL_INLINE void ADC_HWA_SetDataAlignment(ADC_Type *const pAdc, ADC_AlignType eAlign) +{ + pAdc->CFG1 = (pAdc->CFG1 & ~ADC_CFG1_ALIGN_MASK) | ADC_CFG1_ALIGN(eAlign); +} + +/** + * @brief Get the ADC resolution of the ADC instance + * + * @param pAdc the base address of the ADC instance + * @return ADC_ResolutionType the resolution of the ADC instance + */ +LOCAL_INLINE ADC_ResolutionType ADC_HWA_GetDataResolution(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG1 & ADC_CFG1_RES_MASK) >> ADC_CFG1_RES_SHIFT; + return (ADC_ResolutionType)u32TmpVal; +} + +/** + * @brief Set the resolution of the ADC instance + * + * @param pAdc the base address of the ADC instance + * @param eResolution the resolution of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_SetDataResolution(ADC_Type *const pAdc, ADC_ResolutionType eResolution) +{ + pAdc->CFG1 = (pAdc->CFG1 & ~ADC_CFG1_RES_MASK) | ADC_CFG1_RES(eResolution); +} + +/** + * @brief Get whether DMA for the ADC instance is enabled + * + * @param pAdc the base address of the ADC instance + * @return true DMA is enabled for the ADC instance + * @return false DMA is disabled for the ADC instance + */ +LOCAL_INLINE bool ADC_HWA_GetDMAEnableFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG1 & ADC_CFG1_DMAEN_MASK) >> ADC_CFG1_DMAEN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Enable or disable the DMA for the ADC instance + * + * @param pAdc the base address of the ADC instance + * @param bEnable whether to enable the DMA for the ADC instance + */ +LOCAL_INLINE void ADC_HWA_SetDMAEnableFlag(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->CFG1 = (pAdc->CFG1 & ~ADC_CFG1_DMAEN_MASK) | ADC_CFG1_DMAEN(bEnable); +} + +/** + * @brief Get the ADC_CFG1 config + * + * @param pAdc the base address of the ADC instance + * @return uint32_t the ADC_CFG1 config + */ +LOCAL_INLINE uint32_t ADC_HWA_GetConfig1(const ADC_Type *const pAdc) +{ + return pAdc->CFG1; +} + +/** + * @brief Set the ADC_CFG1 config + * + * @param pAdc the base address of the ADC instance + * @param u32Config the ADC_CFG1 config + */ +LOCAL_INLINE void ADC_HWA_SetConfig1(ADC_Type *const pAdc, uint32_t u32Config) +{ + pAdc->CFG1 = u32Config; +} + +/** + * @brief Get the FIFO water mark settings for the ADC instance + * + * @param pAdc the base address of the ADC instance + * @return uint8_t the ADC FIFO water mark setting + */ +LOCAL_INLINE uint8_t ADC_HWA_GetFIFOWaterMark(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG2 & ADC_CFG2_FWMARK_MASK) >> ADC_CFG2_FWMARK_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set the FIFO water mark for the ADC instance + * + * @param pAdc the base address of the ADC instance + * @param u8WaterMark the ADC FIFO water mark setting + */ +LOCAL_INLINE void ADC_HWA_SetFIFOWaterMark(ADC_Type *const pAdc, uint8_t u8WaterMark) +{ + pAdc->CFG2 = (pAdc->CFG2 & ~ADC_CFG2_FWMARK_MASK) | ADC_CFG2_FWMARK(u8WaterMark); +} + +/** + * @brief Get the priority of Trigger Latch + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE uint8_t ADC_HWA_GetTriggerLatchUnitPriority(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG2 & ADC_CFG2_TRG_PRI_MASK) >> ADC_CFG2_TRG_PRI_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set the priority of Trigger Latch + * + * @param pAdc the base address of the ADC instance + * @param eTrgLatchUnitPri the priority of Trigger Latch Unit setting + */ +LOCAL_INLINE void ADC_HWA_SetTriggerLatchUnitPriority(ADC_Type *const pAdc, ADC_TrgLatchUnitPri eTrgLatchUnitPri) +{ + pAdc->CFG2 = (pAdc->CFG2 & ~ADC_CFG2_TRG_CLR_MASK) | ADC_CFG2_TRG_CLR(eTrgLatchUnitPri); +} + +/** + * @brief Clear Latch Trigger in Trigger Latch Unit + * + * @param pAdc the base address of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_ClearLatchTrigger(ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->CFG2; + pAdc->CFG2 = u32TmpVal | ADC_CFG2_TRG_CLR(1); +} + +/** + * @brief Get whether hardware average is enabled + * + * @param pAdc the base address of the ADC instance + * @return true hardware average is enabled + * @return false hardware average is disabled + */ +LOCAL_INLINE bool ADC_HWA_GetAverageEnableFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG2 & ADC_CFG2_AVG_EN_MASK) >> ADC_CFG2_AVG_EN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Enable or disable hardware average for the ADC instance + * + * @param pAdc the base address of the ADC instance + * @param bEnable whether to enable the ADC hardware average + */ +LOCAL_INLINE void ADC_HWA_SetAverageEnableFlag(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->CFG2 = (pAdc->CFG2 & ~ADC_CFG2_AVG_EN_MASK) | ADC_CFG2_AVG_EN(bEnable); +} + +/** + * @brief Get the hardware average number + * + * @param pAdc the base address of the ADC instance + * @return ADC_AverageType the hardware average number + */ +LOCAL_INLINE ADC_AverageType ADC_HWA_GetAverageNumber(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG2 & ADC_CFG2_AVG_LEN_MASK) >> ADC_CFG2_AVG_LEN_SHIFT; + return (ADC_AverageType)u32TmpVal; +} + +/** + * @brief Set the hardware average number + * + * @param pAdc the base address of the ADC instance + * @param eAverageNumber the hardware average number to set + */ +LOCAL_INLINE void ADC_HWA_SetAverageNumber(ADC_Type *const pAdc, ADC_AverageType eAverageNumber) +{ + pAdc->CFG2 = (pAdc->CFG2 & ~ADC_CFG2_AVG_LEN_MASK) | ADC_CFG2_AVG_LEN(eAverageNumber); +} +/** + * @brief Whether clock gating is acknowledged + * + * @note This feature is only available in FC4150F2M + * + * @param pAdc the base address of the ADC instance + * @return true ADC clock source is off after setting Clock Gating Enable Flag + * @return false ADC clock source is on after clearing Clock Gating Enable Flag + */ +LOCAL_INLINE bool ADC_HWA_GetClockGatingAck(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG2 & ADC_CFG2_CG_ACK_MASK) >> ADC_CFG2_CG_ACK_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get whether clock gating is enabled + * + * @note This feature is only available in FC4150F2M + * + * @param pAdc the base address of the ADC instance + * @return true Clock gating is enabled, ADC clock is off + * @return false Clock gating is disabled, ADC clock is on + */ +LOCAL_INLINE bool ADC_HWA_GetClockGatingEnableFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG2 & ADC_CFG2_CG_MASK) >> ADC_CFG2_CG_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable ADC clock gating + * + * @note This feature is only available in FC4150F2M + * + * @param pAdc the base address of the ADC instance + * @param bEnable whether to enable ADC clock gating + */ +LOCAL_INLINE void ADC_HWA_SetClockGatingEnableFlag(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->CFG2 = (pAdc->CFG2 & ~ADC_CFG2_CG_MASK) | ADC_CFG2_CG(bEnable); +} + +/** + * @brief Get the voltage reference of the ADC instance + * + * @param pAdc the base address of the ADC instance + * @return ADC_REF_INTERNAL the ADC instance uses internal voltage reference + * @return ADC_REF_EXTERNAL the ADC instance uses external voltage reference + */ +LOCAL_INLINE ADC_RefType ADC_HWA_GetVoltageReference(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG2 & ADC_CFG2_REF_EXT_MASK) >> ADC_CFG2_REF_EXT_SHIFT; + return (ADC_RefType)u32TmpVal; +} + +/** + * @brief Set the voltage reference of the ADC instance + * + * @param pAdc the base address of the ADC instance + * @param eRefSel the voltage reference of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_SetVoltageReference(ADC_Type *const pAdc, ADC_RefType eRefSel) +{ + pAdc->CFG2 = (pAdc->CFG2 & ~ADC_CFG2_REF_EXT_MASK) | ADC_CFG2_REF_EXT(eRefSel); +} + +/** + * @brief Get the ADC clock divider + * + * @note This feature is only available in FC4150F2M + * + * @param pAdc the base address of the ADC instance + * @return ADC_ClockDivideType the ADC clock divider + */ +LOCAL_INLINE ADC_ClockDivideType ADC_HWA_GetClockDivider(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG2 & ADC_CFG2_DIV_MASK) >> ADC_CFG2_DIV_SHIFT; + return (ADC_ClockDivideType)u32TmpVal; +} + +/** + * @brief Set the ADC clock divider + * + * @note Before configuring DIV, must set CG and wait for CG_ACK=1. + * After configuring DIV, must clear CG and wait for CG_ACK=0. + * @note This feature is only available in FC4150F2M + * + * @param pAdc the base address of the ADC instance + * @param eDivider the ADC clock divider to set + */ +LOCAL_INLINE void ADC_HWA_SetClockDivider(ADC_Type *const pAdc, ADC_ClockDivideType eDivider) +{ + pAdc->CFG2 = (pAdc->CFG2 & ~ADC_CFG2_DIV_MASK) | ADC_CFG2_DIV(eDivider); +} + +/** + * @brief Get the ADC start up count + * + * @param pAdc the base address of the ADC instance + * @return uint8_t the start count of the ADC instance + */ +LOCAL_INLINE uint8_t ADC_HWA_GetStartupCnt(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CFG2 & ADC_CFG2_STCNT_MASK) >> ADC_CFG2_STCNT_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set the ADC start up count + * + * @param pAdc the base address of the ADC instance + * @param u8StartupCnt the start count of the ADC instance + */ +LOCAL_INLINE void ADC_HWA_SetStartupCnt(ADC_Type *const pAdc, uint8_t u8StartupCnt) +{ + pAdc->CFG2 = (pAdc->CFG2 & ~ADC_CFG2_STCNT_MASK) | ADC_CFG2_STCNT(u8StartupCnt); +} + +/** + * @brief Get the ADC_CFG2 config + * + * @param pAdc the base address of the ADC instance + * @return uint32_t the ADC_CFG2 config + */ +LOCAL_INLINE uint32_t ADC_HWA_GetConfig2(const ADC_Type *const pAdc) +{ + return pAdc->CFG2; +} + +/** + * @brief Set the ADC_CFG2 config + * + * @param pAdc the base address of the ADC instance + * @param u32Config the ADC_CFG2 config + */ +LOCAL_INLINE void ADC_HWA_SetConfig2(ADC_Type *const pAdc, uint32_t u32Config) +{ + pAdc->CFG2 = u32Config; +} + +/** + * @brief Set the ADC_CAL config + * + * @param pAdc the base address of the ADC instance + * @param u32Cal the ADC_CAL config + */ +LOCAL_INLINE void ADC_HWA_SetCal(ADC_Type *const pAdc, uint32_t u32Cal) +{ + pAdc->CAL = u32Cal; +} + +/** + * @brief Get the sample time of the ADC instance + * + * @param pAdc the base address of the ADC instance + * @param u8Selection the sample time index, range 0~3 + * @return uint8_t the sample time of the selected index + */ +LOCAL_INLINE uint8_t ADC_HWA_GetSampleTime(ADC_Type *const pAdc, uint8_t u8Selection) +{ + uint32_t ret; + ret = (pAdc->SMPR & (ADC_SMPR_SMP_OPT0_MASK << (8U * u8Selection))) >> (8U * u8Selection); + return (uint8_t)ret; +} + +/** + * @brief Set the sample time of the ADC instance + * + * @param pAdc the base address of the ADC instance + * @param u8Selection the sample time index, range 0~3 + * @param u8SampleTime the sample time of the selected index + */ +LOCAL_INLINE void ADC_HWA_SetSampleTime(ADC_Type *const pAdc, uint8_t u8Selection, uint8_t u8SampleTime) +{ + DEV_ASSERT(u8Selection < ADC_SAMPLE_TIME_OPTION_CNT); + pAdc->SMPR = (pAdc->SMPR & ~(ADC_SMPR_SMP_OPT0_MASK << (8U * u8Selection))) | + (ADC_SMPR_SMP_OPT0(u8SampleTime) << (8U * u8Selection)); +} + +/** + * @brief Set the ADC hardware compare channel + * + * @param pAdc the base address of the ADC instance + * @param eChannelType whether the hardware compare enabled on single channel or all channels + * @param u8ChannalNum if hardware compare is enabled on single channel, this specifies the channel number + */ +LOCAL_INLINE void ADC_HWA_SetHwCompareChannel(ADC_Type *const pAdc, ADC_CmpChannelType eChannelType, + uint8_t u8ChannalNum) +{ + pAdc->CMP_CTRL = (pAdc->CMP_CTRL & (~ADC_CMP_CTRL_ACMPSGL_MASK) & (~ADC_CMP_CTRL_ACMPCH_MASK)) | + ADC_CMP_CTRL_ACMPSGL(eChannelType) | ADC_CMP_CTRL_ACMPCH(u8ChannalNum); +} + +/** + * @brief Get whether hardware compare is enabled + * + * @param pAdc the base address of the ADC instance + * @return true hardware compare is enabled + * @return false hardware compare is disabled + */ +LOCAL_INLINE bool ADC_HWA_GetHwCompareEnableFlag(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = (pAdc->CMP_CTRL & ADC_CMP_CTRL_ACMPEN_MASK) >> ADC_CMP_CTRL_ACMPEN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set to enable or disable the hardware compare + * + * @param pAdc the base address of the ADC instance + * @param bEnable whether the ADC hardware compare is enabled + */ +LOCAL_INLINE void ADC_HWA_SetHwCompareEnableFlag(ADC_Type *const pAdc, bool bEnable) +{ + pAdc->CMP_CTRL = (pAdc->CMP_CTRL & ~ADC_CMP_CTRL_ACMPEN_MASK) | ADC_CMP_CTRL_ACMPEN(bEnable); +} + +/** + * @brief Set the ADC hardware compare threshold + * + * @param pAdc the base address of the ADC instance + * @param u16LowThres the lower threshold + * @param u16HighThres the higher threshold + */ +LOCAL_INLINE void ADC_HWA_SetHwCompareThreshold(ADC_Type *const pAdc, uint16_t u16LowThres, uint16_t u16HighThres) +{ + pAdc->CMP_TR = ADC_CMP_TR_LT(u16LowThres) | ADC_CMP_TR_HT(u16HighThres); +} + +/** + * @brief Get the end of sequence group flag + * + * @param pAdc the base address of the ADC instance + * @param u8SeqGroupIndex the index of the sequence group + * @param bool the sequence group interrupt flag + */ +LOCAL_INLINE bool ADC_HWA_GetEndOfSequenceGroupInterruptFlag(ADC_Type *const pAdc, const uint8_t u8SeqGroupIndex) +{ + uint32_t u32TmpVal = (pAdc->SGCSR[u8SeqGroupIndex] & ADC_SGCSR_EOSG_MASK) >> ADC_SGCSR_EOSG_SHIFT; + return u32TmpVal ? true : false; +} + +/** + * @brief Clear the end of sequence group flag + * + * @param pAdc the base address of the ADC instance + * @param u8SeqGroupIndex the index of the sequence group + */ +LOCAL_INLINE void ADC_HWA_ClearEndOfSequenceGroupInterruptFlag(ADC_Type *const pAdc, const uint8_t u8SeqGroupIndex) +{ + uint32_t u32TmpVal = pAdc->SGCSR[u8SeqGroupIndex]; + pAdc->SGCSR[u8SeqGroupIndex] = (u32TmpVal & ~ADC_SGCSR_EOSG_MASK) | ADC_SGCSR_EOSG(1U); +} + +/** + * @brief Set the sequence group end of sequence interrupt enable + * + * @param pAdc the base address of the ADC instance + * @param u8SeqGroupIndex the index of the sequence group + * @param bEnable the sequence group interrupt enable or disable + */ +LOCAL_INLINE void ADC_HWA_SetEndOfSequenceGroupInterruptEnable(ADC_Type *const pAdc, const uint8_t u8SeqGroupIndex, const bool bEnable) +{ + uint32_t u32TmpVal = pAdc->SGCSR[u8SeqGroupIndex]; + pAdc->SGCSR[u8SeqGroupIndex] = (u32TmpVal & ~ADC_SGCSR_EOSGIE_MASK) | ADC_SGCSR_EOSGIE(bEnable); +} + +/** + * @brief Get the sequence group start point + * + * @param pAdc the base address of the ADC instance + * @param u8SeqGroupIndex the index of the sequence group + */ +LOCAL_INLINE uint32_t ADC_HWA_GetSeqGroupStartPoint(ADC_Type *const pAdc, const uint8_t u8SeqGroupIndex) +{ + return (pAdc->SGCSR[u8SeqGroupIndex] & ~ADC_SGCSR_SG_START_MASK) >> ADC_SGCSR_SG_START_SHIFT; +} + +/** + * @brief Get the sequence group end point + * + * @param pAdc the base address of the ADC instance + * @param u8SeqGroupIndex the index of the sequence group + */ +LOCAL_INLINE uint32_t ADC_HWA_GetSeqGroupEndPoint(ADC_Type *const pAdc, const uint8_t u8SeqGroupIndex) +{ + return (pAdc->SGCSR[u8SeqGroupIndex] & ~ADC_SGCSR_SG_END_MASK) >> ADC_SGCSR_SG_END_SHIFT; +} + +/** + * @brief Set the sequence group start point & end point + * + * @param pAdc the base address of the ADC instance + * @param u8SeqGroupIndex the index of the sequence group + * @param u8Start the sequence group start point + * @param u8End the sequence group end point + */ +LOCAL_INLINE void ADC_HWA_SetSeqGroupStartEndPoint(ADC_Type *const pAdc, const uint8_t u8SeqGroupIndex, const uint8_t u8Start, const uint8_t u8End) +{ + uint32_t u32TmpVal = pAdc->SGCSR[u8SeqGroupIndex]; + u32TmpVal = (u32TmpVal & ~ADC_SGCSR_SG_END_MASK) | ADC_SGCSR_SG_END(u8End); + u32TmpVal = (u32TmpVal & ~ADC_SGCSR_SG_START_MASK) | ADC_SGCSR_SG_START(u8Start); + pAdc->SGCSR[u8SeqGroupIndex] = u32TmpVal; +} + +/** + * @brief Get the conversion result FIFO data of the ADC instance + * + * @note only reslut data of ADC single mode and continuous mode will be stored + * in FIFO register. + * + * @param pAdc the base address of the ADC instance + * @return uint32_t the ADC conversion result + */ +LOCAL_INLINE uint32_t ADC_HWA_GetFIFOData(const ADC_Type *const pAdc) +{ + uint32_t u32TmpVal = pAdc->FIFO_DATA; + u32TmpVal = (u32TmpVal & ADC_FIFO_DATA_FIFO_DATA_MASK) >> ADC_FIFO_DATA_FIFO_DATA_SHIFT; + return (uint32_t)u32TmpVal; +} + +/** + * @brief Get the differential mode state of the ADC channel + * + * @param pAdc the base address of the ADC instance + * @param u8ChnIdx the index of the channel + * @return bool the state of diff mode for ADC channel + */ +LOCAL_INLINE bool ADC_HWA_GetChannelDiff(const ADC_Type *const pAdc, const uint8_t u8ChnIdx) +{ + uint32_t u32TmpVal = (pAdc->SC[u8ChnIdx] & ADC_SC_DIFF_MASK) >> ADC_SC_DIFF_SHIFT; + return u32TmpVal ? true : false; +} + +/** + * @brief Set the differential mode state of the ADC channel + * + * @param pAdc the base address of the ADC instance + * @param u8ChnIdx the index of the channel + * @param bEnable the state of diff mode for ADC channel + */ +LOCAL_INLINE void ADC_HWA_SetChannelDiff(ADC_Type *const pAdc, const uint8_t u8ChnIdx, const bool bEnable) +{ + pAdc->SC[u8ChnIdx] = (pAdc->SC[u8ChnIdx] & ~ADC_SC_DIFF_MASK) | ADC_SC_DIFF(bEnable); +} + +/** + * @brief Get the sample time index of the ADC channel + * + * @param pAdc the base address of the ADC instance + * @param u8ChnIdx the index of the channel + * @return uint8_t the sample time index of the ADC channel + */ +LOCAL_INLINE uint8_t ADC_HWA_GetChannelSampleTimeIndex(const ADC_Type *const pAdc, const uint8_t u8ChnIdx) +{ + uint32_t u32TmpVal = (pAdc->SC[u8ChnIdx] & ADC_SC_SMPSEL_MASK) >> ADC_SC_SMPSEL_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set the sample time index of the ADC channel + * + * @param pAdc the base address of the ADC instance + * @param u8ChnIdx the index of the channel + * @param u8SmpSel the sample time index of the ADC channel + */ +LOCAL_INLINE void ADC_HWA_SetChannelSampleTimeIndex(ADC_Type *const pAdc, const uint8_t u8ChnIdx, uint8_t u8SmpSel) +{ + pAdc->SC[u8ChnIdx] = (pAdc->SC[u8ChnIdx] & ~ADC_SC_SMPSEL_MASK) | ADC_SC_SMPSEL(u8SmpSel); +} + +/** + * @brief Get the channel conversion complete status of the ADC instance + * + * @note this function is used only in ADC discontinuous mode to get the channel complete + * status + * + * @param pAdc the base address of the ADC instance + * @param u8ChnIdx the index of the channel + * @return true the ADC conversion on the selected channel is completed + * @return false the ADC conversion on the selected channel is not completed + */ +LOCAL_INLINE bool ADC_HWA_GetChannelConvertComplete(const ADC_Type *const pAdc, const uint8_t u8ChnIdx) +{ + uint32_t u32TmpVal = pAdc->SC[u8ChnIdx]; + u32TmpVal = (u32TmpVal & ADC_SC_COCO_MASK) >> ADC_SC_COCO_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Check whether interrupt is enabled on the selected ADC channel + * + * @note this function is used only in ADC discontinuous mode to get the channel interrupt + * settings + * + * @param pAdc the base address of the ADC instance + * @param u8ChnIdx the index of the channel + * @return true interrupt is enabled on the selected channel + * @return false interrupt is disabled on the selected channel + */ +LOCAL_INLINE bool ADC_HWA_GetChannelInterruptEnable(const ADC_Type *const pAdc, const uint8_t u8ChnIdx) +{ + uint32_t u32TmpVal = pAdc->SC[u8ChnIdx]; + u32TmpVal = (u32TmpVal & ADC_SC_AIEN_MASK) >> ADC_SC_AIEN_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set to enable or disable interrupt on the selected ADC channel + * + * @note this function is used only in ADC discontinuous mode to get the channel interrupt + * settings + * + * @param pAdc the base address of the ADC instance + * @param u8ChnIdx the index of the channel + * @param bEnable whether to enable interrupt on the selected ADC channel + */ +LOCAL_INLINE void ADC_HWA_SetChannelInterruptEnable(ADC_Type *const pAdc, const uint8_t u8ChnIdx, bool bEnable) +{ + pAdc->SC[u8ChnIdx] = (pAdc->SC[u8ChnIdx] & ~ADC_SC_AIEN_MASK) | ADC_SC_AIEN(bEnable); +} + +/** + * @brief Get the input channel of the selected ADC channel + * + * @param pAdc the base address of the ADC instance + * @param u8ChnIdx the index of the channel + * @return uint8_t the hardware input channel + */ +LOCAL_INLINE uint8_t ADC_HWA_GetChannelInput(const ADC_Type *const pAdc, const uint8_t u8ChnIdx) +{ + uint32_t u32TmpVal = (pAdc->SC[u8ChnIdx] & ADC_SC_CHS_MASK) >> ADC_SC_CHS_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set the input channel to the selected ADC channel + * + * @param pAdc the base address of the ADC instance + * @param u8ChnIdx the index of the channel + * @param u8InputChann the hardware input channel + */ +LOCAL_INLINE void ADC_HWA_SetChannelInput(ADC_Type *const pAdc, const uint8_t u8ChnIdx, uint8_t u8InputChann) +{ + pAdc->SC[u8ChnIdx] = (pAdc->SC[u8ChnIdx] & ~ADC_SC_CHS_MASK) | ADC_SC_CHS(u8InputChann); +} + +/** + * @brief Get the conversion result data of the ADC instance + * + * @note only result data of ADC discontinuous mode will be stored in RESULTn register. + * + * @param pAdc the base address of the ADC instance + * @param u8ChnIdx the index of the ADC channel + * @return uint32_t the ADC conversion result + */ +LOCAL_INLINE uint32_t ADC_HWA_GetChannelData(const ADC_Type *const pAdc, const uint8_t u8ChnIdx) +{ + uint32_t u32TmpVal = pAdc->RESULT[u8ChnIdx]; + u32TmpVal = (u32TmpVal & ADC_RESULT_RESULT_MASK) >> ADC_RESULT_RESULT_SHIFT; + + return (uint32_t)u32TmpVal; +} + +/** @}*/ + +#endif /* _HWA_ADC_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_aontimer.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_aontimer.h new file mode 100644 index 0000000..c9fd40d --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_aontimer.h @@ -0,0 +1,299 @@ +/** + * @file HwA_aontimer.h + * @author Flagchip + * @brief FC7xxx aontimer hardware access layer + * @version 0.1.0 + * @date 2024-01-10 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-10 Flagchip076 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef HWA_INCLUDE_HWA_AONTIMER_H_ +#define HWA_INCLUDE_HWA_AONTIMER_H_ + +#include "device_header.h" + +/** + * @addtogroup HwA_AONTIMER + * @{ + * + */ + +/********* Local typedef ************/ +/** + * @brief The clock source of the pulse mode + * + */ +typedef enum +{ + + AONTIMER_CLK0_PIN = 0, /*!< select the Aontimer_clk0 pin as pulse sourse*/ + AONTIMER_CLK1_PIN, /*!< select the Aontimer_clk1 pin as pulse sourse*/ + AONTIMER_CLK2_PIN, /*!< select the Aontimer_clk2 pin as pulse sourse*/ + AONTIMER_TRGSEL_OUTPUT, /*!< select the tresel as pulse sourse*/ + +} AONTIMER_PulseClkSrcType; + +/** + * @brief Aontimer clock source, please refer to Reference Manual chapter8.Aontimer for details. + * + * */ +typedef enum +{ + AONTIMER_SIRC_1MHZ = 0U, /*!< AONTIMER SIRC 1mhz clock */ + AONTIMER_RTC_CLK = 2U, /*!< AONTIMER RTC clock */ + AONTIMER_IRC_CLK = 3U /*!< AONTIMER internal clock, which comes from PCC */ +} AONTIMER_ClkSrcType; + +/** + * @brief The polarity of pulse mode + * + * */ +typedef enum +{ + AONTIMER_PulsePolarityType_HIGH = 0, /*!< select the high polarity */ + AONTIMER_PulsePolarityType_LOW /*!< select the low polarity */ +} AONTIMER_PulsePolarityType; + +/********* Local inline function ************/ +/** + * @brief Configure AONTIMER module + * + * @param u32RegValue CSR register value + */ +LOCAL_INLINE void AONTIMER_HWA_ConfigModule(uint32_t u32RegValue) +{ + AONTIMER->CSR = u32RegValue; +} + +/** + * @brief Configure AONTIMER module prescale + * + * @param u32RegValue PSR register value + */ +LOCAL_INLINE void AONTIMER_HWA_ConfigModulePrescale(uint32_t u32RegValue) +{ + AONTIMER->PSR = u32RegValue; +} + +/** + * @brief Set AONTIMER compare value + * + * @param u32RegValue CMR register value + */ +LOCAL_INLINE void AONTIMER_HWA_SetModuleCompareValue(uint32_t u32RegValue) +{ + AONTIMER->CMR = u32RegValue; +} + +/** + * @brief Set AONTIMER current counter value + * + * @param u32RegValue CNR register value + */ +LOCAL_INLINE void AONTIMER_HWA_SetModuleCounterValue(uint32_t u32RegValue) +{ + AONTIMER->CNR = u32RegValue; +} + +/** + * @brief Set AONTIMER module running on debug mode + * + */ +LOCAL_INLINE void AONTIMER_HWA_SetModuleRunOnDebug(void) +{ + AONTIMER->CSR |= (uint32_t)AONTIMER_CSR_DBGEN_MASK; +} + +/** + * @brief Enable AONTIMER module interrupt + * + */ +LOCAL_INLINE void AONTIMER_HWA_EnableModuleInterrupt(void) +{ + AONTIMER->CSR |= (uint32_t)AONTIMER_CSR_TIE_MASK; +} + +/** + * @brief Select AONTIMER module external clock source when timer configured to pulse mode + * + * @param eClk Input counter clock source + */ +LOCAL_INLINE void AONTIMER_HWA_SelectClkSrcOnPulseMode(AONTIMER_PulseClkSrcType eClk) +{ + uint32_t u32RegValue = AONTIMER->CSR; + AONTIMER->CSR |= (u32RegValue & ~(uint32_t)AONTIMER_CSR_TPS_MASK) | AONTIMER_CSR_TPS(eClk); +} + +/** + * @brief Clear AONTIMER interrupt flags + * + */ +LOCAL_INLINE void AONTIMER_HWA_ClearInterruptFlag(void) +{ + AONTIMER->CSR |= (uint32_t)AONTIMER_CSR_TCF_MASK; +} + +/** + * @brief Set AONTIMER module polarity. Pulse counter input source is active-low, and the CNR increments on falling-edge. + * + */ +LOCAL_INLINE void AONTIMER_HWA_SetModulePolarity(void) +{ + AONTIMER->CSR |= (uint32_t)AONTIMER_CSR_TPP_MASK; +} + +/** + * @brief Configure AONTIMER module polarity. If ePol is 0:Pulse counter input source is active-high, and the CNR increments on rising-edge. + * If ePol is 1:Pulse counter input source is active-low, and the CNR increments on falling-edge. + * + * @param ePol Polarity enumeration + */ +LOCAL_INLINE void AONTIMER_HWA_ConfigModulePolarity(AONTIMER_PulsePolarityType ePol) +{ + AONTIMER->CSR |= AONTIMER_CSR_TPP(ePol); +} + +/** + * @brief Enable AONTIMER module pulse mode + * + */ +LOCAL_INLINE void AONTIMER_HWA_EnablePulseMode(void) +{ + AONTIMER->CSR |= (uint32_t)AONTIMER_CSR_TMS_MASK; +} + +/** + * @brief Enable AONTIMER timer + * + */ +LOCAL_INLINE void AONTIMER_HWA_EnableTimer(void) +{ + AONTIMER->CSR |= (uint32_t)AONTIMER_CSR_TEN_MASK; +} + +/** + * @brief Set AONTIMER prescale + * + * @param u8PrescalerValue Prescaler value,the range of the input value is :0~15, and the range of prescaler is :2^1 ~ 2^16. + */ +LOCAL_INLINE void AONTIMER_HWA_SetPrescale(uint8_t u8PrescalerValue) +{ + uint32_t u32RegValue = AONTIMER->PSR; + AONTIMER->PSR = ((u32RegValue & ~(uint32_t)AONTIMER_PSR_PRESCALE_MASK) | AONTIMER_PSR_PRESCALE(u8PrescalerValue)); +} + +/** + * @brief If enable bypass mode, the timer will bypass the prescaler in timer counter mode or glitch filter in pulse mode + * + */ +LOCAL_INLINE void AONTIMER_HWA_EnableBypassMode(void) +{ + AONTIMER->PSR |= (uint32_t)AONTIMER_PSR_PBYP_MASK; +} + +/** + * @brief Select AONTIMER mdoule clock source + * + * @param eClk Aontimer clock source + */ +LOCAL_INLINE void AONTIMER_HWA_SelectModuleClkSrc(AONTIMER_ClkSrcType eClk) +{ + uint32_t u32RegValue = AONTIMER->PSR; + AONTIMER->PSR = ((u32RegValue & ~(uint32_t)AONTIMER_PSR_PCS_MASK) | AONTIMER_PSR_PCS(eClk)); +} + +/** + * @brief Set AONTIMER module stop on debug mode + * + */ +LOCAL_INLINE void AONTIMER_HWA_SetModuleStopOnDebug(void) +{ + AONTIMER->CSR &= ~(uint32_t)AONTIMER_CSR_DBGEN_MASK; +} + + +/** + * @brief Disable AONTIMER module interrupt + * + */ +LOCAL_INLINE void AONTIMER_HWA_DisableModuleInterrupt(void) +{ + AONTIMER->CSR &= ~(uint32_t)AONTIMER_CSR_TIE_MASK; +} + +/** + * @brief Clear AONTIMER module mode + * + */ +LOCAL_INLINE void AONTIMER_HWA_ClearModuleMode(void) +{ + AONTIMER->CSR &= ~(uint32_t)AONTIMER_CSR_TPS_MASK; +} + +/** + * @brief Clear AONTIMER module polarity. Pulse counter input source is active-high, and the CNR increments on rising-edge. + * + */ +LOCAL_INLINE void AONTIMER_HWA_ClearModulePolarity(void) +{ + AONTIMER->CSR &= ~(uint32_t)AONTIMER_CSR_TPP_MASK; +} + +/** + * @brief Disable AONTIEMR module pulse mode + * + */ +LOCAL_INLINE void AONTIMER_HWA_DisablePulseMode(void) +{ + AONTIMER->CSR &= ~(uint32_t)AONTIMER_CSR_TMS_MASK; +} + +/** + * @brief Disable AONTIMER module timer + * + */ +LOCAL_INLINE void AONTIMER_HWA_DisableTimer(void) +{ + AONTIMER->CSR &= ~(uint32_t)AONTIMER_CSR_TEN_MASK; +} + +/** + * @brief Clear AONTIMER module prescaler + * + */ +LOCAL_INLINE void AONTIMER_HWA_ClearPrescale(void) +{ + AONTIMER->PSR &= ~(uint32_t)AONTIMER_PSR_PRESCALE_MASK; +} + +/** + * @brief If disable bypass mode, the timer will enable the prescaler in timer counter mode or glitch filter in pulse mode + * + */ +LOCAL_INLINE void AONTIMER_HWA_DisableBypassMode(void) +{ + AONTIMER->PSR &= ~(uint32_t)AONTIMER_PSR_PBYP_MASK; +} + +/** + * @brief Clear AONTIMER module clock source + * + */ +LOCAL_INLINE void AONTIMER_HWA_ClearModuleClkSrc(void) +{ + AONTIMER->PSR &= ~(uint32_t)AONTIMER_PSR_PCS_MASK; +} + +/** @}*/ /* HwA_AONTIMER */ + +#endif /* HWA_INCLUDE_HWA_AONTIMER_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_cm7.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_cm7.h new file mode 100644 index 0000000..694fbcc --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_cm7.h @@ -0,0 +1,39 @@ +/** + * @file HwA_cm7.h + * @author Flagchip + * @brief FC7xxx cortex m4 hardware access layer + * @version 0.1.0 + * @date 2022-11-21 + * + * @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. + * + * @details + */ + +#ifndef _HWA_CM7_H_ +#define _HWA_CM7_H_ + +#include "device_header.h" + +/** + * @brief Enable deepsleep mode + * + */ +LOCAL_INLINE void CM7_HWA_EnableDeepSleep(void) +{ + SCB->SCR |= (uint32_t)SCB_SCR_SLEEPDEEP_Msk; +} + +/** + * @brief Disable deepsleep mode + * + */ +LOCAL_INLINE void CM7_HWA_DisableDeepSleep(void) +{ + SCB->SCR &= ~(uint32_t)SCB_SCR_SLEEPDEEP_Msk; +} + + + + +#endif /* #ifndef _HWA_CM7_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_cmp.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_cmp.h new file mode 100644 index 0000000..ebdd75b --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_cmp.h @@ -0,0 +1,947 @@ +/** + * @file HwA_cmp.h + * @author Flagchip0126 + * @brief FC7xxx CMP driver type definition and API + * @version 0.1.0 + * @date 2024-01-15 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-15 Flagchip0126 N/A First version for FC7240 + ******************************************************************************** */ + + +#ifndef _HWA_CMP_H_ +#define _HWA_CMP_H_ + +#include "device_header.h" + +/********* Local typedef ************/ + +/** + * @brief The CMP complete DMA callback function prototype + * + */ + +/** + * @brief The instance index of the CMP mode + */ +typedef enum +{ + CMP_MOD_DISABLE = 0U, /*!< CMP function mode is disable */ + CMP_MOD_CONTINUOUS = 1U, /*!< CMP function mode is continuous */ + CMP_MOD_SAMPLE_NONFILTER_EXTCLK = 2U, /*!< CMP function mode is sampled,non-filtered mode 1*/ + CMP_MOD_SAMPLE_NONFILTER_INTCLK = 3U, /*!< CMP function mode is sampled,non-filtered mode 2*/ + CMP_MOD_SAMPLE_FILTER_EXTCLK = 4U, /*!< CMP function mode is sampled,filtered mode 1*/ + CMP_MOD_SAMPLE_FILTER_INTCLK = 5U, /*!< CMP function mode is sampled,filtered mode 2*/ + CMP_MOD_WINDOW = 6U, /*!< CMP function mode is windowed mode */ + CMP_MOD_WINDOW_RESAMPLE = 7U, /*!< CMP function mode is windowed,re-sampled mode */ + CMP_MOD_WINDOW_FILTER = 8U, /*!< CMP function mode is windowed,filtered mode */ + CMP_MOD_CHANNEL_SCAN = 9U /*!< CMP channel scan mode */ +} CMP_ModSelType; + +/** + * @brief The instance index of the CMP peripheral + */ +typedef enum +{ + CMP_INSTANCE_0 = 0U, /*!< CMP instance 0 is selected */ + CMP_INSTANCE_1 = 1U /*!< CMP instance 1 is selected */ +} CMP_InstanceType; + +/** + * @brief The instance index of the CMP DAC enable select + */ +typedef enum +{ + CMP_DACENABLE_DCR = 0U, /*!< CMP Dac is enabled by DCR[DAC_EN] */ + CMP_DACENABLE_CCR0 = 1U /*!< CMP Dac is enabled by CCR0[EN] */ +} CMP_DacEnableSrcType; + +/** + * @brief The instance index of the CMP output invert + */ +typedef enum +{ + CMP_NON_INVERT = 0U, /*!< CMP output do not Invert*/ + CMP_INVERT = 1U /*!< CMP output Invert */ +} CMP_InvertType; + +/** + * @brief The instance index of the CMP output select + */ +typedef enum +{ + CMP_FILTEROUT = 0U, /*!< CMP filter output */ + CMP_UNFILTEROUT = 1U /*!< CMP Unfilter output */ +} CMP_OutSelectType; + +/** + * @brief The instance index of the CMP window level + */ +typedef enum +{ + CMP_HOLD = 0U, /*!< CMP output hold when window close */ + CMP_USERDEF = 1U /*!< CMP output userdefine when window close */ +} CMP_OutWinLevelType; + +/** + * @brief The instance index of the window output under userdefine CMP window level + */ +typedef enum +{ + CMP_OUTWIN_0 = 0U, /*!< CMP window output is 0 */ + CMP_OUTWIN_1 = 1U /*!< CMP window output is 1 */ +} CMP_OutWinLevel_UserDefType; + + +/** + * @brief The instance index of the CMP Event caused window close + */ +typedef enum +{ + CMP_RISINGEDGE = 0U, /*!< CMP output event RisingEdge causes window close */ + CMP_FALLINGEDGE = 1U, /*!< CMP output event FallingEdge causes window close */ + CMP_BOTHEDGES = 2U, /*!< CMP output event bothEdges causes window close */ +} CMP_EventType; + +/** + * @brief The instance index of the CMP filter count numbers + */ +typedef enum +{ + CMP_FILTERCNT_0 = 0U, /*!< CMP filter is bypassed */ + CMP_FILTERCNT_1 = 1U, /*!< CMP filter is 1 consecutive sample */ + CMP_FILTERCNT_2 = 2U, /*!< CMP filter is 2 consecutive sample */ + CMP_FILTERCNT_3 = 3U, /*!< CMP filter is 3 consecutive sample */ + CMP_FILTERCNT_4 = 4U /*!< CMP filter is 4 consecutive sample */ +} CMP_FilterCntType; + +/** + * @brief The instance index of the CMP hysteresis control + */ +typedef enum +{ + CMP_HYSTCTRL_0 = 0U, /*!< CMP 0 hysteresis internal */ + CMP_HYSTCTRL_1 = 1U, /*!< CMP 1 hysteresis internal */ + CMP_HYSTCTRL_2 = 2U, /*!< CMP 2 hysteresis internal */ + CMP_HYSTCTRL_3 = 3U /*!< CMP 3 hysteresis internal */ +} CMP_HystCtrlType; + +/** + * @brief The fixed CMP port for reference in channel scan mode + */ +typedef enum +{ + CMP_PORTSEL_MUX_POSITIVE = 0U, + CMP_PORTSEL_MUX_NEGATIVE = 1U +} CMP_PortSelType; + +/** + * @brief The source of the CMP input + */ +typedef enum +{ + CMP_INSRCSEL_DAC = 0U, /*!< CMP input source is DAC */ + CMP_INSRCSEL_MUX = 1U /*!< CMP input source is analog 1-8 mux */ +} CMP_INSrcSelType; + +/** + * @brief The instance index of the CMP input mux + */ +typedef enum +{ + CMP_INSEL_MUX_IN0 = 0U, /*!< CMP input mux from IN0(CMP0,CMP1) */ + CMP_INSEL_MUX_IN1 = 1U, /*!< CMP input mux from IN1(CMP0,CMP1) */ + CMP_INSEL_MUX_IN2 = 2U, /*!< CMP input mux from IN2(CMP0,CMP1) */ + CMP_INSEL_MUX_IN3 = 3U, /*!< CMP input mux from IN3(CMP0,CMP1) */ + CMP_INSEL_MUX_IN4 = 4U, /*!< CMP input mux from IN4(CMP0,CMP1) */ + CMP_INSEL_MUX_IN5 = 5U, /*!< CMP input mux from IN5(CMP0,CMP1) */ + CMP_INSEL_MUX_IN6 = 6U, /*!< CMP input mux from IN6(CMP0,CMP1) */ + CMP_INSEL_MUX_IN7 = 7U /*!< CMP input mux from IN7(CMP0,CMP1) */ +} CMP_MuxSelType; + +/** + * @brief The instance index of DAC high voltage reference select + */ +typedef enum +{ + CMP_DACVINREF_H0 = 0U, /*!< CMP DAC high voltage input reference vrefh0 */ + CMP_DACVINREF_H1 = 1U /*!< CMP DAC high voltage input reference vrefh1 */ +} CMP_DacVinRefSelType; + +/** + * @brief The instance index of high power mode select + */ +typedef enum +{ + CMP_LOWSPEEDMOD = 0U, /*!< CMP low speed mode */ + CMP_HIGHSPEEDMOD = 1U /*!< CMP high speed mode */ +} CMP_SpeedModSelType; + +/** + * @brief Defines CMP out status + */ +typedef enum +{ + CMP_OUT_FALLING_EDGE = 0U, /*!< CMP out detect falling edge */ + CMP_OUT_RISING_EDGE = 1U, /*!< CMP out detect rising edge */ + CMP_OUT_NONE = 2U /*!< CMP out detect none */ +} CMP_OutStatus; + +/********* Local inline function ************/ + +/** + * @brief set CMP enable + * + * @param pCmp the CMP instance to use + */ +LOCAL_INLINE void CMP_HWA_Enable(CMP_Type *const pCmp) +{ + uint32_t u32RegVal = pCmp->CCR0; + pCmp->CCR0 = ((u32RegVal & (~(uint32_t)CMP_CCR0_EN_MASK)) | CMP_CCR0_EN(true)); +} + +/** + * @brief set CMP disable + * + * @param pCmp the CMP instance to use + */ +LOCAL_INLINE void CMP_HWA_Disable(CMP_Type *const pCmp) +{ + uint32_t u32RegVal = pCmp->CCR0; + pCmp->CCR0 = ((u32RegVal & (~(uint32_t)CMP_CCR0_EN_MASK)) | CMP_CCR0_EN(false)); +} + +/** + * @brief set CMP DMA enable + * + * @param pCmp the CMP instance to use + */ +LOCAL_INLINE void CMP_HWA_DmaEnable(CMP_Type *const pCmp) +{ + uint32_t u32RegVal = pCmp->CCR1; + pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_DMA_EN_MASK)) | CMP_CCR1_DMA_EN(true)); +} + +/** + * @brief set CMP DMA disable + * + * @param pCmp the CMP instance to use + */ +LOCAL_INLINE void CMP_HWA_DmaDisable(CMP_Type *const pCmp) +{ + uint32_t u32RegVal = pCmp->CCR1; + pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_DMA_EN_MASK)) | CMP_CCR1_DMA_EN(false)); +} + +/** + * @brief set CMP mode + * + * @param pCmp the CMP instance to use + * @param eMod the CMP mode to use + * @param u8FilterPrd the CMP filter period + * @param eFilterCnt the CMP filter sample count + */ +LOCAL_INLINE void CMP_HWA_SetComparatorMod(CMP_Type *const pCmp, CMP_ModSelType eMod, uint8_t u8FilterPrd, CMP_FilterCntType eFilterCnt) +{ + switch (eMod) + { + case CMP_MOD_DISABLE: + { + /* Nothing deal with */ + } + break; + + case CMP_MOD_CONTINUOUS: + { + pCmp->CCR1 |= CMP_CCR1_WIN_EN(false) | + CMP_CCR1_SAMPLE_EN(false); + } + break; + + case CMP_MOD_SAMPLE_NONFILTER_EXTCLK: + { + pCmp->CCR1 |= CMP_CCR1_WIN_EN(false) | + CMP_CCR1_SAMPLE_EN(true) | + CMP_CCR1_FILT_CNT(0x01); + } + break; + + case CMP_MOD_SAMPLE_NONFILTER_INTCLK: + { + pCmp->CCR1 |= CMP_CCR1_WIN_EN(false) | + CMP_CCR1_SAMPLE_EN(false) | + CMP_CCR1_FILT_CNT(0x01) | + CMP_CCR1_FILT_PER(u8FilterPrd); + } + break; + + case CMP_MOD_SAMPLE_FILTER_EXTCLK: + { + pCmp->CCR1 |= CMP_CCR1_WIN_EN(false) | + CMP_CCR1_SAMPLE_EN(true) | + CMP_CCR1_FILT_CNT(u8FilterPrd); + } + break; + + case CMP_MOD_SAMPLE_FILTER_INTCLK: + { + pCmp->CCR1 |= CMP_CCR1_WIN_EN(false) | + CMP_CCR1_SAMPLE_EN(false) | + CMP_CCR1_FILT_CNT(eFilterCnt) | + CMP_CCR1_FILT_PER(u8FilterPrd); + } + break; + + case CMP_MOD_WINDOW: + { + pCmp->CCR1 |= CMP_CCR1_WIN_EN(true) | + CMP_CCR1_SAMPLE_EN(false) | + CMP_CCR1_FILT_CNT(0x00) | + CMP_CCR1_FILT_PER(0x00); + } + break; + + case CMP_MOD_WINDOW_RESAMPLE: + { + pCmp->CCR1 |= CMP_CCR1_WIN_EN(true) | + CMP_CCR1_SAMPLE_EN(false) | + CMP_CCR1_FILT_CNT(0x01) | + CMP_CCR1_FILT_PER(u8FilterPrd); + } + break; + + case CMP_MOD_WINDOW_FILTER: + { + pCmp->CCR1 |= CMP_CCR1_WIN_EN(true) | + CMP_CCR1_SAMPLE_EN(false) | + CMP_CCR1_FILT_CNT(eFilterCnt) | + CMP_CCR1_FILT_PER(u8FilterPrd); + } + break; + + case CMP_MOD_CHANNEL_SCAN: + { + pCmp->CSCR0 |= CMP_CSCR0_CS_EN(true) ; + } + + break; + default: + break; + } +} + +/** + * @brief STOP mode enable + * + * @param pCmp the CMP instance to use + * @param bEnable enable/disable flag + */ +LOCAL_INLINE void CMP_HWA_SetEnStopMod(CMP_Type *const pCmp, bool bEnable) +{ + uint32_t u32RegVal = pCmp->CCR0; + pCmp->CCR0 = ((u32RegVal & (~(uint32_t)CMP_CCR0_STOP_EN_MASK)) | CMP_CCR0_STOP_EN(bEnable)); +} + +/** + * @brief set DAC enable selection + * + * @param pCmp the CMP instance to use + * @param eType Dac enable source + */ +LOCAL_INLINE void CMP_HWA_SetDacEnableSrc(CMP_Type *const pCmp, CMP_DacEnableSrcType eType) +{ + uint32_t u32RegVal = pCmp->CCR0; + pCmp->CCR0 = ((u32RegVal & (~(uint32_t)CMP_CCR0_DACEN_SEL_MASK)) | CMP_CCR0_DACEN_SEL(eType)); +} + +/** + * @brief set CPM output invert + * + * @param pCmp the CMP instance to use + * @param eType CPM output invert type + */ +LOCAL_INLINE void CMP_HWA_SetCmpOutInvert(CMP_Type *const pCmp, CMP_InvertType eType) +{ + uint32_t u32RegVal = pCmp->CCR1; + pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_CMPOUT_INV_MASK)) | CMP_CCR1_CMPOUT_INV(eType)); +} + +/** + * @brief set CPM output filter/unfilter selection + * + * @param pCmp the CMP instance to use + * @param eType CPM output filter/unfilter type + */ +LOCAL_INLINE void CMP_HWA_SetCmpOutSel(CMP_Type *const pCmp, CMP_OutSelectType eType) +{ + uint32_t u32RegVal = pCmp->CCR1; + pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_CMPOUT_SEL_MASK)) | CMP_CCR1_CMPOUT_SEL(eType)); +} + +/** + * @brief set comparator output pin enable + * + * @param pCmp the CMP instance to use + * @param bEnable enable/disable flag + */ +LOCAL_INLINE void CMP_HWA_SetEnCmpOutPack(CMP_Type *const pCmp, bool bEnable) +{ + uint32_t u32RegVal = pCmp->CCR1; + pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_CMPOUT_PEN_MASK)) | CMP_CCR1_CMPOUT_PEN(bEnable)); +} + +/** + * @brief set CMPOUT_WIN level, when window is closed + * + * @param pCmp the CMP instance to use + * @param eType CMPOUT_WIN level type + */ +LOCAL_INLINE void CMP_HWA_SetCmpOutWinLevel(CMP_Type *const pCmp, CMP_OutWinLevelType eType) +{ + uint32_t u32RegVal = pCmp->CCR1; + pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_CMPOUT_WIN_OWEN_MASK)) | CMP_CCR1_CMPOUT_WIN_OWEN(eType)); +} + +/** + * @brief set CMPOUT_WIN level in user-define mode, when window is closed + * + * @param pCmp the CMP instance to use + * @param eType user-define CMPOUT_WIN level type + */ +LOCAL_INLINE void CMP_HWA_SetCmpOutWin(CMP_Type *const pCmp, CMP_OutWinLevel_UserDefType eType) +{ + uint32_t u32RegVal = pCmp->CCR1; + pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_CMPOUT_WIN_OW_MASK)) | CMP_CCR1_CMPOUT_WIN_OW(eType)); +} + +/** + * @brief set invert the WINDOW/SAMPLE signal enable or not + * + * @param pCmp the CMP instance to use + * @param bEnable enable/disable flag + */ +LOCAL_INLINE void CMP_HWA_SetEnWinSampleInvert(CMP_Type *const pCmp, bool bEnable) +{ + uint32_t u32RegVal = pCmp->CCR1; + pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_WIN_INV_MASK)) | CMP_CCR1_WIN_INV(bEnable)); +} + +/** + * @brief WINDOW signal can or not be closed by CMPO event when window mode + * + * @param pCmp the CMP instance to use + * @param bEnable enable/disable flag + */ +LOCAL_INLINE void CMP_HWA_SetEnEventCloseWin(CMP_Type *const pCmp, bool bEnable) +{ + uint32_t u32RegVal = pCmp->CCR1; + pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_WIN_CLS_MASK)) | CMP_CCR1_WIN_CLS(bEnable)); +} + +/** + * @brief set which CMPO event causes window close + * + * @param pCmp the CMP instance to use + * @param eType CMPO event type + */ +LOCAL_INLINE void CMP_HWA_SetEventCloseWin(CMP_Type *const pCmp, CMP_EventType eType) +{ + uint32_t u32RegVal = pCmp->CCR1; + pCmp->CCR1 = ((u32RegVal & (~(uint32_t)CMP_CCR1_EVT_SEL_MASK)) | CMP_CCR1_EVT_SEL(eType)); +} + +/** + * @brief set CMP power mode select + * + * @param pCmp the CMP instance to use + * @param eMod CMP power mode + */ +LOCAL_INLINE void CMP_HWA_SetSpeedMod(CMP_Type *const pCmp, CMP_SpeedModSelType eMod) +{ + uint32_t u32RegVal = pCmp->CCR2; + pCmp->CCR2 = ((u32RegVal & (~(uint32_t)CMP_CCR2_HPMD_MASK)) | CMP_CCR2_HPMD(eMod)); +} + +/** + * @brief set Comparator hard block hysteresis control + * + * @param pCmp the CMP instance to use + * @param eType CMP hysteresis control type + */ +LOCAL_INLINE void CMP_HWA_SetHystCtrl(CMP_Type *const pCmp, CMP_HystCtrlType eType) +{ + uint32_t u32RegVal = pCmp->CCR2; + pCmp->CCR2 = ((u32RegVal & (~(uint32_t)CMP_CCR2_HYSTCTR_MASK)) | CMP_CCR2_HYSTCTR(eType)); +} + +/** + * @brief set Comparator analog confifuration transition bypass + * + * @param pCmp the CMP instance to use + * @param Enable The status for Comparator analog confifuration transition bypass + */ +LOCAL_INLINE void CMP_HWA_SetAnalogConfTransByp(CMP_Type *const pCmp, bool Enable) +{ + uint32_t u32RegVal = pCmp->CCR3; + pCmp->CCR3 = ((u32RegVal & (~(uint32_t)CMP_CCR3_DAC_TRANS_BYP_MASK)) | CMP_CCR3_DAC_TRANS_BYP(Enable)); +} + +/** + * @brief set Comparator hard block hysteresis control + * + * @param pCmp the CMP instance to use + * @param Count Comparator analog confifuration transition bypass count + */ +LOCAL_INLINE void CMP_HWA_SetAnalogConfTransBypCnt(CMP_Type *const pCmp, uint16_t Count) +{ + uint32_t u32RegVal = pCmp->CCR3; + Count = Count & 0x3ff; + pCmp->CCR3 = ((u32RegVal & (~(uint32_t)CMP_CCR3_DAC_RDY_CNT_MASK)) | CMP_CCR3_DAC_RDY_CNT(Count)); +} + +/** + * @brief set which input is selected for the positive mux + * + * @param pCmp the CMP instance to use + * @param eType CMP positive mux type + */ +LOCAL_INLINE void CMP_HWA_SetPSelMux(CMP_Type *const pCmp, CMP_MuxSelType eType) +{ + uint32_t u32RegVal = pCmp->CCR2; + pCmp->CCR2 = ((u32RegVal & (~(uint32_t)CMP_CCR2_PSEL_MASK)) | CMP_CCR2_PSEL(eType)); +} + +/** + * @brief set which input is selected for the negative mux + * + * @param pCmp the CMP instance to use + * @param eType CMP negative mux type + */ +LOCAL_INLINE void CMP_HWA_SetNSelMux(CMP_Type *const pCmp, CMP_MuxSelType eType) +{ + uint32_t u32RegVal = pCmp->CCR2; + pCmp->CCR2 = ((u32RegVal & (~(uint32_t)CMP_CCR2_MSEL_MASK)) | CMP_CCR2_MSEL(eType)); +} + +/** + * @brief set the input to the positive port of the comparator + * + * @param pCmp the CMP instance to use + * @param eType CMP positive input source type(analog mux,dac) + */ +LOCAL_INLINE void CMP_HWA_SetINPSel(CMP_Type *const pCmp, CMP_INSrcSelType eType) +{ + uint32_t u32RegVal = pCmp->CCR2; + pCmp->CCR2 = ((u32RegVal & (~(uint32_t)CMP_CCR2_INPSEL_MASK)) | CMP_CCR2_INPSEL(eType)); +} + +/** + * @brief set the input to the negative port of the comparator + * + * @param pCmp the CMP instance to use + * @param eType CMP negative input source type(analog mux,dac) + */ +LOCAL_INLINE void CMP_HWA_SetINNSel(CMP_Type *const pCmp, CMP_INSrcSelType eType) +{ + uint32_t u32RegVal = pCmp->CCR2; + pCmp->CCR2 = ((u32RegVal & (~(uint32_t)CMP_CCR2_INMSEL_MASK)) | CMP_CCR2_INMSEL(eType)); +} + +/** + * @brief set CMP DAC enable + * + * @param pCmp the CMP instance to use + * @param bEnable enable/disable flag + */ +LOCAL_INLINE void CMP_HWA_SetEnDac(CMP_Type *const pCmp, bool bEnable) +{ + uint32_t u32RegVal = pCmp->DCR; + pCmp->DCR = ((u32RegVal & (~(uint32_t)CMP_DCR_DAC_EN_MASK)) | CMP_DCR_DAC_EN(bEnable)); +} + + +/** + * @brief set DAC reference voltage source + * + * @param pCmp the CMP instance to use + * @param eType CMP reference voltage source type + */ +LOCAL_INLINE void CMP_HWA_SetVinRefSel(CMP_Type *const pCmp, CMP_DacVinRefSelType eType) +{ + uint32_t u32RegVal = pCmp->DCR; + pCmp->DCR = ((u32RegVal & (~(uint32_t)CMP_DCR_VRSEL_MASK)) | CMP_DCR_VRSEL(eType)); +} + +/** + * @brief set CMP Dac output + * + * @param pCmp the CMP instance to use + * @param u8Data the Dac data + * @note output = (VinRef / 256) * (u8Data + 1) + */ +LOCAL_INLINE void CMP_HWA_SetDacData(CMP_Type *const pCmp, uint8_t u8Data) +{ + uint32_t u32RegVal = pCmp->DCR; + pCmp->DCR = ((u32RegVal & (~(uint32_t)CMP_DCR_DAC_DATA_MASK)) | CMP_DCR_DAC_DATA(u8Data)); +} + +/** + * @brief set comparator rising interrupt enable + * + * @param pCmp the CMP instance to use + * @param bEnable enable/disable flag + */ +LOCAL_INLINE void CMP_HWA_SetIntEn_Rising(CMP_Type *const pCmp, bool bEnable) +{ + uint32_t u32RegVal = pCmp->IER; + pCmp->IER = ((u32RegVal & (~(uint32_t)CMP_IER_CFR_IE_MASK)) | CMP_IER_CFR_IE(bEnable)); +} + +/** + * @brief get comparator rising interrupt enable status + * + * @param pCmp the CMP instance to use + * @return comparator rising interrupt status + */ +LOCAL_INLINE bool CMP_HWA_GetIntEn_Rising(CMP_Type *const pCmp) +{ + bool RetStatus = false; + uint32_t u32RegVal = pCmp->IER; + + RetStatus = (bool)((((u32RegVal & CMP_IER_CFR_IE_MASK) >> CMP_IER_CFR_IE_SHIFT) != 0U) ? true : false); + return RetStatus; +} + +/** + * @brief set comparator falling interrupt enable + * + * @param pCmp the CMP instance to use + * @param bEnable enable/disable flag + */ +LOCAL_INLINE void CMP_HWA_SetIntEn_Falling(CMP_Type *const pCmp, bool bEnable) +{ + uint32_t u32RegVal = pCmp->IER; + pCmp->IER = ((u32RegVal & (~(uint32_t)CMP_IER_CFF_IE_MASK)) | CMP_IER_CFF_IE(bEnable)); +} + +/** + * @brief get comparator falling interrupt enable status + * + * @param pCmp the CMP instance to use + * @return comparator falling interrupt status + */ +LOCAL_INLINE bool CMP_HWA_GetIntEn_Falling(CMP_Type *const pCmp) +{ + bool bRetStatus = false; + uint32_t u32RegVal = pCmp->IER; + + bRetStatus = (bool)((((u32RegVal & CMP_IER_CFF_IE_MASK) >> CMP_IER_CFF_IE_SHIFT) != 0U) ? true : false); + return bRetStatus; +} + +/** + * @brief set comparator channel scan interrupt enable + * + * @param pCmp the CMP instance to use + * @param bEnable enable/disable flag + */ +LOCAL_INLINE void CMP_HWA_SetIntEn_ChannelScan(CMP_Type *const pCmp, bool bEnable) +{ + uint32_t u32RegVal = pCmp->IER; + pCmp->IER = ((u32RegVal & (~(uint32_t)CMP_IER_CSF_IE_MASK)) | CMP_IER_CSF_IE(bEnable)); +} + +/** + * @brief get comparator channel scan interrupt enable status + * + * @param pCmp the CMP instance to use + * @return comparator channel scan interrupt status + */ +LOCAL_INLINE bool CMP_HWA_GetIntEn_ChannelScan(CMP_Type *const pCmp) +{ + bool bRetStatus = false; + uint32_t u32RegVal = pCmp->IER; + + bRetStatus = (bool)((((u32RegVal & CMP_IER_CSF_IE_MASK) >> CMP_IER_CSF_IE_SHIFT) != 0U) ? true : false); + return bRetStatus; +} + +/** + * @brief get CMP output rising edge status + * + * @param pCmp the CMP instance to use + * @return CMP rising edge status + */ +LOCAL_INLINE bool CMP_HWA_GetIntFlag_Rising(CMP_Type *const pCmp) +{ + bool bRetStatus = false; + uint32_t u32RegVal = pCmp->CSR; + + bRetStatus = (bool)((((u32RegVal & CMP_CSR_CFR_MASK) >> CMP_CSR_CFR_SHIFT) != 0U) ? true : false); + return bRetStatus; +} + +/** + * @brief get CMP output falling edge status + * + * @param pCmp the CMP instance to use + * @return CMP falling edge status + */ +LOCAL_INLINE bool CMP_HWA_GetIntFlag_Falling(CMP_Type *const pCmp) +{ + bool bRetStatus = false; + uint32_t u32RegVal = pCmp->CSR; + + bRetStatus = (bool)((((u32RegVal & CMP_CSR_CFF_MASK) >> CMP_CSR_CFF_SHIFT) != 0U) ? true : false); + return bRetStatus; +} + +/** + * @brief get CMP output channel scan status + * + * @param pCmp the CMP instance to use + * @return CMP channel scan status + */ +LOCAL_INLINE bool CMP_HWA_GetIntFlag_ChannelScan(CMP_Type *const pCmp) +{ + bool bRetStatus = false; + uint32_t u32RegVal = pCmp->CSR; + + bRetStatus = (bool)((((u32RegVal & CMP_CSR_CSF_MASK) >> CMP_CSR_CSF_SHIFT) != 0U) ? true : false); + return bRetStatus; +} + + +/** + * @brief clear rising interrupt flag + * + * @param pCmp the CMP instance to use + */ +LOCAL_INLINE void CMP_HWA_ClearIntFlag_Rising(CMP_Type *const pCmp) +{ + uint32_t u32RegVal = pCmp->CSR; + pCmp->CSR = ((u32RegVal & (~(uint32_t)CMP_CSR_CFR_MASK)) | CMP_CSR_CFR(true)); +} + +/** + * @brief clear falling interrupt flag + * + * @param pCmp the CMP instance to use + */ +LOCAL_INLINE void CMP_HWA_ClearIntFlag_Falling(CMP_Type *const pCmp) +{ + uint32_t u32RegVal = pCmp->CSR; + pCmp->CSR = ((u32RegVal & (~(uint32_t)CMP_CSR_CFF_MASK)) | CMP_CSR_CFF(true)); +} + +/** + * @brief clear channel scan interrupt flag + * + * @param pCmp the CMP instance to use + */ +LOCAL_INLINE void CMP_HWA_ClearIntFlag_ChannelScan(CMP_Type *const pCmp) +{ + uint32_t u32RegVal = pCmp->CSR; + pCmp->CSR = ((u32RegVal & (~(uint32_t)CMP_CSR_CSF_MASK)) | CMP_CSR_CSF(true)); +} + +/** + * @brief get CMP filtered output + * + * @param pCmp the CMP instance to use + * @return CMP filtered output + */ +LOCAL_INLINE bool CMP_HWA_GetCmpOut(CMP_Type *const pCmp) +{ + bool CmpOut; + uint32_t u32RegVal = pCmp->CSR; + CmpOut = ((u32RegVal & CMP_CSR_CMPOUT_FILTER_MASK) >> CMP_CSR_CMPOUT_FILTER_SHIFT) ? true : false; + return CmpOut; +} + +/** + * @brief set CMP and DAC initialization delay modulus + * + * @param pCmp the CMP instance to use + */ +LOCAL_INLINE void CMP_HWA_SetCSInitModulus(CMP_Type *const pCmp, uint8_t u8Modulus) +{ + uint32_t u32RegVal = pCmp->CSCR0; + pCmp->CSCR0 = ((u32RegVal & (~(uint32_t)CMP_CSCR0_CS_INITMOD_MASK)) | CMP_CSCR0_CS_INITMOD(u8Modulus)); +} + +/** + * @brief set number of clock cycles for sampling + * + * @param pCmp the CMP instance to use + * @param u8Nsam the sampling clocks value + */ +LOCAL_INLINE void CMP_HWA_SetCSNumOfSampleClocks(CMP_Type *const pCmp, uint8_t u8Nsam) +{ + uint32_t u32RegVal = pCmp->CSCR0; + pCmp->CSCR0 = ((u32RegVal & (~(uint32_t)CMP_CSCR0_CS_NSAM_MASK)) | CMP_CSCR0_CS_NSAM(u8Nsam)); +} + +/** + * @brief set CMP channel scan enable + * + * @param pCmp the CMP instance to use + */ +LOCAL_INLINE void CMP_HWA_CSEnable(CMP_Type *const pCmp) +{ + uint32_t u32RegVal = pCmp->CSCR0; + pCmp->CSCR0 = ((u32RegVal & (~(uint32_t)CMP_CSCR0_CS_EN_MASK)) | CMP_CSCR0_CS_EN(true)); +} + +/** + * @brief set CMP channel scan disable + * + * @param pCmp the CMP instance to use + */ +LOCAL_INLINE void CMP_HWA_CSDisable(CMP_Type *const pCmp) +{ + uint32_t u32RegVal = pCmp->CSCR0; + pCmp->CSCR0 = ((u32RegVal & (~(uint32_t)CMP_CSCR0_CS_EN_MASK)) | CMP_CSCR0_CS_EN(false)); +} + +/** + * @brief set channel scan fixed channel + * + * @param pCmp the CMP instance to use + * @param eChannel the fixed channel + */ +LOCAL_INLINE void CMP_HWA_SetCSFixedChannel(CMP_Type *const pCmp, CMP_MuxSelType eChannel) +{ + uint32_t u32RegVal = pCmp->CSCR1; + pCmp->CSCR1 = ((u32RegVal & (~(uint32_t)CMP_CSCR1_FIXCH_MASK)) | CMP_CSCR1_FIXCH(eChannel)); +} + +/** + * @brief set channel scan fixed port + * + * @param pCmp the CMP instance to use + * @param ePort the fixed port + */ +LOCAL_INLINE void CMP_HWA_SetCSFixedPort(CMP_Type *const pCmp, CMP_PortSelType ePort) +{ + uint32_t u32RegVal = pCmp->CSCR1; + pCmp->CSCR1 = ((u32RegVal & (~(uint32_t)CMP_CSCR1_FIXP_MASK)) | CMP_CSCR1_FIXP(ePort)); +} + +/** + * @brief set channel scan channel enabled + * + * @param pCmp the CMP instance to use + * @param eChannel the enabled channel + * @param bEnable enable/disable flag + */ +LOCAL_INLINE void CMP_HWA_SetCSChannelEn(CMP_Type *const pCmp, CMP_MuxSelType eChannel, bool bEnable) +{ + uint32_t u32RegVal = pCmp->CSCR1; + pCmp->CSCR1 = ((u32RegVal & (~(uint32_t)(1 << eChannel))) | (((uint32_t)bEnable) << eChannel)); +} + +/** + * @brief set channel scan channel enabled + * + * @param pCmp the CMP instance to use + * @param eChannel the enabled channel + * @param bPresetstate preset state for channel + */ +LOCAL_INLINE void CMP_HWA_SetCSChannelPresetstate(CMP_Type *const pCmp, CMP_MuxSelType eChannel, bool bPresetstate) +{ + uint32_t u32RegVal = pCmp->CSCSR; + pCmp->CSCSR = ((u32RegVal & (~(uint32_t)(1 << eChannel))) | (((uint32_t)bPresetstate) << eChannel)); +} + +/** + * @brief get channel scan channel current state + * + * @param pCmp the CMP instance to use + * @param eChannel the channel that want to get state + */ +LOCAL_INLINE bool CMP_HWA_GetCSChannelsOut(CMP_Type *const pCmp, CMP_MuxSelType eChannel) +{ + bool OutFlag; + uint32_t u32RegVal = pCmp->CSCSR; + OutFlag = (bool)((u32RegVal & ((uint32_t)(1 << eChannel))) >> eChannel); + + return OutFlag; +} + +/** + * @brief software clear channel scan comparison results + * + * @param pCmp the CMP instance to use + */ +LOCAL_INLINE void CMP_HWA_ClearCSComparisonResults(CMP_Type *const pCmp) +{ + uint32_t u32RegVal = pCmp->CSCSR; + pCmp->CSCSR = ((u32RegVal & (~(uint32_t)CMP_CSCSR_CS_SWCLR_MASK)) | CMP_CSCSR_CS_SWCLR(true)); +} + +/** + * @brief software clear channel scan comparison results + * + * @param pCmp the CMP instance to use + * @param bEnable enable/disable flag + */ +LOCAL_INLINE void CMP_HWA_SetCSComparisonResultsAutoClearEn(CMP_Type *const pCmp, bool bEnable) +{ + uint32_t u32RegVal = pCmp->CSCSR; + pCmp->CSCSR = ((u32RegVal & (~(uint32_t)CMP_CSCSR_CS_ACLR_MASK)) | CMP_CSCSR_CS_ACLR(bEnable)); +} + +/** + * @brief get channel scan comparison reuslt + * + * @param pCmp the CMP instance to use + * @param eChannel the enabled channel + * @return channel comparison result for a given channel + */ +LOCAL_INLINE uint32_t CMP_HWA_GetCSComparisonResult(CMP_Type *const pCmp, CMP_MuxSelType eChannel) +{ + uint32_t u32RegVal = pCmp->CSCSR; + u32RegVal = (u32RegVal & (1 << eChannel)) >> eChannel; + return u32RegVal; +} + +/** + * @brief set channel scan active + * + * @param pCmp the CMP instance to use + * @return status cmp channel whether is active + */ +LOCAL_INLINE bool CMP_HWA_GetCSActive(CMP_Type *const pCmp) +{ + bool status; + uint32_t u32RegVal = pCmp->CSSR; + status = ((u32RegVal & ((uint32_t)CMP_CSSR_CS_ACTIVE_MASK)) >> CMP_CSSR_CS_ACTIVE_SHIFT) ? true : false; + return status; +} + +/** + * @brief get channel scan comparison result changed flag + * + * @param pCmp the CMP instance to use + * @param eChannel the channel to get comparison result changed flag + * @return the comparison result changed flag for a given channel + */ +LOCAL_INLINE bool CMP_HWA_GetCSComparisonResultFlag(CMP_Type *const pCmp, CMP_MuxSelType eChannel) +{ + bool flag; + uint32_t u32RegVal = pCmp->CSSR; + flag = ((u32RegVal & (1 << eChannel)) >> eChannel) ? true : false; + return flag; +} + +#endif /* #ifndef _HWA_CMP_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_cmu.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_cmu.h new file mode 100644 index 0000000..887dc31 --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_cmu.h @@ -0,0 +1,271 @@ +/** + * @file HwA_cmu.h + * @author Flagchip085 + * @brief FC7xxx CMU hardware access layer + * @version 0.1.0 + * @date 2024-01-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240 +******************************************************************************** */ + +#ifndef _HWA_CMU_H_ +#define _HWA_CMU_H_ + +#include "device_header.h" + +/********* Local inline function ************/ +/** + * @brief Set Reference Window value. + * @param pCmu CMU Instance. + * @param u32Value Ref Window value. +*/ +LOCAL_INLINE void CMU_HWA_SetRefWindow(CMU_Type *const pCmu, uint32_t u32Value) +{ + pCmu->REF_WINDOW = CMU_REF_WINDOW_REF_WINDOW(u32Value); +} + +/** + * @brief Get Reference Window value. + * @param pCmu CMU Instance. + * @return Reference Window value. + */ +LOCAL_INLINE uint32_t CMU_HWA_GetRefWindow(const CMU_Type *const pCmu) +{ + return (pCmu->REF_WINDOW & CMU_REF_WINDOW_REF_WINDOW_MASK) >> CMU_REF_WINDOW_REF_WINDOW_SHIFT; +} + +/** +* @brief Set Minimun Counter value + * @param pCmu CMU Instance. + * @param u32Value Min Count value. +*/ +LOCAL_INLINE void CMU_HWA_SetMinCnts(CMU_Type *const pCmu, uint32_t u32Value) +{ + pCmu->MIN = CMU_MIN_MIN(u32Value); +} + +/** + * @brief Get Minimun Counter value. + * @param pCmu CMU Instance. + * @return Min count value. + */ +LOCAL_INLINE uint32_t CMU_HWA_GetMinCnts(const CMU_Type *const pCmu) +{ + return (pCmu->MIN & CMU_MIN_MIN_MASK) >> CMU_MIN_MIN_SHIFT; +} + +/** + * @brief Set Maximun Counter value. + * @param pCmu CMU Instance. + * @param u32Value Max count value. +*/ +LOCAL_INLINE void CMU_HWA_SetMaxCnts(CMU_Type *const pCmu, uint32_t u32Value) +{ + pCmu->MAX = CMU_MAX_MAX(u32Value); +} + +/** + * @brief Get Maximun Counter value. + * @param pCmu CMU Instance. + * @return Max count value. + */ +LOCAL_INLINE uint32_t CMU_HWA_GetMaxCnts(const CMU_Type *const pCmu) +{ + return (pCmu->MAX & CMU_MAX_MAX_MASK) >> CMU_MAX_MAX_SHIFT; +} + +/** + * @brief Get Counter value. + * @param pCmu CMU Instance. + * @return Counter value. + */ +LOCAL_INLINE uint32_t CMU_HWA_GetCount(const CMU_Type *const pCmu) +{ + return (pCmu->MON_CNT & CMU_MON_CNT_MON_CNT_MASK) >> CMU_MON_CNT_MON_CNT_SHIFT; +} + +/** + * @brief Set period window Counter. + * @param pCmu CMU Instance. + * @param u32Value Period value. +*/ +LOCAL_INLINE void CMU_HWA_SetPeriodWindow(CMU_Type *const pCmu, uint32_t u32Value) +{ + pCmu->PERIOD = (pCmu->PERIOD & ~CMU_PERIOD_WINDOW_MASK) | CMU_PERIOD_WINDOW(u32Value); +} + +/** + * @brief Set period enble bit. +* + * @param pCmu CMU Instance. + * @param bEnable Set enable bit. +*/ +LOCAL_INLINE void CMU_HWA_SetPeriodEnable(CMU_Type *const pCmu, bool bEnable) +{ + pCmu->PERIOD = (pCmu->PERIOD & ~((uint32_t)CMU_PERIOD_EN_MASK)) | CMU_PERIOD_EN(bEnable); +} + +/** +* @brief Set control register value. + * + * @param pCmu CMU Instance. + * @param u32Value Control value. +*/ +LOCAL_INLINE void CMU_HWA_SETCTRL(CMU_Type *const pCmu, uint32_t u32Value) +{ + pCmu->CTRL = u32Value; +} + +/** +* @brief return control register value. + * + * @param pCmu CMU Instance. + * @return CMU Control register value +*/ +LOCAL_INLINE uint32_t CMU_HWA_GetCTRL(const CMU_Type *const pCmu) +{ + return pCmu->CTRL; +} + +/** + * @brief return status register value. + * @param pCmu CMU Instance. + * @return Status value. +*/ +LOCAL_INLINE uint32_t CMU_HWA_GetST(const CMU_Type *const pCmu) +{ + return pCmu->ST; +} + +/** + * @brief Clear clock monitor status + * @param pCmu CMU Instance. +*/ +LOCAL_INLINE void CMU_HWA_ClearST(CMU_Type *const pCmu) +{ + pCmu->ST = (uint32_t)(CMU_ST_MIS_MASK | CMU_ST_LOC_MASK); +} + +/** + * @brief Set the Divider for Reference Clock + * @param pCmu CMU Instance. + * @param eDivider The Divider of Reference Clock +*/ +LOCAL_INLINE void CMU_HWA_SetRefClockDiv(CMU_Type *const pCmu, uint8_t eDivider) +{ + pCmu->CTRL = (pCmu->CTRL & ~((uint32_t)CMU_CTRL_REF_DIV_MASK)) | CMU_CTRL_REF_DIV(eDivider); +} + +/** + * @brief Get the Divider for Reference Clock + * @param pCmu CMU Instance. + * @return The Divider of Reference Clock +*/ +LOCAL_INLINE uint8_t CMU_HWA_GetRefClockDiv(const CMU_Type *const pCmu) +{ + uint32_t u32Temp = (pCmu->CTRL & (uint32_t)CMU_CTRL_REF_DIV_MASK) >> CMU_CTRL_REF_DIV_SHIFT; + return (uint8_t)u32Temp; +} + +/** + * @brief Enable interrupt when LOC or MIS asserted + * @param pCmu CMU Instance. + * @param bEnable Enable or disable CMU interrupt +*/ +LOCAL_INLINE void CMU_HWA_IrqEnable(CMU_Type *const pCmu, bool bEnable) +{ + pCmu->CTRL = (pCmu->CTRL & (~((uint32_t)CMU_CTRL_IRQ_EN_MASK))) | CMU_CTRL_IRQ_EN(bEnable); +} + +/** + * @brief Get CMU interrupt enable flag + * @param pCmu CMU Instance. + * @return 1 : CMU interrupt enabled + * 0 : CMU interrupt disabled +*/ +LOCAL_INLINE uint8_t CMU_HWA_GetIrqEnableFlag(const CMU_Type *const pCmu) +{ + uint32_t u32Temp = (pCmu->CTRL & (uint32_t)CMU_CTRL_IRQ_EN_MASK) >> CMU_CTRL_IRQ_EN_SHIFT; + return (uint8_t)u32Temp; +} + +/** + * @brief Enable Standby mode + * @param pCmu CMU Instance. + * @param bEnable Enable mode +*/ +LOCAL_INLINE void CMU_HWA_StanbyModeEnable(CMU_Type *const pCmu, bool bEnable) +{ + pCmu->CTRL = (pCmu->CTRL & ~((uint32_t)CMU_CTRL_LP_EN_MASK)) | CMU_CTRL_LP_EN(bEnable); +} + +/** + * @brief Enable Stop mode + * @param pCmu CMU Instance. + * @param bEnable Enable mode +*/ +LOCAL_INLINE void CMU_HWA_StopModeEnable(CMU_Type *const pCmu, bool bEnable) +{ + pCmu->CTRL = (pCmu->CTRL & ~((uint32_t)CMU_CTRL_STOP_EN_MASK)) | CMU_CTRL_STOP_EN(bEnable); +} + +/** + * @brief Enable hardware restart CMU after exiting from the low-power mode + * @param pCmu CMU Instance. + * @param bEnable Enable mode +*/ +LOCAL_INLINE void CMU_HWA_LPRestartEnable(CMU_Type *const pCmu, bool bEnable) +{ + pCmu->CTRL = (pCmu->CTRL & ~((uint32_t)CMU_CTRL_RESTART_EN_MASK)) | CMU_CTRL_RESTART_EN(bEnable); +} + +/** + * @brief Software Reset the CMU + * @param pCmu CMU Instance. +*/ +LOCAL_INLINE void CMU_HWA_SoftwareReset(CMU_Type *const pCmu) +{ + pCmu->CTRL |= CMU_CTRL_SW_RST_MASK; +} + +/** + * @brief Enable the CMU + * @param pCmu CMU Instance. +*/ +LOCAL_INLINE void CMU_HWA_Enable(CMU_Type *const pCmu) +{ + pCmu->CTRL |= CMU_CTRL_ENABLE_MASK; +} + +/** + * @brief Disable the CMU + * @param pCmu CMU Instance. +*/ +LOCAL_INLINE void CMU_HWA_Disable(CMU_Type *const pCmu) +{ + pCmu->CTRL &= ~(CMU_CTRL_ENABLE_MASK | CMU_CTRL_IRQ_EN_MASK); + +} + +/** + * @brief Get the CMU enabled status + * @param pCmu CMU Instance. + * @return 1 : CMU is enabled + * 0 : CMU is disabled +*/ +LOCAL_INLINE uint8_t CMU_HWA_GetEnableStatus(const CMU_Type *const pCmu) +{ + uint32_t u32Temp = (pCmu->CTRL & (uint32_t)CMU_CTRL_ENABLE_MASK) >> CMU_CTRL_ENABLE_SHIFT; + return (uint8_t)u32Temp; +} + +#endif /* #ifndef _HWA_CMU_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_cordic.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_cordic.h new file mode 100644 index 0000000..276a7b3 --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_cordic.h @@ -0,0 +1,134 @@ +/** + * @file HwA_cordic.h + * @author Flagchip + * @brief Hardware access layer for Cordic + * @version 0.1.0 + * @date 2024-01-11 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-11 Flagchip054 N/A First version for FC7240 + ******************************************************************************** */ +#ifndef _HWA_CORDIC_H_ +#define _HWA_CORDIC_H_ +#include "device_header.h" + +typedef enum +{ + CORDIC_Iteration_8 = 0, + CORDIC_Iteration_16, + CORDIC_Iteration_24 +}CORDIC_IterationType; + +typedef enum +{ + CORDIC_Trigonometric = 0, + CORDIC_Hyperbolic, + CORDIC_Linear +}CORDIC_SystemType; + +typedef enum +{ + CORDIC_Rotate = 0, + CORDIC_Vector +}CORDIC_ModeType; + + +#define CORDIC_CTR_VAL(s,a,b,c,d) (CORDIC_CTRL_SCALE(s) | CORDIC_CTRL_IE(a) | CORDIC_CTRL_ITER(b) | CORDIC_CTRL_OS(c) | CORDIC_CTRL_MODE(d)) +/** + * @brief Set Cordic module Ctrl register + * + * @param u32Value Ctrl register value + */ +LOCAL_INLINE void Cordic_HWA_SetCtrl(uint32_t u32Value) +{ + CORDIC->CTRL = u32Value; +} + +/** + * @brief Read Cordic module Ctrl register + * + * @return Ctrl register value + */ +LOCAL_INLINE uint32_t Cordic_HWA_GetCtrl(void) +{ + return (uint32_t)(CORDIC->CTRL); +} + +/** + * @brief Set Cordic module XInput register + * + * @param u32Value XInput register value + */ +LOCAL_INLINE void Cordic_HWA_Set_XInput(int32_t u32Value) +{ + CORDIC->X_INPUT = (uint32_t)u32Value; +} + +/** + * @brief Set Cordic module YInput register + * + * @param u32Value YInput register value + */ +LOCAL_INLINE void Cordic_HWA_Set_YInput(int32_t u32Value) +{ + CORDIC->Y_INPUT = (uint32_t)u32Value; +} + +/** + * @brief Set Cordic module ZInput register + * + * @param u32Value ZInput register value + */ +LOCAL_INLINE void Cordic_HWA_Set_ZInput(int32_t u32Value) +{ + CORDIC->Z_INPUT = (uint32_t)u32Value; +} + +/** + * @brief Read Cordic module XOutput register + * + * @return XOutput register value + */ +LOCAL_INLINE uint32_t Cordic_HWA_Get_XOutput(void) +{ + return (uint32_t)(CORDIC->X_OUTPUT); +} + +/** + * @brief Read Cordic module YOutput register + * + * @return YOutput register value + */ +LOCAL_INLINE uint32_t Cordic_HWA_Get_YOutput(void) +{ + return (uint32_t)(CORDIC->Y_OUTPUT); +} + +/** + * @brief Read Cordic module ZOutput register + * + * @return ZOutput register value + */ +LOCAL_INLINE uint32_t Cordic_HWA_Get_ZOutput(void) +{ + return (uint32_t)(CORDIC->Z_OUTPUT); +} + +/** + * @brief Read Cordic module state + * + * @return Cordic module current state + */ +LOCAL_INLINE bool Cordic_HWA_Get_Stat(void) +{ + return (bool)(CORDIC->STAT & CORDIC_STAT_DONE_MASK); +} + +#endif diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_cpm.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_cpm.h new file mode 100644 index 0000000..a9904ed --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_cpm.h @@ -0,0 +1,350 @@ +/** + * @file HwA_cpm.h + * @author Flagchip + * @brief FC7xxx CPM register API + * @version 0.1.0 + * @date 2024-1-5 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-1-5 Flagchip120 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef HWA_INCLUDE_HWA_CPM_H_ +#define HWA_INCLUDE_HWA_CPM_H_ +#include "device_header.h" +/* ################################################################################## */ +/* ####################################### Macro #################################### */ + +/** FPSCR Bit Fields */ +#define FPSCR_IOC_MASK 0x00000001U +#define FPSCR_DZC_MASK 0x00000002U +#define FPSCR_OFC_MASK 0x00000004U +#define FPSCR_UFC_MASK 0x00000008U +#define FPSCR_IXC_MASK 0x00000010U +#define FPSCR_IDC_MASK 0x00000080U +#define CPM_FPU_INTFLAGMASK 0x0000003FU + +/** + * @defgroup HwA_cpm + * @ingroup fc7xxx_driver_cpm + * @{ + */ + +/** + * @brief FPU INTERRUPT type. + * + * This provides constants for FPU interrupt type for use in the FPU functions. + * Please refer to Reference Manual chapter 14 CPM, it introduce register FISCR for details. + * + */ + + +typedef enum +{ + CPM_FPU_FIO = 1U, /*!< in function CPM_FpuIntMode, set CPM_FISCR FIOCE bit; in function CPM_GetFpuIntStatus, get CPM_FISCR FIOC Status*/ + CPM_FPU_FDZ = 2U, /*!< in function CPM_FpuIntMode, set CPM_FISCR FDZCE bit; in function CPM_GetFpuIntStatus, get CPM_FISCR FDZC Status*/ + CPM_FPU_FUF = 4U, /*!< in function CPM_FpuIntMode, set CPM_FISCR FUFCE bit; in function CPM_GetFpuIntStatus, get CPM_FISCR FUFC Status*/ + CPM_FPU_FOF = 8U, /*!< in function CPM_FpuIntMode, set CPM_FISCR FOFCE bit; in function CPM_GetFpuIntStatus, get CPM_FISCR FOFC Status*/ + CPM_FPU_FID = 16U, /*!< in function CPM_FpuIntMode, set CPM_FISCR FIDCE bit; in function CPM_GetFpuIntStatus, get CPM_FISCR FIDC Status*/ + CPM_FPU_FIX = 32U /*!< in function CPM_FpuIntMode, set CPM_FISCR FIXCE bit; in function CPM_GetFpuIntStatus, get CPM_FISCR FIXC Status*/ +} FPU_IntType; + + +/** @brief Cpm return type. */ + +typedef enum +{ + CPM_STATUS_SUCCESS = 0U, /*!< CPM status success */ + CPM_STATUS_PARAM_INVALID = 1U /*!< CPM status parameter invalid */ +} CPM_RetType; + +/** + * @brief Get the value of CPM FISCR. + * + * This function returns FISCR value. + * + * @return uint32_t the value of the FISCR register. + */ +LOCAL_INLINE uint32_t CPM_HWA_GetFiscr(void) +{ + return CPM->FISCR; +} + +/** + * @brief Return CPM_FISCR FIOC value + * + * @return 0: No interrupt; 1: Interrupt occurred + */ +LOCAL_INLINE bool CPM_HWA_GetFpuFiocFlag(void) +{ + uint32_t u32TmpVal = CPM->FISCR; + u32TmpVal = (u32TmpVal & CPM_FISCR_FIOC_MASK) >> CPM_FISCR_FIOC_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Return CPM_FISCR FDZC value + * + * @return 0: No interrupt; 1: Interrupt occurred + */ +LOCAL_INLINE bool CPM_HWA_GetFpuFdzcFlag(void) +{ + uint32_t u32TmpVal = CPM->FISCR; + u32TmpVal = (u32TmpVal & CPM_FISCR_FDZC_MASK) >> CPM_FISCR_FDZC_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Return CPM_FISCR FOFC value + * + * @return 0: No interrupt; 1: Interrupt occurred + */ +LOCAL_INLINE bool CPM_HWA_GetFpuFofcFlag(void) +{ + uint32_t u32TmpVal = CPM->FISCR; + u32TmpVal = (u32TmpVal & CPM_FISCR_FOFC_MASK) >> CPM_FISCR_FOFC_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Return CPM_FISCR FUFC value + * + * @return 0: No interrupt; 1: Interrupt occurred + */ +LOCAL_INLINE bool CPM_HWA_GetFpuFufcFlag(void) +{ + uint32_t u32TmpVal = CPM->FISCR; + u32TmpVal = (u32TmpVal & CPM_FISCR_FUFC_MASK) >> CPM_FISCR_FUFC_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Return CPM_FISCR FIXC value + * + * @return 0: No interrupt; 1: Interrupt occurred + */ +LOCAL_INLINE bool CPM_HWA_GetFpuFixcFlag(void) +{ + uint32_t u32TmpVal = CPM->FISCR; + u32TmpVal = (u32TmpVal & CPM_FISCR_FIXC_MASK) >> CPM_FISCR_FIXC_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Return CPM_FISCR FIDC value + * + * @return 0: No interrupt; 1: Interrupt occurred + */ +LOCAL_INLINE bool CPM_HWA_GetFpuFidcFlag(void) +{ + uint32_t u32TmpVal = CPM->FISCR; + u32TmpVal = (u32TmpVal & CPM_FISCR_FIDC_MASK) >> CPM_FISCR_FIDC_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set FIOCE interrupt + * + * @param bEnable 1: enable interrupt 0: disable interrupt + */ +LOCAL_INLINE void CPM_HWA_SetFioceInt(bool bEnable) +{ + CPM->FISCR = ((CPM->FISCR & (~CPM_FISCR_FIOCE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_FISCR_FIOCE_SHIFT)); +} + +/** + * @brief Set FDZCE interrupt + * + * @param bEnable 1: enable interrupt 0: disable interrupt + */ +LOCAL_INLINE void CPM_HWA_SetFdzceInt(bool bEnable) +{ + CPM->FISCR = ((CPM->FISCR & (~CPM_FISCR_FDZCE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_FISCR_FDZCE_SHIFT)); +} + +/** + * @brief Set FOFCE interrupt + * + * @param bEnable 1: enable interrupt 0: disable interrupt + */ +LOCAL_INLINE void CPM_HWA_SetFofceInt(bool bEnable) +{ + CPM->FISCR = ((CPM->FISCR & (~CPM_FISCR_FOFCE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_FISCR_FOFCE_SHIFT)); +} + +/** + * @brief Set FUFCE interrupt + * + * @param bEnable 1: enable interrupt 0: disable interrupt + */ +LOCAL_INLINE void CPM_HWA_SetFufceInt(bool bEnable) +{ + CPM->FISCR = ((CPM->FISCR & (~CPM_FISCR_FUFCE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_FISCR_FUFCE_SHIFT)); +} + +/** + * @brief Set FIXCE interrupt + * + * @param bEnable 1: enable interrupt 0: disable interrupt + */ +LOCAL_INLINE void CPM_HWA_SetFixceInt(bool bEnable) +{ + CPM->FISCR = ((CPM->FISCR & (~CPM_FISCR_FIXCE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_FISCR_FIXCE_SHIFT)); +} + +/** + * @brief Set FIDCE interrupt + * + * @param bEnable 1: enable interrupt 0: disable interrupt + */ +LOCAL_INLINE void CPM_HWA_SetFidceInt(bool bEnable) +{ + CPM->FISCR = ((CPM->FISCR & (~CPM_FISCR_FIDCE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_FISCR_FIDCE_SHIFT)); +} + +/** + * @brief Set FISCR value + * + * @param u32Val the value want to set the register + */ +LOCAL_INLINE void CPM_HWA_SetFiscr(uint32_t u32Val) +{ + CPM->FISCR = u32Val; +} + +/** + * @brief Get the value of CPM TCMRCR. + * + * This function returns TCMRCR value. + * + * @return uint32_t the value of the TCMRCR register. + */ +LOCAL_INLINE uint32_t CPM_HWA_GetTcmrcr(void) +{ + return CPM->TCMRCR; +} + +/** + * @brief Set DTCM1 retry buffer force clear + * + * @param bEnable 1:Force clear DTCM1 retry buffer 0: No operation + */ +LOCAL_INLINE void CPM_HWA_SetDTCM1BufClear(bool bEnable) +{ + CPM->FISCR = ((CPM->FISCR & (~CPM_TCMRCR_D1RBCLR_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_TCMRCR_D1RBCLR_SHIFT)); +} + +/** + * @brief Set DTCM0 retry buffer force clear + * + * @param bEnable 1:Force clear DTCM0 retry buffer 0: No operation + */ +LOCAL_INLINE void CPM_HWA_SetDTCM0BufClear(bool bEnable) +{ + CPM->FISCR = ((CPM->FISCR & (~CPM_TCMRCR_D0RBCLR_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_TCMRCR_D0RBCLR_SHIFT)); +} + +/** + * @brief Set ITCM retry buffer force clear + * + * @param bEnable 1:Force clear ITCM retry buffer 0: No operation + */ +LOCAL_INLINE void CPM_HWA_SetITCMBufClear(bool bEnable) +{ + CPM->FISCR = ((CPM->FISCR & (~CPM_TCMRCR_IRBCLR_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_TCMRCR_IRBCLR_SHIFT)); +} + +/** + * @brief Set DTCM1 retry buffer invalid + */ +LOCAL_INLINE void CPM_HWA_SetDTCM1BufInvalid(void) +{ + CPM->FISCR = ((CPM->FISCR & (~CPM_TCMRCR_D1RBVLD_MASK)) | (1U << CPM_TCMRCR_D1RBCLR_SHIFT)); +} + +/** + * @brief Set DTCM0 retry buffer invalid + */ +LOCAL_INLINE void CPM_HWA_SetDTCM0BufInvalid(void) +{ + CPM->FISCR = ((CPM->FISCR & (~CPM_TCMRCR_D0RBVLD_MASK)) | (1U << CPM_TCMRCR_D0RBCLR_SHIFT)); +} + +/** + * @brief Set ITCM retry buffer invalid + */ +LOCAL_INLINE void CPM_HWA_SetITCMBufInvalid(void) +{ + CPM->FISCR = ((CPM->FISCR & (~CPM_TCMRCR_IRBVLD_MASK)) | (1U << CPM_TCMRCR_IRBCLR_SHIFT)); +} + +/** + * @brief Set DTCM1 retry buffer timeout interrupt enable + * + * @param bEnable 1:Interrupt enable 0: No operation + */ +LOCAL_INLINE void CPM_HWA_SetDTCM1TimeoutInt(bool bEnable) +{ + CPM->FISCR = ((CPM->FISCR & (~CPM_TCMRCR_D1RBIE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_TCMRCR_D1RBIE_SHIFT)); +} + +/** + * @brief Set DTCM0 retry buffer timeout interrupt enable + * + * @param bEnable 1:Interrupt enable 0: No operation + */ +LOCAL_INLINE void CPM_HWA_SetDTCM0TimeoutInt(bool bEnable) +{ + CPM->FISCR = ((CPM->FISCR & (~CPM_TCMRCR_D0RBIE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_TCMRCR_D0RBIE_SHIFT)); +} + +/** + * @brief Set ITCM retry buffer timeout interrupt enable + * + * @param bEnable 1:Interrupt enable 0: No operation + */ +LOCAL_INLINE void CPM_HWA_SetITCMTimeoutInt(bool bEnable) +{ + CPM->FISCR = ((CPM->FISCR & (~CPM_TCMRCR_IRBIE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_TCMRCR_IRBIE_SHIFT)); +} + +/** + * @brief Set DTCM1 retry buffer autoclear + * + * @param bEnable 1:Enable autoclear 0: No operation + */ +LOCAL_INLINE void CPM_HWA_SetDTCM1AutoClear(bool bEnable) +{ + CPM->FISCR = ((CPM->FISCR & (~CPM_TCMRCR_D1RBAC_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_TCMRCR_D1RBAC_SHIFT)); +} + +/** + * @brief Set DTCM0 retry buffer autoclear + * + * @param bEnable 1:Enable autoclear 0: No operation + */ +LOCAL_INLINE void CPM_HWA_SetDTCM0AutoClear(bool bEnable) +{ + CPM->FISCR = ((CPM->FISCR & (~CPM_TCMRCR_D0RBAC_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_TCMRCR_D0RBAC_SHIFT)); +} + +/** + * @brief Set ITCM retry buffer autoclear + * + * @param bEnable 1:Enable autoclear 0: No operation + */ +LOCAL_INLINE void CPM_HWA_SetITCMAutoClear(bool bEnable) +{ + CPM->FISCR = ((CPM->FISCR & (~CPM_TCMRCR_IRBAC_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << CPM_TCMRCR_IRBAC_SHIFT)); +} + +/** @}*/ + +#endif /* HWA_INCLUDE_HWA_CPM_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_crc.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_crc.h new file mode 100644 index 0000000..8877410 --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_crc.h @@ -0,0 +1,313 @@ +/** + * @file HwA_crc.h + * @author Flagchip + * @brief FC7xxx CRC hardware access layer + * @version 0.1.0 + * @date 2024-01-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-12 Flagchip119 N/A First version for FC7240 + ******************************************************************************** */ + + +#ifndef _HWA_CRC_H_ +#define _HWA_CRC_H_ + +#include "device_header.h" + + +/********* Local typedef ************/ + +/** + * @brief The data swap for write + */ +typedef enum{ + WRITE_DATASWAP_NONE = 0U, /*!< none data swap for write */ + WRITE_DATASWAP_BIT = 1U, /*!< only bits data swap for write */ + WRITE_DATASWAP_BIT_BYTE = 2U, /*!< both bits and bytes data swap for write */ + WRITE_DATASWAP_BYTE = 3U /*!< only bytes data swap for write */ +} CRC_WriteDataSwapType; + +/** + * @brief The data swap for read + */ +typedef enum{ + READ_DATASWAP_NONE = 0U, /*!< none data swap for read */ + READ_DATASWAP_BIT = 1U, /*!< only bits data swap for read */ + READ_DATASWAP_BIT_BYTE = 2U, /*!< both bits and bytes data swap for read */ + READ_DATASWAP_BYTE = 3U /*!< only bytes data swap for read */ +} CRC_ReadDataSwapType; + +/** + * @brief The complement of reading crc data + */ +typedef enum{ + READ_DATA_NORMAL = 0U, /*!< none complement of reading crc data */ + READ_DATA_FXOR = 1U /*!< Invert or complement with 0xFFFFFFFF or 0xFFFF of crc data */ +} CRC_ReadDataFXORType; + +/** + * @brief The command type of write crc data or seed value + */ +typedef enum{ + WRITE_COMMAND_DATA = 0U, /*!< write crc data */ + WRITE_COMMAND_SEED = 1U /*!< write seed value(used to initialization crc calculation) */ +} CRC_WriteCommondType; + +/** + * @brief The crc mode select + */ +typedef enum{ + CRC_BIT_16 = 0U, /*!< crc 16 bit is selected */ + CRC_BIT_32 = 1U, /*!< crc 32 bit is selected */ + CRC_BIT_8 = 2U, + CRC_BIT_INVALID = 3U +} CRC_BitWidthType; + + +/********* Local inline function ************/ + +/** + * @brief set CRC CR register for writing data or seed + * + * @param pCrc CRC instance + * @param u32Mod WAS mode + */ +LOCAL_INLINE void CRC_HWA_SetDataOrSeed(CRC_Type *const pCrc, CRC_WriteCommondType u32Mod) +{ + uint32_t u32RegVal = pCrc->CR; + pCrc->CR = ((u32RegVal & (~(uint32_t)CRC_CR_WAS_MASK)) | CRC_CR_WAS(u32Mod)); +} + +/** + * @brief set polynomial value + * + * @param pCrc CRC instance + * @param u32Poly the polynomial value + */ +LOCAL_INLINE void CRC_HWA_SetPolyVal(CRC_Type *const pCrc, uint32_t u32Poly) +{ + pCrc->POLY = u32Poly; +} + +/** + * @brief set data register(32 bits) + * + * @param pCrc CRC instance + * @param u32Data data to be set + */ +LOCAL_INLINE void CRC_HWA_SetData_U32(CRC_Type *const pCrc, uint32_t u32Data) +{ + pCrc->DATA.uDATA = u32Data; +} + +/** + * @brief set data register(16 bits) + * + * @param pCrc CRC instance + * @param u16Data data to be set + */ +LOCAL_INLINE void CRC_HWA_SetData_U16(CRC_Type *const pCrc, uint16_t u16Data) +{ + pCrc->DATA.tDATA_16.L = u16Data; +} + +/** + * @brief set data register(low 8 bits) + * + * @param pCrc CRC instance + * @param u8Data data to be set + */ +LOCAL_INLINE void CRC_HWA_SetData_U8(CRC_Type *const pCrc, uint8_t u8Data) +{ + pCrc->DATA.tDATA_8.LL = u8Data; +} + +/** + * @brief get data register(32 bits) + * + * @param pCrc CRC instance + * + * @return 32-bit value + */ +LOCAL_INLINE uint32_t CRC_HWA_GetData_U32(CRC_Type *const pCrc) +{ + return (pCrc->DATA.uDATA); +} + +/** + * @brief get data register(high 8 bits) + * + * @param pCrc CRC instance + * + * @return high 8-bit value + */ +LOCAL_INLINE uint8 CRC_HWA_GetData_U8_H(CRC_Type *const pCrc) +{ + return (pCrc->DATA.tDATA_8.HL); +} + +/** + * @brief get data register(low 8 bits) + * + * @param pCrc CRC instance + * + * @return low 8-bit value + */ +LOCAL_INLINE uint8 CRC_HWA_GetData_U8_L(CRC_Type *const pCrc) +{ + return (pCrc->DATA.tDATA_8.LL); +} + +/** + * @brief get data register(high 16 bits) + * + * @param pCrc CRC instance + * + * @return high 16-bit value + */ +LOCAL_INLINE uint16_t CRC_HWA_GetData_U16_H(CRC_Type *const pCrc) +{ + return (pCrc->DATA.tDATA_16.H); +} + +/** + * @brief get data register(low 16 bits) + * + * @param pCrc CRC instance + * + * @return low 16-bit value + */ +LOCAL_INLINE uint16_t CRC_HWA_GetData_U16_L(CRC_Type *const pCrc) +{ + return (pCrc->DATA.tDATA_16.L); +} + +/** + * @brief set data swap for writes + * + * @param pCrc CRC instance + * @param eWrDataSwap the CRC_WriteDataSwapType type + */ +LOCAL_INLINE void CRC_HWA_SetWriteDataSwap(CRC_Type *const pCrc, CRC_WriteDataSwapType eWrDataSwap) +{ + uint32_t u32RegVal = pCrc->CR; + pCrc->CR = ((u32RegVal & (~(uint32_t)CRC_CR_DSW_MASK)) | CRC_CR_DSW(eWrDataSwap)); +} + +/** + * @brief set data swap for read + * + * @param pCrc CRC instance + * @param eRdDataSwap the eRdDataSwap type + */ +LOCAL_INLINE void CRC_HWA_SetReadDataSwap(CRC_Type *const pCrc, CRC_ReadDataSwapType eRdDataSwap) +{ + uint32_t u32RegVal = pCrc->CR; + pCrc->CR = ((u32RegVal & (~(uint32_t)CRC_CR_DSR_MASK)) | CRC_CR_DSR(eRdDataSwap)); +} + +/** + * @brief set complement read Of CRC data + * + * @param pCrc CRC instance + * @param eRdDataFXOR the CRC_ReadDataFXORType type + */ +LOCAL_INLINE void CRC_HWA_SetReadDataFXOR(CRC_Type *const pCrc, CRC_ReadDataFXORType eRdDataFXOR) +{ + uint32_t u32RegVal = pCrc->CR; + pCrc->CR = ((u32RegVal & (~(uint32_t)CRC_CR_FXOR_MASK)) | CRC_CR_FXOR(eRdDataFXOR)); +} + +/** + * @brief set width of CRC protocol + * + * @param pCrc CRC instance + * @param eWidth the CRC_BitWidthType type + */ +LOCAL_INLINE void CRC_HWA_SetBitWidth(CRC_Type *const pCrc, CRC_BitWidthType eWidth) +{ + uint32_t u32RegVal = pCrc->CR; + pCrc->CR = ((u32RegVal & (~(uint32_t)CRC_CR_TCRC_MASK)) | CRC_CR_TCRC(eWidth)); +} + +/** + * @brief set width of CRC protocol + * + * @param pCrc CRC instance + * @param eWidth the CRC_BitWidthType type + */ +LOCAL_INLINE void CRC_HWA_Set_8Bit_Width(CRC_Type *const pCrc, CRC_BitWidthType eWidth) +{ + uint32_t u32RegVal = pCrc->CR; + pCrc->CR = ((u32RegVal & (~(uint32_t)CRC_CR_TCRC8_MASK)) | CRC_CR_TCRC8(eWidth)); +} + +/** + * @brief get width of CRC protocol + * + * @param pCrc CRC instance + */ +LOCAL_INLINE CRC_BitWidthType CRC_HWA_GetBitWidth(CRC_Type *const pCrc) +{ + uint32_t u32TempVal = (pCrc->CR & ((uint32_t)CRC_CR_TCRC_MASK)) >> CRC_CR_TCRC_SHIFT; + return ((u32TempVal == 0U)?CRC_BIT_16:CRC_BIT_32); +} + +/** + * @brief get 8-bit width of CRC protocol + * + * @param pCrc CRC instance + */ +LOCAL_INLINE CRC_BitWidthType CRC_HWA_Get8BitWidth(CRC_Type *const pCrc) +{ + uint32 u32TempVal = (pCrc->CR & ((uint32)CRC_CR_TCRC8_MASK)) >> CRC_CR_TCRC8_SHIFT; + return ((u32TempVal == 1U)?CRC_BIT_8:CRC_BIT_INVALID); +} + +/** + * @brief get data swap type for read + * + * @param pCrc CRC instance + */ +LOCAL_INLINE CRC_ReadDataSwapType CRC_HWA_GetReadDataSwap(CRC_Type *const pCrc) +{ + CRC_ReadDataSwapType eRet = READ_DATASWAP_NONE; + uint32_t u32TempVal; + + u32TempVal = (pCrc->CR & ((uint32_t)CRC_CR_DSR_MASK))>>CRC_CR_DSR_SHIFT; + if (u32TempVal == 0U) + { + eRet = READ_DATASWAP_NONE; + } + else if (u32TempVal == 1U) + { + eRet = READ_DATASWAP_BIT; + } + else if (u32TempVal == 2U) + { + eRet = READ_DATASWAP_BIT_BYTE; + } + else if (u32TempVal == 3U) + { + eRet = READ_DATASWAP_BYTE; + } + else + { + /*Noting to do*/ + } + return eRet; +} + + + + +#endif /* #ifndef _HWA_CRC_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_csc.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_csc.h new file mode 100644 index 0000000..c346294 --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_csc.h @@ -0,0 +1,1705 @@ +/** + * @file HwA_csc.h + * @author Flagchip085 + * @brief Hardware access layer for CSC + * @version 0.1.0 + * @date 2024-01-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef _HWA_CSC_H_ +#define _HWA_CSC_H_ + +#include "device_header.h" + +#define CSC_STOP_PERIPH_GROUP_MAX 3U + +#define CSC_STOP_PERIPH_GROUP0_MASK (CSC0_STOP_MODER0_MASK & 0x00FFFFFFU) + +#define CSC_STOP_PERIPH_GROUP1_MASK (CSC0_STOP_MODER1_MASK & 0x00FFFFFFU) + +#define CSC_STOP_PERIPH_GROUP2_MASK (CSC0_STOP_MODER2_MASK & 0x00FFFFFFU) + +#define CSC_SMU_CTRL_GROUP0_MASK (CSC0_SMU_CTRL0_MASK & 0xFFFFFFFEU) + +#define CSC_SMU_CTRL_GROUP1_MASK (CSC0_SMU_CTRL1_MASK & 0xFFFFFFFEU) + +#define CSC_SMU_CTRL_GROUP4_MASK (CSC0_SMU_CTRL4_MASK & 0xFFFFFFFEU) + +#define CSC_SMU_CTRL_GROUP5_MASK (CSC0_SMU_CTRL5_MASK & 0xFFFFFFFEU) + + +/********* Local typedef ************/ + +/** + * @brief Control cpu type + * + */ +typedef enum +{ + CSC_WP_CPU_ALL = 0U, /*!< All CPUs are allowed to write this peripheral */ + CSC_WP_CPU_0 = 1U, /*!< Only CPU0 is allowed to control this peripheral */ + CSC_WP_CPU_NONE = 2U /*!< No CPU is allowed to control this peripheral */ +} CSC_WPB_CpuType; + +/** + * @brief Hand shake mode type + * + */ +typedef enum +{ + CSC_WAIT_ALL_ACK = 0U, /*!< follow other master stop acknowledge state */ + CSC_WAIT_REQ_ACK = 3U /*!< follow cpu stop acknowledge state */ +} CSC_HandShakeModeType; + +/** + * @brief CSC0 clock out divide ratio type + * + */ +typedef enum +{ + CSC0_CLKOUT_DIV_BY1 = 0U, /*!< Divided by 1 */ + CSC0_CLKOUT_DIV_BY2 = 1U, /*!< Divided by 2 */ + CSC0_CLKOUT_DIV_BY3 = 2U, /*!< Divided by 3 */ + CSC0_CLKOUT_DIV_BY4 = 3U, /*!< Divided by 4 */ + CSC0_CLKOUT_DIV_BY5 = 4U, /*!< Divided by 5 */ + CSC0_CLKOUT_DIV_BY6 = 5U, /*!< Divided by 6 */ + CSC0_CLKOUT_DIV_BY7 = 6U, /*!< Divided by 7 */ + CSC0_CLKOUT_DIV_BY8 = 7U /*!< Divided by 8 */ +} CSC0_ClockOutDivType; + +/** + * @brief CSC0 clock out source type + * + */ +typedef enum +{ + CSC0_CLKOUT_SCG_CLKOUT = 0U, /*!< SCG CLKOUT */ + CSC0_CLKOUT_FOSC_DIVM_CLK = 2U, /*!< FOSC DIVM CLK */ + CSC0_CLKOUT_SLOW_CLK = 3U, /*!< SLOW CLK */ + CSC0_CLKOUT_SIRC_DIVM_CLK = 4U, /*!< SIRC DIVM CLK */ + CSC0_CLKOUT_PLL1_DIVM_CLK = 5U, /*!< PLL1 DIVM CLK */ + CSC0_CLKOUT_FIRC_DIVM_CLK = 6U, /*!< FIRC DIVM CLK */ + CSC0_CLKOUT_CORE_CLK = 7U, /*!< CORE CLK */ + CSC0_CLKOUT_PLL0_DIVM_CLK = 8U, /*!< PLL0 DIVM CLK */ + CSC0_CLKOUT_BUS_CLK = 9U, /*!< BUS CLK */ + CSC0_CLKOUT_SIRC_128K_CLK = 10U, /*!< SIRC 128K CLK */ + CSC0_CLKOUT_AON_CLK = 12U, /*!< AON CLK */ + CSC0_CLKOUT_RTC_CLK = 14U /*!< RTC CLK */ +} CSC0_ClockOutSrcType; + +/** + * @brief Data type for CSC0_AONCLKSR[32KAONCLKSEL], set AON32KCLK source clock + * + */ +typedef enum +{ + CSC0_AON32K_SIRCDIV_32K_CLK = 1U, /*!< CSC0_AONCLKSR[32KAONCLKSEL], SIRCDIV_32K */ + CSC0_AON32K_SOSC32K_CLK = 2U, /*!< CSC0_AONCLKSR[32KAONCLKSEL], SOSC32K */ + CSC0_AON32K_SIRC32K_CLK = 3U /*!< CSC0_AONCLKSR[32KAONCLKSEL], SIRC32K */ +} CSC0_AON32KClkSrcType; + +/** + * @brief Data type for CSC0_RTCCLKSEL[RTCCLKSEL], set RTCCLK source clock + * + */ +typedef enum +{ + CSC0_RTC_FOSCDIVL_CLK = 0U, /*!< CSC0_RTCCLKSEL[RTCCLKSEL], FOSC_DIVL */ + CSC0_RTC_SIRCDIV_32K_CLK = 1U, /*!< CSC0_RTCCLKSEL[RTCCLKSEL], SIRC_DIV */ + CSC0_RTC_SOSC_CLK = 2U, /*!< CSC0_RTCCLKSEL[RTCCLKSEL], SOSC */ + CSC0_RTC_SIRC32K_CLK = 3U /*!< CSC0_RTCCLKSEL[RTCCLKSEL], SIRC_32K */ +} CSC0_RTCClkSrcType; + +/** + * @brief Data type for CSC0_AONCLKSEL[AONCLKSEL], set AONCLK source clock + * + */ +typedef enum +{ + CSC0_AON_SIRCDIV_128K_CLK = 0U, /*!< CSC0_AONCLKSEL[AONCLKSEL], SIRCDIV_128K */ + CSC0_AON_SIRC32K_CLK = 1U, /*!< CSC0_AONCLKSEL[AONCLKSEL], SIRC32K */ + CSC0_AON_SIRCDIV_32K_CLK = 2U, /*!< CSC0_AONCLKSEL[AONCLKSEL], SIRCDIV_32K */ + CSC0_AON_SIRC32_1K_CLK = 3U /*!< CSC0_AONCLKSEL[AONCLKSEL], SIRC32_1K */ +} CSC0_AONClkSrcType; + + +/** + * @brief Register 0 related peripheral(CSC0,CSC1,CSC2) + */ +typedef enum +{ + CSC_STOPMODE_FLEXCAN1 = (int)CSC0_STOP_MODER0_FLEXCAN1_MASK, /*!< Stop acknowledge function FLEXCAN1 */ + CSC_STOPMODE_FLEXCAN0 = (int)CSC0_STOP_MODER0_FLEXCAN0_MASK, /*!< Stop acknowledge function FLEXCAN0 */ + CSC_STOPMODE_FREQM = (int)CSC0_STOP_MODER0_FREQM_MASK, /*!< Stop acknowledge function FREQM */ + CSC_STOPMODE_FCUART3 = (int)CSC0_STOP_MODER0_FCUART3_MASK, /*!< Stop acknowledge function FCUART3 */ + CSC_STOPMODE_FCUART2 = (int)CSC0_STOP_MODER0_FCUART2_MASK, /*!< Stop acknowledge function FCUART2 */ + CSC_STOPMODE_FCUART1 = (int)CSC0_STOP_MODER0_FCUART1_MASK, /*!< Stop acknowledge function FCUART1 */ + CSC_STOPMODE_FCSPI2 = (int)CSC0_STOP_MODER0_FCSPI2_MASK, /*!< Stop acknowledge function FCSPI2 */ + CSC_STOPMODE_FCSPI1 = (int)CSC0_STOP_MODER0_FCSPI1_MASK, /*!< Stop acknowledge function FCSPI1 */ + CSC_STOPMODE_SENT0 = (int)CSC0_STOP_MODER0_SENT0_MASK, /*!< Stop acknowledge function SENT0 */ + CSC_STOPMODE_TMU = (int)CSC0_STOP_MODER0_TMU_MASK, /*!< Stop acknowledge function TMU */ + CSC_STOPMODE_ADC1 = (int)CSC0_STOP_MODER0_ADC1_MASK, /*!< Stop acknowledge function ADC1 */ + CSC_STOPMODE_ADC0 = (int)CSC0_STOP_MODER0_ADC0_MASK, /*!< Stop acknowledge function ADC0 */ + CSC_STOPMODE_CMU4 = (int)CSC0_STOP_MODER0_CMU4_MASK, /*!< Stop acknowledge function CMU4 */ + CSC_STOPMODE_WDOG0 = (int)CSC0_STOP_MODER0_WDOG0_MASK, /*!< Stop acknowledge function WDG0 */ + CSC_STOPMODE_ISM0 = (int)CSC0_STOP_MODER0_ISM0_MASK, /*!< Stop acknowledge function ISM0 */ + CSC_STOPMODE_DMA0 = (int)CSC0_STOP_MODER0_DMA0_MASK /*!< Stop acknowledge function DMA0 */ +} CSCx_Reg0_PeriphType; + +/** + * @brief Register 1 related peripheral(CSC0,CSC1,CSC2) + */ +typedef enum +{ + CSC_STOPMODE_FLEXCAN3 = (int)CSC0_STOP_MODER1_FLEXCAN3_MASK, /*!< Stop acknowledge function FLEXCAN3 */ + CSC_STOPMODE_FLEXCAN2 = (int)CSC0_STOP_MODER1_FLEXCAN2_MASK, /*!< Stop acknowledge function FLEXCAN2 */ + CSC_STOPMODE_MSC0 = (int)CSC0_STOP_MODER1_MSC0_MASK, /*!< Stop acknowledge function MSC0 */ + CSC_STOPMODE_FCUART7 = (int)CSC0_STOP_MODER1_FCUART7_MASK, /*!< Stop acknowledge function FCUART7 */ + CSC_STOPMODE_FCUART6 = (int)CSC0_STOP_MODER1_FCUART6_MASK, /*!< Stop acknowledge function FCUART6 */ + CSC_STOPMODE_FCUART5 = (int)CSC0_STOP_MODER1_FCUART5_MASK, /*!< Stop acknowledge function FCUART5 */ + CSC_STOPMODE_FCUART4 = (int)CSC0_STOP_MODER1_FCUART4_MASK, /*!< Stop acknowledge function FCUART4 */ + CSC_STOPMODE_FCIIC1 = (int)CSC0_STOP_MODER1_FCIIC1_MASK, /*!< Stop acknowledge function FCIIC1 */ + CSC_STOPMODE_FCSPI5 = (int)CSC0_STOP_MODER1_FCSPI5_MASK, /*!< Stop acknowledge function FCSPI5 */ + CSC_STOPMODE_FCSPI4 = (int)CSC0_STOP_MODER1_FCSPI4_MASK, /*!< Stop acknowledge function FCSPI4 */ + CSC_STOPMODE_FCSPI3 = (int)CSC0_STOP_MODER1_FCSPI3_MASK, /*!< Stop acknowledge function FCSPI3 */ + CSC_STOPMODE_WDOG1 = (int)CSC0_STOP_MODER1_WDOG1_MASK, /*!< Stop acknowledge function WDOG1 */ +} CSCx_Reg1_PeriphType; + +/** + * @brief Regsister 2 related peripheral(CSC0,CSC1,CSC2) + */ +typedef enum +{ + CSC_STOPMODE_FCUART0 = (int)CSC0_STOP_MODER2_FCUART0_MASK, /*!< Stop acknowledge function FCUART0 */ + CSC_STOPMODE_FCIIC0 = (int)CSC0_STOP_MODER2_FCIIC0_MASK, /*!< Stop acknowledge function FCIIC0 */ + CSC_STOPMODE_FCSPI0 = (int)CSC0_STOP_MODER2_FCSPI0_MASK, /*!< Stop acknowledge function FCSPI0 */ + CSC_STOPMODE_CMP1 = (int)CSC0_STOP_MODER2_CMP1_MASK, /*!< Stop acknowledge function CMP1 */ + CSC_STOPMODE_CMP0 = (int)CSC0_STOP_MODER2_CMP0_MASK, /*!< Stop acknowledge function CMP0 */ + CSC_STOPMODE_CMU3 = (int)CSC0_STOP_MODER2_CMU3_MASK, /*!< Stop acknowledge function CMU3 */ + CSC_STOPMODE_CMU2 = (int)CSC0_STOP_MODER2_CMU2_MASK, /*!< Stop acknowledge function CMU2 */ + CSC_STOPMODE_CMU1 = (int)CSC0_STOP_MODER2_CMU1_MASK, /*!< Stop acknowledge function CMU1 */ + CSC_STOPMODE_CMU0 = (int)CSC0_STOP_MODER2_CMU0_MASK /*!< Stop acknowledge function CMU0 */ +} CSCx_Reg2_PeriphType; + +/** + * @brief CCM stop clock type(CSC0,CSC1,CSC2) + */ +typedef enum +{ + CSC_CCM_STOPCLOCK_STATUS_SYS_SLAVE = (int)CSC0_CCM0_STATUS_CPU0_STOP_SYS_SLAVE_MASK, /*!< System Slave Clock */ + CSC_CCM_STOPCLOCK_STATUS_MASTER = (int)CSC0_CCM0_STATUS_CPU0_STOP_MASTER_MASK, /*!< Master Clock */ + CSC_CCM_STOPCLOCK_STATUS_SLOW_SLAVE = (int)CSC0_CCM0_STATUS_CPU0_STOP_SLOW_SLAVE_MASK, /*!< Slave Clock */ + CSC_CCM_STOPCLOCK_STATUS_BUS_SLAVE = (int)CSC0_CCM0_STATUS_CPU0_STOP_BUS_SLAVE_MASK /*!< Bus Slave Clock */ +} CSCx_CCM_StopClockType; + +/** + * @brief CSC0 SMU control group 0 + */ +typedef enum +{ + CSC_SMU_CMU4 = (int)CSC0_SMU_CTRL0_CMU4_MASK, /*!< CMU4 to FCSMU */ + CSC_SMU_PMC_MON = (int)CSC0_SMU_CTRL0_PMC_MON_MASK, /*!< PMC Monitor to FCSMU */ + CSC_SMU_CMU2 = (int)CSC0_SMU_CTRL0_CMU2_MASK, /*!< CMU2 to FCSMU */ + CSC_SMU_CMU1 = (int)CSC0_SMU_CTRL0_CMU1_MASK, /*!< CMU1 to FCSMU */ + CSC_SMU_PMC_LVD_HVD = (int)CSC0_SMU_CTRL0_PMC_LVD_HVD_MASK, /*!< PMC HVD/LVD to FCSMU */ + CSC_SMU_SRAM1_MON = (int)CSC0_SMU_CTRL0_SRAM1_MON_MASK, /*!< SRAM1 Decoder Monitor to FCSMU */ + CSC_SMU_SRAM0_MON = (int)CSC0_SMU_CTRL0_SRAM0_MON_MASK, /*!< SRAM0 Decoder Monitor to FCSMU */ + CSC_SMU_MCM = (int)CSC0_SMU_CTRL0_CPM_MON_MASK, /*!< CPU Private Module Monitor to FCSMU */ + CSC_SMU_MAM0_S5_DS_ECC = (int)CSC0_SMU_CTRL0_MAM0_S5_DS_ECC_MASK, /*!< MAM0 S5 Downsize ECC to FCSMU */ + CSC_SMU_MAM0_S8_DS = (int)CSC0_SMU_CTRL0_MAM0_S8_DS_MASK, /*!< MAM0 S8 Downsize Monitor to FCSMU */ + CSC_SMU_MAM0_S5_DS = (int)CSC0_SMU_CTRL0_MAM0_S5_DS_MASK, /*!< MAM0 S5 Downsize Monitor to FCSMU */ + CSC_SMU_DMA0 = (int)CSC0_SMU_CTRL0_DMA0_MASK, /*!< DMA0 ECC to FCSMU */ + CSC_SMU_HSM = (int)CSC0_SMU_CTRL0_HSM_MASK, /*!< HSM ECC to FCSMU */ + CSC_SMU_MAM0_S2F_MON = (int)CSC0_SMU_CTRL0_MAM0_S2F_MON_MASK, /*!< MAM0 S5 Slow to Fast AHBS Monitor to FCSMU */ + CSC_SMU_CPU0_AHBS = (int)CSC0_SMU_CTRL0_CPU0_AHBS_MASK, /*!< CPU0_AHBS ECC to FCSMU */ + CSC_SMU_MAM0_S8 = (int)CSC0_SMU_CTRL0_MAM0_S8_MASK, /*!< MAM0 S8 ECC to FCSMU */ + CSC_SMU_MAM0_S7 = (int)CSC0_SMU_CTRL0_MAM0_S7_MASK, /*!< MAM0 S7 ECC to FCSMU */ + CSC_SMU_MAM0_S6 = (int)CSC0_SMU_CTRL0_MAM0_S6_MASK, /*!< MAM0 S6 ECC to FCSMU */ + CSC_SMU_MAM0_S5 = (int)CSC0_SMU_CTRL0_MAM0_S5_MASK, /*!< MAM0 S5 ECC to FCSMU */ + CSC_SMU_MAM0_S4 = (int)CSC0_SMU_CTRL0_MAM0_S4_MASK, /*!< MAM0 S4 ECC to FCSMU */ + CSC_SMU_MAM0_S3 = (int)CSC0_SMU_CTRL0_MAM0_S3_MASK, /*!< MAM0 S3 ECC to FCSMU */ + CSC_SMU_MAM0_S2 = (int)CSC0_SMU_CTRL0_MAM0_S2_MASK, /*!< MAM0 S2 ECC to FCSMU */ + CSC_SMU_MAM0_S1 = (int)CSC0_SMU_CTRL0_MAM0_S1_MASK, /*!< MAM0 S1 ECC to FCSMU */ + CSC_SMU_MAM0_S0 = (int)CSC0_SMU_CTRL0_MAM0_S0_MASK /*!< MAM0 S0 ECC to FCSMU */ +} CSC_SMU_CtrlGrp0Type; + +/** + * @brief CSC0 SMU control group of CPUx(group1~3) + */ +typedef enum +{ + CSC_SMU_DTCM1_S_EN = (int)CSC0_SMU_CTRL1_CPU0_DTCM1_S_EN_MASK, /*!< CPU0 DTCM1 Single Bit Data to FCSMU */ + CSC_SMU_DTCM0_S_EN = (int)CSC0_SMU_CTRL1_CPU0_DTCM0_S_EN_MASK, /*!< CPU0 DTCM0 Single Bit Data to FCSMU */ + CSC_SMU_ITCM_S_EN = (int)CSC0_SMU_CTRL1_CPU0_ITCM_S_EN_MASK, /*!< CPU0 ITCM Single Bit Data to FCSMU */ + CSC_SMU_OVERLAY = (int)CSC0_SMU_CTRL1_CPU0_OVERLAY_MASK, /*!< CPU0 Overlay to FCSMU */ + CSC_SMU_DTCM1_MON = (int)CSC0_SMU_CTRL1_CPU0_DTCM1_MON_MASK, /*!< CPU0_DTCM1_MON to FCSMU */ + CSC_SMU_DTCM0_MON = (int)CSC0_SMU_CTRL1_CPU0_DTCM0_MON_MASK, /*!< CPU0_DTCM0_MON to FCSMU */ + CSC_SMU_ITCM_MON = (int)CSC0_SMU_CTRL1_CPU0_ITCM_MON_MASK, /*!< CPU0 ITCM Decoder Monitor to FCSMU */ + CSC_SMU_AHBM1_F2S = (int)CSC0_SMU_CTRL1_CPU0_AHBM1_F2S_MASK, /*!< CPU0 AHBM1 Fast to Slow Monitor to FCSMU */ + CSC_SMU_AHBM0_F2S = (int)CSC0_SMU_CTRL1_CPU0_AHBM0_F2S_MASK, /*!< CPU0 AHBM0 Fast to Slow Monitor to FCSMU */ + CSC_SMU_AHBP_F2S = (int)CSC0_SMU_CTRL1_CPU0_AHBP_F2S_MASK, /*!< CPU0 AHBP Fast to Slow Monito to FCSMU */ + CSC_SMU_DTCM1 = (int)CSC0_SMU_CTRL1_CPU0_DTCM1_MASK, /*!< CPU0 DTCM1 ECC to FCSMU */ + CSC_SMU_DTCM0 = (int)CSC0_SMU_CTRL1_CPU0_DTCM0_MASK, /*!< CPU0 DTCM0 ECC to FCSMU */ + CSC_SMU_ITCM = (int)CSC0_SMU_CTRL1_CPU0_ITCM_MASK, /*!< CPU0 ITCM ECC to FCSMU */ + CSC_SMU_DCACHE = (int)CSC0_SMU_CTRL1_CPU0_DCACHE_MASK, /*!< CPU0 Data CACHE to FCSMU */ + CSC_SMU_ICACHE = (int)CSC0_SMU_CTRL1_CPU0_ICACHE_MASK, /*!< CPU0 Code CACHE to FCSMU */ + CSC_SMU_AHBP = (int)CSC0_SMU_CTRL1_CPU0_AHBP_MASK, /*!< CPU0 AHBP ECC to FCSMU */ + CSC_SMU_AHBM = (int)CSC0_SMU_CTRL1_CPU0_AHBM_MASK /*!< CPU0 AHBM ECC to FCSMU */ +} CSC_SMU_Cpux_CtrlGrpType; + +/** + * @brief CSC0 SMU control group 4 + */ +typedef enum +{ + CSC_SMU_HSM_WDOG = (int)CSC0_SMU_CTRL4_HSM_WDOG_MASK, /*!< HSM WDOG Request Enable to FCSMU */ + CSC_SMU_FMC_ERR = (int)CSC0_SMU_CTRL4_FMC_ERR_MASK, /*!< FMC ECC Error Enable to FCSMU */ + CSC_SMU_ROM_S_EN = (int)CSC0_SMU_CTRL4_ROM_S_EN_MASK, /*!< ROM Single Bit Data Error Enable to FCSMU */ + CSC_SMU_SRAM1_EDC_MON_EN = (int)CSC0_SMU_CTRL4_SRAM1_EDC_MON_EN_MASK, /*!< SRAM1_EDC Monitor Error Enable to FCSMU */ + CSC_SMU_SRAM0_EDC_MON_EN = (int)CSC0_SMU_CTRL4_SRAM0_EDC_MON_EN_MASK, /*!< SRAM0_EDC Monitor Error Enable to FCSMU */ + CSC_SMU_SRAM1_S_EN = (int)CSC0_SMU_CTRL4_SRAM1_S_EN_MASK, /*!< SRAM1 Single Bit Data Error Enable to FCSMU */ + CSC_SMU_SRAM0_S_EN = (int)CSC0_SMU_CTRL4_SRAM0_S_EN_MASK, /*!< SRAM0 Single Bit Data Error Enable to FCSMU */ + CSC_SMU_FLASH_ECC_EN_S = (int)CSC0_SMU_CTRL4_FLASH_ECC_EN_S_MASK, /*!< FLASH Single Bit Error Enable to FCSMU */ + CSC_SMU_FLASH_ECC_EN = (int)CSC0_SMU_CTRL4_FLASH_ECC_EN_MASK, /*!< FLASH ECC Error Enable to FCSMU */ + CSC_SMU_AFCB1_MON = (int)CSC0_SMU_CTRL4_AFCB1_MON_MASK, /*!< AFCB1 Monitor Error Enable to FCSMU */ + CSC_SMU_AFCB0_MON = (int)CSC0_SMU_CTRL4_AFCB0_MON_MASK, /*!< AFCB0 Monitor Error Enable to FCSMU */ + CSC_SMU_SCF_RST = (int)CSC0_SMU_CTRL4_SCF_RST_EN_MASK, /*!< Self Check Feature Enable */ + CSC_SMU_SCF_IRQ = (int)CSC0_SMU_CTRL4_SCF_IRQ_EN_MASK, /*!< Self Check Feature Interrupt Request Enable */ + CSC_SMU_TMU = (int)CSC0_SMU_CTRL4_TMU_MASK, /*!< TMU Error Enable to FCSMU */ + CSC_SMU_SCM_CRC = (int)CSC0_SMU_CTRL4_SCM_CRC_MASK, /*!< SCM CRC Error Enable to FCSMU */ + CSC_SMU_SCG_CRC = (int)CSC0_SMU_CTRL4_SCG_CRC_MASK, /*!< SCG CRC Error Enable to FCSMU */ + CSC_SMU_SRAM1_ECC = (int)CSC0_SMU_CTRL4_SRAM1_ECC_MASK, /*!< SRAM1 ECC Error Enable to FCSMU */ + CSC_SMU_SRAM0_ECC = (int)CSC0_SMU_CTRL4_SRAM0_ECC_MASK, /*!< SRAM0 ECC Error Enable to FCSMU */ + CSC_SMU_MAM0_ERR = (int)CSC0_SMU_CTRL4_MAM0_ERR_MASK /*!< Matrix Access Monitor 0 Timeout Error Enable to FCSMU */ +} CSC_SMU_CtrlGrp4Type; + +/** + * @brief CSC0 SMU control group 5 + */ +typedef enum +{ + CSC_SMU_SRAM1_EDC = (int)CSC0_SMU_CTRL5_SRAM1_EDC_MASK, /*!< SRAM1 EDC Error Enable to FCSMU */ + CSC_SMU_SRAM0_EDC = (int)CSC0_SMU_CTRL5_SRAM0_EDC_MASK, /*!< SRAM0 EDC Error Enable to FCSMU */ + CSC_SMU_FLASH_EDC_P1_EN = (int)CSC0_SMU_CTRL5_FLASH_EDC_P1_EN_MASK,/*!< FLASH P1 EDC Error Enable to FCSMU */ + CSC_SMU_FLASH_EDC_P0_EN = (int)CSC0_SMU_CTRL5_FLASH_EDC_P0_EN_MASK,/*!< FLASH P0 EDC Error Enable to FCSMU */ + CSC_SMU_HSM_IRAM_S = (int)CSC0_SMU_CTRL5_HSM_IRAM_S_MASK, /*!< HSM IRAM Single Bit Data Error Enable to FCSMU */ + CSC_SMU_HSM_DRAM_S = (int)CSC0_SMU_CTRL5_HSM_DRAM_S_MASK, /*!< HSM DRAM Single Bit Data Error Enable to FCSMU */ + CSC_SMU_HSM_IRAM = (int)CSC0_SMU_CTRL5_HSM_IRAM_MASK, /*!< HSM IRAM ECC Error Enable to FCSMU */ + CSC_SMU_HSM_DRAM = (int)CSC0_SMU_CTRL5_HSM_DRAM_MASK, /*!< HSM DRAM ECC Error Enable to FCSMU */ + CSC_SMU_DMA0_ECC_S = (int)CSC0_SMU_CTRL5_DMA0_ECC_S_MASK, /*!< DMA0_CFG_ECC Single Bit Data Error Enable to FCSMU */ + CSC_SMU_DMA0_ECC = (int)CSC0_SMU_CTRL5_DMA0_ECC_MASK, /*!< DMA0 CFG ECC Error Enable to FCSMU */ + CSC_SMU_DMA0_LOCKSTEP = (int)CSC0_SMU_CTRL5_DMA0_LOCKSTEP_MASK, /*!< DMA0 lockstep Error Enable to FCSMU */ + CSC_SMU_FOSC_ERR = (int)CSC0_SMU_CTRL5_FOSC_ERR_MASK, /*!< FOSC Loss of Clock Error Enable to FCSMU */ + CSC_SMU_PLL1_ERR = (int)CSC0_SMU_CTRL5_PLL1_ERR_MASK, /*!< PLL1 Loss of Clock Error Enable to FCSMU */ + CSC_SMU_PLL0_ERR = (int)CSC0_SMU_CTRL5_PLL0_ERR_MASK, /*!< PLL0 Loss of Clock Error Enable to FCSMU */ + CSC_SMU_STCU_ERR = (int)CSC0_SMU_CTRL5_STCU_ERR_MASK, /*!< STCU Self Test Error Enable to FCSMU */ + CSC_SMU_NONUSER_ERR = (int)CSC0_SMU_CTRL5_NONUSER_ERR_MASK, /*!< STCU Non User Error Enable to FCSMU */ + CSC_SMU_NVR_ERR = (int)CSC0_SMU_CTRL5_NVR_ERR_MASK, /*!< NVR Error Enable to FCSMU */ +} CSC_SMU_CtrlGrp5Type; + +/** + * @brief CSC0 CMU control group + */ +typedef enum +{ + CSC_CMU_DMA0_CFG_S_EN_ADDR = (int)CSC0_CMU_CTRL_DMA0_CFG_S_EN_ADDR_MASK,/*!< Enable to Report Single Error When One Bit Address_ECC Error Inject */ + CSC_CMU_CMU3_FCSMU_RST = (int)CSC0_CMU_CTRL_CMU3_FCSMU_RST_MASK, /*!< CMU3 clcok error to assert reset request to RGM to reset System and FCSMU */ + CSC_CMU_CMU3_RST = (int)CSC0_CMU_CTRL_CMU3_RST_EN_MASK, /*!< CMU3 clock error to assert reset request to RGM to reset System */ + CSC_CMU_CMU4_LOC = (int)CSC0_CMU_CTRL_CMU4_LOC_EN_MASK /*!< Enable CMU4 Loss of clock error request to SCG */ +} CSC0_CMU_CtrlGrpType; + +/** + * @brief CSC0 Low Power Wakeup configuration group type + */ +typedef enum +{ + CSC_LP_WAKEUP_GROUP_0 = 0U, /*!< CSC0 Low Power Wakeup configuration group0 */ + CSC_LP_WAKEUP_GROUP_1 = 1U, /*!< CSC0 Low Power Wakeup configuration group1 */ + CSC_LP_WAKEUP_GROUP_2 = 2U, /*!< CSC0 Low Power Wakeup configuration group2 */ + CSC_LP_WAKEUP_GROUP_3 = 3U, /*!< CSC0 Low Power Wakeup configuration group3 */ + CSC_LP_WAKEUP_GROUP_4 = 4U /*!< CSC0 Low Power Wakeup configuration group4 */ +} CSC0_LPWakeupGrpType; + +/** + * @brief CSC0 Low Power Wakeup configuration source type + */ +typedef enum +{ + CSC_LP_WAKEUP_DISABLE = 0U, /*!< Disable */ + CSC_LP_WAKEUP_AONTIMER_TRIGGER = 1U, /*!< AONTIMER Trigger */ + CSC_LP_WAKEUP_RTC_TIME_ALARM = 2U, /*!< RTC Time Alarm */ + CSC_LP_WAKEUP_CPM0_OUTPUT = 3U, /*!< CPM0 output */ + CSC_LP_WAKEUP_CPM1_OUTPUT = 4U, /*!< CPM1 output */ + CSC_LP_WAKEUP_RESERVED = 5U, /*!< Reserved */ + CSC_LP_WAKEUP_PMC_RPM_ENTRY = 6U, /*!< PMC RPM Entry */ + CSC_LP_WAKEUP_WKU_INTERRUPT = 7U, /*!< WKU Interrupt */ + CSC_LP_WAKEUP_TSTMP0_PWM_TRIGGER0 = 8U, /*!< TSTMP0 PWM TRIGGER0 */ + CSC_LP_WAKEUP_TSTMP0_PWM_TRIGGER1 = 9U, /*!< TSTMP0 PWM TRIGGER1 */ + CSC_LP_WAKEUP_FCPIT0_PWM_TRIGGER0 = 10U, /*!< FCPT0 PWM TRIGGER0 */ + CSC_LP_WAKEUP_FCPIT0_PWM_TRIGGER1 = 11U, /*!< FCPT0 PWM TRIGGER1 */ + CSC_LP_WAKEUP_FCPIT0_TRIGGER_OUT0 = 12U, /*!< FCPIT0 Trigger out[0] */ + CSC_LP_WAKEUP_FCPIT0_TRIGGER_OUT1 = 13U, /*!< FCPIT0 Trigger out[1] */ + CSC_LP_WAKEUP_FCPIT0_TRIGGER_OUT2 = 14U, /*!< FCPIT0 Trigger out[2] */ + CSC_LP_WAKEUP_FCPIT0_TRIGGER_OUT3 = 15U /*!< FCPIT0 Trigger out[3] */ +} CSC0_LPWakeupSrcType; + +/** + * @brief CSC0 Low Power Wakeup polarity type + */ +typedef enum +{ + CSC_LP_WAKEUP_POL_KEEP = 0U, /*!< Keep the LP_WAKEUP CFGx */ + CSC_LP_WAKEUP_POL_INVERT = 1U, /*!< Invert the LP_WAKEUP CFGx */ +} CSC0_LPWakeupPolType; + + +/********* Local inline function ************/ +/****** Operation on CSC0_xxxRegister0 ******/ +/** + * @brief Lock the cpu to control stop mode register 0 + * + */ +LOCAL_INLINE void CSC0_HWA_MODER0_LockWritePermit(void) +{ + CSC0->STOP_MODER0 |= (uint32_t)CSC0_STOP_MODER0_WPB_LOCK_MASK; +} + +/** + * @brief Get the stop mode register 0 lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_MODER0_GetWPBLockStatus(void) +{ + return (CSC0->STOP_MODER0 & (uint32_t)CSC0_STOP_MODER0_WPB_LOCK_MASK); +} + +/** + * @brief Get the CPU type of writing permission + * + * @return CSC_WPB_CpuType The CPU which has the write permission + */ +LOCAL_INLINE CSC_WPB_CpuType CSC0_HWA_MODER0_GetCpuWritePermit(void) +{ + uint32_t u32RegVal = ((CSC0->STOP_MODER0 & (uint32_t)CSC0_STOP_MODER0_WPB_MASK)>>CSC0_STOP_MODER0_WPB_SHIFT); + return (CSC_WPB_CpuType)u32RegVal; +} + +/** + * @brief Set cpu to control this stop mode register 0 + * + * @param eCpuType Cpu allowed to control peripheral + */ +LOCAL_INLINE void CSC0_HWA_MODER0_SetCpuWritePermit(CSC_WPB_CpuType eCpuType) +{ + uint32_t u32RegVal = CSC0->STOP_MODER0; + CSC0->STOP_MODER0 = ((u32RegVal & (~(uint32_t)CSC0_STOP_MODER0_WPB_MASK)) | CSC0_STOP_MODER0_WPB(eCpuType)); +} + +/** + * @brief Enable the stop acknowledge function of register 0 group + * + * @param ePeriphType Peripheral to be set + */ +LOCAL_INLINE void CSC0_HWA_MODER0_EnableStopAck(CSCx_Reg0_PeriphType ePeriphType) +{ + CSC0->STOP_MODER0 |= (uint32_t)ePeriphType; +} + +/** + * @brief Disable the stop acknowledge function of register 0 group + * + * @param ePeriphType Peripheral to be set + */ +LOCAL_INLINE void CSC0_HWA_MODER0_DisableStopAck(CSCx_Reg0_PeriphType ePeriphType) +{ + CSC0->STOP_MODER0 &= ~(uint32_t)ePeriphType; +} + +/** + * @brief Set multiple stop ack enable/disable value + * + * @param u32Value the OR value of type CSCx_Reg0_PeriphType + */ +LOCAL_INLINE void CSC0_HWA_MODER0_SetMultiStopAck(uint32_t u32Value) +{ + CSC0->STOP_MODER0 = u32Value; +} + +/** + * @brief Clear multiple stop ack enable/disable value + * + * @param u32Value the OR value of type CSCx_Reg0_PeriphType + */ +LOCAL_INLINE void CSC0_HWA_MODER0_ClearMultiStopAck(uint32_t u32Value) +{ + CSC0->STOP_MODER0 = (CSC0->STOP_MODER0 & (~u32Value)); +} + +/** + * @brief Lock the cpu to control this stop request register 0 + * + * @param eLockType Cpu lock type + */ +LOCAL_INLINE void CSC0_HWA_REQR0_LockWritePermit(void) +{ + CSC0->STOP_REQR0 |= (uint32_t)CSC0_STOP_REQR0_WPB_LOCK_MASK; +} + +/** + * @brief Get the stop request register 0 lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_REQR0_GetWPBLockStatus(void) +{ + return (CSC0->STOP_REQR0 & (uint32_t)CSC0_STOP_REQR0_WPB_LOCK_MASK); +} + +/** + * @brief Get the CPU type of writing permission + * + * @return CSC_WPB_CpuType The CPU which has the write permission + */ +LOCAL_INLINE CSC_WPB_CpuType CSC0_HWA_REQR0_GetCpuWritePermit(void) +{ + uint32_t u32RegVal = ((CSC0->STOP_REQR0 & (uint32_t)CSC0_STOP_REQR0_WPB_MASK)>>CSC0_STOP_REQR0_WPB_SHIFT); + return (CSC_WPB_CpuType)u32RegVal; +} + +/** + * @brief Set cpu to control stop request register 0 + * + * @param eCpuType Cpu allowed to control peripheral + */ +LOCAL_INLINE void CSC0_HWA_REQR0_SetCpuWritePermit(CSC_WPB_CpuType eCpuType) +{ + uint32_t u32RegVal = CSC0->STOP_REQR0; + CSC0->STOP_REQR0 = ((u32RegVal & (~(uint32_t)CSC0_STOP_REQR0_WPB_MASK)) | CSC0_STOP_REQR0_WPB(eCpuType)); +} + +/** + * @brief Set stop request in register 0 + * + * @param ePeriphType Peripheral to be set + */ +LOCAL_INLINE void CSC0_HWA_REQR0_SetStopRequest(CSCx_Reg0_PeriphType ePeriphType) +{ + CSC0->STOP_REQR0 |= (uint32_t)ePeriphType; +} + +/** + * @brief Clear stop request in register 0 + * + * @param ePeriphType Peripheral to be cleared + */ +LOCAL_INLINE void CSC0_HWA_REQR0_ClearStopRequest(CSCx_Reg0_PeriphType ePeriphType) +{ + CSC0->STOP_REQR0 &= ~(uint32_t)ePeriphType; +} + +/** + * @brief Set multiple stop request enable/disable value + * + * @param u32Value the OR value of type CSCx_Reg0_PeriphType + */ +LOCAL_INLINE void CSC0_HWA_REQR0_SetMultiStopRequest(uint32_t u32Value) +{ + CSC0->STOP_REQR0 = u32Value; +} + +/** + * @brief Clear stop request in register 0 + * + * @param u32Value the OR value of type CSCx_Reg0_PeriphType + */ +LOCAL_INLINE void CSC0_HWA_REQR0_ClearMultiStopRequest(uint32_t u32Value) +{ + CSC0->STOP_REQR0 = (CSC0->STOP_REQR0 & (~u32Value)); +} + +/** + * @brief Get stop ack status in register 0 + * + * @param u32Value value to be set + * @return Stop ack status + */ +LOCAL_INLINE uint32_t CSC0_HWA_ACKR0_GetStopAckStatus(CSCx_Reg0_PeriphType ePeriphType) +{ + return (CSC0->STOP_ACKR0 & ((uint32_t)ePeriphType)); +} + +/** + * @brief Get multiple stop ack status in register 0 + * + * @param u32Value the OR value of type CSCx_Reg0_PeriphType + * @return Stop ack status + */ +LOCAL_INLINE uint32_t CSC0_HWA_ACKR0_GetMultiStopAckStatus(uint32_t u32Value) +{ + return (CSC0->STOP_ACKR0 & u32Value); +} + + + +/****** Operation on CSC0_xxxRegister1 ******/ +/** + * @brief Lock the cpu to control stop mode register 1 + * + */ +LOCAL_INLINE void CSC0_HWA_MODER1_LockWritePermit(void) +{ + CSC0->STOP_MODER1 |= (uint32_t)CSC0_STOP_MODER1_WPB_LOCK_MASK; +} + +/** + * @brief Get the stop mode register 1 lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_MODER1_GetWPBLockStatus(void) +{ + return (CSC0->STOP_MODER1 & (uint32_t)CSC0_STOP_MODER1_WPB_LOCK_MASK); +} + +/** + * @brief Set cpu to control this stop mode register 1 + * + * @param eCpuType Cpu allowed to control peripheral + */ +LOCAL_INLINE void CSC0_HWA_MODER1_SetCpuWritePermit(CSC_WPB_CpuType eCpuType) +{ + uint32_t u32RegVal = CSC0->STOP_MODER1; + CSC0->STOP_MODER1 = ((u32RegVal & (~(uint32_t)CSC0_STOP_MODER1_WPB_MASK)) | CSC0_STOP_MODER1_WPB(eCpuType)); +} + +/** + * @brief Get the CPU type of writing permission + * + * @return CSC_WPB_CpuType The Cpu which has the write permission + */ +LOCAL_INLINE CSC_WPB_CpuType CSC0_HWA_MODER1_GetCpuWritePermit(void) +{ + uint32_t u32RegVal = ((CSC0->STOP_MODER1 & (uint32_t)CSC0_STOP_MODER1_WPB_MASK)>>CSC0_STOP_MODER1_WPB_SHIFT); + return (CSC_WPB_CpuType)u32RegVal; +} + +/** + * @brief Enable the stop acknowledge function of register 1 group + * + * @param ePeriphType Peripheral to be set + */ +LOCAL_INLINE void CSC0_HWA_MODER1_EnableStopAck(CSCx_Reg1_PeriphType ePeriphType) +{ + CSC0->STOP_MODER1 |= (uint32_t)ePeriphType; +} + +/** + * @brief Disable the stop acknowledge function of register 1 group + * + * @param ePeriphType Peripheral to be set + */ +LOCAL_INLINE void CSC0_HWA_MODER1_DisableStopAck(CSCx_Reg1_PeriphType ePeriphType) +{ + CSC0->STOP_MODER1 &= ~(uint32_t)ePeriphType; +} + +/** + * @brief Set multiple stop ack enable/disable value + * + * @param u32Value the OR value of type CSCx_Reg1_PeriphType + */ +LOCAL_INLINE void CSC0_HWA_MODER1_SetMultiStopAck(uint32_t u32Value) +{ + CSC0->STOP_MODER1 = u32Value; +} + +/** + * @brief Clear multiple stop ack enable/disable value + * + * @param u32Value the OR value of type CSCx_Reg1_PeriphType + */ +LOCAL_INLINE void CSC0_HWA_MODER1_ClearMultiStopAck(uint32_t u32Value) +{ + CSC0->STOP_MODER1 = (CSC0->STOP_MODER1 & (~u32Value)); +} + +/** + * @brief Lock the cpu to control this stop request register 1 + * + */ +LOCAL_INLINE void CSC0_HWA_REQR1_LockWritePermit(void) +{ + CSC0->STOP_REQR1 |= (uint32_t)CSC0_STOP_REQR1_WPB_LOCK_MASK; +} + +/** + * @brief Get the stop request register 1 lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_REQR1_GetWPBLockStatus(void) +{ + return (CSC0->STOP_REQR1 & (uint32_t)CSC0_STOP_REQR1_WPB_LOCK_MASK); +} + +/** + * @brief Get the CPU type of writing permission + * + * @return CSC_WPB_CpuType CPU type which has the write permission + */ +LOCAL_INLINE CSC_WPB_CpuType CSC0_HWA_REQR1_GetCpuWritePermit(void) +{ + uint32_t u32RegVal = ((CSC0->STOP_REQR1 & (uint32_t)CSC0_STOP_REQR1_WPB_MASK)>>CSC0_STOP_REQR1_WPB_SHIFT); + return (CSC_WPB_CpuType)u32RegVal; +} + +/** + * @brief Set cpu to control stop request register 1 + * + * @param eCpuType Cpu allowed to control peripheral + */ +LOCAL_INLINE void CSC0_HWA_REQR1_SetCpuWritePermit(CSC_WPB_CpuType eCpuType) +{ + uint32_t u32RegVal = CSC0->STOP_REQR1; + CSC0->STOP_REQR1 |= ((u32RegVal & (~(uint32_t)CSC0_STOP_REQR1_WPB_MASK)) | CSC0_STOP_REQR1_WPB(eCpuType)); +} + +/** + * @brief Set stop request in register 1 + * + * @param ePeriphType Peripheral to be set + */ +LOCAL_INLINE void CSC0_HWA_REQR1_SetStopRequest(CSCx_Reg1_PeriphType ePeriphType) +{ + CSC0->STOP_REQR1 |= (uint32_t)ePeriphType; +} + +/** + * @brief Clear stop request in register 1 + * + * @param ePeriphType Peripheral to be cleared + */ +LOCAL_INLINE void CSC0_HWA_REQR1_ClearStopRequest(CSCx_Reg1_PeriphType ePeriphType) +{ + CSC0->STOP_REQR1 &= ~(uint32_t)ePeriphType; +} + +/** + * @brief Set multiple stop request enable/disable value + * + * @param u32Value the OR value of type CSCx_Reg1_PeriphType + */ +LOCAL_INLINE void CSC0_HWA_REQR1_SetMultiStopRequest(uint32_t u32Value) +{ + CSC0->STOP_REQR1 = u32Value; +} + +/** + * @brief Clear multiple stop request in register 0 + * + * @param u32Value the OR value of type CSCx_Reg1_PeriphType + */ +LOCAL_INLINE void CSC0_HWA_REQR1_ClearMultiStopRequest(uint32_t u32Value) +{ + CSC0->STOP_REQR1 = (CSC0->STOP_REQR1 & (~u32Value)); +} + +/** + * @brief Get stop ack status in register 1 + * + * @param u32Value value to be set + * @return Stop ack status + */ +LOCAL_INLINE uint32_t CSC0_HWA_ACKR1_GetStopAckStatus(CSCx_Reg1_PeriphType ePeriphType) +{ + return (CSC0->STOP_ACKR1 & (uint32_t)ePeriphType); +} + +/** + * @brief Get multiple stop ack status in register 1 + * + * @param u32Value the OR value of type CSCx_Reg1_PeriphType + * @return Stop ack status + */ +LOCAL_INLINE uint32_t CSC0_HWA_ACKR1_GetMultiStopAckStatus(uint32_t u32Value) +{ + return (CSC0->STOP_ACKR1 & u32Value); +} + +/****** Operation on CSC0_xxxRegister2 ******/ +/** + * @brief Lock the cpu to control stop mode register 2 + * + */ +LOCAL_INLINE void CSC0_HWA_MODER2_LockWritePermit(void) +{ + CSC0->STOP_MODER2 |= (uint32_t)CSC0_STOP_MODER2_WPB_LOCK_MASK; +} + +/** + * @brief Get the stop mode register 2 lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_MODER2_GetWPBLockStatus(void) +{ + return (CSC0->STOP_MODER2 & (uint32_t)CSC0_STOP_MODER2_WPB_LOCK_MASK); +} + +/** + * @brief Set cpu to control this stop mode register 2 + * + * @param eCpuType Cpu allowed to control peripheral + */ +LOCAL_INLINE void CSC0_HWA_MODER2_SetCpuWritePermit(CSC_WPB_CpuType eCpuType) +{ + uint32_t u32RegVal = CSC0->STOP_MODER2; + CSC0->STOP_MODER2 = ((u32RegVal & (~(uint32_t)CSC0_STOP_MODER2_WPB_MASK)) | CSC0_STOP_MODER2_WPB(eCpuType)); +} + +/** + * @brief Get the CPU type of writing permission + * + * @return CSC_WPB_CpuType The Cpu which has the write permission + */ +LOCAL_INLINE CSC_WPB_CpuType CSC0_HWA_MODER2_GetCpuWritePermit(void) +{ + uint32_t u32RegVal = ((CSC0->STOP_MODER2 & (uint32_t)CSC0_STOP_MODER2_WPB_MASK)>>CSC0_STOP_MODER2_WPB_SHIFT); + return (CSC_WPB_CpuType)u32RegVal; +} + + +/** + * @brief Enable the stop acknowledge function of register 2 group + * + * @param ePeriphType Peripheral to be set + */ +LOCAL_INLINE void CSC0_HWA_MODER2_EnableStopAck(CSCx_Reg2_PeriphType ePeriphType) +{ + CSC0->STOP_MODER2 |= (uint32_t)ePeriphType; +} + +/** + * @brief Disable the stop acknowledge function of register 1 group + * + * @param ePeriphType Peripheral to be set + */ +LOCAL_INLINE void CSC0_HWA_MODER2_DisableStopAck(CSCx_Reg2_PeriphType ePeriphType) +{ + CSC0->STOP_MODER2 &= ~(uint32_t)ePeriphType; +} + +/** + * @brief Set multiple stop ack enable/disable value + * + * @param u32Value value to be set + */ +LOCAL_INLINE void CSC0_HWA_MODER2_SetMultiStopAck(uint32_t u32Value) +{ + CSC0->STOP_MODER2 = u32Value; +} + +/** + * @brief Clear multiple stop ack enable/disable value + * + * @param u32Value value to be set + */ +LOCAL_INLINE void CSC0_HWA_MODER2_ClearMultiStopAck(uint32_t u32Value) +{ + CSC0->STOP_MODER2 = (CSC0->STOP_MODER2 & (~u32Value)); +} + +/** + * @brief Lock the cpu to control this stop request register 2 + * + */ +LOCAL_INLINE void CSC0_HWA_REQR2_LockWritePermit(void) +{ + CSC0->STOP_REQR2 |= (uint32_t)CSC0_STOP_REQR2_WPB_LOCK_MASK; +} + +/** + * @brief Get the stop request register 2 lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_REQR2_GetWPBLockStatus(void) +{ + return (CSC0->STOP_REQR2 & (uint32_t)CSC0_STOP_REQR2_WPB_LOCK_MASK); +} + +/** + * @brief Set cpu to control stop request register 2 + * + * @param eCpuType Cpu allowed to control peripheral + */ +LOCAL_INLINE void CSC0_HWA_REQR2_SetCpuWritePermit(CSC_WPB_CpuType eCpuType) +{ + uint32_t u32RegVal = CSC0->STOP_REQR2; + CSC0->STOP_REQR2 = ((u32RegVal & (~(uint32_t)CSC0_STOP_REQR2_WPB_MASK)) | CSC0_STOP_REQR2_WPB(eCpuType)); +} + +/** + * @brief Get the CPU type of writing permission + * + * @return CSC_WPB_CpuType The Cpu which has the write permission + */ +LOCAL_INLINE CSC_WPB_CpuType CSC0_HWA_REQR2_GetCpuWritePermit(void) +{ + uint32_t u32RegVal = ((CSC0->STOP_REQR2 & (uint32_t)CSC0_STOP_REQR2_WPB_MASK)>>CSC0_STOP_REQR2_WPB_SHIFT); + return (CSC_WPB_CpuType)u32RegVal; +} + + +/** + * @brief Set stop request in register 2 + * + * @param ePeriphType Peripheral to be set + */ +LOCAL_INLINE void CSC0_HWA_REQR2_SetStopRequest(CSCx_Reg2_PeriphType ePeriphType) +{ + CSC0->STOP_REQR2 |= (uint32_t)ePeriphType; +} + +/** + * @brief Clear stop request in register 2 + * + * @param ePeriphType Peripheral to be cleared + */ +LOCAL_INLINE void CSC0_HWA_REQR2_ClearStopRequest(CSCx_Reg2_PeriphType ePeriphType) +{ + CSC0->STOP_REQR2 &= ~(uint32_t)ePeriphType; +} + +/** + * @brief Set multiple stop request enable/disable value + * + * @param u32Value the OR value of type CSCx_Reg2_PeriphType + */ +LOCAL_INLINE void CSC0_HWA_REQR2_SetMultiStopRequest(uint32_t u32Value) +{ + CSC0->STOP_REQR2 = u32Value; +} + +/** + * @brief Clear multiple stop request in register 0 + * + * @param u32Value the OR value of type CSCx_Reg2_PeriphType + */ +LOCAL_INLINE void CSC0_HWA_REQR2_ClearMultiStopRequest(uint32_t u32Value) +{ + CSC0->STOP_REQR2 = (CSC0->STOP_REQR2 & (~u32Value)); +} + +/** + * @brief Get stop ack status in register 2 + * + * @param u32Value value to be set + * @return Stop ack status + */ +LOCAL_INLINE uint32_t CSC0_HWA_ACKR2_GetStopAckStatus(CSCx_Reg2_PeriphType ePeriphType) +{ + return (CSC0->STOP_ACKR2 & (uint32_t)ePeriphType); +} + +/** + * @brief Get multiple stop ack status in register 2 + * + * @param u32Value the OR value of type CSCx_Reg2_PeriphType + * @return Stop ack status + */ +LOCAL_INLINE uint32_t CSC0_HWA_ACKR2_GetMultiStopAckStatus(uint32_t u32Value) +{ + return (CSC0->STOP_ACKR2 & u32Value); +} + +/** + * @brief Lock the cpu to control CCM0 register + * + */ +LOCAL_INLINE void CSC0_HWA_CCM0_LockWritePermit(void) +{ + CSC0->CCM0_CFG |= (uint32_t)CSC0_CCM0_CFG_WPB_LOCK_MASK; +} + +/** + * @brief Unlock the cpu to control CCM0 register + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_CCM0_GetWPBLockStatus(void) +{ + return (CSC0->CCM0_CFG & (uint32_t)CSC0_CCM0_CFG_WPB_LOCK_MASK); +} + +/** + * @brief Get the CPU type of writing permission + * + * @param CSC_WPB_CpuType The Cpu which has the write permission + */ +LOCAL_INLINE CSC_WPB_CpuType CSC0_HWA_CCM0_GetCpuWritePermit(void) +{ + uint32_t u32RegVal = (CSC0->CCM0_CFG & CSC0_CCM0_CFG_WPB_MASK) >> CSC0_CCM0_CFG_WPB_SHIFT; + return (CSC_WPB_CpuType)u32RegVal; +} + +/** + * @brief Set cpu to control this CCM0 register + * + * @param eCpuType Cpu allowed to control peripheral + */ +LOCAL_INLINE void CSC0_HWA_CCM0_SetCpuWritePermit(CSC_WPB_CpuType eCpuType) +{ + uint32_t u32RegVal = CSC0->CCM0_CFG; + CSC0->CCM0_CFG = ((u32RegVal & (~(uint32_t)CSC0_CCM0_CFG_WPB_MASK)) | CSC0_CCM0_CFG_WPB(eCpuType)); +} + +/** + * @brief Force enable HClock of cpu 0 + * + */ +LOCAL_INLINE bool CSC0_HWA_GetHClockEnFlag(void) +{ + return (bool)((CSC0->CCM0_CFG & CSC0_CCM0_CFG_CPU0_FORCE_HCLKEN_MASK) != 0U); +} + +/** + * @brief Force enable HClock of cpu 0 + * + */ +LOCAL_INLINE void CSC0_HWA_HClockEnable(bool bEnable) +{ + CSC0->CCM0_CFG = (CSC0->CCM0_CFG & (~(uint32_t)CSC0_CCM0_CFG_CPU0_FORCE_HCLKEN_MASK)) | + CSC0_CCM0_CFG_CPU0_FORCE_HCLKEN(bEnable); +} + +/** + * @brief Get CCM0 hand shake mode + * + * @param eHandShakeType CCM0 hand shake mode + */ +LOCAL_INLINE CSC_HandShakeModeType CSC0_HWA_GetHandShakeMode(void) +{ + uint32_t u32RegVal = (CSC0->CCM0_CFG & CSC0_CCM0_CFG_CCM0_HANDSHAKE_MODE_MASK) >> CSC0_CCM0_CFG_CCM0_HANDSHAKE_MODE_SHIFT; + return (CSC_HandShakeModeType)u32RegVal; +} + +/** + * @brief Set CCM0 hand shake mode + * + * @param eHandShakeType CCM0 hand shake mode + */ +LOCAL_INLINE void CSC0_HWA_SetHandShakeMode(CSC_HandShakeModeType eHandShakeType) +{ + uint32_t u32RegVal = CSC0->CCM0_CFG; + CSC0->CCM0_CFG = ((u32RegVal & (~(uint32_t)CSC0_CCM0_CFG_CCM0_HANDSHAKE_MODE_MASK)) | CSC0_CCM0_CFG_CCM0_HANDSHAKE_MODE(eHandShakeType)); +} + +/** + * @brief Get CCM0 clock status + * + * @param eStopClockType CCM0 stop clock type + * @return CCM0 clock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_CCM0_GetClockStatus(CSCx_CCM_StopClockType eStopClockType) +{ + return (CSC0->CCM0_STATUS & (uint32_t)eStopClockType); +} + +/** + * @brief Enable SCG MAM stall + * + */ +LOCAL_INLINE void CSC0_HWA_EnalbeSCGStall(void) +{ + CSC0->SCG_MAM_STALL |= (uint32_t)CSC0_SCG_MAM_STALL_SCG_STALL_MASK; +} + +/** + * @brief Disable SCG MAM stall + * + */ +LOCAL_INLINE void CSC0_HWA_DisableSCGStall(void) +{ + CSC0->SCG_MAM_STALL &= ~(uint32_t)CSC0_SCG_MAM_STALL_SCG_STALL_MASK; +} + +/** + * @brief Lock SCG_MAM_STALL register status + * + */ +LOCAL_INLINE void CSC0_HWA_LockSCG_MAM_STALL(void) +{ + CSC0->SCG_MAM_STALL |= (uint32_t)CSC0_SCG_MAM_STALL_LOCK_MASK; +} + +/** + * @brief Get SCG_MAM_STALL register lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_SCG_MAM_STALL_GetLockStatus(void) +{ + return (CSC0->SCG_MAM_STALL & (uint32_t)CSC0_SCG_MAM_STALL_LOCK_MASK); +} + +/** + * @brief Lock the cpu to control CPU0_INT register + * + */ +LOCAL_INLINE void CSC0_HWA_CPU0INT_LockWritePermit(void) +{ + CSC0->CPU0_INT |= (uint32_t)CSC0_CPU0_INT_WPB_LOCK_MASK; +} + +/** + * @brief Get CPU0_INT register WPB lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_CPU0INT_GetWPBLockStatus(void) +{ + return (CSC0->CPU0_INT & (uint32_t)CSC0_CPU0_INT_WPB_LOCK_MASK); +} + +/** + * @brief Get the CPU type of writing permission + * + * @param CSC_WPB_CpuType The Cpu which has the write permission + */ +LOCAL_INLINE CSC_WPB_CpuType CSC0_HWA_CPU0INT_GetCpuWritePermit(void) +{ + uint32_t u32RegVal = (CSC0->CPU0_INT & CSC0_CPU0_INT_WPB_MASK) >> CSC0_CPU0_INT_WPB_SHIFT; + return (CSC_WPB_CpuType)u32RegVal; +} + +/** + * @brief Set cpu to control this CPU0_INT register + * + * @param eCpuType Cpu allowed to control peripheral + */ +LOCAL_INLINE void CSC0_HWA_CPU0INT_SetCpuWritePermit(CSC_WPB_CpuType eCpuType) +{ + uint32_t u32RegVal = CSC0->CPU0_INT; + CSC0->CPU0_INT = ((u32RegVal & (~(uint32_t)CSC0_CPU0_INT_WPB_MASK)) | CSC0_CPU0_INT_WPB(eCpuType)); +} + +/** + * @brief Enable cpu0 software interrupt + * + */ +LOCAL_INLINE void CSC0_HWA_CPU0INT_EnableSWInterrupt(void) +{ + CSC0->CPU0_INT |= (uint32_t)CSC0_CPU0_INT_SW_INT_MASK; +} + +/** + * @brief Disable cpu0 software interrupt + * + */ +LOCAL_INLINE void CSC0_HWA_CPU0INT_DisableSWInterrupt(void) +{ + CSC0->CPU0_INT &= ~(uint32_t)CSC0_CPU0_INT_SW_INT_MASK; +} + +/** + * @brief Enable CSC0 clock out + * + */ +LOCAL_INLINE void CSC0_HWA_EnableClockOut(void) +{ + CSC0->CLKOUT_CTRL |= (uint32_t)CSC0_CLKOUT_CTRL_CLKOUT_EN_MASK; +} + +/** + * @brief Disable CSC0 clock out + * + */ +LOCAL_INLINE void CSC0_HWA_DisableClockOut(void) +{ + CSC0->CLKOUT_CTRL &= ~(uint32_t)CSC0_CLKOUT_CTRL_CLKOUT_EN_MASK; +} + +/** + * @brief Get CLKOUT CSC0 clock out divider + * + * @return CSC0_ClockOutDivType CSC0 clock out divider + */ +LOCAL_INLINE CSC0_ClockOutDivType CSC0_HWA_GetClkOutDiv(void) +{ + uint32_t u32RegVal = (CSC0->CLKOUT_CTRL & CSC0_CLKOUT_CTRL_CLKOUT_DIV_MASK) >> CSC0_CLKOUT_CTRL_CLKOUT_DIV_SHIFT; + return (CSC0_ClockOutDivType)u32RegVal; +} + +/** + * @brief Set CLKOUTDIV + * + * @param eDivType CSC0 clock out divider + */ +LOCAL_INLINE void CSC0_HWA_SetClkOutDiv(CSC0_ClockOutDivType eDivType) +{ + uint32_t u32RegVal = CSC0->CLKOUT_CTRL; + CSC0->CLKOUT_CTRL = ((u32RegVal & (~(uint32_t)CSC0_CLKOUT_CTRL_CLKOUT_DIV_MASK)) | CSC0_CLKOUT_CTRL_CLKOUT_DIV(eDivType)); +} + +/** + * @brief Get CLKOUT source Select + * + * @return CSC0_ClockOutSrcType CSC0 clock out source + */ +LOCAL_INLINE CSC0_ClockOutSrcType CSC0_HWA_GetClkOutSel(void) +{ + uint32_t u32RegVal = (CSC0->CLKOUT_CTRL & CSC0_CLKOUT_CTRL_CLKOUT_SEL_MASK) >> CSC0_CLKOUT_CTRL_CLKOUT_SEL_SHIFT; + return (CSC0_ClockOutSrcType)u32RegVal; +} + +/** + * @brief Set CLKOUT source Select + * + * @param eClkSrcType CSC0 clock out source + */ +LOCAL_INLINE void CSC0_HWA_SetClkOutSel(CSC0_ClockOutSrcType eClkSrcType) +{ + uint32_t u32RegVal = CSC0->CLKOUT_CTRL; + CSC0->CLKOUT_CTRL = ((u32RegVal & (~(uint32_t)CSC0_CLKOUT_CTRL_CLKOUT_SEL_MASK)) | CSC0_CLKOUT_CTRL_CLKOUT_SEL(eClkSrcType)); +} + +/** + * @brief Lock CSC0_CLKOUT_CTRL register + * + */ +LOCAL_INLINE void CSC0_HWA_LockCLKOUT_CTRL(void) +{ + CSC0->CLKOUT_CTRL |= (uint32_t)CSC0_CLKOUT_CTRL_LOCK_MASK; +} + +/** + * @brief Get CSC0_CLKOUT_CTRL register lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_CLKOUT_CTRL_GetLockStatus(void) +{ + return (CSC0->CLKOUT_CTRL & (uint32_t)CSC0_CLKOUT_CTRL_LOCK_MASK); +} + +/** + * @brief Get AONCLKSR register status + * + * @return AONCLKSR register status + */ +LOCAL_INLINE uint32_t CSC0_HWA_GetStatus_AONCLKSR(void) +{ + return CSC0->AONCLKSR; +} + +/** + * @brief Get CSC0_AON32KCLK source clock + * + * @return CSC0_AON32KClkSrcType CSC0_AON32KCLK source type + */ +LOCAL_INLINE CSC0_AON32KClkSrcType CSC0_HWA_GetAON32kClkSrc(void) +{ + uint32_t u32RegVal = (CSC0->AONCLKSR & CSC0_AONCLKSR_AON32KCLKSEL_MASK) >> CSC0_AONCLKSR_AON32KCLKSEL_SHIFT; + return (CSC0_AON32KClkSrcType)u32RegVal; +} + +/** + * @brief Set CSC0_AON32KCLK source clock + * + * @param CSC0_AON32KClkSrcType CSC0_AON32KCLK source type + */ +LOCAL_INLINE void CSC0_HWA_SetAON32kClkSrc(CSC0_AON32KClkSrcType eClkSrcType) +{ + uint32_t u32RegVal = CSC0->AONCLKSR; + CSC0->AONCLKSR = ((u32RegVal & (~(uint32_t)CSC0_AONCLKSR_AON32KCLKSEL_MASK)) | CSC0_AONCLKSR_AON32KCLKSEL(eClkSrcType)); +} + +/** + * @brief Get CSC0_RTCCLK source clock + * + * @return CSC0_RTCClkSrcType CSC0_RTCCLK source type + */ +LOCAL_INLINE CSC0_RTCClkSrcType CSC0_HWA_GetRTCClkSrc(void) +{ + uint32_t u32RegVal = (CSC0->AONCLKSR & CSC0_AONCLKSR_RTCCLKSEL_MASK) >> CSC0_AONCLKSR_RTCCLKSEL_SHIFT; + return (CSC0_RTCClkSrcType)u32RegVal; +} + +/** + * @brief Set CSC0_RTCCLK source clock + * + * @param CSC0_RTCClkSrcType CSC0_RTCCLK source type + */ +LOCAL_INLINE void CSC0_HWA_SetRTCClkSrc(CSC0_RTCClkSrcType eClkSrcType) +{ + uint32_t u32RegVal = CSC0->AONCLKSR; + CSC0->AONCLKSR = ((u32RegVal & (~(uint32_t)CSC0_AONCLKSR_RTCCLKSEL_MASK)) | CSC0_AONCLKSR_RTCCLKSEL(eClkSrcType)); +} + +/** + * @brief Get CSC0_AONCLK source clock + * + * @return CSC0_AONClkSrcType CSC0_AONCLK source type + */ +LOCAL_INLINE CSC0_AONClkSrcType CSC0_HWA_GetAONClkSrc(void) +{ + uint32_t u32RegVal = (CSC0->AONCLKSR & CSC0_AONCLKSR_AONCLKSEL_MASK) >> CSC0_AONCLKSR_AONCLKSEL_SHIFT; + return (CSC0_AONClkSrcType)u32RegVal; +} + +/** + * @brief Set CSC0_AONCLK source clock + * + * @param CSC0_AONClkSrcType CSC0_AONCLK source type + */ +LOCAL_INLINE void CSC0_HWA_SetAONClkSrc(CSC0_AONClkSrcType eClkSrcType) +{ + uint32_t u32RegVal = CSC0->AONCLKSR; + CSC0->AONCLKSR = ((u32RegVal & (~(uint32_t)CSC0_AONCLKSR_AONCLKSEL_MASK)) | CSC0_AONCLKSR_AONCLKSEL(eClkSrcType)); +} + +/** + * @brief Enable CSC0_SIRCDIV32K clock out + * + */ +LOCAL_INLINE void CSC0_HWA_EnableSIRCDIV_32KClkOut(void) +{ + CSC0->AONCLKSR |= (uint32_t)CSC0_AONCLKSR_SIRCDIV32KEN_MASK; +} + +/** + * @brief Disable CSC0_SIRCDIV32K clock out + * + */ +LOCAL_INLINE void CSC0_HWA_DisableSIRCDIV_32KClkOut(void) +{ + CSC0->AONCLKSR &= ~(uint32_t)CSC0_AONCLKSR_SIRCDIV32KEN_MASK; +} + +/** + * @brief Enable CSC0_SIRC32_1K clock out + * + */ +LOCAL_INLINE void CSC0_HWA_EnableSIRC32_1KClkOut(void) +{ + CSC0->AONCLKSR |= (uint32_t)CSC0_AONCLKSR_AON1KCLKEN_MASK; +} + +/** + * @brief Disable CSC0_SIRC32_1K clock out + * + */ +LOCAL_INLINE void CSC0_HWA_DisableSIRC32_1KClkOut(void) +{ + CSC0->AONCLKSR &= ~(uint32_t)CSC0_AONCLKSR_AON1KCLKEN_MASK; +} + +/** + * @brief Lock CSC0_AONCLKSR register + * + */ +LOCAL_INLINE void CSC0_HWA_LockAONCLKSR(void) +{ + CSC0->AONCLKSR |= (uint32_t)CSC0_AONCLKSR_LOCK_MASK; +} + +/** + * @brief Get CSC0_AONCLKSR register lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_AONCLKSR_GetLockStaus(void) +{ + return (CSC0->AONCLKSR & (uint32_t)CSC0_AONCLKSR_LOCK_MASK); +} + +/** + * @brief Set count for reduce power mode exit + * + * @param u8Conut count to be set + */ +LOCAL_INLINE void CSC0_HWA_SetRpmExitCount(uint8_t u8Conut) +{ + uint32_t u32RegVal = CSC0->PCU_CTRL; + CSC0->PCU_CTRL = ((u32RegVal & (~(uint32_t)CSC0_PCU_CTRL_RPM_EXIT_CNT_MASK)) | CSC0_PCU_CTRL_RPM_EXIT_CNT(u8Conut)); +} + +/** + * @brief Get count of reduce power mode exit + * + * @return count be got + */ +LOCAL_INLINE uint8_t CSC0_HWA_GetRpmExitCount(void) +{ + return (uint8_t)((CSC0->PCU_CTRL & (uint32_t)CSC0_PCU_CTRL_RPM_EXIT_CNT_MASK)>>CSC0_PCU_CTRL_RPM_EXIT_CNT_SHIFT); +} + +/** + * @brief Set power domain 1 isolation enable hold + * + */ +LOCAL_INLINE void CSC0_HWA_SetPadIsoHold(void) +{ + CSC0->PCU_CTRL |= CSC0_PCU_CTRL_PAD_ISO_HOLD_MASK; +} + +/** + * @brief Power domain 1 isolation enable hold clear + * + */ +LOCAL_INLINE void CSC0_HWA_CLearPadIsoHold(void) +{ + CSC0->PCU_CTRL |= CSC0_PCU_CTRL_PAD_ISO_HOLD_CLR_MASK; +} + +/** + * @brief Lock CSC0_PCU_CTRL register + * + */ +LOCAL_INLINE void CSC0_HWA_LockPCU_CTRL(void) +{ + CSC0->PCU_CTRL |= (uint32_t)CSC0_PCU_CTRL_LOCK_MASK; +} + +/** + * @brief Unlock CSC0_PCU_CTRL register + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_PCU_CTRL_GetLockStatus(void) +{ + return (CSC0->PCU_CTRL & (uint32_t)CSC0_PCU_CTRL_LOCK_MASK); +} + +/** + * @brief Enable CSC_SMU control group 0 + * + * @param eType CSC_SMU control group 0 type + */ +LOCAL_INLINE void CSC0_HWA_CTRL0_EnableReqToSMU(CSC_SMU_CtrlGrp0Type eType) +{ + CSC0->SMU_CTRL0 |= (uint32_t)eType; +} + +/** + * @brief Disable CSC_SMU control group 0 + * + * @param eType CSC_SMU control group 0 type + */ +LOCAL_INLINE void CSC0_HWA_CTRL0_DisableReqToSMU(CSC_SMU_CtrlGrp0Type eType) +{ + CSC0->SMU_CTRL0 &= ~(uint32_t)eType; +} + +/** + * @brief Set multiple CSC_SMU control group 0 + * + * @param u32Value The or value of CSC_SMU_CtrlGrp0Type + */ +LOCAL_INLINE void CSC0_HWA_CTRL0_SetMultiReqToSMU(uint32_t u32Value) +{ + CSC0->SMU_CTRL0 = u32Value; +} + +/** + * @brief Clear multiple CSC_SMU control group 0 + * + * @param u32Value The or value of CSC_SMU_CtrlGrp0Type + */ +LOCAL_INLINE void CSC0_HWA_CTRL0_ClearMultiReqToSMU(uint32_t u32Value) +{ + CSC0->SMU_CTRL0 &= ~u32Value; +} + +/** + * @brief Lock CSC0_SMU_CTRL0 register + * + */ +LOCAL_INLINE void CSC0_HWA_LockSMU_CTRL0(void) +{ + CSC0->SMU_CTRL0 |= (uint32_t)CSC0_SMU_CTRL0_LOCK_MASK; +} + +/** + * @brief Get CSC0_SMU_CTRL0 register lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_SMU_CTRL0_GetLockStatus(void) +{ + return (CSC0->SMU_CTRL0 & (uint32_t)CSC0_SMU_CTRL0_LOCK_MASK); +} + +/** + * @brief Enable CSC_SMU control group 1 + * + * @param eType CSC_SMU control group 1 type + */ +LOCAL_INLINE void CSC0_HWA_CTRL1_EnableReqToSMU(CSC_SMU_Cpux_CtrlGrpType eType) +{ + CSC0->SMU_CTRL1 |= (uint32_t)eType; +} + +/** + * @brief Disable CSC_SMU control group 1 + * + * @param eType CSC_SMU control group 1 type + */ +LOCAL_INLINE void CSC0_HWA_CTRL1_DisableReqToSMU(CSC_SMU_Cpux_CtrlGrpType eType) +{ + CSC0->SMU_CTRL1 &= ~(uint32_t)eType; +} + +/** + * @brief Set multiple CSC_SMU control group 1 + * + * @param u32Value The or value of CSC_SMU_Cpux_CtrlGrpType + */ +LOCAL_INLINE void CSC0_HWA_CTRL1_SetMultiReqToSMU(uint32_t u32Value) +{ + CSC0->SMU_CTRL1 = u32Value; +} + +/** + * @brief Clear multiple CSC_SMU control group 1 + * + * @param u32Value The or value of CSC_SMU_Cpux_CtrlGrpType + */ +LOCAL_INLINE void CSC0_HWA_CTRL1_ClearMultiReqToSMU(uint32_t u32Value) +{ + CSC0->SMU_CTRL1 &= ~u32Value; +} + +/** + * @brief Lock CSC0_SMU_CTRL1 register + * + */ +LOCAL_INLINE void CSC0_HWA_LockSMU_CTRL1(void) +{ + CSC0->SMU_CTRL1 |= (uint32_t)CSC0_SMU_CTRL1_LOCK_MASK; +} + +/** + * @brief Get CSC0_SMU_CTRL1 register lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_SMU_CTRL1_GetLockStatus(void) +{ + return (CSC0->SMU_CTRL1 & (uint32_t)CSC0_SMU_CTRL1_LOCK_MASK); +} + +/** + * @brief Enable CSC_SMU control group 4 + * + * @param eType CSC_SMU control group 4 type + */ +LOCAL_INLINE void CSC0_HWA_CTRL4_EnableReqToSMU(CSC_SMU_CtrlGrp4Type eType) +{ + CSC0->SMU_CTRL4 |= (uint32_t)eType; +} + +/** + * @brief Disable CSC_SMU control group 4 + * + * @param eType CSC_SMU control group 4 type + */ +LOCAL_INLINE void CSC0_HWA_CTRL4_DisableReqToSMU(CSC_SMU_CtrlGrp4Type eType) +{ + CSC0->SMU_CTRL4 &= ~(uint32_t)eType; +} + +/** + * @brief Set multiple CSC_SMU control group 4 + * + * @param u32Value The or value of CSC_SMU_CtrlGrp4Type + */ +LOCAL_INLINE void CSC0_HWA_CTRL4_SetMultiReqToSMU(uint32_t u32Value) +{ + CSC0->SMU_CTRL4 = u32Value; +} + +/** + * @brief Clear multiple CSC_SMU control group 4 + * + * @param u32Value The or value of CSC_SMU_CtrlGrp4Type + */ +LOCAL_INLINE void CSC0_HWA_CTRL4_ClearMultiReqToSMU(uint32_t u32Value) +{ + CSC0->SMU_CTRL4 &= ~u32Value; +} + +/** + * @brief Lock CSC0_SMU_CTRL4 register + * + */ +LOCAL_INLINE void CSC0_HWA_LockSMU_CTRL4(void) +{ + CSC0->SMU_CTRL4 |= (uint32_t)CSC0_SMU_CTRL4_LOCK_MASK; +} + +/** + * @brief Get CSC0_SMU_CTRL4 register lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_SMU_CTRL4_GetLockStatus(void) +{ + return (CSC0->SMU_CTRL4 & (uint32_t)CSC0_SMU_CTRL4_LOCK_MASK); +} + +/** + * @brief Enable CSC_SMU control group 5 + * + * @param eType CSC_SMU control group 5 type + */ +LOCAL_INLINE void CSC0_HWA_CTRL5_EnableReqToSMU(CSC_SMU_CtrlGrp5Type eType) +{ + CSC0->SMU_CTRL5 |= (uint32_t)eType; +} + +/** + * @brief Disable CSC_SMU control group 5 + * + * @param eType CSC_SMU control group 5 type + */ +LOCAL_INLINE void CSC0_HWA_CTRL5_DisableReqToSMU(CSC_SMU_CtrlGrp5Type eType) +{ + CSC0->SMU_CTRL5 &= ~(uint32_t)eType; +} + +/** + * @brief Set multiple CSC_SMU control group 5 + * + * @param u32Value The or value of CSC_SMU_CtrlGrp5Type + */ +LOCAL_INLINE void CSC0_HWA_CTRL5_SetMultiReqToSMU(uint32_t u32Value) +{ + CSC0->SMU_CTRL5 = u32Value; +} + +/** + * @brief Clear multiple CSC_SMU control group 5 + * + * @param u32Value The or value of CSC_SMU_CtrlGrp4Type + */ +LOCAL_INLINE void CSC0_HWA_CTRL5_ClearMultiReqToSMU(uint32_t u32Value) +{ + CSC0->SMU_CTRL5 &= ~u32Value; +} + +/** + * @brief Lock CSC0_SMU_CTRL5 register + * + */ +LOCAL_INLINE void CSC0_HWA_LockSMU_CTRL5(void) +{ + CSC0->SMU_CTRL5 |= (uint32_t)CSC0_SMU_CTRL5_LOCK_MASK; +} + +/** + * @brief Get CSC0_SMU_CTRL5 register lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_SMU_CTRL5_GetLockStatus(void) +{ + return (CSC0->SMU_CTRL5 & (uint32_t)CSC0_SMU_CTRL5_LOCK_MASK); +} + +/** + * @brief Enable CSC_CMU control group + * + * @param eType CSC_CMU control group type + */ +LOCAL_INLINE void CSC0_HWA_EnableReqToCMU(CSC0_CMU_CtrlGrpType eType) +{ + CSC0->CMU_CTRL |= (uint32_t)eType; +} + +/** + * @brief Disable CSC_CMU control group + * + * @param eType CSC_CMU control group type + */ +LOCAL_INLINE void CSC0_HWA_DisableReqToCMU(CSC0_CMU_CtrlGrpType eType) +{ + CSC0->CMU_CTRL &= ~(uint32_t)eType; +} + +/** + * @brief Lock CSC0_SMU_CTRL4 register + * + */ +LOCAL_INLINE void CSC0_HWA_LockCMU_CTRL(void) +{ + CSC0->CMU_CTRL |= (uint32_t)CSC0_CMU_CTRL_LOCK_MASK; +} + +/** + * @brief Get CSC0_SMU_CTRL4 register lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_CMU_CTRL_GetLockStatus(void) +{ + return (CSC0->CMU_CTRL & (uint32_t)CSC0_CMU_CTRL_LOCK_MASK); +} + +/** + * @brief Set low power wakeup PADx configure source + * + * @param eGroup Low power PADx group type + * @eSrc eSrc Low power wakeup PADx configure source + */ +LOCAL_INLINE void CSC0_HWA_SetLP_WAKEUPCfgSrc(CSC0_LPWakeupGrpType eGroup, CSC0_LPWakeupSrcType eSrc) +{ + CSC0->LP_WAKEUP = (CSC0->LP_WAKEUP & (~(CSC0_LP_WAKEUP_LP_WAKEUP_CFG0_MASK >> (4U * (uint32_t)eGroup)))) | + (CSC0_LP_WAKEUP_LP_WAKEUP_CFG0(eSrc) >> (4U * (uint32_t)eGroup)); +} + + +/** + * @brief Set low power wakeup PADx configure source polarity + * + * @param eGroup Low power PADx group type + * @eSrc eSrc Low power wakeup PADx configure source polarity + */ +LOCAL_INLINE void CSC0_HWA_SetLP_WAKEUPCfgPol(CSC0_LPWakeupGrpType eGroup, CSC0_LPWakeupPolType ePolarity) +{ + CSC0->LP_WAKEUP = (CSC0->LP_WAKEUP & (~(CSC0_LP_WAKEUP_LP0_POL_MASK >> (uint32_t)eGroup))) | + (CSC0_LP_WAKEUP_LP0_POL(ePolarity) >> (uint32_t)eGroup); +} + +/** + * @brief Lock low power wakeup register + * + */ +LOCAL_INLINE void CSC0_HWA_LockLP_WAKEUP(void) +{ + CSC0->LP_WAKEUP |= (uint32_t)CSC0_LP_WAKEUP_LOCK_MASK; +} + +/** + * @brief Get low power wakeup register lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t CSC0_HWA_LP_WAKEUP_GetLockStatus(void) +{ + return (CSC0->LP_WAKEUP & (uint32_t)CSC0_LP_WAKEUP_LOCK_MASK); +} + +#endif /*#ifndef _HWA_CSC_H_*/ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_dma.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_dma.h new file mode 100644 index 0000000..03f7632 --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_dma.h @@ -0,0 +1,1514 @@ +/** + * @file HwA_dma.h + * @author Flagchip0126 + * @brief Hardware access layer for DMA + * @version 0.1.0 + * @date 2024-01-15 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-15 Flagchip0126 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef _HWA_DMA_H_ +#define _HWA_DMA_H_ + +#include "device_header.h" + +#define DMA_CH_TO_DCHPRI(x) ((x) ^ 3U) + +/** + * @defgroup HwA_dma + * @ingroup fc7xxx_driver_dma + * @{ + */ + +/** + * @brief DMA running status + * + */ +typedef enum +{ + DMA_RUNNING_STATUS_IDLE = 0x0U, /*!< The DMA engine is idle */ + DMA_RUNNING_STATUS_ACTIVE = 0x1U /*!< The DMA engine is transferring data */ +} DMA_RunningStatusType; + +/** + * @brief DMA channel arbitration algorithm used in the channel arbitration phase + * + */ +typedef enum +{ + DMA_ARBITRATION_ALGORITHM_FIXED_PRIORITY = 0U, /*!< Use the fixed priority for arbitration */ + DMA_ARBITRATION_ALGORITHM_ROUND_ROBIN = 1U /*!< Use the channel number for arbitration, + higher channel number has higher priority */ +} DMA_ArbitrationAlgorithmType; + +/** + * @brief Defines the size of data in one transfer + * + * One transfer can contain multiple block, and one block may contain multiple + * data, this parameter specifies the size of data which the DMA engine will + * access one time in the memory. + * + */ +typedef enum +{ + + DMA_TRANSFER_SIZE_1B = 0x0U, + DMA_TRANSFER_SIZE_2B = 0x1U, + DMA_TRANSFER_SIZE_4B = 0x2U, + DMA_TRANSFER_SIZE_8B = 0x3U, + DMA_TRANSFER_SIZE_32B = 0x5U +} DMA_TransferSizeType; + +/** + * @brief Get active status of the DMA instance + * + * @param pDma the base address of the DMA instance + * @return DMA_RUNNING_STATUS_ACTIVE DMA is executing a channel + * @return DMA_RUNNING_STATUS_IDLE DMA is idle + */ +LOCAL_INLINE DMA_RunningStatusType DMA_HWA_GetStatus(const DMA_Type *const pDma) +{ + uint32_t u32TmpVal = (pDma->CR & DMA_CR_ACTIVE_MASK) >> DMA_CR_ACTIVE_SHIFT; + return (DMA_RunningStatusType)u32TmpVal; +} + +/** + * @brief Get whether the DMA instance is cancelling + * + * @param pDma the base address of the DMA instance + * @return true cancel operation is requested and has not been finished + * @return false DMA is under normal operation + */ +LOCAL_INLINE bool DMA_HWA_GetCancelTransferStatus(const DMA_Type *const pDma) +{ + uint32_t u32TmpVal = (pDma->CR & DMA_CR_CX_MASK) >> DMA_CR_CX_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Cancel the remaining transfer of the DMA + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_CancelTransfer(DMA_Type *const pDma) +{ + pDma->CR |= DMA_CR_CX_MASK; +} + +/** + * @brief Get whether the DMA instance is cancelling with error + * + * @param pDma the base address of the DMA instance + * @return true cancel operation is requested and has not been finished + * @return false DMA is under normal operation + */ +LOCAL_INLINE bool DMA_HWA_GetErrorCancelTransferStatus(const DMA_Type *const pDma) +{ + uint32_t u32TmpVal = (pDma->CR & DMA_CR_ECX_MASK) >> DMA_CR_ECX_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set Channel Group 0 Priority + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_SetGPR0PRI(DMA_Type *const pDma) +{ + pDma->CR = (pDma->CR & ~DMA_CR_GPR0PRI_MASK) | DMA_CR_GPR0PRI(1U); +} + +/** + * @brief Cancel the remaining transfer of the DMA and generate an error after finished cancelling + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_ErrorCancelTransfer(DMA_Type *const pDma) +{ + pDma->CR |= DMA_CR_ECX_MASK; +} + +/** + * @brief Get whether inner loop mapping is enabled + * + * @param pDma the base address of the DMA instance + * @return true inner loop mapping is enabled + * @return false inner loop mapping is disabled + */ +LOCAL_INLINE bool DMA_HWA_GetInnerLoopMappingEnableFlag(const DMA_Type *const pDma) +{ + uint32_t u32TmpVal = (pDma->CR & DMA_CR_EILM_MASK) >> DMA_CR_EILM_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable inner loop mapping + * + * @note Only after enabling inner loop mapping, you can apply an offset to the source + * and/or destination address after the inner loop finishes. + * + * @param pDma the base address of the DMA instance + * @param bEnable whether to enable the inner loop mapping + */ +LOCAL_INLINE void DMA_HWA_SetInnerLoopMappingEnableFlag(DMA_Type *const pDma, bool bEnable) +{ + pDma->CR = (pDma->CR & ~DMA_CR_EILM_MASK) | DMA_CR_EILM(bEnable); +} + +/** + * @brief Get whether the continuous trig mode is enabled + * When continuous trig mode is enabled, channel arbitration is not used for a inner loop + * channel trig before being activated again. Upon inner loop completion, the channel + * activates again if that channel has a inner loop channel trig enabled and the trig + * channel is itself. This effectively applies the inner loop offsets and restarts the next + * inner loop. + * + * @param pDma the base address of the DMA instance + * @return true continuous trig mode is enabled + * @return false continuous trig mode is disabled + */ +LOCAL_INLINE bool DMA_HWA_GetContinuousTrigModeEnableFlag(const DMA_Type *const pDma) +{ + uint32_t u32TmpVal = (pDma->CR & DMA_CR_CTM_MASK) >> DMA_CR_CTM_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable the continuous trig mode + * + * @param pDma the base address of the DMA instance + * @param bEnable whether to enable the continuous trig mode + */ +LOCAL_INLINE void DMA_HWA_SetContinuousTrigModeEnableFlag(DMA_Type *const pDma, bool bEnable) +{ + pDma->CR = (pDma->CR & ~DMA_CR_CTM_MASK) | DMA_CR_CTM(bEnable); +} + +/** + * @brief Get whether the DMA is halted + * When the DMA is halted, it will ignore all service requests + * @param pDma the base address of the DMA instance + * @return true the DMA is halted + * @return true the DMA is not halted + */ +LOCAL_INLINE bool DMA_HWA_GetHatlStatus(const DMA_Type *const pDma) +{ + uint32_t u32TmpVal = (pDma->CR & DMA_CR_HALT_MASK) >> DMA_CR_HALT_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Halt the DMA operations + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_HaltOperations(DMA_Type *const pDma) +{ + pDma->CR |= DMA_CR_HALT_MASK; +} + +/** + * @brief Clear the halt flag of the DMA instance + * After HALT is cleared, the DMA could continue to operate + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_ClearHaltFlag(DMA_Type *const pDma) +{ + pDma->CR &= ~DMA_CR_HALT_MASK; +} + +/** + * @brief Get whether halt on error is enabled on the DMA instance + * + * @param pDma the base address of the DMA instance + * @return true halt on error is enabled, any error will cause HALT flag to be set + * @return false halt on error is disabled + */ +LOCAL_INLINE bool DMA_HWA_GetHaltOnErrorFlag(const DMA_Type *const pDma) +{ + uint32_t u32TmpVal = (pDma->CR & DMA_CR_HOE_MASK) >> DMA_CR_HOE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable halt on error on the DMA instance + * + * @note Ff halt on error is enabled, any error will cause HALT flag to be set + * + * @param pDma the base address of the DMA instance + * @param bEnable whether to enable halt on error + */ +LOCAL_INLINE void DMA_HWA_SetHaltOnErrorFlag(DMA_Type *const pDma, bool bEnable) +{ + pDma->CR = (pDma->CR & ~DMA_CR_HOE_MASK) | DMA_CR_HOE(bEnable); +} + +/** + * @brief Get the DMA arbitration algorithm + * + * @param pDma the base address of the DMA instance + * @return DMA_ArbitrationAlgorithmType the DMA arbitration algorithm + */ +LOCAL_INLINE DMA_ArbitrationAlgorithmType DMA_HWA_GetArbitrationAlgorithm(const DMA_Type *const pDma) +{ + uint32_t u32TmpVal = (pDma->CR & DMA_CR_ERCA_MASK) >> DMA_CR_ERCA_SHIFT; + return (DMA_ArbitrationAlgorithmType)u32TmpVal; +} + +/** + * @brief Set the DMA arbitration algorithm + * + * @param pDma the base address of the DMA instance + * @param eAlgorithm the DMA arbitration algorithm + */ +LOCAL_INLINE void DMA_HWA_SetArbitrationAlgorithm(DMA_Type *const pDma, DMA_ArbitrationAlgorithmType eAlgorithm) +{ + pDma->CR = (pDma->CR & ~DMA_CR_ERCA_MASK) | DMA_CR_ERCA(eAlgorithm); +} + +/** + * @brief Get whether the DMA is configured to stop under debug mode + * + * @param pDma the base address of the DMA instance + * @return true the DMA is will stop under debug mode + * @return true the DMA is will continue to operate under debug mode + */ +LOCAL_INLINE bool DMA_HWA_GetDebugModeStopFlag(const DMA_Type *const pDma) +{ + uint32_t u32TmpVal = (pDma->CR & DMA_CR_DBGS_MASK) >> DMA_CR_DBGS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get the control register of the DMA instance + * + * @param pDma the base address of the DMA instance + * @return uint32_t the control register settings + */ +LOCAL_INLINE uint32_t DMA_HWA_GetControlRegister(const DMA_Type *const pDma) +{ + return pDma->CR; +} + +/** + * @brief Set the control register of the DMA instance + * + * @param pDma the base address of the DMA instance + * @param u32Settings the settings of the DMA control register + */ +LOCAL_INLINE void DMA_HWA_SetControlRegister(DMA_Type *const pDma, uint32_t u32Settings) +{ + pDma->CR = u32Settings; +} + +/** + * @brief Set whether to stop DMA under debug mode + * + * @param pDma the base address of the DMA instance + * @param bEnable whether to stop DMA under debug mode + */ +LOCAL_INLINE void DMA_HWA_SetDebugModeStopFlag(DMA_Type *const pDma, bool bEnable) +{ + pDma->CR = (pDma->CR & ~DMA_CR_DBGS_MASK) | DMA_CR_DBGS(bEnable); +} + +/** + * @brief Get the DMA error status + * + * @param pDma the base address of the DMA instance + * @return uint32_t the DMA error status + */ +LOCAL_INLINE uint32_t DMA_HWA_GetErrorStatus(const DMA_Type *const pDma) +{ + return pDma->ES; +} + +/** + * @brief Get whether there is error occured on the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true there is error on the specified channel + * @return false there is no error on the specified channel + */ +LOCAL_INLINE bool DMA_HWA_GetChannelErrorFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pDma->ERR & (1UL << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get the channel error status, each bit represents a channel + * + * @param pDma the base address of the DMA instance + * @return uint16_t the channel error status + */ +LOCAL_INLINE uint16_t DMA_HWA_GetAllChannelErrorFlag(const DMA_Type *const pDma) +{ + uint32_t u32TmpVal = pDma->ERR; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Get whether error interrupt is enabled on the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true error interrupt is enabled on the specified channel + * @return false error interrupt is disabled on the specified channel + */ +LOCAL_INLINE bool DMA_HWA_GetChannelErrorInterruptEnableFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pDma->EEI & (1UL << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get channel error interrupt enable status + * + * @param pDma the base address of the DMA instance + * @return uint16_t the channel error interrupt enable status + */ +LOCAL_INLINE uint16_t DMA_HWA_GetAllChannelErrorInterruptEnableFlag(const DMA_Type *const pDma) +{ + uint32_t u32TmpVal = pDma->EEI; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Enable error interrupt for the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + */ +LOCAL_INLINE void DMA_HWA_EnableChannelErrorInterrupt(DMA_Type *const pDma, uint8_t u8Channel) +{ + pDma->SEEI = DMA_SEEI_SEEI(u8Channel); +} + +/** + * @brief Enable error interrupt for all channels + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_EnableAllChannelErrorInterrupt(DMA_Type *const pDma) +{ + pDma->SEEI = DMA_SEEI_SAEE_MASK; +} + +/** + * @brief Disable error interrupt for the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + */ +LOCAL_INLINE void DMA_HWA_DisableChannelErrorInterrupt(DMA_Type *const pDma, uint8_t u8Channel) +{ + pDma->CEEI = DMA_CEEI_CEEI(u8Channel); +} + +/** + * @brief Disable error interrupt for all channels + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_DisableAllChannelErrorInterrupt(DMA_Type *const pDma) +{ + pDma->CEEI = DMA_CEEI_CAEE_MASK; +} + +/** + * @brief Enable channel request for the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + */ +LOCAL_INLINE void DMA_HWA_EnableChannelRequest(DMA_Type *const pDma, uint8_t u8Channel) +{ + pDma->SERQ = DMA_SERQ_SERQ(u8Channel); +} + +/** + * @brief Enable channel request for all channels + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_EnableAllChannelRequest(DMA_Type *const pDma) +{ + pDma->SERQ = DMA_SERQ_SAER_MASK; +} + +/** + * @brief Disable channel request for the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + */ +LOCAL_INLINE void DMA_HWA_DisableChannelRequest(DMA_Type *const pDma, uint8_t u8Channel) +{ + pDma->CERQ = DMA_CERQ_CERQ(u8Channel); +} + +/** + * @brief Disable channel request for all channels + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_DisableAllChannelRequest(DMA_Type *const pDma) +{ + pDma->CERQ = DMA_CERQ_CAER_MASK; +} + +/** + * @brief Clear DONE bit for the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + */ +LOCAL_INLINE void DMA_HWA_ClearChannelDoneStatus(DMA_Type *const pDma, uint8_t u8Channel) +{ + pDma->CDNE = DMA_CDNE_CDNE(u8Channel); +} + +/** + * @brief Clear DONE bit for the all channels + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_ClearAllChannelDoneStatus(DMA_Type *const pDma) +{ + pDma->CDNE = DMA_CDNE_CADN_MASK; +} + +/** + * @brief Clear ERR bit for the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + */ +LOCAL_INLINE void DMA_HWA_ClearChannelErrorFlag(DMA_Type *const pDma, uint8_t u8Channel) +{ + pDma->CERR = DMA_CERR_CERR(u8Channel); +} + +/** + * @brief Clear ERR bit for the all channels + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_ClearAllChannelErrorFlag(DMA_Type *const pDma) +{ + pDma->CERR = DMA_CERR_CAEI_MASK; +} + +/** + * @brief Clear interrupt flag for the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + */ +LOCAL_INLINE void DMA_HWA_ClearChannelInterruptFlag(DMA_Type *const pDma, uint8_t u8Channel) +{ + pDma->CINT = DMA_CINT_CINT(u8Channel); +} + +/** + * @brief Clear interrupt flag for the all channels + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_ClearAllChannelInterruptFlag(DMA_Type *const pDma) +{ + pDma->CINT = DMA_CINT_CAIR_MASK; +} + +/** + * @brief Set start for the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + */ +LOCAL_INLINE void DMA_HWA_SetChannelStart(DMA_Type *const pDma, uint8_t u8Channel) +{ + pDma->SSRT = DMA_SSRT_SSRT(u8Channel); +} + +/** + * @brief Set start for the all channels + * + * @param pDma the base address of the DMA instance + */ +LOCAL_INLINE void DMA_HWA_SetAllChannelStart(DMA_Type *const pDma) +{ + pDma->SSRT = DMA_SSRT_SAST_MASK; +} + +/** + * @brief Get whether source unalign modulo is enabled for the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + */ +LOCAL_INLINE bool DMA_HWA_GetSrcUnalignModuloEnableFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pDma->DUME[u8Channel/16U] & ((uint32_t)DMA_DUME_SUME0_MASK << (2U * (u8Channel % 16U)))) >> + (DMA_DUME_SUME0_SHIFT + 2U * (u8Channel % 16U)); + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get whether destination unalign modulo is enabled for the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + */ +LOCAL_INLINE bool DMA_HWA_GetDestUnalignModuloEnableFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint32_t u32TmpVal = (pDma->DUME[u8Channel/16U] & ((uint32_t)DMA_DUME_DUME0_MASK << (2U * (u8Channel % 16U)))) >> + (DMA_DUME_DUME0_SHIFT + 2U * (u8Channel % 16U)); + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get whether to enable unalign modulo for the specified channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param bEnableSrcModulo whether source unalign modulo is to be enabled + * @param bEnableDestModulo whether destination unalign modulo is to be enabled + */ +LOCAL_INLINE void DMA_HWA_SetUnalignModuloEnableFlag(DMA_Type *const pDma, uint8_t u8Channel, + bool bEnableSrcModulo, bool bEnableDestModulo) +{ + pDma->DUME[u8Channel/16U] = (pDma->DUME[u8Channel/16U] & ~((DMA_DUME_DUME0_MASK | DMA_DUME_SUME0_MASK) << (2U * (u8Channel % 16U)))) | + ((DMA_DUME_DUME0(bEnableDestModulo) | DMA_DUME_SUME0(bEnableSrcModulo)) << (2U * (u8Channel % 16U))); +} + +/** + * @brief Get the source unalign modulo of the index + * + * @param pDma the base address of the DMA instance + * @param u8Selection the index of the unalign modulo + * @return uint16_t the source unalign modulo + */ +LOCAL_INLINE uint16_t DMA_HWA_GetSrcUnalignModulo(const DMA_Type *const pDma, uint8_t u8Selection) +{ + uint32_t u32TmpVal = (pDma->DUMO[u8Selection] & DMA_DUMO_SUMO_MASK) >> DMA_DUMO_SUMO_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Get the destination unalign modulo of the index + * + * @param pDma the base address of the DMA instance + * @param u8Selection the index of the unalign modulo + * @return uint16_t the destination unalign modulo + */ +LOCAL_INLINE uint16_t DMA_HWA_GetDestUnalignModulo(const DMA_Type *const pDma, uint8_t u8Selection) +{ + uint32_t u32TmpVal = (pDma->DUMO[u8Selection] & DMA_DUMO_DUMO_MASK) >> DMA_DUMO_DUMO_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Set unalign modulo of the index + * + * @param pDma the base address of the DMA instance + * @param u8Selection the index of the unalign modulo + * @param u16SrcModulo the source unalign modulo + * @param u16DestModulo the destination unalign modulo + */ +LOCAL_INLINE void DMA_HWA_SetUnalignModulo(DMA_Type *const pDma, uint8_t u8Selection, + uint16_t u16SrcModulo, uint16_t u16DestModulo) +{ + pDma->DUMO[u8Selection] = DMA_DUMO_SUMO(u16SrcModulo) | DMA_DUMO_DUMO(u16DestModulo); +} + +/** + * @brief Get priority of the channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint8_t the priority of the channel + */ +LOCAL_INLINE uint8_t DMA_HWA_GetPriority(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint8_t u8TmpVal = pDma->DCHPRI[DMA_CH_TO_DCHPRI(u8Channel)]; + return u8TmpVal; +} + +/** + * @brief Set priority of the channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param u8Priority the priority of the channel + */ +LOCAL_INLINE void DMA_HWA_SetPriority(DMA_Type *const pDma, uint8_t u8Channel, uint8_t u8Priority) +{ + pDma->DCHPRI[DMA_CH_TO_DCHPRI(u8Channel)] = u8Priority; +} + +/** + * @brief Get the source address of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint32_t the source address of the DMA channel + */ +LOCAL_INLINE uint32_t DMA_HWA_GetSrcAddr(const DMA_Type *const pDma, uint8_t u8Channel) +{ + return pDma->CFG[u8Channel].SADDR; +} + +/** + * @brief Set the source address of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param u32SrcAddr the source address of the DMA channel + */ +LOCAL_INLINE void DMA_HWA_SetSrcAddr(DMA_Type *const pDma, uint8_t u8Channel, uint32_t u32SrcAddr) +{ + pDma->CFG[u8Channel].SADDR = u32SrcAddr; +} + +/** + * @brief Get the destination address of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint32_t the destination address of the DMA channel + */ +LOCAL_INLINE uint32_t DMA_HWA_GetDestAddr(const DMA_Type *const pDma, uint8_t u8Channel) +{ + return pDma->CFG[u8Channel].DADDR; +} + +/** + * @brief Set the destination address of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param u32DestAddr the destination address of the DMA channel + */ +LOCAL_INLINE void DMA_HWA_SetDestAddr(DMA_Type *const pDma, uint8_t u8Channel, uint32_t u32DestAddr) +{ + pDma->CFG[u8Channel].DADDR = u32DestAddr; +} + +/** + * @brief Get source data offset of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return int16_t the source data offset + */ +LOCAL_INLINE int16_t DMA_HWA_GetSrcOffset(const DMA_Type *const pDma, uint8_t u8Channel) +{ + return (int16_t)pDma->CFG[u8Channel].SOFF; +} + +/** + * @brief Set source data offset of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param s16Offset the source data offset + */ +LOCAL_INLINE void DMA_HWA_SetSrcOffset(DMA_Type *const pDma, uint8_t u8Channel, int16_t s16Offset) +{ + pDma->CFG[u8Channel].SOFF = (uint16_t)s16Offset; +} + +/** + * @brief Get destination data offset of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return int16_t the destination data offset + */ +LOCAL_INLINE int16_t DMA_HWA_GetDestOffset(const DMA_Type *const pDma, uint8_t u8Channel) +{ + return (int16_t)pDma->CFG[u8Channel].DOFF; +} + +/** + * @brief Set destination data offset of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param s16Offset the destination data offset + */ +LOCAL_INLINE void DMA_HWA_SetDestOffset(DMA_Type *const pDma, uint8_t u8Channel, int16_t s16Offset) +{ + pDma->CFG[u8Channel].DOFF = (uint16_t)s16Offset; +} + +/** + * @brief Get the source data size of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return DMA_TransferSizeType the source data size of the DMA channel + */ +LOCAL_INLINE DMA_TransferSizeType DMA_HWA_GetSrcDataSize(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].ATTR & DMA_CFG_ATTR_SSIZE_MASK) >> DMA_CFG_ATTR_SSIZE_SHIFT; + return (DMA_TransferSizeType)u16TmpVal; +} + +/** + * @brief Set the source data size of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param eDataSize the source data size of the DMA channel + */ +LOCAL_INLINE void DMA_HWA_SetSrcDataSize(DMA_Type *const pDma, uint8_t u8Channel, DMA_TransferSizeType eDataSize) +{ + pDma->CFG[u8Channel].ATTR = (pDma->CFG[u8Channel].ATTR & ~DMA_CFG_ATTR_SSIZE_MASK) | DMA_CFG_ATTR_SSIZE(eDataSize); +} + +/** + * @brief Get the destination data size of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return DMA_TransferSizeType the destination data size of the DMA channel + */ +LOCAL_INLINE DMA_TransferSizeType DMA_HWA_GetDestDataSize(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].ATTR & DMA_CFG_ATTR_DSIZE_MASK) >> DMA_CFG_ATTR_DSIZE_SHIFT; + return (DMA_TransferSizeType)u16TmpVal; +} + +/** + * @brief Set the destination data size of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param eDataSize the destination data size of the DMA channel + */ +LOCAL_INLINE void DMA_HWA_SetDestDataSize(DMA_Type *const pDma, uint8_t u8Channel, DMA_TransferSizeType eDataSize) +{ + pDma->CFG[u8Channel].ATTR = (pDma->CFG[u8Channel].ATTR & ~DMA_CFG_ATTR_DSIZE_MASK) | DMA_CFG_ATTR_DSIZE(eDataSize); +} + +/** + * @brief Get the source address aligned modulo of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint8_t the source address aligned modulo + */ +LOCAL_INLINE uint8_t DMA_HWA_GetSrcModulo(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].ATTR & DMA_CFG_ATTR_SMOD_MASK) >> DMA_CFG_ATTR_SMOD_SHIFT; + return (uint8_t)u16TmpVal; +} + +/** + * @brief Set the source address aligned modulo of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param u8SrcModulo the source address aligned modulo + */ +LOCAL_INLINE void DMA_HWA_SetSrcModulo(DMA_Type *const pDma, uint8_t u8Channel, uint8_t u8SrcModulo) +{ + pDma->CFG[u8Channel].ATTR = (pDma->CFG[u8Channel].ATTR & ~DMA_CFG_ATTR_SMOD_MASK) | DMA_CFG_ATTR_SMOD(u8SrcModulo); +} + +/** + * @brief Get the destination address aligned modulo of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint8_t the destination address aligned modulo + */ +LOCAL_INLINE uint8_t DMA_HWA_GetDestModulo(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].ATTR & DMA_CFG_ATTR_DMOD_MASK) >> DMA_CFG_ATTR_DMOD_SHIFT; + return (uint8_t)u16TmpVal; +} + +/** + * @brief Set the destination address aligned modulo of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param u8DestModulo the destination address aligned modulo + */ +LOCAL_INLINE void DMA_HWA_SetDestModulo(DMA_Type *const pDma, uint8_t u8Channel, uint8_t u8DestModulo) +{ + pDma->CFG[u8Channel].ATTR = (pDma->CFG[u8Channel].ATTR & ~DMA_CFG_ATTR_DMOD_MASK) | DMA_CFG_ATTR_DMOD(u8DestModulo); +} + +/** + * @brief Get the address adjustment applied to the source address after major loop finished + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return int32_t the address adjustment applied to the source address after major loop finished + */ +LOCAL_INLINE int32_t DMA_HWA_GetSrcLastAddrAdjustment(const DMA_Type *const pDma, uint8_t u8Channel) +{ + return (int32_t)pDma->CFG[u8Channel].SLAST; +} + +/** + * @brief Set the address adjustment applied to the source address after major loop finished + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param s32LastAdj the address adjustment applied to the source address after major loop finished + */ +LOCAL_INLINE void DMA_HWA_SetSrcLastAddrAdjustment(DMA_Type *const pDma, uint8_t u8Channel, int32_t s32LastAdj) +{ + pDma->CFG[u8Channel].SLAST = (uint32_t)s32LastAdj; +} + +/** + * @brief Get the address adjustment applied to the destination address after major loop finished + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return int32_t the address adjustment applied to the destination address after major loop finished + */ +LOCAL_INLINE int32_t DMA_HWA_GetDestLastAddrAdjustment(const DMA_Type *const pDma, uint8_t u8Channel) +{ + return (int32_t)pDma->CFG[u8Channel].DLAST; +} + +/** + * @brief Set the address adjustment applied to the destination address after major loop finished + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param s32LastAdj the address adjustment applied to the destination address after major loop finished + */ +LOCAL_INLINE void DMA_HWA_SetDestLastAddrAdjustment(DMA_Type *const pDma, uint8_t u8Channel, int32_t s32LastAdj) +{ + pDma->CFG[u8Channel].DLAST = (uint32_t)s32LastAdj; +} + +/** + * @brief Get whether source address inner loop offset is enabled + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true source address inner loop offset is enabled + * @return false source address inner loop offset is disabled + */ +LOCAL_INLINE bool DMA_HWA_GetInnerLoopSrcOffsetEnableFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + if (DMA_HWA_GetInnerLoopMappingEnableFlag(pDma) == false) + { + u32TmpVal = 0U; + } + else + { + u32TmpVal = (pDma->CFG[u8Channel].NBYTES.ILOFFNO & DMA_CFG_NBYTES_ILOFFNO_SILOE_MASK) >> + DMA_CFG_NBYTES_ILOFFNO_SILOE_SHIFT; + } + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get whether destination address inner loop offset is enabled + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true destination address inner loop offset is enabled + * @return false destination address inner loop offset is disabled + */ +LOCAL_INLINE bool DMA_HWA_GetInnerLoopDestOffsetEnableFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + if (DMA_HWA_GetInnerLoopMappingEnableFlag(pDma) == false) + { + u32TmpVal = 0U; + } + else + { + u32TmpVal = (pDma->CFG[u8Channel].NBYTES.ILOFFNO & DMA_CFG_NBYTES_ILOFFNO_DILOE_MASK) >> + DMA_CFG_NBYTES_ILOFFNO_DILOE_SHIFT; + } + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get the inner loop offset of the DMA channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return int32_t the signed inner loop offset + */ +LOCAL_INLINE int32_t DMA_HWA_GetInnerLoopOffset(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + if (DMA_HWA_GetInnerLoopMappingEnableFlag(pDma) == false) + { + u32TmpVal = 0U; + } + else + { + bool bDmaInnerLoopSrcOffsetEnable = DMA_HWA_GetInnerLoopSrcOffsetEnableFlag(pDma, u8Channel); + bool bDmaInnerLoopDestOffsetEnable = DMA_HWA_GetInnerLoopDestOffsetEnableFlag(pDma, u8Channel); + if ((bDmaInnerLoopSrcOffsetEnable == false) && (bDmaInnerLoopDestOffsetEnable == false)) + { + u32TmpVal = 0U; + } + else + { + u32TmpVal = (pDma->CFG[u8Channel].NBYTES.ILOFFYES & DMA_CFG_NBYTES_ILOFFYES_ILOFF_MASK) >> + DMA_CFG_NBYTES_ILOFFYES_ILOFF_SHIFT; + } + } + /* Convert sign-extended 20bit value to signed 32bit value */ + if ((u32TmpVal & (1U << 19U)) != 0U) + { + u32TmpVal |= 0xFFF00000U; + } + return (int32_t)u32TmpVal; +} + +/** + * @brief Get the transfer data size of the inner loop + * @note if inner loop mapping is disabled, the range is 0~2^31-1 + * if inner loop mapping is enabled and inner loop offset is disabled, the range is 0~2^30-1 + * if inner loop mapping is enabled and inner loop offset is enabled, the range is 0~2^10-1 + * 0 means 2^32 + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint32_t the transfer data size of the inner loop + */ +LOCAL_INLINE uint32_t DMA_HWA_GetInnerLoopSize(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + if (DMA_HWA_GetInnerLoopMappingEnableFlag(pDma) == false) + { + u32TmpVal = pDma->CFG[u8Channel].NBYTES.ILNO; + } + else + { + bool bDmaInnerLoopSrcOffsetEnable = DMA_HWA_GetInnerLoopSrcOffsetEnableFlag(pDma, u8Channel); + bool bDmaInnerLoopDestOffsetEnable = DMA_HWA_GetInnerLoopDestOffsetEnableFlag(pDma, u8Channel); + if ((bDmaInnerLoopSrcOffsetEnable == false) && (bDmaInnerLoopDestOffsetEnable == false)) + { + u32TmpVal = (pDma->CFG[u8Channel].NBYTES.ILOFFNO & DMA_CFG_NBYTES_ILOFFNO_NBYTES_MASK) >> + DMA_CFG_NBYTES_ILOFFNO_NBYTES_SHIFT; + } + else + { + u32TmpVal = (pDma->CFG[u8Channel].NBYTES.ILOFFYES & DMA_CFG_NBYTES_ILOFFYES_NBYTES_MASK) >> + DMA_CFG_NBYTES_ILOFFYES_NBYTES_SHIFT; + } + } + return u32TmpVal; +} + +/** + * @brief Set the inner loop offset of the DMA channel + * + * @note the inner loop offset can only be enabled when inner loop mapping is enabled + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param bEnableSrcOffset whether to enable source address inner loop offset + * @param bEnableDestOffset whether to enable destination address inner loop offset + * @param s32Offset the inner loop offset + */ +LOCAL_INLINE void DMA_HWA_SetInnerLoopOffset(DMA_Type *const pDma, uint8_t u8Channel, bool bEnableSrcOffset, + bool bEnableDestOffset, int32_t s32Offset) +{ + if (DMA_HWA_GetInnerLoopMappingEnableFlag(pDma) == false) + { + //ignore the action + } + else + { + if ((bEnableSrcOffset == false) && (bEnableDestOffset == false)) + { + bool bDmaInnerLoopSrcOffsetEnable = DMA_HWA_GetInnerLoopSrcOffsetEnableFlag(pDma, u8Channel); + bool bDmaInnerLoopDestOffsetEnable = DMA_HWA_GetInnerLoopDestOffsetEnableFlag(pDma, u8Channel); + /* If inner loop offset is enabled, to disable inner loop offset, we should clear the inner + loop offset enable bit and meanwhile the inner loop offset bits */ + if ((bDmaInnerLoopSrcOffsetEnable == true) || (bDmaInnerLoopDestOffsetEnable == true)) + { + pDma->CFG[u8Channel].NBYTES.ILOFFNO &= ~(DMA_CFG_NBYTES_ILOFFNO_SILOE_MASK | DMA_CFG_NBYTES_ILOFFNO_DILOE_MASK | + DMA_CFG_NBYTES_ILOFFYES_ILOFF_MASK); + } + } + else + { + pDma->CFG[u8Channel].NBYTES.ILOFFYES = (pDma->CFG[u8Channel].NBYTES.ILOFFYES & ~(DMA_CFG_NBYTES_ILOFFYES_SILOE_MASK | + DMA_CFG_NBYTES_ILOFFYES_DILOE_MASK | DMA_CFG_NBYTES_ILOFFYES_ILOFF_MASK)) | + DMA_CFG_NBYTES_ILOFFYES_SILOE(bEnableSrcOffset) | + DMA_CFG_NBYTES_ILOFFYES_DILOE(bEnableDestOffset) | + DMA_CFG_NBYTES_ILOFFYES_ILOFF(s32Offset); + } + } +} + +/** + * @brief Set the transfer data size of the inner loop + * @note if inner loop mapping is disabled, the range is 0~2^31-1 + * if inner loop mapping is enabled and inner loop offset is disabled, the range is 0~2^30-1 + * if inner loop mapping is enabled and inner loop offset is enabled, the range is 0~2^10-1 + * 0 means 2^32 + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param u32Size the transfer data size of the inner loop + */ +LOCAL_INLINE void DMA_HWA_SetInnerLoopSize(DMA_Type *const pDma, uint8_t u8Channel, uint32_t u32Size) +{ + if (DMA_HWA_GetInnerLoopMappingEnableFlag(pDma) == false) + { + pDma->CFG[u8Channel].NBYTES.ILNO = DMA_CFG_NBYTES_ILNO_NBYTES(u32Size); + } + else + { + bool bDmaInnerLoopSrcOffsetEnable = DMA_HWA_GetInnerLoopSrcOffsetEnableFlag(pDma, u8Channel); + bool bDmaInnerLoopDestOffsetEnable = DMA_HWA_GetInnerLoopDestOffsetEnableFlag(pDma, u8Channel); + if ((bDmaInnerLoopSrcOffsetEnable == false) && (bDmaInnerLoopDestOffsetEnable == false)) + { + pDma->CFG[u8Channel].NBYTES.ILOFFNO = (pDma->CFG[u8Channel].NBYTES.ILOFFNO & ~DMA_CFG_NBYTES_ILOFFNO_NBYTES_MASK) | + DMA_CFG_NBYTES_ILOFFNO_NBYTES(u32Size); + } + else + { + pDma->CFG[u8Channel].NBYTES.ILOFFYES = (pDma->CFG[u8Channel].NBYTES.ILOFFYES & ~DMA_CFG_NBYTES_ILOFFYES_NBYTES_MASK) | + DMA_CFG_NBYTES_ILOFFYES_NBYTES(u32Size); + } + } +} + +/** + * @brief Get whether current channel to channel trig is enabled when inner loop complete + * @note this field shall always be same with the beginning channel to channel trig enable flag + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true channel to channel trig is enabled when inner loop complete + * @return false channel to channel trig is disabled when inner loop complete + */ +LOCAL_INLINE bool DMA_HWA_GetCurrentChannelToChannelTrigEnableFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].CLC.CHTRGENNO & DMA_CFG_CLC_CHTRGENNO_CHTRGEN_MASK) >> + DMA_CFG_CLC_CHTRGENNO_CHTRGEN_SHIFT; + return (bool)((u16TmpVal != 0U) ? true : false); +} + +/** + * @brief Get the target channel when current channel to channel trig is enabled + * @note this field shall always be same with the beginning traget channel trig field + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint8_t the target channel + */ +LOCAL_INLINE uint8_t DMA_HWA_GetCurrentChannelToChannelTrigChannel(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal; + if (DMA_HWA_GetCurrentChannelToChannelTrigEnableFlag(pDma, u8Channel) == true) + { + u16TmpVal = (pDma->CFG[u8Channel].CLC.CHTRGENYES & DMA_CFG_CLC_CHTRGENYES_TRGCH_MASK) >> + DMA_CFG_CLC_CHTRGENYES_TRGCH_SHIFT; + } + else + { + u16TmpVal = 0U; + } + return (uint8_t)u16TmpVal; +} + +/** + * @brief Get the current loop count + * The current loop count is the same as the beginning loop count initially, and it will decrement + * each time a inner loop finishes + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint16_t the current loop count + */ +LOCAL_INLINE uint16_t DMA_HWA_GetCurrentLoopCount(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal; + if (DMA_HWA_GetCurrentChannelToChannelTrigEnableFlag(pDma, u8Channel) == false) + { + u16TmpVal = (pDma->CFG[u8Channel].CLC.CHTRGENNO & DMA_CFG_CLC_CHTRGENNO_CLC_MASK) >> DMA_CFG_CLC_CHTRGENNO_CLC_SHIFT; + } + else + { + u16TmpVal = (pDma->CFG[u8Channel].CLC.CHTRGENYES & DMA_CFG_CLC_CHTRGENYES_CLC_MASK) >> DMA_CFG_CLC_CHTRGENYES_CLC_SHIFT; + } + return u16TmpVal; +} + +/** + * @brief Get whether beginning channel to channel trig is enabled when inner loop complete + * @note this field shall always be same with the current channel to channel trig enable flag + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true channel to channel trig is enabled when inner loop complete + * @return false channel to channel trig is disabled when inner loop complete + */ +LOCAL_INLINE bool DMA_HWA_GetBeginningChannelToChannelTrigEnableFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].BLC.CHTRGENNO & DMA_CFG_BLC_CHTRGENNO_CHTRGEN_MASK) >> + DMA_CFG_BLC_CHTRGENNO_CHTRGEN_SHIFT; + return (bool)((u16TmpVal != 0U) ? true : false); +} + +/** + * @brief Get the target channel when beginning channel to channel trig is enabled + * @note this field shall always be same with the current traget channel trig field + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint8_t the target channel + */ +LOCAL_INLINE uint8_t DMA_HWA_GetBeginningChannelToChannelTrigChannel(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal; + if (DMA_HWA_GetBeginningChannelToChannelTrigEnableFlag(pDma, u8Channel) == true) + { + u16TmpVal = (pDma->CFG[u8Channel].BLC.CHTRGENYES & DMA_CFG_BLC_CHTRGENYES_TRGCH_MASK) >> + DMA_CFG_BLC_CHTRGENYES_TRGCH_SHIFT; + } + else + { + u16TmpVal = 0U; + } + return (uint8_t)u16TmpVal; +} + +/** + * @brief Get the beginning loop count + * This field specifies how many inner loops will be executed in a DMA transfer + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint16_t the beginning loop count + */ +LOCAL_INLINE uint16_t DMA_HWA_GetBeginningLoopCount(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal; + if (DMA_HWA_GetBeginningChannelToChannelTrigEnableFlag(pDma, u8Channel) == false) + { + u16TmpVal = (pDma->CFG[u8Channel].BLC.CHTRGENNO & DMA_CFG_BLC_CHTRGENNO_BLC_MASK) >> DMA_CFG_BLC_CHTRGENNO_BLC_SHIFT; + } + else + { + u16TmpVal = (pDma->CFG[u8Channel].BLC.CHTRGENYES & DMA_CFG_BLC_CHTRGENYES_BLC_MASK) >> DMA_CFG_BLC_CHTRGENYES_BLC_SHIFT; + } + return u16TmpVal; +} + +/** + * @brief Set channel to channel trig when inner loop complete + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param bEnable whether to enbable channel to channel trig when inner loop complete + * @param u8TrigChannel the target channel + */ +LOCAL_INLINE void DMA_HWA_SetChannelToChannelTrig(DMA_Type *const pDma, uint8_t u8Channel, bool bEnable, + uint8_t u8TrigChannel) +{ + if (bEnable == false) + { + if (DMA_HWA_GetBeginningChannelToChannelTrigEnableFlag(pDma, u8Channel) == true) + { + pDma->CFG[u8Channel].BLC.CHTRGENNO &= ~(DMA_CFG_BLC_CHTRGENNO_CHTRGEN_MASK); + pDma->CFG[u8Channel].CLC.CHTRGENNO &= ~(DMA_CFG_CLC_CHTRGENNO_CHTRGEN_MASK); + } + } + else + { + pDma->CFG[u8Channel].BLC.CHTRGENYES = (pDma->CFG[u8Channel].BLC.CHTRGENYES & + ~(DMA_CFG_BLC_CHTRGENYES_CHTRGEN_MASK | DMA_CFG_BLC_CHTRGENYES_TRGCH_MASK)) | + DMA_CFG_BLC_CHTRGENYES_CHTRGEN(bEnable) | DMA_CFG_BLC_CHTRGENYES_TRGCH(u8TrigChannel); + pDma->CFG[u8Channel].CLC.CHTRGENYES = (pDma->CFG[u8Channel].CLC.CHTRGENYES & + ~(DMA_CFG_CLC_CHTRGENYES_CHTRGEN_MASK | DMA_CFG_CLC_CHTRGENYES_TRGCH_MASK)) | + DMA_CFG_CLC_CHTRGENYES_CHTRGEN(bEnable) | DMA_CFG_CLC_CHTRGENYES_TRGCH(u8TrigChannel); + } +} + +/** + * @brief Set the loop count of the DMA transfer + * This field specifies how many inner loops will be executed in a DMA transfer + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param u16LoopCnt the inner loop count in a DMA transfer + */ +LOCAL_INLINE void DMA_HWA_SetLoopCount(DMA_Type *const pDma, uint8_t u8Channel, uint16_t u16LoopCnt) +{ + if (DMA_HWA_GetBeginningChannelToChannelTrigEnableFlag(pDma, u8Channel) == false) + { + pDma->CFG[u8Channel].BLC.CHTRGENNO = (pDma->CFG[u8Channel].BLC.CHTRGENNO & ~DMA_CFG_BLC_CHTRGENNO_BLC_MASK) | + DMA_CFG_BLC_CHTRGENNO_BLC(u16LoopCnt); + pDma->CFG[u8Channel].CLC.CHTRGENNO = (pDma->CFG[u8Channel].CLC.CHTRGENNO & ~DMA_CFG_CLC_CHTRGENNO_CLC_MASK) | + DMA_CFG_CLC_CHTRGENNO_CLC(u16LoopCnt); + } + else + { + pDma->CFG[u8Channel].BLC.CHTRGENYES = (pDma->CFG[u8Channel].BLC.CHTRGENYES & ~DMA_CFG_BLC_CHTRGENYES_BLC_MASK) | + DMA_CFG_BLC_CHTRGENYES_BLC(u16LoopCnt); + pDma->CFG[u8Channel].CLC.CHTRGENYES = (pDma->CFG[u8Channel].CLC.CHTRGENYES & ~DMA_CFG_CLC_CHTRGENYES_CLC_MASK) | + DMA_CFG_CLC_CHTRGENYES_CLC(u16LoopCnt); + } +} + +/** + * @brief Get the unalign modulo index selection + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint8_t the unalign modulo index selection + */ +LOCAL_INLINE uint8_t DMA_HWA_GetUnalignModuloSel(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].CSR & DMA_CFG_CSR_UMS_MASK) >> DMA_CFG_CSR_UMS_SHIFT; + return (uint8_t)u16TmpVal; +} + +/** + * @brief Set the unalign modulo index selection + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param u8UnalignModuloSel the unalign modulo index selection + */ +LOCAL_INLINE void DMA_HWA_SetUnalignModuloSel(DMA_Type *const pDma, uint8_t u8Channel, uint8_t u8UnalignModuloSel) +{ + pDma->CFG[u8Channel].CSR = (pDma->CFG[u8Channel].CSR & ~DMA_CFG_CSR_UMS_MASK) | DMA_CFG_CSR_UMS(u8UnalignModuloSel); +} + +/** + * @brief Get the target channel to trig when outer loop is completed + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint8_t the target channel + */ +LOCAL_INLINE uint8_t DMA_HWA_GetOuterLoopTrigChannel(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].CSR & DMA_CFG_CSR_OTRGCH_MASK) >> DMA_CFG_CSR_OTRGCH_SHIFT; + return (uint8_t)u16TmpVal; +} + +/** + * @brief Set the target channel to trig when outer loop is completed + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param u8TrigChannel the target channel + */ +LOCAL_INLINE void DMA_HWA_SetOuterLoopTrigChannel(DMA_Type *const pDma, uint8_t u8Channel, uint8_t u8TrigChannel) +{ + pDma->CFG[u8Channel].CSR = (pDma->CFG[u8Channel].CSR & ~DMA_CFG_CSR_OTRGCH_MASK) | DMA_CFG_CSR_OTRGCH(u8TrigChannel); +} + +/** + * @brief Get whether the transfer is done on the selected channel + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true the transfer is done + * @return false the transfer has not done + */ +LOCAL_INLINE bool DMA_HWA_GetChannelDoneStatus(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].CSR & DMA_CFG_CSR_DONE_MASK) >> DMA_CFG_CSR_DONE_SHIFT; + return (bool)((u16TmpVal != 0U) ? true : false); +} + +/** + * @brief Get the active status of the DMA channel + * This flag signals the channel is currently in execution. It is set when channel service begins, + * and is cleared by the DMA as the inner loop completes or when any error condition is detected + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true the channel is in execution + * @return false the channel is idle + */ +LOCAL_INLINE DMA_RunningStatusType DMA_HWA_GetChannelActiveStatus(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].CSR & DMA_CFG_CSR_ACTIVE_MASK) >> DMA_CFG_CSR_ACTIVE_SHIFT; + return (DMA_RunningStatusType)u16TmpVal; +} + +/** + * @brief Get channel to channel trig is enabled when outer loop is completed + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true the target channel will be trigged when outer loop is completed + * @return false the channel to channel trig when outer loop is completed is disabled + */ +LOCAL_INLINE bool DMA_HWA_GetOuterLoopTrigEnableFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].CSR & DMA_CFG_CSR_OCHTRGEN_MASK) >> DMA_CFG_CSR_OCHTRGEN_SHIFT; + return (bool)((u16TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable channel to channel trig when outer loop is completed + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param bEnable whether to enable channel to channel trig when outer loop is completed + */ +LOCAL_INLINE void DMA_HWA_SetOuterLoopTrigEnableFlag(DMA_Type *const pDma, uint8_t u8Channel, bool bEnable) +{ + pDma->CFG[u8Channel].CSR = (pDma->CFG[u8Channel].CSR & ~DMA_CFG_CSR_OCHTRGEN_MASK) | DMA_CFG_CSR_OCHTRGEN(bEnable); +} + +/** + * @brief Get whether DMA request will be disabled automatically when outer loop is completed + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true DMA request will be disabled automatically when outer loop is completed + * @return false DMA request will not be cleared when outer loop is completed + */ +LOCAL_INLINE bool DMA_HWA_GetAutoDisableReuqestEnableFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].CSR & DMA_CFG_CSR_DREQ_MASK) >> DMA_CFG_CSR_DREQ_SHIFT; + return (bool)((u16TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to disable DMA request automatically when outer loop is completed + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param bEnable whether to disable DMA request automatically when outer loop is completed + */ +LOCAL_INLINE void DMA_HWA_SetAutoDisableReuqestEnableFlag(DMA_Type *const pDma, uint8_t u8Channel, bool bEnable) +{ + pDma->CFG[u8Channel].CSR = (pDma->CFG[u8Channel].CSR & ~DMA_CFG_CSR_DREQ_MASK) | DMA_CFG_CSR_DREQ(bEnable); +} + +/** + * @brief Get whether DMA interrupt wiil be generated when the outer loop is half done + * @note When outer loop count is 1, do not enable half complete interrupt + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true DMA will generate interrupt when outer loop is half done + * @return true DMA will not generate interrupt when outer loop is half done + */ +LOCAL_INLINE bool DMA_HWA_GetHalfCompleteInterruptEnableFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].CSR & DMA_CFG_CSR_INTHALF_MASK) >> DMA_CFG_CSR_INTHALF_SHIFT; + return (bool)((u16TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable DMA interrupt when the outer loop is half done + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param bEnable whether to enable DMA interrupt when the outer loop is half done + */ +LOCAL_INLINE void DMA_HWA_SetHalfCompleteInterruptEnableFlag(DMA_Type *const pDma, uint8_t u8Channel, bool bEnable) +{ + pDma->CFG[u8Channel].CSR = (pDma->CFG[u8Channel].CSR & ~DMA_CFG_CSR_INTHALF_MASK) | DMA_CFG_CSR_INTHALF(bEnable); +} + +/** + * @brief Get whether DMA interrupt is enabled when DMA transfer is completed + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true DMA will generate interrupt when outer loop is completed + * @return false DMA will not generate interrupt when outer loop is completed + */ +LOCAL_INLINE bool DMA_HWA_GetTransferCompleteInterruptEnableFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].CSR & DMA_CFG_CSR_INTOUTER_MASK) >> DMA_CFG_CSR_INTOUTER_SHIFT; + return (bool)((u16TmpVal != 0U) ? true : false); +} + +/** + * @brief Enable DMA transfer complete interrupt + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + */ +LOCAL_INLINE void DMA_HWA_EnableTransferCompleteInterrupt(DMA_Type *const pDma, uint8_t u8Channel) +{ + pDma->CFG[u8Channel].CSR |= DMA_CFG_CSR_INTOUTER_MASK; +} + +/** + * @brief Disable DMA transfer complete interrupt + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + */ +LOCAL_INLINE void DMA_HWA_DisableTransferCompleteInterrupt(DMA_Type *const pDma, uint8_t u8Channel) +{ + pDma->CFG[u8Channel].CSR &= ~DMA_CFG_CSR_INTOUTER_MASK; +} + +/** + * @brief Get whether the DMA start is requested but has not been executed + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return true the DMA start is requested but has not been executed + * @return false the DMA start is not requested or it has started execution + */ +LOCAL_INLINE bool DMA_HWA_GetWaitStartFlag(const DMA_Type *const pDma, uint8_t u8Channel) +{ + uint16_t u16TmpVal = (pDma->CFG[u8Channel].CSR & DMA_CFG_CSR_START_MASK) >> DMA_CFG_CSR_START_SHIFT; + return (bool)((u16TmpVal != 0U) ? true : false); +} + +/** + * @brief Get DMA channel control and status + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @return uint16_t control and status of the selected channel + */ +LOCAL_INLINE uint16_t DMA_HWA_GetChannelControlStatus(const DMA_Type *const pDma, uint8_t u8Channel) +{ + return pDma->CFG[u8Channel].CSR; +} + +/** + * @brief Set DMA channel control and status + * + * @param pDma the base address of the DMA instance + * @param u8Channel the selected channel + * @param u16Setting control settings of the selected channel + */ +LOCAL_INLINE void DMA_HWA_SetChannelControlStatus(DMA_Type *const pDma, uint8_t u8Channel, uint16_t u16Setting) +{ + pDma->CFG[u8Channel].CSR = u16Setting; +} + +/** @}*/ + +#endif /* _HWA_DMA_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_dmamux.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_dmamux.h new file mode 100644 index 0000000..8c31777 --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_dmamux.h @@ -0,0 +1,210 @@ +/** + * @file HwA_dmamux.h + * @author Flagchip0126 + * @brief Hardware access layer for DMAMUX + * @version 0.1.0 + * @date 2024-01-15 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-15 Flagchip0126 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef _HWA_DMAMUX_H_ +#define _HWA_DMAMUX_H_ + +#include "device_header.h" + +/** + * @defgroup HwA_dmamux + * @ingroup fc7xxx_driver_dma + * @{ + */ + +/** + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum +{ + DMA_REQ_DISABLED = 0U, + DMA_REQ_FCIIC0_RX = 1U, + DMA_REQ_FCIIC0_TX = 2U, + DMA_REQ_FCIIC1_RX = 3U, + DMA_REQ_FCIIC1_TX = 4U, + DMA_REQ_FCSPI0_RX = 5U, + DMA_REQ_FCSPI0_TX = 6U, + DMA_REQ_FCSPI1_RX = 7U, + DMA_REQ_FCSPI1_TX = 8U, + DMA_REQ_FCSPI2_RX = 9U, + DMA_REQ_FCSPI2_TX = 10U, + DMA_REQ_FCSPI3_RX = 11U, + DMA_REQ_FCSPI3_TX = 12U, + DMA_REQ_FCSPI4_RX = 13U, + DMA_REQ_FCSPI4_TX = 14U, + DMA_REQ_FCSPI5_RX = 15U, + DMA_REQ_FCSPI5_TX = 16U, + /* 17 ~ 22 reserved */ + DMA_REQ_FLEXCAN0 = 23U, + DMA_REQ_FLEXCAN1 = 24U, + DMA_REQ_FLEXCAN2 = 25U, + DMA_REQ_FLEXCAN3 = 26U, + /* 27 ~ 32 reserved */ + DMA_REQ_ADC0 = 33U, + DMA_REQ_ADC1 = 34U, + /* 35 ~ 40 reserved */ + DMA_REQ_FCUART0_RX = 41U, + DMA_REQ_FCUART0_TX = 42U, + DMA_REQ_FCUART1_RX = 43U, + DMA_REQ_FCUART1_TX = 44U, + DMA_REQ_FCUART2_RX = 45U, + DMA_REQ_FCUART2_TX = 46U, + DMA_REQ_FCUART3_RX = 47U, + DMA_REQ_FCUART3_TX = 48U, + DMA_REQ_FCUART4_RX = 49U, + DMA_REQ_FCUART4_TX = 50U, + DMA_REQ_FCUART5_RX = 51U, + DMA_REQ_FCUART5_TX = 52U, + DMA_REQ_FCUART6_RX = 53U, + DMA_REQ_FCUART6_TX = 54U, + DMA_REQ_FCUART7_RX = 55U, + DMA_REQ_FCUART7_TX = 56U, + /* 57 ~ 58 reserved */ + DMA_REQ_TPU0 = 59U, + DMA_REQ_TPU1 = 60U, + DMA_REQ_TPU2 = 61U, + DMA_REQ_TPU3 = 62U, + DMA_REQ_TPU4 = 63U, + DMA_REQ_TPU5 = 64U, + DMA_REQ_TPU6 = 65U, + DMA_REQ_TPU7 = 66U, + DMA_REQ_TPU8 = 67U, + DMA_REQ_TPU9 = 68U, + DMA_REQ_TPU10 = 69U, + DMA_REQ_TPU11 = 70U, + DMA_REQ_TPU12 = 71U, + DMA_REQ_TPU13 = 72U, + DMA_REQ_TPU14 = 73U, + DMA_REQ_TPU15 = 74U, + DMA_REQ_TPU16TO23 = 75U, + DMA_REQ_TPU24TO31 = 76U, + DMA_REQ_PORTA = 77U, + DMA_REQ_PORTB = 78U, + DMA_REQ_PORTC = 79U, + DMA_REQ_PORTD = 80U, + DMA_REQ_PORTE = 81U, + /* 82 ~ 85 reserved */ + DMA_REQ_AONTIMER0 = 86U, + DMA_REQ_CMP0 = 87U, + DMA_REQ_CMP1 = 88U, + /* 89 reserved */ + DMA_REQ_PTIMER0 = 90U, + DMA_REQ_PTIMER1 = 91U, + /* 92 ~ 97 reserved */ + DMA_REQ_FTU0_ALL_CH_OR = 98U, + DMA_REQ_FTU1_ALL_CH_OR = 99U, + DMA_REQ_FTU2_ALL_CH_OR = 100U, + DMA_REQ_FTU3_ALL_CH_OR = 101U, + DMA_REQ_FTU4_ALL_CH_OR = 102U, + DMA_REQ_FTU5_ALL_CH_OR = 103U, + DMA_REQ_FTU6_ALL_CH_OR = 104U, + DMA_REQ_FTU7_ALL_CH_OR = 105U, + /* 106 ~ 109 reserved */ + DMA_REQ_SENT0_CH0_FAST = 110U, + DMA_REQ_SENT0_CH1_FAST = 111U, + DMA_REQ_SENT0_CH2_FAST = 112U, + DMA_REQ_SENT0_CH3_FAST = 113U, + /* 114 ~ 117 reserved */ + DMA_REQ_SENT0_CH0_SLOW = 118U, + DMA_REQ_SENT0_CH1_SLOW = 119U, + DMA_REQ_SENT0_CH2_SLOW = 120U, + DMA_REQ_SENT0_CH3_SLOW = 121U, + /* 122 ~ 125 reserved */ + DMA_REQ_ALWAYS_ENABLE_0 = 126U, + DMA_REQ_ALWAYS_ENABLE_1 = 127U +} DMA_RequestSourceType; + +/** + * @brief Get whether DMAMUX is enabled for the specified DMA channel + * + * @param pDmamux the base address of the DMAMUX instance + * @param u8Channel the selected DMA channel + * @return true DMAMUX is enabled for the specified DMA channel + * @return false DMAMUX is disabled for the specified DMA channel + */ +LOCAL_INLINE bool DMAMUX_HWA_GetEnableFlag(const DMAMUX_Type *const pDmamux, uint8_t u8Channel) +{ + uint8_t u8TmpVal = (pDmamux->CHCFG[u8Channel] & DMAMUX_CHCFG_ENBL_MASK) >> DMAMUX_CHCFG_ENBL_SHIFT; + return (bool)((u8TmpVal != 0U) ? true : false); +} + +/** + * @brief Get the request source for the specified DMA channel + * + * @param pDmamux the base address of the DMAMUX instance + * @param u8Channel the selected DMA channel + * @return DMA_RequestSourceType the request source of the specified DMA channel + */ +LOCAL_INLINE DMA_RequestSourceType DMAMUX_HWA_GetRequestSource(const DMAMUX_Type *const pDmamux, uint8_t u8Channel) +{ + uint8_t u8TmpVal = (pDmamux->CHCFG[u8Channel] & DMAMUX_CHCFG_SOURCE_MASK) >> DMAMUX_CHCFG_SOURCE_SHIFT; + return (DMA_RequestSourceType)u8TmpVal; +} + +/** + * @brief Set the request source for the specified DMA channel + * + * @param pDmamux the base address of the DMAMUX instance + * @param u8Channel the selected DMA channel + * @param bEnable whether to enable DMAMUX for the specified DMA channel + * @param eReqSrc the request source to set for the specified DMA channel + */ +LOCAL_INLINE void DMAMUX_HWA_SetRequestSource(DMAMUX_Type *const pDmamux, uint8_t u8Channel, bool bEnable, + DMA_RequestSourceType eReqSrc) +{ + pDmamux->CHCFG[u8Channel] = (pDmamux->CHCFG[u8Channel] & ~(DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE_MASK)) | + DMAMUX_CHCFG_ENBL(bEnable) | DMAMUX_CHCFG_SOURCE(eReqSrc); +} + +/** + * @brief Get whether periodic trig is enabled for the specified DMA channel + * + * @note Only DMA channel 0~3 supports periodic trig + * + * @param pDmamux the base address of the DMAMUX instance + * @param u8Channel the selected DMA channel + * @return true periodic trig is enabled for the specified DMA channel + * @return true periodic trig is disabled for the specified DMA channel + */ +LOCAL_INLINE bool DMAMUX_HWA_GetPeriodicTrigFlag(const DMAMUX_Type *const pDmamux, uint8_t u8Channel) +{ + uint8_t u8TmpVal = (pDmamux->CHTRG & (DMAMUX_CHTRG_TRIG_MASK << u8Channel)) >> u8Channel; + return (bool)((u8TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable periodic trig for the specified DMA channel + * + * @note Only DMA channel 0~3 supports periodic trig + * + * @param pDmamux the base address of the DMAMUX instance + * @param u8Channel the selected DMA channel + * @param bEnable whether to enable periodic trig for the specified DMA channel + */ +LOCAL_INLINE void DMAMUX_HWA_SetPeriodicTrigFlag(DMAMUX_Type *const pDmamux, uint8_t u8Channel, bool bEnable) +{ + pDmamux->CHTRG = (pDmamux->CHTRG & ~(DMAMUX_CHTRG_TRIG_MASK << u8Channel)) | (DMAMUX_CHTRG_TRIG(bEnable) << u8Channel); +} + +/** @}*/ + +#endif /* _HWA_DMAMUX_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_eim.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_eim.h new file mode 100644 index 0000000..073a970 --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_eim.h @@ -0,0 +1,276 @@ +/** + * @file HwA_eim.h + * @author Flagchip + * @brief FC7xxx FCEim register API + * @version 0.1.0 + * @date 2024-01-14 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-14 qxw0100 N/A FC7240 Eim first version + *********************************************************************************/ + +#ifndef HWA_INCLUDE_HWA_EIM_H_ +#define HWA_INCLUDE_HWA_EIM_H_ +#include "device_header.h" +#define EIM_MAXCHANNEL 76U /*!< EIM max channel support */ + +/** + * @defgroup HwA_eim + * @ingroup HwA_eim + * @{ + */ + +/** @brief EIM channel number configuration type */ +typedef enum +{ + EIM_MAM0_S0 = 0U, /*!< Channel 0 SCM Matrix Access Monitor Error Inection0(MAM0_S0) */ + EIM_MAM0_S1 = 1U, /*!< Channel 1 SCM Matrix Access Monitor Error Inection1(MAM0_S1) */ + EIM_MAM0_S2 = 2U, /*!< Channel 2 SCM Matrix Access Monitor Error Inection2(MAM0_S2) */ + EIM_MAM0_S3 = 4U, /*!< Channel 4 SCM Matrix Access Monitor Error Inection3(MAM0_S3) */ + EIM_MAM0_S4 = 5U, /*!< Channel 5 SCM Matrix Access Monitor Error Inection4(MAM0_S4) */ + EIM_MAM0_S5 = 7U, /*!< Channel 7 SCM Matrix Access Monitor Error Inection5(MAM0_S5) */ + EIM_MAM0_S6 = 8U, /*!< Channel 8 SCM Matrix Access Monitor Error Inection6(MAM0_S6) */ + EIM_MAM0_S7 = 9U, /*!< Channel 9 SCM Matrix Access Monitor Error Inection7(MAM0_S7) */ + EIM_MAM0_S8 = 10U, /*!< Channel 10 SCM Matrix Access Monitor Error Inection8(MAM0_S8) */ + EIM_CPU0_AHBM = 11U, /*!< Channel 11 SCM Matrix Access Monitor Error Inection9(CPU0_AHBM) */ + EIM_CPU0_AHBP = 12U, /*!< Channel 12 SCM Matrix Access Monitor Error Inection10(CPU0_AHBP) */ + EIM_HSM = 18U, /*!< Channel 18 SCM Matrix Access Monitor Error Inection12(HSM) */ + EIM_DMA0 = 19U, /*!< Channel 19 SCM Matrix Access Monitor Error Inection13(DMA0) */ + EIM_CPU0_AHBS = 21U, /*!< Channel 21 SCM Matrix Access Monitor Error Inection11(CPU0_AHBS) */ + EIM_CPU0_ITCM = 24U, /*!< Channel 24 CPU0_ITCM */ + EIM_CPU0_DTCM0 = 25U, /*!< Channel 25 CPU0_DTCM0 */ + EIM_CPU0_DTCM1 = 26U, /*!< Channel 26 CPU0_DTCM1 */ + EIM_SRAM0 = 33U, /*!< Channel 33 SRAM0_INJECTION */ + EIM_SRAM1 = 34U, /*!< Channel 34 SRAM1_INJECTION */ + EIM_CPU0DCACHE_DATA0_01 = 36U, /*!< Channel 36 CPU0_DCACHE_DATA0_01 Injection */ + EIM_CPU0DCACHE_DATA0_23 = 37U, /*!< Channel 37 CPU0_DCACHE_DATA0_23 Injection */ + EIM_CPU0DCACHE_DATA1_01 = 38U, /*!< Channel 38 CPU0_DCACHE_DATA1_01 Injection */ + EIM_CPU0DCACHE_DATA1_23 = 39U, /*!< Channel 39 CPU0_DCACHE_DATA1_23 Injection */ + EIM_CPU0DCACHE_TAG_01 = 40U, /*!< Channel 40 CPU0_DCACHE_TAG_01 Injection */ + EIM_CPU0DCACHE_TAG_23 = 41U, /*!< Channel 41 CPU0_DCACHE_TAG_23 Injection */ + EIM_CPU0ICACHE_DATA0 = 42U, /*!< Channel 42 CPU0_ICACHE_DATA0 Injection */ + EIM_CPU0ICACHE_DATA1 = 43U, /*!< Channel 43 CPU0_ICACHE_DATA1 Injection */ + EIM_CPU0ICACHE_TAG = 44U, /*!< Channel 44 CPU0_ICACHE_TAG Injection */ + EIM_SCM_S5_DOWNSIZE = 63U, /*!< Channel 63 SCM S5 64:32 DownSize Monitor Error Injection */ + EIM_DMA0_CFG = 65U, /*!< Channel 65 DMA0_CFG_ECC Injection */ + EIM_ROM_ECC = 67U, /*!< Channel 67 ROM_ECC Injection */ + EIM_SCM_S5_DOWNSIZE_AHBS = 68U, /*!< Channel 68 SCM S5 DownSize ECC Check with AHBS Error Injection */ + EIM_CPU0AHBP_AHBS_MONITOR = 70U, /*!< Channel 70 SCM CPU0 AHBP and AHBS gasket Monitor Error Injection */ + EIM_SCM_S8_DOWNSIZE_MONITOR = 75U, /*!< Channel 75 SCM S8 64:32 DownSize Monitor Error Injection */ + EIM_RAM_DECODER_MONITOR = 77U, /*!< Channel 77 RAM Decoder Monitor Error Injection */ + EIM_AFCB0_MONITOR = 78U, /*!< Channel 78 AFCB0 Monitor Error Injection */ + EIM_AFCB1_MONITOR = 79U, /*!< Channel 79 AFCB1 Monitor Error Injection */ + EIM_CPU0_OVERLAY_MONITOR = 80U, /*!< Channel 80 CPU0 Overlay Monitor */ + EIM_HSM_DRAM = 82U, /*!< Channel 82 HSM DRAM ECC Error Injection */ + EIM_HSM_IRAM = 83U, /*!< Channel 83 HSM IRAM ECC Error Injection */ +} EIM_ChannelType; + +/** @brief EIM Lockstep channel configuration type */ +typedef enum +{ + EIM_CPU0_LOCKSTEP, /*!< CPU0 LOCKSTEP Injection */ + EIM_CHNTYPE_RESVD, + EIM_DMA0_LOCKSTEP, /*!< DMA0 LOCKSTEP Injection */ +} EIM_CPU_ChnType; + +/** @brief EIM CPU monitor configuration type */ +typedef enum +{ + EIM_MONITOR0, /*!< CPU0 LOCKSTEP monitor0 Injection */ + EIM_MONITOR1, /*!< CPU0 LOCKSTEP monitor1 Injection */ +} EIM_MONType; + +/** @brief Eim return type. */ + +typedef enum +{ + EIM_STATUS_SUCCESS = 0U, /*!< EIM status success */ + EIM_STATUS_PARAM_INVALID = 1U /*!< EIM status parameter invalid */ +} EIM_RetType; + +/** + * @brief Select the EIM DWP mode + * + */ +typedef enum +{ + EIM_CPU0ALLOWED_0 = 0U, /**< cpu0 is allowed */ + EIM_CPU0ALLOWED_1 = 1U, /**< cpu0 is allowed */ +} EIM_DWPType; + +/** + * @brief Select error injection bus sel + * + */ +typedef enum +{ + EIM_BUSREG0 = 0U, /**< Sel bus REG0 to injection */ + EIM_BUSREG1 = 1U, /**< Sel bus REG1 to injection */ + EIM_BUSREG2 = 2U, /**< Sel bus REG2 to injection */ + EIM_BUSREG3 = 3U /**< Sel bus REG3 to injection */ +} EIM_BUSChnType; +/** + * @brief Select the EIM InitType + * + */ +typedef struct +{ + uint8_t u8EimChn; + uint8_t u8BusSelIdx; + uint8_t u8Attreenable; + uint8_t u8AttrPosition; + uint8_t u8Addreenable; + uint8_t u8AddrePosition; + uint8_t u8Data0enable; + uint8_t u8Data0Val; + uint8_t u8Data1enable; + uint8_t u8Data1Val; +} EIM_InitType; + +/** + * @brief Select the CPU Lockstep InitType + * + */ +typedef struct +{ + uint8_t u8CpuChn; + uint8_t u8Monitor0Set; + uint8_t u8Monitor0Clr; + uint8_t u8Monitor1Set; + uint8_t u8Monitor1Clr; +} EIM_CpuLockType; + + +/** + * @brief Enable EIM Global Error Injection + * + */ +LOCAL_INLINE void EIM_HWA_EnableGlobalErrorInjection(void) +{ + EIM->CR = 1U; +} + +/** + * @brief Disable EIM Global Error Injection + * + */ +LOCAL_INLINE void EIM_HWA_DisableGlobalErrorInjection(void) +{ + EIM->CR &= ~(uint32_t) EIM_CR_GEIEN_MASK; +} + +/** + * @brief get EIM channel N control register, N:0~82 + * + * @return EIM channel N control register value + */ +LOCAL_INLINE uint32_t EIM_HWA_Get_CtrlRegn(uint8_t idx) +{ + uint32_t u32RegValue; + u32RegValue = EIM->CTRL_REG[idx]; + return u32RegValue; +} + +/** + * @brief get EIM bus register, idx:0~3 + * + * @return EIM bus register value + */ +LOCAL_INLINE uint32_t EIM_HWA_Get_BUSRegn(uint8_t idx) +{ + uint32_t u32RegValue; + u32RegValue = EIM->BUS_REG[idx]; + return u32RegValue; +} + +/** + * @brief Get EIM_CTRL_GEGn register DWP lock status + * @param u8idx index (0~82) + * @return Lock status + */ +LOCAL_INLINE uint8_t EIM_HWA_GetCtrlDWPLockStatus(uint8_t u8idx) +{ + uint32_t u32RegValue; + u32RegValue = EIM->CTRL_REG[u8idx]; + u32RegValue = (u32RegValue & EIM_CTRL_REG_DWP_LOCK_MASK) >> EIM_CTRL_REG_DWP_LOCK_SHIFT; + return (uint8_t)((u32RegValue != 0U) ? true : false); +} + +/** + * @brief set EIM_CTRL_GEGn register DWP lock mode, idx:0~76 + * + * @param u8idx index (0~82) + * @param u8DwpMode DWP mode + */ +LOCAL_INLINE void EIM_HWA_Set_CtrlLockMode(uint8_t u8idx, uint8_t u8DwpMode) +{ + uint32_t u32Value = EIM->CTRL_REG[u8idx]; + EIM->CTRL_REG[u8idx] = ((u32Value & (~(uint32_t)EIM_CTRL_REG_DWP_MASK)) | EIM_CTRL_REG_DWP(u8DwpMode)); +} + +/** + * @brief set EIM_CTRL_GEGn register DWP lock status, idx:0~76 + * + * @param u8idx index (0~82) + * @param u8Enable enable or disable + */ +LOCAL_INLINE void EIM_HWA_CtrlRegnWritePermit(uint8_t u8idx) +{ + uint32_t u32Value = EIM->CTRL_REG[u8idx]; + EIM->CTRL_REG[u8idx] = (u32Value | EIM_CTRL_REG_DWP_LOCK_MASK); +} + +/** + * @brief set eim channel N control register + * + * @param idx index (0~82) + * @param u32RegValue access control value + */ +LOCAL_INLINE void EIM_HWA_Set_CtrlRegn(uint8_t idx, uint32_t u32RegValue) +{ + EIM->CTRL_REG[idx] = u32RegValue; +} + +/** + * @brief set EIM CPU LOCKSTEP error injection register, idx:0~2 + * + * @param idx index (0~2) + * @param u32RegValue access control value + */ +LOCAL_INLINE void EIM_HWA_Set_CPULockstep(uint8_t idx, uint32_t u32RegValue) +{ + *((volatile uint32_t *)(&(EIM->CPU0_LOCKSTEP) + (int32_t)idx)) = u32RegValue; +} + +/** + * @brief set EIM CPU LOCKSTEP error injection register, idx:0~2 + * + * @param idx index (0~2) + * @return access control value + */ +LOCAL_INLINE uint32_t EIM_HWA_Get_CPULockstep(uint8_t idx) +{ + return *((volatile uint32_t *)(&(EIM->CPU0_LOCKSTEP) + (int32_t)idx)); +} + +/** + * @brief set EIM bus register, idx:0~3 + * + * @param idx index (0~3) + * @param u32RegValue access control value + */ +LOCAL_INLINE void EIM_HWA_Set_BUSRegn(uint8_t idx, uint32_t u32RegValue) +{ + EIM->BUS_REG[idx] |= u32RegValue; +} + + +/** @}*/ +#endif /* HWA_INCLUDE_HWA_EIM_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_erm.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_erm.h new file mode 100644 index 0000000..b114c70 --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_erm.h @@ -0,0 +1,119 @@ +/** + * @file HwA_erm.h + * @author Flagchip + * @brief FC7xxx erm driver type definition and API + * @version 0.1.0 + * @date 2024-01-14 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-14 qxw0100 N/A FC7240 Erm first version + ******************************************************************************** */ + +#ifndef HWA_INCLUDE_HWA_ERM_H_ +#define HWA_INCLUDE_HWA_ERM_H_ +#include "device_header.h" + +#define ERM_SR_MASK 0xCCCCCCCCu + + +/** + * @defgroup HwA_erm + * @ingroup HwA_erm + * @{ + */ + +/** @brief ERM configuration type */ +typedef enum +{ + ERM_NONE_CORRECTABLE = 1U, /*!< select Non-correctable interrupt report */ + ERM_SINGLE_BIT = 2U /*!< select single correction interrupt report */ +} ERM_InterruptType; + + +/** @brief ERM configuration type */ +typedef enum +{ + ERM_PFLASH0_ECC = 1U, /*!< PFlash0 ECC Error */ + ERM_PFLASH1_ECC = 2U, /*!< PFlash1 ECC Error */ + ERM_DFLASH_ECC = 3U, /*!< DFlash ECC error */ + ERM_DMACFG0_ECC = 4U, /*!< DMACFG0 ECC Error */ + ERM_ROM_ECC = 6U, /*!< ROM ECC Error */ + ERM_SYSRAM0_ECC = 8U, /*!< SysRAM0 ECC ERROR */ + ERM_SYSRAM1_ECC = 9U, /*!< SysRAM1 ECC ERROR */ + ERM_CPU0ITCM_ECC = 11U, /*!< CPU0 ITCM ECC Error */ + ERM_CPU0DTCM0_ECC = 12U, /*!< CPU0 DTCM0 ECC Error */ + ERM_CPU0DTCM1_ECC = 13U, /*!< CPU0 DTCM1 ECC Error */ + ERM_CPU0ICACHE_ECC = 14U, /*!< CPU0 ICACHE ECC Error */ + ERM_CPU0DCACHE_ECC = 15U, /*!< CPU0 DCACHE ECC Error */ + ERM_HSMDRAM_ECC = 26U, /*!< HSM DRAM ECC Error */ + ERM_HSMIRAM_ECC = 27U, /*!< HSM IRAM ECC Error */ +} ERM_ChannelType; + + +/** + * @brief get ERM configuration register 0~3 + * + * @return ERM CRn value + */ +LOCAL_INLINE uint32_t ERM_HWA_Get_CRn(uint8_t idx) +{ + uint32_t u32RegValue; + u32RegValue = *((volatile uint32_t *)(&(ERM->CR0) + (uint32_t)idx)); + return u32RegValue; +} + +/** + * @brief get ERM status register 0~3 + * + * @return ERM SRn value + */ +LOCAL_INLINE uint32_t ERM_HWA_Get_SRn(uint8_t idx) +{ + uint32_t u32RegValue; + u32RegValue = *((volatile uint32_t *)(&(ERM->SR0) + (uint32_t)idx)); + return u32RegValue; +} + +/** + * @brief get ERM error address register 0~25 + * + * @return ERM error address register value + */ +LOCAL_INLINE uint32_t ERM_HWA_Get_EARn(uint8_t idx) +{ + uint32_t u32RegValue; + u32RegValue = *((const volatile uint32_t *)(&(ERM->EAR0) + (uint32_t)idx * 0x10UL/4UL)); + + return u32RegValue; +} + +/** + * @brief set erm configuration register + * + * @param idx index (0~3) + * @param u32RegValue access control value + */ +LOCAL_INLINE void ERM_HWA_Set_CRn(uint8_t idx, uint32_t u32RegValue) +{ + *((volatile uint32_t *)(&(ERM->CR0) + (int32_t)idx)) = u32RegValue; +} +/** + * @brief set erm error address register + * + * @param idx index (0~3) + * @param u32RegValue access control value + */ +LOCAL_INLINE void ERM_HWA_Set_SRn(uint8_t idx, uint32_t u32RegValue) +{ + *((volatile uint32_t *)(&(ERM->SR0) + (int32_t)idx)) = u32RegValue; +} + +/** @}*/ +#endif /* HWA_INCLUDE_HWA_ERM_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_fciic.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_fciic.h new file mode 100644 index 0000000..c10014e --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_fciic.h @@ -0,0 +1,542 @@ +/** + * @file HwA_fciic.h + * @author Flagchip + * @brief FC7xxx FCIIC hardware access layer + * @version 0.2.0 + * @date 2023-2-14 + * + * @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2022/12/31 qxw0052 N/A First version for FC7300 + * 0.2.0 2023/02/14 qxw0052 N/A Fix MISRA issues + ******************************************************************************** */ + +#ifndef _HWA_FCIIC_H_ +#define _HWA_FCIIC_H_ + +#include "device_header.h" + + +/** + * @addtogroup HwA_fciic + * @{ + */ + + +/* ################################################################################## */ +/* ################################### type define ################################## */ + + +/** + * \brief IIC Command Type Enumeration + * + */ +typedef enum +{ + FCIIC_TX_CMD_TRANSMIT = 0, /**< FCIIC_TX_CMD_TRANSMIT transmit command */ + FCIIC_TX_CMD_RECEIVE, /**< FCIIC_TX_CMD_RECEIVE receive command*/ + FCIIC_TX_CMD_STOP, /**< FCIIC_TX_CMD_STOP stop command */ + FCIIC_TX_CMD_RECANDDISCARD, /**< FCIIC_TX_CMD_RECANDDISCARD receive and discard data command*/ + FCIIC_TX_CMD_STARTANDTRANSMIT, /**< FCIIC_TX_CMD_STARTANDTRANSMIT start and then transmit data */ + FCIIC_TX_CMD_STARTANDTRANSMIT_WITHNAK/**< FCIIC_TX_CMD_STARTANDTRANSMIT_WITHNAK start and then transmit and don't care ACK */ + +} FCIIC_TX_CMDType; + + +/** + * \brief IIC Master status type enumeration + * + */ +typedef enum +{ + FCIIC_MSR_BBF_STATUS = 25U, /**< FCIIC_MSR_BBF_STATUS Bus Busy Flag */ + FCIIC_MSR_MBF_STATUS = 24U, /**< FCIIC_MSR_MBF_STATUS Master Busy Flag */ + FCIIC_MSR_DMF_STATUS = 14U, /**< FCIIC_MSR_DMF_STATUS Data Match Flag */ + FCIIC_MSR_PLTF_STATUS = 13U, /**< FCIIC_MSR_PLTF_STATUS Pin Low Timeout Flag */ + FCIIC_MSR_FEF_STATUS = 12U, /**< FCIIC_MSR_FEF_STATUS FIFO Error Flag */ + FCIIC_MSR_ALF_STATUS = 11U, /**< FCIIC_MSR_ALF_STATUS Arbitration Lost Flag */ + FCIIC_MSR_NDF_STATUS = 10U, /**< FCIIC_MSR_NDF_STATUS NACK Detect Flag */ + FCIIC_MSR_SDF_STATUS = 9U, /**< FCIIC_MSR_SDF_STATUS STOP Detect Flag */ + FCIIC_MSR_EPF_STATUS = 8U, /**< FCIIC_MSR_EPF_STATUS End Packet Flag */ + FCIIC_MSR_RXFPEF_STATUS = 3U, /**< FCIIC_MSR_EPF_STATUS RX FIFO Parity Error Flag */ + FCIIC_MSR_TXFPEF_STATUS = 2U, /**< FCIIC_MSR_EPF_STATUS TX FIFO Parity Error Flag */ + FCIIC_MSR_RDF_STATUS = 1U, /**< FCIIC_MSR_RDF_STATUS Receive Data Flag */ + FCIIC_MSR_TDF_STATUS = 0U /**< FCIIC_MSR_TDF_STATUS Transmit Data Flag */ +} FCIIC_MasterStatusType; + + + +/** + * \brief IIC Slave status type enumeration + * + */ +typedef enum +{ + FCIIC_SSR_BBF_STATUS = 25U, /**< FCIIC_SSR_BBF_STATUS Bus Busy Flag */ + FCIIC_SSR_SBF_STATUS = 24U, /**< FCIIC_SSR_SBF_STATUS Slave Busy Flag */ + FCIIC_SSR_SARF_STATUS = 15U, /**< FCIIC_SSR_SARF_STATUS SMBus Alert Response Flag */ + FCIIC_SSR_GCF_STATUS = 14U, /**< FCIIC_SSR_GCF_STATUS General Call Flag */ + FCIIC_SSR_AM1F_STATUS = 13U, /**< FCIIC_SSR_AM1F_STATUS Address Match 1 Flag */ + FCIIC_SSR_AM0F_STATUS = 12U, /**< FCIIC_SSR_AM0F_STATUS Address Match 0 Flag */ + FCIIC_SSR_TREF_STATUS = 11U, /**< FCIIC_SSR_TREF_STATUS FIFO Error Flag */ + FCIIC_SSR_BEF_STATUS = 10U, /**< FCIIC_SSR_BEF_STATUS Bit Error Flag */ + FCIIC_SSR_SDF_STATUS = 9U, /**< FCIIC_SSR_SDF_STATUS STOP Detect Flag */ + FCIIC_SSR_RSF_STATUS = 8U, /**< FCIIC_SSR_RSF_STATUS Repeated Start Flag */ + FCIIC_SSR_TAF_STATUS = 3U, /**< FCIIC_SSR_TAF_STATUS Transmit ACK Flag */ + FCIIC_SSR_AVF_STATUS = 2U, /**< FCIIC_SSR_AVF_STATUS Address Valid Flag */ + FCIIC_SSR_RDF_STATUS = 1U, /**< FCIIC_SSR_RDF_STATUS Receive Data Flag */ + FCIIC_SSR_TDF_STATUS = 0U, /**< FCIIC_SSR_TDF_STATUS Transmit Data Flag */ +} FCIIC_SlaveStatusType; + + +/** + * \brief Master Transmit Data + * + * \param pFciic IIC instance value + * \param tCmdType is command type + * \param u8Data to transmit + */ +LOCAL_INLINE void FCIIC_Master_HWA_Transmit(FCIIC_Type *pFciic, FCIIC_TX_CMDType tCmdType, uint8_t u8Data) +{ + pFciic->MTDR = FCIIC_MTDR_CMD(tCmdType) | FCIIC_MTDR_DATA(u8Data); +} + +/** + * \brief Master Receive Data + * + * \param pFciic IIC instance value + * \return the data received + */ +LOCAL_INLINE uint8_t FCIIC_Master_HWA_Receive(FCIIC_Type *pFciic) +{ + /* copy data */ + return (uint8_t)((uint8_t)(pFciic->MRDR) & 0xFFU); +} + +/** + * \brief Get and clear IIC master status + * + * \param pFciic is IIC instance value + * \param eStatus is status type + */ +LOCAL_INLINE void FCIIC_Master_HwA_CheckClearStatus(FCIIC_Type *pFciic, FCIIC_MasterStatusType eStatus) +{ + uint32_t u32RetVal; + + u32RetVal = (pFciic->MSR >> eStatus) & 0x01U; + + + if (u32RetVal != 0U) + { + pFciic->MSR |= (1UL << eStatus); /* w1c */ + } +} + +/** + * \brief This Function is used to get master status + * + * \param pFciic is IIC instance value + * \param eStatus is status type enumeration + * \return Status value 0 or 1 and 1 is OK + */ +LOCAL_INLINE uint8_t FCIIC_Master_HWA_GetStatus(FCIIC_Type *pFciic, FCIIC_MasterStatusType eStatus) +{ + uint32_t u32RetVal; + + u32RetVal = (pFciic->MSR >> (uint32_t)eStatus) & 0x01U; + + return (uint8_t)(u32RetVal == 1U ? 1U : 0U); +} + +/** + * \brief This Function is used to clear master status + * + * \param pFciic is IIC instance value + * \param u32Value is the clear bits + */ +LOCAL_INLINE void FCIIC_Master_HWA_ClrStatus(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->MSR |= u32Value; +} + +/** + * \brief This Function is used to get slave status + * + * \param pFciic is IIC instance value + * \param eStatus is status type enumeration + * \return Status value 0 or 1 and 1 is OK + */ +LOCAL_INLINE uint8_t FCIIC_Slave_HWA_GetStatus(FCIIC_Type *pFciic, FCIIC_SlaveStatusType eStatus) +{ + uint32_t u32RetVal; + + u32RetVal = (pFciic->SSR >> (uint32_t)eStatus) & 0x01U; + + return (uint8_t)(u32RetVal == 1U ? 1U : 0U); +} + +/** + * \brief This Function is used to clear slave status + * + * \param pFciic is IIC instance value + * \param u32Value is the clear bits value + */ +LOCAL_INLINE void FCIIC_Slave_HWA_ClrStatus(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->SSR |= u32Value; +} + +/** + * \brief Slave Transmit Data + * + * \param pFciic IIC instance value + * \param u8Data to transmit + */ +LOCAL_INLINE void FCIIC_Slave_HWA_Transmit(FCIIC_Type *pFciic, uint8_t u8Data) +{ + pFciic->STDR = FCIIC_STDR_DATA(u8Data); +} + + +/** + * \brief Slave Get Data + * + * \param pFciic IIC instance value + * \return the data value + */ +LOCAL_INLINE uint8_t FCIIC_Slave_HWA_Receive(FCIIC_Type *pFciic) +{ + /* copy data */ + return (uint8_t)((uint8_t)(pFciic->SRDR) & 0xFFU); +} + +/** + * \brief Enable Receive Interrupt + * + * \param pFciic IIC instance value + */ +LOCAL_INLINE void FCIIC_Master_HWA_EnableReceiveInterrupt(FCIIC_Type *pFciic) +{ + pFciic->MIER |= FCIIC_MIER_RDIE_MASK; +} + +/** + * \brief Disable Receive Interrupt + * + * \param pFciic IIC instance value + */ +LOCAL_INLINE void FCIIC_Master_HWA_DisableReceiveInterrupt(FCIIC_Type *pFciic) +{ + pFciic->MIER &= ~FCIIC_MIER_RDIE_MASK; +} + +/** + * \brief Enable Error Interrupt + * + * \param pFciic IIC instance value + */ +LOCAL_INLINE void FCIIC_Master_HWA_EnableErrorInterrupt(FCIIC_Type *pFciic) +{ + pFciic->MIER |= FCIIC_MIER_FEIE_MASK; +} + +/** + * \brief Disable Error Interrupt + * + * \param pFciic IIC instance value + */ +LOCAL_INLINE void FCIIC_Master_HWA_DisableErrorInterrupt(FCIIC_Type *pFciic) +{ + pFciic->MIER &= FCIIC_MIER_FEIE_MASK; +} + +/** + * \brief Get Error Flag + * + * \param pFciic IIC instance value + */ +LOCAL_INLINE uint32_t FCIIC_Master_HWA_GetErrorFlag(FCIIC_Type *pFciic) +{ + return pFciic->MSR & FCIIC_MSR_FEF_MASK; +} + +/** + * \brief Clr Error Flag + * + * \param pFciic IIC instance value + */ +LOCAL_INLINE void FCIIC_Master_HWA_ClrErrorFlag(FCIIC_Type *pFciic) +{ + pFciic->MSR |= FCIIC_MSR_FEF_MASK; +} + +/** + * \brief Enable Transmit Interrupt + * + * \param pFciic IIC instance value + */ +LOCAL_INLINE void FCIIC_Master_HWA_EnableTransmitInterrupt(FCIIC_Type *pFciic) +{ + pFciic->MIER |= FCIIC_MIER_TDIE_MASK; +} + +/** + * \brief Disable Transmit Interrupt + * + * \param pFciic IIC instance value + */ +LOCAL_INLINE void FCIIC_Master_HWA_DisableTransmitInterrupt(FCIIC_Type *pFciic) +{ + pFciic->MIER &= ~FCIIC_MIER_TDIE_MASK; +} + + +/** + * \brief Enable Receive Interrupt + * + * \param pFciic IIC instance value + */ +LOCAL_INLINE void FCIIC_Slave_HWA_EnableReceiveInterrupt(FCIIC_Type *pFciic) +{ + pFciic->SIER |= FCIIC_SIER_RDIE_MASK; +} + +/** + * \brief Disable Receive Interrupt + * + * \param pFciic IIC instance value + */ +LOCAL_INLINE void FCIIC_Slave_HWA_DisableReceiveInterrupt(FCIIC_Type *pFciic) +{ + pFciic->SIER &= ~FCIIC_SIER_RDIE_MASK; +} + +/** + * \brief Enable Error Interrupt + * + * \param pFciic IIC instance value + */ +LOCAL_INLINE void FCIIC_Slave_HWA_EnableErrorInterrupt(FCIIC_Type *pFciic) +{ + pFciic->SIER |= FCIIC_SIER_TREIE_MASK | FCIIC_SIER_BEIE_MASK ; +} + +/** + * \brief Disable Error Interrupt + * + * \param pFciic IIC instance value + */ +LOCAL_INLINE void FCIIC_Slave_HWA_DisableErrorInterrupt(FCIIC_Type *pFciic) +{ + pFciic->SIER &= ~(FCIIC_SIER_TREIE_MASK | FCIIC_SIER_BEIE_MASK); +} + +/** + * \brief Get Error Flag + * + * \param pFciic IIC instance value + */ +LOCAL_INLINE uint32_t FCIIC_Slave_HWA_GetErrorFlag(FCIIC_Type *pFciic) +{ + return pFciic->SSR & (FCIIC_SSR_TREF_MASK | FCIIC_SSR_BEF_MASK); +} + +/** + * \brief Clear Error Flag + * + * \param pFciic IIC instance value + */ +LOCAL_INLINE void FCIIC_Slave_HWA_ClrErrorFlag(FCIIC_Type *pFciic) +{ + pFciic->SSR |= (FCIIC_SSR_TREF_MASK | FCIIC_SSR_BEF_MASK); +} + +/** + * \brief Enable Transmit Interrupt + * + * \param pFciic IIC instance value + */ +LOCAL_INLINE void FCIIC_Slave_HWA_EnableTransmitInterrupt(FCIIC_Type *pFciic) +{ + pFciic->SIER |= FCIIC_SIER_TDIE_MASK; +} + +/** + * \brief FCIIC Disable Transmit Interrupt + * + * \param pFciic IIC instance value + */ +LOCAL_INLINE void FCIIC_Slave_HWA_DisableTransmitInterrupt(FCIIC_Type *pFciic) +{ + pFciic->SIER &= ~FCIIC_SIER_TDIE_MASK; /* Receive Interrupt Enable */ +} + + +/** + * \brief Set FCIIC MCR register + * + * \param pFciic FCIIC instance value + * \param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_SetMcr(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->MCR = u32Value; +} + +/** + * \brief Attach FCIIC MCR register + * + * \param pFciic FCIIC instance value + * \param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_AttachMcr(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->MCR |= u32Value; +} + + +/** + * \brief Set FCIIC MDER register + * + * \param pFciic FCIIC instance value + * \param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_SetMder(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->MDER = u32Value; +} + +/** + * \brief Set FCIIC MCFGR0 register + * + * \param pFciic FCIIC instance value + * \param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_SetMCFGR0(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->MCFGR0 = u32Value; +} + +/** + * \brief Set FCIIC MCFGR1 register + * + * \param pFciic FCIIC instance value + * \param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_SetMCFGR1(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->MCFGR1 = u32Value; +} + +/** + * \brief Set FCIIC MCFGR2 register + * + * \param pFciic FCIIC instance value + * \param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_SetMCFGR2(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->MCFGR2 = u32Value; +} + +/** + * \brief Set FCIIC MCFGR3 register + * + * \param pFciic FCIIC instance value + * \param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_SetMCFGR3(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->MCFGR3 = u32Value; +} + +/** + * \brief Set FCIIC MFCR register + * + * \param pFciic FCIIC instance value + * \param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_SetMFCR(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->MFCR = u32Value; +} + +/** + * \brief Set FCIIC MCCR register + * + * \param pFciic FCIIC instance value + * \param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_SetMCCR(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->MCCR = u32Value; +} + +/** + * \brief Set FCIIC SDER register + * + * \param pFciic FCIIC instance value + * \param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_SetSDER(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->SDER = u32Value; +} + + + +/** + * \brief Set FCIIC SCFGR1 register + * + * \param pFciic FCIIC instance value + * \param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_SetSCFGR1(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->SCFGR1 = u32Value; +} + +/** + * \brief Set FCIIC MCCR register + * + * \param pFciic FCIIC instance value + * \param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_SetSCFGR2(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->SCFGR2 = u32Value; +} + +/** + * \brief Set FCIIC MCCR register + * + * \param pFciic FCIIC instance value + * \param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_SetSAMR(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->SAMR = u32Value; +} + +/** + * \brief Set FCIIC MCCR register + * + * \param pFciic FCIIC instance value + * \param u32Value written value + */ +LOCAL_INLINE void FCIIC_HWA_SetSCR(FCIIC_Type *pFciic, uint32_t u32Value) +{ + pFciic->SCR = u32Value; +} + + + +/** @}*/ + +#endif /* end for #ifndef _HWA_FCIIC_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_fcpit.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_fcpit.h new file mode 100644 index 0000000..6991ab2 --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_fcpit.h @@ -0,0 +1,412 @@ +/** + * @file HwA_fcpit.h + * @author Flagchip + * @brief FC7xxx FCPIT hardware access layer + * @version 0.1.0 + * @date 2024-01-10 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-10 Flagchip076 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef _HWA_FCPIT_H_ +#define _HWA_FCPIT_H_ + +#include "device_header.h" +/********* Local typedef ************/ +/** @brief Fcpit counter mode, the default mode is 32bit periodic count mode */ +typedef enum +{ + FCPIT_32PERIODIC_COUNTER = 0, + FCPIT_DUAL_16PERIODIC_COUNTER, + FCPIT_ACCUMULATOR, + FCPIT_32InputCaptue, +} FCPIT_TimerModeType; + +/** @brief Fcpit channel number */ +typedef enum +{ + FCPIT_CHANNEL_0 = 0U, + FCPIT_CHANNEL_1, + FCPIT_CHANNEL_2, + FCPIT_CHANNEL_3 +} FCPIT_ChannelType; +/********* Local inline function ************/ +/** + * @brief Set FCPIT channel value + * + * @param eChannel FCPIT channel number + * @param u32RegValue Timer value + */ +LOCAL_INLINE void FCPIT_HWA_SetChannelValue(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel, uint32_t u32RegValue) +{ + pFcpit->CONTROLS[eChannel].TVAL = u32RegValue; +} + + +/** + * @brief read FCPIT channel value + * + * @param eChannel FCPIT channel number + * @return Timer value + */ +LOCAL_INLINE uint32_t FCPIT_HWA_ReadChannelValue(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + return (uint32_t)(pFcpit->CONTROLS[eChannel].TVAL ); +} + +/** + * @brief Configure FCPIT channel + * + * @param eChannel FCPIT channel number + * @param u32RegValue TCTRL register value + */ +LOCAL_INLINE void FCPIT_HWA_ConfigChannel(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel, uint32_t u32RegValue) +{ + pFcpit->CONTROLS[eChannel].TCTRL = u32RegValue; +} + +/** + * @brief Configure FCPIT module + * + * @param u32RegValue MCR register value + */ +LOCAL_INLINE void FCPIT_HWA_ConfigModule(FCPIT_Type *pFcpit, uint32_t u32RegValue) +{ + pFcpit->MCR = u32RegValue; +} + + +/** + * @brief Read FCPIT module enable + * + * @return MCR register with FCPIT_MCR_M_CEN_MASK + */ +LOCAL_INLINE uint32_t FCPIT_HWA_ReadModuleEnable(FCPIT_Type *pFcpit) +{ + return (uint32_t)(pFcpit->MCR & FCPIT_MCR_M_CEN_MASK); +} + +/** + * @brief Read FCPIT channel + * + * @param eChannel Channel number + * @return TCTRL register with FCPIT_TCTRL_T_EN_MASK + */ +LOCAL_INLINE uint32_t FCPIT_HWA_ReadChannelEnable(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + return (uint32_t)(pFcpit->CONTROLS[eChannel].TCTRL & FCPIT_TCTRL_T_EN_MASK); +} + +/** + * @brief Read FCPIT active interrupt flag + * + * @return FCPIT active interrupt flag + */ +LOCAL_INLINE uint32_t FCPIT_HWA_ReadInterruptFlag(FCPIT_Type *pFcpit) +{ + return (pFcpit->MSR); +} + +/** + * @brief Read FCPIT enable interrupt flag + * + * @return FCPIT enable interrupt flag + */ +LOCAL_INLINE uint32_t FCPIT_HWA_ReadEnableInterruptFlag(FCPIT_Type *pFcpit) +{ + return (pFcpit->MIER); +} + +/** + * @brief Set FCPIT channel running on debug mode + * + */ +LOCAL_INLINE void FCPIT_HWA_SetChannelRunOnDebug(FCPIT_Type *pFcpit) +{ + pFcpit->MCR |= FCPIT_MCR_DBG_EN_MASK; +} + +/** + * @brief Set FCPIT channel running on low power mode + * + */ +LOCAL_INLINE void FCPIT_HWA_SetChannelRunOnLpm(FCPIT_Type *pFcpit) +{ + pFcpit->MCR |= FCPIT_MCR_LPM_EN_MASK; +} + +/** + * @brief Enable FCPIT module + * + */ +LOCAL_INLINE void FCPIT_HWA_EnableModule(FCPIT_Type *pFcpit) +{ + pFcpit->MCR |= FCPIT_MCR_M_CEN_MASK; +} + +/** + * @brief Enable FCPIT channel(n) interrupt + * + * @param u32RegValue u32RegValue 0-3 bit indicate TIE0-TIE3 + */ +LOCAL_INLINE void FCPIT_HWA_EnableChannelsInterrupt(FCPIT_Type *pFcpit, uint32_t u32RegValue) +{ + pFcpit->MIER |= u32RegValue; +} + +/** + * @brief Enable FCPIT channel + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_EnableChannel(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL |= FCPIT_TCTRL_T_EN_MASK; +} + +/** + * @brief Enable FCPIT channel + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_SetTimerEnable(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->SETTEN |= (FCPIT_SETTEN_SET_T_EN_0_MASK << (uint32_t)eChannel); +} + + +/** + * @brief Disable FCPIT channel + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_ClearTimerEnable(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CLRTEN |= (FCPIT_CLRTEN_CLR_T_EN_0_MASK << (uint32_t)eChannel); +} + +/** + * @brief Enable FCPIT channel(n) chain mode + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_EnableChannelChainMode(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL |= FCPIT_TCTRL_CHAIN_MASK; +} + +/** + * @brief Configure FCPIT channel operation mode + * + * @param eChannel FCPIT channel number + * @param eMode FCPIT operation mode + */ +LOCAL_INLINE void FCPIT_HWA_ConfigChannelMode(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel, FCPIT_TimerModeType eMode) +{ + uint32_t u32RegValue = pFcpit->CONTROLS[eChannel].TCTRL; + pFcpit->CONTROLS[eChannel].TCTRL = (u32RegValue & ~(uint32_t)FCPIT_TCTRL_MODE_MASK) | FCPIT_TCTRL_MODE(eMode); +} + +/** + * @brief Set FCPIT channel start on trigger + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_SetChannelStartOnTrig(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL |= FCPIT_TCTRL_TSOT_MASK; +} + +/** + * @brief Set FCPIT channel stop on interrupt + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_SetChannelStopOnInterrupt(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL |= FCPIT_TCTRL_TSOI_MASK; +} + +/** + * @brief Set FCPIT channel reload on trigger + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_SetChannelReloadOnTrig(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL |= FCPIT_TCTRL_TROT_MASK; +} + +/** + * @brief Set FCPIT channel trigger source + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_SetChannelTriggerSrc(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL |= FCPIT_TCTRL_TRG_SRC_MASK; +} + +/** + * @brief Select FCPIT channel trigger + * + * @param eChannel FCPIT channel number + * @param u8SelChannel Select channel, range is 0-3 + */ +LOCAL_INLINE void FCPIT_HWA_SelectChannelTrigger(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel, uint8_t u8SelChannel) +{ + uint32_t u32RegValue = pFcpit->CONTROLS[eChannel].TCTRL; + pFcpit->CONTROLS[eChannel].TCTRL = (u32RegValue & ~(uint32_t)FCPIT_TCTRL_TRG_SEL_MASK) | + FCPIT_TCTRL_TRG_SEL(u8SelChannel); +} + +/** + * @brief Set FCPIT channel stop on debug mode + * + */ +LOCAL_INLINE void FCPIT_HWA_SetChannelStopOnDebug(FCPIT_Type *pFcpit) +{ + pFcpit->MCR &= ~(uint32_t)FCPIT_MCR_DBG_EN_MASK; +} + +/** + * @brief Set FCPIT channel stop on low power mode + * + */ +LOCAL_INLINE void FCPIT_HWA_SetChannelStopOnLpm(FCPIT_Type *pFcpit) +{ + pFcpit->MCR &= ~(uint32_t)FCPIT_MCR_LPM_EN_MASK; +} + +/** + * @brief Disable FCPIT module + * + */ +LOCAL_INLINE void FCPIT_HWA_DisableModule(FCPIT_Type *pFcpit) +{ + pFcpit->MCR &= ~(uint32_t)FCPIT_MCR_M_CEN_MASK; +} + +/** + * @brief Clear FCPIT channel(n) interrupt flag + * + * @param u32RegValue 0-3 bit indicate TIF0-TIF3 + */ +LOCAL_INLINE void FCPIT_HWA_ClearChannelsInterruptFlag(FCPIT_Type *pFcpit, uint32_t u32RegValue) +{ + pFcpit->MSR |= u32RegValue; +} + +/** + * @brief Disable FCPIT channel(n) interrupt + * + * @param u32RegValue u32RegValue 0-3 bit indicate TIE0-TIE3 + */ +LOCAL_INLINE void FCPIT_HWA_DisableChannelsInterrupt(FCPIT_Type *pFcpit, uint32_t u32RegValue) +{ + pFcpit->MIER &= ~u32RegValue; +} + +/** + * @brief Disable FCPIT channel + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_DisableChannel(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_T_EN_MASK; +} + +/** + * @brief Disable FCPIT channel chain mode + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_DisableChannelChainMode(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_CHAIN_MASK; +} + +/** + * @brief Clear FCPIT channel operation mode + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_ClearChannelMode(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_MODE_MASK; +} + +/** + * @brief read FCPIT channel operation mode + * + * @param eChannel FCPIT channel number + */ + +LOCAL_INLINE uint32 FCPIT_HWA_ReadChannelMode(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + return (uint32) ((pFcpit->CONTROLS[eChannel].TCTRL & (uint32_t)FCPIT_TCTRL_MODE_MASK) >>FCPIT_TCTRL_MODE_SHIFT); +} + + +/** + * @brief Clear FCPIT channel start on trigger + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_ClearChannelStartOnTrig(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_TSOT_MASK; +} + +/** + * @brief Clear FCPIT channel stop on interrupt + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_ClearChannelStopOnInterrupt(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_TSOI_MASK; +} + +/** + * @brief Clear FCPIT channel reload on trigger + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_ClearChannelReloadOnTrig(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_TROT_MASK; +} + +/** + * @brief Clear FCPIT channel trigger source + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_ClearChannelTriggerSrc(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_TRG_SRC_MASK; +} + +/** + * @brief Clear FCPIT channel trigger select + * + * @param eChannel FCPIT channel number + */ +LOCAL_INLINE void FCPIT_HWA_ClearChannelTriggerSelect(FCPIT_Type *pFcpit, FCPIT_ChannelType eChannel) +{ + pFcpit->CONTROLS[eChannel].TCTRL &= ~(uint32_t)FCPIT_TCTRL_TRG_SEL_MASK; +} + + +#endif /* #ifndef _HWA_FCPIT_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_fcsmu.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_fcsmu.h new file mode 100644 index 0000000..68d99a3 --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_fcsmu.h @@ -0,0 +1,671 @@ +/** + * @file HwA_fcsmu.h + * @author Flagchip + * @brief FC7xxx FCSMU hardware access layer + * @version 0.1.0 + * @date 2024-01-14 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-14 qxw0100 N/A First version for FC7240 + ******************************************************************************** */ +#ifndef _HWA_FCSMU_H_ +#define _HWA_FCSMU_H_ + +#include "device_header.h" + +/** + * @addtogroup HwA_fcsmu + * @{ + * + */ +/********* macros ************/ +typedef enum +{ + FCSMU_OPC_NONE = 0U, /*!< FCSMU operation code none */ + FCSMU_OPC_MOVE_TO_CONFIG = 1U, /*!< FCSMU operation code move to configuration state */ + FCSMU_OPC_MOVE_TO_NORMAL = 2U, /*!< FCSMU operation code move to normal state */ + FCSMU_OPC_CLEAR_FAULT_IMFO = 13U, /*!< FCSMU operation code clear fault channel information register */ + FCSMU_OPC_CLEAR_OPS_TO_IDLE = 15U, /*!< FCSMU operation code clear ops to idle */ + FCSMU_OPC_LOAD_NVR_CONFIG = 31U /*!< FCSMU operation code load configuration from nvr */ +} FCSMU_OperationCodeType; + +typedef enum +{ + FCSMU_Crc_STATE_IDLE = 0U, /*!< FCSMU crc status idle */ + FCSMU_Crc_STATE_BUSY = 1U /*!< FCSMU crc status busy */ +} FCSMU_CrcStatusType; +/********* Local typedef ************/ + +/********* Local inline function ************/ + +/********* FCSMU Register interface ************/ + +/** + * @brief Set the fcsmu CTRL register + * + * @param pFcsmu FCSMU Instance + * @param u32Value The register value + */ +LOCAL_INLINE void FCSMU_HWA_SetCrtl(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->CTRL = u32Value; +} + +/** + * @brief Get the fcsmu CTRL register + * + * @param pFcsmu FCSMU Instance + * @return CTRL register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetCtrl(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->CTRL; +} + +/** + * @brief Get the fcsmu CTRL register OPS + * + * @param pFcsmu FCSMU Instance + * @return CTRL register OPS value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetCtrlOps(FCSMU_Type *const pFcsmu) +{ + return ((pFcsmu->CTRL & FCSMU_CTRL_OPS_MASK) >> FCSMU_CTRL_OPS_SHIFT); +} + +/** + * @brief Set the fcsmu OPRK register + * + * @param pFcsmu FCSMU Instance + * @param u32Value The register value + */ +LOCAL_INLINE void FCSMU_HWA_SetOprk(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->OPRK = u32Value; +} + + +/** + * @brief Set the fcsmu SOCTRL register + * + * @param pFcsmu FCSMU Instance + * @param u32Value The register value + */ +LOCAL_INLINE void FCSMU_HWA_SetSoctrl(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->SOCTRL = u32Value; +} + +/** + * @brief Get the fcsmu SOCTRL register + * + * @param pFcsmu FCSMU Instance + * @return SOCTRL register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetSoctrl(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->SOCTRL; +} + +/** + * @brief Set the fcsmu FCCR0 register + * + * @param pFcsmu FCSMU Instance + * @param u32Value FCCR0 register value + */ +LOCAL_INLINE void FCSMU_HWA_SetFccr0(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->FCCR0 = u32Value; +} + +/** + * @brief Get the fcsmu FCCR0 register + * + * @param pFcsmu FCSMU Instance + * @return FCCR0 register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetFccr0(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->FCCR0; +} + +/** + * @brief Set the fcsmu FRST0 register + * + * @param pFcsmu FCSMU Instance + * @param u32Value FRST0 register value + */ +LOCAL_INLINE void FCSMU_HWA_SetFRST0(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->FRST0 = u32Value; +} + +/** + * @brief Get the fcsmu FRST0 register + * + * @param pFcsmu FCSMU Instance + * @return FRST0 register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetFRST0(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->FRST0; +} + +/** + * @brief Set the fcsmu FST0 register + * + * @param pFcsmu FCSMU Instance + * @param u32Value FST0 register value + */ +LOCAL_INLINE void FCSMU_HWA_SetFst0(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->FST0 = u32Value; +} + +/** + * @brief Get the fcsmu FST0 register + * + * @param pFcsmu FCSMU Instance + * @return FST0 register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetFst0(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->FST0; +} + +/** + * @brief Set the fcsmu FST_UNLK register + * + * @param pFcsmu FCSMU Instance + * @param u32Value FST_UNLK register value + */ +LOCAL_INLINE void FCSMU_HWA_SetFunlk(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->FST_UNLK = u32Value; +} + +/** + * @brief Set the fcsmu FE0 register + * + * @param pFcsmu FCSMU Instance + * @param u32Value FE0 register value + */ +LOCAL_INLINE void FCSMU_HWA_SetFe0(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->FE0 = u32Value; +} + +/** + * @brief Get the fcsmu FE0 register + * + * @param pFcsmu FCSMU Instance + * @return FE0 register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetFE0(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->FE0; +} + +/** + * @brief Set the fcsmu WARNING_EN0 register + * + * @param pFcsmu FCSMU Instance + * @param u32Value WARNING_EN0 register value + */ +LOCAL_INLINE void FCSMU_HWA_SetWarningEn0(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->WARNING_EN0 = u32Value; +} + +/** + * @brief Get the fcsmu WARNING_EN0 register + * + * @param pFcsmu FCSMU Instance + * @return WARNING_EN0 register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetWarningEn0(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->WARNING_EN0; +} + +/** + * @brief Set the fcsmu WARNING_TO register + * + * @param pFcsmu FCSMU Instance + * @param u32Value WARNING_TO register value + */ +LOCAL_INLINE void FCSMU_HWA_SetWaringTo(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->WARNING_TO = u32Value; +} + +/** + * @brief Get the fcsmu WARNING_TO register + * + * @param pFcsmu FCSMU Instance + * @return WARNING_TO register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetWaringTo(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->WARNING_TO; +} + +/** + * @brief Set the fcsmu CFG_TO register + * + * @param pFcsmu FCSMU Instance + * @param u32Value CFG_TO register value + */ +LOCAL_INLINE void FCSMU_HWA_SetCfgTo(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->CFG_TO = u32Value; +} + +/** + * @brief Get the fcsmu CFG_TO register + * + * @param pFcsmu FCSMU Instance + * @return CFG_TO register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetCfgTo(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->CFG_TO; +} + +/** + * @brief Set the fcsmu SOUT_DIAG register + * + * @param pFcsmu FCSMU Instance + * @param u32Value SOUT_DIAG register value + */ +LOCAL_INLINE void FCSMU_HWA_SetSoutDiag(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->SOUT_DIAG = u32Value; +} + +/** + * @brief Get the fcsmu SOUT_DIAG register + * + * @param pFcsmu FCSMU Instance + * @return SOUT_DIAG register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetSoutDiag(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->SOUT_DIAG; +} + +/** + * @brief Get the fcsmu STATUS register + * + * @param pFcsmu FCSMU Instance + * @return STATUS register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetStatus(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->STATUS; +} + +/** + * @brief Get the fcsmu STATUS register FIF value + * + * @param pFcsmu FCSMU Instance + * @return STATUS register FIF value + */ +LOCAL_INLINE bool FCSMU_HWA_GetFaultState(FCSMU_Type *const pFcsmu) +{ + return (pFcsmu->STATUS & FCSMU_STATUS_FIF_MASK) == FCSMU_STATUS_FIF_MASK ? true : false; +} + +/** + * @brief Get the fcsmu STATUS register STAT value + * + * @param pFcsmu FCSMU Instance + * @return STATUS register STAT value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetState(FCSMU_Type *const pFcsmu) +{ + return (pFcsmu->STATUS & FCSMU_STATUS_STAT_MASK) >> FCSMU_STATUS_STAT_SHIFT; +} + +/** + * @brief Get the fcsmu NTW register + * + * @param pFcsmu FCSMU Instance + * @return NTW register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetNtw(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->NTW; +} + +/** + * @brief Get the fcsmu WTF register + * + * @param pFcsmu FCSMU Instance + * @return WTF register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetWtf(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->WTF; +} + +/** + * @brief Get the fcsmu NTF register + * + * @param pFcsmu FCSMU Instance + * @return NTF register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetNtf(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->NTF; +} + +/** + * @brief Get the fcsmu FTW register + * + * @param pFcsmu FCSMU Instance + * @return FTW register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetFtw(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->FTW; +} + +/** + * @brief Set the fcsmu INJECT register + * + * @param pFcsmu FCSMU Instance + * @param u32Value INJECT register value + */ +LOCAL_INLINE void FCSMU_HWA_SetInject(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->INJECT = u32Value; +} + +/** + * @brief Get the fcsmu IRQ_STAT register + * + * @param pFcsmu FCSMU Instance + * @return IRQ_STAT register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetIrqStat(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->IRQ_STAT; +} + +/** + * @brief Set the fcsmu IRQ_STAT register + * + * @param pFcsmu FCSMU Instance + * @param u32Value IRQ_STAT register value + */ +LOCAL_INLINE void FCSMU_HWA_ClearCfgToIrq(FCSMU_Type *const pFcsmu) +{ + pFcsmu->IRQ_STAT |= FCSMU_IRQ_STAT_CFG_TO_IRQ_MASK; +} + + +/** + * @brief Set the fcsmu IRQ_EN register + * + * @param pFcsmu FCSMU Instance + * @param bEnable IRQ_EN register value + */ +LOCAL_INLINE void FCSMU_HWA_EnableCfgToIrq(FCSMU_Type *const pFcsmu, bool bEnable) +{ + pFcsmu->IRQ_EN = (pFcsmu->IRQ_EN & ~FCSMU_IRQ_STAT_CFG_TO_IRQ_MASK) | FCSMU_IRQ_EN_CFG_TO_IEN(bEnable); +} + +/** + * @brief Set the fcsmu TEMP_UNLK register + * + * @param pFcsmu FCSMU Instance + * @param u32Value TEMP_UNLK register value + */ +LOCAL_INLINE void FCSMU_HWA_SetTempUnlk(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->TEMP_UNLK = u32Value; +} + +/** + * @brief Set the fcsmu PERMNT_LOCK register + * + * @param pFcsmu FCSMU Instance + * @param u32Value PERMNT_LOCK register value + */ +LOCAL_INLINE void FCSMU_HWA_SetPermntLock(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->PERMNT_LOCK = u32Value; +} + +/** + * @brief Set the fcsmu STMR register + * + * @param pFcsmu FCSMU Instance + * @param u32Value STMR register value + */ +LOCAL_INLINE void FCSMU_HWA_SetStmr(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->STMR = u32Value; +} + + +/** + * @brief Set the fcsmu WARNING_IEN0 register + * + * @param pFcsmu FCSMU Instance + * @param u32Value WARNING_IEN0 register value + */ +LOCAL_INLINE void FCSMU_HWA_SetWarningIen(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->WARNING_IEN0 = u32Value; +} + +/** + * @brief Set the fcsmu FAULT_IEN0 register + * + * @param pFcsmu FCSMU Instance + * @param u32Value FAULT_IEN0 register value + */ +LOCAL_INLINE void FCSMU_HWA_SetFaultIen(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->FAULT_IEN0 = u32Value; +} + +/** + * @brief Set the fcsmu SOUT_EN0 register + * + * @param pFcsmu FCSMU Instance + * @param u32Value SOUT_EN0 register value + */ +LOCAL_INLINE void FCSMU_HWA_SetSoutEn(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->SOUT_EN0 = u32Value; +} + +/** + * @brief Get the fcsmu WARNING_TMR register + * + * @param pFcsmu FCSMU Instance + * @return WARNING_TMR register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetWarningTmr(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->WARNING_TMR; +} + +/** + * @brief Get the fcsmu SM_TMR register + * + * @param pFcsmu FCSMU Instance + * @return SM_TMR register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetSafeModeTmr(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->SM_TMR; +} + +/** + * @brief Get the fcsmu CFG_TMR register + * + * @param pFcsmu FCSMU Instance + * @return CFG_TMR register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetConfigTmr(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->CFG_TMR; +} + +/** + * @brief Get the fcsmu SOUT_TMR register + * + * @param pFcsmu FCSMU Instance + * @return SOUT_TMR register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetSoutTmr(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->SOUT_TMR; +} + +/** + * @brief Set the fcsmu CRC_CTRL register + * + * @param pFcsmu FCSMU Instance + * @param u32Value CRC_CTRL register value + */ +LOCAL_INLINE void FCSMU_HWA_SetCrcCtrl(FCSMU_Type *const pFcsmu, uint32_t u32Value) +{ + pFcsmu->CRC_CTRL = u32Value; +} + +/** + * @brief Get the fcsmu CRC_CTRL register BUSY value + * + * @param pFcsmu FCSMU Instance + * @return BUSY value + */ +LOCAL_INLINE bool FCSMU_HWA_GetCrcBusy(FCSMU_Type *const pFcsmu) +{ + return (pFcsmu->CRC_CTRL & FCSMU_CRC_CTRL_BUSY_MASK) == FCSMU_CRC_CTRL_BUSY_MASK ? true : false; +} + +/** + * @brief Get the fcsmu CRC_CTRL register EF value + * + * @param pFcsmu FCSMU Instance + * @return EF value + */ +LOCAL_INLINE bool FCSMU_HWA_GetCrcErrorFlag(FCSMU_Type *const pFcsmu) +{ + return (pFcsmu->CRC_CTRL & FCSMU_CRC_CTRL_EF_MASK) == FCSMU_CRC_CTRL_EF_MASK ? true : false; +} + +/** + * @brief Clear the fcsmu CRC_CTRL register EF + * + * @param pFcsmu FCSMU Instance + * @param u32Value CRC_CTRL register value + */ +LOCAL_INLINE void FCSMU_HWA_ClearCrcErrorFlag(FCSMU_Type *const pFcsmu) +{ + pFcsmu->CRC_CTRL |= FCSMU_CRC_CTRL_EF_MASK; +} + +/** + * @brief Set the fcsmu CRC_CTRL register + * + * @param pFcsmu FCSMU Instance + * @param u32Value CRC_CTRL register value + */ +LOCAL_INLINE void FCSMU_HWA_EnableErrorOutput(FCSMU_Type *const pFcsmu, bool bEnable) +{ + pFcsmu->CRC_CTRL = (pFcsmu->CRC_CTRL & ~FCSMU_CRC_CTRL_EOEN_MASK) | FCSMU_CRC_CTRL_EOEN(bEnable); +} + +/** + * @brief Get the fcsmu CRC_CTRL register EOEN value + * + * @param pFcsmu FCSMU Instance + * @return EOEN value + */ +LOCAL_INLINE bool FCSMU_HWA_GetCrcErrorOutputEnable(FCSMU_Type *const pFcsmu) +{ + return (pFcsmu->CRC_CTRL & FCSMU_CRC_CTRL_EOEN_MASK) == FCSMU_CRC_CTRL_EOEN_MASK ? true : false; +} + +/** + * @brief Set the fcsmu CRC_CTRL register + * + * @param pFcsmu FCSMU Instance + * @param bEnable CRC_CTRL register value + */ +LOCAL_INLINE void FCSMU_HWA_EnableCrcChecker(FCSMU_Type *const pFcsmu, bool bEnable) +{ + pFcsmu->CRC_CTRL = (pFcsmu->CRC_CTRL & ~FCSMU_CRC_CTRL_CHKEN_MASK) | FCSMU_CRC_CTRL_CHKEN(bEnable); +} + +/** + * @brief Get the fcsmu CRC_CTRL register CHKEN value + * + * @param pFcsmu FCSMU Instance + * @return CHKEN value + */ +LOCAL_INLINE bool FCSMU_HWA_GetCrcCheckerEnable(FCSMU_Type *const pFcsmu) +{ + return (pFcsmu->CRC_CTRL & FCSMU_CRC_CTRL_CHKEN_MASK) == FCSMU_CRC_CTRL_CHKEN_MASK ? true : false; +} + +/** + * @brief Set the fcsmu CRC_CTRL register + * + * @param pFcsmu FCSMU Instance + * @param bEnable CRC_CTRL register value + */ +LOCAL_INLINE void FCSMU_HWA_EnableTrigger(FCSMU_Type *const pFcsmu, bool bEnable) +{ + pFcsmu->CRC_CTRL = (pFcsmu->CRC_CTRL & ~FCSMU_CRC_CTRL_TRGEN_MASK) | FCSMU_CRC_CTRL_TRGEN(bEnable); +} + +/** + * @brief Get the fcsmu CRC_CTRL register TRGEN value + * + * @param pFcsmu FCSMU Instance + * @return TRGEN value + */ +LOCAL_INLINE bool FCSMU_HWA_GetTriggerEnable(FCSMU_Type *const pFcsmu) +{ + return (pFcsmu->CRC_CTRL & FCSMU_CRC_CTRL_TRGEN_MASK) == FCSMU_CRC_CTRL_TRGEN_MASK ? true : false; +} + +/** + * @brief Set the fcsmu CRC_CTRL register + * + * @param pFcsmu FCSMU Instance + */ +LOCAL_INLINE void FCSMU_HWA_GenerateCrc(FCSMU_Type *const pFcsmu) +{ + pFcsmu->CRC_CTRL |= FCSMU_CRC_CTRL_GEN(true); +} + +/** + * @brief Get the fcsmu CRC_RES register + * + * @param pFcsmu FCSMU Instance + * @return CRC_RES register value + */ +LOCAL_INLINE uint32_t FCSMU_HWA_GetCrcResult(FCSMU_Type *const pFcsmu) +{ + return pFcsmu->CRC_RES; +} + +/** @}*/ /* HwA_fcsmu */ + +#endif /* #ifndef _HWA_FCSMU_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_fcspi.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_fcspi.h new file mode 100644 index 0000000..3c204cc --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_fcspi.h @@ -0,0 +1,478 @@ +/** + * @file HwA_fcspi.h + * @author Flagchip + * @brief FC7xxx FCSPI hardware access layer + * @version 0.1.0 + * @date 2024-01-13 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-12 Flagchip071 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef _HWA_FCSPI_H_ +#define _HWA_FCSPI_H_ + +#include "device_header.h" + +/** + * @addtogroup HwA_fcspi + * @{ + */ + +/** + * @brief Boolean false value definition for type FCSPI_AtomicBoolType used by FCSPI to ensure read/write atomic + * + */ +#define FCSPI_FALSE ((uint8_t)0) + +/** + * @brief Boolean true value definition for type FCSPI_AtomicBoolType used by FCSPI to ensure read/write atomic + * + */ +#define FCSPI_TRUE ((uint8_t)1) + +/********* Local typedef ************/ +/** + * @brief FCSPI Mode type, master or slave. + */ +typedef enum { + FCSPI_MODE_SLAVE = 0, + FCSPI_MODE_MASTER = 1 +} FCSPI_MasterSlaveModeType; + +/** + * @brief Boolean type for FCSpi + */ +typedef uint8_t FCSPI_AtomicBoolType; + +/********* Local inline function ************/ + +/** + * @brief Read the FCSPI CTRL register value for all. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @return FCSPI CTRL regsiter value. + */ +LOCAL_INLINE uint32_t FCSPI_HWA_GetCtrlValue(FCSPI_Type *pFCSPI) +{ + return pFCSPI->CTRL; +} + +/** + * @brief Set FCSPI CTRL value, users should write the whole value to this register. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @param u32Value the value which will be written to the CTRL register. + */ +LOCAL_INLINE void FCSPI_HWA_SetCtrlValue(FCSPI_Type *pFCSPI, uint32_t u32Value) +{ + pFCSPI->CTRL = u32Value; +} + +/** + * @brief Enable the feature of FCSPI hardware, only for starting the feature of SPI module. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + */ +LOCAL_INLINE void FCSPI_HWA_ModuleEnable(FCSPI_Type *pFCSPI) +{ + pFCSPI->CTRL |= FCSPI_CTRL_M_EN(1); +} + +/** + * @brief Disable the feature of FCSPI, and shutdown the FCSPI module. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + */ +LOCAL_INLINE void FCSPI_HWA_ModuleDisable(FCSPI_Type *pFCSPI) +{ + pFCSPI->CTRL &= (~(FCSPI_CTRL_M_EN_MASK)); +} + +/** + * @brief Getting the FCSPI transfer status by reading the STATUS register. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @return the whole status of FCSPI transfer, which can be read in STATUS register. + */ +LOCAL_INLINE uint32_t FCSPI_HWA_GetStatus(FCSPI_Type *pFCSPI) +{ + return pFCSPI->STATUS; +} + +/** + * @brief Clear FCSPI STATUS register for certain function. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @param u32Value the value write to the register. + */ +LOCAL_INLINE void FCSPI_HWA_ClearStatus(FCSPI_Type *pFCSPI, uint32_t u32Value) +{ + pFCSPI->STATUS = u32Value; +} + +/** + * @brief Get FCSPI INT_EN register value for checking which interrupt is enabled. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @return FCSPI INT_EN regsiter value will be returned. + */ +LOCAL_INLINE uint32_t FCSPI_HWA_GetIntrruptEnableReg(FCSPI_Type *pFCSPI) +{ + return pFCSPI->INT_EN; +} + +/** + * @brief Set the FCSPI INT_EN register value for enable or disable some interrupts. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @param u32Value the value write to the register. + */ +LOCAL_INLINE void FCSPI_HWA_SetInterruptEnableReg(FCSPI_Type *pFCSPI, uint32_t u32Value) +{ + pFCSPI->INT_EN = u32Value; +} + +/** + * @brief Getting the DMA enabled status through the regsiter FCSPI DMA_EN value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @return FCSPI DMA_EN regsiter value + */ +LOCAL_INLINE uint32_t FCSPI_HWA_GetDMAEnableReg(FCSPI_Type *pFCSPI) +{ + return pFCSPI->DMA_EN; +} + +/** + * @brief Enable or disable the DMA feature by setting the FCSPI DMA_EN register value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @param u32Value the value write to the register. + */ +LOCAL_INLINE void FCSPI_HWA_SetDMAEnableReg(FCSPI_Type *pFCSPI, uint32_t u32Value) +{ + pFCSPI->DMA_EN = u32Value; +} + +/** + * @brief Get FCSPI CFG0 register value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @return FCSPI CFG0 regsiter value + */ +LOCAL_INLINE uint32_t FCSPI_HWA_GetCFG0Reg(FCSPI_Type *pFCSPI) +{ + return pFCSPI->CFG0; +} + +/** + * @brief Set FCSPI CFG0 register value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @param u32Value the value write to the register. + */ +LOCAL_INLINE void FCSPI_HWA_SetCFG0Reg(FCSPI_Type *pFCSPI, uint32_t u32Value) +{ + pFCSPI->CFG0 = u32Value; +} + +/** + * @brief Get FCSPI CFG1 register value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @return FCSPI CFG1 regsiter value + */ +LOCAL_INLINE uint32_t FCSPI_HWA_GetCFG1Reg(FCSPI_Type *pFCSPI) +{ + return pFCSPI->CFG1; +} + +/** + * @brief Set FCSPI CFG1 register value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @param u32Value the value write to the register. + */ +LOCAL_INLINE void FCSPI_HWA_SetCFG1Reg(FCSPI_Type *pFCSPI, uint32_t u32Value) +{ + pFCSPI->CFG1 = u32Value; +} + +/** + * @brief Set the FCSPI to master mode. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + */ +LOCAL_INLINE void FCSPI_HWA_SetMasterMode(FCSPI_Type *pFCSPI) +{ + pFCSPI->CFG1 |= FCSPI_CFG1_MASTER(1); +} + +/** + * @brief Set FCSPI to slave mode. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + */ +LOCAL_INLINE void FCSPI_HWA_SetSlaveMode(FCSPI_Type *pFCSPI) +{ + pFCSPI->CFG1 &= (~(FCSPI_CFG1_MASTER_MASK)); +} + +/** + * @brief Check the current mode status, master or slave. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @return the mode type of FCSPI, FCSPI_MODE_MASTER or FCSPI_MODE_SLAVE + */ +LOCAL_INLINE FCSPI_MasterSlaveModeType FCSPI_HWA_CheckMode(FCSPI_Type *pFCSPI) +{ + FCSPI_MasterSlaveModeType eRet = FCSPI_MODE_SLAVE; + + if ((pFCSPI->CFG1 & FCSPI_CFG1_MASTER_MASK) == FCSPI_CFG1_MASTER(1)) + { + eRet = FCSPI_MODE_MASTER; + } + + return eRet; +} + +/** + * @brief Get FCSPI MATCH0 register value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @return FCSPI MATCH0 regsiter value + */ +LOCAL_INLINE uint32_t FCSPI_HWA_GetMatch0Value(FCSPI_Type *pFCSPI) +{ + return pFCSPI->DATA_MATCH0; +} + +/** + * @brief Set FCSPI MATCH0 register value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @param u32Value the value write to the register. + */ +LOCAL_INLINE void FCSPI_HWA_SetMatch0Value(FCSPI_Type *pFCSPI, uint32_t u32Value) +{ + pFCSPI->DATA_MATCH0 = u32Value; +} + +/** + * @brief Get FCSPI MATCH1 register value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @return FCSPI MATCH1 regsiter value + */ +LOCAL_INLINE uint32_t FCSPI_HWA_GetMatch1Value(FCSPI_Type *pFCSPI) +{ + return pFCSPI->DATA_MATCH1; +} + +/** + * @brief Set FCSPI MATCH1 register value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @param u32Value the value write to the register. + */ +LOCAL_INLINE void FCSPI_HWA_SetMatch1Value(FCSPI_Type *pFCSPI, uint32_t u32Value) +{ + pFCSPI->DATA_MATCH1 = u32Value; +} + +/** + * @brief Get FCSPI CLK_CFG register value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @return FCSPI CLK_CFG regsiter value + */ +LOCAL_INLINE uint32_t FCSPI_HWA_GetClockConfig(FCSPI_Type *pFCSPI) +{ + return pFCSPI->CLK_CFG; +} + +/** + * @brief Set FCSPI CLK_CFG register value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @param u32Value the value write to the register. + */ +LOCAL_INLINE void FCSPI_HWA_SetClockConfig(FCSPI_Type *pFCSPI, uint32_t u32Value) +{ + pFCSPI->CLK_CFG = u32Value; +} + +/** + * @brief Get FCSPI FIFO_WTM register value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @return FCSPI FIFO_WTM regsiter value + */ +LOCAL_INLINE uint32_t FCSPI_HWA_GetFIFOWaterMark(FCSPI_Type *pFCSPI) +{ + return pFCSPI->FIFO_WTM; +} + +/** + * @brief Set FCSPI FIFO_WTM register value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @param u8RxWatermark the rx water mark value. + * @param u8TxWatermark the tx water mark value. + */ +LOCAL_INLINE void FCSPI_HWA_SetWatermark(FCSPI_Type *pFCSPI, uint8_t u8RxWatermark, uint8_t u8TxWatermark) +{ + uint32_t u32Flag = 0U; + + u32Flag |= ((uint32_t)u8RxWatermark << FCSPI_FIFO_WTM_RXWATER_SHIFT); + u32Flag |= ((uint32_t)u8TxWatermark << FCSPI_FIFO_WTM_TXWATER_SHIFT); + + pFCSPI->FIFO_WTM = u32Flag; +} + +/** + * @brief Get FCSPI RX FIFO count. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @return the real count value of rx fifo. + */ +LOCAL_INLINE uint8_t FCSPI_HWA_GetRxFifoStoredCount(FCSPI_Type *pFCSPI) +{ + return (uint8_t)(((pFCSPI->FIFO_STATUS) & FCSPI_FIFO_STATUS_RXCNT_MASK) >> FCSPI_FIFO_STATUS_RXCNT_SHIFT); +} + +/** + * @brief Get FCSPI TX FIFO count value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @return the real count of tx fifo. + */ +LOCAL_INLINE uint8_t FCSPI_HWA_GetTxFifoStoredCount(FCSPI_Type *pFCSPI) +{ + return (uint8_t)(((pFCSPI->FIFO_STATUS) & FCSPI_FIFO_STATUS_TXCNT_MASK) >> FCSPI_FIFO_STATUS_TXCNT_SHIFT); +} + +/** + * @brief Get FCSPI TR_CTRL register value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @return FCSPI TR_CTRL regsiter value + */ +LOCAL_INLINE uint32_t FCSPI_HWA_GetTxRxControl(FCSPI_Type *pFCSPI) +{ + return pFCSPI->TR_CTRL; +} + +/** + * @brief Set FCSPI TR_CTRL register value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @param u32Value the value write to the register. + */ +LOCAL_INLINE void FCSPI_HWA_SetTxRxControl(FCSPI_Type *pFCSPI, uint32_t u32Value) +{ + pFCSPI->TR_CTRL = u32Value; +} + +/** + * @brief Set RX enable status in register FCSPI TR_CTRL. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @param eEnable FCSPI_TRUE for enabled, FCSPI_FALSE for disable. + */ +LOCAL_INLINE void FCSPI_HWA_EnableRxDataMask(FCSPI_Type *pFCSPI, FCSPI_AtomicBoolType eEnable) +{ + if (FCSPI_FALSE == eEnable) + { + pFCSPI->TR_CTRL |= FCSPI_TR_CTRL_RX_MSK_MASK; + } + else + { + pFCSPI->TR_CTRL &= (~(FCSPI_TR_CTRL_RX_MSK_MASK)); + } +} + +/** + * @brief Set TX enable status in register FCSPI TR_CTRL. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @param eEnable FCSPI_TRUE for enabled, FCSPI_FALSE for disable. + */ +LOCAL_INLINE void FCSPI_HWA_EnableTxDataMask(FCSPI_Type *pFCSPI, FCSPI_AtomicBoolType eEnable) +{ + if (FCSPI_FALSE == eEnable) + { + pFCSPI->TR_CTRL |= FCSPI_TR_CTRL_TX_MSK_MASK; + } + else + { + pFCSPI->TR_CTRL &= (~(FCSPI_TR_CTRL_TX_MSK_MASK)); + } +} + +/** + * @brief Set FCSPI TX_DATA register value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @param u32Value the value write to the register. + */ +LOCAL_INLINE void FCSPI_HWA_WriteData(FCSPI_Type *pFCSPI, uint32_t u32Value) +{ + pFCSPI->TX_DATA = u32Value; +} + +/** + * @brief Get the address of FCSPI TX_DATA register,return value is the pointer address of TX_DATA. + * + * @param pFCSPI FCSPI instance，e.g. FCSPI0, FCSPI1. + * @return FCSPI TX_DATA address. + */ +LOCAL_INLINE uint32_t volatile *FCSPI_HWA_GetTxDataAddr(FCSPI_Type *pFCSPI) +{ + return (uint32_t volatile *)&(pFCSPI->TX_DATA); +} + +/** + * @brief Read FCSPI RX_STATUS register value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @return FCSPI RX_STATUS regsiter value + */ +LOCAL_INLINE uint32_t FCSPI_HWA_GetRxStatus(FCSPI_Type *pFCSPI) +{ + return pFCSPI->RX_STATUS; +} + +/** + * @brief Read FCSPI RX_DATA register value. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @return FCSPI RX_DATA regsiter value + */ +LOCAL_INLINE uint32_t FCSPI_HWA_ReadData(FCSPI_Type *pFCSPI) +{ + return pFCSPI->RX_DATA; +} + +/** + * @brief Get the address of FCSPI RX_DATA register,return value is the pointer address of RX_DATA. + * + * @param pFCSPI FCSPI instance，e.g. FCSPI0, FCSPI1. + * @return FCSPI RX_DATA address. + */ +LOCAL_INLINE uint32_t volatile const *FCSPI_HWA_GetRxDataAddr(FCSPI_Type *pFCSPI) +{ + return &(pFCSPI->RX_DATA); +} + + +#endif /* #ifndef _HWA_FCPIT_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_fcuart.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_fcuart.h new file mode 100644 index 0000000..1cb80a5 --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_fcuart.h @@ -0,0 +1,830 @@ +/** + * @file HwA_fcuart.h + * @author Flagchip + * @brief FC7xxx FCUart register API + * @version 0.1.0 + * @date 2024-01-14 + * + * @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. + * + */ +/******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-14 Flagchip0122 N/A FC7xxx internal release version + ********************************************************************************/ + +#ifndef _HWA_FCUART_H_ +#define _HWA_FCUART_H_ + +#include "device_header.h" + + +/** + * @addtogroup HwA_fcuart + * @{ + */ + + +/********* Local typedef ************/ + +/** + * @brief UART STAT register flag + * + */ +typedef enum +{ + FCUART_STAT_LBKDIF = (int32_t)FCUART_STAT_LBKDIF_MASK, /**< FCUART_STAT_LBKDIF LIN Break Detect Interrupt Flag, w1c */ + FCUART_STAT_RPAEIF = (int32_t)FCUART_STAT_RPAEIF_MASK, /**< FCUART_STAT_RPAEIF RXD Pin Active Edge Interrupt Flag, w1c */ + FCUART_STAT_MSBF = (int32_t)FCUART_STAT_MSBF_MASK, /**< FCUART_STAT_MSBF MSB First, RW */ + FCUART_STAT_RXINV = (int32_t)FCUART_STAT_RXINV_MASK, /**< FCUART_STAT_RXINV Receive Data Inversion, RW */ + FCUART_STAT_RWUID = (int32_t)FCUART_STAT_RWUID_MASK, /**< FCUART_STAT_RWUID Receive Wake Up Idle Detect, RW */ + FCUART_STAT_BCGL = (int32_t)FCUART_STAT_BCGL_MASK, /**< FCUART_STAT_BCGL Break Character Generation Length, RW */ + FCUART_STAT_LBKDE = (int32_t)FCUART_STAT_LBKDE_MASK, /**< FCUART_STAT_LBKDE LIN Break Detection Enable, RW */ + FCUART_STAT_RAF = (int32_t)FCUART_STAT_RAF_MASK, /**< FCUART_STAT_RAF Receiver Active Flag, RO */ + FCUART_STAT_TDREF = (int32_t)FCUART_STAT_TDREF_MASK, /**< FCUART_STAT_TDREF Transmit Data Register Empty Flag, RO */ + FCUART_STAT_TCF = (int32_t)FCUART_STAT_TCF_MASK, /**< FCUART_STAT_TCF Transmission Complete Flag, RO */ + FCUART_STAT_RDRFF = (int32_t)FCUART_STAT_RDRFF_MASK, /**< FCUART_STAT_RDRFF Receive Data Register Full Flag, RO */ + FCUART_STAT_IDLEF = (int32_t)FCUART_STAT_IDLEF_MASK, /**< FCUART_STAT_IDLEF Idle Line Flag, w1c */ + FCUART_STAT_RORF = (int32_t)FCUART_STAT_RORF_MASK, /**< FCUART_STAT_RORF Receiver Overrun Flag, w1c */ + FCUART_STAT_NF = (int32_t)FCUART_STAT_NF_MASK, /**< FCUART_STAT_NF Noise Flag, w1c */ + FCUART_STAT_FEF = (int32_t)FCUART_STAT_FEF_MASK, /**< FCUART_STAT_FEF Frame Error Flag, w1c */ + FCUART_STAT_PEF = (int32_t)FCUART_STAT_PEF_MASK, /**< FCUART_STAT_PEF Parity Error Flag, w1c */ + FCUART_STAT_M0F = (int32_t)FCUART_STAT_M0F_MASK, /**< FCUART_STAT_M0F Match address 0 Flag, w1c */ + FCUART_STAT_M1F = (int32_t)FCUART_STAT_M1F_MASK, /**< FCUART_STAT_M1F Match address 1 Flag, w1c */ + FCUART_STAT_RPEF = (int32_t)FCUART_STAT_RPEF_MASK, /**< FCUART_STAT_RPEF Receive Data Parity Error Flag, w1c */ + FCUART_STAT_TPEF = (int32_t)FCUART_STAT_TPEF_MASK /**< FCUART_STAT_TPEF Transmit Data Parity Error Flag, w1c */ +} FCUART_StatType; + +/** + * @brief UART data bit length mode + * + */ +typedef enum +{ + UART_BITMODE_8 = 0, /**< UART_BITMODE_8 */ + UART_BITMODE_9 /**< UART_BITMODE_9 */ +} FCUART_BitModeType; + +/** + * @brief UART stop bits number + * + */ +typedef enum +{ + UART_STOPBIT_NUM_1 = 0, /**< UART_STOPBIT_NUM_1 */ + UART_STOPBIT_NUM_2 /**< UART_STOPBIT_NUM_2 */ +} FCUART_StopBitNumType; + +/** + * @brief UART parity check type + * + */ +typedef enum +{ + UART_PARITY_EVEN = 0, /**< UART_PARITY_EVEN */ + UART_PARITY_ODD /**< UART_PARITY_ODD */ +} FCUART_ParityType; + + + + +/********* Local inline function ************/ +/** + * @brief Get Stat Flag + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_SetSoftWareReset(FCUART_Type *pUart) +{ + pUart->RST |= FCUART_RST_RST_MASK; + pUart->RST &= ~FCUART_RST_RST_MASK; +} + +/** + * @brief Get Stat Flag + * + * @param pUart UART instance value + * @param eStatusType stat type + * @return FCUART STAT status flag + */ +LOCAL_INLINE uint32_t FCUART_HWA_GetStatus(FCUART_Type *pUart, FCUART_StatType eStatusType) +{ + return (pUart->STAT & (uint32_t)eStatusType); +} + +/** + * @brief Clear Stat Flag + * + * @param pUart UART instance value + * @param u32StatusType stat type + */ +LOCAL_INLINE void FCUART_HWA_ClearStatus(FCUART_Type *pUart, uint32_t u32StatusType) +{ + pUart->STAT |= u32StatusType; +} + +/** + * @brief Enable Interrupt + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_EnableInterrupt(FCUART_Type *pUart, uint32 u32Value) +{ + pUart->CTRL |= u32Value; /* Interrupt Enable */ +} + +/** + * @brief Disable Interrupt + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_DisableInterrupt(FCUART_Type *pUart, uint32 u32Value) +{ + pUart->CTRL &= ~u32Value; /* Interrupt Disable */ +} + +/** + * @brief Enable Receive Interrupt + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_EnableReceiveInterrupt(FCUART_Type *pUart) +{ + pUart->CTRL |= FCUART_CTRL_RIE_MASK; /* Receive Interrupt Enable */ +} + +/** + * @brief Disable Receive Interrupt + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_DisableReceiveInterrupt(FCUART_Type *pUart) +{ + pUart->CTRL &= ~FCUART_CTRL_RIE_MASK; /* Receive Interrupt Enable */ + +} + +/** + * @brief Enable Error Interrupt + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_EnableErrorInterrupt(FCUART_Type *pUart) +{ + pUart->CTRL |= FCUART_CTRL_ORIE_MASK | /* Overrun Interrupt Enable */ + FCUART_CTRL_NEIE_MASK | /* Noise Error Interrupt Enable */ + FCUART_CTRL_FEIE_MASK | /* Frame Error Interrupt Enable */ + FCUART_CTRL_PEIE_MASK; /* Parity Error Interrupt Enable */ +} + +/** + * @brief Disable Error Interrupt + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_DisableErrorInterrupt(FCUART_Type *pUart) +{ + pUart->CTRL &= ~(FCUART_CTRL_ORIE_MASK | /* Overrun Interrupt Enable */ + FCUART_CTRL_NEIE_MASK | /* Noise Error Interrupt Enable */ + FCUART_CTRL_FEIE_MASK | /* Frame Error Interrupt Enable */ + FCUART_CTRL_PEIE_MASK); /* Parity Error Interrupt Enable */ + +} + +/** + * @brief Set FCUART Ctrl register + * + * @param pUart UART instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCUART_HWA_SetCtrl(FCUART_Type *pUart, uint32_t u32Value) +{ + pUart->CTRL = u32Value; +} + +/** + * @brief Get FCUART Ctrl register + * + * @param pUart UART instance value + * @return Register value + */ +LOCAL_INLINE uint32_t FCUART_HWA_GetCtrl(FCUART_Type *pUart) +{ + return pUart->CTRL; +} + +/** + * @brief Attach FCUART Ctrl register + * + * @param pUart UART instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCUART_HWA_AttachCtrl(FCUART_Type *pUart, uint32_t u32Value) +{ + pUart->CTRL |= u32Value; +} + +/** + * @brief Set FCUART Baud register + * + * @param pUart UART instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCUART_HWA_SetBaud(FCUART_Type *pUart, uint32_t u32Value) +{ + pUart->BAUD = u32Value; +} + +/** + * @brief Get FCUART baud register + * + * @param pUart UART instance value + * @return Register value + */ +LOCAL_INLINE uint32_t FCUART_HWA_GetBaud(FCUART_Type *pUart) +{ + return pUart->BAUD; +} + +/** + * @brief Attach FCUART Baud register + * + * @param pUart UART instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCUART_HWA_AttachBaud(FCUART_Type *pUart, uint32_t u32Value) +{ + pUart->BAUD |= u32Value; +} + +/** + * @brief Set FCUART Fifo register + * + * @param pUart UART instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCUART_HWA_SetFifo(FCUART_Type *pUart, uint32_t u32Value) +{ + pUart->FIFO = u32Value; +} + +/** + * @brief Get FCUART fifo register + * + * @param pUart UART instance value + * @return Register value + */ +LOCAL_INLINE uint32_t FCUART_HWA_GetFifo(FCUART_Type *pUart) +{ + return pUart->FIFO; +} + +/** + * @brief Get FCUART fifo register + * + * @param pUart UART instance value + * @return Register value + */ +LOCAL_INLINE bool FCUART_HWA_GetEnStatusRxFifo(FCUART_Type *pUart) +{ + return ((((pUart->FIFO & FCUART_FIFO_RXFEN_MASK) >> FCUART_FIFO_RXFEN_SHIFT) == 1U) ? true: false); +} + +/** + * @brief Get FCUART fifo register + * + * @param pUart UART instance value + * @return Register value + */ +LOCAL_INLINE bool FCUART_HWA_GetEnStatusTxFifo(FCUART_Type *pUart) +{ + return ((((pUart->FIFO & FCUART_FIFO_TXFEN_MASK) >> FCUART_FIFO_TXFEN_SHIFT) == 1U) ? true: false); +} + +/** + * @brief Attach FCUART Fifo register + * + * @param pUart UART instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCUART_HWA_AttachFifo(FCUART_Type *pUart, uint32_t u32Value) +{ + pUart->FIFO |= u32Value; +} + +/** + * @brief Set FCUART WaterMark register + * + * @param pUart UART instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCUART_HWA_SetWaterMark(FCUART_Type *pUart, uint32_t u32Value) +{ + pUart->WATERMARK = u32Value; +} + +/** + * @brief Get FCUART Rx WaterMark + * + * @param pUart UART instance value + * @return Rxcount value + */ +LOCAL_INLINE uint8_t FCUART_HWA_GetRxWaterMark(FCUART_Type *pUart) +{ + return ((uint8_t)(((pUart->WATERMARK) & FCUART_WATERMARK_RXWATER_MASK) >> FCUART_WATERMARK_RXWATER_SHIFT)); +} + +/** + * @brief Get FCUART Tx WaterMark + * + * @param pUart UART instance value + * @return Rxcount value + */ +LOCAL_INLINE uint8_t FCUART_HWA_GetTxWaterMark(FCUART_Type *pUart) +{ + return ((uint8_t)(((pUart->WATERMARK) & FCUART_WATERMARK_TXWATER_MASK) >> FCUART_WATERMARK_TXWATER_SHIFT)); +} + +/** + * @brief Get FCUART WaterMark Rxcount + * + * @param pUart UART instance value + * @return Rxcount value + */ +LOCAL_INLINE uint8_t FCUART_HWA_GetFifoRxCount(FCUART_Type *pUart) +{ + return ((uint8_t)(((pUart->WATERMARK) & FCUART_WATERMARK_RXCOUNT_MASK) >> FCUART_WATERMARK_RXCOUNT_SHIFT)); +} + +/** + * @brief Get FCUART WaterMark Txcount + * + * @param pUart UART instance value + * @return Rxcount value + */ +LOCAL_INLINE uint8_t FCUART_HWA_GetFifoTxCount(FCUART_Type *pUart) +{ + return ((uint8_t)(((pUart->WATERMARK) & FCUART_WATERMARK_TXCOUNT_MASK) >> FCUART_WATERMARK_TXCOUNT_SHIFT)); +} + +/** + * @brief Attach FCUART WaterMark register + * + * @param pUart UART instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCUART_HWA_AttachWaterMark(FCUART_Type *pUart, uint32_t u32Value) +{ + pUart->WATERMARK |= u32Value; +} + +/** + * @brief Set FCUART Match register + * + * @param pUart UART instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCUART_HWA_SetMatch(FCUART_Type *pUart, uint32_t u32Value) +{ + pUart->MATCH = u32Value; +} + +/** + * @brief Attach FCUART Match register + * + * @param pUart UART instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCUART_HWA_AttachMatch(FCUART_Type *pUart, uint32_t u32Value) +{ + pUart->MATCH |= u32Value; +} + +/** + * @brief Get FCUART Match register + * + * @param pUart UART instance value + * @return Register value + */ +LOCAL_INLINE uint32_t FCUART_HWA_GetMatch(FCUART_Type *pUart) +{ + return pUart->MATCH; +} + +/** + * @brief Read FCUART STAT register + * + * @param pUart UART instance value + * @return STAT read value + */ +LOCAL_INLINE uint32_t FCUART_HWA_GetSTAT(FCUART_Type *pUart) +{ + return pUart->STAT; +} + +/** + * @brief Write 1 Clear FCUART STAT register + * + * @param pUart UART instance value + * @param u32Value written value + */ +LOCAL_INLINE void FCUART_HWA_WriteClearSTAT(FCUART_Type *pUart, uint32_t u32Value) +{ + pUart->STAT |= u32Value; +} + +/** + * @brief Set Bit Mode and Parity + * + * @param pUart UART instance value + * @param eBitMode is bit mode, 8 or 9 bits + */ +LOCAL_INLINE void FCUART_HWA_SetBitMode(FCUART_Type *pUart, FCUART_BitModeType eBitMode) +{ + uint32_t u32RegVal = pUart->CTRL; + pUart->CTRL = ((u32RegVal & (~ FCUART_CTRL_BMSEL_MASK)) | FCUART_CTRL_BMSEL(eBitMode)); +} + +/** + * @brief Set Bit Mode and Parity + * + * @param pUart UART instance value + * @param bParityEnable If enable Parity, set 1U, or set 0U + * @param eParityType Parity type, odd-even + */ +LOCAL_INLINE void FCUART_HWA_SetParity(FCUART_Type *pUart, FCUART_ParityType eParityType, bool bParityEnable) +{ + uint32_t u32RegVal = pUart->CTRL; + pUart->CTRL = ((u32RegVal & (~ FCUART_CTRL_PE_MASK | FCUART_CTRL_PT_MASK)) | + FCUART_CTRL_PE(bParityEnable) | + FCUART_CTRL_PT(eParityType) ); +} + +/** + * @brief Set Bit Mode and Parity + * + * @param pUart UART instance value + * @param eStopBit stop bits number 1 or 2 bits + */ +LOCAL_INLINE void FCUART_HWA_SetStopBit(FCUART_Type *pUart, FCUART_StopBitNumType eStopBit) +{ + uint32_t u32RegVal = pUart->BAUD; + pUart->BAUD = ((u32RegVal & (~ FCUART_BAUD_SBNS_MASK)) | FCUART_BAUD_SBNS(eStopBit)); +} + +/** + * @brief Enable Receive DMA + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_EnableReceiveDMA(FCUART_Type *pUart) +{ + pUart->BAUD |= FCUART_BAUD_RDMAEN_MASK; +} + +/** + * @brief Disable Receive DMA + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_DisableReceiveDMA(FCUART_Type *pUart) +{ + pUart->BAUD &= ~FCUART_BAUD_RDMAEN_MASK; + +} + +/** + * @brief Enable Receive FIFO + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_EnableReceiveFIFO(FCUART_Type *pUart) +{ + pUart->FIFO |= FCUART_FIFO_RXFEN_MASK; +} + +/** + * @brief Disable Receive FIFO + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_DisableReceiveFIFO(FCUART_Type *pUart) +{ + pUart->FIFO &= ~FCUART_FIFO_RXFEN_MASK; + +} + +/** + * @brief Clear Fifo Overflow/Underflow flag + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_ClearFIFOErrorFlag(FCUART_Type *pUart) +{ + pUart->FIFO |= FCUART_FIFO_TXOF_MASK | FCUART_FIFO_RXUF_MASK; +} + + +/** + * @brief Set Data Value + * + * @param pUart UART instance value + * @param u32Data Set data + */ +LOCAL_INLINE void FCUART_HWA_SetData(FCUART_Type *pUart, uint32_t u32Data) +{ + pUart->DATA = u32Data; /* data 32 bit */ +} + +/** + * @brief Get Data Value + * + * @param pUart UART instance value + * @return the data value + */ +LOCAL_INLINE uint8_t FCUART_HWA_GetData(FCUART_Type *pUart) +{ + uint8_t u8Data; + + u8Data = *((volatile uint8_t *)&pUart->DATA); /* data 32 bit */ + + return u8Data; +} + +/** + * @brief Set R8T9 bit + * + * @param pUart UART instance value + * @return the data value + */ +LOCAL_INLINE void FCUART_HWA_SetR8T9(FCUART_Type *pUart, uint8_t u8Data) +{ + uint32_t u32RegVal = pUart->CTRL; + pUart->CTRL = ((u32RegVal & (~ FCUART_CTRL_R8T9_MASK)) | FCUART_CTRL_R8T9(u8Data)); +} + +/** + * @brief Get R8T9 bit + * + * @param pUart UART instance value + * @return the data value + */ +LOCAL_INLINE uint8_t FCUART_HWA_GetR8T9(FCUART_Type *pUart) +{ + return (uint8_t)((pUart->CTRL & FCUART_CTRL_R8T9_MASK) >> FCUART_CTRL_R8T9_SHIFT); +} + +/** + * @brief Set R9T8 bit + * + * @param pUart UART instance value + * @return the data value + */ +LOCAL_INLINE void FCUART_HWA_SetR9T8(FCUART_Type *pUart, uint8_t u8Data) +{ + uint32_t u32RegVal = pUart->CTRL; + pUart->CTRL = ((u32RegVal & (~ FCUART_CTRL_R9T8_MASK)) | FCUART_CTRL_R9T8(u8Data)); +} + +/** + * @brief Get R9T8 bit + * + * @param pUart UART instance value + * @return the data value + */ +LOCAL_INLINE uint8_t FCUART_HWA_GetR9T8(FCUART_Type *pUart) +{ + return (uint8_t)((pUart->CTRL & FCUART_CTRL_R9T8_MASK) >> FCUART_CTRL_R9T8_SHIFT); +} + +/** + * @brief Reset the instance by software. + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_SoftwareReset(FCUART_Type *pUart) +{ + pUart->RST |= FCUART_RST_RST_MASK; + pUart->RST &= ~FCUART_RST_RST_MASK; +} + +/** + * @brief Set fcuart TX Transfer enable or disable. + * + * @param pUart UART instance value + * @param bEnable Enable cmd, false for disable, true for enable. + */ +LOCAL_INLINE void FCUART_HWA_SetTxTransfer(FCUART_Type *pUart, bool bEnable) +{ + if (true == bEnable) + { + pUart->CTRL |= FCUART_CTRL_TE_MASK; + } + else + { + pUart->CTRL &= ~FCUART_CTRL_TE_MASK; + } +} + +/** + * @brief Set fcuart RX Transfer enable or disable. + * + * @param pUart UART instance value + * @param bEnable Enable cmd, false for disable, true for enable. + */ +LOCAL_INLINE void FCUART_HWA_SetRxTransfer(FCUART_Type *pUart, bool bEnable) +{ + if (true == bEnable) + { + pUart->CTRL |= FCUART_CTRL_RE_MASK; + } + else + { + pUart->CTRL &= ~FCUART_CTRL_RE_MASK; + } +} + +/** + * @brief Set lin break detect interrupt. + * + * @param pUart UART instance value + * @param bEnable Enable cmd, false for disable, true for enable. + */ +LOCAL_INLINE void FCUART_HWA_SetLinBreakDetectInterrupt(FCUART_Type *pUart, bool bEnable) +{ + if (true == bEnable) + { + pUart->BAUD |= FCUART_BAUD_LBKDIE_MASK; + } + else + { + pUart->BAUD &= ~FCUART_BAUD_LBKDIE_MASK; + } +} + +/** + * @brief Set lin break detect feature enable. + * + * @param pUart UART instance value + * @param bEnable Enable cmd, false for disable, true for enable. + */ +LOCAL_INLINE void FCUART_HWA_SetLinBreakDetectEnable(FCUART_Type *pUart, bool bEnable) +{ + if (true == bEnable) + { + pUart->STAT |= (FCUART_STAT_LBKDE_MASK | FCUART_STAT_BCGL_MASK); + } + else + { + pUart->STAT &= ~(FCUART_STAT_LBKDE_MASK | FCUART_STAT_BCGL_MASK); + } +} + +/** + * @brief Send a lin break field. + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_SendBreakField(FCUART_Type *pUart) +{ + pUart->DATA |= FCUART_DATA_FETSC_MASK; +} + +/** + * @brief Set uart receive active interrupt. + * + * @param pUart UART instance value + * @param bEnable Enable cmd, false for disable, true for enable. + */ +LOCAL_INLINE void FCUART_HWA_SetReceiveActiveInterrupt(FCUART_Type *pUart, bool bEnable) +{ + if (true == bEnable) + { + pUart->BAUD |= FCUART_BAUD_RIAEIE_MASK; + } + else + { + pUart->BAUD &= ~FCUART_BAUD_RIAEIE_MASK; + } +} + +/** + * @brief Set uart receive active interrupt. + * + * @param pUart UART instance value + * @param return false for disable, true for enable. + */ +LOCAL_INLINE bool FCUART_HWA_GetReceiveActiveInterrupt(FCUART_Type *pUart) +{ + bool bRetVal = false; + + if (0U != (pUart->BAUD & FCUART_BAUD_RIAEIE_MASK)) + { + bRetVal = true; + } + + return bRetVal; +} + +/** + * @brief Set FCUART inverse feature. + * + * @param pUart UART instance value + * @param bEnable false for disable, true for enable. + */ +LOCAL_INLINE void FCUART_HWA_SetReceiveDataInverse(FCUART_Type *pUart, bool bEnable) +{ + if (true == bEnable) + { + pUart->STAT |= FCUART_STAT_RXINV_MASK; + } + else + { + pUart->STAT &= ~FCUART_STAT_RXINV_MASK; + } +} + +/** + * @brief Get the FCUART inverse bit value. + * + * @param pUart UART instance value + * @param return false for disable, true for enable. + */ +LOCAL_INLINE bool FCUART_HWA_GetReceiveDataInverse(FCUART_Type *pUart) +{ + bool bRetVal = false; + + if (0U != (pUart->STAT & FCUART_STAT_RXINV_MASK)) + { + bRetVal = true; + } + + return bRetVal; +} + +/** + * @brief Set the FCUART frame error interrupt. + * + * @param pUart UART instance value + * @param bEnable false for disable, true for enable. + */ +LOCAL_INLINE void FCUART_HWA_SetFrameErrorInterrupt(FCUART_Type *pUart, bool bEnable) +{ + if (true == bEnable) + { + pUart->CTRL |= FCUART_CTRL_FEIE_MASK; + } + else + { + pUart->CTRL &= ~FCUART_CTRL_FEIE_MASK; + } +} + +/** + * @brief Enable the FCUART loop mode. + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_EnableLoopMode(FCUART_Type *pUart) +{ + pUart->CTRL |= FCUART_CTRL_LOOPMS_MASK; +} + +/** + * @brief Disable the FCUART loop mode. + * + * @param pUart UART instance value + */ +LOCAL_INLINE void FCUART_HWA_DisableLoopMode(FCUART_Type *pUart) +{ + pUart->CTRL &= ~FCUART_CTRL_LOOPMS_MASK; +} + +/** + * \brief Set FCUART MODIR value + * + * \param pUart UART instance value + * \param u32Data Set data + */ +LOCAL_INLINE void FCUART_HWA_SetModir(FCUART_Type *pUart, uint32_t u32Data) +{ + pUart->MODIR = u32Data; /* data 32 bit */ +} + +/** + * \brief Get FCUART MODIR value + * + * \param pUart UART instance value + * \param u32Data Get data + */ +LOCAL_INLINE uint32_t FCUART_HWA_GetModir(FCUART_Type *pUart) +{ + return pUart->MODIR ; +} + +/** @}*/ + +#endif /* end for #ifndef _HWA_FCUART_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_flexcan.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_flexcan.h new file mode 100644 index 0000000..0a3d69b --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_flexcan.h @@ -0,0 +1,1001 @@ +/** + * @file fc7xxx_driver_flexcan.h + * @author Flagchip + * @brief FC7xxx FlexCAN register API + * @version 0.1.0 + * @date 2024-1-13 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ + +/* ******************************************************************************** + * Revision History: + * + * Version Date Author Descriptions + * --------- ---------- ------------ --------------- + * 0.1.0 2024-1-13 Flagchip0112 First version for FC7240 + ******************************************************************************** */ + +#ifndef _HWA_FLEXCAN_H_ +#define _HWA_FLEXCAN_H_ + +#include "device_header.h" + + + + + +/* ################################################################################## */ +/* ####################################### Macro #################################### */ + +/* ****************************** Message Buffer Structure ************************************* */ + +/* ************************************************ 8bytes data ******************************************************* */ +/* 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 */ +/* 0x00 | EDL | BRS | ESI | | CODE | | SRR | IDE | RTR | DLC | TIME STAMP | */ +/* 0x04 | PRIO | ID (STD/EXT high 11bits) | ID (EXT low 18bits) | */ +/* 0x08 | Data Byte 0 | Data Byte 1 | Data Byte 2 | Data Byte 3 | */ +/* 0x0C | Data Byte 4 | Data Byte 5 | Data Byte 6 | Data Byte 7 | */ + + +/* ************************************************ 16bytes data ****************************************************** */ +/* 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 */ +/* 0x00 | EDL | BRS | ESI | | CODE | | SRR | IDE | RTR | DLC | TIME STAMP | */ +/* 0x04 | PRIO | ID (STD/EXT high 11bits) | ID (EXT low 18bits) | */ +/* 0x08 | Data Byte 0 | Data Byte 1 | Data Byte 2 | Data Byte 3 | */ +/* 0x0C | Data Byte 4 | Data Byte 5 | Data Byte 6 | Data Byte 7 | */ +/* ................................ */ +/* 0x1C | Data Byte 12 | Data Byte 13 | Data Byte 14 | Data Byte 15| */ + + +/* ************************************************ 32bytes data ****************************************************** */ +/* 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 */ +/* 0x00 | EDL | BRS | ESI | | CODE | | SRR | IDE | RTR | DLC | TIME STAMP | */ +/* 0x04 | PRIO | ID (STD/EXT high 11bits) | ID (EXT low 18bits) | */ +/* 0x08 | Data Byte 0 | Data Byte 1 | Data Byte 2 | Data Byte 3 | */ +/* 0x0C | Data Byte 4 | Data Byte 5 | Data Byte 6 | Data Byte 7 | */ +/* ................................ */ +/* 0x30 | Data Byte 28 | Data Byte 29 | Data Byte 30 | Data Byte 31| */ + + +/* ************************************************ 64bytes data ****************************************************** */ +/* 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 */ +/* 0x00 | EDL | BRS | ESI | | CODE | | SRR | IDE | RTR | DLC | TIME STAMP | */ +/* 0x04 | PRIO | ID (STD/EXT high 11bits) | ID (EXT low 18bits) | */ +/* 0x08 | Data Byte 0 | Data Byte 1 | Data Byte 2 | Data Byte 3 | */ +/* 0x0C | Data Byte 4 | Data Byte 5 | Data Byte 6 | Data Byte 7 | */ +/* ................................ */ +/* 0x44 | Data Byte 60 | Data Byte 61 | Data Byte 62 | Data Byte 63| */ + + +/** + * @addtogroup HwA_flexcan + * @{ + */ + + +/** Register address with offset */ +#define FLEXCAN_REGISTER_WITHOFFSET(reg,offset1,offset2) ((uint32_t)(reg)+(uint32_t)(offset1)+(uint32_t)(offset2)) +/** Get register value */ +#define FLEXCAN_REG32_CONTENT(reg) (*((uint32_t*)(reg))) + + + + +/** U32 value around */ +#define FLEXCAN_U32MACRO(var) ((uint32_t)(var)) +#define FLEXCAN_U32SHIFT(var,mask,shift) ((uint32_t)((((uint32_t)(var))&(mask))<<(shift))) +#define FLEXCAN_U32NOTSHIFT(mask,shift) ((uint32_t)(~(((uint32_t)(mask))<<(shift)))) + + +/* legacy message buffer */ + +/** Legacy/EnHanced Message Buffer Header */ +#define FLEXCAN_MB_HEADER_BYTELEN 8UL +/** Legacy Message Buffer Address */ +#define FLEXCAN_MB_ADDR(mbOffset, mbIndex, dataLen) FLEXCAN_U32MACRO(FLEXCAN_U32MACRO(mbOffset)+FLEXCAN_U32MACRO(mbIndex)*(FLEXCAN_U32MACRO(dataLen)+FLEXCAN_MB_HEADER_BYTELEN)) + + +/** Legacy Message Buffer word n Address */ +#define FLEXCAN_MB_WORDN_ADDR(mbOffset, mbIndex, dataLen, offset) (FLEXCAN_MB_ADDR((mbOffset), (mbIndex), (dataLen))+FLEXCAN_U32MACRO(offset)) + +/** Legacy Message Buffer Data Address */ +/* #define FLEXCAN_MB_DATA_ADDR_GET(mbOffset, mbIndex, dataLen) (FLEXCAN_MB_WORDN_ADDR((mbOffset), (mbIndex), (dataLen),2U)) */ + +/** Legacy Message Buffer EDL Get */ +#define FLEXCAN_MB_EDL_GET(edlAddr) ((FLEXCAN_REG32_CONTENT(edlAddr)>>31)&0x01U) +/** Legacy Message Buffer EDL Clear */ +#define FLEXCAN_MB_EDL_CLR(edlAddr) (FLEXCAN_REG32_CONTENT(edlAddr) &= FLEXCAN_U32NOTSHIFT(0x01U,31)) +/** Legacy Message Buffer EDL Attach */ +#define FLEXCAN_MB_EDL_ATTACH(edlAddr,var) (FLEXCAN_REG32_CONTENT(edlAddr) |= FLEXCAN_U32SHIFT(var,0x01U,31)) +/** Legacy Message Buffer EDL Set */ +#define FLEXCAN_MB_EDL_SET(edlAddr,var) FLEXCAN_MB_EDL_CLR(edlAddr); FLEXCAN_MB_EDL_ATTACH(edlAddr,var) + + +/** Legacy Message Buffer BRS Get */ +#define FLEXCAN_MB_BRS_GET(brsAddr) (((FLEXCAN_REG32_CONTENT(brsAddr))>>30)&0x01U) +/** Legacy Message Buffer BRS Clear */ +#define FLEXCAN_MB_BRS_CLR(brsAddr) (FLEXCAN_REG32_CONTENT(brsAddr) &= FLEXCAN_U32NOTSHIFT(0x01U,30)) +/** Legacy Message Buffer BRS Attach */ +#define FLEXCAN_MB_BRS_ATTACH(brsAddr,var) (FLEXCAN_REG32_CONTENT(brsAddr) |= FLEXCAN_U32SHIFT(var,0x01U,30)) +/** Legacy Message Buffer BRS set */ +#define FLEXCAN_MB_BRS_SET(brsAddr,var) FLEXCAN_MB_BRS_CLR(brsAddr); FLEXCAN_MB_BRS_ATTACH(brsAddr,var) + +/** Legacy Message Buffer ESI Get */ +#define FLEXCAN_MB_ESI_GET(esiAddr) (((FLEXCAN_REG32_CONTENT(esiAddr))>>29)&0x01U) +/** Legacy Message Buffer ESI Clear */ +#define FLEXCAN_MB_ESI_CLR(esiAddr) (FLEXCAN_REG32_CONTENT(esiAddr) &= FLEXCAN_U32NOTSHIFT(0x01U,29)) +/** Legacy Message Buffer ESI Attach */ +#define FLEXCAN_MB_ESI_ATTACH(esiAddr,var) (FLEXCAN_REG32_CONTENT(esiAddr) |= FLEXCAN_U32SHIFT(var,0x01U,29)) +/** Legacy Message Buffer ESI Set */ +#define FLEXCAN_MB_ESI_SET(esiAddr,var) FLEXCAN_MB_ESI_CLR(esiAddr); FLEXCAN_MB_ESI_ATTACH(esiAddr,var) + +/** Legacy Message Buffer CODE Get */ +#define FLEXCAN_MB_CODE_GET(codeAddr) (((FLEXCAN_REG32_CONTENT(codeAddr))>>24)&0x0FU) +/** Legacy Message Buffer CODE Clear */ +#define FLEXCAN_MB_CODE_CLR(codeAddr) (FLEXCAN_REG32_CONTENT(codeAddr) &= FLEXCAN_U32NOTSHIFT(0x0FU,24)) +/** Legacy Message Buffer CODE Attach */ +#define FLEXCAN_MB_CODE_ATTACH(codeAddr,var) (FLEXCAN_REG32_CONTENT(codeAddr) |= FLEXCAN_U32SHIFT(var,0x0FU,24)) +/** Legacy Message Buffer CODE set */ +#define FLEXCAN_MB_CODE_SET(codeAddr,var) FLEXCAN_MB_CODE_CLR(codeAddr); FLEXCAN_MB_CODE_ATTACH(codeAddr,var) + + +/** Legacy Message Buffer SRR Get */ +#define FLEXCAN_MB_SRR_GET(srrAddr) (((FLEXCAN_REG32_CONTENT(srrAddr)) >>22)&0x01U) +/** Legacy Message Buffer SRR Clear */ +#define FLEXCAN_MB_SRR_CLR(srrAddr) (FLEXCAN_REG32_CONTENT(srrAddr) &= FLEXCAN_U32NOTSHIFT(0x01U,22)) +/** Legacy Message Buffer SRR Attach */ +#define FLEXCAN_MB_SRR_ATTACH(srrAddr,var) (FLEXCAN_REG32_CONTENT(srrAddr) |= FLEXCAN_U32SHIFT(var,0x01U,22)) +/** Legacy Message Buffer SRR set */ +#define FLEXCAN_MB_SRR_SET(srrAddr,var) FLEXCAN_MB_SRR_CLR(srrAddr); FLEXCAN_MB_SRR_ATTACH(srrAddr,var) + +/** Legacy Message Buffer IDE Get */ +#define FLEXCAN_MB_IDE_GET(ideAddr) (((FLEXCAN_REG32_CONTENT(ideAddr))>>21)&0x01U) +/** Legacy Message Buffer IDE Clear */ +#define FLEXCAN_MB_IDE_CLR(ideAddr) (FLEXCAN_REG32_CONTENT(ideAddr) &= FLEXCAN_U32NOTSHIFT(0x01U,21)) +/** Legacy Message Buffer IDE Attach */ +#define FLEXCAN_MB_IDE_ATTACH(ideAddr,var) (FLEXCAN_REG32_CONTENT(ideAddr) |= FLEXCAN_U32SHIFT(var,0x01U,21)) +/** Legacy Message Buffer IDE set */ +#define FLEXCAN_MB_IDE_SET(ideAddr,var) FLEXCAN_MB_IDE_CLR(ideAddr); FLEXCAN_MB_IDE_ATTACH(ideAddr,var) + + +/** Legacy Message Buffer RTR Get */ +#define FLEXCAN_MB_RTR_GET(rtrAddr) (((FLEXCAN_REG32_CONTENT(rtrAddr))>>20)&0x01U) +/** Legacy Message Buffer RTR Clear */ +#define FLEXCAN_MB_RTR_CLR(rtrAddr) (FLEXCAN_REG32_CONTENT(rtrAddr) &= FLEXCAN_U32NOTSHIFT(0x01U,20)) +/** Legacy Message Buffer RTR Attach */ +#define FLEXCAN_MB_RTR_ATTACH(rtrAddr,var) (FLEXCAN_REG32_CONTENT(rtrAddr) |= FLEXCAN_U32SHIFT(var,0x01U,20)) +/** Legacy Message Buffer RTR set */ +#define FLEXCAN_MB_RTR_SET(rtrAddr,var) FLEXCAN_MB_RTR_CLR(rtrAddr); FLEXCAN_MB_RTR_ATTACH(rtrAddr,var) + +/** Legacy Message Buffer DLC Get */ +#define FLEXCAN_MB_DLC_GET(dlcAddr) (((FLEXCAN_REG32_CONTENT(dlcAddr))>>16)&0x0FU) +/** Legacy Message Buffer DLC Clear */ +#define FLEXCAN_MB_DLC_CLR(dlcAddr) (FLEXCAN_REG32_CONTENT(dlcAddr) &= FLEXCAN_U32NOTSHIFT(0x0FU,16)) +/** Legacy Message Buffer DLC Attach */ +#define FLEXCAN_MB_DLC_ATTACH(dlcAddr,var) (FLEXCAN_REG32_CONTENT(dlcAddr) |= FLEXCAN_U32SHIFT(var,0x0FU,16)) +/** Legacy Message Buffer DLC Set */ +#define FLEXCAN_MB_DLC_SET(dlcAddr,var) FLEXCAN_MB_DLC_CLR(dlcAddr); FLEXCAN_MB_DLC_ATTACH(dlcAddr,var) + +/** Legacy Message Buffer TIME STAMP Get */ +#define FLEXCAN_MB_TIMESTAMP_GET(timestampAddr) (FLEXCAN_REG32_CONTENT(timestampAddr)&0xFFFFU) +/** Legacy Message Buffer TIME STAMP Clear */ +#define FLEXCAN_MB_TIMESTAMP_CLR(timestampAddr) (FLEXCAN_REG32_CONTENT(timestampAddr) &= FLEXCAN_U32NOTSHIFT(0xFFFFU,0)) +/** Legacy Message Buffer TIME STAMP Attach */ +#define FLEXCAN_MB_TIMESTAMP_ATTACH(timestampAddr,var) (FLEXCAN_REG32_CONTENT(timestampAddr) |= FLEXCAN_U32SHIFT(var,0xFFFFU,0)) +/** Legacy Message Buffer TIME STAMP Set */ +#define FLEXCAN_MB_TIMESTAMP_SET(timestampAddr,var) FLEXCAN_MB_TIMESTAMP_CLR(timestampAddr); FLEXCAN_MB_TIMESTAMP_ATTACH(timestampAddr,var) + +/** Legacy Message Buffer PRIO Get */ +#define FLEXCAN_MB_PRIO_GET(prioAddr) (((FLEXCAN_REG32_CONTENT(prioAddr))>>29)&0x07U) +/** Legacy Message Buffer PRIO Clear */ +#define FLEXCAN_MB_PRIO_CLR(prioAddr) (FLEXCAN_REG32_CONTENT(prioAddr) &= FLEXCAN_U32NOTSHIFT(0x07U,29)) +/** Legacy Message Buffer PRIO Attach */ +#define FLEXCAN_MB_PRIO_ATTACH(prioAddr,var) (FLEXCAN_REG32_CONTENT(prioAddr) |= FLEXCAN_U32SHIFT(var,0x07U,29)) +/** Legacy Message Buffer PRIO Set */ +#define FLEXCAN_MB_PRIO_SET(prioAddr,var) FLEXCAN_MB_PRIO_CLR(prioAddr); FLEXCAN_MB_PRIO_ATTACH(prioAddr,var) + +/** Legacy Message Buffer STD ID Get */ +#define FLEXCAN_MB_STDID_GET(stdidAddr) (((FLEXCAN_REG32_CONTENT(stdidAddr))>>18)&0x7FFU) +/** Legacy Message Buffer STD ID CLR */ +#define FLEXCAN_MB_STDID_CLR(stdidAddr) (FLEXCAN_REG32_CONTENT(stdidAddr) &= FLEXCAN_U32NOTSHIFT(0x7FFU,18)) +/** Legacy Message Buffer STD ID Attach */ +#define FLEXCAN_MB_STDID_ATTACH(stdidAddr,var) (FLEXCAN_REG32_CONTENT(stdidAddr) |= FLEXCAN_U32SHIFT(var,0x7FFU,18)) +/** Legacy Message Buffer STD ID set */ +#define FLEXCAN_MB_STDID_SET(stdidAddr,var) FLEXCAN_MB_STDID_CLR(stdidAddr); FLEXCAN_MB_STDID_ATTACH(stdidAddr,var) + +/** Legacy Message Buffer EXT ID Get */ +#define FLEXCAN_MB_EXTID_GET(extidAddr) ((FLEXCAN_REG32_CONTENT(extidAddr))&0x1FFFFFFF) +/** Legacy Message Buffer EXT ID Clear */ +#define FLEXCAN_MB_EXTID_CLR(extidAddr) (FLEXCAN_REG32_CONTENT(extidAddr) &= FLEXCAN_U32NOTSHIFT(0x1FFFFFFF,0)) +/** Legacy Message Buffer EXT ID Attach */ +#define FLEXCAN_MB_EXTID_ATTACH(extidAddr,var) (FLEXCAN_REG32_CONTENT(extidAddr) |= FLEXCAN_U32SHIFT(var,0x1FFFFFFF,0)) +/** Legacy Message Buffer EXT ID set */ +#define FLEXCAN_MB_EXTID_SET(extidAddr,var) FLEXCAN_MB_EXTID_CLR(extidAddr); FLEXCAN_MB_EXTID_ATTACH(extidAddr,var) + +/* enhanced fifo message buffer */ + +/** Enhanced FIFO Message Buffer EDL Get */ +#define FLEXCAN_EFIFOMB_EDL_GET() ((pCan->ERX_FIFO[0U]>>31)&0x01U) + +/** Enhanced FIFO Message Buffer BRS Get */ +#define FLEXCAN_EFIFOMB_BRS_GET() ((pCan->ERX_FIFO[0U]>>30)&0x01U) + +/** Enhanced FIFO Message Buffer ESI Get */ +#define FLEXCAN_EFIFOMB_ESI_GET() ((pCan->ERX_FIFO[0U]>>29)&0x01U) + +/** Enhanced FIFO Message Buffer SRR Get */ +#define FLEXCAN_EFIFOMB_SRR_GET() ((pCan->ERX_FIFO[0U] >>22)&0x01U) + +/** Enhanced FIFO Message Buffer IDE Get */ +#define FLEXCAN_EFIFOMB_IDE_GET() ((pCan->ERX_FIFO[0U]>>21)&0x01U) + +/** Enhanced FIFO Message Buffer RTR Get */ +#define FLEXCAN_EFIFOMB_RTR_GET() ((pCan->ERX_FIFO[0U]>>20)&0x01U) + +/** Enhanced FIFO Message Buffer DLC Get */ +#define FLEXCAN_EFIFOMB_DLC_GET() ((pCan->ERX_FIFO[0U]>>16)&0x0FU) + +/** Enhanced FIFO Message Buffer TIME STAMP Get */ +#define FLEXCAN_EFIFOMB_TIMESTAMP_GET() (pCan->ERX_FIFO[0U]&0xFFU) + +/** Enhanced FIFO Message Buffer STD ID Get */ +#define FLEXCAN_EFIFOMB_STDID_GET() ((pCan->ERX_FIFO[1U]>>18)&0x7FFU) + +/** Enhanced FIFO Message Buffer EXT ID Get */ +#define FLEXCAN_EFIFOMB_EXTID_GET() (pCan->ERX_FIFO[1U]&0x1FFFFFFF) + +/** Enhanced FIFO Message Buffer Data Get */ +#define FLEXCAN_EFIFOMB_DATAADDR_GET(wordIndex) (&(pCan->ERX_FIFO[2U+(wordIndex)])) + +/** Enhanced FIFO Message Buffer IDHIT Get */ +#define FLEXCAN_EFIFOMB_IDHIT_GET(dataWordLen) ((pCan->ERX_FIFO[2U+(dataWordLen)])&0x1FFU) + +/** Enhanced FIFO Message Buffer HR Time Stamp Get */ +#define FLEXCAN_EFIFOMB_HRTIMESTAMP_GET(dataWordLen) (pCan->ERX_FIFO[3U+(dataWordLen)]) + +/* enhanced fifo message buffer from user buffer*/ + +/** Enhanced FIFO Message Buffer EDL Get */ +#define FLEXCAN_EFIFOMB_EDL_GET_FROM_BUFFER(Addr) ((((uint32_t*)Addr)[0U]>>31)&0x01U) + +/** Enhanced FIFO Message Buffer BRS Get */ +#define FLEXCAN_EFIFOMB_BRS_GET_FROM_BUFFER(Addr) ((((uint32_t*)Addr)[0U]>>30)&0x01U) + +/** Enhanced FIFO Message Buffer ESI Get */ +#define FLEXCAN_EFIFOMB_ESI_GET_FROM_BUFFER(Addr) ((((uint32_t*)Addr)[0U]>>29)&0x01U) + +/** Enhanced FIFO Message Buffer SRR Get */ +#define FLEXCAN_EFIFOMB_SRR_GET_FROM_BUFFER(Addr) ((((uint32_t*)Addr)[0U] >>22)&0x01U) + +/** Enhanced FIFO Message Buffer IDE Get */ +#define FLEXCAN_EFIFOMB_IDE_GET_FROM_BUFFER(Addr) ((((uint32_t*)Addr)[0U]>>21)&0x01U) + +/** Enhanced FIFO Message Buffer RTR Get */ +#define FLEXCAN_EFIFOMB_RTR_GET_FROM_BUFFER(Addr) ((((uint32_t*)Addr)[0U]>>20)&0x01U) + +/** Enhanced FIFO Message Buffer DLC Get */ +#define FLEXCAN_EFIFOMB_DLC_GET_FROM_BUFFER(Addr) ((((uint32_t*)Addr)[0U]>>16)&0x0FU) + +/** Enhanced FIFO Message Buffer TIME STAMP Get */ +#define FLEXCAN_EFIFOMB_TIMESTAMP_GET_FROM_BUFFER(Addr) (((uint32_t*)Addr)[0U]&0xFFU) + +/** Enhanced FIFO Message Buffer STD ID Get */ +#define FLEXCAN_EFIFOMB_STDID_GET_FROM_BUFFER(Addr) ((((uint32_t*)Addr)[1U]>>18)&0x7FFU) + +/** Enhanced FIFO Message Buffer EXT ID Get */ +#define FLEXCAN_EFIFOMB_EXTID_GET_FROM_BUFFER(Addr) (((uint32_t*)Addr)[1U]&0x1FFFFFFF) + +/** Enhanced FIFO Message Buffer Data Get */ +#define FLEXCAN_EFIFOMB_DATAADDR_GET_FROM_BUFFER(Addr, wordIndex) (&(((uint32_t*)Addr)[2U+(wordIndex)])) + +/** Enhanced FIFO Message Buffer IDHIT Get */ +#define FLEXCAN_EFIFOMB_IDHIT_GET_FROM_BUFFER(Addr, dataWordLen) ((((uint32_t*)Addr)[2U+(dataWordLen)])&0x1FFU) + +/** Enhanced FIFO Message Buffer HR Time Stamp Get */ +#define FLEXCAN_EFIFOMB_HRTIMESTAMP_GET_FROM_BUFFER(Addr, dataWordLen) (((uint32_t*)Addr)[3U+(dataWordLen)]) + +/* ################################################################################## */ +/* ################################### Type define ################################## */ + +/** + * \brief FLEXCAN Clock Source Select Enumeration + * + */ +typedef enum +{ + FLEXCAN_CLOCK_FUNCTION = 0x00U,/**< FLEXCAN_CLOCK_FUNCTION clock from asynchronous clock */ + FLEXCAN_CLOCK_MODULE = 0x01U /**< FLEXCAN_CLOCK_MODULE clock from peripheral clock */ +} FLEXCAN_ClockSrcType; + + + +/* ################################################################################## */ +/* ################################## Local Inline ################################## */ + + + +/** + * \brief Set Module Disable + * + * \param pCan FLEXCAN instance value + * \param bDisable set whether disable + */ +LOCAL_INLINE void FLEXCAN_HWA_SetMcrDisable(FLEXCAN_Type *const pCan, uint8_t bDisable) +{ + if (bDisable == TRUE) + { + pCan->MCR |= FLEXCAN_MCR_MDIS_MASK; /* bitMDIS=1: Disable module before selecting clock */ + } + else + { + pCan->MCR &= ~FLEXCAN_MCR_MDIS_MASK; + } +} + +/** + * \brief Set Module Freeze + * + * \param pCan FLEXCAN instance value + * \param bFreeze set whether freeze + */ +LOCAL_INLINE void FLEXCAN_HWA_SetMcrFreeze(FLEXCAN_Type *const pCan, uint8_t bFreeze) +{ + if (bFreeze == TRUE) + { + pCan->MCR |= FLEXCAN_MCR_FRZ_MASK; /* bitMDIS=1: Disable module before selecting clock */ + } + else + { + pCan->MCR &= ~FLEXCAN_MCR_FRZ_MASK; + } +} + + +/** + * \brief Set Module Halt and Freeze + * + * \param pCan FLEXCAN instance value + * \param bFreeze set whether freeze + */ +LOCAL_INLINE void FLEXCAN_HWA_SetHaltFreeze(FLEXCAN_Type *const pCan) +{ + pCan->MCR |= FLEXCAN_MCR_FRZ_MASK | FLEXCAN_MCR_HALT_MASK; +} + +/** + * \brief Wait FLEXCAN Module Enter Freezen mode + * + * \param pCan FLEXCAN instance value + * \param u32TimeoutTick Timeout tick + * \return 0U is really in freezen mode + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_WaitMcrFreezen(FLEXCAN_Type *const pCan, uint32_t u32TimeoutTick) +{ + /* wait for bitFRZACK=1 on freeze mode entry/exit */ + while ( (!((pCan->MCR & FLEXCAN_MCR_FRZACK_MASK) >> FLEXCAN_MCR_FRZACK_SHIFT)) && (u32TimeoutTick-->0U) ) + { + + } + + return (u32TimeoutTick==0U); +} + +/** + * \brief Wait FLEXCAN Module Exit Freezen mode + * + * \param pCan FLEXCAN instance value + * \param u32TimeoutTick Timeout tick + * \return 1U is really in freezen mode + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_WaitMcrExitFreezen(FLEXCAN_Type *const pCan, uint32_t u32TimeoutTick) +{ + while ( ((pCan->MCR & FLEXCAN_MCR_FRZACK_MASK) >> FLEXCAN_MCR_FRZACK_SHIFT) && (u32TimeoutTick-->0U) ) + {} + /* wait for bitFRZACK to clear (not in freeze mode) */ + + return (u32TimeoutTick==0U); +} + +/** + * \brief Wait FLEXCAN Module Ready + * + * \param pCan FLEXCAN instance value + * \param u32TimeoutTick Timeout tick + * \return 1U is really ready + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_WaitMcrReady(FLEXCAN_Type *const pCan, uint32_t u32TimeoutTick) +{ + while ( ((pCan->MCR & FLEXCAN_MCR_NOTRDY_MASK) >> FLEXCAN_MCR_NOTRDY_SHIFT) && (u32TimeoutTick-->0U) ) + {} + /* wait for bitNOTRDY to clear (module ready) */ + + return (u32TimeoutTick==0U); +} + +/** + * \brief Wait FLEXCAN Module Not Ready + * + * \param pCan FLEXCAN instance value + * \param u32TimeoutTick Timeout tick + * \return 1U is really not ready + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_WaitMcrNoReady(FLEXCAN_Type *const pCan, uint32_t u32TimeoutTick) +{ + while ( (!((pCan->MCR & FLEXCAN_MCR_NOTRDY_MASK) >> FLEXCAN_MCR_NOTRDY_SHIFT)) && (u32TimeoutTick-->0U) ) + {} + /* wait for bitNOTRDY to set (module ready) */ + + return (u32TimeoutTick==0U); +} + +/** + * \brief Set FLEXCAN MCR value + * + * \param pCan FLEXCAN instance value + * \param u32Value write value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetMCR(FLEXCAN_Type *const pCan, uint32_t u32Value) +{ + pCan->MCR = u32Value; +} + +/** + * \brief Get FLEXCAN MCR value + * + * \param pCan FLEXCAN instance value + * \return MCR value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_GetMCR(FLEXCAN_Type *const pCan) +{ + return (uint32_t)pCan->MCR; +} + +/** + * \brief Attach FLEXCAN MCR value + * + * \param pCan FLEXCAN instance value + * \param u32Value attached value + */ +LOCAL_INLINE void FLEXCAN_HWA_AttachMCR(FLEXCAN_Type *const pCan, uint32_t u32Value) +{ + pCan->MCR |= u32Value; +} + + +/** + * \brief Set FLEXCAN baudrate clock source + * + * \param pCan FLEXCAN instance value + * \param tBaudClk Baudrate clock source + */ +LOCAL_INLINE void FLEXCAN_HWA_SetCtrl1BaudSrc(FLEXCAN_Type *const pCan, FLEXCAN_ClockSrcType tBaudClk) +{ + if (tBaudClk == FLEXCAN_CLOCK_MODULE) + { + pCan->CTRL1 |= FLEXCAN_CTRL1_CLKSRC_MASK; + } + else + { + pCan->CTRL1 &= ~FLEXCAN_CTRL1_CLKSRC_MASK; + } +} + +/** + * \brief Set FLEXCAN ctrl1 value + * + * \param pCan FLEXCAN instance value + * \param u32Value write value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetCtrl1(FLEXCAN_Type *const pCan, uint32_t u32Value) +{ + pCan->CTRL1 = u32Value; +} + +/** + * \brief Attach FLEXCAN ctrl1 value + * + * \param pCan FLEXCAN instance value + * \param u32Value attached value + */ +LOCAL_INLINE void FLEXCAN_HWA_AttachCtrl1(FLEXCAN_Type *const pCan, uint32_t u32Value) +{ + pCan->CTRL1 |= u32Value; +} + + +/** + * \brief Get IFLAG1 Flag + * + * \param pCan FLEXCAN instance value + * \return flag1 value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_GetFlag1(FLEXCAN_Type *const pCan) +{ + return pCan->IFLAG1; +} + + +/** + * \brief Clear IFLAG1 Flag + * + * \param pCan FLEXCAN instance value + * \param u32W1cFlag write clear value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetFlag1(FLEXCAN_Type *const pCan, uint32_t u32W1cFlag) +{ + pCan->IFLAG1 = u32W1cFlag; +} + +/** + * \brief Clear Rx Flag and unlock MB + * + * \param pCan FLEXCAN instance value + * \param u32MbIndex Message Buffer Index + */ +LOCAL_INLINE void FLEXCAN_HWA_UnlockMbNoFifoFlag(FLEXCAN_Type *const pCan, uint32_t u32MbIndex) +{ + (void)pCan->TIMER; /* Read TIMER to unlock message buffers */ + pCan->IFLAG1 = 1U << u32MbIndex; +} + +/** + * \brief Clear MB Flag + * + * \param pCan FLEXCAN instance value + * \param u32MbIndex Message Buffer Index + */ +LOCAL_INLINE void FLEXCAN_HWA_W1cFlag1NoFifoFlag(FLEXCAN_Type *const pCan, uint32_t u32MbIndex) +{ + pCan->IFLAG1 = 1U << u32MbIndex; +} + +/** + * \brief Get MB Flag + * + * \param pCan FLEXCAN instance value + * \param u32MbIndex Message Buffer Index + * \return flag value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_GetFlag1NoFifoFlag(FLEXCAN_Type *const pCan, uint32_t u32MbIndex) +{ + return (pCan->IFLAG1 >> u32MbIndex) & 0x01U; +} + +/** + * \brief Get Legacy Fifo Rx Flag + * + * \param pCan FLEXCAN instance value + * \return flag fifo value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_GetIFLAG1FifoFlag(FLEXCAN_Type *const pCan) +{ + /* IFLAG1[BIT5] (Frames available in Rx FIFO) is asserted when there is at least one frame available to be read from the FIFO. */ + return (pCan->IFLAG1 >> 5) & 0x01U; +} + +/** + * \brief Clear Legacy Fifo Rx Flag + * + * \param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_ClearIFLAG1FifoFlag(FLEXCAN_Type *const pCan) +{ + /* Read TIMER to unlock message buffers */ + (void)pCan->TIMER; + + pCan->IFLAG1 = 1U << 5; +} + +/** + * \brief Set special message buffer interrupt + * + * \param pCan FLEXCAN instance value + * \param u32Mask Message Buffer interrupt mask value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetMaskMbInterrupt(FLEXCAN_Type *const pCan, uint32_t u32Mask) +{ + pCan->IMASK1 = u32Mask; +} + +/** + * \brief Attach special message buffer interrupt + * + * \param pCan FLEXCAN instance value + * \param u32MbIndex Message Buffer index + */ +LOCAL_INLINE void FLEXCAN_HWA_AttachMaskMbInterrupt(FLEXCAN_Type *const pCan, uint32_t u32Mask) +{ + pCan->IMASK1 |= u32Mask; +} + +/** + * \brief Attach special message buffer interrupt + * + * \param pCan FLEXCAN instance value + * \param u32MbIndex Message Buffer index + */ +LOCAL_INLINE void FLEXCAN_HWA_AttachMbIndexInterrupt(FLEXCAN_Type *const pCan, uint32_t u32MbIndex) +{ + pCan->IMASK1 |= 1U << u32MbIndex; +} + +/** + * \brief Set Legacy Fifo Rx interrupt + * + * \param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetMaskFifoInterrupt(FLEXCAN_Type *const pCan) +{ + pCan->IMASK1 = 1U << 5U; +} + +/** + * \brief Set CTRL2 value + * + * \param pCan FLEXCAN instance value + * \param u32Value write value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetCtrl2(FLEXCAN_Type *const pCan, uint32_t u32Value) +{ + pCan->CTRL2 = u32Value; +} + +/** + * \brief Attach FLEXCAN ctrl2 value + * + * \param pCan FLEXCAN instance value + * \param u32Value attached value + */ +LOCAL_INLINE void FLEXCAN_HWA_AttachCtrl2(FLEXCAN_Type *const pCan, uint32_t u32Value) +{ + pCan->CTRL2 |= u32Value; +} + +/** + * \brief Set CBT value + * + * \param pCan FLEXCAN instance value + * \param u32Value write value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetCBT(FLEXCAN_Type *const pCan, uint32_t u32Value) +{ + pCan->CBT = u32Value; +} + +/** + * \brief Set FDCBT value + * + * \param pCan FLEXCAN instance value + * \param u32Value write value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetFDCBT(FLEXCAN_Type *const pCan, uint32_t u32Value) +{ + pCan->FDCBT = u32Value; +} + +/** + * \brief Set FDCTRL value + * + * \param pCan FLEXCAN instance value + * \param u32Value write value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetFDCTRL(FLEXCAN_Type *const pCan, uint32_t u32Value) +{ + pCan->FDCTRL = u32Value; +} + + +/** + * \brief This Function is used to get FLEXCAN rx timestamp + * + * \param pCan is FLEXCAN instance value + * \return timestamp Register Value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_GetTimeStamp(FLEXCAN_Type *const pCan) +{ + return pCan->TIMER; +} + +/** + * \brief This Function is used to get FLEXCAN error + * + * \param pCan is FLEXCAN instance value + * \return ESR1 Register Value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_GetErrorInfo(FLEXCAN_Type *const pCan) +{ + return pCan->ESR1; +} + +/** + * \brief This Function is used to get FLEXCAN error with interrupt + * + * \param pCan is FLEXCAN instance value + * \return ESR1 Register Value with interrupt mask + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_GetErrorIntInfo(FLEXCAN_Type *const pCan) +{ + uint32_t u32IntMask = 0U; + + u32IntMask = ((0U == (pCan->CTRL1 & FLEXCAN_CTRL1_ERRMSK_MASK))?0U:FLEXCAN_ESR1_ERRINT_MASK); + u32IntMask |= ((0U == (pCan->CTRL1 & FLEXCAN_CTRL1_BOFFMSK_MASK))?0U:FLEXCAN_ESR1_BOFFINT_MASK); + u32IntMask |= ((0U == (pCan->CTRL2 & FLEXCAN_CTRL2_ERRMSK_FAST_MASK))?0U:FLEXCAN_ESR1_ERRINT_FAST_MASK); + u32IntMask |= ((0U == (pCan->CTRL2 & FLEXCAN_CTRL2_BOFFDONEMSK_MASK))?0U:FLEXCAN_ESR1_BOFFDONEINT_MASK); + + return (pCan->ESR1 & u32IntMask); +} + +/** + * \brief Clear Error Info + * + * \param pCan FLEXCAN instance value + * \param u32ErrorEsr1 is read from FLEXCAN_GetErrorInfo + */ +LOCAL_INLINE void FLEXCAN_HWA_ClrErrorInfo(FLEXCAN_Type *const pCan, uint32_t u32ErrorEsr1) +{ + pCan->ESR1 = u32ErrorEsr1; +} + +/** + * \brief This Function is used to get FLEXCAN error count + * + * \param pCan is FLEXCAN instance value + * \return ECR Register Value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_GetErrorCount(FLEXCAN_Type *const pCan) +{ + return pCan->ECR; +} + +/** + * \brief Enable FLEXCAN Legacy Fifo + * + * \param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_EnableLegacyFifo(FLEXCAN_Type *const pCan) +{ + /* if enable legacy fifo, FD fifo must be disabled */ + pCan->MCR |= FLEXCAN_MCR_RFEN_MASK; /* set legacy fifo */ +} + +/** + * \brief Disable FLEXCAN Legacy Fifo + * + * \param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_DisableLegacyFifo(FLEXCAN_Type *const pCan) +{ + /* if enable legacy fifo, FD fifo must be disabled */ + pCan->MCR &= ~FLEXCAN_MCR_RFEN_MASK; /* clear legacy fifo */ +} + +/** + * \brief Enable FLEXCAN FD Fifo + * + * \param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_EnableFDFifo(FLEXCAN_Type *const pCan) +{ + /* if enable fd fifo, legacy fifo must be disabled */ + pCan->ERFCR |= FLEXCAN_ERFCR_ERFEN_MASK; /* set enhanced fifo */ +} + +/** + * \brief Disable FLEXCAN FD Fifo + * + * \param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_DisableFDFifo(FLEXCAN_Type *const pCan) +{ + /* if enable fd fifo, legacy fifo must be disabled */ + pCan->ERFCR &= ~FLEXCAN_ERFCR_ERFEN_MASK; /* clear enhanced fifo */ +} + + + +/** + * \brief Check FLEXCAN legacy fifo if enabled + * + * \param pCan FLEXCAN instance value + * \return 1 is legacy fifo enabled, 0 is disabled + */ +LOCAL_INLINE uint8_t FLEXCAN_HWA_CheckLegacyFifoEnabled(FLEXCAN_Type *const pCan) +{ + uint8_t u8RetVal; + uint32_t u32Value; + + /* get legacy fifo */ + u32Value = (pCan->MCR & FLEXCAN_MCR_RFEN_MASK) >> FLEXCAN_MCR_RFEN_SHIFT; + + u8RetVal = u32Value == 0U ? (uint8_t)0x0U : (uint8_t)0x1U; + + return u8RetVal; +} + +/** + * \brief Check FLEXCAN FD fifo if enabled + * + * \param pCan FLEXCAN instance value + * \return 1 is legacy fifo enabled, 0 is disabled + */ +LOCAL_INLINE uint8_t FLEXCAN_HWA_CheckFdFifoEnabled(FLEXCAN_Type *const pCan) +{ + uint8_t u8RetVal; + uint32_t u32Value; + /* get enhanced fifo */ + u32Value = (pCan->ERFCR & FLEXCAN_ERFCR_ERFEN_MASK) >> FLEXCAN_ERFCR_ERFEN_SHIFT; + + u8RetVal = u32Value == 0U ? (uint8_t)0x0U : (uint8_t)0x1U; + + return u8RetVal; +} + +/** + * \brief Set legacy fifo filter number number + * + * \param pCan FLEXCAN instance value + * \param u32FilterNum is total filter number + */ +LOCAL_INLINE void FLEXCAN_HWA_SetLegacyFifoFilterNum(FLEXCAN_Type *const pCan, uint32_t u32FilterNum) +{ + pCan->CTRL2 &= ~FLEXCAN_CTRL2_RFFN_MASK; /* clear fifo filter number */ + pCan->CTRL2 |= ((u32FilterNum - 1U) << FLEXCAN_CTRL2_RFFN_SHIFT)&FLEXCAN_CTRL2_RFFN_MASK; +} + + +/** + * \brief Check FLEXCAN FD enable + * + * \param pCan FLEXCAN instance value + * \return 1 is fd enabled, 0 is disabled + */ +LOCAL_INLINE uint8_t FLEXCAN_HWA_CheckFd(FLEXCAN_Type *const pCan) +{ + uint8_t u8RetVal; + uint32_t u32Value; + + /* get fd enable */ + u32Value = (pCan->MCR & FLEXCAN_MCR_FDEN_MASK) >> FLEXCAN_MCR_FDEN_SHIFT; + + u8RetVal = u32Value == 0U ? (uint8_t)0x0U : (uint8_t)0x1U; + + return u8RetVal; +} + + +/** + * \brief Set RXIMR for FLEXCAN + * + * \param pCan FLEXCAN instance value + * \param u32MbIndex Message Buffer Index + * \param u32Mask ID Mask + */ +LOCAL_INLINE void FLEXCAN_HWA_SetIndividualMask(FLEXCAN_Type *const pCan, uint32_t u32MbIndex, uint32_t u32Mask) +{ + pCan->RXIMR[u32MbIndex] = u32Mask; +} + +/** + * \brief Set global mask value + * + * \param pCan FLEXCAN instance value + * \param u32Mask mask value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetGlobalMask(FLEXCAN_Type *const pCan, uint32_t u32Mask) +{ + pCan->RXMGMASK = u32Mask; +} + +/** + * \brief Set rx14 mask value + * + * \param pCan FLEXCAN instance value + * \param u32Mask mask value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetRx14Mask(FLEXCAN_Type *const pCan, uint32_t u32Mask) +{ + pCan->RX14MASK = u32Mask; +} + +/** + * \brief Set rx15 mask value + * + * \param pCan FLEXCAN instance value + * \param u32Mask mask value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetRx15Mask(FLEXCAN_Type *const pCan, uint32_t u32Mask) +{ + pCan->RX15MASK = u32Mask; +} + +/** + * \brief Set value to FLEXCAN RAM + * + * \param pCan FLEXCAN instance value + * \param u32RamIndex RAM index for FLEXCAN + * \param u32Value written value + */ +LOCAL_INLINE void FLEXCAN_HWA_MbRam(FLEXCAN_Type *const pCan, uint32_t u32RamIndex, uint32_t u32Value) +{ + pCan->RAM[u32RamIndex] = u32Value; +} + + +/** + * \brief Set ERFCR value + * + * \param pCan FLEXCAN instance value + * \param u32Value written value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetERFCR(FLEXCAN_Type *const pCan, uint32_t u32Value) +{ + pCan->ERFCR = u32Value; +} + +/** + * \brief Reset Enhanced FIFO Engine + * + * \param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_ERFSRResetEnhancedFifo(FLEXCAN_Type *const pCan) +{ + /* Write one to ERFSR[ERFCLR] to reset Enhanced Rx FIFO engine */ + pCan->ERFSR |= FLEXCAN_ERFSR_ERFCLR_MASK; +} + + +/** + * \brief Clear Enhanced Fifo Flag with mask + * + * \param pCan FLEXCAN instance value + * \param u32Shift flag shift + * \param u32Mask flag mask + * \return flag value + */ +LOCAL_INLINE uint32_t FLEXCAN_HWA_ERFSRGetEnhancedFifoFlag(FLEXCAN_Type *const pCan, uint32_t u32Shift, uint32_t u32Mask) +{ + /* Write one clear status */ + return ((pCan->ERFSR & u32Mask) >> u32Shift); +} + +/** + * \brief Clear Enhanced Fifo status + * + * \param pCan FLEXCAN instance value + * \param u32ClearMask clear mask value + */ +LOCAL_INLINE void FLEXCAN_HWA_ERFSRClearEnhancedFifoFlag(FLEXCAN_Type *const pCan, uint32_t u32ClearMask) +{ + /* Write one clear status */ + pCan->ERFSR |= u32ClearMask; +} + + + +/** + * \brief Set Enhance Fifo interrupt value + * + * \param pCan FLEXCAN instance value + */ +LOCAL_INLINE void FLEXCAN_HWA_SetERFIERDataInterrupt(FLEXCAN_Type *const pCan) +{ + pCan->ERFIER |= FLEXCAN_ERFIER_ERFDAIE_MASK; +} + +/** + * \brief Set Enhanced Fifo filter value + * + * \param pCan FLEXCAN instance value + * \param u32FilterIndex Filter index + * \param u32Value filter value + */ +LOCAL_INLINE void FLEXCAN_HWA_EnhancedFifoFilter(FLEXCAN_Type *const pCan, uint32_t u32FilterIndex, uint32_t u32Value) +{ + pCan->ERFFEL[u32FilterIndex] = u32Value; +} + +/** @}*/ + +#endif diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_fmc.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_fmc.h new file mode 100644 index 0000000..bd9b913 --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_fmc.h @@ -0,0 +1,402 @@ +/** + * @file HwA_cpm.h + * @author Flagchip + * @brief FC7xxx FMC register API + * @version 0.1.0 + * @date 2024-1-5 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-1-5 Flagchip120 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef HWA_INCLUDE_HWA_FMC_H_ +#define HWA_INCLUDE_HWA_FMC_H_ +#include "device_header.h" +/* ################################################################################## */ +/* ####################################### Macro #################################### */ + + + +/** + * @brief Read the FMC FAPC0 register value for all. + * + * @param pFMC FMC instance. + * @return FMC FAPC0 regsiter value. + */ +LOCAL_INLINE uint32_t FMC_HWA_GetFAPC0Value(FMC_Type *pFMC) +{ + return pFMC->FAPC0; +} + +/** + * @brief Set FMC FAPC0 value, users should write the whole value to this register. + * + * @param pFMC FMC instance. + * @param u32Value the value which will be written to the FAPC0 register. + */ +LOCAL_INLINE void FMC_HWA_SetFAPC0Value(FMC_Type *pFMC, uint32_t u32Value) +{ + pFMC->FAPC0 = u32Value; +} + +/** + * @brief Set FAPC0 data bus prefetch enable + * + * @param bEnable 0:Data prefetching is disabled. 1:Data prefetching is enabled. + */ +LOCAL_INLINE void FMC_HWA_SetFAPC0DataPrefechEnable(FMC_Type *pFMC, bool bEnable) +{ + pFMC->FAPC0 = ((pFMC->FAPC0 & (~FMC_FAPC0_DBPEN_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FAPC0_DBPEN_SHIFT)); +} + +/** + * @brief Set FAPC0 code bus prefetch enable + * + * @param bEnable 0:Code prefetching is disabled. 1:Code prefetching is disabled. + */ +LOCAL_INLINE void FMC_HWA_SetFAPC0CodePrefechEnable(FMC_Type *pFMC, bool bEnable) +{ + pFMC->FAPC0 = ((pFMC->FAPC0 & (~FMC_FAPC0_CBPEN_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FAPC0_CBPEN_SHIFT)); +} + +/** + * @brief Set FAPC0 data bus read buffers enable + * + * @param bEnable 0:Read data buffers are disabled. 1:Read data buffers are enabled. + */ +LOCAL_INLINE void FMC_HWA_SetFAPC0DataBuffersEnable(FMC_Type *pFMC, bool bEnable) +{ + pFMC->FAPC0 = ((pFMC->FAPC0 & (~FMC_FAPC0_DBBEN_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FAPC0_DBBEN_SHIFT)); +} + +/** + * @brief Set FAPC0 code bus read buffers enable + * + * @param bEnable 0:Read code buffers are disabled. 1:Read code buffers are enabled. + */ +LOCAL_INLINE void FMC_HWA_SetFAPC0CodeBuffersEnable(FMC_Type *pFMC, bool bEnable) +{ + pFMC->FAPC0 = ((pFMC->FAPC0 & (~FMC_FAPC0_CBBEN_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FAPC0_CBBEN_SHIFT)); +} + +/** + * @brief Set FAPC1 data bus prefetch enable + * + * @param bEnable 0:Data prefetching is disabled. 1:Data prefetching is enabled. + */ +LOCAL_INLINE void FMC_HWA_SetFAPC1DataPrefechEnable(FMC_Type *pFMC, bool bEnable) +{ + pFMC->FAPC1 = ((pFMC->FAPC1 & (~FMC_FAPC1_DBPEN_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FAPC1_DBPEN_SHIFT)); +} + +/** + * @brief Set FAPC1 code bus prefetch enable + * + * @param bEnable 0:Code prefetching is disabled. 1:Code prefetching is disabled. + */ +LOCAL_INLINE void FMC_HWA_SetFAPC1CodePrefechEnable(FMC_Type *pFMC, bool bEnable) +{ + pFMC->FAPC1 = ((pFMC->FAPC1 & (~FMC_FAPC1_CBPEN_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FAPC1_CBPEN_SHIFT)); +} + +/** + * @brief Set FAPC1 data bus read buffers enable + * + * @param bEnable 0:Read data buffers are disabled. 1:Read data buffers are enabled. + */ +LOCAL_INLINE void FMC_HWA_SetFAPC1DataBuffersEnable(FMC_Type *pFMC, bool bEnable) +{ + pFMC->FAPC1 = ((pFMC->FAPC1 & (~FMC_FAPC1_DBBEN_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FAPC1_DBBEN_SHIFT)); +} + +/** + * @brief Set FAPC1 code bus read buffers enable + * + * @param bEnable 0:Read code buffers are disabled. 1:Read code buffers are enabled. + */ +LOCAL_INLINE void FMC_HWA_SetFAPC1CodeBuffersEnable(FMC_Type *pFMC, bool bEnable) +{ + pFMC->FAPC1 = ((pFMC->FAPC1 & (~FMC_FAPC1_CBBEN_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FAPC1_CBBEN_SHIFT)); +} + +/** + * @brief Set FAPC2 data bus prefetch enable + * + * @param bEnable 0:Data prefetching is disabled. 1:Data prefetching is enabled. + */ +LOCAL_INLINE void FMC_HWA_SetFAPC2DataPrefechEnable(FMC_Type *pFMC, bool bEnable) +{ + pFMC->FAPC2 = ((pFMC->FAPC2 & (~FMC_FAPC2_DBPEN_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FAPC2_DBPEN_SHIFT)); +} + +/** + * @brief Set FAPC2 code bus prefetch enable + * + * @param bEnable 0:Code prefetching is disabled. 1:Code prefetching is disabled. + */ +LOCAL_INLINE void FMC_HWA_SetFAPC2CodePrefechEnable(FMC_Type *pFMC, bool bEnable) +{ + pFMC->FAPC2 = ((pFMC->FAPC2 & (~FMC_FAPC2_CBPEN_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FAPC2_CBPEN_SHIFT)); +} + +/** + * @brief Set FAPC2 data bus read buffers enable + * + * @param bEnable 0:Read data buffers are disabled. 1:Read data buffers are enabled. + */ +LOCAL_INLINE void FMC_HWA_SetFAPC2DataBuffersEnable(FMC_Type *pFMC, bool bEnable) +{ + pFMC->FAPC2 = ((pFMC->FAPC2 & (~FMC_FAPC2_DBBEN_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FAPC2_DBBEN_SHIFT)); +} + +/** + * @brief Set FAPC2 code bus read buffers enable + * + * @param bEnable 0:Read code buffers are disabled. 1:Read code buffers are enabled. + */ +LOCAL_INLINE void FMC_HWA_SetFAPC2CodeBuffersEnable(FMC_Type *pFMC, bool bEnable) +{ + pFMC->FAPC2 = ((pFMC->FAPC2 & (~FMC_FAPC2_CBBEN_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FAPC2_CBBEN_SHIFT)); +} + +/** + * @brief Read the FMC FEEC register value for all. + * + * @param pFMC FMC instance. + * @return FMC FEEC regsiter value. + */ +LOCAL_INLINE uint32_t FMC_HWA_GetFEECValue(FMC_Type *pFMC) +{ + return pFMC->FEEC; +} + +/** + * @brief Set FMC FEEC value, users should write the whole value to this register. + * + * @param pFMC FMC instance. + * @param u32Value the value which will be written to the FEEC register. + */ +LOCAL_INLINE void FMC_HWA_SetFEECValue(FMC_Type *pFMC, uint32_t u32Value) +{ + pFMC->FEEC = u32Value; +} + +/** + * @brief Read the FMC FEIPC register value for all. + * + * @param pFMC FMC instance. + * @return FMC FEIPC regsiter value. + */ +LOCAL_INLINE uint32_t FMC_HWA_GetFEIPCValue(FMC_Type *pFMC) +{ + return pFMC->FEIPC; +} + +/** + * @brief Set the date error position 1 & position 2 + * + * @param pFMC FMC instance. + * @param u32Position1 Data error position 1 + * @param u32Position2 Data error position 2 + */ +LOCAL_INLINE void FMC_HWA_SetInjectPositon(FMC_Type *pFMC, uint32_t u32Position1, uint32_t u32Position2) +{ + pFMC->FEIPC = (pFMC->FEIPC & ~FMC_FEIPC_EDATA_POS1_MASK) | FMC_FEIPC_EDATA_POS1(u32Position1); + pFMC->FEIPC = (pFMC->FEIPC & ~FMC_FEIPC_EDATA_POS2_MASK) | FMC_FEIPC_EDATA_POS2(u32Position2); +} + +/** + * @brief Read the FMC FPESA_L register value for all. + * + * @param pFMC FMC instance. + * @return FMC FPESA_L regsiter value. + */ +LOCAL_INLINE uint32_t FMC_HWA_GetFPESALValue(FMC_Type *pFMC) +{ + return pFMC->FPESA_L; +} + +/** + * @brief Set FMC FPESA_L value. + * + * @param pFMC FMC instance. + * @param u32Value the value which will be written to the FPESA_L register. + */ +LOCAL_INLINE void FMC_HWA_SetFPESALValue(FMC_Type *pFMC, uint32_t u32Value) +{ + pFMC->FPESA_L = u32Value; +} + +/** + * @brief Read the FMC FPESA_P register value for all. + * + * @param pFMC FMC instance. + * @return FMC FPESA_P regsiter value. + */ +LOCAL_INLINE uint32_t FMC_HWA_GetFPESAPValue(FMC_Type *pFMC) +{ + return pFMC->FPESA_P; +} + +/** + * @brief Read the FMC FB_FPELCK register value for all. + * + * @param pFMC FMC instance. + * @param u8SeqGroupIndex the index of the sequence group + * @return FMC FB_FPELCK regsiter value. + */ +LOCAL_INLINE uint32_t FMC_HWA_GetFBFPELCKValue(FMC_Type *pFMC, uint8_t u8SeqGroupIndex) +{ + return pFMC->FB_FPELCK[u8SeqGroupIndex]; +} + +/** + * @brief Set FMC FB_FPELCK value. + * + * @param pFMC FMC instance. + * @param u8SeqGroupIndex the index of the sequence group + * @param u32Value the value which will be written to the FB_FPELCK register. + */ +LOCAL_INLINE void FMC_HWA_SetFBFPELCKValue(FMC_Type *pFMC, uint8_t u8SeqGroupIndex, uint32_t u32Value) +{ + pFMC->FB_FPELCK[u8SeqGroupIndex] = u32Value; +} + +/** + * @brief NVI program erase Lock + * + * @param bEnable 0:unlock. 1:locked. + */ +LOCAL_INLINE void FMC_HWA_SetNVRLocked(FMC_Type *pFMC, bool bEnable) +{ + pFMC->FN_FPELCK = ((pFMC->FN_FPELCK & (~FMC_FN_FPELCK_FPELCK_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_FN_FPELCK_FPELCK_SHIFT)); +} + +/** + * @brief Get NVR lock status. + * + * @param pFCSPI FCSPI instance, e.g. FCSPI0, FCSPI1. + * @return the NVR status(1:locked 0:unlocked). + */ +LOCAL_INLINE uint8_t FCSPI_HWA_GetNVRLockedStatus(FMC_Type *pFMC) +{ + return (uint8_t)(((pFMC->FN_FPELCK) & FMC_FN_FPELCK_FPELCK_MASK) >> FMC_FN_FPELCK_FPELCK_SHIFT); +} + +/** + * @brief Read the FMC FB_CPELCK register value for all. + * + * @param pFMC FMC instance. + * @param u8SeqGroupIndex the index of the sequence group + * @return FMC FB_CPELCK regsiter value. + */ +LOCAL_INLINE uint32_t FMC_HWA_GetFBCPELCKValue(FMC_Type *pFMC, uint8_t u8SeqGroupIndex) +{ + return pFMC->FB_CPELCK[u8SeqGroupIndex]; +} + +/** + * @brief Set FMC FB_CPELCK value. + * + * @param pFMC FMC instance. + * @param u8SeqGroupIndex the index of the sequence group + * @param u32Value the value which will be written to the FB_CPELCK register. + */ +LOCAL_INLINE void FMC_HWA_SetFBCPELCKValue(FMC_Type *pFMC, uint8_t u8SeqGroupIndex, uint32_t u32Value) +{ + pFMC->FB_CPELCK[u8SeqGroupIndex] = u32Value; +} + +/** + * @brief Set OTA register lock + * + * @param pFMC FMC instance. + * @param u8SeqGroupIndex the index of the sequence group + * @param bEnable 0:OTA_CTRL can be written. 1:OTA_CTRL is locked. + */ +LOCAL_INLINE void FMC_HWA_SetOTALock(FMC_Type *pFMC, uint8_t u8SeqGroupIndex, bool bEnable) +{ + pFMC->OTA_CTRL[u8SeqGroupIndex] = ((pFMC->OTA_CTRL[u8SeqGroupIndex] & (~FMC_OTA_CTRL_OTA_LOCK_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_OTA_CTRL_OTA_LOCK_SHIFT)); +} + +/** + * @brief Set OTA active block + * + * @param pFMC FMC instance. + * @param u8SeqGroupIndex the index of the sequence group + * @param bEnable 0: block0 is the currently active OTA region. 1: block1 is the currently active OTA region. + */ +LOCAL_INLINE void FMC_HWA_SetOTAActive(FMC_Type *pFMC, uint8_t u8SeqGroupIndex, bool bEnable) +{ + pFMC->OTA_CTRL[u8SeqGroupIndex] = ((pFMC->OTA_CTRL[u8SeqGroupIndex] & (~FMC_OTA_CTRL_OTA_ACTIVE_MASK)) | ((uint32_t)(bEnable ? 1U : 0U) << FMC_OTA_CTRL_OTA_ACTIVE_SHIFT)); +} + +/** + * @brief Enable OTA + * + * @param pFMC FMC instance. + * @param u8SeqGroupIndex the index of the sequence group + */ +LOCAL_INLINE void FMC_HWA_SetOTAEnable(FMC_Type *pFMC, uint8_t u8SeqGroupIndex) +{ + pFMC->OTA_CTRL[u8SeqGroupIndex] = ((pFMC->OTA_CTRL[u8SeqGroupIndex] & (~FMC_OTA_CTRL_OTA_EN_MASK)) | FMC_OTA_CTRL_OTA_EN(0xA)); +} + +/** + * @brief Disable OTA + * + * @param pFMC FMC instance. + * @param u8SeqGroupIndex the index of the sequence group + */ +LOCAL_INLINE void FMC_HWA_SetOTADisable(FMC_Type *pFMC, uint8_t u8SeqGroupIndex) +{ + pFMC->OTA_CTRL[u8SeqGroupIndex] = ((pFMC->OTA_CTRL[u8SeqGroupIndex] & (~FMC_OTA_CTRL_OTA_EN_MASK)) | FMC_OTA_CTRL_OTA_EN(0x15)); +} + +/** + * @brief Read the FMC OTA_CTRL register value for all. + * + * @param pFMC FMC instance. + * @param u8SeqGroupIndex the index of the sequence group + * @return FMC OTA_CTRL regsiter value. + */ +LOCAL_INLINE uint32_t FMC_HWA_GetOTACtrlValue(FMC_Type *pFMC, uint8_t u8SeqGroupIndex) +{ + return pFMC->OTA_CTRL[u8SeqGroupIndex]; +} + +/** + * @brief Read the FMC OTA_VER_LOC register value for all. + * + * @param pFMC FMC instance. + * @param u8SeqGroupIndex the index of the sequence group + * @return FMC OTA_VER_LOC regsiter value. + */ +LOCAL_INLINE uint32_t FMC_HWA_GetOTAVerLocValue(FMC_Type *pFMC, uint8_t u8SeqGroupIndex) +{ + return pFMC->OTA_VER_LOC[u8SeqGroupIndex]; +} + +/** + * @brief Read the FMC OTA_ACT_VER register value for all. + * + * @param pFMC FMC instance. + * @param u8SeqGroupIndex the index of the sequence group + * @return FMC OTA_ACT_VER regsiter value. + */ +LOCAL_INLINE uint32_t FMC_HWA_GetOTAActVerValue(FMC_Type *pFMC, uint8_t u8SeqGroupIndex) +{ + return pFMC->OTA_ACT_VER[u8SeqGroupIndex]; +} + + +/** @}*/ + +#endif /* HWA_INCLUDE_HWA_FMC_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_fpu.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_fpu.h new file mode 100644 index 0000000..f7fcb0d --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_fpu.h @@ -0,0 +1,52 @@ +/** + * @file HwA_fpu.h + * @author Flagchip051 + * @brief FC4xxx FPU hardware access layer + * @version 0.1.0 + * @date 2024-01-11 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-11 Flagchip054 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef _HWA_FPU_H_ +#define _HWA_FPU_H_ + +#include "device_header.h" + +/* CPACR Bit Fields */ +#define FC7240_SCB_CPACR_CP10_MASK 0x300000u +#define FC7240_SCB_CPACR_CP10_SHIFT 20u +#define FC7240_SCB_CPACR_CP10_WIDTH 2u +#define FC7240_SCB_CPACR_CP10(x) (((uint32_t)(((uint32_t)(x))<CPACR |= (FC7240_SCB_CPACR_CP10(3) | FC7240_SCB_CPACR_CP11(3)); /* set CP10 and CP11 Full Access */ +} + +/** + * @brief disable fpu + * + */ +LOCAL_INLINE void FPU_HWA_Disable(void) +{ + SCB->CPACR &= ~((FC7240_SCB_CPACR_CP10(3) | FC7240_SCB_CPACR_CP11(3))); /* Access denied. Any attempted access generates a NOCP UsageFault */ +} + + +#endif /* HWA_INCLUDE_HWA_FPU_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_freqm.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_freqm.h new file mode 100644 index 0000000..de384e9 --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_freqm.h @@ -0,0 +1,229 @@ +/** + * @file HwA_freqm.h + * @author Flagchip + * @brief FC7xxx freqm hardware access layer + * @version 0.1.0 + * @date 2024-01-14 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-14 qxw0100 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef _HWA_FREQM_H_ +#define _HWA_FREQM_H_ + +#include "device_header.h" + +/** + * @brief Select the measured clock + * + */ +typedef enum +{ + MES_RSVD00 = 0U, + MES_SLOW_CLK = 1U, + MES_PLL1_FEEDBACK = 2U, + MES_PLL0_FEEDBACK = 3U, + MES_SCG_CLKOUT = 4U, + MES_RTC_CLK = 5U, + MES_AON_CLK = 6U, + MES_SIRC128K_CLK = 7U, + MES_RSVD01 = 8U, + MES_RSVD02 = 9U, + MES_FCPIT0_FUN_CLK = 10U, + MES_RSVD03 = 11U, + MES_RSVD04 = 12U, + MES_FCSPI0_FUN_CLK = 13U, + MES_FCSPI1_FUN_CLK = 14U, + MES_FCSPI2_FUN_CLK = 15U, + MES_RSVD05 = 16U, + MES_FCUART0_FUN_CLK = 17U, + MES_FCUART1_FUN_CLK = 18U, + MES_FCUART2_FUN_CLK = 19U, + MES_RSVD06 = 20U, + MES_TRGSEL1_OUT4 = 21U, + MES_FTU0_FUN_CLK = 22U, + MES_FTU1_FUN_CLK = 23U, + MES_RSVD07 = 24U, + MES_FTU2_FUN_CLK = 25U, + MES_FTU3_FUN_CLK = 26U, + MES_ADC0_FUN_CLK = 27U, + MES_RSVD08 = 28U, + MES_ADC1_FUN_CLK = 29U, + MES_RSVD09 = 30U, + MES_RSVD10 = 31U, + MES_RSVD11 = 32U, + MES_FOSC_DIVL = 33U, + MES_SIRC_DIVL = 34U, + MES_FIRC_DIVL = 35U, + MES_RSVD12 = 36U, + MES_PLL1_DIVL = 37U, + MES_PLL0_DIVL = 38U, + MES_RSVD13 = 39U, + MES_RSVD14 = 40U, + MES_FOSC_DIVM = 41U, + MES_SIRC_DIVM = 42U, + MES_FIRC_DIVM = 43U, + MES_RSVD15 = 44U, + MES_PLL1_DIVM = 45U, + MES_PLL0_DIVM = 46U, + MES_RSVD16 = 47U, + MES_RSVD17 = 48U, + MES_FOSC_DIVH = 49U, + MES_SIRC_DIVH = 50U, + MES_FIRC_DIVH = 51U, + MES_RSVD18 = 52U, + MES_PLL1_DIVH = 53U, + MES_PLL0_DIVH = 54U, + MES_RSVD19 = 55U, + MES_RSVD20 = 56U, + MES_SENT0_FUN_CLK = 57U, + MES_FLEXCAN0_FUN_CLK = 58U, + MES_FLEXCAN1_FUN_CLK = 59U, + MES_RSVD21 = 60U, + MES_MSC0_FUN_CLK = 61U, + MES_TPU_FUN_CLK = 62U, + MES_RSVD22 = 63U, +} FREQM_MesClkSelType; + +/** + * @brief Set the clock selection + * + * @param pFreqm the base address of the FREQM + * @param eClkSel the clock selection index + */ +LOCAL_INLINE void FREQM_HWA_MesClkSel(FREQM_Type *pFreqm,FREQM_MesClkSelType eClkSel) +{ + pFreqm->CTRL &= ~FREQM_CTRL_MES_CLK_SEL_MASK; + pFreqm->CTRL |= FREQM_CTRL_MES_CLK_SEL((uint32_t)eClkSel); +} + +/** + * @brief Set the clock selection + * + * @param pFreqm the base address of the FREQM + * @param u8PredivVal the measure clock prediv value + */ +LOCAL_INLINE void FREQM_HWA_MesClk_PreDiv(FREQM_Type *pFreqm,uint8_t u8PredivVal) +{ + pFreqm->CTRL &= ~FREQM_CTRL_MES_CLK_PREDIV_MASK; + pFreqm->CTRL |= FREQM_CTRL_MES_CLK_PREDIV(u8PredivVal); +} + +/** + * @brief Enable count event interrupt + * + * @param pFreqm the base address of the FREQM + */ +LOCAL_INLINE void FREQM_HWA_EnableCntEventInterrupt(FREQM_Type *pFreqm) +{ + pFreqm->CTRL |= FREQM_CTRL_CNT_EVENT_IE_MASK; +} + +/** + * @brief Disable count event interrupt + * + * @param pFreqm the base address of the FREQM + */ +LOCAL_INLINE void FREQM_HWA_DisableCntEventInterrupt(FREQM_Type *pFreqm) +{ + pFreqm->CTRL &= ~((uint32_t)FREQM_CTRL_CNT_EVENT_IE_MASK); +} + +/** + * @brief Set counting length of measure counter + * + * @param pFreqm the base address of the FREQM + * @param u32MesLen counting length of measure counter + */ +LOCAL_INLINE void FREQM_HWA_SetMesLength(FREQM_Type *pFreqm,uint32_t u32MesLen) +{ + pFreqm->MES_LENGTH = u32MesLen; +} + +/** + * @brief Set timeout value of reference counter + * + * @param pFreqm the base address of the FREQM + * @param u32RefTo timeout value of reference counter + */ +LOCAL_INLINE void FREQM_HWA_SetRefTimeout(FREQM_Type *pFreqm,uint32_t u32RefTo) +{ + pFreqm->REF_TIMEOUT = u32RefTo; +} + +/** + * @brief Set value of reference counter + * + * @param pFreqm the base address of the FREQM + * @param u32RefCnt value of reference counter + */ +LOCAL_INLINE void FREQM_HWA_SetRefCnt(FREQM_Type *pFreqm,uint32_t u32RefCnt) +{ + pFreqm->REF_CNT = u32RefCnt; +} + +/** + * @brief Clear counter event interrupt flag + * + * @param pFreqm the base address of the FREQM + */ +LOCAL_INLINE void FREQM_HWA_ClearInterruptFlag(FREQM_Type *pFreqm) +{ + pFreqm->CNT_STATUS |= FREQM_CNT_STATUS_CNT_EVENT_MASK; +} + +/** + * @brief Get counter event interrupt flag + * + * @param pFreqm the base address of the FREQM + * @param return false for disable, true for enable. + */ +LOCAL_INLINE bool FREQM_HWA_GetInterruptFlag(FREQM_Type *pFreqm) +{ + return ((pFreqm->CNT_STATUS & FREQM_CNT_STATUS_CNT_EVENT_MASK) == FREQM_CNT_STATUS_CNT_EVENT_MASK) ? true : false; +} + +/** + * @brief Get counter status + * + * @param pFreqm the base address of the FREQM + * @param return Counter status. + */ +LOCAL_INLINE uint32_t FREQM_HWA_GetCntStatus(FREQM_Type *pFreqm) +{ + uint32_t u32Mask = (FREQM_CNT_STATUS_MES_CNT_START_MASK|FREQM_CNT_STATUS_MES_CNT_STOP_MASK|FREQM_CNT_STATUS_REF_CNT_STOP_MASK); + return (pFreqm->CNT_STATUS & u32Mask); +} + +/** + * @brief Set value of measure counter + * + * @param pFreqm the base address of the FREQM + * @param u32MesCnt value of measure counter + */ +LOCAL_INLINE void FREQM_HWA_SetMesCnt(FREQM_Type *pFreqm,uint32_t u32MesCnt) +{ + pFreqm->MES_CNT = u32MesCnt; +} + +/** + * @brief Get saved reference counter value + * + * @param pFreqm the base address of the FREQM + * @param return saved reference counter value. + */ +LOCAL_INLINE uint32_t FREQM_HWA_GetRefCntSave(FREQM_Type *pFreqm) +{ + return pFreqm->REF_CNT_SAVE; +} + +#endif /* #ifndef _HWA_FREQM_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_ftu.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_ftu.h new file mode 100644 index 0000000..db782eb --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_ftu.h @@ -0,0 +1,1924 @@ +/** + * @file HwA_ftu.h + * @author Flagchip070 + * @brief FC7xxx FTU hardware access layer + * @version 0.1.0 + * @date 2022-11-15 + * + * @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2022-11-15 Flagchip070 N/A First version for FC7300 + ******************************************************************************** */ + +#ifndef _HWA_FTU_H_ +#define _HWA_FTU_H_ + +#include "device_header.h" +/********* Local typedef ************/ +/** + * @brief The definition of enable the deadtime of channel and channel+1 + * + */ +#define FTU_CHCTRL_DEADTIME_CHANNEL(channel) (uint32_t)((uint32_t)1U << ((((uint32_t)(channel) >> 1U) << 3U) + 4U)) +/** + * @brief The definition of enable the complement of channel + * + */ +#define FTU_CHCTRL_COMPLEMENT_CHANNEL(channel) (uint32_t)((uint32_t)1U << ((((uint32_t)(channel) >> 1U) << 3U) + 1U)) +/** + * @brief The definition of enable the synchronization for channel and channel+1 + * + */ +#define FTU_CHCTRL_SYNCEN_CHANNEL(channel) (uint32_t)((uint32_t)1U << ((((uint32_t)(channel) >> 1U) << 3U) + 5U)) +/** + * @brief The definition of enable the Phase shift mode for channel and channel+1 + * + */ +#define FTU_CHCTRL_PHASE_CHANNEL(channel) (uint32_t)((uint32_t)1U << (((uint32_t)(channel) >> 1U) << 3U)) +/** + * @brief The definition of enable the Enhanced Phase shift mode for channel and channel+1 + * + */ +#define FTU_CHCTRL_EPHASE_CHANNEL(channel) (uint32_t)((uint32_t)1U << ((((uint32_t)(channel) >> 1U) << 3U) + 7U)) +/** + * @brief The definition of enable the fault control in channel and channel+1 + * + */ +#define FTU_CHCTRL_FAULT_CHANNEL(channel) (uint32_t)((uint32_t)1U << ((((uint32_t)(channel) >> 1U) << 3U) + 6U)) + +/********* Local typedef ************/ +/** + * @brief Select the FTU Debug Mode + * + */ +typedef enum +{ + FTU_DBG_COUNTER_STOP_CHN_WORKS = 0U, /*!< FTU counter stopped, channel works as function mode. */ + FTU_DBG_COUNTER_STOP_CHN_FORCE_SAFE = 1U, /*!< FTU counter stopped, channel output force to safe state. */ + FTU_DBG_COUNTER_STOP_CHN_FROZEN = 2U, /*!< FTU counter stopped, channel output is frozen. */ + FTU_DBG_COUNTER_WORKS_CHN_WORKS = 3U /*!< FTU counter works as function mode, channel works as function mode. */ +} FTU_DebugModeType; + +typedef enum +{ + FTU_CHANNEL_MODE_INPUT = 0u, + FTU_CHANNEL_MODE_OUTPUT_COMPARE = 1u, + FTU_CHANNEL_MODE_EDGE_ALIGN_PWM = 2u, + FTU_CHANNEL_MODE_DO_NOT_CARE = 3u, +} FTU_ChannelModeType; + +typedef enum +{ + FTU_CHANNEL_EDGE_NOT_USED = 0u, + FTU_CHANNEL_EDGE_RISING = 1u, + FTU_CHANNEL_EDGE_FALLING = 2u, + FTU_CHANNEL_EDGE_BOTH = 3u, + FTU_CHANNEL_OC_TOGGLE = 1u, + FTU_CHANNEL_OC_CLEAR = 2u, + FTU_CHANNEL_OC_SET = 3u, + FTU_CHANNEL_PWM_HIGH_TRUE = 2u, + FTU_CHANNEL_PWM_LOW_TRUE = 3u, +} FTU_ChannelEdgeLevelType; +/** + * @brief Select the prescaler of the FTU + * + */ +typedef enum +{ + FTU_DIV_1 = 0U, + FTU_DIV_2, + FTU_DIV_4, + FTU_DIV_8, + FTU_DIV_16, + FTU_DIV_32, + FTU_DIV_64, + FTU_DIV_128 +} FTU_PrescalerType; + +/** + * @brief Select the prescaler of the FTU filter + * + */ +typedef enum +{ + FTU_FLT_DIV_1 = 0U, + FTU_FLT_DIV_2, + FTU_FLT_DIV_3, + FTU_FLT_DIV_4, + FTU_FLT_DIV_5, + FTU_FLT_DIV_6, + FTU_FLT_DIV_7, + FTU_FLT_DIV_8, + FTU_FLT_DIV_9, + FTU_FLT_DIV_10, + FTU_FLT_DIV_11, + FTU_FLT_DIV_12, + FTU_FLT_DIV_13, + FTU_FLT_DIV_14, + FTU_FLT_DIV_15, + FTU_FLT_DIV_16 +} FTU_FilterPrescalerType; + +/** + * @brief selects the encoding mode used in the Quadrature Decoder mode + * + */ +typedef enum +{ + FTU_QUADMODE_PHA_PHB_ENCODING_MODE = 0U, /*!< Phase A and phase B encoding mode */ + FTU_QUADMODE_COUNT_DIR_ENCODING_MODE, /*!< Count and direction encoding mode */ +} FTU_QuadratureModeType; + +/** + * @brief FTU Counter Direction In Quadrature Decoder Mode + * + */ +typedef enum +{ + FTU_QUADIR_DECREMENT = 0U, /*!< FTU counter decrement */ + FTU_QUADIR_INCREMENT, /*!< FTU counter increment */ +} FTU_QuadratureDirectionType; + +/** + * @brief Timer Overflow Direction In Quadrature Decoder Mode + * + */ +typedef enum +{ + FTU_TOFDIR_TOF_SET_ON_BOTTOM = 0U, /*!< TOF bit was set on the bottom of counting */ + FTU_TOFDIR_TOF_SET_ON_TOP, /*!< TOF bit was set on the top of counting */ +}FTU_TimerOverflowDirectionType; + +/** + * @brief register bit status + * + */ +typedef enum +{ + FTU_BIT_LOW = 0U, + FTU_BIT_HIGH +} FTU_BitStatusType; + +/** + * @brief Ftu module clock source + * + */ +typedef enum +{ + FTU_MODULE_NO_CLK = 0U, /*!< No clock selected */ + FTU_MODULE_INTERNAL_CLK = 1U, /*!< FTU input clock */ + FTU_MODULE_EXTERNAL_CLK = 3U, /*!< External pin input clock */ +} FTU_ModuleClkSrcType; + +/** + * @brief Disable channel match trigger/interrupt when count-up/down in CPWM/QUAD mode + * + */ +typedef enum +{ + FTU_DISABLE_TRIG_INTR_NONE = 0U, /*!< No effect */ + FTU_DISABLE_TRIG_INTR_CNT_DOWN = 1U, /*!< Disable trigger/interrupt when count-down */ + FTU_DISABLE_TRIG_INTR_CNT_UP = 2U, /*!< Disable trigger/interrupt when count-up */ + FTU_DISABLE_TRIG_INTR_CNT_UP_DOWN = 3U, /*!< Disable trigger/interrupt when count-up/down */ +}FTU_UpDownDisableType; + +/** + * @brief hardware trig(n) mode + * + */ +typedef enum +{ + FTU_CLEARS_TRIG_WHEN_DETECTED = 0x0U, /*!< FTU clears the TRIG(n) bit when the hardware trigger j is detected, where n = 0, 1,2. */ + FTU_NOT_CLEARS_TRIG_WHEN_DETECTED = 0x01U /*!< FTU does not clear the TRIG(n) bit when the hardware trigger j is detected, where n = 0, 1,2. */ +} FTU_TrigModeType; + +/** + * @brief fault mode enumeration + * + */ +typedef enum +{ + FTU_FAULT_MODE_DISABLED = 0x00U, /*!< Fault control is disabled for all channels */ + FTU_FAULT_MODE_EVEN_CHANNEL = 0x01U, /*!< Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing */ + FTU_FAULT_MODE_CHANNEL_ALL = 0x02U, /*!< Fault control is enabled for all channels, and the selected mode is the manual fault clearing */ + FTU_FAULT_MODE_AUTO = 0x03U /*!< Fault control is enabled for all channels, and the selected mode is the automatic fault clearing */ +} FTU_FaultModeType; + +/** + * @brief external clock enumeration + * + */ +typedef enum +{ + FTU_TCLK0_USED = 0U, /*!< FTU_TCLK0 pin as FTU external clock */ + FTU_TCLK1_USED = 1U, /*!< FTU_TCLK1 pin as FTU external clock */ + FTU_TCLK2_USED = 2U, /*!< FTU_TCLK2 pin as FTU external clock */ + FTU_NO_CLK_USED = 3U, /*!< No clock input */ +} FTU_TclkSelType; + +/** + * @brief Deadtime Prescaler Value + * + */ +typedef enum +{ + FTU_DEADTIME_PRESCALER_DIV_1 = 0U, /*!< Divide the FTU input clock by 1 */ + FTU_DEADTIME_PRESCALER_DIV_4 = 2U, /*!< Divide the FTU input clock by 4 */ + FTU_DEADTIME_PRESCALER_DIV_16 = 3U, /*!< Divide the FTU input clock by 16 */ +} FTU_DeadTimePrescalerType; + +/** + * @brief Trigger output control + * + */ +typedef enum +{ + FTU_TRIG_OUTPUT_AS_CHANNEL_MODE = 0U, /*!< channel outputs will be controlled by channel mode */ + FTU_TRIG_OUTPUT_AS_TRIGGER = 1U, /*!< If a match in the channel occurs, channel output will be a trigger */ +}FTU_TrigOutputModeType; + +/** + * @brief Fault disable channel output delay value selection + * + */ +typedef enum +{ + FTU_FAULT_DISABLE_DELAY_NO_DELAY = 0u, /*!< Select no delay */ + FTU_FAULT_DISABLE_DELAY_VALUE_0 = 1u, /*!< Select delay value 0 */ + FTU_FAULT_DISABLE_DELAY_VALUE_1 = 2u /*!< Select delay value 1 */ +}FTU_FaultDisableDelayType; + +/** + * @brief Input Capture Measurement Mode + * + */ +typedef enum +{ + FTU_MEASURE_MODE_OFF = 0u, /*!< Do not use measurement mode */ + FTU_MEASURE_MODE_DUTY_CYCLE = 1u, /*!< Duty-cycle Measure */ + FTU_MEASURE_MODE_PERIOD = 2u, /*!< Period Measure */ + FTU_MEASURE_EDGE_NUMBER = 3u, /*!< Edge Number Measure */ + FTU_MEASURE_EXPECT_EDGE_NUMBER = 4u, /*!< Expect Edge Number Measure */ + FTU_MEASURE_ICENM_WIND_WRITE = 7u, /*!< Configure ICENM Window */ +}FTU_MeasurementModeType; + +/********* Local inline function ************/ + +/** + * @brief Clear FTU module registers + * + * @param pFtu FTU instance + */ +LOCAL_INLINE void FTU_HWA_ClearModuleRegister(FTU_Type *pFtu) +{ + uint32_t u32Loop; + pFtu->SC &= 0U; + pFtu->CNT = 0U; + pFtu->MOD = 0U; + for(u32Loop = 0u; u32Loop < FTU_CHANNEL_CONTROLS_COUNT; u32Loop++) + { + pFtu->CONTROLS[u32Loop].CSCn = (uint32_t)0u; + pFtu->CONTROLS[u32Loop].CVn = (uint32_t)0u; + } + pFtu->CNTIN = 0U; + pFtu->STATUS |= FTU_STATUS_CHNF_MASK; + pFtu->MODE = 0x00000004U; + pFtu->SYNC = 0U; + pFtu->OUTINIT = 0U; + pFtu->OUTMASK = 0U; + pFtu->CHCTRL = 0U; + pFtu->DEADTIME = 0U; + pFtu->TRIGCONF = 0U; + pFtu->POL = 0U; + pFtu->FMS &= 0U; + pFtu->FILTER = 0U; + pFtu->FLTCTRL = 0U; + pFtu->QDCTRL = 0U; + pFtu->CONF = FTU_CONF_DBG(3u); + pFtu->FLTPOL = 0U; + pFtu->SYNCONF = 0U; + pFtu->INVCTRL = 0U; + pFtu->SWOCTRL = 0U; + pFtu->PWMLOAD = 0U; + pFtu->PAIRDEADTIME0 = 0U; + pFtu->PAIRDEADTIME1 = 0U; + pFtu->PAIRDEADTIME2 = 0U; + pFtu->PAIRDEADTIME3 = 0U; +} + +/** + * @brief Disable Global Time Base Enable + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableGlobalTimeBase(FTU_Type *pFtu) +{ + pFtu->CONF &= ~FTU_CONF_GTBEEN_MASK; +} + +/** + * @brief Enable Global Time Base Enable + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableGlobalTimeBase(FTU_Type *pFtu) +{ + pFtu->CONF |= FTU_CONF_GTBEEN_MASK; +} + +/** + * @brief Set the LDOK flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_SetPwmLoadEnable(FTU_Type *pFtu) +{ + pFtu->PWMLOAD |= FTU_PWMLOAD_LDOK_MASK; +} + +/** + * @brief Clear the LDOK flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_ClearPwmLoadEnable(FTU_Type *pFtu) +{ + pFtu->PWMLOAD &= ~FTU_PWMLOAD_LDOK_MASK; +} + +/** + * @brief Set the CNTINC flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_SetCntinSync(FTU_Type *pFtu) +{ + pFtu->SYNCONF |= FTU_SYNCONF_CNTINC_MASK; +} + +/** + * @brief Clear the CNTINC flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_ClearCntinSync(FTU_Type *pFtu) +{ + pFtu->SYNCONF &= ~FTU_SYNCONF_CNTINC_MASK; +} + +/** + * @brief Set the SYNCEN flag + * + * @param pFtu the base address of the FTU instance + * @param u32Index the index of SYNCEN + */ +LOCAL_INLINE void FTU_HWA_SetChannelSyncEnable(FTU_Type *pFtu, uint32_t u32Index) +{ + const uint32_t u32MaskTab[4] = {FTU_CHCTRL_SYNCEN0_MASK, FTU_CHCTRL_SYNCEN1_MASK, + FTU_CHCTRL_SYNCEN2_MASK, FTU_CHCTRL_SYNCEN3_MASK}; + pFtu->CHCTRL |= u32MaskTab[u32Index]; +} + +/** + * @brief Clear the SYNCEN flag + * + * @param pFtu the base address of the FTU instance + * @param u32Index the index of SYNCEN + */ +LOCAL_INLINE void FTU_HWA_ClearChannelSyncEnable(FTU_Type *pFtu, uint32_t u32Index) +{ + const uint32_t u32MaskTab[4] = {FTU_CHCTRL_SYNCEN0_MASK, FTU_CHCTRL_SYNCEN1_MASK, + FTU_CHCTRL_SYNCEN2_MASK, FTU_CHCTRL_SYNCEN3_MASK}; + pFtu->CHCTRL &= ~u32MaskTab[u32Index]; +} + +/** + * @brief Set the PWMSYNC flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_SetPwmSyncMode(FTU_Type *pFtu) +{ + pFtu->MODE |= FTU_MODE_PWMSYNC_MASK; +} + +/** + * @brief Clear the PWMSYNC flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_ClearPwmSyncMode(FTU_Type *pFtu) +{ + pFtu->MODE &= ~FTU_MODE_PWMSYNC_MASK; +} + +/** + * @brief Set the REINIT flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_SetReinitBySync(FTU_Type *pFtu) +{ + pFtu->SYNC |= FTU_SYNC_REINIT_MASK; +} + +/** + * @brief Clear the REINIT flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_ClearReinitBySync(FTU_Type *pFtu) +{ + pFtu->SYNC &= ~FTU_SYNC_REINIT_MASK; +} + +/** + * @brief Set the CNTMAX flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableMaxLoadPoint(FTU_Type *pFtu) +{ + pFtu->SYNC |= FTU_SYNC_CNTMAX_MASK; +} + +/** + * @brief Clear the CNTMAX flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableMaxLoadPoint(FTU_Type *pFtu) +{ + pFtu->SYNC &= ~FTU_SYNC_CNTMAX_MASK; +} + +/** + * @brief Set the CNTMIN flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableMinLoadPoint(FTU_Type *pFtu) +{ + pFtu->SYNC |= FTU_SYNC_CNTMIN_MASK; +} + +/** + * @brief Clear the CNTMIN flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableMinLoadPoint(FTU_Type *pFtu) +{ + pFtu->SYNC &= ~FTU_SYNC_CNTMIN_MASK; +} + +/** + * @brief Set the CHNSEL flag of a channel + * + * @param pFtu the base address of the FTU instance + * @param u32Channel channel index + */ +LOCAL_INLINE void FTU_HWA_EnableChannelMatchReload(FTU_Type *pFtu, uint32_t u32Channel) +{ + pFtu->PWMLOAD |= FTU_PWMLOAD_CHNSEL((uint32_t)1u << u32Channel); +} + +/** + * @brief Clear the CHNSEL flag of a channel + * + * @param pFtu the base address of the FTU instance + * @param u32Channel channel index + */ +LOCAL_INLINE void FTU_HWA_DisableChannelMatchReload(FTU_Type *pFtu, uint32_t u32Channel) +{ + pFtu->PWMLOAD &= ~FTU_PWMLOAD_CHNSEL((uint32_t)1u << u32Channel); +} + +/** + * @brief configure the frequency of the reload opportunities + * + * @param pFtu the base address of the FTU instance + * @param u8Freq the number of enabled reload opportunities that should happen until an + * enabled reload opportunity becomes a reload point + */ +LOCAL_INLINE void FTU_HWA_ConfigFreqOfReloadOp(FTU_Type *pFtu, uint8_t u8Freq) +{ + pFtu->CONF &= ~FTU_CONF_LDFQ_MASK; + pFtu->CONF |= FTU_CONF_LDFQ(u8Freq); +} + +/** + * @brief Selects the FTU behavior in Debug mode + * + * @param pFtu the base address of the FTU instance + * @param u32Mode debug mode + */ +LOCAL_INLINE void FTU_HWA_ConfigDebugMode(FTU_Type *pFtu, uint32_t u32Mode) +{ + pFtu->CONF &= ~FTU_CONF_DBG_MASK; + pFtu->CONF |= FTU_CONF_DBG(u32Mode); +} + +/** + * @brief Disable channel match trigger/interrupt when count-up/down in CPWM/QUAD mode + * + * @param pFtu the base address of the FTU instance + * @param eUpdownDisable up-down disable mode + */ +LOCAL_INLINE void FTU_HWA_ConfigUpDownDisable(FTU_Type *pFtu, FTU_UpDownDisableType eUpdownDisable) +{ + pFtu->SC &= ~FTU_SC_UPDOWN_DIS_MASK; + pFtu->SC |= FTU_SC_UPDOWN_DIS((uint32_t)eUpdownDisable); +} + +/** + * @brief Enable reload point interrupt + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableReloadPointInterrupt(FTU_Type *pFtu) +{ + pFtu->SC |= FTU_SC_RIE_MASK; +} + +/** + * @brief Disable reload point interrupt + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableReloadPointInterrupt(FTU_Type *pFtu) +{ + pFtu->SC &= ~((uint32_t)FTU_SC_RIE_MASK); +} + +/** + * @brief Enable software output control of channels + * + * @param pFtu the base address of the FTU instance + * @param u32Mask channel mask + */ +LOCAL_INLINE void FTU_HWA_EnalbeSWOControl(FTU_Type *pFtu, uint32_t u32Mask) +{ + pFtu->SWOCTRL |= FTU_SWOCTRL_CHNOC(u32Mask); +} + +/** + * @brief Disable software output control of channels + * + * @param pFtu the base address of the FTU instance + * @param u32Mask channel mask + */ +LOCAL_INLINE void FTU_HWA_DisalbeSWOControl(FTU_Type *pFtu, uint32_t u32Mask) +{ + pFtu->SWOCTRL &= ~FTU_SWOCTRL_CHNOC(u32Mask); +} + +/** + * @brief Set the software output control value + * + * @param pFtu the base address of the FTU instance + * @param u32Mask channel mask + */ +LOCAL_INLINE void FTU_HWA_SetSWOValue(FTU_Type *pFtu, uint32_t u32Mask) +{ + pFtu->SWOCTRL |= FTU_SWOCTRL_CHNOCV(u32Mask); +} + +/** + * @brief Clear the software output control value + * + * @param pFtu the base address of the FTU instance + * @param u32Mask channel mask + */ +LOCAL_INLINE void FTU_HWA_ClearSWOValue(FTU_Type *pFtu, uint32_t u32Mask) +{ + pFtu->SWOCTRL &= ~FTU_SWOCTRL_CHNOCV(u32Mask); +} + +/** + * @brief Configure the pair deadtime prescaler value + * + * @param pFtu the base address of the FTU instance + * @param u32Channel channel index + * @param ePrescaler prescaler value + */ +LOCAL_INLINE void FTU_HWA_ConfigPairDeadtimePrescaler(FTU_Type *pFtu, uint32_t u32Channel, FTU_DeadTimePrescalerType ePrescaler) +{ + uint32_t u32RegValue; + volatile uint32_t *pPairDeadtime = &pFtu->PAIRDEADTIME0; + u32Channel = u32Channel >> 1u; + u32RegValue = pPairDeadtime[(u32Channel << 1u)]; + u32RegValue &= ~(uint32_t)FTU_DEADTIME_DTPS_MASK; + u32RegValue |= FTU_DEADTIME_DTPS(ePrescaler); + *pPairDeadtime = u32RegValue; +} + +/** + * @brief Configure the deadtime value + * + * @param pFtu the base address of the FTU instance + * @param u32Channel channel index + * @param u32Value deadtime value + */ +LOCAL_INLINE void FTU_HWA_ConfigPairDeadtimeValue(FTU_Type *pFtu, uint32_t u32Channel, uint32_t u32Value) +{ + uint32_t u32RegValue; + volatile uint32_t *pPairDeadtime = &pFtu->PAIRDEADTIME0; + u32Channel = u32Channel >> 1u; + u32RegValue = pPairDeadtime[(u32Channel << 1u)]; + u32RegValue &= ~(uint32_t)FTU_DEADTIME_DTVAL_MASK; + u32RegValue &= ~(uint32_t)FTU_DEADTIME_DTVALEX_MASK; + u32RegValue |= FTU_DEADTIME_DTVAL(u32Value & 0x3Fu); + u32RegValue |= FTU_DEADTIME_DTVALEX(u32Value >> 6); + *pPairDeadtime = u32RegValue; +} + +/** + * @brief Configure the deadtime prescaler value + * + * @param pFtu the base address of the FTU instance + * @param ePrescaler prescaler value + */ +LOCAL_INLINE void FTU_HWA_ConfigDeadtimePrescaler(FTU_Type *pFtu, FTU_DeadTimePrescalerType ePrescaler) +{ + uint32_t u32RegValue = pFtu->DEADTIME; + u32RegValue &= ~(uint32_t)FTU_DEADTIME_DTPS_MASK; + u32RegValue |= FTU_DEADTIME_DTPS(ePrescaler); + pFtu->DEADTIME = u32RegValue; +} + +/** + * @brief Configure the deadtime value + * + * @param pFtu the base address of the FTU instance + * @param u32Value deadtime value + */ +LOCAL_INLINE void FTU_HWA_ConfigDeadtimeValue(FTU_Type *pFtu, uint32_t u32Value) +{ + uint32_t u32RegValue = pFtu->DEADTIME; + u32RegValue &= ~(uint32_t)FTU_DEADTIME_DTVAL_MASK; + u32RegValue &= ~(uint32_t)FTU_DEADTIME_DTVALEX_MASK; + u32RegValue |= FTU_DEADTIME_DTVAL(u32Value & 0x3Fu); + u32RegValue |= FTU_DEADTIME_DTVALEX(u32Value >> 6); + pFtu->DEADTIME = u32RegValue; +} + +/** + * @brief Get the counter value of the selected FTU module + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE uint32_t FTU_HWA_GetCounterValue(FTU_Type *pFtu) +{ + return (uint32_t)pFtu->CNT; +} + +/** + * @brief Clear FTU counter + * + * @param pFtu the base address of the FTU instance + * @param u32RegValue CNT register value + */ +LOCAL_INLINE void FTU_HWA_ClearModuleCounter(FTU_Type *pFtu, uint32_t u32RegValue) +{ + pFtu->CNT = u32RegValue; +} + +/** + * @brief Configure FTU channel + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + * @param u32RegValue the value to write to CSC register + */ +LOCAL_INLINE void FTU_HWA_ConfigChannel(FTU_Type *pFtu, uint8_t u8Channel, uint32_t u32RegValue) +{ + pFtu->CONTROLS[u8Channel].CSCn = u32RegValue; +} + +/** + * @brief Get FTU channel value + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + * @return CVn register value + */ +LOCAL_INLINE uint32_t FTU_HWA_GetChannelValue(FTU_Type *pFtu, uint8_t u8Channel) +{ + return (pFtu->CONTROLS[u8Channel].CVn); +} + +/** + * @brief Set FTU channel value + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + * @param u32RegValue CVn register value + */ +LOCAL_INLINE void FTU_HWA_SetChannelValue(FTU_Type *pFtu, uint8_t u8Channel, uint32_t u32RegValue) +{ + pFtu->CONTROLS[u8Channel].CVn = u32RegValue; +} + +/** + * @brief Set FTU counter compare val + * + * @param pFtu the base address of the FTU instance + * @param u32RegValue MOD register value + */ +LOCAL_INLINE void FTU_HWA_SetModuleCompareValue(FTU_Type *pFtu, uint32_t u32RegValue) +{ + pFtu->MOD = u32RegValue & FTU_MOD_MASK; +} + +/** + * @brief Set FTU counter initial value + * + * @param pFtu the base address of the FTU instance + * @param u32RegValue CNTIN register value + */ +LOCAL_INLINE void FTU_HWA_SetCounterInitialValue(FTU_Type *pFtu, uint32_t u32RegValue) +{ + pFtu->CNTIN = u32RegValue & FTU_CNTIN_INIT_MASK; +} + +/** + * @brief Configure FTU mode + * + * @param pFtu the base address of the FTU instance + * @param u32RegValue MODE register value + */ +LOCAL_INLINE void FTU_HWA_ConfigModuleMode(FTU_Type *pFtu, uint32_t u32RegValue) +{ + pFtu->MODE = u32RegValue; +} + +/** + * @brief Configure FTU deadtime + * + * @param pFtu the base address of the FTU instance + * @param u32RegValue DEADTIME register value + */ +LOCAL_INLINE void FTU_HWA_ConfigDeadtime(FTU_Type *pFtu, uint32_t u32RegValue) +{ + pFtu->DEADTIME = u32RegValue; +} + +/** + * @brief Configure input capture filter + * + * @param pFtu the base address of the FTU instance + * @param u32Channel Channel of FTU instance + * @param u32FilterValue Filter value + */ +LOCAL_INLINE void FTU_HWA_ConfigInputCaptureFilter(FTU_Type *pFtu, uint32_t u32Channel, uint32_t u32FilterValue) +{ + pFtu->FILTER &= ~((uint32_t)0xFu << (u32Channel << 2)); + pFtu->FILTER |= u32FilterValue << (u32Channel << 2); +} + +/** + * @brief Enable FTU module fault + * + * @param pFtu the base address of the FTU instance + * @param u8InputMask Fault input mask, 0-3 bit indicate fault 0-3 + */ +LOCAL_INLINE void FTU_HWA_EnableModuleFault(FTU_Type *pFtu, uint8_t u8InputMask) +{ + pFtu->FLTCTRL |= ((uint32_t)u8InputMask & (uint32_t)0xFU); +} + +/** + * @brief get the fault input enable status + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE uint32_t FTU_HWA_GetFaultEnable(FTU_Type *pFtu) +{ + uint32_t u32RegValue = pFtu->FLTCTRL; + return u32RegValue & (uint32_t)0xFU; +} + +/** + * @brief Disable FTU module fault + * + * @param pFtu the base address of the FTU instance + * @param u8Input Fault input number, 0-3 bit indicate fault 0-3 + */ +LOCAL_INLINE void FTU_HWA_DisableModuleFault(FTU_Type *pFtu, uint8_t u8Input) +{ + pFtu->FLTCTRL &= ~((uint32_t)u8Input & (uint32_t)0xFU); +} + +/** + * @brief Enable FTU module fault glitch filter + * + * @param pFtu the base address of the FTU instance + * @param u8Input Fault input number, 0-3 bit indicate fault 0-3 + */ +LOCAL_INLINE void FTU_HWA_EnableModuleFaultGlitchFilter(FTU_Type *pFtu, uint8_t u8Input) +{ + pFtu->FLTCTRL |= (((uint32_t)u8Input & (uint32_t)0xFU) << 4U); +} + +/** + * @brief Disable FTU module fault glitch filter + * + * @param pFtu the base address of the FTU instance + * @param u8Input Fault input number, 0-3 bit indicate fault 0-3 + */ +LOCAL_INLINE void FTU_HWA_DisableModuleFaultGlitchFilter(FTU_Type *pFtu, uint8_t u8Input) +{ + pFtu->FLTCTRL &= ~(((uint32_t)u8Input & (uint32_t)0xFU) << FTU_FLTCTRL_FLT0GFEN_SHIFT); +} + +/** + * @brief Set FTU module fault filter value + * + * @param pFtu the base address of the FTU instance + * @param u8Value FTU fault filter value + */ +LOCAL_INLINE void FTU_HWA_SetModuleFaultFilterValue(FTU_Type *pFtu, uint8_t u8Value) +{ + uint32_t u32TempRegValue = pFtu->FLTCTRL; + pFtu->FLTCTRL = (u32TempRegValue & ~(uint32_t)FTU_FLTCTRL_FFVAL_MASK) | FTU_FLTCTRL_FFVAL(u8Value); +} + +/** + * @brief Set FTU module fault disable channel output delay value0 + * + * @param pFtu the base address of the FTU instance + * @param u8Value FTU fault delay value0 + */ +LOCAL_INLINE void FTU_HWA_SetFaultDelay0(FTU_Type *pFtu, uint8_t u8Value) +{ + pFtu->FLTCTRL &= ~(uint32_t)FTU_FLTCTRL_FDLYV0_MASK; + pFtu->FLTCTRL |= FTU_FLTCTRL_FDLYV0(u8Value); +} + +/** + * @brief Set FTU module fault disable channel output delay value + * + * @param pFtu the base address of the FTU instance + * @param u8Value FTU fault delay value1 + */ +LOCAL_INLINE void FTU_HWA_SetFaultDelay1(FTU_Type *pFtu, uint8_t u8Value) +{ + pFtu->FLTPOL &= ~(uint32_t)FTU_FLTPOL_FDLYV1_MASK; + pFtu->FLTPOL |= FTU_FLTPOL_FDLYV1(u8Value); +} + +/** + * @brief Configure FTU module fault polarity + * + * @param pFtu the base address of the FTU instance + * @param u32FaultIndex index of the fault + * @param u8InputPol the polarity of the fault input + */ +LOCAL_INLINE void FTU_HWA_ConfigFaultPolarity(FTU_Type *pFtu, uint32_t u32FaultIndex, uint8_t u8InputPol) +{ + uint32_t u32RegValue = pFtu->FLTPOL; + u32RegValue &= ~(FTU_FLTPOL_FLT0POL_MASK << u32FaultIndex); + u32RegValue |= FTU_FLTPOL_FLT0POL(u8InputPol) << u32FaultIndex; + pFtu->FLTPOL = u32RegValue; +} + +/** + * @brief Set FTU module prescale + * + * @param pFtu the base address of the FTU instance + * @param ePs FTU clock prescaler enumeration + */ +LOCAL_INLINE void FTU_HWA_SetModulePrescale(FTU_Type *pFtu, FTU_PrescalerType ePs) +{ + uint32_t u32RegValue = pFtu->SC; + pFtu->SC = (u32RegValue & ~(uint32_t)FTU_SC_PS_MASK) | FTU_SC_PS(ePs); +} + +/** + * @brief Read FTU module overflow flag + * + * @param pFtu the base address of the FTU instance + * @return FTU overflow flag + */ +LOCAL_INLINE uint8_t FTU_HWA_ReadModuleOverflowFlag(FTU_Type *pFtu) +{ + return (uint8_t)((pFtu->SC & (uint32_t)FTU_SC_TOF_MASK) >> FTU_SC_TOF_SHIFT); +} + +/** + * @brief Read FTU module overflow interrupt enable + * + * @param pFtu the base address of the FTU instance + * @return FTU overflow interrupt enable + */ +LOCAL_INLINE uint8_t FTU_HWA_ReadModuleOverflowIntrEnable(FTU_Type *pFtu) +{ + return (uint8_t)((pFtu->SC & (uint32_t)FTU_SC_TOIE_MASK) >> FTU_SC_TOIE_SHIFT); +} + +/** + * @brief Read FTU module reload flag + * + * @param pFtu the base address of the FTU instance + * @return FTU reload flag + */ +LOCAL_INLINE uint8_t FTU_HWA_ReadModuleReloadFlag(FTU_Type *pFtu) +{ + return (uint8_t)((pFtu->SC & (uint32_t)FTU_SC_RF_MASK) >> FTU_SC_RF_SHIFT); +} + +/** + * @brief Read FTU module reload interrupt enable + * + * @param pFtu the base address of the FTU instance + * @return reload interrupt enable + */ +LOCAL_INLINE uint8_t FTU_HWA_ReadReloadIntrEnable(FTU_Type *pFtu) +{ + return (uint8_t)((pFtu->SC & (uint32_t)FTU_SC_RIE_MASK) >> FTU_SC_RIE_SHIFT); +} + +/** + * @brief Read FTU channel interrupt flag + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + * @return FTU channel interrupt flag + */ +LOCAL_INLINE bool FTU_HWA_ReadChannelInterruptFlag(FTU_Type *pFtu, uint8_t u8Channel) +{ + return (0u != (pFtu->CONTROLS[u8Channel].CSCn & (uint32_t)FTU_CSC_CHF_MASK)); +} + +/** + * @brief Configure the channel output mode + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + * @param eMode output mode of the selected channel. + */ +LOCAL_INLINE void FTU_HWA_ConfigTrigOutputMode(FTU_Type *pFtu, uint8_t u8Channel, FTU_TrigOutputModeType eMode) +{ + pFtu->CONTROLS[u8Channel].CSCn &= ~(uint32_t)FTU_CSC_TRIGMODE_MASK; + pFtu->CONTROLS[u8Channel].CSCn |= (uint32_t)FTU_CSC_TRIGMODE(eMode); +} + +/** + * @brief Select fault disable channel output delay value + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + * @param eSelection Fault disable channel output delay value selection. + */ +LOCAL_INLINE void FTU_HWA_SelectFaultDelay(FTU_Type *pFtu, uint8_t u8Channel, FTU_FaultDisableDelayType eSelection) +{ + pFtu->CONTROLS[u8Channel].CSCn &= ~(uint32_t)FTU_CSC_FDLYSEL_MASK; + pFtu->CONTROLS[u8Channel].CSCn |= (uint32_t)FTU_CSC_FDLYSEL(eSelection); +} + +/** + * @brief Read FTU channel interrupt enable flag + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + * @return FTU channel interrupt flag + */ +LOCAL_INLINE uint8_t FTU_HWA_ReadChannelInterruptEnableFlag(FTU_Type *pFtu, uint8_t u8Channel) +{ + return (uint8_t)((pFtu->CONTROLS[u8Channel].CSCn & (uint32_t)FTU_CSC_CHIE_MASK) >> FTU_CSC_CHIE_SHIFT); +} + +/** + * @brief Read FTU module fault(n) flag + * + * @param pFtu the base address of the FTU instance + * @return FTU fault flag + */ +LOCAL_INLINE uint32_t FTU_HWA_ReadModuleFaultFlag(FTU_Type *pFtu) +{ + return (uint32_t)(pFtu->FMS & (uint32_t)0xFU); +} + +/** + * @brief Read FTU module fault interrupt enable + * + * @param pFtu the base address of the FTU instance + * @return FTU fault interrupt enable + */ +LOCAL_INLINE uint8_t FTU_HWA_ReadFaultIntrEnable(FTU_Type *pFtu) +{ + return (uint8_t)((pFtu->MODE & (uint32_t)FTU_MODE_FAULTIE_MASK) >> FTU_MODE_FAULTIE_SHIFT); +} + +/** + * @brief Read FTU module fault detection flag + * + * @param pFtu the base address of the FTU instance + * @return FTU fault detection flag + */ +LOCAL_INLINE uint8_t FTU_HWA_ReadModuleFaultDetectionFlag(FTU_Type *pFtu) +{ + return (uint8_t)((pFtu->FMS & (uint32_t)FTU_FMS_FAULTF_MASK) >> FTU_FMS_FAULTF_SHIFT); +} + +/** + * @brief Enable FTU module channel(n) output + * + * @param pFtu the base address of the FTU instance + * @param u8ChannelMask 0-7 bit indicate 0-7 channel + */ +LOCAL_INLINE void FTU_HWA_EnableChannelsOutput(FTU_Type *pFtu, uint8_t u8ChannelMask) +{ + pFtu->SC |= (uint32_t)FTU_SC_CHNOUTEN(u8ChannelMask); +} + +/** + * @brief Get cpwm mode of the FTU module + * + * @param pFtu the base address of the FTU instance + * @return cpwm mode bit value of the FTU module + */ +LOCAL_INLINE uint8_t FTU_HWA_GetModuleCpwmMode(FTU_Type *pFtu) +{ + return (uint8_t)((pFtu->SC & (uint32_t)FTU_SC_CPWMS_MASK) >> FTU_SC_CPWMS_SHIFT); +} + +/** + * @brief Enable FTU module cpwm mode + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableModuleCpwmMode(FTU_Type *pFtu) +{ + pFtu->SC |= (uint32_t)FTU_SC_CPWMS_MASK; +} + +/** + * @brief Disable FTU module cpwm mode + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableModuleCpwmMode(FTU_Type *pFtu) +{ + pFtu->SC &= ~(uint32_t)FTU_SC_CPWMS_MASK; +} + +/** + * @brief Set FTU module filter prescale + * + * @param pFtu the base address of the FTU instance + * @param eFilterPs FTU clock filter prescaler enumeration + */ +LOCAL_INLINE void FTU_HWA_ConfigModuleFilterPrescale(FTU_Type *pFtu, FTU_FilterPrescalerType eFilterPs) +{ + pFtu->SC &= ~(uint32_t)FTU_SC_FLTPS_MASK; + pFtu->SC |= FTU_SC_FLTPS(eFilterPs); +} + +/** + * @brief Selects the external clock as the FTU function clock + * + * @param pFtu the base address of the FTU instance + * @param eTclk FTU external clock enumeration + */ +LOCAL_INLINE void FTU_HWA_ConfigExternalClkSrc(FTU_Type *pFtu, FTU_TclkSelType eTclk) +{ + pFtu->SC &= ~(uint32_t)FTU_SC_TCKSEL_MASK; + pFtu->SC |= FTU_SC_TCKSEL(eTclk); +} + +LOCAL_INLINE void FTU_HWA_ConfigChannelMode(FTU_Type *pFtu, uint8_t u8Channel, FTU_ChannelModeType eMode) +{ + pFtu->CONTROLS[u8Channel].CSCn &= ~(uint32_t)(FTU_CSC_MSB_MASK | FTU_CSC_MSA_MASK); + pFtu->CONTROLS[u8Channel].CSCn |= (eMode << FTU_CSC_MSA_SHIFT) & (uint32_t)(FTU_CSC_MSB_MASK | FTU_CSC_MSA_MASK); +} + +LOCAL_INLINE void FTU_HWA_ConfigChannelEdgeLevel(FTU_Type *pFtu, uint8_t u8Channel, FTU_ChannelEdgeLevelType eEdgeLevel) +{ + pFtu->CONTROLS[u8Channel].CSCn &= ~(uint32_t)(FTU_CSC_ELSB_MASK | FTU_CSC_ELSA_MASK); + pFtu->CONTROLS[u8Channel].CSCn |= (eEdgeLevel << FTU_CSC_ELSA_SHIFT) & (uint32_t)(FTU_CSC_ELSB_MASK | FTU_CSC_ELSA_MASK); +} + +LOCAL_INLINE uint8_t FTU_HWA_GetEdgeNumberCount(FTU_Type *pFtu, uint8_t u8Channel) +{ + return (uint8_t)((pFtu->CONTROLS[u8Channel].CSCn & FTU_CSC_ICM_ICEXP_NUM_ICM_ECNT_MASK) >> FTU_CSC_ICM_ICEXP_NUM_ICM_ECNT_SHIFT); +} + +LOCAL_INLINE void FTU_HWA_ConfigEdgeNumber(FTU_Type *pFtu, uint8_t u8Channel, uint8_t u8EdgeNumber) +{ + pFtu->CONTROLS[u8Channel].CSCn &= (uint32_t)~FTU_CSC_ICM_ICEXP_NUM_ICM_ECNT_MASK; + pFtu->CONTROLS[u8Channel].CSCn |= FTU_CSC_ICM_ICEXP_NUM_ICM_ECNT(u8EdgeNumber); +} + +/** + * @brief Re-start measurement when in single mode + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + */ +LOCAL_INLINE void FTU_HWA_SingleMeasurement(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CONTROLS[u8Channel].CSCn |= (uint32_t)FTU_CSC_ICM_SINGLE_MASK; +} +/** + * @brief Set the measurement channel to continuous mode + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + */ +LOCAL_INLINE void FTU_HWA_EnableMeasureContinous(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CONTROLS[u8Channel].CSCn |= (uint32_t)FTU_CSC_ICM_CONT_MASK; +} +/** + * @brief Set the measurement channel to single mode + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + */ +LOCAL_INLINE void FTU_HWA_DisableMeasureContinous(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CONTROLS[u8Channel].CSCn &= ~(uint32_t)FTU_CSC_ICM_CONT_MASK; +} +/** + * @brief Set the channel starts measuring after the first edge is detected + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + */ +LOCAL_INLINE void FTU_HWA_EnableMeasureStartImmd(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CONTROLS[u8Channel].CSCn |= (uint32_t)FTU_CSC_ICM_START_MASK; +} + +LOCAL_INLINE void FTU_HWA_ConfigInputCaptureMeasureMode(FTU_Type *pFtu, uint8_t u8Channel, FTU_MeasurementModeType eMode) +{ + pFtu->CONTROLS[u8Channel].CSCn &= ~(uint32_t)FTU_CSC_ICM_MODE_MASK; + pFtu->CONTROLS[u8Channel].CSCn |= FTU_CSC_ICM_MODE(eMode); +} + +/** + * @brief Set the measurement starts immediately after activating the channel + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + */ +LOCAL_INLINE void FTU_HWA_DisableMeasureStartImmd(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CONTROLS[u8Channel].CSCn &= ~(uint32_t)FTU_CSC_ICM_START_MASK; +} + +/** + * @brief Get channel measure mode + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel + * @return measure mode + */ +LOCAL_INLINE FTU_MeasurementModeType FTU_HWA_GetMeasureMode(FTU_Type *pFtu, uint8_t u8Channel) +{ + return (FTU_MeasurementModeType)((pFtu->CONTROLS[u8Channel].CSCn & FTU_CSC_ICM_MODE_MASK) >> FTU_CSC_ICM_MODE_SHIFT); +} + +/** + * @brief Configure Edge-Aligned pwm mode channel to High-true pulses(clear output on match) + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + */ +LOCAL_INLINE void FTU_HWA_SetChannelEpwmHighTrue(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CONTROLS[u8Channel].CSCn &= ~(uint32_t)FTU_CSC_ELSA_MASK; + pFtu->CONTROLS[u8Channel].CSCn |= (uint32_t)(FTU_CSC_MSB_MASK | FTU_CSC_ELSB_MASK); +} + +/** + * @brief Configure Edge-Aligned pwm mode channel to Low-true pulses(set output on match) + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + */ +LOCAL_INLINE void FTU_HWA_SetChannelEpwmLowTrue(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CONTROLS[u8Channel].CSCn |= (uint32_t)(FTU_CSC_MSB_MASK | FTU_CSC_ELSA_MASK); +} + +/** + * @brief Configure pwm link mode channel + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + */ +LOCAL_INLINE void FTU_HWA_ConfigChannelPwmLinkMode(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CONTROLS[u8Channel].CSCn &= ~(uint32_t)(FTU_CSC_ELSA_MASK | FTU_CSC_MSB_MASK | FTU_CSC_MSA_MASK); + pFtu->CONTROLS[u8Channel].CSCn |= (uint32_t)FTU_CSC_ELSB_MASK; +} + +/** + * @brief Enable FTU channel interrupt + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + */ +LOCAL_INLINE void FTU_HWA_EnableChannelInterrupt(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CONTROLS[u8Channel].CSCn |= (uint32_t)FTU_CSC_CHIE_MASK; +} + +/** + * @brief Set MODE[FTUEN], this field define different free running counter and synchronization behavior. + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_SetModuleUpdateRegBySync(FTU_Type *pFtu) +{ + pFtu->MODE |= (uint32_t)FTU_MODE_FTUEN_MASK; +} + +/** + * @brief Clear MODE[FTUEN], this field define different free running counter and synchronization behavior. + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_ClearModuleUpdateRegBySync(FTU_Type *pFtu) +{ + pFtu->MODE &= ~(uint32_t)FTU_MODE_FTUEN_MASK; +} + +/** + * @brief Enable FTU module fault interrupt + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableModuleFaultInterrupt(FTU_Type *pFtu) +{ + pFtu->MODE |= (uint32_t)FTU_MODE_FAULTIE_MASK; +} + + +/** + * @brief Enable FTU channel dma + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + */ +LOCAL_INLINE void FTU_HWA_EnableChannelDma(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CONTROLS[u8Channel].CSCn |= (uint32_t)FTU_CSC_DMA_MASK; +} + + +/** + * @brief Configure FTU module fault mode + * + * @param pFtu the base address of the FTU instance + * @param eMode Fault mode type + */ +LOCAL_INLINE void FTU_HWA_ConfigModuleFaultMode(FTU_Type *pFtu, FTU_FaultModeType eMode) +{ + pFtu->MODE &= ~(uint32_t)FTU_MODE_FAULTM_MASK; + pFtu->MODE |= FTU_MODE_FAULTM(eMode); +} + +/** + * @brief Enable synchronization hardware trigger 0 + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableTrigger0Sync(FTU_Type *pFtu) +{ + pFtu->SYNC |= (uint32_t)FTU_SYNC_TRIG0_MASK; +} + +/** + * @brief Enable synchronization hardware trigger 1 + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableTrigger1Sync(FTU_Type *pFtu) +{ + pFtu->SYNC |= (uint32_t)FTU_SYNC_TRIG1_MASK; +} + +/** + * @brief Enable synchronization hardware trigger 2 + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableTrigger2Sync(FTU_Type *pFtu) +{ + pFtu->SYNC |= (uint32_t)FTU_SYNC_TRIG2_MASK; +} + +/** + * @brief Enable FTU module output mask synchronization + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableOutputMaskBySync(FTU_Type *pFtu) +{ + pFtu->SYNC |= (uint32_t)FTU_SYNC_SYNCHOM_MASK; +} + +/** + * @brief Disable FTU module output mask synchronization + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableOutputMaskBySync(FTU_Type *pFtu) +{ + pFtu->SYNC &= ~(uint32_t)FTU_SYNC_SYNCHOM_MASK; +} + +/** + * @brief Generate FTU software trigger + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_GenerateSwSync(FTU_Type *pFtu) +{ + pFtu->SYNC |= (uint32_t)FTU_SYNC_SWSYNC_MASK; +} + +/** + * @brief Configure FTU trigger mode + * + * @param pFtu the base address of the FTU instance + * @param eTrigMode Trigger mode type + */ +LOCAL_INLINE void FTU_HWA_ConfigTrigMode(FTU_Type *pFtu, FTU_TrigModeType eTrigMode) +{ + pFtu->SYNCONF &= ~(uint32_t)FTU_SYNCONF_HWTRIGMODE_MASK; + pFtu->SYNCONF |= (uint32_t)FTU_SYNCONF_HWTRIGMODE(eTrigMode); +} + +/** + * @brief Enable channel(n/n+1) deadtime functionality + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + */ +LOCAL_INLINE void FTU_HWA_EnableChannelDeadtime(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CHCTRL |= FTU_CHCTRL_DEADTIME_CHANNEL(u8Channel); +} + +/** + * @brief Enable channel(n/n+1) complement functionality + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + */ +LOCAL_INLINE void FTU_HWA_EnableChannelComplement(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CHCTRL |= FTU_CHCTRL_COMPLEMENT_CHANNEL(u8Channel); +} + +/** + * @brief Enable channel(n/n+1) synchronization functionality + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + */ +LOCAL_INLINE void FTU_HWA_EnableChannelSync(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CHCTRL |= FTU_CHCTRL_SYNCEN_CHANNEL(u8Channel); +} + +/** + * @brief Enable channel(n/n+1) Phase Shift Mode functionality + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + */ +LOCAL_INLINE void FTU_HWA_EnableChannelPhase(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CHCTRL |= FTU_CHCTRL_PHASE_CHANNEL(u8Channel); +} +/** + * @brief Disable channel(n/n+1) Phase Shift Mode functionality + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + */ +LOCAL_INLINE void FTU_HWA_DisableChannelPhase(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CHCTRL &= ~FTU_CHCTRL_PHASE_CHANNEL(u8Channel); +} +/** + * @brief Enable channel(n/n+1) Enhanced Phase Shift Mode functionality + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + */ +LOCAL_INLINE void FTU_HWA_EnableChannelEnhancedPhase(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CHCTRL |= FTU_CHCTRL_EPHASE_CHANNEL(u8Channel); +} +/** + * @brief Disable channel(n/n+1) Enhanced Phase Shift Mode functionality + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + */ +LOCAL_INLINE void FTU_HWA_DisableChannelEnhancedPhase(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CHCTRL &= ~FTU_CHCTRL_EPHASE_CHANNEL(u8Channel); +} + +/** + * @brief Enable channel(n/n+1) fault functionality + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + */ +LOCAL_INLINE void FTU_HWA_EnableChannelFault(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CHCTRL |= FTU_CHCTRL_FAULT_CHANNEL(u8Channel); +} + +/** + * @brief Enable channel trigger out + * + * @param pFtu the base address of the FTU instance + * @param u8ChannelMask FTU channel mask, bit 0-7 indicate channel 0-7 + */ +LOCAL_INLINE void FTU_HWA_EnableChannelTriggerOut(FTU_Type *pFtu, uint8_t u8ChannelMask) +{ + + uint32_t u32TempRegValue = FTU_TRIGCONF_CH7TRIG(((uint32_t)u8ChannelMask >> 7u) & 1u) | + FTU_TRIGCONF_CH6TRIG(((uint32_t)u8ChannelMask >> 6u) & 1u) | + FTU_TRIGCONF_CH5TRIG(((uint32_t)u8ChannelMask >> 5u) & 1u) | + FTU_TRIGCONF_CH4TRIG(((uint32_t)u8ChannelMask >> 4u) & 1u) | + FTU_TRIGCONF_CH3TRIG(((uint32_t)u8ChannelMask >> 3u) & 1u) | + FTU_TRIGCONF_CH2TRIG(((uint32_t)u8ChannelMask >> 2u) & 1u) | + FTU_TRIGCONF_CH1TRIG(((uint32_t)u8ChannelMask >> 1u) & 1u) | + FTU_TRIGCONF_CH0TRIG((uint32_t)u8ChannelMask & 1u); + pFtu->TRIGCONF |= u32TempRegValue; +} + +/** + * @brief Disable channel trigger out + * + * @param pFtu the base address of the FTU instance + * @param u8ChannelMask FTU channel mask, bit 0-7 indicate channel 0-7 + */ +LOCAL_INLINE void FTU_HWA_DisableChannelTriggerOut(FTU_Type *pFtu, uint8_t u8ChannelMask) +{ + uint32_t u32TempRegValue = FTU_TRIGCONF_CH7TRIG(((uint32_t)u8ChannelMask >> 7u) & 1u) | + FTU_TRIGCONF_CH6TRIG(((uint32_t)u8ChannelMask >> 6u) & 1u) | + FTU_TRIGCONF_CH5TRIG(((uint32_t)u8ChannelMask >> 5u) & 1u) | + FTU_TRIGCONF_CH4TRIG(((uint32_t)u8ChannelMask >> 4u) & 1u) | + FTU_TRIGCONF_CH3TRIG(((uint32_t)u8ChannelMask >> 3u) & 1u) | + FTU_TRIGCONF_CH2TRIG(((uint32_t)u8ChannelMask >> 2u) & 1u) | + FTU_TRIGCONF_CH1TRIG(((uint32_t)u8ChannelMask >> 1u) & 1u) | + FTU_TRIGCONF_CH0TRIG((uint32_t)u8ChannelMask & 1u); + pFtu->TRIGCONF &= ~u32TempRegValue; +} + +/** + * @brief clear the channel trigger flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_ClearChannelTriggerFlag(FTU_Type *pFtu) +{ + pFtu->TRIGCONF &= ~FTU_TRIGCONF_TRIGF_MASK; +} + +/** + * @brief Enable reload trigger + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableReloadTrigger(FTU_Type *pFtu) +{ + pFtu->TRIGCONF |= (uint32_t)FTU_TRIGCONF_RELOADTRIGEN_MASK; +} + +/** + * @brief Set channel polarity + * + * @param pFtu the base address of the FTU instance + * @param u8Mask FTU channel mask, bit 0-7 indicate channel 0-7 + */ +LOCAL_INLINE void FTU_HWA_SetChannelPolarity(FTU_Type *pFtu, uint8_t u8Mask) +{ + pFtu->POL |= FTU_POL_POLN(u8Mask); +} + +/** + * @brief Set FTU module outmask + * + * @param pFtu the base address of the FTU instance + * @param u8Channel Bit of channel indicate channel number, range: 0~7 bit + */ +LOCAL_INLINE void FTU_HWA_ConfigModuleOutmask(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->OUTMASK &= ~(uint32_t)0xFFU; + pFtu->OUTMASK |= (uint32_t)u8Channel & (uint32_t)0xFFU; +} + +/** + * @brief Set channel filter value + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-3 + * @param u8FilterVal FTU filter value + */ +LOCAL_INLINE void FTU_HWA_ConfigChannelFilterValue(FTU_Type *pFtu, uint8_t u8Channel, uint8_t u8FilterVal) +{ + pFtu->FILTER &= ~((uint32_t)0xFu << ((uint32_t)u8Channel << 2U)); + pFtu->FILTER |= ((uint32_t)u8FilterVal << ((uint32_t)u8Channel << 2U)); +} + +/** + * @brief Configure quadrature mode + * + * @param pFtu the base address of the FTU instance + * @param eMode FTU quadrature mode + */ +LOCAL_INLINE void FTU_HWA_ConfigQuadratureMode(FTU_Type *pFtu, FTU_QuadratureModeType eMode) +{ + pFtu->QDCTRL &= ~(uint32_t)FTU_QDCTRL_QUADMODE_MASK; + pFtu->QDCTRL |= (uint32_t)FTU_QDCTRL_QUADMODE(eMode); +} + +/** + * @brief Configure FTU Counter Direction In Quadrature Decoder Mode + * + * @param pFtu the base address of the FTU instance + * @param eDir the counting direction + */ +LOCAL_INLINE void FTU_HWA_ConfigQuadDirection(FTU_Type *pFtu, FTU_QuadratureDirectionType eDir) +{ + pFtu->QDCTRL &= ~(uint32_t)FTU_QDCTRL_QUADIR_MASK; + pFtu->QDCTRL |= (uint32_t)FTU_QDCTRL_QUADIR(eDir); +} + +/** + * @brief Configure Timer Overflow Direction In Quadrature Decoder Mode + * + * @param pFtu the base address of the FTU instance + * @param eDir Indicates if the TOF bit was set on the top or the bottom of counting + */ +LOCAL_INLINE void FTU_HWA_ConfigTimerOverflowDir(FTU_Type *pFtu, FTU_TimerOverflowDirectionType eDir) +{ + pFtu->QDCTRL &= ~(uint32_t)FTU_QDCTRL_TOFDIR_MASK; + pFtu->QDCTRL |= (uint32_t)FTU_QDCTRL_TOFDIR(eDir); +} + +/** + * @brief inverted polarity of phase B input signal + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnablePhbInv(FTU_Type *pFtu) +{ + pFtu->QDCTRL |= (uint32_t)FTU_QDCTRL_PHBPOL_MASK; +} + +/** + * @brief do not inverted polarity of phase B input signal + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisablePhbInv(FTU_Type *pFtu) +{ + pFtu->QDCTRL &= ~(uint32_t)FTU_QDCTRL_PHBPOL_MASK; +} + +/** + * @brief inverted polarity of phase A input signal + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnablePhaInv(FTU_Type *pFtu) +{ + pFtu->QDCTRL |= (uint32_t)FTU_QDCTRL_PHAPOL_MASK; +} + +/** + * @brief do not inverted polarity of phase B input signal + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisablePhaInv(FTU_Type *pFtu) +{ + pFtu->QDCTRL &= ~(uint32_t)FTU_QDCTRL_PHAPOL_MASK; +} + +/** + * @brief Enable phase A glitch filter + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnablePhaGlitchFilter(FTU_Type *pFtu) +{ + pFtu->QDCTRL |= (uint32_t)FTU_QDCTRL_PHAGFEN_MASK; +} + +/** + * @brief Disable phase A glitch filter + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisablePhaGlitchFilter(FTU_Type *pFtu) +{ + pFtu->QDCTRL &= ~(uint32_t)FTU_QDCTRL_PHAGFEN_MASK; +} + +/** + * @brief Enable phase B glitch filter + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnablePhbGlitchFilter(FTU_Type *pFtu) +{ + pFtu->QDCTRL |= (uint32_t)FTU_QDCTRL_PHBGFEN_MASK; +} + +/** + * @brief Disable phase B glitch filter + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisablePhbGlitchFilter(FTU_Type *pFtu) +{ + pFtu->QDCTRL &= ~(uint32_t)FTU_QDCTRL_PHBGFEN_MASK; +} + +/** + * @brief Enable FTU module quadrature mode + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableQuadratureMode(FTU_Type *pFtu) +{ + pFtu->QDCTRL |= (uint32_t)FTU_QDCTRL_QUADEN_MASK; +} + +/** + * @brief Disable FTU module quadrature mode + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableQuadratureMode(FTU_Type *pFtu) +{ + pFtu->QDCTRL &= ~(uint32_t)FTU_QDCTRL_QUADEN_MASK; +} + +/** + * @brief Configure FTU module debug mode + * + * @param pFtu the base address of the FTU instance + * @param eDbgMode debug mode enumeration + */ +LOCAL_INLINE void FTU_HWA_ConfigModuleDebugMode(FTU_Type *pFtu, FTU_DebugModeType eDbgMode) +{ + pFtu->CONF &= ~(uint32_t)FTU_CONF_DBG_MASK; + pFtu->CONF |= FTU_CONF_DBG(eDbgMode); +} + +/** + * @brief Set FTU module clock source + * + * @param pFtu the base address of the FTU instance + * @param eClkSrc FTU module clock source type + */ +LOCAL_INLINE void FTU_HWA_ConfigModuleClkSrc(FTU_Type *pFtu, FTU_ModuleClkSrcType eClkSrc) +{ + pFtu->SC &= ~(uint32_t)FTU_SC_CLKS_MASK; + pFtu->SC |= FTU_SC_CLKS(eClkSrc); +} + +/** + * @brief Clear FTU module overflow flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_ClearOverflowFlag(FTU_Type *pFtu) +{ + pFtu->SC &= ~(uint32_t)FTU_SC_TOF_MASK; +} + +/** + * @brief Clear FTU module reload flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_ClearReloadFlag(FTU_Type *pFtu) +{ + pFtu->SC &= ~(uint32_t)FTU_SC_RF_MASK; +} + +/** + * @brief Enable FTU module interrupt + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_EnableOverflowInterrupt(FTU_Type *pFtu) +{ + pFtu->SC |= (uint32_t)FTU_SC_TOIE_MASK; +} + +/** + * @brief Disable FTU module overflow interrupt + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableOverflowInterrupt(FTU_Type *pFtu) +{ + pFtu->SC &= ~(uint32_t)FTU_SC_TOIE_MASK; +} + +/** + * @brief Clear FTU channel interrupt flag + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + */ +LOCAL_INLINE void FTU_HWA_ClearChannelInterruptFlag(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CONTROLS[u8Channel].CSCn &= ~(uint32_t)FTU_CSC_CHF_MASK; +} + +/** + * @brief Disable channel interrupt + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel number, range is 0-7. + */ +LOCAL_INLINE void FTU_HWA_DisableChannelInterrupt(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CONTROLS[u8Channel].CSCn &= ~(uint32_t)FTU_CSC_CHIE_MASK; +} + +/** + * @brief Disable write protection + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableWriteProtection(FTU_Type *pFtu) +{ + pFtu->MODE |= (uint32_t)FTU_MODE_WPDIS_MASK; +} + +/** + * @brief Disable FTU module fault interrupt + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableModuleFaultInterrupt(FTU_Type *pFtu) +{ + pFtu->MODE &= ~(uint32_t)FTU_MODE_FAULTIE_MASK; +} + +/** + * @brief Disable synchronization hardware trigger 0 + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableTrigger0Sync(FTU_Type *pFtu) +{ + pFtu->SYNC &= ~(uint32_t)FTU_SYNC_TRIG0_MASK; +} + +/** + * @brief Disable synchronization hardware trigger 1 + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableTrigger1Sync(FTU_Type *pFtu) +{ + pFtu->SYNC &= ~(uint32_t)FTU_SYNC_TRIG1_MASK; +} + +/** + * @brief Disable synchronization hardware trigger 2 + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableTrigger2Sync(FTU_Type *pFtu) +{ + pFtu->SYNC &= ~(uint32_t)FTU_SYNC_TRIG2_MASK; +} + +/** + * @brief Disable generate FTU software trigger + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableGenerateSwSync(FTU_Type *pFtu) +{ + pFtu->SYNC &= ~(uint32_t)FTU_SYNC_SWSYNC_MASK; +} + +/** + * @brief Disable reload trigger + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_DisableReloadTrigger(FTU_Type *pFtu) +{ + pFtu->TRIGCONF &= ~(uint32_t)FTU_TRIGCONF_RELOADTRIGEN_MASK; +} + +/** + * @brief Disable channel(n/n+1) deadtime functionality + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + */ +LOCAL_INLINE void FTU_HWA_DisableChannelDeadtime(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CHCTRL &= ~FTU_CHCTRL_DEADTIME_CHANNEL(u8Channel); +} + +/** + * @brief Disable channel(n/n+1) complement functionality + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + */ +LOCAL_INLINE void FTU_HWA_DisableChannelComplement(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CHCTRL &= ~FTU_CHCTRL_COMPLEMENT_CHANNEL(u8Channel); +} + +/** + * @brief Disable channel(n/n+1) synchronization functionality + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + */ +LOCAL_INLINE void FTU_HWA_DisableChannelSync(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CHCTRL &= ~FTU_CHCTRL_SYNCEN_CHANNEL(u8Channel); +} + +/** + * @brief Disable channel(n/n+1) fault functionality + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel number, range is 0-7 + */ +LOCAL_INLINE void FTU_HWA_DisableChannelFault(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->CHCTRL &= ~FTU_CHCTRL_FAULT_CHANNEL(u8Channel); +} + +/** + * @brief Clear channel polarity + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel, bit 0-7 indicate channel 0-7 + */ +LOCAL_INLINE void FTU_HWA_ClearChannelPolarity(FTU_Type *pFtu, uint8_t u8Channel) +{ + pFtu->POL &= ~FTU_POL_POLN(u8Channel); +} + +/** + * @brief Get channel polarity + * + * @param pFtu the base address of the FTU instance + * @param u8Channel FTU channel, bit 0-7 indicate channel 0-7 + * @return polarity of the channels + */ +LOCAL_INLINE uint32_t FTU_HWA_GetChannelPolarity(FTU_Type *pFtu, uint8_t u8Channel) +{ + return pFtu->POL & FTU_POL_POLN(u8Channel); +} + +/** + * @brief Clear FTU module fault flag + * + * @param pFtu the base address of the FTU instance + * @param u8Flag bit 0-3 indicate fault flag 0-3. + */ +LOCAL_INLINE void FTU_HWA_ClearModuleFaultFlag(FTU_Type *pFtu, uint8_t u8Flag) +{ + pFtu->FMS &= ~(uint32_t)((uint32_t)u8Flag & 0xFu); +} + +/** + * @brief Clear FTU global fault flag + * + * @param pFtu the base address of the FTU instance + */ +LOCAL_INLINE void FTU_HWA_ClearGlobalFaultFlag(FTU_Type *pFtu) +{ + pFtu->FMS &= ~(uint32_t)FTU_FMS_FAULTF_MASK; +} + +#endif /* #ifndef _HWA_FTU_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_gpio.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_gpio.h new file mode 100644 index 0000000..ca7629e --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_gpio.h @@ -0,0 +1,245 @@ +/** + * @file HwA_gpio.h + * @author Flagchip + * @brief FC7xxx GPIO hardware access layer + * @version 0.1.0 + * @date 2023-02-13 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2022-11-18 Flagchip071 N/A First version for FC7xxx + ******************************************************************************** */ + +#ifndef _HWA_GPIO_H_ +#define _HWA_GPIO_H_ + +#include "device_header.h" + +/** @brief GPIO initialization level */ +typedef enum +{ + GPIO_LOW = 0U, + GPIO_HIGH = 1U +} GPIO_PinLevelType; + + +/** + * @brief Set port data output, port output can set 1 or 0 + * + * @param pGpio Gpio instance + * @param u32Value Written value + */ +LOCAL_INLINE void GPIO_HWA_ConfigPortDataOutput(GPIO_Type *pGpio, uint32_t u32Value) +{ + pGpio->PDOR = u32Value; +} + +/** + * @brief Set pin data output, pin output can set 1 or 0 + * + * @param pGpio Gpio instance + * @param u32Pin Pin mask + * @param ePinLevel Pin level + */ +LOCAL_INLINE void GPIO_HWA_ConfigPinDataOutput(GPIO_Type *pGpio, uint32_t u32Pin, GPIO_PinLevelType ePinLevel) +{ + if (GPIO_HIGH == ePinLevel) + { + pGpio->PDOR |= GPIO_PDOR_PDO(u32Pin); + } + else + { + pGpio->PDOR &= ~GPIO_PDOR_PDO(u32Pin); + } +} + +/** + * @brief Set port output to 1 + * + * @param pGpio Gpio instance + * @param u32Value Written value + */ +LOCAL_INLINE void GPIO_HWA_SetPortOutput(GPIO_Type *pGpio, uint32_t u32Value) +{ + pGpio->PSOR |= u32Value; +} + +/** + * @brief Set port output to 0 + * + * @param pGpio Gpio instance + * @param u32Value Written value + */ +LOCAL_INLINE void GPIO_HWA_ClearPortOutput(GPIO_Type *pGpio, uint32_t u32Value) +{ + pGpio->PCOR |= u32Value; +} + +/** + * @brief Toggle port output + * + * @param pGpio Gpio instance + * @param u32Value Written value + */ +LOCAL_INLINE void GPIO_HWA_TogglePort(GPIO_Type *pGpio, uint32_t u32Value) +{ + pGpio->PTOR = u32Value; +} + +/** + * @brief Set port direction + * + * @param pGpio Gpio instance + * @param u32Value Written value + */ +LOCAL_INLINE void GPIO_HWA_SetPortDirection(GPIO_Type *pGpio, uint32_t u32Value) +{ + pGpio->PDDR = u32Value; +} + +/** + * @brief Set port input disable + * + * @param pGpio Gpio instance + * @param u32Value Written value + */ +LOCAL_INLINE void GPIO_HWA_SetPortInputDisable(GPIO_Type *pGpio, uint32_t u32Value) +{ + pGpio->PIDR = u32Value; +} + + +/** + * @brief Read port data output + * + * @param pGpio Gpio instance + * @return PDOR register value + */ +LOCAL_INLINE uint32_t GPIO_HWA_ReadPortDataOutput(GPIO_Type *pGpio) +{ + return pGpio->PDOR; +} + +/** + * @brief Read port data input, this register indicate data on pad. + * + * @param pGpio Gpio instance + * @return PDIR register value + */ +LOCAL_INLINE uint32_t GPIO_HWA_ReadPortDataInput(GPIO_Type *pGpio) +{ + return pGpio->PDIR; +} + + +/** + * @brief Set pin data output, pin output can set 1 or 0 + * + * @param pGpio Gpio instance + * @param u8Pin Pin number + */ +LOCAL_INLINE void GPIO_HWA_SetPinDataOutput(GPIO_Type *pGpio, uint8_t u8Pin) +{ + pGpio->PDOR |= (uint32_t)1 << u8Pin; +} + +/** + * @brief Set pin output to 1 + * + * @param pGpio Gpio instance + * @param u8Pin Pin number + */ +LOCAL_INLINE void GPIO_HWA_SetPinOutput(GPIO_Type *pGpio, uint8_t u8Pin) +{ + pGpio->PSOR |= (uint32_t)1 << u8Pin; +} + +/** + * @brief Set pin output to 0 + * + * @param pGpio Gpio instance + * @param u8Pin Pin number + */ +LOCAL_INLINE void GPIO_HWA_ClearPinOutput(GPIO_Type *pGpio, uint8_t u8Pin) +{ + pGpio->PCOR |= (uint32_t)1 << u8Pin; +} + +/** + * @brief Toggle pin + * + * @param pGpio Gpio instance + * @param u8Pin Pin number + */ +LOCAL_INLINE void GPIO_HWA_TogglePin(GPIO_Type *pGpio, uint8_t u8Pin) +{ + pGpio->PTOR |= (uint32_t)1 << u8Pin; +} + +/** + * @brief Set pin direction + * + * @param pGpio Gpio instance + * @param u8Pin Pin number + */ +LOCAL_INLINE void GPIO_HWA_SetPinDirection(GPIO_Type *pGpio, uint8_t u8Pin) +{ + pGpio->PDDR |= (uint32_t)1 << u8Pin; +} + +/** + * @brief Set pin input disable + * + * @param pGpio Gpio instance + * @param u8Pin Pin number + */ +LOCAL_INLINE void GPIO_HWA_SetPinInputDisable(GPIO_Type *pGpio, uint8_t u8Pin) +{ + pGpio->PIDR |= (uint32_t)1 << u8Pin; +} + + +/** + * @brief Clear pin data output + * + * @param pGpio Gpio instance + * @param u8Pin Pin number + */ +LOCAL_INLINE void GPIO_HWA_ClearPinDataOutput(GPIO_Type *pGpio, uint8_t u8Pin) +{ + pGpio->PDOR &= ~((uint32_t)1 << u8Pin); +} + +/** + * @brief Clear pin direction + * + * @param pGpio Gpio instance + * @param u8Pin Pin number + */ +LOCAL_INLINE void GPIO_HWA_ClearPinDirection(GPIO_Type *pGpio, uint8_t u8Pin) +{ + pGpio->PDDR &= ~((uint32_t)1 << u8Pin); +} + +/** + * @brief Clear pin input disable + * + * @param pGpio Gpio instance + * @param u8Pin Pin number + */ +LOCAL_INLINE void GPIO_HWA_ClearPinInputDisable(GPIO_Type *pGpio, uint8_t u8Pin) +{ + pGpio->PIDR &= ~((uint32_t)1 << u8Pin); +} + + + + +#endif /* #ifndef _HWA_GPIO_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_intm.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_intm.h new file mode 100644 index 0000000..5016a93 --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_intm.h @@ -0,0 +1,179 @@ +/** + * @file HwA_intm.h + * @author Flagchip + * @brief FC7240 INTM HWA driver type definition and API + * @version 0.1.0 + * @date 2024-01-10 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-10 Flagchip084 N/A FC7240 release version + ******************************************************************************** */ + +#ifndef _HWA_INTM_H_ +#define _HWA_INTM_H_ + +#include "device_header.h" + +typedef struct +{ + __IO uint32_t IRQSELR; /* INTM Interrupt Request Select Register*/ + __IO uint32_t LATR; /* INTM Latency Register */ + __IO uint32_t TMR; /* INTM Timer Register */ + __I uint32_t SR; /* INTM Status Register */ +} INTM_MonitorType, *INTM_MonitorMemMapPtr; + +/** + * @brief Enable the INTM. + * @param pIntm INTM instance. INTM instance. + * @param bEnable Enable the ITNM. + */ +LOCAL_INLINE void INTM_HWA_Enable(INTM_Type *const pIntm, bool bEnable) +{ + if (bEnable) + { + pIntm->ER = INTM_ER_EN_MASK; + } + else + { + pIntm->ER = 0U; + } +} + +/** + * @brief Get the instance of interrupt monitor. + * @param pIntm INTM instance. + * @param u8IrqMonitorIndex Interrupt monitor index. + * @return Monitor Instance. + */ +LOCAL_INLINE INTM_MonitorType *INTM_HWA_GetIrqMonitor(INTM_Type *const pIntm, uint8_t u8IrqMonitorIndex) +{ + return (INTM_MonitorType *)((uint32_t) & (pIntm->IRQSELR0) + (uint32_t)u8IrqMonitorIndex * 0x10U); +} + +/** + * @brief Set the interrupt acknowledge. + * @param pIntm INTM instance. + * @param u16IrqNum Interrupt number to be monitored. + */ +LOCAL_INLINE void INTM_HWA_SetIACKR(INTM_Type *const pIntm, uint16_t u16IrqNum) +{ + pIntm->IACKR = u16IrqNum; +} + +/** + * @brief Set which interrupt to be monoterd. + * @param pIntm INTM instance. + * @param u16IrqNum Interrupt number to be monitored. + */ +LOCAL_INLINE void INTM_HWA_SetIRQReqNum(INTM_MonitorType *const pIrqMon, uint16_t u16IrqNum) +{ + pIrqMon->IRQSELR = u16IrqNum; +} + +/** + * @brief Enable reset when interrupt delays overtime. + * @param pIrqMon Interrupt monitor instance. + * @param bEnable Enable reset. + */ +LOCAL_INLINE void INTM_HWA_EnableReset(INTM_MonitorType *const pIrqMon, bool bEnable) +{ + pIrqMon->IRQSELR = (pIrqMon->IRQSELR & ~INTM_IRQSELR_RSTE_MASK) | INTM_IRQSELR_RSTE(bEnable); +} + +/** + * @brief Enable interrupt when monitored interrupt delays overtime. + * @param pIrqMon Interrupt monitor instance. + * @param bEnable Enabel the interrupt. + */ +LOCAL_INLINE void INTM_HWA_EnableInterrupt(INTM_MonitorType *const pIrqMon, bool bEnable) +{ + pIrqMon->IRQSELR = (pIrqMon->IRQSELR & ~INTM_IRQSELR_INTE_MASK) | INTM_IRQSELR_INTE(bEnable); +} + +/** + * @brief Enable inactive mode. + * @param pIrqMon Interrupt monitor instance. + * @param bEnable Enable inactive mode. + */ +LOCAL_INLINE void INTM_HWA_EnableInactiveMode(INTM_MonitorType *const pIrqMon, bool bEnable) +{ + pIrqMon->IRQSELR = (pIrqMon->IRQSELR & ~INTM_IRQSELR_IACTE_MASK) | INTM_IRQSELR_IACTE(bEnable); + __asm volatile( + "dmb \n" + "ldr r8, [%[IRQSELR]] \n"/* Must Read IRQSELR after set. */ + : : [IRQSELR] "r"(&pIrqMon->IRQSELR) : "r8", "memory" + ); +} + +/** + * @brief Start the inactive mode. + * @param pIrqMon Interrupt monitor instance. + */ +LOCAL_INLINE void INTM_HWA_StartInactiveMode(INTM_MonitorType *const pIrqMon) +{ + pIrqMon->IRQSELR |= INTM_IRQSELR_IACTST_MASK; + __asm volatile( + "dmb \n" + "ldr r8, [%[IRQSELR]] \n"/* Must Read IRQSELR after set. */ + : : [IRQSELR] "r"(&pIrqMon->IRQSELR) : "r8", "memory" + ); +} + +/** + * @brief Stop the inactive mode. + * @param pIrqMon Interrupt monitor instance. + * @param bEnable + */ +LOCAL_INLINE void INTM_HWA_StopInactiveMode(INTM_MonitorType *const pIrqMon) +{ + pIrqMon->IRQSELR &= ~INTM_IRQSELR_IACTST_MASK; +} + +/** + * @brief Set the timeout value of interrupt. + * @param pIrqMon Interrupt monitor instance. + * @param u32Latency the timeout value of interrupt monitor. + */ +LOCAL_INLINE void INTM_HWA_SetLatency(INTM_MonitorType *const pIrqMon, uint32_t u32Latency) +{ + pIrqMon->LATR = u32Latency; +} + +/** + * @brief Get the value of timer. + * @param pIrqMon Interrupt monitor instance. + * @return Timer value + */ +LOCAL_INLINE uint32_t INTM_HWA_GetTimerCounter(INTM_MonitorType *const pIrqMon) +{ + return pIrqMon->TMR; +} + +/** + * @brief Set the value of timer. + * @param pIrqMon Interrupt monitor instance. + * @param u32Value The value to be set. + */ +LOCAL_INLINE void INTM_HWA_SetTimerCounter(INTM_MonitorType *const pIrqMon, uint32_t u32Value) +{ + pIrqMon->TMR = u32Value; +} + +/** + * @brief Read interrupt status. + * @param pIrqMon Interrupt monitor instance. + * @return Interrupt status. + */ +LOCAL_INLINE bool INTM_HWA_ReadStatus(INTM_MonitorType *const pIrqMon) +{ + return (pIrqMon->SR & INTM_SR_MASK) == INTM_SR_MASK ? true : false; +} + +#endif /*#ifndef _HWA_INTM_H_*/ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_ism.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_ism.h new file mode 100644 index 0000000..38eef1a --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_ism.h @@ -0,0 +1,645 @@ +/** + * @file HwA_ism.h + * @author Flagchip084 + * @brief FC7xxx ISM hardware access layer + * @version 0.2.0 + * @date 2023-02-13 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2022-11-18 Flagchip084 N/A First version for FC7xxx + * 0.2.0 2023-02-13 Flagchip084 N/A FC7xxx release version + ******************************************************************************** */ +#ifndef _HWA_ISM_H_ +#define _HWA_ISM_H_ + +#include "device_header.h" + +/** + * @addtogroup HwA_ism + * @{ + * + */ +/********* macros ************/ + +/********* Local typedef ************/ + +typedef struct +{ + __IO uint32_t FPC_STATUS; + __IO uint32_t FPC_CTRL; + __IO uint32_t FPC_CONFIG; + __IO uint32_t FPC_TIMER; +} FPC_Type, *FPC_MemMapPtr; + +typedef struct +{ + __IO uint32_t LAM_STATUS; + __IO uint32_t LAM_CTRL; + __IO uint32_t LAM_CONFIG; + __IO uint32_t LAM_CONTER; +} LAM_Type, *LAM_MemMapPtr; + +typedef enum +{ + ISM_FPC_DETECT_NO_FILTER = 0U, /*No filter mode. Copy input to SOUT directly, which is LAM input.*/ + ISM_FPC_DETECT_IMMI_FILTER = 1U, /*Immediate filter mode.*/ + ISM_FPC_DETECT_DELAY_MODE = 2U, /*Delay mode.*/ + ISM_FPC_DETECT_PRESCALER_MODE = 3U /*Prescaler mode.*/ +} ISM_FPC_EdgeDetectModeType; + +typedef enum +{ + ISM_FPC_DELAY_FIXED0 = 0U, /*Fixed delay mode.*/ + ISM_FPC_DELAY_FIXED1 = 1U, /*Fixed delay mode.*/ + ISM_FPC_DELAY_SMART_DELAY0 = 2U, /*Smart delay mode. The counter is decremented when a glitch happens.*/ + ISM_FPC_DELAY_SMART_DELAY1 = 3U /*Smart delay mode. The counter is reset when a glitch happens.*/ +} ISM_FPC_EdgeDelayModeType; + + +typedef enum +{ + ISM_LAM_EVT_WIN_NON_INVERT = 0U, /*Event window non-inverted.*/ + ISM_LAM_EVT_WIN_INVERT = 1U /*Event window inverted.*/ +} ISM_LAM_InvertEventWindowType; + +typedef enum +{ + ISM_LAM_NTR_CLEAR_NTR_GATE = 0U, /*Neither edge used to clear the event window counter. Neither edge used to gate event generation.*/ + ISM_LAM_POS_CLEAR_NTR_GATE = 1U, /*Positive edge used to clear the event window counter. Neither edge used to gate event generation.*/ + ISM_LAM_NEG_CLEAR_NTR_GATE = 2U, /*Negative edge used to clear the event window counter. Neither edge used to gate event generation.*/ + ISM_LAM_ETR_CLEAR_NTR_GATE = 3U, /*Either edge used to clear the event window counter. Neither edge used to gate event generation.*/ + ISM_LAM_NTR_CLEAR_POS_GATE = 4U, /*Neither edge used to clear the event window counter. Positive edge used to gate event generation.*/ + ISM_LAM_POS_CLEAR_POS_GATE = 5U, /*Positive edge used to clear the event window counter. Positive edge used to gate event generation.*/ + ISM_LAM_NEG_CLEAR_POS_GATE = 6U, /*Negative edge used to clear the event window counter. Positive edge used to gate event generation.*/ + ISM_LAM_ETR_CLEAR_POS_GATE = 7U, /*Either edge used to clear the event window counter. Positive edge used to gate event generation.*/ + ISM_LAM_NTR_CLEAR_NEG_GATE = 8U, /*Neither edge used to clear the event window counter. Negative edge used to gate event generation.*/ + ISM_LAM_POS_CLEAR_NEG_GATE = 9U, /*Positive edge used to clear the event window counter. Negative edge used to gate event generation.*/ + ISM_LAM_NEG_CLEAR_NEG_GATE = 10U, /*Negative edge used to clear the event window counter. Negative edge used to gate event generation.*/ + ISM_LAM_ETR_CLEAR_NEG_GATE = 11U, /*Either edge used to clear the event window counter. Negative edge used to gate event generation.*/ + ISM_LAM_NTR_CLEAR_ETR_GATE = 12U, /*Neither edge used to clear the event window counter. Either edge used to gate event generation.*/ + ISM_LAM_POS_CLEAR_ETR_GATE = 13U, /*Positive edge used to clear the event window counter. Either edge used to gate event generation.*/ + ISM_LAM_NEG_CLEAR_ETR_GATE = 14U, /*Negative edge used to clear the event window counter. Either edge used to gate event generation.*/ + ISM_LAM_ETR_CLEAR_ETR_GATE = 15U /*Either edge used to clear the event window counter. Either edge used to gate event generation.*/ +} ISM_LAM_EventWindowEdgeType; + +typedef enum +{ + ISM_LAM_EVT_WIN_SEL_REF = 0U, /*Event window generation is determined from the reference signal.*/ + ISM_LAM_EVT_WIN_SEL_MON = 1U /*Event window generation is determined from the monitor signal.*/ +} ISM_LAM_EventWindowSelectType; + +typedef enum +{ + ISM_LAM_RUN_FREE = 0U, /*Event window generation is free-running.*/ + ISM_LAM_RUN_GATED = 1U /*Event window generation is gated with the monitor or reference signal.*/ +} ISM_LAM_RunModeSelectType; + + +typedef enum +{ + ISM_LAM_SRC_FPC_MON = 0U, /* Monitor signal is sourced directly from FPC monitor channel.*/ + ISM_LAM_SRC_EXORD_FPC_REF = 1U /* Monitor signal is EXOR'd with FPC reference channel.*/ +} ISM_LAM_MonitorSourceType; + +typedef enum +{ + ISM_LAM_FPC_MON_NON_INVERT = 0U, /* Do not invert the monitor signal from FPC.*/ + ISM_LAM_FPC_MON_INVERT = 1U /* Invert the monitor signal from FPC.*/ +} ISM_LAM_InvertMonitorType; + +typedef enum +{ + ISM_LAM_FPC_REF_NON_INVERT = 0U, /* Do not invert the reference signal from FPC.*/ + ISM_LAM_FPC_REF_INVERT = 1U /* Invert the reference signal from FPC.*/ +} ISM_LAM_InvertReferenceType; + +/********* Local inline function ************/ + +/********* ISM Register interface ************/ + +/** + * @brief Get ISM ECM count + * + * @param pIsm ISM Instance + * @return ECM count + */ +LOCAL_INLINE uint8_t ISM_HWA_PARAM_ECMC(ISM_Type *const pIsm) +{ + return (uint8_t)((pIsm->PARAM & ISM_PARAM_ECMC_MASK) >> ISM_PARAM_ECMC_SHIFT); +} + +/** + * @brief Get ISM FPC count + * + * @param pIsm ISM Instance + * @return FPC count + */ +LOCAL_INLINE uint8_t ISM_HWA_PARAM_FPC(ISM_Type *const pIsm) +{ + return (uint8_t)((pIsm->PARAM & ISM_PARAM_FPC_MASK) >> ISM_PARAM_FPC_SHIFT); +} + +/** + * @brief Get ISM LAM count + * + * @param pIsm ISM Instance + * @return LAM count + */ +LOCAL_INLINE uint8_t ISM_HWA_PARAM_LAM(ISM_Type *const pIsm) +{ + return (uint8_t)((pIsm->PARAM & ISM_PARAM_LAM_MASK) >> ISM_PARAM_LAM_SHIFT); +} + +/** + * @brief Enable ISM + * + * @param pIsm ISM Instance + * @param bEnable EN value + */ +LOCAL_INLINE void ISM_HWA_Enable(ISM_Type *const pIsm, bool bEnable) +{ + pIsm->CTRL = (pIsm->CTRL & ~ISM_CTRL_EN_MASK) | ISM_CTRL_EN(bEnable); +} + +/** + * @brief Enable ISM Interrupt + * + * @param pIsm ISM Instance + * @param bEnable IEN value + */ +LOCAL_INLINE void ISM_HWA_InterruptEnable(ISM_Type *const pIsm, bool bEnable) +{ + pIsm->CTRL = (pIsm->CTRL & ~ISM_CTRL_IEN_MASK) | ISM_CTRL_IEN(bEnable); +} + +/** + * @brief Get ECS of ISM_E_STATUS register + * + * @param pIsm ISM Instance + * @return ECS value + */ +LOCAL_INLINE uint8_t ISM_HWA_GetEcs(ISM_Type *const pIsm) +{ + return (uint8_t)((pIsm->E_STATUS & ISM_E_STATUS_ECS_MASK) >> ISM_E_STATUS_ECS_SHIFT); +} + +/** + * @brief Clear ECS of ISM_E_STATUS register + * + * @param pIsm ISM Instance + * @param u32Channels ECM channels + */ +LOCAL_INLINE void ISM_HWA_ClearEcs(ISM_Type *const pIsm, uint32_t u32Channels) +{ + pIsm->E_STATUS = (u32Channels << ISM_E_STATUS_ECS_SHIFT) & ISM_E_STATUS_ECS_MASK; +} + +/** + * @brief Get ES of ISM_E_STATUS register + * + * @param pIsm ISM Instance + * @return ES value + */ +LOCAL_INLINE uint16_t ISM_HWA_GetEs(ISM_Type *const pIsm) +{ + return (uint16_t)((pIsm->E_STATUS & ISM_E_STATUS_ES_MASK) >> ISM_E_STATUS_ES_SHIFT); +} + +/** + * @brief Clear ES of ISM_E_STATUS register + * + * @param pIsm ISM Instance + * @param u32Channels ECM channels + */ +LOCAL_INLINE void ISM_HWA_ClearEs(ISM_Type *const pIsm, uint32_t u32Channels) +{ + pIsm->E_STATUS = (u32Channels << ISM_E_STATUS_ES_SHIFT) & ISM_E_STATUS_ES_MASK; +} + +/** + * @brief Enable ISM ECM channels system event + * + * @param pIsm ISM Instance + * @param u32Channels ECM Channels + * @param bEnable enable value + */ +LOCAL_INLINE void ISM_HWA_EnableEcmSystemEvent(ISM_Type *const pIsm, uint32_t u32Channels, bool bEnable) +{ + if (bEnable) + { + pIsm->E_CTRL = pIsm->E_CTRL | (u32Channels << ISM_E_CTRL_ECE_SHIFT); + } + else + { + pIsm->E_CTRL = pIsm->E_CTRL & ~(u32Channels << ISM_E_CTRL_ECE_SHIFT); + } +} + +/** + * @brief Get Enabled ISM ECM channels system event + * + * @param pIsm ISM Instance + * @return Enabled ECM event + */ +LOCAL_INLINE uint8_t ISM_HWA_GetEnabledEcmSystemEvent(ISM_Type *const pIsm) +{ + return (uint8_t)((pIsm->E_CTRL & ISM_E_CTRL_ECE_MASK) >> ISM_E_CTRL_ECE_SHIFT); +} + +/** + * @brief Enable ISM LAM channels system event + * + * @param pIsm ISM Instance + * @param u32Channels LAM Channels + * @param bEnable enable value + */ +LOCAL_INLINE void ISM_HWA_EnableLamSystemEvent(ISM_Type *const pIsm, uint32_t u32Channels, bool bEnable) +{ + if (bEnable) + { + pIsm->E_CTRL = pIsm->E_CTRL | (u32Channels << ISM_E_CTRL_EE_SHIFT); + } + else + { + pIsm->E_CTRL = pIsm->E_CTRL & ~(u32Channels << ISM_E_CTRL_EE_SHIFT); + } +} + +/** + * @brief Get Enabled ISM LAM channels system event + * + * @param pIsm ISM Instance + * @return Enabled LAM event + */ +LOCAL_INLINE uint16_t ISM_HWA_GetEnabledLamSystemEvent(ISM_Type *const pIsm) +{ + return (uint16_t)((pIsm->E_CTRL & ISM_E_CTRL_EE_MASK) >> ISM_E_CTRL_EE_SHIFT); +} + +/** + * @brief Set the EC_CTRL register + * + * @param pIsm ISM Instance + * @param u32Value register Value + */ +LOCAL_INLINE void ISM_HWA_SetEcCtrl(ISM_Type *const pIsm, uint32_t u32Value) +{ + pIsm->EC_CTRL = u32Value; +} + +/** + * @brief Set THRL and LAM channel of ECM0 + * + * @param pIsm ISM Instance + * @param u32Value THRL value + * @param u32LamChannel Lam channel + */ +LOCAL_INLINE void ISM_HWA_SetEcm0EcCtrl(ISM_Type *const pIsm, uint32_t u32Value, uint32_t u32LamChannel) +{ + uint32_t u32TempValue = pIsm->EC_CTRL; + + u32TempValue = (u32TempValue & ~ISM_EC_CTRL_SEL_0_MASK) | ISM_EC_CTRL_SEL_0(u32LamChannel); + u32TempValue = (u32TempValue & ~ISM_EC_CTRL_THRL_0_MASK) | ISM_EC_CTRL_THRL_0(u32Value); + pIsm->EC_CTRL = u32TempValue; +} + +/** + * @brief Set THRL and LAM channel of ECM1 + * + * @param pIsm ISM Instance + * @param u32Value THRL value + * @param u32LamChannel Lam channel + */ +LOCAL_INLINE void ISM_HWA_SetEcm1EcCtrl(ISM_Type *const pIsm, uint32_t u32Value, uint32_t u32LamChannel) +{ + uint32_t u32TempValue = pIsm->EC_CTRL; + + u32TempValue = (u32TempValue & ~ISM_EC_CTRL_SEL_1_MASK) | ISM_EC_CTRL_SEL_1(u32LamChannel); + u32TempValue = (u32TempValue & ~ISM_EC_CTRL_THRL_1_MASK) | ISM_EC_CTRL_THRL_1(u32Value); + pIsm->EC_CTRL = u32TempValue; +} + +/** + * @brief Set THRL and LAM channel of ECM2 + * + * @param pIsm ISM Instance + * @param u32Value THRL value + * @param u32LamChannel Lam channel + */ +LOCAL_INLINE void ISM_HWA_SetEcm2EcCtrl(ISM_Type *const pIsm, uint32_t u32Value, uint32_t u32LamChannel) +{ + uint32_t u32TempValue = pIsm->EC_CTRL; + + u32TempValue = (u32TempValue & ~ISM_EC_CTRL_SEL_2_MASK) | ISM_EC_CTRL_SEL_2(u32LamChannel); + u32TempValue = (u32TempValue & ~ISM_EC_CTRL_THRL_2_MASK) | ISM_EC_CTRL_THRL_2(u32Value); + pIsm->EC_CTRL = u32TempValue; +} + +/** + * @brief Set THRL and LAM channel of ECM3 + * + * @param pIsm ISM Instance + * @param u32Value THRL value + * @param u32LamChannel Lam channel + */ +LOCAL_INLINE void ISM_HWA_SetEcm3EcCtrl(ISM_Type *const pIsm, uint32_t u32Value, uint32_t u32LamChannel) +{ + uint32_t u32TempValue = pIsm->EC_CTRL; + + u32TempValue = (u32TempValue & ~ISM_EC_CTRL_SEL_3_MASK) | ISM_EC_CTRL_SEL_3(u32LamChannel); + u32TempValue = (u32TempValue & ~ISM_EC_CTRL_THRL_3_MASK) | ISM_EC_CTRL_THRL_3(u32Value); + pIsm->EC_CTRL = u32TempValue; +} + +/** + * @brief Get the RGD value of FPC_STATUS + * + * @param pFpc FPC Instance + * @return RGD value + */ +LOCAL_INLINE bool ISM_HWA_GetFpcRgd(FPC_Type *const pFpc) +{ + return (pFpc->FPC_STATUS & ISM_FPC_STATUS_RGD_MASK) == ISM_FPC_STATUS_RGD_MASK ? true : false; +} + +/** + * @brief Clear the RGD value of FPC_STATUS + * + * @param pFpc FPC Instance + */ +LOCAL_INLINE void ISM_HWA_ClearFpcRgd(FPC_Type *const pFpc) +{ + pFpc->FPC_STATUS = ISM_FPC_STATUS_RGD_MASK; +} + +/** + * @brief Get the FGD value of FPC_STATUS + * + * @param pFpc FPC Instance + * @return FGD value + */ +LOCAL_INLINE bool ISM_HWA_GetFpcFgd(FPC_Type *const pFpc) +{ + return (pFpc->FPC_STATUS & ISM_FPC_STATUS_FGD_MASK) == ISM_FPC_STATUS_FGD_MASK ? true : false; +} + +/** + * @brief Clear the FGD value of FPC_STATUS + * + * @param pFpc FPC Instance + */ +LOCAL_INLINE void ISM_HWA_ClearFpcFgd(FPC_Type *const pFpc) +{ + pFpc->FPC_STATUS = ISM_FPC_STATUS_FGD_MASK; +} + +/** + * @brief Set the EN of FPC_CTRL + * + * @param pFpc FPC Instance + * @param bEnable EN value + */ +LOCAL_INLINE void ISM_HWA_SetFpcCtrlEn(FPC_Type *const pFpc, bool bEnable) +{ + pFpc->FPC_CTRL = (pFpc->FPC_CTRL & ~ISM_FPC_CTRL_EN_MASK) | ISM_FPC_CTRL_EN(bEnable); +} + +/** + * @brief Set the IEN of FPC_CTRL + * + * @param pFpc FPC Instance + * @param bEnable IEN value + */ +LOCAL_INLINE void ISM_HWA_SetFpcCtrlIen(FPC_Type *const pFpc, bool bEnable) +{ + pFpc->FPC_CTRL = (pFpc->FPC_CTRL & ~ISM_FPC_CTRL_IEN_MASK) | ISM_FPC_CTRL_IEN(bEnable); +} + +/** + * @brief Get the IEN of FPC_CTRL + * + * @param pFpc FPC Instance + * @return Interrupt enable bit + */ +LOCAL_INLINE bool ISM_HWA_GetFpcCtrlIen(FPC_Type *const pFpc) +{ + return (pFpc->FPC_CTRL & ISM_FPC_CTRL_IEN_MASK) == ISM_FPC_CTRL_IEN_MASK ? true : false; +} + +/** + * @brief Set the FEG of FPC_CONFIG + * + * @param pFpc FPC Instance + * @param eMode FEG mode + */ +LOCAL_INLINE void ISM_HWA_SetFpcFallingDetectMode(FPC_Type *const pFpc, ISM_FPC_EdgeDetectModeType eMode) +{ + pFpc->FPC_CONFIG = (pFpc->FPC_CONFIG & ~ISM_FPC_CONFIG_FEG_MASK) | ISM_FPC_CONFIG_FEG(eMode); +} + +/** + * @brief Set the FED of FPC_CONFIG + * + * @param pFpc FPC Instance + * @param eMode FED mode + */ +LOCAL_INLINE void ISM_HWA_SetFpcFallingDelayMode(FPC_Type *const pFpc, ISM_FPC_EdgeDelayModeType eMode) +{ + pFpc->FPC_CONFIG = (pFpc->FPC_CONFIG & ~ISM_FPC_CONFIG_FED_MASK) | ISM_FPC_CONFIG_FED(eMode); +} + +/** + * @brief Set the REG of FPC_CONFIG + * + * @param pFpc FPC Instance + * @param eMode REG mode + */ +LOCAL_INLINE void ISM_HWA_SetFpcRisingDetectMode(FPC_Type *const pFpc, ISM_FPC_EdgeDetectModeType eMode) +{ + pFpc->FPC_CONFIG = (pFpc->FPC_CONFIG & ~ISM_FPC_CONFIG_REG_MASK) | ISM_FPC_CONFIG_REG(eMode); +} + +/** + * @brief Set the RED of FPC_CONFIG + * + * @param pFpc FPC Instance + * @param eMode RED mode + */ +LOCAL_INLINE void ISM_HWA_SetFpcRisingDelayMode(FPC_Type *const pFpc, ISM_FPC_EdgeDelayModeType eMode) +{ + pFpc->FPC_CONFIG = (pFpc->FPC_CONFIG & ~ISM_FPC_CONFIG_RED_MASK) | ISM_FPC_CONFIG_RED(eMode); +} + +/** + * @brief Set the CMP of FPC_CONFIG + * + * @param pFpc FPC Instance + * @param u32Value FPC threshold value that is compared with the 16-bit timer. + */ +LOCAL_INLINE void ISM_HWA_SetFpcConfigCmp(FPC_Type *const pFpc, uint32_t u32Value) +{ + pFpc->FPC_CONFIG = (pFpc->FPC_CONFIG & ~ISM_FPC_CONFIG_CMP_MASK) | ISM_FPC_CONFIG_CMP(u32Value); +} + +/** + * @brief Set the value of FPC_CONFIG + * + * @param pFpc FPC Instance + * @param u32Value Register value + */ +LOCAL_INLINE void ISM_HWA_SetFpcConfig(FPC_Type *const pFpc, uint32_t u32Value) +{ + pFpc->FPC_CONFIG = u32Value; +} + +/** + * @brief Get the TIM of FPC_TIMER + * + * @param pFpc FPC Instance + * @return TIM value + */ +LOCAL_INLINE uint16_t ISM_HWA_GetFpcTimer(FPC_Type *const pFpc) +{ + return (uint16_t)((pFpc->FPC_TIMER & ISM_FPC_TIMER_TIM_MASK) >> ISM_FPC_TIMER_TIM_SHIFT); +} + +/** + * @brief Clear the TIM of FPC_TIMER + * + * @param pFpc FPC Instance + */ +LOCAL_INLINE void ISM_HWA_ClearFpcTimer(FPC_Type *const pFpc) +{ + pFpc->FPC_TIMER = ISM_FPC_TIMER_TIM_MASK; +} + +/** + * @brief Get the COUNT of LAM_STATUS + * + * @param pLam LAM Instance + * @return COUNT value + */ +LOCAL_INLINE uint32_t ISM_HWA_GetLamStatusCounter(LAM_Type *const pLam) +{ + return (pLam->LAM_STATUS & ISM_LAM_STATUS_COUNT_MASK) >> ISM_LAM_STATUS_COUNT_SHIFT; +} + +/** + * @brief Clear the COUNT of LAM_STATUS + * + * @param pLam LAM Instance + */ +LOCAL_INLINE void ISM_HWA_ClearLamStatusCounter(LAM_Type *const pLam) +{ + pLam->LAM_STATUS = ISM_LAM_STATUS_COUNT_MASK; +} + +/** + * @brief Get the OVFL of LAM_STATUS + * + * @param pLam LAM Instance + * @return OVFL value + */ +LOCAL_INLINE bool ISM_HWA_GetLamStatusOvfl(LAM_Type *const pLam) +{ + return (pLam->LAM_STATUS & ISM_LAM_STATUS_OVFL_MASK) == ISM_LAM_STATUS_OVFL_MASK ? true : false; +} + +/** + * @brief Clear the OVFL of LAM_STATUS + * + * @param pLam LAM Instance + */ +LOCAL_INLINE void ISM_HWA_ClearLamStatusOvfl(LAM_Type *const pLam) +{ + pLam->LAM_STATUS = ISM_LAM_STATUS_OVFL_MASK; +} + +/** + * @brief Set the IEN of LAM_CTRL + * + * @param pLam LAM Instance + * @param bEnable IEN value, LAM Channel Overflow Interrupt Enable + */ +LOCAL_INLINE void ISM_HWA_SetLamCtrIen(LAM_Type *const pLam, bool bEnable) +{ + pLam->LAM_CTRL = (pLam->LAM_CTRL & ~ISM_LAM_CTRL_IEN_MASK) | ISM_LAM_CTRL_IEN(bEnable); +} + +/** + * @brief Get the IEN of LAM_CTRL + * + * @param pLam LAM Instance + * @return LAM Channel Overflow Interrupt Enable bit + */ +LOCAL_INLINE bool ISM_HWA_GetLamCtrIen(LAM_Type *const pLam) +{ + return (pLam->LAM_CTRL & ISM_LAM_CTRL_IEN_MASK) == ISM_LAM_CTRL_IEN_MASK ? true : false; +} + +/** + * @brief Set the EN of LAM_CTRL + * + * @param pLam LAM Instance + * @param bEnable EN value, LAM Channel Enable + */ +LOCAL_INLINE void ISM_HWA_SetLamCtrEn(LAM_Type *const pLam, bool bEnable) +{ + pLam->LAM_CTRL = (pLam->LAM_CTRL & ~ISM_LAM_CTRL_EN_MASK) | ISM_LAM_CTRL_EN(bEnable); +} + +/** + * @brief Set the value of LAM_CONFIG + * + * @param pLam LAM Instance + * @param u32Value Reigster value + */ +LOCAL_INLINE void ISM_HWA_SetLamConfig(LAM_Type *const pLam, uint32_t u32Value) +{ + pLam->LAM_CONFIG = u32Value; +} + +/** + * @brief Set the value of LAM_COUNTER + * + * @param pLam LAM Instance + * @param u32Value Reigster value + */ +LOCAL_INLINE void ISM_HWA_SetLamCounter(LAM_Type *const pLam, uint32_t u32Value) +{ + pLam->LAM_CONTER = u32Value; +} + +/** + * @brief Get the FPC instance. + * @param pIsm ISM Instance + * @param u8FpcIndex FPC index + * @return FPC Instance + */ +LOCAL_INLINE FPC_Type *ISM_HWA_GetFpc(ISM_Type *const pIsm, uint8_t u8FpcIndex) +{ + return (FPC_Type *)((uint32_t) & (pIsm->FPC_STATUS0) + (uint32_t)u8FpcIndex * 0x10U); +} + +/** + * @brief Get the LAM instance. + * @param pIsm ISM Instance + * @param u8FpcIndex LAM index + * @return LAM Instance + */ +LOCAL_INLINE LAM_Type *ISM_HWA_GetLam(ISM_Type *const pIsm, uint8_t u8LamIndex) +{ + return (LAM_Type *)((uint32_t) & (pIsm->LAM_STATUS0) + (uint32_t)u8LamIndex * 0x10U); +} + +/** @}*/ /* HwA_ism */ + +#endif /* #ifndef _HWA_ISM_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_lu.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_lu.h new file mode 100644 index 0000000..f94599d --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_lu.h @@ -0,0 +1,248 @@ +/** + * @file HwA_lu.h + * @author Flagchip0103 + * @brief FC7xxx LU hardware access layer + * @version 0.1.0 + * @date 2023-12-19 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-19 Flagchip0103 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef _HWA_LU_H_ +#define _HWA_LU_H_ + +#include "device_header.h" + +/********* Local typedef ************/ +/** @brief LU LG instance */ +typedef enum +{ + LU_LG_0 = 0U, + LU_LG_1, + LU_LG_2, + LU_LG_3 +} LU_LgType; + +/** @brief LU AOI mode */ +typedef enum +{ + LU_NO_BYPASS = 0U, + LU_AOI0_BYPASS, + LU_AOI1_BYPASS, + LU_AOI0_AOI1_BYPASS +} LU_BypassModeType; + +/** @brief LU FF mode */ +typedef enum +{ + LU_BYPASS_MODE0 = 0U, + LU_RS_MODE, + LU_TFF_MODE, + LU_DFF_MODE, + LU_JKFF_MODE, + LU_LATCH_MODE +} LU_ConfigModeType; + +/** @brief LU Input(n) type */ +typedef enum +{ + LU_INPUT_N_A = 0U, + LU_INPUT_N_B, + LU_INPUT_N_C, + LU_INPUT_N_D +} LU_InputNType; +/********* Local inline function ************/ +/** + * @brief Configure LU LG(n) AOI0 configuration + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32RegValue AOI0 register value + */ +LOCAL_INLINE void LU_HWA_ConfigAOI0(LU_Type* pLu, LU_LgType eLg, uint32_t u32RegValue) +{ + pLu->LG[eLg].AOI_0 = u32RegValue; +} + +/** + * @brief Configure LU LG(n) AOI1 configuration + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32RegValue AOI1 register value + */ +LOCAL_INLINE void LU_HWA_ConfigAOI1(LU_Type* pLu, LU_LgType eLg, uint32_t u32RegValue) +{ + pLu->LG[eLg].AOI_1 = u32RegValue; +} + +/** + * @brief Configure LU LG(n) contrl configuration + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32RegValue CTRL register value + */ +LOCAL_INLINE void LU_HWA_ConfigCtrl(LU_Type* pLu, LU_LgType eLg, uint32_t u32RegValue) +{ + pLu->LG[eLg].CTRL = u32RegValue; +} + +/** + * @brief Configure LU LG(n) filter configuration + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32RegValue FILT register value + */ +LOCAL_INLINE void LU_HWA_ConfigFilter(LU_Type* pLu, LU_LgType eLg, uint32_t u32RegValue) +{ + pLu->LG[eLg].FILT = u32RegValue; +} + +/** + * @brief Set LG bypass control + * + * @param pLu LU instance + * @param eLg LG instance + * @param eMode LG bypass control mode + */ +LOCAL_INLINE void LU_HWA_SetLgBypassControl(LU_Type* pLu, LU_LgType eLg, LU_BypassModeType eMode) +{ + uint32_t u32TempRegValue = pLu->LG[eLg].CTRL; + pLu->LG[eLg].CTRL = ((u32TempRegValue & ~(uint32_t)LU_CTRL_BYPASS_MASK) | LU_CTRL_BYPASS(eMode)); +} + +/** + * @brief Set LG Flip-Flop mode + * + * @param pLu LU instance + * @param eLg LG instance + * @param eMode Flip-Flop mode + */ +LOCAL_INLINE void LU_HWA_SetLgFlipFlopMode(LU_Type* pLu, LU_LgType eLg, LU_ConfigModeType eMode) +{ + uint32_t u32TempRegValue = pLu->LG[eLg].CTRL; + pLu->LG[eLg].CTRL = ((u32TempRegValue & ~(uint32_t)LU_CTRL_MOD_MASK) | LU_CTRL_MOD(eMode)); +} + +/** + * @brief Set LG inputs synchronous control + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32Value LG input bit,0-3 bit indicate INPUT(n)A/INPUT(n)B/INPUT(n)C/INPUT(n)D + */ +LOCAL_INLINE void LU_HWA_SetLgInputsSyncCtrl(LU_Type* pLu, LU_LgType eLg, uint32_t u32Value) +{ + uint32_t u32TempRegValue = pLu->LG[eLg].CTRL; + pLu->LG[eLg].CTRL = ((u32TempRegValue & ~(uint32_t)LU_CTRL_SYNC_MASK) | LU_CTRL_SYNC(u32Value)); +} + +/** + * @brief Set LG output feedback override control + * + * @param pLu LU instance + * @param eLg LG instance + * @param eInput Feedback to LG input + */ +LOCAL_INLINE void LU_HWA_SetLgFeedbackOverrideCtrl(LU_Type* pLu, LU_LgType eLg, LU_InputNType eInput) +{ + uint32_t u32TempRegValue = pLu->LG[eLg].CTRL; + pLu->LG[eLg].CTRL = ((u32TempRegValue & ~(uint32_t)LU_CTRL_FB_OVRD_MASK) | LU_CTRL_FB_OVRD(eInput)); +} + +/** + * @brief Configure the output of flip-flop as "1" + * + * @param pLu LU instance + * @param eLg LG instance + */ +LOCAL_INLINE void LU_HWA_ConfigFlipFlopTo1(LU_Type* pLu, LU_LgType eLg) +{ + pLu->LG[eLg].CTRL |= (uint32_t)LU_CTRL_FF_INIT_MASK; +} + +/** + * @brief Generate enable pulse + * + * @param pLu LU instance + * @param eLg LG instance + */ +LOCAL_INLINE void LU_HWA_EnableControlFlipFlopInitOutput(LU_Type* pLu, LU_LgType eLg) +{ + pLu->LG[eLg].CTRL |= (uint32_t)LU_CTRL_INIT_EN_MASK; +} + +/** + * @brief Input filter sample count for AOI0 + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32Value Sample count value + */ +LOCAL_INLINE void LU_HWA_SetAOI0InputFilterSampleCount(LU_Type* pLu, LU_LgType eLg, uint32_t u32Value) +{ + uint32_t u32TempRegValue = pLu->LG[eLg].FILT; + pLu->LG[eLg].FILT = ((u32TempRegValue & ~(uint32_t)LU_FILT_CNT0_MASK) | LU_FILT_CNT0(u32Value)); +} + +/** + * @brief Input filter sample period for AOI0 + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32Value Sample period value + */ +LOCAL_INLINE void LU_HWA_SetAOI0InputFilterSamplePeriod(LU_Type* pLu, LU_LgType eLg, uint32_t u32Value) +{ + uint32_t u32TempRegValue = pLu->LG[eLg].FILT; + pLu->LG[eLg].FILT = ((u32TempRegValue & ~(uint32_t)LU_FILT_PRE0_MASK) | LU_FILT_PRE0(u32Value)); +} + +/** + * @brief Input filter sample count for AOI1 + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32Value Sample count value + */ +LOCAL_INLINE void LU_HWA_SetAOI1InputFilterSampleCount(LU_Type* pLu, LU_LgType eLg, uint32_t u32Value) +{ + uint32_t u32TempRegValue = pLu->LG[eLg].FILT; + pLu->LG[eLg].FILT = ((u32TempRegValue & ~(uint32_t)LU_FILT_CNT1_MASK) | LU_FILT_CNT1(u32Value)); +} + +/** + * @brief Input filter sample period for AOI1 + * + * @param pLu LU instance + * @param eLg LG instance + * @param u32Value Sample period value + */ +LOCAL_INLINE void LU_HWA_SetAOI1InputFilterSamplePeriod(LU_Type* pLu, LU_LgType eLg, uint32_t u32Value) +{ + uint32_t u32TempRegValue = pLu->LG[eLg].FILT; + pLu->LG[eLg].FILT = ((u32TempRegValue & ~(uint32_t)LU_FILT_PRE1_MASK) | LU_FILT_PRE1(u32Value)); +} + +/** + * @brief Configure the output of flip-flop as "0" + * + * @param pLu LU instance + * @param eLg LG instance + */ +LOCAL_INLINE void LU_HWA_ConfigFlipFlopTo0(LU_Type* pLu, LU_LgType eLg) +{ + pLu->LG[eLg].CTRL &= ~(uint32_t)LU_CTRL_FF_INIT_MASK; +} + +#endif /* #ifndef _HWA_LU_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_mam.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_mam.h new file mode 100644 index 0000000..4897dec --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_mam.h @@ -0,0 +1,126 @@ +/** + * @file HwA_mam.h + * @author Flagchip + * @brief Hardware access layer for MAM + * @version 0.2.0 + * @date 2023-02-08 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-02-08 Flagchip054 N/A First version for FC7300 + ******************************************************************************** */ +#ifndef _HWA_MAM_H_ +#define _HWA_MAM_H_ +#include "device_header.h" + +/** + * @brief Set Mam module Matrix Configure register + * + * @param1 MAM base pointer + * + * @param2 u32Value Matrix Configure register value + */ +LOCAL_INLINE void Mam_HWA_SetMatrixCfg(MAM_Type *MAMInstance, uint32_t u32Value) +{ + MAMInstance->MAXCFG = u32Value; +} + +/** + * @brief Read Mam module Ctrl register + * + * @param MAM base pointer + * + * @return Matrix Configure register value + */ +LOCAL_INLINE uint32_t Mam_HWA_GetMatrixCfg(MAM_Type *MAMInstance) +{ + return (uint32_t)(MAMInstance->MAXCFG); +} + +/** + * @brief Set Mam module Wdgctr register + * + * @param1 MAM base pointer + * + * @param2 u32Value Wdgctr register value + */ +LOCAL_INLINE void Mam_HWA_Set_Wdgctr(MAM_Type *MAMInstance, uint32_t u32Value) +{ + MAMInstance->WDGCR = u32Value; +} + +/** + * @brief Read Mam module Wdgctr register + * + * @param MAM base pointer + * + * @return Wdgctr register value + */ +LOCAL_INLINE uint32 Mam_HWA_Get_Wdgctr(MAM_Type *MAMInstance) +{ + return MAMInstance->WDGCR; +} + +/** + * @brief Set Mam module ACR register + * + * @param1 MAM base pointer + * + * @param2 idx ACR register index + * + * @param3 u32Value ACR register value + */ +LOCAL_INLINE void Mam_HWA_Set_ACR(MAM_Type *MAMInstance, uint32_t idx, uint32_t u32Value) +{ + MAMInstance->ACR[idx] = u32Value; +} + +/** + * @brief Read Mam module ACR register + * + * @param1 MAM base pointer + * + * @param2 idx ACR register index + * + * @return ACR register value + */ +LOCAL_INLINE uint32_t Mam_HWA_Get_ACR(MAM_Type *MAMInstance, uint32_t idx) +{ + return MAMInstance->ACR[idx]; +} + +/** + * @brief Set Mam module ACLR register + * + * @param1 MAM base pointer + * + * @param2 idx ACLR register index + * + * @param3 u32Value ACLR register value + */ +LOCAL_INLINE void Mam_HWA_Set_ACLR(MAM_Type *MAMInstance, uint32_t idx, uint32_t u32Value) +{ + MAMInstance->ACLR[idx] = u32Value; +} + +/** + * @brief Read Mam module ACLR register + * + * @param1 MAM base pointer + * + * @param2 idx ACLR register index + * + * @return ACLR register value + */ +LOCAL_INLINE uint32_t Mam_HWA_Get_ACLR(MAM_Type *MAMInstance, uint32_t idx) +{ + return MAMInstance->ACLR[idx]; +} + +#endif diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_mb.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_mb.h new file mode 100644 index 0000000..9cfb2cb --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_mb.h @@ -0,0 +1,408 @@ +/** + * @file HwA_mb.h + * @author Flagchip070 + * @brief FC7xxx Mailbox hardware access layer + * @version 0.1.0 + * @date 2022-11-15 + * + * @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2022-11-15 Flagchip070 N/A First version for FC7300 + ******************************************************************************** */ + +#ifndef _HWA_MAILBOX_H_ +#define _HWA_MAILBOX_H_ +#include "device_header.h" + +/** + * @brief The definition of mask all events + * + */ +#define MB_EVENT_NONE 0u +/** + * @brief The definition of receiving all events + * + */ +#define MB_EVENT_ALL 0xFFFFFFFFu +/** + * @brief The definition of receiving all request events + * + */ +#define MB_EVENT_ALL_REQ 0x0000FFFFu +/** + * @brief The definition of receiving all done events + * + */ +#define MB_EVENT_ALL_DONE 0xFFFF0000u +/** + * @brief The definition of request events on ch + * + */ +#define MB_EVENT_REQ(ch) (uint32_t)((uint32_t)1u << (ch)) +/** + * @brief The definition of done events on ch + * + */ +#define MB_EVENT_DONE(ch) (uint32_t)((uint32_t)1u << ((ch) + 16u)) +/** + * @brief The definition of issue to no core + * + */ +#define MB_CORE_MASK_CORE_NONE 0u +/** + * @brief The definition of issue to core 0 + * + */ +#define MB_CORE_MASK_CORE_0 1u +/** + * @brief The definition of issue to HSM + * + */ +#define MB_CORE_MASK_HSM 2u +/** + * @brief The definition of issue to all cores + * + */ +#define MB_CORE_MASK_ALL 0x3u +/** + * @brief The definition of issue to core + * + */ +#define MB_CORE_MASK(core) (uint32_t)(1ul << (core)) + +enum +{ + MB_CORE_INDEX_CORE_0 = 0, /*!< Core index of core 0 */ + MB_CORE_INDEX_HSM, /*!< Core index of HSM */ +}; + +/** + * @brief Configure receive events of mailbox interrupt channel + * + * @param u32CoreIndex the index of the core + * @param u32Mask configuration for receiving events + */ +LOCAL_INLINE void MB_HWA_ConfigFlagMask(uint32_t u32CoreIndex, uint32_t u32Mask) +{ + MB->INTR[u32CoreIndex].MB_INTn_CTRL &= ~MB_INTn_CTRL_FLG_MASK_LOCK_MASK; + MB->INTR[u32CoreIndex].MB_INTn_FLG_MASK = u32Mask; + MB->INTR[u32CoreIndex].MB_INTn_CTRL |= MB_INTn_CTRL_FLG_MASK_LOCK_MASK; +} + +/** + * @brief Enable receive events of mailbox interrupt channel + * + * @param u32CoreIndex the index of the core + * @param u32Mask indicates the events to be enabled + */ +LOCAL_INLINE void MB_HWA_EnableEvent(uint32_t u32CoreIndex, uint32_t u32Mask) +{ + MB->INTR[u32CoreIndex].MB_INTn_CTRL &= ~MB_INTn_CTRL_FLG_MASK_LOCK_MASK; + MB->INTR[u32CoreIndex].MB_INTn_FLG_MASK |= u32Mask; + MB->INTR[u32CoreIndex].MB_INTn_CTRL |= MB_INTn_CTRL_FLG_MASK_LOCK_MASK; +} + +/** + * @brief Disable receive events of mailbox interrupt channel + * + * @param u32CoreIndex the index of the core + * @param u32Mask indicates the events to be enabled + */ +LOCAL_INLINE void MB_HWA_DisableEvent(uint32_t u32CoreIndex, uint32_t u32Mask) +{ + MB->INTR[u32CoreIndex].MB_INTn_CTRL &= ~MB_INTn_CTRL_FLG_MASK_LOCK_MASK; + MB->INTR[u32CoreIndex].MB_INTn_FLG_MASK &= ~u32Mask; + MB->INTR[u32CoreIndex].MB_INTn_CTRL |= MB_INTn_CTRL_FLG_MASK_LOCK_MASK; +} + +/** + * @brief Configure the interrupt of mailbox interrupt channel + * + * @param u32CoreIndex the index of the core + * @param u32Mask configuration for interrupts + */ +LOCAL_INLINE void MB_HWA_ConfigIntrEnable(uint32_t u32CoreIndex, uint32_t u32Mask) +{ + MB->INTR[u32CoreIndex].MB_INTn_CTRL &= ~MB_INTn_CTRL_INTEN_LOCK_MASK; + MB->INTR[u32CoreIndex].MB_INTn_INTEN = u32Mask; + MB->INTR[u32CoreIndex].MB_INTn_CTRL |= MB_INTn_CTRL_INTEN_LOCK_MASK; +} + +/** + * @brief Enable the interrupt of mailbox interrupt channel + * + * @param u32CoreIndex the index of the core + * @param u32Mask indicates the interrupts to be enabled + */ +LOCAL_INLINE void MB_HWA_EnableIntr(uint32_t u32CoreIndex, uint32_t u32Mask) +{ + MB->INTR[u32CoreIndex].MB_INTn_CTRL &= ~MB_INTn_CTRL_INTEN_LOCK_MASK; + MB->INTR[u32CoreIndex].MB_INTn_INTEN |= u32Mask; + MB->INTR[u32CoreIndex].MB_INTn_CTRL |= MB_INTn_CTRL_INTEN_LOCK_MASK; +} + +/** + * @brief Disable the interrupt of mailbox interrupt channel + * + * @param u32CoreIndex the index of the core + * @param u32Mask indicates the interrupts to be disabled + */ +LOCAL_INLINE void MB_HWA_DisableIntr(uint32_t u32CoreIndex, uint32_t u32Mask) +{ + MB->INTR[u32CoreIndex].MB_INTn_CTRL &= ~MB_INTn_CTRL_INTEN_LOCK_MASK; + MB->INTR[u32CoreIndex].MB_INTn_INTEN &= ~u32Mask; + MB->INTR[u32CoreIndex].MB_INTn_CTRL |= MB_INTn_CTRL_INTEN_LOCK_MASK; +} + +/** + * @brief Clear the flag of mailbox interrupt channel + * + * @param u32CoreIndex the index of the core + * @param u32Mask indicates the flags to be cleared + */ +LOCAL_INLINE void MB_HWA_ClearFlag(uint32_t u32CoreIndex, uint32_t u32Mask) +{ + MB->INTR[u32CoreIndex].MB_INTn_CTRL &= ~MB_INTn_CTRL_FLG_LOCK_MASK; + MB->INTR[u32CoreIndex].MB_INTn_FLG |= u32Mask; + MB->INTR[u32CoreIndex].MB_INTn_CTRL |= MB_INTn_CTRL_FLG_LOCK_MASK; +} + +/** + * @brief Get the flag masks of mailbox interrupt channel + * + * @param u32CoreIndex the index of the core + * @param u32Mask the mask to get + * @return the flag masks of the mailbox interrupt channel + */ +LOCAL_INLINE uint32_t MB_HWA_GetFlagMask(uint32_t u32CoreIndex, uint32_t u32Mask) +{ + uint32_t u32RegValue = MB->INTR[u32CoreIndex].MB_INTn_FLG_MASK & u32Mask; + return u32RegValue; +} + +/** + * @brief Get the flags of mailbox interrupt channel + * + * @param u32CoreIndex the index of the core + * @param u32Mask the mask to get + * @return the flags of the mailbox interrupt channel + */ +LOCAL_INLINE uint32_t MB_HWA_GetFlag(uint32_t u32CoreIndex, uint32_t u32Mask) +{ + uint32_t u32RegValue = MB->INTR[u32CoreIndex].MB_INTn_FLG & u32Mask; + return u32RegValue; +} + +/** + * @brief Get the result of flag & inten of mailbox interrupt channel + * + * @param u32CoreIndex the index of the core + * @param u32Mask the mask to get + * @return the result of flag & inten of the mailbox interrupt channel + */ +LOCAL_INLINE uint32_t MB_HWA_GetFlagStat(uint32_t u32CoreIndex, uint32_t u32Mask) +{ + uint32_t u32RegValue = MB->INTR[u32CoreIndex].MB_INTn_FLG_STAT & u32Mask; + return u32RegValue; +} + +/** + * @brief Get the master ID of the currently obtained channel + * + * @param u32Channel the index of the channel + * @return the master ID + */ +LOCAL_INLINE uint32_t MB_HWA_GetMasterID(uint32_t u32Channel) +{ + uint32_t u32MasterId = MB->CHANNEL[u32Channel].MB_CCn_STAT; + u32MasterId = (u32MasterId & MB_CCn_STAT_CURRENT_LOCK_MASTER_ID_MASK) >> MB_CCn_STAT_CURRENT_LOCK_MASTER_ID_SHIFT; + return u32MasterId; +} + +/** + * @brief Get the security information of the currently obtained channel + * + * @param u32Channel the index of the channel + * @return the security information + */ +LOCAL_INLINE uint32_t MB_HWA_GetSecure(uint32_t u32Channel) +{ + uint32_t u32Secure = MB->CHANNEL[u32Channel].MB_CCn_STAT & MB_CCn_STAT_CURRENT_LOCK_MASTER_SEC_MASK; + return u32Secure; +} + +/** + * @brief Get the processing mode of the currently obtained channel + * + * @param u32Channel the index of the channel + * @return the processing mode + */ +LOCAL_INLINE uint32_t MB_HWA_GetSupervisor(uint32_t u32Channel) +{ + uint32_t u32Supervisor = MB->CHANNEL[u32Channel].MB_CCn_STAT & MB_CCn_STAT_CURRENT_LOCK_MASTER_SUPERVISOR_MASK; + return u32Supervisor; +} + +/** + * @brief Send data to the mailbox channel + * + * @param u32Channel the index of the channel + * @param pData the buffer to be written + */ +LOCAL_INLINE void MB_HWA_WriteData(uint32_t u32Channel, uint32_t *pData) +{ + MB->CHANNEL[u32Channel].MB_CCn_DATA0 = pData[0]; + MB->CHANNEL[u32Channel].MB_CCn_DATA1 = pData[1]; +} + +/** + * @brief Receive data from the mailbox channel + * + * @param u32Channel the index of the channel + * @param pData the buffer to receive data + */ +LOCAL_INLINE void MB_HWA_GetData(uint32_t u32Channel, uint32_t *pData) +{ + pData[0] = MB->CHANNEL[u32Channel].MB_CCn_DATA0; + pData[1] = MB->CHANNEL[u32Channel].MB_CCn_DATA1; +} + +/** + * @brief Get the automatically clear status of the mailbox channel + * + * @param u32Channel the index of the channel + * @param u32CoreIndex the index of the core + * @return automatically clear the channel lock enable bit + */ +LOCAL_INLINE uint32_t MB_HWA_GetAutoClear(uint32_t u32Channel, uint32_t u32CoreIndex) +{ + uint32_t u32SemaUnlock = MB->CHANNEL[u32Channel].MB_CCn_SEMA_UNLK; + u32SemaUnlock &= (uint32_t)1u << (u32CoreIndex + MB_CCn_SEMA_UNLK_AUTO_CLEAR_EN_SHIFT); + return u32SemaUnlock; +} + +/** + * @brief Release the mailbox channel + * + * @param u32Channel the index of the channel + */ +LOCAL_INLINE void MB_HWA_ReleaseChannel(uint32_t u32Channel) +{ + MB->CHANNEL[u32Channel].MB_CCn_DONE = MB_MASTER_DONE_CODE; +} + +/** + * @brief Software clears channel lock + * + * @param u32Channel the index of the channel + */ +LOCAL_INLINE void MB_HWA_UnlockChanne(uint32_t u32Channel) +{ + MB->CHANNEL[u32Channel].MB_CCn_CLR = MB_FORCE_UNLOCK_CODE; +} + +/** + * @brief Issue a done event + * + * @param u32Channel the index of the channel + * @param u32DoneMask the cores to issue + */ +LOCAL_INLINE void MB_HWA_SetDone(uint32_t u32Channel, uint32_t u32DoneMask) +{ + MB->CHANNEL[u32Channel].MB_CCn_DONE |= (u32DoneMask & MB_CCn_DONE_DONE_MASK); +} + +/** + * @brief Try to lock a channel + * + * @param u32Channel the index of the channel + * @return Channel Lock Acquisition + */ +LOCAL_INLINE uint32_t MB_HWA_LockChannel(uint32_t u32Channel) +{ + uint32_t u32RegValue = MB->CHANNEL[u32Channel].MB_CCn_SEMA; + return u32RegValue & MB_CCn_SEMA_LOCK_MASK; +} + +/** + * @brief Configure the master ID of the core that generates a done event + * + * @param u32Channel the index of the channel + * @param u32MasterId master ID + */ +LOCAL_INLINE void MB_HWA_ConfigDoneMasterId(uint32_t u32Channel, uint32_t u32MasterId) +{ + MB->CHANNEL[u32Channel].MB_CCn_DONE_MASK &= ~MB_CCn_DONE_MASK_DONE_MASTER_ID_MASK; + MB->CHANNEL[u32Channel].MB_CCn_DONE_MASK |= MB_CCn_DONE_MASK_DONE_MASTER_ID(u32MasterId); +} + +/** + * @brief Get the master ID of the core that generates a done event + * + * @param u32Channel the index of the channel + * @return the master ID + */ +LOCAL_INLINE uint32_t MB_HWA_GetDoneMasterId(uint32_t u32Channel) +{ + uint32_t u32MasterId = + (MB->CHANNEL[u32Channel].MB_CCn_DONE_MASK & MB_CCn_DONE_MASK_DONE_MASTER_ID_MASK) + >> MB_CCn_DONE_MASK_DONE_MASTER_ID_SHIFT; + return u32MasterId; + +} + +/** + * @brief Configure the mask of the done events + * + * @param u32Channel the index of the channel + * @param u32DoneMask the cores to issue + */ +LOCAL_INLINE void MB_HWA_ConfigDoneMask(uint32_t u32Channel, uint32_t u32DoneMask) +{ + MB->CHANNEL[u32Channel].MB_CCn_DONE_MASK &= ~MB_CCn_DONE_DONE_MASK; + MB->CHANNEL[u32Channel].MB_CCn_DONE_MASK |= (u32DoneMask << MB_CCn_DONE_DONE_SHIFT) & MB_CCn_DONE_DONE_MASK; +} + +/** + * @brief Get the mask of the done events + * + * @param u32Channel the index of the channel + * @return the mask of the done events + */ +LOCAL_INLINE uint32_t MB_HWA_GetDoneMask(uint32_t u32Channel) +{ + uint32_t u32Mask = MB->CHANNEL[u32Channel].MB_CCn_DONE_MASK & MB_CCn_DONE_DONE_MASK; + return u32Mask; +} + +/** + * @brief Configure the automatically clear of the lock enable bit + * + * @param u32Channel the index of the channel + * @param u32AutoUnlockMask the automatically clear of the lock enable bit + */ +LOCAL_INLINE void MB_HWA_ConfigAutoUnlock(uint32_t u32Channel, uint32_t u32AutoUnlockMask) +{ + MB->CHANNEL[u32Channel].MB_CCn_SEMA_UNLK = MB_CCn_SEMA_UNLK_AUTO_CLEAR_EN(u32AutoUnlockMask); +} + +/** + * @brief Issue request events + * + * @param u32Channel the index of the channel + * @param u32RequestMask the cores to issue + */ +LOCAL_INLINE void MB_HWA_ConfigRequest(uint32_t u32Channel, uint32_t u32RequestMask) +{ + MB->CHANNEL[u32Channel].MB_CCn_REQUEST = MB_CCn_REQUEST_REQ(u32RequestMask); +} + +#endif + diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_mpu.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_mpu.h new file mode 100644 index 0000000..aeee8a1 --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_mpu.h @@ -0,0 +1,320 @@ +/** + * @file HwA_mpu.h + * @author Flagchip085 + * @brief FC7xxx MPU hardware access layer + * @version 0.1.0 + * @date 2024-01-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240 + ******************************************************************************** */ +#ifndef _HWA_MPU_H_ +#define _HWA_MPU_H_ + +#include "device_header.h" + +/** + * @brief The MPU registers struct + * + */ +typedef struct { + __I uint32_t MPU_TYPE; /* TYPE, offset: 0x0 */ + __IO uint32_t MPU_CTRL; /* CTRL, offset: 0x4 */ + __IO uint32_t MPU_RNR; /* RNR, offset: 0x8 */ + __IO uint32_t MPU_RBAR; /* RBAR, offset: 0xC */ + __IO uint32_t MPU_RASR; /* RASR, offset: 0x10 */ +} CORTEX_MPU_Type, *PCORTEX_MPU_Type; + +/** mpu base Address */ +#define CORTEX_MPU_BASE (0xE000ED90U) +#define CORTEX_MPU ((CORTEX_MPU_Type *)CORTEX_MPU_BASE) + + +/** TYPE Bit Fields **/ +#define CORTEX_MPU_TYPE_IREGION_MASK 0xFF0000U + +#define CORTEX_MPU_TYPE_IREGION_SHIFT 16U + +#define CORTEX_MPU_TYPE_IREGION_WIDTH 8U + +#define CORTEX_MPU_TYPE_IREGION(x) (((uint32_t)(((uint32_t)(x))<MPU_TYPE; +} + +/** + * @brief disable fault exceptions + * + * + */ +LOCAL_INLINE void MPU_HWA_Fault_Disable(void) +{ + SCB->SHCSR &= ~((uint32_t)SCB_SHCSR_MEMFAULTENA_Msk); +} + +/** + * @brief enable fault exceptions + * + * + */ +LOCAL_INLINE void MPU_HWA_Fault_Enable(void) +{ + SCB->SHCSR |= (uint32_t)SCB_SHCSR_MEMFAULTENA_Msk; +} + +/** + * @brief set mpu control register + * + * @param u32RegValue the value write to register + * @return LOCAL_INLINE + */ +LOCAL_INLINE void MPU_HWA_Set_CR(uint32_t u32RegValue) +{ + CORTEX_MPU->MPU_CTRL = u32RegValue; +} + +/** + * @brief set mpu number register + * + * @param u32RegValue the value write to register + * @return LOCAL_INLINE + */ +LOCAL_INLINE void MPU_HWA_Set_NR(uint8_t u32RegValue) +{ + CORTEX_MPU->MPU_RNR = (MPU_REGION_MASK_U32 & u32RegValue); +} + +/** + * @brief set mpu base address register + * + * @param u32RegValue the value write to register + * @return LOCAL_INLINE + */ +LOCAL_INLINE void MPU_HWA_Set_BAR(uint32_t u32RegValue) +{ + CORTEX_MPU->MPU_RBAR = u32RegValue; +} + + +/** + * @brief set mpu attribute and size register + * + * @param u32RegValue the value write to registe + * @return LOCAL_INLINE + */ +LOCAL_INLINE void MPU_HWA_Set_ASR(uint32_t u32RegValue) +{ + CORTEX_MPU->MPU_RASR = u32RegValue; +} + + +#endif /* _HWA_MPU_H_ */ + diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_msc.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_msc.h new file mode 100644 index 0000000..4498f9c --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_msc.h @@ -0,0 +1,841 @@ +/** + * @file HwA_msc.h + * @author Flagchip + * @brief FC7240 MSC HWA driver type definition and API + * @version 0.1.0 + * @date 2024-01-10 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-10 Flagchip084 N/A FC7240 release version + ******************************************************************************** */ + +#ifndef _HWA_MSC_H_ +#define _HWA_MSC_H_ + +#include "device_header.h" + +/** + * @addtogroup HwA_msc + * @{ + * + */ +/********* macros ************/ + +typedef enum +{ + MSC_RSV_SUCCESS = 0x0U, /*!< MSC receive status is successful. */ + MSC_RSV_PARITY_ERROR = 0x1U, /*!< MSC receive has parity error. */ + MSC_RSV_STOP_ERROR = 0x2U /*!< MSC receive has stop error. */ +} MSC_ReceiveStatusType; + +/********* Local typedef ************/ + +/********* Local inline function ************/ + +/********* xxx Register interface ************/ + +/** + * @brief Get the msc TCCTR register + * + * @param pMsc MSCInstance + * @param u32Value TCCTR register value + */ +LOCAL_INLINE void MSC_HWA_SetTcctr(MSC_Type *const pMsc, uint32_t u32Value) +{ + pMsc->TCCTR = u32Value; +} + +/** + * @brief Get the msc TCCTR register DTS bit + * + * @param pMsc MSCInstance + * @return DTS value + */ +LOCAL_INLINE bool MSC_HWA_GetDataNeedSend(MSC_Type *const pMsc) +{ + return (pMsc->TCCTR & MSC_TCCTR_DTS_MASK) == MSC_TCCTR_DTS_MASK ? true : false; +} + +/** + * @brief Set the msc TCCTR register DTS bit + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_SetDataNeedSend(MSC_Type *const pMsc) +{ + pMsc->ISCR = MSC_ISCR_SDTS_MASK; +} + +/** + * @brief Get the msc TCCTR register CTS bit + * + * @param pMsc MSCInstance + * @return CTS value + */ +LOCAL_INLINE bool MSC_HWA_GetCmdNeedSend(MSC_Type *const pMsc) +{ + return (pMsc->TCCTR & MSC_TCCTR_CTS_MASK) == MSC_TCCTR_CTS_MASK ? true : false; +} + +/** + * @brief Get the CFB value of TCSTR register + * + * @param pMsc MSCInstance + * @return CFB value + */ +LOCAL_INLINE bool MSC_HWA_GetCfb(MSC_Type *const pMsc) +{ + return (bool)(((pMsc->TCSTR & (uint32_t)MSC_TCSTR_CFB_MASK) != 0U) ? true : false); +} + +/** + * @brief Get the DFB value of TCSTR register + * + * @param pMsc MSCInstance + * @return DFB value + */ +LOCAL_INLINE bool MSC_HWA_GetDfb(MSC_Type *const pMsc) +{ + return ((pMsc->TCSTR & (uint32_t)MSC_TCSTR_DFB_MASK) != 0U) ? true : false; +} + +/** + * @brief Set the NP value of TCSTR register + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_SetNp(MSC_Type *const pMsc, uint8_t u8Np) +{ + pMsc->TCSTR = (pMsc->TCSTR & ~MSC_TCSTR_NP_MASK) | MSC_TCSTR_NP(u8Np); +} + +/** + * @brief Get the NP value of TCSTR register + * + * @param pMsc MSCInstance + * @return NP value + */ +LOCAL_INLINE uint32_t MSC_HWA_GetNp(MSC_Type *const pMsc) +{ + return ((pMsc->TCSTR & (uint32_t)MSC_TCSTR_NP_MASK)) >> MSC_TCSTR_NP_SHIFT; +} + +/** + * @brief Set the msc TCDAR register + * + * @param pMsc MSCInstance + * @param u32Value TCDAR value + */ +LOCAL_INLINE void MSC_HWA_SetTcdar(MSC_Type *const pMsc, uint32_t u32Value) +{ + pMsc->TCDAR = u32Value; +} + +/** + * @brief Set the TDH of TCDAR register + * + * @param pMsc MSCInstance + * @param u16Value TDH value + */ +LOCAL_INLINE void MSC_HWA_SetTcdarTdh(MSC_Type *const pMsc, uint16_t u16Value) +{ + pMsc->TCDAR = (pMsc->TCDAR & ~MSC_TCDAR_TDH_MASK) | MSC_TCDAR_TDH(u16Value); +} + +/** + * @brief Set the TDL of TCDAR register + * + * @param pMsc MSCInstance + * @param u16Value TDL value + */ +LOCAL_INLINE void MSC_HWA_SetTcdarTdl(MSC_Type *const pMsc, uint16_t u16Value) +{ + pMsc->TCDAR = (pMsc->TCDAR & ~MSC_TCDAR_TDL_MASK) | MSC_TCDAR_TDL(u16Value); +} + +/** + * @brief Set the TCCOR register + * + * @param pMsc MSCInstance + * @param u32Value TCCOR value + */ +LOCAL_INLINE void MSC_HWA_SetTccor(MSC_Type *const pMsc, uint32_t u32Value) +{ + pMsc->TCCOR = u32Value; +} + +/** + * @brief Set the TCH of TCCOR register + * + * @param pMsc MSCInstance + * @param u16Value TCH value + */ +LOCAL_INLINE void MSC_HWA_SetTccorTch(MSC_Type *const pMsc, uint16_t u16Value) +{ + pMsc->TCCOR = (pMsc->TCCOR & ~MSC_TCCOR_TCH_MASK) | MSC_TCCOR_TCH(u16Value); +} + +/** + * @brief Set the TCL of TCCOR register + * + * @param pMsc MSCInstance + * @param u16Value TCL value + */ +LOCAL_INLINE void MSC_HWA_SetTccorTcl(MSC_Type *const pMsc, uint16_t u16Value) +{ + pMsc->TCCOR = (pMsc->TCCOR & ~MSC_TCCOR_TCL_MASK) | MSC_TCCOR_TCL(u16Value); +} + +/** + * @brief Set the TCSLR register + * + * @param pMsc MSCInstance + * @param u32Value TCSLR value + */ +LOCAL_INLINE void MSC_HWA_SetTcslr(MSC_Type *const pMsc, uint32_t u32Value) +{ + pMsc->TCSLR = u32Value; +} + +/** + * @brief Set the TCSHR register + * + * @param pMsc MSCInstance + * @param u32Value TCSHR value + */ +LOCAL_INLINE void MSC_HWA_SetTcshr(MSC_Type *const pMsc, uint32_t u32Value) +{ + pMsc->TCSHR = u32Value; +} + +/** + * @brief Set the TCELR register + * + * @param pMsc MSCInstance + * @param u32Value TCELR value + */ +LOCAL_INLINE void MSC_HWA_SetTcelr(MSC_Type *const pMsc, uint32_t u32Value) +{ + pMsc->TCELR = u32Value; +} + +/** + * @brief Get the IOCR register value + * + * @param pMsc MSCInstance + * @return IOCR value + */ +LOCAL_INLINE uint32_t MSC_HWA_GetIocr(MSC_Type *const pMsc) +{ + return pMsc->IOCR; +} + +/** + * @brief Set the IOCR register + * + * @param pMsc MSCInstance + * @param u32Value IOCR value + */ +LOCAL_INLINE void MSC_HWA_SetIocr(MSC_Type *const pMsc, uint32_t u32Value) +{ + pMsc->IOCR = u32Value; +} + +/** + * @brief Set the ISCR register + * + * @param pMsc MSCInstance + * @param u32Value ISCR value + */ +LOCAL_INLINE void MSC_HWA_SetIscr(MSC_Type *const pMsc, uint32_t u32Value) +{ + pMsc->ISCR = u32Value; +} + +/** + * @brief Set the msc TCDIS + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_SetTcdis(MSC_Type *const pMsc) +{ + pMsc->ISCR = MSC_ISCR_SDIS_MASK; +} + +/** + * @brief Clear the msc TCDIS + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_ClearTcdis(MSC_Type *const pMsc) +{ + pMsc->ISCR = MSC_ISCR_CDIS_MASK; +} + +/** + * @brief Clear the msc CRFI + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_ClearCrfi(MSC_Type *const pMsc) +{ + pMsc->ISCR = MSC_ISCR_CRFI_MASK; +} + +/** + * @brief Clear the msc CTFI + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_ClearCtfi(MSC_Type *const pMsc) +{ + pMsc->ISCR = MSC_ISCR_CTFI_MASK; +} + +/** + * @brief Clear the msc CCFI + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_ClearCcfi(MSC_Type *const pMsc) +{ + pMsc->ISCR = MSC_ISCR_CCFI_MASK; +} + +/** + * @brief Clear the msc CDFI + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_ClearCdfi(MSC_Type *const pMsc) +{ + pMsc->ISCR = MSC_ISCR_CDFI_MASK; +} + +/** + * @brief Get the msc INSR register + * + * @param pMsc MSCInstance + * @return INSR register value + */ +LOCAL_INLINE uint32_t MSC_HWA_GetInsr(MSC_Type *const pMsc) +{ + return pMsc->INSR & (uint32_t)MSC_INSR_MASK; +} + +/** + * @brief Set the INCR register + * + * @param pMsc MSCInstance + * @param u32Value INCR value + */ +LOCAL_INLINE void MSC_HWA_SetIncr(MSC_Type *const pMsc, uint32_t u32Value) +{ + pMsc->INCR = u32Value; +} + +/** + * @brief Check the RFIE of INCR register + * + * @param pMsc MSCInstance + * @return RFIE enable + */ +LOCAL_INLINE bool MSC_HWA_GetRfieEnable(MSC_Type *const pMsc) +{ + return (pMsc->INCR & MSC_INCR_RFIE_MASK) != 0U ? true : false; +} + +/** + * @brief Set the RFIE of INCR register + * + * @param pMsc MSCInstance + * @param bEnable enable RFIE + */ +LOCAL_INLINE void MSC_HWA_SetRfieEnable(MSC_Type *const pMsc, bool bEnable) +{ + pMsc->INCR = (pMsc->INCR & ~MSC_INCR_RFIE_MASK) | MSC_INCR_RFIE(bEnable); +} + +/** + * @brief Check the TFIE of INCR register + * + * @param pMsc MSCInstance + * @return TFIE enable + */ +LOCAL_INLINE bool MSC_HWA_GetTfieEnable(MSC_Type *const pMsc) +{ + return (pMsc->INCR & MSC_INCR_TFIE_MASK) == MSC_INCR_TFIE_MASK ? true : false; +} + +/** + * @brief Set the TFIE of INCR register + * + * @param pMsc MSCInstance + * @param bEnable enable TFIE + */ +LOCAL_INLINE void MSC_HWA_SetTfieEnable(MSC_Type *const pMsc, bool bEnable) +{ + pMsc->INCR = (pMsc->INCR & ~MSC_INCR_TFIE_MASK) | MSC_INCR_TFIE(bEnable); +} + +/** + * @brief Check the CFIE of INCR register + * + * @param pMsc MSCInstance + * @return CFIE enable + */ +LOCAL_INLINE bool MSC_HWA_GetCfieEnable(MSC_Type *const pMsc) +{ + return (pMsc->INCR & MSC_INCR_CFIE_MASK) == MSC_INCR_CFIE_MASK ? true : false; +} + +/** + * @brief Set the CFIE of INCR register + * + * @param pMsc MSCInstance + * @param bEnable enable CFIE + */ +LOCAL_INLINE void MSC_HWA_SetCfieEnable(MSC_Type *const pMsc, bool bEnable) +{ + pMsc->INCR = (pMsc->INCR & ~MSC_INCR_CFIE_MASK) | MSC_INCR_CFIE(bEnable); +} + +/** + * @brief Check the DFIE of INCR register + * + * @param pMsc MSCInstance + * @return DFIE enable + */ +LOCAL_INLINE bool MSC_HWA_GetDfieEnable(MSC_Type *const pMsc) +{ + return (pMsc->INCR & MSC_INCR_DFIE_MASK) == MSC_INCR_DFIE_MASK ? true : false; +} + +/** + * @brief Set the DFIE of INCR register + * + * @param pMsc MSCInstance + * @param bEnable enable DFIE + */ +LOCAL_INLINE void MSC_HWA_SetDfieEnable(MSC_Type *const pMsc, bool bEnable) +{ + pMsc->INCR = (pMsc->INCR & ~MSC_INCR_DFIE_MASK) | MSC_INCR_DFIE(bEnable); +} + +/** + * @brief Check the TOIE of RTOR register + * + * @param pMsc MSCInstance + * @return TOIE enable + */ +LOCAL_INLINE bool MSC_HWA_GetToieEnable(MSC_Type *const pMsc) +{ + return (pMsc->RTOR & MSC_RTOR_TOIE_MASK) == MSC_RTOR_TOIE_MASK ? true : false; +} + +/** + * @brief Set the TOIE of RTOR register + * + * @param pMsc MSCInstance + * @param bEnable enable TOIE + */ +LOCAL_INLINE void MSC_HWA_SetToieEnable(MSC_Type *const pMsc, bool bEnable) +{ + pMsc->RTOR = (pMsc->RTOR & ~MSC_RTOR_TOIE_MASK) | MSC_RTOR_TOIE(bEnable); +} + +/** + * @brief Check the TOF of RTOR register + * + * @param pMsc MSCInstance + * @return TOIE enable + */ +LOCAL_INLINE bool MSC_HWA_GetTofEnable(MSC_Type *const pMsc) +{ + return (pMsc->RTOR & MSC_RTOR_TOF_MASK) == MSC_RTOR_TOF_MASK ? true : false; +} + +/** + * @brief Check the TOF of RTOR register + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_ClearTofEnable(MSC_Type *const pMsc) +{ + pMsc->RTOR = (pMsc->RTOR & (~(MSC_RTOR_TOFC_MASK | MSC_RTOR_TOFS_MASK))) | MSC_RTOR_TOFC_MASK; +} + +/** + * @brief Check the RX busy status of RCCSR register + * + * @param pMsc MSCInstance + * @return rx busy status + */ +LOCAL_INLINE bool MSC_HWA_GetRxBusy(MSC_Type *const pMsc) +{ + return (pMsc->RCCSR & MSC_RCCSR_RX_BUSY_MASK) == MSC_RCCSR_RX_BUSY_MASK ? true : false; +} + +/** + * @brief Get the msc RCCSR register + * + * @param pMsc MSCInstance + * @return RCCSR register value + */ +LOCAL_INLINE uint32_t MSC_HWA_GetRccsr(MSC_Type *const pMsc) +{ + return pMsc->RCCSR; +} + +/** + * @brief Set the RCCSR register + * + * @param pMsc MSCInstance + * @param u32Value RCCSR value + */ +LOCAL_INLINE void MSC_HWA_SetRccsr(MSC_Type *const pMsc, uint32_t u32Value) +{ + pMsc->RCCSR = u32Value; +} + +/** + * @brief Get the DATA of RDR0 register + * + * @param pMsc MSCInstance + * @return RDATA value + */ +LOCAL_INLINE uint8_t MSC_HWA_GetRdr0Data(MSC_Type *const pMsc) +{ + return (uint8_t)((pMsc->RDR0 & MSC_RDR0_RDATA_MASK) >> MSC_RDR0_RDATA_SHIFT); +} + +/** + * @brief Get the LAF of RDR0 register + * + * @param pMsc MSCInstance + * @return LAF value + */ +LOCAL_INLINE uint8_t MSC_HWA_GetRdr0Addr(MSC_Type *const pMsc) +{ + return (uint8_t)((pMsc->RDR0 & MSC_RDR0_LAF_MASK) >> MSC_RDR0_LAF_SHIFT); +} + +/** + * @brief Get the VLD of RDR0 register + * + * @param pMsc MSCInstance + * @return VLD value + */ +LOCAL_INLINE bool MSC_HWA_GetRdr0Vld(MSC_Type *const pMsc) +{ + return (pMsc->RDR0 & MSC_RDR0_VLD_MASK) == MSC_RDR0_VLD_MASK ? true : false; +} + +/** + * @brief Get the RERR of RDR0 register + * + * @param pMsc MSCInstance + * @return RERR value + */ +LOCAL_INLINE MSC_ReceiveStatusType MSC_HWA_GetRdr0Rerr(MSC_Type *const pMsc) +{ + uint32_t u32Tempvalue = (pMsc->RDR0 & MSC_RDR0_RERR_MASK) >> MSC_RDR0_RERR_SHIFT; + return (MSC_ReceiveStatusType)u32Tempvalue; +} + +/** + * @brief Clear the VLD of register + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_ClearRdr0Vld(MSC_Type *const pMsc) +{ + pMsc->RDR0 |= MSC_RDR0_CLR_MASK; +} + + +/** + * @brief Get the DATA of RDR1 register + * + * @param pMsc MSCInstance + * @return RDATA value + */ +LOCAL_INLINE uint8_t MSC_HWA_GetRdr1Data(MSC_Type *const pMsc) +{ + return (uint8_t)((pMsc->RDR1 & MSC_RDR1_RDATA_MASK) >> MSC_RDR1_RDATA_SHIFT); +} + +/** + * @brief Get the LAF of RDR1 register + * + * @param pMsc MSCInstance + * @return LAF value + */ +LOCAL_INLINE uint8_t MSC_HWA_GetRdr1Addr(MSC_Type *const pMsc) +{ + return (uint8_t)((pMsc->RDR1 & MSC_RDR1_LAF_MASK) >> MSC_RDR1_LAF_SHIFT); +} + +/** + * @brief Get the VLD of RDR1 register + * + * @param pMsc MSCInstance + * @return VLD value + */ +LOCAL_INLINE bool MSC_HWA_GetRdr1Vld(MSC_Type *const pMsc) +{ + return (pMsc->RDR1 & MSC_RDR1_VLD_MASK) == MSC_RDR1_VLD_MASK ? true : false; +} + +/** + * @brief Get the RERR of RDR1 register + * + * @param pMsc MSCInstance + * @return RERR value + */ +LOCAL_INLINE MSC_ReceiveStatusType MSC_HWA_GetRdr1Rerr(MSC_Type *const pMsc) +{ + uint32_t u32Tempvalue = (pMsc->RDR1 & MSC_RDR1_RERR_MASK) >> MSC_RDR1_RERR_SHIFT; + return (MSC_ReceiveStatusType)u32Tempvalue ; +} + +/** + * @brief Clear the VLD of register + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_ClearRdr1Vld(MSC_Type *const pMsc) +{ + pMsc->RDR1 |= MSC_RDR1_CLR_MASK; +} + + +/** + * @brief Get the DATA of RDR2 register + * + * @param pMsc MSCInstance + * @return RDATA value + */ +LOCAL_INLINE uint8_t MSC_HWA_GetRdr2Data(MSC_Type *const pMsc) +{ + return (uint8_t)((pMsc->RDR2 & MSC_RDR2_RDATA_MASK) >> MSC_RDR2_RDATA_SHIFT); +} + +/** + * @brief Get the LAF of RDR2 register + * + * @param pMsc MSCInstance + * @return LAF value + */ +LOCAL_INLINE uint8_t MSC_HWA_GetRdr2Addr(MSC_Type *const pMsc) +{ + return (uint8_t)((pMsc->RDR2 & MSC_RDR2_LAF_MASK) >> MSC_RDR2_LAF_SHIFT); +} + +/** + * @brief Get the VLD of RDR2 register + * + * @param pMsc MSCInstance + * @return VLD value + */ +LOCAL_INLINE bool MSC_HWA_GetRdr2Vld(MSC_Type *const pMsc) +{ + return (pMsc->RDR2 & MSC_RDR2_VLD_MASK) == MSC_RDR2_VLD_MASK ? true : false; +} + +/** + * @brief Get the RERR of RDR2 register + * + * @param pMsc MSCInstance + * @return RERR value + */ +LOCAL_INLINE MSC_ReceiveStatusType MSC_HWA_GetRdr2Rerr(MSC_Type *const pMsc) +{ + uint32_t u32Tempvalue = (pMsc->RDR2 & MSC_RDR2_RERR_MASK) >> MSC_RDR2_RERR_SHIFT; + return (MSC_ReceiveStatusType)u32Tempvalue; +} + +/** + * @brief Clear the VLD of register + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_ClearRdr2Vld(MSC_Type *const pMsc) +{ + pMsc->RDR2 |= MSC_RDR2_CLR_MASK; +} + + +/** + * @brief Get the DATA of RDR3 register + * + * @param pMsc MSCInstance + * @return RDATA value + */ +LOCAL_INLINE uint8_t MSC_HWA_GetRdr3Data(MSC_Type *const pMsc) +{ + return (uint8_t)(pMsc->RDR3 & MSC_RDR3_RDATA_MASK) >> MSC_RDR3_RDATA_SHIFT; +} + +/** + * @brief Get the LAF of RDR3 register + * + * @param pMsc MSCInstance + * @return LAF value + */ +LOCAL_INLINE uint8_t MSC_HWA_GetRdr3Addr(MSC_Type *const pMsc) +{ + return (uint8_t)((pMsc->RDR3 & MSC_RDR3_LAF_MASK) >> MSC_RDR3_LAF_SHIFT); +} + +/** + * @brief Get the VLD of RDR3 register + * + * @param pMsc MSCInstance + * @return VLD value + */ +LOCAL_INLINE bool MSC_HWA_GetRdr3Vld(MSC_Type *const pMsc) +{ + return (pMsc->RDR3 & MSC_RDR3_VLD_MASK) == MSC_RDR3_VLD_MASK ? true : false; +} + +/** + * @brief Get the RERR of RDR3 register + * + * @param pMsc MSCInstance + * @return RERR value + */ +LOCAL_INLINE MSC_ReceiveStatusType MSC_HWA_GetRdr3Rerr(MSC_Type *const pMsc) +{ + uint32_t u32Tempvalue = (pMsc->RDR3 & MSC_RDR3_RERR_MASK) >> MSC_RDR3_RERR_SHIFT; + return (MSC_ReceiveStatusType)u32Tempvalue; +} + +/** + * @brief Clear the VLD of register + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_ClearRdr3Vld(MSC_Type *const pMsc) +{ + pMsc->RDR3 |= MSC_RDR3_CLR_MASK; +} + +/** + * @brief Reset the msc + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_SetMsrRst(MSC_Type *const pMsc) +{ + pMsc->MSR |= MSC_MSR_RST_MASK; +} + +/** + * @brief Get the reset status + * + * @param pMsc MSCInstance + * @return reset status + */ +LOCAL_INLINE bool MSC_HWA_GetMsrRdone(MSC_Type *const pMsc) +{ + return (bool)(((pMsc->MSR & MSC_MSR_RDONE_MASK) != 0U) ? true : false); +} + +/** + * @brief clear reset status + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_ClearMsrDone(MSC_Type *const pMsc) +{ + pMsc->SRCR = MSC_SRCR_RCLR_MASK; +} + +/** + * @brief Get the msc RTOR register + * + * @param pMsc MSCInstance + * @return RTOR register value + */ +LOCAL_INLINE uint32_t MSC_HWA_GetRtor(MSC_Type *const pMsc) +{ + return pMsc->RTOR; +} + +/** + * @brief Set the msc RTOR register + * + * @param pMsc MSCInstance + * @param u32Value RTOR value + */ +LOCAL_INLINE void MSC_HWA_SetRtor(MSC_Type *const pMsc, uint32_t u32Value) +{ + pMsc->RTOR = u32Value; +} + +/** + * @brief Get the msc TCCTR1 register + * + * @param pMsc MSCInstance + * @return TCCTR1 register value + */ +LOCAL_INLINE uint32_t MSC_HWA_GetTcctr1(MSC_Type *const pMsc) +{ + return pMsc->TCCTR1; +} + +/** + * @brief Set the msc TCCTR1 register + * + * @param pMsc MSCInstance + * @param u32Value TCCTR1 value + */ +LOCAL_INLINE void MSC_HWA_SetTcctr1(MSC_Type *const pMsc, uint32_t u32Value) +{ + pMsc->TCCTR1 = u32Value; +} + +/** + * @brief Set the EN msc GCR register + * + * @param pMsc MSCInstance + * @param bEnable EN value + */ +LOCAL_INLINE void MSC_HWA_SetMscEnable(MSC_Type *const pMsc, bool bEnable) +{ + pMsc->GCR = (pMsc->GCR & ~MSC_GCR_EN_MASK) | MSC_GCR_EN(bEnable); +} + +/** + * @brief Set the WP_EN of msc GCR register + * + * @param pMsc MSCInstance + * @param bEnable WP_EN value + */ +LOCAL_INLINE void MSC_HWA_SetMscWriteProtection(MSC_Type *const pMsc, bool bEnable) +{ + pMsc->GCR = (pMsc->GCR & ~MSC_GCR_WP_EN_MASK) | MSC_GCR_WP_EN(bEnable); +} + +/** + * @brief Unlock the msc CCULR register + * + * @param pMsc MSCInstance + */ +LOCAL_INLINE void MSC_HWA_Unlock(MSC_Type *const pMsc) +{ + pMsc->CCULR = 0x10248888U; +} + + +/** @}*/ /* HwA_msc */ + +#endif /* #ifndef _HWA_MSC_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_overlay.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_overlay.h new file mode 100644 index 0000000..1e181b5 --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_overlay.h @@ -0,0 +1,315 @@ +/** + * @file HwA_overlay.h + * @author Flagchip + * @brief FC4xxx Overlay hardware access layer + * @version 0.1.0 + * @date 2023-12-25 + * + * @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. + * + */ + +/******************************************************************************** +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2023-12-29 Flagchip0038 N/A First version for FC7240 +********************************************************************************/ + +#ifndef _HWA_OVERLAY_H_ +#define _HWA_OVERLAY_H_ + +#include "device_header.h" + +/** + * @defgroup HwA_overlay + * @ingroup fc7xxx_hwa_overlay + * @{ + */ + + +/** Overlay Region Count */ +#define OVERLYA_REGION_CNT 3U + +/** FAR source address */ +#define OVERLAY_FAR_SRC 0x08000000U + +/** FAR max size */ +#define OVERLAY_FAR_SIZE_MAX 0x2000000U +/** FAR size align */ +#define OVERLAY_FAR_SIZE_ALIGN 0x10000U +/** FAR size max mask **/ +#define OVERLAY_FAR_SIZE_MASK 0xFFFFU + +/** + * @brief OVERlay Region size + * + */ +typedef enum +{ + OVERLAY_OVERLAYSIZE_1KB = 0x1, /**< OVERLAY_OVERLAYSIZE_1KB, remapping overlay region size to 1KB */ + OVERLAY_OVERLAYSIZE_2KB = 0x2, /**< OVERLAY_OVERLAYSIZE_2KB, remapping overlay region size to 2KB */ + OVERLAY_OVERLAYSIZE_4KB = 0x4, /**< OVERLAY_OVERLAYSIZE_4KB, remapping overlay region size to 4KB */ + OVERLAY_OVERLAYSIZE_8KB = 0x8, /**< OVERLAY_OVERLAYSIZE_8KB, remapping overlay region size to 8KB */ + OVERLAY_OVERLAYSIZE_16KB = 0x10, /**< OVERLAY_OVERLAYSIZE_16KB, remapping overlay region size to 16KB */ + OVERLAY_OVERLAYSIZE_32KB = 0x20, /**< OVERLAY_OVERLAYSIZE_32KB, remapping overlay region size to 32KB */ + OVERLAY_OVERLAYSIZE_64KB = 0x40 /**< OVERLAY_OVERLAYSIZE_64KB, remapping overlay region size to 64KB */ +}OVERLAY_OverlaySizeType; + +/** + * @brief FAR Size + * + */ +typedef enum +{ + OVERLAY_FARUINTSIZE_64KB = 0x10000, /**< OVERLAY_FARUINTSIZE_64KB, remapping far uint size to 64KB */ +}OVERLAY_FARSizeType; + +/** + * @brief enable overlay global switch + * + */ +LOCAL_INLINE void OVERLAY_HWA_OverlayEnable(void) +{ + AHB_OVERLAY->GLOBAL_EN |= AHB_OVERLAY_GLOBAL_EN_OVERLAY_EN_MASK; +} + +/** + * @brief disable overlay global switch + * + */ +LOCAL_INLINE void OVERLAY_HWA_OverlayDisable(void) +{ + AHB_OVERLAY->GLOBAL_EN &= ~((uint32_t)AHB_OVERLAY_GLOBAL_EN_OVERLAY_EN_MASK); +} + +/** + * @brief enable far global switch + * + */ +LOCAL_INLINE void OVERLAY_HWA_FAREnable(void) +{ + AHB_OVERLAY->GLOBAL_EN |= AHB_OVERLAY_GLOBAL_EN_FAR_EN_MASK; +} + +/** + * @brief disable far global switch + * + */ +LOCAL_INLINE void OVERLAY_HWA_FARDisable(void) +{ + AHB_OVERLAY->GLOBAL_EN &= ~((uint32_t)AHB_OVERLAY_GLOBAL_EN_FAR_EN_MASK); +} + +/** + * @brief enable overlay region 0 + * + */ +LOCAL_INLINE void OVERLAY_HWA_OverlayRegion0Enable(void) +{ + AHB_OVERLAY->REGION_0_EN |= AHB_OVERLAY_REGION_0_EN_REGION0_EN_MASK; +} + +/** + * @brief disable overlay region 0 + * + */ +LOCAL_INLINE void OVERLAY_HWA_OverlayRegion0Disable(void) +{ + AHB_OVERLAY->REGION_0_EN &= ~((uint32_t)AHB_OVERLAY_REGION_0_EN_REGION0_EN_MASK); +} + +/** + * @brief Set Overlay Region 0 Source + * + * @param u32Src Source address + */ +LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion0Src(uint32_t u32Src) +{ + AHB_OVERLAY->REGION_0_SRC = AHB_OVERLAY_REGION_0_SRC_REGION0_SRC(u32Src); +} + +/** + * @brief Set Overlay Region 0 Destination + * + * @param u32Dst Destination address + */ +LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion0Dst(uint32_t u32Dst) +{ + AHB_OVERLAY->REGION_0_DST = AHB_OVERLAY_REGION_0_DST_REGION0_DST(u32Dst); +} + +/** + * @brief Set Overlay Region 0 Size + * + * @param eSize size + */ +LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion0Size(OVERLAY_OverlaySizeType eSize) +{ + AHB_OVERLAY->REGION_0_SIZE = AHB_OVERLAY_REGION_0_SIZE_REGION0_SIZE((uint32_t)eSize); +} + + + +/** + * @brief enable overlay region 1 + * + */ +LOCAL_INLINE void OVERLAY_HWA_OverlayRegion1Enable(void) +{ + AHB_OVERLAY->REGION_1_EN |= AHB_OVERLAY_REGION_1_EN_REGION1_EN_MASK; +} + +/** + * @brief disable overlay region 1 + * + */ +LOCAL_INLINE void OVERLAY_HWA_OverlayRegion1Disable(void) +{ + AHB_OVERLAY->REGION_1_EN &= ~((uint32_t)AHB_OVERLAY_REGION_1_EN_REGION1_EN_MASK); +} + +/** + * @brief Set Overlay Region 1 Source + * + * @param u32Src Source address + */ +LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion1Src(uint32_t u32Src) +{ + AHB_OVERLAY->REGION_1_SRC = AHB_OVERLAY_REGION_1_SRC_REGION1_SRC(u32Src); +} + +/** + * @brief Set Overlay Region 1 Destination + * + * @param u32Dst Destination address + */ +LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion1Dst(uint32_t u32Dst) +{ + AHB_OVERLAY->REGION_1_DST = AHB_OVERLAY_REGION_1_DST_REGION1_DST(u32Dst); +} + +/** + * @brief Set Overlay Region 1 Size + * + * @param eSize size + */ +LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion1Size(OVERLAY_OverlaySizeType eSize) +{ + AHB_OVERLAY->REGION_1_SIZE = AHB_OVERLAY_REGION_1_SIZE_REGION1_SIZE((uint32_t)eSize); +} + + +/** + * @brief enable overlay region 2 + * + */ +LOCAL_INLINE void OVERLAY_HWA_OverlayRegion2Enable(void) +{ + AHB_OVERLAY->REGION_2_EN |= AHB_OVERLAY_REGION_2_EN_REGION2_EN_MASK; +} + +/** + * @brief disable overlay region 2 + * + */ +LOCAL_INLINE void OVERLAY_HWA_OverlayRegion2Disable(void) +{ + AHB_OVERLAY->REGION_2_EN &= ~((uint32_t)AHB_OVERLAY_REGION_2_EN_REGION2_EN_MASK); +} + +/** + * @brief Set Overlay Region 2 Source + * + * @param u32Src Source address + */ +LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion2Src(uint32_t u32Src) +{ + AHB_OVERLAY->REGION_2_SRC = AHB_OVERLAY_REGION_2_SRC_REGION2_SRC(u32Src); +} + +/** + * @brief Set Overlay Region 2 Destination + * + * @param u32Dst Destination address + */ +LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion2Dst(uint32_t u32Dst) +{ + AHB_OVERLAY->REGION_2_DST = AHB_OVERLAY_REGION_2_DST_REGION2_DST(u32Dst); +} + +/** + * @brief Set Overlay Region 2 Size + * + * @param eSize size + */ +LOCAL_INLINE void OVERLAY_HWA_SetOverlayRegion2Size(OVERLAY_OverlaySizeType eSize) +{ + AHB_OVERLAY->REGION_2_SIZE = AHB_OVERLAY_REGION_2_SIZE_REGION2_SIZE((uint32_t)eSize); +} + + + + +/** + * @brief Set Far Destination + * + * @param u32Dst Destination address, must pflash + */ +LOCAL_INLINE void OVERLAY_HWA_SetFarDst(uint32_t u32Dst) +{ + AHB_OVERLAY->FAR_DST = AHB_OVERLAY_FAR_DST_FAR_DST_ADDR(u32Dst); +} + +/** + * @brief Set Far Size + * + * @param u32Size size=(u32Size+1)*64KB + */ +LOCAL_INLINE void OVERLAY_HWA_SetFarSize(uint32_t u32Size) +{ + AHB_OVERLAY->FAR_SIZE = AHB_OVERLAY_FAR_SIZE_FAR_SIZE_VAL(u32Size); +} + + +/** + * @brief enable error interrupt + * + */ +LOCAL_INLINE void OVERLAY_HWA_ErrorInterruptEnable(void) +{ + AHB_OVERLAY->INTR_EN |= AHB_OVERLAY_INTR_EN_INTR_ENABLE_MASK; +} + +/** + * @brief disable error interrupt + * + */ +LOCAL_INLINE void OVERLAY_HWA_ErrorInterruptDisable(void) +{ + AHB_OVERLAY->INTR_EN &= ~((uint32_t)AHB_OVERLAY_INTR_EN_INTR_ENABLE_MASK); +} + +/** + * @brief get error flag + * + */ +LOCAL_INLINE uint32 OVERLAY_HWA_GetErrorFlag(void) +{ + return (AHB_OVERLAY->INTR_FLAG & AHB_OVERLAY_INTR_FLAG_MASK); +} + +/** + * @brief clear error flag + * + */ +LOCAL_INLINE uint32 OVERLAY_HWA_ClrErrorFlag(uint32_t u32ClrBits) +{ + return AHB_OVERLAY->INTR_CLR |= AHB_OVERLAY_INTR_FLAG_MASK & u32ClrBits; +} + + +/** @}*/ + +#endif /* _HWA_OVERLAY_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_pcc.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_pcc.h new file mode 100644 index 0000000..980c653 --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_pcc.h @@ -0,0 +1,191 @@ +/** + * @file HwA_pcc.h + * @author Flagchip085 + * @brief FC7xxx PCC register API + * @version 0.1.0 + * @date 2024-01-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240 + ******************************************************************************** */ +#ifndef HWA_INCLUDE_HWA_PCC_H_ +#define HWA_INCLUDE_HWA_PCC_H_ +#include "device_header.h" + +/** + * @defgroup HwA_pcc + * @ingroup HwA_pcc + * @{ + */ + +/** @brief Marco for PCCn Bit Field definition */ +#define PCC_CGC_MASK 0x800000U +#define PCC_CGC_SHIFT 23U +#define PCC_CGC_WIDTH 1U +#define PCC_CGC(x) (((uint32_t)(((uint32_t)(x))<>PCC_CGC_SHIFT) + +#define PCC_SEL_MASK 0x700000U +#define PCC_SEL_SHIFT 20U +#define PCC_SEL_WIDTH 3U +#define PCC_SEL(x) (((uint32_t)(((uint32_t)(x))<>PCC_SEL_SHIFT) + +#define PCC_DIV_MASK 0x7U +#define PCC_DIV_SHIFT 0U +#define PCC_DIV_WIDTH 3U +#define PCC_DIV(x) (((uint32_t)(((uint32_t)(x))<>PCC_DIV_SHIFT) + +#define PCC_SWR_MASK 0x10000u + +/** + * @brief defined the clock source for function clock,match with PCC_XXX[SEL] bit filed. + */ +typedef enum +{ + PCC_CLKGATE_SRC_OFF_OR_TCLK = 0U, + PCC_CLKGATE_SRC_FOSCDIV = 1U, + PCC_CLKGATE_SRC_SIRCDIV = 2U, + PCC_CLKGATE_SRC_FIRCDIV = 3U, + PCC_CLKGATE_SRC_RESERVE0 = 4U, + PCC_CLKGATE_SRC_PLL1DIV = 5U, + PCC_CLKGATE_SRC_PLL0DIV = 6U, + PCC_CLKGATE_SRC_RESERVE1 = 7U, + PCC_CLKGATE_UNINVOLVED = 8U +} PCC_ClkGateSrcType; + +/** + * @brief define the clock divider,match with PCC_XXX[DIV] bit filed. + */ +typedef enum +{ + PCC_CLK_DIV_BY1 = 0U, /*!< Divide by 1 (pass-through, no clock divide) */ + PCC_CLK_DIV_BY2 = 1U, /*!< Divide by 2 */ + PCC_CLK_DIV_BY3 = 2U, /*!< Divide by 3 */ + PCC_CLK_DIV_BY4 = 3U, /*!< Divide by 4 */ + PCC_CLK_DIV_BY5 = 4U, /*!< Divide by 5 */ + PCC_CLK_DIV_BY6 = 5U, /*!< Divide by 6 */ + PCC_CLK_DIV_BY7 = 6U, /*!< Divide by 7 */ + PCC_CLK_DIV_BY8 = 7U, /*!< Divide by 8 */ + PCC_CLK_UNINVOLVED = 8U /*!< Current peripheral dose not contain DIV configuration */ +} PCC_ClkDivType; + + +/** + * @brief Get PCC register value + * + * @param u32Offset the PCC register offset + * @return uint32_t PCC register value + */ +LOCAL_INLINE uint32_t PCC_HWA_GetRegister(uint32_t u32Offset) +{ + return *((uint32_t *)((uint32_t)PCC_BASE + u32Offset)); +} + +/** + * @brief Set PCC register value + * + * @param u32Offset the PCC register offset + * @param eValue value to set + */ +LOCAL_INLINE void PCC_HWA_SetRegister(uint32_t u32Offset,uint32_t eValue) +{ + *((uint32_t *)((uint32_t)PCC_BASE + u32Offset)) = eValue; +} + +/** + * @brief Get PCC clock gate control + * + * @param u32Offset the PCC register offset + * @return bool PCC clock enabled or disabled + */ +LOCAL_INLINE bool PCC_HWA_GetClockGateControl(uint32_t u32Offset) +{ + uint32_t u32Value = *((uint32_t *)((uint32_t)PCC_BASE + u32Offset)); + return (bool)PCC_GetCGC(u32Value); +} + +/** + * @brief Set PCC clock gate control + * + * @param u32Offset the PCC register offset + * @param eSrc PCC clock source + */ +LOCAL_INLINE void PCC_HWA_SetClockGateControl(uint32_t u32Offset,bool bEnable) +{ + uint32_t *pRegister = (uint32_t *)((uint32_t)PCC_BASE + u32Offset); + *pRegister = ((*pRegister) & (~PCC_CGC_MASK)) | PCC_CGC(bEnable); +} + +/** + * @brief Get PCC clock source + * + * @param u32Offset the PCC register offset + * @return PCC_ClkGateSrcType PCC clock source + */ +LOCAL_INLINE PCC_ClkGateSrcType PCC_HWA_GetClockSource(uint32_t u32Offset) +{ + uint32_t u32Value = *((uint32_t *)((uint32_t)PCC_BASE + u32Offset)); + return (PCC_ClkGateSrcType)PCC_GetSEL(u32Value); +} + +/** + * @brief Set PCC clock source + * + * @param u32Offset the PCC register offset + * @param eSrc PCC clock source + */ +LOCAL_INLINE void PCC_HWA_SetClockSource(uint32_t u32Offset,PCC_ClkGateSrcType eSrc) +{ + uint32_t *pRegister = (uint32_t *)((uint32_t)PCC_BASE + u32Offset); + *pRegister = ((*pRegister) & (~PCC_SEL_MASK)) | PCC_SEL(eSrc); +} + +/** + * @brief PCC peripheral software reset + * + * @param u32Offset the PCC register offset + */ +LOCAL_INLINE void PCC_HWA_SoftwareReset(uint32_t u32Offset) +{ + *((uint32_t *)((uint32_t)PCC_BASE + u32Offset)) |= (uint32_t)PCC_SWR_MASK; + *((uint32_t *)((uint32_t)PCC_BASE + u32Offset)) &= ~(uint32_t)PCC_SWR_MASK; +} + +/** + * @brief Get PCC divider + * + * @param u32Offset the PCC register offset + * @return PCC_ClkDivType PCC clock divider + */ +LOCAL_INLINE PCC_ClkDivType PCC_HWA_GetDivider(uint32_t u32Offset) +{ + uint32_t u32Value = *((uint32_t *)((uint32_t)PCC_BASE + u32Offset)); + return (PCC_ClkDivType)PCC_GetDIV(u32Value); +} + +/** + * @brief Set PCC register value + * + * @param u32Offset the PCC register offset + * @param eDivider PCC clock divider + */ +LOCAL_INLINE void PCC_HWA_SetDivider(uint32_t u32Offset,PCC_ClkDivType eDivider) +{ + uint32_t *pRegister = (uint32_t *)((uint32_t)PCC_BASE + u32Offset); + *pRegister = ((*pRegister) & (~PCC_DIV_MASK)) | PCC_DIV(eDivider); +} + + + +/** @}*/ + +#endif /* HWA_INCLUDE_HWA_PCC_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_pmc.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_pmc.h new file mode 100644 index 0000000..67ad751 --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_pmc.h @@ -0,0 +1,92 @@ +/** + * @file HwA_pmc.h + * @author Flagchip0105 + * @brief FC7xxx PMC register API + * @version 0.1.0 + * @date 2024-01-08 + * + * @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-08 Flagchip0105 N/A First version for FC7240 + ******************************************************************************** */ +#ifndef HWA_INCLUDE_HWA_PMC_H_ +#define HWA_INCLUDE_HWA_PMC_H_ +#include "device_header.h" + +/** + * @defgroup HwA_pmc + * @ingroup fc7xxx_driver_pmc + * @{ + */ + +/** + * @brief get PMC LVCSR register + * + * @return uint32_t LVCSR register value + */ +LOCAL_INLINE uint32_t PMC_HWA_GetLVCSRRegister(void) +{ + return (uint32)(PMC->LVSCR); +} + +/** + * @brief set PMC LVCSR register. + * + * This function configures the PMC LVCSR registe. + * + * @param u32LvcsrValue Set PMC LVCSR register value. + */ +LOCAL_INLINE void PMC_HWA_SetLVCSRRegister(uint32_t u32LvcsrValue) +{ + PMC->LVSCR = u32LvcsrValue; +} + +/** + * @brief get PMC CONFIG register + * + * @return uint32_t CONFIG register value + */ +LOCAL_INLINE uint32_t PMC_HWA_GetConfigRegister(void) +{ + return (uint32)(PMC -> CONFIG); +} + +/** + * @brief set PMC CONFIG register. + * + * This function configures the PMC CONFIG registe. + * + * @param u32LVSCRValue Set PMC CONFIG register value. + */ +LOCAL_INLINE void PMC_HWA_SetConfigRegister(uint32_t u32LVSCRValue) +{ + PMC -> CONFIG = u32LVSCRValue; +} + +/** + * @brief Unlock control for V15_EXT_EN and V15_AUTOSW + * + */ +LOCAL_INLINE void PMC_HWA_UnlockConfigRegister(void) +{ + PMC->CONFIG &= ~(uint32_t)PMC_CONFIG_V15_LOCK_MASK; +} + +/** + * @brief lock control for V15_EXT_EN and V15_AUTOSW + * + */ +LOCAL_INLINE void PMC_HWA_LockConfigRegister(void) +{ + PMC->CONFIG |= (uint32_t)PMC_CONFIG_V15_LOCK_MASK; +} + +/** @}*/ + +#endif /* HWA_INCLUDE_HWA_PMC_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_port.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_port.h new file mode 100644 index 0000000..54f7288 --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_port.h @@ -0,0 +1,2348 @@ +/** + * @file HwA_port.h + * @author Flagchip + * @brief FC7xxx PORT hardware access layer + * @version 0.1.0 + * @date 2023-02-13 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2022-11-18 Flagchip071 N/A First version for FC7xxx + ******************************************************************************** */ + +#ifndef _HWA_PORT_H_ +#define _HWA_PORT_H_ + +#include "device_header.h" + +/********* Local typedef ************/ +/** @brief Port Mode Type */ +typedef uint32_t Port_PinModeType; + +/** @brief PORTA 0 Mode enumeration */ +typedef enum +{ +PORTA_0_ADC1_SE30 = 0U, +PORTA_0_GPIO = 1U, +PORTA_0_FTU2_CH1 = 2U, +PORTA_0_AONTIMER0_CLK1 = 3U, +PORTA_0_SENT0_RXD3 = 4U, +PORTA_0_TPU_CH1 = 5U, +PORTA_0_FCUART0_CTS = 6U, +PORTA_0_TRGSEL_OUT3 = 7U, +} PORT_A0MuxType; + +/** @brief PORTA 1 Mode enumeration */ +typedef enum +{ +PORTA_1_ADC1_SE29 = 0U, +PORTA_1_GPIO = 1U, +PORTA_1_FTU1_CH1 = 2U, +PORTA_1_AONTIMER0_CLK2 = 3U, +PORTA_1_SENT0_RXD2 = 4U, +PORTA_1_FTU1_QD_PHB = 5U, +PORTA_1_FCUART0_RTS = 6U, +PORTA_1_TRGSEL_OUT0 = 7U, +} PORT_A1MuxType; + +/** @brief PORTA 10 Mode enumeration */ +typedef enum +{ +PORTA_10_GPIO = 1U, +PORTA_10_FTU1_CH4 = 2U, +PORTA_10_AONTIMER0_CLK0 = 3U, +PORTA_10_TPU_CH30 = 4U, +PORTA_10_FCIIC0_SCL = 5U, +PORTA_10_JTAG_TDO = 7U, +} PORT_A10MuxType; + +/** @brief PORTA 11 Mode enumeration */ +typedef enum +{ +PORTA_11_GPIO = 1U, +PORTA_11_FTU1_CH5 = 2U, +PORTA_11_LP_WAKEUP2 = 3U, +PORTA_11_TPU_CH29 = 4U, +PORTA_11_FCSPI0_PCS0 = 5U, +PORTA_11_NMI_b = 7U, +} PORT_A11MuxType; + +/** @brief PORTA 12 Mode enumeration */ +typedef enum +{ +PORTA_12_GPIO = 1U, +PORTA_12_FTU1_CH6 = 2U, +PORTA_12_FLEXCAN1_RX = 3U, +PORTA_12_FCSPI0_SOUT = 5U, +PORTA_12_FTU1_QD_PHB = 6U, +PORTA_12_TPU_CH9 = 7U, +} PORT_A12MuxType; + +/** @brief PORTA 13 Mode enumeration */ +typedef enum +{ +PORTA_13_ADC0_SE20 = 0U, +PORTA_13_GPIO = 1U, +PORTA_13_FTU1_CH7 = 2U, +PORTA_13_FLEXCAN1_TX = 3U, +PORTA_13_CMP1_OUT = 4U, +PORTA_13_FCUART0_RX = 5U, +PORTA_13_FTU1_QD_PHA = 6U, +PORTA_13_TPU_CH8 = 7U, +} PORT_A13MuxType; + +/** @brief PORTA 14 Mode enumeration */ +typedef enum +{ +PORTA_14_ADC0_SE21 = 0U, +PORTA_14_GPIO = 1U, +PORTA_14_FTU_FLT17 = 2U, +PORTA_14_AONTIMER0_CLK1 = 3U, +PORTA_14_FCUART0_TX = 5U, +PORTA_14_TPU_CH7 = 6U, +} PORT_A14MuxType; + +/** @brief PORTA 15 Mode enumeration */ +typedef enum +{ +PORTA_15_ADC0_SE26 = 0U, +PORTA_15_GPIO = 1U, +PORTA_15_FTU1_CH2 = 2U, +PORTA_15_TRGSEL_OUT0 = 5U, +PORTA_15_FLEXCAN3_RX = 6U, +PORTA_15_TPU_CH5 = 7U, +} PORT_A15MuxType; + +/** @brief PORTA 16 Mode enumeration */ +typedef enum +{ +PORTA_16_ADC0_SE28 = 0U, +PORTA_16_GPIO = 1U, +PORTA_16_FTU1_CH3 = 2U, +PORTA_16_FCSPI1_PCS2 = 3U, +PORTA_16_FTU1_QD_PHA = 4U, +PORTA_16_SENT0_RXD1 = 5U, +PORTA_16_FLEXCAN3_TX = 6U, +PORTA_16_TPU_CH4 = 7U, +} PORT_A16MuxType; + +/** @brief PORTA 17 Mode enumeration */ +typedef enum +{ +PORTA_17_GPIO = 1U, +PORTA_17_FTU0_CH6 = 2U, +PORTA_17_FTU7_CH0 = 3U, +PORTA_17_FLEXCAN2_TX = 4U, +PORTA_17_FCSPI5_PCS0 = 5U, +PORTA_17_FTU_FLT15 = 6U, +PORTA_17_FCUART3_RX = 7U, +} PORT_A17MuxType; + +/** @brief PORTA 18 Mode enumeration */ +typedef enum +{ +PORTA_18_GPIO = 1U, +PORTA_18_FTU4_CH0 = 2U, +PORTA_18_FCUART1_TX = 3U, +PORTA_18_TPU_CH0 = 4U, +PORTA_18_TPU_TCRCLK = 5U, +PORTA_18_FCSPI4_PCS1 = 6U, +} PORT_A18MuxType; + +/** @brief PORTA 19 Mode enumeration */ +typedef enum +{ +PORTA_19_GPIO = 1U, +PORTA_19_FTU4_CH1 = 2U, +PORTA_19_FCUART1_RX = 3U, +PORTA_19_TPU_CH1 = 4U, +PORTA_19_FCSPI4_PCS2 = 6U, +} PORT_A19MuxType; + +/** @brief PORTA 2 Mode enumeration */ +typedef enum +{ +PORTA_2_GPIO = 1U, +PORTA_2_FTU3_CH0 = 2U, +PORTA_2_FCIIC0_SDA = 3U, +PORTA_2_TPU_CH1 = 4U, +PORTA_2_FCSPI5_SOUT = 5U, +PORTA_2_FCUART0_RX = 6U, +} PORT_A2MuxType; + +/** @brief PORTA 20 Mode enumeration */ +typedef enum +{ +PORTA_20_GPIO = 1U, +PORTA_20_FTU4_CH2 = 2U, +PORTA_20_FCUART3_RTS = 3U, +PORTA_20_TPU_CH2 = 4U, +PORTA_20_FLEXCAN2_RX = 5U, +PORTA_20_FCSPI4_PCS3 = 6U, +} PORT_A20MuxType; + +/** @brief PORTA 21 Mode enumeration */ +typedef enum +{ +PORTA_21_GPIO = 1U, +PORTA_21_FTU4_CH3 = 2U, +PORTA_21_FCUART3_CTS = 3U, +PORTA_21_TPU_CH3 = 4U, +PORTA_21_FLEXCAN2_TX = 5U, +} PORT_A21MuxType; + +/** @brief PORTA 23 Mode enumeration */ +typedef enum +{ +PORTA_23_GPIO = 1U, +PORTA_23_FTU4_CH6 = 2U, +PORTA_23_FCUART3_RX = 3U, +PORTA_23_TPU_CH25 = 4U, +PORTA_23_FCSPI4_SCK = 6U, +} PORT_A23MuxType; + +/** @brief PORTA 24 Mode enumeration */ +typedef enum +{ +PORTA_24_GPIO = 1U, +PORTA_24_FTU4_CH7 = 2U, +PORTA_24_FCUART3_TX = 3U, +PORTA_24_TPU_CH4 = 4U, +PORTA_24_FCSPI4_SIN = 6U, +} PORT_A24MuxType; + +/** @brief PORTA 25 Mode enumeration */ +typedef enum +{ +PORTA_25_ADC0_SE0 = 0U, +PORTA_25_GPIO = 1U, +PORTA_25_FTU5_CH0 = 2U, +PORTA_25_FCSPI2_PCS2 = 3U, +PORTA_25_FTU2_CH5 = 4U, +PORTA_25_FCUART2_RX = 5U, +PORTA_25_TPU_TCRCLK = 6U, +PORTA_25_TPU_CH0 = 7U, +} PORT_A25MuxType; + +/** @brief PORTA 26 Mode enumeration */ +typedef enum +{ +PORTA_26_ADC0_SE2 = 0U, +PORTA_26_GPIO = 1U, +PORTA_26_FTU5_CH1 = 2U, +PORTA_26_FTU2_CH4 = 4U, +PORTA_26_FCSPI1_PCS0 = 5U, +PORTA_26_TPU_CH1 = 7U, +} PORT_A26MuxType; + +/** @brief PORTA 27 Mode enumeration */ +typedef enum +{ +PORTA_27_ADC0_SE6 = 0U, +PORTA_27_GPIO = 1U, +PORTA_27_FTU5_CH2 = 2U, +PORTA_27_FLEXCAN0_TX = 3U, +PORTA_27_FCUART0_TX = 4U, +PORTA_27_FCSPI1_SOUT = 5U, +PORTA_27_TPU_CH2 = 7U, +} PORT_A27MuxType; + +/** @brief PORTA 28 Mode enumeration */ +typedef enum +{ +PORTA_28_ADC0_SE7 = 0U, +PORTA_28_GPIO = 1U, +PORTA_28_FTU5_CH3 = 2U, +PORTA_28_FLEXCAN0_RX = 3U, +PORTA_28_FCUART0_RX = 4U, +PORTA_28_FCSPI1_SCK = 5U, +PORTA_28_TPU_CH4 = 7U, +} PORT_A28MuxType; + +/** @brief PORTA 29 Mode enumeration */ +typedef enum +{ +PORTA_29_ADC0_SE9 = 0U, +PORTA_29_GPIO = 1U, +PORTA_29_FTU5_CH4 = 2U, +PORTA_29_FCUART2_TX = 3U, +PORTA_29_FCSPI1_SIN = 5U, +PORTA_29_TPU_CH6 = 7U, +} PORT_A29MuxType; + +/** @brief PORTA 3 Mode enumeration */ +typedef enum +{ +PORTA_3_GPIO = 1U, +PORTA_3_FTU3_CH1 = 2U, +PORTA_3_FCIIC0_SCL = 3U, +PORTA_3_TPU_CH2 = 4U, +PORTA_3_FCSPI5_SCK = 5U, +PORTA_3_FCUART0_TX = 6U, +} PORT_A3MuxType; + +/** @brief PORTA 30 Mode enumeration */ +typedef enum +{ +PORTA_30_GPIO = 1U, +PORTA_30_FTU5_CH5 = 2U, +PORTA_30_FCUART2_RX = 3U, +PORTA_30_TPU_CH7 = 7U, +} PORT_A30MuxType; + +/** @brief PORTA 31 Mode enumeration */ +typedef enum +{ +PORTA_31_ADC0_SE13_CMP0_IN3 = 0U, +PORTA_31_GPIO = 1U, +PORTA_31_FTU5_CH6 = 2U, +PORTA_31_FLEXCAN3_TX = 3U, +PORTA_31_TPU_CH8 = 6U, +PORTA_31_FCSPI0_PCS1 = 7U, +} PORT_A31MuxType; + +/** @brief PORTA 4 Mode enumeration */ +typedef enum +{ +PORTA_4_GPIO = 1U, +PORTA_4_FTU1_CH0 = 2U, +PORTA_4_TRGSEL_OUT7 = 3U, +PORTA_4_CMP0_OUT = 4U, +PORTA_4_LP_WAKEUP4 = 5U, +PORTA_4_JTAG_TMS_SWD_DIO = 7U, +} PORT_A4MuxType; + +/** @brief PORTA 6 Mode enumeration */ +typedef enum +{ +PORTA_6_ADC1_SE9 = 0U, +PORTA_6_GPIO = 1U, +PORTA_6_FTU_FLT13 = 2U, +PORTA_6_FCSPI1_PCS1 = 3U, +PORTA_6_FTU5_CH5 = 4U, +PORTA_6_TRGSEL_OUT4 = 5U, +PORTA_6_FCUART1_CTS = 6U, +PORTA_6_FTU4_CH7 = 7U, +} PORT_A6MuxType; + +/** @brief PORTA 7 Mode enumeration */ +typedef enum +{ +PORTA_7_GPIO = 1U, +PORTA_7_FTU_FLT12 = 2U, +PORTA_7_FTU3_CH1 = 3U, +PORTA_7_FTU5_CH3 = 4U, +PORTA_7_FCSPI1_SCK = 5U, +PORTA_7_FCUART1_RTS = 6U, +PORTA_7_MSC0_EN0 = 7U, +} PORT_A7MuxType; + +/** @brief PORTA 8 Mode enumeration */ +typedef enum +{ +PORTA_8_ADC1_SE3 = 0U, +PORTA_8_GPIO = 1U, +PORTA_8_FCUART2_RX = 2U, +PORTA_8_FTU1_CH0 = 3U, +PORTA_8_CMP0_OUT = 4U, +PORTA_8_FTU_FLT21 = 5U, +PORTA_8_FCUART0_RX = 6U, +PORTA_8_TPU_CH13 = 7U, +} PORT_A8MuxType; + +/** @brief PORTA 9 Mode enumeration */ +typedef enum +{ +PORTA_9_ADC1_SE7 = 0U, +PORTA_9_GPIO = 1U, +PORTA_9_FCUART2_TX = 2U, +PORTA_9_FTU4_CH4 = 3U, +PORTA_9_FTU_FLT20 = 5U, +PORTA_9_FCUART0_TX = 6U, +PORTA_9_TPU_CH12 = 7U, +} PORT_A9MuxType; + +/** @brief PORTB 0 Mode enumeration */ +typedef enum +{ +PORTB_0_ADC1_SE10 = 0U, +PORTB_0_GPIO = 1U, +PORTB_0_FCUART0_RX = 2U, +PORTB_0_FCSPI0_PCS0 = 3U, +PORTB_0_FTU1_CH5 = 4U, +PORTB_0_FLEXCAN0_RX = 5U, +PORTB_0_FTU4_CH6 = 6U, +PORTB_0_MSC0_SDI1 = 7U, +} PORT_B0MuxType; + +/** @brief PORTB 1 Mode enumeration */ +typedef enum +{ +PORTB_1_ADC1_SE11 = 0U, +PORTB_1_GPIO = 1U, +PORTB_1_FCUART0_TX = 2U, +PORTB_1_FCSPI0_SOUT = 3U, +PORTB_1_FTU_TCK0 = 4U, +PORTB_1_FLEXCAN0_TX = 5U, +PORTB_1_FTU4_CH5 = 6U, +PORTB_1_MSC0_EN1 = 7U, +} PORT_B1MuxType; + +/** @brief PORTB 10 Mode enumeration */ +typedef enum +{ +PORTB_10_GPIO = 1U, +PORTB_10_FTU3_CH2 = 2U, +PORTB_10_FLEXCAN0_TX = 3U, +PORTB_10_SENT0_RXD0 = 4U, +PORTB_10_TRGSEL_OUT2 = 5U, +PORTB_10_TPU_CH0 = 6U, +PORTB_10_TPU_TCRCLK = 7U, +} PORT_B10MuxType; + +/** @brief PORTB 11 Mode enumeration */ +typedef enum +{ +PORTB_11_V15_BASE_DRIVER = 0U, +PORTB_11_GPIO = 1U, +PORTB_11_FTU6_CH0 = 2U, +PORTB_11_FCUART2_TX = 3U, +PORTB_11_FLEXCAN0_TX = 4U, +} PORT_B11MuxType; + +/** @brief PORTB 12 Mode enumeration */ +typedef enum +{ +PORTB_12_GPIO = 1U, +PORTB_12_FTU0_CH0 = 2U, +PORTB_12_TPU_CH26 = 5U, +PORTB_12_FCSMU_PIN0 = 7U, +} PORT_B12MuxType; + +/** @brief PORTB 13 Mode enumeration */ +typedef enum +{ +PORTB_13_GPIO = 1U, +PORTB_13_FTU0_CH1 = 2U, +PORTB_13_FCUART6_CTS = 4U, +PORTB_13_TPU_CH25 = 5U, +PORTB_13_FCSMU_PIN1 = 7U, +} PORT_B13MuxType; + +/** @brief PORTB 14 Mode enumeration */ +typedef enum +{ +PORTB_14_ADC1_SE18 = 0U, +PORTB_14_GPIO = 1U, +PORTB_14_FTU0_CH2 = 2U, +PORTB_14_FCSPI1_SCK = 3U, +PORTB_14_TPU_CH5 = 4U, +PORTB_14_FTU5_CH4 = 6U, +PORTB_14_FLEXCAN2_RX = 7U, +} PORT_B14MuxType; + +/** @brief PORTB 15 Mode enumeration */ +typedef enum +{ +PORTB_15_ADC1_SE17 = 0U, +PORTB_15_GPIO = 1U, +PORTB_15_FTU0_CH3 = 2U, +PORTB_15_FCSPI1_SIN = 3U, +PORTB_15_TPU_CH6 = 4U, +PORTB_15_FTU5_CH5 = 6U, +PORTB_15_FLEXCAN2_TX = 7U, +} PORT_B15MuxType; + +/** @brief PORTB 16 Mode enumeration */ +typedef enum +{ +PORTB_16_ADC1_SE16 = 0U, +PORTB_16_GPIO = 1U, +PORTB_16_FTU0_CH4 = 2U, +PORTB_16_FCSPI1_SOUT = 3U, +PORTB_16_TPU_CH7 = 4U, +PORTB_16_FTU5_CH6 = 6U, +} PORT_B16MuxType; + +/** @brief PORTB 17 Mode enumeration */ +typedef enum +{ +PORTB_17_GPIO = 1U, +PORTB_17_FTU0_CH5 = 2U, +PORTB_17_FCSPI1_PCS3 = 3U, +PORTB_17_FLEXCAN2_RX = 4U, +PORTB_17_TRGSEL_OUT3 = 5U, +PORTB_17_FTU5_CH7 = 6U, +PORTB_17_FCUART3_TX = 7U, +} PORT_B17MuxType; + +/** @brief PORTB 18 Mode enumeration */ +typedef enum +{ +PORTB_18_GPIO = 1U, +PORTB_18_FTU5_CH7 = 2U, +PORTB_18_FLEXCAN3_RX = 3U, +PORTB_18_FCSPI4_PCS2 = 4U, +PORTB_18_FCSPI1_PCS1 = 5U, +PORTB_18_TPU_CH9 = 6U, +} PORT_B18MuxType; + +/** @brief PORTB 19 Mode enumeration */ +typedef enum +{ +PORTB_19_CMP0_IN4 = 0U, +PORTB_19_GPIO = 1U, +PORTB_19_FTU6_CH2 = 2U, +PORTB_19_FCUART4_RX = 3U, +PORTB_19_FLEXCAN3_TX = 4U, +PORTB_19_TPU_CH5 = 6U, +} PORT_B19MuxType; + +/** @brief PORTB 20 Mode enumeration */ +typedef enum +{ +PORTB_20_ADC0_SE14 = 0U, +PORTB_20_GPIO = 1U, +PORTB_20_FTU2_CH5 = 2U, +PORTB_20_FCUART1_TX = 3U, +PORTB_20_FTU6_CH2 = 4U, +PORTB_20_TPU_CH10 = 6U, +PORTB_20_SCG_CLKOUT = 7U, +} PORT_B20MuxType; + +/** @brief PORTB 21 Mode enumeration */ +typedef enum +{ +PORTB_21_ADC0_SE15 = 0U, +PORTB_21_GPIO = 1U, +PORTB_21_FTU2_CH4 = 2U, +PORTB_21_FCUART1_RX = 3U, +PORTB_21_FTU6_CH3 = 4U, +PORTB_21_TPU_CH11 = 6U, +} PORT_B21MuxType; + +/** @brief PORTB 22 Mode enumeration */ +typedef enum +{ +PORTB_22_GPIO = 1U, +PORTB_22_FTU_FLT8 = 2U, +PORTB_22_FLEXCAN2_TX = 3U, +PORTB_22_TPU_CH12 = 4U, +PORTB_22_FTU6_CH6 = 5U, +PORTB_22_MSC0_EN0 = 6U, +PORTB_22_FCSPI3_PCS1 = 7U, +} PORT_B22MuxType; + +/** @brief PORTB 23 Mode enumeration */ +typedef enum +{ +PORTB_23_CMP1_IN6 = 0U, +PORTB_23_GPIO = 1U, +PORTB_23_FTU_FLT9 = 2U, +PORTB_23_FCUART1_RX = 3U, +PORTB_23_FTU4_CH7 = 4U, +PORTB_23_FTU7_CH7 = 5U, +PORTB_23_TPU_CH13 = 6U, +PORTB_23_MSC0_FCLP = 7U, +} PORT_B23MuxType; + +/** @brief PORTB 24 Mode enumeration */ +typedef enum +{ +PORTB_24_CMP0_IN5 = 0U, +PORTB_24_GPIO = 1U, +PORTB_24_FTU6_CH3 = 2U, +PORTB_24_FCUART4_TX = 3U, +PORTB_24_FLEXCAN3_RX = 4U, +PORTB_24_TPU_CH6 = 6U, +} PORT_B24MuxType; + +/** @brief PORTB 25 Mode enumeration */ +typedef enum +{ +PORTB_25_GPIO = 1U, +PORTB_25_FTU1_CH2 = 2U, +PORTB_25_FTU1_QD_PHB = 3U, +PORTB_25_FCSPI2_PCS0 = 4U, +PORTB_25_FTU6_CH7 = 5U, +PORTB_25_FCUART3_TX = 6U, +} PORT_B25MuxType; + +/** @brief PORTB 26 Mode enumeration */ +typedef enum +{ +PORTB_26_CMP0_IN6 = 0U, +PORTB_26_GPIO = 1U, +PORTB_26_FTU6_CH4 = 2U, +PORTB_26_FCSPI3_SCK = 3U, +PORTB_26_FCUART3_TX = 4U, +PORTB_26_TPU_CH7 = 6U, +} PORT_B26MuxType; + +/** @brief PORTB 27 Mode enumeration */ +typedef enum +{ +PORTB_27_GPIO = 1U, +PORTB_27_FTU7_CH5 = 2U, +PORTB_27_FTU2_CH2 = 3U, +PORTB_27_FCSPI2_SOUT = 4U, +PORTB_27_FCUART5_RTS = 5U, +PORTB_27_TPU_CH14 = 6U, +} PORT_B27MuxType; + +/** @brief PORTB 28 Mode enumeration */ +typedef enum +{ +PORTB_28_GPIO = 1U, +PORTB_28_FTU7_CH4 = 2U, +PORTB_28_FTU2_CH1 = 3U, +PORTB_28_FCSPI2_SIN = 4U, +PORTB_28_FCUART5_CTS = 5U, +PORTB_28_TPU_CH15 = 6U, +} PORT_B28MuxType; + +/** @brief PORTB 29 Mode enumeration */ +typedef enum +{ +PORTB_29_GPIO = 1U, +PORTB_29_FTU1_CH0 = 2U, +PORTB_29_FCUART5_TX = 3U, +PORTB_29_FCSPI2_SCK = 4U, +PORTB_29_FTU1_QD_PHB = 5U, +PORTB_29_FCUART7_RTS = 6U, +PORTB_29_TPU_CH16 = 7U, +} PORT_B29MuxType; + +/** @brief PORTB 3 Mode enumeration */ +typedef enum +{ +PORTB_3_GPIO = 1U, +PORTB_3_FTU1_CH1 = 2U, +PORTB_3_FCSPI0_SIN = 3U, +PORTB_3_FTU1_QD_PHA = 4U, +PORTB_3_FTU7_CH3 = 5U, +PORTB_3_TPU_CH10 = 6U, +PORTB_3_FCUART5_RX = 7U, +} PORT_B3MuxType; + +/** @brief PORTB 30 Mode enumeration */ +typedef enum +{ +PORTB_30_CMP0_IN7 = 0U, +PORTB_30_GPIO = 1U, +PORTB_30_FTU6_CH5 = 2U, +PORTB_30_FCSPI3_SIN = 3U, +PORTB_30_FCUART3_RX = 4U, +PORTB_30_TPU_CH8 = 6U, +} PORT_B30MuxType; + +/** @brief PORTB 31 Mode enumeration */ +typedef enum +{ +PORTB_31_CMP1_IN0 = 0U, +PORTB_31_GPIO = 1U, +PORTB_31_FTU7_CH7 = 2U, +PORTB_31_FCSPI3_SOUT = 3U, +PORTB_31_FCUART5_TX = 4U, +PORTB_31_TPU_CH9 = 5U, +} PORT_B31MuxType; + +/** @brief PORTB 4 Mode enumeration */ +typedef enum +{ +PORTB_4_GPIO = 1U, +PORTB_4_FTU0_CH4 = 2U, +PORTB_4_FCIIC1_SDA = 3U, +PORTB_4_FCSPI4_SOUT = 4U, +PORTB_4_FTU7_CH6 = 5U, +PORTB_4_ETM_TRACE_D6 = 6U, +PORTB_4_TRGSEL_OUT4 = 7U, +} PORT_B4MuxType; + +/** @brief PORTB 5 Mode enumeration */ +typedef enum +{ +PORTB_5_GPIO = 1U, +PORTB_5_FTU0_CH5 = 2U, +PORTB_5_FCIIC1_SCL = 3U, +PORTB_5_FCSPI4_PCS0 = 4U, +PORTB_5_SCG_CLKOUT = 5U, +PORTB_5_ETM_TRACE_D5 = 6U, +PORTB_5_TRGSEL_OUT5 = 7U, +} PORT_B5MuxType; + +/** @brief PORTB 6 Mode enumeration */ +typedef enum +{ +PORTB_6_XTAL = 0U, +PORTB_6_GPIO = 1U, +PORTB_6_FCIIC0_SDA = 2U, +} PORT_B6MuxType; + +/** @brief PORTB 7 Mode enumeration */ +typedef enum +{ +PORTB_7_EXTAL = 0U, +PORTB_7_GPIO = 1U, +PORTB_7_FCIIC0_SCL = 2U, +} PORT_B7MuxType; + +/** @brief PORTB 8 Mode enumeration */ +typedef enum +{ +PORTB_8_ADC1_SE28 = 0U, +PORTB_8_GPIO = 1U, +PORTB_8_FTU3_CH0 = 2U, +PORTB_8_FLEXCAN0_RX = 3U, +PORTB_8_SENT0_RXD1 = 4U, +PORTB_8_TPU_CH0 = 5U, +PORTB_8_FCUART1_CTS = 6U, +} PORT_B8MuxType; + +/** @brief PORTB 9 Mode enumeration */ +typedef enum +{ +PORTB_9_ADC1_SE25 = 0U, +PORTB_9_GPIO = 1U, +PORTB_9_FTU3_CH1 = 2U, +PORTB_9_FTU1_CH6 = 3U, +PORTB_9_TRGSEL_OUT1 = 5U, +PORTB_9_TPU_CH29 = 6U, +PORTB_9_FCSPI5_PCS0 = 7U, +} PORT_B9MuxType; + +/** @brief PORTC 0 Mode enumeration */ +typedef enum +{ +PORTC_0_GPIO = 1U, +PORTC_0_FTU0_CH0 = 2U, +PORTC_0_FLEXCAN2_RX = 3U, +PORTC_0_TPU_CH15 = 4U, +PORTC_0_FlexCore_TCLK = 5U, +PORTC_0_FTU1_CH6 = 6U, +PORTC_0_FCSPI3_PCS2 = 7U, +} PORT_C0MuxType; + +/** @brief PORTC 1 Mode enumeration */ +typedef enum +{ +PORTC_1_GPIO = 1U, +PORTC_1_FTU0_CH1 = 2U, +PORTC_1_TPU_CH16 = 3U, +PORTC_1_FCSPI2_SOUT = 4U, +PORTC_1_FlexCore_TDI = 5U, +PORTC_1_FTU1_CH7 = 6U, +PORTC_1_FCUART3_TX = 7U, +} PORT_C1MuxType; + +/** @brief PORTC 10 Mode enumeration */ +typedef enum +{ +PORTC_10_ADC1_SE12 = 0U, +PORTC_10_GPIO = 1U, +PORTC_10_FTU3_CH4 = 2U, +PORTC_10_FTU0_CH5 = 3U, +PORTC_10_FCUART6_RX = 4U, +PORTC_10_FTU7_CH1 = 6U, +PORTC_10_TPU_CH8 = 7U, +} PORT_C10MuxType; + +/** @brief PORTC 11 Mode enumeration */ +typedef enum +{ +PORTC_11_ADC1_SE13 = 0U, +PORTC_11_GPIO = 1U, +PORTC_11_FTU3_CH5 = 2U, +PORTC_11_FTU4_CH2 = 3U, +PORTC_11_FCUART6_TX = 4U, +PORTC_11_FCSPI1_PCS0 = 5U, +PORTC_11_FTU7_CH2 = 6U, +PORTC_11_TPU_CH9 = 7U, +} PORT_C11MuxType; + +/** @brief PORTC 12 Mode enumeration */ +typedef enum +{ +PORTC_12_ADC1_SE14 = 0U, +PORTC_12_GPIO = 1U, +PORTC_12_FTU3_CH6 = 2U, +PORTC_12_FTU2_CH6 = 3U, +PORTC_12_FCUART2_CTS = 4U, +PORTC_12_TRGSEL_OUT5 = 5U, +PORTC_12_FCUART7_RX = 6U, +PORTC_12_MSC0_SOP = 7U, +} PORT_C12MuxType; + +/** @brief PORTC 13 Mode enumeration */ +typedef enum +{ +PORTC_13_ADC1_SE15 = 0U, +PORTC_13_GPIO = 1U, +PORTC_13_FTU3_CH7 = 2U, +PORTC_13_FTU2_CH7 = 3U, +PORTC_13_FCUART2_RTS = 4U, +PORTC_13_TRGSEL_OUT6 = 5U, +PORTC_13_FCUART7_TX = 6U, +PORTC_13_MSC0_FCLP = 7U, +} PORT_C13MuxType; + +/** @brief PORTC 14 Mode enumeration */ +typedef enum +{ +PORTC_14_CMP1_IN7 = 0U, +PORTC_14_GPIO = 1U, +PORTC_14_FTU1_CH2 = 2U, +PORTC_14_TPU_CH11 = 3U, +PORTC_14_FCSPI2_PCS0 = 4U, +PORTC_14_FTU1_QD_PHA = 5U, +PORTC_14_TRGSEL_OUT6 = 6U, +} PORT_C14MuxType; + +/** @brief PORTC 15 Mode enumeration */ +typedef enum +{ +PORTC_15_CMP1_IN5 = 0U, +PORTC_15_GPIO = 1U, +PORTC_15_FTU1_CH3 = 2U, +PORTC_15_TPU_CH12 = 3U, +PORTC_15_FCSPI2_SCK = 4U, +PORTC_15_FTU6_CH1 = 5U, +PORTC_15_TRGSEL_OUT7 = 6U, +PORTC_15_FCUART5_TX = 7U, +} PORT_C15MuxType; + +/** @brief PORTC 16 Mode enumeration */ +typedef enum +{ +PORTC_16_CMP1_IN4 = 0U, +PORTC_16_GPIO = 1U, +PORTC_16_FTU_FLT7 = 2U, +PORTC_16_FTU4_CH0 = 3U, +PORTC_16_FCSPI2_SIN = 4U, +PORTC_16_FTU7_CH4 = 5U, +PORTC_16_TPU_CH13 = 6U, +PORTC_16_FCUART5_RX = 7U, +} PORT_C16MuxType; + +/** @brief PORTC 17 Mode enumeration */ +typedef enum +{ +PORTC_17_DEBUGMUX_P1 = 0U, +PORTC_17_GPIO = 1U, +PORTC_17_FTU_FLT6 = 2U, +PORTC_17_FTU4_CH1 = 3U, +PORTC_17_FCSPI2_PCS3 = 4U, +PORTC_17_FTU6_CH2 = 5U, +PORTC_17_TPU_CH14 = 6U, +PORTC_17_FCUART4_TX = 7U, +} PORT_C17MuxType; + +/** @brief PORTC 18 Mode enumeration */ +typedef enum +{ +PORTC_18_CMP1_IN1 = 0U, +PORTC_18_GPIO = 1U, +PORTC_18_FTU7_CH6 = 2U, +PORTC_18_FCSPI3_PCS0 = 3U, +PORTC_18_FCUART5_RX = 4U, +PORTC_18_TPU_CH10 = 5U, +} PORT_C18MuxType; + +/** @brief PORTC 19 Mode enumeration */ +typedef enum +{ +PORTC_19_GPIO = 1U, +PORTC_19_FTU7_CH3 = 2U, +PORTC_19_FCSPI2_PCS1 = 4U, +PORTC_19_TPU_CH17 = 5U, +PORTC_19_FCUART3_RX = 6U, +} PORT_C19MuxType; + +/** @brief PORTC 2 Mode enumeration */ +typedef enum +{ +PORTC_2_DEBUGMUX_P2 = 0U, +PORTC_2_GPIO = 1U, +PORTC_2_FTU0_CH2 = 2U, +PORTC_2_FLEXCAN0_RX = 3U, +PORTC_2_FCUART0_RX = 4U, +PORTC_2_FTU5_CH4 = 5U, +PORTC_2_ETM_TRACE_CLKOUT = 6U, +PORTC_2_FCSPI0_PCS2 = 7U, +} PORT_C2MuxType; + +/** @brief PORTC 20 Mode enumeration */ +typedef enum +{ +PORTC_20_GPIO = 1U, +PORTC_20_FTU7_CH2 = 2U, +PORTC_20_FCSPI2_SCK = 4U, +PORTC_20_FCUART3_RTS = 5U, +PORTC_20_TPU_CH12 = 6U, +PORTC_20_MSC0_FCLP = 7U, +} PORT_C20MuxType; + +/** @brief PORTC 21 Mode enumeration */ +typedef enum +{ +PORTC_21_GPIO = 1U, +PORTC_21_FTU7_CH1 = 2U, +PORTC_21_FCSPI2_SIN = 4U, +PORTC_21_FCUART3_CTS = 5U, +PORTC_21_TPU_CH13 = 6U, +PORTC_21_MSC0_SOP = 7U, +} PORT_C21MuxType; + +/** @brief PORTC 22 Mode enumeration */ +typedef enum +{ +PORTC_22_GPIO = 1U, +PORTC_22_FTU6_CH4 = 2U, +PORTC_22_FCSPI0_SCK = 3U, +PORTC_22_FCUART5_RX = 4U, +PORTC_22_FTU7_CH6 = 5U, +PORTC_22_TPU_CH18 = 6U, +PORTC_22_MSC0_EN2 = 7U, +} PORT_C22MuxType; + +/** @brief PORTC 23 Mode enumeration */ +typedef enum +{ +PORTC_23_GPIO = 1U, +PORTC_23_FTU7_CH0 = 2U, +PORTC_23_FCUART6_TX = 3U, +PORTC_23_FCSPI2_SOUT = 4U, +PORTC_23_TPU_CH14 = 6U, +PORTC_23_MSC0_EN3 = 7U, +} PORT_C23MuxType; + +/** @brief PORTC 24 Mode enumeration */ +typedef enum +{ +PORTC_24_GPIO = 1U, +PORTC_24_FTU4_CH3 = 2U, +PORTC_24_FCUART6_RX = 3U, +PORTC_24_FCSPI2_PCS0 = 4U, +PORTC_24_TPU_CH15 = 6U, +PORTC_24_MSC0_SDI2 = 7U, +} PORT_C24MuxType; + +/** @brief PORTC 25 Mode enumeration */ +typedef enum +{ +PORTC_25_ADC1_SE20 = 0U, +PORTC_25_GPIO = 1U, +PORTC_25_FTU4_CH1 = 2U, +PORTC_25_FCUART5_RTS = 3U, +PORTC_25_FCUART6_TX = 4U, +PORTC_25_FTU0_CH6 = 5U, +PORTC_25_SENT0_RXD0 = 6U, +PORTC_25_FCSPI4_SCK = 7U, +} PORT_C25MuxType; + +/** @brief PORTC 26 Mode enumeration */ +typedef enum +{ +PORTC_26_ADC1_SE21 = 0U, +PORTC_26_GPIO = 1U, +PORTC_26_FTU4_CH0 = 2U, +PORTC_26_FCUART5_CTS = 3U, +PORTC_26_FCUART6_RX = 4U, +PORTC_26_FTU1_CH4 = 5U, +PORTC_26_SENT0_RXD1 = 6U, +PORTC_26_FCSPI4_PCS0 = 7U, +} PORT_C26MuxType; + +/** @brief PORTC 27 Mode enumeration */ +typedef enum +{ +PORTC_27_GPIO = 1U, +PORTC_27_FTU4_CH4 = 2U, +PORTC_27_FTU3_CH3 = 3U, +PORTC_27_FCSPI4_SOUT = 4U, +PORTC_27_TPU_CH19 = 6U, +PORTC_27_MSC0_EN0 = 7U, +} PORT_C27MuxType; + +/** @brief PORTC 28 Mode enumeration */ +typedef enum +{ +PORTC_28_GPIO = 1U, +PORTC_28_FTU4_CH7 = 2U, +PORTC_28_FLEXCAN3_TX = 3U, +PORTC_28_FTU3_CH2 = 4U, +PORTC_28_TPU_CH20 = 6U, +PORTC_28_MSC0_SDI0 = 7U, +} PORT_C28MuxType; + +/** @brief PORTC 29 Mode enumeration */ +typedef enum +{ +PORTC_29_GPIO = 1U, +PORTC_29_FTU5_CH2 = 2U, +PORTC_29_FLEXCAN3_RX = 3U, +PORTC_29_FCSPI4_SIN = 4U, +PORTC_29_TPU_CH21 = 6U, +} PORT_C29MuxType; + +/** @brief PORTC 3 Mode enumeration */ +typedef enum +{ +PORTC_3_GPIO = 1U, +PORTC_3_FTU0_CH3 = 2U, +PORTC_3_FLEXCAN0_TX = 3U, +PORTC_3_FCUART0_TX = 4U, +PORTC_3_FTU5_CH2 = 5U, +PORTC_3_ETM_TRACE_D7 = 6U, +PORTC_3_FCSPI0_SOUT = 7U, +} PORT_C3MuxType; + +/** @brief PORTC 30 Mode enumeration */ +typedef enum +{ +PORTC_30_GPIO = 1U, +PORTC_30_FTU5_CH4 = 2U, +PORTC_30_FTU3_CH0 = 3U, +PORTC_30_FCSPI4_PCS0 = 4U, +PORTC_30_TPU_CH22 = 6U, +} PORT_C30MuxType; + +/** @brief PORTC 31 Mode enumeration */ +typedef enum +{ +PORTC_31_GPIO = 1U, +PORTC_31_FTU5_CH6 = 2U, +PORTC_31_FTU3_CH4 = 3U, +PORTC_31_FCIIC1_SDA = 4U, +PORTC_31_FLEXCAN1_RX = 5U, +PORTC_31_TPU_CH23 = 6U, +} PORT_C31MuxType; + +/** @brief PORTC 4 Mode enumeration */ +typedef enum +{ +PORTC_4_GPIO = 1U, +PORTC_4_JTAG_TCLK_SWD_CLK = 7U, +} PORT_C4MuxType; + +/** @brief PORTC 5 Mode enumeration */ +typedef enum +{ +PORTC_5_GPIO = 1U, +PORTC_5_FTU2_CH0 = 2U, +PORTC_5_RTC_CLKOUT = 3U, +PORTC_5_CMP1_OUT = 4U, +PORTC_5_FCIIC0_SDA = 5U, +PORTC_5_FTU2_QD_PHB = 6U, +PORTC_5_JTAG_TDI = 7U, +} PORT_C5MuxType; + +/** @brief PORTC 6 Mode enumeration */ +typedef enum +{ +PORTC_6_ADC0_SE29 = 0U, +PORTC_6_GPIO = 1U, +PORTC_6_FCUART1_RX = 2U, +PORTC_6_FLEXCAN1_RX = 3U, +PORTC_6_FTU3_CH2 = 4U, +PORTC_6_SENT0_RXD0 = 5U, +PORTC_6_TPU_CH3 = 6U, +} PORT_C6MuxType; + +/** @brief PORTC 7 Mode enumeration */ +typedef enum +{ +PORTC_7_ADC0_SE30 = 0U, +PORTC_7_GPIO = 1U, +PORTC_7_FCUART1_TX = 2U, +PORTC_7_FLEXCAN1_TX = 3U, +PORTC_7_FTU3_CH3 = 4U, +PORTC_7_TPU_CH2 = 6U, +} PORT_C7MuxType; + +/** @brief PORTC 8 Mode enumeration */ +typedef enum +{ +PORTC_8_GPIO = 1U, +PORTC_8_FCUART1_RX = 2U, +PORTC_8_FTU_FLT11 = 3U, +PORTC_8_FTU5_CH1 = 4U, +PORTC_8_FCSPI1_SIN = 5U, +PORTC_8_FCUART0_CTS = 6U, +PORTC_8_MSC0_EN1 = 7U, +} PORT_C8MuxType; + +/** @brief PORTC 9 Mode enumeration */ +typedef enum +{ +PORTC_9_GPIO = 1U, +PORTC_9_FCUART1_TX = 2U, +PORTC_9_FTU_FLT10 = 3U, +PORTC_9_FTU5_CH0 = 4U, +PORTC_9_FCSPI1_SOUT = 5U, +PORTC_9_FCUART0_RTS = 6U, +PORTC_9_FCUART5_TX = 7U, +} PORT_C9MuxType; + +/** @brief PORTD 0 Mode enumeration */ +typedef enum +{ +PORTD_0_ADC1_SE1 = 0U, +PORTD_0_GPIO = 1U, +PORTD_0_FTU0_CH2 = 2U, +PORTD_0_FTU2_CH0 = 3U, +PORTD_0_FCSPI1_SCK = 4U, +PORTD_0_TPU_CH28 = 5U, +PORTD_0_ETM_TRACE_D0 = 6U, +PORTD_0_TRGSEL_OUT1 = 7U, +} PORT_D0MuxType; + +/** @brief PORTD 1 Mode enumeration */ +typedef enum +{ +PORTD_1_ADC1_SE5 = 0U, +PORTD_1_GPIO = 1U, +PORTD_1_FTU0_CH3 = 2U, +PORTD_1_FTU2_CH1 = 3U, +PORTD_1_FCSPI1_SIN = 4U, +PORTD_1_TPU_CH29 = 5U, +PORTD_1_TRGSEL_OUT2 = 7U, +} PORT_D1MuxType; + +/** @brief PORTD 10 Mode enumeration */ +typedef enum +{ +PORTD_10_GPIO = 1U, +PORTD_10_FTU2_CH0 = 2U, +PORTD_10_FTU2_QD_PHB = 3U, +PORTD_10_SCG_CLKOUT = 4U, +PORTD_10_FlexCore_TMS = 5U, +PORTD_10_ETM_TRACE_D3 = 6U, +PORTD_10_FCSPI3_PCS3 = 7U, +} PORT_D10MuxType; + +/** @brief PORTD 11 Mode enumeration */ +typedef enum +{ +PORTD_11_GPIO = 1U, +PORTD_11_FTU2_CH1 = 2U, +PORTD_11_FTU2_QD_PHA = 3U, +PORTD_11_FCSPI4_PCS1 = 4U, +PORTD_11_FCUART2_CTS = 5U, +PORTD_11_ETM_TRACE_D2 = 6U, +PORTD_11_FCSPI3_PCS0 = 7U, +} PORT_D11MuxType; + +/** @brief PORTD 12 Mode enumeration */ +typedef enum +{ +PORTD_12_GPIO = 1U, +PORTD_12_FTU2_CH2 = 2U, +PORTD_12_FCUART4_RX = 3U, +PORTD_12_FTU6_CH7 = 4U, +PORTD_12_FCUART2_RTS = 5U, +PORTD_12_ETM_TRACE_D1 = 6U, +PORTD_12_FCSPI3_SOUT = 7U, +} PORT_D12MuxType; + +/** @brief PORTD 13 Mode enumeration */ +typedef enum +{ +PORTD_13_GPIO = 1U, +PORTD_13_FTU6_CH3 = 2U, +PORTD_13_FCUART1_TX = 3U, +PORTD_13_TPU_CH11 = 4U, +PORTD_13_FCUART7_CTS = 6U, +PORTD_13_MSC0_SOP = 7U, +} PORT_D13MuxType; + +/** @brief PORTD 15 Mode enumeration */ +typedef enum +{ +PORTD_15_ADC0_SE11_CMP0_IN1 = 0U, +PORTD_15_GPIO = 1U, +PORTD_15_FTU0_CH0 = 2U, +PORTD_15_FCUART2_RTS = 3U, +PORTD_15_TPU_CH18 = 4U, +PORTD_15_ETM_TRACE_D3 = 6U, +PORTD_15_FCSPI0_SCK = 7U, +} PORT_D15MuxType; + +/** @brief PORTD 16 Mode enumeration */ +typedef enum +{ +PORTD_16_ADC0_SE10_CMP0_IN0 = 0U, +PORTD_16_GPIO = 1U, +PORTD_16_FTU0_CH1 = 2U, +PORTD_16_TPU_CH19 = 4U, +PORTD_16_ETM_TRACE_D2 = 6U, +PORTD_16_FCSPI0_SIN = 7U, +} PORT_D16MuxType; + +/** @brief PORTD 17 Mode enumeration */ +typedef enum +{ +PORTD_17_ADC0_SE8 = 0U, +PORTD_17_GPIO = 1U, +PORTD_17_FTU6_CH1 = 2U, +PORTD_17_FCUART7_RX = 3U, +PORTD_17_FTU_FLT3 = 4U, +PORTD_17_FCSPI4_PCS0 = 6U, +PORTD_17_TPU_CH5 = 7U, +} PORT_D17MuxType; + +/** @brief PORTD 18 Mode enumeration */ +typedef enum +{ +PORTD_18_GPIO = 1U, +PORTD_18_FTU5_CH7 = 2U, +PORTD_18_FTU3_CH5 = 3U, +PORTD_18_FCSPI4_SCK = 4U, +PORTD_18_TPU_CH24 = 6U, +} PORT_D18MuxType; + +/** @brief PORTD 19 Mode enumeration */ +typedef enum +{ +PORTD_19_GPIO = 1U, +PORTD_19_FTU6_CH0 = 2U, +PORTD_19_FCSPI1_PCS2 = 3U, +PORTD_19_FCIIC1_SCL = 4U, +PORTD_19_FLEXCAN1_TX = 5U, +PORTD_19_SENT0_RXD2 = 6U, +} PORT_D19MuxType; + +/** @brief PORTD 2 Mode enumeration */ +typedef enum +{ +PORTD_2_GPIO = 1U, +PORTD_2_FTU3_CH4 = 2U, +PORTD_2_FTU6_CH5 = 3U, +PORTD_2_FCUART6_RX = 4U, +PORTD_2_FCSPI5_PCS2 = 5U, +PORTD_2_FTU1_CH1 = 6U, +PORTD_2_ISP_EN_B = 7U, +} PORT_D2MuxType; + +/** @brief PORTD 20 Mode enumeration */ +typedef enum +{ +PORTD_20_GPIO = 1U, +PORTD_20_FTU6_CH2 = 2U, +PORTD_20_FCUART5_RX = 3U, +PORTD_20_TPU_CH16 = 4U, +PORTD_20_SENT0_RXD2 = 6U, +PORTD_20_FCSPI4_SIN = 7U, +} PORT_D20MuxType; + +/** @brief PORTD 21 Mode enumeration */ +typedef enum +{ +PORTD_21_ADC1_SE22 = 0U, +PORTD_21_GPIO = 1U, +PORTD_21_FTU6_CH3 = 2U, +PORTD_21_FCUART5_TX = 3U, +PORTD_21_TPU_CH17 = 4U, +PORTD_21_SENT0_RXD3 = 6U, +PORTD_21_FCSPI4_SOUT = 7U, +} PORT_D21MuxType; + +/** @brief PORTD 22 Mode enumeration */ +typedef enum +{ +PORTD_22_ADC1_SE19 = 0U, +PORTD_22_GPIO = 1U, +PORTD_22_FTU6_CH1 = 2U, +PORTD_22_FTU0_CH1 = 3U, +PORTD_22_TPU_TCRCLK = 4U, +PORTD_22_FCSPI5_PCS3 = 5U, +PORTD_22_FLEXCAN1_RX = 6U, +} PORT_D22MuxType; + +/** @brief PORTD 23 Mode enumeration */ +typedef enum +{ +PORTD_23_GPIO = 1U, +PORTD_23_FTU6_CH5 = 2U, +PORTD_23_FLEXCAN3_TX = 4U, +PORTD_23_TPU_CH27 = 5U, +PORTD_23_FTU1_CH0 = 6U, +} PORT_D23MuxType; + +/** @brief PORTD 24 Mode enumeration */ +typedef enum +{ +PORTD_24_GPIO = 1U, +PORTD_24_FTU3_CH3 = 2U, +PORTD_24_TPU_CH28 = 3U, +PORTD_24_FCUART6_RTS = 4U, +PORTD_24_FCSPI5_PCS1 = 5U, +PORTD_24_FLEXCAN1_TX = 6U, +} PORT_D24MuxType; + +/** @brief PORTD 25 Mode enumeration */ +typedef enum +{ +PORTD_25_ADC1_SE24 = 0U, +PORTD_25_GPIO = 1U, +PORTD_25_FTU6_CH6 = 2U, +PORTD_25_FTU0_CH0 = 3U, +PORTD_25_FCUART4_RTS = 4U, +PORTD_25_TPU_CH18 = 6U, +PORTD_25_FCSPI5_SCK = 7U, +} PORT_D25MuxType; + +/** @brief PORTD 26 Mode enumeration */ +typedef enum +{ +PORTD_26_ADC1_SE26 = 0U, +PORTD_26_GPIO = 1U, +PORTD_26_FTU6_CH7 = 2U, +PORTD_26_FTU3_CH7 = 3U, +PORTD_26_FCUART4_CTS = 4U, +PORTD_26_SENT0_RXD3 = 5U, +PORTD_26_TPU_CH19 = 6U, +PORTD_26_FCSPI5_SIN = 7U, +} PORT_D26MuxType; + +/** @brief PORTD 27 Mode enumeration */ +typedef enum +{ +PORTD_27_ADC1_SE27 = 0U, +PORTD_27_GPIO = 1U, +PORTD_27_FTU7_CH0 = 2U, +PORTD_27_FCUART6_TX = 3U, +PORTD_27_FLEXCAN3_RX = 4U, +PORTD_27_TPU_CH30 = 6U, +} PORT_D27MuxType; + +/** @brief PORTD 28 Mode enumeration */ +typedef enum +{ +PORTD_28_GPIO = 1U, +PORTD_28_FTU7_CH1 = 2U, +PORTD_28_FCUART6_RX = 3U, +PORTD_28_TPU_CH31 = 6U, +PORTD_28_FCSPI5_PCS1 = 7U, +} PORT_D28MuxType; + +/** @brief PORTD 29 Mode enumeration */ +typedef enum +{ +PORTD_29_GPIO = 1U, +PORTD_29_FTU7_CH2 = 2U, +PORTD_29_FCUART7_RX = 3U, +PORTD_29_TPU_CH14 = 6U, +} PORT_D29MuxType; + +/** @brief PORTD 3 Mode enumeration */ +typedef enum +{ +PORTD_3_GPIO = 1U, +PORTD_3_FTU3_CH5 = 2U, +PORTD_3_FCSPI1_PCS0 = 3U, +PORTD_3_FCSPI5_PCS0 = 5U, +PORTD_3_FTU1_CH2 = 6U, +PORTD_3_TPU_CH3 = 7U, +} PORT_D3MuxType; + +/** @brief PORTD 30 Mode enumeration */ +typedef enum +{ +PORTD_30_ADC1_SE31 = 0U, +PORTD_30_GPIO = 1U, +PORTD_30_FTU7_CH3 = 2U, +PORTD_30_FCUART7_TX = 3U, +PORTD_30_TPU_CH15 = 6U, +} PORT_D30MuxType; + +/** @brief PORTD 31 Mode enumeration */ +typedef enum +{ +PORTD_31_ADC0_SE31 = 0U, +PORTD_31_GPIO = 1U, +PORTD_31_FTU7_CH4 = 2U, +PORTD_31_AONTIMER0_CLK0 = 3U, +PORTD_31_SENT0_RXD2 = 4U, +PORTD_31_FCUART7_RX = 5U, +PORTD_31_TPU_CH20 = 6U, +PORTD_31_FCSPI5_PCS2 = 7U, +} PORT_D31MuxType; + +/** @brief PORTD 4 Mode enumeration */ +typedef enum +{ +PORTD_4_ADC1_SE23 = 0U, +PORTD_4_GPIO = 1U, +PORTD_4_FTU_FLT16 = 2U, +PORTD_4_FTU6_CH4 = 3U, +PORTD_4_FCUART6_TX = 4U, +PORTD_4_FCSPI5_SIN = 5U, +PORTD_4_FTU1_CH3 = 6U, +PORTD_4_TPU_CH4 = 7U, +} PORT_D4MuxType; + +/** @brief PORTD 5 Mode enumeration */ +typedef enum +{ +PORTD_5_GPIO = 1U, +PORTD_5_FTU2_CH3 = 2U, +PORTD_5_FCUART4_TX = 3U, +PORTD_5_FTU_FLT5 = 4U, +PORTD_5_FTU7_CH5 = 5U, +PORTD_5_TPU_CH20 = 6U, +PORTD_5_FCSPI3_SIN = 7U, +} PORT_D5MuxType; + +/** @brief PORTD 6 Mode enumeration */ +typedef enum +{ +PORTD_6_GPIO = 1U, +PORTD_6_FCUART2_RX = 2U, +PORTD_6_FLEXCAN3_RX = 3U, +PORTD_6_FTU_FLT4 = 4U, +PORTD_6_FTU2_CH4 = 5U, +PORTD_6_TPU_CH21 = 6U, +PORTD_6_FCSPI3_SCK = 7U, +} PORT_D6MuxType; + +/** @brief PORTD 7 Mode enumeration */ +typedef enum +{ +PORTD_7_GPIO = 1U, +PORTD_7_FCUART2_TX = 2U, +PORTD_7_FLEXCAN3_TX = 3U, +PORTD_7_FCSPI4_SIN = 4U, +PORTD_7_FTU2_CH5 = 5U, +PORTD_7_ETM_TRACE_D0 = 6U, +} PORT_D7MuxType; + +/** @brief PORTD 8 Mode enumeration */ +typedef enum +{ +PORTD_8_CMP1_IN3 = 0U, +PORTD_8_GPIO = 1U, +PORTD_8_FCIIC1_SDA = 2U, +PORTD_8_FTU4_CH2 = 3U, +PORTD_8_FCSPI2_PCS2 = 4U, +PORTD_8_FlexCore_TRST = 5U, +PORTD_8_FTU1_CH4 = 6U, +PORTD_8_FCUART4_RX = 7U, +} PORT_D8MuxType; + +/** @brief PORTD 9 Mode enumeration */ +typedef enum +{ +PORTD_9_CMP1_IN2 = 0U, +PORTD_9_GPIO = 1U, +PORTD_9_FCIIC1_SCL = 2U, +PORTD_9_FTU4_CH3 = 3U, +PORTD_9_FCSPI2_PCS1 = 4U, +PORTD_9_FlexCore_TDO = 5U, +PORTD_9_FTU1_CH5 = 6U, +PORTD_9_FCUART3_RX = 7U, +} PORT_D9MuxType; + +/** @brief PORTE 0 Mode enumeration */ +typedef enum +{ +PORTE_0_ADC0_SE16 = 0U, +PORTE_0_GPIO = 1U, +PORTE_0_FCUART0_CTS = 2U, +PORTE_0_FTU_TCK1 = 3U, +PORTE_0_FCIIC1_SDA = 4U, +PORTE_0_FCSPI0_SCK = 5U, +PORTE_0_FTU_FLT19 = 6U, +PORTE_0_TPU_CH11 = 7U, +} PORT_E0MuxType; + +/** @brief PORTE 1 Mode enumeration */ +typedef enum +{ +PORTE_1_ADC0_SE17 = 0U, +PORTE_1_GPIO = 1U, +PORTE_1_FCUART0_RTS = 2U, +PORTE_1_FCIIC1_SCL = 4U, +PORTE_1_FCSPI0_SIN = 5U, +PORTE_1_FTU_FLT18 = 6U, +PORTE_1_TPU_CH10 = 7U, +} PORT_E1MuxType; + +/** @brief PORTE 10 Mode enumeration */ +typedef enum +{ +PORTE_10_ADC1_SE0 = 0U, +PORTE_10_GPIO = 1U, +PORTE_10_FTU2_CH4 = 2U, +PORTE_10_FCSPI2_PCS1 = 3U, +PORTE_10_TPU_CH26 = 4U, +PORTE_10_FCUART2_TX = 5U, +PORTE_10_SCG_CLKOUT = 6U, +PORTE_10_TRGSEL_OUT4 = 7U, +} PORT_E10MuxType; + +/** @brief PORTE 11 Mode enumeration */ +typedef enum +{ +PORTE_11_ADC1_SE4 = 0U, +PORTE_11_GPIO = 1U, +PORTE_11_FTU2_CH5 = 2U, +PORTE_11_FCSPI2_PCS0 = 3U, +PORTE_11_TPU_CH27 = 5U, +PORTE_11_TRGSEL_OUT5 = 7U, +} PORT_E11MuxType; + +/** @brief PORTE 12 Mode enumeration */ +typedef enum +{ +PORTE_12_ADC0_SE3 = 0U, +PORTE_12_GPIO = 1U, +PORTE_12_FTU6_CH0 = 2U, +PORTE_12_FCUART7_TX = 3U, +PORTE_12_FTU_FLT2 = 4U, +PORTE_12_FCSPI4_SOUT = 6U, +PORTE_12_TPU_CH3 = 7U, +} PORT_E12MuxType; + +/** @brief PORTE 13 Mode enumeration */ +typedef enum +{ +PORTE_13_ADC0_SE5 = 0U, +PORTE_13_GPIO = 1U, +PORTE_13_FTU4_CH5 = 2U, +PORTE_13_FCSPI2_SOUT = 3U, +PORTE_13_TPU_CH24 = 4U, +PORTE_13_FTU3_CH3 = 5U, +} PORT_E13MuxType; + +/** @brief PORTE 14 Mode enumeration */ +typedef enum +{ +PORTE_14_OSC32K_XTAL = 0U, +PORTE_14_GPIO = 1U, +PORTE_14_FTU2_CH7 = 2U, +PORTE_14_FTU2_QD_PHA = 3U, +PORTE_14_FTU_FLT0 = 4U, +PORTE_14_FLEXCAN0_RX = 5U, +PORTE_14_TPU_TCRCLK = 6U, +} PORT_E14MuxType; + +/** @brief PORTE 15 Mode enumeration */ +typedef enum +{ +PORTE_15_ADC1_SE2 = 0U, +PORTE_15_GPIO = 1U, +PORTE_15_FTU2_CH6 = 2U, +PORTE_15_FCSPI2_SCK = 3U, +PORTE_15_TPU_CH30 = 4U, +PORTE_15_FCUART1_CTS = 6U, +PORTE_15_TRGSEL_OUT6 = 7U, +} PORT_E15MuxType; + +/** @brief PORTE 16 Mode enumeration */ +typedef enum +{ +PORTE_16_ADC1_SE6 = 0U, +PORTE_16_GPIO = 1U, +PORTE_16_FTU2_CH7 = 2U, +PORTE_16_FCSPI2_SIN = 3U, +PORTE_16_TPU_CH31 = 4U, +PORTE_16_FCUART1_RTS = 6U, +PORTE_16_TRGSEL_OUT7 = 7U, +} PORT_E16MuxType; + +/** @brief PORTE 17 Mode enumeration */ +typedef enum +{ +PORTE_17_GPIO = 1U, +PORTE_17_FTU7_CH5 = 2U, +PORTE_17_SENT0_RXD0 = 4U, +PORTE_17_TPU_CH21 = 6U, +PORTE_17_FCSPI5_SOUT = 7U, +} PORT_E17MuxType; + +/** @brief PORTE 18 Mode enumeration */ +typedef enum +{ +PORTE_18_ADC0_SE27 = 0U, +PORTE_18_GPIO = 1U, +PORTE_18_FTU7_CH6 = 2U, +PORTE_18_FTU6_CH7 = 3U, +PORTE_18_SENT0_RXD1 = 4U, +PORTE_18_FCUART7_TX = 5U, +PORTE_18_TPU_CH22 = 6U, +PORTE_18_FCSPI5_PCS3 = 7U, +} PORT_E18MuxType; + +/** @brief PORTE 19 Mode enumeration */ +typedef enum +{ +PORTE_19_ADC0_SE23 = 0U, +PORTE_19_GPIO = 1U, +PORTE_19_SCG_CLKOUT = 2U, +PORTE_19_FCIIC0_SCL = 3U, +PORTE_19_RTC_CLKOUT = 4U, +PORTE_19_FLEXCAN2_RX = 5U, +PORTE_19_TPU_CH31 = 6U, +} PORT_E19MuxType; + +/** @brief PORTE 2 Mode enumeration */ +typedef enum +{ +PORTE_2_ADC0_SE24 = 0U, +PORTE_2_GPIO = 1U, +PORTE_2_FTU6_CH6 = 2U, +PORTE_2_AONTIMER0_CLK2 = 3U, +PORTE_2_FTU3_CH6 = 4U, +PORTE_2_SENT0_RXD3 = 5U, +PORTE_2_FCUART1_CTS = 6U, +PORTE_2_FTU1_CH7 = 7U, +} PORT_E2MuxType; + +/** @brief PORTE 20 Mode enumeration */ +typedef enum +{ +PORTE_20_ADC0_SE22 = 0U, +PORTE_20_GPIO = 1U, +PORTE_20_FTU4_CH0 = 2U, +PORTE_20_FCIIC0_SDA = 3U, +PORTE_20_FTU1_CH3 = 4U, +PORTE_20_FCSPI0_PCS0 = 5U, +} PORT_E20MuxType; + +/** @brief PORTE 21 Mode enumeration */ +typedef enum +{ +PORTE_21_GPIO = 1U, +PORTE_21_FTU4_CH1 = 2U, +PORTE_21_AONTIMER0_CLK2 = 3U, +PORTE_21_FLEXCAN0_TX = 4U, +PORTE_21_FCUART0_RTS = 5U, +} PORT_E21MuxType; + +/** @brief PORTE 22 Mode enumeration */ +typedef enum +{ +PORTE_22_GPIO = 1U, +PORTE_22_FTU4_CH2 = 2U, +PORTE_22_LP_WAKEUP0 = 3U, +PORTE_22_FLEXCAN0_RX = 4U, +PORTE_22_FCUART0_CTS = 5U, +} PORT_E22MuxType; + +/** @brief PORTE 23 Mode enumeration */ +typedef enum +{ +PORTE_23_ADC0_SE19 = 0U, +PORTE_23_GPIO = 1U, +PORTE_23_FTU4_CH3 = 2U, +PORTE_23_FCUART0_TX = 3U, +PORTE_23_TPU_CH26 = 4U, +PORTE_23_FCSPI0_PCS3 = 5U, +PORTE_23_LP_WAKEUP1 = 6U, +} PORT_E23MuxType; + +/** @brief PORTE 24 Mode enumeration */ +typedef enum +{ +PORTE_24_ADC0_SE18 = 0U, +PORTE_24_GPIO = 1U, +PORTE_24_FTU4_CH4 = 2U, +PORTE_24_FLEXCAN2_TX = 3U, +PORTE_24_TPU_CH27 = 4U, +PORTE_24_FCSPI0_PCS2 = 5U, +} PORT_E24MuxType; + +/** @brief PORTE 25 Mode enumeration */ +typedef enum +{ +PORTE_25_DEBUGMUX_P0 = 0U, +PORTE_25_GPIO = 1U, +PORTE_25_FTU4_CH5 = 2U, +PORTE_25_FCUART0_RX = 3U, +PORTE_25_TPU_CH28 = 4U, +PORTE_25_FCSPI0_PCS1 = 5U, +} PORT_E25MuxType; + +/** @brief PORTE 26 Mode enumeration */ +typedef enum +{ +PORTE_26_GPIO = 1U, +PORTE_26_FTU4_CH6 = 2U, +PORTE_26_LP_WAKEUP3 = 3U, +PORTE_26_FTU1_CH2 = 4U, +PORTE_26_FCUART1_TX = 5U, +PORTE_26_TPU_CH23 = 6U, +} PORT_E26MuxType; + +/** @brief PORTE 27 Mode enumeration */ +typedef enum +{ +PORTE_27_GPIO = 1U, +PORTE_27_FTU4_CH7 = 2U, +PORTE_27_FLEXCAN2_RX = 3U, +PORTE_27_FTU1_CH0 = 4U, +PORTE_27_FCUART1_RX = 5U, +PORTE_27_TPU_CH24 = 6U, +} PORT_E27MuxType; + +/** @brief PORTE 29 Mode enumeration */ +typedef enum +{ +PORTE_29_GPIO = 1U, +PORTE_29_FTU2_CH0 = 2U, +PORTE_29_RTC_CLKOUT = 3U, +PORTE_29_FTU1_CH1 = 4U, +PORTE_29_FLEXCAN2_TX = 5U, +PORTE_29_FTU2_QD_PHA = 6U, +PORTE_29_TPU_CH25 = 7U, +} PORT_E29MuxType; + +/** @brief PORTE 3 Mode enumeration */ +typedef enum +{ +PORTE_3_OSC32K_EXTAL = 0U, +PORTE_3_GPIO = 1U, +PORTE_3_FTU2_CH6 = 2U, +PORTE_3_FCUART2_RX = 3U, +PORTE_3_FTU_FLT1 = 4U, +PORTE_3_FTU2_QD_PHB = 5U, +PORTE_3_FTU_TCK0 = 6U, +} PORT_E3MuxType; + +/** @brief PORTE 4 Mode enumeration */ +typedef enum +{ +PORTE_4_ADC0_SE4 = 0U, +PORTE_4_GPIO = 1U, +PORTE_4_FTU6_CH0 = 2U, +PORTE_4_FTU2_QD_PHB = 3U, +PORTE_4_FCSPI1_PCS0 = 4U, +PORTE_4_FTU2_CH2 = 5U, +PORTE_4_ETM_TRACE_D1 = 6U, +PORTE_4_TPU_CH22 = 7U, +} PORT_E4MuxType; + +/** @brief PORTE 5 Mode enumeration */ +typedef enum +{ +PORTE_5_ADC0_SE1 = 0U, +PORTE_5_GPIO = 1U, +PORTE_5_FTU_TCK2 = 2U, +PORTE_5_FTU2_QD_PHA = 3U, +PORTE_5_FCSPI1_SOUT = 4U, +PORTE_5_FTU2_CH3 = 5U, +PORTE_5_TPU_CH23 = 6U, +} PORT_E5MuxType; + +/** @brief PORTE 6 Mode enumeration */ +typedef enum +{ +PORTE_6_ADC0_SE25 = 0U, +PORTE_6_GPIO = 1U, +PORTE_6_FTU7_CH7 = 2U, +PORTE_6_FTU6_CH3 = 3U, +PORTE_6_FTU3_CH7 = 4U, +PORTE_6_SENT0_RXD2 = 5U, +PORTE_6_FCUART1_RTS = 6U, +PORTE_6_TPU_CH6 = 7U, +} PORT_E6MuxType; + +/** @brief PORTE 7 Mode enumeration */ +typedef enum +{ +PORTE_7_ADC1_SE8 = 0U, +PORTE_7_GPIO = 1U, +PORTE_7_FTU0_CH7 = 2U, +PORTE_7_FTU_FLT14 = 3U, +PORTE_7_FTU5_CH6 = 4U, +PORTE_7_TRGSEL_OUT3 = 5U, +PORTE_7_SENT0_RXD3 = 6U, +PORTE_7_MSC0_SDI3 = 7U, +} PORT_E7MuxType; + +/** @brief PORTE 8 Mode enumeration */ +typedef enum +{ +PORTE_8_GPIO = 1U, +PORTE_8_FTU0_CH6 = 2U, +PORTE_8_FCSPI4_SCK = 4U, +PORTE_8_FTU7_CH7 = 5U, +PORTE_8_ETM_TRACE_D4 = 6U, +PORTE_8_FCSPI0_PCS3 = 7U, +} PORT_E8MuxType; + +/** @brief PORTE 9 Mode enumeration */ +typedef enum +{ +PORTE_9_ADC0_SE12_CMP0_IN2 = 0U, +PORTE_9_GPIO = 1U, +PORTE_9_FTU0_CH7 = 2U, +PORTE_9_FCUART2_CTS = 3U, +PORTE_9_TPU_CH17 = 4U, +PORTE_9_ETM_TRACE_CLKOUT = 6U, +PORTE_9_FCSPI0_PCS0 = 7U, +} PORT_E9MuxType; + + +/** @brief Port Pin Mux structure */ +typedef union +{ + PORT_A0MuxType ePortA0Mode; + PORT_A1MuxType ePortA1Mode; + PORT_A2MuxType ePortA2Mode; + PORT_A3MuxType ePortA3Mode; + PORT_A4MuxType ePortA4Mode; + PORT_A6MuxType ePortA6Mode; + PORT_A7MuxType ePortA7Mode; + PORT_A8MuxType ePortA8Mode; + PORT_A9MuxType ePortA9Mode; + PORT_A10MuxType ePortA10Mode; + PORT_A11MuxType ePortA11Mode; + PORT_A12MuxType ePortA12Mode; + PORT_A13MuxType ePortA13Mode; + PORT_A14MuxType ePortA14Mode; + PORT_A15MuxType ePortA15Mode; + PORT_A16MuxType ePortA16Mode; + PORT_A17MuxType ePortA17Mode; + PORT_A18MuxType ePortA18Mode; + PORT_A19MuxType ePortA19Mode; + PORT_A20MuxType ePortA20Mode; + PORT_A21MuxType ePortA21Mode; + PORT_A23MuxType ePortA23Mode; + PORT_A24MuxType ePortA24Mode; + PORT_A25MuxType ePortA25Mode; + PORT_A26MuxType ePortA26Mode; + PORT_A27MuxType ePortA27Mode; + PORT_A28MuxType ePortA28Mode; + PORT_A29MuxType ePortA29Mode; + PORT_A30MuxType ePortA30Mode; + PORT_A31MuxType ePortA31Mode; + PORT_B0MuxType ePortB0Mode; + PORT_B1MuxType ePortB1Mode; + PORT_B3MuxType ePortB3Mode; + PORT_B4MuxType ePortB4Mode; + PORT_B5MuxType ePortB5Mode; + PORT_B6MuxType ePortB6Mode; + PORT_B7MuxType ePortB7Mode; + PORT_B8MuxType ePortB8Mode; + PORT_B9MuxType ePortB9Mode; + PORT_B10MuxType ePortB10Mode; + PORT_B11MuxType ePortB11Mode; + PORT_B12MuxType ePortB12Mode; + PORT_B13MuxType ePortB13Mode; + PORT_B14MuxType ePortB14Mode; + PORT_B15MuxType ePortB15Mode; + PORT_B16MuxType ePortB16Mode; + PORT_B17MuxType ePortB17Mode; + PORT_B18MuxType ePortB18Mode; + PORT_B19MuxType ePortB19Mode; + PORT_B20MuxType ePortB20Mode; + PORT_B21MuxType ePortB21Mode; + PORT_B22MuxType ePortB22Mode; + PORT_B23MuxType ePortB23Mode; + PORT_B24MuxType ePortB24Mode; + PORT_B25MuxType ePortB25Mode; + PORT_B26MuxType ePortB26Mode; + PORT_B27MuxType ePortB27Mode; + PORT_B28MuxType ePortB28Mode; + PORT_B29MuxType ePortB29Mode; + PORT_B30MuxType ePortB30Mode; + PORT_B31MuxType ePortB31Mode; + PORT_C0MuxType ePortC0Mode; + PORT_C1MuxType ePortC1Mode; + PORT_C2MuxType ePortC2Mode; + PORT_C3MuxType ePortC3Mode; + PORT_C4MuxType ePortC4Mode; + PORT_C5MuxType ePortC5Mode; + PORT_C6MuxType ePortC6Mode; + PORT_C7MuxType ePortC7Mode; + PORT_C8MuxType ePortC8Mode; + PORT_C9MuxType ePortC9Mode; + PORT_C10MuxType ePortC10Mode; + PORT_C11MuxType ePortC11Mode; + PORT_C12MuxType ePortC12Mode; + PORT_C13MuxType ePortC13Mode; + PORT_C14MuxType ePortC14Mode; + PORT_C15MuxType ePortC15Mode; + PORT_C16MuxType ePortC16Mode; + PORT_C17MuxType ePortC17Mode; + PORT_C18MuxType ePortC18Mode; + PORT_C19MuxType ePortC19Mode; + PORT_C20MuxType ePortC20Mode; + PORT_C21MuxType ePortC21Mode; + PORT_C22MuxType ePortC22Mode; + PORT_C23MuxType ePortC23Mode; + PORT_C24MuxType ePortC24Mode; + PORT_C25MuxType ePortC25Mode; + PORT_C26MuxType ePortC26Mode; + PORT_C27MuxType ePortC27Mode; + PORT_C28MuxType ePortC28Mode; + PORT_C29MuxType ePortC29Mode; + PORT_C30MuxType ePortC30Mode; + PORT_C31MuxType ePortC31Mode; + PORT_D0MuxType ePortD0Mode; + PORT_D1MuxType ePortD1Mode; + PORT_D2MuxType ePortD2Mode; + PORT_D3MuxType ePortD3Mode; + PORT_D4MuxType ePortD4Mode; + PORT_D5MuxType ePortD5Mode; + PORT_D6MuxType ePortD6Mode; + PORT_D7MuxType ePortD7Mode; + PORT_D8MuxType ePortD8Mode; + PORT_D9MuxType ePortD9Mode; + PORT_D10MuxType ePortD10Mode; + PORT_D11MuxType ePortD11Mode; + PORT_D12MuxType ePortD12Mode; + PORT_D13MuxType ePortD13Mode; + PORT_D15MuxType ePortD15Mode; + PORT_D16MuxType ePortD16Mode; + PORT_D17MuxType ePortD17Mode; + PORT_D18MuxType ePortD18Mode; + PORT_D19MuxType ePortD19Mode; + PORT_D20MuxType ePortD20Mode; + PORT_D21MuxType ePortD21Mode; + PORT_D22MuxType ePortD22Mode; + PORT_D23MuxType ePortD23Mode; + PORT_D24MuxType ePortD24Mode; + PORT_D25MuxType ePortD25Mode; + PORT_D26MuxType ePortD26Mode; + PORT_D27MuxType ePortD27Mode; + PORT_D28MuxType ePortD28Mode; + PORT_D29MuxType ePortD29Mode; + PORT_D30MuxType ePortD30Mode; + PORT_D31MuxType ePortD31Mode; + PORT_E0MuxType ePortE0Mode; + PORT_E1MuxType ePortE1Mode; + PORT_E2MuxType ePortE2Mode; + PORT_E3MuxType ePortE3Mode; + PORT_E4MuxType ePortE4Mode; + PORT_E5MuxType ePortE5Mode; + PORT_E6MuxType ePortE6Mode; + PORT_E7MuxType ePortE7Mode; + PORT_E8MuxType ePortE8Mode; + PORT_E9MuxType ePortE9Mode; + PORT_E10MuxType ePortE10Mode; + PORT_E11MuxType ePortE11Mode; + PORT_E12MuxType ePortE12Mode; + PORT_E13MuxType ePortE13Mode; + PORT_E14MuxType ePortE14Mode; + PORT_E15MuxType ePortE15Mode; + PORT_E16MuxType ePortE16Mode; + PORT_E17MuxType ePortE17Mode; + PORT_E18MuxType ePortE18Mode; + PORT_E19MuxType ePortE19Mode; + PORT_E20MuxType ePortE20Mode; + PORT_E21MuxType ePortE21Mode; + PORT_E22MuxType ePortE22Mode; + PORT_E23MuxType ePortE23Mode; + PORT_E24MuxType ePortE24Mode; + PORT_E25MuxType ePortE25Mode; + PORT_E26MuxType ePortE26Mode; + PORT_E27MuxType ePortE27Mode; + PORT_E29MuxType ePortE29Mode; + Port_PinModeType u32PortPinMode; +} Port_PinMuxType; + +/** @brief Port interrupt configuration */ +typedef enum +{ + PORT_IRQ_DISABLE = 0U, + PORT_IRQ_LOGIC_0 = 8U, + PORT_IRQ_RISING = 9U, + PORT_IRQ_FALLING = 10U, + PORT_IRQ_BOTH_EDGE = 11U, + PORT_IRQ_LOGIC_1 = 12U +} PORT_IntConfigType; + +/** @brief Port DMA request configuration */ +typedef enum +{ + PORT_DMA_REQ_DISABLE = 0U, + PORT_DMA_REQ_RISING = 1U, + PORT_DMA_REQ_FALLING = 2U, + PORT_DMA_REQ_BOTH_EDGE = 3U, +} PORT_DMAReqType; + +/** @brief Port digital filter clock source */ +typedef enum +{ + PORT_FILTER_BUS_CLK = 0U, + PORT_FILTER_AON32K_CLK, +} PORT_DigitalFilterClkSrcType; + +/** @brief Port pull status */ +typedef enum +{ + PORT_PULL_DOWN = 0U, + PORT_PULL_UP +} PORT_PullStatusType; + +/********* Local inline function ************/ +/** + * @brief Configure pin + * + * @param pPort Port instance + * @param u8Pin Pin number + * @param u32PcrReg Pin PCR register value + */ +LOCAL_INLINE void PORT_HWA_ConfigPin(PORT_Type *pPort, uint8_t u8Pin, uint32_t u32PcrReg) +{ + pPort->PCR[u8Pin] = u32PcrReg; +} + +/** + * @brief Configure Pin Domain Write Protection + * + * @param pPort Port instance + * @param u8Pin Pin number + * @param u32DwpValue Bit field value:Domain Write Protection + */ +LOCAL_INLINE void PORT_HWA_SelPinRegWrtPermit(PORT_Type *pPort, uint8_t u8Pin, uint32_t u32DwpValue) +{ + uint32_t u32TempRegVal = (uint32_t)(pPort->PCR[u8Pin]); + pPort->PCR[u8Pin] = (u32TempRegVal & (~ (uint32_t)PORT_PCR_DWP_MASK)) | PORT_PCR_DWP(u32DwpValue); +} + +/** + * @brief Configure Pin Domain Write Protection Lock + * + * @param pPort Port instance + * @param u8Pin Pin number + * @param bEnable Enable or Disable DWP Lock + */ +LOCAL_INLINE void PORT_HWA_ConfigPinDwpLock(PORT_Type *pPort, uint8_t u8Pin, bool bEnable) +{ + uint32_t u32TempRegVal = (uint32_t)(pPort->PCR[u8Pin]); + pPort->PCR[u8Pin] = (u32TempRegVal & (~ (uint32_t)PORT_PCR_DWPLK_MASK)) | PORT_PCR_DWPLK(bEnable); +} + +/** + * @brief Configure Pin Emergency Stop + * + * @param pPort Port instance + * @param u8Pin Pin number + * @param bEnable Enable or Disable Emergency Stop of this Pin + */ +LOCAL_INLINE void PORT_HWA_CfgPinEmgcyStop(PORT_Type *pPort, uint8_t u8Pin, bool bEnable) +{ + uint32_t u32TempRegVal = (uint32_t)(pPort->PCR[u8Pin]); + pPort->PCR[u8Pin] = (u32TempRegVal & (~ (uint32_t)PORT_PCR_ESTOP_MASK)) | PORT_PCR_ESTOP(bEnable); +} + +/** + * @brief Configure Global Domain Write Protection Lock + * + * @param pPort Port instance + * @param u8Pin Pin number + * @param bEnable Enable or Disable Global DWP Lock + */ +LOCAL_INLINE void PORT_HWA_CfgGlobalDwpLock(PORT_Type *pPort, bool bEnable) +{ + uint32_t u32TempRegVal = (uint32_t)(pPort->GLDWP); + pPort->GLDWP = (u32TempRegVal & (~ (uint32_t)PORT_GLDWP_DWPLK_MASK)) | PORT_GLDWP_DWPLK(bEnable); +} + +/** + * @brief Configure Global Domain Write Protection + * + * @param pPort Port instance + * @param u8Pin Pin number + * @param u32GlbDwpValue Bit field value:Global Domain Write Protection + */ +LOCAL_INLINE void PORT_HWA_CfgGlobalRegWrtPermit(PORT_Type *pPort, uint8_t u8Pin, uint32_t u32GlbDwpValue) +{ + uint32_t u32TempRegVal = (uint32_t)(pPort->PCR[u8Pin]); + pPort->GLDWP = (u32TempRegVal & (~ (uint32_t)PORT_GLDWP_DWP_MASK)) | PORT_GLDWP_DWP(u32GlbDwpValue); +} + +/** + * @brief Read pin interrupt flag + * + * @param pPort Port instance + * @param u8Pin Pin number + * @return interrupt flag value + */ +LOCAL_INLINE bool PORT_HWA_ReadPinInterruptFlag(PORT_Type *pPort, uint8_t u8Pin) +{ + return (bool)(pPort->PCR[u8Pin] & (uint32_t)PORT_PCR_ISF_MASK); +} + + +/** + * @brief Set pin multiplexing + * + * @param pPort Port instance + * @param u8Pin Pin number + * @param Port_PinMuxType Pin MXU configuration value + */ +LOCAL_INLINE void PORT_HWA_SetPinMux(PORT_Type *pPort, uint8_t u8Pin, Port_PinMuxType u32PinMux) +{ + uint32_t u32TempRegVal = (uint32_t)(pPort->PCR[u8Pin]); + pPort->PCR[u8Pin] = ((u32TempRegVal & ~(uint32_t)PORT_PCR_MUX_MASK) | PORT_PCR_MUX(u32PinMux.u32PortPinMode)); +} + +/** + * @brief Set pin interrupt mode + * + * @param pPort Port instance + * @param u8Pin Pin number + * @param u32PinIrqc Pin IRQC configuration value + */ +LOCAL_INLINE void PORT_HWA_SetPinInterruptMode(PORT_Type *pPort, uint8_t u8Pin, PORT_IntConfigType u32PinIrqc) +{ + uint32_t u32TempRegVal = (uint32_t)(pPort->PCR[u8Pin]); + pPort->PCR[u8Pin] = ((u32TempRegVal & ~(uint32_t)PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(u32PinIrqc)); +} + +/** + * @brief Set pin DMA request mode + * + * @param pPort Port instance + * @param u8Pin Pin number + * @param u32DMAReqMode Pin DMA request mode + */ +LOCAL_INLINE void PORT_HWA_SetPinDMAReqMode(PORT_Type *pPort, uint8_t u8Pin, PORT_DMAReqType u32DMAReqMode) +{ + uint32_t u32TempRegVal = (uint32_t)(pPort->PCR[u8Pin]); + pPort->PCR[u8Pin] = ((u32TempRegVal & ~(uint32_t)PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(u32DMAReqMode)); +} + +/** + * @brief Set pin pull enable + * + * @param pPort Port instance + * @param u8Pin Pin number + * @param u8PeValue Pin PE configuration value(1/0) + */ +LOCAL_INLINE void PORT_HWA_SetPinPullEnable(PORT_Type *pPort, uint8_t u8Pin, bool bPullEnable) +{ + if (bPullEnable) + { + pPort->PCR[u8Pin] |= (uint32_t)PORT_PCR_PE_MASK; + } + else + { + pPort->PCR[u8Pin] &= ~(uint32_t)PORT_PCR_PE_MASK; + } +} + +/** + * @brief Set pin pull mode + * + * @param pPort Port instance + * @param u8Pin Pin number + * @param u8PsValue Pin PS configuration value(1/0) + */ +LOCAL_INLINE void PORT_HWA_SetPinPullMode(PORT_Type *pPort, uint8_t u8Pin, PORT_PullStatusType u8PullSelect) +{ + uint32_t u32TempRegVal = (uint32_t)(pPort->PCR[u8Pin]); + pPort->PCR[u8Pin] = ((u32TempRegVal & ~(uint32_t)PORT_PCR_PS_MASK) | PORT_PCR_PS(u8PullSelect)); +} + +/** + * @brief Set pin drive strength 0 + * + * @param pPort Port instance + * @param u8Pin Pin number + * @note only hs PAD use this bit + */ +LOCAL_INLINE void PORT_HWA_EnablePinDriveStrength0(PORT_Type *pPort, uint8_t u8Pin) +{ + pPort->PCR[u8Pin] |= (uint32_t)PORT_PCR_DSE0_MASK; +} + +/** + * @brief Set pin drive strength 1 + * + * @param pPort Port instance + * @param u8Pin Pin number + * @note only UHS PAD use this bit + */ +LOCAL_INLINE void PORT_HWA_EnablePinDriveStrength1(PORT_Type *pPort, uint8_t u8Pin) +{ + pPort->PCR[u8Pin] |= (uint32_t)(PORT_PCR_DSE1_MASK | PORT_PCR_DSE0_MASK); +} + +/** + * @brief Set pin passive filter enable + * + * @param pPort Port instance + * @param u8Pin Pin number + * @param u8PfeValue Pin PFE configuration value(1/0) + */ +LOCAL_INLINE void PORT_HWA_SetPinPassiveFilterEnable(PORT_Type *pPort, uint8_t u8Pin, bool bPfEable) +{ + if (bPfEable) + { + pPort->PCR[u8Pin] |= (uint32_t)PORT_PCR_PFE_MASK; + } + else + { + pPort->PCR[u8Pin] &= ~(uint32_t)PORT_PCR_PFE_MASK; + } +} + +/** + * @brief Configure port digital filter + * + * @param pPort Port instance + * @param u32RegValue Enable bit,0-31 bit indicate pin 0-31 + */ +LOCAL_INLINE void PORT_HWA_ConfigDigitalFilter(PORT_Type *pPort, uint32_t u32RegValue) +{ + pPort->DFER = u32RegValue; +} + +/** + * @brief Set port digital filter enable + * + * @param pPort Port instance + * @param u8RegBit DFER register bit + */ +LOCAL_INLINE void PORT_HWA_SetDigitalFilterEnable(PORT_Type *pPort, uint8_t u8RegBit) +{ + pPort->DFER |= (uint32_t)1 << u8RegBit; +} + +/** + * @brief Set port digital filter clock source + * + * @param pPort Port instance + * @param eClkSrc Digital filter clock source + */ +LOCAL_INLINE void PORT_HWA_SetDigitalFilterClkSrc(PORT_Type *pPort, PORT_DigitalFilterClkSrcType eClkSrc) +{ + pPort->DFCR |= PORT_DFCR_CS(eClkSrc); +} + +/** + * @brief Configure digital filter width + * @param pPort Port instance + * @param u32FilterWidth Digital filter length value,range:0-31 + */ +LOCAL_INLINE void PORT_HWA_ConfigDigitalFilterWidth(PORT_Type *pPort, uint32_t u32FilterWidth) +{ + pPort->DFWR = PORT_DFWR_FILT(u32FilterWidth); +} + +/** + * @brief Clear pin interrupt mode + * + * @param pPort Port instance + * @param u8Pin Pin number + */ +LOCAL_INLINE void PORT_HWA_ClearPinInterruptMode(PORT_Type *pPort, uint8_t u8Pin) +{ + pPort->PCR[u8Pin] &= ~(uint32_t)PORT_PCR_IRQC_MASK; +} + +/** + * @brief Clear pin interrupt flag + * + * @param pPort Port instance + * @param u8Pin Pin number + */ +LOCAL_INLINE void PORT_HWA_ClearPinInterruptFlag(PORT_Type *pPort, uint8_t u8Pin) +{ + pPort->PCR[u8Pin] |= (uint32_t)PORT_PCR_ISF_MASK; +} + +/** + * @brief CLear port digital filter enable + * + * @param pPort Port instance + */ +LOCAL_INLINE void PORT_HWA_ClearDigitalFilterEnable(PORT_Type *pPort) +{ + pPort->DFER = (uint32_t)0U; +} + +/** + * @brief Clear port digital filter enable for specific pin + * + * @param pPort Port instance + * @param u8RegBit DFER register bit + */ +LOCAL_INLINE void PORT_HWA_ClearDigitalFilterPin(PORT_Type *pPort, uint8_t u8RegBit) +{ + pPort->DFER &= (uint32_t)~((uint32_t)1 << u8RegBit); +} + +/** + * @brief Clear port digital filter clock source + * + * @param pPort Port instance + */ +LOCAL_INLINE void PORT_HWA_ClearDigitalFilterClkSrc(PORT_Type *pPort) +{ + pPort->DFCR &= ~(uint32_t)PORT_DFCR_CS_MASK; +} + +/** + * @brief Clear port digital filter width + * + * @param pPort Port instance + */ +LOCAL_INLINE void PORT_HWA_ClearDigitalFilterWidth(PORT_Type *pPort) +{ + pPort->DFWR &= ~(uint32_t)PORT_DFWR_FILT_MASK; +} + +/** + * @brief Write Global Pin Control Low Register( Write Regvalue to bits[15:0] of PCR0 ~ 15 ) + * + * @param pPort Port instance + * @param u32Pin Port pin number + * @param u32LowPcrRegValue Register value in bits[15:0] of PCR0 ~ 15 + */ +LOCAL_INLINE void PORT_HWA_WriteGPCLR(PORT_Type *pPort,uint32_t u32Pin,uint32_t u32LowPcrRegValue) +{ + pPort->GPCLR = PORT_GPCLR_GPWE(u32Pin) | PORT_GPCLR_GPWD(u32LowPcrRegValue); +} + +/** + * @brief Write Global Pin Control High Register( Write Regvalue to bits[15:0] of PCR16 ~ 31 ) + * + * @param pPort Port instance + * @param u32Pin Port pin number + * @param u32LowPcrRegValue Register value in bits[15:0] of PCR16 ~ 31 + */ +LOCAL_INLINE void PORT_HWA_WriteGPCHR(PORT_Type *pPort,uint32_t u32Pin,uint32_t u32LowPcrRegValue) +{ + pPort->GPCHR = (u32Pin & PORT_GPCHR_GPWE_MASK) | PORT_GPCHR_GPWD(u32LowPcrRegValue); +} + +/** + * @brief Write Global Interrupt Control Low Register( Write Regvalue to bits[31:16] of PCR0 ~ 15 ) + * + * @param pPort Port instance + * @param u32Pin Port pin number + * @param u32HighPcrRegValue Register value in bits[31:16] of PCR0 ~ 15 + */ +LOCAL_INLINE void PORT_HWA_WriteGICLR(PORT_Type *pPort,uint32_t u32Pin,uint32_t u32HighPcrRegValue) +{ + pPort->GICLR = (u32HighPcrRegValue & PORT_GICLR_GIWD_MASK) | PORT_GICLR_GIWE(u32Pin); +} + +/** + * @brief Write Global Interrupt Control High Register( Write Regvalue to bits[31:16] of PCR16 ~ 31 ) + * + * @param pPort Port instance + * @param u32Pin Port pin number + * @param u32HighPcrRegValue Register value in bits[31:16] of PCR16 ~ 31 + */ +LOCAL_INLINE void PORT_HWA_WriteGICHR(PORT_Type *pPort,uint32_t u32Pin,uint32_t u32HighPcrRegValue) +{ + pPort->GICHR = (u32HighPcrRegValue & PORT_GICHR_GIWD_MASK) & PORT_GICHR_GIWE(u32Pin); +} + + +#endif /* #ifndef _HWA_PORT_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_ptimer.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_ptimer.h new file mode 100644 index 0000000..3e7dbfc --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_ptimer.h @@ -0,0 +1,701 @@ +/** + * @file HwA_ptimer.h + * @author Flagchip0126 + * @brief Hardware access layer for PTIMER + * @version 0.1.0 + * @date 2024-01-15 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-15 Flagchip0126 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef _HWA_PTIMER_H_ +#define _HWA_PTIMER_H_ + +#include "device_header.h" + +/** + * @defgroup HwA_ptimer + * @ingroup fc4xxx_driver_ptimer + * @{ + */ + +/** + * @brief Ptimer value load mode + * + * Some Ptimer registers are buffered and will only take effect after called + * PTIMER_LoadValue() function, and this option selects when the buffered configurations + * will tack effect after PTIMER_LoadValue() is called. + * + */ +typedef enum +{ + PTIMER_LOAD_VAL_IMMEDIATELY = 0U, + /*!< Loaded immediately after load operation. */ + PTIMER_LOAD_VAL_AT_MODULO_COUNTER = 1U, + /*!< Loaded when counter hits the max count after load operation. */ + PTIMER_LOAD_VAL_AT_NEXT_TRIGGER = 2U, + /*!< Loaded when detecting an input trigger after load operation. */ + PTIMER_LOAD_VAL_AT_MODULO_COUNTER_OR_NEXT_TRIGGER = 3U + /*!< Loaded when counter hits the max count or detecting an input trigger after load operation. */ +} PTIMER_LoadValueModeType; + +/** + * @brief Ptimer clock pre-divider factor + * + * The Ptimer clock source is from core clock and the divider is a multiplication of + * PTIMER_ClockPreDividerType and PTIMER_ClockPreDivMultiplyFactorType, and thus: + * Freq = Core_Freq / (PTIMER_ClockPreDividerType * PTIMER_ClockPreDivMultiplyFactorType) + * + */ +typedef enum +{ + PTIMER_PRE_DIVIDE_BY_1 = 0U, + PTIMER_PRE_DIVIDE_BY_2 = 1U, + PTIMER_PRE_DIVIDE_BY_4 = 2U, + PTIMER_PRE_DIVIDE_BY_8 = 3U, + PTIMER_PRE_DIVIDE_BY_16 = 4U, + PTIMER_PRE_DIVIDE_BY_32 = 5U, + PTIMER_PRE_DIVIDE_BY_64 = 6U, + PTIMER_PRE_DIVIDE_BY_128 = 7U +} PTIMER_ClockPreDividerType; + +/** + * @brief Ptimer clock divider multiplication factor + * + * The Ptimer clock source is from core clock and the divider is a multiplication of + * PTIMER_ClockPreDividerType and PTIMER_ClockPreDivMultiplyFactorType, and thus: + * Freq = Core_Freq / (PTIMER_ClockPreDividerType * PTIMER_ClockPreDivMultiplyFactorType) + * + */ +typedef enum +{ + PTIMER_PRE_DIVIDER_MULTIPLY_BY_1 = 0U, + PTIMER_PRE_DIVIDER_MULTIPLY_BY_10 = 1U, + PTIMER_PRE_DIVIDER_MULTIPLY_BY_20 = 2U, + PTIMER_PRE_DIVIDER_MULTIPLY_BY_40 = 3U +} PTIMER_ClockPreDivMultiplyFactorType; + +/** + * @brief Ptimer trigger source + * + */ +typedef enum +{ + PTIMER_TRGSRC_TRGSEL = 0x00U, /*!< Ptimer trigger source from TrgSel */ + PTIMER_TRGSRC_SW = 0x0FU /*!< Ptimer trigger source from software trigger*/ +} PTIMER_TrgSrcType; + +/** + * @brief Get the STATUS_CTRL register value + * + * @param pPtimer the base address of the Ptimer instance + */ +LOCAL_INLINE uint32_t PTIMER_HWA_GetStatusCtrl(const PTIMER_Type *const pPtimer) +{ + return pPtimer->STATUS_CTRL; +} + +/** + * @brief Set the STATUS_CTRL register value + * + * @param pPtimer the base address of the Ptimer instance + * @param u32CfgValue the register value to set + */ +LOCAL_INLINE void PTIMER_HWA_SetStatusCtrl(PTIMER_Type *const pPtimer, uint32_t u32CfgValue) +{ + pPtimer->STATUS_CTRL = u32CfgValue; +} + +/** + * @brief Get the load mode of the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @return PTIMER_LoadValueModeType the load mode of the Ptimer instance + */ +LOCAL_INLINE PTIMER_LoadValueModeType PTIMER_HWA_GetLoadMode(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_LDMODE_MASK) >> PTIMER_STATUS_CTRL_LDMODE_SHIFT; + return (PTIMER_LoadValueModeType)u32TmpVal; +} + +/** + * @brief Set the load mode of the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @param eLoadMode the load mode of the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_SetLoadMode(PTIMER_Type *const pPtimer, PTIMER_LoadValueModeType eLoadMode) +{ + pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_LDMODE_MASK) | PTIMER_STATUS_CTRL_LDMODE(eLoadMode); +} + +/** + * @brief Get whether sequence error interrupt is enabled + * + * @param pPtimer the base address of the Ptimer instance + * @return true sequence error interrupt is enabled + * @return false sequence error interrupt is disabled + */ +LOCAL_INLINE bool PTIMER_HWA_GetSeqErrIntEnableFlag(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_SERR_INTEN_MASK) >> PTIMER_STATUS_CTRL_SERR_INTEN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable sequence error interrupt + * + * @param pPtimer the base address of the Ptimer instance + * @param bEnable whether to enable sequence error interrupt + */ +LOCAL_INLINE void PTIMER_HWA_SetSeqErrIntEnableFlag(PTIMER_Type *const pPtimer, bool bEnable) +{ + pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_SERR_INTEN_MASK) | PTIMER_STATUS_CTRL_SERR_INTEN( + bEnable ? 1U : 0U); +} + +/** + * @brief Generate software trigger signal for Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_GenerateSwTrigger(PTIMER_Type *const pPtimer) +{ + pPtimer->STATUS_CTRL |= PTIMER_STATUS_CTRL_SWTRG_MASK; +} + +/** + * @brief Get whether DMA is enabled for the Ptimer insstance + * + * @param pPtimer the base address of the Ptimer instance + * @return true DMA is enabled + * @return false DMA is disabled + */ +LOCAL_INLINE bool PTIMER_HWA_GetDMAEnableFlag(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_DMAEN_MASK) >> PTIMER_STATUS_CTRL_DMAEN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable Ptimer DMA + * + * @param pPtimer the base address of the Ptimer instance + * @param bEnable whether to enable DMA for the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_SetDMAEnableFlag(PTIMER_Type *const pPtimer, bool bEnable) +{ + pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_DMAEN_MASK) | PTIMER_STATUS_CTRL_DMAEN(bEnable ? 1U : 0U); +} + +/** + * @brief Get the predivider value of the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @return PTIMER_ClockPreDividerType the predivider of the Ptimer instance + */ +LOCAL_INLINE PTIMER_ClockPreDividerType PTIMER_HWA_GetDivPrescaler(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_PRESCALER_MASK) >> PTIMER_STATUS_CTRL_PRESCALER_SHIFT; + return (PTIMER_ClockPreDividerType)u32TmpVal; +} + +/** + * @brief Set the predivider value of the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @param eDivPrescaler the predivider of the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_SetDivPrescaler(PTIMER_Type *const pPtimer, PTIMER_ClockPreDividerType eDivPrescaler) +{ + pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_PRESCALER_MASK) | PTIMER_STATUS_CTRL_PRESCALER( + eDivPrescaler); +} + +/** + * @brief Get the trigger source of the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @return PTIMER_TRGSRC_TRGSEL the trigger source is from TrgSel + * @return PTIMER_TRGSRC_SW the trigger source is from software + */ +LOCAL_INLINE PTIMER_TrgSrcType PTIMER_HWA_GetTriggerSource(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_TRGSEL_MASK) >> PTIMER_STATUS_CTRL_TRGSEL_SHIFT; + return (PTIMER_TrgSrcType)u32TmpVal; +} + +/** + * @brief Set the trigger source of the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @param eTriggerSource the trigger source of the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_SetTriggerSource(PTIMER_Type *const pPtimer, PTIMER_TrgSrcType eTriggerSource) +{ + pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_TRGSEL_MASK) | PTIMER_STATUS_CTRL_TRGSEL( + eTriggerSource); +} + +/** + * @brief Get whether the Ptimer instance is enabled + * + * @param pPtimer the base address of the Ptimer instance + * @return true the Ptimer instance is enabled + * @return false the Ptimer instance is disabled + */ +LOCAL_INLINE bool PTIMER_HWA_GetEnableFlag(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_ENABLE_MASK) >> PTIMER_STATUS_CTRL_ENABLE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Enable the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_Enable(PTIMER_Type *const pPtimer) +{ + pPtimer->STATUS_CTRL |= PTIMER_STATUS_CTRL_ENABLE_MASK; +} + +/** + * @brief Disable the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_Disable(PTIMER_Type *const pPtimer) +{ + pPtimer->STATUS_CTRL &= ~PTIMER_STATUS_CTRL_ENABLE_MASK; +} + +/** + * @brief Get the delay interrupt flag of the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @return true the delay interrupt flag of the Ptimer instance is generated + * @return false the delay interrupt flag of the Ptimer instance is not generated + */ +LOCAL_INLINE bool PTIMER_HWA_GetInterruptFlag(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_INTFLAG_MASK) >> PTIMER_STATUS_CTRL_INTFLAG_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the delay interrupt flag of the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_ClearInterruptFlag(PTIMER_Type *const pPtimer) +{ + pPtimer->STATUS_CTRL &= ~PTIMER_STATUS_CTRL_INTFLAG_MASK; +} + +/** + * @brief Get whether delay interrupt is enabled for the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + */ +LOCAL_INLINE bool PTIMER_HWA_GetInterruptEnableFlag(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_INTEN_MASK) >> PTIMER_STATUS_CTRL_INTEN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable delay interrupt for the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @param bEnable whether to enable delay interrupt for the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_SetInterruptEnableFlag(PTIMER_Type *const pPtimer, bool bEnable) +{ + pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_INTEN_MASK) | PTIMER_STATUS_CTRL_INTEN(bEnable ? 1U : 0U); +} + +/** + * @brief Get the multiply factor of the predivider of the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @return PTIMER_ClockPreDivMultiplyFactorType the multiply factor of the Ptimer instance + */ +LOCAL_INLINE PTIMER_ClockPreDivMultiplyFactorType PTIMER_HWA_GetDivMultiply(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_MULT_MASK) >> PTIMER_STATUS_CTRL_MULT_SHIFT; + return (PTIMER_ClockPreDivMultiplyFactorType)u32TmpVal; +} + +/** + * @brief Set the multiply factor of the predivider of the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @param eMultFactor the multiply factor of the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_SetDivMultiply(PTIMER_Type *const pPtimer, + PTIMER_ClockPreDivMultiplyFactorType eMultFactor) +{ + pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_MULT_MASK) | PTIMER_STATUS_CTRL_MULT(eMultFactor); +} + +/** + * @brief Get whether continuous mode is enabled for the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @return true continuous mode is enabled for the Ptimer instance + * @return false continuous mode is disabled for the Ptimer instance + */ +LOCAL_INLINE bool PTIMER_HWA_GetContinuoiusModeFlag(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_CONT_MASK) >> PTIMER_STATUS_CTRL_CONT_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set whether to enable continuous mode for the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @param bEnable whether to enable continuous mode for the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_SetContinuoiusModeFlag(PTIMER_Type *const pPtimer, bool bEnable) +{ + pPtimer->STATUS_CTRL = (pPtimer->STATUS_CTRL & ~PTIMER_STATUS_CTRL_CONT_MASK) | PTIMER_STATUS_CTRL_CONT(bEnable ? 1U : 0U); +} + +/** + * @brief Get the config value loading status + * + * @param pPtimer the base address of the Ptimer instance + * @return true the config values are in loading status + * @return false the config values are loaded + */ +LOCAL_INLINE bool PTIMER_HWA_GetValueLoadStatus(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->STATUS_CTRL & PTIMER_STATUS_CTRL_LDOK_MASK) >> PTIMER_STATUS_CTRL_LDOK_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Load the buffered values into register + * + * @note Some Ptimer registers are buffered and will only take effect after called + * this function + * + * @param pPtimer the base address of the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_LoadValue(PTIMER_Type *const pPtimer) +{ + pPtimer->STATUS_CTRL |= PTIMER_STATUS_CTRL_LDOK_MASK; +} + +/** + * @brief Get the Ptimer max counter period + * When the Ptimer counter reaches the period, it will return to zero + * + * @param pPtimer the base address of the Ptimer instance + * @return uint16_t the Ptimer max count + */ +LOCAL_INLINE uint16_t PTIMER_HWA_GetMaxCount(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->MAX_CNT & PTIMER_MAX_CNT_MAX_CNT_MASK) >> PTIMER_MAX_CNT_MAX_CNT_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Set the Ptimer max counter period + * When the Ptimer counter reaches the period, it will return to zero + * + * @note the period parameter is buffered and will take effect only after called PTIMER_LoadValue() + * function. + * + * @param pPtimer the base address of the Ptimer instance + * @param u16MaxCnt the Ptimer max count + */ +LOCAL_INLINE void PTIMER_HWA_SetMaxCount(PTIMER_Type *const pPtimer, uint16_t u16MaxCnt) +{ + pPtimer->MAX_CNT = PTIMER_MAX_CNT_MAX_CNT(u16MaxCnt); +} + +/** + * @brief Get the Ptimer current count value + * + * @param pPtimer the base address of the Ptimer instance + * @return uint16_t the Ptimer current count value + */ +LOCAL_INLINE uint16_t PTIMER_HWA_GetCounterValue(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->CNT & PTIMER_CNT_CNT_MASK) >> PTIMER_CNT_CNT_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Get the ptimer interrupt period + * + * @param pPtimer the base address of the Ptimer instance + * @return uint16_t the Ptimer interrupt period + */ +LOCAL_INLINE uint16_t PTIMER_HWA_GetInterruptDelay(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->INT_DLY & PTIMER_INT_DLY_INT_DLY_MASK) >> PTIMER_INT_DLY_INT_DLY_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Set the ptimer interrupt period + * + * @param pPtimer the base address of the Ptimer instance + * @param u16InterruptDelay the Ptimer interrupt period + */ +LOCAL_INLINE void PTIMER_HWA_SetInterruptDelay(PTIMER_Type *const pPtimer, uint16_t u16InterruptDelay) +{ + pPtimer->INT_DLY = PTIMER_INT_DLY_INT_DLY(u16InterruptDelay); +} + +/** + * @brief Get whether back to back trigger is enbaled for the Ptimer channel + * + * @param pPtimer the base address of the Ptimer instance + * @param u8Channel the Ptimer channel + * @return true back to back trigger is enbaled for the Ptimer channel + * @return false back to back trigger is disabled for the Ptimer channel + */ +LOCAL_INLINE bool PTIMER_HWA_GetChannelBackToBackFlag(const PTIMER_Type *const pPtimer, uint8_t u8Channel) +{ + uint8_t u8PtimerChannelIdx = u8Channel / 8U; + uint8_t u8PtimerCtrlIdx = u8Channel % 8U; + uint32_t u32TmpVal = (pPtimer->CH[u8PtimerChannelIdx].CTRL & PTIMER_CTRL_CH_BTB(1UL << u8PtimerCtrlIdx)) >> + (PTIMER_CTRL_CH_BTB_SHIFT + u8PtimerCtrlIdx); + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get whether pre-trigger output is enbaled for the Ptimer channel + * + * @param pPtimer the base address of the Ptimer instance + * @param u8Channel the Ptimer channel + * @return true pre-trigger output is enbaled for the Ptimer channel + * @return false pre-trigger output is disabled for the Ptimer channel + */ +LOCAL_INLINE bool PTIMER_HWA_GetChannelPretriggerOutputFlag(const PTIMER_Type *const pPtimer, uint8_t u8Channel) +{ + uint8_t u8PtimerChannelIdx = u8Channel / 8U; + uint8_t u8PtimerCtrlIdx = u8Channel % 8U; + uint32_t u32TmpVal = (pPtimer->CH[u8PtimerChannelIdx].CTRL & PTIMER_CTRL_CH_PTOS(1UL << u8PtimerCtrlIdx)) >> + (PTIMER_CTRL_CH_PTOS_SHIFT + u8PtimerCtrlIdx); + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get whether pre-trigger is enbaled for the Ptimer channel + * + * @param pPtimer the base address of the Ptimer instance + * @param u8Channel the Ptimer channel + * @return true pre-trigger is enbaled for the Ptimer channel + * @return false pre-trigger is disabled for the Ptimer channel + */ +LOCAL_INLINE bool PTIMER_HWA_GetChannelPretriggerEnableFlag(const PTIMER_Type *const pPtimer, uint8_t u8Channel) +{ + uint8_t u8PtimerChannelIdx = u8Channel / 8U; + uint8_t u8PtimerCtrlIdx = u8Channel % 8U; + uint32_t u32TmpVal = (pPtimer->CH[u8PtimerChannelIdx].CTRL & PTIMER_CTRL_CH_PTEN(1UL << u8PtimerCtrlIdx)) >> + (PTIMER_CTRL_CH_PTEN_SHIFT + u8PtimerCtrlIdx); + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the Ptimer channel control flags + * + * @param pPtimer the base address of the Ptimer instance + * @param u8Channel the Ptimer channel + * @param bEnablePretrigger whether to enable pre-trigger + * @param bEnablePretriggerOutput whether to enable pre-trigger output + * @param bEnableBackToBack whether to enable back to back trigger + */ +LOCAL_INLINE void PTIMER_HWA_SetChannelControl(PTIMER_Type *const pPtimer, uint8_t u8Channel, bool bEnablePretrigger, + bool bEnablePretriggerOutput, bool bEnableBackToBack) +{ + uint8_t u8PtimerChannelIdx = u8Channel / 8U; + uint8_t u8PtimerCtrlIdx = u8Channel % 8U; + uint32_t u32CtrlMask = PTIMER_CTRL_CH_PTEN(1UL << u8PtimerCtrlIdx) | + PTIMER_CTRL_CH_PTOS(1UL << u8PtimerCtrlIdx) | + PTIMER_CTRL_CH_BTB(1UL << u8PtimerCtrlIdx); + pPtimer->CH[u8PtimerChannelIdx].CTRL = (pPtimer->CH[u8PtimerChannelIdx].CTRL & ~u32CtrlMask) | + PTIMER_CTRL_CH_PTEN((bEnablePretrigger ? 1UL : 0UL) << u8PtimerCtrlIdx) | + PTIMER_CTRL_CH_PTOS((bEnablePretriggerOutput ? 1UL : 0UL) << u8PtimerCtrlIdx) | + PTIMER_CTRL_CH_BTB((bEnableBackToBack ? 1UL : 0UL) << u8PtimerCtrlIdx); +} + +/** + * @brief Get whether the Ptimer counter matches the channel counter + * + * @param pPtimer the base address of the Ptimer instance + * @param u8Channel the Ptimer channel + * @return true the Ptimer counter matches the channel counter + * @return false the Ptimer counter has not reached the channel counter + */ +LOCAL_INLINE bool PTIMER_HWA_GetChannelCounterFlag(const PTIMER_Type *const pPtimer, uint8_t u8Channel) +{ + uint8_t u8PtimerChannelIdx = u8Channel / 8U; + uint8_t u8PtimerStatusIdx = u8Channel % 8U; + uint32_t u32TmpVal = (pPtimer->CH[u8PtimerChannelIdx].STATUS & PTIMER_STATUS_CH_CHN_FLAG(1UL << u8PtimerStatusIdx)) >> + (PTIMER_STATUS_CH_CHN_FLAG_SHIFT + u8PtimerStatusIdx); + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the Ptimer channel counter match flag + * + * @param pPtimer the base address of the Ptimer instance + * @param u8Channel the Ptimer channel + */ +LOCAL_INLINE void PTIMER_HWA_ClearChannelCounterFlag(PTIMER_Type *const pPtimer, uint8_t u8Channel) +{ + uint8_t u8PtimerChannelIdx = u8Channel / 8U; + uint8_t u8PtimerStatusIdx = u8Channel % 8U; + pPtimer->CH[u8PtimerChannelIdx].STATUS &= ~PTIMER_STATUS_CH_CHN_FLAG(1UL << u8PtimerStatusIdx); +} + +/** + * @brief Get the sequence error status of the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + * @param u8Channel the channel related to the sequence error + * @return true the selected channel has sequence error + * @return false the selected channel does not have sequence error + */ +LOCAL_INLINE bool PTIMER_HWA_GetChannelSequenceErrorFlag(const PTIMER_Type *const pPtimer, uint8_t u8Channel) +{ + uint8_t u8PtimerChannelIdx = u8Channel / 8U; + uint8_t u8PtimerStatusIdx = u8Channel % 8U; + uint32_t u32TmpVal = (pPtimer->CH[u8PtimerChannelIdx].STATUS & PTIMER_STATUS_CH_SERR_FLAG(1UL << u8PtimerStatusIdx)) >> + (PTIMER_STATUS_CH_SERR_FLAG_SHIFT + u8PtimerStatusIdx); + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the sequence error flag of the selected Ptimer channel + * + * @param pPtimer the base address of the Ptimer instance + * @param u8Channel the Ptimer channel to clear the sequence error flag + */ +LOCAL_INLINE void PTIMER_HWA_ClearChannelSequenceErrorFlag(PTIMER_Type *const pPtimer, uint8_t u8Channel) +{ + uint8_t u8PtimerChannelIdx = u8Channel / 8U; + uint8_t u8PtimerStatusIdx = u8Channel % 8U; + pPtimer->CH[u8PtimerChannelIdx].STATUS &= ~PTIMER_STATUS_CH_SERR_FLAG(1UL << u8PtimerStatusIdx); +} + +/** + * @brief Get the channel delay value + * + * @param pPtimer the base address of the Ptimer instance + * @param u8Channel the Ptimer channel + * @return uint16_t the channel delay value + */ +LOCAL_INLINE uint16_t PTIMER_HWA_GetChannelDelay(const PTIMER_Type *const pPtimer, uint8_t u8Channel) +{ + uint8_t u8PtimerChannelIdx = u8Channel / PTIMER_CH_DLY_CNT; + uint8_t u8PtimerDelayIdx = u8Channel % PTIMER_CH_DLY_CNT; + uint32_t u32TmpVal = (pPtimer->CH[u8PtimerChannelIdx].DLY[u8PtimerDelayIdx] & PTIMER_DLY_CH_CHNDLY_MASK) >> + PTIMER_DLY_CH_CHNDLY_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Set the channel delay value + * + * @param pPtimer the base address of the Ptimer instance + * @param u8Channel the Ptimer channel + * @param u16Delay the channel delay value + */ +LOCAL_INLINE void PTIMER_HWA_SetChannelDelay(PTIMER_Type *const pPtimer, uint8_t u8Channel, uint16_t u16Delay) +{ + uint8_t u8PtimerChannelIdx = u8Channel / PTIMER_CH_DLY_CNT; + uint8_t u8PtimerDelayIdx = u8Channel % PTIMER_CH_DLY_CNT; + pPtimer->CH[u8PtimerChannelIdx].DLY[u8PtimerDelayIdx] = PTIMER_DLY_CH_CHNDLY(u16Delay); +} + +/** + * @brief Get whether pulse-out is enabled + * + * @param pPtimer the base address of the Ptimer instance + * @return true pulse-out is enabled + * @return false pulse-out is disabled + */ +LOCAL_INLINE bool PTIMER_HWA_GetPulseOutEnableFlag(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->POEN & PTIMER_POEN_POEN_MASK) >> PTIMER_POEN_POEN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Enable pulse-out for the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_EnablePulseOut(PTIMER_Type *const pPtimer) +{ + pPtimer->POEN |= PTIMER_POEN_POEN_MASK; +} + +/** + * @brief Disable pulse-out for the Ptimer instance + * + * @param pPtimer the base address of the Ptimer instance + */ +LOCAL_INLINE void PTIMER_HWA_DisablePulseOut(PTIMER_Type *const pPtimer) +{ + pPtimer->POEN &= ~PTIMER_POEN_POEN_MASK; +} + +/** + * @brief Get the delay high value for the pulse-out function + * When the Ptimer counter reach the delay high value, the pulse output goes high + * + * @param pPtimer the base address of the Ptimer instance + */ +LOCAL_INLINE uint16_t PTIMER_HWA_GetPulseOutDelayHigh(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->PODLY & PTIMER_PODLY_DLY1_MASK) >> PTIMER_PODLY_DLY1_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Get the delay low value for the pulse-out function + * When the Ptimer counter reach the delay low value, the pulse output goes low + * + * @param pPtimer the base address of the Ptimer instance + */ +LOCAL_INLINE uint16_t PTIMER_HWA_GetPulseOutDelayLow(const PTIMER_Type *const pPtimer) +{ + uint32_t u32TmpVal = (pPtimer->PODLY & PTIMER_PODLY_DLY2_MASK) >> PTIMER_PODLY_DLY2_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Set the pulse out delay value + * When the Ptimer counter reach the delay high value, the pulse output goes high + * When the Ptimer counter reach the delay low value, the pulse output goes low + * The delay high value can be either greater or less than the delay low value + * + * @param pPtimer the base address of the Ptimer instance + * @param u16DelayHigh the delay high value + * @param u16DelayLow the delay low value + */ +LOCAL_INLINE void PTIMER_HWA_SetPulseOutDelay(PTIMER_Type *const pPtimer, uint16_t u16DelayHigh, uint16_t u16DelayLow) +{ + pPtimer->PODLY = PTIMER_PODLY_DLY1(u16DelayHigh) | PTIMER_PODLY_DLY2(u16DelayLow); +} + +/** @}*/ + +#endif /* _HWA_PTIMER_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_rgm.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_rgm.h new file mode 100644 index 0000000..22ccab7 --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_rgm.h @@ -0,0 +1,427 @@ +/** + * @file HwA_rgm.h + * @author Flagchip + * @brief FC7xxx RGM hardware access layer + * @version 0.1.0 + * @date 2024-01-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-12 Flagchip119 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef _HWA_RGM_H_ +#define _HWA_RGM_H_ + +#include "device_header.h" +/********* Local typedef ************/ +/** @brief Rgm reset event */ +typedef enum +{ + RGM_WAKEUP = 0x00000001U, + RGM_LVD = 0x00000002U, + RGM_CLKERR1 = 0x00000004U, + RGM_CLKERR0 = 0x00000008U, + RGM_FSCMU = 0x00000010U, + RGM_HSMWDOG = 0x00000020U, + RGM_PIN = 0x00000040U, + RGM_POR = 0x00000080U, + RGM_JTAG = 0x00000100U, + RGM_SYSAP = 0x00000800U, + RGM_WDOG1 = 0x00001000U, + RGM_SACKERR = 0x00002000U, + RGM_CMU = 0x00004000U, + RGM_LBIST = 0x00008000U, + RGM_FSMERR = 0x20000000U, + RGM_PINRSTTOUT = 0x40000000U, + RGM_SYSRSTTOUT = 0x80000000U +} RGM_ResetEventType; + +/** @brief Rgm reset interrupt delay cycles type. */ +typedef enum +{ + RGM_8_CLOCK_CYCLES = 0x00U, + RGM_32_CLOCK_CYCLES = 0x01U, + RGM_128_CLOCK_CYCLES = 0x02U, + RGM_512_CLOCK_CYCLES = 0x03U +} RGM_ResetDelayType; + +/** @brief Rgm reset interrupt event manger */ +typedef enum +{ + RGM_INT_CLKERR0 = 0x0008U, + RGM_INT_FCSMU = 0x0010U, + RGM_INT_WDG = 0x0020U, + RGM_INT_PIN = 0x0040U, + RGM_INT_JTAG = 0x0100U, + RGM_INT_CPULOC = 0x0200U, + RGM_INT_SW = 0x0400U, + RGM_INT_SYSAP = 0x0800U, + RGM_INT_WDOG1 = 0x1000U, + RGM_INT_SACKERR = 0x2000U, + RGM_INT_CMU = 0x4000U +} RGM_ResetIntMangerType; + +/** @brief Select the Rgm CORE Write protection */ +typedef enum +{ + RGM_WPB_ALL = 0x00U, + RGM_WPB_CPU0 = 0x01U, + RGM_WPB_NOCORE = 0x04U +} RGM_WriteprotectionBitType; + +/** @brief Rgm CPU0,1,2 related interrupt event manger */ +typedef enum +{ + RGM_CPU_INT_LOCKUP = 0x01U, + RGM_CPU_INT_SYSRST = 0x02U, + RGM_CPU_INT_WDOG = 0x04U, + RGM_CPU_INT_INTM = 0x08U, + RGM_CPU_INT_SWRST = 0x10U +} RGM_CPUIntMangerType; + +/** @brief Rgm CPU0,1,2 software reset status */ +typedef enum +{ + RGM_CPU_OUT_RST_UNDER = 0x00U, + RGM_CPU_OUT_RST_OUT = 0x01U +} RGM_CPUOutResetType; + +/** @brief Rgm CPU0,1,2 reset event */ +typedef enum +{ + RGM_CPU_WAKEUP = 0x00000001U, + RGM_CPU_LVD = 0x00000002U, + RGM_CPU_CLKERR1 = 0x00000004U, + RGM_CPU_CLKERR0 = 0x00000008U, + RGM_CPU_FSCMU = 0x00000010U, + RGM_CPU_HSMWDOG = 0x00000020U, + RGM_CPU_PIN = 0x00000040U, + RGM_CPU_POR = 0x00000080U, + RGM_CPU_JTAG = 0x00000100U, + RGM_CPU_SYSAP = 0x00000800U, + RGM_CPU_WDOG1 = 0x00001000U, + RGM_CPU_SACKERR = 0x00002000U, + RGM_CPU_CMU = 0x00004000U, + RGM_CPU_LBIST = 0x00008000U, + RGM_CPU_LOCKUP = 0x00010000U, + RGM_CPU_SYSRST = 0x00020000U, + RGM_CPU_WDOG = 0x00040000U, + RGM_CPU_INTM = 0x00080000U, + RGM_CPU_SWRST = 0x00100000U, + RGM_CPU_FSMERR = 0x20000000U, + RGM_CPU_PINRSTTOUT = 0x40000000U, + RGM_CPU_SYSRSTTOUT = 0x80000000U +} RGM_CPUResetEventType; + +/** @brief Rgm CPU1,2 system reset enable flag */ +typedef enum +{ + RGM_CPU_EN_LOCKUP = 0x00010000U, + RGM_CPU_EN_SYSRST = 0x00020000U, + RGM_CPU_EN_WDOG = 0x00040000U, + RGM_CPU_EN_INTM = 0x00080000U, + RGM_CPU_EN_SWRST = 0x00100000U, +} RGM_CPUSystemRstMangerType; +/********* Local inline function ************/ +/** + * @brief Read last reset flag + * + * @return Last reset flag + */ +LOCAL_INLINE uint32_t RGM_HWA_ReadLastResetFlag(void) +{ + return (uint32_t)RGM->SRS; +} + +/** + * @brief Read all reset flag before POR,SSRS register is reset on POR only + * + * @return All reset flag before POR + */ +LOCAL_INLINE uint32_t RGM_HWA_ReadAllResetFlagBeforePOR(void) +{ + return (uint32_t)RGM->SSRS; +} + +/** + * @brief Read reset pin filter register + * + * @return Reset pin filter register + */ +LOCAL_INLINE uint32_t RGM_HWA_ReadResetPinFilterEnable(void) +{ + return (uint32_t)RGM->RSTFLT; +} + +/** + * @brief This api can clear reset flag of SSRS register which indicate all reset sources since the last POR or LVD that have not been cleared by software. + * + * @param eReset Reset flag + */ +LOCAL_INLINE void RGM_HWA_ClearResetFlagAfterPOR(RGM_ResetEventType eReset) +{ + RGM->SSRS = (uint32_t)(eReset); +} + +/** + * @brief This api can clear all reset flag of SSRS register which indicate all reset sources since the last POR or LVD that have not been cleared by software. + * + */ +LOCAL_INLINE void RGM_HWA_ClearAllResetFlagAfterPOR(void) +{ + RGM->SSRS = (uint32_t)0xE000F9FFU; +} + +/** + * @brief Set reset pin filter bus clock filter width + * + * @param u8Value Bus clock filter width value + */ +LOCAL_INLINE void RGM_HWA_SetBusClockFilterWidth(uint8_t u8Value) +{ + uint32_t u32RegValue = RGM->RSTFLT; + RGM->RSTFLT = (u32RegValue & ~(uint32_t)RGM_RSTFLT_RSTFLT_BUSW_MASK) | RGM_RSTFLT_RSTFLT_BUSW(u8Value); +} + +/** + * @brief Enable reset pin filter bus clock + * + */ +LOCAL_INLINE void RGM_HWA_EnableBusClockFilter(void) +{ + RGM->RSTFLT |= (uint32_t)RGM_RSTFLT_RSTFLT_BUS_MASK; +} + +/** + * @brief Enable reset pin filter AON32K clock + * + */ +LOCAL_INLINE void RGM_HWA_EnableAon32kClockFilter(void) +{ + RGM->RSTFLT |= (uint32_t)RGM_RSTFLT_RSTFLT_AON_MASK; +} + +/** + * @brief Enable reset pin filter AON32K low power clock + * + */ +LOCAL_INLINE void RGM_HWA_EnableAon32kLPClockFilter(void) +{ + RGM->RSTFLT |= (uint32_t)RGM_RSTFLT_RSTFLT_AON_LP_MASK; +} + +/** + * @brief Clear reset pin filter bus clock filter width + * + */ +LOCAL_INLINE void RGM_HWA_ClearBusClockFilterWidth(void) +{ + RGM->RSTFLT &= ~(uint32_t)RGM_RSTFLT_RSTFLT_BUSW_MASK; +} + +/** + * @brief Disable reset pin filter bus clock + * + */ +LOCAL_INLINE void RGM_HWA_DisableBusClockFilter(void) +{ + RGM->RSTFLT &= ~(uint32_t)RGM_RSTFLT_RSTFLT_BUS_MASK; +} + +/** + * @brief Disable reset pin filter AON32K clock + * + */ +LOCAL_INLINE void RGM_HWA_DisableAon32kClockFilter(void) +{ + RGM->RSTFLT &= ~(uint32_t)RGM_RSTFLT_RSTFLT_AON_MASK; +} + +/** + * @brief Disable reset pin filter AON32K low power clock + * + */ +LOCAL_INLINE void RGM_HWA_DisableAon32kLPClockFilter(void) +{ + RGM->RSTFLT &= ~(uint32_t)RGM_RSTFLT_RSTFLT_AON_LP_MASK; +} + +/** + * @brief Set Reset delay + * + * @param eDelay Reset delay type + */ +LOCAL_INLINE void RGM_HWA_SetResetDelay(RGM_ResetDelayType eDelay) +{ + uint32_t u32RegValue = RGM->SRIE; + RGM->SRIE = (u32RegValue & ~(uint32_t)RGM_SRIE_DELAY_MASK) | RGM_SRIE_DELAY(eDelay); +} + +/** + * @brief Clear Reset delay + */ +LOCAL_INLINE void RGM_HWA_ClearResetDelay(void) +{ + RGM->SRIE &= ~(uint32_t)RGM_SRIE_DELAY_MASK; +} + +/** + * @brief Enable global reset interrupt + * + */ +LOCAL_INLINE void RGM_HWA_EnableGlobalResetInterrupt(void) +{ + RGM->SRIE |= (uint32_t)RGM_SRIE_GLOBAL_RIE_MASK; +} + +/** + * @brief Enable reset interrupt + * + * @param eResetInterrupt Reset interrupt type + */ +LOCAL_INLINE void RGM_HWA_EnableResetInterrupt(RGM_ResetIntMangerType eResetInterrupt) +{ + RGM->SRIE |= (uint32_t)((uint32_t)eResetInterrupt & (RGM_SRIE_CLKERR0_RIE_MASK | RGM_SRIE_WDG_RIE_MASK | + RGM_SRIE_PIN_RIE_MASK | RGM_SRIE_JTAG_RIE_MASK | RGM_SRIE_CPULOC_RIE_MASK | RGM_SRIE_SW_RIE_MASK | + RGM_SRIE_SYSAP_RIE_MASK | RGM_SRIE_WDOG1_RIE_MASK | RGM_SRIE_SACKERR_RIE_MASK)); +} + +/** + * @brief Disable reset interrupt + * + * @param eResetInterrupt Reset interrupt type + */ +LOCAL_INLINE void RGM_HWA_DisableResetInterrupt(RGM_ResetIntMangerType eResetInterrupt) +{ + RGM->SRIE &= ~(uint32_t)((uint32_t)eResetInterrupt & (RGM_SRIE_CLKERR0_RIE_MASK | RGM_SRIE_WDG_RIE_MASK | + RGM_SRIE_PIN_RIE_MASK | RGM_SRIE_JTAG_RIE_MASK | RGM_SRIE_CPULOC_RIE_MASK | RGM_SRIE_SW_RIE_MASK | + RGM_SRIE_SYSAP_RIE_MASK | RGM_SRIE_WDOG1_RIE_MASK | RGM_SRIE_SACKERR_RIE_MASK)); +} + +/** + * @brief Get enabling status of system reset + * + * @return Interrupt enabling status of system reset + */ +LOCAL_INLINE uint32_t RGM_HWA_GetResetInterrupt(void) +{ + return (uint32_t)(RGM->SRIE & (RGM_SRIE_CLKERR0_RIE_MASK | RGM_SRIE_WDG_RIE_MASK | + RGM_SRIE_PIN_RIE_MASK | RGM_SRIE_GLOBAL_RIE_MASK | RGM_SRIE_JTAG_RIE_MASK | RGM_SRIE_CPULOC_RIE_MASK | + RGM_SRIE_SW_RIE_MASK | RGM_SRIE_SYSAP_RIE_MASK | RGM_SRIE_WDOG1_RIE_MASK | RGM_SRIE_SACKERR_RIE_MASK)); +} + +/** + * @brief Perform system reset. + * + */ +LOCAL_INLINE void CM7_HWA_SystemReset(void) +{ + uint32 u32Temp; + u32Temp = SCB->AIRCR; + u32Temp &= ~(uint32)(SCB_AIRCR_VECTKEY_Msk); + u32Temp |= (uint32)((((uint32_t)(((uint32_t)(0x5FAU))<AIRCR = u32Temp; +} + +/** + * @brief Enable CPU0 interrupt + * + * @param eCPU0ResetInterrupt CPU0 related interrupt type + */ +LOCAL_INLINE void RGM_HWA_EnableCPU0InterruptFlag(RGM_CPUIntMangerType eCPU0ResetInterrupt) +{ + RGM->C0_CFG |= (uint32_t)((uint32_t)eCPU0ResetInterrupt & (RGM_C0_CFG_C0_SWRST_IE_MASK | RGM_C0_CFG_C0_INTM_IE_MASK | RGM_C0_CFG_C0_WDOG_IE_MASK | + RGM_C0_CFG_C0_SYSRST_IE_MASK | RGM_C0_CFG_C0_LOCKUP_IE_MASK)); +} + +/** + * @brief Disable CPU0 interrupt + * + * @param eCPU0ResetInterrupt CPU0 related interrupt type + */ +LOCAL_INLINE void RGM_HWA_DisableCPU0InterruptFlag(RGM_CPUIntMangerType eCPU0ResetInterrupt) +{ + RGM->C0_CFG &= ~(uint32_t)((uint32_t)eCPU0ResetInterrupt & (RGM_C0_CFG_C0_SWRST_IE_MASK | RGM_C0_CFG_C0_INTM_IE_MASK | RGM_C0_CFG_C0_WDOG_IE_MASK | + RGM_C0_CFG_C0_SYSRST_IE_MASK | RGM_C0_CFG_C0_LOCKUP_IE_MASK)); +} + +/** + * @brief Get enabling status of CPU0 core related reset + * + * @return Interrupt enabling status of CPU0 core related reset + */ +LOCAL_INLINE uint32_t RGM_HWA_GetCPU0ResetInterrupt(void) +{ + return (uint32_t)(RGM->C0_CFG & (RGM_C0_CFG_C0_SWRST_IE_MASK | RGM_C0_CFG_C0_INTM_IE_MASK | RGM_C0_CFG_C0_WDOG_IE_MASK | + RGM_C0_CFG_C0_SYSRST_IE_MASK | RGM_C0_CFG_C0_LOCKUP_IE_MASK)); +} + +/** + * @brief Get the CPU0 exit reset flag + * + * @return RGM_CPU_OUT_RST_UNDER CPU0 is under reset + * @return RGM_CPU_OUT_RST_OUT CPU0 is out of reset + */ +LOCAL_INLINE RGM_CPUOutResetType RGM_HWA_GetCPU0OutResetFlag(void) +{ + uint8_t u8TmpVal = (uint8_t)(RGM->C0_RST & RGM_C0_RST_C0_OUT_OF_RST_MASK) >> RGM_C0_RST_C0_OUT_OF_RST_SHIFT; + return (RGM_CPUOutResetType)u8TmpVal; +} + +/** + * @brief Issue a CPU0 software reset. + * + */ +LOCAL_INLINE void RGM_HWA_CPU0SWReset(void) +{ + RGM->C0_RST |= (uint32_t)RGM_C0_RST_C0_SWRST_MASK; +} + +/** + * @brief Read CPU0 last reset flag + * + * @return CPU0 last reset flag + */ +LOCAL_INLINE uint32_t RGM_HWA_ReadCPU0LastResetFlag(void) +{ + return (uint32_t)RGM->C0_SRS; +} + +/** + * @brief Read CPU0 all reset flag before POR,SSRS register is reset on POR only + * + * @return CPU0 all reset flag before POR + */ +LOCAL_INLINE uint32_t RGM_HWA_ReadCPU0AllResetFlagBeforePOR(void) +{ + return (uint32_t)RGM->C0_SSRS; +} + +/** + * @brief This api can clear reset flag of RGM_C0_SSRS register which indicate all reset sources since the last POR or LVD that have not been cleared by software. + * + * @param eReset Reset flag + */ +LOCAL_INLINE void RGM_HWA_ClearC0ResetFlagAfterPOR(RGM_CPUResetEventType eReset) +{ + RGM->C0_SSRS = (uint32_t)(eReset); +} + +/** + * @brief This api can clear all reset flag of SSRGM_C0_SSRSRS register which indicate all reset sources since the last POR or LVD that have not been cleared by software. + * + */ +LOCAL_INLINE void RGM_HWA_ClearC0AllResetFlagAfterPOR(void) +{ + RGM->C0_SSRS = (uint32_t)0xE01FF9FFU; +} +#endif /* #ifndef _HWA_RGM_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_rtc.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_rtc.h new file mode 100644 index 0000000..576f811 --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_rtc.h @@ -0,0 +1,276 @@ +/** + * @file HwA_rtc.h + * @author Flagchip + * @brief FC7xxx rtc hardware access layer + * @version 0.1.0 + * @date 2024-01-10 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-10 Flagchip0076 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef HWA_INCLUDE_HWA_RTC_H_ +#define HWA_INCLUDE_HWA_RTC_H_ + + +#include "device_header.h" + +/** + * @addtogroup HwA_RTC + * @{ + * + */ + +/********* Local typedef ************/ + +/** + * @brief in the second interrupt mode, this type indicates the interrupt frequency. + * in the clkout mode , this type indicates the clkout frequency . + * + * */ +typedef enum +{ + RTC_FREQ_1HZ = 0, /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 1Hz */ + RTC_FREQ_2HZ, /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 2Hz */ + RTC_FREQ_4HZ, /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 4Hz */ + RTC_FREQ_8HZ, /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 8Hz */ + RTC_FREQ_16HZ, /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 16Hz */ + RTC_FREQ_32hZ, /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 32Hz */ + RTC_FREQ_64HZ, /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 64Hz */ + RTC_FREQ_128HZ /*!< Set the RTC Seconds interrupt and the RTC_CLKOUT prescale output frequency to 128Hz */ +} RTC_ClkoutSecIntFreqType; +/********* Local inline function ************/ + +/** + * @brief Read second value + * + * @return Second value + */ +LOCAL_INLINE uint32_t RTC_HWA_ReadSecondValue(void) +{ + return (uint32_t)RTC->SR; +} + +/** + * @brief Read RTC SR overflow flag + * + * @return true means Overflow flag is 1 ;false means Overflow flag is 0. + */ +LOCAL_INLINE bool RTC_HWA_GetOverflowFlag(void) +{ + return (bool)(((RTC->STR & (uint32_t)RTC_STR_TOF_MASK)!=0u)? true:false); +} + +/** + * @brief Read RTC IER overflow enable bit + * + * @return true means enable Overflow Interrupt ;false means disable Overflow Interrupt + */ +LOCAL_INLINE bool RTC_HWA_GetOverflowEnable(void) +{ + return (bool)(((RTC->IER & (uint32_t)RTC_IER_TOIE_MASK)!=0u) ? true:false); +} + +/** + * @brief Read RTC alarm flag + * + * @return true means alarm flag is 1 ;false means alarm flag is 0. + */ +LOCAL_INLINE bool RTC_HWA_GetAlarmFlag(void) +{ + return (bool)(((RTC->STR & (uint32_t)RTC_STR_TAF_MASK)!=0u)?true:false); +} + +/** + * @brief Read RTC alarm Enable + * + * @return true means enable alarm Interrupt ;false means disable alarm Interrupt + */ +LOCAL_INLINE bool RTC_HWA_GetAlarmEnable(void) +{ + return (bool)(((RTC->IER & (uint32_t)RTC_IER_TAIE_MASK)!=0u)?true:false); +} + +/** + * @brief Read RTC second interrupt Enable + * + * @return true means enable second Interrupt ;false means disable second Interrupt + */ +LOCAL_INLINE bool RTC_HWA_GetSecondEnable(void) +{ + return (bool)(((RTC->IER & (uint32_t)RTC_IER_TSIE_MASK)!=0u)?true:false); +} + +/** + * @brief Set RTC prescaler register + * + * @param u16Value PR register value + */ +LOCAL_INLINE void RTC_HWA_SetPrescalerCounterValue(uint16_t u16Value) +{ + RTC->PR = (uint32_t)u16Value; +} + +/** + * @brief Set RTC seconds register + * + * @param u32Value SR register value + */ +LOCAL_INLINE void RTC_HWA_SetSecondCounterValue(uint32_t u32Value) +{ + RTC->SR = u32Value; +} + +/** + * @brief Set RTC alarm value + * + * @param u32Value TAR register value + */ +LOCAL_INLINE void RTC_HWA_SetAlarmCounterValue(uint32_t u32Value) +{ + RTC->AR = u32Value; +} + +/** + * @brief Set RTC interrupt value + * + * @param u32Value IER register value + */ +LOCAL_INLINE void RTC_HWA_SetInterruptValue(uint32_t u32Value) +{ + RTC->IER = u32Value; +} + +/** + * @brief Configure control register + * + * @param u32Value Control value + */ +LOCAL_INLINE void RTC_HWA_ConfigControl(uint32_t u32Value) +{ + RTC->CR = u32Value; +} + +/** + * @brief Enable RTC time counter + * + */ +LOCAL_INLINE void RTC_HWA_EnableRtcCounter(void) +{ + RTC->STR |= (uint32_t)RTC_STR_TCE_MASK; +} + +/** + * @brief Set RTC_CLKOUT is from the 32.768 khz clock + * + */ +LOCAL_INLINE void RTC_HWA_SetClkoutFreqStable(void) +{ + RTC->CR |= (uint32_t)RTC_CR_CKPS_MASK; +} + +/** + * @brief Enable alarm interrupt + * + */ +LOCAL_INLINE void RTC_HWA_EnableAlarmInterrupt(void) +{ + RTC->IER |= (uint32_t)RTC_IER_TAIE_MASK; +} + +/** + * @brief Enable second interrupt + * + */ +LOCAL_INLINE void RTC_HWA_EnableSecondInterrupt(void) +{ + RTC->IER |= (uint32_t)RTC_IER_TSIE_MASK; +} + +/** + * @brief Enable overflow interrupt + * + */ +LOCAL_INLINE void RTC_HWA_EnableOverflowInterrupt(void) +{ + RTC->IER |= (uint32_t)RTC_IER_TOIE_MASK; +} + +/** + * @brief Unlock lock/status/control/compensation register + * + */ +LOCAL_INLINE void RTC_HWA_UnlockStatusControlCompensationReg(void) +{ + RTC->LR |= (uint32_t)(RTC_LR_LRL_MASK | RTC_LR_STRL_MASK | RTC_LR_CRL_MASK | RTC_LR_CPL_MASK); +} + +/** + * @brief Set second interrupt and RTC_CLKOUT frequency + * + * @param eFreq Frequency value + */ +LOCAL_INLINE void RTC_HWA_SetSecondAndClkoutFreq(RTC_ClkoutSecIntFreqType eFreq) +{ + uint32_t u32RegValue = RTC->IER; + RTC->IER &= ~(uint32_t)RTC_IER_TSIE_MASK; + RTC->IER = (u32RegValue & ~(uint32_t)RTC_IER_TSIC_MASK) | RTC_IER_TSIC(eFreq); +} + +/** + * @brief Disable RTC time counter + * + */ +LOCAL_INLINE void RTC_HWA_DisableRtcCounter(void) +{ + RTC->STR &= ~(uint32_t)RTC_STR_TCE_MASK; +} + +/** + * @brief Set RTC_CLKOUT is from the prescaler output clock selected by IER[TSIC] + * + */ +LOCAL_INLINE void RTC_HWA_SetClkoutFromSelectFreq(void) +{ + RTC->CR &= ~(uint32_t)RTC_CR_CKPS_MASK; +} + +/** + * @brief Disable alarm interrupt + * + */ +LOCAL_INLINE void RTC_HWA_DisableAlarmInterrupt(void) +{ + RTC->IER &= ~(uint32_t)RTC_IER_TAIE_MASK; +} + +/** + * @brief Disable second interrupt + * + */ +LOCAL_INLINE void RTC_HWA_DisableSecondInterrupt(void) +{ + RTC->IER &= ~(uint32_t)RTC_IER_TSIE_MASK; +} + +/** + * @brief Disable overflow interrupt + * + */ +LOCAL_INLINE void RTC_HWA_DisableOverflowInterrupt(void) +{ + RTC->IER &= ~(uint32_t)RTC_IER_TOIE_MASK; +} + + + +/** @}*/ /* HwA_RTC */ +#endif /* HWA_INCLUDE_HWA_RTC_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_scg.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_scg.h new file mode 100644 index 0000000..efd3664 --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_scg.h @@ -0,0 +1,917 @@ +/** + * @file HwA_SCG.h + * @author Flagchip + * @brief FC7xxx SCG hardware access layer + * @version 0.1.0 + * @date 2023-01-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240 + ******************************************************************************** */ +#ifndef _HWA_SCG_H_ +#define _HWA_SCG_H_ + +#include "device_header.h" + +/** + * @addtogroup HwA_SCG + * @{ + * + */ +/********* macros ************/ +#define UNKNOWN_CLOCK 0xFFFFFFFFU + +#define SCG_CORE_CLOCK_SYMBOL CORE +#define SCG_BUS_CLOCK_SYMBOL BUS +#define SCG_SLOW_CLOCK_SYMBOL SLOW +#define SCG_SIRC_CLOCK_SYMBOL SIRC +#define SCG_SIRC32K_CLOCK_SYMBOL SIRC32K +#define SCG_FIRC_CLOCK_SYMBOL FIRC +#define SCG_FOSC_CLOCK_SYMBOL FOSC +#define SCG_SOSC_CLOCK_SYMBOL SOSC +#define SCG_PLL0_CLOCK_SYMBOL PLL0 +#define SCG_PLL1_CLOCK_SYMBOL PLL1 + +/* PLL related */ +#define SCG_PLLCSR_LK_MASK 0x800000u +#define SCG_PLLCSR_EN_MASK 0x1u +#define SCG_PLLCSR_CMRE_MASK 0x20000u +#define SCG_PLLCSR_CMRE_SHIFT 17u +#define SCG_PLLCSR_CMRE(x) (((uint32_t)(((uint32_t)(x))<_pll_##CSR = val +#define SCG_HWA_SetPllCsr(pll, val) _SCG_HWA_SetPllCsr(pll, val) + +#define _SCG_HWA_UnlockPllCsr(_pll_) SCG->_pll_##CSR &= ~(uint32_t)SCG_PLLCSR_LK_MASK +#define SCG_HWA_UnlockPllCsr(pll) _SCG_HWA_UnlockPllCsr(pll) + +#define _SCG_HWA_LockPllCsr(_pll_) SCG->_pll_##CSR |= (uint32_t)SCG_PLLCSR_LK_MASK +#define SCG_HWA_LockPllCsr(pll) _SCG_HWA_LockPllCsr(pll) + +#define _SCG_HWA_EnablePllClockMonitor(_pll_) SCG->_pll_##CSR |= (uint32_t)SCG_PLLCSR_CM_MASK +#define SCG_HWA_EnablePllClockMonitor(pll) _SCG_HWA_EnablePllClockMonitor(pll) + +#define _SCG_HWA_EnablePllClockMonitorReset(_pll_) SCG->_pll_##CSR |= (uint32_t)SCG_PLLCSR_CMRE_MASK +#define SCG_HWA_EnablePllClockMonitorReset(pll) _SCG_HWA_EnablePllClockMonitorReset(pll) + +#define _SCG_HWA_SetPllCfg(_pll_, val) SCG->_pll_##CFG = val +#define SCG_HWA_SetPllCfg(pll, val) _SCG_HWA_SetPllCfg(pll, val) + +#define _SCG_HWA_SetPllDiv(_pll_, val) SCG->_pll_##DIV = val +#define SCG_HWA_SetPllDiv(pll, val) _SCG_HWA_SetPllDiv(pll, val) + +#define _SCG_HWA_EnablePll(_pll_) SCG->_pll_##CSR |= (uint32_t)(SCG_PLLCSR_EN_MASK) +#define SCG_HWA_EnablePll(pll) _SCG_HWA_EnablePll(pll) + + + +#define _SCG_HWA_GetPllMult(_pll_) (uint32_t)(((uint32_t)(SCG->_pll_##CFG) & SCG_PLLCFG_MULT_MASK) >> SCG_PLLCFG_MULT_SHIFT) +#define SCG_HWA_GetPllMult(pll) _SCG_HWA_GetPllMult(pll) + +#define _SCG_HWA_GetPllPrediv(_pll_) (uint32_t)(((uint32_t)(SCG->_pll_##CFG) & SCG_PLLCFG_PREDIV_MASK) >> SCG_PLLCFG_PREDIV_SHIFT) +#define SCG_HWA_GetPllPrediv(pll) _SCG_HWA_GetPllPrediv(pll) + +#define _SCG_HWA_GetPllPstdiv(_pll_) (uint32_t)(((uint32_t)(SCG->_pll_##CFG) & SCG_PLLCFG_PSTDIV_MASK) >> SCG_PLLCFG_PSTDIV_SHIFT) +#define SCG_HWA_GetPllPstdiv(pll) _SCG_HWA_GetPllPstdiv(pll) + +#define _SCG_HWA_GetPllSrc(_pll_) (uint32_t)(((uint32_t)(SCG->_pll_##CFG) & SCG_PLLCFG_SOURCE_MASK) >> SCG_PLLCFG_SOURCE_SHIFT) +#define SCG_HWA_GetPllSrc(pll) _SCG_HWA_GetPllSrc(pll) + +/* Clock valid and div related */ +#define _SCG_HWA_GetClockVliad(_clock_) (bool)((((uint32_t)SCG->_clock_##CSR & (uint32_t)SCG_##_clock_##CSR_VLD_MASK) != 0U) ? true : false) +#define SCG_HWA_GetClockVliad(_clock_) _SCG_HWA_GetClockVliad(_clock_) + +#define _SCG_HWA_GetClockDiv(_clock_) (uint32_t)SCG->_clock_##DIV +#define SCG_HWA_GetClockDiv(_clock_) _SCG_HWA_GetClockDiv(_clock_) + +#define SCG_CLOCKDIV_DIVL_ACK_MASK 0x40000000u +#define SCG_CLOCKDIV_DIVM_ACK_MASK 0x20000000u +#define SCG_CLOCKDIV_DIVH_ACK_MASK 0x10000000u +#define SCG_CLOCKDIV_DIVL_ACK_SHIFT 30u +#define SCG_CLOCKDIV_DIVM_ACK_SHIFT 29u +#define SCG_CLOCKDIV_DIVH_ACK_SHIFT 28u + +#define SCG_CLOCKDIV_DIVL_EN_MASK 0x4000000u +#define SCG_CLOCKDIV_DIVM_EN_MASK 0x2000000u +#define SCG_CLOCKDIV_DIVH_EN_MASK 0x1000000u +#define SCG_CLOCKDIV_DIVL_EN_SHIFT 26u +#define SCG_CLOCKDIV_DIVM_EN_SHIFT 25u +#define SCG_CLOCKDIV_DIVH_EN_SHIFT 24u + +#define SCG_CLOCKDIV_EN2ACK_SHIFT 4u + +#define SCG_CLOCKDIV_DIVL_VAL_MASK 0x70000u +#define SCG_CLOCKDIV_DIVM_VAL_MASK 0x700u +#define SCG_CLOCKDIV_DIVH_VAL_MASK 0x7u +#define SCG_CLOCKDIV_DIVL_VAL_SHIFT 16u +#define SCG_CLOCKDIV_DIVM_VAL_SHIFT 8u +#define SCG_CLOCKDIV_DIVH_VAL_SHIFT 0u + +#define SCG_CHECK_DIVL_ACK(reg_val) ((reg_val & SCG_CLOCKDIV_DIVL_ACK_MASK) >> SCG_CLOCKDIV_DIVL_ACK_SHIFT) +#define SCG_CHECK_DIVM_ACK(reg_val) ((reg_val & SCG_CLOCKDIV_DIVM_ACK_MASK) >> SCG_CLOCKDIV_DIVM_ACK_SHIFT) +#define SCG_CHECK_DIVH_ACK(reg_val) ((reg_val & SCG_CLOCKDIV_DIVH_ACK_MASK) >> SCG_CLOCKDIV_DIVH_ACK_SHIFT) +#define SCG_CHECK_DIVL_EN(reg_val) ((reg_val & SCG_CLOCKDIV_DIVL_EN_MASK) >> SCG_CLOCKDIV_DIVL_EN_SHIFT) +#define SCG_CHECK_DIVM_EN(reg_val) ((reg_val & SCG_CLOCKDIV_DIVM_EN_MASK) >> SCG_CLOCKDIV_DIVM_EN_SHIFT) +#define SCG_CHECK_DIVH_EN(reg_val) ((reg_val & SCG_CLOCKDIV_DIVH_EN_MASK) >> SCG_CLOCKDIV_DIVH_EN_SHIFT) +#define SCG_GET_DIVL_VAL(reg_val) ((0U == ((reg_val & SCG_CLOCKDIV_DIVL_VAL_MASK) >> SCG_CLOCKDIV_DIVL_VAL_SHIFT)) ? 1U : ((reg_val & SCG_CLOCKDIV_DIVL_VAL_MASK) >> SCG_CLOCKDIV_DIVL_VAL_SHIFT)) +#define SCG_GET_DIVM_VAL(reg_val) ((0U == ((reg_val & SCG_CLOCKDIV_DIVM_VAL_MASK) >> SCG_CLOCKDIV_DIVM_VAL_SHIFT)) ? 1U : ((reg_val & SCG_CLOCKDIV_DIVM_VAL_MASK) >> SCG_CLOCKDIV_DIVM_VAL_SHIFT)) +#define SCG_GET_DIVH_VAL(reg_val) ((0U == ((reg_val & SCG_CLOCKDIV_DIVH_VAL_MASK) >> SCG_CLOCKDIV_DIVH_VAL_SHIFT)) ? 1U : ((reg_val & SCG_CLOCKDIV_DIVH_VAL_MASK) >> SCG_CLOCKDIV_DIVH_VAL_SHIFT)) +#define SCG_CALCULATE_DIVL_FREQ(clk_freq, reg_val) (((1U == SCG_CHECK_DIVL_EN(reg_val)) && (clk_freq != UNKNOWN_CLOCK)) ? (uint32_t)clk_freq >> (uint8_t)(SCG_GET_DIVL_VAL(reg_val) - 1U) : (uint32_t)UNKNOWN_CLOCK) +#define SCG_CALCULATE_DIVM_FREQ(clk_freq, reg_val) (((1U == SCG_CHECK_DIVM_EN(reg_val)) && (clk_freq != UNKNOWN_CLOCK)) ? (uint32_t)clk_freq >> (uint8_t)(SCG_GET_DIVM_VAL(reg_val) - 1U) : (uint32_t)UNKNOWN_CLOCK) +#define SCG_CALCULATE_DIVH_FREQ(clk_freq, reg_val) (((1U == SCG_CHECK_DIVH_EN(reg_val)) && (clk_freq != UNKNOWN_CLOCK)) ? (uint32_t)clk_freq >> (uint8_t)(SCG_GET_DIVH_VAL(reg_val) - 1U) : (uint32_t)UNKNOWN_CLOCK) + + +typedef enum +{ + SCG_CLOCK_DIV_H = 0x01000000U, /* DIVH clock enable bit [24] */ + SCG_CLOCK_DIV_M = 0x02000000U, /* DIVM clock enable bit [25] */ + SCG_CLOCK_DIV_L = 0x04000000U, /* DIVL clock enable bit [26] */ + SCG_CLOCK_DIV_ALL = 0x07000000U, /* DIVH DIVM DIVL clock enable bit [26:24] */ +}SCG_DivEnableType; + +/********* Local inline function ************/ + +/** + * @brief Get clock out configure register CLKOUTSEL value + */ +LOCAL_INLINE uint8_t SCG_HWA_GetClkOutSel(void) +{ + return (uint8_t)(((uint32_t)SCG->CLKOUTCFG & SCG_CLKOUTCFG_CLKOUTSEL_MASK) >> SCG_CLKOUTCFG_CLKOUTSEL_SHIFT); +} + +/** + * @brief Get clock out configure register value + */ +LOCAL_INLINE uint32_t SCG_HWA_GetClkOutCfg(void) +{ + return SCG->CLKOUTCFG; +} + +/** + * @brief Unlock SOSC CSR register + * + */ +LOCAL_INLINE void SCG_HWA_UnlockSoscCsrReg(void) +{ + SCG->SOSCCSR &= ~(uint32_t)(SCG_SOSCCSR_LK_MASK); +} + +/** + * @brief Lock SOSC CSR register + * + */ +LOCAL_INLINE void SCG_HWA_LockSoscCsrReg(void) +{ + SCG->SOSCCSR |= (uint32_t)(SCG_SOSCCSR_LK_MASK); +} + +/** + * @brief Enable SOSC clock monitor + * + */ +LOCAL_INLINE void SCG_HWA_EnableSoscClockMonitor(void) +{ + SCG->SOSCCSR |= (uint32_t)(SCG_SOSCCSR_CM_MASK); +} + +/** + * @brief Enable SOSC clock monitor Reset + * + */ +LOCAL_INLINE void SCG_HWA_EnableSoscClockMonitorReset(void) +{ + SCG->SOSCCSR |= (uint32_t)(SCG_SOSCCSR_CMRE_MASK); +} + +/** + * @brief Set SOSC enable + */ +LOCAL_INLINE void SCG_HWA_EnableSosc(void) +{ + SCG->SOSCCSR |= (uint32_t)SCG_SOSCCSR_EN_MASK; +} + +/** + * @brief Diable SOSC + */ +LOCAL_INLINE void SCG_HWA_DisableSosc(void) +{ + SCG->SOSCCSR &= ~(uint32_t)SCG_SOSCCSR_EN_MASK; +} + +/** + * @brief Set recommend value to SOSCCFG register + * + */ +LOCAL_INLINE void SCG_HWA_SetSoscRecommendCfg(void) +{ + SCG->SOSCCFG = (uint32_t)(SCG_SOSCCFG_EOCV(64U) | SCG_SOSCCFG_GM_SEL(3U) | SCG_SOSCCFG_CURPRG_SF(3U) | SCG_SOSCCFG_CURPRG_COMP(3U)); +} + +/** + * @brief Set SOSC CSR register value + * + * @param u32CsrValue configured register value + */ +LOCAL_INLINE void SCG_HWA_SetSoscCsr(uint32_t u32CsrValue) +{ + SCG->SOSCCSR = u32CsrValue; +} + +/** + * @brief Get SOSC CSR register value + * + */ +LOCAL_INLINE uint32_t SCG_HWA_GetSoscCsr(void) +{ + return (uint32_t)SCG->SOSCCSR; +} + +/********* Fosc Register interface ************/ +/** + * @brief Enable FOSC + */ +LOCAL_INLINE void SCG_HWA_EnableFosc(void) +{ + SCG->FOSCCSR |= (uint32_t)SCG_FOSCCSR_EN_MASK; +} + +/** + * @brief Disable FOSC + */ +LOCAL_INLINE void SCG_HWA_DisableFosc(void) +{ + SCG->FOSCCSR &= ~SCG_FOSCCSR_EN_MASK; +} + +/** + * @brief Set FOSCCFG register value + * + * @param u32CfgValue configured register value + */ +LOCAL_INLINE void SCG_HWA_SetFoscCfg(uint32_t u32CfgValue) +{ + SCG->FOSCCFG = u32CfgValue; +} + +/** + * @brief Set FOSCCSR register value + * + * @param u32CsrValue configured register value + */ +LOCAL_INLINE void SCG_HWA_SetFoscCsr(uint32_t u32CsrValue) +{ + SCG->FOSCCSR = u32CsrValue; +} + +/** + * @brief Get FOSCCSR register value + * + */ +LOCAL_INLINE uint32_t SCG_HWA_GetFoscCsr(void) +{ + return (uint32_t)SCG->FOSCCSR; +} + +/** + * @brief Unlock FOSC CSR register + * + */ +LOCAL_INLINE void SCG_HWA_UnlockFoscCsrReg(void) +{ + SCG->FOSCCSR &= ~(uint32_t)(SCG_FOSCCSR_LK_MASK); +} + +/** + * @brief lock FOSC CSR register + * + */ +LOCAL_INLINE void SCG_HWA_LockFoscCsrReg(void) +{ + SCG->FOSCCSR |= (uint32_t)(SCG_FOSCCSR_LK_MASK); +} + +/** + * @brief Enable FOSC clock monitor + * + */ +LOCAL_INLINE void SCG_HWA_EnableFoscClockMonitor(void) +{ + SCG->FOSCCSR |= (uint32_t)(SCG_FOSCCSR_CM_MASK); +} + +/** + * @brief Enable FOSC clock monitor Reset + * + */ +LOCAL_INLINE void SCG_HWA_EnableFoscClockMonitorReset(void) +{ + SCG->FOSCCSR |= (uint32_t)(SCG_FOSCCSR_CMRE_MASK); +} + +/** + * @brief enable FOSCDIV as user manual request sequence + * @param DivEn the or value of SCG_DivEnableType + */ +LOCAL_INLINE void SCG_HWA_EnableFoscDiv(SCG_DivEnableType DivEn) +{ + SCG->FOSCDIV |= (uint32_t)DivEn; +} + +/** + * @brief Disable FOSCDIV as user manual request sequence + * @param DivEn the or value of SCG_DivEnableType + */ +LOCAL_INLINE void SCG_HWA_DiableFoscDiv(SCG_DivEnableType DivEn) +{ + SCG->FOSCDIV &= ~(uint32_t)DivEn; +} + +/** + * @brief Get the acknowledgment of DIV clocks enabled by SCG_HWA_EnableFoscDiv + * @param DivEn the or value of SCG_DivEnableType + * @return bool true : The enabled DIV clocks are acknowledged + * false : The enabled DIV clocks are not acknowledged + */ +LOCAL_INLINE bool SCG_HWA_GetFoscDivAck(SCG_DivEnableType DivEn) +{ + return (bool)((SCG->FOSCDIV & (DivEn << SCG_CLOCKDIV_EN2ACK_SHIFT)) == (DivEn << SCG_CLOCKDIV_EN2ACK_SHIFT)); +} + +/** + * @brief Set FOSCDIV register value + * + * @param u32DivValue configured register value + */ +LOCAL_INLINE void SCG_HWA_SetFoscDiv(uint32_t u32DivValue) +{ + SCG->FOSCDIV = u32DivValue; +} + +/** + * @brief Set Low Power Wakeup WDOG Register + * + * @param u8MSBVal Most Significant value, if OSC is 40M + * and FOSC not valid after 1.8ms wakeup, + * the chip will reset and RGM register will + * report clock error reset reason. + */ +LOCAL_INLINE void SCG_HWA_SetWKPWDG(uint8_t u8MSBVal) +{ + SCG->WKPWDG = SCG_WKPWDG_MSB(u8MSBVal) | SCG_WKPWDG_EN_MASK; +} + + + +/********* Sirc Register interface ************/ +/** + * @brief Set SIRCCSR register value + * + * @param u32CsrValue configured register value + */ +LOCAL_INLINE void SCG_HWA_SetSircCsr(uint32_t u32CsrValue) +{ + SCG->SIRCCSR = u32CsrValue; +} + +/** + * @brief Get SIRCCSR register value + * + */ +LOCAL_INLINE uint32_t SCG_HWA_GetSircCsr(void) +{ + return (uint32_t)SCG->SIRCCSR; +} + +/** + * @brief Unlock SIRC CSR register + * + */ +LOCAL_INLINE void SCG_HWA_UnlockSircCsrReg(void) +{ + SCG->SIRCCSR &= ~(uint32_t)SCG_SIRCCSR_LK_MASK; +} + +/** + * @brief Lock SIRC CSR register + * + */ +LOCAL_INLINE void SCG_HWA_LockSircCsrReg(void) +{ + SCG->SIRCCSR |= (uint32_t)SCG_SIRCCSR_LK_MASK; +} + +/** + * @brief Enable SIRC clock monitor + * + */ +LOCAL_INLINE void SCG_HWA_EnableSircClockMonitor(void) +{ + SCG->SIRCCSR |= (uint32_t)(SCG_SIRCCSR_CM_MASK); +} + +/** + * @brief Set SIRCDIV register value + * + * @param u32DivValue configured register value + */ +LOCAL_INLINE void SCG_HWA_SetSircDiv(uint32_t u32DivValue) +{ + SCG->SIRCDIV = u32DivValue; +} + +/** + * @brief enable SIRCDIV as user manual request sequence + * @param DivEn the or value of SCG_DivEnableType + */ +LOCAL_INLINE void SCG_HWA_EnableSircDiv(SCG_DivEnableType DivEn) +{ + SCG->SIRCDIV |= (uint32_t)DivEn; +} + +/** + * @brief Disable SIRCDIV as user manual request sequence + * @param DivEn the or value of SCG_DivEnableType + */ +LOCAL_INLINE void SCG_HWA_DiableSircDiv(SCG_DivEnableType DivEn) +{ + SCG->SIRCDIV &= ~(uint32_t)DivEn; +} + +/** + * @brief Get the acknowledgment of DIV clocks enabled by SCG_HWA_EnableSircDiv + * @param DivEn the or value of SCG_DivEnableType + * @return bool true : The enabled DIV clocks are acknowledged + * false : The enabled DIV clocks are not acknowledged + */ +LOCAL_INLINE bool SCG_HWA_GetSircDivAck(SCG_DivEnableType DivEn) +{ + return (bool)((SCG->SIRCDIV & (DivEn << SCG_CLOCKDIV_EN2ACK_SHIFT)) == (DivEn << SCG_CLOCKDIV_EN2ACK_SHIFT)); +} + +/** + * @brief Set SIRCTCFG register value for SIRC Trim configure. + * + * @param u32TcfgValue configured register value + */ +LOCAL_INLINE void SCG_HWA_SetSircTcfg(uint32_t u32TcfgValue) +{ + SCG->SIRCTCFG = u32TcfgValue; +} + +/********* Sirc32k Register interface ************/ +/** + * @brief Enable SIRC32KCSR register + * + */ +LOCAL_INLINE void SCG_HWA_EnableSirc32kCsr(void) +{ + SCG->SIRC32KCSR |= (uint32_t)SCG_SIRC32KCSR_EN_MASK; +} + +/** + * @brief Disable SIRC32KCSR register + * + */ +LOCAL_INLINE void SCG_HWA_DisableSirc32kCsr(void) +{ + SCG->SIRC32KCSR &= ~(uint32_t)SCG_SIRC32KCSR_EN_MASK; +} + +/** + * @brief Unlock SIRC32K CSR register + */ +LOCAL_INLINE void SCG_HWA_UnlockSirc32kCsrReg(void) +{ + SCG->SIRC32KCSR &= ~(uint32_t)(SCG_SIRC32KCSR_LK_MASK); +} + +/** + * @brief Lock SIRC32K CSR register + */ +LOCAL_INLINE void SCG_HWA_LockSirc32kCsrReg(void) +{ + SCG->SIRC32KCSR |= (uint32_t)(SCG_SIRC32KCSR_LK_MASK); +} + +/********* Firc Register interface ************/ +/** + * @brief Get FIRC CSR register value. + */ +LOCAL_INLINE uint32_t SCG_HWA_GetFircCsr(void) +{ + return (uint32_t)SCG->FIRCCSR; +} + +/** + * @brief Enable FIRC. + */ +LOCAL_INLINE void SCG_HWA_EnableFirc(void) +{ + SCG->FIRCCSR |= (uint32_t)SCG_FIRCCSR_EN_MASK; +} + +/** + * @brief Unlock FIRC CSR register + */ +LOCAL_INLINE void SCG_HWA_UnlockFircCsrReg(void) +{ + SCG->FIRCCSR &= ~(uint32_t)(SCG_FIRCCSR_LK_MASK); +} + +/** + * @brief Lock FIRC CSR register + */ +LOCAL_INLINE void SCG_HWA_LockFircCsrReg(void) +{ + SCG->FIRCCSR |= (uint32_t)(SCG_FIRCCSR_LK_MASK); +} + +/** + * @brief Enable FIRC clock monitor + * + */ +LOCAL_INLINE void SCG_HWA_EnableFircClockMonitor(void) +{ + SCG->FIRCCSR |= (uint32_t)(SCG_FIRCCSR_CM_MASK); +} + +/** + * @brief Disable FIRC. + */ +LOCAL_INLINE void SCG_HWA_DisableFirc(void) +{ + SCG->FIRCCSR &= ~(uint32_t)SCG_FIRCCSR_EN_MASK; +} + +/** + * @brief Set FIRCCSR register value + * + * @param u32CsrValue configured register value + */ +LOCAL_INLINE void SCG_HWA_SetFircCsr(uint32_t u32CsrValue) +{ + SCG->FIRCCSR = u32CsrValue; +} + +/** + * @brief Set FIRCCFG register value + * + * @param u32CfgValue configured register value + */ +LOCAL_INLINE void SCG_HWA_SetFircCfg(uint32_t u32CfgValue) +{ + SCG->FIRCCFG = u32CfgValue; +} + +/** + * @brief Set FOSCDIV register value + * + * @param u32DivValue configured register value + */ +LOCAL_INLINE void SCG_HWA_SetFircDiv(uint32_t u32DivValue) +{ + SCG->FIRCDIV = u32DivValue; +} + +/** + * @brief enable FIRCDIV as user manual request sequence + * @param DivEn the or value of SCG_DivEnableType + */ +LOCAL_INLINE void SCG_HWA_EnableFircDiv(SCG_DivEnableType DivEn) +{ + SCG->FIRCDIV |= (uint32_t)DivEn; +} + +/** + * @brief Disable FIRCDIV as user manual request sequence + * @param DivEn the or value of SCG_DivEnableType + */ +LOCAL_INLINE void SCG_HWA_DiableFircDiv(SCG_DivEnableType DivEn) +{ + SCG->FIRCDIV &= ~(uint32_t)DivEn; +} + +/** + * @brief Get the acknowledgment of DIV clocks enabled by SCG_HWA_EnableFircDiv + * @param DivEn the or value of SCG_DivEnableType + * @return bool true : The enabled DIV clocks are acknowledged + * false : The enabled DIV clocks are not acknowledged + */ +LOCAL_INLINE bool SCG_HWA_GetFircDivAck(SCG_DivEnableType DivEn) +{ + return (bool)((SCG->FIRCDIV & (DivEn << SCG_CLOCKDIV_EN2ACK_SHIFT)) == (DivEn << SCG_CLOCKDIV_EN2ACK_SHIFT)); +} + +/** + * @brief Set FIRCTCFG register value for FIRC clock trim configure. + * + * @param u32TcfgValue configured register value. + */ +LOCAL_INLINE void SCG_HWA_SetFircTcfg(uint32_t u32TcfgValue) +{ + SCG->FIRCTCFG = u32TcfgValue; +} + + +/********* PLL0 clock Register interface ************/ +/** + * @brief enable PLL0DIV as user manual request sequence + * @param DivEn the or value of SCG_DivEnableType + */ +LOCAL_INLINE void SCG_HWA_EnablePll0Div(SCG_DivEnableType DivEn) +{ + SCG->PLL0DIV |= (uint32_t)DivEn; +} + +/** + * @brief Disable FOSCDIV as user manual request sequence + * @param DivEn the or value of SCG_DivEnableType + */ +LOCAL_INLINE void SCG_HWA_DiablePll0Div(SCG_DivEnableType DivEn) +{ + SCG->PLL0DIV &= ~(uint32_t)DivEn; +} + +/** + * @brief Get the acknowledgment of DIV clocks enabled by SCG_HWA_EnablePll0Div + * @param DivEn the or value of SCG_DivEnableType + * @return bool true : The enabled DIV clocks are acknowledged + * false : The enabled DIV clocks are not acknowledged + */ +LOCAL_INLINE bool SCG_HWA_GetPll0DivAck(SCG_DivEnableType DivEn) +{ + return (bool)((SCG->PLL0DIV & (DivEn << SCG_CLOCKDIV_EN2ACK_SHIFT)) == (DivEn << SCG_CLOCKDIV_EN2ACK_SHIFT)); +} + + +/********* PLL1 clock Register interface ************/ +/** + * @brief enable PLL0DIV as user manual request sequence + * @param DivEn the or value of SCG_DivEnableType + */ +LOCAL_INLINE void SCG_HWA_EnablePll1Div(SCG_DivEnableType DivEn) +{ + SCG->PLL1DIV |= (uint32_t)DivEn; +} + +/** + * @brief Disable FOSCDIV as user manual request sequence + * @param DivEn the or value of SCG_DivEnableType + */ +LOCAL_INLINE void SCG_HWA_DiablePll1Div(SCG_DivEnableType DivEn) +{ + SCG->PLL1DIV &= ~(uint32_t)DivEn; +} + +/** + * @brief Get the acknowledgment of DIV clocks enabled by SCG_HWA_EnablePll1Div + * @param DivEn the or value of SCG_DivEnableType + * @return bool true : The enabled DIV clocks are acknowledged + * false : The enabled DIV clocks are not acknowledged + */ +LOCAL_INLINE bool SCG_HWA_GetPll1DivAck(SCG_DivEnableType DivEn) +{ + return (bool)((SCG->PLL1DIV & (DivEn << SCG_CLOCKDIV_EN2ACK_SHIFT)) == (DivEn << SCG_CLOCKDIV_EN2ACK_SHIFT)); +} + +/********* System clock Register interface ************/ +/** + * @brief Get system clock CCR register value + * + * @return system clock CCR register value + */ +LOCAL_INLINE uint32_t SCG_HWA_GetCCR(void) +{ + return SCG->CCR; +} + +/** + * @brief Set system clock CCR register value + * + * @param u32CcrValue configured register value + */ +LOCAL_INLINE void SCG_HWA_SetCCR(uint32_t u32CcrValue) +{ + SCG->CCR = u32CcrValue; +} + +/** + * @brief Set system clock + * + * @param u8SystemCLock System clock value + */ +LOCAL_INLINE void SCG_HWA_SetSystemClock(uint8_t u8SystemCLock) +{ + SCG->CCR = ((SCG->CCR & ~(uint32_t)SCG_CCR_SCS_MASK) | SCG_CCR_SCS(u8SystemCLock)); +} + +/** + * @brief Get system clock source. used to calculate system clock frequency at startup. + * used to check if the target clock soure successfully switched. + * @return uint8_t. system clock source. + */ +LOCAL_INLINE uint8_t SCG_HWA_GetSysClkSrc(void) +{ + return (uint8_t)(((uint32_t)(SCG->CSR) & (uint32_t)SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT); +} + +/** + * @brief Get system clock valid status, use this status to check system clock update finished or not. + * @return bool. true as updated; false as not updated. + */ +LOCAL_INLINE bool SCG_HWA_GetSysClkUPRD(void) +{ + return (bool)((((uint32_t)SCG->CSR & (uint32_t)SCG_CSR_CCR_UPRD_MASK) != 0U) ? true : false); +} + +/** + * @brief Get system clock Divcore. used to calculate core clock frequency at startup. + * @return uint8_t. system clock Divcore. + */ +LOCAL_INLINE uint8_t SCG_HWA_GetSysClkDivCore(void) +{ + return (uint8_t)(((uint32_t)(SCG->CSR) & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT); +} + +/** + * @brief Get system clock Divbus. used to calculate bus clock frequency at startup. + * @return uint8_t. system clock Divbus. + */ +LOCAL_INLINE uint8_t SCG_HWA_GetSysClkDivBus(void) +{ + return (uint8_t)(((uint32_t)(SCG->CSR) & SCG_CSR_DIVBUS_MASK) >> SCG_CSR_DIVBUS_SHIFT); +} + +/** + * @brief Get system clock Divslow. used to calculate slow clock frequency at startup. + * @return uint8_t. system clock Divslow. + */ +LOCAL_INLINE uint8_t SCG_HWA_GetSysClkDivSlow(void) +{ + return (uint8_t)(((uint32_t)(SCG->CSR) & SCG_CSR_DIVSLOW_MASK) >> SCG_CSR_DIVSLOW_SHIFT); +} + +/********* Clkout Register interface ************/ +/** + * @brief Select clock out source + * + * @param u8ClkOutSel Clock out select + */ +LOCAL_INLINE void SCG_HWA_SetClkOutSel(uint8_t u8ClkOutSel) +{ + SCG->CLKOUTCFG = ((SCG->CLKOUTCFG & ~(uint32_t)SCG_CLKOUTCFG_CLKOUTSEL_MASK) | SCG_CLKOUTCFG_CLKOUTSEL(u8ClkOutSel)); +} + +/** + * @brief Set Nvm clock source + * + * @param u32NvmClkMask Nvm clock source mask + */ +LOCAL_INLINE void SCG_HWA_SetNvmClk(uint32_t u32NvmClkMask) +{ + SCG->CLKOUTCFG &= ~(uint32_t)(SCG_CLKOUTCFG_NVMCLK_FIRC_MASK | SCG_CLKOUTCFG_NVMCLK_SIRC_MASK); + SCG->CLKOUTCFG |= u32NvmClkMask; +} + +/** + * @brief Set CMU4 clock source + * + * @param u32Cmu4ClkMask CMU4 clock source mask + */ +LOCAL_INLINE void SCG_HWA_SetCmu4Clk(uint32_t u32Cmu4ClkMask) +{ + SCG->CLKOUTCFG &= ~(uint32_t)(SCG_CLKOUTCFG_CMU4CLK_FOSC_MASK | SCG_CLKOUTCFG_CMU4CLK_SIRC_MASK); + SCG->CLKOUTCFG |= u32Cmu4ClkMask; +} + +/********* CRC Register interface ************/ +/** + * @brief Generate SCG register CRC value + */ +LOCAL_INLINE void SCG_HWA_GenCrcVal(void) +{ + SCG->CRCCSR |= (uint32_t)SCG_CRCCSR_GEN_MASK; +} + +/** + * @brief Enable SCG register CRC check + */ +LOCAL_INLINE void SCG_HWA_EnableCrcCheck(void) +{ + SCG->CRCCSR |= (uint32_t)SCG_CRCCSR_CHKEN_MASK; +} + +/** + * @brief Disable SCG register CRC check + */ +LOCAL_INLINE void SCG_HWA_DisableCrcCheck(void) +{ + SCG->CRCCSR &= ~(uint32_t)SCG_CRCCSR_CHKEN_MASK; +} + +/** + * @brief Enable SCG register CRC error output + */ +LOCAL_INLINE void SCG_HWA_EnableCrcErrorOutput(void) +{ + SCG->CRCCSR |= (uint32_t)SCG_CRCCSR_EOEN_MASK; +} + +/** + * @brief Disable SCG register CRC error output + */ +LOCAL_INLINE void SCG_HWA_DisableCrcErrorOutput(void) +{ + SCG->CRCCSR &= ~(uint32_t)SCG_CRCCSR_EOEN_MASK; +} + +/** + * @brief Get CRC busy status + */ +LOCAL_INLINE bool SCG_HWA_GetCrcBusyStatus(void) +{ + return (0U != (SCG->CRCCSR & (uint32_t)SCG_CRCCSR_BUSY_MASK)); +} + +/** + * @brief Get CRC error status + */ +LOCAL_INLINE bool SCG_HWA_GetCrcErrorStatus(void) +{ + return (0U != (SCG->CRCCSR & (uint32_t)SCG_CRCCSR_ERR_MASK)); +} + +/** + * @brief Clear CRC error flag + */ +LOCAL_INLINE void SCG_HWA_ClearCrcErrorFlag(void) +{ + SCG->CRCCSR |= (uint32_t)SCG_CRCCSR_ERR_MASK; +} + +/** + * @brief Get CRC result + */ +LOCAL_INLINE uint32_t SCG_HWA_GetCrcResult(void) +{ + return SCG->CRCRES; +} + +/** + * @brief Enable SCG register CRC trigger mode + */ +LOCAL_INLINE void SCG_HWA_EnableCrcTriggerMode(void) +{ + SCG->CRCCSR |= (uint32_t)SCG_CRCCSR_TRGEN_MASK; +} + +/** + * @brief Disable SCG register CRC trigger mode + */ +LOCAL_INLINE void SCG_HWA_DisableCrcTriggerMode(void) +{ + SCG->CRCCSR &= ~(uint32_t)SCG_CRCCSR_TRGEN_MASK; +} + +/** @}*/ /* HwA_SCG */ + +#endif /* #ifndef _HWA_SCG_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_scm.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_scm.h new file mode 100644 index 0000000..40e5e72 --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_scm.h @@ -0,0 +1,2388 @@ +/** + * @file HwA_scm.h + * @author Flagchip085 + * @brief Hardware access layer for SCM + * @version 0.1.0 + * @date 2024-01-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef _HWA_SCM_H_ +#define _HWA_SCM_H_ +#include "device_header.h" + +/********* Local typedef ************/ + +/** + * @brief WPB cpu type + * + */ +typedef enum +{ + SCM_WP_CPU_ALL = 0U, /*!< All CPUs are allowed to write this peripheral */ + SCM_WP_CPU_0 = 1U, /*!< Only CPU0 is allowed to control this peripheral */ + SCM_WP_CPU_NONE /*!< No CPU is allowed to control this peripheral */ +} SCM_WPB_CpuType; + +/** + * @brief ECC Enable mode Control type + * + */ +typedef enum +{ + SCM_ECC_WRITE_EN_READ_DIS = 2U, /*!< ECC Generate Enable During Write, ECC Check Disable During Read */ + SCM_ECC_WRITE_EN_READ_EN = 3U /*!< ECC Generate Enable During Write, ECC Check Enable During Read */ +} SCM_EccEnModeType; + +/** + * @brief MAMECCEN0 MAM ECC Enable group 0 type + * + */ +typedef enum +{ + SCM_MAM0_S0_ECC = 0U, /*!< MAM0 S0 ROM Array ECC Enable Control */ + SCM_MAM0_S1_ECC = 1U, /*!< MAM0 S1 PFlash Slave ECC Enable Control */ + SCM_MAM0_S2_ECC = 3U, /*!< MAM0 S2 DFlash Slave ECC Enable Control */ + SCM_MAM0_S3_ECC = 4U, /*!< MAM0 S3 SRAM0 Slave ECC Enable Control */ + SCM_MAM0_S4_ECC = 5U, /*!< MAM0 S4 SRAM1 Slave ECC Enable Control */ + SCM_MAM0_S5_ECC = 7U, /*!< MAM0 S5 TCM Slave ECC Enable Control */ + SCM_MAM0_S6_ECC = 8U, /*!< MAM0 S6 AFCB0 Slave ECC Enable Control */ + SCM_MAM0_S7_ECC = 9U, /*!< MAM0 S7 AFCB1 Slave ECC Enable Control */ + SCM_MAM0_S8_ECC = 10U, /*!< MAM0 S8 GPIO Slave ECC Enable Control */ + SCM_SRAM0_ECC = 11U, /*!< SRAM0 Array ECC Enable Control */ + SCM_SRAM1_ECC = 12U /*!< SRAM1 Array ECC Enable Control */ +} SCM_MAMEccCtrlGrp0Type; + +/** + * @brief MAMECCEN1 MAM ECC Enable group 1 type + * + */ +typedef enum +{ + SCM_HSM_ECC = 0U, /*!< HSM Master ECC Enable Control */ + SCM_DMA0_ECC = 2U, /*!< DMA0 Master ECC Enable Control */ + SCM_DMA0_CFG_ECC = 4U, /*!< DMA0 CFG Memory ECC Enable Control */ + SCM_HSM_DRAM_ECC = 5U, /*!< HSM DRAM Memory ECC Enable Control */ + SCM_HSM_IRAM_ECC = 6U /*!< HSM IRAM Memory ECC Enable Control */ +} SCM_MAMEccCtrlGrp1Type; + +/** + * @brief CPU0 ECC Enable Register type + * + */ +typedef enum +{ + SCM_CPUXECCEN_CPUX_AHBM_ECC = 0U, /*!< SCM_CPUXECCEN_CPUX_AHBM_ECC peripheral */ + SCM_CPUXECCEN_CPUX_AHBP_ECC = 1U, /*!< SCM_CPUXECCEN_CPUX_AHBP_ECC peripheral */ + SCM_CPUXECCEN_CPUX_AHBS_ECC = 2U, /*!< SCM_CPUXECCEN_CPUX_AHBS_ECC peripheral */ + SCM_CPUXECCEN_CPUX_DTCM0_ECC = 3U, /*!< SCM_CPUXECCEN_CPUX_DTCM0_ECC peripheral */ + SCM_CPUXECCEN_CPUX_DTCM1_ECC = 4U, /*!< SCM_CPUXECCEN_CPUX_DTCM1_ECC peripheral */ + SCM_CPUXECCEN_CPUX_ITCM_ECC = 5U /*!< SCM_CPUXECCEN_CPUX_ITCM_ECC peripheral */ +} SCM_CPUEccCtrlType; + +/** + * @brief FCSPI monitor type + * + */ +typedef enum +{ + SCM_MON_FCSPI0 = 0U, /*!< Monitor FCSPI0's transmit interface */ + SCM_MON_FCSPI1, /*!< Monitor FCSPI1's transmit interface */ + SCM_MON_FCSPI2, /*!< Monitor FCSPI2's transmit interface */ + SCM_MON_FCSPI3, /*!< Monitor FCSPI3's transmit interface */ + SCM_MON_FCSPI4, /*!< Monitor FCSPI4's transmit interface */ + SCM_MON_FCSPI5 /*!< Monitor FCSPI5's transmit interface */ +} SCM_FCSPIxType; + +/** + * @brief FCUART monitor type + * + */ +typedef enum +{ + SCM_MON_FCUART0 = 0U, /*!< Monitor FCUART0's transmit interface */ + SCM_MON_FCUART1, /*!< Monitor FCUART1's transmit interface */ + SCM_MON_FCUART2, /*!< Monitor FCUART2's transmit interface */ + SCM_MON_FCUART3, /*!< Monitor FCUART3's transmit interface */ + SCM_MON_FCUART4, /*!< Monitor FCUART4's transmit interface */ + SCM_MON_FCUART5, /*!< Monitor FCUART5's transmit interface */ + SCM_MON_FCUART6, /*!< Monitor FCUART6's transmit interface */ + SCM_MON_FCUART7 /*!< Monitor FCUART7's transmit interface */ +} SCM_MON_FCUARTxType; + +/** + * @brief PTIMER Loop Mode Select type + * + */ +typedef enum +{ + SCM_LM_PTMR0CH0_PTMR1CH0 = 0U,/*!< PTIMER0 CH0 loop, PTIMER1 CH0 loop */ + SCM_LM_PTMR1CH0_CH1 = 1U,/*!< PTIMER1 CH0 and CH1 in loop mode */ + SCM_LM_PTMR0CH0_CH1 = 2U,/*!< PTIMER0 CH0 and CH1 in loop mode */ + SCM_LM_PTMR0CH0CH1_PTMR1CH0CH1 = 3U,/*!< PTIMER1 CH0 and CH1 in loop mode, PTIMER0 CH0 and CH1 in loop mode */ + SCM_LM_PTMR0_PTMR1_CH0 = 4U /*!< PTIMER0 CH0 and PTIMER1 CH0 in loop mode */ +} SCM_PTimerLMSelType; + +/** + * @brief ADC Trigger Source type + * + */ +typedef enum +{ + SCM_ADC_TRIGGER_SRC_PTIMER = 0U, /*!< ADC Trigger Source PTIMER output */ + SCM_ADC_TRIGGER_SRC_TRGSEL = 1U /*!< ADC Trigger Source TRGSEL output */ +} SCM_AdcTriggerSrcType; + +/** + * @brief ADC PreTrigger Source type + * + */ +typedef enum +{ + SCM_ADC_PRETRIGGER_PTIMER = 0U, /*!< ADC Pre-trigger PTIMER */ + SCM_ADC_PRETRIGGER_SCMSOFTWARE = 2U /*!< ADC Pre-trigger SCM software */ +} SCM_AdcPreTriggerSrcType; + +/** + * @brief ADC SCM software Pre-trigger Sources type + * + */ +typedef enum +{ + SCM_SOFTWARE_PRETRIGGER_DISABLED = 0U, /*!< SCM Software pre-trigger disabled */ + SCM_SOFTWARE_PRETRIGGER_0 = 4U, /*!< SCM Software pre-trigger 0 */ + SCM_SOFTWARE_PRETRIGGER_1 = 5U, /*!< SCM Software pre-trigger 1 */ + SCM_SOFTWARE_PRETRIGGER_2 = 6U, /*!< SCM Software pre-trigger 2 */ + SCM_SOFTWARE_PRETRIGGER_3 = 7U /*!< SCM Software pre-trigger 3 */ +} SCM_SoftwarePreTriggerType; + +/** + * @brief FTUx output source selection type + * + */ +typedef enum +{ + SCM_FTU_OUTPUT_STD = 0U, /*!< FTUx CHx output will direct route to corresponding pad(standard) */ + SCM_FTU_OUT_COMBINE /*!< FTUx pad output is equal to FTUx CHx output & FTUx CH1 output(combine) */ +} SCM_FTU_OutputSelType; + +/** + * @brief FTU2 CH1 input selection type + * + */ +typedef enum +{ + SCM_FTU_INPUT_STD = 0U, /*!< FTU2_CH1 input */ + SCM_FTU_INPUT_OR /*!< OR of FTU2_CH0,FTU2_CH1,and FTU1_CH1 */ +} SCM_FTU2_CH1_InputSelType; + +/** + * @brief FTUx CH0 input selection type + * + */ +typedef enum +{ + SCM_FTU_CH0_INPUT_STD = 0U, /*!< FTU2_CH0 input */ + SCM_FTU_CH0_INPUT_CMP0, /*!< CMP0 output */ + SCM_FTU_CH0_INPUT_CMP1 /*!< CMP1 output */ +} SCM_FTUx_CH0_InputSelType; + +/** + * @brief FTU Global Time Base Control type + * + */ +typedef enum +{ + SCM_FTU0_GTBC = 0x01U, /*!< FTU0 Global Time Base Control Select */ + SCM_FTU1_GTBC = 0x02U, /*!< FTU1 Global Time Base Control Select */ + SCM_FTU2_GTBC = 0x04U, /*!< FTU2 Global Time Base Control Select */ + SCM_FTU3_GTBC = 0x08U, /*!< FTU3 Global Time Base Control Select */ + SCM_FTU4_GTBC = 0x10U, /*!< FTU4 Global Time Base Control Select */ + SCM_FTU5_GTBC = 0x20U, /*!< FTU5 Global Time Base Control Select */ + SCM_FTU6_GTBC = 0x40U, /*!< FTU6 Global Time Base Control Select */ + SCM_FTU7_GTBC = 0x80U, /*!< FTU7 Global Time Base Control Select */ +} SCM_FTUGTBCtrlType; + +/** + * @brief FTU SYNC Control type + * + */ +typedef enum +{ + SCM_FTU0_SYNC = SCM_FTU_SYNC_FTU0SYNC_MASK, /*!< FTU0 Sync Control */ + SCM_FTU1_SYNC = SCM_FTU_SYNC_FTU1SYNC_MASK, /*!< FTU1 Sync Control */ + SCM_FTU2_SYNC = SCM_FTU_SYNC_FTU2SYNC_MASK, /*!< FTU2 Sync Control */ + SCM_FTU3_SYNC = SCM_FTU_SYNC_FTU3SYNC_MASK, /*!< FTU3 Sync Control */ + SCM_FTU4_SYNC = SCM_FTU_SYNC_FTU4SYNC_MASK, /*!< FTU4 Sync Control */ + SCM_FTU5_SYNC = SCM_FTU_SYNC_FTU5SYNC_MASK, /*!< FTU5 Sync Control */ + SCM_FTU6_SYNC = SCM_FTU_SYNC_FTU6SYNC_MASK, /*!< FTU6 Sync Control */ + SCM_FTU7_SYNC = SCM_FTU_SYNC_FTU7SYNC_MASK, /*!< FTU7 Sync Control */ +} SCM_FTUSyncCtrlType; + +/** + * @brief Trace clock selection + * + */ +typedef enum +{ + SCM_TRACE_CORE_CLK = 0U, /*!< Select platform fclk to trace clock */ + SCM_TRACE_PLL1DIVH_CLK = 1U /*!< Select SCG PLL1 platform clock to trace clock */ +} SCM_TraceClkSrcType; + +/** + * @brief Software trigger to TRGSEL0/TRGSEL1 + * + */ +typedef enum +{ + SCM_SW_TRIG_0 = 1U, /*!< Generate software trigger0 to (TRGSEL0 & TRGSEL4) */ + SCM_SW_TRIG_1 = 2U, /*!< Generate software trigger1 to (TRGSEL0 & TRGSEL4) */ + SCM_SW_TRIG_2 = 4U, /*!< Generate software trigger2 to (TRGSEL0 & TRGSEL4) */ + SCM_SW_TRIG_3 = 8U, /*!< Generate software trigger3 to (TRGSEL0 & TRGSEL4) */ + SCM_SW_TRIG_4 = 1U, /*!< Generate software trigger4 to (TRGSEL1 & TRGSEL5) */ + SCM_SW_TRIG_5 = 2U, /*!< Generate software trigger5 to (TRGSEL1 & TRGSEL5) */ + SCM_SW_TRIG_6 = 4U, /*!< Generate software trigger6 to (TRGSEL1 & TRGSEL5) */ + SCM_SW_TRIG_7 = 8U /*!< Generate software trigger7 to (TRGSEL1 & TRGSEL5) */ +} SCM_SwTrigxType; + +/** + * @brief Software trigger to TRGSEL0/TRGSEL1 + * + */ +typedef enum +{ + SCM_CCM0_STATUS_CPU_STOP_SYS_SLAVE = SCM_CCM0_STATUS_CPU0_STOP_SYS_SLAVE_MASK, /*!< CCM0 FCG Stop Sys Slave Ack */ + SCM_CCM0_STATUS_CPU_STOP_MASTER = SCM_CCM0_STATUS_CPU0_STOP_MASTER_MASK, /*!< CCM0 FCG Stop Master Ack */ + SCM_CCM0_STATUS_CPU_STOP_SLOW_SLAVE = SCM_CCM0_STATUS_CPU0_STOP_SLOW_SLAVE_MASK,/*!< CCM0 FCG Stop Slow Slave Ack */ + SCM_CCM0_STATUS_CPU_STOP_BUS_SLAVE = SCM_CCM0_STATUS_CPU0_STOP_BUS_SLAVE_MASK, /*!< CCM0 FCG Stop Bus Slave Ack */ + SCM_CCM0_STATUS_CPU_DEEPSLEEPING = SCM_CCM0_STATUS_CPU0_DEEPSLEEPING_MASK, /*!< CPU0 Sleepdeep */ + SCM_CCM0_STATUS_CPU_SLEEPING = SCM_CCM0_STATUS_CPU0_SLEEPING_MASK /*!< CPU0 Sleeping */ +} SCM_CCMxStatusType; + +/** + * @brief SDDF channel clock output selection + * + */ +typedef enum +{ + SCM_SDDF0_RESERVE = 0U, /*!< Reserved */ + SCM_SDDF0_CLKO0, /*!< SDDF0 CLKO0 */ + SCM_SDDF0_CLKO1, /*!< SDDF0 CLKO1 */ + SCM_SDDF0_CLKO2 /*!< SDDF0 CLKO2 */ +} SCM_SDDF_ClkOutSelType; + +/** + * @brief SDDF channel clock input selection + * + */ +typedef enum +{ + SCM_SDDF0_CLK0_IND = 0U, /*!< SDDF0 CLK0_IND */ + SCM_SDDF0_CLK1_IND, /*!< SDDF0 CLK1_IND */ + SCM_SDDF0_CLK2_IND, /*!< SDDF0 CLK2_IND */ + SCM_SDDF0_CLK3_IND /*!< SDDF0 CLK3_IND */ +} SCM_SDDF_ClkInSelType; + +/** + * @brief FLEXCAN routing selection + * + */ +typedef enum +{ + SCM_FLEXCAN_9_9_OR_8_8 = 0U, /*!< FLEXCAN 9 Rx/Tx pad from/to FLEXCAN 9 Rx/Tx pad or + FLEXCAN 8 Rx/Tx pad from/to FLEXCAN 8 Rx/Tx pad */ + SCM_FLEXCAN_9_1_OR_8_0, /*!< FLEXCAN 9 Rx/Tx pad from/to FLEXCAN 1 Rx/Tx pad or + FLEXCAN 8 Rx/Tx pad from/to FLEXCAN 0 Rx/Tx pad */ + SCM_FLEXCAN_9_3_OR_8_2, /*!< FLEXCAN 9 Rx/Tx pad from/to FLEXCAN 3 Rx/Tx pad or + FLEXCAN 8 Rx/Tx pad from/to FLEXCAN 2 Rx/Tx pad */ + SCM_FLEXCAN_9_5_OR_8_4 /*!< FLEXCAN 9 Rx/Tx pad from/to FLEXCAN 5 Rx/Tx pad or + FLEXCAN 8 Rx/Tx pad from/to FLEXCAN 4 Rx/Tx pad */ +} SCM_FlexCanRouterType; + +/** + * @brief MSC routing selection + * + */ +typedef enum +{ + SCM_MSC_FTU0_TO_MSC = 0U, /*!< Select FTU0 ch do out[7:0] to MSCx ALTIN[31:24]/[23:16]/[15:8]/[7:0] */ + SCM_MSC_FTU1_TO_MSC, /*!< Select FTU1 ch do out[7:0] to MSCx ALTIN[31:24]/[23:16]/[15:8]/[7:0] */ + SCM_MSC_FTU2_TO_MSC, /*!< Select FTU2 ch do out[7:0] to MSCx ALTIN[31:24]/[23:16]/[15:8]/[7:0] */ + SCM_MSC_FTU3_TO_MSC, /*!< Select FTU3 ch do out[7:0] to MSCx ALTIN[31:24]/[23:16]/[15:8]/[7:0] */ + SCM_MSC_FTU4_TO_MSC, /*!< Select FTU4 ch do out[7:0] to MSCx ALTIN[31:24]/[23:16]/[15:8]/[7:0] */ + SCM_MSC_FTU5_TO_MSC, /*!< Select FTU5 ch do out[7:0] to MSCx ALTIN[31:24]/[23:16]/[15:8]/[7:0] */ + SCM_MSC_FTU6_TO_MSC, /*!< Select FTU6 ch do out[7:0] to MSCx ALTIN[31:24]/[23:16]/[15:8]/[7:0] */ + SCM_MSC_FTU7_TO_MSC /*!< Select FTU7 ch do out[7:0] to MSCx ALTIN[31:24]/[23:16]/[15:8]/[7:0] */ +} SCM_MSCAltInSelType; + +/** + * @brief ISM routing selection + * + */ +typedef enum +{ + SCM_ISM_FTU0_TO_TRGSEL3 = 0U, /*!< Select FTU0 ch do out[7:0] to TRGSEL3 source [89:82]/[81:74] */ + SCM_ISM_FTU1_TO_TRGSEL3, /*!< Select FTU1 ch do out[7:0] to TRGSEL3 source [89:82]/[81:74] */ + SCM_ISM_FTU2_TO_TRGSEL3, /*!< Select FTU2 ch do out[7:0] to TRGSEL3 source [89:82]/[81:74] */ + SCM_ISM_FTU3_TO_TRGSEL3, /*!< Select FTU3 ch do out[7:0] to TRGSEL3 source [89:82]/[81:74] */ + SCM_ISM_FTU4_TO_TRGSEL3, /*!< Select FTU4 ch do out[7:0] to TRGSEL3 source [89:82]/[81:74] */ + SCM_ISM_FTU5_TO_TRGSEL3, /*!< Select FTU5 ch do out[7:0] to TRGSEL3 source [89:82]/[81:74] */ + SCM_ISM_FTU6_TO_TRGSEL3, /*!< Select FTU6 ch do out[7:0] to TRGSEL3 source [89:82]/[81:74] */ + SCM_ISM_FTU7_TO_TRGSEL3 /*!< Select FTU7 ch do out[7:0] to TRGSEL3 source [89:82]/[81:74] */ +} SCM_ISMRouterType; + +/** + * @brief Matrix status register 0 type + * + */ +typedef enum +{ + SCM_MATRIX_STATUS0_MAM0_S5_M = SCM_MATRIX_STATUS0_MAM0_S5_M_MASK, /*!< MAM0_S5 slave ECC multi bit data error */ + SCM_MATRIX_STATUS0_MAM0_S5_AT = SCM_MATRIX_STATUS0_MAM0_S5_AT_MASK, /*!< MAM0_S5 slave ECC attribute error */ + SCM_MATRIX_STATUS0_MAM0_S5_D = SCM_MATRIX_STATUS0_MAM0_S5_D_MASK, /*!< MAM0_S5 slave ECC single bit data error */ + SCM_MATRIX_STATUS0_MAM0_S5_A = SCM_MATRIX_STATUS0_MAM0_S5_A_MASK, /*!< MAM0_S5 slave ECC address error */ + SCM_MATRIX_STATUS0_MAM0_S4_M = SCM_MATRIX_STATUS0_MAM0_S4_M_MASK, /*!< MAM0_S4 slave ECC multi bit data error */ + SCM_MATRIX_STATUS0_MAM0_S4_AT = SCM_MATRIX_STATUS0_MAM0_S4_AT_MASK, /*!< MAM0_S4 slave ECC attribute error */ + SCM_MATRIX_STATUS0_MAM0_S4_D = SCM_MATRIX_STATUS0_MAM0_S4_D_MASK, /*!< MAM0_S4 slave ECC single bit data error */ + SCM_MATRIX_STATUS0_MAM0_S4_A = SCM_MATRIX_STATUS0_MAM0_S4_A_MASK, /*!< MAM0_S4 slave ECC address error */ + SCM_MATRIX_STATUS0_MAM0_S3_M = SCM_MATRIX_STATUS0_MAM0_S3_M_MASK, /*!< MAM0_S3 slave ECC multi bit data error */ + SCM_MATRIX_STATUS0_MAM0_S3_AT = SCM_MATRIX_STATUS0_MAM0_S3_AT_MASK, /*!< MAM0_S3 slave ECC attribute error */ + SCM_MATRIX_STATUS0_MAM0_S3_D = SCM_MATRIX_STATUS0_MAM0_S3_D_MASK, /*!< MAM0_S3 slave ECC single bit data error*/ + SCM_MATRIX_STATUS0_MAM0_S3_A = SCM_MATRIX_STATUS0_MAM0_S3_A_MASK, /*!< MAM0_S3 slave ECC address error */ + SCM_MATRIX_STATUS0_MAM0_S2_M = SCM_MATRIX_STATUS0_MAM0_S2_M_MASK, /*!< MAM0_S2 slave ECC multi bit data error*/ + SCM_MATRIX_STATUS0_MAM0_S2_AT = SCM_MATRIX_STATUS0_MAM0_S2_AT_MASK, /*!< MAM0_S2 slave ECC attribute error */ + SCM_MATRIX_STATUS0_MAM0_S2_D = SCM_MATRIX_STATUS0_MAM0_S2_D_MASK, /*!< MAM0_S2 slave ECC single bit data error*/ + SCM_MATRIX_STATUS0_MAM0_S2_A = SCM_MATRIX_STATUS0_MAM0_S2_A_MASK, /*!< MAM0_S2 slave ECC address error */ + SCM_MATRIX_STATUS0_MAM0_S1_M = SCM_MATRIX_STATUS0_MAM0_S1_M_MASK, /*!< MAM0_S1 slave ECC multi bit data error */ + SCM_MATRIX_STATUS0_MAM0_S1_AT = SCM_MATRIX_STATUS0_MAM0_S1_AT_MASK, /*!< MAM0_S1 slave ECC attribute error */ + SCM_MATRIX_STATUS0_MAM0_S1_D = SCM_MATRIX_STATUS0_MAM0_S1_D_MASK, /*!< MAM0_S1 slave ECC single bit data error */ + SCM_MATRIX_STATUS0_MAM0_S1_A = SCM_MATRIX_STATUS0_MAM0_S1_A_MASK, /*!< MAM0_S1 slave ECC address error */ + SCM_MATRIX_STATUS0_ROM_M = SCM_MATRIX_STATUS0_ROM_M_MASK, /*!< ROM array ECC multi bit data error */ + SCM_MATRIX_STATUS0_ROM_D = SCM_MATRIX_STATUS0_ROM_D_MASK, /*!< ROM array ECC single bit data error */ + SCM_MATRIX_STATUS0_ROM_A = SCM_MATRIX_STATUS0_ROM_A_MASK /*!< ROM array ECC address error */ +} SCM_MatrixStatus0Type; + +/** + * @brief Matrix status register 1 type + * + */ +typedef enum +{ + SCM_MATRIX_STATUS1_DMA0_M = SCM_MATRIX_STATUS1_DMA0_M_MASK, /*!< DMA0 master ECC multi bit data error */ + SCM_MATRIX_STATUS1_DMA0_D = SCM_MATRIX_STATUS1_DMA0_D_MASK, /*!< DMA0 master ECC single bit data error */ + SCM_MATRIX_STATUS1_DMA0_A = SCM_MATRIX_STATUS1_DMA0_A_MASK, /*!< DMA0 master ECC address error */ + SCM_MATRIX_STATUS1_HSM_M = SCM_MATRIX_STATUS1_HSM_M_MASK, /*!< HSM master ECC multi bit data error */ + SCM_MATRIX_STATUS1_HSM_D = SCM_MATRIX_STATUS1_HSM_D_MASK, /*!< HSM master ECC single bit data error */ + SCM_MATRIX_STATUS1_HSM_A = SCM_MATRIX_STATUS1_HSM_A_MASK, /*!< HSM master ECC address error */ + SCM_MATRIX_STATUS1_MAM0_S5_DS_M = SCM_MATRIX_STATUS1_MAM0_S5_DS_M_MASK, /*!< MAM0_S5 downsize ECC multi bit data error */ + SCM_MATRIX_STATUS1_MAM0_S5_DS_D = SCM_MATRIX_STATUS1_MAM0_S5_DS_D_MASK, /*!< MAM0_S5 downsize ECC single bit data error */ + SCM_MATRIX_STATUS1_MAM0_S5_DS_A = SCM_MATRIX_STATUS1_MAM0_S5_DS_A_MASK, /*!< MAM0_S5 downsize ECC address error */ + SCM_MATRIX_STATUS1_MAM0_S8_M = SCM_MATRIX_STATUS1_MAM0_S8_M_MASK, /*!< MAM0_S8 slave ECC multi bit data error */ + SCM_MATRIX_STATUS1_MAM0_S8_AT = SCM_MATRIX_STATUS1_MAM0_S8_AT_MASK, /*!< MAM0_S8 slave ECC attribute error */ + SCM_MATRIX_STATUS1_MAM0_S8_D = SCM_MATRIX_STATUS1_MAM0_S8_D_MASK, /*!< MAM0_S8 slave ECC single bit data error */ + SCM_MATRIX_STATUS1_MAM0_S8_A = SCM_MATRIX_STATUS1_MAM0_S8_A_MASK, /*!< MAM0_S8 slave ECC address error */ + SCM_MATRIX_STATUS1_MAM0_S7_M = SCM_MATRIX_STATUS1_MAM0_S7_M_MASK, /*!< MAM0_S7 slave ECC multi bit data error */ + SCM_MATRIX_STATUS1_MAM0_S7_AT = SCM_MATRIX_STATUS1_MAM0_S7_AT_MASK, /*!< MAM0_S7 slave ECC attribute error */ + SCM_MATRIX_STATUS1_MAM0_S7_D = SCM_MATRIX_STATUS1_MAM0_S7_D_MASK, /*!< MAM0_S7 slave ECC single bit data error */ + SCM_MATRIX_STATUS1_MAM0_S7_A = SCM_MATRIX_STATUS1_MAM0_S7_A_MASK, /*!< MAM0_S7 slave ECC address error */ + SCM_MATRIX_STATUS1_MAM0_S6_M = SCM_MATRIX_STATUS1_MAM0_S6_M_MASK, /*!< MAM0_S6 slave ECC multi bit data error */ + SCM_MATRIX_STATUS1_MAM0_S6_AT = SCM_MATRIX_STATUS1_MAM0_S6_AT_MASK, /*!< MAM0_S6 slave ECC attribute error */ + SCM_MATRIX_STATUS1_MAM0_S6_D = SCM_MATRIX_STATUS1_MAM0_S6_D_MASK, /*!< MAM0_S6 slave ECC single bit data error*/ + SCM_MATRIX_STATUS1_MAM0_S6_A = SCM_MATRIX_STATUS1_MAM0_S6_A_MASK, /*!< MAM0_S6 slave ECC address error */ +} SCM_MatrixStatus1Type; + +/** + * @brief Matrix status register 2 type + * + */ +typedef enum +{ + SCM_MATRIX_STATUS2_C0_OVERLAY = SCM_MATRIX_STATUS2_C0_OVERLAY_MASK, /*!< CPU0 AHB Overlay error */ + SCM_MATRIX_STATUS2_C0_LOCKSTEP = SCM_MATRIX_STATUS2_C0_LOCKSTEP_MASK, /*!< CPU0 Lockstep error */ + SCM_MATRIX_STATUS2_C0_DTCM1_A = SCM_MATRIX_STATUS2_C0_DTCM1_A_MASK, /*!< CPU0 DTCM1 ECC Address error */ + SCM_MATRIX_STATUS2_C0_DTCM1_M = SCM_MATRIX_STATUS2_C0_DTCM1_M_MASK, /*!< CPU0 DTCM1 ECC Multi Bit Data error */ + SCM_MATRIX_STATUS2_C0_DTCM1_S = SCM_MATRIX_STATUS2_C0_DTCM1_S_MASK, /*!< CPU0 DTCM1 ECC Single Bit Data error */ + SCM_MATRIX_STATUS2_C0_DTCM0_A = SCM_MATRIX_STATUS2_C0_DTCM0_A_MASK, /*!< CPU0 DTCM0 ECC Address error */ + SCM_MATRIX_STATUS2_C0_DTCM0_M = SCM_MATRIX_STATUS2_C0_DTCM0_M_MASK, /*!< CPU0 DTCM0 ECC Multi Bit Data error */ + SCM_MATRIX_STATUS2_C0_DTCM0_S = SCM_MATRIX_STATUS2_C0_DTCM0_S_MASK, /*!< CPU0 DTCM0 ECC Single Bit Data error */ + SCM_MATRIX_STATUS2_C0_ITCM_A = SCM_MATRIX_STATUS2_C0_ITCM_A_MASK, /*!< CPU0 ITCM ECC Address error */ + SCM_MATRIX_STATUS2_C0_ITCM_M = SCM_MATRIX_STATUS2_C0_ITCM_M_MASK, /*!< CPU0 ITCM ECC Multi Bit Data error */ + SCM_MATRIX_STATUS2_C0_ITCM_S = SCM_MATRIX_STATUS2_C0_ITCM_S_MASK, /*!< CPU0 ITCM ECC Single Bit Data error */ + SCM_MATRIX_STATUS2_C0_DCACHE = SCM_MATRIX_STATUS2_C0_DCACHE_MASK, /*!< CPU0 DCache Array error */ + SCM_MATRIX_STATUS2_C0_ICACHE = SCM_MATRIX_STATUS2_C0_ICACHE_MASK, /*!< CPU0 ICache Array error */ + SCM_MATRIX_STATUS2_C0_DTCM1_DEC = SCM_MATRIX_STATUS2_C0_DTCM1_DEC_MASK, /*!< CPU0 DTCM1 decode monitor error */ + SCM_MATRIX_STATUS2_C0_DTCM0_DEC = SCM_MATRIX_STATUS2_C0_DTCM0_DEC_MASK, /*!< CPU0 DTCM0 decode monitor error */ + SCM_MATRIX_STATUS2_C0_ITCM_DEC = SCM_MATRIX_STATUS2_C0_ITCM_DEC_MASK, /*!< CPU0 ITCM decode monitor error */ + SCM_MATRIX_STATUS2_C0_AHBP_F2S = SCM_MATRIX_STATUS2_C0_AHBP_F2S_MASK, /*!< CPU0 AHBP fast to slow monitor error */ + SCM_MATRIX_STATUS2_C0_AHBM_M = SCM_MATRIX_STATUS2_C0_AHBM_M_MASK, /*!< CPU0 AHBM master ECC multi bit data error */ + SCM_MATRIX_STATUS2_C0_AHBM_D = SCM_MATRIX_STATUS2_C0_AHBM_D_MASK, /*!< CPU0 AHBM master ECC single bit data error */ + SCM_MATRIX_STATUS2_C0_AHBM_A = SCM_MATRIX_STATUS2_C0_AHBM_A_MASK, /*!< CPU0 AHBM master ECC address error */ + SCM_MATRIX_STATUS2_C0_AHBS_M = SCM_MATRIX_STATUS2_C0_AHBS_M_MASK, /*!< CPU0 AHBS master ECC multi bit data error */ + SCM_MATRIX_STATUS2_C0_AHBS_D = SCM_MATRIX_STATUS2_C0_AHBS_D_MASK, /*!< CPU0 AHBS master ECC single bit data error */ + SCM_MATRIX_STATUS2_C0_AHBS_A = SCM_MATRIX_STATUS2_C0_AHBS_A_MASK, /*!< CPU0 AHBS master ECC address error */ + SCM_MATRIX_STATUS2_C0_AHBP_M = SCM_MATRIX_STATUS2_C0_AHBP_M_MASK, /*!< CPU0 AHBP master ECC multi bit data error */ + SCM_MATRIX_STATUS2_C0_AHBP_D = SCM_MATRIX_STATUS2_C0_AHBP_D_MASK, /*!< CPU0 AHBP master ECC single bit data error */ + SCM_MATRIX_STATUS2_C0_AHBP_A = SCM_MATRIX_STATUS2_C0_AHBP_A_MASK, /*!< CPU0 AHBP master ECC address error */ +} SCM_MatrixStatus2Type; + +/** + * @brief Matrix status register 5 type + * + */ +typedef enum +{ + + SCM_MATRIX_STATUS5_DMA0_CFG_M = SCM_MATRIX_STATUS5_DMA0_CFG_M_MASK, /*!< DMA0_CFG ECC Multi Bit Data Error */ + SCM_MATRIX_STATUS5_DMA0_LOCKSTEP = SCM_MATRIX_STATUS5_DMA0_LOCKSTEP_MASK,/*!< DMA0 Lockstep Error */ + SCM_MATRIX_STATUS5_DMA0_CFG_S = SCM_MATRIX_STATUS5_DMA0_CFG_S_MASK, /*!< DMA0_CFG ECC Single Bit Data Error */ + SCM_MATRIX_STATUS5_DMA0_CFG_A = SCM_MATRIX_STATUS5_DMA0_CFG_A_MASK, /*!< DMA0_CFG ECC Address Error */ + SCM_MATRIX_STATUS5_EDC_HI = SCM_MATRIX_STATUS5_EDC_HI_MASK, /*!< Flash Control OCM EDC FCCU Alarm High Error */ + SCM_MATRIX_STATUS5_LINE_SBC = SCM_MATRIX_STATUS5_LINE_SBC_MASK, /*!< FCCU Alarm Linebuffer Self ECC Single Bit Error */ + SCM_MATRIX_STATUS5_LINE_MULTI = SCM_MATRIX_STATUS5_LINE_MULTI_MASK, /*!< FCCU Alarm Linebuffer Self ECC Multi Bit Error */ + SCM_MATRIX_STATUS5_ENC = SCM_MATRIX_STATUS5_ENC_MASK, /*!< FLASH Control OCM ENC FCCU Alarm Error */ + SCM_MATRIX_STATUS5_EDC = SCM_MATRIX_STATUS5_EDC_MASK, /*!< Flash Control OCM EDC FCCU Alarm Error */ + SCM_MATRIX_STATUS5_P2_D_M = SCM_MATRIX_STATUS5_P2_D_M_MASK, /*!< Flash Control Port 2 Data Multi Error */ + SCM_MATRIX_STATUS5_P1_D_M = SCM_MATRIX_STATUS5_P1_D_M_MASK, /*!< Flash Control Port 1 Data Multi Error */ + SCM_MATRIX_STATUS5_P0_D_M = SCM_MATRIX_STATUS5_P0_D_M_MASK, /*!< Flash Control Port 0 Data Multi Error */ + SCM_MATRIX_STATUS5_P2_C_M = SCM_MATRIX_STATUS5_P2_C_M_MASK, /*!< Flash Control Port 2 Code Multi Error */ + SCM_MATRIX_STATUS5_P1_C_M = SCM_MATRIX_STATUS5_P1_C_M_MASK, /*!< Flash Control Port 1 Code Multi Error */ + SCM_MATRIX_STATUS5_P0_C_M = SCM_MATRIX_STATUS5_P0_C_M_MASK, /*!< Flash Control Port 0 Code Multi Error */ + SCM_MATRIX_STATUS5_P2_D_S = SCM_MATRIX_STATUS5_P2_D_S_MASK, /*!< Flash Control Port 2 Data Single Error */ + SCM_MATRIX_STATUS5_P1_D_S = SCM_MATRIX_STATUS5_P1_D_S_MASK, /*!< Flash Control Port 1 Data Single Error */ + SCM_MATRIX_STATUS5_P0_D_S = SCM_MATRIX_STATUS5_P0_D_S_MASK, /*!< Flash Control Port 0 Data Single Error */ + SCM_MATRIX_STATUS5_P2_C_S = SCM_MATRIX_STATUS5_P2_C_S_MASK, /*!< Flash Control Port 2 Code Single Error */ + SCM_MATRIX_STATUS5_P1_C_S = SCM_MATRIX_STATUS5_P1_C_S_MASK, /*!< Flash Control Port 1 Code Single Error */ + SCM_MATRIX_STATUS5_P0_C_S = SCM_MATRIX_STATUS5_P0_C_S_MASK /*!< Flash Control Port 0 Code Single Error */ +} SCM_MatrixStatus5Type; + +/** + * @brief Matrix status register 6 type + * + */ +typedef enum +{ + SCM_MATRIX_STATUS6_STALL_ERR = SCM_MATRIX_STATUS6_STALL_ERR_MASK, /*!< MAM Stall Error */ + SCM_MATRIX_STATUS6_MAM0_S8_DS = SCM_MATRIX_STATUS6_MAM0_S8_DS_MASK, /*!< MAM0_S8 Downsize Monitor Error */ + SCM_MATRIX_STATUS6_MAM0_S5_DS = SCM_MATRIX_STATUS6_MAM0_S5_DS_MASK, /*!< MAM0_S5 Downsize Monitor Error */ + SCM_MATRIX_STATUS6_MAM0_S5_S2F = SCM_MATRIX_STATUS6_MAM0_S5_S2F_MASK, /*!< MAM0_S5 Slow to Fast Gasket Monitor Error */ + SCM_MATRIX_STATUS6_SRAM1_DEC = SCM_MATRIX_STATUS6_SRAM1_DEC_MASK, /*!< SARM1 Decode Monitor Error */ + SCM_MATRIX_STATUS6_SRAM0_DEC = SCM_MATRIX_STATUS6_SRAM0_DEC_MASK, /*!< SARM0 Decode Monitor Error */ + SCM_MATRIX_STATUS6_AFCB1_MON = SCM_MATRIX_STATUS6_AFCB1_MON_MASK, /*!< AFCB0 Monitor Error */ + SCM_MATRIX_STATUS6_AFCB0_MON = SCM_MATRIX_STATUS6_AFCB0_MON_MASK, /*!< AFCB1 Monitor Error */ + SCM_MATRIX_STATUS6_STCU_ST = SCM_MATRIX_STATUS6_STCU_ST_MASK, /*!< STCU Self Test Monitor Error */ + SCM_MATRIX_STATUS6_DCM_SCAN = SCM_MATRIX_STATUS6_DCM_SCAN_MASK, /*!< FCM Scan ECC Error */ + SCM_MATRIX_STATUS6_NON_USER = SCM_MATRIX_STATUS6_NON_USER_MASK, /*!< STCU Nonuser Error */ + SCM_MATRIX_STATUS6_SCM_CRC = SCM_MATRIX_STATUS6_SCM_CRC_MASK, /*!< SCM CRC Error */ + SCM_MATRIX_STATUS6_SCG_CRC = SCM_MATRIX_STATUS6_SCG_CRC_MASK, /*!< SCG CRC Error */ + SCM_MATRIX_STATUS6_SRAM1_CTRL_MON = SCM_MATRIX_STATUS6_SRAM1_CTRL_MON_MASK, /*!< SRAM1 Control Monitor Error */ + SCM_MATRIX_STATUS6_SRAM0_CTRL_MON = SCM_MATRIX_STATUS6_SRAM0_CTRL_MON_MASK, /*!< SRAM0 Control Monitor Error */ + SCM_MATRIX_STATUS6_SRAM1_M = SCM_MATRIX_STATUS6_SRAM1_M_MASK, /*!< SRAM1 Multi Bit Data Error */ + SCM_MATRIX_STATUS6_SRAM1_EDC = SCM_MATRIX_STATUS6_SRAM1_EDC_MASK, /*!< SRAM1 EDC Error */ + SCM_MATRIX_STATUS6_SRAM1_A = SCM_MATRIX_STATUS6_SRAM1_A_MASK, /*!< SRAM1 Address Error */ + SCM_MATRIX_STATUS6_SRAM1_S = SCM_MATRIX_STATUS6_SRAM1_S_MASK, /*!< SRAM1 Single Bit Data Error */ + SCM_MATRIX_STATUS6_SAM0_M = SCM_MATRIX_STATUS6_SAM0_M_MASK, /*!< SRAM0 Multi Bit Data Error */ + SCM_MATRIX_STATUS6_SRAM0_EDC = SCM_MATRIX_STATUS6_SRAM0_EDC_MASK, /*!< SRAM0 EDC Error */ + SCM_MATRIX_STATUS6_SRAM0_A = SCM_MATRIX_STATUS6_SRAM0_A_MASK, /*!< SRAM0 Address Error */ + SCM_MATRIX_STATUS6_SRAM0_S = SCM_MATRIX_STATUS6_SRAM0_S_MASK /*!< SRAM0 Single Bit Data Error */ +} SCM_MatrixStatus6Type; + +/** + * @brief Matrix status register 7 type + * + */ +typedef enum +{ + SCM_MATRIX_STATUS7_HSM_IRAM_M = SCM_MATRIX_STATUS7_HSM_IRAM_M_MASK, /*!< HSM IRAM Multi Bit Data Error */ + SCM_MATRIX_STATUS7_HSM_IRAM_S = SCM_MATRIX_STATUS7_HSM_IRAM_S_MASK, /*!< HSM IRAM Single Bit Data Error */ + SCM_MATRIX_STATUS7_HSM_DRAM_M = SCM_MATRIX_STATUS7_HSM_DRAM_M_MASK, /*!< HSM DRAM Multi Bit Data Error*/ + SCM_MATRIX_STATUS7_HSM_DRAM_S = SCM_MATRIX_STATUS7_HSM_DRAM_S_MASK, /*!< HSM DRAM Single Bit Data Error */ + SCM_MATRIX_STATUS7_HSM_WDOG = SCM_MATRIX_STATUS7_HSM_WDOG_MASK, /*!< HSM WDOG Request */ + SCM_MATRIX_STATUS7_MAM0_ERR = SCM_MATRIX_STATUS7_MAM0_ERR_MASK, /*!< MAM0 Timeout Error*/ + SCM_MATRIX_STATUS7_FOSC_ERR = SCM_MATRIX_STATUS7_FOSC_ERR_MASK, /*!< FOSC Loss of Clock Error*/ + SCM_MATRIX_STATUS7_PLL1_ERR = SCM_MATRIX_STATUS7_PLL1_ERR_MASK, /*!< PLL1 Loss of Clock Error*/ + SCM_MATRIX_STATUS7_PLL0_ERR = SCM_MATRIX_STATUS7_PLL0_ERR_MASK /*!< PLL0 Loss of Clock Error */ +} SCM_MatrixStatus7Type; + +/** + * @brief Matrix ID status type + * + */ +typedef enum +{ + SCM_MATRIX_ID_STATUS0_MAM0_S3_ID = 0U, /*!< MAM0_S3 Slave ECC Error with Which Master Access */ + SCM_MATRIX_ID_STATUS0_MAM0_S4_ID = 1U, /*!< MAM0_S4 Slave ECC Error with Which Master Access */ + SCM_MATRIX_ID_STATUS0_MAM0_S5_ID = 3U, /*!< MAM0_S5 Slave ECC Error with Which Master Access */ + SCM_MATRIX_ID_STATUS0_SRAM0_ID = 4U, /*!< SARM0 ECC error with which master access */ + SCM_MATRIX_ID_STATUS0_SRAM1_ID = 5U /*!< SARM1 ECC Error with Which Master Access */ +} SCM_MatrixIDStatusType; + +/** + * @brief Matrix ID status master type + * + */ +typedef enum +{ + SCM_MATRIX_ID_STATUS0_MASTER_CPU0 = 0x0U, /*!< SARM2 ECC error with CPU0 access */ + SCM_MATRIX_ID_STATUS0_MASTER_HSM = 0x8U, /*!< SARM1 ECC error with HSM access */ + SCM_MATRIX_ID_STATUS0_MASTER_DMA0 = 0xAU, /*!< SARM0 ECC error with DMA0 access */ +} SCM_MatrixIDStatusMasterType; + +/** + * @brief SCM SYSAP control Status2 Register Selection typ + * + */ +typedef enum +{ + SCM_SYSAP_STATUS2_SEL_UID0 = 0U, /*!< Select UID0 */ + SCM_SYSAP_STATUS2_SEL_UID1 = 1U, /*!< Select UID1 */ + SCM_SYSAP_STATUS2_SEL_UID2 = 2U, /*!< Select UID2 */ + SCM_SYSAP_STATUS2_SEL_UID3 = 3U, /*!< Select UID3 */ + SCM_SYSAP_STATUS2_SEL_NVRVERSION = 4U /*!< Select NVR version */ +} SCM_SysAPStatus2SelType; + +/** + * @brief Mass erase type + * + */ +typedef enum +{ + SCM_SECTORERASE_AS_MASSERASE = 0U, /*!< Use sector erase for mass erase */ + SCM_CHIPERASE_AS_MASSERASE /*!< Use chip erase for mass erase */ +} SCM_SysApMassEraseType; + +/** + * @brief Cpu Type of forcing to halt + * + */ +typedef enum +{ + SCM_DEBUG_CPU0 = 1U, /*!< Force CPU0 to halt */ +} SCM_SysApCpuDebugReqType; + +/** + * @brief Subsystem status type + * + */ +typedef enum +{ + SCM_SUBSYS_STATUS_CHIP_IS_FT = SCM_SUBSYS_STATUS_CHIP_IS_FT_MASK, /*!< SEC dc lifecycle ft */ + SCM_SUBSYS_STATUS_CHIP_IS_VIRGIN = SCM_SUBSYS_STATUS_CHIP_IS_VIRGIN_MASK, /*!< SEC dc lifecycle virgin */ + SCM_SUBSYS_STATUS_TPU_CLK_EN = SCM_SUBSYS_STATUS_TPU_CLK_EN_MASK, /*!< TPU Clock Enable */ + SCM_SUBSYS_STATUS_HSM_RST = SCM_SUBSYS_STATUS_HSM_RST_MASK, /*!< Subsystem reset state */ + SCM_SUBSYS_STATUS_HSM_SYS_ERR_INT = SCM_SUBSYS_STATUS_HSM_SYS_ERR_INT_MASK, /*!< Subsystem error interrupt */ + SCM_SUBSYS_STATUS_WDG_RST = SCM_SUBSYS_STATUS_WDG_RST_MASK, /*!< Subsystem WDG generated reset flag */ + SCM_SUBSYS_STATUS_INIT_DONE = SCM_SUBSYS_STATUS_INIT_DONE_MASK, /*!< Subsystem Initial done flag */ + SCM_SUBSYS_STATUS_ISP_TOGGLE = SCM_SUBSYS_STATUS_ISP_TOGGLE_MASK, /*!< Subsystem ISP PIN toggle flag */ + SCM_SUBSYS_STATUS_SUBSYS_SLEEP = SCM_SUBSYS_STATUS_HSM_SLEEP_MASK, /*!< Subsystem sleep state */ + SCM_SUBSYS_STATUS_STOP_ACK = SCM_SUBSYS_STATUS_STOP_ACK_MASK /*!< Subsystem stop mode ack */ +} SCM_SUBSYSStatusType; + +/** + * @brief Master halt request type + * + */ +typedef enum +{ + SCM_MASTER_HALT_REQ_HSM_REQ = 0U, /*!< HSM Halt Request */ + SCM_MASTER_HALT_REQ_DMA0_REQ = 2U, /*!< DMA0 Halt Request */ +} SCM_HaltReqType; + +/** + * @brief Master halt request type + * + */ +typedef enum +{ + SCM_MASTER_HALT_REQ_NOT_HALTED = 0U, /*!< Not Halted state */ + SCM_MASTER_HALT_REQ_HALTED_STATE = 1U, /*!< Halted state */ +} SCM_HaltReqAckType; + + +/********* Local inline function ************/ +/** + * @brief Get UIDL data(Unique identification for the chip. Loaded from NVR) + * + * @return return value + */ +LOCAL_INLINE uint32_t SCM_HWA_GetData_UIDL(void) +{ + return SCM->UIDL; +} + +/** + * @brief Get UIDML data(Unique identification for the chip. Loaded from NVR) + * + * @return return value + */ +LOCAL_INLINE uint32_t SCM_HWA_GetData_UIDML(void) +{ + return SCM->UIDML; +} + +/** + * @brief Get UIDMH data(Unique identification for the chip. Loaded from NVR) + * + * @return return value + */ +LOCAL_INLINE uint32_t SCM_HWA_GetData_UIDMH(void) +{ + return SCM->UIDMH; +} + +/** + * @brief Get UIDH data(Unique identification for the chip. Loaded from NVR) + * + * @return return value + */ +LOCAL_INLINE uint32_t SCM_HWA_GetData_UIDH(void) +{ + return SCM->UIDH; +} + +/** + * @brief Get Family Identification + * + * @return return value + */ +LOCAL_INLINE uint8_t SCM_HWA_GetData_FamilyID(void) +{ + return (uint8_t)((SCM->PARTID0 & (uint32_t)SCM_PARTID0_FAM_ID_MASK) >> (uint32_t)SCM_PARTID0_FAM_ID_SHIFT); +} + +/** + * @brief Get Revision Identification + * + * @return return value + */ +LOCAL_INLINE uint8_t SCM_HWA_GetData_RevID(void) +{ + return (uint8_t)((SCM->PARTID0 & (uint32_t)SCM_PARTID0_REVID_MASK)); +} + +/** + * @brief Get CHIPCFG0 register status + * + * @return return value + */ +LOCAL_INLINE uint32_t SCM_HWA_GetStatus_CHIPCFG0(void) +{ + return SCM->CHIPCFG0; +} + +/** + * @brief Get CPU lock step enable/disable status + * + * @return 1: CPU lock step is enabled + * 0: CPU lock step is disabled + */ +LOCAL_INLINE uint32_t SCM_HWA_GetLockStepStatus_Cpu0(void) +{ + return ((SCM->CHIPCFG0 & (uint32_t)SCM_CHIPCFG0_CPU0_LOCKSTEP_EN_MASK)>>(uint32_t)SCM_CHIPCFG0_CPU0_LOCKSTEP_EN_SHIFT); +} + +/** + * @brief Get CANFD enable/disable status + * + * @return 1: CANFD is enabled + * 0: CANFD is disabled + */ +LOCAL_INLINE uint32_t SCM_HWA_GetStatus_CANFD(void) +{ + return ((SCM->CHIPCFG0 & (uint32_t)SCM_CHIPCFG0_CAN_FD_MASK)>>(uint32_t)SCM_CHIPCFG0_CAN_FD_SHIFT); +} + +/** + * @brief Get device ID + * + * @return The device ID + */ +LOCAL_INLINE uint32_t SCM_HWA_GetData_DeviceID(void) +{ + return ((SCM->CHIPCFG1 & (uint32_t)SCM_CHIPCFG1_DEVICE_ID_MASK) >> (uint32_t)SCM_CHIPCFG1_DEVICE_ID_SHIFT); +} + +/** + * @brief Lock the CPU permission(WPB) in MAMECCEN0 register, and WPB cannot be written until a power-on reset + * + */ +LOCAL_INLINE void SCM_HWA_MAMECCEN0_LockWritePermit(void) +{ + SCM->MAMECCEN0 |= (uint32_t)SCM_MAMECCEN0_WPB_LOCK_MASK; +} + +/** + * @brief Get the lock status of CPU permission(WPB) in MAMECCEN0 register + * + * @return 1: The WPB of MAMECCEN0 register is locked + * 0: The WPB of MAMECCEN0 register is not locked + */ +LOCAL_INLINE uint32_t SCM_HWA_MAMECCEN0_GetWPBLockStatus(void) +{ + return (SCM->MAMECCEN0 & (uint32_t)SCM_MAMECCEN0_WPB_LOCK_MASK) >> SCM_MAMECCEN0_WPB_LOCK_SHIFT; +} + +/** + * @brief Get the CPU type of writing permission to MAMECCEN0 register + * + * @return SCM_WPB_CpuType The CPU which has the write permission + */ +LOCAL_INLINE SCM_WPB_CpuType SCM_HWA_MAMECCEN0_GetCpuWritePermit(void) +{ + uint32_t u32RegVal = ((SCM->MAMECCEN0 & (uint32_t)SCM_MAMECCEN0_WPB_MASK) >> SCM_MAMECCEN0_WPB_SHIFT); + return (SCM_WPB_CpuType)u32RegVal; +} + +/** + * @brief Set CPU to control the MAMECCEN0 register + * + * @param eCpuType CPU allowed to control peripheral + */ +LOCAL_INLINE void SCM_HWA_MAMECCEN0_SetCpuWritePermit(SCM_WPB_CpuType eCpuType) +{ + SCM->MAMECCEN0 = ((SCM->MAMECCEN0 & (~(uint32_t)SCM_MAMECCEN0_WPB_MASK)) | SCM_MAMECCEN0_WPB(eCpuType)); +} + +/** + * @brief Get the value of MAMECCEN0 register + * @return register value + */ +LOCAL_INLINE uint32_t SCM_HWA_MAMECCEN0_GetValue(void) +{ + return SCM->MAMECCEN0; +} + +/** + * @brief Set the value of MAMECCEN0 register + * @param u32Value value to be set, the value must be the or value of SCM_MAMEccCtrlGrp0Type + */ +LOCAL_INLINE void SCM_HWA_MAMECCEN0_SetValue(uint32_t u32Value) +{ + SCM->MAMECCEN0 = u32Value & 0x03FFCFCFu; +} + +/** + * @brief Set the MAMECCEN0 ECC enable + * @param eMamEccType the MAM peripheral to enable ECC + * @param eEnable the ECC enable mode + */ +LOCAL_INLINE void SCM_HWA_MAMECCEN0_Ctrl(SCM_MAMEccCtrlGrp0Type eMamEccType, SCM_EccEnModeType eEnable) +{ + + SCM->MAMECCEN0 = (SCM->MAMECCEN0 & (~(SCM_MAMECCEN0_ECC_MASK << ((uint32_t)eMamEccType * SCM_MAMECCEN0_ECC_WIDTH)))) | + SCM_MAMECCEN0_ECC(eEnable) << ((uint32_t)eMamEccType * SCM_MAMECCEN0_ECC_WIDTH); +} + +/** + * @brief Lock the CPU permission(WPB) in MAMECCEN1 register, and WPB cannot be written until a power-on reset + * + */ +LOCAL_INLINE void SCM_HWA_MAMECCEN1_LockWritePermit(void) +{ + SCM->MAMECCEN1 |= (uint32_t)SCM_MAMECCEN1_WPB_LOCK_MASK; +} + +/** + * @brief Get the lock status of CPU permission(WPB) in MAMECCEN1 register + * + * @return 1: The WPB of MAMECCEN1 register is locked + * 0: The WPB of MAMECCEN1 register is not locked + */ +LOCAL_INLINE uint32_t SCM_HWA_MAMECCEN1_GetWPBLockStatus(void) +{ + return (SCM->MAMECCEN1 & (uint32_t)SCM_MAMECCEN1_WPB_LOCK_MASK) >> SCM_MAMECCEN1_WPB_LOCK_SHIFT; +} + +/** + * @brief Get the CPU type of writing permission to MAMECCEN1 register + * + * @return SCM_WPB_CpuType The CPU which has the write permission + */ +LOCAL_INLINE SCM_WPB_CpuType SCM_HWA_MAMECCEN1_GetCpuWritePermit(void) +{ + uint32_t u32RegVal = ((SCM->MAMECCEN1 & (uint32_t)SCM_MAMECCEN1_WPB_MASK) >> SCM_MAMECCEN1_WPB_SHIFT); + return (SCM_WPB_CpuType)u32RegVal; +} + +/** + * @brief Set CPU to control the MAMECCEN1 register + * + * @param eCpuType CPU allowed to control peripheral + */ +LOCAL_INLINE void SCM_HWA_MAMECCEN1_SetCpuWritePermit(SCM_WPB_CpuType eCpuType) +{ + SCM->MAMECCEN1 = ((SCM->MAMECCEN1 & (~(uint32_t)SCM_MAMECCEN1_WPB_MASK)) | SCM_MAMECCEN1_WPB(eCpuType)); +} + +/** + * @brief Get the value of MAMECCEN1 register + * @return register value + */ +LOCAL_INLINE uint32_t SCM_HWA_MAMECCEN1_GetValue(void) +{ + return SCM->MAMECCEN1; +} + +/** + * @brief Set the value of MAMECCEN1 register + * @param u32Value value to be set + */ +LOCAL_INLINE void SCM_HWA_MAMECCEN1_SetValue(uint32_t u32Value) +{ + SCM->MAMECCEN1 = u32Value & 0x00003D33u; +} + +/** + * @brief Set the MAMECCEN1 ECC enable + * @param eMamEccType the MAM peripheral to enable ECC + * @param eEnable the ECC enable mode + */ +LOCAL_INLINE void SCM_HWA_MAMECCEN1_Ctrl(SCM_MAMEccCtrlGrp1Type eMamEccType, SCM_EccEnModeType eEnable) +{ + if(SCM_DMA0_CFG_ECC == eMamEccType) + { + SCM->MAMECCEN1 = (SCM->MAMECCEN1 & (~(SCM_MAMECCEN1_DMA0_CFG_ECC_MASK))) | + SCM_MAMECCEN1_DMA0_CFG_ECC(eEnable); + } + else + { + SCM->MAMECCEN1 = (SCM->MAMECCEN1 & (~(SCM_MAMECCEN1_ECC_MASK << ((uint32_t)eMamEccType * SCM_MAMECCEN1_ECC_WIDTH)))) | + SCM_MAMECCEN1_ECC(eEnable) << ((uint32_t)eMamEccType * SCM_MAMECCEN1_ECC_WIDTH); + } +} + +/** + * @brief Lock the CPU permission(WPB) in CPU0ECCEN register, and WPB cannot be written until a power-on reset + * + */ +LOCAL_INLINE void SCM_HWA_CPU0ECCEN_LockWritePermit(void) +{ + SCM->CPU0ECCEN |= (uint32_t)SCM_CPU0ECCEN_WPB_LOCK_MASK; +} + +/** + * @brief Get the lock status of CPU permission(WPB) in CPU0ECCEN register + * + * @return 1: The WPB of CPU0ECCEN register is locked + * 0: The WPB of CPU0ECCEN register is not locked + */ +LOCAL_INLINE uint32_t SCM_HWA_CPU0ECCEN_GetWPBLockStatus(void) +{ + return (SCM->CPU0ECCEN & (uint32_t)SCM_CPU0ECCEN_WPB_LOCK_MASK) >> SCM_CPU0ECCEN_WPB_LOCK_SHIFT; +} + +/** + * @brief Get the CPU type of writing permission to CPU0ECCEN register + * + * @return SCM_WPB_CpuType The CPU which has the write permission + */ +LOCAL_INLINE SCM_WPB_CpuType SCM_HWA_CPU0ECCEN_GetCpuWritePermit(void) +{ + uint32_t u32RegVal = ((SCM->CPU0ECCEN & (uint32_t)SCM_CPU0ECCEN_WPB_MASK) >> SCM_CPU0ECCEN_WPB_SHIFT); + return (SCM_WPB_CpuType)u32RegVal; +} + +/** + * @brief Set CPU to control the CPU0ECCEN register + * + * @param eCpuType CPU allowed to control peripheral + */ +LOCAL_INLINE void SCM_HWA_CPU0ECCEN_SetCpuWritePermit(SCM_WPB_CpuType eCpuType) +{ + uint32_t u32RegVal = SCM->CPU0ECCEN; + SCM->CPU0ECCEN = ((u32RegVal & (~(uint32_t)SCM_CPU0ECCEN_WPB_MASK)) | SCM_CPU0ECCEN_WPB(eCpuType)); +} + +/** + * @brief Get the value of CPU0ECCEN register + * @return register value + */ +LOCAL_INLINE uint32_t SCM_HWA_CPU0ECCEN_GetValue(void) +{ + return SCM->CPU0ECCEN; +} + +/** + * @brief Set the value of CPU0ECCEN register + * @param u32Value value to be set + */ +LOCAL_INLINE void SCM_HWA_CPU0ECCEN_SetValue(uint32_t u32Value) +{ + SCM->CPU0ECCEN = u32Value & 0x00000FFFu; +} + +/** + * @brief Set the peripheral ECC enable of CPU0 + * @param eCpuEccType the peripheral to enable ECC + * @param eEnable the ECC enable mode + */ +LOCAL_INLINE void SCM_HWA_CPU0ECCEN_Ctrl(SCM_CPUEccCtrlType eCpuEccType, SCM_EccEnModeType eEnable) +{ + SCM->CPU0ECCEN = (SCM->CPU0ECCEN & (~(SCM_CPU0ECCEN_CPU0_ECC_MASK << ((uint32_t)eCpuEccType * SCM_CPU0ECCEN_CPU0_ECC_WIDTH)))) | + SCM_CPU0ECCEN_CPU0_ECC(eEnable) << ((uint32_t)eCpuEccType * SCM_CPU0ECCEN_CPU0_ECC_WIDTH); +} + +/** + * @brief Get SRAM1 ECC Detect Control + * @return 0: Disable EDC error when SRAM1 Multi Bit ECC Error Exist + * 1: Only Enable EDC error when SRAM1 Multi Bit ECC Error Exist + */ +LOCAL_INLINE uint32_t SCM_HWA_SRAM1_EDCErrorEnStatus(void) +{ + return (SCM->SRAM_EDC_CTRL & SCM_SRAM_EDC_CTRL_SRAM1_EDC_MASK) >> SCM_SRAM_EDC_CTRL_SRAM1_EDC_SHIFT; +} + +/** + * @brief Set SRAM1 ECC Detect Control + * @param bEnable true: Disable EDC error when SRAM1 Multi Bit ECC Error Exist + * false: Only Enable EDC error when SRAM1 Multi Bit ECC Error Exist + */ +LOCAL_INLINE void SCM_HWA_SRAM1_EDCErrorEnable(bool bEnable) +{ + SCM->SRAM_EDC_CTRL = (SCM->SRAM_EDC_CTRL & (~SCM_SRAM_EDC_CTRL_SRAM1_EDC_MASK)) | SCM_SRAM_EDC_CTRL_SRAM1_EDC(bEnable); +} + +/** + * @brief Get SRAM0 ECC Detect Control + * @return 0: Disable EDC error when SRAM0 Multi Bit ECC Error Exist + * 1: Only Enable EDC error when SRAM0 Multi Bit ECC Error Exist + */ +LOCAL_INLINE uint32_t SCM_HWA_SRAM0_EDCErrorEnStatus(void) +{ + return (SCM->SRAM_EDC_CTRL & SCM_SRAM_EDC_CTRL_SRAM0_EDC_MASK) >> SCM_SRAM_EDC_CTRL_SRAM0_EDC_SHIFT; +} + +/** + * @brief Set SRAM0 ECC Detect Control + * @param bEnable false: Disable EDC error when SRAM0 Multi Bit ECC Error Exist + * true: Only Enable EDC error when SRAM0 Multi Bit ECC Error Exist + */ +LOCAL_INLINE void SCM_HWA_SRAM0_EDCErrorEnable(bool bEnable) +{ + SCM->SRAM_EDC_CTRL = (SCM->SRAM_EDC_CTRL & (~SCM_SRAM_EDC_CTRL_SRAM0_EDC_MASK)) | SCM_SRAM_EDC_CTRL_SRAM0_EDC(bEnable); +} + +/** + * @brief Lock ROM Configuration Register + * + */ +LOCAL_INLINE void SCM_HWA_LockROMCFG(void) +{ + SCM->ROMCFG |= (uint32_t)SCM_ROMCFG_LOCK_MASK; +} + +/** + * @brief Get ROMCFG register lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t SCM_HWA_ROMCFG_GetLockStatus(void) +{ + return(SCM->ROMCFG & (uint32_t)SCM_ROMCFG_LOCK_MASK) >> SCM_ROMCFG_LOCK_SHIFT; +} + +/** + * @brief Get HSM ROM Power Gating Enable status + * @return 0: Not Power Gating + * 1: Power Gating + */ +LOCAL_INLINE uint32_t SCM_HWA_GetHsmRomPowerGatingEnStatus(void) +{ + return (SCM->ROMCFG & SCM_ROMCFG_HSMROM_PGEN_MASK) >> SCM_ROMCFG_HSMROM_PGEN_SHIFT; +} + +/** + * @brief Set HSM ROM Power Gating Enable + * @param bEnable false: Not Power Gating + * true: Power Gating + */ +LOCAL_INLINE void SCM_HWA_HsmRomPowerGatingEnable(bool bEnable) +{ + SCM->ROMCFG = (SCM->ROMCFG & (~SCM_ROMCFG_HSMROM_PGEN_MASK)) | SCM_ROMCFG_HSMROM_PGEN(bEnable); +} + +/** + * @brief Get System ROM Power Gating Enable status + * @return 0: Not Power Gating + * 1: Power Gating + */ +LOCAL_INLINE uint32_t SCM_HWA_GetSysRomPowerGatingEnStatus(void) +{ + return (SCM->ROMCFG & SCM_ROMCFG_SYSROM_PGEN_MASK) >> SCM_ROMCFG_SYSROM_PGEN_SHIFT; +} + +/** + * @brief Set System ROM Power Gating Enable + * @param bEnable false: Not Power Gating + * true: Power Gating + */ +LOCAL_INLINE void SCM_HWA_SysRomPowerGatingEnable(bool bEnable) +{ + SCM->ROMCFG = (SCM->ROMCFG & (~SCM_ROMCFG_SYSROM_PGEN_MASK)) | SCM_ROMCFG_SYSROM_PGEN(bEnable); +} + +/** + * @brief Use FCSPI5 to monitor other FCSPI's transmit interface + * + * @param eSPIxType SPI type + */ +LOCAL_INLINE void SCM_HWA_FCSPI5MonSPIx(SCM_FCSPIxType eSPIxType) +{ + uint32_t u32RegVal = SCM->FCSPI_ROUTING; + SCM->FCSPI_ROUTING = ((u32RegVal & (~(uint32_t)SCM_FCSPI_ROUTING_SPI5_ROUTER_MASK)) | SCM_FCSPI_ROUTING_SPI5_ROUTER(eSPIxType)); +} + +/** + * @brief Use FCSPI4 to monitor other FCSPI's transmit interface + * + * @param eSPIxType SPI type + */ +LOCAL_INLINE void SCM_HWA_FCSPI4MonSPIx(SCM_FCSPIxType eSPIxType) +{ + uint32_t u32RegVal = SCM->FCSPI_ROUTING; + SCM->FCSPI_ROUTING = ((u32RegVal & (~(uint32_t)SCM_FCSPI_ROUTING_SPI4_ROUTER_MASK)) | SCM_FCSPI_ROUTING_SPI4_ROUTER(eSPIxType)); +} + +/** + * @brief Use FCSPI3 to monitor other FCSPI's transmit interface + * + * @param eSPIxType SPI type + */ +LOCAL_INLINE void SCM_HWA_FCSPI3MonSPIx(SCM_FCSPIxType eSPIxType) +{ + uint32_t u32RegVal = SCM->FCSPI_ROUTING; + SCM->FCSPI_ROUTING = ((u32RegVal & (~(uint32_t)SCM_FCSPI_ROUTING_SPI3_ROUTER_MASK)) | SCM_FCSPI_ROUTING_SPI3_ROUTER(eSPIxType)); +} + +/** + * @brief Use FCSPI2 to monitor other FCSPI's transmit interface + * + * @param eSPIxType SPI type + */ +LOCAL_INLINE void SCM_HWA_FCSPI2MonSPIx(SCM_FCSPIxType eSPIxType) +{ + uint32_t u32RegVal = SCM->FCSPI_ROUTING; + SCM->FCSPI_ROUTING = ((u32RegVal & (~(uint32_t)SCM_FCSPI_ROUTING_SPI2_ROUTER_MASK)) | SCM_FCSPI_ROUTING_SPI2_ROUTER(eSPIxType)); +} + +/** + * @brief Use FCSPI1 to monitor other FCSPI's transmit interface + * + * @param eSPIxType SPI type + */ +LOCAL_INLINE void SCM_HWA_FCSPI1MonSPIx(SCM_FCSPIxType eSPIxType) +{ + uint32_t u32RegVal = SCM->FCSPI_ROUTING; + SCM->FCSPI_ROUTING = ((u32RegVal & (~(uint32_t)SCM_FCSPI_ROUTING_SPI1_ROUTER_MASK)) | SCM_FCSPI_ROUTING_SPI1_ROUTER(eSPIxType)); +} + +/** + * @brief Use FCSPI0 to monitor other FCSPI's transmit interface + * + * @param eSPIxType SPI type + */ +LOCAL_INLINE void SCM_HWA_FCSPI0MonSPIx(SCM_FCSPIxType eSPIxType) +{ + uint32_t u32RegVal = SCM->FCSPI_ROUTING; + SCM->FCSPI_ROUTING = ((u32RegVal & (~(uint32_t)SCM_FCSPI_ROUTING_SPI0_ROUTER_MASK)) | SCM_FCSPI_ROUTING_SPI0_ROUTER(eSPIxType)); +} + +/** + * @brief Use FCUART7 to monitor other FCSPI's transmit interface + * + * @param eUartxType Uart type + */ +LOCAL_INLINE void SCM_HWA_FCUART7MonUARTx(SCM_MON_FCUARTxType eUartxType) +{ + uint32_t u32RegVal = SCM->FCUART_ROUTING0; + SCM->FCUART_ROUTING0 = ((u32RegVal & (~(uint32_t)SCM_FCUART_ROUTING0_UART7_ROUTER_MASK)) | SCM_FCUART_ROUTING0_UART7_ROUTER(eUartxType)); +} + +/** + * @brief Use FCUART6 to monitor other FCSPI's transmit interface + * + * @param eUartxType Uart type + */ +LOCAL_INLINE void SCM_HWA_FCUART6MonUARTx(SCM_MON_FCUARTxType eUartxType) +{ + uint32_t u32RegVal = SCM->FCUART_ROUTING0; + SCM->FCUART_ROUTING0 = ((u32RegVal & (~(uint32_t)SCM_FCUART_ROUTING0_UART6_ROUTER_MASK)) | SCM_FCUART_ROUTING0_UART6_ROUTER(eUartxType)); +} + +/** + * @brief Use FCUART5 to monitor other FCSPI's transmit interface + * + * @param eUartxType Uart type + */ +LOCAL_INLINE void SCM_HWA_FCUART5MonUARTx(SCM_MON_FCUARTxType eUartxType) +{ + uint32_t u32RegVal = SCM->FCUART_ROUTING0; + SCM->FCUART_ROUTING0 = ((u32RegVal & (~(uint32_t)SCM_FCUART_ROUTING0_UART5_ROUTER_MASK)) | SCM_FCUART_ROUTING0_UART5_ROUTER(eUartxType)); +} + +/** + * @brief Use FCUART4 to monitor other FCSPI's transmit interface + * + * @param eUartxType Uart type + */ +LOCAL_INLINE void SCM_HWA_FCUART4MonUARTx(SCM_MON_FCUARTxType eUartxType) +{ + uint32_t u32RegVal = SCM->FCUART_ROUTING0; + SCM->FCUART_ROUTING0 = ((u32RegVal & (~(uint32_t)SCM_FCUART_ROUTING0_UART4_ROUTER_MASK)) | SCM_FCUART_ROUTING0_UART4_ROUTER(eUartxType)); +} + +/** + * @brief Use FCUART3 to monitor other FCSPI's transmit interface + * + * @param eUartxType Uart type + */ +LOCAL_INLINE void SCM_HWA_FCUART3MonUARTx(SCM_MON_FCUARTxType eUartxType) +{ + uint32_t u32RegVal = SCM->FCUART_ROUTING0; + SCM->FCUART_ROUTING0 = ((u32RegVal & (~(uint32_t)SCM_FCUART_ROUTING0_UART3_ROUTER_MASK)) | SCM_FCUART_ROUTING0_UART3_ROUTER(eUartxType)); +} + +/** + * @brief Use FCUART2 to monitor other FCSPI's transmit interface + * + * @param eUartxType Uart type + */ +LOCAL_INLINE void SCM_HWA_FCUART2MonUARTx(SCM_MON_FCUARTxType eUartxType) +{ + uint32_t u32RegVal = SCM->FCUART_ROUTING0; + SCM->FCUART_ROUTING0 = ((u32RegVal & (~(uint32_t)SCM_FCUART_ROUTING0_UART2_ROUTER_MASK)) | SCM_FCUART_ROUTING0_UART2_ROUTER(eUartxType)); +} + +/** + * @brief Use FCUART1 to monitor other FCSPI's transmit interface + * + * @param eUartxType Uart type + */ +LOCAL_INLINE void SCM_HWA_FCUART1MonUARTx(SCM_MON_FCUARTxType eUartxType) +{ + uint32_t u32RegVal = SCM->FCUART_ROUTING0; + SCM->FCUART_ROUTING0 = ((u32RegVal & (~(uint32_t)SCM_FCUART_ROUTING0_UART1_ROUTER_MASK)) | SCM_FCUART_ROUTING0_UART1_ROUTER(eUartxType)); +} + +/** + * @brief Use FCUART0 to monitor other FCSPI's transmit interface + * + * @param eUartxType Uart type + */ +LOCAL_INLINE void SCM_HWA_FCUART0MonUARTx(SCM_MON_FCUARTxType eUartxType) +{ + uint32_t u32RegVal = SCM->FCUART_ROUTING0; + SCM->FCUART_ROUTING0 = ((u32RegVal & (~(uint32_t)SCM_FCUART_ROUTING0_UART0_ROUTER_MASK)) | SCM_FCUART_ROUTING0_UART0_ROUTER(eUartxType)); +} + +/** + * @brief Set PTIMER Loop Mode selection + * + * @param ePTimerLoopMode PTIMER Loop Mode + */ +LOCAL_INLINE void SCM_HWA_PTimerLoopModeSel(SCM_PTimerLMSelType ePTimerLoopMode) +{ + uint32_t u32RegVal = SCM->ADC_ROUTING; + SCM->ADC_ROUTING = ((u32RegVal & + (~(uint32_t)(SCM_ADC_ROUTING_PTIMER01LOOP_MASK | + SCM_ADC_ROUTING_PTIMER01LOOP_1_MASK | + SCM_ADC_ROUTING_PTIMER01LOOP_2_MASK))) | + SCM_ADC_ROUTING_PTIMER01LOOP((uint32_t)ePTimerLoopMode >> 2U)) | + SCM_ADC_ROUTING_PTIMER01LOOP_1((uint32_t)ePTimerLoopMode >> 1U) | + SCM_ADC_ROUTING_PTIMER01LOOP_2((uint32_t)ePTimerLoopMode); +} + +/** + * @brief Set ADC1 Trigger Source selection + * + * @param eAdcTriggerSrc ADC1 Trigger Source + */ +LOCAL_INLINE void SCM_HWA_ADC1TriggerSrcSel(SCM_AdcTriggerSrcType eAdcTriggerSrc) +{ + uint32_t u32RegVal = SCM->ADC_ROUTING; + SCM->ADC_ROUTING = ((u32RegVal & (~(uint32_t)SCM_ADC_ROUTING_ADC1_TRGSEL_MASK)) | + SCM_ADC_ROUTING_ADC1_TRGSEL(eAdcTriggerSrc)); +} + +/** + * @brief Set ADC1 Pre-trigger Source selection + * + * @param eAdcTriggerSrc ADC1 Pre-trigger Source + */ +LOCAL_INLINE void SCM_HWA_ADC1PreTriggerSrcSel(SCM_AdcPreTriggerSrcType eAdcPreTriggerSrc) +{ + uint32_t u32RegVal = SCM->ADC_ROUTING; + SCM->ADC_ROUTING = ((u32RegVal & (~(uint32_t)SCM_ADC_ROUTING_ADC1_PRETRGSEL_MASK)) | + SCM_ADC_ROUTING_ADC1_PRETRGSEL(eAdcPreTriggerSrc)); +} + +/** + * @brief Set ADC1 SCM Pre-trigger Source selection + * + * @param eScmSoftwarePreTriggerSrc ADC1 SCM software Pre-trigger Source + */ +LOCAL_INLINE void SCM_HWA_ADC1ScmSoftWarePreTriggerSrcSel(SCM_SoftwarePreTriggerType eScmSoftwarePreTriggerSrc) +{ + uint32_t u32RegVal = SCM->ADC_ROUTING; + SCM->ADC_ROUTING = ((u32RegVal & (~(uint32_t)SCM_ADC_ROUTING_ADC1_SWPRETRG_MASK)) | + SCM_ADC_ROUTING_ADC1_SWPRETRG(eScmSoftwarePreTriggerSrc)); +} + +/** + * @brief Set ADC0 Trigger Source selection + * + * @param eAdcTriggerSrc ADC0 Trigger Source + */ +LOCAL_INLINE void SCM_HWA_ADC0TriggerSrcSel(SCM_AdcTriggerSrcType eAdcTriggerSrc) +{ + uint32_t u32RegVal = SCM->ADC_ROUTING; + SCM->ADC_ROUTING = ((u32RegVal & (~(uint32_t)SCM_ADC_ROUTING_ADC0_TRGSEL_MASK)) | + SCM_ADC_ROUTING_ADC0_TRGSEL(eAdcTriggerSrc)); +} + +/** + * @brief Set ADC0 Pre-trigger Source selection + * + * @param eAdcTriggerSrc ADC0 Pre-trigger Source + */ +LOCAL_INLINE void SCM_HWA_ADC0PreTriggerSrcSel(SCM_AdcPreTriggerSrcType eAdcPreTriggerSrc) +{ + uint32_t u32RegVal = SCM->ADC_ROUTING; + SCM->ADC_ROUTING = ((u32RegVal & (~(uint32_t)SCM_ADC_ROUTING_ADC0_PRETRGSEL_MASK)) | + SCM_ADC_ROUTING_ADC0_PRETRGSEL(eAdcPreTriggerSrc)); +} + +/** + * @brief Set ADC0 SCM Pre-trigger Source selection + * + * @param eScmSoftwarePreTriggerSrc ADC0 SCM software Pre-trigger Source + */ +LOCAL_INLINE void SCM_HWA_ADC0ScmSoftWarePreTriggerSrcSel(SCM_SoftwarePreTriggerType eScmSoftwarePreTriggerSrc) +{ + uint32_t u32RegVal = SCM->ADC_ROUTING; + SCM->ADC_ROUTING = ((u32RegVal & (~(uint32_t)SCM_ADC_ROUTING_ADC0_SWPRETRG_MASK)) | + SCM_ADC_ROUTING_ADC0_SWPRETRG(eScmSoftwarePreTriggerSrc)); +} + +/** + * @brief Select the FTU3 output source, should be ignored when FTU3 in input mode + * + * @param eOutSelType FTU3 output source selection type + */ +LOCAL_INLINE void SCM_HWA_SetOutSel_FTU3(SCM_FTU_OutputSelType eOutSelType) +{ + uint32_t u32RegVal = SCM->FTU_ROUTING; + SCM->FTU_ROUTING = ((u32RegVal & (~(uint32_t)SCM_FTU_ROUTING_FTU3_OUTSEL_MASK)) | SCM_FTU_ROUTING_FTU3_OUTSEL(eOutSelType)); +} + +/** + * @brief Select the FTU0 output source, should be ignored when FTU0 in input mode + * + * @param eOutSelType FTU0 output source selection type + */ +LOCAL_INLINE void SCM_HWA_SetOutSel_FTU0(SCM_FTU_OutputSelType eOutSelType) +{ + uint32_t u32RegVal = SCM->FTU_ROUTING; + SCM->FTU_ROUTING = ((u32RegVal & (~(uint32_t)SCM_FTU_ROUTING_FTU0_OUTSEL_MASK)) | SCM_FTU_ROUTING_FTU0_OUTSEL(eOutSelType)); +} + +/** + * @brief Selects FTU2 CH1 input + * + * @param eInputSelType FTU2 CH1 input selection type + */ +LOCAL_INLINE void SCM_HWA_SetInSel_FTU2_CH1(SCM_FTU2_CH1_InputSelType eInputSelType) +{ + uint32_t u32RegVal = SCM->FTU_ROUTING; + SCM->FTU_ROUTING = ((u32RegVal & (~(uint32_t)SCM_FTU_ROUTING_FTU2_CH1SEL_MASK)) | SCM_FTU_ROUTING_FTU2_CH1SEL(eInputSelType)); +} + +/** + * @brief Selects FTU2 CH0 input + * + * @param eInputSelType FTU2 CH0 input selection type + */ +LOCAL_INLINE void SCM_SetInSel_FTU2_CH0(SCM_FTUx_CH0_InputSelType eInputSelType) +{ + uint32_t u32RegVal = SCM->FTU_ROUTING; + SCM->FTU_ROUTING = ((u32RegVal & (~(uint32_t)SCM_FTU_ROUTING_FTU2_CH0SEL_MASK)) | SCM_FTU_ROUTING_FTU2_CH0SEL(eInputSelType)); +} + +/** + * @brief Selects FTU1 CH0 input + * + * @param eInputSelType FTU1 CH0 input selection type + */ +LOCAL_INLINE void SCM_SetInSel_FTU1_CH0(SCM_FTUx_CH0_InputSelType eInputSelType) +{ + uint32_t u32RegVal = SCM->FTU_ROUTING; + SCM->FTU_ROUTING = ((u32RegVal & (~(uint32_t)SCM_FTU_ROUTING_FTU1_CH0SEL_MASK)) | SCM_FTU_ROUTING_FTU1_CH0SEL(eInputSelType)); +} + +/** + * @brief Lock FTU Routing Register + * + */ +LOCAL_INLINE void SCM_HWA_LockFTU_ROUTING(void) +{ + SCM->FTU_ROUTING |= (uint32_t)SCM_FTU_ROUTING_LOCK_MASK; +} + +/** + * @brief Get FTU_ROUTING register lock status + * + * @return Lock status + * 1: FTU_ROUTING register is lock + * 0: FTU_ROUTING register is not lock + */ +LOCAL_INLINE uint32_t SCM_HWA_FTU_ROUTING_GetLockStatus(void) +{ + return (SCM->FTU_ROUTING & (uint32_t)SCM_FTU_ROUTING_LOCK_MASK) >> SCM_FTU_ROUTING_LOCK_SHIFT; +} + +/** + * @brief Lock FTU Global Time Base Control Register + * + */ +LOCAL_INLINE void SCM_HWA_LockFTU_GTB(void) +{ + SCM->FTU_GTBC |= (uint32_t)SCM_FTU_GTBC_LOCK_MASK; +} + +/** + * @brief Get FTU GTB register lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t SCM_HWA_FTU_GTB_GetLockStatus(void) +{ + return (SCM->FTU_GTBC & (uint32_t)SCM_FTU_GTBC_LOCK_MASK) >> SCM_FTU_GTBC_LOCK_SHIFT; +} + +/** + * @brief Configure FTU global time base control selection + * + * @param u32SelectedFtu The GTBC mask of Selected Ftu instance,it is the or value of SCM_FTUGTBCtrlType. + * eg.u32SelectedFtu == 1 means FTU0 selected, u32SelectedFtu == 5 means FTU0 and FTU2 selected. + */ +LOCAL_INLINE void SCM_HWA_ConfigFtuGTBSelect(uint32_t u32SelectedFtu) +{ + SCM->FTU_GTBC &= ~(uint32_t)SCM_FTU_GTBC_FTU_GTBC_MASK; + SCM->FTU_GTBC |= (uint32_t)SCM_FTU_GTBC_FTU_GTBC(u32SelectedFtu); +} + +/** + * @brief Set FTU global time base control selection + * + * @param u32SelectedFtu The GTBC mask of Selected Ftu instance,it is the or value of SCM_FTUGTBCtrlType. + * eg.u32SelectedFtu == 1 means FTU0 selected, u32SelectedFtu == 5 means FTU0 and FTU2 selected. + */ +LOCAL_INLINE void SCM_HWA_SetFtuGTBSelect(uint32_t u32SelectedFtu) +{ + SCM->FTU_GTBC |= (uint32_t)SCM_FTU_GTBC_FTU_GTBC(u32SelectedFtu); +} + +/** + * @brief Clear FTU global time base control selection + * + * @param u32SelectedFtu The GTBC mask of Selected Ftu instance,it is the or value of SCM_FTUGTBCtrlType. + * eg.u32SelectedFtu == 1 means FTU0 selected, u32SelectedFtu == 5 means FTU0 and FTU2 selected. + */ +LOCAL_INLINE void SCM_HWA_ClearFtuGTBSelect(uint32_t u32SelectedFtu) +{ + SCM->FTU_GTBC &= ~(uint32_t)SCM_FTU_GTBC_FTU_GTBC(u32SelectedFtu); +} + +/** + * @brief Configure TPU global time base control selection + * + * @param bEn Enable or disable TPU Global Time Base + */ +LOCAL_INLINE void SCM_HWA_ConfigTpuGTBSelect(bool bEn) +{ + SCM->FTU_GTBC &= ~(uint32_t)SCM_FTU_GTBC_TPU_GTBC_MASK; + SCM->FTU_GTBC |= (uint32_t)SCM_FTU_GTBC_TPU_GTBC(bEn); +} + +/** + * @brief Set the value of TPU Global Time Base Control Mask Register + * + * @param u32Value Value to be set + */ +LOCAL_INLINE void SCM_HWA_SetTpuGTBMValue(uint32_t u32Value) +{ + SCM->FTU_GTBCM = u32Value; +} + +/** + * @brief Configure TPU Channel [31:24] Source Select + * + * @param eTrgSelMask The TPU Channel [31:24] Source Select mask bits + */ +LOCAL_INLINE void SCM_HWA_ConfigTpuTrgSel(uint8_t eTrgSelMask) +{ + SCM->FTU_GTBCM = (SCM->FTU_GTBCM & (~(uint32_t)SCM_TPU_GTBCM_TPU_TRGSEL_MASK)) | + (uint32_t)SCM_TPU_GTBCM_TPU_TRGSEL(eTrgSelMask); +} + +/** + * @brief Configure TPU GTBC Mask is corresponding to channel trigger of TSTMP1 + * + * @param eTpuGTBMask The TPU GTBC Mask (must be 0 ~ 15) + */ +LOCAL_INLINE void SCM_HWA_ConfigTpuGTBMask(uint8_t eTpuGTBMask) +{ + SCM->FTU_GTBCM = (SCM->FTU_GTBCM & (~(uint32_t)SCM_TPU_GTBCM_TPU_GTBCM_MASK)) | + (uint32_t)SCM_TPU_GTBCM_TPU_GTBCM(eTpuGTBMask); +} + +/** + * @brief Configure FTU Global Time Base Control Mask Register + * + * @param u8FtuIndex The selected FTU instance (must be 0 ~ 7) + * @param u32Value Value to be set (must be 0 ~ 15) + */ +LOCAL_INLINE void SCM_HWA_ConfigFtuGTBMask(uint8_t u8FtuIndex, uint32_t u32Value) +{ + SCM->FTU_GTBCM &= ~ ((uint32_t)SCM_FTU_GTBCM_FTU0_GTBCM_MASK << (SCM_FTU_GTBCM_FTU0_GTBCM_WIDTH * u8FtuIndex)); + SCM->FTU_GTBCM |= (((uint32_t)u32Value & SCM_FTU_GTBCM_FTU0_GTBCM_MASK) << (SCM_FTU_GTBCM_FTU0_GTBCM_WIDTH * u8FtuIndex)); +} + +/** + * @brief Clear FTU Global Time Base Control Mask Register + * + * @param u8FtuIndex The selected FTU instance (must be 0 ~ 7) + */ +LOCAL_INLINE void SCM_HWA_ClearFtuGTBMask(uint8_t u8FtuIndex) +{ + SCM->FTU_GTBCM &= ~ ((uint32_t)SCM_FTU_GTBCM_FTU0_GTBCM_MASK << (SCM_FTU_GTBCM_FTU0_GTBCM_WIDTH * u8FtuIndex)); +} + +/** + * @brief Set FTU sync control + * + * @param u32Value The sync mask of selected FTU instance + * u32Value must be the or value of SCM_FTUSyncCtrlType + */ +LOCAL_INLINE void SCM_HWA_SetFTUSync(uint32_t u32Value) +{ + SCM->FTU_SYNC = u32Value & SCM_FTU_SYNC_MASK; +} + +/** + * @brief Lock FTU GTB Register + * + */ +LOCAL_INLINE void SCM_HWA_LockDEBUG_TRACE(void) +{ + SCM->DEBUG_TRACE |= (uint32_t)SCM_DEBUG_TRACE_LOCK_MASK; +} + +/** + * @brief Get FTU GTB register lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t SCM_HWA_DEBUG_TRACE_GetLockStatus(void) +{ + return(SCM->DEBUG_TRACE & (uint32_t)SCM_DEBUG_TRACE_LOCK_MASK) >> SCM_DEBUG_TRACE_LOCK_SHIFT; +} + +/** + * @brief Set debug atclk enable/disable + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SetEnable_DebugATClk(bool bEnable) +{ + SCM->DEBUG_TRACE = (SCM->DEBUG_TRACE & (~(SCM_DEBUG_TRACE_DEBUG_ATCLK_EN_MASK))) | + SCM_DEBUG_TRACE_DEBUG_ATCLK_EN(bEnable); +} + +/** + * @brief Set trace clock divider value + * + * @param u32Value The divider value to be set + */ +LOCAL_INLINE void SCM_HWA_SetTraceClkDiv(uint32_t u32Value) +{ + SCM->DEBUG_TRACE = ((SCM->DEBUG_TRACE & (~(uint32_t)SCM_DEBUG_TRACE_TRACECLK_DIV_MASK)) | + SCM_DEBUG_TRACE_TRACECLK_DIV(u32Value)); +} + +/** + * @brief Set trace clock selection + * + * @param eSrcClkType Clock selection + */ +LOCAL_INLINE void SCM_HWA_SetTraceClkSrc(SCM_TraceClkSrcType eSrcClkType) +{ + SCM->DEBUG_TRACE = ((SCM->DEBUG_TRACE & (~(uint32_t)SCM_DEBUG_TRACE_TRACECLK_SEL_MASK)) | + SCM_DEBUG_TRACE_TRACECLK_SEL(eSrcClkType)); +} + +/** + * @brief Set trace clock divider enable/disable + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SetEnable_TraceClk(bool bEnable) +{ + SCM->DEBUG_TRACE = (SCM->DEBUG_TRACE & (~(SCM_DEBUG_TRACE_TRACECLK_EN_MASK))) | + SCM_DEBUG_TRACE_TRACECLK_EN(bEnable); +} + +/** + * @brief Lock the SOCMISC register + * + */ +LOCAL_INLINE void SCM_HWA_SOCMISC_LockWritePermit(void) +{ + SCM->SOCMISC |= (uint32_t)SCM_SOCMISC_WPB_LOCK_MASK; +} + +/** + * @brief Get the SOCMISC register lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t SCM_HWA_SOCMISC_GetWPBLockStatus(void) +{ + return (SCM->SOCMISC & (uint32_t)SCM_SOCMISC_WPB_LOCK_MASK) >> SCM_SOCMISC_WPB_LOCK_SHIFT; +} + +/** + * @brief Get the CPU type of writing permission to SOCMISC register + * + * @return SCM_WPB_CpuType The CPU which has the write permission + */ +LOCAL_INLINE SCM_WPB_CpuType SCM_HWA_SOCMISC_GetCpuWritePermit(void) +{ + uint32_t u32RegVal = (SCM->SOCMISC & (uint32_t)SCM_SOCMISC_WPB_MASK) >> SCM_SOCMISC_WPB_SHIFT; + return (SCM_WPB_CpuType)u32RegVal; +} + +/** + * @brief Set cpu to control SOCMISC register + * + * @param eCpuType Cpu allowed to control peripheral + */ +LOCAL_INLINE void SCM_HWA_SOCMISC_SetCpuWritePermit(SCM_WPB_CpuType eCpuType) +{ + SCM->SOCMISC = ((SCM->SOCMISC & (~(uint32_t)SCM_SOCMISC_WPB_MASK)) | SCM_SOCMISC_WPB(eCpuType)); +} + +/** + * @brief Set software trigger 4~7 to TRGSEL1 & TRGSEL5 + * + * @param eTriggerType software trigger number (SCM_SW_TRIG_0 ~ SCM_SW_TRIG_3) + */ +LOCAL_INLINE void SCM_HWA_SetSwTrigx_Trgsel15(SCM_SwTrigxType eTriggerType) +{ + SCM->SOCMISC = ((SCM->SOCMISC & (~(uint32_t)SCM_SOCMISC_GPR_SW_TRIG_7_4_MASK)) | + SCM_SOCMISC_GPR_SW_TRIG_7_4(eTriggerType)); +} + +/** + * @brief Set software trigger 0~3 to TRGSEL0 & TRGSEL4 + * + * @param eTriggerType software trigger number (SCM_SW_TRIG_4 ~ SCM_SW_TRIG_7) + */ +LOCAL_INLINE void SCM_HWA_SetSwTrigx_Trgsel04(SCM_SwTrigxType eTriggerType) +{ + SCM->SOCMISC = ((SCM->SOCMISC & (~(uint32_t)SCM_SOCMISC_GPR_SW_TRIG_3_0_MASK)) | + SCM_SOCMISC_GPR_SW_TRIG_3_0(eTriggerType)); +} + +/** + * @brief Get CCM0 status + * + * @return CCM0 Status, it is the or value of SCM_CCMxStatusType + */ +LOCAL_INLINE uint32_t SCM_HWA_GetStatus_CCM0( void ) +{ + return SCM->CCM0_STATUS & SCM_CCM0_STATUS_MASK; +} + +/** + * @brief Lock FLEXCAN_ROUTING Register + * + */ +LOCAL_INLINE void SCM_HWA_LockFLEXCAN_ROUTING(void) +{ + SCM->FLEXCAN_ROUTING |= (uint32_t)SCM_FLEXCAN_ROUTING_LOCK_MASK; +} + +/** + * @brief Get FLEXCAN_ROUTING register lock status + * + * @return Lock status + * 1: FLEXCAN_ROUTING register is lock + * 0: FLEXCAN_ROUTING register is not lock + */ +LOCAL_INLINE uint32_t SCM_HWA_FLEXCAN_ROUTING_GetLockStatus(void) +{ + return (SCM->FLEXCAN_ROUTING & (uint32_t)SCM_FLEXCAN_ROUTING_LOCK_MASK) >> SCM_FLEXCAN_ROUTING_LOCK_SHIFT; +} + +/** + * @brief Select TRESEL input from pad TRGSEL_IN0~TRGSEL_IN15 for FLEXCAN0/1/2/3 RX + * + * @param u16TrgSel Enable Select TRESEL input from pad TRGSEL_IN0~TRGSEL_IN15 for FLEXCAN0/1/2/3 RX + */ +LOCAL_INLINE void SCM_HWA_FLEXCAN_ROUTING_SetTriggerSel(uint16_t u16TrgSel) +{ + SCM->FLEXCAN_ROUTING = ((SCM->FLEXCAN_ROUTING & (~(uint32_t)SCM_FLEXCAN_ROUTING_FLEXCAN_TRIGGER_MASK_MASK)) | + SCM_FLEXCAN_ROUTING_FLEXCAN_TRIGGER_MASK(u16TrgSel)); +} + +/** + * @brief Set MSC0 ALTIN high higher bits[31:24] source selection + * + * @param eInSelType Router selection + */ +LOCAL_INLINE void SCM_HWA_SetSel_MSC0AltInHH(SCM_MSCAltInSelType eInSelType) +{ + uint32_t u32RegVal = SCM->MSC0_ROUTING; + SCM->MSC0_ROUTING = ((u32RegVal & (~(uint32_t)SCM_MSC0_ROUTING_MSC0_31_24_SEL_MASK)) | SCM_MSC0_ROUTING_MSC0_31_24_SEL(eInSelType)); +} + +/** + * @brief Set MSC0 ALTIN high lower bits[23:16] source selection + * + * @param eInSelType Router selection + */ +LOCAL_INLINE void SCM_HWA_SetSel_MSC0AltInHL(SCM_MSCAltInSelType eInSelType) +{ + uint32_t u32RegVal = SCM->MSC0_ROUTING; + SCM->MSC0_ROUTING = ((u32RegVal & (~(uint32_t)SCM_MSC0_ROUTING_MSC0_23_16_SEL_MASK)) | SCM_MSC0_ROUTING_MSC0_23_16_SEL(eInSelType)); +} + +/** + * @brief Set MSC0 ALTIN low higher bits[15:8] source selection + * + * @param eInSelType Router selection + */ +LOCAL_INLINE void SCM_HWA_SetSel_MSC0AltInLH(SCM_MSCAltInSelType eInSelType) +{ + uint32_t u32RegVal = SCM->MSC0_ROUTING; + SCM->MSC0_ROUTING = ((u32RegVal & (~(uint32_t)SCM_MSC0_ROUTING_MSC0_15_8_SEL_MASK)) | SCM_MSC0_ROUTING_MSC0_15_8_SEL(eInSelType)); +} + +/** + * @brief Set MSC0 ALTIN low lower bits[7:0] source selection + * + * @param eInSelType Router selection + */ +LOCAL_INLINE void SCM_HWA_SetSel_MSC0AltInLL(SCM_MSCAltInSelType eInSelType) +{ + uint32_t u32RegVal = SCM->MSC0_ROUTING; + SCM->MSC0_ROUTING = ((u32RegVal & (~(uint32_t)SCM_MSC0_ROUTING_MSC0_7_0_SEL_MASK)) | SCM_MSC0_ROUTING_MSC0_7_0_SEL(eInSelType)); +} + +/** + * @brief Lock MSC0_ROUTING Register + * + */ +LOCAL_INLINE void SCM_HWA_LockMSC0_ROUTING(void) +{ + SCM->MSC0_ROUTING |= (uint32_t)SCM_MSC0_ROUTING_LOCK_MASK; +} + +/** + * @brief Get MSC0_ROUTING register lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t SCM_HWA_MSC0_ROUTING_GetLockStatus(void) +{ + return(SCM->MSC0_ROUTING & (uint32_t)SCM_MSC0_ROUTING_LOCK_MASK) >> SCM_MSC0_ROUTING_LOCK_SHIFT; +} + +/** + * @brief Set FCSMU software trigger enable/disable + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SetEnable_FCSMUSwTrigger(bool bEnable) +{ + SCM->FCSMU_SW = (SCM->FCSMU_SW & (~(SCM_FCSMU_SW_FCSMU_SW_MASK))) | + SCM_FCSMU_SW_FCSMU_SW(bEnable); +} + +/** + * @brief FTU_IN[15:8] Source Select + * + * @param eRouterType Router source selection + */ +LOCAL_INLINE void SCM_HWA_SetIsmRouterFtuD(SCM_ISMRouterType eRouterType) +{ + SCM->ISM_ROUTING = ((SCM->ISM_ROUTING & (~(uint32_t)SCM_ISM_ROUTING_ISM_ROUT_FTU_D_MASK)) | + SCM_ISM_ROUTING_ISM_ROUT_FTU_D(eRouterType)); +} + +/** + * @brief FTU_IN[7:0] Source Select + * + * @param eRouterType Router source selection + */ +LOCAL_INLINE void SCM_HWA_SetIsmRouterFtuC(SCM_ISMRouterType eRouterType) +{ + SCM->ISM_ROUTING = ((SCM->ISM_ROUTING & (~(uint32_t)SCM_ISM_ROUTING_ISM_ROUT_FTU_C_MASK)) | + SCM_ISM_ROUTING_ISM_ROUT_FTU_C(eRouterType)); +} + +/** + * @brief Set ISM_FTU_ROUT[15:8] source select + * + * @param eRouterType Router source selection + */ +LOCAL_INLINE void SCM_HWA_SetIsmRouterFtuB(SCM_ISMRouterType eRouterType) +{ + SCM->ISM_ROUTING = ((SCM->ISM_ROUTING & (~(uint32_t)SCM_ISM_ROUTING_ISM_ROUT_FTU_B_MASK)) | + SCM_ISM_ROUTING_ISM_ROUT_FTU_B(eRouterType)); +} + +/** + * @brief Set ISM_FTU_ROUT[7:0] source select + * + * @param eRouterType Router source selection + */ +LOCAL_INLINE void SCM_HWA_SetIsmRouterFtuA(SCM_ISMRouterType eRouterType) +{ + SCM->ISM_ROUTING = ((SCM->ISM_ROUTING & (~(uint32_t)SCM_ISM_ROUTING_ISM_ROUT_FTU_A_MASK)) | + SCM_ISM_ROUTING_ISM_ROUT_FTU_A(eRouterType)); +} + +/** + * @brief Get matrix status register 0 status + * + * @return Register status + */ +LOCAL_INLINE uint32_t SCM_HWA_GetStatus_MATRIX_STATUS0(void) +{ + return SCM->MATRIX_STATUS0; +} + +/** + * @brief clear matrix status register 0 status + * + * @u32Status Matrix status + */ +LOCAL_INLINE void SCM_HWA_Clear_MATRIX_STATUS0(uint32_t u32Status) +{ + SCM->MATRIX_STATUS0 |= u32Status & SCM_MATRIX_STATUS0_MASK; +} + +/** + * @brief Get matrix status register 1 status + * + * @return Register status + */ +LOCAL_INLINE uint32_t SCM_HWA_GetStatus_MATRIX_STATUS1(void) +{ + return SCM->MATRIX_STATUS1; +} + +/** + * @brief clear matrix status register 1 status + * + * @u32Status Matrix status + */ +LOCAL_INLINE void SCM_HWA_Clear_MATRIX_STATUS1(uint32_t u32Status) +{ + SCM->MATRIX_STATUS1 |= u32Status & SCM_MATRIX_STATUS1_MASK; +} + +/** + * @brief Get matrix status register 2 status + * + * @return Register status + */ +LOCAL_INLINE uint32_t SCM_HWA_GetStatus_MATRIX_STATUS2(void) +{ + return SCM->MATRIX_STATUS2; +} + +/** + * @brief clear matrix status register 2 status + * + * @u32Status Matrix status + */ +LOCAL_INLINE void SCM_HWA_Clear_MATRIX_STATUS2(uint32_t u32Status) +{ + SCM->MATRIX_STATUS2 |= u32Status & SCM_MATRIX_STATUS2_MASK; +} + +/** + * @brief Get matrix status register 5 status + * + * @return Register status + */ +LOCAL_INLINE uint32_t SCM_HWA_GetStatus_MATRIX_STATUS5(void) +{ + return SCM->MATRIX_STATUS5; +} + +/** + * @brief clear matrix status register 5 status + * + * @u32Status Matrix status + */ +LOCAL_INLINE void SCM_HWA_Clear_MATRIX_STATUS5(uint32_t u32Status) +{ + SCM->MATRIX_STATUS5 |= u32Status & SCM_MATRIX_STATUS5_MASK; +} + +/** + * @brief Get matrix status register 6 status + * + * @return Register status + */ +LOCAL_INLINE uint32_t SCM_HWA_GetStatus_MATRIX_STATUS6(void) +{ + return SCM->MATRIX_STATUS6; +} + +/** + * @brief clear matrix status register 6 status + * + * @u32Status Matrix status + */ +LOCAL_INLINE void SCM_HWA_Clear_MATRIX_STATUS6(uint32_t u32Status) +{ + SCM->MATRIX_STATUS6 |= u32Status & SCM_MATRIX_STATUS6_MASK; +} + +/** + * @brief Get matrix status register 7 status + * + * @return Register status + */ +LOCAL_INLINE uint32_t SCM_HWA_GetStatus_MATRIX_STATUS7(void) +{ + return SCM->MATRIX_STATUS7; +} + +/** + * @brief clear matrix status register 7 status + * + * @u32Status Matrix status + */ +LOCAL_INLINE void SCM_HWA_Clear_MATRIX_STATUS7(uint32_t u32Status) +{ + SCM->MATRIX_STATUS7 |= u32Status & SCM_MATRIX_STATUS7_MASK; +} + +/** + * @brief Get matrix ID status register status + * + * @return Register status + */ +LOCAL_INLINE uint32_t SCM_HWA_GetStatus_MATRIX_ID_STATUS0(void) +{ + return SCM->MATRIX_ID_STATUS0; +} + +/** + * @brief clear matrix ID status register status + * + * @u32Status Matrix ID status + */ +LOCAL_INLINE void SCM_HWA_Clear_MATRIX_ID_STATUS0(uint32_t u32Status) +{ + SCM->MATRIX_ID_STATUS0 |= u32Status & SCM_MATRIX_ID_STATUS0_MASK; +} + +/** + * @brief Set SCM module mailbox data out, output from device to debug + * + * @param u32Value Ouputdata value + */ +LOCAL_INLINE void SCM_HWA_SetData_MDO(uint32_t u32Value) +{ + SCM->SYSAP_MDO = u32Value; +} + +/** + * @brief Get SCM module mailbox data in, input from debug to device + * + * @return u32Value Input data value + */ +LOCAL_INLINE uint32_t SCM_HWA_GetData_MDI(void) +{ + return SCM->SYSAP_MDI; +} + +/** + * @brief Select the type of Status2 Register + * + * @param eStatus2Sel Selected Status2 type + */ +LOCAL_INLINE void SCM_HWA_Status2RegisterSelection(SCM_SysAPStatus2SelType eStatus2Sel) +{ + SCM->SYSAP_CTRL = (SCM->SYSAP_CTRL & (~(SCM_SYSAP_CTRL_STATUS2_REG_SEL_MASK))) | + SCM_SYSAP_CTRL_STATUS2_REG_SEL(eStatus2Sel); +} + +/** + * @brief Get new mailbox data input available flag, + * device read MDI regiser will automatically clear the bit + * + * @return Mailbox data input available/disable + */ +LOCAL_INLINE uint32_t SCM_HWA_GetStatus_NewMDIAvailable(void) +{ + return ((SCM->SYSAP_CTRL & (uint32_t)SCM_SYSAP_CTRL_NEW_MDI_AVAILABLE_MASK)>>(uint32_t)SCM_SYSAP_CTRL_NEW_MDI_AVAILABLE_SHIFT); +} + +/** + * @brief Control if CPU0 hold in wait at the end of reset sequence + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SetEnable_Cpu0HoldInWait(bool bEnable) +{ + SCM->SYSAP_CTRL = (SCM->SYSAP_CTRL & (~(SCM_SYSAP_CTRL_CPU0_HOLD_IN_WAIT_MASK))) | + SCM_SYSAP_CTRL_CPU0_HOLD_IN_WAIT(bEnable); +} + +/** + * @brief Control if hold CPU0 in reset at the end of reset sequence + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SetEnable_Cpu0HoldInReset(bool bEnable) +{ + SCM->SYSAP_CTRL = (SCM->SYSAP_CTRL & (~(SCM_SYSAP_CTRL_CPU0_HOLD_IN_RESET_MASK))) | + SCM_SYSAP_CTRL_CPU0_HOLD_IN_RESET(bEnable); +} + +/** + * @brief Set to force a system reset, clear the bit to release system from reset + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SetEnable_SystemReset(bool bEnable) +{ + SCM->SYSAP_CTRL = (SCM->SYSAP_CTRL & (~(SCM_SYSAP_CTRL_SYSTEM_RESET_REQ_MASK))) | + SCM_SYSAP_CTRL_SYSTEM_RESET_REQ(bEnable); +} + +/** + * @brief Set to force all CPU debug restarted, CPU to exit halt state + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SetEnable_AllCpuDebugRestart(bool bEnable) +{ + SCM->SYSAP_CTRL = (SCM->SYSAP_CTRL & (~(SCM_SYSAP_CTRL_CPU_DEBUG_RESTART_MASK))) | + SCM_SYSAP_CTRL_CPU_DEBUG_RESTART(bEnable); +} + +/** + * @brief Set to force core to halt, if core is in stop mode. + * This bit can be used to wakeup the core and transition to halt state + * + * @param eSelType Cpu type selection + */ +LOCAL_INLINE void SCM_HWA_SetSel_CpuDebugRequest(SCM_SysApCpuDebugReqType eSelType) +{ + SCM->SYSAP_CTRL = ((SCM->SYSAP_CTRL & (~(uint32_t)SCM_SYSAP_CTRL_CPU_DEBUG_REQ_MASK)) | + SCM_SYSAP_CTRL_CPU_DEBUG_REQ(eSelType)); +} + +/** + * @brief Set to disable the debug, clear to allow debug operation + * + * @param bDisable Disable/Enable + */ +LOCAL_INLINE void SCM_HWA_SetDisable_Debug(bool bDisable) +{ + SCM->SYSAP_CTRL = ((SCM->SYSAP_CTRL & (~(uint32_t)SCM_SYSAP_CTRL_DEBUG_DIS_MASK)) | + SCM_SYSAP_CTRL_DEBUG_DIS(bDisable)); +} + +/** + * @brief Set to Trigger Flash Mass Erase.Cleared by hardware after mass erase is done + * + */ +LOCAL_INLINE void SCM_HWA_TriggerFlashMassErase(void) +{ + SCM->SYSAP_CTRL |= SCM_SYSAP_CTRL_FLASH_MASS_ERASE_MASK; +} + +/** + * @brief Lock the CPU permission(WPB) in SUBSYS_PCC register, and WPB cannot be written until a power-on reset + * + */ +LOCAL_INLINE void SCM_HWA_SUBSYS_PCC_LockWritePermit(void) +{ + SCM->SUBSYS_PCC |= (uint32_t)SCM_SUBSYS_PCC_WPB_LOCK_MASK; +} + +/** + * @brief Get the lock status of CPU permission(WPB) in SUBSYS_PCC register + * + * @return 1: The WPB of SUBSYS_PCC register is locked + * 0: The WPB of SUBSYS_PCC register is not locked + */ +LOCAL_INLINE uint32_t SCM_HWA_SUBSYS_PCC_GetWPBLockStatus(void) +{ + return (SCM->SUBSYS_PCC & (uint32_t)SCM_SUBSYS_PCC_WPB_LOCK_MASK) >> SCM_SUBSYS_PCC_WPB_LOCK_SHIFT; +} + +/** + * @brief Get the CPU type of writing permission to SUBSYS_PCC register + * + * @return SCM_WPB_CpuType The CPU which has the write permission + */ +LOCAL_INLINE SCM_WPB_CpuType SCM_HWA_SUBSYS_PCC_GetCpuWritePermit(void) +{ + uint32_t u32RegVal = ((SCM->SUBSYS_PCC & (uint32_t)SCM_SUBSYS_PCC_WPB_MASK) >> SCM_SUBSYS_PCC_WPB_SHIFT); + return (SCM_WPB_CpuType)u32RegVal; +} + +/** + * @brief Set CPU to control the SUBSYS_PCC register + * + * @param eCpuType CPU allowed to control peripheral + */ +LOCAL_INLINE void SCM_HWA_SUBSYS_PCC_SetCpuWritePermit(SCM_WPB_CpuType eCpuType) +{ + SCM->SUBSYS_PCC = ((SCM->SUBSYS_PCC & (~(uint32_t)SCM_SUBSYS_PCC_WPB_MASK)) | SCM_SUBSYS_PCC_WPB(eCpuType)); +} + +/** + * @brief Get TPU clock enable/disable status + * + * @return 1: TPU clock disabled + * 0: TPU clock enabled + */ +LOCAL_INLINE uint32_t SCM_HWA_SUBSYS_PCC_GetStatus_TPUClock(void) +{ + return (SCM->SUBSYS_PCC & SCM_SUBSYS_PCC_CLKEN_TPU_MASK) >> SCM_SUBSYS_PCC_CLKEN_TPU_SHIFT; +} + +/** + * @brief Set TPU clock enable/disable + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SUBSYS_PCC_SetEnable_TPUClock(bool bEnable) +{ + SCM->SUBSYS_PCC = ((SCM->SUBSYS_PCC & (~(uint32_t)SCM_SUBSYS_PCC_CLKEN_TPU_MASK)) | + SCM_SUBSYS_PCC_CLKEN_TPU(bEnable)); +} + +/** + * @brief Get HSM clock enable/disable status + * + * @return 1: HSM clock disabled + * 0: HSM clock enabled + */ +LOCAL_INLINE uint32_t SCM_HWA_SUBSYS_PCC_GetStatus_HSMClock(void) +{ + return (SCM->SUBSYS_PCC & SCM_SUBSYS_PCC_CLKEN_HSM_ENGINE_MASK) >> SCM_SUBSYS_PCC_CLKEN_HSM_ENGINE_SHIFT; +} + +/** + * @brief Set HSM clock enable/disable + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SUBSYS_PCC_SetEnable_HSMClock(bool bEnable) +{ + SCM->SUBSYS_PCC = ((SCM->SUBSYS_PCC & (~(uint32_t)SCM_SUBSYS_PCC_CLKEN_HSM_ENGINE_MASK)) | + SCM_SUBSYS_PCC_CLKEN_HSM_ENGINE(bEnable)); +} + +/** + * @brief Get SubSystem clock enable/disable status + * + * @return 1: SubSystem clock disabled + * 0: SubSystem clock enabled + */ +LOCAL_INLINE uint32_t SCM_HWA_SUBSYS_PCC_GetStatus_SubSystemClock(void) +{ + return (SCM->SUBSYS_PCC & SCM_SUBSYS_PCC_CLKEN_SUBSYS_MASK) >> SCM_SUBSYS_PCC_CLKEN_SUBSYS_SHIFT; +} + +/** + * @brief Set SubSystem clock enable/disable + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SUBSYS_PCC_SetEnable_SubSystemClock(bool bEnable) +{ + SCM->SUBSYS_PCC = ((SCM->SUBSYS_PCC & (~(uint32_t)SCM_SUBSYS_PCC_CLKEN_SUBSYS_MASK)) | + SCM_SUBSYS_PCC_CLKEN_SUBSYS(bEnable)); +} + +/** + * @brief Set SubSystem software reset + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SUBSYS_PCC_SetEnable_SwReset(bool bEnable) +{ + SCM->SUBSYS_PCC = ((SCM->SUBSYS_PCC & (~(uint32_t)SCM_SUBSYS_PCC_SWRST_MASK)) | + SCM_SUBSYS_PCC_SWRST(bEnable)); +} + +/** + * @brief Set SubSystem watchdog reset + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SUBSYS_PCC_SetEnable_SubsysWdgReset(bool bEnable) +{ + SCM->SUBSYS_PCC = ((SCM->SUBSYS_PCC & (~(uint32_t)SCM_SUBSYS_PCC_WDG_RSTEN_MASK)) | + SCM_SUBSYS_PCC_WDG_RSTEN(bEnable)); +} + +/** + * @brief Set SubSystem stop mode request + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SUBSYS_PCC_SetEnable_SubsysStopModReq(bool bEnable) +{ + SCM->SUBSYS_PCC = ((SCM->SUBSYS_PCC & (~(uint32_t)SCM_SUBSYS_PCC_STOP_REQ_MASK)) | + SCM_SUBSYS_PCC_STOP_REQ(bEnable)); +} + +/** + * @brief Subsystem status register value + * + * @return Subsystem status register + */ +LOCAL_INLINE uint32_t SCM_HWA_GetValue_SUBSYS_STATUS(void) +{ + return SCM->SUBSYS_STATUS; +} + +/** + * @brief Get Subsystem Error Report + * + * @return Subsystem Error Report + */ +LOCAL_INLINE uint16_t SCM_HWA_GetStatus_SUBSYS_ERR(void) +{ + return (SCM->SUBSYS_STATUS & SCM_SUBSYS_STATUS_HSM_SYS_ERR_MASK) >> SCM_SUBSYS_STATUS_HSM_SYS_ERR_SHIFT; +} + +/** + * @brief Get Subsystem status + * + * @return true: Subsystem status asserted + * false: Subsystem status not asserted + */ +LOCAL_INLINE bool SCM_HWA_GetStatus_SUBSYS_STATUS(SCM_SUBSYSStatusType eStatusType) +{ + return ((SCM->SUBSYS_STATUS & (uint32_t)eStatusType) != 0U) ? true : false; +} + +/** + * @brief Get mailbox data output from device to debug flag + * + * @return Flag status + */ +LOCAL_INLINE uint32_t SCM_HWA_GetStatus_MDOFlag(void) +{ + return (SCM->MDO_FLAG & SCM_MDO_FLAG_MDO_FLAG_MASK) >> SCM_MDO_FLAG_MDO_FLAG_SHIFT; +} + +/** + * @brief Lock the CPU permission(WPB) in MASTER_HALT_REQ register, and WPB cannot be written until a power-on reset + * + */ +LOCAL_INLINE void SCM_HWA_MASTER_HALT_REQ_LockWritePermit(void) +{ + SCM->MASTER_HALT_REQ |= (uint32_t)SCM_MASTER_HALT_REQ_WPB_LOCK_MASK; +} + +/** + * @brief Get the lock status of CPU permission(WPB) in MASTER_HALT_REQ register + * + * @return 1: The WPB of MASTER_HALT_REQ register is locked + * 0: The WPB of MASTER_HALT_REQ register is not locked + */ +LOCAL_INLINE uint32_t SCM_HWA_MASTER_HALT_REQ_GetWPBLockStatus(void) +{ + return (SCM->MASTER_HALT_REQ & (uint32_t)SCM_MASTER_HALT_REQ_WPB_LOCK_MASK); +} + +/** + * @brief Get the CPU type of writing permission to MASTER_HALT_REQ register + * + * @return SCM_WPB_CpuType The CPU which has the write permission + */ +LOCAL_INLINE SCM_WPB_CpuType SCM_HWA_MASTER_HALT_REQ_GetCpuWritePermit(void) +{ + uint32_t u32RegVal = ((SCM->MASTER_HALT_REQ & (uint32_t)SCM_MASTER_HALT_REQ_WPB_MASK) >> SCM_MASTER_HALT_REQ_WPB_SHIFT); + return (SCM_WPB_CpuType)u32RegVal; +} + +/** + * @brief Set CPU to control the MASTER_HALT_REQ register + * + * @param eCpuType CPU allowed to control peripheral + */ +LOCAL_INLINE void SCM_HWA_MASTER_HALT_REQ_SetCpuWritePermit(SCM_WPB_CpuType eCpuType) +{ + SCM->MASTER_HALT_REQ = ((SCM->MASTER_HALT_REQ & (~(uint32_t)SCM_MASTER_HALT_REQ_WPB_MASK)) | + SCM_MASTER_HALT_REQ_WPB(eCpuType)); +} + +/** + * @brief Set MASTER_HALT_REQ halt request + * + * @param eHaltReq halt request defined in SCM_HaltReqType + */ +LOCAL_INLINE void SCM_HWA_SetSel_MASTER_HALT_REQ(SCM_HaltReqType eHaltReq) +{ + SCM->MASTER_HALT_REQ |= (uint32_t)1U << ((uint32_t)eHaltReq * 8U); +} + +/** + * @brief Get MASTER_HALT_ACK halt ACK status + * + * @return SCM_HaltReqAckType Ack status + */ +LOCAL_INLINE SCM_HaltReqAckType SCM_HWA_GetStatus_MASTER_HALT_ACK(SCM_HaltReqType eHaltReq) +{ + uint32_t u32RegVal = (SCM->MASTER_HALT_ACK >> ((uint32_t)eHaltReq * 8U)) & 0x7U; + return (SCM_HaltReqAckType)u32RegVal; +} + +/** + * @brief Set CPU0 NMI interrupt router enable/disable + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SetEnable_Cpu0NMIIrqRouter(bool bEnable) +{ + SCM->INT_ROUTER_NMI = (SCM->INT_ROUTER_NMI & (~(SCM_INT_ROUTER_NMI_C0_EN_MASK))) | + SCM_INT_ROUTER_NMI_C0_EN(bEnable); +} + +/** + * @brief Lock SCM_INT_ROUTER_NMI register + * + */ +LOCAL_INLINE void SCM_HWA_LockINT_ROUTER_NMI(void) +{ + SCM->INT_ROUTER_NMI |= (uint32_t)SCM_INT_ROUTER_NMI_LOCK_MASK; +} + +/** + * @brief Get SCM_INT_ROUTER_NMI register lock status + * + * @return Lock status + */ +LOCAL_INLINE uint32_t SCM_HWA_INT_ROUTER_NMI_GetLockStatus(void) +{ + return (SCM->INT_ROUTER_NMI & (uint32_t)SCM_INT_ROUTER_NMI_LOCK_MASK) >> SCM_INT_ROUTER_NMI_LOCK_SHIFT; +} + +/** + * @brief Get CRC done Flag + * + * @return CRC done Flag + */ +LOCAL_INLINE uint32_t SCM_HWA_GetStatus_CrcDoneFlag(void) +{ + return((SCM->CRCCSR & (uint32_t)SCM_CRCCSR_DONE_MASK)>>(uint32_t)SCM_CRCCSR_DONE_SHIFT); +} + +/** + * @brief Get CRC Error Flag + * + * @return CRC Error Flag + */ +LOCAL_INLINE uint32_t SCM_HWA_GetStatus_CrcErrFlag(void) +{ + return((SCM->CRCCSR & (uint32_t)SCM_CRCCSR_ERR_MASK)>>(uint32_t)SCM_CRCCSR_ERR_SHIFT); +} + +/** + * @brief Clear CRC error flag + */ +LOCAL_INLINE void SCM_HWA_ClearCrcErrorFlag(void) +{ + SCM->CRCCSR |= (uint32_t)SCM_CRCCSR_ERR_MASK; +} + +/** + * @brief Get CRC Busy Flag + * + * @return CRC Busy Flag + */ +LOCAL_INLINE uint32_t SCM_HWA_GetStatus_CrcBusyFlag(void) +{ + return((SCM->CRCCSR & (uint32_t)SCM_CRCCSR_BUY_MASK)>>(uint32_t)SCM_CRCCSR_BUY_SHIFT); +} + +/** + * @brief Set CRC error out enable/disable + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SetEnable_CrcErrOut(bool bEnable) +{ + SCM->CRCCSR = (SCM->CRCCSR & (~(SCM_CRCCSR_EOEN_MASK))) | SCM_CRCCSR_EOEN(bEnable); +} + +/** + * @brief Set CRC check enable/disable + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SetEnable_CrcCheck(bool bEnable) +{ + SCM->CRCCSR = (SCM->CRCCSR & (~(SCM_CRCCSR_CHKEN_MASK))) | SCM_CRCCSR_CHKEN(bEnable); +} + +/** + * @brief Set CRC trigger enable/disable + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SetEnable_CrcTrigger(bool bEnable) +{ + SCM->CRCCSR = (SCM->CRCCSR & (~(SCM_CRCCSR_TRGEN_MASK))) | SCM_CRCCSR_TRGEN(bEnable); +} + +/** + * @brief Set CRC software generate enable/disable + * + * @param bEnable Enable/Disable + */ +LOCAL_INLINE void SCM_HWA_SetEnable_CrcSwGen(bool bEnable) +{ + SCM->CRCCSR = (SCM->CRCCSR & (~(SCM_CRCCSR_GEN_MASK))) | SCM_CRCCSR_GEN(bEnable); +} + +/** + * @brief Get CRC result + * + * @return CRC result + */ +LOCAL_INLINE uint32_t SCM_HWA_GetCrcResult(void) +{ + return SCM->CRCRES; +} + + + + +#endif /*#ifndef _HWA_SCM_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_sec.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_sec.h new file mode 100644 index 0000000..2e4752a --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_sec.h @@ -0,0 +1,859 @@ +/** + * @file HwA_sec.h + * @author Flagchip + * @brief FC7xxx sec hardware access layer + * @version 0.2.0 + * @date 2023-2-7 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.2.0 2023-2-7 Flagchip076 N/A First version for FC7300 + ******************************************************************************** */ + +#ifndef HWA_INCLUDE_HWA_SEC_H_ +#define HWA_INCLUDE_HWA_SEC_H_ +#include "device_header.h" + +/** + * @addtogroup HwA_SEC + * @{ + * + */ + +/* DEN Bit Fields */ +/** + *@brief Enable the debug module + * */ +LOCAL_INLINE void SEC_HWA_EnDebug(void) +{ + SEC->DEN = SEC_DEN_DEN(0X5) ; +} + +/* FSEC0 Bit Fields */ +/** + * @brief Get the system security KEY0 + * */ +LOCAL_INLINE uint16_t SEC_HWA_GetSScontrol0(void) +{ + return (uint16_t)((SEC->FSEC0) & (SEC_FSEC0_SSC0_MASK)); +} + +/* FSEC1 Bit Fields */ +/** + * @brief Get the system security KEY1 + * */ +LOCAL_INLINE uint16_t SEC_HWA_GetSScontrol1(void) +{ + return (uint16_t)((SEC->FSEC1) & (SEC_FSEC1_SSC1_MASK)); +} + +/* DCWOR Bit Fields */ +/** + * @brief Re-enable the Debug mode. + * @note This register can only be write once. startup_fc4150.s has lock the register. + * */ +LOCAL_INLINE void SEC_HWA_ReEnDebug(void) +{ + SEC->DCWOR = ((SEC->DCWOR & (~SEC_DCWOR_DEA_MASK)) | SEC_DCWOR_DEA(0X5)); +} + +/** + * @brief Get the Re-enable Debug permission. + * */ +LOCAL_INLINE bool SEC_HWA_GetReEnDebug(void) +{ + bool ret = false; + uint8_t dea = (uint8_t)((SEC->DCWOR & (SEC_DCWOR_DEA_MASK)) >> SEC_DCWOR_DEA_SHIFT); + if (dea == 0x5U) + { + ret = true; + } + return ret; +} + +/** + * @brief Enable the write operation for SEC register. + * @note This register can only be write once. startup_fc4150.s has lock the register. + * */ +LOCAL_INLINE void SEC_HWA_WriteUnlock(void) +{ + SEC->DCWOR = ((SEC->DCWOR & (~SEC_DCWOR_RWL_MASK)) | SEC_DCWOR_RWL(0X5)); +} + +/** + * @brief Get the sec write permission + * @return true means allow write. false means forbid write. +*/ +LOCAL_INLINE bool SEC_HWA_GetWritePer(void) +{ + bool ret = false; + uint8_t rwl = (uint8_t)((SEC->DCWOR & (SEC_DCWOR_RWL_MASK)) >> SEC_DCWOR_RWL_SHIFT); + if ((rwl == 0x5U) || (rwl == 0xFU)) + { + ret = true; + } + return ret; +} + +/* DEK Bit Fields */ +/** + * @brief Enable the write operation for SEC register. + * */ +LOCAL_INLINE void SEC_HWA_ChangeDBK(uint8_t count, uint32_t key) +{ + + SEC->DEK[count] = SEC_DEK_DEK(key) ; + +} + +/* TME Bit Fields */ +/** + *@brief Enable the Test module + * */ +LOCAL_INLINE void SEC_HWA_EnTest(void) +{ + SEC->TME = SEC_TME_TME(0X5) ; +} + +/* TMEA Bit Fields */ +/** + * @brief Re-Enable Test mode + * */ +LOCAL_INLINE void SEC_HWA_ReEnTest(void) +{ + SEC->TMEA = SEC_TMEA_TMEA(0X5) ; +} + +/** + * @brief Get the Re-enable Test permission. + * */ +LOCAL_INLINE bool SEC_HWA_GetReEnTest(void) +{ + bool ret = false; + uint8_t tmea = (uint8_t)((SEC->TMEA & (SEC_TMEA_TMEA_MASK)) >> SEC_TMEA_TMEA_SHIFT); + if ((tmea == 0x5U) || (tmea == 0xFU)) + { + ret = true; + } + return ret; +} + +/* TMEK Bit Fields */ +/** + *@brief write Test re-enable mode key + * + */ +LOCAL_INLINE void SEC_HWA_ReEnTestKey(uint32_t testkey) +{ + SEC->TMEK = SEC_TMEK_TMEK(testkey) ; +} + +/* FCR0 Bit Fields */ +/** + * @brief Enable the Mass Erase + */ +LOCAL_INLINE void SEC_HWA_EnME(void) +{ + SEC->FCR0 = ((SEC->FCR0 & (~SEC_FCR0_MED_MASK)) | SEC_FCR0_MED(0x5)); +} + +/** + * @brief Enable the Block 0 NVR write . + */ +LOCAL_INLINE void SEC_HWA_EnWriteB0NVR(void) +{ + SEC->FCR0 = ((SEC->FCR0 & (~SEC_FCR0_NWP_MASK)) | SEC_FCR0_NWP(0x5)) ; +} + +/** + * @brief Disable the Block 0 NVR write . + */ +LOCAL_INLINE void SEC_HWA_DisWriteB0NVR(void) +{ + SEC->FCR0 = ((SEC->FCR0 & (~SEC_FCR0_NWP_MASK)) | SEC_FCR0_NWP(0xA)) ; +} + +/** + * @brief Enable the Block 0 NVR erase . + */ +LOCAL_INLINE void SEC_HWA_EnEraseB0NVR(void) +{ + SEC->FCR0 = ((SEC->FCR0 & (~SEC_FCR0_NEP_MASK)) | SEC_FCR0_NEP(0x5)) ; +} + +/** + * @brief Disable the Block 0 NVR erase . + */ +LOCAL_INLINE void SEC_HWA_DisEraseB0NVR(void) +{ + SEC->FCR0 = ((SEC->FCR0 & (~SEC_FCR0_NEP_MASK)) | SEC_FCR0_NEP(0xA)) ; +} + +/* NKRP Bit Fields */ +/** + * @brief NVR Key Read Protection. + * @brief Enable the Block 0 NVR read. + */ +LOCAL_INLINE void SEC_HWA_EnReadB0NVR(void) +{ + SEC->FCR0 = ((SEC->NKRP & (~SEC_NKRP_NKRP_MASK)) | SEC_NKRP_NKRP(0x5)) ; +} + +/** + * @brief Disable the Block 0 NVR read . + */ +LOCAL_INLINE void SEC_HWA_DisReadB0NVR(void) +{ + SEC->FCR0 = ((SEC->FCR0 & (~SEC_NKRP_NKRP_MASK)) | SEC_NKRP_NKRP(0xA)) ; +} + + +/* BCS Bit Fields */ +/** + * @brief Get the Fast Boot Select. + * @return 0b - Select PLL0 as the core clock source; the core clock is 300MHz + * 1b - Select FIRC as the core clock source; the core clock is 96MHz. + * */ +LOCAL_INLINE uint8_t SEC_HWA_GetFastBootClock(void) +{ + return (uint8_t)((SEC->BCS & SEC_BCS_FBS_MASK) >> SEC_BCS_FBS_SHIFT); +} + +/** + * @brief NMI Function Enable/Disable + * @return false - NMI pin function is disabled after reset. + * true - NMI pin function is enabled + * */ +LOCAL_INLINE bool SEC_HWA_GetNmiPin(void) +{ + return (bool)((SEC->BCS & SEC_BCS_NMIDIS_MASK) >> SEC_BCS_NMIDIS_SHIFT); +} + +/** + * @brief ISP Function Enable/Disable ISP Mode Status + * @return false - ISP mode is inactive. + * true - ISP mode is active. + * */ +LOCAL_INLINE bool SEC_HWA_GetIspStatus(void) +{ + return (bool)((SEC->BCS & SEC_BCS_ISPMODE_MASK) >> SEC_BCS_ISPMODE_SHIFT); +} + +/** + * @brief Boot Rom Configuration + * @return false - Boot from GPR defined address (except ROM). + * true - Boot from ROM. + * */ +LOCAL_INLINE bool SEC_HWA_GetBootRom(void) +{ + return (bool)((SEC->BCS & SEC_BCS_BOOTROM_MASK) >> SEC_BCS_BOOTROM_SHIFT); +} + +/** + * @brief Get Chip Part Mode + * @return false - Chip is in FlexCore part mode. + * true - Chip is in HSM part mode. + * */ +LOCAL_INLINE bool SEC_HWA_GetPartMode(void) +{ + return (bool)((SEC->BCS & SEC_BCS_PART_MODE_MASK) >> SEC_BCS_PART_MODE_SHIFT); +} + +/** + * @brief Get PF_128BIT_MODE + * @return false - Chip is in FlexCore part mode. + * true - Chip is in HSM part mode. + * */ +LOCAL_INLINE bool SEC_HWA_GetPF128BitMode(void) +{ + return (bool)((SEC->BCS & SEC_BCS_PF_128BIT_MODE_MASK) >> SEC_BCS_PF_128BIT_MODE_SHIFT); +} + +/* UKAC Bit Fields */ + +/** + * @brief User Key Access Enable. Only valid under non-secure boot + * @return true means User key can be read/programmed/erased by host CPU ,false means User key is not available for host cpu + * */ +LOCAL_INLINE bool SEC_HWA_GetUKAS(void) +{ + bool ret = false; + uint8_t uake =(uint8_t)((SEC->UKAC & SEC_UKAC_UKAE_MASK) >> SEC_UKAC_UKAE_SHIFT); + if ((uake == 0x5U) || (uake == 0xFU)) + { + ret = true; + } + return ret; +} + +/* BRC0 Bit Fields */ +/** + * @brief Secure Boot Disable (Value loaded from NVR sector) + * @return true means Secure boot mode , false means Non secure boot mode. + */ +LOCAL_INLINE bool SEC_HWA_GetSB(void) +{ + bool ret = false; + uint8_t sbdis = (uint8_t)((SEC->BRC0 & SEC_BRC0_SECURE_BOOT_DIS_MASK) >> SEC_BRC0_SECURE_BOOT_DIS_SHIFT); + if (sbdis == 0x0u) + { + ret = true; + } + return ret; +} + +/** + * @brief Host Debug Auth Enable. Only valid in secure boot. (Value loaded from NVR sector) + * @return true means Host debug authentication enable. false means Host debug authentication disable. + */ +LOCAL_INLINE bool SEC_HWA_GetDEAUEn(void) +{ + bool ret = false; + uint8_t dean = (uint8_t)((SEC->BRC0 & SEC_BRC0_DEBUG_AUTH_EN_MASK) >> SEC_BRC0_DEBUG_AUTH_EN_SHIFT); + if ((dean == 0x5u) || (dean == 0xFu)) + { + ret = true; + } + return ret; +} + +/** + * @brief ISP Auth Enable. Only valid in secure boot. (Value loaded from NVR sector) + * @return true means ISP authentication enable, false means ISP authentication disable. + */ +LOCAL_INLINE bool SEC_HWA_GetISPAU(void) +{ + bool ret = false; + uint8_t isp = (uint8_t)((SEC->BRC0 & SEC_BRC0_ISP_AUTH_EN_MASK) >> SEC_BRC0_ISP_AUTH_EN_SHIFT); + if ((isp == 0x5u) || (isp == 0xFu)) + { + ret = true; + } + return ret; +} + +/* BRC1 Bit Fields */ +/** + * @brief Get the FCUART Baud Rate for ISP + * @return FCUART Baud Rate for ISP + * */ +LOCAL_INLINE uint8_t SEC_HWA_GetUartBR(void) +{ + return (uint8_t)((SEC->BRC1 & SEC_BRC1_UARTBR_MASK) >> SEC_BRC1_UARTBR_SHIFT); +} + +/** + * @brief Get CAN Baud Rate for ISP + * @return CAN Baud Rate for ISP + * */ +LOCAL_INLINE uint8_t SEC_HWA_GetCanBR(void) +{ + return (uint8_t)((SEC->BRC1 & SEC_BRC1_CANBR_MASK) >> SEC_BRC1_CANBR_SHIFT); +} + +/** + * @brief Get OSC Frequency + * @return OSC Frequency + * */ +LOCAL_INLINE uint8_t SEC_HWA_GetOSCFre(void) +{ + return (uint8_t)((SEC->BRC1 & SEC_BRC1_OSCFREQ_MASK) >> SEC_BRC1_OSCFREQ_SHIFT); +} + +/** + * @brief Get whether OSC Available. + * @return true means OSC is available. false means -OSC is not available + * */ +LOCAL_INLINE bool SEC_HWA_GetOSCAvail(void) +{ + bool ret = false; + uint8_t osc = (uint8_t)((SEC->BRC1 & SEC_BRC1_OSCA_MASK) >> SEC_BRC1_OSCA_SHIFT); + if (osc == 0x0U) + { + ret = true; + } + return ret; +} + +/** + * @brief Get Debug Backdoor Key Input Enable. + * @return + * 0011b - User can input DBK through debug mailbox, ISP is not valid + * 1100b - User can input DBK through ISP, debug mailbox is not valid. + * 1111b - User can input DBK through both debug mailbox and ISP. + * Other Values - User cannot input DBK through both debug mailbox andISP + * */ +LOCAL_INLINE uint32_t SEC_HWA_GetMBBKEN(void) +{ + return (uint32_t)((SEC->BRC1 & SEC_BRC1_DBK_IN_EN_MASK) >> SEC_BRC1_DBK_IN_EN_SHIFT); +} + +/** + * @brief Get Debug Backdoor Key Encryption Algorithm + * @return false-User code verification enable in non-secure boot mode + true- User code verification disable in non-secure boot mode. + * */ +LOCAL_INLINE bool SEC_HWA_GetNonSecVerifEN(void) +{ + bool ret = false; + uint8_t dean = (uint8_t)((SEC->BRC0 & SEC_BRC1_NON_SEC_VERIF_EN_MASK) >> SEC_BRC1_NON_SEC_VERIF_EN_SHIFT); + if (dean == 1u) + { + ret = true; + } + return ret; +} + +/** + * @brief Get User Code Verification Enable under Non-secure Boot Mode + * @return Bootloader Verification Algorithm + * 000b - AES256-CBC + * 111b - SM4-CBC. + * */ +LOCAL_INLINE uint8_t SEC_HWA_GetDBDkeyEncrypAlg(void) +{ + return (uint8_t)((SEC->BRC1 & SEC_BRC1_DBKEA_MASK) >> SEC_BRC1_DBKEA_SHIFT); +} + +/** + * @brief ISP Function Enable/Disable，Only valid in non-secure mode + * @return false - ISP pin function is disabled after reset. + * true - ISP pin function is enabled. + * */ +LOCAL_INLINE bool SEC_HWA_GetIspEn(void) +{ + return (bool)((SEC->BRC1 & SEC_BRC1_ISP_PIN_EN_MASK) >> SEC_BRC1_ISP_PIN_EN_SHIFT); +} + +/** + * @brief GET ISP Mode whether Allowed in Recovery Mode + * @return false - ISP mode is not allowed in recovery mode + * true - ISP mode is allowed in recovery mode. + * */ +LOCAL_INLINE bool SEC_HWA_GetIspIsAllowedInRec(void) +{ + return (bool)((SEC->BRC1 & SEC_BRC1_ISPAIRM_MASK) >> SEC_BRC1_ISPAIRM_SHIFT); +} + +/** + * @brief GET Enable the Output of Plaintext Decrypted ROOT Key + * @return false - The output of plaintext decrypted ROOT key is enabled + * true - The output of plaintext decrypted ROOT key is disabled. + * */ +LOCAL_INLINE bool SEC_HWA_GetKeyPlaRoot(void) +{ + return (bool)((SEC->BRC1 & SEC_BRC1_KEY_PROT_MASK) >> SEC_BRC1_KEY_PROT_SHIFT); +} + +/** + * @brief Get ROM Loop Control Flag + * @return false - ROM executes normal run under VIRGIN and FT state. + * true - ROM enters debug loop under VIRGIN and FT state. + * */ +LOCAL_INLINE bool SEC_HWA_GetLoopCtrFlag(void) +{ + return (bool)((SEC->BRC1 & SEC_BRC1_ROM_LOOP_CTRL_MASK) >> SEC_BRC1_ROM_LOOP_CTRL_SHIFT); +} + +/** + * @brief Get Enable Software Configuration to Enter ISP + * @return false - Software configuration to enter ISP is enabled. + * true - Software configuration to enter ISP is disabled. + * */ +LOCAL_INLINE bool SEC_HWA_GetIspSoftConfig(void) +{ + return (bool)((SEC->BRC1 & SEC_BRC1_SW_CFG_ISP_EN_MASK) >> SEC_BRC1_SW_CFG_ISP_EN_SHIFT); +} + + +/* SW_CFG_ISP_FLG Bit Fields */ +/** + * @brief Software Configuration to Enter ISP Flag + * @return ISP Flag. + * */ +LOCAL_INLINE uint8_t SEC_HWA_GetSwCfgIspFlg(void) +{ + return (uint8_t)((SEC->SW_CFG_ISP_FLG & SEC_SW_CFG_ISP_FLG_SW_CFG_ISP_FLG_MASK) >> SEC_SW_CFG_ISP_FLG_SW_CFG_ISP_FLG_SHIFT); +} + + +/* BRC2 Bit Fields */ +/** + * @brief Get USERCODE_VERIFY_MASK_MASK + * @return USERCODE_VERIFY_MASK_MASK. + * */ +LOCAL_INLINE uint32_t SEC_HWA_GetBLMask(void) +{ + return (uint32_t)((SEC->BRC2 & SEC_BRC2_USERCODE_VERIFY_MASK_MASK) >> SEC_BRC2_USERCODE_VERIFY_MASK_SHIFT); +} + +/** + * @brief Get the ISP Instance Select. + * @return ISP Instance Select + * */ +LOCAL_INLINE uint8_t SEC_HWA_GetIspIns(void) +{ + return (uint8_t)((SEC->BRC2 & SEC_BRC2_ISP_INST_SEL_MASK) >> SEC_BRC2_ISP_INST_SEL_SHIFT); +} + +/** + * @brief Get Bootloader Verification Algorithm + * @return Bootloader Verification Algorithm + * */ +LOCAL_INLINE uint8_t SEC_HWA_GetBLVer(void) +{ + return (uint8_t)((SEC->BRC2 & SEC_BRC2_USERCODE_VERIFICATION_ALG_MASK) >> SEC_BRC2_USERCODE_VERIFICATION_ALG_SHIFT); +} + +/** + * @brief Get Debug/ISP/PREFA Authentication and USRK decryption algorithm + * @return 1b - SM2, 0b - ECC256 + * */ +LOCAL_INLINE uint8_t SEC_HWA_GetDecrypt(void) +{ + return (uint8_t)((SEC->BRC2 & SEC_BRC2_DECRP_ALG_MASK) >> SEC_BRC2_DECRP_ALG_SHIFT); +} + +/* IMAGEA Bit Fields */ +/** + * @brief Get the bootloader address. + * @return Bootloader Address. + * */ +LOCAL_INLINE uint32_t SEC_HWA_GetBLAddr(void) +{ + return (uint32_t)((SEC->IMGEA & SEC_IMGEA_IMAGE_ADDR_MASK) >> SEC_IMGEA_IMAGE_ADDR_SHIFT); +} + + +/* NVR VER Bit Fields */ +/** + * @brief Get C version. + * @return C version. + * */ +LOCAL_INLINE uint32_t SEC_HWA_GetCVer(void) +{ + return (uint32_t)((SEC->NVR_VER & SEC_NVR_VER_C_VER_MASK) >> SEC_NVR_VER_C_VER_SHIFT); +} + +/** + * @brief Set C version. + * @return C version. + * */ +LOCAL_INLINE void SEC_HWA_SetCVer(uint32_t C_Ver) +{ + SEC->NVR_VER=((SEC->NVR_VER & (~SEC_NVR_VER_C_VER_MASK)) | SEC_NVR_VER_C_VER(C_Ver)); +} + +/** + * @brief Get R version. + * @return R version. + * */ +LOCAL_INLINE uint32_t SEC_HWA_GetRVer(void) +{ + return (uint32_t)((SEC->NVR_VER & SEC_NVR_VER_R_VER_MASK) >> SEC_NVR_VER_R_VER_SHIFT); +} + +/** + * @brief Set R version. + * */ +LOCAL_INLINE void SEC_HWA_SetRVer(uint32_t R_Ver) +{ + SEC->NVR_VER=((SEC->NVR_VER & (~SEC_NVR_VER_R_VER_MASK)) | SEC_NVR_VER_R_VER(R_Ver)); +} + +/** + * @brief Get V version. + * @return V version. + * */ +LOCAL_INLINE uint32_t SEC_HWA_GetVVer(void) +{ + return (uint32_t)((SEC->NVR_VER & SEC_NVR_VER_V_VER_MASK) >> SEC_NVR_VER_V_VER_SHIFT); +} + +/** + * @brief Set V version. + * */ +LOCAL_INLINE void SEC_HWA_SetVVer(uint32_t V_Ver) +{ + SEC->NVR_VER=((SEC->NVR_VER & (~SEC_NVR_VER_V_VER_MASK)) | SEC_NVR_VER_V_VER(V_Ver)); +} + +/** + * @brief Get CHIP version. + * @return CHIP version. + * */ +LOCAL_INLINE uint32_t SEC_HWA_GetChipVer(void) +{ + return (uint32_t)((SEC->NVR_VER & SEC_NVR_VER_CHIP_VER_MASK) >> SEC_NVR_VER_CHIP_VER_SHIFT); +} + +/** + * @brief Set CHIP version. + * */ +LOCAL_INLINE void SEC_HWA_SetChipVer(uint32_t CHIP_Ver) +{ + SEC->NVR_VER=((SEC->NVR_VER & (~SEC_NVR_VER_CHIP_VER_MASK)) | SEC_NVR_VER_V_VER(CHIP_Ver)); +} + +/* LCSTAT Bit Fields */ +/** + * @brief Get the life cycle status of the chip. + * @return The lifecycle status + * */ +LOCAL_INLINE uint8_t SEC_HWA_GetLCStaus(void) +{ + return (uint8_t)(SEC->LCSTAT & 0XFFU); +} + +/** + * @brief Get Lifecycle OEM Development + * @return 0b - Chip is not in this lifecycle + * 1b - Chip is in this lifecycle + * */ +LOCAL_INLINE bool SEC_HWA_GetLCOemDev(void) +{ + return (bool)((SEC->LCSTAT & SEC_LCSTAT_LIFECYCLE_OEM_DEV_MASK) >> SEC_LCSTAT_LIFECYCLE_OEM_DEV_SHIFT); +} + +/** + * @brief Get Lifecycle OEM Production + * @return false - Chip is not in this lifecycle + * true - Chip is in this lifecycle + * */ +LOCAL_INLINE bool SEC_HWA_GetLCOemPdt(void) +{ + return (bool)((SEC->LCSTAT & SEC_LCSTAT_LIFECYCLE_OEM_PDT_MASK) >> SEC_LCSTAT_LIFECYCLE_OEM_PDT_SHIFT); +} + +/** + * @brief Get Lifecycle In Field + * @return false - Chip is not in this lifecycle + * true - Chip is in this lifecycle + * */ +LOCAL_INLINE bool SEC_HWA_GetLCInField(void) +{ + return (bool)((SEC->LCSTAT & SEC_LCSTAT_LIFECYCLE_IN_FIELD_MASK) >> SEC_LCSTAT_LIFECYCLE_IN_FIELD_SHIFT); +} + +/** + * @brief Get Lifecycle Software Fault Analysis + * @return false - Chip is not in this lifecycle + * true - Chip is in this lifecycle + * */ +LOCAL_INLINE bool SEC_HWA_GetLCSwFa(void) +{ + return (bool)((SEC->LCSTAT & SEC_LCSTAT_LIFECYCLE_SWFA_MASK) >> SEC_LCSTAT_LIFECYCLE_SWFA_SHIFT); +} + +/** + * @brief Get Lifecycle Hardware Fault Analysis + * @return false - Chip is not in this lifecycle + * true - Chip is in this lifecycle + * */ +LOCAL_INLINE bool SEC_HWA_GetLCHwFa(void) +{ + return (bool)((SEC->LCSTAT & SEC_LCSTAT_LIFECYCLE_HWFA_MASK) >> SEC_LCSTAT_LIFECYCLE_HWFA_SHIFT); +} + +/* FAC Bit Fields */ +/** + * @brief Get the Host User Key Read Protection + * @return true - Host read access to User Key region is enabled + * false - Host read access to User Key region is disabled + * */ +LOCAL_INLINE bool SEC_HWA_GetHUKRead(void) +{ + return (bool)(~(((SEC->FAC) & SEC_FAC_HOST_UKEY_RPROT_MASK) >> SEC_FAC_HOST_UKEY_RPROT_SHIFT)); +} + +/** + * @brief Get the Host User Key write Protection + * @return true - Host write access to User Key region is enabled + * false - Host write access to User Key region is disabled + * */ +LOCAL_INLINE bool SEC_HWA_GetHUKWrite(void) +{ + return (bool)(~(((SEC->FAC) & SEC_FAC_HOST_UKEY_WPROT_MASK) >> SEC_FAC_HOST_UKEY_WPROT_SHIFT)); +} + +/** + * @brief Get the Host User Key erase Protection + * @return true - Host erase access to User Key region is enabled + * false - Host erase access to User Key region is disabled + * */ +LOCAL_INLINE bool SEC_HWA_GetHUKErase(void) +{ + return (bool)(~(((SEC->FAC) & SEC_FAC_HOST_UKEY_EPROT_MASK) >> SEC_FAC_HOST_UKEY_EPROT_SHIFT)); +} + +/** + * @brief Get the Host NVR Read Protection + * @return true - Host read access to NVR region is enabled + * false - Host read access to NVR region is disabled + * */ +LOCAL_INLINE bool SEC_HWA_GetHostNvrRead(void) +{ + return (bool)(~(((SEC->FAC) & SEC_FAC_HOST_NVR_RPROT_MASK) >> SEC_FAC_HOST_NVR_RPROT_SHIFT)); +} + +/** + * @brief Get the Host NVR write Protection + * @return true - Host write access to NVR region is enabled + * false - Host write access to NVR region is disabled + * */ +LOCAL_INLINE bool SEC_HWA_GetHostNvrWrite(void) +{ + return (bool)(~(((SEC->FAC) & SEC_FAC_HOST_NVR_WPROT_MASK) >> SEC_FAC_HOST_NVR_WPROT_SHIFT)); +} + +/** + * @brief Get the Host NVR erase Protection + * @return true - Host erase access to NVR region is enabled + * false - Host erase access to NVR region is disabled- + * */ +LOCAL_INLINE bool SEC_HWA_GetHostNvrErase(void) +{ + return (bool)(~(((SEC->FAC) & SEC_FAC_HOST_NVR_EPROT_MASK) >> SEC_FAC_HOST_NVR_EPROT_SHIFT)); +} + +/** + * @brief Get HSM User Key Read Protection + * @return true - HSM Read access to User Key region is disabled + * false - HSM Read access to User Key region is enabled + * */ +LOCAL_INLINE bool SEC_HWA_GetHsmUKRead(void) +{ + return (bool)(~(((SEC->FAC) & SEC_FAC_HSM_UKEY_RPROT_MASK) >> SEC_FAC_HSM_UKEY_RPROT_SHIFT)); +} + +/** + * @brief Get HSM User Key Program Protection + * @return true - HSM Program access to User Key region is disabled + * false - HSM Program access to User Key region is enabled + * */ +LOCAL_INLINE bool SEC_HWA_GetHsmUKProg(void) +{ + return (bool)(~(((SEC->FAC) & SEC_FAC_HSM_UKEY_WPROT_MASK) >> SEC_FAC_HSM_UKEY_WPROT_SHIFT)); +} + +/** + * @brief Get the HSM User Key Erase Protection + * @return true - HSM erase access to User Key region is enabled + * false -HSM erase access to User Key region is disabled + * */ +LOCAL_INLINE bool SEC_HWA_GetHsmUKErase(void) +{ + return (bool)(~(((SEC->FAC) & SEC_FAC_HSM_UKEY_EPROT_MASK) >> SEC_FAC_HSM_UKEY_EPROT_SHIFT)); +} + +/** + * @brief Get HSM NVR Key Read Protection + * @return true - HSM Read access to NVR key region is disabled + * false - HSM Read access to NVR key region is enabled + * */ +LOCAL_INLINE bool SEC_HWA_GetHsmNvrKRead(void) +{ + return (bool)(~(((SEC->FAC) & SEC_FAC_HSM_NVR_RPROT_MASK) >> SEC_FAC_HSM_NVR_RPROT_SHIFT)); +} + +/** + * @brief Get HSM NVR Program Protection + * @return true - HSM Program access to NVR region is disabled + * false - HSM Program access to NVR region is enabled + * */ +LOCAL_INLINE bool SEC_HWA_GetHsmNvrProg(void) +{ + return (bool)(~(((SEC->FAC) & SEC_FAC_HSM_NVR_WPROT_MASK) >> SEC_FAC_HSM_NVR_WPROT_SHIFT)); +} + +/** + * @brief Get the HSM NVR Erase Protection + * @return true - HSM erase access to NVR region is enabled + * false -HSM erase access to NVR region is disabled + * */ +LOCAL_INLINE bool SEC_HWA_GetHsmNvrErase(void) +{ + return (bool)(~(((SEC->FAC) & SEC_FAC_HSM_NVR_EPROT_MASK) >> SEC_FAC_HSM_NVR_EPROT_SHIFT)); +} + +/* FLEXCORE_EN Bit Fields */ +/** + * @brief Get the FlexCore Enable. + * @return true means enable ,false means disable. + * */ +LOCAL_INLINE bool SEC_HWA_GetFlexCoreEn(void)//? +{ + bool ret = false; + uint8_t srk = (uint8_t)((SEC->FLEXCORE_EN & SEC_FLEXCORE_EN_FLEXCORE_EN_MASK) >> SEC_FLEXCORE_EN_FLEXCORE_EN_SHIFT); + if (srk == 0xFU||srk == 0x5U) + { + ret = true; + } + return ret; +} +/** + * @brief Set the FlexCore Enable. + * @return true means set sucess ,false means set fail,0x5 and 0xf is enable,others is disable. + * */ +LOCAL_INLINE bool SEC_HWA_SetFlexCoreEn(uint8_t CoreEn) +{ + if(CoreEn>0xF) + return false; + SEC->FLEXCORE_EN = ((SEC->FLEXCORE_EN & (~SEC_FLEXCORE_EN_FLEXCORE_EN_MASK)) | SEC_FLEXCORE_EN_FLEXCORE_EN(CoreEn)); + return true; +} + +/** + * @brief Get SEC_FLEXCORE_EN FLEXCORE_DBG. + * @return true means enable ,false means disable. + * */ +LOCAL_INLINE bool SEC_HWA_GetFlexCoreDbgEn(void) +{ + return (bool)((SEC->FLEXCORE_EN & SEC_FLEXCORE_EN_FLEXCORE_DBG_EN_MASK) >> SEC_FLEXCORE_EN_FLEXCORE_DBG_EN_SHIFT); +} + +/** + * @brief Set SEC_FLEXCORE_EN FLEXCORE_DBG. + * */ +LOCAL_INLINE void SEC_HWA_SetFlexCoreDbgEn(uint8_t DbgEn) +{ + SEC->FLEXCORE_EN=((SEC->FLEXCORE_EN & (~SEC_FLEXCORE_EN_FLEXCORE_DBG_EN_MASK)) | SEC_FLEXCORE_EN_FLEXCORE_DBG_EN(DbgEn)); +} + +/* FLEX_CODE_ADDR Bit Fields */ +/** + * @brief Get Code Header Address for FlexCore Always 4-byte aligned + * @return FLEX Code Header Address. + * */ +LOCAL_INLINE uint32_t SEC_HWA_GetFlexCodeHeadAddr(void) +{ + return (uint32_t)((SEC->FLEX_CODE_ADDR & SEC_FLEX_CODE_ADDR_FLEX_CODE_ADDR_MASK) >> SEC_FLEX_CODE_ADDR_FLEX_CODE_ADDR_SHIFT); +} + +/* PFLASH_PRLLL_EN Bit Fields */ +/** + * @brief Get PFLASH Parallel Enable + * @return + * 0101b - Disable + * Others - Enable + * */ +LOCAL_INLINE bool SEC_HWA_GetPflashPrlllEn(void) +{ + bool ret = false; + uint32_t srk=(uint32_t)((SEC->PFLASH_PRLLL_EN & SEC_PFLASH_PRLLL_EN_PFLASH_PRLLL_EN_MASK) >> SEC_PFLASH_PRLLL_EN_PFLASH_PRLLL_EN_SHIFT); + if (srk !=0x5U) + { + ret =true ; + } + return ret; +} + +/** @}*/ /* HwA_SEC */ +#endif /* HWA_INCLUDE_HWA_SEC_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_sent.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_sent.h new file mode 100644 index 0000000..9b2efa4 --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_sent.h @@ -0,0 +1,1454 @@ +/** + * @file HwA_sent.h + * @author Flagchip073 + * @brief Hardware access layer for SENT + * @version 0.0.1 + * @date 2022-12-14 + * + * @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.0.1 2022-12-14 Flagchip073 N/A First version for FC7300 SENT + ******************************************************************************** */ + +#ifndef _HWA_SENT_H_ +#define _HWA_SENT_H_ + +#include "device_header.h" + +#define DMA_CH_TO_DCHPRI(x) ((x) ^ 3U) + +/** + * @defgroup HwA_sent + * @ingroup fc7xxx_driver_sent + * @{ + */ + +/** + * @brief sent running status + * + */ +typedef enum +{ + SENT_NIBBLE_DATA_MODE_A = 0x0U, /*!< Frame format A */ + SENT_NIBBLE_DATA_MODE_H1 = 0x1U, /*!< Frame format H1 */ + SENT_NIBBLE_DATA_MODE_H2 = 0x2U, /*!< Frame format H2 */ + SENT_NIBBLE_DATA_MODE_H3 = 0x3U, /*!< Frame format H3 */ + SENT_NIBBLE_DATA_MODE_H4 = 0x4U, /*!< Frame format H4 */ + SENT_NIBBLE_DATA_MODE_H5 = 0x5U, /*!< Frame format H5 */ + SENT_NIBBLE_DATA_MODE_H6 = 0x6U, /*!< Frame format H6 */ + SENT_NIBBLE_DATA_MODE_H7 = 0x7U /*!< Frame format H7 */ +} SENT_NibbleDataModeType; + +/** + * @brief sent slow message type + * + */ +typedef enum +{ + SENT_SLOW_MESSAGE_SHORT = 0x0U, /*!< short serial data message */ + SENT_SLOW_MESSAGE_ENHANCE_12DATA_8ID = 0x1U, /*!< enhanced serial data message with 12-bit data and 8-bit ID */ + SENT_SLOW_MESSAGE_ENHANCE_16DATA_4ID = 0x2U, /*!< enhanced serial data message with 16-bit data and 4-bit ID */ +} SENT_SlowMessageType; + +/** + * @brief sent SPC trigger type + * + */ +typedef enum +{ + SENT_SPC_SW_TRIGGER = 0x0U, /*!< SPC pulse triggered by software method */ + SENT_SPC_HW_TRIGGER = 0x1U, /*!< SPC pulse triggered by external trigger */ +} SENT_SPCTriggerType; + +/** + * @brief sent SPC tick base + * + */ +typedef enum +{ + SENT_SPC_TICK_PRE_RECEIVED_MESSAGE = 0x0U, /*!< Previous received message tick base */ + SENT_SPC_TICK_CONFIG = 0x1U, /*!< SENT configured tick base */ +} SENT_SPCTickType; + +/** + * @brief Set SENT Global pre-scaler value + * + * @param pSent the base address of the SENT instance + * @param u8PreScaler the value of the PreSclaer. + */ +LOCAL_INLINE void SENT_HWA_SetGlobalPreScaler(SENT_Type *const pSent, uint8_t u8PreScaler) +{ + pSent->GLBL_CTL = (pSent->GLBL_CTL & ~SENT_GLBL_CTL_PRE_SCALER_MASK) | SENT_GLBL_CTL_PRE_SCALER(u8PreScaler); +} + +/** + * @brief Set SENT Global DMA watermark value + * + * @param pSent the base address of the SENT instance + * @param u8WaterMark the value of the dma watermark. + */ +LOCAL_INLINE void SENT_HWA_SetDMAWaterMark(SENT_Type *const pSent, uint8_t u8WaterMark) +{ + pSent->GLBL_CTL = (pSent->GLBL_CTL & ~SENT_GLBL_CTL_DMA_WATERMARK_MASK) | SENT_GLBL_CTL_DMA_WATERMARK(u8WaterMark); +} + +/** + * @brief Enable SENT Fast message FIFO overflow interrupt + * + * @param pSent the base address of the SENT instance + */ +LOCAL_INLINE void SENT_HWA_EnableFastMessageFIFOOverflowInterrupt(SENT_Type *const pSent) +{ + pSent->GLBL_CTL |= SENT_GLBL_CTL_F_FIFO_OVFL_IE_MASK; +} + +/** + * @brief Disable SENT Fast message FIFO overflow interrupt + * + * @param pSent the base address of the SENT instance + */ +LOCAL_INLINE void SENT_HWA_DisableFastMessageFIFOOverflowInterrupt(SENT_Type *const pSent) +{ + pSent->GLBL_CTL &= ~SENT_GLBL_CTL_F_FIFO_OVFL_IE_MASK; +} + +/** + * @brief Enable SENT Fast message read underflow interrupt + * + * @param pSent the base address of the SENT instance + */ +LOCAL_INLINE void SENT_HWA_EnableFastMessagedmaReadUnderflowInterrupt(SENT_Type *const pSent) +{ + pSent->GLBL_CTL |= SENT_GLBL_CTL_F_DMA_UDFL_IE_MASK; +} + +/** + * @brief Disable SENT Fast message read underflow interrupt + * + * @param pSent the base address of the SENT instance + */ +LOCAL_INLINE void SENT_HWA_DisableFastMessagedmaReadUnderflowInterrupt(SENT_Type *const pSent) +{ + pSent->GLBL_CTL &= ~SENT_GLBL_CTL_F_DMA_UDFL_IE_MASK; +} + +/** + * @brief Enable SENT slow message read underflow interrupt + * + * @param pSent the base address of the SENT instance + */ +LOCAL_INLINE void SENT_HWA_EnableSlowMessagedmaReadUnderflowInterrupt(SENT_Type *const pSent) +{ + pSent->GLBL_CTL |= SENT_GLBL_CTL_S_DMA_UDFL_IE_MASK; +} + +/** + * @brief Disable SENT slow message read underflow interrupt + * + * @param pSent the base address of the SENT instance + */ +LOCAL_INLINE void SENT_HWA_DisableSlowMessagedmaReadUnderflowInterrupt(SENT_Type *const pSent) +{ + pSent->GLBL_CTL &= ~SENT_GLBL_CTL_S_DMA_UDFL_IE_MASK; +} + +/** + * @brief Enable SENT debug mode + * + * @param pSent the base address of the SENT instance + */ +LOCAL_INLINE void SENT_HWA_EnableDebugMode(SENT_Type *const pSent) +{ + pSent->GLBL_CTL |= SENT_GLBL_CTL_DBG_EN_MASK; +} + +/** + * @brief Disable SENT debug mode + * + * @param pSent the base address of the SENT instance + */ +LOCAL_INLINE void SENT_HWA_DisableDebugMode(SENT_Type *const pSent) +{ + pSent->GLBL_CTL &= ~SENT_GLBL_CTL_DBG_EN_MASK; +} + +/** + * @brief Enable Global SENT debug mode + * + * @param pSent the base address of the SENT instance + */ +LOCAL_INLINE void SENT_HWA_EnableGlobal(SENT_Type *const pSent) +{ + pSent->GLBL_CTL |= SENT_GLBL_CTL_SENT_EN_MASK; +} + +/** + * @brief Disable Global SENT debug mode + * + * @param pSent the base address of the SENT instance + */ +LOCAL_INLINE void SENT_HWA_DisableGlobal(SENT_Type *const pSent) +{ + pSent->GLBL_CTL &= ~SENT_GLBL_CTL_SENT_EN_MASK; +} + +/** + * @brief Enable Global SENT debug mode + * + * @param pSent the base address of the SENT instance + */ +LOCAL_INLINE void SENT_HWA_EnableDataOverflowFlagFastClear(SENT_Type *const pSent) +{ + pSent->GLBL_CTL |= SENT_GLBL_CTL_FAST_CLR_MASK; +} + +/** + * @brief Disable Global SENT debug mode + * + * @param pSent the base address of the SENT instance + */ +LOCAL_INLINE void SENT_HWA_DisableDataOverflowFlagFastClear(SENT_Type *const pSent) +{ + pSent->GLBL_CTL &= ~SENT_GLBL_CTL_FAST_CLR_MASK; +} + +/** + * @brief Enable SENT channel receive + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelReceive(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->CHN_EN |= SENT_CHN_EN_CHN_EN((uint32_t)1u << u8Channel); +} + +/** + * @brief Disable SENT channel receive + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelReceive(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->CHN_EN &= ~SENT_CHN_EN_CHN_EN((uint32_t)1u << u8Channel); +} + +/** + * @brief Get SENT channel receive + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE bool SENT_HWA_GetChannelReceive(const SENT_Type *const pSent, uint8_t u8Channel) +{ + if(SENT_CHN_EN_CHN_EN((uint32_t)1u << u8Channel) == (pSent->CHN_EN & SENT_CHN_EN_CHN_EN((uint32_t)1u << u8Channel))) + { + return true; + } + else + { + return false; + } +} + +/** + * @brief Get Channel slow message dma read underflow flag + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @return bool true: the related channel slow message dma is underflow + */ +LOCAL_INLINE bool SENT_HWA_GetSLowMessageUnderflowFlag(const SENT_Type *const pSent, uint8_t u8Channel) +{ + if(((uint32_t)1u << u8Channel) == (pSent->GLBL_STAT & SENT_GLBL_STAT_S_DMA_UDFL((uint32_t)1u << u8Channel))) + { + return true; + } + else + { + return false; + } +} + +/** + * @brief Clear Channel slow message dma read underflow flag + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_ClearSLowMessageUnderflowFlag(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->GLBL_STAT |= SENT_GLBL_STAT_S_DMA_UDFL((uint32_t)1u << u8Channel); +} + +/** + * @brief Get Channel fast message ready flag + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @return bool true: the related channel fast message is ready + */ +LOCAL_INLINE bool SENT_HWA_GetFastMessageReadyFlag(const SENT_Type *const pSent, uint8_t u8Channel) +{ + if(SENT_FMSG_STAT_F_MSG_RDY((uint32_t)1u << u8Channel) == (pSent->FMSG_STAT & SENT_FMSG_STAT_F_MSG_RDY((uint32_t)1u << u8Channel))) + { + return true; + } + else + { + return false; + } +} + +/** + * @brief Clear Channel fast message ready flag + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_ClearFastMessageReadyFlag(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->FMSG_STAT |= SENT_FMSG_STAT_F_MSG_RDY((uint32_t)1u << u8Channel); +} + +/** + * @brief Get Channel slow message ready flag + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @return bool true: the related channel slow message is ready + */ +LOCAL_INLINE bool SENT_HWA_GetSlowMessageReadyFlag(const SENT_Type *const pSent, uint8_t u8Channel) +{ + if(((uint32_t)1u << u8Channel) == (pSent->SMSG_STAT & ((uint32_t)1u << u8Channel))) + { + return true; + } + else + { + return false; + } +} + +/** + * @brief Clear Channel slow message ready flag + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_ClearSlowMessageReadyFlag(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SMSG_STAT |= SENT_FMSG_STAT_F_MSG_RDY((uint32_t)1u << u8Channel); +} + +/** + * @brief Enable SENT channel FIFO function + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelFIFO(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->FIFO_EN |= SENT_FIFO_EN_FIFO_EN((uint32_t)1u << u8Channel); +} + +/** + * @brief Disable SENT channel receive function + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelFIFO(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->FIFO_EN &= ~SENT_FIFO_EN_FIFO_EN((uint32_t)1u << u8Channel); +} + +/** + * @brief Set SENT channel data nibble number + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param u8Number the received data number + */ +LOCAL_INLINE void SENT_HWA_SetChannelNibbleNumber(SENT_Type *const pSent, uint8_t u8Channel, uint8_t u8Number) +{ + pSent->DATA_NUM_CTL1 = (pSent->DATA_NUM_CTL1 & ~(SENT_DATA_NUM_CTL1_CH0_DATA_CTL_MASK >> (4u * u8Channel))) | (SENT_DATA_NUM_CTL1_CH0_DATA_CTL(u8Number) >> (4u * u8Channel)); +} + +/** + * @brief Get SENT channel data nibble number + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param uint8_t the config data number + */ +LOCAL_INLINE uint8_t SENT_HWA_GetChannelNibbleNumber(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return (uint8_t)((pSent->DATA_NUM_CTL1 & (SENT_DATA_NUM_CTL1_CH0_DATA_CTL_MASK >> (4u * u8Channel))) >> (SENT_DATA_NUM_CTL1_CH0_DATA_CTL_SHIFT - (4u * u8Channel))); +} + +/** + * @brief Get Channel fast message FIFO overflow flag + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @return bool true: the related channel fast message FIFO is overflow + */ +LOCAL_INLINE bool SENT_HWA_GetFastMessageFIFOOverflowFlag(const SENT_Type *const pSent, uint8_t u8Channel) +{ + if(SENT_OVFL_UDFL_STAT_FIFO_F_OVFL_FLAG((uint32_t)1u << u8Channel) == (pSent->OVFL_UDFL_STAT & SENT_OVFL_UDFL_STAT_FIFO_F_OVFL_FLAG((uint32_t)1u << u8Channel))) + { + return true; + } + else + { + return false; + } +} + +/** + * @brief Clear Channel fast message FIFO overflow flag + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_ClearFastMessageFIFOOverflowFlag(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->OVFL_UDFL_STAT |= SENT_OVFL_UDFL_STAT_FIFO_F_OVFL_FLAG((uint32_t)1u << u8Channel); +} + +/** + * @brief Get Channel fast message DMA underflow flag + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @return bool true: the related channel fast message DMA read is underflow + */ +LOCAL_INLINE bool SENT_HWA_GetFastMessageDMAUnderflowFlag(const SENT_Type *const pSent, uint8_t u8Channel) +{ + if(SENT_OVFL_UDFL_STAT_DMA_F_UDFL_FLAG((uint32_t)1u << u8Channel) == (pSent->OVFL_UDFL_STAT & SENT_OVFL_UDFL_STAT_DMA_F_UDFL_FLAG((uint32_t)1u << u8Channel))) + { + return true; + } + else + { + return false; + } +} + +/** + * @brief Clear Channel fast message DMA underflow flag + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_ClearFastMessageDMAUnderflowFlag(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->OVFL_UDFL_STAT |= SENT_OVFL_UDFL_STAT_DMA_F_UDFL_FLAG((uint32_t)1u << u8Channel); +} + +/** + * @brief Set SENT channel nibble data mode + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param eMode the nibble data mode + */ +LOCAL_INLINE void SENT_HWA_SetChannelNibbleDataMode(SENT_Type *const pSent, uint8_t u8Channel, SENT_NibbleDataModeType eMode) +{ + pSent->NB_MODE1 = (pSent->NB_MODE1 & ~(SENT_NB_MODE1_CH0_NB_MODE_MASK >> (4u * u8Channel))) | (SENT_NB_MODE1_CH0_NB_MODE(eMode) >> (4u * u8Channel)); +} + +/** + * @brief Enable SENT channel fast message DMA request + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelFastMessageDmaRequest(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->FDMA_CTL |= SENT_FDMA_CTL_FDMA_EN((uint32_t)1u << u8Channel); +} + +/** + * @brief Disable SENT channel fast message DMA request + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelFastMessageDmaRequest(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->FDMA_CTL &= ~SENT_FDMA_CTL_FDMA_EN((uint32_t)1u << u8Channel); +} + +/** + * @brief Enable SENT channel slow message DMA request + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelSlowMessageDmaRequest(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SDMA_CTL |= SENT_SDMA_CTL_SDMA_EN((uint32_t)1u << u8Channel); +} + +/** + * @brief Disable SENT channel slow message DMA request + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelSlowMessageDmaRequest(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SDMA_CTL &= ~SENT_SDMA_CTL_SDMA_EN((uint32_t)1u << u8Channel); +} + +/** + * @brief Enable SENT channel Fast message interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelFastMessageInterrupt(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->FINT_CTL |= SENT_FINT_CTL_FINT_CTL((uint32_t)1u << u8Channel); +} + +/** + * @brief Disable SENT channel Fast message interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelFastMessageInterrupt(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->FINT_CTL &= ~SENT_FINT_CTL_FINT_CTL((uint32_t)1u << u8Channel); +} + +/** + * @brief Enable SENT channel slow message interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelSlowMessageInterrupt(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SINT_CTL |= SENT_SINT_CTL_SINT_CTL((uint32_t)1u << u8Channel); +} + +/** + * @brief Disable SENT channel slow message interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelSlowMessageInterrupt(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SINT_CTL &= ~SENT_SINT_CTL_SINT_CTL((uint32_t)1u << u8Channel); +} + +/** + * @brief Enable SENT channel Compensate + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelCompensate(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CLK_CTL |= SENT_CHN_CLK_CTL_COMP_EN_MASK; +} + +/** + * @brief Disable SENT channel Compensate + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelCompensate(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CLK_CTL &= ~SENT_CHN_CLK_CTL_COMP_EN_MASK; +} + +/** + * @brief Set SENT channel pre-scaler + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param u16PreScaler the related Channel Prescaler value + */ +LOCAL_INLINE void SENT_HWA_SetChannelPreScaler(SENT_Type *const pSent, uint8_t u8Channel, uint16_t u16PreScaler) +{ + pSent->SENT_CHN[u8Channel].CHN_CLK_CTL = (pSent->SENT_CHN[u8Channel].CHN_CLK_CTL & ~SENT_CHN_CLK_CTL_PRE_SCALER_MASK) | SENT_CHN_CLK_CTL_PRE_SCALER(u16PreScaler); +} + +/** + * @brief Get Channel Prescaler value after compensate + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @return uint8_t the related Channel Prescaler value after compensate + */ +LOCAL_INLINE uint16_t SENT_HWA_GetChannelCompensatePreScaler(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return (uint16_t)((pSent->SENT_CHN[u8Channel].CHN_CLK_CTL & SENT_CHN_CLK_CTL_COMPED_PRE_SCALER_MASK) >> SENT_CHN_CLK_CTL_COMPED_PRE_SCALER_SHIFT); +} + +/** + * @brief Get Channel status + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @return uint32_t the related Channel status + */ +LOCAL_INLINE uint32_t SENT_HWA_GetChannelStatus(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return pSent->SENT_CHN[u8Channel].CHN_STAT; +} + +/** + * @brief Clear Channel status + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param u32W1CBit the status bits need to be clear. + */ +LOCAL_INLINE void SENT_HWA_ClearChannelStatus(SENT_Type *const pSent, uint8_t u8Channel, uint32_t u32W1CBit) +{ + pSent->SENT_CHN[u8Channel].CHN_STAT |= u32W1CBit; +} + +/** + * @brief Enable SENT channel all error interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelAllErrorInterrupt(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL |= (SENT_CHN_CTL_CAL_RESYNC_IE_MASK | SENT_CHN_CTL_CAL_20_25_IE_MASK | SENT_CHN_CTL_SMSG_OVFL_IE_MASK | \ + SENT_CHN_CTL_FMSG_OVFL_IE_MASK | SENT_CHN_CTL_PP_DIAG_ERR_IE_MASK | SENT_CHN_CTL_CAL_DIAG_ERR_IE_MASK | \ + SENT_CHN_CTL_CAL_ERR_IE_MASK | SENT_CHN_CTL_NIB_ERR_IE_MASK | SENT_CHN_CTL_S_CRC_ERR_IE_MASK | \ + SENT_CHN_CTL_F_CRC_ERR_IE_MASK | SENT_CHN_CTL_EDGE_ERR_IE_MASK | SENT_CHN_CTL_SPC_OVERRUN_IE_MASK); +} + +/** + * @brief Disable SENT channel all error interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelAllErrorInterrupt(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~(SENT_CHN_CTL_CAL_RESYNC_IE_MASK | SENT_CHN_CTL_CAL_20_25_IE_MASK | SENT_CHN_CTL_SMSG_OVFL_IE_MASK | \ + SENT_CHN_CTL_FMSG_OVFL_IE_MASK | SENT_CHN_CTL_PP_DIAG_ERR_IE_MASK | SENT_CHN_CTL_CAL_DIAG_ERR_IE_MASK | \ + SENT_CHN_CTL_CAL_ERR_IE_MASK | SENT_CHN_CTL_NIB_ERR_IE_MASK | SENT_CHN_CTL_S_CRC_ERR_IE_MASK | \ + SENT_CHN_CTL_F_CRC_ERR_IE_MASK | SENT_CHN_CTL_EDGE_ERR_IE_MASK | SENT_CHN_CTL_SPC_OVERRUN_IE_MASK); +} + +/** + * @brief Enable/disable SENT channel idle flag interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelBusIdleInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_BUS_IDLE_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_BUS_IDLE_IE_MASK; + } +} + +/** + * @brief Enable/disable SENT channel sync/calibration pulse error interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelCalResyncInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_CAL_RESYNC_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_CAL_RESYNC_IE_MASK; + } +} + +/** + * @brief Enable/disable Sync/calibration pulse difference eceed 1.5625% error interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelCalERRInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_CAL_ERR_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_CAL_ERR_IE_MASK; + } +} + +/** + * @brief Enable/disable SENT channel Calibration 20% pass 25% fail interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelCalFailInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_CAL_20_25_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_CAL_20_25_IE_MASK; + } +} + +/** + * @brief Enable/disable SENT channel Slow message overflow interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelSOVFLInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_SMSG_OVFL_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_SMSG_OVFL_IE_MASK; + } +} + +/** + * @brief Enable/disable SENT channel fast message overflow interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelFOVFLInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_FMSG_OVFL_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_FMSG_OVFL_IE_MASK; + } +} + +/** + * @brief Enable/disable SENT channel Nibble value error interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelNibbleErrorInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_NIB_ERR_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_NIB_ERR_IE_MASK; + } +} + +/** + * @brief Enable/disable SENT channel Previous pulse diagnosis error interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelPPDiagInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_PP_DIAG_ERR_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_PP_DIAG_ERR_IE_MASK; + } +} + +/** + * @brief Enable/disable SENT channel Calibration diagnosis over 25% error interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelCALDiagInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_CAL_DIAG_ERR_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_CAL_DIAG_ERR_IE_MASK; + } +} + +/** + * @brief Enable/disable SENT channel SPC overrun error interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelSPCOverRunInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_SPC_OVERRUN_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_SPC_OVERRUN_IE_MASK; + } +} + +/** + * @brief Enable/disable SENT channel Fast message CRC check error interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelFCRCInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_F_CRC_ERR_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_F_CRC_ERR_IE_MASK; + } +} + +/** + * @brief Enable/disable SENT channel slow message CRC check error interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelSCRCInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_S_CRC_ERR_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_S_CRC_ERR_IE_MASK; + } +} + +/** + * @brief Enable/disable SENT channel Falling edge number error interrupt + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param bEn Enable or disable the interrupt + */ +LOCAL_INLINE void SENT_HWA_EnableChannelEdgeERRInterrupt(SENT_Type *const pSent, uint8_t u8Channel, bool bEn) +{ + if(bEn) + { + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_EDGE_ERR_IE_MASK; + } + else + { + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_EDGE_ERR_IE_MASK; + } +} + +/** + * @brief Enable SENT channel Alternative 4-bit CRC algorithm + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelAltCRC(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_ALT_4BIT_CRC_MASK; +} + +/** + * @brief Disable SENT channel Alternative 4-bit CRC algorithm + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelAltCRC(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_ALT_4BIT_CRC_MASK; +} + +/** + * @brief Enable SENT channel Fast message data change + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelFastMessageDataChange(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_DATA_CHANGE_EN_MASK; +} + +/** + * @brief Disable SENT channel Fast message data change + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelFastMessageDataChange(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_DATA_CHANGE_EN_MASK; +} + +/** + * @brief Enable SENT channel calibration valid range from 20% tp 25% + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelCalValid20To25(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_CAL_SEL_MASK; +} + +/** + * @brief Disable SENT channel calibration valid range from 20% tp 25% + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelCalValid20To25(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_CAL_SEL_MASK; +} + +/** + * @brief Enable SENT channel calibration valid diagnostic + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelCalValidDiagnostic(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_PP_CHK_DIS_MASK; +} + +/** + * @brief Disable SENT channel calibration valid diagnostic + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelCalValidDiagnostic(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_PP_CHK_DIS_MASK; +} + +/** + * @brief Enable SENT channel fast message CRC with Augmentation + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelFastMessageAugmentation(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_FCRC_SEL_MASK; +} + +/** + * @brief Disable SENT channel fast message CRC with Augmentation + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelFastMessageAugmentation(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_FCRC_SEL_MASK; +} + +/** + * @brief Enable SENT channel Fast message crc with S&C + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelFastMessageCRCWithSC(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_FCRC_SC_EN_MASK; +} + +/** + * @brief Disable SENT channel Fast message crc with S&C + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelFastMessageCRCWithSC(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_FCRC_SC_EN_MASK; +} + +/** + * @brief Enable SENT channel slow message CRC with Augmentation + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelSlowMessageAugmentation(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_SCRC_SEL_MASK; +} + +/** + * @brief Disable SENT channel slow message CRC with Augmentation + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelSlowMessageAugmentation(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_SCRC_SEL_MASK; +} + +/** + * @brief Enable SENT channel Pause pulse + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelPausePulse(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_PAUSE_DET_EN_MASK; +} + +/** + * @brief Disable SENT channel Successive calibration pulses diagnostic option1 + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelPausePulse(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_PAUSE_DET_EN_MASK; +} + +/** + * @brief Enable SENT channel Successive calibration pulses diagnostic option1 + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelSPCOption1(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_SCP_CHK_MASK; +} + +/** + * @brief Disable SENT channel Pause pulse + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelSPCOption1(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_SCP_CHK_MASK; +} + +/** + * @brief Enable SENT channel Fast message crc check + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelFastMessageCRCCheck(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL &= ~SENT_CHN_CTL_FMSG_CRC_CHECK_OFF_MASK; +} + +/** + * @brief Disable SENT channel Fast message crc check + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelFastMessageCRCCheck(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL |= SENT_CHN_CTL_FMSG_CRC_CHECK_OFF_MASK; +} + +/** + * @brief Set SENT channel digital filter count + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param u8Count the count of channel digital filter + */ +LOCAL_INLINE void SENT_HWA_SetChannelDigitalFilterCount(SENT_Type *const pSent, uint8_t u8Channel, uint8_t u8Count) +{ + pSent->SENT_CHN[u8Channel].CHN_CTL = (pSent->SENT_CHN[u8Channel].CHN_CTL & ~SENT_CHN_CTL_FILT_CNT_MASK) | SENT_CHN_CTL_FILT_CNT(u8Count); +} + +/** + * @brief Get Channel fast message data nibble + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return uint32_t the corresponding channel data nibble value + */ +LOCAL_INLINE uint32_t SENT_HWA_GetChannelDataNibble(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return pSent->SENT_CHN[u8Channel].CHN_FDATA; +} + +/** + * @brief Get Channel fast message crc nibble + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return uint8_t the corresponding channel crc nibble value + */ +LOCAL_INLINE uint8_t SENT_HWA_GetChannelFastMessageCRCNibble(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return (uint8_t)((pSent->SENT_CHN[u8Channel].CHN_FCRC & SENT_CHN_FCRC_CRC_DATA_MASK) >> SENT_CHN_FCRC_CRC_DATA_SHIFT); +} + +/** + * @brief Get Channel fast message status communication nibble + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return uint8_t the corresponding channel status communication nibble value + */ +LOCAL_INLINE uint8_t SENT_HWA_GetChannelFastMessageStatusNibble(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return (uint8_t)((pSent->SENT_CHN[u8Channel].CHN_FCRC & SENT_CHN_FCRC_SC_NB_MASK) >> SENT_CHN_FCRC_SC_NB_SHIFT); +} + +/** + * @brief Get Channel fast message status timestamp + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return uint32_t the corresponding channel timestamp value + */ +LOCAL_INLINE uint32_t SENT_HWA_GetChannelFastMessageTimeStamp(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return ((pSent->SENT_CHN[u8Channel].CHN_FTS & SENT_CHN_FTS_TIMESTAMP_VAL_MASK) >> SENT_CHN_FTS_TIMESTAMP_VAL_SHIFT); +} + +/** + * @brief Get Channel slow message type + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return SENT_SlowMessageType the corresponding channel slow message type + */ +LOCAL_INLINE SENT_SlowMessageType SENT_HWA_GetChannelSLowMessageType(const SENT_Type *const pSent, uint8_t u8Channel) +{ + SENT_SlowMessageType eRet = SENT_SLOW_MESSAGE_SHORT; + + if(SENT_CHN_SBIT3__MSG_TYPE_MASK == (pSent->SENT_CHN[u8Channel].CHN_SBIT3 & SENT_CHN_SBIT3__MSG_TYPE_MASK)) + { + if(SENT_CHN_SBIT3__CFG_MASK == (pSent->SENT_CHN[u8Channel].CHN_SBIT3 & SENT_CHN_SBIT3__CFG_MASK)) + { + eRet = SENT_SLOW_MESSAGE_ENHANCE_16DATA_4ID; + } + else + { + eRet = SENT_SLOW_MESSAGE_ENHANCE_12DATA_8ID; + } + } + else + { + //do nothing + } + return eRet; +} + +/** + * @brief Get Channel enhanced serial message id bit 7 to bit4 or id bit 3 to id bit 0 + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return uint8_t the corresponding channel enhanced serial message id bit 7 to bit4 or id bit 3 to id bit 0 + */ +LOCAL_INLINE uint8_t SENT_HWA_GetChannelBit3EnhancedID7_4_OR_ID3_0(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return (uint8_t)((pSent->SENT_CHN[u8Channel].CHN_SBIT3 & SENT_CHN_SBIT3__ID7_4_OR_ID3_0_MASK) >> SENT_CHN_SBIT3__ID7_4_OR_ID3_0_SHIFT); +} + +/** + * @brief Get Channel enhanced serial message id bit 3 to bit0 or data bit 15 to id bit 12 + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return uint8_t the corresponding channel enhanced serial message id bit 3 to bit0 or data bit 15 to id bit 12 + */ +LOCAL_INLINE uint8_t SENT_HWA_GetChannelBit3EnhancedID3_0_OR_DATA15_12(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return (uint8_t)((pSent->SENT_CHN[u8Channel].CHN_SBIT3 & SENT_CHN_SBIT3__ID3_0_OR_DATA15_12_MASK) >> SENT_CHN_SBIT3__ID3_0_OR_DATA15_12_SHIFT); +} + +/** + * @brief Get Channel slow message bit2 with CRC + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return uint8_t the corresponding channel slow message CRC value + */ +LOCAL_INLINE uint8_t SENT_HWA_GetChannelBit2CRC(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return (uint8_t)((pSent->SENT_CHN[u8Channel].CHN_SBIT2 & SENT_CHN_SBIT2__SMSG_CRC_MASK) >> SENT_CHN_SBIT2__SMSG_CRC_SHIFT); +} + +/** + * @brief Get Channel slow message bit2 with DATA + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return uint16_t the corresponding channel slow message DATA value + */ +LOCAL_INLINE uint16_t SENT_HWA_GetChannelBit2DATA(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return (uint16_t)((pSent->SENT_CHN[u8Channel].CHN_SBIT2 & SENT_CHN_SBIT2__SMSG_DATA_MASK) >> SENT_CHN_SBIT2__SMSG_DATA_SHIFT); +} + +/** + * @brief Get Channel slow message status timestamp + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return uint32_t the corresponding channel timestamp value + */ +LOCAL_INLINE uint32_t SENT_HWA_GetChannelSlowMessageTimeStamp(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return ((pSent->SENT_CHN[u8Channel].CHN_STS & SENT_CHN_STS_SMSG_TIMESTAMP_MASK) >> SENT_CHN_STS_SMSG_TIMESTAMP_SHIFT); +} + +/** + * @brief Get Channel number of received frames + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return uint32_t the number of received frames + */ +LOCAL_INLINE uint32_t SENT_HWA_GetChanneReceivedFrameNumber(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return ((pSent->SENT_CHN[u8Channel].CHN_MCNT & SENT_CHN_MCNT_FRAME_CNT_MASK) >> SENT_CHN_MCNT_FRAME_CNT_SHIFT); +} + +/** + * @brief Get Channel number of received edges + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return uint32_t the number of received edges + */ +LOCAL_INLINE uint32_t SENT_HWA_GetChanneReceivedEdgeNumber(const SENT_Type *const pSent, uint8_t u8Channel) +{ + return ((pSent->SENT_CHN[u8Channel].CHN_MCNT & SENT_CHN_MCNT_EDGE_CNT_MASK) >> SENT_CHN_MCNT_EDGE_CNT_SHIFT); +} + +/** + * @brief Clear the number of received frames + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_ClearChannelReceivedFrameNumber(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_MCNT |= SENT_CHN_MCNT_FRAME_CNT_CLR_MASK; +} + +/** + * @brief Clear the number of received edges + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_ClearChannelReceivedEdgeNumber(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_MCNT |= SENT_CHN_MCNT_EDGE_CNT_CLR_MASK; +} + +/** + * @brief Enable SENT channel SPC mode + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelSPCMode(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_SPC_CTL |= SENT_CHN_SPC_CTL_SPC_ENABLE_MASK; +} + +/** + * @brief Disable SENT channel SPC mode + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelSPCMode(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_SPC_CTL &= ~SENT_CHN_SPC_CTL_SPC_ENABLE_MASK; +} + +/** + * @brief Enable SENT channel calibration diagnosis in SPC mod + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_EnableChannelCalibrationDiag(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_SPC_CTL &= ~SENT_CHN_SPC_CTL_CAL_DIAG_DIS_MASK; +} + +/** + * @brief Disable SENT channel calibration diagnosis in SPC mod + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_DisableChannelCalibrationDiag(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_SPC_CTL |= SENT_CHN_SPC_CTL_CAL_DIAG_DIS_MASK; +} + + +/** + * @brief Set the SPC pulse trigger method + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param eTrigger the SPC pulse trigger method + */ +LOCAL_INLINE void SENT_HWA_SetChannelSPCTriggerMethod(SENT_Type *const pSent, uint8_t u8Channel, SENT_SPCTriggerType eTrigger) +{ + pSent->SENT_CHN[u8Channel].CHN_SPC_CTL = (pSent->SENT_CHN[u8Channel].CHN_SPC_CTL & ~SENT_CHN_SPC_CTL_SPC_MODE_MASK) | SENT_CHN_SPC_CTL_SPC_MODE(eTrigger); +} + +/** + * @brief Set the delay between SPC-trigger assert and finally generate a SPC pulse + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param eTrigger the delay value + */ +LOCAL_INLINE void SENT_HWA_SetChannelSPCPulseDelay(SENT_Type *const pSent, uint8_t u8Channel, uint8 u8Delay) +{ + pSent->SENT_CHN[u8Channel].CHN_SPC_CTL = (pSent->SENT_CHN[u8Channel].CHN_SPC_CTL & ~SENT_CHN_SPC_CTL_SPC_PULSE_DELAY_MASK) | SENT_CHN_SPC_CTL_SPC_PULSE_DELAY(u8Delay); +} + +/** + * @brief Set the delay between SPC-trigger assert and finally generate a SPC pulse + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param eTick the selected tick base of SPC + */ +LOCAL_INLINE void SENT_HWA_SetChannelSPCTickBase(SENT_Type *const pSent, uint8_t u8Channel, SENT_SPCTickType eTick) +{ + pSent->SENT_CHN[u8Channel].CHN_SPC_CTL = (pSent->SENT_CHN[u8Channel].CHN_SPC_CTL & ~SENT_CHN_SPC_CTL_SPC_TICK_BASE_MASK) | SENT_CHN_SPC_CTL_SPC_TICK_BASE(eTick); +} + +/** + * @brief trigger the SENT to generate a SPC pulse by software + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + */ +LOCAL_INLINE void SENT_HWA_StartChannelSPC(SENT_Type *const pSent, uint8_t u8Channel) +{ + pSent->SENT_CHN[u8Channel].CHN_SPC_CTL |= SENT_CHN_SPC_CTL_SPC_START_MASK; +} + +/** + * @brief Set the width of the SPC pulse. + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param u8Width the width of the SPC pulse. + */ +LOCAL_INLINE void SENT_HWA_SetChannelSPCPulseWidth(SENT_Type *const pSent, uint8_t u8Channel, uint8_t u8Width) +{ + pSent->SENT_CHN[u8Channel].CHN_SPC_CTL = (pSent->SENT_CHN[u8Channel].CHN_SPC_CTL & ~SENT_CHN_SPC_CTL_SPC_PULSE_WIDTH_MASK) | SENT_CHN_SPC_CTL_SPC_PULSE_WIDTH(u8Width); +} + +/** + * @brief Set the idle count determines how long the bus idle flag will assert when bus is idle + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel + * @param u8Count the idle count + */ +LOCAL_INLINE void SENT_HWA_SetChannelIdleCount(SENT_Type *const pSent, uint8_t u8Channel, uint8_t u8Count) +{ + pSent->SENT_CHN[u8Channel].CHN_IDLE_CTL = (pSent->SENT_CHN[u8Channel].CHN_IDLE_CTL & ~SENT_CHN_IDLE_CTL_IDLE_CNT_MASK) | SENT_CHN_IDLE_CTL_IDLE_CNT(u8Count); +} + +/** + * @brief Get the flag indicating the spc is busy + * + * @param pSent the base address of the SENT instance + * @param u8Channel the index of sent channel(0-3) + * @return bool the flag indicating the spc is busy + */ +LOCAL_INLINE bool SENT_HWA_GetChanneSPCBusyFlag(const SENT_Type *const pSent, uint8_t u8Channel) +{ + if(SENT_CHN_SPC_CTL_SPC_BUSY_MASK == (pSent->SENT_CHN[u8Channel].CHN_SPC_CTL & SENT_CHN_SPC_CTL_SPC_BUSY_MASK)) + { + return true; + } + else + { + return false; + } +} + +/** @}*/ + +#endif /* _HWA_SENT_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_smc.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_smc.h new file mode 100644 index 0000000..dd468b6 --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_smc.h @@ -0,0 +1,74 @@ +/** + * @file HwA_smc.h + * @author Flagchip + * @brief FC7xxx SMC hardware access layer + * @version 0.1.0 + * @date 2022-11-21 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + * @details + */ + +#ifndef _HWA_SMC_H_ +#define _HWA_SMC_H_ + +#include "device_header.h" +/********* Local typedef ************/ +/** @brief SMC stop mode control */ +typedef enum +{ + SMC_STOP_MODE = 0U, + SMC_STANDBY_MODE = 4U +} SMC_LpwModeCtrlType; + +/** @brief SMC standby mode */ +typedef enum +{ + SMC_CFG_STANDBY_0 = 0U, + SMC_CFG_STANDBY_1 = 1U, + SMC_CFG_STANDBY_2 = 2U, + SMC_CFG_STANDBY_3 = 3U +} SMC_StandbyModeType; + +/********* Local inline function ************/ +/** + * @brief Clear stop mode control value + * + */ +LOCAL_INLINE void SMC_HWA_ClearStopModeCtrl(void) +{ + SMC->PMCTRL &= ~(uint32_t)SMC_PMCTRL_STOP_MODE_MASK; +} + +/** + * @brief Set stop mode control + * + * @param eMode Stop mode control type + */ +LOCAL_INLINE void SMC_HWA_SetStopModeCtrl(SMC_LpwModeCtrlType eMode) +{ + SMC->PMCTRL = (uint32_t)eMode; +} + +/** + * @brief Clear standby mode + * + */ +LOCAL_INLINE void SMC_HWA_ClearStandbyMode(void) +{ + SMC->STANDBY_CFG &= ~(uint32_t)SMC_STANDBY_CFG_OPTION_MASK; +} + +/** + * @brief Set standby mode + * + * @param eMode Standby mode type + */ +LOCAL_INLINE void SMC_HWA_SetStandbyMode(SMC_StandbyModeType eMode) +{ + SMC->STANDBY_CFG = (uint32_t)eMode; +} + + +#endif /* #ifndef _HWA_SMC_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_stcu.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_stcu.h new file mode 100644 index 0000000..3f69c69 --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_stcu.h @@ -0,0 +1,265 @@ +/** + * @file HwA_stcu.h + * @author Flagchip + * @brief Safety Test and Control Unit + * @version 0.1.0 + * @date 2022-11-30 + * + * @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 03/08/2022 Flagchip038 N/A First version for FC7xxx + ******************************************************************************** */ + +#ifndef _HWA_STCU_H_ +#define _HWA_STCU_H_ + +#include "device_header.h" +#include "fc7xxx_driver_stcu.h" + +/** + * \brief Get Self Test Status + * + * \return Status, maybe more than one status, refer to "STCU_SelfTestStatusType" + */ +LOCAL_INLINE uint32_t STCU_HWA_GetSelfTestStatus(void) +{ + return STCU->SELF_TEST_STATUS; +} + +/** + * \brief Clear all Self Test Status + */ +LOCAL_INLINE void STCU_HWA_ClearSelfTestStatus(void) +{ + STCU->SELF_TEST_STATUS = 0x0UL; +} + + +/** + * \brief Mbist select for self-test + * + * \param u32MbistSel maybe more than one + */ +LOCAL_INLINE void STCU_HWA_MbistSelect(uint32_t u32MbistSel) +{ + STCU->MBIST_SEL = u32MbistSel; +} + +/** + * \brief Get Mbist Done Flag + * + * \return All Mbist Done flags, refer to "STCU_MbistDoneType" + */ +LOCAL_INLINE uint32_t STCU_GetMbistDone(void) +{ + return STCU->MBIST_DONE_STATUS; +} + +/** + * \brief Get Mbist Fail Flag + * + * \return All Mbist Fail flags "STCU_MbistFailedType" + */ +LOCAL_INLINE uint32_t STCU_GetMbistFail(void) +{ + return STCU->MBIST_FAIL_STATUS; +} + +/** + * \brief Check Lbist execution failed status + * + * \return LBIST status, refer to "STCU_LbistStatusType" + */ +LOCAL_INLINE uint32_t STCU_HWA_CheckLbistStatus(void) +{ + return STCU->LBIST_STATUS; +} + + +/** + * \brief Get STCU Hardware Ram Initial Status + * + * \return Initial Status, refer to "STCU_HardwareInitRamStatusType" + */ +LOCAL_INLINE uint32_t STCU_HWA_GetHardwareRamInitStatus(void) +{ + return STCU->SRAM_INI_STATUS; +} + +/** + * \brief STCU RAM Init Mode set, can select more than one, for example: STCU_INIT_RAM_TYPE_SRAM0 | STCU_INIT_RAM_TYPE_SRAM1 + * + * \param u32InitRamType Init Mode + */ +LOCAL_INLINE void STCU_HWA_SetRamInitType(uint32_t u32InitRamType) +{ + STCU->SRAM_INI_SEL = u32InitRamType; +} + +/** + * \brief Set STCU Interrupt + * + * \param bIntEn Normal interrupt enable + * \param bSequenceErrorIntEn Sequence error interrupt enable + * \param bSizeErrorIntEn Size error interrupt enable + */ +LOCAL_INLINE void STCU_HWA_SetInterrupt(uint8_t bIntEn, uint8_t bSequenceErrorIntEn, uint8_t bSizeErrorIntEn) +{ + STCU->IRQ = STCU_IRQ_EN(bIntEn) | STCU_IRQ_SEQ_ERR(bSequenceErrorIntEn) | STCU_IRQ_SIZE_ERR(bSizeErrorIntEn); +} + +/** + * \brief STCU Ram Initial Start + * + * \param eInitRamMode Initial mode + * \param bEnable Enable Initial + * \param bLock Lock after initial + */ +LOCAL_INLINE void STCU_HWA_StartRamInit(STCU_InitRamModeType eInitRamMode, uint8_t bLock) +{ + STCU->SRAM_INI_CTRL = STCU_SRAM_INI_CTRL_MODE(eInitRamMode) | STCU_SRAM_INI_CTRL_EN_MASK | STCU_SRAM_INI_CTRL_LOCK(bLock) ; +} + +/** + * \brief Get Ram Initial Done flag + * + * \return All Done flag, maybe more than one flag, refer to "STCU_InitRamDoneType" + */ +LOCAL_INLINE uint32_t STCU_HWA_GetRamInitDone(void) +{ + return STCU->SRAM_INI_DONE_STATUS; +} + +/** + * \brief Get Ram Initial status + * + * \return All Done flag, maybe more than one flag, refer to "STCU_HardwareInitRamStatusType" + */ +LOCAL_INLINE uint32_t STCU_HWA_GetRamInitStatus(void) +{ + return STCU->SRAM_INI_STATUS; +} + +/** + * \brief Set the LBIST pattern amount control value N. + * + * \param u32Amount LBIST pattern amount control value N. (pattern amount = N * 256) + */ +LOCAL_INLINE void STCU_HWA_SetLBISTPatternAmount(uint32_t u32Amount) +{ + STCU->LBIST_PAT_CTRL = u32Amount; +} + +/** + * \brief Set the MBIST algorithm for SW trigger self-test + * + * \param bFullTest Enable Full test for MBIST. + * \param bSRAMInit Enable SRAM initialization at the end of software trigger self-test. + */ +LOCAL_INLINE void STCU_HWA_SetMBISTSWAlg(bool bFullTest, bool bSRAMInit) +{ + STCU->MBIST_ALG = (STCU->MBIST_ALG & ~(STCU_MBIST_ALG_TRIG_ALG_SEL_MASK | STCU_MBIST_ALG_TRIG_INI_EN_MASK)) | \ + (STCU_MBIST_ALG_TRIG_ALG_SEL(bFullTest?0X1FU:0x19U) | STCU_MBIST_ALG_TRIG_INI_EN(bSRAMInit?0x1U:0x0U)); +} + +/** + * \brief Set safety key + * + * \param u32Key Safety Key. + */ +LOCAL_INLINE void STCU_HWA_SetSafetyKey(uint32_t u32Key) +{ + STCU->SELF_TEST_KEY = u32Key; +} + +/** + * \brief Enable A self-test software trigger. + */ +LOCAL_INLINE void STCU_HWA_SwTriggerA(void) +{ + STCU->SELF_TEST_TRIG_A = STCU_SELF_TEST_TRIG_A_MASK; +} + +/** + * \brief Enable B self-test software trigger. + */ +LOCAL_INLINE void STCU_HWA_SwTriggerB(void) +{ + STCU->SELF_TEST_TRIG_B = STCU_SELF_TEST_TRIG_B_MASK; +} + +/** + * \brief Set self test ctrl register + * + * \param u32Reg Register value. + */ +LOCAL_INLINE void STCU_HWA_SetSelfTestCTRL(uint32_t u32Reg) +{ + STCU->SELF_TEST_CTRL = u32Reg; +} + +/** + * \brief Enable interrupt + */ +LOCAL_INLINE void STCU_HWA_EnableInterrupt(void) +{ + STCU->IRQ |= STCU_IRQ_EN_MASK; +} + +/** + * \brief Disable interrupt + */ +LOCAL_INLINE void STCU_HWA_DisableInterrupt(void) +{ + STCU->IRQ &= ~STCU_IRQ_EN_MASK; +} + +/** + * \brief Get STCU interrupt flags + * + * \return Status, maybe more than one status, refer to "STCU_InterruptFlagType" + */ +LOCAL_INLINE uint32_t STCU_HWA_GetInterruptFlag(void) +{ + return ((STCU->IRQ) & (STCU_IRQ_SEQ_ERR_MASK | STCU_IRQ_SIZE_ERR_MASK)); +} + +/** + * \brief Clear STCU interrupt flags + */ +LOCAL_INLINE void STCU_HWA_ClearInterruptFlag(void) +{ + STCU->IRQ &= ~(STCU_IRQ_SEQ_ERR_MASK | STCU_IRQ_SIZE_ERR_MASK); +} + +/** + * \brief Set STCU LBIST expected misr value + */ +LOCAL_INLINE void STCU_HWA_SetExpectedMisr(uint32_t u32Misr) +{ + STCU->LBIST_EXP_MISR = STCU_LBIST_EXP_MISR_MISR(u32Misr); +} + +/** + * \brief Get STCU LBIST expected misr value + */ +LOCAL_INLINE uint32_t STCU_HWA_GetExpectedMisr(void) +{ + return STCU->LBIST_EXP_MISR; +} + +/** + * \brief Get STCU LBIST actual misr value + */ +LOCAL_INLINE uint32_t STCU_HWA_GetActualMisr(void) +{ + return STCU->LBIST_ACT_MISR; +} + +#endif /*#ifndef _HWA_STCU_H_*/ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_tmu.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_tmu.h new file mode 100644 index 0000000..601ceb6 --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_tmu.h @@ -0,0 +1,548 @@ +/** + * @file HwA_tmu.h + * @author Flagchip + * @brief Hardware access layer for TMU + * @version 0.1.0 + * @date 2023-12-29 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + */ +/********************************************************************************* +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2023-12-29 qxw074 N/A First version for FC7240 +******************************************************************************** */ + +#ifndef _HWA_TMU_H +#define _HWA_TMU_H + +#include "device_header.h" +#include "HwA_csc.h" + +/** + * @defgroup HwA_tmu + * @ingroup fc7xxx_driver_tmu + * @{ + */ + +/** + * @brief Select the TF_CTRL and TV_CTRL register is lock or not + * + */ +typedef enum +{ + TMU_TF_TV_LOCK = 0U, /*!< TF_CTRL and TV_CTRL register is lock*/ + TMU_TF_TV_UNLOCK = 1U /*!< TF_CTRL and TV_CTRL register is unlock*/ +}TMU_LockType; + +/** + * @brief Select the Flag-based temperature sensor hysteresis control + * + */ +typedef enum +{ + TMU_TF_HYSOFF_ON = 0U, /*!< Flag-based temperature sensor hysteresis is on*/ + TMU_TF_HYSOFF_OFF = 1U /*!< Flag-based temperature sensor hysteresis is off*/ +}TMU_HysteresisType; + +/** + * @brief Select the Flag-based temperature sensor filter control + * + */ +typedef enum +{ + TMU_TF_FILT_BYP_BYPASSED = 0U, /*!< Flag-based temperature sensor filter is bypassed*/ + TMU_TF_FILT_BYP_ENABLED = 1U /*!< Flag-based temperature sensor filter is enabled*/ +}TMU_bypassType; + +/** + * @brief Get the status of whether the temperature sensor register is locked + * + * @param pTmu the base address of the TMU instance + * @return true Temperature register is locked(CTRL) + * @return false Temperature register is unlocked(CTRL) + */ +LOCAL_INLINE TMU_LockType TMU_HWA_GetTemperatureLockStatus(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = (pTmu->UNLOCK & TMU_UNLOCK_UNLOCK_MASK) >> TMU_UNLOCK_UNLOCK_SHIFT; + return (TMU_LockType)u32TmpVal; +} + +/** + * @brief Set the status of whether the temperature sensor register is locked or not + * + * @param pTmu the base address of the TMU instance + * @param eLockStatus Select the TF_CTRL and TV_CTRL register is lock or not + */ +LOCAL_INLINE void TMU_HWA_SetTemperatureLockStatus(TMU_Type *const pTmu,TMU_LockType eLockStatus) +{ + if((bool)eLockStatus) + { + pTmu->UNLOCK = 0xA5A50000U | TMU_UNLOCK_UNLOCK(eLockStatus); + }else + { + pTmu->UNLOCK = TMU_UNLOCK_UNLOCK(eLockStatus); + } +} + +/** + * @brief Get the Flag-based temperature sensor over 150 Celsius interrupt flag + * + * @param pTmu the base address of the TMU instance + * @return true Temperature over 150 Celsius interrupt is enabled + * @return false Temperature over 150 Celsius interrupt is disabled + */ +LOCAL_INLINE bool TMU_HWA_GetFlagTemperature150InterruptFlag(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = (pTmu->TF_CTRL & TMU_TF_CTRL_TF_150F_IE_MASK) >> TMU_TF_CTRL_TF_150F_IE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the Flag-based temperature sensor over 150 Celsius interrupt flag + * + * @param pTmu the base address of the TMU instance + * @param bEnable whether to enable the temperature over 150 Celsius interrupt + */ +LOCAL_INLINE void TMU_HWA_SetFlagTemperature150InterruptFlag(TMU_Type *const pTmu,bool bEnable) +{ + pTmu->TF_CTRL = (pTmu->TF_CTRL & ~TMU_TF_CTRL_TF_150F_IE_MASK) | TMU_TF_CTRL_TF_150F_IE(bEnable); +} + +/** + * @brief Get the Flag-based temperature sensor over 125 Celsius interrupt flag + * + * @param pTmu the base address of the TMU instance + * @return true Temperature over 125 Celsius interrupt is enabled + * @return false Temperature over 125 Celsius interrupt is disabled + */ +LOCAL_INLINE bool TMU_HWA_GetFlagTemperature125InterruptFlag(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = (pTmu->TF_CTRL & TMU_TF_CTRL_TF_125F_IE_MASK) >> TMU_TF_CTRL_TF_125F_IE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the Flag-based temperature sensor over 125 Celsius interrupt flag + * + * @param pTmu the base address of the TMU instance + * @param bEnable whether to enable the temperature over 125 Celsius interrupt + */ +LOCAL_INLINE void TMU_HWA_SetFlagTemperature125InterruptFlag(TMU_Type *const pTmu,bool bEnable) +{ + pTmu->TF_CTRL = (pTmu->TF_CTRL & ~TMU_TF_CTRL_TF_125F_IE_MASK) | TMU_TF_CTRL_TF_125F_IE(bEnable); +} + +/** + * @brief Get the Flag-based temperature sensor ready interrupt flag + * + * @param pTmu the base address of the TMU instance + * @return true Temperature sensor ready interrupt is enabled + * @return false Temperature sensor ready interrupt is disabled + */ +LOCAL_INLINE bool TMU_HWA_GetFlagTemperatureReadyInterruptFlag(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = (pTmu->TF_CTRL & TMU_TF_CTRL_TF_RDYF_IE_MASK) >> TMU_TF_CTRL_TF_RDYF_IE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the Flag-based temperature sensor over ready interrupt flag + * + * @param pTmu the base address of the TMU instance + * @param bEnable whether to enable the temperature sensor ready interrupt + */ +LOCAL_INLINE void TMU_HWA_SetFlagTemperatureReadyInterruptFlag(TMU_Type *const pTmu,bool bEnable) +{ + pTmu->TF_CTRL = (pTmu->TF_CTRL & ~TMU_TF_CTRL_TF_RDYF_IE_MASK) | TMU_TF_CTRL_TF_RDYF_IE(bEnable); +} + +/** + * @brief Get the Flag-based temperature sensor hysteresis control status + * + * @param pTmu the base address of the TMU instance + * @return true Temperature sensor Hysteresis is off + * @return false Temperature sensor Hysteresis is on + */ +LOCAL_INLINE bool TMU_HWA_GetFlagTemperatureHysteresisStatus(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = (pTmu->TF_CTRL & TMU_TF_CTRL_TF_HYSOFF_MASK) >> TMU_TF_CTRL_TF_HYSOFF_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the Flag-based temperature sensor hysteresis control status + * + * @param pTmu the base address of the TMU instance + * @param bEnable whether to off(1)/on(0) the temperature sensor hysteresis + */ +LOCAL_INLINE void TMU_HWA_SetFlagTemperatureHysteresisStatus(TMU_Type *const pTmu,bool bEnable) +{ + pTmu->TF_CTRL = (pTmu->TF_CTRL & ~TMU_TF_CTRL_TF_HYSOFF_MASK) | TMU_TF_CTRL_TF_HYSOFF(bEnable); +} + +/** + * @brief Get the Flag-based temperature sensor startup counter + * + * @param pTmu the base address of the TMU instance + * @return u32TmpVal count of the startup + */ +LOCAL_INLINE uint8_t TMU_HWA_GetFlagTemperatureCounter(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = (pTmu->TF_CTRL & TMU_TF_CTRL_TF_START_CNT_MASK) >> TMU_TF_CTRL_TF_START_CNT_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set the Flag-based temperature sensor startup counter + * + * @param pTmu the base address of the TMU instance + * @param u8Counter the startup counter + */ +LOCAL_INLINE void TMU_HWA_SetFlagTemperatureCounter(TMU_Type *const pTmu,uint8_t u8Counter) +{ + pTmu->TF_CTRL = (pTmu->TF_CTRL & ~TMU_TF_CTRL_TF_START_CNT_MASK) | TMU_TF_CTRL_TF_START_CNT(u8Counter); +} + +/** + * @brief Get the Flag-based temperature sensor filter bypass control status + * + * @param pTmu the base address of the TMU instance + * @return true Temperature sensor Filter is enabled + * @return false Temperature sensor Filter is bypassed + */ +LOCAL_INLINE bool TMU_HWA_GetFlagTemperatureFilterBypassStatus(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = (pTmu->TF_CTRL & TMU_TF_CTRL_TF_FILT_BYP_MASK) >> TMU_TF_CTRL_TF_FILT_BYP_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the Flag-based temperature sensor filter bypass control status + * + * @param pTmu the base address of the TMU instance + * @param bEnable whether the temperature sensor filter is enabled(1) or bypassed(0) + */ +LOCAL_INLINE void TMU_HWA_SetFlagTemperatureFilterBypassStatus(TMU_Type *const pTmu,bool bEnable) +{ + pTmu->TF_CTRL = (pTmu->TF_CTRL & ~TMU_TF_CTRL_TF_FILT_BYP_MASK) | TMU_TF_CTRL_TF_FILT_BYP(bEnable); +} + +/** + * @brief Get the Flag-based temperature sensor enable status + * + * @param pTmu the base address of the TMU instance + * @return true Temperature sensor is on + * @return false Temperature sensor is off + */ +LOCAL_INLINE bool TMU_HWA_GetFlagTemperatureEnableStatus(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = (pTmu->TF_CTRL & TMU_TF_CTRL_TF_EN_MASK) >> TMU_TF_CTRL_TF_EN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the Flag-based temperature sensor enable status + * + * @param pTmu the base address of the TMU instance + * @param bEnable whether the temperature sensor is on(1) or off(0) + */ +LOCAL_INLINE void TMU_HWA_SetFlagTemperatureEnableStatus(TMU_Type *const pTmu,bool bEnable) +{ + pTmu->TF_CTRL = (pTmu->TF_CTRL & ~TMU_TF_CTRL_TF_EN_MASK) | TMU_TF_CTRL_TF_EN(bEnable); +} + +/** + * @brief Check whether the temperature is over 150 Celsius + * + * @param pTmu the base address of the TMU instance + * @return true the temperature is over 150 Celsius + * @return false the temperature is not over 150 Celsius + */ +LOCAL_INLINE bool TMU_HWA_Get150Status(TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = pTmu->TF_STATUS; + u32TmpVal = (u32TmpVal & TMU_TF_STATUS_TF_150_MASK) >> TMU_TF_STATUS_TF_150_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Check whether the temperature is over 125 Celsius + * + * @param pTmu the base address of the TMU instance + * @return true the temperature is over 125 Celsius + * @return false the temperature is not over 125 Celsius + */ +LOCAL_INLINE bool TMU_HWA_Get125Status(TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = pTmu->TF_STATUS; + u32TmpVal = (u32TmpVal & TMU_TF_STATUS_TF_125_MASK) >> TMU_TF_STATUS_TF_125_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Check whether the flag for temperature over 150 Celsius is set + * + * @param pTmu the base address of the TMU instance + * @return true the temperature has exceeded 150 Celsius since last time W1C + * @return false the temperature has not exceeded 150 Celsius since TF is ready + */ +LOCAL_INLINE bool TMU_HWA_Get150Flag(TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = pTmu->TF_STATUS; + u32TmpVal = (u32TmpVal & TMU_TF_STATUS_TF_150F_MASK) >> TMU_TF_STATUS_TF_150F_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the temperature over 150 Celsius flag + * + * @param pTmu the base address of the TMU instance + */ +LOCAL_INLINE void TMU_HWA_Clear150Flag(TMU_Type *const pTmu) +{ + pTmu->TF_STATUS |= TMU_TF_STATUS_TF_150F(1U); +} + +/** + * @brief Check whether the flag for temperature over 125 Celsius is set + * + * @param pTmu the base address of the TMU instance + * @return true the temperature has exceeded 125 Celsius since last time W1C + * @return false the temperature has not exceeded 125 Celsius since TF is ready + */ +LOCAL_INLINE bool TMU_HWA_Get125Flag(TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = pTmu->TF_STATUS; + u32TmpVal = (u32TmpVal & TMU_TF_STATUS_TF_125F_MASK) >> TMU_TF_STATUS_TF_125F_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the temperature over 125 Celsius flag + * + * @param pTmu the base address of the TMU instance + */ +LOCAL_INLINE void TMU_HWA_Clear125Flag(TMU_Type *const pTmu) +{ + pTmu->TF_STATUS |= TMU_TF_STATUS_TF_125F(1U); +} + +/** + * @brief Check whether the Flag-based temperature sensor is ready + * + * @param pTmu the base address of the TMU instance + * @return true the Flag-based temperature sensor is ready + * @return false the Flag-based temperature sensor is not ready + */ +LOCAL_INLINE bool TMU_HWA_GetFlagTemperatureReady(TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = pTmu->TF_STATUS; + u32TmpVal = (u32TmpVal & TMU_TF_STATUS_TF_RDYF_MASK) >> TMU_TF_STATUS_TF_RDYF_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the Flag-based temperature sensor ready flag + * + * @param pTmu the base address of the TMU instance + */ +LOCAL_INLINE void TMU_HWA_ClearFlagTemperatureReady(TMU_Type *const pTmu) +{ + pTmu->TF_STATUS |= TMU_TF_STATUS_TF_RDYF(1U); +} + +/** + * @brief Get the Vlotage-based temperature sensor ready interrupt flag + * + * @param pTmu the base address of the TMU instance + * @return true Temperature sensor ready interrupt is enabled + * @return false Temperature sensor ready interrupt is disabled + */ +LOCAL_INLINE bool TMU_HWA_GetVoltageTemperatureReadyInterruptFlag(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = (pTmu->TV_CTRL & TMU_TV_CTRL_TV_RDYF_IE_MASK) >> TMU_TV_CTRL_TV_RDYF_IE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the Voltage-based temperature sensor over ready interrupt flag + * + * @param pTmu the base address of the TMU instance + * @param bEnable whether to enable the temperature sensor ready interrupt + */ +LOCAL_INLINE void TMU_HWA_SetVoltageTemperatureReadyInterruptFlag(TMU_Type *const pTmu,bool bEnable) +{ + pTmu->TV_CTRL = (pTmu->TV_CTRL & ~TMU_TV_CTRL_TV_RDYF_IE_MASK) | TMU_TV_CTRL_TV_RDYF_IE(bEnable); +} + +/** + * @brief Get the Voltage-based temperature sensor startup counter + * + * @param pTmu the base address of the TMU instance + * @return u32TmpVal count of the startup + */ +LOCAL_INLINE uint8_t TMU_HWA_GetVoltageTemperatureCounter(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = (pTmu->TV_CTRL & TMU_TV_CTRL_TV_START_CNT_MASK) >> TMU_TV_CTRL_TV_START_CNT_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set the Voltage-based temperature sensor startup counter + * + * @param pTmu the base address of the TMU instance + * @param u8Counter the startup counter + */ +LOCAL_INLINE void TMU_HWA_SetVoltageTemperatureCounter(TMU_Type *const pTmu,uint8_t u8Counter) +{ + pTmu->TV_CTRL = (pTmu->TV_CTRL & ~TMU_TV_CTRL_TV_START_CNT_MASK) | TMU_TV_CTRL_TV_START_CNT(u8Counter); +} + +/** + * @brief Get the Voltage-based temperature sensor enable status + * + * @param pTmu the base address of the TMU instance + * @return true Temperature sensor is on + * @return false Temperature sensor is off + */ +LOCAL_INLINE bool TMU_HWA_GetVoltageTemperatureEnableStatus(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = (pTmu->TV_CTRL & TMU_TV_CTRL_TV_EN_MASK) >> TMU_TV_CTRL_TV_EN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set the Voltage-based temperature sensor enable status + * + * @param pTmu the base address of the TMU instance + * @param bEnable whether the temperature sensor is on(1) or off(0) + */ +LOCAL_INLINE void TMU_HWA_SetVoltageTemperatureEnableStatus(TMU_Type *const pTmu,bool bEnable) +{ + pTmu->TV_CTRL = (pTmu->TV_CTRL & ~TMU_TV_CTRL_TV_EN_MASK) | TMU_TV_CTRL_TV_EN(bEnable); +} + +/** + * @brief Check whether the Voltage-based temperature sensor is ready + * + * @param pTmu the base address of the TMU instance + * @return true the Voltage-based temperature sensor is ready + * @return false the Voltage-based temperature sensor is not ready + */ +LOCAL_INLINE bool TMU_HWA_GetVoltageTemperatureReady(TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = pTmu->TV_STATUS; + u32TmpVal = (u32TmpVal & TMU_TV_STATUS_TV_RDYF_MASK) >> TMU_TV_STATUS_TV_RDYF_SHIFT; + + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear the Voltage-based temperature sensor ready flag + * + * @param pTmu the base address of the TMU instance + */ +LOCAL_INLINE void TMU_HWA_ClearVoltageTemperatureReady(TMU_Type *const pTmu) +{ + pTmu->TV_STATUS |= TMU_TV_STATUS_TV_RDYF(1U); +} + +/** + * @brief Get the TMU_TF_CTRL config + * + * @param pTmu the base address of the TMU instance + * @return uint32_t the TMU_TF_CTRL config + */ +LOCAL_INLINE uint32_t TMU_HWA_GetFlagTempCtrl(const TMU_Type *const pTmu) +{ + return pTmu->TF_CTRL; +} + +/** + * @brief Set the TMU_TF_CTRL config + * + * @param pTmu the base address of the TMU instance + * @param u32Config the TMU_TF_CTRL config + */ +LOCAL_INLINE void TMU_HWA_SetFlagTempCtrl(TMU_Type *const pTmu, uint32_t u32Config) +{ + pTmu->TF_CTRL = u32Config; +} + +/** + * @brief Get the TMU_TV_CTRL config + * + * @param pTmu the base address of the TMU instance + * @return uint32_t the TMU_TV_CTRL config + */ +LOCAL_INLINE uint32_t TMU_HWA_GetVoltageTempCtrl(const TMU_Type *const pTmu) +{ + return pTmu->TV_CTRL; +} + +/** + * @brief Set the TMU_TV_CTRL config + * + * @param pTmu the base address of the TMU instance + * @param u32Config the TMU_TV_CTRL config + */ +LOCAL_INLINE void TMU_HWA_SetVoltageTempCtrl(TMU_Type *const pTmu, uint32_t u32Config) +{ + pTmu->TV_CTRL = u32Config; +} + +/** + * @brief Controls the stop ack function enable or not to the TMU0 + * + * @param bEnable set the ACK enable or not + */ +LOCAL_INLINE void TMU_HWA_SetStopAck(bool bEnable) +{ + if(bEnable) + { + CSC0_HWA_MODER0_EnableStopAck(CSC_STOPMODE_TMU); + } + else + { + CSC0_HWA_MODER0_DisableStopAck(CSC_STOPMODE_TMU); + } +} + +/** + * @brief Get the TV_TRIM_TV_TCODE value + * + * @param pTmu the base address of the TMU instance + * @return uint32_t the TV_TRIM_TV_TCODE value + */ +LOCAL_INLINE uint32_t TMU_HWA_GetTemperatureCode(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = pTmu->TV_TRIM; + u32TmpVal = (u32TmpVal & TMU_TV_TRIM_TV_TCODE_MASK) >> TMU_TV_TRIM_TV_TCODE_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get the TV_TRIM_TV_SLOPE value + * + * @param pTmu the base address of the TMU instance + * @return uint32_t the TV_TRIM_TV_SLOPE value + */ +LOCAL_INLINE uint32_t TMU_HWA_GetSlopeFactor(const TMU_Type *const pTmu) +{ + uint32_t u32TmpVal = pTmu->TV_TRIM; + u32TmpVal = (u32TmpVal & TMU_TV_TRIM_TV_SLOPE_MASK) >> TMU_TV_TRIM_TV_SLOPE_SHIFT; + return u32TmpVal; +} + +/** @}*/ + +#endif /* _HWA_TMU_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_tpue.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_tpue.h new file mode 100644 index 0000000..370e737 --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_tpue.h @@ -0,0 +1,2062 @@ +/** + * @file HwA_tpue.h + * @author Flagchip + * @brief FC7xxx TPUE hardware access layer + * @version 0.1.0 + * @date 2024-1-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ + +#ifndef _HWA_TPUE_H_ +#define _HWA_TPUE_H_ + +#include "device_header.h" + +/********* Local typedef ************/ + +/** @brief TPU channel digital filter control type */ +typedef enum +{ + TPUE_TWO_SAMPLE_MODE = 0U, + TPUE_BYPASS_MODE = 1U, + TPUE_THREE_SAMPLE_MODE = 2U, + TPUE_CONTINUOUS_MODE = 3U +} TPUE_FilterCtrlType; + +/** @brief TPU filter clock source selection type */ +typedef enum +{ + TPUE_TPU_CLK_DIV2 = 0U, + TPUE_TPU_CLK = 1U +} TPUE_FilterClkSrcType; + +/** @brief TPU channel digital filter control type */ +typedef enum +{ + TPUE_SYSCLK_DIV_1 = 0U, + TPUE_SYSCLK_DIV_2 = 1U, + TPUE_SYSCLK_DIV_4 = 2U, + TPUE_SYSCLK_DIV_8 = 3U, + TPUE_SYSCLK_DIV_16 = 4U, + TPUE_SYSCLK_DIV_32 = 5U, + TPUE_SYSCLK_DIV_64 = 6U, + TPUE_SYSCLK_DIV_128 = 7U +} TPUE_FilterPrescalerCtrlType; + +/** @brief TPU TCR1 clock control mode type */ +typedef enum +{ + TPUE_TCR1CLK_CLK_SRC = 0U, + TPUE_TCR1CLK_UPDOWN_CNT_MODE = 3U, + TPUE_TCR1CLK_CLK_SRC_TPUCLKDIV2 = 4U, + TPUE_TCR1CLK_SRC_TPUCLK = 5U +} TPUE_TCR1ClkCtrlModeType; + +/** @brief TPU angle tick gen clk type */ +typedef enum +{ + TPUE_TCR1_PRESCAL_OUTPUT = 0U, + TPUE_TCR2_PRESCAL_OUTPUT = 1U +} TPUE_AngleTickGenClkType; + +/** @brief TPU Angle Mode Selection type */ +typedef enum +{ + TPUE_TCR2_TIMEBASE_EAC_DISABLE = 0U, + TPUE_TOOTHSIGNAL_AS_TCRCLK_TOOTH_CH_0 = 1U, + TPUE_TOOTHSIGNAL_AS_CH1INPUT_TOOTH_CH_1 = 2U, + TPUE_TOOTHSIGNAL_AS_CH1INPUT_TOOTH_CH_2 = 3U +} TPUE_AngleModeSel; + +/** @brief TPU Angle Mode Selection type */ +typedef enum +{ + TPUE_TWO_SAMPLE_MODE_TPU_CLK_DIV2 = 0U, + TPUE_TWO_SAMPLE_MODE_CH_CLK = 1U, + TPUE_INTEGRATOR_MODE_TPU_CLK_DIV2 = 2U, + TPUE_INTEGRATOR_MODE_CH_CLK = 3U +} TPUE_TCRClkFilterType; + +/** @brief TPU TCR2 clock control mode0 type */ +typedef enum +{ + TPUE_GATED_DIV8_CLK = 0U, + TPUE_RISE_TRANSITION_INCREMENT_TCR2_PRESCALER = 1U, + TPUE_FALL_TRANSITION_INCREMENT_TCR2_PRESCALER = 2U, + TPUE_DIV8_CLK = 4U, + TPUE_UPDOWN_CNT_MODE = 5U, + TPUE_FROZEN = 7U +} TPUE_TCR1ClkCtrlMode0Type; + +typedef enum +{ + TPUE_RSING_EDGE = 1U, + TPUE_FALLING_EDGE = 2U, + TPUE_BOTH_EDGES = 3U, + TPUE_NO_EDGE = 6U, +} TPUE_TCR1ClkCtrlMode1Type; + +/** @brief Missing Tooth Counter */ +typedef enum +{ + TPUE_NOT_A_MISSING_TOOTH = 0U, + TPUE_ONE_MISSING_TOOTH = 1U, + TPUE_TWO_MISSING_TOOTH = 2U, + TPUE_THREE_MISSING_TOOTH = 3U, +} TPUE_MissToothCntType; + +/** @brief Channel Trigger Configuration */ +typedef enum +{ + TPUE_DISABLED = 0U, + TPUE_ANY_EVENT_GATED_BY_MSRTSR = 2U, + TPUE_HSA_EVENT_ON_FLEXCORE_MODE = 3U, + TPUE_MRL1_EVENT_NOT_GATED_BY_MSR = 4U, + TPUE_MRL2_EVENT_NOT_GATED_BY_MSR = 5U, + TPUE_MRL1_OR_MRL2_EVENT_NOT_GATED_BY_MSR = 6U, + TPUE_MRL1_AND_MRL2_EVENT_NOT_GATED_BY_MSR = 7U, + TPUE_TDL1_OR_TDL2_EVENT_NOT_GATED_BY_TSR = 8U, + TPUE_TDL1_AND_TDL2_EVENT_NOT_GATED_BY_TSR = 9U, + TPUE_EVENT_EQUAL_TO_CH_DO_LEVEL = 10U, + TPUE_EVENT_NEGATIVE_TO_CH_DO_LEVEL = 11U, + TPUE_EVENT_EQUAL_TO_CH_DO_PART1_LEVEL = 12U, + TPUE_EVENT_EQUAL_TO_CH_DO_PART2_LEVEL = 13U, + TPUE_EVENT_EQUAL_TO_CH_IND_LEVEL = 14U, + TPUE_EVENT_EQUAL_TO_CH_IND_LATCH_LEVEL = 15U, +} TPUE_ChTrigCFGType; + +/** @brief Filter Grade for 7 value in 1 loop */ +typedef enum +{ + TPUE_FILTER_DISABLE = 0U, + TPUE_FILTER_LOW = 1U, + TPUE_FILTER_MIDDLE = 2U, + TPUE_FILTER_HIGH = 3U, +} TPUE_FilterGradeType; + +/** @brief Channel event triggered interrupt priority */ +typedef enum +{ + TPUE_PRIORITY_DISABLE = 0U, + TPUE_PRIORITY_LOW = 1U, + TPUE_PRIORITY_MIDDLE = 2U, + TPUE_PRIORITY_HIGH = 3U, +} TPUE_EventIntPriorityType; + +/** @brief Channel time base selection of part 1. */ +typedef enum +{ + TPUE_GREATER_OR_EQUAL_CAPBASE_TCR1_MATCHBASE_TCR1 = 0U, + TPUE_GREATER_OR_EQUAL_CAPBASE_TCR1_MATCHBASE_TCR2 = 1U, + TPUE_GREATER_OR_EQUAL_CAPBASE_TCR2_MATCHBASE_TCR1 = 2U, + TPUE_GREATER_OR_EQUAL_CAPBASE_TCR2_MATCHBASE_TCR2 = 3U, + TPUE_EQUAL_ONLY_CAPBASE_TCR1_MATCHBASE_TCR1 = 4U, + TPUE_EQUAL_ONLY_CAPBASE_TCR1_MATCHBASE_TCR2 = 5U, + TPUE_EQUAL_ONLY_CAPBASE_TCR2_MATCHBASE_TCR1 = 6U, + TPUE_EQUAL_ONLY_CAPBASE_TCR2_MATCHBASE_TCR2 = 7U, +} TPUE_TimeBaseSelctionType; + +/** @brief Channel Input Pin Action Control. */ +typedef enum +{ + TPUE_NO_TRANSITIONS = 0U, + TPUE_DETECT_RISING_EDGE_ONLY = 1U, + TPUE_DETECT_FALLING_EDGE_ONLY = 2U, + TPUE_DETECT_EITHER_EDGE_ONLY = 3U, + TPUE_DETECT_SIGNAL_0_ON_MATCH = 4U, + TPUE_DETECT_SIGNAL_1_ON_MATCH = 5U, +} TPUE_IPACType; + +/** @brief Channel output Pin Action Control. */ +typedef enum +{ + TPUE_NO_CHANGE_OUTPUT = 0U, + TPUE_MATCH_SET_OUTPUT_HIGH = 1U, + TPUE_MATCH_SET_OUTPUT_LOW = 2U, + TPUE_MATCH_TOGGLE_OUTPUT = 3U, + TPUE_TRANSITION_SET_OUTPUT_HIGH = 4U, + TPUE_TRANSITION_SET_OUTPUT_LOW = 5U, + TPUE_TRANSITION_TOGGLE_OUTPUT = 6U, + TPUE_NO_CHANGE_OPAC = 7U, +} TPUE_OPACType; + +/** @brief PDCM Encoding. */ +typedef enum +{ + TPUE_EM_B_ST = 0U, + TPUE_EM_B_DT = 1U, + TPUE_EM_NB_ST = 2U, + TPUE_EM_NB_DT = 3U, + TPUE_M2_ST = 4U, + TPUE_M2_DT = 5U, + TPUE_BM_ST = 6U, + TPUE_BM_DT = 7U, + TPUE_M2_O_ST = 8U, + TPUE_M2_O_DT = 9U, + TPUE_SM_ST = 12U, + TPUE_SM_DT = 13U, + TPUE_SM_ST_E = 14U, +} TPUE_PDCMEncodeType; + +/********* Local inline function ************/ +/** + * @brief Get channel digital filter control + * + */ +LOCAL_INLINE TPUE_FilterCtrlType TPU_E_HWA_GetFilterCtrl(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_CR & TPU_E_GCR_CR_CDFC_MASK) >> TPU_E_GCR_CR_CDFC_SHIFT; + return (TPUE_FilterCtrlType)u32TmpVal; +} + +/** + * @brief Set channel digital filter control + * + */ +LOCAL_INLINE void TPU_E_HWA_SetFilterCtrl(TPU_E_Type *const pTPUE, TPUE_FilterCtrlType eControlMode) +{ + pTPUE->GCR_CR = (pTPUE->GCR_CR & ~TPU_E_GCR_CR_CDFC_MASK) | TPU_E_GCR_CR_CDFC(eControlMode); +} + +/** + * @brief Get filter clock source + * + */ +LOCAL_INLINE TPUE_FilterClkSrcType TPU_E_HWA_GetFilterClkSrc(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_CR & TPU_E_GCR_CR_FCSS_MASK) >> TPU_E_GCR_CR_FCSS_SHIFT; + return (TPUE_FilterClkSrcType)u32TmpVal; +} + +/** + * @brief Set filter clock source + * + */ +LOCAL_INLINE void TPU_E_HWA_SetFilterClkSrc(TPU_E_Type *const pTPUE, TPUE_FilterClkSrcType eClkSrc) +{ + pTPUE->GCR_CR = (pTPUE->GCR_CR & ~TPU_E_GCR_CR_FCSS_MASK) | TPU_E_GCR_CR_FCSS(eClkSrc); +} + +/** + * @brief Get filter prescaler clock control + * + */ +LOCAL_INLINE TPUE_FilterPrescalerCtrlType TPU_E_HWA_GetFilterPrescaler(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_CR & TPU_E_GCR_CR_FPSCK_MASK) >> TPU_E_GCR_CR_FPSCK_SHIFT; + return (TPUE_FilterPrescalerCtrlType)u32TmpVal; +} + +/** + * @brief Get filter prescaler clock control + * + */ +LOCAL_INLINE void TPU_E_HWA_SetFilterPrescaler(TPU_E_Type *const pTPUE, TPUE_FilterPrescalerCtrlType ePrescaler) +{ + pTPUE->GCR_CR = (pTPUE->GCR_CR & ~TPU_E_GCR_CR_FPSCK_MASK) | TPU_E_GCR_CR_FPSCK(ePrescaler); +} + +/** + * @brief Whether channel function is disabled in Stop mode + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetFuncDisableInStopMode(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_CR & TPU_E_GCR_CR_HALT_CH_MASK) >> TPU_E_GCR_CR_HALT_CH_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Enable channel function is disabled or normal in Stop mode + * + */ +LOCAL_INLINE void TPU_E_HWA_SetFuncDisableInStopMode(TPU_E_Type *const pTPUE, bool bEnable) +{ + pTPUE->GCR_CR = (pTPUE->GCR_CR & ~TPU_E_GCR_CR_HALT_CH_MASK) | TPU_E_GCR_CR_HALT_CH(bEnable); +} + +/** + * @brief Whether channel function is disabled in Stop mode + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetTimeBaseCntStopInStopMode(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_CR & TPU_E_GCR_CR_HALT_TB_MASK) >> TPU_E_GCR_CR_HALT_TB_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Enable channel function is disabled or normal in Stop mode + * + */ +LOCAL_INLINE void TPU_E_HWA_SetTimeBaseCntStopInStopMode(TPU_E_Type *const pTPUE, bool bEnable) +{ + pTPUE->GCR_CR = (pTPUE->GCR_CR & ~TPU_E_GCR_CR_HALT_TB_MASK) | TPU_E_GCR_CR_HALT_TB(bEnable); +} + +/** + * @brief Enable channel function is disabled or normal in Stop mode + * + */ +LOCAL_INLINE void TPU_E_HWA_TrigReset(TPU_E_Type *const pTPUE) +{ + pTPUE->GCR_SRR = 0xFC005AFEU; +} + +/** + * @brief Get service request status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetSRStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_VSR & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get pin input status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetInputStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_VIR & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get pin output status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetoutputStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_VOR & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get pin output enable status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetoutputEnStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_VOBR & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get MRL1 status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetMRL1Status(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_VM1R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get MRL2 status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetMRL2Status(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_VM2R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get TDL1 status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetTDL1Status(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_VT1R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get TDL2 status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetTDL2Status(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_VT2R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get MRL1 event status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetMRL1EventStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_EM1R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get MRL2 event status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetMRL2EventStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_EM2R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get TDL1 event status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetTDL1eventStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_ET1R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get TDL2 event status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetTDL2eventStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_ET2R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get HAS status of specific channel + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetHSRStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_VHSR & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get Filter Grade + * + */ +LOCAL_INLINE TPUE_FilterGradeType TPU_E_HWA_GetFilterGrade(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_AFGR & TPU_E_GCR_AFGR_FLT_GRD_MASK) >> TPU_E_GCR_AFGR_FLT_GRD_SHIFT; + return (TPUE_FilterGradeType)u32TmpVal; +} + +/** + * @brief Set Filter Grade + * + */ +LOCAL_INLINE void TPU_E_HWA_SetFilterGrade(TPU_E_Type *const pTPUE, TPUE_FilterGradeType eGrade) +{ + pTPUE->GCR_AFGR = (pTPUE->GCR_AFGR & ~TPU_E_GCR_AFGR_FLT_GRD_MASK) | TPU_E_GCR_AFGR_FLT_GRD(eGrade); +} + +/** + * @brief Get Filter Grade setting results + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetFilterGradeCFGErrFlg(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_ASR & TPU_E_GCR_ASR_ERROR_MASK) >> TPU_E_GCR_ASR_ERROR_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear filter grade setting results + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearFilterGradeCFGErrFlg(TPU_E_Type *const pTPUE) +{ + pTPUE->GCR_ASR = (pTPUE->GCR_ASR & ~TPU_E_GCR_ASR_ERROR_MASK) | TPU_E_GCR_ASR_ERROR(1U); +} + +/** + * @brief Get endian configuration + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetEndianCFG(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_ASR & TPU_E_GCR_ASR_ENDIAN_MASK) >> TPU_E_GCR_ASR_ENDIAN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set endian configuration + * + */ +LOCAL_INLINE void TPU_E_HWA_SetEndianCFG(TPU_E_Type *const pTPUE) +{ + pTPUE->GCR_ASR = (pTPUE->GCR_ASR & ~TPU_E_GCR_ASR_ENDIAN_MASK) | TPU_E_GCR_ASR_ENDIAN(1U); +} + +/** + * @brief Get channel function entry table select + * + */ +LOCAL_INLINE uint8_t TPU_E_HWA_GetEntryFuncSel(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_AID & TPU_E_GCR_AID_ETCS_MASK) >> TPU_E_GCR_AID_ETCS_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Get channel function entry table condition + * + */ +LOCAL_INLINE uint8_t TPU_E_HWA_GetEntryFuncCond(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_AID & TPU_E_GCR_AID_COND_MASK) >> TPU_E_GCR_AID_COND_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Get channel ID info + * + */ +LOCAL_INLINE uint8_t TPU_E_HWA_GetChIDInfo(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->GCR_AID & TPU_E_GCR_AID_ID_MASK) >> TPU_E_GCR_AID_ID_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Get TCR1 prescaler. + * + */ +LOCAL_INLINE uint8_t TPU_E_HWA_GetTCR1Prescaler(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_CR & TPU_E_TBR_CR_TCR1P_MASK) >> TPU_E_TBR_CR_TCR1P_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Get TCR1 prescaler. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetTCR1Prescaler(TPU_E_Type *const pTPUE, uint8_t u8Prescaler) +{ + pTPUE->TBR_CR = (pTPUE->TBR_CR & ~TPU_E_TBR_CR_TCR1P_MASK) | TPU_E_TBR_CR_TCR1P(u8Prescaler); +} + +/** + * @brief Get TCR1 clock control. + * + */ +LOCAL_INLINE TPUE_TCR1ClkCtrlModeType TPU_E_HWA_GetTCR1ClkControl(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_CR & TPU_E_TBR_CR_TCR1CTL_MASK) >> TPU_E_TBR_CR_TCR1CTL_SHIFT; + return (TPUE_TCR1ClkCtrlModeType)u32TmpVal; +} + +/** + * @brief Set TCR1 clock control. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetTCR1ClkControl(TPU_E_Type *const pTPUE, TPUE_TCR1ClkCtrlModeType eMode) +{ + pTPUE->TBR_CR = (pTPUE->TBR_CR & ~TPU_E_TBR_CR_TCR1CTL_MASK) | TPU_E_TBR_CR_TCR1CTL(eMode); +} + +/** + * @brief Get TCR2 prescaler. + * + */ +LOCAL_INLINE uint8_t TPU_E_HWA_GetTCR2Prescaler(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_CR & TPU_E_TBR_CR_TCR2P_MASK) >> TPU_E_TBR_CR_TCR2P_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set TCR2 prescaler. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetTCR2Prescaler(TPU_E_Type *const pTPUE, uint8_t ePrescaler) +{ + pTPUE->TBR_CR = (pTPUE->TBR_CR & ~TPU_E_TBR_CR_TCR2P_MASK) | TPU_E_TBR_CR_TCR2P(ePrescaler); +} + +/** + * @brief Get Angle tick generator clock. + * + */ +LOCAL_INLINE TPUE_AngleTickGenClkType TPU_E_HWA_GetATGC(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_CR & TPU_E_TBR_CR_ATGC_MASK) >> TPU_E_TBR_CR_ATGC_SHIFT; + return (TPUE_AngleTickGenClkType)u32TmpVal; +} + +/** + * @brief Set Angle tick generator clock. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetATGC(TPU_E_Type *const pTPUE, TPUE_AngleTickGenClkType eSrc) +{ + pTPUE->TBR_CR = (pTPUE->TBR_CR & ~TPU_E_TBR_CR_ATGC_MASK) | TPU_E_TBR_CR_ATGC(eSrc); +} + +/** + * @brief Get Angle Mode Selection. + * + */ +LOCAL_INLINE TPUE_AngleModeSel TPU_E_HWA_GetAM(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_CR & TPU_E_TBR_CR_AM_MASK) >> TPU_E_TBR_CR_AM_SHIFT; + return (TPUE_AngleModeSel)u32TmpVal; +} + +/** + * @brief Set Angle Mode Selection. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetAM(TPU_E_Type *const pTPUE, TPUE_AngleModeSel eMode) +{ + pTPUE->TBR_CR = (pTPUE->TBR_CR & ~TPU_E_TBR_CR_AM_MASK) | TPU_E_TBR_CR_AM(eMode); +} + +/** + * @brief Get TCRCLK signal Filter Control. + * + */ +LOCAL_INLINE TPUE_TCRClkFilterType TPU_E_HWA_GetTCRClkFilter(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_CR & TPU_E_TBR_CR_TCRCF_MASK) >> TPU_E_TBR_CR_TCRCF_SHIFT; + return (TPUE_TCRClkFilterType)u32TmpVal; +} + +/** + * @brief Set TCRCLK signal Filter Control. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetTCRClkFilter(TPU_E_Type *const pTPUE, TPUE_TCRClkFilterType eMode) +{ + pTPUE->TBR_CR = (pTPUE->TBR_CR & ~TPU_E_TBR_CR_TCRCF_MASK) | TPU_E_TBR_CR_TCRCF(eMode); +} + +/** + * @brief Get TCR2 clock control. + * + */ +LOCAL_INLINE TPUE_TCR1ClkCtrlMode0Type TPU_E_HWA_GetTCR2ClkControlAM0(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_CR & TPU_E_TBR_CR_TCR2CTL_MASK) >> TPU_E_TBR_CR_TCR2CTL_SHIFT; + return (TPUE_TCR1ClkCtrlMode0Type)u32TmpVal; +} + +/** + * @brief Get TCR2 clock control. + * + */ +LOCAL_INLINE TPUE_TCR1ClkCtrlMode1Type TPU_E_HWA_GetTCR2ClkControlAM1(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_CR & TPU_E_TBR_CR_TCR2CTL_MASK) >> TPU_E_TBR_CR_TCR2CTL_SHIFT; + return (TPUE_TCR1ClkCtrlMode1Type)u32TmpVal; +} + +/** + * @brief Set TCR2 clock control. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetTCR2ClkControlAM1(TPU_E_Type *const pTPUE, TPUE_TCR1ClkCtrlMode1Type eMode) +{ + pTPUE->TBR_CR = (pTPUE->TBR_CR & ~TPU_E_TBR_CR_TCR2CTL_MASK) | TPU_E_TBR_CR_TCR2CTL(eMode); +} + +/** + * @brief Get TCR1 cnt value. + * + */ +LOCAL_INLINE uint32_t TPU_E_HWA_GetTCR1CntVal(const TPU_E_Type *const pTPUE) +{ + return pTPUE->TBR_T1R; +} + +/** + * @brief Get TCR2 cnt value. + * + */ +LOCAL_INLINE uint32_t TPU_E_HWA_GetTCR2CntVal(const TPU_E_Type *const pTPUE) +{ + return pTPUE->TBR_T2R; +} + +/** + * @brief Get last tooth indication. + * + */ +LOCAL_INLINE bool TPU_E_HWA_NotLastTooth(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_TPR & TPU_E_TBR_TPR_LAST_MASK) >> TPU_E_TBR_TPR_LAST_SHIFT; + return (bool)((u32TmpVal == 0U) ? true : false); +} + +/** + * @brief Set last tooth indication. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetLastTooth(TPU_E_Type *const pTPUE, bool bEnable) +{ + pTPUE->TBR_TPR = (pTPUE->TBR_TPR & ~TPU_E_TBR_TPR_LAST_MASK) | TPU_E_TBR_TPR_LAST(bEnable); +} + +/** + * @brief Get missing tooth counter. + * + */ +LOCAL_INLINE TPUE_MissToothCntType TPU_E_HWA_GetMissingTooth(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_TPR & TPU_E_TBR_TPR_MISSCNT_MASK) >> TPU_E_TBR_TPR_MISSCNT_SHIFT; + return (TPUE_MissToothCntType)u32TmpVal; +} + +/** + * @brief Set missing tooth counter. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetMissingTooth(TPU_E_Type *const pTPUE, TPUE_MissToothCntType eCnt) +{ + pTPUE->TBR_TPR = (pTPUE->TBR_TPR & ~TPU_E_TBR_TPR_MISSCNT_MASK) | TPU_E_TBR_TPR_MISSCNT(eCnt); +} + +/** + * @brief Get last tooth indication. + * + */ +LOCAL_INLINE bool TPU_E_HWA_NoInsertTooth(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_TPR & TPU_E_TBR_TPR_IPH_MASK) >> TPU_E_TBR_TPR_IPH_SHIFT; + return (bool)((u32TmpVal == 0U) ? true : false); +} + +/** + * @brief Set last tooth indication to exit halt mode. + * + */ +LOCAL_INLINE void TPU_E_HWA_InsertPhyTooth(TPU_E_Type *const pTPUE) +{ + pTPUE->TBR_TPR = (pTPUE->TBR_TPR & ~TPU_E_TBR_TPR_IPH_MASK) | TPU_E_TBR_TPR_IPH(1U); +} + +/** + * @brief Get last tooth indication. + * + */ +LOCAL_INLINE bool TPU_E_HWA_NoForceEACHalt(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_TPR & TPU_E_TBR_TPR_HOLD_MASK) >> TPU_E_TBR_TPR_HOLD_SHIFT; + return (bool)((u32TmpVal == 0U) ? true : false); +} + +/** + * @brief Get last tooth indication. + * + */ +LOCAL_INLINE void TPU_E_HWA_HaltEAC(TPU_E_Type *const pTPUE) +{ + pTPUE->TBR_TPR = (pTPUE->TBR_TPR & ~TPU_E_TBR_TPR_HOLD_MASK) | TPU_E_TBR_TPR_HOLD(1U); +} + +/** + * @brief Get angle ticks number. + * + */ +LOCAL_INLINE uint16_t TPU_E_HWA_GetAngleTicksVal(const TPU_E_Type *const pTPUE) +{ + return (uint16_t)(pTPUE->TBR_TPR & TPU_E_TBR_TPR_TICKS_MASK) >> TPU_E_TBR_TPR_TICKS_SHIFT; +} + +/** + * @brief Get angle ticks number. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetAngleTicksVal(TPU_E_Type *const pTPUE, uint16_t u16Tick) +{ + pTPUE->TBR_TPR = (pTPUE->TBR_TPR & ~TPU_E_TBR_TPR_TICKS_MASK) | TPU_E_TBR_TPR_TICKS(u16Tick); +} + +/** + * @brief Get the integer part of TCR1 clocks in one Angle tick. + * + */ +LOCAL_INLINE uint32_t TPU_E_HWA_GetIntergerPerAngleTick(const TPU_E_Type *const pTPUE) +{ + return (pTPUE->TBR_TRR & TPU_E_TBR_TRR_INTEGER_MASK) >> TPU_E_TBR_TRR_INTEGER_SHIFT; +} + +/** + * @brief Set the integer part of TCR1 clocks in one Angle tick. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetIntergerPerAngleTick(TPU_E_Type *const pTPUE, uint16_t u16Integer) +{ + pTPUE->TBR_TRR = (pTPUE->TBR_TRR & ~TPU_E_TBR_TRR_INTEGER_MASK) | TPU_E_TBR_TRR_INTEGER(u16Integer); +} + +/** + * @brief Get the fraction part of TCR1 clocks in one Angle tick. + * + */ +LOCAL_INLINE uint32_t TPU_E_HWA_GetFractionPerAngleTick(const TPU_E_Type *const pTPUE) +{ + return (pTPUE->TBR_TRR & TPU_E_TBR_TRR_FRACTION_MASK) >> TPU_E_TBR_TRR_FRACTION_SHIFT; +} + +/** + * @brief Set the fraction part of TCR1 clocks in one Angle tick. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetFractionPerAngleTick(TPU_E_Type *const pTPUE, uint16_t u16Fraction) +{ + pTPUE->TBR_TRR = (pTPUE->TBR_TRR & ~TPU_E_TBR_TRR_FRACTION_MASK) | TPU_E_TBR_TRR_FRACTION(u16Fraction); +} + +/** + * @brief Get TCR1 overflow flag. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetTCR1Overflow(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_T1MR & TPU_E_TBR_T1MR_OVF_MASK) >> TPU_E_TBR_T1MR_OVF_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear TCR1 overflow flag. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearTCR1Overflow(TPU_E_Type *const pTPUE) +{ + pTPUE->TBR_T1MR = (pTPUE->TBR_T1MR | TPU_E_TBR_T1MR_OVF_MASK); +} + +/** + * @brief Get TCR1 IRQ enable flag. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetTCR1OVFIRQEn(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_T1MR & TPU_E_TBR_T1MR_IRQ_EN_MASK) >> TPU_E_TBR_T1MR_IRQ_EN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get TCR1 IRQ enable flag. + * + */ +LOCAL_INLINE void TPU_E_HWA_EnableTCR1OVFIRQ(TPU_E_Type *const pTPUE, bool bEn) +{ + pTPUE->TBR_T1MR = (pTPUE->TBR_T1MR & ~TPU_E_TBR_T1MR_IRQ_EN_MASK) | TPU_E_TBR_T1MR_IRQ_EN(bEn); +} + +/** + * @brief Get the maximum value of TCR1 counter in TCR1 updown mode. + * + */ +LOCAL_INLINE uint32_t TPU_E_HWA_GetTCR1MaxCnt(const TPU_E_Type *const pTPUE) +{ + return (pTPUE->TBR_T1MR & TPU_E_TBR_T1MR_MAX_MASK) >> TPU_E_TBR_T1MR_MAX_SHIFT; +} + +/** + * @brief Get the maximum value of TCR1 counter in TCR1 updown mode. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetTCR1MaxCnt(TPU_E_Type *const pTPUE, uint32_t u32MaxCnt) +{ + pTPUE->TBR_T1MR = (pTPUE->TBR_T1MR & ~TPU_E_TBR_T1MR_MAX_MASK) | TPU_E_TBR_T1MR_MAX(u32MaxCnt); +} + +/** + * @brief Get TCR2 overflow flag. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetTCR2Overflow(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_T2MR & TPU_E_TBR_T2MR_OVF_MASK) >> TPU_E_TBR_T2MR_OVF_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear TCR2 overflow flag. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearTCR2Overflow(TPU_E_Type *const pTPUE) +{ + pTPUE->TBR_T2MR = (pTPUE->TBR_T2MR | TPU_E_TBR_T2MR_OVF_MASK); +} + +/** + * @brief Get TCR2 IRQ enable flag. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetTCR2OVFIRQEnable(const TPU_E_Type *const pTPUE) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->TBR_T2MR & TPU_E_TBR_T2MR_IRQ_EN_MASK) >> TPU_E_TBR_T2MR_IRQ_EN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Enable TCR2 IRQ enable flag. + * + */ +LOCAL_INLINE void TPU_E_HWA_EnableTCR2OVFIRQ(TPU_E_Type *const pTPUE, bool bEn) +{ + pTPUE->TBR_T2MR = (pTPUE->TBR_T2MR & ~TPU_E_TBR_T2MR_IRQ_EN_MASK) | TPU_E_TBR_T2MR_IRQ_EN(bEn); +} + +/** + * @brief Get the maximum value of TCR2 counter in TCR1 updown mode. + * + */ +LOCAL_INLINE uint32_t TPU_E_HWA_GetTCR2MaxCnt(const TPU_E_Type *const pTPUE) +{ + return (pTPUE->TBR_T2MR & TPU_E_TBR_T2MR_MAX_MASK) >> TPU_E_TBR_T2MR_MAX_SHIFT; +} + +/** + * @brief Set the maximum value of TCR2 counter in TCR2 updown mode. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetTCR2MaxCnt(TPU_E_Type *const pTPUE, uint32_t u32MaxCnt) +{ + pTPUE->TBR_T2MR = (pTPUE->TBR_T2MR & ~TPU_E_TBR_T2MR_MAX_MASK) | TPU_E_TBR_T2MR_MAX(u32MaxCnt); +} + +/** + * @brief Get channel event triggered interrupt enable flag. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChEventIntEnable(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR & TPU_E_CHn_CR_CIE_MASK) >> TPU_E_CHn_CR_CIE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Enable channel event triggered interrupt. + * + */ +LOCAL_INLINE void TPU_E_HWA_EnableChEventInt(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].CR = (pTPUE->CH[u8Channel].CR & ~TPU_E_CHn_CR_CIE_MASK) | TPU_E_CHn_CR_CIE(bEn); +} + +/** + * @brief Get channel event triggered interrupt priority. + * + */ +LOCAL_INLINE TPUE_EventIntPriorityType TPU_E_HWA_GetChEventIntPriority(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR & TPU_E_CHn_CR_CPR_MASK) >> TPU_E_CHn_CR_CPR_SHIFT; + return (TPUE_EventIntPriorityType)u32TmpVal; +} + +/** + * @brief Set channel event triggered interrupt priority. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetChEventIntPriority(TPU_E_Type *const pTPUE, uint8_t u8Channel, TPUE_EventIntPriorityType ePriority) +{ + pTPUE->CH[u8Channel].CR = (pTPUE->CH[u8Channel].CR & ~TPU_E_CHn_CR_CPR_MASK) | TPU_E_CHn_CR_CPR(ePriority); +} + +/** + * @brief Get channel Filter Bypass + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChFilterBypassEnable(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR & TPU_E_CHn_CR_CFB_MASK) >> TPU_E_CHn_CR_CFB_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set channel Filter Bypass + * + */ +LOCAL_INLINE void TPU_E_HWA_OpenChFilter(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].CR = (pTPUE->CH[u8Channel].CR & ~TPU_E_CHn_CR_CFB_MASK) | TPU_E_CHn_CR_CFB(bEn); +} + +/** + * @brief Get channel entry function + * + */ +LOCAL_INLINE uint8_t TPU_E_HWA_GetChEntryFunc(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR & TPU_E_CHn_CR_CFS_MASK) >> TPU_E_CHn_CR_CFS_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set channel entry function + * + */ +LOCAL_INLINE void TPU_E_HWA_SetChEntryFunc(TPU_E_Type *const pTPUE, uint8_t u8Channel, uint8_t u8EntryFunc) +{ + pTPUE->CH[u8Channel].CR = (pTPUE->CH[u8Channel].CR & ~TPU_E_CHn_CR_CFS_MASK) | TPU_E_CHn_CR_CFS(u8EntryFunc); +} + +/** + * @brief Get channel entry table pin direction + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChEntryTblPinDirOutput(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR & TPU_E_CHn_CR_ETPD_MASK) >> TPU_E_CHn_CR_ETPD_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set channel entry table pin direction + * + */ +LOCAL_INLINE void TPU_E_HWA_SetChEntryTblPinDirOutput(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].CR = (pTPUE->CH[u8Channel].CR & ~TPU_E_CHn_CR_ETPD_MASK) | TPU_E_CHn_CR_ETPD(bEn); +} + +/** + * @brief Get channel entry table condition select + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChEntryTblCondSelAlt(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR & TPU_E_CHn_CR_ECTS_MASK) >> TPU_E_CHn_CR_ECTS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set channel entry table condition select + * + */ +LOCAL_INLINE void TPU_E_HWA_SetChEntryTblCondSelAlt(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].CR = (pTPUE->CH[u8Channel].CR & ~TPU_E_CHn_CR_ECTS_MASK) | TPU_E_CHn_CR_ECTS(bEn); +} + +/** + * @brief Get channel entry table flag1 + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChEntryTblflag1(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR & TPU_E_CHn_CR_FLG1_MASK) >> TPU_E_CHn_CR_FLG1_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set channel entry table flag1 + * + */ +LOCAL_INLINE void TPU_E_HWA_SetChEntryTblflag1(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].CR = (pTPUE->CH[u8Channel].CR & ~TPU_E_CHn_CR_FLG1_MASK) | TPU_E_CHn_CR_FLG1(bEn); +} + +/** + * @brief Get channel entry table flag0 + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChEntryTblflag0(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR & TPU_E_CHn_CR_FLG0_MASK) >> TPU_E_CHn_CR_FLG0_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set channel entry table flag0 + * + */ +LOCAL_INLINE void TPU_E_HWA_SetChEntryTblflag0(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].CR = (pTPUE->CH[u8Channel].CR & ~TPU_E_CHn_CR_FLG0_MASK) | TPU_E_CHn_CR_FLG0(bEn); +} + +/** + * @brief Get channel output polarity + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChOutputHigh(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR & TPU_E_CHn_CR_OPOL_MASK) >> TPU_E_CHn_CR_OPOL_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set channel output polarity + * + */ +LOCAL_INLINE void TPU_E_HWA_SetChOutputActiveHigh(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].CR = (pTPUE->CH[u8Channel].CR & ~TPU_E_CHn_CR_OPOL_MASK) | TPU_E_CHn_CR_OPOL(bEn); +} + +/** + * @brief Get channel output disable + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChOutputDisable(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR & TPU_E_CHn_CR_ODIS_MASK) >> TPU_E_CHn_CR_ODIS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set channel output disable + * + */ +LOCAL_INLINE void TPU_E_HWA_SetChOutputDisable(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].CR = (pTPUE->CH[u8Channel].CR & ~TPU_E_CHn_CR_ODIS_MASK) | TPU_E_CHn_CR_ODIS(bEn); +} + +/** + * @brief Get channel HSA index. + * + */ +LOCAL_INLINE uint8_t TPU_E_HWA_GetChHSAIdx(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR & TPU_E_CHn_CR_CHSA_MASK) >> TPU_E_CHn_CR_CHSA_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set channel HSA index. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetChHSAIdx(TPU_E_Type *const pTPUE, uint8_t u8Channel, uint8_t u8HSAIdx) +{ + pTPUE->CH[u8Channel].CR = ((pTPUE->CH[u8Channel].CR & ~TPU_E_CHn_CR_CHSA_MASK) | TPU_E_CHn_CR_CHSA(u8HSAIdx)); +} + +/** + * @brief Get channel event trigger interrupt status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChEventTrigISRStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].SR & TPU_E_CHn_SR_CIS_MASK) >> TPU_E_CHn_SR_CIS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get channel host service request (HSR) status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChHSRStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].SR & TPU_E_CHn_SR_CHRS_MASK) >> TPU_E_CHn_SR_CHRS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get Channel HSR Info & Index . + * + */ +LOCAL_INLINE uint8_t TPU_E_HWA_GetChHSRIdx(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].SR & TPU_E_CHn_SR_CHRI_MASK) >> TPU_E_CHn_SR_CHRI_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Get channel event as interrupt status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChEventReqISRStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].SR & TPU_E_CHn_SR_CEIS_MASK) >> TPU_E_CHn_SR_CEIS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get channel event as interrupt status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChDMAReq(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].SR & TPU_E_CHn_SR_CHDS_MASK) >> TPU_E_CHn_SR_CHDS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get channel trigger status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChTrigStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].SR & TPU_E_CHn_SR_CTS_MASK) >> TPU_E_CHn_SR_CTS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get channel host service acknowledge (HSA) interrupt status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChHSAReqStatus(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].SR & TPU_E_CHn_SR_CHAS_MASK) >> TPU_E_CHn_SR_CHAS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear channel interrupt by event. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearChEventISRFlg(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].SCR = TPU_E_CHn_SCR_CISC_MASK; +} + +/** + * @brief Clear channel HSA Dma. + * + */ +LOCAL_INLINE void TPU_E_HWA_ChReqDMA(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].SCR = TPU_E_CHn_SCR_CHDT_MASK; +} + +/** + * @brief Clear channel HSA. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearChHSAISR(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].SCR = TPU_E_CHn_SCR_CHAT_MASK; +} + +/** + * @brief Clear channel HSR. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearChHSR(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].SCR = TPU_E_CHn_SCR_CHRC_MASK; +} + +/** + * @brief Get channel service request. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChServiceReq(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].EFR & TPU_E_CHn_EFR_CSR_MASK) >> TPU_E_CHn_EFR_CSR_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get channel service request to HOST. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChServiceReqToHost(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].EFR & TPU_E_CHn_EFR_CHSR_MASK) >> TPU_E_CHn_EFR_CHSR_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get match recognition latch 1 event status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChMatchRecLatch1Event(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].EFR & TPU_E_CHn_EFR_EMRL1_MASK) >> TPU_E_CHn_EFR_EMRL1_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get match recognition latch 2 event status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChMatchRecLatch2Event(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].EFR & TPU_E_CHn_EFR_EMRL2_MASK) >> TPU_E_CHn_EFR_EMRL2_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get transition detect latch 1 event status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChTransDetectLatch1Event(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].EFR & TPU_E_CHn_EFR_ETDL1_MASK) >> TPU_E_CHn_EFR_ETDL1_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get transition detect latch 2 event status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChTransDetectLatch2Event(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].EFR & TPU_E_CHn_EFR_ETDL2_MASK) >> TPU_E_CHn_EFR_ETDL2_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get match recognition latch 1 enable status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChMatchRecLatch1En(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].EFR & TPU_E_CHn_EFR_MRLE1_MASK) >> TPU_E_CHn_EFR_MRLE1_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get match recognition latch 2 enable status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChMatchRecLatch2En(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].EFR & TPU_E_CHn_EFR_MRLE2_MASK) >> TPU_E_CHn_EFR_MRLE2_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get match recognition latch 1 enable status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChMatchRecLatch1Status(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].EFR & TPU_E_CHn_EFR_MRL1_MASK) >> TPU_E_CHn_EFR_MRL1_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get match recognition latch 2 enable status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChMatchRecLatch2Status(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].EFR & TPU_E_CHn_EFR_MRL2_MASK) >> TPU_E_CHn_EFR_MRL2_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get Transition Detect latch 1 enable status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChTransDetectLatch1Status(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].EFR & TPU_E_CHn_EFR_TDL1_MASK) >> TPU_E_CHn_EFR_TDL1_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get Transition Detect latch 2 enable status. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChTransDetectLatch2Status(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].EFR & TPU_E_CHn_EFR_TDL2_MASK) >> TPU_E_CHn_EFR_TDL2_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get comparator selection for time base selection. + * + */ +LOCAL_INLINE TPUE_TimeBaseSelctionType TPU_E_HWA_GetChTBS1(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR2 & TPU_E_CHn_CR2_TBS1_MASK) >> TPU_E_CHn_CR2_TBS1_SHIFT; + return (TPUE_TimeBaseSelctionType)u32TmpVal; +} + +/** + * @brief Set comparator selection for time base selection. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetChTBS1(TPU_E_Type *const pTPUE, uint8_t u8Channel, TPUE_TimeBaseSelctionType eType) +{ + pTPUE->CH[u8Channel].CR2 = (pTPUE->CH[u8Channel].CR2 & ~TPU_E_CHn_CR2_TBS1_MASK) | TPU_E_CHn_CR2_TBS1(eType); +} + +/** + * @brief Get pin state input. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChPinStateInputHigh(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR2 & TPU_E_CHn_CR2_PSTI_MASK) >> TPU_E_CHn_CR2_PSTI_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get pin state output. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChPinStateOutputHigh(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR2 & TPU_E_CHn_CR2_PSTO_MASK) >> TPU_E_CHn_CR2_PSTO_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get pin request service sample. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChPinReqSrvSample(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR2 & TPU_E_CHn_CR2_PRSS_MASK) >> TPU_E_CHn_CR2_PRSS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get Input Pin Action Control of Part 1 . + * + */ +LOCAL_INLINE TPUE_IPACType TPU_E_HWA_GetIPAC1(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR2 & TPU_E_CHn_CR2_IPAC1_MASK) >> TPU_E_CHn_CR2_IPAC1_SHIFT; + return (TPUE_IPACType)u32TmpVal; +} + +/** + * @brief Set Input Pin Action Control of Part 1 . + * + */ +LOCAL_INLINE void TPU_E_HWA_SetIPAC1(TPU_E_Type *const pTPUE, uint8_t u8Channel, TPUE_IPACType eType) +{ + pTPUE->CH[u8Channel].CR2 = (pTPUE->CH[u8Channel].CR2 & ~TPU_E_CHn_CR2_IPAC1_MASK) | TPU_E_CHn_CR2_IPAC1(eType); +} + +/** + * @brief Get Output Buffer Enable. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetChOutputBufEn(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR2 & TPU_E_CHn_CR2_OBE_MASK) >> TPU_E_CHn_CR2_OBE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get Output Buffer Enable. + * + */ +LOCAL_INLINE void TPU_E_HWA_EnableChOutputBuf(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEnable) +{ + pTPUE->CH[u8Channel].CR2 = (pTPUE->CH[u8Channel].CR2 & ~TPU_E_CHn_CR2_OBE_MASK) | TPU_E_CHn_CR2_OBE(bEnable); +} + +/** + * @brief Get Output Pin Action Control of Part 1. + * + */ +LOCAL_INLINE TPUE_OPACType TPU_E_HWA_GetOPAC1(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR2 & TPU_E_CHn_CR2_OPAC1_MASK) >> TPU_E_CHn_CR2_OPAC1_SHIFT; + return (TPUE_OPACType)u32TmpVal; +} + +/** + * @brief Set Input Pin Action Control of Part 2 . + * + */ +LOCAL_INLINE void TPU_E_HWA_SetOPAC1(TPU_E_Type *const pTPUE, uint8_t u8Channel, TPUE_OPACType eType) +{ + pTPUE->CH[u8Channel].CR2 = (pTPUE->CH[u8Channel].CR2 & ~TPU_E_CHn_CR2_OPAC1_MASK) | TPU_E_CHn_CR2_OPAC1(eType); +} + +/** + * @brief Get comparator selection for time base selection. + * + */ +LOCAL_INLINE TPUE_TimeBaseSelctionType TPU_E_HWA_GetChTBS2(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR2 & TPU_E_CHn_CR2_TBS2_MASK) >> TPU_E_CHn_CR2_TBS2_SHIFT; + return (TPUE_TimeBaseSelctionType)u32TmpVal; +} + +/** + * @brief Set comparator selection for time base selection. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetChTBS2(TPU_E_Type *const pTPUE, uint8_t u8Channel, TPUE_TimeBaseSelctionType eType) +{ + pTPUE->CH[u8Channel].CR2 = (pTPUE->CH[u8Channel].CR2 & ~TPU_E_CHn_CR2_TBS2_MASK) | TPU_E_CHn_CR2_TBS2(eType); +} + +/** + * @brief Get Input Pin Action Control of Part 2. + * + */ +LOCAL_INLINE TPUE_IPACType TPU_E_HWA_GetIPAC2(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR2 & TPU_E_CHn_CR2_IPAC2_MASK) >> TPU_E_CHn_CR2_IPAC2_SHIFT; + return (TPUE_IPACType)u32TmpVal; +} + +/** + * @brief Set Input Pin Action Control of Part 2. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetIPAC2(TPU_E_Type *const pTPUE, uint8_t u8Channel, TPUE_IPACType eType) +{ + pTPUE->CH[u8Channel].CR2 = (pTPUE->CH[u8Channel].CR2 & ~TPU_E_CHn_CR2_IPAC2_MASK) | TPU_E_CHn_CR2_IPAC2(eType); +} + +/** + * @brief Get Output Pin Action Control of Part 1. + * + */ +LOCAL_INLINE TPUE_OPACType TPU_E_HWA_GetOPAC2(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].CR2 & TPU_E_CHn_CR2_OPAC2_MASK) >> TPU_E_CHn_CR2_OPAC2_SHIFT; + return (TPUE_OPACType)u32TmpVal; +} + +/** + * @brief Set Input Pin Action Control of Part 2 . + * + */ +LOCAL_INLINE void TPU_E_HWA_SetOPAC2(TPU_E_Type *const pTPUE, uint8_t u8Channel, TPUE_OPACType eType) +{ + pTPUE->CH[u8Channel].CR2 = (pTPUE->CH[u8Channel].CR2 & ~TPU_E_CHn_CR2_OPAC2_MASK) | TPU_E_CHn_CR2_OPAC2(eType); +} + +/** + * @brief Clear sevice request write enable. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearSrvReqEn(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].MR = (pTPUE->CH[u8Channel].MR | TPU_E_CHn_MR_SRIE_MASK); +} + +/** + * @brief Get service request inhibit latch. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetSrvReqEn(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].MR & TPU_E_CHn_MR_SRI_MASK) >> TPU_E_CHn_MR_SRI_SHIFT; + return (bool)((u32TmpVal == 0U) ? true : false); +} + +/** + * @brief Set service request inhibit latch. + * + */ +LOCAL_INLINE void TPU_E_HWA_EnableSrvReq(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + if (bEn) + { + pTPUE->CH[u8Channel].MR = (pTPUE->CH[u8Channel].MR & ~TPU_E_CHn_MR_SRI_MASK) | TPU_E_CHn_MR_SRIE_MASK; + } + else + { + pTPUE->CH[u8Channel].MR = (pTPUE->CH[u8Channel].MR & TPU_E_CHn_MR_SRI_MASK) | TPU_E_CHn_MR_SRIE_MASK; + } + +} + +/** + * @brief Clear PDCM Write Enable. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearPDCMEn(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].MR = (pTPUE->CH[u8Channel].MR | TPU_E_CHn_MR_PDME_MASK); +} + +/** + * @brief Get Predefined Channel Mode. + * + */ +LOCAL_INLINE uint8_t TPU_E_HWA_GetPDCM(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].MR & TPU_E_CHn_MR_PDCM_MASK) >> TPU_E_CHn_MR_PDCM_SHIFT; + return (uint8_t)u32TmpVal; +} + +/** + * @brief Set Predefined Channel Mode. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetPDCM(TPU_E_Type *const pTPUE, uint8_t u8Channel, TPUE_PDCMEncodeType eMode) +{ + pTPUE->CH[u8Channel].MR = (pTPUE->CH[u8Channel].MR & ~TPU_E_CHn_MR_PDCM_MASK) | TPU_E_CHn_MR_PDCM(eMode) | TPU_E_CHn_MR_PDME_MASK; +} + +/** + * @brief Get transition continuous capture enable. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetTransContinueEn(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].MR & TPU_E_CHn_MR_TCCE_MASK) >> TPU_E_CHn_MR_TCCE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set Predefined Channel Mode. + * + */ +LOCAL_INLINE void TPU_E_HWA_EnableTransContinue(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].MR = (pTPUE->CH[u8Channel].MR & ~TPU_E_CHn_MR_TCCE_MASK) | TPU_E_CHn_MR_TCCE(bEn); +} + +/** + * @brief Clear UDCM Write Enable. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearUDCMWriteEn(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].MR = (pTPUE->CH[u8Channel].MR | TPU_E_CHn_MR_UDME_MASK); +} + +/** + * @brief Get User Defined Channel Mode. + * + */ +LOCAL_INLINE uint16_t TPU_E_HWA_GetUDCM(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].MR & TPU_E_CHn_MR_UDCM_MASK) >> TPU_E_CHn_MR_UDCM_SHIFT; + return (uint16_t)u32TmpVal; +} + +/** + * @brief Set User Defined Channel Mode. + * + */ +LOCAL_INLINE void TPU_E_HWA_EnableUDCM(TPU_E_Type *const pTPUE, uint8_t u8Channel, uint16_t u16Mode) +{ + pTPUE->CH[u8Channel].MR = (pTPUE->CH[u8Channel].MR & ~TPU_E_CHn_MR_UDCM_MASK) | TPU_E_CHn_MR_UDCM(u16Mode) | TPU_E_CHn_MR_UDME_MASK; +} + +/** + * @brief Clear Match Configuration Enable part1. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearMatchEn1(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].ER1 = (pTPUE->CH[u8Channel].ER1 | TPU_E_CHn_ER1_ERW_MASK); +} + +/** + * @brief Get User Defined Channel Mode part1. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetMatchEn(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].ER1 & TPU_E_CHn_ER1_MEF_MASK) >> TPU_E_CHn_ER1_MEF_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set User Defined Channel Mode. + * + */ +LOCAL_INLINE void TPU_E_HWA_EnableMatch(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].ER1 = (pTPUE->CH[u8Channel].ER1 & ~TPU_E_CHn_ER1_MEF_MASK) | TPU_E_CHn_ER1_MEF(bEn); +} + +/** + * @brief Set ER1 value for match. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetMatchER1(TPU_E_Type *const pTPUE, uint8_t u8Channel, uint32_t u32ER1) +{ + uint32_t u32Temp; + u32Temp = pTPUE->CH[u8Channel].ER1 | TPU_E_CHn_ER1_ERS_MASK; + pTPUE->CH[u8Channel].ER1 = (u32Temp & ~TPU_E_CHn_ER1_ER1_MASK) | TPU_E_CHn_ER1_ER1(u32ER1) | TPU_E_CHn_ER1_ERW_MASK; +} + +/** + * @brief Set ER1 value for capture. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetCaptureER1(TPU_E_Type *const pTPUE, uint8_t u8Channel, uint32_t u32ER1) +{ + uint32_t u32Temp; + u32Temp = (pTPUE->CH[u8Channel].ER1 & ~TPU_E_CHn_ER1_ERS_MASK) | TPU_E_CHn_ER1_ERS(0U); + pTPUE->CH[u8Channel].ER1 = (u32Temp & ~TPU_E_CHn_ER1_ER1_MASK) | TPU_E_CHn_ER1_ER1(u32ER1) | TPU_E_CHn_ER1_ERW_MASK; +} + +/** + * @brief Get Capture/Match Select for Value of ER1/ER2. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetMatchSelForERx(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].ER1 & TPU_E_CHn_ER1_ERS_MASK) >> TPU_E_CHn_ER1_ERS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get ER1 value. + * + */ +LOCAL_INLINE uint32_t TPU_E_HWA_GetER1Val(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].ER1 & TPU_E_CHn_ER1_ER1_MASK) >> TPU_E_CHn_ER1_ER1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get ER1 value. + * + */ +LOCAL_INLINE uint32_t TPU_E_HWA_GetCaptureER1Val(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + pTPUE->CH[u8Channel].ER1 = (pTPUE->CH[u8Channel].ER1 & ~TPU_E_CHn_ER1_ERS_MASK) | TPU_E_CHn_ER1_ERS(0U); + u32TmpVal = (pTPUE->CH[u8Channel].ER1 & TPU_E_CHn_ER1_ER1_MASK) >> TPU_E_CHn_ER1_ER1_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set ER1 value. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetER1(TPU_E_Type *const pTPUE, uint8_t u8Channel, uint32_t u32ER1) +{ + pTPUE->CH[u8Channel].ER1 = (pTPUE->CH[u8Channel].ER1 & ~TPU_E_CHn_ER1_ER1_MASK) | TPU_E_CHn_ER1_ER1(u32ER1) | TPU_E_CHn_ER1_ERW_MASK; +} + +/** + * @brief Clear Match Configuration Enable part2. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearMatchEn2(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].ER2 = (pTPUE->CH[u8Channel].ER2 | TPU_E_CHn_ER2_ERW_MASK); +} + +/** + * @brief Get ER2 value. + * + */ +LOCAL_INLINE uint32_t TPU_E_HWA_GetER2Val(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].ER2 & TPU_E_CHn_ER2_ER2_MASK) >> TPU_E_CHn_ER2_ER2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get ER2 value. + * + */ +LOCAL_INLINE uint32_t TPU_E_HWA_GetCaptureER2Val(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + pTPUE->CH[u8Channel].ER1 = (pTPUE->CH[u8Channel].ER1 & ~TPU_E_CHn_ER1_ERS_MASK); + u32TmpVal = (pTPUE->CH[u8Channel].ER2 & TPU_E_CHn_ER2_ER2_MASK) >> TPU_E_CHn_ER2_ER2_SHIFT; + return u32TmpVal; +} + +/** + * @brief Set ER2 value. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetER2(TPU_E_Type *const pTPUE, uint8_t u8Channel, uint32_t u32ER2) +{ + pTPUE->CH[u8Channel].ER2 = (pTPUE->CH[u8Channel].ER2 & ~TPU_E_CHn_ER2_ER2_MASK) | TPU_E_CHn_ER2_ER2(u32ER2) | TPU_E_CHn_ER2_ERW_MASK; +} + +/** + * @brief Clear Match1 Configuration Enable. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearMatch1CFGFlg(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].ECR = TPU_E_CHn_ECR_MRE1_CLR_MASK; +} + +/** + * @brief Clear Match1 event Enable. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearMatch1Event(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].ECR = TPU_E_CHn_ECR_MRL1_CLR_MASK; +} + +/** + * @brief Clear transition detect1 Enable. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearTransDetect1Event(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].ECR = TPU_E_CHn_ECR_TDL1_CLR_MASK; +} + +/** + * @brief Clear Match2 Configuration Enable. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearMatch2CFGFlg(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].ECR = TPU_E_CHn_ECR_MRE2_CLR_MASK; +} + +/** + * @brief Clear Match2 event Enable. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearMatch2Event(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].ECR = TPU_E_CHn_ECR_MRL2_CLR_MASK; +} + +/** + * @brief Clear transition detect2 Enable. + * + */ +LOCAL_INLINE void TPU_E_HWA_ClearTransDetect2Event(TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + pTPUE->CH[u8Channel].ECR = TPU_E_CHn_ECR_TDL2_CLR_MASK; +} + +/** + * @brief Get output user control, high or low select. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetOutputSelHigh(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].OCR & TPU_E_CHn_OCR_OUT_HIS_MASK) >> TPU_E_CHn_OCR_OUT_HIS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear output user control. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetOutputSelHigh(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].OCR = TPU_E_CHn_OCR_OUT_HIS(bEn); +} + +/** + * @brief Get output user control, select OPAC1. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetOutputUsrCtrlSelOPAC1(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].OCR & TPU_E_CHn_OCR_OUT_OP1_MASK) >> TPU_E_CHn_OCR_OUT_OP1_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set output user control, select OPAC1. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetOutputSelOPAC1(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].OCR = (pTPUE->CH[u8Channel].OCR & ~TPU_E_CHn_OCR_OUT_OP1_MASK) | TPU_E_CHn_OCR_OUT_OP1(bEn); +} + +/** + * @brief Get output user control, select OPAC2. + * + */ +LOCAL_INLINE bool TPU_E_HWA_GetOutputUsrCtrlSelOPAC2(const TPU_E_Type *const pTPUE, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUE->CH[u8Channel].OCR & TPU_E_CHn_OCR_OUT_OP2_MASK) >> TPU_E_CHn_OCR_OUT_OP2_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set output user control, select OPAC2. + * + */ +LOCAL_INLINE void TPU_E_HWA_SetOutputSelOPAC2(TPU_E_Type *const pTPUE, uint8_t u8Channel, bool bEn) +{ + pTPUE->CH[u8Channel].OCR = (pTPUE->CH[u8Channel].OCR & ~TPU_E_CHn_OCR_OUT_OP2_MASK) | TPU_E_CHn_OCR_OUT_OP2(bEn); +} + +#endif /* #ifndef _HWA_TPUE_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_tpuh.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_tpuh.h new file mode 100644 index 0000000..d23a900 --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_tpuh.h @@ -0,0 +1,902 @@ +/** + * @file HwA_tpuh.h + * @author Flagchip + * @brief FC7xxx TPUH hardware access layer + * @version 0.1.0 + * @date 2024-1-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ + +#ifndef _HWA_TPUH_H_ +#define _HWA_TPUH_H_ + +#include "device_header.h" +#if 1 +/********* Local typedef ************/ +/** @brief TPU TCR1 clock control mode type */ +typedef enum +{ + TPUH_CLK_SRC_TCRCLK = 0U, + UTPUH_PDOWN_CNT_MODE = 3U, + TPUH_CLK_SRC_TPUCLKDIV2 = 4U, + TPUH_CLK_SRC_TPUCLK = 5U +} TPUH_TCR1ClkCtrlModeType; + +/** @brief TPU angle tick gen clk type */ +typedef enum +{ + TPUH_TCR1_PRESCAL_OUTPUT = 0U, + TPUH_TCR2_PRESCAL_OUTPUT = 1U +} TPUH_AngleTickGenClkType; + +/** @brief TPU Angle Mode Selection type */ +typedef enum +{ + TPUH_TCR2_TIMEBASE_EAC_DISABLE = 0U, + TPUH_TOOTHSIGNAL_AS_TCRCLK_TOOTH_CH_0 = 1U, + TPUH_TOOTHSIGNAL_AS_CH1INPUT_TOOTH_CH_1 = 2U, + TPUH_TOOTHSIGNAL_AS_CH2INPUT_TOOTH_CH_2 = 3U +} TPUH_AngleModeSel; + +/** @brief TPU Angle Mode Selection type */ +typedef enum +{ + TPUH_TWO_SAMPLE_MODE_TPU_CLK_DIV2 = 0U, + TPUH_TWO_SAMPLE_MODE_CH_CLK = 1U, + TPUH_INTEGRATOR_MODE_TPU_CLK_DIV2 = 2U, + TPUH_INTEGRATOR_MODE_CH_CLK = 3U +} TPUH_TCRClkFilterType; + +/** @brief TPU TCR2 clock control mode0 type */ +typedef enum +{ + TPUH_GATED_DIV8_CLK = 0U, + TPUH_RISE_TRANSITION_INCREMENT_TCR2_PRESCALER = 1U, + TPUH_FALL_TRANSITION_INCREMENT_TCR2_PRESCALER = 2U, + TPUH_DIV8_CLK = 4U, + TPUH_UPDOWN_CNT_MODE = 5U, + TPUH_FROZEN = 7U +} TPUH_TCR1ClkCtrlMode0Type; + +typedef enum +{ + TPUH_RSING_EDGE = 1U, + TPUH_FALLING_EDGE = 2U, + TPUH_BOTH_EDGES = 3U, + TPUH_NO_EDGE = 6U, +} TPUH_TCR1ClkCtrlMode1Type; + +/** @brief Missing Tooth Counter */ +typedef enum +{ + TPUH_NOT_A_MISSING_TOOTH = 0U, + TPUH_ONE_MISSING_TOOTH = 1U, + TPUH_TWO_MISSING_TOOTH = 2U, + TPUH_THREE_MISSING_TOOTH = 3U, +} TPUH_MissToothCntType; + +/** @brief Channel Trigger Configuration */ +typedef enum +{ + TPUH_DISABLED = 0U, + TPUH_ANY_EVENT_GATED_BY_MSRTSR = 2U, + TPUH_HSA_EVENT_ON_FLEXCORE_MODE = 3U, + TPUH_MRL1_EVENT_NOT_GATED_BY_MSR = 4U, + TPUH_MRL2_EVENT_NOT_GATED_BY_MSR = 5U, + TPUH_MRL1_OR_MRL2_EVENT_NOT_GATED_BY_MSR = 6U, + TPUH_MRL1_AND_MRL2_EVENT_NOT_GATED_BY_MSR = 7U, + TPUH_TDL1_OR_TDL2_EVENT_NOT_GATED_BY_TSR = 8U, + TPUH_TDL1_AND_TDL2_EVENT_NOT_GATED_BY_TSR = 9U, + TPUH_EVENT_EQUAL_TO_CH_DO_LEVEL = 10U, + TPUH_EVENT_NEGATIVE_TO_CH_DO_LEVEL = 11U, + TPUH_EVENT_EQUAL_TO_CH_DO_PART1_LEVEL = 12U, + TPUH_EVENT_EQUAL_TO_CH_DO_PART2_LEVEL = 13U, + TPUH_EVENT_EQUAL_TO_CH_IND_LEVEL = 14U, + TPUH_EVENT_EQUAL_TO_CH_IND_LATCH_LEVEL = 15U, +} TPUH_ChTrigCFGType; +#endif +/********* Local inline function ************/ +/** + * @brief Get service request status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetSRStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_VSR & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get pin input status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetInputStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_VIR & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get pin output status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetoutputStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_VOR & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get pin output enable status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetoutputEnStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_VOBR & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get MRL1 status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetMRL1Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_VM1R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get MRL2 status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetMRL2Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_VM2R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get TDL1 status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetTDL1Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_VT1R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get TDL2 status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetTDL2Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_VT2R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get MRL1 event status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetMRL1EventStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_EM1R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get MRL2 event status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetMRL2EventStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_EM2R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get TDL1 event status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetTDL1eventStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_ET1R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get TDL2 event status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetTDL2eventStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_ET2R & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get HAS status of specific channel + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetHASStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->GCR_VHSR & (1U << u8Channel)) >> u8Channel; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get TCR1 prescaler. + * + */ +LOCAL_INLINE uint32_t TPU_H_HWA_GetTCR1Prescaler(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_TCR1P_MASK) >> TPU_H_TBR_CR_TCR1P_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get TCR1 clock control. + * + */ +LOCAL_INLINE TPUH_TCR1ClkCtrlModeType TPU_H_HWA_GetTCR1ClkControl(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_TCR1CTL_MASK) >> TPU_H_TBR_CR_TCR1CTL_SHIFT; + return (TPUH_TCR1ClkCtrlModeType)u32TmpVal; +} + +/** + * @brief Get TCR2 prescaler. + * + */ +LOCAL_INLINE uint32_t TPU_H_HWA_GetTCR2Prescaler(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_TCR2P_MASK) >> TPU_H_TBR_CR_TCR2P_SHIFT; + return u32TmpVal; +} + +/** + * @brief Get Angle tick generator clock. + * + */ +LOCAL_INLINE TPUH_AngleTickGenClkType TPU_H_HWA_GetATGC(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_ATGC_MASK) >> TPU_H_TBR_CR_ATGC_SHIFT; + return (TPUH_AngleTickGenClkType)u32TmpVal; +} + +/** + * @brief Get Angle Mode Selection. + * + */ +LOCAL_INLINE TPUH_AngleModeSel TPU_H_HWA_GetAM(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_AM_MASK) >> TPU_H_TBR_CR_AM_SHIFT; + return (TPUH_AngleModeSel)u32TmpVal; +} + +/** + * @brief Get TCRCLK signal Filter Control. + * + */ +LOCAL_INLINE TPUH_TCRClkFilterType TPU_H_HWA_GetTCRClkFilter(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_TCRCF_MASK) >> TPU_H_TBR_CR_TCRCF_SHIFT; + return (TPUH_TCRClkFilterType)u32TmpVal; +} + +/** + * @brief Get TCR2 clock control. + * + */ +LOCAL_INLINE TPUH_TCR1ClkCtrlMode0Type TPU_H_HWA_GetTCR2ClkControlAM0(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_TCR2CTL_MASK) >> TPU_H_TBR_CR_TCR2CTL_SHIFT; + return (TPUH_TCR1ClkCtrlMode0Type)u32TmpVal; +} + +/** + * @brief Get TCR2 clock control. + * + */ +LOCAL_INLINE TPUH_TCR1ClkCtrlMode1Type TPU_H_HWA_GetTCR2ClkControlAM1(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_CR & TPU_H_TBR_CR_TCR2CTL_MASK) >> TPU_H_TBR_CR_TCR2CTL_SHIFT; + return (TPUH_TCR1ClkCtrlMode1Type)u32TmpVal; +} + +/** + * @brief Get TCR1 cnt value. + * + */ +LOCAL_INLINE uint32_t TPU_H_HWA_GetTCR1CntVal(const TPU_H_Type *const pTPUH) +{ + return pTPUH->TBR_T1R; +} + +/** + * @brief Get TCR2 cnt value. + * + */ +LOCAL_INLINE uint32_t TPU_H_HWA_GetTCR2CntVal(const TPU_H_Type *const pTPUH) +{ + return pTPUH->TBR_T2R; +} + +/** + * @brief Get last tooth indication. + * + */ +LOCAL_INLINE bool TPU_H_HWA_NotLastTooth(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_TPR & TPU_H_TBR_TPR_LAST_MASK) >> TPU_H_TBR_TPR_LAST_SHIFT; + return (bool)((u32TmpVal == 0U) ? true : false); +} + +/** + * @brief Get missing tooth counter. + * + */ +LOCAL_INLINE TPUH_MissToothCntType TPU_H_HWA_GetMissingTooth(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_TPR & TPU_H_TBR_TPR_MISSCNT_MASK) >> TPU_H_TBR_TPR_MISSCNT_SHIFT; + return (TPUH_MissToothCntType)u32TmpVal; +} + +/** + * @brief Get last tooth indication. + * + */ +LOCAL_INLINE bool TPU_H_HWA_NoInsertTooth(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_TPR & TPU_H_TBR_TPR_IPH_MASK) >> TPU_H_TBR_TPR_IPH_SHIFT; + return (bool)((u32TmpVal == 0U) ? true : false); +} + +/** + * @brief Get last tooth indication. + * + */ +LOCAL_INLINE bool TPU_H_HWA_NoForceEACHalt(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_TPR & TPU_H_TBR_TPR_HOLD_MASK) >> TPU_H_TBR_TPR_HOLD_SHIFT; + return (bool)((u32TmpVal == 0U) ? true : false); +} + +/** + * @brief Get angle ticks number. + * + */ +LOCAL_INLINE uint32_t TPU_H_HWA_GetAngleTicksVal(const TPU_H_Type *const pTPUH) +{ + return (pTPUH->TBR_TPR & TPU_H_TBR_TPR_TICKS_MASK) >> TPU_H_TBR_TPR_TICKS_SHIFT; +} + +/** + * @brief Get the integer part of TCR1 clocks in one Angle tick. + * + */ +LOCAL_INLINE uint32_t TPU_H_HWA_GetIntergerPerAngleTick(const TPU_H_Type *const pTPUH) +{ + return (pTPUH->TBR_TRR & TPU_H_TBR_TRR_INTEGER_MASK) >> TPU_H_TBR_TRR_INTEGER_SHIFT; +} + +/** + * @brief Get the fraction part of TCR1 clocks in one Angle tick. + * + */ +LOCAL_INLINE uint32_t TPU_H_HWA_GetFractionPerAngleTick(const TPU_H_Type *const pTPUH) +{ + return (pTPUH->TBR_TRR & TPU_H_TBR_TRR_FRACTION_MASK) >> TPU_H_TBR_TRR_FRACTION_SHIFT; +} + +/** + * @brief Get TCR1 overflow flag. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetTCR1Overflow(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_T1MR & TPU_H_TBR_T1MR_OVF_MASK) >> TPU_H_TBR_T1MR_OVF_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get TCR1 IRQ enable flag. + * + */ +LOCAL_INLINE bool TPU_H_HWA_TCR1IRQEnable(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_T1MR & TPU_H_TBR_T1MR_IRQ_EN_MASK) >> TPU_H_TBR_T1MR_IRQ_EN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get the maximum value of TCR1 counter in TCR1 updown mode. + * + */ +LOCAL_INLINE uint32_t TPU_H_HWA_GetTCR1MaxCnt(const TPU_H_Type *const pTPUH) +{ + return (pTPUH->TBR_T1MR & TPU_H_TBR_T1MR_MAX_MASK) >> TPU_H_TBR_T1MR_MAX_SHIFT; +} + +/** + * @brief Get TCR2 overflow flag. + * + */ +LOCAL_INLINE bool TPU_H_HWA_TCR2Overflow(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_T2MR & TPU_H_TBR_T2MR_OVF_MASK) >> TPU_H_TBR_T2MR_OVF_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get TCR2 IRQ enable flag. + * + */ +LOCAL_INLINE bool TPU_H_HWA_TCR2IRQEnable(const TPU_H_Type *const pTPUH) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->TBR_T2MR & TPU_H_TBR_T2MR_IRQ_EN_MASK) >> TPU_H_TBR_T2MR_IRQ_EN_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get the maximum value of TCR2 counter in TCR1 updown mode. + * + */ +LOCAL_INLINE uint32_t TPU_H_HWA_GetTCR2MaxCnt(const TPU_H_Type *const pTPUH) +{ + return (pTPUH->TBR_T2MR & TPU_H_TBR_T2MR_MAX_MASK) >> TPU_H_TBR_T2MR_MAX_SHIFT; +} + +/** + * @brief Get channel HSA enable flag. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChHSAEnable(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].CR & TPU_H_CHn_CR_CHAE_MASK) >> TPU_H_CHn_CR_CHAE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set channel HSA enable or disable. + * + */ +LOCAL_INLINE void TPU_H_HWA_SetChHSA(TPU_H_Type *const pTPUH, uint8_t u8Channel, bool benable) +{ + pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CHAE_MASK) | TPU_H_CHn_CR_CHAE(benable)); +} + +/** + * @brief Set channel event trigger dma enable or disable. + * + */ +LOCAL_INLINE void TPU_H_HWA_SetChEventDMAEnable(TPU_H_Type *const pTPUH, uint8_t u8Channel, bool benable) +{ + pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CDFD_MASK) | TPU_H_CHn_CR_CDFD(benable)); +} + +/** + * @brief Set channel request Dma enable or disable. + * + */ +LOCAL_INLINE void TPU_H_HWA_SetChReqDMAEnable(TPU_H_Type *const pTPUH, uint8_t u8Channel, bool benable) +{ + pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CHDE_MASK) | TPU_H_CHn_CR_CHDE(benable)); +} + +/** + * @brief Get channel HSR Dma request enable flag. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChDMAEnable(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].CR & TPU_H_CHn_CR_CHDE_MASK) >> TPU_H_CHn_CR_CHDE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set channel Sync isr from flexcore enable or disable. + * + */ +LOCAL_INLINE void TPU_H_HWA_SetChSyncISR(TPU_H_Type *const pTPUH, uint8_t u8Channel, bool benable) +{ + pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CHEE_MASK) | TPU_H_CHn_CR_CHEE(benable)); +} + +/** + * @brief Get channel HSR event as interrupt enable flag. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChHSRISREnable(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].CR & TPU_H_CHn_CR_CHEE_MASK) >> TPU_H_CHn_CR_CHEE_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set channel channel HSR event as interrupt enable or disable. + * + */ +LOCAL_INLINE void TPU_H_HWA_SetChHSRISR(TPU_H_Type *const pTPUH, uint8_t u8Channel, bool benable) +{ + pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CHEE_MASK) | TPU_H_CHn_CR_CHEE(benable)); +} + +/** + * @brief Get channel trigger configuration. + * + */ +LOCAL_INLINE TPUH_ChTrigCFGType TPU_H_HWA_GetChTrigCondition(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].CR & TPU_H_CHn_CR_CTC_MASK) >> TPU_H_CHn_CR_CTC_SHIFT; + return (TPUH_ChTrigCFGType)u32TmpVal; +} + +/** + * @brief Set channel trigger configuration. + * + */ +LOCAL_INLINE void TPU_H_HWA_SetChTrig(TPU_H_Type *const pTPUH, uint8_t u8Channel, TPUH_ChTrigCFGType etrgcfg) +{ + pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CTC_MASK) | TPU_H_CHn_CR_CTC(etrgcfg)); +} + +/** + * @brief Get channel trigger DMA enable. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChTrigDMAEnable(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].CR & TPU_H_CHn_CR_CDFD_MASK) >> TPU_H_CHn_CR_CDFD_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Set channel trigger DMA enable. + * + */ +LOCAL_INLINE void TPU_H_HWA_SetChTrigDMAEnable(TPU_H_Type *const pTPUH, uint8_t u8Channel, bool benable) +{ + pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CDFD_MASK) | TPU_H_CHn_CR_CDFD(benable)); +} + +/** + * @brief Get channel HSR index. + * + */ +LOCAL_INLINE uint8 TPU_H_HWA_GetChHSRIdx(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].CR & TPU_H_CHn_CR_CHSR_MASK) >> TPU_H_CHn_CR_CHSR_SHIFT; + return (uint8)u32TmpVal; +} + +/** + * @brief Get channel HSR index. + * + */ +LOCAL_INLINE void TPU_H_HWA_SetChHSRIdx(TPU_H_Type *const pTPUH, uint8_t u8Channel, uint8_t u8HSRIdx) +{ + pTPUH->CH[u8Channel].CR = ((pTPUH->CH[u8Channel].CR & ~TPU_H_CHn_CR_CHSR_MASK) | TPU_H_CHn_CR_CHSR(u8HSRIdx)); +} + +/** + * @brief Get channel event trigger interrupt status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChEventTrigISRStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].SR & TPU_H_CHn_SR_CIS_MASK) >> TPU_H_CHn_SR_CIS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get channel host service request (HSR) status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChHSRStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (uint8_t)(pTPUH->CH[u8Channel].SR & TPU_H_CHn_SR_CHRS_MASK) >> TPU_H_CHn_SR_CHRS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get HSA. + * + */ +LOCAL_INLINE uint8 TPU_H_HWA_GetChHSAIdx(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].SR & TPU_H_CHn_SR_CHRI_MASK) >> TPU_H_CHn_SR_CHRI_SHIFT; + return (uint8_t)u32TmpVal; +} + + +/** + * @brief Get channel event as interrupt status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChDMAReq(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].SR & TPU_H_CHn_SR_CHDS_MASK) >> TPU_H_CHn_SR_CHDS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get channel trigger status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChTrigStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].SR & TPU_H_CHn_SR_CTS_MASK) >> TPU_H_CHn_SR_CTS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get channel host service acknowledge (HSA) interrupt status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChHSAReqStatus(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].SR & TPU_H_CHn_SR_CHAS_MASK) >> TPU_H_CHn_SR_CHAS_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Clear channel interrupt by event. + * + */ +LOCAL_INLINE void TPU_H_HWA_ClearChEventISRFlg(TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + pTPUH->CH[u8Channel].SCR = TPU_H_CHn_SCR_CEIC_MASK; +} + +/** + * @brief Clear channel HSA. + * + */ +LOCAL_INLINE void TPU_H_HWA_ClearChHSA(TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + pTPUH->CH[u8Channel].SCR = TPU_H_CHn_SCR_CHAC_MASK; +} + +/** + * @brief Clear channel HSR. + * + */ +LOCAL_INLINE void TPU_H_HWA_ClearChHSR(TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + pTPUH->CH[u8Channel].SCR = TPU_H_CHn_SCR_CHRT_MASK; +} + +/** + * @brief Get channel service request. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChServiceReq(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_CSR_MASK) >> TPU_H_CHn_EFR_CSR_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get channel service request to HOST. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChServiceReqToHost(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_CHSR_MASK) >> TPU_H_CHn_EFR_CHSR_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get match recognition latch 1 event status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChMatchRecLatch1Event(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_EMRL1_MASK) >> TPU_H_CHn_EFR_EMRL1_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get match recognition latch 2 event status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChMatchRecLatch2Event(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_EMRL2_MASK) >> TPU_H_CHn_EFR_EMRL2_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get transition detect latch 1 event status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChTransDetectLatch1Event(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_ETDL1_MASK) >> TPU_H_CHn_EFR_ETDL1_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get transition detect latch 2 event status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChTransDetectLatch2Event(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_ETDL2_MASK) >> TPU_H_CHn_EFR_ETDL2_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get match recognition latch 1 enable status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChMatchRecLatch1En(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_MRLE1_MASK) >> TPU_H_CHn_EFR_MRLE1_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get match recognition latch 2 enable status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChMatchRecLatch2En(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_MRLE2_MASK) >> TPU_H_CHn_EFR_MRLE2_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get match recognition latch 1 enable status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChMatchRecLatch1Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_MRL1_MASK) >> TPU_H_CHn_EFR_MRL1_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get match recognition latch 2 enable status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChMatchRecLatch2Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_MRL2_MASK) >> TPU_H_CHn_EFR_MRL2_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get Transition Detect latch 1 enable status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChTransDetectLatch1Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_TDL1_MASK) >> TPU_H_CHn_EFR_TDL1_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + +/** + * @brief Get Transition Detect latch 2 enable status. + * + */ +LOCAL_INLINE bool TPU_H_HWA_GetChTransDetectLatch2Status(const TPU_H_Type *const pTPUH, uint8_t u8Channel) +{ + uint32_t u32TmpVal; + + u32TmpVal = (pTPUH->CH[u8Channel].EFR & TPU_H_CHn_EFR_TDL2_MASK) >> TPU_H_CHn_EFR_TDL2_SHIFT; + return (bool)((u32TmpVal != 0U) ? true : false); +} + + +#endif /* #ifndef _HWA_TPUH_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_trgsel.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_trgsel.h new file mode 100644 index 0000000..7ba17ae --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_trgsel.h @@ -0,0 +1,150 @@ +/** + * @file HwA_trgsel.h + * @author Flagchip0103 + * @brief Hardware access layer for TrgSel + * @version 0.1.0 + * @date 2023-12-19 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-19 Flagchip0103 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef _HWA_TRGSEL_H_ +#define _HWA_TRGSEL_H_ + +#include "device_header.h" + +#define TRGSEL_REGSIZE 4U + +/** + * @brief Get the trigger source of the selected trigger target + * + * @param pTrgsel the base address of the TrgSel instance + * @param u32TargetIndex the trigger target to get the trigger source + * @return uint32_t the trigger source of the selected trigger target + */ +LOCAL_INLINE uint32_t TRGSEL_HWA_GetTargetTriggerSource(const TRGSEL_Type *const pTrgsel, uint32_t u32TargetIndex) +{ + uint32_t u32RegIdx = u32TargetIndex / TRGSEL_REGSIZE; + uint32_t u32SelIdx = u32TargetIndex % TRGSEL_REGSIZE; + + uint32_t u32Tmp = pTrgsel->OUT_SEL[u32RegIdx]; + switch (u32SelIdx) + { + case 0U: + { + u32Tmp = (u32Tmp & TRGSEL_OUT_SEL_SEL_0_MASK) >> TRGSEL_OUT_SEL_SEL_0_SHIFT; + break; + } + case 1U: + { + u32Tmp = (u32Tmp & TRGSEL_OUT_SEL_SEL_1_MASK) >> TRGSEL_OUT_SEL_SEL_1_SHIFT; + break; + } + case 2U: + { + u32Tmp = (u32Tmp & TRGSEL_OUT_SEL_SEL_2_MASK) >> TRGSEL_OUT_SEL_SEL_2_SHIFT; + break; + } + case 3U: + { + u32Tmp = (u32Tmp & TRGSEL_OUT_SEL_SEL_3_MASK) >> TRGSEL_OUT_SEL_SEL_3_SHIFT; + break; + } + + default: + break; + } + + return (uint32_t)u32Tmp; +} + +/** + * @brief Set the trigger source of the selected trigger target + * + * @param pTrgsel the base address of the TrgSel instance + * @param u32TargetIndex the trigger target to set the trigger source + * @param u32SourceIndex the selected trigger source to trig the target + */ +LOCAL_INLINE void TRGSEL_HWA_SetTargetTriggerSource(TRGSEL_Type *const pTrgsel, uint32_t u32TargetIndex, + uint32_t u32SourceIndex) +{ + uint32_t u32RegIdx = u32TargetIndex / TRGSEL_REGSIZE; + uint32_t u32SelIdx = u32TargetIndex % TRGSEL_REGSIZE; + uint32_t u32Tmp = pTrgsel->OUT_SEL[u32RegIdx]; + + switch (u32SelIdx) + { + case 0U: + { + u32Tmp = (u32Tmp & ~TRGSEL_OUT_SEL_SEL_0_MASK) | TRGSEL_OUT_SEL_SEL_0(u32SourceIndex); + break; + } + case 1U: + { + u32Tmp = (u32Tmp & ~TRGSEL_OUT_SEL_SEL_1_MASK) | TRGSEL_OUT_SEL_SEL_1(u32SourceIndex); + break; + } + case 2U: + { + u32Tmp = (u32Tmp & ~TRGSEL_OUT_SEL_SEL_2_MASK) | TRGSEL_OUT_SEL_SEL_2(u32SourceIndex); + break; + } + case 3U: + { + u32Tmp = (u32Tmp & ~TRGSEL_OUT_SEL_SEL_3_MASK) | TRGSEL_OUT_SEL_SEL_3(u32SourceIndex); + break; + } + + default: + break; + } + + pTrgsel->OUT_SEL[u32RegIdx] = u32Tmp; +} + +/** + * @brief Get wether the trigger source of the selected target is locked + * + * @param pTrgsel the base address of the TrgSel instance + * @param u32TargetIndex the trigger target to get the lock status + * @return true the trigger source of the selected target cannot be modified + * @return false the trigger source of the selected target can be modified + */ +LOCAL_INLINE bool TRGSEL_HWA_GetTargetLockStatus(const TRGSEL_Type *const pTrgsel, uint32_t u32TargetIndex) +{ + uint32_t u32RegIdx = u32TargetIndex / TRGSEL_REGSIZE; + + uint32_t u32Tmp = pTrgsel->OUT_SEL[u32RegIdx]; + u32Tmp = (u32Tmp & TRGSEL_OUT_SEL_LOCK_MASK) >> TRGSEL_OUT_SEL_LOCK_SHIFT; + + return (bool)((u32Tmp != 0U) ? true : false); +} + +/** + * @brief Lock the trigger source of the selected target + * + * @note The trigger target is grouped by four, so if you lock the trigger source of one target, the + * adjacent three trigger targets in the same register group are also be locked. So please ensure the + * trigger sources are not to be modified before lock the trigger target. + * + * @param pTrgsel the base address of the TrgSel instance + * @param u32TargetIndex the trigger target to lock the trigger source + */ +LOCAL_INLINE void TRGSEL_HWA_LockTargetTriggerSource(TRGSEL_Type *const pTrgsel, uint32_t u32TargetIndex) +{ + uint32_t u32RegIdx = u32TargetIndex / TRGSEL_REGSIZE; + + pTrgsel->OUT_SEL[u32RegIdx] |= TRGSEL_OUT_SEL_LOCK_MASK; +} + +/** @}*/ + +#endif /* _HWA_TRGSEL_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_tstmp.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_tstmp.h new file mode 100644 index 0000000..830fcd9 --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_tstmp.h @@ -0,0 +1,222 @@ +/** + * @file HwA_tstmp.h + * @author Flagchip + * @brief FC7xxx TSTMP hardware access layer + * @version 0.1.0 + * @date 2024-01-14 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + * @details + */ + +/******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-14 Flagchip0122 N/A FC7xxx internal release version + ********************************************************************************/ + + +#ifndef _HWA_TSTMP_H_ +#define _HWA_TSTMP_H_ + +#include "device_header.h" +/********* Local typedef ************/ +/** @brief Tstmp modulate number */ +typedef enum +{ + TSTMP_MOD0 = 0U, + TSTMP_MOD1, + TSTMP_MOD2, + TSTMP_MOD3, +} TSTMP_ModulateType; + +/** @brief Tstmp running mode */ +typedef enum +{ + TSTMP_MODE_ALWAYS_RUNNING = 0U, + TSTMP_MODE_PERIOD_RUNNING = 1U +} TSTMP_ModeCounterRunningMode; + +typedef enum +{ + TSTMP_SIRC1M_CLK = 0U, + TSTMP_AON_CLK = 1U +} TSTMP_ClockSourceType; +/********* Local inline function ************/ +/** + * @brief Read TSTMP value + * + * @param pTstmp TSTMP instance + * @return TSTMP value + */ +LOCAL_INLINE uint64_t TSTMP_HWA_ReadTstmpValue(TSTMP_Type *pTstmp) +{ + uint32_t u32TstmpL, u32TstmpH; + uint64_t u64TempValue; + u32TstmpL = pTstmp->VALL; + u32TstmpH = pTstmp->VALH; + + u64TempValue = u32TstmpH; + u64TempValue = (u64TempValue << 32U) + u32TstmpL; + return u64TempValue; +} + +/** + * @brief Read TSTMP interrupt enable bits + * + * @param pTstmp TSTMP instance + * @return TSTMP interrupt enable bits + */ +LOCAL_INLINE uint32_t TSTMP_HWA_ReadTstmpInterruptEnable(TSTMP_Type *pTstmp) +{ + return (uint32_t)pTstmp->MOD_INTEN; +} + +/** + * @brief Enable TSTMP MOD(n) match interrupt + * + * @param pTstmp TSTMP instance + * @param eMod MOD number + */ +LOCAL_INLINE void TSTMP_HWA_EnableModMatchInterrupt(TSTMP_Type *pTstmp, TSTMP_ModulateType eMod) +{ + pTstmp->MOD_INTEN |= ((uint32_t)1U << (uint32_t)eMod); +} + +/** + * @brief Disable TSTMP MOD(n) match interrupt + * + * @param pTstmp TSTMP instance + * @param eMod MOD number + */ +LOCAL_INLINE void TSTMP_HWA_DisableModMatchInterrupt(TSTMP_Type *pTstmp, TSTMP_ModulateType eMod) +{ + pTstmp->MOD_INTEN &= ~((uint32_t)1U << (uint32_t)eMod); +} + +/** + * @brief Set the counting modes of TSTMP MOD(n) + * + * @param pTstmp TSTMP instance + * @param eMod MOD number + * @param eCounterMode Counting mode set + */ +LOCAL_INLINE void TSTMP_HWA_SetModCounterMode(TSTMP_Type *pTstmp, TSTMP_ModulateType eMod, TSTMP_ModeCounterRunningMode eCounterMode) +{ + pTstmp->MOD_INTEN = (pTstmp->MOD_INTEN & ~((uint32_t)0x100U << (uint32_t)eMod)) | + (((uint32_t)eCounterMode << TSTMP_MOD_INTEN_MOD0_MODE_SHIFT) << (uint32_t)eMod); +} + +/** + * @brief Enable TSTMP MOD(n) counter + * + * @param pTstmp TSTMP instance + * @param eMod MOD number + */ +LOCAL_INLINE void TSTMP_HWA_EnableModCounter(TSTMP_Type *pTstmp, TSTMP_ModulateType eMod) +{ + pTstmp->MOD_INTEN |= (TSTMP_MOD_INTEN_MOD0_ENABLE_MASK << (uint32_t)eMod); +} + +/** + * @brief Disable TSTMP MOD(n) counter + * + * @param pTstmp TSTMP instance + * @param eMod MOD number + */ +LOCAL_INLINE void TSTMP_HWA_DisableModCounter(TSTMP_Type *pTstmp, TSTMP_ModulateType eMod) +{ + pTstmp->MOD_INTEN &= ~(TSTMP_MOD_INTEN_MOD0_ENABLE_MASK << (uint32_t)eMod); +} + +/** + * @brief Select TSTMP MOD(n) clock source + * + * @param pTstmp TSTMP instance + * @param eMod MOD number + */ +LOCAL_INLINE void TSTMP_HWA_SelectClkSource(TSTMP_Type *pTstmp, TSTMP_ModulateType eMod, TSTMP_ClockSourceType eClk) +{ + pTstmp->MOD_INTEN |= (((uint32_t)eClk) << (TSTMP_MOD_INTEN_MOD0_CLK_SHIFT + (uint32_t)eMod)); +} + +/** + * @brief Read TSTMP all MOD match flag + * + * @param pTstmp TSTMP instance + * @return TSTMP all MOD match flag + */ +LOCAL_INLINE uint32_t TSTMP_HWA_ReadModMatchFlag(TSTMP_Type *pTstmp) +{ + return ((uint32_t)(pTstmp->MOD_STATUS) & (uint32_t)(TSTMP_MOD_STATUS_MOD0_MATCH_MASK | TSTMP_MOD_STATUS_MOD1_MATCH_MASK + | TSTMP_MOD_STATUS_MOD2_MATCH_MASK | TSTMP_MOD_STATUS_MOD3_MATCH_MASK)); +} + +/** + * @brief Clear TSTMP all MOD(0) match flag + * + * @param pTstmp TSTMP instance + */ +LOCAL_INLINE void TSTMP_HWA_ClearMod0MatchFlag(TSTMP_Type *pTstmp) +{ + pTstmp->MOD_STATUS = (uint32_t)(TSTMP_MOD_STATUS_MOD0_MATCH_MASK); +} + +/** + * @brief Clear TSTMP all MOD(1,2,3) match flag + * + * @param pTstmp TSTMP instance + */ +LOCAL_INLINE void TSTMP_HWA_ClearAllMod123MatchFlag(TSTMP_Type *pTstmp) +{ + pTstmp->MOD_STATUS = (uint32_t)(TSTMP_MOD_STATUS_MOD1_MATCH_MASK | TSTMP_MOD_STATUS_MOD2_MATCH_MASK | + TSTMP_MOD_STATUS_MOD3_MATCH_MASK); +} + +/** + * @brief Clear TSTMP single MOD(1,2,3) match flag + * + * @param pTstmp TSTMP instance + * @param eMod MOD number + */ +LOCAL_INLINE void TSTMP_HWA_ClearSingleMod123MatchFlag(TSTMP_Type *pTstmp, TSTMP_ModulateType eMod) +{ + pTstmp->MOD_STATUS = ((uint32_t)1U << (uint32_t)eMod); +} + +/** + * @brief Set MOD match value + * + * @param pTstmp TSTMP instance + * @param eMod MOD number + * @param u32ModValue MOD value + */ +LOCAL_INLINE void TSTMP_HWA_SetModMatchValue(TSTMP_Type *pTstmp, TSTMP_ModulateType eMod, uint32_t u32ModValue) +{ + switch(eMod) + { + case TSTMP_MOD0: + pTstmp->MOD0_SETVAL = u32ModValue; + break; + + case TSTMP_MOD1: + pTstmp->MOD1_SETVAL = u32ModValue; + break; + + case TSTMP_MOD2: + pTstmp->MOD2_SETVAL = u32ModValue; + break; + + case TSTMP_MOD3: + pTstmp->MOD3_SETVAL = u32ModValue; + break; + + default: + break; + } +} + +#endif /* #ifndef _HWA_TSTMP_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_wdog.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_wdog.h new file mode 100644 index 0000000..5edfd57 --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_wdog.h @@ -0,0 +1,115 @@ +/** + * @file HwA_WDOG.h + * @author Flagchip + * @brief FC7xxx Wdog hardware access layer + * @version 0.1.0 + * @date 2022-04-16 + * + * @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/********************************************************************************* +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2023-12-29 qxw0074 N/A First version for FC7240 +******************************************************************************** */ + +#ifndef _HWA_WDOG_H_ +#define _HWA_WDOG_H_ + +#include "device_header.h" + +/** + * @addtogroup HwA_WDOG + * @{ + */ + +/********* Local typedef ************/ + +/********* Local inline function ************/ + +/********* Wdog Register interface ************/ +/** + * @brief Set CS register value, for Wdog working mode configuration. + * + * @param WDOG_Type *pWdog. point to wdog instance base register address. + * + * @param uint32_t u32Cs. configured register value + */ +LOCAL_INLINE void WDOG_HWA_SetCs(WDOG_Type *pWdog, uint32_t u32Cs) +{ + pWdog->CS = u32Cs; +} + +/** + * @brief Get CS register value, for WDOG working mode configuration. + * @return uint32_t CS register value. + */ +LOCAL_INLINE uint32_t WDOG_HWA_GetCs(WDOG_Type *pWdog) +{ + uint32_t u32Temp = 0U; + u32Temp = pWdog->CS; + return u32Temp; +} + +/** + * @brief Clear Wdog interrupt flag. + * + * @param WDOG_Type *pWdog. point to wdog instance base register address. + */ +LOCAL_INLINE void WDOG_HWA_ClearInterruptFlag(WDOG_Type *pWdog) +{ + pWdog->CS |= WDOG_CS_FLAG_MASK; +} + +/** + * @brief Get WDOG unlock status, if locked, register can't be written. + * @return bool. true as unlocked. false as locked. + */ +LOCAL_INLINE bool WDOG_HWA_GetUnlockStatus(WDOG_Type *pWdog) +{ + return (bool)((((uint32_t)pWdog->CS & (uint32_t)WDOG_CS_ULK_STAT_MASK) != 0U) ? true : false); +} + +/** + * @brief Set COUNTER register value. for Wdog unlock and refresh usage. + * + * @param pWdog. point to wdog instance base register address. + * + * @param u32Counter. configured register value + */ +LOCAL_INLINE void WDOG_HWA_SetCounter(WDOG_Type *pWdog, uint32_t u32Counter) +{ + pWdog->COUNTER = u32Counter; +} + +/** + * @brief Set TIMEOUT register value. for WDOG timeout value + * + * @param WDOG_Type *pWdog. point to wdog instance base register address. + * + * @param uint16_t u16Timeout configured register value + */ +LOCAL_INLINE void WDOG_HWA_SetTimeout(WDOG_Type *pWdog, uint16_t u16Timeout) +{ + pWdog->TIMEOUT = u16Timeout; +} + +/** + * @brief Set WINDOW register value. for windowed WDOG low threshold value. + * + * @param WDOG_Type *pWdog. point to wdog instance base register address. + * + * @param uint16_t u16Window. configured register value + */ +LOCAL_INLINE void WDOG_HWA_SetWindow(WDOG_Type *pWdog, uint16_t u16Window) +{ + pWdog->WINDOW = u16Window; +} + +/** @}*/ /* HwA_WODG */ + +#endif /* #ifndef _HWA_WDOG_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/Inc/HwA_wku.h b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_wku.h new file mode 100644 index 0000000..60a0802 --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/Inc/HwA_wku.h @@ -0,0 +1,168 @@ +/** + * @file HwA_wku.h + * @author Flagchip + * @brief FC7xxx WKU hardware access layer + * @version 0.1.0 + * @date 2024-01-05 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + * @details + */ + +#ifndef _HWA_WKU_H_ +#define _HWA_WKU_H_ + +#include "device_header.h" +/********* Local typedef ************/ +/** @brief Wku input */ +/* +typedef enum +{ + WKU_INPUT_FCSPI0 = 0x000040U, + WKU_INPUT_FCUART = 0x000080U, + WKU_INPUT_CMP0 = 0x000400U, + WKU_INPUT_CMP1 = 0x000800U, + WKU_INPUT_TSTMP0 = 0x002000U, + WKU_INPUT_RTC_ALARM = 0x004000U, + WKU_INPUT_RTC_SECONDS = 0x008000U, + WKU_INPUT_FCPIT0 = 0x010000U, + WKU_INPUT_CMU0 = 0x020000U, + WKU_INPUT_AONTIMER = 0x040000U, + WKU_INPUT_GPIOA = 0x080000U, + WKU_INPUT_GPIOC = 0x100000U, + WKU_INPUT_GPIOE = 0x200000U, + WKU_INPUT_GPIOF = 0x400000U, + WKU_INPUT_GPIOG = 0x800000U, + WKU_INPUT_MAX = 0xFFFFFFU +} WKU_WakeupInputType; +*/ +typedef enum +{ + WKU_INPUT_FCSPI0 = 0x000040U, + WKU_INPUT_FCUART = 0x000080U, + WKU_INPUT_CMP0 = 0x000400U, + WKU_INPUT_CMP1 = 0x000800U, + WKU_INPUT_TSTMP0 = 0x002000U, + WKU_INPUT_RTC_ALARM = 0x004000U, + WKU_INPUT_RTC_SECONDS = 0x008000U, + WKU_INPUT_FCPIT0 = 0x010000U, + WKU_INPUT_CMU0 = 0x020000U, + WKU_INPUT_AONTIMER = 0x040000U, + WKU_INPUT_GPIOA = 0x080000U, + WKU_INPUT_GPIOC = 0x100000U, + WKU_INPUT_GPIOD = 0x200000U, // <-- ДОБАВИТЬ (бит 21) + WKU_INPUT_GPIOE = 0x800000U, // <-- СМЕСТИТЬ (было 0x200000) + WKU_INPUT_GPIOF = 0x800000U, + WKU_INPUT_GPIOG = 0x1000000U, // <-- СМЕСТИТЬ (было 0x800000) + WKU_INPUT_MAX = 0xFFFFFFU +} WKU_WakeupInputType; + +/********* mcaro ************/ +#define WKU_INPUT_ALL_MASK (WKU_INPUT_FCSPI0 |\ + WKU_INPUT_FCUART |\ + WKU_INPUT_CMP0 |\ + WKU_INPUT_CMP1 |\ + WKU_INPUT_TSTMP0 |\ + WKU_INPUT_RTC_ALARM |\ + WKU_INPUT_RTC_SECONDS |\ + WKU_INPUT_FCPIT0 |\ + WKU_INPUT_CMU0 |\ + WKU_INPUT_AONTIMER |\ + WKU_INPUT_GPIOA |\ + WKU_INPUT_GPIOC |\ + WKU_INPUT_GPIOE |\ + WKU_INPUT_GPIOF |\ + WKU_INPUT_GPIOG |\ + WKU_INPUT_MAX) + +/********* Local inline function ************/ +/** + * @brief Enable wakeup delay counter + * + */ +LOCAL_INLINE void WKU_HWA_EnableDelayCounter(void) +{ + WKU->MDC |= (uint32_t)WKU_MDC_DLYEN_MASK; +} + +/** + * @brief Disable wakeup delay counter + * + */ +LOCAL_INLINE void WKU_HWA_DisableDelayCounter(void) +{ + WKU->MDC &= ~((uint32_t)WKU_MDC_DLYEN_MASK); +} + +/** + * @brief Set wakeup delay time + * + * @param u8DelayTime delay time + */ +LOCAL_INLINE void WKU_HWA_SetDelayTime(uint8_t u8DelayTime) +{ + uint32_t u32RegVal = WKU->MDC; + WKU->MDC = ((u32RegVal & (~WKU_MDC_DELAYTIME_MASK)) | WKU_MDC_DELAYTIME(u8DelayTime)); +} + +/** + * @brief Enable wakeup source + * + * @param eWakeup Wakeup source type + */ +LOCAL_INLINE void WKU_HWA_EnableWakeupSource(const WKU_WakeupInputType eWakeup) +{ + if (eWakeup < WKU_INPUT_CMP0) + { + WKU->MWER0 |= (uint32_t)eWakeup; + } + else if ((eWakeup < WKU_INPUT_FCPIT0) && (eWakeup > WKU_INPUT_FCUART)) + { + WKU->MWER1 |= ((uint32_t)eWakeup >> 8U); + } + else + { + WKU->MWER2 |= ((uint32_t)eWakeup >> 16U); + } +} + +/** + * @brief Disable wakeup source + * + * @param eWakeup Wakeup source type + */ +LOCAL_INLINE void WKU_HWA_DisableWakeupSource(const WKU_WakeupInputType eWakeup) +{ + if (eWakeup < WKU_INPUT_CMP0) + { + WKU->MWER0 &= ((~((uint32_t)eWakeup)) & (uint32_t)0xFF); + } + else if ((eWakeup < WKU_INPUT_FCPIT0) && (eWakeup > WKU_INPUT_FCUART)) + { + WKU->MWER1 &= ((~(uint32_t)((uint32_t)eWakeup >> 8U)) & (uint32_t)0xFF); + } + else + { + WKU->MWER2 &= ((~(uint32_t)((uint32_t)eWakeup >> 16U)) & (uint32_t)0xFF); + } +} + +/** + * @brief Read WKU wakeup source + * + * @return WKU wakeup source value + */ +LOCAL_INLINE uint32_t WKU_HWA_ReadWakeupSource(void) +{ + uint32_t u32WakeupSource = 0U; + + u32WakeupSource = (uint32_t)(WKU->MWER0); + u32WakeupSource |= (uint32_t)((uint32_t)(WKU->MWER1) << 8U); + u32WakeupSource |= (uint32_t)((uint32_t)(WKU->MWER2) << 16U); + + return u32WakeupSource; +} + + +#endif /* #ifndef _HWA_WKU_H_ */ diff --git a/MODULES/HwA_Flagchip_FC7240/modular.json b/MODULES/HwA_Flagchip_FC7240/modular.json new file mode 100644 index 0000000..174bad2 --- /dev/null +++ b/MODULES/HwA_Flagchip_FC7240/modular.json @@ -0,0 +1,7 @@ +{ + "cmake": { + "inc_dirs": [ + "Inc" + ] + } +} diff --git a/MODULES/InternalFlashPage_Flagchip_FC7240/Inc/InternalFlashPage.h b/MODULES/InternalFlashPage_Flagchip_FC7240/Inc/InternalFlashPage.h new file mode 100644 index 0000000..4bf192a --- /dev/null +++ b/MODULES/InternalFlashPage_Flagchip_FC7240/Inc/InternalFlashPage.h @@ -0,0 +1,113 @@ +// +// Created by cfif on 07.10.22. +// + +#ifndef HVAC_INTERNAL_FLASH_PAGE_H +#define HVAC_INTERNAL_FLASH_PAGE_H + +#include +#include "fc7xxx_driver_flash.h" +#include "stddef.h" + +bool D_bInternalFlashPage_Clear( + uint32_t pageAddress, + void *wdTriggerFct, + void *wdTriggerFct_env +); + +size_t D_sInternalFlashPage_Write( + uint32_t pageAddress, + size_t offset, + uint8_t *data, + size_t size +); + +size_t D_bInternalFlashPage_DumpFromRam( + uint32_t beginPageAddr, + void *sourceRamAddr, + uint32_t size +); + +size_t D_sInternalFlashPage_Read( + uint32_t pageAddress, + size_t offset, + uint8_t *data, + size_t size +); + +bool D_bInternalFlashPage_ClearRange( + uint32_t firstPageAddr, + uint32_t totalSize, + void *wdTriggerFct, + void *wdTriggerFct_env +); + +bool D_bInternalFlashPage_WriteFromRam(uint32_t beginPageAddr, void *sourceRamAddr, uint32_t size); + +bool D_bInternalFlashPage_CopyRange( + uint32_t targetPageAddr, + uint32_t sourcePageAddr, + uint32_t totalCopySize, + void *wdTriggerFct, + void *wdTriggerFct_env +); + +uint32_t D_iInternalFlashPage_ReadWord(uint32_t addressOnFlash); + + + + + + + + + + + + + +bool P_bInternalFlashPage_Clear( + uint32_t pageAddress +); + +size_t P_sInternalFlashPage_Write( + uint32_t pageAddress, + size_t offset, + uint8_t *data, + size_t size +); + +size_t P_bInternalFlashPage_DumpFromRam( + uint32_t beginPageAddr, + void *sourceRamAddr, + uint32_t size +); + +size_t P_sInternalFlashPage_Read( + uint32_t pageAddress, + size_t offset, + uint8_t *data, + size_t size +); + +bool P_bInternalFlashPage_ClearRange( + uint32_t firstPageAddr, + uint32_t totalSize, + void *wdTriggerFct, + void *wdTriggerFct_env +); + +bool P_bInternalFlashPage_WriteFromRam(uint32_t beginPageAddr, void *sourceRamAddr, uint32_t size); + +bool P_bInternalFlashPage_CopyRange( + uint32_t targetPageAddr, + uint32_t sourcePageAddr, + uint32_t totalCopySize, + void *wdTriggerFct, + void *wdTriggerFct_env +); + +uint32_t P_iInternalFlashPage_ReadWord(uint32_t addressOnFlash); + + +#endif //HVAC_INTERNAL_FLASH_PAGE_H diff --git a/MODULES/InternalFlashPage_Flagchip_FC7240/Src/InternalFlashPage_DFlash.c b/MODULES/InternalFlashPage_Flagchip_FC7240/Src/InternalFlashPage_DFlash.c new file mode 100644 index 0000000..1f8ba35 --- /dev/null +++ b/MODULES/InternalFlashPage_Flagchip_FC7240/Src/InternalFlashPage_DFlash.c @@ -0,0 +1,310 @@ +// +// Created by cfif on 07.10.22. +// +#include "InternalFlashPage.h" + +uint32_t D_iInternalFlashPage_ReadWord(uint32_t addressOnFlash) { + return (*(__IO uint32_t *) (addressOnFlash)); +} + +size_t D_sInternalFlashPage_Read( + uint32_t pageAddress, + size_t offset, + uint8_t *data, + size_t size +) { + if ((offset & (uint32_t) 0x3) != 0) { + // The offset is not a multiple of 4 + return 0; + } + + size_t left = size; + + while (left) { + if (left >= 4) { + *((uint32_t *) data) = D_iInternalFlashPage_ReadWord(pageAddress + offset); + data += 4; + offset += 4; + left -= 4; + } else { + uint32_t word = D_iInternalFlashPage_ReadWord(pageAddress + offset); + for (uint8_t sub_byte = 0; sub_byte < left; ++sub_byte) { + *data = ((uint8_t *) &word)[sub_byte]; + ++data; + } + offset += 4; + left = 0; + } + } + + return size; +} + +bool D_bInternalFlashPage_Clear( + uint32_t pageAddress, + void *wdTriggerFct, + void *wdTriggerFct_env +) { + FLASHDRIVER_Init(); + + FLASH_DRIVER_ParamType tFlashParam = {.pData = wdTriggerFct, + .wdTriggerFct = wdTriggerFct_env + }; + + tFlashParam.u32Address = pageAddress; + tFlashParam.u32Length = FLASH_PAGE_D_SIZE; + if (FLASH_ERROR_OK != FLASHDRIVER_DFlashEraseSector(&tFlashParam)) { + return false; + } + + +/* + flash_unlock(); + +// if (FLASH_OPERATE_DONE != flash_block_erase(pageAddress)) { +// return false; +// } + if (FLASH_OPERATE_DONE != flash_sector_erase(pageAddress)) { + flash_lock(); + return false; + } + + flash_lock(); +*/ + return true; +} + +bool D_bInternalFlashPage_ClearRange( + uint32_t firstPageAddr, + uint32_t totalSize, + void *wdTriggerFct, + void *wdTriggerFct_env +) { + if (totalSize % FLASH_PAGE_D_SIZE) { + return false; + } + + uint32_t endAddr = firstPageAddr + totalSize; + for (; firstPageAddr < endAddr; firstPageAddr += FLASH_PAGE_D_SIZE) { + if (!D_bInternalFlashPage_Clear(firstPageAddr, wdTriggerFct, wdTriggerFct_env)) { + return false; + } + } + + return true; +} + +bool D_bInternalFlashPage_CopyRange( + uint32_t targetPageAddr, + uint32_t sourcePageAddr, + uint32_t size, + void *wdTriggerFct, + void *wdTriggerFct_env +) { + if (!D_bInternalFlashPage_ClearRange(targetPageAddr, size, wdTriggerFct, wdTriggerFct_env)) { + return false; + } + + FLASHDRIVER_Init(); + + FLASH_DRIVER_ParamType tFlashParam = {.pData = (uint8_t *) sourcePageAddr, + .wdTriggerFct = (void *) 0 + }; + + tFlashParam.u32Address = targetPageAddr; + tFlashParam.u32Length = size; + FLASHDRIVER_DFlashWrite(&tFlashParam); + + return size; + + /* + flash_unlock(); + + for (size_t i = 0; i < size; ++i) { + + if (FLASH_OPERATE_DONE != flash_byte_program(targetPageAddr + i, (*(__IO uint8_t *) (sourcePageAddr + i)))) { + flash_lock(); + return i; + } + } + + flash_lock(); + + return size; + */ + /* + flash_unlock(); + uint32_t offset = 0; + + uint32_t word; + while (offset < size) { + word = iInternalFlashPage_ReadWord(sourcePageAddr + offset); + + if (FLASH_OPERATE_DONE != flash_word_program(targetPageAddr + offset, word)) { + flash_lock(); + // whole isn't written + return offset; + } + offset += 4; + } + + flash_lock(); + return size; + */ +} + +bool D_bInternalFlashPage_WriteFromRam(uint32_t beginPageAddr, void *sourceRamAddr, uint32_t size) { + FLASHDRIVER_Init(); + + FLASH_DRIVER_ParamType tFlashParam = {.pData = (uint8_t *) sourceRamAddr, + .wdTriggerFct = (void *) 0 + }; + + tFlashParam.u32Address = beginPageAddr; + tFlashParam.u32Length = size; + + if (FLASH_ERROR_OK != FLASHDRIVER_DFlashWrite(&tFlashParam)) { + return false; + } + + return true; +} + +size_t D_bInternalFlashPage_DumpFromRam( + uint32_t beginPageAddr, + void *sourceRamAddr, + uint32_t size +) { + size_t alignedSize = ((size / FLASH_PAGE_D_SIZE) + (size % FLASH_PAGE_D_SIZE ? 1 : 0)) * FLASH_PAGE_D_SIZE; + + if (!D_bInternalFlashPage_ClearRange(beginPageAddr, alignedSize,NULL, 0)) { + return 0; + } + + FLASHDRIVER_Init(); + + FLASH_DRIVER_ParamType tFlashParam = {.pData = (uint8_t *) sourceRamAddr, + .wdTriggerFct = (void *) 0 + }; + + tFlashParam.u32Address = beginPageAddr; + tFlashParam.u32Length = size; + if (FLASH_ERROR_OK != FLASHDRIVER_DFlashWrite(&tFlashParam)) { + return 0; + } + + return size; +/* + flash_unlock(); + + for (size_t i = 0; i < size; ++i) { + if (FLASH_OPERATE_DONE != flash_byte_program(beginPageAddr + i, ((uint8_t*)sourceRamAddr)[i])) { + flash_lock(); + return i; + } + } + + flash_lock(); + + return size; + */ +/* + flash_unlock(); + + uint32_t offset = 0; + + uint32_t word; + while (offset < size) { + word = *(uint32_t *) (sourceRamAddr + offset); + + if (size < 4) { + word = word & (0xFFFFFFFF >> (8 * (4 - size))); + } + + if (FLASH_OPERATE_DONE != flash_word_program(beginPageAddr + offset, word)) { + flash_lock(); + // whole isn't written + return offset; + } + offset += 4; + } + + flash_lock(); + return offset; +*/ +} + +size_t D_sInternalFlashPage_Write( + uint32_t pageAddress, + size_t offset, + uint8_t *data, + size_t size +) { + + FLASHDRIVER_Init(); + + FLASH_DRIVER_ParamType tFlashParam = {.pData = (uint8_t *) data, + .wdTriggerFct = (void *) 0 + }; + + tFlashParam.u32Address = pageAddress + offset; + tFlashParam.u32Length = size; + FLASH_StatusType ret = FLASHDRIVER_DFlashWrite(&tFlashParam); + + return size; + + /* + flash_unlock(); + + for (size_t i = 0; i < size; ++i) { + if (FLASH_OPERATE_DONE != flash_byte_program(pageAddress + i + offset, data[i])) { + flash_lock(); + return i; + } + } + + flash_lock(); + + return size; +*/ + +/* + flash_unlock(); + size_t left = size; + + while (left) { + if (left >= 4) { + if (FLASH_OPERATE_DONE != flash_word_program(pageAddress + offset, *((uint32_t *) data))) { + // whole isn't written + return size - left; + } + data += 4; + offset += 4; + left -= 4; + } else { + uint32_t word; + for (uint8_t sub_byte = 0; sub_byte < 4; ++sub_byte) { + if (sub_byte < left) { + ((uint8_t *) &word)[sub_byte] = *data; + ++data; + } else { + ++size; + ((uint8_t *) &word)[sub_byte] = 0; + } + } + + if (FLASH_OPERATE_DONE != flash_word_program(pageAddress + offset, word)) { + // whole isn't written + return size - left; + } + offset += 4; + left = 0; + + } + + } + flash_lock(); + + return size; +*/ +} diff --git a/MODULES/InternalFlashPage_Flagchip_FC7240/Src/InternalFlashPage_PFlash.c b/MODULES/InternalFlashPage_Flagchip_FC7240/Src/InternalFlashPage_PFlash.c new file mode 100644 index 0000000..38001c3 --- /dev/null +++ b/MODULES/InternalFlashPage_Flagchip_FC7240/Src/InternalFlashPage_PFlash.c @@ -0,0 +1,331 @@ +// +// Created by cfif on 07.10.22. +// +#include "InternalFlashPage.h" + +uint32_t P_iInternalFlashPage_ReadWord(uint32_t addressOnFlash) { + return (*(__IO uint32_t *) (addressOnFlash)); +} + +size_t P_sInternalFlashPage_Read( + uint32_t pageAddress, + size_t offset, + uint8_t *data, + size_t size +) { + if ((offset & (uint32_t) 0x3) != 0) { + // The offset is not a multiple of 4 + return 0; + } + + size_t left = size; + + while (left) { + if (left >= 4) { + *((uint32_t *) data) = P_iInternalFlashPage_ReadWord(pageAddress + offset); + data += 4; + offset += 4; + left -= 4; + } else { + uint32_t word = P_iInternalFlashPage_ReadWord(pageAddress + offset); + for (uint8_t sub_byte = 0; sub_byte < left; ++sub_byte) { + *data = ((uint8_t *) &word)[sub_byte]; + ++data; + } + offset += 4; + left = 0; + } + } + + return size; +} + +bool P_bInternalFlashPage_Clear( + uint32_t pageAddress +) { + FLASHDRIVER_Init(); + + FLASH_DRIVER_ParamType tFlashParam = {.pData = NULL, + .wdTriggerFct = (void *) 0 + }; + + + tFlashParam.u32Address = pageAddress; + tFlashParam.u32Length = FLASH_PAGE_P_SIZE; + if (FLASH_ERROR_OK != FLASHDRIVER_PFlashEraseSector(&tFlashParam)) { + return false; + } + + +/* + flash_unlock(); + +// if (FLASH_OPERATE_DONE != flash_block_erase(pageAddress)) { +// return false; +// } + if (FLASH_OPERATE_DONE != flash_sector_erase(pageAddress)) { + flash_lock(); + return false; + } + + flash_lock(); +*/ + return true; +} + +bool P_bInternalFlashPage_ClearRange( + uint32_t firstPageAddr, + uint32_t totalSize, + void *wdTriggerFct, + void *wdTriggerFct_env +) { + if (totalSize % FLASH_PAGE_P_SIZE) { + return false; + } + + FLASHDRIVER_Init(); + + FLASH_DRIVER_ParamType tFlashParam = { + .pData = 0, + .wdTriggerFct = wdTriggerFct, + .wdTriggerFct_env = wdTriggerFct_env, + .u32Address = firstPageAddr, + .u32Length = totalSize + }; + + FLASH_StatusType Res = FLASHDRIVER_PFlashEraseSector(&tFlashParam); + + bool result = false; + if (FLASH_ERROR_OK == Res) { + result = true; + } + + return result; + /* + uint32_t endAddr = firstPageAddr + totalSize; + for (; firstPageAddr < endAddr; firstPageAddr += FLASH_PAGE_SIZE) { + if (!P_bInternalFlashPage_Clear(firstPageAddr)) { + return false; + } + } + + return true; +*/ + +} + +bool P_bInternalFlashPage_CopyRange( + uint32_t targetPageAddr, + uint32_t sourcePageAddr, + uint32_t size, + void *wdTriggerFct, + void *wdTriggerFct_env +) { + if (!P_bInternalFlashPage_ClearRange(targetPageAddr, size, wdTriggerFct, wdTriggerFct_env)) { + return false; + } + + FLASHDRIVER_Init(); + + FLASH_DRIVER_ParamType tFlashParam = {.pData = (uint8_t *) sourcePageAddr, + .wdTriggerFct = wdTriggerFct, + .wdTriggerFct_env = wdTriggerFct_env + }; + + tFlashParam.u32Address = targetPageAddr; + tFlashParam.u32Length = size; + FLASH_StatusType result = FLASHDRIVER_PFlashWrite(&tFlashParam); + + return size; + + /* + flash_unlock(); + + for (size_t i = 0; i < size; ++i) { + + if (FLASH_OPERATE_DONE != flash_byte_program(targetPageAddr + i, (*(__IO uint8_t *) (sourcePageAddr + i)))) { + flash_lock(); + return i; + } + } + + flash_lock(); + + return size; + */ + /* + flash_unlock(); + uint32_t offset = 0; + + uint32_t word; + while (offset < size) { + word = iInternalFlashPage_ReadWord(sourcePageAddr + offset); + + if (FLASH_OPERATE_DONE != flash_word_program(targetPageAddr + offset, word)) { + flash_lock(); + // whole isn't written + return offset; + } + offset += 4; + } + + flash_lock(); + return size; + */ +} + +bool P_bInternalFlashPage_WriteFromRam(uint32_t beginPageAddr, void *sourceRamAddr, uint32_t size) { + FLASHDRIVER_Init(); + + FLASH_DRIVER_ParamType tFlashParam = {.pData = (uint8_t *) sourceRamAddr, + .wdTriggerFct = (void *) 0 + }; + + tFlashParam.u32Address = beginPageAddr; + tFlashParam.u32Length = size; + + if (FLASH_ERROR_OK != FLASHDRIVER_PFlashWrite(&tFlashParam)) { + return false; + } + + return true; +} + +size_t P_bInternalFlashPage_DumpFromRam( + uint32_t beginPageAddr, + void *sourceRamAddr, + uint32_t size +) { + size_t alignedSize = ((size / FLASH_PAGE_P_SIZE) + (size % FLASH_PAGE_P_SIZE ? 1 : 0)) * FLASH_PAGE_P_SIZE; + + if (!P_bInternalFlashPage_ClearRange(beginPageAddr, alignedSize, NULL, 0)) { + return 0; + } + + FLASHDRIVER_Init(); + + FLASH_DRIVER_ParamType tFlashParam = {.pData = (uint8_t *) sourceRamAddr, + .wdTriggerFct = (void *) 0 + }; + + tFlashParam.u32Address = beginPageAddr; + tFlashParam.u32Length = size; + if (FLASH_ERROR_OK != FLASHDRIVER_PFlashWrite(&tFlashParam)) { + return 0; + } + + return size; +/* + flash_unlock(); + + for (size_t i = 0; i < size; ++i) { + if (FLASH_OPERATE_DONE != flash_byte_program(beginPageAddr + i, ((uint8_t*)sourceRamAddr)[i])) { + flash_lock(); + return i; + } + } + + flash_lock(); + + return size; + */ +/* + flash_unlock(); + + uint32_t offset = 0; + + uint32_t word; + while (offset < size) { + word = *(uint32_t *) (sourceRamAddr + offset); + + if (size < 4) { + word = word & (0xFFFFFFFF >> (8 * (4 - size))); + } + + if (FLASH_OPERATE_DONE != flash_word_program(beginPageAddr + offset, word)) { + flash_lock(); + // whole isn't written + return offset; + } + offset += 4; + } + + flash_lock(); + return offset; +*/ +} + +size_t P_sInternalFlashPage_Write( + uint32_t pageAddress, + size_t offset, + uint8_t *data, + size_t size +) { + + FLASHDRIVER_Init(); + + FLASH_DRIVER_ParamType tFlashParam = {.pData = (uint8_t *) data, + .wdTriggerFct = (void *) 0 + }; + + tFlashParam.u32Address = pageAddress + offset; + tFlashParam.u32Length = size; + FLASH_StatusType ret = FLASHDRIVER_PFlashWrite(&tFlashParam); + + return size; + + /* + flash_unlock(); + + for (size_t i = 0; i < size; ++i) { + if (FLASH_OPERATE_DONE != flash_byte_program(pageAddress + i + offset, data[i])) { + flash_lock(); + return i; + } + } + + flash_lock(); + + return size; +*/ + +/* + flash_unlock(); + size_t left = size; + + while (left) { + if (left >= 4) { + if (FLASH_OPERATE_DONE != flash_word_program(pageAddress + offset, *((uint32_t *) data))) { + // whole isn't written + return size - left; + } + data += 4; + offset += 4; + left -= 4; + } else { + uint32_t word; + for (uint8_t sub_byte = 0; sub_byte < 4; ++sub_byte) { + if (sub_byte < left) { + ((uint8_t *) &word)[sub_byte] = *data; + ++data; + } else { + ++size; + ((uint8_t *) &word)[sub_byte] = 0; + } + } + + if (FLASH_OPERATE_DONE != flash_word_program(pageAddress + offset, word)) { + // whole isn't written + return size - left; + } + offset += 4; + left = 0; + + } + + } + flash_lock(); + + return size; +*/ +} diff --git a/MODULES/InternalFlashPage_Flagchip_FC7240/modular.json b/MODULES/InternalFlashPage_Flagchip_FC7240/modular.json new file mode 100644 index 0000000..71971cd --- /dev/null +++ b/MODULES/InternalFlashPage_Flagchip_FC7240/modular.json @@ -0,0 +1,10 @@ +{ + "cmake": { + "inc_dirs": [ + "Inc" + ], + "srcs": [ + "Src/**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/LinInterface/Inc/LinIO.h b/MODULES/LinInterface/Inc/LinIO.h new file mode 100644 index 0000000..24491f9 --- /dev/null +++ b/MODULES/LinInterface/Inc/LinIO.h @@ -0,0 +1,33 @@ +// +// Created by cfif on 17.11.22. +// + +#ifndef MODULE_LINIO_H +#define MODULE_LINIO_H + +#include "stdint.h" +#include "cmsis_os2.h" + +typedef enum { + LIN_DIRECTION_GET = 0, + LIN_DIRECTION_SET = 1 +} eDirection; + +typedef struct { + osMessageQueueId_t rxDataQueue; + eDirection direction; + uint8_t g_aTxBufferLen; + uint8_t g_aTxBuffer[8]; + uint8_t g_aRxBufferLen; + uint8_t g_aRxBuffer[8]; +} tLinData; + +typedef uint8_t (* LinIOTransaction )(void *env, uint8_t command, uint32_t timeout); + +typedef struct { + void *env; + LinIOTransaction runCommand; +} tLinIO; + + +#endif //MODULE_LINIO_H diff --git a/MODULES/LinInterface/modular.json b/MODULES/LinInterface/modular.json new file mode 100644 index 0000000..9bdd478 --- /dev/null +++ b/MODULES/LinInterface/modular.json @@ -0,0 +1,7 @@ +{ + "cmake": { + "inc_dirs": [ + "Inc" + ] + } +} \ No newline at end of file diff --git a/MODULES/Lin_Flagchip_FC7240/Inc/LinFlagchip.h b/MODULES/Lin_Flagchip_FC7240/Inc/LinFlagchip.h new file mode 100644 index 0000000..26c90ee --- /dev/null +++ b/MODULES/Lin_Flagchip_FC7240/Inc/LinFlagchip.h @@ -0,0 +1,62 @@ +// +// Created by cfif on 17.11.22. +// + +#ifndef LIN_FLAGCHIP_H +#define LIN_FLAGCHIP_H + +#include "LinIO.h" +#include "cmsis_os2.h" +#include "fc7xxx_driver_adc.h" +#include "fc7xxx_driver_pcc.h" +#include "interrupt_manager.h" +#include "fc7xxx_driver_lin.h" + +// LIN protocol ID definition +//#define LIN_MASTER_SEND_ID (0x3FU) +//#define LIN_MASTER_RECEIVE_ID (0x02U) +//#define LIN_MASTER_GO_TO_SLEEP_ID (0x03U) + +typedef void (*lin_callback_ext_t)(tLinData *env, uint8_t u8LinIndex, void *linState); + +typedef struct { + + FCUART_Type *UART; + + uint8_t UART_INDEX; + + tLinData linData; + + lin_config_t g_linMasterConfig; + lin_xfer_state_t g_xferMasterState; + + lin_callback_ext_t LinExtCallbackHandler; + void *envCallExtBack; + +} tLinFlagchip; + +void LIN_Initial( + tLinFlagchip *env, + FCUART_Type *uart, + uint32_t BoundRate, + + uint8 UART_INDEX, // UART0 = 0 ... UART7 = 7 + IRQn_Type IRQ_UART, // FCUART0_IRQn ... FCUART7_IRQn + uint8 UART_PRIORITY, + + lin_get_interval_time_t LIN_TimerGetTimeIntervalValue, + lin_callback_t LinCallbackHandler, + lin_callback_ext_t LinExtCallbackHandler, + void *envCallExtBack, + + const uint8_t *classicPID, + uint8_t numOfClassicPID +); + +//void GetLinCallbackHandler(tLinFlagchip *env, uint8_t u8LinIndex, void *state); + +//void Get_LIN_Result(tLinFlagchip *env); + +tLinIO vLinGetIo(tLinFlagchip *env); + +#endif //LIN_FLAGCHIP_H diff --git a/MODULES/Lin_Flagchip_FC7240/Src/LinFlagchip.c b/MODULES/Lin_Flagchip_FC7240/Src/LinFlagchip.c new file mode 100644 index 0000000..8202780 --- /dev/null +++ b/MODULES/Lin_Flagchip_FC7240/Src/LinFlagchip.c @@ -0,0 +1,94 @@ +// +// Created by cfif on 07.09.22. +// +#include +#include "LinFlagchip.h" + +static const PCC_ClkSrcType s_ePccUartTable[] = + { + PCC_CLK_FCUART0, + PCC_CLK_FCUART1, + PCC_CLK_FCUART2, + PCC_CLK_FCUART3, + PCC_CLK_FCUART4, + PCC_CLK_FCUART5, + PCC_CLK_FCUART6, + PCC_CLK_FCUART7 + }; + +void LIN_Initial( + tLinFlagchip *env, + FCUART_Type *uart, + uint32_t BoundRate, + + uint8 UART_INDEX, // UART0 = 0 ... UART7 = 7 + IRQn_Type IRQ_UART, // FCUART0_IRQn ... FCUART7_IRQn + uint8 UART_PRIORITY, + + lin_get_interval_time_t LIN_TimerGetTimeIntervalValue, + lin_callback_t LinCallbackHandler, + lin_callback_ext_t LinExtCallbackHandler, + void *envCallExtBack, + + const uint8_t *classicPID, + uint8_t numOfClassicPID +) { + + env->UART_INDEX = UART_INDEX; + env->UART = uart; + + env->linData.rxDataQueue = osMessageQueueNew(1, 1, NULL); + + env->LinExtCallbackHandler = LinExtCallbackHandler; + env->envCallExtBack = envCallExtBack; + + LIN_DrvGetDefaultConfig(LIN_NODE_MASTER, &env->g_linMasterConfig); + env->g_linMasterConfig.baudRate = BoundRate; + env->g_linMasterConfig.clockSrcFreq = PCC_GetPccFunctionClock(s_ePccUartTable[UART_INDEX]); + + + env->g_linMasterConfig.getIntervalTimeValueCallback = LIN_TimerGetTimeIntervalValue; + + env->g_linMasterConfig.numOfClassicPID = numOfClassicPID; + env->g_linMasterConfig.classicPID = (uint8_t *)classicPID; + + + +// Switch TJA1021 device to normal mode +// GPIO_WritePins(PORT_E, PORT_PIN_24, PORT_GPIO_HIGH); + + LIN_DrvInit(UART_INDEX, &env->g_linMasterConfig); + + env->g_xferMasterState.Callback = LinCallbackHandler; + LIN_DrvStart(UART_INDEX, &env->g_xferMasterState); + + NVIC_SetPriority(IRQ_UART, UART_PRIORITY); + NVIC_EnableIRQ(IRQ_UART); + +} + +static uint8_t vLinRunCommand(tLinFlagchip *env, uint8_t command, uint32_t timeout) { + + LIN_DrvSendHeader(env->UART_INDEX, command); + + lin_event_id_t state; + if (osMessageQueueGet(env->linData.rxDataQueue, &state, NULL, timeout) == osOK) { + LIN_DrvGoToIdleMode(env->UART_INDEX); + lin_event_id_t id = state; + return id; + } + + LIN_DrvGoToIdleMode(env->UART_INDEX); +// LIN_DrvReceiveFrameBlocking(env->UART_INDEX, env->linData.g_aRxBuffer, env->linData.g_aRxBufferLen, 3000U); + + return LIN_TIMEOUT; +} + + +tLinIO vLinGetIo(tLinFlagchip *env) { + tLinIO io = { + .env = env, + .runCommand = (LinIOTransaction) vLinRunCommand, + }; + return io; +} \ No newline at end of file diff --git a/MODULES/Lin_Flagchip_FC7240/modular.json b/MODULES/Lin_Flagchip_FC7240/modular.json new file mode 100644 index 0000000..40455a0 --- /dev/null +++ b/MODULES/Lin_Flagchip_FC7240/modular.json @@ -0,0 +1,17 @@ +{ + "dep": [ + { + "type": "local", + + "dir": "./MODULES/LinInterface" + } + ], + "cmake": { + "inc_dirs": [ + "Inc" + ], + "srcs": [ + "Src/**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/LoggerInterface/Inc/LoggerInterface.h b/MODULES/LoggerInterface/Inc/LoggerInterface.h new file mode 100644 index 0000000..cbe1cf0 --- /dev/null +++ b/MODULES/LoggerInterface/Inc/LoggerInterface.h @@ -0,0 +1,195 @@ +// +// Created by CFIF on 13.11.22. +// + +#ifndef UVEOS_ON_NATION_LOGGERINTERFACE_H +#define UVEOS_ON_NATION_LOGGERINTERFACE_H + +#include +#include "stddef.h" +#include "stdint.h" +#include "stdbool.h" + +#define MAX_COUNT_BUF_LOG 15 +#define MAX_LEN_BUF_NAME_LOG 16 + +#define MAX_LEN_BUF_SMALL_LOG 32 +#define MAX_LEN_BUF_BIG1_LOG 64 +#define MAX_LEN_BUF_BIG2_LOG 192 + + + +typedef enum +{ + LOG_BUF_SMALL, + LOG_BUF_BIG1, + LOG_BUF_BIG2 +} LOG_BUF_TYPE; + +typedef enum { + LOGLEVEL_FATAL, + LOGLEVEL_ERROR, + LOGLEVEL_WARN, + LOGLEVEL_INFO, + LOGLEVEL_DEBUG, + LOGLEVEL_TRACE, +} eLoggerLevel; + +typedef void (*LoggerGenericMethod)( + void *env, + const char *authorStatic, + const uint8_t authorLen, + eLoggerLevel loglevel, + char *msg, + uint16_t msgLen, + bool complete +); + +typedef void (*LoggerGenericCanMethod)( + void *env, + uint16_t mChannel, /* номер канала */ + uint8_t mFlags, /* бит 7 = RTR, остальные – направление */ + uint8_t mDLC, /* длина данных (0-8) */ + uint32_t mID, /* идентификатор */ + uint8_t *mData, /* данные */ + uint32_t timestamp +); + +typedef uint8_t * (*getMemPrintfBufLogMethod)( + void *env, + const char *authorStatic, + const uint8_t authorLen, + LOG_BUF_TYPE logBufType +); + +extern tStringStatic LOGGER_LEVEL_NAMES[]; + +typedef struct { + void *env; + LoggerGenericMethod logging; + LoggerGenericCanMethod loggingCan; + getMemPrintfBufLogMethod getMemPrintfBufLog; +} tLoggerInterface; + + +void LoggerPrintf( + tLoggerInterface *logger, + const char *authorStatic, + const uint8_t authorLen, + eLoggerLevel loglevel, + bool complete, + const char *fmt, + ... +); + +#ifndef LOGGER_LEVEL_INFO + +#define LOGGER_LEVEL_INFO 1 + +#endif + +#ifndef LOGGER_LEVEL_TRACE + +#define LOGGER_LEVEL_TRACE 0 + +#endif + +#ifndef LOGGER_LEVEL_ERROR + +#define LOGGER_LEVEL_ERROR 1 + +#endif + +#define LoggerFormat + +#if LOGGER_LEVEL_ERROR +#define LoggerErrorStatic(LOGGER, AUTHOR, MSG) if(LOGGER){ (LOGGER)->logging((LOGGER)->env,AUTHOR,sizeof(AUTHOR)-1,LOGLEVEL_ERROR, MSG, sizeof(MSG)-1,true); } +#define LoggerCnErrorStatic(LOGGER, AUTHOR, MSG) if(LOGGER){ (LOGGER)->logging((LOGGER)->env,AUTHOR,sizeof(AUTHOR)-1,LOGLEVEL_ERROR, MSG, sizeof(MSG)-1,false); } +#define LoggerError(LOGGER, AUTHOR, MSG, SIZE) if(LOGGER){ (LOGGER)->logging((LOGGER)->env,AUTHOR,sizeof(AUTHOR)-1,LOGLEVEL_ERROR, MSG, SIZE,true); } +#define LoggerCnError(LOGGER, AUTHOR, MSG, SIZE) if(LOGGER){ (LOGGER)->logging((LOGGER)->env,AUTHOR,sizeof(AUTHOR)-1,LOGLEVEL_ERROR, MSG, SIZE,false); } +#define LoggerFormatError(LOGGER, AUTHOR, FMT_MSG, ...) if(LOGGER){ LoggerPrintf(LOGGER,AUTHOR,sizeof(AUTHOR)-1,LOGLEVEL_ERROR,true, FMT_MSG, __VA_ARGS__); } + +#define LoggerErrorStatic(LOGGER, AUTHOR, MSG) if(LOGGER){ (LOGGER)->logging((LOGGER)->env,AUTHOR,sizeof(AUTHOR)-1,LOGLEVEL_ERROR, MSG, sizeof(MSG)-1,true); } +#define LoggerCnErrorStatic(LOGGER, AUTHOR, MSG) if(LOGGER){ (LOGGER)->logging((LOGGER)->env,AUTHOR,sizeof(AUTHOR)-1,LOGLEVEL_ERROR, MSG, sizeof(MSG)-1,false); } +#define LoggerError(LOGGER, AUTHOR, MSG, SIZE) if(LOGGER){ (LOGGER)->logging((LOGGER)->env,AUTHOR,sizeof(AUTHOR)-1,LOGLEVEL_ERROR, MSG, SIZE,true); } +#define LoggerCnError(LOGGER, AUTHOR, MSG, SIZE) if(LOGGER){ (LOGGER)->logging((LOGGER)->env,AUTHOR,sizeof(AUTHOR)-1,LOGLEVEL_ERROR, MSG, SIZE,false); } +#define LoggerFormatError(LOGGER, AUTHOR, FMT_MSG, ...) if(LOGGER){ LoggerPrintf(LOGGER,AUTHOR,sizeof(AUTHOR)-1,LOGLEVEL_ERROR,true, FMT_MSG, __VA_ARGS__); } + +#else +#define LoggerStrErrorStatic(LOGGER, AUTHOR, MSG) // невыводим +#define LoggerStrCnErrorStatic(LOGGER, AUTHOR, MSG) // невыводим +#define LoggerStrError(LOGGER, AUTHOR, MSG, SIZE) // невыводим +#define LoggerStrCnError(LOGGER, AUTHOR, MSG, SIZE) // невыводим +#define LoggerStrFormatError(LOGGER, AUTHOR, FMT_MSG, ...) // невыводим + + +#define LoggerStrErrorStatic(LOGGER, AUTHOR, MSG) // невыводим +#define LoggerStrCnErrorStatic(LOGGER, AUTHOR, MSG) // невыводим +#define LoggerStrError(LOGGER, AUTHOR, MSG, SIZE) // невыводим +#define LoggerStrCnError(LOGGER, AUTHOR, MSG, SIZE) // невыводим +#define LoggerStrFormatError(LOGGER, AUTHOR, FMT_MSG, ...) // невыводим + +#endif + +#if LOGGER_LEVEL_INFO +#define LoggerInfoRaw(LOGGER, AUTHOR, MSG, SIZE) if(LOGGER){ (LOGGER)->logging((LOGGER)->env,AUTHOR,sizeof(AUTHOR)-1,LOGLEVEL_INFO, MSG, SIZE, true); } + +#define LoggerInfoStatic(LOGGER, AUTHOR, MSG) if(LOGGER){ (LOGGER)->logging((LOGGER)->env,AUTHOR,sizeof(AUTHOR)-1,LOGLEVEL_INFO, MSG, sizeof(MSG)-1,true); } +#define LoggerCnInfoStatic(LOGGER, AUTHOR, MSG) if(LOGGER){ (LOGGER)->logging((LOGGER)->env,AUTHOR,sizeof(AUTHOR)-1,LOGLEVEL_INFO, MSG, sizeof(MSG)-1,false); } +#define LoggerInfo(LOGGER, AUTHOR, MSG, SIZE) if(LOGGER){ (LOGGER)->logging((LOGGER)->env,AUTHOR,sizeof(AUTHOR)-1,LOGLEVEL_INFO, MSG, SIZE,true); } +#define LoggerCnInfo(LOGGER, AUTHOR, MSG, SIZE) if(LOGGER){ (LOGGER)->logging((LOGGER)->env,AUTHOR,sizeof(AUTHOR)-1,LOGLEVEL_INFO, MSG, SIZE,false); } +#define LoggerFormatInfo(LOGGER, AUTHOR, FMT_MSG, ...) if(LOGGER){ LoggerPrintf(LOGGER,AUTHOR,sizeof(AUTHOR)-1,LOGLEVEL_INFO,true, FMT_MSG, __VA_ARGS__); } + + +#define LoggerStrInfoStatic(LOGGER, AUTHOR, MSG) if(LOGGER){ (LOGGER)->logging((LOGGER)->env,AUTHOR,strlen(AUTHOR),LOGLEVEL_INFO, MSG, sizeof(MSG)-1,true); } +#define LoggerStrCnInfoStatic(LOGGER, AUTHOR, MSG) if(LOGGER){ (LOGGER)->logging((LOGGER)->env,AUTHOR,strlen(AUTHOR),LOGLEVEL_INFO, MSG, sizeof(MSG)-1,false); } +#define LoggerStrInfo(LOGGER, AUTHOR, MSG, SIZE) if(LOGGER){ (LOGGER)->logging((LOGGER)->env,AUTHOR,strlen(AUTHOR),LOGLEVEL_INFO, MSG, SIZE,true); } +#define LoggerStrCnInfo(LOGGER, AUTHOR, MSG, SIZE) if(LOGGER){ (LOGGER)->logging((LOGGER)->env,AUTHOR,strlen(AUTHOR),LOGLEVEL_INFO, MSG, SIZE,false); } +#define LoggerStrFormatInfo(LOGGER, AUTHOR, FMT_MSG, ...) if(LOGGER){ LoggerPrintf(LOGGER,AUTHOR,strlen(AUTHOR),LOGLEVEL_INFO,true, FMT_MSG, __VA_ARGS__); } + +#else +#define LoggerInfoStatic(LOGGER, AUTHOR, MSG) // невыводим +#define LoggerCnInfoStatic(LOGGER, AUTHOR, MSG) // невыводим +#define LoggerInfo(LOGGER, AUTHOR, MSG, SIZE) // невыводим +#define LoggerCnInfo(LOGGER, AUTHOR, MSG, SIZE) // невыводим +#define LoggerFormatInfo(LOGGER, AUTHOR, FMT_MSG, ...) // невыводим + +#define LoggerStrInfoStatic(LOGGER, AUTHOR, MSG) // невыводим +#define LoggerStrCnInfoStatic(LOGGER, AUTHOR, MSG) // невыводим +#define LoggerStrInfo(LOGGER, AUTHOR, MSG, SIZE) // невыводим +#define LoggerStrCnInfo(LOGGER, AUTHOR, MSG, SIZE) // невыводим +#define LoggerStrFormatInfo(LOGGER, AUTHOR, FMT_MSG, ...) // невыводим + +#endif + + +#if LOGGER_LEVEL_TRACE +#define LoggerCnTraceStatic(LOGGER, AUTHOR, MSG) if(LOGGER){ (LOGGER)->logging((LOGGER)->env,AUTHOR,sizeof(AUTHOR)-1,LOGLEVEL_TRACE, MSG, sizeof(MSG)-1,false); } +#define LoggerTraceStatic(LOGGER, AUTHOR, MSG) if(LOGGER){ (LOGGER)->logging((LOGGER)->env,AUTHOR,sizeof(AUTHOR)-1,LOGLEVEL_TRACE, MSG, sizeof(MSG)-1,true); } +#define LoggerTrace(LOGGER, AUTHOR, MSG, SIZE) if(LOGGER){ (LOGGER)->logging((LOGGER)->env,AUTHOR,sizeof(AUTHOR)-1,LOGLEVEL_TRACE, MSG, SIZE,true); } +#define LoggerCnTrace(LOGGER, AUTHOR, MSG, SIZE) if(LOGGER){ (LOGGER)->logging((LOGGER)->env,AUTHOR,sizeof(AUTHOR)-1,LOGLEVEL_TRACE, MSG, SIZE,false); } +#define LoggerFormatTrace(LOGGER, AUTHOR, FMT_MSG, ...) if(LOGGER){ LoggerPrintf(LOGGER,AUTHOR,sizeof(AUTHOR)-1,LOGLEVEL_TRACE,true, FMT_MSG, __VA_ARGS__); } + +#define LoggerStrCnTraceStatic(LOGGER, AUTHOR, MSG) if(LOGGER){ (LOGGER)->logging((LOGGER)->env,AUTHOR,sizeof(AUTHOR)-1,LOGLEVEL_TRACE, MSG, sizeof(MSG)-1,false); } +#define LoggerStrTraceStatic(LOGGER, AUTHOR, MSG) if(LOGGER){ (LOGGER)->logging((LOGGER)->env,AUTHOR,sizeof(AUTHOR)-1,LOGLEVEL_TRACE, MSG, sizeof(MSG)-1,true); } +#define LoggerStrTrace(LOGGER, AUTHOR, MSG, SIZE) if(LOGGER){ (LOGGER)->logging((LOGGER)->env,AUTHOR,sizeof(AUTHOR)-1,LOGLEVEL_TRACE, MSG, SIZE,true); } +#define LoggerStrCnTrace(LOGGER, AUTHOR, MSG, SIZE) if(LOGGER){ (LOGGER)->logging((LOGGER)->env,AUTHOR,sizeof(AUTHOR)-1,LOGLEVEL_TRACE, MSG, SIZE,false); } +#define LoggerStrFormatTrace(LOGGER, AUTHOR, FMT_MSG, ...) if(LOGGER){ LoggerPrintf(LOGGER,AUTHOR,sizeof(AUTHOR)-1,LOGLEVEL_TRACE,true, FMT_MSG, __VA_ARGS__); } + +#else +#define LoggerCnTraceStatic(LOGGER, AUTHOR, MSG) // невыводим +#define LoggerTraceStatic(LOGGER, AUTHOR, MSG) // невыводим +#define LoggerTrace(LOGGER, AUTHOR, MSG, SIZE) // невыводим +#define LoggerCnTrace(LOGGER, AUTHOR, MSG, SIZE) // невыводим +#define LoggerFormatTrace(LOGGER, AUTHOR, FMT_MSG, ...) // невыводим + + +#define LoggerStrCnTraceStatic(LOGGER, AUTHOR, MSG) // невыводим +#define LoggerStrTraceStatic(LOGGER, AUTHOR, MSG) // невыводим +#define LoggerStrTrace(LOGGER, AUTHOR, MSG, SIZE) // невыводим +#define LoggerStrCnTrace(LOGGER, AUTHOR, MSG, SIZE) // невыводим +#define LoggerStrFormatTrace(LOGGER, AUTHOR, FMT_MSG, ...) // невыводим + +#endif + +#endif //UVEOS_ON_NATION_LOGGERINTERFACE_H diff --git a/MODULES/LoggerInterface/Src/LoggerLevelNames.c b/MODULES/LoggerInterface/Src/LoggerLevelNames.c new file mode 100644 index 0000000..4eb26bd --- /dev/null +++ b/MODULES/LoggerInterface/Src/LoggerLevelNames.c @@ -0,0 +1,25 @@ +// +// Created by CFIF on 13.11.22. +// + +#include "LoggerInterface.h" + +tStringStatic LOGGER_LEVEL_NAMES[] = { + StringStaticInit("FATAL"), + StringStaticInit("ERROR"), + StringStaticInit("WARN"), + StringStaticInit("INFO"), + StringStaticInit("DEBUG"), + StringStaticInit("TRACE"), +}; + +void LoggerInterfaceLogFormat(void *env, + char *authorStatic, + uint8_t authorLen, + eLoggerLevel loglevel, + char *msg, + uint16_t msgLen, + bool complete +) { + +} \ No newline at end of file diff --git a/MODULES/LoggerInterface/Src/LoggerPrintf.c b/MODULES/LoggerInterface/Src/LoggerPrintf.c new file mode 100644 index 0000000..f2e21aa --- /dev/null +++ b/MODULES/LoggerInterface/Src/LoggerPrintf.c @@ -0,0 +1,1175 @@ +#include +#include +#include +#include +#include +#include "LoggerInterface.h" + +#define FETCH_BYTE(p) (*(unsigned char*)(p)) +/* Max number conversion buffer length: a long in base 2, plus NUL byte. */ +#define MAXNBUF (sizeof(long) * 8 + 1) + +static unsigned char *ksprintn(unsigned char *buf, unsigned long v, unsigned char base, + int width, unsigned char *lp); + +static unsigned char mkhex(unsigned char ch); + +#define ARCH_HAVE_FPU 1 + +#if ARCH_HAVE_FPU + +static int cvt_f(double number, int prec, int sharpflag, unsigned char *negp, + unsigned char fmtch, unsigned char *startp, unsigned char *endp); + +#endif + +/* +int stream_logger_vprintf(tLoggerInterface *logger, char const *fmt, va_list ap) { + //#define PUTC(c) { putchar(stream,(unsigned char)(c)); ++retval; } +#define PUTC(c) { char p = c; (logger)->logging((logger)->env, NULL, 0, 0, &p, 1, false); ++retval; } + + + unsigned char nbuf[MAXNBUF], padding, *q; + const unsigned char *s; + unsigned char c, base, lflag, ladjust, sharpflag, neg, dot, size; + int16_t n, width, dwidth, retval, uppercase, extrazeros, sign; + unsigned long ul; + + if (!logger) + return 0; + if (!fmt) + fmt = "(null)\n"; + + retval = 0; + for (;;) { + while ((c = FETCH_BYTE (fmt++)) != '%') { + if (!c) + return retval; + PUTC (c); + } + padding = ' '; + width = 0; + extrazeros = 0; + lflag = 0; + ladjust = 0; + sharpflag = 0; + neg = 0; + sign = 0; + dot = 0; + uppercase = 0; + dwidth = -1; + reswitch: + switch (c = FETCH_BYTE (fmt++)) { + case '.': + dot = 1; + padding = ' '; + dwidth = 0; + goto reswitch; + + case '#': + sharpflag = 1; + goto reswitch; + + case '+': + sign = -1; + goto reswitch; + + case '-': + ladjust = 1; + goto reswitch; + + case '%': PUTC (c); + break; + + case '*': + if (!dot) { + width = va_arg (ap, int); + if (width < 0) { + ladjust = !ladjust; + width = -width; + } + } else { + dwidth = va_arg (ap, int); + } + goto reswitch; + + case '0': + if (!dot) { + padding = '0'; + goto reswitch; + } + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + for (n = 0;; ++fmt) { + n = n * 10 + c - '0'; + c = FETCH_BYTE (fmt); + if (c < '0' || c > '9') + break; + } + if (dot) + dwidth = n; + else + width = n; + goto reswitch; + + case 'b': + ul = va_arg (ap, int); + s = va_arg (ap, const unsigned char*); + q = ksprintn(nbuf, ul, *s++, -1, 0); + while (*q) PUTC (*q--); + + if (!ul) + break; + size = 0; + while (*s) { + n = *s++; + if ((char) (ul >> (n - 1)) & 1) { + PUTC (size ? ',' : '<'); + for (; (n = *s) > ' '; ++s) PUTC (n); + size = 1; + } else + while (*s > ' ') + ++s; + } + if (size) PUTC ('>'); + break; + + case 'c': + if (!ladjust && width > 0) + while (width--) PUTC (' '); + + PUTC (va_arg(ap, int)); + + if (ladjust && width > 0) + while (width--) PUTC (' '); + break; + + case 'D': + s = va_arg (ap, const unsigned char*); + if (!width) + width = 16; + if (sharpflag) + padding = ':'; + while (width--) { + c = *s++; + PUTC (mkhex(c >> 4)); + PUTC (mkhex(c)); + if (width) PUTC (padding); + } + break; + + case 'd': + ul = lflag ? va_arg (ap, long) : va_arg (ap, int); + if (!sign) sign = 1; + base = 10; + goto number; + + case 'l': + lflag = 1; + goto reswitch; + + case 'o': + ul = lflag ? va_arg (ap, unsigned long) : + va_arg (ap, unsigned int); + base = 8; + goto nosign; + + case 'p': + ul = (size_t) va_arg (ap, void*); + if (!ul) { + s = (const unsigned char *) "(nil)"; + goto const_string; + } + base = 16; + sharpflag = (width == 0); + goto nosign; + + case 'n': + ul = lflag ? va_arg (ap, unsigned long) : + sign ? (unsigned long) va_arg (ap, int) : + va_arg (ap, unsigned int); + base = 10; + goto number; + + case 'S': +#if __AVR__ + s = va_arg (ap, const unsigned char*); + if (! s) + s = (const unsigned char*) "(null)"; + const_string: + n = 0; + if (! dot) + while (FETCH_BYTE (s+n)) + ++n; + else + while (n 0) + while (width--) + PUTC (' '); + while (n--) + PUTC (FETCH_BYTE (s++)); + if (ladjust && width > 0) + while (width--) + PUTC (' '); + break; +#endif // LY: AVR, and no break here! + + case 's': + s = va_arg (ap, unsigned char*); +#ifdef __AVR__ + if (! s) { + s = (const unsigned char*) "(null)"; + goto const_string; + } +#else + if (!s) + s = (const unsigned char *) "(null)"; + const_string: +#endif + if (!dot) + n = strlen(s); + else + for (n = 0; n < dwidth && s[n]; n++) + continue; + + width -= n; + + if (!ladjust && width > 0) + while (width--) PUTC (' '); + while (n--) PUTC (*s++); + if (ladjust && width > 0) + while (width--) PUTC (' '); + break; + + case 'r': + // Saturated counters. + base = 10; + if (lflag) { + ul = va_arg (ap, unsigned long); + if (ul == -1) { + cnt_unknown: + if (ladjust) PUTC ('-'); + while (--width > 0) PUTC (' '); + if (!ladjust) PUTC ('-'); + break; + } + if (ul >= -2) { + ul = -3; + neg = '>'; + goto nosign; + } + } else { + ul = va_arg (ap, unsigned int); + if (ul == (unsigned short) -1) + goto cnt_unknown; + if (ul >= (unsigned short) -2) { + ul = (unsigned short) -3; + neg = '>'; + goto nosign; + } + } + goto nosign; + + case 'u': + ul = lflag ? va_arg (ap, unsigned long) : + va_arg (ap, unsigned int); + base = 10; + goto nosign; + + case 'x': + case 'X': + ul = lflag ? va_arg (ap, unsigned long) : + va_arg (ap, unsigned int); + base = 16; + uppercase = (c == 'X'); + goto nosign; + case 'z': + case 'Z': + ul = lflag ? va_arg (ap, unsigned long) : + sign ? (unsigned long) va_arg (ap, int) : + va_arg (ap, unsigned int); + base = 16; + uppercase = (c == 'Z'); + goto number; + + nosign: + sign = 0; + number: + if (sign && ((long) ul != 0L)) { + if ((long) ul < 0L) { + neg = '-'; + ul = -(long) ul; + } else if (sign < 0) + neg = '+'; + } + if (dwidth >= (int) sizeof(nbuf)) { + extrazeros = dwidth - sizeof(nbuf) + 1; + dwidth = sizeof(nbuf) - 1; + } + s = ksprintn(nbuf, ul, base, dwidth, &size); + if (sharpflag && ul != 0) { + if (base == 8) + size++; + else if (base == 16) + size += 2; + } + if (neg) + size++; + + if (!ladjust && width && padding == ' ' && + (width -= size) > 0) + do { + PUTC (' '); + } while (--width > 0); + + if (neg) PUTC (neg); + + if (sharpflag && ul != 0) { + if (base == 8) { + PUTC ('0'); + } else if (base == 16) { + PUTC ('0'); + PUTC (uppercase ? 'X' : 'x'); + } + } + + if (extrazeros) + do { + PUTC ('0'); + } while (--extrazeros > 0); + + if (!ladjust && width && (width -= size) > 0) + do { + PUTC (padding); + } while (--width > 0); + + for (; *s; --s) { + if (uppercase && *s >= 'a' && *s <= 'z') { + PUTC (*s + 'A' - 'a'); + } else { + PUTC (*s); + } + } + + if (ladjust && width && (width -= size) > 0) + do { + PUTC (' '); + } while (--width > 0); + break; +#if ARCH_HAVE_FPU + case 'e': + case 'E': + case 'f': + case 'F': + case 'g': + case 'G': { + double d = va_arg (ap, double); + + // don't do unrealistic precision; just pad it with + // zeroes later, so buffer size stays rational. + + if (dwidth > DBL_DIG) { + if ((c != 'g' && c != 'G') || sharpflag) + extrazeros = dwidth - DBL_DIG; + dwidth = DBL_DIG; + } else if (dwidth == -1) { + dwidth = (lflag ? DBL_DIG : FLT_DIG); + } + + // softsign avoids negative 0 if d is < 0 and + // no significant digits will be shown + + if (d < 0) { + neg = 1; + d = -d; + } + + // cvt may have to round up past the "start" of the + // buffer, i.e. ``intf("%.2f", (double)9.999);''; + // if the first char isn't NULL, it did. + + if (isnan (d) || isinf (d)) { + strcpy(nbuf, isnan (d) ? "NaN" : "Inf"); + size = 3; + extrazeros = 0; + s = nbuf; + } else { + *nbuf = 0; + size = cvt_f(d, dwidth, sharpflag, &neg, c, + nbuf, nbuf + sizeof(nbuf) - 1); + if (*nbuf) { + s = nbuf; + nbuf[size] = 0; + } else { + s = nbuf + 1; + nbuf[size + 1] = 0; + } + } + if (neg) + size++; + if (!ladjust && width && padding == ' ' && + (width -= size) > 0) + do { + PUTC (' '); + } while (--width > 0); + + if (neg) PUTC ('-'); + + if (!ladjust && width && (width -= size) > 0) + do { + PUTC (padding); + } while (--width > 0); + + for (; *s; ++s) { + if (extrazeros && (*s == 'e' || *s == 'E')) + do { + PUTC ('0'); + } while (--extrazeros > 0); + + PUTC (*s); + } + if (extrazeros) + do { + PUTC ('0'); + } while (--extrazeros > 0); + + if (ladjust && width && (width -= size) > 0) + do { + PUTC (' '); + } while (--width > 0); + break; + } +#endif + default: PUTC ('%'); + if (lflag) PUTC ('l'); + PUTC (c); + break; + } + } +} + +static unsigned char * +ksprintn(unsigned char *nbuf, unsigned long ul, unsigned char base, int width, + unsigned char *lenp) { + unsigned char *p; + + p = nbuf; + *p = 0; + for (;;) { + *++p = mkhex(ul % base); + ul /= base; + if (--width > 0) + continue; + if (!ul) + break; + } + if (lenp) + *lenp = p - nbuf; + return (p); +} + +static unsigned char +mkhex(unsigned char ch) { + ch &= 15; + if (ch > 9) + return ch + 'a' - 10; + return ch + '0'; +} + +#if ARCH_HAVE_FPU + +static unsigned char * +cvtround_f(double fract, int *exp, unsigned char *start, unsigned char *end, unsigned char ch, + unsigned char *negp) { + double tmp; + + if (fract) { + modf(fract * 10, &tmp); + } else { + tmp = ch - '0'; + } + if (tmp > 4) { + for (;; --end) { + if (*end == '.') { + --end; + } + if (++*end <= '9') { + break; + } + *end = '0'; + if (end == start) { + if (exp) { // e/E; increment exponent + *end = '1'; + ++*exp; + } else { // f; add extra digit + *--end = '1'; + --start; + } + break; + } + } + } else if (*negp) { + // ``"%.3f", (double)-0.0004'' gives you a negative 0. + + for (;; --end) { + if (*end == '.') { + --end; + } + if (*end != '0') { + break; + } + if (end == start) { + *negp = 0; + } + } + } + return start; +} + +static unsigned char * +exponent(unsigned char *p, int exp, unsigned char fmtch) { + unsigned char expbuf[8], *t; + + *p++ = fmtch; + if (exp < 0) { + exp = -exp; + *p++ = '-'; + } else { + *p++ = '+'; + } + t = expbuf + sizeof(expbuf); + if (exp > 9) { + do { + *--t = exp % 10 + '0'; + } while ((exp /= 10) > 9); + *--t = exp + '0'; + for (; t < expbuf + sizeof(expbuf); *p++ = *t++) + continue; + } else { + *p++ = '0'; + *p++ = exp + '0'; + } + return p; +} + +static int +cvt_f(double number, int prec, int sharpflag, unsigned char *negp, unsigned char fmtch, + unsigned char *startp, unsigned char *endp) { + unsigned char *p, *t; + double fract; + int dotrim, expcnt, gformat; + double integer, tmp; + + expcnt = 0; + dotrim = expcnt = gformat = 0; + fract = modf(number, &integer); + + + t = ++startp; + + + for (p = endp - 1; integer; ++expcnt) { + tmp = modf(integer / 10, &integer); + *p-- = (int) ((tmp + .01) * 10) + '0'; + } + switch (fmtch) { + case 'f': + + if (expcnt) { + for (; ++p < endp; *t++ = *p); + } else { + *t++ = '0'; + } + + + if (prec || sharpflag) { + *t++ = '.'; + } + + + if (fract) { + if (prec) { + do { + fract = modf(fract * 10, &tmp); + *t++ = (int) tmp + '0'; + } while (--prec && fract); + } + if (fract) { + startp = cvtround_f(fract, 0, startp, + t - 1, '0', negp); + } + } + for (; prec--; *t++ = '0'); + break; + case 'e': + case 'E': + eformat: + if (expcnt) { + *t++ = *++p; + if (prec || sharpflag) { + *t++ = '.'; + } + + + for (; prec && ++p < endp; --prec) { + *t++ = *p; + } + + + if (!prec && ++p < endp) { + fract = 0; + startp = cvtround_f(0, &expcnt, startp, + t - 1, *p, negp); + } + + --expcnt; + } + + else if (fract) { + + for (expcnt = -1;; --expcnt) { + fract = modf(fract * 10, &tmp); + if (tmp) { + break; + } + } + *t++ = (int) tmp + '0'; + if (prec || sharpflag) { + *t++ = '.'; + } + } else { + *t++ = '0'; + if (prec || sharpflag) { + *t++ = '.'; + } + } + + if (fract) { + if (prec) { + do { + fract = modf(fract * 10, &tmp); + *t++ = (int) tmp + '0'; + } while (--prec && fract); + } + if (fract) { + startp = cvtround_f(fract, &expcnt, startp, + t - 1, '0', negp); + } + } + + for (; prec--; *t++ = '0'); + + + if (gformat && !sharpflag) { + while (t > startp && *--t == '0'); + if (*t == '.') { + --t; + } + ++t; + } + t = exponent(t, expcnt, fmtch); + break; + case 'g': + case 'G': + + if (!prec) { + ++prec; + } + + + if (expcnt > prec || (!expcnt && fract && fract < .0001)) { + + --prec; + fmtch -= 2; + gformat = 1; + goto eformat; + } + + if (expcnt) { + for (; ++p < endp; *t++ = *p, --prec); + } else { + *t++ = '0'; + } + + if (prec || sharpflag) { + dotrim = 1; + *t++ = '.'; + } else { + dotrim = 0; + } + + while (prec && fract) { + fract = modf(fract * 10, &tmp); + *t++ = (int) tmp + '0'; + prec--; + } + if (fract) { + startp = cvtround_f(fract, 0, startp, t - 1, '0', negp); + } + + if (sharpflag) { + for (; prec--; *t++ = '0'); + } else if (dotrim) { + while (t > startp && *--t == '0'); + if (*t != '.') { + ++t; + } + } + } + return (t - startp); +} + +#endif +*/ + + +void LoggerPrintf( + tLoggerInterface *logger, + const char *authorStatic, + const uint8_t authorLen, + eLoggerLevel loglevel, + bool complete, + const char *fmt, + ... +) { + +// va_list args; +// int err; +// +// LoggerCnInfo(logger, "ss", "", 0); +// +// va_start (args, fmt); +// err = stream_logger_vprintf(logger, fmt, args); +// va_end (args); +// +// LoggerInfo(logger, "ss", "", 0); + + //char str[128]; + char *str = (char *) logger->getMemPrintfBufLog(logger->env, authorStatic, authorLen, LOG_BUF_BIG2); + + int result; + va_list args; + + va_start(args, fmt); + result = vsnprintf(str, MAX_LEN_BUF_BIG2_LOG, fmt, args); + va_end(args); + + +// va_start(args, fmt); +// result = vsprintf(str, fmt, args); +// va_end(args); + + if (result > 0) { + logger->logging(logger->env, authorStatic, authorLen, loglevel, str, result, complete); + } else { + str[0] = 0; + strcat(str, "Error LOG"); + logger->logging(logger->env, authorStatic, authorLen, loglevel, str, sizeof("Error LOG") - 1, complete); + } +} + +#ifdef TEST +/* + * Testing vprintf(3). + */ +#undef printf +#undef fclose +#undef fflush +#undef vprintf +#undef getchar +#undef putchar +#undef gets +#undef puts +#undef feof +#define snprintf snprintf_tmp +#define vsnprintf vsnprintf_tmp +#include +#undef snprintf +#undef vsnprintf + +#ifndef UCHAR_MAX +#define UCHAR_MAX ((unsigned char) -1) +#endif +#ifndef USHRT_MAX +#define USHRT_MAX ((unsigned short) -1) +#endif + +#define fputs(s,f) printstring (s) +#define puts(s) { printstring (s); write (1, "\n", 1); } + +unsigned write (int fd, const void *buf, unsigned count); + +static void +printchar (stream_t *stream, short ch) +{ + write (1, &ch, 1); +} + +static void +printstring (const char *str) +{ + write (1, str, strlen (str)); +} + +int +printf (const char *fmt, ...) +{ + static stream_interface_t output_interface = { + (void (*) (stream_t*, short)) printchar, + 0, 0, + }; + stream_t output = { &output_interface }; + va_list args; + int err; + + va_start (args, fmt); + err = stream_vprintf (&output, fmt, args); + va_end (args); + return err; +} + +static void rfg1 (void); +static void rfg2 (void); +static void rfg3 (void); + +static void fmtchk (const char *fmt) +{ + (void)fputs (fmt, stdout); + (void)printf (":\t`"); + (void)printf (fmt, 0x12); + (void)printf ("'\n"); +} + +static void fmtst1chk (const char *fmt) +{ + (void)fputs (fmt, stdout); + (void)printf (":\t`"); + (void)printf (fmt, 4, 0x12); + (void)printf ("'\n"); +} + +static void fmtst2chk (const char *fmt) +{ + (void)fputs (fmt, stdout); + (void)printf (":\t`"); + (void)printf (fmt, 4, 4, 0x12); + (void)printf ("'\n"); +} + +/* This page is covered by the following copyright: */ + +/* (C) Copyright C E Chew + * + * Feel free to copy, use and distribute this software provided: + * + * 1. you do not pretend that you wrote it + * 2. you leave this copyright notice intact. + */ + +/* + * Extracted from exercise.c for glibc-1.05 bug report by Bruce Evans. + */ + +#define DEC -123 +#define INT 255 +#define UNS (~0) + +/* Formatted Output Test + * + * This exercises the output formatting code. + */ + +static void fp_test (void) +{ + int i, j, k, l; + char buf[7]; + char *prefix = buf; + char tp[20]; + + puts ("\nFormatted output test"); + printf ("prefix 6d 6o 6x 6X 6u\n"); + strcpy (prefix, "%"); + for (i = 0; i < 2; i++) { + for (j = 0; j < 2; j++) { + for (k = 0; k < 2; k++) { + for (l = 0; l < 2; l++) { + strcpy (prefix, "%"); + if (i == 0) + strcat (prefix, "-"); + if (j == 0) + strcat (prefix, "+"); + if (k == 0) + strcat (prefix, "#"); + if (l == 0) + strcat (prefix, "0"); + printf ("%5s |", prefix); + strcpy (tp, prefix); + strcat (tp, "6d |"); + printf (tp, DEC); + strcpy (tp, prefix); + strcat (tp, "6o |"); + printf (tp, INT); + strcpy (tp, prefix); + strcat (tp, "6x |"); + printf (tp, INT); + strcpy (tp, prefix); + strcat (tp, "6X |"); + printf (tp, INT); + strcpy (tp, prefix); + strcat (tp, "6u |"); + printf (tp, UNS); + printf ("\n"); + } + } + } + } + printf ("%10s\n", (char *)0); + printf ("%-10s\n", (char *)0); +} + +int main () +{ + static char shortstr[] = "Hi, Z."; + static char longstr[] = "Good morning, Doctor Chandra. This is Hal. \ +I am ready for my first lesson today."; + int result = 0; + + fmtchk ("%.4x"); + fmtchk ("%04x"); + fmtchk ("%4.4x"); + fmtchk ("%04.4x"); + fmtchk ("%4.3x"); + fmtchk ("%04.3x"); + + fmtst1chk ("%.*x"); + fmtst1chk ("%0*x"); + fmtst2chk ("%*.*x"); + fmtst2chk ("%0*.*x"); + + printf ("binary format:\t\"%b\"\n", 55, "\20\7b7\6b6\5b5\4b4\3b3\2b2\1b1"); + printf ("nil pointer (padded):\t\"%10p\"\n", (void *)0); + + printf ("decimal negative:\t\"%d\"\n", -2345); + printf ("octal negative:\t\"%o\"\n", -2345); + printf ("hex negative:\t\"%x\"\n", -2345); + printf ("long decimal number:\t\"%ld\"\n", -123456L); + printf ("long octal negative:\t\"%lo\"\n", -2345L); + printf ("long unsigned decimal number:\t\"%lu\"\n", -123456L); + printf ("zero-padded LDN:\t\"%010ld\"\n", -123456L); + printf ("left-adjusted ZLDN:\t\"%-010ld\"\n", -123456L); + printf ("space-padded LDN:\t\"%10ld\"\n", -123456L); + printf ("left-adjusted SLDN:\t\"%-10ld\"\n", -123456L); + + printf ("zero-padded string:\t\"%010s\"\n", shortstr); + printf ("left-adjusted Z string:\t\"%-010s\"\n", shortstr); + printf ("space-padded string:\t\"%10s\"\n", shortstr); + printf ("left-adjusted S string:\t\"%-10s\"\n", shortstr); + printf ("null string:\t\"%s\"\n", (char *)0); + printf ("limited string:\t\"%.22s\"\n", longstr); + + printf ("e-style >= 1:\t\"%e\"\n", 12.34); + printf ("e-style >= .1:\t\"%e\"\n", 0.1234); + printf ("e-style < .1:\t\"%e\"\n", 0.001234); + printf ("e-style big:\t\"%.60e\"\n", 1e20); + printf ("e-style == .1:\t\"%e\"\n", 0.1); + printf ("f-style >= 1:\t\"%f\"\n", 12.34); + printf ("f-style >= .1:\t\"%f\"\n", 0.1234); + printf ("f-style < .1:\t\"%f\"\n", 0.001234); + printf ("g-style >= 1:\t\"%g\"\n", 12.34); + printf ("g-style >= .1:\t\"%g\"\n", 0.1234); + printf ("g-style < .1:\t\"%g\"\n", 0.001234); + printf ("g-style big:\t\"%.60g\"\n", 1e20); + + printf (" %6.5f\n", .099999999860301614); + printf (" %6.5f\n", .1); + printf ("x%5.4fx\n", .5); + + printf ("%#03x\n", 1); + + printf ("something really insane: %.10000f\n", 1.0); + + { + double d = FLT_MIN; + int niter = 17; + + while (niter-- != 0) + printf ("%.17e\n", d / 2); + fflush (stdout); + } + + printf ("%15.5e\n", 4.9406564584124654e-324); + +#define FORMAT "|%12.4f|%12.4e|%12.4g|\n" + printf (FORMAT, 0.0, 0.0, 0.0); + printf (FORMAT, 1.0, 1.0, 1.0); + printf (FORMAT, -1.0, -1.0, -1.0); + printf (FORMAT, 100.0, 100.0, 100.0); + printf (FORMAT, 1000.0, 1000.0, 1000.0); + printf (FORMAT, 10000.0, 10000.0, 10000.0); + printf (FORMAT, 12345.0, 12345.0, 12345.0); + printf (FORMAT, 100000.0, 100000.0, 100000.0); + printf (FORMAT, 123456.0, 123456.0, 123456.0); +#undef FORMAT + + { + char buf[20]; + char buf2[512]; + + printf ("snprintf (\"%%30s\", \"foo\") == %d, \"%.*s\"\n", + snprintf (buf, sizeof (buf), "%30s", "foo"), (int)sizeof (buf), + buf); + printf ("snprintf (\"%%.999999u\", 10) == %d\n", + snprintf (buf2, sizeof (buf2), "%.999999u", 10)); + } + + fp_test (); + + printf ("%e should be 1.234568e+06\n", 1234567.8); + printf ("%f should be 1234567.800000\n", 1234567.8); + printf ("%g should be 1.23457e+06\n", 1234567.8); + printf ("%g should be 123.456\n", 123.456); + printf ("%g should be 1e+06\n", 1000000.0); + printf ("%g should be 10\n", 10.0); + printf ("%g should be 0.02\n", 0.02); + + { + char buf[200]; + + snprintf (buf, sizeof(buf), "%*s%*s%*s", -1, "one", -20, "two", -30, "three"); + + result |= strcmp (buf, + "onetwo three "); + + puts (result != 0 ? "Test failed!" : "Test ok."); + } +#if 0 + { + char buf[200]; + + snprintf (buf, sizeof(buf), "%07Lo", 040000000000ll); + printf ("sprintf (buf, \"%%07Lo\", 040000000000ll) = %s", buf); + + if (strcmp (buf, "40000000000") != 0) { + result = 1; + fputs ("\tFAILED", stdout); + } + puts (""); + } + + printf ("printf (\"%%hhu\", %u) = %hhu\n", UCHAR_MAX + 2, UCHAR_MAX + 2); + printf ("printf (\"%%hu\", %u) = %hu\n", USHRT_MAX + 2, USHRT_MAX + 2); +#endif + puts ("--- Should be no further output. ---"); + rfg1 (); + rfg2 (); +#if 0 + rfg3 (); + { + char bytes[7]; + char buf[20]; + + memset (bytes, '\xff', sizeof bytes); + snprintf (buf, sizeof(buf), "foo%hhn\n", &bytes[3]); + if (bytes[0] != '\xff' || bytes[1] != '\xff' || bytes[2] != '\xff' + || bytes[4] != '\xff' || bytes[5] != '\xff' || bytes[6] != '\xff') { + puts ("%hhn overwrite more bytes"); + result = 1; + } + if (bytes[3] != 3) { + puts ("%hhn wrote incorrect value"); + result = 1; + } + } +#endif + return result != 0; +} + +static void rfg1 (void) +{ + char buf[100]; + + snprintf (buf, sizeof(buf), "%5.s", "xyz"); + if (strcmp (buf, " ") != 0) + printf ("got: '%s', expected: '%s'\n", buf, " "); + snprintf (buf, sizeof(buf), "%5.f", 33.3); + if (strcmp (buf, " 33") != 0) + printf ("got: '%s', expected: '%s'\n", buf, " 33"); + snprintf (buf, sizeof(buf), "%8.e", 33.3e7); + if (strcmp (buf, " 3e+08") != 0) + printf ("got: '%s', expected: '%s'\n", buf, " 3e+08"); + snprintf (buf, sizeof(buf), "%8.E", 33.3e7); + if (strcmp (buf, " 3E+08") != 0) + printf ("got: '%s', expected: '%s'\n", buf, " 3E+08"); + snprintf (buf, sizeof(buf), "%.g", 33.3); + if (strcmp (buf, "3e+01") != 0) + printf ("got: '%s', expected: '%s'\n", buf, "3e+01"); + snprintf (buf, sizeof(buf), "%.G", 33.3); + if (strcmp (buf, "3E+01") != 0) + printf ("got: '%s', expected: '%s'\n", buf, "3E+01"); +} + +static void rfg2 (void) +{ + int prec; + char buf[100]; + + prec = 0; + snprintf (buf, sizeof(buf), "%.*g", prec, 3.3); + if (strcmp (buf, "3") != 0) + printf ("got: '%s', expected: '%s'\n", buf, "3"); + prec = 0; + snprintf (buf, sizeof(buf), "%.*G", prec, 3.3); + if (strcmp (buf, "3") != 0) + printf ("got: '%s', expected: '%s'\n", buf, "3"); + prec = 0; + snprintf (buf, sizeof(buf), "%7.*G", prec, 3.33); + if (strcmp (buf, " 3") != 0) + printf ("got: '%s', expected: '%s'\n", buf, " 3"); + prec = 3; + snprintf (buf, sizeof(buf), "%04.*o", prec, 33); + if (strcmp (buf, " 041") != 0) + printf ("got: '%s', expected: '%s'\n", buf, " 041"); + prec = 7; + snprintf (buf, sizeof(buf), "%09.*u", prec, 33); + if (strcmp (buf, " 0000033") != 0) + printf ("got: '%s', expected: '%s'\n", buf, " 0000033"); + prec = 3; + snprintf (buf, sizeof(buf), "%04.*x", prec, 33); + if (strcmp (buf, " 021") != 0) + printf ("got: '%s', expected: '%s'\n", buf, " 021"); + prec = 3; + snprintf (buf, sizeof(buf), "%04.*X", prec, 33); + if (strcmp (buf, " 021") != 0) + printf ("got: '%s', expected: '%s'\n", buf, " 021"); +} + +static void rfg3 (void) +{ + char buf[100]; + double g = 5.0000001; + unsigned long l = 1234567890; + double d = 321.7654321; + const char s[] = "test-string"; + int i = 12345; + int h = 1234; + + snprintf (buf, sizeof(buf), + "%1$*5$d %2$*6$hi %3$*7$lo %4$*8$f %9$*12$e %10$*13$g %11$*14$s", + i, h, l, d, 8, 5, 14, 14, d, g, s, 14, 3, 14); + if (strcmp (buf, + " 12345 1234 11145401322 321.765432 3.217654e+02 5 test-string") != 0) + printf ("got: '%s', expected: '%s'\n", buf, + " 12345 1234 11145401322 321.765432 3.217654e+02 5 test-string"); +} +#endif diff --git a/MODULES/LoggerInterface/modular.json b/MODULES/LoggerInterface/modular.json new file mode 100644 index 0000000..330c86e --- /dev/null +++ b/MODULES/LoggerInterface/modular.json @@ -0,0 +1,17 @@ +{ + "dep": [ + { + "type": "local", + + "dir": "./MODULES/BaseTypes" + } + ], + "cmake": { + "inc_dirs": [ + "Inc" + ], + "srcs": [ + "Src/**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/LoggerToSerialPort/Inc/LoggerToSerialPort.h b/MODULES/LoggerToSerialPort/Inc/LoggerToSerialPort.h new file mode 100644 index 0000000..1cd50f9 --- /dev/null +++ b/MODULES/LoggerToSerialPort/Inc/LoggerToSerialPort.h @@ -0,0 +1,85 @@ +// +// Created by CFIF on 13.11.22. +// + +#ifndef UVEOS_ON_NATION_LOGGERTOSERIALPORT_H +#define UVEOS_ON_NATION_LOGGERTOSERIALPORT_H + +#include "SerialPort.h" +#include "LoggerInterface.h" +#include "RtcIO.h" +#include + +typedef struct { + uint8_t buf_big1[MAX_LEN_BUF_BIG1_LOG]; + uint8_t buf_big2[MAX_LEN_BUF_BIG2_LOG]; + uint8_t buf_small[MAX_LEN_BUF_SMALL_LOG]; + +} tLoggerDataBuf; + +typedef struct __attribute__((packed)) { + uint8_t start_pkt; // 0x02 + uint8_t type_pkt; + uint8_t len_pkt; + uint32_t timestamp; + uint8_t channel; + uint8_t flags; + uint8_t dlc; + uint32_t id; + uint8_t data[8]; // максимум 8 байт +} CanLogPacket_t; + +typedef struct { + tSerialPortIO *serialPortIo_VIRT; + tSerialPortIO *serialPortIo_PHYSIC; + tRtcIO *rtc; + uint32_t timeout; + uint32_t timeoutTransmittedLog; + uint8_t authorLimit; + bool open; + tLoggerInterface logger; + uint16_t flags; + int32_t greenwichOffset; + + uint8_t buf_LOG[1024]; + + tLoggerDataBuf bufLogger[MAX_COUNT_BUF_LOG]; + uint8_t bufLoggerNames[MAX_COUNT_BUF_LOG][MAX_LEN_BUF_NAME_LOG]; + uint8_t countBufLoggerNames; + + uint8_t bufLoggerCan[32]; + + osMutexId_t access; + + struct { + osThreadId_t id; + uint32_t stack[384]; + StaticTask_t controlBlock; + osThreadAttr_t attr; + } thread; + +} tLoggerToSerialPort; + +#define SERIAL_LOGGER_SHOW_AUTHOR 0b1 << 0 +#define SERIAL_LOGGER_SHOW_LOG_LEVEL 0b1 << 1 +#define SERIAL_LOGGER_SHOW_TIME 0b1 << 2 +#define SERIAL_LOGGER_SHOW_DATE 0b1 << 3 + +void LoggerToSerialPort_Init( + tLoggerToSerialPort *env, + int32_t greenwichOffset, + tSerialPortIO *serialPortIo_VIRT, + tSerialPortIO *serialPortIo_PHYSIC, + tRtcIO *rtc, + uint16_t flags, + uint32_t timeoutTransmittedLog +// bool showDate, +// bool showTime, +// bool showLoglevel, +// bool showAuthor +); + +void LogTransmitter_StartThread(tLoggerToSerialPort *env); +void LoggerToSerialPort_Cmd(tLoggerToSerialPort *env, char *msg, uint16_t msgLen); + +#endif //UVEOS_ON_NATION_LOGGERTOSERIALPORT_H diff --git a/MODULES/LoggerToSerialPort/Src/LoggerToSerialPort.c b/MODULES/LoggerToSerialPort/Src/LoggerToSerialPort.c new file mode 100644 index 0000000..d38b379 --- /dev/null +++ b/MODULES/LoggerToSerialPort/Src/LoggerToSerialPort.c @@ -0,0 +1,300 @@ +// +// Created by CFIF on 13.11.22. +// +#include +#include "LoggerToSerialPort.h" +#include "SystemDelayInterface.h" +#include "AsciiStringAssmeblingUtils.h" +#include "Rtc.h" +#include +#include "CmsisRtosThreadUtils.h" +#include "memory.h" +#include CMSIS_device_header + +static uint8_t * +getMemLoggerBufLog(tLoggerToSerialPort *env, char *authorStatic, const uint8_t authorLen, LOG_BUF_TYPE logBufType) { + + for (uint8_t i = 0; i < env->countBufLoggerNames; ++i) { + if (memcmp(env->bufLoggerNames[i], authorStatic, authorLen) == 0) { + + if (logBufType == LOG_BUF_SMALL) { + return env->bufLogger[i].buf_small; + } + + if (logBufType == LOG_BUF_BIG1) { + return env->bufLogger[i].buf_big1; + } + + return env->bufLogger[i].buf_big2; + } + } + + configASSERT(env->countBufLoggerNames < MAX_COUNT_BUF_LOG); + + uint8_t len = authorLen; + if (authorLen > MAX_LEN_BUF_NAME_LOG) { + len = MAX_LEN_BUF_NAME_LOG; + } + + memcpy(env->bufLoggerNames[env->countBufLoggerNames], authorStatic, len); + ++env->countBufLoggerNames; + + if (logBufType == LOG_BUF_SMALL) { + return env->bufLogger[env->countBufLoggerNames - 1].buf_small; + } + + if (logBufType == LOG_BUF_BIG1) { + return env->bufLogger[env->countBufLoggerNames - 1].buf_big1; + } + + return env->bufLogger[env->countBufLoggerNames - 1].buf_big2; + +} + +static void LoggerToSerialPort_TimeToString(time_t timestamp, char *strbuf) { + struct tm timestampTM; + localtime_r(×tamp, ×tampTM); + asctime_r(×tampTM, strbuf); +} + +static uint32_t LoggerToSerialPort_PrintLegend( + tLoggerToSerialPort *env, + char *outStr[], + char *authorStatic, + const uint8_t authorLen, + eLoggerLevel loglevel +) { + //char str[128]; + char *str = (char *) getMemLoggerBufLog(env, authorStatic, authorLen, LOG_BUF_BIG1); + size_t strLen = 0; + + if (env->flags & (SERIAL_LOGGER_SHOW_DATE | SERIAL_LOGGER_SHOW_TIME)) { + + time_t timestamp; + //char timeString[24]; + char *timeString = (char *) getMemLoggerBufLog(env, authorStatic, authorLen, LOG_BUF_SMALL); + + if (env->rtc) { + RtcGet(env->rtc, ×tamp); + timestamp += env->greenwichOffset * 3600; + } else { + uint32_t msFromDeviceStart = SystemGetMs() / 1000; + timestamp = 1672531200 + msFromDeviceStart; + } + + LoggerToSerialPort_TimeToString(timestamp, timeString); + + if (env->flags & SERIAL_LOGGER_SHOW_DATE) { + vAsciiStringAdd(str, &strLen, &timeString[20], 4); + vAsciiStringAdd(str, &strLen, &timeString[3], 7); + vAsciiStringAdd(str, &strLen, " ", 1); + } + + if (env->flags & SERIAL_LOGGER_SHOW_TIME) { + vAsciiStringAdd(str, &strLen, &timeString[11], 8); + vAsciiStringAdd(str, &strLen, " ", 1); + } + } + + if (env->flags & SERIAL_LOGGER_SHOW_AUTHOR) { + //выводим автора сообщения + vAsciiStringAdd(str, &strLen, authorStatic, authorLen); + } + + if (env->flags & SERIAL_LOGGER_SHOW_LOG_LEVEL) { + tStringStatic levelName = LOGGER_LEVEL_NAMES[loglevel]; + //выводим уровень сообщения + vAsciiStringAddChar(str, &strLen, '['); + vAsciiStringAdd(str, &strLen, levelName.data, levelName.length); + vAsciiStringAddChar(str, &strLen, ']'); + } + + + //разделитель + if (env->flags) + vAsciiStringAdd(str, &strLen, ": ", 2); + +// SerialPortTransmit(env->serialPortIo_VIRT, (uint8_t *) str, strLen, env->timeout); + *outStr = str; + + env->open = true; + + return strLen; +} + +#include // для offsetof + +static void LoggerCanToSerialPort_Logging( + tLoggerToSerialPort *env, + uint16_t mChannel, + uint8_t mFlags, + uint8_t mDLC, + uint32_t mID, + uint8_t *mData, + uint32_t timestamp +) { + if (osMutexAcquire(env->access, env->timeout) == osOK) { + CanLogPacket_t *pkt = (CanLogPacket_t*)env->bufLoggerCan; + + // Заполняем структуру + pkt->start_pkt = 0x02; + pkt->type_pkt = 1; + pkt->timestamp = timestamp; + pkt->channel = mChannel; + pkt->flags = mFlags; + pkt->dlc = mDLC; + pkt->id = mID; + + // Копируем данные (только mDLC байт) + if (mData != NULL && mDLC > 0) { + memcpy(pkt->data, mData, mDLC); + } + // Остальные байты data[8] не трогаем – они не будут отправлены + + // Вычисляем len_pkt = полезная нагрузка (без start, type, len, end) + pkt->len_pkt = (4 + 1 + 1 + 4 + mDLC + 1); // = mDLC + 11 (без CRC) + + // Размер данных без завершающих байтов (CRC и 0x03) + size_t data_size = offsetof(CanLogPacket_t, data) + mDLC; // от начала пакета до конца данных + + // Вычисляем CRC как сумму всех байтов, кроме pkt->start_pkt, + // т.е. начиная с type_pkt и заканчивая последним байтом данных + uint8_t crc = 0; + uint8_t *crc_start = (uint8_t*)pkt + 1; // пропускаем start_pkt + size_t crc_len = data_size - 1; // размер данных для CRC (без start_pkt) + for (size_t i = 0; i < crc_len; i++) { + crc += crc_start[i]; + } + + // Записываем CRC после данных + uint8_t *crc_ptr = (uint8_t*)pkt + data_size; + *crc_ptr = crc; + + // Записываем байт 0x03 после CRC + uint8_t *end_ptr = (uint8_t*)pkt + data_size + 1; + *end_ptr = 0x03; + + // Размер для отправки: от начала до 0x03 включительно + size_t pkt_size = data_size + 2; // данные + CRC + 0x03 + + // Отправка +// SerialPortTransmit(env->serialPortIo_VIRT, env->bufLoggerCan, pkt_size, env->timeout); + + osMutexRelease(env->access); + } +} + +static void LoggerToSerialPort_Logging( + tLoggerToSerialPort *env, + char *authorStatic, + const uint8_t authorLen, + eLoggerLevel loglevel, + char *msg, + uint16_t msgLen, + bool complete +) { + +// uint32_t adr = *(uint32_t *)(env->serialPortIo->env); + +// uint32_t timeoutLocal = env->timeout; + // Если это UART (виртуальный) +// if (adr < PERIPH_BASE) { +// env->timeout = 0; +// } + char *outStr = NULL; + uint32_t lenStr; + +// if (!env->open) { + lenStr = LoggerToSerialPort_PrintLegend(env, &outStr, authorStatic, authorLen, loglevel); +// } + + if (osMutexAcquire(env->access, env->timeout) == osOK) { + + //выводим сообщение + if (outStr != NULL) { + SerialPortTransmit(env->serialPortIo_VIRT, (uint8_t *) outStr, lenStr, env->timeout); + } + + SerialPortTransmit(env->serialPortIo_VIRT, (uint8_t *) msg, msgLen, env->timeout); + + if (complete) { + //переводим строку + SerialPortTransmit(env->serialPortIo_VIRT, (uint8_t *) "\r\n", 2, env->timeout); + // env->open = false; + } else { + // env->open = true; + } + osMutexRelease(env->access); + } + +// env->timeout = timeoutLocal; +} + +void LoggerToSerialPort_Cmd(tLoggerToSerialPort *env, char *msg, uint16_t msgLen) { + + if (osMutexAcquire(env->access, env->timeout) == osOK) { + SerialPortTransmit(env->serialPortIo_VIRT, (uint8_t *) msg, msgLen, env->timeout); + osMutexRelease(env->access); + } +} + +void LoggerToSerialPort_Init( + tLoggerToSerialPort *env, + int32_t greenwichOffset, + tSerialPortIO *serialPortIo_VIRT, + tSerialPortIO *serialPortIo_PHYSIC, + tRtcIO *rtc, + uint16_t flags, + uint32_t timeoutTransmittedLog +) { + env->serialPortIo_VIRT = serialPortIo_VIRT; + env->serialPortIo_PHYSIC = serialPortIo_PHYSIC; + env->open = false; + env->timeout = 0;// не ждем на каждой операции так как если порт исправен то все должно отрабатывать моментально + env->logger.env = env; + env->greenwichOffset = greenwichOffset; + env->logger.logging = (LoggerGenericMethod) LoggerToSerialPort_Logging; + + env->logger.loggingCan = (LoggerGenericCanMethod) LoggerCanToSerialPort_Logging; + + env->logger.getMemPrintfBufLog = (getMemPrintfBufLogMethod) getMemLoggerBufLog; + env->rtc = rtc; + env->flags = flags; + env->timeoutTransmittedLog = timeoutTransmittedLog; + + env->access = osMutexNew(NULL); + +// env->showDate = showDate; +// env->showTime = showTime; +// env->showLoglevel = showLoglevel; +// env->showAuthor = showAuthor; + + InitThreadAtrStatic(&env->thread.attr, "LogTransmitter", env->thread.controlBlock, env->thread.stack, + osPriorityNormal); + + LogTransmitter_StartThread(env); +} + + +static _Noreturn void LogTransmitter_Thread(tLoggerToSerialPort *env) { + for (;;) { + uint16_t len = env->serialPortIo_VIRT->receive(env->serialPortIo_VIRT->env, env->buf_LOG, + sizeof(env->buf_LOG), env->timeoutTransmittedLog); + + if (len == 1024) { + asm("nop"); + } + + if (len > 0) { + len = env->serialPortIo_PHYSIC->transmit(env->serialPortIo_PHYSIC->env, env->buf_LOG, + len, env->timeoutTransmittedLog); + } + } +} + + +void LogTransmitter_StartThread(tLoggerToSerialPort *env) { + if (!env->thread.id) { + env->thread.id = osThreadNew((osThreadFunc_t) (LogTransmitter_Thread), (void *) (env), &env->thread.attr); + } +} \ No newline at end of file diff --git a/MODULES/LoggerToSerialPort/modular.json b/MODULES/LoggerToSerialPort/modular.json new file mode 100644 index 0000000..8806536 --- /dev/null +++ b/MODULES/LoggerToSerialPort/modular.json @@ -0,0 +1,37 @@ +{ + "dep": [ + { + "type": "local", + + "dir": "./MODULES/RtcInterface" + }, + { + "type": "local", + + "dir": "./MODULES/Rtc" + }, + { + "type": "local", + + "dir": "./MODULES/SerialPort" + }, + { + "type": "local", + + "dir": "./MODULES/LoggerInterface" + }, + { + "type": "local", + + "dir": "./MODULES/AsciiStringAssemblingUtils" + } + ], + "cmake": { + "inc_dirs": [ + "Inc" + ], + "srcs": [ + "Src/**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_board_conf.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_board_conf.h new file mode 100644 index 0000000..5ce82ab --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_board_conf.h @@ -0,0 +1,58 @@ +/** + * @file fc7xxx_board_conf.h + * @author Flagchip032 + * @brief FC7xxx board configuration file + * @version 0.1.0 + * @date 2024-01-12 + * + * @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-12 Flagchip032 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef _DRIVER_FC7XXX_BOARD_CONF_H_ +#define _DRIVER_FC7XXX_BOARD_CONF_H_ +#include "device_header.h" + +#if defined(__cplusplus) +extern "C" { +#endif +/** + * @addtogroup fc7xxx_board_conf + * @{ + */ + +/******************* Oscillator Values *******************/ +/** + * @brief Fast OSC frequency + */ +#ifndef FOSC_FREQUENCY +#define FOSC_FREQUENCY 24000000U +#endif + +/** + * @brief Slow OSC frequency + */ +#ifndef SOSC_FREQUENCY +#define SOSC_FREQUENCY 32768U +#endif + +/** + * @brief FTU input TCLK frequency + */ +#ifndef PCC_FTU_TCLK_FREQ +#define PCC_FTU_TCLK_FREQ 0U +#endif + + +/** @}*/ /* fc7xxx_board_conf */ +#if defined(__cplusplus) +} +#endif +#endif diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_adc.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_adc.h new file mode 100644 index 0000000..51b715f --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_adc.h @@ -0,0 +1,422 @@ +/** + * @file fc7xxx_driver_adc.h + * @author Flagchip0126 + * @brief FC7xxx ADC driver type definition and API + * @version 0.1.0 + * @date 2024-01-15 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-15 Flagchip0126 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef _DRIVER_FC7XXX_DRIVER_ADC_H_ +#define _DRIVER_FC7XXX_DRIVER_ADC_H_ +#include "device_header.h" +#include "HwA_adc.h" +#include "fc7xxx_driver_dma.h" + +#if defined(__cplusplus) +extern "C" { +#endif +/** + * @addtogroup fc7xxx_driver_adc + * @{ + */ + +/** + * @name ADC0 Internal Channels + * @brief Available internal ADC channels for ADC Instance 0 + * + * @{ + */ +#define ADC0_CHANNEL_VBG_BUFFER ADC_CHANNEL_INTERNAL_0 +#define ADC0_CHANNEL_V25 ADC_CHANNEL_INTERNAL_1 +#define ADC0_CHANNEL_V11 ADC_CHANNEL_INTERNAL_2 +#define ADC0_CHANNEL_CMP0_DAC ADC_CHANNEL_INTERNAL_4 +#define ADC0_CHANNEL_TEMPSENSOR_OUT ADC_CHANNEL_INTERNAL_5 /* Must be in differential mode */ +/** @}*/ + +/** + * @name ADC1 Internal channels + * @brief Available internal ADC channels for ADC Instance 1 + * + * @{ + */ +#define ADC1_CHANNEL_V11_PD0 ADC_CHANNEL_INTERNAL_0 +#define ADC1_CHANNEL_VREFH ADC_CHANNEL_INTERNAL_1 +#define ADC1_CHANNEL_VDDA ADC_CHANNEL_INTERNAL_2 +#define ADC1_CHANNEL_V15 ADC_CHANNEL_INTERNAL_3 +#define ADC1_CHANNEL_CMP1_DAC ADC_CHANNEL_INTERNAL_4 +/** @}*/ + +/** + * @brief The ADC conversion complete callback function prototype + * + */ +typedef void (*ADC_ConvCompleteCallbackType)(const uint32_t *const pBuff); + +/** + * @brief The ADC overrun callback function prototype + * + */ +typedef void (*ADC_OverRunInterruptCallbackType)(void); + +/** + * @brief The ADC compare callback function prototype + * + */ +typedef void (*ADC_CompareInterruptCallbackType)(void); + +/** + * @brief The ADC end of sequence group callback function prototype + * + */ +typedef void (*ADC_EndOfSeqGroupInterruptCallbackType)(uint8_t u8SeqGroupIdx); + +/** + * @brief The instance index of the ADC peripheral + * + */ +typedef enum +{ + ADC_INSTANCE_0 = 0U, /*!< ADC instance 0 is selected */ + ADC_INSTANCE_1 = 1U, /*!< ADC instance 1 is selected */ +} ADC_InstanceType; + +/** + * @brief The channel selected for ADC conversion + * + */ +typedef enum +{ + ADC_CHANNEL_0 = 0U, + ADC_CHANNEL_1 = 1U, + ADC_CHANNEL_2 = 2U, + ADC_CHANNEL_3 = 3U, + ADC_CHANNEL_4 = 4U, + ADC_CHANNEL_5 = 5U, + ADC_CHANNEL_6 = 6U, + ADC_CHANNEL_7 = 7U, + ADC_CHANNEL_8 = 8U, + ADC_CHANNEL_9 = 9U, + ADC_CHANNEL_10 = 10U, + ADC_CHANNEL_11 = 11U, + ADC_CHANNEL_12 = 12U, + ADC_CHANNEL_13 = 13U, + ADC_CHANNEL_14 = 14U, + ADC_CHANNEL_15 = 15U, + ADC_CHANNEL_16 = 16U, + ADC_CHANNEL_17 = 17U, + ADC_CHANNEL_18 = 18U, + ADC_CHANNEL_19 = 19U, + ADC_CHANNEL_20 = 20U, + ADC_CHANNEL_21 = 21U, + ADC_CHANNEL_22 = 22U, + ADC_CHANNEL_23 = 23U, + ADC_CHANNEL_24 = 24U, + ADC_CHANNEL_25 = 25U, + ADC_CHANNEL_26 = 26U, + ADC_CHANNEL_27 = 27U, + ADC_CHANNEL_28 = 28U, + ADC_CHANNEL_29 = 29U, + ADC_CHANNEL_30 = 30U, + ADC_CHANNEL_31 = 31U, + ADC_CHANNEL_INTERNAL_0 = 32U, + ADC_CHANNEL_INTERNAL_1 = 33U, + ADC_CHANNEL_INTERNAL_2 = 34U, + ADC_CHANNEL_INTERNAL_3 = 35U, + ADC_CHANNEL_INTERNAL_4 = 36U, + ADC_CHANNEL_INTERNAL_5 = 37U +} ADC_ChannelType; + +/** + * @brief The channel selected for ADC conversion in differential mode + * + */ +typedef enum +{ + ADC_CHANNEL_0_4 = 0U, + ADC_CHANNEL_1_5 = 1U, + ADC_CHANNEL_2_6 = 2U, + ADC_CHANNEL_3_7 = 3U, + ADC_CHANNEL_TEMPSENSOR = 37U +} ADC_DifferentialChannelType; + +/** + * @brief The ADC sample time option for selection + * + */ +typedef enum +{ + ADC_SAMPLE_TIME_OPTION_0 = 0U, + ADC_SAMPLE_TIME_OPTION_1 = 1U, + ADC_SAMPLE_TIME_OPTION_2 = 2U, + ADC_SAMPLE_TIME_OPTION_3 = 3U +} ADC_SampleTimeOptionType; + +/** + * @brief The ADC SequenceGroup Index + * + */ +typedef enum +{ + ADC_SEQUENCE_GROUP_0 = 0U, + ADC_SEQUENCE_GROUP_1 = 1U, + ADC_SEQUENCE_GROUP_2 = 2U, + ADC_SEQUENCE_GROUP_3 = 3U +} ADC_SequenceGroupIndex; + +/** + * @brief ADC operation return values + * + */ +typedef enum +{ + ADC_STATUS_SUCCESS = 0x0U, /*!< The ADC operation is succeed */ + ADC_STATUS_ERROR = 0x1U, /*!< The ADC operation is failed */ + ADC_STATUS_TIMEOUT = 0x2U /*!< The ADC operation is failed because of time out */ +} ADC_StatusType; + +/** + * @brief Defines the converter configuration + * + * This structure is used to configure the ADC converter + * + * Implements : ADC_InitType + */ +typedef struct +{ + ADC_ResolutionType eResolution; /*!< ADC eResolution (8,10,12 bit) */ + ADC_AlignType eAlign; /*!< ADC alignment (left, right) */ + ADC_TrigModeType eTriggerMode; /*!< ADC trigger type (software, hardware) + - affects only the first control channel */ + bool bWaitEnable; /*!< Whether to enable ADC wait conversion mode */ + bool bSequenceGroupModeEnable; /*!< Whether to enable ADC sequence group mode, if true, ignore eSequenceMode*/ + bool bCalEnable; /*!< Whether to enable ADC calibration > */ + int32_t s32CalOffset; /*!< ADC calibration offset value > */ + int32_t s32CalGain; /*!< ADC calibration gain value > */ + ADC_TrgLatchUnitPri eTrgLatchUnitPri; /*!< Select priority of Trigger Latch Unit */ + ADC_ClockDivideType eClockDivider; /*!< ADC clock divider */ + ADC_SeqModeType eSequenceMode; /*!< ADC sequence mode (single, continuous, discontinuous) */ + bool bAutoDis; /*!< Whether to enable audo disable mode, only set this when adc in off state */ + ADC_OvrModeType eOverrunMode; /*!< Whether to preserve data when ADC overruns */ + ADC_RefType eVoltageRef; /*!< Voltage reference used (external, internal) */ + bool bHwAvgEnable; /*!< Enable averaging functionality */ + ADC_AverageType eHwAverage; /*!< Selection for number of samples used for averaging */ + uint8_t aSampleTimes[ADC_SAMPLE_TIME_OPTION_CNT]; /*!< ADC sample time options, range: 4 ~ 257 */ +} ADC_InitType; + +/** + * @brief The configuration option for the ADC channel + * + */ +typedef struct +{ + ADC_ChannelType eChannel; /*!< Selected ADC channel */ + ADC_SampleTimeOptionType eSampleTimeOption; /*!< The sample time selection for the channel */ + bool bDiff; /*!< Whether diff mode, if a channel do not support differential mode, ignore this */ +} ADC_ChannelCfgType; + +/** + * @brief The configuration option for the ADC sequence group + * + */ +typedef struct +{ + uint8_t u8Start; /*!< Sequence channel start */ + uint8_t u8Len; /*!< Sequence group length, is must be >= 0 */ +} ADC_SequenceGroupType; + + +/** + * @brief Defines the hardware compare configuration + * + * This structure is used to configure the hardware compare feature for the ADC + * + * Implements : ADC_CompareType + */ +typedef struct +{ + /* ADC_CMP_CTRL */ + bool bCmpEnable; /*!< Enable hardware compare */ + ADC_CmpChannelType eCmpSingleChn; /*!< 0: ADC compare on all channels; + 1: ADC compare on the selected channel */ + uint8_t u8CmpChnSel; /*!< Compare channel selection */ + + /* ADC_CMP_TR */ + uint16_t u16HighThres; /*!< Compare high threshold */ + uint16_t u16LowThres; /*!< Compare low threshold */ +} ADC_CompareType; + +/** + * @brief Defines the interrupt configuration + * + * This structure is used to configure the enabled interrupts and interrupt + * callbacks for ADC + * + */ +typedef struct +{ + /* ADC_INT_ENABLE */ + bool bConversionCompleteIntEn; /*!< Enable interrupt when conversion completed */ + bool bOverRunIntEn; /*!< Enable interrupt when overrun occured */ + bool bAnalogCmpIntEn; /*!< Enable interrupt when conversion result lays in the compare threshold */ + bool bEndOfSeqGroupIntEn; /*!< Enable interrupt when sequence group complete >*/ + uint32_t *pResultBuffer; /*!< When conversion complete interrupt is enabled, you shall provide the + result buffer to store the conversion results, this buffer only used for mode 0 ~ 3 */ + uint32_t *pSequenceGroupResultBuffer[ADC_SEQUENCE_GROUP_CNT]; /*!< When conversion complete interrupt is enabled, you shall provide the + result buffer to store the conversion results, these buffer only used for mode 4 */ + ADC_ConvCompleteCallbackType pConvCompleteNotify; /*!< Conversion complete interrupt callback */ + ADC_OverRunInterruptCallbackType pOverRunNotify; /*!< Overrun interrupt callback */ + ADC_CompareInterruptCallbackType pCompareNotify; /*!< Compare interrupt callback */ + ADC_EndOfSeqGroupInterruptCallbackType pEndOfSeqGroupNotify; /*!< End of Sequence End callback >*/ +} ADC_InterruptType; + +/** + * @brief Defines the DMA configuretion + * + * This structure is used to configure the DMA result transfer feature for ADC + * + */ +typedef struct +{ + bool bDmaEnable; /*!< Enable DMA for the ADC */ + ADC_SequenceGroupIndex eSeqGroupIndex; /*!< Only valid when SequenceGroupEn = true, otherwish ignore this */ + DMA_InstanceType eDmaInstance; /*!< The instance of DMA to use */ + DMA_ChannelType eDmaChannel; /*!< The DMA channel used to transfer the ADC conversion results */ + uint8_t u8ChannelPriority; /*!< The DMA channel priority, higher value means higher priority. + The priority for different channels must be unique. Default priority + value is same the channel number */ + uint32_t *pResultBuffer; /*!< Buffer to store the ADC conversion results */ + ADC_ConvCompleteCallbackType pConvCompleteNotify; /*!< DMA transfer complete callback */ +} ADC_DmaType; + +/** + * @brief Provide the default values of ADC_InitType + * + * @param pInitCfg the structure to initialize + */ +void ADC_InitStructure(ADC_InitType *const pInitCfg); + +/** + * @brief Initialize the ADC instance + * + * @param eInstance the ADC instance to init + * @param pInitCfg the configurations of the ADC instance + */ +void ADC_Init(const ADC_InstanceType eInstance, const ADC_InitType *const pInitCfg); + +/** + * @brief De-initialize the ADC instance + * + * Restore the ADC instance to its reset state + * + * @param eInstance the ADC instance to de-init + */ +void ADC_DeInit(const ADC_InstanceType eInstance); + +/** + * @brief Configure the ADC sample channels + * + * @param eInstance the ADC instance to use + * @param pChannels the channels to use + * @param u8ChnCnt the quantity of channels + */ +void ADC_InitChannel(const ADC_InstanceType eInstance, const ADC_ChannelCfgType aChannels[], + const uint8_t u8ChnCnt); + +/** + * @brief Configure the Sequence groups + * + * @param eInstance the ADC instance to use + * @param aSeqGroup the sequence groups to use + * @param u8SeqGroupCnt the quantity of sequence groups + */ +void ADC_InitSequenceGroup(const ADC_InstanceType eInstance, const ADC_SequenceGroupType aSeqGroup[], + const uint8_t u8SeqGroupCnt); + +/** + * @brief Configure the hardware compare feature of ADC + * + * @param eInstance the ADC instance to use + * @param pCmpCfg the compare paremeters + */ +void ADC_InitCompare(const ADC_InstanceType eInstance, const ADC_CompareType *const pCmpCfg); + +/** + * @brief Configure the interrupt of ADC + * + * @param eInstance the ADC instance to use + * @param pInterruptCfg the interrupt paremeters + */ +void ADC_InitInterrupt(const ADC_InstanceType eInstance, + const ADC_InterruptType *const pInterruptCfg); + +/** + * @brief Configure the DMA feature of ADC + * + * @param eInstance the ADC instance to use + * @param pAdcDmaCfg the DMA paremeters for the ADC instance + */ +void ADC_InitDmaChannel(const ADC_InstanceType eInstance, const ADC_DmaType *const pAdcDmaCfg); + +/** + * @brief Enable the ADC instance + * + * @param eInstance the ADC instance to enable + * @return ADC_StatusType whether ADC is enabled successfully + */ +ADC_StatusType ADC_Enable(const ADC_InstanceType eInstance); + +/** + * @brief Disable the ADC instance + * + * @param eInstance the ADC instance to disable + * @return ADC_StatusType whether ADC is disabled successfully + */ +ADC_StatusType ADC_Disable(const ADC_InstanceType eInstance); + +/** + * @brief Start the ADC conversion + * + * If the ADC sequence mode is single or continuous, and the trigger mode is ADC_TRIGMODE_SW, + * the adc conversion will start immediately. Otherwise, the ADC will wait for the trigger + * signal to start the conversion + * + * @param eInstance the ADC instance to start + */ +void ADC_Start(const ADC_InstanceType eInstance); + +/** + * @brief Stop the ADC conversion + * + * If the ADC sequence mode is single, it will stop the ongoing conversion. If no ongoing + * conversion, it will have no effect. If the ADC sequence mode is continuous or discontinuous, + * it will stop the ongoing conversion and meanwhile the further conversions. + * + * @param eInstance the ADC instance to stop + * @return ADC_StatusType whether ADC is stopped successfully + */ +ADC_StatusType ADC_Stop(const ADC_InstanceType eInstance); + +/** + * @brief Reset the ADC hardware + * + * @param eInstance the ADC instance to reset + */ +void ADC_Reset(const ADC_InstanceType eInstance); + +/** @}*/ + +/** @}*/ /* fc7xxx_driver_adc */ +#if defined(__cplusplus) +} +#endif +#endif diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_aontimer.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_aontimer.h new file mode 100644 index 0000000..56fc655 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_aontimer.h @@ -0,0 +1,140 @@ +/** + * @file fc7xxx_driver_aontimer.h + * @author Flagchip + * @brief FC7xxx aontimer driver type definition and API + * @version 0.1.0 + * @date 2024-01-10 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/******************************************************************************** +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2024-01-10 Flagchip0076 N/A First version for FC7240 +********************************************************************************/ + + +#ifndef DRIVER_INCLUDE_FC7XXX_DRIVER_AONTIMER_H_ +#define DRIVER_INCLUDE_FC7XXX_DRIVER_AONTIMER_H_ + +#include "HwA_aontimer.h" + +/** + * @addtogroup fc7xxx_driver_aontimer + * @{ + */ + +/** @brief Aontimer return type. */ +typedef enum +{ + AONTIMER_STATUS_SUCCESS = 0U, /**< Aontimer status is success.*/ + AONTIMER_STATUS_PARAM_INVALID = 1U, /**< Aontimer failed for param invalid.*/ + AONTIMER_STATUS_CLOCK_INVALID = 2U /**< Aontimer failed for colck invalid.*/ +} AONTIMER_StatusType; + +/** @brief Aontimer debug mode */ +typedef enum +{ + AONTIMER_DBG_COUNTER_STOP = 0x00U, /**< Aontimer is stop in debug mode.*/ + AONTIMER_DBG_COUNTER_RUNNING = 0x01U /**< Aontimer is running in debug mode.*/ +} AONTIMER_DebugType; + +/** @brief Aontimer mode. */ +typedef enum +{ + AONTIMER_COUNTER_MODE = 0, /**< In this mode ,the clock source is internal.*/ + AONTIMER_PULSE_MODE /**< In this mode ,the clock source is external(pin/trgsel).*/ +} AONTIMER_ModeType; + +/** @brief callback function type */ + +typedef void (*Aontimer_InterruptCallBackType)(void); + +typedef struct +{ + bool bIntEn; /**< whether to use interrupt */ + Aontimer_InterruptCallBackType pIsrNotify; /**< the notification function of interrupt */ +} AONTIMER_IntType; + +/** @brief Aontimer Initialization struct type */ +typedef struct +{ + AONTIMER_ModeType eMode; /**< enumeration of aontier mode */ + + AONTIMER_DebugType eDbgMode; /**< enumeration of aontier debug mode */ + + bool bBypassEn; /**< Whether to use prescaler in counter mode or use glitch filter in pulse mode, + if set input value is true ,then not use the prescaler or glitch filter.*/ + AONTIMER_PulseClkSrcType ePulseClkSrc; /**< clock source of pulse mode */ + AONTIMER_PulsePolarityType ePulsePol; /**< polarity of pulse mode */ + uint8_t u8PulseFilterWidth; /**< the width of glitch filter in pulse mode , the range of the input value is :1~15, + and the range of glitch filter is :2^1 ~ 2^15. */ + uint8_t u8Prescaler; /**< the width of prescaler in counter mode, the range of the input value is :0~15, + and the range of prescaler is :2^1 ~ 2^16. */ + AONTIMER_ClkSrcType eClkSrc; /**< clock source of counter mode */ + uint16_t u16StartValue; /**< start value of counter mode ,the range is : 0 ~ 65535 */ +} AONTIMER_InitType; + +/* global function */ +/** + * @brief Initialize aontimer instance + * + * @param pInitStruct Aontimer Initialize structure + */ +void AONTIMER_Init(const AONTIMER_InitType *const pInitStruct); + +/** + * @brief De-initialize aontimer instance + * + */ +void AONTIMER_Deinit(void); + +/** + * @brief Initialize aontimer interrupt functionality + * + * @param pIntStruct Aontimer interrupt structure + * @return Aontimer return type + * @note this function will disable timer + */ +AONTIMER_StatusType AONTIMER_InitInterrupt(const AONTIMER_IntType *const pIntStruct); + +/** + * @brief Enable AONTIMER interrupt + * @note this function will enable AONTIEMR timer. + */ +void AONTIMER_EnableInterrupt(void); + +/** + * @brief Disable AONTIMER interrupt + * @note this function will enable AONTIEMR timer. + * + */ +void AONTIMER_DisableInterrupt(void); + +/** + * @brief Start Aontimer + * + */ +void AONTIMER_StartTimer(void); + +/** + * @brief Stop Aontimer + * + */ +void AONTIMER_StopTimer(void); + +/** + * @brief Update value of aontimer counter + * + * @param u16StartValue input value, range : 0~65535 + */ +void AONTIMER_UpdateCounterValue(const uint16_t u16StartValue); + + +/** @}*/ /* fc7xxx_driver_aontimer */ + +#endif /* DRIVER_INCLUDE_FC7XXX_DRIVER_AONTIMER_H_ */ diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_cmp.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_cmp.h new file mode 100644 index 0000000..d41657c --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_cmp.h @@ -0,0 +1,295 @@ +/** + * @file fc7xxx_driver_cmp.h + * @author Flagchip + * @brief FC7xxx CMP driver type definition and API + * @version 0.1.0 + * @date 2024-01-15 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + */ +/******************************************************************************** +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2024-01-15 Flagchip0126 N/A First version for FC7240 +********************************************************************************/ +#ifndef _DRIVER_FC7XXX_DRIVER_CMP_H_ +#define _DRIVER_FC7XXX_DRIVER_CMP_H_ +#include "HwA_cmp.h" + + + +#if defined(__cplusplus) +extern "C" { +#endif + +/********* Local typedef ************/ + +/** + * @brief The CMP complete interrupt callback function prototype + * + */ +typedef void (*CMP_CompleteIntCallback)(void); + +/** + * @brief The instance index of the CMP Dac parts + */ +typedef struct +{ + bool bDacEn; /*!< CMP DAC enable/disable */ + uint8_t u8DacData; /*!< CMP DAC output voltage, output = Vin / 256 * (aDacData + 1) */ + CMP_DacEnableSrcType eDacEnsrc; /*!< CMP DAC enable selection(DCR,CCR0) */ + CMP_DacVinRefSelType eVinRefSel; /*!< CMP DAC high voltage reference (vrefh0,vrefh1) */ +} CMP_DacType; + +/** + * @brief The instance index of the CMP Mux parts + */ +typedef struct +{ + CMP_INSrcSelType eINPSel; /*!< CMP input positive select(DAC or analog mux) */ + CMP_INSrcSelType eINNSel; /*!< CMP input negative select(DAC or analog mux) */ + CMP_MuxSelType ePSelMux; /*!< CMP input positive mux select, this is ignored in channel scan mode */ + CMP_MuxSelType eNSelMux; /*!< CMP input negative mux select, this is ignored in channel scan mode */ + CMP_MuxSelType eChannelScanFixedChannel; /*!< CMP channel scan fixed channel select, this is ignored if DAC is enabled */ + CMP_PortSelType eChannelScanFixedPort; /*!< CMP channel scan fixed channel port select */ +} CMP_MuxType; + +/** + * @brief The instance index of the CMP Comparator parts + */ +typedef struct +{ + bool bStopModEn; /*!< CMP stop mode enable */ + bool bOutToPackagePinEn; /*!< CMP output to package pin enable */ + bool bWinSampleInvertEn; /*!< CMP window/sample signal invert enable */ + bool bEventCloseWinEn; /*!< CMP out event close window enable */ + bool bAnalogConfTransByp; /*!< CMP analog configuration transition bypass enable */ + uint16 u16AnalogConfTransBypCnt; /*!< Target count value for bypass function */ + uint8_t u8FilterPeriod; /*!< CMP set Filter Sample Period */ + CMP_ModSelType eModSel; /*!< CMP set function mode */ + CMP_InvertType eInvert; /*!< CMP output Invert or not(invert, non-invert) */ + CMP_OutSelectType eOutSelect; /*!< CMP output filter or not(CMPO = CMPOUT_FILTER/CMPOUT_WIN) */ + CMP_OutWinLevelType eOutWinLevel; /*!< CMP output when window close(hold, userdefine) */ + CMP_OutWinLevel_UserDefType eOutWin; /*!< CMP output under userdefine (0, 1) */ + CMP_EventType eEventSelect; /*!< CMP output event cause window close(rising edge, falling edge) */ + CMP_FilterCntType eFilterCnt; /*!< CMP filter count numbers(0,1,2,3,4) */ + CMP_SpeedModSelType eSpeedMod; /*!< CMP speed mode(low,high) */ + CMP_HystCtrlType eHystCrtl; /*!< CMP hysteresis internal control(0,1,2,3) */ +} CMP_ComparatorType; + +/** + * @brief Defines the comparator interrupt configuration + * + * @note This structure is used to configure CMP interrupt + * Implements : CMP_InterruptType + */ +typedef struct +{ + bool bRisingIntEn; /*!< Enable/disable rising interrupt */ + bool bFallingIntEn; /*!< Enable/disable falling interrupt */ + bool bChannelScanFlagIntEn; /*!< Enable/disable channel scan flag interrupt */ + CMP_CompleteIntCallback pInterrupterNotify; /*!< CMP complete interrupt callback */ +} CMP_InterruptType; + +/** + * @brief Defines the comparator dma configuration + * + * @note This structure is used to configure CMP dma + * Implements : CMP_DmaType + */ +typedef struct +{ + bool bRisingDmaEn; /*!< Enable/disable rising edge trigger dma */ + bool bFallingDmaEn; /*!< Enable/disable falling edge trigger dma */ +} CMP_DmaType; + +/** + * @brief Defines the comparator channel selected in channel scan mode + * + * @note This structure is used to configure a CMP channel that want to be enabled in channel scan sequence + * Implements : CMP_ChannelScanChannelCfgType + */ +typedef struct +{ + CMP_MuxSelType eChannel; /*!< Enabled channel */ + bool bPreSetState; /*!< Preset state for the given channel */ + bool bCurState; /*!< Current state for the given channel */ +} CMP_ChannelScanChannelCfgType; + +/** + * @brief Defines the comparator channel scan configuration + * + * @note This structure is used to configure CMP channel scan + * Implements : CMP_ChannelScanType + */ +typedef struct +{ + uint8_t u8ChannelScanInitModulus; /*! C/C++ Build -> Settings -> Tool Settings -> Target Processor -> Float ABI -> FP instructions(hard) -> FPU Type set to "fpv5-sp-d16" +2) configure FCIDE to enable FPU compiler support, "Properties" -> C/C++ Build -> Settings -> Tool Settings -> GNU Arm Cross C Compiler -> Preprocessor -> Defined symbols(-D) -> Add "__FPU_PRESENT=1" (without ") +3) and call FPU_Enable to enable FPU at the beginning of program. + +If want to use DSP, +1) configure FCIDE to enable FPU compiler support, Properties -> C/C++ Build -> Settings -> Tool Settings -> Target Processor -> Float ABI -> FP instructions(hard) +2) add MACRO "DRIVER_CM7_DSP_ENABLE" in FCIDE Properties -> C/C++ General -> Paths and Symbols -> Symbols -> GNU C and GNU C++ and Assembly +3) add Include Path to project Properties -> C/C++ General -> Paths and Symbols -> Includes -> GNU C and GNU C++ and Assembly: + ../../../../../Template/Device/CMSIS5_590/DSP/Include + ../../../../../Template/Device/CMSIS5_590/Core/Include + ../../../../../Template/Device/CMSIS5_590/DSP/PrivateInclude +4) and call FPU_Enable to enable FPU at the beginning of program. + @endverbatim + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-11 Flagchip054 N/A First version for FC7240 + ******************************************************************************** */ +#ifndef _DRIVER_FC4XXX_DRIVER_DSP_H_ +#define _DRIVER_FC4XXX_DRIVER_DSP_H_ + +#include "device_header.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#if defined(__cplusplus) +} +#endif +#endif /* _DRIVER_FC4XXX_DRIVER_DSP_H_ */ diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_eim.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_eim.h new file mode 100644 index 0000000..2978ac6 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_eim.h @@ -0,0 +1,87 @@ +/** + * @file fc7xxx_driver_eim.h + * @author Flagchip + * @brief FC7xxx EIM driver type definition and API + * @version 0.1.0 + * @date 2024-01-14 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/******************************************************************************** +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- ------------------- +* 0.1.0 2024-01-14 qxw0100 N/A First version for FC7240 +********************************************************************************/ +#ifndef _DRIVER_FC7XXX_DRIVER_EIM_H_ +#define _DRIVER_FC7XXX_DRIVER_EIM_H_ + +#include "HwA_eim.h" +#include "device_header.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** + * @addtogroup fc4xxx_driver_eim + * @{ + */ + + +/** + * @brief Initialize EIM function + * + * @param pEimInitCfg Initialization structure of EIM + * @return return 0: initialize successful. 1: invalid parameter + */ +EIM_RetType EIM_Init(const EIM_InitType *pEimInitCfg); + +/** + * @brief Initialize EIM function + * + * @param eEimChannel channel want to set + * @param eDwpType Cpu to use + * @param bLockStatus Lock the cpu control settings + * @return Set operation success/failed + */ +EIM_RetType EIM_SetDwpMode(const EIM_ChannelType eEimChannel, const EIM_DWPType eDwpType, bool bLockStatus); + +/** + * @brief Deinin EIM function + * + */ +void Eim_Deinit(void); + +/** + * @brief Enable CPU lockstep monitor + * + * @param eEimCpuType EIM_CPU0_LOCKSTEP or EIM_CPU1_LOCKSTEP + * @param eMonitorType EIM_MONITOR0 or EIM_MONITOR1 + */ +void EIM_CpuLockStepMonitorSet_MonSet(const EIM_CPU_ChnType eEimCpuType,const EIM_MONType eMonitorType); + +/** + * @brief Clear CPU lockstep monitor + * + * @param eEimCpuType EIM_CPU0_LOCKSTEP or EIM_CPU1_LOCKSTEP + * @param eMonitorType EIM_MONITOR0 or EIM_MONITOR1 + */ +void EIM_CpuLockStepMonitorSet_MonClr(const EIM_CPU_ChnType eEimCpuType,const EIM_MONType eMonitorType); + +/** + * @brief Clean CPU lockstep monitor bit + * + * @param eEimCpuType EIM_CPU0_LOCKSTEP or EIM_CPU1_LOCKSTEP + * @param eMonitorType EIM_MONITOR0 or EIM_MONITOR1 + */ +void EIM_CpuLockStepMonitorClr(const EIM_CPU_ChnType eEimCpuType, const EIM_MONType eMonitorType); + +/** @} */ /* fc7xxx_driver_eim */ + +#if defined(__cplusplus) +} +#endif +#endif /* _DRIVER_FC4XXX_DRIVER_EIM_H_ */ diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_erm.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_erm.h new file mode 100644 index 0000000..2b74128 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_erm.h @@ -0,0 +1,107 @@ +/** + * @file fc7xxx_driver_erm.h + * @author Flagchip + * @brief FC7xxx ERM driver type definition and API + * @version 0.1.0 + * @date 2024-01-14 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/******************************************************************************** +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2024-01-14 qxw0100 N/A First version for FC7240 +********************************************************************************/ +#ifndef _DRIVER_FC7XXX_DRIVER_ERM_H_ +#define _DRIVER_FC7XXX_DRIVER_ERM_H_ + +#include "HwA_erm.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/* @addtogroup fc7xxx_driver_erm + * @{ + */ + +typedef enum +{ + ERM_STATUS_SUCCESS = 0U, /**< ERM status success */ + ERM_STATUS_PARAM_INVALID = 1U /**< ERM status parameter invalid */ +} ERM_RetType; + +/** @brief Erm interrupt notification type */ +typedef void (*ERM_InterruptCallBackType)(void); + +/** + * @brief Structure to configure ERM Init type + * + */ +typedef struct +{ + ERM_ChannelType eChannel; /*!< ERM enable memory No, No 0-31 */ + ERM_InterruptType eInt; /*!< ERM Interrupt type */ + uint8 u8ErmEnable; /*!< ERM enable Interrupt */ + ERM_InterruptCallBackType pIsrNotify; /**< Erm interrupt notification function pointer */ +} ERM_MemorytInitType; +/** + * @brief Initialize ERM function + * + * @param pErmInt_cfg Initialization structure of ERM + * @return return 0: initialize successful. 1: invalid parameter + */ + +ERM_RetType Erm_Init(const ERM_MemorytInitType *pErmInt_cfg); + +/** + * @brief De-initialize ERM function + * Restore the ERM instance to its reset state + */ +void Erm_DeInit(void); +/** + * @brief ERM Read EARn address. + * @param eChannel The channel type + * @return u32Address The error address + */ +//uint32_t ERM_ReadAddress(ERM_channelType eChannel); + +/** + * @brief ERM Clear SRn register. + * + * This function Clear ERM SR0 register. + */ +void ERM_ClearSRnRegister(void); + +/** + * @brief ERM read SRn register. + * + * This function Clear ERM SR0 register. + * @param u8Index the SRn channel + */ +uint32_t ERM_ReadSRnVal(uint8_t u8Index); + +/** + * @brief ERM clear CRn register. + * + * This function Clear ERM CRn register. + * @param u8Index of the CRn channel + */ +void ERM_ClearCRnVal(uint8_t u8Index); + +/** + * @brief ERM clear SRn register. + * + * This function Clear ERM SR0 register. + * @param u8Index the SRn channel + */ +uint32_t ERM_ClearSRnVal(uint8_t u8Index); +/** @} */ /* fc7xxx_driver_erm */ + +#if defined(__cplusplus) +} +#endif +#endif /* _DRIVER_FC4XXX_DRIVER_ERM_H_ */ diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_fciic.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_fciic.h new file mode 100644 index 0000000..6915170 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_fciic.h @@ -0,0 +1,209 @@ +/** + * @file fc7xxx_driver_fciic.h + * @author Flagchip + * @brief FC7xxx FCIIC driver type definition and API + * @version 0.2.0 + * @date 2022-12-05 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + */ + +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2022/12/31 qxw0052 N/A First version for FC7300 + * 0.2.0 2023/02/14 qxw0052 N/A Fix MISRA issues + *********************************************************************************/ + +#ifndef _DRIVER_FC7XXX_DRIVER_FCIIC_H_ +#define _DRIVER_FC7XXX_DRIVER_FCIIC_H_ + +#include "HwA_fciic.h" + +/** + * @addtogroup fc7xxx_driver_iic + * @{ + */ + +/** + * \brief IIC initial data define + * + */ +typedef struct +{ + uint32_t u32ClkSrcHz; /**< module clock hz */ + uint8_t bMasterMode; /**< bMasterMode=1 master mode */ + uint8_t u8SlaveAddr; /**< if bMasterMode=0, this is used, and address format is 7bits , not ended with R/W bit */ + uint8_t bTxFifoWMrk; /**< Tx FIFO Water Mark, FIFO always on, transmit FIFO is equal or less than TXWATER, set TDF */ + uint8_t bRxFifoWMrk; /**< Tx FIFO Water Mark, FIFO always on, receive FIFO is greater than RXWATER, set RDF */ + uint8_t bEnDma; /**< Enable DMA) */ + uint32_t u32Frequency; /**< normal frequency, only used in master mode */ + +} FCIIC_InitType; + + + +/** + * \brief IIC transmit data define + * + */ +typedef struct +{ + FCIIC_TX_CMDType eCmd; /**< command type */ + uint8_t u8Data; /**< 8bit data */ +} FCIIC_TxDataType; + + +/** + * \brief IIC receive data define + * + */ +typedef struct +{ + uint8_t u8Data; /**< 8bit data */ +} FCIIC_RxDataType; + + +/** Error call back function type */ +typedef void (*FCIIC_ErrorInterrupt_CallBackType)(uint8_t u8IicIndex, uint8_t bMaster, uint32_t u32Error); + +/** Receive call back function type */ +typedef void (*FCIIC_RxInterrupt_CallBackType)(uint8_t u8IicIndex, FCIIC_RxDataType *pRxCfg); + +/** + * \brief IIC interrupt callback setting + * + */ +typedef struct +{ + uint8_t bEnErrorInterrupt; /**< enable error interrupt */ + FCIIC_ErrorInterrupt_CallBackType pErrorNotify; /**< error interrupt callback function address */ + uint8_t bEnRxInterrupt; /**< enable receive interrupt */ + FCIIC_RxInterrupt_CallBackType pRxNotify; /**< receive interrupt callback function address */ + +} FCIIC_InterruptType; + + +/** + * \brief This Function is used to initial IIC instance + * + * \param u8IicIndex Iic Index, 0,1 + * \param pInitCfg is the structure address of IIC initial configuration parameters, and it contains IIC instance + * \return 0 is ok, others are not ok + */ +uint8_t FCIIC_Init(uint8_t u8IicIndex, FCIIC_InitType *pInitCfg); + +/** + * \brief This Function is used to de-initial IIC instance + * + * \param u8IicIndex Iic Index, 0,1 + * \param pInitCfg is the structure address of IIC initial configuration parameters, bMaster should be set + * \return 0 is ok, others are not ok + */ +uint8_t FCIIC_DeInit(uint8_t u8IicIndex, FCIIC_InitType *pInitCfg); + +/** + * \brief This Function is used to configure IIC master interrupt + * + * \param u8IicIndex Iic Index, 0,1 + * \param pIntCfg contains IIC instance and interrupt callback functions + * \return 0 is ok, others are not ok + */ +uint8_t FCIIC_Master_SetInterrupt(uint8_t u8IicIndex, FCIIC_InterruptType *pIntCfg); + +/** + * \brief This Function is used to transmit data in master mode + * + * \param u8IicIndex Iic Index, 0,1 + * \param pTxData contains IIC instance and buffer address + * \return 0 is ok, others are not ok + */ +uint8_t FCIIC_Master_Transmit(uint8_t u8IicIndex, FCIIC_TxDataType *pTxData); + +/** + * \brief This Function is used to get master status + * + * \param u8IicIndex Iic Index, 0,1 + * \param eStatus is status type enumeration + * \return 0 is ok, others are not ok + */ +uint8_t FCIIC_Master_GetStatus(uint8_t u8IicIndex, FCIIC_MasterStatusType eStatus); + +/** + * \brief This Function is used to receive data when polling (not used when rx interrupt enabled) in master mode + * + * \param u8IicIndex Iic Index, 0,1 + * \param pRxData contains IIC instance + * \return 0 is ok, others are not ok + */ +uint8_t FCIIC_Master_Receive(uint8_t u8IicIndex, FCIIC_RxDataType *pRxData); + +/** + * \brief This Function is used to get master error value + * + * \param u8IicIndex Iic Index, 0,1 + * \return error value + */ +uint32_t FCIIC_Master_GetError(uint8_t u8IicIndex); + +/** + * \brief This Function is used to clear master error value + * + * \param u8IicIndex Iic Index, 0,1 + */ +void FCIIC_Master_ClrError(uint8_t u8IicIndex); + +/** + * \brief This Function is used to configure IIC slave interrupt + * + * \param u8IicIndex Iic Index, 0,1 + * \param pIntCfg contains IIC instance and interrupt callback functions + * \return 0 is ok, others are not ok + */ +uint8_t FCIIC_Slave_SetInterrupt(uint8_t u8IicIndex, FCIIC_InterruptType *pIntCfg); + +/** + * \brief This Function is used to transmit data in slave mode + * + * \param u8IicIndex Iic Index, 0,1 + * \param pTxData contains IIC instance and buffer address + * \return 0 is ok, others are not ok + */ +uint8_t FCIIC_Slave_Transmit(uint8_t u8IicIndex, FCIIC_TxDataType *pTxData); + +/** + * \brief This Function is used to receive data when polling (not used when rx interrupt enabled) in slave mode + * + * \param u8IicIndex Iic Index, 0,1 + * \param pRxData contains IIC instance and buffer address + * \return 0 is ok, others are not ok + */ +uint8_t FCIIC_Slave_Receive(uint8_t u8IicIndex, FCIIC_RxDataType *pRxData); + +/** + * \brief This Function is used to get slave error value + * + * \param u8IicIndex Iic Index, 0,1 + * \return error value + */ +uint32_t FCIIC_Slave_GetError(uint8_t u8IicIndex); + +/** + * \brief This Function is used to clear slave error value + * + * \param u8IicIndex Iic Index, 0,1 + */ +void FCIIC_Slave_ClrError(uint8_t u8IicIndex); + + +#ifdef FCIIC_MASTER_STOP + uint8_t FCIIC_Master_Stop(uint8_t u8IicIndex); +#endif + + +/** @}*/ + +#endif diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_fcpit.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_fcpit.h new file mode 100644 index 0000000..6eb08e9 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_fcpit.h @@ -0,0 +1,179 @@ +/** + * @file fc7xxx_driver_fcpit.h + * @author Flagchip + * @brief FC7xxx FCPIT driver type definition and API + * @version 0.1.0 + * @date 2024-01-10 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/******************************************************************************** +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2024-01-10 Flagchip0076 N/A First version for FC7240 +********************************************************************************/ + +#ifndef _DRIVER_FC7XXX_DRIVER_FCPIT_H_ +#define _DRIVER_FC7XXX_DRIVER_FCPIT_H_ +#include "HwA_fcpit.h" + +/** + * @addtogroup fc7xxx_driver_fcpit + * @{ + */ + +/** @brief Fcpit return type. */ +typedef enum +{ + FCPIT_STATUS_SUCCESS = 0U, + FCPIT_STATUS_PARAM_INVALID = 1U, + FCPIT_STATUS_FUNCTION_ERROR = 2U +} FCPIT_StatusType; + +/** @brief Fcpit trigger source */ +typedef enum +{ + FCPIT_TRIGGER_INTERNAL_0 = 0, + FCPIT_TRIGGER_INTERNAL_1, + FCPIT_TRIGGER_INTERNAL_2, + FCPIT_TRIGGER_INTERNAL_3, + FCPIT_TRIGGER_EXTERNAL +} FCPIT_TriggerSelectType; + +/** @brief callback function type */ +typedef void (*FCPIT_InterruptCallBackType)(void); + +typedef struct +{ + FCPIT_ChannelType eFcpitChannel; /**< Fcpit channel number */ + FCPIT_TriggerSelectType eTriggerSel; /**< trigger source */ + bool bStartOnTrigger; /**< Fcpit timer start when triggered */ + bool bStopOnInterrupt; /**< Fcpit timer stop on interrupt */ + bool bReloadOnTrigger; /**< Fcpit timer reload when triggered */ +} FCPIT_TrggerType; + +/** @brief Fcpit interrupt structure */ +typedef struct +{ + FCPIT_ChannelType eFcpitChannel; /**< Fcpit channel number */ + bool bChannelIsrEn; /**< whether to use interrupt */ + FCPIT_InterruptCallBackType pIsrNotify; /**< interrupt notification function */ +} FCPIT_IntType; + +/** @brief Fcpit initialization type */ +typedef struct +{ + FCPIT_ChannelType eFcpitChannel; /**< Fcpit channel number */ + FCPIT_TimerModeType eMode; /**< Fcpit counter mode */ + bool bChainModeEn; /**< whether to use chain mode, if use this mode, channel must not be the channel 0 */ + uint32_t u32TimerValue; /**< timer compare value, the range of value is related to the counter mode */ + + bool bDebugEn; /**< whether to use debug mode ,if enable this mode, the counter will stop when debugging. */ + bool bLowPowerModeEn; /**< Configure the timer channels to continue running or stop when the device enters the LPM mode */ +} FCPIT_InitType; + +/** @brief FCPIT instance number */ +typedef enum +{ + FCPIT_0 = 0U, +} FCPIT_InstanceType; + + +/* global functions */ +/** + * @brief Initialize Fcpit instance. + * @param eFcpit instance + * @param pInitStruct Fcpit initialization structure + * @return Fcpit return type + */ +FCPIT_StatusType FCPIT_Init(const FCPIT_InstanceType eFcpit, const FCPIT_InitType *const pInitStruct); + +/** + * @brief Initialize Fcpit trigger configuration + * @param eFcpit instance + * @param pTrgStruct Fcpit trigger structure + * @return Fcpit return type + */ +FCPIT_StatusType FCPIT_InitTrigger(const FCPIT_InstanceType eFcpit, const FCPIT_TrggerType *const pTrgStruct); + +/** + * @brief De-initialize Fcpit instance. + * @param eFcpit instance + */ +FCPIT_StatusType FCPIT_Deinit(const FCPIT_InstanceType eFcpit); + +/** + * @brief Initialize Fcpit interrupt functionality + * @param eFcpit instance + * @param pTrgStruct Fcpit interrupt structure + * @return Fcpit return type + * @note this function will stop timer + */ +FCPIT_StatusType FCPIT_InitInterrupt(const FCPIT_InstanceType eFcpit, const FCPIT_IntType *const pIntStruct); + +/** + * @brief Enable Fcpit interrupt + * @param eFcpit instance + * @param pIntStruct Fcpit interrupt structure + * @return Fcpit return type + */ +FCPIT_StatusType FCPIT_EnableInterrupt(const FCPIT_InstanceType eFcpit, const FCPIT_ChannelType eChannel); + +/** + * @brief Disable Fcpit interrupt + * @param eFcpit instance + * @param eChannel Fcpit channel + * @return Fcpit return type + */ +FCPIT_StatusType FCPIT_DisableInterrupt(const FCPIT_InstanceType eFcpit, const FCPIT_ChannelType eChannel); + +/** + * @brief Fcpit start timer + * @param eFcpit instance + * @param eChannel Fcpit channel + * @return Fcpit return type + */ +FCPIT_StatusType FCPIT_Start(const FCPIT_InstanceType eFcpit, const FCPIT_ChannelType eChannel); + +/** + * @brief Fcpit stop + * @param eFcpit instance + * @param eChannel Fcpit channel + * @return Fcpit return type + */ +FCPIT_StatusType FCPIT_Stop(const FCPIT_InstanceType eFcpit, const FCPIT_ChannelType eChannel); + +/** + * @brief Update Fcpit channel value + * @param eFcpit instance + * @param eChannel Fcpit channel + * @param u32ChannelValue in/Out value + * @return Fcpit return type + */ +FCPIT_StatusType FCPIT_UpdateChannelValue(const FCPIT_InstanceType eFcpit, const FCPIT_ChannelType eChannel, const uint32_t u32ChannelValue); + +/** + * @brief read Fcpit channel time stamps. + * @param eFcpit instance + * @param eChannel Fcpit channel + * @param *u32timeStampValue channel value + * @return Fcpit return type + */ + +FCPIT_StatusType FCPIT_ReadTimstamp(const FCPIT_InstanceType eFcpit, const FCPIT_ChannelType eChannel,uint32_t *u32timeStampValue); + +/** + * @brief Immediately update Fcpit channel value + * @param eFcpit instance + * @param eChannel Fcpit channel + * @param u32ChannelValue in/Out value + * @return Fcpit return type + */ +FCPIT_StatusType FCPIT_ImmediateUpdateChannelValue(const FCPIT_InstanceType eFcpit, const FCPIT_ChannelType eChannel, const uint32_t u32ChannelValue); + +/** @}*/ /* fc7xxx_driver_fcpit */ +#endif diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_fcsmu.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_fcsmu.h new file mode 100644 index 0000000..1b3d75a --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_fcsmu.h @@ -0,0 +1,251 @@ +/** + * @file fc7xxx_driver_fcsmu.h + * @author Flagchip + * @brief FC7xxx FCSMU driver type definition and API + * @version 0.1.0 + * @date 2024-01-14 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-14 qxw0100 N/A First version for FC7240 + ******************************************************************************** */ +#ifndef _DRIVER_FC7XXX_DRIVER_FCSMU_H_ +#define _DRIVER_FC7XXX_DRIVER_FCSMU_H_ +#include "device_header.h" +#include "HwA_fcsmu.h" +/** + * @addtogroup fc7xxx_driver_fcsmu + * @{ +. */ + +typedef enum +{ + FCSMU_INSTANCE_0 = 0U, /*!< FCSMU instance 0 is selected. */ +} FCSMU_InstanceType; + +typedef enum +{ + FCSMU_STATUS_SUCCESS = 0U, /*!< FCSMU operation is succeed. */ + FCSMU_STATUS_ERROR = 1U /*!< FCSMU operation is failed. */ +} FCSMU_StatusType; + +typedef enum +{ + FCSMU_STATE_NORMAL = 0U, /*!< FCSMU state normal */ + FCSMU_STATE_CONGIG = 1U, /*!< FCSMU state config */ + FCSMU_STATE_WARN = 2U, /*!< FCSMU state warn */ + FCSMU_STATE_FAULT = 3U /*!< FCSMU state fault */ +} FCSMU_StateType; + +typedef enum +{ + FCSMU_OP_STATE_IDLE = 0U, /*!< FCSMU operation status idle */ + FCSMU_OP_STATE_BUSY = 1U, /*!< FCSMU operation status busy */ + FCSMU_OP_STATE_FAILED = 2U, /*!< FCSMU operation status failed */ + FCSMU_OP_STATE_SUCCESSFUL = 3U /*!< FCSMU operation status successful */ +} FCSMU_OperationStatusType; + +typedef enum +{ + FCSMU_CRC_SW_MODE = 0U, /*!< FCSMU crc software mode. */ + FCSMU_CRC_TRIGGER_MODE = 1U /*!< FCSMU crc trigger mode. */ +} FCSMU_CrcModeType; + +typedef enum +{ + FCSMU_SOUT_CTRL_BY_FSM = 0U, /*!< SOUT is controlled by the FSM. */ + FCSMU_SOUT_CTRL_KEEP_LOW = 1U, /*!< SOUT keeps low. */ + FCSMU_SOUT_CTRL_BY_FSM2 = 2U, /*!< SOUT is controlled by the FSM. */ + FCSMU_SOUT_CTRL_KEEP_HIGH_THEN_FSM = 3U /*!< SOUT keeps high until a fault occures on a channel, then controlled by FSM. */ +} FCSMU_SoutControlType; + +typedef enum +{ + FCSMU_SOUT_DEFAUT_POLARITY = 0U, /*!< Default polarity. */ + FCSMU_SOUT_SWITCH_POLARITY = 1U /*!< Switch polarity. */ +} FCSMU_SoutPolarityType; + +typedef enum +{ + FCSMU_SOUT_PROTOCOL_DUAL_RAIL = 0U, + FCSMU_SOUT_PROTOCOL_TIME_SWITCH = 1U, + FCSMU_SOUT_PROTOCOL_BISTABLE = 2U, + FCSMU_SOUT_PROTOCOL_FAULT_TOGGLE = 3U, + FCSMU_SOUT_PROTOCOL_TIME_DUAL_RAIL = 4U, + FCSMU_SOUT_PROTOCOL_DIAG0 = 5U, + FCSMU_SOUT_PROTOCOL_DIAG1 = 6U, + FCSMU_SOUT_PROTOCOL_DIAG2 = 7U, +} FCSMU_SoutProtocolType; + +typedef enum +{ + FCSMU_WARNING_IRQ = 0U, + FCSMU_FAULT_IRQ = 1U, + FCSMU_CFG_TIMEOUT = 2U +} FCSMU_IQRType; + +typedef enum +{ + FCSMU_FAULT_CHANNEL_NONE = 0x0U, + FCSMU_FAULT_CHANNEL_TEMP_ERROR = 0x1U, /*!< Event from temperature sensor. */ + FCSMU_FAULT_CHANNEL_PMC_ERROR = 0x2U, /*!< Voltage out of range indication from PMC. */ + FCSMU_FAULT_CHANNEL_NVR_ERROR = 0x4U, /*!< NVR load error/System abnormal alarm signal. */ + FCSMU_FAULT_CHANNEL_STCU_BIST_ERROR = 0x8U, /*!< STCU MBIST or LBIST fail. */ + FCSMU_FAULT_CHANNEL_STCU_LS0_ERROR = 0x10U, /*!< Lockstep compare fault. */ + FCSMU_FAULT_CHANNEL_SYSTEM_CPU0_ERROR = 0x40U, /*!< System RAM CPU0 access error. */ + FCSMU_FAULT_CHANNEL_SYSTEM_NON_CPU_ERROR = 0x200U, /*!< System RAM None CPU access error. */ + FCSMU_FAULT_CHANNEL_SCM_CPU0_ERROR = 0x400U, /*!< Matrix Access Monitor ECC check CPU0 error. */ + FCSMU_FAULT_CHANNEL_SCM_NON_CPU_ERROR = 0x2000U, /*!< Matrix Access Monitor ECC check non CPU error. */ + FCSMU_FAULT_CHANNEL_CPU0_ECC_ERROR = 0x4000U, /*!< Including ITCM/DTCM/ICACHE/DCACHE. */ + FCSMU_FAULT_CHANNEL_CMU4_FAIL_ERROR = 0x80000U, /*!< CMU4 failure interrupt. */ + FCSMU_FAULT_CHANNEL_CMU_FAIL_ERROR = 0x100000U, /*!< CMU1/2 failure interrupt. */ + FCSMU_FAULT_CHANNEL_FLASH_ECC_ERROR = 0x200000U, /*!< Flash ECC error. */ + FCSMU_FAULT_CHANNEL_SCG_PLL_FOSC_ERROR = 0x400000U, /*!< PLL/FOSC loss of clock. */ + FCSMU_FAULT_CHANNEL_DMA0_ERROR = 0x800000U, /*!< DM0 AHB Error/LS Error/CFG RAM Error. */ + FCSMU_FAULT_CHANNEL_INTM0_ERROR = 0x2000000U, /*!< Interrupt Monitor error. */ + FCSMU_FAULT_CHANNEL_FMC_ERROR = 0x10000000U, /*!< FMC ECC error. */ + FCSMU_FAULT_CHANNEL_SCG_SCM_CRC_ERROR = 0x20000000U, /*!< SCG and SCM etc. CRC check error. */ + FCSMU_FAULT_CHANNEL_MAM_WDG_ERROR = 0x80000000U, /*!< MAM master access time out error. */ +} FCSMU_ChannelAssignmentType; + +/** + * @brief FCSMU Channel ISR callback function prototype + * + */ +typedef void (*FCSMU_ISRCallbackType)(FCSMU_IQRType eIrqType, uint32_t u32IrqChannel); + +typedef struct +{ + bool bEnable; /*!< Enable or disable status output. */ + bool eFastMode; /*!< Enable or disable fast mode. */ + bool bDivex; /*!< SOUT Divider Extend Control. */ + FCSMU_SoutControlType eSoutCtrl; /*!< Configure Sout Control. */ + FCSMU_SoutPolarityType ePolarity; /*!< Status output polarity. */ + FCSMU_SoutProtocolType eProtocal; /*!< Status output protocal. */ + uint32_t u32Delaytimer; /*!< Configure the safe mode request delay in cycles of CLKSAFE. */ + uint32_t u32Divder; /*!< Configure the status output divider ratio. + bDevex = 0, SOUT_freq = CLKSAFE_freq/((SOUT_DIV+1)*2*256) + bDevex = 1, SOUT_freq = CLKSAFE_freq/((SOUT_DIV+1)*2*64) + */ + uint32_t u32SoutChannel; /*!< Configure the status output channel. */ +} FCSMU_StatusOutputConfigType; + +typedef struct +{ + uint32_t u32WarnTo; /*!< FCSMU warning timeoout value. */ + uint32_t u32WarnChannel; /*!< FCSMU warning channel. */ + uint32_t u32FaultChannel; /*!< FCSMU fault channel. */ + uint32_t u32WarnInterruptChannel; /*!< FCSMU warning interrupt channel. */ + uint32_t u32FaultInterruptChannel; /*!< FCSMU fault interrupt channel. */ + uint32_t u32FaultResetChannel; /*!< FCSMU fault reset channel. */ + uint32_t u32SoftwareClearedChannel; /*!< FCSMU fault is Cleard by software. */ + FCSMU_ISRCallbackType pISRCallback; /*!< ISR callback. */ +} FCSMU_InitCfgType; + +/** + * @brief Init the FCSMU. + * + * @param pInitConfig FCSMU initial configuration. + */ +FCSMU_StatusType FCSMU_init(const FCSMU_InitCfgType *pInitConfig); + +/** + * @brief Config the FCSMU status output. + * + * @param pInitConfig FCSMU status output configuration. + */ +FCSMU_StatusType FCSMU_ConfigStatusOutput(FCSMU_StatusOutputConfigType *pInitConfig); + +/** + * @brief Generate the CRC. + * + */ +void FCSMU_CrcGen(void); + +/** + * @brief Query CRC busy status. + * + * @return FCSMU_CrcModeType CRC status. + */ +bool FCSMU_IsCrcBusy(void); + +/** + * @brief Configure the FCSMU CRC. + * + * @param eMode Crc mode. + * @return FCSMU_StatusType Status of configuration. + */ +FCSMU_StatusType FCSMU_CrcConfig(FCSMU_CrcModeType eMode); + +/** + * @brief Clear the falut flag. + * + * @param u32FaultChannel Channel flag to be cleared. + * @return FCSMU_StatusType Status of clear. + */ +FCSMU_StatusType FCSMU_ClearFaultFlag(uint32_t u32FaultChannel); + +/** + * @brief Transform state from configuration to normal. + * + * @return FCSMU_StatusType Status of Transformation. + */ +FCSMU_StatusType FCSMU_TransStateCTN(void); + +/** + * @brief Transform state from normal to configuration. + * + * @return FCSMU_StatusType Status of Transformation. + */ +FCSMU_StatusType FCSMU_TransStateNTC(void); + +/** + * @brief Inject the fault tp fcsmu. + * + * @param u32ChannelIndex channel to be injected. + */ +void FCSMU_InjectionFault(uint32_t u32ChannelIndex); + +/** + * @brief Get the fault channels fcsmu. + * + * @return Fault channels. + */ +uint32_t FCSMU_GetFaultChannel(void); + +/** + * @brief Get the interrupt state of fcsmu. + * + * @return interrupt state. + */ +uint32_t FCSMU_GetIrqState(void); + +/** + * @brief Get the NTF flags of fcsmu. + * + * @return NTF flags. + */ +uint32_t FCSMU_GetNtfFlag(void); + +/** + * @brief Get the WTF flags of fcsmu. + * + * @return WTF flags. + */ +uint32_t FCSMU_GetWtfFlag(void); + +/** + * @brief Get the NTW flags of fcsmu. + * + * @return NTW flags. + */ +uint32_t FCSMU_GetNtwFlag(void); + +/** @}*/ /* fc7xxx_driver_fcsmu. */ +#endif diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_fcspi.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_fcspi.h new file mode 100644 index 0000000..d6c4513 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_fcspi.h @@ -0,0 +1,620 @@ +/** + * @file fc7xxx_driver_fcspi.h + * @author Flagchip + * @brief FC7xxx FCSPI driver type definition and API + * @version 0.1.0 + * @date 2024-1-12 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + */ +/******************************************************************************** +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2024/01/12 Flagchip071 N/A First version for FC7240 +********************************************************************************/ +#ifndef _DRIVER_FC7XXX_DRIVER_FCSPI_H_ +#define _DRIVER_FC7XXX_DRIVER_FCSPI_H_ + +#include "device_header.h" +#include "HwA_fcspi.h" +#include "fc7xxx_driver_dma.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** + * @addtogroup fc4xxx_driver_fcspi + * @{ + */ + +/** + * @brief Status returned by FCSpi APIs + * + */ +typedef enum { + FCSPI_STATUS_SUCCESS = 0, /*!< API execute successfully */ + FCSPI_STATUS_INSTANCE_ERROR, /*!< FCSpi instance index parameter error */ + FCSPI_STATUS_PARAM_ERR, /*!< parameter error */ + FCSPI_STATUS_ERROR, /*!< some error occur in API */ + FCSPI_STATUS_NO_DATA, /*!< user want to transfer nothing */ + FCSPI_STATUS_BUSY, /*!< FCSpi hardware is busy, not available */ + FCSPI_STATUS_SYNC_TIMEOUT, /*!< FCSpi synchronous transfer timeout */ + FCSPI_STATUS_TRANSFER_FAIL, /*!< FCSpi transfer fail */ + + FCSPI_STATUS_TRIGGER_OK, /*!< FCSpi user trigger successfully */ + FCSPI_STATUS_TRIGGER_ABORT_TX_FAIL, /*!< FCSpi user trigger fail due to send underrun */ + FCSPI_STATUS_TRIGGER_ABORT_RX_FAIL, /*!< FCSpi user trigger fail due to receive overflow */ + FCSPI_STATUS_TRIGGER_FINISH /*!< FCSpi user trigger finish, all data already send */ +} FCSPI_StatusType; + +/** + * @name Type definition for FCSpi master/slave mode + * + */ +/**@{*/ + +/** + * @brief FCSpi hardware instances + * + * FCSpi consist of multiple hardware instances, for example, FCSPI0, FCSPI1... + * Just as the enumeration type "FCSPI_InstanceType" definition shows. + * We use variables of this type to indicate which hardware instance to use. + */ +typedef enum { + FCSPI_0 = 0, + FCSPI_1 = 1, + FCSPI_2 = 2, + FCSPI_3 = 3, + FCSPI_4 = 4, + FCSPI_5 = 5, +} FCSPI_InstanceType; + + +/** + * @brief PCS(Peripheral Chip Select) pin select + * + * FCSPI has four PCS lines, in our driver code, + * we use FCSPI_PCS_0/FCSPI_PCS_1/FCSPI_PCS_2/FCSPI_PCS_3 to present them. + * Like the above, we use enumeration type "FCSPI_PCSType" to indicate + * which PCS to connect to the external device, + * "PCS" is short for Peripheral Chip Select, + * which usually use low level voltage to select the external chip to communicate. + */ +typedef enum { + FCSPI_PCS_0 = 0U, + FCSPI_PCS_1 = 1U, + FCSPI_PCS_2 = 2U, + FCSPI_PCS_3 = 3U +} FCSPI_PCSType; + +/** + * @brief Valid PCS pin voltage polarity + * + * The external device determines the voltage polarity (low or high) of PCS to enable it. + * So, FCSpi use enumeration type "FCSPI_PcsPolarityType" to indicate + * the polarity the PCS output when select the external device + */ +typedef enum { + FCSPI_PCS_POL_ACTIVE_HIGH = 1, /*!< pcs use high level to select external device */ + FCSPI_PCS_POL_ACTIVE_LOW = 0 /*!< pcs use low level to select external device */ +} FCSPI_PcsPolarityType; + +/** + * @brief SCK(serial clock) active phase + * + * Just as the SPI bus specification says, clock polarity (CPOL) and clock phase (CPHA) determine the sample point. + * FCSpi use enumeration type "FCSPI_SckPolarityType" to present CPOL configuration. + */ +typedef enum { + FCSPI_SCK_ACTIVE_HIGH = 0, /*!< sck is high level when active (idles low). */ + FCSPI_SCK_ACTIVE_LOW = 1 /*!< sck is low level when active (idles high). */ +} FCSPI_SckPolarityType; + +/** + * @brief SCK(serial clock) sample edge + * + * Just as the SPI bus specification says, + * clock polarity (CPOL) and clock phase (CPHA) determine the sample point. + * FCSpi use enumeration type "FCSPI_SckSamplePhaseType" to present CPHA configuration. + */ +typedef enum { + FCSPI_SCK_SAMPLE_FIRST_EDGE = 0, /*!< sample on first edge of sck active polarity, change on second */ + FCSPI_SCK_SAMPLE_SECOND_EDGE = 1 /*!< changed on first edge of sck active polarity, sample on second */ +} FCSPI_SckSamplePhaseType; + +/** + * @brief The order of rx/tx handles bit + * + * When send or receive data, the MOSI and MISO handle only one bit at a time, + * FCSpi map the bit data order according to the specific configuration. + * FCSpi driver provides the enumeration type "FCSPI_BitFirstOrderType" to indicate the order. + */ +typedef enum { + FCSPI_MSB_FIRST = 0, /*!< most significant bit first handle, from msb to lsb */ + FCSPI_LSB_FIRST = 1 /*!< least significant bit first handle, from lsb to msb */ +} FCSPI_BitFirstOrderType; + + +/** + * @brief Transfer method between memory and FCSpi's registers + * + * FCSpi support transferring data by ISR, DMA, or user poll. + * + * If use ISR method, in interrupt handler function, + * the driver will write data to register "FCSPI_TX_DATA" to push it into Tx FIFO + * and read the register "FCSPI_RX_DATA" to pop data from Rx FIFO. + * When finish, the hardware will create an interrupt to notify the end. + * + * If use DMA, the DMA channel and priority should also be configured. + * After configuring these, driver user doesn't need to take care of the detail of transferring. + * Just send data or send & receive at same time. When finish, the hardware will create an interrupt to notify the end. + * + * If use User Poll mode, driver user should call + * "FCSPI_SyncTransfer" API to move the data until it return error or finished. + * In this mode, the interrupt in driver is disabled. + */ +typedef enum { + FCSPI_TRANSFER_TRIGGER_SRC_ISR = 0, /*!< software(interrupt function) move data between register and memory, when finish, notified by interrupt */ + FCSPI_TRANSFER_TRIGGER_SRC_DMA_ISR, /*!< hardware(DMA) move data between register and memory, when finish, notified by interrupt */ + FCSPI_TRANSFER_TRIGGER_SRC_USER_POLL /*!< NOT use ISR and DMA!!! driver user use API to move data between register and memory, notified by return value when finish */ +} FCSPI_TriggerSrcType; + + +/** + * @brief transfer stop callback function's prototype + * + * FCSpi use this type to define one function pointer variable, + * which is called when the transfer is aborted or finished. + */ +typedef void (*FCSPI_StopCbType)(FCSPI_InstanceType eInst, FCSPI_AtomicBoolType bIsInIsr); + + +/** + * @brief Type return by semaphore callback function + * + * If want to use synchronous tranfer API, driver user need to provide semaphore callback, + * these callback function should return value of this enumeration defined. + */ +typedef enum { + FCSPI_SEMAPHORE_SUCCESS = 0, /*!< semaphore function execute successfully */ + FCSPI_SEMAPHORE_FAIL = 1, /*!< semaphore function execute fail */ + FCSPI_SEMAPHORE_TIMEOUT = 2 /*!< wait to get semaphore until reaching deadline */ +} FCSPI_SemaphoreStatType; + +/** + * @brief Callback function to reset semaphore + * + * After calling this function, the semaphore variable has a zero semaphore count. + * Then if try to take the semaphore, the take API will blocks. + * + * If the RTOS is FreeRTOS, the reference code as following. + * + * @code + * FCSPI_SemaphoreStatType SpiSemaphoreReset(FCSPI_InstanceType eInst) + * { + * while ( xSemaphoreTake( xSemaphore, ( TickType_t ) 0 ) == pdTRUE ); + * return FCSPI_SEMAPHORE_SUCCESS; + * } + * @endcode + */ +typedef FCSPI_SemaphoreStatType (*FCSPI_SemaphoreResetCbType)(FCSPI_InstanceType eInst); + +/** + * @brief Callback function to obtain semaphore + * + * This function will only try to obtain the semaphore before the time expires. + * + * If the RTOS is FreeRTOS, the reference code as following. + * + * @code + * FCSPI_SemaphoreStatType SpiSemaphoreTake(FCSPI_InstanceType eInst, uint32_t u32Timeout) + * { + * if ( xSemaphoreTake( xSemaphore, ( TickType_t ) u32Timeout ) == pdTRUE ) + * return FCSPI_SEMAPHORE_SUCCESS; + * else + * return FCSPI_SEMAPHORE_TIMEOUT; + * } + * @endcode + */ +typedef FCSPI_SemaphoreStatType (*FCSPI_SemaphoreTakeCbType)(FCSPI_InstanceType eInst, uint32_t u32Timeout); + + +/** + * @brief Callback function to release semaphore + * + * This function will only release semaphore. + * + * If the RTOS is FreeRTOS, the reference code as following. + * + * @code + * static FCSPI_SemaphoreStatType SpiSemaphorePost(FCSPI_InstanceType eInst, FCSPI_AtomicBoolType bIsInIsr) + * { + * FCSPI_SemaphoreStatType eRet = FCSPI_SEMAPHORE_SUCCESS; + * + * (void)eInst; + * if (FCSPI_TRUE == bIsInIsr) + * { + * BaseType_t tBase = pdFALSE; + * + * if ( xSemaphoreGiveFromISR( xSemaphore, &tBase ) == pdPASS ) + * { + * portYIELD_FROM_ISR(tBase); + * eRet = FCSPI_SEMAPHORE_SUCCESS; + * } + * else + * { + * eRet = FCSPI_SEMAPHORE_FAIL; + * } + * } + * else + * { + * if ( xSemaphoreGive( xSemaphore ) == pdPASS ) + * eRet = FCSPI_SEMAPHORE_SUCCESS; + * else + * eRet = FCSPI_SEMAPHORE_FAIL; + * } + * + * return eRet; + * } + * @endcode + */ +typedef FCSPI_SemaphoreStatType (*FCSPI_SemaphorePostCbType)(FCSPI_InstanceType eInst, FCSPI_AtomicBoolType bIsInIsr); + + +/** + * @brief Asynchronous Transfer data buffer information + * + * @note @verbatim +if init frame bit count need N bytes to store, for example, 7bits need N=1 byte, 9bits need N=2bytes, 23bits need N=3bytes. +N = 1, one frame data stored in pSendBuffer using uint8_t, driver read data using step 1byte. +N = 2, one frame data stored in pSendBuffer using uint16_t, driver read data using step 2byte. +N = 3, one frame data stored in pSendBuffer using uint32_t, driver read data using step 4byte.The highest byte is dropped. +N > 3, byte count of frame data stored in the parameter pointer pSendBuffer aligned with 4bytes, + for example, one frame uses 5bytes, it will need two uint32_t, the highest 3bytes are dropped, + driver API user need declare as "uint32_t data[N]"; it use index 0 to 1, the next frame is 2 to 3. + @endverbatim + */ +typedef struct { + const uint8_t *pSendBuffer; /*!< The buffer containing data to be send, must keep valid before sending is terminated or finished, can be NULL */ + uint8_t *pReceiveBuffer; /*!< Optional, can be NULL. Buffer to store the data received.The data received is 1byte aligned, no dummy data insert. */ + uint16_t u16FrameCount; /*!< The frame count to be sent, the data stored in pSendBuffer is divided into many frames. */ +} FCSPI_AsyncDataInfType; + + +/** + * @brief Synchronous Transfer data buffer information + * + * @note @verbatim +if init frame bit count need N bytes to store, for example, 7bits need N=1 byte, 9bits need N=2bytes, 23bits need N=3bytes. +N = 1, one frame data stored in pSendBuffer using uint8_t, driver read data using step 1byte. +N = 2, one frame data stored in pSendBuffer using uint16_t, driver read data using step 2byte. +N = 3, one frame data stored in pSendBuffer using uint32_t, driver read data using step 4byte.The highest byte is dropped. +N > 3, byte count of frame data stored in the parameter pointer pSendBuffer aligned with 4bytes, + for example, one frame uses 5bytes, it will need two uint32_t, the highest 3bytes are dropped, + driver API user need declare as "uint32_t data[N]"; it use index 0 to 1, the next frame is 2 to 3. + @endverbatim + */ +typedef struct { + const uint8_t *pSendBuffer; /*!< The buffer containing data to be send, must keep valid before sending is terminated or finished, can be NULL */ + uint8_t *pReceiveBuffer; /*!< Optional, can be NULL. Buffer to store the data received.The data received is 1byte aligned, no dummy data insert. */ + uint16_t u16FrameCount; /*!< The frame count to be sent, the data stored in pSendBuffer is divided into many frames. */ + uint32_t u32Timeout; /*!< The timeout value, it will only be passed to the semaphore callback API configured by driver user */ +} FCSPI_SyncDataInfType; + +/** + * @brief tx/rx remain information + * + * + */ +typedef struct { + uint32_t u32ByteCountSendRemained; /*!< byte count remains to be sent */ + uint32_t u32ByteCountReceiveRemained; /*!< byte count remains to be get */ +} FCSPI_TransferRemainInfType; + + +/** + * @brief configuration when use DMA + * + * + */ +typedef struct { + DMA_InstanceType eDMAInstance; /*!< DMA Instance number, if DMA not used, this ignored */ + uint8_t u8RxDMAChannel; /*!< DMA channel number for Rx, if DMA not used, this ignored */ + uint8_t u8TxDMAChannel; /*!< DMA channel number for Tx, if DMA not used, this ignored */ + uint8_t u8RxDMAChannelPriority; /*!< DMA channel priority for Rx, should differ from others in project scope */ + uint8_t u8TxDMAChannelPriority; /*!< DMA channel priority for Tx, should differ from others in project scope */ +} FCSPI_TriggerDmaInfType; +/**@}*/ + + + +/** + * @name Type definition for FCSpi master mode + * + */ +/**@{*/ +/** + * @brief FCSpi Master mode configuration + * + * When One FCSpi instance used as master side, API "FCSPI_Master_Init" need this parameter to configure the driver. + * + */ +typedef struct { + uint32_t u32FCSpiSrcClk; /*!< fcspi hardware module source clock */ + + /* peripheral chip select configuration */ + FCSPI_PCSType ePcs; /*!< chip select pin */ + FCSPI_PcsPolarityType ePcsPolarity; /*!< chip select pin polarity */ + FCSPI_AtomicBoolType eIsPcsContinuous; /*!< keep PCS select enable until transfer finish */ + + /* about sample point, sample bit order */ + FCSPI_SckSamplePhaseType eSckSamplePhase; /*!< select which edge of active sck clock to capture data */ + FCSPI_SckPolarityType eSckPolarity; /*!< select output sclk clock polarity */ + FCSPI_BitFirstOrderType eBitFirstOrder; /*!< transmit LSB/MSB first */ + uint32_t u32BitCntPerSecond; /*!< baud rate in bits per second, actual baudrate is calculated in driver, it's the nearest value to this parameter */ + uint16_t u16BitCountPerFrame; /*!< bit count of one frame, should >= 8, we call the data after pcs select, before pcs become invalid, as a frame, */ + + FCSPI_TriggerSrcType eTransferTriggerSrc; /*!< type of transfer data between memory and data register of FCSPI */ + + /* if eTransferTriggerSrc is "FCSPI_TRANSFER_TRIGGER_SRC_DMA_ISR", these following fields should be set, or ingore */ + FCSPI_TriggerDmaInfType tTriggerDmaInf; /*!< if trigger src is DMA, this MUST configure */ + + /* if to be notified when transmittion successfully or aborted, need set these following fields */ + FCSPI_StopCbType pStopNotifyCb; /*!< transfer stop(transfer successfully or aborted) callback function, can be NULL */ + + /* if want to use semaphore to synchronous transfer, the following need to be set */ + FCSPI_SemaphoreResetCbType pSemaResetCb; /*!< function to reset the semaphore to init state */ + FCSPI_SemaphoreTakeCbType pSemaTakeCb; /*!< function pointer to get the semaphore */ + FCSPI_SemaphorePostCbType pSemaPostCb; /*!< function pointer to release the semaphore */ +} FCSPI_MasterCfgType; + +/** + * @brief parameters about the holding time (in us) between PCS and SCK + * + * Configure the duration (in us) of the clock voltage between PCS and SCK + */ +typedef struct { + uint32_t u32PCStoPCSHoldUs; /*!< Configures the delay cycles from the PCS negation to the next PCS assertion, in microsecond(us) */ + uint32_t u32SCKtoPCSHoldUs; /*!< Configure the delay cycles from the last SCK edge to the PCS negation, in microsecond(us) */ + uint32_t u32PCStoSCKHoldUs; /*!< Configure the delay cycles from the PCS assertion to the first SCK edge, in microsecond(us) */ +} FCSPI_MasterSckPcsHoldTimeType; + +/** + * @brief parameters about the holding time (in PCS/100) between PCS and SCK + * + * Configure the duration (in PCS/100) of the clock voltage between PCS and SCK + */ +typedef struct { + uint32_t u32PCStoPCSHoldPercentage; /*!< Configure the delay cycles from the PCS negation to the next PCS assertion, in PCS/100 */ + uint32_t u32SCKtoPCSHoldPercentage; /*!< Configure the delay cycles from the last SCK edge to the PCS negation, in PCS/100 */ + uint32_t u32PCStoSCKHoldPercentage; /*!< Configure the delay cycles from the PCS assertion to the first SCK edge, in PCS/100 */ +} FCSPI_MasterSckPcsHoldSckCycleType; + +/** + * @brief parameters about the PCS and its Polarity + * + * Configure the specific PCS to be used and its active polarity when FCSPI running as master side + */ +typedef struct { + FCSPI_PCSType ePcs; /*!< Which PCS pin to configure */ + FCSPI_PcsPolarityType ePolarity; /*!< Pin's active polarity */ +} FCSPI_MasterPcsConfType; +/**@}*/ + + +/** + * @name Type definition for FCSpi slave mode + * + */ +/**@{*/ +/** + * @brief FCSpi Slave mode configuration + * + * When One FCSpi instance used as slave side, API "FCSPI_Slave_Init" need this parameter to configure the driver. + */ +typedef struct { + FCSPI_BitFirstOrderType eBitFirstOrder; /*!< transmit LSB/MSB first */ + uint16_t u16BitCountPerFrame; /*!< bit count of one frame, should >= 8 */ + + FCSPI_PcsPolarityType ePcsPolarity; /*!< pcs polarity */ + FCSPI_PCSType ePcs; /*!< chip select pin */ + + + FCSPI_SckSamplePhaseType eSckSamplePhase; /*!< select which edge of active sck clock to capture data */ + FCSPI_SckPolarityType eSckPolarity; /*!< selects clock polarity */ + + + + FCSPI_TriggerSrcType eTransferTriggerSrc; /*!< type of transfer data between memory and data register of FCSPI */ + + /* if eTransferTriggerSrc is "FCSPI_TRANSFER_TRIGGER_SRC_DMA_ISR", these following fields should be set, or ingore */ + FCSPI_TriggerDmaInfType tTriggerDmaInf; /*!< if trigger src is DMA, this MUST configure */ + + /* if to be notified when transmittion stop(successfully, fail, aborted), need set these following fields */ + FCSPI_StopCbType pStopNotifyCb; /*!< transfer stop(successfully or fail, or aborted) callback function, can be NULL */ + + /* if want to use semaphore to synchronous transfer, the following need to be set */ + FCSPI_SemaphoreResetCbType pSemaResetCb; /*!< function to reset the semaphore to init state */ + FCSPI_SemaphoreTakeCbType pSemaTakeCb; /*!< function pointer to get the semaphore */ + FCSPI_SemaphorePostCbType pSemaPostCb; /*!< function pointer to release the semaphore */ +} FCSPI_SlaveCfgType; +/**@}*/ + +/** + * @name API declaration for FCSpi master mode + * + */ +/**@{*/ +/** + * @brief Init the FCSpi instance as spi master side + * + * @param eInst Which FCSpi Hardware instance + * @param pCfg Configuration of the FCSpi, MUST NOT NULL + * @return FCSPI_StatusType FCSPI_STATUS_SUCCESS when configure successfully. Others, some error occur. + */ +FCSPI_StatusType FCSPI_Master_Init(const FCSPI_InstanceType eInst, const FCSPI_MasterCfgType *pCfg); + +/** + * @brief Configure the holding time (in us) between PCS and SCK + * + * @param eInst Which FCSpi Hardware instance + * @param pCfg Configure the delay parameters between PCS and SCK, MUST NOT null + * @return FCSPI_StatusType FCSPI_STATUS_SUCCESS when configure successfully. Others, the hardware is busy now. + */ +FCSPI_StatusType FCSPI_Master_SetSckPcsHoldTime(const FCSPI_InstanceType eInst, const FCSPI_MasterSckPcsHoldTimeType *pCfg); + +/** + * @brief Configure the holding time (in SCK/100) between PCS and SCK + * + * @param eInst Which FCSpi Hardware instance + * @param pCfg Configure the delay parameters between PCS and SCK, MUST NOT null + * @return FCSPI_StatusType FCSPI_STATUS_SUCCESS when configure successfully. Others, the hardware is busy now. + */ +FCSPI_StatusType FCSPI_Master_SetSckPcsHoldSckPercentage(const FCSPI_InstanceType eInst, const FCSPI_MasterSckPcsHoldSckCycleType *pCfg); +/** + * @brief Select the PCS to use and configure + * + * @param eInst Which FCSpi Hardware instance + * @param pCfg Parameters about PCS configuration, MUST NOT null + * @return FCSPI_StatusType FCSPI_STATUS_SUCCESS when configure successfully. Others, the hardware is busy now. + */ +FCSPI_StatusType FCSPI_Master_SelectPcs(const FCSPI_InstanceType eInst, const FCSPI_MasterPcsConfType *pCfg); +/**@}*/ + +/** + * @name API declaration for FCSpi slave mode + * + */ +/**@{*/ +/** + * @brief Init the FCSpi instance as spi slave side + * + * @param eInst Which FCSpi Hardware instance + * @param pCfg Configuration of the FCSpi + * @return FCSPI_StatusType FCSPI_STATUS_SUCCESS when configure successfully. Others, some error occur. + */ +FCSPI_StatusType FCSPI_Slave_Init(const FCSPI_InstanceType eInst, const FCSPI_SlaveCfgType *pCfg); +/**@}*/ + +/** + * @name Type definition for FCSpi master/slave mode + * + */ +/**@{*/ +/** + * @brief Send and receive asynchronously + * 1) If the trigger source is driver user poll, this api not support this mode. + * 2) If the trigger source is interrupt or DMA, this api will start the transmission, then return immediately. + * After transmission stop, it will trigger an interrupt. + * During the transmission, the send data buffer and receive data buffer + * should keep valid until the transmission stop. + * @param eInst Which FCSpi Hardware instance + * @param pCfg the data information, MUST NOT null + * @return FCSPI_StatusType FCSPI_STATUS_SUCCESS when start transfer successfully. Others, some error occur. + */ +FCSPI_StatusType FCSPI_AsyncTransfer(const FCSPI_InstanceType eInst, const FCSPI_AsyncDataInfType *pCfg); + +/** + * @brief Send and receive synchronously + * 1) If the semaphore callbacks are configured, + * and the driver is configured transmitting triggered by interrupt, or by DMA, + * the driver will use semaphore to wait the transmission stopped. + * In this case, the timeout value is passed to semaphore callback directly. + * 2) If the semaphore callbacks are not configured, + * this api will poll the status when triggered by interrupt or DMA, + * or poll to trigger the transmission when the mode is "FCSPI_TRANSFER_TRIGGER_SRC_USER_POLL". + * In this case, the timeout value has different meaning for different trigger mode. + * Read the source code for detail. + * @param eInst Which FCSpi Hardware instance + * @param pCfg the data information, MUST NOT null + * @return FCSPI_StatusType FCSPI_STATUS_SUCCESS when transfer successfully. Others, some error occur. + */ +FCSPI_StatusType FCSPI_SyncTransfer(const FCSPI_InstanceType eInst, const FCSPI_SyncDataInfType *pCfg); + +/** + * @brief If it's in transfer, get its stat, or get the last transfer's stat. + * + * @param eInst Which FCSpi Hardware instance + * @param pCfg the transfer information, can be null + * @return FCSPI_StatusType FCSPI_STATUS_SUCCESS when the last transfer is finish successfully. Others, busy or error occur. + */ +FCSPI_StatusType FCSPI_GetLatestTransferStat(const FCSPI_InstanceType eInst, FCSPI_TransferRemainInfType *pCfg); + +/** + * @brief Abort current transfer if exist, or just recovery the hardware. + * + * @param eInst Which FCSpi Hardware instance + */ +void FCSPI_AbortTransfer(const FCSPI_InstanceType eInst); + +/** + * @brief Deinit the FCSpi + * + * @param eInst Which FCSpi Hardware instance + * @return FCSPI_StatusType FCSPI_STATUS_SUCCESS when deinit the FCSpi successfully. Others, the hardware is busy now. + */ +FCSPI_StatusType FCSPI_Deinit(const FCSPI_InstanceType eInst); + +/** + * @brief Select the trigger source(DMA with interrupt / interrupt / user poll) + * + * @param eInst Which FCSpi Hardware instance + * @param eSrc three source, 1) DMA move data between memory and registers, notified when finish by interrupt; 2) purely by interrupt; 3) purely by user poll. + * @return FCSPI_StatusType FCSPI_STATUS_SUCCESS when successfully. Others, error. + */ +FCSPI_StatusType FCSPI_SelectTriggerSrc(FCSPI_InstanceType eInst, FCSPI_TriggerSrcType eSrc); + +/** + * @brief fcspi 0 interrupt handler + * + * @note This function should be called as/in FCSPI 0 interrupt handler + */ +void FCSPI0_IRQHandler(void); + +/** + * @brief fcspi 1 interrupt handler + * + * @note This function should be called as/in FCSPI 1 interrupt handler + */ +void FCSPI1_IRQHandler(void); + +/** + * @brief fcspi 2 interrupt handler + * + * @note This function should be called as/in FCSPI 2 interrupt handler + */ +void FCSPI2_IRQHandler(void); + +/** + * @brief fcspi 3 interrupt handler + * + * @note This function should be called as/in FCSPI 3 interrupt handler + */ +void FCSPI3_IRQHandler(void); + +/** + * @brief fcspi 4 interrupt handler + * + * @note This function should be called as/in FCSPI 4 interrupt handler + */ +void FCSPI4_IRQHandler(void); + +/** + * @brief fcspi 5 interrupt handler + * + * @note This function should be called as/in FCSPI 5 interrupt handler + */ +void FCSPI5_IRQHandler(void); + +/**@}*/ + +/** @}*/ /* fc7xxx_driver_fcspi */ + +#if defined(__cplusplus) +} +#endif +#endif /* _DRIVER_FC7XXX_DRIVER_FCSPI_H_ */ diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_fcuart.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_fcuart.h new file mode 100644 index 0000000..1ae3a21 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_fcuart.h @@ -0,0 +1,437 @@ +/** + * @file fc7xxx_driver_fcuart.h + * @author Flagchip + * @brief FC7xxx FCUart driver type definition and API + * @version 0.1.0 + * @date 2024-01-10 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + */ + +/******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-10 Flagchip0122 N/A FC7xxx internal release version + ********************************************************************************/ + + +#ifndef _DRIVER_FC7XXX_DRIVER_FCUART_H_ +#define _DRIVER_FC7XXX_DRIVER_FCUART_H_ + + +#include "HwA_fcuart.h" + +/** + * @addtogroup fc7xxx_driver_fcuart + * @{ + */ + +/********* Macro ************/ +#define FCUART_FIFO_DEPTH 16U + +#define ESCAPE_CHARACTER (char)0x5c +#define ENTER (uint8_t)0x0d +#define NEW_LINE (uint8_t)0x0a +#define SPACE (uint8_t)0x20 +#define FLOAT_ZERO 0.00000001 + + +/********* Local typedef ************/ +/** + * @brief FCUART error status + * + */ +typedef enum +{ + FCUART_ERROR_OK = 0x00U, /**< FCUART_ERROR_OK means no error */ + FCUART_ERROR_INVALID_VERSION = 0x01U, /**< FCUART_ERROR_INVALID_VERSION means version is not same */ + FCUART_ERROR_FAILED = 0x02U, /**< FCUART_ERROR_FAILED means operation is failed */ + FCUART_ERROR_INVALID_PARAM = 0x04U, /**< FCUART_ERROR_INVALID_PARAM means parameters are invalid */ + FCUART_ERROR_INVALID_SIZE = 0x08U, /**< FCUART_ERROR_INVALID_SIZE means size is invalid */ + FCUART_ERROR_INVALID_SEQUENCE = 0x10U, /**< FCUART_ERROR_INVALID_SEQUENCE means sequence is error */ + FCUART_ERROR_TIMEOUT = 0x20U, /**< FCUART_ERROR_TIMEOUT means operation is timeout */ +}FCUART_ErrorTypeEnum; + +/** + * @brief UART fifo receive idle character number + */ +typedef enum +{ + FCUART_FIFO_RX_IDLE_DISABLE = 0U, + FCUART_FIFO_RX_IDLE_CHARACTER_1, + FCUART_FIFO_RX_IDLE_CHARACTER_2, + FCUART_FIFO_RX_IDLE_CHARACTER_4, + FCUART_FIFO_RX_IDLE_CHARACTER_8, + FCUART_FIFO_RX_IDLE_CHARACTER_16, + FCUART_FIFO_RX_IDLE_CHARACTER_32, + FCUART_FIFO_RX_IDLE_CHARACTER_64 +} FCUART_Fifo_RxIdleCharNumType; + + +/** + * @brief UART CTRL register interrupt + * + */ +typedef enum +{ + FCUART_INT_CTRL_ORIE = FCUART_CTRL_ORIE_MASK, + FCUART_INT_CTRL_NEIE = FCUART_CTRL_NEIE_MASK, + FCUART_INT_CTRL_FEIE = FCUART_CTRL_FEIE_MASK, + FCUART_INT_CTRL_PEIE = FCUART_CTRL_PEIE_MASK, + FCUART_INT_CTRL_TIE = FCUART_CTRL_TIE_MASK, + FCUART_INT_CTRL_TCIE = FCUART_CTRL_TCIE_MASK, + FCUART_INT_CTRL_RIE = FCUART_CTRL_RIE_MASK, + FCUART_INT_CTRL_IIE = FCUART_CTRL_IIE_MASK, + FCUART_INT_CTRL_TE = FCUART_CTRL_TE_MASK, + FCUART_INT_CTRL_RE = FCUART_CTRL_RE_MASK, + FCUART_INT_CTRL_M0IE = FCUART_CTRL_M0IE_MASK, + FCUART_INT_CTRL_M1IE = FCUART_CTRL_M1IE_MASK +} FCUART_InterruptSel; + +/** + * @brief UART error status type + * + */ +typedef enum +{ + FCUART_ERROR_NONE = 0x0000U, /**< FCUART_ERROR_NONE No Error, */ + FCUART_ERROR_RORF = 0x0001U, /**< FCUART_ERROR_RORF Receiver Overrun Flag, */ + FCUART_ERROR_NF = 0x0002U, /**< FCUART_ERROR_NF Noise Flag, */ + FCUART_ERROR_FEF = 0x0004U, /**< FCUART_ERROR_FEF Frame Error Flag, */ + FCUART_ERROR_PEF = 0x0008U, /**< FCUART_ERROR_PEF Parity Error Flag, */ + FCUART_ERROR_RPEF = 0x0010U, /**< FCUART_ERROR_RPEF Receive Data Parity Error Flag, */ + FCUART_ERROR_TPEF = 0x0020U /**< FCUART_ERROR_TPEF Transmit Data Parity Error Flag, */ +}FCUART_ErrorStatusType; + +/** + * @brief UART idle character number + */ +typedef enum +{ + FCUART_IDLE_CHARCTER_1 = 0U, + FCUART_IDLE_CHARCTER_2, + FCUART_IDLE_CHARCTER_4, + FCUART_IDLE_CHARCTER_8, + FCUART_IDLE_CHARCTER_16, + FCUART_IDLE_CHARCTER_32, + FCUART_IDLE_CHARCTER_64, + FCUART_IDLE_CHARCTER_128 +} FCUART_IdleCharNumType; + +/** + * @brief UART idle type + */ +typedef enum +{ + FCUART_START_AFTER_STARTBIT = 0U, + FCUART_START_AFTER_STOPBIT +} FCUART_IdleStartType; + +/** + * @brief UART initial data define + * + */ +typedef struct +{ + uint32_t u32ClkSrcHz; /**< module clock hz */ + FCUART_BitModeType eBitMode; /**< 8bits or 9bits */ + bool bParityEnable; /**< Parity Enable=1 */ + FCUART_ParityType eParityType; /**< parity type */ + FCUART_StopBitNumType eStopBit; /**< stop bit num; */ + bool bEnTxFifo; /**< Enable Tx FIFO, 16 data words depth */ + uint8_t u8TxFifoWaterMark; /**< Tx FIFO,When FIFO/buffer number equal or less than this + an interrupt or a DMA request will be generated */ + bool bEnRxFifo; /**< Enable Rx FIFO, 16 data words depth */ + uint8_t u8RxFifoWaterMark; /**< Rx FIFO, When FIFO/buffer number greater than this + an interrupt or a DMA request will be generated */ + FCUART_Fifo_RxIdleCharNumType eFifoRxIdleCharNum; /**< Fifo Rx idle character number */ + bool bEnTxEmptyDma; /**< Enable transmit DMA */ + bool bEnRxFullDma; /**< Enable receiver full DMA */ + bool bEnRxIdleDma; /**< Enable Rx Idle DMA */ + FCUART_IdleCharNumType eIdleCharNum; /**< Idle character number */ + FCUART_IdleStartType eIdleStart; /**< Idle character start type */ + uint32_t u32Baudrate; /**< normal baud-rate */ + uint32_t u32TransmitTimeout; /**< transmit timeout tick, default 3000U */ +} FCUART_InitType; + +/** + * @brief UART transmit and receive data define + * + */ +typedef struct +{ + uint8_t* pDatas; /**< Data buffer point, Must be initial with a array address */ + uint32_t u32DataLen; /**< data length */ +}FCUART_DataType; + +/** Error call back function type, errors are combine with FCUART_ErrorStatusType */ +typedef void (*FCUART_ErrorInterrupt_CallBackType)(uint8_t u8UartIndex, uint32_t u32Error); + +/** Transmit/Receive call back function type */ +typedef void (*FCUART_TxRxInterrupt_CallBackType)(uint8_t u8UartIndex, FCUART_DataType *pTxRxCfg); + +/** Idle call back function type */ +typedef void (*FCUART_IdleInterrupt_CallBackType)(uint8_t u8UartIndex); + +/** + * @brief UART callback functions data define + * + */ +typedef struct +{ + bool bEnErrorInterrupt; /**< enable error interrupt */ + FCUART_ErrorInterrupt_CallBackType pErrorNotify; /**< error interrupt callback function address */ + bool bEnRxInterrupt; /**< enable receive interrupt */ + FCUART_DataType *pRxBuf; /**< receive interrupt message buffer */ + FCUART_TxRxInterrupt_CallBackType pRxNotify; /**< receive interrupt callback function address */ + bool bEnTxInterrupt; /**< enable receive interrupt */ + FCUART_DataType *pTxBuf; /**< transfer interrupt message buffer */ + FCUART_TxRxInterrupt_CallBackType pTxEmptyNotify; /**< transfer empty interrupt callback function address */ + FCUART_TxRxInterrupt_CallBackType pTxCompleteNotify; /**< transfer complete interrupt callback function address */ + bool bEnIdleInterrupt; /**< enable idle interrupt */ + FCUART_IdleInterrupt_CallBackType pIdleNotify; /**< idle interrupt callback function address */ +} FCUART_InterruptType; + +/** + * @brief UART WakeUp functions data define + * + */ +typedef struct +{ + bool bEnWakeup; /**< enable wake-up */ + uint32_t u32WakeUpData; /**< wake-up data */ + +} FCUART_WakeupType; + + + +/** Errortype Define as uint8 */ +typedef uint8_t FCUART_ErrorType; + +/* ################################################################################## */ +/* ########################### Global Prototype Functions ########################### */ + + +/** + * @brief Initial UART variables Memory + * + */ +void FCUART_InitMemory(uint8_t u8UartIndex); + +/** + * @brief This Function is used to initial UART instance + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @param pInitCfg contains clock, baud-rate, Bit Mode, parity and so on. + * @return FCUART_ERROR_OK is ok, others are not ok + */ +FCUART_ErrorType FCUART_Init(uint8_t u8UartIndex, FCUART_InitType *pInitCfg); + +/** + * @brief This Function is used to de-initial UART instance + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @return FCUART_ERROR_OK is ok, others are not ok + */ +FCUART_ErrorType FCUART_DeInit(uint8_t u8UartIndex); + +/** + * @brief This Function is used to set UART interrupt + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @param pInterruptCfg contains callback functions + * @return FCUART_ERROR_OK is ok, others are not ok + */ +FCUART_ErrorType FCUART_SetInterrupt(uint8_t u8UartIndex, FCUART_InterruptType *pInterruptCfg); + +/** + * @brief This Function is used to set UART WakeUp + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @param pWakeupCfg contains UART wake-up parameters + * @return FCUART_ERROR_OK is ok, others are not ok + */ +FCUART_ErrorType FCUART_SetWakeup(uint8_t u8UartIndex, FCUART_WakeupType *pWakeupCfg); + +/** + * @brief This Function is used to start receiving + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @return FCUART_ERROR_OK is ok, others are not ok + */ +FCUART_ErrorType FCUART_StartReceive(uint8_t u8UartIndex); + +/** + * @brief This Function is used to stop receiving + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @return FCUART_ERROR_OK is ok, others are not ok + */ +FCUART_ErrorType FCUART_StopReceive(uint8_t u8UartIndex); + +/** + * @brief This Function is used to start transmit + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @return FCUART_ERROR_OK is ok, others are not ok + */ +FCUART_ErrorType FCUART_StartTransmit(uint8_t u8UartIndex); + +/** + * @brief This Function is used to stop transmitting + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @return FCUART_ERROR_OK is ok, others are not ok + */ +FCUART_ErrorType FCUART_StopTransmit(uint8_t u8UartIndex); + +/** + * @brief This Function is used to transmit UART data + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @param pUartData contains UART data and length + * @return FCUART_ERROR_OK is ok, others are not ok + */ +FCUART_ErrorType FCUART_Transmit(uint8_t u8UartIndex, FCUART_DataType *pUartData); + + +/** + * @brief This Function is used to print ASCII char from UART + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @param fmt is char format + * @return FCUART_ERROR_OK is ok, others are not ok + */ +FCUART_ErrorType FCUART_Printf(uint8_t u8UartIndex, char* fmt,...); + +/** + * @brief Get Stat Flag + * + * @param u8UartIndex UART instance + * @param eStatusType stat type + * @return FCUART STAT status flag + */ +uint32_t FCUART_GetStatus(uint8_t u8UartIndex, FCUART_StatType eStatusType); + +/** + * @brief This Function is used to receive data when polling (not used when rx interrupt enabled) + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @param pRxMsg is data buffer address, and pDatas need to be initialed with external buffer + * @return FCUART_ERROR_OK is ok, others are not ok + */ +FCUART_ErrorType FCUART_Receive_Polling(uint8_t u8UartIndex, FCUART_DataType *pRxMsg); + + +/** + * @brief This Function is used to get error when polling (not used when error interrupt enabled) + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @param pErrorValue is error value + * @return FCUART_ERROR_OK is ok, others are not ok + */ +FCUART_ErrorType FCUART_Error_Polling(uint8_t u8UartIndex, uint32_t *pErrorValue); + +/** + * @brief This Function is used to enable fcuart loop mode + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @param bStatus enable/disable status of loop mode + * @return FCUART_ERROR_OK is ok, others are not ok + * + */ +FCUART_ErrorType FCUART_SetLoopMode(uint8_t u8UartIndex, bool bStatus); + +/** + * @brief This Function is used to deal with FCUART TxRx interrupt + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * + */ +void FCUARTN_RxTx_IRQHandler(uint8_t u8UartIndex); + +/** + * @brief This Function is used to send 9 bits data + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @param u16Data data to send + * @return FCUART_ERROR_OK is ok, others are not ok + * + */ +FCUART_ErrorType FCUART_SendData_9Bits(uint8_t u8UartIndex, uint16_t u16Data); + +/** + * @brief This Function is used to Get 9 bits data + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @param pData pointer to data + * @return FCUART_ERROR_OK is ok, others are not ok + * + */ +FCUART_ErrorType FCUART_GetData_9Bits(uint8_t u8UartIndex, uint16_t *pData); + +/** + * @brief This Function is used to send 10 bits data + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @param u16Data data to send + * @return FCUART_ERROR_OK is ok, others are not ok + * + */ +FCUART_ErrorType FCUART_SendData_10Bits(uint8_t u8UartIndex, uint16_t u16Data); + +/** + * @brief This Function is used to Get 10 bits data + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @param pData pointer to data + * @return FCUART_ERROR_OK is ok, others are not ok + * + */ +FCUART_ErrorType FCUART_GetData_10Bits(uint8_t u8UartIndex, uint16_t *pData); + +/** + * @brief This Function is used to set bit mode,parity and stop bit + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @param pData pointer to data + * @return FCUART_ERROR_OK is ok, others are not ok + * + */ +FCUART_ErrorType FCUART_SetBitModeAndParity( uint8_t u8UartIndex, + FCUART_BitModeType eBitMode, + FCUART_StopBitNumType eStopBit, + FCUART_ParityType eParityType, + bool bParityEnable + ); + +/** + * @brief This Function is used to Get current interrupt mode + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @param u32Data Interrupt type to get + * @return true/false + * + */ +bool FCUART_GetInterruptMode(uint8_t u8UartIndex, uint32_t u32Data); + +/** + * @brief This Function is used to assign data to send through interrupt + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @param pData data pointer + * @param u32Length data length to send + * @return FCUART_ERROR_OK is ok, others are not ok + * + */ +FCUART_ErrorType FCUART_AssignTxInterruptData(uint8_t u8UartIndex, uint8_t * pData, uint32_t u32Length); + +/** @}*/ + + +FCUART_ErrorType FCUART_BufTransmitted(uint8_t u8UartIndex, FCUART_InterruptType *pInterruptCfg); + +#endif diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_flash.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_flash.h new file mode 100644 index 0000000..8382b95 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_flash.h @@ -0,0 +1,183 @@ +/** + * @file fc7xxx_driver_flash.c + * @author Flagchip + * @brief FC7xxx Flash driver type definition and API + * @version 0.1.0 + * @date 2024-01-11 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-11 Flagchip054 N/A First version for FC7200 + ******************************************************************************** */ +#ifndef _DRIVER_FC7XXX_DRIVER_FLASH_H_ +#define _DRIVER_FC7XXX_DRIVER_FLASH_H_ + +#include "device_header.h" + + +/** + * @addtogroup fc7xxx_driver_flash + * @{ + */ +/*********************************************************************************************************************** + * DEFINES + **********************************************************************************************************************/ + +/* ------------------------- PFlash ------------------------ */ +/** PFlash start address */ +#define PFLASH_ADDR_START 0x01000000U + +#define PFLASH_ADDR_END 0x011FFFFFU + +#define PFLASH_SIZE 0x00200000U /* 256KB */ + +#define PFLASH_BANK_SIZE 0x00100000U + +#define PFLASH_LAST256K_OFFSET 0xC0000UL + +/** Program minimum size */ +#define PFLASH_PROGRAM_PAGE_MIN_SIZE 0x08U /* 8 bytes */ +/** Program maximum */ +#define PFLASH_PROGRAM_PAGE_MAX_SIZE 0x80U /* 128 bytes */ + +/** Erase size */ +#define PFLASH_ERASE_SECTOR_SIZE 0x800U /* 2 KBytes */ + +/** Erase value of flash memory */ +#define PFLASH_ERASED_VALUE 0xFFU + +/** 4 PFlash Banks, every bank is 2MB */ +#define PFLASH_BANK_NUM 0x02U + + +/* ------------------------- DFlash ------------------------ */ + +/** DFlash total size */ +#define DFLASH_SIZE 0x00040000U /* 256KB */ +/** DFlash start address */ +#define DFLASH_ADDR_START 0x04000000U +/** DFlash end address */ +#define DFLASH_ADDR_END 0x0401FFFFU + +/** Program minimum size */ +#define DFLASH_PROGRAM_PAGE_MIN_SIZE 0x08U /* 16 bytes */ +/** Program maximum */ +#define DFLASH_PROGRAM_PAGE_MAX_SIZE 0x80U /* 128 bytes */ + +/** Erase size */ +#define DFLASH_ERASE_SECTOR_SIZE 0x800U /* 8 KBytes */ + +/** Erase value of flash memory */ +#define DFLASH_ERASED_VALUE 0xFFU + +/** 1 DFlash Banks, every bank is 2MB */ +#define DFLASH_BANK_NUM 0x01U + +/** DFlash Bank 0 size */ +#define DFLASH_BANK0_SIZE 0x00040000U + + + +#define FLASH_256KB_SIZE 0x00040000U + + +/** ########################################## Error Code ################################################ */ + + +/** + * \brief FLASH API error status + * + */ +typedef enum +{ + FLASH_ERROR_OK = 0x00U,/**< FLASH_ERROR_OK means no error */ + FLASH_ERROR_NO_INIT, /**< FLASH_ERROR_NO_INIT means rom code api address is not initialed */ + FLASH_ERROR_INVALID_VERSION, /**< FLASH_ERROR_INVALID_VERSION means rom code api version is not same */ + FLASH_ERROR_FAILED, /**< FLASH_ERROR_FAILED means operation is failed */ + FLASH_ERROR_INVALID_PARAM, /**< FLASH_ERROR_INVALID_PARAM means parameters are invalid */ + FLASH_ERROR_INVALID_ADDR, /**< FLASH_ERROR_INVALID_ADDR means address is invalid */ + FLASH_ERROR_INVALID_SIZE, /**< FLASH_ERROR_INVALID_SIZE means size is invalid */ + FLASH_ERROR_INVALID_SEQUENCE, /**< FLASH_ERROR_INVALID_SEQUENCE means sequence is error */ + FLASH_ERROR_TIMEOUT, /**< FLASH_ERROR_TIMEOUT means operation is timeout */ + FLASH_ERROR_END = 0xFFFFFFFFU /**< FLASH_ERROR_END make aligned 32bits */ +}FLASH_StatusType; + +typedef enum +{ + FLASH_BLOCK_SELECT0 =0x000u, + FLASH_BLOCK_SELECT1 =0x001u, + FLASH_DATA_BLOCK_SELECT0 =0x002u +}FLASH_API_BLOCK_SELECT_TYPE; + +/** ########################################## Type define ################################################ */ + + +/** + * \brief Flash driver parameter define + * + */ +typedef struct +{ + uint32_t u32Address; /**< Logical target address */ + uint32_t u32Length; /**< Length in logical sectors or bytes */ + uint8_t *pData; /**< Pointer to data buffer (read only) */ + uint8_t (*wdTriggerFct)(void*); /**< Pointer to watchdog handling function */ + void *wdTriggerFct_env; + uint32_t u32ErrorAddress; /**< Error address */ + +} FLASH_DRIVER_ParamType; + +/** + * \brief Initial Flash api address + * + */ +void FLASHDRIVER_Init(void); + +/** + * \brief flash driver erase block function + * + * \param blk_sel c + * \return ErrorType + */ +FLASH_StatusType FLASHDRIVER_FlashEraseBlock ( FLASH_API_BLOCK_SELECT_TYPE blk_sel ); + +/** + * \brief Pflash driver erase function, called after FLASHDRIVER_ArrayCopyToRam + * + * \param pFlashParam contains flash erase function parameter, address is align to 0x400, and length is align to 0x400 + * \return ErrorType + */ +FLASH_StatusType FLASHDRIVER_PFlashEraseSector ( FLASH_DRIVER_ParamType * pFlashParam ); + +/** + * \brief Pflash driver write function, called after FLASHDRIVER_ArrayCopyToRam + * + * \param pFlashParam contains flash write function parameter, address is align to 0x08, and length is align to 0x08 + * \return ErrorType + */ +FLASH_StatusType FLASHDRIVER_PFlashWrite ( FLASH_DRIVER_ParamType * pFlashParam ); + +/** + * \brief DFlash Driver Function for Erasing + * + * \param pFlashParam flash driver erase parameter + * \return ErrorType + */ +FLASH_StatusType FLASHDRIVER_DFlashEraseSector(FLASH_DRIVER_ParamType *pFlashParam); + +/** + * \brief DFlash Driver Function for Writing + * + * \param pFlashParam flash driver write parameter + * \return ErrorType + */ +FLASH_StatusType FLASHDRIVER_DFlashWrite(FLASH_DRIVER_ParamType *pFlashParam); + + +#endif /* end of DRIVER_FLASH_H_ */ diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_flexcan.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_flexcan.h new file mode 100644 index 0000000..43073c5 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_flexcan.h @@ -0,0 +1,463 @@ +/** + * @file fc7xxx_driver_flexcan.h + * @author Flagchip + * @brief FC7xxx CAN driver type definition and API + * @version 0.1.0 + * @date 2022-02-20 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ + +/* ******************************************************************************** + * Revision History: + * + * Version Date Author Descriptions + * --------- ---------- ------------ --------------- + * 0.1.0 2024-1-13 Flagchip0112 First version for FC7240 + ******************************************************************************** */ + +#ifndef _DRIVER_FC4XXX_DRIVER_FLEXCAN_H_ +#define _DRIVER_FC4XXX_DRIVER_FLEXCAN_H_ + +#include "HwA_flexcan.h" + + +/* ################################################################################## */ +/* ####################################### Macro #################################### */ + +#define FLEXCAN_CHECK_PARAMETERS STD_ON + + +/* ################################################################################## */ +/* ################################### Type define ################################## */ + +/** + * @addtogroup fc7xxx_driver_can + * @{ + */ + + + + + +/** + * @brief FLEXCAN ID Type + * + */ +typedef enum +{ + FLEXCAN_ID_STD = 0x00U, /**< FLEXCAN_ID_STD standard id */ + FLEXCAN_ID_EXT = 0x01U /**< FLEXCAN_ID_EXT extended id */ +} FLEXCAN_IdType; + +/** + * @brief FLEXCAN Data Frame Type + * + */ +typedef enum +{ + FLEXCAN_FRAME_DATA = 0x00U, /**< FLEXCAN_FRAME_DATA data frame */ + FLEXCAN_FRAME_REMOTE = 0x01U /**< FLEXCAN_FRAME_REMOTE remote frame */ +} FLEXCAN_DataType; + + +/** + * @brief FLEXCAN baud-rate clock source + * + */ +typedef enum +{ + FLEXCAN_BAUDCLK_HZ_8M = 8000000U, /**< FLEXCAN_BAUDCLK_HZ_8M 8MHz clock source */ + FLEXCAN_BAUDCLK_HZ_12M = 12000000U, /**< FLEXCAN_BAUDCLK_HZ_12M 12MHz clock source */ + FLEXCAN_BAUDCLK_HZ_16M = 16000000U, /**< FLEXCAN_BAUDCLK_HZ_16M 16MHz clock source */ + FLEXCAN_BAUDCLK_HZ_24M = 24000000U, /**< FLEXCAN_BAUDCLK_HZ_24M 24MHz clock source */ + FLEXCAN_BAUDCLK_HZ_48M = 48000000U, /**< FLEXCAN_BAUDCLK_HZ_48M 48MHz clock source */ + FLEXCAN_BAUDCLK_HZ_96M = 96000000U, /**< FLEXCAN_BAUDCLK_HZ_96M 96MHz clock source */ + FLEXCAN_BAUDCLK_HZ_120M = 120000000U,/**< FLEXCAN_BAUDCLK_HZ_120M 120MHz clock source */ + FLEXCAN_BAUDCLK_HZ_150M = 150000000U /**< FLEXCAN_BAUDCLK_HZ_150M 150MHz clock source */ +} FLEXCAN_BaudClkType; + + + +/** + * @brief FLEXCAN baud-rate source + * + */ +typedef enum +{ + FLEXCAN_BAUD_100K = 100000U, /**< FLEXCAN_BAUD_100K normal bit 100Kbps */ + FLEXCAN_BAUD_125K = 125000U, /**< FLEXCAN_BAUD_100K normal bit 125Kbps */ + FLEXCAN_BAUD_250K = 250000U, /**< FLEXCAN_BAUD_250K normal bit 250Kbps */ + FLEXCAN_BAUD_500K = 500000U, /**< FLEXCAN_BAUD_500K normal bit 500Kbps */ + FLEXCAN_BAUD_800K = 800000U, /**< FLEXCAN_BAUD_500K normal bit 800Kbps */ + FLEXCAN_BAUD_1M = 1000000U,/**< FLEXCAN_BAUD_1M normal bit 1Mbps */ + FLEXCAN_BAUD_2M = 2000000U,/**< FLEXCAN_BAUD_2M normal bit 2Mbps */ + FLEXCAN_BAUD_3M = 3000000U,/**< FLEXCAN_BAUD_3M normal bit 3Mbps */ + FLEXCAN_BAUD_4M = 4000000U,/**< FLEXCAN_BAUD_4M normal bit 4Mbps */ + FLEXCAN_BAUD_5M = 5000000U,/**< FLEXCAN_BAUD_5M normal bit 5Mbps */ + FLEXCAN_BAUD_6M = 6000000U,/**< FLEXCAN_BAUD_6M normal bit 6Mbps */ + FLEXCAN_BAUD_8M = 8000000U /**< FLEXCAN_BAUD_8M normal bit 8Mbps */ +} FLEXCAN_BaudType; + +/** + * @brief FLEXCAN data length type + * + */ +typedef enum +{ + FLEXCAN_DATAWIDTH_8 = 8U, /**< FLEXCAN_DATALEN_8 8 bytes data width */ + FLEXCAN_DATAWIDTH_16 = 16U,/**< FLEXCAN_DATALEN_16 16 bytes data width */ + FLEXCAN_DATAWIDTH_32 = 32U,/**< FLEXCAN_DATALEN_32 32 bytes data width */ + FLEXCAN_DATAWIDTH_64 = 64U /**< FLEXCAN_DATALEN_64 64 bytes data width */ + +} FLEXCAN_DataWidthType; + +/** + * @brief FLEXCAN data length type + * + */ +typedef enum +{ + FLEXCAN_DIR_DISABLE = 0U, /**< FLEXCAN_DATALEN_8 8 bytes data width */ + FLEXCAN_DIR_ENABLE_WITHOUT_TRIG = 1U, /**< FLEXCAN_DATALEN_8 8 bytes data width */ + FLEXCAN_DIR_ENABLE_WITH_TRIG = 3U /**< FLEXCAN_DATALEN_8 8 bytes data width */ +} FLEXCAN_DirectType; + +/** + * @brief FLEXCAN init structure definition + */ +typedef struct +{ + FLEXCAN_ClockSrcType eClkSrcSel; /**< Clock Source Select */ + FLEXCAN_BaudClkType eClkSrcHz; /**< clock hz for baud-rate */ + uint8_t bListenOnly; + uint8_t bEnFd; /**< enable FLEXCAN fd */ + uint8_t bEnBrs; /**< data bit baud-rate used */ + uint8_t bEnRxFifo; /**< Rx FIFO */ + uint8_t bEnDma; /**< The DMA feature FLEXCAN only be used in Rx FIFO */ + uint8_t u8EnhancedFifoDmaWM; /**< The DMA watermark only work in CANFD FIFO mode, range 1- 12 */ + FLEXCAN_BaudType eBaudrate; /**< normal baud-rate */ + FLEXCAN_BaudType eDataBaud; /**< data baud-rate */ + FLEXCAN_DataWidthType eMbDataWidth; /**< when bEnFd=0, only FLEXCAN be set 8; when bEnFd=1, FLEXCAN be set as 8/16/32/64 */ + FLEXCAN_DirectType eDirect; /** C/C++ Build -> Settings -> Tool Settings -> Target Processor -> Float ABI -> FP instructions(hard) -> FPU Type set to "fpv5-sp-d16" +2) configure FCIDE to enable FPU compiler support, "Properties" -> C/C++ Build -> Settings -> Tool Settings -> GNU Arm Cross C Compiler -> Preprocessor -> Defined symbols(-D) -> Add "__FPU_PRESENT=1" (without ") +3) and call FPU_Enable to enable FPU at the beginning of program. + +If want to use DSP, +1) configure FCIDE to enable FPU compiler support, Properties -> C/C++ Build -> Settings -> Tool Settings -> Target Processor -> Float ABI -> FP instructions(hard) +2) add MACRO "DRIVER_CM7_DSP_ENABLE" in FCIDE Properties -> C/C++ General -> Paths and Symbols -> Symbols -> GNU C and GNU C++ and Assembly +3) add Include Path to project Properties -> C/C++ General -> Paths and Symbols -> Includes -> GNU C and GNU C++ and Assembly: + ../../../../../../Template/Device/CMSIS5_590/DSP/Include + ../../../../../../Template/Device/CMSIS5_590/Core/Include + ../../../../../../Template/Device/CMSIS5_590/DSP/PrivateInclude +4) and call FPU_Enable to enable FPU at the beginning of program. + @endverbatim + */ +void FPU_Enable(void); + +/** + * @brief Disable the FPU hardware. + * + */ +void FPU_Disable(void); + +/** @} */ /* fc7xxx_driver_fpu */ +#if defined(__cplusplus) +} +#endif +#endif /* _DRIVER_FC4XXX_DRIVER_FPU_H_ */ diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_freqm.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_freqm.h new file mode 100644 index 0000000..14a6d02 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_freqm.h @@ -0,0 +1,143 @@ +/** + * @file fc7xxx_driver_freqm.h + * @author Flagchip + * @brief FC7xxx FREQM driver type definition and API + * @version 0.1.0 + * @date 2024-01-14 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/******************************************************************************** +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2024-01-14 qxw0100 N/A First version for FC7240 +********************************************************************************/ + +#ifndef _DRIVER_FC4XXX_DRIVER_FREQM_H_ +#define _DRIVER_FC4XXX_DRIVER_FREQM_H_ + +#include "HwA_freqm.h" +#include "stddef.h" +#if defined(__cplusplus) +extern "C" { +#endif + +/** + * @brief FREQM operation return values + * + */ +typedef enum +{ + FREQM_STATUS_SUCCESS = 0U, /*!< The FREQM operation is succeed */ + FREQM_STATUS_PARAM_INVALID, /*!< The FREQM operation is failed because of parameter error */ + FREQM_STATUS_TIMEOUT, /*!< The FREQM operation is failed because of time out */ +} FREQM_StatusType; + +/** + * @brief The FREQM measure counter start interrupt callback function prototype + * + */ +typedef void (*FREQM_MesCntStartCallBackType)(void); + +/** + * @brief The FREQM measure counter stop interrupt callback function prototype + * + */ +typedef void (*FREQM_MesCntStopCallBackType)(void); + +/** + * @brief The FREQM reference counter stop interrupt callback function prototype + * + */ +typedef void (*FREQM_RefCntStopCallBackType)(void); +/** + * @brief The FREQM fault interrupt callback function prototype + * + */ +typedef void (*FREQM_FaultCallBackType)(void); + + +/** + * @brief The configuration option for the FREQM interrupt + * + */ +typedef struct +{ + bool bIntEnable; /*!< interrupt enable mask */ + FREQM_MesCntStartCallBackType pMesCntStartCallback; /*!< Measure Counter Start interrupt callback */ + FREQM_MesCntStopCallBackType pMesCntStopCallback; /*!< Measure Counter Stop interrupt callback */ + FREQM_RefCntStopCallBackType pRefCntStopCallback; /*!< Reference Counter Stop interrupt callback */ + FREQM_FaultCallBackType pFaultCallback; /*!< Fault interrupt callback */ +} FREQM_InterruptType; + +/** + * @brief The basic configuration option for the FREQM peripheral + * + */ +typedef struct +{ + uint32_t u32MesLen; + uint32_t u32RefTo; + FREQM_MesClkSelType eClkSel; /*!< Ftu clock source */ + uint8_t u8PredivVal; /*!< Frequency of the Reload Opportunities. Range is 0-31, */ +} FREQM_InitType; + + +/** + * @brief Initialize FREQM configuration + * + * @param pInitStruct the basic configurations of the FREQM + * @return FREQM_StatusType whether the operation is successfully + */ +FREQM_StatusType FREQM_Init(const FREQM_InitType *const pInitStruct); + +/** + * @brief De-initialize the FREQM + * + * @param eInstance the selected FREQM + * @return FREQM_StatusType whether the operation is successfully + */ +FREQM_StatusType FREQM_DeInit(void); + +/** + * @brief Start the FREQM + * + * @return FREQM_StatusType whether the operation is successfully + */ +FREQM_StatusType FREQM_ClearStatus(void); + +/** + * @brief Start the reference/measure counter + * + */ +void FREQM_StartMeasureCnt(void); + +/** + * @brief Get saved reference counter value + * + * @return uint32_t saved reference counter value + */ +uint32_t FREQM_GetRefCntSave(void); + +/** + * @brief Interrupt IRQ handle of FREQM + * + */ +void FREQM_IRQHandler(void); +/** + * @brief FREQM initialize interrupt function + * + * @param pIntStruct FREQM interrupt structure + * @return FREQM_StatusType whether the operation is successfully + */ +FREQM_StatusType FREQM_InterruptInit(const FREQM_InterruptType *const pIntrStruct); + +/** @}*/ /* fc7xxx_driver_freqm */ +#if defined(__cplusplus) +} +#endif +#endif diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_ftu.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_ftu.h new file mode 100644 index 0000000..120ac10 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_ftu.h @@ -0,0 +1,855 @@ +/** + * @file fc7xxx_driver_ftu.h + * @author Flagchip070 + * @brief FC7xxx FTU driver type definition and API + * @version 0.1.0 + * @date 2022-11-15 + * + * @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/******************************************************************************** +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2022-11-15 Flagchip070 N/A First version for FC7300 +********************************************************************************/ + +#ifndef _DRIVER_FC4XXX_DRIVER_FTU_H_ +#define _DRIVER_FC4XXX_DRIVER_FTU_H_ +#include "HwA_ftu.h" +#include "stddef.h" +#if defined(__cplusplus) +extern "C" { +#endif + +/** + * @addtogroup fc7xxx_driver_ftu + * @{ + */ + +/** + * @name FTU Channel Bit Flag + * @brief Bit of channel indicate channel number + * + * @{ + */ +#define BIT_FTU_CHANNEL_0 0x01U +#define BIT_FTU_CHANNEL_1 0x02U +#define BIT_FTU_CHANNEL_2 0x04U +#define BIT_FTU_CHANNEL_3 0x08U +#define BIT_FTU_CHANNEL_4 0x10U +#define BIT_FTU_CHANNEL_5 0x20U +#define BIT_FTU_CHANNEL_6 0x40U +#define BIT_FTU_CHANNEL_7 0x80U +/** @}*/ + +/** + * @name FTU Fault Bit Flag + * @brief Bit of fault flag + * + * @{ + */ +#define FTU_FAULT_INPUT_0 0x01U +#define FTU_FAULT_INPUT_1 0x02U +/** @}*/ + +/** + * @brief Max number of Ftu fault + * + */ +#define FTU_FAULT_COUNT 2u + +/** + * @brief Max number of Ftu input count + * + */ +#define FTU_INPUT_FILTER_COUNT 4u +/** + * @brief FTU operation return values + * + */ +typedef enum +{ + FTU_STATUS_SUCCESS = 0U, /*!< The FTU operation is success */ + FTU_STATUS_PARAM_INVALID, /*!< The FTU operation is failed because of parameter error */ + FTU_STATUS_NO_CLOCK_SOURCE, /*!< The FTU operation is failed because of instance clock source is not set */ +} FTU_StatusType; + +/** + * @brief The FTU overflow and reload point callback function prototype + * + */ +typedef void (*FTU_InterruptCallBackType)(void); + +/** + * @brief The FTU fault callback function prototype + * + */ +typedef void (*FTU_FaultCallBackType)(uint32_t); + +/** + * @brief The FTU channel callback function prototype + * + */ +typedef void (*FTU_ChannelCallBackType)(uint32_t, uint32_t); + +/** + * @brief The instance index of the FTU peripheral + * + */ +typedef enum +{ + FTU_INSTANCE_0 = 0U, + FTU_INSTANCE_1, + FTU_INSTANCE_2, + FTU_INSTANCE_3, + FTU_INSTANCE_4, + FTU_INSTANCE_5, + FTU_INSTANCE_6, + FTU_INSTANCE_7, +} FTU_InstanceType; + +/** + * @brief The channel index of the FTU peripheral + * + */ +typedef enum +{ + FTU_CHANNEL_0 = 0U, + FTU_CHANNEL_1, + FTU_CHANNEL_2, + FTU_CHANNEL_3, + FTU_CHANNEL_4, + FTU_CHANNEL_5, + FTU_CHANNEL_6, + FTU_CHANNEL_7 +} FTU_ChannelType; + +/** + * @brief The clock source of FTU peripheral + * + */ +typedef enum +{ + FTU_NO_CLK = 0U, /*!< No clock selected */ + FTU_INTERNAL_CLK = 1U, /*!< FTU input clock */ + FTU_EXTERNAL_CLK0 = 3U, /*!< External pin 0 input clock */ + FTU_EXTERNAL_CLK1 = 4U, /*!< External pin 1 input clock */ + FTU_EXTERNAL_CLK2 = 5U /*!< External pin 2 input clock */ +} FTU_ClkSrcType; + +/** + * @brief The channel operation of output compare mode + * + */ +typedef enum +{ + FTU_OUTPUT_TOGGLE_PIN = 0U, /*!< Toggle Output on match */ + FTU_OUTPUT_CLEAR_PIN, /*!< Clear Output on match */ + FTU_OUTPUT_SET_PIN /*!< Set Output on match */ +} FTU_OutputComparePinModeType; + +/** + * @brief The initial level of the output compare channel + * + */ +typedef enum +{ + FTU_OUTPUT_CMP_INIT_LOW = 0U, /*!< The initial level is low */ + FTU_OUTPUT_CMP_INIT_HIGH, /*!< The initial level is high */ +} FTU_OutputCompareInitLevelType; + +/** + * @brief The channel operation of PWM mode + * + */ +typedef enum +{ + FTU_PWM_HIGH_TRUE_PULSE = 0U, /*!< High-true pulses in PWM */ + FTU_PWM_LOW_TRUE_PULSE, /*!< Low-true pulses in PWM */ +} FTU_PwmPinModeType; + +/** + * @brief PWM Aligned Mode + * + */ +typedef enum +{ + FTU_EDGE_ALIGNED_PWM = 0u, /*!< Edge-Aligned PWM */ + FTU_CENTER_ALIGNED_PWM /*!< Center-Aligned PWM */ +}FTU_PwmAlignedType; + +/** + * @brief The measurement is single or continuous + * + */ +typedef enum +{ + FTU_MEASURE_SINGLE_MODE = 0u, /*!< Single mode */ + FTU_MEASURE_CONTINUOUS_MODE /*!< Continuous mode */ +} FTU_MeasureContModeType; + +/** + * @brief Timing of start measurement + * + */ +typedef enum +{ + FTU_MEASURE_START_AFTER_EDGE = 0u, /*!< The channel starts measuring after the first edge is detected */ + FTU_MEASURE_START_IMMEDIATELY /*!< The measurement starts immediately after activating the channel */ +}FTU_MeasureStartModeType; + +/** + * @brief The reload point flag of FTU peripheral + * + */ +typedef enum +{ + FTU_RELOAD_POINT_CNTMAX = 1u, /*!< Maximum Loading Point */ + FTU_RELOAD_POINT_CNTMIN = (1u << 1), /*!< Minimum Loading Point */ + FTU_RELOAD_POINT_CHANNEL_0 = (1u << 2), /*!< Channel 0 match is included as a reload opportunity */ + FTU_RELOAD_POINT_CHANNEL_1 = (1u << 3), /*!< Channel 1 match is included as a reload opportunity */ + FTU_RELOAD_POINT_CHANNEL_2 = (1u << 4), /*!< Channel 2 match is included as a reload opportunity */ + FTU_RELOAD_POINT_CHANNEL_3 = (1u << 5), /*!< Channel 3 match is included as a reload opportunity */ + FTU_RELOAD_POINT_CHANNEL_4 = (1u << 6), /*!< Channel 4 match is included as a reload opportunity */ + FTU_RELOAD_POINT_CHANNEL_5 = (1u << 7), /*!< Channel 5 match is included as a reload opportunity */ + FTU_RELOAD_POINT_CHANNEL_6 = (1u << 8), /*!< Channel 6 match is included as a reload opportunity */ + FTU_RELOAD_POINT_CHANNEL_7 = (1u << 9), /*!< Channel 7 match is included as a reload opportunity */ +} FTU_ReloadPointCfgType; + +/** + * @brief The synchronization flag of FTU peripheral + * + */ +typedef enum +{ + FTU_SYNC_FLAG_FTUEN = 1u, /*!< FTU Enable */ + FTU_SYNC_FLAG_LDOK = (1u << 1), /*!< Load Enable */ + FTU_SYNC_FLAG_CNTINC = (1u << 2), /*!< CNTIN Register Synchronization */ + FTU_SYNC_FLAG_PWMSYNC = (1u << 3), /*!< Synchronization Mode: Selects which triggers can be used + by MOD, CV, OUTMASK, and FTU counter synchronization. */ + FTU_SYNC_FLAG_REINIT = (1u << 4), /*!< FTU Counter re-initialization by Synchronization */ + FTU_SYNC_FLAG_SYNCHOM = (1u << 5), /*!< Selects when the OUTMASK register is updated with the + value of its buffer */ + FTU_SYNC_FLAG_SYNCEN01 = (1u << 6), /*!< synchronization of registers C(0)V and C(1)V. */ + FTU_SYNC_FLAG_SYNCEN23 = (1u << 7), /*!< synchronization of registers C(2)V and C(3)V. */ + FTU_SYNC_FLAG_SYNCEN45 = (1u << 8), /*!< synchronization of registers C(4)V and C(5)V. */ + FTU_SYNC_FLAG_SYNCEN67 = (1u << 9), /*!< synchronization of registers C(6)V and C(7)V. */ + FTU_SYNC_FLAG_HW_TRIG0 = (1u << 10), /*!< hardware trigger 0 to the synchronization */ + FTU_SYNC_FLAG_HW_TRIG1 = (1u << 11), /*!< hardware trigger 1 to the synchronization */ + FTU_SYNC_FLAG_HW_TRIG2 = (1u << 12), /*!< hardware trigger 2 to the synchronization */ +} FTU_SyncFlagType; + +/** + * @brief The interrupt enable/disable mask of FTU peripheral + * + */ +typedef enum +{ + FTU_INTR_MASK_CHANNEL_0 = 1u, /*!< interrupt mask of channel 0 */ + FTU_INTR_MASK_CHANNEL_1 = (1u << 1), /*!< interrupt mask of channel 1 */ + FTU_INTR_MASK_CHANNEL_2 = (1u << 2), /*!< interrupt mask of channel 2 */ + FTU_INTR_MASK_CHANNEL_3 = (1u << 3), /*!< interrupt mask of channel 3 */ + FTU_INTR_MASK_CHANNEL_4 = (1u << 4), /*!< interrupt mask of channel 4 */ + FTU_INTR_MASK_CHANNEL_5 = (1u << 5), /*!< interrupt mask of channel 5 */ + FTU_INTR_MASK_CHANNEL_6 = (1u << 6), /*!< interrupt mask of channel 6 */ + FTU_INTR_MASK_CHANNEL_7 = (1u << 7), /*!< interrupt mask of channel 7 */ + FTU_INTR_MASK_OVERFLOW = (1u << 8), /*!< interrupt mask of overflow */ + FTU_INTR_MASK_FAULT = (1u << 9), /*!< interrupt mask of fault */ + FTU_INTR_MASK_RELOAD_POINT = (1u << 10), /*!< interrupt mask of reload point */ +} FTU_IntrMaskType; + +/** + * @brief The fault control enable/disable mask for channels + * + */ +typedef enum +{ + FTU_FAULT_FOR_CHANNEL01 = 1u, /*!< fault control for channel 0 and channel 1 */ + FTU_FAULT_FOR_CHANNEL23 = (1u << 1), /*!< fault control for channel 2 and channel 3 */ + FTU_FAULT_FOR_CHANNEL45 = (1u << 2), /*!< fault control for channel 4 and channel 5 */ + FTU_FAULT_FOR_CHANNEL67 = (1u << 3), /*!< fault control for channel 6 and channel 7 */ +} FTU_FaultChannelEnableType; + +/** + * @brief the fault input polarity + * + */ +typedef enum +{ + FTU_FAULT_POL_ACTIVE_HIGH = 0u, /*!< The fault input polarity is active high. + 1 at the fault input indicates a fault */ + FTU_FAULT_POL_ACTIVE_LOW = 1u, /*!< The fault input polarity is active low. + 0 at the fault input indicates a fault */ +}FTU_FaultPolActiveType; + +/** + * @brief the output trigger mask + * + */ +typedef enum +{ + FTU_TRIG_OUTPUT_MASK_CHANNEL_0_MATCH = 1u, /*!< Enables/Disables the channel 0 match trigger */ + FTU_TRIG_OUTPUT_MASK_CHANNEL_1_MATCH = (1u << 1), /*!< Enables/Disables the channel 1 match trigger */ + FTU_TRIG_OUTPUT_MASK_CHANNEL_2_MATCH = (1u << 2), /*!< Enables/Disables the channel 2 match trigger */ + FTU_TRIG_OUTPUT_MASK_CHANNEL_3_MATCH = (1u << 3), /*!< Enables/Disables the channel 3 match trigger */ + FTU_TRIG_OUTPUT_MASK_CHANNEL_4_MATCH = (1u << 4), /*!< Enables/Disables the channel 4 match trigger */ + FTU_TRIG_OUTPUT_MASK_CHANNEL_5_MATCH = (1u << 5), /*!< Enables/Disables the channel 5 match trigger */ + FTU_TRIG_OUTPUT_MASK_CHANNEL_6_MATCH = (1u << 6), /*!< Enables/Disables the channel 6 match trigger */ + FTU_TRIG_OUTPUT_MASK_CHANNEL_7_MATCH = (1u << 7), /*!< Enables/Disables the channel 7 match trigger */ + FTU_TRIG_OUTPUT_MASK_ALL_CHANNEL_MATCH = (0xFFu), /*!< Enables/Disables all channel match trigger */ + FTU_TRIG_OUTPUT_MASK_RELOAD = (1u << 8), /*!< Enables/Disables reload trigger */ +}FTU_TriggerOutputMaskType; + +/** @brief Ftu input capture mode */ +typedef enum +{ + FTU_INPUT_RISING_EDGE = 0U, /*!< capture on rising edge only */ + FTU_INPUT_FALLING_EDGE, /*!< capture on falling edge only */ + FTU_INPUT_BOTH_EDGE /*!< capture on rising or falling edge */ +} FTU_InputCapturePinModeType; + +/** @brief Ftu Global Time Base instance start mask */ +typedef enum +{ + FTU_GTB_INSTANCE_START_FTU0 = 1u, /*!< FTU0 GTB start */ + FTU_GTB_INSTANCE_START_FTU1 = (1u << 1), /*!< FTU1 GTB start */ + FTU_GTB_INSTANCE_START_FTU2 = (1u << 2), /*!< FTU2 GTB start */ + FTU_GTB_INSTANCE_START_FTU3 = (1u << 3), /*!< FTU3 GTB start */ + FTU_GTB_INSTANCE_START_FTU4 = (1u << 4), /*!< FTU4 GTB start */ + FTU_GTB_INSTANCE_START_FTU5 = (1u << 5), /*!< FTU5 GTB start */ + FTU_GTB_INSTANCE_START_FTU6 = (1u << 6), /*!< FTU6 GTB start */ + FTU_GTB_INSTANCE_START_FTU7 = (1u << 7), /*!< FTU7 GTB start */ +} FTU_GlobalTimeBaseStartInstanceType; + +/** @brief Ftu Global Time Base start mask */ +typedef enum +{ + FTU_GTB_START_AT_ONCE = 1u, /*!< GTB start at once */ + FTU_GTB_START_AT_TSTMP1_MOD0 = (1u << 1), /*!< GTB start at modulate timer 0 of TSTMP1 */ + FTU_GTB_START_AT_TSTMP1_MOD1 = (1u << 2), /*!< GTB start at modulate timer 1 of TSTMP1 */ + FTU_GTB_START_AT_TSTMP1_MOD2 = (1u << 3), /*!< GTB start at modulate timer 2 of TSTMP1 */ + FTU_GTB_START_AT_TSTMP1_MOD3 = (1u << 4), /*!< GTB start at modulate timer 3 of TSTMP1 */ +} FTU_GlobalTimeBaseStartType; + +/** @brief FTU signal measurement mode type */ +typedef enum +{ + FTU_SIGNAL_MEASURE_HIGH_TIME = 0u, /*!< Measurement high time */ + FTU_SIGNAL_MEASURE_LOW_TIME = 1u, /*!< Measurement low time */ + FTU_SIGNAL_MEASURE_PERIOD_RISING_EDGE = 2u, /*!< Measurement period of rising edge */ + FTU_SIGNAL_MEASURE_PERIOD_FALLING_EDGE = 3u /*!< Measurement period of falling edge */ +} FTU_SignalMeasureModeType; + +/** @brief FTU signal measurement configuration type */ +typedef struct +{ + uint8_t u8Channel; /*!< selected FTU channel */ + FTU_SignalMeasureModeType eMeasureMode; /*!< signal measurement mode type */ + FTU_MeasureContModeType eContinuouslyMode; /*!< The measurement is single or continuous */ + FTU_MeasureStartModeType eStartMode; /*!< Timing of start measurement */ +} FTU_SignalMeasureType; + +/** @brief FTU signal measurement result time */ +typedef struct +{ + uint32_t u32StartTime; /*!< start time of measured signal */ + uint32_t u32EndTime; /*!< end time of measured signal */ +} FTU_SignalMeasureValueType; + +/** @brief Expect edge number result time */ +typedef struct +{ + uint32_t u32FirstEdgeTime; /*!< first edge time of measured signal */ + uint32_t u32LastEdgeTime; /*!< last edge time of measured signal */ +} FTU_ExpectEdgeNumberResultType; + +/** @brief FTU edge number measurement configuration type */ +typedef struct +{ + uint8_t u8Channel; /*!< selected FTU channel */ + FTU_InputCapturePinModeType eEdgeMode; /*!< input capture mode */ + FTU_MeasureContModeType eContinuouslyMode; /*!< The measurement is single or continuous */ + uint32_t u32StartWindow; /*!< start-point window */ + uint32_t u32EndWindow; /*!< end-point window */ +} FTU_EdgeNumberMeasureType; + +/** @brief FTU expect edge number measurement configuration type */ +typedef struct +{ + uint8_t u8Channel; /*!< selected FTU channel */ + FTU_InputCapturePinModeType eEdgeMode; /*!< input capture mode */ + uint8_t u8ExpectEdgeNumber; /*!< Expected number of edges */ + FTU_MeasureContModeType eContinuouslyMode; /*!< The measurement is single or continuous */ +} FTU_ExpectEdgeNumberMeasureType; + +/** + * @brief The configuration option for the FTU interrupt + * + */ +typedef struct +{ + uint32_t u32InterruptMask; /*!< interrupt enable mask */ + FTU_ChannelCallBackType pChannelCallback; /*!< channel interrupt callback */ + FTU_FaultCallBackType pFaultCallback; /*!< fault interrupt callback */ + FTU_InterruptCallBackType pOverflowCallback; /*!< overflow interrupt callback */ + FTU_InterruptCallBackType pReloadPointCallback; /*!< reload point interrupt callback */ +} FTU_InterruptType; + +/** + * @brief The configuration for the Pwm channel + * + */ +typedef struct +{ + uint8_t u8Channel; /*!< selected FTU channel */ + FTU_PwmPinModeType ePinMode; /*!< pwm mode */ + uint32_t u32PwmDuty; /*!< pwm duty (timer ticks) */ + uint32_t u32PhaseShift; /*!< pwm phase shift (timer ticks)*/ + bool bLinkMode; /*!< pwm channel link mode enable, channel num must be even,and the linked channel is current_channel+1*/ + bool bLinkChannelComplement; /*!< pwm link channel output complement */ + bool bDeadtimeEnable; /*!< Deadtime Enable */ + uint32_t u32ChannelDeadtime; /*!< The separated deadtime (source clock ticks) */ +} FTU_PwmChannelType; + +/** + * @brief The configuration option for the Pwm Mode + * + */ +typedef struct +{ + uint32_t u32PwmPeriod; /*!< pwm period (timer ticks) */ + uint32_t u32PublicDeadtime; /*!< pwm deadtime (source clock ticks) */ + FTU_PwmAlignedType eAlignedMode; /*!< pwm Aligned Mode */ + uint32_t u32ChannelCount; /*!< channel count of the Ftu instance */ + FTU_PwmChannelType *pPwmChannels; /*!< point to the pwm channel */ +} FTU_PwmModeType; + +/** + * @brief The configuration option for the output compare mode + * + */ +typedef struct +{ + uint8_t u8Channel; /*!< selected FTU channel */ + FTU_OutputComparePinModeType eOutputMode; /*!< ouput compare mode */ + uint32_t u32CompareValue; /*!< output compare value (timer ticks) */ + FTU_OutputCompareInitLevelType eInitLevel; /*!< the initial level of the channel */ +} FTU_OutputCompareModeType; + +/** + * @brief The configuration option for the time counter mode + * + */ +typedef struct +{ + uint32_t u32CounterValue; /*!< counter overflow value (timer ticks) */ + uint32_t u32InitialValue; /*!< counter initial value (timer ticks) */ +} FTU_CounterModeType; + +/** + * @brief The basic configuration option for the FTU peripheral + * + */ +typedef struct +{ + FTU_PrescalerType ePrescaler; /*!< Ftu prescaler */ + FTU_ClkSrcType eClkSrc; /*!< Ftu clock source */ + FTU_FilterPrescalerType eFliterPrescaler; /*!< Select the prescaler of the FTU filter */ + uint32_t u32OverflowValue; /*!< Ftu modulo value */ + uint16_t u16ReloadPoints; /*!< Ftu Synchronization points to update the buffered registers.Multiple + update modes can be used by providing an OR'ed list of options + available in enumeration ::FTU_ReloadPointCfgType. */ + uint8_t u8ReloadFreq; /*!< Frequency of the Reload Opportunities. Range is 0-31, */ + uint16_t u16SyncFlag; /*!< Ftu Synchronization flags to config the Synchronization and update of + the buffered registers. Multiple update modes can be used by + providing an OR'ed list of options available in + enumeration ::FTU_SyncFlagType. */ + FTU_TrigModeType eHwTrigMode; /*!< hardware trigger mode */ + FTU_DebugModeType eDbgMode; /*!< Ftu debug mode */ + FTU_UpDownDisableType eUpDownDisable; /*!< Disable channel match trigger/interrupt when count-up/down in CPWM/QUAD mode */ + bool bGtbEnable; /*!< Global Time Base Enable */ +} FTU_CommonType; + +/** + * @brief The configuration option for initializing FTU fault + * + */ +typedef struct +{ + FTU_FaultModeType eFaultMode; /*!< fault control mode */ + uint8_t u8FilterValue; /*!< selects the filter value for the fault inputs */ + uint8_t u8FaultChannelEnable; /*!< fault control for channel */ + uint8_t u8FaultDisableDelay0; /*!< Fault Disable Channel Output Delay Value 0 (timer ticks) */ + uint8_t u8FaultDisableDelay1; /*!< Fault Disable Channel Output Delay Value 1 (timer ticks) */ +} FTU_FaultInitType; + +/** + * @brief The configuration option for enabling a FTU fault + * + */ +typedef struct +{ + uint8_t u8FaultIndex; /*!< fault index */ + FTU_FaultPolActiveType eFaultPol; /*!< the fault input active polarity */ + bool bFaultFilterEnable; /*!< whether to enable fault input glitch filter*/ +} FTU_FaultControlType; + +/** + * @brief The configuration option for a input capture channel + * + */ +typedef struct +{ + uint8_t u8Channel; /*!< selected FTU channel */ + FTU_InputCapturePinModeType eInputMode; /*!< input capture mode */ + uint8_t u8FilterValue; /*!< selects the filter value for the channel input */ +} FTU_InputChannelType; + +/** + * @brief The configuration option for the quadrature decoder mode + * + */ +typedef struct +{ + FTU_QuadratureModeType eQuadMode; /*!< selects the encoding mode used in the Quadrature Decoder mode */ + FTU_QuadratureDirectionType eQuadDirection; /*!< indicates the counting direction */ + FTU_TimerOverflowDirectionType eOveflowDirection; /*!< Indicates if the TOF bit was set on the top or the bottom of counting */ + uint8_t u8PhaFilterVal; /*!< The filter value for the phase A input */ + uint8_t u8PhbFilterVal; /*!< The filter value for the phase B input */ + bool bPhaInverted; /*!< whether to inverted polarity of phase A input */ + bool bPhbInverted; /*!< whether to inverted polarity of phase B input */ + uint16_t u16TopValue; /*!< the top value of counting */ + uint16_t u16BottomValue; /*!< the bottom value of counting */ +} FTU_QuadratureInitType; + +/** + * @brief Initialize FTU basic configuration + * + * @param eInstance the selected FTU instance + * @param pCommonStruct the basic configurations of the FTU instance + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_CommonInit(const FTU_InstanceType eInstance, const FTU_CommonType *const pCommonStruct); + +/** + * @brief Fills in the FTU configuration structure with the default settings. + * + * @param pCommonStruct Pointer to the user configuration structure + */ +void FTU_GetDefaultInitCfg(FTU_CommonType *pCommonStruct); + +/** + * @brief Configure FTU to counter mode + * + * @param eInstance the selected FTU instance + * @param pCounterStruct the configurations of the counter mode + * @return FTU_StatusType whether the operation is successfully + * @note This function will stop timer + */ +FTU_StatusType FTU_CounterModeInit(const FTU_InstanceType eInstance, + const FTU_CounterModeType *const pCounterStruct); + + +/** + * @brief Configure FTU to output compare mode + * + * @param eInstance the selected FTU instance + * @param pOutputModeStruct the configurations of the output compare mode + * @return FTU_StatusType whether the operation is successfully + * @note This function will stop timer + */ +FTU_StatusType FTU_OutputCompareModeInit(const FTU_InstanceType eInstance, + const FTU_OutputCompareModeType *const pOutputModeStruct); + +/** + * @brief Configure Configure FTU to PWM mode + * + * @param eInstance the selected FTU instance + * @param pPwmModeStruct the configurations of the PWM mode + * @return FTU_StatusType whether the operation is successfully + * @note This function will stop timer + */ +FTU_StatusType FTU_PwmModeInit(const FTU_InstanceType eInstance, const FTU_PwmModeType *const pPwmModeStruct); + +/** + * @brief Update the duty cycle of the FTU instance + * + * @param eInstance the selected FTU instance + * @param u8Channel the selected FTU channel + * @param u32Duty duty cycle of the PWM mode + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_PwmUpdateDuty(const FTU_InstanceType eInstance, uint8_t u8Channel, uint32_t u32Duty); + +/** + * @brief Ftu initialize interrupt function + * + * @param eInstance the selected FTU instance + * @param pIntStruct the configurations of the interrupt + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_InterruptInit(const FTU_InstanceType eInstance, const FTU_InterruptType *const pIntStruct); + +/** + * @brief Enable FTU interrupt + * + * @param eInstance the selected FTU instance + * @param u32InterruptMask interrupt enable mask + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_EnableInterrupt(const FTU_InstanceType eInstance, uint32_t u32InterruptMask); + +/** + * @brief Enable FTU interrupt + * + * @param eInstance the selected FTU instance + * @param u32InterruptMask interrupt disable mask + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_DisableInterrupt(const FTU_InstanceType eInstance, uint32_t u32InterruptMask); +/** + * @brief Start the FTU instance + * + * @param eInstance the selected FTU instance + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_StartTimer(const FTU_InstanceType eInstance); +/** + * @brief Stop the FTU global time base + * + * @param u32InstanceMask The selected FTU, each bit represents an instance + */ +void FTU_StopGlobalTimeBase(uint32_t u32InstanceMask); +/** + * @brief Start the FTU global time base + * + * @param u32InstanceMask The selected FTU, each bit represents an instance + * @param u32StartMask Start time, refer to FTU_GlobalTimeBaseStartType + */ +void FTU_StartGlobalTimeBase(uint32_t u32InstanceMask, uint32_t u32StartMask); +/** + * @brief Stop the FTU instance + * + * @param eInstance the selected FTU instance + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_StopTimer(const FTU_InstanceType eInstance); + +/** + * @brief De-initialize the FTU instance + * + * @param eInstance the selected FTU instance + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_DeInit(const FTU_InstanceType eInstance); + +/** + * @brief initialize fault input of the selected Ftu instance + * + * @param eInstance the selected FTU instance + * @param pFaultInit the fault configurations of the FTU instance + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_FaultInit(const FTU_InstanceType eInstance, const FTU_FaultInitType *const pFaultInit); + +/** + * @brief Enable a fault input + * + * @param eInstance the selected FTU instance + * @param pFaultCtrl configurations of the fault input + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_FaultEnable(const FTU_InstanceType eInstance, const FTU_FaultControlType *const pFaultCtrl); + +/** + * @brief Select fault disable channel output delay value + * + * @param eInstance the selected FTU instance + * @param u8Channel FTU channel number, range is 0-7. + * @param eDelaySelection Fault disable channel output delay value selection. + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_FaultSelectDelayValue(const FTU_InstanceType eInstance, uint8_t u8Channel, FTU_FaultDisableDelayType eDelaySelection); +/** + * @brief Get Edge number counter + * + * @param eInstance the selected FTU instance + * @param u8Channel FTU channel number. + * @return uint8_t Edge number counter + */ +uint8_t FTU_GetEdgeNumberCount(const FTU_InstanceType eInstance, uint8_t u8Channel); +/** + * @brief Initialize a Edge Number Measurement channel + * + * @param eInstance the selected FTU instance + * @param pEdgeNumMeasure measurement configuration. + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_EdgeNumberMeasureChannelInit(const FTU_InstanceType eInstance, FTU_EdgeNumberMeasureType *pEdgeNumMeasure); +/** + * @brief Initialize a signal measure channel + * + * @param eInstance the selected FTU instance + * @param pMeasure measurement configuration. + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_SignalMeasureChannelInit(const FTU_InstanceType eInstance, FTU_SignalMeasureType *pMeasure); +/** + * @brief Re-start measurement when in single mode + * + * @param eInstance the selected FTU instance + * @param u8Channel FTU channel number, range is 0-7. + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_SignalMeasureChannelSingle(const FTU_InstanceType eInstance, uint8_t u8Channel); +/** + * @brief Get the measurement result of the channel + * + * @param eInstance the selected FTU instance + * @param u8Channel FTU channel number, range is 0-7. + * @param pResult point to the result buffer. + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_GetSignaMeasureResult(const FTU_InstanceType eInstance, uint8_t u8Channel, FTU_SignalMeasureValueType *pResult); +/** + * @brief Disable a fault input + * + * @param eInstance the selected FTU instance + * @param u32FaultIndex index of the fault input + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_FaultDisable(const FTU_InstanceType eInstance, uint32_t u32FaultIndex); + +/** + * @brief Clear the fault flag of the FTU instance + * + * @param eInstance the selected FTU instance + * @param u32FaultFlag flag to clear + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_ClearFault(const FTU_InstanceType eInstance, uint32_t u32FaultFlag); + +/** + * @brief Get the fault flag of the FTU instance + * + * @param eInstance the selected FTU instance + * @return uint32_t the fault flag of the selected Ftu instance + */ +uint32_t FTU_GetFaultFlag(const FTU_InstanceType eInstance); + +/** + * @brief initialize a input capture channel of the selected Ftu instance + * + * @param eInstance the selected FTU instance + * @param pInputChannel configurations of the input capture channel + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_InputCaptureChannelInit(const FTU_InstanceType eInstance, + const FTU_InputChannelType *const pInputChannel); +/** + * @brief enable the synchronization of the selected FTU + * + * @param eInstance the selected FTU instance + * @param u16ReloadPoints The synchronization flag + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_EnableSync(const FTU_InstanceType eInstance, uint16_t u16SyncFlag); +/** + * @brief disable the synchronization of the selected FTU + * + * @param eInstance the selected FTU instance + * @param u16SyncFlag The synchronization flag + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_DisableSync(const FTU_InstanceType eInstance, uint16_t u16SyncFlag); +/** + * @brief Enable the output trigger of the selected FTU instance + * + * @param eInstance the selected FTU instance + * @param u32TriggerOutputMask the output trigger mask + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_EnableTriggerOutput(const FTU_InstanceType eInstance, uint32_t u32TriggerOutputMask); +/** + * @brief Disable the output trigger of the selected FTU instance + * + * @param eInstance the selected FTU instance + * @param u32TriggerOutputMask the output trigger mask + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_DisableTriggerOutput(const FTU_InstanceType eInstance, uint32_t u32TriggerOutputMask); +/** + * @brief initialize the quadrature decoder mode + * + * @param eInstance the selected FTU instance + * @param pQuadInit configurations of the quadrature decoder + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_QuadratureModeInit(const FTU_InstanceType eInstance, + const FTU_QuadratureInitType *const pQuadInit); +/** + * @brief Enable the reload points of the selected FTU instance + * + * @param eInstance the selected FTU instance + * @param u16ReloadPoints The reload points flag + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_EnableReloadPoints(const FTU_InstanceType eInstance, uint16_t u16ReloadPoints); +/** + * @brief Disable the reload points of the selected FTU instance + * + * @param eInstance the selected FTU instance + * @param u16ReloadPoints The reload points flag + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_DisableReloadPoints(const FTU_InstanceType eInstance, uint16_t u16ReloadPoints); + +/** + * @brief Enable ftu channel DMA + * + * @param eInstance the selected FTU instance + * @param u32DmaMask The dma channel mask. + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_EnableChannelDma(const FTU_InstanceType eInstance, uint32_t u32DmaMask); +/** + * @brief Get the expect edge number result of the channel + * + * @param eInstance the selected FTU instance + * @param u8Channel FTU channel number, range is 0-7. + * @param pResult point to the result buffer. + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_GetExpectEdgeNumberResult(const FTU_InstanceType eInstance, uint8_t u8Channel, FTU_ExpectEdgeNumberResultType *pResult); +/** + * @brief Initialize a Expect Edge Number Measurement channel + * + * @param eInstance the selected FTU instance + * @param pExpectEdgeNumMeasure measurement configuration. + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_ExpectEdgeNumberMeasureChannelInit(const FTU_InstanceType eInstance, FTU_ExpectEdgeNumberMeasureType *pExpectEdgeNumMeasure); +/** + * @brief Get the measurement result of the channel + * + * @param eInstance the selected FTU instance + * @param u8Channel FTU channel number, range is 0-7. + * @param pResult point to the result buffer. + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_GetSignalMeasureResult(const FTU_InstanceType eInstance, uint8_t u8Channel, FTU_SignalMeasureValueType *pResult); +/** + * @brief Interrupt IRQ handle of FTU instance + * + * @param eInstance the selected FTU instance + */ +void FTUn_IRQHandler(const FTU_InstanceType eInstance); +/** @}*/ /* fc7xxx_driver_ftu */ +#if defined(__cplusplus) +} +#endif +#endif diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_gpio.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_gpio.h new file mode 100644 index 0000000..9e92846 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_gpio.h @@ -0,0 +1,145 @@ +/** + * @file fc7xxx_driver_gpio.h + * @author Flagchip + * @brief FC7xxx GPIO driver type definition and API + * @version 0.1.0 + * @date 2023-2-14 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + */ +/******************************************************************************** +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2022/12/31 Flagchip071 N/A First version for FC7240 +********************************************************************************/ +#ifndef DRIVER_GPIO_H_ +#define DRIVER_GPIO_H_ +#include "HwA_gpio.h" + +/** + * @addtogroup fc7xxx_driver_port + * @{ + */ + +/********* global define ************/ + +#define GPIO_MAX_PORT_PINS 32 + +#define GPIO_PIN_0 ((uint32_t)0x00000001) /**< GPIO Pin 0 select */ +#define GPIO_PIN_1 ((uint32_t)0x00000002) /**< GPIO Pin 1 select */ +#define GPIO_PIN_2 ((uint32_t)0x00000004) /**< GPIO Pin 2 select */ +#define GPIO_PIN_3 ((uint32_t)0x00000008) /**< GPIO Pin 3 select */ +#define GPIO_PIN_4 ((uint32_t)0x00000010) /**< GPIO Pin 4 select */ +#define GPIO_PIN_5 ((uint32_t)0x00000020) /**< GPIO Pin 5 select */ +#define GPIO_PIN_6 ((uint32_t)0x00000040) /**< GPIO Pin 6 select */ +#define GPIO_PIN_7 ((uint32_t)0x00000080) /**< GPIO Pin 7 select */ +#define GPIO_PIN_8 ((uint32_t)0x00000100) /**< GPIO Pin 8 select */ +#define GPIO_PIN_9 ((uint32_t)0x00000200) /**< GPIO Pin 9 select */ +#define GPIO_PIN_10 ((uint32_t)0x00000400) /**< GPIO Pin 10 select */ +#define GPIO_PIN_11 ((uint32_t)0x00000800) /**< GPIO Pin 11 select */ +#define GPIO_PIN_12 ((uint32_t)0x00001000) /**< GPIO Pin 12 select */ +#define GPIO_PIN_13 ((uint32_t)0x00002000) /**< GPIO Pin 13 select */ +#define GPIO_PIN_14 ((uint32_t)0x00004000) /**< GPIO Pin 14 select */ +#define GPIO_PIN_15 ((uint32_t)0x00008000) /**< GPIO Pin 15 select */ +#define GPIO_PIN_16 ((uint32_t)0x00010000) /**< GPIO Pin 16 select */ +#define GPIO_PIN_17 ((uint32_t)0x00020000) /**< GPIO Pin 17 select */ +#define GPIO_PIN_18 ((uint32_t)0x00040000) /**< GPIO Pin 18 select */ +#define GPIO_PIN_19 ((uint32_t)0x00080000) /**< GPIO Pin 19 select */ +#define GPIO_PIN_20 ((uint32_t)0x00100000) /**< GPIO Pin 20 select */ +#define GPIO_PIN_21 ((uint32_t)0x00200000) /**< GPIO Pin 21 select */ +#define GPIO_PIN_22 ((uint32_t)0x00400000) /**< GPIO Pin 22 select */ +#define GPIO_PIN_23 ((uint32_t)0x00800000) /**< GPIO Pin 23 select */ +#define GPIO_PIN_24 ((uint32_t)0x01000000) /**< GPIO Pin 24 select */ +#define GPIO_PIN_25 ((uint32_t)0x02000000) /**< GPIO Pin 25 select */ +#define GPIO_PIN_26 ((uint32_t)0x04000000) /**< GPIO Pin 26 select */ +#define GPIO_PIN_27 ((uint32_t)0x08000000) /**< GPIO Pin 27 select */ +#define GPIO_PIN_28 ((uint32_t)0x10000000) /**< GPIO Pin 28 select */ +#define GPIO_PIN_29 ((uint32_t)0x20000000) /**< GPIO Pin 29 select */ +#define GPIO_PIN_30 ((uint32_t)0x40000000) /**< GPIO Pin 30 select */ +#define GPIO_PIN_31 ((uint32_t)0x80000000) /**< GPIO Pin 31 select */ + +/************************************global typedef ***************************************/ + +/** @brief GPIO return structure */ +typedef enum +{ + GPIO_STATUS_SUCCESS = 0U, + GPIO_STATUS_PARAM_INVALID = 1U +} GPIO_StatusType; + +/** @brief GPIO instance number */ +typedef enum +{ + GPIO_A = 0U, + GPIO_B, + GPIO_C, + GPIO_D, + GPIO_E +} GPIO_InstanceType; + +/** @brief GPIO direction */ +typedef enum +{ + GPIO_OUT = 0U, /* GPIO pin directon is output */ + GPIO_IN = 1U, /* GPIO pin directon is input */ + GPIO_ZERO = 2U /* GPIO pin directon is input disable */ +} GPIO_PinDirectionType; + +typedef struct +{ + uint32_t u32GpioPins; + GPIO_PinDirectionType ePinDirection; + GPIO_PinLevelType ePinLevel; +}GPIO_InitType; + +/************************************global typedef ***************************************/ + +/** + * @brief Initialize GPIO. + * + * @param eGpio GPIO instance + * @param pInitStruct Initialization structure of GPIO. + */ +GPIO_StatusType GPIO_InitPins(const GPIO_InstanceType eGpio, const GPIO_InitType *const pInitStruct); + +/** + * @brief Initialize GPIO. + * + * @param eGpio GPIO instance + * @param u32Pins The bit of u32Pins indicate the pin number of this GPIO. + */ +GPIO_StatusType GPIO_Deinit(const GPIO_InstanceType eGpio, const uint32_t u32Pins); + +/** + * @brief Read level of input port pins. + * + * @param ePort Port instance for GPIO functionality + * @param u32Pins The bit of u32Pins indicate the pin number of this Port. + * @return Pins level + */ +uint32_t GPIO_ReadPins(const GPIO_InstanceType ePort, const uint32_t u32Pins); + +/** + * @brief Write gpio level to u32Pins. + * + * @param ePort Port instance for GPIO functionality + * @param u32Pins The bit of u32Pins indicate the pin number of this Port. + * @param eOutput Output level enumeration + * @return Port return type. + */ +GPIO_StatusType GPIO_WritePins(const GPIO_InstanceType ePort, const uint32_t u32Pins, const GPIO_PinLevelType eOutput); + +/** + * @brief Toggle gpio api + * + * @param ePort ePort Port instance for GPIO functionality + * @param u32Pins The bit of u32Pins indicate the pin number of this Port. + * @return Port return type. + */ +GPIO_StatusType GPIO_Toggle(const GPIO_InstanceType ePort, const uint32_t u32Pins); + + +#endif /* end of DRIVER_GPIO_H_ */ diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_hsm.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_hsm.h new file mode 100644 index 0000000..249d1dd --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_hsm.h @@ -0,0 +1,3277 @@ +/** + * @file fc7xxx_driver_hsm.h + * @author Flagchip0103 + * @brief FC7xxx HSM driver type definition and API + * @version 0.1.0 + * @date 2023-12-20 + * + * @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-20 Flagchip0103 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef DRIVER_HSM_H_ +#define DRIVER_HSM_H_ + +#include "device_header.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** + * @addtogroup fc7xxx_driver_hsm + * @{ + */ + + +/** + * @brief Status returned by HSM SDK CM7 side APIs + * + */ +typedef enum +{ + HSM_STATUS_SUCCESS = 0U, /*!< return this when HSM API execute successfully */ + HSM_STATUS_PARAM_ERR, /*!< return this when parameter error */ + HSM_STATUS_AGAIN, /*!< return this when need more API call to continue process */ + HSM_STATUS_FINISH, /*!< return this when the process is finish */ +} HSM_StatusType; + + +/** + * @name definitions for HSM_MailboxApiRetType + * + */ +/**@{*/ +/** + * @brief success status (HSM_MailboxApiRetType) returned by HSM subsystem APIs + * + */ +#define MAILBOXAPI_RET_SUCCESS (0u) + +/** + * @brief error status (HSM_MailboxApiRetType) returned by HSM subsystem APIs + * + */ +#define MAILBOXAPI_RET_ERROR (1u) + +/** + * @brief failure status (HSM_MailboxApiRetType) returned by HSM subsystem APIs + * + */ +#define MAILBOXAPI_RET_FAIL (2u) + +/** + * @brief verify pass status (HSM_MailboxApiRetType) returned by HSM subsystem APIs + * + */ +#define MAILBOXAPI_RET_PASS (3u) + +/** + * @brief function not support status (HSM_MailboxApiRetType) returned by HSM subsystem APIs + * + */ +#define MAILBOXAPI_RET_NOT_SUPPORT (4u) + +/** + * @brief hardware error status (HSM_MailboxApiRetType) returned by HSM subsystem APIs + * + */ +#define MAILBOXAPI_RET_HW_ERROR (5u) + +/** + * @brief have no permission status (HSM_MailboxApiRetType) returned by HSM subsystem APIs + * + */ +#define MAILBOXAPI_RET_NO_PRIVILEGES (6u) + +/** + * @brief parameters error status (HSM_MailboxApiRetType) returned by HSM subsystem APIs + * + */ +#define MAILBOXAPI_RET_PARAMETER_ERROR (7u) + +/** + * @brief authority error status (HSM_MailboxApiRetType) returned by HSM subsystem APIs + * + */ +#define MAILBOXAPI_RET_AUTHORITY_ERROR (8u) + +/** + * @brief hardware busy status (HSM_MailboxApiRetType) returned by HSM subsystem APIs + * + */ +#define MAILBOXAPI_RET_BUSY (9u) + +/** + * @brief flash ecc error status (HSM_MailboxApiRetType) returned by HSM subsystem APIs + * + */ +#define MAILBOXAPI_RET_ECC_ERR (10u) + +/** + * @brief time expire error status (HSM_MailboxApiRetType) returned by HSM subsystem APIs + * + */ +#define MAILBOXAPI_RET_TIMEOUIT (11u) + +/** + * @brief status type definition returned by HSM subsystem APIs + * + */ +typedef uint32_t HSM_MailboxApiRetType; +/**@}*/ + + +/** + * @brief HSM 4bytes unit data format for HSM_DataFormatType + * for example, if data is 0x000102030405060708090a0b0c0d0e0f, use this format, should be divided as following. + * 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f + */ +#define HSM_DATA_FORMAT_4B 0u + +/** + * @brief HSM 1byte unit data format for HSM_DataFormatType + * for example, if data is 0x000102030405060708090a0b0c0d0e0f, use this format, should be divided as following. + * 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f + */ +#define HSM_DATA_FORMAT_1B 1u + +/** + * @brief HSM data format + * refer to HSM_DATA_FORMAT_4B, HSM_DATA_FORMAT_1B + */ +typedef uint32_t HSM_DataFormatType; + + +/** + * @name Type definition for HSM Isr/Poll mode + * + */ +/**@{*/ + +typedef struct +{ + uint32_t u32Cmd; /*!< current command id to HSM core via mailbox */ + uint32_t u32Addr; /*!< current parameter address to HSM core via mailbox */ +} HSM_CmdType; + + +/** + * @name definitions for HSM_BoolType + * + */ +/**@{*/ +/** + * @brief Boolean false value definition for type HSM_BoolType used by HSM + * + */ +#define HSM_FALSE (0u) + +/** + * @brief Boolean true value definition for type HSM_BoolType used by HSM + * + */ +#define HSM_TRUE (1u) + +/** + * @brief Boolean type for HSM + * + */ +typedef uint32_t HSM_BoolType; +/**@}*/ + + +/* ------------------------------------------------------------------------------- */ +/** + * @brief the true random count return by the API + * + */ +#define HSM_TRNG_RAND_U32_CNT (16u) +/* ------------------------------------------------------------------------------- */ +/** + * @brief the true random source_0 definition for type HSMCom_TrueRandType.u32RandSrcType + * + */ +#define HSM_TRNG_SRC_0 (0u) +/* ------------------------------------------------------------------------------- */ +/** + * @brief the true random source_1 definition for type HSMCom_TrueRandType.u32RandSrcType + * + */ +#define HSM_TRNG_SRC_1 (1u) +/* ------------------------------------------------------------------------------- */ +/** + * @brief the true XOR random source_1 definition for type HSMCom_TrueRandType.u32RandSrcType + * + */ +#define HSM_TRNG_SRC_XOR (2u) +/* ------------------------------------------------------------------------------- */ +/** + * @brief the true any random source_1 definition for type HSMCom_TrueRandType.u32RandSrcType + * + */ +#define HSM_TRNG_SRC_ANY (3u) +/* ------------------------------------------------------------------------------- */ +/** + * @brief the pseudorandom source definition for type HSMCom_TrueRandType.u32RandSrcType + * + */ +#define HSM_DRNG_SRC (4u) +typedef uint32_t HSM_RndSrcType; +/** + * @brief the true random information passed to HSM core by mailbox + * + */ +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + uint32_t (*aRandom)[HSM_TRNG_RAND_U32_CNT]; /*!< the buffer address, HSM core will write random data to this buffer */ + HSM_RndSrcType u32RandSrc; /*!< which random source will be selected */ +} HSMCom_TrueRandType; + +/* ------------------------------------------------------------------------------- */ + + +/** + * @name definitions for HSM_HashAlgType + * + */ +/**@{*/ +/** + * @brief MD5 algorithm value for type "HSM_HashAlgType" + * + */ +#define HSM_HASH_MD5 (0U) + +/** + * @brief SHA160 algorithm value for type "HSM_HashAlgType" + * + */ +#define HSM_HASH_SHA160 (1U) + +/** + * @brief SHA224 algorithm value for type "HSM_HashAlgType" + * + */ +#define HSM_HASH_SHA224 (2U) + +/** + * @brief SHA256 algorithm value for type "HSM_HashAlgType" + * + */ +#define HSM_HASH_SHA256 (3U) + +/** + * @brief SHA384 algorithm value for type "HSM_HashAlgType" + * + */ +#define HSM_HASH_SHA384 (4U) + +/** + * @brief SHA512 algorithm value for type "HSM_HashAlgType" + * + */ +#define HSM_HASH_SHA512 (5U) + +/** + * @brief SHA512_224 algorithm value for type "HSM_HashAlgType" + * + */ +#define HSM_HASH_SHA512_224 (6U) + +/** + * @brief SHA512_256 algorithm value for type "HSM_HashAlgType" + * + */ +#define HSM_HASH_SHA512_256 (7U) + +/** + * @brief SM3 algorithm value for type "HSM_HashAlgType" + * + */ +#define HSM_HASH_SM3 (8U) + +/** + * @brief type definition for HASH algorithm + * refer to HSM_HASH_MD5,HSM_HASH_SHA160,HSM_HASH_SHA224,HSM_HASH_SHA256,HSM_HASH_SHA384,HSM_HASH_SHA512,HSM_HASH_SHA512_224,HSM_HASH_SHA512_256,HSM_HASH_SM3 + */ +typedef uint32_t HSM_HashAlgType; +/**@}*/ + + +/** + * @name definitions for HSM_ShaAlgType + * + */ +/**@{*/ +/** + * @brief SHA160 algorithm value for type "HSM_ShaAlgType" + * @note it's the so-called SHA1 + */ +#define HSM_SHA_160 (1U) + +/** + * @brief SHA224 algorithm value for type "HSM_ShaAlgType" + * @note it's the so-called SHA2-224 + */ +#define HSM_SHA_224 (2U) + +/** + * @brief SHA256 algorithm value for type "HSM_ShaAlgType" + * @note it's the so-called SHA2-256 + */ +#define HSM_SHA_256 (3U) + +/** + * @brief SHA384 algorithm value for type "HSM_ShaAlgType" + * @note it's the so-called SHA2-384 + */ +#define HSM_SHA_384 (4U) + +/** + * @brief SHA512 algorithm value for type "HSM_ShaAlgType" + * @note it's the so-called SHA2-512 + */ +#define HSM_SHA_512 (5U) + +/** + * @brief SHA512/224 algorithm value for type "HSM_ShaAlgType" + * @note it's the so-called SHA2-512/224 + */ +#define HSM_SHA_512_224 (6U) + +/** + * @brief SHA512/256 algorithm value for type "HSM_ShaAlgType" + * @note it's the so-called SHA2-512/256 + */ +#define HSM_SHA_512_256 (7U) + +/** + * @brief type definition for SHA algorithm + * refer to HSM_SHA_160,HSM_SHA_224,HSM_SHA_256,HSM_SHA_384,HSM_SHA_512,HSM_SHA_512_224,HSM_SHA_512_256 + */ +typedef uint32_t HSM_ShaAlgType; +/**@}*/ + + +/** + * @name definitions for HSM_HfamMacType + * + */ +/**@{*/ +/** + * @brief SMAC mode value for type "HSM_HfamMacType" + * + */ +#define HSM_HFAM_MAC_SMAC (0U) + +/** + * @brief HMAC mode value for type "HSM_HfamMacType" + * + */ +#define HSM_HFAM_MAC_HMAC (1U) + +/** + * @brief SM3/MD5/SHA can generate MAC, use this to select the type of MAC + * SMAC refer to HSM_HFAM_MAC_SMAC + * HMAC refer to HSM_HFAM_MAC_HMAC + */ +typedef uint32_t HSM_HfamMacType; +/**@}*/ + + +/** + * @brief SHA/MD5/SM3 context information used by driver when call specific API + * + */ +typedef struct +{ + HSM_BoolType bGenerateMacEn; /*!< whether generate MAC */ + HSM_HfamMacType eMacType; /*!< if enable generating MAC, this should configure */ + uint32_t *pKeyData; /*!< key to generate MAC, if enable generating MAC, this should configure */ + uint32_t u32KeyByteCnt; /*!< the byte count of key data */ + uint32_t u32GenerateMacByteCnt; /*!< the byte count of MAC data output */ + + uint32_t u32InputDataByteCnt; /*!< the byte count of input data */ + const uint32_t *pInputData; /*!< point to the input data */ +} HSM_SmsCfgType; /* sms is short for sha/md5/sm3 */ + +/** + * @brief SHA context information used by driver when call specific API + * + */ +typedef HSM_SmsCfgType HSM_ShaCtxType; + +/** + * @brief type definition for driver to store information + * + */ +typedef struct +{ + uint32_t aResult[0x10]; /*!< store the sha result, max size 0x10 is for SHA512 */ + uint32_t u32ResultU32Cnt; /*!< store the result uint32_t count, it's set by driver */ +} HSM_ShaResultBufType; + +/** + * @brief SHA information used by driver when call specific API + * + */ +typedef struct +{ + HSM_ShaAlgType eAlg; /*!< select sha algorithm type */ + HSM_ShaCtxType tCfg; /*!< sha algorithm parameter set by user */ + HSM_ShaResultBufType *pResult; /*!< point to the memory that HSM core to write result */ +} HSM_ShaType; + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + HSM_ShaType tCfg; /*!< sha algorithm parameter set by user */ +} HSMCom_ShaType; + +/** + * @brief SHA information used by driver when call specific API + * + */ +typedef struct +{ + HSM_ShaAlgType eAlg; /*!< select sha algorithm type */ + HSM_ShaCtxType tCfg; /*!< sha algorithm parameter set by user */ + uint8_t *pResult; /*!< point to the memory that HSM core to write result */ + HSM_DataFormatType eInputFmt; /*!< input data organized format,uint8_t array or uint32_t array */ + HSM_DataFormatType eOutputFmt; /*!< output data organized format,uint8_t array or uint32_t array */ +} HSM_Sha2Type; + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout Millisecond count, max 916000ms, if set to 0, means 1000ms */ + HSM_Sha2Type tCfg; /*!< sha algorithm parameter set by user */ +} HSMCom_Sha2Type; + +typedef struct +{ + HSM_ShaAlgType eAlg; /*!< select sha algorithm type */ + HSM_ShaCtxType tCfg; /*!< sha algorithm parameter set by user */ + uint32_t (*pResult)[18]; /*!< point to the memory that HSM core to write result */ +} HSM_ScatterHashType; + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout Millisecond count, max 916000ms, if set to 0, means 1000ms */ + HSM_ScatterHashType tCfg; /*!< sha algorithm parameter set by user */ +} HSMCom_ScatterHashType; +/* ------------------------------------------------------------------------------- */ +typedef struct { + uint32_t u32KeyType; + uint32_t u32KeySel; + uint32_t *pKeyData; +} HSM_AesmKeyCfgType; + +typedef struct { + HSM_AesmKeyCfgType *pKeyCfg; + uint32_t u32KeyCfgEn; + uint32_t u32AesMode; + uint32_t u32AesAs; + uint32_t u32AesEncDecrypt; + uint32_t u32EngSel; + uint32_t u32AhbEn; + uint32_t u32IcvEn; + uint32_t u32DataLen; + uint32_t u32IcvLen; + uint32_t u32AadLen; + uint32_t *pInput; + uint32_t *pOutput; + uint32_t *pIvData; + uint32_t u32DbgWait; + uint32_t u32IvLen; +} HSM_AesmHwEntryCfgType; + +typedef struct { + HSM_AesmHwEntryCfgType tCfg; + HSM_AesmKeyCfgType tKeyCfg; + uint32_t (*pCtx)[16]; +} HSM_AesmRawApiType; + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout Millisecond count, max 916000ms, if set to 0, means 1000ms */ + uint32_t u32UserKeyId; + HSM_AesmRawApiType tCfg; /*!< algorithm parameter set by user */ +} HSMCom_AesmRawApiType; + +/* ------------------------------------------------------------------------------- */ +typedef struct { + uint32_t u32Flags; + uint32_t *pKeyData; + uint32_t *pMacOut; + uint32_t u32MacOutBufSz; + uint32_t *aData[8]; + uint32_t aDataSize[8]; +} HSM_ScatterMacType; + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout Millisecond count, max 916000ms, if set to 0, means 1000ms */ + uint32_t u32UserKeyId; + HSM_ScatterMacType tCfg; /*!< algorithm parameter set by user */ +} HSMCom_ScatterMacType; + + +/* ------------------------------------------------------------------------------- */ +/** + * @name definitions for HSM_DrvEccCurvePrmIndexType + * + */ +/**@{*/ +/** + * @brief ECC curve NIST SECP224R1 value for type "HSM_DrvEccCurvePrmIndexType" + * + */ +#define HSM_DRV_ECC_CURVE_PRM_IDX_SECP224R1 (0U) + +/** + * @brief ECC curve NIST SECP256R1 value for type "HSM_DrvEccCurvePrmIndexType" + * + */ +#define HSM_DRV_ECC_CURVE_PRM_IDX_SECP256R1 (1U) + +/** + * @brief ECC curve NIST SECP384R1 value for type "HSM_DrvEccCurvePrmIndexType" + * + */ +#define HSM_DRV_ECC_CURVE_PRM_IDX_SECP384R1 (2U) + +/** + * @brief ECC curve NIST SECP521R1 value for type "HSM_DrvEccCurvePrmIndexType" + * + */ +#define HSM_DRV_ECC_CURVE_PRM_IDX_SECP521R1 (3U) + +/** + * @brief ECC curve NIST SECP224R1_FIX value for type "HSM_DrvEccCurvePrmIndexType" + * + */ +#define HSM_DRV_ECC_CURVE_PRM_IDX_SECP224R1_FIX (4U) + + +/** + * @brief max count of ECC curve supported for type "HSM_DrvEccCurvePrmIndexType" + * + */ +#define HSM_DRV_ECC_CURVE_PRM_IDX_MAX (5U) + +/** + * @brief type definition for ECC curve data that defined by NIST + * + */ +typedef uint32_t HSM_DrvEccCurvePrmIndexType; +/**@}*/ + +/** + * @brief ECC curve information used by driver when call specific API + * + */ +typedef struct +{ + const uint32_t *pP; /*!< ecc curve modulus */ + const uint32_t *pN; /*!< ecc curve order; size; the count of all possible EC points */ + const uint32_t *pA; /*!< the constant "a" in y^2 = x^3 + a*x + b (mod p) */ + const uint32_t *pB; /*!< the constant "b" in y^2 = x^3 + a*x + b (mod p) */ + const uint32_t *pGx; /*!< x of the curve generator point G {x, y} */ + const uint32_t *pGy; /*!< y of the curve generator point G {x, y} */ +} HSM_DrvEccCurveParamType; + +/** + * @brief ECC sign information used by driver when call specific API + * + */ +typedef struct +{ + uint32_t u32ByteCount; /*!< all the data size, it should contains all N data */ + HSM_DrvEccCurveParamType tCurve; /*!< ecc curve parameters */ + const uint32_t *pPrivateKey; /*!< private key */ + const uint32_t *pHashData; /*!< hash of the data to verify */ + + /* the following the sign output */ + uint32_t *pR; /*!< driver internal use this buffer to store the sign result R of the data to sign */ + uint32_t *pS; /*!< driver internal use this buffer to store the sign result S of the data to sign */ +} HSM_EccSignType; + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + uint32_t u32UserKeyID_PrivateKey; /*!< 0 means use key from HSM internal key space, otherwise would load key with KEYID from key space */ + uint32_t u32BitCnt; /*!< ECC parameter N bit count */ + HSM_DrvEccCurvePrmIndexType u32EccCurve; /*!< select hsm rom internal ecc curve parameters, if use user's self curve, set it to HSM_DRV_ECC_CURVE_PRM_IDX_MAX */ + HSM_EccSignType tCfg; /*!< ecc sign parameters */ +} HSMCom_EccSignType; + +/* ------------------------------------------------------------------------------- */ +/** + * @brief ECC verify information used by driver when call specific API + * + */ +typedef struct +{ + uint32_t u32DataByteCnt; /*!< the byte count of all ecc curve parameter */ + HSM_DrvEccCurveParamType tCurve; /*!< ecc curve parameters */ + const uint32_t *pkG_x; /*!< public key axis x */ + const uint32_t *pkG_y; /*!< public key axis y */ + const uint32_t *pHashData; /*!< hash of the data to verify */ + const uint32_t *pR; /*!< the sign result R of the data to verify */ + const uint32_t *pS; /*!< the sign result S of the data to verify */ +} HSM_EccVerifyType; +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + uint32_t u32UserKeyID_PublicKey; /*!< 0 means don't use key from HSM internal key space, otherwise would load key with KEYID from HSM */ + uint32_t u32BitCnt; /*!< ECC parameter N bit count */ + HSM_DrvEccCurvePrmIndexType u32EccCurve; /*!< select hsm rom internal ecc curve parameters, if use user's self curve, set it to HSM_DRV_ECC_CURVE_PRM_IDX_MAX */ + HSM_EccVerifyType tCfg; /*!< ecc verify parameters */ +} HSMCom_EccVerifyType; + +/* ------------------------------------------------------------------------------- */ +/** + * @brief SM2 key pair generation information used by driver when call specific API + * + */ +typedef struct +{ + uint32_t (*pPrivateKey)[8]; /*!< private key */ + uint32_t (*pPublicKey_X)[8]; /*!< the public key X */ + uint32_t (*pPublicKey_Y)[8]; /*!< the public key Y */ +} HSM_Sm2GenKeyPairType; + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + HSM_Sm2GenKeyPairType tCfg; /*!< sm2 generate key pair parameters */ +} HSMCom_Sm2GenKeyPairType; + +/* ------------------------------------------------------------------------------- */ +/** + * @brief SM2 encrypt information used by driver when call specific API + * + */ +typedef struct +{ + uint32_t u32SM2InputByteCnt; /*!< the length should be <= 32bytes */ + uint32_t *pSM2OutputByteCnt; /*!< driver internal will set output byte count in the memory this pointer point to */ + uint32_t *pInputData; /*!< length should be more than u32SM2InputByteCnt, and must be 4bytes align */ + uint32_t (*pPublicKey_x)[8]; /*!< public key axis x data */ + uint32_t (*pPublicKey_y)[8]; /*!< public key axis y data */ + uint32_t *pOutputData; /*!< length should be more than u32SM2InputByteCnt+97, and must be 4bytes align */ +} HSM_Sm2EncryptType; + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + uint32_t u32UserKeyID_PublicKey; /*!< 0 means don't use key from HSM internal key space, otherwise would load key with KEYID from HSM */ + HSM_Sm2EncryptType tCfg; /*!< sm2 encrypt parameters */ +} HSMCom_Sm2EncryptType; + +/* ------------------------------------------------------------------------------- */ +/** + * @brief SM2 decrypt information used by driver when call specific API + * + */ +typedef struct +{ + uint32_t u32SM2InputByteCnt; /*!< the length should be <= 129bytes */ + uint32_t *pSM2OutputByteCnt; /*!< driver internal will set output byte count in the memory this pointer point to */ + uint32_t *pInputData; /*!< length should be more than u32SM2InputByteCnt, and must be 4bytes align */ + uint32_t (*pPrivateKey)[8]; /*!< private key */ + uint32_t *pOutputData; /*!< length should be more than u32SM2InputByteCnt-97, and must be 4bytes align */ +} HSM_Sm2DecryptType; + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + uint32_t u32UserKeyID_PrivateKey; /*!< 0 means don't use key from HSM internal key space, otherwise would load key with KEYID from HSM */ + HSM_Sm2DecryptType tCfg; +} HSMCom_Sm2DecryptType; + +/* ------------------------------------------------------------------------------- */ +/** + * @brief SM2 sign information used by driver when call specific API + * + */ +typedef struct +{ + HSM_BoolType bUseDefaultID; /*!< TRUE means use default ID. FALSE means use specific ID with "pInputData_ID" and "u32SM2InputIDByteCnt" params. */ + HSM_BoolType bHashInput; /*!< TRUE means process hash message. FALSE means process raw M message */ + uint32_t u32SM2InputMByteCnt; /*!< the length should be <= 32bytes */ + uint32_t u32SM2InputIDByteCnt; /*!< the length should be <= 32bytes note: If "bUseDefaultID" is FALSE, would use this specific ID length with byte unit. */ + uint32_t *pInputData_ID; /*!< note: If "bUseDefaultID" is FALSE, would use this specific ID. length should be more than u32SM2InputIDByteCnt, and must be 4bytes align */ + uint32_t *pInputData_MOrHash; /*!< length should be more than u32SM2InputMOrHashByteCnt, and must be 4bytes align */ + uint32_t (*pPrivateKey)[8]; /*!< private key */ + uint32_t (*pPublicKey_X)[8]; /*!< If bHashInput is false, the pointer must be not NULL */ + uint32_t (*pPublicKey_Y)[8]; /*!< If bHashInput is false, the pointer must be not NULL */ + uint32_t (*pOutputData_R)[8]; /*!< sign result R */ + uint32_t (*pOutputData_S)[8]; /*!< sign result S */ +} HSM_Sm2SignType; + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + uint32_t u32UserKeyID_PublicKey; /*!< 0 means don't use key from HSM internal key space, otherwise would load key with KEYID from HSM */ + uint32_t u32UserKeyID_PrivateKey; /*!< 0 means don't use key from HSM internal key space, otherwise would load key with KEYID from HSM */ + HSM_Sm2SignType tCfg; +} HSMCom_Sm2SignType; + +/* ------------------------------------------------------------------------------- */ +/** + * @brief SM2 verify information used by driver when call specific API + * + */ +typedef struct +{ + HSM_BoolType bUseDefaultID; /*!< TRUE means use default ID. FALSE means use specific ID with "pInputData_ID" and "u32SM2InputIDByteCnt" params. */ + HSM_BoolType bHashInput; /*!< TRUE means process hash message. FALSE means process raw M message */ + uint32_t u32SM2InputMByteCnt; /*!< the length should be <= 32bytes */ + uint32_t u32SM2InputIDByteCnt; /*!< the length should be <= 32bytes note: If "bUseDefaultID" is FALSE, would use this specific ID length with byte unit. */ + uint32_t *pInputData_MOrHash; /*!< length should be more than u32SM2InputMOrHashByteCnt, and must be 4bytes align */ + uint32_t *pInputData_ID; /*!< note: If "bUseDefaultID" is FALSE, would use this specific ID. length should be more than u32SM2InputIDByteCnt, and must be 4bytes align */ + uint32_t (*pInputData_R)[8]; /*!< the sign result R */ + uint32_t (*pInputData_S)[8]; /*!< the sign result S */ + uint32_t (*pPublicKey_X)[8]; /*!< the public key X */ + uint32_t (*pPublicKey_Y)[8]; /*!< the public key Y */ +} HSM_Sm2VerifyType; + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + uint32_t u32UserKeyID_PublicKey; /*!< 0 means don't use key from HSM internal key space, otherwise would load key with KEYID from HSM */ + HSM_Sm2VerifyType tCfg; /*!< sm2 verify parameters */ +} HSMCom_Sm2VerifyType; + +/* ------------------------------------------------------------------------------- */ +/** + * @brief SM2 ZA generation information used by driver when call specific API + * + */ +typedef struct +{ + HSM_BoolType bUseDefaultID; /*!< TRUE means use default ID. FALSE means use specific ID with "pInputData_ID" and "u32SM2InputIDByteCnt" params. */ + uint32_t u32SM2InputIDByteCnt;/*!< the length should be <= 32bytes note: If "bUseDefaultID" is FALSE, would use this specific ID length with byte unit.*/ + uint32_t (*pPublicKey_X)[8]; + uint32_t (*pPublicKey_Y)[8]; + uint32_t *pInputData_ID; /*!< note: If "bUseDefaultID" is FALSE, would use this specific ID. length should be more than u32SM2InputIDByteCnt, and must be 4bytes align */ + uint32_t (*pOutputData_Za)[8]; /*!< Length is 32bytes, SM3 always output 256bit */ +} HSM_Sm2GenZaType; + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + uint32_t u32UserKeyID_PublicKey; /*!< 0 means don't use key from HSM internal key space, otherwise would load key with KEYID from HSM */ + HSM_Sm2GenZaType tCfg; +} HSMCom_Sm2GenZaType; +/* ------------------------------------------------------------------------------- */ +/** + * @brief SM2 HASH generation information used by driver when call specific API + * + */ +typedef struct +{ + uint32_t u32InputDataByteCnt; /*!< input data byte count */ + uint32_t *pInputData_ZaAndM; /*!< note: it should be ZA||M, the length should be more than u32InputDataByteCnt, and must be 4bytes align */ + uint32_t (*pOutputData_Hash)[8]; /*!< Length is 32bytes, SM3 always output 256bit */ +} HSM_Sm2GenHashType; + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + HSM_Sm2GenHashType tCfg; +} HSMCom_Sm2GenHashType; +/* ------------------------------------------------------------------------------- */ +/** + * @name definitions for HSM_Sm4KeyType + * + */ +/**@{*/ +/** + * @brief vendor key value for type "HSM_Sm4KeyType" + * + * HSM hardware support accessing the SM4 key stored in nvr flash directly, + * chip user should program the key in flash already. + * This way don't need software read data and write it to some place, + * hardware will read the data itself automatically. + */ +#define HSM_SM4_KEY_CHIP_VENDOR_IFR (0U) /* key has existed in Flash IFR, it provided by chip, not changeable */ + +/** + * @brief driver user's new key value for type "HSM_Sm4KeyType" + * + * HSM use the key passed by driver API user. + */ +#define HSM_SM4_KEY_NEW (1U) /* user should provide the new key */ +typedef uint32_t HSM_Sm4KeyType; +/**@}*/ + +/** + * @name definitions for HSM_Sm4EnDecryptAlgType + * + */ +/**@{*/ +/** + * @brief SM4 CTR mode value for type "HSM_Sm4EnDecryptAlgType" + * + */ +#define HSM_SM4_CTR (0U) + +/** + * @brief SM4 CBC mode value for type "HSM_Sm4EnDecryptAlgType" + * + */ +#define HSM_SM4_CBC (1U) + +/** + * @brief SM4 ECB mode value for type "HSM_Sm4EnDecryptAlgType" + * + */ +#define HSM_SM4_ECB (2U) + +/** + * @brief SM4 CFB mode value for type "HSM_Sm4EnDecryptAlgType" + * + */ +#define HSM_SM4_CFB (3U) + +/** + * @brief SM4 OFB mode value for type "HSM_Sm4EnDecryptAlgType" + * + */ +#define HSM_SM4_OFB (4U) + +/** + * @brief type definition for SM4 encrypt/decrypt mode + * + * HSM support CTR/CBC/ECB/CFB/OFB mode, driver api use this to select the encrypt/decrypt mode. + */ +typedef uint32_t HSM_Sm4EnDecryptAlgType; +/**@}*/ + +/** + * @brief SM4 encrypt/decrypt information used by driver when call specific API + * + */ +typedef struct +{ + HSM_Sm4KeyType eUseKeyType; /*!< the key source:vendor key programmed in nvr flash or new key in software */ + const uint32_t (*pKeyAddr)[4]; /*!< when eUseKeyType is HSM_SM4_KEY_NEW, this MUST configure */ + HSM_Sm4EnDecryptAlgType eSm4Alg; /*!< SM4 encrypt/decrypt mode */ + + const uint32_t *pDataInput; /*!< address should align with 4bytes */ + uint32_t u32InputByteCnt; /*!< 128bit(16Bytes) align */ + uint32_t *pDataOutput; /*!< address should align with 4bytes */ + uint32_t u32OutputMemSize; /*!< the output data buffer "pDataOutput" size, should >= "u32InputByteCnt" */ + + uint32_t (*pIvData)[4]; /*!< 128bit(16Bytes) iv(initialization vector) data array, ECB not need configure this */ +} HSM_Sm4EnDecryptType; + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + uint32_t u32UserKeyID; /*!< 0 means don't use key from HSM internal key space, otherwise would load key with KEYID from HSM */ + HSM_Sm4EnDecryptType tCfg; +} HSMCom_Sm4EnDecryptType; + +typedef HSMCom_Sm4EnDecryptType HSMCom_Sm4DecryptType; + +typedef HSMCom_Sm4EnDecryptType HSMCom_Sm4EncryptType; + +typedef struct { + HSMCom_Sm4EncryptType *pParam; + uint32_t u32Remain; +} HSMWrap_Sm4EncryptType; +/* ------------------------------------------------------------------------------- */ +/** + * @brief ECC encrypt information used by driver when call specific API + * + */ +typedef struct +{ + uint32_t u32ByteCount; /*!< all the data size, it should contains all N data */ + + const uint32_t *pCoeffi_A; /*!< the constant "a" in y^2 = x^3 + a*x + b (mod p), all data 8 bytes aligned */ + const uint32_t *pCoeffi_B; /*!< the constant "b" in y^2 = x^3 + a*x + b (mod p) */ + const uint32_t *pP; /*!< ecc curve modulus */ + const uint32_t *pN; /*!< ecc curve order; size; the count of all possible EC points */ + const uint32_t *pOtherSidePublicKey_x; /*!< decrypt side's public key axis x data */ + const uint32_t *pOtherSidePublicKey_y; /*!< decrypt side's public key axis y data */ + const uint32_t *pPrivateKey; /*!< encrypt side private key */ + const uint32_t *pPlainData; /*!< data to be encrypted, its byte count should be same as u32ByteCount */ + + uint32_t *pEncryedData; /*!< driver internal write the result to this buffer */ +} HSM_EccEasyEncryType; + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + uint32_t u32UserKeyID_PrivateKey;/*!< 0 means don't use key from HSM internal key space, otherwise would load key with KEYID from HSM */ + uint32_t u32UserKeyID_PublicKey; /*!< 0 means don't use key from HSM internal key space, otherwise would load key with KEYID from HSM */ + uint32_t u32BitCnt; + HSM_DrvEccCurvePrmIndexType u32EccCurve; + HSM_EccEasyEncryType tCfg; +} HSMCom_EccEasyEncryType; + +/* ------------------------------------------------------------------------------- */ +/** + * @brief ECC decrypt information used by driver when call specific API + * + */ +typedef struct +{ + uint32_t u32ByteCount; /*!< all the data size, it should contains all N data */ + const uint32_t *pCoeffi_A; /*!< the constant "a" in y^2 = x^3 + a*x + b (mod p), all data 8 bytes aligned */ + const uint32_t *pCoeffi_B; /*!< the constant "b" in y^2 = x^3 + a*x + b (mod p) */ + const uint32_t *pP; /*!< ecc curve modulus */ + const uint32_t *pN; /*!< ecc curve order; size; the count of all possible EC points */ + const uint32_t *pOtherSidePublicKey_x; /*!< encrypt side's public key axis x data */ + const uint32_t *pOtherSidePublicKey_y; /*!< encrypt side's public key axis y data */ + const uint32_t *pPrivateKey; /*!< decrypt side private key */ + const uint32_t *pEncryedData; /*!< data to be decrypted, its byte count should be same as u32ByteCount */ + uint32_t *pPlainData; /*!< driver internal write the result to this buffer */ +} HSM_EccEasyDecryType; + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + uint32_t u32UserKeyID_PrivateKey; /*!< 0 means don't use key from HSM internal key space, otherwise would load key with KEYID from HSM */ + uint32_t u32UserKeyID_PublicKey; /*!< 0 means don't use key from HSM internal key space, otherwise would load key with KEYID from HSM */ + uint32_t u32BitCnt; + HSM_DrvEccCurvePrmIndexType u32EccCurve; + HSM_EccEasyDecryType tCfg; +} HSMCom_EccEasyDecryType; +/* ------------------------------------------------------------------------------- */ +/** + * @brief ECC generate key pair information used by driver when call specific API + * + */ +typedef struct +{ + uint32_t u32ByteCount; /*!< all the data size, it should contains all N data */ + HSM_DrvEccCurveParamType tEccParam; + uint32_t *pPrivateKey; /*!< decrypt side private key */ + uint32_t *pPublicKey_x; /*!< encrypt side's public key axis x data */ + uint32_t *pPublicKey_y; /*!< encrypt side's public key axis y data */ +} HSM_EccKeyPairGenType; + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + uint32_t u32Bitcnt; /*!< 0 means don't use key from HSM internal key space, otherwise would load key with KEYID from HSM */ + HSM_DrvEccCurvePrmIndexType u32EccCurve; + HSM_EccKeyPairGenType tCfg; +} HSMCom_EccKeyPairGenType; +/* ------------------------------------------------------------------------------- */ + + +#define HSM_ECC_CALC_PADD 0xFC73F800 +#define HSM_ECC_CALC_PDBL 0xFC73F801 +#define HSM_ECC_CALC_PMUL 0xFC73F802 +#define HSM_ECC_CALC_PCHK 0xFC73F803 + +/** + * @brief ECC point calclulate used by driver when call specific API + * + */ +typedef struct +{ + uint32_t u32ByteCount; /*!< all the data size, it should contains all N data */ + const uint32_t *pCoeffi_A; /*!< address should align with 4bytes, the constant "a" in y^2 = x^3 + a*x + b (mod p), all data 8 bytes aligned */ + const uint32_t *pCoeffi_B; /*!< address should align with 4bytes, the constant "b" in y^2 = x^3 + a*x + b (mod p) */ + const uint32_t *pP; /*!< address should align with 4bytes, ecc curve modulus */ + const uint32_t *pN; /*!< address should align with 4bytes, ecc curve order; size; the count of all possible EC points */ + const uint32_t *pP1x; /*!< address should align with 4bytes, encrypt side's public key axis x data */ + const uint32_t *pP1y; /*!< address should align with 4bytes, encrypt side's public key axis y data */ + const uint32_t *pE; /*!< address should align with 4bytes, decrypt side private key */ + const uint32_t *pP2x; /*!< address should align with 4bytes, data to be decrypted, its byte count should be same as u32ByteCount */ + uint32_t *pResultx; /*!< address should align with 4bytes, driver internal write the result to this buffer */ + uint32_t u32CalcType; + const uint32_t *pP2y; + uint32_t *pResulty; +} HSM_EccCalcType; + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout Millisecond count, max 916000ms, if set to 0, means 1000ms */ + uint32_t u32UserKeyID_E; /*!< 0 means don't use key from HSM internal key space, otherwise would load key with KEYID from HSM */ + uint32_t u32UserKeyID_P1; /*!< 0 means don't use key from HSM internal key space, otherwise would load key with KEYID from HSM */ + uint32_t u32BitCnt; /*!< ecc encrypt data bit count */ + HSM_DrvEccCurvePrmIndexType u32EccCurve; /*!< ecc curve */ + HSM_EccCalcType tCfg; /*!< ecc decrypt parameters */ +} HSMCom_EccCalcType; +/* ------------------------------------------------------------------------------- */ + +#define HSM_COM_REQUEST_AUTH_DATA_U32_CNT 8 +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + uint32_t (*pData)[HSM_COM_REQUEST_AUTH_DATA_U32_CNT]; +} HSMCom_RequestAuthType; +/* ------------------------------------------------------------------------------- */ +#define AUTH_CHECK_DATA_BYTE_CNT 32 +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + const uint32_t *pkG_x; + const uint32_t *pkG_y; + const uint32_t *pR; + const uint32_t *pS; + //For user code verify function + const uint32_t *pData; + uint32_t u32DataLength; +} HSMCom_LifeCycleChangeType; +/* ------------------------------------------------------------------------------- */ +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + uint32_t u32MailboxChannel; +} HSMCom_CancelJobType; +/* ------------------------------------------------------------------------------- */ +/** + * @name definitions for HSMCom_FirmwareLoadStatus + * + */ +/**@{*/ +/** + * @brief no firmware detected in flash status + * + */ +#define HSMCOM_FIRMWARE_LOAD_NONE (0u) + +/** + * @brief status value represents firmware is loading now + * + */ +#define HSMCOM_FIRMWARE_LOADING (1u) + +/** + * @brief status value represents firmware waiting user to trigger load in CM7 side + * + */ +#define HSMCOM_FIRMWARE_NEED_USER_LOAD (2u) + +/** + * @brief status value represents firmware is loaded successfully + * + */ +#define HSMCOM_FIRMWARE_LOAD_OK (3u) + +/** + * @brief status value represents firmware load fail + * + */ +#define HSMCOM_FIRMWARE_LOAD_FAIL (4u) + +typedef uint32_t HSMCom_FirmwareLoadStatus; +/**@}*/ + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + uint32_t u32Rng0CtrlAndNotFlag; // conf val, only ft mode, other mode REPO_COMMIT_ID + uint32_t u32Rng0CtrlOrFlag; // conf val,only ft mode, other mode REPO_BUILD_DATA + uint32_t u32FirmVersion; /*!< firmware version */ + uint32_t u32Rng1CtrlOrFlag; /*< FIX to 0x4d6f0000 */ + uint32_t u32BusClk; /*!< the hsm bus clock */ + uint32_t u32EntropyDelay0; + uint32_t u32FreqMax0; + uint32_t u32EntropyDelay1; + uint32_t u32FreqMax1; + HSMCom_FirmwareLoadStatus u32FirmwareLoadStatus; /*!< the status of loading firmware, IF >= 4 FAIL */ +} HSMCom_SelfTestType; +/* ------------------------------------------------------------------------------- */ + +#define HSMCOM_NVR_OTP_START_ADDR 0x04400400 +#define HSMCOM_NVR_OTP_END_ADDR 0x04401fff + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + uint32_t u32Addr; // 0x04400400 - 0x04401fff, 16bytes align + uint32_t aData[4]; +} HSMCom_NvrOtpType; +/* ------------------------------------------------------------------------------- */ +/** + * @name definitions for KeyManager_BoolType + * + */ +/**@{*/ +#define KEYMANAGER_FALSE (0u) +#define KEYMANAGER_TRUE (1u) +typedef uint32_t KeyManager_BoolType; +/**@}*/ + +/** + * @name definitions for KEYMANAGER_KeyExportType + * + */ +/**@{*/ +#define KEYMANAGER_KEY_EXPORT_FORBIRD (0u) +#define KEYMANAGER_KEY_EXPORT_PLAIN (1u) +#define KEYMANAGER_KEY_EXPORT_CIPHER (2u) +#define KEYMANAGER_KEY_EXPORT_MAX (3u) +typedef uint32_t KEYMANAGER_KeyExportType; +/**@}*/ + +/** + * @name definitions for KeyManager_UserKeyEnDecryType + * + */ +/**@{*/ +#define KEYMANAGER_ENDECRY_NONE (0u)/* For plain key, no need to encrypt or decrypt. */ +#define KEYMANAGER_ENDECRY_AES256 (1u) +#define KEYMANAGER_ENDECRY_SM4 (2u) +#define KEYMANAGER_ENDECRY_MAX (3u) +typedef uint32_t KeyManager_UserKeyEnDecryType; +/**@}*/ + +/** + * @name definitions for KeyManager_UserKeyTypeType + * + */ +/**@{*/ +#define KEYMANAGER_USER_KEY_TYPE_NONE (0u)//not configure the key type, HSM shall not check if the key type is matched with de/encrypt ALG. +#define KEYMANAGER_USER_KEY_TYPE_AES (1u) +#define KEYMANAGER_USER_KEY_TYPE_SM4 (2u) +#define KEYMANAGER_USER_KEY_TYPE_ECC_PRIVATE (3u) +#define KEYMANAGER_USER_KEY_TYPE_ECC_PUBLIC (4u) +#define KEYMANAGER_USER_KEY_TYPE_SM2_PRIVATE (5u) +#define KEYMANAGER_USER_KEY_TYPE_SM2_PUBLIC (6u) +#define KEYMANAGER_USER_KEY_TYPE_RSA_E (7u) +#define KEYMANAGER_USER_KEY_TYPE_RSA_N (8u) +#define KEYMANAGER_USER_KEY_TYPE_XMAC (9u) +#define KEYMANAGER_USER_KEY_TYPE_CMAC (10u) +#define KEYMANAGER_USER_KEY_TYPE_CCM (11u) +#define KEYMANAGER_USER_KEY_TYPE_GCM (12u) +typedef uint32_t KeyManager_UserKeyTypeType; +/**@}*/ + +/** + * @name definitions for KEYMANAGER_EnDecryAlgType + * + */ +/**@{*/ + +#define KEYMANAGER_ENDECRY_ALG_CTR (0u) +#define KEYMANAGER_ENDECRY_ALG_CBC (1u) +#define KEYMANAGER_ENDECRY_ALG_ECB (2u) +#define KEYMANAGER_ENDECRY_ALG_CFB (3u) +#define KEYMANAGER_ENDECRY_ALG_OFB (4u) +#define KEYMANAGER_ENDECRY_ALG_MAX (5u) + +typedef uint32_t KEYMANAGER_EnDecryAlgType; +/**@}*/ + +typedef struct +{ + uint32_t *pDataAddr; + uint32_t *pDataLength; + uint32_t u32KeyID; + KeyManager_UserKeyEnDecryType eEncryType; //indicate if the key exported is need to be encrypted + //if the key exported need to be encrypted, below Param need to configure + uint32_t u32EncryKeyID; //0 means use USRK as encrykey, otherwise load decrykey with KEYID from hsm key space + KEYMANAGER_EnDecryAlgType eAlgType; + uint32_t (*pIV)[4]; + uint32_t *pCiperKeyLength; +} KeyManager_ExportUserKeyType; + +typedef struct +{ + KeyManager_BoolType bStoreInFlash; //true means store the key in flash, false means store the key in ram + KEYMANAGER_KeyExportType eExportType; + uint32_t *pDataAddr; //the address of key imported + uint32_t u32DataLength; // the length of key imported + uint32_t *pKeyID; + KeyManager_UserKeyEnDecryType eDecryType; //indicate if the key imported is plain + //if the key imported is encrypted, below Param need to configure + uint32_t u32DecryKeyID; //0 means use USRK as decrykey, otherwise load decrykey with KEYID from hsm key space + KeyManager_UserKeyTypeType eUserKeyType; + KEYMANAGER_EnDecryAlgType eAlgType; + uint32_t (*pIV)[4]; +} KeyManager_ImportUserKeyType; + +#define KEYMANAGER_GEN_KEYPAIR_SM2 (0u) +#define KEYMANAGER_GEN_KEYPAIR_ECC (1u) +#define KEYMANAGER_GEN_KEYPAIR_MAX (2u) +typedef uint32_t KeyManager_GeNKeyPairType; + +typedef struct +{ + KeyManager_GeNKeyPairType eKeyPairType; + KEYMANAGER_KeyExportType eExportType; + KeyManager_BoolType bStoreInFlash; + uint32_t *pPrivateKeyID; + uint32_t *pPublicKeyID; +} KeyManager_GenAsymmetricUserKeyType; + +typedef struct +{ + KEYMANAGER_KeyExportType eExportType; + KeyManager_BoolType bStoreInFlash; + uint32_t u32KeyLength; + uint32_t *pKeyID; +} KeyManager_GenSymmetricUserKeyType; + +typedef struct +{ + union{ + KeyManager_GenAsymmetricUserKeyType tGenKeyPairCfg; + KeyManager_GenSymmetricUserKeyType tGenKeyCfg; + }; + HSM_DrvEccCurveParamType tEccParam; //only for generate ECC key pair + uint32_t u32EccBitLength; //only for generate ECC key pair + HSM_BoolType bGenSymmetricKey; + HSM_DrvEccCurvePrmIndexType u32EccCurve; +} HSMCom_GenUserKeyType; + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + union + { + uint32_t u32RevokeUserKeyID;/* For revoke UserKey function*/ + KeyManager_ImportUserKeyType tImportUserKeyCfg;/* For import User Key function*/ + KeyManager_ExportUserKeyType tExportUserKeyCfg;/* For export user key function */ + HSMCom_GenUserKeyType tGenUserKeyCfg;/* For generate key pair function */ + }; +} HSMCom_UserKeyManageType; +/* ------------------------------------------------------------------------------- */ +typedef struct +{ + //For Key Flash Space + KeyManager_BoolType bCriticalError; + KeyManager_BoolType bKMLackKeyHeadSpace; + KeyManager_BoolType bKMLackKeyDataSpace; + uint32_t u32KeyHeadRestSpace; //The unit is number + uint32_t u32KeyDataRestSpace; //The unit is page + uint32_t u32InvalidKeyCounter; + //For Key ram space + uint32_t u32KeyRamSpaceUsed; +} KeyManager_SpaceStatusType; + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + KeyManager_SpaceStatusType *pKMSpaceStatus; +} HSMCom_KeySpaceStatusType; +/* ------------------------------------------------------------------------------- */ + +/** + * @name definitions for HSM_AesKeyType + * + */ +/**@{*/ + +/** + * @brief vendor key value for type "HSM_AesKeyType" + * + * HSM hardware support accessing the aes key stored in nvr flash directly, + * chip user should program the key in flash already. + * This way don't need software read data and write it to some place, + * hardware will read the data itself automatically. + */ +#define HSM_AES_KEY_CHIP_VENDOR_IFR (0U) /* key has existed in Flash IFR, it provided by chip hardware, not changeable */ + +/** + * @brief driver user's new key value for type "HSM_AesKeyType" + * + * HSM use the key passed by driver API user. + */ +#define HSM_AES_KEY_NEW (1U) /* user should provide the new key */ + +/** + * @brief type definition for the key source + * + * key from the nvr refer to HSM_AES_KEY_CHIP_VENDOR_IFR + * key from driver user's parameters refer to HSM_AES_KEY_NEW + */ +typedef uint32_t HSM_AesKeyType; +/**@}*/ + +/** + * @name definitions for HSM_AesKeyBitCntType + * + */ +/**@{*/ + +/** + * @brief AES128 key type value for type "HSM_AesKeyBitCntType" + * + */ +#define HSM_AES_KEY128 (0U) + +/** + * @brief AES192 key type value for type "HSM_AesKeyBitCntType" + * + */ +#define HSM_AES_KEY192 (1U) + +/** + * @brief AES256 key type value for type "HSM_AesKeyBitCntType" + * + */ +#define HSM_AES_KEY256 (2U) + +/** + * @brief type definition for AES key + * + * HSM support AES128/192/256, driver api use this to select the algorithm. + */ +typedef uint32_t HSM_AesKeyBitCntType; +/**@}*/ + + +/** + * @brief key information used by AES when use one key in software + * + */ +typedef struct +{ + HSM_AesKeyBitCntType eKeyType; /*!< the key bit count, which determine the AES algorithm type */ + const uint32_t *pKeyAddr; /*!< the key data pointer, the address should 4bytes align, the buffer array should declared by uint32_t */ +} HSM_AesNewKeyInfType; + +/** + * @brief key information used by AES when use one key in nvr flash + * + */ +typedef struct +{ + HSM_AesKeyBitCntType eKeyType; /*!< the key bit count, which determine the AES algorithm type */ +} HSM_AesVendorKeyInfType; + +/** + * @name definitions for HSM_AesEnDecryptAlgType + * + */ +/**@{*/ + +/** + * @brief AES CTR mode value for type "HSM_AesEnDecryptAlgType" + * + */ +#define HSM_AES_CTR (0U) + +/** + * @brief AES CBC mode value for type "HSM_AesEnDecryptAlgType" + * + */ +#define HSM_AES_CBC (1U) + +/** + * @brief AES ECB mode value for type "HSM_AesEnDecryptAlgType" + * + */ +#define HSM_AES_ECB (2U) + +/** + * @brief AES CFB mode value for type "HSM_AesEnDecryptAlgType" + * + */ +#define HSM_AES_CFB (3U) + +/** + * @brief AES OFB mode value for type "HSM_AesEnDecryptAlgType" + * + */ +#define HSM_AES_OFB (4U) + +/** + * @brief type definition for AES encrypt/decrypt mode + * + * HSM support CTR/CBC/ECB/CFB/OFB mode, driver api use this to select the encrypt/decrypt mode. + */ +typedef uint32_t HSM_AesEnDecryptAlgType; +/**@}*/ + +/** + * @brief AES encrypt/decrypt information used by driver when call specific API + * + */ +typedef struct +{ + HSM_AesKeyType eUseKeyType; /*!< the key source:vendor key programmed in nvr flash or new key in software */ + HSM_AesNewKeyInfType tNewKeyInf; /*!< when eUseKeyType is HSM_AES_KEY_NEW, this MUST configure */ + HSM_AesVendorKeyInfType tVendorKeyInf; /*!< when eUseKeyType is HSM_AES_KEY_CHIP_VENDOR_IFR, this MUST configure */ + HSM_AesEnDecryptAlgType eAesAlg; /*!< encrypt/decrypt mode */ + + const uint32_t *pDataInput; /*!< address should align with 4bytes */ + uint32_t u32InputByteCnt; /*!< 128bit(16Bytes) align */ + uint32_t *pDataOutput; /*!< address should align with 4bytes */ + uint32_t u32OutputMemSize; /*!< the output data buffer "pDataOutput" size, should >= "u32InputByteCnt" */ + + uint32_t (*pIvData)[4]; /*!< 128bit(16Bytes) iv(initialization vector) data array, ECB not need configure this */ + +} HSM_AesEnDecryptType; + +/** + * @brief Flexiable AES zero padding type for type "HSM_FlexAesPadType" + * if input data is not aligned with 16bytes, this configuration will make append byte data 0 to keep 16bytes align. + */ +#define HSM_FLEXAES_PAD_ZERO 0u + +/** + * @brief Flexiable AES PKCS7 padding type for type "HSM_FlexAesPadType" + * if input data is not aligned with 16bytes, this configuration will make append bytes by PKCS7 method to keep 16bytes align. + */ +#define HSM_FLEXAES_PAD_PKCS7 1u + +/** + * @brief Flexiable AES padding type definition + * if use zero padding, refer to HSM_FLEXAES_PAD_ZERO, after decrypt, user should remove the zero manually + * if use PKCS7 padding, refer to HSM_FLEXAES_PAD_PKCS7 + */ +typedef uint32_t HSM_FlexAesPadType; + +/* ------------------------------------------------------------------------------- */ +/** + * @brief AES hardware backend for AES for type "HSM_AesBackendType" + * + */ +#define HSM_AES_BACKEND_AES 0u + +/** + * @brief SM4 hardware backend for AES for type "HSM_AesBackendType" + * + */ +#define HSM_AES_BACKEND_SM4 1u + +/** + * @brief type definition for GCM's hardware backend + * AES backend refer to HSM_AES_BACKEND_AES + * SM4 backend refer to HSM_GCM_BACKEND_SM4 + */ +typedef uint32_t HSM_AesBackendType; + +/** + * @brief Flex AES encrypt/decrypt information used by driver when call specific API + * + */ +typedef struct +{ + HSM_AesKeyType eUseKeyType; /*!< the key source:vendor key programmed in nvr flash or new key in software */ + HSM_AesNewKeyInfType tNewKeyInf; /*!< when eUseKeyType is HSM_AES_KEY_NEW, this MUST configure */ + HSM_AesVendorKeyInfType tVendorKeyInf; /*!< when eUseKeyType is HSM_AES_KEY_CHIP_VENDOR_IFR, this MUST configure */ + HSM_AesEnDecryptAlgType eAesAlg; /*!< encrypt/decrypt mode */ + + const uint32_t *pDataInput; /*!< address should align with 4bytes */ + uint32_t u32InputByteCnt; /*!< 128bit(16Bytes) align */ + uint32_t *pDataOutput; /*!< address should align with 4bytes */ + uint32_t u32OutputMemSize; /*!< the output data buffer "pDataOutput" size, should >= "u32InputByteCnt" */ + + uint32_t (*pIvData)[4]; /*!< address should align with 4bytes, 128bit(16Bytes) iv(initialization vector) data array, ECB not need configure this */ + + uint32_t *pGenerateOutByteCnt; /*!< point to the uint32_t variable to store the result byte count, can't be NULL */ + + HSM_FlexAesPadType epad; + HSM_DataFormatType eInputFmt; + HSM_DataFormatType eOutputFmt; + HSM_AesBackendType eBackend; +} HSM_FlexAesEnDecryptType; + +/** + * @brief AES decrypt information used by driver when call specific API + * + */ +typedef HSM_AesEnDecryptType HSM_AesEncryptType; +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + uint32_t u32UserKeyID; /*!< 0 means don't use key from HSM internal key space, otherwise would load key with KEYID from HSM */ + HSM_AesEncryptType tCfg; /*!< aes parameters */ +} HSMCom_AesEncryptType; +/* ------------------------------------------------------------------------------- */ +/** + * @brief AES encrypt information used by driver when call specific API + * + */ +typedef HSM_AesEnDecryptType HSM_AesDecryptType; + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + uint32_t u32UserKeyID; /*!< 0 means don't use key from HSM internal key space, otherwise would load key with KEYID from HSM */ + HSM_AesDecryptType tCfg; /*!< AES decrypt parameters */ +} HSMCom_AesDecryptType; +/* ------------------------------------------------------------------------------- */ + +/** + * @brief Flex AES decrypt information used by driver when call specific API + * + */ +typedef HSM_FlexAesEnDecryptType HSM_FlexAesEncryptType; +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout Millisecond count, max 916000ms, if set to 0, means 1000ms */ + uint32_t u32UserKeyID; /*!< 0 means don't use key from HSM internal key space, otherwise would load key with KEYID from HSM */ + HSM_FlexAesEncryptType tCfg; /*!< aes parameters */ +} HSMCom_FlexAesEncryptType; +/* ------------------------------------------------------------------------------- */ +/** + * @brief AES encrypt information used by driver when call specific API + * + */ +typedef HSM_FlexAesEnDecryptType HSM_FlexAesDecryptType; + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout Millisecond count, max 916000ms, if set to 0, means 1000ms */ + uint32_t u32UserKeyID; /*!< 0 means don't use key from HSM internal key space, otherwise would load key with KEYID from HSM */ + HSM_FlexAesDecryptType tCfg; /*!< AES decrypt parameters */ +} HSMCom_FlexAesDecryptType; +/* ------------------------------------------------------------------------------- */ + +/** + * @brief CMAC/XMAC information used by driver when call specific API + * + */ + +#define HSM_XCMAC_BACKEND_AES 0u +#define HSM_XCMAC_BACKEND_SM4 1u + +typedef uint32_t HSM_XCMAC_BackendType; + +typedef struct +{ + HSM_AesKeyType eUseKeyType; /*!< fix to HSM_AES_KEY_NEW */ + HSM_AesNewKeyInfType tNewKeyInf; /*!< when eUseKeyType is HSM_AES_KEY_NEW, this MUST configure */ + HSM_AesVendorKeyInfType tVendorKeyInf; /*!< when eUseKeyType is HSM_AES_KEY_CHIP_VENDOR_IFR, this MUST configure */ + uint32_t u32GenMacByteCnt; /*!< XCMAC API generate MAC data, it's "u32GenMacByteCnt" size ICV data */ + HSM_BoolType bCheckMacEn; /*!< if enable this check, user should place the data after the input data, hsm will check the generated data and it, if fail, hsm generate a interrupt, and if user get hw status, will get a error status */ + const uint32_t *pDataInput; /*!< address should align with 4bytes */ + uint32_t u32InputByteCnt; /*!< 128bit(16Bytes) align */ + uint32_t *pDataOutput; /*!< address should align with 4bytes */ + uint32_t u32OutputMemSize; /*!< 4bytes align, the output data buffer "pDataOutput" size, should >= "u32GenMacByteCnt" */ +} HSM_XCMacType; + +/** + * @brief CMAC information used by driver when call specific API + * + */ +typedef HSM_XCMacType HSM_CMacType; + + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + uint32_t u32UserKeyID; /*!< 0 means don't use key from HSM internal key space, otherwise would load key with KEYID from HSM */ + HSM_CMacType tCfg; /*!< CMAC parameters */ +} HSMCom_CMacType; + +typedef struct +{ + HSM_AesKeyType eUseKeyType; /*!< fix to HSM_AES_KEY_NEW */ + HSM_AesNewKeyInfType tNewKeyInf; /*!< when eUseKeyType is HSM_AES_KEY_NEW, this MUST configure */ + HSM_AesVendorKeyInfType tVendorKeyInf; /*!< when eUseKeyType is HSM_AES_KEY_CHIP_VENDOR_IFR, this MUST configure */ + uint32_t u32GenMacByteCnt; /*!< XCMAC API generate MAC data, it's "u32GenMacByteCnt" size ICV data */ + HSM_BoolType bCheckMacEn; /*!< if enable this check, user should place the data after the input data, hsm will check the generated data and it, if fail, hsm generate a interrupt, and if user get hw status, will get a error status */ + const uint32_t *pDataInput; /*!< address should align with 4bytes */ + uint32_t u32InputByteCnt; /*!< 128bit(16Bytes) align */ + uint32_t *pDataOutput; /*!< address should align with 4bytes */ + uint32_t u32OutputMemSize; /*!< 4bytes align, the output data buffer "pDataOutput" size, should >= "u32GenMacByteCnt" */ + + HSM_XCMAC_BackendType eBackend; + HSM_DataFormatType eInputFmt; + HSM_DataFormatType eOutputFmt; +} HSM_XCMacExType; + +typedef HSM_XCMacExType HSM_CMacExType; +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + uint32_t u32UserKeyID; /*!< 0 means don't use key from HSM internal key space, otherwise would load key with KEYID from HSM */ + HSM_CMacExType tCfg; /*!< CMAC parameters */ +} HSMCom_CMacExType; + + +/* ------------------------------------------------------------------------------- */ +/** + * @brief XMAC information used by driver when call specific API + * + */ +typedef HSM_XCMacType HSM_XMacType; +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + uint32_t u32UserKeyID; /*!< 0 means don't use key from HSM internal key space, otherwise would load key with KEYID from HSM */ + HSM_XMacType tCfg; /*!< XMAC parameter */ +} HSMCom_XMacType; + +typedef HSM_XCMacExType HSM_XMacExType; +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + uint32_t u32UserKeyID; /*!< 0 means don't use key from HSM internal key space, otherwise would load key with KEYID from HSM */ + HSM_XMacExType tCfg; /*!< XMAC parameter */ +} HSMCom_XMacExType; + +/* ------------------------------------------------------------------------------- */ +/** + * @brief AES hardware backend for CCM for type "HSM_CcmBackendType" + * + */ +#define HSM_CCM_BACKEND_AES 0u + +/** + * @brief SM4 hardware backend for CCM for type "HSM_CcmBackendType" + * + */ +#define HSM_CCM_BACKEND_SM4 1u + +/** + * @brief type definition for CCM's hardware backend + * AES backend refer to HSM_CCM_BACKEND_AES + * SM4 backend refer to HSM_CCM_BACKEND_SM4 + */ +typedef uint32_t HSM_CcmBackendType; + + +/** + * @brief CCM Encrypt information used by driver when call specific API + * + */ +typedef struct +{ + HSM_AesKeyType eUseKeyType; /*!< the key source:vendor key programmed in nvr flash or new key in software */ + HSM_AesNewKeyInfType tNewKeyInf; /*!< when eUseKeyType is HSM_AES_KEY_NEW, this MUST configure */ + HSM_AesVendorKeyInfType tVendorKeyInf; /*!< when eUseKeyType is HSM_AES_KEY_CHIP_VENDOR_IFR, this MUST configure */ + uint32_t *pAllData; /*!< address should align with 4bytes, place AAD data(16bytes align) first, then input data */ + uint32_t u32AadByteCnt; /*!< the byte count contain the 2bytes in the head, it's the valid data size, not after aligned, 128bit(16Bytes) align, if not, only the aligned data treat as AAD, the left AAD bytes will be treated as input data */ + uint32_t u32InputByteCnt; /*!< 128bit(16Bytes) align, ONLY represent data */ + uint32_t u32GenMacByteCnt; /*!< output mac size */ + uint32_t *pDataOutput; /*!< address should align with 4bytes */ + uint32_t u32OutputMemSize; /*!< the output data buffer "pDataOutput" size, should >= "u32InputByteCnt" */ + uint32_t (*pIvData)[8]; /*!< iv data, consist of 16bytes B0 data, and 16bytes CTR, MUST configure */ + uint32_t (*pMacOut)[4]; /*!< HSM generated MAC data */ + uint32_t (*pEmacOut)[4]; /*!< HSM generated encrypted MAC data */ +} HSM_CcmEncryptType; + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + uint32_t u32UserKeyID; /*!< 0 means don't use key from HSM internal key space, otherwise would load key with KEYID from HSM */ + HSM_CcmEncryptType tCfg; /*!< CCM encrypt parameters */ +} HSMCom_CcmEncryptType; + +typedef struct +{ + HSM_AesKeyType eUseKeyType; /*!< the key source:vendor key programmed in nvr flash or new key in software */ + HSM_AesNewKeyInfType tNewKeyInf; /*!< when eUseKeyType is HSM_AES_KEY_NEW, this MUST configure */ + HSM_AesVendorKeyInfType tVendorKeyInf; /*!< when eUseKeyType is HSM_AES_KEY_CHIP_VENDOR_IFR, this MUST configure */ + uint32_t *pAllData; /*!< address should align with 4bytes, place AAD data(16bytes align) first, then input data */ + uint32_t u32AadByteCnt; /*!< the byte count contain the 2bytes in the head, it's the valid data size, not after aligned, 128bit(16Bytes) align, if not, only the aligned data treat as AAD, the left AAD bytes will be treated as input data */ + uint32_t u32InputByteCnt; /*!< 128bit(16Bytes) align, ONLY represent data */ + uint32_t u32GenMacByteCnt; /*!< output mac size */ + uint32_t *pDataOutput; /*!< address should align with 4bytes */ + uint32_t u32OutputMemSize; /*!< the output data buffer "pDataOutput" size, should >= "u32InputByteCnt" */ + uint32_t (*pIvData)[8]; /*!< iv data, consist of 16bytes B0 data, and 16bytes CTR, MUST configure */ + uint32_t (*pMacOut)[4]; /*!< HSM generated MAC data */ + uint32_t (*pEmacOut)[4]; /*!< HSM generated encrypted MAC data */ + HSM_CcmBackendType eBackend; +} HSM_CcmEncryptExType; + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + uint32_t u32UserKeyID; /*!< 0 means don't use key from HSM internal key space, otherwise would load key with KEYID from HSM */ + HSM_CcmEncryptExType tCfg; /*!< CCM encrypt parameters */ +} HSMCom_CcmEncryptExType; + +/* ------------------------------------------------------------------------------- */ +/** + * @brief CCM Decrypt information used by driver when call specific API + * + */ +typedef struct +{ + HSM_AesKeyType eUseKeyType; /*!< the key source:vendor key programmed in nvr flash or new key in software */ + HSM_AesNewKeyInfType tNewKeyInf; /*!< when eUseKeyType is HSM_AES_KEY_NEW, this MUST configure */ + HSM_AesVendorKeyInfType tVendorKeyInf; /*!< when eUseKeyType is HSM_AES_KEY_CHIP_VENDOR_IFR, this MUST configure */ + uint32_t *pAllData; /*!< address should align with 4bytes, place AAD data(if exist, 16bytes align) first, then input data, then MAC data(if exist) */ + uint32_t u32AadByteCnt; /*!< 128bit(16Bytes) align, if not, only the aligned data treat as AAD, the left AAD bytes will be treated as input data */ + uint32_t u32InputByteCnt; /*!< 128bit(16Bytes) align */ + HSM_BoolType bCheckMacEn; /*!< check the MAC data in input or not */ + uint32_t u32MacByteCnt; /*!< 128bit(16Bytes) align */ + uint32_t *pDataOutput; /*!< point to the buffer that store the result */ + uint32_t u32OutputMemSize; /*!< the output data buffer "pDataOutput" size, should >= "u32InputByteCnt" */ + uint32_t (*pIvData)[8]; /*!< iv data, consist of 16bytes B0 data, and 16bytes CTR, MUST configure */ +} HSM_CcmDecryptType; + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + uint32_t u32UserKeyID; /*!< 0 means don't use key from HSM internal key space, otherwise would load key with KEYID from HSM */ + HSM_CcmDecryptType tCfg; /*!< CCM decrypt parameter */ +} HSMCom_CcmDecryptType; + +typedef struct +{ + HSM_AesKeyType eUseKeyType; /*!< the key source:vendor key programmed in nvr flash or new key in software */ + HSM_AesNewKeyInfType tNewKeyInf; /*!< when eUseKeyType is HSM_AES_KEY_NEW, this MUST configure */ + HSM_AesVendorKeyInfType tVendorKeyInf; /*!< when eUseKeyType is HSM_AES_KEY_CHIP_VENDOR_IFR, this MUST configure */ + uint32_t *pAllData; /*!< address should align with 4bytes, place AAD data(if exist, 16bytes align) first, then input data, then MAC data(if exist) */ + uint32_t u32AadByteCnt; /*!< 128bit(16Bytes) align, if not, only the aligned data treat as AAD, the left AAD bytes will be treated as input data */ + uint32_t u32InputByteCnt; /*!< 128bit(16Bytes) align */ + HSM_BoolType bCheckMacEn; /*!< check the MAC data in input or not */ + uint32_t u32MacByteCnt; /*!< 128bit(16Bytes) align */ + uint32_t *pDataOutput; /*!< point to the buffer that store the result */ + uint32_t u32OutputMemSize; /*!< the output data buffer "pDataOutput" size, should >= "u32InputByteCnt" */ + uint32_t (*pIvData)[8]; /*!< iv data, consist of 16bytes B0 data, and 16bytes CTR, MUST configure */ + HSM_CcmBackendType eBackend; +} HSM_CcmDecryptExType; + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + uint32_t u32UserKeyID; /*!< 0 means don't use key from HSM internal key space, otherwise would load key with KEYID from HSM */ + HSM_CcmDecryptExType tCfg; /*!< CCM decrypt parameter */ +} HSMCom_CcmDecryptExType; + +/* ------------------------------------------------------------------------------- */ +/** + * @brief AES hardware backend for GCM for type "HSM_GcmBackendType" + * + */ +#define HSM_GCM_BACKEND_AES 0u + +/** + * @brief SM4 hardware backend for GCM for type "HSM_GcmBackendType" + * + */ +#define HSM_GCM_BACKEND_SM4 1u + +/** + * @brief type definition for GCM's hardware backend + * AES backend refer to HSM_GCM_BACKEND_AES + * SM4 backend refer to HSM_GCM_BACKEND_SM4 + */ +typedef uint32_t HSM_GcmBackendType; + +/** + * @brief GCM Encrypt information used by driver when call specific API + * + */ +typedef struct +{ + HSM_AesKeyType eUseKeyType; /*!< the key source:vendor key programmed in nvr flash or new key in software */ + HSM_AesNewKeyInfType tNewKeyInf; /*!< when eUseKeyType is HSM_AES_KEY_NEW, this MUST configure */ + HSM_AesVendorKeyInfType tVendorKeyInf; /*!< when eUseKeyType is HSM_AES_KEY_CHIP_VENDOR_IFR, this MUST configure */ + uint32_t *pAllData; /*!< address should align with 4bytes, place IV data first, then AAD data(16bytes align), then input data */ + uint32_t u32IvDataByteCnt; /*!< 64bit(8Bytes) align, if not, only the aligned data treat as IV, the left IV bytes will be treated as AAD data */ + uint32_t u32AadByteCnt; /*!< 64bit(8Bytes) align, if not, only the aligned data treat as AAD, the left AAD bytes will be treated as input data */ + uint32_t u32InputByteCnt; /*!< 128bit(16Bytes) align */ + uint32_t u32GenMacByteCnt; /*!< set the MAC result byte count */ + uint32_t *pDataOutput; /*!< address should align with 4bytes */ + uint32_t u32OutputMemSize; /*!< the output data buffer "pDataOutput" size, should >= "u32InputByteCnt" */ + uint32_t (*pMacOut)[4]; /*!< buffer address, this buffer store the result */ +} HSM_GcmEncryptType; + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + uint32_t u32UserKeyID; /*!< 0 means don't use key from HSM internal key space, otherwise would load key with KEYID from HSM */ + HSM_GcmEncryptType tCfg; /*!< GCM parameters */ +} HSMCom_GcmEncryptType; + +/** + * @brief GCM Encrypt information used by driver when call specific API + * + */ +typedef struct +{ + HSM_AesKeyType eUseKeyType; /*!< the key source:vendor key programmed in nvr flash or new key in software */ + HSM_AesNewKeyInfType tNewKeyInf; /*!< when eUseKeyType is HSM_AES_KEY_NEW, this MUST configure */ + HSM_AesVendorKeyInfType tVendorKeyInf; /*!< when eUseKeyType is HSM_AES_KEY_CHIP_VENDOR_IFR, this MUST configure */ + uint32_t *pAllData; /*!< address should align with 4bytes, place IV data first, then AAD data(16bytes align), then input data */ + uint32_t u32IvDataByteCnt; /*!< 64bit(8Bytes) align, if not, only the aligned data treat as IV, the left IV bytes will be treated as AAD data */ + uint32_t u32AadByteCnt; /*!< 64bit(8Bytes) align, if not, only the aligned data treat as AAD, the left AAD bytes will be treated as input data */ + uint32_t u32InputByteCnt; /*!< 128bit(16Bytes) align */ + uint32_t u32GenMacByteCnt; /*!< set the MAC result byte count */ + uint32_t *pDataOutput; /*!< address should align with 4bytes */ + uint32_t u32OutputMemSize; /*!< the output data buffer "pDataOutput" size, should >= "u32InputByteCnt" */ + uint32_t (*pMacOut)[4]; /*!< buffer address, this buffer store the result */ + HSM_GcmBackendType eBackend; +} HSM_GcmEncryptExType; + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + uint32_t u32UserKeyID; /*!< 0 means don't use key from HSM internal key space, otherwise would load key with KEYID from HSM */ + HSM_GcmEncryptExType tCfg; /*!< GCM parameters */ +} HSMCom_GcmEncryptExType; + +/* ------------------------------------------------------------------------------- */ +/** + * @brief GCM Decrypt information used by driver when call specific API + * + */ +typedef struct +{ + HSM_AesKeyType eUseKeyType; /*!< the key source:vendor key programmed in nvr flash or new key in software */ + HSM_AesNewKeyInfType tNewKeyInf; /*!< when eUseKeyType is HSM_AES_KEY_NEW, this MUST configure */ + HSM_AesVendorKeyInfType tVendorKeyInf; /*!< when eUseKeyType is HSM_AES_KEY_CHIP_VENDOR_IFR, this MUST configure */ + uint32_t *pAllData; /*!< address should align with 4bytes, place IV data first, then AAD data(if exist, 16bytes align), then input data, then MAC data(if exist) */ + uint32_t u32IvDataByteCnt; /*!< 64bit(8Bytes) align, if not, only the aligned data treat as IV, the left IV bytes will be treated as AAD data */ + uint32_t u32AadByteCnt; /*!< 64bit(8Bytes) align, if not, only the aligned data treat as AAD, the left AAD bytes will be treated as input data */ + uint32_t u32InputByteCnt; /*!< 128bit(16Bytes) align */ + HSM_BoolType bCheckMacEn; /*!< check the MAC data in input or not */ + uint32_t u32MacByteCnt; /*!< 128bit(16Bytes) align */ + uint32_t *pDataOutput; /*!< point to the buffer that store the result */ + uint32_t u32OutputMemSize; /*!< the output data buffer "pDataOutput" size, should >= "u32InputByteCnt" */ +} HSM_GcmDecryptType; + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + uint32_t u32UserKeyID; /*!< 0 means don't use key from HSM internal key space, otherwise would load key with KEYID from HSM */ + HSM_GcmDecryptType tCfg; /*!< GCM decrypt parameter */ +} HSMCom_GcmDecryptType; + +/** + * @brief GCM Decrypt information used by driver when call specific API + * + */ +typedef struct +{ + HSM_AesKeyType eUseKeyType; /*!< the key source:vendor key programmed in nvr flash or new key in software */ + HSM_AesNewKeyInfType tNewKeyInf; /*!< when eUseKeyType is HSM_AES_KEY_NEW, this MUST configure */ + HSM_AesVendorKeyInfType tVendorKeyInf; /*!< when eUseKeyType is HSM_AES_KEY_CHIP_VENDOR_IFR, this MUST configure */ + uint32_t *pAllData; /*!< address should align with 4bytes, place IV data first, then AAD data(if exist, 16bytes align), then input data, then MAC data(if exist) */ + uint32_t u32IvDataByteCnt; /*!< 64bit(8Bytes) align, if not, only the aligned data treat as IV, the left IV bytes will be treated as AAD data */ + uint32_t u32AadByteCnt; /*!< 64bit(8Bytes) align, if not, only the aligned data treat as AAD, the left AAD bytes will be treated as input data */ + uint32_t u32InputByteCnt; /*!< 128bit(16Bytes) align */ + HSM_BoolType bCheckMacEn; /*!< check the MAC data in input or not */ + uint32_t u32MacByteCnt; /*!< 128bit(16Bytes) align */ + uint32_t *pDataOutput; /*!< point to the buffer that store the result */ + uint32_t u32OutputMemSize; /*!< the output data buffer "pDataOutput" size, should >= "u32InputByteCnt" */ + HSM_GcmBackendType eBackend; +} HSM_GcmDecryptExType; + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + uint32_t u32UserKeyID; /*!< 0 means don't use key from HSM internal key space, otherwise would load key with KEYID from HSM */ + HSM_GcmDecryptExType tCfg; /*!< GCM decrypt parameter */ +} HSMCom_GcmDecryptExType; + +/* ------------------------------------------------------------------------------- */ +/** + * @brief MD5 context information used by driver when call specific API + * + */ +typedef HSM_SmsCfgType HSM_Md5CtxType; +/** + * @brief MD5 information used by driver when call specific API + * + */ +typedef struct +{ + HSM_Md5CtxType tCfg; /*!< MD5 algorithm parameter set by user */ + uint32_t (*pRet)[4]; /*!< point to the memory that driver to store result */ + HSM_DataFormatType eIntputFmt; + HSM_DataFormatType eOutputFmt; +} HSM_Md5Type; + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + HSM_Md5Type tCfg; +} HSMCom_Md5Type; +/* ------------------------------------------------------------------------------- */ +/** + * @brief SM3 context information used by driver when call specific API + * + */ +typedef HSM_SmsCfgType HSM_Sm3CtxType; +/** + * @brief SM3 information used by driver when call specific API + * + */ +typedef struct +{ + HSM_Sm3CtxType tCfg; /*!< sm3 algorithm parameter set by user */ + uint32_t (*pRet)[8]; /*!< point to the memory that driver to store result */ + HSM_DataFormatType eIntputFmt; + HSM_DataFormatType eOutputFmt; +} HSM_Sm3Type; + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + HSM_Sm3Type tCfg; +} HSMCom_Sm3Type; + +/* ------------------------------------------------------------------------------- */ +#define HSMCOM_MONOTOIC_COUNTER_FLEX_REG_CNT 8 +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + uint32_t u32MonotonicIndex; // 0-13 + uint32_t u32CurrentValue; + uint32_t (*u32ExtraValue)[HSMCOM_MONOTOIC_COUNTER_FLEX_REG_CNT - 1]; + uint32_t (*u32ExtraAdd)[HSMCOM_MONOTOIC_COUNTER_FLEX_REG_CNT]; +} HSMCom_MonCountType; +/* ------------------------------------------------------------------------------- */ +/** + * @brief RSA information used by driver when call specific API + * + */ +typedef struct +{ + uint32_t *pInputData; /*!< input data, if not 64bytes align, the last uint64_t's high byte left to patch 0 to align */ + uint32_t u32InputDataByteCount; /*!< the byte count of input data */ + uint32_t *pKey_E; /*!< input key E data for "A = (input data)^E mod N", if not 64bytes align, the last uint64_t's high byte left to patch 0 to align */ + uint32_t u32Key_E_ByteCount; /*!< the byte count of key E */ + uint32_t *pKey_N; /*!< input key N data for "A = (input data)^E mod N", if not 64bytes align, the last uint64_t's high byte left to patch 0 to align */ + uint32_t u32Key_N_ByteCount; /*!< hw will get the actual key data bit count according to the non-zero bit count, it means key not generate by multiply 2 */ + uint32_t *pResult; /*!< output buffer, the buffer size should >= "u32Key_N_ByteCount" */ + uint32_t u32ResultBufByteCnt; /*!< the result buffer size */ +} HSM_RsaType; + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout tick count, tick refer to the HSM bus clock */ + uint32_t u32UserKeyID_KEY_E; //0 means don't load key from HSM, otherwise would load key with KEYID from HSM + uint32_t u32UserKeyID_KEY_N; //0 means don't load key from HSM, otherwise would load key with KEYID from HSM + uint32_t u32RsaBitCnt; + HSM_RsaType tCfg; +} HSMCom_RsaType; +/* ------------------------------------------------------------------------------- */ +#define HSM_BIGNUMBER_CALC_A_ADD_B 0xFC730002 +#define HSM_BIGNUMBER_CALC_A_SUB_B 0xFC730003 +#define HSM_BIGNUMBER_CALC_B_SUB_A 0xFC730004 +#define HSM_BIGNUMBER_CALC_A_MUL_B 0xFC730005 +#define HSM_BIGNUMBER_CALC_A_EXP_E 0xFC730006 +#define HSM_BIGNUMBER_CALC_A_RED_N 0xFC730007 +#define HSM_BIGNUMBER_CALC_A_INV 0xFC730008 + +/** + * @brief RSA information used by driver when call specific API + * + */ +typedef struct +{ + uint32_t *pA; /*!< address is 4bytes aligned, input data, if not 64bytes align, the last uint64_t's high byte left to patch 0 to align */ + uint32_t u32AByteCount; /*!< the byte count of input data */ + uint32_t *pE; /*!< address is 4bytes aligned, input key E data for "A = (input data)^E mod N", if not 64bytes align, the last uint64_t's high byte left to patch 0 to align */ + uint32_t u32EByteCount; /*!< the byte count of key E */ + uint32_t *pN; /*!< address is 4bytes aligned, input key N data for "A = (input data)^E mod N", if not 64bytes align, the last uint64_t's high byte left to patch 0 to align */ + uint32_t u32NByteCount; /*!< hw will get the actual key data bit count according to the non-zero bit count, it means key not generate by multiply 2 */ + uint32_t *pResult; /*!< address is 4bytes aligned, output buffer, the buffer size should >= "u32Key_N_ByteCount" */ + uint32_t u32ResultBufByteCnt; /*!< the result buffer size */ + uint32_t u32CalcType; + uint32_t *pB; + uint32_t u32BByteCount; +} HSM_BigNumberCalcType; + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout Millisecond count, max 916000ms, if set to 0, means 1000ms */ + uint32_t u32UserKeyID_KEY_E; /*!< means don't load key from HSM, otherwise would load key with KEYID from HSM */ + uint32_t u32UserKeyID_KEY_N; /*!< means don't load key from HSM, otherwise would load key with KEYID from HSM */ + uint32_t u32BitCnt; /*!< the bit count of numbers used of N */ + HSM_BigNumberCalcType tCfg; /*!< RSA parameters */ +} HSMCom_BigNumberCalcType; +/* ------------------------------------------------------------------------------- */ + + +typedef struct +{ + HSM_MailboxApiRetType u32HSMStatusRet; /*!< HSM core write return status value in this */ + uint32_t u32Timeout; /*!< current command timeout Millisecond count, max 916000ms, if set to 0, means 1000ms */ +} HSMCom_LoadFirmwareType; + +/* ------------------------------------------------------------------------------- */ + +typedef HSMCom_LoadFirmwareType HSMCom_BasicType; + +/* #define AUTH_CHECK_DATA_BYTE_CNT 32 */ + +typedef struct { + uint32_t u32HSMStatusRet; + uint32_t u32Timeout; + const uint32_t *pkG_x; /*!< address should align with 4bytes */ + const uint32_t *pkG_y; /*!< address should align with 4bytes */ + const uint32_t *pR; /*!< address should align with 4bytes */ + const uint32_t *pS; /*!< address should align with 4bytes */ + //For user code verify function + const uint32_t *pData; /*!< address should align with 4bytes */ + uint32_t u32DataLength; +} HSMCom_AuthCheckType; + +typedef struct { + HSM_BoolType bStoreInFlash; + HSM_BoolType bUseDefaultID; //TRUE means use default ID. FALSE means use specific ID with "pInputData_ID" and "u32SM2InputIDByteCnt" params. + uint32_t u32SM2InputIDByteCnt;//the length should be <= 32bytes note: If "bUseDefaultID" is FALSE, would use this specific ID length with byte unit. + uint32_t *pInputData_ID; //note: If "bUseDefaultID" is FALSE, would use this specific ID. length should be more than u32SM2InputIDByteCnt, and must be 4bytes align + uint32_t (*pRaPublicKey_X)[8]; + uint32_t (*pRaPublicKey_Y)[8]; + uint32_t (*pPaPublicKey_X)[8]; + uint32_t (*pPaPublicKey_Y)[8]; + uint32_t (*pPublicKey_X)[8]; + uint32_t (*pPublicKey_Y)[8]; + uint32_t (*PrivateKey)[8]; + uint32_t (*pRbPublicKey_X)[8]; + uint32_t (*pRbPublicKey_Y)[8]; + uint32_t *pOutputKeyID; +}HSM_SmDHType; + +typedef struct { + uint32_t u32HSMStatusRet; + uint32_t u32Timeout; + HSM_SmDHType tCfg; +} HSMCom_SmDHType; + +typedef struct { + uint32_t u32ByteCount; /*!< all the data size, it should contains all N data */ + HSM_DrvEccCurveParamType tCurve; + const uint32_t *pASidePublicKey_x; /*!< A side's public key axis x data */ + const uint32_t *pASidePublicKey_y; /*!< A side's public key axis y data */ + const uint32_t *pBSidePrivateKey; /*!< B side private key */ + /* Below is output data */ + uint32_t *pBSidePublicKey_x; /*!< B side's public key axis x data */ + uint32_t *pBSidePublicKey_y; /*!< B side's public key axis y data */ + uint32_t *pSharedPublicKey_x; + uint32_t *pSharedPublicKey_y; +}HSM_ECDHType; + +typedef struct { + uint32_t u32HSMStatusRet; + uint32_t u32Timeout; + uint32_t u32UserKeyID_BSidePrivateKey; //0 means don't load key from HSM, otherwise would load key with KEYID from HSM + uint32_t u32UserKeyID_BSidePublicKey; //0 means don't load key from HSM, otherwise would load key with KEYID from HSM + uint32_t u32BitCnt; + HSM_DrvEccCurvePrmIndexType u32EccCurve; + HSM_ECDHType tCfg; +} HSMCom_ECDHType; + +typedef struct { + uint32_t *pInputKey_a; /*!< input private key b data, if not 64bytes align, the last uint64_t's high byte left to patch 0 to align */ + uint32_t u32Key_a_ByteCount; /*!< the byte count of key b */ + uint32_t *pInputKey_B; /*!< input public key A data, if not 64bytes align, the last uint64_t's high byte left to patch 0 to align */ + uint32_t u32Key_B_ByteCount; /*!< the byte count of key A */ + uint32_t *pPublicParam_g; /*!< Param g data for "A = g^a mod p", if not 64bytes align, the last uint64_t's high byte left to patch 0 to align */ + uint32_t u32PublicParam_g_ByteCount; /*!< the byte count of param g */ + uint32_t *pPublicParam_p; /*!< Param p data for "A = g^a mod p", if not 64bytes align, the last uint64_t's high byte left to patch 0 to align */ + uint32_t u32PublicParam_p_ByteCount; /*!< the byte count of param p */ + uint32_t *pOutputKey_A; /*!< output public key B data, if not 64bytes align, the last uint64_t's high byte left to patch 0 to align */ + uint32_t *pOutputKey_S; +} HSM_RsaDHType; + +typedef struct { + uint32_t u32HSMStatusRet; + uint32_t u32Timeout; + uint32_t u32UserKeyID_a; //0 means don't load key from HSM, otherwise would load key with KEYID from HSM + uint32_t u32UserKeyID_B; //0 means don't load key from HSM, otherwise would load key with KEYID from HSM + HSM_RsaDHType tCfg; +} HSMCom_RsaDHType; + +typedef struct { + HSM_HashAlgType eHashAlg; + uint32_t u32Counter; + uint32_t u32dkLen; + uint32_t u32PasswordByteLength; + const uint32_t *pPassword; + uint32_t u32SaltByteLength; + const uint32_t *pSalt; + uint32_t *pKdfOutput; +} HSM_PBKDF2Type; + +/** + * @brief RSA SSA input data is the raw message for HSM_RsaSsaInputType + * + */ +#define HSM_RSA_SSA_INPUT_RAW_MESSAGE 0u + +/** + * @brief RSA SSA input data is the hash value of raw message for HSM_RsaSsaInputType + * + */ +#define HSM_RSA_SSA_INPUT_HASH_DATA 1u + +/** + * @brief type definition for rsa ssa input data type + * refer to HSM_RSA_SSA_INPUT_RAW_MESSAGE, HSM_RSA_SSA_INPUT_HASH_DATA + */ +typedef uint32_t HSM_RsaSsaInputType; + + +/** + * @brief RSA PSS signature information used by driver when call specific API + * + */ +typedef struct { + HSM_BoolType bUsePseudoRand; + HSM_HashAlgType eMgfHashType; + HSM_DataFormatType eInputFmt; /*!< input data organized format, uint8_t array, or uint32_t array */ + HSM_DataFormatType eOutputFmt; /*!< output data organized format, uint8_t array, or uint32_t array */ + uint32_t u32EmBitCnt; /* RFC8017 require set it to (N's bit count - 1).the em data bit count, it MUST < N's bit count */ + HSM_HashAlgType eHashType; /*!< the hash type used by signature */ + HSM_RsaSsaInputType eInputType; /*!< input data type, may raw input message, or the hash data of raw message */ + const uint8_t *pInputData; /*!< input data */ + uint32_t u32InputDataByteCount; /*!< the byte count of input data */ + const uint8_t *pPrivateKey; /*!< private key, input key E data for "A = (input data)^E mod N" */ + uint32_t u32PrivateKeyByteCnt; /*!< the byte count of key E */ + HSM_BoolType bUseInputSaltData; /*!< use input salt data or not, , suggest set to HSM_FALSE to use internal random data */ + const uint8_t *pSalt; /*!< input salt data, , suggest set to NULL. if use hsm internal random data, just set it to NULL */ + uint32_t u32SaltByteCount; /*!< the byte count of salt data, it must > 0, suggest use hash length, for example, if eHashType is HSM_SHA_256, set this to 256/8=32bytes */ + const uint8_t *pKeyN; /*!< input key N data for "A = (input data)^E mod N" */ + uint32_t u32KeyNByteCount; /*!< key N's data byte count */ + uint8_t *pResult; /*!< output buffer, the buffer size should >= "u32KeyNByteCount" */ + uint32_t u32ResultBufByteCnt; /*!< the result buffer size */ + uint32_t *pResultByteCnt; /*!< the result data byte count */ +} HSM_RsaSsaPssSignType; + +typedef struct { + uint32_t u32HSMStatusRet; + uint32_t u32Timeout; + uint32_t u32UserKeyID_KEY_E; + uint32_t u32UserKeyID_KEY_N; + uint32_t u32RsaBitCnt; + HSM_RsaSsaPssSignType tCfg; +}HSMCom_RsaSsaPssSignType; + +/** + * @brief RSA PSS signature verify information used by driver when call specific API + * + */ +typedef struct { + uint32_t u32EmBitCnt; /* RFC8017 require set it to (N's bit count - 1). the em data bit count, it MUST < N's bit count, should keep same with the signature generate configuration */ + HSM_HashAlgType eMgfHashType; + HSM_HashAlgType eHashType; /*!< the hash type used by signature */ + uint32_t u32SaltByteCount; /*!< the byte count of salt data, it must > 0, suggest use hash length, for example, if eHashType is HSM_SHA_256, set this to 256/8=32bytes */ + HSM_DataFormatType eInputDataFmt; /*!< input data(raw message or hash data) organized format, uint8_t array, or uint32_t array */ + HSM_RsaSsaInputType eInputType; /*!< input data type, may raw input message, or the hash data of raw message */ + const uint8_t *pInputData; /*!< input data */ + uint32_t u32InputDataByteCount; /*!< the byte count of input data, when the eInputType is HSM_RSA_SSA_INPUT_RAW_MESSAGE */ + HSM_DataFormatType eSignDataFmt; /*!< Signature/Public key/N input data organized format, uint8_t array, or uint32_t array */ + const uint8_t *pSignData; /*!< input signature data */ + uint32_t u32SignDataByteCount; /*!< the byte count of signature data, it must > 0 */ + HSM_DataFormatType ePublicKeyDataFmt; + const uint8_t *pPublicKey; /*!< public key, input key E data for "A = (input data)^E mod N" */ + uint32_t u32PublicKeyByteCnt; /*!< the byte count of key E */ + HSM_DataFormatType eKeyNDataFmt; + const uint8_t *pKeyN; /*!< input key N data for "A = (input data)^E mod N" */ + uint32_t u32KeyNByteCount; /*!< key N data byte count */ +} HSM_RsaSsaPssVerifyType; + +typedef struct { + uint32_t u32HSMStatusRet; + uint32_t u32Timeout; + uint32_t u32UserKeyID_KEY_E; + uint32_t u32UserKeyID_KEY_N; + uint32_t u32RsaBitCnt; + HSM_RsaSsaPssVerifyType tCfg; +}HSMCom_RsaSsaPssVerifyType; + +/** + * @brief RSA PKCS1 V1.5 signature information used by driver when call specific API + * + */ +typedef struct { + HSM_DataFormatType eInputFmt; /*!< input data organized format, uint8_t array, or uint32_t array */ + HSM_DataFormatType eOutputFmt; /*!< output data organized format, uint8_t array, or uint32_t array */ + uint32_t u32EmByteCnt; /* RFC8017 require set it to N'byte count, equal to u32KeyNByteCount. the em data byte count, itx8 MUST < N's bit count, should keep same with the signature generate configuration */ + HSM_HashAlgType eHashType; /*!< the hash type used by signature */ + const uint8_t *pInputData; /*!< input data */ + uint32_t u32InputDataByteCount; /*!< the byte count of input data */ + const uint8_t *pPrivateKey; /*!< private key, input key E data for "A = (input data)^E mod N" */ + uint32_t u32PrivateKeyByteCnt; /*!< the byte count of key E */ + HSM_BoolType bUseInputDer; /*!< set to HSM_TRUE when RFC8017 not support some hash algorithm, for example SM3 Hash type, DER encoding of the DigestInfo value, if use hsm internal data, just set it to HSM_FALSE */ + const uint8_t *pDer; /*!< when bUseInputDer is HSM_TRUE, this field point to the DER encoding of the DigestInfo value, others, ignore */ + uint32_t u32DerByteCount; /*!< when bUseInputDer is HSM_TRUE, this field represent the byte count of DER data, if bUseInputDer is HSM_FALSE, ignore this field */ + const uint8_t *pKeyN; /*!< input key N data for "A = (input data)^E mod N" */ + uint32_t u32KeyNByteCount; /*!< key N's data byte count */ + uint8_t *pResult; /*!< output buffer, the buffer size should >= "u32KeyNByteCount" */ + uint32_t u32ResultBufByteCnt; /*!< the result buffer size */ + uint32_t *pResultByteCnt; /*!< the result data byte count */ +} HSM_RsaSsaPkcs1V15SignType; + +typedef struct { + uint32_t u32HSMStatusRet; + uint32_t u32Timeout; + uint32_t u32UserKeyID_KEY_E; + uint32_t u32UserKeyID_KEY_N; + uint32_t u32RsaBitCnt; + HSM_RsaSsaPkcs1V15SignType tCfg; +}HSMCom_RsaSsaPkcs1V15SignType; + +/** + * @brief RSA PKCS1 V1.5 signature verify information used by driver when call specific API + * + */ +typedef struct { + HSM_DataFormatType eInputFmt; /*!< input data organized format, uint8_t array, or uint32_t array */ + uint32_t u32EmByteCnt; /* RFC8017 require set it to N'byte count, equal to u32KeyNByteCount. the em data byte count, itx8 MUST < N's bit count, should keep same with the signature generate configuration */ + HSM_HashAlgType eHashType; /*!< the hash type used by signature */ + const uint8_t *pInputData; /*!< input data */ + uint32_t u32InputDataByteCount; /*!< the byte count of input data */ + const uint8_t *pSignData; /*!< input signature data */ + uint32_t u32SignDataByteCount; /*!< the byte count of signature data, it must > 0 */ + const uint8_t *pPublicKey; /*!< public key, input key E data for "A = (input data)^E mod N" */ + uint32_t u32PublicKeyByteCnt; /*!< the byte count of key E */ + HSM_BoolType bUseInputDer; /*!< set to HSM_TRUE when RFC8017 not support some hash algorithm, for example SM3 Hash type, DER encoding of the DigestInfo value, if use hsm internal data, just set it to HSM_FALSE */ + const uint8_t *pDer; /*!< when bUseInputDer is HSM_TRUE, this field point to the DER encoding of the DigestInfo value, others, ignore */ + uint32_t u32DerByteCount; /*!< when bUseInputDer is HSM_TRUE, this field represent the byte count of DER data, if bUseInputDer is HSM_FALSE, ignore this field */ + const uint8_t *pKeyN; /*!< input key N data for "A = (input data)^E mod N" */ + uint32_t u32KeyNByteCount; /*!< key N's data byte count */ +} HSM_RsaSsaPkcs1V15VerifyType; + +typedef struct { + uint32_t u32HSMStatusRet; + uint32_t u32Timeout; + uint32_t u32UserKeyID_KEY_E; + uint32_t u32UserKeyID_KEY_N; + uint32_t u32RsaBitCnt; + HSM_RsaSsaPkcs1V15VerifyType tCfg; +}HSMCom_RsaSsaPkcs1V15VerifyType; + +typedef struct { + + HSM_BoolType bUsePseudoRand; + const uint8_t *pInputData; /*!< input data */ + uint32_t u32InputDataByteCount; + HSM_DataFormatType eInputDataFmt; + const uint8_t *pKeyE; + uint32_t u32KeyEByteCount; + HSM_DataFormatType eKeyEFmt; + const uint8_t *pKeyN; + uint32_t u32KeyNByteCount; + HSM_DataFormatType eKeyNFmt; + uint8_t *pResult; + uint32_t u32ResultBufByteCnt; + HSM_DataFormatType eOutputFmt; + uint32_t *pResultByteCnt; +} HSM_RsaEsPkcs1V15EnDecryptType; + +typedef struct { + uint32_t u32HSMStatusRet; + uint32_t u32Timeout; + uint32_t u32UserKeyID_KEY_E; + uint32_t u32UserKeyID_KEY_N; + uint32_t u32RsaBitCnt; + HSM_RsaEsPkcs1V15EnDecryptType tCfg; +}HSMCom_RsaEsPkcs1V15EnDecryptType; + +typedef HSMCom_RsaEsPkcs1V15EnDecryptType HSMCom_RsaEsPkcs1V15EncryptType; + +typedef HSMCom_RsaEsPkcs1V15EnDecryptType HSMCom_RsaEsPkcs1V15DecryptType; + +typedef struct { + HSM_BoolType bUsePseudoRand; + HSM_HashAlgType eHashType; /*!< the hash type used by signature */ + HSM_HashAlgType eMgfHashType; + const uint8_t *pLabel; /*!< input data */ + uint32_t u32LabelByteCount; + HSM_DataFormatType eLabelFmt; + const uint8_t *pInputData; /*!< input data */ + uint32_t u32InputDataByteCount; + HSM_DataFormatType eInputDataFmt; + const uint8_t *pKeyE; + uint32_t u32KeyEByteCount; + HSM_DataFormatType eKeyEFmt; + const uint8_t *pKeyN; + uint32_t u32KeyNByteCount; + HSM_DataFormatType eKeyNFmt; + uint8_t *pResult; + uint32_t u32ResultBufByteCnt; + HSM_DataFormatType eOutputFmt; + uint32_t *pResultByteCnt; +} HSM_RsaEsOaepEnDecryptType; + +typedef struct { + uint32_t u32HSMStatusRet; + uint32_t u32Timeout; + uint32_t u32UserKeyID_KEY_E; + uint32_t u32UserKeyID_KEY_N; + uint32_t u32RsaBitCnt; + HSM_RsaEsOaepEnDecryptType tCfg; +}HSMCom_RsaEsOaepEnDecryptType; + + +typedef HSMCom_RsaEsOaepEnDecryptType HSMCom_RsaEsOaepEncryptType; + +typedef HSMCom_RsaEsOaepEnDecryptType HSMCom_RsaEsOaepDecryptType; + + +typedef struct { + uint32_t u32HSMStatusRet; + uint32_t u32Timeout; + uint32_t u32UserKeyID_Password; //0 means don't load key from HSM, otherwise would load key with KEYID from HSM + HSM_PBKDF2Type tCfg; +} HSMCom_Pbkdf2Type; + +typedef struct { + uint32_t u32Counter; + uint32_t u32dkLen; + uint32_t u32PasswordByteLength; + const uint32_t *pPassword; + uint32_t u32SaltByteLength; + const uint32_t *pSalt; + uint32_t *pKdfOutput; +} HSM_GMPBKDFType; + +typedef struct { + uint32_t u32HSMStatusRet; + uint32_t u32Timeout; + uint32_t u32UserKeyID_Password; //0 means don't load key from HSM, otherwise would load key with KEYID from HSM + HSM_GMPBKDFType tCfg; +} HSMCom_GMpbkdfType; +/* ------------------------------------------------------------------------------- */ + +/**@}*/ + + +/** + * @name API declaration for HSM + * + */ +/**@{*/ + +/** + * @brief Get the true random data + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pRandom the array address to store the result + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_TrueRandGetSrc0(HSM_CmdType *pCmd, const HSMCom_TrueRandType*pCfg); + + +/** + * @brief Get the true random data + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pRandom the array address to store the result + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_TrueRandGetSrc1(HSM_CmdType *pCmd, const HSMCom_TrueRandType*pCfg); + + +/** + * @brief Get the true random data + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pRandom the array address to store the result + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_TrueRandGetSrcXor(HSM_CmdType *pCmd, const HSMCom_TrueRandType*pCfg); + + +/** + * @brief Get the true random data + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pRandom the array address to store the result + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_TrueRandGet(HSM_CmdType *pCmd, const HSMCom_TrueRandType*pCfg); + + +/** + * @brief Get the pseudo random data + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pRandom the array address to store the result + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_PseudoRandGet(HSM_CmdType *pCmd, const HSMCom_TrueRandType*pCfg); + + +/** + * @brief SHA + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg SHA parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_Sha(HSM_CmdType *pCmd, const HSMCom_ShaType *pCfg); + + +/** + * @brief SHAEx + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg SHA parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_ShaEx(HSM_CmdType *pCmd, const HSMCom_Sha2Type *pCfg); + + +/** + * @brief Md5Ex + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg MD5 parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_Md5Ex(HSM_CmdType *pCmd, const HSMCom_Md5Type *pCfg); + + +/** + * @brief Sm3Ex + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg SM3 parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_Sm3Ex(HSM_CmdType *pCmd, const HSMCom_Sm3Type *pCfg); + + +/** + * @brief HashEx Init + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg HashEx parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY when driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_HashInitEx(HSM_CmdType *pCmd, const HSMCom_ShaType *pCfg); + + +/** + * @brief HashEx Update + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg HashEx parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY when driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_HashUpdateEx(HSM_CmdType *pCmd, const HSMCom_ShaType *pCfg); + + +/** + * @brief HashEx Finally + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg HashEx parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY when driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_HashFinallyEx(HSM_CmdType *pCmd, const HSMCom_ShaType *pCfg); + + +/** + * @brief Scatter Hash Init + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg scatter hash parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY when driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_ScatterHashInit(HSM_CmdType *pCmd, const HSMCom_ScatterHashType *pCfg); + + +/** + * @brief Scatter Hash Update + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg scatter hash parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY when driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_ScatterHashUpdate(HSM_CmdType *pCmd, const HSMCom_ScatterHashType *pCfg); + + +/** + * @brief Scatter Hash Finally + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg scatter hash parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY when driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_ScatterHashFinally(HSM_CmdType *pCmd, const HSMCom_ScatterHashType *pCfg); + +/** + * @brief ECC Sign + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg ECC sign parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_EccSign(HSM_CmdType *pCmd, const HSMCom_EccSignType *pCfg); + + +/** + * @brief EccPointCalc + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg EccPointCalc parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_EccPointCalc(HSM_CmdType *pCmd, const HSMCom_EccCalcType *pCfg); + + +/** + * @brief ECC Verify + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg ECC verify parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_EccVerify(HSM_CmdType *pCmd, const HSMCom_EccVerifyType *pCfg); + + +/** + * @brief ECC key pair generate + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg ECC key pair parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_EccGenKeyPair(HSM_CmdType *pCmd, const HSMCom_EccKeyPairGenType *pCfg); + + +/** + * @brief SM2 key pair generate + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg SM2 key pair parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_Sm2GenKeyPair(HSM_CmdType *pCmd, const HSMCom_Sm2GenKeyPairType *pCfg); + + +/** + * @brief SM2 encrypt + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg SM2 encrypt parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_Sm2Encry(HSM_CmdType *pCmd, const HSMCom_Sm2EncryptType *pCfg); + + +/** + * @brief SM2 decrypt + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg SM2 decrypt parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_Sm2Decry(HSM_CmdType *pCmd, const HSMCom_Sm2DecryptType *pCfg); + + +/** + * @brief SM2 sign + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg SM2 sign parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_Sm2Sign(HSM_CmdType *pCmd, const HSMCom_Sm2SignType *pCfg); + + +/** + * @brief SM2 verify + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg SM2 verify parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_Sm2Verify(HSM_CmdType *pCmd, const HSMCom_Sm2VerifyType *pCfg); + + +/** + * @brief SM2 ZA + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg SM2 ZA parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_Sm2GenZa(HSM_CmdType *pCmd, const HSMCom_Sm2GenZaType *pCfg); + + +/** + * @brief SM2 Hash generate + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg SM2 HASH parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_Sm2GenHash(HSM_CmdType *pCmd, const HSMCom_Sm2GenHashType *pCfg); + + +/** + * @brief SM4 encrypt + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg SM4 encrypt parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_Sm4Encrypt(HSM_CmdType *pCmd, const HSMCom_Sm4EncryptType *pCfg); + + +/** + * @brief SM4 decrypt + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg SM4 decrypt parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_Sm4Decrypt(HSM_CmdType *pCmd, const HSMCom_Sm4DecryptType *pCfg); + + +/** + * @brief ECC easy encrypt + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg ECC encrypt parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_EccEasyEncry(HSM_CmdType *pCmd, const HSMCom_EccEasyEncryType *pCfg); + + +/** + * @brief ECC easy decrypt + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg ECC decrypt parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_EccEasyDecry(HSM_CmdType *pCmd, const HSMCom_EccEasyDecryType *pCfg); + + +/** + * @brief RequestAuthorization + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg ECC decrypt parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_RequestAuthorization(HSM_CmdType *pCmd, const HSMCom_RequestAuthType *pCfg); + + +/** + * @brief TakeEffect + * + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_TakeEffect(HSM_CmdType *pCmd); + + +/** + * @brief OemDevEnter + * + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_OemDevEnter(HSM_CmdType *pCmd); + + +/** + * @brief HSM_OemPdtEnter + * + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_OemPdtEnter(HSM_CmdType *pCmd); + +/** + * @brief HSM_InFieldEnter + * + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_InFieldEnter(HSM_CmdType *pCmd); + + +/** + * @brief CancelJob + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_CancelJob(HSM_CmdType *pCmd, const HSMCom_CancelJobType *pCfg); + + +/** + * @brief SelfTest + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg self test parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_SelfTest(HSM_CmdType *pCmd, const HSMCom_SelfTestType *pCfg); + + +/** + * @brief NvrOtpProgram + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_NvrOtpProgram(HSM_CmdType *pCmd, const HSMCom_NvrOtpType *pCfg); + + +/** + * @brief NvrOtpRead + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_NvrOtpRead(HSM_CmdType *pCmd, const HSMCom_NvrOtpType *pCfg); + + +/** + * @brief Revoke UserKey + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg UserKeyManage parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_UserKeyRevoke(HSM_CmdType *pCmd, const HSMCom_UserKeyManageType *pCfg); + + +/** + * @brief Revoke Umrk0 + * + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_RevokeUmrk0(HSM_CmdType *pCmd); + + +/** + * @brief Revoke Umrk1 + * + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_RevokeUmrk1(HSM_CmdType *pCmd); + + +/** + * @brief Revoke Umrk2 + * + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_RevokeUmrk2(HSM_CmdType *pCmd); + + +/** + * @brief Revoke Umrk3 + * + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_RevokeUmrk3(HSM_CmdType *pCmd); + + +/** + * @brief UserKeyImport + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_UserKeyImport(HSM_CmdType *pCmd, const HSMCom_UserKeyManageType *pCfg); + + +/** + * @brief UserKeyExport + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_UserKeyExport(HSM_CmdType *pCmd, const HSMCom_UserKeyManageType *pCfg); + + +/** + * @brief Generate User Key + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_UserKeyGen(HSM_CmdType *pCmd, const HSMCom_UserKeyManageType *pCfg); + + +/** + * @brief Generate Usrk + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_GenUsrk(HSM_CmdType *pCmd,const HSMCom_RsaType *pCfg); + + +/** + * @brief Erase Key in Flash + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_EraseKeyFlash(HSM_CmdType *pCmd, HSMCom_BasicType *pCfg); + + +/** + * @brief Enable Ram Key Copy + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_EnableKeyRamCopy(HSM_CmdType *pCmd, const HSMCom_UserKeyManageType *pCfg); + + +/** + * @brief Disable Ram Key Copy + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_DisableKeyRamCopy(HSM_CmdType *pCmd, const HSMCom_UserKeyManageType *pCfg); + + +/** + * @brief GetKeySpaceStatus + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg ECC decrypt parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_GetKeySpaceStatus(HSM_CmdType *pCmd, const HSMCom_KeySpaceStatusType *pCfg); + + +/** + * @brief TidyUpKeySpace + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg ECC decrypt parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_TidyUpKeySpace(HSM_CmdType *pCmd, const HSMCom_KeySpaceStatusType *pCfg); + + +/** + * @brief AES encrypt + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg AES encrypt parameters. + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_AesEncrypt(HSM_CmdType *pCmd, const HSMCom_AesEncryptType *pCfg); + + +/** + * @brief AES decrypt + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg AES decrypt parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. Others, some error occur. + */ +HSM_StatusType HSM_AesDecrypt(HSM_CmdType *pCmd, const HSMCom_AesDecryptType *pCfg); + + +/** + * @brief AES FlexEncrypt + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg AES encrypt parameters. + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_Aes_FlexEncrypt(HSM_CmdType *pCmd, const HSMCom_FlexAesEncryptType *pCfg); + + +/** + * @brief AES FlexDecrypt + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg AES decrypt parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. Others, some error occur. + */ +HSM_StatusType HSM_Aes_FlexDecrypt(HSM_CmdType *pCmd, const HSMCom_FlexAesDecryptType *pCfg); + + +/** + * @brief CMAC + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg CMAC parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY when driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_CMac(HSM_CmdType *pCmd, const HSMCom_CMacType *pCfg); + + +/** + * @brief CmacAesm + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY when driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_CmacAesm(HSM_CmdType *pCmd, const HSMCom_AesmRawApiType *pCfg); + + +/** + * @brief CmacEx + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg CMAC parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY when driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_CmacEx(HSM_CmdType *pCmd, const HSMCom_CMacExType *pCfg); + + +/** + * @brief Scatter Cmac + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg CMAC parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY when driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_CmacScatter(HSM_CmdType *pCmd, const HSMCom_ScatterMacType *pCfg); + + +/** + * @brief XMAC + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg XMAC parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY when driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_XMac(HSM_CmdType *pCmd, const HSMCom_XMacType *pCfg); + + +/** + * @brief XMacEx + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg XMAC parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY when driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_XMacEx(HSM_CmdType *pCmd, const HSMCom_XMacExType *pCfg); + + +/** + * @brief CCM encrypt + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg CCM encrypt parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY when driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_CcmEncry(HSM_CmdType *pCmd, const HSMCom_CcmEncryptType *pCfg); + + +/** + * @brief CCM decrypt + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg CCM decrypt parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY when driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_CcmDecry(HSM_CmdType *pCmd, const HSMCom_CcmDecryptType *pCfg); + + +/** + * @brief CcmEncryEx + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg Ccm encrypt parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY when driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_CcmEncryEx(HSM_CmdType *pCmd, const HSMCom_CcmEncryptExType *pCfg); + + +/** + * @brief CcmDecryEx + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg Ccm decrypt parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY when driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_CcmDecryEx(HSM_CmdType *pCmd, const HSMCom_CcmDecryptExType *pCfg); + + +/** + * @brief GCM encrypt + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg GCM encrypt parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY when driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_GcmEncry(HSM_CmdType *pCmd, const HSMCom_GcmEncryptType *pCfg); + + +/** + * @brief GCM decrypt + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg GCM decrypt parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY when driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_GcmDecry(HSM_CmdType *pCmd, const HSMCom_GcmDecryptType *pCfg); + + + +/** + * @brief GcmEncryEx + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg Gcm encrypt parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY when driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_GcmEncryEx(HSM_CmdType *pCmd, const HSMCom_GcmEncryptExType *pCfg); + + +/** + * @brief GcmDecryEx + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg Gcm decrypt parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY when driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_GcmDecryEx(HSM_CmdType *pCmd, const HSMCom_GcmDecryptExType *pCfg); + +/** + * @brief MD5 + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg MD5 parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_Md5(HSM_CmdType *pCmd, const HSMCom_Md5Type *pCfg); + + +/** + * @brief SM3 + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg SM3 parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_Sm3(HSM_CmdType *pCmd, const HSMCom_Sm3Type *pCfg); + + +/** + * @brief Increase Monotonic Counter + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg MonotonicCounter parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_MonotonicCounterIncrease(HSM_CmdType *pCmd, const HSMCom_MonCountType *pCfg); + + +/** + * @brief Read Monotonic Counter + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg MonotonicCounter parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_MonotonicCounterRead(HSM_CmdType *pCmd, const HSMCom_MonCountType *pCfg); + + +/** + * @brief Set Monotonic Counter Value + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg MonotonicCounter parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_MonotonicCounterSetValue(HSM_CmdType *pCmd, const HSMCom_MonCountType *pCfg); + + +/** + * @brief Read All Flex Counters + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg MonotonicCounter parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_MonotonicReadAllFlexCounters(HSM_CmdType *pCmd, const HSMCom_MonCountType *pCfg); + + +/** + * @brief Set Single Config + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg MonotonicCounter parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_MonotonicCounterSetSingleCfg(HSM_CmdType *pCmd, const HSMCom_MonCountType *pCfg); + + +/** + * @brief Get Single Config + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg MonotonicCounter parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_MonotonicCounterGetSingleCfg(HSM_CmdType *pCmd, const HSMCom_MonCountType *pCfg); + + +/** + * @brief Increase Monotonic Counter 2 + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg MonotonicCounter parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_MonotonicIncreaseCounter2(HSM_CmdType *pCmd, const HSMCom_MonCountType *pCfg); + + +/** + * @brief Read Monotonic Counter 2 + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg MonotonicCounter parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_MonotonicReadCounter2(HSM_CmdType *pCmd, const HSMCom_MonCountType *pCfg); + + +/** + * @brief Increase Monotonic Counter when equal + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg MonotonicCounter parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY When driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_MonotonicIncCountWhenEqu(HSM_CmdType *pCmd, const HSMCom_MonCountType *pCfg); + + +/** + * @brief LoadFirmware + * + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. Others, some error occur. + */ +HSM_StatusType HSM_LoadFirmware(HSM_CmdType *pCmd); + + +/** + * @brief RSA + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg RSA parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. Others, some error occur. + */ +HSM_StatusType HSM_Rsa(HSM_CmdType *pCmd, const HSMCom_RsaType *pCfg); + + +/** + * @brief RSA PSS Sign + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg RSA Sign parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY when driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_RSA_SSA_PSS_Sign(HSM_CmdType *pCmd, const HSMCom_RsaSsaPssSignType *pCfg); + + +/** + * @brief RSA PSS Verify + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg RSA Verify parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY when driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_RSA_SSA_PSS_Verify(HSM_CmdType *pCmd, const HSMCom_RsaSsaPssVerifyType *pCfg); + + +/** + * @brief RSA ES_PKCS1V15 Encrypt + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg RSA encrypt parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY when driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_RSA_SSA_ES_PKCS1V15_Encrypt(HSM_CmdType *pCmd, const HSMCom_RsaEsPkcs1V15EncryptType *pCfg); + + +/** + * @brief RSA ES_PKCS1V15 Decrypt + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg RSA decrypt parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY when driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_RSA_SSA_ES_PKCS1V15_Decrypt(HSM_CmdType *pCmd, const HSMCom_RsaEsPkcs1V15DecryptType *pCfg); + + +/** + * @brief RSA ES_PKCS1V15 Verify + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg RSA Verify parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY when driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_RSA_SSA_ES_PKCS1V15_Verify(HSM_CmdType *pCmd, const HSMCom_RsaSsaPkcs1V15VerifyType *pCfg); + + +/** + * @brief RSA ES PKCS1V15 Sign + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg RSA Verify parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY when driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_RSA_SSA_ES_PKCS1V15_Sign(HSM_CmdType *pCmd, const HSMCom_RsaSsaPkcs1V15SignType *pCfg); + + +/** + * @brief RSA ES OAEP Encrypt + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg RSA encrypt parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY when driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_RSA_SSA_ES_OAEP_Encrypt(HSM_CmdType *pCmd, const HSMCom_RsaEsOaepEncryptType *pCfg); + + +/** + * @brief RSA ES OAEP Decrypt + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg RSA decrypt parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY when driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_RSA_SSA_ES_OAEP_Decrypt(HSM_CmdType *pCmd, const HSMCom_RsaEsOaepDecryptType *pCfg); + + +/** + * @brief BigNumberCalc + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY when driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_BigNumberCalc(HSM_CmdType *pCmd, const HSMCom_BigNumberCalcType *pCfg); + + +/** + * @brief SMDH + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY when driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_SMDH(HSM_CmdType *pCmd, HSMCom_SmDHType *pCfg); + + +/** + * @brief ECDH + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY when driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_ECDH(HSM_CmdType *pCmd, HSMCom_ECDHType *pCfg); + + +/** + * @brief DH + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY when driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_DH(HSM_CmdType *pCmd, HSMCom_RsaDHType *pCfg); + + +/** + * @brief PBKDF2 + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY when driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_PBKDF2(HSM_CmdType *pCmd, HSMCom_Pbkdf2Type *pCfg); + + +/** + * @brief GMPBKDF + * @param pCmd point to the struct variable used to configure the mailbox information send to HSM core + * @param pCfg parameters for trigger the process + * @return HSM_StatusType HSM_STATUS_SUCCESS when succeed. HSM_STATUS_BUSY when driver is busy. Others, some error occur. + */ +HSM_StatusType HSM_GMPBKDF(HSM_CmdType *pCmd, HSMCom_GMpbkdfType *pCfg); + + +/**@}*/ + +/** @}*/ /* fc7xxx_driver_hsm */ + +#if defined(__cplusplus) +} +#endif + +#endif /* end of DRIVER_HSM_H_ */ diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_intm.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_intm.h new file mode 100644 index 0000000..b5280e4 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_intm.h @@ -0,0 +1,137 @@ +/** + * @file fc7xxx_driver_intm.h + * @author Flagchip + * @brief FC7240 INTM driver type definition and API + * @version 0.1.0 + * @date 2024-01-10 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-10 Flagchip084 N/A FC7240 release version + ******************************************************************************** */ + +#ifndef _DRIVER_INTM_H_ +#define _DRIVER_INTM_H_ + +#include "HwA_intm.h" + +typedef enum +{ + INTM_INSTANCE_0 = 0U, + INTM_INSTANCE_MAX = 1u +} INTM_InstanceType; + +typedef enum +{ + INTM_IRQ_MONITOR_0 = 0U, + INTM_IRQ_MONITOR_1 = 1U, + INTM_IRQ_MONITOR_MAX = 2U +} INTM_IrqMonitorType; + +typedef enum +{ + INTM_RETURN_OK = 0x00U, /*!< The INTM operation is succeeded */ + INTM_RETURN_E_NOT_OK = 0x01U, /*!< The INTM operation is failed */ + INTM_RETURN_E_ALREADY_INIT = 0x02U, /*!< The INTM has been initialized. */ + INTM_RETURN_E_UNINIT = 0x03U, /*!< The INTM is not initialized */ + INTM_RETURN_E_PARAM = 0x04U /*!< The INTM parameter is incorrect or out of range. */ +} INTM_ReturnType; + +typedef enum +{ + INTM_INTERRUPT_MODE_ACTIVE = 0x00U, /*!< INTM is configured as active mode */ + INTM_INTERRUPT_MODE_INACTIVE /*!< INTM is configured as inactive mode */ +} INTM_InterruptModeType; + +/** + * @brief INTM Channel ISR callback function prototype + * + */ +typedef void (*INTM_ISRCallbackType)(void); + +typedef struct +{ + INTM_InterruptModeType eMode; /*!< INTM active mode */ + bool bEnReset; /*!< Enable Reset */ + bool bEnInterrupt; /*!< Enable Interrupt */ + uint32_t u32SrcDelayCnt; /*!< Enable Interrupt */ + uint16_t u16IrqNumber; /*!< Monitored interrupt number */ + INTM_ISRCallbackType pIntmIsrCallback; /*!< INTM interrupt callback. */ +} INTM_InitType; + +/** + * @brief Init the INTM. + * @param eInstance INTM instance. + * @param eIrqMonitorIndex Monitor index. + * @param pInitCfg Init Configuration. + * @return INTM_ReturnType INTM Status. + */ +INTM_ReturnType INTM_Init(INTM_InstanceType eInstance, INTM_IrqMonitorType eIrqMonitorIndex, INTM_InitType *pInitCfg); + +/** + * @brief Enable INTM. + * + * @param eInstance INTM instance. + * @param bEnable Enable INTM. + * @return INTM_ReturnType INTM Status. + */ +INTM_ReturnType INTM_enable(INTM_InstanceType eInstance, bool bEnable); + +/** + * @brief Start INTM inactive mode. + * @param eInstance INTM instance. + * @param eIrqMonitorIndex Monitor index. + * @return INTM_ReturnType INTM Status. + */ +INTM_ReturnType INTM_StartInactiveMode(INTM_InstanceType eInstance, INTM_IrqMonitorType eIrqMonitorIndex); + +/** + * @brief + * @param eInstance INTM instance. + * @param eIrqMonitorIndex Monitor index. + * @return INTM_ReturnType INTM Status. + */ +INTM_ReturnType INTM_StopInactiveMode(INTM_InstanceType eInstance, INTM_IrqMonitorType eIrqMonitorIndex); + +/** + * @brief Write the interrupt acknowledge. + * + * @param eInstance INTM instance. + * @param u16IrqNumber Interrupt nunmber. + * @return INTM_ReturnType INTM Status. + */ +INTM_ReturnType INTM_SetAcknowledge(INTM_InstanceType eInstance, uint16_t u16IrqNumber); + +/** + * @brief Return counter value. + * + * @param eInstance INTM instance. + * @param eIrqMonitorIndex Monitor index. + * @return Counter value. + */ +uint32_t INTM_GetCounterValue(INTM_InstanceType eInstance, INTM_IrqMonitorType eIrqMonitorIndex); + +/** + * @brief Clear the interrupt flag. + * + * @param eInstance INTM instance. + * @param eIrqMonitorIndex Monitor index. + */ +INTM_ReturnType INTM_ClearIntFlag(INTM_InstanceType eInstance, INTM_IrqMonitorType eIrqMonitorIndex); + +/** + * @brief Get the timeout flag. Return true if INTM_TMR value has exceeded the INTM_LATR value. + * + * @param eInstance INTM instance. + * @param eIrqMonitorIndex Monitor index. + * @return Timeout flag. + */ +bool INTM_GetTimeoutStatus(INTM_InstanceType eInstance, INTM_IrqMonitorType eIrqMonitorIndex); + +#endif /* end of _DRIVER_INTM_H_ */ diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_ism.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_ism.h new file mode 100644 index 0000000..4867328 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_ism.h @@ -0,0 +1,249 @@ +/** + * @file fc7xxx_driver_ism.h + * @author Flagchip084 + * @brief FC7xxx ISM driver type definition and API + * @version 0.2.0 + * @date 2023-02-13 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2022-11-18 Flagchip084 N/A First version for FC7xxx + * 0.2.0 2023-02-13 Flagchip084 N/A FC7xxx release version + ******************************************************************************** */ + +#ifndef _DRIVER_FC7XXX_DRIVER_ISM_H_ +#define _DRIVER_FC7XXX_DRIVER_ISM_H_ +#include "device_header.h" +#include "HwA_ism.h" +/** + * @addtogroup fc7xxx_driver_ism + * @{ + */ + +#define ISM_ECM_CHANNEL(x) (1<<(x)) +#define ISM_LAM_CHANNEL(x) (1<<(x)) +#define ISM_FPC_CHANNEL(x) (1<<(x)) + +typedef enum +{ + ISM_INSTANCE_0 = 0U, /*!< ISM instance 0 is selected. */ +} ISM_InstanceType; + +typedef enum +{ + FPC_RISING_GLITCH_DETECTED = 0x01U, /*!< PFC Rising Glitch Detected. */ + FPC_FALLING_GLITCH_DETECTED = 0x02U /*!< PFC Falling Glitch Detected. */ +} FPC_GlitchDetectType; + +/** + * @brief ISM Channel ISR callback function prototype + * + */ +typedef void (*ISM_EventISRCallbackType)(const uint16_t u16LamStatus, const uint8_t u8EcmStatus); + +/** + * @brief FPC Channel Glitch dectection ISR callback function prototype + * + */ +typedef void (*FPC_ISRCallbackType)(const uint32_t u32Status); + +/** + * @brief LAM Channel Overflow ISR callback function prototype + * + */ +typedef void (*LAM_ISRCallbackType)(void); + +typedef struct +{ + + bool bIntEnable; + ISM_EventISRCallbackType pEventIsrCallback; +} ISM_InitCfgType; + +typedef struct +{ + bool bGlitchIntEnable; + ISM_FPC_EdgeDetectModeType eFallingDetectMode; + ISM_FPC_EdgeDelayModeType eFallingDelayNode; + ISM_FPC_EdgeDetectModeType eRisingDetectMode; + ISM_FPC_EdgeDelayModeType eRisingDelayNode; + uint16_t u32ThresholdValue; + FPC_ISRCallbackType pFpcIsrCallback; +} ISM_FpcCfgType; + +typedef struct +{ + bool bOvflIntEnable; + uint8_t u8SrcSel; + uint8_t u8MonSel; + ISM_LAM_InvertEventWindowType eInvWin; + ISM_LAM_EventWindowEdgeType eWinEdgSel; + ISM_LAM_EventWindowSelectType eEvtWinSel; + ISM_LAM_RunModeSelectType eRunMode; + ISM_LAM_MonitorSourceType eMonSrcSel; + ISM_LAM_InvertMonitorType eInvMon; + ISM_LAM_InvertReferenceType eInvRef; + uint32_t u32EvtCntThreshold; + LAM_ISRCallbackType pLamOverFlowIsrCallback; +} ISM_LamCfgType; + +/** + * @brief Init the ISM. + * + * @param pInitConfig ISMInstance initial configuration. + */ +void ISM_Init(const ISM_InitCfgType *pInitConfig); + +/** + * @brief Get the channels mask of ECM that has event happened. + * + * @return Channels mask. + */ +uint8_t ISM_GetEcmEventHappenedChannels(void); + +/** + * @brief Get the channels mask of LAM that has event happened. + * + * @return Channels mask. + */ +uint16_t ISM_GetLamEventHappenedChannels(void); + +/** + * @brief Clear the channels status of ECM that has event happened. + * + * @param u8Channels Channels mask. + */ +void ISM_ClearEcmEventHappenedChannels(uint8_t u8Channels); + +/** + * @brief Clear the channels status of LAM that has event happened. + * + * @param u16Channels Channels mask. + */ +void ISM_ClearLamEventHappenedChannels(uint16_t u16Channels); + +/** + * @brief Enable or disable ISM. + * + * @param bEnable Enable value. + */ +void ISM_Enable(bool bEnable); + +/** + * @brief Enable or disable ISM interrupt. + * + * @param bEnable Enable value. + */ +void ISM_InterruptEnable(bool bEnable); + +/** + * @brief ENable LAM overflow interrupt. + * + * @param u8LamIndex LAM index. + * @param bEnable Enable value. + */ +void ISM_LamOverflowInterruptEnable(uint8_t u8LamIndex, bool bEnable); + +/** + * @brief Enable LAM Channel. + * + * @param u8LamIndex LAM index. + * @param bEnable Enable value. + */ +void ISM_LamEnable(uint8_t u8LamIndex, bool bEnable); + +/** + * @brief Config the LAM channel. + * + * @param u8LamIndex LAM index. + * @param pConfig LAM configuration. + */ +void ISM_LamConfig(uint8_t u8LamIndex, const ISM_LamCfgType *pConfig); + +/** + * @brief Enable FPC glitch interrupt. + * + * @param u8FpcIndex FPC index. + * @param bEnable Enable value. + */ +void ISM_FpcGlitchInterruptEnable(uint8_t u8FpcIndex, bool bEnable); + +/** + * @brief Enable FPC channel. + * + * @param u8FpcIndex FPC index. + * @param bEnable Enable value. + */ +void ISM_FpcEnable(uint8_t u8FpcIndex, bool bEnable); + +/** + * @brief Config the FPC channel. + * + * @param u8FpcIndex FPC index. + * @param pConfig FPC configuration. + */ +void ISM_FpcConfig(uint8_t u8FpcIndex, const ISM_FpcCfgType *pConfig); + +/** + * @brief Enable ECM system event + * + * @param u32Channels Channel masks. + * @param bEnable Enable value. + */ +void ISM_EnableEcmSystemEvent(uint32_t u32Channels, bool bEnable); + +/** + * @brief Enable LAM system event + * + * @param u32Channels Channel masks. + * @param bEnable Enable value. + */ +void ISM_EnableLamSystemEvent(uint32_t u32Channels, bool bEnable); + +/** + * @brief Enable LAM system event + * + * @param u32LamIndex Lam channel index. + * @param u32EcmIndex Ecm channel index. + * @param u8EventCount Threshold of the ECM channel counter value. + */ +void ISM_EcmEventConfig(uint8_t u32LamIndex, uint8_t u32EcmIndex, uint8_t u8EventCount); + +/** + * @brief Clears the value of the LAM counter. + * + * @param u32LamIndex Lam channel index. + */ +void ISM_ClearLamStatusCounter(uint8_t u8LamIndex); + +/** + * @brief Gets the value of the LAM counter when a LAM event is triggered. + * + * @param u32LamIndex Lam channel index. + * @return Counter value. + */ +uint32_t ISM_GetLamStatusCounter(uint8_t u8LamIndex); + +/** + * @brief Clears LAM Timer Overflow Flag. + * + * @param u32LamIndex Lam channel index. + */ +void ISM_ClearLamStatusOvfl(uint8_t u8LamIndex); + +/** + * @brief Gets LAM Timer Overflow Flag. + * + * @param u32LamIndex Lam channel index. + * @return Overflow flag. + */ +bool ISM_GetLamStatusOvfl(uint8_t u8LamIndex); + +/** @}*/ /* fc7xxx_driver_ism. */ +#endif diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_lin.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_lin.h new file mode 100644 index 0000000..107ba23 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_lin.h @@ -0,0 +1,427 @@ +/** + * @file fc7xxx_driver_lin.h + * @author Flagchip0122 + * @brief FC7xxx LIN driver type definition and API + * @version 0.1.0 + * @date 2023-12-26 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-26 Flagchip0122 N/A First version for FC7xxx + ******************************************************************************** */ + +#ifndef _DRIVER_FC4XXX_DRIVER_LIN_H_ +#define _DRIVER_FC4XXX_DRIVER_LIN_H_ + +#include "HwA_fcuart.h" +#include "device_header.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** + * @addtogroup fc4xxx_driver_lin + * @{ + */ + +/** + * @brief LIN status type use in API. + */ +typedef enum +{ + LIN_STATUS_SUCCESS = 0x00U, /*!< API execute successfully */ + LIN_STATUS_ERROR, /*!< API excute error */ + LIN_STATUS_BUSY, /*!< currently instance busy. */ + LIN_STATUS_TIMEOUT, /*!< timeout status */ + LIN_STATUS_PARAM_ERROR, /*!< Parameter error. */ + LIN_STATUS_NOT_INIT, /*!< LIN node has not been initialized. */ + LIN_STATUS_USEED, /*!< LIN node has not been initialized. */ + LIN_STATUS_NOT_START, /*!< LIN node has not been started. */ + LIN_STATUS_UNSUPPORTED, /*!< unsupport status */ +} LIN_StatusType; + +/** + * @brief LIN node type use in API, master or slave. + */ +typedef enum +{ + LIN_NODE_MASTER, /*!< LIN Master node. */ + LIN_NODE_SLAVE, /*!< LIN slave node. */ +} LIN_NodeType; + +/** + * @brief A callback function to get the interval time value in nanoseconds. + */ +typedef uint32_t (*lin_get_interval_time_t)(uint32_t *nanoSeconds); + +/** + * @brief Structure for LIN hardware configurations. + */ +typedef struct +{ + LIN_NodeType nodeMode; /*!< Node mode as Master node or Slave node. 0: slave 1: master */ + uint32_t baudRate; /*!< baudrate configurations for LIN protocol. */ + uint32_t clockSrcFreq; /*!< LIN instance clock source frequency. */ + lin_get_interval_time_t getIntervalTimeValueCallback; /*!< Callback function to get time interval in nanoseconds */ + uint8_t *classicPID; /*!< List of PIDs use classic checksum */ + uint8_t numOfClassicPID; /*!< Number of PIDs use classic checksum */ +} lin_config_t; + +/** + * @brief Types for an event related Identifier. + */ +typedef enum +{ + LIN_NO_EVENT = 0x00U, /*!< No event occurred. */ + LIN_WAKEUP_SIGNAL, /*!< Wakeup signal */ + LIN_BAUDRATE_ADJUSTED, /*!< Baudrate was adjusted in slave autobaud mode. */ + LIN_RECV_BREAK_FIELD_OK, /*!< Break Field was received */ + LIN_SYNC_OK, /*!< Sync field is correct */ + LIN_SYNC_ERROR, /*!< Sync field is incorrect */ + LIN_PID_OK, /*!< PID receive correct */ + LIN_PID_ERROR, /*!< PID receive incorrect */ + LIN_FRAME_ERROR, /*!< Frame receive error */ + LIN_READBACK_ERROR, /*!< Readback words are incorrect */ + LIN_CHECKSUM_ERROR, /*!< Checksum byte error */ + LIN_TX_COMPLETED, /*!< TX data completed */ + LIN_RX_COMPLETED, /*!< rx data completed */ + LIN_RX_OVERRUN, /*!< RX overflow occurred */ + LIN_TIMEOUT, /*!< RX overflow occurred */ +} lin_event_id_t; + +/*! + * @brief Define type for an enumerating LIN Node state. + */ +typedef enum +{ + LIN_NODE_STATE_UNINIT = 0x00U, /*!< LIN hardware uninitialized state */ + LIN_NODE_STATE_SLEEP_MODE, /*!< LIN node in sleep mode state */ + LIN_NODE_STATE_IDLE, /*!< LIN node in idle state */ + LIN_NODE_STATE_SEND_BREAK_FIELD, /*!< LIN node in send break field state */ + LIN_NODE_STATE_RECV_SYNC, /*!< LIN node in receive the synchronization byte state */ + LIN_NODE_STATE_SEND_PID, /*!< LIN node in rend PID state */ + LIN_NODE_STATE_RECV_PID, /*!< LIN node in receive PID state */ + LIN_NODE_STATE_RECV_DATA, /*!< LIN node in receive data state */ + LIN_NODE_STATE_RECV_DATA_COMPLETED, /*!< LIN node in receive data completed state */ + LIN_NODE_STATE_SEND_DATA, /*!< LIN node in send data state */ + LIN_NODE_STATE_SEND_DATA_COMPLETED /*!< LIN node in send data completed state */ +} lin_node_state_t; + +/*! + * @brief LIN Driver callback function type + */ +typedef void (*lin_callback_t)(uint8_t u8LinIndex, void *linState); + +/*! + * @brief Runtime state of the LIN driver. + * + * Note that the caller provides memory for the driver state structures during + * initialization because the driver does not statically allocate memory. + * Implements : lin_state_t_Class + */ +typedef struct +{ + const uint8_t *txBuff; /*!< The buffer of data being sent. */ + uint8_t *rxBuff; /*!< The buffer of received data. */ + uint8_t cntByte; /*!< To count number of bytes already transmitted or received. */ + volatile uint8_t txSize; /*!< The remaining number of bytes to be transmitted. */ + volatile uint8_t rxSize; /*!< The remaining number of bytes to be received. */ + uint8_t checkSum; /*!< Checksum byte. */ + volatile bool isTxBusy; /*!< True if the LIN interface is transmitting frame data. */ + volatile bool isRxBusy; /*!< True if the LIN interface is receiving frame data. */ + volatile bool isBusBusy; /*!< True if there are data, frame headers being transferred on bus */ + volatile bool isTxBlocking; /*!< True if transmit is blocking transaction. */ + volatile bool isRxBlocking; /*!< True if receive is blocking transaction. */ + lin_callback_t Callback; /*!< Callback function to invoke after receiving a byte or transmitting a byte. */ + uint8_t currentId; /*!< Current ID */ + uint8_t currentPid; /*!< Current PID */ + volatile lin_event_id_t currentEventId; /*!< Current ID Event */ + volatile lin_node_state_t currentNodeState; /*!< Current Node state */ + volatile uint32_t timeoutCounter; /*!< Value of the timeout counter */ + volatile bool timeoutCounterFlag; /*!< Timeout counter flag */ +} lin_xfer_state_t; + +/**@}*/ +/** + * @name API declaration for LIN driver. + * + */ +/**@{*/ + +/** + * @brief Init the LIN instance for LIN network. This API will help initialize the FCUART to expect state, + * but will nots start the TX&RX function, if users want to start the LIN protocol transfer, please + * call the function LIN_DrvStart() after this API is called. + * + * @param u8LinIndex LIN hardware instance, 0U... + * @param pConfig Configuration for LIN hardware, must not be null. + * @return operation status: + * - LIN_STATUS_SUCCESS : operation is successfully. + * - LIN_STATUS_USEED : The instance has been used, user should use another instance or de-initialize this instance firstly. + * - LIN_STATUS_ERROR : the baudrate has not been set successfully. + */ +LIN_StatusType LIN_DrvInit(uint8_t u8LinIndex, lin_config_t *pConfig); + +/** + * @brief De-Init the LIN instance used by LIN network. + * This API will help disable the fcuart interrupts and stop the TX/RX transfer. + * + * @return operation status: + * - LIN_STATUS_SUCCESS : operation is successfully. + * - LIN_STATUS_NOT_INIT : The instance has not been initialized. + */ +LIN_StatusType LIN_DrvDeInit(uint8_t u8LinIndex); + +/** + * @brief Help users get the default configuration of LIN node. users should provide the configuration structure + * in app code, and transfer the ptr address to driver code. uses can also set this parameters in the application code + * as designed. + * + * @param u8NodeMode LIN node mode select, 0 for slave mode and 1 for master mode. + * @param pConfig default configuration for LIN node, must not be null. + */ +void LIN_DrvGetDefaultConfig(LIN_NodeType eNodeMode, lin_config_t *pConfig); + +/** + * @brief Start LIN node transfer, this API should be called after LIN hardware has been initialized, and must + * be called before starting a LIN node transfer. Users should provide a tansfer structure for storing the + * transfer state, ant LIN node state changed will be stored to this xfer state. + * + * @param u8LinIndex LIN hardware instance, 0U... + * @param pXferState Transfer state structure which will help store the trasnfer state. + * @return operation status: + * - LIN_STATUS_SUCCESS : operation is successfully. + * - LIN_STATUS_PARAM_ERROR: the parameter setting maybe not correct, maybe instance has bot been initialized. + */ +LIN_StatusType LIN_DrvStart(uint8_t u8LinIndex, lin_xfer_state_t *pXferState); + +/** + * @brief This function will help install callback function that used by application code. + * users can handle some needed operations in driver code or get some important states. + * or uses can also setting this in transfer state structure. + * + * @param u8LinIndex LIN hardware instance, 0U... + * @param callback user's callbak function that need be called in driver code. + * @return operation status: + * - LIN_STATUS_SUCCESS : operation is successfully. + * - LIN_STATUS_NOT_INIT : The instance required has bot been initialized. + */ +LIN_StatusType LIN_DrvInstallUserCallback(uint8_t u8LinIndex, lin_callback_t callback); + +/** + * @brief This function will help users send a header in master node which will help start a new + * frame transfer. please do not used this API will LIN instance is configured as slave node. + * This API will make a parity ID, and only send a break field to the protocol, all the other + * filed like sync filed and pid byte will be handled in FCUART IRQHandler. more details can + * refer to IRQ routine. + * + * @param u8LinIndex LIN hardware instance, 0U... + * @param u8Id The ID data that useds need to send in header. + * @return operation status: + * - LIN_STATUS_SUCCESS : operation is successfully. + * - LIN_STATUS_NOT_INIT : Instance required has not been intialized. + * - LIN_STATUS_UNSUPPORTED : Current node is slave not, could not send header to protocol. + * - LIN_STATUS_BUSY : Bus busy which means node is sending or receiving another frame. + */ +LIN_StatusType LIN_DrvSendHeader(uint8_t u8LinIndex, uint8_t u8Id); + +/** + * @brief This API will help users send a frame data through LIN protocol, and will return only when + * all frame data has been sent to the protocol, or while timeout occurred, so please configure + * the u32TimeOut parameter as needed. And currentlyt this API has not implement the OS feature, + * so do not call this API in interrupt routine, otherwise, routine maybe halted by this API. + * + * @param u8LinIndex LIN hardware instance, 0U... + * @param pTxBuf TX buffer whihc will be sent to protocol, MUST NOT BE NULL. + * @param u8Length bytes lengths in TX buffer. + * @param u32TimeOut Timeout value, 0 indicates timeout feature is not used, in unit of millieconds. + * @return operation status: + * - LIN_STATUS_SUCCESS : operation is successfully. + * - LIN_STATUS_NOT_INIT : Instance required has not been initialized. + * - LIN_STATUS_BUSY : Bus busy, node is transfer state. + */ +LIN_StatusType LIN_DrvSendFrameBlocking(uint8_t u8LinIndex, uint8_t *pTxBuf, uint8_t u8Length, uint32_t u32TimeOut); + +/** + * @brief This API will help users send a frame data through LIN protocol, this API will return immediately. + * data will be stored in txbuffer, users can check the transmit status while data is sending. + * + * @param u8LinIndex LIN hardware instance, 0U... + * @param pTxBuf TX buffer whihc will be sent to protocol, MUST NOT BE NULL. + * @param u8Length bytes lengths in TX buffer. + * @param u32TimeOut Timeout value, 0 indicates timeout feature is not used, in unit of millieconds. + * @return operation status: + * - LIN_STATUS_SUCCESS : operation is successfully. + * - LIN_STATUS_NOT_INIT : Instance required has not been initialized. + * - LIN_STATUS_BUSY : Bus busy, node is transfer state. + */ +LIN_StatusType LIN_DrvSendFrameNonBlocking(uint8_t u8LinIndex, uint8_t *pTxBuf, uint8_t u8Length); + +/** + * @brief This API will help users get the LIN transfer status while data is sending. and will also + * help user get remainning byte in transfer still need sending in buffer. + * + * @param u8LinIndex LIN hardware instance, 0U... + * @param pRemainBytes Address to be stored the remain byte value, should not be NULL. + * @return operation status: + * - LIN_STATUS_TIMEOUT : node transfer timeout occurred. + * - LIN_STATUS_SUCCESS : transfer complete. + * - LIN_STATUS_BUSY : transfer is going + */ +LIN_StatusType LIN_DrvGetTransmitStatus(uint8_t u8LinIndex, uint8_t *pRemainBytes); + +/** + * @brief This API will help users receive frame data through LIN protocol, this API will return only when + * all frame data has been received from the protocol, or while timeout occurred, so please configure + * the u32TimeOut parameter as needed. And currently, this API has not implement the OS feature, + * so do not call this API in interrupt routine, otherwise, routine maybe halted by this API. + * + * @param u8LinIndex LIN hardware instance, 0U... + * @param pRxBuf RX buffer which will be received from protocol, MUST not be NULL. + * @param u8Length bytes lengths should be received. + * @param u32TimeOut Timeout value, 0 indicates timeout feature is not used, in millieconds. + * @return operation status: + * - LIN_STATUS_SUCCESS : operation is successfully. + * - LIN_STATUS_NOT_INIT : Instance has not been initialized + * - LIN_STATUS_BUSY : Bus in busy state, need wait bus idle. + * - LIN_STATUS_TIMEOUT : Timeout occurred, data received may not successful. + */ +LIN_StatusType LIN_DrvReceiveFrameBlocking(uint8_t u8LinIndex, uint8_t *pRxBuf, uint8_t u8Length, uint32_t u32TimeOut); + +/** + * @brief This API will help users received frame data through LIN protocol, this API will return immediately. + * data will be stored in rxbuffer, users can check the receive status while using this API. + * + * @param u8LinIndex LIN hardware instance, 0U... + * @param pRxBuf RX buffer which will be received from protocol, MUST not be NULL. + * @param u8Length bytes lengths should be received. + * @param u32TimeOut Timeout value, 0 indicates timeout feature is not used, in millieconds. + * @return operation status: + * - LIN_STATUS_SUCCESS : operation is successfully. + * - LIN_STATUS_NOT_INIT : Instance has not been initialized + * - LIN_STATUS_BUSY : Bus in busy state, need wait bus idle. + * - LIN_STATUS_TIMEOUT : Timeout occurred, data received may not successful. + */ +LIN_StatusType LIN_DrvReceiveFrameNonBlocking(uint8_t u8LinIndex, uint8_t *pRxBuf, uint8_t u8Length); + +/** + * @brief This API will help users get the LIN transfer status while data is receiving. and will also + * help user get remainning byte in transfer still need receiving in buffer. + * + * @param u8LinIndex LIN hardware instance, 0U... + * @param pRemainBytes Address to be stored the remain byte value, should not be NULL. + * @return operation status: + * - LIN_STATUS_SUCCESS : operation is successfully. + * - others are not successfully. + */ +LIN_StatusType LIN_DrvGetReceiveStatus(uint8_t u8LinIndex, uint8_t *pRemainBytes); + +/** + * @brief Abort transfer both sending or receiving data, actually, call this APU will enter IDLE state. + * will stop end and receive even data transfer is on going. + * + * @param u8LinIndex LIN hardware instance, 0U... + * @return operation status: + * - LIN_STATUS_SUCCESS : operation is successfully. + */ +LIN_StatusType LIN_DrvAbortTransfer(uint8_t u8LinIndex); + +/** + * @brief This API should be called while no data is transferring, once this API is called, node will + * enter sleep mode, TX/RX and interrupts will also be disabled, and node will wait a wakeup signal + * on the protocol. This API will enable receive active interrupt, once a wakeup signal triggered, + * routine will entern uart IRQHandler to handle this case, and then wakeup the LIN node. + * + * @param u8LinIndex LIN hardware instance, 0U... + * @return operation status: + * - LIN_STATUS_SUCCESS : operation is successfully. + */ +LIN_StatusType LIN_DrvGoToSleepMode(uint8_t u8LinIndex); + +/** + * @brief THis API will help confgure the mode into IDLE state. In IDLE state, node will enable receive interrupt and break + * field detect interrupt, slave node will wait the break field from master node, master node will prepare to send a + * new break filed to start a new frame. + * + * @param u8LinIndex LIN hardware instance, 0U... + * @return operation status: + * - LIN_STATUS_SUCCESS : operation is successfully. + */ +LIN_StatusType LIN_DrvGoToIdleMode(uint8_t u8LinIndex); + +/** + * @brief Sending a wakeup signal to the protocol, all LIN network nodes receive this signal will + * wakeup from sleep mode. Actually, the master will send a character which will cause a 150us + * larger active level to the protocol. while receiving this signal, LIN node will wake up + * from sleep mode. + * + * @param u8LinIndex LIN hardware instance, 0U... + * @return operation status: + * - LIN_STATUS_SUCCESS : operation is successfully. + * - LIN_STATUS_NOT_INIT : Instance required is not initialized. + * - LIN_STATUS_BUSY ：LIN node state is not correct, need update state firstly. + */ +LIN_StatusType LIN_DrvSendWakeupSignal(uint8_t u8LinIndex); + +/** + * @brief Get the LIN node state. + * + * @param u8LinIndex LIN hardware instance, 0U... + * @return the node current state, refer to @lin_node_state_t + */ +lin_node_state_t LIN_DrvGetNodeState(uint8_t u8LinIndex); + +/** + * @brief This API should be called by user's application code, and the timeout periods should be 500ms once. + * Better to provide a timer IRQhandler to call this APIs 500ms onces. + * + * @param u8LinIndex LIN hardware instance, 0U... + * @return operation status: + * - LIN_STATUS_SUCCESS : operation is successfully. + * - others are not successfully. + */ +LIN_StatusType LIN_DrvTimeOutService(uint8_t u8LinIndex); + +/** + * @brief This API will help users set the timeout counter with one API, users should use this feature with LIN_DrvTimeOutService() + * called every fixed time. + * + * @param u8LinIndex LIN hardware instance, 0U... + * @param u32TimeOutValue Timeout value. + * @return operation status: + * - LIN_STATUS_SUCCESS : operation is successfully. + * - LIN_STATUS_NOT_INIT : Instance required is not initialized. + */ +LIN_StatusType LIN_DrvSetTimeOutCounter(uint8_t u8LinIndex, uint32_t u32TimeOutValue); + +/** + * @brief This API will help users get the Node timeout flag status. + * + * @param u8LinIndex LIN hardware instance, 0U... + * @return true for timeout occurred, false indicate no timeout. + */ +bool LIN_DrvGetTimeOutFlag(uint8_t u8LinIndex); + +/** + * @brief This is LIN IRQ routine code, uses should call this in the FCUART IRQhandler code. please must implement + * the feature in application code. + * + * @param u8LinIndex LIN hardware instance, 0U... + */ +void LIN_DrvIRQHandler(uint8_t u8LinIndex); + +/**@}*/ + +/** @}*/ /* fc4xxx_driver_lin */ +#if defined(__cplusplus) +} +#endif + +#endif /* _DRIVER_FC4XXX_DRIVER_LIN_H_ */ diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_lu.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_lu.h new file mode 100644 index 0000000..6b7166c --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_lu.h @@ -0,0 +1,138 @@ +/** + * @file fc7xxx_driver_lu.h + * @author Flagchip0103 + * @brief FC7xxx LU driver header file + * @version 0.1.0 + * @date 2023-12-19 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-19 Flagchip0103 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef _DRIVER_FC4XXX_DRIVER_LU_H_ +#define _DRIVER_FC4XXX_DRIVER_LU_H_ +#include "HwA_lu.h" +/** + * @addtogroup fc7xxx_driver_lu + * @{ + */ + +#define LU_AOI_IN_N_CFG_N(AoiIn, AoiInN, InNCfgNType) ((((uint32_t)(InNType) & 0x3U) << (((uint32_t)3U - (uint32_t)(AoiInN)) << 3U)) << (((uint32_t)3U - (uint32_t)(AoiIn)) << 3U)) +#define LU_AOI_IN_N_CFG_N_MASK(AoiIn, AoiInN) (((uint32_t)0x3U << (((uint32_t)3U - (uint32_t)(AoiInN)) << 3U)) << (((uint32_t)3U - (uint32_t)(AoiIn)) << 3U)) + +#define LU_AOI_IN_CFG(AoiInN, CfgNType) ((((uint32_t)(CfgNType) & 0x3U) << (((uint32_t)3U - (uint32_t)(AoiInN)) << 1U))) +#define LU_AOI_IN_CFG_MASK(AoiInN) ((((uint32_t)0x3U) << (((uint32_t)3U - (uint32_t)(AoiInN)) << 1U))) + +#define LU_AOI_IN_N_CFG(AoiIn, InNType) ((((uint32_t)(InNType) & 0xFFU) << (((uint32_t)3U - (uint32_t)(AoiIn)) << 3U))) +#define LU_AOI_IN_N_CFG_MASK(AoiIn) ((((uint32_t)0xFFU) << (((uint32_t)3U - (uint32_t)(AoiIn)) << 3U))) + +#define LU_SYNC_CONTROL_INPUT_N(InputN, value) ((uint32_t)(value) << (InputN)) + +/** @brief LU return structure */ +typedef enum +{ + LU_STATUS_SUCCESS = 0U, + LU_STATUS_PARAM_INVALID = 1U +} LU_StatusType; + +/** @brief LU IN type */ +typedef enum +{ + LU_AOI_IN_0 = 0U, + LU_AOI_IN_1, + LU_AOI_IN_2, + LU_AOI_IN_3, +} LU_AoiInType; + +/** @brief LU IN(n) configuration type */ +typedef enum +{ + LU_AOI_IN_N_A = 0U, + LU_AOI_IN_N_B, + LU_AOI_IN_N_C, + LU_AOI_IN_N_D +} LU_AoiInNType; + +/** @brief LU IN(n) configuration */ +typedef enum +{ + FORCE_ITEM_AS_ZERO = 0U, /**< force item as logic zero */ + PASS_THROUGH_ITEM, /**< pass through item */ + COMPLEMENT_ITEM, /**< complement item */ + FORCE_ITEM_AS_ONE /**< force item as logic one */ +} LU_InModeType; + +/** @brief LU output initialization value */ +typedef enum +{ + LU_OUTPUT_INIT_ZERO = 0U, + LU_OUTPUT_INIT_ONE, + LU_OUTPUT_INIT_DISABLE +} LU_OutputInitValueType; + +/** @brief LU IN(n) configuration register type */ +typedef struct +{ + LU_InModeType eInNACfg; /**< AOI IN(n) A configuration */ + LU_InModeType eInNBCfg; /**< AOI IN(n) B configuration */ + LU_InModeType eInNCCfg; /**< AOI IN(n) C configuration */ + LU_InModeType eInNDCfg; /**< AOI IN(n) D configuration */ +} LU_InConfigType; + +/** @brief LU AOI IN(n) configuration type */ +typedef struct +{ + LU_InConfigType tIn0Config; /**< AOI IN0 configuration */ + LU_InConfigType tIn1Config; /**< AOI IN1 configuration */ + LU_InConfigType tIn2Config; /**< AOI IN2 configuration */ + LU_InConfigType tIn3Config; /**< AOI IN3 configuration */ +} LU_AoiConfigType; + +/** @brief LU LG inputs synchronous control */ +typedef struct +{ + bool bInputNA; /**< LU IN(n) A sync control */ + bool bInputNB; /**< LU IN(n) B sync control */ + bool bInputNC; /**< LU IN(n) C sync control */ + bool bInputND; /**< LU IN(n) D sync control */ +} LU_InputsSyncCtrlType; + +/** @brief LU initialization type */ +typedef struct +{ + LU_LgType eLgNum; /**< LG number */ + LU_AoiConfigType tAoi0Config; /**< aoi0 configuration */ + LU_AoiConfigType tAoi1Config; /**< aoi1 configuration */ + LU_InputsSyncCtrlType tSyncCtrl; /**< inputs sync control, when set, would sync input product with bus clock */ + LU_BypassModeType eAoiMode; /**< AOI mode */ + LU_ConfigModeType eFFMode; /**< flip-flop mode */ + LU_OutputInitValueType eFFInitValue; /**< flip-flop initial value */ + LU_InputNType eFbMode; /**< feedback override control in JKFF mode */ + uint8_t u8Aoi0FiltCnt; /**< aoi0 input filter sample count */ + uint8_t u8Aoi0Period; /**< aoi0 input filter sample period */ + uint8_t u8Aoi1FiltCnt; /**< aoi1 input filter sample count */ + uint8_t u8Aoi1Period; /**< aoi1 input filter sample period */ +} LU_InitType; + +/* global functions */ +/** + * @brief Initialize LU instance + * @param pInitStruct LU initialization structure + * @return LU return type + */ +LU_StatusType LU_Init(const LU_InitType *const pInitStruct); + +/** + * @brief De-initialize LU instance + */ +void LU_Deinit(void); + +/** @}*/ /* fc7xxx_driver_lu */ +#endif diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_mam.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_mam.h new file mode 100644 index 0000000..9f1a303 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_mam.h @@ -0,0 +1,109 @@ +/** + * @file fc7xxx_driver_mam.h + * @author Flagchip + * @brief FC7xxx MAM driver type definition and API + * @version 0.2.0 + * @date 2023-02-08 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-02-08 Flagchip095 N/A First version for FC7240 + ******************************************************************************** */ +#ifndef _DRIVER_FC7XXX_DRIVER_MAM_H_ +#define _DRIVER_FC7XXX_DRIVER_MAM_H_ + +#include "device_header.h" +#include "HwA_mam.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** + * @brief The master index of the mam peripheral + * + */ +typedef enum { + MAM_MASTER_CPU0_AXIM = 0, + MAM_MASTER_CPU0_AHBP, + MAM_MASTER_DMA0, + MAM_MASTER_HSM, + MAM_MASTER_NUM +} MAM_Master_Type; + +/** + * @brief The mam index + * + */ +typedef enum { + NVM_MAM0 = 0, + RAM_MAM1, + PERIPHERAL_MAM2 +} MAM_Index_Type; + + +/** + * @brief the MAM slave information + * + */ +typedef struct +{ + uint8_t error; + uint32_t block_num; +} MAM_Inf_Type; + + +typedef enum { + FORBID_READ_ACCESS = 1, + FORBID_WRITE_ACCESS = 2, + FORBID_EXECUTE_ACCESS = 4, + FORBID_USER_ACCESS = 8 +} MAM_Forbid_Access_Type; + +/** + * @brief The function of software reset to MAM + * + * @param number mam index + */ +void MAM_Reset(MAM_Index_Type idx); + +/** + * @brief The function to enable MAM watch dog + * + * @param1 Master The master index + * + * @param2 u32Addr The input address + */ +uint8_t MAM_Enable_Wdg(MAM_Master_Type Master,uint32_t u32Addr); + +/** + * @brief The function to disable MAM watch dog + * + * @param1 Master The master index + * + * @param2 u32Addr The input address + */ +uint8_t MAM_Disable_Wdg(MAM_Master_Type Master,uint32_t u32Addr); + +/** + * @brief The function to config MAM + * + * @param1 Master The master index + * + * @param2 u32Addr The input address + * + * @param3 u32Val The value to set + */ +uint8_t MAM_Config(MAM_Master_Type Master, uint32_t u32Addr, uint32_t u32Val); + +#if defined(__cplusplus) +} +#endif + +#endif /* end of DRIVER_UART_H_ */ diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_mb.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_mb.h new file mode 100644 index 0000000..12b55e4 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_mb.h @@ -0,0 +1,201 @@ +/** + * @file fc7xxx_driver_mb.h + * @author Flagchip070 + * @brief FC7xxx Mailbox driver type definition and API + * @version 0.1.0 + * @date 2022-11-15 + * + * @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/******************************************************************************** +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2022-11-15 Flagchip070 N/A First version for FC7300 +********************************************************************************/ + +#ifndef _DRIVER_fc7xxx_driver_mb_H_ +#define _DRIVER_fc7xxx_driver_mb_H_ + +#include "device_header.h" +#include "HwA_mb.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** + * @addtogroup fc7xxx_driver_mb + * @{ + */ + + +/** + * @brief Mailbox channel bit flag of security information + * + */ +#define MB_CHANNEL_STATUS_SECURE 2u + +/** + * @brief Mailbox channel bit flag of processing information + * + */ +#define MB_CHANNEL_STATUS_PRIVILEGED 1u + +/** + * @name Mailbox channel bit mask + * @brief Bit of channel indicate channel number + * + * @{ + */ +#define MB_CHANNEL_MASK_NONE 0u +#define MB_CHANNEL_MASK_ALL 0xFFFFu +#define MB_CHANNEL_MASK(ch) ((uint32_t)(1ul << (ch))) +/** @}*/ + +/** + * @brief Mailbox has not initialized, the core index will be MB_NOT_INIT + * + */ + +#define MB_NOT_INIT 0xFFFFFFFFu +/** + * @brief Mailbox operation return values + * + */ +typedef enum { + MB_STATUS_SUCCESS = 0u, /*!< The Mailbox operation is success */ + MB_STATUS_FAILED, /*!< The Mailbox operation is failed */ + MB_STATUS_PARAM_ERROR, /*!< The Mailbox operation is failed because of parameter error*/ + MB_STATUS_ALREADY_INITED, /*!< The Mailbox operation is failed because of + Mailbox has already initialized*/ + MB_STATUS_UNINIT, /*!< The Mailbox operation is failed because of + Mailbox has not initialized*/ + MB_STATUS_LOCKED, /*!< The Mailbox channel is locked */ + MB_STATUS_NO_REQUEST, /*!< No valid requests */ +} MB_StatusType; + +/** + * @brief Configuration of a Mailbox request + * + */ +typedef struct +{ + uint8_t u8Channel; /*!< The selected Mailbox channel */ + uint8_t u8RequestMask; /*!< The mask for issuing requests */ + uint8_t u8DoneMasterIndex; /*!< The master ID of the core that generates a done event */ + uint8_t u8DoneMask; /*!< The mask for the done events */ + uint8_t u8AutoReleaseFlag; /*!< Automatically clear the channel lock enable bit */ + uint8_t u8Reserved[3]; + uint32_t aData[2]; /*!< Sending data */ +} MB_RequestType; + +/** + * @brief Configuration of a receiving request + * + */ +typedef struct +{ + uint8_t u8Channel; /*!< The selected Mailbox channel */ + uint8_t u8MasterCoreIndex; /*!< Buffer to store the master core index */ + uint8_t u8ChannelStatus; /*!< Buffer to store the security information + and processing mode of the channel*/ + uint8_t u8Reserved; + uint32_t aData[2]; /*!< Buffer to store the receiving data */ +} MB_ReceiveType; + +/** + * @brief Configuration of the Mailbox + * + */ +typedef struct +{ + uint32_t u32EventMask; /*!< Mask for the request events and done events */ + uint32_t u32IntrMask; /*!< Mask for enable the interrupts */ + void (*pRequestCallback)(MB_ReceiveType *pReceive); /*!< Callback of the request events */ + void (*pDoneCallback)(uint32_t u32ChannelMask); /*!< Callback of the done events */ +} MB_InitType; + +/** + * @brief Initialize the Mailbox + * + * @param pInitConfig the configurations of the Mailbox + * @return MB_StatusType whether the operation is successfully + */ +MB_StatusType MB_Init(const MB_InitType *pInitConfig); +/** + * @brief De-initialize the Mailbox + * + * @return MB_StatusType whether the operation is successfully + */ +MB_StatusType MB_DeInit(void); +/** + * @brief Attempt to acquire a Mailbox channel + * + * @param u32Channel the selected Mailbox channel + * @return MB_StatusType whether the operation is successfully + */ +MB_StatusType MB_LockChannel(uint32_t u32Channel); +/** + * @brief Release a Mailbox channel + * + * @param u32Channel the selected Mailbox channel + * @return MB_StatusType whether the operation is successfully + */ +MB_StatusType MB_ReleaseChannel(uint32_t u32Channel); +/** + * @brief Get the index of the core + * + * @return uint32_t index of the core + */ +uint32_t MB_GetCoreIndex(void); +/** + * @brief Launching a Mailbox request + * + * @param pRequest Configuration of the request + * @return MB_StatusType whether the operation is successfully + */ +MB_StatusType MB_SendRequest(MB_RequestType *pRequest); +/** + * @brief Attempt to receive a request from the selected channel + * + * @param pReceive Configuration of the receiving request + * @return MB_StatusType whether the operation is successfully + */ +MB_StatusType MB_ReceiveChannel(MB_ReceiveType *pReceive); +/** + * @brief Software clears channel lock + * + * @param u32Channel the selected Mailbox channel + * @return MB_StatusType whether the operation is successfully + */ +MB_StatusType MB_UnlockChannel(uint32_t u32Channel); +/** + * @brief Polling the done event of all channels + * + * @param u32PollMask mask of the done event + * @param pDoneMask buffer to store the done events + * @return MB_StatusType whether the operation is successfully + */ +MB_StatusType MB_PollDone(uint32_t u32PollMask, uint32_t *pDoneMask); +/** + * @brief Issue a done event to the selected channel + * + * @param u32Channel the selected Mailbox channel + * @param u32DoneMask The mask for issuing done + * @return MB_StatusType whether the operation is successfully + */ +MB_StatusType MB_DoneChannel(uint32_t u32Channel, uint32_t u32DoneMask); +/** + * @brief Interrupt IRQ handle of Mailbox + * + */ +void MB_IRQProcess(void); +/** @}*/ /* fc7xxx_driver_mb */ +#if defined(__cplusplus) +} +#endif +#endif diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_mpu.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_mpu.h new file mode 100644 index 0000000..7937cf7 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_mpu.h @@ -0,0 +1,242 @@ +/** + * @file fc7xxx_driver_mpu.h + * @author Flagchip085 + * @brief FC7xxx MPU driver type definition and API + * @version 0.1.0 + * @date 2024-01-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + * @details The MPU only checks the CPU master access to CTCM and DTCM memory. When access denied, it will cause MemManage Interrupt. + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240 + ******************************************************************************** */ +#ifndef _DRIVER_FC7XXX_DRIVER_MPU_H_ +#define _DRIVER_FC7XXX_DRIVER_MPU_H_ + +#include "HwA_mpu.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** + * @addtogroup fc7xxx_driver_mpu + * @{ + */ + +/** + * @brief Status enumeration used by Flagchip MPU Driver + * + */ +typedef enum { + MPU_STATUS_SUCCESS = 0, /*!< MPU API execute successfully */ + MPU_STATUS_ERROR, /*!< Some error occur in MPU API */ +} MPU_StatusType; + +/** + * @brief + * + */ +typedef enum { + MPU_EN_HFNMI_PRIVDEF_NONE = 0U, /*!< disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault, + MPU is disabled during hard fault, NMI, and FAULTMASK handlers */ + MPU_EN_HARDFAULT_NMI = 1, /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */ + MPU_EN_PRIVILEGED_DEFAULT = 2, /*!< enables use of the default memory map as a background region for privileged software accesses. + When enabled, the background region acts as if it is region number -1. + Any region that is defined and enabled has priority over this default map. */ + MPU_EN_HFNMI_PRIVDEF = 3, /*!< same with MPU_EN_HARDFAULT_NMI | MPU_EN_PRIVILEGED_DEFAULT */ +} MPU_EnableOptionType; + +/** + * @brief Enable Status for Sub-region configuration + * + */ +typedef enum { + MPU_REGION_SRD_ENABLE_SUBREGION = 0, /*!< sub-region is enabled */ + MPU_REGION_SRD_DISABLE_SUBREGION = 1, /*!< sub-region is not enabled */ +} MPU_RegionSubDisableType; + +/** + * @brief Configure the code in the region whether can be execute + * + */ +typedef enum { + MPU_REGION_XN_EXECUTE_ENABLE = 0x0, + MPU_REGION_XN_EXECUTE_DISABLE = 0x1 +} MPU_RegionExecuteNeverType; + +/** + * @brief region Shareable configuration + * + */ +typedef enum { + MPU_REGION_S_DISABLE = 0, + MPU_REGION_S_ENABLE = 1 +} MPU_RegionShareableType; + +/** + * @brief Region Cacheable configuration + * + */ +typedef enum { + MPU_REGION_C_DISABLE = 0, + MPU_REGION_C_ENABLE = 1 +} MPU_RegionCacheableType; + +/** + * @brief Region Bufferable configuration + * + */ +typedef enum { + MPU_REGION_B_DISABLE = 0, + MPU_REGION_B_ENABLE = 1 +} MPU_RegionBufferableType; + +/** + * @brief Region Type Extend Level configuration + * + */ +typedef enum { + MPU_REGION_TEX_LEVEL_0 = 0, + MPU_REGION_TEX_LEVEL_1 = 1, + MPU_REGION_TEX_LEVEL_2 = 2 +} MPU_RegionTypeExtLevelType; + +/** + * @brief Region size enumeration for enabling MPU region + * + */ +typedef enum { + MPU_REGION_SIZE_32B = 0x04, + MPU_REGION_SIZE_64B = 0x05, + MPU_REGION_SIZE_128B = 0x06, + MPU_REGION_SIZE_256B = 0x07, + MPU_REGION_SIZE_512B = 0x08, + MPU_REGION_SIZE_1KB = 0x09, + MPU_REGION_SIZE_2KB = 0x0A, + MPU_REGION_SIZE_4KB = 0x0B, + MPU_REGION_SIZE_8KB = 0x0C, + MPU_REGION_SIZE_16KB = 0x0D, + MPU_REGION_SIZE_32KB = 0x0E, + MPU_REGION_SIZE_64KB = 0x0F, + MPU_REGION_SIZE_128KB = 0x10, + MPU_REGION_SIZE_256KB = 0x11, + MPU_REGION_SIZE_512KB = 0x12, + MPU_REGION_SIZE_1MB = 0x13, + MPU_REGION_SIZE_2MB = 0x14, + MPU_REGION_SIZE_4MB = 0x15, + MPU_REGION_SIZE_8MB = 0x16, + MPU_REGION_SIZE_16MB = 0x17, + MPU_REGION_SIZE_32MB = 0x18, + MPU_REGION_SIZE_64MB = 0x19, + MPU_REGION_SIZE_128MB = 0x1A, + MPU_REGION_SIZE_256MB = 0x1B, + MPU_REGION_SIZE_512MB = 0x1C, + MPU_REGION_SIZE_1GB = 0x1D, + MPU_REGION_SIZE_2GB = 0x1E, + MPU_REGION_SIZE_4GB = 0x1F +} MPU_RegionSizeType; + +/** + * @brief MPU Permission Enumeration + * + */ +typedef enum { + MPU_REGION_AP_NO_ACCESS = 0x00, /*!< Any access generates a permission fault */ + MPU_REGION_AP_PRIV_RW = 0x01, /*!< Privileged access only, unprivileged no access */ + MPU_REGION_AP_PRIV_RW_URO = 0x02, /*!< Any unprivileged write generates a permission fault */ + MPU_REGION_AP_FULL_ACCESS = 0x03, /*!< Full access */ + MPU_REGION_AP_PRIV_RO = 0x05, /*!< Privileged read-only, unprivileged no access */ + MPU_REGION_AP_PRIV_RO_URO = 0x06 /*!< Privileged and unprivileged read-only */ +} MPU_RegionAccessPermissionType; + + +typedef enum { + MPU_REGION_NUMBER_0 = 0x0, /*!< lowest priority */ + MPU_REGION_NUMBER_1 = 0x1, + MPU_REGION_NUMBER_2 = 0x2, + MPU_REGION_NUMBER_3 = 0x3, + MPU_REGION_NUMBER_4 = 0x4, + MPU_REGION_NUMBER_5 = 0x5, + MPU_REGION_NUMBER_6 = 0x6, + MPU_REGION_NUMBER_7 = 0x7, + MPU_REGION_NUMBER_8 = 0x8, + MPU_REGION_NUMBER_9 = 0x9, + MPU_REGION_NUMBER_10 = 0xA, + MPU_REGION_NUMBER_11 = 0xB, + MPU_REGION_NUMBER_12 = 0xC, + MPU_REGION_NUMBER_13 = 0xD, + MPU_REGION_NUMBER_14 = 0xE, + MPU_REGION_NUMBER_15 = 0xF /*!< highest priority */ +} MPU_RegionNumberType; + + +typedef struct { + uint32_t u32BaseAddr; /*!< the start address of region, the least significant 5 bits should be 0 */ + MPU_RegionSizeType eRegionSize; /*!< region size */ + MPU_RegionAccessPermissionType eAccessPermission; /*!< region access permission */ + MPU_RegionExecuteNeverType eExecuteNever; /*!< region data can be execute or not */ + MPU_RegionTypeExtLevelType eTypeExtLevel; /*!< region type extend level */ + MPU_RegionShareableType eShareable; /*!< region shareable */ + MPU_RegionCacheableType eCacheable; /*!< region cacheable */ + MPU_RegionBufferableType eBufferable; /*!< region bufferable */ + MPU_RegionSubDisableType eSubRegionDis_0; /*!< sub-region 0 disable or not */ + MPU_RegionSubDisableType eSubRegionDis_1; /*!< sub-region 1 disable or not */ + MPU_RegionSubDisableType eSubRegionDis_2; /*!< sub-region 2 disable or not */ + MPU_RegionSubDisableType eSubRegionDis_3; /*!< sub-region 3 disable or not */ + MPU_RegionSubDisableType eSubRegionDis_4; /*!< sub-region 4 disable or not */ + MPU_RegionSubDisableType eSubRegionDis_5; /*!< sub-region 5 disable or not */ + MPU_RegionSubDisableType eSubRegionDis_6; /*!< sub-region 6 disable or not */ + MPU_RegionSubDisableType eSubRegionDis_7; /*!< sub-region 7 disable or not */ +} MPU_RegionConfigurationType; + + +/** + * @brief Check the MPU exist or not + * + * @return MPU_StatusType if exist return MPU_STATUS_SUCCESS, others not exist + */ +MPU_StatusType MPU_CheckExist(void); + +/** + * @brief Enable the MPU + * + * @param eOption Enable Options + */ +void MPU_Enable(MPU_EnableOptionType eOption); + +/** + * @brief Disable MPU + * + */ +void MPU_Disable(void); + +/** + * @brief Disable region + * + * @param eRegion Region index + * @return MPU_StatusType MPU_STATUS_SUCCESS when disable successfully, others fail + */ +MPU_StatusType MPU_RegionDisable(MPU_RegionNumberType eRegion); + +/** + * @brief Enable region + * + * @param eRegion Region index + * @param pConfig Region Configuration Parameter + * @return MPU_StatusType MPU_STATUS_SUCCESS when disable successfully, others fail + */ +MPU_StatusType MPU_RegionEnable(MPU_RegionNumberType eRegion, const MPU_RegionConfigurationType *pConfig); + + +/** @} */ /* fc7xxx_driver_mpu */ +#if defined(__cplusplus) +} +#endif +#endif /* _DRIVER_FC7XXX_DRIVER_MPU_H_ */ diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_msc.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_msc.h new file mode 100644 index 0000000..cc96c5d --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_msc.h @@ -0,0 +1,402 @@ +/** + * @file fc7xxx_driver_msc.h + * @author Flagchip + * @brief FC7240 MSC driver type definition and API + * @version 0.1.0 + * @date 2024-01-10 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-10 Flagchip084 N/A FC7240 release version + ******************************************************************************** */ + +#ifndef _DRIVER_FC7XXX_DRIVER_MSC_H_ +#define _DRIVER_FC7XXX_DRIVER_MSC_H_ +#include "device_header.h" +#include "HwA_msc.h" +/** + * @addtogroup fc7xxx_driver_msc + * @{ +. */ + +typedef enum +{ + MSC_RETURN_OK = 0x00U, /*!< The SENT operation is succeeded */ + MSC_RETURN_E_NOT_OK = 0x01U, /*!< The SENT operation is failed */ + MSC_RETURN_E_PARAM = 0x04U, /*!< The SENT parameter is incorrect or out of range. */ +} MSC_ReturnType; + +typedef enum +{ + MSC_RDR0 = 0x0U, + MSC_RDR1 = 0x1U, + MSC_RDR2 = 0x2U, + MSC_RDR3 = 0x3U, + MSC_RDRx_COUNT = 0x4U +} MSC_RDRxIndexType; + +typedef enum +{ + MSC_INSTANCE_0 = 0U, /*!< MSC instance 0 is selected. */ + MSC_INSTANCE_1 = 1U /*!< MSC instance 1 is selected. */ +} MSC_InstanceType; + +typedef enum +{ + MSC_RFIE_DISABLE = 0x0U, /*!< Interrupt generation disabled. */ + MSC_RFIE_MODE1 = 0x1U, /*!< The interrupt is generated when data is received and written into the RDRx. */ + MSC_RFIE_MODE2 = 0x2U, /*!< The interrupt is generated when received data is not equal to 0. */ + MSC_RFIE_MODE3 = 0x3U /*!< The interrupt is generated when data is received and written into register RDR3. */ +} MSC_RFIEModeType; + +typedef enum +{ + MSC_DFIE_DISABLE = 0x0U, /*!< Disable. */ + MSC_DFIE_MODE1 = 0x1U, /*!< Interrupt is generated when the last data bit has been shifted. */ + MSC_DFIE_MODE2 = 0x2U /*!< Interrupt is generated when the first data bit has been shifted. */ +} MSC_DFIEModeType; + +/** + * @brief MSC Channel ISR callback function prototype + * + */ +typedef void (*MSC_ISRCallbackType)(const MSC_InstanceType eInstance); + +/** @brief MSC interrupt configure structure. */ +typedef struct +{ + bool bCFIntEnable; /*!< MSC_INCR[CFIE] bit, interrupt enable, if this bit asserted, command frame can lead the interrupt. */ + bool bTFIntEnable; /*!< MSC_INCR[TFIE] bit, interrupt enable, if this bit asserted, time frame can lead the interrupt. */ + MSC_RFIEModeType eRFIEMode; /*!< Interrupt mode of RFIE. */ + MSC_DFIEModeType eDFIEMode; /*!< Interrupt mode of DFIE. */ + bool bTOIntEnable; /*!< Enable the interrupt of timeout. */ + uint16_t u16TimeoutValue; /*!< Timeout value of timeout interrupt. */ + MSC_ISRCallbackType pReceiveFrameISRCallback; /*!< Receive frame ISR callback. */ + MSC_ISRCallbackType pTimeFrameISRCallback; /*!< Time Frame ISR callback. */ + MSC_ISRCallbackType pCommandFrameISRCallback; /*!< Command Frame ISR callback. */ + MSC_ISRCallbackType pDataFrameISRCallback; /*!< Data Frame ISR callback. */ + MSC_ISRCallbackType pReceiveTimeOutISRCallback; /*!< Data Frame ISR callback. */ +} MSC_InterruptCfgType; + +typedef enum +{ + MSC_SDI_SEL_SDI0 = 0x0U, /*!< SDI0 input is selected for SDI. */ + MSC_SDI_SEL_SDI1 = 0x1U, /*!< SDI1 input is selected for SDI. */ + MSC_SDI_SEL_SDI2 = 0x2U, /*!< SDI2 input is selected for SDI. */ + MSC_SDI_SEL_SDI3 = 0x3U, /*!< SDI3 input is selected for SDI. */ + MSC_SDI_SEL_SDI4 = 0x4U, /*!< SDI4 input is selected for SDI. */ + MSC_SDI_SEL_SDI5 = 0x5U, /*!< SDI5 input is selected for SDI. */ + MSC_SDI_SEL_SDI6 = 0x6U, /*!< SDI6 input is selected for SDI. */ + MSC_SDI_SEL_SDI7 = 0x7U /*!< SDI7 input is selected for SDI. */ +} MSC_SDISelectionType; + +typedef enum +{ + MSC_ENC_SEL_EN0 = 0x0U, /*!< EN0 is selected for ENC. */ + MSC_ENC_SEL_EN1 = 0x1U, /*!< EN1 is selected for ENC. */ + MSC_ENC_SEL_EN2 = 0x2U, /*!< EN2 is selected for ENC. */ + MSC_ENC_SEL_EN3 = 0x3U /*!< EN3 is selected for ENC. */ +} MSC_ENCSelectionType; + +typedef enum +{ + MSC_ENH_SEL_EN0 = 0x0U, /*!< EN0 is selected for ENH. */ + MSC_ENH_SEL_EN1 = 0x1U, /*!< EN1 is selected for ENH. */ + MSC_ENH_SEL_EN2 = 0x2U, /*!< EN2 is selected for ENH. */ + MSC_ENH_SEL_EN3 = 0x3U /*!< EN3 is selected for ENH. */ +} MSC_ENHSelectionType; + +typedef enum +{ + MSC_ENL_SEL_EN0 = 0x0U, /*!< EN0 is selected for ENL. */ + MSC_ENL_SEL_EN1 = 0x1U, /*!< EN1 is selected for ENL. */ + MSC_ENL_SEL_EN2 = 0x2U, /*!< EN2 is selected for ENL. */ + MSC_ENL_SEL_EN3 = 0x3U /*!< EN3 is selected for ENL. */ +} MSC_ENLSelectionType; + +typedef enum +{ + MSC_EN_SELECTION_0 = 0x00, /*!< EN0 is selected for ENX. */ + MSC_EN_SELECTION_1 = 0x01, /*!< EN1 is selected for ENX. */ + MSC_EN_SELECTION_2 = 0x02, /*!< EN2 is selected for ENX. */ + MSC_EN_SELECTION_3 = 0x03, /*!< EN3 is selected for ENX. */ +} Msc_ENxActiveType; + +typedef enum +{ + MSC_ENC = 0x00, + MSC_ENL = 0x01, + MSC_ENH = 0x02, +} Msc_ENxType; + +typedef enum +{ + MSC_FLC_ACTIVE_ON_FRAMES = 0x0U, /*!< FCL is actived only during the active phases of frames. */ + MSC_FLC_ALWAYS_ACTIVE = 0x1U /*!< FCL is always active whether or not a downstream frame is transmitted currently.. */ +} MSC_FCLControlType; + +typedef enum +{ + MSC_INPUT_IDENTICAL = 0x0U, /*!< SDI and SI signal polarities are identical. */ + MSC_INPUT_INVERTED = 0x1U /*!< SDI and SI signal polarities are inverted. */ +} MSC_InputPolarityType; + +typedef enum +{ + MSC_ENX_IDENTICAL = 0x0U, /*!< Enx and ENL, ENH, ENC signal polarities are identical (high active). */ + MSC_ENX_INVERTED = 0x1U /*!< ENx and ENL, ENH, ENC signal polarities are inverted (low active). */ +} MSC_ENxPolarityType; + +typedef enum +{ + MSC_SO_IDENTICAL = 0x0U, /*!< SOP and SO signal polarity is identical. */ + MSC_SO_INVERTED = 0x1U /*!< SOP and SO signal polarity is inverted. */ +} MSC_SOPolarityType; + +typedef enum +{ + MSC_FLC_IDENTICAL = 0x0U, /*!< FCLP and FCL polarity is identical. */ + MSC_FLC_INVERTED = 0x1U /*!< FCLP and FCL polarity is inverted. */ +} MSC_FCLpolarityType; + +typedef struct +{ + MSC_SDISelectionType eSDIsel; /*!< SDI seletion. */ + MSC_ENCSelectionType eENCSel; /*!< ENC seletion. */ + MSC_ENHSelectionType eENHSel; /*!< ENH seletion. */ + MSC_ENLSelectionType eENLSel; /*!< ENL seletion. */ + MSC_FCLControlType eFclCtrl; /*!< FCL Control. */ + MSC_InputPolarityType eSDIPol; /*!< SDI Polarity. */ + MSC_ENxPolarityType eENXPol; /*!< ENX Polarity. */ + MSC_SOPolarityType eSOPPol; /*!< SO Polarity. */ + MSC_FCLpolarityType eFCLPPol; /*!< FCL Polarity. */ +} MSC_IOControlInitType; + +typedef enum +{ + MSC_TRANS_SOURCE_DATA_REG = 0x0U, /*!< SSL[x] is taken from TCDAR.DL[x]. */ + MSC_TRANS_SOURCE_ALTIN = 0x2U, /*!< SSL[x] is taken from the ALTINL input line x. */ + MSC_TRANS_SOURCE_ALTIN_INV = 0x3U, /*!< SSL[x] is taken from the ALTINL input line x in inverted state. */ +} MSC_TransSourceType; + +typedef enum +{ + MSC_TRIGGER_MODE = 0x00U, /*!< Trigger work mode. */ + MSC_REPETITION_MODE = 0x01U /*!< Repetition work mode. */ +} MSC_WorkModeType; + +typedef enum +{ + MSC_EVEN_PARITY = 0x00U, /*!< Reception even parity. */ + MSC_ODD_PARITY = 0x01U /*!< Reception odd parity. */ +} MSC_ParityType; + +typedef enum +{ + MSC_RECEIVE_DISABLED = 0x00U, /*!< Receiving channel is disabled. */ + MSC_BAUDRATE_FMSC_DIV4 = 0x01U, /*!< Baud rate=fmsc/4. */ + MSC_BAUDRATE_FMSC_DIV8 = 0x02U, /*!< Baud rate=fmsc/8. */ + MSC_BAUDRATE_FMSC_DIV16 = 0x03U, /*!< Baud rate=fmsc/16. */ + MSC_BAUDRATE_FMSC_DIV32 = 0x04U, /*!< Baud rate=fmsc/32. */ + MSC_BAUDRATE_FMSC_DIV64 = 0x05U, /*!< Baud rate=fmsc/64. */ + MSC_BAUDRATE_FMSC_DIV128 = 0x06U, /*!< Baud rate=fmsc/128. */ + MSC_BAUDRATE_FMSC_DIV256 = 0x07U /*!< Baud rate=fmsc/256. */ +} MSC_ReceiveBaudRateType; + +typedef enum +{ + MSC_FRAME_12_BIT = 0x00U, /*!< 12-bit frame selected. */ + MSC_FRAME_16_BIT = 0x01U /*!< 16-bit frame selected. */ +} MSC_ReceiveFrameType; + +typedef struct +{ + uint8_t u8PassiveLength; /*!< Frame Passive length. */ + uint8_t u8PTFNumber; /*!< The number of passive time frames that are inserted in repetition mode between two data frames. */ + MSC_WorkModeType eWorkMode; /*!< MSC work mode. */ + uint8_t u8CommandBitLength; /*!< Bit length of command frame. */ + bool bSelSRH; /*!< Select SRH. */ + uint8_t u8SRHDataBitLength; /*!< Bit length of SRH. */ + bool bSelSRL; /*!< Select SRL. */ + uint8_t u8SRLDataBitLength; /*!< Bit length of SRL. */ + bool bDelayControl; /*!< Hardware Receive Interrupt Delay Control. */ + MSC_ParityType eParity; /*!< Parity mode. */ + MSC_ReceiveBaudRateType eBaudRate; /*!< Baudrate. */ + MSC_ReceiveFrameType eRsvFrameType; /*!< Frame type. */ +} MSC_InitCfgType; + +/** + * @brief Init the MSC. + * + * @param eInstance MSCInstance. + * @param pInitConfig MSCInstance initial configuration. + */ +MSC_ReturnType MSC_init(const MSC_InstanceType eInstance, const MSC_InitCfgType *pInitConfig); + +/** + * @brief Init the MSC interrupt. + * + * @param eInstance MSCInstance. + * @param pInteruptConfig MSCInstance interrupt configuration. + */ +void MSC_initInterrupt(const MSC_InstanceType eInstance, const MSC_InterruptCfgType *pInteruptConfig); + +/** + * @brief Select the transmitting sources. + * + * @param eInstance MSCInstance. + * @param u32SourceMask Transmitting sources. + * @param eSourceType Transmitting sources type. + */ +void MSC_SelTranmittingSource(const MSC_InstanceType eInstance, uint32_t u32SourceMask, MSC_TransSourceType eSourceType); + +/** + * @brief Set Emergency load value. + * + * @param eInstance MSCInstance. + * @param u32Value Emergency load value. + */ +void MSC_SetEmergencyLoad(const MSC_InstanceType eInstance, uint32_t u32Value); + +/** + * @brief Configure the MSC IO control. + * + * @param eInstance MSCInstance. + * @param pIOConfig MSC IO control configuration. + */ +void MSC_SetIOControl(const MSC_InstanceType eInstance, const MSC_IOControlInitType *pIOConfig); + +/** + * @brief Enable MSC. + * + * @param eInstance MSCInstance. + */ +void MSC_Enable(const MSC_InstanceType eInstance); + +/** + * @brief Disable MSC. + * + * @param eInstance MSCInstance. + */ +void MSC_Disable(const MSC_InstanceType eInstance); + +/** + * @brief MSC set data frame. + * + * @param eInstance MSCInstance. + * @param u32Data Data to be sent. + */ +void MSC_SetDataFrame(const MSC_InstanceType eInstance, uint32_t u32Data); + +/** + * @brief MSC send data frame. + * + * @param eInstance MSCInstance. + */ +void MSC_SendDataFrame(const MSC_InstanceType eInstance); + +/** + * @brief MSC send command frame. + * + * @param eInstance MSCInstance. + * @param u32Command command to be sent. + */ +void MSC_SendCommandFrame(const MSC_InstanceType eInstance, uint32_t u32Command); + +/** + * @brief Get the msc received data address. + * + * @param eInstance MSCInstance. + * @param eIndex Receive data register index. + * @return uint8_t Receiverd data address. + */ +uint8_t MSC_GetReceivedFrameAddr(const MSC_InstanceType eInstance, MSC_RDRxIndexType eIndex); + +/** + * @brief Get the msc received data. + * + * @param eInstance MSCInstance. + * @param eIndex Receive data register index. + * @param pData Received data value. + * @return MSC_ReceiveStatusType Status of getting received data. + */ +MSC_ReceiveStatusType MSC_GetReceivedFrame(const MSC_InstanceType eInstance, MSC_RDRxIndexType eIndex, uint8_t *pData); + +/** + * @brief Get the msc interrupt status. + * + * @param eInstance MSCInstance. + * @return uint32_t Interrupt status. + */ +uint32_t MSC_GetInterruptStatus(const MSC_InstanceType eInstance); + +/** + * @brief Get the msc interrupt status. + * + * @param eInstance MSCInstance. + * @param bEnable Enable transmit channel. + */ +void MSC_EnableTrasmit(const MSC_InstanceType eInstance, bool bEnable); + +/** + * @brief Enable the msc data frame interrupt. + * + * @param eInstance MSCInstance. + */ +void MSC_EnableDataFrameInterrupt(const MSC_InstanceType eInstance, bool bEnable); + +/** + * @brief Enable the msc command frame interrupt. + * + * @param eInstance MSCInstance. + */ +void MSC_EnableCommandFrameInterrupt(const MSC_InstanceType eInstance, bool bEnable); + +/** + * @brief Enable the msc time frame interrupt. + * + * @param eInstance MSCInstance. + */ +void MSC_EnableTimeFrameInterrupt(const MSC_InstanceType eInstance, bool bEnable); + +/** + * @brief Enable the msc receive interrupt. + * + * @param eInstance MSCInstance. + */ +void MSC_EnableReceiveInterrupt(const MSC_InstanceType eInstance, bool bEnable); + +/** + * @brief Enable the msc timeout interrupt. + * + * @param eInstance MSCInstance. + */ +void MSC_EnableTimeoutInterrupt(const MSC_InstanceType eInstance, bool bEnable); + +/** + * @brief Switch ENC/ENH/ENL active EN selection. + * @param eInstance MSCInstance. + * @param eEnx ENC/ENH/ENL. + * @param eENn ENX selection. + * @param u32TimeoutLoops Wait timeout if transmission is busy. + * @return + */ +MSC_ReturnType Msc_SwitchENXChannel(const MSC_InstanceType eInstance, Msc_ENxType eEnx, Msc_ENxActiveType eENn, uint32_t u32TimeoutLoops); + +/** + * @brief Switch the SDI Channel. + * @param eInstance MSCInstance. + * @param eSDIChannel SDI channel. + * @param u32TimeoutLoops Wait timeout if receiving is busy. + * @return + */ +MSC_ReturnType Msc_SwitchSDIChannel(const MSC_InstanceType eInstance, MSC_SDISelectionType eSDIChannel, uint32_t u32TimeoutLoops); + +/** @}*/ /* fc7xxx_driver_msc. */ +#endif diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_overlay.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_overlay.h new file mode 100644 index 0000000..d6921f6 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_overlay.h @@ -0,0 +1,172 @@ +/** + * @file fc7xxx_driver_overlay.h + * @author Flagchip + * @brief FC7xxx overlay driver type definition and API + * @version 0.1.0 + * @date 2023-12-25 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + */ + +/******************************************************************************** +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2023-12-25 Flagchip0038 N/A First version for FC7240 +********************************************************************************/ + +#ifndef _DRIVER_FC7XXX_DRIVER_OVERLAY_H_ +#define _DRIVER_FC7XXX_DRIVER_OVERLAY_H_ +#include "HwA_overlay.h" + +/** + * @addtogroup fc7xxx_driver_overlay + * @{ + */ + + +/** + * @brief Overlay Error Information + * + */ +typedef enum +{ + OVERLAY_ERROR_OK, /**< no error */ + OVERLAY_ERROR_ADDR, /**< error address */ + OVERLAY_ERROR_SIZE, /**< error size */ + OVERLAY_ERROR_FLAG, /**< error flag */ +} OVERLAY_ErrorType; + + +/** + * @brief Overlay Region parameters + * + */ +typedef struct +{ + uint32_t aOverlayRegionEn[OVERLYA_REGION_CNT]; /**< Overlay region enable array */ + uint32_t aOverlayRegionSrc[OVERLYA_REGION_CNT]; /**< Overlay region source array, pflash */ + uint32_t aOverlayRegionDst[OVERLYA_REGION_CNT]; /**< Overlay region destination array, sram */ + OVERLAY_OverlaySizeType aOverlayRegionSize[OVERLYA_REGION_CNT]; /**< Overlay region size array */ +}OVERLAY_OverlayRegionInitType; + +/** + * @brief FAR parameter + * + */ +typedef struct +{ + uint32_t u32FAREn; /**< Overlay region enable array */ + uint32_t u32FARDst; /**< Overlay region destination array, pflash, source always is 0x08000000 */ + uint32_t u32FARSize; /**< Overlay region size array, must align to 64KB */ +}OVERLAY_FARInitType; + + +/** + * @brief Error Info + * + */ +typedef struct +{ + uint8_t bError_FAR_SIZE_INTR; /**< bit 17, The FAR of size value is invalid */ + uint8_t bError_FAR_DST_OVERFLOW_INTR; /**< bit 16, FAR of destination region is overflow with size */ + uint8_t bError_FAR_DST_NO_FLASH_INTR; /**< bit 15, FAR of destination address is not flash */ + uint8_t bError_REGION2_D_CROS_INTR; /**< bit 14, The range of region 2 destination address is crossed with other region */ + uint8_t bError_REGION2_S_CROS_INTR; /**< bit 13, The range of region 2 source address is crossed with other region */ + uint8_t bError_REGION2_SIZE_INTR; /**< bit 12, The region 2 of size value is invalid */ + uint8_t bError_REGION2_DST_INTR; /**< bit 11, The region 2 of destination address is not aligned with size */ + uint8_t bError_REGION2_SRC_INTR; /**< bit 10, The region 2 of source address is not aligned with size */ + uint8_t bError_REGION1_D_CROS_INTR; /**< bit 9, The range of region 1 destination address is crossed with other region */ + uint8_t bError_REGION1_S_CROS_INTR; /**< bit 8, The range of region 1 source address is crossed with other region */ + uint8_t bError_REGION1_SIZE_INTR; /**< bit 7, The region 1 of size value is invalid */ + uint8_t bError_REGION1_DST_INTR; /**< bit 6, The region 1 of destination address is not aligned with size */ + uint8_t bError_REGION1_SRC_INTR; /**< bit 5, The region 1 of source address is not aligned with size */ + uint8_t bError_REGION0_D_CROS_INTR; /**< bit 4, The range of region 0 destination address is crossed with other region */ + uint8_t bError_REGION0_S_CROS_INTR; /**< bit 3, The range of region 0 source address is crossed with other region */ + uint8_t bError_REGION0_SIZE_INTR; /**< bit 2, The region 0 of size value is invalid */ + uint8_t bError_REGION0_DST_INTR; /**< bit 1, The region 0 of destination address is not aligned with size */ + uint8_t bError_REGION0_SRC_INTR; /**< bit 0, The region 0 of source address is not aligned with size */ +}OVERLAY_ErrorInfoType; + + +/** Overlay Setting Error callback type */ +typedef void (*OVERLAY_ErrorCallback_Type)(OVERLAY_ErrorInfoType u16ErrorFlag); + + +/** + * @brief Interrupt Parameter + * + */ +typedef struct +{ + uint32_t bEnableInterrupt; /**< Enable interrupt, 0 is disable, 1 is enable */ + OVERLAY_ErrorCallback_Type pCallBack; /**< Callback function for error interrupt */ +}OVERLAY_InterruptType; + + +/** + * @brief Overlay region initial function + * + * @param pOverlayInitCfg initial parameters + * @return ERROR_OK is ok, others are not ok + */ +OVERLAY_ErrorType OVERLAY_RegionInit(OVERLAY_OverlayRegionInitType *pOverlayInitCfg); + +/** + * @brief De-Init Overlay Region + * + * @return ERROR_OK is ok, others are not ok + */ +OVERLAY_ErrorType OVERLAY_RegionDeInit(void); + +/** + * @brief Far initial function + * + * @param pFarInitCfg initial parameters + * @return ERROR_OK is ok, others are not ok + */ +OVERLAY_ErrorType OVERLAY_FARInit(OVERLAY_FARInitType *pFarInitCfg); + +/** + * @brief De-Init FAR Region + * + * @return ERROR_OK is ok, others are not ok + */ +OVERLAY_ErrorType OVERLAY_FARDeInit(void); + +/** + * @brief Enable or Disable Interrupt + * + * @param pInterruptCfg interrupt config parameter + */ +void OVERLAY_SetInterrupt(OVERLAY_InterruptType *pInterruptCfg); + +/** + * @brief Get Error Info + * + * @param pErrorInfo error info point + */ +void OVERLAY_GetErrorInfo(OVERLAY_ErrorInfoType *pErrorInfo); + +/** + * @brief Clear Error Info + * + * @param pErrorInfo error info point + */ +void OVERLAY_ClrErrorInfo(OVERLAY_ErrorInfoType *pErrorInfo); + +/** + * @brief Call Me in Overlay Error interrupt handler + * + */ +void OVERLAY_ErrorInterruptRoutine(void); + + +/** @}*/ /* fc7xxx_driver_overlay */ + + +#endif + + diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_pcc.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_pcc.h new file mode 100644 index 0000000..40aaf5f --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_pcc.h @@ -0,0 +1,157 @@ +/** + * @file fc7xxx_driver_pcc.h + * @author Flagchip085 + * @brief FC7xxx PCC driver type definition and API + * @version 0.1.0 + * @date 2024-01-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240 + ******************************************************************************** */ +#ifndef _DRIVER_FC7XXX_DRIVER_PCC_H_ +#define _DRIVER_FC7XXX_DRIVER_PCC_H_ +#include "HwA_pcc.h" +/** + * @addtogroup fc7xxx_driver_pcc + * @{ + */ + + +#define PCC_MUX_MAX_NUMBER 8U + +/** @brief PCC clock list */ +typedef enum +{ + PCC_CLK_DMA0 = 0U, + PCC_CLK_DMAMUX0, + PCC_CLK_ROMC, + PCC_CLK_ERM0, + PCC_CLK_EIM0, + PCC_CLK_INTM0, + PCC_CLK_ISM0, + PCC_CLK_WDOG0, + PCC_CLK_TRGSEL0, + PCC_CLK_TRGSEL1, + PCC_CLK_TRGSEL2, + PCC_CLK_TRGSEL3, + PCC_CLK_CRC0, + PCC_CLK_CORDIC, + PCC_CLK_TSTMP0, + PCC_CLK_TSTMP1, + PCC_CLK_FCPIT0, + PCC_CLK_AONTIMER0, + PCC_CLK_RTC, + PCC_CLK_CMU0, + PCC_CLK_CMU1, + PCC_CLK_CMU2, + PCC_CLK_CMU3, + PCC_CLK_CMU4, + PCC_CLK_PTIMER0, + PCC_CLK_PTIMER1, + PCC_CLK_ADC0, + PCC_CLK_ADC1, + PCC_CLK_WKU0, + PCC_CLK_CMP0, + PCC_CLK_CMP1, + PCC_CLK_TMU0, + PCC_CLK_SENT0, + PCC_CLK_MB0, + PCC_CLK_FTU0, + PCC_CLK_FTU1, + PCC_CLK_FTU2, + PCC_CLK_FTU3, + PCC_CLK_FCSPI0, + PCC_CLK_FCSPI1, + PCC_CLK_FCSPI2, + PCC_CLK_FCIIC0, + PCC_CLK_FCUART0, + PCC_CLK_FCUART1, + PCC_CLK_FCUART2, + PCC_CLK_FCUART3, + PCC_CLK_LU0, + PCC_CLK_FREQM, + PCC_CLK_STCU, + PCC_CLK_FLEXCAN0, + PCC_CLK_FLEXCAN1, + PCC_CLK_WDOG1, + PCC_CLK_TRGSEL4, + PCC_CLK_TRGSEL5, + PCC_CLK_FCSPI3, + PCC_CLK_FCSPI4, + PCC_CLK_FCSPI5, + PCC_CLK_FTU4, + PCC_CLK_FTU5, + PCC_CLK_FTU6, + PCC_CLK_FTU7, + PCC_CLK_FCIIC1, + PCC_CLK_FCUART4, + PCC_CLK_FCUART5, + PCC_CLK_FCUART6, + PCC_CLK_FCUART7, + PCC_CLK_MSC0, + PCC_CLK_FLEXCAN2, + PCC_CLK_FLEXCAN3, + PCC_END_OF_CLOCKS +} PCC_ClkSrcType; + +/** + * @brief Pcc clock status +*/ +typedef enum +{ + PCC_STATUS_SUCCESS = 0U, + PCC_STATUS_CLOCK_INVALID = 1U, + PCC_STATUS_CONFIGURED_NOT_SUPPORT = 1U, +} PCC_StatusType; + +/** + * @brief define the PCC module initialization structure. + */ +typedef struct +{ + PCC_ClkSrcType eClockName; /*!< Peripheral clock */ + bool bEn; /*!< Peripheral clock enable or disable */ + PCC_ClkGateSrcType eClkSrc; /*!< Peripheral function clock source select */ + PCC_ClkDivType eDivider; /*!< Peripheral clock divider value */ +} PCC_CtrlType; + +/** + * @brief get PCC function clock status and value. + * + * @param pcc_ClkSrcType eClockName: used for choose PCC clock source to query. + * @return uint32_t Pcc function clock frequency, if PCC is not enable or do not have clock mux configuration, + * the function will return 0 + */ +uint32_t PCC_GetPccFunctionClock(const PCC_ClkSrcType eClockName); + +/** + * @brief get PCC interface clock status and value. + * + * @param pcc_ClkSrcType eClockName: used for choose PCC clock source to query. + */ +uint32_t PCC_GetPccInterfaceClock(const PCC_ClkSrcType eClockName); + +/** + * @brief set PCC one peripheral clock configuration. + * + * @param PCC_CtrlType* pConfig: the PCC initialize value point set by user. + * @return PCC_StatusType pcc function status + */ +PCC_StatusType PCC_SetPcc(const PCC_CtrlType *const pConfig); + +/** + * @brief Generate peripheral reset + * + */ +void PCC_GenPeripheralReset(const PCC_ClkSrcType eClockName); + + +/** @}*/ /* fc7xxx_driver_pcc */ +#endif diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_pmc.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_pmc.h new file mode 100644 index 0000000..57542e8 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_pmc.h @@ -0,0 +1,181 @@ +/* @file fc7xxx_driver_pmc.h +* @author Flagchip032 +* @brief FC7xxx PMC driver type definition and API +* @version 0.1.0 +* @date 2022-11-21 +* +* @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. +* +*/ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials Descriptions + * --------- ---------- ------------ --------------- + * 0.1.0 2022-11-21 Flagchip032 First version for FC7xxx + ******************************************************************************** */ +#ifndef _DRIVER_FC7XXX_DRIVER_PMC_H_ +#define _DRIVER_FC7XXX_DRIVER_PMC_H_ +#include "HwA_pmc.h" + +#if defined(__cplusplus) +extern "C" { +#endif + + +/** + * @addtogroup fc7xxx_driver_pmc + * @{ + */ + +/***************** typedef *********************/ +/** + * @brief PMC voltage flags. + * + */ +typedef enum +{ + PMC_HVD5V_FLAG = PMC_LVSCR_HVD5V_FLAG_MASK, /**< interrupt flag on V5 domain in FPM */ + PMC_HVD2P5V_FLAG = PMC_LVSCR_HVD2P5V_FLAG_MASK, /**< interrupt flag on V25 domain in FPM */ + PMC_HVD1P1V_FLAG = PMC_LVSCR_HVD1P1V_FLAG_MASK, /**< interrupt flag on V11 domain in FPM */ + PMC_LVD5V_FLAG = PMC_LVSCR_LVD5V_FLAG_MASK, /**< interrupt flag on V5 domain in FPM */ + PMC_LVD1P5V_FLAG = PMC_LVSCR_LVD1P5V_FLAG_MASK, /**< interrupt flag on V15 domain in FPM */ + PMC_HVD1P5V_FLAG = PMC_LVSCR_HVD1P5V_FLAG_MASK, /**< interrupt flag on V15 domain in FPM */ + PMC_LVR5V_FPM_FLAG = PMC_LVSCR_LVR5V_FPM_FLAG_MASK, /**< Low voltage reset flag of V5 domain in FPM */ + PMC_LVR5V_RPM_FLAG = PMC_LVSCR_LVR5V_RPM_FLAG_MASK, /**< Low voltage reset flag of V5 domain in RPM */ + PMC_LVR2P5V_FPM_FLAG = PMC_LVSCR_LVR2P5V_FPM_FLAG_MASK, /**< Low voltage reset flag of V25 domain in FPM */ + PMC_LVR2P5V_RPM_FLAG = PMC_LVSCR_LVR2P5V_RPM_FLAG_MASK, /**< Low voltage reset flag of V25 domain in RPM */ + PMC_LVR1P1V_FPM_FLAG = PMC_LVSCR_LVR1P1V_FPM_FLAG_MASK, /**< Low voltage reset flag of V11 domain in FPM */ + PMC_LVR1P1V_RPM_FLAG = PMC_LVSCR_LVR1P1V_RPM_FLAG_MASK, /**< Low voltage reset flag of V11 domain in RPM */ + PMC_POR_FLAG = PMC_LVSCR_POR_FLAG_MASK /**< POR flag */ +} PMC_FlagType; + +/** + * @brief PMC voltage status. + * + */ +typedef enum +{ + PMC_HVD5V_STATUS = PMC_LVSCR_HVD5V_STATUS_MASK, /**< HVD5V status on V5 domain in FPM */ + PMC_HVD2P5V_STATUS = PMC_LVSCR_HVD2P5V_STATUS_MASK, /**< HVD25 status on V25 domain in FPM */ + PMC_HVD1P1V_STATUS = PMC_LVSCR_HVD1P1V_STATUS_MASK, /**< HVD11 status on V11 domain in FPM */ + PMC_LVD5V_STATUS = PMC_LVSCR_LVD5V_STATUS_MASK, /**< LVD5V status on V5 domain in FPM */ + PMC_LVD1P5V_STATUS = PMC_LVSCR_LVD1P5V_STATUS_MASK, /**< LVD1P5V status on V15 domain in FPM */ + PMC_HVD1P5V_STATUS = PMC_LVSCR_HVD1P5V_STATUS_MASK, /**< HVD1P5V status on V15 domain in FPM */ + PMC_V15_LDO_STATUS = PMC_LVSCR_V15_STATUS(0U), /**< V15 is working on internal V15 LDO */ + PMC_V15_ON_BOARD_NPN_STATUS = PMC_LVSCR_V15_STATUS(1U), /**< V15 is working on internal V15 controller with on board NPN */ + PMC_V15_DRIVEN_BY_EXTERNAL_STATUS = PMC_LVSCR_V15_STATUS(2U) /**< V15 is driven by external driver such as on board DCDC, V15_CFG PAD is driven high */ +} PMC_StatusType; + +typedef void (*PMC_VolIntCallbackType)(void); + +/** @brief Pmc control type */ +typedef struct +{ + boolean bLvdIntEn; /**< bit9, low voltage detect interrupt enable */ + boolean bHvdIntEn; /**< bit8, high voltage detect interrupt enable */ + boolean b5VBMonEn; /**< bit6, VDD5V_B LVR monitor enable during RPM */ + boolean bV15CtrlEn; /**< bit5, V15 controller with on board NPN enable */ + boolean bV15AutoswEn; /**< bit4, V15 auto switch enable */ + boolean bRpmV25En; /**< bit3, V25 domain enable during RPM */ + PMC_VolIntCallbackType pIsrNotify; /**< interrupt notification */ +} PMC_CtrlType; + +/***************** macro *********************/ +/**< All flags of LVCSR MSASK */ +#define PMC_LVCSR_ALLFLAG_MASK (uint32_t)(PMC_LVSCR_HVD5V_FLAG_MASK|\ + PMC_LVSCR_HVD2P5V_FLAG_MASK|\ + PMC_LVSCR_HVD1P1V_FLAG_MASK|\ + PMC_LVSCR_LVD5V_FLAG_MASK|\ + PMC_LVSCR_LVD1P5V_FLAG_MASK|\ + PMC_LVSCR_HVD1P5V_FLAG_MASK|\ + PMC_LVSCR_LVR5V_FPM_FLAG_MASK|\ + PMC_LVSCR_LVR5V_RPM_FLAG_MASK|\ + PMC_LVSCR_LVR2P5V_FPM_FLAG_MASK|\ + PMC_LVSCR_LVR2P5V_RPM_FLAG_MASK|\ + PMC_LVSCR_LVR1P1V_FPM_FLAG_MASK|\ + PMC_LVSCR_LVR1P1V_RPM_FLAG_MASK|\ + PMC_LVSCR_POR_FLAG_MASK) + +#define PMC_LVCSR_ALLSTATUS_MASK (uint32_t)(PMC_LVSCR_HVD5V_STATUS_MASK|\ + PMC_LVSCR_HVD2P5V_STATUS_MASK|\ + PMC_LVSCR_HVD1P1V_STATUS_MASK|\ + PMC_LVSCR_LVD5V_STATUS_MASK|\ + PMC_LVSCR_LVD1P5V_STATUS_MASK|\ + PMC_LVSCR_HVD1P5V_STATUS_MASK|\ + PMC_LVSCR_V15_STATUS_MASK) + + + + + + +/***************** API *********************/ +/** + * @brief Get LVCSRRegister Value + * + * @return uint32_t LVCSRRegister Value + */ +uint32_t PMC_GetLVCSRRegister(void); +/** + * @brief Get All voltage flag + * + * @return uint32_t All voltage flag + */ +uint32_t PMC_GetAllVolFlag(void); + +/** + * @brief Get specific voltage flag + * + * @param eFlag Voltage flag + * @return boolean If return true, the specific voltage flag is 0, otherwise, the flag is 1. + */ +boolean PMC_GetSpecificVolFlag(const PMC_FlagType eFlag); + +/** + * @brief Clear all voltage flag + * + */ +void PMC_ClearAllVolFlag(void); + +/** + * @brief Clear specific voltage flag + * + * @param eFlag Voltage flag + */ +void PMC_ClearSpecificVolFlag(const PMC_FlagType eFlag); + +/** + * @brief Get All voltage status + * + * @return uint32_t All voltage status + */ +uint32_t PMC_GetAllVolStatus(void); + +/** + * @brief Get specific voltage status + * + * @param eStatus Specific voltage status + * @return boolean If return true, the specific voltage status is 0, otherwise, the status is 1. + */ +boolean PMC_GetSpecificVolStatus(const PMC_StatusType eStatus); + +/** + * @brief Configure Voltage + * + * @param pCtrl Configuration of voltage + */ +void PMC_ConfigVoltage(const PMC_CtrlType *const pCtrl); + +/** + * @brief Clear all PMC register + * + */ +void PMC_Deinit(void); + + +#if defined(__cplusplus) +} +#endif +/** @}*/ /* fc7xxx_driver_pmc */ +#endif diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_port.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_port.h new file mode 100644 index 0000000..d384331 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_port.h @@ -0,0 +1,239 @@ +/** + * @file fc7xxx_driver_port.h + * @author Flagchip + * @brief FC7xxx PORT driver type definition and API + * @version 0.1.0 + * @date 2023-2-14 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/******************************************************************************** +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2022/12/31 Flagchip0121 N/A First version for FC7240 +********************************************************************************/ +#ifndef _DRIVER_FC7XXX_DRIVER_PORT_H_ +#define _DRIVER_FC7XXX_DRIVER_PORT_H_ +#include "HwA_port.h" +#include +/** + * @addtogroup fc7xxx_driver_port + * @{ + */ + +/********* global define ************/ +/** @brief Max number of Port */ +#define MAX_PORT_NUM 5U + +/** @brief Max number of Port Pin */ +#define PORT_PIN_NUM_MAX (uint32_t)(MAX_PORT_NUM*PORT_PCR_COUNT) + +/** @brief number of Port Pin */ +#define PORT_PIN_NUM(port,pin) (((uint32_t)(port) << 5U)+(uint32_t)(pin)) + +#define PORT_PIN_0 ((uint32_t)0x00000001) /**< PORT Pin 0 select */ +#define PORT_PIN_1 ((uint32_t)0x00000002) /**< PORT Pin 1 select */ +#define PORT_PIN_2 ((uint32_t)0x00000004) /**< PORT Pin 2 select */ +#define PORT_PIN_3 ((uint32_t)0x00000008) /**< PORT Pin 3 select */ +#define PORT_PIN_4 ((uint32_t)0x00000010) /**< PORT Pin 4 select */ +#define PORT_PIN_5 ((uint32_t)0x00000020) /**< PORT Pin 5 select */ +#define PORT_PIN_6 ((uint32_t)0x00000040) /**< PORT Pin 6 select */ +#define PORT_PIN_7 ((uint32_t)0x00000080) /**< PORT Pin 7 select */ +#define PORT_PIN_8 ((uint32_t)0x00000100) /**< PORT Pin 8 select */ +#define PORT_PIN_9 ((uint32_t)0x00000200) /**< PORT Pin 9 select */ +#define PORT_PIN_10 ((uint32_t)0x00000400) /**< PORT Pin 10 select */ +#define PORT_PIN_11 ((uint32_t)0x00000800) /**< PORT Pin 11 select */ +#define PORT_PIN_12 ((uint32_t)0x00001000) /**< PORT Pin 12 select */ +#define PORT_PIN_13 ((uint32_t)0x00002000) /**< PORT Pin 13 select */ +#define PORT_PIN_14 ((uint32_t)0x00004000) /**< PORT Pin 14 select */ +#define PORT_PIN_15 ((uint32_t)0x00008000) /**< PORT Pin 15 select */ +#define PORT_PIN_16 ((uint32_t)0x00010000) /**< PORT Pin 16 select */ +#define PORT_PIN_17 ((uint32_t)0x00020000) /**< PORT Pin 17 select */ +#define PORT_PIN_18 ((uint32_t)0x00040000) /**< PORT Pin 18 select */ +#define PORT_PIN_19 ((uint32_t)0x00080000) /**< PORT Pin 19 select */ +#define PORT_PIN_20 ((uint32_t)0x00100000) /**< PORT Pin 20 select */ +#define PORT_PIN_21 ((uint32_t)0x00200000) /**< PORT Pin 21 select */ +#define PORT_PIN_22 ((uint32_t)0x00400000) /**< PORT Pin 22 select */ +#define PORT_PIN_23 ((uint32_t)0x00800000) /**< PORT Pin 23 select */ +#define PORT_PIN_24 ((uint32_t)0x01000000) /**< PORT Pin 24 select */ +#define PORT_PIN_25 ((uint32_t)0x02000000) /**< PORT Pin 25 select */ +#define PORT_PIN_26 ((uint32_t)0x04000000) /**< PORT Pin 26 select */ +#define PORT_PIN_27 ((uint32_t)0x08000000) /**< PORT Pin 27 select */ +#define PORT_PIN_28 ((uint32_t)0x10000000) /**< PORT Pin 28 select */ +#define PORT_PIN_29 ((uint32_t)0x20000000) /**< PORT Pin 29 select */ +#define PORT_PIN_30 ((uint32_t)0x40000000) /**< PORT Pin 30 select */ +#define PORT_PIN_31 ((uint32_t)0x80000000) /**< PORT Pin 31 select */ + +#define PORT_DWP_CPU0_ALLOWED ((uint32_t)0x00000001) /**< Only CPU0 is allowed to write PCR and GPIO register corresponding to this pin. */ +#define PORT_DWP_DMA0_ALLOWED ((uint32_t)0x00000008) /**< Only DMA0 is allowed to write PCR and GPIO register corresponding to this pin. */ +#define PORT_DWP_FlexCore_ALLOWED ((uint32_t)0x00000010) /**< Only DMA1 is allowed to write PCR and GPIO register corresponding to this pin. */ + +/** @brief Port Alternate 0 Mode */ +#define PORT_ALT0_FUNC_MODE ((Port_PinModeType)0) +/** @brief Port GPIO Mode */ +#define PORT_GPIO_MODE ((Port_PinModeType)1) +/** @brief Port Alternate 2 Mode */ +#define PORT_ALT2_FUNC_MODE ((Port_PinModeType)2) +/** @brief Port Alternate 3 Mode */ +#define PORT_ALT3_FUNC_MODE ((Port_PinModeType)3) +/** @brief Port Alternate 4 Mode */ +#define PORT_ALT4_FUNC_MODE ((Port_PinModeType)4) +/** @brief Port Alternate 5 Mode */ +#define PORT_ALT5_FUNC_MODE ((Port_PinModeType)5) +/** @brief Port Alternate 6 Mode */ +#define PORT_ALT6_FUNC_MODE ((Port_PinModeType)6) +/** @brief Port Alternate 7 Mode */ +#define PORT_ALT7_FUNC_MODE ((Port_PinModeType)7) + + +/********* global typedef ************/ +/** @brief Port return structure */ +typedef enum +{ + PORT_STATUS_SUCCESS = 0U, + PORT_STATUS_PARAM_INVALID = 1U +} PORT_StatusType; + +/** @brief Port instance number */ +typedef enum +{ + PORT_A = 0U, + PORT_B, + PORT_C, + PORT_D, + PORT_E +} PORT_InstanceType; + +typedef enum +{ + PORT_TRIGGER_DISABLE = 0U, + PORT_TRIGGER_INPUT_CONSISTENT_WITH_PAD = 1U, + PORT_TRIGGER_INPUT_OPPOSITE_WITH_PAD = 2U +} PORT_TriggerInputType; + +/** @brief Port interrupt notification type */ +typedef void (*PORT_PinInterruptCallBackType)(void); + +/** @brief Port initialization structure */ +typedef struct +{ + uint32_t u32PortPins; /**< Port pin, 0~31 bit indicates the pin 0~31 */ + Port_PinMuxType uPortPinMux; /**< Port pin mode */ + PORT_TriggerInputType eTriggrtMode; /**< Port trigger mode */ + bool bPullEn; /**< whether to pull the port pin */ + PORT_PullStatusType ePullSel; /**< pull status, pull up or pull down */ + bool bDrvStrength0En; /**< whether to enable pad drive strength 0 , only hs PAD used */ + bool bDrvStrength1En; /**< whether to enable pad drive strength 1, only uhs PAD used */ + bool u8PassiveFilterEn; /**< whether to use passive filter, please refer to reference manual for details */ +} PORT_InitType; + +/** @brief Port interrupt configuration structure */ +typedef struct +{ + uint32_t u32PortPins; /**< Port pin, 0~31 bit indicates the pin 0~31 */ + PORT_IntConfigType ePortIsrMode; /**< Port interrupt mode */ + PORT_PinInterruptCallBackType pIsrNotify; /**< Port interrupt notification pointer */ +} PORT_InterruptType; + +/** @brief Port digital filter configuration structure */ +typedef struct +{ + uint32_t u32PortPinsEn; /**< Port pin, 0~31 bit indicates the pin 0~31 */ + PORT_DigitalFilterClkSrcType eClkSrc; /**< Port clock source */ + uint8_t u8FilterLength; /**< digital filter length, the range is :0~31 */ +} PORT_DigitalFilterType; + + +/********* global API ************/ +/** + * @brief Initialize port pins + * + * @param ePort Port instance + * @param pInitStruct Initialization structure of port + * @return Port return type. + */ +PORT_StatusType PORT_InitPins(const PORT_InstanceType ePort, const PORT_InitType *const pInitStruct); + +/** + * @brief De-initialize the Port instance + * + * @param ePort Port instance enumeration + * @param u32Pins The bit of u32Pins indicate the Pin number of this Port. + * @return Port return type. + */ +PORT_StatusType PORT_Deinit(const PORT_InstanceType ePort, const uint32_t u32Pins); + +/** + * @brief Enable interrupt function of port + * + * @param ePort Port instance enumeration + * @param pIntStruct Interrupt structure of port. + * @return Port return type. + */ +PORT_StatusType PORT_InitInterrupt(const PORT_InstanceType ePort, const PORT_InterruptType *const pIntStruct); + +/** + * @brief Enable interrupt function of port + * + * @param ePort Port instance enumeration + * @param u32Pins The bit of u32Pins indicate the Pin number of this Port. + * @return Port return type. + */ +PORT_StatusType PORT_EnableInterrupt(const PORT_InstanceType ePort, const uint32_t u32Pins); + +/** + * @brief Disable interrupt function of port + * + * @param ePort Port instance enumeration + * @param u32Pins The bit of u32Pins indicate the Pin number of this Port. + * @return Port return type. + */ +PORT_StatusType PORT_DisableInterrupt(const PORT_InstanceType ePort, const uint32_t u32Pins); + +PORT_StatusType PORT_SetPinsDmaReqMode(const PORT_InstanceType ePort, const uint32_t u32Pins, const PORT_DMAReqType eDMAReqMode); +/** + * @brief Initialize digital filter for Port instance + * + * @param ePort Port instance enumeration + * @param pDFStruct Digital filter initialization structure of port + * @return Port return type. + */ +PORT_StatusType PORT_InitDigitalFilterPort(const PORT_InstanceType ePort, + const PORT_DigitalFilterType *pDFStruct); + +/** + * @brief De-initialize digital filter for Port instance + * + * @param ePort Port instance enumeration + * @return Port return type. + */ +PORT_StatusType PORT_DeinitDigitalFilterPort(const PORT_InstanceType ePort); + +/** + * @brief Enable the digital filter function for the specific pin. + * + * @param ePort Port instance enumeration + * @param u32Pins The bit of u32Pins indicate the Pin number of this Port. + * @return Port return type. + */ +PORT_StatusType PORT_EnableDigitalFilterPin(const PORT_InstanceType ePort, const uint32_t u32Pins); + +/** + * @brief Disable the digital filter function for the specific pin. + * + * @param ePort Port instance enumeration + * @param u32Pins The bit of u32Pins indicate the Pin number of this Port. + * @return Port return type. + */ +PORT_StatusType PORT_DisableDigitalFilterPin(const PORT_InstanceType ePort, const uint32_t u32Pins); + + + +/** @}*/ /* fc7xxx_driver_port */ + +#endif + diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_ptimer.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_ptimer.h new file mode 100644 index 0000000..5196609 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_ptimer.h @@ -0,0 +1,226 @@ +/** + * @file fc7xxx_driver_ptimer.h + * @author Flagchip0126 + * @brief FC7xxx PTIMER driver type definition and API + * @version 0.1.0 + * @date 2024-01-15 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-15 Flagchip0126 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef _DRIVER_FC7XXX_DRIVER_PTIMER_H_ +#define _DRIVER_FC7XXX_DRIVER_PTIMER_H_ +#include "device_header.h" +#include "HwA_ptimer.h" +#include "HwA_scm.h" + +#if defined(__cplusplus) +extern "C" { +#endif +/** + * @addtogroup fc7xxx_driver_ptimer + * @{ + */ + +/** + * @brief PTIMER interrupt callback function prototype + * + */ +typedef void (*PTIMER_InterruptCallbackType)(void); + +/** + * @brief PTIMER sequence error callback function prototype + * + */ +typedef void (*PTIMER_SeqErrorCallbackType)(uint8_t u8Channel); + +/** + * @brief The instance index of the PTIMER peripheral + * + */ +typedef enum +{ + PTIMER_INSTANCE_0 = 0U, + PTIMER_INSTANCE_1 = 1U +} PTIMER_InstanceType; + +/** + * @brief Ptimer instance initialization parameters + * + */ +typedef struct +{ + PTIMER_LoadValueModeType eLoadValueMode; /*!< Select the load mode */ + PTIMER_ClockPreDividerType eClkPreDiv; /*!< Select the prescaler divider */ + PTIMER_ClockPreDivMultiplyFactorType eClkPreMultFactor; /*!< Select multiplication factor for prescaler */ + PTIMER_TrgSrcType eTriggerInput; /*!< Select the trigger input source */ + bool bContinuousModeEnable; /*!< Enable the continuous mode */ + bool bDmaEnable; /*!< Enable the dma for timer */ +} PTIMER_InitType; + +/** + * @brief Ptimer interrupt configuration parameters + * + */ +typedef struct +{ + bool bDelayIntEnable; /*!< Enable the interrupt for timer */ + uint32_t u32IntDelayPeriodUs; /*!< The period in micro second */ + PTIMER_InterruptCallbackType pIntNotify; /*!< Ptimer interrupt callback function pointer */ + bool bSeqErrIntEnable; /*!< Enable PTIMER Sequence Error Interrupt */ + PTIMER_SeqErrorCallbackType pSeqErrorNotify; /*!< Ptimer sequence error callback function pointer */ +} PTIMER_InterruptType; + +/** + * @brief Ptimer channel configuration parameters + * + */ +typedef struct +{ + uint32_t u32DelayUs; /*!< Setting pre_trigger's delay in microsecond. */ + bool bPreTriggerEnable; /*!< Enable the pre_trigger. */ + bool bPreTriggerOutputEnable; /*!< Enable the pre_trigger output. */ + bool bPreTriggerBackToBackEnable; /*!< Enable the back to back mode for ADC pre_trigger. */ +} PTIMER_ChannelCfgType; + +/** + * @brief Ptimer pulse out configgurations + * + * When the Ptimer counter time reaches u32PulseOutDlyHighUs, the pulse-out goes high; + * When the Ptimer counter time reaches u32PulseOutDlyLowUs, the pulse-out goes low. + * + */ +typedef struct +{ + uint32_t u32PulseOutDlyHighUs; /*!< Microsecond delay for pulse out to output high */ + uint32_t u32PulseOutDlyLowUs; /*!< Microsecond delay for pulse out to output low */ +} PTIMER_PulseOutType; + +/** + * @brief Initialize the Ptimer instance + * + * @param eInstance the Ptimer instance to use + * @param pInitCfg the Ptimer initialization parameters + */ +void PTIMER_Init(const PTIMER_InstanceType eInstance, const PTIMER_InitType *const pInitCfg); + +/** + * @brief De-initialize the Ptimer instance + * Disable the Ptimer instance and reset the configurations to its reset values + * + * @param eInstance the Ptimer instance to use + */ +void PTIMER_DeInit(const PTIMER_InstanceType eInstance); + +/** + * @brief Initialize the Ptimer interrupt + * + * @note the interrupt delay value is buffered and will take effect only after called PTIMER_LoadValue() + * function. + * + * @param eInstance the Ptimer instance to configure + * @param pInterruptCfg the Ptimer initialization parameters + */ +void PTIMER_InitInterrupt(const PTIMER_InstanceType eInstance, + const PTIMER_InterruptType *const pInterruptCfg); + +/** + * @brief Initialize the Ptimer channels + * + * @note the channel delay value is buffered and will take effect only after called PTIMER_LoadValue() + * function. + * + * @param eInstance the Ptimer instance to use + * @param aChannelCfg the array of channels to config + * @param u8ChnNum the channel numbers in the channel array + */ +void PTIMER_InitChannel(const PTIMER_InstanceType eInstance, + const PTIMER_ChannelCfgType aChannelCfg[], const uint8_t u8ChnNum); + +/** + * @brief Set the Ptimer max counter period in microsecond + * When the Ptimer counter reaches the period, it will return to zero + * + * @note the period parameter is buffered and will take effect only after called PTIMER_LoadValue() + * function. + * + * @param eInstance the Ptimer instance to use + * @param u32PeriodUs the max counter period in microsecond + */ +void PTIMER_SetPeriod(const PTIMER_InstanceType eInstance, uint32_t u32PeriodUs); + +/** + * @brief Set the Ptimer pulse-out function + * + * @note the pulse-out delay values are buffered and will take effect only after called PTIMER_LoadValue() + * function. + * + * @param eInstance the Ptimer instance to use + * @param pPulseOutCfg the pulse-out configuration + */ +void PTIMER_SetPulseOut(const PTIMER_InstanceType eInstance, const PTIMER_PulseOutType *pPulseOutCfg); + +/** + * @brief Load the buffered values into register + * + * Some Ptimer registers are buffered and will only take effect after called + * this function + * + * @param eInstance the Ptimer instance to use + */ +void PTIMER_LoadValue(const PTIMER_InstanceType eInstance); + +/** + * @brief Enable the Ptimer instance + * + * @param eInstance the Ptimer instance to use + */ +void PTIMER_Enable(const PTIMER_InstanceType eInstance); + +/** + * @brief Disable the Ptimer instance + * + * @param eInstance the Ptimer instance to use + */ +void PTIMER_Disable(const PTIMER_InstanceType eInstance); + +/** + * @brief Enable the Ptimer pulse-out function + * + * @param eInstance the Ptimer instance to use + */ +void PTIMER_EnablePulseOut(const PTIMER_InstanceType eInstance); + +/** + * @brief Disable the Ptimer pulse-out function + * + * @param eInstance the Ptimer instance to use + */ +void PTIMER_DisablePulseOut(const PTIMER_InstanceType eInstance); + +void PTIMER_SelectInstance01BackToBackMode(SCM_PTimerLMSelType ePTimerLoopMode); + +/** + * @brief Generate the software trigger signal for the Ptimer instance + * + * If the Ptimer trigger source is selected as PTIMER_TRGSRC_SW, call this function + * will make the Ptimer instance to start. + * + * @param eInstance the Ptimer instance to use + */ +void PTIMER_GenerateSWTrigger(const PTIMER_InstanceType eInstance); + +/** @}*/ /* fc7xxx_driver_ptimer */ + +#if defined(__cplusplus) +} +#endif +#endif diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_rgm.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_rgm.h new file mode 100644 index 0000000..166438b --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_rgm.h @@ -0,0 +1,182 @@ +/** + * @file fc7xxx_driver_rgm.h + * @author Flagchip + * @brief FC7xxx RGM driver type definition and API + * @version 0.1.0 + * @date 2024-01-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/******************************************************************************** +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2024-01-12 Flagchip119 N/A First version for FC7240 +********************************************************************************/ +#ifndef _DRIVER_FC7XXX_DRIVER_RCM_H_ +#define _DRIVER_FC7XXX_DRIVER_RCM_H_ + +#include "HwA_rgm.h" + +/** + * @addtogroup fc7xxx_driver_rcgm + * @{ + */ + +/** @brief Get which core currently belongs to. */ +#define GET_CORE_NUM (*(uint32_t *)0xE0080004) + +/** @brief Rgm return type. */ +typedef enum +{ + RGM_STATUS_SUCCESS = 0U, + RGM_STATUS_PARAM_INVALID = 1U, + RGM_STATUS_COREID_INVALID = 2U +} RGM_StatusType; + +/** @brief Rgm reset pin filter clock type. */ +typedef enum +{ + RGM_RESET_FILTER_BUS_CLOCK = 0U, + RGM_RESET_FILTER_AON32K_CLOCK = 1U +} RGM_FilterClkSrc; + +/** @brief Rgm interrupt notification type */ +typedef void (*RGM_InterruptCallBackType)(uint32_t u32SRS); + +/** + * @brief This api can get RGM_SRS register that indicate the source of the most recent reset. + * + * @return RGM->RGM_SRS register, bit 0-15,29-31 corresponding to RGM_ResetEventType, refer to reference manual for details. + * @note Multiple flags can be set if multiple reset events occur at the same time + */ +uint32_t RGM_GetLastResetFLag(void); + +/** + * @brief This api can get RGM_SSRS register that indicate all reset sources since the last POR or LVD that have not been cleared by software. + * + * @returnRGM->RGM_SSRS register, bit 0-15,29-31 corresponding to RGM_ResetEventType, refer to reference manual for details. + */ +uint32_t RGM_GetAllResetFlag(void); + +/** + * @brief This api can clear reset flag of RGM_SSRS register which indicate all reset sources since the last POR or LVD that have not been cleared by software. + * + * @param eReset Enumeration of reset event flag + */ +void RGM_ClearResetFlagAfterPOR(const RGM_ResetEventType eReset); + +/** + * @brief This api can clear all reset flag of RGM_SSRS register which indicate all reset sources since the last POR or LVD that have not been cleared by software. + * + */ +void RGM_ClearAllResetFlagAfterPOR(void); + +/** + * @brief Enable reset pin filter + * + * @param eClk Reset pin filter clock source + * @param u8BusClockFilterWidth Bus clock filter width + * @param bLpClkEn select whether enable reset pin filter using AON32clock in low power mode + * @return RGM return type + * @note If use AON32K clock, A reset signal whose length is less than 2 AON32K clock periods will be filtered + */ +RGM_StatusType RGM_EnableResetFilter(RGM_FilterClkSrc eClk, uint8_t u8BusClockFilterWidth, bool bLpClkEn); + +/** + * @brief Disable reset pin filter + * + * @param eClk Reset pin filter clock source + * @param bLpClkEn select whether disable reset pin filter using AON32clock in low power mode + * @return RGM return type + */ +RGM_StatusType RGM_DisableResetFilter(RGM_FilterClkSrc eClk, bool bLpClkEn); + +/** + * @brief This api can enable interrupt before an system reset appear. + * + * @param eDelay Enumeration of delay cycles + * @param eResetInterrupt Reset event flag, like: RGM_INT_CLKERR0 | RGM_INT_FCSMU + * @return RGM return type + */ +RGM_StatusType RGM_EnableSystemResetInt(RGM_ResetDelayType eDelay, RGM_ResetIntMangerType eResetInterrupt); + +/** + * @brief This api can disable interrupt before an system reset appear. + * + * @param eResetInterrupt Reset event flag, like: RGM_INT_CLKERR0 | RGM_INT_FCSMU + * @param bClearDelay Whether to clear delay configuration + * @return RGM return type + */ +RGM_StatusType RGM_DisableSystemResetInt(RGM_ResetIntMangerType eResetInterrupt, bool bClearDelay); + +/** + * @brief Generate software reset through cotex-m register + * + */ +void RGM_GenerateSwReset(void); + +/** + * @brief This api can enable interrupt before an CPU0 core related reset appear. + * + * @param eCPU0Interrupt Reset event flag, like: RGM_CPU_INT_SWRST | RGM_CPU_INT_SYSRST + * @param pIsrNotify Interrupt function + * @return RGM return type + */ +RGM_StatusType RGM_EnableCPU0CoreResetInt(RGM_CPUIntMangerType eCPU0Interrupt,RGM_InterruptCallBackType pIsrNotify); + +/** + * @brief This api can disable interrupt before an CPU0 core related reset appear. + * + * @param eCPU0Interrupt Reset event flag, like: RGM_CPU_INT_SWRST | RGM_CPU_INT_SYSRST + * @return RGM return type + */ +RGM_StatusType RGM_DisableCPU0CoreResetInt(RGM_CPUIntMangerType eCPU0Interrupt); + +/** + * @brief Get the CPU0 exit reset flag + * + * @return RGM_CPU_OUT_RST_UNDER CPU0 is under reset + * @return RGM_CPU_OUT_RST_OUT CPU0 is out of reset + */ +RGM_CPUOutResetType RGM_GetCPU0OutResetFlag(void); + +/** + * @brief Generate a CPU0 software reset. + * + */ +void RGM_GenerateCPU0SwReset(void); + +/** + * @brief This api can get RGM_C0_SRS register that indicate the source of the most recent CPU0 reset. + * + * @return RGM->RGM_C0_SRS register, bit 0-20 corresponding to RGM_ResetEventType, refer to reference manual for details. + * @note Multiple flags can be set if multiple reset events occur at the same time + */ +uint32_t RGM_GetCPU0LastResetFLag(void); + +/** + * @brief This api can get RGM_C0_SSRS register that indicate all CPU0 reset sources since the last POR or LVD that have not been cleared by software. + * + * @returnRGM->RGM_C0_SSRS register, bit 0-20,29-31 corresponding to RGM_CPUResetEventType, refer to reference manual for details. + */ +uint32_t RGM_GetCPU0AllResetFlag(void); + +/** + * @brief This api can clear reset flag of RGM_C0_SSRS register which indicate CPU0 all reset sources since the last POR or LVD that have not been cleared by software. + * + * @param eReset Enumeration of reset event flag + */ +void RGM_ClearCPU0ResetFlagAfterPOR(const RGM_CPUResetEventType eReset); + +/** + * @brief This api can clear all reset flag of RGM_C0_SSRS register which indicate CPU0 all reset sources since the last POR or LVD that have not been cleared by software. + * + */ +void RGM_ClearCPU0AllResetFlagAfterPOR(void); + +/** @}*/ /* fc7xxx_driver_rgm */ +#endif /* end of _DRIVER_FC7XXX_DRIVER_RGM_H_ */ diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_rtc.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_rtc.h new file mode 100644 index 0000000..599a6f8 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_rtc.h @@ -0,0 +1,152 @@ +/** + * @file fc7xxx_driver_rtc.h + * @author Flagchip + * @brief FC7xxx rtc driver type definition and API + * @version 0.1.0 + * @date 2024-01-10 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/******************************************************************************** +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2024-01-10 Flagchip0076 N/A First version for FC7240 +********************************************************************************/ + + +#ifndef DRIVER_INCLUDE_FC7XXX_DRIVER_RTC_H_ +#define DRIVER_INCLUDE_FC7XXX_DRIVER_RTC_H_ + +#include"HwA_rtc.h" + + +/** + * @addtogroup fc7xxx_driver_rtc + * @{ + */ + +/** @brief Rtc return type. */ +typedef enum +{ + RTC_STATUS_SUCCESS = 0U, /**< rtc status is success */ + RTC_STATUS_PARAM_INVALID = 1U, /**< rtc status is failed because the param is invalid */ + RTC_STATUS_FUNCTION_ERROR = 2U, /**< rtc status is failed because the function is error */ + RTC_STATUS_CLOCK_INVALID = 3U /**< rtc status is failed because the clock is invalid */ +} RTC_StatusType; + +/** @brief Rtc mode */ +typedef enum +{ + RTC_ALARM_INT = 0U, /**< rtc interrupt mode is alarm */ + RTC_SECOND_INT = 1U, /**< rtc interrupt mode is second */ + RTC_OVERFLOW_INT = 2U /**< rtc interrupt mode is overflow */ +} RTC_IntEventType; + +/** @brief Rtc interrupt notification type */ +typedef void (*RTC_InterruptCallBackType)(void); + +/** @brief Rtc interrupt configuration type */ +typedef struct +{ + bool bAlarmIntEn; /**< whether enable rtc alarm interrupt */ + RTC_InterruptCallBackType pIsrAlarmNotify; /**< rtc alarm notification function pointer */ + bool bSecondIntEn; /**< whether to use the second interrupt */ + RTC_InterruptCallBackType pIsrSecondNotify; /**< second interrupt notification function pointer */ + bool bOverflowIntEn ; /**< overflow interrupt notification function pointer */ + RTC_InterruptCallBackType pIsrOverflowNotify; /**< overflow interrupt notification function pointer */ +} RTC_InterruptType; + +/** @brief Rtc initialization type */ +typedef struct +{ + uint32_t u32AlarmValue; /**< rtc alarm value */ + RTC_ClkoutSecIntFreqType eSecIntAndClkoutFreq; /**< Select the RTC Seconds interrupt and the RTC_CLKOUT prescaler output frequency */ + bool bStableClkoutFreq; /**< Select the RTC Seconds interrupt and the RTC_CLKOUT prescaler output frequency or RTC_CLKOUT is from the 32.768 kHz clock. */ +} RTC_InitType; + +/* global functions */ +/** + * @brief Initialize Rtc instance + * @param pInitStruct Rtc initialization structure + */ +void RTC_Init(const RTC_InitType *const pInitStruct); + +/** + * @brief Rtc set interrupt + * + * @param pIntStruct interrupt structure pointer + * @return Rtc return type + * @note this function will stop Rtc timer + */ +RTC_StatusType RTC_InitInterrupt(const RTC_InterruptType *const pIntStruct); + +/** + * @brief De-initialize Rtc instance + * + */ +void RTC_Deinit(void); + +/** + * @brief Rtc enable interrupt + * + * @param bAlarmIntEn whether enable alarm interrupt + * @param bSecondIntEn whether enable second interrupt + */ +void RTC_EnableInterrupt(const bool bAlarmIntEn, const bool bSecondIntEn, const bool bOverflowIntEn); + +/** + * @brief Rtc disable interrupt + * + * @param bAlarmIntEn whether disable alarm interrupt + * @param bSecondIntEn whether disable second interrupt + */ +void RTC_DisableInterrupt(const bool bAlarmIntEn, const bool bSecondIntEn, const bool boverflowIntEn); + +/** + * @brief Rtc start + * + */ +void RTC_Start(void); + +/** + * @brief Rtc stop + * + */ +void RTC_Stop(void); + +/** + * @brief Rtc alarm value + * + * @param u32AlarmValue Input value + */ +void RTC_UpdateAlarmValue(const uint32_t u32AlarmValue); + +/** + * @brief Get Rtc counter value + * + * @return Rtc counter value + */ +uint32_t RTC_GetTime(void); + +/** + * @brief Check RTC overflow flag + * + * @return Overflow flag + */ +bool RTC_CheckOverflowFlag(void); + + +/** + * @brief Set second counter value + * @param u32Value the second value. + * */ + +void RTC_SetSecondCounterValue(uint32_t u32Value); + + +/** @}*/ /* fc7xxx_driver_rtc */ +#endif /* DRIVER_INCLUDE_FC7XXX_DRIVER_RTC_H_ */ diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_scg.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_scg.h new file mode 100644 index 0000000..64bd5a1 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_scg.h @@ -0,0 +1,459 @@ +/** + * @file fc7xxx_driver_scg.h + * @author Flagchip085 + * @brief FC7xxx SCG driver type definition and API + * @version 0.1.0 + * @date 2024-01-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240 + ******************************************************************************** */ +#ifndef _DRIVER_FC7XXX_DRIVER_SCG_H_ +#define _DRIVER_FC7XXX_DRIVER_SCG_H_ +#include "HwA_scg.h" +#include "HwA_csc.h" +/** + * @addtogroup fc7xxx_driver_scg + * @{ + */ + +/** @brief clock list for internal clock tree */ +typedef enum +{ + /* Main clocks */ + SCG_CORE_CLK = 0U, /*!< Core clock */ + SCG_BUS_CLK = 1U, /*!< Bus clock */ + SCG_SLOW_CLK = 2U, /*!< Slow clock */ + + /* Other internal clocks used by peripherals. */ + SCG_FOSC_CLK = 3U, /*!< FOSC clock */ + SCG_FIRC_CLK = 4U, /*!< FIRC clock */ + SCG_PLL0_CLK = 5U, /*!< PLL0 clock */ + SCG_PLL1_CLK = 6U, /*!< PLL1 clock */ + SCG_SIRC_CLK = 7U, /*!< SIRC clock */ + SCG_SIRC32K_CLK = 8U, /*!< SIRC32K clock */ + SCG_SOSC_CLK = 9U, /*!< SOSC clock */ + SCG_SCG_CLKOUT_CLK = 10U, /*!< SCG CLK_OUT clock */ + SCG_SIRCDIVH_CLK = 11U, /*!< SIRCDIVH functional clock */ + SCG_SIRCDIVM_CLK = 12U, /*!< SIRCDIVM functional clock */ + SCG_SIRCDIVL_CLK = 13U, /*!< SIRCDIVL functional clock */ + SCG_FIRCDIVH_CLK = 14U, /*!< FIRCDIVH functional clock */ + SCG_FIRCDIVM_CLK = 15U, /*!< FIRCDIVM functional clock */ + SCG_FIRCDIVL_CLK = 16U, /*!< FIRCDIVL functional clock */ + SCG_FOSCDIVH_CLK = 17U, /*!< FOSCDIVH functional clock */ + SCG_FOSCDIVM_CLK = 18U, /*!< FOSCDIVM functional clock */ + SCG_FOSCDIVL_CLK = 19U, /*!< FOSCDIVL functional clock */ + SCG_PLL0DIVH_CLK = 20U, /*!< PLL0DIVH functional clock */ + SCG_PLL0DIVM_CLK = 21U, /*!< PLL0DIVM functional clock */ + SCG_PLL0DIVL_CLK = 22U, /*!< PLL0DIVL functional clock */ + SCG_PLL1DIVH_CLK = 23U, /*!< PLL1DIVH functional clock */ + SCG_PLL1DIVM_CLK = 24U, /*!< PLL1DIVM functional clock */ + SCG_PLL1DIVL_CLK = 25U, /*!< PLL1DIVL functional clock */ + SCG_NVMINIT_CLK = 26U, /*!< NVM initial clock source */ + SCG_CMU4REF_CLK = 27U, /*!< CMU4 reference clock */ + SCG_END_OF_CLOCKS = 28U /*!< End of SCG clocks */ +} SCG_ClkSrcType; + +/** + * @brief PLL clock type + */ +typedef enum +{ + SCG_PLL0 = 0U, /*!< PLL0 clock */ + SCG_PLL1 = 1U /*!< PLL1 clock */ +} SCG_PllClkType; + +/** + * @brief indicate the clock function status + * + */ +typedef enum +{ + SCG_STATUS_SUCCESS = 0U, /*!< function called success */ + SCG_STATUS_SEQUENCE_ERROR = 1U, /*!< function called report sequence error */ + SCG_STATUS_TIMEOUT = 2U, /*!< function called report timeout error */ + SCG_STATUS_IRC_ERROR = 3U, /*!< function called report internal clock error */ + SCG_STATUS_PARAM_ERROR = 4U /*!< function called report internal clock error */ +} SCG_StatusType; + +/** + * @brief indicate the CRC check result + * + */ +typedef enum +{ + SCG_CRC_CHECK_SUCCESS = 0U, /*!< CRC check success *//**< SCG_CRC_CHECK_SUCCESS */ + SCG_CRC_GEN_TIMEOUT = 1U, /*!< CRC Generate Timeout *//**< SCG_CRC_GEN_TIMEOUT */ + SCG_CRC_CHECK_FAILED = 2U /*!< CRC check failed */ /**< SCG_CRC_CHECK_FAILED */ +} SCG_CrcCheckResType; + +/** + * @brief SCG xxxIRC TRIMSRC type. +*/ +typedef enum +{ + SCG_IRC_TRIMSRC_RESERVE0 = 0U, /*!< Clock Trim source reserve0 */ + SCG_IRC_TRIMSRC_RESERVE1 = 1U, /*!< Clock Trim source reserve1 */ + SCG_IRC_TRIMSRC_FOSC = 2U, /*!< Clock Trim source FOSC */ + SCG_IRC_TRIMSRC_SOSC = 3U, /*!< Clock Trim source SOSC */ +} SCG_IrcTrimSrcType; + +/** + * @brief SCG_CCR [SCS] to Select system clock source + * + */ +typedef enum +{ + SCG_CLOCK_SRC_FOSC = 1U, /*!< System OSC. */ + SCG_CLOCK_SRC_SIRC = 2U, /*!< Slow IRC 12MHz. */ + SCG_CLOCK_SRC_FIRC = 3U, /*!< Fast IRC. */ + SCG_CLOCK_SRC_PLL0 = 6U, /*!< System PLL. */ + SCG_CLOCK_SRC_NONE = 255U /*!< MAX value. */ +} SCG_ClockSrcType; + +/** + * @brief SCG_CCR [DIVCORE ]/ SCG_CCR [DIVBUS ]/ SCG_CCR [DIVSLOW ] to Select system clock source. + * + */ +typedef enum +{ + SCG_CLOCK_DIV_BY1 = 0U, /*!< Divided by 1. */ + SCG_CLOCK_DIV_BY2 = 1U, /*!< Divided by 2. */ + SCG_CLOCK_DIV_BY3 = 2U, /*!< Divided by 3. */ + SCG_CLOCK_DIV_BY4 = 3U /*!< Divided by 4. */ +} SCG_ClockDivType; + +/** + * @brief SCG_ CLKOUTCFG [CLKOUTSEL] to Select system clock source. + */ +typedef enum +{ + SCG_CLOCKOUT_SRC_OFF = 0U, /*!< SCG OFF. */ + SCG_CLOCKOUT_SRC_FOSC = 1U, /*!< Fast OSC. */ + SCG_CLOCKOUT_SRC_SIRC = 2U, /*!< Slow IRC. */ + SCG_CLOCKOUT_SRC_FIRC = 3U, /*!< Fast IRC. */ + SCG_CLOCKOUT_SRC_SOSC = 4U, /*!< Slow OSC. */ + SCG_CLOCKOUT_SRC_PLL1 = 5U, /*!< System PLL1. */ + SCG_CLOCKOUT_SRC_PLL0 = 6U, /*!< System PLL0. */ + SCG_CLOCKOUT_SRC_SIRC32K = 7U, /*!< SIRC32K_CLK.*/ +} SCG_ClockoutSrcType; + +/** + * @brief NVM clock source enumeration + */ +typedef enum +{ + SCG_NVMCLK_SRC_SIRC = 30u, /*!< NVM source choose SIRC. */ + SCG_NVMCLK_SRC_FIRC = 31u /*!< NVM source choose FIRC. */ +} SCG_NvmClkSrcType; + +/** + * @brief CMU4 clock source enumeration + */ +typedef enum +{ + SCG_CMU4CLK_SRC_SIRC = 28u, /*!< NVM source choose SIRC. */ + SCG_CMU4CLK_SRC_FOSC = 29u /*!< NVM source choose FORC. */ +} SCG_Cmu4ClkSrcType; + +/** + * @brief SCG registers CRC trigger mode + */ +typedef enum +{ + SCG_CRC_SW_MODE = 0U, /*!< SCG registers CRC software mode. */ + SCG_CRC_TRIGGER_MODE = 1U /*!< SCG registers CRC trigger mode. */ +} SCG_CrcModeType; + +/** @brief [DIVL]/[DIVM]/[DIVH] bit field definition for SCG_SIRC/ SCG_FIRC/ SCG_FOSC/ SCG_PLL0 registers */ +typedef enum +{ + SCG_ASYNC_CLOCK_DISABLE = 0U, /*!< Clock output is disabled. */ + SCG_ASYNCCLOCKDIV_BY1 = 1U, /*!< Divided by 1. */ + SCG_ASYNCCLOCKDIV_BY2 = 2U, /*!< Divided by 2. */ + SCG_ASYNCCLOCKDIV_BY4 = 3U, /*!< Divided by 4. */ + SCG_ASYNCCLOCKDIV_BY8 = 4U, /*!< Divided by 8. */ + SCG_ASYNCCLOCKDIV_BY16 = 5U, /*!< Divided by 16. */ + SCG_ASYNCCLOCKDIV_BY32 = 6U, /*!< Divided by 32. */ + SCG_ASYNCCLOCKDIV_BY64 = 7U /*!< Divided by 64. */ +} SCG_AsyncClockDivType; + +/** @brief SCG_ PLLCFG[PREDIV] for PLL clock calculation. The pre-div value range is 0 ~ 31 */ +typedef uint8_t SCG_PllPredivType; + +/** @brief SCG_ PLLCFG[PSTDIV] for PLL clock calculation */ +typedef enum +{ + SCG_PLLPSTDIV_BY2 = 1U, + SCG_PLLPSTDIV_BY4 = 2U, + SCG_PLLPSTDIV_BY8 = 3U +} SCG_PllPstdivType; + +/** @brief SCG_ PLLCFG[SOURCE] to Select PLL clock source */ +typedef enum +{ + SCG_PLLSOURCE_FOSC = 0U, + SCG_PLLSOURCE_FIRC = 1U +} SCG_PllSourceType; + +/** @brief SCG_ PLLCFG [MULT] for PLL clock calculation. The mult value range is 96 ~ 512 */ +typedef uint16_t SCG_PllMultiplyType; + +/** @brief FOSC initial definition, include register SCG_FOSCCSR/SCG_FOSCDIV/SCG_FOSCCFG. */ +typedef struct +{ + bool bLock; /*!< SCG_FOSCCSR[LK] bit, Write to set the register can be written or not */ + bool bCm; /*!< SCG_FOSCCSR[CM] bit, Clock Monitor is enable */ + bool bCmre; /*!< SCG_FOSCCSR[CMRE] bit, Clock Monitor Reset Enable + 0 Generates interrupt, 1 Generates rese */ + bool bSten; /*!< SCG_FOSCCSR[STEN] bit, Clock Stop in Stop modes */ + bool bBypass; /*!< SCG_FOSCCFG[BYPASS] bit, Configures FOSC for bypassing the internal oscillator.*/ + SCG_AsyncClockDivType eDivH; /*!< SCG_FOSCDIV[DIVH] bit field definition, 0 means disable. */ + SCG_AsyncClockDivType eDivM; /*!< SCG_FOSCDIV[DIVM] bit field definition, 0 means disable. */ + SCG_AsyncClockDivType eDivL; /*!< SCG_FOSCDIV[DIVL] bit field definition, 0 means disable. */ +} SCG_FoscType; + +/** @brief SIRC initial definition, include register SCG_ SIRCCSR/ SCG_ SIRCDIV/ SCG_ SIRCTCCFG. */ +typedef struct +{ + bool bLock; /*!< SCG_SIRCCSR[LK] bit, Write to set the register can be written or not */ + bool bCm; /*!< SCG_SIRCCSR[CM] bit, SIRC Clock Monitor Enable */ + bool bTrEn; /*!< SCG_SIRCCSR[TREN] bit, IRC software trim enable (auto trim) */ + bool bLpen; /*!< SCG_SIRCCSR[LPEN] bit, Clock Stop Enable */ + bool bSten; /*!< SCG_SIRCCSR[STEN] bit, Clock Standby Enable */ + SCG_AsyncClockDivType eDivH; /*!< SCG_SIRCDIV[DIVH] bit field definition.*/ + SCG_AsyncClockDivType eDivM; /*!< SCG_SIRCDIV[DIVM] bit field definition.*/ + SCG_AsyncClockDivType eDivL; /*!< SCG_SIRCDIV[DIVL] bit field definition.*/ + uint8_t u8TrimSrc; /*!< SCG_SIRCTCFG[TRIMSRC] IRC clock auto trim reference clock source select.*/ +} SCG_SircType; + +typedef struct +{ + bool bLock; /*!< SIRC32KCSR[LK] bit, Write to set the register can be written or not */ +} SCG_Sirc32kType; + +/** @brief FIRC initial definition, include register SCG_ FIRCCSR/ SCG_ FIRCDIV/ SCG_ FIRCFG. */ +typedef struct +{ + bool bLock; /*!< SCG_FIRCCSR[LK] bit, Write to set the register can be written or not */ + bool bCm; /*!< SCG_FIRCCSR[CM] bit, FIRC Clock Monitor Enable */ + bool bTrEn; /*!< SCG_FIRCCSR[TREN] bit, IRC software trim enable (auto trim) */ + bool bSten; /*!< SCG_FIRCCSR[STEN] bit, Clock Standby Enable */ + SCG_AsyncClockDivType eDivH; /*!< SCG_FIRCDIV[DIVH] bit field definition.*/ + SCG_AsyncClockDivType eDivM; /*!< SCG_FIRCDIV[DIVM] bit field definition.*/ + SCG_AsyncClockDivType eDivL; /*!< SCG_FIRCDIV[DIVL] bit field definition.*/ + uint8_t u8TrimSrc; /*!< SCG_FIRCTCFG[TRIMSRC] IRC clock auto trim reference clock source select.*/ +} SCG_FircType; + +/** @brief SOSC definition, include register SCG_SOSCCFG. */ +typedef struct +{ + bool bLock; /*!< SCG_SOSCCSR[LK] bit, Write to set the register can be written or not.*/ + bool bBypass; /*!< SCG_SOSCCSR[BYPASS] bit, Configures SOSC for bypassing the internal oscillator.*/ + bool bCm; /*!< SCG_SOSCCSR[CM] bit,Clock Monitor enable.*/ + bool bCmre; /*!< SCG_SOSCCSR[CMRE] bit, 1:Clock Monitor Reset, 0: interrupt*/ +} SCG_SoscType; + +/** @brief PLL definition, include register SCG_PLLCSR/ SCG_PLLDIV/SCG_PLL0CFG. */ +typedef struct +{ + bool bLock; /*!< SCG_PLLCSR[LK] bit, Write to set the register can be written or not.*/ + bool bCm; /*!< SCG_PLLCSR[CM] bit,Clock Monitor enable.*/ + bool bCmre; /*!< SCG_PLLCSR[CMRE] bit, 1:Clock Monitor Reset, 0: interrupt*/ + bool bSten; /*!< SCG_PLLCSR[STEN] bit, Clock Standby Enable */ + SCG_AsyncClockDivType eDivH; /*!< SCG_PLLDIV[DIVH] bit field definition.*/ + SCG_AsyncClockDivType eDivM; /*!< SCG_PLLDIV[DIVM] bit field definition.*/ + SCG_AsyncClockDivType eDivL; /*!< SCG_PLLDIV[DIVL] bit field definition.*/ + SCG_PllPredivType u8Prediv; /*!< SCG_PLLCFG[PREDIV] bit field definition, the range is 0~31. [Pre-divider = u8Prediv + 1] */ + SCG_PllPstdivType ePstDiv; /*!< SCG_PLLCFG[PSTDIV] bit field definition. [Post Divider = (ePstDiv == 0 ? 2 : 2^ePstDiv)] */ + SCG_PllMultiplyType u16Mult; /*!< SCG_PLLCFG[MULT] bit field definition, this value need to be greater than 95. + [Multiplier = u16Mult + 1] */ + SCG_PllSourceType eSrc; /*!< SCG_PLLCFG[SOURCE] bit field definition.*/ +} SCG_PllType; + +/** @brief Current system clock definition, include register SCG_CCR. */ +typedef struct +{ + bool bSysClkMonitor; /*!< SCG_CCR[SYSCLK_CME], System Clock monitor bit.*/ + SCG_ClockSrcType eSrc; /*!< SCG_CCR[SCS], System Clock Source.*/ + SCG_ClockDivType eDivSlow; /*!< SCG_CCR[DIVSLOW], Slow Clock Divide Ratio.*/ + SCG_ClockDivType eDivBus; /*!< SCG_CCR[DIVBUS], Bus Clock Divide Ratio.*/ + SCG_ClockDivType eDivCore; /*!< SCG_CCR[DIVCORE], Core Clock Divide Ratio.*/ +} SCG_ClockCtrlType; + +/** + * @brief Enable SOSC + * + * @param pSoscConfig SOSC configuration + * @return SCG_StatusType Function status + */ +SCG_StatusType SCG_EnableSOSC(const SCG_SoscType *const pSoscConfig); + +/** + * @brief Disable SOSC + * + * @return SCG_StatusType Funtion status + */ +SCG_StatusType SCG_DisableSOSC(void); + +/** + * @brief Enable FOSC clock with input configuration + * + * @param pFoscConfig FOSC configuration + * @return SCG_StatusType function status + */ +SCG_StatusType SCG_EnableFOSC(const SCG_FoscType *const pFoscConfig); + +/** + * @brief Disable FOSC + * + * @return SCG_StatusType function status + */ +SCG_StatusType SCG_DisableFOSC(void); + +/** + * @brief Set SIRC configuration and configure SIRC DIV + * + * @param pSircConfig SIRC configuation + * @return SCG_StatusType function status + */ +SCG_StatusType SCG_SetSIRC(const SCG_SircType *const pSircConfig); + +/** + * @brief Disable SIRC DIV and clear DIV configuration + * + * @return SCG_StatusType function status + */ +SCG_StatusType SCG_ClearSIRC(void); + +/** + * @brief Enable SIRC32K + * + * @param pSirc32kConfig SIRC32K configuration + * @return SCG_StatusType function status + */ +SCG_StatusType SCG_EnableSIRC32K(const SCG_Sirc32kType *const pSirc32kConfig); + +/** + * @brief Disable SIRC32K + * + * @return SCG_StatusType function status + */ +SCG_StatusType SCG_DisableSIRC32K(void); + +/** + * @brief Enable FIRC + * + * @param pFircConfig FIRC configuration + * @return SCG_StatusType function status + */ +SCG_StatusType SCG_EnableFIRC(const SCG_FircType *const pFircConfig); + +/** + * @brief Disable FIRC + * + * @return SCG_StatusType function status + */ +SCG_StatusType SCG_DisableFIRC(void); + +/** + * @brief Enable PLL + * + * @param ePll PLL instance + * @param pPllConfig PLL configuration + * @return SCG_StatusType function status + */ +SCG_StatusType SCG_EnablePLL(const SCG_PllClkType ePll, const SCG_PllType *const pPllConfig); + +/** + * @brief Disable PLL + * + * @param ePll PLL instance + * @return SCG_StatusType function status + */ +SCG_StatusType SCG_DisablePLL(const SCG_PllClkType ePll); + +/** + * @brief Set system run time clock and related CORE/BUS/SLOW clock. + * + * @param pSysClkConfig pointer to the clockCtrlType structure data instance,which defined for system clock selection. + * @return SCG_StatusType function status + * SCG_STATUS_SUCCESS : clock source and dividers are valid,and switch system clock successfully + * SCG_STATUS_SEQUENCE_ERROR: new clock source is not enabled + * SCG_STATUS_PARAM_ERROR: the core bus slow divider are invalid + * SCG_STATUS_TIMEOUT: switch system clock procedure time out + */ +SCG_StatusType SCG_SetClkCtrl(const SCG_ClockCtrlType *const pSysClkConfig); + +/** + * @brief Get clock frequency + * + * @param eScgClockName Clock source type + * @return uint32_t frequency value + */ +uint32_t SCG_GetScgClockFreq(const SCG_ClkSrcType eScgClockName); + +/** + * @brief Select clock out source + * + * @param eClkoutSel clock out source + */ +void SCG_SetClkOut(const SCG_ClockoutSrcType eClkoutSel); + +/** + * @brief Select NVM clock source + * + * @param eNvmClkSrc NVM clock source + * @return uint32_t function status + */ +SCG_StatusType SCG_SetNvmClk(const SCG_NvmClkSrcType eNvmClkSrc); + +/** + * @brief Select CMU4 clock source + * + * @param eCmu4ClkSrc CMU4 clock source + * @return SCG_StatusType function status + */ +SCG_StatusType SCG_SetCmu4Clk(const SCG_Cmu4ClkSrcType eCmu4ClkSrc); + +/** + * @brief Generate the origion SCG register CRC result, and configure the SCG register CRC option. + * + * @param eMode The SCG register CRC trigger mode + * @return CRC configure status + * SCG_STATUS_SUCCESS : CRC configure successfully + * SCG_STATUS_TIMEOUT : CRC configure time out + */ +SCG_StatusType SCG_RegCrcConfig(SCG_CrcModeType eMode); + +/** + * @brief Trigger the SCG register CRC generation by software + * + */ +void SCG_RegCrcGenerate(void); + +/** + * @brief Trigger the SCG register CRC generation by software,and wait the CRC check result + * + * @return CRC check result + */ +SCG_CrcCheckResType SCG_RegCrcGenerateWaitResult(void); + +/** + * @brief Clock source De-init + * + * @return SCG_StatusType function status + */ +SCG_StatusType SCG_Deinit(void); + + + +/** @}*/ /* fc7xxx_driver_scg */ +#endif diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_scm.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_scm.h new file mode 100644 index 0000000..dd3c071 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_scm.h @@ -0,0 +1,232 @@ +/** + * @file fc7xxx_driver_scm.h + * @author Flagchip085 + * @brief FC7xxx SCM driver type definition and API + * @version 0.1.0 + * @date 2024-01-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240 + ******************************************************************************** */ + +#ifndef _DRIVER_SCM_H_ +#define _DRIVER_SCM_H_ + +#include "HwA_scm.h" +#include "HwA_csc.h" +#include "interrupt_manager.h" + +/********* Local typedef ************/ +/** + * @brief SCM return status + * + */ +typedef enum +{ + SCM_E_OK = 0U, /*!< Return ok */ + SCM_E_NOT_OK, /*!< Return not ok */ + SCM_E_PARAM, /*!< Return invalid parameters */ + SCM_E_LOCK, /*!< Return register has been locked */ + SCM_E_TIMEOUT, /*!< Return operation timeout */ + SCM_E_CRC /*!< Return CRC check failed */ +} SCM_RetStatusType; + +/** + * @brief CCMx type + * + */ +typedef enum +{ + SCM_CCM0 = 0U /*!< CCM0 */ +} SCM_CCM_Type; + +/** + * @brief Matrixx type + * + */ +typedef enum +{ + SCM_MatrixStatus_0 = 0U, /*!< Matrix status 0 */ + SCM_MatrixStatus_1, /*!< Matrix status 1 */ + SCM_MatrixStatus_2, /*!< Matrix status 2 */ + SCM_MatrixStatus_5, /*!< Matrix status 5 */ + SCM_MatrixStatus_6, /*!< Matrix status 6 */ + SCM_MatrixStatus_7, /*!< Matrix status 7 */ + SCM_MatrixStatus_ID /*!< Matrix ID status */ +} SCM_MatrixStatusType; + +/** + * @brief SCM registers CRC trigger mode + */ +typedef enum +{ + SCM_CRC_SW_MODE = 0U, /*!< SCM registers CRC software mode. */ + SCM_CRC_TRIGGER_MODE = 1U /*!< SCM registers CRC trigger mode. */ +} SCM_CrcModeType; + +/********* Local function ************/ +/** + * @brief Get unique identification for the chip, loaded from NVR. + * + * @param pUid Pointer to UID + * + */ +void SCM_GetChip_UID(uint32 *pUid); + +/** + * @brief Get CCMx status. + * + * @param eCCMType CCM type + * @param u32Value The or value of SCM_CCMxStatusType to select the status to get + * + */ +uint32_t SCM_GetStatus_CCMx(SCM_CCM_Type eCCMType, uint32_t u32Value); + +/** + * @brief Get matrix status. + * + * @param eMatrixType Matrix type + * @param u32Value selection to get + * + */ +uint32_t SCM_GetStatus_Matrix(SCM_MatrixStatusType eMatrixType, uint32_t u32Value); + +/** + * @brief Set cpu to control MAM ECC enable register 0. + * + * @param eCpuType Cpu to use + * @param bLockStatus Lock the cpu control settings + * + * @return Set operation success/failed + */ +SCM_RetStatusType SCM_SetCpuCtrl_MAMECCR0(const SCM_WPB_CpuType eCpuType, bool bLockStatus); + +/** + * @brief Set cpu to control MAM ECC enable register 1. + * + * @param eCpuType Cpu to use + * @param bLockStatus Lock the cpu control settings + * + * @return Set operation success/failed + */ +SCM_RetStatusType SCM_SetCpuCtrl_MAMECCR1(const SCM_WPB_CpuType eCpuType, bool bLockStatus); + +/** + * @brief Set cpu to control CPU0 ECC enable register. + * + * @param eCpuType Cpu to use + * @param bLockStatus Lock the cpu control settings + * + * @return Set operation success/failed + */ +SCM_RetStatusType SCM_SetCpuCtrl_CPU0ECCEN(const SCM_WPB_CpuType eCpuType, bool bLockStatus); + +/** + * @brief Set cpu to control SOCMISC register. + * + * @param eCpuType Cpu to use + * @param bLockStatus Lock the cpu control settings + * + * @return Set operation success/failed + */ +SCM_RetStatusType SCM_SetCpuCtrl_SOCMISC(const SCM_WPB_CpuType eCpuType, bool bLockStatus); + +/** + * @brief Set cpu to control Subsystem pcc register. + * + * @param eCpuType Cpu to use + * @param bLockStatus Lock the cpu control settings + * + * @return Set operation success/failed + */ +SCM_RetStatusType SCM_SetCpuCtrl_SUBSYS_PCC(const SCM_WPB_CpuType eCpuType, bool bLockStatus); + +/** + * @brief Set cpu to control master halt request register. + * + * @param eCpuType Cpu to use + * @param bLockStatus Lock the cpu control settings + * + * @return Set operation success/failed + */ +SCM_RetStatusType SCM_SetCpuCtrl_MASTER_HALT_REQ(const SCM_WPB_CpuType eCpuType, bool bLockStatus); + +/** + * @brief Set lock FTU_ROUTING register. + * + */ +void SCM_SetLock_FTU_ROUTING(void); + +/** + * @brief Set lock FTU_GTB register. + * + */ +void SCM_SetLock_FTU_GTB(void); + +/** + * @brief Set lock DEBUG_TRACE register. + * + */ +void SCM_SetLock_DEBUG_TRACE(void); + +/** + * @brief Set lock FLEXCAN_ROUTING register. + * + */ +void SCM_SetLock_FLEXCAN_ROUTING(void); + +/** + * @brief Set lock MSC0_ROUTING register. + * + */ +void SCM_SetLock_MSC0_ROUTING(void); + +/** + * @brief Set lock INT_ROUTER_NMI register. + * + */ +void SCM_SetLock_INT_ROUTER_NMI(void); + +/** + * @brief Set NMI interrupt router . + * + * @param eCpuType Cpu to use + * @param bEnable Enable/Disable + * @return Set operation success/failed + * SCM_E_OK: Set NMI interrupt router successfully + * SCM_E_PARAM: eCpuType invalid + */ +SCM_RetStatusType SCM_SetEnable_NMIIntRouter(const SCM_WPB_CpuType eCpuType, bool bEnable); + +/** + * @brief Generate the origion SCM register CRC result, and configure the SCM register CRC option. + * + * @param eMode The SCM register CRC trigger mode + * @return CRC configure status + * SCM_E_OK : CRC configure successfully + * SCM_E_TIMEOUT : CRC configure time out + */ +SCM_RetStatusType SCM_RegCrcConfig(SCM_CrcModeType eMode); + +/** + * @brief Trigger the SCM register CRC generation by software + * + */ +void SCM_RegCrcGenerate(void); + +/** + * @brief Trigger the SCM register CRC generation by software,and wait the CRC check result + * + * @return CRC check result + */ +SCM_RetStatusType SCM_RegCrcGenerateWaitResult(void); + + +#endif /* end of _DRIVER_SCM_H_ */ diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_scst.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_scst.h new file mode 100644 index 0000000..7a11c88 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_scst.h @@ -0,0 +1,137 @@ +/** + * @file fc7xxx_driver_scst.h + * @author Flagchip + * @brief FC7xxx scst driver type definition and API + * @version 0.1.0 + * @date 2023-12-29 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + */ +/********************************************************************************* +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2023-12-29 qxw074 N/A First version for FC7240 +******************************************************************************** */ + +#ifndef _DRIVER_FC7XXX_DRIVER_SCST_H_ +#define _DRIVER_FC7XXX_DRIVER_SCST_H_ + +#include "device_header.h" + +/** + * @addtogroup fc7xxx_driver_scst + * @{ + */ + +/** + * @brief typed of test result returned + * + */ +typedef enum +{ + M7ST_FaultInjectError, + M7ST_ErrorAluTest, + M7ST_ErrorAluMLATest, + M7ST_ErrorAluSHIFTTest, + M7ST_ErrorAluTes1t, + M7ST_ErrorAluTest2, + M7ST_ErrorAluTest3, + M7ST_ErrorAluTest4, + M7ST_ErrorAluTest5, + M7ST_ErrorAluTest6, + M7ST_ErrorRegbankTest1, + M7ST_ErrorRegbankTest2, + M7ST_ErrorRegbankTest3, + M7ST_ErrorRegbankTest4, + M7ST_ErrorRegbankTest5, + M7ST_ErrorRegbankTest6, + M7ST_ErrorLoadStoreTest1, + M7ST_ErrorLoadStoreTest2, + M7ST_ErrorLoadStoreTest3, + M7ST_ErrorLoadStoreTest4, + M7ST_ErrorLoadStoreTest5, + M7ST_ErrorLoadStoreTest6, + M7ST_ErrorSimdSatTest1, + M7ST_ErrorSimdSatTest2, + M7ST_ErrorSimdSatTest3, + M7ST_ErrorSimdSatTest4, + M7ST_ErrorMacTest1, + M7ST_ErrorMacTest2, + M7ST_ErrorFetchTest, + M7ST_ErrorStatusTest1, + M7ST_ErrorStatusTest2, + M7ST_ErrorBranchTest1, + M7ST_ErrorBranchTest2, + M7ST_ErrorIntSvcTest, + M7ST_ErrorIntBusFaultTest, + M7ST_ErrorIntHardFaultTest1, + M7ST_ErrorIntHardFaultTest2, + M7ST_ErrorIntUsageFaultTest, + M7ST_ErrorIntSystickTest, + M7ST_ErrorIntPendSvTest, + M7ST_ErrorIntMemFaultTest, + M7ST_ErrorIntMaskingTest, + M7ST_ErrorIntHandlerThreadsTest, + M7ST_ErrorIntNMIHfTest, + M7ST_ErrorIntTailChainTest, + M7ST_ErrorIntAluTest, + M7ST_ErrorIntBranchTest, + M7ST_ErrorIntStatusTest, + M7ST_ErrorM7ST_TestPass +} Type_M7ST_AtomicStatus; + +/** + * @brief typed of test index + * + */ +typedef enum +{ + M7ST_AluTest, + M7ST_AluMLATest, + M7ST_AluSHIFTTest, + M7ST_AluTes1t, + M7ST_AluTest2, + M7ST_AluTest3, + M7ST_AluTest4, + M7ST_AluTest5, + M7ST_AluTest6, + M7ST_RegbankTest1, + M7ST_RegbankTest2, + M7ST_RegbankTest3, + M7ST_RegbankTest4, + M7ST_RegbankTest5, + M7ST_RegbankTest6, + M7ST_LoadStoreTest1, + M7ST_LoadStoreTest2, + M7ST_LoadStoreTest3, + M7ST_LoadStoreTest4, + M7ST_LoadStoreTest5, + M7ST_LoadStoreTest6, + M7ST_SimdSatTest1, + M7ST_SimdSatTest2, + M7ST_SimdSatTest3, + M7ST_SimdSatTest4, + M7ST_MacTest1, + M7ST_MacTest2, + M7ST_FetchTest, + M7ST_StatusTest1, + M7ST_StatusTest2, + M7ST_BranchTest1, + M7ST_BranchTest2, + M7ST_RegressionTest +} SCST_TestIndexType; + +/** + * @brief This function is used to get the result of the executed test + * + * @param test_index is test number,0U..32U + * @param s_u32RamBase The first address of the 1k memory that the program needs to run + * @return M7ST_ErrorM7ST_TestPass is ok, others are not ok + */ +Type_M7ST_AtomicStatus SCST_ExecuteTest(SCST_TestIndexType test_index,uint32_t *s_u32RamBase); + +/** @}*/ /* fc7xxx_driver_scst */ +#endif diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_sec.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_sec.h new file mode 100644 index 0000000..9f842af --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_sec.h @@ -0,0 +1,371 @@ +/** + * @file fc7xxx_driver_sec.h + * @author Flagchip + * @brief FC7xxx sec driver type definition and API + * @version 0.2.0 + * @date 2023-2-7 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/******************************************************************************** +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.2.0 2023-2-7 Flagchip076 N/A First version for FC7300 +********************************************************************************/ + + +#ifndef _DRIVER_SEC_H_ +#define _DRIVER_SEC_H_ + +#include "HwA_sec.h" +#include "device_header.h" + +/** + * @addtogroup fc7xxx_driver_sec + * @{ + */ + +/** + * @brief Debug Re-Enable Key + * @note Only if four 32-bit writes match, it will set the DEN to 0x5 to enable + debug and unlock SEC registers. The key is up to the user to decide in advance. + * */ +typedef struct +{ + uint32_t Re_key0; /*!< The Debug Re-enable key 0*/ + uint32_t Re_key1; /*!< The Debug Re-enable key 1*/ + uint32_t Re_key2; /*!< The Debug Re-enable key 2*/ + uint32_t Re_key3; /*!< The Debug Re-enable key 3*/ + +} ReEnDebug_Keys; + +typedef enum +{ + SEC_STATUS_SUCCESS = 0U, /*!< SEC status success */ + SEC_STATUS_FAILED = 1U /*!< SEC status failed */ +}SEC_RetType; + +/** + * @brief NVR write and read Permissions. + * @*/ +typedef struct +{ + bool WritEn; /*!< The NVR write permission*/ + bool ReadEn; /*!< The NVR read permission*/ + bool EraseEn; /*!< The NVR Erase permission*/ +} NVR_Per; + +/** + * @brief Indicate the system state + * + * */ +typedef enum +{ + Securedstate = 0u, /*!< The system is in secured state*/ + UnSecuredstate = 1u /*!< The system is in no secured state*/ +} Systemstate; + +/** + * @brief Indicate the ISP instance + * + * */ +typedef enum +{ + ISP_FCUART1 = 0U, /*!< The ISP instance is FCUART1 */ + ISP_FCUART3 = 1U, /*!< The ISP instance is FCUART3 */ + ISP_FLEXCAN1 = 2U, /*!< The ISP instance is FLEXCAN1 */ + ISP_FLEXCAN5 = 3U /*!< The ISP instance is FLEXCAN3 */ +}Isp_Instance; + +/** + * @brief Indicate the FCUART Baud Rate for ISP + * + * */ +typedef enum +{ + ISP_FCUART_2MBPS =0u, /*!< the FCUART Baud Rate is 2Mbps*/ + ISP_FCUART_1MBPS =1u, /*!< the FCUART Baud Rate is 1Mbps*/ + ISP_FCUART_512KBPS =2u, /*!< the FCUART Baud Rate is 512kbps*/ + ISP_FCUART_115200BPS =3u, /*!< the FCUART Baud Rate is 115200bps*/ + ISP_FCUART_INVALID = 4u /*!< the ISP instance is not FCUART*/ +}FCUART_ISP_BAUDRATE; + +/** + * @brief Indicate the FLEXCAN Baud Rate for ISP + * + * */ +typedef enum +{ + ISP_FLEXCANFD_4MBPS =0u, /*!< the CANFD Baud Rate is 4Mbps*/ + ISP_FLEXCANFD_2MBPS =1u, /*!< the CANFD Baud Rate is 2Mbps*/ + ISP_FLEXCAN_1MBPS =2u, /*!< the CAN Baud Rate is 1Mbps*/ + ISP_FLEXCAN_500kBPS =3u, /*!< the FCUART Baud Rate is 500kbps*/ + ISP_FLEXCAN_INVALID = 4u /*!< the ISP instance is not FLEXCAN*/ +}FLEXCAN_ISP_BAUDRATE; + +/** + * @brief Indicate the ISP information. + * + * */ +typedef struct +{ + bool IspModeEn; /*!< true means - ISP mode is active.*/ + bool IspPinEn; /*!< true means - ISP pin is active.The associated pin defaults to internal pull up enabled.*/ + bool IspAuthEn; /*!<*true means - ISP Auth Enable. Only valid in secure boot. (Value loaded from NVR sector)*/ + Isp_Instance Ispinstance; /*!< the Isp instance*/ + FCUART_ISP_BAUDRATE Ispfcuartbaudrate; /*!< Indicate the FCUART Baud Rate for ISP*/ + FLEXCAN_ISP_BAUDRATE Ispflexcanbaudrate; /*!< Indicate the FLEXCAN Baud Rate for ISP*/ + +}SEC_IspInfo; + +/** + * @brief Indicate the fast boot speed. + * + * */ +typedef enum +{ + FASTBOOT_300MHZ = 0u, /*!< Select PLL0 as the core clock source; the core clock is 300MHz.*/ + FASTBOOT_96MHZ = 1u /*!< Select FIRC as the core clock source; the core clock is 96MHz.*/ +}FastBoot_Speed; + +/** + * @brief Indicate the OSC Frequency + * + * */ +typedef enum +{ + OSC_8MHZ = 0u, /*!SENT_CHN[echannel].CHN_DFD)) +#define SENT_GET_FAST_MSG_DMA_BYTELENGTH (12U) +#define SENT0_GET_SLOW_MSG_DMA_ADDR(echannel) (&(SENT->SENT_CHN[echannel].CHN_DSB3)) +#define SENT_GET_SLOW_MSG_DMA_BYTELENGTH (12U) + + /** + * @brief SENT operation return values + * + */ + typedef enum + { + SENT_RETURN_OK = 0x00U, /*!< The SENT operation is succeeded */ + SENT_RETURN_E_NOT_OK = 0x01U, /*!< The SENT operation is failed */ + SENT_RETURN_E_ALREADY_INIT = 0x02U, /*!< The SENT has been initialized. */ + SENT_RETURN_E_UNINIT = 0x03U, /*!< The SENT is not initialized */ + SENT_RETURN_E_PARAM = 0x04U, /*!< The SENT parameter is incorrect or out of range. */ + } + Sent_ReturnType; + + /** + * @brief SENT Channel index + * + */ + typedef enum + { + SENT_CHANNEL_0 = 0x00U, /*!< The SENT channel 0 */ + SENT_CHANNEL_1 = 0x01U, /*!< The SENT channel 1 */ + SENT_CHANNEL_2 = 0x02U, /*!< The SENT channel 2 */ + SENT_CHANNEL_3 = 0x03U, /*!< The SENT channel 3 */ + SENT_CHANNEL_MAX = SENT_CHANNEL_COUNT + } Sent_ChannelType; + + /** + * @brief SENT instance index + * + */ + typedef enum + { + SENT_INSTANCE_0 = 0x00U, /*!< The SENT channel 0 */ + SENT_INSTANCE_1 = 0x01U, /*!< The SENT channel 1 */ + SENT_INSTANCE_MAX = SENT_INSTANCE_COUNT + } Sent_InstanceType; + + /** + * @brief SENT nibble data mode control. Refer to SENT SAE J2716 2010 for detail protocol definition + * + */ + typedef enum + { + SENT_DATA_NIBBLE_MODE_A = 0x0U, /*!< Frame format A */ + SENT_DATA_NIBBLE_MODE_H1 = 0x1U, /*!< Frame format H1 */ + SENT_DATA_NIBBLE_MODE_H2 = 0x2U, /*!< Frame format H2 */ + SENT_DATA_NIBBLE_MODE_H3 = 0x3U, /*!< Frame format H3 */ + SENT_DATA_NIBBLE_MODE_H4 = 0x4U, /*!< Frame format H4 */ + SENT_DATA_NIBBLE_MODE_H5 = 0x5U, /*!< Frame format H5 */ + SENT_DATA_NIBBLE_MODE_H6 = 0x6U, /*!< Frame format H6 */ + SENT_DATA_NIBBLE_MODE_H7 = 0x7U /*!< Frame format H7 */ + } Sent_DataNibbleModeType; + + /** + * @brief SENT calibration valid type + * + */ + typedef enum + { + SENT_CALIBRATION_VALID_DISABLE = 0x0U, /*!< The successive calibration pulses diagnostic will be disabled */ + SENT_CALIBRATION_VALID_WITHIN_20 = 0x1U, /*!< The difference of received calibration pulse and receiver configuration is within 20%, the message is deemed to be valid */ + SENT_CALIBRATION_VALID_FROM_20_TO_25 = 0x2U, /*!< The difference of received calibration pulse and receiver configuration is more than 20% but less than 25%, the message is deemed to be valid */ + } Sent_CalibrationValidType; + + /** + * @brief SENT Successive calibration pulses diagnostic option + * + */ + typedef enum + { + SENT_CALIBRATION_PULSE_DIAG_OPTION2 = 0x0U, /*!< Option 2 i.e. Low Latency Option as per SAE Specification */ + SENT_CALIBRATION_PULSE_DIAG_OPTION1 = 0x1U, /*!< Option 1 i.e. Preferred but High Latency Option as per SAE Specification */ + } Sent_CalDiagOptionType; + + /** + * @brief Determines how long the bus idle flag will assert when SENT bus is idle + * + */ + typedef enum + { + SENT_IDLE_COUNT_FLAG_DISABLE = 0x0U, /*!< The bus idle flag will never assert */ + SENT_IDLE_COUNT_FLAG_254_TICKS = 0x1U, /*!< The bus is idle for more than 127*2 ticks, then the bus idle flag will assert */ + SENT_IDLE_COUNT_FLAG_508_TICKS = 0x2U, /*!< The bus is idle for more than 127*2 ticks, then the bus idle flag will assert */ + SENT_IDLE_COUNT_FLAG_1016_TICKS = 0x4U, /*!< The bus is idle for more than 127*2 ticks, then the bus idle flag will assert */ + SENT_IDLE_COUNT_FLAG_2032_TICKS = 0x8U, /*!< The bus is idle for more than 127*2 ticks, then the bus idle flag will assert */ + } Sent_IdleCountType; + + /** + * @brief SENT Slow message type. + * + */ + typedef enum + { + SENT_SERIAL_MESSAGE_SHORT = 0x0U, /*!< short serial data message */ + SENT_SERIAL_MESSAGE_ENHANCE_12DATA_8ID = 0x1U, /*!< enhanced serial data message with 12-bit data and 8-bit ID */ + SENT_SERIAL_MESSAGE_ENHANCE_16DATA_4ID = 0x2U, /*!< enhanced serial data message with 16-bit data and 4-bit ID */ + } Sent_SerialMessageType; + + /** + * @brief SENT trigger type in SPC mode + * + */ + typedef enum + { + SENT_SPC_SOFTWARE_TRIGGER = 0x0U, /*!< SPC pulse triggered by software method */ + SENT_SPC_EXTERNAL_TRIGGER = 0x1U, /*!< SPC pulse triggered by external trigger */ + } Sent_SpcTriggerType; + + /** + * @brief Select the tick base in SPC mode + * + */ + typedef enum + { + SENT_SPC_TICK_BASE_PRE_MSG = 0x0U, /*!< Previous received message tick base */ + SENT_SPC_TICK_BASE_CONFIGURED = 0x1U, /*!< SENT configured tick base */ + } Sent_SpcTickBaseType; + + /** + * @brief Sent global interrupt type. + * + */ + typedef enum + { + SENT_SLOW_MSG_DMA_UF_IT = 0U, /*!< Slow message dma read underflow interrupt enable. */ + SENT_FAST_MSG_DMA_DF_IT = 1U, /*!< Fast message dma read underflow interrupt enable. */ + SENT_FAST_MSG_READY_IT = 2U, /*!< Fast message ready interrupt enable. */ + SENT_SLOW_MSG_READY_IT = 3U, /*!< Slow message ready interrupt enable. */ + SENT_FAST_MSG_FIFO_OF_IT = 4U, /*!< Fast message FIFO overflow interrupt enable. */ + } Sent_GlobalInterruptType; + + /** + * @brief Structure to enable or disable the channel interrupts. + * + */ + typedef struct + { + bool bBusIdleITEn; /*!< Bus idle interrupt enable. */ + bool bSpcOverrunITEn; /*!< SPC overrun interrupt enable. */ + bool bCalResyncErrITEn; /*!< Continuous 2 sync/calibration pulse difference exceed 1.5625% error interrupt enable. */ + bool bCalFailITEn; /*!< Calibation 20% pass 25% fail interrupt enable. */ + bool bSlowMsgOFITEn; /*!< Slow message overflow interrupt enable. */ + bool bFastMsgOFITEn; /*!< Fast message overflow interrupt enable. */ + bool bNibbleValueErrITEn; /*!< Nibble value more than 15 or less than 0 error interrupt enable. */ + bool bPrePulseDiagErrITEn; /*!< Previous pulse diagnosis error interrupt enable. */ + bool bCalDiagErrITEn; /*!< Calibration diagnosis over 25% error interrupt enable. */ + bool bCalErrITEn; /*!< Sync/calibration pulse difference eceed 1.5625% error interrupt enable. */ + bool bSlowMsgCrcErrITEn; /*!< Slow message CRC check error interrupt enable. */ + bool bFastMsgCrcErrITEn; /*!< Fast message CRC check error interrupt enable. */ + bool bFallingEdgeNumErrITEn; /*!< Falling edge number error interrupt enable. */ + } Sent_ChannelInterruptType; + + /** + * @brief Structure for fast message buffer. + * + */ + typedef struct + { + uint8_t u8CRC; /*!< Receied fast message CRC data. */ + uint8_t u8SC; /*!< Fast message status communication nibble value. */ + uint32_t u32Timestamp; /*!< Fast message timestamp value. */ + uint32_t u32Data; /*!< Received fast message data nibble. */ + } Sent_FastMessageDataType; + + /** + * @brief Structure for slow message buffer. + * + */ + typedef struct + { + Sent_SerialMessageType eMsgType; /*!< Slow message type. */ + uint8_t u8CRC; /*!< Slow message crc data. */ + uint8_t u8ID; /*!< Slow message ID. */ + uint16_t u16Data; /*!< Slow message data. */ + uint32_t u32Timestamp; /*!< Slow message timestamp value. */ + } Sent_SlowMessageDataType; + + /** + * @brief SENT Global ISR callback function prototype + * + */ + typedef void (*SENT_GBISRCallbackType)(Sent_ChannelType eChannel, const Sent_GlobalInterruptType eInterrupt); + + /** + * @brief SENT Channel ISR callback function prototype + * + */ + typedef void (*SENT_CHISRCallbackType)(Sent_ChannelType eChannel, const uint32_t u32ChannelStatus); + + /** + * @brief structure to configure the SENT. + * + */ + typedef struct + { + uint8_t u8PreScaler; /**/ + STCU_SELFTEST_DONE = 0x01U, /***/ + STCU_SELFTEST_ABORT = 0x02U, /***/ + STCU_SELFTEST_LBIST_ERROR = 0x10U, /***/ + STCU_SELFTEST_MBIST_ERROR = 0x20U, /***/ + STCU_SELFTEST_TIMEOUT_ERROR = 0x40U, /***/ + STCU_SELFTEST_NVRLOAD_ERROR = 0x100U, /***/ + STCU_SELFTEST_SELFCHECK_ERROR = 0x200u /***/ +}STCU_SelfTestStatusType; + +/** @brief STCU interrupt flag */ +typedef enum +{ + STCU_INTERRUPT_FLAG_NONE = 0x00U, /***/ + STCU_INTERRUPT_FLAG_SIZE_ERR = 0x01U, /***/ + STCU_INTERRUPT_FLAG_SEQ_ERR = 0x02U, /***/ +}STCU_InterruptFlagType; + +/** @brief The items select for MBIST */ +typedef enum +{ + STCU_MBIST_SEL_NONE = 0x00U, /***/ + STCU_MBIST_SEL_SRAM = 0x01U, /***/ + STCU_MBIST_SEL_ITCM_CPU0 = 0x02U, /***/ + STCU_MBIST_SEL_DTCM0_CPU0 = 0x04U, /***/ + STCU_MBIST_SEL_DTCM1_CPU0 = 0x08U, /***/ + STCU_MBIST_SEL_CACHE_CPU0 = 0x10U, /***/ + STCU_MBIST_SEL_SUBSYS = 0x20U, /***/ + STCU_MBIST_SEL_SRAM_HSM = 0x40U, /***/ + STCU_MBIST_SEL_SRAM_DMACAN = 0x80U, /***/ + STCU_MBIST_SEL_ROM_HOST = 0x100U, /***/ + STCU_MBIST_SEL_ROM_HSM = 0x200U /***/ +}STCU_MbistSelType; + +/** @brief MBIST done status flag. */ +typedef enum +{ + STCU_MBIST_DONE_NONE = 0x00U, /***/ + STCU_MBIST_DONE_SRAM = 0x01U, /***/ + STCU_MBIST_DONE_ITCM_CPU0 = 0x02U, /***/ + STCU_MBIST_DONE_DTCM0_CPU0 = 0x04U, /***/ + STCU_MBIST_DONE_DTCM1_CPU0 = 0x08U, /***/ + STCU_MBIST_DONE_CACHE_CPU0 = 0x10U, /***/ + STCU_MBIST_DONE_SUBSYS = 0x20U, /***/ + STCU_MBIST_DONE_SRAM_HSM = 0x40U, /***/ + STCU_MBIST_DONE_SRAM_DMACAN = 0x80U, /***/ + STCU_MBIST_DONE_ROM_HOST = 0x100U, /***/ + STCU_MBIST_DONE_ROM_HSM = 0x200U /***/ +}STCU_MbistDoneType; + +/** @brief MBIST fail status flag. */ +typedef enum +{ + STCU_MBIST_FAIL_NONE = 0x00U, /***/ + STCU_MBIST_FAIL_SRAM = 0x01U, /***/ + STCU_MBIST_FAIL_ITCM_CPU0 = 0x02U, /***/ + STCU_MBIST_FAIL_DTCM0_CPU0 = 0x04U, /***/ + STCU_MBIST_FAIL_DTCM1_CPU0 = 0x08U, /***/ + STCU_MBIST_FAIL_CACHE_CPU0 = 0x10U, /***/ + STCU_MBIST_FAIL_SUBSYS = 0x20U, /***/ + STCU_MBIST_FAIL_SRAM_HSM = 0x40U, /***/ + STCU_MBIST_FAIL_SRAM_DMACAN = 0x80U, /***/ + STCU_MBIST_FAIL_ROM_HOST = 0x100U, /***/ + STCU_MBIST_FAIL_ROM_HSM = 0x200U /***/ +}STCU_MbistFailedType; + +/** @brief Hardware SRAM initialization mode. */ +typedef enum +{ + STCU_INIT_RAM_MODE_POR_OR_WAKEUP4STANDBY0 = 0U, /***/ + STCU_INIT_RAM_MODE_AFTER_WAKEUP4STANDBY1, /***/ + STCU_INIT_RAM_MODE_AFTER_WAKEUP4STANDBY2, /***/ + STCU_INIT_RAM_MODE_AFTER_WAKEUP4STANDBY3 /***/ +}STCU_InitRamModeType; + +/** @brief The items select for Hardware SRAM Initialization. */ +typedef enum +{ + STCU_INIT_RAM_TYPE_NONE = 0x00U, /***/ + STCU_INIT_RAM_TYPE_SRAM = 0x01U, /***/ + STCU_INIT_RAM_TYPE_ITCM_CPU0 = 0x02U, /***/ + STCU_INIT_RAM_TYPE_DTCM0_CPU0 = 0x04U, /***/ + STCU_INIT_RAM_TYPE_DTCM1_CPU0 = 0x08U, /***/ +}STCU_InitRamType; + +/** @brief Init Ram done status flag. */ +typedef enum +{ + STCU_INIT_RAM_DONE_TYPE_NONE = 0x00U, /***/ + STCU_INIT_RAM_DONE_TYPE_SRAM = 0x01U, /***/ + STCU_INIT_RAM_DONE_TYPE_ITCM_CPU0 = 0x02U, /***/ + STCU_INIT_RAM_DONE_TYPE_DTCM0_CPU0 = 0x04U, /***/ + STCU_INIT_RAM_DONE_TYPE_DTCM1_CPU0 = 0x08U, /***/ +}STCU_InitRamDoneType; + +/** @brief Init Ram status flag. */ +typedef enum +{ + STCU_HARDWARE_INIT_RAM_STATUS_NONE = 0U, /***/ + STCU_HARDWARE_INIT_RAM_STATUS_DONE = 1U, /***/ + STCU_HARDWARE_INIT_RAM_STATUS_BUSY = 2U, /***/ + STCU_HARDWARE_INIT_RAM_STATUS_ABORT = 4U /***/ +}STCU_HardwareInitRamStatusType; + +/** @brief LBIST status flag. */ +typedef enum +{ + STCU_LBIST_STATUS_NONE = 0U, /***/ + STCU_LBIST_STATUS_DONE = 1U, /***/ + STCU_LBIST_STATUS_FAILED = 2U /***/ +}STCU_LbistStatusType; + +/** @brief LBIST Clock Divider. */ +typedef enum +{ + STCU_LBIST_CLK_DIVIDER_BY_2 = 1U, /***/ + STCU_LBIST_CLK_DIVIDER_BY_3 = 2U, /***/ + STCU_LBIST_CLK_DIVIDER_BY_4 = 3U, /***/ +}STCU_LbistClkDivType; + +/** @brief clock source of self-test. */ +typedef enum +{ + STCU_CLK_SOURCE_FIRC = 0U, /***/ + STCU_CLK_SOURCE_PLL = 1U /***/ +}STCU_ClkSourceType; + +/** @brief Self-test Port Pull Selection. */ +typedef enum +{ + STCU_PORT_PULL_DISABLE = 0U, /***/ + STCU_PORT_PULL_DOWN, /***/ + STCU_PORT_PULL_UP /***/ +}STCU_PortPullModeType; + +/** @brief Stcu call back function type, the u32status should refer to "STCU_InterruptFlagType" */ +typedef void (*Stcu_IRQCallback)(uint32_t u32Status); + +typedef struct +{ + bool bLbistEn; /***/ + bool bMbistLPC; /***/ + bool bMbistEn; /***/ + bool bMbistFullTest; /***/ + bool bMbistSramInit; /***/ + bool bInterruptEn; /***/ + STCU_PortPullModeType ePortPullMode; /***/ + STCU_ClkSourceType eClkSource; /***/ + STCU_LbistClkDivType eLbistClkDivider; /***/ + uint16_t u16MaxTime; /***/ + uint32_t u32MbistSel; /***/ +}STCU_ConfigType; + + +typedef struct +{ + STCU_InitRamModeType eInitMode; /**< RAM Initial Mode */ + uint8_t bLockAfterEn; /**< Lock STCU after RAM Initial */ + uint32_t u32InitRamType; /**< RAM Type, DTCM, ITCM, SRAM, refer to "STCU_InitRamType" and use OR to combine them */ +}STCU_InitRamConfigType; + + +/** + * \brief Init the STCU module + * + * \param pConfig the configuration structure + */ +void STCU_Init(STCU_ConfigType *pConfig); + +/** + * \brief Trigger to start Software self test + * + */ +void STCU_StartSelfTest(void); + +/** + * \brief Check Software Trigger Self-test result + * + * \return refer to "STCU_SelfTestStatusType" enum. + */ +uint32_t STCU_CheckTriggerResult(void); + +/** + * \brief Initial RAM with hardware + * + * \param pConfig the configuration structure + */ +void STCU_StartRamInit(STCU_InitRamConfigType *pInitCfg); + +/** + * \brief Get status of RAM initialize action + * + * \return the status of ram initialize action, refer to "STCU_HardwareInitRamStatusType" + */ +uint32_t STCU_GetRamInitStatus(void); + +/** + * \brief Get if the LBIST test result is Fail + * + * \return true means LBIST fail. false means LBIST pass. + */ +bool STCU_GetLbistFailResult(void); +/** + * \brief Get each MBIST Fail result + * + * \return refer to "STCU_MbistFailedType" enum. + */ +uint32_t STCU_GetMbistFailResult(void); + +/** + * \brief Get each done status of SRAM initialize + * + * \return the done status of SRAM initialize action, refer to "STCU_InitRamDoneType" + */ +uint32_t STCU_GetRamInitDoneStatus(void); + +/** + * \brief Set the LBIST Pattern value and expected misr value. + * The two value should be load from NVR, but also can reconfigure by this API. + * The expected misr value is calculated from pattern, so please make sure this two value is right, or the LBST would fail. + * + * \param u16Pattern the LBIST Pattern value + * \param u16Pattern the LBIST expected misr value + */ +void STCU_LBIST_Set_Pattern_Misr(uint16_t u16Pattern, uint32_t u32ExpectedMisr); + +/** + * \brief Get LBIST actual MISR value, the value should be read and use DFT tool to decode it, if LBIST test resault is fail. + * + * \return the LBIST actual MISR value + */ +uint32_t STCU_GetLbistAcutalMisr(void); + +/** + * @brief STCU 0 interrupt handler + * + * @note This function should be called as/in STCU 0 interrupt handler + */ +void STCU0_IRQHandler(void); +#endif /* end of _DRIVER_STCU_H_ */ diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_systick.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_systick.h new file mode 100644 index 0000000..5517e64 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_systick.h @@ -0,0 +1,28 @@ +#ifndef _DRIVER_CORE_SYSTICK_H_ +#define _DRIVER_CORE_SYSTICK_H_ + +#include "device_header.h" + + +/** + * \brief Config system tick + * + * \param u32ReloadVal reload value, val is decrease from reload value + * \return 0 is ok, and others are not ok + */ +uint8_t Core_SysTick_Config(uint32_t u32ReloadVal); + +void Core_SysTick_DeConfig(void); + +void Core_SysTick_SetValue(uint32_t u32Value); + +void Core_SysTick_ClearValue(void); + +uint32_t Core_SysTick_GetValue(void); + +void Core_SysTick_Enable(void); + +void Core_SysTick_Disable(void); + + +#endif /* end of _DRIVER_CORE0_SYSTICK_H_ */ diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_tmu.h b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_tmu.h new file mode 100644 index 0000000..711afec --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Inc/fc7xxx_driver_tmu.h @@ -0,0 +1,156 @@ +/** + * @file fc7xxx_driver_tmu.h + * @author Flagchip + * @brief FC7xxx TMU driver type definition and API + * @version 0.1.0 + * @date 2023-12-29 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + */ +/********************************************************************************* +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2023-12-29 qxw074 N/A First version for FC7240 +******************************************************************************** */ + +#ifndef _DRIVER_FC7XXX_DRIVER_TMU_H_ +#define _DRIVER_FC7XXX_DRIVER_TMU_H_ +#include "device_header.h" +#include "HwA_tmu.h" + +#if defined(__cplusplus) +extern "C" { +#endif +/** + * @addtogroup fc7xxx_driver_tmu + * @{ + */ + +/** + * @brief The Flag-based temperature sensor over 150 Celsius callback function prototype + * + */ +typedef void (*TMU_TempOver150InterruptCallbackType)(void); + +/** + * @brief The Flag-based temperature sensor over 125 Celsius callback function prototype + * + */ +typedef void (*TMU_TempOver125InterruptCallbackType)(void); + +/** + * @brief The Flag-based temperature sensor ready callback function prototype + * + */ +typedef void (*TMU_TempFlagReadyInterruptCallbackType)(void); + +/** + * @brief The Voltage-based temperature sensor ready callback function prototype + * + */ +typedef void (*TMU_TempVoltageReadyInterruptCallbackType)(void); + +/** + * @brief TMU operation return values + * + */ +typedef enum +{ + TMU_STATUS_ERROR = 0x0U, /*!< The TMU operation is failed */ + TMU_STATUS_SUCCESS = 0x1U, /*!< The TMU operation is succeed */ + TMU_STATUS_TIMEOUT = 0x2U /*!< The TMU operation is failed because of time out */ +} TMU_StatusType; + +/** + * @brief Defines the temperature sensor configuration + * + * This structure is used to configure for Flag-based temperature sensor ane Voltage-based temperature sensor + * + * Implements : TMU_InitType + */ +typedef struct +{ + TMU_LockType eTempRegisterLockCon; /*!eResolution = ADC_RESOLUTION_12_BIT; /* 12 bit Resolution */ + pInitCfg->eAlign = ADC_ALIGN_RIGHT; /* Align right */ + pInitCfg->eTriggerMode = ADC_TRIGMODE_SW; /* Software trigger */ + pInitCfg->bWaitEnable = false; /* Disable wait conversion mode */ + pInitCfg->bSequenceGroupModeEnable = false; /* Disable sequence group mode */ + pInitCfg->eTrgLatchUnitPri = TRG_LATCH_UNIT_PRI_ROUND_ROBIN; /* Round Robin priority */ + pInitCfg->eClockDivider = ADC_CLOCK_DIV_1; /* Adc clock divided by 1 */ + pInitCfg->eSequenceMode = ADC_SEQMODE_SINGLE; /* Single sequence mode */ + pInitCfg->bAutoDis = false; /* Disable auto disable mode */ + pInitCfg->eOverrunMode = ADC_OVERRUN_MODE_PRESERVE; /* Old conversion data preserved when overrun occured */ + pInitCfg->eVoltageRef = ADC_REF_INTERNAL; /* Use internal reference */ + pInitCfg->bHwAvgEnable = false; /* Disable averaging functionality */ + pInitCfg->eHwAverage = ADC_AVERAGE_4; /* Average by 4 samples if average is enabled */ + pInitCfg->aSampleTimes[0] = ADC_DEFAULT_SAMPLE_TIME_OPTION_0; /* Sample time option 0 is 4 ADC Clock */ + pInitCfg->aSampleTimes[1] = ADC_DEFAULT_SAMPLE_TIME_OPTION_1; /* Sample time option 1 is 10 ADC Clock */ + pInitCfg->aSampleTimes[2] = ADC_DEFAULT_SAMPLE_TIME_OPTION_2; /* Sample time option 2 is 34 ADC Clock */ + pInitCfg->aSampleTimes[3] = ADC_DEFAULT_SAMPLE_TIME_OPTION_3; /* Sample time option 3 is 130 ADC Clock */ +} + +void ADC_Init(const ADC_InstanceType eInstance, const ADC_InitType *const pInitCfg) +{ + DEV_ASSERT(eInstance < ADC_INSTANCE_COUNT); + DEV_ASSERT(pInitCfg != NULL); + + ADC_Type *const pAdc = s_apAdcBase[eInstance]; + uint32_t u32TimeOut = 15000000U; + uint32_t u32Cfg1; + uint32_t u32Cfg2; + uint32_t u32Cal; + ADC_TrigSrcType eTriggerSrc; + ADC_TrigModeType eTriggerMode; + uint32_t u32ClockDiv; + uint32_t u32StartupCnt; + + if (pInitCfg->bSequenceGroupModeEnable == false) + { + if (pInitCfg->eSequenceMode == ADC_SEQMODE_DISCONTINUOUS_1) + { + eTriggerSrc = ADC_TRIGSRC_PTIMER; + eTriggerMode = ADC_TRIGMODE_RISING_EDGE; + } + else + { + eTriggerSrc = ADC_TRIGSRC_TRGSEL; + eTriggerMode = pInitCfg->eTriggerMode; + } + } + else + { + eTriggerSrc = ADC_TRIGSRC_TRIG_LATCH_UNIT; + eTriggerMode = ADC_TRIGMODE_RISING_EDGE; + } + + PCC_ClkSrcType eAdcClkName = PCC_CLK_ADC0; + uint32_t u32AdcClk; + + switch (eInstance) + { + case ADC_INSTANCE_0: + { + eAdcClkName = PCC_CLK_ADC0; + break; + } + + case ADC_INSTANCE_1: + { + eAdcClkName = PCC_CLK_ADC1; + break; + } + + default: + break; + } + u32ClockDiv = 1U << pInitCfg->eClockDivider; + + u32AdcClk = PCC_GetPccFunctionClock(eAdcClkName); + + /* The start up count shall be around 5us */ + u32StartupCnt = u32AdcClk / u32ClockDiv / 1000000U * 5U + 1U; + if (u32StartupCnt < 2U) + { + u32StartupCnt = 2U; + } + else if (u32StartupCnt > 255U) + { + u32StartupCnt = 255U; + } + else + {} + + ADC_HWA_Reset(pAdc); + + u32Cfg1 = ADC_CFG1_OVRMOD(pInitCfg->eOverrunMode) | + ADC_CFG1_SEQGP_EN(pInitCfg->bSequenceGroupModeEnable) | + ADC_CFG1_SEQ_LEN(0) | + ADC_CFG1_SEQ_MOD(pInitCfg->eSequenceMode) | + ADC_CFG1_AUTO_DIS(pInitCfg->bAutoDis) | + ADC_CFG1_WAIT(pInitCfg->bWaitEnable) | + ADC_CFG1_TRIGSRC(eTriggerSrc) | + ADC_CFG1_TRIGMODE(eTriggerMode) | + ADC_CFG1_ALIGN(pInitCfg->eAlign) | + ADC_CFG1_RES(pInitCfg->eResolution) | + ADC_CFG1_DMAEN(false); + ADC_HWA_SetConfig1(pAdc, u32Cfg1); + + u32Cfg2 = ADC_CFG2_FWMARK(ADC_DEFAULT_WATER_MARK) | + ADC_CFG2_TRG_PRI(pInitCfg->eTrgLatchUnitPri) | + ADC_CFG2_TRG_CLR(1U) | + ADC_CFG2_AVG_EN(pInitCfg->bHwAvgEnable) | + ADC_CFG2_AVG_LEN(pInitCfg->eHwAverage) | + ADC_CFG2_REF_EXT(pInitCfg->eVoltageRef) | + ADC_CFG2_STCNT(u32StartupCnt); + ADC_HWA_SetConfig2(pAdc, u32Cfg2); + + u32Cal = ADC_CAL_CAL_EN(pInitCfg->bCalEnable) | + ADC_CAL_OFFSET(pInitCfg->s32CalOffset) | + ADC_CAL_GAIN(pInitCfg->s32CalGain); + + ADC_HWA_SetCal(pAdc, u32Cal); + + ADC_HWA_SetClockGatingEnableFlag(pAdc, true); + while ((ADC_HWA_GetClockGatingAck(pAdc) != true) && (u32TimeOut != 0)) + { + u32TimeOut--; + } + if (ADC_HWA_GetClockGatingAck(pAdc) == true) + { + ADC_HWA_SetClockDivider(pAdc, pInitCfg->eClockDivider); + } + u32TimeOut = 15000000U; + ADC_HWA_SetClockGatingEnableFlag(pAdc, false); + while ((ADC_HWA_GetClockGatingAck(pAdc) != false) && (u32TimeOut != 0)) + { + u32TimeOut--; + } + + uint8_t u8SmprIndex; + for (u8SmprIndex = 0U; u8SmprIndex < ADC_SAMPLE_TIME_OPTION_CNT; u8SmprIndex++) + { + ADC_HWA_SetSampleTime(pAdc, u8SmprIndex, pInitCfg->aSampleTimes[u8SmprIndex] - 2U); + } +} + +void ADC_DeInit(const ADC_InstanceType eInstance) +{ + DEV_ASSERT(eInstance < ADC_INSTANCE_COUNT); + + ADC_Type *const pAdc = s_apAdcBase[eInstance]; + uint32_t u32Cfg1; + uint32_t u32Cfg2; + + ADC_HWA_Reset(pAdc); + + ADC_HWA_SetInterruptEnable(pAdc, 0U); + + u32Cfg1 = ADC_CFG1_OVRMOD(ADC_OVERRUN_MODE_PRESERVE) | + ADC_CFG1_SEQGP_EN(false) | + ADC_CFG1_SEQ_LEN(0U) | + ADC_CFG1_SEQ_MOD(ADC_SEQMODE_SINGLE) | + ADC_CFG1_AUTO_DIS(false) | + ADC_CFG1_WAIT(false) | + ADC_CFG1_TRIGSRC(ADC_TRIGSRC_PTIMER) | + ADC_CFG1_TRIGMODE(ADC_TRIGMODE_SW) | + ADC_CFG1_ALIGN(ADC_ALIGN_RIGHT) | + ADC_CFG1_RES(ADC_RESOLUTION_12_BIT) | + ADC_CFG1_DMAEN(false); + ADC_HWA_SetConfig1(pAdc, u32Cfg1); + + u32Cfg2 = ADC_CFG2_FWMARK(ADC_DEFAULT_WATER_MARK) | + ADC_CFG2_TRG_PRI(TRG_LATCH_UNIT_PRI_ROUND_ROBIN) | + ADC_CFG2_TRG_CLR(1U) | + ADC_CFG2_AVG_EN(false) | + ADC_CFG2_AVG_LEN(ADC_AVERAGE_4) | + ADC_CFG2_REF_EXT(ADC_REF_INTERNAL) | + ADC_CFG2_STCNT(ADC_DEFAULT_STARTUP_COUNTER); + ADC_HWA_SetConfig2(pAdc, u32Cfg2); + + ADC_HWA_SetSampleTime(pAdc, 0U, ADC_DEFAULT_SAMPLE_TIME_OPTION_0 - 2U); + ADC_HWA_SetSampleTime(pAdc, 1U, ADC_DEFAULT_SAMPLE_TIME_OPTION_1 - 2U); + ADC_HWA_SetSampleTime(pAdc, 2U, ADC_DEFAULT_SAMPLE_TIME_OPTION_2 - 2U); + ADC_HWA_SetSampleTime(pAdc, 3U, ADC_DEFAULT_SAMPLE_TIME_OPTION_3 - 2U); + + ADC_HWA_SetHwCompareEnableFlag(pAdc, false); + ADC_HWA_SetHwCompareChannel(pAdc, ADC_CMP_CHANNEL_ALL, 0U); + + ADC_HWA_SetHwCompareThreshold(pAdc, ADC_DEFAULT_COMPARE_LOW_THRESHOLD, ADC_DEFAULT_COMPARE_HIGH_THRESHOLD); + + uint8_t u8ChnIndex; + for (u8ChnIndex = 0U; u8ChnIndex < ADC_SC_COUNT; u8ChnIndex++) + { + ADC_HWA_SetChannelSampleTimeIndex(pAdc, u8ChnIndex, 0U); + ADC_HWA_SetChannelInterruptEnable(pAdc, u8ChnIndex, false); + ADC_HWA_SetChannelInput(pAdc, u8ChnIndex, ADC_DEFAULT_SC_CHANNEL); + } + + /* TODO : CAL Rregister */ +} + +void ADC_InitChannel(const ADC_InstanceType eInstance, const ADC_ChannelCfgType aChannels[], + const uint8_t u8ChnCnt) +{ + DEV_ASSERT(eInstance < ADC_INSTANCE_COUNT); + DEV_ASSERT(u8ChnCnt < ADC_SC_COUNT); + DEV_ASSERT(aChannels != NULL); + + ADC_Type *const pAdc = s_apAdcBase[eInstance]; + + s_u8ChannelCnt[eInstance] = u8ChnCnt; + + uint8_t u8ChnIndex; + for (u8ChnIndex = 0U; u8ChnIndex < u8ChnCnt; u8ChnIndex++) + { + ADC_HWA_SetChannelDiff(pAdc, u8ChnIndex, aChannels[u8ChnIndex].bDiff); + ADC_HWA_SetChannelSampleTimeIndex(pAdc, u8ChnIndex, aChannels[u8ChnIndex].eSampleTimeOption); + ADC_HWA_SetChannelInterruptEnable(pAdc, u8ChnIndex, false); + ADC_HWA_SetChannelInput(pAdc, u8ChnIndex, aChannels[u8ChnIndex].eChannel); + } + + if (ADC_HWA_GetSeqGpEn(pAdc) != true && ADC_HWA_GetSequenceMode(pAdc) != ADC_SEQMODE_DISCONTINUOUS_1) + { + ADC_HWA_SetSequenceLength(pAdc, u8ChnCnt - 1U); + ADC_HWA_SetFIFOWaterMark(pAdc, u8ChnCnt - 1U); + } +} + +void ADC_InitSequenceGroup(const ADC_InstanceType eInstance, const ADC_SequenceGroupType aSeqGroup[], + const uint8_t u8SeqGroupCnt) +{ + DEV_ASSERT(eInstance < ADC_INSTANCE_COUNT); + DEV_ASSERT(u8SeqGroupCnt < ADC_SEQUENCE_GROUP_CNT); + DEV_ASSERT(aSeqGroup != NULL); + + ADC_Type *const pAdc = s_apAdcBase[eInstance]; + + s_u8SeqGroupCnt[eInstance] = u8SeqGroupCnt; + + uint8_t u8ChnIndex; + for (u8ChnIndex = 0U; u8ChnIndex < u8SeqGroupCnt; u8ChnIndex++) + { + ADC_HWA_SetSeqGroupStartEndPoint(pAdc, u8ChnIndex, aSeqGroup[u8ChnIndex].u8Start, aSeqGroup[u8ChnIndex].u8Start + aSeqGroup[u8ChnIndex].u8Len); + ADC_HWA_SetEndOfSequenceGroupInterruptEnable(pAdc, u8ChnIndex, false); + } +} + +void ADC_InitCompare(const ADC_InstanceType eInstance, const ADC_CompareType *const pCmpCfg) +{ + DEV_ASSERT(eInstance < ADC_INSTANCE_COUNT); + DEV_ASSERT(pCmpCfg != NULL); + + ADC_Type *const pAdc = s_apAdcBase[eInstance]; + + ADC_HWA_SetHwCompareChannel(pAdc, pCmpCfg->eCmpSingleChn, pCmpCfg->u8CmpChnSel); + ADC_HWA_SetHwCompareThreshold(pAdc, pCmpCfg->u16LowThres, pCmpCfg->u16HighThres); + ADC_HWA_SetHwCompareEnableFlag(pAdc, pCmpCfg->bCmpEnable); +} + +void ADC_InitInterrupt(const ADC_InstanceType eInstance, const ADC_InterruptType *const pInterruptCfg) +{ + DEV_ASSERT(eInstance < ADC_INSTANCE_COUNT); + DEV_ASSERT(pInterruptCfg != NULL); + DEV_ASSERT(s_u8ChannelCnt[eInstance] > 0U); + ADC_Type *const pAdc = s_apAdcBase[eInstance]; + uint32_t u32InterruptCfg; + uint8_t u8SeqGroupIndex; + + if (ADC_HWA_GetSeqGpEn(pAdc) == false) + { + s_apAdcResultBuffer[eInstance] = pInterruptCfg->pResultBuffer; + if (ADC_HWA_GetSequenceMode(pAdc) == ADC_SEQMODE_DISCONTINUOUS_1) + { + u32InterruptCfg = ADC_INT_ENABLE_TRGERR_IE(false) | + ADC_INT_ENABLE_FIFO_RDY_IE(false) | + ADC_INT_ENABLE_ACMP_IE(pInterruptCfg->bAnalogCmpIntEn) | + ADC_INT_ENABLE_OVRIE(false) | + ADC_INT_ENABLE_EOSEQIE(false) | + ADC_INT_ENABLE_EOCIE(false) | + ADC_INT_ENABLE_EOSMPIE(false) | + ADC_INT_ENABLE_ADRDYIE(false); + ADC_HWA_SetInterruptEnable(pAdc, u32InterruptCfg); + ADC_HWA_SetChannelInterruptEnable(pAdc, s_u8ChannelCnt[eInstance] - 1U, pInterruptCfg->bConversionCompleteIntEn); + } + else + { + u32InterruptCfg = ADC_INT_ENABLE_TRGERR_IE(false) | + ADC_INT_ENABLE_FIFO_RDY_IE(false) | + ADC_INT_ENABLE_ACMP_IE(pInterruptCfg->bAnalogCmpIntEn) | + ADC_INT_ENABLE_OVRIE(pInterruptCfg->bOverRunIntEn) | + ADC_INT_ENABLE_EOSEQIE(pInterruptCfg->bConversionCompleteIntEn) | + ADC_INT_ENABLE_EOCIE(false) | + ADC_INT_ENABLE_EOSMPIE(false) | + ADC_INT_ENABLE_ADRDYIE(false); + ADC_HWA_SetInterruptEnable(pAdc, u32InterruptCfg); + } + } + else + { + for (u8SeqGroupIndex = 0U; u8SeqGroupIndex < ADC_SEQUENCE_GROUP_CNT; u8SeqGroupIndex++) + { + s_apAdcSeqGroupResultBuffer[eInstance][u8SeqGroupIndex] = pInterruptCfg->pSequenceGroupResultBuffer[u8SeqGroupIndex]; + } + u32InterruptCfg = ADC_INT_ENABLE_TRGERR_IE(false) | + ADC_INT_ENABLE_FIFO_RDY_IE(false) | + ADC_INT_ENABLE_ACMP_IE(pInterruptCfg->bAnalogCmpIntEn) | + ADC_INT_ENABLE_OVRIE(false) | + ADC_INT_ENABLE_EOSEQIE(false) | + ADC_INT_ENABLE_EOCIE(false) | + ADC_INT_ENABLE_EOSMPIE(false) | + ADC_INT_ENABLE_ADRDYIE(false); + ADC_HWA_SetInterruptEnable(pAdc, u32InterruptCfg); + for (u8SeqGroupIndex = 0U; u8SeqGroupIndex < s_u8SeqGroupCnt[eInstance]; u8SeqGroupIndex++) + { + ADC_HWA_SetEndOfSequenceGroupInterruptEnable(pAdc, u8SeqGroupIndex, true); + } + } + + s_apAdcCoCoNotify[eInstance] = pInterruptCfg->pConvCompleteNotify; + s_apAdcOvrNotify[eInstance] = pInterruptCfg->pOverRunNotify; + s_apAdcCmpNotify[eInstance] = pInterruptCfg->pCompareNotify; + s_apEndOfSeqGroupNotify[eInstance] = pInterruptCfg->pEndOfSeqGroupNotify; +} + +void ADC_InitDmaChannel(const ADC_InstanceType eInstance, const ADC_DmaType *const pAdcDmaCfg) +{ + DEV_ASSERT(eInstance < ADC_INSTANCE_COUNT); + DEV_ASSERT(pAdcDmaCfg != NULL); + uint32_t u32ResultStart; + uint32_t u32ResultEnd; + + ADC_Type *const pAdc = s_apAdcBase[eInstance]; + + if (pAdcDmaCfg->bDmaEnable == true) + { + s_apAdcResultBuffer[eInstance] = pAdcDmaCfg->pResultBuffer; + s_apAdcCoCoNotify[eInstance] = pAdcDmaCfg->pConvCompleteNotify; + + DMA_ChannelCfgType tDmaCfg; + if (ADC_HWA_GetSeqGpEn(pAdc) == true) + { + u32ResultStart = ADC_HWA_GetSeqGroupStartPoint(pAdc, (uint8_t)pAdcDmaCfg->eSeqGroupIndex); + u32ResultEnd = ADC_HWA_GetSeqGroupEndPoint(pAdc, (uint8_t)pAdcDmaCfg->eSeqGroupIndex); + tDmaCfg.pSrcBuffer = &pAdc->RESULT[u32ResultStart]; + tDmaCfg.pDestBuffer = pAdcDmaCfg->pResultBuffer; + tDmaCfg.u32BlockSize = 4U; + tDmaCfg.u16BlockCount = u32ResultStart - u32ResultEnd; + tDmaCfg.eSrcIncMode = DMA_INCREMENT_DATA_SIZE; + } + else if (ADC_HWA_GetSequenceMode(pAdc) == ADC_SEQMODE_DISCONTINUOUS_1) + { + tDmaCfg.pSrcBuffer = &pAdc->RESULT[0U]; + tDmaCfg.pDestBuffer = pAdcDmaCfg->pResultBuffer; + tDmaCfg.u32BlockSize = 4U; + tDmaCfg.u16BlockCount = s_u8ChannelCnt[eInstance]; + tDmaCfg.eSrcIncMode = DMA_INCREMENT_DATA_SIZE; + } + else + { + tDmaCfg.pSrcBuffer = &pAdc->FIFO_DATA; + tDmaCfg.pDestBuffer = pAdcDmaCfg->pResultBuffer; + tDmaCfg.u32BlockSize = 4U * s_u8ChannelCnt[eInstance]; + tDmaCfg.u16BlockCount = 1U; + tDmaCfg.eSrcIncMode = DMA_INCREMENT_DISABLE; + } + tDmaCfg.eDestIncMode = DMA_INCREMENT_DATA_SIZE; + tDmaCfg.eSrcDataSize = DMA_TRANSFER_SIZE_4B; + tDmaCfg.eDestDataSize = DMA_TRANSFER_SIZE_4B; + tDmaCfg.u8ChannelPriority = pAdcDmaCfg->u8ChannelPriority; + tDmaCfg.bSrcBlockOffsetEn = false; + tDmaCfg.bDestBlockOffsetEn = false; + tDmaCfg.s32BlockOffset = 0; + tDmaCfg.bSrcAddrLoopbackEn = true; + tDmaCfg.bDestAddrLoopbackEn = true; + tDmaCfg.bAutoStop = false; + tDmaCfg.bSrcCircularBufferEn = false; + tDmaCfg.u32SrcCircBufferSize = DMA_CIRCULAR_BUFFER_SIZE_1B; + tDmaCfg.bDestCircularBufferEn = false; + tDmaCfg.u32DestCircBufferSize = DMA_CIRCULAR_BUFFER_SIZE_1B; + if (eInstance == ADC_INSTANCE_0) + { + tDmaCfg.eTriggerSrc = DMA_REQ_ADC0; + } + else if (eInstance == ADC_INSTANCE_1) + { + tDmaCfg.eTriggerSrc = DMA_REQ_ADC1; + } + else + {} + + DMA_InterruptCfgType dmaIntCfg = {0}; + dmaIntCfg.bTransferCompleteIntEn = true; + if (eInstance == ADC_INSTANCE_0) + { + dmaIntCfg.pTransferCompleteNotify = ADC0_DMAHandler; + } + else if (eInstance == ADC_INSTANCE_1) + { + dmaIntCfg.pTransferCompleteNotify = ADC1_DMAHandler; + } + else + {} + + dmaIntCfg.bTransferErrorIntEn = false; + dmaIntCfg.pTransferErrorNotify = NULL; + + ADC_HWA_SetDMAEnableFlag(pAdc, true); + + DMA_InitChannel(pAdcDmaCfg->eDmaInstance, pAdcDmaCfg->eDmaChannel, &tDmaCfg); + DMA_InitChannelInterrupt(pAdcDmaCfg->eDmaInstance, pAdcDmaCfg->eDmaChannel, &dmaIntCfg); + } + else + { + ADC_HWA_SetDMAEnableFlag(pAdc, false); + } +} + +ADC_StatusType ADC_Enable(const ADC_InstanceType eInstance) +{ + DEV_ASSERT(eInstance < ADC_INSTANCE_COUNT); + ADC_StatusType eRet = ADC_STATUS_SUCCESS; + uint32_t u32TimeOut = 15000000U; + ADC_Type *const pAdc = s_apAdcBase[eInstance]; + + ADC_HWA_Enable(pAdc); + while ((ADC_HWA_GetReady(pAdc) != true) && (u32TimeOut != 0U)) + { + u32TimeOut--; + } + if (u32TimeOut != 0U) + { + ADC_HWA_ClearReady(pAdc); + eRet = ADC_STATUS_SUCCESS; + } + else + { + eRet = ADC_STATUS_TIMEOUT; + } + return eRet; +} + +ADC_StatusType ADC_Disable(const ADC_InstanceType eInstance) +{ + DEV_ASSERT(eInstance < ADC_INSTANCE_COUNT); + ADC_StatusType eRet = ADC_STATUS_SUCCESS; + uint32_t u32TimeOut = 15000000U; + ADC_Type *const pAdc = s_apAdcBase[eInstance]; + + if (ADC_HWA_GetStart(pAdc) == true) + { + eRet = ADC_Stop(eInstance); + } + + if (eRet == ADC_STATUS_SUCCESS) + { + ADC_HWA_Disable(pAdc); + while ((ADC_HWA_GetEnable(pAdc) == true) && (u32TimeOut != 0U)) + { + u32TimeOut--; + } + if (u32TimeOut != 0U) + { + eRet = ADC_STATUS_SUCCESS; + } + else + { + eRet = ADC_STATUS_TIMEOUT; + } + } + return eRet; +} + +void ADC_Start(const ADC_InstanceType eInstance) +{ + DEV_ASSERT(eInstance < ADC_INSTANCE_COUNT); + ADC_Type *const pAdc = s_apAdcBase[eInstance]; + ADC_HWA_Start(pAdc); +} + +ADC_StatusType ADC_Stop(const ADC_InstanceType eInstance) +{ + DEV_ASSERT(eInstance < ADC_INSTANCE_COUNT); + ADC_StatusType eRet = ADC_STATUS_ERROR; + uint32_t u32TimeOut = 15000000U; + ADC_Type *const pAdc = s_apAdcBase[eInstance]; + + ADC_HWA_Stop(pAdc); + + while ((ADC_HWA_GetStop(pAdc) == true) && (u32TimeOut != 0U)) + { + u32TimeOut--; + } + if (u32TimeOut != 0U) + { + eRet = ADC_STATUS_SUCCESS; + } + else + { + eRet = ADC_STATUS_TIMEOUT; + } + return eRet; +} + +void ADC_Reset(const ADC_InstanceType eInstance) +{ + DEV_ASSERT(eInstance < ADC_INSTANCE_COUNT); + ADC_Type *const pAdc = s_apAdcBase[eInstance]; + ADC_HWA_Reset(pAdc); +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_aontimer.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_aontimer.c new file mode 100644 index 0000000..a36ecae --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_aontimer.c @@ -0,0 +1,187 @@ +/** + * @file fc7xxx_driver_aontimer.c + * @author Flagchip + * @brief FC7xxx aontimer driver type definition and API + * @version 0.1.0 + * @date 2024-01-10 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/******************************************************************************** +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2024-01-10 Flagchip0076 N/A First version for FC7240 +********************************************************************************/ +#include "fc7xxx_driver_aontimer.h" + +#include "fc7xxx_driver_csc.h" + +extern void AONTIMER_IRQHandler(void); + +/** @brief Aontimer common interrupt handle function */ +static void Aontimer_CommonProcessInterrupt(void); + +/** @brief Aontimer user defined interrupt function */ +static Aontimer_InterruptCallBackType s_pAontimerNotifyPtr = NULL; + +/** + * @brief Initialize aontimer instance + * + * @param pInitStruct Aontimer Initialize structure + */ +void AONTIMER_Init(const AONTIMER_InitType *const pInitStruct) +{ + DEV_ASSERT(pInitStruct != NULL); + /* Disable the Aontimer, and clear control register. */ + AONTIMER_HWA_ConfigModule((uint32_t)0U); + AONTIMER_HWA_ConfigModulePrescale((uint32_t)0U); + AONTIMER->CSR |= AONTIMER_CSR_DBGEN(pInitStruct->eDbgMode); + if (AONTIMER_PULSE_MODE == pInitStruct->eMode) + { + AONTIMER_HWA_SelectClkSrcOnPulseMode(pInitStruct->ePulseClkSrc); + AONTIMER_HWA_ConfigModulePolarity(pInitStruct->ePulsePol); + AONTIMER_HWA_EnablePulseMode(); + if (pInitStruct->bBypassEn) + { + AONTIMER_HWA_EnableBypassMode(); + } + else + { + AONTIMER_HWA_DisableBypassMode(); + } + AONTIMER_HWA_SetPrescale(pInitStruct->u8PulseFilterWidth); + } + else + { + AONTIMER_HWA_SetPrescale(pInitStruct->u8Prescaler); + } + AONTIMER_HWA_SetModuleRunOnDebug(); + AONTIMER_HWA_SelectModuleClkSrc(pInitStruct->eClkSrc); + AONTIMER_HWA_SetModuleCompareValue((uint32_t)pInitStruct->u16StartValue); +} + +/** + * @brief De-initialize aontimer instance + * + */ +void AONTIMER_Deinit(void) +{ + AONTIMER_HWA_ConfigModule((uint32_t)0U); + AONTIMER_HWA_ConfigModulePrescale((uint32_t)0U); + AONTIMER_HWA_SetModuleCompareValue((uint32_t)0xFFFFFFFFU); + s_pAontimerNotifyPtr = NULL; +} + +/** + * @brief Initialize aontimer interrupt functionality + * + * @param pIntStruct Aontimer interrupt structure + * @return Aontimer return type + * @note this function will disable timer + */ +AONTIMER_StatusType AONTIMER_InitInterrupt(const AONTIMER_IntType *const pIntStruct) +{ + AONTIMER_StatusType eRet = AONTIMER_STATUS_SUCCESS; + if (NULL == pIntStruct) + { + eRet = AONTIMER_STATUS_PARAM_INVALID; + } + else + { + AONTIMER_HWA_DisableTimer(); + if (pIntStruct->bIntEn) + { + AONTIMER_HWA_EnableModuleInterrupt(); + s_pAontimerNotifyPtr = pIntStruct->pIsrNotify; + } + else + { + AONTIMER_HWA_DisableModuleInterrupt(); + s_pAontimerNotifyPtr = NULL; + } + } + return eRet; +} + +/** + * @brief Enable AONTIMER interrupt + * @note this function will enable AONTIEMR timer. + */ +void AONTIMER_EnableInterrupt(void) +{ + AONTIMER_HWA_DisableTimer(); + AONTIMER_HWA_EnableModuleInterrupt(); + AONTIMER_HWA_EnableTimer(); +} + +/** + * @brief Disable AONTIMER interrupt + * @note this function will enable AONTIEMR timer. + * + */ +void AONTIMER_DisableInterrupt(void) +{ + AONTIMER_HWA_DisableTimer(); + AONTIMER_HWA_DisableModuleInterrupt(); + AONTIMER_HWA_EnableTimer(); +} + +/** + * @brief Start Aontimer + * + */ +void AONTIMER_StartTimer(void) +{ + AONTIMER_HWA_EnableTimer(); +} + +/** + * @brief Stop Aontimer + * + */ +void AONTIMER_StopTimer(void) +{ + AONTIMER_HWA_DisableTimer(); +} + +/** + * @brief Update value of aontimer counter + * + * @param u16StartValue input value, range : 0~65535 + */ +void AONTIMER_UpdateCounterValue(const uint16_t u16StartValue) +{ + if (0U == (AONTIMER->CSR & AONTIMER_CSR_TMS_MASK)) + { + AONTIMER_HWA_DisableTimer(); + AONTIMER_HWA_SetModuleCompareValue((uint32_t)u16StartValue); + AONTIMER_HWA_EnableTimer(); + } +} + +/** + * @brief Aontimer common interrupt handle function + * + */ +static void Aontimer_CommonProcessInterrupt(void) +{ + if (NULL != s_pAontimerNotifyPtr) + { + s_pAontimerNotifyPtr(); + } +} + +/** + * @brief Aontimer interrupt entry + * + */ +void AONTIMER_IRQHandler(void) +{ + Aontimer_CommonProcessInterrupt(); + AONTIMER_HWA_ClearInterruptFlag(); + AONTIMER_HWA_EnableTimer(); +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_cmp.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_cmp.c new file mode 100644 index 0000000..260ff16 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_cmp.c @@ -0,0 +1,324 @@ +/** + * @file fc7xxx_driver_cmp.c + * @author Flagchip0126 + * @brief FC7xxx CMP driver source code + * @version 0.1.0 + * @date 2024-01-15 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/******************************************************************************** +* Revision History: +* +* Version Date Author CR# Descriptions +* --------- ---------- ------------ ---------- ------------------------ +* 0.1.0 2024-01-15 Flagchip0126 N/A First version for FC7240 +**********************************************************************************/ + +#include "fc7xxx_driver_cmp.h" +#include "interrupt_manager.h" + +/********* Local Variables ************/ +static CMP_Type *const s_apCmpBase[CMP_INSTANCE_COUNT] = CMP_BASE_PTRS; +static CMP_CompleteIntCallback s_apCmpIntNotify[CMP_INSTANCE_COUNT] = {NULL}; + +/******* Local Function Prototype *********/ + +/** + * @brief set CMPn IRQHandler + * + * @param eInstance the CMP instance to use + */ +static void CMPn_IRQHandler(const CMP_InstanceType eInstance); + +void CMP0_IRQHandler(void); + +void CMP1_IRQHandler(void); + +static void CMPn_IRQHandler(const CMP_InstanceType eInstance) +{ + DEV_ASSERT(eInstance < CMP_INSTANCE_COUNT); + + /*callback function*/ + if (s_apCmpIntNotify[eInstance] != NULL) + { + s_apCmpIntNotify[eInstance](); + } + else + { + /*Noting to do*/ + } + + /*clear interrupter status regs*/ + CMP_ClearIntFlag(eInstance); +} + +void CMP0_IRQHandler(void) +{ + CMPn_IRQHandler(CMP_INSTANCE_0); +} + +void CMP1_IRQHandler(void) +{ + CMPn_IRQHandler(CMP_INSTANCE_1); +} + +/********* Local Functions ************/ +void CMP_Enable(const CMP_InstanceType eInstance) +{ + DEV_ASSERT(eInstance < CMP_INSTANCE_COUNT); + CMP_Type *const pCmp = s_apCmpBase[eInstance]; + + CMP_HWA_Enable(pCmp); +} + +void CMP_Disable(const CMP_InstanceType eInstance) +{ + DEV_ASSERT(eInstance < CMP_INSTANCE_COUNT); + CMP_Type *const pCmp = s_apCmpBase[eInstance]; + + CMP_HWA_Disable(pCmp); +} + +void CMP_CSEnable(const CMP_InstanceType eInstance) +{ + DEV_ASSERT(eInstance < CMP_INSTANCE_COUNT); + CMP_Type *const pCmp = s_apCmpBase[eInstance]; + + CMP_HWA_CSEnable(pCmp); +} + +void CMP_CSDisable(const CMP_InstanceType eInstance) +{ + DEV_ASSERT(eInstance < CMP_INSTANCE_COUNT); + CMP_Type *const pCmp = s_apCmpBase[eInstance]; + + CMP_HWA_CSDisable(pCmp); +} + +bool CMP_GetCmpOut(const CMP_InstanceType eInstance) +{ + bool CmpOut; + + DEV_ASSERT(eInstance < CMP_INSTANCE_COUNT); + CMP_Type *const pCmp = s_apCmpBase[eInstance]; + + CmpOut = CMP_HWA_GetCmpOut(pCmp); + return CmpOut; +} + +void CMP_SetDacData(const CMP_InstanceType eInstance, uint8_t u8Data) +{ + DEV_ASSERT(eInstance < CMP_INSTANCE_COUNT); + CMP_Type *const pCmp = s_apCmpBase[eInstance]; + + CMP_HWA_SetDacData(pCmp, u8Data); +} + +CMP_OutStatus CMP_GetOutFlagStatus(const CMP_InstanceType eInstance) +{ + DEV_ASSERT(eInstance < CMP_INSTANCE_COUNT); + bool bCFF_Status = false; + bool bCFR_Status = false; + CMP_Type *const pCmp = s_apCmpBase[eInstance]; + CMP_OutStatus eRetVal = CMP_OUT_NONE; + + bCFF_Status = CMP_HWA_GetIntFlag_Falling(pCmp); + bCFR_Status = CMP_HWA_GetIntFlag_Rising(pCmp); + + if ((bCFF_Status == true) && (bCFR_Status == false)) + { + eRetVal = CMP_OUT_FALLING_EDGE; + } + else if ((bCFF_Status == false) && (bCFR_Status == true)) + { + eRetVal = CMP_OUT_RISING_EDGE; + } + else + { + eRetVal = CMP_OUT_NONE; + } + + return eRetVal; +} + +bool CMP_GetChannelScanFlagStatus(const CMP_InstanceType eInstance) +{ + DEV_ASSERT(eInstance < CMP_INSTANCE_COUNT); + bool bCSF_Status = false; + CMP_Type *const pCmp = s_apCmpBase[eInstance]; + + bCSF_Status = CMP_HWA_GetIntFlag_ChannelScan(pCmp); + + return bCSF_Status; +} + +void CMP_ClearIntFlag(const CMP_InstanceType eInstance) +{ + DEV_ASSERT(eInstance < CMP_INSTANCE_COUNT); + CMP_Type *const pCmp = s_apCmpBase[eInstance]; + + CMP_HWA_ClearIntFlag_Rising(pCmp); + CMP_HWA_ClearIntFlag_Falling(pCmp); + CMP_HWA_ClearIntFlag_ChannelScan(pCmp); +} + +void CMP_Init(const CMP_InstanceType eInstance, const CMP_InitType *const pInitCfg) +{ + DEV_ASSERT(eInstance < CMP_INSTANCE_COUNT); + DEV_ASSERT(pInitCfg != NULL); + CMP_Type *const pCmp = s_apCmpBase[eInstance]; + + /* disable CMP module */ + CMP_HWA_Disable(pCmp); + + /* determine comparator function mode */ + CMP_HWA_SetComparatorMod(pCmp, (pInitCfg->tComparatorConfig).eModSel, ((pInitCfg->tComparatorConfig).u8FilterPeriod), ((pInitCfg->tComparatorConfig).eFilterCnt)); + + /* configure CMP module */ + /* CCR0 register */ + CMP_HWA_SetEnStopMod(pCmp, (pInitCfg->tComparatorConfig).bStopModEn); + CMP_HWA_SetDacEnableSrc(pCmp, (pInitCfg->tDacConfig).eDacEnsrc); + + /* CCR1 register */ + CMP_HWA_SetCmpOutInvert(pCmp, (pInitCfg->tComparatorConfig).eInvert); + CMP_HWA_SetCmpOutSel(pCmp, (pInitCfg->tComparatorConfig).eOutSelect); + CMP_HWA_SetEnCmpOutPack(pCmp, (pInitCfg->tComparatorConfig).bOutToPackagePinEn); + CMP_HWA_SetCmpOutWinLevel(pCmp, (pInitCfg->tComparatorConfig).eOutWinLevel); + CMP_HWA_SetCmpOutWin(pCmp, (pInitCfg->tComparatorConfig).eOutWin); + CMP_HWA_SetEnWinSampleInvert(pCmp, (pInitCfg->tComparatorConfig).bWinSampleInvertEn); + CMP_HWA_SetEnEventCloseWin(pCmp, (pInitCfg->tComparatorConfig).bEventCloseWinEn); + CMP_HWA_SetEventCloseWin(pCmp, (pInitCfg->tComparatorConfig).eEventSelect); + + /* CCR2 register */ + CMP_HWA_SetSpeedMod(pCmp, (pInitCfg->tComparatorConfig).eSpeedMod); + CMP_HWA_SetHystCtrl(pCmp, (pInitCfg->tComparatorConfig).eHystCrtl); + CMP_HWA_SetPSelMux(pCmp, (pInitCfg->tMuxConfig).ePSelMux); + CMP_HWA_SetNSelMux(pCmp, (pInitCfg->tMuxConfig).eNSelMux); + CMP_HWA_SetINPSel(pCmp, (pInitCfg->tMuxConfig).eINPSel); + CMP_HWA_SetINNSel(pCmp, (pInitCfg->tMuxConfig).eINNSel); + + /* CCR3 register */ + CMP_HWA_SetAnalogConfTransByp(pCmp, (pInitCfg->tComparatorConfig).bAnalogConfTransByp); + CMP_HWA_SetAnalogConfTransBypCnt(pCmp, (pInitCfg->tComparatorConfig).u16AnalogConfTransBypCnt); + + /* DCR register */ + CMP_HWA_SetEnDac(pCmp, (pInitCfg->tDacConfig).bDacEn); + CMP_HWA_SetVinRefSel(pCmp, (pInitCfg->tDacConfig).eVinRefSel); + CMP_HWA_SetDacData(pCmp, (pInitCfg->tDacConfig).u8DacData); + + if ((pInitCfg->tComparatorConfig).eModSel == CMP_MOD_CHANNEL_SCAN) + { + /* CSCR0 register */ + CMP_HWA_SetCSInitModulus(pCmp, (pInitCfg->tChannelScanConfig).u8ChannelScanInitModulus); + CMP_HWA_SetCSNumOfSampleClocks(pCmp, (pInitCfg->tChannelScanConfig).u8ChannelScanNumOfSampleClocks); + + /* CSCR1 register */ + CMP_HWA_SetCSFixedChannel(pCmp, (pInitCfg->tMuxConfig).eChannelScanFixedChannel); + CMP_HWA_SetCSFixedPort(pCmp, (pInitCfg->tMuxConfig).eChannelScanFixedPort); + + /* CSCSR register */ + CMP_HWA_SetCSComparisonResultsAutoClearEn(pCmp, (pInitCfg->tChannelScanConfig).bComparisonResultAutoClear); + } +} + +void CMP_InitInterrupt(const CMP_InstanceType eInstance, const CMP_InterruptType *const pInterruptCfg) +{ + DEV_ASSERT(eInstance < CMP_INSTANCE_COUNT); + DEV_ASSERT(pInterruptCfg != NULL); + CMP_Type *const pCmp = s_apCmpBase[eInstance]; + + /*disable DMA*/ + CMP_HWA_DmaDisable(pCmp); + + /*clear interrupter flag*/ + CMP_ClearIntFlag(eInstance); + + /*configure interrupter */ + CMP_SetIntEn(eInstance, pInterruptCfg); + + s_apCmpIntNotify[eInstance] = pInterruptCfg->pInterrupterNotify; +} + +void CMP_InitInterrupt_Dma(const CMP_InstanceType eInstance, const CMP_DmaType *const pInterruptDmaCfg) +{ + DEV_ASSERT(eInstance < CMP_INSTANCE_COUNT); + DEV_ASSERT(pInterruptDmaCfg != NULL); + + CMP_InterruptType pInterruptCfg; + + pInterruptCfg.bRisingIntEn = pInterruptDmaCfg->bRisingDmaEn; + pInterruptCfg.bFallingIntEn = pInterruptDmaCfg->bFallingDmaEn; + pInterruptCfg.bChannelScanFlagIntEn = false; + pInterruptCfg.pInterrupterNotify = NULL; + + /* Set rising/falling edge interrupt to trigger Dma*/ + CMP_SetIntEn(eInstance, &pInterruptCfg); + + if ((pInterruptDmaCfg->bRisingDmaEn == true) || (pInterruptDmaCfg->bFallingDmaEn == true)) + { + CMP_DmaEnable(eInstance); + } + else + { + CMP_DmaDisable(eInstance); + } +} + +void CMP_SetIntEn(const CMP_InstanceType eInstance, const CMP_InterruptType *const pInterruptCfg) +{ + CMP_Type *const pCmp = s_apCmpBase[eInstance]; + + /*set rising edges interrupter enable*/ + CMP_HWA_SetIntEn_Rising(pCmp, pInterruptCfg->bRisingIntEn); + /*set falling edges interrupter enable*/ + CMP_HWA_SetIntEn_Falling(pCmp, pInterruptCfg->bFallingIntEn); + /*set channel scan flag interrupter enable*/ + CMP_HWA_SetIntEn_ChannelScan(pCmp, pInterruptCfg->bChannelScanFlagIntEn); +} + +void CMP_DmaEnable(const CMP_InstanceType eInstance) +{ + CMP_Type *const pCmp = s_apCmpBase[eInstance]; + CMP_HWA_DmaEnable(pCmp); +} + +void CMP_DmaDisable(const CMP_InstanceType eInstance) +{ + CMP_Type *const pCmp = s_apCmpBase[eInstance]; + CMP_HWA_DmaDisable(pCmp); +} + +void CMP_SetCSChannls(const CMP_InstanceType eInstance, const CMP_ChannelScanChannelCfgType s_tChnCfg[], const uint8_t u8ChnCnt) +{ + DEV_ASSERT(eInstance < CMP_INSTANCE_COUNT); + uint8_t u8ChnIndex; + + CMP_Type *const pCmp = s_apCmpBase[eInstance]; + for (u8ChnIndex = 0U; u8ChnIndex < u8ChnCnt; u8ChnIndex++) + { + CMP_HWA_SetCSChannelEn(pCmp, s_tChnCfg[u8ChnIndex].eChannel, true); + CMP_HWA_SetCSChannelPresetstate(pCmp, s_tChnCfg[u8ChnIndex].eChannel, s_tChnCfg[u8ChnIndex].bPreSetState); + } +} + +void CMP_GetCSChannlsOut(const CMP_InstanceType eInstance, CMP_ChannelScanChannelCfgType s_tChnCfg[], const uint8_t u8ChnCnt) +{ + DEV_ASSERT(eInstance < CMP_INSTANCE_COUNT); + uint8_t u8ChnIndex; + + CMP_Type *const pCmp = s_apCmpBase[eInstance]; + for (u8ChnIndex = 0U; u8ChnIndex < u8ChnCnt; u8ChnIndex++) + { + s_tChnCfg[u8ChnIndex].bCurState = CMP_HWA_GetCSChannelsOut(pCmp, s_tChnCfg[u8ChnIndex].eChannel); + } +} + +bool CMP_GetCmpCSActive(const CMP_InstanceType eInstance) +{ + DEV_ASSERT(eInstance < CMP_INSTANCE_COUNT); + CMP_Type *const pCmp = s_apCmpBase[eInstance]; + + return CMP_HWA_GetCSActive(pCmp); +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_cmu.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_cmu.c new file mode 100644 index 0000000..594849e --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_cmu.c @@ -0,0 +1,386 @@ +/** + * @file fc7xxx_driver_cmu.c + * @author Flagchip085 + * @brief FC7xxx CMU driver type definition and API + * @version 0.1.0 + * @date 2024-01-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/******************************************************************************** +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240 +********************************************************************************/ +#include "fc7xxx_driver_cmu.h" +#include "fc7xxx_driver_scg.h" +#include "fc7xxx_driver_csc.h" +#include "HwA_cmu.h" + +#define CMU_MULTIPLY_FACTOR 100U +#define CMU_PERCENT_FACTOR 100U +#define CMU_DIVID_FACTOR_1K 1000U + +/** @brief CMU Reference clock div type. */ + +/** + * @brief Defines the CMU_ClkFrequenceType + * + * This structure is used to configure the CMU frequence include Reference clock and monitor clock + * + */ +typedef struct +{ + uint32_t u32RefClk; /*!< The Reference clock frequence */ + uint32_t u32MonitorClk; /*!< The target monitored clock frequence. */ +} CMU_ClkFrequenceType; + +typedef struct +{ + uint32_t u32RefWindow; /*!< CMU_REF_WINDOW (Reference Window). */ + uint32_t u32IdealMonitorCnts; /*!< Ideal monitor counter value, used to calculate the MIN,Max threshold. */ + uint32_t u32MinThreshold; /*!< CMU_MIN (Minimum threshold). */ + uint32_t u32MaxThreshold; /*!< CMU_MAX (Maximum threshold). */ + uint32_t u32PerWindow; /*!< CMU_PERIOD (Period monitor mode configuration). */ +} CMU_RegMapType; + + +static CMU_Type *const s_apCmuBase[CMU_INSTANCE_COUNT] = CMU_BASE_PTRS; +static CMU_ISRCallbackType s_apCmuISRCallback[CMU_INSTANCE_COUNT] = {NULL}; + +void CMU0_IRQHandler(void); +void CMU1_IRQHandler(void); +void CMU2_IRQHandler(void); +void CMU3_IRQHandler(void); +void CMU4_IRQHandler(void); + +/* Check Reference clock and monitor clock status.*/ +static CMU_StatusType CMU_ClkStatusCheck(CMU_InstanceType eInstance, CMU_ClkFrequenceType *ptCmuFreq) +{ + CSC_RetStatusType bCscClkStatus; + CMU_StatusType bCmuClkStatus = CMU_VALID; + + if (eInstance == CMU_INSTANCE_0) + { + /* Instance ---- Reference CLK ---- Monitored CLK.*/ + /* CMU0 ---- SIRC ---- RTC_CLK.*/ + ptCmuFreq->u32RefClk = SCG_GetScgClockFreq(SCG_SIRC_CLK); + + bCscClkStatus = CSC0_GetCSC0ClockFreq(CSC0_RTC_CLK, &(ptCmuFreq->u32MonitorClk)); + if (bCscClkStatus != CSC_E_OK) + { + bCmuClkStatus = CMU_CLK_ERROR; + } + } + else if (eInstance == CMU_INSTANCE_1) + { + /* Instance ---- Reference CLK ---- Monitored CLK.*/ + /* CMU1 ---- SIRC ---- FOSC.*/ + ptCmuFreq->u32RefClk = SCG_GetScgClockFreq(SCG_SIRC_CLK); + ptCmuFreq->u32MonitorClk = SCG_GetScgClockFreq(SCG_FOSC_CLK); + } + else if (eInstance == CMU_INSTANCE_2) + { + /* Instance ---- Reference CLK ---- Monitored CLK.*/ + /* CMU2 ---- SIRC ---- FIRC.*/ + ptCmuFreq->u32RefClk = SCG_GetScgClockFreq(SCG_SIRC_CLK); + ptCmuFreq->u32MonitorClk = SCG_GetScgClockFreq(SCG_FIRC_CLK); + } + else if (eInstance == CMU_INSTANCE_3) + { + /* Instance ---- Reference CLK ---- Monitored CLK.*/ + /* CMU3 ---- FIRC ---- SIRC.*/ + ptCmuFreq->u32RefClk = SCG_GetScgClockFreq(SCG_FIRC_CLK); + ptCmuFreq->u32MonitorClk = SCG_GetScgClockFreq(SCG_SIRC_CLK); + } + else if (eInstance == CMU_INSTANCE_4) + { + /* Instance ---- Reference CLK ---- Monitored CLK.*/ + /* CMU4 ---- SIRC ---- SLOW CLOCK.*/ + ptCmuFreq->u32MonitorClk = SCG_GetScgClockFreq(SCG_SLOW_CLK); + ptCmuFreq->u32RefClk = SCG_GetScgClockFreq(SCG_CMU4REF_CLK); + } + else + { + /* Never come here */ + bCmuClkStatus = CMU_CLK_ERROR; + } + + if(bCmuClkStatus == CMU_VALID) + { + if ((ptCmuFreq->u32MonitorClk == 0U) || (ptCmuFreq->u32RefClk == 0U)) + { + bCmuClkStatus = CMU_CLK_ERROR; + } + } + + return bCmuClkStatus; +} + +CMU_StatusType CMU_Init(CMU_InstanceType eInstance, const CMU_CfgType *pInitCfg) +{ + CMU_StatusType eStatus; + CMU_Type *pCmu; + CMU_RefClockDivType eDiv; + CMU_ClkFrequenceType tCmuFreq; + uint32_t u32RefWindow, u32MaxRefWindow, u32MinRefWindow; + uint32_t u32MonitorCnts, u32MinMonitorCnts, u32MaxMonitorCnts; + uint32_t u32RefClk, u32MonitorClk; + uint32_t u32Temp; + + DEV_ASSERT((uint8_t)eInstance < CMU_INSTANCE_COUNT); + DEV_ASSERT(pInitCfg != NULL); + pCmu = s_apCmuBase[(uint8_t)eInstance]; + eDiv = pInitCfg->eDiv; + + /* Check Reference clock and monitor clock status.*/ + eStatus = CMU_ClkStatusCheck(eInstance, &tCmuFreq); + + if (eStatus == CMU_VALID) + { + /* divide the clock value by 1K_factor */ + u32RefClk = (tCmuFreq.u32RefClk >> eDiv) / CMU_DIVID_FACTOR_1K; + u32MonitorClk = tCmuFreq.u32MonitorClk / CMU_DIVID_FACTOR_1K; + + if (u32RefClk / u32MonitorClk <= 0x100U) + { + u32MaxRefWindow = (0xffffffU - 3U) / u32MonitorClk * u32RefClk / 105U * CMU_PERCENT_FACTOR - 2U; + + if (u32MaxRefWindow > 0xffffffU) + { + u32MaxRefWindow = 0xffffffU; + } + } + else + { + u32MaxRefWindow = 0xffffffU; + } + + u32MinRefWindow = 6U + 5U * u32RefClk / u32MonitorClk; + u32RefWindow = 100U * u32MinRefWindow; + + if (u32RefWindow > u32MaxRefWindow) + { + u32RefWindow = u32MaxRefWindow; + } + + u32MonitorCnts = u32MonitorClk * (u32RefWindow + 2U) / u32RefClk; + u32MinMonitorCnts = u32MonitorCnts * 95U / CMU_PERCENT_FACTOR - 3U; + u32MaxMonitorCnts = u32MonitorCnts * 105U / CMU_PERCENT_FACTOR + 3U; + + CMU_HWA_SetRefWindow(pCmu, u32RefWindow); + CMU_HWA_SetMinCnts(pCmu, u32MinMonitorCnts); + CMU_HWA_SetMaxCnts(pCmu, u32MaxMonitorCnts); + + /* Program program PERIOD[EN] and PERIOD[WINDOW]. */ + CMU_HWA_SetPeriodEnable(pCmu, false); + if (pInitCfg->bPerMonitorEnable == true) + { + uint8_t u8MaxPeriod = (uint8_t)(u32RefClk / u32RefWindow); + + if ((u8MaxPeriod >> (uint8_t)CMU_PERIOD_WINDOW_WIDTH) != 0U) + { + u8MaxPeriod = (1U << (uint8_t)CMU_PERIOD_WINDOW_WIDTH) - 1U; + } + + if (u8MaxPeriod != 0U) + { + if (pInitCfg->u8PerMonitorWindow <= u8MaxPeriod) + { + CMU_HWA_SetPeriodWindow(pCmu, (uint32_t)(pInitCfg->u8PerMonitorWindow)); + } + else + { + CMU_HWA_SetPeriodWindow(pCmu, (uint32_t)(u8MaxPeriod)); + } + CMU_HWA_SetPeriodEnable(pCmu, pInitCfg->bPerMonitorEnable); + } + } + + /* Program DIV,IRQ_EN,LP_EN,STOP_EN,ENABLE */ + u32Temp = CMU_HWA_GetCTRL(pCmu); + u32Temp &= ~(uint32_t)(CMU_CTRL_REF_DIV_MASK | CMU_CTRL_IRQ_EN_MASK | \ + CMU_CTRL_LP_EN_MASK | CMU_CTRL_STOP_EN_MASK | CMU_CTRL_ENABLE_MASK); + u32Temp |= (uint32_t)(CMU_CTRL_REF_DIV(eDiv) | CMU_CTRL_IRQ_EN(pInitCfg->bIntEnable) | \ + CMU_CTRL_LP_EN(pInitCfg->bLpen) | CMU_CTRL_STOP_EN(pInitCfg->bSten) | \ + CMU_CTRL_ENABLE(pInitCfg->bEnable)); + CMU_HWA_SETCTRL(pCmu, u32Temp); + + s_apCmuISRCallback[(uint8_t)eInstance] = pInitCfg->pIsrCallback; + } + else + { + /* clock status invalid, change, do nothing */ + } + + return eStatus; +} + +void CMU_Enable(CMU_InstanceType eInstance) +{ + DEV_ASSERT((uint8_t)eInstance < CMU_INSTANCE_COUNT); + CMU_HWA_Enable(s_apCmuBase[(uint8_t)eInstance]); +} + +void CMU_Disable(CMU_InstanceType eInstance) +{ + CMU_Type *pCmu; + + DEV_ASSERT((uint8_t)eInstance < CMU_INSTANCE_COUNT); + pCmu = s_apCmuBase[(uint8_t)eInstance]; + + CMU_HWA_Disable(pCmu); + CMU_HWA_ClearST(pCmu); +} + +void CMU_EnableInterrupt(CMU_InstanceType eInstance) +{ + DEV_ASSERT((uint8_t)eInstance < CMU_INSTANCE_COUNT); + CMU_HWA_IrqEnable(s_apCmuBase[(uint8_t)eInstance],true); +} + +void CMU_DisableInterrupt(CMU_InstanceType eInstance) +{ + DEV_ASSERT((uint8_t)eInstance < CMU_INSTANCE_COUNT); + CMU_HWA_IrqEnable(s_apCmuBase[(uint8_t)eInstance],false); +} + +CMU_InterruptType CMU_GetInterruptType(CMU_InstanceType eInstance) +{ + uint32_t u32Temp; + CMU_InterruptType eStatus; + + DEV_ASSERT((uint8_t)eInstance < CMU_INSTANCE_COUNT); + + u32Temp = CMU_HWA_GetST(s_apCmuBase[(uint8_t)eInstance]); + if ((u32Temp & CMU_ST_LOC_MASK) != 0U) + { + eStatus = CMU_INTERRUPT_LOC; + } + else if ((u32Temp & CMU_ST_MIS_MASK) != 0U) + { + eStatus = CMU_INTERRUPT_MIS; + } + else + { + eStatus = CMU_INTERRUPT_NONE; + } + + return eStatus; +} + +CMU_StatusType CMU_SetCmu4RefSrc(CMU_Cmu4ClkSrcType eSrc) +{ + SCG_StatusType eStatus; + + SCG_HWA_SetCmu4Clk(0U); + + if (CMU_CMU4_REF_CLK_FOSC == eSrc) + { + eStatus = SCG_SetCmu4Clk(SCG_CMU4CLK_SRC_FOSC); + } + else if (CMU_CMU4_REF_CLK_SIRC == eSrc) + { + eStatus = SCG_SetCmu4Clk(SCG_CMU4CLK_SRC_SIRC); + } + else + { + eStatus = SCG_STATUS_PARAM_ERROR; + } + + return (eStatus == SCG_STATUS_SUCCESS) ? CMU_VALID : CMU_CLK_ERROR; +} + +uint32_t CMU_GetCount(CMU_InstanceType eInstance) +{ + DEV_ASSERT((uint8_t)eInstance < CMU_INSTANCE_COUNT); + + return CMU_HWA_GetCount(s_apCmuBase[(uint8_t)eInstance]); +} + +uint32_t CMU_GetMinCount(CMU_InstanceType eInstance) +{ + DEV_ASSERT((uint8_t)eInstance < CMU_INSTANCE_COUNT); + + return CMU_HWA_GetMinCnts(s_apCmuBase[(uint8_t)eInstance]); +} + +uint32_t CMU_GetMaxCount(CMU_InstanceType eInstance) +{ + DEV_ASSERT((uint8_t)eInstance < CMU_INSTANCE_COUNT); + + return CMU_HWA_GetMaxCnts(s_apCmuBase[(uint8_t)eInstance]); +} + +void CMU_LowPowerModeEnable(CMU_InstanceType eInstance, CMU_LowpowerModeType eMode, bool bModeEnable, bool bRestartEnable) +{ + CMU_Type *pCmu; + + DEV_ASSERT((uint8_t)eInstance < CMU_INSTANCE_COUNT); + pCmu = s_apCmuBase[(uint8_t)eInstance]; + + if (eMode == CMU_STANDBY_MODE) + { + CMU_HWA_StopModeEnable(pCmu, bModeEnable); + CMU_HWA_StanbyModeEnable(pCmu, bModeEnable); + } + else if (eMode == CMU_STOP_MODE) + { + CMU_HWA_StopModeEnable(pCmu, bModeEnable); + } + else + { + + } + + CMU_HWA_LPRestartEnable(pCmu, bRestartEnable); +} + + +/***************CMU IRQ Functions*****************/ + +static void CMU_IRQHandler(CMU_InstanceType eInstance) +{ + CMU_Type *pCmu; + CMU_InterruptType eStatus; + + DEV_ASSERT((uint8_t)eInstance < CMU_INSTANCE_COUNT); + pCmu = s_apCmuBase[(uint8_t)eInstance]; + + eStatus = CMU_GetInterruptType(eInstance); + + if (s_apCmuISRCallback[(uint8_t)eInstance] != NULL) + { + s_apCmuISRCallback[(uint8_t)eInstance](eInstance, eStatus); + } + + CMU_HWA_ClearST(pCmu); +} + +void CMU0_IRQHandler(void) +{ + CMU_IRQHandler(CMU_INSTANCE_0); +} + +void CMU1_IRQHandler(void) +{ + CMU_IRQHandler(CMU_INSTANCE_1); +} + +void CMU2_IRQHandler(void) +{ + CMU_IRQHandler(CMU_INSTANCE_2); +} + +void CMU3_IRQHandler(void) +{ + CMU_IRQHandler(CMU_INSTANCE_3); +} + +void CMU4_IRQHandler(void) +{ + CMU_IRQHandler(CMU_INSTANCE_4); +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_cordic.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_cordic.c new file mode 100644 index 0000000..4f4162a --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_cordic.c @@ -0,0 +1,280 @@ +/** + * @file fc7xxx_driver_cordic.c + * @author Flagchip + * @brief FC7xxx Cordic driver source code + * @version 0.1.0 + * @date 2024-01-11 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-11 Flagchip054 N/A First version for FC7240 + ******************************************************************************** */ +#include "fc7xxx_driver_cordic.h" +#include "interrupt_manager.h" + +#define CORDIC_SIGN_BIT 0x80000000UL +#define CORDIC_EXP_BIT 0x7F800000UL +#define CORDIC_TAIL_BIT 0x007FFFFFUL + +#define REVERSE_SCALEING_FACTOR_K 0x4dba76b2 +#define REVERSE_SCALEING_FACTOR_KA 0x9A8F4314 + +#define USE_FPU_HARDWARE 0 + + +/** + * @brief Floating-point conversion to 24 bit fixed-point + * + * @param nFloat Input value + */ + + +/*************** Local Functions ***************/ +/** + * @brief Clips Q63 to Q31 values. + */ +__attribute__((always_inline)) static inline int32_t clip_q63_to_q31( + int64_t x) +{ + return ((int32_t)(x >> 32) != ((int32_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((int32_t)(x >> 63)))) : (int32_t) x; +} + + +static int32_t Float2Fix_Convert(const float data) +{ + return clip_q63_to_q31((int64_t)(data * 2147483648.0f)); +} + +/***************** Global Functions *******************/ +/** + * @brief The function to calculate sin & cos + * + * @param radian the input value to calculate + * + * input range (−90°, +90°)/180° + */ +CORDIC_SinCos_Type Cordic_Circular_Sin_Cos(const float radian) +{ + /* angles are expressed in radian, multiplied by a constant number. 𝜃/180 * 𝜋c (where 𝜋c is 13.42177) */ + CORDIC_SinCos_Type tRetVal; + //float tmp = REVERSE_SCALEING_FACTOR_K; + float tmp = 0; + int32_t fix_radian = Float2Fix_Convert(radian); + int32_t x_input = REVERSE_SCALEING_FACTOR_K; + Cordic_HWA_Set_XInput(x_input); + Cordic_HWA_Set_YInput(0); + Cordic_HWA_Set_ZInput(fix_radian); + /* Disable interrupt + Iteration Number16 + Trigonometric system + Rotate mode */ + Cordic_HWA_SetCtrl(CORDIC_CTR_VAL(0, false, (uint32_t)CORDIC_Iteration_16, (uint32_t)CORDIC_Trigonometric, (uint32_t)CORDIC_Rotate)); + while (!Cordic_HWA_Get_Stat()) {} + tmp = (int32_t)Cordic_HWA_Get_YOutput() / 2147483648.f; //134217728.f; + tRetVal.sinx = tmp; + tmp = (int32_t)Cordic_HWA_Get_XOutput() / 2147483648.f; //134217728.f; + tRetVal.cosx = tmp; + return tRetVal; +} + +/** + * @brief The function to calculate circular radical add + * + * @param1 x the first input value + * + * @param2 y the second input value + */ +CORDIC_Radical_Type Cordic_Circular_Radical_Add(const float x, const float y) +{ + CORDIC_Radical_Type tRetVal; + /*** 40752053.5625 = REVERSE_SCALEING_FACTOR_K / 32 ***/ + int32_t x_input = (int32_t)(40752053.5625 * x); + int32_t y_input = (int32_t)(40752053.5625 * y); + Cordic_HWA_Set_XInput(x_input); + Cordic_HWA_Set_YInput(y_input); + Cordic_HWA_Set_ZInput(0); + /* Disable interrupt + Iteration Number16 + Trigonometric system + Vector mode */ + Cordic_HWA_SetCtrl(CORDIC_CTR_VAL(5, false, (uint32_t)CORDIC_Iteration_16, (uint32_t)CORDIC_Trigonometric, (uint32_t)CORDIC_Vector)); + while (!Cordic_HWA_Get_Stat()) {} + /*** 67,108,864 = 2147483648.f / 32 ***/ + tRetVal = Cordic_HWA_Get_XOutput() / 67108864.f; + return tRetVal; +} + +/** + * @brief The function to calculate circular arctan + * + * @param y the input value + */ +CORDIC_Arctan_Type Cordic_Circular_Arctan_F(const float y) +{ + CORDIC_Arctan_Type tRetVal; + if ((y > 96.6) || (y < -96.6)) + { + tRetVal = 89.4069; + } + else + { + int32_t x_input = 2147484; + int32_t y_input = (int32_t)(y * 2147484); + Cordic_HWA_Set_XInput(x_input); + Cordic_HWA_Set_YInput(y_input); + Cordic_HWA_Set_ZInput(0); + /* Disable interrupt + Iteration Number16 + Trigonometric system + Vector mode */ + Cordic_HWA_SetCtrl(CORDIC_CTR_VAL(0, false, (uint32_t)CORDIC_Iteration_16, (uint32_t)CORDIC_Trigonometric, (uint32_t)CORDIC_Vector)); + while (!Cordic_HWA_Get_Stat()) {} + /*** 11,930,464.711111 = 12147483648 / 180 ***/; + tRetVal = (int32_t)Cordic_HWA_Get_ZOutput() / 11930464.711111; + } + return tRetVal; +} + +/** + * @brief The function to calculate circular arctan + * + * @param1 x the first input value + * + * @param2 y the second input value + */ +CORDIC_Arctan_Type Cordic_Circular_Arctan(const int32_t x, const int32_t y) +{ + CORDIC_Arctan_Type tRetVal; + + Cordic_HWA_Set_XInput(x); + Cordic_HWA_Set_YInput(y); + Cordic_HWA_Set_ZInput(0); + /* Disable interrupt + Iteration Number16 + Trigonometric system + Vector mode */ + Cordic_HWA_SetCtrl(CORDIC_CTR_VAL(0, false, (uint32_t)CORDIC_Iteration_16, (uint32_t)CORDIC_Trigonometric, (uint32_t)CORDIC_Vector)); + while (!Cordic_HWA_Get_Stat()) {} + /*** 11,930,464.711111 = 12147483648 / 180 ***/; + tRetVal = (int32_t)Cordic_HWA_Get_ZOutput() / 11930464.711111; + return tRetVal; +} + +/** + * @brief The function to calculate circular Sinh & Cosh + * + * @param z the input value + */ +CORDIC_SinhCosh_Type Cordic_Circular_Sinh_Cosh(const float z) +{ + CORDIC_SinhCosh_Type tRetVal; + float tmp = 0; + + /*** 1073741824 = 2147483648 / 2 ***/ + int32_t z_input = (int32_t)(z * 1073741824.f); + /*** 1296540042 = REVERSE_SCALEING_FACTOR_KA / 2 ***/ + int32_t x_input = 1296540042; + + Cordic_HWA_Set_XInput(x_input); + Cordic_HWA_Set_YInput(0); + Cordic_HWA_Set_ZInput(z_input); + /* Scale 1 + Disable interrupt + Iteration Number16 + Hyperbolic system + Rotate mode */ + Cordic_HWA_SetCtrl(CORDIC_CTR_VAL(1, false, (uint32_t)CORDIC_Iteration_16, (uint32_t)CORDIC_Hyperbolic, (uint32_t)CORDIC_Rotate)); + while (!Cordic_HWA_Get_Stat()) {} + /*** 1073741824 = 2147483648 / 2 ***/ + tmp = (int32_t)Cordic_HWA_Get_YOutput() / 1073741824.f ; + tRetVal.sinxh = tmp; + /*** 1073741824 = 2147483648 / 2 ***/ + tmp = (int32_t)Cordic_HWA_Get_XOutput() / 1073741824.f; + tRetVal.cosxh = tmp; + return tRetVal; +} + +/** + * @brief The function to calculate circular radical sub + * + * @param1 x the first input value + * + * @param2 y the second input value + */ +CORDIC_Radical_Type Cordic_Circular_Radical_Sub(const float x, const float y) +{ + CORDIC_Radical_Type tRetVal; + /*** 162067505 = REVERSE_SCALEING_FACTOR_KA / 16 ***/ + int32_t x_input = (int32_t)(162067505.f * x); + int32_t y_input = (int32_t)(162067505.f * y); + + Cordic_HWA_Set_XInput(x_input); + Cordic_HWA_Set_YInput(y_input); + Cordic_HWA_Set_ZInput(0); + /* Disable interrupt + Iteration Number16 + Hyperbolic system + Vector mode */ + Cordic_HWA_SetCtrl(CORDIC_CTR_VAL(4, false, (uint32_t)CORDIC_Iteration_16, (uint32_t)CORDIC_Hyperbolic, (uint32_t)CORDIC_Vector)); + while (!Cordic_HWA_Get_Stat()) {} + /*** 134217728 = 2147483648.f / 16 ***/ + tRetVal = Cordic_HWA_Get_XOutput() / 134217728.f; + return tRetVal; +} + +/** + * @brief The function to calculate circular arctanh + * + * @param y the input value + */ +CORDIC_Arctanh_Type Cordic_Circular_Arctanh(const float y) +{ + CORDIC_Arctanh_Type tRetVal; + + /*** 1073741824 = 2147483648 / 2 ***/ + int32_t x_input = 1073741824; + int32_t y_input = (int32_t)(y * 1073741824.f); + + Cordic_HWA_Set_XInput(x_input); + Cordic_HWA_Set_YInput(y_input); + Cordic_HWA_Set_ZInput(0); + /* Disable interrupt + Iteration Number16 + Hyperbolic system + Vector mode */ + Cordic_HWA_SetCtrl(CORDIC_CTR_VAL(1, false, (uint32_t)CORDIC_Iteration_16, (uint32_t)CORDIC_Hyperbolic, (uint32_t)CORDIC_Vector)); + while (!Cordic_HWA_Get_Stat()) {} + /*** 1073741824 = 2147483648 / 2 ***/ + tRetVal = (int32_t)Cordic_HWA_Get_ZOutput() / 1073741824.f; + return tRetVal; +} + +/** + * @brief The function to calculate ln + * + * @param y the input value (0.1068482375 , 9.3590687463) + */ +CORDIC_Ln_Type Cordic_Extended_LN(const float y) +{ + CORDIC_Ln_Type tRetVal; + /*** 134217728 = 2147483648 / 16 ***/ + int32_t x_input = (int32_t)((y + 1) * 134217728.f); + int32_t f_input = (int32_t)((y - 1) * 134217728.f); + Cordic_HWA_Set_XInput(x_input); + Cordic_HWA_Set_YInput(f_input); + Cordic_HWA_Set_ZInput(0); + /* Disable interrupt + Iteration Number16 + Hyperbolic system + Vector mode */ + Cordic_HWA_SetCtrl(CORDIC_CTR_VAL(4, false, (uint32_t)CORDIC_Iteration_16, (uint32_t)CORDIC_Hyperbolic, (uint32_t)CORDIC_Vector)); + while (!Cordic_HWA_Get_Stat()) {} + /*** 67108864 = 12147483648.f / 32 ***/; + tRetVal = (int32_t)Cordic_HWA_Get_ZOutput() / 67108864.f; + return tRetVal; +} + +/** + * @brief The function to calculate sqrt + * + * @param y the input value (0.0267120594,2.3397671865) + */ +CORDIC_Ln_Type Cordic_Extended_Sqrt(const float y) +{ + CORDIC_Radical_Type tRetVal; + /*** 648270021 = 2593080084 / 4 ***/ + int32_t x_input = (int32_t)(648270021.f * (y + 0.25)); + int32_t y_input = (int32_t)(648270021.f * (y - 0.25)); + + Cordic_HWA_Set_XInput(x_input); + Cordic_HWA_Set_YInput(y_input); + Cordic_HWA_Set_ZInput(0); + /* Disable interrupt + Iteration Number16 + Hyperbolic system + Vector mode */ + Cordic_HWA_SetCtrl(CORDIC_CTR_VAL(2, false, (uint32_t)CORDIC_Iteration_16, (uint32_t)CORDIC_Hyperbolic, (uint32_t)CORDIC_Vector)); + while (!Cordic_HWA_Get_Stat()) {} + /*** 536870912 = 2147483648 / 4 ***/ + tRetVal = Cordic_HWA_Get_XOutput() / 536870912.f; + return tRetVal; +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_cpm.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_cpm.c new file mode 100644 index 0000000..688ce50 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_cpm.c @@ -0,0 +1,210 @@ + /* @file fc7xxx_driver_cpm.c + * @author Flagchip + * @brief FC7xxx CPM driver type definition and API + * @version 0.1.0 + * @date 2024-01-5 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + */ + + /* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-1-5 Flagchip120 N/A First version for FC7240 + ******************************************************************************** */ +#include "fc7xxx_driver_cpm.h" +#include "interrupt_manager.h" +#include "fc7xxx_driver_fcuart.h" + +/** + * @brief Cpm user defined interrupt function + * */ +static CPM_InterruptCallBackType s_pCpmNotifyPtr = NULL; + +/* ################################################################################## */ +/* ########################### Local Prototype Functions ############################ */ +void CPM_IRQHandler(void); + +/* ################################################################################## */ +/* ################################ Global Functions ################################ */ +/** + * + * @brief Configures the CPM module interrupts. + * + * This function configures the CPM module interrupts to enable/disable various interrupt sources. + * + * @param eIntSrc CPM FPU interrupt type. refer CPM FISCR register + * @param bEnable 1: interrupt enable, 0:interrupt disable. + */ +void CPM_FpuIntMode(FPU_IntType eIntSrc, bool bEnable) +{ + switch (eIntSrc) + { + case CPM_FPU_FIO: + CPM_HWA_SetFioceInt(bEnable); + break; + case CPM_FPU_FDZ: + CPM_HWA_SetFdzceInt(bEnable); + break; + case CPM_FPU_FOF: + CPM_HWA_SetFofceInt(bEnable); + break; + case CPM_FPU_FUF: + CPM_HWA_SetFufceInt(bEnable); + break; + case CPM_FPU_FIX: + CPM_HWA_SetFixceInt(bEnable); + break; + case CPM_FPU_FID: + CPM_HWA_SetFidceInt(bEnable); + break; + default : + /* Invalid parameter: return */ + break; + } +} + +/** + * @brief Get CPM Interrupt occurred flag + * + * This function returns the interrupt flag. + * + * @param eIntSrc CPM FPU interrupt type. refer CPM FISCR register + * @return true interrupt occurred + * @return false No interrupt + */ +bool CPM_GetFpuIntStatus(FPU_IntType eIntSrc) +{ + bool bRetVal = false; + switch(eIntSrc){ + case CPM_FPU_FIO: + bRetVal = CPM_HWA_GetFpuFiocFlag(); + break; + case CPM_FPU_FDZ: + bRetVal = CPM_HWA_GetFpuFdzcFlag(); + break; + case CPM_FPU_FOF: + bRetVal = CPM_HWA_GetFpuFofcFlag(); + break; + case CPM_FPU_FUF: + bRetVal = CPM_HWA_GetFpuFufcFlag(); + break; + case CPM_FPU_FIX: + bRetVal = CPM_HWA_GetFpuFixcFlag(); + break; + case CPM_FPU_FID: + bRetVal = CPM_HWA_GetFpuFidcFlag(); + break; + default: + break; + + } + return bRetVal; +} + + +#ifdef FPU_USED_ENABLE +/** + * @brief CPM_Read_FPSCR + * Return the current value of FPSCR + * @return u32RetVal + */ +uint32_t CPM_Read_FPSCR(void) +{ + uint32_t u32RetVal = 0U; + __asm( + "vmrs %0, fpscr" : "=r" (u32RetVal) + ); + return u32RetVal; +} + +/** + * @brief CPM_Write_FPSCR + * + * @param u32SetVal set the value for FPSCR + */ +void CPM_Write_FPSCR(uint32_t u32SetVal) +{ + __asm( + "vmsr fpscr, %0" : : "r" (u32SetVal) + ); +} + +/** + * @brief Deinit Cpm set interrupt + * + * Restore the Cpm FISCR to its reset state + */ +void CPM_DeInitInterrupt(void) +{ + uint32_t u32RetVal; + CPM_HWA_SetFiscr(0x0U); + u32RetVal = CPM_Read_FPSCR(); + /* Clear FPSCR IDC/IXC/UFC/OPF/DZC/IOC flag*/ + u32RetVal &=0xFFFFFF90u; + CPM_Write_FPSCR(u32RetVal); +} +#endif + +/** + * @brief CPM interrupt function + * + */ +void CPM_IRQHandler(void) +{ + if(s_pCpmNotifyPtr != NULL) + { + s_pCpmNotifyPtr(); + } +} + +/** + * @brief Cpm set interrupt + * + * @param pIntStruct interrupt structure pointer + * @return Cpm return type + */ +CPM_RetType CPM_InitInterrupt(const CPM_InterruptType *pIntStruct) +{ + CPM_RetType eRet = CPM_STATUS_SUCCESS; + if(NULL == pIntStruct) + { + eRet = CPM_STATUS_PARAM_INVALID; + } + else + { + if(pIntStruct->u8CpmEnable != 0U) + { + if(((uint32_t)(pIntStruct->eFPU_IntType) & CPM_FISCR_FIOC_MASK) == CPM_FPU_FIO) + { + CPM_FpuIntMode(CPM_FPU_FIO,true); + } + if(((uint32_t)(pIntStruct->eFPU_IntType) & CPM_FISCR_FDZC_MASK) == CPM_FPU_FDZ) + { + CPM_FpuIntMode(CPM_FPU_FDZ,true); + } + if(((uint32_t)(pIntStruct->eFPU_IntType) & CPM_FISCR_FUFC_MASK) == CPM_FPU_FUF) + { + CPM_FpuIntMode(CPM_FPU_FUF,true); + } + if(((uint32_t)(pIntStruct->eFPU_IntType) & CPM_FISCR_FOFC_MASK) == CPM_FPU_FOF) + { + CPM_FpuIntMode(CPM_FPU_FOF,true); + } + if(((uint32_t)(pIntStruct->eFPU_IntType) & CPM_FISCR_FIDC_MASK) == CPM_FPU_FID) + { + CPM_FpuIntMode(CPM_FPU_FID,true); + } + if(((uint32_t)(pIntStruct->eFPU_IntType) & CPM_FISCR_FIXC_MASK) == CPM_FPU_FIX) + { + CPM_FpuIntMode(CPM_FPU_FIX,true); + } + } + s_pCpmNotifyPtr = pIntStruct->pIsrNotify; + } + return eRet; +} + diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_crc.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_crc.c new file mode 100644 index 0000000..feacc2f --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_crc.c @@ -0,0 +1,167 @@ +/** + * @file fc7xxx_driver_crc.c + * @author Flagchip + * @brief FC7xxx CRC driver source code + * @version 0.1.0 + * @date 2024-01-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/******************************************************************************** +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2024-01-12 Flagchip119 N/A First version for FC7240 +********************************************************************************/ + +#include "fc7xxx_driver_crc.h" + + + +/********* Local Variables ************/ +static CRC_Type *const s_apCrcBase[CRC_INSTANCE_COUNT] = CRC_BASE_PTRS; + + +/********* Local Functions ************/ + +void CRC_Init(uint8_t u8Instance, const CRC_InitType *const pInitCfg) +{ + DEV_ASSERT(u8Instance < CRC_INSTANCE_COUNT); + DEV_ASSERT(pInitCfg != NULL); + CRC_Type *const pCrc = s_apCrcBase[u8Instance]; + + if (pInitCfg->eBitWidth == CRC_BIT_8) + { + /* set CRC bit width(8-bit) */ + CRC_HWA_Set_8Bit_Width(pCrc, (CRC_BitWidthType)(pInitCfg->eBitWidth - 1)); + CRC_HWA_SetBitWidth(pCrc, (CRC_BitWidthType)0); + } + else + { + /* set CRC bit width(16-bit or 32-bit) */ + CRC_HWA_Set_8Bit_Width(pCrc, (CRC_BitWidthType)0); + CRC_HWA_SetBitWidth(pCrc, pInitCfg->eBitWidth); + } + + /* set CRC write/read swap and FXOR */ + CRC_HWA_SetWriteDataSwap(pCrc, pInitCfg->eWriteDataSwap); + CRC_HWA_SetReadDataSwap(pCrc, pInitCfg->eReadDataSwap); + CRC_HWA_SetReadDataFXOR(pCrc, pInitCfg->eReadDataFXOR); + + /* set CRC polynomial value */ + CRC_HWA_SetPolyVal(pCrc, pInitCfg->u32Polynomial); + + /* set CRC seed value */ + CRC_SetSeed(u8Instance, pInitCfg->u32SeedValue); +} + +void CRC_DeInit(uint8_t u8Instance) +{ + DEV_ASSERT(u8Instance < CRC_INSTANCE_COUNT); + CRC_Type *const pCrc = s_apCrcBase[u8Instance]; + + /* set CRC bit width(32-bit) */ + CRC_HWA_SetBitWidth(pCrc, CRC_BIT_32); + + /* set CRC write/read swap and FXOR */ + CRC_HWA_SetWriteDataSwap(pCrc, WRITE_DATASWAP_NONE); + CRC_HWA_SetReadDataSwap(pCrc, READ_DATASWAP_NONE); + CRC_HWA_SetReadDataFXOR(pCrc, READ_DATA_NORMAL); + + /* set CRC polynomial value */ + CRC_HWA_SetPolyVal(pCrc, CRC_DEFAULT_POLY); + + /* set CRC seed value */ + CRC_SetSeed(u8Instance, CRC_DEFAULT_INTVAL); +} + +uint32_t CRC_GetCrcResult(uint8_t u8Instance) +{ + DEV_ASSERT(u8Instance < CRC_INSTANCE_COUNT); + CRC_Type *const pCrc = s_apCrcBase[u8Instance]; + CRC_ReadDataSwapType eTempVal; + uint32_t u32Ret; + + eTempVal = CRC_HWA_GetReadDataSwap(pCrc); + + if (CRC_BIT_8 == CRC_HWA_Get8BitWidth(pCrc)) + { + /* Returns upper 8 bits of CRC because of swap in 8 bits mode */ + if ((eTempVal == READ_DATASWAP_BIT_BYTE) || (eTempVal == READ_DATASWAP_BYTE)) + { + u32Ret = CRC_HWA_GetData_U8_H(pCrc); + } + else + { + u32Ret = CRC_HWA_GetData_U8_L(pCrc); + } + return u32Ret; + } + else if (CRC_BIT_16 == CRC_HWA_GetBitWidth(pCrc)) + { + /* Returns upper 16 bits of CRC because of swap in 16 bits mode */ + if ((eTempVal == READ_DATASWAP_BIT_BYTE) || (eTempVal == READ_DATASWAP_BYTE)) + { + u32Ret = CRC_HWA_GetData_U16_H(pCrc); + } + else + { + u32Ret = CRC_HWA_GetData_U16_L(pCrc); + } + } + else + { + u32Ret = CRC_HWA_GetData_U32(pCrc); + } + + return u32Ret; +} + +void CRC_SetCalcData_U8(uint8_t u8Instance, uint8_t u8Data) +{ + DEV_ASSERT(u8Instance < CRC_INSTANCE_COUNT); + CRC_Type *const pCrc = s_apCrcBase[u8Instance]; + + CRC_HWA_SetData_U8(pCrc, u8Data); +} + +void CRC_SetCalcData_U16(uint8_t u8Instance, uint16_t u16Data) +{ + DEV_ASSERT(u8Instance < CRC_INSTANCE_COUNT); + CRC_Type *const pCrc = s_apCrcBase[u8Instance]; + + CRC_HWA_SetData_U16(pCrc, u16Data); +} + +void CRC_SetCalcData_U32(uint8_t u8Instance, uint32_t u32Data) +{ + DEV_ASSERT(u8Instance < CRC_INSTANCE_COUNT); + CRC_Type *const pCrc = s_apCrcBase[u8Instance]; + + CRC_HWA_SetData_U32(pCrc, u32Data); +} + +void CRC_SetSeed(uint8_t u8Instance, uint32_t u32SeedVal) +{ + DEV_ASSERT(u8Instance < CRC_INSTANCE_COUNT); + CRC_Type *const pCrc = s_apCrcBase[u8Instance]; + + CRC_HWA_SetDataOrSeed(pCrc, WRITE_COMMAND_SEED); + CRC_HWA_SetData_U32(pCrc, u32SeedVal); + CRC_HWA_SetDataOrSeed(pCrc, WRITE_COMMAND_DATA); +} + +void CRC_SetInputData(uint8_t u8Instance, const uint8_t pData[], uint32_t u32DataSize) +{ + DEV_ASSERT(u8Instance < CRC_INSTANCE_COUNT); + uint32_t i; + + for (i = 0U; i < u32DataSize; i++) + { + CRC_SetCalcData_U8(u8Instance, pData[i]); + } +} + + diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_csc.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_csc.c new file mode 100644 index 0000000..71e091d --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_csc.c @@ -0,0 +1,1698 @@ +/** + * @file fc7xxx_driver_csc.h + * @author Flagchip + * @brief FC7xxx csc driver type definition and API + * @version 0.1.0 + * @date 2024-01-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ + +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240 + ******************************************************************************** */ + +#include "fc7xxx_driver_csc.h" +#include "fc7xxx_driver_scg.h" + +/********* Local Macros ************/ +#define CSC_GET_CPU_ID() ((CSC_WPB_CpuType)1U) + +/********* Local Variables ************/ + +/********* Local functions ************/ + +/** + * @brief Get the frequency of AONCLK clock selected by CSC0_AONCLKSR[AONCLKSEL]. + * + * @return the frequency of AONCLK + */ +static uint32_t CSC0_GetAONClkFreq(void) +{ + CSC0_AONClkSrcType eAonClkSrc; + uint32_t u32Freq; + + eAonClkSrc = CSC0_HWA_GetAONClkSrc(); + + if (CSC0_AON_SIRCDIV_128K_CLK == eAonClkSrc) + { + u32Freq = CSC0_AONCLK_128K; + } + else if (CSC0_AON_SIRC32_1K_CLK == eAonClkSrc) + { + u32Freq = CSC0_AONCLK_1K; + } + else + { + u32Freq = CSC0_AONCLK_32K; + } + return u32Freq; +} + +/** + * @brief Get the frequency of AON32K clock selected by CSC0_AONCLKSR[AON32KCLKSEL]. + * + * @return the frequency of AON32K + */ +static uint32_t CSC0_GetAON32kClkFreq(void) +{ + CSC0_AON32KClkSrcType eAon32KSrc; + uint32_t u32Freq; + + eAon32KSrc = CSC0_HWA_GetAON32kClkSrc(); + + if (CSC0_AON32K_SOSC32K_CLK == eAon32KSrc) + { + u32Freq = CSC0_AONCLK_SOSC_32K; + } + else + { + u32Freq = CSC0_AONCLK_32K; + } + return u32Freq; +} + +/** + * @brief Get the frequency of RTC clock selected by CSC0_AONCLKSR[RTCCLKSEL]. + * + * @return the frequency of RTC + */ +static uint32_t CSC0_GetRTCClkFreq(void) +{ + CSC0_RTCClkSrcType eRtcClkSrc; + uint32_t u32Freq; + + eRtcClkSrc = CSC0_HWA_GetRTCClkSrc(); + if (CSC0_RTC_FOSCDIVL_CLK == eRtcClkSrc) + { + u32Freq = SCG_GetScgClockFreq(SCG_FOSCDIVL_CLK); + } + else if (CSC0_RTC_SOSC_CLK == eRtcClkSrc) + { + u32Freq = CSC0_AONCLK_SOSC_32K; + } + else + { + u32Freq = CSC0_AONCLK_32K; + } + + return u32Freq; +} + +/** + * @brief Get the frequency of output clock selected by CSC0_CLKOUT_CTRL[CLKOUT_SEL]. + * + * @return the frequency of CSC0 output clock + */ +static uint32_t CSC0_GetClockOutFreq(void) +{ + uint32_t u32Freq; + CSC0_ClockOutSrcType eClkOutSrc; + CSC0_ClockOutDivType eClkOutDiv; + + + eClkOutSrc = CSC0_HWA_GetClkOutSel(); + eClkOutDiv = CSC0_HWA_GetClkOutDiv(); + + if(eClkOutSrc == CSC0_CLKOUT_SCG_CLKOUT) + { + u32Freq = SCG_GetScgClockFreq(SCG_SCG_CLKOUT_CLK); + } + else if(eClkOutSrc == CSC0_CLKOUT_FOSC_DIVM_CLK) + { + u32Freq = SCG_GetScgClockFreq(SCG_FOSCDIVM_CLK); + } + else if(eClkOutSrc == CSC0_CLKOUT_SLOW_CLK) + { + u32Freq = SCG_GetScgClockFreq(SCG_SLOW_CLK); + } + else if(eClkOutSrc == CSC0_CLKOUT_SIRC_DIVM_CLK) + { + u32Freq = SCG_GetScgClockFreq(SCG_SIRCDIVM_CLK); + } + else if(eClkOutSrc == CSC0_CLKOUT_PLL1_DIVM_CLK) + { + u32Freq = SCG_GetScgClockFreq(SCG_PLL1DIVM_CLK); + } + else if(eClkOutSrc == CSC0_CLKOUT_FIRC_DIVM_CLK) + { + u32Freq = SCG_GetScgClockFreq(SCG_FIRCDIVM_CLK); + } + else if(eClkOutSrc == CSC0_CLKOUT_CORE_CLK) + { + u32Freq = SCG_GetScgClockFreq(SCG_CORE_CLK); + } + else if(eClkOutSrc == CSC0_CLKOUT_PLL0_DIVM_CLK) + { + u32Freq = SCG_GetScgClockFreq(SCG_PLL0DIVM_CLK); + } + else if(eClkOutSrc == CSC0_CLKOUT_BUS_CLK) + { + u32Freq = SCG_GetScgClockFreq(SCG_BUS_CLK); + } + else if(eClkOutSrc == CSC0_CLKOUT_SIRC_128K_CLK) + { + u32Freq = CSC0_AONCLK_128K; + } + else if(eClkOutSrc == CSC0_CLKOUT_AON_CLK) + { + u32Freq = CSC0_GetAONClkFreq(); + } + else if(eClkOutSrc == CSC0_CLKOUT_RTC_CLK) + { + u32Freq = CSC0_GetRTCClkFreq(); + } + else + { + u32Freq = 0U; + } + + return u32Freq / ((uint32_t)eClkOutDiv + 1U); +} + +/** + * @brief Set cpu to control peripheral group 0 in CSC0. + * + * @param eCpuType Cpu to use + * @param eTarget Target to be set stop ack/request + * @param bLockStatus Lock current register.Once locked, calling the API returns an error(CSC_E_LOCK). + * + * @return Set clock out operation success/failed + */ +static CSC_RetStatusType CSC0_SetCpuCtrlGrp0(const CSC_WPB_CpuType eCpuType, CSC_SetTargetType eTarget, bool bLockStatus) +{ + CSC_RetStatusType eRetVal = CSC_E_LOCK; + + if (CSC_STOPACK == eTarget) + { + if (0U == CSC0_HWA_MODER0_GetWPBLockStatus()) + { + CSC0_HWA_MODER0_SetCpuWritePermit(eCpuType); + + if(bLockStatus != false) + { + CSC0_HWA_MODER0_LockWritePermit(); + } + eRetVal = CSC_E_OK; + } + } + else + { + if (0U == CSC0_HWA_REQR0_GetWPBLockStatus()) + { + CSC0_HWA_REQR0_SetCpuWritePermit(eCpuType); + if(bLockStatus != false) + { + CSC0_HWA_REQR0_LockWritePermit(); + } + eRetVal = CSC_E_OK; + } + } + + return eRetVal; +} + +/** + * @brief Set cpu to control peripheral group 1 in CSC0. + * + * @param eCpuType Cpu to use + * @param eTarget Target to be set stop ack/request + * + * @return Set clock out operation success/failed + */ +static CSC_RetStatusType CSC0_SetCpuCtrlGrp1(const CSC_WPB_CpuType eCpuType, CSC_SetTargetType eTarget, bool bLockStatus) +{ + CSC_RetStatusType eRetVal = CSC_E_LOCK; + + if (CSC_STOPACK == eTarget) + { + if (0U == CSC0_HWA_MODER1_GetWPBLockStatus()) + { + CSC0_HWA_MODER1_SetCpuWritePermit(eCpuType); + if(bLockStatus != false) + { + CSC0_HWA_MODER1_LockWritePermit(); + } + eRetVal = CSC_E_OK; + } + } + else + { + if (0U == CSC0_HWA_REQR1_GetWPBLockStatus()) + { + CSC0_HWA_REQR1_SetCpuWritePermit(eCpuType); + if(bLockStatus != false) + { + CSC0_HWA_REQR1_LockWritePermit(); + } + eRetVal = CSC_E_OK; + } + } + + return eRetVal; +} + +/** + * @brief Set cpu to control peripheral group 2 in CSC0. + * + * @param eCpuType Cpu to use + * @param eTarget Target to be set stop ack/request + * + * @return Set clock out operation success/failed + */ +static CSC_RetStatusType CSC0_SetCpuCtrlGrp2(const CSC_WPB_CpuType eCpuType, CSC_SetTargetType eTarget, bool bLockStatus) +{ + CSC_RetStatusType eRetVal = CSC_E_LOCK; + + if (CSC_STOPACK == eTarget) + { + if (0U == CSC0_HWA_MODER2_GetWPBLockStatus()) + { + CSC0_HWA_MODER2_SetCpuWritePermit(eCpuType); + if(bLockStatus != false) + { + CSC0_HWA_MODER2_LockWritePermit(); + } + eRetVal = CSC_E_OK; + } + } + else + { + if (0U == CSC0_HWA_REQR2_GetWPBLockStatus()) + { + CSC0_HWA_REQR2_SetCpuWritePermit(eCpuType); + if(bLockStatus != false) + { + CSC0_HWA_REQR2_LockWritePermit(); + } + eRetVal = CSC_E_OK; + } + } + + return eRetVal; +} + +/** + * @brief Set the stop mode ACK of all group peripherals in CSC0. + * + * @param ePeriphGrp the group of peripherals to set the stop mode ACK value + * @param u32Value the CSCx_STOP_MODERx register value + * + * @return Operation success/failed + */ +static CSC_RetStatusType CSC0_SetStopModeAck(const CSC_PeriphGrpType ePeriphGrp,uint32_t u32Value) +{ + CSC_RetStatusType eRetVal = CSC_E_NO_PERM; + CSC_WPB_CpuType eCtrlCpu; + + if(ePeriphGrp == CSC_STOP_CTRL_GROUP_0) + { + eCtrlCpu = CSC0_HWA_MODER0_GetCpuWritePermit(); + + if((eCtrlCpu == CSC_GET_CPU_ID()) || (eCtrlCpu == CSC_WP_CPU_ALL)) + { + CSC0_HWA_MODER0_SetMultiStopAck(u32Value); + eRetVal = CSC_E_OK; + } + + } + else if(ePeriphGrp == CSC_STOP_CTRL_GROUP_1) + { + eCtrlCpu = CSC0_HWA_MODER1_GetCpuWritePermit(); + + if((eCtrlCpu == CSC_GET_CPU_ID()) || (eCtrlCpu == CSC_WP_CPU_ALL)) + { + CSC0_HWA_MODER1_SetMultiStopAck(u32Value); + eRetVal = CSC_E_OK; + } + + } + else + { + eCtrlCpu = CSC0_HWA_MODER2_GetCpuWritePermit(); + + if((eCtrlCpu == CSC_GET_CPU_ID()) || (eCtrlCpu == CSC_WP_CPU_ALL)) + { + CSC0_HWA_MODER2_SetMultiStopAck(u32Value); + eRetVal = CSC_E_OK; + } + + } + + return eRetVal; +} + +/** + * @brief Set the stop request of all group peripherals in CSC0. + * + * @param eTargetCpuType The target CPU which acknowledges the peripherals when entering stop mode. + * @param ePeriphGrp the group of peripherals to set the stop request value + * @param u32Value the CSCx_STOP_REQRx register value + * + * @return Operation success/failed + */ +static CSC_RetStatusType CSC0_SetStopRequest(const CSC_PeriphGrpType ePeriphGrp,uint32_t u32Value) +{ + CSC_RetStatusType eRetVal = CSC_E_NO_PERM; + CSC_WPB_CpuType eCtrlCpu; + + if(ePeriphGrp == CSC_STOP_CTRL_GROUP_0) + { + eCtrlCpu = CSC0_HWA_REQR0_GetCpuWritePermit(); + + if((eCtrlCpu == CSC_GET_CPU_ID()) || (eCtrlCpu == CSC_WP_CPU_ALL)) + { + CSC0_HWA_REQR0_SetMultiStopRequest(u32Value); + eRetVal = CSC_E_OK; + } + + } + else if(ePeriphGrp == CSC_STOP_CTRL_GROUP_1) + { + eCtrlCpu = CSC0_HWA_REQR1_GetCpuWritePermit(); + + if((eCtrlCpu == CSC_GET_CPU_ID()) || (eCtrlCpu == CSC_WP_CPU_ALL)) + { + CSC0_HWA_REQR1_SetMultiStopRequest(u32Value); + eRetVal = CSC_E_OK; + } + + } + else + { + eCtrlCpu = CSC0_HWA_REQR2_GetCpuWritePermit(); + + if((eCtrlCpu == CSC_GET_CPU_ID()) || (eCtrlCpu == CSC_WP_CPU_ALL)) + { + CSC0_HWA_REQR2_SetMultiStopRequest(u32Value); + eRetVal = CSC_E_OK; + } + + } + + return eRetVal; +} + +/** + * @brief Get the stop Acknowledge status of all group peripherals in CSC0. + * + * @param ePeriphType the peripheral to get stop acknowledge status + * @return uint32_t the stop ACK status of all the peripherals in the group indicated by ePeriphGrp. + */ +static uint32_t CSC0_GetStopAckStatus(const CSC_PeriphGrpType ePeriphGrp) +{ + uint32_t eRetVal; + + if(CSC_STOP_CTRL_GROUP_0 == ePeriphGrp) + { + eRetVal = CSC0_HWA_ACKR0_GetMultiStopAckStatus(CSC_STOP_PERIPH_GROUP0_MASK); + } + else if(CSC_STOP_CTRL_GROUP_1 == ePeriphGrp) + { + eRetVal = CSC0_HWA_ACKR1_GetMultiStopAckStatus(CSC_STOP_PERIPH_GROUP1_MASK); + } + else + { + eRetVal = CSC0_HWA_ACKR2_GetMultiStopAckStatus(CSC_STOP_PERIPH_GROUP2_MASK); + } + return eRetVal; +} + + + + + + +/********* Global functions ************/ +/** + * @brief set clock out. with clock out pin configure, the clock would be monitored. + * This Function may combined with SCG_ClkOut setting + * need to call SCG_SetClkOut,if clock out source set to SCG_CLKOUT. * + * @param pCsc0ClkOut to Csc0ClkOut instance for clock out configuration + * @param bLockStatus to lock current register.Once locked, calling the API returns an error(CSC_E_LOCK). + * + * @return CSC_RetStatusType + * CSC_E_OK: The API is successfully called + * CSC_E_LOCK: The register has been locked and can not be written + * @note configuration sequence: + * 1. Disable CLKOUTEN + * 2. Set CLKOUTSEL + * 3. Enable CLKOUTEN + */ +CSC_RetStatusType CSC0_SetClockOut(const CSC0_ClkoutType *const pCsc0ClkOut, bool bLockStatus) +{ + DEV_ASSERT(pCsc0ClkOut != NULL); + CSC_RetStatusType eRetVal; + + /* Check CSC0_CLKOUT_CTRL register lock status */ + if (0U == CSC0_HWA_CLKOUT_CTRL_GetLockStatus()) + { + eRetVal = CSC_E_OK; + /* Disable CLKOUTEN */ + CSC0_HWA_DisableClockOut(); + /* Set CLKOUTDIV */ + CSC0_HWA_SetClkOutDiv(pCsc0ClkOut->eDivider); + /* Set CLKOUTSEL */ + CSC0_HWA_SetClkOutSel(pCsc0ClkOut->eClkOutSrc); + /* Enable CLKOUTEN */ + CSC0_HWA_EnableClockOut(); + + if (true == bLockStatus) + { + /* Lock CSC0_CLKOUT_CTRL register */ + CSC0_HWA_LockCLKOUT_CTRL(); + } + } + else + { + eRetVal = CSC_E_LOCK; + } + + return eRetVal; +} + +/** + * @brief set always on clock source configuration include AON32K, RTC, AONCLK clock. + * + * @param pAonclkSrcType pointer to AONCLKSR instance for AON clock source configuration + * @param bLockStatus to lock current register.Once locked, calling the API returns an error(CSC_E_LOCK). + * + * @return CSC_RetStatusType + * CSC_E_OK: The API is successfully called + * CSC_E_LOCK: The register has been locked and can not be written + */ +CSC_RetStatusType CSC0_SetAonClkSrc(const CSC0_AONCLKSRType *const pAonclkSrcType, bool bLockStatus) +{ + CSC_RetStatusType eRetVal; + + DEV_ASSERT(pAonclkSrcType != NULL); + DEV_ASSERT(pAonclkSrcType->eAon32KSel == CSC0_AON32K_SIRCDIV_32K_CLK || + pAonclkSrcType->eAon32KSel == CSC0_AON32K_SOSC32K_CLK || + pAonclkSrcType->eAon32KSel == CSC0_AON32K_SIRC32K_CLK); + DEV_ASSERT(pAonclkSrcType->eRtcSel == CSC0_RTC_FOSCDIVL_CLK || + pAonclkSrcType->eRtcSel == CSC0_RTC_SIRCDIV_32K_CLK || + pAonclkSrcType->eRtcSel == CSC0_RTC_SOSC_CLK || + pAonclkSrcType->eRtcSel == CSC0_RTC_SIRC32K_CLK); + DEV_ASSERT(pAonclkSrcType->eAonSel == CSC0_AON_SIRCDIV_128K_CLK || + pAonclkSrcType->eAonSel == CSC0_AON_SIRC32K_CLK || + pAonclkSrcType->eAonSel == CSC0_AON_SIRCDIV_32K_CLK || + pAonclkSrcType->eAonSel == CSC0_AON_SIRC32_1K_CLK); + + + /* Check CSC0_AONCLKSR register lock status */ + if (0U == CSC0_HWA_AONCLKSR_GetLockStaus()) + { + eRetVal = CSC_E_OK; + + /* Gating SIRC_32K clock*/ + if ((CSC0_AON32K_SIRCDIV_32K_CLK == pAonclkSrcType->eAon32KSel) || + (CSC0_AON_SIRCDIV_32K_CLK == pAonclkSrcType->eAonSel) || + (CSC0_RTC_SIRCDIV_32K_CLK == pAonclkSrcType->eRtcSel)) + { + CSC0_HWA_EnableSIRCDIV_32KClkOut(); + } + + /* Gating SIRC32_1K clock*/ + if (CSC0_AON_SIRC32_1K_CLK == pAonclkSrcType->eAonSel) + { + CSC0_HWA_EnableSIRC32_1KClkOut(); + } + + /* Set AONCLOCK configuration */ + CSC0_HWA_SetAON32kClkSrc(pAonclkSrcType->eAon32KSel); + CSC0_HWA_SetRTCClkSrc(pAonclkSrcType->eRtcSel); + CSC0_HWA_SetAONClkSrc(pAonclkSrcType->eAonSel); + + if (true == bLockStatus) + { + /* Lock CSC0_AONCLKSR register */ + CSC0_HWA_LockAONCLKSR(); + } + } + else + { + eRetVal = CSC_E_LOCK; + } + + return eRetVal; +} + +/** + * @brief Report the clock source status and frequency configured in MCU run time. + * The clock frequency and status would change by clock set function. + * + * @param eClkkName: the CSC0 clock source to query + * @param pFreq: frequency variable point to get the frequency value + * + * @return CSC_RetStatusType + * CSC_E_OK: The API is successfully called + * CSC_E_NOT_OK: eClkkName invalid + */ +CSC_RetStatusType CSC0_GetCSC0ClockFreq(CSC0_ClkSrcType eClkkName, uint32_t *const pFreq) +{ + CSC_RetStatusType eRetVal; + DEV_ASSERT(pFreq != NULL); + + if ((uint32_t)eClkkName >= (uint32_t)CSC0_END_OF_CLOCKS) + { + eRetVal = CSC_E_NOT_OK; + *pFreq = 0U; + } + else + { + eRetVal = CSC_E_OK; + + if (CSC0_AON_CLK == eClkkName) + { + *pFreq = CSC0_GetAONClkFreq(); + } + else if (CSC0_AON32K_CLK == eClkkName) + { + *pFreq = CSC0_GetAON32kClkFreq(); + } + else if (CSC0_RTC_CLK == eClkkName) + { + *pFreq = CSC0_GetRTCClkFreq(); + } + else + { + /* CSC0_CLKOUT_CLK */ + *pFreq = CSC0_GetClockOutFreq(); + } + } + + return eRetVal; +} + +/** + * @brief SCG MAM stall request. + * @details Need to assert the SCG_STALL to stall MAM when configuring the SCG clock source. + * + * @param bEnable: true asserts SCG MAM stall request + * false do not asserts SCG MAM stall request + * @param bLockStatus: Lock the register.Once locked, calling the API returns an error(CSC_E_LOCK). + * + * @return CSC_RetStatusType + * CSC_E_OK: The API is successfully called + * CSC_E_LOCK: The register has been locked + */ +CSC_RetStatusType CSC0_ScgMAMStallRequest(bool bEnable, bool bLockStatus) +{ + CSC_RetStatusType eRetVal= CSC_E_LOCK; + + if (0U == CSC0_HWA_SCG_MAM_STALL_GetLockStatus()) + { + if(bEnable != false) + { + CSC0_HWA_EnalbeSCGStall(); + } + else + { + CSC0_HWA_DisableSCGStall(); + } + + if(bLockStatus != false) + { + CSC0_HWA_LockSCG_MAM_STALL(); + } + + eRetVal = CSC_E_OK; + } + + return eRetVal; +} + +/** + * @brief Set request to SMU of group 0. + * + * @param u32Value Value to be set(the or bits defined in CSC_SMU_CtrlGrp0Type,do not involve lock bit) + * @param bLockStatus Lock the register.Once locked, calling the API returns an error(CSC_E_LOCK). + * + * @return CSC_RetStatusType + * CSC_E_OK: The API is successfully called + * CSC_E_NOT_OK: The u32Value contains invalid bits + * CSC_E_LOCK: The register has been locked + */ +CSC_RetStatusType CSC0_SetReqToSMUGrp0(uint32_t u32Value, bool bLockStatus) +{ + CSC_RetStatusType eRetVal = CSC_E_PARAM; + + /* Check register bits invalid */ + if((u32Value & (~CSC_SMU_CTRL_GROUP0_MASK)) == 0U) + { + + /* Check register lock status */ + if (0U == CSC0_HWA_SMU_CTRL0_GetLockStatus()) + { + eRetVal = CSC_E_OK; + /* Set value(do not involve lock bit) */ + CSC0_HWA_CTRL0_SetMultiReqToSMU(u32Value); + if (true == bLockStatus) + { + /* Lock register */ + CSC0_HWA_LockSMU_CTRL0(); + } + } + else + { + eRetVal = CSC_E_LOCK; + } + } + + return eRetVal; +} + +/** + * @brief Set request to SMU of group 1. + * + * @param u32Value Value to be set(the or bits defined in CSC_SMU_CtrlGrp1Type,do not involve lock bit) + * @param bLockStatus Lock the register.Once locked, calling the API returns an error(CSC_E_LOCK). + * + * @return CSC_RetStatusType + * CSC_E_OK: The API is successfully called + * CSC_E_NOT_OK: The u32Value contains invalid bits + * CSC_E_LOCK: The register has been locked + */ +CSC_RetStatusType CSC0_SetReqToSMUGrp1(uint32_t u32Value, bool bLockStatus) +{ + CSC_RetStatusType eRetVal = CSC_E_PARAM; + + /* Check register bits invalid */ + if((u32Value & (~CSC_SMU_CTRL_GROUP1_MASK)) == 0U) + { + + /* Check register lock status */ + if (0U == CSC0_HWA_SMU_CTRL1_GetLockStatus()) + { + eRetVal = CSC_E_OK; + /* Set value(do not involve lock bit) */ + CSC0_HWA_CTRL1_SetMultiReqToSMU(u32Value); + if (true == bLockStatus) + { + /* Lock register */ + CSC0_HWA_LockSMU_CTRL1(); + } + } + else + { + eRetVal = CSC_E_LOCK; + } + } + + return eRetVal; +} + +/** + * @brief Set request to SMU of group 4. + * + * @param u32Value Value to be set(the or bits defined in CSC_SMU_CtrlGrp4Type,do not involve lock bit) + * @param bLockStatus Lock the register.Once locked, calling the API returns an error(CSC_E_LOCK). + * + * @return CSC_RetStatusType + * CSC_E_OK: The API is successfully called + * CSC_E_NOT_OK: The u32Value contains invalid bits + * CSC_E_LOCK: The register has been locked + */ +CSC_RetStatusType CSC0_SetReqToSMUGrp4(uint32_t u32Value, bool bLockStatus) +{ + CSC_RetStatusType eRetVal = CSC_E_PARAM; + + /* Check register bits invalid */ + if((u32Value & (~CSC_SMU_CTRL_GROUP4_MASK)) == 0U) + { + + /* Check register lock status */ + if (0U == CSC0_HWA_SMU_CTRL4_GetLockStatus()) + { + eRetVal = CSC_E_OK; + /* Set value(do not involve lock bit) */ + CSC0_HWA_CTRL4_SetMultiReqToSMU(u32Value); + if (true == bLockStatus) + { + /* Lock register */ + CSC0_HWA_LockSMU_CTRL4(); + } + } + else + { + eRetVal = CSC_E_LOCK; + } + } + + return eRetVal; +} + +/** + * @brief Set request to SMU of group 5. + * + * @param u32Value Value to be set(the or bits defined in CSC_SMU_CtrlGrp5Type,do not involve lock bit) + * @param bLockStatus Lock the register.Once locked, calling the API returns an error(CSC_E_LOCK). + * + * @return CSC_RetStatusType + * CSC_E_OK: The API is successfully called + * CSC_E_NOT_OK: The u32Value contains invalid bits + * CSC_E_LOCK: The register has been locked + */ +CSC_RetStatusType CSC0_SetReqToSMUGrp5(uint32_t u32Value, bool bLockStatus) +{ + CSC_RetStatusType eRetVal = CSC_E_PARAM; + + /* Check register bits invalid */ + if((u32Value & (~CSC_SMU_CTRL_GROUP5_MASK)) == 0U) + { + + /* Check register lock status */ + if (0U == CSC0_HWA_SMU_CTRL5_GetLockStatus()) + { + eRetVal = CSC_E_OK; + /* Set value(do not involve lock bit) */ + CSC0_HWA_CTRL5_SetMultiReqToSMU(u32Value); + if (true == bLockStatus) + { + /* Lock register */ + CSC0_HWA_LockSMU_CTRL5(); + } + } + else + { + eRetVal = CSC_E_LOCK; + } + } + + return eRetVal; +} + +/** + * @brief Set request to SMU . + * + * @param eCtrlGrp CSC0_SMU control group + * @param u32Value Value to be set(the or bits defined in CSC_SMU_CtrlGrp5Type,do not involve lock bit) + * @param bLockStatus Lock the register.Once locked, calling the API returns an error(CSC_E_LOCK). + * + * @return CSC_RetStatusType + * CSC_E_OK: The API is successfully called + * CSC_E_PARAM: The eCtrlGrp is invalid + * CSC_E_NOT_OK: The u32Value contains invalid bits + * CSC_E_LOCK: The register has been locked + * @note Group must be matched with u32Value which select from CSC0_SmuCtrlGrpType + */ +CSC_RetStatusType CSC0_SetReqToSMU(CSC0_SmuCtrlGrpType eCtrlGrp, uint32_t u32Value, bool bLockStatus) +{ + CSC_RetStatusType eRetVal; + + if (CSC0_SMU_CTRL_GROUP_0 == eCtrlGrp) + { + eRetVal = CSC0_SetReqToSMUGrp0(u32Value, bLockStatus); + } + else if (CSC0_SMU_CTRL_GROUP_1 == eCtrlGrp) + { + eRetVal = CSC0_SetReqToSMUGrp1(u32Value, bLockStatus); + } + else if (CSC0_SMU_CTRL_GROUP_4 == eCtrlGrp) + { + eRetVal = CSC0_SetReqToSMUGrp4(u32Value, bLockStatus); + } + else if (CSC0_SMU_CTRL_GROUP_5 == eCtrlGrp) + { + eRetVal = CSC0_SetReqToSMUGrp5(u32Value, bLockStatus); + } + else + { + eRetVal = CSC_E_NOT_OK; + } + + return eRetVal; +} + +/** + * @brief Configure the low power wakeup PAD output in CSC0_LP_WAKEUP register. + * + * @param eLPWakeupCfg: the low power wakeup PAD source and polarity configuration + * @param bLockStatus: Lock the register.Once locked, calling the API returns an error(CSC_E_LOCK). + * + * @return CSC_RetStatusType + * CSC_E_OK: The API is successfully called + * CSC_E_LOCK: The WPB of CSCx_STOP_MODERx is already locked + */ +CSC_RetStatusType CSC0_LP_WakeupPadOutputCfg(const CSC0_LPWakeupCfgType * const eLPWakeupCfg, bool bLockStatus) +{ + CSC_RetStatusType eRetVal; + + DEV_ASSERT(eLPWakeupCfg != NULL_PTR); + DEV_ASSERT((uint32_t)eLPWakeupCfg->eCfgGrp0 <= (uint32_t)CSC_LP_WAKEUP_FCPIT0_TRIGGER_OUT3); + DEV_ASSERT((uint32_t)eLPWakeupCfg->eCfgGrp1 <= (uint32_t)CSC_LP_WAKEUP_FCPIT0_TRIGGER_OUT3); + DEV_ASSERT((uint32_t)eLPWakeupCfg->eCfgGrp2 <= (uint32_t)CSC_LP_WAKEUP_FCPIT0_TRIGGER_OUT3); + DEV_ASSERT((uint32_t)eLPWakeupCfg->eCfgGrp3 <= (uint32_t)CSC_LP_WAKEUP_FCPIT0_TRIGGER_OUT3); + DEV_ASSERT((uint32_t)eLPWakeupCfg->eCfgGrp4 <= (uint32_t)CSC_LP_WAKEUP_FCPIT0_TRIGGER_OUT3); + DEV_ASSERT((uint32_t)eLPWakeupCfg->ePolGrp0 <= (uint32_t)CSC_LP_WAKEUP_POL_INVERT); + DEV_ASSERT((uint32_t)eLPWakeupCfg->ePolGrp1 <= (uint32_t)CSC_LP_WAKEUP_POL_INVERT); + DEV_ASSERT((uint32_t)eLPWakeupCfg->ePolGrp2 <= (uint32_t)CSC_LP_WAKEUP_POL_INVERT); + DEV_ASSERT((uint32_t)eLPWakeupCfg->ePolGrp3 <= (uint32_t)CSC_LP_WAKEUP_POL_INVERT); + DEV_ASSERT((uint32_t)eLPWakeupCfg->ePolGrp4 <= (uint32_t)CSC_LP_WAKEUP_POL_INVERT); + + if (0U == CSC0_HWA_LP_WAKEUP_GetLockStatus()) + { + CSC0_HWA_SetLP_WAKEUPCfgSrc(CSC_LP_WAKEUP_GROUP_0,eLPWakeupCfg->eCfgGrp0); + CSC0_HWA_SetLP_WAKEUPCfgSrc(CSC_LP_WAKEUP_GROUP_1,eLPWakeupCfg->eCfgGrp1); + CSC0_HWA_SetLP_WAKEUPCfgSrc(CSC_LP_WAKEUP_GROUP_2,eLPWakeupCfg->eCfgGrp2); + CSC0_HWA_SetLP_WAKEUPCfgSrc(CSC_LP_WAKEUP_GROUP_3,eLPWakeupCfg->eCfgGrp3); + CSC0_HWA_SetLP_WAKEUPCfgSrc(CSC_LP_WAKEUP_GROUP_4,eLPWakeupCfg->eCfgGrp4); + CSC0_HWA_SetLP_WAKEUPCfgPol(CSC_LP_WAKEUP_GROUP_0,eLPWakeupCfg->ePolGrp0); + CSC0_HWA_SetLP_WAKEUPCfgPol(CSC_LP_WAKEUP_GROUP_1,eLPWakeupCfg->ePolGrp1); + CSC0_HWA_SetLP_WAKEUPCfgPol(CSC_LP_WAKEUP_GROUP_2,eLPWakeupCfg->ePolGrp2); + CSC0_HWA_SetLP_WAKEUPCfgPol(CSC_LP_WAKEUP_GROUP_3,eLPWakeupCfg->ePolGrp3); + CSC0_HWA_SetLP_WAKEUPCfgPol(CSC_LP_WAKEUP_GROUP_4,eLPWakeupCfg->ePolGrp4); + + if(bLockStatus != false) + { + CSC0_HWA_LockLP_WAKEUP(); + } + + eRetVal = CSC_E_OK; + } + else + { + eRetVal = CSC_E_LOCK; + } + return eRetVal; +} + + +/** + * @brief Set CPU stop mode control permission. + * @detail This API is used to set the CPU write permission of a CPU's stop mode registers. + * eg.If the CPU(eTargetCpuType) enter stop mode, it acknowledges the peripherals according to the configuration + * in CSCx_STOP_MODERy (x: (CPUID) range[0] , y:(GROUP) range[0,1,2]), and the CPU(eCtrlCpuType) + * has the write permission of CSCx_STOP_MODERy registers, the permission is controlled by this API. + * + * @param eTargetCpuType The target CPU to set. + * @param eCtrlCpuType The CPU that has the write permission to the CSCx_STOP_MODERy register. + * @param ePeriphGrp Peripheral group (range:0,1,2) + * @param bLockStatus Lock the WPB of CSCx_STOP_MODERy.Once locked, calling the API returns an error(CSC_E_LOCK). + * + * @return CSC_RetStatusType + * CSC_E_OK: The API is successfully called + * CSC_E_NOT_OK: eTargetCpuType invalid + * CSC_E_LOCK: The WPB of CSCx_STOP_MODERx is already locked + */ +CSC_RetStatusType CSC_SetStopModeAckPermission(CSC_WPB_CpuType eTargetCpuType, CSC_WPB_CpuType eCtrlCpuType, + CSC_PeriphGrpType ePeriphGrp, bool bLockStatus) +{ + CSC_RetStatusType eRetVal = CSC_E_NOT_OK; + DEV_ASSERT((uint32_t)eCtrlCpuType < (uint32_t)CSC_WP_CPU_NONE); + DEV_ASSERT((uint32_t)ePeriphGrp <= (uint32_t)CSC_STOP_CTRL_GROUP_2); + + if (CSC_WP_CPU_0 == eTargetCpuType) + { + if (CSC_STOP_CTRL_GROUP_0 == ePeriphGrp) + { + eRetVal = CSC0_SetCpuCtrlGrp0(eCtrlCpuType, CSC_STOPACK, bLockStatus); + } + else if (CSC_STOP_CTRL_GROUP_1 == ePeriphGrp) + { + eRetVal = CSC0_SetCpuCtrlGrp1(eCtrlCpuType, CSC_STOPACK, bLockStatus); + } + else + { + eRetVal = CSC0_SetCpuCtrlGrp2(eCtrlCpuType, CSC_STOPACK, bLockStatus); + } + } + + return eRetVal; +} + +/** + * @brief Set CPU stop mode request control permission. + * @detail This API is used to set the CPU write permission of a CPU's stop mode request registers + * to generate a stop request to peripherals + * + * @param eTargetCpuType The target CPU to acknowledges stop mode to the enabled peripherals. + * @param eCtrlCpuType The CPU that has the write permission to the CSCx_STOP_REQRx register. + * @param ePeriphGrp Peripheral group (range:0,1,2) + * @param bLockStatus Lock the WPB of CSCx_STOP_REQRx.Once locked, calling the API returns an error(CSC_E_LOCK). + * + * @return CSC_RetStatusType + * CSC_E_OK: The API is successfully called + * CSC_E_NOT_OK: eTargetCpuType invalid + * CSC_E_LOCK: The WPB of CSCx_STOP_REQRx is already locked + */ +CSC_RetStatusType CSC_SetStopRequestPermission(CSC_WPB_CpuType eTargetCpuType, CSC_WPB_CpuType eCtrlCpuType, + CSC_PeriphGrpType ePeriphGrp, bool bLockStatus) +{ + CSC_RetStatusType eRetVal = CSC_E_NOT_OK; + DEV_ASSERT((uint32_t)eCtrlCpuType < (uint32_t)CSC_WP_CPU_NONE); + DEV_ASSERT((uint32_t)ePeriphGrp <= (uint32_t)CSC_STOP_CTRL_GROUP_2); + + if (CSC_WP_CPU_0 == eTargetCpuType) + { + if (CSC_STOP_CTRL_GROUP_0 == ePeriphGrp) + { + eRetVal = CSC0_SetCpuCtrlGrp0(eCtrlCpuType, CSC_STOPREQ, bLockStatus); + } + else if (CSC_STOP_CTRL_GROUP_1 == ePeriphGrp) + { + eRetVal = CSC0_SetCpuCtrlGrp1(eCtrlCpuType, CSC_STOPREQ, bLockStatus); + } + else + { + eRetVal = CSC0_SetCpuCtrlGrp2(eCtrlCpuType, CSC_STOPREQ, bLockStatus); + } + } + + return eRetVal; +} + +/** + * @brief Set the stop mode ACK of peripheral group 0 in CSC. + * + * @param eTargetCpuType The target CPU which acknowledges the ePeriphType when entering stop mode. + * @param ePeriphType the peripheral to enable or disable the stop mode ACK + * @param bEnable true: enable the stop mode ACK + * false: disable the stop mode ACK + * + * @return CSC_RetStatusType + * CSC_E_OK: The API is successfully called + * CSC_E_NOT_OK: eTargetCpuType invalid + * CSC_E_NO_PERM: Current CPU has no permission to access the register + */ +CSC_RetStatusType CSC_SetStopModeAckGrp0(CSC_WPB_CpuType eTargetCpuType, CSCx_Reg0_PeriphType ePeriphType, bool bEnable) +{ + CSC_RetStatusType eRetVal = CSC_E_NOT_OK; + CSC_WPB_CpuType eCtrlCpu; + + DEV_ASSERT((ePeriphType == CSC_STOPMODE_FLEXCAN1) || + (ePeriphType == CSC_STOPMODE_FLEXCAN0) || + (ePeriphType == CSC_STOPMODE_FREQM) || + (ePeriphType == CSC_STOPMODE_FCUART3) || + (ePeriphType == CSC_STOPMODE_FCUART2) || + (ePeriphType == CSC_STOPMODE_FCUART1) || + (ePeriphType == CSC_STOPMODE_FCSPI2) || + (ePeriphType == CSC_STOPMODE_FCSPI1) || + (ePeriphType == CSC_STOPMODE_SENT0) || + (ePeriphType == CSC_STOPMODE_TMU) || + (ePeriphType == CSC_STOPMODE_ADC1) || + (ePeriphType == CSC_STOPMODE_ADC0) || + (ePeriphType == CSC_STOPMODE_CMU4) || + (ePeriphType == CSC_STOPMODE_WDOG0) || + (ePeriphType == CSC_STOPMODE_ISM0) || + (ePeriphType == CSC_STOPMODE_DMA0)); + + if (CSC_WP_CPU_0 == eTargetCpuType) + { + eCtrlCpu = CSC0_HWA_MODER0_GetCpuWritePermit(); + + if((eCtrlCpu == CSC_GET_CPU_ID()) || (eCtrlCpu == CSC_WP_CPU_ALL)) + { + /* Set peripheral stop ack enable */ + if(bEnable != false) + { + CSC0_HWA_MODER0_EnableStopAck(ePeriphType); + } + else + { + CSC0_HWA_MODER0_DisableStopAck(ePeriphType); + } + eRetVal = CSC_E_OK; + } + else + { + eRetVal = CSC_E_NO_PERM; + } + } + + return eRetVal; +} + +/** + * @brief Set the stop request of peripheral group 0 in CSC. + * + * @param eTargetCpuType The target CPU which acknowledges the ePeriphType when entering stop mode. + * @param ePeriphType the peripheral to set stop request + * @param bEnable true: set the stop request + * false: clear the stop request + * + * @return CSC_RetStatusType + * CSC_E_OK: The API is successfully called + * CSC_E_NOT_OK: eTargetCpuType invalid + * CSC_E_NO_PERM: Current CPU has no permission to access the register + */ +CSC_RetStatusType CSC_SetStopRequestGrp0(CSC_WPB_CpuType eTargetCpuType, CSCx_Reg0_PeriphType ePeriphType, bool bEnable) +{ + CSC_RetStatusType eRetVal = CSC_E_NOT_OK; + CSC_WPB_CpuType eCtrlCpu; + + DEV_ASSERT((ePeriphType == CSC_STOPMODE_FLEXCAN1) || + (ePeriphType == CSC_STOPMODE_FLEXCAN0) || + (ePeriphType == CSC_STOPMODE_FREQM) || + (ePeriphType == CSC_STOPMODE_FCUART3) || + (ePeriphType == CSC_STOPMODE_FCUART2) || + (ePeriphType == CSC_STOPMODE_FCUART1) || + (ePeriphType == CSC_STOPMODE_FCSPI2) || + (ePeriphType == CSC_STOPMODE_FCSPI1) || + (ePeriphType == CSC_STOPMODE_SENT0) || + (ePeriphType == CSC_STOPMODE_TMU) || + (ePeriphType == CSC_STOPMODE_ADC1) || + (ePeriphType == CSC_STOPMODE_ADC0) || + (ePeriphType == CSC_STOPMODE_CMU4) || + (ePeriphType == CSC_STOPMODE_WDOG0) || + (ePeriphType == CSC_STOPMODE_ISM0) || + (ePeriphType == CSC_STOPMODE_DMA0)); + + if (CSC_WP_CPU_0 == eTargetCpuType) + { + eCtrlCpu = CSC0_HWA_REQR0_GetCpuWritePermit(); + + if((eCtrlCpu == CSC_GET_CPU_ID()) || (eCtrlCpu == CSC_WP_CPU_ALL)) + { + /* Set peripheral stop ack enable */ + if(bEnable != false) + { + CSC0_HWA_REQR0_SetStopRequest(ePeriphType); + } + else + { + CSC0_HWA_REQR0_ClearStopRequest(ePeriphType); + } + eRetVal = CSC_E_OK; + } + else + { + eRetVal = CSC_E_NO_PERM; + } + } + + return eRetVal; +} + +/** + * @brief Set the stop mode ACK of peripheral group 1 in CSC. + * + * @param eTargetCpuType The target CPU which acknowledges the ePeriphType when entering stop mode. + * @param ePeriphType the peripheral to enable or disable the stop mode ACK + * @param bEnable true: enable the stop mode ACK + * false: disable the stop mode ACK + * + * @return CSC_RetStatusType + * CSC_E_OK: The API is successfully called + * CSC_E_NOT_OK: eTargetCpuType invalid + * CSC_E_NO_PERM: Current CPU has no permission to access the register + */ +CSC_RetStatusType CSC_SetStopModeAckGrp1(CSC_WPB_CpuType eTargetCpuType, CSCx_Reg1_PeriphType ePeriphType, bool bEnable) +{ + CSC_RetStatusType eRetVal = CSC_E_NOT_OK; + CSC_WPB_CpuType eCtrlCpu; + + DEV_ASSERT((ePeriphType == CSC_STOPMODE_FLEXCAN3) || + (ePeriphType == CSC_STOPMODE_FLEXCAN2) || + (ePeriphType == CSC_STOPMODE_MSC0) || + (ePeriphType == CSC_STOPMODE_FCUART7) || + (ePeriphType == CSC_STOPMODE_FCUART6) || + (ePeriphType == CSC_STOPMODE_FCUART5) || + (ePeriphType == CSC_STOPMODE_FCUART4) || + (ePeriphType == CSC_STOPMODE_FCIIC1) || + (ePeriphType == CSC_STOPMODE_FCSPI5) || + (ePeriphType == CSC_STOPMODE_FCSPI4) || + (ePeriphType == CSC_STOPMODE_FCSPI3) || + (ePeriphType == CSC_STOPMODE_WDOG1)); + + if (CSC_WP_CPU_0 == eTargetCpuType) + { + eCtrlCpu = CSC0_HWA_MODER1_GetCpuWritePermit(); + + if((eCtrlCpu == CSC_GET_CPU_ID()) || (eCtrlCpu == CSC_WP_CPU_ALL)) + { + /* Set peripheral stop ack enable */ + if(bEnable != false) + { + CSC0_HWA_MODER1_EnableStopAck(ePeriphType); + } + else + { + CSC0_HWA_MODER1_DisableStopAck(ePeriphType); + } + eRetVal = CSC_E_OK; + } + else + { + eRetVal = CSC_E_NO_PERM; + } + } + + return eRetVal; +} + +/** + * @brief Set the stop request of peripheral group 1 in CSC. + * + * @param eTargetCpuType The target CPU which acknowledges the ePeriphType when entering stop mode. + * @param ePeriphType the peripheral to set stop request + * @param bEnable true: set the stop request + * false: clear the stop request + * + * @return CSC_RetStatusType + * CSC_E_OK: The API is successfully called + * CSC_E_NOT_OK: eTargetCpuType invalid + * CSC_E_NO_PERM: Current CPU has no permission to access the register + */ +CSC_RetStatusType CSC_SetStopRequestGrp1(CSC_WPB_CpuType eTargetCpuType, CSCx_Reg1_PeriphType ePeriphType, bool bEnable) +{ + CSC_RetStatusType eRetVal = CSC_E_NOT_OK; + CSC_WPB_CpuType eCtrlCpu; + + DEV_ASSERT((ePeriphType == CSC_STOPMODE_FLEXCAN3) || + (ePeriphType == CSC_STOPMODE_FLEXCAN2) || + (ePeriphType == CSC_STOPMODE_MSC0) || + (ePeriphType == CSC_STOPMODE_FCUART7) || + (ePeriphType == CSC_STOPMODE_FCUART6) || + (ePeriphType == CSC_STOPMODE_FCUART5) || + (ePeriphType == CSC_STOPMODE_FCUART4) || + (ePeriphType == CSC_STOPMODE_FCIIC1) || + (ePeriphType == CSC_STOPMODE_FCSPI5) || + (ePeriphType == CSC_STOPMODE_FCSPI4) || + (ePeriphType == CSC_STOPMODE_FCSPI3) || + (ePeriphType == CSC_STOPMODE_WDOG1)); + + if (CSC_WP_CPU_0 == eTargetCpuType) + { + eCtrlCpu = CSC0_HWA_REQR1_GetCpuWritePermit(); + + if((eCtrlCpu == CSC_GET_CPU_ID()) || (eCtrlCpu == CSC_WP_CPU_ALL)) + { + /* Set peripheral stop ack enable */ + if(bEnable != false) + { + CSC0_HWA_REQR1_SetStopRequest(ePeriphType); + } + else + { + CSC0_HWA_REQR1_ClearStopRequest(ePeriphType); + } + eRetVal = CSC_E_OK; + } + else + { + eRetVal = CSC_E_NO_PERM; + } + } + + return eRetVal; +} + +/** + * @brief Set the stop mode ACK of peripheral group 2 in CSC. + * + * @param eTargetCpuType The target CPU which acknowledges the ePeriphType when entering stop mode. + * @param ePeriphType the peripheral to enable or disable the stop mode ACK + * @param bEnable true: enable the stop mode ACK + * false: disable the stop mode ACK + * + * @return CSC_RetStatusType + * CSC_E_OK: The API is successfully called + * CSC_E_NOT_OK: eTargetCpuType invalid + * CSC_E_NO_PERM: Current CPU has no permission to access the register + */ +CSC_RetStatusType CSC_SetStopModeAckGrp2(CSC_WPB_CpuType eTargetCpuType, CSCx_Reg2_PeriphType ePeriphType, bool bEnable) +{ + CSC_RetStatusType eRetVal = CSC_E_NOT_OK; + CSC_WPB_CpuType eCtrlCpu; + + DEV_ASSERT((ePeriphType == CSC_STOPMODE_FCUART0) || + (ePeriphType == CSC_STOPMODE_FCIIC0) || + (ePeriphType == CSC_STOPMODE_FCSPI0) || + (ePeriphType == CSC_STOPMODE_CMP1) || + (ePeriphType == CSC_STOPMODE_CMP0) || + (ePeriphType == CSC_STOPMODE_CMU3) || + (ePeriphType == CSC_STOPMODE_CMU2) || + (ePeriphType == CSC_STOPMODE_CMU1) || + (ePeriphType == CSC_STOPMODE_CMU0)); + + if (CSC_WP_CPU_0 == eTargetCpuType) + { + eCtrlCpu = CSC0_HWA_MODER2_GetCpuWritePermit(); + + if((eCtrlCpu == CSC_GET_CPU_ID()) || (eCtrlCpu == CSC_WP_CPU_ALL)) + { + /* Set peripheral stop ack enable */ + if(bEnable != false) + { + CSC0_HWA_MODER2_EnableStopAck(ePeriphType); + } + else + { + CSC0_HWA_MODER2_DisableStopAck(ePeriphType); + } + eRetVal = CSC_E_OK; + } + else + { + eRetVal = CSC_E_NO_PERM; + } + } + + return eRetVal; +} + +/** + * @brief Set the stop request of peripheral group 2 in CSC. + * + * @param eTargetCpuType The target CPU which acknowledges the ePeriphType when entering stop mode. + * @param ePeriphType the peripheral to set stop request + * @param bEnable true: set the stop request + * false: clear the stop request + * + * @return CSC_RetStatusType + * CSC_E_OK: The API is successfully called + * CSC_E_NOT_OK: eTargetCpuType invalid + * CSC_E_NO_PERM: Current CPU has no permission to access the register + */ +CSC_RetStatusType CSC_SetStopRequestGrp2(CSC_WPB_CpuType eTargetCpuType, CSCx_Reg2_PeriphType ePeriphType, bool bEnable) +{ + CSC_RetStatusType eRetVal = CSC_E_NOT_OK; + CSC_WPB_CpuType eCtrlCpu; + + DEV_ASSERT((ePeriphType == CSC_STOPMODE_FCUART0) || + (ePeriphType == CSC_STOPMODE_FCIIC0) || + (ePeriphType == CSC_STOPMODE_FCSPI0) || + (ePeriphType == CSC_STOPMODE_CMP1) || + (ePeriphType == CSC_STOPMODE_CMP0) || + (ePeriphType == CSC_STOPMODE_CMU3) || + (ePeriphType == CSC_STOPMODE_CMU2) || + (ePeriphType == CSC_STOPMODE_CMU1) || + (ePeriphType == CSC_STOPMODE_CMU0)); + + if (CSC_WP_CPU_0 == eTargetCpuType) + { + eCtrlCpu = CSC0_HWA_REQR2_GetCpuWritePermit(); + + if((eCtrlCpu == CSC_GET_CPU_ID()) || (eCtrlCpu == CSC_WP_CPU_ALL)) + { + /* Set peripheral stop ack enable */ + if(bEnable != false) + { + CSC0_HWA_REQR2_SetStopRequest(ePeriphType); + } + else + { + CSC0_HWA_REQR2_ClearStopRequest(ePeriphType); + } + eRetVal = CSC_E_OK; + } + else + { + eRetVal = CSC_E_NO_PERM; + } + } + + return eRetVal; +} + +/** + * @brief Set the stop mode ACK of all group peripherals in CSC. + * + * @param eTargetCpuType The target CPU which acknowledges the peripherals when entering stop mode. + * @param ePeriphGrp the group of peripherals to set the stop mode ACK value + * @param u32Value the CSCx_STOP_MODERx register value + * + * @return CSC_RetStatusType + * CSC_E_OK: The API is successfully called + * CSC_E_NOT_OK: eTargetCpuType invalid + * CSC_E_PARAM: ePeriphGrp or u32Value invalid + * CSC_E_NO_PERM: Current CPU has no permission to access the register + */ +CSC_RetStatusType CSC_SetStopModeAck(CSC_WPB_CpuType eTargetCpuType, CSC_PeriphGrpType ePeriphGrp, uint32_t u32Value) +{ + CSC_RetStatusType eRetVal = CSC_E_NOT_OK; + uint32_t eGrpMask[CSC_STOP_PERIPH_GROUP_MAX] = {CSC_STOP_PERIPH_GROUP0_MASK, + CSC_STOP_PERIPH_GROUP1_MASK, + CSC_STOP_PERIPH_GROUP2_MASK + }; + + if((uint32_t)ePeriphGrp >= (uint32_t)CSC_STOP_PERIPH_GROUP_MAX) + { + eRetVal = CSC_E_PARAM; + } + else if(((~eGrpMask[(uint32_t)ePeriphGrp]) & u32Value) != 0U) + { + eRetVal = CSC_E_PARAM; + } + else + { + if (CSC_WP_CPU_0 == eTargetCpuType) + { + eRetVal = CSC0_SetStopModeAck(ePeriphGrp,u32Value); + } + } + + return eRetVal; +} + +/** + * @brief Set the stop request of all group peripherals in CSC. + * + * @param eTargetCpuType The target CPU which acknowledges the peripherals when entering stop mode. + * @param ePeriphGrp the group of peripherals to set the stop request value + * @param u32Value the CSCx_STOP_REQRx register value + * + * @return CSC_RetStatusType + * CSC_E_OK: The API is successfully called + * CSC_E_NOT_OK: eTargetCpuType invalid + * CSC_E_PARAM: ePeriphGrp or u32Value invalid + * CSC_E_NO_PERM: Current CPU has no permission + */ +CSC_RetStatusType CSC_SetStopRequest(CSC_WPB_CpuType eTargetCpuType, CSC_PeriphGrpType ePeriphGrp, uint32_t u32Value) +{ + CSC_RetStatusType eRetVal = CSC_E_NOT_OK; + uint32_t eGrpMask[CSC_STOP_PERIPH_GROUP_MAX] = {CSC_STOP_PERIPH_GROUP0_MASK, + CSC_STOP_PERIPH_GROUP1_MASK, + CSC_STOP_PERIPH_GROUP2_MASK + }; + + if((uint32_t)ePeriphGrp >= (uint32_t)CSC_STOP_PERIPH_GROUP_MAX) + { + eRetVal = CSC_E_PARAM; + } + else if(((~eGrpMask[(uint32_t)ePeriphGrp]) & u32Value) != 0U) + { + eRetVal = CSC_E_PARAM; + } + else + { + if (CSC_WP_CPU_0 == eTargetCpuType) + { + eRetVal = CSC0_SetStopRequest(ePeriphGrp,u32Value); + } + } + + return eRetVal; +} + +/** + * @brief Get the stop Acknowledge status of peripherals group0 in CSC. + * + * @param eTargetCpuType The target CPU which acknowledges the peripherals when entering stop mode. + * @param ePeriphType the peripheral to get stop acknowledge status + * @param bool true: Stop acknowledge is asserted (the module is in Stop mode) + * false: Stop acknowledge is not asserted + * @return Operation success/failed + */ +CSC_RetStatusType CSC_GetStopAckStatusGrp0(CSC_WPB_CpuType eTargetCpuType,CSCx_Reg0_PeriphType ePeriphType, bool * const pStatus) +{ + CSC_RetStatusType eRetVal = CSC_E_NOT_OK; + DEV_ASSERT((ePeriphType == CSC_STOPMODE_FLEXCAN1) || + (ePeriphType == CSC_STOPMODE_FLEXCAN0) || + (ePeriphType == CSC_STOPMODE_FREQM) || + (ePeriphType == CSC_STOPMODE_FCUART3) || + (ePeriphType == CSC_STOPMODE_FCUART2) || + (ePeriphType == CSC_STOPMODE_FCUART1) || + (ePeriphType == CSC_STOPMODE_FCSPI2) || + (ePeriphType == CSC_STOPMODE_FCSPI1) || + (ePeriphType == CSC_STOPMODE_SENT0) || + (ePeriphType == CSC_STOPMODE_TMU) || + (ePeriphType == CSC_STOPMODE_ADC1) || + (ePeriphType == CSC_STOPMODE_ADC0) || + (ePeriphType == CSC_STOPMODE_CMU4) || + (ePeriphType == CSC_STOPMODE_WDOG0) || + (ePeriphType == CSC_STOPMODE_ISM0) || + (ePeriphType == CSC_STOPMODE_DMA0)); + + if (CSC_WP_CPU_0 == eTargetCpuType) + { + *pStatus = (bool)(0U != CSC0_HWA_ACKR0_GetStopAckStatus(ePeriphType)); + eRetVal = CSC_E_OK; + } + return eRetVal; +} + +/** + * @brief Get the stop Acknowledge status of peripherals group1 in CSC. + * + * @param eTargetCpuType The target CPU which acknowledges the peripherals when entering stop mode. + * @param ePeriphType the peripheral to get stop acknowledge status + * @param bool true: Stop acknowledge is asserted (the module is in Stop mode) + * false: Stop acknowledge is not asserted + * @return Operation success/failed + */ +CSC_RetStatusType CSC_GetStopAckStatusGrp1(CSC_WPB_CpuType eTargetCpuType, CSCx_Reg1_PeriphType ePeriphType, bool * const pStatus) +{ + CSC_RetStatusType eRetVal = CSC_E_NOT_OK; + DEV_ASSERT((ePeriphType == CSC_STOPMODE_FLEXCAN3) || + (ePeriphType == CSC_STOPMODE_FLEXCAN2) || + (ePeriphType == CSC_STOPMODE_MSC0) || + (ePeriphType == CSC_STOPMODE_FCUART7) || + (ePeriphType == CSC_STOPMODE_FCUART6) || + (ePeriphType == CSC_STOPMODE_FCUART5) || + (ePeriphType == CSC_STOPMODE_FCUART4) || + (ePeriphType == CSC_STOPMODE_FCIIC1) || + (ePeriphType == CSC_STOPMODE_FCSPI5) || + (ePeriphType == CSC_STOPMODE_FCSPI4) || + (ePeriphType == CSC_STOPMODE_FCSPI3) || + (ePeriphType == CSC_STOPMODE_WDOG1)); + + if (CSC_WP_CPU_0 == eTargetCpuType) + { + *pStatus = (bool)(0U != CSC0_HWA_ACKR1_GetStopAckStatus(ePeriphType)); + eRetVal = CSC_E_OK; + } + return eRetVal; +} + +/** + * @brief Get the stop Acknowledge status of peripherals group2 in CSC. + * + * @param eTargetCpuType The target CPU which acknowledges the peripherals when entering stop mode. + * @param ePeriphType the peripheral to get stop acknowledge status + * @param bool true: Stop acknowledge is asserted (the module is in Stop mode) + * false: Stop acknowledge is not asserted + * @return Operation success/failed + */ +CSC_RetStatusType CSC_GetStopAckStatusGrp2(CSC_WPB_CpuType eTargetCpuType,CSCx_Reg2_PeriphType ePeriphType, bool * const pStatus) +{ + CSC_RetStatusType eRetVal = CSC_E_NOT_OK; + DEV_ASSERT((ePeriphType == CSC_STOPMODE_FCUART0) || + (ePeriphType == CSC_STOPMODE_FCIIC0) || + (ePeriphType == CSC_STOPMODE_FCSPI0) || + (ePeriphType == CSC_STOPMODE_CMP1) || + (ePeriphType == CSC_STOPMODE_CMP0) || + (ePeriphType == CSC_STOPMODE_CMU3) || + (ePeriphType == CSC_STOPMODE_CMU2) || + (ePeriphType == CSC_STOPMODE_CMU1) || + (ePeriphType == CSC_STOPMODE_CMU0)); + + if (CSC_WP_CPU_0 == eTargetCpuType) + { + *pStatus = (bool)(0U != CSC0_HWA_ACKR2_GetStopAckStatus(ePeriphType)); + eRetVal = CSC_E_OK; + } + return eRetVal; +} + +/** + * @brief Get the stop Acknowledge status of all group peripherals in CSC. + * + * @param eTargetCpuType The target CPU which acknowledges the peripherals when entering stop mode. + * @param ePeriphType the peripheral to get stop acknowledge status + * @param pU32Status Output parameter,to save the stop ACK status of all the peripherals in the group indicated by ePeriphGrp. + * The corresponding bit is 1, indicates that stop acknowledge is asserted,and 0 not asserted. + * @return CSC_RetStatusType Operation success/failed + * CSC_E_OK: The API is successfully called + * CSC_E_NOT_OK: eTargetCpuType invalid + */ +CSC_RetStatusType CSC_GetStopAckStatus(CSC_WPB_CpuType eTargetCpuType,CSC_PeriphGrpType ePeriphGrp, uint32_t * const pU32Status) +{ + CSC_RetStatusType eRetVal = CSC_E_NOT_OK; + DEV_ASSERT((uint32_t)ePeriphGrp <= (uint32_t)CSC_STOP_CTRL_GROUP_2); + + if (CSC_WP_CPU_0 == eTargetCpuType) + { + *pU32Status = CSC0_GetStopAckStatus(ePeriphGrp); + eRetVal = CSC_E_OK; + } + return eRetVal; +} + +/** + * @brief Set the CPU write permission of CSCx_CCMx_CFG register in CSC. + * + * @param eTargetCpuType The target CPU controlled by CSCx_CCMx_CFG register. + * @param eCtrlCpuType The CPU that has the permission to access the CSCx_CCMx_CFG register. + * @param bLockStatus Lock the WPB of CSCx_CCMx_CFG register.Once locked, calling the API returns an error(CSC_E_LOCK). + * + * @return CSC_RetStatusType + * CSC_E_OK: The API is successfully called + * CSC_E_NOT_OK: eTargetCpuType invalid + * CSC_E_LOCK: WPB is locked(WPB_LOCK set 1) and can not be written + */ +CSC_RetStatusType CSC_SetCCMCfgPermission(CSC_WPB_CpuType eTargetCpuType, CSC_WPB_CpuType eCtrlCpuType, bool bLockStatus) +{ + CSC_RetStatusType eRetVal = CSC_E_NOT_OK; + DEV_ASSERT((uint32_t)eCtrlCpuType < (uint32_t)CSC_WP_CPU_NONE); + + if (CSC_WP_CPU_0 == eTargetCpuType) + { + if (0U == CSC0_HWA_CCM0_GetWPBLockStatus()) + { + CSC0_HWA_CCM0_SetCpuWritePermit(eCtrlCpuType); + + if(bLockStatus != false) + { + CSC0_HWA_CCM0_LockWritePermit(); + } + eRetVal = CSC_E_OK; + } + else + { + eRetVal = CSC_E_LOCK; + } + } + return eRetVal; +} + +/** + * @brief Set the CCM configuration of CPUx indicated by eTargetCpuType. + * + * @param eTargetCpuType The target CPU controlled by CSCx_CCMx_CFG register. + * @param pCCMCfg Pointer to the configuration of CSCx_CCMx_CFG register. + * + * @return CSC_RetStatusType + * CSC_E_OK: The API is successfully called + * CSC_E_NOT_OK: eTargetCpuType invalid + * CSC_E_LOCK: Current CPU has no permission + */ +CSC_RetStatusType CSC_SetCCMConfiguration(CSC_WPB_CpuType eTargetCpuType,const CSC_CCMCfgType *const pCCMCfg) +{ + CSC_RetStatusType eRetVal = CSC_E_NOT_OK; + CSC_WPB_CpuType eCtrlCpu; + + DEV_ASSERT(pCCMCfg != NULL_PTR); + DEV_ASSERT(pCCMCfg->eHandShakeMode == CSC_WAIT_ALL_ACK || + pCCMCfg->eHandShakeMode == CSC_WAIT_REQ_ACK); + + if (CSC_WP_CPU_0 == eTargetCpuType) + { + eCtrlCpu = CSC0_HWA_CCM0_GetCpuWritePermit(); + + if((eCtrlCpu == CSC_GET_CPU_ID()) || (eCtrlCpu == CSC_WP_CPU_ALL)) + { + CSC0_HWA_HClockEnable(pCCMCfg->HclkEn); + CSC0_HWA_SetHandShakeMode(pCCMCfg->eHandShakeMode); + eRetVal = CSC_E_OK; + } + else + { + eRetVal = CSC_E_LOCK; + } + } + return eRetVal; +} + +/** + * @brief Get the CCM stop clock status. + * + * @param eTargetCpuType The target CPU controlled by CSCx_CCMx_CFG register. + * @param eCCMType CCM stop clock type. + * @param pStatus Pointer to memory to save the clock status. + * + * @return CSC_RetStatusType + * CSC_E_OK: The API is successfully called + * CSC_E_NOT_OK: eTargetCpuType invalid + */ +CSC_RetStatusType CSC_GetCCMStopClockStatus(CSC_WPB_CpuType eTargetCpuType, CSCx_CCM_StopClockType eCCMType, bool * const pStatus) +{ + CSC_RetStatusType eRetVal = CSC_E_NOT_OK; + + DEV_ASSERT(pStatus != NULL_PTR); + DEV_ASSERT(eCCMType == CSC_CCM_STOPCLOCK_STATUS_SYS_SLAVE || + eCCMType == CSC_CCM_STOPCLOCK_STATUS_MASTER || + eCCMType == CSC_CCM_STOPCLOCK_STATUS_SLOW_SLAVE || + eCCMType == CSC_CCM_STOPCLOCK_STATUS_BUS_SLAVE); + + if (CSC_WP_CPU_0 == eTargetCpuType) + { + *pStatus = (bool)(0u != CSC0_HWA_CCM0_GetClockStatus(eCCMType)); + eRetVal = CSC_E_OK; + } + return eRetVal; +} + +/** + * @brief Set the CPU write permission of CSCx_CPUx_INT register in CSC. + * + * @param eTargetCpuType The target CPU controlled by CSCx_CPUx_INT register. + * @param eCtrlCpuType The CPU that has the permission to access the CSCx_CPUx_INT register. + * @param bLockStatus Lock the WPB of CSCx_CPUx_INT register.Once locked, calling the API returns an error(CSC_E_LOCK). + * + * @return CSC_RetStatusType + * CSC_E_OK: The API is successfully called + * CSC_E_NOT_OK: eTargetCpuType invalid + * CSC_E_LOCK: WPB is locked(WPB_LOCK set 1) and can not be written + */ +CSC_RetStatusType CSC_SetCpuIntPermission(CSC_WPB_CpuType eTargetCpuType, CSC_WPB_CpuType eCtrlCpuType, bool bLockStatus) +{ + CSC_RetStatusType eRetVal = CSC_E_NOT_OK; + DEV_ASSERT((uint32_t)eCtrlCpuType < (uint32_t)CSC_WP_CPU_NONE); + + if (CSC_WP_CPU_0 == eTargetCpuType) + { + if (0U == CSC0_HWA_CPU0INT_GetWPBLockStatus()) + { + CSC0_HWA_CPU0INT_SetCpuWritePermit(eCtrlCpuType); + + if(bLockStatus != false) + { + CSC0_HWA_CPU0INT_LockWritePermit(); + } + eRetVal = CSC_E_OK; + } + else + { + eRetVal = CSC_E_LOCK; + } + } + return eRetVal; +} + +/** + * @brief Generate software interrupt via CSCx_CPUx_INT. + * + * @param eTargetCpuType The target CPU to generate interrupt. + * @param bEnable true: Generate software interrupt. + * false: Do not generate software interrupt. + * + * @return CSC_RetStatusType + * CSC_E_OK: The API is successfully called + * CSC_E_NOT_OK: eTargetCpuType invalid + * CSC_E_LOCK: The current CPU has no permission to access this bit + */ +CSC_RetStatusType CSC_CpuSwInterruptGen(CSC_WPB_CpuType eTargetCpuType, bool bEnable) +{ + CSC_RetStatusType eRetVal = CSC_E_NOT_OK; + CSC_WPB_CpuType eCtrlCpu; + + if (CSC_WP_CPU_0 == eTargetCpuType) + { + eCtrlCpu = CSC0_HWA_CPU0INT_GetCpuWritePermit(); + + if((eCtrlCpu == CSC_GET_CPU_ID()) || (eCtrlCpu == CSC_WP_CPU_ALL)) + { + if(bEnable != false) + { + CSC0_HWA_CPU0INT_EnableSWInterrupt(); + } + else + { + CSC0_HWA_CPU0INT_DisableSWInterrupt(); + } + eRetVal = CSC_E_OK; + } + else + { + eRetVal = CSC_E_LOCK; + } + } + return eRetVal; +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_dma.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_dma.c new file mode 100644 index 0000000..76882f4 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_dma.c @@ -0,0 +1,818 @@ +/** + * @file fc7xxx_driver_dma.c + * @author Flagchip0126 + * @brief FC7xxx DMA driver source code + * @version 0.1.0 + * @date 2024-01-15 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Author CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-15 Flagchip0126 N/A First version for FC7240 + ******************************************************************************** */ + +#include "fc7xxx_driver_dma.h" +#include "interrupt_manager.h" + +#define DMA_CHANNEL_INVALID (0xFFU) + +#define CPM_CORE_ID_CORE0 (0x0U) +#define CPM_CORE_ID_CORE1 (0x2U) +#define CPM_CORE_ID_CORE2 (0x4U) + +static uint8_t s_aDmaDumoUsedStatus[DMA_DUMO_COUNT] = {DMA_CHANNEL_INVALID, DMA_CHANNEL_INVALID, DMA_CHANNEL_INVALID, DMA_CHANNEL_INVALID}; + +static DMA_TransferCompleteCallbackType s_dmaTransferCompleteNotify[DMA_INSTANCE_COUNT][DMA_CFG_COUNT] = {NULL}; +static DMA_TransferErrorCallbackType s_dmaTransferErrorNotify[DMA_INSTANCE_COUNT][DMA_CFG_COUNT] = {NULL}; + +/** + * @brief DMA IRQ function prototypes + * + */ +void DMA0_IRQHandler(void); +void DMA1_IRQHandler(void); +void DMA2_IRQHandler(void); +void DMA3_IRQHandler(void); +void DMA4_IRQHandler(void); +void DMA5_IRQHandler(void); +void DMA6_IRQHandler(void); +void DMA7_IRQHandler(void); +void DMA8_IRQHandler(void); +void DMA9_IRQHandler(void); +void DMA10_IRQHandler(void); +void DMA11_IRQHandler(void); +void DMA12_IRQHandler(void); +void DMA13_IRQHandler(void); +void DMA14_IRQHandler(void); +void DMA15_IRQHandler(void); +void DMA_Error_IRQHandler(void); + + +/** + * @brief Get the first unused DUMO register index + * + * @param [out] pDumoIndex the DUMO register index + * @return DMA_StatusType whether there is unused DUMO index + * @return DMA_STATUS_SUCCESS the DUMO register index is successfully get + * @return DMA_STATUS_NO_RESOURCE all DUMO registers are already occupied + */ +static inline DMA_StatusType DMA_GetDumoIndex(uint8_t *pDumoIndex); + +/** + * @brief Check whether the value is power of 2 and return the ceil value of the log2(u32Value) + * + * @param [in] u32Value the value to check + * @param [out] u8Log2 the ceil value of log2(u32Value) + * @return true the u32Value is power of 2 + * @return false the u32Value is not power of 2 + */ +static bool DMA_IsPowerOf2(uint32_t u32Value, uint8_t *u8Log2); + +/** + * @brief Reset the DMAMUX config values + * @param Dmamux_Instance the selected DMA Instance + * + */ +static inline void Dmamux_Reset(DMAMUX_Type * const Dmamux_Instance); + +/** + * @brief Get the data offset value of the selected increment mode and data size + * + * @param eIncMode the selected increment mode + * @param eDataSize the selected data size + * @return int16_t the calculated data offset + */ +static inline uint16_t DMA_GetDataOffset(DMA_IncrementModeType eIncMode, + DMA_TransferSizeType eDataSize); + +/** + * @brief Get the IRQ number of the selected DMA channel + * + * @param u8Channel the selected DMA channel + * @return IRQn_Type the IRQ number of the selected DMA channel + */ +//static inline IRQn_Type DMA_GetChannelIRQn(const DMA_InstanceType eDma_Instance); + +/** + * @brief The internal interrupt handler for DMA transfer complete + * + * @param u8Channel the channel of the DMA interrpt + */ +static inline void DMA_Transfer_Complete_IRQHandler(const DMA_InstanceType eDma_Instance, const DMA_ChannelType eChannel); + +static inline DMA_StatusType DMA_GetDumoIndex(uint8_t *pDumoIndex) +{ + DMA_StatusType ret = DMA_STATUS_ERROR; + for (*pDumoIndex = 0U; *pDumoIndex < DMA_DUMO_COUNT; (*pDumoIndex)++) + { + if (s_aDmaDumoUsedStatus[*pDumoIndex] == DMA_CHANNEL_INVALID) + { + ret = DMA_STATUS_SUCCESS; + break; + } + } + if (*pDumoIndex == DMA_DUMO_COUNT) + { + ret = DMA_STATUS_NO_RESOURCE; + } + return ret; +} + +static bool DMA_IsPowerOf2(uint32_t u32Value, uint8_t *u8Log2) +{ + bool ret = (bool)false; + *u8Log2 = 0U; + while (u32Value > (1UL << *u8Log2)) + { + (*u8Log2)++; + } + if ((u32Value & ((1UL << *u8Log2) - 1U)) == 0U) + { + ret = (bool)true; + } + return ret; +} + +static inline uint16_t DMA_GetDataOffset(DMA_IncrementModeType eIncMode, + DMA_TransferSizeType eDataSize) +{ + uint16_t u16DataOffset = 0U; + switch (eIncMode) + { + case DMA_INCREMENT_DISABLE: + { + u16DataOffset = 0U; + break; + } + + case DMA_INCREMENT_DATA_SIZE: + { + u16DataOffset = (uint16_t)(1UL << ((uint8_t)eDataSize)); + break; + } + + case DMA_INCREMENT_DATA_SIZE_4BYTE_ALIGNED: + { + switch (eDataSize) + { + case DMA_TRANSFER_SIZE_1B: + case DMA_TRANSFER_SIZE_2B: + case DMA_TRANSFER_SIZE_4B: + u16DataOffset = 4U; + break; + + case DMA_TRANSFER_SIZE_8B: + u16DataOffset = 8U; + break; + + case DMA_TRANSFER_SIZE_32B: + u16DataOffset = 32U; + break; + + default: + break; + } + break; + } + + default: + break; + } + return u16DataOffset; +} + +void DMA0_IRQHandler(void) +{ + DMA_Transfer_Complete_IRQHandler(DMA_INSTANCE_0, DMA_CHANNEL_0); +} + +void DMA1_IRQHandler(void) +{ + DMA_Transfer_Complete_IRQHandler(DMA_INSTANCE_0, DMA_CHANNEL_1); +} + +void DMA2_IRQHandler(void) +{ + DMA_Transfer_Complete_IRQHandler(DMA_INSTANCE_0, DMA_CHANNEL_2); +} + +void DMA3_IRQHandler(void) +{ + DMA_Transfer_Complete_IRQHandler(DMA_INSTANCE_0, DMA_CHANNEL_3); +} + +void DMA4_IRQHandler(void) +{ + DMA_Transfer_Complete_IRQHandler(DMA_INSTANCE_0, DMA_CHANNEL_4); +} + +void DMA5_IRQHandler(void) +{ + DMA_Transfer_Complete_IRQHandler(DMA_INSTANCE_0, DMA_CHANNEL_5); +} + +void DMA6_IRQHandler(void) +{ + DMA_Transfer_Complete_IRQHandler(DMA_INSTANCE_0, DMA_CHANNEL_6); +} + +void DMA7_IRQHandler(void) +{ + DMA_Transfer_Complete_IRQHandler(DMA_INSTANCE_0, DMA_CHANNEL_7); +} + +void DMA8_IRQHandler(void) +{ + DMA_Transfer_Complete_IRQHandler(DMA_INSTANCE_0, DMA_CHANNEL_8); +} + +void DMA9_IRQHandler(void) +{ + DMA_Transfer_Complete_IRQHandler(DMA_INSTANCE_0, DMA_CHANNEL_9); +} + +void DMA10_IRQHandler(void) +{ + DMA_Transfer_Complete_IRQHandler(DMA_INSTANCE_0, DMA_CHANNEL_10); +} + +void DMA11_IRQHandler(void) +{ + DMA_Transfer_Complete_IRQHandler(DMA_INSTANCE_0, DMA_CHANNEL_11); +} + +void DMA12_IRQHandler(void) +{ + DMA_Transfer_Complete_IRQHandler(DMA_INSTANCE_0, DMA_CHANNEL_12); +} + +void DMA13_IRQHandler(void) +{ + DMA_Transfer_Complete_IRQHandler(DMA_INSTANCE_0, DMA_CHANNEL_13); +} + +void DMA14_IRQHandler(void) +{ + DMA_Transfer_Complete_IRQHandler(DMA_INSTANCE_0, DMA_CHANNEL_14); +} + +void DMA15_IRQHandler(void) +{ + DMA_Transfer_Complete_IRQHandler(DMA_INSTANCE_0, DMA_CHANNEL_15); +} + +void DMA_Error_IRQHandler(void) +{ + uint8_t u8Channel; + DMA_InstanceType eDma_Instance; + DMA_Type *pDma; + DMA_Type * aDma[] = DMA_BASE_PTRS; + + eDma_Instance = DMA_INSTANCE_0; + + pDma = aDma[DMA_INSTANCE_0]; + for (u8Channel = 0U; u8Channel < DMA_CFG_COUNT; u8Channel++) + { + if (DMA_HWA_GetChannelErrorFlag(pDma, u8Channel) == true) + { + DMA_HWA_ClearChannelErrorFlag(pDma, u8Channel); + if (s_dmaTransferErrorNotify[eDma_Instance][u8Channel] != NULL) + { + s_dmaTransferErrorNotify[eDma_Instance][u8Channel](); + } + } + } +} + +static inline void DMA_Transfer_Complete_IRQHandler(const DMA_InstanceType eDma_Instance, const DMA_ChannelType eChannel) +{ + DMA_Type * aDma[] = DMA_BASE_PTRS; + DMA_Type *const pDma = aDma[eDma_Instance]; + + DMA_HWA_ClearChannelInterruptFlag(pDma, (uint8_t)eChannel); + if (s_dmaTransferCompleteNotify[eDma_Instance][eChannel] != NULL) + { + s_dmaTransferCompleteNotify[eDma_Instance][eChannel](); + } +} + +static inline void Dmamux_Reset(DMAMUX_Type * const Dmamux_Instance) +{ + uint8_t u8Index; + for (u8Index = 0U; u8Index < DMAMUX_CHCFG_COUNT; u8Index++) + { + DMAMUX_HWA_SetRequestSource(Dmamux_Instance, u8Index, false, DMA_REQ_DISABLED); + } + for (u8Index = 0U; u8Index < DMAMUX_CHTRG_TRG_COUNT; u8Index++) + { + //DMAMUX_HWA_SetPeriodicTrigFlag(Dmamux_Instance, u8Index, false); + } +} + +void DMA_Init(const DMA_InstanceType eDma_Instance, const DMA_InitType *const pInitCfg) +{ + DEV_ASSERT(eDma_Instance < DMA_INSTANCE_MAX); + DEV_ASSERT(pInitCfg != NULL); + + DMA_Type * aDma[] = DMA_BASE_PTRS; + DMA_Type *const pDma = aDma[eDma_Instance]; + + DMA_DeInit(eDma_Instance); + DMA_HWA_SetHaltOnErrorFlag(pDma, pInitCfg->bHaltOnError); + DMA_HWA_SetArbitrationAlgorithm(pDma, pInitCfg->eArbitrationAlgorithm); + DMA_HWA_SetInnerLoopMappingEnableFlag(pDma, true); +} + +void DMA_DeInit(const DMA_InstanceType eDma_Instance) +{ + DEV_ASSERT(eDma_Instance < DMA_INSTANCE_MAX); + + uint8_t u8Index; + DMA_Type * aDma[] = DMA_BASE_PTRS; + DMA_Type *const pDma = aDma[eDma_Instance]; + DMAMUX_Type * aDmamux[] = DMAMUX_BASE_PTRS; + DMAMUX_Type *const pDmamux = aDmamux[eDma_Instance]; + + DMA_HWA_SetControlRegister(pDma, 0U); + DMA_HWA_DisableAllChannelErrorInterrupt(pDma); + DMA_HWA_DisableAllChannelRequest(pDma); + DMA_HWA_ClearAllChannelDoneStatus(pDma); + DMA_HWA_ClearAllChannelErrorFlag(pDma); + DMA_HWA_ClearAllChannelInterruptFlag(pDma); + pDma->DUME[0] = 0U; + for (u8Index = 0U; u8Index < DMA_DUMO_COUNT; u8Index++) + { + DMA_HWA_SetUnalignModulo(pDma, u8Index, 0U, 0U); + } + for (u8Index = 0U; u8Index < DMA_CFG_COUNT; u8Index++) + { + DMA_HWA_SetUnalignModuloEnableFlag(pDma, u8Index, false, false); + DMA_HWA_SetPriority(pDma, u8Index, u8Index); + DMA_HWA_SetSrcAddr(pDma, u8Index, 0U); + DMA_HWA_SetSrcOffset(pDma, u8Index, 0); + DMA_HWA_SetSrcLastAddrAdjustment(pDma, u8Index, 0); + DMA_HWA_SetDestAddr(pDma, u8Index, 0U); + DMA_HWA_SetDestOffset(pDma, u8Index, 0); + DMA_HWA_SetDestLastAddrAdjustment(pDma, u8Index, 0); + DMA_HWA_SetSrcDataSize(pDma, u8Index, DMA_TRANSFER_SIZE_1B); + DMA_HWA_SetSrcModulo(pDma, u8Index, 0U); + DMA_HWA_SetDestDataSize(pDma, u8Index, DMA_TRANSFER_SIZE_1B); + DMA_HWA_SetDestModulo(pDma, u8Index, 0U); + DMA_HWA_SetInnerLoopSize(pDma, u8Index, 0U); + DMA_HWA_SetChannelControlStatus(pDma, u8Index, 0U); + DMA_HWA_SetChannelToChannelTrig(pDma, u8Index, false, 0U); + DMA_HWA_SetLoopCount(pDma, u8Index, 0U); + } + Dmamux_Reset(pDmamux); + +} + +DMA_StatusType DMA_InitChannel(const DMA_InstanceType eDma_Instance, const DMA_ChannelType eChannel, const DMA_ChannelCfgType *const pChnCfg) +{ + DEV_ASSERT(eDma_Instance < DMA_INSTANCE_MAX); + DEV_ASSERT(eChannel < DMA_CHANNEL_MAX); + DEV_ASSERT(pChnCfg != NULL); + DEV_ASSERT(pChnCfg->u16BlockCount > 0U); + DEV_ASSERT(pChnCfg->u32BlockSize > 0U); + DEV_ASSERT(((pChnCfg->u32BlockSize >> pChnCfg->eSrcDataSize) << pChnCfg->eSrcDataSize == pChnCfg->u32BlockSize) && + ((pChnCfg->u32BlockSize >> pChnCfg->eDestDataSize) << pChnCfg->eDestDataSize == pChnCfg->u32BlockSize)); + + DMA_Type * aDma[] = DMA_BASE_PTRS; + DMA_Type *const pDma = aDma[eDma_Instance]; + DMAMUX_Type * aDmamux[] = DMAMUX_BASE_PTRS; + DMAMUX_Type *const pDmamux = aDmamux[eDma_Instance]; + + DMA_StatusType ret; + + uint16_t u16SrcDataOffset = DMA_GetDataOffset(pChnCfg->eSrcIncMode, pChnCfg->eSrcDataSize); + uint16_t u16DestDataOffset = DMA_GetDataOffset(pChnCfg->eDestIncMode, pChnCfg->eDestDataSize); + + int32_t s32SrcLastOffset; + int32_t s32DestLastOffset; + + uint8_t u8SrcMod = 0U; + uint8_t u8DestMod = 0U; + + bool bUseSrcDumo = (bool)false; + bool bUseDestDumo = (bool)false; + uint8_t u8DumoIndex = 0U; + uint16_t u16Sumo = 0U; + uint16_t u16Dumo = 0U; + + if ((pChnCfg->bSrcCircularBufferEn == true) || (pChnCfg->bDestCircularBufferEn == true)) + { + /* If the circular buffer size is not power of 2 aligned, need to use the DUMO */ + if (pChnCfg->bSrcCircularBufferEn == true) + { + DEV_ASSERT(pChnCfg->u32SrcCircBufferSize != 0U); + bUseSrcDumo = (bool)(DMA_IsPowerOf2(pChnCfg->u32SrcCircBufferSize, &u8SrcMod) ? false : true); + } + if (pChnCfg->bDestCircularBufferEn == true) + { + DEV_ASSERT(pChnCfg->u32DestCircBufferSize != 0U); + bUseDestDumo = (bool)(DMA_IsPowerOf2(pChnCfg->u32DestCircBufferSize, &u8DestMod) ? false : true); + } + + /* If circular buffer is enabled, the buffer address must be power of 2 aligned */ + if (((pChnCfg->bSrcCircularBufferEn == true) && + (((uint32_t)pChnCfg->pSrcBuffer & ((1UL << u8SrcMod) - 1U)) != 0U)) || + ((pChnCfg->bDestCircularBufferEn == true) && + (((uint32_t)pChnCfg->pDestBuffer & ((1UL << u8DestMod) - 1U)) != 0U))) + { + ret = DMA_STATUS_INVALID_ADDRESS; + } + /* If circular buffer is enabled, the buffer size must not less than the data offset */ + else if (((pChnCfg->bSrcCircularBufferEn == true) && + (pChnCfg->u32SrcCircBufferSize < u16SrcDataOffset)) || + ((pChnCfg->bDestCircularBufferEn == true) && + (pChnCfg->u32DestCircBufferSize < u16SrcDataOffset))) + { + ret = DMA_STATUS_UNSUPPORTED; + } + /* If source or destination unalign modulo is used, check whether all DUMO registers are occupied */ + else if ((bUseSrcDumo == true) || (bUseDestDumo == true)) + { + ret = DMA_GetDumoIndex(&u8DumoIndex); + if (ret == DMA_STATUS_SUCCESS) + { + s_aDmaDumoUsedStatus[u8DumoIndex] = (uint8_t)eChannel; + } + } + else + { + ret = DMA_STATUS_SUCCESS; + } + } + else + { + ret = DMA_STATUS_SUCCESS; + } + + if (ret == DMA_STATUS_SUCCESS) + { + if (pChnCfg->bSrcAddrLoopbackEn == true) + { + if (pChnCfg->bSrcBlockOffsetEn == false) + { + s32SrcLastOffset = -((int32_t)((pChnCfg->u32BlockSize >> pChnCfg->eSrcDataSize) * u16SrcDataOffset) * + (int32_t)(pChnCfg->u16BlockCount)); + } + else + { + s32SrcLastOffset = -(((int32_t)((pChnCfg->u32BlockSize >> pChnCfg->eSrcDataSize) * u16SrcDataOffset)) * + (int32_t)(pChnCfg->u16BlockCount)) - ((pChnCfg->s32BlockOffset) * (int32_t)(pChnCfg->u16BlockCount - 1U)); + } + } + else + { + s32SrcLastOffset = 0; + } + if (pChnCfg->bDestAddrLoopbackEn == true) + { + if (pChnCfg->bDestBlockOffsetEn == false) + { + s32DestLastOffset = -(((pChnCfg->u32BlockSize >> pChnCfg->eDestDataSize) * u16DestDataOffset) * + (pChnCfg->u16BlockCount)); + } + else + { + s32DestLastOffset = -(((int32_t)((pChnCfg->u32BlockSize >> pChnCfg->eDestDataSize) * u16DestDataOffset)) * + (int32_t)(pChnCfg->u16BlockCount)) - ((pChnCfg->s32BlockOffset) * (int32_t)(pChnCfg->u16BlockCount - 1U)); + } + } + else + { + s32DestLastOffset = 0; + } + + DMA_HWA_SetSrcAddr(pDma, (uint8_t)eChannel, (uint32_t)pChnCfg->pSrcBuffer); + DMA_HWA_SetDestAddr(pDma, (uint8_t)eChannel, (uint32_t)pChnCfg->pDestBuffer); + DMA_HWA_SetPriority(pDma, (uint8_t)eChannel, pChnCfg->u8ChannelPriority); + + if ((pChnCfg->bSrcCircularBufferEn == true) && (pChnCfg->bDestCircularBufferEn == true)) + { + DMA_HWA_SetSrcDataSize(pDma, (uint8_t)eChannel, pChnCfg->eSrcDataSize); + DMA_HWA_SetSrcModulo(pDma, (uint8_t)eChannel, u8SrcMod); + DMA_HWA_SetDestDataSize(pDma, (uint8_t)eChannel, pChnCfg->eDestDataSize); + DMA_HWA_SetDestModulo(pDma, (uint8_t)eChannel, u8DestMod); + } + else if (pChnCfg->bSrcCircularBufferEn == true) + { + DMA_HWA_SetSrcDataSize(pDma, (uint8_t)eChannel, pChnCfg->eSrcDataSize); + DMA_HWA_SetSrcModulo(pDma, (uint8_t)eChannel, u8SrcMod); + DMA_HWA_SetDestDataSize(pDma, (uint8_t)eChannel, pChnCfg->eDestDataSize); + DMA_HWA_SetDestModulo(pDma, (uint8_t)eChannel, 0U); + } + else if (pChnCfg->bDestCircularBufferEn == true) + { + DMA_HWA_SetSrcDataSize(pDma, (uint8_t)eChannel, pChnCfg->eSrcDataSize); + DMA_HWA_SetSrcModulo(pDma, (uint8_t)eChannel, 0U); + DMA_HWA_SetDestDataSize(pDma, (uint8_t)eChannel, pChnCfg->eDestDataSize); + DMA_HWA_SetDestModulo(pDma, (uint8_t)eChannel, u8DestMod); + } + else + { + DMA_HWA_SetSrcDataSize(pDma, (uint8_t)eChannel, pChnCfg->eSrcDataSize); + DMA_HWA_SetSrcModulo(pDma, (uint8_t)eChannel, 0U); + DMA_HWA_SetDestDataSize(pDma, (uint8_t)eChannel, pChnCfg->eDestDataSize); + DMA_HWA_SetDestModulo(pDma, (uint8_t)eChannel, 0U); + } + + if (bUseSrcDumo == true) + { + u16Sumo = (uint16_t)((pChnCfg->u32SrcCircBufferSize / u16SrcDataOffset - 1U) * u16SrcDataOffset); + } + if (bUseDestDumo == true) + { + u16Dumo = (uint16_t)((pChnCfg->u32DestCircBufferSize / u16DestDataOffset - 1U) * u16DestDataOffset); + } + if ((bUseSrcDumo == true) || (bUseDestDumo == true)) + { + DMA_HWA_SetUnalignModulo(pDma, u8DumoIndex, u16Sumo, u16Dumo); + DMA_HWA_SetUnalignModuloEnableFlag(pDma, (uint8_t)eChannel, bUseSrcDumo, bUseDestDumo); + DMA_HWA_SetUnalignModuloSel(pDma, (uint8_t)eChannel, u8DumoIndex); + } + DMA_HWA_SetAutoDisableReuqestEnableFlag(pDma, (uint8_t)eChannel, pChnCfg->bAutoStop); + + DMA_HWA_SetSrcOffset(pDma, (uint8_t)eChannel, (int16_t)u16SrcDataOffset); + DMA_HWA_SetDestOffset(pDma, (uint8_t)eChannel, (int16_t)u16DestDataOffset); + + DMA_HWA_SetInnerLoopOffset(pDma, (uint8_t)eChannel, pChnCfg->bSrcBlockOffsetEn, pChnCfg->bDestBlockOffsetEn, + pChnCfg->s32BlockOffset); + DMA_HWA_SetInnerLoopSize(pDma, (uint8_t)eChannel, pChnCfg->u32BlockSize); + + if ((pChnCfg->u16BlockCount > 1U) && (true == pChnCfg->bInnerChannelChain)) + { + DMA_HWA_SetChannelToChannelTrig(pDma, (uint8_t)eChannel, true, (uint8_t)eChannel); + DMA_HWA_SetLoopCount(pDma, (uint8_t)eChannel, pChnCfg->u16BlockCount); + } + else + { + DMA_HWA_SetChannelToChannelTrig(pDma, (uint8_t)eChannel, false, 0U); + DMA_HWA_SetLoopCount(pDma, (uint8_t)eChannel, pChnCfg->u16BlockCount); + } + + DMA_HWA_SetSrcLastAddrAdjustment(pDma, (uint8_t)eChannel, s32SrcLastOffset); + DMA_HWA_SetDestLastAddrAdjustment(pDma, (uint8_t)eChannel, s32DestLastOffset); + + if (pChnCfg->eTriggerSrc == DMA_REQ_DISABLED) + { + DMAMUX_HWA_SetRequestSource(pDmamux, (uint8_t)eChannel, false, DMA_REQ_DISABLED); + } + else + { + DMAMUX_HWA_SetRequestSource(pDmamux, (uint8_t)eChannel, true, pChnCfg->eTriggerSrc); + } + } + return ret; +} + +void DMA_DeinitChannel(const DMA_InstanceType eDma_Instance, const DMA_ChannelType eChannel) +{ + DEV_ASSERT(eDma_Instance < DMA_INSTANCE_MAX); + DEV_ASSERT(eChannel < DMA_CHANNEL_MAX); + + DMA_Type * aDma[] = DMA_BASE_PTRS; + DMA_Type *const pDma = aDma[eDma_Instance]; + uint8_t u8DumoIndex; + + for (u8DumoIndex = 0U; u8DumoIndex < DMA_DUMO_COUNT; u8DumoIndex++) + { + if (s_aDmaDumoUsedStatus[u8DumoIndex] == (uint8_t)eChannel) + { + s_aDmaDumoUsedStatus[u8DumoIndex] = DMA_CHANNEL_INVALID; + DMA_HWA_SetUnalignModulo(pDma, u8DumoIndex, 0U, 0U); + } + } + DMA_HWA_SetUnalignModuloEnableFlag(pDma, (uint8_t)eChannel, false, false); + DMA_HWA_DisableChannelErrorInterrupt(pDma, (uint8_t)eChannel); + DMA_HWA_DisableChannelRequest(pDma, (uint8_t)eChannel); + DMA_HWA_ClearChannelDoneStatus(pDma, (uint8_t)eChannel); + DMA_HWA_ClearChannelErrorFlag(pDma, (uint8_t)eChannel); + DMA_HWA_ClearChannelInterruptFlag(pDma, (uint8_t)eChannel); + + DMA_HWA_SetSrcAddr(pDma, (uint8_t)eChannel, 0U); + DMA_HWA_SetSrcOffset(pDma, (uint8_t)eChannel, 0); + DMA_HWA_SetSrcLastAddrAdjustment(pDma, (uint8_t)eChannel, 0); + DMA_HWA_SetDestAddr(pDma, (uint8_t)eChannel, 0U); + DMA_HWA_SetDestOffset(pDma, (uint8_t)eChannel, 0); + DMA_HWA_SetDestLastAddrAdjustment(pDma, (uint8_t)eChannel, 0); + DMA_HWA_SetSrcDataSize(pDma, (uint8_t)eChannel, DMA_TRANSFER_SIZE_1B); + DMA_HWA_SetSrcModulo(pDma, (uint8_t)eChannel, 0U); + DMA_HWA_SetDestDataSize(pDma, (uint8_t)eChannel, DMA_TRANSFER_SIZE_1B); + DMA_HWA_SetDestModulo(pDma, (uint8_t)eChannel, 0U); + DMA_HWA_SetInnerLoopOffset(pDma, (uint8_t)eChannel, false, false, 0); + DMA_HWA_SetInnerLoopSize(pDma, (uint8_t)eChannel, 0U); + DMA_HWA_SetChannelControlStatus(pDma, (uint8_t)eChannel, 0U); + DMA_HWA_SetChannelToChannelTrig(pDma, (uint8_t)eChannel, false, 0U); + DMA_HWA_SetLoopCount(pDma, (uint8_t)eChannel, 0U); +} + +void DMA_InitChannelInterrupt(const DMA_InstanceType eDma_Instance, const DMA_ChannelType eChannel, const DMA_InterruptCfgType *const pInterruptCfg) +{ + DEV_ASSERT(eDma_Instance < DMA_INSTANCE_MAX); + DEV_ASSERT(eChannel < DMA_CHANNEL_MAX); + DEV_ASSERT(pInterruptCfg != NULL); + + DMA_Type * aDma[] = DMA_BASE_PTRS; + DMA_Type *const pDma = aDma[eDma_Instance]; + + if (pInterruptCfg->bTransferCompleteIntEn) + { + s_dmaTransferCompleteNotify[eDma_Instance][eChannel] = pInterruptCfg->pTransferCompleteNotify; + DMA_HWA_EnableTransferCompleteInterrupt(pDma, (uint8_t)eChannel); + //IntMgr_EnableInterrupt(DMA_GetChannelIRQn(eChannel)); + } + else + { + DMA_HWA_DisableTransferCompleteInterrupt(pDma, (uint8_t)eChannel); + s_dmaTransferCompleteNotify[eDma_Instance][eChannel] = NULL; + //IntMgr_DisableInterrupt(DMA_GetChannelIRQn(eChannel)); + } + + if (pInterruptCfg->bTransferErrorIntEn) + { + s_dmaTransferErrorNotify[eDma_Instance][eChannel] = pInterruptCfg->pTransferErrorNotify; + DMA_HWA_EnableChannelErrorInterrupt(pDma, (uint8_t)eChannel); + //IntMgr_EnableInterrupt(DMA_error_IRQn); + } + else + { + DMA_HWA_DisableChannelErrorInterrupt(pDma, (uint8_t)eChannel); + s_dmaTransferErrorNotify[eDma_Instance][eChannel] = NULL; + //if (DMA_HWA_GetAllChannelErrorInterruptEnableFlag(pDma) == 0U) + //{ + //IntMgr_DisableInterrupt(DMA_error_IRQn); + //} + } +} + +void DMA_ConfigChainedTransfer(const DMA_InstanceType eDma_Instance, const DMA_ChannelType eChannel, + const DMA_ChainTransferType *const pChainTransferCfg) +{ + DEV_ASSERT(eDma_Instance < DMA_INSTANCE_MAX); + DEV_ASSERT(eChannel < DMA_CHANNEL_MAX); + DEV_ASSERT(pChainTransferCfg != NULL); + + DMA_Type * aDma[] = DMA_BASE_PTRS; + DMA_Type *const pDma = aDma[eDma_Instance]; + + DMA_HWA_SetOuterLoopTrigEnableFlag(pDma, (uint8_t)eChannel, pChainTransferCfg->bChanelChainEn); + DMA_HWA_SetOuterLoopTrigChannel(pDma, (uint8_t)eChannel, pChainTransferCfg->u8ChainedChannel); +} + + + +DMA_StatusType DMA_ModifySize(const DMA_InstanceType eDma_Instance, const DMA_ChannelType eChannel, uint16_t u16LoopCnt) { + DEV_ASSERT(eDma_Instance < DMA_INSTANCE_MAX); + DEV_ASSERT(eChannel < DMA_CHANNEL_MAX); + + DMA_Type * aDma[] = DMA_BASE_PTRS; + DMA_Type *const pDma = aDma[eDma_Instance]; + DMA_StatusType ret; + + if (DMA_GetChannelStatus(eDma_Instance, eChannel) == DMA_RUNNING_STATUS_IDLE) + { + DMA_HWA_SetLoopCount(pDma, (uint8_t)eChannel, u16LoopCnt); + + ret = DMA_STATUS_SUCCESS; + } + else + { + ret = DMA_STATUS_BUSY; + } + return ret; +} + +DMA_StatusType DMA_ModifyAddress(const DMA_InstanceType eDma_Instance, const DMA_ChannelType eChannel, + const volatile void *pSrcBuffer, const volatile void *pDestBuffer) +{ + DEV_ASSERT(eDma_Instance < DMA_INSTANCE_MAX); + DEV_ASSERT(eChannel < DMA_CHANNEL_MAX); + + DMA_Type * aDma[] = DMA_BASE_PTRS; + DMA_Type *const pDma = aDma[eDma_Instance]; + DMA_StatusType ret; + + if (DMA_GetChannelStatus(eDma_Instance, eChannel) == DMA_RUNNING_STATUS_IDLE) + { + if (pSrcBuffer != NULL) + { + DMA_HWA_SetSrcAddr(pDma, (uint8_t)eChannel, (uint32_t)pSrcBuffer); + } + if (pDestBuffer != NULL) + { + DMA_HWA_SetDestAddr(pDma, (uint8_t)eChannel, (uint32_t)pDestBuffer); + } + ret = DMA_STATUS_SUCCESS; + } + else + { + ret = DMA_STATUS_BUSY; + } + return ret; +} + +void DMA_StartChannel(const DMA_InstanceType eDma_Instance, const DMA_ChannelType eChannel) +{ + DEV_ASSERT(eDma_Instance < DMA_INSTANCE_MAX); + DEV_ASSERT(eChannel < DMA_CHANNEL_MAX); + + DMA_Type * aDma[] = DMA_BASE_PTRS; + DMA_Type *const pDma = aDma[eDma_Instance]; + + if (DMA_GetChannelRequestSrc(eDma_Instance, eChannel) == DMA_REQ_DISABLED) + { + DMA_HWA_SetChannelStart(pDma, (uint8_t)eChannel); + } + else + { + DMA_HWA_EnableChannelRequest(pDma, (uint8_t)eChannel); + } +} + +void DMA_StopChannel(const DMA_InstanceType eDma_Instance, const DMA_ChannelType eChannel) +{ + DEV_ASSERT(eDma_Instance < DMA_INSTANCE_MAX); + DEV_ASSERT(eChannel < DMA_CHANNEL_MAX); + + DMA_Type * aDma[] = DMA_BASE_PTRS; + DMA_Type *const pDma = aDma[eDma_Instance]; + + DMA_HWA_DisableChannelRequest(pDma, (uint8_t)eChannel); +} + +DMA_StatusType DMA_CancelTransfer(const DMA_InstanceType eDma_Instance, bool bGenerateErr) +{ + DEV_ASSERT(eDma_Instance < DMA_INSTANCE_MAX); + + DMA_Type * aDma[] = DMA_BASE_PTRS; + DMA_Type *const pDma = aDma[eDma_Instance]; + DMA_StatusType eRet; + uint32_t u32TimeOut = 15000000U; + + if (bGenerateErr) + { + DMA_HWA_ErrorCancelTransfer(pDma); + while ((DMA_HWA_GetErrorCancelTransferStatus(pDma) == true) && (u32TimeOut != 0U)) + { + u32TimeOut--; + } + } + else + { + DMA_HWA_CancelTransfer(pDma); + while ((DMA_HWA_GetCancelTransferStatus(pDma) == true) && (u32TimeOut != 0U)) + { + u32TimeOut--; + } + } + if (u32TimeOut != 0U) + { + eRet = DMA_STATUS_SUCCESS; + } + else + { + eRet = DMA_STATUS_TIMEOUT; + } + return eRet; +} + +DMA_RequestSourceType DMA_GetChannelRequestSrc(const DMA_InstanceType eDma_Instance, const DMA_ChannelType eChannel) +{ + DEV_ASSERT(eDma_Instance < DMA_INSTANCE_MAX); + DEV_ASSERT(eChannel < DMA_CHANNEL_MAX); + + DMAMUX_Type * aDmamux[] = DMAMUX_BASE_PTRS; + DMAMUX_Type *const pDmamux = aDmamux[eDma_Instance]; + + DMA_RequestSourceType eReqSrc = DMAMUX_HWA_GetRequestSource(pDmamux, (uint8_t)eChannel); + + return eReqSrc; +} + +DMA_RunningStatusType DMA_GetStatus(const DMA_InstanceType eDma_Instance) +{ + DEV_ASSERT(eDma_Instance < DMA_INSTANCE_MAX); + + DMA_Type * aDma[] = DMA_BASE_PTRS; + DMA_Type *const pDma = aDma[eDma_Instance]; + DMA_RunningStatusType eDMAStatus = DMA_HWA_GetStatus(pDma); + return eDMAStatus; +} + +DMA_RunningStatusType DMA_GetChannelStatus(const DMA_InstanceType eDma_Instance, const DMA_ChannelType eChannel) +{ + DEV_ASSERT(eDma_Instance < DMA_INSTANCE_MAX); + DEV_ASSERT(eChannel < DMA_CHANNEL_MAX); + + DMA_Type * aDma[] = DMA_BASE_PTRS; + DMA_Type *const pDma = aDma[eDma_Instance]; + DMA_RunningStatusType eChannelStatus = DMA_HWA_GetChannelActiveStatus(pDma, (uint8_t)eChannel); + return eChannelStatus; +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_dsp.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_dsp.c new file mode 100644 index 0000000..51f181b --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_dsp.c @@ -0,0 +1,38 @@ +/** + * @file fc7xxx_driver_dsp.c + * @author Flagchip051 + * @brief FC4xxx DSP driver type definition and API + * @version 0.1.0 + * @date 2022-04-23 + * + * @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2022-04-23 Flagchip054 N/A First version for FC7300 + ******************************************************************************** */ + +#include "fc7xxx_driver_dsp.h" + + +/* + * @details @verbatim +If only want use FPU, +1) configure FCIDE to enable FPU compiler support, "Properties" -> C/C++ Build -> Settings -> Tool Settings -> Target Processor -> Float ABI -> FP instructions(hard) -> FPU Type set to "fpv5-sp-d16" +2) configure FCIDE to enable FPU compiler support, "Properties" -> C/C++ Build -> Settings -> Tool Settings -> GNU Arm Cross C Compiler -> Preprocessor -> Defined symbols(-D) -> Add "__FPU_PRESENT=1" (without ") +3) and call FPU_Enable to enable FPU at the beginning of program. + +If want to use DSP, +1) configure FCIDE to enable FPU compiler support, Properties -> C/C++ Build -> Settings -> Tool Settings -> Target Processor -> Float ABI -> FP instructions(hard) +2) add MACRO "DRIVER_CM7_DSP_ENABLE" in FCIDE Properties -> C/C++ General -> Paths and Symbols -> Symbols -> GNU C and GNU C++ and Assembly +3) add Include Path to project Properties -> C/C++ General -> Paths and Symbols -> Includes -> GNU C and GNU C++ and Assembly: + ../../../../../../Template/Device/CMSIS5_590/DSP/Include + ../../../../../../Template/Device/CMSIS5_590/Core/Include + ../../../../../../Template/Device/CMSIS5_590/DSP/PrivateInclude +4) and call FPU_Enable to enable FPU at the beginning of program. + @endverbatim + */ diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_eim.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_eim.c new file mode 100644 index 0000000..b18e4e6 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_eim.c @@ -0,0 +1,217 @@ +/** + * @file fc7xxx_driver_eim.c + * @author Flagchip + * @brief FC7xxx EIM driver type definition and API + * @version 0.1.0 + * @date 2024-01-14 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/******************************************************************************** +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2024-01-14 qxw0100 N/A First version for FC7240 +********************************************************************************/ + +#include "fc7xxx_driver_eim.h" +#include "fc7xxx_driver_pcc.h" + +/******************* Local Variables ***********************/ + +/******************* Local Function Prototype **************/ + + +/****************** Global Functions ***********************/ +/** + * @brief Initialize EIM function + * + * @param pEimInitCfg Initialization structure of EIM + * @return return 0: initialize successful. 1: invalid parameter + */ +EIM_RetType EIM_Init(const EIM_InitType *pEimInitCfg) +{ + EIM_RetType eRet = EIM_STATUS_SUCCESS; + uint32_t u32CtrlVal = 0U; + uint32_t u32BusVal = 0U; + uint8_t u8BusChn; + if (NULL == pEimInitCfg) + { + eRet = EIM_STATUS_PARAM_INVALID; + } + else + { + u32CtrlVal |= EIM_CTRL_REG_BUS_SEL(pEimInitCfg->u8BusSelIdx); + u8BusChn = (uint8_t)pEimInitCfg->u8BusSelIdx; + if(pEimInitCfg->u8Attreenable != 0U) + { + if((pEimInitCfg->u8EimChn>=1U) && (pEimInitCfg->u8EimChn<=23U)) + { + u32CtrlVal |= EIM_CTRL_REG_ATTREIE(1U); + u32BusVal |= EIM_BUS_REG_ATTR(pEimInitCfg->u8AttrPosition); + } + else + { + eRet = EIM_STATUS_PARAM_INVALID; + } + + } + if(pEimInitCfg->u8Addreenable != 0U) + { + if((pEimInitCfg->u8EimChn>=1U) && (pEimInitCfg->u8EimChn<=23U)) + { + u32CtrlVal |= EIM_CTRL_REG_ADDREIE(1U); + u32BusVal |= EIM_BUS_REG_ADDR(pEimInitCfg->u8AddrePosition); + } + else + { + eRet = EIM_STATUS_PARAM_INVALID; + } + } + if(pEimInitCfg->u8Data0enable != 0U) + { + u32CtrlVal |= EIM_CTRL_REG_DATA0EIE(1U); + u32BusVal |= EIM_BUS_REG_DATA0(pEimInitCfg->u8Data0Val); + } + if(pEimInitCfg->u8Data1enable != 0U) + { + u32CtrlVal |= EIM_CTRL_REG_DATA1EIE(1U); + u32BusVal |= EIM_BUS_REG_DATA1(pEimInitCfg->u8Data1Val); + } + EIM_HWA_Set_BUSRegn(u8BusChn,u32BusVal); + EIM_HWA_Set_CtrlRegn((uint8_t)pEimInitCfg->u8EimChn,u32CtrlVal); + EIM_HWA_EnableGlobalErrorInjection(); + } + + return eRet; +} + +/** + * @brief Initialize EIM function + * + * @param eEimChannel channel want to set + * @param eDwpType Cpu to use + * @param bLockStatus Lock the cpu control settings + * @return Set operation success/failed + */ +EIM_RetType EIM_SetDwpMode(const EIM_ChannelType eEimChannel, const EIM_DWPType eDwpType, bool bLockStatus) +{ + uint8_t u8ChnIdx = (uint8_t)eEimChannel; + EIM_RetType eRet = EIM_STATUS_SUCCESS; + if (0U == EIM_HWA_GetCtrlDWPLockStatus(u8ChnIdx)) + { + EIM_HWA_Set_CtrlLockMode((uint8_t)eEimChannel,(uint8_t)eDwpType); + if(true == bLockStatus) + { + /* Lock the dwp mode until reset */ + EIM_HWA_CtrlRegnWritePermit(u8ChnIdx); + } + } + else + { + eRet = EIM_STATUS_PARAM_INVALID; + } + + return eRet; +} + +/** + * @brief Enable CPU lockstep monitor + * + * @param eEimCpuType EIM_CPU0_LOCKSTEP or EIM_CPU1_LOCKSTEP + * @param eMonitorType EIM_MONITOR0 or EIM_MONITOR1 + */ +void EIM_CpuLockStepMonitorSet_MonSet(const EIM_CPU_ChnType eEimCpuType,const EIM_MONType eMonitorType) +{ + uint32_t u32val = 0U; + + u32val = EIM_HWA_Get_CPULockstep((uint8_t)eEimCpuType); + + if(eMonitorType == EIM_MONITOR0) + { + u32val &= 0xFFFFFFFD;//clear mon0 clr + u32val |= EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_SET(1U); + } + + if(eMonitorType == EIM_MONITOR1) + { + u32val &= 0xFFFFFFFE;//clear mon1 clr + u32val |= EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_SET(1U); + } + + EIM_HWA_Set_CPULockstep((uint8_t)eEimCpuType, u32val); +} + +/** + * @brief Clear CPU lockstep monitor + * + * @param eEimCpuType EIM_CPU0_LOCKSTEP or EIM_CPU1_LOCKSTEP + * @param eMonitorType EIM_MONITOR0 or EIM_MONITOR1 + */ +void EIM_CpuLockStepMonitorSet_MonClr(const EIM_CPU_ChnType eEimCpuType,const EIM_MONType eMonitorType) +{ + uint32_t u32val = 0U; + + u32val = EIM_HWA_Get_CPULockstep((uint8_t)eEimCpuType); + + if(eMonitorType == EIM_MONITOR0) + { + u32val |= EIM_CPU0_LOCKSTEP_LOCKSTEP_MON0_CLR(1U); + } + if(eMonitorType == EIM_MONITOR1) + { + u32val |= EIM_CPU0_LOCKSTEP_LOCKSTEP_MON1_CLR(1U); + } + + EIM_HWA_Set_CPULockstep((uint8_t)eEimCpuType, u32val); +} + +/** + * @brief Clean CPU lockstep monitor bit + * + * @param eEimCpuType EIM_CPU0_LOCKSTEP or EIM_CPU1_LOCKSTEP + * @param eMonitorType EIM_MONITOR0 or EIM_MONITOR1 + */ +void EIM_CpuLockStepMonitorClr(const EIM_CPU_ChnType eEimCpuType, const EIM_MONType eMonitorType) +{ + uint32_t u32val = 0U; + + u32val = EIM_HWA_Get_CPULockstep((uint8_t)eEimCpuType); + + if(eMonitorType == EIM_MONITOR0) + { + u32val &= 0xFFFFFFF5;//clear mon0 clr + } + + if(eMonitorType == EIM_MONITOR1) + { + u32val &= 0xFFFFFFFA;//clear mon1 clr + } + + EIM_HWA_Set_CPULockstep((uint8_t)eEimCpuType, u32val); +} + +/** + * @brief Deinin EIM function + * + */ +void Eim_Deinit(void) +{ + uint8_t u8loop; + EIM_HWA_DisableGlobalErrorInjection(); + for (u8loop = 0U; u8loop < EIM_CTRL_REG_COUNT; u8loop++) + { + EIM_HWA_Set_CtrlRegn(u8loop, 0U); + } + + EIM_HWA_Set_CPULockstep(EIM_CPU0_LOCKSTEP, 0U); + EIM_HWA_Set_CPULockstep(EIM_DMA0_LOCKSTEP, 0U); + + for (u8loop = 0U; u8loop < EIM_BUS_REG_COUNT; u8loop++) + { + EIM_HWA_Set_BUSRegn(u8loop, 0U); + } +} + diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_erm.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_erm.c new file mode 100644 index 0000000..432356b --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_erm.c @@ -0,0 +1,175 @@ +/** + * @file fc7xxx_driver_erm.c + * @author Flagchip + * @brief FC7xxx ERM driver type definition and API + * @version 0.1.0 + * @date 2024-01-14 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/******************************************************************************** +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2024-01-14 qxw0100 N/A First version for FC7240 +********************************************************************************/ + +#include "fc7xxx_driver_erm.h" +#include "fc7xxx_driver_pcc.h" +#include "interrupt_manager.h" + +/* ############################## Local Variables ################################ */ +/** + * @brief Erm user defined interrupt function + * */ +static ERM_InterruptCallBackType s_pErmNotifyPtr = NULL; + +/* ################################################################################## */ +/* ########################### Global Prototype Functions ########################### */ + +void ERM_fault_IRQHandler(void); + +/* ################################################################################## */ +/* ################################ Local Functions ################################# */ +/** + * @brief Initialize ERM function + * + * @param pErmInt_cfg Initialization structure of ERM + * @return return 0: initialize successful. 1: invalid parameter + */ + +ERM_RetType Erm_Init(const ERM_MemorytInitType *pErmInt_cfg) +{ + ERM_RetType eRet = ERM_STATUS_SUCCESS; + uint32_t u32ErmCrVal = 0U; + ERM_ClearSRnRegister(); + + if (NULL == pErmInt_cfg) + { + eRet = ERM_STATUS_PARAM_INVALID; + } + else + { + if(pErmInt_cfg->u8ErmEnable != 0U) + { + if ((uint32_t)pErmInt_cfg->eChannel < 8U) + { + u32ErmCrVal |= (uint32_t)((uint32_t)pErmInt_cfg->eInt << (30UL - (uint32)pErmInt_cfg->eChannel*4U)); + ERM_HWA_Set_CRn(0, u32ErmCrVal); + } + else if (((uint32_t)pErmInt_cfg->eChannel >= 8U) && ((uint32_t)pErmInt_cfg->eChannel < 16U)) + { + u32ErmCrVal |= (uint32_t)((uint32_t)pErmInt_cfg->eInt << (62UL - (uint32)pErmInt_cfg->eChannel*4U)); + ERM_HWA_Set_CRn(1, u32ErmCrVal); + } + else if (((uint32_t)pErmInt_cfg->eChannel >= 16U) && ((uint32_t)pErmInt_cfg->eChannel < 24U)) + { + u32ErmCrVal |= (uint32_t)((uint32_t)pErmInt_cfg->eInt << (94UL - (uint32)pErmInt_cfg->eChannel*4U)); + ERM_HWA_Set_CRn(2, u32ErmCrVal); + } + else if (((uint32_t)pErmInt_cfg->eChannel >= 24U) && ((uint32_t)pErmInt_cfg->eChannel < 32U)) + { + u32ErmCrVal |= (uint32_t)((uint32_t)pErmInt_cfg->eInt << (126UL - (uint32)pErmInt_cfg->eChannel*4U)); + ERM_HWA_Set_CRn(3, u32ErmCrVal); + } + else + { + eRet = ERM_STATUS_PARAM_INVALID; + } + if(eRet == ERM_STATUS_SUCCESS) + { + s_pErmNotifyPtr = pErmInt_cfg->pIsrNotify; + } + } + + } + return eRet; +} +/** + * @brief De-initialize ERM function + * Restore the ERM instance to its reset state + */ +void Erm_DeInit(void) +{ + uint8_t u8loop; + for (u8loop = 0U; u8loop < 4U; u8loop++) + { + ERM_HWA_Set_CRn(u8loop, 0x0U); + ERM_HWA_Set_SRn(u8loop, 0x0U); + } +} +/** + * @brief ERM Clear SR0 register. + * + * This function Clear ERM SR0 register. + */ +void ERM_ClearSRnRegister(void) +{ + uint8_t u8loop; + for (u8loop = 0U; u8loop < 4U; u8loop++) + { + ERM_HWA_Set_SRn(u8loop, ERM_SR_MASK); + } +} + +/** + * @brief ERM read SRn register. + * + * This function Clear ERM SRn register. + * @param u8Index the SRn channel + */ +uint32_t ERM_ReadSRnVal(uint8_t u8Index) +{ + uint32_t u32Val; + u32Val = ERM_HWA_Get_SRn(u8Index); + return u32Val; +} +/** + * @brief ERM clear CRn register. + * + * This function Clear ERM CRn register. + * @param u8Index of the CRn channel + */ +void ERM_ClearCRnVal(uint8_t u8Index) +{ + ERM_HWA_Set_CRn(u8Index, 0UL); +} + +/** + * @brief ERM clear SRn register. + * + * This function Clear ERM SR0 register. + * @param u8Index the SRn channel + */ +uint32_t ERM_ClearSRnVal(uint8_t u8Index) +{ + uint32_t u32Val; + u32Val = ERM_HWA_Get_SRn(u8Index); + ERM_HWA_Set_SRn(u8Index, u32Val); + return u32Val; +} +/** + * @brief ERM interrupt function + */ +void ERM_fault_IRQHandler(void) +{ + if(s_pErmNotifyPtr != NULL) + { + s_pErmNotifyPtr(); + } +} +/** + * @brief ERM Read EARn address. + * @param eChannel The channel type + * @return u32Address The error address + */ +/* +uint32_t ERM_ReadAddress(ERM_channelType eChannel) +{ + uint32_t u32Address = 0U; + u32Address = ERM_HWA_GetEARn(eChannel); + return u32Address; +}*/ + diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_fciic.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_fciic.c new file mode 100644 index 0000000..d56136f --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_fciic.c @@ -0,0 +1,817 @@ +/** + * @file fc7xxx_driver_fciic.c + * @author Flagchip + * @brief FC7xxx FCIIC driver type definition and API + * @version 0.1.0 + * @date 2022-12-31 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + */ + +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024/1/10 qxw0095 N/A First version for FC7240 + ******************************************************************************** */ + +#include "fc7xxx_driver_fciic.h" +#include "interrupt_manager.h" + +#include "stdarg.h" +#include "stdio.h" +#include "string.h" +#include "stdlib.h" + +/* #define FCIIC_RX_FIFO */ + + +/* iic instance value */ +static FCIIC_Type *const s_aFCIIC_InstanceTable[FCIIC_INSTANCE_COUNT] = FCIIC_BASE_PTRS; + +/* store notify callback function point */ +static FCIIC_ErrorInterrupt_CallBackType s_aFCIIC_ErrorNotifyTable[FCIIC_INSTANCE_COUNT] = {NULL}; +static FCIIC_RxInterrupt_CallBackType s_aFCIIC_RxNotifyTable[FCIIC_INSTANCE_COUNT] = {NULL}; + +#ifdef FCIIC_RX_ALL_POLLING + /* check every pFciic instance whether is used */ + static uint8_t s_aFCIIC_IicMasterUsed[FCIIC_INSTANCE_COUNT]; + static uint8_t s_aFCIIC_IicSlaveUsed[FCIIC_INSTANCE_COUNT]; +#endif + + +/* ################################################################################## */ +/* ########################### Local Prototype Functions ############################ */ +#if 0 +static void CheckAndClear(FCIIC_Type *pFciic); +#endif +static void FCIIC_LL_MasterIRQnHandler(uint8_t u8IicIndex); +static void FCIIC_LL_SlaveIRQnHandler(uint8_t u8IicIndex); +static uint8_t FCIIC_Init_Master(uint8_t u8IicIndex, FCIIC_InitType *pInitCfg); +static uint8_t FCIIC_Init_Slave(uint8_t u8IicIndex, FCIIC_InitType *pInitCfg); + + +/* ################################################################################## */ +/* ########################### Global Prototype Functions ########################### */ + +void FCIIC0_IRQHandler(void); +void FCIIC1_IRQHandler(void); + +/* ################################################################################## */ +/* ################################ Local Functions ################################# */ + + +#if 0 +static void CheckAndClear(FCIIC_Type *pFciic) +{ + FCIIC_Master_HwA_CheckClearStatus(pFciic, FCIIC_MSR_EPF_STATUS); + FCIIC_Master_HwA_CheckClearStatus(pFciic, FCIIC_MSR_SDF_STATUS); + FCIIC_Master_HwA_CheckClearStatus(pFciic, FCIIC_MSR_NDF_STATUS); + FCIIC_Master_HwA_CheckClearStatus(pFciic, FCIIC_MSR_FEF_STATUS); + FCIIC_Master_HwA_CheckClearStatus(pFciic, FCIIC_MSR_ALF_STATUS); +} +#endif + + + +/*************************************************** + * FCIIC_LL_MasterIRQnHandler + * @detail: Iic n interrupt process + * + * param in : u8IicIndex, 0,1,2,3 + * param out: none + * + * return : none + * ************************************************/ +static void FCIIC_LL_MasterIRQnHandler(uint8_t u8IicIndex) +{ + /* uint8_t iic_status; */ + uint8_t u8RetVal; + FCIIC_RxDataType pRxData; + uint32_t u32ErrorValue; + + /* check pFciic receive data */ + u8RetVal = FCIIC_Master_Receive(u8IicIndex, &pRxData); + + if ((s_aFCIIC_RxNotifyTable[u8IicIndex] != NULL) && (u8RetVal == 0U)) + { + s_aFCIIC_RxNotifyTable[u8IicIndex](u8IicIndex, &pRxData); + } + + /* check error */ + u32ErrorValue = FCIIC_Master_GetError(u8IicIndex); + if ((u32ErrorValue != 0U) && (s_aFCIIC_ErrorNotifyTable[u8IicIndex] != NULL)) + { + s_aFCIIC_ErrorNotifyTable[u8IicIndex](u8IicIndex, 1U, u32ErrorValue); + FCIIC_Master_ClrError(u8IicIndex); + } + +} + + +/*************************************************** + * FCIIC_LL_SlaveIRQnHandler + * @detail: Iic n interrupt process + * + * param in : u8IicIndex, 0,1,2,3 + * param out: none + * + * return : none + * ************************************************/ +static void FCIIC_LL_SlaveIRQnHandler(uint8_t u8IicIndex) +{ + /* uint8_t iic_status; */ + uint8_t u8RetVal; + FCIIC_RxDataType pRxData; + uint32_t u32ErrorValue; + + /* check pFciic receive data */ + u8RetVal = FCIIC_Slave_Receive(u8IicIndex, &pRxData); + + if ((s_aFCIIC_RxNotifyTable[u8IicIndex] != NULL) && (u8RetVal == 0U)) + { + s_aFCIIC_RxNotifyTable[u8IicIndex](u8IicIndex, &pRxData); + } + + /* check error */ + u32ErrorValue = FCIIC_Slave_GetError(u8IicIndex); + if ((u32ErrorValue != 0U) && (s_aFCIIC_ErrorNotifyTable[u8IicIndex] != NULL)) + { + s_aFCIIC_ErrorNotifyTable[u8IicIndex](u8IicIndex, 0U, u32ErrorValue); + FCIIC_Slave_ClrError(u8IicIndex); + } + +} + + + + + +/*************************************************** + * FCIIC_Init_Master + * @detail: Iic device master mode initial + * + * param in : pInitCfg, pFciic initial config parameters + * structure address + * param out: none + * + * return : 0 is ok, others are not ok + * ************************************************/ +static uint8_t FCIIC_Init_Master(uint8_t u8IicIndex, FCIIC_InitType *pInitCfg) +{ + uint32_t u32TempMcr, u32TempMder, u32TempMcfgr0, u32TempMcfgr1, u32TempMcfgr2, u32TempMcfgr3, u32TempMccr0; + uint32_t u32TempMFCR; + + FCIIC_Type *pFciic; + uint32_t u32ClkSrcHz; + uint32_t u32FreqDeltaCur, u32FreqDeltaOld; + uint32_t u32FreqDesired, u32FreqCur; + uint32_t u32Prescale, u8PrescaleTemp; + uint32_t u32CLKHI, u32CLKHITemp; + uint32_t u32CLKLO, u32CLKLOTemp; + + pFciic = (FCIIC_Type *)s_aFCIIC_InstanceTable[u8IicIndex]; + + u32ClkSrcHz = pInitCfg->u32ClkSrcHz; + u32FreqDesired = pInitCfg->u32Frequency; + u32FreqDeltaOld = u32FreqDesired; + + /* SCL_LATENCY is defined as ROUNDDOWN ((2 + FILTSCL + SCL_RISETIME) / (2 ^ PRESCALE)) */ + /* CLKLO: Minimum value is 0x3 */ + /* CLKHI: Minimum value is 0x1 */ + /* SCL clock period: (CLKHI + CLKLO + 2 + SCL_LATENCY) �� (2 ^ PRESCALE) �� function clock period */ + for(u32CLKHITemp=1U; (u32CLKHITemp < 63U); u32CLKHITemp++) + { + for(u32CLKLOTemp=3U; (u32CLKLOTemp < 63U); u32CLKLOTemp++) + { + /* get the linear prescale */ + for (u8PrescaleTemp = 0U; u8PrescaleTemp < 8U; u8PrescaleTemp++) + { + u32FreqCur = u32ClkSrcHz / Fc_Power(2U, (uint32_t)u8PrescaleTemp)/(u32CLKHITemp+u32CLKLOTemp+2U); + /* If the current frequency is less than the desired frequency, + * compare the delta with the previous one and select the parameter with the smallest delta + * */ + if(u32FreqCur <= u32FreqDesired) + { + u32FreqDeltaCur = u32FreqDesired - u32FreqCur; + if (u32FreqDeltaCur < u32FreqDeltaOld) + { + u32FreqDeltaOld = u32FreqDeltaCur; + u32Prescale = u8PrescaleTemp; + u32CLKHI = u32CLKHITemp; + u32CLKLO = u32CLKLOTemp; + } + break; + } + } + + if(u32FreqDeltaOld == 0U) + { + break; + } + } + + if(u32FreqDeltaOld==0U) + { + break; + } + } + + u32TempMcr = FCIIC_MCR_RRF(0U) | + FCIIC_MCR_RTF(0U) | + FCIIC_MCR_DBGEN(0U) | + FCIIC_MCR_RST(0U) | + FCIIC_MCR_MEN(1U); /* master enable */ + + + u32TempMder = FCIIC_MDER_RDDE(pInitCfg->bEnDma) | /* enable receive dma */ + FCIIC_MDER_TDDE(pInitCfg->bEnDma); /* enable transmit dma */ + + u32TempMcfgr0 = FCIIC_MCFGR0_RDMO(0U) | + FCIIC_MCFGR0_TRGEN(0U); + + u32TempMcfgr1 = FCIIC_MCFGR1_PINCFG(0U) | /* 0=open drain; 1=push-pull mode */ + FCIIC_MCFGR1_MATCFG(0U) | + FCIIC_MCFGR1_TIMECFG(0U) | + FCIIC_MCFGR1_IGNACK(1U) | + FCIIC_MCFGR1_AUTOSTOP(0U) | + FCIIC_MCFGR1_PRESCALE(u32Prescale); /* Prescaler = 2^n */ + + u32TempMcfgr2 = FCIIC_MCFGR2_FILTSDA(0U) | + FCIIC_MCFGR2_FILTSCL(0U) | + FCIIC_MCFGR2_BUSIDLE(0U); + + u32TempMcfgr3 = FCIIC_MCFGR3_PINLOW(0U); + + + u32TempMccr0 = FCIIC_MCCR_DATAVD(0x09U) | + FCIIC_MCCR_SETHOLD(0x13U) | + FCIIC_MCCR_CLKHI(u32CLKHI) | + FCIIC_MCCR_CLKLO(u32CLKLO); /* 0x09131327; */ + + u32TempMFCR = FCIIC_MFCR_TXWATER(pInitCfg->bTxFifoWMrk) | FCIIC_MFCR_RXWATER(pInitCfg->bRxFifoWMrk); + + FCIIC_HWA_SetMder(pFciic, u32TempMder); + FCIIC_HWA_SetMCFGR0(pFciic, u32TempMcfgr0); + FCIIC_HWA_SetMCFGR1(pFciic, u32TempMcfgr1); + FCIIC_HWA_SetMCFGR2(pFciic, u32TempMcfgr2); + FCIIC_HWA_SetMCFGR3(pFciic, u32TempMcfgr3); + FCIIC_HWA_SetMCCR(pFciic, u32TempMccr0); + FCIIC_HWA_SetMFCR(pFciic, u32TempMFCR); + + FCIIC_HWA_SetMcr(pFciic, u32TempMcr); /* | FCIIC_MCR_RRF_MASK | FCIIC_MCR_RTF_MASK | FCIIC_MCR_DBGEN_MASK | FCIIC_MCR_RST_MASK; */ + + #ifdef FCIIC_INIT_WAITRESET + u8RetVal = 1; + + while (u8RetVal) + { + u8RetVal = (pFciic->MCR & FCIIC_MCR_RST_MASK) >> FCIIC_MCR_RST_SHIFT; + pFciic->MCR = u32TempMcr; + } + #endif + return 0U; +} + + + +/*************************************************** + * FCIIC_DeInit_Master + * @detail: Iic device master mode de-initial + * + * param in : u8IicIndex + * param out: none + * + * return : 0 is ok, others are not ok + * ************************************************/ +static uint8_t FCIIC_DeInit_Master(uint8_t u8IicIndex) +{ + uint32_t u32TempMcr, u32TempMder; + + FCIIC_Type *pFciic; + pFciic = (FCIIC_Type *)s_aFCIIC_InstanceTable[u8IicIndex]; + + + u32TempMcr = FCIIC_MCR_RRF(0U) | + FCIIC_MCR_RTF(0U) | + FCIIC_MCR_DBGEN(0U) | + FCIIC_MCR_RST(0U) | + FCIIC_MCR_MEN(0U); /* master enable */ + + + u32TempMder = FCIIC_MDER_RDDE(0U) | /* disable receive dma */ + FCIIC_MDER_TDDE(0U); /* disable transmit dma */ + + + + + FCIIC_HWA_SetMder(pFciic, u32TempMder); + + FCIIC_HWA_SetMcr(pFciic, u32TempMcr); /* | FCIIC_MCR_RRF_MASK | FCIIC_MCR_RTF_MASK | FCIIC_MCR_DBGEN_MASK | FCIIC_MCR_RST_MASK; */ + + + return 0U; +} + + + +/*************************************************** + * FCIIC_Init_Slave + * @detail: Iic device master mode initial + * + * param in : u8IicIndex + * param out: none + * + * return : 0 is ok, others are not ok + * ************************************************/ +static uint8_t FCIIC_Init_Slave(uint8_t u8IicIndex, FCIIC_InitType *pInitCfg) +{ + uint32_t u32TempScr, u32TempSder, u32TempScfgr1, u32TempScfgr2, u32TempSamr; + + FCIIC_Type *pFciic; + + pFciic = (FCIIC_Type *)s_aFCIIC_InstanceTable[u8IicIndex]; + + + u32TempScr = FCIIC_SCR_FILTEN(0U) | + FCIIC_SCR_RST(0U) | + FCIIC_SCR_SEN(1U); /* slave enable */ + + + u32TempSder = FCIIC_SDER_AVDE(pInitCfg->bEnDma) | + FCIIC_SDER_RDDE(pInitCfg->bEnDma) | /* enable receive dma */ + FCIIC_SDER_TDDE(pInitCfg->bEnDma); /* enable transmit dma */ + + + + u32TempScfgr1 = FCIIC_SCFGR1_ADDRCFG(0U) | /* Address Configuration, 7bit */ + FCIIC_SCFGR1_HSMEN(0U) | + FCIIC_SCFGR1_IGNACK(1U) | + FCIIC_SCFGR1_RXCFG(0U) | + FCIIC_SCFGR1_TXCFG(0U) | + FCIIC_SCFGR1_SAEN(0U) | + FCIIC_SCFGR1_GCEN(0U) | + FCIIC_SCFGR1_ACKSTALL(0U) | + FCIIC_SCFGR1_TXDSTALL(0U) | + FCIIC_SCFGR1_RXSTALL(0U) | + FCIIC_SCFGR1_ADRSTALL(0U); + + u32TempScfgr2 = FCIIC_SCFGR2_FILTSDA(0U) | + FCIIC_SCFGR2_FILTSCL(0U) | + FCIIC_SCFGR2_DATAVD(0x09U) | + FCIIC_SCFGR2_CLKHOLD(1U); + + + + + u32TempSamr = FCIIC_SAMR_ADDR1(0U) | + FCIIC_SAMR_ADDR0(pInitCfg->u8SlaveAddr); + + + + FCIIC_HWA_SetSDER(pFciic, u32TempSder); + FCIIC_HWA_SetSCFGR1(pFciic, u32TempScfgr1); + FCIIC_HWA_SetSCFGR2(pFciic, u32TempScfgr2); + FCIIC_HWA_SetSAMR(pFciic, u32TempSamr); + + + FCIIC_HWA_SetSCR(pFciic, u32TempScr); + + return 0U; +} + + +/*************************************************** + * FCIIC_DeInit_Slave + * @detail: Iic device master mode de-initial + * + * param in : pInitCfg, pFciic initial config parameters + * structure address + * param out: none + * + * return : 0 is ok, others are not ok + * ************************************************/ +static uint8_t FCIIC_DeInit_Slave(uint8_t u8IicIndex) +{ + uint32_t u32TempScr, u32TempSder; + + FCIIC_Type *pFciic; + + pFciic = (FCIIC_Type *)s_aFCIIC_InstanceTable[u8IicIndex]; + + u32TempScr = FCIIC_SCR_FILTEN(0U) | + FCIIC_SCR_RST(0U) | + FCIIC_SCR_SEN(0U); /* slave enable */ + + + u32TempSder = FCIIC_SDER_AVDE(0U) | + FCIIC_SDER_RDDE(0U) | /* disable receive dma */ + FCIIC_SDER_TDDE(0U); /* disable transmit dma */ + + FCIIC_HWA_SetSDER(pFciic, u32TempSder); + + + FCIIC_HWA_SetSCR(pFciic, u32TempScr); + + return 0U; + +} + + +/* ################################################################################## */ +/* ################################ Global Functions ################################ */ + + + +/** + * \brief This Function is used to initial IIC instance + * + * \param u8IicIndex Iic Index, 0,1 + * \param pInitCfg is the structure address of IIC initial configuration parameters, and it contains IIC instance + * \return 0 is ok, others are not ok + */ +uint8_t FCIIC_Init(uint8_t u8IicIndex, FCIIC_InitType *pInitCfg) +{ + /* master mode */ + if (pInitCfg->bMasterMode != 0U) + { + FCIIC_Init_Master(u8IicIndex, pInitCfg); + #ifdef FCIIC_RX_ALL_POLLING + s_aFCIIC_IicMasterUsed[u8IicIndex] = 1U; + s_aFCIIC_IicSlaveUsed[u8IicIndex] = 0U; + #endif + } + else /* slave mode */ + { + FCIIC_Init_Slave(u8IicIndex, pInitCfg); + #ifdef FCIIC_RX_ALL_POLLING + s_aFCIIC_IicMasterUsed[u8IicIndex] = 0U; + s_aFCIIC_IicSlaveUsed[u8IicIndex] = 1U; + #endif + } + #if (defined(__ICCARM__)) + u8IicIndex = u8IicIndex; + #elif defined __GNUC__ + (void)u8IicIndex; + #endif + + return 0U; +} + + +/** + * \brief This Function is used to de-initial IIC instance + * + * \param u8IicIndex Iic Index, 0,1 + * \param pInitCfg is the structure address of IIC initial configuration parameters, bMaster should be set + * \return 0 is ok, others are not ok + */ +uint8_t FCIIC_DeInit(uint8_t u8IicIndex, FCIIC_InitType *pInitCfg) +{ + + /* master mode */ + if (pInitCfg->bMasterMode != 0U) + { + FCIIC_DeInit_Master(u8IicIndex); + #ifdef FCIIC_RX_ALL_POLLING + s_aFCIIC_IicMasterUsed[u8IicIndex] = 0U; + s_aFCIIC_IicSlaveUsed[u8IicIndex] = 0U; + #endif + } + else /* slave mode */ + { + FCIIC_DeInit_Slave(u8IicIndex); + #ifdef FCIIC_RX_ALL_POLLING + s_aFCIIC_IicMasterUsed[u8IicIndex] = 0U; + s_aFCIIC_IicSlaveUsed[u8IicIndex] = 0U; + #endif + } + + + #if (defined(__ICCARM__)) + u8IicIndex = u8IicIndex; + #elif defined __GNUC__ + (void)u8IicIndex; + #endif + + return 0U; +} + + +/** + * \brief This Function is used to configure IIC master interrupt + * + * \param u8IicIndex Iic Index, 0,1 + * \param pIntCfg contains IIC instance and interrupt callback functions + * \return 0 is ok, others are not ok + */ +uint8_t FCIIC_Master_SetInterrupt(uint8_t u8IicIndex, FCIIC_InterruptType *pIntCfg) +{ + FCIIC_Type *pFciic; + + pFciic = (FCIIC_Type *)s_aFCIIC_InstanceTable[u8IicIndex]; + + if ((pIntCfg->bEnErrorInterrupt != 0U) || (pIntCfg->bEnRxInterrupt != 0U)) + { + /* enable global interrupt for pFciic */ + IntMgr_EnableInterrupt((IRQn_Type)((uint8_t)((uint8_t)FCIIC0_IRQn + u8IicIndex))); + /* IntMag_ReplaceHandler(FCIIC0_IRQn+u8IicIndex,u8IicIndex==0?FCIIC0_IRQHandler:FCIIC1_IRQHandler); */ + } + + if (pIntCfg->bEnErrorInterrupt != 0U) + { + FCIIC_Master_HWA_EnableErrorInterrupt(pFciic); + s_aFCIIC_ErrorNotifyTable[u8IicIndex] = pIntCfg->pErrorNotify; + } + + if (pIntCfg->bEnRxInterrupt != 0U) + { + /* pFciic->MIER |= FCIIC_MIER_RDIE_MASK; */ + FCIIC_Master_HWA_EnableReceiveInterrupt(pFciic); + s_aFCIIC_RxNotifyTable[u8IicIndex] = pIntCfg->pRxNotify; + } + + return 0U; +} + + + + +/** + * \brief This Function is used to transmit data in master mode + * + * \param u8IicIndex Iic Index, 0,1 + * \param pTxData contains IIC instance and buffer address + * \return 0 is ok, others are not ok + */ +uint8_t FCIIC_Master_Transmit(uint8_t u8IicIndex, FCIIC_TxDataType *pTxData) +{ + uint8_t u8RetVal; + FCIIC_Type *pFciic; + + pFciic = (FCIIC_Type *)s_aFCIIC_InstanceTable[u8IicIndex]; + + /* clear error flag */ + /* CheckAndClear(pFciic); */ + + /* check tx data flag */ + u8RetVal = FCIIC_Master_HWA_GetStatus(pFciic, FCIIC_MSR_TDF_STATUS); + + /* pFciic->MSR |= FCIIC_MSR_FEF_MASK; */ /* clear fifo error error */ + if (u8RetVal == 1U) + { + FCIIC_Master_HWA_Transmit(pFciic, pTxData->eCmd, pTxData->u8Data); + } + + return (uint8_t)(1U >> u8RetVal); +} + + + +/** + * \brief This Function is used to get master status + * + * \param u8IicIndex is IIC instance + * \param eStatus is status type enumeration + * \return 0 is ok, others are not ok + */ +uint8_t FCIIC_Master_GetStatus(uint8_t u8IicIndex, FCIIC_MasterStatusType eStatus) +{ + FCIIC_Type *pFciic = (FCIIC_Type *)s_aFCIIC_InstanceTable[u8IicIndex]; + return (uint8_t)(1U >> FCIIC_Master_HWA_GetStatus(pFciic, eStatus)); +} + + +/** + * \brief This Function is used to receive data when polling (not used when rx interrupt enabled) in master mode + * + * \param u8IicIndex Iic Index, 0,1 + * \param pRxData contains IIC instance + * \return 0 is ok, others are not ok + */ +uint8_t FCIIC_Master_Receive(uint8_t u8IicIndex, FCIIC_RxDataType *pRxData) +{ + FCIIC_Type *pFciic; + uint8_t u8RetVal; + + pFciic = (FCIIC_Type *)s_aFCIIC_InstanceTable[u8IicIndex]; + + /* CheckAndClear(pFciic); */ + + + /* check receive flag */ + u8RetVal = FCIIC_Master_HWA_GetStatus(pFciic, FCIIC_MSR_RDF_STATUS); + + /* u8RetVal = (pFciic->MRDR & FCIIC_MRDR_RXEMPTY_MASK)>>FCIIC_MRDR_RXEMPTY_SHIFT; */ + + if (u8RetVal == 1U) + { + /* copy data */ + pRxData->u8Data = FCIIC_Master_HWA_Receive(pFciic); + } + + return (uint8_t)(1U >> u8RetVal); +} + +/** + * \brief This Function is used to get master error value + * + * \param u8IicIndex Iic Index, 0,1 + * \return error value + */ +uint32_t FCIIC_Master_GetError(uint8_t u8IicIndex) +{ + FCIIC_Type *pFciic; + uint32_t u32RetVal; + + pFciic = (FCIIC_Type *)s_aFCIIC_InstanceTable[u8IicIndex]; + + /* check receive flag */ + u32RetVal = FCIIC_Master_HWA_GetErrorFlag(pFciic); + + return u32RetVal; +} + +/** + * \brief This Function is used to clear master error value + * + * \param u8IicIndex Iic Index, 0,1 + */ +void FCIIC_Master_ClrError(uint8_t u8IicIndex) +{ + FCIIC_Type *pFciic; + + pFciic = (FCIIC_Type *)s_aFCIIC_InstanceTable[u8IicIndex]; + + /* clear receive flag */ + FCIIC_Master_HWA_ClrErrorFlag(pFciic); + +} + +/** + * \brief This Function is used to configure IIC slave interrupt + * + * \param u8IicIndex Iic Index, 0,1 + * \param pIntCfg contains IIC instance and interrupt callback functions + * \return 0 is ok, others are not ok + */ +uint8_t FCIIC_Slave_SetInterrupt(uint8_t u8IicIndex, FCIIC_InterruptType *pIntCfg) +{ + FCIIC_Type *pFciic; + + pFciic = (FCIIC_Type *)s_aFCIIC_InstanceTable[u8IicIndex]; + + if ((pIntCfg->bEnErrorInterrupt != 0U) || (pIntCfg->bEnRxInterrupt != 0U)) + { + /* enable global interrupt for pFciic */ + IntMgr_EnableInterrupt((IRQn_Type)((uint8_t)((uint8_t)FCIIC0_IRQn + u8IicIndex))); + /* IntMag_ReplaceHandler(FCIIC0_IRQn+u8IicIndex,u8IicIndex==0?FCIIC0_IRQHandler:FCIIC1_IRQHandler); */ + } + + + if (pIntCfg->bEnErrorInterrupt != 0U) + { + FCIIC_Slave_HWA_EnableErrorInterrupt(pFciic); + s_aFCIIC_ErrorNotifyTable[u8IicIndex] = pIntCfg->pErrorNotify; + } + + if (pIntCfg->bEnRxInterrupt != 0U) + { + FCIIC_Slave_HWA_EnableReceiveInterrupt(pFciic); + + s_aFCIIC_RxNotifyTable[u8IicIndex] = pIntCfg->pRxNotify; + } + + return 0U; +} + + +/** + * \brief This Function is used to transmit data in slave mode + * + * \param u8IicIndex Iic Index, 0,1 + * \param pTxData contains IIC instance and buffer address + * \return 0 is ok, others are not ok + */ +uint8_t FCIIC_Slave_Transmit(uint8_t u8IicIndex, FCIIC_TxDataType *pTxData) +{ + #ifdef FCIIC_TX_CHECK + uint8_t u8RetVal; + uint32_t u32TryTick; + uint32_t u32TryCount; + #endif + FCIIC_Type *pFciic; + + pFciic = (FCIIC_Type *)s_aFCIIC_InstanceTable[u8IicIndex]; + + #ifdef FCIIC_TX_CHECK + /* u8RetVal = (pFciic->SSR & FCIIC_SSR_TDF_MASK)>> FCIIC_SSR_TDF_SHIFT; */ + + /* pFciic->SSR |= FCIIC_SSR_TREF_MASK; */ /* clear receive & transmit error error */ + /* if(u8RetVal) */ + { + #endif + FCIIC_Slave_HWA_Transmit(pFciic, pTxData->u8Data); + #ifdef FCIIC_TX_CHECK + /* after transmit completed, close TE */ + /* u8RetVal = 0; */ + /* u32TryCount = 0; */ + /* while(u8RetVal==0 && u32TryCount++<100) */ + /* { */ + /* u8RetVal = (pFciic->SSR & FCIIC_SSR_TDF_MASK)>> FCIIC_SSR_TDF_SHIFT; */ + /* u32TryTick = 0; */ + /* while(u32TryTick++<100){} */ + + /* } */ + } + #endif + + return 0U; +} + + + +/** + * \brief This Function is used to receive data when polling (not used when rx interrupt enabled) in slave mode + * + * \param u8IicIndex Iic Index, 0,1 + * \param pRxData contains IIC instance and buffer address + * \return 0 is ok, others are not ok + */ +uint8_t FCIIC_Slave_Receive(uint8_t u8IicIndex, FCIIC_RxDataType *pRxData) +{ + FCIIC_Type *pFciic; + uint8_t u8RetVal; + + pFciic = (FCIIC_Type *)s_aFCIIC_InstanceTable[u8IicIndex]; + + + /* check slave receive flag */ + u8RetVal = FCIIC_Slave_HWA_GetStatus(pFciic, FCIIC_SSR_RDF_STATUS); + + /* u8RetVal = (pFciic->MRDR & FCIIC_MRDR_RXEMPTY_MASK)>>FCIIC_MRDR_RXEMPTY_SHIFT; */ + + if (u8RetVal != 0U) + { + /* get received data */ + pRxData->u8Data = FCIIC_Slave_HWA_Receive(pFciic); + } + + return (uint8_t)(1U >> u8RetVal); +} + + +/** + * \brief This Function is used to get slave error value + * + * \param u8IicIndex Iic Index, 0,1 + * \return error value + */ +uint32_t FCIIC_Slave_GetError(uint8_t u8IicIndex) +{ + FCIIC_Type *pFciic; + uint32_t u32RetVal; + + pFciic = (FCIIC_Type *)s_aFCIIC_InstanceTable[u8IicIndex]; + + /* check receive flag */ + u32RetVal = FCIIC_Slave_HWA_GetErrorFlag(pFciic); + + return u32RetVal; +} + +/** + * \brief This Function is used to clear slave error value + * + * \param u8IicIndex Iic Index, 0,1 + */ +void FCIIC_Slave_ClrError(uint8_t u8IicIndex) +{ + FCIIC_Type *pFciic; + + pFciic = (FCIIC_Type *)s_aFCIIC_InstanceTable[u8IicIndex]; + + /* clear receive flag */ + FCIIC_Slave_HWA_ClrErrorFlag(pFciic); +} + + +/* ################################################################################## */ +/* ############################## Interrupt Services ################################ */ + + +void FCIIC0_IRQHandler(void) +{ + FCIIC_LL_MasterIRQnHandler(0U); + FCIIC_LL_SlaveIRQnHandler(0U); +} + +void FCIIC1_IRQHandler(void) +{ + FCIIC_LL_MasterIRQnHandler(1U); + FCIIC_LL_SlaveIRQnHandler(1U); +} + + diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_fcpit.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_fcpit.c new file mode 100644 index 0000000..5c6bd51 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_fcpit.c @@ -0,0 +1,524 @@ +/** + * @file fc7xxx_driver_fcpit.h + * @author Flagchip + * @brief FC7xxx FCPIT driver type definition and API + * @version 0.1.0 + * @date 2024-01-10 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/******************************************************************************** +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2024-01-10 Flagchip0076 N/A First version for FC7240 +********************************************************************************/ +#include "fc7xxx_driver_fcpit.h" +#include "interrupt_manager.h" + + +/********* Local Variables ************/ +/** @brief FCPIT instance list */ +static FCPIT_Type *s_pFcpitInstanceTable[FCPIT_INSTANCE_COUNT] = FCPIT_BASE_PTRS; + +/** @brief Fcpit user defined interrupt function */ +static FCPIT_InterruptCallBackType s_aFcpitIntNotifyTab[FCPIT_INSTANCE_COUNT][MAX_FCPIT_CHANNEL_NUM] = {0}; + + + + +/** @brief Fcpit interrupt entry */ +void FCPIT0_IRQHandler(void); + +/** @brief Fcpit common interrupt handle function */ +static void Fcpit_CommonProcessInterrupt(const FCPIT_InstanceType eFcpit, const FCPIT_ChannelType eChannel); + + +/** + * @brief Initialize Fcpit instance. + * @param eFcpit instance + * @param pInitStruct Fcpit initialization structure + * @return Fcpit return type + */ +FCPIT_StatusType FCPIT_Init(const FCPIT_InstanceType eFcpit, const FCPIT_InitType *const pInitStruct) +{ + FCPIT_Type *pFcpit; + FCPIT_StatusType eRet = FCPIT_STATUS_SUCCESS; + + if ( ((uint32_t)eFcpit >= FCPIT_INSTANCE_COUNT) || (NULL == pInitStruct) ) + { + eRet = FCPIT_STATUS_PARAM_INVALID; + } + else + { + pFcpit = s_pFcpitInstanceTable[eFcpit]; + /*Enable module clock*/ + FCPIT_HWA_EnableModule(pFcpit); + if (pInitStruct->bDebugEn) + { + FCPIT_HWA_SetChannelRunOnDebug(pFcpit); + } + else + { + FCPIT_HWA_SetChannelStopOnDebug(pFcpit); + } + + if (pInitStruct->bLowPowerModeEn) + { + FCPIT_HWA_SetChannelRunOnLpm(pFcpit); + } + else + { + FCPIT_HWA_SetChannelStopOnLpm(pFcpit); + } + /* w1c , clear channel interrupt flag*/ + FCPIT_HWA_ClearChannelsInterruptFlag(pFcpit, (uint32_t)1U << (uint32_t)pInitStruct->eFcpitChannel); + + FCPIT_HWA_ConfigChannel(pFcpit, pInitStruct->eFcpitChannel, (uint32_t)0U); + FCPIT_HWA_ConfigChannelMode(pFcpit, pInitStruct->eFcpitChannel, pInitStruct->eMode); + + if (pInitStruct->bChainModeEn) + { + if (pInitStruct->eFcpitChannel > FCPIT_CHANNEL_0) + { + FCPIT_HWA_EnableChannelChainMode(pFcpit, pInitStruct->eFcpitChannel); + } + else + { + /* channel 0 is the first channel can not be chained to last channel */ + eRet = FCPIT_STATUS_PARAM_INVALID; + } + } + else + { + /*Chain mode is not enabled, no operation */ + } + + FCPIT_HWA_SetChannelValue(pFcpit, pInitStruct->eFcpitChannel, pInitStruct->u32TimerValue); + } + + return eRet; +} + +/** + * @brief Initialize Fcpit trigger configuration + * @param eFcpit instance + * @param pTrgStruct Fcpit trigger structure + * @return Fcpit return type + */ +FCPIT_StatusType FCPIT_InitTrigger(const FCPIT_InstanceType eFcpit, const FCPIT_TrggerType *const pTrgStruct) +{ + FCPIT_Type *pFcpit; + FCPIT_StatusType eRet = FCPIT_STATUS_SUCCESS; + + if ( ((uint32_t)eFcpit >= FCPIT_INSTANCE_COUNT) || (NULL == pTrgStruct) ) + { + eRet = FCPIT_STATUS_PARAM_INVALID; + } + else + { + pFcpit = s_pFcpitInstanceTable[eFcpit]; + if ( (uint32_t)0U == FCPIT_HWA_ReadModuleEnable(pFcpit) ) + { + eRet = FCPIT_STATUS_FUNCTION_ERROR; + } + else + { + if (pTrgStruct->bStartOnTrigger) + { + FCPIT_HWA_SetChannelStartOnTrig(pFcpit, pTrgStruct->eFcpitChannel); + } + else + { + FCPIT_HWA_ClearChannelStartOnTrig(pFcpit, pTrgStruct->eFcpitChannel); + } + + if (pTrgStruct->bStopOnInterrupt) + { + FCPIT_HWA_SetChannelStopOnInterrupt(pFcpit, pTrgStruct->eFcpitChannel); + } + else + { + FCPIT_HWA_ClearChannelStopOnInterrupt(pFcpit, pTrgStruct->eFcpitChannel); + } + + if (pTrgStruct->bReloadOnTrigger) + { + FCPIT_HWA_SetChannelReloadOnTrig(pFcpit, pTrgStruct->eFcpitChannel); + } + else + { + FCPIT_HWA_ClearChannelReloadOnTrig(pFcpit, pTrgStruct->eFcpitChannel); + } + + if (FCPIT_TRIGGER_EXTERNAL != pTrgStruct->eTriggerSel) + { + FCPIT_HWA_SetChannelTriggerSrc(pFcpit, pTrgStruct->eFcpitChannel); + FCPIT_HWA_SelectChannelTrigger(pFcpit, pTrgStruct->eFcpitChannel, (uint8_t)pTrgStruct->eTriggerSel); + } + else + { + FCPIT_HWA_ClearChannelTriggerSrc(pFcpit, pTrgStruct->eFcpitChannel); + FCPIT_HWA_SelectChannelTrigger(pFcpit, pTrgStruct->eFcpitChannel, (uint8_t)pTrgStruct->eFcpitChannel); + } + + } + + } + + return eRet; +} + +/** + * @brief De-initialize Fcpit instance. + * @param eFcpit instance + */ +FCPIT_StatusType FCPIT_Deinit(const FCPIT_InstanceType eFcpit) +{ + uint8_t u8Index; + FCPIT_Type *pFcpit; + FCPIT_StatusType eRet = FCPIT_STATUS_SUCCESS; + + if ((uint32_t)eFcpit >= FCPIT_INSTANCE_COUNT) + { + eRet = FCPIT_STATUS_PARAM_INVALID; + } + else + { + pFcpit = s_pFcpitInstanceTable[eFcpit]; + FCPIT_HWA_ConfigModule(pFcpit, (uint32_t)FCPIT_MCR_M_CEN_MASK); + FCPIT_HWA_ClearChannelsInterruptFlag(pFcpit, (uint32_t)(FCPIT_MSR_TIF3_MASK | FCPIT_MSR_TIF2_MASK | FCPIT_MSR_TIF1_MASK | + FCPIT_MSR_TIF0_MASK)); + FCPIT_HWA_DisableChannelsInterrupt(pFcpit, (uint32_t)0U); + for (u8Index = 0U; u8Index < MAX_FCPIT_CHANNEL_NUM; u8Index++) + { + FCPIT_HWA_ConfigChannel(pFcpit, (FCPIT_ChannelType)u8Index, (uint32_t)0U); + FCPIT_HWA_SetChannelValue(pFcpit, (FCPIT_ChannelType)u8Index, (uint32_t)0U); + s_aFcpitIntNotifyTab[eFcpit][u8Index] = NULL; + } + FCPIT_HWA_ConfigModule(pFcpit, (uint32_t)0U); + } + + return eRet; +} + +/** + * @brief Initialize Fcpit interrupt functionality + * @param eFcpit instance + * @param pIntStruct Fcpit interrupt structure + * @return Fcpit return type + * @note this function will stop timer + */ +FCPIT_StatusType FCPIT_InitInterrupt(const FCPIT_InstanceType eFcpit, const FCPIT_IntType *const pIntStruct) +{ + FCPIT_Type *pFcpit; + FCPIT_StatusType eRet = FCPIT_STATUS_SUCCESS; + + if ( ((uint8_t)eFcpit >= FCPIT_INSTANCE_COUNT) || (NULL == pIntStruct) ) + { + eRet = FCPIT_STATUS_PARAM_INVALID; + } + else + { + pFcpit = s_pFcpitInstanceTable[eFcpit]; + if ((uint32_t)0U == (uint32_t)FCPIT_HWA_ReadModuleEnable(pFcpit)) + { + eRet = FCPIT_STATUS_FUNCTION_ERROR; + } + else + { + FCPIT_HWA_DisableChannel(pFcpit, pIntStruct->eFcpitChannel); + /* w1c , clear channel interrupt flag*/ + FCPIT_HWA_ClearChannelsInterruptFlag(pFcpit, (uint32_t)1U << (uint32_t)pIntStruct->eFcpitChannel); + if (pIntStruct->bChannelIsrEn) + { + FCPIT_HWA_EnableChannelsInterrupt(pFcpit, (uint32_t)1U << (uint32_t)pIntStruct->eFcpitChannel); + s_aFcpitIntNotifyTab[eFcpit][pIntStruct->eFcpitChannel] = pIntStruct->pIsrNotify; + } + else + { + FCPIT_HWA_DisableChannelsInterrupt(pFcpit, (uint32_t)1U << (uint32_t)pIntStruct->eFcpitChannel); + s_aFcpitIntNotifyTab[eFcpit][pIntStruct->eFcpitChannel] = pIntStruct->pIsrNotify; + } + } + } + + return eRet; +} + +/** + * @brief Enable Fcpit interrupt + * @param eFcpit instance + * @param eChannel Fcpit channel + * @return Fcpit return type + */ +FCPIT_StatusType FCPIT_EnableInterrupt(const FCPIT_InstanceType eFcpit, const FCPIT_ChannelType eChannel) +{ + FCPIT_Type *pFcpit; + FCPIT_StatusType eRet = FCPIT_STATUS_SUCCESS; + + if ( ((uint32_t)eFcpit >= FCPIT_INSTANCE_COUNT) || ((uint32_t)eChannel >= MAX_FCPIT_CHANNEL_NUM)) + { + eRet = FCPIT_STATUS_PARAM_INVALID; + } + else + { + pFcpit = s_pFcpitInstanceTable[eFcpit]; + + if ((uint32_t)0U == (uint32_t)FCPIT_HWA_ReadModuleEnable(pFcpit)) + { + eRet = FCPIT_STATUS_FUNCTION_ERROR; + } + else + { + FCPIT_HWA_DisableChannel(pFcpit, eChannel); + /* w1c , clear channel interrupt flag*/ + FCPIT_HWA_ClearChannelsInterruptFlag(pFcpit, (uint32_t)1U << (uint32_t)eChannel); + FCPIT_HWA_EnableChannelsInterrupt(pFcpit, (uint32_t)1U << (uint32_t)eChannel); + FCPIT_HWA_EnableChannel(pFcpit, eChannel); + } + + } + + return eRet; +} + +/** + * @brief Disable Fcpit interrupt + * @param eFcpit instance + * @param eChannel Fcpit channel + * @return Fcpit return type + */ +FCPIT_StatusType FCPIT_DisableInterrupt(const FCPIT_InstanceType eFcpit, const FCPIT_ChannelType eChannel) +{ + FCPIT_Type *pFcpit; + FCPIT_StatusType eRet = FCPIT_STATUS_SUCCESS; + + if ( ((uint32_t)eFcpit >= FCPIT_INSTANCE_COUNT) || ((uint32_t)eChannel >= MAX_FCPIT_CHANNEL_NUM) ) + { + eRet = FCPIT_STATUS_PARAM_INVALID; + } + else + { + pFcpit = s_pFcpitInstanceTable[eFcpit]; + + if ((uint32_t)0U == (uint32_t)FCPIT_HWA_ReadModuleEnable(pFcpit)) + { + eRet = FCPIT_STATUS_FUNCTION_ERROR; + } + else + { + FCPIT_HWA_DisableChannel(pFcpit, eChannel); + /* w1c , clear channel interrupt flag*/ + FCPIT_HWA_ClearChannelsInterruptFlag(pFcpit, (uint32_t)1U << (uint32_t)eChannel); + FCPIT_HWA_DisableChannelsInterrupt(pFcpit, (uint32_t)1U << (uint32_t)eChannel); + FCPIT_HWA_EnableChannel(pFcpit, eChannel); + } + } + + return eRet; +} + +/** + * @brief Fcpit start timer + * @param eFcpit instance + * @param eChannel Fcpit channel + * @return Fcpit return type + */ +FCPIT_StatusType FCPIT_Start(const FCPIT_InstanceType eFcpit, const FCPIT_ChannelType eChannel) +{ + FCPIT_Type *pFcpit; + FCPIT_StatusType eRet = FCPIT_STATUS_SUCCESS; + if ( ((uint32_t)eFcpit >= FCPIT_INSTANCE_COUNT) || ((uint32_t)eChannel >= MAX_FCPIT_CHANNEL_NUM) ) + { + eRet = FCPIT_STATUS_PARAM_INVALID; + } + else + { + pFcpit = s_pFcpitInstanceTable[eFcpit]; + if ((uint32_t)0U == (uint32_t)FCPIT_HWA_ReadModuleEnable(pFcpit)) + { + eRet = FCPIT_STATUS_FUNCTION_ERROR; + } + + if (FCPIT_STATUS_SUCCESS == eRet) + { + FCPIT_HWA_EnableChannel(pFcpit, eChannel); + } + } + + return eRet; +} + +/** + * @brief Fcpit stop + * @param eFcpit instance + * @param eChannel Fcpit channel + * @return Fcpit return type + */ +FCPIT_StatusType FCPIT_Stop(const FCPIT_InstanceType eFcpit, const FCPIT_ChannelType eChannel) +{ + FCPIT_Type *pFcpit; + FCPIT_StatusType eRet = FCPIT_STATUS_SUCCESS; + + if ( ((uint32_t)eFcpit >= FCPIT_INSTANCE_COUNT) || ((uint32_t)eChannel >= MAX_FCPIT_CHANNEL_NUM) ) + { + eRet = FCPIT_STATUS_PARAM_INVALID; + } + else + { + pFcpit = s_pFcpitInstanceTable[eFcpit]; + if ((uint32_t)0U == (uint32_t)FCPIT_HWA_ReadModuleEnable(pFcpit)) + { + eRet = FCPIT_STATUS_FUNCTION_ERROR; + } + else + { + FCPIT_HWA_DisableChannel(pFcpit, eChannel); + } + } + + return eRet; +} + +/** + * @brief Immediately update Fcpit channel value + * @param eFcpit instance + * @param eChannel Fcpit channel + * @param u32ChannelValue in/Out value + * @return Fcpit return type + */ +FCPIT_StatusType FCPIT_ImmediateUpdateChannelValue(const FCPIT_InstanceType eFcpit, const FCPIT_ChannelType eChannel, const uint32_t u32ChannelValue) +{ + FCPIT_Type *pFcpit; + FCPIT_StatusType eRet; + + pFcpit = s_pFcpitInstanceTable[eFcpit]; + + eRet = FCPIT_Stop(eFcpit, eChannel); + + if (FCPIT_STATUS_SUCCESS == eRet) + { + FCPIT_HWA_SetChannelValue(pFcpit, eChannel, u32ChannelValue); + eRet = FCPIT_Start(eFcpit, eChannel); + } + else + { + return eRet; + } + + return eRet; +} + +/** + * @brief Update Fcpit channel value + * @param eFcpit instance + * @param eChannel Fcpit channel + * @param u32ChannelValue in/Out value + * @return Fcpit return type + */ +FCPIT_StatusType FCPIT_UpdateChannelValue(const FCPIT_InstanceType eFcpit, const FCPIT_ChannelType eChannel, const uint32_t u32ChannelValue) +{ + FCPIT_Type *pFcpit; + FCPIT_StatusType eRet = FCPIT_STATUS_SUCCESS; + + if ( ((uint32_t)eFcpit >= FCPIT_INSTANCE_COUNT) || ((uint32_t)eChannel >= MAX_FCPIT_CHANNEL_NUM) ) + { + eRet = FCPIT_STATUS_PARAM_INVALID; + } + else + { + pFcpit = s_pFcpitInstanceTable[eFcpit]; + if ((uint32_t)0U == (uint32_t)FCPIT_HWA_ReadModuleEnable(pFcpit)) + { + eRet = FCPIT_STATUS_FUNCTION_ERROR; + } + + if (FCPIT_STATUS_SUCCESS == eRet) + { + FCPIT_HWA_SetChannelValue(pFcpit, eChannel, u32ChannelValue); + } + } + + return eRet; +} + +/** + * @brief read Fcpit channel time stamps. + * #param eFcpit Fcpit instance + * @param eChannel Fcpit channel + * @param *u32timeStampValue value + * @return Fcpit return type + */ + +FCPIT_StatusType FCPIT_ReadTimstamp(const FCPIT_InstanceType eFcpit, const FCPIT_ChannelType eChannel,uint32_t *u32timeStampValue) +{ + FCPIT_Type *pFcpit; + FCPIT_StatusType eRet = FCPIT_STATUS_SUCCESS; + if ( ((uint32_t)eFcpit >= FCPIT_INSTANCE_COUNT) || ((uint32_t)eChannel >= MAX_FCPIT_CHANNEL_NUM) ) + { + eRet = FCPIT_STATUS_PARAM_INVALID; + } + pFcpit = s_pFcpitInstanceTable[eFcpit]; + + if((uint32_t)0x3u != FCPIT_HWA_ReadChannelMode(pFcpit,eChannel)) + { + eRet = FCPIT_STATUS_PARAM_INVALID; + } + else + { + + *u32timeStampValue = FCPIT_HWA_ReadChannelValue(pFcpit,eChannel); + } + return eRet; +} + + + +/** + * @brief Fcpit common interrupt handle function + * @param eFcpit instance + * @param eChannel Fcpit interrupt channel + */ +static void Fcpit_CommonProcessInterrupt(const FCPIT_InstanceType eFcpit, const FCPIT_ChannelType eChannel) +{ + if (NULL != s_aFcpitIntNotifyTab[eFcpit][eChannel]) + { + s_aFcpitIntNotifyTab[eFcpit][eChannel](); + } +} + +/** + * @brief Fcpit_0 interrupt handler entry + * + */ +void FCPIT0_IRQHandler(void) +{ + uint32_t u32TifValue = FCPIT_HWA_ReadEnableInterruptFlag(FCPIT) & FCPIT_HWA_ReadInterruptFlag(FCPIT); + + if ((u32TifValue & FCPIT_MSR_TIF0_MASK) != 0u) + { + Fcpit_CommonProcessInterrupt(FCPIT_0, FCPIT_CHANNEL_0); + FCPIT_HWA_ClearChannelsInterruptFlag(FCPIT, (uint32_t)FCPIT_MSR_TIF0_MASK); + } + if ((u32TifValue & FCPIT_MSR_TIF1_MASK) != 0u) + { + Fcpit_CommonProcessInterrupt(FCPIT_0, FCPIT_CHANNEL_1); + FCPIT_HWA_ClearChannelsInterruptFlag(FCPIT, (uint32_t)FCPIT_MSR_TIF1_MASK); + } + if ((u32TifValue & FCPIT_MSR_TIF2_MASK) != 0u) + { + Fcpit_CommonProcessInterrupt(FCPIT_0, FCPIT_CHANNEL_2); + FCPIT_HWA_ClearChannelsInterruptFlag(FCPIT, (uint32_t)FCPIT_MSR_TIF2_MASK); + } + if ((u32TifValue & FCPIT_MSR_TIF3_MASK) != 0u) + { + Fcpit_CommonProcessInterrupt(FCPIT_0, FCPIT_CHANNEL_3); + FCPIT_HWA_ClearChannelsInterruptFlag(FCPIT, (uint32_t)FCPIT_MSR_TIF3_MASK); + } + +} + diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_fcsmu.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_fcsmu.c new file mode 100644 index 0000000..61df4e6 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_fcsmu.c @@ -0,0 +1,408 @@ +/** + * @file fc7xxx_driver_fcsmu.c + * @author Flagchip + * @brief FC7xxx FCSMU driver type definition and API + * @version 0.1.0 + * @date 2024-01-14 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-14 qxw0100 N/A First version for FC7240 + ******************************************************************************** */ +#include "fc7xxx_driver_fcsmu.h" +#include "HwA_csc.h" + +/* ################################################################################## */ +/* ####################################### Macro #################################### */ + +#define FCSMU_FST_UNLOCK_KEY 0x951413CFU +#define FCSMU_OPC1_UNLOCK_KEY 0xFC2020CFU +#define FCSMU_OPC2_UNLOCK_KEY 0x20FCCF20U +#define FCSMU_CONFIG_TMEP_UNLOCK_KEY 0xFCU + +/* ################################################################################## */ +/* ################################### Type define ################################## */ + +/* ################################################################################## */ +/* ################################ Local Variables ################################# */ +static FCSMU_Type *const s_apFcsmuBase[FCSMU_INSTANCE_COUNT] = FCSMU_BASE_PTRS; +static FCSMU_ISRCallbackType s_apFcsmuISRCallback = NULL; + +/* ################################################################################## */ +/* ########################### Local Prototype Functions ############################ */ + +/* ################################################################################## */ +/* ######################### Global prototype Functions ############################ */ +void FCSMU0_IRQHandler(void); +/* ################################################################################## */ +/* ################################ Local Functions ################################ */ + +/* ################################################################################## */ +/* ################################ Global Functions ################################ */ + +FCSMU_StatusType FCSMU_init(const FCSMU_InitCfgType *pInitConfig) +{ + DEV_ASSERT(pInitConfig != NULL); + FCSMU_StatusType eRet; + + FCSMU_Type *const pFcsmu = s_apFcsmuBase[FCSMU_INSTANCE_0]; + + eRet = FCSMU_TransStateNTC(); + + if (eRet != FCSMU_STATUS_SUCCESS) + { + return eRet; + } + + if (pInitConfig->u32WarnTo > 432000U) + { + FCSMU_HWA_SetWaringTo(pFcsmu, 432000U); + } + else + { + FCSMU_HWA_SetWaringTo(pFcsmu, pInitConfig->u32WarnTo); + } + FCSMU_HWA_ClearCfgToIrq(pFcsmu); + FCSMU_HWA_SetWarningEn0(pFcsmu, pInitConfig->u32WarnChannel); + FCSMU_HWA_SetWarningIen(pFcsmu, pInitConfig->u32WarnInterruptChannel); + FCSMU_HWA_SetFaultIen(pFcsmu, pInitConfig->u32FaultInterruptChannel); + FCSMU_HWA_SetFRST0(pFcsmu, pInitConfig->u32FaultResetChannel); + FCSMU_HWA_SetFe0(pFcsmu, pInitConfig->u32FaultChannel); + FCSMU_HWA_SetFccr0(pFcsmu, pInitConfig->u32SoftwareClearedChannel); + + eRet = FCSMU_TransStateCTN(); + FCSMU_HWA_SetTempUnlk(pFcsmu, 0xFFU); + + s_apFcsmuISRCallback = pInitConfig->pISRCallback; + + return eRet; +} + +FCSMU_StatusType FCSMU_ConfigStatusOutput(FCSMU_StatusOutputConfigType *pInitConfig) +{ + + DEV_ASSERT(pInitConfig != NULL); + + FCSMU_Type *const pFcsmu = s_apFcsmuBase[FCSMU_INSTANCE_0]; + uint32_t u32TempValue; + FCSMU_StatusType eRet; + + if (pInitConfig->eFastMode == true) + { + if (pInitConfig->eProtocal != FCSMU_SOUT_PROTOCOL_DUAL_RAIL && pInitConfig->eProtocal != FCSMU_SOUT_PROTOCOL_TIME_SWITCH) + { + return FCSMU_STATUS_ERROR; + } + } + + u32TempValue = FCSMU_SOCTRL_SOUT_PEN(pInitConfig->bEnable) | + FCSMU_SOCTRL_FASTEN(pInitConfig->eFastMode) | + FCSMU_SOCTRL_POLSW(pInitConfig->ePolarity) | + FCSMU_SOCTRL_SOUT_PTC(pInitConfig->eProtocal) | + FCSMU_SOCTRL_DIVEX(pInitConfig->bDivex) | + FCSMU_SOCTRL_SOUT_CTRL(pInitConfig->eSoutCtrl) | + FCSMU_SOCTRL_SOUT_DIV(pInitConfig->u32Divder) | + FCSMU_SOCTRL_SMRDT(pInitConfig->u32Delaytimer); + + eRet = FCSMU_TransStateNTC(); + + if (eRet != FCSMU_STATUS_SUCCESS) + { + return eRet; + } + + FCSMU_HWA_SetSoctrl(pFcsmu, u32TempValue); + FCSMU_HWA_SetSoutEn(pFcsmu, pInitConfig->u32SoutChannel); + + eRet = FCSMU_TransStateCTN(); + + return eRet; +} + +void FCSMU_CrcGen(void) +{ + FCSMU_Type *const pFcsmu = s_apFcsmuBase[FCSMU_INSTANCE_0]; + FCSMU_HWA_GenerateCrc(pFcsmu); +} + +bool FCSMU_IsCrcBusy(void) +{ + FCSMU_Type *const pFcsmu = s_apFcsmuBase[FCSMU_INSTANCE_0]; + return FCSMU_HWA_GetCrcBusy(pFcsmu); +} + +FCSMU_StatusType FCSMU_CrcConfig(FCSMU_CrcModeType eMode) +{ + FCSMU_Type *const pFcsmu = s_apFcsmuBase[FCSMU_INSTANCE_0]; + uint32_t u32TimeoutTimes = 65535U; + FCSMU_StatusType eRet = FCSMU_STATUS_SUCCESS; + + FCSMU_HWA_GenerateCrc(pFcsmu); + while (FCSMU_HWA_GetCrcBusy(pFcsmu) == FCSMU_Crc_STATE_BUSY) + { + u32TimeoutTimes--; + if (u32TimeoutTimes == 0U) + { + eRet = FCSMU_STATUS_ERROR; + break; + } + } + + if (eRet == FCSMU_STATUS_SUCCESS) + { + if (eMode == FCSMU_CRC_TRIGGER_MODE) + { + FCSMU_HWA_EnableTrigger(pFcsmu, true); + } + else + { + + } + + CSC0_HWA_CTRL4_EnableReqToSMU(CSC_SMU_SCF_IRQ); + FCSMU_HWA_EnableErrorOutput(pFcsmu, true); + FCSMU_HWA_EnableCrcChecker(pFcsmu, true); + } + + return eRet; + +} + +FCSMU_StatusType FCSMU_ClearFaultFlag(uint32_t u32FaultChannel) +{ + FCSMU_Type *const pFcsmu = s_apFcsmuBase[FCSMU_INSTANCE_0]; + uint32_t u32TimeoutTimes = 65535U; + FCSMU_StatusType eRet = FCSMU_STATUS_SUCCESS; + + FCSMU_HWA_SetFunlk(pFcsmu, FCSMU_FST_UNLOCK_KEY); + FCSMU_HWA_SetFst0(pFcsmu, u32FaultChannel); + + while (FCSMU_HWA_GetCtrlOps(pFcsmu) != (uint32_t)FCSMU_OP_STATE_SUCCESSFUL) + { + u32TimeoutTimes--; + if (u32TimeoutTimes == 0U) + { + eRet = FCSMU_STATUS_ERROR; + break; + } + } + + return eRet; +} + +FCSMU_StatusType FCSMU_TransStateCTN(void) +{ + FCSMU_Type *const pFcsmu = s_apFcsmuBase[FCSMU_INSTANCE_0]; + uint32_t u32TimeoutTimes; + uint32_t u32RetryTimes = 65535U; + uint32_t u32Temp; + FCSMU_StatusType eRet = FCSMU_STATUS_ERROR; + + while (u32RetryTimes != 0U) + { + u32TimeoutTimes = 65535U; + u32Temp = (uint32_t)FCSMU_HWA_GetCtrl(pFcsmu); + u32Temp |= (uint32_t)FCSMU_OPC_MOVE_TO_NORMAL; + + FCSMU_HWA_SetOprk(pFcsmu, FCSMU_OPC2_UNLOCK_KEY); + FCSMU_HWA_SetCrtl(pFcsmu, u32Temp); + + while (FCSMU_HWA_GetCtrlOps(pFcsmu) != (uint32_t)FCSMU_OP_STATE_SUCCESSFUL) + { + u32TimeoutTimes--; + if (u32TimeoutTimes == 0U) + { + break; + } + } + + if (u32TimeoutTimes != 0U) + { + if (FCSMU_HWA_GetState(pFcsmu) == (uint32_t)FCSMU_STATE_NORMAL) + { + break; + } + } + + u32RetryTimes--; + } + + if (u32RetryTimes != 0U) + { + eRet = FCSMU_STATUS_SUCCESS; + } + + return eRet; +} + +FCSMU_StatusType FCSMU_TransStateNTC(void) +{ + FCSMU_Type *const pFcsmu = s_apFcsmuBase[FCSMU_INSTANCE_0]; + uint32_t u32TimeoutTimes; + uint32_t u32RetryTimes = 65535U; + FCSMU_StatusType eRet = FCSMU_STATUS_ERROR; + uint32_t u32Temp; + + while (u32RetryTimes != 0U) + { + u32TimeoutTimes = 65535U; + u32Temp = FCSMU_HWA_GetCtrl(pFcsmu); + u32Temp |= (uint32_t)FCSMU_OPC_MOVE_TO_CONFIG; + FCSMU_HWA_SetTempUnlk(pFcsmu, FCSMU_CONFIG_TMEP_UNLOCK_KEY); + FCSMU_HWA_SetOprk(pFcsmu, FCSMU_OPC1_UNLOCK_KEY); + FCSMU_HWA_SetCrtl(pFcsmu, u32Temp); + + while (FCSMU_HWA_GetCtrlOps(pFcsmu) != (uint32_t)FCSMU_OP_STATE_SUCCESSFUL) + { + if (FCSMU_HWA_GetCtrlOps(pFcsmu) == (uint32_t)FCSMU_OP_STATE_BUSY) + { + u32TimeoutTimes--; + if (u32TimeoutTimes == 0U) + { + break; + } + } + else + { + break; + } + } + + if (u32TimeoutTimes != 0U) + { + if (FCSMU_HWA_GetState(pFcsmu) == (uint32_t)FCSMU_STATE_CONGIG) + { + break; + } + } + + u32RetryTimes--; + } + + if (u32RetryTimes != 0U) + { + eRet = FCSMU_STATUS_SUCCESS; + } + + return eRet; +} + +void FCSMU_InjectionFault(uint32_t u32ChannelIndex) +{ + FCSMU_Type *const pFcsmu = s_apFcsmuBase[FCSMU_INSTANCE_0]; + + FCSMU_HWA_SetInject(pFcsmu, u32ChannelIndex); +} + +uint32_t FCSMU_GetFaultChannel(void) +{ + FCSMU_Type *const pFcsmu = s_apFcsmuBase[FCSMU_INSTANCE_0]; + + return FCSMU_HWA_GetFst0(pFcsmu); +} + +uint32_t FCSMU_GetIrqState(void) +{ + FCSMU_Type *const pFcsmu = s_apFcsmuBase[FCSMU_INSTANCE_0]; + + return FCSMU_HWA_GetIrqStat(pFcsmu); +} + +uint32_t FCSMU_GetNtfFlag(void) +{ + FCSMU_Type *const pFcsmu = s_apFcsmuBase[FCSMU_INSTANCE_0]; + + return FCSMU_HWA_GetNtf(pFcsmu); +} + +uint32_t FCSMU_GetWtfFlag(void) +{ + FCSMU_Type *const pFcsmu = s_apFcsmuBase[FCSMU_INSTANCE_0]; + + return FCSMU_HWA_GetWtf(pFcsmu); +} + +uint32_t FCSMU_GetNtwFlag(void) +{ + FCSMU_Type *const pFcsmu = s_apFcsmuBase[FCSMU_INSTANCE_0]; + + return FCSMU_HWA_GetNtw(pFcsmu); +} + +static void FCSMUn_IRQHandler(void) +{ + uint32_t u32TempValue = FCSMU_GetIrqState(); + uint32_t u32IrqChannel; + + if ((FCSMU_IRQ_STAT_FAULT_IRQ_MASK & u32TempValue) == FCSMU_IRQ_STAT_FAULT_IRQ_MASK) + { + if ((FCSMU_GetNtfFlag() & FCSMU_NTF_FLAG_MASK) == FCSMU_NTF_FLAG_MASK) + { + u32IrqChannel = FCSMU_GetNtfFlag() & 0xFFU; + } + else + { + u32IrqChannel = FCSMU_GetWtfFlag() & 0xFFU; + } + + if (u32IrqChannel == 0xFFU) + { + u32IrqChannel = FCSMU_GetFaultChannel(); + } + else + { + if (u32IrqChannel > 0U && u32IrqChannel <= 32U) + { + u32IrqChannel = (uint32_t)1U << (u32IrqChannel - (uint32_t)1U); + } + else + { + u32IrqChannel = 0U; + } + } + + s_apFcsmuISRCallback(FCSMU_FAULT_IRQ, u32IrqChannel); + } + else if ((FCSMU_IRQ_STAT_WARNING_IRQ_MASK & u32TempValue) == FCSMU_IRQ_STAT_WARNING_IRQ_MASK) + { + u32IrqChannel = FCSMU_GetNtwFlag() & 0xFFU; + + if (u32IrqChannel == 0xFFU) + { + u32IrqChannel = FCSMU_GetFaultChannel(); + } + else + { + if (u32IrqChannel > 0U && u32IrqChannel <= 32U) + { + u32IrqChannel = (uint32_t)1U << (u32IrqChannel - (uint32_t)1U); + } + else + { + u32IrqChannel = 0U; + } + } + + s_apFcsmuISRCallback(FCSMU_WARNING_IRQ, u32IrqChannel); + + } + else if ((FCSMU_IRQ_STAT_CFG_TO_IRQ_MASK & u32TempValue) == FCSMU_IRQ_STAT_CFG_TO_IRQ_MASK) + { + s_apFcsmuISRCallback(FCSMU_CFG_TIMEOUT, 0); + } + else + { + + } +} + +void FCSMU0_IRQHandler(void) +{ + FCSMUn_IRQHandler(); +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_fcspi.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_fcspi.c new file mode 100644 index 0000000..3bb82e8 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_fcspi.c @@ -0,0 +1,3229 @@ +/** + * @file fc7xxx_driver_fcspi.c + * @author Flagchip + * @brief FC7xxx FCSPI driver type definition and API + * @version 0.1.0 + * @date 2024-01-14 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024/01/12 Flagchip071 N/A First version for FC240 + ******************************************************************************** */ + +#include "interrupt_manager.h" +#include "fc7xxx_driver_fcspi.h" +#define FCSPI_DRV_STATUS_REG_W1C_U32 ((uint32_t)( FCSPI_STATUS_DMF(1) | \ + FCSPI_STATUS_RX_FO(1) | \ + FCSPI_STATUS_TX_FU(1) | \ + FCSPI_STATUS_TCF(1) | \ + FCSPI_STATUS_FEF(1) | \ + FCSPI_STATUS_RX_WF(1))) + +#define FCSPI_DRV_STATUS_REG_W1C_MASK_U32 ((uint32_t)(FCSPI_STATUS_DMF_MASK | \ + FCSPI_STATUS_RX_FO_MASK | \ + FCSPI_STATUS_TX_FU_MASK | \ + FCSPI_STATUS_TCF_MASK | \ + FCSPI_STATUS_FEF_MASK | \ + FCSPI_STATUS_RX_WF_MASK)) + +#define FCSPI_DRV_INT_EN_REG_ALL_U32 ((uint32_t)(FCSPI_INT_EN_DMIE(1) | \ + FCSPI_INT_EN_RFOIE(1) | \ + FCSPI_INT_EN_TFUIE(1) | \ + FCSPI_INT_EN_TCIE(1) | \ + FCSPI_INT_EN_FEIE(1) | \ + FCSPI_INT_EN_RWIE(1) | \ + FCSPI_INT_EN_RX_PEIE(1) | \ + FCSPI_INT_EN_TX_PEIE(1) | \ + FCSPI_INT_EN_RFIE(1) | \ + FCSPI_INT_EN_TFIE(1))) + +#define FCSPI_DRV_RX_FIFO_WORD_CNT (8) + +#define FCSPI_DRV_TX_FIFO_WORD_CNT (8) + +#define FCSPI_CFGR1_PCS23_PCS_MODE_U32 FCSPI_CFG1_PCS_CFG(0) /* PCS[3:2] as PCS feature */ +#define FCSPI_CFGR1_PCS23_DATABUS_IN_4BIT_MODE_U32 FCSPI_CFG1_PCS_CFG(1) /* PCS[3:2] as data bus in 4-bit mode */ + +#define FCSPI_CFGR1_OUTCFG_RETAIN_LAST_WHEN_NEGATE_U32 FCSPI_CFG1_OUT_CFG(0) +#define FCSPI_CFGR1_OUTCFG_TRISTATE_WHEN_NEGATE_U32 FCSPI_CFG1_OUT_CFG(1) + +#define FCSPI_CFGR1_PINCFG_SIN_INPUT_SOUT_OUTPUT_U32 FCSPI_CFG1_PIN_CFG(0) /* SIN is used for input data and SOUT for output data */ +#define FCSPI_CFGR1_PINCFG_SIN_INPUT_OUTPUT_U32 FCSPI_CFG1_PIN_CFG(1) /* SIN is used for both input and output data */ +#define FCSPI_CFGR1_PINCFG_SOUT_INPUT_OUTPUT_U32 FCSPI_CFG1_PIN_CFG(2) /* SOUT is used for both input and output data */ +#define FCSPI_CFGR1_PINCFG_SOUT_INPUT_SIN_OUTPUT_U32 FCSPI_CFG1_PIN_CFG(3) /* SOUT is used for input data and SIN for output data */ + +#define FCSPI_CFGR1_PCS0_ACTIVE_HIGH_U32 FCSPI_CFG1_PCS_POL(1) /* Peripheral Chip Select Polarity - Active High */ +#define FCSPI_CFGR1_PCS0_POL_MASK_U32 FCSPI_CFG1_PCS_POL(1) +#define FCSPI_CFGR1_PCS1_ACTIVE_HIGH_U32 FCSPI_CFG1_PCS_POL(2) /* Peripheral Chip Select Polarity - Active High */ +#define FCSPI_CFGR1_PCS1_POL_MASK_U32 FCSPI_CFG1_PCS_POL(2) +#define FCSPI_CFGR1_PCS2_ACTIVE_HIGH_U32 FCSPI_CFG1_PCS_POL(4) /* Peripheral Chip Select Polarity - Active High */ +#define FCSPI_CFGR1_PCS2_POL_MASK_U32 FCSPI_CFG1_PCS_POL(4) +#define FCSPI_CFGR1_PCS3_ACTIVE_HIGH_U32 FCSPI_CFG1_PCS_POL(8) /* Peripheral Chip Select Polarity - Active High */ +#define FCSPI_CFGR1_PCS3_POL_MASK_U32 FCSPI_CFG1_PCS_POL(8) + +#define FCSPI_TRCR_SCKPOL_ACTIVE_HIGH_U32 FCSPI_TR_CTRL_SCK_POL(0) /* When inactive, SCK is low */ +#define FCSPI_TRCR_SCKPOL_ACTIVE_LOW_U32 FCSPI_TR_CTRL_SCK_POL(1) /* When inactive, SCK is high */ + +#define FCSPI_TRCR_SCKPHA_CAP_LEADING_U32 FCSPI_TR_CTRL_SCK_PHA(0) /* Data is changed on the leading edge of SCK and captured on the following edge */ +#define FCSPI_TRCR_SCKPHA_CAP_TRAILING_U32 FCSPI_TR_CTRL_SCK_PHA(1) /* Data is captured on the leading edge of SCK and changed on the following edge */ + +#define FCSPI_TRCR_PRESCALE_1_U32 FCSPI_TR_CTRL_PRESCALE(0) /* Divide by 1 */ +#define FCSPI_TRCR_PRESCALE_2_U32 FCSPI_TR_CTRL_PRESCALE(1) /* Divide by 2 */ +#define FCSPI_TRCR_PRESCALE_4_U32 FCSPI_TR_CTRL_PRESCALE(2) /* Divide by 4 */ +#define FCSPI_TRCR_PRESCALE_8_U32 FCSPI_TR_CTRL_PRESCALE(3) /* Divide by 8 */ +#define FCSPI_TRCR_PRESCALE_16_U32 FCSPI_TR_CTRL_PRESCALE(4) /* Divide by 16 */ +#define FCSPI_TRCR_PRESCALE_32_U32 FCSPI_TR_CTRL_PRESCALE(5) /* Divide by 32 */ +#define FCSPI_TRCR_PRESCALE_64_U32 FCSPI_TR_CTRL_PRESCALE(6) /* Divide by 64 */ +#define FCSPI_TRCR_PRESCALE_128_U32 FCSPI_TR_CTRL_PRESCALE(7) /* Divide by 128 */ + +#define FCSPI_TRCR_PCS0_EN_U32 FCSPI_TR_CTRL_PCS(0) /* Transfer using FCSPI_PCS[0] */ +#define FCSPI_TRCR_PCS1_EN_U32 FCSPI_TR_CTRL_PCS(1) /* Transfer using FCSPI_PCS[1] */ +#define FCSPI_TRCR_PCS2_EN_U32 FCSPI_TR_CTRL_PCS(2) /* Transfer using FCSPI_PCS[2] */ +#define FCSPI_TRCR_PCS3_EN_U32 FCSPI_TR_CTRL_PCS(3) /* Transfer using FCSPI_PCS[3] */ + +#define FCSPI_TRCR_MSB_U32 FCSPI_TR_CTRL_LSBF(0) /* Data is transferred MSB first */ +#define FCSPI_TRCR_LSB_U32 FCSPI_TR_CTRL_LSBF(1) /* Data is transferred LSB first */ + +#define FCSPI_TRCR_BYSW_EN_U32 FCSPI_TR_CTRL_BYSW(1) /* Byte swap enabled */ +#define FCSPI_TRCR_BYSW_DIS_U32 FCSPI_TR_CTRL_BYSW(0) /* Byte swap disable */ + +#define FCSPI_TRCR_CONT_EN_U32 FCSPI_TR_CTRL_CT_EN(1) /* Continuous transfer enabled */ +#define FCSPI_TRCR_CONT_DIS_U32 FCSPI_TR_CTRL_CT_EN(0) /* Continuous transfer disabled */ + +#define FCSPI_TRCR_CONTC_EN_U32 FCSPI_TR_CTRL_CT_GO(1) /* Command word for continuing transfer */ + +#define FCSPI_TRCR_WIDTH_1_U32 FCSPI_TR_CTRL_WIDTH(0) /* Single bit transfer */ +#define FCSPI_TRCR_WIDTH_2_U32 FCSPI_TR_CTRL_WIDTH(1) /* Two bita transfer */ +#define FCSPI_TRCR_WIDTH_4_U32 FCSPI_TR_CTRL_WIDTH(2) /* Four bits transfer */ + +#define ITCM_START_ADDRESS 0x0u +#define ITCM_END_ADDRESS 0xFFFFu +#define DTCM_START_ADDRESS 0x20000000u +#define DTCM_END_ADDRESS 0x2001FFFFu +#define ITCM_TO_BACKDOOR_OFFSET 0x24000000u +#define DTCM_TO_BACKDOOR_OFFSET 0x02000000u + + + +typedef enum { + SIN_INPUT_SOUT_OUTPUT = 0, + SIN_INPUT_OUTPUT = 1, + SOUT_INPUT_OUTPUT = 2, + SOUT_INPUT_SIN_OUTPUT = 3 +} FCSPI_PinModeType; + +typedef enum { + FCSPI_PRESCALE_1 = 0, + FCSPI_PRESCALE_2 = 1, + FCSPI_PRESCALE_4 = 2, + FCSPI_PRESCALE_8 = 3, + FCSPI_PRESCALE_16 = 4, + FCSPI_PRESCALE_32 = 5, + FCSPI_PRESCALE_64 = 6, + FCSPI_PRESCALE_128 = 7, + FCSPI_PRESCALE_MAX = 8 +} FCSPI_PrescaleValueType; + +typedef enum { + FCSPI_TRANSFER_1_BIT = 0, /* 1-bit shift at a time, data out on SDO, in on SDI (normal mode) */ + FCSPI_TRANSFER_2_BIT = 1, /* 2-bits shift out on SDO/SDI and in on SDO/SDI */ + FCSPI_TRANSFER_4_BIT = 2 /* 4-bits shift out on SDO/SDI/PCS[3:2] and in on SDO/SDI/PCS[3:2] */ +} FCSPI_TransferWidthType; + +typedef enum { + PINOUT_RETAIN_LAST = 0, + PINOUT_TRISTATE = 1 +} FCSPI_NegatedPinOutStatType; + +typedef enum { + PCS2_3_PCS = 0, + PCS2_3_DATA_BUS_IN_4BIT_MODE = 1 +} FCSPI_PCS2_3ModeType; + +typedef struct { + FCSPI_SckPolarityType eSckPolarity; + FCSPI_SckSamplePhaseType eSckPhase; + FCSPI_PrescaleValueType ePrescalerValue; + FCSPI_PCSType ePCSSelect; + FCSPI_BitFirstOrderType eBitFirstOrder; + FCSPI_AtomicBoolType eByteSwap; + FCSPI_AtomicBoolType eContTransEnable; + FCSPI_AtomicBoolType eContCmdEnable; + FCSPI_AtomicBoolType eRxDisable; + FCSPI_AtomicBoolType eTxDisable; + FCSPI_TransferWidthType eTransferWidth; + uint16_t u16FrameBitCnt; +} FCSPI_TxRxCtrlType; + +typedef enum { + FCSPI_TRANSFER_OK = 0U, /* Transfer OK */ + FCSPI_TRANSFER_TX_FAIL, /* Error during transmission */ + FCSPI_TRANSFER_RX_FAIL, /* Error during reception */ + FCSPI_TRANSFER_ABORT, /* Transfer is aborted */ +} FCSPI_TransferStatusType; + +typedef struct { + uint16_t u16BitsPerFrame; /* count of bits per frame: 8-4096bits */ + uint16_t u16BytesCntFrameNeed; /* count of bytes per frame: 1-512bytes for external buffer passed into driver */ + FCSPI_BitFirstOrderType eBitFirstOrder; /* MSB/LSB first to send/receive */ + uint8_t u8TxFifoSize; /* Tx fifo size */ + uint8_t u8RxFifoSize; /* Rx fifo size */ + FCSPI_TriggerDmaInfType tTriggerDmaInf; + FCSPI_TriggerSrcType eTransferTriggerSrc; /* Type of transfer */ + FCSPI_StopCbType pStopNotifyCb; /* callback to transfer stop, transfer successfully or aborted */ + FCSPI_SemaphoreResetCbType pSemaResetCb; /* synchronous send need, reset the semaphore */ + FCSPI_SemaphoreTakeCbType pSemaTakeCb; /* synchronous send need, acquire the semaphore */ + FCSPI_SemaphorePostCbType pSemaPostCb; /* synchronous send need, release the semaphore outside of the interrupt */ + uint32_t u32DmaDummyData; /* DMA mode, TX is NULL, just send this data, RX is NULL, just store in this var */ + + FCSPI_SckSamplePhaseType eSckSamplePhase; /* select which edge of active sck clock to capture data */ + FCSPI_SckPolarityType eSckPolarity; /* select output sclk clock polarity */ + + FCSPI_PCSType ePcs; /* chip select pin */ + FCSPI_PcsPolarityType ePcsPolarity; /* chip select pin polarity */ + + /* only master mode use, slave not */ + FCSPI_AtomicBoolType eIsPcsContinuous; /* Option to keep chip select asserted until transfer complete; needed for TCR programming */ + uint32_t u32FCSpiSrcClk; /* Module source clock */ + uint32_t u32Baundrate; /* the bit per second of current transmission */ + + /* dynamic state */ + volatile uint8_t u8WaitSemaphore; + const uint8_t *pbyTxBuff; /* The buffer from which transmitted bytes are taken */ + uint8_t *pbyRxBuff; /* The buffer into which received bytes are placed */ + volatile uint16_t u16TxIndex; + volatile uint16_t u16RxIndex; + + volatile uint16_t u16TxByteCntRemainToSend; /* Number of bytes remaining to send */ + volatile uint16_t u16RxByteCntRemainToGet; /* Number of bytes remaining to receive */ + volatile uint16_t u16TxSendByteCntOfCurFrame; /* Number of bytes from current frame which were already sent */ + volatile uint16_t u16RxGetByteCntOfCurFrame; /* Number of bytes from current frame which were already received */ + volatile FCSPI_TransferStatusType eTransferStat; /* The status of the current */ + volatile FCSPI_AtomicBoolType eIsInTransfer; /* True if there is an active transfer */ +} FCSPI_DrvStateType; + +typedef struct +{ + FCSPI_MemMapPtr tFCSpiInstance; + FCSPI_DrvStateType tFCSpiStat; + IRQn_Type eFCSpiIrq; +} FCSPI_DriverInfoType; + +static FCSPI_DriverInfoType s_atFCSpiInfo[FCSPI_INSTANCE_COUNT] = { + {FCSPI0, {0} ,FCSPI0_IRQn}, + {FCSPI1, {0} ,FCSPI1_IRQn}, + {FCSPI2, {0} ,FCSPI2_IRQn}, + {FCSPI3, {0} ,FCSPI3_IRQn}, + {FCSPI4, {0} ,FCSPI4_IRQn}, + {FCSPI5, {0} ,FCSPI5_IRQn} + }; + + +/* soft reset just reset the logic and registers except CTRL */ +static void FCSpi_Hw_Reset(FCSPI_InstanceType eInst, + FCSPI_AtomicBoolType eRxFifo, + FCSPI_AtomicBoolType eTxFifo, + FCSPI_AtomicBoolType eSoftRst); +static FCSPI_StatusType FCSpi_Hw_Disable(FCSPI_InstanceType eInst); + +/* get status value and check using macro */ +#define FCSpi_Hw_ChkBusy(status) (((status) & FCSPI_STATUS_BF_MASK) != 0U) +#define FCSpi_Hw_ChkDataMatch(status) (((status) & FCSPI_STATUS_DMF_MASK) != 0U) +#define FCSpi_Hw_ChkRxFifoOverflow(status) (((status) & FCSPI_STATUS_RX_FO_MASK) != 0U) +#define FCSpi_Hw_ChkTxFifoUnderrun(status) (((status) & FCSPI_STATUS_TX_FU_MASK) != 0U) +#define FCSpi_Hw_ChkTransferComplete(status) (((status) & FCSPI_STATUS_TCF_MASK) != 0U) +#define FCSpi_Hw_ChkFrameEndDetected(status) (((status) & FCSPI_STATUS_FEF_MASK) != 0U) +#define FCSpi_Hw_ChkReceiveWordComplete(status) (((status) & FCSPI_STATUS_RX_WF_MASK) != 0U) +#define FCSpi_Hw_ChkRxGreaterThanWater(status) (((status) & FCSPI_STATUS_RX_FF_MASK) != 0U) +#define FCSpi_Hw_ChkTxEqualOrLessThanWater(status) (((status) & FCSPI_STATUS_TX_FF_MASK) != 0U) + +static void FCSpi_Hw_ClearSomeStatusW1CFlag(FCSPI_InstanceType eInst, uint32_t u32FlagBitSet); /* refer to FCSPI_DRV_STATUS_REG_W1C_U32 */ +static void FCSpi_Hw_EnableMoreInterrupts(FCSPI_InstanceType eInst, uint32_t u32Interrupts); /* refer to FCSPI_INT_EN_DMIE(1) */ +static void FCSpi_Hw_DisableSomeInterrupts(FCSPI_InstanceType eInst, uint32_t u32Interrupts); /* refer to FCSPI_INT_EN_DMIE(1) */ +#define FCSpi_Hw_EnableTransmitDataInterrupt(eInst) FCSpi_Hw_EnableMoreInterrupts((eInst), FCSPI_INT_EN_TFIE_MASK) +#define FCSpi_Hw_DisableTransmitDataInterrupt(eInst) FCSpi_Hw_DisableSomeInterrupts((eInst), FCSPI_INT_EN_TFIE_MASK) +#define FCSpi_Hw_EnableReceiveDataInterrupt(eInst) FCSpi_Hw_EnableMoreInterrupts((eInst), FCSPI_INT_EN_RFIE_MASK) +#define FCSpi_Hw_DisableReceiveDataInterrupt(eInst) FCSpi_Hw_DisableSomeInterrupts((eInst), FCSPI_INT_EN_RFIE_MASK) +#define FCSpi_Hw_EnableTransmitCompleteInterrupt(eInst) FCSpi_Hw_EnableMoreInterrupts((eInst), FCSPI_INT_EN_TCIE_MASK) +#define FCSpi_Hw_DisableTransmitCompleteInterrupt(eInst) FCSpi_Hw_DisableSomeInterrupts((eInst), FCSPI_INT_EN_TCIE_MASK) + +static void FCSpi_Hw_SetPcs_2_3_Mode(FCSPI_InstanceType eInst, FCSPI_PCS2_3ModeType eMode); +static void FCSpi_Hw_SetPin(FCSPI_InstanceType eInst, FCSPI_PinModeType eMode, FCSPI_NegatedPinOutStatType eStat); + +static void FCSpi_Hw_SetOnePcsPolarity(FCSPI_InstanceType eInst, + FCSPI_PCSType ePcs, FCSPI_PcsPolarityType ePolarity); + +static void FCSpi_Hw_Master_SetSckLoopbackSample(FCSPI_InstanceType eInst, FCSPI_AtomicBoolType eEnable); + +#define FCSpi_Hw_PrescalerRegToActualVal(eVal) (((uint32_t)1) << ((uint8_t)(eVal))) +static void FCSpi_Hw_SetContinuousCommand(FCSPI_InstanceType eInst, FCSPI_AtomicBoolType eEnable); + +static void FCSpi_Hw_SelectUsePcs(FCSPI_InstanceType eInst, FCSPI_PCSType ePCS); +static uint32_t FCSpi_Hw_Master_CalcBaudRate(const FCSPI_MasterCfgType *pCfg, uint32_t *pdwPrescaleRegVal, uint32_t *pdwActualSckDiv); + +static FCSPI_StatusType FCSpi_Hw_SetTRCR(FCSPI_InstanceType eInst, FCSPI_TxRxCtrlType *ptCtrl); +static FCSPI_PrescaleValueType FCSpi_Hw_GetRegPrescalerVal(FCSPI_InstanceType eInst); + +static void FCSpi_Hw_Get_SCK_PCS_DIV_Hold(FCSPI_InstanceType eInst, uint8_t *pbySCKPCS, uint8_t *pbyPCSSCK, uint8_t *pbyPCSPCS, uint8_t *pbySCKDIV); +static void FCSpi_Hw_Set_SCK_PCS_DIV_Hold(FCSPI_InstanceType eInst, uint8_t u8SCKPCS, uint8_t u8PCSSCK, uint8_t u8PCSPCS, uint8_t u8SCKDIV); +static void FCSpi_Hw_Set_SCK_PCS_Hold(FCSPI_InstanceType eInst, uint8_t u8SCKPCS, uint8_t u8PCSSCK, uint8_t u8PCSPCS); +static void FCSpi_Hw_SetRxTxDmaEnableStatus(FCSPI_InstanceType eInst, FCSPI_AtomicBoolType eRxEnable, FCSPI_AtomicBoolType eTxEnable); +static void fcspi_read_rx_fifo(FCSPI_InstanceType eInst); +static void fcspi_write_tx_fifo(FCSPI_InstanceType eInst); +static void fcspi_master_clean_transfer(FCSPI_InstanceType eInst, FCSPI_AtomicBoolType bIsInInterrupt); +static void fcspi_master_abort_transfer(FCSPI_InstanceType eInst, FCSPI_AtomicBoolType bIsInISR); +static void fcspi_master_dma_rx_err_interrupt(FCSPI_InstanceType eInst); +static void fcspi_0_master_dma_rx_err_interrupt(void); +static void fcspi_1_master_dma_rx_err_interrupt(void); +static void fcspi_2_master_dma_rx_err_interrupt(void); +static void fcspi_3_master_dma_rx_err_interrupt(void); +static void fcspi_4_master_dma_rx_err_interrupt(void); +static void fcspi_5_master_dma_rx_err_interrupt(void); +static void fcspi_master_dma_rx_finish_interrupt(void); +static void fcspi_master_dma_tx_err_interrupt(FCSPI_InstanceType eInst); +static void fcspi_0_master_dma_tx_err_interrupt(void); +static void fcspi_1_master_dma_tx_err_interrupt(void); +static void fcspi_2_master_dma_tx_err_interrupt(void); +static void fcspi_3_master_dma_tx_err_interrupt(void); +static void fcspi_4_master_dma_tx_err_interrupt(void); +static void fcspi_5_master_dma_tx_err_interrupt(void); +static void fcspi_master_dma_tx_finish_interrupt(FCSPI_InstanceType eInst); +static void fcspi_0_master_dma_tx_finish_interrupt(void); +static void fcspi_1_master_dma_tx_finish_interrupt(void); +static void fcspi_2_master_dma_tx_finish_interrupt(void); +static void fcspi_3_master_dma_tx_finish_interrupt(void); +static void fcspi_4_master_dma_tx_finish_interrupt(void); +static void fcspi_5_master_dma_tx_finish_interrupt(void); +static FCSPI_StatusType fcspi_master_async_transfer_bytes(FCSPI_InstanceType eInst, + const uint8_t *pSendBuffer, uint8_t *pReceiveBuffer, + uint16_t u16TransferByteCnt); +static FCSPI_StatusType fcspi_master_trigger(FCSPI_InstanceType eInst, FCSPI_AtomicBoolType bIsInIsr); +static void fcspi_slave_clean_transfer(FCSPI_InstanceType eInst, FCSPI_AtomicBoolType bIsInInterrupt); +static void fcspi_slave_abort_transfer(FCSPI_InstanceType eInst, FCSPI_AtomicBoolType bIsInInterrupt); +static void fcspi_slave_dma_rx_err_interrupt(FCSPI_InstanceType eInst); +static void fcspi_0_slave_dma_rx_err_interrupt(void); +static void fcspi_1_slave_dma_rx_err_interrupt(void); +static void fcspi_2_slave_dma_rx_err_interrupt(void); +static void fcspi_3_slave_dma_rx_err_interrupt(void); +static void fcspi_4_slave_dma_rx_err_interrupt(void); +static void fcspi_5_slave_dma_rx_err_interrupt(void); +static void fcspi_slave_dma_rx_finish_interrupt(FCSPI_InstanceType eInst); +static void fcspi_0_slave_dma_rx_finish_interrupt(void); +static void fcspi_1_slave_dma_rx_finish_interrupt(void); +static void fcspi_2_slave_dma_rx_finish_interrupt(void); +static void fcspi_3_slave_dma_rx_finish_interrupt(void); +static void fcspi_4_slave_dma_rx_finish_interrupt(void); +static void fcspi_5_slave_dma_rx_finish_interrupt(void); +static void fcspi_slave_dma_tx_err_interrupt(FCSPI_InstanceType eInst); +static void fcspi_0_slave_dma_tx_err_interrupt(void); +static void fcspi_1_slave_dma_tx_err_interrupt(void); +static void fcspi_2_slave_dma_tx_err_interrupt(void); +static void fcspi_3_slave_dma_tx_err_interrupt(void); +static void fcspi_4_slave_dma_tx_err_interrupt(void); +static void fcspi_5_slave_dma_tx_err_interrupt(void); +static void fcspi_slave_dma_tx_finish_interrupt(FCSPI_InstanceType eInst); +static void fcspi_0_slave_dma_tx_finish_interrupt(void); +static void fcspi_1_slave_dma_tx_finish_interrupt(void); +static void fcspi_2_slave_dma_tx_finish_interrupt(void); +static void fcspi_3_slave_dma_tx_finish_interrupt(void); +static void fcspi_4_slave_dma_tx_finish_interrupt(void); +static void fcspi_5_slave_dma_tx_finish_interrupt(void); + +static FCSPI_StatusType fcspi_slave_async_transfer_bytes(FCSPI_InstanceType eInst, + const uint8_t *pSendBuffer, uint8_t *pReceiveBuffer, uint16_t u16TransferByteCnt); +static FCSPI_StatusType fcspi_slave_trigger(FCSPI_InstanceType eInst, FCSPI_AtomicBoolType bIsInISR); +static void fcspi_irq_handler(FCSPI_InstanceType eInst); + +static void FCSpi_Hw_Reset(FCSPI_InstanceType eInst, + FCSPI_AtomicBoolType eRxFifo, FCSPI_AtomicBoolType eTxFifo, FCSPI_AtomicBoolType eSoftRst) +{ + uint32_t u32Flag = 0U; + uint32_t u32OldFlag = FCSPI_HWA_GetCtrlValue(s_atFCSpiInfo[eInst].tFCSpiInstance); + uint32_t u32Mask = FCSPI_CTRL_MASK; + + if (eRxFifo) + { + u32Flag |= FCSPI_CTRL_RST_RF(1); + } + + if (eTxFifo) + { + u32Flag |= FCSPI_CTRL_RST_TF(1); + } + + if (FCSPI_TRUE == eSoftRst) + { + u32Flag |= FCSPI_CTRL_SW_RST(1); + } + + u32Flag |= u32OldFlag; + FCSPI_HWA_SetCtrlValue(s_atFCSpiInfo[eInst].tFCSpiInstance, u32Flag); + + /* no need delay */ + if (FCSPI_TRUE == eSoftRst) + { + FCSPI_HWA_SetCtrlValue(s_atFCSpiInfo[eInst].tFCSpiInstance, 0U); + } + else + { + FCSPI_HWA_SetCtrlValue(s_atFCSpiInfo[eInst].tFCSpiInstance, (u32OldFlag & u32Mask)); + } +} + +#ifdef FCSPI_DRV_INTERNAL_FUNC_EN +static FCSPI_AtomicBoolType FCSpi_Hw_ChkEnabled(FCSPI_InstanceType eInst) +{ + return (FCSPI_AtomicBoolType)((FCSPI_HWA_GetCtrlValue(s_atFCSpiInfo[eInst].tFCSpiInstance) & + FCSPI_CTRL_M_EN_MASK) >> FCSPI_CTRL_M_EN_SHIFT); +} +#endif + +static FCSPI_StatusType FCSpi_Hw_Disable(FCSPI_InstanceType eInst) +{ + FCSPI_StatusType eStatus = FCSPI_STATUS_SUCCESS; + + if (0U != (FCSPI_HWA_GetStatus(s_atFCSpiInfo[eInst].tFCSpiInstance) & FCSPI_STATUS_BF_MASK)) + { + eStatus = FCSPI_STATUS_BUSY; + } + else + { + FCSPI_HWA_ModuleDisable(s_atFCSpiInfo[eInst].tFCSpiInstance); + } + + return eStatus; +} + +static void FCSpi_Hw_ClearSomeStatusW1CFlag( + FCSPI_InstanceType eInst, uint32_t u32FlagBitSet) /* refer to FCSPI_DRV_STATUS_REG_W1C_U32 */ +{ + FCSPI_HWA_ClearStatus(s_atFCSpiInfo[eInst].tFCSpiInstance, (u32FlagBitSet & FCSPI_DRV_STATUS_REG_W1C_MASK_U32)); +} + +#ifdef FCSPI_DRV_INTERNAL_FUNC_EN +static void FCSpi_Hw_SetAllInterruptEnableStatus( + FCSPI_InstanceType eInst, uint32_t u32Interrupts) /* refer to FCSPI_DRV_INT_EN_REG_ALL_U32 */ +{ + FCSPI_HWA_SetInterruptEnableReg(s_atFCSpiInfo[eInst].tFCSpiInstance, (u32Interrupts & FCSPI_INT_EN_MASK)); +} + +static uint32_t FCSpi_Hw_GetAllInterruptEnableStatus(FCSPI_InstanceType eInst) +{ + return FCSPI_HWA_GetIntrruptEnableReg(s_atFCSpiInfo[eInst].tFCSpiInstance); +} +#endif + +static void FCSpi_Hw_EnableMoreInterrupts(FCSPI_InstanceType eInst, uint32_t u32Interrupts) +{ + uint32_t u32RegVal = FCSPI_HWA_GetIntrruptEnableReg(s_atFCSpiInfo[eInst].tFCSpiInstance); + u32RegVal |= (u32Interrupts & FCSPI_INT_EN_MASK); + + FCSPI_HWA_SetInterruptEnableReg(s_atFCSpiInfo[eInst].tFCSpiInstance, u32RegVal); +} + +static void FCSpi_Hw_DisableSomeInterrupts(FCSPI_InstanceType eInst, uint32_t u32Interrupts) +{ + uint32_t u32RegVal = FCSPI_HWA_GetIntrruptEnableReg(s_atFCSpiInfo[eInst].tFCSpiInstance); + u32RegVal &= (~(u32Interrupts & FCSPI_INT_EN_MASK)); + + FCSPI_HWA_SetInterruptEnableReg(s_atFCSpiInfo[eInst].tFCSpiInstance, u32RegVal); +} + +static void FCSpi_Hw_SetRxTxDmaEnableStatus( + FCSPI_InstanceType eInst, FCSPI_AtomicBoolType eRxEnable, FCSPI_AtomicBoolType eTxEnable) +{ + uint32_t u32Flag = 0U; + + if (eRxEnable) + { + u32Flag |= FCSPI_DMA_EN_RFDE(1); + } + + if (eTxEnable) + { + u32Flag |= FCSPI_DMA_EN_TFDE(1); + } + + FCSPI_HWA_SetDMAEnableReg(s_atFCSpiInfo[eInst].tFCSpiInstance, u32Flag); +} + +#ifdef FCSPI_DRV_INTERNAL_FUNC_EN +static void FCSpi_Hw_SetRxDmaEnableStatus(FCSPI_InstanceType eInst, FCSPI_AtomicBoolType eEnable) +{ + uint32_t u32RegVal = FCSPI_HWA_GetDMAEnableReg(s_atFCSpiInfo[eInst].tFCSpiInstance); + + if (eEnable) + { + u32RegVal |= FCSPI_DMA_EN_RFDE(1); + } + else + { + u32RegVal &= (~(FCSPI_DMA_EN_RFDE_MASK)); + } + + FCSPI_HWA_SetDMAEnableReg(s_atFCSpiInfo[eInst].tFCSpiInstance, u32RegVal); +} + +static void FCSpi_Hw_SetTxDmaEnableStatus(FCSPI_InstanceType eInst, FCSPI_AtomicBoolType eEnable) +{ + uint32_t u32RegVal = FCSPI_HWA_GetDMAEnableReg(s_atFCSpiInfo[eInst].tFCSpiInstance); + + if (FCSPI_TRUE == eEnable) + { + u32RegVal |= FCSPI_DMA_EN_TFDE(1); + } + else + { + u32RegVal &= (~(FCSPI_DMA_EN_TFDE_MASK)); + } + + FCSPI_HWA_SetDMAEnableReg(s_atFCSpiInfo[eInst].tFCSpiInstance, u32RegVal); +} +#endif + +static void FCSpi_Hw_SetPcs_2_3_Mode(FCSPI_InstanceType eInst, FCSPI_PCS2_3ModeType eMode) +{ + uint32_t u32RegVal = FCSPI_HWA_GetCFG1Reg(s_atFCSpiInfo[eInst].tFCSpiInstance); + + if (PCS2_3_PCS == eMode) + { + u32RegVal &= (~(FCSPI_CFG1_PCS_CFG_MASK)); + } + else + { + u32RegVal |= (FCSPI_CFGR1_PCS23_DATABUS_IN_4BIT_MODE_U32); + } + + FCSPI_HWA_SetCFG1Reg(s_atFCSpiInfo[eInst].tFCSpiInstance, u32RegVal); +} + +static void FCSpi_Hw_SetPin(FCSPI_InstanceType eInst, + FCSPI_PinModeType eMode, FCSPI_NegatedPinOutStatType eStat) +{ + uint32_t u32Flag = FCSPI_HWA_GetCFG1Reg(s_atFCSpiInfo[eInst].tFCSpiInstance); + + u32Flag &= (~(FCSPI_CFG1_PIN_CFG_MASK)); + u32Flag &= (~(FCSPI_CFG1_OUT_CFG_MASK)); + + switch (eMode) + { + case SIN_INPUT_OUTPUT: + u32Flag |= FCSPI_CFGR1_PINCFG_SIN_INPUT_OUTPUT_U32; + break; + case SOUT_INPUT_OUTPUT: + u32Flag |= FCSPI_CFGR1_PINCFG_SOUT_INPUT_OUTPUT_U32; + break; + case SOUT_INPUT_SIN_OUTPUT: + u32Flag |= FCSPI_CFGR1_PINCFG_SOUT_INPUT_SIN_OUTPUT_U32; + break; + case SIN_INPUT_SOUT_OUTPUT: + u32Flag |= FCSPI_CFGR1_PINCFG_SIN_INPUT_SOUT_OUTPUT_U32; + break; + default: + u32Flag |= FCSPI_CFGR1_PINCFG_SIN_INPUT_SOUT_OUTPUT_U32; + break; + } + + if (PINOUT_RETAIN_LAST == eStat) + { + u32Flag |= FCSPI_CFGR1_OUTCFG_RETAIN_LAST_WHEN_NEGATE_U32; + } + else + { + u32Flag |= FCSPI_CFGR1_OUTCFG_TRISTATE_WHEN_NEGATE_U32; + } + + FCSPI_HWA_SetCFG1Reg(s_atFCSpiInfo[eInst].tFCSpiInstance, u32Flag); +} + +#ifdef FCSPI_DRV_INTERNAL_FUNC_EN +static void FCSpi_Hw_SetPcsPolarity(FCSPI_InstanceType eInst, + FCSPI_AtomicBoolType eSetPCS0, FCSPI_PcsPolarityType ePCS0Polarity, + FCSPI_AtomicBoolType eSetPCS1, FCSPI_PcsPolarityType ePCS1Polarity, + FCSPI_AtomicBoolType eSetPCS2, FCSPI_PcsPolarityType ePCS2Polarity, + FCSPI_AtomicBoolType eSetPCS3, FCSPI_PcsPolarityType ePCS3Polarity) +{ + uint32_t u32Flag = FCSPI_HWA_GetCFG1Reg(s_atFCSpiInfo[eInst].tFCSpiInstance); + + if (eSetPCS0) + { + if (FCSPI_PCS_POL_ACTIVE_HIGH == ePCS0Polarity) + u32Flag |= FCSPI_CFGR1_PCS0_ACTIVE_HIGH_U32; + else + u32Flag &= (~(FCSPI_CFGR1_PCS0_POL_MASK_U32)); + } + + if (eSetPCS1) + { + if (FCSPI_PCS_POL_ACTIVE_HIGH == ePCS1Polarity) + u32Flag |= FCSPI_CFGR1_PCS1_ACTIVE_HIGH_U32; + else + u32Flag &= (~(FCSPI_CFGR1_PCS1_POL_MASK_U32)); + } + + if (eSetPCS2) + { + if (FCSPI_PCS_POL_ACTIVE_HIGH == ePCS2Polarity) + u32Flag |= FCSPI_CFGR1_PCS2_ACTIVE_HIGH_U32; + else + u32Flag &= (~(FCSPI_CFGR1_PCS2_POL_MASK_U32)); + } + + if (eSetPCS3) + { + if (FCSPI_PCS_POL_ACTIVE_HIGH == ePCS3Polarity) + u32Flag |= FCSPI_CFGR1_PCS3_ACTIVE_HIGH_U32; + else + u32Flag &= (~(FCSPI_CFGR1_PCS3_POL_MASK_U32)); + } + + FCSPI_HWA_SetCFG1Reg(s_atFCSpiInfo[eInst].tFCSpiInstance, u32Flag); +} +#endif + +static void FCSpi_Hw_SetOnePcsPolarity(FCSPI_InstanceType eInst, + FCSPI_PCSType ePcs, FCSPI_PcsPolarityType ePolarity) +{ + uint32_t u32Flag = FCSPI_HWA_GetCFG1Reg(s_atFCSpiInfo[eInst].tFCSpiInstance); + + if (FCSPI_PCS_POL_ACTIVE_HIGH == ePolarity) + { + if (0U == ((((uint32_t)0x1) << (FCSPI_CFG1_PCS_POL_SHIFT + (uint32_t)ePcs)) & u32Flag)) + { + u32Flag |= (((uint32_t)0x1) << (FCSPI_CFG1_PCS_POL_SHIFT + (uint32_t)ePcs)); + } + } + else /* active low */ + { + if (0U != ((((uint32_t)0x1) << (FCSPI_CFG1_PCS_POL_SHIFT + (uint32_t)ePcs)) & u32Flag)) + { + u32Flag &= (~(((uint32_t)0x1) << (FCSPI_CFG1_PCS_POL_SHIFT + (uint32_t)ePcs))); + } + } + + FCSPI_HWA_SetCFG1Reg(s_atFCSpiInfo[eInst].tFCSpiInstance, u32Flag); +} + +/* before call this function, ensure in master mode */ +static void FCSpi_Hw_Master_SetSckLoopbackSample( + FCSPI_InstanceType eInst, FCSPI_AtomicBoolType eEnable) +{ + uint32_t u32Flag = FCSPI_HWA_GetCFG1Reg(s_atFCSpiInfo[eInst].tFCSpiInstance); + + if (FCSPI_TRUE == eEnable) + { + if (FCSPI_CFG1_SCK_LB(1) != (u32Flag & FCSPI_CFG1_SCK_LB_MASK)) + { + u32Flag |= FCSPI_CFG1_SCK_LB(1); + } + } + else + { + if (FCSPI_CFG1_SCK_LB(0) != (u32Flag & FCSPI_CFG1_SCK_LB_MASK)) + { + u32Flag &= (~(FCSPI_CFG1_SCK_LB_MASK)); + } + } + + FCSPI_HWA_SetCFG1Reg(s_atFCSpiInfo[eInst].tFCSpiInstance, u32Flag); +} + +static void FCSpi_Hw_Set_SCK_PCS_DIV_Hold(FCSPI_InstanceType eInst, + uint8_t u8SCKPCS, uint8_t u8PCSSCK, uint8_t u8PCSPCS, uint8_t u8SCKDIV) +{ + uint32_t u32Flag = FCSPI_HWA_GetClockConfig(s_atFCSpiInfo[eInst].tFCSpiInstance); + uint32_t u32Val; + + { + u32Val = u8SCKPCS; + u32Flag &= (~(FCSPI_CLK_CFG_SCKPCS_MASK)); + u32Flag |= (u32Val << FCSPI_CLK_CFG_SCKPCS_SHIFT); + } + + { + u32Val = u8PCSSCK; + u32Flag &= (~(FCSPI_CLK_CFG_PCSSCK_MASK)); + u32Flag |= (u32Val << FCSPI_CLK_CFG_PCSSCK_SHIFT); + } + + { + u32Val = u8PCSPCS; + u32Flag &= (~(FCSPI_CLK_CFG_PCSPCS_MASK)); + u32Flag |= (u32Val << FCSPI_CLK_CFG_PCSPCS_SHIFT); + } + + { + u32Val = u8SCKDIV; + u32Flag &= (~(FCSPI_CLK_CFG_SCKDIV_MASK)); + u32Flag |= (u32Val << FCSPI_CLK_CFG_SCKDIV_SHIFT); + } + + { + FCSPI_HWA_SetClockConfig(s_atFCSpiInfo[eInst].tFCSpiInstance, u32Flag); + } +} + +static void FCSpi_Hw_Set_SCK_PCS_Hold(FCSPI_InstanceType eInst, + uint8_t u8SCKPCS, uint8_t u8PCSSCK, uint8_t u8PCSPCS) +{ + uint32_t u32Flag = FCSPI_HWA_GetClockConfig(s_atFCSpiInfo[eInst].tFCSpiInstance); + uint32_t u32Val; + + { + u32Val = u8SCKPCS; + u32Flag &= (~(FCSPI_CLK_CFG_SCKPCS_MASK)); + u32Flag |= (u32Val << FCSPI_CLK_CFG_SCKPCS_SHIFT); + } + + { + u32Val = u8PCSSCK; + u32Flag &= (~(FCSPI_CLK_CFG_PCSSCK_MASK)); + u32Flag |= (u32Val << FCSPI_CLK_CFG_PCSSCK_SHIFT); + } + + { + u32Val = u8PCSPCS; + u32Flag &= (~(FCSPI_CLK_CFG_PCSPCS_MASK)); + u32Flag |= (u32Val << FCSPI_CLK_CFG_PCSPCS_SHIFT); + } + + { + FCSPI_HWA_SetClockConfig(s_atFCSpiInfo[eInst].tFCSpiInstance, u32Flag); + } +} + +static void FCSpi_Hw_Get_SCK_PCS_DIV_Hold(FCSPI_InstanceType eInst, + uint8_t *pbySCKPCS, + uint8_t *pbyPCSSCK, + uint8_t *pbyPCSPCS, + uint8_t *pbySCKDIV) +{ + uint32_t u32Flag = FCSPI_HWA_GetClockConfig(s_atFCSpiInfo[eInst].tFCSpiInstance); + + if (pbySCKPCS != NULL) + { + *pbySCKPCS = (uint8_t)((u32Flag & FCSPI_CLK_CFG_SCKPCS_MASK) >> FCSPI_CLK_CFG_SCKPCS_SHIFT); + } + + if (pbyPCSSCK != NULL) + { + *pbyPCSSCK = (uint8_t)((u32Flag & FCSPI_CLK_CFG_PCSSCK_MASK) >> FCSPI_CLK_CFG_PCSSCK_SHIFT); + } + + if (pbyPCSPCS != NULL) + { + *pbyPCSPCS = (uint8_t)((u32Flag & FCSPI_CLK_CFG_PCSPCS_MASK) >> FCSPI_CLK_CFG_PCSPCS_SHIFT); + } + + if (pbySCKDIV != NULL) + { + *pbySCKDIV = ((uint8_t)(u32Flag & FCSPI_CLK_CFG_SCKDIV_MASK) >> FCSPI_CLK_CFG_SCKDIV_SHIFT); + } +} + +#ifdef FCSPI_DRV_INTERNAL_FUNC_EN +static void FCSpi_Hw_GetTRCR(FCSPI_InstanceType eInst, FCSPI_TxRxCtrlType *ptCtrl) +{ + uint32_t u32Flag = FCSPI_HWA_GetTxRxControl(s_atFCSpiInfo[eInst].tFCSpiInstance); + + ptCtrl->eSckPolarity = (FCSPI_SckPolarityType) + ((u32Flag & FCSPI_TR_CTRL_SCK_POL_MASK) >> FCSPI_TR_CTRL_SCK_POL_SHIFT); + ptCtrl->eSckPhase = (FCSPI_SckSamplePhaseType) + ((u32Flag & FCSPI_TR_CTRL_SCK_PHA_MASK) >> FCSPI_TR_CTRL_SCK_PHA_SHIFT); + ptCtrl->ePrescalerValue = (FCSPI_PrescaleValueType) + ((u32Flag & FCSPI_TR_CTRL_PRESCALE_MASK) >> FCSPI_TR_CTRL_PRESCALE_SHIFT); + ptCtrl->ePCSSelect = (FCSPI_PCSType) + ((u32Flag & FCSPI_TR_CTRL_PCS_MASK) >> FCSPI_TR_CTRL_PCS_SHIFT); + ptCtrl->eBitFirstOrder = (FCSPI_BitFirstOrderType) + ((u32Flag & FCSPI_TR_CTRL_LSBF_MASK) >> FCSPI_TR_CTRL_LSBF_SHIFT); + ptCtrl->eByteSwap = (FCSPI_AtomicBoolType) + ((u32Flag & FCSPI_TR_CTRL_BYSW_MASK) >> FCSPI_TR_CTRL_BYSW_SHIFT); + ptCtrl->eContTransEnable = (FCSPI_AtomicBoolType) + ((u32Flag & FCSPI_TR_CTRL_CT_EN_MASK) >> FCSPI_TR_CTRL_CT_EN_SHIFT); + + ptCtrl->eContCmdEnable = (FCSPI_AtomicBoolType) + ((u32Flag & FCSPI_TR_CTRL_CT_GO_MASK) >> FCSPI_TR_CTRL_CT_GO_SHIFT); + ptCtrl->eRxDisable = (FCSPI_AtomicBoolType) + ((u32Flag & FCSPI_TR_CTRL_RX_MSK_MASK) >> FCSPI_TR_CTRL_RX_MSK_SHIFT); + ptCtrl->eTxDisable = (FCSPI_AtomicBoolType) + ((u32Flag & FCSPI_TR_CTRL_TX_MSK_MASK) >> FCSPI_TR_CTRL_TX_MSK_SHIFT); + ptCtrl->eTransferWidth = (FCSPI_TransferWidthType) + ((u32Flag & FCSPI_TR_CTRL_WIDTH_MASK) >> FCSPI_TR_CTRL_WIDTH_SHIFT); + ptCtrl->u16FrameBitCnt = (uint16_t) + (((u32Flag & FCSPI_TR_CTRL_FRM_SZ_MASK) >> FCSPI_TR_CTRL_FRM_SZ_SHIFT)+1); +} +#endif + +static FCSPI_StatusType FCSpi_Hw_SetTRCR(FCSPI_InstanceType eInst, FCSPI_TxRxCtrlType *ptCtrl) +{ + uint32_t u32Flag = 0U; + FCSPI_StatusType eRet = FCSPI_STATUS_SUCCESS; + + if ((ptCtrl->u16FrameBitCnt < ((uint16_t)8)) || + (((uint16_t)0) != (ptCtrl->u16FrameBitCnt & ((uint16_t)0x1)))) + { + eRet = FCSPI_STATUS_PARAM_ERR; + } + else + { + u32Flag |= (((uint32_t)(ptCtrl->eSckPolarity)) << FCSPI_TR_CTRL_SCK_POL_SHIFT); + u32Flag |= (((uint32_t)(ptCtrl->eSckPhase)) << FCSPI_TR_CTRL_SCK_PHA_SHIFT); + u32Flag |= (((uint32_t)(ptCtrl->ePrescalerValue)) << FCSPI_TR_CTRL_PRESCALE_SHIFT); + u32Flag |= (((uint32_t)(ptCtrl->ePCSSelect)) << FCSPI_TR_CTRL_PCS_SHIFT); + u32Flag |= (((uint32_t)(ptCtrl->eBitFirstOrder)) << FCSPI_TR_CTRL_LSBF_SHIFT); + u32Flag |= (((uint32_t)(ptCtrl->eByteSwap)) << FCSPI_TR_CTRL_BYSW_SHIFT); + u32Flag |= (((uint32_t)(ptCtrl->eContTransEnable)) << FCSPI_TR_CTRL_CT_EN_SHIFT); + u32Flag |= (((uint32_t)(ptCtrl->eContCmdEnable)) << FCSPI_TR_CTRL_CT_GO_SHIFT); + u32Flag |= (((uint32_t)(ptCtrl->eRxDisable)) << FCSPI_TR_CTRL_RX_MSK_SHIFT); + u32Flag |= (((uint32_t)(ptCtrl->eTxDisable)) << FCSPI_TR_CTRL_TX_MSK_SHIFT); + u32Flag |= (((uint32_t)(ptCtrl->eTransferWidth)) << FCSPI_TR_CTRL_WIDTH_SHIFT); + u32Flag |= (((uint32_t)((uint16_t)(ptCtrl->u16FrameBitCnt - (uint16_t)1))) << FCSPI_TR_CTRL_FRM_SZ_SHIFT); + + FCSPI_HWA_SetTxRxControl(s_atFCSpiInfo[eInst].tFCSpiInstance, u32Flag); + } + + return eRet; +} + +/* caution:write TR_CTRL */ +static void FCSpi_Hw_SelectUsePcs(FCSPI_InstanceType eInst, FCSPI_PCSType ePCS) +{ + uint32_t u32Flag = FCSPI_HWA_GetTxRxControl(s_atFCSpiInfo[eInst].tFCSpiInstance); + + u32Flag &= (~(FCSPI_TR_CTRL_PCS_MASK)); + u32Flag |= (((uint32_t)ePCS) << FCSPI_TR_CTRL_PCS_SHIFT); + + FCSPI_HWA_SetTxRxControl(s_atFCSpiInfo[eInst].tFCSpiInstance, u32Flag); +} + +static FCSPI_PrescaleValueType FCSpi_Hw_GetRegPrescalerVal(FCSPI_InstanceType eInst) +{ + return (FCSPI_PrescaleValueType)((FCSPI_HWA_GetTxRxControl(s_atFCSpiInfo[eInst].tFCSpiInstance) & + FCSPI_TR_CTRL_PRESCALE_MASK) >> FCSPI_TR_CTRL_PRESCALE_SHIFT); +} + +/* caution:write TR_CTRL */ +static void FCSpi_Hw_SetContinuousCommand(FCSPI_InstanceType eInst, FCSPI_AtomicBoolType eEnable) +{ + uint32_t u32Flag = FCSPI_HWA_GetTxRxControl(s_atFCSpiInfo[eInst].tFCSpiInstance); + + u32Flag &= (~(FCSPI_TR_CTRL_CT_GO_MASK)); + u32Flag |= (((uint32_t)eEnable) << FCSPI_TR_CTRL_CT_GO_SHIFT); + + FCSPI_HWA_SetTxRxControl(s_atFCSpiInfo[eInst].tFCSpiInstance, u32Flag); +} + +#ifdef FCSPI_DRV_INTERNAL_FUNC_EN +static uint32_t FCSpi_Hw_ReadRxFifoFirstEntry(FCSPI_InstanceType eInst) +{ + return FCSPI_HWA_ReadData(s_atFCSpiInfo[eInst].tFCSpiInstance); +} +#endif + +#ifdef FCSPI_DRV_INTERNAL_FUNC_EN +static void FCSpi_Hw_WriteDataToTxFifo(FCSPI_InstanceType eInst, uint32_t u32TxData) +{ + FCSPI_HWA_WriteData(s_atFCSpiInfo[eInst].tFCSpiInstance, u32TxData); +} +#endif + +/* + * Before call this function, ensure the FCSPI is disabled and in MASTER mode. + * Src Clk -> Prescaler -> sck divider -> SCLK + */ +#define FCSPI_CAL_DISTANCE(x, y) ((x) > (y) ? ((x) - (y)) : ((y) - (x))) +typedef struct { + uint32_t u32CacheTargetBps; + uint32_t u32CacheSrcClkHz; + uint32_t u32CachePrescaleRegVal; + uint32_t u32CacheBps; + uint32_t u32CacheSckDiv; +} FCSPI_BaundrateCacheType; +#define FCSPI_PCS_CLK_CACHE_CNT ((uint8_t)2) + +/* Often use case, just set the same baundrate for specific external device linked with one FCSPI PCS */ +static uint32_t FCSpi_Hw_Master_CalcBaudRate(const FCSPI_MasterCfgType *pCfg, + uint32_t *pdwPrescaleRegVal, uint32_t *pdwActualSckDiv) +{ + uint32_t u32TargetBps = pCfg->u32BitCntPerSecond; + uint32_t u32SrcClkHz = pCfg->u32FCSpiSrcClk; + uint32_t u32TestFreq = 0U; + int16_t s16TestSckDivRegVal = (int16_t)0; + uint8_t u8PrescalerRegVal = (uint8_t)0; + int16_t s16SckDivLow, s16SckDivHigh; + uint32_t u32Prescale = 0U; + uint32_t u32ActualBps = 0U; + uint32_t u32ActualSckDiv = 0U; + uint32_t u32ActualPrescaleRegVal = 0U; + uint32_t u32ThisPrescaleBestBps = 0U; + uint32_t u32ThisPrescaleBestSckDiv = 0U; + uint32_t u32AbsDistance1, u32AbsDistance2; + uint8_t u8Find = (uint8_t)0; + uint32_t u32Ret = 0U; + + if (u32SrcClkHz < (u32TargetBps * 2U)) + { + u32Ret = 0U; + } + else + { + if ((uint8_t)0 == u8Find) + { + u32ActualSckDiv = 0U; + u32ActualPrescaleRegVal = 0U; + u32ActualBps = (uint32_t)(u32SrcClkHz / ((uint32_t)((((uint32_t)1) << + u32ActualPrescaleRegVal) * (u32ActualSckDiv + (uint32_t)2U)))); + + for (u8PrescalerRegVal = (uint8_t)0; u8PrescalerRegVal < FCSPI_PRESCALE_MAX; ++u8PrescalerRegVal) + { + s16SckDivLow = (int16_t)0; + + if ((FCSPI_SCK_SAMPLE_SECOND_EDGE == pCfg->eSckSamplePhase) && /* sample the 2nd edge */ + (FCSPI_FALSE != pCfg->eIsPcsContinuous)) /* continuous pcs */ + { + /* hw bug fix, sck must be 0 */ + s16SckDivHigh = (int16_t)0; + } + else + { + s16SckDivHigh = (int16_t)255; + } + + u32Prescale = ((uint32_t)1) << u8PrescalerRegVal; + u32ThisPrescaleBestSckDiv = 0U; + u32ThisPrescaleBestBps = (uint32_t)(u32SrcClkHz / ((uint32_t)(u32Prescale * + (u32ThisPrescaleBestSckDiv + (uint32_t)2U)))); + + while(s16SckDivHigh > s16SckDivLow) + { + s16TestSckDivRegVal = s16SckDivLow + s16SckDivHigh; + s16TestSckDivRegVal = (s16TestSckDivRegVal / (int16_t)2); + u32TestFreq = (uint32_t)(u32SrcClkHz / + ((uint32_t)(u32Prescale * ((uint32_t)s16TestSckDivRegVal + (uint32_t)2U)))); + + u32AbsDistance1 = FCSPI_CAL_DISTANCE(u32TargetBps, u32ThisPrescaleBestBps); + u32AbsDistance2 = FCSPI_CAL_DISTANCE(u32TargetBps, u32TestFreq); + if (u32AbsDistance1 > u32AbsDistance2) + { + u32ThisPrescaleBestBps = u32TestFreq; + u32ThisPrescaleBestSckDiv = (uint32_t)s16TestSckDivRegVal; + } + + if (u32TestFreq == u32TargetBps) + { + break; + } + else if (u32TestFreq < u32TargetBps) + { + s16SckDivHigh = s16TestSckDivRegVal - 1; + } + else + { + s16SckDivLow = s16TestSckDivRegVal + 1; + } + } + + u32AbsDistance1 = FCSPI_CAL_DISTANCE(u32TargetBps, u32ActualBps); + u32AbsDistance2 = FCSPI_CAL_DISTANCE(u32TargetBps, u32ThisPrescaleBestBps); + if (u32AbsDistance1 > u32AbsDistance2) + { + u32ActualBps = u32ThisPrescaleBestBps; + u32ActualSckDiv = u32ThisPrescaleBestSckDiv; + u32ActualPrescaleRegVal = u8PrescalerRegVal; + } + + if(u32ThisPrescaleBestBps == u32TargetBps) + { + break; + } + } + + if (0U != u32ActualBps) + { + if (NULL != pdwActualSckDiv) + { + *pdwActualSckDiv = u32ActualSckDiv; + } + + if (NULL != pdwPrescaleRegVal) + { + *pdwPrescaleRegVal = u32ActualPrescaleRegVal; + } + } + + /* return the actual calculated baud rate */ + u32Ret = u32ActualBps; + } + } + + return u32Ret; +} + +/* Master/Slave side all use */ + +static void fcspi_read_rx_fifo(FCSPI_InstanceType eInst) +{ + uint32_t u32RxWordData = 0U; + uint16_t u16ByteCount = (uint16_t)0; + uint8_t u8ByteIndex = (uint8_t)0; + uint8_t u8WordCntInRxFifo = FCSPI_HWA_GetRxFifoStoredCount(s_atFCSpiInfo[eInst].tFCSpiInstance); + + while (u8WordCntInRxFifo > (uint8_t)0) + { + u32RxWordData = FCSPI_HWA_ReadData(s_atFCSpiInfo[eInst].tFCSpiInstance); + /* Get the number of bytes which can be read from this 32 bites */ + if (s_atFCSpiInfo[eInst].tFCSpiStat.u16BytesCntFrameNeed <= + (s_atFCSpiInfo[eInst].tFCSpiStat.u16RxGetByteCntOfCurFrame + (uint16_t)4)) + { + u16ByteCount = (uint16_t)(s_atFCSpiInfo[eInst].tFCSpiStat.u16BytesCntFrameNeed - + s_atFCSpiInfo[eInst].tFCSpiStat.u16RxGetByteCntOfCurFrame); + } + else + { + u16ByteCount = (uint16_t)4; + } + + /* Generate the word which will be write in buffer. */ + for (u8ByteIndex = (uint8_t)0; u8ByteIndex < u16ByteCount; ++u8ByteIndex) + { + (s_atFCSpiInfo[eInst].tFCSpiStat.pbyRxBuff)[s_atFCSpiInfo[eInst].tFCSpiStat.u16RxIndex] = + (uint8_t)((u32RxWordData >> (uint32_t)((uint32_t)u8ByteIndex * (uint32_t)8)) & (uint8_t)0xFF); + (s_atFCSpiInfo[eInst].tFCSpiStat.u16RxIndex)++; + } + + s_atFCSpiInfo[eInst].tFCSpiStat.u16RxGetByteCntOfCurFrame = + (uint16_t)((s_atFCSpiInfo[eInst].tFCSpiStat.u16RxGetByteCntOfCurFrame + + u16ByteCount) % s_atFCSpiInfo[eInst].tFCSpiStat.u16BytesCntFrameNeed); + + /* Update internal variable used in transmission. */ + s_atFCSpiInfo[eInst].tFCSpiStat.u16RxByteCntRemainToGet = + (uint16_t)(s_atFCSpiInfo[eInst].tFCSpiStat.u16RxByteCntRemainToGet - u16ByteCount); + /* Verify if all bytes were sent. */ + if ((uint16_t)0 == s_atFCSpiInfo[eInst].tFCSpiStat.u16RxByteCntRemainToGet) + { + break; + } + + u8WordCntInRxFifo--; + } +} + +static void fcspi_write_tx_fifo(FCSPI_InstanceType eInst) +{ + uint32_t u32DataToSend = 0U; + uint16_t u16ThisSendByteCnt = (uint16_t)0; + uint8_t u8TxFifoFreeWordCnt = (uint8_t)(s_atFCSpiInfo[eInst].tFCSpiStat.u8TxFifoSize - + (uint8_t)FCSPI_HWA_GetTxFifoStoredCount(s_atFCSpiInfo[eInst].tFCSpiInstance)); + uint16_t u16BytesTxLeft = s_atFCSpiInfo[eInst].tFCSpiStat.u16TxByteCntRemainToSend; + + while ((u8TxFifoFreeWordCnt != (uint8_t)0) && ((uint16_t)0 != u16BytesTxLeft)) + { + if (FCSPI_TRUE == s_atFCSpiInfo[eInst].tFCSpiStat.eIsPcsContinuous) + { + if((uint16_t)1 == s_atFCSpiInfo[eInst].tFCSpiStat.u16TxByteCntRemainToSend) + { + /* Disable continuous PCS */ + FCSpi_Hw_SetContinuousCommand(eInst, FCSPI_FALSE); + s_atFCSpiInfo[eInst].tFCSpiStat.u16TxByteCntRemainToSend = (uint16_t)0; + u16BytesTxLeft = (uint16_t)0; + break; + } + } + + /* Get the number of bytes which can be written in a single 32 bits word. */ + if ((s_atFCSpiInfo[eInst].tFCSpiStat.u16BytesCntFrameNeed - + s_atFCSpiInfo[eInst].tFCSpiStat.u16TxSendByteCntOfCurFrame) <= (uint16_t)4) + { + u16ThisSendByteCnt = (uint16_t)(s_atFCSpiInfo[eInst].tFCSpiStat.u16BytesCntFrameNeed - + s_atFCSpiInfo[eInst].tFCSpiStat.u16TxSendByteCntOfCurFrame); + } + else + { + u16ThisSendByteCnt = (uint16_t)4; + } + + u32DataToSend = 0U; + + if (NULL != s_atFCSpiInfo[eInst].tFCSpiStat.pbyTxBuff) + { + switch(s_atFCSpiInfo[eInst].tFCSpiStat.u16BytesCntFrameNeed) + { + case 1: + u32DataToSend = *((const uint8_t *)&(s_atFCSpiInfo[eInst].tFCSpiStat.pbyTxBuff[s_atFCSpiInfo[eInst].tFCSpiStat.u16TxIndex])); + s_atFCSpiInfo[eInst].tFCSpiStat.u16TxIndex += sizeof(uint8_t); + break; + + case 2: + u32DataToSend = *((const uint16_t *)&(s_atFCSpiInfo[eInst].tFCSpiStat.pbyTxBuff[s_atFCSpiInfo[eInst].tFCSpiStat.u16TxIndex])); + s_atFCSpiInfo[eInst].tFCSpiStat.u16TxIndex += sizeof(uint16_t); + break; + + default: + u32DataToSend = *((const uint32_t *)&(s_atFCSpiInfo[eInst].tFCSpiStat.pbyTxBuff[s_atFCSpiInfo[eInst].tFCSpiStat.u16TxIndex])); + s_atFCSpiInfo[eInst].tFCSpiStat.u16TxIndex += sizeof(uint32_t); + break; + } + + s_atFCSpiInfo[eInst].tFCSpiStat.u16TxSendByteCntOfCurFrame = + (uint16_t)((s_atFCSpiInfo[eInst].tFCSpiStat.u16TxSendByteCntOfCurFrame + u16ThisSendByteCnt) % + s_atFCSpiInfo[eInst].tFCSpiStat.u16BytesCntFrameNeed); + } + + FCSPI_HWA_WriteData(s_atFCSpiInfo[eInst].tFCSpiInstance, u32DataToSend); + /* Update internal variable used in transmission. */ + s_atFCSpiInfo[eInst].tFCSpiStat.u16TxByteCntRemainToSend -= u16ThisSendByteCnt; + u16BytesTxLeft = s_atFCSpiInfo[eInst].tFCSpiStat.u16TxByteCntRemainToSend; + u8TxFifoFreeWordCnt -= (uint8_t)1; + } +} + +/* MASTER side API */ +/*----------------------------------------------------------------------------*/ +/** + * @brief Init the FCSpi instance as spi master side + * + * @param eInst Which FCSpi Hardware instance + * @param pCfg Configuration of the FCSpi, MUST NOT NULL + * @return FCSPI_StatusType FCSPI_STATUS_SUCCESS when configure successfully. Others, some error occur. + */ +FCSPI_StatusType FCSPI_Master_Init(const FCSPI_InstanceType eInst, const FCSPI_MasterCfgType *pCfg) +{ + uint32_t u32BaudRate = 0U; + uint32_t u32PrescaleRegVal = 0U; + uint32_t u32SckDiv = 0U; + FCSPI_TxRxCtrlType tTxRxCtrlCfg; + FCSPI_StatusType eRet = FCSPI_STATUS_SUCCESS; + + if (NULL != pCfg) + { + if ((pCfg->u16BitCountPerFrame >= (uint16_t)8) && + (pCfg->u16BitCountPerFrame <= (uint16_t)4096)) /* TR_CTRL[FRM_SZ] 12bits */ + { + u32BaudRate = FCSpi_Hw_Master_CalcBaudRate(pCfg, &u32PrescaleRegVal, &u32SckDiv); + if (0U != u32BaudRate) + { + FCSpi_Hw_Reset(eInst, FCSPI_FALSE, FCSPI_FALSE, FCSPI_TRUE); + FCSPI_HWA_SetMasterMode(s_atFCSpiInfo[eInst].tFCSpiInstance); + FCSpi_Hw_SetPcs_2_3_Mode(eInst, PCS2_3_PCS); + FCSpi_Hw_SetPin(eInst, SIN_INPUT_SOUT_OUTPUT, PINOUT_RETAIN_LAST); + + /* set internal state parameters for spi */ + s_atFCSpiInfo[eInst].tFCSpiStat.u8TxFifoSize = (uint8_t)FCSPI_DRV_TX_FIFO_WORD_CNT; + s_atFCSpiInfo[eInst].tFCSpiStat.u8RxFifoSize = (uint8_t)FCSPI_DRV_RX_FIFO_WORD_CNT; + s_atFCSpiInfo[eInst].tFCSpiStat.u32DmaDummyData = 0U; + s_atFCSpiInfo[eInst].tFCSpiStat.u16BitsPerFrame = pCfg->u16BitCountPerFrame; + s_atFCSpiInfo[eInst].tFCSpiStat.u16BytesCntFrameNeed = (uint16_t)(((pCfg->u16BitCountPerFrame + (uint16_t)7)) >> (uint16_t)3); + s_atFCSpiInfo[eInst].tFCSpiStat.eIsPcsContinuous = pCfg->eIsPcsContinuous; + s_atFCSpiInfo[eInst].tFCSpiStat.u32FCSpiSrcClk = pCfg->u32FCSpiSrcClk; + s_atFCSpiInfo[eInst].tFCSpiStat.eIsInTransfer = FCSPI_FALSE; + s_atFCSpiInfo[eInst].tFCSpiStat.eBitFirstOrder = pCfg->eBitFirstOrder; + s_atFCSpiInfo[eInst].tFCSpiStat.eTransferTriggerSrc = pCfg->eTransferTriggerSrc; + s_atFCSpiInfo[eInst].tFCSpiStat.eSckPolarity = pCfg->eSckPolarity; + s_atFCSpiInfo[eInst].tFCSpiStat.eSckSamplePhase = pCfg->eSckSamplePhase; + s_atFCSpiInfo[eInst].tFCSpiStat.ePcs = pCfg->ePcs; + s_atFCSpiInfo[eInst].tFCSpiStat.ePcsPolarity = pCfg->ePcsPolarity; + s_atFCSpiInfo[eInst].tFCSpiStat.u32Baundrate = u32BaudRate; + + /* DMA require frames of 3 bytes per frame handled as 4 bytes per frame. */ + if (s_atFCSpiInfo[eInst].tFCSpiStat.u16BytesCntFrameNeed == (uint16_t)3) + { + s_atFCSpiInfo[eInst].tFCSpiStat.u16BytesCntFrameNeed = (uint16_t)4; + } + /* 4 bytes align requirement when > 32bits */ + if (s_atFCSpiInfo[eInst].tFCSpiStat.u16BytesCntFrameNeed > (uint16_t)4) + { + s_atFCSpiInfo[eInst].tFCSpiStat.u16BytesCntFrameNeed = + ((((s_atFCSpiInfo[eInst].tFCSpiStat.u16BytesCntFrameNeed + (uint16_t)3)) >> (uint16_t)2)) << (uint16_t)2; + } + + s_atFCSpiInfo[eInst].tFCSpiStat.tTriggerDmaInf = pCfg->tTriggerDmaInf; + s_atFCSpiInfo[eInst].tFCSpiStat.pStopNotifyCb = pCfg->pStopNotifyCb; + s_atFCSpiInfo[eInst].tFCSpiStat.pSemaResetCb = pCfg->pSemaResetCb; + s_atFCSpiInfo[eInst].tFCSpiStat.pSemaTakeCb = pCfg->pSemaTakeCb; + s_atFCSpiInfo[eInst].tFCSpiStat.pSemaPostCb = pCfg->pSemaPostCb; + + /* Configure the desired PCS polarity */ + FCSpi_Hw_SetOnePcsPolarity(eInst, pCfg->ePcs, pCfg->ePcsPolarity); + + /* enable sample delay */ + FCSpi_Hw_Master_SetSckLoopbackSample(eInst, FCSPI_TRUE); + + /* set up the baudrate */ + FCSpi_Hw_Set_SCK_PCS_DIV_Hold(eInst, + (uint8_t)(u32SckDiv >> 2U), + (uint8_t)(u32SckDiv >> 2U), + (uint8_t)(u32SckDiv >> 2U), + (uint8_t)u32SckDiv); /* write best baudrate scaler to SCKDIV */ + + /* Write the TCR for this transfer. */ + tTxRxCtrlCfg.eSckPolarity = pCfg->eSckPolarity; + tTxRxCtrlCfg.eSckPhase = pCfg->eSckSamplePhase; + tTxRxCtrlCfg.ePrescalerValue = (FCSPI_PrescaleValueType)u32PrescaleRegVal; + tTxRxCtrlCfg.ePCSSelect = pCfg->ePcs; + tTxRxCtrlCfg.eBitFirstOrder = pCfg->eBitFirstOrder; + tTxRxCtrlCfg.eByteSwap = FCSPI_FALSE; + tTxRxCtrlCfg.eContTransEnable = pCfg->eIsPcsContinuous; + tTxRxCtrlCfg.eContCmdEnable = FCSPI_FALSE; + tTxRxCtrlCfg.eRxDisable = FCSPI_FALSE; + tTxRxCtrlCfg.eTxDisable = FCSPI_FALSE; + tTxRxCtrlCfg.eTransferWidth = FCSPI_TRANSFER_1_BIT; + tTxRxCtrlCfg.u16FrameBitCnt = pCfg->u16BitCountPerFrame; + eRet = FCSpi_Hw_SetTRCR(eInst, &tTxRxCtrlCfg); + + if (FCSPI_STATUS_SUCCESS == eRet) + { + if (FCSPI_TRANSFER_TRIGGER_SRC_USER_POLL != pCfg->eTransferTriggerSrc) + { + IntMgr_EnableInterrupt(s_atFCSpiInfo[eInst].eFCSpiIrq); + } + + FCSPI_HWA_ModuleEnable(s_atFCSpiInfo[eInst].tFCSpiInstance); + } + else + { + eRet = FCSPI_STATUS_ERROR; + } + } + else + { + eRet = FCSPI_STATUS_ERROR; + } + } + else + { + eRet = FCSPI_STATUS_PARAM_ERR; + } + } + else + { + eRet = FCSPI_STATUS_PARAM_ERR; + } + + return eRet; +} + +/** + * @brief Deinit the FCSpi + * + * @param eInst Which FCSpi Hardware instance + * @return FCSPI_StatusType FCSPI_STATUS_SUCCESS when deinit the FCSpi successfully. Others, the hardware is busy now. + */ +FCSPI_StatusType FCSPI_Deinit(const FCSPI_InstanceType eInst) +{ + FCSPI_StatusType eRet = FCSPI_STATUS_SUCCESS; + + if (FCSPI_TRUE != s_atFCSpiInfo[eInst].tFCSpiStat.eIsInTransfer) + { + /* reset registers, disabling spi module */ + FCSpi_Hw_Reset(eInst, FCSPI_FALSE, FCSPI_FALSE, FCSPI_TRUE); + } + else + { + eRet = FCSPI_STATUS_BUSY; + } + + return eRet; +} + +/** + * @brief Configure the holding time (in us) between PCS and SCK + * + * @param eInst Which FCSpi Hardware instance + * @param pCfg Configure the delay parameters between PCS and SCK, MUST NOT null + * @return FCSPI_StatusType FCSPI_STATUS_SUCCESS when configure successfully. Others, the hardware is busy now. + */ +FCSPI_StatusType FCSPI_Master_SetSckPcsHoldTime(const FCSPI_InstanceType eInst, + const FCSPI_MasterSckPcsHoldTimeType *pCfg) +{ + FCSPI_StatusType eStat = FCSPI_STATUS_SUCCESS; + uint32_t u32PCSPCSCycle, + u32SCKPCSCycle, + u32PCSSCKCycle; + FCSPI_PrescaleValueType ePrescaler; + uint32_t u32PrescaleValue; + uint32_t u32ClkAfterScalePerUs; + + if (NULL != pCfg) + { + /* disable FCSPI first */ + eStat = FCSpi_Hw_Disable(eInst); + if (FCSPI_STATUS_SUCCESS == eStat) + { + ePrescaler = FCSpi_Hw_GetRegPrescalerVal(eInst); + u32PrescaleValue = FCSpi_Hw_PrescalerRegToActualVal(ePrescaler); + if (0U != u32PrescaleValue) /* actually unreachable */ + { + u32ClkAfterScalePerUs = (uint32_t)(s_atFCSpiInfo[eInst].tFCSpiStat.u32FCSpiSrcClk / + u32PrescaleValue / (uint32_t)1000000); + u32PCSPCSCycle = pCfg->u32PCStoPCSHoldUs * u32ClkAfterScalePerUs; + u32SCKPCSCycle = pCfg->u32SCKtoPCSHoldUs * u32ClkAfterScalePerUs; + u32PCSSCKCycle = pCfg->u32PCStoSCKHoldUs * u32ClkAfterScalePerUs; + + if (u32PCSPCSCycle > (uint32_t)257U) + { + u32PCSPCSCycle = (uint32_t)257U; + } + + if(u32SCKPCSCycle > (uint32_t)256U) + { + u32SCKPCSCycle = (uint32_t)256U; + } + + if(u32PCSSCKCycle > (uint32_t)256U) + { + u32PCSSCKCycle = (uint32_t)256U; + } + + if (u32PCSPCSCycle < (uint32_t)2U) + { + u32PCSPCSCycle = (uint32_t)2U; + } + + if(u32SCKPCSCycle == (uint32_t)0) + { + u32SCKPCSCycle = (uint32_t)1U; + } + + if(u32PCSSCKCycle == (uint32_t)0U) + { + u32PCSSCKCycle = (uint32_t)1U; + } + + FCSpi_Hw_Set_SCK_PCS_Hold(eInst, + (uint8_t)(u32SCKPCSCycle - 1U), + (uint8_t)(u32PCSSCKCycle - 1U), + (uint8_t)(u32PCSPCSCycle - 2U)); + /* Enable module */ + FCSPI_HWA_ModuleEnable(s_atFCSpiInfo[eInst].tFCSpiInstance); + } + else + { + eStat = FCSPI_STATUS_ERROR; + } + } + else + { + eStat = FCSPI_STATUS_BUSY; + } + } + else + { + eStat = FCSPI_STATUS_PARAM_ERR; + } + + return eStat; +} + +/** + * @brief Configure the holding time (in SCK/100) between PCS and SCK + * + * @param eInst Which FCSpi Hardware instance + * @param pCfg Configure the delay parameters between PCS and SCK, MUST NOT null + * @return FCSPI_StatusType FCSPI_STATUS_SUCCESS when configure successfully. Others, the hardware is busy now. + */ +FCSPI_StatusType FCSPI_Master_SetSckPcsHoldSckPercentage( + const FCSPI_InstanceType eInst, const FCSPI_MasterSckPcsHoldSckCycleType *pCfg) +{ + uint8_t u8PCSPCSCycle; + uint8_t u8SCKPCSCycle; + uint8_t u8PCSSCKCycle; + uint8_t u8SckDiv; + FCSPI_StatusType eRet = FCSPI_STATUS_SUCCESS; + + if (NULL != pCfg) + { + /* disable FCSPI first */ + eRet = FCSpi_Hw_Disable(eInst); + if (FCSPI_STATUS_SUCCESS == eRet) + { + FCSpi_Hw_Get_SCK_PCS_DIV_Hold(eInst, NULL, NULL, NULL, &u8SckDiv); + + u8PCSPCSCycle = (uint8_t)((uint32_t)pCfg->u32PCStoPCSHoldPercentage * + (uint32_t)u8SckDiv / (uint32_t)100); + u8SCKPCSCycle = (uint8_t)((uint32_t)pCfg->u32SCKtoPCSHoldPercentage * + (uint32_t)u8SckDiv / (uint32_t)100); + u8PCSSCKCycle = (uint8_t)((uint32_t)pCfg->u32PCStoSCKHoldPercentage * + (uint32_t)u8SckDiv / (uint32_t)100); + + if (u8PCSPCSCycle < (uint8_t)2) + { + u8PCSPCSCycle = (uint8_t)2; + } + + if(u8SCKPCSCycle == (uint8_t)0) + { + u8SCKPCSCycle = (uint8_t)1; + } + + if(u8PCSSCKCycle == (uint8_t)0) + { + u8PCSSCKCycle = (uint8_t)1; + } + + FCSpi_Hw_Set_SCK_PCS_Hold(eInst, + (uint8_t)(u8SCKPCSCycle - (uint8_t)1), + (uint8_t)(u8PCSSCKCycle - (uint8_t)1), + (uint8_t)(u8PCSPCSCycle - (uint8_t)2)); + /* Enable module */ + FCSPI_HWA_ModuleEnable(s_atFCSpiInfo[eInst].tFCSpiInstance); + } + else + { + eRet = FCSPI_STATUS_BUSY; + } + } + else + { + eRet = FCSPI_STATUS_PARAM_ERR; + } + + return eRet; +} + +/** + * @brief Select the PCS to use and configure + * + * @param eInst Which FCSpi Hardware instance + * @param pCfg Parameters about PCS configuration, MUST NOT null + * @return FCSPI_StatusType FCSPI_STATUS_SUCCESS when configure successfully. Others, the hardware is busy now. + */ +FCSPI_StatusType FCSPI_Master_SelectPcs( + const FCSPI_InstanceType eInst, const FCSPI_MasterPcsConfType *pCfg) +{ + FCSPI_StatusType eRet = FCSPI_STATUS_SUCCESS; + + if (pCfg) + { + eRet = FCSpi_Hw_Disable(eInst); + if (FCSPI_STATUS_SUCCESS == eRet) + { + FCSpi_Hw_SetOnePcsPolarity(eInst, pCfg->ePcs, pCfg->ePolarity); + FCSPI_HWA_ModuleEnable(s_atFCSpiInfo[eInst].tFCSpiInstance); + FCSpi_Hw_SelectUsePcs(eInst, pCfg->ePcs); + } + else + { + eRet = FCSPI_STATUS_BUSY; + } + } + else + { + eRet = FCSPI_STATUS_PARAM_ERR; + } + + return eRet; +} + +static void fcspi_master_clean_transfer(FCSPI_InstanceType eInst, FCSPI_AtomicBoolType bIsInInterrupt) +{ + s_atFCSpiInfo[eInst].tFCSpiStat.eIsInTransfer = FCSPI_FALSE; + + if (FCSPI_TRANSFER_TRIGGER_SRC_DMA_ISR == s_atFCSpiInfo[eInst].tFCSpiStat.eTransferTriggerSrc) + { + FCSpi_Hw_SetRxTxDmaEnableStatus(eInst, FCSPI_FALSE, FCSPI_FALSE); + } + else + { + FCSpi_Hw_DisableSomeInterrupts(eInst, + FCSPI_INT_EN_RFIE(1) | FCSPI_INT_EN_TFIE(1)); + } + + FCSpi_Hw_DisableSomeInterrupts(eInst, + FCSPI_INT_EN_RFOIE(1) | FCSPI_INT_EN_TFUIE(1) | FCSPI_INT_EN_TCIE(1)); + FCSpi_Hw_ClearSomeStatusW1CFlag(eInst, + FCSPI_STATUS_RX_FO(1) | FCSPI_STATUS_TX_FU(1) | FCSPI_STATUS_TCF(1)); + + if (FCSPI_TRUE == bIsInInterrupt) + { + if (NULL != s_atFCSpiInfo[eInst].tFCSpiStat.pStopNotifyCb) + { + s_atFCSpiInfo[eInst].tFCSpiStat.pStopNotifyCb(eInst, FCSPI_TRUE); + } + + if (s_atFCSpiInfo[eInst].tFCSpiStat.u8WaitSemaphore) + { + s_atFCSpiInfo[eInst].tFCSpiStat.pSemaPostCb(eInst, FCSPI_TRUE); + s_atFCSpiInfo[eInst].tFCSpiStat.u8WaitSemaphore = (uint8_t)0; + } + } + else + { + if (NULL != s_atFCSpiInfo[eInst].tFCSpiStat.pStopNotifyCb) + { + s_atFCSpiInfo[eInst].tFCSpiStat.pStopNotifyCb(eInst, FCSPI_FALSE); + } + + if (s_atFCSpiInfo[eInst].tFCSpiStat.u8WaitSemaphore) + { + s_atFCSpiInfo[eInst].tFCSpiStat.pSemaPostCb(eInst, FCSPI_FALSE); + s_atFCSpiInfo[eInst].tFCSpiStat.u8WaitSemaphore = (uint8_t)0; + } + } +} + +static void fcspi_master_abort_transfer(FCSPI_InstanceType eInst, FCSPI_AtomicBoolType bIsInISR) +{ + fcspi_master_clean_transfer(eInst, bIsInISR); + + /* clean the fifo */ + FCSpi_Hw_Reset(eInst, FCSPI_TRUE, FCSPI_TRUE, FCSPI_FALSE); + FCSpi_Hw_Reset(eInst, FCSPI_TRUE, FCSPI_TRUE, FCSPI_FALSE); /* for shifter */ +} + +static void fcspi_master_dma_rx_err_interrupt(FCSPI_InstanceType eInst) +{ + s_atFCSpiInfo[eInst].tFCSpiStat.eTransferStat = FCSPI_TRANSFER_RX_FAIL; + fcspi_master_abort_transfer(eInst, FCSPI_TRUE); +} + +static void fcspi_0_master_dma_rx_err_interrupt(void) +{ + fcspi_master_dma_rx_err_interrupt(FCSPI_0); +} + +static void fcspi_1_master_dma_rx_err_interrupt(void) +{ + fcspi_master_dma_rx_err_interrupt(FCSPI_1); +} + +static void fcspi_2_master_dma_rx_err_interrupt(void) +{ + fcspi_master_dma_rx_err_interrupt(FCSPI_2); +} + +static void fcspi_3_master_dma_rx_err_interrupt(void) +{ + fcspi_master_dma_rx_err_interrupt(FCSPI_3); +} + +static void fcspi_4_master_dma_rx_err_interrupt(void) +{ + fcspi_master_dma_rx_err_interrupt(FCSPI_4); +} + +static void fcspi_5_master_dma_rx_err_interrupt(void) +{ + fcspi_master_dma_rx_err_interrupt(FCSPI_5); +} + +static void fcspi_master_dma_rx_finish_interrupt(void) +{ + ; /* in master mode, the tx trigger the sclk output, so when rx finish, ignore. */ +} + +static void fcspi_master_dma_tx_err_interrupt(FCSPI_InstanceType eInst) +{ + s_atFCSpiInfo[eInst].tFCSpiStat.eTransferStat = FCSPI_TRANSFER_TX_FAIL; + fcspi_master_abort_transfer(eInst, FCSPI_TRUE); +} + +static void fcspi_0_master_dma_tx_err_interrupt(void) +{ + fcspi_master_dma_tx_err_interrupt(FCSPI_0); +} + +static void fcspi_1_master_dma_tx_err_interrupt(void) +{ + fcspi_master_dma_tx_err_interrupt(FCSPI_1); +} + +static void fcspi_2_master_dma_tx_err_interrupt(void) +{ + fcspi_master_dma_tx_err_interrupt(FCSPI_2); +} + +static void fcspi_3_master_dma_tx_err_interrupt(void) +{ + fcspi_master_dma_tx_err_interrupt(FCSPI_3); +} + +static void fcspi_4_master_dma_tx_err_interrupt(void) +{ + fcspi_master_dma_tx_err_interrupt(FCSPI_4); +} + +static void fcspi_5_master_dma_tx_err_interrupt(void) +{ + fcspi_master_dma_tx_err_interrupt(FCSPI_5); +} + +static void fcspi_master_dma_tx_finish_interrupt(FCSPI_InstanceType eInst) +{ + if (FCSPI_TRUE == s_atFCSpiInfo[eInst].tFCSpiStat.eIsPcsContinuous) + { + FCSpi_Hw_SetContinuousCommand(eInst, FCSPI_FALSE); + } + + s_atFCSpiInfo[eInst].tFCSpiStat.u16TxByteCntRemainToSend = (uint16_t)0; + s_atFCSpiInfo[eInst].tFCSpiStat.u16RxByteCntRemainToGet = (uint16_t)0; + + /* DMA -> TX FIFO -> PIN, DMA send to tx fifo finish, enable tx fifo finish interrupt */ + FCSpi_Hw_EnableTransmitCompleteInterrupt(eInst); +} + +static void fcspi_0_master_dma_tx_finish_interrupt(void) +{ + fcspi_master_dma_tx_finish_interrupt(FCSPI_0); +} + +static void fcspi_1_master_dma_tx_finish_interrupt(void) +{ + fcspi_master_dma_tx_finish_interrupt(FCSPI_1); +} + +static void fcspi_2_master_dma_tx_finish_interrupt(void) +{ + fcspi_master_dma_tx_finish_interrupt(FCSPI_2); +} + +static void fcspi_3_master_dma_tx_finish_interrupt(void) +{ + fcspi_master_dma_tx_finish_interrupt(FCSPI_3); +} + +static void fcspi_4_master_dma_tx_finish_interrupt(void) +{ + fcspi_master_dma_tx_finish_interrupt(FCSPI_4); +} + +static void fcspi_5_master_dma_tx_finish_interrupt(void) +{ + fcspi_master_dma_tx_finish_interrupt(FCSPI_5); +} + +/* if enter transfer state, return success, others, not start tranfer */ +static FCSPI_StatusType fcspi_master_async_transfer_bytes(FCSPI_InstanceType eInst, + const uint8_t *pSendBuffer, uint8_t *pReceiveBuffer, + uint16_t u16TransferByteCnt) +{ + DMA_InterruptCfgType tDmaTxInterruptCfg = {0}; + DMA_ChannelCfgType tDmaTxChnlCfg = {0}; + uint8_t u8DmaTxBlkByteCnt = (uint8_t)1; + DMA_InterruptCfgType tDmaRxInterruptCfg = {0}; + DMA_ChannelCfgType tDmaRxChnlCfg = {0}; + uint8_t u8DmaRxBlkByteCnt = (uint8_t)1; + FCSPI_StatusType eRet = FCSPI_STATUS_SUCCESS; + uint32_t u32StatRegVal = 0u; + + if ((uint16_t)0 != s_atFCSpiInfo[eInst].tFCSpiStat.u16BytesCntFrameNeed) + { + if ((uint16_t)0 != u16TransferByteCnt) + { + if ((u16TransferByteCnt % s_atFCSpiInfo[eInst].tFCSpiStat.u16BytesCntFrameNeed) == (uint16_t)0) + { + u32StatRegVal = FCSPI_HWA_GetStatus(s_atFCSpiInfo[eInst].tFCSpiInstance); + if ((FCSPI_TRUE != s_atFCSpiInfo[eInst].tFCSpiStat.eIsInTransfer) && + (!FCSpi_Hw_ChkBusy(u32StatRegVal))) + { + if (!FCSpi_Hw_ChkBusy(FCSPI_HWA_GetStatus(s_atFCSpiInfo[eInst].tFCSpiInstance))) + { + FCSpi_Hw_Reset(eInst, FCSPI_TRUE, FCSPI_TRUE, FCSPI_FALSE); + FCSpi_Hw_Reset(eInst, FCSPI_TRUE, FCSPI_TRUE, FCSPI_FALSE); /* ensure clear data in shifter */ + + /* if pcs need continuous, set command continuous bit */ + if (s_atFCSpiInfo[eInst].tFCSpiStat.eIsPcsContinuous) + { + FCSpi_Hw_SetContinuousCommand(eInst, FCSPI_TRUE); + } + + s_atFCSpiInfo[eInst].tFCSpiStat.eTransferStat = FCSPI_TRANSFER_OK; + + FCSPI_HWA_SetWatermark(s_atFCSpiInfo[eInst].tFCSpiInstance, (uint8_t)0, (uint8_t)2); + + FCSpi_Hw_ClearSomeStatusW1CFlag(eInst, FCSPI_DRV_STATUS_REG_W1C_U32); + FCSpi_Hw_EnableMoreInterrupts(eInst, FCSPI_INT_EN_TFUIE(1)); + + /* if rx needed, enable overflow interrupt and rx */ + if (NULL != pReceiveBuffer) + { + FCSpi_Hw_EnableMoreInterrupts(eInst, FCSPI_INT_EN_RFOIE(1)); + s_atFCSpiInfo[eInst].tFCSpiStat.u16RxByteCntRemainToGet = u16TransferByteCnt; + FCSPI_HWA_EnableRxDataMask(s_atFCSpiInfo[eInst].tFCSpiInstance, FCSPI_TRUE); + } + else + { + s_atFCSpiInfo[eInst].tFCSpiStat.u16RxByteCntRemainToGet = (uint16_t)0; + FCSPI_HWA_EnableRxDataMask(s_atFCSpiInfo[eInst].tFCSpiInstance, FCSPI_FALSE); + } + + if (FCSPI_TRANSFER_TRIGGER_SRC_DMA_ISR == s_atFCSpiInfo[eInst].tFCSpiStat.eTransferTriggerSrc) + { + /* TX */ + tDmaTxChnlCfg.u8ChannelPriority = s_atFCSpiInfo[eInst].tFCSpiStat.tTriggerDmaInf.u8TxDMAChannelPriority; + tDmaTxChnlCfg.bDestAddrLoopbackEn = false; + tDmaTxChnlCfg.bSrcAddrLoopbackEn = false; + tDmaTxChnlCfg.bAutoStop = true; /* auto stop dma after send finish */ + tDmaTxChnlCfg.bSrcCircularBufferEn = false; + tDmaTxChnlCfg.bDestCircularBufferEn = false; + + switch (s_atFCSpiInfo[eInst].tFCSpiStat.u16BytesCntFrameNeed) + { + case 1: + tDmaTxChnlCfg.eSrcDataSize = DMA_TRANSFER_SIZE_1B; + tDmaTxChnlCfg.eDestDataSize = DMA_TRANSFER_SIZE_1B; + tDmaTxChnlCfg.bSrcBlockOffsetEn = true; + tDmaTxChnlCfg.s32BlockOffset = (int32_t)1; + u8DmaTxBlkByteCnt = (uint8_t)1; + break; + + case 2: + tDmaTxChnlCfg.eSrcDataSize = DMA_TRANSFER_SIZE_2B; + tDmaTxChnlCfg.eDestDataSize = DMA_TRANSFER_SIZE_2B; + tDmaTxChnlCfg.bSrcBlockOffsetEn = true; + tDmaTxChnlCfg.s32BlockOffset = (int32_t)2; + u8DmaTxBlkByteCnt = (uint8_t)2; + break; + + default: + tDmaTxChnlCfg.eSrcDataSize = DMA_TRANSFER_SIZE_4B; + tDmaTxChnlCfg.eDestDataSize = DMA_TRANSFER_SIZE_4B; + tDmaTxChnlCfg.bSrcBlockOffsetEn = true; + tDmaTxChnlCfg.s32BlockOffset = (int32_t)4; + u8DmaTxBlkByteCnt = (uint8_t)4; + break; + } + + tDmaTxChnlCfg.u16BlockCount = u16TransferByteCnt / u8DmaTxBlkByteCnt; + tDmaTxChnlCfg.bDestBlockOffsetEn = false; + + tDmaTxInterruptCfg.bTransferCompleteIntEn = true; + tDmaTxInterruptCfg.bTransferErrorIntEn = true; + switch (eInst) + { + case FCSPI_0: + tDmaTxChnlCfg.eTriggerSrc = DMA_REQ_FCSPI0_TX; + tDmaTxInterruptCfg.pTransferCompleteNotify = fcspi_0_master_dma_tx_finish_interrupt; + tDmaTxInterruptCfg.pTransferErrorNotify = fcspi_0_master_dma_tx_err_interrupt; + break; + + case FCSPI_1: + tDmaTxChnlCfg.eTriggerSrc = DMA_REQ_FCSPI1_TX; + tDmaTxInterruptCfg.pTransferCompleteNotify = fcspi_1_master_dma_tx_finish_interrupt; + tDmaTxInterruptCfg.pTransferErrorNotify = fcspi_1_master_dma_tx_err_interrupt; + break; + + case FCSPI_2: + tDmaTxChnlCfg.eTriggerSrc = DMA_REQ_FCSPI2_TX; + tDmaTxInterruptCfg.pTransferCompleteNotify = fcspi_2_master_dma_tx_finish_interrupt; + tDmaTxInterruptCfg.pTransferErrorNotify = fcspi_2_master_dma_tx_err_interrupt; + break; + + case FCSPI_3: + tDmaTxChnlCfg.eTriggerSrc = DMA_REQ_FCSPI3_TX; + tDmaTxInterruptCfg.pTransferCompleteNotify = fcspi_3_master_dma_tx_finish_interrupt; + tDmaTxInterruptCfg.pTransferErrorNotify = fcspi_3_master_dma_tx_err_interrupt; + break; + + case FCSPI_4: + tDmaTxChnlCfg.eTriggerSrc = DMA_REQ_FCSPI4_TX; + tDmaTxInterruptCfg.pTransferCompleteNotify = fcspi_4_master_dma_tx_finish_interrupt; + tDmaTxInterruptCfg.pTransferErrorNotify = fcspi_4_master_dma_tx_err_interrupt; + break; + + case FCSPI_5: + tDmaTxChnlCfg.eTriggerSrc = DMA_REQ_FCSPI5_TX; + tDmaTxInterruptCfg.pTransferCompleteNotify = fcspi_5_master_dma_tx_finish_interrupt; + tDmaTxInterruptCfg.pTransferErrorNotify = fcspi_5_master_dma_tx_err_interrupt; + break; + + default: + tDmaTxChnlCfg.eTriggerSrc = DMA_REQ_FCSPI3_TX; + tDmaTxInterruptCfg.pTransferCompleteNotify = fcspi_3_master_dma_tx_finish_interrupt; + tDmaTxInterruptCfg.pTransferErrorNotify = fcspi_3_master_dma_tx_err_interrupt; + break; + } + + tDmaTxChnlCfg.eDestIncMode = DMA_INCREMENT_DISABLE; + tDmaTxChnlCfg.eSrcIncMode = DMA_INCREMENT_DISABLE; + tDmaTxChnlCfg.pDestBuffer = FCSPI_HWA_GetTxDataAddr(s_atFCSpiInfo[eInst].tFCSpiInstance); + tDmaTxChnlCfg.u32BlockSize = (uint32_t)u8DmaTxBlkByteCnt; + + if (NULL != pSendBuffer) + { + tDmaTxChnlCfg.pSrcBuffer = pSendBuffer; + } + else + { + tDmaTxChnlCfg.pSrcBuffer = &(s_atFCSpiInfo[eInst].tFCSpiStat.u32DmaDummyData); + tDmaTxChnlCfg.bSrcBlockOffsetEn = false; /* if send buffer is NULL, just send dummy data, MUST fix the source to the dummy variable */ + tDmaTxChnlCfg.s32BlockOffset = (int32_t)0; + } + + DMA_InitChannel(s_atFCSpiInfo[eInst].tFCSpiStat.tTriggerDmaInf.eDMAInstance, (DMA_ChannelType)s_atFCSpiInfo[eInst].tFCSpiStat.tTriggerDmaInf.u8TxDMAChannel, &tDmaTxChnlCfg); + + /* RX */ + /* if needed, configure the DMA Rx function */ + if (NULL != pReceiveBuffer) + { + tDmaRxChnlCfg.u8ChannelPriority = s_atFCSpiInfo[eInst].tFCSpiStat.tTriggerDmaInf.u8RxDMAChannelPriority; + tDmaRxChnlCfg.bDestAddrLoopbackEn = false; + tDmaRxChnlCfg.bSrcAddrLoopbackEn = false; + tDmaRxChnlCfg.bAutoStop = true; /* auto stop dma after send finish */ + tDmaRxChnlCfg.bSrcCircularBufferEn = false; + tDmaRxChnlCfg.bDestCircularBufferEn = false; + + switch (s_atFCSpiInfo[eInst].tFCSpiStat.u16BytesCntFrameNeed) + { + case 1: + tDmaRxChnlCfg.eDestDataSize = DMA_TRANSFER_SIZE_1B; + tDmaRxChnlCfg.eSrcDataSize = DMA_TRANSFER_SIZE_1B; + tDmaRxChnlCfg.bDestBlockOffsetEn = true; + tDmaRxChnlCfg.s32BlockOffset = (int32_t)1; + u8DmaRxBlkByteCnt = (uint8_t)1; + break; + + case 2: + tDmaRxChnlCfg.eDestDataSize = DMA_TRANSFER_SIZE_2B; + tDmaRxChnlCfg.eSrcDataSize = DMA_TRANSFER_SIZE_2B; + tDmaRxChnlCfg.bDestBlockOffsetEn = true; + tDmaRxChnlCfg.s32BlockOffset = (int32_t)2; + u8DmaRxBlkByteCnt = (uint8_t)2; + break; + + default: + tDmaRxChnlCfg.eDestDataSize = DMA_TRANSFER_SIZE_4B; + tDmaRxChnlCfg.eSrcDataSize = DMA_TRANSFER_SIZE_4B; + tDmaRxChnlCfg.bDestBlockOffsetEn = true; + tDmaRxChnlCfg.s32BlockOffset = (int32_t)4; + u8DmaRxBlkByteCnt = (uint8_t)4; + break; + } + + tDmaRxChnlCfg.u16BlockCount = u16TransferByteCnt / u8DmaRxBlkByteCnt; + tDmaRxChnlCfg.bSrcBlockOffsetEn = false; + + tDmaRxInterruptCfg.bTransferCompleteIntEn = true; + tDmaRxInterruptCfg.bTransferErrorIntEn = true; + switch (eInst) + { + case FCSPI_0: + tDmaRxChnlCfg.eTriggerSrc = DMA_REQ_FCSPI0_RX; + tDmaRxInterruptCfg.pTransferCompleteNotify = fcspi_master_dma_rx_finish_interrupt; + tDmaRxInterruptCfg.pTransferErrorNotify = fcspi_0_master_dma_rx_err_interrupt; + break; + + case FCSPI_1: + tDmaRxChnlCfg.eTriggerSrc = DMA_REQ_FCSPI1_RX; + tDmaRxInterruptCfg.pTransferCompleteNotify = fcspi_master_dma_rx_finish_interrupt; + tDmaRxInterruptCfg.pTransferErrorNotify = fcspi_1_master_dma_rx_err_interrupt; + break; + + case FCSPI_2: + tDmaRxChnlCfg.eTriggerSrc = DMA_REQ_FCSPI2_RX; + tDmaRxInterruptCfg.pTransferCompleteNotify = fcspi_master_dma_rx_finish_interrupt; + tDmaRxInterruptCfg.pTransferErrorNotify = fcspi_2_master_dma_rx_err_interrupt; + break; + + case FCSPI_3: + tDmaRxChnlCfg.eTriggerSrc = DMA_REQ_FCSPI3_RX; + tDmaRxInterruptCfg.pTransferCompleteNotify = fcspi_master_dma_rx_finish_interrupt; + tDmaRxInterruptCfg.pTransferErrorNotify = fcspi_3_master_dma_rx_err_interrupt; + break; + + case FCSPI_4: + tDmaRxChnlCfg.eTriggerSrc = DMA_REQ_FCSPI4_RX; + tDmaRxInterruptCfg.pTransferCompleteNotify = fcspi_master_dma_rx_finish_interrupt; + tDmaRxInterruptCfg.pTransferErrorNotify = fcspi_4_master_dma_rx_err_interrupt; + break; + + case FCSPI_5: + tDmaRxChnlCfg.eTriggerSrc = DMA_REQ_FCSPI5_RX; + tDmaRxInterruptCfg.pTransferCompleteNotify = fcspi_master_dma_rx_finish_interrupt; + tDmaRxInterruptCfg.pTransferErrorNotify = fcspi_5_master_dma_rx_err_interrupt; + break; + + default: + tDmaRxChnlCfg.eTriggerSrc = DMA_REQ_FCSPI3_RX; + tDmaRxInterruptCfg.pTransferCompleteNotify = fcspi_master_dma_rx_finish_interrupt; + tDmaRxInterruptCfg.pTransferErrorNotify = fcspi_3_master_dma_rx_err_interrupt; + break; + } + + tDmaRxChnlCfg.eDestIncMode = DMA_INCREMENT_DISABLE; + tDmaRxChnlCfg.eSrcIncMode = DMA_INCREMENT_DISABLE; + tDmaRxChnlCfg.pSrcBuffer = FCSPI_HWA_GetRxDataAddr(s_atFCSpiInfo[eInst].tFCSpiInstance); + tDmaRxChnlCfg.u32BlockSize = (uint32_t)u8DmaRxBlkByteCnt; + tDmaRxChnlCfg.pDestBuffer = pReceiveBuffer; + + DMA_InitChannel(s_atFCSpiInfo[eInst].tFCSpiStat.tTriggerDmaInf.eDMAInstance, + (DMA_ChannelType)s_atFCSpiInfo[eInst].tFCSpiStat.tTriggerDmaInf.u8RxDMAChannel, &tDmaRxChnlCfg); + DMA_InitChannelInterrupt(s_atFCSpiInfo[eInst].tFCSpiStat.tTriggerDmaInf.eDMAInstance, + (DMA_ChannelType)s_atFCSpiInfo[eInst].tFCSpiStat.tTriggerDmaInf.u8RxDMAChannel, &tDmaRxInterruptCfg); + DMA_StartChannel(s_atFCSpiInfo[eInst].tFCSpiStat.tTriggerDmaInf.eDMAInstance, + (DMA_ChannelType)s_atFCSpiInfo[eInst].tFCSpiStat.tTriggerDmaInf.u8RxDMAChannel); + } + + DMA_InitChannelInterrupt(s_atFCSpiInfo[eInst].tFCSpiStat.tTriggerDmaInf.eDMAInstance, + (DMA_ChannelType)s_atFCSpiInfo[eInst].tFCSpiStat.tTriggerDmaInf.u8TxDMAChannel, &tDmaTxInterruptCfg); + + DMA_StartChannel(s_atFCSpiInfo[eInst].tFCSpiStat.tTriggerDmaInf.eDMAInstance, + (DMA_ChannelType)s_atFCSpiInfo[eInst].tFCSpiStat.tTriggerDmaInf.u8TxDMAChannel); + + s_atFCSpiInfo[eInst].tFCSpiStat.eIsInTransfer = FCSPI_TRUE; + + if (pReceiveBuffer) + { + FCSpi_Hw_SetRxTxDmaEnableStatus(eInst, FCSPI_TRUE, FCSPI_TRUE); + } + else + { + /* only enable TX DMA */ + FCSpi_Hw_SetRxTxDmaEnableStatus(eInst, FCSPI_FALSE, FCSPI_TRUE); + } + } + else + { + s_atFCSpiInfo[eInst].tFCSpiStat.pbyTxBuff = pSendBuffer; + s_atFCSpiInfo[eInst].tFCSpiStat.pbyRxBuff = pReceiveBuffer; + s_atFCSpiInfo[eInst].tFCSpiStat.u16TxIndex = (uint16_t)0; + s_atFCSpiInfo[eInst].tFCSpiStat.u16RxIndex = (uint16_t)0; + s_atFCSpiInfo[eInst].tFCSpiStat.u16TxSendByteCntOfCurFrame = (uint16_t)0; + s_atFCSpiInfo[eInst].tFCSpiStat.u16RxGetByteCntOfCurFrame = (uint16_t)0; + s_atFCSpiInfo[eInst].tFCSpiStat.u16TxByteCntRemainToSend = u16TransferByteCnt; + if (FCSPI_TRUE == s_atFCSpiInfo[eInst].tFCSpiStat.eIsPcsContinuous) + { + /* continuous transfer need an extra word to negate PCS */ + s_atFCSpiInfo[eInst].tFCSpiStat.u16TxByteCntRemainToSend++; + } + s_atFCSpiInfo[eInst].tFCSpiStat.eIsInTransfer = FCSPI_TRUE; + + if (NULL != pReceiveBuffer) /* need rx fifo */ + { + FCSpi_Hw_EnableMoreInterrupts(eInst, FCSPI_INT_EN_RFIE(1) | FCSPI_INT_EN_TFIE(1)); + } + else + { + FCSpi_Hw_EnableMoreInterrupts(eInst, FCSPI_INT_EN_TFIE(1)); + } + } + eRet = FCSPI_STATUS_SUCCESS; + } + else + { + eRet = FCSPI_STATUS_BUSY; + } + } + else + { + eRet = FCSPI_STATUS_BUSY; + } + } + else + { + eRet = FCSPI_STATUS_ERROR; + } + } + else + { + eRet = FCSPI_STATUS_NO_DATA; + } + } + else + { + eRet = FCSPI_STATUS_ERROR; + } + + return eRet; +} + +/** + * @brief Send and receive asynchronously + * 1) If the trigger source is driver user poll, this api not support this mode. + * 2) If the trigger source is interrupt or DMA, this api will start the transmission, then return immediately. + * After transmission stop, it will trigger an interrupt. + * During the transmission, the send data buffer and receive data buffer + * should keep valid until the transmission stop. + * @param eInst Which FCSpi Hardware instance + * @param pCfg the data information, MUST NOT null + * @return FCSPI_StatusType FCSPI_STATUS_SUCCESS when start transfer successfully. Others, some error occur. + */ +FCSPI_StatusType FCSPI_AsyncTransfer(const FCSPI_InstanceType eInst, const FCSPI_AsyncDataInfType *pCfg) +{ + FCSPI_StatusType eRet = FCSPI_STATUS_SUCCESS; + + if (NULL != pCfg) + { + if (FCSPI_TRANSFER_TRIGGER_SRC_USER_POLL != s_atFCSpiInfo[eInst].tFCSpiStat.eTransferTriggerSrc) + { + if (FCSPI_MODE_MASTER == FCSPI_HWA_CheckMode(s_atFCSpiInfo[eInst].tFCSpiInstance)) + { + eRet = fcspi_master_async_transfer_bytes(eInst, + pCfg->pSendBuffer, pCfg->pReceiveBuffer, + pCfg->u16FrameCount * s_atFCSpiInfo[eInst].tFCSpiStat.u16BytesCntFrameNeed); + } + else + { + eRet = fcspi_slave_async_transfer_bytes(eInst, pCfg->pSendBuffer, pCfg->pReceiveBuffer, + s_atFCSpiInfo[eInst].tFCSpiStat.u16BytesCntFrameNeed * pCfg->u16FrameCount); + } + } + else + { + eRet = FCSPI_STATUS_ERROR; + } + } + else + { + eRet = FCSPI_STATUS_PARAM_ERR; + } + + return eRet; +} + +/** + * @brief Send and receive synchronously + * 1) If the semaphore callbacks are configured, + * and the driver is configured transmitting triggered by interrupt, or by DMA, + * the driver will use semaphore to wait the transmission stopped. + * In this case, the timeout value is passed to semaphore callback directly. + * 2) If the semaphore callbacks are not configured, + * this api will poll the status when triggered by interrupt or DMA, + * or poll to trigger the transmission when the mode is "FCSPI_TRANSFER_TRIGGER_SRC_USER_POLL". + * In this case, the timeout value has different meaning for different trigger mode. + * Read the source code for detail. + * @param eInst Which FCSpi Hardware instance + * @param pCfg the data information, MUST NOT null + * @return FCSPI_StatusType FCSPI_STATUS_SUCCESS when transfer successfully. Others, some error occur. + */ +FCSPI_StatusType FCSPI_SyncTransfer(const FCSPI_InstanceType eInst, const FCSPI_SyncDataInfType *pCfg) +{ + FCSPI_StatusType tStatus; + FCSPI_SemaphoreStatType tSemaStat; + FCSPI_StatusType eRet = FCSPI_STATUS_SUCCESS; + FCSPI_AtomicBoolType bIsMaster; + uint32_t u32MonitorTimeout = 0xFFFFFFFFu; + uint16_t u16RxRemain = (uint16_t)0; + uint16_t u16TxRemain = (uint16_t)0; + uint16_t u16PreRxRemain = (uint16_t)0; + uint16_t u16PreTxRemain = (uint16_t)0; + uint32_t u32TryTimeout = 0xFFFFFFFFu; + FCSPI_AtomicBoolType bIsBlockType = FCSPI_TRUE; + bIsMaster = (FCSPI_MODE_MASTER == FCSPI_HWA_CheckMode(s_atFCSpiInfo[eInst].tFCSpiInstance)) ? FCSPI_TRUE : FCSPI_FALSE; + FCSPI_AtomicBoolType bNeedExitLoop = FCSPI_FALSE; + + if (NULL != pCfg) + { + if ((uint16_t)0 != pCfg->u16FrameCount) + { + if ((NULL != s_atFCSpiInfo[eInst].tFCSpiStat.pSemaResetCb) && + (NULL != s_atFCSpiInfo[eInst].tFCSpiStat.pSemaTakeCb) && + (NULL != s_atFCSpiInfo[eInst].tFCSpiStat.pSemaPostCb) && + ((FCSPI_TRANSFER_TRIGGER_SRC_ISR == s_atFCSpiInfo[eInst].tFCSpiStat.eTransferTriggerSrc) || + (FCSPI_TRANSFER_TRIGGER_SRC_DMA_ISR == s_atFCSpiInfo[eInst].tFCSpiStat.eTransferTriggerSrc))) + { + if (FCSPI_SEMAPHORE_SUCCESS == s_atFCSpiInfo[eInst].tFCSpiStat.pSemaResetCb(eInst)) + { + s_atFCSpiInfo[eInst].tFCSpiStat.u8WaitSemaphore = (uint8_t)1; + + if (FCSPI_TRUE == bIsMaster) + { + tStatus = fcspi_master_async_transfer_bytes(eInst, pCfg->pSendBuffer, pCfg->pReceiveBuffer, + s_atFCSpiInfo[eInst].tFCSpiStat.u16BytesCntFrameNeed * pCfg->u16FrameCount); + } + else + { + tStatus = fcspi_slave_async_transfer_bytes(eInst, pCfg->pSendBuffer, pCfg->pReceiveBuffer, + s_atFCSpiInfo[eInst].tFCSpiStat.u16BytesCntFrameNeed * pCfg->u16FrameCount); + } + + if (FCSPI_STATUS_SUCCESS == tStatus) + { + tSemaStat = s_atFCSpiInfo[eInst].tFCSpiStat.pSemaTakeCb(eInst, pCfg->u32Timeout); + if (FCSPI_SEMAPHORE_FAIL == tSemaStat) + { + s_atFCSpiInfo[eInst].tFCSpiStat.u8WaitSemaphore = (uint8_t)0; + s_atFCSpiInfo[eInst].tFCSpiStat.eTransferStat = FCSPI_TRANSFER_ABORT; + if (FCSPI_TRUE == bIsMaster) + { + fcspi_master_abort_transfer(eInst, FCSPI_FALSE); + } + else + { + fcspi_slave_abort_transfer(eInst, FCSPI_FALSE); + } + + eRet = FCSPI_STATUS_ERROR; + } + else if (FCSPI_SEMAPHORE_TIMEOUT == tSemaStat) + { + s_atFCSpiInfo[eInst].tFCSpiStat.u8WaitSemaphore = (uint8_t)0; + s_atFCSpiInfo[eInst].tFCSpiStat.eTransferStat = FCSPI_TRANSFER_ABORT; + if (FCSPI_TRUE == bIsMaster) + { + fcspi_master_abort_transfer(eInst, FCSPI_FALSE); + } + else + { + fcspi_slave_abort_transfer(eInst, FCSPI_FALSE); + } + eRet = FCSPI_STATUS_SYNC_TIMEOUT; + } + else + { + s_atFCSpiInfo[eInst].tFCSpiStat.u8WaitSemaphore = (uint8_t)0; + if (FCSPI_TRANSFER_OK != s_atFCSpiInfo[eInst].tFCSpiStat.eTransferStat) + { + eRet = FCSPI_STATUS_TRANSFER_FAIL; + } + else + { + eRet = FCSPI_STATUS_SUCCESS; + } + } + } + else + { + s_atFCSpiInfo[eInst].tFCSpiStat.u8WaitSemaphore = (uint8_t)0; + eRet = tStatus; + } + } + else + { + eRet = FCSPI_STATUS_ERROR; + } + } + else + { + if (FCSPI_TRUE == bIsMaster) + { + tStatus = fcspi_master_async_transfer_bytes(eInst, pCfg->pSendBuffer, pCfg->pReceiveBuffer, + s_atFCSpiInfo[eInst].tFCSpiStat.u16BytesCntFrameNeed * pCfg->u16FrameCount); + } + else + { + tStatus = fcspi_slave_async_transfer_bytes(eInst, pCfg->pSendBuffer, pCfg->pReceiveBuffer, + s_atFCSpiInfo[eInst].tFCSpiStat.u16BytesCntFrameNeed * pCfg->u16FrameCount); + } + + if (FCSPI_STATUS_SUCCESS == tStatus) + { + if (pCfg->u32Timeout > 0u) + { + u32TryTimeout = pCfg->u32Timeout; + bIsBlockType = FCSPI_FALSE; + } + else + { + bIsBlockType = FCSPI_TRUE; + } + + if (FCSPI_TRANSFER_TRIGGER_SRC_USER_POLL == s_atFCSpiInfo[eInst].tFCSpiStat.eTransferTriggerSrc) + { + if (FCSPI_TRUE == bIsMaster) + { + do { + eRet = fcspi_master_trigger(eInst, FCSPI_FALSE); + if (FCSPI_FALSE == bIsBlockType) + { + u32TryTimeout--; + if (0u == u32TryTimeout) + { + break; + } + } + } while (FCSPI_STATUS_TRIGGER_OK == eRet); + } + else + { + do { + eRet = fcspi_slave_trigger(eInst, FCSPI_FALSE); + + if (FCSPI_FALSE == bIsBlockType) + { + u32TryTimeout--; + if (0u == u32TryTimeout) + { + break; + } + } + } while (FCSPI_STATUS_TRIGGER_OK == eRet); + } + + if (FCSPI_STATUS_TRIGGER_FINISH == eRet) + { + eRet = FCSPI_STATUS_SUCCESS; + } + else if ((FCSPI_FALSE == bIsBlockType) && (0u == u32TryTimeout)) + { + s_atFCSpiInfo[eInst].tFCSpiStat.eTransferStat = FCSPI_TRANSFER_ABORT; + if (FCSPI_TRUE == bIsMaster) + { + fcspi_master_abort_transfer(eInst, FCSPI_FALSE); + } + else + { + fcspi_slave_abort_transfer(eInst, FCSPI_FALSE); + } + eRet = FCSPI_STATUS_SYNC_TIMEOUT; + } + else + { + eRet = FCSPI_STATUS_TRANSFER_FAIL; + } + } + else if ((FCSPI_TRANSFER_TRIGGER_SRC_ISR == s_atFCSpiInfo[eInst].tFCSpiStat.eTransferTriggerSrc) || + (FCSPI_TRANSFER_TRIGGER_SRC_DMA_ISR == s_atFCSpiInfo[eInst].tFCSpiStat.eTransferTriggerSrc)) + { + u32MonitorTimeout = 0xfffff00u; /* ensure 1s */ + + u16PreRxRemain = s_atFCSpiInfo[eInst].tFCSpiStat.u16RxByteCntRemainToGet; + u16PreTxRemain = s_atFCSpiInfo[eInst].tFCSpiStat.u16TxByteCntRemainToSend; + + while (FCSPI_TRUE == s_atFCSpiInfo[eInst].tFCSpiStat.eIsInTransfer) + { + u32MonitorTimeout--; + if (0u == u32MonitorTimeout) + { + bNeedExitLoop = FCSPI_FALSE; + u16RxRemain = s_atFCSpiInfo[eInst].tFCSpiStat.u16RxByteCntRemainToGet; + u16TxRemain = s_atFCSpiInfo[eInst].tFCSpiStat.u16TxByteCntRemainToSend; + if (((u16PreRxRemain == u16RxRemain) && ((uint16_t)0 != u16RxRemain)) || + ((u16PreTxRemain == u16TxRemain) && ((uint16_t)0 != u16TxRemain))) + { + s_atFCSpiInfo[eInst].tFCSpiStat.eTransferStat = FCSPI_TRANSFER_ABORT; + if (FCSPI_TRUE == bIsMaster) + { + fcspi_master_abort_transfer(eInst, FCSPI_FALSE); + } + else + { + fcspi_slave_abort_transfer(eInst, FCSPI_FALSE); + } + + bNeedExitLoop = FCSPI_TRUE; + } + else + { + u16PreRxRemain = u16RxRemain; + u16PreTxRemain = u16TxRemain; + u32MonitorTimeout = 0xfffff00u; + + if (FCSPI_FALSE == bIsBlockType) + { + u32TryTimeout--; + if (0u == u32TryTimeout) + { + bNeedExitLoop = FCSPI_TRUE; + } + } + } + + if (FCSPI_TRUE == bNeedExitLoop) + { + break; + } + } + } + + if ((FCSPI_FALSE == bIsBlockType) && (0u == u32TryTimeout)) + { + s_atFCSpiInfo[eInst].tFCSpiStat.eTransferStat = FCSPI_TRANSFER_ABORT; + if (FCSPI_TRUE == bIsMaster) + { + fcspi_master_abort_transfer(eInst, FCSPI_FALSE); + } + else + { + fcspi_slave_abort_transfer(eInst, FCSPI_FALSE); + } + eRet = FCSPI_STATUS_SYNC_TIMEOUT; + } + else if (FCSPI_TRANSFER_OK == s_atFCSpiInfo[eInst].tFCSpiStat.eTransferStat) + { + eRet = FCSPI_STATUS_SUCCESS; + } + else + { + eRet = FCSPI_STATUS_TRANSFER_FAIL; + } + } + else + { + s_atFCSpiInfo[eInst].tFCSpiStat.eTransferStat = FCSPI_TRANSFER_ABORT; + if (FCSPI_TRUE == bIsMaster) + { + fcspi_master_abort_transfer(eInst, FCSPI_FALSE); + } + else + { + fcspi_slave_abort_transfer(eInst, FCSPI_FALSE); + } + + eRet = FCSPI_STATUS_TRANSFER_FAIL; + } + } + else + { + eRet = tStatus; + } + } + } + else + { + eRet = FCSPI_STATUS_SUCCESS; + } + } + else + { + eRet = FCSPI_STATUS_PARAM_ERR; + } + + return eRet; +} + +static FCSPI_StatusType fcspi_master_trigger( + FCSPI_InstanceType eInst, FCSPI_AtomicBoolType bIsInIsr) +{ + uint32_t u32StatusRegValue; + FCSPI_StatusType eRet = FCSPI_STATUS_TRIGGER_OK; + + /* if an error is detected the transfer will be aborted */ + u32StatusRegValue = FCSPI_HWA_GetStatus(s_atFCSpiInfo[eInst].tFCSpiInstance); + + /* if tx need more data but hungry, and has data, sth wrong */ + if (FCSpi_Hw_ChkTxFifoUnderrun(u32StatusRegValue) && + (NULL != s_atFCSpiInfo[eInst].tFCSpiStat.pbyTxBuff)) + { + s_atFCSpiInfo[eInst].tFCSpiStat.eTransferStat = FCSPI_TRANSFER_TX_FAIL; + fcspi_master_abort_transfer(eInst, bIsInIsr); + eRet = FCSPI_STATUS_TRIGGER_ABORT_TX_FAIL; + } + /* if rx need more space but overflow, and has space to store, sth wrong */ + else if (FCSpi_Hw_ChkRxFifoOverflow(u32StatusRegValue) && + (NULL != s_atFCSpiInfo[eInst].tFCSpiStat.pbyRxBuff)) + { + s_atFCSpiInfo[eInst].tFCSpiStat.eTransferStat = FCSPI_TRANSFER_RX_FAIL; + fcspi_master_abort_transfer(eInst, bIsInIsr); + eRet = FCSPI_STATUS_TRIGGER_ABORT_RX_FAIL; + } + /* rx data ready */ + else + { + if (FCSpi_Hw_ChkRxGreaterThanWater(u32StatusRegValue)) + { + if ((uint16_t)0 != s_atFCSpiInfo[eInst].tFCSpiStat.u16RxByteCntRemainToGet) + { + fcspi_read_rx_fifo(eInst); + } + } + + /* transmit some, need add more */ + if (FCSpi_Hw_ChkTxEqualOrLessThanWater(u32StatusRegValue)) + { + if ((uint16_t)0 != s_atFCSpiInfo[eInst].tFCSpiStat.u16TxByteCntRemainToSend) + { + fcspi_write_tx_fifo(eInst); + } + } + + if ((uint16_t)0 == s_atFCSpiInfo[eInst].tFCSpiStat.u16TxByteCntRemainToSend) + { + /* disable tx interrupt. enable tx completion interrupt.*/ + FCSpi_Hw_DisableTransmitDataInterrupt(eInst); + FCSpi_Hw_EnableTransmitCompleteInterrupt(eInst); + + /* tx finish first, if rx also finish, just check completion */ + if ((uint16_t)0 == s_atFCSpiInfo[eInst].tFCSpiStat.u16RxByteCntRemainToGet) + { + u32StatusRegValue = FCSPI_HWA_GetStatus(s_atFCSpiInfo[eInst].tFCSpiInstance); + if (FCSpi_Hw_ChkTransferComplete(u32StatusRegValue)) + { + fcspi_master_clean_transfer(eInst, bIsInIsr); + eRet = FCSPI_STATUS_TRIGGER_FINISH; + } + } + } + } + return eRet; +} + +/******************************************************************************/ + +static void fcspi_slave_clean_transfer(FCSPI_InstanceType eInst, FCSPI_AtomicBoolType bIsInInterrupt) +{ + s_atFCSpiInfo[eInst].tFCSpiStat.eIsInTransfer = FCSPI_FALSE; + + if (FCSPI_TRANSFER_TRIGGER_SRC_DMA_ISR == s_atFCSpiInfo[eInst].tFCSpiStat.eTransferTriggerSrc) + { + FCSpi_Hw_SetRxTxDmaEnableStatus(eInst, FCSPI_FALSE, FCSPI_FALSE); + } + else + { + FCSpi_Hw_DisableSomeInterrupts(eInst, FCSPI_INT_EN_RFIE(1) | FCSPI_INT_EN_TFIE(1)); + } + + FCSpi_Hw_DisableSomeInterrupts(eInst, FCSPI_INT_EN_RFOIE(1) | FCSPI_INT_EN_TFUIE(1)); + FCSpi_Hw_ClearSomeStatusW1CFlag(eInst, FCSPI_STATUS_RX_FO(1) | FCSPI_STATUS_TX_FU(1)); + + if (FCSPI_TRUE == bIsInInterrupt) + { + if (NULL != s_atFCSpiInfo[eInst].tFCSpiStat.pStopNotifyCb) + { + s_atFCSpiInfo[eInst].tFCSpiStat.pStopNotifyCb(eInst, FCSPI_TRUE); + } + + if (s_atFCSpiInfo[eInst].tFCSpiStat.u8WaitSemaphore) + { + s_atFCSpiInfo[eInst].tFCSpiStat.pSemaPostCb(eInst, FCSPI_TRUE); + s_atFCSpiInfo[eInst].tFCSpiStat.u8WaitSemaphore = (uint8_t)0; + } + } + else + { + if (NULL != s_atFCSpiInfo[eInst].tFCSpiStat.pStopNotifyCb) + { + s_atFCSpiInfo[eInst].tFCSpiStat.pStopNotifyCb(eInst, FCSPI_FALSE); + } + + if (s_atFCSpiInfo[eInst].tFCSpiStat.u8WaitSemaphore) + { + s_atFCSpiInfo[eInst].tFCSpiStat.pSemaPostCb(eInst, FCSPI_FALSE); + s_atFCSpiInfo[eInst].tFCSpiStat.u8WaitSemaphore = (uint8_t)0; + } + } +} + +static void fcspi_slave_abort_transfer(FCSPI_InstanceType eInst, FCSPI_AtomicBoolType bIsInInterrupt) +{ + fcspi_slave_clean_transfer(eInst, bIsInInterrupt); + FCSpi_Hw_Reset(eInst, FCSPI_TRUE, FCSPI_TRUE, FCSPI_FALSE); + FCSpi_Hw_Reset(eInst, FCSPI_TRUE, FCSPI_TRUE, FCSPI_FALSE); /* for shifter */ +} + +/** + * @brief Init the FCSpi instance as spi slave side + * + * @param eInst Which FCSpi Hardware instance + * @param pCfg Configuration of the FCSpi + * @return FCSPI_StatusType FCSPI_STATUS_SUCCESS when configure successfully. Others, some error occur. + */ +FCSPI_StatusType FCSPI_Slave_Init(const FCSPI_InstanceType eInst, const FCSPI_SlaveCfgType * pCfg) +{ + FCSPI_TxRxCtrlType tTxRxCtrlCfg; + FCSPI_StatusType eRet = FCSPI_STATUS_SUCCESS; + + s_atFCSpiInfo[eInst].tFCSpiStat.eBitFirstOrder = pCfg->eBitFirstOrder; + s_atFCSpiInfo[eInst].tFCSpiStat.u16BitsPerFrame = pCfg->u16BitCountPerFrame; + s_atFCSpiInfo[eInst].tFCSpiStat.eTransferTriggerSrc = pCfg->eTransferTriggerSrc; + s_atFCSpiInfo[eInst].tFCSpiStat.tTriggerDmaInf = pCfg->tTriggerDmaInf; + s_atFCSpiInfo[eInst].tFCSpiStat.pStopNotifyCb = pCfg->pStopNotifyCb; + s_atFCSpiInfo[eInst].tFCSpiStat.pSemaResetCb = pCfg->pSemaResetCb; + s_atFCSpiInfo[eInst].tFCSpiStat.pSemaTakeCb = pCfg->pSemaTakeCb; + s_atFCSpiInfo[eInst].tFCSpiStat.pSemaPostCb = pCfg->pSemaPostCb; + s_atFCSpiInfo[eInst].tFCSpiStat.eSckPolarity = pCfg->eSckPolarity; + s_atFCSpiInfo[eInst].tFCSpiStat.eSckSamplePhase = pCfg->eSckSamplePhase; + s_atFCSpiInfo[eInst].tFCSpiStat.ePcs = pCfg->ePcs; + s_atFCSpiInfo[eInst].tFCSpiStat.ePcsPolarity = pCfg->ePcsPolarity; + + s_atFCSpiInfo[eInst].tFCSpiStat.u16BytesCntFrameNeed = + (uint16_t)((s_atFCSpiInfo[eInst].tFCSpiStat.u16BitsPerFrame + (uint16_t)7) >> (uint16_t)3); + + /* DMA use 4 bytes/frame. */ + if ((uint16_t)3 == s_atFCSpiInfo[eInst].tFCSpiStat.u16BytesCntFrameNeed) + { + s_atFCSpiInfo[eInst].tFCSpiStat.u16BytesCntFrameNeed = (uint16_t)4; + } + + /* FCSPI require 4 bytes align when > 32bits. */ + if (s_atFCSpiInfo[eInst].tFCSpiStat.u16BytesCntFrameNeed > (uint16_t)4) + { + s_atFCSpiInfo[eInst].tFCSpiStat.u16BytesCntFrameNeed = (uint16_t) + ((((s_atFCSpiInfo[eInst].tFCSpiStat.u16BytesCntFrameNeed + (uint16_t)3)) >> (uint16_t)2) << (uint16_t)2); + } + + s_atFCSpiInfo[eInst].tFCSpiStat.eIsInTransfer = FCSPI_FALSE; + + FCSpi_Hw_Reset(eInst, FCSPI_FALSE, FCSPI_FALSE, FCSPI_TRUE); + FCSPI_HWA_SetSlaveMode(s_atFCSpiInfo[eInst].tFCSpiInstance); + FCSpi_Hw_SetPcs_2_3_Mode(eInst, PCS2_3_PCS); + FCSpi_Hw_SetPin(eInst, SIN_INPUT_SOUT_OUTPUT, PINOUT_RETAIN_LAST); + /* set fifo size param */ + s_atFCSpiInfo[eInst].tFCSpiStat.u8TxFifoSize = (uint8_t)FCSPI_DRV_TX_FIFO_WORD_CNT; + s_atFCSpiInfo[eInst].tFCSpiStat.u8RxFifoSize = (uint8_t)FCSPI_DRV_RX_FIFO_WORD_CNT; + s_atFCSpiInfo[eInst].tFCSpiStat.u32DmaDummyData = 0xFFu; + + /* Set polarity */ + FCSpi_Hw_SetOnePcsPolarity(eInst, pCfg->ePcs, pCfg->ePcsPolarity); + + /* Write the TCR for this transfer */ + tTxRxCtrlCfg.eSckPolarity = pCfg->eSckPolarity; + tTxRxCtrlCfg.eSckPhase = pCfg->eSckSamplePhase; + tTxRxCtrlCfg.ePrescalerValue = FCSPI_PRESCALE_1; /* not use */ + tTxRxCtrlCfg.ePCSSelect = pCfg->ePcs; + tTxRxCtrlCfg.eBitFirstOrder = pCfg->eBitFirstOrder; + tTxRxCtrlCfg.eByteSwap = FCSPI_FALSE; + tTxRxCtrlCfg.eContTransEnable = FCSPI_FALSE; /* not use */ + tTxRxCtrlCfg.eContCmdEnable = FCSPI_FALSE; /* not use */ + tTxRxCtrlCfg.eRxDisable = FCSPI_FALSE; + tTxRxCtrlCfg.eTxDisable = FCSPI_FALSE; + tTxRxCtrlCfg.eTransferWidth = FCSPI_TRANSFER_1_BIT; + tTxRxCtrlCfg.u16FrameBitCnt = pCfg->u16BitCountPerFrame; + + eRet = FCSpi_Hw_SetTRCR(eInst, &tTxRxCtrlCfg); + if (FCSPI_STATUS_SUCCESS == eRet) + { + FCSPI_HWA_ModuleEnable(s_atFCSpiInfo[eInst].tFCSpiInstance); + + if (FCSPI_TRANSFER_TRIGGER_SRC_USER_POLL != pCfg->eTransferTriggerSrc) + { + IntMgr_EnableInterrupt(s_atFCSpiInfo[eInst].eFCSpiIrq); + } + } + else + { + eRet = FCSPI_STATUS_ERROR; + } + + return eRet; +} + +static void fcspi_slave_dma_rx_err_interrupt(FCSPI_InstanceType eInst) +{ + s_atFCSpiInfo[eInst].tFCSpiStat.eTransferStat = FCSPI_TRANSFER_RX_FAIL; + fcspi_slave_abort_transfer(eInst, FCSPI_TRUE); +} + +static void fcspi_0_slave_dma_rx_err_interrupt(void) +{ + fcspi_slave_dma_rx_err_interrupt(FCSPI_0); +} + +static void fcspi_1_slave_dma_rx_err_interrupt(void) +{ + fcspi_slave_dma_rx_err_interrupt(FCSPI_1); +} + +static void fcspi_2_slave_dma_rx_err_interrupt(void) +{ + fcspi_slave_dma_rx_err_interrupt(FCSPI_2); +} + +static void fcspi_3_slave_dma_rx_err_interrupt(void) +{ + fcspi_slave_dma_rx_err_interrupt(FCSPI_3); +} + +static void fcspi_4_slave_dma_rx_err_interrupt(void) +{ + fcspi_slave_dma_rx_err_interrupt(FCSPI_4); +} + +static void fcspi_5_slave_dma_rx_err_interrupt(void) +{ + fcspi_slave_dma_rx_err_interrupt(FCSPI_5); +} + +static void fcspi_slave_dma_rx_finish_interrupt(FCSPI_InstanceType eInst) +{ + fcspi_slave_abort_transfer(eInst, FCSPI_TRUE); +} + +static void fcspi_0_slave_dma_rx_finish_interrupt(void) +{ + fcspi_slave_dma_rx_finish_interrupt(FCSPI_0); +} + +static void fcspi_1_slave_dma_rx_finish_interrupt(void) +{ + fcspi_slave_dma_rx_finish_interrupt(FCSPI_1); +} + +static void fcspi_2_slave_dma_rx_finish_interrupt(void) +{ + fcspi_slave_dma_rx_finish_interrupt(FCSPI_2); +} + +static void fcspi_3_slave_dma_rx_finish_interrupt(void) +{ + fcspi_slave_dma_rx_finish_interrupt(FCSPI_3); +} + +static void fcspi_4_slave_dma_rx_finish_interrupt(void) +{ + fcspi_slave_dma_rx_finish_interrupt(FCSPI_4); +} + +static void fcspi_5_slave_dma_rx_finish_interrupt(void) +{ + fcspi_slave_dma_rx_finish_interrupt(FCSPI_5); +} + +static void fcspi_slave_dma_tx_err_interrupt(FCSPI_InstanceType eInst) +{ + s_atFCSpiInfo[eInst].tFCSpiStat.eTransferStat = FCSPI_TRANSFER_TX_FAIL; + fcspi_slave_abort_transfer(eInst, FCSPI_TRUE); +} + +static void fcspi_0_slave_dma_tx_err_interrupt(void) +{ + fcspi_slave_dma_tx_err_interrupt(FCSPI_0); +} + +static void fcspi_1_slave_dma_tx_err_interrupt(void) +{ + fcspi_slave_dma_tx_err_interrupt(FCSPI_1); +} + +static void fcspi_2_slave_dma_tx_err_interrupt(void) +{ + fcspi_slave_dma_tx_err_interrupt(FCSPI_2); +} + +static void fcspi_3_slave_dma_tx_err_interrupt(void) +{ + fcspi_slave_dma_tx_err_interrupt(FCSPI_3); +} + +static void fcspi_4_slave_dma_tx_err_interrupt(void) +{ + fcspi_slave_dma_tx_err_interrupt(FCSPI_4); +} + +static void fcspi_5_slave_dma_tx_err_interrupt(void) +{ + fcspi_slave_dma_tx_err_interrupt(FCSPI_5); +} + +static void fcspi_slave_dma_tx_finish_interrupt(FCSPI_InstanceType eInst) +{ + fcspi_slave_abort_transfer(eInst, FCSPI_TRUE); +} + +static void fcspi_0_slave_dma_tx_finish_interrupt(void) +{ + fcspi_slave_dma_tx_finish_interrupt(FCSPI_0); +} + +static void fcspi_1_slave_dma_tx_finish_interrupt(void) +{ + fcspi_slave_dma_tx_finish_interrupt(FCSPI_1); +} + +static void fcspi_2_slave_dma_tx_finish_interrupt(void) +{ + fcspi_slave_dma_tx_finish_interrupt(FCSPI_2); +} + +static void fcspi_3_slave_dma_tx_finish_interrupt(void) +{ + fcspi_slave_dma_tx_finish_interrupt(FCSPI_3); +} + +static void fcspi_4_slave_dma_tx_finish_interrupt(void) +{ + fcspi_slave_dma_tx_finish_interrupt(FCSPI_4); +} + +static void fcspi_5_slave_dma_tx_finish_interrupt(void) +{ + fcspi_slave_dma_tx_finish_interrupt(FCSPI_5); +} + +static FCSPI_StatusType fcspi_slave_async_transfer_bytes(FCSPI_InstanceType eInst, + const uint8_t *pSendBuffer, uint8_t *pReceiveBuffer, uint16_t u16TransferByteCnt) +{ + DMA_InterruptCfgType tDmaTxInterruptCfg = {0}; + DMA_ChannelCfgType tDmaTxChnlCfg = {0}; + uint8_t u8DmaTxBlkByteCnt = (uint8_t)1; + DMA_InterruptCfgType tDmaRxInterruptCfg = {0}; + DMA_ChannelCfgType tDmaRxChnlCfg = {0}; + uint8_t u8DmaRxBlkByteCnt = (uint8_t)1; + FCSPI_StatusType eRet = FCSPI_STATUS_SUCCESS; + + if ((NULL == pSendBuffer) && (NULL == pReceiveBuffer)) + { + eRet = FCSPI_STATUS_ERROR; + } + else if ((uint16_t)0 == s_atFCSpiInfo[eInst].tFCSpiStat.u16BytesCntFrameNeed) + { + eRet = FCSPI_STATUS_ERROR; + } + else if ((uint16_t)0 == u16TransferByteCnt) + { + eRet = FCSPI_STATUS_NO_DATA; + } + else if ((uint16_t)0 != (u16TransferByteCnt % s_atFCSpiInfo[eInst].tFCSpiStat.u16BytesCntFrameNeed)) + { + eRet = FCSPI_STATUS_ERROR; + } + else if (FCSPI_TRUE == s_atFCSpiInfo[eInst].tFCSpiStat.eIsInTransfer) + { + eRet = FCSPI_STATUS_BUSY; + } + else + { + s_atFCSpiInfo[eInst].tFCSpiStat.eTransferStat = FCSPI_TRANSFER_OK; + FCSpi_Hw_Reset(eInst, FCSPI_TRUE, FCSPI_TRUE, FCSPI_FALSE); + FCSpi_Hw_Reset(eInst, FCSPI_TRUE, FCSPI_TRUE, FCSPI_FALSE); /* for shifter */ + + FCSpi_Hw_ClearSomeStatusW1CFlag(eInst, FCSPI_DRV_STATUS_REG_W1C_U32); + + /* in slave mode, rx and tx all enabled */ + FCSpi_Hw_EnableMoreInterrupts(eInst, FCSPI_INT_EN_TFUIE(1) | FCSPI_INT_EN_RFOIE(1)); + + s_atFCSpiInfo[eInst].tFCSpiStat.pbyTxBuff = pSendBuffer; + s_atFCSpiInfo[eInst].tFCSpiStat.pbyRxBuff = pReceiveBuffer; + s_atFCSpiInfo[eInst].tFCSpiStat.u16TxIndex = (uint16_t)0; + s_atFCSpiInfo[eInst].tFCSpiStat.u16RxIndex = (uint16_t)0; + + if (FCSPI_TRANSFER_TRIGGER_SRC_DMA_ISR == s_atFCSpiInfo[eInst].tFCSpiStat.eTransferTriggerSrc) + { + FCSPI_HWA_SetWatermark(s_atFCSpiInfo[eInst].tFCSpiInstance, (uint8_t)0, (uint8_t)3); + + /* TX */ + tDmaTxChnlCfg.u8ChannelPriority = s_atFCSpiInfo[eInst].tFCSpiStat.tTriggerDmaInf.u8TxDMAChannelPriority; + tDmaTxChnlCfg.bDestAddrLoopbackEn = false; + tDmaTxChnlCfg.bSrcAddrLoopbackEn = false; + tDmaTxChnlCfg.bAutoStop = true; /* auto stop dma after send finish */ + tDmaTxChnlCfg.bSrcCircularBufferEn = false; + tDmaTxChnlCfg.bDestCircularBufferEn = false; + + switch (s_atFCSpiInfo[eInst].tFCSpiStat.u16BytesCntFrameNeed) + { + case 1: + tDmaTxChnlCfg.eSrcDataSize = DMA_TRANSFER_SIZE_1B; + tDmaTxChnlCfg.eDestDataSize = DMA_TRANSFER_SIZE_1B; + tDmaTxChnlCfg.bSrcBlockOffsetEn = true; + tDmaTxChnlCfg.s32BlockOffset = (int32_t)1; + u8DmaTxBlkByteCnt = (uint8_t)1; + break; + + case 2: + tDmaTxChnlCfg.eSrcDataSize = DMA_TRANSFER_SIZE_2B; + tDmaTxChnlCfg.eDestDataSize = DMA_TRANSFER_SIZE_2B; + tDmaTxChnlCfg.bSrcBlockOffsetEn = true; + tDmaTxChnlCfg.s32BlockOffset = (int32_t)2; + u8DmaTxBlkByteCnt = (uint8_t)2; + break; + + default: + tDmaTxChnlCfg.eSrcDataSize = DMA_TRANSFER_SIZE_4B; + tDmaTxChnlCfg.eDestDataSize = DMA_TRANSFER_SIZE_4B; + tDmaTxChnlCfg.bSrcBlockOffsetEn = true; + tDmaTxChnlCfg.s32BlockOffset = (int32_t)4; + u8DmaTxBlkByteCnt = (uint8_t)4; + break; + } + + tDmaTxChnlCfg.u16BlockCount = u16TransferByteCnt / u8DmaTxBlkByteCnt; + tDmaTxChnlCfg.bDestBlockOffsetEn = false; + tDmaTxInterruptCfg.bTransferCompleteIntEn = true; + tDmaTxInterruptCfg.bTransferErrorIntEn = true; + switch (eInst) + { + case FCSPI_0: + tDmaTxChnlCfg.eTriggerSrc = DMA_REQ_FCSPI0_TX; + tDmaTxInterruptCfg.pTransferCompleteNotify = fcspi_0_slave_dma_tx_finish_interrupt; + tDmaTxInterruptCfg.pTransferErrorNotify = fcspi_0_slave_dma_tx_err_interrupt; + break; + + case FCSPI_1: + tDmaTxChnlCfg.eTriggerSrc = DMA_REQ_FCSPI1_TX; + tDmaTxInterruptCfg.pTransferCompleteNotify = fcspi_1_slave_dma_tx_finish_interrupt; + tDmaTxInterruptCfg.pTransferErrorNotify = fcspi_1_slave_dma_tx_err_interrupt; + break; + + case FCSPI_2: + tDmaTxChnlCfg.eTriggerSrc = DMA_REQ_FCSPI2_TX; + tDmaTxInterruptCfg.pTransferCompleteNotify = fcspi_2_slave_dma_tx_finish_interrupt; + tDmaTxInterruptCfg.pTransferErrorNotify = fcspi_2_slave_dma_tx_err_interrupt; + break; + + case FCSPI_3: + tDmaTxChnlCfg.eTriggerSrc = DMA_REQ_FCSPI3_TX; + tDmaTxInterruptCfg.pTransferCompleteNotify = fcspi_3_slave_dma_tx_finish_interrupt; + tDmaTxInterruptCfg.pTransferErrorNotify = fcspi_3_slave_dma_tx_err_interrupt; + break; + + case FCSPI_4: + tDmaTxChnlCfg.eTriggerSrc = DMA_REQ_FCSPI4_TX; + tDmaTxInterruptCfg.pTransferCompleteNotify = fcspi_4_slave_dma_tx_finish_interrupt; + tDmaTxInterruptCfg.pTransferErrorNotify = fcspi_4_slave_dma_tx_err_interrupt; + break; + + case FCSPI_5: + tDmaTxChnlCfg.eTriggerSrc = DMA_REQ_FCSPI5_TX; + tDmaTxInterruptCfg.pTransferCompleteNotify = fcspi_5_slave_dma_tx_finish_interrupt; + tDmaTxInterruptCfg.pTransferErrorNotify = fcspi_5_slave_dma_tx_err_interrupt; + break; + + default: + tDmaTxChnlCfg.eTriggerSrc = DMA_REQ_FCSPI3_TX; + tDmaTxInterruptCfg.pTransferCompleteNotify = fcspi_3_slave_dma_tx_finish_interrupt; + tDmaTxInterruptCfg.pTransferErrorNotify = fcspi_3_slave_dma_tx_err_interrupt; + break; + } + + tDmaTxChnlCfg.eDestIncMode = DMA_INCREMENT_DISABLE; + tDmaTxChnlCfg.eSrcIncMode = DMA_INCREMENT_DISABLE; + tDmaTxChnlCfg.pDestBuffer = FCSPI_HWA_GetTxDataAddr(s_atFCSpiInfo[eInst].tFCSpiInstance); + tDmaTxChnlCfg.u32BlockSize = (uint32_t)u8DmaTxBlkByteCnt; + + if (NULL != pSendBuffer) + { + s_atFCSpiInfo[eInst].tFCSpiStat.u16TxByteCntRemainToSend = u16TransferByteCnt; + tDmaTxChnlCfg.pSrcBuffer = pSendBuffer; + } + else + { + s_atFCSpiInfo[eInst].tFCSpiStat.u16TxByteCntRemainToSend = (uint16_t)0; + tDmaTxChnlCfg.bSrcBlockOffsetEn = false; /* if send buffer is NULL, just send dummy data, MUST fix the source to the dummy variable */ + tDmaTxChnlCfg.s32BlockOffset = (int32_t)0; + tDmaTxChnlCfg.pSrcBuffer = &(s_atFCSpiInfo[eInst].tFCSpiStat.u32DmaDummyData); + } + + DMA_InitChannel(s_atFCSpiInfo[eInst].tFCSpiStat.tTriggerDmaInf.eDMAInstance, + (DMA_ChannelType)s_atFCSpiInfo[eInst].tFCSpiStat.tTriggerDmaInf.u8TxDMAChannel, &tDmaTxChnlCfg); + + /* RX */ + tDmaRxChnlCfg.u8ChannelPriority = s_atFCSpiInfo[eInst].tFCSpiStat.tTriggerDmaInf.u8RxDMAChannelPriority; + tDmaRxChnlCfg.bDestAddrLoopbackEn = false; + tDmaRxChnlCfg.bSrcAddrLoopbackEn = false; + tDmaRxChnlCfg.bAutoStop = true; /* auto stop dma after send finish */ + tDmaRxChnlCfg.bSrcCircularBufferEn = false; + tDmaRxChnlCfg.bDestCircularBufferEn = false; + + switch (s_atFCSpiInfo[eInst].tFCSpiStat.u16BytesCntFrameNeed) + { + case 1: + tDmaRxChnlCfg.eDestDataSize = DMA_TRANSFER_SIZE_1B; + tDmaRxChnlCfg.eSrcDataSize = DMA_TRANSFER_SIZE_1B; + tDmaRxChnlCfg.bDestBlockOffsetEn = true; + tDmaRxChnlCfg.s32BlockOffset = (int32_t)1; + u8DmaRxBlkByteCnt = (uint8_t)1; + break; + + case 2: + tDmaRxChnlCfg.eDestDataSize = DMA_TRANSFER_SIZE_2B; + tDmaRxChnlCfg.eSrcDataSize = DMA_TRANSFER_SIZE_2B; + tDmaRxChnlCfg.bDestBlockOffsetEn = true; + tDmaRxChnlCfg.s32BlockOffset = (int32_t)2; + u8DmaRxBlkByteCnt = (uint8_t)2; + break; + + default: + tDmaRxChnlCfg.eDestDataSize = DMA_TRANSFER_SIZE_4B; + tDmaRxChnlCfg.eSrcDataSize = DMA_TRANSFER_SIZE_4B; + tDmaRxChnlCfg.bDestBlockOffsetEn = true; + tDmaRxChnlCfg.s32BlockOffset = (int32_t)4; + u8DmaRxBlkByteCnt = (uint8_t)4; + break; + } + + tDmaRxChnlCfg.u16BlockCount = u16TransferByteCnt / u8DmaRxBlkByteCnt; + tDmaRxChnlCfg.bSrcBlockOffsetEn = false; + tDmaRxInterruptCfg.bTransferCompleteIntEn = true; + tDmaRxInterruptCfg.bTransferErrorIntEn = true; + switch (eInst) + { + case FCSPI_0: + tDmaRxChnlCfg.eTriggerSrc = DMA_REQ_FCSPI0_RX; + tDmaRxInterruptCfg.pTransferCompleteNotify = fcspi_0_slave_dma_rx_finish_interrupt; + tDmaRxInterruptCfg.pTransferErrorNotify = fcspi_0_slave_dma_rx_err_interrupt; + break; + + case FCSPI_1: + tDmaRxChnlCfg.eTriggerSrc = DMA_REQ_FCSPI1_RX; + tDmaRxInterruptCfg.pTransferCompleteNotify = fcspi_1_slave_dma_rx_finish_interrupt; + tDmaRxInterruptCfg.pTransferErrorNotify = fcspi_1_slave_dma_rx_err_interrupt; + break; + + case FCSPI_2: + tDmaRxChnlCfg.eTriggerSrc = DMA_REQ_FCSPI2_RX; + tDmaRxInterruptCfg.pTransferCompleteNotify = fcspi_2_slave_dma_rx_finish_interrupt; + tDmaRxInterruptCfg.pTransferErrorNotify = fcspi_2_slave_dma_rx_err_interrupt; + break; + + case FCSPI_3: + tDmaRxChnlCfg.eTriggerSrc = DMA_REQ_FCSPI3_RX; + tDmaRxInterruptCfg.pTransferCompleteNotify = fcspi_3_slave_dma_rx_finish_interrupt; + tDmaRxInterruptCfg.pTransferErrorNotify = fcspi_3_slave_dma_rx_err_interrupt; + break; + + case FCSPI_4: + tDmaRxChnlCfg.eTriggerSrc = DMA_REQ_FCSPI4_RX; + tDmaRxInterruptCfg.pTransferCompleteNotify = fcspi_4_slave_dma_rx_finish_interrupt; + tDmaRxInterruptCfg.pTransferErrorNotify = fcspi_4_slave_dma_rx_err_interrupt; + break; + + case FCSPI_5: + tDmaRxChnlCfg.eTriggerSrc = DMA_REQ_FCSPI5_RX; + tDmaRxInterruptCfg.pTransferCompleteNotify = fcspi_5_slave_dma_rx_finish_interrupt; + tDmaRxInterruptCfg.pTransferErrorNotify = fcspi_5_slave_dma_rx_err_interrupt; + break; + + default: + tDmaRxChnlCfg.eTriggerSrc = DMA_REQ_FCSPI3_RX; + tDmaRxInterruptCfg.pTransferCompleteNotify = fcspi_3_slave_dma_rx_finish_interrupt; + tDmaRxInterruptCfg.pTransferErrorNotify = fcspi_3_slave_dma_rx_err_interrupt; + break; + } + + tDmaRxChnlCfg.eSrcIncMode = DMA_INCREMENT_DISABLE; + tDmaRxChnlCfg.eDestIncMode = DMA_INCREMENT_DISABLE; + tDmaRxChnlCfg.pSrcBuffer = FCSPI_HWA_GetRxDataAddr(s_atFCSpiInfo[eInst].tFCSpiInstance); + tDmaRxChnlCfg.u32BlockSize = (uint32_t)u8DmaRxBlkByteCnt; + + if (NULL != pReceiveBuffer) + { + s_atFCSpiInfo[eInst].tFCSpiStat.u16RxByteCntRemainToGet = u16TransferByteCnt; + tDmaRxChnlCfg.pDestBuffer = pReceiveBuffer; + } + else + { + s_atFCSpiInfo[eInst].tFCSpiStat.u16RxByteCntRemainToGet = (uint16_t)0; + tDmaRxChnlCfg.bDestBlockOffsetEn = false; + tDmaRxChnlCfg.s32BlockOffset = (int32_t)0; + tDmaRxChnlCfg.pDestBuffer = &(s_atFCSpiInfo[eInst].tFCSpiStat.u32DmaDummyData); + } + + DMA_InitChannel(s_atFCSpiInfo[eInst].tFCSpiStat.tTriggerDmaInf.eDMAInstance, + (DMA_ChannelType)s_atFCSpiInfo[eInst].tFCSpiStat.tTriggerDmaInf.u8RxDMAChannel, &tDmaRxChnlCfg); + + s_atFCSpiInfo[eInst].tFCSpiStat.eIsInTransfer = FCSPI_TRUE; + + DMA_InitChannelInterrupt(s_atFCSpiInfo[eInst].tFCSpiStat.tTriggerDmaInf.eDMAInstance, + (DMA_ChannelType)s_atFCSpiInfo[eInst].tFCSpiStat.tTriggerDmaInf.u8RxDMAChannel, &tDmaRxInterruptCfg); + DMA_InitChannelInterrupt(s_atFCSpiInfo[eInst].tFCSpiStat.tTriggerDmaInf.eDMAInstance, + (DMA_ChannelType)s_atFCSpiInfo[eInst].tFCSpiStat.tTriggerDmaInf.u8TxDMAChannel, &tDmaTxInterruptCfg); + DMA_StartChannel(s_atFCSpiInfo[eInst].tFCSpiStat.tTriggerDmaInf.eDMAInstance, + (DMA_ChannelType)s_atFCSpiInfo[eInst].tFCSpiStat.tTriggerDmaInf.u8RxDMAChannel); + DMA_StartChannel(s_atFCSpiInfo[eInst].tFCSpiStat.tTriggerDmaInf.eDMAInstance, + (DMA_ChannelType)s_atFCSpiInfo[eInst].tFCSpiStat.tTriggerDmaInf.u8TxDMAChannel); + FCSpi_Hw_SetRxTxDmaEnableStatus(eInst, FCSPI_TRUE, FCSPI_TRUE); + } + else + { + FCSPI_HWA_SetWatermark(s_atFCSpiInfo[eInst].tFCSpiInstance, (uint8_t)0, (uint8_t)2); + + if (NULL == s_atFCSpiInfo[eInst].tFCSpiStat.pbyTxBuff) + { + s_atFCSpiInfo[eInst].tFCSpiStat.u16TxByteCntRemainToSend = (uint16_t)0; + FCSPI_HWA_EnableTxDataMask(s_atFCSpiInfo[eInst].tFCSpiInstance, FCSPI_FALSE); + } + else + { + s_atFCSpiInfo[eInst].tFCSpiStat.u16TxByteCntRemainToSend = u16TransferByteCnt; + FCSPI_HWA_EnableTxDataMask(s_atFCSpiInfo[eInst].tFCSpiInstance, FCSPI_TRUE); + } + + if (NULL == s_atFCSpiInfo[eInst].tFCSpiStat.pbyRxBuff) + { + s_atFCSpiInfo[eInst].tFCSpiStat.u16RxByteCntRemainToGet = (uint16_t)0; + FCSPI_HWA_EnableRxDataMask(s_atFCSpiInfo[eInst].tFCSpiInstance, FCSPI_FALSE); + } + else + { + s_atFCSpiInfo[eInst].tFCSpiStat.u16RxByteCntRemainToGet = u16TransferByteCnt; + FCSPI_HWA_EnableRxDataMask(s_atFCSpiInfo[eInst].tFCSpiInstance, FCSPI_TRUE); + } + + s_atFCSpiInfo[eInst].tFCSpiStat.u16RxGetByteCntOfCurFrame = (uint16_t)0; + s_atFCSpiInfo[eInst].tFCSpiStat.u16TxSendByteCntOfCurFrame = (uint16_t)0; + s_atFCSpiInfo[eInst].tFCSpiStat.eIsPcsContinuous = FCSPI_FALSE; + s_atFCSpiInfo[eInst].tFCSpiStat.eIsInTransfer = FCSPI_TRUE; + + if (NULL != pReceiveBuffer) /* need rx fifo */ + { + FCSpi_Hw_EnableMoreInterrupts(eInst, FCSPI_INT_EN_RFIE(1)); + } + + if (NULL != pSendBuffer) + { + FCSpi_Hw_EnableMoreInterrupts(eInst, FCSPI_INT_EN_TFIE(1)); + } + } + } + + return eRet; +} + +static FCSPI_StatusType fcspi_slave_trigger( + FCSPI_InstanceType eInst, FCSPI_AtomicBoolType bIsInISR) +{ + uint32_t u32StatusRegValue; + uint16_t u16RemainTx = (uint16_t)0; + uint16_t u16RemainRx = (uint16_t)0; + FCSPI_StatusType eRet = FCSPI_STATUS_TRIGGER_OK; + + /* If an error is detected the transfer will be aborted */ + u32StatusRegValue = FCSPI_HWA_GetStatus(s_atFCSpiInfo[eInst].tFCSpiInstance); + if (FCSpi_Hw_ChkTxFifoUnderrun(u32StatusRegValue) && + (NULL != s_atFCSpiInfo[eInst].tFCSpiStat.pbyTxBuff)) + { + s_atFCSpiInfo[eInst].tFCSpiStat.eTransferStat = FCSPI_TRANSFER_TX_FAIL; + fcspi_slave_abort_transfer(eInst, bIsInISR); + eRet = FCSPI_STATUS_TRIGGER_ABORT_TX_FAIL; + } + else if (FCSpi_Hw_ChkRxFifoOverflow(u32StatusRegValue) && + (NULL != s_atFCSpiInfo[eInst].tFCSpiStat.pbyRxBuff)) + { + s_atFCSpiInfo[eInst].tFCSpiStat.eTransferStat = FCSPI_TRANSFER_RX_FAIL; + fcspi_slave_abort_transfer(eInst, bIsInISR); + eRet = FCSPI_STATUS_TRIGGER_ABORT_RX_FAIL; + } + /* rx data ready */ + else + { + if (FCSpi_Hw_ChkRxGreaterThanWater(u32StatusRegValue)) + { + if ((uint16_t)0 != s_atFCSpiInfo[eInst].tFCSpiStat.u16RxByteCntRemainToGet) + { + fcspi_read_rx_fifo(eInst); + } + } + + /* transmit some, need add more */ + if (FCSpi_Hw_ChkTxEqualOrLessThanWater(u32StatusRegValue)) + { + if ((uint16_t)0 != s_atFCSpiInfo[eInst].tFCSpiStat.u16TxByteCntRemainToSend) + { + fcspi_write_tx_fifo(eInst); + } + } + + if ((uint16_t)0 == s_atFCSpiInfo[eInst].tFCSpiStat.u16TxByteCntRemainToSend) + { + /* Disable TX flag. Software buffer is empty.*/ + FCSpi_Hw_DisableTransmitDataInterrupt(eInst); + } + + if ((uint16_t)0 == s_atFCSpiInfo[eInst].tFCSpiStat.u16RxByteCntRemainToGet) + { + FCSpi_Hw_DisableReceiveDataInterrupt(eInst); + } + + u16RemainTx = s_atFCSpiInfo[eInst].tFCSpiStat.u16TxByteCntRemainToSend; + u16RemainRx = s_atFCSpiInfo[eInst].tFCSpiStat.u16RxByteCntRemainToGet; + if (((uint16_t)0 == u16RemainTx) && ((uint16_t)0 == u16RemainRx)) + { + FCSpi_Hw_DisableSomeInterrupts(eInst, FCSPI_INT_EN_RFOIE(1) | FCSPI_INT_EN_TFUIE(1)); + + if (s_atFCSpiInfo[eInst].tFCSpiStat.pStopNotifyCb) + { + s_atFCSpiInfo[eInst].tFCSpiStat.pStopNotifyCb(eInst, bIsInISR); + } + + if (s_atFCSpiInfo[eInst].tFCSpiStat.u8WaitSemaphore) + { + s_atFCSpiInfo[eInst].tFCSpiStat.pSemaPostCb(eInst, bIsInISR); + s_atFCSpiInfo[eInst].tFCSpiStat.u8WaitSemaphore = (uint8_t)0; + } + + s_atFCSpiInfo[eInst].tFCSpiStat.eIsInTransfer = FCSPI_FALSE; + eRet = FCSPI_STATUS_TRIGGER_FINISH; + } + } + + return eRet; +} + +/*----------------------------------------------------------------------------*/ +/** + * @brief If it's in transfer, get its stat, or get the last transfer's stat. + * + * @param eInst Which FCSpi Hardware instance + * @param pCfg the transfer information, can be null + * @return FCSPI_StatusType FCSPI_STATUS_SUCCESS when the last transfer is finish successfully. Others, busy or error occur. + */ +FCSPI_StatusType FCSPI_GetLatestTransferStat(const FCSPI_InstanceType eInst, FCSPI_TransferRemainInfType *pCfg) +{ + FCSPI_StatusType eRet = FCSPI_STATUS_SUCCESS; + + if (NULL != pCfg) + { + pCfg->u32ByteCountReceiveRemained = s_atFCSpiInfo[eInst].tFCSpiStat.u16RxByteCntRemainToGet; + pCfg->u32ByteCountSendRemained = s_atFCSpiInfo[eInst].tFCSpiStat.u16TxByteCntRemainToSend; + } + + if (FCSPI_TRANSFER_OK != s_atFCSpiInfo[eInst].tFCSpiStat.eTransferStat) + { + eRet = FCSPI_STATUS_ERROR; + } + else if (FCSPI_TRUE == s_atFCSpiInfo[eInst].tFCSpiStat.eIsInTransfer) + { + eRet = FCSPI_STATUS_BUSY; + } + else + { + eRet = FCSPI_STATUS_SUCCESS; + } + + return eRet; +} + +#ifdef FCSPI_DRV_INTERNAL_FUNC_EN +/** + * @brief Trigger the driver to transfer data when select FCSPI_TRANSFER_TRIGGER_SRC_USER_POLL + * + * @param eInst Which FCSpi Hardware instance + * @return FCSPI_StatusType FCSPI_STATUS_TRIGGER_OK when api trigger successfully, FCSPI_STATUS_TRIGGER_FINISH when all data transfer finish. Others, error happen. + */ +FCSPI_StatusType FCSPI_PollTrigger(FCSPI_InstanceType eInst) +{ + FCSPI_StatusType eRet = FCSPI_STATUS_TRIGGER_OK; + + if (FCSPI_TRANSFER_TRIGGER_SRC_USER_POLL == s_atFCSpiInfo[eInst].tFCSpiStat.eTransferTriggerSrc) + { + if (FCSPI_TRUE == s_atFCSpiInfo[eInst].tFCSpiStat.eIsInTransfer) + { + if (FCSPI_MODE_MASTER == FCSPI_HWA_CheckMode(s_atFCSpiInfo[eInst].tFCSpiInstance)) + { + eRet = fcspi_master_trigger(eInst, FCSPI_FALSE); + } + else + { + eRet = fcspi_slave_trigger(eInst, FCSPI_FALSE); + } + } + else + { + eRet = FCSPI_STATUS_ERROR; + } + } + else + { + eRet = FCSPI_STATUS_ERROR; + } + + return eRet; +} +#endif + +/** + * @brief Select the trigger source(DMA with interrupt / interrupt / user poll) + * + * @param eInst Which FCSpi Hardware instance + * @param eSrc three source, 1) DMA move data between memory and registers, notified when finish by interrupt; 2) purely by interrupt; 3) purely by user poll. + * @return FCSPI_StatusType FCSPI_STATUS_SUCCESS when successfully. Others, error. + */ +FCSPI_StatusType FCSPI_SelectTriggerSrc( + FCSPI_InstanceType eInst, FCSPI_TriggerSrcType eSrc) +{ + FCSPI_StatusType eRet = FCSPI_STATUS_SUCCESS; + uint32_t u32StatRegVal = 0u; + + u32StatRegVal = FCSPI_HWA_GetStatus(s_atFCSpiInfo[eInst].tFCSpiInstance); + if ((FCSPI_TRUE != s_atFCSpiInfo[eInst].tFCSpiStat.eIsInTransfer) && + (!FCSpi_Hw_ChkBusy(u32StatRegVal))) + { + switch (eSrc) + { + case FCSPI_TRANSFER_TRIGGER_SRC_ISR: + s_atFCSpiInfo[eInst].tFCSpiStat.eTransferTriggerSrc = eSrc; + break; + case FCSPI_TRANSFER_TRIGGER_SRC_DMA_ISR: + s_atFCSpiInfo[eInst].tFCSpiStat.eTransferTriggerSrc = eSrc; + break; + case FCSPI_TRANSFER_TRIGGER_SRC_USER_POLL: + s_atFCSpiInfo[eInst].tFCSpiStat.eTransferTriggerSrc = eSrc; + break; + default: + s_atFCSpiInfo[eInst].tFCSpiStat.eTransferTriggerSrc = eSrc; + break; + } + } + else + { + eRet = FCSPI_STATUS_BUSY; + } + + return eRet; +} + +/** + * @brief Abort current transfer if exist, or just recovery the hardware. + * + * @param eInst Which FCSpi Hardware instance + */ +void FCSPI_AbortTransfer(const FCSPI_InstanceType eInst) +{ + s_atFCSpiInfo[eInst].tFCSpiStat.eTransferStat = FCSPI_TRANSFER_ABORT; + + if (FCSPI_MODE_MASTER == FCSPI_HWA_CheckMode(s_atFCSpiInfo[eInst].tFCSpiInstance)) + { + fcspi_master_abort_transfer(eInst, FCSPI_FALSE); + } + else + { + fcspi_slave_abort_transfer(eInst, FCSPI_FALSE); + } +} + +static void fcspi_irq_handler(FCSPI_InstanceType eInst) +{ + if (FCSPI_MODE_MASTER == FCSPI_HWA_CheckMode(s_atFCSpiInfo[eInst].tFCSpiInstance)) + { + fcspi_master_trigger(eInst, FCSPI_TRUE); + } + else + { + fcspi_slave_trigger(eInst, FCSPI_TRUE); + } +} + +/** + * @brief fcspi 0 interrupt handler + * + * @note This function should be called as/in FCSPI 0 interrupt handler + */ +void FCSPI0_IRQHandler(void) +{ + fcspi_irq_handler(FCSPI_0); +} + +/** + * @brief fcspi 1 interrupt handler + * + * @note This function should be called as/in FCSPI 1 interrupt handler + */ +void FCSPI1_IRQHandler(void) +{ + fcspi_irq_handler(FCSPI_1); +} + +/** + * @brief fcspi 2 interrupt handler + * + * @note This function should be called as/in FCSPI 2 interrupt handler + */ +void FCSPI2_IRQHandler(void) +{ + fcspi_irq_handler(FCSPI_2); +} + +/** + * @brief fcspi 3 interrupt handler + * + * @note This function should be called as/in FCSPI 3 interrupt handler + */ +void FCSPI3_IRQHandler(void) +{ + fcspi_irq_handler(FCSPI_3); +} + +/** + * @brief fcspi 4 interrupt handler + * + * @note This function should be called as/in FCSPI 4 interrupt handler + */ +void FCSPI4_IRQHandler(void) +{ + fcspi_irq_handler(FCSPI_4); +} + +/** + * @brief fcspi 5 interrupt handler + * + * @note This function should be called as/in FCSPI 5 interrupt handler + */ +void FCSPI5_IRQHandler(void) +{ + fcspi_irq_handler(FCSPI_5); +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_fcuart.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_fcuart.c new file mode 100644 index 0000000..a74d1cd --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_fcuart.c @@ -0,0 +1,1768 @@ +/** + * @file fc7xxx_driver_fcuart.c + * @author Flagchip + * @brief FC7xxx FCUart driver type definition and API + * @version 0.1.0 + * @date 2024-01-14 + * + * @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. + * + */ + +/******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-14 Flagchip0122 N/A FC7xxx internal release version + ********************************************************************************/ + +#include "fc7xxx_driver_fcuart.h" + + + + +/********* Macro ************/ + +/********* Local typedef ************/ + +typedef enum { + UART_PRINT_RADIX_BIN = 2U, + UART_PRINT_RADIX_OCT = 8U, + UART_PRINT_RADIX_DEC = 10U, + UART_PRINT_RADIX_HEX = 16U +} UART_PrintIntType; + +/** + * @brief FCUART Operation Sequence + * + */ +typedef enum { + FCUART_SEQUENCE_VAR_NOINIT, /**< FCUART_SEQUENCE_DEINIT means fcuart variables data is not initialed */ + FCUART_SEQUENCE_DEINIT, /**< FCUART_SEQUENCE_DEINIT means fcuart driver is not initialed */ + FCUART_SEQUENCE_NOTSTART_RECEIVE, /**< FCUART_SEQUENCE_NOTSTART_RECEIVE means fcuart driver initialed and write/erase is allowed */ + FCUART_SEQUENCE_START_RECEIVE /**< FCUART_SEQUENCE_START_RECEIVE means fcuart driver started received */ +} FCUART_SequenceType; + +/********* Local Variables ************/ +/* UART instance array */ +static FCUART_Type *const s_aFCUART_InstanceTable[FCUART_INSTANCE_COUNT] = FCUART_BASE_PTRS; + +/* sequence table */ +static FCUART_SequenceType s_aCurrentSequence[FCUART_INSTANCE_COUNT] = {FCUART_SEQUENCE_VAR_NOINIT}; + +/* error notify callback function point */ +static FCUART_ErrorInterrupt_CallBackType s_aFCUART_ErrorNotifyTable[FCUART_INSTANCE_COUNT]; + +/* receive notify callback function point */ +static FCUART_TxRxInterrupt_CallBackType s_aFCUART_RxNotifyTable[FCUART_INSTANCE_COUNT]; + +/* Transfer empty notify callback function point */ +static FCUART_TxRxInterrupt_CallBackType s_aFCUART_TxEmptyNotifyTable[FCUART_INSTANCE_COUNT]; + +/* Transfer complete notify callback function point */ +static FCUART_TxRxInterrupt_CallBackType s_aFCUART_TxCompleteNotifyTable[FCUART_INSTANCE_COUNT]; + +/* Idle notify callback function point */ +static FCUART_IdleInterrupt_CallBackType s_aFCUART_IdleNotifyTable[FCUART_INSTANCE_COUNT]; + +/* check every pUart instance whether is used */ +static uint8_t s_aFCUART_UartUsed[FCUART_INSTANCE_COUNT]; + +/* check every pUart instance transmit timeout */ +static uint32_t s_aFCUART_TransmitTimeout[FCUART_INSTANCE_COUNT]; + +/* pUart instance receive buffer */ +static FCUART_DataType *s_aFCUART_RxMsg[FCUART_INSTANCE_COUNT]; + +/* pUart instance transfer buffer */ +static FCUART_DataType *s_aFCUART_TxMsg[FCUART_INSTANCE_COUNT]; + +/********* Local Prototype Functions ************/ + +static FCUART_ErrorType FCUART_LL_CheckInstance(uint8_t u8UartIndex); + +static uint32_t FCUART_LL_Error(uint8_t u8UartIndex); + +static FCUART_ErrorType FCUART_LL_ProcessBaud(uint32_t u32Smb, uint32_t *u32OverSamp, uint32_t *u32Sbr); + +static FCUART_ErrorType FCUART_LL_Transmit_Char(FCUART_Type *pUart, uint8_t u8Data, uint32_t u32TimeoutTick); + +static FCUART_ErrorType FCUART_LL_Receive(uint8_t u8UartIndex, FCUART_DataType *pUartData); + +static FCUART_ErrorType FCUART_LL_Transmit_Empty(uint8_t u8UartIndex, FCUART_DataType *pUartData); + +static FCUART_ErrorType FCUART_LL_Transmit_Complete(uint8_t u8UartIndex); + +static FCUART_ErrorType FCUART_LL_Idle(uint8_t u8UartIndex); + +static uint8_t FCUART_Float2Char(double Value, char *pOutStr, uint32_t u32Eps); + +static uint8_t FCUART_Int2Char(int i32Value, char *pOutStr, UART_PrintIntType eRadix, bool bHexUpper); + +/********* Global Prototype Functions ************/ + +/********* Local Functions ************/ +/** + * @brief Check UART instance + * + * @param u8UartIndex UART instance number + * @return + */ +static FCUART_ErrorType FCUART_LL_CheckInstance(uint8_t u8UartIndex) { + FCUART_ErrorType tRetVal; + + if (u8UartIndex < FCUART_INSTANCE_COUNT) { + tRetVal = (FCUART_ErrorType) FCUART_ERROR_OK; + } else { + tRetVal = (FCUART_ErrorType) FCUART_ERROR_INVALID_PARAM; + } + + return tRetVal; +} + +/** + * @brief Process get OverSamp and SBR + * + * @param u32Smb the value OverSame*SBR + * @param u32OverSamp out OverSampe + * @param u32Sbr out + * @return FCUART_ERROR_OK is ok, others are not ok + */ +static FCUART_ErrorType FCUART_LL_ProcessBaud(uint32_t u32Smb, uint32_t *u32OverSamp, uint32_t *u32Sbr) { + FCUART_ErrorType tRetVal; + uint32_t u32SbrTemp; + uint32_t u32OverSampTemp; + uint32_t u32TempSmbDiff; + uint32_t u32SmbDiff; + uint32_t u32CalcSmb; + uint32_t u32OverSamp1; + uint32_t u32Sbr1; + uint32_t u32OriginDiff; + + u32OverSamp1 = 4U; /* 4..32 */ + + /* sbr = smb / oversamp */ + u32Sbr1 = (uint16_t) (u32Smb / (u32OverSamp1)); + u32CalcSmb = (u32OverSamp1) * (u32Sbr1); + + if (u32CalcSmb > u32Smb) { + u32SmbDiff = u32CalcSmb - u32Smb; + } else { + u32SmbDiff = u32Smb - u32CalcSmb; + } + u32OriginDiff = u32SmbDiff; + + if (u32SmbDiff != 0U) { + + /* loop to find the best u32OverSamp1 value possible, one that generates minimum u32SmbDiff + * iterate through the rest of the supported values of u32OverSamp */ + for (u32OverSampTemp = 5U; u32OverSampTemp <= 32U; u32OverSampTemp++) { + /* calculate the temporary u32Sbr value */ + u32SbrTemp = (uint32_t) (u32Smb / u32OverSampTemp); + /* calculate the baud rate based on the temporary u32OverSamp and u32Sbr values */ + u32CalcSmb = (uint32_t) (u32OverSampTemp * u32SbrTemp); + + if (u32CalcSmb > u32Smb) { + u32TempSmbDiff = u32CalcSmb - u32Smb; + } else { + u32TempSmbDiff = u32Smb - u32CalcSmb; + } + + if (u32TempSmbDiff < u32SmbDiff) { + u32SmbDiff = u32TempSmbDiff; + u32OverSamp1 = u32OverSampTemp; /* update and store the best u32OverSamp value calculated */ + u32Sbr1 = u32SbrTemp; /* update store the best u32Sbr value calculated */ + } + + /* when differ is 0U, break */ + if (u32SmbDiff == 0U) { + break; + } + } + } + + /* check differ */ + if (u32SmbDiff <= u32OriginDiff) { + tRetVal = (FCUART_ErrorType) FCUART_ERROR_OK; + + /* out the calculated value */ + *u32Sbr = u32Sbr1; + *u32OverSamp = u32OverSamp1; + } else { + tRetVal = (FCUART_ErrorType) FCUART_ERROR_FAILED; + } + + return tRetVal; +} + +/** + * @brief Function to Transmit single Char + * + * @param pUart UART Instance point + * @param u8Data UART data + * @return FCUART_ERROR_OK is ok, others are not ok + */ +static FCUART_ErrorType FCUART_LL_Transmit_Char(FCUART_Type *pUart, uint8_t u8Data, uint32_t u32TimeoutTick) { + uint32_t u32Result; + uint32_t u32TryCount; + + /* check transmit ready flag */ + u32Result = FCUART_HWA_GetStatus(pUart, FCUART_STAT_TDREF); + + if (u32Result != 0U) { + FCUART_HWA_SetData(pUart, (uint32_t) u8Data); /* Send data */ + FCUART_HWA_SetTxTransfer(pUart, true); /* start transmit */ + + u32Result = 0U; + u32TryCount = 0U; + + while ((u32Result == 0U) && (u32TryCount < u32TimeoutTick)) { + /* check transmit flag */ + u32Result = FCUART_HWA_GetStatus(pUart, FCUART_STAT_TCF); + u32TryCount++; + } + + /* after transmit completed, close TE */ + FCUART_HWA_SetTxTransfer(pUart, false); + } + + return (u32Result == 0U) ? (FCUART_ErrorType) FCUART_ERROR_FAILED : (FCUART_ErrorType) FCUART_ERROR_OK; +} + +/** + * @brief Function to Transmit single Char by interrupt + * + * @param u8UartIndex UART Instance + * @param pUartData UART receive buffer + * @return FCUART_ERROR_OK is ok, others are not ok + */ +static FCUART_ErrorType FCUART_LL_Transmit_Empty(uint8_t u8UartIndex, FCUART_DataType *pUartData) { + FCUART_ErrorType tRetVal = (FCUART_ErrorType) FCUART_ERROR_INVALID_PARAM; + FCUART_Type *pUart; + uint32_t u32TempStats; + uint32_t u32Index; + uint8_t u8Index; + uint8_t u8TxWaterMark; + + pUart = (FCUART_Type *) s_aFCUART_InstanceTable[u8UartIndex]; + if ((pUartData != NULL) && (pUartData->pDatas != NULL)) { + /* get and clear receive flag */ + u32TempStats = FCUART_HWA_GetStatus(pUart, FCUART_STAT_TDREF); + if (u32TempStats > 0U) { + /* TDRFF Flag has been got */ + tRetVal = (FCUART_ErrorType) FCUART_ERROR_OK; + if (pUartData->u32DataLen > 0U) { + if (true == FCUART_HWA_GetEnStatusTxFifo(pUart)) { + /* Tx fifo enable */ + u8TxWaterMark = FCUART_HWA_GetTxWaterMark(pUart); + + if (((pUartData->u32DataLen) >= (uint32_t) (FCUART_FIFO_DEPTH - u8TxWaterMark))) { + for (u8Index = 0U; u8Index < (FCUART_FIFO_DEPTH - u8TxWaterMark); u8Index++) { + FCUART_HWA_SetData(pUart, (uint8_t) (pUartData->pDatas[0U])); /* Send data */ + + /* Update pointer position */ + (pUartData->pDatas)++; + (pUartData->u32DataLen)--; + } + } else { + for (u32Index = 0U; u32Index < (pUartData->u32DataLen); u32Index++) { + FCUART_HWA_SetData(pUart, (uint8_t) (pUartData->pDatas[0U])); /* Send data */ + + /* Update pointer position */ + (pUartData->pDatas)++; + (pUartData->u32DataLen)--; + } + } + } else { + /* Tx fifo disable */ + FCUART_HWA_SetData(pUart, (uint8_t) (pUartData->pDatas[0U])); /* Send data */ + + /* Update pointer position */ + (pUartData->pDatas)++; + (pUartData->u32DataLen)--; + } + + if (0U == pUartData->u32DataLen) { + /* There's no new data, disable transmit empty interrupt and enable transmit complete interrupt */ + FCUART_HWA_DisableInterrupt(pUart, (uint32_t) FCUART_INT_CTRL_TIE); + FCUART_HWA_EnableInterrupt(pUart, (uint32_t) FCUART_INT_CTRL_TCIE); + } + } + } + } + + return tRetVal; +} + +/** + * @brief Function to deal transmit complete + * + * @param u8UartIndex UART Instance + * @return FCUART_ERROR_OK is ok, others are not ok + */ +static FCUART_ErrorType FCUART_LL_Transmit_Complete(uint8_t u8UartIndex) { + FCUART_ErrorType tRetVal = (FCUART_ErrorType) FCUART_ERROR_INVALID_PARAM; + FCUART_Type *pUart; + uint32_t u32TempStats; + + /* No need to check instance */ + pUart = (FCUART_Type *) s_aFCUART_InstanceTable[u8UartIndex]; + /* get and clear receive flag */ + u32TempStats = FCUART_HWA_GetStatus(pUart, FCUART_STAT_TCF); + + if (u32TempStats > 0U) { + /* TCF Flag has been got */ + tRetVal = (FCUART_ErrorType) FCUART_ERROR_OK; + + FCUART_HWA_DisableInterrupt(pUart, (uint32_t) (FCUART_INT_CTRL_TE | FCUART_INT_CTRL_TCIE)); + } + return tRetVal; +} + +/** + * @brief Function to deal idle line + * + * @param u8UartIndex UART Instance + * @return FCUART_ERROR_OK is ok, others are not ok + */ +static FCUART_ErrorType FCUART_LL_Idle(uint8_t u8UartIndex) { + FCUART_ErrorType tRetVal = (FCUART_ErrorType) FCUART_ERROR_INVALID_PARAM; + FCUART_Type *pUart; + uint32_t u32TempStats; + + /* get and clear receive flag */ + pUart = (FCUART_Type *) s_aFCUART_InstanceTable[u8UartIndex]; + /* No need to check instance */ + u32TempStats = FCUART_HWA_GetStatus(pUart, FCUART_STAT_IDLEF); + + if (u32TempStats > 0U) { + /* IDLF Flag has been got */ + tRetVal = (FCUART_ErrorType) FCUART_ERROR_OK; + FCUART_HWA_ClearStatus(pUart, (uint32_t) FCUART_STAT_IDLEF); + } + return tRetVal; +} + +/** + * @brief Receive UART data + * + * @param u8UartIndex UART Instance + * @param pUartData UART receive buffer + * @return FCUART_ERROR_OK is ok, others are not ok + */ +static FCUART_ErrorType FCUART_LL_Receive(uint8_t u8UartIndex, FCUART_DataType *pUartData) { + FCUART_ErrorType tRetVal = (FCUART_ErrorType) FCUART_ERROR_INVALID_PARAM; + FCUART_Type *pUart; + uint8_t u8ReadData; + uint32_t u32TempStats; + uint8_t u8RxCount; + uint8_t u8Index; + + pUart = (FCUART_Type *) s_aFCUART_InstanceTable[u8UartIndex]; + + if ((pUartData != NULL) && (pUartData->pDatas != NULL)) { + /* get and clear receive flag */ + u32TempStats = FCUART_HWA_GetStatus(pUart, FCUART_STAT_RDRFF); + + if (u32TempStats > 0U) { + /* RDRFF Flag has been got */ + tRetVal = (FCUART_ErrorType) FCUART_ERROR_OK; + + pUartData->u32DataLen = 0U; + if (true == FCUART_HWA_GetEnStatusRxFifo(pUart)) { + /* Rx fifo enable */ + u8RxCount = FCUART_HWA_GetFifoRxCount(pUart); + for (u8Index = 0U; u8Index < u8RxCount; u8Index++) { + u8ReadData = FCUART_HWA_GetData(pUart); + pUartData->pDatas[u8Index] = u8ReadData; + pUartData->u32DataLen++; + } + } else { + /* Rx fifo disable */ + u8ReadData = FCUART_HWA_GetData(pUart); + pUartData->pDatas[0U] = u8ReadData; + pUartData->u32DataLen++; + } + } + } + + return tRetVal; +} + +/** + * @brief Get Error Status + * + * @param u8UartIndex + * @return All Error Combine, 0U is no error + */ +static uint32_t FCUART_LL_Error(uint8_t u8UartIndex) { + uint32_t u32RetVal; + uint32_t u32ErrorValue; + FCUART_Type *pUart; + + u32ErrorValue = 0U; + + pUart = (FCUART_Type *) s_aFCUART_InstanceTable[u8UartIndex]; + + /* receive overrun */ + u32RetVal = FCUART_HWA_GetStatus(pUart, FCUART_STAT_RORF); + + /* FCUART_HWA_ClearStatus(pUart, FCUART_STAT_RORF); */ + if (u32RetVal != 0U) { + u32ErrorValue = (uint32_t) FCUART_ERROR_RORF; + } + + /* noise flag */ + u32RetVal = FCUART_HWA_GetStatus(pUart, FCUART_STAT_NF); + + /*FCUART_HWA_ClearStatus(pUart, FCUART_STAT_NF);*/ + if (u32RetVal != 0U) { + u32ErrorValue |= (uint32_t) FCUART_ERROR_NF; + } + + /* Frame Error flag */ + u32RetVal = FCUART_HWA_GetStatus(pUart, FCUART_STAT_FEF); + + /*FCUART_HWA_ClearStatus(pUart, FCUART_STAT_FEF);*/ + if (u32RetVal != 0U) { + u32ErrorValue |= (uint32_t) FCUART_ERROR_FEF; + } + + /* Parity Error Flag */ + u32RetVal = FCUART_HWA_GetStatus(pUart, FCUART_STAT_PEF); + + /*FCUART_HWA_ClearStatus(pUart, FCUART_STAT_PEF);*/ + if (u32RetVal != 0U) { + u32ErrorValue |= (uint32_t) FCUART_ERROR_PEF; + } + + /* Receive Data Parity Error Flag */ + u32RetVal = FCUART_HWA_GetStatus(pUart, FCUART_STAT_RPEF); + + /*FCUART_HWA_ClearStatus(pUart, FCUART_STAT_RPEF);*/ + if (u32RetVal != 0U) { + u32ErrorValue |= (uint32_t) FCUART_ERROR_RPEF; + } + + /* Transmit Data Parity Error Flag */ + u32RetVal = FCUART_HWA_GetStatus(pUart, FCUART_STAT_TPEF); + + /*FCUART_HWA_ClearStatus(pUart, FCUART_STAT_TPEF);*/ + if (u32RetVal != 0U) { + u32ErrorValue |= (uint32_t) FCUART_ERROR_TPEF; + } + + /* clear error flags */ + FCUART_HWA_ClearStatus(pUart, u32ErrorValue); + + return u32ErrorValue; +} + +/********************* Global Functions *********************/ + +/** + * @brief Initial UART variables Memory + * + */ +void FCUART_InitMemory(uint8_t u8UartIndex) { + + s_aFCUART_ErrorNotifyTable[u8UartIndex] = NULL; + + s_aFCUART_RxNotifyTable[u8UartIndex] = NULL; + + s_aFCUART_TxEmptyNotifyTable[u8UartIndex] = NULL; + + s_aFCUART_TxCompleteNotifyTable[u8UartIndex] = NULL; + + s_aFCUART_IdleNotifyTable[u8UartIndex] = NULL; + + s_aFCUART_UartUsed[u8UartIndex] = 0U; + + /* set first state */ + s_aCurrentSequence[u8UartIndex] = FCUART_SEQUENCE_DEINIT; + +} + +/** + * @brief This Function is used to initial UART instance + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @param pInitCfg contains clock, baud-rate, Bit Mode, parity and so on. + * @return FCUART_ERROR_OK is ok, others are not ok + */ +FCUART_ErrorType FCUART_Init(uint8_t u8UartIndex, FCUART_InitType *pInitCfg) { + FCUART_ErrorType tRetVal; + uint32_t u32TempBaudReg; + uint32_t u32TempCtrlReg; + uint32_t u32TempFifoReg; + uint32_t u32TempWatermarkReg; + uint32_t u32TempStat; + uint32_t u32TempModir; + FCUART_Type *pUart; + uint32_t u32Sbr = 0U; + uint32_t u32OverSamp = 0U; + uint32_t u32Smb = 0U; + + /* check parameter */ + tRetVal = FCUART_LL_CheckInstance(u8UartIndex); + + if ((tRetVal == (FCUART_ErrorType) FCUART_ERROR_OK) && + (s_aCurrentSequence[u8UartIndex] == FCUART_SEQUENCE_DEINIT)) { + + tRetVal = (FCUART_ErrorType) FCUART_ERROR_OK; + } else { + tRetVal |= (FCUART_ErrorType) FCUART_ERROR_INVALID_SEQUENCE; + } + + if (pInitCfg != NULL) { + if (tRetVal == (FCUART_ErrorType) FCUART_ERROR_OK) { + + /* set not start state */ + s_aCurrentSequence[u8UartIndex] = FCUART_SEQUENCE_NOTSTART_RECEIVE; + + if (0U != pInitCfg->u32Baudrate) { + u32Smb = pInitCfg->u32ClkSrcHz / pInitCfg->u32Baudrate; + } else { + u32Smb = 0; + tRetVal = (FCUART_ErrorType) FCUART_ERROR_INVALID_PARAM; + } + + pUart = (FCUART_Type *) s_aFCUART_InstanceTable[u8UartIndex]; + + /* process for baud-rate */ + if ((FCUART_ErrorType) FCUART_ERROR_OK == FCUART_LL_ProcessBaud(u32Smb, &u32OverSamp, &u32Sbr)) { + /* temporary BAUD register */ + u32TempBaudReg = (uint32_t) 0U | + /* initial value */ + FCUART_BAUD_MAEN0(0U) | + /* Match mode enable 0 */ + FCUART_BAUD_MAEN1(0U) | + /* Match mode enable 1 */ + FCUART_BAUD_10BIT_MODE(0U) | + /* 10bit mode select */ + FCUART_BAUD_OVR_SAMP(u32OverSamp - 1U) | + /* Over sampling Ratio, n+1 */ + FCUART_BAUD_TDMAEN(pInitCfg->bEnTxEmptyDma) | + /* Transmitter DMA Enable */ + FCUART_BAUD_RDMAEN(pInitCfg->bEnRxFullDma) | + /* Receiver Full DMA Enable */ + FCUART_BAUD_RIDMAEN(0U) | + /* Receiver Idle DMA Enable */ + FCUART_BAUD_MATCH_CFG(0U) | + /* Match Configuration */ + FCUART_BAUD_BEDGE_SAMP(1U) | + /* Both Edge Sampling */ + FCUART_BAUD_RESYNC_DIS(0U) | + /* Re-synchronization Disable */ + FCUART_BAUD_LBKDIE(0U) | + /* LIN Break Detect Interrupt Enable */ + FCUART_BAUD_RIAEIE(0U) | + /* RX Input Active Edge Interrupt Enable */ + FCUART_BAUD_SBNS(pInitCfg->eStopBit) | + /* Stop Bit Number Select */ + FCUART_BAUD_SBR( + u32Sbr); /* Baud Rate Modulo Divisor. baud-rate = baud clock / ((OVR_SAMP+1) * SBR) */ + + /* temporary CTRL register */ + u32TempCtrlReg = (uint32_t) 0U |/* initial value */ + FCUART_CTRL_R8T9(0U) | + /* Receive Bit 8 / Transmit Bit 9 */ + FCUART_CTRL_R9T8(0U) | + /* Receive Bit 9 / Transmit Bit 8 */ + FCUART_CTRL_TXDIR(0U) | + /* TXD Pin Direction in Single-Wire Mode */ + FCUART_CTRL_TXINV(0U) | + /* Transmit Data Inversion */ + FCUART_CTRL_ORIE(0U) | + /* Overrun Interrupt Enable */ + FCUART_CTRL_NEIE(0U) | + /* Noise Error Interrupt Enable */ + FCUART_CTRL_FEIE(0U) | + /* Frame Error Interrupt Enable */ + FCUART_CTRL_PEIE(0U) | + /* Parity Error Interrupt Enable */ + FCUART_CTRL_TIE(0U) | + /* Transmit Interrupt Enable */ + FCUART_CTRL_TCIE(0U) | + /* Transmission Complete Interrupt Enable */ + FCUART_CTRL_RIE(0U) | + /* Receiver Interrupt Enable */ + FCUART_CTRL_IIE(0U) | + /* Idle Line Interrupt Enable */ + FCUART_CTRL_TE(0U) | + /* Transmitter Enable */ + FCUART_CTRL_RE(0U) | + /* Receiver Enable */ + FCUART_CTRL_RWC(0U) | + /* Receiver WakeUp Control */ + FCUART_CTRL_SBK(0U) | + /* Send Break */ + FCUART_CTRL_M0IE(0U) | + /* Match address 0 Interrupt Enable */ + FCUART_CTRL_M1IE(0U) | + /* Match address 1 Interrupt Enable */ + FCUART_CTRL_7BMS(0U) | + /* 7-Bit Mode Select */ + FCUART_CTRL_IDLECFG(pInitCfg->eIdleCharNum) | + /* Idle Configuration 2^n bytes time no data entry IDLE */ + FCUART_CTRL_LOOPMS(0U) | + /* Loop Mode Select */ + FCUART_CTRL_WAITEN(0U) | + /* WAIT Enable */ + FCUART_CTRL_RXSRC(0U) | + /* Receiver Source Select */ + FCUART_CTRL_BMSEL(pInitCfg->eBitMode) | + /* 9-Bit or 8-Bit Mode Select */ + FCUART_CTRL_RSWMS(0U) | + /* Receiver WakeUp Method Select */ + FCUART_CTRL_ITS(pInitCfg->eIdleStart) | + /* Idle Line Type Select */ + FCUART_CTRL_PE(pInitCfg->bParityEnable) | + /* Parity Enable */ + FCUART_CTRL_PT( + pInitCfg->eParityType); /* Parity Type */ + + /* temporary FIFO register */ + u32TempFifoReg = + (uint32_t) 0U | /* initial value */ + FCUART_FIFO_TXEMPTY(0U) | /* Transmit Buffer/FIFO Empty */ + FCUART_FIFO_RXEMPTY(0U) | /* Receive Buffer/FIFO Empty */ + FCUART_FIFO_TXOF(0U) | /* Transmitter Buffer Overflow Flag */ + FCUART_FIFO_RXUF(0U) | /* Receiver Buffer Underflow Flag */ + FCUART_FIFO_TXFLUSH(1U) | /* Transmit FIFO/Buffer Flush */ + FCUART_FIFO_RXFLUSH(1U) | /* Receive FIFO/Buffer Flush */ + FCUART_FIFO_RXIDEN(pInitCfg->eFifoRxIdleCharNum) | + /* Receiver Idle Empty Enable */ + FCUART_FIFO_TXOFIE(0U) | /* Transmit FIFO Overflow Interrupt Enable */ + FCUART_FIFO_RXUFIE(0U) | /* Receive FIFO Underflow Interrupt Enable */ + FCUART_FIFO_TXFEN(pInitCfg->bEnTxFifo) | /* Transmit FIFO Enable */ + FCUART_FIFO_TXFIFODEP(1U) | /* Transmit FIFO Buffer Depth */ + FCUART_FIFO_RXFEN(pInitCfg->bEnRxFifo) | /* Receive FIFO Enable, enable RX FIFO */ + FCUART_FIFO_RXFIFODEP(1U); /* Receive FIFO Buffer Depth */ + + /* temporary WATERMARK register */ + u32TempWatermarkReg = (uint32_t) 0U |/* initial value */ + FCUART_WATERMARK_RXCOUNT(0U) | + /* Receive Counter */ + FCUART_WATERMARK_RXWATER(pInitCfg->u8RxFifoWaterMark) | + /* Receive WaterMark, receive n-1 request interrupt or DMA */ + FCUART_WATERMARK_TXCOUNT(0U) | + /* Transmit Counter */ + FCUART_WATERMARK_TXWATER( + pInitCfg->u8TxFifoWaterMark); /* Transmit WaterMark */ + + /* temporary MODIR register */ + u32TempModir = (uint32_t) 0U | /* initial value */ + FCUART_MODIR_RXRTSCFG(0U) | + /* Receive RTS Configuration */ + FCUART_MODIR_TXCTSSRC(0U) | + /* Transmit CTS Source */ + FCUART_MODIR_TXCTSCFG(0U) | + /* Transmit CTS Configuration */ + FCUART_MODIR_RXRTSEN(0U) | /* Receiver Request-to-Send Enable */ + FCUART_MODIR_TXRTSPOL(0U) | + /* Transmitter Request-to-Send Polarity */ + FCUART_MODIR_TXRTSEN(0U) | /* Transmitter Request-to-Send Enable */ + FCUART_MODIR_TXCTSEN( + 0U); /* Transmitter Clear-to-Send Enable */ + + /* write register with temporary data */ + FCUART_HWA_SetBaud(pUart, u32TempBaudReg); /* 0x19000008; */ + FCUART_HWA_SetFifo(pUart, u32TempFifoReg); + FCUART_HWA_SetWaterMark(pUart, u32TempWatermarkReg); + FCUART_HWA_SetModir(pUart, u32TempModir); + + FCUART_HWA_SetCtrl(pUart, u32TempCtrlReg); + + /* clear all status */ + u32TempStat = FCUART_HWA_GetSTAT(pUart); + FCUART_HWA_WriteClearSTAT(pUart, u32TempStat); + FCUART_HWA_ClearFIFOErrorFlag(pUart); + + /* instance used */ + s_aFCUART_UartUsed[u8UartIndex] = 1U; + s_aFCUART_TransmitTimeout[u8UartIndex] = + pInitCfg->u32TransmitTimeout > 0U ? pInitCfg->u32TransmitTimeout : 3000U; + } else { + tRetVal |= (FCUART_ErrorType) FCUART_ERROR_FAILED; + } + } + } else { + tRetVal |= (FCUART_ErrorType) FCUART_ERROR_INVALID_PARAM; + } + + return tRetVal; +} + +/** + * @brief This Function is used to de-initial UART instance + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @return FCUART_ERROR_OK is ok, others are not ok + */ +FCUART_ErrorType FCUART_DeInit(uint8_t u8UartIndex) { + FCUART_ErrorType tRetVal; + FCUART_Type *pUart; + + /* check parameter */ + tRetVal = FCUART_LL_CheckInstance(u8UartIndex); + + if ((tRetVal == (FCUART_ErrorType) FCUART_ERROR_OK) && (s_aCurrentSequence[u8UartIndex] > FCUART_SEQUENCE_DEINIT)) { + + tRetVal = (FCUART_ErrorType) FCUART_ERROR_OK; + } else { + tRetVal |= (FCUART_ErrorType) FCUART_ERROR_INVALID_SEQUENCE; + } + + if (tRetVal == (FCUART_ErrorType) FCUART_ERROR_OK) { + /* set deinit state */ + s_aCurrentSequence[u8UartIndex] = FCUART_SEQUENCE_DEINIT; + pUart = (FCUART_Type *) s_aFCUART_InstanceTable[u8UartIndex]; + + FCUART_HWA_SetSoftWareReset(pUart); + } + + return tRetVal; +} + +FCUART_ErrorType FCUART_BufTransmitted(uint8_t u8UartIndex, FCUART_InterruptType *pInterruptCfg) { + FCUART_ErrorType tRetVal; + + /* check parameter */ + tRetVal = FCUART_LL_CheckInstance(u8UartIndex); + + if ((tRetVal == (FCUART_ErrorType) FCUART_ERROR_OK) && + (s_aCurrentSequence[u8UartIndex] == FCUART_SEQUENCE_NOTSTART_RECEIVE)) { + tRetVal = (FCUART_ErrorType) FCUART_ERROR_OK; + } else { + tRetVal |= (FCUART_ErrorType) FCUART_ERROR_INVALID_SEQUENCE; + } + + s_aFCUART_TxMsg[u8UartIndex] = pInterruptCfg->pTxBuf; + s_aFCUART_TxEmptyNotifyTable[u8UartIndex] = pInterruptCfg->pTxEmptyNotify; + s_aFCUART_TxCompleteNotifyTable[u8UartIndex] = pInterruptCfg->pTxCompleteNotify; + + return tRetVal; +} + +/** + * @brief This Function is used to set UART interrupt + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @param pIntCfg contains callback functions + * @return FCUART_ERROR_OK is ok, others are not ok + */ +FCUART_ErrorType FCUART_SetInterrupt(uint8_t u8UartIndex, FCUART_InterruptType *pInterruptCfg) { + FCUART_ErrorType tRetVal; + FCUART_Type *pUart; + + /* check parameter */ + tRetVal = FCUART_LL_CheckInstance(u8UartIndex); + + if ((tRetVal == (FCUART_ErrorType) FCUART_ERROR_OK) && + (s_aCurrentSequence[u8UartIndex] == FCUART_SEQUENCE_NOTSTART_RECEIVE)) { + tRetVal = (FCUART_ErrorType) FCUART_ERROR_OK; + } else { + tRetVal |= (FCUART_ErrorType) FCUART_ERROR_INVALID_SEQUENCE; + } + + if (tRetVal == (FCUART_ErrorType) FCUART_ERROR_OK) { + if (pInterruptCfg != NULL) { + pUart = (FCUART_Type *) s_aFCUART_InstanceTable[u8UartIndex]; + + /* error interrupt */ + if (true == pInterruptCfg->bEnErrorInterrupt) { + FCUART_HWA_EnableInterrupt(pUart, (uint32_t) (FCUART_INT_CTRL_ORIE | FCUART_INT_CTRL_NEIE | + FCUART_INT_CTRL_FEIE | FCUART_INT_CTRL_PEIE)); + + s_aFCUART_ErrorNotifyTable[u8UartIndex] = pInterruptCfg->pErrorNotify; + } else { + FCUART_HWA_DisableInterrupt(pUart, (uint32_t) (FCUART_INT_CTRL_ORIE | FCUART_INT_CTRL_NEIE | + FCUART_INT_CTRL_FEIE | FCUART_INT_CTRL_PEIE)); + } + + /* receive interrupt */ + if (true == pInterruptCfg->bEnRxInterrupt) { + /* check buffer point if it is null */ + if (pInterruptCfg->pRxBuf != NULL) { + FCUART_HWA_EnableInterrupt(pUart, (uint32_t) FCUART_INT_CTRL_RIE); + + s_aFCUART_RxMsg[u8UartIndex] = pInterruptCfg->pRxBuf; + s_aFCUART_RxNotifyTable[u8UartIndex] = pInterruptCfg->pRxNotify; + } else { + tRetVal |= (FCUART_ErrorType) FCUART_ERROR_INVALID_PARAM; + } + + } else { + FCUART_HWA_DisableInterrupt(pUart, (uint32_t) FCUART_INT_CTRL_RIE); + } + + /* Transfer interrupt */ + if (true == pInterruptCfg->bEnTxInterrupt) { + /* check buffer point if it is null */ + if (pInterruptCfg->pTxBuf != NULL) { + FCUART_HWA_EnableInterrupt(pUart, (uint32_t) FCUART_INT_CTRL_TIE); + s_aFCUART_TxMsg[u8UartIndex] = pInterruptCfg->pTxBuf; + s_aFCUART_TxEmptyNotifyTable[u8UartIndex] = pInterruptCfg->pTxEmptyNotify; + s_aFCUART_TxCompleteNotifyTable[u8UartIndex] = pInterruptCfg->pTxCompleteNotify; + } else { + tRetVal |= (FCUART_ErrorType) FCUART_ERROR_INVALID_PARAM; + } + + } else { + FCUART_HWA_DisableInterrupt(pUart, (uint32_t) FCUART_INT_CTRL_TIE); + } + + /* Idle interrupt */ + if (true == pInterruptCfg->bEnIdleInterrupt) { + FCUART_HWA_EnableInterrupt(pUart, (uint32_t) FCUART_INT_CTRL_IIE); + s_aFCUART_IdleNotifyTable[u8UartIndex] = pInterruptCfg->pIdleNotify; + } else { + FCUART_HWA_DisableInterrupt(pUart, (uint32_t) FCUART_INT_CTRL_IIE); + } + } else { + tRetVal |= (FCUART_ErrorType) FCUART_ERROR_INVALID_PARAM; + } + } else { + /* No deal with */ + } + + return tRetVal; +} + +/** + * @brief This Function is used to set UART WakeUp + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @param pWakeupCfg contains UART wake-up parameters + * @return FCUART_ERROR_OK is ok, others are not ok + */ +FCUART_ErrorType FCUART_SetWakeup(uint8_t u8UartIndex, FCUART_WakeupType *pWakeupCfg) { + FCUART_ErrorType tRetVal; + FCUART_Type *pUart; + + /* check parameter */ + tRetVal = FCUART_LL_CheckInstance(u8UartIndex); + + if ((tRetVal == (FCUART_ErrorType) FCUART_ERROR_OK) && + (s_aCurrentSequence[u8UartIndex] == FCUART_SEQUENCE_NOTSTART_RECEIVE)) { + tRetVal = (FCUART_ErrorType) FCUART_ERROR_OK; + } else { + tRetVal |= (FCUART_ErrorType) FCUART_ERROR_INVALID_SEQUENCE; + } + + if (pWakeupCfg != NULL) { + if (tRetVal == (FCUART_ErrorType) FCUART_ERROR_OK) { + pUart = (FCUART_Type *) s_aFCUART_InstanceTable[u8UartIndex]; + + /* + * RWC MATCH0|MATCH1 MATCH_CFG [RSWMS,RWUID] Receiver Wakeup + 0 0 X X Normal operation + 1 0 00 00 Receiver wakeup on idle line, IDLE flag not set + 1 0 00 01 Receiver wakeup on idle line, IDLE flag set + 1 0 00 10 Receiver wakeup on address mark + 1 1 11 10 Receiver wakeup on address match + 0 1 00 X0 Address mark address match, IDLE flag not set for discarded characters + 0 1 00 X1 Address mark address match, IDLE flag set for discarded characters + 0 1 01 X0 Idle line address match + 0 1 10 X0 Address match on and address match off, IDLE flag not set for discarded characters + 0 1 10 X1 Address match on and address match off, IDLE flag set for discarded characters + * + */ + + FCUART_HWA_AttachCtrl(pUart, FCUART_CTRL_RWC_MASK | + FCUART_CTRL_RSWMS_MASK); /* WakeUp enable and method select address-mark */ + FCUART_HWA_AttachBaud(pUart, FCUART_BAUD_MATCH_CFG(3U) | + FCUART_BAUD_MAEN0(1U)); /* match0 data */ + FCUART_HWA_AttachMatch(pUart, FCUART_MATCH_MATCH0(pWakeupCfg->u32WakeUpData)); /* set wake-up data*/ + } + } else { + tRetVal |= (FCUART_ErrorType) FCUART_ERROR_INVALID_PARAM; + } + + return tRetVal; +} + +/** + * @brief This Function is used to start receiving + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @return FCUART_ERROR_OK is ok, others are not ok + */ +FCUART_ErrorType FCUART_StartReceive(uint8_t u8UartIndex) { + FCUART_ErrorType tRetVal; + FCUART_Type *pUart; + + tRetVal = FCUART_LL_CheckInstance(u8UartIndex); + + if ((FCUART_ErrorType) FCUART_ERROR_OK == tRetVal) { + if (s_aCurrentSequence[u8UartIndex] == FCUART_SEQUENCE_NOTSTART_RECEIVE) { + tRetVal = (FCUART_ErrorType) FCUART_ERROR_OK; + /* set started receive state */ + s_aCurrentSequence[u8UartIndex] = FCUART_SEQUENCE_START_RECEIVE; + + pUart = (FCUART_Type *) s_aFCUART_InstanceTable[u8UartIndex]; + + /* start receive */ + FCUART_HWA_SetRxTransfer(pUart, true); + } else { + tRetVal = (FCUART_ErrorType) FCUART_ERROR_INVALID_SEQUENCE; + } + } else { + tRetVal = (FCUART_ErrorType) FCUART_ERROR_INVALID_PARAM; + } + + return tRetVal; +} + +/** + * @brief This Function is used to stop receiving + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @return FCUART_ERROR_OK is ok, others are not ok + */ +FCUART_ErrorType FCUART_StopReceive(uint8_t u8UartIndex) { + FCUART_ErrorType tRetVal; + FCUART_Type *pUart; + + /* check parameter */ + tRetVal = FCUART_LL_CheckInstance(u8UartIndex); + + if ((tRetVal == (FCUART_ErrorType) FCUART_ERROR_OK) && + ((s_aCurrentSequence[u8UartIndex] == FCUART_SEQUENCE_START_RECEIVE) || + (s_aCurrentSequence[u8UartIndex] == FCUART_SEQUENCE_NOTSTART_RECEIVE))) { + + tRetVal = (FCUART_ErrorType) FCUART_ERROR_OK; + } else { + tRetVal |= (FCUART_ErrorType) FCUART_ERROR_INVALID_SEQUENCE; + } + + if (tRetVal == (FCUART_ErrorType) FCUART_ERROR_OK) { + /* set stop state */ + s_aCurrentSequence[u8UartIndex] = FCUART_SEQUENCE_NOTSTART_RECEIVE; + pUart = (FCUART_Type *) s_aFCUART_InstanceTable[u8UartIndex]; + + /* stop receive */ + FCUART_HWA_SetRxTransfer(pUart, false); + } + + return tRetVal; +} + +/** + * @brief This Function is used to start transmit through interrupt + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @return FCUART_ERROR_OK is ok, others are not ok + */ +FCUART_ErrorType FCUART_StartTransmit(uint8_t u8UartIndex) { + FCUART_ErrorType tRetVal; + FCUART_Type *pUart; + + tRetVal = FCUART_LL_CheckInstance(u8UartIndex); + + if ((FCUART_ErrorType) FCUART_ERROR_OK == tRetVal) { + + tRetVal = (FCUART_ErrorType) FCUART_ERROR_OK; + + pUart = (FCUART_Type *) s_aFCUART_InstanceTable[u8UartIndex]; + + /* start transmit */ + FCUART_HWA_SetTxTransfer(pUart, true); + + if (false == FCUART_GetInterruptMode(u8UartIndex, (uint32_t) FCUART_INT_CTRL_TIE)) { + FCUART_HWA_EnableInterrupt(pUart, (uint32_t) FCUART_INT_CTRL_TIE); + } + } else { + tRetVal = (FCUART_ErrorType) FCUART_ERROR_INVALID_PARAM; + } + + return tRetVal; +} + +/** + * @brief This Function is used to stop transmitting + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @return FCUART_ERROR_OK is ok, others are not ok + */ +FCUART_ErrorType FCUART_StopTransmit(uint8_t u8UartIndex) { + FCUART_ErrorType tRetVal; + FCUART_Type *pUart; + + /* check parameter */ + tRetVal = FCUART_LL_CheckInstance(u8UartIndex); + + if (tRetVal == (FCUART_ErrorType) FCUART_ERROR_OK) { + + tRetVal = (FCUART_ErrorType) FCUART_ERROR_OK; + pUart = (FCUART_Type *) s_aFCUART_InstanceTable[u8UartIndex]; + + /* stop receive */ + FCUART_HWA_SetTxTransfer(pUart, false); + } else { + /* No deal with */ + } + + return tRetVal; +} + +/** + * @brief This Function is used to transmit UART data + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @param pUartData contains UART data and length + * @return FCUART_ERROR_OK is ok, others are not ok + */ +FCUART_ErrorType FCUART_Transmit(uint8_t u8UartIndex, FCUART_DataType *pUartData) { + FCUART_ErrorType tRetVal; + + FCUART_Type *pUart; + uint8_t *pData; + uint32_t u32DataLen; + uint8_t u8Index; + + /* check parameter */ + tRetVal = FCUART_LL_CheckInstance(u8UartIndex); + + if ((tRetVal == (FCUART_ErrorType) FCUART_ERROR_OK) && + ((s_aCurrentSequence[u8UartIndex] == FCUART_SEQUENCE_START_RECEIVE) || + (s_aCurrentSequence[u8UartIndex] == FCUART_SEQUENCE_NOTSTART_RECEIVE))) { + + tRetVal = (FCUART_ErrorType) FCUART_ERROR_OK; + } else { + tRetVal |= (FCUART_ErrorType) FCUART_ERROR_INVALID_SEQUENCE; + } + + if (pUartData != NULL) { + if (pUartData->pDatas != NULL) { + if (tRetVal == (FCUART_ErrorType) FCUART_ERROR_OK) { + pData = pUartData->pDatas; + u32DataLen = pUartData->u32DataLen; + pUart = (FCUART_Type *) s_aFCUART_InstanceTable[u8UartIndex]; + + for (u8Index = 0U; u8Index < u32DataLen; u8Index++) { + tRetVal |= FCUART_LL_Transmit_Char(pUart, pData[u8Index], s_aFCUART_TransmitTimeout[u8UartIndex]); + + if (tRetVal != (FCUART_ErrorType) FCUART_ERROR_OK) { + break; + } + } + } + } else { + tRetVal |= (FCUART_ErrorType) FCUART_ERROR_INVALID_PARAM; + } + } else { + tRetVal |= (FCUART_ErrorType) FCUART_ERROR_INVALID_PARAM; + } + + return tRetVal; +} + +/** + * @brief Get Stat Flag + * + * @param u8UartIndex UART instance + * @param eStatusType stat type + * @return FCUART STAT status flag + */ +uint32_t FCUART_GetStatus(uint8_t u8UartIndex, FCUART_StatType eStatusType) { + FCUART_ErrorType tRetVal; + FCUART_Type *pUart; + uint32_t u32RetVal; + + /* check parameter */ + tRetVal = FCUART_LL_CheckInstance(u8UartIndex); + + if (tRetVal == (FCUART_ErrorType) FCUART_ERROR_OK) { + pUart = (FCUART_Type *) s_aFCUART_InstanceTable[u8UartIndex]; + u32RetVal = FCUART_HWA_GetStatus(pUart, eStatusType); + } else { + u32RetVal = 0U; + } + + return u32RetVal; +} + +/** + * @brief This Function is used to receive data when polling (not used when rx interrupt enabled) + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @param pRxMsg is data buffer address, and pDatas need to be initialed with external buffer + * @return FCUART_ERROR_OK is ok, others are not ok + */ +FCUART_ErrorType FCUART_Receive_Polling(uint8_t u8UartIndex, FCUART_DataType *pRxMsg) { + FCUART_ErrorType tRetVal; + + /* check parameter */ + tRetVal = FCUART_LL_CheckInstance(u8UartIndex); + + if ((tRetVal == (FCUART_ErrorType) FCUART_ERROR_OK) && + (s_aCurrentSequence[u8UartIndex] == FCUART_SEQUENCE_START_RECEIVE)) { + + tRetVal = (FCUART_ErrorType) FCUART_ERROR_OK; + } else { + tRetVal |= (FCUART_ErrorType) FCUART_ERROR_INVALID_SEQUENCE; + } + + if (pRxMsg != NULL) { + if (pRxMsg->pDatas != NULL) { + if (s_aFCUART_UartUsed[u8UartIndex] == 1U) { + tRetVal = FCUART_LL_Receive(u8UartIndex, pRxMsg); + } + } else { + tRetVal |= (FCUART_ErrorType) FCUART_ERROR_INVALID_PARAM; + } + } else { + tRetVal |= (FCUART_ErrorType) FCUART_ERROR_INVALID_PARAM; + } + + return tRetVal; +} + +/** + * @brief This Function is used to get error when polling (not used when error interrupt enabled) + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @param pErrorValue is error value + * @return FCUART_ERROR_OK is ok, others are not ok + */ +FCUART_ErrorType FCUART_Error_Polling(uint8_t u8UartIndex, uint32_t *pErrorValue) { + FCUART_ErrorType tRetVal; + + /* check parameter */ + tRetVal = FCUART_LL_CheckInstance(u8UartIndex); + + if ((tRetVal == (FCUART_ErrorType) FCUART_ERROR_OK) && + (s_aCurrentSequence[u8UartIndex] >= FCUART_SEQUENCE_NOTSTART_RECEIVE)) { + + tRetVal = (FCUART_ErrorType) FCUART_ERROR_OK; + } else { + tRetVal |= (FCUART_ErrorType) FCUART_ERROR_INVALID_SEQUENCE; + } + + if (tRetVal == (FCUART_ErrorType) FCUART_ERROR_OK) { + if (s_aFCUART_UartUsed[u8UartIndex] == 1U) { + /* check error */ + *pErrorValue = FCUART_LL_Error(u8UartIndex); + } else { + tRetVal = (FCUART_ErrorType) FCUART_ERROR_FAILED; + } + } + + return tRetVal; +} + +/** + * @brief This Function is used to enable fcuart loop mode + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @param bStatus enable/disable status of loop mode + * @return FCUART_ERROR_OK is ok, others are not ok + * + */ +FCUART_ErrorType FCUART_SetLoopMode(uint8_t u8UartIndex, bool bStatus) { + FCUART_Type *pUart; + FCUART_ErrorType tRetVal; + + /* check parameter */ + tRetVal = FCUART_LL_CheckInstance(u8UartIndex); + + if (tRetVal == (FCUART_ErrorType) FCUART_ERROR_OK) { + pUart = (FCUART_Type *) s_aFCUART_InstanceTable[u8UartIndex]; + + if (true == bStatus) { + FCUART_HWA_EnableLoopMode(pUart); + } else { + FCUART_HWA_DisableLoopMode(pUart); + } + } else { + /* No deal with */ + } + return tRetVal; +} + +/** + * @brief This Function is used to send 9 bits data + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @param u16Data data to send + * @return FCUART_ERROR_OK is ok, others are not ok + * + */ +FCUART_ErrorType FCUART_SendData_9Bits(uint8_t u8UartIndex, uint16_t u16Data) { + FCUART_Type *pUart; + FCUART_ErrorType tRetVal; + uint8_t u8SingleBit_8; + + /* check parameter */ + tRetVal = FCUART_LL_CheckInstance(u8UartIndex); + if (tRetVal == (FCUART_ErrorType) FCUART_ERROR_OK) { + pUart = (FCUART_Type *) s_aFCUART_InstanceTable[u8UartIndex]; + + u8SingleBit_8 = (uint8_t) ((u16Data >> 8U) & 1U); + + /* Set bit8 */ + FCUART_HWA_SetR9T8(pUart, u8SingleBit_8); + /* Set 0 ~ 7 bits */ + FCUART_HWA_SetData(pUart, (uint8_t) u16Data); + } else { + /* No deal with */ + } + return tRetVal; + +} + +/** + * @brief This Function is used to Get 9 bits data + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @param pData pointer to data + * @return FCUART_ERROR_OK is ok, others are not ok + * + */ +FCUART_ErrorType FCUART_GetData_9Bits(uint8_t u8UartIndex, uint16_t *pData) { + FCUART_Type *pUart; + FCUART_ErrorType tRetVal; + uint8_t u8SingleBit_8; + uint8_t u8Temp; + + /* check parameter */ + tRetVal = FCUART_LL_CheckInstance(u8UartIndex); + if (tRetVal == (FCUART_ErrorType) FCUART_ERROR_OK) { + pUart = (FCUART_Type *) s_aFCUART_InstanceTable[u8UartIndex]; + /* Get bit8 */ + u8SingleBit_8 = FCUART_HWA_GetR8T9(pUart); + /* Get 0 ~ 7 bits */ + u8Temp = FCUART_HWA_GetData(pUart); + /* Get 0 ~ 8 bits */ + *pData = (((uint16_t) u8SingleBit_8 << 8U) | (uint16_t) u8Temp); + } else { + /* No deal with */ + } + return tRetVal; + +} + +/** + * @brief This Function is used to send 10 bits data + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @param u16Data data to send + * @return FCUART_ERROR_OK is ok, others are not ok + * + */ +FCUART_ErrorType FCUART_SendData_10Bits(uint8_t u8UartIndex, uint16_t u16Data) { + FCUART_Type *pUart; + FCUART_ErrorType tRetVal; + uint8_t u8SingleBit_8; + uint8_t u8SingleBit_9; + + /* check parameter */ + tRetVal = FCUART_LL_CheckInstance(u8UartIndex); + if (tRetVal == (FCUART_ErrorType) FCUART_ERROR_OK) { + pUart = (FCUART_Type *) s_aFCUART_InstanceTable[u8UartIndex]; + + u8SingleBit_8 = (uint8_t) ((u16Data >> 8U) & 1U); + u8SingleBit_9 = (uint8_t) ((u16Data >> 9U) & 1U); + + /* Set bit8 */ + FCUART_HWA_SetR9T8(pUart, u8SingleBit_8); + /* Set bit9 */ + FCUART_HWA_SetR8T9(pUart, u8SingleBit_9); + /* Set 0 ~ 7 bits */ + FCUART_HWA_SetData(pUart, (uint8_t) u16Data); + } else { + /* No deal with */ + } + return tRetVal; + +} + +/** + * @brief This Function is used to Get 10 bits data + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @param pData pointer to data + * @return FCUART_ERROR_OK is ok, others are not ok + * + */ +FCUART_ErrorType FCUART_GetData_10Bits(uint8_t u8UartIndex, uint16_t *pData) { + FCUART_Type *pUart; + FCUART_ErrorType tRetVal; + uint8_t u8SingleBit_8; + uint8_t u8SingleBit_9; + uint8_t u8Temp; + + /* check parameter */ + tRetVal = FCUART_LL_CheckInstance(u8UartIndex); + if (tRetVal == (FCUART_ErrorType) FCUART_ERROR_OK) { + pUart = (FCUART_Type *) s_aFCUART_InstanceTable[u8UartIndex]; + /* Get bit8 */ + u8SingleBit_8 = FCUART_HWA_GetR8T9(pUart); + /* Get bit9 */ + u8SingleBit_9 = FCUART_HWA_GetR9T8(pUart); + /* Get 0 ~ 7 bits */ + u8Temp = FCUART_HWA_GetData(pUart); + /* Get 0 ~ 9 bits */ + *pData = (((uint16_t) u8SingleBit_8 << 8U) | ((uint16_t) u8SingleBit_9 << 9U) | (uint16_t) u8Temp); + } else { + /* No deal with */ + } + return tRetVal; + +} + +/** + * @brief This Function is used to set bit mode,parity and stop bit + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @param pData pointer to data + * @return FCUART_ERROR_OK is ok, others are not ok + * + */ +FCUART_ErrorType FCUART_SetBitModeAndParity(uint8_t u8UartIndex, + FCUART_BitModeType eBitMode, + FCUART_StopBitNumType eStopBit, + FCUART_ParityType eParityType, + bool bParityEnable +) { + FCUART_Type *pUart; + FCUART_ErrorType tRetVal; + + /* check parameter */ + tRetVal = FCUART_LL_CheckInstance(u8UartIndex); + if (tRetVal == (FCUART_ErrorType) FCUART_ERROR_OK) { + pUart = (FCUART_Type *) s_aFCUART_InstanceTable[u8UartIndex]; + + FCUART_HWA_SetBitMode(pUart, eBitMode); + FCUART_HWA_SetStopBit(pUart, eStopBit); + FCUART_HWA_SetParity(pUart, eParityType, bParityEnable); + } else { + /* No deal with */ + } + return tRetVal; +} + +/** + * @brief This Function is used to Get current interrupt mode + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @param u32Data Interrupt type to get + * @return true/false + * + */ +bool FCUART_GetInterruptMode(uint8_t u8UartIndex, uint32_t u32Data) { + FCUART_ErrorType tTempVal; + bool bRetVal; + FCUART_Type *pUart; + uint32_t u32CtrlRegData; + + /* check parameter */ + tTempVal = FCUART_LL_CheckInstance(u8UartIndex); + if (tTempVal == (FCUART_ErrorType) FCUART_ERROR_OK) { + pUart = (FCUART_Type *) s_aFCUART_InstanceTable[u8UartIndex]; + + u32CtrlRegData = FCUART_HWA_GetCtrl(pUart); + bRetVal = ((u32CtrlRegData & u32Data) > 0U) ? true : false; + } else { + bRetVal = false; + } + + return bRetVal; +} + +/** + * @brief This Function is used to assign data to send through interrupt + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @param pData data pointer + * @param u32Length data length to send + * @return FCUART_ERROR_OK is ok, others are not ok + * + */ +FCUART_ErrorType FCUART_AssignTxInterruptData(uint8_t u8UartIndex, uint8_t *pData, uint32_t u32Length) { + FCUART_ErrorType tTempVal; + /* check parameter */ + tTempVal = FCUART_LL_CheckInstance(u8UartIndex); + if (tTempVal == (FCUART_ErrorType) FCUART_ERROR_OK) { + if (pData != NULL) { + s_aFCUART_TxMsg[u8UartIndex]->pDatas = pData; + s_aFCUART_TxMsg[u8UartIndex]->u32DataLen = u32Length; + } else { + tTempVal = (FCUART_ErrorType) FCUART_ERROR_INVALID_PARAM; + } + } else { + /* No deal with */ + } + + return tTempVal; +} + + +/* ################################################################################## */ +/* ############################## Interrupt Services ################################ */ +/** + * @brief This Function is used to deal with FCUART TxRx interrupt + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * + */ +void FCUARTN_RxTx_IRQHandler(uint8_t u8UartIndex) { + FCUART_ErrorType tTempVal; + FCUART_DataType *pRxMsgList; + FCUART_DataType *pTxMsgList; + uint32_t u32ErrorValue; + uint32_t u32CtrlRegData; + + //Do not check instance because it should be checked before + u32CtrlRegData = FCUART_HWA_GetCtrl((FCUART_Type *) s_aFCUART_InstanceTable[u8UartIndex]); + + /* Handle receive interrupt */ + if (((uint32_t) FCUART_INT_CTRL_RIE) == (u32CtrlRegData & ((uint32_t) FCUART_INT_CTRL_RIE))) { + /* get buffer point and it stored when called SetInterrupt */ + pRxMsgList = s_aFCUART_RxMsg[u8UartIndex]; + /* check pUart receive data */ + tTempVal = FCUART_LL_Receive(u8UartIndex, pRxMsgList); + + /* check buffer valid */ + if ((tTempVal == (FCUART_ErrorType) FCUART_ERROR_OK) && (pRxMsgList != NULL)) { + if (s_aFCUART_RxNotifyTable[u8UartIndex] != NULL) { + s_aFCUART_RxNotifyTable[u8UartIndex](u8UartIndex, pRxMsgList); + } + } + } + + /* Handle transmit interrupt */ + if (((uint32_t) FCUART_INT_CTRL_TIE) == (u32CtrlRegData & ((uint32_t) FCUART_INT_CTRL_TIE))) { + /* get buffer point and it stored when called SetInterrupt */ + pTxMsgList = s_aFCUART_TxMsg[u8UartIndex]; + /* transfer data */ + tTempVal = FCUART_LL_Transmit_Empty(u8UartIndex, pTxMsgList); + + if ((tTempVal == (FCUART_ErrorType) FCUART_ERROR_OK) && (pTxMsgList != NULL)) { + if (s_aFCUART_TxEmptyNotifyTable[u8UartIndex] != NULL) { + s_aFCUART_TxEmptyNotifyTable[u8UartIndex](u8UartIndex, pTxMsgList); + } + } + } + + /* Handle transmit complete interrupt */ + if (((uint32_t) FCUART_INT_CTRL_TCIE) == (u32CtrlRegData & ((uint32_t) FCUART_INT_CTRL_TCIE))) { + tTempVal = FCUART_LL_Transmit_Complete(u8UartIndex); + + if ((tTempVal == (FCUART_ErrorType) FCUART_ERROR_OK) && + (s_aFCUART_TxCompleteNotifyTable[u8UartIndex] != NULL)) { + s_aFCUART_TxCompleteNotifyTable[u8UartIndex](u8UartIndex, NULL); + } + } + + /* Handle idle interrupt */ + if (((uint32_t) FCUART_INT_CTRL_IIE) == (u32CtrlRegData & ((uint32_t) FCUART_INT_CTRL_IIE))) { + tTempVal = FCUART_LL_Idle(u8UartIndex); + if ((tTempVal == (FCUART_ErrorType) FCUART_ERROR_OK) && (s_aFCUART_IdleNotifyTable[u8UartIndex] != NULL)) { + s_aFCUART_IdleNotifyTable[u8UartIndex](u8UartIndex); + } + } + + /* Handle error interrupt */ + if (0U != (u32CtrlRegData & ((uint32_t) (FCUART_INT_CTRL_ORIE | FCUART_INT_CTRL_NEIE | FCUART_INT_CTRL_FEIE | + FCUART_INT_CTRL_PEIE)))) { + /* check error */ + u32ErrorValue = FCUART_LL_Error(u8UartIndex); + + if ((u32ErrorValue != 0U) && (s_aFCUART_ErrorNotifyTable[u8UartIndex] != NULL)) { + s_aFCUART_ErrorNotifyTable[u8UartIndex](u8UartIndex, u32ErrorValue); + } + + PROCESS_UNUSED_VAR(u32ErrorValue) + } +} + +/************************ Uart Print Library ************************/ + +/** + * @brief This Function is used to print ASCII char from UART + * + * @param u8UartIndex is UART instance, 0U..(FCUART_INSTANCE_COUNT-1U) + * @param fmt is char format + * @return FCUART_ERROR_OK is ok, others are not ok + */ +FCUART_ErrorType FCUART_Printf(uint8_t u8UartIndex, char *fmt, ...) { + FCUART_Type *pUart; + FCUART_ErrorType tRetVal; + const char *pStr; + int i32Temp; + unsigned char TxData; + uint8_t u8Number; + uint8_t u8LenthNumber = 4U; + char TempBuffer[16]; + va_list ap; + + va_start(ap, fmt); + /* check parameter */ + tRetVal = FCUART_LL_CheckInstance(u8UartIndex); + + if ((tRetVal == (FCUART_ErrorType) FCUART_ERROR_OK) && + ((s_aCurrentSequence[u8UartIndex] == FCUART_SEQUENCE_START_RECEIVE) || + (s_aCurrentSequence[u8UartIndex] == FCUART_SEQUENCE_NOTSTART_RECEIVE))) { + + tRetVal = (FCUART_ErrorType) FCUART_ERROR_OK; + } else { + tRetVal |= (FCUART_ErrorType) FCUART_ERROR_INVALID_SEQUENCE; + } + + if (tRetVal == (FCUART_ErrorType) FCUART_ERROR_OK) { + pUart = (FCUART_Type *) s_aFCUART_InstanceTable[u8UartIndex]; + + while (*fmt != (char) 0) { + /* Escape character */ + if ((*fmt) == ESCAPE_CHARACTER) { + switch (*(++fmt)) { + case 'r': { + TxData = ENTER; + tRetVal = FCUART_LL_Transmit_Char(pUart, TxData, s_aFCUART_TransmitTimeout[u8UartIndex]); + fmt++; + } + break; + + case 'n': { + TxData = NEW_LINE; + tRetVal = FCUART_LL_Transmit_Char(pUart, TxData, s_aFCUART_TransmitTimeout[u8UartIndex]); + fmt++; + } + break; + + default: + fmt++; + break; + } + } else if ((*fmt) == (char) '%') { + switch (*(++fmt)) { + case 's': { + pStr = va_arg(ap, const char *); + for (; *pStr; pStr++) { + tRetVal = FCUART_LL_Transmit_Char(pUart, *((unsigned char *) pStr), + s_aFCUART_TransmitTimeout[u8UartIndex]); + } + fmt++; + } + break; + + case 'd': { + i32Temp = va_arg(ap, int); + if (0U == FCUART_Int2Char(i32Temp, TempBuffer, UART_PRINT_RADIX_DEC, false)) { + for (pStr = TempBuffer; *pStr; pStr++) { + tRetVal = FCUART_LL_Transmit_Char(pUart, *((unsigned char *) pStr), + s_aFCUART_TransmitTimeout[u8UartIndex]); + } + } + fmt++; + } + break; + + case 'x': { + i32Temp = va_arg(ap, int); + if (0U == FCUART_Int2Char(i32Temp, TempBuffer, UART_PRINT_RADIX_HEX, false)) { + for (pStr = TempBuffer; *pStr; pStr++) { + tRetVal = FCUART_LL_Transmit_Char(pUart, *((unsigned char *) pStr), + s_aFCUART_TransmitTimeout[u8UartIndex]); + } + } + fmt++; + } + break; + + case 'X': { + i32Temp = va_arg(ap, int); + if (0U == FCUART_Int2Char(i32Temp, TempBuffer, UART_PRINT_RADIX_HEX, true)) { + for (pStr = TempBuffer; *pStr; pStr++) { + tRetVal = FCUART_LL_Transmit_Char(pUart, *((unsigned char *) pStr), + s_aFCUART_TransmitTimeout[u8UartIndex]); + } + } + fmt++; + } + break; + + case '.': { + u8Number = (uint8_t) (*(++fmt) - '0'); + if ((*(++fmt)) == 'f') { + double num = va_arg(ap, double); + if (0U == FCUART_Float2Char(num, TempBuffer, u8Number)) { + for (pStr = TempBuffer; *pStr; pStr++) { + tRetVal = FCUART_LL_Transmit_Char(pUart, *((unsigned char *) pStr), + s_aFCUART_TransmitTimeout[u8UartIndex]); + } + } + fmt++; + } + } + break; + + case 'f': { + double num = va_arg(ap, double); + if (0U == FCUART_Float2Char(num, TempBuffer, u8LenthNumber)) { + for (pStr = TempBuffer; *pStr; pStr++) { + tRetVal = FCUART_LL_Transmit_Char(pUart, *((unsigned char *) pStr), + s_aFCUART_TransmitTimeout[u8UartIndex]); + } + } + fmt++; + } + break; + + default: + fmt++; + break; + } + } else { + tRetVal = FCUART_LL_Transmit_Char(pUart, *((unsigned char *) fmt), + s_aFCUART_TransmitTimeout[u8UartIndex]); + + if (tRetVal != FCUART_ERROR_OK) { + break; + } + + fmt++; + } + } + } + + va_end(ap); + + return tRetVal; +} + +/** + * @brief Convert integer to char + * + * @param i32Value + * @param pOutStr + * @param eRadix + * @return 0 is ok + */ +static uint8_t FCUART_Int2Char(int i32Value, char *pOutStr, UART_PrintIntType eRadix, bool bHexUpper) { + uint8_t u8Retval; + char aCharListUpper[] = "0123456789ABCDEF"; + char aCharListLower[] = "0123456789abcdef"; + char aNumList[] = "0123456789"; + char *pCharList; + uint32_t u32Temp; + uint8_t u8Index = 0U; + uint8_t u8ValueStart = 0U; + char Temp = 0; + uint32_t j; + + if (NULL == pOutStr) { + u8Retval = 1U; + } else { + u8Retval = 0U; + if ((UART_PRINT_RADIX_DEC == eRadix) && (i32Value < 0)) { + // Decimal and negative + u32Temp = (uint32_t) (0 - i32Value); + pOutStr[u8Index++] = '-'; + u8ValueStart = 1U; + pCharList = aNumList; + } else { + if (true == bHexUpper) { + pCharList = aCharListUpper; + } else { + pCharList = aCharListLower; + } + u32Temp = (uint32_t) i32Value; + } + + // Data is converted to a string and stored in reverse order + do { + pOutStr[u8Index++] = pCharList[u32Temp % (uint8_t) eRadix]; + u32Temp /= (uint8_t) eRadix; + } while (u32Temp); + + pOutStr[u8Index] = '\0'; + + // Convert the string with reverse order to positive + for (j = u8ValueStart; j < (u8Index + u8ValueStart) / 2U; j++) { + Temp = pOutStr[j]; + pOutStr[j] = pOutStr[u8Index - j - 1U + u8ValueStart]; + pOutStr[u8Index - j - 1U + u8ValueStart] = Temp; + } + } + return u8Retval; +} + +/** + * @brief Convert float to char + * + * @param Value + * @param pOutStr + * @param U32Eps + * @return 0 is ok + */ +static uint8_t FCUART_Float2Char(double Value, char *pOutStr, uint32_t u32Eps) { + uint32_t u32Integer; + double Decimal; + char aCharList[] = "0123456789"; + uint8_t u8ValueStart = 0U; + uint32_t u32TempCnt = 1U; + char Temp = 0; + double TempFactor = 0.1; + uint8_t u8Index = 0U; + uint32_t u32TempDecimal; + uint8_t u8Retval; + uint32_t j; + + if (NULL == pOutStr) { + u8Retval = 1U; + } else { + u8Retval = 0U; + // Extract integer and decimal from the input number + if (Value < FLOAT_ZERO) { + Decimal = (double) ((int32_t) Value - Value); + u32Integer = (uint32_t) (0.0 - Value); + pOutStr[u8Index++] = '-'; + u8ValueStart = 1U; + } else { + u32Integer = (uint32_t) Value; + Decimal = (double) (Value - u32Integer); + } + // The integer part of the data is converted into a string and stored in reverse order + do { + pOutStr[u8Index++] = aCharList[u32Integer % 10U]; + u32Integer /= 10U; + } while (0U != u32Integer); + + pOutStr[u8Index] = '\0'; + + // Convert the string with reverse order to positive + for (j = u8ValueStart; j < (u8Index + u8ValueStart) / 2U; j++) { + Temp = pOutStr[j]; + pOutStr[j] = pOutStr[u8Index - j - 1U + u8ValueStart]; + pOutStr[u8Index - j - 1U + u8ValueStart] = Temp; + } + + // Accuracy problem, preventing input 1.2 and output 1.19 + for (j = 0U; j <= u32Eps; j++) { + TempFactor *= 0.1; + } + Decimal += TempFactor; + + for (j = 0; j < u32Eps; j++) { + Decimal *= (double) 10.0; + u32TempCnt *= 10U; + } + + u32TempDecimal = (uint32_t) Decimal; + pOutStr[u8Index++] = '.'; + for (j = 0; j < u32Eps; j++) { + u32TempCnt /= 10U; + if (0U != u32TempCnt) { + pOutStr[u8Index++] = u32TempDecimal / u32TempCnt + '0'; + u32TempDecimal %= u32TempCnt; + } + } + pOutStr[u8Index] = '\0'; + } + return u8Retval; +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_flash.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_flash.c new file mode 100644 index 0000000..8f8e08f --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_flash.c @@ -0,0 +1,998 @@ +/** + * @file fc7xxx_driver_flash.c + * @author Flagchip + * @brief FC7xxx Flash driver source code + * @version 0.1.0 + * @date 2024-01-11 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-11 Flagchip054 N/A First version for FC7240 + ******************************************************************************** */ + +#include "fc7xxx_driver_flash.h" + +/* ################################################################################## */ +/* ####################################### Macro #################################### */ + +#define STATUS_SUCCESS 0x001UL +#define STATUS_HVOP 0x8001UL +#define FLASH_API_DISABLE 0x0UL +#define FLASH_API_ENABLE 0x1UL +#define FLASH_API_SIZE_8M 0x0UL +#define WDG_TUNE_DISABLE 0x1u +#define FLASH_AUTO_HOLD_ENABLE 0x1UL +#define FLASH_AUTO_HOLD_DISABLE 0x0UL +#define FLASH_REG_BIT_CFG_DISABLE 0x0UL +#define FLASH_REG_BIT_CFG_ENABLE 0x1UL +#define FLASH_REG_BIT_CFG_HOLD 0x2UL + +#define INVAILD_ADDR ((void*)0xFFFFFFFFU) + +#define FLS_MAX_ERASE_BLANK_CHECK (256U) + +#define FLS_ABT_TIMEOUT_VALUE (1000000U) +#define FLS_ASYNC_WRITE_TIMEOUT_VALUE (1000U) +#define FLS_ASYNC_ERASE_TIMEOUT_VALUE (500000U) +/*================================================================================================= +* LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS) +=================================================================================================*/ + +typedef uint32_t status_t; + +typedef struct { + uint32_t blk_sel; + uint32_t dest; +} FLASH_DRV_ERASESECTOR_CFG_T; + +typedef struct { + uint32_t dest; + uint32_t size; + uint32_t *pData; + uint32_t wdg_tune; + uint32_t pgff; +} FLASH_DRV_PRGM_CFG_T; + + +typedef struct +{ + uint16 u16FlashRomApiMajorVersion; + uint16 u16FlashRomApiMinorVersion; + + status_t (*FLASH_DRV_EraseBlock)(FLASH_API_BLOCK_SELECT_TYPE blk_se, uint32_t int_en, uint32_t type); + status_t (*FLASH_DRV_EraseBlock_Clear)(void); + status_t (*FLASH_DRV_EraseSector)(FLASH_DRV_ERASESECTOR_CFG_T * flash_api_cfg, uint32_t int_en, uint32_t type); + status_t (*FLASH_DRV_EraseSector_Clear)(void); + uint32_t RESERVED2[2U]; + status_t (*FLASH_DRV_Program)(FLASH_DRV_PRGM_CFG_T * flash_api_cfg, uint32_t int_en, uint32_t type); + status_t (*FLASH_DRV_Program_Clear)(void); + uint32_t RESERVED3[6U]; + status_t (*FLASH_DRV_HV_Status_Check)(void); + uint32_t RESERVED4[8U]; + status_t (*FLASH_DRV_ENABLE_HOLD_CFG)(uint32_t flash_api_cfg); +}FLASH_ROM_API_ENTRY_T; + + +/** flash driver header for finding function in special address */ +#define FLASHAPI_IN_ROM_ADDR 0x04810200U /* flash api address in rom */ +const FLASH_ROM_API_ENTRY_T *s_pFlashDriver_RomApiHeader; + +/* ################################################################################## */ +/* ################################ Local Variables ################################# */ + + +/* ################################################################################## */ +/* ########################### Local Prototype Functions ############################ */ + + +/* ################################################################################## */ +/* ########################### Global Prototype Functions ########################### */ + + + + +/* ################################################################################## */ +/* ################################ Local Functions ################################# */ + + +/** + * \brief PFlash Driver Function for Erasing Address Check + * + * \param pFlashParam flash driver erase parameter + */ +static FLASH_StatusType FLASHDRIVER_LL_PFlashEraseCheck(FLASH_DRIVER_ParamType *pFlashParam) +{ + FLASH_StatusType tRetVal; + + if (s_pFlashDriver_RomApiHeader != (FLASH_ROM_API_ENTRY_T *)FLASHAPI_IN_ROM_ADDR) + { + tRetVal = FLASH_ERROR_NO_INIT; + } + else + { + tRetVal = FLASH_ERROR_OK; + /* check address align */ + if (pFlashParam->u32Address & (PFLASH_ERASE_SECTOR_SIZE - 1U)) + { + tRetVal = FLASH_ERROR_INVALID_ADDR; + pFlashParam->u32ErrorAddress = pFlashParam->u32Address; + + } + else + { + /* check length align */ + if (pFlashParam->u32Length & (PFLASH_ERASE_SECTOR_SIZE - 1U)) + { + tRetVal = FLASH_ERROR_INVALID_SIZE; + pFlashParam->u32ErrorAddress = pFlashParam->u32Address; + } + + } + } + return tRetVal; +} + +/** + * \brief DFlash Driver Function for Erasing Address Check + * + * \param pFlashParam flash driver erase parameter + */ +static FLASH_StatusType FLASHDRIVER_LL_DFlashEraseCheck(FLASH_DRIVER_ParamType *pFlashParam) +{ + FLASH_StatusType tRetVal; + + if (s_pFlashDriver_RomApiHeader != (FLASH_ROM_API_ENTRY_T *)FLASHAPI_IN_ROM_ADDR) + { + tRetVal = FLASH_ERROR_NO_INIT; + } + else + { + + tRetVal = FLASH_ERROR_OK; + + /* check address align */ + if (pFlashParam->u32Address & (DFLASH_ERASE_SECTOR_SIZE - 1U)) + { + tRetVal = FLASH_ERROR_INVALID_ADDR; + pFlashParam->u32ErrorAddress = pFlashParam->u32Address; + + } + else + { + /* check length align */ + if (pFlashParam->u32Length & (DFLASH_ERASE_SECTOR_SIZE - 1U)) + { + tRetVal = FLASH_ERROR_INVALID_SIZE; + pFlashParam->u32ErrorAddress = pFlashParam->u32Address; + } + + } + + } + return tRetVal; +} + +/** + * \brief PFlash Driver Function for Writing address Check + * + * \param pFlashParam flash driver write parameter + */ +static FLASH_StatusType FLASHDRIVER_PFlashWriteCheck(FLASH_DRIVER_ParamType *pFlashParam) +{ + FLASH_StatusType tRetVal; + + if (s_pFlashDriver_RomApiHeader != (FLASH_ROM_API_ENTRY_T *)FLASHAPI_IN_ROM_ADDR) + { + tRetVal = FLASH_ERROR_NO_INIT; + } + else + { + tRetVal = FLASH_ERROR_OK; + + /* check address align */ + if (pFlashParam->u32Address & (PFLASH_PROGRAM_PAGE_MIN_SIZE - 1U)) + { + tRetVal = FLASH_ERROR_INVALID_ADDR; + pFlashParam->u32ErrorAddress = pFlashParam->u32Address; + } + + else + { + /* check length align */ + if (pFlashParam->u32Length & (PFLASH_PROGRAM_PAGE_MIN_SIZE - 1U)) + { + tRetVal = FLASH_ERROR_INVALID_SIZE; + pFlashParam->u32ErrorAddress = pFlashParam->u32Address; + } + } + } + return tRetVal; +} + +/** + * \brief DFlash Driver Function for Writing address Check + * + * \param pFlashParam flash driver write parameter + */ +static FLASH_StatusType FLASHDRIVER_DFlashWriteCheck(FLASH_DRIVER_ParamType *pFlashParam) +{ + FLASH_StatusType tRetVal; + + if (s_pFlashDriver_RomApiHeader != (FLASH_ROM_API_ENTRY_T *)FLASHAPI_IN_ROM_ADDR) + { + tRetVal = FLASH_ERROR_NO_INIT; + } + else + { + tRetVal = FLASH_ERROR_OK; + + /* check address align */ + if (pFlashParam->u32Address & (DFLASH_PROGRAM_PAGE_MIN_SIZE - 1U)) + { + tRetVal = FLASH_ERROR_INVALID_ADDR; + pFlashParam->u32ErrorAddress = pFlashParam->u32Address; + } + + else + { + /* check length align */ + if (pFlashParam->u32Length & (DFLASH_PROGRAM_PAGE_MIN_SIZE - 1U)) + { + tRetVal = FLASH_ERROR_INVALID_SIZE; + pFlashParam->u32ErrorAddress = pFlashParam->u32Address; + } + } + } + return tRetVal; +} + +/** + * \brief PFlash Driver Function for lock/unlock sector + * + * \param u32Address sector address + * \param bLock 0U-unlock, 1U-lock + */ +static void FLASHDRIVER_PFlashLockBlock(FLASH_API_BLOCK_SELECT_TYPE blk_sel, uint8_t bLock) +{ + uint32_t u32Index; + uint32_t u32Temp; + + u32Index = (uint32_t)blk_sel; + /* 1 bank contains more than 256KB, used FB_CPELCK for first and last 256KB used FB_FPELCK */ + /* PFLASH bank index */ + u32Temp = bLock ? 0xFFFFFFFFUL : 0x0UL; + if(blk_sel < FLASH_DATA_BLOCK_SELECT0) + { + FMC1->FB_CPELCK[u32Index] = u32Temp; + FMC1->FB_FPELCK[u32Index] = u32Temp; + } + else + { + FMC1->FB_FPELCK[u32Index] = u32Temp; + } +} + +/** + * \brief PFlash Driver Function for lock/unlock sector + * + * \param u32Address sector address + * \param bLock 0U-unlock, 1U-lock + */ +static FLASH_StatusType FLASHDRIVER_PFlashLockSector(uint32_t u32Address, uint8_t bLock) +{ + FLASH_StatusType tRetVal; + uint32_t u32Index; + uint32_t u32Length; + uint32_t u32Temp; + + tRetVal = FLASH_ERROR_OK; + + /* 1 bank contains more than 256KB, used FB_CPELCK for first and last 256KB used FB_FPELCK */ + if ((u32Address >= PFLASH_ADDR_START) && (u32Address <= PFLASH_ADDR_END)) + { + /* PFLASH bank index */ + u32Index = (u32Address - PFLASH_ADDR_START) / PFLASH_BANK_SIZE; + u32Length = ((u32Address - PFLASH_ADDR_START) % PFLASH_BANK_SIZE) ; + if (u32Length < (PFLASH_BANK_SIZE - FLASH_256KB_SIZE)) /* first 1792KB */ + { + u32Temp = ((uint32_t)1UL << ((u32Address - PFLASH_ADDR_START - PFLASH_BANK_SIZE * u32Index) >> 16)); + u32Temp = bLock ? 0xFFFFFFFFUL : (0xFFFFFFFFUL ^ u32Temp); + FMC1->FB_CPELCK[u32Index] = u32Temp; + } + else /* last 256KB */ + { + u32Temp = ((u32Address - PFLASH_ADDR_START - PFLASH_BANK_SIZE * u32Index - PFLASH_LAST256K_OFFSET) >> 13); + u32Temp = ((uint32_t)1UL << u32Temp); + u32Temp = bLock ? 0xFFFFFFFFUL : (0xFFFFFFFFUL ^ u32Temp); + /* 0x1C0000UL */ + FMC1->FB_FPELCK[u32Index] = u32Temp; + } + } + else + { + tRetVal = FLASH_ERROR_INVALID_ADDR; + } + return tRetVal; +} + +/** + * \brief DFlash Driver Function for lock/unlock sector + * + * \param u32Address sector address + * \param bLock 0U-unlock, 1U-lock + */ +static FLASH_StatusType FLASHDRIVER_DFlashLockSector(uint32_t u32Address, uint8_t bLock) +{ + FLASH_StatusType tRetVal; + uint32_t u32Index; + uint32_t u32Temp; + tRetVal = FLASH_ERROR_OK; + + /* 1 bank contains only 256KB, only used FB_FPELCK */ + u32Index = 2U; + if ((u32Address >= DFLASH_ADDR_START) && (u32Address <= DFLASH_ADDR_END)) + { + u32Temp = 0xFFFFFFFFUL ^ (1UL << ((u32Address - DFLASH_ADDR_START - DFLASH_BANK0_SIZE * (u32Index - 2U)) >> 13)); + FMC1->FB_FPELCK[u32Index] = bLock ? 0xFFFFFFFFUL : u32Temp ; + } + else + { + tRetVal = FLASH_ERROR_INVALID_ADDR; + } + return tRetVal; +} + +/** + * \brief Get Flash Configuration + * + * \param u32Address the flash address + * \param pFlash_api_cfg out flash parameter + */ +static FLASH_StatusType FLASHDRIVER_GetFlashConfig(uint32_t u32Address, FLASH_DRV_ERASESECTOR_CFG_T *pFlash_api_cfg) +{ + FLASH_StatusType tRetVal; + tRetVal = FLASH_ERROR_OK; + + if ((u32Address >= PFLASH_ADDR_START) && (u32Address < PFLASH_ADDR_START + PFLASH_BANK_SIZE)) + { + pFlash_api_cfg->blk_sel = FLASH_BLOCK_SELECT0; + pFlash_api_cfg->dest = u32Address; + + } + else if ((u32Address >= PFLASH_ADDR_START) && (u32Address < PFLASH_ADDR_START + PFLASH_BANK_SIZE*2U)) + { + pFlash_api_cfg->blk_sel = FLASH_BLOCK_SELECT1; + pFlash_api_cfg->dest = u32Address; + } + else if ((u32Address >= DFLASH_ADDR_START) && (u32Address < DFLASH_ADDR_START + DFLASH_BANK0_SIZE)) + { + pFlash_api_cfg->blk_sel = FLASH_DATA_BLOCK_SELECT0; + pFlash_api_cfg->dest = u32Address; + } + else + { + tRetVal = FLASH_ERROR_INVALID_ADDR; + } + return tRetVal; +} + +/* ################################################################################## */ +/* ################################# Global Functions ############################### */ + +void FLASHDRIVER_Init(void) +{ + s_pFlashDriver_RomApiHeader = (FLASH_ROM_API_ENTRY_T *)FLASHAPI_IN_ROM_ADDR; +} + +/** + * \brief PFlash Driver Function for Erasing + * + * \param pFlashParam flash driver erase parameter + * \return ErrorType + */ +FLASH_StatusType FLASHDRIVER_FlashEraseBlock(FLASH_API_BLOCK_SELECT_TYPE blk_sel) +{ + uint32_t u32TryCount; + + FLASH_StatusType tRetVal; + uint32_t u32Temp; + + tRetVal = FLASH_ERROR_OK; + + if(blk_sel > FLASH_DATA_BLOCK_SELECT0) + { + tRetVal = FLASH_ERROR_INVALID_PARAM; + } + else + { + s_pFlashDriver_RomApiHeader->FLASH_DRV_ENABLE_HOLD_CFG(FLASH_AUTO_HOLD_ENABLE); + FLASHDRIVER_PFlashLockBlock(blk_sel, 0); + __asm(" cpsid i"); + u32Temp = s_pFlashDriver_RomApiHeader-> FLASH_DRV_EraseBlock(blk_sel, FLASH_API_DISABLE, 0); + __asm(" cpsie i"); + tRetVal = (u32Temp == STATUS_SUCCESS) ? FLASH_ERROR_OK : FLASH_ERROR_FAILED; + /* check erase operation valid */ + if (tRetVal != FLASH_ERROR_OK) + { + + } + else + { + /* check erasing still in progress */ + tRetVal = FLASH_ERROR_FAILED; + u32TryCount = 0; + while ((tRetVal != FLASH_ERROR_OK) && (u32TryCount++ < 1000000)) + { + u32Temp = s_pFlashDriver_RomApiHeader->FLASH_DRV_HV_Status_Check(); + /* check if finished */ + if (u32Temp == STATUS_HVOP) + { + tRetVal = FLASH_ERROR_FAILED; + } + else + { + tRetVal = FLASH_ERROR_OK; + } + } + + if (tRetVal != FLASH_ERROR_OK) + { + /* erasing timeout, exit */ + *(uint32_t*)(0x00000014U) = *((uint32_t*)0x40020004U); + } + else + { + /* check erasing result */ + u32Temp = s_pFlashDriver_RomApiHeader-> FLASH_DRV_EraseBlock_Clear(); + tRetVal = (u32Temp == STATUS_SUCCESS) ? FLASH_ERROR_OK : FLASH_ERROR_FAILED; + } + } + } + return tRetVal; +} + +/** + * \brief PFlash Driver Function for Erasing + * + * \param pFlashParam flash driver erase parameter + * \return ErrorType + */ +FLASH_StatusType FLASHDRIVER_PFlashEraseSector(FLASH_DRIVER_ParamType *pFlashParam) +{ + uint32_t u32Addr, u32Length; + uint32_t u32TryCount; + FLASH_DRV_ERASESECTOR_CFG_T tFlash_api_cfg; + + FLASH_StatusType tRetVal; + uint32_t u32Temp; + + tRetVal = FLASH_ERROR_OK; + + /* FLASH_DRV_WDG_CFG_T tFlash_wdg_cfg; */ + + u32Addr = pFlashParam->u32Address; + u32Length = pFlashParam->u32Length; + + tRetVal = FLASH_ERROR_OK; + pFlashParam->u32ErrorAddress = 0x0U; + + tRetVal = FLASHDRIVER_LL_PFlashEraseCheck(pFlashParam); + + if (tRetVal == FLASH_ERROR_OK) + { + /* config flash wdog */ + //ConfigFlashWdog(); + + s_pFlashDriver_RomApiHeader->FLASH_DRV_ENABLE_HOLD_CFG(FLASH_AUTO_HOLD_ENABLE); + + + pFlashParam->u32Length = PFLASH_ERASE_SECTOR_SIZE; + + /* loop erase */ + for (pFlashParam->u32Address = u32Addr; pFlashParam->u32Address < u32Addr + u32Length; + pFlashParam->u32Address += PFLASH_ERASE_SECTOR_SIZE) + { + + FLASHDRIVER_PFlashLockSector(pFlashParam->u32Address, 0U); + FLASHDRIVER_GetFlashConfig(pFlashParam->u32Address, &tFlash_api_cfg); + /* start erase */ + __asm(" cpsid i"); + u32Temp = s_pFlashDriver_RomApiHeader->FLASH_DRV_EraseSector(&tFlash_api_cfg, FLASH_API_DISABLE, 0); + __asm(" cpsie i"); + tRetVal = (u32Temp == STATUS_SUCCESS) ? FLASH_ERROR_OK : FLASH_ERROR_FAILED; + + + /* check erase operation valid */ + if (tRetVal != FLASH_ERROR_OK) + { + /* erase operation failed, exit */ + pFlashParam->u32ErrorAddress = pFlashParam->u32Address; + break; + } + else + { + /* check erasing still in progress */ + tRetVal = FLASH_ERROR_FAILED; + u32TryCount = 0; + while ((tRetVal != FLASH_ERROR_OK) && (u32TryCount++ < 100000)) + { + u32Temp = s_pFlashDriver_RomApiHeader->FLASH_DRV_HV_Status_Check(); + /* check if finished */ + if (u32Temp == STATUS_HVOP) + { + tRetVal = FLASH_ERROR_FAILED; + } + else + { + tRetVal = FLASH_ERROR_OK; + } + } + + if (tRetVal != FLASH_ERROR_OK) + { + /* erasing timeout, exit */ + *(uint32_t*)(0x00000014U) = *((uint32_t*)0x40020004U); + break; + } + else + { + /* check erasing result */ + u32Temp = s_pFlashDriver_RomApiHeader->FLASH_DRV_EraseSector_Clear(); + tRetVal = (u32Temp == STATUS_SUCCESS) ? FLASH_ERROR_OK : FLASH_ERROR_FAILED; + + if (tRetVal != FLASH_ERROR_OK) + { + /* erasing failed, exit */ + pFlashParam->u32ErrorAddress = pFlashParam->u32Address; + break; + } + else + { + + if (tRetVal != FLASH_ERROR_OK) + { + /* erasing failed, exit */ + pFlashParam->u32ErrorAddress = pFlashParam->u32Address; + break; + } + else + { + + /* trigger watchdog function */ + if (pFlashParam->wdTriggerFct != ((void *)0)) + { + pFlashParam->wdTriggerFct(pFlashParam->wdTriggerFct_env); + } + } + + + } + } + } + /* lock sector */ + FLASHDRIVER_PFlashLockSector(pFlashParam->u32Address, 1U); + } + } + return tRetVal; +} + +/** + * \brief PFlash Driver Function for Writing + * + * \param pFlashParam flash driver write parameter + * \return ErrorType + */ +FLASH_StatusType FLASHDRIVER_PFlashWrite(FLASH_DRIVER_ParamType *pFlashParam) +{ + uint32_t u32Addr, u32Length, u32DataAddr, u32AlignLen, u32TempLen; + /* uint8_t *pTempBuf; */ + uint32_t u32AlignOffset, u32Index, u32Count; + uint32_t u32TryCount; + FLASH_DRV_PRGM_CFG_T tFlash_api_cfg; + + FLASH_StatusType tRetVal; + uint32_t u32Temp; + + + tRetVal = FLASH_ERROR_OK; + + u32Addr = pFlashParam->u32Address; + u32Length = pFlashParam->u32Length; + + pFlashParam->u32ErrorAddress = 0x0U; + + + tRetVal = FLASHDRIVER_PFlashWriteCheck(pFlashParam); + + if (tRetVal == FLASH_ERROR_OK) + { + /* config flash wdog */ + //ConfigFlashWdog(); + + s_pFlashDriver_RomApiHeader->FLASH_DRV_ENABLE_HOLD_CFG(FLASH_AUTO_HOLD_ENABLE); + + /* align address, write must align to FLASH_PROGRAM_PAGE_MAX_SIZE */ + u32AlignOffset = u32Addr & (PFLASH_PROGRAM_PAGE_MAX_SIZE - 1U); + u32AlignLen = u32Length + u32AlignOffset; + + u32Count = u32AlignLen & (PFLASH_PROGRAM_PAGE_MAX_SIZE - 1U); + + u32Count = u32Count > 0U ? 1U : 0U; + + u32Count += u32AlignLen / PFLASH_PROGRAM_PAGE_MAX_SIZE; + + u32DataAddr = (uint32_t)pFlashParam->pData; + u32TempLen = u32AlignLen; + + for (u32Index = 0U; u32Index < u32Count; u32Index++) + { + /* real write length in this cycle */ + u32TempLen = u32Length + u32AlignOffset; + u32TempLen = u32TempLen >= PFLASH_PROGRAM_PAGE_MAX_SIZE ? PFLASH_PROGRAM_PAGE_MAX_SIZE : u32TempLen; + u32TempLen -= u32AlignOffset; + + pFlashParam->u32Address = u32Addr; + pFlashParam->u32Length = u32TempLen; + + /* unlock sector */ + FLASHDRIVER_PFlashLockSector(pFlashParam->u32Address, 0U); + tFlash_api_cfg.pgff = FLASH_REG_BIT_CFG_DISABLE; + tFlash_api_cfg.dest = pFlashParam->u32Address; + tFlash_api_cfg.size = (pFlashParam->u32Length / 4); /* one data is 4 bytes */ + tFlash_api_cfg.pData = (uint32_t *)u32DataAddr; + tFlash_api_cfg.wdg_tune = WDG_TUNE_DISABLE; + + /* next address and length */ + u32Addr += u32TempLen; + u32DataAddr += u32TempLen; + u32Length -= u32TempLen; + + u32AlignOffset = 0U; + + /* start write */ + __asm(" cpsid i"); + u32Temp = s_pFlashDriver_RomApiHeader->FLASH_DRV_Program(&tFlash_api_cfg, FLASH_API_DISABLE, 0); + __asm(" cpsie i"); + tRetVal = u32Temp == STATUS_SUCCESS ? FLASH_ERROR_OK : FLASH_ERROR_FAILED; + + /* check erase operation valid */ + if (tRetVal != FLASH_ERROR_OK) + { + /* write operation failed, exit */ + pFlashParam->u32ErrorAddress = pFlashParam->u32Address; + break; + } + else + { + /* FLASHDRIVER_LL_Delay(); */ + + /* check write still in progress */ + tRetVal = FLASH_ERROR_FAILED; + u32TryCount = 0; + while ((tRetVal != FLASH_ERROR_OK) && (u32TryCount++ < 10000)) + { + u32Temp = s_pFlashDriver_RomApiHeader->FLASH_DRV_HV_Status_Check(); + /* check if finished */ + if (u32Temp == STATUS_HVOP) + { + tRetVal = FLASH_ERROR_FAILED; + } + else + { + tRetVal = FLASH_ERROR_OK; + } + } + + + if (tRetVal != FLASH_ERROR_OK) + { + /* erasing timeout, exit */ + pFlashParam->u32ErrorAddress = pFlashParam->u32Address; + break; + } + else + { + + /* check write result */ + u32Temp = s_pFlashDriver_RomApiHeader->FLASH_DRV_Program_Clear(); + tRetVal = (u32Temp == STATUS_SUCCESS) ? FLASH_ERROR_OK : FLASH_ERROR_FAILED; + + if (tRetVal != FLASH_ERROR_OK) + { + /* write failed, exit */ + pFlashParam->u32ErrorAddress = pFlashParam->u32Address; + break; + } + else + { + /* trigger watchdog function */ + if (pFlashParam->wdTriggerFct != ((void *)0)) + { + pFlashParam->wdTriggerFct(pFlashParam->wdTriggerFct_env); + } + + } + } + } + + /* lock sector */ + FLASHDRIVER_PFlashLockSector(pFlashParam->u32Address, 1U); + } + } + return tRetVal; +} + +/** + * \brief DFlash Driver Function for Erasing + * + * \param pFlashParam flash driver erase parameter + * \return ErrorType + */ +FLASH_StatusType FLASHDRIVER_DFlashEraseSector(FLASH_DRIVER_ParamType *pFlashParam) +{ + uint32_t u32Addr, u32Length; + uint32_t u32TryCount; + FLASH_DRV_ERASESECTOR_CFG_T tFlash_api_cfg; + FLASH_StatusType tRetVal; + uint32_t u32Temp; + + tRetVal = FLASH_ERROR_OK; + + + u32Addr = pFlashParam->u32Address; + u32Length = pFlashParam->u32Length; + + tRetVal = FLASH_ERROR_OK; + pFlashParam->u32ErrorAddress = 0x0U; + + tRetVal = FLASHDRIVER_LL_DFlashEraseCheck(pFlashParam); + + if (tRetVal == FLASH_ERROR_OK) + { + /* config flash wdog */ + //ConfigFlashWdog(); + + s_pFlashDriver_RomApiHeader->FLASH_DRV_ENABLE_HOLD_CFG(FLASH_AUTO_HOLD_ENABLE); + + + pFlashParam->u32Length = DFLASH_ERASE_SECTOR_SIZE; + + /* loop erase */ + for (pFlashParam->u32Address = u32Addr; pFlashParam->u32Address < u32Addr + u32Length; + pFlashParam->u32Address += DFLASH_ERASE_SECTOR_SIZE) + { + /* unlock data flash */ + FLASHDRIVER_DFlashLockSector(pFlashParam->u32Address, 0U); + + FLASHDRIVER_GetFlashConfig(pFlashParam->u32Address, &tFlash_api_cfg); + /* start erase */ + __asm(" cpsid i"); + u32Temp = s_pFlashDriver_RomApiHeader->FLASH_DRV_EraseSector(&tFlash_api_cfg, FLASH_API_DISABLE, 0); + __asm(" cpsie i"); + tRetVal = (u32Temp == STATUS_SUCCESS) ? FLASH_ERROR_OK : FLASH_ERROR_FAILED; + + + /* check erase operation valid */ + if (tRetVal != FLASH_ERROR_OK) + { + /* erase operation failed, exit */ + pFlashParam->u32ErrorAddress = pFlashParam->u32Address; + break; + } + else + { + /* check erasing still in progress */ + tRetVal = FLASH_ERROR_FAILED; + u32TryCount = 0; + while ((tRetVal != FLASH_ERROR_OK) && (u32TryCount++ < 100000)) + { + u32Temp = s_pFlashDriver_RomApiHeader->FLASH_DRV_HV_Status_Check(); + /* check if finished */ + if (u32Temp == STATUS_HVOP) + { + tRetVal = FLASH_ERROR_FAILED; + } + else + { + tRetVal = FLASH_ERROR_OK; + } + } + + if (tRetVal != FLASH_ERROR_OK) + { + /* erasing timeout, exit */ + pFlashParam->u32ErrorAddress = pFlashParam->u32Address; + break; + } + else + { + /* check erasing result */ + u32Temp = s_pFlashDriver_RomApiHeader->FLASH_DRV_EraseSector_Clear(); + tRetVal = (u32Temp == STATUS_SUCCESS) ? FLASH_ERROR_OK : FLASH_ERROR_FAILED; + + if (tRetVal != FLASH_ERROR_OK) + { + /* erasing failed, exit */ + pFlashParam->u32ErrorAddress = pFlashParam->u32Address; + break; + } + else + { + + if (tRetVal != FLASH_ERROR_OK) + { + /* erasing failed, exit */ + pFlashParam->u32ErrorAddress = pFlashParam->u32Address; + break; + } + else + { + + /* trigger watchdog function */ + if (pFlashParam->wdTriggerFct != ((void *)0)) + { + pFlashParam->wdTriggerFct(pFlashParam->wdTriggerFct_env); + } + } + + + } + } + } + + /* lock data flash */ + FLASHDRIVER_DFlashLockSector(pFlashParam->u32Address, 1U); + } + } + return tRetVal; +} + +/** + * \brief DFlash Driver Function for Writing + * + * \param pFlashParam flash driver write parameter + * \return ErrorType + */ +FLASH_StatusType FLASHDRIVER_DFlashWrite(FLASH_DRIVER_ParamType *pFlashParam) +{ + uint32_t u32Addr, u32Length, u32DataAddr, u32AlignLen, u32TempLen; + /* uint8_t *pTempBuf; */ + uint32_t u32AlignOffset, u32Index, u32Count; + uint32_t u32TryCount; + FLASH_DRV_PRGM_CFG_T tFlash_api_cfg; + + FLASH_StatusType tRetVal; + uint32_t u32Temp; + + tRetVal = FLASH_ERROR_OK; + + u32Addr = pFlashParam->u32Address; + u32Length = pFlashParam->u32Length; + + pFlashParam->u32ErrorAddress = 0x0U; + + + tRetVal = FLASHDRIVER_DFlashWriteCheck(pFlashParam); + + if (tRetVal == FLASH_ERROR_OK) + { + /* config flash wdog */ + //ConfigFlashWdog(); + + s_pFlashDriver_RomApiHeader->FLASH_DRV_ENABLE_HOLD_CFG(FLASH_AUTO_HOLD_ENABLE); + + /* align address, write must align to FLASH_PROGRAM_PAGE_MAX_SIZE */ + u32AlignOffset = u32Addr & (DFLASH_PROGRAM_PAGE_MAX_SIZE - 1U); + u32AlignLen = u32Length + u32AlignOffset; + + u32Count = u32AlignLen & (DFLASH_PROGRAM_PAGE_MAX_SIZE - 1U); + + u32Count = u32Count > 0U ? 1U : 0U; + + u32Count += u32AlignLen / DFLASH_PROGRAM_PAGE_MAX_SIZE; + + u32DataAddr = (uint32_t)pFlashParam->pData; + u32TempLen = u32AlignLen; + + for (u32Index = 0U; u32Index < u32Count; u32Index++) + { + /* real write length in this cycle */ + u32TempLen = u32Length + u32AlignOffset; + u32TempLen = u32TempLen >= DFLASH_PROGRAM_PAGE_MAX_SIZE ? DFLASH_PROGRAM_PAGE_MAX_SIZE : u32TempLen; + u32TempLen -= u32AlignOffset; + + pFlashParam->u32Address = u32Addr; + pFlashParam->u32Length = u32TempLen; + + /* unlock sector */ + FLASHDRIVER_DFlashLockSector(pFlashParam->u32Address, 0U); + tFlash_api_cfg.pgff = FLASH_REG_BIT_CFG_DISABLE; + tFlash_api_cfg.dest = pFlashParam->u32Address; + tFlash_api_cfg.size = (pFlashParam->u32Length / 4); /* one data is 4 bytes */ + tFlash_api_cfg.pData = (uint32_t *)u32DataAddr; + tFlash_api_cfg.wdg_tune = WDG_TUNE_DISABLE; + + /* next address and length */ + u32Addr += u32TempLen; + u32DataAddr += u32TempLen; + u32Length -= u32TempLen; + + u32AlignOffset = 0U; + + /* start write */ + __asm(" cpsid i"); + u32Temp = s_pFlashDriver_RomApiHeader->FLASH_DRV_Program(&tFlash_api_cfg, FLASH_API_DISABLE, 0); + __asm(" cpsie i"); + tRetVal = u32Temp == STATUS_SUCCESS ? FLASH_ERROR_OK : FLASH_ERROR_FAILED; + + /* check erase operation valid */ + if (tRetVal != FLASH_ERROR_OK) + { + /* write operation failed, exit */ + pFlashParam->u32ErrorAddress = pFlashParam->u32Address; + break; + } + else + { + /* FLASHDRIVER_LL_Delay(); */ + + /* check write still in progress */ + tRetVal = FLASH_ERROR_FAILED; + u32TryCount = 0; + while ((tRetVal != FLASH_ERROR_OK) && (u32TryCount++ < 10000)) + { + u32Temp = s_pFlashDriver_RomApiHeader->FLASH_DRV_HV_Status_Check(); + /* check if finished */ + if (u32Temp == STATUS_HVOP) + { + tRetVal = FLASH_ERROR_FAILED; + } + else + { + tRetVal = FLASH_ERROR_OK; + } + } + + + if (tRetVal != FLASH_ERROR_OK) + { + /* erasing timeout, exit */ + pFlashParam->u32ErrorAddress = pFlashParam->u32Address; + break; + } + else + { + /* check write result */ + u32Temp = s_pFlashDriver_RomApiHeader->FLASH_DRV_Program_Clear(); + tRetVal = (u32Temp == STATUS_SUCCESS) ? FLASH_ERROR_OK : FLASH_ERROR_FAILED; + + if (tRetVal != FLASH_ERROR_OK) + { + /* write failed, exit */ + pFlashParam->u32ErrorAddress = pFlashParam->u32Address; + break; + } + else + { + /* trigger watchdog function */ + if (pFlashParam->wdTriggerFct != ((void *)0)) + { + pFlashParam->wdTriggerFct(pFlashParam->wdTriggerFct_env); + } + + } + } + } + /* lock data flash */ + FLASHDRIVER_DFlashLockSector(pFlashParam->u32Address, 1U); + + } + } + return tRetVal; +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_flexcan.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_flexcan.c new file mode 100644 index 0000000..db38f93 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_flexcan.c @@ -0,0 +1,2998 @@ +/** + * @file fc7xxx_driver_flexcan.h + * @author Flagchip + * @brief FC7xxx CAN driver type definition and API + * @version 0.1.0 + * @date 2022-02-20 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ + +/* ******************************************************************************** + * Revision History: + * + * Version Date Author Descriptions + * --------- ---------- ------------ --------------- + * 0.1.0 2024-1-13 Flagchip0112 First version for FC7240 + ******************************************************************************** */ + + + +#include "fc7xxx_driver_flexcan.h" /* include peripheral declarations */ + +#include "interrupt_manager.h" + + +/* ################################################################################## */ +/* ####################################### Macro #################################### */ + + +#ifndef NULL + #define NULL ((void *)0) +#endif + +#define FLEXCAN_FD_INSTANCE_COUNT FLEXCAN_INSTANCE_COUNT /** all support can fd */ + +#define FLEXCAN_MB_NUM 32U /** Every CAN contains message buffer number */ + + +#define FLEXCAN_RX_FIFO_ENABLE STD_OFF +#define FLEXCAN_DMA_ENABLE STD_OFF + +#define FLEXCAN_DET_ERROR_REPORT STD_OFF + + +#define FLEXCAN_DET_ERROR_ID_FUNC_INIT 0x01U +#define FLEXCAN_DET_ERROR_ID_FUNC_MSGCFG 0x02U +#define FLEXCAN_DET_ERROR_ID_FUNC_SETINTERRUPT 0x03U +#define FLEXCAN_DET_ERROR_ID_FUNC_START 0x04U +#define FLEXCAN_DET_ERROR_ID_FUNC_STOP 0x05U +#define FLEXCAN_DET_ERROR_ID_FUNC_TRANSMIT 0x06U +#define FLEXCAN_DET_ERROR_ID_FUNC_RECEIVE 0x07U + + +#define FLEXCAN_DET_ERROR_ID_PARAM_POINTCHECK 0x01U +#define FLEXCAN_DET_ERROR_ID_PARAM_INDEXCHECK 0x02U + + + +/* register word num */ +#define FLEXCAN_MEM_WORD_LEN 0x04U + + +#define MB_RAM_OFFSET 0x80U +#define RXIMR_OFFSET 0x880U +#define RXFIR_TEST_OFFSET 0xA80U +#define MASK_OFFSET 0xAA0U +#define SMBTX_OFFSET 0xAB0U +#define SMBRX0_OFFSET 0xAC0U +#define SMBRX1_OFFSET 0xAD0U +#define FD_SMBTX_OFFSET 0xF28U +#define FD_SMBRX0_OFFSET 0xF70U +#define FD_SMBRX1_OFFSET 0xFB8U +#define ERX_FIFO_OFFSET 0x2000U +#define ERFFEL_OFFSET 0x3000U + + +#define MB_RAM_WORD_NUM 128U +#define RXIMR_WORD_NUM 32U +#define RXFIR_TEST_WORD_NUM 8U +#define MASK_WORD_NUM 4U +#define SMBTX_WORD_NUM 4U +#define SMBRX0_WORD_NUM 4U +#define SMBRX1_WORD_NUM 4U +#define FD_SMBTX_WORD_NUM 18U +#define FD_SMBRX0_WORD_NUM 18U +#define FD_SMBRX1_WORD_NUM 18U +#define ERX_FIFO_WORD_NUM 240U +#define ERFFEL_WORD_NUM 32U + + + +#define USE_CBT_NORMAL + + + +#define TQ_NUM_IPT 2U + +#define TQ_SYNC_NUM 1U + +/* Ctrl1 */ +#define TQ_NUM_CTRL1_MAX 25U +#define TQ_NUM_CTRL1_MIN 8U + +#define CTRL1_PRESDIV_MAX 256U +#define CTRL1_PRESDIV_MIN 1U + +#define CTRL1_RJW_MAX 4U +#define CTRL1_RJW_MIN 1U + +#define CTRL1_PROPSEG_MAX 8U +#define CTRL1_PROPSEG_MIN 1U + +#define CTRL1_PSEG1_MAX 8U +#define CTRL1_PSEG1_MIN 1U + +#define CTRL1_TIMERSEGMENT1_MAX 16U +#define CTRL1_TIMERSEGMENT1_MIN 2U + +#define CTRL1_PSEG2_MAX 8U +#define CTRL1_PSEG2_MIN 2U + + +/* CBT */ +#define TQ_NUM_CBT_MAX 25U /* 80U */ +#define TQ_NUM_CBT_MIN 8U + +#define CBT_PRESDIV_MAX 1024U +#define CBT_PRESDIV_MIN 1U + +#define CBT_RJW_MAX 32U +#define CBT_RJW_MIN 1U + +#define CBT_PROPSEG_MAX 64U +#define CBT_PROPSEG_MIN 1U + +#define CBT_PSEG1_MAX 32U +#define CBT_PSEG1_MIN 1U + +#define CBT_TIMERSEGMENT1_MAX 96U +#define CBT_TIMERSEGMENT1_MIN 2U + +#define CBT_PSEG2_MAX 32U +#define CBT_PSEG2_MIN 2U + + +/* FDCBT */ +#define TQ_NUM_FDCBT_MAX 25U +#define TQ_NUM_FDCBT_MIN 5U + +#define FDCBT_PRESDIV_MAX 1024U +#define FDCBT_PRESDIV_MIN 1U + +#define FDCBT_RJW_MAX 8U +#define FDCBT_RJW_MIN 1U + +#define FDCBT_PROPSEG_MAX 31U +#define FDCBT_PROPSEG_MIN 0U + +#define FDCBT_PSEG1_MAX 8U +#define FDCBT_PSEG1_MIN 1U + +#define FDCBT_TIMERSEGMENT1_MAX 39U +#define FDCBT_TIMERSEGMENT1_MIN 2U + +#define FDCBT_PSEG2_MAX 8U +#define FDCBT_PSEG2_MIN 2U + + + +/* ################################################################################## */ +/* ################################### Type define ################################## */ + + + + + + + +typedef enum +{ + /* RXIDA=0: bitIDE=29-19,EXT=29-1; */ + RXFIFO_FILTERFORMATA = 0, + /* RXIDB_0: bitIDE=29-19,EXT=29-16; RXIDB_1: bitIDE=13-3,EXT=13-0; */ + RXFIFO_FILTERFORMATB = 1, + /* RXIDC_0: bitIDE/EXT=31-24; RXIDC_1: bitIDE/EXT=23-16; RXIDC_2: bitIDE/EXT=15-8; RXIDC_3: bitIDE/EXT=7-0 */ + RXFIFO_FILTERFORMATC = 2 + +} FLEXCAN_RxFifoFilterFormatType; + +typedef struct +{ + FLEXCAN_RxFifoFilterFormatType eFilterFormat; + uint32_t u32RxElementNum; + uint32_t *pRxElementList; +} FLEXCAN_RxFifoFilterType; + + + +/** + * @brief CAN Baudrate setting + * + */ +typedef struct +{ + uint8_t bEnFd; /**< if enable can FD, set 1U */ + uint8_t bEnBrs; /**< if enable can BRS, set 1U */ + FLEXCAN_DataWidthType eMbDataWidth; /**< Message Buffer Data Width */ + + FLEXCAN_BaudClkType eClkSrcHz; /**< clock source HZ */ + FLEXCAN_BaudType eBaudrate; /**< normal bit rate */ + FLEXCAN_BaudType eDataBaud; /**< can fd data bit rate */ + + uint32_t u32Ctrl1; /**< ctrl1 register value */ + uint32_t u32Cbt; /**< cbt register value */ + uint32_t u32FdCtrl; /**< fdctrl register value */ + uint32_t u32FdCbt; /**< fdcbt register value */ + +} FLEXCAN_BaudCfgType; + + + +/** + * @brief CAN setting configuration + * + */ +typedef struct +{ + uint8_t bEnableFd; /**< if enable can FD, set 1U */ + uint8_t bEnableFifo; /**< if enable can fifo, set 1U */ + uint8_t bEnableDMA; /**< if enable can dma, set 1U */ + uint8_t bEnableErrInt; /**< if enable can error interrupt, set 1U */ + uint8_t bEnableFifoInt; /**< if enable can fifo interrupt, set 1U */ + uint8_t bEnableTxMBInt; /**< if enable can Tx MB interrupt, set 1U */ + uint8_t bEnableRxMBInt; /**< if enable can Rx MB interrupt, set 1U */ + uint8_t u8EnhancedFifoDmaWM;/**< The watermark for DMA in CANFD FIFO mode */ + uint8_t u8RxFifoCnt; /**< can receive start message buffer index */ + uint8_t u8RxMbStart1; /**< can receive start message buffer index */ + uint8_t u8RxMbCnt1; /**< can receive message buffer count */ + uint8_t u8TxMbStart1; /**< can transmit start message buffer index */ + uint8_t u8TxMbCnt1; /**< can receive message buffer count */ + FLEXCAN_DataWidthType eMbDataWidth; /**< Message Buffer Data Width */ + FLEXCAN_RxMsgType *pRxBuf; /**< receive buffer address, length same to u8RxFilterCnt, must global array */ +} FLEXCAN_SettingType; + +/** + * @brief CAN Operation Sequence + * + */ +typedef enum +{ + FLEXCAN_SEQUENCE_VAR_NOINIT, /**< FLEXCAN_SEQUENCE_DEINIT means CAN variables data is not initialed */ + FLEXCAN_SEQUENCE_DEINIT, /**< FLEXCAN_SEQUENCE_DEINIT means CAN driver is not initialed */ + FLEXCAN_SEQUENCE_NOTSTART, /**< FLEXCAN_SEQUENCE_NOTSTART means can driver initialed and not start */ + FLEXCAN_SEQUENCE_STARTED /**< FLEXCAN_SEQUENCE_STARTED means can driver started */ +} FLEXCAN_SequenceType; + + +/** + * @brief Baud-rate clock and divider + * + */ +typedef struct +{ + FLEXCAN_BaudClkType eClkHz; /**< Clock Hz for baudrate */ + FLEXCAN_BaudType eBaudrate; /**< Normal bit baudrate */ + uint32_t u32Presdiv; /**< Presdiv for can */ + uint32_t u32Propseg; /**< Propseg for can */ + uint32_t u32Pseg1; /**< Pseg1 for can */ + uint32_t u32Pseg2; /**< Pseg2 for can */ + uint32_t u32Rjw; /**< RJW for can */ +} FLEXCAN_BaudRegType; + + +/* ################################################################################## */ +/* ############################# Local Const Variables ############################## */ + +/* CAN Instance */ +static FLEXCAN_Type *const s_aFlexCan_InstanceTable[FLEXCAN_INSTANCE_COUNT] = +{ + FLEXCAN0, + FLEXCAN1, + FLEXCAN2, + FLEXCAN3 +}; + +/* Normal bit table */ +static const FLEXCAN_BaudRegType s_aFlexCan_NormalBaudDividerTable[] = +{ + /* clock source hz baudrate presdiv propseg pseg1 pseg2 rjw */ + { FLEXCAN_BAUDCLK_HZ_16M, FLEXCAN_BAUD_500K, 2, 8, 4, 3, 2 }, + { FLEXCAN_BAUDCLK_HZ_24M, FLEXCAN_BAUD_100K, 12, 7, 6, 6, 1 }, + { FLEXCAN_BAUDCLK_HZ_24M, FLEXCAN_BAUD_125K, 12, 5, 5, 5, 1 }, + { FLEXCAN_BAUDCLK_HZ_24M, FLEXCAN_BAUD_250K, 8, 5, 3, 3, 1 }, + { FLEXCAN_BAUDCLK_HZ_24M, FLEXCAN_BAUD_500K, 4, 5, 3, 3, 1 }, + { FLEXCAN_BAUDCLK_HZ_24M, FLEXCAN_BAUD_800K, 3, 5, 2, 2, 1 }, + { FLEXCAN_BAUDCLK_HZ_24M, FLEXCAN_BAUD_1M, 2, 5, 3, 3, 1 }, + { FLEXCAN_BAUDCLK_HZ_24M, FLEXCAN_BAUD_2M, 1, 5, 3, 3, 1 }, + { FLEXCAN_BAUDCLK_HZ_48M, FLEXCAN_BAUD_100K, 32, 8, 3, 3, 1 }, + { FLEXCAN_BAUDCLK_HZ_48M, FLEXCAN_BAUD_125K, 24, 7, 4, 4, 1 }, + { FLEXCAN_BAUDCLK_HZ_48M, FLEXCAN_BAUD_250K, 24, 3, 2, 2, 1 }, + { FLEXCAN_BAUDCLK_HZ_48M, FLEXCAN_BAUD_500K, 6, 7, 4, 4, 1 }, + { FLEXCAN_BAUDCLK_HZ_48M, FLEXCAN_BAUD_800K, 4, 8, 3, 3, 1 }, + { FLEXCAN_BAUDCLK_HZ_48M, FLEXCAN_BAUD_1M, 3, 7, 4, 4, 1 }, + { FLEXCAN_BAUDCLK_HZ_48M, FLEXCAN_BAUD_2M, 2, 5, 3, 3, 1 }, + { FLEXCAN_BAUDCLK_HZ_120M, FLEXCAN_BAUD_100K, 80, 8, 3, 3, 1 }, + { FLEXCAN_BAUDCLK_HZ_120M, FLEXCAN_BAUD_125K, 64, 8, 3, 3, 1 }, + { FLEXCAN_BAUDCLK_HZ_120M, FLEXCAN_BAUD_250K, 32, 8, 3, 3, 1 }, + { FLEXCAN_BAUDCLK_HZ_120M, FLEXCAN_BAUD_500K, 16, 8, 3, 3, 3 }, + { FLEXCAN_BAUDCLK_HZ_120M, FLEXCAN_BAUD_800K, 15, 5, 2, 2, 1 }, + { FLEXCAN_BAUDCLK_HZ_120M, FLEXCAN_BAUD_1M, 8, 8, 3, 3, 1 }, + { FLEXCAN_BAUDCLK_HZ_120M, FLEXCAN_BAUD_2M, 4, 8, 3, 3, 1 }, + { FLEXCAN_BAUDCLK_HZ_150M, FLEXCAN_BAUD_500K, 20, 8, 3, 3, 1 }, + { FLEXCAN_BAUDCLK_HZ_150M, FLEXCAN_BAUD_1M, 10, 8, 3, 3, 1 }, + { FLEXCAN_BAUDCLK_HZ_150M, FLEXCAN_BAUD_2M, 5, 8, 3, 3, 1 }, + +}; + +/* Data bit table */ +static const FLEXCAN_BaudRegType s_aFlexCan_DataBaudDividerTable[] = +{ + /* clock source hz baudrate presdiv propseg pseg1 pseg2 rjw */ + { FLEXCAN_BAUDCLK_HZ_16M, FLEXCAN_BAUD_2M, 1, 3, 2, 2, 1 }, + { FLEXCAN_BAUDCLK_HZ_24M, FLEXCAN_BAUD_1M, 2, 5, 3, 3, 1 }, + { FLEXCAN_BAUDCLK_HZ_24M, FLEXCAN_BAUD_2M, 1, 5, 3, 3, 1 }, + { FLEXCAN_BAUDCLK_HZ_24M, FLEXCAN_BAUD_3M, 1, 3, 2, 2, 1 }, + { FLEXCAN_BAUDCLK_HZ_48M, FLEXCAN_BAUD_1M, 3, 7, 4, 4, 1 }, + { FLEXCAN_BAUDCLK_HZ_48M, FLEXCAN_BAUD_2M, 2, 5, 3, 3, 1 }, + { FLEXCAN_BAUDCLK_HZ_48M, FLEXCAN_BAUD_3M, 1, 7, 4, 4, 1 }, + { FLEXCAN_BAUDCLK_HZ_48M, FLEXCAN_BAUD_4M, 1, 5, 3, 3, 1 }, + { FLEXCAN_BAUDCLK_HZ_48M, FLEXCAN_BAUD_6M, 1, 3, 2, 2, 1 }, + { FLEXCAN_BAUDCLK_HZ_120M, FLEXCAN_BAUD_1M, 8, 8, 3, 3, 1 }, + { FLEXCAN_BAUDCLK_HZ_120M, FLEXCAN_BAUD_2M, 4, 8, 3, 3, 1 }, + { FLEXCAN_BAUDCLK_HZ_120M, FLEXCAN_BAUD_3M, 4, 5, 2, 2, 1 }, + { FLEXCAN_BAUDCLK_HZ_120M, FLEXCAN_BAUD_4M, 3, 5, 2, 2, 1 }, + { FLEXCAN_BAUDCLK_HZ_120M, FLEXCAN_BAUD_5M, 2, 5, 3, 3, 1 }, + { FLEXCAN_BAUDCLK_HZ_120M, FLEXCAN_BAUD_6M, 2, 5, 2, 2, 1 }, + { FLEXCAN_BAUDCLK_HZ_120M, FLEXCAN_BAUD_8M, 1, 8, 3, 3, 1 }, + { FLEXCAN_BAUDCLK_HZ_150M, FLEXCAN_BAUD_1M, 10, 8, 3, 3, 1 }, + { FLEXCAN_BAUDCLK_HZ_150M, FLEXCAN_BAUD_2M, 5, 8, 3, 3, 1 }, + { FLEXCAN_BAUDCLK_HZ_150M, FLEXCAN_BAUD_3M, 5, 5, 2, 2, 1 }, + { FLEXCAN_BAUDCLK_HZ_150M, FLEXCAN_BAUD_5M, 2, 8, 3, 3, 1 } + +}; + + +/* ################################################################################## */ +/* ################################ Local Variables ################################# */ + + +/* sequence var */ +static FLEXCAN_SequenceType s_aCurrentSequence[FLEXCAN_INSTANCE_COUNT] = {FLEXCAN_SEQUENCE_VAR_NOINIT}; + + +/* message buffer word length, default pCan is 16bytes, 4words */ +/* static uint8_t s_aFlexCan_DataLen[FLEXCAN_INSTANCE_COUNT]; */ + +/* pCan message buffer used count stored */ +/* static FLEXCAN_MBConfigType s_aFlexCan_MBCfg_Table[FLEXCAN_INSTANCE_COUNT]; */ + +/* can setting */ +static FLEXCAN_SettingType s_aFlexCan_Setting_Table[FLEXCAN_INSTANCE_COUNT]; + + +/* store notify callback function point */ +static FLEXCAN_ErrorInterruptCallBackType s_aFlexCan_ErrorNotifyTable[FLEXCAN_INSTANCE_COUNT]; +static FLEXCAN_TxInterruptCallBackType s_aFlexCan_TxNotifyTable[FLEXCAN_INSTANCE_COUNT]; +static FLEXCAN_RxInterruptCallBackType s_aFlexCan_RxNotifyTable[FLEXCAN_INSTANCE_COUNT]; +static FLEXCAN_RxInterruptCallBackType s_aFlexCan_RxFifoNotifyTable[FLEXCAN_INSTANCE_COUNT]; + +/* check every pCan instance whether is used */ +/* static FLEXCAN_RxMsgType const * s_aFlexCan_RxBufList[FLEXCAN_INSTANCE_COUNT]; */ + +/* check every pCan instance whether is used */ +static uint8_t s_aFlexCan_CanUsed[FLEXCAN_INSTANCE_COUNT]; + +#if FLEXCAN_DET_ERROR_REPORT == STD_ON +typedef struct +{ + uint8_t u8FunctionID; + uint8_t u8ParameterID; +} FLEXCAN_DetErrorType; + +static FLEXCAN_DetErrorType s_tFlexCan_DetErrorId; +#endif + + +/* ################################################################################## */ +/* ########################### Local Prototype Functions ############################ */ + + + + +/* ################################################################################## */ +/* ########################### Global Prototype Functions ########################### */ + + +/* ################################################################################## */ +/* ################################ Local Functions ################################# */ + +#if FLEXCAN_DET_ERROR_REPORT == STD_ON +static void FLEXCAN_ReportDet(uint8_t funcId, uint8_t paramId) +{ + s_tFlexCan_DetErrorId.u8FunctionID = funcId; + s_tFlexCan_DetErrorId.u8ParameterID = paramId; + + while (1) + { + + } + +} + +#endif + + +#if FLEXCAN_CHECK_PARAMETERS == STD_ON +/** + * @brief Check FLEXCAN instance + * + * @param u8CanIndex Can Index, must less than FLEXCAN_INSTANCE_COUNT + * @return FLEXCAN_ERROR_OK is OK + */ +LOCAL_INLINE FLEXCAN_ErrorType FLEXCAN_LL_CheckInstance(uint8_t u8CanIndex) +{ + FLEXCAN_ErrorType tRetVal; + + if (u8CanIndex < FLEXCAN_INSTANCE_COUNT) + { + tRetVal = FLEXCAN_ERROR_OK; + } + else + { + tRetVal = FLEXCAN_ERROR_INVALID_PARAM; + } + + return tRetVal; +} + +#endif + +/** + * @brief Check FLEXCAN Fd Support instance + * + * @param u8CanIndex Can Index, must less than FLEXCAN_INSTANCE_COUNT + * @return FLEXCAN_ERROR_OK is OK + */ +LOCAL_INLINE FLEXCAN_ErrorType FLEXCAN_LL_CheckFdInstance(uint8_t u8CanIndex) +{ + FLEXCAN_ErrorType tRetVal; + + if (u8CanIndex < FLEXCAN_FD_INSTANCE_COUNT) + { + tRetVal = FLEXCAN_ERROR_OK; + } + else + { + tRetVal = FLEXCAN_ERROR_INVALID_PARAM; + } + + return tRetVal; +} + + +/** + * @brief Initial embedded can ram area + * + * @param u8CanIndex CanIndex, Must less than FLEXCAN_INSTANCE_COUNT + */ +/* Every CAN contains message buffer number */ +#define FLEXCAN_MB_NUM_PTRS {32U,32U,32U,32U} +/* Number of instances of the FLEXCAN FD module. */ +#define FLEXCAN_FD_SUPPORT_PTRS {1U,1U,1U,1U} +/* Support Gate */ +#define FLEXCAN_GATE_BUFNUM_PTRS {0U,0U,0U,0U} +/* Support pretend network */ +#define FLEXCAN_PNET_SUPPORT_PTRS {1U,1U,1U,1U} + +/* IFlag1...IFlagn, IMask1...IMaskn */ +#define FLEXCAN_IFLAGMASK_NUM_PTRS {1U,1U,1U,1U} +#define FLEXCAN_IFLAGMASK_NUM_MAX 1U + +/* MBDSR0..MBDSRn */ +#define FLEXCAN_FD_DATALEN_RANGE_NUM_PTRS {1U,1U,1U,1U} +#define FLEXCAN_FD_DATALEN_RANGE_NUM_MAX 1U + +/* Enhanced Rx FIFO */ +#define FLEXCAN_ENHANCED_FIFO_ELEMENT_MAX_PTRS {32U,32U,32U,32U} +#define FLEXCAN_ENHANCED_FIFO_DEPTH_PTRS {12U,12U,12U,12U} + +static const uint8_t s_aFlexCanFd_SupportTable[FLEXCAN_INSTANCE_COUNT] = FLEXCAN_FD_SUPPORT_PTRS; +static const uint8_t s_aFlexCanEnhancedElementNums[FLEXCAN_INSTANCE_COUNT] = FLEXCAN_ENHANCED_FIFO_ELEMENT_MAX_PTRS; +static const uint8_t s_aFlexCanMbNums[FLEXCAN_INSTANCE_COUNT] = FLEXCAN_MB_NUM_PTRS; +static const uint8_t s_aFlexCanDataLenNums[FLEXCAN_INSTANCE_COUNT] = FLEXCAN_FD_DATALEN_RANGE_NUM_PTRS; +static const uint8_t s_aFlexCanEnhancedDepthp[FLEXCAN_INSTANCE_COUNT] = FLEXCAN_ENHANCED_FIFO_DEPTH_PTRS; +static const uint8_t s_aFlexCanGateNumSizes[FLEXCAN_INSTANCE_COUNT] = FLEXCAN_GATE_BUFNUM_PTRS; +static const uint8_t s_aFlexCanIflagMaskSizes[FLEXCAN_INSTANCE_COUNT] = FLEXCAN_IFLAGMASK_NUM_PTRS; +static const uint8_t s_aFlexCanPnetSupportTable[FLEXCAN_INSTANCE_COUNT]=FLEXCAN_PNET_SUPPORT_PTRS; + +#define FLEXCAN_MB_RAM_OFFSET 0x80U /* length is MB_Num*4*4 */ +#define FLEXCAN_RXIMR_OFFSET 0x880U /* Length is MB_Num*4 */ +#define FLEXCAN_RXFIR_TEST_OFFSET 0xA80U +#define FLEXCAN_RXFIR_TEST_LEN 0x18U /* Length is 0x18 */ +#define FLEXCAN_MASK_OFFSET 0xAA0U +#define FLEXCAN_MASK_LEN 0x10U /* Length is 0x10, RX14MASK, RX15MASK,RXMGMAXK, and RSFGMASK */ +#define FLEXCAN_SMBTX_OFFSET 0xAB0U +#define FLEXCAN_SMBTX_LEN 0x10U /* Length is 0x10 */ +#define FLEXCAN_SMBRX0_OFFSET 0xAC0U +#define FLEXCAN_SMBRX0_LEN 0x10U /* Length is 0x10 */ +#define FLEXCAN_SMBRX1_OFFSET 0xAD0U +#define FLEXCAN_SMBRX1_LEN 0x10U /* Length is 0x10 */ +#define FLEXCAN_FD_SMBTX_OFFSET 0xF28U +#define FLEXCAN_FD_SMBTX_LEN 0x48U /* Length is 0x48 */ +#define FLEXCAN_FD_SMBRX0_OFFSET 0xF70U +#define FLEXCAN_FD_SMBRX0_LEN 0x48U /* Length is 0x48 */ +#define FLEXCAN_FD_SMBRX1_OFFSET 0xFB8U +#define FLEXCAN_FD_SMBRX1_LEN 0x48U /* Length is 0x48 */ +#define FLEXCAN_ERX_FIFO_OFFSET 0x2000U /* Length is Depth*20(fd) or Depth*6(non-fd) */ +#define FLEXCAN_ERX_FIFO_FD_WIDTH 20U +#define FLEXCAN_ERX_FIFO_NONFD_WIDTH 6U +#define FLEXCAN_ERFFEL_OFFSET 0x3000U /* Length is element_num*4 */ +#define FLEXCAN_GATEBUF_OFFSET 0x1A10U /* Length is gatebuf_num*2*4 */ + + + +static void FLEXCAN_LL_EmbededRam_Init(uint8_t u8CanIndex) +{ + volatile uint32_t u32Index ; + volatile uint32_t ramAddr; + FLEXCAN_Type *pCan; + + pCan = (FLEXCAN_Type *)s_aFlexCan_InstanceTable[(uint8_t)u8CanIndex]; + + for (u32Index = 0U; u32Index < s_aFlexCanMbNums[u8CanIndex]*4U; u32Index++) + { + ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_MB_RAM_OFFSET, u32Index * 4U); + FLEXCAN_REG32_CONTENT(ramAddr) = 0U; + } + + for (u32Index = 0U; u32Index < s_aFlexCanMbNums[u8CanIndex]; u32Index++) + { + ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_RXIMR_OFFSET, u32Index * 4U); + FLEXCAN_REG32_CONTENT(ramAddr) = 0U; + } + + for (u32Index = 0U; u32Index < FLEXCAN_RXFIR_TEST_LEN; u32Index+=4U) + { + ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_RXFIR_TEST_OFFSET, u32Index); + FLEXCAN_REG32_CONTENT(ramAddr) = 0U; + } + + for (u32Index = 0U; u32Index < FLEXCAN_MASK_LEN; u32Index+=4U) + { + ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_MASK_OFFSET, u32Index); + FLEXCAN_REG32_CONTENT(ramAddr) = 0U; + } + + for (u32Index = 0U; u32Index < FLEXCAN_SMBTX_LEN; u32Index+=4U) + { + ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_SMBTX_OFFSET, u32Index); + FLEXCAN_REG32_CONTENT(ramAddr) = 0U; + } + + for (u32Index = 0U; u32Index < FLEXCAN_SMBRX0_LEN; u32Index+=4U) + { + ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_SMBRX0_OFFSET, u32Index); + FLEXCAN_REG32_CONTENT(ramAddr) = 0U; + } + + for (u32Index = 0U; u32Index < FLEXCAN_SMBRX1_LEN; u32Index+=4U) + { + ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_SMBRX1_OFFSET, u32Index); + FLEXCAN_REG32_CONTENT(ramAddr) = 0U; + } + + /* only can fd support these memory */ + if(s_aFlexCanFd_SupportTable[u8CanIndex]) + { + for (u32Index = 0U; u32Index < FLEXCAN_FD_SMBTX_LEN; u32Index+=4U) + { + ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_FD_SMBTX_OFFSET, u32Index); + FLEXCAN_REG32_CONTENT(ramAddr) = 0U; + } + + for (u32Index = 0U; u32Index < FLEXCAN_FD_SMBRX0_LEN; u32Index+=4U) + { + ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_FD_SMBRX0_OFFSET, u32Index); + FLEXCAN_REG32_CONTENT(ramAddr) = 0U; + } + + for (u32Index = 0U; u32Index < FLEXCAN_FD_SMBRX1_LEN; u32Index+=4U) + { + ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_FD_SMBRX1_OFFSET, u32Index); + FLEXCAN_REG32_CONTENT(ramAddr) = 0U; + } + } + + /* only enhanced rx fifo support these memory */ + if(s_aFlexCanEnhancedDepthp[u8CanIndex]) + { + /** initial rx fifo with fd */ + for (u32Index = 0U; u32Index < s_aFlexCanEnhancedDepthp[u8CanIndex]*4U*FLEXCAN_ERX_FIFO_FD_WIDTH; u32Index+=4U) + { + ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_ERX_FIFO_OFFSET, u32Index ); + FLEXCAN_REG32_CONTENT(ramAddr) = 0U; + } + + /* enhanced fifo elements */ + for (u32Index = 0U; u32Index < s_aFlexCanEnhancedElementNums[u8CanIndex]; u32Index++) + { + ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_ERFFEL_OFFSET, u32Index * 4U); + FLEXCAN_REG32_CONTENT(ramAddr) = 0U; + } + } + + /* gate buffer */ + if(s_aFlexCanGateNumSizes[u8CanIndex]) + { + for (u32Index = 0U; u32Index < s_aFlexCanGateNumSizes[u8CanIndex]*2U; u32Index++) + { + ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FLEXCAN_GATEBUF_OFFSET, u32Index * 4U); + FLEXCAN_REG32_CONTENT(ramAddr) = 0U; + } + } +} + +/* +static void FLEXCAN_LL_EmbededRam_Init(uint8_t u8CanIndex) +{ + volatile uint32_t u8Index ; + volatile uint32_t ramAddr; + FLEXCAN_Type *pCan; + + pCan = (FLEXCAN_Type *)s_aFlexCan_InstanceTable[u8CanIndex]; + + for (u8Index = 0U; u8Index < MB_RAM_WORD_NUM; u8Index++) + { + ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, MB_RAM_OFFSET, u8Index * FLEXCAN_MEM_WORD_LEN); + FLEXCAN_REG32_CONTENT(ramAddr) = 0U; + } + + for (u8Index = 0U; u8Index < RXIMR_WORD_NUM; u8Index++) + { + ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, RXIMR_OFFSET, u8Index * FLEXCAN_MEM_WORD_LEN); + FLEXCAN_REG32_CONTENT(ramAddr) = 0U; + } + + for (u8Index = 0U; u8Index < RXFIR_TEST_WORD_NUM; u8Index++) + { + ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, RXFIR_TEST_OFFSET, u8Index * FLEXCAN_MEM_WORD_LEN); + FLEXCAN_REG32_CONTENT(ramAddr) = 0U; + } + + + for (u8Index = 0U; u8Index < MASK_WORD_NUM; u8Index++) + { + ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, MASK_OFFSET, u8Index * FLEXCAN_MEM_WORD_LEN); + FLEXCAN_REG32_CONTENT(ramAddr) = 0U; + } + + for (u8Index = 0U; u8Index < SMBTX_WORD_NUM; u8Index++) + { + ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, SMBTX_OFFSET, u8Index * FLEXCAN_MEM_WORD_LEN); + FLEXCAN_REG32_CONTENT(ramAddr) = 0U; + } + + for (u8Index = 0U; u8Index < SMBRX0_WORD_NUM; u8Index++) + { + ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, SMBRX0_OFFSET, u8Index * FLEXCAN_MEM_WORD_LEN); + FLEXCAN_REG32_CONTENT(ramAddr) = 0U; + } + + for (u8Index = 0U; u8Index < SMBRX1_WORD_NUM; u8Index++) + { + ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, SMBRX1_OFFSET, u8Index * FLEXCAN_MEM_WORD_LEN); + FLEXCAN_REG32_CONTENT(ramAddr) = 0U; + } + + // can fd only + if (FLEXCAN_LL_CheckFdInstance(u8CanIndex) == FLEXCAN_ERROR_OK) + { + for (u8Index = 0U; u8Index < FD_SMBTX_WORD_NUM; u8Index++) + { + ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FD_SMBTX_OFFSET, u8Index * FLEXCAN_MEM_WORD_LEN); + FLEXCAN_REG32_CONTENT(ramAddr) = 0U; + } + + for (u8Index = 0U; u8Index < FD_SMBRX0_WORD_NUM; u8Index++) + { + ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FD_SMBRX0_OFFSET, u8Index * FLEXCAN_MEM_WORD_LEN); + FLEXCAN_REG32_CONTENT(ramAddr) = 0U; + } + + for (u8Index = 0U; u8Index < FD_SMBRX1_WORD_NUM; u8Index++) + { + ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, FD_SMBRX1_OFFSET, u8Index * FLEXCAN_MEM_WORD_LEN); + FLEXCAN_REG32_CONTENT(ramAddr) = 0U; + } + + + // initial rx fifo + for (u8Index = 0U; u8Index < ERX_FIFO_WORD_NUM; u8Index++) + { + ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, ERX_FIFO_OFFSET, u8Index * FLEXCAN_MEM_WORD_LEN); + FLEXCAN_REG32_CONTENT(ramAddr) = 0U; + } + + for (u8Index = 0U; u8Index < ERFFEL_WORD_NUM; u8Index++) + { + ramAddr = FLEXCAN_REGISTER_WITHOFFSET(pCan, ERFFEL_OFFSET, u8Index * FLEXCAN_MEM_WORD_LEN); + FLEXCAN_REG32_CONTENT(ramAddr) = 0U; + } + + } + +} +*/ + + +/** + * @brief This Function is used to receive Special Message Buffer data + * + * @param u8CanIndex Can Index, Must less than FLEXCAN_INSTANCE_COUNT + * @param u8RealMbIndex, message buffer index 0...31, if fifo enable, always 0 + * @param u8MbDataLen, message buffer data length + * @param pRxMsg, received data buffer + * @return 0 means no data, others means received data + */ +static uint8_t FLEXCAN_LL_ReceiveMb(uint8_t u8CanIndex, uint8_t u8RealMbIndex, uint8 bEnFifo, uint8_t u8MbDataLen, FLEXCAN_RxMsgType *const pRxMsg) +{ + + FLEXCAN_Type *pCan; + uint32_t u32Status; + + uint32_t *pSrc; + uint32_t *pDest; + uint8_t u8Index; + + uint32_t u32TempAddr; + uint32_t u32WordLen; + uint8 u8IflagIndex; + + pCan = (FLEXCAN_Type *)s_aFlexCan_InstanceTable[u8CanIndex]; + + if (bEnFifo != 0U) + { + u8IflagIndex = 5U; /* IFLAG1[BIT5] (Frames available in Rx FIFO) is asserted when there is at least one frame available to be read from the FIFO */ + u8RealMbIndex = 0U; /* fifo received always in MB0 */ + } + else + { + u8IflagIndex = u8RealMbIndex; + } + + pRxMsg->u32DataLen = 0U; + + u32Status = FLEXCAN_HWA_GetFlag1NoFifoFlag(pCan, (uint32_t)u8IflagIndex); + + if (u32Status != 0U) + { + pRxMsg->u8CanIndex = u8CanIndex; + pRxMsg->u8MbIndex = u8RealMbIndex; + + /* message buffer 1th word */ + u32TempAddr = (uint32_t)FLEXCAN_MB_WORDN_ADDR(&(pCan->RAM[0U]), u8RealMbIndex, u8MbDataLen, 0U); + + pRxMsg->bEnFd = (uint8_t)((FLEXCAN_MB_EDL_GET(u32TempAddr) == 0U) ? 0U : 1U); + pRxMsg->bEnBrs = (uint8_t)((FLEXCAN_MB_BRS_GET(u32TempAddr) == 0U) ? 0U : 1U); + + + pRxMsg->u32DataLen = FLEXCAN_MB_DLC_GET(u32TempAddr); + pRxMsg->u32DataLen = FLEXCAN_DlcToDataLen(pRxMsg->u32DataLen); + pRxMsg->eFrameType = (FLEXCAN_IdType)(FLEXCAN_MB_IDE_GET(u32TempAddr)); + + /* message buffer 2th word */ + u32TempAddr = (uint32_t)FLEXCAN_MB_WORDN_ADDR(&(pCan->RAM[0U]), u8RealMbIndex, u8MbDataLen, 4U); + + if (pRxMsg->eFrameType) + { + pRxMsg->u32CanId = FLEXCAN_MB_EXTID_GET(u32TempAddr); + } + else + { + pRxMsg->u32CanId = FLEXCAN_MB_STDID_GET(u32TempAddr); + } + + + + pDest = (uint32_t *)pRxMsg->aData; + /* message buffer 3th word */ + pSrc = (uint32_t *)FLEXCAN_MB_WORDN_ADDR(&(pCan->RAM[0U]), u8RealMbIndex, u8MbDataLen, 8U); + + + u32WordLen = pRxMsg->u32DataLen / 4U + (pRxMsg->u32DataLen % 4U > 0U ? 1U : 0U); + + for (u8Index = 0U; u8Index < u32WordLen; u8Index++) + { + /* big endian to little endian */ + REV_BYTES_32(pSrc[u8Index], pDest[u8Index]); + } + + FLEXCAN_HWA_UnlockMbNoFifoFlag(pCan, (uint32_t)u8IflagIndex); + + } + else + { + } + + return pRxMsg->u32DataLen > 0U; +} + + +/** + * @brief This Function is used to receive Enhance FIFO Buffer data + * + * @param u8CanIndex Can Index, Must less than FLEXCAN_INSTANCE_COUNT + * @param pRxMsg, received data buffer + * @return 0 means no data, others means received data + */ +static uint8_t FLEXCAN_LL_ReceiveEnhanceFifo(uint8_t u8CanIndex, FLEXCAN_RxMsgType *const pRxMsg) +{ + uint32_t u32Status; + + volatile uint32_t *pSrc; + volatile uint32_t *pDest; + uint8_t u8Index; + FLEXCAN_Type *pCan; + + pRxMsg->u32DataLen = 0U; + + #if FLEXCAN_CHECK_PARAMETERS == STD_ON + if (FLEXCAN_LL_CheckFdInstance(u8CanIndex) == FLEXCAN_ERROR_OK) + { + #endif + pCan = (FLEXCAN_Type *)s_aFlexCan_InstanceTable[u8CanIndex]; + + /* The enhanced Rx FIFO has a watermark that is configured by setting EFRCR[ERFWM]. + * If EFRCR[ERFWM] is set, the CPU is notified only if a minimum number of messages is stored in the FIFO. + * When the number of stored messages is greater than the value in EFRCR[ERFWM], ERFSR[ERFWMI] is set by the hardware. */ + + /* check fd fifo data available */ + u32Status = FLEXCAN_HWA_ERFSRGetEnhancedFifoFlag(pCan, FLEXCAN_ERFSR_ERFDA_SHIFT, FLEXCAN_ERFSR_ERFDA_MASK); + + if (u32Status != 0U) + { + + pRxMsg->u8CanIndex = u8CanIndex; + pRxMsg->u8MbIndex = 0U; + + pRxMsg->bEnFd = (uint8_t)(FLEXCAN_EFIFOMB_EDL_GET()); + pRxMsg->bEnBrs = (uint8_t)(FLEXCAN_EFIFOMB_BRS_GET()); + + + pRxMsg->u32DataLen = FLEXCAN_EFIFOMB_DLC_GET(); + pRxMsg->u32DataLen = (uint8_t)(FLEXCAN_DlcToDataLen(pRxMsg->u32DataLen)); + pRxMsg->eFrameType = (FLEXCAN_IdType)(FLEXCAN_EFIFOMB_IDE_GET()); + + + if (pRxMsg->eFrameType) + { + pRxMsg->u32CanId = FLEXCAN_EFIFOMB_EXTID_GET(); + } + else + { + pRxMsg->u32CanId = FLEXCAN_EFIFOMB_STDID_GET(); + } + + pDest = (uint32_t *)pRxMsg->aData; + /* message buffer 3th word */ + pSrc = (volatile uint32_t *)FLEXCAN_EFIFOMB_DATAADDR_GET(0U); + + + //u32WordLen = pRxMsg->u32DataLen / 4U + (pRxMsg->u32DataLen % 4U > 0U ? 1U : 0U); + + for (u8Index = 0U; u8Index < 18U; u8Index++) + { + /* big endian to little endian */ + REV_BYTES_32(pSrc[u8Index], pDest[u8Index]); + } + + //u32WordLen = FLEXCAN_EFIFOMB_HRTIMESTAMP_GET(u32WordLen); /* Read TIMER to unlock message buffers */ + + /* clear fifo data available status */ + FLEXCAN_HWA_ERFSRClearEnhancedFifoFlag(pCan, FLEXCAN_ERFSR_ERFDA_MASK); + + /* get fifo data available status */ + u32Status = FLEXCAN_HWA_ERFSRGetEnhancedFifoFlag(pCan, FLEXCAN_ERFSR_ERFDA_SHIFT, FLEXCAN_ERFSR_ERFDA_MASK); + + } + #if FLEXCAN_CHECK_PARAMETERS == STD_ON + } + #endif + + return pRxMsg->u32DataLen > 0U; +} + + +/** + * @brief Polling Message Buffer Received Data + * + * @param u8CanIndex Can Index, Must less than FLEXCAN_INSTANCE_COUNT + * @param pRxMsgList Message Stored buffer point + * @return Received message count + */ +static uint8_t FLEXCAN_LL_PollingMb(uint8_t u8CanIndex, FLEXCAN_RxMsgType *const pRxMsgList) +{ + uint8_t u8MsgNum; + uint32_t u32Status; + uint8_t u8RealMbIndex; + + FLEXCAN_SettingType *pCurSetting; + + uint8_t u8MBindex; + uint8_t u8MbDataWidth; + + pCurSetting = &s_aFlexCan_Setting_Table[u8CanIndex]; + + u8MsgNum = 0U; + + /* loop check all receive message buffer */ + for (u8MBindex = 0U; u8MBindex < pCurSetting->u8RxMbCnt1; u8MBindex++) + { + u8RealMbIndex = (uint8_t)(pCurSetting->u8RxMbStart1 + u8MBindex); + u8MbDataWidth = pCurSetting->eMbDataWidth; + + u32Status = FLEXCAN_LL_ReceiveMb(u8CanIndex, u8RealMbIndex, 0U, u8MbDataWidth, &pRxMsgList[u8MsgNum]); + + if (u32Status != 0U) + { + u8MsgNum ++; + } + else + { + } + } + + return u8MsgNum; +} + +/** + * @brief Polling Legacy Rx FIFO + * + * @param u8CanIndex CanIndex, Must less than FLEXCAN_INSTANCE_COUNT + * @param u8MbDataWidth Message Buffer Data Width + * @param pRxMsgList received data buffer + * @return receive message count + */ +static uint8_t FLEXCAN_LL_PollingLegacyFifo(uint8_t u8CanIndex, uint8_t u8MbDataWidth, FLEXCAN_RxMsgType *pRxMsgList) +{ + uint8_t u8MsgNum; + uint32_t u32Status; + uint8_t u8MBindex; + + u8MsgNum = 0U; + pRxMsgList[u8MsgNum].u32DataLen = 0U; + + /* legacy fifo only receive in MB 0 */ + u8MBindex = 0U; + + /* IFLAG1[BIT5] (Frames available in Rx FIFO) is asserted when there is at least one frame available to be read from the FIFO. */ + u32Status = 1U; + + while (u32Status != 0U) + { + u32Status = FLEXCAN_LL_ReceiveMb(u8CanIndex, u8MBindex, 1U, u8MbDataWidth, &pRxMsgList[u8MsgNum]); + + if (u32Status != 0U) + { + u8MsgNum ++; + } + else + { + } + + } + + return u8MsgNum; +} + +/** + * @brief Polling Enhanced Rx FIFO Data + * + * @param u8CanIndex Can Index, must less than FLEXCAN_INSTANCE_COUNT + * @param pRxMsgList received data buffer + * @return receive message count + */ +static uint8_t FLEXCAN_LL_PollingEnhancedFifo(uint8_t u8CanIndex, FLEXCAN_RxMsgType *pRxMsgList) +{ + uint8_t u8MsgNum; + uint32_t u32Status; + + /* The enhanced Rx FIFO has a watermark that is configured by setting EFRCR[ERFWM]. + * If EFRCR[ERFWM] is set, the CPU is notified only if a minimum number of messages is stored in the FIFO. + * When the number of stored messages is greater than the value in EFRCR[ERFWM], ERFSR[ERFWMI] is set by the hardware. */ + + /* check fd fifo data available */ + u8MsgNum = 0U; + u32Status = 1U; + while (u32Status != 0U) + { + u32Status = FLEXCAN_LL_ReceiveEnhanceFifo(u8CanIndex, &pRxMsgList[u8MsgNum]); + if (u32Status > 0U) + { + u8MsgNum ++; + } + } + + return u8MsgNum; +} + + +/** + * @brief Receive Can FIFO Data + * + * @param u8CanIndex Can Index, must less than FLEXCAN_INSTANCE_COUNT + * @param bEnableFd if it is CAN FD Fifo + * @param pRxMsgList received data buffer + * @return receive message count + */ +static uint8_t FLEXCAN_LL_ReceiveFifo(uint8_t u8CanIndex, uint8_t bEnableFd, FLEXCAN_RxMsgType *pRxMsgList) +{ + + uint8_t u8MsgNum; + + FLEXCAN_SettingType *pCurSetting; + + pCurSetting = &s_aFlexCan_Setting_Table[u8CanIndex]; + + + if (bEnableFd) /* can fd fifo receive */ + { + u8MsgNum = FLEXCAN_LL_PollingEnhancedFifo(u8CanIndex, pRxMsgList); + + } + else /* legacy fifo receive */ + { + u8MsgNum = FLEXCAN_LL_PollingLegacyFifo(u8CanIndex, pCurSetting->eMbDataWidth, pRxMsgList); + + } + + return u8MsgNum; +} + + +/** + * @brief Process CAN Baudrate from table + * + * @param pBaudCfg baudrate configuration + * @return 0 is ok + */ +static uint8_t FLEXCAN_LL_ProcessBaud(FLEXCAN_BaudCfgType *pBaudCfg) +{ + uint32_t u32Mod; + uint8_t u8RetVal; + uint32_t u32Index; + + + u8RetVal = 1U; + + if (pBaudCfg->bEnFd) + { + u32Mod = (uint32_t)pBaudCfg->eClkSrcHz % (uint32_t)pBaudCfg->eBaudrate; + if (u32Mod != 0U) + { + u8RetVal = 1U; + } + else + { + + /* loop check for normal bit rate */ + for (u32Index = 0U; u32Index < sizeof(s_aFlexCan_NormalBaudDividerTable) / sizeof(s_aFlexCan_NormalBaudDividerTable[0]); u32Index++) + { + if ((pBaudCfg->eClkSrcHz == s_aFlexCan_NormalBaudDividerTable[u32Index].eClkHz) && (pBaudCfg->eBaudrate == s_aFlexCan_NormalBaudDividerTable[u32Index].eBaudrate)) + { + /* when pCan fd enabled, pCan normal bit set by CBT !!!! */ + pBaudCfg->u32Cbt = FLEXCAN_CBT_EPRESDIV(s_aFlexCan_NormalBaudDividerTable[u32Index].u32Presdiv - 1U) | + FLEXCAN_CBT_ERJW(s_aFlexCan_NormalBaudDividerTable[u32Index].u32Rjw - 1U) | + FLEXCAN_CBT_EPSEG1(s_aFlexCan_NormalBaudDividerTable[u32Index].u32Pseg1 - 1U) | + FLEXCAN_CBT_EPSEG2(s_aFlexCan_NormalBaudDividerTable[u32Index].u32Pseg2 - 1U) | + FLEXCAN_CBT_EPROPSEG(s_aFlexCan_NormalBaudDividerTable[u32Index].u32Propseg - 1U) | + FLEXCAN_CBT_BTF(1U); /* SMP = 1: use 3 bits per CAN sample */ + + u8RetVal = 0U; + break; + } + } + + + if (u8RetVal == 0U) + { + u8RetVal = 1U; + + /* loop for fd data bit rate */ + for (u32Index = 0U; u32Index < sizeof(s_aFlexCan_DataBaudDividerTable) / sizeof(s_aFlexCan_DataBaudDividerTable[0]); u32Index++) + { + if ((pBaudCfg->eClkSrcHz == s_aFlexCan_DataBaudDividerTable[u32Index].eClkHz) && (pBaudCfg->eDataBaud == s_aFlexCan_DataBaudDividerTable[u32Index].eBaudrate)) + { + pBaudCfg->u32FdCtrl = FLEXCAN_FDCTRL_FDRATE(pBaudCfg->bEnBrs) | + /* MBDSR0, pMb 0-31 data length, 8-0,16-1,32-2,64-3 */ + FLEXCAN_FDCTRL_MBDSR0(pBaudCfg->eMbDataWidth == FLEXCAN_DATAWIDTH_8 ? 0U : (pBaudCfg->eMbDataWidth == FLEXCAN_DATAWIDTH_16 ? 1U : + (pBaudCfg->eMbDataWidth == FLEXCAN_DATAWIDTH_32 ? 2U : 3U))) + | FLEXCAN_FDCTRL_TDCOFF(1U); + + + /* when pCan fd enabled, pCan normal bit set by CBT !!!! */ + pBaudCfg->u32FdCbt = FLEXCAN_FDCBT_FPRESDIV(s_aFlexCan_DataBaudDividerTable[u32Index].u32Presdiv - 1U) | + FLEXCAN_FDCBT_FRJW(s_aFlexCan_DataBaudDividerTable[u32Index].u32Rjw - 1U) | + FLEXCAN_FDCBT_FPSEG1(s_aFlexCan_DataBaudDividerTable[u32Index].u32Pseg1 - 1U) | + FLEXCAN_FDCBT_FPSEG2(s_aFlexCan_DataBaudDividerTable[u32Index].u32Pseg2 - 1U) | + FLEXCAN_FDCBT_FPROPSEG(s_aFlexCan_DataBaudDividerTable[u32Index].u32Propseg); + + u8RetVal = 0U; + break; + } + } + } + + + } + } + else + { + u32Mod = (uint32_t)pBaudCfg->eClkSrcHz % (uint32_t)pBaudCfg->eBaudrate; + if (u32Mod != 0U) + { + u8RetVal = 1U; + } + + else + { + u8RetVal = 1U; + /* loop check for normal bit rate */ + for (u32Index = 0U; u32Index < sizeof(s_aFlexCan_NormalBaudDividerTable) / sizeof(s_aFlexCan_NormalBaudDividerTable[0]); u32Index++) + { + if ((pBaudCfg->eClkSrcHz == s_aFlexCan_NormalBaudDividerTable[u32Index].eClkHz) && (pBaudCfg->eBaudrate == s_aFlexCan_NormalBaudDividerTable[u32Index].eBaudrate)) + { + /* when pCan fd enabled, pCan normal bit set by CBT !!!! */ + pBaudCfg->u32Ctrl1 = FLEXCAN_CTRL1_PRESDIV(s_aFlexCan_NormalBaudDividerTable[u32Index].u32Presdiv - 1U) | + FLEXCAN_CTRL1_RJW(s_aFlexCan_NormalBaudDividerTable[u32Index].u32Rjw - 1U) | + FLEXCAN_CTRL1_PSEG1(s_aFlexCan_NormalBaudDividerTable[u32Index].u32Pseg1 - 1U) | + FLEXCAN_CTRL1_PSEG2(s_aFlexCan_NormalBaudDividerTable[u32Index].u32Pseg2 - 1U) | + FLEXCAN_CTRL1_PROPSEG(s_aFlexCan_NormalBaudDividerTable[u32Index].u32Propseg - 1U); + + u8RetVal = 0U; + } + } + + + } + } + + + return u8RetVal; + +} + +/** + * @brief Set Legacy Rx FIFO + * + * @param u8CanIndex Can Index, must less than FLEXCAN_INSTANCE_COUNT + * @param pRxFilterList Filter id list + * @param u32RxFilterCnt Filter id list length + * @return FLEXCAN_ERROR_OK is ok + */ +static FLEXCAN_ErrorType FLEXCAN_LL_SetLegacyFifo(uint8_t u8CanIndex, FLEXCAN_RxMbFilterType *pRxFilterList, uint32_t u32RxFilterCnt) +{ + FLEXCAN_ErrorType tRetVal; + uint32_t u32FilterNum; + uint32_t u32FilterNumLeft; + uint32_t u32Index; + + FLEXCAN_Type *pCan; + + #if FLEXCAN_CHECK_PARAMETERS == STD_ON + tRetVal = FLEXCAN_LL_CheckFdInstance(u8CanIndex); + + if (tRetVal == FLEXCAN_ERROR_OK) + { + #else + tRetVal = FLEXCAN_ERROR_OK; + #endif + pCan = (FLEXCAN_Type *)s_aFlexCan_InstanceTable[u8CanIndex]; + + /* set legacy fifo */ + FLEXCAN_HWA_EnableLegacyFifo(pCan); + + + /* 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 */ + /* Format A: RTR IDE | RXIDA (standard =29-19, extended = 29-1) | */ + /* Format B: RTR IDE | RXIDB_0 (standart = 29-19, extended = 29-16) MSB compare | RTR IDE|RXIDB_1 (standart = 13-3, extended = 13-0) MSB compare */ + /* Format C: RXIDC_0 (std/ext = 31-24) MSB compare | RXIDC_1 (std/ext = 23-16) MSB compare | RXIDC_2 (std/ext =15-8) MSB compare | RXIDC_3 (std/ext =7-0) MSB compare */ + + /* set always format A */ + + + u32FilterNum = 0U; + + /* filter start from MB 6 */ + for (u32Index = 0U; u32Index < u32RxFilterCnt; u32Index++) + { + /* extended id */ + if (pRxFilterList[u32Index].eRxFrameType == FLEXCAN_ID_EXT) + { + FLEXCAN_HWA_MbRam(pCan, 4U * 6U + u32FilterNum, (1U << 30) | (pRxFilterList[u32Index].u32RxCanId << 1)); /* id */ + FLEXCAN_HWA_SetIndividualMask(pCan, u32FilterNum, (1U << 30) | pRxFilterList[u32Index].u32RxCanIdMask) ; /* mask */ + } + else /* standard id */ + { + FLEXCAN_HWA_MbRam(pCan, 4U * 6U + u32FilterNum, pRxFilterList[u32Index].u32RxCanId << 19); /* id */ + FLEXCAN_HWA_SetIndividualMask(pCan, u32FilterNum, (1U << 30) | (pRxFilterList[u32Index].u32RxCanIdMask << 19)) ; /* mask */ + } + + u32FilterNum++; + } + + /* filter elements number are multiple of 8 */ + u32FilterNumLeft = 8U - u32RxFilterCnt % 8U; + /* set left same to last filter */ + for (u32Index = 0U; u32Index < u32FilterNumLeft; u32Index++) + { + /* extended id */ + if (pRxFilterList[u32FilterNum - 1U].eRxFrameType == FLEXCAN_ID_EXT) + { + FLEXCAN_HWA_MbRam(pCan, 4U * 6U + u32FilterNum + u32Index, (1U << 30) | (pRxFilterList[u32FilterNum - 1U].u32RxCanId << 1)); /* id */ + FLEXCAN_HWA_SetIndividualMask(pCan, u32FilterNum + u32Index, (1U << 30) | pRxFilterList[u32FilterNum - 1U].u32RxCanIdMask); /* mask */ + } + else /* standard id */ + { + FLEXCAN_HWA_MbRam(pCan, 4U * 6U + u32FilterNum + u32Index, pRxFilterList[u32FilterNum - 1U].u32RxCanId << 19); /* id */ + FLEXCAN_HWA_SetIndividualMask(pCan, u32FilterNum + u32Index, (1U << 30) | (pRxFilterList[u32FilterNum - 1U].u32RxCanIdMask << 19)); /* mask */ + + } + } + + /* set fifo filter, 1 group filter contains 8 filter elements (2MBs) */ + /* left for tx = MaxMb-6 - (RFFN+1)*2 */ + u32FilterNum = u32FilterNum / 8U + (u32FilterNum % 8U > 0U ? 1U : 0U); + FLEXCAN_HWA_SetLegacyFifoFilterNum(pCan, u32FilterNum); + #if FLEXCAN_CHECK_PARAMETERS == STD_ON + } + #endif + + return tRetVal; +} + +/** + * @brief Set Enhanced Rx FIFO + * + * @param u8CanIndex Can Index, must less than FLEXCAN_INSTANCE_COUNT + * @param pRxFilterList Filter id list + * @param u32RxFilterCnt Filter id list length + * @param u8WaterMark DMA Wartmark + * @return FLEXCAN_ERROR_OK is ok + */ +static FLEXCAN_ErrorType FLEXCAN_LL_SetEnhancedFifo(uint8_t u8CanIndex, FLEXCAN_RxMbFilterType *pRxFilterList, uint32_t u32RxFilterCnt, uint8_t u8WaterMark) +{ + FLEXCAN_ErrorType tRetVal; + uint32_t u32FilterERFCRNum; + uint32_t u32Index; + FLEXCAN_Type *pCan; + + #if FLEXCAN_CHECK_PARAMETERS == STD_ON + tRetVal = FLEXCAN_LL_CheckFdInstance(u8CanIndex); + + if (tRetVal == FLEXCAN_ERROR_OK) + { + #else + tRetVal = FLEXCAN_ERROR_OK; + #endif + + uint32_t u32ExtIDFilterNum; + uint32_t u32StdIDFilterNum; + uint32_t u32TempERFCR; + + /* current pCan instance */ + pCan = (FLEXCAN_Type *)s_aFlexCan_InstanceTable[u8CanIndex]; + + /* Configure the filter elements by writing in the ERFFELn registers (ERFFELn registers are implemented in RAM; thus, they must be explicitly initialized prior to any reception). */ + + /* standard id filter */ + /* 31-30 29-28 27 26-16 15-12 11 10-0 */ + /* FSCH=b00 Reserved RTR filter STD ID filter Reserved RTR mask STD ID mask id_filter&id_mask */ + /* FSCH=b01 Reserved RTR filter STD ID filter2 Reserved RTR mask STD ID filter1 id filter1<=id<= id filter2 */ + /* FSCH=b10 Reserved RTR filter2 STD ID filter2 Reserved RTR filter1 STD ID filter1 id filter1= id = id filter2 */ + + /* extended id filter */ + /* 31-30 29 28-0 */ + /* FSCH=00b RTR filter EXT ID filter */ + /* Reserved RTR mask EXT ID mask */ + /* FSCH=01b RTR filter EXT ID filter2 */ + /* Reserved RTR mask EXT ID filter1 */ + /* FSCH=10b RTR filter2 EXT ID filter2 */ + /* Reserved RTR filter1 EXT ID filter1 */ + + u32ExtIDFilterNum = 0U; + u32StdIDFilterNum = 0U; + + /* get extended id count and standard id count */ + for (u32Index = 0U; u32Index < u32RxFilterCnt; u32Index++) + { + if (pRxFilterList[u32Index].eRxFrameType == FLEXCAN_ID_EXT) + { + /* extended id first */ + /* pCan->ERFFEL[u32Index] &= 0xFFFFFFFU; */ + FLEXCAN_HWA_EnhancedFifoFilter(pCan, u32ExtIDFilterNum * 2U, pRxFilterList[u32Index].u32RxCanId); /* id */ + FLEXCAN_HWA_EnhancedFifoFilter(pCan, u32ExtIDFilterNum * 2U + 1U, pRxFilterList[u32Index].u32RxCanIdMask); /* mask */ + + u32ExtIDFilterNum++; + } + } + + for (u32Index = 0U; u32Index < u32RxFilterCnt; u32Index++) + { + /* standard id */ + if (pRxFilterList[u32Index].eRxFrameType == FLEXCAN_ID_STD) + { + FLEXCAN_HWA_EnhancedFifoFilter(pCan, u32ExtIDFilterNum * 2U + u32StdIDFilterNum, (pRxFilterList[u32Index].u32RxCanId << 16) | pRxFilterList[u32Index].u32RxCanIdMask); + u32StdIDFilterNum++; + } + } + + /* standard id number must multiple of 2 */ + tRetVal = (FLEXCAN_ErrorType)(tRetVal | ((u32StdIDFilterNum % 2U == 1U) ? FLEXCAN_ERROR_INVALID_PARAM : FLEXCAN_ERROR_OK)); + + if (tRetVal == FLEXCAN_ERROR_OK) + { + /* total id filter number in ERFCR, two std */ + u32FilterERFCRNum = u32StdIDFilterNum / 2U + u32ExtIDFilterNum - 1U; + + + + /* Write one to ERFSR[ERFCLR] to reset Enhanced Rx FIFO engine */ + FLEXCAN_HWA_ERFSRResetEnhancedFifo(pCan); + /* Clear EFRSR[ERFUFW], EFRSR[ERFOVF], EFRSR[ERFWMI], and EFRSR[ERFDA], if they are set. */ + FLEXCAN_HWA_ERFSRClearEnhancedFifoFlag(pCan, FLEXCAN_ERFSR_ERFUFW_MASK | FLEXCAN_ERFSR_ERFWMI_MASK | FLEXCAN_ERFSR_ERFDA_MASK); + /* Write EFRCR[NFE] to configure the total number of enhanced Rx FIFO filter elements to be used in Enhanced Rx FIFO reception. */ + + + /* set rx fifo filter num */ + u32TempERFCR = ((u32FilterERFCRNum) << FLEXCAN_ERFCR_NFE_SHIFT)&FLEXCAN_ERFCR_NFE_MASK; + + /* Write ERFCR[NEXIF] to configure the number of extended ID and standard ID filter elements to be used in Enhanced Rx FIFO reception (NEXIF �� NFE + 1). */ + /* set rx fifo extended id filter num, <= NFE+1 */ + u32TempERFCR |= (u32ExtIDFilterNum << FLEXCAN_ERFCR_NEXIF_SHIFT)&FLEXCAN_ERFCR_NEXIF_MASK; + + u32TempERFCR |= FLEXCAN_ERFCR_ERFWM(u8WaterMark - 1U); /* receive 1 message will indicate to fifo water mark */ + + u32TempERFCR |= FLEXCAN_ERFCR_DMALW(19U); + + u32TempERFCR |= FLEXCAN_ERFCR_ERFEN_MASK; /* enable enhance fifo dma */ + + FLEXCAN_HWA_SetERFCR(pCan, u32TempERFCR); + + /* set enhanced fifo */ + FLEXCAN_HWA_EnableFDFifo(pCan); + + /* Configure the Enhanced Rx FIFO watermark by writing ERFCR[ERFWM]. */ + + /* If interrupts will be used, set the interrupt enables in the ERIER register */ + + /* If DMA will be used, set MCR[DMA] to enable DMA operation and write ERFCR[DMALW] to configure the number of words to transfer for each Enhanced Rx FIFO data element */ + + } + #if FLEXCAN_CHECK_PARAMETERS == STD_ON + } + #endif + + return tRetVal; + +} + + + +/** + * @brief Process Tx Iflag and return result + * + * @param u8CanIndex Can Index, must less than FLEXCAN_INSTANCE_COUNT + * @param u8Handler Transmit Handler + * @return 1 means process successfully and can transmit next time, 0 means no active flag, 0xff means out of range + */ +static uint8_t FLEXCAN_LL_ProcessTx(uint8_t u8CanIndex, uint8_t u8Handler) +{ + uint8_t u8Index; + FLEXCAN_Type *pCan; + FLEXCAN_SettingType *pCurSetting; + uint32_t u32Iflag; + uint32_t u32HandlerMask; + + pCurSetting = &s_aFlexCan_Setting_Table[u8CanIndex]; + +#if FLEXCAN_CHECK_PARAMETERS == STD_ON + if(u8Handler < pCurSetting->u8TxMbCnt1) + { +#endif + pCan = (FLEXCAN_Type *)s_aFlexCan_InstanceTable[u8CanIndex]; + + u32Iflag = FLEXCAN_HWA_GetFlag1(pCan);; + u32HandlerMask = (1U << (pCurSetting->u8TxMbStart1+u8Handler)); + + u32Iflag = u32Iflag & u32HandlerMask; + + if(u32Iflag>0U) + FLEXCAN_HWA_SetFlag1(pCan, u32Iflag); + + u8Index = ((u32Iflag>0U)?1U:0U); +#if FLEXCAN_CHECK_PARAMETERS == STD_ON + } + else + { + u8Index = 0xFFU; + } +#endif + + return u8Index; +} + + +/* ################################################################################## */ +/* ################################ Global Functions ################################ */ + + + +/** + * @brief Initial FLEXCAN variables Memory + * + * @param u8CanIndex Can Index, must less than FLEXCAN_INSTANCE_COUNT + */ +void FLEXCAN_InitMemory(uint8_t u8CanIndex) +{ + + #if FLEXCAN_CHECK_PARAMETERS == STD_ON + FLEXCAN_ErrorType tRetVal; + /* check parameter */ + tRetVal = FLEXCAN_LL_CheckInstance(u8CanIndex); + if (tRetVal == FLEXCAN_ERROR_OK) + { + #endif + + s_aFlexCan_Setting_Table[u8CanIndex].bEnableFd = 0U; + s_aFlexCan_Setting_Table[u8CanIndex].bEnableFifo = 0U; + s_aFlexCan_Setting_Table[u8CanIndex].bEnableDMA = 0U; + s_aFlexCan_Setting_Table[u8CanIndex].pRxBuf = NULL; + s_aFlexCan_Setting_Table[u8CanIndex].u8RxMbCnt1 = 0U; + s_aFlexCan_Setting_Table[u8CanIndex].u8RxMbStart1 = 0U; + s_aFlexCan_Setting_Table[u8CanIndex].u8TxMbCnt1 = 0U; + s_aFlexCan_Setting_Table[u8CanIndex].u8TxMbStart1 = 0U; + s_aFlexCan_Setting_Table[u8CanIndex].u8RxFifoCnt = 0U; + s_aFlexCan_Setting_Table[u8CanIndex].eMbDataWidth = FLEXCAN_DATAWIDTH_8; + s_aFlexCan_Setting_Table[u8CanIndex].u8EnhancedFifoDmaWM = 0U; + s_aFlexCan_ErrorNotifyTable[u8CanIndex] = NULL; + s_aFlexCan_TxNotifyTable[u8CanIndex] = NULL; + s_aFlexCan_RxNotifyTable[u8CanIndex] = NULL; + + s_aFlexCan_CanUsed[u8CanIndex] = 0U; + + /* set first state */ + s_aCurrentSequence[u8CanIndex] = FLEXCAN_SEQUENCE_DEINIT; + #if FLEXCAN_CHECK_PARAMETERS == STD_ON + } + #endif + +} + + +void SystemDelayMs(uint32_t ms); + +/** + * @brief Initial CAN + * + * @param u8CanIndex Can Index, must less than FLEXCAN_INSTANCE_COUNT + * @param pInitCfg clock, baud-rate, canfd, data length and so on. + * @return 0 is ok, others are not ok + */ +FLEXCAN_ErrorType FLEXCAN_Init(uint8_t u8CanIndex, const FLEXCAN_InitType *const pInitCfg) +{ + FLEXCAN_ErrorType tRetVal; + uint32_t u32TempCtrl1; + uint32_t u32TempMcr; + uint8_t u8Result; + FLEXCAN_Type *pCan; + FLEXCAN_BaudCfgType tBaudCfg; + + SystemDelayMs(0); + + #if FLEXCAN_CHECK_PARAMETERS == STD_ON + /* check parameter */ + tRetVal = FLEXCAN_LL_CheckInstance(u8CanIndex); + + if ((tRetVal == FLEXCAN_ERROR_OK) && (s_aCurrentSequence[u8CanIndex] == FLEXCAN_SEQUENCE_DEINIT)) + { + tRetVal = FLEXCAN_ERROR_OK; + } + else + { + tRetVal |= FLEXCAN_ERROR_INVALID_SEQUENCE; + } + + + if (pInitCfg == NULL || (pInitCfg->u8EnhancedFifoDmaWM > 12U)) + { + tRetVal |= FLEXCAN_ERROR_INVALID_PARAM; + } + else + { + /* DMA only support in Legacy Rx FIFO and Enhance Rx FIFO */ + if (pInitCfg->bEnDma != 0U) + { + if ((pInitCfg->bEnRxFifo == 0U)) + { + tRetVal |= FLEXCAN_ERROR_INVALID_PARAM; + } + } + } + + if ((pInitCfg->bEnFd == 0U) && (pInitCfg->bEnBrs == 1U)) + { + tRetVal |= FLEXCAN_ERROR_INVALID_PARAM; + } + + if ((pInitCfg->bEnFd == 1U) && (u8CanIndex >= FLEXCAN_FD_INSTANCE_COUNT)) + { + tRetVal |= FLEXCAN_ERROR_INVALID_PARAM; + } + + if (tRetVal == FLEXCAN_ERROR_OK) + { + #endif + /* set not start state */ + s_aCurrentSequence[u8CanIndex] = FLEXCAN_SEQUENCE_NOTSTART; + + pCan = (FLEXCAN_Type *)s_aFlexCan_InstanceTable[u8CanIndex]; + + u8Result = 0U; + tRetVal = FLEXCAN_ERROR_OK; + + FLEXCAN_HWA_SetMcrDisable(pCan, TRUE); + FLEXCAN_HWA_SetCtrl1(pCan, 0U); + FLEXCAN_HWA_SetCtrl1BaudSrc(pCan, pInitCfg->eClkSrcSel); + + FLEXCAN_HWA_SetMcrDisable(pCan, FALSE); + + /* mcr->B.bitMDIS = 0; */ + + FLEXCAN_HWA_SetHaltFreeze(pCan); + + /* wait for bitFRZACK=1 on freeze mode entry/exit */ + if (FLEXCAN_HWA_WaitMcrFreezen(pCan, 10000U) != 0U) + { + tRetVal |= FLEXCAN_ERROR_TIMEOUT; + } + else + { +// FLEXCAN_HWA_SetCtrl2(pCan, +// FLEXCAN_CTRL2_WRMFRZ(1U) | /* initial ram ecc */ +// FLEXCAN_CTRL2_TASD(20U) | +// FLEXCAN_CTRL2_DIRECT_EN(((pInitCfg->eDirect) & FLEXCAN_CTRL2_DIRECT_EN_MASK) ? 1U : 0U) | +// FLEXCAN_CTRL2_DIRECT_TRIG(((pInitCfg->eDirect) & FLEXCAN_CTRL2_DIRECT_TRIG_MASK) ? 1U : 0U) | +// FLEXCAN_CTRL2_ISOCANFDEN(1U)); + FLEXCAN_HWA_SetCtrl2(pCan, + FLEXCAN_CTRL2_WRMFRZ(1U) | /* initial ram ecc */ + FLEXCAN_CTRL2_TASD(20U) | + FLEXCAN_CTRL2_ISOCANFDEN(1U)); + + + + tBaudCfg.bEnFd = pInitCfg->bEnFd; + tBaudCfg.bEnBrs = pInitCfg->bEnBrs; + tBaudCfg.eMbDataWidth = pInitCfg->eMbDataWidth; + + tBaudCfg.eClkSrcHz = pInitCfg->eClkSrcHz; + tBaudCfg.eBaudrate = pInitCfg->eBaudrate; + tBaudCfg.eDataBaud = pInitCfg->eDataBaud; + + + u8Result = FLEXCAN_LL_ProcessBaud(&tBaudCfg); + + + if (u8Result) + { + tRetVal = FLEXCAN_ERROR_INVALID_PARAM; + } + else + { + /* when pCan fd disabled, pCan normal bit set by CTRL1 !!!! */ + u32TempCtrl1 = FLEXCAN_CTRL1_CLKSRC(pInitCfg->eClkSrcSel) | FLEXCAN_CTRL1_LOM(pInitCfg->bListenOnly); + + if (!tBaudCfg.bEnFd) + { + u32TempCtrl1 |= tBaudCfg.u32Ctrl1; /* SMP = 1: use 3 bits per CAN sample */ + } + else + { + FLEXCAN_HWA_SetCBT(pCan, tBaudCfg.u32Cbt); + + FLEXCAN_HWA_SetFDCTRL(pCan, tBaudCfg.u32FdCtrl); + FLEXCAN_HWA_SetFDCBT(pCan, tBaudCfg.u32FdCbt); + } + + + FLEXCAN_HWA_SetCtrl1(pCan, u32TempCtrl1); + + /* initial RAM to avoid ECC error CFIFCFIF*/ + FLEXCAN_LL_EmbededRam_Init(u8CanIndex); + + u32TempMcr = FLEXCAN_MCR_MDIS(0) | /* enable pCan module */ + FLEXCAN_MCR_FRZ(1) | /* not frozen */ + FLEXCAN_MCR_RFEN(((!pInitCfg->bEnFd) && pInitCfg->bEnRxFifo) ? 1U : 0U) | /* Legacy RX FIFO, only when canfd not enable */ + FLEXCAN_MCR_HALT(1) | /* not halt */ + FLEXCAN_MCR_SOFTRST(0) | /* not reset */ + FLEXCAN_MCR_SUPV(1) | /* supervisor mode */ + FLEXCAN_MCR_WRNEN(0) | /* wake up disable */ + FLEXCAN_MCR_SRXDIS(1) | /* self reception disable */ + FLEXCAN_MCR_IRMQ(0) | /* individual Rx masking */ + FLEXCAN_MCR_DMA(pInitCfg->bEnDma) | /* DMA enable */ + FLEXCAN_MCR_PNET_EN(0) | /* Pretended Networking Enable */ + FLEXCAN_MCR_LPRIOEN(0) | /* Local Priority disable */ + FLEXCAN_MCR_AEN(0) | /* abort disable */ + FLEXCAN_MCR_FDEN(pInitCfg->bEnFd) | /* CAN FD enable */ + FLEXCAN_MCR_IDAM(0) | /* ID Acceptance Mode for Rx FIFO, format A */ + FLEXCAN_MCR_MAXMB(0); /* Max number of Message Buffer, num 31 is the 32th MB */ + + FLEXCAN_HWA_SetMCR(pCan, u32TempMcr); /* Negate FlexCAN 1 halt state for 32 MBs */ + + /* store setting value */ + s_aFlexCan_Setting_Table[u8CanIndex].bEnableFd = pInitCfg->bEnFd; + s_aFlexCan_Setting_Table[u8CanIndex].bEnableFifo = pInitCfg->bEnRxFifo; + s_aFlexCan_Setting_Table[u8CanIndex].bEnableDMA = pInitCfg->bEnDma; + s_aFlexCan_Setting_Table[u8CanIndex].eMbDataWidth = pInitCfg->eMbDataWidth; + s_aFlexCan_Setting_Table[u8CanIndex].u8EnhancedFifoDmaWM = pInitCfg->u8EnhancedFifoDmaWM; + } + } + #if FLEXCAN_CHECK_PARAMETERS == STD_ON + } + #endif + + return tRetVal; + +} + + +/** + * @brief De-initial can instance + * + * @param u8CanIndex Can Index, must less than FLEXCAN_INSTANCE_COUNT + * @return 0 is ok, others are not ok + */ +FLEXCAN_ErrorType FLEXCAN_DeInit(uint8_t u8CanIndex) +{ + FLEXCAN_ErrorType tRetVal; + uint32_t u32TempMcr; + FLEXCAN_Type *pCan; + + #if FLEXCAN_CHECK_PARAMETERS == STD_ON + /* check parameter */ + tRetVal = FLEXCAN_LL_CheckInstance(u8CanIndex); + + if (tRetVal == FLEXCAN_ERROR_OK) + { + tRetVal = FLEXCAN_ERROR_OK; + } + else + { + tRetVal |= FLEXCAN_ERROR_INVALID_SEQUENCE; + } + + if (tRetVal == FLEXCAN_ERROR_OK) + { + #else + tRetVal = FLEXCAN_ERROR_OK; + #endif + pCan = (FLEXCAN_Type *)s_aFlexCan_InstanceTable[u8CanIndex]; + FLEXCAN_HWA_SetHaltFreeze(pCan); + + /* wait for bitFRZACK=1 on freeze mode entry/exit */ + if (FLEXCAN_HWA_WaitMcrFreezen(pCan, 10000U) != 0U) + { + tRetVal |= FLEXCAN_ERROR_TIMEOUT; + } + else + { + if(u8CanIndex < FLEXCAN_FD_INSTANCE_COUNT) + { + FLEXCAN_HWA_DisableFDFifo(pCan); + } + + + FLEXCAN_HWA_DisableLegacyFifo(pCan); + + u32TempMcr = FLEXCAN_MCR_MDIS(1) | /* enable pCan module */ + FLEXCAN_MCR_FRZ(0) | /* not frozen */ + FLEXCAN_MCR_RFEN(0U) | /* RX FIFO disable */ + FLEXCAN_MCR_HALT(0) | /* not halt */ + FLEXCAN_MCR_SOFTRST(0) | /* not reset */ + FLEXCAN_MCR_SUPV(1) | /* supervisor mode */ + FLEXCAN_MCR_WRNEN(0) | /* wake up disable */ + FLEXCAN_MCR_SRXDIS(1) | /* self reception disable */ + FLEXCAN_MCR_IRMQ(0) | /* individual Rx masking */ + FLEXCAN_MCR_DMA(0) | /* DMA enable */ + FLEXCAN_MCR_PNET_EN(0) | /* Pretended Networking Enable */ + FLEXCAN_MCR_LPRIOEN(0) | /* Local Priority disable */ + FLEXCAN_MCR_AEN(0) | /* abort disable */ + FLEXCAN_MCR_FDEN(0) | /* CAN FD enable */ + FLEXCAN_MCR_IDAM(0) | /* ID Acceptance Mode for Rx FIFO, format A */ + FLEXCAN_MCR_MAXMB(0); /* Max number of Message Buffer, num 31 is the 32th MB */ + + + FLEXCAN_HWA_SetCtrl1(pCan, 0U); + FLEXCAN_HWA_SetMCR(pCan, u32TempMcr); /* Negate FlexCAN 1 halt state for 32 MBs */ + + /* clear setting value */ + FLEXCAN_InitMemory(u8CanIndex); + } + + #if FLEXCAN_CHECK_PARAMETERS == STD_ON + } + #endif + + return tRetVal; +} + + +/** + * @brief Configure can receive message box and id filter + * + * @param u8CanIndex Can Index, must less than FLEXCAN_INSTANCE_COUNT + * @param pRxMbCfg contains CAN Instance, Rx CAN ID and Mask + * @return 0 is ok + */ +FLEXCAN_ErrorType FLEXCAN_RxFilterConfig(uint8_t u8CanIndex, const FLEXCAN_MBConfigType *const pRxMbCfg) +{ + FLEXCAN_ErrorType tRetVal; + FLEXCAN_Type *pCan; + FLEXCAN_RxMbFilterType *pCurRxCfg; + uint32_t u32Mask; + uint8_t u8Index; + FLEXCAN_SettingType *pCurSetting; + uint8_t bIndividualMask; + uint32_t u32TempAddr; + + #if FLEXCAN_CHECK_PARAMETERS == STD_ON + /* check parameter */ + tRetVal = FLEXCAN_LL_CheckInstance(u8CanIndex); + + if ((tRetVal == FLEXCAN_ERROR_OK) && (s_aCurrentSequence[u8CanIndex] == FLEXCAN_SEQUENCE_NOTSTART)) + { + tRetVal = FLEXCAN_ERROR_OK; + } + else + { + tRetVal |= FLEXCAN_ERROR_INVALID_SEQUENCE; + } + + if (pRxMbCfg == NULL) + { + tRetVal |= FLEXCAN_ERROR_INVALID_PARAM; + } + else + { + /* check buffer point if it is null */ + if ((pRxMbCfg->pRxBuf == NULL) || (((pRxMbCfg->u8RxFilterFifoCnt > 0U) && (pRxMbCfg->pRxFilterFifoList == NULL)))) + { + tRetVal |= FLEXCAN_ERROR_INVALID_PARAM; + } + } + + if (tRetVal == FLEXCAN_ERROR_OK) + { + #else + tRetVal = FLEXCAN_ERROR_OK; + #endif + bIndividualMask = 1U; + + /* current pCan instance */ + pCan = (FLEXCAN_Type *)s_aFlexCan_InstanceTable[u8CanIndex]; + + /* current pCan message pMb cnt */ + pCurSetting = &s_aFlexCan_Setting_Table[u8CanIndex]; + + + pCurSetting->pRxBuf = pRxMbCfg->pRxBuf; + + pCurSetting->u8RxMbStart1 = 0U; /* receive message buffer always start from 0 */ + pCurSetting->u8TxMbStart1 = 0U; + pCurSetting->u8RxMbCnt1 = pRxMbCfg->u8RxFilterMBCnt; + pCurSetting->u8TxMbCnt1 = pRxMbCfg->u8TxMsgCnt; + pCurSetting->u8RxFifoCnt = pRxMbCfg->u8RxFilterFifoCnt; + + if (pCurSetting->bEnableFifo) + { + /* only non-fd fifo need rx filter between rx and tx message buffer */ + if (pCurSetting->bEnableFd) + { +#if 0 + /* must multiple of 2 */ + if (pRxMbCfg->u8RxFilterFifoCnt % 2U) + { + tRetVal |= FLEXCAN_ERROR_INVALID_PARAM; + } +#endif + + /* set fifo filter parameter */ + tRetVal = (FLEXCAN_ErrorType)(tRetVal | FLEXCAN_LL_SetEnhancedFifo(u8CanIndex, pRxMbCfg->pRxFilterFifoList, (uint32_t)pRxMbCfg->u8RxFilterFifoCnt, + pCurSetting->u8EnhancedFifoDmaWM)); + } + else + { + /* insert rx filter before tx message buffer, every group filter contains 8 elements(2MBs), at least 2 groups */ + if (pRxMbCfg->u8RxFilterFifoCnt <= 8U) + { + pCurSetting->u8RxMbStart1 = 8U; + } + else + { + pCurSetting->u8RxMbStart1 = (uint8_t)(6U + 2U * (pRxMbCfg->u8RxFilterFifoCnt / 8U + (pRxMbCfg->u8RxFilterFifoCnt % 8U > 0U ? 1U : 0U))); + + } + pCurSetting->u8TxMbStart1 = (uint8_t)(pCurSetting->u8RxMbStart1 + pCurSetting->u8RxMbCnt1); + + + /* set fifo filter parameter */ + tRetVal |= FLEXCAN_LL_SetLegacyFifo(u8CanIndex, pRxMbCfg->pRxFilterFifoList, (uint32_t)pRxMbCfg->u8RxFilterFifoCnt); + } + + + } + else + { + if (pCurSetting->bEnableFd) + { + + /* clear enhanced fifo */ + FLEXCAN_HWA_DisableFDFifo(pCan); + } + else + { + /* clear legacy fifo */ + FLEXCAN_HWA_DisableLegacyFifo(pCan); + } + } + + + /* For normal message buffer. */ + + /* fifo can exist with normal mb */ + /* Receive MB first set */ + + for (u8Index = 0U; u8Index < pCurSetting->u8RxMbCnt1; u8Index++) + { + uint8_t u8MBIndex; + /* ############## current rx pMb #################### */ + u8MBIndex = (uint8_t)(pCurSetting->u8RxMbStart1 + u8Index); + pCurSetting->u8TxMbStart1 ++; + /* current rx filter */ + pCurRxCfg = &(pRxMbCfg->pRxFilterMBList[u8Index]); + /* message buffer 1th word */ + u32TempAddr = (uint32_t)FLEXCAN_MB_WORDN_ADDR(&(pCan->RAM[0U]), u8MBIndex, pCurSetting->eMbDataWidth, 0U); + + FLEXCAN_MB_IDE_SET(u32TempAddr, pCurRxCfg->eRxFrameType); + + /* message buffer 2th word */ + u32TempAddr = (uint32_t)FLEXCAN_MB_WORDN_ADDR(&(pCan->RAM[0U]), u8MBIndex, pCurSetting->eMbDataWidth, 4U); + + /* 1. set filter id */ + if (pCurRxCfg->eRxFrameType == FLEXCAN_ID_STD) + { + FLEXCAN_MB_STDID_SET(u32TempAddr, pCurRxCfg->u32RxCanId); + + u32Mask = pCurRxCfg->u32RxCanIdMask << 18U; /* stardard id left shift 18 bits */ + } + else /* extended id filter */ + { + FLEXCAN_MB_EXTID_SET(u32TempAddr, pCurRxCfg->u32RxCanId); + u32Mask = pCurRxCfg->u32RxCanIdMask; /* stardard id */ + } + + /* message buffer 1th word */ + u32TempAddr = (uint32_t)FLEXCAN_MB_WORDN_ADDR(&(pCan->RAM[0U]), u8MBIndex, pCurSetting->eMbDataWidth, 0U); + /* set code 0x04U to enable rx */ + FLEXCAN_MB_CODE_SET(u32TempAddr, 4U); + + /* 3. set rx filter u32Mask */ + if (bIndividualMask) + { + /* In FRZ mode, init CAN1 16 msg buf filters */ + FLEXCAN_HWA_SetIndividualMask(pCan, (uint32_t)u8MBIndex, u32Mask); + } + else + { + /* global u32Mask */ + /* Global acceptance u32Mask: check all ID bits */ + if (u8MBIndex == 14U) + { + FLEXCAN_HWA_SetRx14Mask(pCan, u32Mask); + } + else if (u8MBIndex == 15U) + { + FLEXCAN_HWA_SetRx15Mask(pCan, u32Mask); + } + else + { + FLEXCAN_HWA_SetGlobalMask(pCan, u32Mask); + } + } + + + } + u8Index = (uint8_t)(pCurSetting->u8TxMbStart1 + pCurSetting->u8TxMbCnt1 - (uint8_t)0x1U); + + /* set max pMb number */ + FLEXCAN_HWA_AttachMCR(pCan, FLEXCAN_MCR_MAXMB(u8Index) /* Maximum pMb index */ + | FLEXCAN_MCR_IRMQ(bIndividualMask)); /* individual Rx masking */ + + #if FLEXCAN_CHECK_PARAMETERS == STD_ON + } + #endif + + return tRetVal; +} + + +/** + * @brief Configure can interrupt + * + * @param u8CanIndex Can Index, must less than FLEXCAN_INSTANCE_COUNT + * @param pIntCfg Contians interrupt enable and call back function points + * @return 0 is ok + */ +FLEXCAN_ErrorType FLEXCAN_SetInterrupt(uint8_t u8CanIndex, const FLEXCAN_InterruptType *const pIntCfg) +{ + FLEXCAN_ErrorType tRetVal; + FLEXCAN_Type *pCan; + uint32_t u32Mask; + uint8_t u8Index; + FLEXCAN_SettingType *pCurSetting; + + #if FLEXCAN_CHECK_PARAMETERS == STD_ON + /* check parameter */ + tRetVal = FLEXCAN_LL_CheckInstance(u8CanIndex); + + if ((tRetVal == FLEXCAN_ERROR_OK) && (s_aCurrentSequence[u8CanIndex] == FLEXCAN_SEQUENCE_NOTSTART)) + { + tRetVal = FLEXCAN_ERROR_OK; + } + else + { + tRetVal |= FLEXCAN_ERROR_INVALID_SEQUENCE; + } + + if (pIntCfg == NULL) + { + tRetVal |= FLEXCAN_ERROR_INVALID_PARAM; + } + else + { + /* check buffer point if it is null */ + if (((pIntCfg->bEnRxFifoInterrupt == 1U) && (pIntCfg->pRxFifoNotify == NULL)) + || ((pIntCfg->bEnRxMBInterrupt == 1U) && (pIntCfg->pRxMBNotify == NULL)) + || ((pIntCfg->bEnErrorInterrupt == 1U) && (pIntCfg->pErrorNotify == NULL))) + { + tRetVal |= FLEXCAN_ERROR_INVALID_PARAM; + } + } + + if (tRetVal == FLEXCAN_ERROR_OK) + { + #else + tRetVal = FLEXCAN_ERROR_OK; + #endif + pCan = (FLEXCAN_Type *)s_aFlexCan_InstanceTable[u8CanIndex]; + + pCurSetting = &s_aFlexCan_Setting_Table[u8CanIndex]; + + if ((pIntCfg->bEnErrorInterrupt) || (pIntCfg->bEnRxFifoInterrupt) || (pIntCfg->bEnRxMBInterrupt)) + { + } + + + if (pIntCfg->bEnErrorInterrupt) + { + FLEXCAN_HWA_AttachCtrl1(pCan, FLEXCAN_CTRL1_ERRMSK(1U) | /* error interrupt u32Mask */ + FLEXCAN_CTRL1_BOFFMSK(1U)); /* busoff interrupt u32Mask */ + + + FLEXCAN_HWA_AttachCtrl2(pCan, FLEXCAN_CTRL2_ERRMSK_FAST(1U) /* fast error */); + + s_aFlexCan_ErrorNotifyTable[u8CanIndex] = pIntCfg->pErrorNotify; + } + + if (pIntCfg->bEnRxFifoInterrupt) + { + /* interrupt for fifo */ + if (pCurSetting->bEnableFifo) + { + /* can fd fifo interrupt */ + if (pCurSetting->bEnableFd) + { + /* enhanced fifo data available interrupt */ + FLEXCAN_HWA_SetERFIERDataInterrupt(pCan); + } + else /* non-fd fifo interrupt */ + { + /* MB 5 at least one message in fifo interrupt */ + FLEXCAN_HWA_SetMaskFifoInterrupt(pCan); + } + s_aFlexCan_RxFifoNotifyTable[u8CanIndex] = pIntCfg->pRxFifoNotify; + } + } + if (pIntCfg->bEnTxMBInterrupt) + { + u32Mask = 0U; + + for (u8Index = 0U; u8Index < pCurSetting->u8TxMbCnt1; u8Index++) + { + u32Mask = (u32Mask << 1U) | (1U << pCurSetting->u8TxMbStart1); + } + + /* MB 31-0 u32Mask */ + FLEXCAN_HWA_AttachMaskMbInterrupt(pCan, u32Mask); + + s_aFlexCan_TxNotifyTable[u8CanIndex] = pIntCfg->pTxMBNotify; + } + + if (pIntCfg->bEnRxMBInterrupt) + { + u32Mask = 0U; + + for (u8Index = 0U; u8Index < pCurSetting->u8RxMbCnt1; u8Index++) + { + u32Mask = (u32Mask << 1U) | (1U << pCurSetting->u8RxMbStart1); + } + + /* MB 31-0 u32Mask */ + FLEXCAN_HWA_AttachMaskMbInterrupt(pCan, u32Mask); + + s_aFlexCan_RxNotifyTable[u8CanIndex] = pIntCfg->pRxMBNotify; + } + s_aFlexCan_Setting_Table[u8CanIndex].bEnableFifoInt = pIntCfg->bEnRxFifoInterrupt; + s_aFlexCan_Setting_Table[u8CanIndex].bEnableTxMBInt = pIntCfg->bEnTxMBInterrupt; + s_aFlexCan_Setting_Table[u8CanIndex].bEnableRxMBInt = pIntCfg->bEnRxMBInterrupt; + s_aFlexCan_Setting_Table[u8CanIndex].bEnableErrInt = pIntCfg->bEnRxMBInterrupt; + #if FLEXCAN_CHECK_PARAMETERS == STD_ON + } + #endif + + return tRetVal; +} + + +/** + * @brief Start can instance + * + * @param u8CanIndex Can Index, must less than FLEXCAN_INSTANCE_COUNT + * @return 0 is ok + */ +FLEXCAN_ErrorType FLEXCAN_Start(uint8_t u8CanIndex) +{ + FLEXCAN_ErrorType tRetVal; + uint32_t u32TempMcr; + FLEXCAN_Type *pCan; + + #if FLEXCAN_CHECK_PARAMETERS == STD_ON + /* check parameter */ + tRetVal = FLEXCAN_LL_CheckInstance(u8CanIndex); + + if ((tRetVal == FLEXCAN_ERROR_OK) && (s_aCurrentSequence[u8CanIndex] == FLEXCAN_SEQUENCE_NOTSTART)) + { + tRetVal = FLEXCAN_ERROR_OK; + } + else + { + tRetVal |= FLEXCAN_ERROR_INVALID_SEQUENCE; + } + + + if (tRetVal == FLEXCAN_ERROR_OK) + { + #else + tRetVal = FLEXCAN_ERROR_OK; + #endif + /* set started state */ + s_aCurrentSequence[u8CanIndex] = FLEXCAN_SEQUENCE_STARTED; + + pCan = (FLEXCAN_Type *)s_aFlexCan_InstanceTable[u8CanIndex]; + + u32TempMcr = FLEXCAN_HWA_GetMCR(pCan); + + u32TempMcr &= ~(FLEXCAN_MCR_FRZ(1U) | /* not frozen */ + FLEXCAN_MCR_HALT(1U) /* not halt */ + /*| FLEXCAN_MCR_SUPV(1) user mode */ + ); /* not reset */ + + FLEXCAN_HWA_SetMCR(pCan, u32TempMcr); + + if (FLEXCAN_HWA_WaitMcrExitFreezen(pCan, 10000U) != 0U) + { + tRetVal |= FLEXCAN_ERROR_TIMEOUT; + } + else + { + + if (FLEXCAN_HWA_WaitMcrReady(pCan, 10000U) != 0U) + { + tRetVal |= FLEXCAN_ERROR_TIMEOUT; + } + else + { + + s_aFlexCan_CanUsed[u8CanIndex] = 1U; + } + } + #if FLEXCAN_CHECK_PARAMETERS == STD_ON + } + #endif + + return tRetVal; +} + + +/** + * @brief Stop can instance + * + * @param u8CanIndex Can Index, must less than FLEXCAN_INSTANCE_COUNT + */ +FLEXCAN_ErrorType FLEXCAN_Stop(uint8_t u8CanIndex) +{ + FLEXCAN_ErrorType tRetVal; + uint32_t u32TempMcr; + FLEXCAN_Type *pCan; + + #if FLEXCAN_CHECK_PARAMETERS == STD_ON + /* check parameter */ + tRetVal = FLEXCAN_LL_CheckInstance(u8CanIndex); + + if ((tRetVal == FLEXCAN_ERROR_OK) && (s_aCurrentSequence[u8CanIndex] >= FLEXCAN_SEQUENCE_DEINIT)) + { + tRetVal = FLEXCAN_ERROR_OK; + } + else + { + tRetVal |= FLEXCAN_ERROR_INVALID_SEQUENCE; + } + + + if (tRetVal == FLEXCAN_ERROR_OK) + { + #else + tRetVal = FLEXCAN_ERROR_OK; + #endif + /* set started state */ + s_aCurrentSequence[u8CanIndex] = FLEXCAN_SEQUENCE_NOTSTART; + + pCan = (FLEXCAN_Type *)s_aFlexCan_InstanceTable[u8CanIndex]; + + u32TempMcr = FLEXCAN_HWA_GetMCR(pCan); + + u32TempMcr |= FLEXCAN_MCR_FRZ(1U) | /* not frozen */ + FLEXCAN_MCR_HALT(1U) /* not halt */ + /*| FLEXCAN_MCR_SUPV(1) user mode */ + ; /* not reset */ + + FLEXCAN_HWA_SetMCR(pCan, u32TempMcr); + + /* must wait */ + if (FLEXCAN_HWA_WaitMcrFreezen(pCan, 10000U) != 0U) + { + tRetVal |= FLEXCAN_ERROR_TIMEOUT; + } + else + { + + /* must wait */ + if (FLEXCAN_HWA_WaitMcrNoReady(pCan, 10000U) != 0U) + { + tRetVal |= FLEXCAN_ERROR_TIMEOUT; + } + else + { + s_aFlexCan_CanUsed[u8CanIndex] = 0U; + } + } + #if FLEXCAN_CHECK_PARAMETERS == STD_ON + } + + #endif + + return tRetVal; +} + + +/** + * @brief Transmit data, if tx disable, must call FLEXCAN_TransmitProcess after transmiting + * + * @param u8CanIndex Can Index, must less than FLEXCAN_INSTANCE_COUNT + * @param pTxMsg contains CAN instance, CAN ID, CAN FD and CAN data. + * @return 0 is ok + */ +FLEXCAN_ErrorType FLEXCAN_TransmitData(uint8_t u8CanIndex, const FLEXCAN_TxMsgType *const pTxMsg) +{ + FLEXCAN_ErrorType tRetVal; + uint32_t *pSrc; + uint32_t *pDest; + uint32_t u32Index; + FLEXCAN_Type *pCan; + FLEXCAN_SettingType *pCurSetting; + uint8_t u8TxRealMbIndex; + uint32_t u32WordLen; + uint32_t u32TempAddr; + uint32_t u32Code; + + #if FLEXCAN_CHECK_PARAMETERS == STD_ON + /* check parameter */ + tRetVal = FLEXCAN_LL_CheckInstance(u8CanIndex); + + if ((tRetVal == FLEXCAN_ERROR_OK) && (s_aCurrentSequence[u8CanIndex] == FLEXCAN_SEQUENCE_STARTED)) + { + tRetVal = FLEXCAN_ERROR_OK; + } + else + { + tRetVal |= FLEXCAN_ERROR_INVALID_SEQUENCE; + } + + if (pTxMsg == NULL) + { + tRetVal |= FLEXCAN_ERROR_INVALID_PARAM; + } + else + { + /* check buffer point if it is null */ + if (&(pTxMsg->aData) == NULL) + { + tRetVal |= FLEXCAN_ERROR_INVALID_PARAM; + } + else + { + if (pTxMsg->u32DataLen > (uint32_t)s_aFlexCan_Setting_Table[u8CanIndex].eMbDataWidth) + { + tRetVal |= FLEXCAN_ERROR_INVALID_PARAM; + } + } + } + + if ((pTxMsg->bEnFd == 1U) && (u8CanIndex >= FLEXCAN_FD_INSTANCE_COUNT)) + { + tRetVal |= FLEXCAN_ERROR_INVALID_PARAM; + } + + + if (tRetVal == FLEXCAN_ERROR_OK) + { + #endif + + pCan = (FLEXCAN_Type *)s_aFlexCan_InstanceTable[u8CanIndex]; + + pCurSetting = &s_aFlexCan_Setting_Table[u8CanIndex]; + if (pTxMsg->u8TxHandler >= pCurSetting->u8TxMbCnt1) + { + tRetVal = FLEXCAN_ERROR_INVALID_PARAM; + } + else + { + u8TxRealMbIndex = (uint8_t)(pTxMsg->u8TxHandler + pCurSetting->u8TxMbStart1); + + /* message buffer 1th word */ + u32TempAddr = (uint32_t)FLEXCAN_MB_WORDN_ADDR(&(pCan->RAM[0U]), u8TxRealMbIndex, pCurSetting->eMbDataWidth, 0U); + u32Code = FLEXCAN_MB_CODE_GET(u32TempAddr); + if((0x8 != u32Code) && (0U != u32Code)) + { + tRetVal = FLEXCAN_ERROR_BUSY; + } + else + { + + /* message buffer 1th word */ + u32TempAddr = (uint32_t)FLEXCAN_MB_WORDN_ADDR(&(pCan->RAM[0U]), u8TxRealMbIndex, pCurSetting->eMbDataWidth, 0U); + /* clear last value */ + FLEXCAN_REG32_CONTENT(u32TempAddr) = 0U; + + FLEXCAN_MB_EDL_SET(u32TempAddr, pTxMsg->bEnFd); + FLEXCAN_MB_BRS_SET(u32TempAddr, pTxMsg->bEnBrs); + + FLEXCAN_MB_IDE_SET(u32TempAddr, pTxMsg->eFrameType); + + /* SRR */ + FLEXCAN_MB_SRR_SET(u32TempAddr, 0U); + /* DLC */ + u32Index = FLEXCAN_DataLenToDlc(pTxMsg->u32DataLen); + FLEXCAN_MB_DLC_SET(u32TempAddr, u32Index); + + /* message buffer 2th word */ + u32TempAddr = (uint32_t)FLEXCAN_MB_WORDN_ADDR(&(pCan->RAM[0U]), u8TxRealMbIndex, pCurSetting->eMbDataWidth, 4U); + /* clear last value */ + FLEXCAN_REG32_CONTENT(u32TempAddr) = 0U; + + /* standard id */ + if (pTxMsg->eFrameType == FLEXCAN_ID_STD) + { + FLEXCAN_MB_STDID_SET(u32TempAddr, pTxMsg->u32CanId); + } + else /* extended id */ + { + FLEXCAN_MB_EXTID_SET(u32TempAddr, pTxMsg->u32CanId); + } + + FLEXCAN_MB_PRIO_SET(u32TempAddr, 0U); + + pSrc = (uint32_t *)(uint32_t)(&(pTxMsg->aData[0])); + /* message buffer 3th word */ + pDest = (uint32_t *)FLEXCAN_MB_WORDN_ADDR(&(pCan->RAM[0U]), u8TxRealMbIndex, pCurSetting->eMbDataWidth, 8U); + + u32WordLen = pTxMsg->u32DataLen / 4U + (pTxMsg->u32DataLen % 4U > 0U ? 1U : 0U); + + /* revert data to little endian */ + for (u32Index = 0U; u32Index < u32WordLen; u32Index++) + { + /* big endian to little endian */ + REV_BYTES_32(pSrc[u32Index], pDest[u32Index]); + } + + + /* message buffer 1th word */ + u32TempAddr = (uint32_t)FLEXCAN_MB_WORDN_ADDR(&(pCan->RAM[0U]), u8TxRealMbIndex, pCurSetting->eMbDataWidth, 0U); + + + /* CODE set 0x0C to transmit */ + FLEXCAN_MB_CODE_SET(u32TempAddr, 0x0CU); + + + if (pTxMsg->bWaitTxCompleted) + { + u32TempAddr = 0U; + u32WordLen = FLEXCAN_HWA_GetFlag1NoFifoFlag(pCan, u8TxRealMbIndex); + while ((u32WordLen == 0U) && (u32TempAddr++ < pTxMsg->u16WaitTxTimeout)) + { + u32WordLen = FLEXCAN_HWA_GetFlag1NoFifoFlag(pCan, u8TxRealMbIndex); + } + + if (u32WordLen == 0U) + { + tRetVal = FLEXCAN_ERROR_TIMEOUT; + } + + } + else + { + u32WordLen = FLEXCAN_HWA_GetFlag1NoFifoFlag(pCan, u8TxRealMbIndex); + if (u32WordLen == 0U) + { + tRetVal = FLEXCAN_ERROR_TIMEOUT; + } + } + + } + } + #if FLEXCAN_CHECK_PARAMETERS == STD_ON + } + #endif + + return tRetVal; +} + + +/** + * @brief Process flag after transmit + * + * @param u8CanIndex Can Index, must less than FLEXCAN_INSTANCE_COUNT + * @param u8Handler Transmit Handler + * @return 1 means process successfully and can transmit next time, 0 means no active flag, 0xff means out of range + */ +uint8_t FLEXCAN_TransmitProcess(uint8_t u8CanIndex, uint8_t u8TxHandler) +{ + #if FLEXCAN_CHECK_PARAMETERS == STD_ON + FLEXCAN_ErrorType tRetVal; + /* check parameter */ + tRetVal = FLEXCAN_LL_CheckInstance(u8CanIndex); + if (tRetVal == FLEXCAN_ERROR_OK) + { + #endif + return FLEXCAN_LL_ProcessTx(u8CanIndex, u8TxHandler); + #if FLEXCAN_CHECK_PARAMETERS == STD_ON + } + else + { + return 0U; + } + #endif +} + + +/** + * @brief Abort transmit with special transmit handler + * + * @param u8CanIndex Can Index, must less than FLEXCAN_INSTANCE_COUNT + * @param u8TxHandler Transmit handler + * @return 0 is ok + */ +FLEXCAN_ErrorType FLEXCAN_TransmitAbort(uint8_t u8CanIndex, uint8_t u8TxHandler) +{ + FLEXCAN_ErrorType tRetVal; + FLEXCAN_SettingType *pCurSetting; + FLEXCAN_Type *pCan; + uint8_t u8TxRealMbIndex; + uint32_t u32TempAddr; + + #if FLEXCAN_CHECK_PARAMETERS == STD_ON + /* check parameter */ + tRetVal = FLEXCAN_LL_CheckInstance(u8CanIndex); + + if ((tRetVal == FLEXCAN_ERROR_OK) && (s_aCurrentSequence[u8CanIndex] == FLEXCAN_SEQUENCE_STARTED)) + { + tRetVal = FLEXCAN_ERROR_OK; + } + else + { + tRetVal |= FLEXCAN_ERROR_INVALID_SEQUENCE; + } + + + if (tRetVal == FLEXCAN_ERROR_OK) + { + + #endif + + pCan = (FLEXCAN_Type *)s_aFlexCan_InstanceTable[u8CanIndex]; + + pCurSetting = &s_aFlexCan_Setting_Table[u8CanIndex]; + if (u8TxHandler >= pCurSetting->u8TxMbCnt1) + { + tRetVal = FLEXCAN_ERROR_INVALID_PARAM; + } + + else + { + u8TxRealMbIndex = (uint8_t)(u8TxHandler + pCurSetting->u8TxMbStart1); + /* message buffer 1th word */ + u32TempAddr = (uint32_t)FLEXCAN_MB_WORDN_ADDR(&(pCan->RAM[0U]), u8TxRealMbIndex, pCurSetting->eMbDataWidth, 0U); + + + /* CODE set 0x09 to aborting transmit */ + FLEXCAN_MB_CODE_SET(u32TempAddr, 0x09U); + } + #if FLEXCAN_CHECK_PARAMETERS == STD_ON + } + #endif + + return tRetVal; +} + + +/** + * @brief Receive data when polling (not used when rx interrupt enabled) + * + * @param u8CanIndex Can Index, must less than FLEXCAN_INSTANCE_COUNT + * @param pRxBufList is FLEXCAN_RxMsgType type point point, and don't need to be initialed + * @return 0 is ok + */ +FLEXCAN_ErrorType FLEXCAN_Receive_Polling(uint8_t u8CanIndex, FLEXCAN_RxMsgListType *const pRxBufList) +{ + FLEXCAN_ErrorType tRetVal; + uint8_t u8RetVal; + + #if FLEXCAN_CHECK_PARAMETERS == STD_ON + /* check parameter */ + tRetVal = FLEXCAN_LL_CheckInstance(u8CanIndex); + + if ((tRetVal == FLEXCAN_ERROR_OK) && (s_aCurrentSequence[u8CanIndex] == FLEXCAN_SEQUENCE_STARTED)) + { + tRetVal = FLEXCAN_ERROR_OK; + } + else + { + tRetVal |= FLEXCAN_ERROR_INVALID_SEQUENCE; + } + + if (pRxBufList == NULL) + { + tRetVal |= FLEXCAN_ERROR_INVALID_PARAM; + } + + + if (tRetVal == FLEXCAN_ERROR_OK) + { + + #else + tRetVal = FLEXCAN_ERROR_OK; + #endif + u8RetVal = 0U; + + pRxBufList->u8RxMsgCnt = 0U; + pRxBufList->pRxMsgBuf = s_aFlexCan_Setting_Table[u8CanIndex].pRxBuf; + + + if (s_aFlexCan_CanUsed[u8CanIndex] == 1U) + { + /* receive from fifo or normal */ + if (s_aFlexCan_Setting_Table[u8CanIndex].bEnableFifo) + { + u8RetVal = FLEXCAN_LL_ReceiveFifo(u8CanIndex, s_aFlexCan_Setting_Table[u8CanIndex].bEnableFd, pRxBufList->pRxMsgBuf); + } + else + { + u8RetVal = FLEXCAN_LL_PollingMb(u8CanIndex, pRxBufList->pRxMsgBuf); + } + pRxBufList->u8RxMsgCnt = u8RetVal; + } + #if FLEXCAN_CHECK_PARAMETERS == STD_ON + } + #endif + + return tRetVal; +} + + + +/** + * @brief Get can error + * + * @param u8CanIndex Can Index, must less than FLEXCAN_INSTANCE_COUNT + * @param pErrorInfo is error information + * @return 0 is no error, others contains error + */ +FLEXCAN_ErrorType FLEXCAN_GetErrorInfo(uint8_t u8CanIndex, FLEXCAN_ErrorInfoType *const pErrorInfo) +{ + FLEXCAN_ErrorType tRetVal; + uint32_t u32ESR1Status, u32ECRStatus; + FLEXCAN_Type *pCan; + + #if FLEXCAN_CHECK_PARAMETERS == STD_ON + /* check parameter */ + tRetVal = FLEXCAN_LL_CheckInstance(u8CanIndex); + + if ((tRetVal == FLEXCAN_ERROR_OK) && (s_aCurrentSequence[u8CanIndex] >= FLEXCAN_SEQUENCE_NOTSTART)) + { + tRetVal = FLEXCAN_ERROR_OK; + } + else + { + tRetVal |= FLEXCAN_ERROR_INVALID_SEQUENCE; + } + + + if (tRetVal == FLEXCAN_ERROR_OK) + { + + #else + tRetVal = FLEXCAN_ERROR_OK; + #endif + pCan = (FLEXCAN_Type *)s_aFlexCan_InstanceTable[u8CanIndex]; + + u32ESR1Status = FLEXCAN_HWA_GetErrorInfo(pCan); + pErrorInfo->u32ErrorValue = u32ESR1Status; + + u32ECRStatus = FLEXCAN_HWA_GetErrorCount(pCan); + pErrorInfo->u32ErrorValue &= FLEXCAN_ESR1_BIT1ERR_FAST_MASK | FLEXCAN_ESR1_BIT0ERR_FAST_MASK | FLEXCAN_ESR1_CRCERR_FAST_MASK | FLEXCAN_ESR1_FRMERR_FAST_MASK | + FLEXCAN_ESR1_STFERR_FAST_MASK | + FLEXCAN_ESR1_ERROVR_MASK | FLEXCAN_ESR1_ERRINT_FAST_MASK | FLEXCAN_ESR1_BOFFDONEINT_MASK | FLEXCAN_ESR1_TWRNINT_MASK | FLEXCAN_ESR1_RWRNINT_MASK | + FLEXCAN_ESR1_BIT1ERR_MASK | FLEXCAN_ESR1_BIT0ERR_MASK | FLEXCAN_ESR1_ACKERR_MASK | FLEXCAN_ESR1_CRCERR_MASK | FLEXCAN_ESR1_FRMERR_MASK | FLEXCAN_ESR1_STFERR_MASK | + FLEXCAN_ESR1_TXWRN_MASK | FLEXCAN_ESR1_RXWRN_MASK | FLEXCAN_ESR1_FLTCONF_MASK | FLEXCAN_ESR1_BOFFINT_MASK | FLEXCAN_ESR1_ERRINT_MASK; + + if(pErrorInfo->u32ErrorValue & FLEXCAN_ESR1_BIT1ERR_FAST_MASK) + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_BIT1ERR_FAST = 1U; + else + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_BIT1ERR_FAST = 0U; + + if(pErrorInfo->u32ErrorValue & FLEXCAN_ESR1_BIT0ERR_FAST_MASK) + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_BIT0ERR_FAST = 1U; + else + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_BIT0ERR_FAST = 0U; + + if(pErrorInfo->u32ErrorValue & FLEXCAN_ESR1_CRCERR_FAST_MASK) + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_CRCERR_FAST = 1U; + else + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_CRCERR_FAST = 0U; + + if(pErrorInfo->u32ErrorValue & FLEXCAN_ESR1_FRMERR_FAST_MASK) + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_FRMERR_FAST = 1U; + else + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_FRMERR_FAST = 0U; + + if(pErrorInfo->u32ErrorValue & FLEXCAN_ESR1_STFERR_FAST_MASK) + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_STFERR_FAST = 1U; + else + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_STFERR_FAST = 0U; + + if(pErrorInfo->u32ErrorValue & FLEXCAN_ESR1_ERROVR_MASK) + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_ERROVR = 1U; + else + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_ERROVR = 0U; + + if(pErrorInfo->u32ErrorValue & FLEXCAN_ESR1_ERRINT_FAST_MASK) + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_ERRINT_FAST = 1U; + else + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_ERRINT_FAST = 0U; + + if(pErrorInfo->u32ErrorValue & FLEXCAN_ESR1_BOFFDONEINT_MASK) + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_BOFFDONEINT = 1U; + else + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_BOFFDONEINT = 0U; + + if(pErrorInfo->u32ErrorValue & FLEXCAN_ESR1_TWRNINT_MASK) + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_TWRNINT = 1U; + else + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_TWRNINT = 0U; + + if(pErrorInfo->u32ErrorValue & FLEXCAN_ESR1_RWRNINT_MASK) + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_RWRNINT = 1U; + else + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_RWRNINT = 0U; + + if(pErrorInfo->u32ErrorValue & FLEXCAN_ESR1_BIT1ERR_MASK) + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_BIT1ERR = 1U; + else + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_BIT1ERR = 0U; + + if(pErrorInfo->u32ErrorValue & FLEXCAN_ESR1_BIT0ERR_MASK) + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_BIT0ERR = 1U; + else + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_BIT0ERR = 0U; + + if(pErrorInfo->u32ErrorValue & FLEXCAN_ESR1_ACKERR_MASK) + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_ACKERR = 1U; + else + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_ACKERR = 0U; + + if(pErrorInfo->u32ErrorValue & FLEXCAN_ESR1_CRCERR_MASK) + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_CRCERR = 1U; + else + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_CRCERR = 0U; + + if(pErrorInfo->u32ErrorValue & FLEXCAN_ESR1_FRMERR_MASK) + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_FRMERR = 1U; + else + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_FRMERR = 0U; + + if(pErrorInfo->u32ErrorValue & FLEXCAN_ESR1_STFERR_MASK) + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_STFERR = 1U; + else + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_STFERR = 0U; + + if(pErrorInfo->u32ErrorValue & FLEXCAN_ESR1_TXWRN_MASK) + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_TXWRN = 1U; + else + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_TXWRN = 0U; + + if(pErrorInfo->u32ErrorValue & FLEXCAN_ESR1_RXWRN_MASK) + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_RXWRN = 1U; + else + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_RXWRN = 0U; + + if(pErrorInfo->u32ErrorValue & FLEXCAN_ESR1_FLTCONF_MASK) + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_FLTCONF = 1U; + else + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_FLTCONF = 0U; + + if(pErrorInfo->u32ErrorValue & FLEXCAN_ESR1_BOFFINT_MASK) + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_BOFFINT = 1U; + else + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_BOFFINT = 0U; + + if(pErrorInfo->u32ErrorValue & FLEXCAN_ESR1_ERRINT_MASK) + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_ERRINT = 1U; + else + pErrorInfo->tErrorDetail.u8Error_FLEXCAN_ESR1_ERRINT = 0U; + + pErrorInfo->u32RxErrCnt = (u32ECRStatus & FLEXCAN_ECR_RXERRCNT_MASK) >> FLEXCAN_ECR_RXERRCNT_SHIFT; + pErrorInfo->u32RxErrCnt_Fast = (u32ECRStatus & FLEXCAN_ECR_RXERRCNT_FAST_MASK) >> FLEXCAN_ECR_RXERRCNT_FAST_SHIFT; + pErrorInfo->u32TxErrCnt = (u32ECRStatus & FLEXCAN_ECR_TXERRCNT_MASK) >> FLEXCAN_ECR_TXERRCNT_SHIFT; + pErrorInfo->u32TxErrCnt_Fast = (u32ECRStatus & FLEXCAN_ECR_TXERRCNT_FAST_MASK) >> FLEXCAN_ECR_TXERRCNT_FAST_SHIFT; + + #if FLEXCAN_CHECK_PARAMETERS == STD_ON + } + else + { + PROCESS_UNUSED_VAR(u32ESR1Status); + PROCESS_UNUSED_VAR(u32ECRStatus); + } + #endif + + return tRetVal; +} + +/** + * @brief Clear can error + * + * @param u8CanIndex Can Index, must less than FLEXCAN_INSTANCE_COUNT + * @param pErrorInfo is error information + * @return 0 is no error, others contains error + */ +FLEXCAN_ErrorType FLEXCAN_ClrErrorInfo(uint8_t u8CanIndex, const FLEXCAN_ErrorInfoType *const pErrorInfo) +{ + FLEXCAN_ErrorType tRetVal; + FLEXCAN_Type *pCan; + + #if FLEXCAN_CHECK_PARAMETERS == STD_ON + /* check parameter */ + tRetVal = FLEXCAN_LL_CheckInstance(u8CanIndex); + + if ((tRetVal == FLEXCAN_ERROR_OK) && (s_aCurrentSequence[u8CanIndex] >= FLEXCAN_SEQUENCE_NOTSTART)) + { + tRetVal = FLEXCAN_ERROR_OK; + } + else + { + tRetVal |= FLEXCAN_ERROR_INVALID_SEQUENCE; + } + + + if (tRetVal == FLEXCAN_ERROR_OK) + { + #else + tRetVal = FLEXCAN_ERROR_OK; + #endif + pCan = (FLEXCAN_Type *)s_aFlexCan_InstanceTable[u8CanIndex]; + + FLEXCAN_HWA_ClrErrorInfo(pCan, pErrorInfo->u32ErrorValue); + #if FLEXCAN_CHECK_PARAMETERS == STD_ON + } + #endif + + return tRetVal; +} + + + + +/** + * @brief Transfer Data length to DLC + * + * @param u32DataLen data length + * @return DLC + */ +uint32_t FLEXCAN_DataLenToDlc(uint32_t u32DataLen) +{ + uint32_t u32Dlc; + + switch (u32DataLen) + { + case 0U: + case 1U: + case 2U: + case 3U: + case 4U: + case 5U: + case 6U: + case 7U: + case 8U: + { + u32Dlc = u32DataLen; + } + break; + case 12U: + { + u32Dlc = 9U; + } + break; + case 16U: + { + u32Dlc = 10U; + } + break; + case 20U: + { + u32Dlc = 11U; + } + break; + case 24U: + { + u32Dlc = 12U; + } + break; + case 32U: + { + u32Dlc = 13U; + } + break; + case 48U: + { + u32Dlc = 14U; + } + break; + case 64U: + { + u32Dlc = 15U; + + } + break; + + default: + u32Dlc = 0U; + break; + } + + return u32Dlc; +} + + +/** + * @brief Transfer DLC to Data length + * + * @param u32Dlc DLC Data Length + * @return + */ +uint32_t FLEXCAN_DlcToDataLen(uint32_t u32Dlc) +{ + uint32_t u32DataLen; + + + switch (u32Dlc) + { + case 0U: + case 1U: + case 2U: + case 3U: + case 4U: + case 5U: + case 6U: + case 7U: + case 8U: + { + u32DataLen = u32Dlc; + } + break; + case 9U: + { + u32DataLen = 12U; + } + break; + case 10U: + { + u32DataLen = 16U; + } + break; + case 11U: + { + u32DataLen = 20U; + } + break; + case 12U: + { + u32DataLen = 24U; + } + break; + case 13U: + { + u32DataLen = 32U; + } + break; + case 14U: + { + u32DataLen = 48U; + } + break; + case 15U: + { + u32DataLen = 64U; + } + break; + + default: + u32DataLen = 0U; + break; + } + + return u32DataLen; +} + + +/* ################################################################################## */ +/* ############################## Interrupt Services ################################ */ + +/** + * @brief Can interrupt process + * + * @param u8CanIndex Can Index, Must less than FLEXCAN_INSTANCE_COUNT + */ +void FLEXCAN_IRQHandler(uint8_t u8CanIndex) +{ + uint8_t u8RecNum, u8Index; + uint32_t u32Flag1, u32ERFSR; + FLEXCAN_Type *pCan; + FLEXCAN_RxMsgType *pRxMsgList; + uint8_t u8FifoInterrupt; + FLEXCAN_ErrorType tRetVal; + + FLEXCAN_ErrorInfoType pErrorInfo; + + #if FLEXCAN_CHECK_PARAMETERS == STD_ON + /* check parameter */ + tRetVal = FLEXCAN_LL_CheckInstance(u8CanIndex); + if (tRetVal == FLEXCAN_ERROR_OK) + { + #endif + + pCan = (FLEXCAN_Type *)s_aFlexCan_InstanceTable[u8CanIndex]; + + FLEXCAN_GetErrorInfo(u8CanIndex, &pErrorInfo); + + pRxMsgList = s_aFlexCan_Setting_Table[u8CanIndex].pRxBuf; + + u32Flag1 = FLEXCAN_HWA_GetFlag1(pCan); + + + /* check pCan error */ + if (pErrorInfo.u32ErrorValue != 0U) + { + /* error notification */ + if (s_aFlexCan_ErrorNotifyTable[u8CanIndex] != NULL) + { + /* clear can error */ + s_aFlexCan_ErrorNotifyTable[u8CanIndex](u8CanIndex, &pErrorInfo); + } + } + + tRetVal = FLEXCAN_LL_CheckFdInstance(u8CanIndex); + + if (tRetVal == FLEXCAN_ERROR_OK) + { + u32ERFSR = FLEXCAN_HWA_ERFSRGetEnhancedFifoFlag(pCan, FLEXCAN_ERFSR_ERFDA_SHIFT, FLEXCAN_ERFSR_ERFDA_MASK); + u8FifoInterrupt = ((true == s_aFlexCan_Setting_Table[u8CanIndex].bEnableFd) && (0U != u32ERFSR) && (s_aFlexCan_Setting_Table[u8CanIndex].bEnableFifoInt)); + } + else + { + u8FifoInterrupt = 0U; + } + u8FifoInterrupt = (uint8_t)(u8FifoInterrupt | ((false == s_aFlexCan_Setting_Table[u8CanIndex].bEnableFd) && (u32Flag1 & 0x20U) && + (s_aFlexCan_Setting_Table[u8CanIndex].bEnableFifoInt))); + + /* check pCan receive data from fifo or normal */ + if ((s_aFlexCan_Setting_Table[u8CanIndex].bEnableFifo) && u8FifoInterrupt) + { + u8RecNum = FLEXCAN_LL_ReceiveFifo(u8CanIndex, s_aFlexCan_Setting_Table[u8CanIndex].bEnableFd, pRxMsgList); + /* rx notification */ + if ((u8RecNum > 0U) && (s_aFlexCan_RxFifoNotifyTable[u8CanIndex] != NULL)) + { + for (u8Index = 0U; u8Index < u8RecNum; u8Index++) + { + s_aFlexCan_RxFifoNotifyTable[u8CanIndex](u8CanIndex, &pRxMsgList[u8Index]); + } + } + } + + /* check transmit interrupt */ + if (s_aFlexCan_Setting_Table[u8CanIndex].bEnableTxMBInt) + { + for (u8Index = 0U; u8Index < s_aFlexCan_Setting_Table[u8CanIndex].u8TxMbCnt1; u8Index++) + { + u8RecNum = FLEXCAN_LL_ProcessTx(u8CanIndex,u8Index); + if ((u8RecNum == 1U) && (s_aFlexCan_TxNotifyTable[u8CanIndex] != NULL)) + { + s_aFlexCan_TxNotifyTable[u8CanIndex](u8CanIndex, u8Index); + } + } + } + + /* check receive interrupt */ + if (s_aFlexCan_Setting_Table[u8CanIndex].bEnableRxMBInt) + { + u8RecNum = FLEXCAN_LL_PollingMb(u8CanIndex, pRxMsgList); + if ((u8RecNum > 0U) && (s_aFlexCan_RxNotifyTable[u8CanIndex] != NULL)) + { + for (u8Index = 0U; u8Index < u8RecNum; u8Index++) + { + s_aFlexCan_RxNotifyTable[u8CanIndex](u8CanIndex, &pRxMsgList[u8Index]); + } + } + } + + PROCESS_UNUSED_VAR(pCan); + + #if FLEXCAN_CHECK_PARAMETERS == STD_ON + } + #endif +} + +bool IsTxBufferFree_ByCode(uint8_t canIndex, uint8_t handler) { + FLEXCAN_Type *pCan = s_aFlexCan_InstanceTable[canIndex]; + FLEXCAN_SettingType *pCurSetting = &s_aFlexCan_Setting_Table[canIndex]; + + if (handler >= pCurSetting->u8TxMbCnt1) { + return false; // Неверный handler + } + + uint8_t realIndex = pCurSetting->u8TxMbStart1 + handler; + + // Читаем код из первого слова MB + uint32_t addr = (uint32_t)FLEXCAN_MB_WORDN_ADDR( + &(pCan->RAM[0U]), realIndex, pCurSetting->eMbDataWidth, 0U); + + uint32_t code = FLEXCAN_MB_CODE_GET(addr); + + // Коды состояния буфера: + // 0x0 = EMPTY (не использовался) - СВОБОДЕН + // 0x8 = INACTIVE (неактивен) - СВОБОДЕН + // 0xC = TRANSMITTING (передаёт) - ЗАНЯТ + // 0x9 = ABORTING (прерывается) - ЗАНЯТ + + return (code == 0x0 || code == 0x8); +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_fmc.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_fmc.c new file mode 100644 index 0000000..221194a --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_fmc.c @@ -0,0 +1,231 @@ +/** + * @file fc7xxx_driver_fmc.c + * @author Flagchip + * @brief FC7xxx Fmc driver source code + * @version 0.1.0 + * @date 2024-1-5 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-1-5 Flagchip120 N/A First version for FC7240 + ******************************************************************************** */ + +#include "fc7xxx_driver_fmc.h" + +/* ################################################################################## */ +/* ####################################### Macro #################################### */ + + +/* ################################################################################## */ +/* ################################ Local Variables ################################# */ +static FMC_Type *const s_apFmcBase[FMC_INSTANCE_COUNT] = FMC_BASE_PTRS; + +/* ################################################################################## */ +/* ########################### Local Prototype Functions ############################ */ + + +/** + * \brief FMC PFlash Driver Function for lock/unlock sector + * + * \param pFMC FMC instance + * \param u32Address sector address + * \param bLock 0U-unlock, 1U-lock + */ +static FMC_Lock_StatusType FMCDRIVER_PFlashLockRegion(const FMC_InstanceType eInstance, uint32_t u32Address, uint8_t bLock); + +/** + * \brief FMC DFlash Driver Function for lock/unlock sector + * + * \param pFMC FMC instance + * \param u32Address sector address + * \param bLock 0U-unlock, 1U-lock + */ +static FMC_Lock_StatusType FMCDRIVER_DFlashLockRegion(const FMC_InstanceType eInstance, uint32_t u32Address, uint8_t bLock); + +/* ################################################################################## */ +/* ########################### Global Prototype Functions ########################### */ + + +/* ################################################################################## */ +/* ################################ Local Functions ################################# */ + +/** + * \brief FMC PFlash Driver Function for lock/unlock sector + * + * \param eInstance FMC instance + * \param u32Address sector address + * \param bLock 0U-unlock, 1U-lock + */ +static FMC_Lock_StatusType FMCDRIVER_PFlashLockRegion(const FMC_InstanceType eInstance, uint32_t u32Address, uint8_t bLock) +{ + FMC_Type *const pFMC = s_apFmcBase[eInstance]; + FMC_Lock_StatusType tRetVal; + uint32_t u32Index; + uint32_t u32Length; + uint32_t u32Temp; + + tRetVal = FMC_LOCK_ERROR_OK; + + /* 1 bank contains more than 256KB, used FB_CPELCK for first and last 256KB used FB_FPELCK */ + if ((u32Address >= PFLASH_ADDR_START) && (u32Address <= (PFLASH_ADDR_START + PFLASH_TOTAL_SIZE))) + { + /* PFLASH bank index */ + u32Index = (u32Address - PFLASH_ADDR_START) / PFLASH_BANK_SIZE; + u32Length = ((u32Address - PFLASH_ADDR_START) % PFLASH_BANK_SIZE) ; + if (u32Length < (PFLASH_BANK_SIZE - FLASH_256KB_SIZE)) /* first 768KB */ + { + u32Temp = ((uint32_t)1UL << ((u32Address - PFLASH_ADDR_START - PFLASH_BANK_SIZE * u32Index) >> 16)); + u32Temp = bLock ? (FMC_HWA_GetFBCPELCKValue(pFMC, u32Index) | u32Temp) : (FMC_HWA_GetFBCPELCKValue(pFMC, u32Index) & ~u32Temp); + FMC_HWA_SetFBCPELCKValue(pFMC, u32Index, u32Temp); + } + else /* last 256KB */ + { + u32Temp = ((u32Address - PFLASH_ADDR_START - PFLASH_BANK_SIZE * u32Index - PFLASH_PHANTOM_OFFSET) >> 13); + u32Temp = ((uint32_t)1UL << u32Temp); + u32Temp = bLock ? (FMC_HWA_GetFBFPELCKValue(pFMC, u32Index) | u32Temp) : (FMC_HWA_GetFBFPELCKValue(pFMC, u32Index) & ~u32Temp); + FMC_HWA_SetFBFPELCKValue(pFMC, u32Index, u32Temp); + } + } + else + { + tRetVal = FMC_LOCK_ERROR_INVALID_ADDR; + } + return tRetVal; +} + + +/** + * \brief FMC DFlash Driver Function for lock/unlock sector + * + * \param eInstance FMC instance + * \param u32Address sector address + * \param bLock 0U-unlock, 1U-lock + */ +static FMC_Lock_StatusType FMCDRIVER_DFlashLockRegion(const FMC_InstanceType eInstance, uint32_t u32Address, uint8_t bLock) +{ + FMC_Type *const pFMC = s_apFmcBase[eInstance]; + FMC_Lock_StatusType tRetVal; + uint32_t u32Index; + uint32_t u32Temp; + tRetVal = FMC_LOCK_ERROR_OK; + + /* 1 bank contains only 128KB, only used FB_FPELCK */ + u32Index = 2U; + if ((u32Address >= DFLASH_ADDR_START) && (u32Address <= DFLASH_ADDR_END)) + { + u32Temp = 1UL << ((u32Address - DFLASH_ADDR_START - DFLASH_BANK0_SIZE_ * (u32Index - 2U)) >> 13); + u32Temp = bLock ? (FMC_HWA_GetFBFPELCKValue(pFMC, u32Index) | u32Temp) : (FMC_HWA_GetFBFPELCKValue(pFMC, u32Index) & ~u32Temp); + FMC_HWA_SetFBFPELCKValue(pFMC, u32Index, u32Temp); + } + else + { + tRetVal = FMC_LOCK_ERROR_INVALID_ADDR; + } + return tRetVal; +} + + +/* ################################################################################## */ +/* ################################# Global Functions ############################### */ + +/** + * \brief FMC Driver Function for flash lock + * + * \param pFmcParam FMC driver flash lock parameter + * \return ErrorType + */ +FMC_Lock_StatusType FMCDRIVER_FlashLock(FMC_DRIVER_Lock_ParamType *pFmcParam) +{ + uint32_t u32Addr, u32Length, u32LockSize, u32TempAddr; + + FMC_Lock_StatusType tRetVal; + tRetVal = FMC_LOCK_ERROR_OK; + + u32Addr = pFmcParam->u32Address; + u32Length = pFmcParam->u32Length; + u32LockSize = (pFmcParam->bClass == FMC_Page) ? FLASH_PROGRAM_PAGE_SIZE : FLASH_ERASE_SECTOR_SIZE; + + /* Address and length should aligned by page/sector */ + if (pFmcParam->u32Address & (u32LockSize - 1U)) + { + tRetVal = FMC_LOCK_ERROR_INVALID_ADDR; + pFmcParam->u32ErrorAddress = pFmcParam->u32Address; + } + if (pFmcParam->u32Length & (u32LockSize - 1U)) + { + tRetVal = FMC_LOCK_ERROR_INVALID_SIZE; + pFmcParam->u32ErrorAddress = pFmcParam->u32Address; + } + + if (tRetVal == FMC_LOCK_ERROR_OK) + { + for (u32TempAddr = u32Addr; u32TempAddr < u32Addr + u32Length; u32TempAddr += u32LockSize) + { + if (pFmcParam->bFlash == FMC_PFlash) + { + tRetVal = FMCDRIVER_PFlashLockRegion(pFmcParam->bFMC, u32TempAddr, pFmcParam->bLock); + } + else + { + tRetVal = FMCDRIVER_DFlashLockRegion(pFmcParam->bFMC, u32TempAddr, pFmcParam->bLock); + } + } + } + return tRetVal; +} + +/** + * \brief FMC set ota active block + * + * \param eInstance FMC instance + * \param bLock 0U-active block 0, 1U-active block 1 + */ +void FMCDRIVER_SwapBlock(const FMC_InstanceType eInstance, FMC_API_ACTIVE_BLOCK_TYPE bActive) +{ + FMC_Type *const pFMC = s_apFmcBase[eInstance]; + if (0U == FMC_HWA_GetOTACtrlValue(pFMC, 0)) + { + FMC_HWA_SetOTAActive(pFMC, 0, bActive); + FMC_HWA_SetOTAEnable(pFMC, 0); + } +} + +/** + * \brief Get current active OTA block + * + * \param eInstance FMC instance + * \return Current active block (FMC_Active0 or FMC_Active1) + * Returns FMC_Active0 by default if OTA is not enabled or error + */ +FMC_API_ACTIVE_BLOCK_TYPE FMCDRIVER_GetActiveBlock(const FMC_InstanceType eInstance) +{ + FMC_Type *const pFMC = s_apFmcBase[eInstance]; + + // Validate instance + if ((eInstance >= FMC_INSTANCE_COUNT) || (pFMC == NULL)) + { + return FMC_Active0; + } + + // Read OTA_CTRL register + uint32_t u32OTACtrl = FMC_HWA_GetOTACtrlValue(pFMC, 0U); + + // Check if OTA is enabled (0xA = enabled) + uint32_t u32OTAEn = (u32OTACtrl & FMC_OTA_CTRL_OTA_EN_MASK) >> FMC_OTA_CTRL_OTA_EN_SHIFT; + + if (u32OTAEn != 0xA) + { + // OTA not enabled - no swapping configured, return default Bank 0 + return FMC_Active0; + } + + // OTA is enabled - read which bank is active + uint32_t u32Active = (u32OTACtrl & FMC_OTA_CTRL_OTA_ACTIVE_MASK) >> FMC_OTA_CTRL_OTA_ACTIVE_SHIFT; + + return (FMC_API_ACTIVE_BLOCK_TYPE)u32Active; +} \ No newline at end of file diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_fpu.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_fpu.c new file mode 100644 index 0000000..3a76265 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_fpu.c @@ -0,0 +1,51 @@ +/** + * @file fc7xxx_driver_fpu.c + * @author Flagchip051 + * @brief FC4xxx FPU driver type definition and API + * @version 0.1.0 + * @date 2024-01-11 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-11 Flagchip054 N/A First version for FC7240 + ******************************************************************************** */ + +#include "fc7xxx_driver_fpu.h" + +/* Note: library user should add interrupt stack support, add compiler support */ +/* + * @details @verbatim +If only want use FPU, +1) configure FCIDE to enable FPU compiler support, "Properties" -> C/C++ Build -> Settings -> Tool Settings -> Target Processor -> Float ABI -> FP instructions(hard) -> FPU Type set to "fpv5-sp-d16" +2) configure FCIDE to enable FPU compiler support, "Properties" -> C/C++ Build -> Settings -> Tool Settings -> GNU Arm Cross C Compiler -> Preprocessor -> Defined symbols(-D) -> Add "__FPU_PRESENT=1" (without ") +3) and call FPU_Enable to enable FPU at the beginning of program. + +If want to use DSP, +1) configure FCIDE to enable FPU compiler support, Properties -> C/C++ Build -> Settings -> Tool Settings -> Target Processor -> Float ABI -> FP instructions(hard) +2) add MACRO "DRIVER_CM7_DSP_ENABLE" in FCIDE Properties -> C/C++ General -> Paths and Symbols -> Symbols -> GNU C and GNU C++ and Assembly +3) add Include Path to project Properties -> C/C++ General -> Paths and Symbols -> Includes -> GNU C and GNU C++ and Assembly: + ../../../../../../Template/Device/CMSIS5_590/DSP/Include + ../../../../../../Template/Device/CMSIS5_590/Core/Include + ../../../../../../Template/Device/CMSIS5_590/DSP/PrivateInclude +4) and call FPU_Enable to enable FPU at the beginning of program. + @endverbatim + */ + +void FPU_Enable(void) +{ + FPU_HWA_Enable(); /* set CP10 and CP11 Full Access */ + __DSB(); + __ISB(); +} + +void FPU_Disable(void) +{ + FPU_HWA_Disable(); /* Access denied. Any attempted access generates a NOCP UsageFault */ +} + diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_freqm.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_freqm.c new file mode 100644 index 0000000..530751a --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_freqm.c @@ -0,0 +1,186 @@ +/** + * @file fc7xxx_driver_freqm.c + * @author Flagchip + * @brief FC7xxx FREQM driver type definition and API + * @version 0.1.0 + * @date 2024-01-14 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-14 qxw0100 N/A First version for FC7240 + ******************************************************************************** */ + +#include "fc7xxx_driver_freqm.h" +#include "fc7xxx_driver_pcc.h" +#include "interrupt_manager.h" + +/********* Local variable ************/ +static FREQM_Type * const pFreqmPtrs = FREQM; + +static FREQM_MesCntStartCallBackType s_pMesCntStartCallback = NULL; +static FREQM_MesCntStopCallBackType s_pMesCntStopCallback = NULL; +static FREQM_RefCntStopCallBackType s_pRefCntStopCallback = NULL; +static FREQM_FaultCallBackType s_pFaultCallback = NULL; + + +/********* Global Functions ************/ +/** + * @brief Initialize FREQM configuration + * + * @param pInitStruct the basic configurations of the FREQM + * @return FREQM_StatusType whether the operation is successfully + */ +FREQM_StatusType FREQM_Init(const FREQM_InitType *const pInitStruct) +{ + FREQM_StatusType eRet = FREQM_STATUS_SUCCESS; + if (NULL == pInitStruct) + { + eRet = FREQM_STATUS_PARAM_INVALID; + } + else + { + /* Configure the clock divider value */ + FREQM_HWA_MesClk_PreDiv(pFreqmPtrs,pInitStruct->u8PredivVal); + /* Select the clock source to be measured */ + FREQM_HWA_MesClkSel(pFreqmPtrs,pInitStruct->eClkSel); + /* Set and clear the S/W reset */ + PCC_GenPeripheralReset(PCC_CLK_FREQM); + /* Configure the measure counter targer value */ + FREQM_HWA_SetMesLength(pFreqmPtrs,pInitStruct->u32MesLen); + /* Configure the reference counter target value */ + FREQM_HWA_SetRefTimeout(pFreqmPtrs,pInitStruct->u32RefTo); + } + return eRet; +} + +/** + * @brief De-initialize the FREQM + * + * @param eInstance the selected FREQM + * @return FREQM_StatusType whether the operation is successfully + */ +FREQM_StatusType FREQM_DeInit() +{ + FREQM_StatusType eStatus = FREQM_STATUS_SUCCESS; + /* Set register to reset value */ + FREQM_HWA_MesClk_PreDiv(pFreqmPtrs,0U); + FREQM_HWA_MesClkSel(pFreqmPtrs,(FREQM_MesClkSelType)0); + FREQM_HWA_SetMesLength(pFreqmPtrs,0xFFFFFFFFU); + FREQM_HWA_SetRefTimeout(pFreqmPtrs,0xFFFFFFFFU); + + FREQM_HWA_DisableCntEventInterrupt(pFreqmPtrs); + s_pMesCntStartCallback = NULL; + s_pMesCntStopCallback = NULL; + s_pRefCntStopCallback = NULL; + s_pFaultCallback = NULL; + + return eStatus; +} + +/** + * @brief Clear all FREQM status + * + * @return FREQM_StatusType whether the operation is successfully + */ +FREQM_StatusType FREQM_ClearStatus() +{ + FREQM_StatusType eStatus = FREQM_STATUS_SUCCESS; + uint32_t u32TimeOutVal = 0xffff; + uint32_t u32CntStatus; + + FREQM_HWA_SetRefCnt(pFreqmPtrs,0U); + + do + { + u32CntStatus = FREQM_HWA_GetCntStatus(pFreqmPtrs); + u32TimeOutVal--; + }while(u32CntStatus!=0U); + + if(u32TimeOutVal == 0U) + { + eStatus = FREQM_STATUS_TIMEOUT; + } + return eStatus; +} + +/** + * @brief Start the reference/measure counter + * + */ +void FREQM_StartMeasureCnt() +{ + FREQM_HWA_SetMesCnt(pFreqmPtrs,0U); +} + +/** + * @brief Get saved reference counter value + * + * @return uint32_t saved reference counter value + */ +uint32_t FREQM_GetRefCntSave() +{ + return FREQM_HWA_GetRefCntSave(pFreqmPtrs); +} + +/** + * @brief FREQM initialize interrupt function + * + * @param pIntStruct FREQM interrupt structure + * @return FREQM_StatusType whether the operation is successfully + */ +FREQM_StatusType FREQM_InterruptInit(const FREQM_InterruptType *const pIntrStruct) +{ + FREQM_StatusType eStatus = FREQM_STATUS_SUCCESS; + + FREQM_HWA_EnableCntEventInterrupt(pFreqmPtrs); + /*register callback functions*/ + s_pMesCntStartCallback = pIntrStruct->pMesCntStartCallback; + s_pMesCntStopCallback = pIntrStruct->pMesCntStopCallback; + s_pRefCntStopCallback = pIntrStruct->pRefCntStopCallback; + s_pFaultCallback = pIntrStruct->pFaultCallback; + + return eStatus; +} + +/** + * @brief Interrupt IRQ handle of FREQM + * + */ +void FREQM_IRQHandler(void) +{ + uint32_t u32CntStatus; + bool bIntFlag; + + bIntFlag = FREQM_HWA_GetInterruptFlag(pFreqmPtrs); + if(bIntFlag) + { + FREQM_HWA_ClearInterruptFlag(pFreqmPtrs); + } + + u32CntStatus = FREQM_HWA_GetCntStatus(pFreqmPtrs); + + if(u32CntStatus == FREQM_CNT_STATUS_MES_CNT_START_MASK)//0x4 + { + s_pMesCntStartCallback(); + } + else if(u32CntStatus == (FREQM_CNT_STATUS_MES_CNT_START_MASK|FREQM_CNT_STATUS_MES_CNT_STOP_MASK) )//0x6 + { + + s_pMesCntStopCallback(); + } + else if(u32CntStatus == (FREQM_CNT_STATUS_MES_CNT_START_MASK|FREQM_CNT_STATUS_MES_CNT_STOP_MASK|FREQM_CNT_STATUS_REF_CNT_STOP_MASK) )//0x7 + { + s_pRefCntStopCallback(); + } + else + { + s_pFaultCallback(); + } +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_ftu.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_ftu.c new file mode 100644 index 0000000..d48df67 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_ftu.c @@ -0,0 +1,1810 @@ +/** + * @file fc7xxx_driver_ftu.c + * @author Flagchip + * @brief FC7xxx FTU driver type definition and API + * @version 0.1.0 + * @date 2022-11-15 + * + * @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2022-11-15 Flagchip070 N/A First version for FC7300 + ******************************************************************************** */ + +#include "fc7xxx_driver_ftu.h" +#include "fc7xxx_driver_pcc.h" +#include "interrupt_manager.h" +#include "HwA_scm.h" + +/********* Local variable ************/ +static const uint32_t s_aFtuMaxCounter[FTU_INSTANCE_COUNT] = {0xFFFFu, 0xFFFFFFu, 0xFFFFFFu, 0xFFFFu, 0xFFFFu, 0xFFFFu, 0xFFFFu, 0xFFFFu}; +static FTU_Type * const s_pFtuBasePtrs[FTU_INSTANCE_COUNT] = FTU_BASE_PTRS; +static FTU_ClkSrcType s_eFtuClkSrc[FTU_INSTANCE_COUNT] = {FTU_NO_CLK}; + +static FTU_ChannelCallBackType s_pChannelCallback[FTU_INSTANCE_COUNT] = {NULL}; +static FTU_FaultCallBackType s_pFaultCallback[FTU_INSTANCE_COUNT] = {NULL}; +static FTU_InterruptCallBackType s_pOverflowCallback[FTU_INSTANCE_COUNT] = {NULL}; +static FTU_InterruptCallBackType s_pReloadPointCallback[FTU_INSTANCE_COUNT] = {NULL}; + +/***************** Local Prototype Functions *********************/ +static void enable_sync_flag(FTU_Type *pFtu, uint16_t u16SyncFlag); +static void disable_sync_flag(FTU_Type *pFtu, uint16_t u16SyncFlag); +static void disable_reload_points(FTU_Type *pFtu, uint16_t u16ReloadPoints); +static void enable_reload_points(FTU_Type *pFtu, uint16_t u16ReloadPoints); + +/********* Local Functions ************/ +/** + * @brief Configure the input capture edge of the selected FTU channel + * + * @param pFtu the base address of the FTU instance + * @param u8Channel channel index of the FTU instance + * @param eEdge input capture edge + */ +static void set_ftu_input_edge(FTU_Type *pFtu, uint8_t u8Channel, FTU_InputCapturePinModeType eEdge) +{ + if (FTU_INPUT_RISING_EDGE == eEdge) + { + FTU_HWA_ConfigChannelEdgeLevel(pFtu, u8Channel, FTU_CHANNEL_EDGE_RISING); + } + else if (FTU_INPUT_FALLING_EDGE == eEdge) + { + FTU_HWA_ConfigChannelEdgeLevel(pFtu, u8Channel, FTU_CHANNEL_EDGE_FALLING); + } + else if (FTU_INPUT_BOTH_EDGE == eEdge) + { + FTU_HWA_ConfigChannelEdgeLevel(pFtu, u8Channel, FTU_CHANNEL_EDGE_BOTH); + } + else + { + FTU_HWA_ConfigChannelEdgeLevel(pFtu, u8Channel, FTU_CHANNEL_EDGE_NOT_USED); + } +} +/** + * @brief Enable the synchronization of the selected FTU instance + * + * @param pFtu the base address of the FTU instance + * @param u16SyncFlag The synchronization flag + */ +static void enable_sync_flag(FTU_Type *pFtu, uint16_t u16SyncFlag) +{ + uint32_t u32Loop; + if(0u != (u16SyncFlag & (uint16_t)FTU_SYNC_FLAG_FTUEN)) + { + FTU_HWA_SetModuleUpdateRegBySync(pFtu); + } + if(0u != (u16SyncFlag & (uint16_t)FTU_SYNC_FLAG_LDOK)) + { + FTU_HWA_SetPwmLoadEnable(pFtu); + } + if(0u != (u16SyncFlag & (uint16_t)FTU_SYNC_FLAG_CNTINC)) + { + FTU_HWA_SetCntinSync(pFtu); + } + for(u32Loop = 0; u32Loop < 4u; u32Loop++) + { + if(0u != (u16SyncFlag & (uint16_t)((uint16_t)FTU_SYNC_FLAG_SYNCEN01 << u32Loop))) + { + FTU_HWA_SetChannelSyncEnable(pFtu, u32Loop); + } + } + if(0u != (u16SyncFlag & (uint16_t)FTU_SYNC_FLAG_PWMSYNC)) + { + FTU_HWA_SetPwmSyncMode(pFtu); + } + if(0u != (u16SyncFlag & (uint16_t)FTU_SYNC_FLAG_REINIT)) + { + FTU_HWA_SetReinitBySync(pFtu); + } + if(0u != (u16SyncFlag & (uint16_t)FTU_SYNC_FLAG_SYNCHOM)) + { + FTU_HWA_EnableOutputMaskBySync(pFtu); + } +} + +/** + * @brief Disable the synchronization of the selected FTU instance + * + * @param pFtu the base address of the FTU instance + * @param u16SyncFlag The synchronization flag + */ +static void disable_sync_flag(FTU_Type *pFtu, uint16_t u16SyncFlag) +{ + uint32_t u32Loop; + if(0u != (u16SyncFlag & (uint16_t)FTU_SYNC_FLAG_FTUEN)) + { + FTU_HWA_ClearModuleUpdateRegBySync(pFtu); + } + if(0u != (u16SyncFlag & (uint16_t)FTU_SYNC_FLAG_LDOK)) + { + FTU_HWA_ClearPwmLoadEnable(pFtu); + } + if(0u != (u16SyncFlag & (uint16_t)FTU_SYNC_FLAG_CNTINC)) + { + FTU_HWA_ClearCntinSync(pFtu); + } + for(u32Loop = 0; u32Loop < 4u; u32Loop++) + { + if(0u != (u16SyncFlag & ((uint16_t)FTU_SYNC_FLAG_SYNCEN01 << u32Loop))) + { + FTU_HWA_ClearChannelSyncEnable(pFtu, u32Loop); + } + } + if(0u != (u16SyncFlag & (uint16_t)FTU_SYNC_FLAG_PWMSYNC)) + { + FTU_HWA_ClearPwmSyncMode(pFtu); + } + if(0u != (u16SyncFlag & (uint16_t)FTU_SYNC_FLAG_REINIT)) + { + FTU_HWA_ClearReinitBySync(pFtu); + } + if(0u != (u16SyncFlag & (uint16_t)FTU_SYNC_FLAG_SYNCHOM)) + { + FTU_HWA_DisableOutputMaskBySync(pFtu); + } +} + +/** + * @brief Disable the reload points of the selected FTU instance + * + * @param pFtu the base address of the FTU instance + * @param u16ReloadPoints The reload points flag + */ +static void disable_reload_points(FTU_Type *pFtu, uint16_t u16ReloadPoints) +{ + uint32_t u32Loop; + if(0u != (u16ReloadPoints & (uint16_t)FTU_RELOAD_POINT_CNTMAX)) + { + /* Enables Maximum Loading Point */ + FTU_HWA_DisableMaxLoadPoint(pFtu); + } + if(0u != (u16ReloadPoints & (uint16_t)FTU_RELOAD_POINT_CNTMIN)) + { + /* Disables Minimum Loading Point */ + FTU_HWA_DisableMinLoadPoint(pFtu); + } + for(u32Loop = 0u; u32Loop < FTU_CHANNEL_CONTROLS_COUNT; u32Loop++) + { + if(0u != (u16ReloadPoints & (uint16_t)((uint16_t)FTU_RELOAD_POINT_CHANNEL_0 << u32Loop))) + { + /* Channel match is not included as a reload opportunity */ + FTU_HWA_DisableChannelMatchReload(pFtu, u32Loop); + } + } +} + +/** + * @brief Enable the reload points of the selected FTU instance + * + * @param pFtu the base address of the FTU instance + * @param u16ReloadPoints The reload points flag + */ +static void enable_reload_points(FTU_Type *pFtu, uint16_t u16ReloadPoints) +{ + uint32_t u32Loop; + if(0u != (u16ReloadPoints & (uint32_t)FTU_RELOAD_POINT_CNTMAX)) + { + /* Enables Maximum Loading Point */ + FTU_HWA_EnableMaxLoadPoint(pFtu); + } + if(0u != (u16ReloadPoints & (uint32_t)FTU_RELOAD_POINT_CNTMIN)) + { + /* Enables Minimum Loading Point */ + FTU_HWA_EnableMinLoadPoint(pFtu); + } + for(u32Loop = 0; u32Loop < FTU_CHANNEL_CONTROLS_COUNT; u32Loop++) + { + if(0u != (u16ReloadPoints & ((uint32_t)FTU_RELOAD_POINT_CHANNEL_0 << u32Loop))) + { + /* Channel match is included as a reload opportunity */ + FTU_HWA_EnableChannelMatchReload(pFtu, u32Loop); + } + } +} + +/********* Global Functions ************/ +/** + * @brief Enable the reload points of the selected FTU instance + * + * @param eInstance the selected FTU instance + * @param u16ReloadPoints The reload points flag + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_EnableReloadPoints(const FTU_InstanceType eInstance, uint16_t u16ReloadPoints) +{ + FTU_StatusType eStatus = FTU_STATUS_SUCCESS; + if ((uint32_t)eInstance >= FTU_INSTANCE_COUNT) + { + eStatus = FTU_STATUS_PARAM_INVALID; + } + else + { + enable_reload_points(s_pFtuBasePtrs[eInstance], u16ReloadPoints); + } + return eStatus; +} + +/** + * @brief Disable the reload points of the selected FTU instance + * + * @param eInstance the selected FTU instance + * @param u16ReloadPoints The reload points flag + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_DisableReloadPoints(const FTU_InstanceType eInstance, uint16_t u16ReloadPoints) +{ + FTU_StatusType eStatus = FTU_STATUS_SUCCESS; + if ((uint32_t)eInstance >= FTU_INSTANCE_COUNT) + { + eStatus = FTU_STATUS_PARAM_INVALID; + } + else + { + disable_reload_points(s_pFtuBasePtrs[eInstance], u16ReloadPoints); + } + return eStatus; +} + +/** + * @brief enable the synchronization of the selected FTU + * + * @param eInstance the selected FTU instance + * @param u16ReloadPoints The synchronization flag + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_EnableSync(const FTU_InstanceType eInstance, uint16_t u16SyncFlag) +{ + FTU_StatusType eStatus = FTU_STATUS_SUCCESS; + if ((uint32_t)eInstance >= FTU_INSTANCE_COUNT) + { + eStatus = FTU_STATUS_PARAM_INVALID; + } + else + { + enable_sync_flag(s_pFtuBasePtrs[eInstance], u16SyncFlag); + } + return eStatus; +} + +/** + * @brief disable the synchronization of the selected FTU + * + * @param eInstance the selected FTU instance + * @param u16ReloadPoints The synchronization flag + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_DisableSync(const FTU_InstanceType eInstance, uint16_t u16SyncFlag) +{ + FTU_StatusType eStatus = FTU_STATUS_SUCCESS; + if ((uint32_t)eInstance >= FTU_INSTANCE_COUNT) + { + eStatus = FTU_STATUS_PARAM_INVALID; + } + else + { + disable_sync_flag(s_pFtuBasePtrs[eInstance], u16SyncFlag); + } + return eStatus; +} + +/** + * @brief Initialize FTU basic configuration + * + * @param eInstance the selected FTU instance + * @param pCommonStruct the basic configurations of the FTU instance + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_CommonInit(const FTU_InstanceType eInstance, const FTU_CommonType *const pCommonStruct) +{ + FTU_StatusType eRet = FTU_STATUS_SUCCESS; + if ((uint32_t)eInstance >= FTU_INSTANCE_COUNT) + { + eRet = FTU_STATUS_PARAM_INVALID; + } + else if (pCommonStruct->u32OverflowValue > s_aFtuMaxCounter[(uint32_t)eInstance]) + { + eRet = FTU_STATUS_PARAM_INVALID; + } + else + { + if (true == pCommonStruct->bGtbEnable) + { + FTU_HWA_EnableGlobalTimeBase(s_pFtuBasePtrs[eInstance]); + } + else + { + FTU_HWA_DisableGlobalTimeBase(s_pFtuBasePtrs[eInstance]); + } + FTU_HWA_DisableModuleCpwmMode(s_pFtuBasePtrs[eInstance]); + /* set FTU prescale */ + FTU_HWA_SetModulePrescale(s_pFtuBasePtrs[eInstance], pCommonStruct->ePrescaler); + /* configure fault filter prescaler */ + FTU_HWA_ConfigModuleFilterPrescale(s_pFtuBasePtrs[eInstance], pCommonStruct->eFliterPrescaler); + /*set the compare register as max value*/ + FTU_HWA_SetModuleCompareValue(s_pFtuBasePtrs[eInstance], (uint32_t)pCommonStruct->u32OverflowValue); + /*set initial value as 0*/ + FTU_HWA_SetCounterInitialValue(s_pFtuBasePtrs[eInstance], 0u); + /*set any value to clear the current counter register to initial value*/ + FTU_HWA_ClearModuleCounter(s_pFtuBasePtrs[eInstance], (uint32_t)0x1U); + /* set ftu OUTMASK sync mode, set bit SYNCHOM and OUTMASK register will update when then sync event happened */ + FTU_HWA_EnableOutputMaskBySync(s_pFtuBasePtrs[eInstance]); + /* set ftu debug mode */ + FTU_HWA_ConfigDebugMode(s_pFtuBasePtrs[eInstance], (uint32_t)pCommonStruct->eDbgMode); + /* Disable channel match trigger/interrupt when count-up/down in CPWM/QUAD mode */ + FTU_HWA_ConfigUpDownDisable(s_pFtuBasePtrs[eInstance], pCommonStruct->eUpDownDisable); + /*configure the synchronization*/ + disable_sync_flag(s_pFtuBasePtrs[eInstance], ~pCommonStruct->u16SyncFlag); + enable_sync_flag(s_pFtuBasePtrs[eInstance], pCommonStruct->u16SyncFlag); + + /*configure the reload points*/ + disable_reload_points(s_pFtuBasePtrs[eInstance], ~pCommonStruct->u16ReloadPoints); + enable_reload_points(s_pFtuBasePtrs[eInstance], pCommonStruct->u16ReloadPoints); + + /* configure hardware trigger mode */ + FTU_HWA_ConfigTrigMode(s_pFtuBasePtrs[eInstance], pCommonStruct->eHwTrigMode); + /* configure the frequency of the reload opportunities*/ + FTU_HWA_ConfigFreqOfReloadOp(s_pFtuBasePtrs[eInstance], pCommonStruct->u8ReloadFreq); + + /* select clock source */ + if (FTU_INTERNAL_CLK == pCommonStruct->eClkSrc) + { + s_eFtuClkSrc[eInstance] = FTU_INTERNAL_CLK; + } + else if (FTU_EXTERNAL_CLK0 == pCommonStruct->eClkSrc) + { + s_eFtuClkSrc[eInstance] = FTU_EXTERNAL_CLK0; + FTU_HWA_ConfigExternalClkSrc(s_pFtuBasePtrs[eInstance], FTU_TCLK0_USED); + } + else if (FTU_EXTERNAL_CLK1 == pCommonStruct->eClkSrc) + { + s_eFtuClkSrc[eInstance] = FTU_EXTERNAL_CLK1; + FTU_HWA_ConfigExternalClkSrc(s_pFtuBasePtrs[eInstance], FTU_TCLK1_USED); + } + else if (FTU_EXTERNAL_CLK2 == pCommonStruct->eClkSrc) + { + s_eFtuClkSrc[eInstance] = FTU_EXTERNAL_CLK2; + FTU_HWA_ConfigExternalClkSrc(s_pFtuBasePtrs[eInstance], FTU_TCLK2_USED); + } + else + { + s_eFtuClkSrc[eInstance] = FTU_NO_CLK; + } + } + return eRet; +} + +/** + * @brief De-initialize the FTU instance + * + * @param eInstance the selected FTU instance + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_DeInit(const FTU_InstanceType eInstance) +{ + FTU_StatusType eStatus = FTU_STATUS_SUCCESS; + if ((uint32_t)eInstance >= FTU_INSTANCE_COUNT) + { + eStatus = FTU_STATUS_PARAM_INVALID; + } + else + { + s_eFtuClkSrc[eInstance] = FTU_NO_CLK; + s_pChannelCallback[eInstance] = NULL; + s_pFaultCallback[eInstance] = NULL; + s_pOverflowCallback[eInstance] = NULL; + s_pReloadPointCallback[eInstance] = NULL; + + FTU_HWA_ClearModuleRegister(s_pFtuBasePtrs[eInstance]); + } + return eStatus; +} + +/** + * @brief Fills in the FTU configuration structure with the default settings. + * + * @param pCommonStruct Pointer to the user configuration structure + */ +void FTU_GetDefaultInitCfg(FTU_CommonType *pCommonStruct) +{ + DEV_ASSERT(NULL_PTR != pCommonStruct); + pCommonStruct->ePrescaler = FTU_DIV_1; + pCommonStruct->eFliterPrescaler = FTU_FLT_DIV_1; + pCommonStruct->u32OverflowValue = 0xFFFF; + pCommonStruct->eClkSrc = FTU_INTERNAL_CLK; + pCommonStruct->u16ReloadPoints = (uint16_t)FTU_RELOAD_POINT_CNTMAX; + pCommonStruct->u8ReloadFreq = 0; + pCommonStruct->u16SyncFlag = 0; + pCommonStruct->eHwTrigMode = FTU_CLEARS_TRIG_WHEN_DETECTED; + pCommonStruct->eDbgMode = FTU_DBG_COUNTER_WORKS_CHN_WORKS; + pCommonStruct->eUpDownDisable = FTU_DISABLE_TRIG_INTR_NONE; + pCommonStruct->bGtbEnable = false; +} + +/** + * @brief Configure FTU to counter mode + * + * @param eInstance the selected FTU instance + * @param pCounterStruct the configurations of the counter mode + * @return FTU_StatusType whether the operation is successfully + * @note This function will stop timer + */ +FTU_StatusType FTU_CounterModeInit(const FTU_InstanceType eInstance, const FTU_CounterModeType *const pCounterStruct) +{ + FTU_StatusType eStatus = FTU_STATUS_SUCCESS; + if ((uint32_t)eInstance >= FTU_INSTANCE_COUNT) + { + eStatus = FTU_STATUS_PARAM_INVALID; + } + else if ( (pCounterStruct->u32CounterValue > s_aFtuMaxCounter[(uint32_t)eInstance]) + || (pCounterStruct->u32InitialValue > s_aFtuMaxCounter[(uint32_t)eInstance])) + { + eStatus = FTU_STATUS_PARAM_INVALID; + } + else + { + /* disable ftu timer */ + FTU_HWA_ConfigModuleClkSrc(s_pFtuBasePtrs[eInstance], FTU_MODULE_NO_CLK); + /* set FTU MOD register value */ + FTU_HWA_SetModuleCompareValue(s_pFtuBasePtrs[eInstance], (uint32_t)pCounterStruct->u32CounterValue); + /*set initial value */ + FTU_HWA_SetCounterInitialValue(s_pFtuBasePtrs[eInstance], (uint32_t)pCounterStruct->u32InitialValue); + } + return eStatus; +} + +/** + * @brief Update the duty cycle of the FTU instance + * + * @param eInstance the selected FTU instance + * @param u8Channel the selected FTU channel + * @param u32Duty duty cycle of the PWM mode + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_PwmUpdateDuty(const FTU_InstanceType eInstance, uint8_t u8Channel, uint32_t u32Duty) +{ + FTU_StatusType eStatus = FTU_STATUS_SUCCESS; + uint8_t u8CpwmFlag; + if (((uint32_t)eInstance >= FTU_INSTANCE_COUNT) || + (u8Channel >= FTU_CHANNEL_CONTROLS_COUNT) || + (u32Duty > s_aFtuMaxCounter[(uint32_t)eInstance])) + { + eStatus = FTU_STATUS_PARAM_INVALID; + } + else + { + /* get the cpwm flag*/ + u8CpwmFlag = FTU_HWA_GetModuleCpwmMode(s_pFtuBasePtrs[eInstance]); + if(0u != u8CpwmFlag) + { + /* Duty value div 2 if cpwm mode*/ + FTU_HWA_SetChannelValue(s_pFtuBasePtrs[eInstance], u8Channel, (uint32_t)u32Duty >> 1u); + } + else + { + FTU_HWA_SetChannelValue(s_pFtuBasePtrs[eInstance], u8Channel, u32Duty); + } + } + return eStatus; +} + +static void set_deadtime(FTU_Type *pFtu, uint8_t u8Channel, uint32_t u32Deadtime, bool bPair) +{ + /* enable channel deadtime, channel 0/1 2/3 4/5 6/7 are combined*/ + FTU_HWA_EnableChannelDeadtime(pFtu, u8Channel); + if(u32Deadtime < 1024u) + { + if(bPair) + { + /* PAIRDEADTIME has a high priority*/ + FTU_HWA_ConfigPairDeadtimePrescaler(pFtu, u8Channel, FTU_DEADTIME_PRESCALER_DIV_1); + FTU_HWA_ConfigPairDeadtimeValue(pFtu, u8Channel, u32Deadtime); + } + else + { + /* DEADTIME shoud recover PAIRDEADTIME*/ + FTU_HWA_ConfigDeadtimePrescaler(pFtu, FTU_DEADTIME_PRESCALER_DIV_1); + FTU_HWA_ConfigDeadtimeValue(pFtu, u32Deadtime); + } + } + else if(u32Deadtime < 4096u) + { + /*deadtime should multiply 2*/ + if(bPair) + { + /* PAIRDEADTIME has a high priority*/ + FTU_HWA_ConfigPairDeadtimePrescaler(pFtu, u8Channel, + FTU_DEADTIME_PRESCALER_DIV_4); + FTU_HWA_ConfigPairDeadtimeValue(pFtu, (uint32_t)u8Channel, u32Deadtime >> 2u); + } + else + { + /* DEADTIME shoud recover PAIRDEADTIME*/ + FTU_HWA_ConfigDeadtimePrescaler(pFtu, FTU_DEADTIME_PRESCALER_DIV_4); + FTU_HWA_ConfigDeadtimeValue(pFtu, u32Deadtime >> 2u); + } + } + else + { + /*deadtime should multiply 4*/ + if(bPair) + { + /* PAIRDEADTIME has a high priority*/ + FTU_HWA_ConfigPairDeadtimePrescaler(pFtu, u8Channel, FTU_DEADTIME_PRESCALER_DIV_16); + FTU_HWA_ConfigPairDeadtimeValue(pFtu, u8Channel, u32Deadtime >> 4u); + } + else + { + /* DEADTIME shoud recover PAIRDEADTIME*/ + FTU_HWA_ConfigDeadtimePrescaler(pFtu, FTU_DEADTIME_PRESCALER_DIV_16); + FTU_HWA_ConfigDeadtimeValue(pFtu, u32Deadtime >> 4u); + } + } +} + +/** + * @brief Configure FTU to PWM mode + * + * @param eInstance the selected FTU instance + * @param pPwmModeStruct the configurations of the PWM mode + * @return FTU_StatusType whether the operation is successfully + * @note This function will stop timer + */ +FTU_StatusType FTU_PwmModeInit(const FTU_InstanceType eInstance, const FTU_PwmModeType *const pPwmModeStruct) +{ + FTU_StatusType eStatus = FTU_STATUS_SUCCESS; + uint8_t u8Channel; + uint32_t u32Loop; + if ((uint32_t)eInstance >= FTU_INSTANCE_COUNT) + { + eStatus = FTU_STATUS_PARAM_INVALID; + } + else if (pPwmModeStruct->u32PwmPeriod > s_aFtuMaxCounter[(uint32_t)eInstance]) + { + eStatus = FTU_STATUS_PARAM_INVALID; + } + + for (u32Loop = 0u; u32Loop < pPwmModeStruct->u32ChannelCount; u32Loop++) + { + if (pPwmModeStruct->pPwmChannels[u32Loop].u8Channel >= FTU_CHANNEL_CONTROLS_COUNT) + { + eStatus = FTU_STATUS_PARAM_INVALID; + break; + } + + if ( (pPwmModeStruct->pPwmChannels[u32Loop].u32PwmDuty > s_aFtuMaxCounter[(uint32_t)eInstance]) + || (pPwmModeStruct->pPwmChannels[u32Loop].u32PhaseShift > s_aFtuMaxCounter[(uint32_t)eInstance])) + { + eStatus = FTU_STATUS_PARAM_INVALID; + break; + } + + if ( (FTU_CENTER_ALIGNED_PWM == pPwmModeStruct->eAlignedMode) + && (0u < pPwmModeStruct->pPwmChannels[u32Loop].u32PhaseShift)) + { + eStatus = FTU_STATUS_PARAM_INVALID; + break; + } + if ( (true == pPwmModeStruct->pPwmChannels[u32Loop].bLinkMode) + && (0u < pPwmModeStruct->pPwmChannels[u32Loop].u32PhaseShift)) + { + eStatus = FTU_STATUS_PARAM_INVALID; + break; + } + if (( (true == pPwmModeStruct->pPwmChannels[u32Loop].bLinkMode) + || (0u < pPwmModeStruct->pPwmChannels[u32Loop].u32PhaseShift)) + && (pPwmModeStruct->pPwmChannels[u32Loop].u8Channel & 1u)) + { + eStatus = FTU_STATUS_PARAM_INVALID; + break; + } + } + + if (FTU_STATUS_SUCCESS == eStatus) + { + /* disable ftu timer */ + FTU_HWA_ConfigModuleClkSrc(s_pFtuBasePtrs[eInstance], FTU_MODULE_NO_CLK); + if (FTU_EDGE_ALIGNED_PWM == pPwmModeStruct->eAlignedMode) + { + FTU_HWA_DisableModuleCpwmMode(s_pFtuBasePtrs[eInstance]); + FTU_HWA_SetModuleCompareValue(s_pFtuBasePtrs[eInstance], pPwmModeStruct->u32PwmPeriod); + } + else + { + FTU_HWA_EnableModuleCpwmMode(s_pFtuBasePtrs[eInstance]); + FTU_HWA_SetModuleCompareValue(s_pFtuBasePtrs[eInstance], pPwmModeStruct->u32PwmPeriod >> 1u); + } + set_deadtime(s_pFtuBasePtrs[eInstance], 0u, pPwmModeStruct->u32PublicDeadtime, false); + + for (u32Loop = 0u; u32Loop < pPwmModeStruct->u32ChannelCount; u32Loop++) + { + FTU_PwmChannelType *pChannelCfg = &pPwmModeStruct->pPwmChannels[u32Loop]; + u8Channel = pChannelCfg->u8Channel; + if(pChannelCfg->bLinkMode) + { + /* set channel(n+1) complement of channel(n) output */ + FTU_HWA_EnableChannelComplement(s_pFtuBasePtrs[eInstance], u8Channel); + if (!pChannelCfg->bLinkChannelComplement) + { + FTU_HWA_ClearChannelPolarity(s_pFtuBasePtrs[eInstance], (uint8_t)1U << u8Channel); + FTU_HWA_SetChannelPolarity(s_pFtuBasePtrs[eInstance], (uint8_t)1U << (u8Channel + (uint8_t)1U)); + } + else + { + FTU_HWA_ClearChannelPolarity(s_pFtuBasePtrs[eInstance], + (uint8_t)1U << u8Channel| (uint8_t)1U << (u8Channel + 1u)); + } + /*link mode, the u8Channel+1->csc.ELSB bit must be set*/ + FTU_HWA_ConfigChannelPwmLinkMode(s_pFtuBasePtrs[eInstance], u8Channel + (uint8_t)1U); + /* enable u8Channel sync function of the ftu*/ + FTU_HWA_EnableChannelSync(s_pFtuBasePtrs[eInstance], u8Channel); + /* configure pin output as channel mode*/ + FTU_HWA_ConfigTrigOutputMode(s_pFtuBasePtrs[eInstance], u8Channel, FTU_TRIG_OUTPUT_AS_CHANNEL_MODE); + FTU_HWA_ConfigTrigOutputMode(s_pFtuBasePtrs[eInstance], u8Channel + 1u, FTU_TRIG_OUTPUT_AS_CHANNEL_MODE); + /* enable FTU output */ + FTU_HWA_EnableChannelsOutput(s_pFtuBasePtrs[eInstance], (uint8_t)3U << u8Channel); + } + else + { + if (pChannelCfg->u32PhaseShift) + { + FTU_HWA_ClearChannelPolarity(s_pFtuBasePtrs[eInstance], (uint8_t)1U << (u8Channel + 1)); + /* enable u8Channel sync function of the ftu*/ + FTU_HWA_EnableChannelSync(s_pFtuBasePtrs[eInstance], u8Channel); + + /*Enable enhanced phase shift mode*/ + FTU_HWA_EnableChannelPhase(s_pFtuBasePtrs[eInstance], u8Channel); + FTU_HWA_EnableChannelEnhancedPhase(s_pFtuBasePtrs[eInstance], u8Channel); + } + else + { + /* enable u8Channel sync function of the ftu*/ + FTU_HWA_DisableChannelSync(s_pFtuBasePtrs[eInstance], u8Channel); + + /*Enable enhanced phase shift mode*/ + FTU_HWA_DisableChannelPhase(s_pFtuBasePtrs[eInstance], u8Channel); + FTU_HWA_DisableChannelPhase(s_pFtuBasePtrs[eInstance], u8Channel); + } + + /* disable channel(n+1) complement of channel(n) output */ + FTU_HWA_DisableChannelComplement(s_pFtuBasePtrs[eInstance], u8Channel); + FTU_HWA_ClearChannelPolarity(s_pFtuBasePtrs[eInstance], (uint8_t)1U << u8Channel); + /* enable FTU output */ + FTU_HWA_EnableChannelsOutput(s_pFtuBasePtrs[eInstance], (uint8_t)1U << u8Channel); + /* configure pin output as channel mode*/ + FTU_HWA_ConfigTrigOutputMode(s_pFtuBasePtrs[eInstance], u8Channel, FTU_TRIG_OUTPUT_AS_CHANNEL_MODE); + + } + /* set FTU pwm mode */ + if ( (FTU_PWM_HIGH_TRUE_PULSE == pChannelCfg->ePinMode) + && (FTU_EDGE_ALIGNED_PWM == pPwmModeStruct->eAlignedMode)) + { + FTU_HWA_ConfigChannelMode(s_pFtuBasePtrs[eInstance], u8Channel, FTU_CHANNEL_MODE_EDGE_ALIGN_PWM); + FTU_HWA_ConfigChannelEdgeLevel(s_pFtuBasePtrs[eInstance], u8Channel, FTU_CHANNEL_PWM_HIGH_TRUE); + } + else if ( (FTU_PWM_LOW_TRUE_PULSE == pChannelCfg->ePinMode) + && (FTU_EDGE_ALIGNED_PWM == pPwmModeStruct->eAlignedMode)) + { + FTU_HWA_ConfigChannelMode(s_pFtuBasePtrs[eInstance], u8Channel, FTU_CHANNEL_MODE_EDGE_ALIGN_PWM); + FTU_HWA_ConfigChannelEdgeLevel(s_pFtuBasePtrs[eInstance], u8Channel, FTU_CHANNEL_PWM_LOW_TRUE); + } + else if ( (FTU_PWM_HIGH_TRUE_PULSE == pChannelCfg->ePinMode) + && (FTU_CENTER_ALIGNED_PWM == pPwmModeStruct->eAlignedMode)) + { + FTU_HWA_ConfigChannelEdgeLevel(s_pFtuBasePtrs[eInstance], u8Channel, FTU_CHANNEL_PWM_HIGH_TRUE); + } + else if ( (FTU_PWM_LOW_TRUE_PULSE == pChannelCfg->ePinMode) + && (FTU_CENTER_ALIGNED_PWM == pPwmModeStruct->eAlignedMode)) + { + FTU_HWA_ConfigChannelEdgeLevel(s_pFtuBasePtrs[eInstance], u8Channel, FTU_CHANNEL_PWM_LOW_TRUE); + } + + if (pChannelCfg->bDeadtimeEnable) + { + FTU_HWA_EnableChannelDeadtime(s_pFtuBasePtrs[eInstance], u8Channel); + } + else + { + FTU_HWA_DisableChannelDeadtime(s_pFtuBasePtrs[eInstance], u8Channel); + } + + /* set the period time and duty time */ + if(FTU_CENTER_ALIGNED_PWM == pPwmModeStruct->eAlignedMode) + { + FTU_HWA_SetChannelValue(s_pFtuBasePtrs[eInstance], u8Channel, pChannelCfg->u32PwmDuty >> 1u); + } + else + { + if (pChannelCfg->u32PhaseShift) + { + FTU_HWA_SetChannelValue(s_pFtuBasePtrs[eInstance], u8Channel, pChannelCfg->u32PhaseShift); + if ((pChannelCfg->u32PhaseShift + pChannelCfg->u32PwmDuty) > pPwmModeStruct->u32PwmPeriod) + { + FTU_HWA_SetChannelValue(s_pFtuBasePtrs[eInstance], u8Channel + 1, + pChannelCfg->u32PhaseShift + pChannelCfg->u32PwmDuty - pPwmModeStruct->u32PwmPeriod - 1); + } + else + { + FTU_HWA_SetChannelValue(s_pFtuBasePtrs[eInstance], u8Channel + 1, + pChannelCfg->u32PhaseShift + pChannelCfg->u32PwmDuty); + } + + } + else + { + FTU_HWA_SetChannelValue(s_pFtuBasePtrs[eInstance], u8Channel, pChannelCfg->u32PwmDuty); + } + } + set_deadtime(s_pFtuBasePtrs[eInstance], u8Channel, pChannelCfg->u32ChannelDeadtime, true); + } + } + return eStatus; +} + +/** + * @brief Configure FTU to output compare mode + * + * @param eInstance the selected FTU instance + * @param pOutputModeStruct the configurations of the output compare mode + * @return FTU_StatusType whether the operation is successfully + * @note This function will stop timer + */ +FTU_StatusType FTU_OutputCompareModeInit(const FTU_InstanceType eInstance, + const FTU_OutputCompareModeType *const pOCConfig) +{ + FTU_StatusType eStatus = FTU_STATUS_SUCCESS; + if (((uint32_t)eInstance >= FTU_INSTANCE_COUNT) || (pOCConfig->u8Channel >= FTU_CHANNEL_CONTROLS_COUNT)) + { + eStatus = FTU_STATUS_PARAM_INVALID; + } + else if ( pOCConfig->u32CompareValue > s_aFtuMaxCounter[(uint32_t)eInstance]) + { + eStatus = FTU_STATUS_PARAM_INVALID; + } + else + { + /* disable ftu timer */ + FTU_HWA_ConfigModuleClkSrc(s_pFtuBasePtrs[eInstance], FTU_MODULE_NO_CLK); + FTU_HWA_DisableChannelEnhancedPhase(s_pFtuBasePtrs[eInstance], pOCConfig->u8Channel); + FTU_HWA_DisableChannelPhase(s_pFtuBasePtrs[eInstance], pOCConfig->u8Channel); + FTU_HWA_ConfigInputCaptureMeasureMode(s_pFtuBasePtrs[eInstance], pOCConfig->u8Channel, + FTU_MEASURE_MODE_OFF); + FTU_HWA_ConfigChannelMode(s_pFtuBasePtrs[eInstance], pOCConfig->u8Channel, FTU_CHANNEL_MODE_OUTPUT_COMPARE); + if (FTU_OUTPUT_TOGGLE_PIN == pOCConfig->eOutputMode) + { + FTU_HWA_ConfigChannelEdgeLevel(s_pFtuBasePtrs[eInstance], pOCConfig->u8Channel, FTU_CHANNEL_OC_TOGGLE); + } + else if (FTU_OUTPUT_CLEAR_PIN == pOCConfig->eOutputMode) + { + FTU_HWA_ConfigChannelEdgeLevel(s_pFtuBasePtrs[eInstance], pOCConfig->u8Channel, FTU_CHANNEL_OC_CLEAR); + } + else if (FTU_OUTPUT_SET_PIN == pOCConfig->eOutputMode) + { + FTU_HWA_ConfigChannelEdgeLevel(s_pFtuBasePtrs[eInstance], pOCConfig->u8Channel, FTU_CHANNEL_OC_SET); + } + /* Disable Up-Down Mode*/ + FTU_HWA_DisableModuleCpwmMode(s_pFtuBasePtrs[eInstance]); + /* enable FTU output */ + FTU_HWA_EnableChannelsOutput(s_pFtuBasePtrs[eInstance], (uint8_t)1U << pOCConfig->u8Channel); + /* configure initial level */ + if (FTU_OUTPUT_CMP_INIT_LOW == pOCConfig->eInitLevel) + { + FTU_HWA_ClearChannelPolarity(s_pFtuBasePtrs[eInstance], (uint8_t)1U << pOCConfig->u8Channel); + } + else + { + FTU_HWA_SetChannelPolarity(s_pFtuBasePtrs[eInstance], (uint8_t)1U << pOCConfig->u8Channel); + } + /* configure pin output as channel mode*/ + FTU_HWA_ConfigTrigOutputMode(s_pFtuBasePtrs[eInstance], pOCConfig->u8Channel, FTU_TRIG_OUTPUT_AS_CHANNEL_MODE); + /* set FTU CV register value*/ + FTU_HWA_SetChannelValue(s_pFtuBasePtrs[eInstance], pOCConfig->u8Channel, (uint32_t)pOCConfig->u32CompareValue); + + } + return eStatus; +} + +/** + * @brief Enable the output trigger of the selected FTU instance + * + * @param eInstance the selected FTU instance + * @param u32TriggerOutputMask the output trigger mask + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_EnableTriggerOutput(const FTU_InstanceType eInstance, uint32_t u32TriggerOutputMask) +{ + FTU_StatusType eStatus = FTU_STATUS_SUCCESS; + + if ((uint32_t)eInstance >= FTU_INSTANCE_COUNT) + { + eStatus = FTU_STATUS_PARAM_INVALID; + } + else + { + /* enable the channel match trigger */ + FTU_HWA_EnableChannelTriggerOut(s_pFtuBasePtrs[eInstance], (uint8_t)(u32TriggerOutputMask & (uint32_t)FTU_TRIG_OUTPUT_MASK_ALL_CHANNEL_MATCH)); + if (0u != (u32TriggerOutputMask & (uint32_t)FTU_TRIG_OUTPUT_MASK_RELOAD)) + { + /* enable reload trigger */ + FTU_HWA_EnableReloadTrigger(s_pFtuBasePtrs[eInstance]); + } + } + return eStatus; +} + +/** + * @brief Disable the output trigger of the selected FTU instance + * + * @param eInstance the selected FTU instance + * @param u32TriggerOutputMask the output trigger mask + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_DisableTriggerOutput(const FTU_InstanceType eInstance, uint32_t u32TriggerOutputMask) +{ + FTU_StatusType eStatus = FTU_STATUS_SUCCESS; + if ((uint32_t)eInstance >= FTU_INSTANCE_COUNT) + { + eStatus = FTU_STATUS_PARAM_INVALID; + } + else + { + /* disenable the channel match trigger */ + FTU_HWA_DisableChannelTriggerOut(s_pFtuBasePtrs[eInstance], (uint8_t)(u32TriggerOutputMask & (uint32_t)FTU_TRIG_OUTPUT_MASK_ALL_CHANNEL_MATCH)); + if (0u != (u32TriggerOutputMask & (uint32_t)FTU_TRIG_OUTPUT_MASK_RELOAD)) + { + /* disable reload trigger */ + FTU_HWA_DisableReloadTrigger(s_pFtuBasePtrs[eInstance]); + } + } + return eStatus; +} + +/** + * @brief Start the FTU instance + * + * @param eInstance the selected FTU instance + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_StartTimer(const FTU_InstanceType eInstance) +{ + FTU_StatusType eStatus = FTU_STATUS_SUCCESS; + if ((uint32_t)eInstance >= FTU_INSTANCE_COUNT) + { + eStatus = FTU_STATUS_PARAM_INVALID; + } + else + { + /* set FTU module clock source */ + if (s_eFtuClkSrc[eInstance] == FTU_NO_CLK) + { + eStatus = FTU_STATUS_NO_CLOCK_SOURCE; + } + else if(s_eFtuClkSrc[eInstance] == FTU_INTERNAL_CLK) + { + FTU_HWA_ConfigModuleClkSrc(s_pFtuBasePtrs[eInstance], FTU_MODULE_INTERNAL_CLK); + } + else + { + FTU_HWA_ConfigModuleClkSrc(s_pFtuBasePtrs[eInstance], FTU_MODULE_EXTERNAL_CLK); + } + } + return eStatus; +} + +/** + * @brief Stop the FTU global time base + * + * @param u32InstanceMask The selected FTU, each bit represents an instance + */ +void FTU_StopGlobalTimeBase(uint32_t u32InstanceMask) +{ + uint32_t u32GTB = 0u, u32Loop0; + for (u32Loop0 = 0u; u32Loop0 < FTU_INSTANCE_COUNT; u32Loop0++) + { + uint32_t u32InstanceFlag = 1u << u32Loop0; + if (0u != (u32InstanceMask & u32InstanceFlag)) + { + u32GTB |= u32InstanceFlag; + SCM_HWA_ClearFtuGTBMask((uint8_t)u32Loop0); + } + } + SCM_HWA_ClearFtuGTBSelect(u32GTB); +} + +/** + * @brief Start the FTU global time base + * + * @param u32InstanceMask The selected FTU, each bit represents an instance + * @param u32StartMask Start time, refer to FTU_GlobalTimeBaseStartType + */ +void FTU_StartGlobalTimeBase(uint32_t u32InstanceMask, uint32_t u32StartMask) +{ + uint32_t u32GTB = 0u, u32Loop0, u32Loop1; + for (u32Loop0 = 0u; u32Loop0 < FTU_INSTANCE_COUNT; u32Loop0++) + { + uint32_t u32InstanceFlag = 1u << u32Loop0; + if (0u != (u32InstanceMask & u32InstanceFlag)) + { + if (u32StartMask & FTU_GTB_START_AT_ONCE) + { + u32GTB |= u32InstanceFlag; + } + for (u32Loop1 = 0u; u32Loop1 < TSTMP_MODULATE_COUNT; u32Loop1++) + { + if (u32StartMask & (FTU_GTB_START_AT_TSTMP1_MOD0 << u32Loop1)) + { + SCM_HWA_ConfigFtuGTBMask((uint8_t)u32Loop0, (1u << u32Loop1)); + } + } + } + } + SCM_HWA_SetFtuGTBSelect(u32GTB); +} + +/** + * @brief Stop the FTU instance + * + * @param eInstance the selected FTU instance + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_StopTimer(const FTU_InstanceType eInstance) +{ + FTU_StatusType eStatus = FTU_STATUS_SUCCESS; + if ((uint32_t)eInstance >= FTU_INSTANCE_COUNT) + { + eStatus = FTU_STATUS_PARAM_INVALID; + } + else + { + /* clear FTU module clock source */ + FTU_HWA_ConfigModuleClkSrc(s_pFtuBasePtrs[eInstance], FTU_MODULE_NO_CLK); + //FTU_HWA_ClearModuleCounter(s_pFtuBasePtrs[eInstance], 0); + } + return eStatus; +} + +/** + * @brief Ftu initialize interrupt function + * + * @param eInstance the selected FTU instance + * @param pIntStruct the configurations of the interrupt + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_InterruptInit(const FTU_InstanceType eInstance, const FTU_InterruptType *const pIntrStruct) +{ + FTU_StatusType eStatus = FTU_STATUS_SUCCESS; + uint32_t u32Loop; + if ((uint32_t)eInstance >= FTU_INSTANCE_COUNT) + { + eStatus = FTU_STATUS_PARAM_INVALID; + } + else + { + for(u32Loop = 0u; u32Loop < FTU_CHANNEL_CONTROLS_COUNT; u32Loop++) + { + if (0u != (pIntrStruct->u32InterruptMask & ((uint32_t)FTU_INTR_MASK_CHANNEL_0 << u32Loop))) + { + /* Enable Channel Interrupt */ + FTU_HWA_EnableChannelInterrupt(s_pFtuBasePtrs[eInstance], (uint8_t)u32Loop); + } + else + { + /* Disable Channel Interrupt */ + FTU_HWA_DisableChannelInterrupt(s_pFtuBasePtrs[eInstance], (uint8_t)u32Loop); + } + } + + if (0u != (pIntrStruct->u32InterruptMask & (uint32_t)FTU_INTR_MASK_OVERFLOW)) + { + /* Enable Overflow Interrupt */ + FTU_HWA_EnableOverflowInterrupt(s_pFtuBasePtrs[eInstance]); + } + else + { + /* Disable Overflow Interrupt */ + FTU_HWA_DisableOverflowInterrupt(s_pFtuBasePtrs[eInstance]); + } + + if (0u != (pIntrStruct->u32InterruptMask & (uint32_t)FTU_INTR_MASK_FAULT)) + { + /* Enable Fault Interrupt */ + FTU_HWA_EnableModuleFaultInterrupt(s_pFtuBasePtrs[eInstance]); + } + else + { + /* Disable Fault Interrupt */ + FTU_HWA_DisableModuleFaultInterrupt(s_pFtuBasePtrs[eInstance]); + } + + if (0u != (pIntrStruct->u32InterruptMask & (uint32_t)FTU_INTR_MASK_RELOAD_POINT)) + { + /* Enable Reload Point Interrupt */ + FTU_HWA_EnableReloadPointInterrupt(s_pFtuBasePtrs[eInstance]); + } + else + { + /* Disable Reload Point Interrupt */ + FTU_HWA_DisableReloadPointInterrupt(s_pFtuBasePtrs[eInstance]); + } + + /*register callback functions*/ + s_pChannelCallback[eInstance] = pIntrStruct->pChannelCallback; + s_pFaultCallback[eInstance] = pIntrStruct->pFaultCallback; + s_pOverflowCallback[eInstance] = pIntrStruct->pOverflowCallback; + s_pReloadPointCallback[eInstance] = pIntrStruct->pReloadPointCallback; + } + return eStatus; +} + +/** + * @brief initialize fault input of the selected Ftu instance + * + * @param eInstance the selected FTU instance + * @param pFaultInit the fault configurations of the FTU instance + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_FaultInit(const FTU_InstanceType eInstance, const FTU_FaultInitType *const pFaultInit) +{ + FTU_StatusType eStatus = FTU_STATUS_SUCCESS; + uint32_t u32Loop, u32Temp; + if ((uint32_t)eInstance >= FTU_INSTANCE_COUNT) + { + eStatus = FTU_STATUS_PARAM_INVALID; + } + else + { + /* configure fault mode */ + FTU_HWA_ConfigModuleFaultMode(s_pFtuBasePtrs[eInstance], pFaultInit->eFaultMode); + /* Disable all fault inputs*/ + u32Temp = FTU_HWA_GetFaultEnable(s_pFtuBasePtrs[eInstance]); + FTU_HWA_DisableModuleFault(s_pFtuBasePtrs[eInstance], 0xFu); + /* configure fault filter value */ + FTU_HWA_SetModuleFaultFilterValue(s_pFtuBasePtrs[eInstance], pFaultInit->u8FilterValue); + /* recover fault inputs*/ + FTU_HWA_EnableModuleFault(s_pFtuBasePtrs[eInstance], (uint8_t)u32Temp); + /* enables the fault control in channels */ + for(u32Loop = 0u; u32Loop < FTU_FAULT_COUNT; u32Loop++) + { + if (0u != (pFaultInit->u8FaultChannelEnable & ((uint8_t)FTU_FAULT_FOR_CHANNEL01 << u32Loop))) + { + FTU_HWA_EnableChannelFault(s_pFtuBasePtrs[eInstance], (uint8_t)u32Loop << 1u); + } + else + { + FTU_HWA_DisableChannelFault(s_pFtuBasePtrs[eInstance], (uint8_t)u32Loop << 1u); + } + } + + /* set fault disable channel output delay value */ + FTU_HWA_SetFaultDelay0(s_pFtuBasePtrs[eInstance], pFaultInit->u8FaultDisableDelay0); + FTU_HWA_SetFaultDelay1(s_pFtuBasePtrs[eInstance], pFaultInit->u8FaultDisableDelay1); + } + return eStatus; +} + +/** + * @brief Select fault disable channel output delay value + * + * @param eInstance the selected FTU instance + * @param u8Channel FTU channel number, range is 0-7. + * @param eSelection Fault disable channel output delay value selection. + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_FaultSelectDelayValue(const FTU_InstanceType eInstance, uint8_t u8Channel, FTU_FaultDisableDelayType eDelaySelection) +{ + FTU_StatusType eStatus = FTU_STATUS_SUCCESS; + if ((uint32_t)eInstance >= FTU_INSTANCE_COUNT) + { + eStatus = FTU_STATUS_PARAM_INVALID; + } + else if (u8Channel >= FTU_CHANNEL_CONTROLS_COUNT) + { + eStatus = FTU_STATUS_PARAM_INVALID; + } + else + { + FTU_HWA_SelectFaultDelay(s_pFtuBasePtrs[eInstance], u8Channel, eDelaySelection); + } + return eStatus; +} + +/** + * @brief Enable a fault input + * + * @param eInstance the selected FTU instance + * @param pFaultCtrl configurations of the fault input + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_FaultEnable(const FTU_InstanceType eInstance, const FTU_FaultControlType *const pFaultCtrl) +{ + FTU_StatusType eStatus = FTU_STATUS_SUCCESS; + + if (((uint32_t)eInstance >= FTU_INSTANCE_COUNT) || + (pFaultCtrl->u8FaultIndex >= FTU_FAULT_COUNT)) + { + eStatus = FTU_STATUS_PARAM_INVALID; + } + else + { + /* configure fault input polarity */ + FTU_HWA_ConfigFaultPolarity(s_pFtuBasePtrs[eInstance], pFaultCtrl->u8FaultIndex, (uint8_t)pFaultCtrl->eFaultPol); + if(true == pFaultCtrl->bFaultFilterEnable) + { + FTU_HWA_EnableModuleFaultGlitchFilter(s_pFtuBasePtrs[eInstance], 1u << pFaultCtrl->u8FaultIndex); + } + else + { + FTU_HWA_DisableModuleFaultGlitchFilter(s_pFtuBasePtrs[eInstance], 1u << pFaultCtrl->u8FaultIndex); + } + /* enable fault input */ + FTU_HWA_EnableModuleFault(s_pFtuBasePtrs[eInstance], 1u << pFaultCtrl->u8FaultIndex); + } + return eStatus; +} + +/** + * @brief Disable a fault input + * + * @param eInstance the selected FTU instance + * @param u32FaultIndex index of the fault input + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_FaultDisable(const FTU_InstanceType eInstance, uint32_t u32FaultIndex) +{ + FTU_StatusType eStatus = FTU_STATUS_SUCCESS; + if (((uint32_t)eInstance >= FTU_INSTANCE_COUNT) || + (u32FaultIndex >= FTU_FAULT_COUNT)) + { + eStatus = FTU_STATUS_PARAM_INVALID; + } + else + { + FTU_HWA_DisableModuleFault(s_pFtuBasePtrs[eInstance], 0x1u << u32FaultIndex); + } + return eStatus; +} + +/** + * @brief initialize a input capture channel of the selected Ftu instance + * + * @param eInstance the selected FTU instance + * @param pInputChannel configurations of the input capture channel + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_InputCaptureChannelInit(const FTU_InstanceType eInstance, + const FTU_InputChannelType *const pInputChannel) +{ + FTU_StatusType eStatus = FTU_STATUS_SUCCESS; + + if (((uint32_t)eInstance >= FTU_INSTANCE_COUNT) || + (pInputChannel->u8Channel >= FTU_CHANNEL_CONTROLS_COUNT)) + { + eStatus = FTU_STATUS_PARAM_INVALID; + } + else + { + FTU_HWA_DisableQuadratureMode(s_pFtuBasePtrs[eInstance]); + FTU_HWA_DisableChannelEnhancedPhase(s_pFtuBasePtrs[eInstance], pInputChannel->u8Channel); + FTU_HWA_DisableChannelPhase(s_pFtuBasePtrs[eInstance], pInputChannel->u8Channel); + FTU_HWA_ConfigInputCaptureMeasureMode(s_pFtuBasePtrs[eInstance], pInputChannel->u8Channel, + FTU_MEASURE_MODE_OFF); + FTU_HWA_ConfigChannelMode(s_pFtuBasePtrs[eInstance], pInputChannel->u8Channel, FTU_CHANNEL_MODE_INPUT); + if(pInputChannel->u8Channel < FTU_INPUT_FILTER_COUNT) + { + /* set FTU input capture filter value */ + FTU_HWA_ConfigInputCaptureFilter( + s_pFtuBasePtrs[eInstance], pInputChannel->u8Channel, + pInputChannel->u8FilterValue); + + } + + set_ftu_input_edge(s_pFtuBasePtrs[eInstance], pInputChannel->u8Channel, pInputChannel->eInputMode); + } + return eStatus; +} + +/** + * @brief initialize the quadrature decoder mode + * + * @param eInstance the selected FTU instance + * @param pQuadInit configurations of the quadrature decoder + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_QuadratureModeInit(const FTU_InstanceType eInstance, + const FTU_QuadratureInitType *const pQuadInit) +{ + FTU_StatusType eStatus = FTU_STATUS_SUCCESS; + + if (((uint32_t)eInstance != FTU_INSTANCE_1) && + ((uint32_t)eInstance != FTU_INSTANCE_2) && + ((uint32_t)eInstance != FTU_INSTANCE_4) && + ((uint32_t)eInstance != FTU_INSTANCE_5)) + { + /* Only FTU1/2/4/5 support quadrature decode*/ + eStatus = FTU_STATUS_PARAM_INVALID; + } + else + { + /* set quadrature mode */ + FTU_HWA_ConfigQuadratureMode(s_pFtuBasePtrs[eInstance], pQuadInit->eQuadMode); + /* set PHA polarity*/ + if(pQuadInit->bPhaInverted) + { + FTU_HWA_EnablePhaInv(s_pFtuBasePtrs[eInstance]); + } + else + { + FTU_HWA_DisablePhaInv(s_pFtuBasePtrs[eInstance]); + } + /* set PHB polarity*/ + if(pQuadInit->bPhbInverted) + { + FTU_HWA_EnablePhbInv(s_pFtuBasePtrs[eInstance]); + } + else + { + FTU_HWA_DisablePhbInv(s_pFtuBasePtrs[eInstance]); + } + + /* Set counter direction */ + FTU_HWA_ConfigQuadDirection(s_pFtuBasePtrs[eInstance], pQuadInit->eQuadDirection); + /* Set overflow direction */ + FTU_HWA_ConfigTimerOverflowDir(s_pFtuBasePtrs[eInstance], pQuadInit->eOveflowDirection); + /* set top value */ + FTU_HWA_SetModuleCompareValue(s_pFtuBasePtrs[eInstance], pQuadInit->u16TopValue); + /* set bottom value */ + FTU_HWA_SetCounterInitialValue(s_pFtuBasePtrs[eInstance], pQuadInit->u16BottomValue); + + /* Set phase A glitch filter value */ + if (0U != pQuadInit->u8PhaFilterVal) + { + FTU_HWA_ConfigChannelFilterValue(s_pFtuBasePtrs[eInstance], 0, pQuadInit->u8PhaFilterVal); + FTU_HWA_EnablePhaGlitchFilter(s_pFtuBasePtrs[eInstance]); + } + else + { + FTU_HWA_DisablePhaGlitchFilter(s_pFtuBasePtrs[eInstance]); + } + /* Set phase B glitch filter value */ + if (0U != pQuadInit->u8PhbFilterVal) + { + FTU_HWA_ConfigChannelFilterValue(s_pFtuBasePtrs[eInstance], 1, pQuadInit->u8PhbFilterVal); + FTU_HWA_EnablePhbGlitchFilter(s_pFtuBasePtrs[eInstance]); + } + else + { + FTU_HWA_DisablePhbGlitchFilter(s_pFtuBasePtrs[eInstance]); + } + /* enable the quadrature*/ + FTU_HWA_EnableQuadratureMode(s_pFtuBasePtrs[eInstance]); + } + return eStatus; +} +/** + * @brief Enable FTU interrupt + * + * @param eInstance the selected FTU instance + * @param u32InterruptMask interrupt enable mask + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_EnableInterrupt(const FTU_InstanceType eInstance, uint32_t u32InterruptMask) +{ + FTU_StatusType eStatus = FTU_STATUS_SUCCESS; + uint32_t u32Loop; + if ((uint32_t)eInstance >= FTU_INSTANCE_COUNT) + { + eStatus = FTU_STATUS_PARAM_INVALID; + } + else + { + for(u32Loop = 0u; u32Loop < FTU_CHANNEL_CONTROLS_COUNT; u32Loop++) + { + if (0u != (u32InterruptMask & ((uint32_t)FTU_INTR_MASK_CHANNEL_0 << u32Loop))) + { + /* Enable Channel Interrupt */ + FTU_HWA_EnableChannelInterrupt(s_pFtuBasePtrs[eInstance], (uint8_t)u32Loop); + } + } + + if (0u != (u32InterruptMask & (uint32_t)FTU_INTR_MASK_OVERFLOW)) + { + /* Enable Overflow Interrupt */ + FTU_HWA_EnableOverflowInterrupt(s_pFtuBasePtrs[eInstance]); + } + + if (0u != (u32InterruptMask & (uint32_t)FTU_INTR_MASK_FAULT)) + { + /* Enable Fault Interrupt */ + FTU_HWA_EnableModuleFaultInterrupt(s_pFtuBasePtrs[eInstance]); + } + + if (0u != (u32InterruptMask & (uint32_t)FTU_INTR_MASK_RELOAD_POINT)) + { + /* Enable Reload Point Interrupt */ + FTU_HWA_EnableReloadPointInterrupt(s_pFtuBasePtrs[eInstance]); + } + } + return eStatus; +} + +/** + * @brief Disable FTU interrupt + * + * @param eInstance the selected FTU instance + * @param u32InterruptMask interrupt disable mask + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_DisableInterrupt(const FTU_InstanceType eInstance, uint32_t u32InterruptMask) +{ + FTU_StatusType eStatus = FTU_STATUS_SUCCESS; + uint32_t u32Loop; + if ((uint32_t)eInstance >= FTU_INSTANCE_COUNT) + { + eStatus = FTU_STATUS_PARAM_INVALID; + } + else + { + for(u32Loop = 0; u32Loop < FTU_CHANNEL_CONTROLS_COUNT; u32Loop++) + { + if (0u != (u32InterruptMask & ((uint32_t)FTU_INTR_MASK_CHANNEL_0 << u32Loop))) + { + /* Disable Channel Interrupt */ + FTU_HWA_DisableChannelInterrupt(s_pFtuBasePtrs[eInstance], (uint8_t)u32Loop); + } + } + + if (0u != (u32InterruptMask & (uint32_t)FTU_INTR_MASK_OVERFLOW)) + { + /* Disable Overflow Interrupt */ + FTU_HWA_DisableOverflowInterrupt(s_pFtuBasePtrs[eInstance]); + } + + if (0u != (u32InterruptMask & (uint32_t)FTU_INTR_MASK_FAULT)) + { + /* Disable Fault Interrupt */ + FTU_HWA_DisableModuleFaultInterrupt(s_pFtuBasePtrs[eInstance]); + } + + if (0u != (u32InterruptMask & (uint32_t)FTU_INTR_MASK_RELOAD_POINT)) + { + /* Disable Reload Point Interrupt */ + FTU_HWA_DisableReloadPointInterrupt(s_pFtuBasePtrs[eInstance]); + } + } + return eStatus; +} + +/** + * @brief Clear the fault flag of the FTU instance + * + * @param eInstance the selected FTU instance + * @param u32FaultFlag flag to clear + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_ClearFault(const FTU_InstanceType eInstance, uint32_t u32FaultFlag) +{ + FTU_StatusType eStatus = FTU_STATUS_SUCCESS; + if ((uint32_t)eInstance >= FTU_INSTANCE_COUNT) + { + eStatus = FTU_STATUS_PARAM_INVALID; + } + else + { + FTU_HWA_ClearModuleFaultFlag(s_pFtuBasePtrs[eInstance], (uint8_t)u32FaultFlag); + } + return eStatus; +} + +/** + * @brief Get the fault flag of the FTU instance + * + * @param eInstance the selected FTU instance + * @return uint32_t the fault flag of the selected Ftu instance + */ +uint32_t FTU_GetFaultFlag(const FTU_InstanceType eInstance) +{ + uint32_t u32FaultFlag = 0; + if ((uint32_t)eInstance < FTU_INSTANCE_COUNT) + { + u32FaultFlag = FTU_HWA_ReadModuleFaultFlag(s_pFtuBasePtrs[eInstance]); + } + return u32FaultFlag; +} + + +/** + * @brief Enable ftu channel DMA + * + * @param eInstance the selected FTU instance + * @param u32DmaMask The dma channel mask. + * @return FTU_StatusType whether the operation is successfully + */ + +FTU_StatusType FTU_EnableChannelDma(const FTU_InstanceType eInstance, uint32_t u32DmaMask) +{ + FTU_StatusType eStatus = FTU_STATUS_SUCCESS; + uint32_t u32Loop; + if ((uint32_t)eInstance >= FTU_INSTANCE_COUNT) + { + eStatus = FTU_STATUS_PARAM_INVALID; + } + else + { + for(u32Loop = 0u; u32Loop < FTU_CHANNEL_CONTROLS_COUNT; u32Loop++) + { + if (0u != (u32DmaMask & ((uint32_t)FTU_INTR_MASK_CHANNEL_0 << u32Loop))) + { + /* Enable Channel Interrupt */ + FTU_HWA_EnableChannelDma(s_pFtuBasePtrs[eInstance], (uint8_t)u32Loop); + } + } + + } + return eStatus; +} + +/** + * @brief Initialize a Expect Edge Number Measurement channel + * + * @param eInstance the selected FTU instance + * @param pExpectEdgeNumMeasure measurement configuration. + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_ExpectEdgeNumberMeasureChannelInit(const FTU_InstanceType eInstance, FTU_ExpectEdgeNumberMeasureType *pExpectEdgeNumMeasure) +{ + FTU_StatusType eStatus = FTU_STATUS_SUCCESS; + if ( ((uint32_t)eInstance >= FTU_INSTANCE_COUNT) + || (pExpectEdgeNumMeasure->u8Channel >= FTU_CHANNEL_CONTROLS_COUNT) + || (pExpectEdgeNumMeasure->u8Channel & 1u)) + { + eStatus = FTU_STATUS_PARAM_INVALID; + } + else + { + FTU_HWA_ConfigChannelMode(s_pFtuBasePtrs[eInstance], pExpectEdgeNumMeasure->u8Channel, + FTU_CHANNEL_MODE_INPUT); + set_ftu_input_edge(s_pFtuBasePtrs[eInstance], pExpectEdgeNumMeasure->u8Channel, + pExpectEdgeNumMeasure->eEdgeMode); + FTU_HWA_ConfigChannelEdgeLevel(s_pFtuBasePtrs[eInstance], pExpectEdgeNumMeasure->u8Channel + 1u, + FTU_CHANNEL_EDGE_NOT_USED); + FTU_HWA_ConfigEdgeNumber(s_pFtuBasePtrs[eInstance], pExpectEdgeNumMeasure->u8Channel + 1, + pExpectEdgeNumMeasure->u8ExpectEdgeNumber); + if (FTU_MEASURE_CONTINUOUS_MODE == pExpectEdgeNumMeasure->eContinuouslyMode) + { + FTU_HWA_EnableMeasureContinous(s_pFtuBasePtrs[eInstance], pExpectEdgeNumMeasure->u8Channel); + } + else + { + FTU_HWA_DisableMeasureContinous(s_pFtuBasePtrs[eInstance], pExpectEdgeNumMeasure->u8Channel); + } + /* Must put the ICM_MODE setting at the end, otherwise it will not be configured correctly. */ + FTU_HWA_ConfigInputCaptureMeasureMode( s_pFtuBasePtrs[eInstance], pExpectEdgeNumMeasure->u8Channel, + FTU_MEASURE_EXPECT_EDGE_NUMBER); + } + return eStatus; +} + +/** + * @brief Initialize a Edge Number Measurement channel + * + * @param eInstance the selected FTU instance + * @param pEdgeNumMeasure measurement configuration. + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_EdgeNumberMeasureChannelInit(const FTU_InstanceType eInstance, FTU_EdgeNumberMeasureType *pEdgeNumMeasure) +{ + FTU_StatusType eStatus = FTU_STATUS_SUCCESS; + if ( ((uint32_t)eInstance >= FTU_INSTANCE_COUNT) + || (pEdgeNumMeasure->u8Channel >= FTU_CHANNEL_CONTROLS_COUNT) + || (pEdgeNumMeasure->u8Channel & 1u) + || (pEdgeNumMeasure->u32StartWindow >= pEdgeNumMeasure->u32EndWindow) + || (pEdgeNumMeasure->u32StartWindow > s_aFtuMaxCounter[eInstance])) + { + eStatus = FTU_STATUS_PARAM_INVALID; + } + else + { + FTU_HWA_ConfigChannelMode(s_pFtuBasePtrs[eInstance], pEdgeNumMeasure->u8Channel, + FTU_CHANNEL_MODE_INPUT); + set_ftu_input_edge(s_pFtuBasePtrs[eInstance], pEdgeNumMeasure->u8Channel, pEdgeNumMeasure->eEdgeMode); + + FTU_HWA_ConfigChannelEdgeLevel(s_pFtuBasePtrs[eInstance], pEdgeNumMeasure->u8Channel + 1u, + FTU_CHANNEL_EDGE_NOT_USED); + FTU_HWA_ConfigInputCaptureMeasureMode(s_pFtuBasePtrs[eInstance], pEdgeNumMeasure->u8Channel, + FTU_MEASURE_ICENM_WIND_WRITE); + FTU_HWA_SetChannelValue(s_pFtuBasePtrs[eInstance], pEdgeNumMeasure->u8Channel, + pEdgeNumMeasure->u32StartWindow); + FTU_HWA_SetChannelValue(s_pFtuBasePtrs[eInstance], pEdgeNumMeasure->u8Channel + 1u, + pEdgeNumMeasure->u32EndWindow); + FTU_HWA_ConfigInputCaptureMeasureMode( s_pFtuBasePtrs[eInstance], pEdgeNumMeasure->u8Channel, + FTU_MEASURE_EDGE_NUMBER); + if (FTU_MEASURE_CONTINUOUS_MODE == pEdgeNumMeasure->eContinuouslyMode) + { + FTU_HWA_EnableMeasureContinous(s_pFtuBasePtrs[eInstance], pEdgeNumMeasure->u8Channel); + } + else + { + FTU_HWA_DisableMeasureContinous(s_pFtuBasePtrs[eInstance], pEdgeNumMeasure->u8Channel); + } + + } + return eStatus; +} + +/** + * @brief Get the expect edge number result of the channel + * + * @param eInstance the selected FTU instance + * @param u8Channel FTU channel number, range is 0-7. + * @param pResult point to the result buffer. + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_GetExpectEdgeNumberResult(const FTU_InstanceType eInstance, uint8_t u8Channel, FTU_ExpectEdgeNumberResultType *pResult) +{ + FTU_StatusType eStatus = FTU_STATUS_SUCCESS; + if ( ((uint32_t)eInstance >= FTU_INSTANCE_COUNT) + || (u8Channel >= FTU_CHANNEL_CONTROLS_COUNT) + || (u8Channel & 1u)) + { + eStatus = FTU_STATUS_PARAM_INVALID; + } + else + { + pResult->u32FirstEdgeTime = FTU_HWA_GetChannelValue(s_pFtuBasePtrs[eInstance], u8Channel); + pResult->u32LastEdgeTime = FTU_HWA_GetChannelValue(s_pFtuBasePtrs[eInstance], u8Channel + 1); + } + return eStatus; +} + +/** + * @brief Get Edge number counter + * + * @param eInstance the selected FTU instance + * @param u8Channel FTU channel number. + * @return uint8_t Edge number counter + */ +uint8_t FTU_GetEdgeNumberCount(const FTU_InstanceType eInstance, uint8_t u8Channel) +{ + uint8_t u8Count = 0; + if ( ((uint32_t)eInstance >= FTU_INSTANCE_COUNT) + || (u8Channel >= FTU_CHANNEL_CONTROLS_COUNT) + || (u8Channel & 1u)) + { + + } + else + { + u8Count = FTU_HWA_GetEdgeNumberCount(s_pFtuBasePtrs[eInstance], u8Channel); + } + return u8Count; +} +/** + * @brief Initialize a signal measure channel + * + * @param eInstance the selected FTU instance + * @param pMeasure measurement configuration. + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_SignalMeasureChannelInit(const FTU_InstanceType eInstance, FTU_SignalMeasureType *pMeasure) +{ + FTU_StatusType eStatus = FTU_STATUS_SUCCESS; + if ( ((uint32_t)eInstance >= FTU_INSTANCE_COUNT) + || (pMeasure->u8Channel >= FTU_CHANNEL_CONTROLS_COUNT) + || (pMeasure->u8Channel & 1u)) + { + eStatus = FTU_STATUS_PARAM_INVALID; + } + else + { + FTU_HWA_ConfigInputCaptureMeasureMode(s_pFtuBasePtrs[eInstance], pMeasure->u8Channel, FTU_MEASURE_MODE_OFF); + FTU_HWA_ConfigInputCaptureMeasureMode(s_pFtuBasePtrs[eInstance], pMeasure->u8Channel + 1u, FTU_MEASURE_MODE_OFF); + FTU_HWA_DisableChannelEnhancedPhase(s_pFtuBasePtrs[eInstance], pMeasure->u8Channel); + FTU_HWA_DisableChannelPhase(s_pFtuBasePtrs[eInstance], pMeasure->u8Channel); + FTU_HWA_DisableChannelEnhancedPhase(s_pFtuBasePtrs[eInstance], pMeasure->u8Channel + 1u); + FTU_HWA_DisableChannelPhase(s_pFtuBasePtrs[eInstance], pMeasure->u8Channel + 1u); + FTU_HWA_DisableModuleCpwmMode(s_pFtuBasePtrs[eInstance]); + + FTU_HWA_ConfigChannelMode(s_pFtuBasePtrs[eInstance], pMeasure->u8Channel, FTU_CHANNEL_MODE_INPUT); + FTU_HWA_ConfigChannelMode(s_pFtuBasePtrs[eInstance], pMeasure->u8Channel + 1u, FTU_CHANNEL_MODE_INPUT); + if (FTU_SIGNAL_MEASURE_HIGH_TIME == pMeasure->eMeasureMode) + { + FTU_HWA_ConfigChannelEdgeLevel(s_pFtuBasePtrs[eInstance], pMeasure->u8Channel, FTU_CHANNEL_EDGE_RISING); + FTU_HWA_ConfigChannelEdgeLevel(s_pFtuBasePtrs[eInstance], pMeasure->u8Channel + 1u, FTU_CHANNEL_EDGE_FALLING); + FTU_HWA_ConfigInputCaptureMeasureMode(s_pFtuBasePtrs[eInstance], pMeasure->u8Channel, FTU_MEASURE_MODE_DUTY_CYCLE); + FTU_HWA_ConfigInputCaptureMeasureMode(s_pFtuBasePtrs[eInstance], pMeasure->u8Channel + 1, FTU_MEASURE_MODE_DUTY_CYCLE); + FTU_HWA_SetChannelPolarity(s_pFtuBasePtrs[eInstance], 1u << pMeasure->u8Channel); + } + else if (FTU_SIGNAL_MEASURE_LOW_TIME == pMeasure->eMeasureMode) + { + FTU_HWA_ConfigChannelEdgeLevel(s_pFtuBasePtrs[eInstance], pMeasure->u8Channel, FTU_CHANNEL_EDGE_RISING); + FTU_HWA_ConfigChannelEdgeLevel(s_pFtuBasePtrs[eInstance], pMeasure->u8Channel + 1u, FTU_CHANNEL_EDGE_FALLING); + FTU_HWA_ConfigInputCaptureMeasureMode(s_pFtuBasePtrs[eInstance], pMeasure->u8Channel, FTU_MEASURE_MODE_DUTY_CYCLE); + FTU_HWA_ConfigInputCaptureMeasureMode(s_pFtuBasePtrs[eInstance], pMeasure->u8Channel + 1u, FTU_MEASURE_MODE_DUTY_CYCLE); + FTU_HWA_ClearChannelPolarity(s_pFtuBasePtrs[eInstance], 1u << pMeasure->u8Channel); + } + else if (FTU_SIGNAL_MEASURE_PERIOD_RISING_EDGE == pMeasure->eMeasureMode) + { + FTU_HWA_ConfigChannelEdgeLevel(s_pFtuBasePtrs[eInstance], pMeasure->u8Channel, FTU_CHANNEL_EDGE_RISING); + FTU_HWA_ConfigChannelEdgeLevel(s_pFtuBasePtrs[eInstance], pMeasure->u8Channel + 1u, FTU_CHANNEL_EDGE_NOT_USED); + FTU_HWA_ConfigInputCaptureMeasureMode(s_pFtuBasePtrs[eInstance], pMeasure->u8Channel, FTU_MEASURE_MODE_PERIOD); + FTU_HWA_ConfigInputCaptureMeasureMode(s_pFtuBasePtrs[eInstance], pMeasure->u8Channel + 1u, FTU_MEASURE_MODE_PERIOD); + } + else if (FTU_SIGNAL_MEASURE_PERIOD_FALLING_EDGE == pMeasure->eMeasureMode) + { + FTU_HWA_ConfigChannelEdgeLevel(s_pFtuBasePtrs[eInstance], pMeasure->u8Channel, FTU_CHANNEL_EDGE_FALLING); + FTU_HWA_ConfigChannelEdgeLevel(s_pFtuBasePtrs[eInstance], pMeasure->u8Channel + 1u, FTU_CHANNEL_EDGE_NOT_USED); + FTU_HWA_ConfigInputCaptureMeasureMode(s_pFtuBasePtrs[eInstance], pMeasure->u8Channel, FTU_MEASURE_MODE_PERIOD); + FTU_HWA_ConfigInputCaptureMeasureMode(s_pFtuBasePtrs[eInstance], pMeasure->u8Channel + 1u, FTU_MEASURE_MODE_PERIOD); + } + + if (FTU_MEASURE_CONTINUOUS_MODE == pMeasure->eContinuouslyMode) + { + FTU_HWA_EnableMeasureContinous(s_pFtuBasePtrs[eInstance], pMeasure->u8Channel); + } + else + { + FTU_HWA_DisableMeasureContinous(s_pFtuBasePtrs[eInstance], pMeasure->u8Channel); + } + + if (FTU_MEASURE_START_IMMEDIATELY == pMeasure->eStartMode) + { + FTU_HWA_EnableMeasureStartImmd(s_pFtuBasePtrs[eInstance], pMeasure->u8Channel); + } + else + { + FTU_HWA_DisableMeasureStartImmd(s_pFtuBasePtrs[eInstance], pMeasure->u8Channel); + } + } + return eStatus; +} +/** + * @brief Re-start measurement when in single mode + * + * @param eInstance the selected FTU instance + * @param u8Channel FTU channel number, range is 0-7. + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_SignalMeasureChannelSingle(const FTU_InstanceType eInstance, uint8_t u8Channel) +{ + FTU_StatusType eStatus = FTU_STATUS_SUCCESS; + if ( ((uint32_t)eInstance >= FTU_INSTANCE_COUNT) + || (u8Channel >= FTU_CHANNEL_CONTROLS_COUNT) + || (u8Channel & 1u)) + { + eStatus = FTU_STATUS_PARAM_INVALID; + } + else + { + FTU_HWA_SingleMeasurement(s_pFtuBasePtrs[eInstance], u8Channel); + } + return eStatus; +} + +/** + * @brief Get the measurement result of the channel + * + * @param eInstance the selected FTU instance + * @param u8Channel FTU channel number, range is 0-7. + * @param pResult point to the result buffer. + * @return FTU_StatusType whether the operation is successfully + */ +FTU_StatusType FTU_GetSignalMeasureResult(const FTU_InstanceType eInstance, uint8_t u8Channel, FTU_SignalMeasureValueType *pResult) +{ + FTU_StatusType eStatus = FTU_STATUS_SUCCESS; + if ( ((uint32_t)eInstance >= FTU_INSTANCE_COUNT) + || (u8Channel >= FTU_CHANNEL_CONTROLS_COUNT) + || (u8Channel & 1u)) + { + eStatus = FTU_STATUS_PARAM_INVALID; + } + else + { + FTU_MeasurementModeType eMeasureMode = FTU_HWA_GetMeasureMode(s_pFtuBasePtrs[eInstance], u8Channel); + if (FTU_MEASURE_MODE_DUTY_CYCLE == eMeasureMode) + { + if (FTU_HWA_GetChannelPolarity(s_pFtuBasePtrs[eInstance], 1u << u8Channel)) + { + pResult->u32StartTime = FTU_HWA_GetChannelValue(s_pFtuBasePtrs[eInstance], u8Channel); + pResult->u32EndTime = FTU_HWA_GetChannelValue(s_pFtuBasePtrs[eInstance], u8Channel + 1); + } + else + { + pResult->u32StartTime = FTU_HWA_GetChannelValue(s_pFtuBasePtrs[eInstance], u8Channel + 1); + pResult->u32EndTime = FTU_HWA_GetChannelValue(s_pFtuBasePtrs[eInstance], u8Channel); + } + } + else if(FTU_MEASURE_MODE_PERIOD == eMeasureMode) + { + pResult->u32StartTime = FTU_HWA_GetChannelValue(s_pFtuBasePtrs[eInstance], u8Channel + 1); + pResult->u32EndTime = FTU_HWA_GetChannelValue(s_pFtuBasePtrs[eInstance], u8Channel); + } + else + { + pResult->u32StartTime = 0u; + pResult->u32EndTime = 0u; + } + } + return eStatus; +} + + + +/** + * @brief Interrupt IRQ handle of FTU instance + * + * @param eInstance the selected FTU instance + */ +void FTUn_IRQHandler(const FTU_InstanceType eInstance) +{ + uint32_t u32FaultFlag = 0u; + uint8_t u8FaultEnable = FTU_HWA_ReadFaultIntrEnable(s_pFtuBasePtrs[eInstance]); + uint8_t u8OverflowFlag = FTU_HWA_ReadModuleOverflowFlag(s_pFtuBasePtrs[eInstance]); + uint8_t u8ReloadFlag = FTU_HWA_ReadReloadIntrEnable(s_pFtuBasePtrs[eInstance]); + uint32_t u32Loop, u32ChannelIntrFlag = 0; + uint16_t u16TimeStamp; + + u8OverflowFlag = FTU_HWA_ReadModuleOverflowIntrEnable(s_pFtuBasePtrs[eInstance]) & u8OverflowFlag; + u8ReloadFlag = FTU_HWA_ReadModuleReloadFlag(s_pFtuBasePtrs[eInstance]) & u8ReloadFlag; + if(0u != u8FaultEnable) + { + u32FaultFlag = FTU_HWA_ReadModuleFaultFlag(s_pFtuBasePtrs[eInstance]); + } + + /* Clear interrupt flag*/ + if (0u != u8OverflowFlag) + { + FTU_HWA_ClearOverflowFlag(s_pFtuBasePtrs[eInstance]); + } + if (0u != u8ReloadFlag) + { + FTU_HWA_ClearReloadFlag(s_pFtuBasePtrs[eInstance]); + } + + for (u32Loop = 0U; u32Loop < FTU_CHANNEL_CONTROLS_COUNT; u32Loop++) + { + if ((0u != FTU_HWA_ReadChannelInterruptFlag(s_pFtuBasePtrs[eInstance], (uint8_t)u32Loop)) && + (0u != FTU_HWA_ReadChannelInterruptEnableFlag(s_pFtuBasePtrs[eInstance], (uint8_t)u32Loop))) + { + FTU_HWA_ClearChannelInterruptFlag(s_pFtuBasePtrs[eInstance], (uint8_t)u32Loop); + u32ChannelIntrFlag |= (uint8_t)(1u << u32Loop); + } + } + + /* call callback functions*/ + if ((0u != u8OverflowFlag) && (NULL != s_pOverflowCallback[eInstance])) + { + s_pOverflowCallback[eInstance](); + } + + if ((0u != u8ReloadFlag) && (NULL != s_pReloadPointCallback[eInstance])) + { + s_pReloadPointCallback[eInstance](); + } + + if ((0u != u32FaultFlag) && (NULL != s_pFaultCallback[eInstance])) + { + for (u32Loop = 0U; u32Loop < FTU_FAULT_COUNT; u32Loop++) + { + if (0u != (u32FaultFlag & ((uint32_t)1u << u32Loop))) + { + s_pFaultCallback[eInstance](u32Loop); + } + } + } + + if ((0u != u32ChannelIntrFlag) && (NULL != s_pChannelCallback[eInstance])) + { + for (u32Loop = 0U; u32Loop < FTU_CHANNEL_CONTROLS_COUNT; u32Loop++) + { + if (0u != (u32ChannelIntrFlag & ((uint32_t)1u << u32Loop))) + { + u16TimeStamp = (uint16_t)FTU_HWA_GetChannelValue(s_pFtuBasePtrs[eInstance], (uint8_t)u32Loop); + s_pChannelCallback[eInstance](u32Loop, u16TimeStamp); + } + } + } +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_gpio.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_gpio.c new file mode 100644 index 0000000..68080a3 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_gpio.c @@ -0,0 +1,175 @@ +/** + * @file fc7xxx_driver_gpio.h + * @author Flagchip + * @brief FC7xxx GPIO driver type definition and API + * @version 0.1.0 + * @date 2023-2-14 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/******************************************************************************** +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 31/12/2022 Flagchip0121 N/A First version for FC7240 +********************************************************************************/ + +#include "fc7xxx_driver_gpio.h" + +/** @brief Gpio instance list */ +static GPIO_Type *s_pGpioInstanceTable[GPIO_INSTANCE_COUNT] = GPIO_BASE_PTRS; + +/** + * @brief Initialize GPIO. + * + * @param eGpio GPIO instance + * @param pInitStruct Initialization structure of GPIO. + */ +GPIO_StatusType GPIO_InitPins(const GPIO_InstanceType eGpio, const GPIO_InitType *const pInitStruct) +{ + GPIO_StatusType eRet = GPIO_STATUS_SUCCESS; + GPIO_Type *pGpio; + uint32_t u32TempPins = 0U; + uint8_t u8PinIndex = 0U; + + if ((uint32_t)eGpio >= GPIO_INSTANCE_COUNT) + { + eRet = GPIO_STATUS_PARAM_INVALID; + } + else + { + pGpio = s_pGpioInstanceTable[(uint32_t)(eGpio)]; + u32TempPins = pInitStruct->u32GpioPins; + while (u32TempPins != 0u) + { + if ((u32TempPins & ((uint32_t)1 << u8PinIndex)) != 0u) + { + if (GPIO_OUT == pInitStruct->ePinDirection) + { + if (GPIO_LOW == pInitStruct->ePinLevel) + { + GPIO_HWA_ClearPinOutput(pGpio, u8PinIndex); + } + else + { + GPIO_HWA_SetPinOutput(pGpio, u8PinIndex); + } + GPIO_HWA_SetPinDirection(pGpio, u8PinIndex); + } + else if (GPIO_IN == pInitStruct->ePinDirection) + { + GPIO_HWA_ClearPinDirection(pGpio, u8PinIndex); + } + else + { + GPIO_HWA_SetPinInputDisable(pGpio, u8PinIndex); /* GPIO_ZERO == pInitStruct->ePinDirection */ + } + } + else + { + + } + u32TempPins &= (uint32_t)~((uint32_t)1 << u8PinIndex); + u8PinIndex++; + } + } + return eRet; +} +/** + * @brief De-initialize the GPIO pin + * + * @param eGpio Gpio instance enumeration + * @param u32Pins The bit of u32Pins indicate the Pin number of this Gpio instance. + * @return GPIO status type. + */ +GPIO_StatusType GPIO_Deinit(const GPIO_InstanceType eGpio, const uint32_t u32Pins) +{ + DEV_ASSERT(eGpio < GPIO_INSTANCE_COUNT); + + GPIO_StatusType eRet = GPIO_STATUS_SUCCESS; + GPIO_Type *pGpio = s_pGpioInstanceTable[(uint32_t)(eGpio)]; + uint8_t u8PinIndex = 0U; + uint32_t u32TempPins = u32Pins; + + while (u32TempPins != 0) + { + if (u32TempPins & ((uint32_t)1 << u8PinIndex)) + { + GPIO_HWA_ClearPinDirection(pGpio, u8PinIndex); + GPIO_HWA_ClearPinDataOutput(pGpio, u8PinIndex); + GPIO_HWA_ClearPinInputDisable(pGpio, u8PinIndex); + } + u32TempPins &= (uint32_t)~((uint32_t)1 << u8PinIndex); + u8PinIndex++; + } + return eRet; +} + +/** + * @brief Read level of input port pins. + * + * @param eGpio Port instance for GPIO functionality + * @param u32Pins The bit of u32Pins indicate the pin number of this Port. + * @return Pins level + */ +uint32_t GPIO_ReadPins(const GPIO_InstanceType eGpio, const uint32_t u32Pins) +{ + DEV_ASSERT(eGpio < GPIO_INSTANCE_COUNT); + GPIO_Type *pGpio = s_pGpioInstanceTable[(uint32_t)eGpio]; + return (GPIO_HWA_ReadPortDataInput(pGpio) & u32Pins); +} + +/** + * @brief Write gpio level to u32Pins. + * + * @param eGpio Port instance for GPIO functionality + * @param u32Pins The bit of u32Pins indicate the pin number of this Port. + * @param eOutput Output level enumeration + * @return Port return type. + */ +GPIO_StatusType GPIO_WritePins(const GPIO_InstanceType eGpio, const uint32_t u32Pins, const GPIO_PinLevelType eOutput) +{ + GPIO_StatusType eRet = GPIO_STATUS_SUCCESS; + GPIO_Type *pGpio = s_pGpioInstanceTable[(uint32_t)eGpio]; + if (((uint32_t)eGpio >= GPIO_INSTANCE_COUNT) || (eOutput > GPIO_HIGH)) + { + eRet = GPIO_STATUS_PARAM_INVALID; + } + else + { + if (GPIO_HIGH == eOutput) + { + GPIO_HWA_SetPortOutput(pGpio, u32Pins); + } + else + { + GPIO_HWA_ClearPortOutput(pGpio, u32Pins); + } + } + return eRet; +} + +/** + * @brief Toggle gpio api + * + * @param eGpio eGpio Port instance for GPIO functionality + * @param u32Pins The bit of u32Pins indicate the pin number of this Port. + * @return Port return type. + */ +GPIO_StatusType GPIO_Toggle(const GPIO_InstanceType eGpio, const uint32_t u32Pins) +{ + GPIO_StatusType eRet = GPIO_STATUS_SUCCESS; + GPIO_Type *pGpio = s_pGpioInstanceTable[(uint32_t)eGpio]; + if ((uint32_t)(eGpio >= GPIO_INSTANCE_COUNT)) + { + eRet = GPIO_STATUS_PARAM_INVALID; + } + else + { + GPIO_HWA_TogglePort(pGpio, u32Pins); + } + return eRet; +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_hsm.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_hsm.c new file mode 100644 index 0000000..094c12d --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_hsm.c @@ -0,0 +1,648 @@ +/** + * @file fc7xxx_driver_hsm.c + * @author Flagchip0103 + * @brief FC7xxx HSM driver source file + * @version 0.1.0 + * @date 2023-12-20 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-20 Flagchip0103 N/A First version for FC7240 + ******************************************************************************** */ + +#include "fc7xxx_driver_hsm.h" + +/* ################################################################################## */ +/* ##################################### Macros ##################################### */ + +typedef enum { + HSM_CMD_ID_TRNG = 0xb55du, + HSM_CMD_ID_SHA = 0xfce2u, + HSM_CMD_ID_ECC_SIGN = 0xde41u, + HSM_CMD_ID_ECC_VERIFY = 0xa522u, + HSM_CMD_ID_SM2_GENKEYPAIR = 0xc9ddu, + HSM_CMD_ID_SM2_ENCRY = 0x30f1u, + HSM_CMD_ID_SM2_DECRY = 0x6351u, + HSM_CMD_ID_SM2_SIGN = 0xe814u, + HSM_CMD_ID_SM2_VERIFY = 0x6e1eu, + HSM_CMD_ID_SM2_GENZA = 0xdbbeu, + HSM_CMD_ID_SM2_GENHASH = 0x5ce5u, + HSM_CMD_ID_SM4_ENCRY = 0xfd5au, + HSM_CMD_ID_SM4_DECRY = 0x4aedu, + HSM_CMD_ID_ECC_ENCRY = 0x4d3fu, + HSM_CMD_ID_ECC_DECRY = 0x97e4u, + HSM_CMD_ID_REQUEST_AUTH = 0x33d9u, + HSM_CMD_ID_LIFECYCLE_CHANGE = 0xbe63u, /* prefa,fa not support in sdk */ + HSM_CMD_ID_DEBUG_AUTH = 0x3928u, // TODO: delete + HSM_CMD_ID_ISP_AUTH = 0xAFBAu, // TODO: delete + HSM_CMD_ID_REVOKE_MRK = 0x19bbu, // TODO: delete + HSM_CMD_ID_REVOKE_UMRK = 0xfdb4u, // TODO: delete + HSM_CMD_ID_USER_KEY_ERASE = 0xac3au, // TODO: delete + HSM_CMD_ID_FLASHTEST_VERIFY = 0xcc29u, // TODO: delete + HSM_CMD_ID_UESR_CODE_VERIFY = 0x72d6u, // TODO: delete + HSM_CMD_ID_CANCEL_JOB = 0x17c3u, + HSM_CMD_ID_SELF_TEST = 0x4e93u, + HSM_CMD_ID_NVR_OTP = 0x2cd8u, + HSM_CMD_ID_LIFECYCLE_CHANGE_TAKE_EFFECT = 0x30fau, + HSM_CMD_ID_USER_KEY_MANAGE = 0xf4cfu, + HSM_CMD_ID_SPACE_MANAGE = 0x4ac0u, + HSM_CMD_ID_AES_ENCRY = 0xa2c6u, + HSM_CMD_ID_AES_DECRY = 0x6576u, + HSM_CMD_ID_CMAC_GEN = 0xf0b9u, + HSM_CMD_ID_XMAC_GEN = 0x32acu, + HSM_CMD_ID_CCM_ENCRY = 0x862fu, + HSM_CMD_ID_CCM_DECRY = 0x79a4u, + HSM_CMD_ID_GCM_ENCRY = 0xd1a6u, + HSM_CMD_ID_GCM_DECRY = 0xc0a3u, + HSM_CMD_ID_MD5 = 0x9371u, + HSM_CMD_ID_SM3 = 0xcfe5u, + HSM_CMD_ID_MONOTONIC_COUNTER = 0xdc97u, + HSM_CMD_ID_RSA = 0x866cu, + HSM_CMD_ID_USRK_GEN = 0xddb7u, // TODO: delete + HSM_CMD_ID_LOAD_FIRMWARE = 0x503du, + HSM_CMD_ID_DH_SM = 0x7F8Au, + HSM_CMD_ID_ECDH = 0x4b06u, + HSM_CMD_ID_DH = 0xb81bu, + HSM_CMD_ID_DH_PBKDF2 = 0xa47du, + HSM_CMD_ID_DH_GMPBKDF = 0xbe1fu, + HSM_CMD_ID_SCATTER_HASH = 0x465du, + HSM_CMD_ID_RAW_AESM = 0x42fdu, + HSM_CMD_ID_SCATTER_MAC = 0xa9e1u, + HSM_CMD_ID_ECC_GENKEYPAIR = 0x16b6u, + HSM_CMD_ID_RSA_SSA_PKCS1V15_SIGN = 0xd047u, + HSM_CMD_ID_RSA_SSA_PSS_SIGN = 0xd873u, + HSM_CMD_ID_RSA_ES_PKCS1V15_ENCRYPT = 0x3090u, + HSM_CMD_ID_RSA_ES_OAEP_ENCRYPT = 0x7F0Bu, + HSM_CMD_ID_RSA_SSA_PKCS1V15_VERIFY = 0x1577u, + HSM_CMD_ID_RSA_SSA_PSS_VERIFY = 0x0076u, + HSM_CMD_ID_RSA_ES_PKCS1V15_DECRYPT = 0x26d5u, + HSM_CMD_ID_RSA_ES_OAEP_DECRYPT = 0xc284u, +} HSM_CmdIdType; + +#define HSMCOM_TRNG_SRC_0 0x40cau +#define HSMCOM_TRNG_SRC_1 0xc51cu +#define HSMCOM_TRNG_SRC_ANY 0x359bu +#define HSMCOM_TRNG_SRC_XOR 0x80a5u +#define HSMCOM_DRNG_SRC 0x648Cu +#define HSMCOM_LIFECYCLE_OEM_DEV 0x4792u +#define HSMCOM_LIFECYCLE_OEM_PDT 0xA4F1u +#define HSMCOM_LIFECYCLE_IN_FIELD 0xaddcu +#define HSMCOM_INCREASE_COUNTER 0xd27fu +#define HSMCOM_READ_COUNTER 0x1875u +#define HSMCOM_SET_COUNTER_VAL 0x439du +#define HSMCOM_INCREASE_COUNTER_WHEN_EQUAL 0x6834u +#define HSMCOM_READ_ALL_FLEX_COUNTERS 0x6a47u +#define HSMCOM_SET_SINGLE_CFG 0x9e4du +#define HSMCOM_GET_SINGLE_CFG 0xaf42u +#define HSMCOM_INCREASE_COUNTER2 0xd280u +#define HSMCOM_READ_COUNTER2 0x1876u +#define HSMCOM_NVR_OTP_READ 0x9C2Fu +#define HSMCOM_NVR_OTP_WRITE 0x358Cu +#define HSMCOM_KEYMANAGER_IMPORT_USER_KEY 0xdcf1u +#define HSMCOM_KEYMANAGER_REVOKE_USER_KEY 0x7278u +#define HSMCOM_KEYMANAGER_EXPORT_USER_KEY 0xd8c9u +#define HSMCOM_KEYMANAGER_GEN_UESR_KEY 0x1853u +#define HSMCOM_KEYMANAGER_ENABLE_KEY_RAM_COPY 0x5ec5u +#define HSMCOM_KEYMANAGER_DISABLE_KEY_RAM_COPY 0x5918u +#define HSMCOM_KEYSPACE_GET_STATUS 0xe39cu +#define HSMCOM_KEYSPACE_NEATEN 0xb12bu +#define HSMCOM_REVOK_UMRK0 0x5edcu +#define HSMCOM_REVOK_UMRK1 0x20d9u +#define HSMCOM_REVOK_UMRK2 0x6ba1u +#define HSMCOM_REVOK_UMRK3 0xac50u + +/* ################################################################################## */ +/* ################################# Local Variables ################################ */ +#define AUTH_CHECK_DATA_BYTE_CNT 32 +static uint32_t s_aHsmDat[8]; +static HSMCom_AuthCheckType s_tHsmDummyCfg = {0, 0, &(s_aHsmDat[0]), &(s_aHsmDat[0]), &(s_aHsmDat[0]), &(s_aHsmDat[0]), &(s_aHsmDat[0]), AUTH_CHECK_DATA_BYTE_CNT}; + +/* ################################################################################## */ +/* ########################### Local Functions Prototype ############################ */ + +/* ################################################################################## */ +/* ################################# Local Functions ############################### */ +static HSM_StatusType hsm_assign_val(HSM_CmdType *pCmd, uint32_t u32Cmd, uint32_t u32Address) +{ + HSM_StatusType eRet = HSM_STATUS_SUCCESS; + + if (NULL != pCmd) + { + pCmd->u32Cmd = u32Cmd; + pCmd->u32Addr = u32Address; + } + else + { + eRet = HSM_STATUS_PARAM_ERR; + } + + return eRet; +} + +/* ################################################################################## */ +/* ################################# Global Functions ############################### */ +HSM_StatusType HSM_TrueRandGetSrc0(HSM_CmdType *pCmd, const HSMCom_TrueRandType*pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_TRNG << 16u) | HSMCOM_TRNG_SRC_0, (uint32_t)pCfg); +} + +HSM_StatusType HSM_TrueRandGetSrc1(HSM_CmdType *pCmd, const HSMCom_TrueRandType*pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_TRNG << 16u) | HSMCOM_TRNG_SRC_1, (uint32_t)pCfg); +} + +HSM_StatusType HSM_TrueRandGetSrcXor(HSM_CmdType *pCmd, const HSMCom_TrueRandType*pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_TRNG << 16) | HSMCOM_TRNG_SRC_XOR, (uint32_t)pCfg); +} + +HSM_StatusType HSM_TrueRandGet(HSM_CmdType *pCmd, const HSMCom_TrueRandType*pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_TRNG << 16) | HSMCOM_TRNG_SRC_ANY, (uint32_t)pCfg); +} + +HSM_StatusType HSM_PseudoRandGet(HSM_CmdType *pCmd, const HSMCom_TrueRandType*pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_TRNG << 16) | HSMCOM_DRNG_SRC, (uint32_t)pCfg); +} + +HSM_StatusType HSM_Sha(HSM_CmdType *pCmd, const HSMCom_ShaType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SHA << 16), (uint32_t)pCfg); +} + +HSM_StatusType HSM_ShaEx(HSM_CmdType *pCmd, const HSMCom_Sha2Type *pCfg) +{ + uint32_t u32CtrBits = (pCfg->tCfg.eInputFmt & 0x1) | ((pCfg->tCfg.eOutputFmt & 0x1) << 1); + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SHA << 16) | u32CtrBits, (uint32_t)pCfg); +} + +HSM_StatusType HSM_HashInitEx(HSM_CmdType *pCmd, const HSMCom_ShaType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SCATTER_HASH << 16), (uint32_t)pCfg); +} + +HSM_StatusType HSM_HashUpdateEx(HSM_CmdType *pCmd, const HSMCom_ShaType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SCATTER_HASH << 16) | 5u, (uint32_t)pCfg); +} + +HSM_StatusType HSM_HashFinallyEx(HSM_CmdType *pCmd, const HSMCom_ShaType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SCATTER_HASH << 16) | 6u, (uint32_t)pCfg); +} + +HSM_StatusType HSM_CmacAesm(HSM_CmdType *pCmd, const HSMCom_AesmRawApiType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_RAW_AESM << 16), (uint32_t)pCfg); +} + +HSM_StatusType HSM_CmacScatter(HSM_CmdType *pCmd, const HSMCom_ScatterMacType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SCATTER_MAC << 16), (uint32_t)pCfg); +} + +HSM_StatusType HSM_EccSign(HSM_CmdType *pCmd, const HSMCom_EccSignType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_ECC_SIGN << 16 | 1u), (uint32_t)pCfg); +} + +HSM_StatusType HSM_EccVerify(HSM_CmdType *pCmd, const HSMCom_EccVerifyType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_ECC_VERIFY << 16), (uint32_t)pCfg); +} + +HSM_StatusType HSM_EccGenKeyPair(HSM_CmdType *pCmd, const HSMCom_EccKeyPairGenType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_ECC_GENKEYPAIR << 16 | 1u), (uint32_t)pCfg); +} + +HSM_StatusType HSM_Sm2GenKeyPair(HSM_CmdType *pCmd, const HSMCom_Sm2GenKeyPairType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SM2_GENKEYPAIR << 16 | 1u), (uint32_t)pCfg); +} + +HSM_StatusType HSM_Sm2Encry(HSM_CmdType *pCmd, const HSMCom_Sm2EncryptType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SM2_ENCRY << 16 | 1u), (uint32_t)pCfg); +} + +HSM_StatusType HSM_Sm2Decry(HSM_CmdType *pCmd, const HSMCom_Sm2DecryptType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SM2_DECRY << 16), (uint32_t)pCfg); +} + +HSM_StatusType HSM_Sm2Sign(HSM_CmdType *pCmd, const HSMCom_Sm2SignType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SM2_SIGN << 16 | 1u), (uint32_t)pCfg); +} + +HSM_StatusType HSM_Sm2Verify(HSM_CmdType *pCmd, const HSMCom_Sm2VerifyType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SM2_VERIFY << 16), (uint32_t)pCfg); +} + +HSM_StatusType HSM_Sm2GenZa(HSM_CmdType *pCmd, const HSMCom_Sm2GenZaType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SM2_GENZA << 16), (uint32_t)pCfg); +} + +HSM_StatusType HSM_Sm2GenHash(HSM_CmdType *pCmd, const HSMCom_Sm2GenHashType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SM2_GENHASH << 16), (uint32_t)pCfg); +} + +HSM_StatusType HSM_Sm4Encrypt(HSM_CmdType *pCmd, const HSMCom_Sm4EncryptType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SM4_ENCRY << 16), (uint32_t)pCfg); +} + +HSM_StatusType HSM_Sm4Decrypt(HSM_CmdType *pCmd, const HSMCom_Sm4DecryptType *pCfg) +{ + return hsm_assign_val(pCmd, (HSM_CMD_ID_SM4_DECRY << 16), (uint32_t)pCfg); +} + +HSM_StatusType HSM_EccEasyEncry(HSM_CmdType *pCmd, const HSMCom_EccEasyEncryType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_ECC_ENCRY << 16), (uint32_t)pCfg); +} + +HSM_StatusType HSM_EccEasyDecry(HSM_CmdType *pCmd, const HSMCom_EccEasyDecryType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_ECC_DECRY << 16), (uint32_t)pCfg); +} + +HSM_StatusType HSM_EccPointCalc(HSM_CmdType *pCmd, const HSMCom_EccCalcType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_ECC_DECRY << 16) | 1u, (uint32_t)pCfg); +} + +HSM_StatusType HSM_ScatterHashInit(HSM_CmdType *pCmd, const HSMCom_ScatterHashType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SCATTER_HASH << 16), (uint32_t)pCfg); +} + +HSM_StatusType HSM_ScatterHashUpdate(HSM_CmdType *pCmd, const HSMCom_ScatterHashType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SCATTER_HASH << 16) | 5u, (uint32_t)pCfg); +} + +HSM_StatusType HSM_ScatterHashFinally(HSM_CmdType *pCmd, const HSMCom_ScatterHashType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SCATTER_HASH << 16) | 6u, (uint32_t)pCfg); +} + +HSM_StatusType HSM_RequestAuthorization(HSM_CmdType *pCmd, const HSMCom_RequestAuthType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_REQUEST_AUTH << 16), (uint32_t)pCfg); +} + +HSM_StatusType HSM_OemDevEnter(HSM_CmdType *pCmd) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_LIFECYCLE_CHANGE << 16) | HSMCOM_LIFECYCLE_OEM_DEV, (uint32_t)(&s_tHsmDummyCfg)); +} + +HSM_StatusType HSM_OemPdtEnter(HSM_CmdType *pCmd) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_LIFECYCLE_CHANGE << 16) | HSMCOM_LIFECYCLE_OEM_PDT, (uint32_t)(&s_tHsmDummyCfg)); +} + +HSM_StatusType HSM_InFieldEnter(HSM_CmdType *pCmd) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_LIFECYCLE_CHANGE << 16) | HSMCOM_LIFECYCLE_IN_FIELD, (uint32_t)(&s_tHsmDummyCfg)); +} + +HSM_StatusType HSM_CancelJob(HSM_CmdType *pCmd, const HSMCom_CancelJobType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_CANCEL_JOB << 16), (uint32_t)pCfg); +} + +HSM_StatusType HSM_SelfTest(HSM_CmdType *pCmd, const HSMCom_SelfTestType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SELF_TEST << 16), (uint32_t)pCfg); +} + +HSM_StatusType HSM_NvrOtpProgram(HSM_CmdType *pCmd, const HSMCom_NvrOtpType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_NVR_OTP << 16) | HSMCOM_NVR_OTP_WRITE, (uint32_t)pCfg); +} + +HSM_StatusType HSM_NvrOtpRead(HSM_CmdType *pCmd, const HSMCom_NvrOtpType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_NVR_OTP << 16) | HSMCOM_NVR_OTP_READ, (uint32_t)pCfg); +} + +HSM_StatusType HSM_TakeEffect(HSM_CmdType *pCmd) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_LIFECYCLE_CHANGE_TAKE_EFFECT << 16), (uint32_t)0); +} + +HSM_StatusType HSM_UserKeyRevoke(HSM_CmdType *pCmd, const HSMCom_UserKeyManageType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_USER_KEY_MANAGE << 16) | HSMCOM_KEYMANAGER_REVOKE_USER_KEY, (uint32_t)pCfg); +} + +HSM_StatusType HSM_UserKeyImport(HSM_CmdType *pCmd, const HSMCom_UserKeyManageType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_USER_KEY_MANAGE << 16) | HSMCOM_KEYMANAGER_IMPORT_USER_KEY, (uint32_t)pCfg); +} + +HSM_StatusType HSM_UserKeyExport(HSM_CmdType *pCmd, const HSMCom_UserKeyManageType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_USER_KEY_MANAGE << 16) | HSMCOM_KEYMANAGER_EXPORT_USER_KEY, (uint32_t)pCfg); +} + +HSM_StatusType HSM_EraseKeyFlash(HSM_CmdType *pCmd, HSMCom_BasicType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_USER_KEY_ERASE << 16) | 0xa80f, (uint32_t)pCfg); +} + +HSM_StatusType HSM_UserKeyGen(HSM_CmdType *pCmd, const HSMCom_UserKeyManageType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_USER_KEY_MANAGE << 16) | HSMCOM_KEYMANAGER_GEN_UESR_KEY, (uint32_t)pCfg); +} + +HSM_StatusType HSM_EnableKeyRamCopy(HSM_CmdType *pCmd, const HSMCom_UserKeyManageType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_USER_KEY_MANAGE << 16) | HSMCOM_KEYMANAGER_ENABLE_KEY_RAM_COPY, (uint32_t)pCfg); +} + +HSM_StatusType HSM_DisableKeyRamCopy(HSM_CmdType *pCmd, const HSMCom_UserKeyManageType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_USER_KEY_MANAGE << 16) | HSMCOM_KEYMANAGER_DISABLE_KEY_RAM_COPY, (uint32_t)pCfg); +} + +HSM_StatusType HSM_GetKeySpaceStatus(HSM_CmdType *pCmd, const HSMCom_KeySpaceStatusType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SPACE_MANAGE << 16) | HSMCOM_KEYSPACE_GET_STATUS, (uint32_t)pCfg); +} + +HSM_StatusType HSM_TidyUpKeySpace(HSM_CmdType *pCmd, const HSMCom_KeySpaceStatusType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SPACE_MANAGE << 16) | HSMCOM_KEYSPACE_NEATEN, (uint32_t)pCfg); +} + +HSM_StatusType HSM_AesEncrypt(HSM_CmdType *pCmd, const HSMCom_AesEncryptType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_AES_ENCRY << 16), (uint32_t)pCfg); +} + +HSM_StatusType HSM_Aes_FlexEncrypt(HSM_CmdType *pCmd, const HSMCom_FlexAesEncryptType *pCfg) +{ + uint32_t u32CtrBits =0x1 | + ((pCfg->tCfg.epad & 0x1) << 1) | ((pCfg->tCfg.eInputFmt & 0x1) << 2) | + ((pCfg->tCfg.eOutputFmt & 0x1) << 3) | ((pCfg->tCfg.eBackend & 0x1) << 4) ; + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_AES_ENCRY << 16) | u32CtrBits, (uint32_t)pCfg); +} + +HSM_StatusType HSM_AesDecrypt(HSM_CmdType *pCmd, const HSMCom_AesDecryptType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_AES_DECRY << 16), (uint32_t)pCfg); +} + +HSM_StatusType HSM_Aes_FlexDecrypt(HSM_CmdType *pCmd, const HSMCom_FlexAesDecryptType *pCfg) +{ + uint32_t u32CtrBits = 0x1 | + ((pCfg->tCfg.epad & 0x1) << 1) | ((pCfg->tCfg.eInputFmt & 0x1) << 2) | + ((pCfg->tCfg.eOutputFmt & 0x1) << 3) | ((pCfg->tCfg.eBackend & 0x1) << 4) ; + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_AES_DECRY << 16) | u32CtrBits, (uint32_t)pCfg); +} + +HSM_StatusType HSM_CMac(HSM_CmdType *pCmd, const HSMCom_CMacType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_CMAC_GEN << 16), (uint32_t)pCfg); +} + +HSM_StatusType HSM_CmacEx(HSM_CmdType *pCmd, const HSMCom_CMacExType *pCfg) +{ + uint32_t u32CtrBits = (pCfg->tCfg.eBackend & 0x1) | ((pCfg->tCfg.eInputFmt & 0x1) << 1) | ((pCfg->tCfg.eOutputFmt & 0x1) << 2); + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_CMAC_GEN << 16) | u32CtrBits, (uint32_t)pCfg); +} + +HSM_StatusType HSM_XMac(HSM_CmdType *pCmd, const HSMCom_XMacType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_XMAC_GEN << 16), (uint32_t)pCfg); +} + +HSM_StatusType HSM_XMacEx(HSM_CmdType *pCmd, const HSMCom_XMacExType *pCfg) +{ + uint32_t u32CtrBits = (pCfg->tCfg.eBackend & 0x1) | ((pCfg->tCfg.eInputFmt & 0x1) << 1) | ((pCfg->tCfg.eOutputFmt & 0x1) << 2); + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_XMAC_GEN << 16) | u32CtrBits, (uint32_t)pCfg); +} + +HSM_StatusType HSM_CcmEncry(HSM_CmdType *pCmd, const HSMCom_CcmEncryptType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_CCM_ENCRY << 16), (uint32_t)pCfg); +} + +HSM_StatusType HSM_CcmEncryEx(HSM_CmdType *pCmd, const HSMCom_CcmEncryptExType *pCfg) +{ + uint32_t u32CtrBits = (pCfg->tCfg.eBackend & 0x1); + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_CCM_ENCRY << 16) | u32CtrBits, (uint32_t)pCfg); +} + +HSM_StatusType HSM_CcmDecry(HSM_CmdType *pCmd, const HSMCom_CcmDecryptType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_CCM_DECRY << 16), (uint32_t)pCfg); +} + +HSM_StatusType HSM_CcmDecryEx(HSM_CmdType *pCmd, const HSMCom_CcmDecryptExType *pCfg) +{ + uint32_t u32CtrBits = (pCfg->tCfg.eBackend & 0x1); + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_CCM_DECRY << 16) | u32CtrBits, (uint32_t)pCfg); +} + +HSM_StatusType HSM_GcmEncry(HSM_CmdType *pCmd, const HSMCom_GcmEncryptType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_GCM_ENCRY << 16), (uint32_t)pCfg); +} + +HSM_StatusType HSM_GcmEncryEx(HSM_CmdType *pCmd, const HSMCom_GcmEncryptExType *pCfg) +{ + uint32_t u32CtrBits = (pCfg->tCfg.eBackend & 0x1); + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_GCM_ENCRY << 16) | u32CtrBits, (uint32_t)pCfg); +} + +HSM_StatusType HSM_GcmDecry(HSM_CmdType *pCmd, const HSMCom_GcmDecryptType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_GCM_DECRY << 16), (uint32_t)pCfg); +} + +HSM_StatusType HSM_GcmDecryEx(HSM_CmdType *pCmd, const HSMCom_GcmDecryptExType *pCfg) +{ + uint32_t u32CtrBits = (pCfg->tCfg.eBackend & 0x1); + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_GCM_DECRY << 16) | u32CtrBits, (uint32_t)pCfg); +} + +HSM_StatusType HSM_Md5(HSM_CmdType *pCmd, const HSMCom_Md5Type *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_MD5 << 16), (uint32_t)pCfg); +} + +HSM_StatusType HSM_Md5Ex(HSM_CmdType *pCmd, const HSMCom_Md5Type *pCfg) +{ + uint32_t u32CtrBits = (pCfg->tCfg.eIntputFmt & 0x1) | ((pCfg->tCfg.eOutputFmt & 0x1) << 1); + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_MD5 << 16) | u32CtrBits, (uint32_t)pCfg); +} + +HSM_StatusType HSM_Sm3(HSM_CmdType *pCmd, const HSMCom_Sm3Type *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SM3 << 16), (uint32_t)pCfg); +} + +HSM_StatusType HSM_Sm3Ex(HSM_CmdType *pCmd, const HSMCom_Sm3Type *pCfg) +{ + uint32_t u32CtrBits = (pCfg->tCfg.eIntputFmt & 0x1) | ((pCfg->tCfg.eOutputFmt & 0x1) << 1); + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_SM3 << 16) | u32CtrBits, (uint32_t)pCfg); +} + +HSM_StatusType HSM_MonotonicCounterIncrease(HSM_CmdType *pCmd, const HSMCom_MonCountType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_MONOTONIC_COUNTER << 16) | HSMCOM_INCREASE_COUNTER, (uint32_t)pCfg); +} + +HSM_StatusType HSM_MonotonicCounterRead(HSM_CmdType *pCmd, const HSMCom_MonCountType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_MONOTONIC_COUNTER << 16) | HSMCOM_READ_COUNTER, (uint32_t)pCfg); +} + +HSM_StatusType HSM_MonotonicCounterSetValue(HSM_CmdType *pCmd, const HSMCom_MonCountType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_MONOTONIC_COUNTER << 16) | HSMCOM_SET_COUNTER_VAL, (uint32_t)pCfg); +} + +HSM_StatusType HSM_MonotonicIncCountWhenEqu(HSM_CmdType *pCmd, const HSMCom_MonCountType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_MONOTONIC_COUNTER << 16) | HSMCOM_INCREASE_COUNTER_WHEN_EQUAL, (uint32_t)pCfg); +} + +HSM_StatusType HSM_MonotonicReadAllFlexCounters(HSM_CmdType *pCmd, const HSMCom_MonCountType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_MONOTONIC_COUNTER << 16) | HSMCOM_READ_ALL_FLEX_COUNTERS, (uint32_t)pCfg); +} + +HSM_StatusType HSM_MonotonicCounterSetSingleCfg(HSM_CmdType *pCmd, const HSMCom_MonCountType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_MONOTONIC_COUNTER << 16) | HSMCOM_SET_SINGLE_CFG, (uint32_t)pCfg); +} + +HSM_StatusType HSM_MonotonicCounterGetSingleCfg(HSM_CmdType *pCmd, const HSMCom_MonCountType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_MONOTONIC_COUNTER << 16) | HSMCOM_GET_SINGLE_CFG, (uint32_t)pCfg); +} + +HSM_StatusType HSM_MonotonicIncreaseCounter2(HSM_CmdType *pCmd, const HSMCom_MonCountType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_MONOTONIC_COUNTER << 16) | HSMCOM_INCREASE_COUNTER2, (uint32_t)pCfg); +} + +HSM_StatusType HSM_MonotonicReadCounter2(HSM_CmdType *pCmd, const HSMCom_MonCountType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_MONOTONIC_COUNTER << 16) | HSMCOM_READ_COUNTER2, (uint32_t)pCfg); +} + +HSM_StatusType HSM_Rsa(HSM_CmdType *pCmd, const HSMCom_RsaType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_RSA << 16), (uint32_t)pCfg); +} + +HSM_StatusType HSM_RSA_SSA_PSS_Sign(HSM_CmdType *pCmd, const HSMCom_RsaSsaPssSignType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_RSA_SSA_PSS_SIGN << 16), (uint32_t)pCfg); +} +HSM_StatusType HSM_RSA_SSA_PSS_Verify(HSM_CmdType *pCmd, const HSMCom_RsaSsaPssVerifyType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_RSA_SSA_PSS_VERIFY << 16), (uint32_t)pCfg); +} + +HSM_StatusType HSM_RSA_SSA_ES_PKCS1V15_Encrypt(HSM_CmdType *pCmd, const HSMCom_RsaEsPkcs1V15EncryptType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_RSA_ES_PKCS1V15_ENCRYPT << 16), (uint32_t)pCfg); +} +HSM_StatusType HSM_RSA_SSA_ES_PKCS1V15_Decrypt(HSM_CmdType *pCmd, const HSMCom_RsaEsPkcs1V15DecryptType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_RSA_ES_PKCS1V15_DECRYPT << 16), (uint32_t)pCfg); +} +HSM_StatusType HSM_RSA_SSA_ES_PKCS1V15_Verify(HSM_CmdType *pCmd, const HSMCom_RsaSsaPkcs1V15VerifyType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_RSA_SSA_PKCS1V15_VERIFY << 16), (uint32_t)pCfg); +} +HSM_StatusType HSM_RSA_SSA_ES_PKCS1V15_Sign(HSM_CmdType *pCmd, const HSMCom_RsaSsaPkcs1V15SignType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_RSA_SSA_PKCS1V15_SIGN << 16), (uint32_t)pCfg); +} + +HSM_StatusType HSM_RSA_SSA_ES_OAEP_Encrypt(HSM_CmdType *pCmd, const HSMCom_RsaEsOaepEncryptType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_RSA_ES_OAEP_ENCRYPT << 16), (uint32_t)pCfg); +} +HSM_StatusType HSM_RSA_SSA_ES_OAEP_Decrypt(HSM_CmdType *pCmd, const HSMCom_RsaEsOaepDecryptType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_RSA_ES_OAEP_DECRYPT << 16), (uint32_t)pCfg); +} + +HSM_StatusType HSM_BigNumberCalc(HSM_CmdType *pCmd, const HSMCom_BigNumberCalcType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_RSA << 16) | 1u, (uint32_t)pCfg); +} + +HSM_StatusType HSM_LoadFirmware(HSM_CmdType *pCmd) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_LOAD_FIRMWARE << 16), (uint32_t)0); +} + +HSM_StatusType HSM_SMDH(HSM_CmdType *pCmd, HSMCom_SmDHType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_DH_SM << 16), (uint32_t)pCfg); +} + +HSM_StatusType HSM_ECDH(HSM_CmdType *pCmd, HSMCom_ECDHType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_ECDH << 16), (uint32_t)pCfg); +} + +HSM_StatusType HSM_DH(HSM_CmdType *pCmd, HSMCom_RsaDHType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_DH << 16), (uint32_t)pCfg); +} + +HSM_StatusType HSM_PBKDF2(HSM_CmdType *pCmd, HSMCom_Pbkdf2Type *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_DH_PBKDF2 << 16), (uint32_t)pCfg); +} + +HSM_StatusType HSM_GMPBKDF(HSM_CmdType *pCmd, HSMCom_GMpbkdfType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_DH_GMPBKDF << 16), (uint32_t)pCfg); +} + +HSM_StatusType HSM_RevokeUmrk0(HSM_CmdType *pCmd) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_REVOKE_UMRK << 16)|HSMCOM_REVOK_UMRK0, (uint32_t)0); +} + +HSM_StatusType HSM_RevokeUmrk1(HSM_CmdType *pCmd) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_REVOKE_UMRK << 16)|HSMCOM_REVOK_UMRK1, (uint32_t)0); +} + +HSM_StatusType HSM_RevokeUmrk2(HSM_CmdType *pCmd) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_REVOKE_UMRK << 16)|HSMCOM_REVOK_UMRK2, (uint32_t)0); +} + +HSM_StatusType HSM_RevokeUmrk3(HSM_CmdType *pCmd) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_REVOKE_UMRK << 16)|HSMCOM_REVOK_UMRK3, (uint32_t)0); +} + +HSM_StatusType HSM_GenUsrk(HSM_CmdType *pCmd,const HSMCom_RsaType *pCfg) +{ + return hsm_assign_val(pCmd,(uint32_t)(HSM_CMD_ID_USRK_GEN << 16), (uint32_t)pCfg); +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_intm.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_intm.c new file mode 100644 index 0000000..5e12985 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_intm.c @@ -0,0 +1,190 @@ +/** + * @file fc7xxx_driver_intm.c + * @author Flagchip + * @brief FC7240 INTM driver type definition and API + * @version 0.1.0 + * @date 2024-01-10 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-10 Flagchip084 N/A FC7240 release version + ******************************************************************************** */ + +#include "fc7xxx_driver_intm.h" +#include "interrupt_manager.h" + +/* ################################################################################## */ +/* ##################################### Macros ##################################### */ + +/* ################################################################################## */ +/* ################################# Local Variables ################################ */ + +static INTM_Type *const s_aIntm_Base[INTM_INSTANCE_MAX] = INTM_BASE_PTRS; +static INTM_ISRCallbackType s_aIntmISRCallback[INTM_INSTANCE_MAX][INTM_IRQ_MONITOR_MAX] = {NULL}; +/* ################################################################################## */ +/* ########################### Local Functions Prototype ############################ */ +void INTM0_IRQHandler(void); +void INTMn_IRQHandler(INTM_InstanceType eInstance); + +/* ################################################################################## */ +/* ################################# Local Functions ############################### */ + +/* ################################################################################## */ +/* ################################# Global Functions ############################### */ + +INTM_ReturnType INTM_Init(INTM_InstanceType eInstance, INTM_IrqMonitorType eIrqMonitorIndex, INTM_InitType *pInitCfg) +{ + INTM_MonitorType *pMonitor; + + if ((NULL == pInitCfg) || (eInstance >= INTM_INSTANCE_MAX) || (eIrqMonitorIndex >= INTM_IRQ_MONITOR_MAX)) + { + return INTM_RETURN_E_PARAM; + } + + if (pInitCfg->u32SrcDelayCnt >= 0xFFFFFFU) + { + return INTM_RETURN_E_PARAM; + } + + if (pInitCfg->u16IrqNumber >= IRQn_MAX) + { + return INTM_RETURN_E_PARAM; + } + + pMonitor = INTM_HWA_GetIrqMonitor(s_aIntm_Base[eInstance], (uint8_t)eIrqMonitorIndex); + INTM_HWA_SetIRQReqNum(pMonitor, pInitCfg->u16IrqNumber); + INTM_HWA_EnableReset(pMonitor, pInitCfg->bEnReset); + INTM_HWA_EnableInterrupt(pMonitor, pInitCfg->bEnInterrupt); + INTM_HWA_SetLatency(pMonitor, pInitCfg->u32SrcDelayCnt); + if (pInitCfg->eMode == INTM_INTERRUPT_MODE_INACTIVE) + { + INTM_HWA_EnableInactiveMode(pMonitor, true); + } + else + { + INTM_HWA_EnableInactiveMode(pMonitor, false); + } + s_aIntmISRCallback[eInstance][eIrqMonitorIndex] = pInitCfg->pIntmIsrCallback; + return INTM_RETURN_OK; +} + +INTM_ReturnType INTM_enable(INTM_InstanceType eInstance, bool bEnable) +{ + if (eInstance >= INTM_INSTANCE_MAX) + { + return INTM_RETURN_E_PARAM; + } + + INTM_HWA_Enable(s_aIntm_Base[eInstance], bEnable); + + return INTM_RETURN_OK; +} + +INTM_ReturnType INTM_StartInactiveMode(INTM_InstanceType eInstance, INTM_IrqMonitorType eIrqMonitorIndex) +{ + INTM_MonitorType *pMonitor; + + if ((eInstance >= INTM_INSTANCE_MAX) || (eIrqMonitorIndex >= INTM_IRQ_MONITOR_MAX)) + { + return INTM_RETURN_E_PARAM; + } + + pMonitor = INTM_HWA_GetIrqMonitor(s_aIntm_Base[eInstance], (uint8_t)eIrqMonitorIndex); + INTM_HWA_StartInactiveMode(pMonitor); + return INTM_RETURN_OK; +} + +INTM_ReturnType INTM_StopInactiveMode(INTM_InstanceType eInstance, INTM_IrqMonitorType eIrqMonitorIndex) +{ + INTM_MonitorType *pMonitor; + + if ((eInstance >= INTM_INSTANCE_MAX) || (eIrqMonitorIndex >= INTM_IRQ_MONITOR_MAX)) + { + return INTM_RETURN_E_PARAM; + } + + pMonitor = INTM_HWA_GetIrqMonitor(s_aIntm_Base[eInstance], (uint8_t)eIrqMonitorIndex); + INTM_HWA_StopInactiveMode(pMonitor); + return INTM_RETURN_OK; +} + +INTM_ReturnType INTM_SetAcknowledge(INTM_InstanceType eInstance, uint16_t u16IrqNumber) +{ + if (eInstance >= INTM_INSTANCE_MAX) + { + return INTM_RETURN_E_PARAM; + } + + INTM_HWA_SetIACKR(s_aIntm_Base[eInstance], u16IrqNumber); + + return INTM_RETURN_OK; +} + +uint32_t INTM_GetCounterValue(INTM_InstanceType eInstance, INTM_IrqMonitorType eIrqMonitorIndex) +{ + INTM_MonitorType *pMonitor; + + if ((eInstance >= INTM_INSTANCE_MAX) || (eIrqMonitorIndex >= INTM_IRQ_MONITOR_MAX)) + { + return 0; + } + + pMonitor = INTM_HWA_GetIrqMonitor(s_aIntm_Base[eInstance], (uint8_t)eIrqMonitorIndex); + return INTM_HWA_GetTimerCounter(pMonitor); +} + +INTM_ReturnType INTM_ClearIntFlag(INTM_InstanceType eInstance, INTM_IrqMonitorType eIrqMonitorIndex) +{ + INTM_MonitorType *pMonitor; + + if ((eInstance >= INTM_INSTANCE_MAX) || (eIrqMonitorIndex >= INTM_IRQ_MONITOR_MAX)) + { + return INTM_RETURN_E_PARAM; + } + + pMonitor = INTM_HWA_GetIrqMonitor(s_aIntm_Base[eInstance], (uint8_t)eIrqMonitorIndex); + INTM_HWA_SetTimerCounter(pMonitor, 0U); + return INTM_RETURN_OK; +} + +bool INTM_GetTimeoutStatus(INTM_InstanceType eInstance, INTM_IrqMonitorType eIrqMonitorIndex) +{ + INTM_MonitorType *pMonitor; + + if ((eInstance >= INTM_INSTANCE_MAX) || (eIrqMonitorIndex >= INTM_IRQ_MONITOR_MAX)) + { + return false; + } + + pMonitor = INTM_HWA_GetIrqMonitor(s_aIntm_Base[eInstance], (uint8_t)eIrqMonitorIndex); + return INTM_HWA_ReadStatus(pMonitor); +} + +void INTMn_IRQHandler(INTM_InstanceType eInstance) +{ + uint8_t u8i; + INTM_MonitorType *pMonitor; + + for (u8i = 0; u8i < (uint8_t)INTM_IRQ_MONITOR_MAX; u8i++) + { + pMonitor = INTM_HWA_GetIrqMonitor(s_aIntm_Base[eInstance], u8i); + if (INTM_HWA_ReadStatus(pMonitor)) + { + if (s_aIntmISRCallback[eInstance][u8i] != NULL) + { + s_aIntmISRCallback[eInstance][u8i](); + } + } + } +} + +void INTM0_IRQHandler(void) +{ + INTMn_IRQHandler(INTM_INSTANCE_0); +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_ism.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_ism.c new file mode 100644 index 0000000..08df27d --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_ism.c @@ -0,0 +1,347 @@ +/** + * @file fc7xxx_driver_ism.c + * @author Flagchip + * @brief FC7xxx ISM driver type definition and API + * @version 0.1.0 + * @date 2023-02-13 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-1-10 Flagchip095 N/A First version for FC7240 + ******************************************************************************** */ +#include "fc7xxx_driver_ism.h" + +/* ################################################################################## */ +/* ####################################### Macro #################################### */ +#define FPC_INSTANCE_COUNT (16U) +#define LAM_INSTANCE_COUNT (16U) +#define ECM_INSTANCE_COUNT (4U) +/* ################################################################################## */ +/* ################################### Type define ################################## */ + +/* ################################################################################## */ +/* ################################ Local Variables ################################# */ +static ISM_Type *const s_apIsmBase[ISM_INSTANCE_COUNT] = ISM_BASE_PTRS; +static ISM_EventISRCallbackType s_apEventISRCallback = NULL; +static FPC_ISRCallbackType s_apFpcISRCallback[FPC_INSTANCE_COUNT] = {NULL}; +static LAM_ISRCallbackType s_apLamOverFlowIsrCallback[LAM_INSTANCE_COUNT] = {NULL}; +/* ################################################################################## */ +/* ########################### Local Prototype Functions ############################ */ + +/* ################################################################################## */ +/* ######################### Global prototype Functions ############################ */ +void ISM0_IRQHandler(void); +/* ################################################################################## */ +/* ################################ Local Functions ################################ */ + +/* ################################################################################## */ +/* ################################ Global Functions ################################ */ + +void ISM_Init(const ISM_InitCfgType *pInitConfig) +{ + ISM_Type *pIsm = ISM; + + DEV_ASSERT(ISM_HWA_PARAM_ECMC(pIsm) == ECM_INSTANCE_COUNT); + DEV_ASSERT(ISM_HWA_PARAM_FPC(pIsm) == FPC_INSTANCE_COUNT); + DEV_ASSERT(ISM_HWA_PARAM_LAM(pIsm) == LAM_INSTANCE_COUNT); + DEV_ASSERT(pInitConfig != NULL); + + s_apEventISRCallback = pInitConfig->pEventIsrCallback; + ISM_HWA_InterruptEnable(pIsm, pInitConfig->bIntEnable); +} + +uint8_t ISM_GetEcmEventHappenedChannels(void) +{ + ISM_Type *pIsm = ISM; + + return (uint8_t)ISM_HWA_GetEcs(pIsm); +} + +uint16_t ISM_GetLamEventHappenedChannels(void) +{ + ISM_Type *pIsm = ISM; + + return ISM_HWA_GetEs(pIsm); +} + +void ISM_ClearEcmEventHappenedChannels(uint8_t u8Channels) +{ + ISM_Type *pIsm = ISM; + + ISM_HWA_ClearEcs(pIsm, (uint32_t)u8Channels); +} + +void ISM_ClearLamEventHappenedChannels(uint16_t u16Channels) +{ + ISM_Type *pIsm = ISM; + + ISM_HWA_ClearEs(pIsm, (uint32_t)u16Channels); +} + +void ISM_EnableEcmSystemEvent(uint32_t u32Channels, bool bEnable) +{ + ISM_Type *pIsm = ISM; + + ISM_HWA_EnableEcmSystemEvent(pIsm, u32Channels, bEnable); +} + +void ISM_EnableLamSystemEvent(uint32_t u32Channels, bool bEnable) +{ + ISM_Type *pIsm = ISM; + + ISM_HWA_EnableLamSystemEvent(pIsm, u32Channels, bEnable); +} + +void ISM_EcmEventConfig(uint8_t u8LamIndex, uint8_t u8EcmIndex, uint8_t u8EventCount) +{ + ISM_Type *pIsm = ISM; + + DEV_ASSERT(u8LamIndex < LAM_INSTANCE_COUNT); + DEV_ASSERT(u8EcmIndex < ECM_INSTANCE_COUNT); + if (u8EcmIndex == 0U) + { + ISM_HWA_SetEcm0EcCtrl(pIsm, u8EventCount, u8LamIndex); + } + else if (u8EcmIndex == 1U) + { + ISM_HWA_SetEcm1EcCtrl(pIsm, u8EventCount, u8LamIndex); + } + else if (u8EcmIndex == 2U) + { + ISM_HWA_SetEcm2EcCtrl(pIsm, u8EventCount, u8LamIndex); + } + else if (u8EcmIndex == 3U) + { + ISM_HWA_SetEcm3EcCtrl(pIsm, u8EventCount, u8LamIndex); + } + else + { + + } +} + +void ISM_ClearLamStatusCounter(uint8_t u8LamIndex) +{ + LAM_Type *pLam; + + DEV_ASSERT(u8LamIndex < LAM_INSTANCE_COUNT); + + pLam = ISM_HWA_GetLam(ISM, u8LamIndex); + + ISM_HWA_ClearLamStatusCounter(pLam); +} + +uint32_t ISM_GetLamStatusCounter(uint8_t u8LamIndex) +{ + LAM_Type *pLam; + + DEV_ASSERT(u8LamIndex < LAM_INSTANCE_COUNT); + + pLam = ISM_HWA_GetLam(ISM, u8LamIndex); + + return ISM_HWA_GetLamStatusCounter(pLam); +} + +void ISM_ClearLamStatusOvfl(uint8_t u8LamIndex) +{ + LAM_Type *pLam; + + DEV_ASSERT(u8LamIndex < LAM_INSTANCE_COUNT); + + pLam = ISM_HWA_GetLam(ISM, u8LamIndex); + + ISM_HWA_ClearLamStatusOvfl(pLam); +} + +bool ISM_GetLamStatusOvfl(uint8_t u8LamIndex) +{ + LAM_Type *pLam; + + DEV_ASSERT(u8LamIndex < LAM_INSTANCE_COUNT); + + pLam = ISM_HWA_GetLam(ISM, u8LamIndex); + + return ISM_HWA_GetLamStatusOvfl(pLam); +} + +void ISM_Enable(bool bEnable) +{ + ISM_Type *pIsm = ISM; + + ISM_HWA_Enable(pIsm, bEnable); +} + +void ISM_InterruptEnable(bool bEnable) +{ + ISM_Type *pIsm = ISM; + + ISM_HWA_InterruptEnable(pIsm, bEnable); +} + +void ISM_LamOverflowInterruptEnable(uint8_t u8LamIndex, bool bEnable) +{ + LAM_Type *pLam; + + DEV_ASSERT(u8LamIndex < LAM_INSTANCE_COUNT); + + pLam = ISM_HWA_GetLam(ISM, u8LamIndex); + + ISM_HWA_SetLamCtrIen(pLam, bEnable); +} + +void ISM_LamEnable(uint8_t u8LamIndex, bool bEnable) +{ + LAM_Type *pLam; + + DEV_ASSERT(u8LamIndex < LAM_INSTANCE_COUNT); + + pLam = ISM_HWA_GetLam(ISM, u8LamIndex); + + ISM_HWA_SetLamCtrEn(pLam, bEnable); +} + +void ISM_LamConfig(uint8_t u8LamIndex, const ISM_LamCfgType *pConfig) +{ + uint32_t u32TempValue = 0; + LAM_Type *pLam; + + DEV_ASSERT(u8LamIndex < LAM_INSTANCE_COUNT); + DEV_ASSERT(pConfig != NULL); + + pLam = ISM_HWA_GetLam(ISM, u8LamIndex); + + ISM_HWA_SetLamCtrIen(pLam, pConfig->bOvflIntEnable); + ISM_HWA_SetLamCounter(pLam, pConfig->u32EvtCntThreshold); + + u32TempValue |= ISM_LAM_CONFIG_RCS(pConfig->u8SrcSel); + u32TempValue |= ISM_LAM_CONFIG_MCS(pConfig->u8MonSel); + u32TempValue |= ISM_LAM_CONFIG_IVW(pConfig->eInvWin); + u32TempValue |= ISM_LAM_CONFIG_EDS(pConfig->eWinEdgSel); + u32TempValue |= ISM_LAM_CONFIG_EWS(pConfig->eEvtWinSel); + u32TempValue |= ISM_LAM_CONFIG_RMS(pConfig->eRunMode); + u32TempValue |= ISM_LAM_CONFIG_MOS(pConfig->eMonSrcSel); + u32TempValue |= ISM_LAM_CONFIG_IVM(pConfig->eInvMon); + u32TempValue |= ISM_LAM_CONFIG_IVR(pConfig->eInvRef); + + s_apLamOverFlowIsrCallback[u8LamIndex] = pConfig->pLamOverFlowIsrCallback; + + ISM_HWA_SetLamConfig(pLam, u32TempValue); +} + +void ISM_FpcGlitchInterruptEnable(uint8_t u8FpcIndex, bool bEnable) +{ + FPC_Type *pFpc; + + DEV_ASSERT(u8FpcIndex < FPC_INSTANCE_COUNT); + + pFpc = ISM_HWA_GetFpc(ISM, u8FpcIndex); + + ISM_HWA_SetFpcCtrlIen(pFpc, bEnable); +} + +void ISM_FpcEnable(uint8_t u8FpcIndex, bool bEnable) +{ + FPC_Type *pFpc; + + DEV_ASSERT(u8FpcIndex < FPC_INSTANCE_COUNT); + + pFpc = ISM_HWA_GetFpc(ISM, u8FpcIndex); + + ISM_HWA_SetFpcCtrlEn(pFpc, bEnable); +} + +void ISM_FpcConfig(uint8_t u8FpcIndex, const ISM_FpcCfgType *pConfig) +{ + uint32_t u32TempValue = 0; + FPC_Type *pFpc; + + DEV_ASSERT(u8FpcIndex < FPC_INSTANCE_COUNT); + DEV_ASSERT(pConfig != NULL); + + pFpc = ISM_HWA_GetFpc(ISM, u8FpcIndex); + + ISM_HWA_SetFpcCtrlIen(pFpc, pConfig->bGlitchIntEnable); + + u32TempValue |= ISM_FPC_CONFIG_FED(pConfig->eFallingDelayNode); + u32TempValue |= ISM_FPC_CONFIG_FEG(pConfig->eFallingDetectMode); + u32TempValue |= ISM_FPC_CONFIG_RED(pConfig->eRisingDelayNode); + u32TempValue |= ISM_FPC_CONFIG_REG(pConfig->eRisingDetectMode); + u32TempValue |= ISM_FPC_CONFIG_CMP(pConfig->u32ThresholdValue); + + s_apFpcISRCallback[u8FpcIndex] = pConfig->pFpcIsrCallback; + + ISM_HWA_SetFpcConfig(pFpc, u32TempValue); +} + +void ISM0_IRQHandler(void) +{ + uint8_t u8i; + FPC_Type *pFpc; + LAM_Type *pLam; + uint8_t u8EcmFlags; + uint16_t u16LamFlags; + ISM_Type *pIsm = s_apIsmBase[ISM_INSTANCE_0]; + + u8EcmFlags = ISM_HWA_GetEcs(pIsm)&ISM_HWA_GetEnabledEcmSystemEvent(pIsm); + u16LamFlags = ISM_HWA_GetEs(pIsm)&ISM_HWA_GetEnabledLamSystemEvent(pIsm); + + if (s_apEventISRCallback != NULL) + { + s_apEventISRCallback(u16LamFlags, u8EcmFlags); + } + + ISM_HWA_ClearEcs(pIsm, u8EcmFlags); + ISM_HWA_ClearEs(pIsm, u16LamFlags); + + for (u8i = 0; u8i < FPC_INSTANCE_COUNT; u8i++) + { + pFpc = ISM_HWA_GetFpc(s_apIsmBase[ISM_INSTANCE_0], u8i); + if (ISM_HWA_GetFpcCtrlIen(pFpc)) + { + uint32_t u32Status = 0U; + if (ISM_HWA_GetFpcRgd(pFpc)) + { + u32Status |= (uint32_t)FPC_RISING_GLITCH_DETECTED; + } + if (ISM_HWA_GetFpcFgd(pFpc)) + { + u32Status |= (uint32_t)FPC_FALLING_GLITCH_DETECTED; + } + if (s_apFpcISRCallback[u8i] != NULL) + { + s_apFpcISRCallback[u8i](u32Status); + } + if ((u32Status & (uint32_t)FPC_RISING_GLITCH_DETECTED) == (uint32_t)FPC_RISING_GLITCH_DETECTED) + { + ISM_HWA_ClearFpcRgd(pFpc); + } + if ((u32Status & (uint32_t)FPC_FALLING_GLITCH_DETECTED) == (uint32_t)FPC_FALLING_GLITCH_DETECTED) + { + ISM_HWA_ClearFpcFgd(pFpc); + } + } + } + + for (u8i = 0; u8i < LAM_INSTANCE_COUNT; u8i++) + { + pLam = ISM_HWA_GetLam(s_apIsmBase[ISM_INSTANCE_0], u8i); + if (ISM_HWA_GetLamCtrIen(pLam)) + { + if (ISM_HWA_GetLamStatusOvfl(pLam)) + { + if (s_apLamOverFlowIsrCallback[u8i] != NULL) + { + s_apLamOverFlowIsrCallback[u8i](); + } + } + ISM_HWA_ClearLamStatusOvfl(pLam); + } + } + +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_lin.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_lin.c new file mode 100644 index 0000000..aa9fe8c --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_lin.c @@ -0,0 +1,1505 @@ +/** + * @file fc7xxx_driver_lin.c + * @author Flagchip + * @brief FC7xxx LIN driver type definition and API + * @version 0.1.0 + * @date 2024-01-14 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-14 Flagchip0122 N/A FC7xxx internal release version + ******************************************************************************** */ + +#include "fc7xxx_driver_lin.h" +#include "device_header.h" +#include "fc7xxx_driver_fcuart.h" + +/* ################################################################################## */ +/* ####################################### Macro #################################### */ + +/** UART Instance Number */ +#define LIN_INSTANCE_NUM FCUART_INSTANCE_COUNT + +/* ################################################################################## */ +/* ################################### type define ################################## */ + +/* ################################################################################## */ +/* ################################ Local Variables ################################# */ + +static uint8_t s_aInstanceUsed[LIN_INSTANCE_NUM] = {0}; +static lin_config_t *s_aLinConfig[LIN_INSTANCE_NUM] = {0}; +static lin_xfer_state_t *s_aLinXfer[LIN_INSTANCE_NUM] = {0}; + +/* UART instance array */ +static FCUART_Type *const s_aFCUART_InstanceTable[FCUART_INSTANCE_COUNT] = FCUART_BASE_PTRS; + +/* ################################################################################## */ +/* ########################### Local Prototype Functions ############################ */ +static LIN_StatusType LIN_DrvCalBaudrate(uint8_t u8LinIndex, uint32_t *u32OverSamp, + uint32_t *u32Sbr); +static LIN_NodeType LIN_DrvCheckMode(uint8_t u8LinIndex); +LOCAL_INLINE uint8_t BIT(uint8_t A, uint8_t B); +static uint8_t LIN_DrvParityMake(uint8_t PID); +static uint8_t LIN_DrvParityCheck(uint8_t PID); +static void LIN_DrvHeaderHandle(uint8_t u8LinIndex, uint8_t u8ReceiveByte); +static uint8_t LIN_DrvMakeCheckSum(uint8_t u8LinIndex, uint8_t *pBuf, uint8_t u8Size, + uint8_t u8Pid); +static void LIN_DrvReceiveFrameData(uint8_t u8LinIndex, uint8_t u8ReceiveByte); +static void LIN_DrvSendFrameData(uint8_t u8LinIndex, uint8_t u8ReceiveByte); +static void LIN_DrvFrameHandle(uint8_t u8LinIndex); +static void LIN_DrvWakeupHandle(uint8_t u8LinIndex); + +/* ################################################################################## */ +/* ########################### Global Prototype Functions ########################### */ + +/* ################################################################################## */ +/* ################################ Local Functions ################################# */ + +/** + * @brief LIN instance generate baudrate value, include oversample value and sbr value. + */ +static LIN_StatusType LIN_DrvCalBaudrate(uint8_t u8LinIndex, uint32_t *u32OverSamp, + uint32_t *u32Sbr) +{ + LIN_StatusType tRetVal = LIN_STATUS_ERROR; + uint32_t u32SbrTemp; + uint32_t u32OverSampTemp; + uint32_t u32TempSmbDiff; + uint32_t u32SmbDiff; + uint32_t u32CalcSmb; + uint32_t u32OverSamp1; + uint32_t u32Sbr1; + uint32_t u32Smb; + + u32OverSamp1 = 4U; /* 4..32 */ + u32Smb = s_aLinConfig[u8LinIndex]->clockSrcFreq / s_aLinConfig[u8LinIndex]->baudRate; + + /* sbr = srcFreq/baudrate/oversamp */ + u32Sbr1 = (uint16_t)(u32Smb / (u32OverSamp1)); + u32CalcSmb = (u32OverSamp1) * (u32Sbr1); + + if (u32CalcSmb > u32Smb) + { + u32SmbDiff = u32CalcSmb - u32Smb; + } + else + { + u32SmbDiff = u32Smb - u32CalcSmb; + } + + if (u32SmbDiff != 0U) + { + + /* loop to find the best u32OverSamp1 value possible, one that generates minimum u32SmbDiff + * iterate through the rest of the supported values of u32OverSamp */ + for (u32OverSampTemp = 5U; u32OverSampTemp <= 32U; u32OverSampTemp++) + { + /* calculate the temporary u32Sbr value */ + u32SbrTemp = (uint32_t)(u32Smb / u32OverSampTemp); + /* calculate the baud rate based on the temporary u32OverSamp and u32Sbr values */ + u32CalcSmb = (uint32_t)(u32OverSampTemp * u32SbrTemp); + + if (u32CalcSmb > u32Smb) + { + u32TempSmbDiff = u32CalcSmb - u32Smb; + } + else + { + u32TempSmbDiff = u32Smb - u32CalcSmb; + } + + if (u32TempSmbDiff < u32SmbDiff) + { + u32SmbDiff = u32TempSmbDiff; + u32OverSamp1 = u32OverSampTemp; /* update and store the best u32OverSamp value calculated */ + u32Sbr1 = u32SbrTemp; /* update store the best u32Sbr value calculated */ + } + + /* when differ is 0U, break */ + if (u32SmbDiff == 0U) + { + break; + } + } + } + + /* check differ */ + if (u32SmbDiff == 0U) + { + tRetVal = LIN_STATUS_SUCCESS; + + /* out the calculated value */ + *u32Sbr = u32Sbr1; + *u32OverSamp = u32OverSamp1; + } + else + { + tRetVal = LIN_STATUS_ERROR; + } + + return tRetVal; +} + +/** + * @brief Check the node mode, slave or master. + */ +static LIN_NodeType LIN_DrvCheckMode(uint8_t u8LinIndex) { return s_aLinConfig[u8LinIndex]->nodeMode; } + +/** + * @brief Bit function. + */ +LOCAL_INLINE uint8_t BIT(uint8_t A, uint8_t B) { return (uint8_t)((A >> B) & 0x01U); } + +/** + * @brief Make parity value. + */ +static uint8_t LIN_DrvParityMake(uint8_t PID) +{ + uint8_t parity; + uint8_t retVal; + + parity = (uint8_t)((((0xFFU & BIT(PID, 0U)) ^ (0xFFU & BIT(PID, 1U)) ^ (0xFFU & BIT(PID, 2U)) ^ (0xFFU & BIT(PID, 4U))) << 6U) | + ((0xFFU ^ (BIT(PID, 1U)) ^ (0xFFU & BIT(PID, 3U)) ^ (0xFFU & BIT(PID, 4U)) ^ (0xFFU & BIT(PID, 5U))) << 7U)); + + /* Making parity bits */ + retVal = (uint8_t)(PID | parity); + + return retVal; +} + +/** + * @brief Check parity value. + */ +static uint8_t LIN_DrvParityCheck(uint8_t PID) +{ + uint8_t parity; + uint8_t retVal; + + parity = (uint8_t)((((0xFFU & BIT(PID, 0U)) ^ (0xFFU & BIT(PID, 1U)) ^ (0xFFU & BIT(PID, 2U)) ^ (0xFFU & BIT(PID, 4U))) << 6U) | + ((0xFFU ^ (BIT(PID, 1U)) ^ (0xFFU & BIT(PID, 3U)) ^ (0xFFU & BIT(PID, 4U)) ^ (0xFFU & BIT(PID, 5U))) << 7U)); + + /* If parity bits are incorrect */ + if ((PID & 0xC0U) != parity) + { + retVal = 0xFFU; + } + else + { + retVal = (uint8_t)(PID & 0x3FU); + } + + return retVal; +} + +/** + * @brief Handle the frame header step by step, break field, sync field and PID field. + */ +static void LIN_DrvHeaderHandle(uint8_t u8LinIndex, uint8_t u8ReceiveByte) +{ + FCUART_Type *base = s_aFCUART_InstanceTable[u8LinIndex]; + lin_xfer_state_t *xferState = s_aLinXfer[u8LinIndex]; + + /* Step 1: Handle the break field state. */ + if (FCUART_HWA_GetStatus(base, FCUART_STAT_LBKDIF)) + { + FCUART_HWA_ClearStatus(base, (uint32_t)FCUART_STAT_LBKDIF); + /* Disable the lin break detect interrupt and clean the status flag. */ + FCUART_HWA_SetLinBreakDetectInterrupt(base, false); + /* Disable lin detect feature, so the data can be stored to RX FIFO. */ + FCUART_HWA_SetLinBreakDetectEnable(base, false); + + /* In this state, maste need send sync field character 0x55U, slave need call callback fucntion.*/ + if (LIN_NODE_MASTER == LIN_DrvCheckMode(u8LinIndex)) + { + if (xferState->currentNodeState == LIN_NODE_STATE_SEND_BREAK_FIELD) + { + xferState->currentNodeState = LIN_NODE_STATE_SEND_PID; + xferState->isBusBusy = true; + + FCUART_HWA_SetData(base, 0x55U); + xferState->currentNodeState = LIN_NODE_STATE_RECV_SYNC; + } + } + else + { + xferState->isBusBusy = true; + xferState->currentEventId = LIN_RECV_BREAK_FIELD_OK; + /* call user's application. */ + if (NULL != xferState->Callback) + { + xferState->Callback(u8LinIndex, xferState); + } + /* Enter next state. */ + xferState->currentNodeState = LIN_NODE_STATE_RECV_SYNC; + } + } + /* Step 2: receive sync filed 0x55U. */ + else if (xferState->currentNodeState == LIN_NODE_STATE_RECV_SYNC) + { + /* If sync byte is 0x55U,transfer success, other failed, maybe baudrate error or protocol error. */ + if (0x55U == u8ReceiveByte) + { + xferState->currentEventId = LIN_SYNC_OK; + xferState->currentNodeState = LIN_NODE_STATE_RECV_PID; + + if (LIN_NODE_MASTER == LIN_DrvCheckMode(u8LinIndex)) + { + FCUART_HWA_SetData(base, (uint32_t)xferState->currentPid); + } + } + else + { + xferState->isBusBusy = false; + xferState->currentEventId = LIN_SYNC_ERROR; + + /* Inform user the transfer status. */ + if (NULL != xferState->Callback) + { + xferState->Callback(u8LinIndex, xferState); + } + + /* Go to IDLE state, start a new transfer. */ + LIN_DrvGoToIdleMode(u8LinIndex); + } + } + /* Step 3: receive and Check PID. */ + else if (xferState->currentNodeState == LIN_NODE_STATE_RECV_PID) + { + /* master node only check if the receive data is match current pid, then enter next state. */ + if (LIN_NODE_MASTER == LIN_DrvCheckMode(u8LinIndex)) + { + /* Update the xfer state */ + if (u8ReceiveByte == xferState->currentPid) + { + xferState->currentNodeState = LIN_NODE_STATE_RECV_DATA; + xferState->isBusBusy = false; + xferState->currentEventId = LIN_PID_OK; + } + else + { + xferState->currentNodeState = LIN_NODE_STATE_IDLE; + xferState->isBusBusy = false; + xferState->currentEventId = LIN_PID_ERROR; + } + + /* Inform user the transfer status. */ + if (NULL != xferState->Callback) + { + xferState->Callback(u8LinIndex, xferState); + } + } + else + { + xferState->currentId = LIN_DrvParityCheck(u8ReceiveByte); + xferState->currentPid = u8ReceiveByte; + + /* Update xfer state. */ + if (0xFFU == xferState->currentId) + { + xferState->currentNodeState = LIN_NODE_STATE_IDLE; + xferState->isBusBusy = false; + xferState->currentEventId = LIN_PID_ERROR; + } + else + { + xferState->currentNodeState = LIN_NODE_STATE_RECV_DATA; + xferState->isBusBusy = false; + xferState->currentEventId = LIN_PID_OK; + } + + /* Inform user the transfer status. */ + if (NULL != xferState->Callback) + { + xferState->Callback(u8LinIndex, xferState); + } + } + } + else + { + /* Misra check */ + } +} + + +/** + * @brief Make checksum byte + */ +static uint8_t LIN_DrvMakeCheckSum(uint8_t u8LinIndex, uint8_t *pBuf, uint8_t u8Size, uint8_t u8Pid) +{ + lin_config_t *pConfig = s_aLinConfig[u8LinIndex]; + uint16_t u16Checksum = 0U; + uint8_t u8Length = 0U; + +// if ((pConfig->numOfClassicPID == 0U) || (pConfig->numOfClassicPID == 255U)) +// { + if (pConfig->classicPID != NULL) + { +// for (uint8_t i = 0U; i < pConfig->numOfClassicPID; i++) +// { +// if (u8Pid == pConfig->classicPID[i]) +// { + u8Pid = 0U; +// break; +// } +// } + } +// } + + /* For PID is 0x3C (ID 0x3C) or 0x7D (ID 0x3D) or 0xFE (ID 0x3E) or 0xBF (ID 0x3F)*/ + if ((0x3CU == u8Pid) || (0x7DU == u8Pid) || (0xFEU == u8Pid) || (0xBFU == u8Pid)) + { + u8Pid = 0U; + } + + u16Checksum += u8Pid; + + for (u8Length = 0U; u8Length < u8Size; u8Length++) + { + u16Checksum += *pBuf; + pBuf++; + if (u16Checksum > 0xFFU) + { + u16Checksum -= 0xFFU; + } + } + + return ~(uint8_t)(u16Checksum); +} + +/** + * @brief receive frame data in IRQ handler. + */ +static void LIN_DrvReceiveFrameData(uint8_t u8LinIndex, uint8_t u8ReceiveByte) +{ + lin_xfer_state_t *xferState = s_aLinXfer[u8LinIndex]; + + xferState->cntByte++; + + if (xferState->cntByte < xferState->rxSize) + { + *(xferState->rxBuff) = u8ReceiveByte; + xferState->rxBuff++; + } + /* Checksum data. */ + else if (xferState->cntByte == xferState->rxSize) + { + xferState->checkSum = u8ReceiveByte; + xferState->rxBuff -= (xferState->rxSize - 1U); + + // Checksun compared. + if (xferState->checkSum == LIN_DrvMakeCheckSum(u8LinIndex, xferState->rxBuff, + xferState->rxSize - 1U, xferState->currentPid)) + { + xferState->currentNodeState = LIN_NODE_STATE_RECV_DATA_COMPLETED; + xferState->currentEventId = LIN_RX_COMPLETED; + } + else + { + xferState->currentEventId = LIN_CHECKSUM_ERROR; + } + + /* call user's application. */ + if (NULL != xferState->Callback) + { + xferState->Callback(u8LinIndex, xferState); + } + + /* Go to IDLE state, start a new transfer. */ + LIN_DrvGoToIdleMode(u8LinIndex); + } + /* Maybe error occurred. */ + else + { + /* MISRA-2012 check. */ + } +} + +/** + * @brief This API will send frame data, due to the LIN node will receive the byte sent by itself, + * we will also check the receive data while sending bytes. + */ +static void LIN_DrvSendFrameData(uint8_t u8LinIndex, uint8_t u8ReceiveByte) +{ + lin_xfer_state_t *xferState = s_aLinXfer[u8LinIndex]; + FCUART_Type *base = s_aFCUART_InstanceTable[u8LinIndex]; + + if (xferState->cntByte < xferState->txSize) + { + /* The received byte should be the byte just send. */ + if (u8ReceiveByte != *(xferState->txBuff - 1)) + { + xferState->currentEventId = LIN_READBACK_ERROR; + + /* call user's application. */ + if (NULL != xferState->Callback) + { + xferState->Callback(u8LinIndex, xferState); + } + } + else + { + if (xferState->cntByte == (xferState->txSize - 1U)) + { + FCUART_HWA_SetData(base, (uint32_t)xferState->checkSum); + } + else + { + FCUART_HWA_SetData(base, (uint32_t) * (xferState->txBuff)); + } + + xferState->txBuff++; + xferState->cntByte++; + } + } + /* Last byte received, no need to send anything. */ + else if (xferState->cntByte == xferState->txSize) + { + if (u8ReceiveByte != xferState->checkSum) + { + xferState->currentEventId = LIN_READBACK_ERROR; + } + else + { + xferState->currentEventId = LIN_TX_COMPLETED; + } + + /* call user's application. */ + if (NULL != xferState->Callback) + { + xferState->Callback(u8LinIndex, xferState); + } + + /* Go to IDLE state, start a new transfer. */ + LIN_DrvGoToIdleMode(u8LinIndex); + } + else + { + /* MISRA Check. */ + } +} + +/** + * @brief Handle the frame data, sending or receiving frame data. + */ + +static void LIN_DrvFrameHandle(uint8_t u8LinIndex) +{ + lin_xfer_state_t *xferState = s_aLinXfer[u8LinIndex]; + FCUART_Type *base = s_aFCUART_InstanceTable[u8LinIndex]; + uint8_t u8ReceiveByte = 0U; + + if (FCUART_HWA_GetStatus(base, FCUART_STAT_RDRFF)) + { + u8ReceiveByte = FCUART_HWA_GetData(base); + } + + /* Handle node to recive frame data. */ + if (LIN_NODE_STATE_RECV_DATA == xferState->currentNodeState) + { + LIN_DrvReceiveFrameData(u8LinIndex, u8ReceiveByte); + } + /* Handle node to send frame data. */ + else if (LIN_NODE_STATE_SEND_DATA == xferState->currentNodeState) + { + LIN_DrvSendFrameData(u8LinIndex, u8ReceiveByte); + } + /* Handle header. */ + else + { + LIN_DrvHeaderHandle(u8LinIndex, u8ReceiveByte); + } +} + +/** + * @brief This API will handle wakeup signal, and calculate the value wakeup signal send. + * Actually, step 1, FCUART will wait a low level in RX pin, and than inverse the RX data + * while the rise edge is coming, another interrupt will be triggered, the time between this + * two interrupt is the wakeup time value. + */ +static void LIN_DrvWakeupHandle(uint8_t u8LinIndex) +{ + lin_xfer_state_t *xferState = s_aLinXfer[u8LinIndex]; + FCUART_Type *base = s_aFCUART_InstanceTable[u8LinIndex]; + uint32_t s_wakeupTime = 0U; + + /* Clear status.*/ + FCUART_HWA_ClearStatus(base, FCUART_STAT_RPAEIF); + + /* Step 1, record the first receive active time. */ + if (false == FCUART_HWA_GetReceiveDataInverse(base)) + { + /* Call the uer time value call function. */ + if (NULL != s_aLinConfig[u8LinIndex]->getIntervalTimeValueCallback) + { + s_aLinConfig[u8LinIndex]->getIntervalTimeValueCallback(&s_wakeupTime); + } + + /* Chang the receive data inverse, and receive the next interrupt. */ + FCUART_HWA_SetReceiveDataInverse(base, true); + } + /* Step 2. calculate the wakeup time. */ + else + { + FCUART_HWA_SetReceiveDataInverse(base, false); + + /* Call the uer time value call function. */ + if (NULL != s_aLinConfig[u8LinIndex]->getIntervalTimeValueCallback) + { + s_aLinConfig[u8LinIndex]->getIntervalTimeValueCallback(&s_wakeupTime); + } + + if (150U < s_wakeupTime) + { + xferState->currentEventId = LIN_WAKEUP_SIGNAL; + + /* call user's application. */ + if (NULL != xferState->Callback) + { + xferState->Callback(u8LinIndex, xferState); + } + + /* Enter IDLE state to prepare next transfer. */ + LIN_DrvGoToIdleMode(u8LinIndex); + } + } +} + +/* ################################################################################## */ +/* ################################ Global Functions ################################ */ + +/** + * @brief Init the LIN instance for LIN network. This API will help initialize the FCUART to expect state, + * but will nots start the TX&RX function, if users want to start the LIN protocol transfer, please + * call the function LIN_DrvStart() after this API is called. + * + * @param u8LinIndex LIN hardware instance, 0U... + * @param pConfig Configuration for LIN hardware, must not be null. + * @return operation status: + * - LIN_STATUS_SUCCESS : operation is successfully. + * - LIN_STATUS_USEED : The instance has been used, user should use another instance or de-initialize this instance + * firstly. + * - LIN_STATUS_ERROR : the baudrate has not been set successfully. + */ +LIN_StatusType LIN_DrvInit(uint8_t u8LinIndex, lin_config_t *pConfig) +{ + LIN_StatusType tRetVal = LIN_STATUS_SUCCESS; + FCUART_Type *base = s_aFCUART_InstanceTable[u8LinIndex]; + uint32_t u32BaudRegValue = 0U; + uint32_t u32CtrlRegValue = 0U; + uint32_t u32StatRegValue = 0U; + uint32_t u32Sbr = 0U; + uint32_t u32OverSamp = 0U; + + DEV_ASSERT(u8LinIndex < LIN_INSTANCE_NUM); + DEV_ASSERT(pConfig != NULL); + + /* Check the LIN instance used or not. */ + if (s_aInstanceUsed[u8LinIndex] == 1U) + { + tRetVal = LIN_STATUS_USEED; + } + else + { + s_aLinConfig[u8LinIndex] = pConfig; + + /* Reset the hardware LIN instance to expect state. */ + FCUART_HWA_SoftwareReset(base); + + /* Set BAUD register configuration: + * - calculate the baudrate generated value. + * - LIN break detect interrupt enable; + * - RX pin active edge disabled, for checking the wakeup signal; + * - Stop bit set to 1; + */ + tRetVal = LIN_DrvCalBaudrate(u8LinIndex, &u32OverSamp, &u32Sbr); + u32BaudRegValue |= FCUART_BAUD_OVR_SAMP(u32OverSamp - 1U) | FCUART_BAUD_BEDGE_SAMP( + 1U) | FCUART_BAUD_SBR(u32Sbr); + FCUART_HWA_SetBaud(base, u32BaudRegValue); + FCUART_HWA_SetLinBreakDetectInterrupt(base, true); + + /* Set LIN break send and detect to 13 bits minimum. If in slave node, only enable detect feature. */ + u32StatRegValue |= FCUART_STAT_BCGL(1U) | FCUART_STAT_LBKDE(0U); + FCUART_HWA_WriteClearSTAT(base, u32StatRegValue); + + /* Set CTRL register configuration: + * - Enable frame error interrupt; + * - Enable receive interrupt; + * - 8 bits transfer mode enabled; + * - Parity check mode disable; + */ + //FCUART_CTRL_IDLECFG(FCUART_IDLE_CHARCTER_128) + + u32CtrlRegValue |= FCUART_CTRL_FEIE(1U) | FCUART_CTRL_RIE(1U) | FCUART_CTRL_BMSEL(0U) | FCUART_CTRL_PE(0U); + FCUART_HWA_SetCtrl(base, u32CtrlRegValue); + + /* Do not use the FIFO feature. the baudrate of LIN protocol is not too high, so do not use fifo feature. */ + FCUART_HWA_SetFifo(base, 0U); + + /* FIFO watermark set to 0. */ + FCUART_HWA_SetWaterMark(base, 0U); + + /* Update the instance used state. */ + s_aInstanceUsed[u8LinIndex] = 1U; + } + + return tRetVal; +} + +/** + * @brief De-Init the LIN instance used by LIN network. + * This API will help disable the fcuart interrupts and stop the TX/RX transfer. + * + * @return operation status: + * - LIN_STATUS_SUCCESS : operation is successfully. + * - LIN_STATUS_NOT_INIT : The instance has not been initialized. + */ +LIN_StatusType LIN_DrvDeInit(uint8_t u8LinIndex) +{ + LIN_StatusType tRetVal = LIN_STATUS_SUCCESS; + FCUART_Type *base = s_aFCUART_InstanceTable[u8LinIndex]; + lin_xfer_state_t *xferState = s_aLinXfer[u8LinIndex]; + + DEV_ASSERT(u8LinIndex < LIN_INSTANCE_NUM); + + /* Instance has not been initialized, no need to do anything */ + if (s_aInstanceUsed[u8LinIndex] == 0U) + { + tRetVal = LIN_STATUS_NOT_INIT; + } + else + { + /* Check if still bytes need to be send or receive. wait the protocol is not busy. */ + while (xferState->isBusBusy) + { + } + + /* Update LIN instance to initialize state. */ + s_aLinConfig[u8LinIndex] = NULL; + s_aLinXfer[u8LinIndex] = NULL; + s_aInstanceUsed[u8LinIndex] = 0U; + + /* Stop TX/TX function and FCUART instance. */ + FCUART_HWA_SetTxTransfer(base, false); + FCUART_HWA_SetRxTransfer(base, false); + + /* Reset the FCUART instance. */ + FCUART_HWA_SoftwareReset(base); + } + + return tRetVal; +} + +/** + * @brief Help users get the default configuration of LIN node. users should provide the configuration structure + * in app code, and transfer the ptr address to driver code. uses can also set this parameters in the application code + * as designed. + * + * @param u8NodeMode LIN node mode select, 0 for slave mode and 1 for master mode. + * @param pConfig default configuration for LIN node, must not be null. + */ +void LIN_DrvGetDefaultConfig(LIN_NodeType eNodeMode, lin_config_t *pConfig) +{ + /* Check NUll ptr for bus error. */ + DEV_ASSERT(pConfig != NULL); + + pConfig->nodeMode = eNodeMode; /*!< Node mode as Master node or Slave node. 0: slave 1: master */ + pConfig->baudRate = 19200U; /*!< baudrate configurations for LIN protocol. */ + pConfig->getIntervalTimeValueCallback = NULL; /*!< Callback function to get time interval in nanoseconds */ + pConfig->classicPID = NULL; /*!< List of PIDs use classic checksum */ + pConfig->numOfClassicPID = 0U; /*!< Number of PIDs use classic checksum */ +} + +/** + * @brief Start LIN node transfer, this API should be called after LIN hardware has been initialized, and must + * be called before starting a LIN node transfer. Users should provide a tansfer structure for storing the + * transfer state, ant LIN node state changed will be stored to this xfer state. + * + * @param u8LinIndex LIN hardware instance, 0U... + * @param pXferState Transfer state structure which will help store the trasnfer state. + * @return operation status: + * - LIN_STATUS_SUCCESS : operation is successfully. + * - LIN_STATUS_PARAM_ERROR: the parameter setting maybe not correct, maybe instance has bot been initialized. + */ +LIN_StatusType LIN_DrvStart(uint8_t u8LinIndex, lin_xfer_state_t *pXferState) +{ + LIN_StatusType tRetVal = LIN_STATUS_ERROR; + FCUART_Type *base = s_aFCUART_InstanceTable[u8LinIndex]; + + DEV_ASSERT(pXferState != NULL); + DEV_ASSERT(u8LinIndex < LIN_INSTANCE_NUM); + + /* If instance has not been intialized, inform users with the error state. */ + if (0U == s_aInstanceUsed[u8LinIndex]) + { + tRetVal = LIN_STATUS_PARAM_ERROR; + } + else + { + /* Register transfer ptr. */ + s_aLinXfer[u8LinIndex] = pXferState; + + /* Initialize the xfer state of LIN transfer. */ + pXferState->isTxBusy = false; + pXferState->isRxBusy = false; + pXferState->isBusBusy = false; + pXferState->isRxBlocking = false; + pXferState->isTxBlocking = false; + pXferState->timeoutCounterFlag = false; + pXferState->timeoutCounter = 0U; + pXferState->currentNodeState = LIN_NODE_STATE_IDLE; + pXferState->currentEventId = LIN_NO_EVENT; + + FCUART_HWA_SetTxTransfer(base, true); + FCUART_HWA_SetRxTransfer(base, true); + { + /*TOBE CHECKED*/ + uint32_t u32Temp; + u32Temp = FCUART_HWA_GetSTAT(base); + u32Temp |= FCUART_STAT_M1F | FCUART_STAT_M0F | FCUART_STAT_FEF; + FCUART_HWA_ClearStatus(base, u32Temp); + FCUART_HWA_GetData(base); + } + + /* Slave will enter the IDEL state, and listening the protocol all time, waiting for a break files. */ + if (LIN_NODE_SLAVE == s_aLinConfig[u8LinIndex]->nodeMode) + { + /* Start hardware. */ + FCUART_HWA_SetLinBreakDetectEnable(base, true); + FCUART_HWA_SetLinBreakDetectInterrupt(base, true); + } + + tRetVal = LIN_STATUS_SUCCESS; + } + + return tRetVal; +} + +/** + * @brief This function will help install callback function that used by application code. + * users can handle some needed operations in driver code or get some important states. + * or uses can also setting this in transfer state structure. + * + * @param u8LinIndex LIN hardware instance, 0U... + * @param callback user's callbak function that need be called in driver code. + * @return operation status: + * - LIN_STATUS_SUCCESS : operation is successfully. + * - LIN_STATUS_NOT_INIT : The instance required has bot been initialized. + */ +LIN_StatusType LIN_DrvInstallUserCallback(uint8_t u8LinIndex, lin_callback_t callback) +{ + DEV_ASSERT(u8LinIndex < LIN_INSTANCE_NUM); + LIN_StatusType tRetVal = LIN_STATUS_ERROR; + lin_xfer_state_t *xferState = s_aLinXfer[u8LinIndex]; + + if (NULL == xferState) + { + tRetVal = LIN_STATUS_NOT_INIT; + } + else + { + xferState->Callback = callback; + tRetVal = LIN_STATUS_SUCCESS; + } + + return tRetVal; +} + +/** + * @brief This function will help users send a header in master node which will help start a new + * frame transfer. please do not used this API will LIN instance is configured as slave node. + * This API will make a parity ID, and only send a break field to the protocol, all the other + * filed like sync filed and pid byte will be handled in FCUART IRQHandler. more details can + * refer to IRQ routine. + * + * @param u8LinIndex LIN hardware instance, 0U... + * @param u8Id The ID data that useds need to send in header. + * @return operation status: + * - LIN_STATUS_SUCCESS : operation is successfully. + * - LIN_STATUS_NOT_INIT : Instance required has not been intialized. + * - LIN_STATUS_UNSUPPORTED : Current node is slave not, could not send header to protocol. + * - LIN_STATUS_BUSY : Bus busy which means node is sending or receiving another frame. + */ +LIN_StatusType LIN_DrvSendHeader(uint8_t u8LinIndex, uint8_t u8Id) +{ + DEV_ASSERT(u8LinIndex < LIN_INSTANCE_NUM); + FCUART_Type *base = s_aFCUART_InstanceTable[u8LinIndex]; + lin_xfer_state_t *xferState = s_aLinXfer[u8LinIndex]; + LIN_StatusType tRetVal = LIN_STATUS_SUCCESS; + + DEV_ASSERT(u8LinIndex < LIN_INSTANCE_NUM); + DEV_ASSERT(xferState != NULL); + + /* Check node state. */ + if (xferState->currentNodeState == LIN_NODE_STATE_UNINIT) + { + tRetVal = LIN_STATUS_NOT_INIT; + } + /* Slave node can not send header. */ + else if (s_aLinConfig[u8LinIndex]->nodeMode == LIN_NODE_SLAVE) + { + tRetVal = LIN_STATUS_UNSUPPORTED; + } + else + { + if (xferState->isBusBusy == true) + { + tRetVal = LIN_STATUS_BUSY; + } + else + { + /* Update node state. */ + xferState->currentId = u8Id; + xferState->currentPid = LIN_DrvParityMake(u8Id); + xferState->currentEventId = LIN_NO_EVENT; + xferState->currentNodeState = LIN_NODE_STATE_SEND_BREAK_FIELD; + xferState->isBusBusy = false; + + /* Start hardware. */ + FCUART_HWA_SetLinBreakDetectEnable(base, true); + FCUART_HWA_SetLinBreakDetectInterrupt(base, true); + + /* Send a break filed to protocol. */ + FCUART_HWA_SendBreakField(base); + } + } + + return tRetVal; +} + +/** + * @brief This API will help users send a frame data through LIN protocol, and will return only when + * all frame data has been sent to the protocol, or while timeout occurred, so please configure + * the u32TimeOut parameter as needed. And currentlyt this API has not implement the OS feature, + * so do not call this API in interrupt routine, otherwise, routine maybe halted by this API. + * + * @param u8LinIndex LIN hardware instance, 0U... + * @param pTxBuf TX buffer whihc will be sent to protocol, MUST NOT BE NULL. + * @param u8Length bytes lengths in TX buffer. + * @param u32TimeOut Timeout value, 0 indicates timeout feature is not used, in unit of millieconds. + * @return operation status: + * - LIN_STATUS_SUCCESS : operation is successfully. + * - LIN_STATUS_NOT_INIT : Instance required has not been initialized. + * - LIN_STATUS_BUSY : Bus busy, node is transfer state. + */ +LIN_StatusType LIN_DrvSendFrameBlocking(uint8_t u8LinIndex, uint8_t *pTxBuf, uint8_t u8Length, + uint32_t u32TimeOut) +{ + FCUART_Type *base = s_aFCUART_InstanceTable[u8LinIndex]; + lin_xfer_state_t *xferState = s_aLinXfer[u8LinIndex]; + LIN_StatusType tRetVal = LIN_STATUS_SUCCESS; + + DEV_ASSERT(u8LinIndex < LIN_INSTANCE_NUM); + DEV_ASSERT((NULL != pTxBuf) && (0U != u8Length)); + DEV_ASSERT(xferState != NULL); + + /* Check node state. */ + if (xferState->currentNodeState == LIN_NODE_STATE_UNINIT) + { + tRetVal = LIN_STATUS_NOT_INIT; + } + else + { + if (xferState->isBusBusy) + { + tRetVal = LIN_STATUS_BUSY; + } + else + { + xferState->currentNodeState = LIN_NODE_STATE_SEND_DATA; + xferState->currentEventId = LIN_NO_EVENT; + + xferState->txBuff = pTxBuf; + xferState->txSize = u8Length + 1U; + xferState->cntByte = 0U; + xferState->checkSum = LIN_DrvMakeCheckSum(u8LinIndex, pTxBuf, u8Length, + xferState->currentPid); + xferState->isTxBusy = true; + xferState->isBusBusy = true; + xferState->isTxBlocking = true; + xferState->timeoutCounter = u32TimeOut; + xferState->timeoutCounterFlag = false; + + FCUART_HWA_SetLinBreakDetectEnable(base, false); + FCUART_HWA_SetData(base, (uint32_t) * (xferState->txBuff)); + + xferState->txBuff++; + xferState->cntByte++; + + /* Waiting for teansfer complete. */ + while (xferState->isTxBusy == true) + { + if (xferState->timeoutCounterFlag == true) + { + tRetVal = LIN_STATUS_TIMEOUT; + break; + } + } + + LIN_DrvGoToIdleMode(u8LinIndex); + } + } + + return tRetVal; +} + +/** + * @brief This API will help users send a frame data through LIN protocol, this API will return immediately. + * data will be stored in txbuffer, users can check the transmit status while data is sending. + * + * @param u8LinIndex LIN hardware instance, 0U... + * @param pTxBuf TX buffer whihc will be sent to protocol, MUST NOT BE NULL. + * @param u8Length bytes lengths in TX buffer. + * @param u32TimeOut Timeout value, 0 indicates timeout feature is not used, in unit of millieconds. + * @return operation status: + * - LIN_STATUS_SUCCESS : operation is successfully. + * - LIN_STATUS_NOT_INIT : Instance required has not been initialized. + * - LIN_STATUS_BUSY : Bus busy, node is transfer state. + */ +LIN_StatusType LIN_DrvSendFrameNonBlocking(uint8_t u8LinIndex, uint8_t *pTxBuf, uint8_t u8Length) +{ + FCUART_Type *base = s_aFCUART_InstanceTable[u8LinIndex]; + lin_xfer_state_t *xferState = s_aLinXfer[u8LinIndex]; + LIN_StatusType tRetVal = LIN_STATUS_SUCCESS; + + DEV_ASSERT(u8LinIndex < LIN_INSTANCE_NUM); + DEV_ASSERT((NULL != pTxBuf) && (0U != u8Length)); + DEV_ASSERT(xferState != NULL); + + /* Check node state. */ + if (xferState->currentNodeState == LIN_NODE_STATE_UNINIT) + { + tRetVal = LIN_STATUS_NOT_INIT; + } + else + { + if (xferState->isBusBusy) + { + tRetVal = LIN_STATUS_BUSY; + } + else + { + xferState->currentNodeState = LIN_NODE_STATE_SEND_DATA; + xferState->currentEventId = LIN_NO_EVENT; + + xferState->txBuff = pTxBuf; + xferState->txSize = u8Length + 1U; + xferState->cntByte = 0U; + xferState->checkSum = LIN_DrvMakeCheckSum(u8LinIndex, pTxBuf, u8Length, xferState->currentPid); + xferState->isTxBusy = true; + xferState->isBusBusy = true; + + FCUART_HWA_SetLinBreakDetectEnable(base, false); + FCUART_HWA_SetData(base, (uint32_t) * (xferState->txBuff)); + + xferState->txBuff++; + xferState->cntByte++; + } + } + + return tRetVal; +} + +/** + * @brief This API will help users get the LIN transfer status while data is sending. and will also + * help user get remainning byte in transfer still need sending in buffer. + * + * @param u8LinIndex LIN hardware instance, 0U... + * @param pRemainBytes Address to be stored the remain byte value, should not be NULL. + * @return operation status: + * - LIN_STATUS_TIMEOUT : node transfer timeout occurred. + * - LIN_STATUS_SUCCESS : transfer complete. + * - LIN_STATUS_BUSY : transfer is going + */ +LIN_StatusType LIN_DrvGetTransmitStatus(uint8_t u8LinIndex, uint8_t *pRemainBytes) +{ + LIN_StatusType tRetVal = LIN_STATUS_SUCCESS; + lin_xfer_state_t *xferState = s_aLinXfer[u8LinIndex]; + + /* Return the remaining byte inlcude checksun byte. */ + *pRemainBytes = xferState->txSize - xferState->cntByte; + + /* Check LIN node status. */ + if (xferState->timeoutCounterFlag == true) + { + tRetVal = LIN_STATUS_TIMEOUT; + } + else if (xferState->isTxBusy == true) + { + tRetVal = LIN_STATUS_BUSY; + } + else + { + } + + return tRetVal; +} + +/** + * @brief This API will help users receive frame data through LIN protocol, this API will return only when + * all frame data has been received from the protocol, or while timeout occurred, so please configure + * the u32TimeOut parameter as needed. And currently, this API has not implement the OS feature, + * so do not call this API in interrupt routine, otherwise, routine maybe halted by this API. + * + * @param u8LinIndex LIN hardware instance, 0U... + * @param pRxBuf RX buffer which will be received from protocol, MUST not be NULL. + * @param u8Length bytes lengths should be received. + * @param u32TimeOut Timeout value, 0 indicates timeout feature is not used, in millieconds. + * @return operation status: + * - LIN_STATUS_SUCCESS : operation is successfully. + * - LIN_STATUS_NOT_INIT : Instance has not been initialized + * - LIN_STATUS_BUSY : Bus in busy state, need wait bus idle. + * - LIN_STATUS_TIMEOUT : Timeout occurred, data received may not successful. + */ +LIN_StatusType LIN_DrvReceiveFrameBlocking(uint8_t u8LinIndex, uint8_t *pRxBuf, uint8_t u8Length, + uint32_t u32TimeOut) +{ + FCUART_Type *base = s_aFCUART_InstanceTable[u8LinIndex]; + lin_xfer_state_t *xferState = s_aLinXfer[u8LinIndex]; + LIN_StatusType tRetVal = LIN_STATUS_SUCCESS; + + DEV_ASSERT(u8LinIndex < LIN_INSTANCE_NUM); + DEV_ASSERT((NULL != pRxBuf) && (0U != u8Length)); + DEV_ASSERT(xferState != NULL); + + /* Check node state. */ + if (xferState->currentNodeState == LIN_NODE_STATE_UNINIT) + { + tRetVal = LIN_STATUS_NOT_INIT; + } + else + { + if (xferState->isBusBusy) + { + tRetVal = LIN_STATUS_BUSY; + } + else + { + xferState->currentNodeState = LIN_NODE_STATE_RECV_DATA; + xferState->currentEventId = LIN_NO_EVENT; + + xferState->rxBuff = pRxBuf; + xferState->rxSize = u8Length + 1U; + xferState->cntByte = 0U; + xferState->isRxBusy = true; + xferState->isBusBusy = true; + xferState->isRxBlocking = true; + xferState->timeoutCounter = u32TimeOut; + xferState->timeoutCounterFlag = false; + + /* Waiting for complete. */ + while (xferState->isRxBusy == true) + { + if (true == xferState->timeoutCounterFlag) + { + tRetVal = LIN_STATUS_TIMEOUT; + break; + } + } + + FCUART_HWA_SetLinBreakDetectEnable(base, false); + } + } + + return tRetVal; +} + +/** + * @brief This API will help users receive frame data through LIN protocol, this API will return immediately. + * data will be stored in rxbuffer, users can check the receive status while using this API. + * + * @param u8LinIndex LIN hardware instance, 0U... + * @param pRxBuf RX buffer which will be received from protocol, MUST not be NULL. + * @param u8Length bytes lengths should be received. + * @param u32TimeOut Timeout value, 0 indicates timeout feature is not used, in millieconds. + * @return operation status: + * - LIN_STATUS_SUCCESS : operation is successfully. + * - LIN_STATUS_NOT_INIT : Instance has not been initialized + * - LIN_STATUS_BUSY : Bus in busy state, need wait bus idle. + * - LIN_STATUS_TIMEOUT : Timeout occurred, data received may not successful. + */ +LIN_StatusType LIN_DrvReceiveFrameNonBlocking(uint8_t u8LinIndex, uint8_t *pRxBuf, uint8_t u8Length) +{ + FCUART_Type *base = s_aFCUART_InstanceTable[u8LinIndex]; + lin_xfer_state_t *xferState = s_aLinXfer[u8LinIndex]; + LIN_StatusType tRetVal = LIN_STATUS_SUCCESS; + + DEV_ASSERT(u8LinIndex < LIN_INSTANCE_NUM); + DEV_ASSERT((NULL != pRxBuf) && (0U != u8Length)); + DEV_ASSERT(xferState != NULL); + + /* Check node state. */ + if (xferState->currentNodeState == LIN_NODE_STATE_UNINIT) + { + tRetVal = LIN_STATUS_NOT_INIT; + } + else + { + if (xferState->isBusBusy) + { + tRetVal = LIN_STATUS_BUSY; + } + else + { + xferState->currentNodeState = LIN_NODE_STATE_RECV_DATA; + xferState->currentEventId = LIN_NO_EVENT; + + xferState->rxBuff = pRxBuf; + xferState->rxSize = u8Length + 1U; + xferState->cntByte = 0U; + xferState->isRxBusy = true; + xferState->isBusBusy = true; + + FCUART_HWA_SetLinBreakDetectEnable(base, false); + } + } + + return tRetVal; +} + +/** + * @brief This API will help users get the LIN transfer status while data is receiving. and will also + * help user get remainning byte in transfer still need receiving in buffer. + * + * @param u8LinIndex LIN hardware instance, 0U... + * @param pRemainBytes Address to be stored the remain byte value, should not be NULL. + * @return operation status: + * - LIN_STATUS_TIMEOUT : node transfer timeout occurred. + * - LIN_STATUS_SUCCESS : transfer complete. + * - LIN_STATUS_BUSY : transfer is going, could read the remain byte in pRemainBytes. + */ +LIN_StatusType LIN_DrvGetReceiveStatus(uint8_t u8LinIndex, uint8_t *pRemainBytes) +{ + LIN_StatusType tRetVal = LIN_STATUS_SUCCESS; + lin_xfer_state_t *xferState = s_aLinXfer[u8LinIndex]; + + DEV_ASSERT(u8LinIndex < LIN_INSTANCE_NUM); + + /* Return the remaining byte inlcude checksun byte. */ + *pRemainBytes = xferState->rxSize - xferState->cntByte; + + if (xferState->timeoutCounterFlag == true) + { + tRetVal = LIN_STATUS_TIMEOUT; + } + else if (xferState->isRxBusy == true) + { + tRetVal = LIN_STATUS_BUSY; + } + else + { + } + return tRetVal; +} + +/** + * @brief Abort transfer both sending or receiving data, actually, call this APU will enter IDLE state. + * will stop end and receive even data transfer is on going. + * + * @param u8LinIndex LIN hardware instance, 0U... + * @return operation status: + * - LIN_STATUS_SUCCESS : operation is successfully. + */ +LIN_StatusType LIN_DrvAbortTransfer(uint8_t u8LinIndex) +{ + LIN_StatusType tRetVal = LIN_STATUS_SUCCESS; + DEV_ASSERT(u8LinIndex < LIN_INSTANCE_NUM); + + /* Update the LIN state to IDLE state directly. */ + tRetVal = LIN_DrvGoToIdleMode(u8LinIndex); + + return tRetVal; +} + +/** + * @brief This API should be called while no data is transferring, once this API is called, node will + * enter sleep mode, TX/RX and interrupts will also be disabled, and node will wait a wakeup signal + * on the protocol. This API will enable receive active interrupt, once a wakeup signal triggered, + * routine will entern uart IRQHandler to handle this case, and then wakeup the LIN node. + * + * @param u8LinIndex LIN hardware instance, 0U... + * @return operation status: + * - LIN_STATUS_SUCCESS : operation is successfully. + */ +LIN_StatusType LIN_DrvGoToSleepMode(uint8_t u8LinIndex) +{ + FCUART_Type *base = s_aFCUART_InstanceTable[u8LinIndex]; + lin_xfer_state_t *xferState = s_aLinXfer[u8LinIndex]; + DEV_ASSERT(u8LinIndex < LIN_INSTANCE_NUM); + + /* Update software status. */ + xferState->currentEventId = LIN_NO_EVENT; + xferState->currentNodeState = LIN_NODE_STATE_SLEEP_MODE; + xferState->isBusBusy = false; + xferState->isRxBusy = false; + xferState->isTxBusy = false; + + /* Disable all enabled interrupt except receive active interrupt. */ + FCUART_HWA_SetLinBreakDetectEnable(base, true); + FCUART_HWA_SetLinBreakDetectInterrupt(base, false); + FCUART_HWA_DisableErrorInterrupt(base); + FCUART_HWA_DisableReceiveInterrupt(base); + FCUART_HWA_SetReceiveActiveInterrupt(base, true); + + return LIN_STATUS_SUCCESS; +} + +/** + * @brief THis API will help confgure the mode into IDLE state. In IDLE state, node will enable receive interrupt and break + * field detect interrupt, slave node will wait the break field from master node, master node will prepare to send a + * new break filed to start a new frame. + * + * @param u8LinIndex LIN hardware instance, 0U... + * @return operation status: + * - LIN_STATUS_SUCCESS : operation is successfully. + */ +LIN_StatusType LIN_DrvGoToIdleMode(uint8_t u8LinIndex) +{ + FCUART_Type *base = s_aFCUART_InstanceTable[u8LinIndex]; + lin_xfer_state_t *xferState = s_aLinXfer[u8LinIndex]; + + DEV_ASSERT(u8LinIndex < LIN_INSTANCE_NUM); + + /* Update software status. */ + xferState->cntByte = 0U; + xferState->txSize = 0U; + xferState->rxSize = 0U; + xferState->isBusBusy = false; + xferState->isRxBusy = false; + xferState->isTxBusy = false; + xferState->isTxBlocking = false; + xferState->isRxBlocking = false; + xferState->currentId = 0U; + xferState->currentPid = 0U; + xferState->currentEventId = LIN_NO_EVENT; + xferState->currentNodeState = LIN_NODE_STATE_IDLE; + xferState->timeoutCounter = 0U; + xferState->timeoutCounterFlag = false; + + /* Update hardware configration. + * 1. Enable LIN break detect interrupr; + * 2. Enable frame error interrupt. + * 3. Enable receive interrupt; + */ + FCUART_HWA_WriteClearSTAT(base, FCUART_STAT_LBKDIF | FCUART_STAT_RPAEIF | FCUART_STAT_RORF_MASK | FCUART_STAT_NF_MASK | FCUART_STAT_FEF_MASK | FCUART_STAT_PEF_MASK); + FCUART_HWA_SetLinBreakDetectEnable(base, true); + FCUART_HWA_SetLinBreakDetectInterrupt(base, true); + FCUART_HWA_EnableErrorInterrupt(base); + FCUART_HWA_EnableReceiveInterrupt(base); + FCUART_HWA_SetReceiveActiveInterrupt(base, false); + FCUART_HWA_SetReceiveDataInverse(base, false); + + return LIN_STATUS_SUCCESS; +} + +/** + * @brief Sending a wakeup signal to the protocol, all LIN network nodes receive this signal will + * wakeup from sleep mode. Actually, the master will send a character which will cause a 150us + * larger active level to the protocol. while receiving this signal, LIN node will wake up + * from sleep mode. + * + * @param u8LinIndex LIN hardware instance, 0U... + * @return operation status: + * - LIN_STATUS_SUCCESS : operation is successfully. + * - LIN_STATUS_NOT_INIT : Instance required is not initialized. + * - LIN_STATUS_BUSY ：LIN node state is not correct, need update state firstly. + */ +LIN_StatusType LIN_DrvSendWakeupSignal(uint8_t u8LinIndex) +{ + FCUART_Type *base = s_aFCUART_InstanceTable[u8LinIndex]; + lin_xfer_state_t *xferState = s_aLinXfer[u8LinIndex]; + LIN_StatusType tRetVal = LIN_STATUS_SUCCESS; + + DEV_ASSERT(u8LinIndex < LIN_INSTANCE_NUM); + DEV_ASSERT(xferState != NULL); + + /* Check node state. */ + if (xferState->currentNodeState == LIN_NODE_STATE_UNINIT) + { + tRetVal = LIN_STATUS_NOT_INIT; + } + else + { + if (xferState->isBusBusy == true) + { + tRetVal = LIN_STATUS_BUSY; + } + else + { + if (s_aLinConfig[u8LinIndex]->baudRate > 10000U) + { + /* Wakeup signal will be range from 400us to 800us depend on baudrate, 0x80U */ + FCUART_HWA_SetData(base, 0x00U); + } + else + { + /* Wakeup signal will be range from 400us to 4ms depend on baudrate, 0xF8U */ + FCUART_HWA_SetData(base, 0xF8U); + } + + tRetVal = LIN_STATUS_SUCCESS; + } + } + + return tRetVal; +} + +/** + * @brief Get the LIN node state. + * + * @param u8LinIndex LIN hardware instance, 0U... + * @return the node current state, refer to @lin_node_state_t + */ +lin_node_state_t LIN_DrvGetNodeState(uint8_t u8LinIndex) +{ + DEV_ASSERT(u8LinIndex < LIN_INSTANCE_NUM); + DEV_ASSERT(s_aLinXfer[u8LinIndex] != NULL); + + lin_xfer_state_t *xferState = s_aLinXfer[u8LinIndex]; + + return xferState->currentNodeState; +} + +/** + * @brief This API should be called by user's application code, and the timeout periods should be 1ms once. + * Better to provide a timer IRQhandler to call this APIs 1ms onces. internal timeout feature will + * use this API t o handle the time counter. + * + * @param u8LinIndex LIN hardware instance, 0U... + * @return operation status: + * - LIN_STATUS_SUCCESS : operation is successfully. + */ +LIN_StatusType LIN_DrvTimeOutService(uint8_t u8LinIndex) +{ + DEV_ASSERT(u8LinIndex < LIN_INSTANCE_NUM); + + lin_xfer_state_t *xferState = s_aLinXfer[u8LinIndex]; + LIN_StatusType tRetVal = LIN_STATUS_SUCCESS; + + if ((LIN_NODE_STATE_SEND_DATA == (xferState->currentNodeState)) || (LIN_NODE_STATE_RECV_DATA == (xferState->currentNodeState))) + { + /* time counter down to 0, timeout occurred. */ + if (0U == xferState->timeoutCounter) + { + xferState->timeoutCounterFlag = true; + + /* If send data blocking feature is enabled. anc callback is not NULL. */ + xferState->currentEventId = LIN_TIMEOUT; + + if (NULL != xferState->Callback) + { + xferState->Callback(u8LinIndex, xferState); + } + + tRetVal = LIN_DrvGoToIdleMode(u8LinIndex); + } + else + { + xferState->timeoutCounter--; + } + } + + return tRetVal; +} + +/** + * @brief This API will help users set the timeout counter with one API, users should use this feature with + * LIN_DrvTimeOutService() called every fixed time. + * + * @param u8LinIndex LIN hardware instance, 0U... + * @param u32TimeOutValue Timeout value. + * @return operation status: + * - LIN_STATUS_SUCCESS : operation is successfully. + * - LIN_STATUS_NOT_INIT : Instance required is not initialized. + */ +LIN_StatusType LIN_DrvSetTimeOutCounter(uint8_t u8LinIndex, uint32_t u32TimeOutValue) +{ + LIN_StatusType tRetVal = LIN_STATUS_SUCCESS; + + DEV_ASSERT(u8LinIndex < LIN_INSTANCE_NUM); + + lin_xfer_state_t *xferState = s_aLinXfer[u8LinIndex]; + + if (NULL == xferState) + { + tRetVal = LIN_STATUS_NOT_INIT; + } + else + { + xferState->timeoutCounterFlag = false; + xferState->timeoutCounter = u32TimeOutValue; + } + + return tRetVal; +} + +/** + * @brief This API will help users get the Node timeout flag status. + * + * @param u8LinIndex LIN hardware instance, 0U... + * @return true for timeout occurred, false indicate no timeout. + */ +bool LIN_DrvGetTimeOutFlag(uint8_t u8LinIndex) +{ + DEV_ASSERT(u8LinIndex < LIN_INSTANCE_NUM); + DEV_ASSERT(NULL != s_aLinXfer[u8LinIndex]); + + lin_xfer_state_t *xferState = s_aLinXfer[u8LinIndex]; + + return xferState->timeoutCounterFlag; +} + +/** + * @brief This is LIN IRQ routine code, uses should call this in the FCUART IRQhandler code. please must implement + * the feature in application code. + * + * @param u8LinIndex LIN hardware instance, 0U... + */ +void LIN_DrvIRQHandler(uint8_t u8LinIndex) +{ + DEV_ASSERT(u8LinIndex < LIN_INSTANCE_NUM); + + FCUART_Type *base = s_aFCUART_InstanceTable[u8LinIndex]; + lin_xfer_state_t *xferState = s_aLinXfer[u8LinIndex]; + + /* Handle the wakeup feature by protocol. */ + if (true == FCUART_HWA_GetReceiveActiveInterrupt(base)) + { + if (FCUART_HWA_GetStatus(base, FCUART_STAT_RPAEIF)) + { + LIN_DrvWakeupHandle(u8LinIndex); + } + } + /* Data or lin break detect has been received from protocol. */ + else if (FCUART_HWA_GetStatus(base, (FCUART_StatType)(FCUART_STAT_LBKDIF | FCUART_STAT_RDRFF))) + { + LIN_DrvFrameHandle(u8LinIndex); + } + /* Handle error status. */ + else + { + if (FCUART_HWA_GetStatus(base, FCUART_STAT_RORF)) + { + xferState->currentEventId = LIN_RX_OVERRUN; + } + else + { + xferState->currentEventId = LIN_FRAME_ERROR; + } + + FCUART_HWA_WriteClearSTAT(base, FCUART_STAT_RORF_MASK | FCUART_STAT_NF_MASK | FCUART_STAT_FEF_MASK | FCUART_STAT_PEF_MASK); + + if (NULL != xferState->Callback) + { + xferState->Callback(u8LinIndex, xferState); + } + + /* Error occurred, enater IDLE state. */ + LIN_DrvGoToIdleMode(u8LinIndex); + } +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_lu.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_lu.c new file mode 100644 index 0000000..616ec93 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_lu.c @@ -0,0 +1,184 @@ +/** + * @file fc7xxx_driver_lu.c + * @author Flagchip0103 + * @brief FC7xxx LU driver type definition and API + * @version 0.1.0 + * @date 2023-12-19 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-19 Flagchip0103 N/A First version for FC7240 + ******************************************************************************** */ + +#include "fc7xxx_driver_lu.h" + +/** + * @brief Initialize Lu instance + * + * @param pInitStruct Lu initialization structure + * @return LU return type + */ +LU_StatusType LU_Init(const LU_InitType *const pInitStruct) +{ + uint32_t u32TempReg, u32TempCfg; + LU_StatusType eRet = LU_STATUS_SUCCESS; + LU_Type* pLu = LU; + + DEV_ASSERT(NULL_PTR != pInitStruct); + + /* set AOI0 value */ + LU_HWA_ConfigAOI0(pLu, pInitStruct->eLgNum, 0U); + /* set AOI1 value */ + LU_HWA_ConfigAOI1(pLu, pInitStruct->eLgNum, 0U); + /* set CTRL value */ + LU_HWA_ConfigCtrl(pLu, pInitStruct->eLgNum, 0U); + /* set FILT value */ + LU_HWA_ConfigFilter(pLu, pInitStruct->eLgNum, 0U); + + u32TempCfg = (uint32_t)0U | + LU_AOI_IN_CFG(LU_AOI_IN_N_A, pInitStruct->tAoi0Config.tIn0Config.eInNACfg) | + LU_AOI_IN_CFG(LU_AOI_IN_N_B, pInitStruct->tAoi0Config.tIn0Config.eInNBCfg) | + LU_AOI_IN_CFG(LU_AOI_IN_N_C, pInitStruct->tAoi0Config.tIn0Config.eInNCCfg) | + LU_AOI_IN_CFG(LU_AOI_IN_N_D, pInitStruct->tAoi0Config.tIn0Config.eInNDCfg); + u32TempReg = (uint32_t)0U | LU_AOI_IN_N_CFG(LU_AOI_IN_0, u32TempCfg); + + u32TempCfg = (uint32_t)0U | + LU_AOI_IN_CFG(LU_AOI_IN_N_A, pInitStruct->tAoi0Config.tIn1Config.eInNACfg) | + LU_AOI_IN_CFG(LU_AOI_IN_N_B, pInitStruct->tAoi0Config.tIn1Config.eInNBCfg) | + LU_AOI_IN_CFG(LU_AOI_IN_N_C, pInitStruct->tAoi0Config.tIn1Config.eInNCCfg) | + LU_AOI_IN_CFG(LU_AOI_IN_N_D, pInitStruct->tAoi0Config.tIn1Config.eInNDCfg); + u32TempReg |= LU_AOI_IN_N_CFG(LU_AOI_IN_1, u32TempCfg); + + u32TempCfg = (uint32_t)0U | + LU_AOI_IN_CFG(LU_AOI_IN_N_A, pInitStruct->tAoi0Config.tIn2Config.eInNACfg) | + LU_AOI_IN_CFG(LU_AOI_IN_N_B, pInitStruct->tAoi0Config.tIn2Config.eInNBCfg) | + LU_AOI_IN_CFG(LU_AOI_IN_N_C, pInitStruct->tAoi0Config.tIn2Config.eInNCCfg) | + LU_AOI_IN_CFG(LU_AOI_IN_N_D, pInitStruct->tAoi0Config.tIn2Config.eInNDCfg); + u32TempReg |= LU_AOI_IN_N_CFG(LU_AOI_IN_2, u32TempCfg); + + u32TempCfg = (uint32_t)0U | + LU_AOI_IN_CFG(LU_AOI_IN_N_A, pInitStruct->tAoi0Config.tIn3Config.eInNACfg) | + LU_AOI_IN_CFG(LU_AOI_IN_N_B, pInitStruct->tAoi0Config.tIn3Config.eInNBCfg) | + LU_AOI_IN_CFG(LU_AOI_IN_N_C, pInitStruct->tAoi0Config.tIn3Config.eInNCCfg) | + LU_AOI_IN_CFG(LU_AOI_IN_N_D, pInitStruct->tAoi0Config.tIn3Config.eInNDCfg); + u32TempReg |= LU_AOI_IN_N_CFG(LU_AOI_IN_3, u32TempCfg); + /* set AOI0 value */ + LU_HWA_ConfigAOI0(pLu, pInitStruct->eLgNum, u32TempReg); + + u32TempCfg = (uint32_t)0U | + LU_AOI_IN_CFG(LU_AOI_IN_N_A, pInitStruct->tAoi1Config.tIn0Config.eInNACfg) | + LU_AOI_IN_CFG(LU_AOI_IN_N_B, pInitStruct->tAoi1Config.tIn0Config.eInNBCfg) | + LU_AOI_IN_CFG(LU_AOI_IN_N_C, pInitStruct->tAoi1Config.tIn0Config.eInNCCfg) | + LU_AOI_IN_CFG(LU_AOI_IN_N_D, pInitStruct->tAoi1Config.tIn0Config.eInNDCfg); + u32TempReg = (uint32_t)0U | LU_AOI_IN_N_CFG(LU_AOI_IN_0, u32TempCfg); + + u32TempCfg = (uint32_t)0U | + LU_AOI_IN_CFG(LU_AOI_IN_N_A, pInitStruct->tAoi1Config.tIn1Config.eInNACfg) | + LU_AOI_IN_CFG(LU_AOI_IN_N_B, pInitStruct->tAoi1Config.tIn1Config.eInNBCfg) | + LU_AOI_IN_CFG(LU_AOI_IN_N_C, pInitStruct->tAoi1Config.tIn1Config.eInNCCfg) | + LU_AOI_IN_CFG(LU_AOI_IN_N_D, pInitStruct->tAoi1Config.tIn1Config.eInNDCfg); + u32TempReg |= LU_AOI_IN_N_CFG(LU_AOI_IN_1, u32TempCfg); + + u32TempCfg = (uint32_t)0U | + LU_AOI_IN_CFG(LU_AOI_IN_N_A, pInitStruct->tAoi1Config.tIn2Config.eInNACfg) | + LU_AOI_IN_CFG(LU_AOI_IN_N_B, pInitStruct->tAoi1Config.tIn2Config.eInNBCfg) | + LU_AOI_IN_CFG(LU_AOI_IN_N_C, pInitStruct->tAoi1Config.tIn2Config.eInNCCfg) | + LU_AOI_IN_CFG(LU_AOI_IN_N_D, pInitStruct->tAoi1Config.tIn2Config.eInNDCfg); + u32TempReg |= LU_AOI_IN_N_CFG(LU_AOI_IN_2, u32TempCfg); + + u32TempCfg = (uint32_t)0U | + LU_AOI_IN_CFG(LU_AOI_IN_N_A, pInitStruct->tAoi1Config.tIn3Config.eInNACfg) | + LU_AOI_IN_CFG(LU_AOI_IN_N_B, pInitStruct->tAoi1Config.tIn3Config.eInNBCfg) | + LU_AOI_IN_CFG(LU_AOI_IN_N_C, pInitStruct->tAoi1Config.tIn3Config.eInNCCfg) | + LU_AOI_IN_CFG(LU_AOI_IN_N_D, pInitStruct->tAoi1Config.tIn3Config.eInNDCfg); + u32TempReg |= LU_AOI_IN_N_CFG(LU_AOI_IN_3, u32TempCfg); + /* set AOI1 value */ + LU_HWA_ConfigAOI1(pLu, pInitStruct->eLgNum, u32TempReg); + + /* force bypass mode */ + LU_HWA_SetLgBypassControl(pLu, pInitStruct->eLgNum, pInitStruct->eAoiMode); + /* set Flip-Flop mode configure */ + LU_HWA_SetLgFlipFlopMode(pLu, pInitStruct->eLgNum, pInitStruct->eFFMode); + u32TempCfg = 0U; + if (pInitStruct->tSyncCtrl.bInputNA) + { + u32TempCfg |= LU_SYNC_CONTROL_INPUT_N(1U, LU_INPUT_N_A); + } + if (pInitStruct->tSyncCtrl.bInputNB) + { + u32TempCfg |= LU_SYNC_CONTROL_INPUT_N(1U, LU_INPUT_N_B); + } + if (pInitStruct->tSyncCtrl.bInputNC) + { + u32TempCfg |= LU_SYNC_CONTROL_INPUT_N(1U, LU_INPUT_N_C); + } + if (pInitStruct->tSyncCtrl.bInputND) + { + u32TempCfg |= LU_SYNC_CONTROL_INPUT_N(1U, LU_INPUT_N_D); + } + /* set LG inputs synchronous control */ + LU_HWA_SetLgInputsSyncCtrl(pLu, pInitStruct->eLgNum, u32TempCfg); + + if (LU_JKFF_MODE == pInitStruct->eFFMode) + { + /* set LG output feedback override control */ + LU_HWA_SetLgFeedbackOverrideCtrl(pLu, pInitStruct->eLgNum, pInitStruct->eFbMode); + } + + if (LU_OUTPUT_INIT_DISABLE > pInitStruct->eFFInitValue) + { + if (LU_OUTPUT_INIT_ONE == pInitStruct->eFFInitValue) + { + /* Configure the output of flip-flop as "1" */ + LU_HWA_ConfigFlipFlopTo1(pLu, pInitStruct->eLgNum); + } + else + { + /* Configure the output of flip-flop as "0" */ + LU_HWA_ConfigFlipFlopTo0(pLu, pInitStruct->eLgNum); + } + /* Flip-Flop initial output enable control */ + LU_HWA_EnableControlFlipFlopInitOutput(pLu, pInitStruct->eLgNum); + } + + /* set input filter sample count for AOI0 */ + LU_HWA_SetAOI0InputFilterSampleCount(pLu, pInitStruct->eLgNum, (uint32_t)pInitStruct->u8Aoi0FiltCnt); + /* set input filter sample period for AOI0 */ + LU_HWA_SetAOI0InputFilterSamplePeriod(pLu, pInitStruct->eLgNum, (uint32_t)pInitStruct->u8Aoi0Period); + /* set input filter sample count for AOI1 */ + LU_HWA_SetAOI1InputFilterSampleCount(pLu, pInitStruct->eLgNum, (uint32_t)pInitStruct->u8Aoi1FiltCnt); + /* set input filter sample period for AOI0 */ + LU_HWA_SetAOI1InputFilterSamplePeriod(pLu, pInitStruct->eLgNum, (uint32_t)pInitStruct->u8Aoi1Period); + + return eRet; +} + +/** + * @brief De-initialize Lu instance + * @param eLu LU instance + */ +void LU_Deinit() +{ + uint8_t u8Index; + LU_Type* pLu = NULL_PTR; + + for (u8Index = 0U; u8Index < (uint8_t)LG_CNT; u8Index++) + { + /* set AOI0 value */ + LU_HWA_ConfigAOI0(pLu, (LU_LgType)u8Index, 0U); + /* set AOI1 value */ + LU_HWA_ConfigAOI1(pLu, (LU_LgType)u8Index, 0U); + /* set CTRL value */ + LU_HWA_ConfigCtrl(pLu, (LU_LgType)u8Index, 0U); + /* set FILT value */ + LU_HWA_ConfigFilter(pLu, (LU_LgType)u8Index, 0U); + } +} + + diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_mam.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_mam.c new file mode 100644 index 0000000..3ed3e5d --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_mam.c @@ -0,0 +1,259 @@ +/** + * @file fc7xxx_driver_mam.c + * @author Flagchip + * @brief FC7xxx MAM driver source code + * @version 0.1.0 + * @date 2023-02-08 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-10 Flagchip095 N/A First version for FC7240 + ******************************************************************************** */ + +#include "fc7xxx_driver_mam.h" +#include "interrupt_manager.h" + + +#define MAM0_MIN_ADDR 0x01000000U +#define MAM0_MAX_ADDR 0x4049FFFFU + +#define ROM_START_ADDR 0x04800000U +#define ROM_END_ADDR 0x0481FFFFU +#define ROM_BLOCK_SIZE 0x20000U + +#define FLASH0_START_ADDR 0x01000000U +#define FLASH0_END_ADDR 0x011FFFFFU +#define FLASH0_BLOCK_SIZE 0x20000U + +#define NVR_START_ADDR 0x04400000U +#define NVR_END_ADDR 0x04411FFFU +#define NVR_BLOCK_SIZE 0x20000U + +#define NVR_CFG_START_ADDR 0x04420000U +#define NVR_CFG_END_ADDR 0x04431FFFU +#define NVR_CFG_BLOCK_SIZE 0x20000U + +#define FLASH1_START_ADDR 0x04000000U +#define FLASH1_END_ADDR 0x0401FFFFU +#define FLASH1_BLOCK_SIZE 0x2000U + +#define SRAM_START_ADDR 0x21000000U +#define SRAM_END_ADDR 0x21017FFFU +#define SRAM_BLOCK_SIZE 0x4000U + +#define CPU0_DTCM_START_ADDR 0x20000000U +#define CPU0_DTCM_END_ADDR 0x2001FFFFU +#define CPU0_DTCM_BLOCK_SIZE 0x4000U + +#define CPU0_ITCM_START_ADDR 0x00000000U +#define CPU0_ITCM_END_ADDR 0x00007FFFU +#define CPU0_ITCM_BLOCK_SIZE 0x4000U + +#define AFCB0_START_ADDR 0x40000000U +#define AFCB0_END_ADDR 0x4009FFFFU +#define AFCB0_BLOCK_SIZE 0x1000U + +#define AFCB1_START_ADDR 0x40400000U +#define AFCB1_END_ADDR 0x4049FFFFU +#define AFCB1_BLOCK_SIZE 0x1000U + +/** + * @brief Get mam information according to the address + * + * @param u32Addr Input address + */ +static MAM_Inf_Type MAM_Get_MAM_Inf(uint32_t u32Addr); + + +/*************** Local Functions ***************/ +static MAM_Inf_Type MAM_Get_MAM_Inf(uint32_t u32Addr) +{ + MAM_Inf_Type inf = {.error = 0}; + if(MAM0_MIN_ADDR <= u32Addr && u32Addr < MAM0_MAX_ADDR) + { + if(ROM_START_ADDR == u32Addr) + { + inf.block_num = 0; + } + else if(FLASH0_START_ADDR <= u32Addr && u32Addr < FLASH0_END_ADDR) + { + if((u32Addr - FLASH0_START_ADDR)%FLASH0_BLOCK_SIZE == 0U) + { + inf.block_num = (u32Addr - FLASH0_START_ADDR) / FLASH0_BLOCK_SIZE + 1U; + } + else + { + inf.error = 1; + } + } + else if(NVR_START_ADDR <= u32Addr && u32Addr < NVR_END_ADDR) + { + if((u32Addr - NVR_START_ADDR)%NVR_BLOCK_SIZE == 0U) + { + inf.block_num = (u32Addr - NVR_START_ADDR) / NVR_BLOCK_SIZE + 17U; + } + else + { + inf.error = 1; + } + } + else if(NVR_CFG_START_ADDR <= u32Addr && u32Addr < NVR_CFG_END_ADDR) + { + if((u32Addr - NVR_CFG_START_ADDR)%NVR_CFG_BLOCK_SIZE == 0U) + { + inf.block_num = (u32Addr - NVR_CFG_START_ADDR) / NVR_CFG_BLOCK_SIZE + 18U; + } + else + { + inf.error = 1; + } + } + else if(FLASH1_START_ADDR <= u32Addr && u32Addr < FLASH1_END_ADDR) + { + if((u32Addr - FLASH1_START_ADDR)%FLASH1_BLOCK_SIZE == 0U) + { + inf.block_num = (u32Addr - FLASH1_START_ADDR) / FLASH1_BLOCK_SIZE + 19U; + } + else + { + inf.error = 1; + } + } + else if(SRAM_START_ADDR <= u32Addr && u32Addr < SRAM_END_ADDR) + { + if((u32Addr - SRAM_START_ADDR)%SRAM_BLOCK_SIZE == 0U) + { + inf.block_num = (u32Addr - SRAM_START_ADDR) / SRAM_BLOCK_SIZE + 35U; + } + else + { + inf.error = 1; + } + } + else if(CPU0_DTCM_START_ADDR <= u32Addr && u32Addr < CPU0_DTCM_END_ADDR) + { + if((u32Addr - CPU0_DTCM_START_ADDR)%SRAM_BLOCK_SIZE == 0U) + { + inf.block_num = (u32Addr - CPU0_DTCM_START_ADDR) / CPU0_DTCM_BLOCK_SIZE + 43U; + } + else + { + inf.error = 1; + } + } + else if(u32Addr < CPU0_ITCM_END_ADDR) + { + if((u32Addr - CPU0_ITCM_START_ADDR)%CPU0_ITCM_BLOCK_SIZE == 0U) + { + inf.block_num = (u32Addr - CPU0_ITCM_START_ADDR) / CPU0_ITCM_BLOCK_SIZE + 41U; + } + else + { + inf.error = 1; + } + } + else if(AFCB0_START_ADDR <= u32Addr && u32Addr < AFCB0_END_ADDR) + { + if((u32Addr - AFCB0_START_ADDR)%AFCB0_BLOCK_SIZE == 0U) + { + inf.block_num = (u32Addr - AFCB0_START_ADDR) / AFCB0_BLOCK_SIZE + 51U; + } + else + { + inf.error = 1; + } + } + else if(AFCB1_START_ADDR <= u32Addr && u32Addr < AFCB1_END_ADDR) + { + if((u32Addr - AFCB1_START_ADDR)%AFCB1_BLOCK_SIZE == 0U) + { + inf.block_num = (u32Addr - AFCB1_START_ADDR) / AFCB1_BLOCK_SIZE + 211U; + } + else + { + inf.error = 1; + } + } + else + { + inf.error = 1; + } + } + else + { + inf.error = 1; + } + return inf; +} + + +/***************** Global Functions *******************/ +uint8_t MAM_Config(MAM_Master_Type Master, uint32_t u32Addr, uint32_t u32Val) +{ + MAM_Inf_Type inf = MAM_Get_MAM_Inf(u32Addr); + uint32_t reg_idx = 0U; + uint32_t bit_idx = 0U; + uint8_t status = 0U; + if(inf.error == 1U) + { + status = 1; + } + else + { + reg_idx = inf.block_num / 8U + 47U*(uint32_t)Master; /* 371 block , 371/8 + 1*/ + bit_idx = inf.block_num % 8U; + Mam_HWA_Set_ACR(MAM, reg_idx, u32Val << (bit_idx * 4U)); + reg_idx = inf.block_num / 32U + 12U*(uint32_t)Master; /* 371 block , 371/32 + 1*/ + bit_idx = inf.block_num % 32U; + Mam_HWA_Set_ACLR(MAM, reg_idx, 1UL << bit_idx); + } + return status; +} + +uint8_t MAM_Enable_Wdg(MAM_Master_Type Master,uint32_t u32Addr) +{ + uint8_t status = 0U; + uint32_t bit_idx = 0U; + uint32_t regval = 0U; + MAM_Inf_Type inf = MAM_Get_MAM_Inf(u32Addr); + + if(Master >= MAM_MASTER_NUM || inf.error == 1U) + { + status = 1; + } + else + { + bit_idx = (uint32_t)Master; + regval = Mam_HWA_Get_Wdgctr(MAM); + regval |= 1UL << bit_idx; + Mam_HWA_Set_Wdgctr(MAM, regval); + } + return status; +} + +uint8_t MAM_Disable_Wdg(MAM_Master_Type Master,uint32_t u32Addr) +{ + uint8_t status = 0U; + uint32_t regval = 0U; + uint32_t bit_idx = 0U; + MAM_Inf_Type inf = MAM_Get_MAM_Inf(u32Addr); + + if(Master >= MAM_MASTER_NUM || inf.error == 1U) + { + status = 1; + } + else + { + bit_idx = (uint32_t)Master; + regval = Mam_HWA_Get_Wdgctr(MAM); + regval &= ~(1U << bit_idx); + Mam_HWA_Set_Wdgctr(MAM, regval); + } + return status; +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_mb.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_mb.c new file mode 100644 index 0000000..d93fce1 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_mb.c @@ -0,0 +1,456 @@ +/** + * @file fc7xxx_driver_mb.c + * @author Flagchip070 + * @brief FC7xxx Mailbox driver type definition and API + * @version 0.1.0 + * @date 2022-11-15 + * + * @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2022-11-15 Flagchip070 N/A First version for FC7300 + ******************************************************************************** */ + +#include "fc7xxx_driver_mb.h" + + +/********* Local variable ************/ +static uint32_t s_u32CoreIndex = MB_NOT_INIT; +static const uint8_t s_aMasterIdTab[MB_INT_CONFIG_COUNT] = { + 0u, 8u +}; + +static void (*s_pRequestCallback)(MB_ReceiveType *pReceive) = NULL; +static void (*s_pDoneCallback)(uint32_t u32ChannelMask) = NULL; + +/******* Local Function Prototype *********/ +static uint32_t core_id_2_index(uint32_t u32MasterId); +static uint8_t get_channel_status(uint32_t u32Channel); + +/** + * @brief Convert core master id to index + * + * @param u32MasterId Core master ID + * + */ +static uint32_t core_id_2_index(uint32_t u32MasterId) +{ + uint32_t u32Index = 0; + uint32_t u32Loop; + for(u32Loop = 0; u32Loop < MB_INT_CONFIG_COUNT; u32Loop++) + { + if(s_aMasterIdTab[u32Loop] == u32MasterId) + { + u32Index = u32Loop; + break; + } + } + return u32Index; +} + +/** + * @brief Get the master security information and processing mode of the channel + * + * @param u32Channel the selected MB channel + * + */ +static uint8_t get_channel_status(uint32_t u32Channel) +{ + uint8_t u8Status = 0; + if(0u == MB_HWA_GetSecure(u32Channel)) + { + u8Status |= MB_CHANNEL_STATUS_SECURE; + } + if(0u != MB_HWA_GetSupervisor(u32Channel)) + { + u8Status |= MB_CHANNEL_STATUS_PRIVILEGED; + } + return u8Status; +} + +/********* Global Functions ************/ + +/** + * @brief Get the index of the core + * + * @return uint32_t index of the core + */ +uint32_t MB_GetCoreIndex(void) +{ + return s_u32CoreIndex; +} + +/** + * @brief Initialize the Mailbox + * + * @param pInitConfig the configurations of the Mailbox + * @return MB_StatusType whether the operation is successfully + */ +MB_StatusType MB_Init(const MB_InitType *pInitConfig) +{ + MB_StatusType eStatus = MB_STATUS_SUCCESS; + if(MB_NOT_INIT != s_u32CoreIndex) + { + eStatus = MB_STATUS_ALREADY_INITED; + } + else + { + /* Get Core Index */ +#if defined(DEVICE_TYPE) && (DEVICE_TYPE == FC7XXXHSM) + s_u32CoreIndex = HSM_MAILBOX_CORE_INDEX; +#else + uint32_t u32CoreId; + uint32_t u32Index; + u32CoreId = (MCM->MICR & MCM_MICR_COREID_Msk) >> MCM_MICR_COREID_Pos; + for(u32Index = 0; u32Index < MB_INT_CONFIG_COUNT; u32Index++) + { + if(u32CoreId == s_aMasterIdTab[u32Index]) + { + s_u32CoreIndex = u32Index; + break; + } + } +#endif + if(MB_NOT_INIT != s_u32CoreIndex) + { + /*Registering callback functions*/ + s_pRequestCallback = pInitConfig->pRequestCallback; + s_pDoneCallback = pInitConfig->pDoneCallback; + /*Configure the event mask*/ + MB_HWA_ConfigFlagMask(s_u32CoreIndex, pInitConfig->u32EventMask); + /*Enable event interrupts */ + MB_HWA_ConfigIntrEnable(s_u32CoreIndex, pInitConfig->u32IntrMask); + } + else + { + eStatus = MB_STATUS_FAILED; + } + } + + return eStatus; +} + +/** + * @brief De-initialize the Mailbox + * + * @return MB_StatusType whether the operation is successfully + */ +MB_StatusType MB_DeInit(void) +{ + MB_StatusType eStatus = MB_STATUS_UNINIT; + if(MB_NOT_INIT != s_u32CoreIndex) + { + /*Disable all event interrupts and flag*/ + MB_HWA_ConfigFlagMask(s_u32CoreIndex, 0); + MB_HWA_ConfigIntrEnable(s_u32CoreIndex, 0); + s_u32CoreIndex = MB_NOT_INIT; + } + return eStatus; +} + +/** + * @brief Attempt to acquire a Mailbox channel + * + * @param u32Channel the selected Mailbox channel + * @return MB_StatusType whether the operation is successfully + */ +MB_StatusType MB_LockChannel(uint32_t u32Channel) +{ + MB_StatusType eStatus = MB_STATUS_SUCCESS; + uint32_t u32Lock; + + if(MB_NOT_INIT == s_u32CoreIndex) + { + eStatus = MB_STATUS_UNINIT; + } + else + { + if(u32Channel < MB_CHANNEL_CONFIG_COUNT) + { + /*Read SEMA to lock the selected channel*/ + u32Lock = MB_HWA_LockChannel(u32Channel); + if(0u == u32Lock) + { + eStatus = MB_STATUS_LOCKED; + } + } + else + { + eStatus = MB_STATUS_PARAM_ERROR; + } + } + return eStatus; +} + +/** + * @brief Release a Mailbox channel + * + * @param u32Channel the selected Mailbox channel + * @return MB_StatusType whether the operation is successfully + */ +MB_StatusType MB_ReleaseChannel(uint32_t u32Channel) +{ + MB_StatusType eStatus = MB_STATUS_SUCCESS; + uint32_t u32MasterId; + if(MB_NOT_INIT == s_u32CoreIndex) + { + eStatus = MB_STATUS_UNINIT; + } + else + { + if(u32Channel < MB_CHANNEL_CONFIG_COUNT) + { + /*Check the master core of the channel*/ + u32MasterId = MB_HWA_GetMasterID(u32Channel); + if(u32MasterId == s_aMasterIdTab[s_u32CoreIndex]) + { + /*Release the selected channel*/ + MB_HWA_ReleaseChannel(u32Channel); + } + else + { + eStatus = MB_STATUS_FAILED; + } + } + else + { + eStatus = MB_STATUS_PARAM_ERROR; + } + } + return eStatus; +} + +/** + * @brief Software clears channel lock + * + * @param u32Channel the selected Mailbox channel + * @return MB_StatusType whether the operation is successfully + */ +MB_StatusType MB_UnlockChannel(uint32_t u32Channel) +{ + MB_StatusType eStatus = MB_STATUS_SUCCESS; + if(MB_NOT_INIT == s_u32CoreIndex) + { + eStatus = MB_STATUS_UNINIT; + } + else + { + if(u32Channel < MB_CHANNEL_CONFIG_COUNT) + { + MB_HWA_UnlockChanne(u32Channel); + } + else + { + eStatus = MB_STATUS_PARAM_ERROR; + } + } + return eStatus; +} + +/** + * @brief Launching a Mailbox request + * + * @param pRequest Configuration of the request + * @return MB_StatusType whether the operation is successfully + */ +MB_StatusType MB_SendRequest(MB_RequestType *pRequest) +{ + MB_StatusType eStatus = MB_LockChannel(pRequest->u8Channel); + if(MB_STATUS_SUCCESS == eStatus) + { + if(pRequest->u8DoneMasterIndex < MB_INT_CONFIG_COUNT) + { + MB_HWA_ConfigDoneMasterId(pRequest->u8Channel, s_aMasterIdTab[pRequest->u8DoneMasterIndex]); + MB_HWA_ConfigDoneMask(pRequest->u8Channel, pRequest->u8DoneMask); + MB_HWA_ConfigAutoUnlock(pRequest->u8Channel, pRequest->u8AutoReleaseFlag); + MB_HWA_WriteData(pRequest->u8Channel, pRequest->aData); + MB_HWA_ConfigRequest(pRequest->u8Channel, pRequest->u8RequestMask); + } + else + { + eStatus = MB_STATUS_PARAM_ERROR; + } + } + return eStatus; +} + +/** + * @brief Attempt to receive a request from the selected channel + * + * @param pReceive Configuration of the receiving request + * @return MB_StatusType whether the operation is successfully + */ +MB_StatusType MB_ReceiveChannel(MB_ReceiveType *pReceive) +{ + MB_StatusType eStatus = MB_STATUS_SUCCESS; + uint32_t u32Flag; + if(MB_NOT_INIT == s_u32CoreIndex) + { + eStatus = MB_STATUS_UNINIT; + } + else if(pReceive->u8Channel < MB_CHANNEL_CONFIG_COUNT) + { + u32Flag = MB_HWA_GetFlag(s_u32CoreIndex, MB_EVENT_REQ(pReceive->u8Channel)); + if(0u != u32Flag) + { + /* Clear events flag */ + MB_HWA_ClearFlag(s_u32CoreIndex, u32Flag); + /* receiving data */ + MB_HWA_GetData(pReceive->u8Channel, pReceive->aData); + /* get the security information and processing mode */ + pReceive->u8ChannelStatus = get_channel_status(pReceive->u8Channel); + /*get the master core index of the request*/ + pReceive->u8MasterCoreIndex = (uint8_t)MB_HWA_GetMasterID(pReceive->u8Channel); + pReceive->u8MasterCoreIndex = (uint8_t)core_id_2_index((uint32_t)pReceive->u8MasterCoreIndex); + } + else + { + eStatus = MB_STATUS_NO_REQUEST; + } + } + else + { + eStatus = MB_STATUS_PARAM_ERROR; + } + return eStatus; +} + +/** + * @brief Issue a done event to the selected channel + * + * @param u32Channel the selected Mailbox channel + * @param u32DoneMask The mask for issuing done + * @return MB_StatusType whether the operation is successfully + */ +MB_StatusType MB_DoneChannel(uint32_t u32Channel, uint32_t u32DoneMask) +{ + MB_StatusType eStatus = MB_STATUS_SUCCESS; + uint32_t u32DoneMasterId, u32DoneMaskAllow; + if(MB_NOT_INIT == s_u32CoreIndex) + { + eStatus = MB_STATUS_UNINIT; + } + else if(u32Channel < MB_CHANNEL_CONFIG_COUNT) + { + /* Check the done master of the channel*/ + u32DoneMasterId = MB_HWA_GetDoneMasterId(u32Channel); + if(u32DoneMasterId == s_aMasterIdTab[s_u32CoreIndex]) + { + /* Check if the done mask is allowed */ + u32DoneMaskAllow = MB_HWA_GetDoneMask(u32Channel); + if((u32DoneMaskAllow & u32DoneMask) == u32DoneMask) + { + /* issue a done event */ + MB_HWA_SetDone(u32Channel, u32DoneMask); + } + else + { + eStatus = MB_STATUS_FAILED; + } + } + else + { + eStatus = MB_STATUS_FAILED; + } + } + else + { + eStatus = MB_STATUS_PARAM_ERROR; + } + return eStatus; +} + +/** + * @brief Polling the done event of all channels + * + * @param u32PollMask mask of the done event + * @param pDoneMask buffer to store the done events + * @return MB_StatusType whether the operation is successfully + */ +MB_StatusType MB_PollDone(uint32_t u32PollMask, uint32_t *pDoneMask) +{ + MB_StatusType eStatus = MB_STATUS_SUCCESS; + uint32_t u32Flag, u32Index; + *pDoneMask = 0; + + if(MB_NOT_INIT == s_u32CoreIndex) + { + eStatus = MB_STATUS_UNINIT; + } + else if(0u != u32PollMask) + { + for(u32Index = 0; u32Index < MB_CHANNEL_CONFIG_COUNT; u32Index++) + { + if(0u != (u32PollMask & ((uint32_t)1u << u32Index))) + { + u32Flag = MB_HWA_GetFlag(s_u32CoreIndex, MB_EVENT_DONE(u32Index)); + if(0u != u32Flag) + { + /* Clear done flag */ + MB_HWA_ClearFlag(s_u32CoreIndex, u32Flag); + /* store the done event */ + *pDoneMask |= (uint32_t)1u << u32Index; + } + } + } + } + else + { + eStatus = MB_STATUS_PARAM_ERROR; + } + return eStatus; +} + +/** + * @brief Interrupt IRQ handle of Mailbox + * + */ +void MB_IRQProcess(void) +{ + uint32_t u32FlagStat = MB_HWA_GetFlagStat(s_u32CoreIndex, MB_INTn_FLG_STAT_MASK); + uint32_t u32Index, u32MasterCore, u32ChannelMask = 0; + MB_ReceiveType tReceive; + + MB_HWA_ClearFlag(s_u32CoreIndex, u32FlagStat); + for(u32Index = 0; u32Index < MB_CHANNEL_CONFIG_COUNT; u32Index++) + { + /* get the master core index of the channel*/ + u32MasterCore = MB_HWA_GetMasterID(u32Index); + u32MasterCore = core_id_2_index(u32MasterCore); + if(0u != (u32FlagStat & ((uint32_t)1u << u32Index))) + { + /* request event */ + if(NULL != s_pRequestCallback) + { + tReceive.u8Channel = (uint8_t)u32Index; + tReceive.u8ChannelStatus = get_channel_status(u32Index); + tReceive.u8MasterCoreIndex = (uint8_t)u32MasterCore; + MB_HWA_GetData(u32Index, tReceive.aData); + /* call the request callback*/ + s_pRequestCallback(&tReceive); + } + } + if(0u != (u32FlagStat & ((uint32_t)1u << (u32Index + MB_INTn_FLG_STAT_FLG_DONE_INT_STAT_SHIFT)))) + { + u32ChannelMask |= (uint32_t)1u << u32Index; + /*done event*/ + if((0u == MB_HWA_GetAutoClear(u32Index, s_u32CoreIndex)) && (u32MasterCore == s_u32CoreIndex)) + { + /* if channel is not automatically clear, + * and master core is self, release the channel */ + MB_HWA_ReleaseChannel(u32Index); + } + } + } + + if((NULL != s_pDoneCallback) && (0u != u32ChannelMask)) + { + s_pDoneCallback(u32ChannelMask); + } +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_mpu.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_mpu.c new file mode 100644 index 0000000..a5e0cca --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_mpu.c @@ -0,0 +1,128 @@ +/** + * @file fc7xxx_driver_mpu.c + * @author Flagchip085 + * @brief FC7xxx MPU driver type definition and API + * @version 0.1.0 + * @date 2024-01-12 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + * @details The MPU only checks the CPU master access to CTCM and DTCM memory. When access denied, it will cause MemManage Interrupt. + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240 + ******************************************************************************** */ + +#include "fc7xxx_driver_mpu.h" + +void MPU_Disable(void) +{ + __DMB(); /* make sure outstanding transfers are done */ + MPU_HWA_Fault_Disable(); + MPU_HWA_Set_CR(0U); /* disable mpu and clear its control register*/ +} + +void MPU_Enable(MPU_EnableOptionType eOption) +{ + uint32_t u32Option; + + switch (eOption) + { + case MPU_EN_HARDFAULT_NMI: + u32Option = CORTEX_MPU_CTRL_HFNMIENA_MASK; + break; + + case MPU_EN_PRIVILEGED_DEFAULT: + u32Option = CORTEX_MPU_CTRL_RPRIVDEFENA_MASK; + break; + + case MPU_EN_HFNMI_PRIVDEF: + u32Option = (CORTEX_MPU_CTRL_HFNMIENA_MASK | CORTEX_MPU_CTRL_RPRIVDEFENA_MASK); + break; + + case MPU_EN_HFNMI_PRIVDEF_NONE: + u32Option = 0U; + break; + + default: + u32Option = 0U; + break; + } + MPU_HWA_Set_CR(CORTEX_MPU_CTRL_ENABLE_MASK | (((uint32_t)u32Option) & MPU_EN_MASK_U32)); + MPU_HWA_Fault_Enable(); /* mpu fault MemManage INT enable */ + __DSB(); + __ISB(); +} + +MPU_StatusType MPU_RegionDisable(MPU_RegionNumberType eRegion) +{ + MPU_HWA_Set_NR((uint8_t)eRegion); + MPU_HWA_Set_BAR(0x00U); + MPU_HWA_Set_ASR(0x00U); + + return MPU_STATUS_SUCCESS; +} + +MPU_StatusType MPU_RegionEnable(MPU_RegionNumberType eRegion, const MPU_RegionConfigurationType *pConfig) +{ + MPU_StatusType eRet = MPU_STATUS_SUCCESS; + uint32_t u32Srd; + uint32_t u32Asr; + + if ((NULL == pConfig) || + ((uint32_t)eRegion > (uint32_t)MPU_REGION_NUMBER_15) || + (0U != (pConfig->u32BaseAddr & MPU_RBAR_VALID_REGION_MASK_U32)) || + ((uint32_t)pConfig->eRegionSize < (uint32_t)MPU_REGION_SIZE_32B) || + ((uint32_t)pConfig->eRegionSize > (uint32_t)MPU_REGION_SIZE_4GB)) + { + eRet = MPU_STATUS_ERROR; + } + else + { + /* use bit shift is surely safe */ + u32Srd = (((((uint32_t)pConfig->eSubRegionDis_0) << 0) | + (((uint32_t)pConfig->eSubRegionDis_1) << 1) | + (((uint32_t)pConfig->eSubRegionDis_2) << 2) | + (((uint32_t)pConfig->eSubRegionDis_3) << 3) | + (((uint32_t)pConfig->eSubRegionDis_4) << 4) | + (((uint32_t)pConfig->eSubRegionDis_5) << 5) | + (((uint32_t)pConfig->eSubRegionDis_6) << 6) | + (((uint32_t)pConfig->eSubRegionDis_7) << 7)) & 0xFFU); + + u32Asr = CORTEX_MPU_RASR_XN(pConfig->eExecuteNever) | + CORTEX_MPU_RASR_AP(pConfig->eAccessPermission) | + CORTEX_MPU_RASR_TEX(pConfig->eTypeExtLevel) | + CORTEX_MPU_RASR_S(pConfig->eShareable) | + CORTEX_MPU_RASR_C(pConfig->eCacheable) | + CORTEX_MPU_RASR_B(pConfig->eBufferable) | + CORTEX_MPU_RASR_SRD(u32Srd) | + CORTEX_MPU_RASR_SIZE(pConfig->eRegionSize) | + CORTEX_MPU_RASR_ENABLE_MASK; + + MPU_HWA_Set_NR((uint8_t)eRegion); + MPU_HWA_Set_BAR(pConfig->u32BaseAddr & MPU_RBAR_BASEADDR_MASK_U32); /* ignore VALID and REGION bits */ + MPU_HWA_Set_ASR(u32Asr); + } + + return eRet; +} + + + + +MPU_StatusType MPU_CheckExist(void) +{ + uint32_t u32RegVal = MPU_HWA_Get_Type(); + MPU_StatusType eRet = MPU_STATUS_SUCCESS; + + if (0U == u32RegVal) + { + eRet = MPU_STATUS_ERROR; + } + + return eRet; +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_msc.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_msc.c new file mode 100644 index 0000000..51d411d --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_msc.c @@ -0,0 +1,569 @@ +/** + * @file fc7xxx_driver_msc.c + * @author Flagchip + * @brief FC7240 MSC driver type definition and API + * @version 0.1.0 + * @date 2024-01-10 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-10 Flagchip084 N/A FC7240 release version + ******************************************************************************** */ + +#include "fc7xxx_driver_msc.h" + +/* ################################################################################## */ +/* ####################################### Macro #################################### */ + +/* ################################################################################## */ +/* ################################### Type define ################################## */ + +/* ################################################################################## */ +/* ################################ Local Variables ################################# */ +static MSC_Type *const s_apMscBase[MSC_INSTANCE_COUNT] = MSC_BASE_PTRS; +static MSC_ISRCallbackType s_apMscRFISRCallback[MSC_INSTANCE_COUNT] = {NULL}; +static MSC_ISRCallbackType s_apMscTFISRCallback[MSC_INSTANCE_COUNT] = {NULL}; +static MSC_ISRCallbackType s_apMscCFISRCallback[MSC_INSTANCE_COUNT] = {NULL}; +static MSC_ISRCallbackType s_apMscDFISRCallback[MSC_INSTANCE_COUNT] = {NULL}; +static MSC_ISRCallbackType s_apMscTOISRCallback[MSC_INSTANCE_COUNT] = {NULL}; + +/* ################################################################################## */ +/* ########################### Local Prototype Functions ############################ */ +static void MSCn_IRQHandler(const MSC_InstanceType eInstance); +static void MSC_ClearReceiveInterruptFlag(const MSC_InstanceType eInstance); +static void MSC_ClearTimeFrameInterruptFlag(const MSC_InstanceType eInstance); +static void MSC_ClearCommandFrameInterruptFlag(const MSC_InstanceType eInstance); +static void MSC_ClearDataFrameInterruptFlag(const MSC_InstanceType eInstance); +/* ################################################################################## */ +/* ######################### Global prototype Functions ############################ */ +void MSC0_IRQHandler(void); +/* ################################################################################## */ +/* ################################ Local Functions ################################ */ +static void MSCn_IRQHandler(const MSC_InstanceType eInstance) +{ + uint32_t u32IntFlag = MSC_GetInterruptStatus(eInstance); + MSC_Type *const pMsc = s_apMscBase[eInstance]; + + if (u32IntFlag & MSC_INSR_RFI_MASK) + { + MSC_ClearReceiveInterruptFlag(eInstance); + if (MSC_HWA_GetRfieEnable(pMsc) && s_apMscRFISRCallback[eInstance] != NULL) + { + s_apMscRFISRCallback[eInstance](eInstance); + } + } + if (u32IntFlag & MSC_INSR_TFI_MASK) + { + MSC_ClearTimeFrameInterruptFlag(eInstance); + if (MSC_HWA_GetTfieEnable(pMsc) && s_apMscTFISRCallback[eInstance] != NULL) + { + s_apMscTFISRCallback[eInstance](eInstance); + } + } + if (u32IntFlag & MSC_INSR_CFI_MASK) + { + MSC_ClearCommandFrameInterruptFlag(eInstance); + if (MSC_HWA_GetCfieEnable(pMsc) && s_apMscCFISRCallback[eInstance] != NULL) + { + s_apMscCFISRCallback[eInstance](eInstance); + } + } + if (u32IntFlag & MSC_INSR_DFI_MASK) + { + MSC_ClearDataFrameInterruptFlag(eInstance); + if (MSC_HWA_GetDfieEnable(pMsc) && s_apMscDFISRCallback[eInstance] != NULL) + { + s_apMscDFISRCallback[eInstance](eInstance); + } + } + if (MSC_HWA_GetTofEnable(pMsc)) + { + MSC_HWA_ClearTofEnable(pMsc); + if (MSC_HWA_GetToieEnable(pMsc) && s_apMscTOISRCallback[eInstance] != NULL) + { + s_apMscTOISRCallback[eInstance](eInstance); + } + } +} +/* ################################################################################## */ +/* ################################ Global Functions ################################ */ + +void MSC0_IRQHandler(void) +{ + MSCn_IRQHandler(MSC_INSTANCE_0); +} + +MSC_ReturnType MSC_init(const MSC_InstanceType eInstance, const MSC_InitCfgType *pInitConfig) +{ + DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT); + DEV_ASSERT(pInitConfig != NULL); + + MSC_Type *const pMsc = s_apMscBase[eInstance]; + uint32_t u32TempValue; + uint32_t u32TimeoutCount = 0xFFFFFFU; + + if (pInitConfig->u8CommandBitLength > 32U || pInitConfig->u8SRLDataBitLength > 16U || pInitConfig->u8SRHDataBitLength > 16U) + { + return MSC_RETURN_E_PARAM; + } + + MSC_HWA_SetMsrRst(pMsc); + + while (MSC_HWA_GetMsrRdone(pMsc) == false) + { + u32TimeoutCount--; + if (u32TimeoutCount == 0U) + { + break; + } + } + + if (u32TimeoutCount == 0U) + { + return MSC_RETURN_E_NOT_OK; + } + + MSC_HWA_ClearMsrDone(pMsc); + + u32TempValue = MSC_TCCTR_PL(pInitConfig->u8PassiveLength) | MSC_TCCTR_WM(pInitConfig->eWorkMode) | MSC_TCCTR_SELH(pInitConfig->bSelSRH) | MSC_TCCTR_SELL(pInitConfig->bSelSRL) | + MSC_TCCTR_NBS(pInitConfig->u8CommandBitLength) | MSC_TCCTR_NHBS(pInitConfig->u8SRHDataBitLength) | MSC_TCCTR_NLBS(pInitConfig->u8SRLDataBitLength); + MSC_HWA_SetTcctr(pMsc, u32TempValue); + + MSC_HWA_SetNp(pMsc, pInitConfig->u8PTFNumber); + + u32TempValue = + MSC_RCCSR_RFT(pInitConfig->eRsvFrameType) | MSC_RCCSR_RBR(pInitConfig->eBaudRate) | MSC_RCCSR_PCTL(pInitConfig->eParity) | MSC_RCCSR_HIDC(pInitConfig->bDelayControl); + MSC_HWA_SetRccsr(pMsc, u32TempValue); + + return MSC_RETURN_OK; +} + +void MSC_initInterrupt(const MSC_InstanceType eInstance, const MSC_InterruptCfgType *pInteruptConfig) +{ + DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT); + DEV_ASSERT(pInteruptConfig != NULL); + uint32_t u32TempValue; + MSC_Type *const pMsc = s_apMscBase[eInstance]; + + u32TempValue = MSC_INCR_RFIE(pInteruptConfig->eRFIEMode) | MSC_INCR_TFIE(pInteruptConfig->bTFIntEnable) | MSC_INCR_CFIE(pInteruptConfig->bCFIntEnable) | + MSC_INCR_DFIE(pInteruptConfig->eDFIEMode); + MSC_HWA_SetIncr(pMsc, u32TempValue); + + u32TempValue = MSC_RTOR_TOIE(pInteruptConfig->bTOIntEnable) | MSC_RTOR_TOV(pInteruptConfig->u16TimeoutValue); + MSC_HWA_SetRtor(pMsc, u32TempValue); + + s_apMscRFISRCallback[eInstance] = pInteruptConfig->pReceiveFrameISRCallback; + s_apMscTFISRCallback[eInstance] = pInteruptConfig->pTimeFrameISRCallback; + s_apMscCFISRCallback[eInstance] = pInteruptConfig->pCommandFrameISRCallback; + s_apMscDFISRCallback[eInstance] = pInteruptConfig->pDataFrameISRCallback; + s_apMscTOISRCallback[eInstance] = pInteruptConfig->pReceiveTimeOutISRCallback; +} + +void MSC_SelTranmittingSource(const MSC_InstanceType eInstance, uint32_t u32SourceMask, MSC_TransSourceType eSourceType) +{ + DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT); + + MSC_Type *const pMsc = s_apMscBase[eInstance]; + uint32_t u32TempValue1 = 0; + uint16_t u32TempValue2; + uint8_t u8i; + + u32TempValue2 = (uint16_t)(u32SourceMask & 0xFFFFU); + + for (u8i = 0U; u8i < 16U; u8i++) + { + if ((u32TempValue2 & 0x01U) != 0U) + { + u32TempValue1 |= (uint32_t)eSourceType << (u8i << 1U); + } + u32TempValue2 = u32TempValue2 >> 1; + } + MSC_HWA_SetTcslr(pMsc, u32TempValue1); + + u32TempValue2 = (uint16_t)((u32SourceMask >> 16) & 0xFFFFU); + for (u8i = 0U; u8i < 16U; u8i++) + { + if ((u32TempValue2 & 0x01U) != 0U) + { + u32TempValue1 |= (uint32_t)eSourceType << (u8i << 1U); + } + u32TempValue2 = u32TempValue2 >> 1; + } + MSC_HWA_SetTcshr(pMsc, u32TempValue1); +} + +void MSC_SetEmergencyLoad(const MSC_InstanceType eInstance, uint32_t u32Value) +{ + DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT); + + MSC_Type *const pMsc = s_apMscBase[eInstance]; + + MSC_HWA_SetTcelr(pMsc, u32Value); +} + +void MSC_SetIOControl(const MSC_InstanceType eInstance, const MSC_IOControlInitType *pIOConfig) +{ + DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT); + + uint32_t u32TempValue = 0; + MSC_Type *const pMsc = s_apMscBase[eInstance]; + + u32TempValue |= MSC_IOCR_IDS(pIOConfig->eSDIsel); + u32TempValue |= MSC_IOCR_ESC(pIOConfig->eENCSel); + u32TempValue |= MSC_IOCR_ESH(pIOConfig->eENHSel); + u32TempValue |= MSC_IOCR_ESL(pIOConfig->eENLSel); + u32TempValue |= MSC_IOCR_FCLCTRL(pIOConfig->eFclCtrl); + u32TempValue |= MSC_IOCR_IPS(pIOConfig->eSDIPol); + u32TempValue |= MSC_IOCR_ENP(pIOConfig->eENXPol); + u32TempValue |= MSC_IOCR_SOP(pIOConfig->eSOPPol); + u32TempValue |= MSC_IOCR_FCLP(pIOConfig->eFCLPPol); + + MSC_HWA_SetIocr(pMsc, u32TempValue); +} + +void MSC_Enable(const MSC_InstanceType eInstance) +{ + DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT); + MSC_Type *const pMsc = s_apMscBase[eInstance]; + + MSC_HWA_SetMscEnable(pMsc, true); +} + +void MSC_Disable(const MSC_InstanceType eInstance) +{ + DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT); + MSC_Type *const pMsc = s_apMscBase[eInstance]; + + MSC_HWA_SetMscEnable(pMsc, false); +} + +void MSC_SetDataFrame(const MSC_InstanceType eInstance, uint32_t u32Data) +{ + DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT); + MSC_Type *const pMsc = s_apMscBase[eInstance]; + + MSC_HWA_SetTcdar(pMsc, u32Data); +} + +void MSC_SendDataFrame(const MSC_InstanceType eInstance) +{ + DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT); + MSC_Type *const pMsc = s_apMscBase[eInstance]; + MSC_HWA_SetDataNeedSend(pMsc); +} + +void MSC_SendCommandFrame(const MSC_InstanceType eInstance, uint32_t u32Command) +{ + DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT); + MSC_Type *const pMsc = s_apMscBase[eInstance]; + + MSC_HWA_SetTccor(pMsc, u32Command); +} + +uint8_t MSC_GetReceivedFrameAddr(const MSC_InstanceType eInstance, MSC_RDRxIndexType eIndex) +{ + DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT); + DEV_ASSERT(eIndex < MSC_RDRx_COUNT); + + MSC_Type *const pMsc = s_apMscBase[eInstance]; + uint8_t u8Addr = 0U; + + if (eIndex == MSC_RDR0) + { + u8Addr = MSC_HWA_GetRdr0Addr(pMsc); + } + else if (eIndex == MSC_RDR1) + { + u8Addr = MSC_HWA_GetRdr1Addr(pMsc); + } + else if (eIndex == MSC_RDR2) + { + u8Addr = MSC_HWA_GetRdr2Addr(pMsc); + } + else if (eIndex == MSC_RDR3) + { + u8Addr = MSC_HWA_GetRdr3Addr(pMsc); + } + else {} + + return u8Addr; +} + +MSC_ReceiveStatusType MSC_GetReceivedFrame(const MSC_InstanceType eInstance, MSC_RDRxIndexType eIndex, uint8_t *pData) +{ + DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT); + DEV_ASSERT(eIndex < MSC_RDRx_COUNT); + + MSC_Type *const pMsc = s_apMscBase[eInstance]; + MSC_ReceiveStatusType eRsvStatus = MSC_RSV_SUCCESS; + + if (eIndex == MSC_RDR0) + { + eRsvStatus = MSC_HWA_GetRdr0Rerr(pMsc); + if (MSC_RSV_SUCCESS == eRsvStatus) + { + *pData = MSC_HWA_GetRdr0Data(pMsc); + } + } + else if (eIndex == MSC_RDR1) + { + eRsvStatus = MSC_HWA_GetRdr1Rerr(pMsc); + if (MSC_RSV_SUCCESS == eRsvStatus) + { + *pData = MSC_HWA_GetRdr1Data(pMsc); + } + } + else if (eIndex == MSC_RDR2) + { + eRsvStatus = MSC_HWA_GetRdr2Rerr(pMsc); + if (MSC_RSV_SUCCESS == eRsvStatus) + { + *pData = MSC_HWA_GetRdr2Data(pMsc); + } + } + else if (eIndex == MSC_RDR3) + { + eRsvStatus = MSC_HWA_GetRdr3Rerr(pMsc); + if (MSC_RSV_SUCCESS == eRsvStatus) + { + *pData = MSC_HWA_GetRdr3Data(pMsc); + } + } + else {} + + return eRsvStatus; +} + +uint32_t MSC_GetInterruptStatus(const MSC_InstanceType eInstance) +{ + DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT); + + MSC_Type *const pMsc = s_apMscBase[eInstance]; + return MSC_HWA_GetInsr(pMsc); +} + +void MSC_EnableTrasmit(const MSC_InstanceType eInstance, bool bEnable) +{ + DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT); + + MSC_Type *const pMsc = s_apMscBase[eInstance]; + + if (bEnable) + { + MSC_HWA_ClearTcdis(pMsc); + } + else + { + MSC_HWA_SetTcdis(pMsc); + } +} + +void MSC_ClearReceiveInterruptFlag(const MSC_InstanceType eInstance) +{ + DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT); + + MSC_Type *const pMsc = s_apMscBase[eInstance]; + + MSC_HWA_ClearCrfi(pMsc); +} + +void MSC_ClearTimeFrameInterruptFlag(const MSC_InstanceType eInstance) +{ + DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT); + + MSC_Type *const pMsc = s_apMscBase[eInstance]; + + MSC_HWA_ClearCtfi(pMsc); +} + +void MSC_ClearCommandFrameInterruptFlag(const MSC_InstanceType eInstance) +{ + DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT); + + MSC_Type *const pMsc = s_apMscBase[eInstance]; + + MSC_HWA_ClearCcfi(pMsc); +} + +void MSC_ClearDataFrameInterruptFlag(const MSC_InstanceType eInstance) +{ + DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT); + + MSC_Type *const pMsc = s_apMscBase[eInstance]; + + MSC_HWA_ClearCdfi(pMsc); +} + +void MSC_EnableDataFrameInterrupt(const MSC_InstanceType eInstance, bool bEnable) +{ + DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT); + + MSC_Type *const pMsc = s_apMscBase[eInstance]; + + MSC_HWA_SetDfieEnable(pMsc, bEnable); +} + +void MSC_EnableCommandFrameInterrupt(const MSC_InstanceType eInstance, bool bEnable) +{ + DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT); + + MSC_Type *const pMsc = s_apMscBase[eInstance]; + + MSC_HWA_SetCfieEnable(pMsc, bEnable); +} + +void MSC_EnableTimeFrameInterrupt(const MSC_InstanceType eInstance, bool bEnable) +{ + DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT); + + MSC_Type *const pMsc = s_apMscBase[eInstance]; + + MSC_HWA_SetTfieEnable(pMsc, bEnable); +} + +void MSC_EnableReceiveInterrupt(const MSC_InstanceType eInstance, bool bEnable) +{ + DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT); + + MSC_Type *const pMsc = s_apMscBase[eInstance]; + + MSC_HWA_SetRfieEnable(pMsc, bEnable); +} + +void MSC_EnableTimeoutInterrupt(const MSC_InstanceType eInstance, bool bEnable) +{ + DEV_ASSERT((uint8_t)eInstance < MSC_INSTANCE_COUNT); + + MSC_Type *const pMsc = s_apMscBase[eInstance]; + + MSC_HWA_SetToieEnable(pMsc, bEnable); +} + +MSC_ReturnType Msc_SwitchENXChannel(const MSC_InstanceType eInstance, Msc_ENxType eEnx, Msc_ENxActiveType eENn, uint32_t u32TimeoutLoops) +{ + MSC_ReturnType eTempReturn = MSC_RETURN_E_NOT_OK; + uint32 u32TempValue; + uint32 u32TempTryCount = 0u; + uint8 u8CmdNeedSend; + uint8 u8CmdFrameBusy; + uint8 u8DataNeedSend; + uint8 u8DataFrameBusy; + MSC_Type *const pMsc = s_apMscBase[eInstance]; + + if (eEnx == MSC_ENC) + { + do + { + u8CmdFrameBusy = MSC_HWA_GetCfb(pMsc); + u8CmdNeedSend = MSC_HWA_GetCmdNeedSend(pMsc); + + if ((u8CmdNeedSend == TRUE) || (u8CmdFrameBusy == TRUE)) + { + u32TempValue = TRUE; + } + else + { + u32TempValue = FALSE; + } + + /* check receive rc flag */ + if (u32TempValue == FALSE) + { + break; + } + else + { + u32TempTryCount++; + } + } while (u32TempTryCount < u32TimeoutLoops); + + if (u32TempTryCount != u32TimeoutLoops) + { + u32TempValue = (MSC_HWA_GetIocr(pMsc) & ~MSC_IOCR_ESC_MASK) | MSC_IOCR_ESC(eENn); + MSC_HWA_SetIocr(pMsc, u32TempValue); + eTempReturn = MSC_RETURN_OK; + } + } + else + { + do + { + u8DataFrameBusy = MSC_HWA_GetDfb(pMsc); + u8DataNeedSend = MSC_HWA_GetDataNeedSend(pMsc); + + if ((u8DataFrameBusy == TRUE) || (u8DataNeedSend == TRUE)) + { + u32TempValue = TRUE; + } + else + { + u32TempValue = FALSE; + } + + /* check receive rc flag */ + if (u32TempValue == FALSE) + { + break; + } + else + { + u32TempTryCount++; + } + } while (u32TempTryCount < u32TimeoutLoops); + + if (u32TempTryCount != u32TimeoutLoops) + { + if (eEnx == MSC_ENH) + { + u32TempValue = (MSC_HWA_GetIocr(pMsc) & ~MSC_IOCR_ESH_MASK) | MSC_IOCR_ESH(eENn); + MSC_HWA_SetIocr(pMsc, u32TempValue); + } + else + { + u32TempValue = (MSC_HWA_GetIocr(pMsc) & ~MSC_IOCR_ESL_MASK) | MSC_IOCR_ESL(eENn); + MSC_HWA_SetIocr(pMsc, u32TempValue); + } + eTempReturn = MSC_RETURN_OK; + } + } + + return eTempReturn; +} + +MSC_ReturnType Msc_SwitchSDIChannel(const MSC_InstanceType eInstance, MSC_SDISelectionType eSDIChannel, uint32_t u32TimeoutLoops) +{ + MSC_ReturnType eTempReturn = MSC_RETURN_E_NOT_OK; + uint32_t u32TempValue; + uint32_t u32TempTryCount = 0u; + MSC_Type *const pMsc = s_apMscBase[eInstance]; + + do + { + u32TempValue = MSC_HWA_GetRxBusy(pMsc); + + /* check receive rc flag */ + if (u32TempValue == 0U) + { + break; + } + else + { + u32TempTryCount++; + } + } while (u32TempTryCount < u32TimeoutLoops); + + if (u32TempTryCount != u32TimeoutLoops) + { + u32TempValue = (MSC_HWA_GetIocr(pMsc) & ~MSC_IOCR_IDS_MASK) | MSC_IOCR_IDS(eSDIChannel); + MSC_HWA_SetIocr(pMsc, u32TempValue); + + eTempReturn = MSC_RETURN_OK; + } + return eTempReturn; +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_overlay.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_overlay.c new file mode 100644 index 0000000..744dfbb --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_overlay.c @@ -0,0 +1,498 @@ +/** + * @file fc7xxx_driver_overlay.c + * @author Flagchip + * @brief FC7xxx overlay driver type definition and API + * @version 0.1.0 + * @date 2023-12-25 + * + * @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. + * + */ + +/******************************************************************************** +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2023-12-25 Flagchip0038 N/A First version for FC7240 +********************************************************************************/ + +#include "fc7xxx_driver_overlay.h" + +typedef void (*Void_Type)(void); +typedef void (*U32_Type)(uint32_t u32Data); +typedef void (*SizeEnum_Type)(OVERLAY_OverlaySizeType eSize); + +static Void_Type const s_aRegionEnDisable[OVERLYA_REGION_CNT] = +{ + OVERLAY_HWA_OverlayRegion0Disable, + OVERLAY_HWA_OverlayRegion1Disable, + OVERLAY_HWA_OverlayRegion2Disable +}; + + +static Void_Type const s_aRegionEnEnable[OVERLYA_REGION_CNT] = +{ + OVERLAY_HWA_OverlayRegion0Enable, + OVERLAY_HWA_OverlayRegion1Enable, + OVERLAY_HWA_OverlayRegion2Enable +}; + +static U32_Type const s_aRegionSrc[OVERLYA_REGION_CNT] = +{ + OVERLAY_HWA_SetOverlayRegion0Src, + OVERLAY_HWA_SetOverlayRegion1Src, + OVERLAY_HWA_SetOverlayRegion2Src +}; + +static U32_Type const s_aRegionDst[OVERLYA_REGION_CNT] = +{ + OVERLAY_HWA_SetOverlayRegion0Dst, + OVERLAY_HWA_SetOverlayRegion1Dst, + OVERLAY_HWA_SetOverlayRegion2Dst +}; + +static SizeEnum_Type const s_aRegionSize[OVERLYA_REGION_CNT] = +{ + OVERLAY_HWA_SetOverlayRegion0Size, + OVERLAY_HWA_SetOverlayRegion1Size, + OVERLAY_HWA_SetOverlayRegion2Size +}; + +static OVERLAY_ErrorCallback_Type s_tErrorCallbackFunc; + +/** + * @brief Overlay region initial function + * + * @param pOverlayInitCfg initial parameters + * @return ERROR_OK is ok, others are not ok + */ +OVERLAY_ErrorType OVERLAY_RegionInit(OVERLAY_OverlayRegionInitType *pOverlayInitCfg) +{ + OVERLAY_ErrorType eRetval; + uint32_t u32Index; + uint32_t u32ErrorInfo; + + eRetval = OVERLAY_ERROR_OK; + + /* global overlay Disable */ + OVERLAY_HWA_OverlayDisable(); + + /* loop all region */ + for (u32Index = 0U; (u32Index < OVERLYA_REGION_CNT) && (eRetval == OVERLAY_ERROR_OK); u32Index++) + { + /* check overlay region enable */ + if (pOverlayInitCfg->aOverlayRegionEn[u32Index]) + { + if ((pOverlayInitCfg->aOverlayRegionSrc[u32Index] >= PFLASH_START) && + (pOverlayInitCfg->aOverlayRegionSrc[u32Index] <= PFLASH_END) && + (pOverlayInitCfg->aOverlayRegionDst[u32Index] >= SRAM_START) && + (pOverlayInitCfg->aOverlayRegionDst[u32Index] <= SRAM_END) + ) + { + + /* disable region n */ + s_aRegionEnDisable[u32Index](); + + /* source */ + s_aRegionSrc[u32Index](pOverlayInitCfg->aOverlayRegionSrc[u32Index]); + + /* dest */ + s_aRegionDst[u32Index](pOverlayInitCfg->aOverlayRegionDst[u32Index]); + + /* size */ + s_aRegionSize[u32Index](pOverlayInitCfg->aOverlayRegionSize[u32Index]); + + /* enable region n */ + s_aRegionEnEnable[u32Index](); + } + else + { + eRetval = OVERLAY_ERROR_ADDR; + } + } + else + { + /* disable region n */ + s_aRegionEnDisable[u32Index](); + } + + } + + if (eRetval == OVERLAY_ERROR_OK) + { + /* global overlay enable */ + OVERLAY_HWA_OverlayEnable(); + } + + /* check error flag */ + u32ErrorInfo = OVERLAY_HWA_GetErrorFlag(); + if (u32ErrorInfo) + { + eRetval = OVERLAY_ERROR_FLAG; + } + + return eRetval; +} + +/** + * @brief De-Init Overlay Region + * + * @return ERROR_OK is ok, others are not ok + */ +OVERLAY_ErrorType OVERLAY_RegionDeInit(void) +{ + OVERLAY_ErrorType eRetval; + uint32_t u32Index; + + eRetval = OVERLAY_ERROR_OK; + + /* disable global overlay */ + OVERLAY_HWA_OverlayDisable(); + + for (u32Index = 0U; u32Index < OVERLYA_REGION_CNT; u32Index++) + { + /* disable region n */ + s_aRegionEnDisable[u32Index](); + + /* source */ + s_aRegionSrc[u32Index](0U); + + /* dest */ + s_aRegionDst[u32Index](0U); + + /* size */ + s_aRegionSize[u32Index](OVERLAY_OVERLAYSIZE_1KB); + } + + return eRetval; +} + + +/** + * @brief Far initial function + * + * @param pFarInitCfg initial parameters + * @return ERROR_OK is ok, others are not ok + */ +OVERLAY_ErrorType OVERLAY_FARInit(OVERLAY_FARInitType *pFarInitCfg) +{ + OVERLAY_ErrorType eRetval; + uint32_t u32ErrorInfo; + + eRetval = OVERLAY_ERROR_OK; + + if (pFarInitCfg->u32FAREn == 0U) + { + + /* disable far */ + OVERLAY_HWA_FARDisable(); + } + else + { + /* must align to 64KB, */ + if ((pFarInitCfg->u32FARSize <= OVERLAY_FAR_SIZE_MAX) && + ((pFarInitCfg->u32FARSize & OVERLAY_FAR_SIZE_MASK) == 0U) + ) + { + if ((pFarInitCfg->u32FARDst >= PFLASH_START) && + (pFarInitCfg->u32FARDst <= PFLASH_END) + ) + { + /* disable far */ + OVERLAY_HWA_FARDisable(); + + /* set far dest */ + OVERLAY_HWA_SetFarDst(pFarInitCfg->u32FARDst); + /* set far size */ + OVERLAY_HWA_SetFarSize(pFarInitCfg->u32FARSize / OVERLAY_FAR_SIZE_ALIGN - 1); + /* disable enable */ + OVERLAY_HWA_FAREnable(); + } + else + { + eRetval = OVERLAY_ERROR_ADDR; + } + } + else + { + eRetval = OVERLAY_ERROR_SIZE; + } + } + + if (eRetval == OVERLAY_ERROR_OK) + { + /* enable far */ + OVERLAY_HWA_FAREnable(); + } + + + /* check error flag */ + u32ErrorInfo = OVERLAY_HWA_GetErrorFlag(); + if (u32ErrorInfo) + { + eRetval = OVERLAY_ERROR_FLAG; + } + + + return eRetval; +} + +/** + * @brief De-Init FAR Region + * + * @return ERROR_OK is ok, others are not ok + */ +OVERLAY_ErrorType OVERLAY_FARDeInit(void) +{ + OVERLAY_ErrorType eRetval; + + eRetval = OVERLAY_ERROR_OK; + + /* disable global far */ + OVERLAY_HWA_FARDisable(); + + /* set far dest */ + OVERLAY_HWA_SetFarDst(0x01000000U); + /* set far size */ + OVERLAY_HWA_SetFarSize(0U); + + return eRetval; +} + +/** + * @brief Enable or Disable Interrupt + * + * @param pInterruptCfg interrupt config parameter + */ +void OVERLAY_SetInterrupt(OVERLAY_InterruptType *pInterruptCfg) +{ + if (pInterruptCfg->bEnableInterrupt) + { + OVERLAY_HWA_ErrorInterruptEnable(); + s_tErrorCallbackFunc = pInterruptCfg->pCallBack; + } + else + { + OVERLAY_HWA_ErrorInterruptDisable(); + s_tErrorCallbackFunc = NULL; + } + +} + +/** + * @brief Get Error Info + * + * @param pErrorInfo error info point + */ +void OVERLAY_GetErrorInfo(OVERLAY_ErrorInfoType *pErrorInfo) +{ + uint32_t u32ErrorInfo; + u32ErrorInfo = OVERLAY_HWA_GetErrorFlag(); + + if (u32ErrorInfo & AHB_OVERLAY_INTR_FLAG_FAR_SIZE_INTR_MASK) + { + pErrorInfo->bError_FAR_SIZE_INTR = 1U; + } + else + { + pErrorInfo->bError_FAR_SIZE_INTR = 0U; + } + + if (u32ErrorInfo & AHB_OVERLAY_INTR_FLAG_FAR_DST_OVERFLOW_INTR_MASK) + { + pErrorInfo->bError_FAR_DST_OVERFLOW_INTR = 1U; + } + else + { + pErrorInfo->bError_FAR_DST_OVERFLOW_INTR = 0U; + } + + if (u32ErrorInfo & AHB_OVERLAY_INTR_FLAG_FAR_DST_NO_FLASH_INTR_MASK) + { + pErrorInfo->bError_FAR_DST_NO_FLASH_INTR = 1U; + } + else + { + pErrorInfo->bError_FAR_DST_NO_FLASH_INTR = 0U; + } + + if (u32ErrorInfo & AHB_OVERLAY_INTR_FLAG_REGION2_D_CROS_INTR_MASK) + { + pErrorInfo->bError_REGION2_D_CROS_INTR = 1U; + } + else + { + pErrorInfo->bError_REGION2_D_CROS_INTR = 0U; + } + + if (u32ErrorInfo & AHB_OVERLAY_INTR_FLAG_REGION2_S_CROS_INTR_MASK) + { + pErrorInfo->bError_REGION2_S_CROS_INTR = 1U; + } + else + { + pErrorInfo->bError_REGION2_S_CROS_INTR = 0U; + } + + if (u32ErrorInfo & AHB_OVERLAY_INTR_FLAG_REGION2_SIZE_INTR_MASK) + { + pErrorInfo->bError_REGION2_SIZE_INTR = 1U; + } + else + { + pErrorInfo->bError_REGION2_SIZE_INTR = 0U; + } + + if (u32ErrorInfo & AHB_OVERLAY_INTR_FLAG_REGION2_DST_INTR_MASK) + { + pErrorInfo->bError_REGION2_DST_INTR = 1U; + } + else + { + pErrorInfo->bError_REGION2_DST_INTR = 0U; + } + + if (u32ErrorInfo & AHB_OVERLAY_INTR_FLAG_REGION2_SRC_INTR_MASK) + { + pErrorInfo->bError_REGION2_SRC_INTR = 1U; + } + else + { + pErrorInfo->bError_REGION2_SRC_INTR = 0U; + } + + if (u32ErrorInfo & AHB_OVERLAY_INTR_FLAG_REGION1_D_CROS_INTR_MASK) + { + pErrorInfo->bError_REGION1_D_CROS_INTR = 1U; + } + else + { + pErrorInfo->bError_REGION1_D_CROS_INTR = 0U; + } + + if (u32ErrorInfo & AHB_OVERLAY_INTR_FLAG_REGION1_S_CROS_INTR_MASK) + { + pErrorInfo->bError_REGION1_S_CROS_INTR = 1U; + } + else + { + pErrorInfo->bError_REGION1_S_CROS_INTR = 0U; + } + + if (u32ErrorInfo & AHB_OVERLAY_INTR_FLAG_REGION1_SIZE_INTR_MASK) + { + pErrorInfo->bError_REGION1_SIZE_INTR = 1U; + } + else + { + pErrorInfo->bError_REGION1_SIZE_INTR = 0U; + } + + if (u32ErrorInfo & AHB_OVERLAY_INTR_FLAG_REGION1_DST_INTR_MASK) + { + pErrorInfo->bError_REGION1_DST_INTR = 1U; + } + else + { + pErrorInfo->bError_REGION1_DST_INTR = 0U; + } + + if (u32ErrorInfo & AHB_OVERLAY_INTR_FLAG_REGION1_SRC_INTR_MASK) + { + pErrorInfo->bError_REGION1_SRC_INTR = 1U; + } + else + { + pErrorInfo->bError_REGION1_SRC_INTR = 0U; + } + + if (u32ErrorInfo & AHB_OVERLAY_INTR_FLAG_REGION0_D_CROS_INTR_MASK) + { + pErrorInfo->bError_REGION0_D_CROS_INTR = 1U; + } + else + { + pErrorInfo->bError_REGION0_D_CROS_INTR = 0U; + } + + if (u32ErrorInfo & AHB_OVERLAY_INTR_FLAG_REGION0_S_CROS_INTR_MASK) + { + pErrorInfo->bError_REGION0_S_CROS_INTR = 1U; + } + else + { + pErrorInfo->bError_REGION0_S_CROS_INTR = 0U; + } + + if (u32ErrorInfo & AHB_OVERLAY_INTR_FLAG_REGION0_SIZE_INTR_MASK) + { + pErrorInfo->bError_REGION0_SIZE_INTR = 1U; + } + else + { + pErrorInfo->bError_REGION0_SIZE_INTR = 0U; + } + + if (u32ErrorInfo & AHB_OVERLAY_INTR_FLAG_REGION0_DST_INTR_MASK) + { + pErrorInfo->bError_REGION0_DST_INTR = 1U; + } + else + { + pErrorInfo->bError_REGION0_DST_INTR = 0U; + } + + if (u32ErrorInfo & AHB_OVERLAY_INTR_FLAG_REGION0_SRC_INTR_MASK) + { + pErrorInfo->bError_REGION0_SRC_INTR = 1U; + } + else + { + pErrorInfo->bError_REGION0_SRC_INTR = 0U; + } +} + +/** + * @brief Clear Error Info + * + * @param pErrorInfo error info point + */ +void OVERLAY_ClrErrorInfo(OVERLAY_ErrorInfoType *pErrorInfo) +{ + uint32_t u32ErrorInfo; + + u32ErrorInfo = AHB_OVERLAY_INTR_FLAG_FAR_SIZE_INTR(pErrorInfo->bError_FAR_SIZE_INTR); + u32ErrorInfo |= AHB_OVERLAY_INTR_FLAG_FAR_DST_OVERFLOW_INTR(pErrorInfo->bError_FAR_DST_OVERFLOW_INTR); + u32ErrorInfo |= AHB_OVERLAY_INTR_FLAG_FAR_DST_NO_FLASH_INTR(pErrorInfo->bError_FAR_DST_NO_FLASH_INTR); + u32ErrorInfo |= AHB_OVERLAY_INTR_FLAG_REGION2_D_CROS_INTR(pErrorInfo->bError_REGION2_D_CROS_INTR); + u32ErrorInfo |= AHB_OVERLAY_INTR_FLAG_REGION2_S_CROS_INTR(pErrorInfo->bError_REGION2_S_CROS_INTR); + u32ErrorInfo |= AHB_OVERLAY_INTR_FLAG_REGION2_SIZE_INTR(pErrorInfo->bError_REGION2_SIZE_INTR); + u32ErrorInfo |= AHB_OVERLAY_INTR_FLAG_REGION2_DST_INTR(pErrorInfo->bError_REGION2_DST_INTR); + u32ErrorInfo |= AHB_OVERLAY_INTR_FLAG_REGION2_SRC_INTR(pErrorInfo->bError_REGION2_SRC_INTR); + u32ErrorInfo |= AHB_OVERLAY_INTR_FLAG_REGION1_D_CROS_INTR(pErrorInfo->bError_REGION1_D_CROS_INTR); + u32ErrorInfo |= AHB_OVERLAY_INTR_FLAG_REGION1_S_CROS_INTR(pErrorInfo->bError_REGION1_S_CROS_INTR); + u32ErrorInfo |= AHB_OVERLAY_INTR_FLAG_REGION1_SIZE_INTR(pErrorInfo->bError_REGION1_SIZE_INTR); + u32ErrorInfo |= AHB_OVERLAY_INTR_FLAG_REGION1_DST_INTR(pErrorInfo->bError_REGION1_DST_INTR); + u32ErrorInfo |= AHB_OVERLAY_INTR_FLAG_REGION1_SRC_INTR(pErrorInfo->bError_REGION1_SRC_INTR); + u32ErrorInfo |= AHB_OVERLAY_INTR_FLAG_REGION0_D_CROS_INTR(pErrorInfo->bError_REGION0_D_CROS_INTR); + u32ErrorInfo |= AHB_OVERLAY_INTR_FLAG_REGION0_S_CROS_INTR(pErrorInfo->bError_REGION0_S_CROS_INTR); + u32ErrorInfo |= AHB_OVERLAY_INTR_FLAG_REGION0_SIZE_INTR(pErrorInfo->bError_REGION0_SIZE_INTR); + u32ErrorInfo |= AHB_OVERLAY_INTR_FLAG_REGION0_DST_INTR(pErrorInfo->bError_REGION0_DST_INTR); + u32ErrorInfo |= AHB_OVERLAY_INTR_FLAG_REGION0_SRC_INTR(pErrorInfo->bError_REGION0_SRC_INTR); + + OVERLAY_HWA_ClrErrorFlag(u32ErrorInfo); +} +/** + * @brief Call Me in Overlay Error interrupt handler + * + */ +void OVERLAY_ErrorInterruptRoutine(void) +{ + OVERLAY_ErrorInfoType tErrorInfo; + if (s_tErrorCallbackFunc != NULL) + { + OVERLAY_GetErrorInfo(&tErrorInfo); + s_tErrorCallbackFunc(tErrorInfo); + } +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_pcc.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_pcc.c new file mode 100644 index 0000000..61c9638 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_pcc.c @@ -0,0 +1,421 @@ +/** + * @file fc7xxx_driver_pcc.c + * @author Flagchip + * @brief FC7xxx PCC driver type definition and API + * @version 0.1.0 + * @date 2024-01-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ + +/******************************************************************************** +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240 +********************************************************************************/ + +#include "fc7xxx_driver_pcc.h" +#include "fc7xxx_driver_scg.h" +#include "fc7xxx_board_conf.h" + +/***************** mcaro *********************/ +/* PCC property MACRO, defines every peripheral clock system architecture */ +#define PCC_CLK_NOT_APPLY (0U) +#define PCC_CGC_AVAILABLE (1U << 0U) +#define PCC_FUNCCLK_MUXDIVH_USED (1U << 1U) +#define PCC_FUNCCLK_MUXDIVM_USED (1U << 2U) +#define PCC_FUNCCLK_MUXDIVL_USED (1U << 3U) +#define PCC_FUNCCLK_MUXDIVHPIN_USED (1U << 4U) +#define PCC_MOUDULE_DIV_USED (1U << 5U) +#define PCC_CLK_DOMAIN_CORE (1U << 6U) +#define PCC_CLK_DOMAIN_BUS (1U << 7U) +#define PCC_CLK_DOMAIN_SLOW (1U << 8U) +#define PCC_DWP_SWR_AVAILABLE (0U << 9U) + +#define PCC_PROPERTY_MUXDIV_MASK (PCC_FUNCCLK_MUXDIVH_USED | PCC_FUNCCLK_MUXDIVM_USED | PCC_FUNCCLK_MUXDIVL_USED) +#define PCC_PROPERTY_MUXDIV_ALL_MASK (PCC_FUNCCLK_MUXDIVH_USED | PCC_FUNCCLK_MUXDIVM_USED | PCC_FUNCCLK_MUXDIVL_USED | PCC_FUNCCLK_MUXDIVHPIN_USED) + +/***************** Type define *********************/ +/** + * @brief PCC clock attribution. + * @param u32RegOffset: the register offset base on PCC module base address 0x4002_4000h + * @param u8ClockProperty include clock domain and clock MUX information by bit filed setting. + */ +typedef struct +{ + uint32_t u32RegOffset; + uint32_t u32ClockProperty; +} PCC_ClockMapType; + +/** + * @brief PCC peripheral clock index map to SCG clock source + * @param ePccClkIndex: PCC peripheral clock index + * @param eScgClkIndex SCG clock source + */ +typedef struct +{ + PCC_ClkGateSrcType ePccClkIndex; + SCG_ClkSrcType eScgClkIndex; +} PCC_ClockIndexMap; + +/***************** Local Variables *********************/ +/** + * @brief PCC clock index to SCG clock source map. +*/ +static const PCC_ClockIndexMap s_tPccClocIndexkMap[PCC_MUX_MAX_NUMBER] = { + {PCC_CLKGATE_SRC_OFF_OR_TCLK, SCG_END_OF_CLOCKS}, + {PCC_CLKGATE_SRC_FOSCDIV, SCG_FOSCDIVH_CLK}, + {PCC_CLKGATE_SRC_SIRCDIV, SCG_SIRCDIVH_CLK}, + {PCC_CLKGATE_SRC_FIRCDIV, SCG_FIRCDIVH_CLK}, + {PCC_CLKGATE_SRC_RESERVE0, SCG_END_OF_CLOCKS}, + {PCC_CLKGATE_SRC_PLL1DIV, SCG_PLL1DIVH_CLK}, + {PCC_CLKGATE_SRC_PLL0DIV, SCG_PLL0DIVH_CLK}, + {PCC_CLKGATE_SRC_RESERVE1, SCG_END_OF_CLOCKS} +}; + +/** + * @brief clock attribution map. + */ +static const PCC_ClockMapType s_tPccClockMap[PCC_END_OF_CLOCKS] = +{ + {0x20, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_DWP_SWR_AVAILABLE}, /* DMA0 */ + {0x28, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_DWP_SWR_AVAILABLE}, /* DMAMUX0 */ + {0x4C, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_DWP_SWR_AVAILABLE}, /* ROMC */ + {0x60, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_DWP_SWR_AVAILABLE}, /* ERM0 */ + {0x64, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* EIM0 */ + {0x68, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* INTM0 */ + {0x6C, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_DWP_SWR_AVAILABLE}, /* ISM0 */ + {0x88, PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* WDOG0 */ + {0x98, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* TRGSEL0 */ + {0x9C, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* TRGSEL1 */ + {0xA0, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* TRGSEL2 */ + {0xA4, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* TRGSEL3 */ + {0xA8, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_DWP_SWR_AVAILABLE}, /* CRC0 */ + {0xAC, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_DWP_SWR_AVAILABLE}, /* CORDIC */ + {0xB0, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_DWP_SWR_AVAILABLE}, /* TSTMP0 */ + {0xB4, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_DWP_SWR_AVAILABLE}, /* TSTMP1 */ + {0xB8, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_DWP_SWR_AVAILABLE}, /* FCPIT0 */ + {0xBC, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_FUNCCLK_MUXDIVL_USED | PCC_MOUDULE_DIV_USED | PCC_DWP_SWR_AVAILABLE}, /* AONTIMER0 */ + {0xC0, PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* RTC */ + {0xC4, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* CMU0 */ + {0xC8, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* CMU1 */ + {0xCC, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* CMU2 */ + {0xD0, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* CMU3 */ + {0xD4, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* CMU4 */ + {0xDC, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_DWP_SWR_AVAILABLE}, /* PTIMER0 */ + {0xE0, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_DWP_SWR_AVAILABLE}, /* PTIMER1 */ + {0xEC, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_MOUDULE_DIV_USED | PCC_DWP_SWR_AVAILABLE}, /* ADC0 */ + {0xF0, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_MOUDULE_DIV_USED | PCC_DWP_SWR_AVAILABLE}, /* ADC1 */ + {0xFC, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* WKU0 */ + {0x100, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* CMP0 */ + {0x104, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* CMP1 */ + {0x10C, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_FUNCCLK_MUXDIVL_USED | PCC_DWP_SWR_AVAILABLE}, /* TMU0 */ + {0x150, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVL_USED | PCC_MOUDULE_DIV_USED | PCC_DWP_SWR_AVAILABLE}, /* SENT0 */ + {0x160, PCC_CLK_DOMAIN_BUS | PCC_DWP_SWR_AVAILABLE}, /* MB0 */ + {0x170, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_FUNCCLK_MUXDIVHPIN_USED | PCC_DWP_SWR_AVAILABLE}, /* FTU0 */ + {0x174, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_FUNCCLK_MUXDIVHPIN_USED | PCC_DWP_SWR_AVAILABLE}, /* FTU1 */ + {0x178, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_FUNCCLK_MUXDIVHPIN_USED | PCC_DWP_SWR_AVAILABLE}, /* FTU2 */ + {0x17C, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_FUNCCLK_MUXDIVHPIN_USED | PCC_DWP_SWR_AVAILABLE}, /* FTU3 */ + {0x188, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED | PCC_DWP_SWR_AVAILABLE}, /* FCSPI0 */ + {0x18C, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED | PCC_DWP_SWR_AVAILABLE}, /* FCSPI1 */ + {0x190, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED | PCC_DWP_SWR_AVAILABLE}, /* FCSPI2 */ + {0x198, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED | PCC_DWP_SWR_AVAILABLE}, /* FCIIC0 */ + {0x1A0, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED | PCC_DWP_SWR_AVAILABLE}, /* FCUART0 */ + {0x1A4, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED | PCC_DWP_SWR_AVAILABLE}, /* FCUART1 */ + {0x1A8, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED | PCC_DWP_SWR_AVAILABLE}, /* FCUART2 */ + {0x1AC, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED | PCC_DWP_SWR_AVAILABLE}, /* FCUART3 */ + {0x1C0, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* LU0 */ + {0x1E0, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_DWP_SWR_AVAILABLE}, /* FREQM */ + {0x1FC, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* STCU */ + {0x200, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_MOUDULE_DIV_USED | PCC_DWP_SWR_AVAILABLE}, /* FLEXCAN0 */ + {0x210, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_MOUDULE_DIV_USED | PCC_DWP_SWR_AVAILABLE}, /* FLEXCAN1 */ + {0x34C, PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* WDOG1 */ + {0x36C, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* TRGSEL4 */ + {0x370, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_SLOW | PCC_DWP_SWR_AVAILABLE}, /* TRGSEL5 */ + {0x37C, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED | PCC_DWP_SWR_AVAILABLE}, /* FCSPI3 */ + {0x380, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED | PCC_DWP_SWR_AVAILABLE}, /* FCSPI4 */ + {0x384, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED | PCC_DWP_SWR_AVAILABLE}, /* FCSPI5 */ + {0x3FC, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_FUNCCLK_MUXDIVHPIN_USED | PCC_DWP_SWR_AVAILABLE}, /* FTU4 */ + {0x400, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_FUNCCLK_MUXDIVHPIN_USED | PCC_DWP_SWR_AVAILABLE}, /* FTU5 */ + {0x404, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_FUNCCLK_MUXDIVHPIN_USED | PCC_DWP_SWR_AVAILABLE}, /* FTU6 */ + {0x408, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_FUNCCLK_MUXDIVHPIN_USED | PCC_DWP_SWR_AVAILABLE}, /* FTU7 */ + {0x41C, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED | PCC_DWP_SWR_AVAILABLE}, /* FCIIC1 */ + {0x420, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED | PCC_DWP_SWR_AVAILABLE}, /* FCUART4 */ + {0x424, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED | PCC_DWP_SWR_AVAILABLE}, /* FCUART5 */ + {0x428, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED | PCC_DWP_SWR_AVAILABLE}, /* FCUART6 */ + {0x42C, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED | PCC_DWP_SWR_AVAILABLE}, /* FCUART7 */ + {0x450, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVM_USED | PCC_MOUDULE_DIV_USED | PCC_DWP_SWR_AVAILABLE}, /* MSC0 */ + {0x480, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_MOUDULE_DIV_USED | PCC_DWP_SWR_AVAILABLE}, /* FLEXCAN2 */ + {0x490, PCC_CGC_AVAILABLE | PCC_CLK_DOMAIN_BUS | PCC_FUNCCLK_MUXDIVH_USED | PCC_MOUDULE_DIV_USED | PCC_DWP_SWR_AVAILABLE}, /* FLEXCAN3 */ +}; + +/***************** Local Prototype Functions *********************/ + +/***************** Local Functions *********************/ + +/***************** Global Functions *********************/ + +/** + * @brief get PCC function clock status and value. + * + * @param pcc_ClkSrcType eClockName: used for choose PCC clock source to query. + */ +uint32_t PCC_GetPccFunctionClock(const PCC_ClkSrcType eClockName) +{ + uint32_t u32DivVal; + PCC_ClkGateSrcType eSelVal; + uint32_t u32ScgClkIndex = 0U; + uint32_t u32FunctionFreqVal = 0U; + uint32_t u32RegVal, u32ScgClkDivIndex; + const PCC_ClockMapType *pAttributeVal; + + DEV_ASSERT((uint32_t)eClockName < (uint32_t)PCC_END_OF_CLOCKS); + + /* Get peripheral PCC register value */ + u32RegVal = PCC_HWA_GetRegister(s_tPccClockMap[(uint32_t)eClockName].u32RegOffset); + pAttributeVal = &s_tPccClockMap[(uint32_t)eClockName]; + + /* Check peripheral PCC is valid or not and peripheral have function clock or not */ + if ((PCC_CGC_MASK == (u32RegVal & PCC_CGC_MASK)) && (0U != (pAttributeVal->u32ClockProperty & PCC_PROPERTY_MUXDIV_ALL_MASK))) + { + eSelVal = (PCC_ClkGateSrcType)((uint8_t)PCC_GetSEL(u32RegVal)); + /* Get PCC divide value */ + if (PCC_MOUDULE_DIV_USED == (pAttributeVal->u32ClockProperty & PCC_MOUDULE_DIV_USED)) + { + u32DivVal = PCC_GetDIV(u32RegVal) + (uint32_t)1U; + } + else + { + u32DivVal = 1U; + } + + /* Get peripheral function clock source which is from SCG or TCLK */ + if (PCC_CLKGATE_SRC_OFF_OR_TCLK == eSelVal) + { + if (PCC_FUNCCLK_MUXDIVHPIN_USED == (pAttributeVal->u32ClockProperty & PCC_FUNCCLK_MUXDIVHPIN_USED)) + { + u32FunctionFreqVal = PCC_FTU_TCLK_FREQ; + } + else + { + u32FunctionFreqVal = 0U; + } + } + else + { + if (PCC_FUNCCLK_MUXDIVH_USED == (pAttributeVal->u32ClockProperty & PCC_FUNCCLK_MUXDIVH_USED)) + { + u32ScgClkDivIndex = 0U; + } + else if (PCC_FUNCCLK_MUXDIVM_USED == (pAttributeVal->u32ClockProperty & PCC_FUNCCLK_MUXDIVM_USED)) + { + u32ScgClkDivIndex = 1U; + } + else if (PCC_FUNCCLK_MUXDIVL_USED == (pAttributeVal->u32ClockProperty & PCC_FUNCCLK_MUXDIVL_USED)) + { + u32ScgClkDivIndex = 2U; + } + else + { + u32ScgClkDivIndex = 0U; + } + u32ScgClkIndex = (uint32_t)s_tPccClocIndexkMap[eSelVal].eScgClkIndex + u32ScgClkDivIndex; + } + + /* If clock source is valid, calculate peripheral function clock */ + if (u32ScgClkIndex < (uint32_t)SCG_END_OF_CLOCKS) + { + u32FunctionFreqVal = SCG_GetScgClockFreq((SCG_ClkSrcType)u32ScgClkIndex) / u32DivVal; + } + } + + return u32FunctionFreqVal; +} + +/** + * @brief get PCC interface clock status and value. + * + * @param pcc_ClkSrcType eClockName: used for choose PCC clock source to query. + */ +uint32_t PCC_GetPccInterfaceClock(const PCC_ClkSrcType eClockName) +{ + uint32_t u32InterfaceFreqVal, u32AttributeVal; + + DEV_ASSERT((uint32_t)eClockName < (uint32_t)PCC_END_OF_CLOCKS); + + u32AttributeVal = s_tPccClockMap[(uint32_t)eClockName].u32ClockProperty; + if (PCC_CLK_DOMAIN_BUS == (u32AttributeVal & PCC_CLK_DOMAIN_BUS)) + { + u32InterfaceFreqVal = SCG_GetScgClockFreq(SCG_BUS_CLK); + } + else if (PCC_CLK_DOMAIN_SLOW == (u32AttributeVal & PCC_CLK_DOMAIN_SLOW)) + { + u32InterfaceFreqVal = SCG_GetScgClockFreq(SCG_SLOW_CLK); + } + else + { + u32InterfaceFreqVal = 0U; + } + + return u32InterfaceFreqVal; +} + + +/** + * @brief set PCC one peripheral clock configuration. + * + * @param PCC_CtrlType* pConfig: the PCC initialize value point set by user. + * @return PCC_StatusType pcc function status + */ +PCC_StatusType PCC_SetPcc(const PCC_CtrlType *const pConfig) +{ + PCC_StatusType eStatus = PCC_STATUS_SUCCESS; + uint32_t u32DivVal; + uint32_t u32ScgClkIndex = 0U, u32ScgClkDivIndex; + uint32_t u32FreqVal = 0U; + uint32_t u32FunctionFreqVal = 0U; + uint32_t u32RegVal = 0U; + uint32_t u32ExpectedRegVal; + const PCC_ClockMapType *pAttributeVal; + + DEV_ASSERT(NULL_PTR != pConfig); + DEV_ASSERT((uint32_t)pConfig->eClockName < (uint32_t)PCC_END_OF_CLOCKS); + + pAttributeVal = &s_tPccClockMap[(uint32_t)pConfig->eClockName]; + /* check peripheral clock domain to calculate module clock */ + if (PCC_CLK_DOMAIN_BUS == (pAttributeVal->u32ClockProperty & PCC_CLK_DOMAIN_BUS)) + { + u32FreqVal = SCG_GetScgClockFreq(SCG_BUS_CLK); + } + else if (PCC_CLK_DOMAIN_SLOW == (pAttributeVal->u32ClockProperty & PCC_CLK_DOMAIN_SLOW)) + { + u32FreqVal = SCG_GetScgClockFreq(SCG_SLOW_CLK); + } + else + { + /* Do nothing */ + } + + if (0U == u32FreqVal) + { + /* Please call SCG function first */ + eStatus = PCC_STATUS_CLOCK_INVALID; + } + + if (PCC_STATUS_SUCCESS == eStatus) + { + /* Disable PCC gate */ + PCC_HWA_SetClockGateControl(pAttributeVal->u32RegOffset,false); + if (pConfig->bEn) + { + if (PCC_MOUDULE_DIV_USED == (pAttributeVal->u32ClockProperty & PCC_MOUDULE_DIV_USED)) + { + u32DivVal = (uint32_t)pConfig->eDivider + (uint32_t)1U; + u32RegVal |= PCC_DIV(pConfig->eDivider); + } + else + { + u32DivVal = 1U; + } + + if (0U != (pAttributeVal->u32ClockProperty & PCC_PROPERTY_MUXDIV_ALL_MASK)) + { + u32RegVal |= PCC_SEL(pConfig->eClkSrc); + } + + if (PCC_CGC_AVAILABLE == (pAttributeVal->u32ClockProperty & PCC_CGC_AVAILABLE)) + { + /* Enable peripheral clock */ + u32RegVal |= PCC_CGC_MASK; + } + + /* Configure PCC register */ + PCC_HWA_SetRegister(pAttributeVal->u32RegOffset,u32RegVal); + + /* Get peripheral function clock source which is from SCG or TCLK */ + if (PCC_CLKGATE_SRC_OFF_OR_TCLK == pConfig->eClkSrc) + { + if (PCC_FUNCCLK_MUXDIVHPIN_USED == (pAttributeVal->u32ClockProperty & PCC_FUNCCLK_MUXDIVHPIN_USED)) + { + u32FunctionFreqVal = PCC_FTU_TCLK_FREQ; + } + else + { + u32FunctionFreqVal = 0U; + } + } + else if (PCC_CLKGATE_UNINVOLVED == pConfig->eClkSrc) + { + /* do nothing */ + } + else + { + if (PCC_FUNCCLK_MUXDIVH_USED == (pAttributeVal->u32ClockProperty & PCC_FUNCCLK_MUXDIVH_USED)) + { + u32ScgClkDivIndex = 0U; + } + else if (PCC_FUNCCLK_MUXDIVM_USED == (pAttributeVal->u32ClockProperty & PCC_FUNCCLK_MUXDIVM_USED)) + { + u32ScgClkDivIndex = 1U; + } + else if (PCC_FUNCCLK_MUXDIVL_USED == (pAttributeVal->u32ClockProperty & PCC_FUNCCLK_MUXDIVL_USED)) + { + u32ScgClkDivIndex = 2U; + } + else + { + u32ScgClkDivIndex = 0U; + } + u32ScgClkIndex = (uint32_t)s_tPccClocIndexkMap[(uint32_t)pConfig->eClkSrc].eScgClkIndex + u32ScgClkDivIndex; + } + + /* Calculate peripheral function clock */ + if (u32ScgClkIndex < (uint32_t)SCG_END_OF_CLOCKS) + { + u32FunctionFreqVal = SCG_GetScgClockFreq((SCG_ClkSrcType)u32ScgClkIndex) / u32DivVal; + } + u32ExpectedRegVal = u32RegVal; + } + else + { + /* Clear PCC register */ + PCC_HWA_SetRegister(pAttributeVal->u32RegOffset,0U); + u32ExpectedRegVal = 0U; + u32FunctionFreqVal = 0U; + } + + /* Check PCC register has been configured, If current CPU do not have permission to configure the PCC register, the except value + * will not match the actual value */ + if (u32ExpectedRegVal != PCC_HWA_GetRegister(pAttributeVal->u32RegOffset)) + { + /* In this case, current core does not have permission to control the register */ + eStatus = PCC_STATUS_CONFIGURED_NOT_SUPPORT; + } + else if (u32FunctionFreqVal > 160000000U) + { + /* In this case, current function clock too high, must configured below 150M */ + eStatus = PCC_STATUS_CONFIGURED_NOT_SUPPORT; + } + else + { + /* do nothing */ + } + } + + return eStatus; +} + +/** + * @brief Generate peripheral reset + * + */ +void PCC_GenPeripheralReset(const PCC_ClkSrcType eClockName) +{ + DEV_ASSERT((uint32_t)eClockName < (uint32_t)PCC_END_OF_CLOCKS); + PCC_HWA_SoftwareReset(s_tPccClockMap[(uint32_t)eClockName].u32RegOffset); +} + + diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_pmc.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_pmc.c new file mode 100644 index 0000000..1d8a4cd --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_pmc.c @@ -0,0 +1,175 @@ +/* @file fc7xxx_driver_pmc.c +* @author Flagchip032 +* @brief FC7xxx PMC driver type definition and API +* @version 0.1.0 +* @date 2022-11-21 +* +* @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. +* +*/ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials Descriptions + * --------- ---------- ------------ --------------- + * 0.1.0 2022-11-21 Flagchip032 First version for FC7xxx + ******************************************************************************** */ +#include "fc7xxx_driver_pmc.h" + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/***************** Local variable *********************/ +static PMC_VolIntCallbackType pIsrNotify = NULL_PTR; + + +/***************** prototype *********************/ +/** + * @brief PMC interrupt function entry + * + */ +void PMC_IRQHandler(void); + +/***************** Global Functions *********************/ +/** + * @brief Get LVCSRRegister Value + * + * @return uint32_t LVCSRRegister Value + */ +uint32_t PMC_GetLVCSRRegister(void) +{ + return PMC_HWA_GetLVCSRRegister(); +} + +/** + * @brief Get All voltage flag + * + * @return uint32_t All voltage flag + */ +uint32_t PMC_GetAllVolFlag(void) +{ + uint32_t u32AllVolFlag = 0U; + u32AllVolFlag = (PMC_HWA_GetLVCSRRegister() & PMC_LVCSR_ALLFLAG_MASK); + return u32AllVolFlag; +} + +/** + * @brief Get specific voltage flag + * + * @param eFlag Voltage flag + * @return boolean If return true, the specific voltage flag is 0, otherwise, the flag is 1. + */ +boolean PMC_GetSpecificVolFlag(const PMC_FlagType eFlag) +{ + return ((PMC_HWA_GetLVCSRRegister() & eFlag) != 0U) ? true : false; +} + +/** + * @brief Clear all voltage flag + * + */ +void PMC_ClearAllVolFlag(void) +{ + PMC_HWA_SetLVCSRRegister(PMC_LVCSR_ALLFLAG_MASK); +} + +/** + * @brief Clear specific voltage flag + * + * @param eFlag Voltage flag + */ +void PMC_ClearSpecificVolFlag(const PMC_FlagType eFlag) +{ + PMC_HWA_SetLVCSRRegister(eFlag); +} + +/** + * @brief Get All voltage status + * + * @return uint32_t All voltage status + */ +uint32_t PMC_GetAllVolStatus(void) +{ + uint32_t u32AllVolStatus = 0U; + u32AllVolStatus = (PMC_HWA_GetLVCSRRegister() & PMC_LVCSR_ALLSTATUS_MASK); + return u32AllVolStatus; +} + +/** + * @brief Get specific voltage status + * + * @param eStatus Specific voltage status + * @return boolean If return true, the specific voltage status is 0, otherwise, the status is 1. + */ +boolean PMC_GetSpecificVolStatus(const PMC_StatusType eStatus) +{ + return ((PMC_HWA_GetLVCSRRegister() & eStatus) != 0U) ? true : false; +} + +/** + * @brief Configure Voltage + * + * @param pCtrl Configuration of voltage + */ +void PMC_ConfigVoltage(const PMC_CtrlType *const pCtrl) +{ + uint32_t u32ConfigVal = 0U; + PMC_HWA_UnlockConfigRegister(); + + if ((pCtrl->bLvdIntEn) || (pCtrl->bHvdIntEn) || (pCtrl->b5VBMonEn) \ + || (pCtrl->bRpmV25En) || (pCtrl->bV15AutoswEn) || (pCtrl->bV15CtrlEn)) + { + pIsrNotify = pCtrl->pIsrNotify; + } + + u32ConfigVal = PMC_CONFIG_LVD_IE(pCtrl->bLvdIntEn) | PMC_CONFIG_HVD_IE(pCtrl->bHvdIntEn) | PMC_CONFIG_V15_CTRL_EN(pCtrl->bV15CtrlEn) | PMC_CONFIG_V15_AUTOSW( + pCtrl->bV15AutoswEn) | PMC_CONFIG_RPM_VDD2P5_EN(pCtrl->bRpmV25En); + PMC_HWA_SetConfigRegister(u32ConfigVal); +} + +/** + * @brief Clear all PMC register + * + */ +void PMC_Deinit(void) +{ + PMC_HWA_SetLVCSRRegister(0x93ff0030U); + PMC_HWA_SetConfigRegister(0x8000U); +} + +/** + * @brief PMC interrupt function entry + * + */ +void PMC_IRQHandler(void) +{ + if (NULL_PTR != pIsrNotify) + { + pIsrNotify(); + } + if(PMC_GetSpecificVolFlag(PMC_HVD5V_FLAG)) + { + PMC_ClearSpecificVolFlag(PMC_HVD5V_FLAG); + } + if (PMC_GetSpecificVolFlag(PMC_HVD2P5V_FLAG)) + { + PMC_ClearSpecificVolFlag(PMC_HVD2P5V_FLAG); + } + if (PMC_GetSpecificVolFlag(PMC_HVD1P1V_FLAG)) + { + PMC_ClearSpecificVolFlag(PMC_HVD1P1V_FLAG); + } + if (PMC_GetSpecificVolFlag(PMC_LVD5V_FLAG)) + { + PMC_ClearSpecificVolFlag(PMC_LVD5V_FLAG); + } + if (PMC_GetSpecificVolFlag(PMC_LVD1P5V_FLAG)) + { + PMC_ClearSpecificVolFlag(PMC_LVD1P5V_FLAG); + } + if (PMC_GetSpecificVolFlag(PMC_HVD1P5V_FLAG)) + { + PMC_ClearSpecificVolFlag(PMC_HVD1P5V_FLAG); + } +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_port.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_port.c new file mode 100644 index 0000000..d83178d --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_port.c @@ -0,0 +1,486 @@ +/** + * @file fc7xxx_driver_port.c + * @author Flagchip + * @brief FC7xxx PORT driver type definition and API + * @version 0.1.0 + * @date 2023-2-4 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/******************************************************************************** +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 31/12/2022 Flagchip0121 N/A First version for FC7240 +********************************************************************************/ +#include "fc7xxx_driver_port.h" +#include "interrupt_manager.h" + +/** @brief PORTA interrupt entry */ +void PORTA_IRQHandler(void); +/** @brief PORTB interrupt entry */ +void PORTB_IRQHandler(void); +/** @brief PORTC interrupt entry */ +void PORTC_IRQHandler(void); +/** @brief PORTD interrupt entry */ +void PORTD_IRQHandler(void); +/** @brief PORTE interrupt entry */ +void PORTE_IRQHandler(void); + + + +/********* Local Variables ************/ +/** @brief PORT instance list */ +static PORT_Type *const s_pPortInstanceTable[PORT_INSTANCE_COUNT] = PORT_BASE_PTRS; +/** @brief PORT user defined interrupt function */ +static PORT_PinInterruptCallBackType s_pPortPinNotifyTable[PORT_PIN_NUM_MAX] = {NULL}; +/** @brief PORT interrupt mode table */ +static PORT_IntConfigType s_aPortPinIrqTable[PORT_PIN_NUM_MAX] = {PORT_IRQ_DISABLE}; +/** @brief port common interrupt handle function */ +static void Port_CommonProcessInterrupt(const PORT_InstanceType ePort, const uint8_t u8Pin); + + +/***************PORT Global Functions*****************/ +/** + * @brief Initialize port + * + * @param ePort Port instance + * @param pInitStruct Initialization structure of port + * @return Port return type. + */ +PORT_StatusType PORT_InitPins(const PORT_InstanceType ePort, const PORT_InitType *const pInitStruct) +{ + PORT_StatusType eRet = PORT_STATUS_SUCCESS; + PORT_Type *pPort; + uint32_t u32PcrRegValue = 0U; + uint32_t u32LowPcrRegValue = 0U; + uint32_t u32HighPcrRegValue = 0U; + + if (((uint32_t)ePort >= PORT_INSTANCE_COUNT) || (NULL == pInitStruct)) + { + eRet = PORT_STATUS_PARAM_INVALID; + } + else + { + pPort = s_pPortInstanceTable[(uint32_t)ePort]; + + u32PcrRegValue |= PORT_PCR_MUX(pInitStruct->uPortPinMux.u32PortPinMode); + + u32PcrRegValue |= PORT_PCR_IRQC(pInitStruct->eTriggrtMode); + + u32PcrRegValue |= PORT_PCR_PE(pInitStruct->bPullEn); + u32PcrRegValue |= PORT_PCR_PS(pInitStruct->ePullSel); + + u32PcrRegValue |= PORT_PCR_DSE0(pInitStruct->bDrvStrength0En); + u32PcrRegValue |= PORT_PCR_DSE1(pInitStruct->bDrvStrength1En); + + u32PcrRegValue |= PORT_PCR_PFE(pInitStruct->u8PassiveFilterEn); + + u32PcrRegValue |= PORT_PCR_ISF_MASK; + + u32LowPcrRegValue = u32PcrRegValue & PORT_PCR_LOW_16BITS_MASK; + u32HighPcrRegValue = u32PcrRegValue & PORT_PCR_HIGH_16BITS_MASK; + + PORT_HWA_WriteGPCLR(pPort,pInitStruct->u32PortPins,u32LowPcrRegValue); + PORT_HWA_WriteGPCHR(pPort,pInitStruct->u32PortPins,u32LowPcrRegValue); + PORT_HWA_WriteGICLR(pPort,pInitStruct->u32PortPins,u32HighPcrRegValue); + PORT_HWA_WriteGICHR(pPort,pInitStruct->u32PortPins,u32HighPcrRegValue); + } + return eRet; +} + +/** + * @brief De-initialize the Port instance + * + * @param ePort Port instance enumeration + * @param u32Pins The bit of u32Pins indicate the Pin number of this Port. + * @return Port return type. + */ +PORT_StatusType PORT_Deinit(const PORT_InstanceType ePort, const uint32_t u32Pins) +{ + PORT_StatusType eRet = PORT_STATUS_SUCCESS; + PORT_Type *pPort = s_pPortInstanceTable[ePort]; + uint8_t u8PinIndex = 0U; + uint32_t u32TempPins = u32Pins; + if ((uint32_t)ePort >= PORT_INSTANCE_COUNT) + { + eRet = PORT_STATUS_PARAM_INVALID; + } + else + { + while (u32TempPins != 0u) + { + if ((u32TempPins & ((uint32_t)1 << u8PinIndex)) != 0u) + { + PORT_HWA_ConfigPin(pPort, u8PinIndex, (uint32_t)0U); + s_aPortPinIrqTable[PORT_PIN_NUM(ePort, u8PinIndex)] = PORT_IRQ_DISABLE; + s_pPortPinNotifyTable[PORT_PIN_NUM(ePort, u8PinIndex)] = NULL; + } + u32TempPins &= (uint32_t)~((uint32_t)1 << u8PinIndex); + u8PinIndex++; + } + } + return eRet; +} + +/** + * @brief Enable interrupt function of port + * + * @param ePort Port instance enumeration + * @param pIntStruct Interrupt structure of port. + * @return Port return type. + */ +PORT_StatusType PORT_InitInterrupt(const PORT_InstanceType ePort, const PORT_InterruptType *const pIntStruct) +{ + PORT_StatusType eRet = PORT_STATUS_SUCCESS; + uint8_t u8PinIndex = 0U; + uint32_t u32TempPins = 0U; + PORT_Type *pPort = s_pPortInstanceTable[ePort]; + if (((uint32_t)ePort >= PORT_INSTANCE_COUNT) || (NULL == pIntStruct)) + { + eRet = PORT_STATUS_PARAM_INVALID; + } + else + { + u32TempPins = pIntStruct->u32PortPins; + while (u32TempPins != 0u) + { + if ((u32TempPins & ((uint32_t)1 << u8PinIndex)) != 0u) + { + PORT_HWA_ClearPinInterruptFlag(pPort, u8PinIndex); + PORT_HWA_SetPinInterruptMode(pPort, u8PinIndex, (PORT_IntConfigType)pIntStruct->ePortIsrMode); + + s_aPortPinIrqTable[PORT_PIN_NUM(ePort, u8PinIndex)] = pIntStruct->ePortIsrMode; + if (NULL != pIntStruct->pIsrNotify) + { + s_pPortPinNotifyTable[PORT_PIN_NUM(ePort, u8PinIndex)] = pIntStruct->pIsrNotify; + } + } + + u32TempPins &= (uint32_t)~((uint32_t)1 << u8PinIndex); + u8PinIndex++; + } + /* IntMgr_EnableInterrupt((IRQn_Type)((uint32_t)PORTA_IRQn + (uint32_t)ePort)); */ + } + return eRet; +} + +/** + * @brief Enable interrupt function of port + * + * @param ePort Port instance enumeration + * @param u32Pins The bit of u32Pins indicate the Pin number of this Port. + * @return Port return type. + */ +PORT_StatusType PORT_EnableInterrupt(const PORT_InstanceType ePort, const uint32_t u32Pins) +{ + PORT_StatusType eRet = PORT_STATUS_SUCCESS; + uint8_t u8PinIndex = 0U; + uint32_t u32TempPins = u32Pins; + PORT_Type *pPort = s_pPortInstanceTable[ePort]; + if ((uint32_t)ePort >= PORT_INSTANCE_COUNT) + { + eRet = PORT_STATUS_PARAM_INVALID; + } + else + { + while (u32TempPins != 0u) + { + if ((u32TempPins & ((uint32_t)1 << u8PinIndex)) != 0u) + { + PORT_HWA_ClearPinInterruptFlag(pPort, u8PinIndex); + PORT_HWA_SetPinInterruptMode(pPort, u8PinIndex, (PORT_IntConfigType)s_aPortPinIrqTable[PORT_PIN_NUM(ePort, + u8PinIndex)]); + } + u32TempPins &= (uint32_t)~((uint32_t)1 << u8PinIndex); + u8PinIndex++; + } + } + return eRet; +} + +/** + * @brief Disable interrupt function of port + * + * @param ePort Port instance enumeration + * @param u32Pins The bit of u32Pins indicate the Pin number of this Port. + * @return Port return type. + */ +PORT_StatusType PORT_DisableInterrupt(const PORT_InstanceType ePort, const uint32_t u32Pins) +{ + PORT_StatusType eRet = PORT_STATUS_SUCCESS; + uint8_t u8PinIndex = 0U; + uint32_t u32TempPins = u32Pins; + PORT_Type *pPort = s_pPortInstanceTable[ePort]; + if ((uint32_t)ePort >= PORT_INSTANCE_COUNT) + { + eRet = PORT_STATUS_PARAM_INVALID; + } + else + { + while (u32TempPins != 0u) + { + if ((u32TempPins & ((uint32_t)1 << u8PinIndex)) != 0u) + { + PORT_HWA_ClearPinInterruptFlag(pPort, u8PinIndex); + PORT_HWA_ClearPinInterruptMode(pPort, u8PinIndex); + } + u32TempPins &= (uint32_t)~((uint32_t)1 << u8PinIndex); + u8PinIndex++; + } + } + return eRet; +} + +PORT_StatusType PORT_SetPinsDmaReqMode(const PORT_InstanceType ePort, const uint32_t u32Pins, const PORT_DMAReqType eDMAReqMode) +{ + PORT_StatusType eRet = PORT_STATUS_SUCCESS; + uint8_t u8PinIndex = 0U; + uint32_t u32TempPins = u32Pins; + PORT_Type *pPort = s_pPortInstanceTable[ePort]; + if ((uint32_t)ePort >= PORT_INSTANCE_COUNT) + { + eRet = PORT_STATUS_PARAM_INVALID; + } + else + { + while (u32TempPins != 0u) + { + if ((u32TempPins & ((uint32_t)1 << u8PinIndex)) != 0u) + { + PORT_HWA_SetPinDMAReqMode(pPort, u8PinIndex, eDMAReqMode); + } + u32TempPins &= (uint32_t)~((uint32_t)1 << u8PinIndex); + u8PinIndex++; + } + } + return eRet; +} + +/** + * @brief Initialize digital filter for Port instance + * + * @param ePort Port instance enumeration + * @param pDFStruct Digital filter initialization structure of port + * @return Port return type. + */ +PORT_StatusType PORT_InitDigitalFilterPort(const PORT_InstanceType ePort, const PORT_DigitalFilterType *pDFStruct) +{ + PORT_StatusType eRet = PORT_STATUS_SUCCESS; + PORT_Type *pPort = s_pPortInstanceTable[ePort]; + if ((NULL == pDFStruct) || ((uint32_t)ePort >= PORT_INSTANCE_COUNT)) + { + eRet = PORT_STATUS_PARAM_INVALID; + } + else + { + if (pDFStruct->u32PortPinsEn != 0u) + { + if (PORT_FILTER_AON32K_CLK == pDFStruct->eClkSrc) + { + PORT_HWA_SetDigitalFilterClkSrc(pPort, pDFStruct->eClkSrc); + } + else + { + PORT_HWA_ClearDigitalFilterClkSrc(pPort); + } + PORT_HWA_ConfigDigitalFilterWidth(pPort, (uint32_t)pDFStruct->u8FilterLength); + PORT_HWA_ConfigDigitalFilter(pPort, pDFStruct->u32PortPinsEn); + } + } + return eRet; +} + +/** + * @brief De-initialize digital filter for Port instance + * + * @param ePort Port instance enumeration + * @return Port return type. + */ +PORT_StatusType PORT_DeinitDigitalFilterPort(const PORT_InstanceType ePort) +{ + PORT_StatusType eRet = PORT_STATUS_SUCCESS; + PORT_Type *pPort = s_pPortInstanceTable[ePort]; + if ((uint32_t)ePort >= PORT_INSTANCE_COUNT) + { + eRet = PORT_STATUS_PARAM_INVALID; + } + else + { + PORT_HWA_ClearDigitalFilterClkSrc(pPort); + PORT_HWA_ClearDigitalFilterWidth(pPort); + PORT_HWA_ClearDigitalFilterEnable(pPort); + } + return eRet; +} + +/** + * @brief Enable the digital filter function for the specific pin. + * + * @param ePort Port instance enumeration + * @param u32Pins The bit of u32Pins indicate the Pin number of this Port. + * @return Port return type. + */ +PORT_StatusType PORT_EnableDigitalFilterPin(const PORT_InstanceType ePort, const uint32_t u32Pins) +{ + PORT_StatusType eRet = PORT_STATUS_SUCCESS; + uint8_t u8PinIndex = 0U; + uint32_t u32TempPins = u32Pins; + PORT_Type *pPort; + if ((uint32_t)ePort >= PORT_INSTANCE_COUNT) + { + eRet = PORT_STATUS_PARAM_INVALID; + } + else + { + pPort = s_pPortInstanceTable[ePort]; + while (u32TempPins != 0u) + { + if ((u32TempPins & ((uint32_t)1 << u8PinIndex)) != 0u) + { + PORT_HWA_SetDigitalFilterEnable(pPort, u8PinIndex); + } + u32TempPins &= (uint32_t)~((uint32_t)1 << u8PinIndex); + u8PinIndex++; + } + } + return eRet; +} + +/** + * @brief Disable the digital filter function for the specific pin. + * + * @param ePort Port instance enumeration + * @param u32Pins The bit of u32Pins indicate the Pin number of this Port. + */ +PORT_StatusType PORT_DisableDigitalFilterPin(const PORT_InstanceType ePort, const uint32_t u32Pins) +{ + PORT_StatusType eRet = PORT_STATUS_SUCCESS; + uint8_t u8PinIndex = 0U; + uint32_t u32TempPins = u32Pins; + PORT_Type *pPort; + if ((uint32_t)ePort >= PORT_INSTANCE_COUNT) + { + eRet = PORT_STATUS_PARAM_INVALID; + } + else + { + pPort = s_pPortInstanceTable[ePort]; + while (u32TempPins != 0u) + { + if ((u32TempPins & ((uint32_t)1 << u8PinIndex)) != 0u) + { + PORT_HWA_ClearDigitalFilterPin(pPort, u8PinIndex); + } + u32TempPins &= (uint32_t)~((uint32_t)1 << u8PinIndex); + u8PinIndex++; + } + } + return eRet; +} + + +/** + * \brief port common interrupt handle function + * + * \param ePort port instance + * \param u8Pin bit of u8Pin indicate pin number + */ +static void Port_CommonProcessInterrupt(const PORT_InstanceType ePort, const uint8_t u8Pin) +{ + if (NULL != s_pPortPinNotifyTable[PORT_PIN_NUM(ePort, u8Pin)]) + { + s_pPortPinNotifyTable[PORT_PIN_NUM(ePort, u8Pin)](); + } +} + + +/***************PORT IRQ Functions*****************/ +/** + * \brief PORTA interrupt entry + * + */ +void PORTA_IRQHandler(void) +{ + uint8_t u8PinIndex; + for (u8PinIndex = 0U; u8PinIndex < (uint32_t)32; u8PinIndex++) + { + if (PORT_HWA_ReadPinInterruptFlag(PORTA, u8PinIndex)) + { + PORT_HWA_ClearPinInterruptFlag(PORTA, u8PinIndex); + Port_CommonProcessInterrupt(PORT_A, u8PinIndex); + } + } +} + +/** + * \brief PORTB interrupt entry + * + */ +void PORTB_IRQHandler(void) +{ + uint8_t u8PinIndex; + for (u8PinIndex = 0U; u8PinIndex < (uint8_t)32; u8PinIndex++) + { + if (PORT_HWA_ReadPinInterruptFlag(PORTB, u8PinIndex)) + { + PORT_HWA_ClearPinInterruptFlag(PORTB, u8PinIndex); + Port_CommonProcessInterrupt(PORT_B, u8PinIndex); + } + } +} + +/** + * \brief PORTC interrupt entry + * + */ +void PORTC_IRQHandler(void) +{ + uint8_t u8PinIndex; + for (u8PinIndex = 0U; u8PinIndex < (uint8_t)32; u8PinIndex++) + { + if (PORT_HWA_ReadPinInterruptFlag(PORTC, u8PinIndex)) + { + PORT_HWA_ClearPinInterruptFlag(PORTC, u8PinIndex); + Port_CommonProcessInterrupt(PORT_C, u8PinIndex); + } + } +} + +/** + * \brief PORTD interrupt entry + * + */ +void PORTD_IRQHandler(void) +{ + uint8_t u8PinIndex; + for (u8PinIndex = 0U; u8PinIndex < (uint8_t)32; u8PinIndex++) + { + if (PORT_HWA_ReadPinInterruptFlag(PORTD, u8PinIndex)) + { + PORT_HWA_ClearPinInterruptFlag(PORTD, u8PinIndex); + Port_CommonProcessInterrupt(PORT_D, u8PinIndex); + } + } +} + +/** + * \brief PORTE interrupt entry + * + */ +void PORTE_IRQHandler(void) +{ + uint8_t u8PinIndex; + for (u8PinIndex = 0U; u8PinIndex < (uint8_t)32; u8PinIndex++) + { + if (PORT_HWA_ReadPinInterruptFlag(PORTE, u8PinIndex)) + { + PORT_HWA_ClearPinInterruptFlag(PORTE, u8PinIndex); + Port_CommonProcessInterrupt(PORT_E, u8PinIndex); + } + } +} + diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_ptimer.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_ptimer.c new file mode 100644 index 0000000..cc5d945 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_ptimer.c @@ -0,0 +1,326 @@ +/** + * @file fc7xxx_driver_ptimer.c + * @author Flagchip0126 + * @brief FC7xxx PTIMER driver source code + * @version 0.1.0 + * @date 2024-01-15 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Author CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-15 Flagchip0126 N/A First version for FC7240 + ******************************************************************************** */ + +#include + +#include "fc7xxx_driver_ptimer.h" +#include "fc7xxx_driver_scg.h" +#include "HwA_scm.h" + +static PTIMER_Type *const s_apPtimerBase[PTIMER_INSTANCE_COUNT] = PTIMER_BASE_PTRS; + +static uint8_t s_u8ChnNum[PTIMER_INSTANCE_COUNT] = {0U}; + +static PTIMER_InterruptCallbackType s_apPtimerIntNotify[PTIMER_INSTANCE_COUNT] = {NULL}; +static PTIMER_SeqErrorCallbackType s_apPtimerSeqErrorNotify[ADC_INSTANCE_COUNT] = {NULL}; + +/** + * @brief Calculate the delay value base on the delay micro seconds + * + * @param eInstance the Ptimer instance to use + * @param u32DelayUs the delay time in micro seconds + * @return uint16_t the delay time in ptimer clock count + */ +static uint16_t PTIMER_CalcDelayValue(const PTIMER_InstanceType eInstance, const uint32_t u32DelayUs); + +/** + * @brief the internal Ptimer interrupt handler + * + * @param eInstance the Ptimer instance to use + */ +static void PTIMERn_IRQHandler(const PTIMER_InstanceType eInstance); + +void PTIMER0_IRQHandler(void); + +void PTIMER1_IRQHandler(void); + +static uint16_t PTIMER_CalcDelayValue(const PTIMER_InstanceType eInstance, const uint32_t u32DelayUs) +{ + DEV_ASSERT((uint8_t)eInstance < PTIMER_INSTANCE_COUNT); + + const PTIMER_Type *const pPtimer = s_apPtimerBase[eInstance]; + + uint32_t u32DelayVal; + uint32_t u32SysFreq; + uint32_t u32PtimerFreqUs = 0U; + PTIMER_ClockPreDividerType ePreDivider = PTIMER_HWA_GetDivPrescaler(pPtimer); + PTIMER_ClockPreDivMultiplyFactorType ePreDivMultFactor = PTIMER_HWA_GetDivMultiply(pPtimer); + uint8_t u8Prescaler = (1U << ePreDivider); + uint8_t u8PrescalerMult = 1U; + + switch (ePreDivMultFactor) + { + case PTIMER_PRE_DIVIDER_MULTIPLY_BY_1: + u8PrescalerMult = 1U; + break; + + case PTIMER_PRE_DIVIDER_MULTIPLY_BY_10: + u8PrescalerMult = 10U; + break; + + case PTIMER_PRE_DIVIDER_MULTIPLY_BY_20: + u8PrescalerMult = 20U; + break; + + case PTIMER_PRE_DIVIDER_MULTIPLY_BY_40: + u8PrescalerMult = 40U; + break; + + default: + u8PrescalerMult = 1U; + break; + } + + u32SysFreq = SCG_GetScgClockFreq(SCG_CORE_CLK); + u32PtimerFreqUs = u32SysFreq / 1000000U; + + u32DelayVal = (u32DelayUs * u32PtimerFreqUs) / ((uint32_t)u8Prescaler * u8PrescalerMult); + DEV_ASSERT(u32DelayVal < (1U << 16U)); + + return (uint16_t)u32DelayVal; +} + +void PTIMER0_IRQHandler(void) +{ + PTIMERn_IRQHandler(PTIMER_INSTANCE_0); +} + +void PTIMER1_IRQHandler(void) +{ + PTIMERn_IRQHandler(PTIMER_INSTANCE_1); +} + +static void PTIMERn_IRQHandler(const PTIMER_InstanceType eInstance) +{ + PTIMER_Type *const pPtimer = s_apPtimerBase[eInstance]; + uint8_t u8Channel; + if (PTIMER_HWA_GetInterruptFlag(pPtimer) == true) + { + PTIMER_HWA_ClearInterruptFlag(pPtimer); + if (s_apPtimerIntNotify[eInstance] != NULL) + { + s_apPtimerIntNotify[eInstance](); + } + } + + for (u8Channel = 0U; u8Channel < s_u8ChnNum[eInstance]; u8Channel++) + { + if (PTIMER_HWA_GetChannelSequenceErrorFlag(pPtimer, u8Channel) == true) + { + PTIMER_HWA_ClearChannelSequenceErrorFlag(pPtimer, u8Channel); + if (s_apPtimerSeqErrorNotify[eInstance] != NULL) + { + s_apPtimerSeqErrorNotify[eInstance](u8Channel); + } + } + } +} + +void PTIMER_DeInit(const PTIMER_InstanceType eInstance) +{ + DEV_ASSERT((uint8_t)eInstance < PTIMER_INSTANCE_COUNT); + + PTIMER_Type *const pPtimer = s_apPtimerBase[eInstance]; + uint8_t u8Chn; + + /* Reset PTIMER Status Ctrl Register */ + PTIMER_HWA_SetStatusCtrl(pPtimer, 0U); + /* Enable PTIMER */ + PTIMER_HWA_Enable(pPtimer); + /* Reset PTIMER Max Cnt Register */ + PTIMER_HWA_SetMaxCount(pPtimer, 0xFFFFU); + /* Reset PTIMER Int Dly Register */ + PTIMER_HWA_SetInterruptDelay(pPtimer, 0xFFFFU); + + for (u8Chn = 0U; u8Chn < PTIMER_DLY_CNT; u8Chn++) + { + PTIMER_HWA_SetChannelControl(pPtimer, u8Chn, false, false, false); + PTIMER_HWA_ClearChannelCounterFlag(pPtimer, u8Chn); + PTIMER_HWA_ClearChannelSequenceErrorFlag(pPtimer, u8Chn); + PTIMER_HWA_SetChannelDelay(pPtimer, u8Chn, 0U); + } + + /* For Pulse out trigger. */ + PTIMER_HWA_DisablePulseOut(pPtimer); + PTIMER_HWA_SetPulseOutDelay(pPtimer, 0U, 0U); + + PTIMER_HWA_LoadValue(pPtimer); + PTIMER_HWA_Disable(pPtimer); +} + +void PTIMER_Init(const PTIMER_InstanceType eInstance, const PTIMER_InitType *const pInitCfg) +{ + DEV_ASSERT(pInitCfg != NULL_PTR); + DEV_ASSERT((uint8_t)eInstance < PTIMER_INSTANCE_COUNT); + + PTIMER_Type *const pPtimer = s_apPtimerBase[(uint8_t)eInstance]; + + PTIMER_DeInit(eInstance); + + PTIMER_HWA_SetLoadMode(pPtimer, pInitCfg->eLoadValueMode); + PTIMER_HWA_SetDivPrescaler(pPtimer, pInitCfg->eClkPreDiv); + PTIMER_HWA_SetTriggerSource(pPtimer, pInitCfg->eTriggerInput); + PTIMER_HWA_SetDivMultiply(pPtimer, pInitCfg->eClkPreMultFactor); + PTIMER_HWA_SetContinuoiusModeFlag(pPtimer, pInitCfg->bContinuousModeEnable); + PTIMER_HWA_SetDMAEnableFlag(pPtimer, pInitCfg->bDmaEnable); +} + +void PTIMER_InitChannel(const PTIMER_InstanceType eInstance, + const PTIMER_ChannelCfgType aChannelCfg[], const uint8_t u8ChnNum) +{ + DEV_ASSERT(aChannelCfg != NULL_PTR); + DEV_ASSERT((uint8_t)eInstance < PTIMER_INSTANCE_COUNT); + DEV_ASSERT(u8ChnNum <= PTIMER_DLY_CNT); + + PTIMER_Type *const pPtimer = s_apPtimerBase[eInstance]; + + uint8_t u8ChnIdx; + uint16_t u16PtimerChannelDelay ; + + for (u8ChnIdx = 0U; u8ChnIdx < u8ChnNum; u8ChnIdx++) + { + PTIMER_HWA_SetChannelControl(pPtimer, u8ChnIdx, aChannelCfg[u8ChnIdx].bPreTriggerEnable, + aChannelCfg[u8ChnIdx].bPreTriggerOutputEnable, aChannelCfg[u8ChnIdx].bPreTriggerBackToBackEnable); + u16PtimerChannelDelay = PTIMER_CalcDelayValue(eInstance, aChannelCfg[u8ChnIdx].u32DelayUs); + PTIMER_HWA_SetChannelDelay(pPtimer, u8ChnIdx, u16PtimerChannelDelay); + } + s_u8ChnNum[eInstance] = u8ChnNum; +} + +void PTIMER_InitInterrupt(const PTIMER_InstanceType eInstance, + const PTIMER_InterruptType *const pInterruptCfg) +{ + DEV_ASSERT(pInterruptCfg != NULL_PTR); + DEV_ASSERT((uint8_t)eInstance < PTIMER_INSTANCE_COUNT); + PTIMER_Type *const pPtimer = s_apPtimerBase[eInstance]; + + PTIMER_HWA_SetSeqErrIntEnableFlag(pPtimer, pInterruptCfg->bSeqErrIntEnable); + uint16_t u16IntDelay = PTIMER_CalcDelayValue(eInstance, pInterruptCfg->u32IntDelayPeriodUs); + PTIMER_HWA_SetInterruptDelay(pPtimer, u16IntDelay); + PTIMER_HWA_SetInterruptEnableFlag(pPtimer, pInterruptCfg->bDelayIntEnable); + + if (pInterruptCfg->bDelayIntEnable) + { + s_apPtimerIntNotify[eInstance] = pInterruptCfg->pIntNotify; + } + else + { + s_apPtimerIntNotify[eInstance] = NULL; + } + + if (pInterruptCfg->bSeqErrIntEnable) + { + s_apPtimerSeqErrorNotify[eInstance] = pInterruptCfg->pSeqErrorNotify; + } + else + { + s_apPtimerSeqErrorNotify[eInstance] = NULL; + } + + if ((pInterruptCfg->bSeqErrIntEnable == true) || (pInterruptCfg->bDelayIntEnable == true)) + { + switch ((uint8_t)eInstance) + { + case (uint8_t)PTIMER_INSTANCE_0: + IntMgr_EnableInterrupt(PTIMER0_IRQn); + break; + + case (uint8_t)PTIMER_INSTANCE_1: + IntMgr_EnableInterrupt(PTIMER1_IRQn); + break; + + default: + break; + } + } +} + +void PTIMER_SetPeriod(const PTIMER_InstanceType eInstance, uint32_t u32PeriodUs) +{ + DEV_ASSERT((uint8_t)eInstance < PTIMER_INSTANCE_COUNT); + + PTIMER_Type *const pPtimer = s_apPtimerBase[eInstance]; + + uint16_t u16MaxCnt = PTIMER_CalcDelayValue(eInstance, u32PeriodUs); + PTIMER_HWA_SetMaxCount(pPtimer, u16MaxCnt); +} + +void PTIMER_SetPulseOut(const PTIMER_InstanceType eInstance, const PTIMER_PulseOutType *pPulseOutCfg) +{ + DEV_ASSERT((uint8_t)eInstance < PTIMER_INSTANCE_COUNT); + DEV_ASSERT(pPulseOutCfg != NULL_PTR); + PTIMER_Type *const pPtimer = s_apPtimerBase[eInstance]; + + uint16_t u16PulseOutCfgDlyHigh = PTIMER_CalcDelayValue(eInstance, pPulseOutCfg->u32PulseOutDlyHighUs); + uint16_t u16PulseOutCfgDlyLow = PTIMER_CalcDelayValue(eInstance, pPulseOutCfg->u32PulseOutDlyLowUs); + + PTIMER_HWA_SetPulseOutDelay(pPtimer, u16PulseOutCfgDlyHigh, u16PulseOutCfgDlyLow); +} + +void PTIMER_LoadValue(const PTIMER_InstanceType eInstance) +{ + DEV_ASSERT((uint8_t)eInstance < PTIMER_INSTANCE_COUNT); + + PTIMER_Type *const pPtimer = s_apPtimerBase[eInstance]; + PTIMER_HWA_LoadValue(pPtimer); +} + +void PTIMER_Enable(const PTIMER_InstanceType eInstance) +{ + DEV_ASSERT((uint8_t)eInstance < PTIMER_INSTANCE_COUNT); + + PTIMER_Type *const pPtimer = s_apPtimerBase[eInstance]; + PTIMER_HWA_Enable(pPtimer); +} + +void PTIMER_Disable(const PTIMER_InstanceType eInstance) +{ + DEV_ASSERT((uint8_t)eInstance < PTIMER_INSTANCE_COUNT); + + PTIMER_Type *const pPtimer = s_apPtimerBase[eInstance]; + PTIMER_HWA_Disable(pPtimer); +} + +void PTIMER_EnablePulseOut(const PTIMER_InstanceType eInstance) +{ + DEV_ASSERT((uint8_t)eInstance < PTIMER_INSTANCE_COUNT); + + PTIMER_Type *const pPtimer = s_apPtimerBase[eInstance]; + PTIMER_HWA_EnablePulseOut(pPtimer); +} + +void PTIMER_DisablePulseOut(const PTIMER_InstanceType eInstance) +{ + DEV_ASSERT((uint8_t)eInstance < PTIMER_INSTANCE_COUNT); + + PTIMER_Type *const pPtimer = s_apPtimerBase[eInstance]; + PTIMER_HWA_DisablePulseOut(pPtimer); +} + +void PTIMER_SelectInstance01BackToBackMode(SCM_PTimerLMSelType ePTimerLoopMode) +{ + SCM_HWA_PTimerLoopModeSel(ePTimerLoopMode); +} + +void PTIMER_GenerateSWTrigger(const PTIMER_InstanceType eInstance) +{ + DEV_ASSERT((uint8_t)eInstance < PTIMER_INSTANCE_COUNT); + + PTIMER_Type *const pPtimer = s_apPtimerBase[eInstance]; + PTIMER_HWA_GenerateSwTrigger(pPtimer); +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_rgm.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_rgm.c new file mode 100644 index 0000000..7a5b4ae --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_rgm.c @@ -0,0 +1,312 @@ +/** + * @file fc7xxx_driver_rgm.c + * @author Flagchip + * @brief FC7xxx RGM driver source code + * @version 0.1.0 + * @date 2024-01-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/******************************************************************************** +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2024-01-12 Flagchip119 N/A First version for FC7240 +********************************************************************************/ +#include "fc7xxx_driver_rgm.h" +#include "interrupt_manager.h" + +/** @brief Rgm user defined CPU0 core related system interrupt function */ +static RGM_InterruptCallBackType s_pRgmCPU0PreIntPtr = NULL; + +/** @brief Rgm pre-reset interrupt entry */ +void RGM_Pre_IRQHandler(void); + +/** + * @brief This api can get RGM_SRS register that indicate the source of the most recent reset. + * + * @return RGM->RGM_SRS register, bit 0-15,29-31 corresponding to RGM_ResetEventType, refer to reference manual for details. + * @note Multiple flags can be set if multiple reset events occur at the same time + */ +uint32_t RGM_GetLastResetFLag(void) +{ + return RGM_HWA_ReadLastResetFlag(); +} + +/** + * @brief This api can get RGM_SSRS register that indicate all reset sources since the last POR or LVD that have not been cleared by software. + * + * @return RGM->RGM_SSRS register, bit 0-15,29-31 corresponding to RGM_ResetEventType, refer to reference manual for details. + */ +uint32_t RGM_GetAllResetFlag(void) +{ + return RGM_HWA_ReadAllResetFlagBeforePOR(); +} + +/** + * @brief This api can clear reset flag of RGM_SSRS register which indicate all reset sources since the last POR or LVD that have not been cleared by software. + * + * @param eReset Enumeration of reset event flag + */ +void RGM_ClearResetFlagAfterPOR(const RGM_ResetEventType eReset) +{ + RGM_HWA_ClearResetFlagAfterPOR(eReset); +} + +/** + * @brief This api can clear all reset flag of RGM_SSRS register which indicate all reset sources since the last POR or LVD that have not been cleared by software. + * + */ +void RGM_ClearAllResetFlagAfterPOR(void) +{ + RGM_HWA_ClearAllResetFlagAfterPOR(); +} + +/** + * @brief Enable reset pin filter + * + * @param eClk Reset pin filter clock source + * @param u8BusClockFilterWidth Bus clock filter width + * @param bLpClkEn select whether enable reset pin filter using AON32clock in low power mode + * @return RGM return type + * @note If use AON32K clock, A reset signal whose length is less than 2 AON32K clock periods will be filtered + */ +RGM_StatusType RGM_EnableResetFilter(RGM_FilterClkSrc eClk, uint8_t u8BusClockFilterWidth, bool bLpClkEn) +{ + RGM_StatusType eRet = RGM_STATUS_SUCCESS; + if(eClk > RGM_RESET_FILTER_AON32K_CLOCK) + { + eRet = RGM_STATUS_PARAM_INVALID; + } + if (RGM_STATUS_SUCCESS == eRet) + { + if (RGM_RESET_FILTER_AON32K_CLOCK == eClk) + { + if ((RGM_HWA_ReadResetPinFilterEnable() & RGM_RSTFLT_RSTFLT_BUS_MASK) >> RGM_RSTFLT_RSTFLT_BUS_SHIFT == 1U) + { + RGM_HWA_DisableBusClockFilter(); + } + RGM_HWA_EnableAon32kClockFilter(); + } + if (RGM_RESET_FILTER_BUS_CLOCK == eClk) + { + if ((RGM_HWA_ReadResetPinFilterEnable() & RGM_RSTFLT_RSTFLT_AON_MASK) >> RGM_RSTFLT_RSTFLT_AON_SHIFT == 1U) + { + RGM_HWA_DisableAon32kClockFilter(); + } + RGM_HWA_SetBusClockFilterWidth(u8BusClockFilterWidth); + RGM_HWA_EnableBusClockFilter(); + } + if (bLpClkEn) + { + RGM_HWA_EnableAon32kLPClockFilter(); + } + } + return eRet; +} + +/** + * @brief Disable reset pin filter + * + * @param eClk Reset pin filter clock source + * @param bLpClkEn select whether disable reset pin filter using AON32clock in low power mode + * @return RGM return type + */ +RGM_StatusType RGM_DisableResetFilter(RGM_FilterClkSrc eClk, bool bLpClkEn) +{ + RGM_StatusType eRet = RGM_STATUS_SUCCESS; + if (eClk > RGM_RESET_FILTER_AON32K_CLOCK) + { + eRet = RGM_STATUS_PARAM_INVALID; + } + if (RGM_STATUS_SUCCESS == eRet) + { + if (RGM_RESET_FILTER_AON32K_CLOCK == eClk) + { + RGM_HWA_DisableAon32kClockFilter(); + } + if (bLpClkEn) + { + RGM_HWA_DisableAon32kLPClockFilter(); + } + if (RGM_RESET_FILTER_BUS_CLOCK == eClk) + { + RGM_HWA_ClearBusClockFilterWidth(); + RGM_HWA_DisableBusClockFilter(); + } + } + return eRet; +} + +/** + * @brief This api can enable interrupt before an system reset appear. + * + * @param eDelay Enumeration of delay cycles + * @param eResetInterrupt Reset event flag, like: RGM_INT_CLKERR0 | RGM_INT_FCSMU + * @return RGM return type + * + * @note Here is the interrupted master switch control + */ +RGM_StatusType RGM_EnableSystemResetInt(RGM_ResetDelayType eDelay, RGM_ResetIntMangerType eResetInterrupt) +{ + RGM_StatusType eRet = RGM_STATUS_SUCCESS; + if (eDelay > RGM_512_CLOCK_CYCLES) + { + eRet = RGM_STATUS_PARAM_INVALID; + } + if (RGM_STATUS_SUCCESS == eRet) + { + RGM_HWA_EnableGlobalResetInterrupt(); + RGM_HWA_SetResetDelay(eDelay); + RGM_HWA_EnableResetInterrupt(eResetInterrupt); + } + return eRet; +} + +/** + * @brief This api can disable interrupt before an system reset appear. + * + * @param eResetInterrupt Reset event flag, like: RGM_INT_CLKERR0 | RGM_INT_FCSMU + * @param bClearDelay Whether to clear delay configuration + * @return RGM return type + */ +RGM_StatusType RGM_DisableSystemResetInt(RGM_ResetIntMangerType eResetInterrupt, bool bClearDelay) +{ + RGM_StatusType eRet = RGM_STATUS_SUCCESS; + if (bClearDelay) + { + RGM_HWA_ClearResetDelay(); + } + RGM_HWA_DisableResetInterrupt(eResetInterrupt); + return eRet; +} + +/** + * @brief Generate software reset through cotex-m register + * + */ +void RGM_GenerateSwReset(void) +{ + CM7_HWA_SystemReset(); +} + +/** + * @brief This api can enable interrupt before an CPU0 core related reset appear. + * + * @param eCPU0Interrupt Reset event flag, like: RGM_CPU_INT_SWRST | RGM_CPU_INT_SYSRST + * @param pIsrNotify Interrupt function + * @return RGM return type + */ +RGM_StatusType RGM_EnableCPU0CoreResetInt(RGM_CPUIntMangerType eCPU0Interrupt,RGM_InterruptCallBackType pIsrNotify) +{ + RGM_StatusType eRet = RGM_STATUS_SUCCESS; + if((uint8_t)eCPU0Interrupt > 0x1FU) + { + eRet = RGM_STATUS_PARAM_INVALID; + } + if (RGM_STATUS_SUCCESS == eRet) + { + RGM_HWA_EnableCPU0InterruptFlag(eCPU0Interrupt); + s_pRgmCPU0PreIntPtr = pIsrNotify; + } + return eRet; +} + +/** + * @brief This api can disable interrupt before an CPU0 core related reset appear. + * + * @param eCPU0Interrupt Reset event flag, like: RGM_CPU_INT_SWRST | RGM_CPU_INT_SYSRST + * @return RGM return type + */ +RGM_StatusType RGM_DisableCPU0CoreResetInt(RGM_CPUIntMangerType eCPU0Interrupt) +{ + RGM_StatusType eRet = RGM_STATUS_SUCCESS; + if((uint8_t)eCPU0Interrupt > 0x1FU) + { + eRet = RGM_STATUS_PARAM_INVALID; + } + if (RGM_STATUS_SUCCESS == eRet) + { + RGM_HWA_DisableCPU0InterruptFlag(eCPU0Interrupt); + } + return eRet; +} + +/** + * @brief Get the CPU0 exit reset flag + * + * @return RGM_CPU_OUT_RST_UNDER CPU0 is under reset + * @return RGM_CPU_OUT_RST_OUT CPU0 is out of reset + */ +RGM_CPUOutResetType RGM_GetCPU0OutResetFlag(void) +{ + return RGM_HWA_GetCPU0OutResetFlag(); +} + +/** + * @brief Generate a CPU0 software reset. + * + */ +void RGM_GenerateCPU0SwReset(void) +{ + RGM_HWA_CPU0SWReset(); +} + +/** + * @brief This api can get RGM_C0_SRS register that indicate the source of the most recent CPU0 reset. + * + * @return RGM->RGM_C0_SRS register, bit 0-20 corresponding to RGM_ResetEventType, refer to reference manual for details. + * @note Multiple flags can be set if multiple reset events occur at the same time + */ +uint32_t RGM_GetCPU0LastResetFLag(void) +{ + return RGM_HWA_ReadCPU0LastResetFlag(); +} + +/** + * @brief This api can get RGM_C0_SSRS register that indicate all CPU0 reset sources since the last POR or LVD that have not been cleared by software. + * + * @returnRGM->RGM_C0_SSRS register, bit 0-20,29-31 corresponding to RGM_CPUResetEventType, refer to reference manual for details. + */ +uint32_t RGM_GetCPU0AllResetFlag(void) +{ + return RGM_HWA_ReadCPU0AllResetFlagBeforePOR(); +} + +/** + * @brief This api can clear reset flag of RGM_C0_SSRS register which indicate CPU0 all reset sources since the last POR or LVD that have not been cleared by software. + * + * @param eReset Enumeration of reset event flag + */ +void RGM_ClearCPU0ResetFlagAfterPOR(const RGM_CPUResetEventType eReset) +{ + RGM_HWA_ClearC0ResetFlagAfterPOR(eReset); +} + +/** + * @brief This api can clear all reset flag of RGM_C0_SSRS register which indicate CPU0 all reset sources since the last POR or LVD that have not been cleared by software. + * + */ +void RGM_ClearCPU0AllResetFlagAfterPOR(void) +{ + RGM_HWA_ClearC0AllResetFlagAfterPOR(); +} + +/** + * @brief RGM Pre-interrupt entry + * + */ +void RGM_Pre_IRQHandler(void) +{ + IntMgr_DisableGlobalInterrupt(); + + if (NULL != s_pRgmCPU0PreIntPtr) + { + s_pRgmCPU0PreIntPtr(RGM_GetCPU0LastResetFLag()); + } + IntMgr_EnableGlobalInterrupt(); +} + diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_rtc.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_rtc.c new file mode 100644 index 0000000..bcc371f --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_rtc.c @@ -0,0 +1,365 @@ +/** + * @file fc7xxx_driver_rtc.c + * @author Flagchip + * @brief FC7xxx rtc driver type definition and API + * @version 0.1.0 + * @date 2024-01-10 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/******************************************************************************** +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2024-01-10 Flagchip0076 N/A First version for FC7240 +********************************************************************************/ +#include "fc7xxx_driver_rtc.h" + +#include "fc7xxx_driver_csc.h" + + + +/** + * @brief Rtc user defined alarm interrupt function + * */ +static RTC_InterruptCallBackType s_pRTCAlarmNotifyPtr = NULL; + +/** + * @brief Rtc user defined seconds interrupt function + * */ +static RTC_InterruptCallBackType s_pRTCSecondNotifyPtr = NULL; + +/** + * @brief Rtc user defined overflow interrupt function + * */ +static RTC_InterruptCallBackType s_pRTCOverFlowNotifyPtr = NULL; + +/** + * @brief RTC common interrupt function + * */ +static void Rtc_CommonProcessInterrupt(const RTC_IntEventType eIntEvent); + +/** + * @brief RTC interrupt entry + * */ +void RTC_IRQHandler(void); + + +/** + * @brief Initialize Rtc instance + * + * @param pInitStruct Rtc initialization structure + * @return Rtc return type + * @note This function could only write once after POR. + */ +void RTC_Init(const RTC_InitType *const pInitStruct) +{ + DEV_ASSERT(pInitStruct != NULL); + /* Disable interrupt */ + RTC_HWA_DisableOverflowInterrupt(); + /*Disable Second interrupt*/ + RTC_HWA_DisableSecondInterrupt(); + /*Disable Alarm interrupt*/ + RTC_HWA_DisableAlarmInterrupt(); + /* disable the rtc clock*/ + RTC_HWA_DisableRtcCounter(); + /* clear PR register */ + RTC_HWA_SetPrescalerCounterValue(0U); + /* clear SR register */ + RTC_HWA_SetSecondCounterValue(0U); + /* clear CR register */ + RTC_HWA_ConfigControl(0U); + if (pInitStruct->bStableClkoutFreq) + { + RTC_HWA_SetClkoutFreqStable(); + } + else + { + RTC_HWA_SetClkoutFromSelectFreq(); + } + /* TSIC should only be altered when TSIE is clear */ + RTC_HWA_SetSecondAndClkoutFreq(pInitStruct->eSecIntAndClkoutFreq); + /* Set alarm value */ + RTC_HWA_SetAlarmCounterValue(pInitStruct->u32AlarmValue); +} + +/** + * @brief Rtc set interrupt + * + * @param pIntStruct interrupt structure pointer + * @return Rtc return type + * @note this function will stop Rtc timer + */ +RTC_StatusType RTC_InitInterrupt(const RTC_InterruptType *const pIntStruct) +{ + RTC_StatusType eRet = RTC_STATUS_SUCCESS; + if (NULL == pIntStruct) + { + eRet = RTC_STATUS_PARAM_INVALID; + } + else + { + /* disable the rtc timer */ + RTC_HWA_DisableRtcCounter(); + if (pIntStruct->bAlarmIntEn) + { + /* enable alarm interrupt */ + RTC_HWA_EnableAlarmInterrupt(); + s_pRTCAlarmNotifyPtr = pIntStruct->pIsrAlarmNotify; + } + else + { + /* disable alarm interrupt */ + RTC_HWA_DisableAlarmInterrupt(); + s_pRTCAlarmNotifyPtr = NULL; + } + + if (pIntStruct->bOverflowIntEn) + { + /* enable overflow interrupt */ + RTC_HWA_EnableOverflowInterrupt(); + s_pRTCOverFlowNotifyPtr = pIntStruct->pIsrOverflowNotify; + } + else + { + /* disable overflow interrupt */ + RTC_HWA_DisableOverflowInterrupt(); + s_pRTCOverFlowNotifyPtr = NULL; + } + + if (pIntStruct->bSecondIntEn) + { + /* enable second interrupt */ + RTC_HWA_EnableSecondInterrupt(); + s_pRTCSecondNotifyPtr = pIntStruct->pIsrSecondNotify; + } + else + { + /* disable second interrupt */ + RTC_HWA_DisableSecondInterrupt(); + s_pRTCSecondNotifyPtr = NULL; + } + } + return eRet; +} + +/** + * @brief De-initialize Rtc instance + * + */ +void RTC_Deinit(void) +{ + /* disable the rtc timer */ + RTC_HWA_DisableRtcCounter(); + /* clear PR register */ + RTC_HWA_SetPrescalerCounterValue(0U); + /* clear SR register */ + RTC_HWA_SetSecondCounterValue(0U); + /* clear TAR register */ + RTC_HWA_SetAlarmCounterValue(0U); + /* clear IER register */ + RTC_HWA_SetInterruptValue(0U); + /* clear CR register */ + RTC_HWA_ConfigControl(0U); + s_pRTCAlarmNotifyPtr = NULL; + s_pRTCSecondNotifyPtr = NULL; + s_pRTCOverFlowNotifyPtr = NULL; +} + +/** + * @brief Rtc enable interrupt + * + * @param bAlarmIntEn whether enable alarm interrupt + * @param bSecondIntEn whether enable second interrupt + * @param bOverflowIntEn whether enable overflow interrupt + */ +void RTC_EnableInterrupt(const bool bAlarmIntEn, const bool bSecondIntEn, const bool bOverflowIntEn) +{ + /* disable the rtc timer */ + RTC_HWA_DisableRtcCounter(); + if (bAlarmIntEn) + { + /* enable alarm interrupt */ + RTC_HWA_EnableAlarmInterrupt(); + } + if (bSecondIntEn) + { + /* enable second interrupt */ + RTC_HWA_EnableSecondInterrupt(); + } + if (bOverflowIntEn) + { + /* enable overflow interrupt */ + RTC_HWA_EnableOverflowInterrupt(); + } + /*enable the rtc clock*/ + RTC_HWA_EnableRtcCounter(); +} + +/** + * @brief Rtc disable interrupt + * + * @param bAlarmIntEn whether disable alarm interrupt + * @param bSecondIntEn whether disable second interrupt + * @param boverflowIntEn whether disable overflow interrupt + */ +void RTC_DisableInterrupt(const bool bAlarmIntEn, const bool bSecondIntEn, const bool boverflowIntEn) +{ + /* disable the rtc timer */ + RTC_HWA_DisableRtcCounter(); + if (bAlarmIntEn) + { + /* disable alarm interrupt */ + RTC_HWA_DisableAlarmInterrupt(); + } + if (bSecondIntEn) + { + /* disable second interrupt */ + RTC_HWA_DisableSecondInterrupt(); + } + if (boverflowIntEn) + { + /* disable overflow interrupt */ + RTC_HWA_DisableOverflowInterrupt(); + } + /*enable the rtc clock*/ + RTC_HWA_EnableRtcCounter(); +} + +/** + * @brief rtc start + * + */ +void RTC_Start(void) +{ + /*enable the rtc clock*/ + RTC_HWA_EnableRtcCounter(); +} + +/** + * @brief Rtc stop + * + */ +void RTC_Stop(void) +{ + /*disable the rtc clock*/ + RTC_HWA_DisableRtcCounter(); +} + +/** + * @brief Rtc alarm value + * + * @param u32AlarmValue Input value + */ +void RTC_UpdateAlarmValue(const uint32_t u32AlarmValue) +{ + /*disable the rtc clock*/ + RTC_HWA_DisableRtcCounter(); + /* clear PR register */ + RTC_HWA_SetPrescalerCounterValue(0U); + /* Set alarm value */ + RTC_HWA_SetAlarmCounterValue(RTC_HWA_ReadSecondValue() + u32AlarmValue - (uint32_t)1U); + /*enable the rtc clock*/ + RTC_HWA_EnableRtcCounter(); +} + +/** + * @brief Get Rtc counter value + * + * @return Rtc counter value + */ +uint32_t RTC_GetTime(void) +{ + return RTC_HWA_ReadSecondValue(); +} + +/** + * @brief Check RTC overflow flag + * + * @return Overflow flag + */ +bool RTC_CheckOverflowFlag(void) +{ + return RTC_HWA_GetOverflowFlag(); +} + +/** + * @brief Set second counter value + * @param u32Value the second value. + * */ +void RTC_SetSecondCounterValue(uint32_t u32Value) +{ + RTC_HWA_DisableRtcCounter(); + RTC_HWA_SetSecondCounterValue(u32Value); + RTC_HWA_EnableRtcCounter(); +} + +/** + * @brief RTC common interrupt function + * + * @param eIntEvent RTC interrupt event + */ +static void Rtc_CommonProcessInterrupt(const RTC_IntEventType eIntEvent) +{ + switch (eIntEvent) + { + case RTC_ALARM_INT: + if (NULL != s_pRTCAlarmNotifyPtr) + { + s_pRTCAlarmNotifyPtr(); + } + break; + case RTC_SECOND_INT: + if (NULL != s_pRTCSecondNotifyPtr) + { + s_pRTCSecondNotifyPtr(); + } + break; + case RTC_OVERFLOW_INT: + if (NULL != s_pRTCOverFlowNotifyPtr) + { + s_pRTCOverFlowNotifyPtr(); + } + break; + default: + /* do nothing*/ + break; + } +} + +/** + * @brief RTC alarm interrupt handler entry + * + */ +void RTC_IRQHandler(void) +{ + bool overflow_flag = RTC_HWA_GetOverflowFlag(); + bool overflow_enablebit = RTC_HWA_GetOverflowEnable(); + bool alarm_flag = RTC_HWA_GetAlarmFlag(); + bool alarm_enablebit = RTC_HWA_GetAlarmEnable(); + if ((overflow_flag) && (overflow_enablebit)) + { + /*oveflow Int*/ + /*disable the rtc clock*/ + RTC_HWA_DisableRtcCounter(); + RTC_HWA_SetSecondCounterValue(0u); + Rtc_CommonProcessInterrupt(RTC_OVERFLOW_INT); + + + } + else if ((alarm_flag) && (alarm_enablebit)) + { + /*alarm Int*/ + RTC_HWA_SetAlarmCounterValue(0u); + Rtc_CommonProcessInterrupt(RTC_ALARM_INT); + + } + else + { + /*second Int*/ + Rtc_CommonProcessInterrupt(RTC_SECOND_INT); + } +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_scg.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_scg.c new file mode 100644 index 0000000..ef8545e --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_scg.c @@ -0,0 +1,1941 @@ +/** + * @file fc7xxx_driver_scg.c + * @author Flagchip + * @brief FC7xxx SCG driver type definition and API + * @version 0.1.0 + * @date 2024-01-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ + +/******************************************************************************** +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240 +********************************************************************************/ +#include "fc7xxx_driver_scg.h" +#include "fc7xxx_board_conf.h" + +#if ((FOSC_FREQUENCY < 16000000U) || (FOSC_FREQUENCY > 48000000U)) +#error "FOSC is not in range 16M ~ 48 M" +#endif + +/***************** Macros *********************/ +#define SIRC_CLOCK 12000000U +#define SIRC32K_CLOCK 32000U +#define FIRC_CLOCK 96000000U +#define NVM_CLOCK 12000000U +#define FOSC_STABILIZATION_TIMEOUT 96000U +#define FIRC_STABILIZATION_TIMEOUT 20U +#define SIRC_STABILIZATION_TIMEOUT 100U +#define SOSC_STABILIZATION_TIMEOUT 320500U +#define PLL_STABILIZATION_TIMEOUT 320500U +#define SCG_CLKSRC_STABILIZATION_TIMEOUT 1000U +#define CLOCK_OFF_STABILIZATION_TIMEOUT 1000U /* clock out time is about 1us */ +#define CLOCK_DIV_STABILIZATION_TIMEOUT 1000U + +#define PLL0_CLK_MAX 240000000U +#define PLL1_CLK_MAX 320000000U +#define PLL_VCO_CLK_MAX 800000000U +#define PLL_VCO_CLK_MIN 300000000U +#define PLL_FEEDBACK_CLK_MAX 4000000U +#define PLL_FEEDBACK_CLK_MIN 2000000U +#define SYS_CORE_CLK_MAX 240000000U +#define SYS_BUS_CLK_MAX 120000000U +#define SYS_SLOW_CLK_MAX 60000000U + +#define FOSC_DIVH_MAX_CLOCK 48000000U +#define FOSC_DIVM_MAX_CLOCK 48000000U +#define FOSC_DIVL_MAX_CLOCK 48000000U +#define FIRC_DIVH_MAX_CLOCK 96000000U +#define FIRC_DIVM_MAX_CLOCK 96000000U +#define FIRC_DIVL_MAX_CLOCK 48000000U +#define PLL0_DIVH_MAX_CLOCK 240000000U +#define PLL0_DIVM_MAX_CLOCK 120000000U +#define PLL0_DIVL_MAX_CLOCK 60000000U +#define PLL1_DIVH_MAX_CLOCK 320000000U +#define PLL1_DIVM_MAX_CLOCK 160000000U +#define PLL1_DIVL_MAX_CLOCK 80000000U + +/***************** mcaro function *********************/ +#define SCG_CheckClockAckStatus(x, timeout, returnVal) \ + while ((x) && (timeout > 0U)) \ + { \ + timeout--; \ + } \ + if (timeout != 0U) \ + { \ + returnVal = SCG_STATUS_SUCCESS; \ + } \ + else \ + { \ + returnVal = SCG_STATUS_TIMEOUT; \ + } + + +#define SCG_GetDivHClock(_clock_, input_freq, ouput_freq) \ + { \ + uint32_t u32DivRegVal; \ + \ + u32DivRegVal = SCG_HWA_GetClockDiv(_clock_); \ + ouput_freq = SCG_CALCULATE_DIVH_FREQ(input_freq, u32DivRegVal); \ + } + +#define SCG_GetDivMClock(_clock_, input_freq, ouput_freq) \ + { \ + uint32_t u32DivRegVal; \ + u32DivRegVal = SCG_HWA_GetClockDiv(_clock_); \ + ouput_freq = SCG_CALCULATE_DIVM_FREQ(input_freq, u32DivRegVal); \ + } + +#define SCG_GetDivLClock(_clock_, input_freq, ouput_freq) \ + { \ + uint32_t u32DivRegVal; \ + u32DivRegVal = SCG_HWA_GetClockDiv(_clock_); \ + ouput_freq = SCG_CALCULATE_DIVL_FREQ(input_freq, u32DivRegVal); \ + } + +/***************** Local Functions *********************/ + +static uint32_t SCG_CalculateSircFreq(const SCG_ClkSrcType eScgClockName) +{ + uint32_t u32Freq; + + if (SCG_SIRC_CLK == eScgClockName) + { + u32Freq = SIRC_CLOCK; + } + else if (SCG_SIRCDIVH_CLK == eScgClockName) + { + SCG_GetDivHClock(SCG_SIRC_CLOCK_SYMBOL, SIRC_CLOCK, u32Freq); + } + else if (SCG_SIRCDIVM_CLK == eScgClockName) + { + SCG_GetDivMClock(SCG_SIRC_CLOCK_SYMBOL, SIRC_CLOCK, u32Freq); + } + else if (SCG_SIRCDIVL_CLK == eScgClockName) + { + SCG_GetDivLClock(SCG_SIRC_CLOCK_SYMBOL, SIRC_CLOCK, u32Freq); + } + else + { + u32Freq = UNKNOWN_CLOCK; + } + + return u32Freq; +} + +static uint32_t SCG_CalculateFircFreq(const SCG_ClkSrcType eScgClockName) +{ + uint32_t u32Freq; + + if (true == SCG_HWA_GetClockVliad(SCG_FIRC_CLOCK_SYMBOL)) + { + if (SCG_FIRC_CLK == eScgClockName) + { + u32Freq = FIRC_CLOCK; + } + else if (SCG_FIRCDIVH_CLK == eScgClockName) + { + SCG_GetDivHClock(SCG_FIRC_CLOCK_SYMBOL, FIRC_CLOCK, u32Freq); + } + else if (SCG_FIRCDIVM_CLK == eScgClockName) + { + SCG_GetDivMClock(SCG_FIRC_CLOCK_SYMBOL, FIRC_CLOCK, u32Freq); + } + else if (SCG_FIRCDIVL_CLK == eScgClockName) + { + SCG_GetDivLClock(SCG_FIRC_CLOCK_SYMBOL, FIRC_CLOCK, u32Freq); + } + else + { + u32Freq = UNKNOWN_CLOCK; + } + } + else + { + u32Freq = UNKNOWN_CLOCK; + } + + return u32Freq; +} + +static uint32_t SCG_CalculateFoscFreq(const SCG_ClkSrcType eScgClockName) +{ + uint32_t u32Freq; + + if (true == SCG_HWA_GetClockVliad(SCG_FOSC_CLOCK_SYMBOL)) + { + if (SCG_FOSC_CLK == eScgClockName) + { + u32Freq = FOSC_FREQUENCY; + } + else if (SCG_FOSCDIVH_CLK == eScgClockName) + { + SCG_GetDivHClock(SCG_FOSC_CLOCK_SYMBOL, FOSC_FREQUENCY, u32Freq); + } + else if (SCG_FOSCDIVM_CLK == eScgClockName) + { + SCG_GetDivMClock(SCG_FOSC_CLOCK_SYMBOL, FOSC_FREQUENCY, u32Freq); + } + else if (SCG_FOSCDIVL_CLK == eScgClockName) + { + SCG_GetDivLClock(SCG_FOSC_CLOCK_SYMBOL, FOSC_FREQUENCY, u32Freq); + } + else + { + u32Freq = UNKNOWN_CLOCK; + } + } + else + { + u32Freq = UNKNOWN_CLOCK; + } + + return u32Freq; +} + +static uint32_t SCG_CalculatePll0Freq(const SCG_ClkSrcType eScgClockName) +{ + uint32_t u32Freq, u32ClkFreq; + uint32_t u32Temp, u32PreDiv, u32PstDiv; + uint32_t u32Mult; + + if (true == SCG_HWA_GetClockVliad(SCG_PLL0_CLOCK_SYMBOL)) + { + u32Temp = SCG_HWA_GetPllSrc(SCG_PLL0_CLOCK_SYMBOL); + if (u32Temp == (uint32_t)SCG_PLLSOURCE_FIRC) + { + + u32ClkFreq = FIRC_CLOCK / 2U; + } + else + { + /* (u32Temp == (uint32_t)SCG_PLLSOURCE_FOSC) */ + u32ClkFreq = FOSC_FREQUENCY; + } + u32PreDiv = SCG_HWA_GetPllPrediv(SCG_PLL0_CLOCK_SYMBOL) + 1U; + u32Mult = SCG_HWA_GetPllMult(SCG_PLL0_CLOCK_SYMBOL) + 1U; + u32PstDiv = SCG_HWA_GetPllPstdiv(SCG_PLL0_CLOCK_SYMBOL); + if(u32PstDiv == 0U) + { + u32PstDiv = 1U; + } + u32ClkFreq = (u32ClkFreq / (u32PreDiv) * (u32Mult)) >> (u32PstDiv); + + if (SCG_PLL0_CLK == eScgClockName) + { + u32Freq = u32ClkFreq; + } + else if (SCG_PLL0DIVH_CLK == eScgClockName) + { + SCG_GetDivHClock(SCG_PLL0_CLOCK_SYMBOL, u32ClkFreq, u32Freq); + } + else if (SCG_PLL0DIVM_CLK == eScgClockName) + { + SCG_GetDivMClock(SCG_PLL0_CLOCK_SYMBOL, u32ClkFreq, u32Freq); + } + else if (SCG_PLL0DIVL_CLK == eScgClockName) + { + SCG_GetDivLClock(SCG_PLL0_CLOCK_SYMBOL, u32ClkFreq, u32Freq); + } + else + { + u32Freq = UNKNOWN_CLOCK; + } + } + else + { + u32Freq = UNKNOWN_CLOCK; + } + + return u32Freq; +} + +static uint32_t SCG_CalculatePll1Freq(const SCG_ClkSrcType eScgClockName) +{ + uint32_t u32Freq, u32ClkFreq; + uint32_t u32Temp, u32PreDiv, u32PstDiv; + uint32_t u32Mult; + + if (true == SCG_HWA_GetClockVliad(SCG_PLL1_CLOCK_SYMBOL)) + { + u32Temp = SCG_HWA_GetPllSrc(SCG_PLL1_CLOCK_SYMBOL); + if (u32Temp == (uint32_t)SCG_PLLSOURCE_FIRC) + { + u32ClkFreq = FIRC_CLOCK / 2U; + } + else + { + /* (u32Temp == (uint32_t)SCG_PLLSOURCE_FOSC) */ + u32ClkFreq = FOSC_FREQUENCY; + } + u32PreDiv = SCG_HWA_GetPllPrediv(SCG_PLL1_CLOCK_SYMBOL) + 1U; + u32Mult = SCG_HWA_GetPllMult(SCG_PLL1_CLOCK_SYMBOL) + 1U; + u32PstDiv = SCG_HWA_GetPllPstdiv(SCG_PLL1_CLOCK_SYMBOL); + if(u32PstDiv == 0U) + { + u32PstDiv = 1U; + } + u32ClkFreq = (u32ClkFreq / (u32PreDiv) * (u32Mult)) >> (u32PstDiv); + + if (SCG_PLL1_CLK == eScgClockName) + { + u32Freq = u32ClkFreq; + } + else if (SCG_PLL1DIVH_CLK == eScgClockName) + { + SCG_GetDivHClock(SCG_PLL1_CLOCK_SYMBOL, u32ClkFreq, u32Freq); + } + else if (SCG_PLL1DIVM_CLK == eScgClockName) + { + SCG_GetDivMClock(SCG_PLL1_CLOCK_SYMBOL, u32ClkFreq, u32Freq); + } + else if (SCG_PLL1DIVL_CLK == eScgClockName) + { + SCG_GetDivLClock(SCG_PLL1_CLOCK_SYMBOL, u32ClkFreq, u32Freq); + } + else + { + u32Freq = UNKNOWN_CLOCK; + } + } + else + { + u32Freq = UNKNOWN_CLOCK; + } + + return u32Freq; +} + +static uint32_t SCG_CalculateSystemFreq(const SCG_ClkSrcType eScgClockName) +{ + uint32_t u32Freq, u32ClkFreq; + uint32_t u32Temp, u32DivCore, u32DivBus, u32DivSlow; + + u32Temp = (uint32_t)SCG_HWA_GetSysClkSrc(); + + if ((uint32_t)SCG_CLOCK_SRC_FOSC == u32Temp) + { + u32ClkFreq = FOSC_FREQUENCY; + } + else if ((uint32_t)SCG_CLOCK_SRC_FIRC == u32Temp) + { + u32ClkFreq = FIRC_CLOCK; + } + else if ((uint32_t)SCG_CLOCK_SRC_PLL0 == u32Temp) + { + u32ClkFreq = SCG_CalculatePll0Freq(SCG_PLL0_CLK); + } + else if ((uint32_t)SCG_CLOCK_SRC_SIRC == u32Temp) + { + u32ClkFreq = SCG_CalculateSircFreq(SCG_SIRC_CLK); + } + else + { + u32ClkFreq = UNKNOWN_CLOCK; + } + + u32DivCore = (uint32_t)(SCG_HWA_GetSysClkDivCore() + 1U); + u32DivBus = (uint32_t)(SCG_HWA_GetSysClkDivBus() + 1U); + u32DivSlow = (uint32_t)(SCG_HWA_GetSysClkDivSlow() + 1U); + + u32ClkFreq = (uint32_t)(u32ClkFreq / u32DivCore); + + if (SCG_CORE_CLK == eScgClockName) + { + u32Freq = u32ClkFreq; + } + else if (SCG_BUS_CLK == eScgClockName) + { + u32Freq = (uint32_t)(u32ClkFreq / u32DivBus); + } + else + { + /* (SCG_SLOW_CLK == eScgClockName) */ + u32Freq = (uint32_t)((u32ClkFreq / u32DivBus) / u32DivSlow); + } + + return u32Freq; +} + +static uint32_t SCG_CalculateClkOutFreq(void) +{ + uint8_t u8ClockoutSrc; + uint32_t u32Freq; + /* check clock out configuration */ + u8ClockoutSrc = SCG_HWA_GetClkOutSel(); + + if ((uint8_t)SCG_CLOCKOUT_SRC_OFF == u8ClockoutSrc) + { + u32Freq = 0U; + } + else if ((uint8_t)SCG_CLOCKOUT_SRC_FOSC == u8ClockoutSrc) + { + u32Freq = FOSC_FREQUENCY; + } + else if ((uint8_t)SCG_CLOCKOUT_SRC_SIRC == u8ClockoutSrc) + { + u32Freq = SCG_CalculateSircFreq(SCG_SIRC_CLK); + } + else if ((uint8_t)SCG_CLOCKOUT_SRC_FIRC == u8ClockoutSrc) + { + u32Freq = SCG_CalculateFircFreq(SCG_FIRC_CLK); + } + else if ((uint8_t)SCG_CLOCKOUT_SRC_SOSC == u8ClockoutSrc) + { + u32Freq = SOSC_FREQUENCY; + } + else if ((uint8_t)SCG_CLOCKOUT_SRC_PLL1 == u8ClockoutSrc) + { + u32Freq = SCG_CalculatePll1Freq(SCG_PLL1_CLK); + } + else if ((uint8_t)SCG_CLOCKOUT_SRC_PLL0 == u8ClockoutSrc) + { + u32Freq = SCG_CalculatePll0Freq(SCG_PLL0_CLK); + } + else if ((uint8_t)SCG_CLOCKOUT_SRC_SIRC32K == u8ClockoutSrc) + { + u32Freq = SIRC32K_CLOCK; + } + else + { + u32Freq = UNKNOWN_CLOCK; + } + + return u32Freq; +} + +static uint32_t SCG_CalculateCMU4RefFreq(void) +{ + uint32_t u32Freq,u32Temp; + + u32Temp = SCG_HWA_GetClkOutCfg(); + + if((u32Temp & SCG_CLKOUTCFG_CMU4CLK_FOSC_MASK) != 0U) + { + u32Freq = FOSC_FREQUENCY; + } + else if((u32Temp & SCG_CLKOUTCFG_CMU4CLK_SIRC_MASK) != 0U) + { + u32Freq = SIRC_CLOCK; + } + else + { + u32Freq = UNKNOWN_CLOCK; + } + + return u32Freq; +} + +static SCG_StatusType SCG_EnablePLL0(const SCG_PllType *const pPllConfig) +{ + SCG_StatusType eStatusVal = SCG_STATUS_SUCCESS; + uint32_t u32TempVal; + uint32_t u32Freq; + uint32_t u32FeedBackFreq,u32VcoFreq; + uint32_t u32DivHClockFreq = 0u; + uint32_t u32DivMClockFreq = 0u; + uint32_t u32DivLClockFreq = 0u; + uint32_t u32Pll0DivEn = 0u; + + /* check pll is valid, if valid, do not configure PLL */ + if (true == SCG_HWA_GetClockVliad(SCG_PLL0_CLOCK_SYMBOL)) + { + eStatusVal = SCG_STATUS_SEQUENCE_ERROR; + } + else + { + /* PLL input is FOSC or FIRC clock/2 */ + u32Freq = (SCG_PLLSOURCE_FOSC == pPllConfig->eSrc) ? (FOSC_FREQUENCY) : (FIRC_CLOCK / 2U); + + /* Check the PLL feedback clock range */ + u32FeedBackFreq = u32Freq / (pPllConfig->u8Prediv + 1U); + if(u32FeedBackFreq < PLL_FEEDBACK_CLK_MIN || u32FeedBackFreq > PLL_FEEDBACK_CLK_MAX) + { + eStatusVal = SCG_STATUS_PARAM_ERROR; + } + else + { + /* Check the PLL VCO clock range */ + u32VcoFreq = u32FeedBackFreq * (pPllConfig->u16Mult + 1U); + if((u32VcoFreq < PLL_VCO_CLK_MIN) || (u32VcoFreq > PLL_VCO_CLK_MAX)) + { + eStatusVal = SCG_STATUS_PARAM_ERROR; + } + else + { + /* Check the PLL out clock range */ + u32Freq = u32VcoFreq >> (uint32_t)pPllConfig->ePstDiv; + if (u32Freq > PLL0_CLK_MAX) + { + eStatusVal = SCG_STATUS_PARAM_ERROR; + } + } + } + + /* Check DIV clock frequency is valid or not */ + if (eStatusVal == SCG_STATUS_SUCCESS) + { + if(pPllConfig->eDivH != SCG_ASYNC_CLOCK_DISABLE) + { + u32DivHClockFreq = (uint32_t)(u32Freq >> ((uint32_t)pPllConfig->eDivH - 1u)); + u32Pll0DivEn |= (uint32_t)SCG_CLOCK_DIV_H; + } + if(pPllConfig->eDivM != SCG_ASYNC_CLOCK_DISABLE) + { + u32DivMClockFreq = (uint32_t)(u32Freq >> ((uint32_t)pPllConfig->eDivM - 1u)); + u32Pll0DivEn |= (uint32_t)SCG_CLOCK_DIV_M; + } + if(pPllConfig->eDivL != SCG_ASYNC_CLOCK_DISABLE) + { + u32DivLClockFreq = (uint32_t)(u32Freq >> ((uint32_t)pPllConfig->eDivL - 1u)); + u32Pll0DivEn |= (uint32_t)SCG_CLOCK_DIV_L; + } + if ((u32DivHClockFreq > PLL0_DIVH_MAX_CLOCK) || (u32DivMClockFreq > PLL0_DIVM_MAX_CLOCK) || (u32DivLClockFreq > PLL0_DIVL_MAX_CLOCK)) + { + eStatusVal = SCG_STATUS_PARAM_ERROR; + } + } + } + + if (eStatusVal == SCG_STATUS_SUCCESS) + { + /* unlock PLL CSR register */ + SCG_HWA_UnlockPllCsr(SCG_PLL0_CLOCK_SYMBOL); + + /* Configure PLLCFG register */ + u32TempVal = SCG_PLLCFG_PREDIV(pPllConfig->u8Prediv) | SCG_PLLCFG_MULT(pPllConfig->u16Mult) | SCG_PLLCFG_PSTDIV( + pPllConfig->ePstDiv) | SCG_PLLCFG_SOURCE(pPllConfig->eSrc) ; + SCG_HWA_SetPllCfg(SCG_PLL0_CLOCK_SYMBOL, u32TempVal); + + /* Configure PLLCSR register */ + u32TempVal = SCG_PLLCSR_STEN(pPllConfig->bSten); + SCG_HWA_SetPllCsr(SCG_PLL0_CLOCK_SYMBOL, u32TempVal); + + /* Configure PLLDIV */ + SCG_HWA_DiablePll0Div(SCG_CLOCK_DIV_ALL); + u32TempVal = SCG_HWA_GetClockDiv(SCG_PLL0_CLOCK_SYMBOL); + u32TempVal &= ~(uint32_t)(SCG_PLLDIV_DIVL_MASK | SCG_PLLDIV_DIVM_MASK | SCG_PLLDIV_DIVH_MASK); + u32TempVal |= (SCG_PLLDIV_DIVH(pPllConfig->eDivH) | SCG_PLLDIV_DIVM(pPllConfig->eDivM) | SCG_PLLDIV_DIVL( + pPllConfig->eDivL)); + SCG_HWA_SetPllDiv(SCG_PLL0_CLOCK_SYMBOL, u32TempVal) ; + + /* Set CSR[EN] bit to 1 */ + SCG_HWA_EnablePll(SCG_PLL0_CLOCK_SYMBOL); + + /* Wait PLL valid */ + u32TempVal = PLL_STABILIZATION_TIMEOUT; + SCG_CheckClockAckStatus((false == SCG_HWA_GetClockVliad(SCG_PLL0_CLOCK_SYMBOL)), u32TempVal, eStatusVal) + + if (eStatusVal == SCG_STATUS_SUCCESS) + { + /* Enable PLLDIV */ + SCG_HWA_EnablePll0Div((SCG_DivEnableType)u32Pll0DivEn); + + if (pPllConfig->bCm) + { + SCG_HWA_EnablePllClockMonitor(SCG_PLL0_CLOCK_SYMBOL); + } + + if (pPllConfig->bCmre) + { + SCG_HWA_EnablePllClockMonitorReset(SCG_PLL0_CLOCK_SYMBOL); + } + + if (pPllConfig->bLock) + { + /* lock CSR register */ + SCG_HWA_LockPllCsr(SCG_PLL0_CLOCK_SYMBOL); + } + + /* Wait DIV[ACK] change to 1 */ + u32TempVal = CLOCK_DIV_STABILIZATION_TIMEOUT; + SCG_CheckClockAckStatus((SCG_HWA_GetPll0DivAck((SCG_DivEnableType)u32Pll0DivEn) != true), u32TempVal, eStatusVal) + } + else + { + /* Clear CFG configuration */ + SCG_HWA_SetPllCfg(SCG_PLL0_CLOCK_SYMBOL, 0U); + + /* Clear CSR configuration */ + SCG_HWA_SetPllCsr(SCG_PLL0_CLOCK_SYMBOL, 0U); + + /* Clear DIV configuration*/ + SCG_HWA_SetPllDiv(SCG_PLL0_CLOCK_SYMBOL, 0U); + } + + } + + return eStatusVal; +} + +static SCG_StatusType SCG_EnablePLL1(const SCG_PllType *const pPllConfig) +{ + SCG_StatusType eStatusVal = SCG_STATUS_SUCCESS; + uint32_t u32TempVal; + uint32_t u32Freq; + uint32_t u32FeedBackFreq,u32VcoFreq; + uint32_t u32DivHClockFreq = 0u; + uint32_t u32DivMClockFreq = 0u; + uint32_t u32DivLClockFreq = 0u; + uint32_t u32Pll1DivEn = 0u; + + /* check pll is valid, if valid, do not configure PLL */ + if (true == SCG_HWA_GetClockVliad(SCG_PLL1_CLOCK_SYMBOL)) + { + eStatusVal = SCG_STATUS_SEQUENCE_ERROR; + } + else + { + /* PLL input is FOSC or FIRC clock/2 */ + u32Freq = (SCG_PLLSOURCE_FOSC == pPllConfig->eSrc) ? (FOSC_FREQUENCY) : (FIRC_CLOCK / 2U); + + /* Check the PLL feedback clock range */ + u32FeedBackFreq = u32Freq / (pPllConfig->u8Prediv + 1U); + if(u32FeedBackFreq < PLL_FEEDBACK_CLK_MIN || u32FeedBackFreq > PLL_FEEDBACK_CLK_MAX) + { + eStatusVal = SCG_STATUS_PARAM_ERROR; + } + else + { + /* Check the PLL VCO clock range */ + u32VcoFreq = u32FeedBackFreq * (pPllConfig->u16Mult + 1U); + if((u32VcoFreq < PLL_VCO_CLK_MIN) || (u32VcoFreq > PLL_VCO_CLK_MAX)) + { + eStatusVal = SCG_STATUS_PARAM_ERROR; + } + else + { + /* Check the PLL out clock range */ + u32Freq = u32VcoFreq >> (uint32_t)pPllConfig->ePstDiv; + if (u32Freq > PLL1_CLK_MAX) + { + eStatusVal = SCG_STATUS_PARAM_ERROR; + } + } + } + + /* Check DIV clock frequency is valid or not */ + if (eStatusVal == SCG_STATUS_SUCCESS) + { + if(pPllConfig->eDivH != SCG_ASYNC_CLOCK_DISABLE) + { + u32DivHClockFreq = (uint32_t)(u32Freq >> ((uint32_t)pPllConfig->eDivH - 1u)); + u32Pll1DivEn |= (uint32_t)SCG_CLOCK_DIV_H; + } + if(pPllConfig->eDivM != SCG_ASYNC_CLOCK_DISABLE) + { + u32DivMClockFreq = (uint32_t)(u32Freq >> ((uint32_t)pPllConfig->eDivM - 1u)); + u32Pll1DivEn |= (uint32_t)SCG_CLOCK_DIV_M; + } + if(pPllConfig->eDivL != SCG_ASYNC_CLOCK_DISABLE) + { + u32DivLClockFreq = (uint32_t)(u32Freq >> ((uint32_t)pPllConfig->eDivL - 1u)); + u32Pll1DivEn |= (uint32_t)SCG_CLOCK_DIV_L; + } + if ((u32DivHClockFreq > PLL1_DIVH_MAX_CLOCK) || (u32DivMClockFreq > PLL1_DIVM_MAX_CLOCK) || (u32DivLClockFreq > PLL1_DIVL_MAX_CLOCK)) + { + eStatusVal = SCG_STATUS_PARAM_ERROR; + } + } + } + + if (eStatusVal == SCG_STATUS_SUCCESS) + { + /* unlock PLL CSR register */ + SCG_HWA_UnlockPllCsr(SCG_PLL1_CLOCK_SYMBOL); + + /* Configure PLLCFG register */ + u32TempVal = SCG_PLLCFG_PREDIV(pPllConfig->u8Prediv) | SCG_PLLCFG_MULT(pPllConfig->u16Mult) | SCG_PLLCFG_PSTDIV( + pPllConfig->ePstDiv) | SCG_PLLCFG_SOURCE(pPllConfig->eSrc) ; + SCG_HWA_SetPllCfg(SCG_PLL1_CLOCK_SYMBOL, u32TempVal); + + /* Configure PLLCSR register */ + u32TempVal = SCG_PLLCSR_STEN(pPllConfig->bSten); + SCG_HWA_SetPllCsr(SCG_PLL1_CLOCK_SYMBOL, u32TempVal); + + /* Configure PLLDIV */ + SCG_HWA_DiablePll1Div(SCG_CLOCK_DIV_ALL); + u32TempVal = SCG_HWA_GetClockDiv(SCG_PLL1_CLOCK_SYMBOL); + u32TempVal &= ~(uint32_t)(SCG_PLLDIV_DIVL_MASK | SCG_PLLDIV_DIVM_MASK | SCG_PLLDIV_DIVH_MASK); + u32TempVal |= (SCG_PLLDIV_DIVH(pPllConfig->eDivH) | SCG_PLLDIV_DIVM(pPllConfig->eDivM) | SCG_PLLDIV_DIVL( + pPllConfig->eDivL)); + SCG_HWA_SetPllDiv(SCG_PLL1_CLOCK_SYMBOL, u32TempVal) ; + + /* Set CSR[EN] bit to 1 */ + SCG_HWA_EnablePll(SCG_PLL1_CLOCK_SYMBOL); + + /* Wait PLL valid */ + u32TempVal = PLL_STABILIZATION_TIMEOUT; + SCG_CheckClockAckStatus((false == SCG_HWA_GetClockVliad(SCG_PLL1_CLOCK_SYMBOL)), u32TempVal, eStatusVal) + + if (eStatusVal == SCG_STATUS_SUCCESS) + { + /* Enable PLLDIV */ + SCG_HWA_EnablePll1Div((SCG_DivEnableType)u32Pll1DivEn); + + if (pPllConfig->bCm) + { + SCG_HWA_EnablePllClockMonitor(SCG_PLL1_CLOCK_SYMBOL); + } + + if (pPllConfig->bCmre) + { + SCG_HWA_EnablePllClockMonitorReset(SCG_PLL1_CLOCK_SYMBOL); + } + + if (pPllConfig->bLock) + { + /* lock CSR register */ + SCG_HWA_LockPllCsr(SCG_PLL1_CLOCK_SYMBOL); + } + + /* Wait DIV[ACK] change to 1 */ + u32TempVal = CLOCK_DIV_STABILIZATION_TIMEOUT; + SCG_CheckClockAckStatus((SCG_HWA_GetPll1DivAck((SCG_DivEnableType)u32Pll1DivEn) != true), u32TempVal, eStatusVal) + } + else + { + /* Clear CFG configuration */ + SCG_HWA_SetPllCfg(SCG_PLL1_CLOCK_SYMBOL, 0U); + + /* Clear CSR configuration */ + SCG_HWA_SetPllCsr(SCG_PLL1_CLOCK_SYMBOL, 0U); + + /* Clear DIV configuration*/ + SCG_HWA_SetPllDiv(SCG_PLL1_CLOCK_SYMBOL, 0U); + } + + } + + return eStatusVal; +} + +static SCG_StatusType SCG_DisablePLL0(void) +{ + SCG_StatusType eStatusVal = SCG_STATUS_SUCCESS; + uint32_t u32TempVal; + + /* unlock PLL CSR register */ + SCG_HWA_UnlockPllCsr(SCG_PLL0_CLOCK_SYMBOL); + + /* Clear CFG configuration */ + SCG_HWA_SetPllCfg(SCG_PLL0_CLOCK_SYMBOL, 0U); + + /* Clear CSR configuration */ + SCG_HWA_SetPllCsr(SCG_PLL0_CLOCK_SYMBOL, 0U); + + u32TempVal = CLOCK_OFF_STABILIZATION_TIMEOUT; + SCG_CheckClockAckStatus((true == SCG_HWA_GetClockVliad(SCG_PLL0_CLOCK_SYMBOL)), u32TempVal, eStatusVal) + + if (eStatusVal == SCG_STATUS_SUCCESS) + { + /* Clear CSR register */ + SCG_HWA_SetPllCsr(SCG_PLL0_CLOCK_SYMBOL, 0U); + + /* In order to avoid the DIV register value not cleared, Clear PLL DIV register twice */ + SCG_HWA_SetPllDiv(SCG_PLL0_CLOCK_SYMBOL, 0U); + SCG_HWA_SetPllDiv(SCG_PLL0_CLOCK_SYMBOL, 0U); + } + + + return eStatusVal; +} + +static SCG_StatusType SCG_DisablePLL1(void) +{ + SCG_StatusType eStatusVal = SCG_STATUS_SUCCESS; + uint32_t u32TempVal; + + /* unlock PLL CSR register */ + SCG_HWA_UnlockPllCsr(SCG_PLL1_CLOCK_SYMBOL); + + /* Clear CFG configuration */ + SCG_HWA_SetPllCfg(SCG_PLL1_CLOCK_SYMBOL, 0U); + + /* Clear CSR configuration */ + SCG_HWA_SetPllCsr(SCG_PLL1_CLOCK_SYMBOL, 0U); + + u32TempVal = CLOCK_OFF_STABILIZATION_TIMEOUT; + SCG_CheckClockAckStatus((true == SCG_HWA_GetClockVliad(SCG_PLL1_CLOCK_SYMBOL)), u32TempVal, eStatusVal) + + if (eStatusVal == SCG_STATUS_SUCCESS) + { + /* Clear CSR register */ + SCG_HWA_SetPllCsr(SCG_PLL1_CLOCK_SYMBOL, 0U); + + /* In order to avoid the DIV register value not cleared, Clear PLL DIV register twice */ + SCG_HWA_SetPllDiv(SCG_PLL1_CLOCK_SYMBOL, 0U); + SCG_HWA_SetPllDiv(SCG_PLL1_CLOCK_SYMBOL, 0U); + } + + return eStatusVal; +} + +/** + * @brief Check the system clock frequency + * @details This function check the system clock source valid and the system clock dividers valid, and get the frequency of eClock + * + * @param eClock selected clock source + * @param pSysClkConfig system clock configuration + * @param pClockFreq pointer to the memory to save clock source frequency + * @return SCG_StatusType function status + * + */ +static SCG_StatusType SCG_CheckSystemClockSourceFreq(const SCG_ClockSrcType eClock,const SCG_ClockCtrlType *const pSysClkConfig,uint32_t *pClockFreq) +{ + SCG_StatusType eStatusVal = SCG_STATUS_SUCCESS; + uint32_t u32Freq; + uint32_t u32FreqCore, u32FreqBus, u32FreqSlow; + bool eClockValid; + + if (SCG_CLOCK_SRC_FOSC == eClock) + { + eClockValid = SCG_HWA_GetClockVliad(SCG_FOSC_CLOCK_SYMBOL); + u32Freq = FOSC_FREQUENCY; + } + else if (SCG_CLOCK_SRC_FIRC == eClock) + { + eClockValid = SCG_HWA_GetClockVliad(SCG_FIRC_CLOCK_SYMBOL); + u32Freq = FIRC_CLOCK; + } + else if (SCG_CLOCK_SRC_PLL0 == eClock) + { + eClockValid = SCG_HWA_GetClockVliad(SCG_PLL0_CLOCK_SYMBOL); + u32Freq = SCG_CalculatePll0Freq(SCG_PLL0_CLK); + + } + else if (SCG_CLOCK_SRC_SIRC == eClock) + { + eClockValid = SCG_HWA_GetClockVliad(SCG_SIRC_CLOCK_SYMBOL); + u32Freq = SIRC_CLOCK; + } + else + { + eClockValid = false; + } + + if(eClockValid == false) + { + eStatusVal = SCG_STATUS_SEQUENCE_ERROR; + } + else + { + *pClockFreq = u32Freq; + + if(pSysClkConfig != NULL_PTR) + { + u32FreqCore = u32Freq / ((uint8_t)pSysClkConfig->eDivCore + 1U); + u32FreqBus = u32FreqCore / ((uint8_t)pSysClkConfig->eDivBus + 1U); + u32FreqSlow = u32FreqBus / ((uint8_t)pSysClkConfig->eDivSlow + 1U); + if ((u32FreqCore > SYS_CORE_CLK_MAX) || (u32FreqBus > SYS_BUS_CLK_MAX) || (u32FreqSlow > SYS_SLOW_CLK_MAX)) + { + eStatusVal = SCG_STATUS_PARAM_ERROR; + } + } + } + return eStatusVal; +} + +/** + * @brief Switch system clock source , and configure system clock divider if pSysClkConfig is not null. + * @details If pSysClkConfig is null , and clock switch form slow to fast(eg. FIRC to PLL0), + * the bus and slow clock may exceed the max value. So the new divider must be configured + * if the system clock is switched to a faster source. + * + * @param eClock selected clock source + * @return SCG_StatusType function status + * SCG_STATUS_SUCCESS : clock source and dividers are valid,and switch system clock successfully + * SCG_STATUS_SEQUENCE_ERROR: new clock source is not enabled + * SCG_STATUS_PARAM_ERROR: the core bus slow divider are invalid + * SCG_STATUS_TIMEOUT: switch system clock procedure time out + */ +static SCG_StatusType SCG_SwitchSystemClockWithConfig(const SCG_ClockSrcType eClock,const SCG_ClockCtrlType *const pSysClkConfig) +{ + SCG_StatusType eStatusVal = SCG_STATUS_SUCCESS; + uint32_t u32Timeout; + uint32_t u32CurClkFreq = 0U,u32NewClkFreq; + uint32_t u32RegValue; + uint8_t u8CurClkSrc,u8ClkSrc; + + u8CurClkSrc = SCG_HWA_GetSysClkSrc(); + if(u8CurClkSrc != eClock) + { + eStatusVal = SCG_CheckSystemClockSourceFreq(eClock,pSysClkConfig,&u32NewClkFreq); + + if(eStatusVal == SCG_STATUS_SUCCESS) + { + /* Get current system clock source frequency */ + if (SCG_CLOCK_SRC_FOSC == u8CurClkSrc) + { + u32CurClkFreq = FOSC_FREQUENCY; + } + else if (SCG_CLOCK_SRC_FIRC == u8CurClkSrc) + { + u32CurClkFreq = FIRC_CLOCK; + } + else if (SCG_CLOCK_SRC_PLL0 == u8CurClkSrc) + { + u32CurClkFreq = SCG_CalculatePll0Freq(SCG_PLL0_CLK); + } + else if (SCG_CLOCK_SRC_SIRC == u8CurClkSrc) + { + u32CurClkFreq = SIRC_CLOCK; + } + else + { + /* Never come here */ + } + + /* To switch the system clock source from slow to fast, configure the divider first to ensure that + the core bus slow clocks do not exceed the max value */ + if((pSysClkConfig != NULL_PTR) && (u32NewClkFreq > u32CurClkFreq)) + { + u32RegValue = SCG_HWA_GetCCR(); + u32RegValue &= ~(SCG_CCR_SYSCLK_CME_MASK | SCG_CCR_DIVCORE_MASK | SCG_CCR_DIVBUS_MASK | SCG_CCR_DIVSLOW_MASK); + u32RegValue |= (uint32_t)((uint32_t)SCG_CCR_SYSCLK_CME(pSysClkConfig->bSysClkMonitor) | + (uint32_t)SCG_CCR_DIVCORE(pSysClkConfig->eDivCore) | + (uint32_t)SCG_CCR_DIVBUS(pSysClkConfig->eDivBus) | + (uint32_t)SCG_CCR_DIVSLOW(pSysClkConfig->eDivSlow)); + SCG_HWA_SetCCR(u32RegValue); + } + + SCG_HWA_SetSystemClock((uint8_t)eClock); + + u32Timeout = SCG_CLKSRC_STABILIZATION_TIMEOUT; + do { + u8ClkSrc = SCG_HWA_GetSysClkSrc(); + --u32Timeout; + if(u32Timeout == 0U) + { + eStatusVal = SCG_STATUS_TIMEOUT; + break; + } + } while((SCG_HWA_GetSysClkUPRD() == false) && (u8ClkSrc != (uint8_t)eClock)); + + if (eStatusVal == SCG_STATUS_SUCCESS) + { + /* To change the system clock source from fast to slow, configure the divider after selecting the clock source, + because it is safe to divide the slow frequency with the old divider */ + if((pSysClkConfig != NULL_PTR) && (u32NewClkFreq <= u32CurClkFreq)) + { + u32RegValue = SCG_HWA_GetCCR(); + u32RegValue &= ~(SCG_CCR_SYSCLK_CME_MASK | SCG_CCR_DIVCORE_MASK | SCG_CCR_DIVBUS_MASK | SCG_CCR_DIVSLOW_MASK); + u32RegValue |= (uint32_t)((uint32_t)SCG_CCR_SYSCLK_CME(pSysClkConfig->bSysClkMonitor) | + (uint32_t)SCG_CCR_DIVCORE(pSysClkConfig->eDivCore) | + (uint32_t)SCG_CCR_DIVBUS(pSysClkConfig->eDivBus) | + (uint32_t)SCG_CCR_DIVSLOW(pSysClkConfig->eDivSlow)); + SCG_HWA_SetCCR(u32RegValue); + + u32Timeout = SCG_CLKSRC_STABILIZATION_TIMEOUT; + while(SCG_HWA_GetSysClkUPRD() == false) + { + --u32Timeout; + if(u32Timeout == 0U) + { + eStatusVal = SCG_STATUS_TIMEOUT; + break; + } + } + } + } + + } + + } + return eStatusVal; +} + +/***************** Global Functions *********************/ +/** + * @brief Enable SOSC + * + * @param pSoscConfig SOSC configuration + * @return SCG_StatusType Function status + */ +SCG_StatusType SCG_EnableSOSC(const SCG_SoscType *const pSoscConfig) +{ + SCG_StatusType eStatusVal = SCG_STATUS_SUCCESS; + uint32_t u32TempVal; + + DEV_ASSERT(NULL_PTR != pSoscConfig); + DEV_ASSERT(32768U == SOSC_FREQUENCY); + + /* Configure SOSC */ + SCG_HWA_SetSoscRecommendCfg(); + + /* Unlock CSR register first */ + SCG_HWA_UnlockSoscCsrReg(); + + /* Configure SOSC CSR register */ + u32TempVal = SCG_HWA_GetSoscCsr(); + u32TempVal &= ~(uint32_t)(SCG_SOSCCSR_BYPASS_MASK | SCG_SOSCCSR_CM_MASK | SCG_SOSCCSR_CMRE_MASK); + u32TempVal |= SCG_SOSCCSR_BYPASS(pSoscConfig->bBypass); + SCG_HWA_SetSoscCsr(u32TempVal); + + /* Enable SOSC*/ + SCG_HWA_EnableSosc(); + + /* Wait SOSC valid */ + u32TempVal = SOSC_STABILIZATION_TIMEOUT; + SCG_CheckClockAckStatus((false == SCG_HWA_GetClockVliad(SCG_SOSC_CLOCK_SYMBOL)), u32TempVal, eStatusVal) + + if (eStatusVal == SCG_STATUS_SUCCESS) + { + if (pSoscConfig->bCm) + { + SCG_HWA_EnableSoscClockMonitor(); + } + + if (pSoscConfig->bCmre) + { + SCG_HWA_EnableSoscClockMonitorReset(); + } + + if (pSoscConfig->bLock) + { + /* Lock CSR */ + SCG_HWA_LockSoscCsrReg(); + } + } + else + { + SCG_HWA_SetSoscCsr(0U); + } + + return eStatusVal; +} + +/** + * @brief Disable SOSC + * + * @return SCG_StatusType Function status + */ +SCG_StatusType SCG_DisableSOSC(void) +{ + SCG_StatusType eStatusVal; + uint32_t u32TempVal; + + /* Unlock CSR register first */ + SCG_HWA_UnlockSoscCsrReg(); + + /* Disable SOSC */ + SCG_HWA_DisableSosc(); + + /* Wait SOSC valid */ + u32TempVal = SOSC_STABILIZATION_TIMEOUT; + SCG_CheckClockAckStatus((true == SCG_HWA_GetClockVliad(SCG_SOSC_CLOCK_SYMBOL)), u32TempVal, eStatusVal) + + if (eStatusVal == SCG_STATUS_SUCCESS) + { + /* Clear CSR register */ + SCG_HWA_SetSoscCsr(0U); + } + + return eStatusVal; +} + +/** + * @brief Enable FOSC clock with input configuration + * + * @param pFoscConfig FOSC configuration + * @return SCG_StatusType function status + */ +SCG_StatusType SCG_EnableFOSC(const SCG_FoscType *const pFoscConfig) +{ + SCG_StatusType eStatusVal = SCG_STATUS_SUCCESS; + uint32_t u32TempVal,u32FoscFreq; + uint8_t u8MSBVal; + uint32_t u32DivHClockFreq = 0U; + uint32_t u32DivMClockFreq = 0U; + uint32_t u32DivLClockFreq = 0U; + uint32_t u32FoscDivEn = 0U; + + DEV_ASSERT(NULL_PTR != pFoscConfig); + + /* Check DIV clock frequency is valid or not */ + if(pFoscConfig->eDivH != SCG_ASYNC_CLOCK_DISABLE) + { + u32DivHClockFreq = (uint32_t)FOSC_FREQUENCY >> ((uint32_t)pFoscConfig->eDivH - 1U); + u32FoscDivEn |= (uint32_t)SCG_CLOCK_DIV_H; + } + if(pFoscConfig->eDivM != SCG_ASYNC_CLOCK_DISABLE) + { + u32DivMClockFreq = (uint32_t)FOSC_FREQUENCY >> ((uint32_t)pFoscConfig->eDivM - 1U); + u32FoscDivEn |= (uint32_t)SCG_CLOCK_DIV_M; + } + if(pFoscConfig->eDivL != SCG_ASYNC_CLOCK_DISABLE) + { + u32DivLClockFreq = (uint32_t)FOSC_FREQUENCY >> ((uint32_t)pFoscConfig->eDivL - 1U); + u32FoscDivEn |= (uint32_t)SCG_CLOCK_DIV_L; + } + + if ((u32DivHClockFreq > FOSC_DIVH_MAX_CLOCK) || (u32DivMClockFreq > FOSC_DIVM_MAX_CLOCK) || (u32DivLClockFreq > FOSC_DIVL_MAX_CLOCK)) + { + eStatusVal = SCG_STATUS_PARAM_ERROR; + } + + if (eStatusVal == SCG_STATUS_SUCCESS) + { + /* Unlock CSR register */ + SCG_HWA_UnlockFoscCsrReg(); + + /* COMP_EN is setting to 1 COMP_EN must be 1 when using an external crystal */ + /* Configure GM to the max value, GM_SEL: 15U */ + u32TempVal = SCG_FOSCCFG_BYPASS(pFoscConfig->bBypass) | SCG_FOSCCFG_COMP_EN(!pFoscConfig->bBypass) | + SCG_FOSCCFG_EOCV(50U) | SCG_FOSCCFG_GM_SEL(15U) | + SCG_FOSCCFG_ALC_D(1U) | SCG_FOSCCFG_HYST_D(0U); + SCG_HWA_SetFoscCfg(u32TempVal); + + /* Configure CSR register */ + u32TempVal = SCG_HWA_GetFoscCsr(); + u32TempVal &= ~(uint32_t)(SCG_FOSCCSR_STEN_MASK | SCG_FOSCCSR_CM_MASK | SCG_FOSCCSR_CMRE_MASK); + u32TempVal |= SCG_FOSCCSR_STEN(pFoscConfig->bSten); + SCG_HWA_SetFoscCsr(u32TempVal); + + /* Configure DIV value */ + SCG_HWA_DiableFoscDiv(SCG_CLOCK_DIV_ALL); + u32TempVal = SCG_HWA_GetClockDiv(SCG_FOSC_CLOCK_SYMBOL); + u32TempVal &= ~(uint32_t)(SCG_FOSCDIV_DIVL_MASK | SCG_FOSCDIV_DIVM_MASK | SCG_FOSCDIV_DIVH_MASK); + u32TempVal |= (SCG_FOSCDIV_DIVH(pFoscConfig->eDivH) | SCG_FOSCDIV_DIVM(pFoscConfig->eDivM) | SCG_FOSCDIV_DIVL( + pFoscConfig->eDivL)); + SCG_HWA_SetFoscDiv(u32TempVal) ; + + /* Enable FOSC */ + SCG_HWA_EnableFosc(); + + /* Wait FOSC vaild */ + u32TempVal = FOSC_STABILIZATION_TIMEOUT; + SCG_CheckClockAckStatus((false == SCG_HWA_GetClockVliad(SCG_FOSC_CLOCK_SYMBOL)), u32TempVal, eStatusVal) + + if (eStatusVal == SCG_STATUS_SUCCESS) + { + /* Enable DIV */ + SCG_HWA_EnableFoscDiv((SCG_DivEnableType)u32FoscDivEn); + + if (pFoscConfig->bCm) + { + SCG_HWA_EnableFoscClockMonitor(); + } + + if (pFoscConfig->bCmre) + { + SCG_HWA_EnableFoscClockMonitorReset(); + } + + if (pFoscConfig->bLock) + { + /* Lock FOSC CSR register */ + SCG_HWA_LockFoscCsrReg(); + } + + /* Wait DIV[ACK] change to 1 */ + u32TempVal = CLOCK_DIV_STABILIZATION_TIMEOUT; + SCG_CheckClockAckStatus((SCG_HWA_GetFoscDivAck((SCG_DivEnableType)u32FoscDivEn) != true), u32TempVal, eStatusVal) + + /* if OSC >= 40M ,set 5, if OSC = 32M,set 10, if OSC = 24M, set 15, if OSC = 16M, set 20, if OSC = 8M, set 25*/ + /* This is the protection measure during low power wake up, if SCG register not valid after the setting time, the chip will reset + * and will set clock error flag in RGM register */ + u32FoscFreq = FOSC_FREQUENCY; + u8MSBVal = ((u32FoscFreq / 8000000U) >= 5U) ? (uint8_t)5U : (uint8_t)((6U - (FOSC_FREQUENCY / 8000000U)) * 5U); + SCG_HWA_SetWKPWDG(u8MSBVal); + } + else + { + /* Clear CSR configuration */ + SCG_HWA_SetFoscCsr(0U); + + /* Clear CFG configuration*/ + SCG_HWA_SetFoscCfg(0U); + + /* Clear DIV configuration*/ + SCG_HWA_SetFoscDiv(0U); + } + } + return eStatusVal; +} + +/** + * @brief Disable FOSC + * + * @return SCG_StatusType function status + */ +SCG_StatusType SCG_DisableFOSC(void) +{ + SCG_StatusType eStatusVal = SCG_STATUS_SUCCESS; + uint32_t u32TempVal; + uint8_t u8ClkSrc; + + u8ClkSrc = SCG_HWA_GetSysClkSrc(); + if ((uint8_t)SCG_CLOCK_SRC_FOSC == u8ClkSrc) + { + eStatusVal = SCG_STATUS_SEQUENCE_ERROR; + } + else if ((SCG_HWA_GetPllSrc(SCG_PLL0_CLOCK_SYMBOL) == (uint8_t)SCG_PLLSOURCE_FOSC) && ((uint8_t)SCG_CLOCK_SRC_PLL0 == u8ClkSrc)) + { + eStatusVal = SCG_STATUS_SEQUENCE_ERROR; + } + else + { + /* do nothing */ + } + + if (eStatusVal == SCG_STATUS_SUCCESS) + { + /* Unlock CSR register */ + SCG_HWA_UnlockFoscCsrReg(); + + /* Clear FOSC[EN] bit */ + SCG_HWA_DisableFosc(); + + u32TempVal = CLOCK_OFF_STABILIZATION_TIMEOUT; + SCG_CheckClockAckStatus((true == SCG_HWA_GetClockVliad(SCG_FOSC_CLOCK_SYMBOL)), u32TempVal, eStatusVal) + + if (eStatusVal == SCG_STATUS_SUCCESS) + { + /* Clear CSR register */ + SCG_HWA_SetFoscCsr(0U); + + /* In order to avoid the DIV register value not cleared, Clear FOSC DIV register twice */ + SCG_HWA_SetFoscDiv(0U); + SCG_HWA_SetFoscDiv(0U); + } + } + + return eStatusVal; +} + +/** + * @brief Set SIRC configuration and configure SIRC DIV + * + * @param pSircConfig SIRC configuration + * @return SCG_StatusType function status + */ +SCG_StatusType SCG_SetSIRC(const SCG_SircType *const pSircConfig) +{ + SCG_StatusType eStatusVal = SCG_STATUS_SUCCESS; + uint32_t u32TempVal; + uint32_t u32SircDivEn = 0U; + uint16_t u16TrimDiv = 0U; + + DEV_ASSERT(NULL_PTR != pSircConfig); + DEV_ASSERT(pSircConfig->eDivH <= (uint32_t)SCG_ASYNCCLOCKDIV_BY64); + DEV_ASSERT(pSircConfig->eDivM <= (uint32_t)SCG_ASYNCCLOCKDIV_BY64); + DEV_ASSERT(pSircConfig->eDivL <= (uint32_t)SCG_ASYNCCLOCKDIV_BY64); + + /* Unlock SIRC CSR register */ + SCG_HWA_UnlockSircCsrReg(); + + /* Configure CSR register */ + u32TempVal = SCG_HWA_GetSircCsr(); + u32TempVal &= ~(uint32_t)(SCG_SIRCCSR_STEN_MASK | SCG_SIRCCSR_LPEN_MASK | SCG_SIRCCSR_TREN_MASK | SCG_SIRCCSR_TRUP_MASK | SCG_SIRCCSR_CM_MASK); + u32TempVal |= (uint32_t)(SCG_SIRCCSR_TRUP(pSircConfig->bTrEn) | SCG_SIRCCSR_TREN(pSircConfig->bTrEn) | SCG_SIRCCSR_LPEN(pSircConfig->bLpen) | SCG_SIRCCSR_STEN(pSircConfig->bSten)); + SCG_HWA_SetSircCsr(u32TempVal); + + /* Disable SIRC DIV[EN] bit */ + SCG_HWA_DiableSircDiv(SCG_CLOCK_DIV_ALL); + + if (pSircConfig->bCm) + { + SCG_HWA_EnableSircClockMonitor(); + } + + if (pSircConfig->bLock) + { + /* lock CSR */ + SCG_HWA_LockSircCsrReg(); + } + + /* Configure SIRC DIV */ + u32TempVal = SCG_HWA_GetClockDiv(SCG_SIRC_CLOCK_SYMBOL); + u32TempVal &= ~(uint32_t)(SCG_SIRCDIV_DIVL_MASK | SCG_SIRCDIV_DIVM_MASK | SCG_SIRCDIV_DIVH_MASK); + u32TempVal |= (uint32_t)(SCG_SIRCDIV_DIVL(pSircConfig->eDivL) | SCG_SIRCDIV_DIVM(pSircConfig->eDivM) | SCG_SIRCDIV_DIVH( + pSircConfig->eDivH)); + SCG_HWA_SetSircDiv(u32TempVal); + + /* Enable SIRC DIV */ + u32SircDivEn |= (pSircConfig->eDivH != SCG_ASYNC_CLOCK_DISABLE) ? (uint32_t)SCG_CLOCK_DIV_H : 0U; + u32SircDivEn |= (pSircConfig->eDivM != SCG_ASYNC_CLOCK_DISABLE) ? (uint32_t)SCG_CLOCK_DIV_M : 0U; + u32SircDivEn |= (pSircConfig->eDivL != SCG_ASYNC_CLOCK_DISABLE) ? (uint32_t)SCG_CLOCK_DIV_L : 0U; + SCG_HWA_EnableSircDiv((SCG_DivEnableType)u32SircDivEn); + u32TempVal = CLOCK_DIV_STABILIZATION_TIMEOUT; + SCG_CheckClockAckStatus((SCG_HWA_GetSircDivAck((SCG_DivEnableType)u32SircDivEn) != true), u32TempVal, eStatusVal) + + if (SCG_STATUS_SUCCESS != eStatusVal) + { + /* Clear SIRC DIV register */ + SCG_HWA_SetSircDiv(0U); + } + + /* Set SIRCTCFG register */ + if (pSircConfig->bTrEn == true) + { + /* set SIRCTCFG trim configuration */ + if (pSircConfig->u8TrimSrc == (uint8_t)SCG_IRC_TRIMSRC_FOSC) + { + /* Trim clock source choose FOSC */ + u16TrimDiv = (uint16_t)(FOSC_FREQUENCY / 250000U - 1U); + } + else if (pSircConfig->u8TrimSrc == (uint8_t)SCG_IRC_TRIMSRC_SOSC) + { + /* Trim clock source choose SOSC */ + u16TrimDiv = 0U; + } + else + { + /* Do nothing */ + } + u32TempVal = (uint32_t)(SCG_SIRCTCFG_TRIMSRC(pSircConfig->u8TrimSrc) | SCG_SIRCTCFG_TRIMDIV(u16TrimDiv)); + SCG_HWA_SetSircTcfg(u32TempVal); + } + + return eStatusVal; +} + +/** + * @brief Disable SIRC DIV and clear DIV configuration + * + * @return SCG_StatusType function status + */ +SCG_StatusType SCG_ClearSIRC(void) +{ + SCG_StatusType eStatusVal = SCG_STATUS_SUCCESS; + + /* check SIRC is invalid, if invalid, do not configure SIRC */ + if (true != SCG_HWA_GetClockVliad(SCG_SIRC_CLOCK_SYMBOL)) + { + eStatusVal = SCG_STATUS_SEQUENCE_ERROR; + } + + if (eStatusVal == SCG_STATUS_SUCCESS) + { + /* Unlock SIRC CSR register */ + SCG_HWA_UnlockSircCsrReg(); + + /* Disable SIRC DIV[EN] bit */ + SCG_HWA_DiableSircDiv(SCG_CLOCK_DIV_ALL); + + /* Clear SIRC DIV register */ + SCG_HWA_SetSircDiv(0U); + } + + return eStatusVal; +} + +/** + * @brief Enable SIRC32K + * + * @param pSirc32kConfig SIRC32K configuration + * @return SCG_StatusType function status + */ +SCG_StatusType SCG_EnableSIRC32K(const SCG_Sirc32kType *const pSirc32kConfig) +{ + SCG_StatusType eStatusVal = SCG_STATUS_SUCCESS; + uint32_t u32TempVal; + + DEV_ASSERT(NULL_PTR != pSirc32kConfig); + + /* Unlock SIRC32K CSR register */ + SCG_HWA_UnlockSirc32kCsrReg(); + + /* Enable SIRC32K */ + SCG_HWA_EnableSirc32kCsr(); + + /* Wait SIRC32K valid */ + u32TempVal = SIRC_STABILIZATION_TIMEOUT; + SCG_CheckClockAckStatus((false == SCG_HWA_GetClockVliad(SCG_SIRC32K_CLOCK_SYMBOL)), u32TempVal, eStatusVal) + + if (eStatusVal == SCG_STATUS_SUCCESS) + { + if (pSirc32kConfig->bLock) + { + /* Lock SIRC32K CSR register */ + SCG_HWA_LockSirc32kCsrReg(); + } + } + + return eStatusVal; +} + +/** + * @brief Disable SIRC32K + * + * @return SCG_StatusType function status + */ +SCG_StatusType SCG_DisableSIRC32K(void) +{ + SCG_StatusType eStatusVal; + uint32_t u32TempVal; + + /* Unlock SIRC32K CSR register */ + SCG_HWA_UnlockSirc32kCsrReg(); + + /* Disable SIRC32K */ + SCG_HWA_DisableSirc32kCsr(); + + /* Wait SIRC32K not valid */ + u32TempVal = SIRC_STABILIZATION_TIMEOUT; + SCG_CheckClockAckStatus((true == SCG_HWA_GetClockVliad(SCG_SIRC32K_CLOCK_SYMBOL)), u32TempVal, eStatusVal) + + return eStatusVal; +} + +/** + * @brief Enable FIRC + * + * @param pFircConfig FIRC configuration + * @return SCG_StatusType function status + */ +SCG_StatusType SCG_EnableFIRC(const SCG_FircType *const pFircConfig) +{ + SCG_StatusType eStatusVal = SCG_STATUS_SUCCESS; + uint32_t u32TempVal, u32DivLClockFreq = 0U; + uint32_t u32FircDivEn = 0U; + uint16_t u16TrimDiv = 0U; + + DEV_ASSERT(NULL_PTR != pFircConfig); + DEV_ASSERT(pFircConfig->eDivH <= (uint32_t)SCG_ASYNCCLOCKDIV_BY64); + DEV_ASSERT(pFircConfig->eDivM <= (uint32_t)SCG_ASYNCCLOCKDIV_BY64); + DEV_ASSERT(pFircConfig->eDivL <= (uint32_t)SCG_ASYNCCLOCKDIV_BY64); + + /* Check DIV clock frequency is valid or not */ + if(pFircConfig->eDivL != SCG_ASYNC_CLOCK_DISABLE) + { + u32DivLClockFreq = (uint32_t)(FIRC_CLOCK >> (pFircConfig->eDivL - 1)); + u32FircDivEn |= (uint32_t)SCG_CLOCK_DIV_L; + } + if (u32DivLClockFreq > FIRC_DIVL_MAX_CLOCK) + { + eStatusVal = SCG_STATUS_PARAM_ERROR; + } + + if (eStatusVal == SCG_STATUS_SUCCESS) + { + /* Unlock CSR register */ + SCG_HWA_UnlockFircCsrReg(); + + /* Configure recommend value */ + SCG_HWA_SetFircCfg(SCG_FIRCCFG_CLKEN(3U)); + + /* Configure CSR register */ + u32TempVal = SCG_HWA_GetFircCsr(); + u32TempVal &= ~(uint32_t)(SCG_FIRCCSR_STEN_MASK | SCG_FIRCCSR_TREN_MASK | SCG_FIRCCSR_TRUP_MASK | SCG_FIRCCSR_CM_MASK); + u32TempVal |= (uint32_t)(SCG_FIRCCSR_TRUP(pFircConfig->bTrEn) | /* configure TRUP and EN together with TREN setting */ + SCG_FIRCCSR_TREN(pFircConfig->bTrEn) | + SCG_FIRCCSR_STEN(pFircConfig->bSten)); + SCG_HWA_SetFircCsr(u32TempVal); + + /* Configure DIV value */ + SCG_HWA_DiableFircDiv(SCG_CLOCK_DIV_ALL); + u32TempVal = SCG_HWA_GetClockDiv(SCG_FIRC_CLOCK_SYMBOL); + u32TempVal &= ~(uint32_t)(SCG_FIRCDIV_DIVL_MASK | SCG_FIRCDIV_DIVM_MASK | SCG_FIRCDIV_DIVH_MASK); + u32TempVal |= (SCG_FIRCDIV_DIVH(pFircConfig->eDivH) | SCG_FIRCDIV_DIVM(pFircConfig->eDivM) | SCG_FIRCDIV_DIVL( + pFircConfig->eDivL)); + SCG_HWA_SetFircDiv(u32TempVal) ; + + /* Set CSR[EN] bit to 1 */ + SCG_HWA_EnableFirc(); + + /* Wait FIRC valid */ + u32TempVal = FIRC_STABILIZATION_TIMEOUT; + SCG_CheckClockAckStatus((false == SCG_HWA_GetClockVliad(SCG_FIRC_CLOCK_SYMBOL)), u32TempVal, eStatusVal) + + if (eStatusVal == SCG_STATUS_SUCCESS) + { + if (pFircConfig->bCm) + { + SCG_HWA_EnableFircClockMonitor(); + } + + if (pFircConfig->bLock) + { + /* lock CSR register */ + SCG_HWA_LockFircCsrReg(); + } + + /* Enable DIV */ + u32FircDivEn |= (pFircConfig->eDivH != SCG_ASYNC_CLOCK_DISABLE) ? (uint32_t)SCG_CLOCK_DIV_H : 0U; + u32FircDivEn |= (pFircConfig->eDivM != SCG_ASYNC_CLOCK_DISABLE) ? (uint32_t)SCG_CLOCK_DIV_M : 0U; + SCG_HWA_EnableFircDiv((SCG_DivEnableType)u32FircDivEn); + + /* Wait DIV[ACK] change to 1 */ + u32TempVal = CLOCK_DIV_STABILIZATION_TIMEOUT; + SCG_CheckClockAckStatus((SCG_HWA_GetSircDivAck((SCG_DivEnableType)u32FircDivEn) != true), u32TempVal, eStatusVal) + + /* For clock auto trim, set TREN to True together with TRUP to True */ + if (pFircConfig->bTrEn == true) + { + /* set FIRCTCFG trim configuration */ + if (pFircConfig->u8TrimSrc == (uint8_t)SCG_IRC_TRIMSRC_FOSC) + { + /* Trim clock source choose FOSC */ + u16TrimDiv = (uint16_t)(FOSC_FREQUENCY / 250000U - 1U); + } + else if (pFircConfig->u8TrimSrc == (uint8_t)SCG_IRC_TRIMSRC_SOSC) + { + /* Trim clock source choose SOSC */ + u16TrimDiv = 0U; + } + else + { + /* do nothing */ + } + u32TempVal = (uint32_t)(SCG_FIRCTCFG_TRIMSRC(pFircConfig->u8TrimSrc) | SCG_FIRCTCFG_TRIMDIV(u16TrimDiv)); + SCG_HWA_SetFircTcfg(u32TempVal); + } + else + { + /* Trim disabled, just using IC internal IRC trim value */ + } + + } + else + { + /* Clear CSR configuration */ + SCG_HWA_SetFircCsr(0U); + + /* Clear DIV configuration*/ + SCG_HWA_SetFircDiv(0U); + } + } + return eStatusVal; +} + +/** + * @brief Disable FIRC + * + * @return SCG_StatusType function status + */ +SCG_StatusType SCG_DisableFIRC(void) +{ + SCG_StatusType eStatusVal = SCG_STATUS_SUCCESS; + uint32_t u32TempVal; + uint8_t u8ClkSrc; + + u8ClkSrc = SCG_HWA_GetSysClkSrc(); + if ((uint8_t)SCG_CLOCK_SRC_FIRC == u8ClkSrc) + { + eStatusVal = SCG_STATUS_SEQUENCE_ERROR; + } + else if ((SCG_HWA_GetPllSrc(SCG_PLL0_CLOCK_SYMBOL) == (uint8_t)SCG_PLLSOURCE_FIRC) && ((uint8_t)SCG_CLOCK_SRC_PLL0 == u8ClkSrc)) + { + eStatusVal = SCG_STATUS_SEQUENCE_ERROR; + } + else + { + /* do nothing */ + } + + if (eStatusVal == SCG_STATUS_SUCCESS) + { + /* Unlock CSR register */ + SCG_HWA_UnlockFircCsrReg(); + + /* Disable FIRC */ + SCG_HWA_DisableFirc(); + + /* Wait FIRC not valid */ + u32TempVal = FIRC_STABILIZATION_TIMEOUT; + SCG_CheckClockAckStatus((true == SCG_HWA_GetClockVliad(SCG_FIRC_CLOCK_SYMBOL)), u32TempVal, eStatusVal) + + if (eStatusVal == SCG_STATUS_SUCCESS) + { + /* Clear CSR register */ + SCG_HWA_SetFircCsr(0U); + + /* In order to avoid the DIV register value not cleared, Clear FIRC DIV register twice */ + SCG_HWA_SetFircDiv(0U); + SCG_HWA_SetFircDiv(0U); + } + } + return eStatusVal; +} + + +/** + * @brief Enable PLL + * + * @param ePLL PLL instance + * @param pPllConfig PLL configuration + * @return SCG_StatusType function status + */ +SCG_StatusType SCG_EnablePLL(const SCG_PllClkType ePll, const SCG_PllType *const pPllConfig) +{ + SCG_StatusType eStatusVal = SCG_STATUS_SUCCESS; + + DEV_ASSERT(NULL_PTR != pPllConfig); + DEV_ASSERT(((ePll == SCG_PLL0) || (ePll == SCG_PLL1))); + DEV_ASSERT(((pPllConfig->eSrc == SCG_PLLSOURCE_FOSC) || (pPllConfig->eSrc == SCG_PLLSOURCE_FIRC))); + DEV_ASSERT((pPllConfig->u16Mult > 95U) && (pPllConfig->u16Mult < 512U)); + DEV_ASSERT(pPllConfig->u8Prediv < 32U); + DEV_ASSERT(pPllConfig->u8Prediv != 2U); + DEV_ASSERT((pPllConfig->ePstDiv == SCG_PLLPSTDIV_BY2) || + (pPllConfig->ePstDiv == SCG_PLLPSTDIV_BY4) || + (pPllConfig->ePstDiv == SCG_PLLPSTDIV_BY8)); + DEV_ASSERT(pPllConfig->eDivH <= (uint32_t)SCG_ASYNCCLOCKDIV_BY64); + DEV_ASSERT(pPllConfig->eDivM <= (uint32_t)SCG_ASYNCCLOCKDIV_BY64); + DEV_ASSERT(pPllConfig->eDivL <= (uint32_t)SCG_ASYNCCLOCKDIV_BY64); + + + if ((true != SCG_HWA_GetClockVliad(SCG_FOSC_CLOCK_SYMBOL)) && (SCG_PLLSOURCE_FOSC == pPllConfig->eSrc)) + { + eStatusVal = SCG_STATUS_SEQUENCE_ERROR; + } + else if ((true != SCG_HWA_GetClockVliad(SCG_FIRC_CLOCK_SYMBOL)) && (SCG_PLLSOURCE_FIRC == pPllConfig->eSrc)) + { + eStatusVal = SCG_STATUS_SEQUENCE_ERROR; + } + else + { + /* do nothing */ + } + + if (eStatusVal == SCG_STATUS_SUCCESS) + { + if (SCG_PLL0 == ePll) + { + eStatusVal = SCG_EnablePLL0(pPllConfig); + } + else if (SCG_PLL1 == ePll) + { + eStatusVal = SCG_EnablePLL1(pPllConfig); + } + else + { + /* do nothing */ + } + } + + return eStatusVal; +} + +/** + * @brief Disable PLL + * + * @param ePll PLL instance + * @return SCG_StatusType function status + */ +SCG_StatusType SCG_DisablePLL(const SCG_PllClkType ePll) +{ + SCG_StatusType eStatusVal = SCG_STATUS_SUCCESS; + + if (SCG_PLL0 == ePll) + { + if (SCG_HWA_GetSysClkSrc() == (uint8_t)SCG_CLOCK_SRC_PLL0) + { + eStatusVal = SCG_STATUS_SEQUENCE_ERROR; + } + else + { + eStatusVal = SCG_DisablePLL0(); + } + } + else + { + /* (SCG_PLL1 == ePll) */ + eStatusVal = SCG_DisablePLL1(); + } + + return eStatusVal; +} + +/** + * @brief Set system run time clock and related CORE/BUS/SLOW clock. + * + * @param pSysClkConfig pointer to the clockCtrlType structure data instance,which defined for system clock selection. + * @return SCG_StatusType function status + * SCG_STATUS_SUCCESS : clock source and dividers are valid,and switch system clock successfully + * SCG_STATUS_SEQUENCE_ERROR: new clock source is not enabled + * SCG_STATUS_PARAM_ERROR: the core bus slow divider are invalid + * SCG_STATUS_TIMEOUT: switch system clock procedure time out + */ +SCG_StatusType SCG_SetClkCtrl(const SCG_ClockCtrlType *const pSysClkConfig) +{ + DEV_ASSERT(NULL_PTR != pSysClkConfig); + + return SCG_SwitchSystemClockWithConfig(pSysClkConfig->eSrc,pSysClkConfig); +} + +/** + * @brief Get clock frequency + * + * @param eScgClockName Clock source type + * @return uint32_t frequency value + */ +uint32_t SCG_GetScgClockFreq(const SCG_ClkSrcType eScgClockName) +{ + uint32_t u32Freq; + DEV_ASSERT(eScgClockName < SCG_END_OF_CLOCKS); + + if ((SCG_CORE_CLK == eScgClockName) || + (SCG_BUS_CLK == eScgClockName) || + (SCG_SLOW_CLK == eScgClockName)) + { + u32Freq = SCG_CalculateSystemFreq(eScgClockName); + } + else if ((SCG_SIRC_CLK == eScgClockName) || + (SCG_SIRCDIVH_CLK == eScgClockName) || + (SCG_SIRCDIVM_CLK == eScgClockName) || + (SCG_SIRCDIVL_CLK == eScgClockName)) + { + u32Freq = SCG_CalculateSircFreq(eScgClockName); + } + else if ((SCG_FIRC_CLK == eScgClockName) || + (SCG_FIRCDIVH_CLK == eScgClockName) || + (SCG_FIRCDIVM_CLK == eScgClockName) || + (SCG_FIRCDIVL_CLK == eScgClockName)) + { + u32Freq = SCG_CalculateFircFreq(eScgClockName); + } + else if ((SCG_FOSC_CLK == eScgClockName) || + (SCG_FOSCDIVH_CLK == eScgClockName) || + (SCG_FOSCDIVM_CLK == eScgClockName) || + (SCG_FOSCDIVL_CLK == eScgClockName)) + { + u32Freq = SCG_CalculateFoscFreq(eScgClockName); + } + else if ((SCG_PLL0_CLK == eScgClockName) || + (SCG_PLL0DIVH_CLK == eScgClockName) || + (SCG_PLL0DIVM_CLK == eScgClockName) || + (SCG_PLL0DIVL_CLK == eScgClockName)) + { + u32Freq = SCG_CalculatePll0Freq(eScgClockName); + } + else if ((SCG_PLL1_CLK == eScgClockName) || + (SCG_PLL1DIVH_CLK == eScgClockName) || + (SCG_PLL1DIVM_CLK == eScgClockName) || + (SCG_PLL1DIVL_CLK == eScgClockName)) + { + u32Freq = SCG_CalculatePll1Freq(eScgClockName); + } + else if (SCG_SIRC32K_CLK == eScgClockName) + { + u32Freq = SIRC32K_CLOCK; + } + else if (SCG_SOSC_CLK == eScgClockName) + { + u32Freq = SOSC_FREQUENCY; + } + else if (SCG_SCG_CLKOUT_CLK == eScgClockName) + { + u32Freq = SCG_CalculateClkOutFreq(); + } + else if(SCG_NVMINIT_CLK == eScgClockName) + { + u32Freq = NVM_CLOCK; + } + else if(SCG_CMU4REF_CLK == eScgClockName) + { + u32Freq = SCG_CalculateCMU4RefFreq(); + } + else + { + u32Freq = UNKNOWN_CLOCK; + } + + if (UNKNOWN_CLOCK == u32Freq) + { + u32Freq = 0U; + } + + return u32Freq; +} + +/** + * @brief Select clock out source + * + * @param eClkoutSel clock out source + */ +void SCG_SetClkOut(const SCG_ClockoutSrcType eClkoutSel) +{ + DEV_ASSERT(eClkoutSel <= SCG_CLOCKOUT_SRC_SIRC32K); + + SCG_HWA_SetClkOutSel((uint8_t)eClkoutSel); +} + +/** + * @brief Select NVM clock source + * + * @param eNvmClkSrc NVM clock source + * @return uint32_t function status + */ +SCG_StatusType SCG_SetNvmClk(const SCG_NvmClkSrcType eNvmClkSrc) +{ + SCG_StatusType eStatusVal = SCG_STATUS_SUCCESS; + DEV_ASSERT((eNvmClkSrc == SCG_NVMCLK_SRC_SIRC) || (eNvmClkSrc == SCG_NVMCLK_SRC_FIRC)); + + if ((true != SCG_HWA_GetClockVliad(SCG_FIRC_CLOCK_SYMBOL)) && (eNvmClkSrc == SCG_NVMCLK_SRC_FIRC)) + { + eStatusVal = SCG_STATUS_SEQUENCE_ERROR; + } + + if (eStatusVal == SCG_STATUS_SUCCESS) + { + SCG_HWA_SetNvmClk(((uint32_t)1U << eNvmClkSrc)); + } + + return eStatusVal; +} + +/** + * @brief Select CMU4 clock source + * + * @param eCmu4ClkSrc CMU4 clock source + * @return SCG_StatusType function status + */ +SCG_StatusType SCG_SetCmu4Clk(const SCG_Cmu4ClkSrcType eCmu4ClkSrc) +{ + SCG_StatusType eStatusVal = SCG_STATUS_SUCCESS; + DEV_ASSERT((eCmu4ClkSrc == SCG_CMU4CLK_SRC_SIRC) || (eCmu4ClkSrc == SCG_CMU4CLK_SRC_FOSC)); + + if ((true != SCG_HWA_GetClockVliad(SCG_FOSC_CLOCK_SYMBOL)) && (eCmu4ClkSrc == SCG_CMU4CLK_SRC_FOSC)) + { + eStatusVal = SCG_STATUS_SEQUENCE_ERROR; + } + + if (eStatusVal == SCG_STATUS_SUCCESS) + { + SCG_HWA_SetCmu4Clk(((uint32_t)1U << eCmu4ClkSrc)); + } + return eStatusVal; +} + +/** + * @brief Generate the origion SCG register CRC result, and configure the SCG register CRC option. + * + * @param eMode The SCG register CRC trigger mode + * @return CRC configure status + * SCG_STATUS_SUCCESS : CRC configure successfully + * SCG_STATUS_TIMEOUT : CRC configure time out + */ +SCG_StatusType SCG_RegCrcConfig(SCG_CrcModeType eMode) +{ + SCG_StatusType eStatusVal = SCG_STATUS_SUCCESS; + uint32_t u32Timeout = 0xFFFFU; + + DEV_ASSERT((eMode == SCG_CRC_SW_MODE) || (eMode == SCG_CRC_TRIGGER_MODE)); + + /* Deinit CRC register */ + SCG_HWA_DisableCrcCheck(); + SCG_HWA_DisableCrcTriggerMode(); + SCG_HWA_DisableCrcErrorOutput(); + SCG_HWA_ClearCrcErrorFlag(); + + /* Generate original CRC result */ + SCG_HWA_GenCrcVal(); + while (SCG_HWA_GetCrcBusyStatus() == true) + { + u32Timeout--; + if (u32Timeout == 0U) + { + eStatusVal = SCG_STATUS_TIMEOUT; + break; + } + } + + if (eStatusVal == SCG_STATUS_SUCCESS) + { + if (eMode == SCG_CRC_TRIGGER_MODE) + { + SCG_HWA_EnableCrcTriggerMode(); + } + + /* Enable SCG CRC error to FCSMU in CSC0_SMU_CTRL4[SCG_CRC] */ + CSC0_HWA_CTRL4_EnableReqToSMU(CSC_SMU_SCG_CRC); + /* Generate CRC error output */ + SCG_HWA_EnableCrcErrorOutput(); + /* Generate CRC check */ + SCG_HWA_EnableCrcCheck(); + } + return eStatusVal; +} + +/** + * @brief Trigger the SCG register CRC generation by software + * + */ +void SCG_RegCrcGenerate(void) +{ + SCG_HWA_GenCrcVal(); +} + +/** + * @brief Trigger the SCG register CRC generation by software,and wait the CRC check result + * + * @return CRC check result + */ +SCG_CrcCheckResType SCG_RegCrcGenerateWaitResult(void) +{ + SCG_CrcCheckResType eStatusVal = SCG_CRC_CHECK_SUCCESS; + uint32_t u32Timeout = 0xFFFFU; + + SCG_HWA_GenCrcVal(); + while (SCG_HWA_GetCrcBusyStatus() == true) + { + u32Timeout--; + if (u32Timeout == 0U) + { + eStatusVal = SCG_CRC_GEN_TIMEOUT; + break; + } + } + + /* Check CRC is success or not */ + if (SCG_HWA_GetCrcErrorStatus()) + { + eStatusVal = SCG_CRC_CHECK_FAILED; + } + + return eStatusVal; +} + +/** + * @brief Clock source De-init + * + * @return SCG_StatusType function status + */ +SCG_StatusType SCG_Deinit(void) +{ + SCG_StatusType eStatusVal = SCG_STATUS_SUCCESS; + SCG_FircType tFircCfg = + { + .bLock = false, + .bCm = false, + .bTrEn = false, + .bSten = false, + .u8TrimSrc = 0U, + .eDivL = SCG_ASYNCCLOCKDIV_BY4, + .eDivM = SCG_ASYNCCLOCKDIV_BY2, + .eDivH = SCG_ASYNCCLOCKDIV_BY1 + }; + + if (SCG_HWA_GetSysClkSrc() != (uint8_t)SCG_CLOCK_SRC_FIRC) + { + eStatusVal = SCG_SwitchSystemClockWithConfig(SCG_CLOCK_SRC_FIRC,NULL_PTR); + if (SCG_STATUS_SEQUENCE_ERROR == eStatusVal) + { + eStatusVal = SCG_EnableFIRC(&tFircCfg); + if (SCG_STATUS_TIMEOUT != eStatusVal) + { + eStatusVal = SCG_SwitchSystemClockWithConfig(SCG_CLOCK_SRC_FIRC,NULL_PTR); + } + } + } + + if (SCG_STATUS_SUCCESS == eStatusVal) + { + /* Disable all clock source */ + (void)SCG_DisablePLL(SCG_PLL1); + (void)SCG_DisablePLL(SCG_PLL0); + (void)SCG_DisableFOSC(); + (void)SCG_DisableSOSC(); + (void)SCG_DisableSIRC32K(); + } + + return eStatusVal; +} + diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_scm.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_scm.c new file mode 100644 index 0000000..2b0edfa --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_scm.c @@ -0,0 +1,482 @@ +/** + * @file fc7xxx_driver_scm.h + * @author Flagchip + * @brief FC7xxx csc driver type definition and API + * @version 0.1.0 + * @date 2024-01-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ + +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-01-12 Flagchip085 N/A First version for FC7240 + ******************************************************************************** */ + +#include "fc7xxx_driver_scm.h" + +/** + * @brief Get unique identification for the chip, loaded from NVR. + * + * @param pUid Pointer to UID + * + */ +void SCM_GetChip_UID(uint32 *pUid) +{ + DEV_ASSERT(NULL_PTR != pUid); + + pUid[0] = SCM_HWA_GetData_UIDL(); + pUid[1] = SCM_HWA_GetData_UIDML(); + pUid[2] = SCM_HWA_GetData_UIDMH(); + pUid[3] = SCM_HWA_GetData_UIDH(); +} + +/** + * @brief Get CCMx status. + * + * @param eCCMType CCM type + * @param u32Value selection to get + * + */ +uint32_t SCM_GetStatus_CCMx(SCM_CCM_Type eCCMType, uint32_t u32Value) +{ + uint32_t u32Temp; + + DEV_ASSERT(eCCMType == SCM_CCM0); + DEV_ASSERT((u32Value & SCM_CCM0_STATUS_MASK) == 0U); + + if (SCM_CCM0 == eCCMType) + { + u32Temp = SCM_HWA_GetStatus_CCM0(); + } + + return (u32Temp & u32Value); +} + +/** + * @brief Get matrix status. + * + * @param eMatrixType Matrix type + * @param u32Value selection to get + * + */ +uint32_t SCM_GetStatus_Matrix(SCM_MatrixStatusType eMatrixType, uint32_t u32Value) +{ + uint32_t u32Temp; + DEV_ASSERT((uint32_t)eMatrixType <= (uint32_t)SCM_MatrixStatus_ID); + + if (SCM_MatrixStatus_0 == eMatrixType) + { + u32Temp = SCM_HWA_GetStatus_MATRIX_STATUS0(); + } + else if (SCM_MatrixStatus_1 == eMatrixType) + { + u32Temp = SCM_HWA_GetStatus_MATRIX_STATUS1(); + } + else if (SCM_MatrixStatus_2 == eMatrixType) + { + u32Temp = SCM_HWA_GetStatus_MATRIX_STATUS2(); + } + else if (SCM_MatrixStatus_5 == eMatrixType) + { + u32Temp = SCM_HWA_GetStatus_MATRIX_STATUS5(); + } + else if (SCM_MatrixStatus_6 == eMatrixType) + { + u32Temp = SCM_HWA_GetStatus_MATRIX_STATUS6(); + } + else if (SCM_MatrixStatus_7 == eMatrixType) + { + u32Temp = SCM_HWA_GetStatus_MATRIX_STATUS7(); + } + else + { + u32Temp = SCM_HWA_GetStatus_MATRIX_ID_STATUS0(); + } + + return (u32Temp & u32Value); +} + +/** + * @brief Set cpu to control MAM ECC enable register 0. + * + * @param eCpuType Cpu to use + * @param bLockStatus Lock the cpu control settings + * + * @return Set operation success/failed + */ +SCM_RetStatusType SCM_SetCpuCtrl_MAMECCR0(const SCM_WPB_CpuType eCpuType, bool bLockStatus) +{ + SCM_RetStatusType eRetVal; + DEV_ASSERT((uint32_t)eCpuType < (uint32_t)SCM_WP_CPU_NONE); + + if (0U == SCM_HWA_MAMECCEN0_GetWPBLockStatus()) + { + SCM_HWA_MAMECCEN0_SetCpuWritePermit(eCpuType); + + if (true == bLockStatus) + { + /* Lock the cpu to control settings until reset */ + SCM_HWA_MAMECCEN0_LockWritePermit(); + } + + eRetVal = SCM_E_OK; + } + else + { + eRetVal = SCM_E_LOCK; + } + + return eRetVal; +} + +/** + * @brief Set cpu to control MAM ECC enable register 1. + * + * @param eCpuType Cpu to use + * @param bLockStatus Lock the cpu control settings + * + * @return Set operation success/failed + */ +SCM_RetStatusType SCM_SetCpuCtrl_MAMECCR1(const SCM_WPB_CpuType eCpuType, bool bLockStatus) +{ + SCM_RetStatusType eRetVal; + DEV_ASSERT((uint32_t)eCpuType < (uint32_t)SCM_WP_CPU_NONE); + + if (0U == SCM_HWA_MAMECCEN1_GetWPBLockStatus()) + { + SCM_HWA_MAMECCEN1_SetCpuWritePermit(eCpuType); + + if (true == bLockStatus) + { + /* Lock the cpu to control settings until reset */ + SCM_HWA_MAMECCEN1_LockWritePermit(); + } + + eRetVal = SCM_E_OK; + } + else + { + eRetVal = SCM_E_LOCK; + } + + return eRetVal; +} + +/** + * @brief Set cpu to control CPU0 ECC enable register. + * + * @param eCpuType Cpu to use + * @param bLockStatus Lock the cpu control settings + * + * @return Set operation success/failed + */ +SCM_RetStatusType SCM_SetCpuCtrl_CPU0ECCEN(const SCM_WPB_CpuType eCpuType, bool bLockStatus) +{ + SCM_RetStatusType eRetVal; + DEV_ASSERT((uint32_t)eCpuType < (uint32_t)SCM_WP_CPU_NONE); + + if (0U == SCM_HWA_CPU0ECCEN_GetWPBLockStatus()) + { + SCM_HWA_CPU0ECCEN_SetCpuWritePermit(eCpuType); + + if (true == bLockStatus) + { + /* Lock the cpu to control settings until reset */ + SCM_HWA_CPU0ECCEN_LockWritePermit(); + } + + eRetVal = SCM_E_OK; + } + else + { + eRetVal = SCM_E_LOCK; + } + + return eRetVal; +} + +/** + * @brief Set cpu to control SOCMISC register. + * + * @param eCpuType Cpu to use + * @param bLockStatus Lock the cpu control settings + * + * @return Set operation success/failed + */ +SCM_RetStatusType SCM_SetCpuCtrl_SOCMISC(const SCM_WPB_CpuType eCpuType, bool bLockStatus) +{ + SCM_RetStatusType eRetVal; + + if (0U == SCM_HWA_SOCMISC_GetWPBLockStatus()) + { + SCM_HWA_SOCMISC_SetCpuWritePermit(eCpuType); + + if (true == bLockStatus) + { + /* Lock the cpu to control settings until reset */ + SCM_HWA_SOCMISC_LockWritePermit(); + } + + eRetVal = SCM_E_OK; + } + else + { + eRetVal = SCM_E_LOCK; + } + + return eRetVal; +} + +/** + * @brief Set cpu to control Subsystem pcc register. + * + * @param eCpuType Cpu to use + * @param bLockStatus Lock the cpu control settings + * + * @return Set operation success/failed + */ +SCM_RetStatusType SCM_SetCpuCtrl_SUBSYS_PCC(const SCM_WPB_CpuType eCpuType, bool bLockStatus) +{ + SCM_RetStatusType eRetVal; + + if (0U == SCM_HWA_SUBSYS_PCC_GetWPBLockStatus()) + { + SCM_HWA_SUBSYS_PCC_SetCpuWritePermit(eCpuType); + + if (true == bLockStatus) + { + /* Lock the cpu to control settings until reset */ + SCM_HWA_SUBSYS_PCC_LockWritePermit(); + } + + eRetVal = SCM_E_OK; + } + else + { + eRetVal = SCM_E_LOCK; + } + + return eRetVal; +} + +/** + * @brief Set cpu to control master halt request register. + * + * @param eCpuType Cpu to use + * @param bLockStatus Lock the cpu control settings + * + * @return Set operation success/failed + */ +SCM_RetStatusType SCM_SetCpuCtrl_MASTER_HALT_REQ(const SCM_WPB_CpuType eCpuType, bool bLockStatus) +{ + SCM_RetStatusType eRetVal; + + if (0U == SCM_HWA_MASTER_HALT_REQ_GetWPBLockStatus()) + { + SCM_HWA_MASTER_HALT_REQ_SetCpuWritePermit(eCpuType); + + if (true == bLockStatus) + { + /* Lock the cpu to control settings until reset */ + SCM_HWA_MASTER_HALT_REQ_LockWritePermit(); + } + + eRetVal = SCM_E_OK; + } + else + { + eRetVal = SCM_E_LOCK; + } + + return eRetVal; +} + +/** + * @brief Set lock FTU_ROUTING register. + * + */ +void SCM_SetLock_FTU_ROUTING(void) +{ + if (0U == SCM_HWA_FTU_ROUTING_GetLockStatus()) + { + SCM_HWA_LockFTU_ROUTING(); + } +} + +/** + * @brief Set lock FTU_GTB register. + * + */ +void SCM_SetLock_FTU_GTB(void) +{ + if (0U == SCM_HWA_FTU_GTB_GetLockStatus()) + { + SCM_HWA_LockFTU_GTB(); + } +} + +/** + * @brief Set lock DEBUG_TRACE register. + * + */ +void SCM_SetLock_DEBUG_TRACE(void) +{ + if (0U == SCM_HWA_DEBUG_TRACE_GetLockStatus()) + { + SCM_HWA_LockDEBUG_TRACE(); + } +} + +/** + * @brief Set lock FLEXCAN_ROUTING register. + * + */ +void SCM_SetLock_FLEXCAN_ROUTING(void) +{ + if (0U == SCM_HWA_FLEXCAN_ROUTING_GetLockStatus()) + { + SCM_HWA_LockFLEXCAN_ROUTING(); + } +} + +/** + * @brief Set lock MSC0_ROUTING register. + * + */ +void SCM_SetLock_MSC0_ROUTING(void) +{ + if (0U == SCM_HWA_MSC0_ROUTING_GetLockStatus()) + { + SCM_HWA_LockMSC0_ROUTING(); + } +} + +/** + * @brief Set lock INT_ROUTER_NMI register. + * + */ +void SCM_SetLock_INT_ROUTER_NMI(void) +{ + if (0U == SCM_HWA_INT_ROUTER_NMI_GetLockStatus()) + { + SCM_HWA_LockINT_ROUTER_NMI(); + } +} + +/** + * @brief Set NMI interrupt router . + * + * @param eCpuType Cpu to use + * @param bEnable Enable/Disable + * @return Set operation success/failed + */ +SCM_RetStatusType SCM_SetEnable_NMIIntRouter(const SCM_WPB_CpuType eCpuType, bool bEnable) +{ + SCM_RetStatusType eRetVal; + + if (SCM_WP_CPU_0 == eCpuType) + { + SCM_HWA_SetEnable_Cpu0NMIIrqRouter(bEnable); + eRetVal = SCM_E_OK; + } + else + { + eRetVal = SCM_E_PARAM; + } + + return eRetVal; +} + +/** + * @brief Generate the origion SCM register CRC result, and configure the SCM register CRC option. + * + * @param eMode The SCM register CRC trigger mode + * @return CRC configure status + * SCM_E_OK : CRC configure successfully + * SCM_E_TIMEOUT : CRC configure time out + */ +SCM_RetStatusType SCM_RegCrcConfig(SCM_CrcModeType eMode) +{ + SCM_RetStatusType eStatusVal = SCM_E_OK; + uint32_t u32Timeout = 0xFFFFU; + + DEV_ASSERT((eMode == SCM_CRC_SW_MODE) || (eMode == SCM_CRC_TRIGGER_MODE)); + + /* Deinit CRC register */ + SCM_HWA_SetEnable_CrcCheck(false); + SCM_HWA_SetEnable_CrcTrigger(false); + SCM_HWA_SetEnable_CrcErrOut(false); + SCM_HWA_ClearCrcErrorFlag(); + + /* Generate original CRC result */ + SCM_HWA_SetEnable_CrcSwGen(true); + while (SCM_HWA_GetStatus_CrcBusyFlag() != 0U) + { + u32Timeout--; + if (u32Timeout == 0U) + { + eStatusVal = SCM_E_TIMEOUT; + break; + } + } + + if (eStatusVal == SCM_E_OK) + { + if (eMode == SCM_CRC_TRIGGER_MODE) + { + SCM_HWA_SetEnable_CrcTrigger(true); + } + + /* Enable SCM CRC error to FCSMU in CSC0_SMU_CTRL4[SCM_CRC] */ + CSC0_HWA_CTRL4_EnableReqToSMU(CSC_SMU_SCM_CRC); + /* Generate CRC error output */ + SCM_HWA_SetEnable_CrcErrOut(true); + /* Generate CRC check */ + SCM_HWA_SetEnable_CrcCheck(true); + } + return eStatusVal; +} + +/** + * @brief Trigger the SCM register CRC generation by software + * + */ +void SCM_RegCrcGenerate(void) +{ + SCM_HWA_SetEnable_CrcSwGen(true); +} + +/** + * @brief Trigger the SCM register CRC generation by software,and wait the CRC check result + * + * @return CRC check result + */ +SCM_RetStatusType SCM_RegCrcGenerateWaitResult(void) +{ + SCM_RetStatusType eStatusVal = SCM_E_OK; + uint32_t u32Timeout = 0xFFFFU; + + SCM_HWA_SetEnable_CrcSwGen(true); + while (SCM_HWA_GetStatus_CrcBusyFlag() != 0U) + { + u32Timeout--; + if (u32Timeout == 0U) + { + eStatusVal = SCM_E_TIMEOUT; + break; + } + } + + /* Check CRC is success or not */ + if (0U != SCM_HWA_GetStatus_CrcErrFlag()) + { + eStatusVal = SCM_E_CRC; + } + + return eStatusVal; +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_scst.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_scst.c new file mode 100644 index 0000000..e6388b9 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_scst.c @@ -0,0 +1,230 @@ +/** + * @file fc7xxx_driver_scst.c + * @author Flagchip + * @brief FC7xxx scst driver source code + * @version 0.1.0 + * @date 2023-12-29 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + */ +/********************************************************************************* +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2023-12-29 qxw074 N/A First version for FC7240 +******************************************************************************** */ + +#include "fc7xxx_driver_scst.h" + +/** + * @brief The address of the specific implementation of the M7ST API + * + */ +#define M7ST_ROM_BASE 0x04812800 + +/** + * @brief The SCST Atomic Test function prototype + * + */ +typedef Type_M7ST_AtomicStatus (*Type_M7ST_RegressionTest) (uint32_t TestStart, uint32_t TestEnd, uint32_t InjectEnable, uint32_t RamBase); + +/** + * @brief The SCST Run selected tests function prototype + * + */ +typedef Type_M7ST_AtomicStatus (*Type_M7ST_AtomicTest) (uint32_t TestID, uint32_t InjectEnable, uint32_t RamBase); + +/** + * @brief M7ST API structure + * + */ +typedef struct Struct_M7ST_RomTable +{ + Type_M7ST_RegressionTest RegressionTest; + Type_M7ST_AtomicTest AluTest; + Type_M7ST_AtomicTest AluMLATest; + Type_M7ST_AtomicTest AluSHIFTTest; + Type_M7ST_AtomicTest AluTest1; + Type_M7ST_AtomicTest AluTest2; + Type_M7ST_AtomicTest AluTest3; + Type_M7ST_AtomicTest AluTest4; + Type_M7ST_AtomicTest AluTest5; + Type_M7ST_AtomicTest AluTest6; + Type_M7ST_AtomicTest RegbankTest1; + Type_M7ST_AtomicTest RegbankTest2; + Type_M7ST_AtomicTest RegbankTest3; + Type_M7ST_AtomicTest RegbankTest4; + Type_M7ST_AtomicTest RegbankTest5; + Type_M7ST_AtomicTest RegbankTest6; + Type_M7ST_AtomicTest LoadStoreTest1; + Type_M7ST_AtomicTest LoadStoreTest2; + Type_M7ST_AtomicTest LoadStoreTest3; + Type_M7ST_AtomicTest LoadStoreTest4; + Type_M7ST_AtomicTest LoadStoreTest5; + Type_M7ST_AtomicTest LoadStoreTest6; + Type_M7ST_AtomicTest SimdSatTest1; + Type_M7ST_AtomicTest SimdSatTest2; + Type_M7ST_AtomicTest SimdSatTest3; + Type_M7ST_AtomicTest SimdSatTest4; + Type_M7ST_AtomicTest MacTest1; + Type_M7ST_AtomicTest MacTest2; + Type_M7ST_AtomicTest FetchTest; + Type_M7ST_AtomicTest StatusTest1; + Type_M7ST_AtomicTest StatusTest2; + Type_M7ST_AtomicTest BranchTest1; + Type_M7ST_AtomicTest BranchTest2; +} Type_M7ST_RomTable; + +/** + * @brief This function is used to get the result of the executed test + * + * @param test_index is test number,0U..32U + * @param s_u32RamBase The first address of the 1k memory that the program needs to run + * @return M7ST_ErrorM7ST_TestPass is ok, others are not ok + */ +Type_M7ST_AtomicStatus SCST_ExecuteTest(SCST_TestIndexType test_index,uint32_t *s_u32RamBase) +{ + Type_M7ST_AtomicStatus Status = M7ST_FaultInjectError; + Type_M7ST_RomTable *M7ST_RomEntry = (Type_M7ST_RomTable *)M7ST_ROM_BASE; + switch(test_index) + { + case M7ST_AluTest: + Status = M7ST_RomEntry->AluTest(0,0,(uint32_t)&s_u32RamBase[0]); + break; + + case M7ST_AluMLATest: + Status = M7ST_RomEntry->AluMLATest(1,0,(uint32_t)&s_u32RamBase[0]); + break; + + case M7ST_AluSHIFTTest: + Status = M7ST_RomEntry->AluSHIFTTest(2,0,(uint32_t)&s_u32RamBase[0]); + break; + + case M7ST_AluTes1t: + Status = M7ST_RomEntry->AluTest1(3,0,(uint32_t)&s_u32RamBase[0]); + break; + + case M7ST_AluTest2: + Status = M7ST_RomEntry->AluTest2(4,0,(uint32_t)&s_u32RamBase[0]); + break; + + case M7ST_AluTest3: + Status = M7ST_RomEntry->AluTest3(5,0,(uint32_t)&s_u32RamBase[0]); + break; + + case M7ST_AluTest4: + Status = M7ST_RomEntry->AluTest4(6,0,(uint32_t)&s_u32RamBase[0]); + break; + + case M7ST_AluTest5: + Status = M7ST_RomEntry->AluTest5(7,0,(uint32_t)&s_u32RamBase[0]); + break; + + case M7ST_AluTest6: + Status = M7ST_RomEntry->AluTest6(8,0,(uint32_t)&s_u32RamBase[0]); + break; + + case M7ST_RegbankTest1: + Status = M7ST_RomEntry->RegbankTest1(9,0,(uint32_t)&s_u32RamBase[0]); + break; + + case M7ST_RegbankTest2: + Status = M7ST_RomEntry->RegbankTest2(10,0,(uint32_t)&s_u32RamBase[0]); + break; + + case M7ST_RegbankTest3: + Status = M7ST_RomEntry->RegbankTest3(11,0,(uint32_t)&s_u32RamBase[0]); + break; + + case M7ST_RegbankTest4: + Status = M7ST_RomEntry->RegbankTest4(12,0,(uint32_t)&s_u32RamBase[0]); + break; + + case M7ST_RegbankTest5: + Status = M7ST_RomEntry->RegbankTest5(13,0,(uint32_t)&s_u32RamBase[0]); + break; + + case M7ST_RegbankTest6: + Status = M7ST_RomEntry->RegbankTest6(14,0,(uint32_t)&s_u32RamBase[0]); + break; + + case M7ST_LoadStoreTest1: + Status = M7ST_RomEntry->LoadStoreTest1(15,0,(uint32_t)&s_u32RamBase[0]); + break; + + case M7ST_LoadStoreTest2: + Status = M7ST_RomEntry->LoadStoreTest2(16,0,(uint32_t)&s_u32RamBase[0]); + break; + + case M7ST_LoadStoreTest3: + Status = M7ST_RomEntry->LoadStoreTest3(17,0,(uint32_t)&s_u32RamBase[0]); + break; + + case M7ST_LoadStoreTest4: + Status = M7ST_RomEntry->LoadStoreTest4(18,0,(uint32_t)&s_u32RamBase[0]); + break; + + case M7ST_LoadStoreTest5: + Status = M7ST_RomEntry->LoadStoreTest5(19,0,(uint32_t)&s_u32RamBase[0]); + break; + + case M7ST_LoadStoreTest6: + Status = M7ST_RomEntry->LoadStoreTest6(20,0,(uint32_t)&s_u32RamBase[0]); + break; + + case M7ST_SimdSatTest1: + Status = M7ST_RomEntry->SimdSatTest1(21,0,(uint32_t)&s_u32RamBase[0]); + break; + + case M7ST_SimdSatTest2: + Status = M7ST_RomEntry->SimdSatTest2(22,0,(uint32_t)&s_u32RamBase[0]); + break; + + case M7ST_SimdSatTest3: + Status = M7ST_RomEntry->SimdSatTest3(23,0,(uint32_t)&s_u32RamBase[0]); + break; + + case M7ST_SimdSatTest4: + Status = M7ST_RomEntry->SimdSatTest4(24,0,(uint32_t)&s_u32RamBase[0]); + break; + + case M7ST_MacTest1: + Status = M7ST_RomEntry->MacTest1(25,0,(uint32_t)&s_u32RamBase[0]); + break; + + case M7ST_MacTest2: + Status = M7ST_RomEntry->MacTest2(26,0,(uint32_t)&s_u32RamBase[0]); + break; + + case M7ST_FetchTest: + Status = M7ST_RomEntry->FetchTest(27,0,(uint32_t)&s_u32RamBase[0]); + break; + + case M7ST_StatusTest1: + Status = M7ST_RomEntry->StatusTest1(28,0,(uint32_t)&s_u32RamBase[0]); + break; + + case M7ST_StatusTest2: + Status = M7ST_RomEntry->StatusTest2(29,0,(uint32_t)&s_u32RamBase[0]); + break; + + case M7ST_BranchTest1: + Status = M7ST_RomEntry->BranchTest1(30,0,(uint32_t)&s_u32RamBase[0]); + break; + + case M7ST_BranchTest2: + Status = M7ST_RomEntry->BranchTest2(31,0,(uint32_t)&s_u32RamBase[0]); + break; + + case M7ST_RegressionTest: + Status = M7ST_RomEntry->RegressionTest(0,31,0,(uint32_t)&s_u32RamBase[0]); + break; + + default: + break; + } + return Status; +} + diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_sec.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_sec.c new file mode 100644 index 0000000..a8d20de --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_sec.c @@ -0,0 +1,424 @@ +/** + * @file fc7xxx_driver_sec.c + * @author FlagchipXXX + * @brief FC7xxx SEC driver type definition and API + * @version 0.1.0 + * @date 2024-1-12 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/******************************************************************************** +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2024-1-12 Flagchip113 N/A First version for FC7240 +********************************************************************************/ +#include "fc7xxx_driver_sec.h" + + + + +/** + * @brief This function can be used to enable the Debug mode. + * @return true means enable debug success ,false means enable debug failed. + * */ +bool SEC_EnDebugMode(void) +{ + bool ret = false; + if (SEC_HWA_GetWritePer()) + { + SEC_HWA_EnDebug(); + ret = true; + } + return ret; +} + +/** + * @brief This function can be used to re-enable the Debug mode by the re-enable keys. + * @param keys The Debug mode re-enable keys. + * @return true means re-enable success,false means re-enable failed. + * */ +bool SEC_ReEnDebugMode(ReEnDebug_Keys keys) +{ + bool ret = false; + if (SEC_HWA_GetReEnDebug()) + { + SEC_HWA_ChangeDBK(0u, keys.Re_key0); + SEC_HWA_ChangeDBK(1u, keys.Re_key1); + SEC_HWA_ChangeDBK(2u, keys.Re_key2); + SEC_HWA_ChangeDBK(3u, keys.Re_key3); + ret = true; + } + return ret; +} + +/** + * @brief This function can get the system state (secured or no secured). + * */ +Systemstate SEC_SystemSecureState(void) +{ + Systemstate ret = Securedstate ; + uint16_t sskey0 = SEC_HWA_GetSScontrol0(); + uint16_t sskey1 = SEC_HWA_GetSScontrol1(); + if ((sskey0 == 0xC35AU) && (sskey1 == 0xFFFFU)) + { + ret = UnSecuredstate; + } + return ret ; +} + + +/** + * @brief This function can enable the test mode. + * @return true means enable test mode success,false means enable test mode failed. + * */ +bool SEC_EnTestMode(void) +{ + + bool ret = false; + if (SEC_HWA_GetWritePer()) + { + SEC_HWA_EnTest(); + ret = true; + } + return ret; +} + + + +/** + *@brief This function can Re-enable the test mode by the re-enable key. + *@param key The test mode re-enable key.The key is up to the user to decide in advance. + *@return true means re-enable success,false means re-enable failed. + * */ +bool SEC_ReEnTestMode(uint32_t key) +{ + bool ret = false; + + bool writeper = SEC_HWA_GetWritePer(); + bool reentest = SEC_HWA_GetReEnTest(); + if ((true == writeper) && (true == reentest)) + { + SEC_HWA_ReEnTestKey(key); + ret = true; + } + return ret; +} + + + +/** + * @brief This function can used to set the NVR write and read permission. + * @return true means setPer success,false means setPer failed. + * */ +bool SEC_SetNvrPer(NVR_Per per) +{ + bool ret = false; + if (SEC_HWA_GetWritePer()) + { + + if (per.ReadEn == true) + { + SEC_HWA_EnReadB0NVR(); + } + else + { + SEC_HWA_DisReadB0NVR(); + } + if (per.WritEn == true) + { + SEC_HWA_EnWriteB0NVR(); + } + else + { + SEC_HWA_DisWriteB0NVR(); + } + + if (per.EraseEn == true) + { + SEC_HWA_EnEraseB0NVR(); + } + else + { + SEC_HWA_DisEraseB0NVR(); + } + + ret = true; + } + return ret; +} + + +/** + * @brief Get Secure Boot Enable Status + * + * @return true is enable and false is disable + */ +bool SEC_GetSecureStatus(void) +{ + return SEC_HWA_GetSB(); +} + +/** + * @brief Get ISP Status + * + * @return true is active and false is inactive + */ +bool SEC_GetISPModeStatus(void) +{ + return SEC_HWA_GetIspStatus(); +} + +/** + * @brief Get User setting bootloader address + * + * @return bootloader address + */ +uint32_t SEC_GetBootAddress(void) +{ + return SEC_HWA_GetBLAddr(); +} + + +///** +// * @brief Get the HSM Firmware Address +// * +// * @return the HSM Firmware address +// */ +//uint32_t SEC_GetHsmFwAddress(void) +//{ +// return SEC_HWA_GetHsmAddr(); +//} + + +/** + * @brief Get the lifecycle. + * + * @return the lifecycle. + */ + +SC_LifeCycle SEC_GetLifeCycle(void) +{ + SC_LifeCycle lifecycle = LIFECYCLE_INVALID; + + uint8_t lifecycle_status; + lifecycle_status = SEC_HWA_GetLCStaus(); + + switch (lifecycle_status) + { + case 1u: + lifecycle = LIFECYCLE_OEM_DEV; + break; + case 2u: + lifecycle = LIFECYCLE_OEM_PDT; + break; + case 4u: + lifecycle = LIFECYCLE_INFIELD; + break; + case 8u: + lifecycle = LIFECYCLE_PREFA; + break; + case 16u: + lifecycle = LIFECYCLE_FA; + break; + default: + break; + + } + return lifecycle; +} + + + +/** + * @brief User Key Access Enable. Only valid under non-secure boot + * @return true means User key can be read/programmed/erased by host CPU + * */ +bool SEC_HostUKAccess(void) +{ + return SEC_HWA_GetUKAS(); +} + +/** + * @brief get the Bootloader Verification Algorithm + * @return the Bootloader Verification Algorithm + * */ +BL_VerifyAlgorithm SEC_GetBLVerifyAlgorithm(void) +{ + + return (BL_VerifyAlgorithm)(uint8_t)(SEC_HWA_GetBLVer()); +} + + +/** + * @brief get the Debug/ISP/PREFA Authentication and USRK decryption algorithm + * @return decryption algorithm + * */ +Decryption_Algorithm SEC_GetDecryptAlgorithm(void) +{ + return (Decryption_Algorithm)(uint8_t)(SEC_HWA_GetDecrypt()); + + +} + + +/** + * @brief Indicate the Host User Key Read/Write/Erase Protection + * @param PHostUKAccess the structure for information + * + * */ +void SEC_GetHostUKAccess(HostUKPermission *const PHostUKAccess) +{ + PHostUKAccess->HostUKEraseEn = SEC_HWA_GetHUKErase(); + PHostUKAccess->HostUKReadEn = SEC_HWA_GetHUKRead(); + PHostUKAccess->HostUKWriteEn = SEC_HWA_GetHUKWrite(); +} + +/** + * @brief Indicate the Host NVR Read/Write/Erase Protection + *@param PHostNvrAccess the structure to initialize + * */ +void SEC_GetHostNVRAccess(HostNVRPermission *const PHostNVRAccess) +{ + PHostNVRAccess->HostNVREraseEn = SEC_HWA_GetHostNvrErase(); + PHostNVRAccess->HostNVRReadEn = SEC_HWA_GetHostNvrRead(); + PHostNVRAccess->HostNVRWriteEn = SEC_HWA_GetHostNvrWrite(); + +} + + + +/** + * @brief Get the HSM User Key Erase Protection + * @return true - HSM erase access to User Key region is enabled + * false -HSM erase access to User Key region is disabled + * */ +bool SEC_GethsmUKEraseAccess(void) +{ + return SEC_HWA_GetHsmUKErase(); + +} + + +/** + * @brief Get the HSM NVR Erase Protection + * @return true - HSM erase access to NVR region is enabled + * false -HSM erase access to NVR region is disabled + * */ +bool SEC_GethsmNVREraseAccess(void) +{ + return SEC_HWA_GetHsmNvrErase(); +} + +/** + * @brief Get Bootloader Verification Mask + * @return Bootloader Verification Mask. + * */ +uint32_t SEC_GetBLVerMask(void) +{ + return SEC_HWA_GetBLMask(); +} + +/** + * @brief Get whether Debug Backdoor Key Input Enable. + * @return + * 0011b - User can input DBK through debug mailbox, ISP is not valid. + * 1100b - User can input DBK through ISP, debug mailbox is not valid. + * 1111b - User can input DBK through both debug mailbox and ISP. + * Other Values - User cannot input DBK through both debug mailbox andISP. + * */ +uint32_t SEC_GetDMBDkeyEn(void) +{ + return SEC_HWA_GetMBBKEN(); +} + + +/** + * @brief Host Debug Auth Enable. Only valid in secure boot. (Value loaded from NVR sector) + * @return true means Host debug authentication enable. false means Host debug authentication disable. + */ +bool SEC_GetDebugAuthEn(void) +{ + return SEC_HWA_GetDEAUEn(); +} + + +/** + * @brief Get the isp information. + * @param pIspInfo the structure to information + * @return Get whether operation is success. + * + * */ +SEC_RetType SEC_GetIspInfo(SEC_IspInfo *const pIspInfo) +{ + + SEC_RetType eRet ; + + if (NULL == pIspInfo) + { + eRet = SEC_STATUS_FAILED; + } + else + { + bool ispen = SEC_HWA_GetIspStatus(); + if (!ispen) + { + eRet = SEC_STATUS_FAILED; + } + else + { + pIspInfo->IspModeEn = SEC_HWA_GetIspStatus(); + pIspInfo->IspPinEn = SEC_HWA_GetIspEn(); + pIspInfo->IspAuthEn = SEC_HWA_GetISPAU(); + Isp_Instance ispins = (Isp_Instance)(uint8_t)(SEC_HWA_GetIspIns()); + if ((ispins == ISP_FCUART1) || (ispins == ISP_FCUART3)) + { + pIspInfo->Ispfcuartbaudrate = (FCUART_ISP_BAUDRATE)(uint8_t)(SEC_HWA_GetUartBR()); + pIspInfo->Ispflexcanbaudrate = ISP_FLEXCAN_INVALID; + } + else if ((ispins == ISP_FLEXCAN1) || (ispins == ISP_FLEXCAN5)) + { + pIspInfo->Ispfcuartbaudrate = ISP_FCUART_INVALID; + pIspInfo->Ispflexcanbaudrate = (FLEXCAN_ISP_BAUDRATE)(uint8_t)(SEC_HWA_GetCanBR()); + } + else + { + /*do nothing*/ + } + eRet = SEC_STATUS_SUCCESS; + } + } + return eRet; +} + +/** + * @brief Get the boot information. + * @param pBootInfo the structure for information + * @return Get whether operation is success. + * + * */ +SEC_RetType SEC_GetBootInfo(SEC_BootInfo *const pBootInfo) +{ + + SEC_RetType eRet ; + if (NULL == pBootInfo) + { + eRet = SEC_STATUS_FAILED; + } + else + { + pBootInfo->BootRom = SEC_HWA_GetBootRom(); + pBootInfo->NmiPinEn = SEC_HWA_GetNmiPin(); + pBootInfo->SecBootEn = SEC_HWA_GetSB(); + pBootInfo->OscEn = SEC_HWA_GetOSCAvail(); + pBootInfo->OscFreq = (Osc_FreqInfo)(uint8_t)(SEC_HWA_GetOSCFre()); + pBootInfo->FastBootSpeed = (FastBoot_Speed)(uint8_t)(SEC_HWA_GetFastBootClock()); + eRet = SEC_STATUS_SUCCESS; + } + return eRet; +} + + diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_sent.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_sent.c new file mode 100644 index 0000000..2111c29 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_sent.c @@ -0,0 +1,896 @@ +/** + * @file fc7xxx_driver_sent.c + * @author Flagchip + * @brief FC7xxx SENT driver source code + * @version 0.2.0 + * @date 2022-12-30 + * + * @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Author CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2022-12-14 Flagchip N/A First version for FC7300 SENT + * 0.2.0 2022-12-30 Flagchip N/A Support SPC mode for SENT + ******************************************************************************** */ + +#include "fc7xxx_driver_sent.h" +#include "interrupt_manager.h" +#include "HwA_sent.h" + +#define SENT_GLBL_CTL_PRESCALER_MAX 255U +#define SENT_GLBL_CTL_WATERMARK_MAX 16U + +static SENT_Type* const aSent_Base[] = SENT_BASE_PTRS; +static bool aSentInit[SENT_INSTANCE_COUNT] = {0u}; +static SENT_GBISRCallbackType aGBISRCallback[SENT_INSTANCE_MAX] = {NULL}; +static SENT_CHISRCallbackType aCHISRCallback[SENT_INSTANCE_MAX] = {NULL}; + +void SENT0_IRQHandler(void); +void SENT1_IRQHandler(void); + +static void SENT_IRQ_Handler(const Sent_InstanceType eInstance) +{ + uint8_t u8Channel; + uint32_t u32ChannelStatus; + SENT_Type *pSent = aSent_Base[eInstance]; + + + for(u8Channel = 0U; u8Channel < SENT_CHANNEL_COUNT; u8Channel++) + { + if(true == SENT_HWA_GetChannelReceive(pSent, u8Channel)) + { + if(true == SENT_HWA_GetSLowMessageUnderflowFlag(pSent, u8Channel)) + { + if(NULL != aGBISRCallback[eInstance]) + { + SENT_HWA_ClearSLowMessageUnderflowFlag(pSent, u8Channel); + aGBISRCallback[eInstance]((Sent_ChannelType)u8Channel, SENT_SLOW_MSG_DMA_UF_IT); + } + } + if(true == SENT_HWA_GetFastMessageReadyFlag(pSent, u8Channel)) + { + if(NULL != aGBISRCallback[eInstance]) + { + SENT_HWA_ClearFastMessageReadyFlag(pSent, u8Channel); + aGBISRCallback[eInstance]((Sent_ChannelType)u8Channel, SENT_FAST_MSG_READY_IT); + } + } + if(true == SENT_HWA_GetSlowMessageReadyFlag(pSent, u8Channel)) + { + if(NULL != aGBISRCallback[eInstance]) + { + SENT_HWA_ClearSlowMessageReadyFlag(pSent, u8Channel); + aGBISRCallback[eInstance]((Sent_ChannelType)u8Channel, SENT_SLOW_MSG_READY_IT); + } + } + if(true == SENT_HWA_GetFastMessageFIFOOverflowFlag(pSent, u8Channel)) + { + if(NULL != aGBISRCallback[eInstance]) + { + SENT_HWA_ClearFastMessageFIFOOverflowFlag(pSent, u8Channel); + aGBISRCallback[eInstance]((Sent_ChannelType)u8Channel, SENT_FAST_MSG_FIFO_OF_IT); + } + } + if(true == SENT_HWA_GetFastMessageDMAUnderflowFlag(pSent, u8Channel)) + { + if(NULL != aGBISRCallback[eInstance]) + { + SENT_HWA_ClearFastMessageDMAUnderflowFlag(pSent, u8Channel); + aGBISRCallback[eInstance]((Sent_ChannelType)u8Channel, SENT_FAST_MSG_DMA_DF_IT); + } + } + u32ChannelStatus = SENT_HWA_GetChannelStatus(pSent, u8Channel); + if(0U != u32ChannelStatus) + { + if(NULL != aCHISRCallback[eInstance]) + { + SENT_HWA_ClearChannelStatus(pSent, u8Channel, u32ChannelStatus); + aCHISRCallback[eInstance]((Sent_ChannelType)u8Channel, u32ChannelStatus); + } + } + } + } +} + +Sent_ReturnType SENT_Init(const Sent_InstanceType eInstance, const Sent_ConfigType *pCfg) +{ + Sent_ReturnType eRet = SENT_RETURN_OK; + SENT_Type *pSent; + + if(false == aSentInit[eInstance]) + { + if((NULL != pCfg) && (eInstance < SENT_INSTANCE_MAX) && \ + (pCfg->u8DmaWaterMark <= SENT_GLBL_CTL_WATERMARK_MAX) && \ + (pCfg->u8PreScaler < SENT_GLBL_CTL_PRESCALER_MAX)) + { + pSent = aSent_Base[eInstance]; + + SENT_HWA_SetGlobalPreScaler(pSent, pCfg->u8PreScaler); + SENT_HWA_SetDMAWaterMark(pSent, pCfg->u8DmaWaterMark); + if(true == pCfg->bDebugModeEn) + { + SENT_HWA_EnableDebugMode(pSent); + } + else + { + SENT_HWA_DisableDebugMode(pSent); + } + if(true == pCfg->bAutoClearReadyFlag) + { + SENT_HWA_EnableDataOverflowFlagFastClear(pSent); + } + else + { + SENT_HWA_DisableDataOverflowFlagFastClear(pSent); + } + aGBISRCallback[eInstance] = pCfg->pGBCallback; + aCHISRCallback[eInstance] = pCfg->pCHCallback; + SENT_HWA_EnableGlobal(pSent); + aSentInit[eInstance] = true; + } + else + { + eRet = SENT_RETURN_E_PARAM; + } + } + else + { + eRet = SENT_RETURN_E_ALREADY_INIT; + } + + return eRet; +} + +Sent_ReturnType SENT_SetChannelConfig(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel, const Sent_ChannelConfigType *pCfg) +{ + Sent_ReturnType eRet = SENT_RETURN_OK; + SENT_Type *pSent; + + if(true == aSentInit[eInstance]) + { + if((NULL != pCfg) && (eInstance < SENT_INSTANCE_MAX) && (eChannel < SENT_CHANNEL_MAX)) + { + pSent = aSent_Base[eInstance]; + if(true == pCfg->bChannelEn) + { + if((pCfg->u8DataNibbleNumber > 0U) && (pCfg->u8DataNibbleNumber < 6U)) + { + SENT_HWA_DisableChannelReceive(pSent, (uint8_t)eChannel); + + SENT_HWA_SetChannelIdleCount(pSent, (uint8_t)eChannel, (uint8_t)pCfg->eIdleCount); + SENT_HWA_SetChannelDigitalFilterCount(pSent, (uint8_t)eChannel, pCfg->u8DigitalFilterCount); + SENT_HWA_SetChannelNibbleNumber(pSent, (uint8_t)eChannel, pCfg->u8DataNibbleNumber); + SENT_HWA_SetChannelPreScaler(pSent, (uint8_t)eChannel, (uint16_t)pCfg->u16TickScaler); + SENT_HWA_SetChannelNibbleDataMode(pSent, (uint8_t)eChannel, (SENT_NibbleDataModeType)(pCfg->eDataNibbleMode)); + + if(SENT_CALIBRATION_PULSE_DIAG_OPTION1 != pCfg->eCalDiagOption) + { + SENT_HWA_DisableChannelSPCOption1(pSent, (uint8_t)eChannel); + } + else + { + SENT_HWA_EnableChannelSPCOption1(pSent, (uint8_t)eChannel); + } + if(true == pCfg->bPausePulseEn) + { + SENT_HWA_EnableChannelPausePulse(pSent, (uint8_t)eChannel); + } + else + { + SENT_HWA_DisableChannelPausePulse(pSent, (uint8_t)eChannel); + } + if(true == pCfg->bTickCompensateEn) + { + SENT_HWA_EnableChannelCompensate(pSent, (uint8_t)eChannel); + } + else + { + SENT_HWA_DisableChannelCompensate(pSent, (uint8_t)eChannel); + } + + if(true == pCfg->bFastMessageFifoEn) + { + SENT_HWA_EnableChannelFIFO(pSent, (uint8_t)eChannel); + } + else + { + SENT_HWA_DisableChannelFIFO(pSent, (uint8_t)eChannel); + } + + if(true == pCfg->bFastMsgCRCAugEn) + { + SENT_HWA_EnableChannelFastMessageAugmentation(pSent, (uint8_t)eChannel); + } + else + { + SENT_HWA_DisableChannelFastMessageAugmentation(pSent, (uint8_t)eChannel); + } + + if(true == pCfg->bFastMsgCRCCheckEn) + { + SENT_HWA_EnableChannelFastMessageCRCCheck(pSent, (uint8_t)eChannel); + } + else + { + SENT_HWA_DisableChannelFastMessageCRCCheck(pSent, (uint8_t)eChannel); + } + + if(true == pCfg->bFastMsgCRCWithSCEn) + { + SENT_HWA_EnableChannelFastMessageCRCWithSC(pSent, (uint8_t)eChannel); + } + else + { + SENT_HWA_DisableChannelFastMessageCRCWithSC(pSent, (uint8_t)eChannel); + } + + if(true == pCfg->bFastMsgDataChangeEn) + { + SENT_HWA_EnableChannelFastMessageDataChange(pSent, (uint8_t)eChannel); + } + else + { + SENT_HWA_DisableChannelFastMessageDataChange(pSent, (uint8_t)eChannel); + } + + + if(true == pCfg->bSlowMsgCRCAugEn) + { + SENT_HWA_EnableChannelSlowMessageAugmentation(pSent, (uint8_t)eChannel); + } + else + { + SENT_HWA_DisableChannelSlowMessageAugmentation(pSent, (uint8_t)eChannel); + } + + if(true == pCfg->bUseAlternativeCrc) + { + SENT_HWA_EnableChannelAltCRC(pSent, (uint8_t)eChannel); + } + else + { + SENT_HWA_DisableChannelAltCRC(pSent, (uint8_t)eChannel); + } + + if(SENT_CALIBRATION_VALID_WITHIN_20 == pCfg->eCalValid) + { + SENT_HWA_DisableChannelCalValid20To25(pSent, (uint8_t)eChannel); + SENT_HWA_EnableChannelCalValidDiagnostic(pSent, (uint8_t)eChannel); + } + else if(SENT_CALIBRATION_VALID_FROM_20_TO_25 == pCfg->eCalValid) + { + SENT_HWA_EnableChannelCalValid20To25(pSent, (uint8_t)eChannel); + SENT_HWA_EnableChannelCalValidDiagnostic(pSent, (uint8_t)eChannel); + } + else + { + SENT_HWA_DisableChannelCalValid20To25(pSent, (uint8_t)eChannel); + SENT_HWA_DisableChannelCalValidDiagnostic(pSent, (uint8_t)eChannel); + } + SENT_HWA_EnableChannelReceive(pSent, (uint8_t)eChannel); + } + else + { + eRet = SENT_RETURN_E_PARAM; + } + } + else + { + SENT_HWA_DisableChannelReceive(pSent, (uint8_t)eChannel); + } + } + } + else + { + eRet = SENT_RETURN_E_UNINIT; + } + + return eRet; +} + +Sent_ReturnType SENT_SetDMAConfig(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel, Sent_DMAConfigType *pCfg) +{ + Sent_ReturnType eRet = SENT_RETURN_OK; + SENT_Type *pSent; + + if(true == aSentInit[eInstance]) + { + if((NULL != pCfg) && (eInstance < SENT_INSTANCE_MAX) && (eChannel < SENT_CHANNEL_MAX)) + { + pSent = aSent_Base[eInstance]; + + if(true == pCfg->bFastMsgDmaEn) + { + SENT_HWA_EnableChannelFastMessageDmaRequest(pSent, (uint8_t)eChannel); + } + else + { + SENT_HWA_DisableChannelFastMessageDmaRequest(pSent, (uint8_t)eChannel); + } + + if(true == pCfg->bSlowMsgDmaEn) + { + SENT_HWA_EnableChannelSlowMessageDmaRequest(pSent, (uint8_t)eChannel); + } + else + { + SENT_HWA_DisableChannelSlowMessageDmaRequest(pSent, (uint8_t)eChannel); + } + } + else + { + eRet = SENT_RETURN_E_PARAM; + } + } + else + { + eRet = SENT_RETURN_E_UNINIT; + } + + return eRet; +} + +Sent_ReturnType SENT_SetSPCConfig(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel, const Sent_SpcConfigType *pCfg) +{ + Sent_ReturnType eRet = SENT_RETURN_OK; + SENT_Type *pSent; + + if(true == aSentInit[eInstance]) + { + if((NULL != pCfg) && (eInstance < SENT_INSTANCE_MAX) && (eChannel < SENT_CHANNEL_MAX)) + { + pSent = aSent_Base[eInstance]; + + SENT_HWA_DisableChannelSPCMode(pSent, (uint8_t)eChannel); + SENT_HWA_SetChannelSPCTickBase(pSent, (uint8_t)eChannel, (SENT_SPCTickType)(pCfg->eSpcTickBase)); + SENT_HWA_SetChannelSPCTriggerMethod(pSent, (uint8_t)eChannel, (SENT_SPCTriggerType)(pCfg->eSpcTrigger)); + SENT_HWA_SetChannelSPCPulseDelay(pSent, (uint8_t)eChannel, pCfg->u8PulseDelay); + SENT_HWA_SetChannelSPCPulseWidth(pSent, (uint8_t)eChannel, pCfg->u8PulseWidth); + if(true == pCfg->bCalDiagEn) + { + SENT_HWA_EnableChannelCalibrationDiag(pSent, (uint8_t)eChannel); + } + else + { + SENT_HWA_DisableChannelCalibrationDiag(pSent, (uint8_t)eChannel); + } + if(true == pCfg->bSpcModeEn) + { + SENT_HWA_EnableChannelSPCMode(pSent, (uint8_t)eChannel); + } + else + { + SENT_HWA_DisableChannelSPCMode(pSent, (uint8_t)eChannel); + } + } + else + { + eRet = SENT_RETURN_E_PARAM; + } + } + else + { + eRet = SENT_RETURN_E_UNINIT; + } + + return eRet; +} + +Sent_ReturnType SENT_GetFastMessageData(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel, Sent_FastMessageDataType *pMsg) +{ + Sent_ReturnType eRet = SENT_RETURN_OK; + SENT_Type *pSent; + uint8_t u8DataShift; + + if(true == aSentInit[eInstance]) + { + if((NULL != pMsg) && (eInstance < SENT_INSTANCE_MAX) && (eChannel < SENT_CHANNEL_MAX)) + { + pSent = aSent_Base[eInstance]; + + pMsg->u8CRC = SENT_HWA_GetChannelFastMessageCRCNibble(pSent, (uint8_t)eChannel); + pMsg->u8SC = SENT_HWA_GetChannelFastMessageStatusNibble(pSent, (uint8_t)eChannel); + pMsg->u32Timestamp = SENT_HWA_GetChannelFastMessageTimeStamp(pSent, (uint8_t)eChannel); + u8DataShift = (5U - SENT_HWA_GetChannelNibbleNumber(pSent, (uint8_t)eChannel)) << 2U; + pMsg->u32Data = SENT_HWA_GetChannelDataNibble(pSent, (uint8_t)eChannel) >> (SENT_CHN_FDATA_DATA6_SHIFT + u8DataShift); + } + else + { + eRet = SENT_RETURN_E_PARAM; + } + } + else + { + eRet = SENT_RETURN_E_UNINIT; + } + + return eRet; +} + +Sent_ReturnType SENT_GetSlowMessageData(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel, Sent_SlowMessageDataType *pMsg) +{ + Sent_ReturnType eRet = SENT_RETURN_OK; + SENT_Type *pSent; + + if(true == aSentInit[eInstance]) + { + if((NULL != pMsg) && (eInstance < SENT_INSTANCE_MAX) && (eChannel < SENT_CHANNEL_MAX)) + { + pSent = aSent_Base[eInstance]; + + pMsg->eMsgType = (Sent_SerialMessageType)SENT_HWA_GetChannelSLowMessageType(pSent, (uint8_t)eChannel); + pMsg->u32Timestamp = SENT_HWA_GetChannelSlowMessageTimeStamp(pSent, (uint8_t)eChannel); + if(SENT_SERIAL_MESSAGE_SHORT == pMsg->eMsgType) + { + pMsg->u8CRC = SENT_HWA_GetChannelBit2CRC(pSent, (uint8_t)eChannel) & 0xFU; + pMsg->u16Data = (uint16_t)SENT_HWA_GetChannelBit2DATA(pSent, (uint8_t)eChannel) & 0xFFU; + pMsg->u8ID = SENT_HWA_GetChannelBit2DATA(pSent, (uint8_t)eChannel) >> 8U; + } + else if(SENT_SERIAL_MESSAGE_ENHANCE_12DATA_8ID == pMsg->eMsgType) + { + pMsg->u8CRC = SENT_HWA_GetChannelBit2CRC(pSent, (uint8_t)eChannel); + pMsg->u16Data = SENT_HWA_GetChannelBit2DATA(pSent, (uint8_t)eChannel); + pMsg->u8ID = (SENT_HWA_GetChannelBit3EnhancedID7_4_OR_ID3_0(pSent, (uint8_t)eChannel) << 4U) | SENT_HWA_GetChannelBit3EnhancedID3_0_OR_DATA15_12(pSent, (uint8_t)eChannel); + } + else if(SENT_SERIAL_MESSAGE_ENHANCE_16DATA_4ID == pMsg->eMsgType) + { + pMsg->u8CRC = SENT_HWA_GetChannelBit2CRC(pSent, (uint8_t)eChannel); + pMsg->u16Data = ((uint16_t)SENT_HWA_GetChannelBit3EnhancedID3_0_OR_DATA15_12(pSent, (uint8_t)eChannel) << 12U) | (uint16_t)SENT_HWA_GetChannelBit2DATA(pSent, (uint8_t)eChannel); + pMsg->u8ID = SENT_HWA_GetChannelBit3EnhancedID7_4_OR_ID3_0(pSent, (uint8_t)eChannel); + } + else + { + eRet = SENT_RETURN_E_NOT_OK; + } + } + else + { + eRet = SENT_RETURN_E_PARAM; + } + } + else + { + eRet = SENT_RETURN_E_UNINIT; + } + + return eRet; +} + +Sent_ReturnType SENT_DecodeFastMessageWithDMABuffer(uint32_t *pDmaBuffer, uint32_t u32BufferLength, Sent_FastMessageDataType *pMsg) +{ + Sent_ReturnType eRet = SENT_RETURN_OK; + + if((NULL != pMsg) && (NULL != pDmaBuffer) && (12U == u32BufferLength)) + { + pMsg->u8CRC = (uint8_t)((pDmaBuffer[1] & SENT_CHN_FCRC_CRC_DATA_MASK) >> SENT_CHN_FCRC_CRC_DATA_SHIFT); + pMsg->u8SC = (uint8_t)((pDmaBuffer[1] & SENT_CHN_FCRC_SC_NB_MASK) >> SENT_CHN_FCRC_SC_NB_SHIFT); + pMsg->u32Timestamp = ((pDmaBuffer[2] & SENT_CHN_FTS_TIMESTAMP_VAL_MASK) >> SENT_CHN_FTS_TIMESTAMP_VAL_SHIFT); + pMsg->u32Data = (pDmaBuffer[0] >> SENT_CHN_FDATA_DATA6_SHIFT); + } + else + { + eRet = SENT_RETURN_E_PARAM; + } + + return eRet; +} + +Sent_ReturnType SENT_DecodeSlowMessageWithDMABuffer(uint32_t *pDmaBuffer, uint32_t u32BufferLength, Sent_SlowMessageDataType *pMsg) +{ + Sent_ReturnType eRet = SENT_RETURN_OK; + + if((NULL != pMsg) && (NULL != pDmaBuffer) && (12U == u32BufferLength)) + { + if(SENT_CHN_SBIT3__MSG_TYPE_MASK == (pDmaBuffer[0] & SENT_CHN_SBIT3__MSG_TYPE_MASK)) + { + if(SENT_CHN_SBIT3__CFG_MASK == (pDmaBuffer[0] & SENT_CHN_SBIT3__CFG_MASK)) + { + pMsg->eMsgType = (Sent_SerialMessageType)SENT_SLOW_MESSAGE_ENHANCE_16DATA_4ID; + } + else + { + pMsg->eMsgType = (Sent_SerialMessageType)SENT_SLOW_MESSAGE_ENHANCE_12DATA_8ID; + } + } + else + { + pMsg->eMsgType = (Sent_SerialMessageType)SENT_SLOW_MESSAGE_SHORT; + } + pMsg->u32Timestamp = ((pDmaBuffer[2] & SENT_CHN_STS_SMSG_TIMESTAMP_MASK) >> SENT_CHN_STS_SMSG_TIMESTAMP_SHIFT); + if(SENT_SERIAL_MESSAGE_SHORT == pMsg->eMsgType) + { + pMsg->u8CRC =(uint8_t)(((pDmaBuffer[1] & SENT_CHN_SBIT2__SMSG_CRC_MASK) >> SENT_CHN_SBIT2__SMSG_CRC_SHIFT) & 0xFU); + pMsg->u16Data = (uint16_t)(((pDmaBuffer[1] & SENT_CHN_SBIT2__SMSG_DATA_MASK) >> SENT_CHN_SBIT2__SMSG_DATA_SHIFT) & 0xFFU); + pMsg->u8ID = (uint8_t)(((pDmaBuffer[1] & SENT_CHN_SBIT2__SMSG_DATA_MASK) >> SENT_CHN_SBIT2__SMSG_DATA_SHIFT) >> 8U); + } + else if(SENT_SERIAL_MESSAGE_ENHANCE_12DATA_8ID == pMsg->eMsgType) + { + pMsg->u8CRC = (uint8_t)((pDmaBuffer[1] & SENT_CHN_SBIT2__SMSG_CRC_MASK) >> SENT_CHN_SBIT2__SMSG_CRC_SHIFT); + pMsg->u16Data = (uint16_t)((pDmaBuffer[1] & SENT_CHN_SBIT2__SMSG_DATA_MASK) >> SENT_CHN_SBIT2__SMSG_DATA_SHIFT); + pMsg->u8ID = (uint8_t)((((pDmaBuffer[0] & SENT_CHN_SBIT3__ID7_4_OR_ID3_0_MASK) >> SENT_CHN_SBIT3__ID7_4_OR_ID3_0_SHIFT) << 4U) |\ + ((pDmaBuffer[0] & SENT_CHN_SBIT3__ID3_0_OR_DATA15_12_MASK) >> SENT_CHN_SBIT3__ID3_0_OR_DATA15_12_SHIFT)); + } + else if(SENT_SERIAL_MESSAGE_ENHANCE_16DATA_4ID == pMsg->eMsgType) + { + pMsg->u8CRC = (uint8_t)((pDmaBuffer[1] & SENT_CHN_SBIT2__SMSG_CRC_MASK) >> SENT_CHN_SBIT2__SMSG_CRC_SHIFT); + pMsg->u16Data = (uint16_t)((((pDmaBuffer[0] & SENT_CHN_SBIT3__ID3_0_OR_DATA15_12_MASK) >> SENT_CHN_SBIT3__ID3_0_OR_DATA15_12_SHIFT) << 12U) |\ + ((pDmaBuffer[1] & SENT_CHN_SBIT2__SMSG_DATA_MASK) >> SENT_CHN_SBIT2__SMSG_DATA_SHIFT)); + pMsg->u8ID = (uint8_t)((pDmaBuffer[0] & SENT_CHN_SBIT3__ID7_4_OR_ID3_0_MASK) >> SENT_CHN_SBIT3__ID7_4_OR_ID3_0_SHIFT); + } + else + { + eRet = SENT_RETURN_E_NOT_OK; + } + } + else + { + eRet = SENT_RETURN_E_PARAM; + } + + return eRet; +} + +Sent_ReturnType SENT_EnableGlobalFastMsgNotification(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel) +{ + Sent_ReturnType eRet = SENT_RETURN_OK; + SENT_Type *pSent; + + if(true == aSentInit[eInstance]) + { + if((eInstance < SENT_INSTANCE_MAX) && (eChannel < SENT_CHANNEL_MAX)) + { + pSent = aSent_Base[eInstance]; + + SENT_HWA_EnableChannelFastMessageInterrupt(pSent, (uint8_t)eChannel); + } + else + { + eRet = SENT_RETURN_E_PARAM; + } + } + else + { + eRet = SENT_RETURN_E_UNINIT; + } + + return eRet; +} + +Sent_ReturnType SENT_DisableGlobalFastMsgNotification(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel) +{ + Sent_ReturnType eRet = SENT_RETURN_OK; + SENT_Type *pSent; + + if(true == aSentInit[eInstance]) + { + if((eInstance < SENT_INSTANCE_MAX) && (eChannel < SENT_CHANNEL_MAX)) + { + pSent = aSent_Base[eInstance]; + + SENT_HWA_DisableChannelFastMessageInterrupt(pSent, (uint8_t)eChannel); + } + else + { + eRet = SENT_RETURN_E_PARAM; + } + } + else + { + eRet = SENT_RETURN_E_UNINIT; + } + + return eRet; +} + +Sent_ReturnType SENT_EnableGlobalSlowMsgNotification(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel) +{ + Sent_ReturnType eRet = SENT_RETURN_OK; + SENT_Type *pSent; + + if(true == aSentInit[eInstance]) + { + if((eInstance < SENT_INSTANCE_MAX) && (eChannel < SENT_CHANNEL_MAX)) + { + pSent = aSent_Base[eInstance]; + + SENT_HWA_EnableChannelSlowMessageInterrupt(pSent, (uint8_t)eChannel); + } + else + { + eRet = SENT_RETURN_E_PARAM; + } + } + else + { + eRet = SENT_RETURN_E_UNINIT; + } + + return eRet; +} + +Sent_ReturnType SENT_DisableGlobalSlowMsgNotification(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel) +{ + Sent_ReturnType eRet = SENT_RETURN_OK; + SENT_Type *pSent; + + if(true == aSentInit[eInstance]) + { + if((eInstance < SENT_INSTANCE_MAX) && (eChannel < SENT_CHANNEL_MAX)) + { + pSent = aSent_Base[eInstance]; + + SENT_HWA_DisableChannelSlowMessageInterrupt(pSent, (uint8_t)eChannel); + } + else + { + eRet = SENT_RETURN_E_PARAM; + } + } + else + { + eRet = SENT_RETURN_E_UNINIT; + } + + return eRet; +} + +Sent_ReturnType SENT_EnableGlobalFastFifoMsgNotification(const Sent_InstanceType eInstance) +{ + Sent_ReturnType eRet = SENT_RETURN_OK; + SENT_Type *pSent; + + if(true == aSentInit[eInstance]) + { + if(eInstance < SENT_INSTANCE_MAX) + { + pSent = aSent_Base[eInstance]; + + SENT_HWA_EnableFastMessageFIFOOverflowInterrupt(pSent); + } + else + { + eRet = SENT_RETURN_E_PARAM; + } + } + else + { + eRet = SENT_RETURN_E_UNINIT; + } + + return eRet; +} + +Sent_ReturnType SENT_DisableGlobalFastFifoMsgNotification(const Sent_InstanceType eInstance) +{ + Sent_ReturnType eRet = SENT_RETURN_OK; + SENT_Type *pSent; + + if(true == aSentInit[eInstance]) + { + if(eInstance < SENT_INSTANCE_MAX) + { + pSent = aSent_Base[eInstance]; + + SENT_HWA_DisableFastMessageFIFOOverflowInterrupt(pSent); + } + else + { + eRet = SENT_RETURN_E_PARAM; + } + } + else + { + eRet = SENT_RETURN_E_UNINIT; + } + + return eRet; +} + +Sent_ReturnType SENT_ConfigChannelStatusNotification(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel, const Sent_ChannelInterruptType *sInterruptEn) +{ + Sent_ReturnType eRet = SENT_RETURN_OK; + SENT_Type *pSent; + + if(true == aSentInit[eInstance]) + { + if((eInstance < SENT_INSTANCE_MAX) && (eChannel < SENT_CHANNEL_MAX)) + { + pSent = aSent_Base[eInstance]; + + SENT_HWA_EnableChannelBusIdleInterrupt(pSent, (uint8_t)eChannel, sInterruptEn->bBusIdleITEn); + SENT_HWA_EnableChannelSPCOverRunInterrupt(pSent, (uint8_t)eChannel, sInterruptEn->bSpcOverrunITEn); + SENT_HWA_EnableChannelCALDiagInterrupt(pSent, (uint8_t)eChannel, sInterruptEn->bCalDiagErrITEn); + SENT_HWA_EnableChannelCalFailInterrupt(pSent, (uint8_t)eChannel, sInterruptEn->bCalFailITEn); + SENT_HWA_EnableChannelCalResyncInterrupt(pSent, (uint8_t)eChannel, sInterruptEn->bCalResyncErrITEn); + SENT_HWA_EnableChannelEdgeERRInterrupt(pSent, (uint8_t)eChannel, sInterruptEn->bFallingEdgeNumErrITEn); + SENT_HWA_EnableChannelFCRCInterrupt(pSent, (uint8_t)eChannel, sInterruptEn->bFastMsgCrcErrITEn); + SENT_HWA_EnableChannelFOVFLInterrupt(pSent, (uint8_t)eChannel, sInterruptEn->bFastMsgOFITEn); + SENT_HWA_EnableChannelNibbleErrorInterrupt(pSent, (uint8_t)eChannel, sInterruptEn->bNibbleValueErrITEn); + SENT_HWA_EnableChannelPPDiagInterrupt(pSent, (uint8_t)eChannel, sInterruptEn->bPrePulseDiagErrITEn); + SENT_HWA_EnableChannelSCRCInterrupt(pSent, (uint8_t)eChannel, sInterruptEn->bSlowMsgCrcErrITEn); + SENT_HWA_EnableChannelSOVFLInterrupt(pSent, (uint8_t)eChannel, sInterruptEn->bSlowMsgOFITEn); + SENT_HWA_EnableChannelCalERRInterrupt(pSent, (uint8_t)eChannel, sInterruptEn->bCalErrITEn); + //SENT_HWA_EnableChannelAllErrorInterrupt(pSent, eChannel); + } + else + { + eRet = SENT_RETURN_E_PARAM; + } + } + else + { + eRet = SENT_RETURN_E_UNINIT; + } + + return eRet; +} + +Sent_ReturnType SENT_RequestSPCPulse(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel) +{ + Sent_ReturnType eRet = SENT_RETURN_OK; + SENT_Type *pSent; + + if(true == aSentInit[eInstance]) + { + if((eInstance < SENT_INSTANCE_MAX) && (eChannel < SENT_CHANNEL_MAX)) + { + pSent = aSent_Base[eInstance]; + + SENT_HWA_StartChannelSPC(pSent, (uint8_t)eChannel); + } + else + { + eRet = SENT_RETURN_E_PARAM; + } + } + else + { + eRet = SENT_RETURN_E_UNINIT; + } + + return eRet; +} + +Sent_ReturnType SENT_GetFastMsgReadyFlag(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel, bool *pFlag) +{ + Sent_ReturnType eRet = SENT_RETURN_OK; + SENT_Type *pSent; + + if(true == aSentInit[eInstance]) + { + if((eInstance < SENT_INSTANCE_MAX) && (eChannel < SENT_CHANNEL_MAX)) + { + pSent = aSent_Base[eInstance]; + + *pFlag = SENT_HWA_GetFastMessageReadyFlag(pSent, (uint8_t)eChannel); + } + else + { + eRet = SENT_RETURN_E_PARAM; + } + } + else + { + eRet = SENT_RETURN_E_UNINIT; + } + + return eRet; +} + +Sent_ReturnType SENT_GetSlowMsgReadyFlag(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel, bool *pFlag) +{ + Sent_ReturnType eRet = SENT_RETURN_OK; + SENT_Type *pSent; + + if(true == aSentInit[eInstance]) + { + if((eInstance < SENT_INSTANCE_MAX) && (eChannel < SENT_CHANNEL_MAX)) + { + pSent = aSent_Base[eInstance]; + + *pFlag = SENT_HWA_GetSlowMessageReadyFlag(pSent, (uint8_t)eChannel); + } + else + { + eRet = SENT_RETURN_E_PARAM; + } + } + else + { + eRet = SENT_RETURN_E_UNINIT; + } + + return eRet; +} + +Sent_ReturnType SENT_GetChannelStatus(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel, uint32_t *pStatus) +{ + Sent_ReturnType eRet = SENT_RETURN_OK; + SENT_Type *pSent; + + if(true == aSentInit[eInstance]) + { + if((eInstance < SENT_INSTANCE_MAX) && (eChannel < SENT_CHANNEL_MAX)) + { + pSent = aSent_Base[eInstance]; + + *pStatus = SENT_HWA_GetChannelStatus(pSent, (uint8_t)eChannel); + } + else + { + eRet = SENT_RETURN_E_PARAM; + } + } + else + { + eRet = SENT_RETURN_E_UNINIT; + } + + return eRet; +} + +Sent_ReturnType SENT_ClearChannelStatus(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel, uint32_t Status) +{ + Sent_ReturnType eRet = SENT_RETURN_OK; + SENT_Type *pSent; + + if(true == aSentInit[eInstance]) + { + if((eInstance < SENT_INSTANCE_MAX) && (eChannel < SENT_CHANNEL_MAX)) + { + pSent = aSent_Base[eInstance]; + + SENT_HWA_ClearChannelStatus(pSent, (uint8_t)eChannel, Status); + } + else + { + eRet = SENT_RETURN_E_PARAM; + } + } + else + { + eRet = SENT_RETURN_E_UNINIT; + } + + return eRet; +} + +Sent_ReturnType SENT_GetChannelSPCBusyFlag(const Sent_InstanceType eInstance, const Sent_ChannelType eChannel, bool *pflag) +{ + Sent_ReturnType eRet = SENT_RETURN_OK; + SENT_Type *pSent; + + if(true == aSentInit[eInstance]) + { + if((eInstance < SENT_INSTANCE_MAX) && (eChannel < SENT_CHANNEL_MAX)) + { + pSent = aSent_Base[eInstance]; + + *pflag = SENT_HWA_GetChanneSPCBusyFlag(pSent, (uint8_t)eChannel); + } + else + { + eRet = SENT_RETURN_E_PARAM; + } + } + else + { + eRet = SENT_RETURN_E_UNINIT; + } + + return eRet; +} + +void SENT0_IRQHandler(void) +{ + SENT_IRQ_Handler(SENT_INSTANCE_0); +} + +void SENT1_IRQHandler(void) +{ + SENT_IRQ_Handler(SENT_INSTANCE_1); +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_smc.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_smc.c new file mode 100644 index 0000000..cdb4ec0 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_smc.c @@ -0,0 +1,122 @@ +/** + * @file fc7xxx_driver_smc.c + * @author Flagchip0105 + * @brief FC7xxx SMC driver type definition and API + * @version 0.1.0 + * @date 2024-01-08 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/******************************************************************************** +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2024-01-08 Flagchip0105 N/A FC7240 First version +********************************************************************************/ +#include "fc7xxx_driver_smc.h" + +/** + * @brief Set system mode + * + * @param eMode MCU low power mode + * @return Smc return type + */ +SMC_StatusType SMC_SetSystemMode(const SMC_ModeType eMode) +{ + SMC_StatusType eRet = SMC_STATUS_SUCCESS; + + DEV_ASSERT(eMode <= SMC_MODE_STANBY_3); + + switch (eMode) + { + case SMC_MODE_RUN: + /* Clear the SLEEPDEEP bit to disable deep sleep mode */ + CM7_HWA_DisableDeepSleep(); + + break; + case SMC_MODE_STOP: + /* switch smc mode to stop mode */ + SMC_HWA_SetStopModeCtrl(SMC_STOP_MODE); + /* Set the SLEEPDEEP bit to enable deep sleep mode (STOP)*/ + CM7_HWA_EnableDeepSleep(); + + /* Cpu is going into deep sleep state */ + STANDBY(); + + break; + + case SMC_MODE_WAIT: + /* Clear the SLEEPDEEP bit to disable deep sleep mode */ + CM7_HWA_DisableDeepSleep(); + + /* Cpu is going into sleep state */ + STANDBY(); + + break; + + case SMC_MODE_STANBY_0: + /* select standby mode*/ + SMC_HWA_SetStandbyMode(SMC_CFG_STANDBY_0); + + /* switch smc mode to standby mode */ + SMC_HWA_SetStopModeCtrl(SMC_STANDBY_MODE); + /* Set the SLEEPDEEP bit to enable deep sleep mode */ + CM7_HWA_EnableDeepSleep(); + + /* Cpu is going into deep sleep state */ + STANDBY(); + + break; + + case SMC_MODE_STANBY_1: + /* select standby mode*/ + SMC_HWA_SetStandbyMode(SMC_CFG_STANDBY_1); + + /* switch smc mode to standby mode */ + SMC_HWA_SetStopModeCtrl(SMC_STANDBY_MODE); + + /* Set the SLEEPDEEP bit to enable deep sleep mode */ + CM7_HWA_EnableDeepSleep(); + + /* Cpu is going into deep sleep state */ + STANDBY(); + break; + + case SMC_MODE_STANBY_2: + /* select standby mode*/ + SMC_HWA_SetStandbyMode(SMC_CFG_STANDBY_2); + + /* switch smc mode to standby mode */ + SMC_HWA_SetStopModeCtrl(SMC_STANDBY_MODE); + + /* Set the SLEEPDEEP bit to enable deep sleep mode */ + CM7_HWA_EnableDeepSleep(); + + /* Cpu is going into deep sleep state */ + STANDBY(); + break; + + case SMC_MODE_STANBY_3: + /* select standby mode*/ + SMC_HWA_SetStandbyMode(SMC_CFG_STANDBY_3); + + /* switch smc mode to standby mode */ + SMC_HWA_SetStopModeCtrl(SMC_STANDBY_MODE); + + /* Set the SLEEPDEEP bit to enable deep sleep mode */ + CM7_HWA_EnableDeepSleep(); + + /* Cpu is going into deep sleep state */ + STANDBY(); + break; + default: + /* do nothing */ + break; + + } + + return eRet; +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_stcu.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_stcu.c new file mode 100644 index 0000000..30e5385 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_stcu.c @@ -0,0 +1,202 @@ +/** + * @file fc7xxx_driver_stcu.c + * @author Flagchip + * @brief FC4xxx stcu driver type definition and API + * @version 0.1.0 + * @date 2023-02-15 + * + * @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. + * + */ + +/* ******************************************************************************** + * Revision History: + * + * Version Date Author CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 1/10/2024 Flagchip0095 N/A First version for FC7240 + ******************************************************************************** */ +#include "HwA_stcu.h" +#include "fc7xxx_driver_stcu.h" + + + +/* ################################################################################## */ +/* ##################################### Macros ##################################### */ +#define STCU_SAFETY_KEY (0xBB40E64DU) +#define STCU_RECOMMENDED_PATTERN (0xBUL) + + +/* ################################################################################## */ +/* ################################# Local Variables ################################ */ + +/* ################################################################################## */ +/* ########################### Local Functions Prototype ############################ */ + +/* ################################################################################## */ +/* ######################### Global Functions prototype ############################ */ +void STCU0_IRQHandler(void); + +/* ################################################################################## */ +/* ################################# Local Functions ############################### */ +static Stcu_IRQCallback sIRQCallback = NULL; + +/* ################################################################################## */ +/* ################################# Global Functions ############################### */ + +/** + * \brief Init the STCU module + * + * \param pConfig the configuration structure + */ +void STCU_Init(STCU_ConfigType *pConfig) +{ + uint32_t u32Reg; + + STCU_HWA_MbistSelect(pConfig->u32MbistSel); + + STCU_HWA_SetMBISTSWAlg(pConfig->bMbistFullTest, pConfig->bMbistSramInit); + + pConfig->bInterruptEn?STCU_HWA_EnableInterrupt():STCU_HWA_DisableInterrupt(); + + sIRQCallback = pConfig->pIrqCallback; + + u32Reg = STCU_SELF_TEST_CTRL_LBIST_CLKDIV((uint32_t)(pConfig->eLbistClkDivider)) | + STCU_SELF_TEST_CTRL_LBIST_EN(pConfig->bLbistEn?1UL:0UL) | + STCU_SELF_TEST_CTRL_MBIST_LP(pConfig->bMbistLPC?1UL:0UL) | + STCU_SELF_TEST_CTRL_MBIST_EN(pConfig->bMbistEn?1UL:0UL) | + STCU_SELF_TEST_CTRL_CLK_SEL((uint32_t)(pConfig->eClkSource)) | + STCU_SELF_TEST_CTRL_MT(pConfig->u16MaxTime) | + STCU_SELF_TEST_CTRL_PE(STCU_PORT_PULL_DISABLE == pConfig->ePortPullMode?0UL:1UL) | + STCU_SELF_TEST_CTRL_PS(STCU_PORT_PULL_UP == pConfig->ePortPullMode?1UL:0UL) | + STCU_SELF_TEST_CTRL_FCSMU_TRIG(0U) | /* FCSMU reset will trigger self-test */ + STCU_SELF_TEST_CTRL_LBIST_TD(1U) | /* enable LBIST at-speed test */ + STCU_SELF_TEST_CTRL_SCHK_EN(1U) | /* self check enable */ + STCU_SELF_TEST_CTRL_STEST_BYPASS(0U);/* self-test will be not bypassed */ + + STCU_HWA_SetSelfTestCTRL(u32Reg); +} + +/** + * \brief Set the LBIST Pattern value and expected misr value. + * The two value should be load from NVR, but also can reconfigure by this API. + * The expected misr value is calculated from pattern, so please make sure this two value is right, or the LBST would fail. + * + * \param u16Pattern the LBIST Pattern value + * \param u16Pattern the LBIST expected misr value + */ +void STCU_LBIST_Set_Pattern_Misr(uint16_t u16Pattern, uint32_t u32ExpectedMisr) +{ + STCU_HWA_SetLBISTPatternAmount(u16Pattern); + STCU_HWA_SetExpectedMisr(u32ExpectedMisr); +} + +/** + * \brief Trigger to start Software self test + * + */ +void STCU_StartSelfTest(void) +{ + /* clear STCU_SELF_TEST_STATUS. */ + STCU_HWA_ClearSelfTestStatus(); + + STCU_HWA_SetSafetyKey(STCU_SAFETY_KEY); /* enable STCU_SELF_TEST_CTRL A/B access */ + + /* set the TRIG bits in both STCU_SELF_TEST_TRIG_A and STCU_SELF_TEST_TRIG_B. */ + STCU_HWA_SwTriggerA(); + STCU_HWA_SwTriggerB(); +} + +/** + * \brief Check Software Trigger Self-test result. If the LBIST is done, could call "STCU_GetLbistFailResult" to check the test result. + * If the MBIST is done, could call "STCU_GetMbistFailResult" to check the test result. + * + * \return refer to "STCU_SelfTestStatusType" enum. + */ +uint32_t STCU_CheckTriggerResult(void) +{ + return STCU_HWA_GetSelfTestStatus(); +} + +/** + * \brief Get each MBIST Fail result + * + * \return refer to "STCU_MbistFailedType" enum. + */ +uint32_t STCU_GetMbistFailResult(void) +{ + uint32_t u32Done, u32Fail; + + u32Done = STCU_GetMbistDone(); + u32Fail = STCU_GetMbistFail(); + + return (u32Done & u32Fail); +} + +/** + * \brief Get if the LBIST test result is Fail + * + * \return true means LBIST fail. false means LBIST pass. + */ +bool STCU_GetLbistFailResult(void) +{ + uint32_t u32status; + + u32status = STCU_HWA_CheckLbistStatus(); + + u32status = (u32status >> STCU_LBIST_STATUS_FAIL_SHIFT) & (u32status & STCU_LBIST_STATUS_DONE_MASK); + + return (0UL == u32status?false:true); +} + +/** + * \brief Initial DTCM with hardware + */ +void STCU_StartRamInit(STCU_InitRamConfigType *pInitCfg) +{ + STCU_HWA_SetRamInitType( pInitCfg->u32InitRamType); + STCU_HWA_StartRamInit(pInitCfg->eInitMode,pInitCfg->bLockAfterEn); +} + +/** + * \brief Get status of RAM initialize action, for more detail, could call "STCU_GetRamInitDoneStatus" + * to get more info for each SRAM + * \return the status of ram initialize action, refer to "STCU_HardwareInitRamStatusType" + */ +uint32_t STCU_GetRamInitStatus(void) +{ + return STCU_HWA_GetRamInitStatus(); +} + +/** + * \brief Get each done status of SRAM initialize + * + * \return the done status of SRAM initialize action, refer to "STCU_InitRamDoneType" + */ +uint32_t STCU_GetRamInitDoneStatus(void) +{ + return STCU_HWA_GetRamInitDone(); +} + +/** + * \brief Get LBIST actual MISR value, the value should be read and use DFT tool to decode it, if LBIST test resault is fail. + * + * \return the LBIST actual MISR value + */ +uint32_t STCU_GetLbistAcutalMisr(void) +{ + return STCU_HWA_GetActualMisr(); +} + + +void STCU0_IRQHandler(void) +{ + uint32_t u32Flag; + + u32Flag = STCU_HWA_GetInterruptFlag(); + STCU_HWA_ClearInterruptFlag(); + if(NULL != sIRQCallback) + { + sIRQCallback(u32Flag); + } +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_systick.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_systick.c new file mode 100644 index 0000000..3136b49 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_systick.c @@ -0,0 +1,60 @@ +#include "fc7xxx_driver_systick.h" + + + +/** + * \brief Config system tick + * + * \param u32ReloadVal reload value, val is decrease from reload value + * \return 0 is ok, and others are not ok + */ +uint8_t Core_SysTick_Config(uint32_t u32ReloadVal) +{ + uint8_t u8Retval; + + if (u32ReloadVal > SysTick_LOAD_RELOAD_Msk) + { + u8Retval = 1U; + } + else + { + SysTick->LOAD = u32ReloadVal; /* set reload register */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk; /* Processor clock */ + u8Retval = 0U; + } + + return u8Retval; +} + +void Core_SysTick_DeConfig(void) +{ + SysTick->CTRL = 0U; + SysTick->LOAD = 0U; + SysTick->VAL = 0U; +} + +void Core_SysTick_ClearValue(void) +{ + SysTick->VAL = 0U; +} + +void Core_SysTick_SetValue(uint32_t u32Value) +{ + SysTick->VAL = u32Value; +} + +uint32_t Core_SysTick_GetValue(void) +{ + return SysTick->VAL; +} + +void Core_SysTick_Enable(void) +{ + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ +} + +void Core_SysTick_Disable(void) +{ + SysTick->CTRL &= ~(SysTick_CTRL_ENABLE_Msk); +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_tmu.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_tmu.c new file mode 100644 index 0000000..c1cc487 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_tmu.c @@ -0,0 +1,312 @@ +/** + * @file fc7xxx_driver_tmu.c + * @author Flagchip + * @brief FC7xxx TMU driver source code + * @version 0.1.0 + * @date 2023-12-29 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/********************************************************************************* +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2023-12-29 qxw074 N/A First version for FC7240 +******************************************************************************** */ + +#include "fc7xxx_driver_tmu.h" +#include "fc7xxx_driver_pcc.h" +#include "interrupt_manager.h" + +/********* Local Variables ************/ +/** @brief TMU peripheral base pointers */ +static TMU_Type *const s_apTmuBase = TMU_BASE_PTRS; +/** @brief Temperature over 150 Celsius notify callback function point */ +static TMU_TempOver150InterruptCallbackType s_apTmuOver150Notify = NULL; +/** @brief Temperature over 125 Celsius notify callback function point */ +static TMU_TempOver125InterruptCallbackType s_apTmuOver125Notify = NULL; +/** @brief The Flag-based temperature sensor ready notify callback function point */ +static TMU_TempFlagReadyInterruptCallbackType s_apTmuFlagReadyNotify = NULL; +/** @brief The Voltage-based temperature sensor ready notify callback function point */ +static TMU_TempVoltageReadyInterruptCallbackType s_apTmuVoltgeReadyNotify = NULL; + +/***************TMU IRQ Functions*****************/ +/** @brief TMU interrupt entry */ +void TMU_IRQHandler(void); +/** + * @brief TMU irq handler + * + */ +void TMU_IRQHandler(void) +{ + TMU_Type *const pTmu = s_apTmuBase; + if (TMU_HWA_GetFlagTemperature150InterruptFlag(pTmu) == true) + { + if (TMU_HWA_Get150Flag(pTmu) == true) + { + if (s_apTmuOver150Notify != NULL) + { + s_apTmuOver150Notify(); + } + TMU_HWA_Clear150Flag(pTmu); + } + } + if (TMU_HWA_GetFlagTemperature125InterruptFlag(pTmu) == true) + { + if (TMU_HWA_Get125Flag(pTmu) == true) + { + if (s_apTmuOver125Notify != NULL) + { + s_apTmuOver125Notify(); + } + TMU_HWA_Clear125Flag(pTmu); + } + } + if (TMU_HWA_GetFlagTemperatureReadyInterruptFlag(pTmu) == true) + { + if (TMU_HWA_GetFlagTemperatureReady(pTmu) == true) + { + if (s_apTmuFlagReadyNotify != NULL) + { + s_apTmuFlagReadyNotify(); + } + TMU_HWA_SetTemperatureLockStatus(pTmu, TMU_TF_TV_UNLOCK); + TMU_HWA_SetFlagTemperatureReadyInterruptFlag(pTmu, false); + TMU_HWA_SetTemperatureLockStatus(pTmu, TMU_TF_TV_LOCK); + } + } + if (TMU_HWA_GetVoltageTemperatureReadyInterruptFlag(pTmu) == true) + { + if (TMU_HWA_GetVoltageTemperatureReady(pTmu) == true) + { + if (s_apTmuVoltgeReadyNotify != NULL) + { + s_apTmuVoltgeReadyNotify(); + } + TMU_HWA_SetTemperatureLockStatus(pTmu, TMU_TF_TV_UNLOCK); + TMU_HWA_SetVoltageTemperatureReadyInterruptFlag(pTmu, false); + TMU_HWA_SetTemperatureLockStatus(pTmu, TMU_TF_TV_LOCK); + } + } +} + +/** + * @brief Initialize the TMU instance + * + * @param pInitCfg the configurations of the TMU instance + */ +void TMU_Init(const TMU_InitType *const pInitCfg) +{ + DEV_ASSERT(pInitCfg != NULL); + + TMU_Type *const pTmu = s_apTmuBase; + uint32_t u32FlagCtrl; + uint32_t u32VoltageCtrl; + uint8_t u8FlagStartupCnt; + uint8_t u8VoltageStartupCnt; + + PCC_ClkSrcType eAdcClkName = PCC_CLK_TMU0; + uint32_t u32TmuClk; + u32TmuClk = PCC_GetPccFunctionClock(eAdcClkName); + + u8FlagStartupCnt = (uint8_t)((u32TmuClk * 11U) / 127000000U + 1U); + u8VoltageStartupCnt = (uint8_t)((u32TmuClk * 5U) / 127000000U + 1U); + if (u8FlagStartupCnt > 15U) + { + u8FlagStartupCnt = 15U; + } + if (u8VoltageStartupCnt > 7U) + { + u8VoltageStartupCnt = 7U; + } + + u32FlagCtrl = TMU_TF_CTRL_TF_150F_IE(pInitCfg->bTemperatureOver150IntEn) | + TMU_TF_CTRL_TF_125F_IE(pInitCfg->bTemperatureOver125IntEn) | + TMU_TF_CTRL_TF_RDYF_IE(pInitCfg->bFlagTempReadyIntEn) | + TMU_TF_CTRL_TF_HYSOFF(pInitCfg->eFlagTempHysteresisCon) | + TMU_TF_CTRL_TF_START_CNT(u8FlagStartupCnt) | + TMU_TF_CTRL_TF_FILT_BYP(pInitCfg->eFlagTempFilterBypassCon); + TMU_HWA_SetFlagTempCtrl(pTmu, u32FlagCtrl); + + u32VoltageCtrl = TMU_TV_CTRL_TV_RDYF_IE(pInitCfg->bVoltageTempReadyIntEn) | + TMU_TV_CTRL_TV_START_CNT(u8VoltageStartupCnt); + TMU_HWA_SetVoltageTempCtrl(pTmu, u32VoltageCtrl); + + TMU_HWA_SetStopAck(pInitCfg->bSmicsStopAckEn); + + /* interrupt callback function */ + s_apTmuOver150Notify = pInitCfg->pTemp150Notify; + s_apTmuOver125Notify = pInitCfg->pTemp125Notify; + s_apTmuFlagReadyNotify = pInitCfg->pFlagReadyNotify; + s_apTmuVoltgeReadyNotify = pInitCfg->pVoltagReadyNotify; + + TMU_HWA_SetTemperatureLockStatus(pTmu, TMU_TF_TV_LOCK); +} + +/** + * @brief Enable the Flag-based temperature sensor + * + * @return TMU_StatusType TMU_STATUS_SUCCESS when enable successfully, others fail + */ +TMU_StatusType TMU_FlagTempEnable(void) +{ + TMU_StatusType eRet; + uint32_t u32TimeOut = 15000000U; + TMU_Type *const pTmu = s_apTmuBase; + + TMU_HWA_SetTemperatureLockStatus(pTmu, TMU_TF_TV_UNLOCK); + TMU_HWA_SetFlagTemperatureEnableStatus(pTmu, true); + while ((TMU_HWA_GetFlagTemperatureReady(pTmu) != true) && (u32TimeOut != 0U)) + { + u32TimeOut--; + } + if (u32TimeOut != 0U) + { + eRet = TMU_STATUS_SUCCESS; + TMU_HWA_ClearFlagTemperatureReady(pTmu); + } + else + { + eRet = TMU_STATUS_TIMEOUT; + } + TMU_HWA_SetTemperatureLockStatus(pTmu, TMU_TF_TV_LOCK); + return eRet; +} + +/** + * @brief Disable the Flag-based temperature sensor + * + * @return TMU_StatusType TMU_STATUS_SUCCESS when disable successfully, others fail + */ +TMU_StatusType TMU_FlagTempDisable(void) +{ + TMU_StatusType eRet; + uint32_t u32TimeOut = 15000000U; + TMU_Type *const pTmu = s_apTmuBase; + + TMU_HWA_SetTemperatureLockStatus(pTmu, TMU_TF_TV_UNLOCK); + TMU_HWA_SetFlagTemperatureEnableStatus(pTmu, false); + TMU_HWA_ClearFlagTemperatureReady(pTmu); + while ((TMU_HWA_GetFlagTemperatureEnableStatus(pTmu) == true) && (u32TimeOut != 0U)) + { + u32TimeOut--; + } + if (u32TimeOut != 0U) + { + eRet = TMU_STATUS_SUCCESS; + } + else + { + eRet = TMU_STATUS_TIMEOUT; + } + TMU_HWA_SetTemperatureLockStatus(pTmu, TMU_TF_TV_LOCK); + return eRet; +} + +/** + * @brief Enable the Voltage-based temperature sensor + * + * @return TMU_StatusType TMU_STATUS_SUCCESS when enable successfully, others fail + */ +TMU_StatusType TMU_VoltageTempEnable(void) +{ + TMU_StatusType eRet; + uint32_t u32TimeOut = 15000000U; + TMU_Type *const pTmu = s_apTmuBase; + + TMU_HWA_SetTemperatureLockStatus(pTmu, TMU_TF_TV_UNLOCK); + TMU_HWA_SetVoltageTemperatureEnableStatus(pTmu, true); + while ((TMU_HWA_GetVoltageTemperatureReady(pTmu) != true) && (u32TimeOut != 0U)) + { + u32TimeOut--; + } + if (u32TimeOut != 0U) + { + eRet = TMU_STATUS_SUCCESS; + TMU_HWA_ClearVoltageTemperatureReady(pTmu); + } + else + { + eRet = TMU_STATUS_TIMEOUT; + } + TMU_HWA_SetTemperatureLockStatus(pTmu, TMU_TF_TV_LOCK); + return eRet; +} + +/** + * @brief Disable the Voltage-based temperature sensor + * + * @return TMU_StatusType TMU_STATUS_SUCCESS when disable successfully, others fail + */ +TMU_StatusType TMU_VoltageTempDisable(void) +{ + TMU_StatusType eRet; + uint32_t u32TimeOut = 15000000U; + TMU_Type *const pTmu = s_apTmuBase; + + TMU_HWA_SetTemperatureLockStatus(pTmu, TMU_TF_TV_UNLOCK); + TMU_HWA_SetVoltageTemperatureEnableStatus(pTmu, false); + TMU_HWA_ClearVoltageTemperatureReady(pTmu); + while ((TMU_HWA_GetVoltageTemperatureEnableStatus(pTmu) == true) && (u32TimeOut != 0U)) + { + u32TimeOut--; + } + if (u32TimeOut != 0U) + { + eRet = TMU_STATUS_SUCCESS; + } + else + { + eRet = TMU_STATUS_TIMEOUT; + } + TMU_HWA_SetTemperatureLockStatus(pTmu, TMU_TF_TV_LOCK); + return eRet; +} + +/** + * @brief Check if cleaning flag is required + * + */ +void TMU_TempOverClear(void) +{ + TMU_Type *const pTmu = s_apTmuBase; + if (TMU_HWA_Get150Flag(pTmu)) + { + if (!TMU_HWA_Get150Status(pTmu)) + { + TMU_HWA_Clear150Flag(pTmu); + } + } + if (TMU_HWA_Get125Flag(pTmu)) + { + if (!TMU_HWA_Get125Status(pTmu)) + { + TMU_HWA_Clear125Flag(pTmu); + } + } +} + +/** + * @brief Get the temperature code from ADC + * + * @return uint32_t the value records the ADC conversion results for voltage-based temperature sensor result in 135 Celsius + */ +uint32_t TMU_GetTcode(void) +{ + TMU_Type *const pTmu = s_apTmuBase; + return TMU_HWA_GetTemperatureCode(pTmu); +} + +/** + * @brief Get the slope factor + * + * @return uint32_t the value records the slope factor for voltage-based temperature sensor + */ +uint32_t TMU_GetTslope(void) +{ + TMU_Type *const pTmu = s_apTmuBase; + return TMU_HWA_GetSlopeFactor(pTmu); +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_tpu.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_tpu.c new file mode 100644 index 0000000..c8d72c1 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_tpu.c @@ -0,0 +1,596 @@ + +/** + * @file module_driver_tpu.c + * @author Flagchip099 + * @brief FC7xxx TPU driver source code + * @version 0.1.0 + * @date 2024-1-12 + * + * @copyright Copyright (c) 2024 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2024-1-12 Flagchip099 N/A First version for FC7240 + ******************************************************************************** */ + +#include "fc7xxx_driver_tpu.h" + +static uint32_t u32PwmLastFrame[TPU_E_CH_COUNT]; +static uint32_t u32PwmNextEdge[TPU_E_CH_COUNT]; +static bool bMeasActivePeriodComplete[TPU_E_CH_COUNT] = {(bool)false}; +static TPU_HSACallbackType s_TpuHSANotify[TPU_E_CH_COUNT] = {NULL}; +static TPU_EventCallbackType s_TpuEventNotify[TPU_E_CH_COUNT] = {NULL}; +static TPU_TCR1OverflowCallbackType s_TpuTCR1OverflowNotify = NULL; +static TPU_TCR2OverflowCallbackType s_TpuTCR2OverflowNotify = NULL; + + +void TPU0_CH0_7_IRQHandler(void); +void TPU0_CH8_15_IRQHandler(void); +void TPU0_CH16_23_IRQHandler(void); +void TPU0_CH24_31_IRQHandler(void); + +/** + * @brief TPU_Overflow_IRQHandler + * + */ +static inline void TPU_Overflow_IRQHandler(void) +{ + TPU_E_Type *const pTpuE = TPU_E_BASE_PTRS; + if (TPU_E_HWA_GetTCR1Overflow(pTpuE)) + { + TPU_E_HWA_ClearTCR1Overflow(pTpuE); + if (s_TpuTCR1OverflowNotify != NULL) + { + s_TpuTCR1OverflowNotify(); + } + } + if (TPU_E_HWA_GetTCR2Overflow(pTpuE)) + { + TPU_E_HWA_ClearTCR2Overflow(pTpuE); + if (s_TpuTCR2OverflowNotify != NULL) + { + s_TpuTCR2OverflowNotify(); + } + } +} + +/** + * @brief TPU_Event_IRQHandler + * + */ +static inline void TPU_Event_IRQHandler(uint8_t u8MinChannel, uint8_t u8MaxChannel) +{ + TPU_H_Type *const pTpuH = TPU_H_BASE_PTRS; + uint8_t u8Channel; + + for (u8Channel = (uint8_t)u8MinChannel; u8Channel < ((uint8_t)u8MaxChannel + 1u); u8Channel++) + { + if (TPU_H_HWA_GetChEventTrigISRStatus(pTpuH, u8Channel) == true) + { + if (s_TpuEventNotify[u8Channel] != NULL) + { + s_TpuEventNotify[u8Channel](); + } + } + if (TPU_H_HWA_GetChHSAReqStatus(pTpuH, u8Channel) == true) + { + TPU_H_HWA_ClearChHSA(pTpuH, u8Channel); + s_TpuHSANotify[u8Channel](); + } + } +} + +/** + * @brief TPU_InitOverflowInterrupt + * + */ +static void TPU_InitOverflowInterrupt(const TPU_InterruptCfgType *const pInterruptCfg) +{ + DEV_ASSERT(pInterruptCfg != NULL); + + TPU_E_Type *const pTPUE = TPU_E_BASE_PTRS; + + if (pInterruptCfg->bTCR1OverFlowEventIntEn) + { + s_TpuTCR1OverflowNotify = pInterruptCfg->pTCR1OverflowNotify; + TPU_E_HWA_EnableTCR1OVFIRQ(pTPUE, (bool)true); + } + else + { + TPU_E_HWA_EnableTCR1OVFIRQ(pTPUE, (bool)false); + s_TpuTCR1OverflowNotify = NULL; + } + + if (pInterruptCfg->bTCR2OverFlowEventIntEn) + { + s_TpuTCR2OverflowNotify = pInterruptCfg->pTCR2OverflowNotify; + TPU_E_HWA_EnableTCR2OVFIRQ(pTPUE, (bool)true); + } + else + { + TPU_E_HWA_EnableTCR2OVFIRQ(pTPUE, (bool)false); + s_TpuTCR2OverflowNotify = NULL; + } +} + +/** + * @brief TPU0_CH0_7_IRQHandler + * + */ +void TPU0_CH0_7_IRQHandler(void) +{ + TPU_Event_IRQHandler(TPU_CHANNEL_0, TPU_CHANNEL_7); +} + +/** + * @brief TPU0_CH8_15_IRQHandler + * + */ +void TPU0_CH8_15_IRQHandler(void) +{ + TPU_Event_IRQHandler(TPU_CHANNEL_8, TPU_CHANNEL_15); +} + +/** + * @brief TPU0_CH16_23_IRQHandler + * + */ +void TPU0_CH16_23_IRQHandler(void) +{ + TPU_Event_IRQHandler(TPU_CHANNEL_16, TPU_CHANNEL_23); +} + +/** + * @brief TPU0_CH24_31_IRQHandler + * + */ +void TPU0_CH24_31_IRQHandler(void) +{ + TPU_Overflow_IRQHandler(); + TPU_Event_IRQHandler(TPU_CHANNEL_24, TPU_CHANNEL_31); +} + +/** + * @brief TPU_InitChannelInterrupt + * + */ +void TPU_InitChannelInterrupt(uint8_t u8Channel, const TPU_InterruptCfgType *const pInterruptCfg) +{ + DEV_ASSERT(u8Channel < TPU_E_CH_COUNT); + DEV_ASSERT(pInterruptCfg != NULL); + + TPU_E_Type *const pTPUE = TPU_E_BASE_PTRS; + TPU_H_Type *const pTPUH = TPU_H_BASE_PTRS; + + if (pInterruptCfg->bEventIntEn) + { + s_TpuEventNotify[u8Channel] = pInterruptCfg->pEventNotify; + TPU_E_HWA_EnableChEventInt(pTPUE, u8Channel, (bool)true); + TPU_E_HWA_EnableSrvReq(pTPUE, u8Channel, (bool)true); + TPU_H_HWA_SetChTrig(pTPUH, u8Channel, pInterruptCfg->eChTrigType); + } + else + { + s_TpuEventNotify[u8Channel] = NULL; + } + TPU_InitOverflowInterrupt(pInterruptCfg); +} + +/** + * @brief TPU_Init + * + */ +void TPU_Init(void) +{ + TPU_E_Type *const pTPUE = TPU_E_BASE_PTRS; + + SCM_HWA_SUBSYS_PCC_SetEnable_TPUClock((bool)true); + TPU_E_HWA_SetTimeBaseCntStopInStopMode(pTPUE, (bool)true); +} + +/** + * @brief TPU_DeInit + * + */ +void TPU_DeInit(void) +{ + TPU_E_Type *const pTPUE = TPU_E_BASE_PTRS; + + TPU_E_HWA_TrigReset(pTPUE); +} + +/** + * @brief TPU_StartChannel + * + */ +void TPU_StartChannel(void) +{ + SCM_HWA_ConfigTpuGTBSelect((bool)true); +} + +/** + * @brief TPU_SetHSR + * + */ +void TPU_SetHSR(uint8_t u8channel, uint8_t u8HSRIdx) +{ + TPU_H_Type *const pTPUH = TPU_H_BASE_PTRS; + + TPU_H_HWA_SetChHSA(pTPUH, u8channel, true); + TPU_H_HWA_SetChHSRIdx(pTPUH, u8channel, u8HSRIdx); + TPU_H_HWA_SetChHSRISR(pTPUH, u8channel, (bool)true); + TPU_H_HWA_SetChSyncISR(pTPUH, u8channel, (bool)false); +} + +/** + * @brief TPU_SendHSR + * + */ +void TPU_SendHSR(uint8_t u8channel) +{ + TPU_H_Type *const pTPUH = TPU_H_BASE_PTRS; + + TPU_H_HWA_ClearChHSR(pTPUH, u8channel); +} + +/** + * @brief TPU_GetHSA + * + */ +uint8_t TPU_GetHSA(uint8_t u8Channel) +{ + TPU_H_Type *const pTPUH = TPU_H_BASE_PTRS; + + return TPU_H_HWA_GetChHSAIdx(pTPUH, (uint8_t)u8Channel); +} + +/** + * @brief TPU_InitChannelInterrupt + * + */ +void TPU_InitChannelHSAInterrupt(uint8_t u8Channel, const TPU_InterruptCfgType *const pInterruptCfg) +{ + s_TpuHSANotify[u8Channel] = pInterruptCfg->pHSANotify; +} + +/** + * @brief TPU_InitChannelOverflowInterrupt + * + */ +void TPU_InitChannelOverflowInterrupt(const TPU_InterruptCfgType *const pInterruptCfg) +{ + s_TpuTCR1OverflowNotify = pInterruptCfg->pTCR1OverflowNotify; + s_TpuTCR2OverflowNotify = pInterruptCfg->pTCR2OverflowNotify; +} + +/** + * @brief TPU_EnableSubSystem + * + */ +void TPU_EnableSubSystem(void) +{ + SCM_HWA_SUBSYS_PCC_SetEnable_SubSystemClock((bool)true); +} + +/** + * @brief TPU_EnableEventTrigDma + * + */ +void TPU_EnableEventTrigDma(uint8_t u8Channel) +{ + TPU_H_Type *const pTPUH = TPU_H_BASE_PTRS; + + TPU_H_HWA_SetChEventDMAEnable(pTPUH, (uint8_t)u8Channel, (bool)true); +} + +void TPU_EnableEventTrigTrgSel(uint8_t u8Channel, const TPU_InterruptCfgType *const pInterruptCfg) +{ + TPU_H_Type *const pTPUH = TPU_H_BASE_PTRS; + + TPU_H_HWA_SetChTrig(pTPUH, u8Channel, pInterruptCfg->eChTrigType); +} + +/** + * @brief TPU_EnableFlexcoreTrigDma + * + */ +void TPU_EnableFlexcoreTrigDma(uint8_t u8Channel) +{ + TPU_H_Type *const pTPUH = TPU_H_BASE_PTRS; + + TPU_H_HWA_SetChReqDMAEnable(pTPUH, (uint8_t)u8Channel, (bool)true); +} + +/** + * @brief TPU_PwmModeInit + * + */ +void TPU_PwmModeInit(uint8_t u8channel, const TPU_PwmCfgType *const p_etpu_config) +{ + TPU_E_Type *const pTPUE = TPU_E_BASE_PTRS; + uint32_t u32ER1_Val; + + TPU_E_HWA_ClearMatch1CFGFlg(pTPUE, u8channel); + TPU_E_HWA_ClearMatch1Event(pTPUE, u8channel); + TPU_E_HWA_ClearTransDetect1Event(pTPUE, u8channel); + TPU_E_HWA_ClearMatch2CFGFlg(pTPUE, u8channel); + TPU_E_HWA_ClearMatch2Event(pTPUE, u8channel); + TPU_E_HWA_ClearTransDetect2Event(pTPUE, u8channel); + TPU_E_HWA_SetOPAC1(pTPUE, u8channel, TPUE_NO_CHANGE_OUTPUT); + TPU_E_HWA_SetOPAC2(pTPUE, u8channel, TPUE_NO_CHANGE_OUTPUT); + TPU_E_HWA_SetTCR1ClkControl(pTPUE, TPUE_TCR1CLK_CLK_SRC_TPUCLKDIV2); + TPU_E_HWA_SetPDCM(pTPUE, u8channel, TPUE_EM_NB_ST); + TPU_E_HWA_SetTCR1MaxCnt(pTPUE, TPU_TCR1_MAXVALUE); + TPU_E_HWA_SetTCR2MaxCnt(pTPUE, TPU_TCR1_MAXVALUE); + + if (p_etpu_config->bPwmUseTCR1) + { + TPU_E_HWA_SetMatchER1(pTPUE, u8channel, (TPU_E_HWA_GetTCR1CntVal(pTPUE) + 1U)); + u32ER1_Val = TPU_E_HWA_GetER1Val(pTPUE, u8channel); + TPU_E_HWA_SetER2(pTPUE, u8channel, (p_etpu_config->u32ActiveTime + u32ER1_Val)); + } + + u32PwmNextEdge[u8channel] = TPU_E_HWA_GetER2Val(pTPUE, u8channel); + + TPU_E_HWA_SetChOutputActiveHigh(pTPUE, u8channel, p_etpu_config->bActiveHigh); + if (p_etpu_config->bActiveHigh) + { + TPU_E_HWA_SetOPAC1(pTPUE, u8channel, TPUE_MATCH_SET_OUTPUT_HIGH); + TPU_E_HWA_SetOPAC2(pTPUE, u8channel, TPUE_MATCH_SET_OUTPUT_LOW); + TPU_E_HWA_SetChTBS1(pTPUE, u8channel, p_etpu_config->eTBS1); + TPU_E_HWA_SetChTBS2(pTPUE, u8channel, p_etpu_config->eTBS2); + TPU_E_HWA_SetChEntryTblflag1(pTPUE, u8channel, (bool)true); + } + else + { + TPU_E_HWA_SetOPAC1(pTPUE, u8channel, TPUE_MATCH_SET_OUTPUT_LOW); + TPU_E_HWA_SetOPAC2(pTPUE, u8channel, TPUE_MATCH_SET_OUTPUT_HIGH); + TPU_E_HWA_SetChTBS1(pTPUE, u8channel, p_etpu_config->eTBS1); + TPU_E_HWA_SetChTBS2(pTPUE, u8channel, p_etpu_config->eTBS2); + TPU_E_HWA_SetChEntryTblflag1(pTPUE, u8channel, (bool)false); + } + /* Set channel priority */ + + /* Here do not enable NVIC */ + + TPU_E_HWA_SetOutputSelOPAC1(pTPUE, u8channel, (bool)true); + TPU_E_HWA_SetOutputSelOPAC2(pTPUE, u8channel, (bool)true); + TPU_E_HWA_EnableChOutputBuf(pTPUE, u8channel, (bool)true); + TPU_E_HWA_EnableMatch(pTPUE, u8channel, (bool)true); + TPU_E_HWA_EnableSrvReq(pTPUE, u8channel, (bool)true); + + return; +} + +/** + * @brief TPU_PwmServiceReq + * + */ +void TPU_PwmServiceReq(uint8_t u8channel, uint32_t u32ActiveTime, uint32_t u32Period) +{ + TPU_E_Type *const pTPUE = TPU_E_BASE_PTRS; + + if (TPU_E_HWA_GetChMatchRecLatch1Status(pTPUE, u8channel) == (bool)true) + { + /* in match1 */ + TPU_E_HWA_ClearMatch1Event(pTPUE, u8channel); + TPU_E_HWA_SetChEntryTblflag0(pTPUE, u8channel, (bool)false); + u32PwmLastFrame[u8channel] = TPU_E_HWA_GetER1Val(pTPUE, u8channel); + /* Next ER1 */ + if ((u32PwmLastFrame[u8channel] + u32Period) > TPU_TCR1_MAXVALUE) + { + TPU_E_HWA_SetMatchER1(pTPUE, u8channel, (u32PwmLastFrame[u8channel] + u32Period - TPU_TCR1_MAXVALUE - 1U)); + } + else + { + TPU_E_HWA_SetMatchER1(pTPUE, u8channel, (u32PwmLastFrame[u8channel] + u32Period)); + } + + if ((TPU_E_HWA_GetER1Val(pTPUE, u8channel) + u32ActiveTime) > TPU_TCR1_MAXVALUE) + { + u32PwmNextEdge[u8channel] = TPU_E_HWA_GetER1Val(pTPUE, u8channel) + u32ActiveTime - TPU_TCR1_MAXVALUE - 1U; + } + else + { + u32PwmNextEdge[u8channel] = TPU_E_HWA_GetER1Val(pTPUE, u8channel) + u32ActiveTime; + } + TPU_E_HWA_EnableMatch(pTPUE, u8channel, (bool)true); + } + else if (TPU_E_HWA_GetChMatchRecLatch2Status(pTPUE, u8channel) == (bool)true) + { + /* in match2 */ + TPU_E_HWA_ClearMatch2Event(pTPUE, u8channel); + TPU_E_HWA_SetChEntryTblflag0(pTPUE, u8channel, (bool)true); + /* Next ER2 */ + TPU_E_HWA_SetER2(pTPUE, u8channel, u32PwmNextEdge[u8channel]); + TPU_E_HWA_EnableMatch(pTPUE, u8channel, (bool)true); + } + TPU_E_HWA_ClearChEventISRFlg(pTPUE, (uint8_t)u8channel); +} + +/** + * @brief TPU_CaptureModeInit + * + */ +void TPU_CaptureModeInit(uint8_t u8channel, const TPU_CaptureCfgType *const p_etpu_config) +{ + TPU_E_Type *const pTPUE = TPU_E_BASE_PTRS; + + TPU_E_HWA_ClearMatchEn1(pTPUE, u8channel); + TPU_E_HWA_ClearMatch1CFGFlg(pTPUE, u8channel); + TPU_E_HWA_ClearMatch1Event(pTPUE, u8channel); + TPU_E_HWA_ClearTransDetect1Event(pTPUE, u8channel); + TPU_E_HWA_ClearMatch2CFGFlg(pTPUE, u8channel); + TPU_E_HWA_ClearMatch2Event(pTPUE, u8channel); + TPU_E_HWA_ClearTransDetect2Event(pTPUE, u8channel); + TPU_E_HWA_SetTCR1ClkControl(pTPUE, TPUE_TCR1CLK_CLK_SRC_TPUCLKDIV2); + TPU_E_HWA_SetChTBS1(pTPUE, u8channel, TPUE_GREATER_OR_EQUAL_CAPBASE_TCR1_MATCHBASE_TCR1); + TPU_E_HWA_SetChTBS2(pTPUE, u8channel, TPUE_GREATER_OR_EQUAL_CAPBASE_TCR1_MATCHBASE_TCR1); + TPU_E_HWA_SetOPAC1(pTPUE, u8channel, TPUE_NO_CHANGE_OUTPUT); + TPU_E_HWA_SetOPAC2(pTPUE, u8channel, TPUE_NO_CHANGE_OUTPUT); + TPU_E_HWA_SetChEntryTblflag1(pTPUE, u8channel, (bool)false); + TPU_E_HWA_SetChEntryTblflag0(pTPUE, u8channel, (bool)false); + TPU_E_HWA_SetTCR1MaxCnt(pTPUE, TPU_TCR1_MAXVALUE); + TPU_E_HWA_SetTCR2MaxCnt(pTPUE, TPU_TCR1_MAXVALUE); + + if (p_etpu_config->eMeasureMode == TPU_DutyMeasurementActiveHigh) + { + TPU_E_HWA_SetPDCM(pTPUE, u8channel, TPUE_SM_DT); + TPU_E_HWA_SetIPAC1(pTPUE, u8channel, TPUE_DETECT_RISING_EDGE_ONLY); + TPU_E_HWA_SetIPAC2(pTPUE, u8channel, TPUE_DETECT_FALLING_EDGE_ONLY); + } + else if (p_etpu_config->eMeasureMode == TPU_DutyMeasurementActiveLow) + { + TPU_E_HWA_SetPDCM(pTPUE, u8channel, TPUE_SM_DT); + TPU_E_HWA_SetIPAC1(pTPUE, u8channel, TPUE_DETECT_FALLING_EDGE_ONLY); + TPU_E_HWA_SetIPAC2(pTPUE, u8channel, TPUE_DETECT_RISING_EDGE_ONLY); + } + else if (p_etpu_config->eMeasureMode == TPU_PeriodMeasurement) + { + TPU_E_HWA_SetPDCM(pTPUE, u8channel, TPUE_SM_ST); + TPU_E_HWA_SetIPAC1(pTPUE, u8channel, p_etpu_config->eInputType); + TPU_E_HWA_SetIPAC2(pTPUE, u8channel, TPUE_NO_TRANSITIONS); + } + else + { + /* do nothing */ + } + + TPU_E_HWA_SetMatchER1(pTPUE, u8channel, (TPU_E_HWA_GetTCR1CntVal(pTPUE) + p_etpu_config->u32SampleTime)); + TPU_E_HWA_EnableTransContinue(pTPUE, u8channel, (bool)true); + + /* Here not set channel priority */ + + /* Here not enable NVIC */ + + TPU_E_HWA_EnableChEventInt(pTPUE, u8channel, (bool)true); + TPU_E_HWA_EnableMatch(pTPUE, u8channel, (bool)true); + TPU_E_HWA_EnableSrvReq(pTPUE, u8channel, (bool)true); + + return; +} + +/** + * @brief TPU_CaptureMeasPeriodServiceReq + * + */ +void TPU_CaptureMeasPeriodServiceReq(uint8_t u8channel, TPU_CaptureCfgType *p_etpu_config) +{ + TPU_E_Type *const pTPUE = TPU_E_BASE_PTRS; + volatile bool bMeasurement = TPU_E_HWA_GetChEntryTblflag1(pTPUE, u8channel); + + if (TPU_E_HWA_GetChMatchRecLatch1Status(pTPUE, u8channel) == (bool)true) + { + TPU_E_HWA_ClearMatch1Event(pTPUE, u8channel); + TPU_E_HWA_ClearTransDetect1Event(pTPUE, u8channel); + TPU_E_HWA_ClearTransDetect2Event(pTPUE, u8channel); + p_etpu_config->LastTime = TPU_E_HWA_GetER1Val(pTPUE, u8channel); + TPU_E_HWA_SetMatchER1(pTPUE, u8channel, (p_etpu_config->LastTime + p_etpu_config->u32SampleTime)); + TPU_E_HWA_EnableMatch(pTPUE, u8channel, (bool)true); + TPU_E_HWA_ClearChEventISRFlg(pTPUE, (uint8_t)u8channel); + TPU_E_HWA_SetChEntryTblflag1(pTPUE, u8channel, (bool)false); + p_etpu_config->u32PeriodTime = 0; + } + else if (TPU_E_HWA_GetChTransDetectLatch1Status(pTPUE, u8channel) == (bool)true) + { + TPU_E_HWA_ClearTransDetect1Event(pTPUE, u8channel); + TPU_E_HWA_ClearChEventISRFlg(pTPUE, (uint8_t)u8channel); + /* transition happened */ + if (bMeasurement) + { + /* Complete once normal measurement */ + if (TPU_E_HWA_GetCaptureER1Val(pTPUE, u8channel) >= p_etpu_config->LastTime) + { + p_etpu_config->u32PeriodTime = (TPU_E_HWA_GetCaptureER1Val(pTPUE, u8channel) - p_etpu_config->LastTime); + } + else + { + p_etpu_config->u32PeriodTime = (TPU_E_HWA_GetCaptureER1Val(pTPUE, u8channel) + TPU_TCR1_MAXVALUE - p_etpu_config->LastTime + 1U); + } + + TPU_E_HWA_SetChEntryTblflag1(pTPUE, u8channel, (bool)false); + } + /* Start normal measurement */ + p_etpu_config->LastTime = TPU_E_HWA_GetCaptureER1Val(pTPUE, u8channel); + TPU_E_HWA_SetMatchER1(pTPUE, u8channel, (p_etpu_config->LastTime + p_etpu_config->u32SampleTime)); + + /* bMeasurement = active */ + TPU_E_HWA_EnableMatch(pTPUE, u8channel, (bool)true); + TPU_E_HWA_SetChEntryTblflag1(pTPUE, u8channel, (bool)true); + } +} + +/** + * @brief TPU_CaptureMeasActiveLowServiceReq + * + */ +void TPU_CaptureMeasActivePeriodServiceReq(uint8_t u8channel, TPU_CaptureCfgType *p_etpu_config) +{ + TPU_E_Type *const pTPUE = TPU_E_BASE_PTRS; + + if (TPU_E_HWA_GetChMatchRecLatch1Status(pTPUE, u8channel) == (bool)true) + { + TPU_E_HWA_ClearMatch1Event(pTPUE, u8channel); + TPU_E_HWA_ClearTransDetect1Event(pTPUE, u8channel); + TPU_E_HWA_ClearTransDetect2Event(pTPUE, u8channel); + p_etpu_config->LastTime = TPU_E_HWA_GetER1Val(pTPUE, u8channel); + TPU_E_HWA_SetMatchER1(pTPUE, u8channel, (p_etpu_config->LastTime + p_etpu_config->u32SampleTime)); + TPU_E_HWA_EnableMatch(pTPUE, u8channel, (bool)true); + TPU_E_HWA_ClearChEventISRFlg(pTPUE, (uint8_t)u8channel); + p_etpu_config->u32PeriodTime = 0; + p_etpu_config->u32ActiveTime = 0; + bMeasActivePeriodComplete[u8channel] = (bool)false; + } + else if ((TPU_E_HWA_GetChTransDetectLatch1Status(pTPUE, u8channel) == (bool)true) || (TPU_E_HWA_GetChTransDetectLatch2Status(pTPUE, u8channel) == (bool)true)) + { + /* transition1 or 2 happened */ + TPU_E_HWA_ClearTransDetect1Event(pTPUE, u8channel); + TPU_E_HWA_ClearTransDetect2Event(pTPUE, u8channel); + TPU_E_HWA_ClearChEventISRFlg(pTPUE, (uint8_t)u8channel); + + /* ER1 stores TCR1 in IPAC1 edge */ + /* Here calculate period */ + if (bMeasActivePeriodComplete[u8channel]) + { + /* Complete once normal measurement */ + if (TPU_E_HWA_GetCaptureER1Val(pTPUE, u8channel) >= p_etpu_config->StartTime) + { + p_etpu_config->u32PeriodTime = (TPU_E_HWA_GetCaptureER1Val(pTPUE, u8channel) - p_etpu_config->StartTime); + } + else + { + p_etpu_config->u32PeriodTime = (TPU_E_HWA_GetCaptureER1Val(pTPUE, u8channel) + TPU_TCR1_MAXVALUE - p_etpu_config->StartTime + 1); + } + + /* MeasurementComplete = inactive */ + bMeasActivePeriodComplete[u8channel] = (bool)false; + } + + /* Start normal low measurement */ + p_etpu_config->LastTime = TPU_E_HWA_GetCaptureER1Val(pTPUE, u8channel); + p_etpu_config->StartTime = p_etpu_config->LastTime; + + /* ER2 stores TCR1 in IPAC2 edge */ + /* Complete once normal measurement */ + if (TPU_E_HWA_GetCaptureER2Val(pTPUE, u8channel) >= p_etpu_config->LastTime) + { + p_etpu_config->u32ActiveTime = (TPU_E_HWA_GetCaptureER2Val(pTPUE, u8channel) - p_etpu_config->LastTime); + } + else + { + p_etpu_config->u32ActiveTime = (TPU_E_HWA_GetCaptureER2Val(pTPUE, u8channel) + TPU_TCR1_MAXVALUE - p_etpu_config->LastTime + 1); + } + + /* MeasurementComplete = active */ + bMeasActivePeriodComplete[u8channel] = (bool)true; + + /* Waiting for first IPAC1 edge */ + p_etpu_config->LastTime = TPU_E_HWA_GetCaptureER2Val(pTPUE, u8channel); + TPU_E_HWA_SetMatchER1(pTPUE, u8channel, (p_etpu_config->LastTime + p_etpu_config->u32SampleTime)); + TPU_E_HWA_EnableMatch(pTPUE, u8channel, (bool)true); + } +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_trgsel.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_trgsel.c new file mode 100644 index 0000000..2043fe6 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_trgsel.c @@ -0,0 +1,314 @@ +/** + * @file fc7xxx_driver_trgsel.c + * @author Flagchip0103 + * @brief FC7xxx TRGSEL driver source code + * @version 0.1.0 + * @date 2023-12-19 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + */ +/* ******************************************************************************** + * Revision History: + * + * Version Date Initials CR# Descriptions + * --------- ---------- ------------ ---------- --------------- + * 0.1.0 2023-12-19 Flagchip0103 N/A First version for FC7240 + ******************************************************************************** */ + +#include + +#include "fc7xxx_driver_trgsel.h" +#include "HwA_trgsel.h" +#include "HwA_scm.h" + +/** + * @brief Number of target outputs of TrgSel 0 + * + */ +#define TRGSEL0_NUM_OUTPUTS 38U + +/** + * @brief Number of target outputs of TrgSel 1 + * + */ +#define TRGSEL1_NUM_OUTPUTS 28U + +/** + * @brief Number of target outputs of TrgSel 2 + * + */ +#define TRGSEL2_NUM_OUTPUTS 30U + +/** + * @brief Number of target outputs of TrgSel 3 + * + */ +#define TRGSEL3_NUM_OUTPUTS 16U + +/** + * @brief Number of target outputs of TrgSel 4 + * + */ +#define TRGSEL4_NUM_OUTPUTS 10U + +/** + * @brief Number of target outputs of TrgSel 5 + * + */ +#define TRGSEL5_NUM_OUTPUTS 13U + +/** + * @brief Number of input sources of TrgSel 0 + * + */ +#define TRGSEL0_NUM_SOURCES 128U + +/** + * @brief Number of input sources of TrgSel 1 + * + */ +#define TRGSEL1_NUM_SOURCES 94U + +/** + * @brief Number of input sources of TrgSel 2 + * + */ +#define TRGSEL2_NUM_SOURCES 32U + +/** + * @brief Number of input sources of TrgSel 3 + * + */ +#define TRGSEL3_NUM_SOURCES 62U + +/** + * @brief Number of input sources of TrgSel 4 + * + */ +#define TRGSEL4_NUM_SOURCES 112U + +/** + * @brief Number of input sources of TrgSel 5 + * + */ +#define TRGSEL5_NUM_SOURCES 64U + +#define TRGSEL_NUM_SW_TRG_CHANNELS 8U + +static TRGSEL_Type *const s_trgselBase[TRGSEL_INSTANCE_COUNT] = TRGSEL_BASE_PTRS; + +#ifndef NDEBUG +/** + * @brief Check whether the TRGSEL target is valid for the TRGSEL instance + * + * @param eInstance the selected TRGSEL instance + * @param eTarget the target value to check + * @return true the TRGSEL target is valid + * @return false the TRGSEL target is invalid + */ +static inline bool TRGSEL_IsValidTarget(const TRGSEL_InstanceType eInstance, const TRGSEL_TargetType eTarget); + +/** + * @brief Check whether the TRGSEL source is valid for the TRGSEL instance + * + * @param eInstance the selected TRGSEL instance + * @param eSource the source value to check + * @return true the TRGSEL source is valid + * @return false the TRGSEL source is invalid + */ +static inline bool TRGSEL_IsValidSource(const TRGSEL_InstanceType eInstance, const TRGSEL_SourceType eSource); + +static inline bool TRGSEL_IsValidTarget(const TRGSEL_InstanceType eInstance, const TRGSEL_TargetType eTarget) +{ + bool bRet = false; + switch (eInstance) + { + case TRGSEL_INSTANCE_0: + { + bRet = (bool)((eTarget < TRGSEL0_NUM_OUTPUTS) ? true : false); + break; + } + + case TRGSEL_INSTANCE_1: + { + bRet = (bool)((eTarget < TRGSEL1_NUM_OUTPUTS) ? true : false); + break; + } + + case TRGSEL_INSTANCE_2: + { + bRet = (bool)((eTarget < TRGSEL2_NUM_OUTPUTS) ? true : false); + break; + } + + case TRGSEL_INSTANCE_3: + { + bRet = (bool)((eTarget < TRGSEL3_NUM_OUTPUTS) ? true : false); + break; + } + + case TRGSEL_INSTANCE_4: + { + bRet = (bool)((eTarget < TRGSEL4_NUM_OUTPUTS) ? true : false); + break; + } + + case TRGSEL_INSTANCE_5: + { + bRet = (bool)((eTarget < TRGSEL5_NUM_OUTPUTS) ? true : false); + break; + } + + default: + break; + } + return bRet; +} + +static inline bool TRGSEL_IsValidSource(const TRGSEL_InstanceType eInstance, const TRGSEL_SourceType eSource) +{ + bool bRet = false; + switch (eInstance) + { + case TRGSEL_INSTANCE_0: + { + bRet = (bool)((eSource < TRGSEL0_NUM_SOURCES) ? true : false); + break; + } + + case TRGSEL_INSTANCE_1: + { + bRet = (bool)((eSource < TRGSEL1_NUM_SOURCES) ? true : false); + break; + } + + case TRGSEL_INSTANCE_2: + { + bRet = (bool)((eSource < TRGSEL2_NUM_SOURCES) ? true : false); + break; + } + + case TRGSEL_INSTANCE_3: + { + bRet = (bool)((eSource < TRGSEL3_NUM_SOURCES) ? true : false); + break; + } + + case TRGSEL_INSTANCE_4: + { + bRet = (bool)((eSource < TRGSEL4_NUM_SOURCES) ? true : false); + break; + } + + case TRGSEL_INSTANCE_5: + { + bRet = (bool)((eSource < TRGSEL5_NUM_SOURCES) ? true : false); + break; + } + + default: + break; + } + return bRet; +} +#endif + +TRGSEL_SourceType TRGSEL_GetTargetTriggerSource(const TRGSEL_InstanceType eInstance, const TRGSEL_TargetType eTarget) +{ + DEV_ASSERT(eInstance < TRGSEL_INSTANCE_COUNT); + DEV_ASSERT(TRGSEL_IsValidTarget(eInstance, eTarget)); + + const TRGSEL_Type *const pTrgsel = s_trgselBase[eInstance]; + + uint32_t u32Tmp = TRGSEL_HWA_GetTargetTriggerSource(pTrgsel, eTarget); + + return (TRGSEL_SourceType)u32Tmp; +} + +void TRGSEL_SetTargetTriggerSource(const TRGSEL_InstanceType eInstance, const TRGSEL_TargetType eTarget, + const TRGSEL_SourceType eSource) +{ + DEV_ASSERT(eInstance < TRGSEL_INSTANCE_COUNT); + DEV_ASSERT(TRGSEL_IsValidTarget(eInstance, eTarget)); + DEV_ASSERT(TRGSEL_IsValidSource(eInstance, eSource)); + DEV_ASSERT(TRGSEL_GetTargetLockStatus(eInstance, eTarget) != true); + + TRGSEL_Type *const pTrgsel = s_trgselBase[eInstance]; + + TRGSEL_HWA_SetTargetTriggerSource(pTrgsel, eTarget, eSource); +} + +bool TRGSEL_GetTargetLockStatus(const TRGSEL_InstanceType eInstance, const TRGSEL_TargetType eTarget) +{ + DEV_ASSERT(eInstance < TRGSEL_INSTANCE_COUNT); + DEV_ASSERT(TRGSEL_IsValidTarget(eInstance, eTarget)); + + const TRGSEL_Type *const pTrgsel = s_trgselBase[eInstance]; + + return TRGSEL_HWA_GetTargetLockStatus(pTrgsel, eTarget); +} + +void TRGSEL_LockTargetTriggerSource(const TRGSEL_InstanceType eInstance, const TRGSEL_TargetType eTarget) +{ + DEV_ASSERT(eInstance < TRGSEL_INSTANCE_COUNT); + DEV_ASSERT(TRGSEL_IsValidTarget(eInstance, eTarget)); + + TRGSEL_Type *const pTrgsel = s_trgselBase[eInstance]; + + if (TRGSEL_GetTargetLockStatus(eInstance, eTarget) != true) + { + TRGSEL_HWA_LockTargetTriggerSource(pTrgsel, eTarget); + } +} + +void TRGSEL_GenerateSwTrigger(const TRGSEL_SwTriggerChannelType eChannel) +{ + DEV_ASSERT(eChannel < TRGSEL_NUM_SW_TRG_CHANNELS); + + switch (eChannel) + { + case TRGSEL_SW_TRIGGER_CHANNEL_0: + { + SCM_HWA_SetSwTrigx_Trgsel04(SCM_SW_TRIG_0); + break; + } + case TRGSEL_SW_TRIGGER_CHANNEL_1: + { + SCM_HWA_SetSwTrigx_Trgsel04(SCM_SW_TRIG_1); + break; + } + case TRGSEL_SW_TRIGGER_CHANNEL_2: + { + SCM_HWA_SetSwTrigx_Trgsel04(SCM_SW_TRIG_2); + break; + } + case TRGSEL_SW_TRIGGER_CHANNEL_3: + { + SCM_HWA_SetSwTrigx_Trgsel04(SCM_SW_TRIG_3); + break; + } + case TRGSEL_SW_TRIGGER_CHANNEL_4: + { + SCM_HWA_SetSwTrigx_Trgsel15(SCM_SW_TRIG_4); + break; + } + case TRGSEL_SW_TRIGGER_CHANNEL_5: + { + SCM_HWA_SetSwTrigx_Trgsel15(SCM_SW_TRIG_5); + break; + } + case TRGSEL_SW_TRIGGER_CHANNEL_6: + { + SCM_HWA_SetSwTrigx_Trgsel15(SCM_SW_TRIG_6); + break; + } + case TRGSEL_SW_TRIGGER_CHANNEL_7: + { + SCM_HWA_SetSwTrigx_Trgsel15(SCM_SW_TRIG_7); + break; + } + default: + break; + } +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_tstmp.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_tstmp.c new file mode 100644 index 0000000..0856be5 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_tstmp.c @@ -0,0 +1,420 @@ +/** + * @file fc7xxx_driver_tstmp.c + * @author Flagchip + * @brief FC7xxx TSTMP driver source code + * @version 0.1.0 + * @date 2024-01-14 + * + * @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/******************************************************************************** +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2024-01-14 Flagchip0122 N/A FC7xxx internal release version +********************************************************************************/ + +#include "fc7xxx_driver_tstmp.h" +#include "interrupt_manager.h" + +/** @brief Tstmp instance list */ +static TSTMP_Type *s_pTstmpPtrs[TSTMP_INSTANCE_COUNT] = TSTMP_BASE_PTRS; +/** @brief Tstmp user defined interrupt function */ +static TSTMP_InterruptCallBackType s_pTstmpModulateNotifyPtr[TSTMP_INSTANCE_COUNT][MAX_MOD_NUMBER] = {NULL}; + +/** @brief TSTMP0 interrupt entry */ +void TSTMP0_IRQHandler(void); +/** @brief TSTMP1 interrupt entry */ +void TSTMP1_IRQHandler(void); + +/** @brief TSTMP common interrupt function */ +static void Tstmp_CommonProcessInterrupt(const TSTMP_InstanceType eInstance, const TSTMP_ModulateType eIntModulate); + +/** + * @brief Initialize TSTMP instance + * + * @param eInstance TSTMP instance + * @param pInitStruct TSTMP initialization structure + * @return TSTMP_StatusType TSTMP return type + * @note TSTMP0 clock source is 1MHZ and TSTMP1,TSTMP2,TSTMP3 clock source is bus clock + */ +TSTMP_StatusType TSTMP_Init(const TSTMP_InstanceType eInstance, const TSTMP_InitType *const pInitStruct) +{ + TSTMP_Type *pTstmp; + TSTMP_StatusType eRet = TSTMP_STATUS_SUCCESS; + if ((NULL == pInitStruct) || (eInstance >= TSTMP_INSTANCE_MAX)) + { + eRet = TSTMP_STATUS_PARAM_INVALID; + } + else + { + pTstmp = s_pTstmpPtrs[eInstance]; + /* clear MOD(n) match flag */ + TSTMP_HWA_ClearMod0MatchFlag(pTstmp); + TSTMP_HWA_ClearAllMod123MatchFlag(pTstmp); + + for(uint8_t i = 0; i < MAX_MOD_NUMBER; i++) + { + TSTMP_HWA_SelectClkSource(pTstmp, (TSTMP_ModulateType)i, pInitStruct->pClk[i]); + } + /* set MOD0 match value */ + TSTMP_HWA_SetModMatchValue(pTstmp, TSTMP_MOD0, pInitStruct->u32Modulate0Value); + /* set MOD1 match value */ + TSTMP_HWA_SetModMatchValue(pTstmp, TSTMP_MOD1, pInitStruct->u32Modulate1Value); + /* set MOD2 match value */ + TSTMP_HWA_SetModMatchValue(pTstmp, TSTMP_MOD2, pInitStruct->u32Modulate2Value); + /* set MOD3 match value */ + TSTMP_HWA_SetModMatchValue(pTstmp, TSTMP_MOD3, pInitStruct->u32Modulate3Value); + } + + return eRet; +} + +/** + * @brief Set the Counting mode of modulate timer counter0,1,2,3 + * + * @param eInstance TSTMP instance + * @param eCounter0Mode Counting mode of counter0 + * @param eCounter1Mode Counting mode of counter1 + * @param eCounter2Mode Counting mode of counter2 + * @param eCounter3Mode Counting mode of counter3 + * @return TSTMP_StatusType TSTMP return type + */ +TSTMP_StatusType TSTMP_SetCounterRunningMode(const TSTMP_InstanceType eInstance, const TSTMP_ModeCounterRunningMode eCounter0Mode, + const TSTMP_ModeCounterRunningMode eCounter1Mode,const TSTMP_ModeCounterRunningMode eCounter2Mode, + const TSTMP_ModeCounterRunningMode eCounter3Mode) +{ + TSTMP_Type *pTstmp; + TSTMP_StatusType eRet = TSTMP_STATUS_SUCCESS; + if (eInstance >= TSTMP_INSTANCE_MAX) + { + eRet = TSTMP_STATUS_PARAM_INVALID; + } + if( (eCounter0Mode > TSTMP_MODE_PERIOD_RUNNING) || (eCounter1Mode > TSTMP_MODE_PERIOD_RUNNING) || + (eCounter2Mode > TSTMP_MODE_PERIOD_RUNNING) || (eCounter3Mode > TSTMP_MODE_PERIOD_RUNNING)) + { + eRet = TSTMP_STATUS_PARAM_INVALID; + } + if(eRet == TSTMP_STATUS_SUCCESS) + { + pTstmp = s_pTstmpPtrs[eInstance]; + TSTMP_HWA_SetModCounterMode(pTstmp,TSTMP_MOD0, eCounter0Mode); + TSTMP_HWA_SetModCounterMode(pTstmp,TSTMP_MOD1, eCounter1Mode); + TSTMP_HWA_SetModCounterMode(pTstmp,TSTMP_MOD2, eCounter2Mode); + TSTMP_HWA_SetModCounterMode(pTstmp,TSTMP_MOD3, eCounter3Mode); + } + return eRet; +} +/** + * @brief De-initialize TSTMP instance + * + * @param eInstance TSTMP instance + * @return TSTMP_StatusType TSTMP return type + */ +TSTMP_StatusType TSTMP_Deinit(const TSTMP_InstanceType eInstance) +{ + TSTMP_Type *pTstmp; + TSTMP_StatusType eRet = TSTMP_STATUS_SUCCESS; + uint8_t u8Index; + if (eInstance >= TSTMP_INSTANCE_MAX) + { + eRet = TSTMP_STATUS_PARAM_INVALID; + } + else + { + pTstmp = s_pTstmpPtrs[eInstance]; + for (u8Index = 0U; u8Index < MAX_MOD_NUMBER; u8Index++) + { + /* Disable TSTMP MOD(n) match interrupt */ + TSTMP_HWA_DisableModMatchInterrupt(pTstmp, (TSTMP_ModulateType)u8Index); + /* Disable TSTMP MOD(n) counter */ + TSTMP_HWA_DisableModCounter(pTstmp, (TSTMP_ModulateType)u8Index); + /* Clear TSTMP MOD(n) match value set*/ + TSTMP_HWA_SetModMatchValue(pTstmp, (TSTMP_ModulateType)u8Index, (uint32_t)0U); + s_pTstmpModulateNotifyPtr[eInstance][u8Index] = NULL; + } + /* clear MOD(n) match flag */ + TSTMP_HWA_ClearMod0MatchFlag(pTstmp); + TSTMP_HWA_ClearAllMod123MatchFlag(pTstmp); + } + return eRet; +} + +/** + * @brief Initialize TSTMP interrupt functionality + * + * @param eInstance TSTMP instance + * @param pIntStruct TSTMP interrupt structure + * @return TSTMP_StatusType TSTMP return type + */ +TSTMP_StatusType TSTMP_InitInterrupt(const TSTMP_InstanceType eInstance, const TSTMP_IntType *const pIntStruct) +{ + TSTMP_StatusType eRet = TSTMP_STATUS_SUCCESS; + TSTMP_Type *pTstmp; + uint8_t u8Index; + if ((NULL == pIntStruct) || (eInstance >= TSTMP_INSTANCE_MAX)) + { + eRet = TSTMP_STATUS_PARAM_INVALID; + } + else + { + pTstmp = s_pTstmpPtrs[eInstance]; + for (u8Index = 0U; u8Index < MAX_MOD_NUMBER; u8Index++) + { + if (pIntStruct->bModulateIntEn[u8Index] == true) + { + /* Enable TSTMP MOD(n) match interrupt */ + TSTMP_HWA_EnableModMatchInterrupt(pTstmp, (TSTMP_ModulateType)u8Index); + s_pTstmpModulateNotifyPtr[eInstance][u8Index] = pIntStruct->pIsrModNotify[u8Index]; + } + else + { + /* Disable TSTMP MOD(n) match interrupt */ + TSTMP_HWA_DisableModMatchInterrupt(pTstmp, (TSTMP_ModulateType)u8Index); + s_pTstmpModulateNotifyPtr[eInstance][u8Index] = NULL; + } + } + } + return eRet; +} + +/** + * @brief Enable TSTMP interrupt function + * + * @param eInstance TSTMP instance + * @param eMod TSTMP modulate enumeration + * @return TSTMP_StatusType TSTMP return type + */ +TSTMP_StatusType TSTMP_EnableInterrupt(const TSTMP_InstanceType eInstance, const TSTMP_ModulateType eMod) +{ + TSTMP_StatusType eRet = TSTMP_STATUS_SUCCESS; + TSTMP_Type *pTstmp; + if (((uint8_t)eMod >= MAX_MOD_NUMBER) || (eInstance >= TSTMP_INSTANCE_MAX)) + { + eRet = TSTMP_STATUS_PARAM_INVALID; + } + else + { + pTstmp = s_pTstmpPtrs[eInstance]; + /* Enable TSTMP MOD(n) match interrupt */ + TSTMP_HWA_EnableModMatchInterrupt(pTstmp, eMod); + } + + return eRet; +} + +/** + * @brief Disable TSTMP interrupt function + * + * @param eInstance TSTMP instance + * @param eMod TSTMP modulate enumeration + * @return TSTMP_StatusType TSTMP return type + */ +TSTMP_StatusType TSTMP_DisableInterrupt(const TSTMP_InstanceType eInstance, const TSTMP_ModulateType eMod) +{ + TSTMP_StatusType eRet = TSTMP_STATUS_SUCCESS; + TSTMP_Type *pTstmp; + if (((uint8_t)eMod >= MAX_MOD_NUMBER) || (eInstance >= TSTMP_INSTANCE_MAX)) + { + eRet = TSTMP_STATUS_PARAM_INVALID; + } + else + { + pTstmp = s_pTstmpPtrs[eInstance]; + /* Disable TSTMP MOD(n) match interrupt */ + TSTMP_HWA_DisableModMatchInterrupt(pTstmp, eMod); + } + + return eRet; +} + +/** + * @brief Get TSTMP count value + * + * @param eInstance TSTMP instance + * @param u64TstmpValue in/out value + * @return TSTMP_StatusType TSTMP return type + */ +TSTMP_StatusType TSTMP_GetTstmpValue(const TSTMP_InstanceType eInstance, uint64_t *const u64TstmpValue) +{ + TSTMP_StatusType eRet = TSTMP_STATUS_SUCCESS; + TSTMP_Type *pTstmp; + if ((NULL == u64TstmpValue) || (eInstance >= TSTMP_INSTANCE_MAX)) + { + eRet = TSTMP_STATUS_PARAM_INVALID; + } + else + { + pTstmp = s_pTstmpPtrs[eInstance]; + *u64TstmpValue = TSTMP_HWA_ReadTstmpValue(pTstmp); + } + return eRet; +} + +/** + * @brief Update Modulate configuration + * + * @param eInstance TSTMP instance + * @param pUpdateStruct TSTMP update structure pointer + * @return TSTMP_StatusType TSTMP return type + */ +TSTMP_StatusType TSTMP_UpdateMod(const TSTMP_InstanceType eInstance, const TSTMP_UpdateType *const pUpdateStruct) +{ + TSTMP_StatusType eRet = TSTMP_STATUS_SUCCESS; + TSTMP_Type *pTstmp; + bool bIntEnStatus; + if ((NULL == pUpdateStruct) || (eInstance >= TSTMP_INSTANCE_MAX)) + { + eRet = TSTMP_STATUS_PARAM_INVALID; + } + else + { + pTstmp = s_pTstmpPtrs[eInstance]; + /* Clear MOD(n) interrupt flag */ + if (TSTMP_MOD0 == pUpdateStruct->eMod) + { + TSTMP_HWA_ClearMod0MatchFlag(pTstmp); + } + else + { + TSTMP_HWA_ClearSingleMod123MatchFlag(pTstmp, pUpdateStruct->eMod); + } + bIntEnStatus = (bool)(((uint32_t)0U == (TSTMP_HWA_ReadTstmpInterruptEnable(pTstmp) & + TSTMP_MOD_INTEN_MOD0_INTEN_MASK << (pUpdateStruct->eMod))) ? true : false); + if ((pUpdateStruct->bIntEn) == true) + { + if(bIntEnStatus == true) + { + /* Enable TSTMP MOD(n) match interrupt */ + TSTMP_HWA_EnableModMatchInterrupt(pTstmp, pUpdateStruct->eMod); + if (NULL != pUpdateStruct->pIsrModNotify) + { + s_pTstmpModulateNotifyPtr[eInstance][pUpdateStruct->eMod] = pUpdateStruct->pIsrModNotify; + } + } + }else + { + if(bIntEnStatus == false) + { + /* Disable TSTMP MOD(n) match interrupt */ + TSTMP_HWA_DisableModMatchInterrupt(pTstmp, pUpdateStruct->eMod); + } + } + /* set MOD(n) match value */ + TSTMP_HWA_SetModMatchValue(pTstmp, pUpdateStruct->eMod, pUpdateStruct->u32ModValue); + } + return eRet; +} + +/** + * @brief Set counter MOD(n) counting on or off + * + * @param eInstance TSTMP instance + * @param eMod MOD number + * @param bCounterEn Whether enable the selected Modulate Timer Counter + * @return TSTMP_StatusType TSTMP return type + */ +TSTMP_StatusType TSTMP_SetModCountConfig(const TSTMP_InstanceType eInstance, const TSTMP_ModulateType eMod, const bool bCounterEn) +{ + TSTMP_StatusType eRet = TSTMP_STATUS_SUCCESS; + TSTMP_Type *pTstmp; + if (eInstance >= TSTMP_INSTANCE_MAX || eMod > TSTMP_MOD3) + { + eRet = TSTMP_STATUS_PARAM_INVALID; + } + else + { + pTstmp = s_pTstmpPtrs[eInstance]; + if(bCounterEn) + { + TSTMP_HWA_EnableModCounter(pTstmp, eMod); + }else + { + TSTMP_HWA_DisableModCounter(pTstmp, eMod); + } + } + return eRet; +} + +/** + * @brief TSTMP common interrupt function + * + * @param eInstance TSTMP instance + * @param eIntModulate TSTMP modulate + */ +static void Tstmp_CommonProcessInterrupt(const TSTMP_InstanceType eInstance, const TSTMP_ModulateType eIntModulate) +{ + if (NULL != s_pTstmpModulateNotifyPtr[eInstance][eIntModulate]) + { + s_pTstmpModulateNotifyPtr[eInstance][eIntModulate](); + } +} + +/** + * @brief TSTMP0 interrupt handler entry + * + */ +void TSTMP0_IRQHandler(void) +{ + uint32_t u32TstmpStatus = TSTMP_HWA_ReadModMatchFlag(TSTMP0); + if ((u32TstmpStatus & TSTMP_MOD_STATUS_MOD0_MATCH_MASK)>>TSTMP_MOD_STATUS_MOD0_MATCH_SHIFT == 1U) + { + Tstmp_CommonProcessInterrupt(TSTMP_INSTANCE_0, TSTMP_MOD0); + /* Clear MOD0 interrupt flag */ + TSTMP_HWA_ClearMod0MatchFlag(TSTMP0); + } + if ((u32TstmpStatus & TSTMP_MOD_STATUS_MOD1_MATCH_MASK)>>TSTMP_MOD_STATUS_MOD1_MATCH_SHIFT == 1U) + { + Tstmp_CommonProcessInterrupt(TSTMP_INSTANCE_0, TSTMP_MOD1); + /* Clear MOD1 interrupt flag */ + TSTMP_HWA_ClearSingleMod123MatchFlag(TSTMP0, TSTMP_MOD1); + } + if ((u32TstmpStatus & TSTMP_MOD_STATUS_MOD2_MATCH_MASK)>>TSTMP_MOD_STATUS_MOD2_MATCH_SHIFT == 1U) + { + Tstmp_CommonProcessInterrupt(TSTMP_INSTANCE_0, TSTMP_MOD2); + /* Clear MOD2 interrupt flag */ + TSTMP_HWA_ClearSingleMod123MatchFlag(TSTMP0, TSTMP_MOD2); + } + if ((u32TstmpStatus & TSTMP_MOD_STATUS_MOD3_MATCH_MASK)>>TSTMP_MOD_STATUS_MOD3_MATCH_SHIFT == 1U) + { + Tstmp_CommonProcessInterrupt(TSTMP_INSTANCE_0, TSTMP_MOD3); + /* Clear MOD3 interrupt flag */ + TSTMP_HWA_ClearSingleMod123MatchFlag(TSTMP0, TSTMP_MOD3); + } +} + +/** + * @brief TSTMP1 interrupt handler entry + * + */ +void TSTMP1_IRQHandler(void) +{ + uint32_t u32TstmpStatus = TSTMP_HWA_ReadModMatchFlag(TSTMP1); + if ((u32TstmpStatus & TSTMP_MOD_STATUS_MOD0_MATCH_MASK)>>TSTMP_MOD_STATUS_MOD0_MATCH_SHIFT == 1U) + { + Tstmp_CommonProcessInterrupt(TSTMP_INSTANCE_1, TSTMP_MOD0); + /* Clear MOD0 interrupt flag */ + TSTMP_HWA_ClearMod0MatchFlag(TSTMP1); + } + if ((u32TstmpStatus & TSTMP_MOD_STATUS_MOD1_MATCH_MASK)>>TSTMP_MOD_STATUS_MOD1_MATCH_SHIFT == 1U) + { + Tstmp_CommonProcessInterrupt(TSTMP_INSTANCE_1, TSTMP_MOD1); + /* Clear MOD1 interrupt flag */ + TSTMP_HWA_ClearSingleMod123MatchFlag(TSTMP1, TSTMP_MOD1); + } + if ((u32TstmpStatus & TSTMP_MOD_STATUS_MOD2_MATCH_MASK)>>TSTMP_MOD_STATUS_MOD2_MATCH_SHIFT == 1U) + { + Tstmp_CommonProcessInterrupt(TSTMP_INSTANCE_1, TSTMP_MOD2); + /* Clear MOD2 interrupt flag */ + TSTMP_HWA_ClearSingleMod123MatchFlag(TSTMP1, TSTMP_MOD2); + } + if ((u32TstmpStatus & TSTMP_MOD_STATUS_MOD3_MATCH_MASK)>>TSTMP_MOD_STATUS_MOD3_MATCH_SHIFT == 1U) + { + Tstmp_CommonProcessInterrupt(TSTMP_INSTANCE_1, TSTMP_MOD3); + /* Clear MOD3 interrupt flag */ + TSTMP_HWA_ClearSingleMod123MatchFlag(TSTMP1, TSTMP_MOD3); + } +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_wdog.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_wdog.c new file mode 100644 index 0000000..36b04b3 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_wdog.c @@ -0,0 +1,131 @@ +/** + * @file fc7xxx_driver_wdog.c + * @author Flagchip + * @brief FC7xxx WDOG driver source code + * @version 0.1.0 + * @date 2023-12-29 + * + * @copyright Copyright (c) 2022 Flagchip Semiconductors Co., Ltd. + * + */ + +/******************************************************************************** +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2023-12-29 qxw0074 N/A First version for FC7240 +********************************************************************************/ + +#include "fc7xxx_driver_wdog.h" + +/** + * @brief UNLOCK and REFRESH CMD For MPW FC100. this may not match with FC4150 user manual + */ +#define WDOG_UNLOCK_CMD (uint32_t)(0x08181982U) +#define WDOG_REFRESH_CMD (uint32_t)(0x20CFFC20U) + +static WDOG_Type *const s_apWdogBase[WDOG_INSTANCE_COUNT] = WDOG_BASE_PTRS; + +static WDOG_IRQ_Callback aIRQCallback[WDOG_INSTANCE_MAX] = {0U}; + +void WDOG0_IRQHandler(void); +void WDOG1_IRQHandler(void); +/** + * @brief unlock the wdog before Watch dog reconfigure set. + * @param instance: WDOG module instance: WDOG0/WDOG1 defined in FC4150. + */ +void WDOG_Unlock(WDOG_InstanceType eInstance) +{ + WDOG_Type *pWdog = s_apWdogBase[eInstance]; + WDOG_HWA_SetCounter(pWdog,WDOG_UNLOCK_CMD); +} + +/** + * @brief feed the watch dog by writing typical cmd to counter. + * @param instance: WDOG module instance: WDOG0/WDOG1 defined in FC4150. + */ +void WDOG_Refresh(WDOG_InstanceType eInstance) +{ + WDOG_Type *pWdog = s_apWdogBase[eInstance]; + WDOG_HWA_SetCounter(pWdog,WDOG_REFRESH_CMD); +} + +/** + * @brief Initialize the WDOG configuration setting. * + * @param pWdogCfg: point to WDOG init module type. + */ +void WDOG_Init(WDOG_InstanceType eInstance,WDOG_CfgType* pWdogCfg) +{ + WDOG_Type *pWdog = s_apWdogBase[eInstance]; + uint32_t u32Temp = 0U; + + /* Disable the global interrupt */ + __disable_irq(); + + u32Temp = WDOG_CS_WIN(pWdogCfg->bWinEnable) | WDOG_CS_PRESCALER(pWdogCfg->bPrescalerEnable) | + WDOG_CS_CLK_SEL(pWdogCfg->eClkSource) | WDOG_CS_TST(pWdogCfg->eTesttype) | + WDOG_CS_DBG(pWdogCfg->bEnableInDebug) | WDOG_CS_UPDATE_MASK | WDOG_CS_ENABLE_MASK | + WDOG_CS_WAIT(pWdogCfg->bEnableInWait) | WDOG_CS_STOP(pWdogCfg->bEnableInStop); + if(WDOG_REACTION_NO_INT != pWdogCfg->eTimeoutReaction) + { + u32Temp |= (WDOG_CS_INT_MASK | WDOG_CS_DLY_CNT_MSB(pWdogCfg->eTimeoutReaction)); + } + else + { + //Do nothing. Keep disabling the wdog interrupt and no reset dealy. + } + + WDOG_Unlock(eInstance); + + while (WDOG_HWA_GetUnlockStatus(pWdog) == false) + { + /* 0 indicate WDOG locked. Wait until registers are unlocked */ + } + + WDOG_HWA_SetCs(pWdog,u32Temp); + + WDOG_Unlock(eInstance); + + while (WDOG_HWA_GetUnlockStatus(pWdog) == false) + { + /* 0 indicate WDOG locked. Wait until registers are unlocked */ + } + + /* configure the timeout value */ + WDOG_HWA_SetTimeout(pWdog,pWdogCfg->u16TimeoutValue); + + WDOG_Unlock(eInstance); + + while (WDOG_HWA_GetUnlockStatus(pWdog) == false) + { + /* 0 indicate WDOG locked. Wait until registers are unlocked */ + } + /* configure window value */ + WDOG_HWA_SetWindow(pWdog,pWdogCfg->u16WindowValue); + + aIRQCallback[eInstance] = pWdogCfg->pISRCallback; + + /* Enable the global interrupt */ + __enable_irq(); + + +} + +void WDOG0_IRQHandler(void) +{ + WDOG_HWA_ClearInterruptFlag(WDOG0); + if(NULL != aIRQCallback[WDOG_INSTANCE_0]) + { + (aIRQCallback[WDOG_INSTANCE_0])(); + } +} + +void WDOG1_IRQHandler(void) +{ + WDOG_HWA_ClearInterruptFlag(WDOG1); + if(NULL != aIRQCallback[WDOG_INSTANCE_1]) + { + (aIRQCallback[WDOG_INSTANCE_1])(); + } +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_wku.c b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_wku.c new file mode 100644 index 0000000..ec16de6 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/Src/fc7xxx_driver_wku.c @@ -0,0 +1,97 @@ +/** + * @file fc7xxx_driver_wku.c + * @author Flagchip + * @brief FC7xxx WKU driver type definition and API + * @version 0.1.0 + * @date 2023-02-13 + * + * @copyright Copyright (c) 2023 Flagchip Semiconductors Co., Ltd. + * + * @details + */ +/******************************************************************************** +* Revision History: +* +* Version Date Initials CR# Descriptions +* --------- ---------- ------------ ---------- --------------- +* 0.1.0 2024-01-05 Flagchip055 N/A FC7240 First version +********************************************************************************/ +#include "fc7xxx_driver_wku.h" + +/** + * @brief WKU Enable wakeup source for single input + * + * @param u32Input Number of input, WKU_WakeupInputType type is wakeup source definition + * @return WKU return type + */ +WKU_StatusType WKU_EnableWakeupSource(const uint32_t u32Input) +{ + uint32_t u32TempValue = 0U; + uint8_t u8Index = 0U; + WKU_StatusType eRet = WKU_STATUS_SUCCESS; + + DEV_ASSERT(((u32Input & ~(uint32_t)WKU_INPUT_ALL_MASK) == 0U)); + + u32TempValue = u32Input; + while (u32TempValue) + { + if (1U == (u32TempValue & ((uint32_t)1))) + { + WKU_HWA_EnableWakeupSource((WKU_WakeupInputType)((uint32_t)1 << u8Index)); + } + u32TempValue >>= 1U; + u8Index++; + } + + return eRet; +} + +/** + * @brief WKU Disable wakeup source for single input + * + * @param u32Input Number of input, WKU_WakeupInputType type is wakeup source definition + * @return WKU return type + */ +WKU_StatusType WKU_DisableWakeupSource(const uint32_t u32Input) +{ + uint32_t u32TempValue = 0U; + uint8_t u8Index = 0U; + WKU_StatusType eRet = WKU_STATUS_SUCCESS; + + DEV_ASSERT(((u32Input & ~(uint32_t)WKU_INPUT_ALL_MASK) == 0U)); + + u32TempValue = u32Input; + while (u32TempValue) + { + if (u32TempValue & ((uint32_t)1 << u8Index)) + { + WKU_HWA_DisableWakeupSource((WKU_WakeupInputType)((uint32_t)1 << u8Index)); + } + u32TempValue &= (uint32_t)~((uint32_t)1 << u8Index); + u8Index++; + } + + return eRet; +} + +/** + * @brief WKU get wakeup source + * + * @return output wakeup source + */ +uint32_t WKU_GetWakeupSources(void) +{ + return WKU_HWA_ReadWakeupSource(); +} + +/** + * @brief WKU set wake up delay time + * + * @param u8Delaytime The delay time is 2^(u8Delaytime+3) AON_CLK cycles + */ +void WKU_SetWakeupDelay(uint8_t u8Delaytime) +{ + WKU_HWA_DisableDelayCounter(); + WKU_HWA_SetDelayTime(u8Delaytime); + WKU_HWA_EnableDelayCounter(); +} diff --git a/MODULES/PeripheralDriver_Flagchip_FC7240/modular.json b/MODULES/PeripheralDriver_Flagchip_FC7240/modular.json new file mode 100644 index 0000000..701bbe8 --- /dev/null +++ b/MODULES/PeripheralDriver_Flagchip_FC7240/modular.json @@ -0,0 +1,13 @@ +{ + "dep": [ + ], + "cmake": { + "inc_dirs": [ + "Inc", + "Inc_src" + ], + "srcs": [ + "Src/**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/PwmCapture_Flagchip_FC7240/Inc/PwmCaptureFlagchip.h b/MODULES/PwmCapture_Flagchip_FC7240/Inc/PwmCaptureFlagchip.h new file mode 100644 index 0000000..bd419ed --- /dev/null +++ b/MODULES/PwmCapture_Flagchip_FC7240/Inc/PwmCaptureFlagchip.h @@ -0,0 +1,46 @@ +// +// Created by cfif on 17.11.22. +// + +#ifndef PWM_CAPTURE_FLAGCHIP_H +#define PWM_CAPTURE_FLAGCHIP_H + +#include "PwmIO.h" +#include "cmsis_os2.h" +#include "fc7xxx_driver_tpu.h" +#include "interrupt_manager.h" + +typedef struct { + uint32_t ActiveTime; + uint32_t PeriodTime; +} tPwmCaptureData; + +typedef struct { + + TPU_InterruptCfgType etpu_Int_config_tbl; + TPU_CaptureCfgType etpu_captureconfig_tbl; + + uint8_t TPU_CAPTURE_CHANNEL; + + osMessageQueueId_t q_u32PeriodActiveTime; + + uint32_t timeout; + uint8_t percent; + tPwmCaptureData data; + +} tPwmCaptureFlagchip; + + +void PWM_Capture_Initial( + tPwmCaptureFlagchip *env, + bool isDeInit, + uint8_t TPU_CAPTURE_CHANNEL, + uint8 TPU_PRIORITY, + TPU_EventCallbackType Bsp_Tpu_PwmCallback, + TPU_TCR1OverflowCallbackType Bsp_Tpu_OverflowCallBack); + +tPwmCaptureIO vPwmCaptureGetIo(tPwmCaptureFlagchip *env); + +void Get_Set_Tpu_PwmCaptureCallback(tPwmCaptureFlagchip *env); + +#endif //PWM_CAPTURE_FLAGCHIP_H diff --git a/MODULES/PwmCapture_Flagchip_FC7240/Src/PwmCaptureFlagchip.c b/MODULES/PwmCapture_Flagchip_FC7240/Src/PwmCaptureFlagchip.c new file mode 100644 index 0000000..0081fc3 --- /dev/null +++ b/MODULES/PwmCapture_Flagchip_FC7240/Src/PwmCaptureFlagchip.c @@ -0,0 +1,108 @@ +// +// Created by cfif on 07.09.22. +// +#include +#include "PwmCaptureFlagchip.h" +#include "PwmFlagchip.h" + +void Get_Set_Tpu_PwmCaptureCallback(tPwmCaptureFlagchip *env) { + + if (env->etpu_captureconfig_tbl.eMeasureMode == TPU_PeriodMeasurement) { + TPU_CaptureMeasPeriodServiceReq(env->TPU_CAPTURE_CHANNEL, &env->etpu_captureconfig_tbl); + } else { + TPU_CaptureMeasActivePeriodServiceReq(env->TPU_CAPTURE_CHANNEL, &env->etpu_captureconfig_tbl); + } + + tPwmCaptureData data; + data.ActiveTime = env->etpu_captureconfig_tbl.u32ActiveTime; + data.PeriodTime = env->etpu_captureconfig_tbl.u32PeriodTime; + + osMessageQueuePut(env->q_u32PeriodActiveTime, &data, 0, 0); +} + +void PWM_Capture_Initial( + tPwmCaptureFlagchip *env, + bool isDeInit, + uint8_t TPU_CAPTURE_CHANNEL, + uint8 TPU_PRIORITY, + TPU_EventCallbackType Bsp_Tpu_PwmCallback, + TPU_TCR1OverflowCallbackType Bsp_Tpu_OverflowCallBack) { + + env->q_u32PeriodActiveTime = osMessageQueueNew(1, sizeof(tPwmCaptureData), NULL); + + env->etpu_captureconfig_tbl.u32PeriodTime = 0u; + env->etpu_captureconfig_tbl.eMeasureMode = TPU_DutyMeasurementActiveHigh; + env->etpu_captureconfig_tbl.eInputType = TPUE_DETECT_FALLING_EDGE_ONLY; + env->etpu_captureconfig_tbl.u32SampleTime = PERIOD_TICKS * 4;//80000; // Ensure sample time > period + env->etpu_captureconfig_tbl.u32ActiveTime = 0; + env->etpu_captureconfig_tbl.LastTime = 0; + env->etpu_captureconfig_tbl.StartTime = 0; + + env->etpu_Int_config_tbl.bEventIntEn = (bool) true; + env->etpu_Int_config_tbl.bTCR1OverFlowEventIntEn = (bool) true; + env->etpu_Int_config_tbl.bTCR2OverFlowEventIntEn = (bool) false; + env->etpu_Int_config_tbl.pEventNotify = Bsp_Tpu_PwmCallback; + env->etpu_Int_config_tbl.pHSANotify = NULL; + env->etpu_Int_config_tbl.pTCR1OverflowNotify = Bsp_Tpu_OverflowCallBack; + env->etpu_Int_config_tbl.pTCR2OverflowNotify = NULL; + env->etpu_Int_config_tbl.eChTrigType = TPUH_TDL1_OR_TDL2_EVENT_NOT_GATED_BY_TSR; + + env->TPU_CAPTURE_CHANNEL = TPU_CAPTURE_CHANNEL; + + if (isDeInit) { + TPU_DeInit(); + } + TPU_Init(); + TPU_CaptureModeInit(TPU_CAPTURE_CHANNEL, &env->etpu_captureconfig_tbl); + TPU_InitChannelInterrupt(TPU_CAPTURE_CHANNEL, &env->etpu_Int_config_tbl); + + if (TPU_CAPTURE_CHANNEL <= 7) { + NVIC_SetPriority(TPU0_CH0_7_IRQn, TPU_PRIORITY); + NVIC_EnableIRQ(TPU0_CH0_7_IRQn); + } else if (TPU_CAPTURE_CHANNEL <= 15) { + NVIC_SetPriority(TPU0_CH8_15_IRQn, TPU_PRIORITY); + NVIC_EnableIRQ(TPU0_CH8_15_IRQn); + } else if (TPU_CAPTURE_CHANNEL <= 23) { + NVIC_SetPriority(TPU0_CH16_23_IRQn, TPU_PRIORITY); + NVIC_EnableIRQ(TPU0_CH16_23_IRQn); + } else if (TPU_CAPTURE_CHANNEL <= 31) { + NVIC_SetPriority(TPU0_CH24_31_IRQn, TPU_PRIORITY); + NVIC_EnableIRQ(TPU0_CH24_31_IRQn); + } + +} + +static uint8_t vGetPwm(tPwmCaptureFlagchip *env) { + + osStatus_t cPeriodActiveTime = osMessageQueueGet(env->q_u32PeriodActiveTime, &env->data, 0, 0); + + if (cPeriodActiveTime == osOK) { + env->timeout = SystemGetMs() + 1000; + + env->percent = env->data.ActiveTime * 100 / env->data.PeriodTime; + + // Инверсия для отображения + env->percent = 100 - env->percent; + } else { + if (env->timeout < SystemGetMs()) { + env->percent = 0; + } + } + + // PWM - Отключен + if (env->percent == 100) { + env->percent = 0; + } + + return env->percent; +} + +tPwmCaptureIO vPwmCaptureGetIo(tPwmCaptureFlagchip *env) { + + tPwmCaptureIO io = { + .env = env, + .getPwm = (PwmIOCaptureTransaction) vGetPwm, + }; + + return io; +} diff --git a/MODULES/PwmCapture_Flagchip_FC7240/modular.json b/MODULES/PwmCapture_Flagchip_FC7240/modular.json new file mode 100644 index 0000000..71971cd --- /dev/null +++ b/MODULES/PwmCapture_Flagchip_FC7240/modular.json @@ -0,0 +1,10 @@ +{ + "cmake": { + "inc_dirs": [ + "Inc" + ], + "srcs": [ + "Src/**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/PwmInterface/Inc/PwmIO.h b/MODULES/PwmInterface/Inc/PwmIO.h new file mode 100644 index 0000000..5ab6d3e --- /dev/null +++ b/MODULES/PwmInterface/Inc/PwmIO.h @@ -0,0 +1,26 @@ +// +// Created by cfif on 17.11.22. +// + +#ifndef MODULE_PWMIO_H +#define MODULE_PWMIO_H + +#include "stdint.h" + +typedef void (*PwmIOTransaction )(void *env); +typedef void (*PwmIOTransactionSetActivePercent )(void *env, uint8_t percent); + +typedef struct { + void *env; + PwmIOTransaction run; + PwmIOTransactionSetActivePercent setActivePercent; +} tPwmIO; + +typedef uint8_t (*PwmIOCaptureTransaction )(void *env); + +typedef struct { + void *env; + PwmIOCaptureTransaction getPwm; +} tPwmCaptureIO; + +#endif //MODULE_PWMIO_H diff --git a/MODULES/PwmInterface/modular.json b/MODULES/PwmInterface/modular.json new file mode 100644 index 0000000..9bdd478 --- /dev/null +++ b/MODULES/PwmInterface/modular.json @@ -0,0 +1,7 @@ +{ + "cmake": { + "inc_dirs": [ + "Inc" + ] + } +} \ No newline at end of file diff --git a/MODULES/Pwm_Flagchip_FC7240/Inc/PwmFlagchip.h b/MODULES/Pwm_Flagchip_FC7240/Inc/PwmFlagchip.h new file mode 100644 index 0000000..9c6aaac --- /dev/null +++ b/MODULES/Pwm_Flagchip_FC7240/Inc/PwmFlagchip.h @@ -0,0 +1,54 @@ +// +// Created by cfif on 17.11.22. +// + +#ifndef PWM_FLAGCHIP_H +#define PWM_FLAGCHIP_H + +#include "PwmIO.h" +#include "cmsis_os2.h" +#include "fc7xxx_driver_tpu.h" +#include "interrupt_manager.h" + +typedef struct { + + TPU_InterruptCfgType etpu_Int_config_tbl; + TPU_PwmCfgType etpu_pwmconfig_tbl; + + volatile uint32_t pendingActiveTime; + volatile bool updatePending; + + uint8_t TPU_PWM_CHANNEL; + + + +} tPwmFlagchip; + + +void PWM_Initial( + tPwmFlagchip *env, + bool isDeInit, + uint32_t PeriodTime, + uint32_t ActiveTime, + uint8_t TPU_PWM_CHANNEL, + uint8 TPU_PRIORITY, + TPU_EventCallbackType Bsp_Tpu_PwmCallback, + TPU_TCR1OverflowCallbackType Bsp_Tpu_OverflowCallBack); + +tPwmIO vPwmGetIo(tPwmFlagchip *env); + +void Get_Set_Tpu_PwmCallback(tPwmFlagchip *env); + +// Частота шины +#define BUS_CLK 120000000U + +// Делитель выходной частоты +#define SCG_CLK_DIV 4U + +#define TPU_FREQ (BUS_CLK / SCG_CLK_DIV) + +#define PWM_FREQ 50 // Реальная частота на выходе = 50 Гц (из-за /2 в TPU) + +#define PERIOD_TICKS (TPU_FREQ / PWM_FREQ) + +#endif //PWM_FLAGCHIP_H diff --git a/MODULES/Pwm_Flagchip_FC7240/Src/PwmFlagchip.c b/MODULES/Pwm_Flagchip_FC7240/Src/PwmFlagchip.c new file mode 100644 index 0000000..0d445e6 --- /dev/null +++ b/MODULES/Pwm_Flagchip_FC7240/Src/PwmFlagchip.c @@ -0,0 +1,158 @@ +// +// Created by cfif on 07.09.22. +// +#include "PwmFlagchip.h" + +void Get_Set_Tpu_PwmCallback(tPwmFlagchip *env) { + + // Обновляем только если есть запрос и канал не отключен + if (env->updatePending) { + env->etpu_pwmconfig_tbl.u32ActiveTime = env->pendingActiveTime; + env->updatePending = false; + } + + TPU_PwmServiceReq(env->TPU_PWM_CHANNEL, env->etpu_pwmconfig_tbl.u32ActiveTime, + env->etpu_pwmconfig_tbl.u32PeriodTime); +} + + +// Функция для полной остановки ШИМ на канале +static void TPU_StopChannel(uint8_t channel) { + TPU_E_Type *const pTPUE = TPU_E_BASE_PTRS; + // Отключаем выход буфера канала + TPU_E_HWA_EnableChOutputBuf(pTPUE, channel, (bool) false); + // Опционально: устанавливаем выход в безопасное состояние + // (нужно определить, какое состояние безопасно для вашей системы) +} + +// Функция для запуска конкретного канала +static void TPU_StartChannelSpecific(uint8_t channel) { + TPU_E_Type *const pTPUE = TPU_E_BASE_PTRS; + // Включаем выход буфера канала + TPU_E_HWA_EnableChOutputBuf(pTPUE, channel, (bool) true); +} + + +void PWM_Initial( + tPwmFlagchip *env, + bool isDeInit, + uint32_t PeriodTime, + uint32_t ActiveTime, + uint8_t TPU_PWM_CHANNEL, + uint8 TPU_PRIORITY, + TPU_EventCallbackType Bsp_Tpu_PwmCallback, + TPU_TCR1OverflowCallbackType Bsp_Tpu_OverflowCallBack) { + + env->etpu_pwmconfig_tbl.eTBS1 = TPUE_EQUAL_ONLY_CAPBASE_TCR1_MATCHBASE_TCR1; + env->etpu_pwmconfig_tbl.eTBS2 = TPUE_EQUAL_ONLY_CAPBASE_TCR1_MATCHBASE_TCR1; + env->etpu_pwmconfig_tbl.bPwmUseTCR1 = (bool) true; + env->etpu_pwmconfig_tbl.bPwmUseTCR2 = (bool) false; + env->etpu_pwmconfig_tbl.u32ActiveTime = ActiveTime; + env->etpu_pwmconfig_tbl.u32PeriodTime = PeriodTime; + env->etpu_pwmconfig_tbl.bActiveHigh = (bool) false; + + + env->etpu_Int_config_tbl.bEventIntEn = (bool) true; + env->etpu_Int_config_tbl.bTCR1OverFlowEventIntEn = (bool) true; + env->etpu_Int_config_tbl.bTCR2OverFlowEventIntEn = (bool) false; + env->etpu_Int_config_tbl.pEventNotify = Bsp_Tpu_PwmCallback; + env->etpu_Int_config_tbl.pHSANotify = NULL; + env->etpu_Int_config_tbl.pTCR1OverflowNotify = Bsp_Tpu_OverflowCallBack; + env->etpu_Int_config_tbl.pTCR2OverflowNotify = NULL; + env->etpu_Int_config_tbl.eChTrigType = TPUH_ANY_EVENT_GATED_BY_MSRTSR; + + env->TPU_PWM_CHANNEL = TPU_PWM_CHANNEL; + env->updatePending = false; + env->pendingActiveTime = 0; + + if (isDeInit) { + TPU_DeInit(); + } + TPU_Init(); + TPU_PwmModeInit(TPU_PWM_CHANNEL, &env->etpu_pwmconfig_tbl); + TPU_InitChannelInterrupt(TPU_PWM_CHANNEL, &env->etpu_Int_config_tbl); + + TPU_StopChannel(env->TPU_PWM_CHANNEL); + + if (TPU_PWM_CHANNEL <= 7) { + NVIC_SetPriority(TPU0_CH0_7_IRQn, TPU_PRIORITY); + NVIC_EnableIRQ(TPU0_CH0_7_IRQn); + } else if (TPU_PWM_CHANNEL <= 15) { + NVIC_SetPriority(TPU0_CH8_15_IRQn, TPU_PRIORITY); + NVIC_EnableIRQ(TPU0_CH8_15_IRQn); + } else if (TPU_PWM_CHANNEL <= 23) { + NVIC_SetPriority(TPU0_CH16_23_IRQn, TPU_PRIORITY); + NVIC_EnableIRQ(TPU0_CH16_23_IRQn); + } else if (TPU_PWM_CHANNEL <= 31) { + NVIC_SetPriority(TPU0_CH24_31_IRQn, TPU_PRIORITY); + NVIC_EnableIRQ(TPU0_CH24_31_IRQn); + } + +} + +static void vPwmAllRun(tPwmFlagchip *env) { + TPU_StartChannel(); +} + +static void setActivePercent(tPwmFlagchip *env, uint8_t percent) { + uint8_t final_percent; + + // Обработка отключения (0%) + if (percent == 0) { + // Отключаем канал ШИМ + TPU_StopChannel(env->TPU_PWM_CHANNEL); + return; + } + + // Для всех ненулевых значений (1-100) + // Принудительно ограничиваем до 95% максимум + if (percent > 95) { + percent = 95; + } + + // Минимальное значение - 1% (не ниже) + if (percent < 1) { + percent = 1; // Минимальный рабочий процент + } + + TPU_StartChannel(); + + // Если был отключен, включаем заново + TPU_StartChannelSpecific(env->TPU_PWM_CHANNEL); + + // Для active LOW (bActiveHigh = false) нужна инверсия + // 10% → 90%, 20% → 80% и т.д. + if (env->etpu_pwmconfig_tbl.bActiveHigh == false) { + final_percent = 100 - percent; + } else { + final_percent = percent; + } + + // Расчет времени активности в тактах + uint32_t activeTime = env->etpu_pwmconfig_tbl.u32PeriodTime * final_percent / 100; + + + // Защита от выхода за пределы + if (activeTime == 0) { + activeTime = 1; // Минимальное значение, чтобы не остановить счетчик + } + if (activeTime >= env->etpu_pwmconfig_tbl.u32PeriodTime) { + activeTime = env->etpu_pwmconfig_tbl.u32PeriodTime - 1; + } + + + // Не обновляем напрямую, а ставим флаг + env->pendingActiveTime = activeTime; + env->updatePending = true; + +} + + +tPwmIO vPwmGetIo(tPwmFlagchip *env) { + tPwmIO io = { + .env = env, + .run = (PwmIOTransaction) vPwmAllRun, + .setActivePercent = (PwmIOTransactionSetActivePercent) setActivePercent + }; + return io; +} \ No newline at end of file diff --git a/MODULES/Pwm_Flagchip_FC7240/modular.json b/MODULES/Pwm_Flagchip_FC7240/modular.json new file mode 100644 index 0000000..71971cd --- /dev/null +++ b/MODULES/Pwm_Flagchip_FC7240/modular.json @@ -0,0 +1,10 @@ +{ + "cmake": { + "inc_dirs": [ + "Inc" + ], + "srcs": [ + "Src/**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/Rtc/Inc/Rtc.h b/MODULES/Rtc/Inc/Rtc.h new file mode 100644 index 0000000..10b33cb --- /dev/null +++ b/MODULES/Rtc/Inc/Rtc.h @@ -0,0 +1,16 @@ +// +// Created by cfif on 11.09.22. +// + +#ifndef RTC_H +#define RTC_H + +#include "RtcIO.h" +#include + +uint16_t RtcGet(tRtcIO *io, time_t *timestamp); +uint16_t RtcSet(tRtcIO *io, time_t *timestamp); +uint16_t RtcGetTM(tRtcIO *io, struct tm *timestampTM); +uint16_t RtcSetTM(tRtcIO *io, struct tm *timestampTM); + +#endif //RTC_H diff --git a/MODULES/Rtc/Src/Rtc.c b/MODULES/Rtc/Src/Rtc.c new file mode 100644 index 0000000..1a9fa0c --- /dev/null +++ b/MODULES/Rtc/Src/Rtc.c @@ -0,0 +1,22 @@ +// +// Created by cfif on 17.11.22. +// + +#include "Rtc.h" +#include "SystemDelayInterface.h" + +uint16_t RtcSet(tRtcIO *io, time_t *timestamp) { + return io->set(io->env, timestamp); +} + +uint16_t RtcGet(tRtcIO *io, time_t *timestamp) { + return io->get(io->env, timestamp); +} + +uint16_t RtcSetTM(tRtcIO *io, struct tm *timestampTM) { + return io->setTM(io->env, timestampTM); +} + +uint16_t RtcGetTM(tRtcIO *io, struct tm *timestampTM) { + return io->getTM(io->env, timestampTM); +} \ No newline at end of file diff --git a/MODULES/Rtc/modular.json b/MODULES/Rtc/modular.json new file mode 100644 index 0000000..676aaf1 --- /dev/null +++ b/MODULES/Rtc/modular.json @@ -0,0 +1,17 @@ +{ + "dep": [ + { + "type": "local", + + "dir": "./MODULES/RtcInterface" + } + ], + "cmake": { + "inc_dirs": [ + "Inc" + ], + "srcs": [ + "Src/**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/RtcInterface/Inc/RtcIO.h b/MODULES/RtcInterface/Inc/RtcIO.h new file mode 100644 index 0000000..00e0340 --- /dev/null +++ b/MODULES/RtcInterface/Inc/RtcIO.h @@ -0,0 +1,22 @@ +// +// Created by cfif on 17.11.22. +// + +#ifndef MODULE_RTCIO_H +#define MODULE_RTCIO_H +#include "stdint.h" +#include + +typedef uint16_t (*RtcIOTransaction )(void *env, time_t *timestamp); +typedef uint16_t (*RtcIOTransactionTM )(void *env, struct tm *timestampTM); + +typedef struct { + void *env; + RtcIOTransaction set; + RtcIOTransaction get; + RtcIOTransactionTM setTM; + RtcIOTransactionTM getTM; +} tRtcIO; + + +#endif //MODULE_RTCIO_H diff --git a/MODULES/RtcInterface/modular.json b/MODULES/RtcInterface/modular.json new file mode 100644 index 0000000..9bdd478 --- /dev/null +++ b/MODULES/RtcInterface/modular.json @@ -0,0 +1,7 @@ +{ + "cmake": { + "inc_dirs": [ + "Inc" + ] + } +} \ No newline at end of file diff --git a/MODULES/Rtc_Flagchip_FC7240/Inc/RtcFC7240.h b/MODULES/Rtc_Flagchip_FC7240/Inc/RtcFC7240.h new file mode 100644 index 0000000..d4a5c22 --- /dev/null +++ b/MODULES/Rtc_Flagchip_FC7240/Inc/RtcFC7240.h @@ -0,0 +1,29 @@ +// +// Created by cfif on 17.11.22. +// + +#ifndef RTC_FLAGCHIP_H +#define RTC_FLAGCHIP_H + +#include "Rtc.h" +#include "cmsis_os2.h" + +typedef struct { + +#ifdef ACCESS_RTC + osMutexId_t access; +#endif + +} tRtcFlagchip; + +void RtcFlagchip_Init(tRtcFlagchip *env); + +tRtcIO RtcFlagchip_GetIo(tRtcFlagchip *env); + +///deprecated +tRtcFlagchip vRtcInit(); + +///deprecated +#define vRtcGetIo RtcFlagchip_GetIo + +#endif //RTC_FLAGCHIP_H diff --git a/MODULES/Rtc_Flagchip_FC7240/Src/RtcFC7240.c b/MODULES/Rtc_Flagchip_FC7240/Src/RtcFC7240.c new file mode 100644 index 0000000..652c049 --- /dev/null +++ b/MODULES/Rtc_Flagchip_FC7240/Src/RtcFC7240.c @@ -0,0 +1,448 @@ +// +// Created by cfif on 17.11.22. +// +#include "RtcFC7240.h" +#include +#include +#include +#include "fc7xxx_driver_csc.h" +#include "fc7xxx_driver_scg.h" +#include "fc7xxx_driver_rtc.h" + +#define SECONDS_DAY 86400UL +#define SECONDS_HOUR 3600UL +#define SECONDS_MINUTE 60UL +#define MINUTES_HOUR 60UL +#define HOURS_DAY 24UL +#define DAYS_LEAP_YEAR 366UL +#define DAYS_COM_YEAR 365UL +#define START_YEAR 1970UL +#define END_YEAR 2099UL + +typedef struct +{ + uint16_t u16Year; /**< Year */ + uint8_t u8Month; /**< Month */ + uint8_t u8Day; /**< Day */ + uint8_t u8Hour; /**< Hour */ + uint8_t u8Minute; /**< Minute */ + uint8_t u8Second; /**< Second */ +} RTC_TimeDate; + +/* Table of month length (in days) for the Common-year*/ +static const uint8_t ComYear[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; + +/* Table of month length (in days) for the Leap-year*/ +static const uint8_t LeapYear[] = {0U, 31U, 29U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; + + +static bool RTC_IsLeapYear(uint16_t u16Year) +{ + bool bYearLeap = false; + + if ((u16Year % 4U) > 0U) + { + bYearLeap = false; + } + else if ((u16Year % 100U) > 0U) + { + bYearLeap = true; + } + else if ((u16Year % 400U) > 0U) + { + bYearLeap = false; + } + else + { + bYearLeap = true; + } + + /* Return the exit code */ + return bYearLeap; +} + +static bool RTC_CheckTimeDate(const RTC_TimeDate * const pTimeDate) +{ + bool bCheckReturn = true; + const uint8_t * pMonth; + pMonth = RTC_IsLeapYear(pTimeDate->u16Year) ? LeapYear : ComYear; + + if (pTimeDate->u16Year < START_YEAR || pTimeDate->u16Year > END_YEAR + || pTimeDate->u8Month < 1U || pTimeDate->u8Month > 12U + || pTimeDate->u8Day < 1U || pTimeDate->u8Day > pMonth[pTimeDate->u8Month] + || pTimeDate->u8Hour >= 24 + || pTimeDate->u8Minute >= 60 + || pTimeDate->u8Second >= 60) + { + bCheckReturn = false; + } + return bCheckReturn; +} +/* +static void RTC_TimeDate_To_Second(RTC_TimeDate * const pTimeDate, uint32_t u32Second) +{ + uint32_t u32CountDays; + uint32_t u32TempCount; + uint32_t u32TempDays; + + u32CountDays = u32Second / SECONDS_DAY; + u32TempCount = u32Second % SECONDS_DAY; + + pTimeDate->u8Hour = (uint8_t)(u32TempCount / SECONDS_HOUR); + u32TempCount = u32TempCount % SECONDS_HOUR; + + pTimeDate->u8Minute = (uint8_t)(u32TempCount / SECONDS_MINUTE); + pTimeDate->u8Second = (uint8_t)(u32TempCount % SECONDS_MINUTE); + + pTimeDate->u16Year = (uint16_t)START_YEAR; + + u32TempDays = DAYS_COM_YEAR; + while (u32CountDays >= u32TempDays) + { + pTimeDate->u16Year++; + u32CountDays -= u32TempDays; + u32TempDays = (RTC_IsLeapYear(pTimeDate->u16Year)) ? DAYS_LEAP_YEAR : DAYS_COM_YEAR; + } + + u32TempDays += 1; + + for (uint8_t u8TempMonth = 1; u8TempMonth <= 12; u8TempMonth++) + { + u32TempCount = (RTC_IsLeapYear(pTimeDate->u16Year)) ? (uint32_t)LeapYear[u8TempMonth] : (uint32_t)ComYear[u8TempMonth]; + if (u32TempDays <= u32TempCount) + { + pTimeDate->u8Month = (uint8_t)u8TempMonth; + pTimeDate->u8Day = (uint8_t)u32TempDays; + break; + } + else + { + u32TempDays -= u32TempCount; + } + } +} + + +static uint32_t RTC_Second_To_TimeDate(const RTC_TimeDate * const pTimeDate) +{ + uint32_t u32Second; + + uint32_t u32TempDay; + + u32Second = (pTimeDate->u16Year - START_YEAR) * SECONDS_DAY * DAYS_COM_YEAR; + + for (uint32_t u32TempYear = START_YEAR; u32TempYear < pTimeDate->u16Year; u32TempYear++) + { + if (RTC_IsLeapYear((uint16_t)u32TempYear)) + { + u32Second += SECONDS_DAY; + } + } + + for (uint8_t u8TempMonth = 1; u8TempMonth < pTimeDate->u8Month; u8TempMonth++) + { + u32TempDay = (RTC_IsLeapYear(pTimeDate->u16Year)) ? (uint32_t)LeapYear[u8TempMonth] : (uint32_t)ComYear[u8TempMonth]; + u32Second += (u32TempDay * SECONDS_DAY); + } + + u32Second += ((uint32_t)((pTimeDate->u8Day - 1U) * SECONDS_DAY) + \ + pTimeDate->u8Hour * SECONDS_HOUR + \ + pTimeDate->u8Minute * SECONDS_MINUTE + \ + pTimeDate->u8Second); + + return u32Second; +} + */ +static void RTC_TimeDate_To_Second(RTC_TimeDate * const pTimeDate, uint32_t u32Second) +{ + uint32_t u32CountDays; + uint32_t u32TempCount; + + u32CountDays = u32Second / SECONDS_DAY; + u32TempCount = u32Second % SECONDS_DAY; + + pTimeDate->u8Hour = (uint8_t)(u32TempCount / SECONDS_HOUR); + u32TempCount = u32TempCount % SECONDS_HOUR; + + pTimeDate->u8Minute = (uint8_t)(u32TempCount / SECONDS_MINUTE); + pTimeDate->u8Second = (uint8_t)(u32TempCount % SECONDS_MINUTE); + + pTimeDate->u16Year = (uint16_t)START_YEAR; + + // Вычисляем год + uint32_t u32DaysInYear = DAYS_COM_YEAR; + while (u32CountDays >= u32DaysInYear) + { + pTimeDate->u16Year++; + u32CountDays -= u32DaysInYear; + u32DaysInYear = RTC_IsLeapYear(pTimeDate->u16Year) ? DAYS_LEAP_YEAR : DAYS_COM_YEAR; + } + + // u32CountDays теперь содержит день года (0-364/365) + // Преобразуем в месяц и день + const uint8_t* pMonthDays = RTC_IsLeapYear(pTimeDate->u16Year) ? LeapYear : ComYear; + uint32_t u32DayOfYear = u32CountDays + 1; // День года (1-366) + + for (uint8_t u8TempMonth = 1; u8TempMonth <= 12; u8TempMonth++) + { + uint32_t u32DaysInMonth = pMonthDays[u8TempMonth]; + if (u32DayOfYear <= u32DaysInMonth) + { + pTimeDate->u8Month = u8TempMonth; + pTimeDate->u8Day = (uint8_t)u32DayOfYear; + break; + } + else + { + u32DayOfYear -= u32DaysInMonth; + } + } +} + +static uint32_t RTC_Second_To_TimeDate(const RTC_TimeDate * const pTimeDate) +{ + uint32_t u32Second = 0; + + // Считаем дни за полные годы с 1970 + for (uint16_t u16Year = START_YEAR; u16Year < pTimeDate->u16Year; u16Year++) + { + u32Second += RTC_IsLeapYear(u16Year) ? DAYS_LEAP_YEAR * SECONDS_DAY : DAYS_COM_YEAR * SECONDS_DAY; + } + + // Считаем дни за полные месяцы в текущем году + const uint8_t* pMonthDays = RTC_IsLeapYear(pTimeDate->u16Year) ? LeapYear : ComYear; + for (uint8_t u8Month = 1; u8Month < pTimeDate->u8Month; u8Month++) + { + u32Second += pMonthDays[u8Month] * SECONDS_DAY; + } + + // Считаем дни, часы, минуты, секунды + u32Second += ((uint32_t)(pTimeDate->u8Day - 1) * SECONDS_DAY) + + ((uint32_t)pTimeDate->u8Hour * SECONDS_HOUR) + + ((uint32_t)pTimeDate->u8Minute * SECONDS_MINUTE) + + ((uint32_t)pTimeDate->u8Second); + + return u32Second; +} + +/** + * @brief Set time and date + * + * @param pRtcHandle the RTC instance + * @param pTimeDate the structure of time and date + */ +static void RTC_SetTimeDate(const RTC_TimeDate *const pTimeDate) { + uint32_t u32Second; + + if (true == RTC_CheckTimeDate(pTimeDate)) { + u32Second = RTC_Second_To_TimeDate(pTimeDate); + RTC_SetSecondCounterValue(u32Second); + } +} + +/** + * @brief Get time and date + * + * @param pRtcHandle the RTC instance + * @param pTimeDate the structure of time and date + */ +void RTC_GetTimeDate(RTC_TimeDate * const pTimeDate) +{ + uint32_t u32Second; + + u32Second = RTC_GetTime(); + RTC_TimeDate_To_Second(pTimeDate, u32Second); +} + +tRtcFlagchip vRtcInit() { + tRtcFlagchip rtcFlagchip; + RtcFlagchip_Init(&rtcFlagchip); + return rtcFlagchip; +} + +void RtcFlagchip_Init(tRtcFlagchip *env) { + + // enable SIRC32K clock source + SCG_Sirc32kType tSIRC32KStruct = + { + .bLock = true + }; + SCG_EnableSIRC32K(&tSIRC32KStruct); + // set RTC clock source is SIRC32K clock + CSC0_AONCLKSRType tAONCLKStruct; + tAONCLKStruct.eRtcSel = CSC0_RTC_SIRC32K_CLK; + tAONCLKStruct.eAon32KSel = CSC0_AON32K_SIRCDIV_32K_CLK; + tAONCLKStruct.eAonSel = CSC0_AON_SIRCDIV_128K_CLK; + CSC0_SetAonClkSrc(&tAONCLKStruct, true); + + + RTC_InitType tInitStruct = {0}; + tInitStruct.eSecIntAndClkoutFreq = RTC_FREQ_1HZ; // set interrupt frequency to 1HZ + RTC_Init(&tInitStruct); + + RTC_Start(); + +#ifdef ACCESS_RTC + + *env = (tRtcFlagchip) { + .access = osMutexNew(NULL) + }; + +#else + *env = (tRtcFlagchip) { + + }; +#endif + + +} + +static uint16_t vRtcSet(tRtcFlagchip *env, time_t *timestamp) { + struct tm dateTime; + + RTC_TimeDate tTimeDate; + + localtime_r(timestamp, &dateTime); + + tTimeDate.u16Year = dateTime.tm_year + 1900; + tTimeDate.u8Month = dateTime.tm_mon + 1; + tTimeDate.u8Day = dateTime.tm_mday; + tTimeDate.u8Hour = dateTime.tm_hour; + tTimeDate.u8Minute = dateTime.tm_min; + tTimeDate.u8Second = dateTime.tm_sec; + +#ifdef ACCESS_RTC + if (osMutexAcquire(env->access, 1000) == osOK) { + + RTC_SetTimeDate(&tTimeDate); + + osMutexRelease(env->access); + } else { + RTC_SetTimeDate(&tTimeDate); + } +#else + RTC_SetTimeDate(&tTimeDate); +#endif + + + return 0; +} + +static uint16_t vRtcSetTM(tRtcFlagchip *env, struct tm *timestampTM) { + + RTC_TimeDate tTimeDate; + + tTimeDate.u16Year = timestampTM->tm_year + 1900; + tTimeDate.u8Month = timestampTM->tm_mon + 1; + tTimeDate.u8Day = timestampTM->tm_mday; + tTimeDate.u8Hour = timestampTM->tm_hour; + tTimeDate.u8Minute = timestampTM->tm_min; + tTimeDate.u8Second = timestampTM->tm_sec; + +#ifdef ACCESS_RTC + if (osMutexAcquire(env->access, 1000) == osOK) { + + RTC_SetTimeDate(&tTimeDate); + + osMutexRelease(env->access); + } else { + RTC_SetTimeDate(&tTimeDate); + } +#else + RTC_SetTimeDate(&tTimeDate); +#endif + + return 0; +} + +static void v_RtcGet(time_t *timestamp) { + + RTC_TimeDate tTimeDate; + + RTC_GetTimeDate(&tTimeDate); + + struct tm dateTime; + + memset(&dateTime, 0, sizeof(dateTime)); + + dateTime.tm_year = tTimeDate.u16Year - 1900; + dateTime.tm_mon = tTimeDate.u8Month - 1; + dateTime.tm_mday = tTimeDate.u8Day; + dateTime.tm_hour = tTimeDate.u8Hour; + dateTime.tm_min = tTimeDate.u8Minute; + dateTime.tm_sec = tTimeDate.u8Second; + + *timestamp = mktime(&dateTime); + *timestamp &= 0xFFFFFFFF; + +} + +static uint16_t vRtcGet(tRtcFlagchip *env, time_t *timestamp) { + + +#ifdef ACCESS_RTC + if (osMutexAcquire(env->access, 1000) == osOK) { + memset(timestamp, 0, sizeof(time_t)); + v_RtcGet(timestamp); + osMutexRelease(env->access); + } else { + v_RtcGet(timestamp); + } +#else + + v_RtcGet(timestamp); + +#endif + + + return 0; +} + +static void v_RtcGetTM(struct tm *timestampTM) { + + RTC_TimeDate tTimeDate; + + RTC_GetTimeDate(&tTimeDate); + + + memset(timestampTM, 0, sizeof(struct tm)); + + timestampTM->tm_year = tTimeDate.u16Year - 1900; + timestampTM->tm_mon = tTimeDate.u8Month - 1; + timestampTM->tm_mday = tTimeDate.u8Day; + timestampTM->tm_hour = tTimeDate.u8Hour; + timestampTM->tm_min = tTimeDate.u8Minute; + timestampTM->tm_sec = tTimeDate.u8Second; + +} + +static uint16_t vRtcGetTM(tRtcFlagchip *env, struct tm *timestampTM) { + +#ifdef ACCESS_RTC + if (osMutexAcquire(env->access, 1000) == osOK) { + + v_RtcGetTM(timestampTM); + + osMutexRelease(env->access); + } else { + v_RtcGetTM(timestampTM); + } +#else + + v_RtcGetTM(timestampTM); + +#endif + + return 0; +} + +tRtcIO RtcFlagchip_GetIo(tRtcFlagchip *env) { + tRtcIO io = { + .env = env, + .get = (RtcIOTransaction) vRtcGet, + .set = (RtcIOTransaction) vRtcSet, + .getTM = (RtcIOTransactionTM) vRtcGetTM, + .setTM = (RtcIOTransactionTM) vRtcSetTM + }; + return io; +} \ No newline at end of file diff --git a/MODULES/Rtc_Flagchip_FC7240/modular.json b/MODULES/Rtc_Flagchip_FC7240/modular.json new file mode 100644 index 0000000..a2a8c5d --- /dev/null +++ b/MODULES/Rtc_Flagchip_FC7240/modular.json @@ -0,0 +1,17 @@ +{ + "dep": [ + { + "type": "local", + + "dir": "./MODULES/Rtc" + } + ], + "cmake": { + "inc_dirs": [ + "Inc" + ], + "srcs": [ + "Src/**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/SerialPort/Inc/SerialPort.h b/MODULES/SerialPort/Inc/SerialPort.h new file mode 100644 index 0000000..5248d4c --- /dev/null +++ b/MODULES/SerialPort/Inc/SerialPort.h @@ -0,0 +1,18 @@ +// +// Created by CFIF on 01.09.22. +// + +#ifndef SERIALPORT_SERIALPORT_H +#define SERIALPORT_SERIALPORT_H + +#include "SerialPortIO.h" + +uint16_t SerialPortReceive(tSerialPortIO *io, uint8_t *data, uint16_t size, uint32_t timeout); + +uint16_t SerialPortReceiveTo(tSerialPortIO *io, uint8_t *data, uint16_t size, uint8_t symbol, uint32_t timeout); + +uint16_t SerialPortTransmit(tSerialPortIO *io, uint8_t *data, uint16_t size, uint32_t timeout); + +void SerialPortClearRxBuffer(tSerialPortIO *io); + +#endif //SERIALPORT_SERIALPORT_H diff --git a/MODULES/SerialPort/Src/SerialPort.c b/MODULES/SerialPort/Src/SerialPort.c new file mode 100644 index 0000000..8dd7c07 --- /dev/null +++ b/MODULES/SerialPort/Src/SerialPort.c @@ -0,0 +1,43 @@ +// +// Created by CFIF on 01.09.22. +// + +#include "SerialPort.h" +#include "SystemDelayInterface.h" + +uint16_t SerialPortReceive(tSerialPortIO *io, uint8_t *data, uint16_t size, uint32_t timeout) { + return io->receive(io->env, data, size, timeout); +} + +void SerialPortClearRxBuffer(tSerialPortIO *io) { + uint8_t byte; + uint32_t antiSpamTimeout = SystemGetMs() + 10; + while ((antiSpamTimeout > SystemGetMs()) && io->receive(io->env, &byte, 1, 0)); +} + +uint16_t SerialPortReceiveTo(tSerialPortIO *io, uint8_t *data, uint16_t size, uint8_t symbol, uint32_t timeout) { + + uint8_t dataToSymbol; + int i = 0; + + uint32_t endMs = SystemGetMs() + timeout; + uint32_t leftMs; + + while (size && ((timeout == SystemWaitForever) || (endMs > SystemGetMs()))) { + + leftMs = (timeout == SystemWaitForever) ? SystemWaitForever : endMs - SystemGetMs(); + if (SerialPortReceive(io, &dataToSymbol, 1, leftMs)) { + size--; + data[i] = dataToSymbol; + i++; + if (dataToSymbol == symbol) { + break; + } + } + } + return i; +} + +uint16_t SerialPortTransmit(tSerialPortIO *io, uint8_t *data, uint16_t size, uint32_t timeout) { + return io->transmit(io->env, data, size, timeout); +} \ No newline at end of file diff --git a/MODULES/SerialPort/modular.json b/MODULES/SerialPort/modular.json new file mode 100644 index 0000000..2fc8762 --- /dev/null +++ b/MODULES/SerialPort/modular.json @@ -0,0 +1,22 @@ +{ + "dep": [ + { + "type": "local", + + "dir": "./MODULES/SerialPortInterface" + }, + { + "type": "local", + + "dir": "./MODULES/SystemDelayInterface" + } + ], + "cmake": { + "inc_dirs": [ + "Inc" + ], + "srcs": [ + "Src/**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/SerialPortCan/Inc/SerialPortCan.h b/MODULES/SerialPortCan/Inc/SerialPortCan.h new file mode 100644 index 0000000..83b58cb --- /dev/null +++ b/MODULES/SerialPortCan/Inc/SerialPortCan.h @@ -0,0 +1,27 @@ +// +// Created by cfif on 12.11.2024. +// + +#ifndef HVAC_SERIALPORTCAN_H +#define HVAC_SERIALPORTCAN_H + +#include "cmsis_os2.h" +#include "SerialPortIO.h" +#include "SerialPortFrameIO.h" + +typedef struct { + tSerialPortFrameIO *CanIO; + osMessageQueueId_t queue; + uint32_t adr; +} tSerialPortCan; + +void vSerialPortCanInit( + tSerialPortCan *env, + tSerialPortFrameIO *CanIO, + uint32_t adr, + uint32_t rxBufferLength +); + +tSerialPortIO vSerialPortCanGetIo(tSerialPortCan *env); + +#endif //HVAC_SERIALPORTCAN_H diff --git a/MODULES/SerialPortCan/Src/SerialPortCan.c b/MODULES/SerialPortCan/Src/SerialPortCan.c new file mode 100644 index 0000000..d0809cd --- /dev/null +++ b/MODULES/SerialPortCan/Src/SerialPortCan.c @@ -0,0 +1,73 @@ +// +// Created by cfif on 12.11.2024. +// + +#include "SerialPortCan.h" +#include "SystemDelayInterface.h" +#include "CanSerialPortFrame.h" + +void vSerialPortCanInit( + tSerialPortCan *env, + tSerialPortFrameIO *CanIO, + uint32_t adr, + uint32_t rxBufferLength +) { + env->CanIO = CanIO; + env->queue = osMessageQueueNew(rxBufferLength, 1, NULL); + env->adr = adr; +} + +static uint16_t vSerialPortReceiveQueue(tSerialPortCan *env, uint8_t *data, uint16_t size, uint32_t timeout, + osMessageQueueId_t queueId) { + uint16_t received = 0; + + + if (timeout) { + uint32_t endMs = SystemGetMs() + timeout; + uint32_t leftMs; + + while (size && ((timeout == SystemWaitForever) || (endMs > SystemGetMs()))) { + leftMs = endMs - SystemGetMs(); + if (osMessageQueueGet(queueId, data, NULL, leftMs) == osOK) { + --size; + ++received; + ++data; + } + } + + } else { + while (size) { + if (osMessageQueueGet(queueId, data, NULL, 0) == osOK) { + --size; + ++received; + ++data; + } else { + return received; + } + } + } + + return received; + +} + +static uint16_t vSerialPortReceive(tSerialPortCan *env, uint8_t *data, uint16_t size, uint32_t timeout) { + return vSerialPortReceiveQueue(env, data, size, timeout, env->queue); +} + +static uint16_t vSerialPortTransmit(tSerialPortCan *env, uint8_t *data, uint16_t size, uint32_t timeout) { + + CanSerialPortFrameSetId(env->CanIO->env, env->adr); + uint16_t sent = env->CanIO->transmit(env->CanIO->env, data, size, env->adr, 0, timeout); + + return sent; +} + +tSerialPortIO vSerialPortCanGetIo(tSerialPortCan *env) { + tSerialPortIO io = { + .env = env, + .receive = (SerialPortIOTransaction) vSerialPortReceive, + .transmit = (SerialPortIOTransaction) vSerialPortTransmit + }; + return io; +} \ No newline at end of file diff --git a/MODULES/SerialPortCan/modular.json b/MODULES/SerialPortCan/modular.json new file mode 100644 index 0000000..71971cd --- /dev/null +++ b/MODULES/SerialPortCan/modular.json @@ -0,0 +1,10 @@ +{ + "cmake": { + "inc_dirs": [ + "Inc" + ], + "srcs": [ + "Src/**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/SerialPortFrameInterface/Inc/SerialPortFrameIO.h b/MODULES/SerialPortFrameInterface/Inc/SerialPortFrameIO.h new file mode 100644 index 0000000..09ab5eb --- /dev/null +++ b/MODULES/SerialPortFrameInterface/Inc/SerialPortFrameIO.h @@ -0,0 +1,19 @@ +// +// Created by cfif on 28.09.22. +// + +#ifndef MODULE_SERIALPORTFRAMEIO_H +#define MODULE_SERIALPORTFRAMEIO_H +#include "stdint.h" + +typedef uint16_t (*SerialPortFrameReceivedTransaction )(void *env, uint8_t idFilter, uint8_t *data, uint16_t size, uint32_t timeout); +typedef uint16_t (*SerialPortFrameTransmitTransaction )(void *env, uint8_t *data, uint16_t size, uint32_t adr, uint8_t canType, uint32_t timeout); + +typedef struct { + void *env; + SerialPortFrameReceivedTransaction receive; + SerialPortFrameTransmitTransaction transmit; +} tSerialPortFrameIO; + + +#endif //MODULE_SERIALPORTFRAMEIO_H diff --git a/MODULES/SerialPortFrameInterface/modular.json b/MODULES/SerialPortFrameInterface/modular.json new file mode 100644 index 0000000..9bdd478 --- /dev/null +++ b/MODULES/SerialPortFrameInterface/modular.json @@ -0,0 +1,7 @@ +{ + "cmake": { + "inc_dirs": [ + "Inc" + ] + } +} \ No newline at end of file diff --git a/MODULES/SerialPortInterface/Inc/SerialPortIO.h b/MODULES/SerialPortInterface/Inc/SerialPortIO.h new file mode 100644 index 0000000..eb2615f --- /dev/null +++ b/MODULES/SerialPortInterface/Inc/SerialPortIO.h @@ -0,0 +1,18 @@ +// +// Created by cfif on 28.09.22. +// + +#ifndef MODULE_SERIALPORTIO_H +#define MODULE_SERIALPORTIO_H +#include "stdint.h" + +typedef uint16_t (*SerialPortIOTransaction )(void *env, uint8_t *data, uint16_t size, uint32_t timeout); + +typedef struct { + void *env; + SerialPortIOTransaction receive; + SerialPortIOTransaction transmit; +} tSerialPortIO; + + +#endif //MODULE_SERIALPORTIO_H diff --git a/MODULES/SerialPortInterface/modular.json b/MODULES/SerialPortInterface/modular.json new file mode 100644 index 0000000..9bdd478 --- /dev/null +++ b/MODULES/SerialPortInterface/modular.json @@ -0,0 +1,7 @@ +{ + "cmake": { + "inc_dirs": [ + "Inc" + ] + } +} \ No newline at end of file diff --git a/MODULES/SerialPort_Flagchip_FC7240/Inc/SerialPortFlagchip.h b/MODULES/SerialPort_Flagchip_FC7240/Inc/SerialPortFlagchip.h new file mode 100644 index 0000000..6dba95d --- /dev/null +++ b/MODULES/SerialPort_Flagchip_FC7240/Inc/SerialPortFlagchip.h @@ -0,0 +1,199 @@ +// +// Created by cfif on 16.09.22. +// + +#ifndef SERIALPORT_SERIALPORT_FLAHCHIP_H +#define SERIALPORT_SERIALPORT_FLAHCHIP_H + +#include "SerialPort.h" +#include "cmsis_os2.h" +#include "stdbool.h" + +#include "interrupt_manager.h" + +#include "fc7xxx_driver_fcuart.h" +#include "fc7xxx_driver_pcc.h" +#include "fc7xxx_driver_port.h" +#include "fc7xxx_driver_scg.h" +#include "fc7xxx_driver_gpio.h" +#include "fc7xxx_driver_dma.h" + + +#define UART_RX_WATERMARK 64U + +typedef struct { + uint8_t UART_INDEX; + DMA_ChannelType RX_DMA_CHANNEL; + DMA_ChannelType TX_DMA_CHANNEL; + FCUART_Type *UART; + + uint32_t DMA_BUF_LEN; + + uint32_t UART_DMA_RECEIVED_POINTER_BUF; + + uint16_t PROCESSED_BYTES; + + FCUART_DataType s_tFCUART_TxMsg; + + FCUART_InitType tInitCfg; + FCUART_InterruptType tInterruptCfg; + + DMA_ChannelCfgType chnCfg_RX; + DMA_InterruptCfgType interruptCfg_RX; + + DMA_ChannelCfgType chnCfg_TX; + DMA_InterruptCfgType interruptCfg_TX; + + uint8_t *dataBufTransmit; + uint32_t dataBufTransmitLen; + + osMessageQueueId_t txAccessQueue; + osMessageQueueId_t rxDataQueue; + osMessageQueueId_t rxDataSnifferQueue; + +} tSerialPortFlagchip; + + +void vSerialPortInitDMA( + tSerialPortFlagchip *env, + + FCUART_Type *uart, + uint32_t BoundRate, + uint8 UART_INDEX, // UART0 = 0 ... UART7 = 7 + IRQn_Type IRQ_UART, // FCUART0_IRQn ... FCUART7_IRQn + uint8 UART_PRIORITY, + + uint8_t *dataBufTransmit, + uint32_t dataBufTransmitLen, + + DMA_ChannelType DMA_CHANNEL_RX, + DMA_RequestSourceType DMA_CHANNEL_REQ_RX, + uint8_t *DMA_BUF_RX, + uint16_t DMA_BUF_LEN_RX, + IRQn_Type IRQ_DMA_RX, + uint8_t IRQ_DMA_PRIORITY_RX, + uint8_t IRQ_DMA_CHANNEL_PRIORITY_RX, + + + DMA_ChannelType DMA_CHANNEL_TX, + DMA_RequestSourceType DMA_CHANNEL_REQ_TX, + uint8_t *DMA_BUF_TX, + uint16_t DMA_BUF_LEN_TX, + IRQn_Type IRQ_DMA_TX, + uint8_t IRQ_DMA_PRIORITY_TX, + uint8_t IRQ_DMA_CHANNEL_PRIORITY_TX, + + + + + uint32_t rxBufferLength, + uint32_t rxSnifferLength, + + DMA_TransferCompleteCallbackType pTransferCompleteNotifyRx, + DMA_TransferErrorCallbackType pTransferErrorNotifyRx, + + DMA_TransferCompleteCallbackType pTransferCompleteNotifyTx, + DMA_TransferErrorCallbackType pTransferErrorNotifyTx, + + FCUART_IdleInterrupt_CallBackType FCUART_IldeInterrupt_CallBack, + FCUART_ErrorInterrupt_CallBackType FCUART_ErrorInterrupt_CallBack, + + FCUART_TxRxInterrupt_CallBackType FCUART_TxEmptyInterrupt_CallBack, + FCUART_TxRxInterrupt_CallBackType FCUART_TxCompleteInterrupt_CallBack +); + +tSerialPortIO vSerialPortGetIo(tSerialPortFlagchip *env); +tSerialPortIO vSerialPortGetSnifferIo(tSerialPortFlagchip *env); + +void SerialPort_RxDmaBufToQueue(tSerialPortFlagchip *env, bool isTransferComplete, const uint8_t *pSrcBuffer); + +void SerialPort_TxEndTransmitted(tSerialPortFlagchip *env, uint8_t data); +/* +#define vSerialPortInitDMAName(ENV, NAME, DMA, RX_DMA_CHANNEL, RX_DMA_CHANNEL_MUX, RX_DMAMUX_DMAREQ_ID, RX_DMA_Channel_IRQ, RX_DMA_FDT_FLAG, DMA_BUF, DMA_BUF_LEN, TX_DMA_CHANNEL, TX_DMA_CHANNEL_MUX, TX_DMAMUX_DMAREQ_ID, TX_DMA_Channel_IRQ, TX_DMA_FDT_FLAG, SWAP, BOUND_RATE, PRIORITY, LEN) \ +vSerialPortInitDMA(ENV, NAME, DMA, RX_DMA_CHANNEL, RX_DMA_CHANNEL_MUX, RX_DMAMUX_DMAREQ_ID, RX_DMA_Channel_IRQ, RX_DMA_FDT_FLAG, DMA_BUF, DMA_BUF_LEN, TX_DMA_CHANNEL, TX_DMA_CHANNEL_MUX, TX_DMAMUX_DMAREQ_ID, TX_DMA_Channel_IRQ, TX_DMA_FDT_FLAG, SWAP, BOUND_RATE, NAME##_IRQn, CRM_##NAME##_PERIPH_CLOCK, PRIORITY, LEN, 0) + +#define vSerialPortInitDMANameWithSniffer(ENV, NAME, DMA, RX_DMA_CHANNEL, RX_DMA_CHANNEL_MUX, RX_DMAMUX_DMAREQ_ID, RX_DMA_Channel_IRQ, RX_DMA_FDT_FLAG, DMA_BUF, DMA_BUF_LEN, TX_DMA_CHANNEL, TX_DMA_CHANNEL_MUX, TX_DMAMUX_DMAREQ_ID, TX_DMA_Channel_IRQ, TX_DMA_FDT_FLAG, SWAP, BOUND_RATE, PRIORITY, LEN, SNIFFER_LEN) \ +vSerialPortInitDMA(ENV, NAME, DMA, RX_DMA_CHANNEL, RX_DMA_CHANNEL_MUX, RX_DMAMUX_DMAREQ_ID, RX_DMA_Channel_IRQ, RX_DMA_FDT_FLAG, DMA_BUF, DMA_BUF_LEN, TX_DMA_CHANNEL, TX_DMA_CHANNEL_MUX, TX_DMAMUX_DMAREQ_ID, TX_DMA_Channel_IRQ, TX_DMA_FDT_FLAG, SWAP, BOUND_RATE, NAME##_IRQn, CRM_##NAME##_PERIPH_CLOCK, PRIORITY, LEN, SNIFFER_LEN) + + +#define DMANONE_CHANNELNONE NULL +#define DMANONE NULL +#define DMANONEMUX_CHANNELNONE NULL +#define DMANONE_FDTNONE_FLAG (uint32_t)0 +#define DMANONE_ChannelNONE_IRQn (IRQn_Type)0 + +#define vSerialPortInitDmaWithNameAndSniffer(\ + ENV, NAME, BOUND_RATE, \ + RX_DMA, RX_CH, \ + TX_DMA, TX_CH, \ + SWAP, PRIORITY, \ + RX_DMA_BUF, RX_DMA_BUF_LEN, \ + QUEUE_LEN, SNIFFER_LEN \ +) \ +vSerialPortInitDMA(\ + ENV, NAME, DMA##RX_DMA, DMA##TX_DMA, \ + DMA##RX_DMA##_CHANNEL##RX_CH, DMA##RX_DMA##MUX_CHANNEL##RX_CH, DMAMUX_DMAREQ_ID_##NAME##_RX, DMA##RX_DMA##_Channel##RX_CH##_IRQn, DMA##RX_DMA##_FDT##RX_CH##_FLAG,\ + RX_DMA_BUF, RX_DMA_BUF_LEN, \ + DMA##TX_DMA##_CHANNEL##TX_CH, DMA##TX_DMA##MUX_CHANNEL##TX_CH, DMAMUX_DMAREQ_ID_##NAME##_TX, DMA##TX_DMA##_Channel##TX_CH##_IRQn, DMA##TX_DMA##_FDT##TX_CH##_FLAG,\ + SWAP, BOUND_RATE, NAME##_IRQn, CRM_##NAME##_PERIPH_CLOCK, \ + PRIORITY, QUEUE_LEN, SNIFFER_LEN\ +) + +#define vSerialPortInitDmaExtWithNameAndSniffer(\ + ENV, NAME, BOUND_RATE, \ + RX_DMA, RX_CH, \ + TX_DMA, TX_CH, \ + SWAP, FLOW, PRIORITY, \ + RX_DMA_BUF, RX_DMA_BUF_LEN, \ + QUEUE_LEN, SNIFFER_LEN \ +) \ +vSerialPortInitDMAExt(\ + ENV, NAME, DMA##RX_DMA, DMA##TX_DMA, \ + DMA##RX_DMA##_CHANNEL##RX_CH, DMA##RX_DMA##MUX_CHANNEL##RX_CH, DMAMUX_DMAREQ_ID_##NAME##_RX, DMA##RX_DMA##_Channel##RX_CH##_IRQn, DMA##RX_DMA##_FDT##RX_CH##_FLAG,\ + RX_DMA_BUF, RX_DMA_BUF_LEN, \ + DMA##TX_DMA##_CHANNEL##TX_CH, DMA##TX_DMA##MUX_CHANNEL##TX_CH, DMAMUX_DMAREQ_ID_##NAME##_TX, DMA##TX_DMA##_Channel##TX_CH##_IRQn, DMA##TX_DMA##_FDT##TX_CH##_FLAG,\ + SWAP, FLOW, BOUND_RATE, NAME##_IRQn, CRM_##NAME##_PERIPH_CLOCK, \ + PRIORITY, QUEUE_LEN, SNIFFER_LEN\ +) + + +#define vSerialPortInitName(ENV, NAME, SWAP, BOUND_RATE, PRIORITY, LEN) \ +vSerialPortInit(ENV, NAME, SWAP, BOUND_RATE, NAME##_IRQn, CRM_##NAME##_PERIPH_CLOCK, PRIORITY, LEN, 0) + +#define vSerialPortExtInitName(ENV, NAME, SWAP, FLOW, BOUND_RATE, PRIORITY, LEN) \ +vSerialPortInit(ENV, NAME, SWAP, FLOW, BOUND_RATE, NAME##_IRQn, CRM_##NAME##_PERIPH_CLOCK, PRIORITY, LEN, 0) + + +#define vSerialPortInitNameWithSniffer(ENV, NAME, SWAP, BOUND_RATE, PRIORITY, LEN, SNIFFER_LEN) \ +vSerialPortInit(ENV, NAME, SWAP, BOUND_RATE, NAME##_IRQn, CRM_##NAME##_PERIPH_CLOCK, PRIORITY, LEN, SNIFFER_LEN) + +#define vSerialPortExtInitNameWithSniffer(ENV, NAME, SWAP, FLOW, BOUND_RATE, PRIORITY, LEN, SNIFFER_LEN) \ +vSerialPortInit(ENV, NAME, SWAP, FLOW, BOUND_RATE, NAME##_IRQn, CRM_##NAME##_PERIPH_CLOCK, PRIORITY, LEN, SNIFFER_LEN) + + +void vSerialPortIrqProcessing(tSerialPortArtery *env); + +void vSerialPortIrqProcessingDMA(tSerialPortArtery *env); + +//void vSerialPortIrqProcessingDMAloop(tSerialPortArtery *env, uint32_t len); + +void SerialPort_IrqProcessing_UartIdle(tSerialPortArtery *env); +void SerialPort_IrqProcessing_DmaRxLoop(tSerialPortArtery *env); +void SerialPort_IrqProcessingFilter_UartIdle(tSerialPortArtery *env, tSerialPortIO *virtualPort, uint16_t *counterBufFilterStr, uint8_t *bufStrFilter, uint16_t maxBufStrFilter, const char *FilterStr[], uint8_t countFiler); +void SerialPort_IrqProcessingFilter_DmaRxLoop(tSerialPortArtery *env, tSerialPortIO *virtualPort, uint16_t *counterBufFilterStr, uint8_t *bufStrFilter, uint16_t maxBufStrFilter, const char *FilterStr[], uint8_t countFiler); + +void SerialPort_IrqProcessing_DmaTx(tSerialPortArtery *env); + +tSerialPortIO vSerialPortGetIo(tSerialPortArtery *env); + +tSerialPortIO vSerialPortGetSnifferIo(tSerialPortArtery *env); + +tSerialPortIO SerialPort_GetSnifferSecondIo(tSerialPortArtery *env); + + uint16_t vSerialPortTransmit(tSerialPortArtery *env, uint8_t *data, uint16_t size, uint32_t timeout); + +uint16_t vSerialPortBlindTransmit(tSerialPortArtery *env, uint8_t *data, uint16_t size, uint32_t timeout); + +void SerialPort_IrqProcessing_DmaTxBlind(tSerialPortArtery *env); +*/ +#endif //SERIALPORT_SERIALPORT_FLAHCHIP_H diff --git a/MODULES/SerialPort_Flagchip_FC7240/Src/SerialPortFlagchip.c b/MODULES/SerialPort_Flagchip_FC7240/Src/SerialPortFlagchip.c new file mode 100644 index 0000000..a1d0040 --- /dev/null +++ b/MODULES/SerialPort_Flagchip_FC7240/Src/SerialPortFlagchip.c @@ -0,0 +1,380 @@ +// +// Created by cfif on 16.09.22. +// +#include +#include "SerialPortFlagchip.h" + +#include "string.h" + +static const PCC_ClkSrcType s_ePccUartTable[] = + { + PCC_CLK_FCUART0, + PCC_CLK_FCUART1, + PCC_CLK_FCUART2, + PCC_CLK_FCUART3, + PCC_CLK_FCUART4, + PCC_CLK_FCUART5, + PCC_CLK_FCUART6, + PCC_CLK_FCUART7 + }; + +void vSerialPortInitDMA( + tSerialPortFlagchip *env, + + FCUART_Type *uart, + uint32_t BoundRate, + uint8 UART_INDEX, // UART0 = 0 ... UART7 = 7 + IRQn_Type IRQ_UART, // FCUART0_IRQn ... FCUART7_IRQn + uint8 UART_PRIORITY, + + uint8_t *dataBufTransmit, + uint32_t dataBufTransmitLen, + + DMA_ChannelType DMA_CHANNEL_RX, + DMA_RequestSourceType DMA_CHANNEL_REQ_RX, + uint8_t *DMA_BUF_RX, + uint16_t DMA_BUF_LEN_RX, + IRQn_Type IRQ_DMA_RX, + uint8_t IRQ_DMA_PRIORITY_RX, + uint8_t IRQ_DMA_CHANNEL_PRIORITY_RX, + + DMA_ChannelType DMA_CHANNEL_TX, + DMA_RequestSourceType DMA_CHANNEL_REQ_TX, + uint8_t *DMA_BUF_TX, + uint16_t DMA_BUF_LEN_TX, + IRQn_Type IRQ_DMA_TX, + uint8_t IRQ_DMA_PRIORITY_TX, + uint8_t IRQ_DMA_CHANNEL_PRIORITY_TX, + + + uint32_t rxBufferLength, + uint32_t rxSnifferLength, + + DMA_TransferCompleteCallbackType pTransferCompleteNotifyRx, + DMA_TransferErrorCallbackType pTransferErrorNotifyRx, + + DMA_TransferCompleteCallbackType pTransferCompleteNotifyTx, + DMA_TransferErrorCallbackType pTransferErrorNotifyTx, + + FCUART_IdleInterrupt_CallBackType FCUART_IldeInterrupt_CallBack, + FCUART_ErrorInterrupt_CallBackType FCUART_ErrorInterrupt_CallBack, + + FCUART_TxRxInterrupt_CallBackType FCUART_TxEmptyInterrupt_CallBack, + FCUART_TxRxInterrupt_CallBackType FCUART_TxCompleteInterrupt_CallBack + + +) { + env->UART_INDEX = UART_INDEX; + env->RX_DMA_CHANNEL = DMA_CHANNEL_RX; + env->TX_DMA_CHANNEL = DMA_CHANNEL_TX; + env->UART = uart; + env->DMA_BUF_LEN = DMA_BUF_LEN_RX; + env->dataBufTransmit = dataBufTransmit; + env->dataBufTransmitLen = dataBufTransmitLen; + env->txAccessQueue = osMessageQueueNew(1, 1, NULL); + env->rxDataQueue = osMessageQueueNew(rxBufferLength, 1, NULL); + + if (rxSnifferLength) { + env->rxDataSnifferQueue = osMessageQueueNew(rxSnifferLength, 1, NULL); + } else { + env->rxDataSnifferQueue = 0; + } + + //начало-----------------------------------DMA-RX------------------------------------------------------------------- + //начало-----------------------------------DMA-RX------------------------------------------------------------------- + //начало-----------------------------------DMA-RX------------------------------------------------------------------- + + env->chnCfg_RX.pSrcBuffer = &(uart->DATA); + env->chnCfg_RX.pDestBuffer = DMA_BUF_RX; + env->chnCfg_RX.u32BlockSize = 1U; + env->chnCfg_RX.u16BlockCount = UART_RX_WATERMARK; + env->chnCfg_RX.u8ChannelPriority = IRQ_DMA_CHANNEL_PRIORITY_RX; + env->chnCfg_RX.eSrcDataSize = DMA_TRANSFER_SIZE_1B; + env->chnCfg_RX.eDestDataSize = DMA_TRANSFER_SIZE_1B; + env->chnCfg_RX.eSrcIncMode = DMA_INCREMENT_DISABLE; + env->chnCfg_RX.eDestIncMode = DMA_INCREMENT_DATA_SIZE; + env->chnCfg_RX.bSrcBlockOffsetEn = false; + env->chnCfg_RX.bDestBlockOffsetEn = false; + env->chnCfg_RX.s32BlockOffset = 0; + env->chnCfg_RX.bSrcAddrLoopbackEn = false; + env->chnCfg_RX.bDestAddrLoopbackEn = false; + env->chnCfg_RX.bAutoStop = false; + + env->chnCfg_RX.bSrcCircularBufferEn = false; + env->chnCfg_RX.u32SrcCircBufferSize = 0U; + env->chnCfg_RX.bDestCircularBufferEn = true; + env->chnCfg_RX.u32DestCircBufferSize = DMA_BUF_LEN_RX; + + env->chnCfg_RX.eTriggerSrc = DMA_CHANNEL_REQ_RX; + DMA_InitChannel(DMA_INSTANCE_0, DMA_CHANNEL_RX, &env->chnCfg_RX); + + env->interruptCfg_RX.bTransferCompleteIntEn = true; + env->interruptCfg_RX.pTransferCompleteNotify = pTransferCompleteNotifyRx; + env->interruptCfg_RX.bTransferErrorIntEn = true; + env->interruptCfg_RX.pTransferErrorNotify = pTransferErrorNotifyRx; + DMA_InitChannelInterrupt(DMA_INSTANCE_0, DMA_CHANNEL_RX, &env->interruptCfg_RX); + + DMA_StartChannel(DMA_INSTANCE_0, DMA_CHANNEL_RX); + +// NVIC_SetPriority(DMA_Error_IRQn, IRQ_DMA_PRIORITY_RX); + NVIC_SetPriority(IRQ_DMA_RX, IRQ_DMA_PRIORITY_RX); + NVIC_EnableIRQ(IRQ_DMA_RX); + + //конец-----------------------------------DMA-RX-------------------------------------------------------------------- + //конец-----------------------------------DMA-RX-------------------------------------------------------------------- + //конец-----------------------------------DMA-RX-------------------------------------------------------------------- + + + //начало-----------------------------------DMA-TX------------------------------------------------------------------- + //начало-----------------------------------DMA-TX------------------------------------------------------------------- + //начало-----------------------------------DMA-TX------------------------------------------------------------------- + + env->chnCfg_TX.pSrcBuffer = DMA_BUF_TX; + env->chnCfg_TX.pDestBuffer = &(uart->DATA); + env->chnCfg_TX.u32BlockSize = 1U; + env->chnCfg_TX.u16BlockCount = 1U; + env->chnCfg_TX.u8ChannelPriority = IRQ_DMA_CHANNEL_PRIORITY_TX; + env->chnCfg_TX.eSrcDataSize = DMA_TRANSFER_SIZE_1B; + env->chnCfg_TX.eDestDataSize = DMA_TRANSFER_SIZE_1B; + env->chnCfg_TX.eSrcIncMode = DMA_INCREMENT_DATA_SIZE; + env->chnCfg_TX.eDestIncMode = DMA_INCREMENT_DISABLE; + env->chnCfg_TX.bSrcBlockOffsetEn = false; + env->chnCfg_TX.bDestBlockOffsetEn = false; + env->chnCfg_TX.s32BlockOffset = 0; + env->chnCfg_TX.bSrcAddrLoopbackEn = false; + env->chnCfg_TX.bDestAddrLoopbackEn = false; + env->chnCfg_TX.bAutoStop = true; + + env->chnCfg_TX.bSrcCircularBufferEn = false; + env->chnCfg_TX.u32SrcCircBufferSize = 0U; + env->chnCfg_TX.bDestCircularBufferEn = false; + env->chnCfg_TX.u32DestCircBufferSize = 0U; + + env->chnCfg_TX.eTriggerSrc = DMA_CHANNEL_REQ_TX; + DMA_InitChannel(DMA_INSTANCE_0, DMA_CHANNEL_TX, &env->chnCfg_TX); + + env->interruptCfg_TX.bTransferCompleteIntEn = true; + env->interruptCfg_TX.pTransferCompleteNotify = pTransferCompleteNotifyTx; + env->interruptCfg_TX.bTransferErrorIntEn = true; + env->interruptCfg_TX.pTransferErrorNotify = pTransferErrorNotifyTx; + DMA_InitChannelInterrupt(DMA_INSTANCE_0, DMA_CHANNEL_TX, &env->interruptCfg_TX); + +// DMA_StartChannel(DMA_INSTANCE_0, DMA_CHANNEL_TX); + + NVIC_SetPriority(IRQ_DMA_TX, IRQ_DMA_PRIORITY_TX); + NVIC_EnableIRQ(IRQ_DMA_TX); + + //конец-----------------------------------DMA-TX-------------------------------------------------------------------- + //конец-----------------------------------DMA-TX-------------------------------------------------------------------- + //конец-----------------------------------DMA-TX-------------------------------------------------------------------- + + //начало------------------------------------UART-------------------------------------------------------------------- + //начало------------------------------------UART-------------------------------------------------------------------- + //начало------------------------------------UART-------------------------------------------------------------------- + + FCUART_ErrorType tRetVal; + uint32_t u32PccFuncClk; + + FCUART_InitMemory(UART_INDEX); + + u32PccFuncClk = PCC_GetPccFunctionClock(s_ePccUartTable[UART_INDEX]); + + if (u32PccFuncClk != 0U) { + env->tInitCfg.bEnRxFullDma = true; // UART receiver full DMA disable + env->tInitCfg.bEnTxEmptyDma = true; + + env->tInitCfg.bEnTxFifo = true; + env->tInitCfg.u8TxFifoWaterMark = 0U; + + env->tInitCfg.bEnRxFifo = true; + env->tInitCfg.u8RxFifoWaterMark = 0U; + + env->tInitCfg.eIdleCharNum = FCUART_IDLE_CHARCTER_64; // UART idle character number 64 + env->tInitCfg.eIdleStart = FCUART_START_AFTER_STOPBIT; // UART idle character type + env->tInitCfg.u32Baudrate = BoundRate; // UART baud-rate + env->tInitCfg.eBitMode = UART_BITMODE_8; // UART bit mode + env->tInitCfg.bParityEnable = false; // UART parity check enable + env->tInitCfg.eStopBit = UART_STOPBIT_NUM_1; // UART stop bit number + env->tInitCfg.u32ClkSrcHz = u32PccFuncClk; // UART function clock + env->tInitCfg.u32TransmitTimeout = 0xFFFFFFFFU; // Transmit timeout tick + + // start initial UART + tRetVal = FCUART_Init(UART_INDEX, &env->tInitCfg); + + if (tRetVal == FCUART_ERROR_OK) { + + env->s_tFCUART_TxMsg.pDatas = (uint8_t *) env->dataBufTransmit; // data buffer must set an array address + env->s_tFCUART_TxMsg.u32DataLen = 0; + env->tInterruptCfg.pTxBuf = &env->s_tFCUART_TxMsg; + + env->tInterruptCfg.bEnIdleInterrupt = true; + env->tInterruptCfg.pIdleNotify = FCUART_IldeInterrupt_CallBack; + env->tInterruptCfg.bEnErrorInterrupt = true; + env->tInterruptCfg.pErrorNotify = FCUART_ErrorInterrupt_CallBack; + env->tInterruptCfg.bEnRxInterrupt = false; + env->tInterruptCfg.pRxNotify = NULL; + + env->tInterruptCfg.bEnTxInterrupt = false; + env->tInterruptCfg.pTxEmptyNotify = FCUART_TxEmptyInterrupt_CallBack; + env->tInterruptCfg.pTxCompleteNotify = FCUART_TxCompleteInterrupt_CallBack; + + tRetVal = FCUART_BufTransmitted(UART_INDEX, &env->tInterruptCfg); + + tRetVal = FCUART_SetInterrupt(UART_INDEX, &env->tInterruptCfg); + + NVIC_SetPriority(IRQ_UART, UART_PRIORITY); + NVIC_EnableIRQ(IRQ_UART); + + FCUART_HWA_SetTxTransfer(env->UART, true); + + tRetVal = FCUART_StartReceive(UART_INDEX); + + } + } + + //конец------------------------------------UART--------------------------------------------------------------------- + //конец------------------------------------UART--------------------------------------------------------------------- + //конец------------------------------------UART--------------------------------------------------------------------- + +} + + +static uint16_t vSerialPortReceiveQueue(tSerialPortFlagchip *env, uint8_t *data, uint16_t size, uint32_t timeout, + osMessageQueueId_t queueId) { + + PROCESS_UNUSED_VAR(env) + + uint16_t received = 0; + + if (timeout) { + uint32_t endMs = SystemGetMs() + timeout; + uint32_t leftMs; + + while (size && ((timeout == SystemWaitForever) || (endMs > SystemGetMs()))) { + leftMs = endMs - SystemGetMs(); + if (osMessageQueueGet(queueId, data, NULL, leftMs) == osOK) { + --size; + ++received; + ++data; + } + } + + } else { + while (size) { + if (osMessageQueueGet(queueId, data, NULL, 0) == osOK) { + --size; + ++received; + ++data; + } else { + return received; + } + } + } + + return received; + +} + +static uint16_t vSerialPortReceive(tSerialPortFlagchip *env, uint8_t *data, uint16_t size, uint32_t timeout) { + return vSerialPortReceiveQueue(env, data, size, timeout, env->rxDataQueue); +} + +static uint16_t vSerialPortReceiveSniffer(tSerialPortFlagchip *env, uint8_t *data, uint16_t size, uint32_t timeout) { + + return env->rxDataSnifferQueue + ? vSerialPortReceiveQueue(env, data, size, timeout, env->rxDataSnifferQueue) + : 0; +} + + +static uint16_t +vSerialPortTransmitOverCore(tSerialPortFlagchip *env, uint8_t *data, uint16_t size, uint32_t timeout) { + + uint16_t sent = 0; + + if (size > 0) { + + DMA_ModifyAddress(DMA_INSTANCE_0, env->TX_DMA_CHANNEL, data, NULL); + DMA_ModifySize(DMA_INSTANCE_0, env->TX_DMA_CHANNEL, size); + + DMA_StartChannel(DMA_INSTANCE_0, env->TX_DMA_CHANNEL); + + uint8_t res; + + sent = (osMessageQueueGet(env->txAccessQueue, &res, 0, timeout) == osOK) ? size : 0; + + DMA_StopChannel(DMA_INSTANCE_0, env->TX_DMA_CHANNEL); + + } + + return sent; + +} + +void SerialPort_TxEndTransmitted(tSerialPortFlagchip *env, uint8_t data) { + osMessageQueuePut(env->txAccessQueue, &data, 0x0, 0U); +} + +void SerialPort_RxDmaBufToQueue(tSerialPortFlagchip *env, bool isTransferComplete, const uint8_t *pSrcBuffer) { + + DMA_Type *aDma[] = DMA_BASE_PTRS; + DMA_Type *const pDma = aDma[DMA_INSTANCE_0]; + + uint16_t remaining_bytes; + + // Если передача завершена + if (isTransferComplete) { + // Количество байт в буфере + remaining_bytes = env->chnCfg_RX.u16BlockCount - env->PROCESSED_BYTES; + env->PROCESSED_BYTES = 0; + } else { + // Количество байт в буфере + remaining_bytes = + env->chnCfg_RX.u16BlockCount - env->PROCESSED_BYTES - pDma->CFG[env->RX_DMA_CHANNEL].CLC.CHTRGENNO; + env->PROCESSED_BYTES += remaining_bytes; + } + + for (uint16_t i = 0; i < remaining_bytes; ++i) { + + osMessageQueuePut(env->rxDataQueue, &pSrcBuffer[env->UART_DMA_RECEIVED_POINTER_BUF], 0x0, 0U); + + if (env->rxDataSnifferQueue) { + osMessageQueuePut(env->rxDataSnifferQueue, &pSrcBuffer[env->UART_DMA_RECEIVED_POINTER_BUF], 0x0, 0U); + } + + ++env->UART_DMA_RECEIVED_POINTER_BUF; + + if (env->UART_DMA_RECEIVED_POINTER_BUF >= env->DMA_BUF_LEN) { + env->UART_DMA_RECEIVED_POINTER_BUF = 0; + } + + } + +} + + +static SerialPortIOTransaction vSerialPortTransmitterGet(tSerialPortFlagchip *env) { + + PROCESS_UNUSED_VAR(env) + + return (SerialPortIOTransaction) vSerialPortTransmitOverCore; + +} + +tSerialPortIO vSerialPortGetIo(tSerialPortFlagchip *env) { + tSerialPortIO io = { + .env = env, + .receive = (SerialPortIOTransaction) vSerialPortReceive, + .transmit = vSerialPortTransmitterGet(env) + }; + return io; +} + +tSerialPortIO vSerialPortGetSnifferIo(tSerialPortFlagchip *env) { + tSerialPortIO io = { + .env = env, + .receive = (SerialPortIOTransaction) vSerialPortReceiveSniffer, + .transmit = vSerialPortTransmitterGet(env) + }; + return io; +} diff --git a/MODULES/SerialPort_Flagchip_FC7240/modular.json b/MODULES/SerialPort_Flagchip_FC7240/modular.json new file mode 100644 index 0000000..4f4eddb --- /dev/null +++ b/MODULES/SerialPort_Flagchip_FC7240/modular.json @@ -0,0 +1,22 @@ +{ + "dep": [ + { + "type": "local", + + "dir": "./MODULES/SerialPort" + }, + { + "type": "local", + + "dir": "./MODULES/SystemDelayInterface" + } + ], + "cmake": { + "inc_dirs": [ + "Inc" + ], + "srcs": [ + "Src/**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/SerialPort_P2P_CmsisRtos/Inc/SerialPortP2p.h b/MODULES/SerialPort_P2P_CmsisRtos/Inc/SerialPortP2p.h new file mode 100644 index 0000000..baf3e9b --- /dev/null +++ b/MODULES/SerialPort_P2P_CmsisRtos/Inc/SerialPortP2p.h @@ -0,0 +1,23 @@ +// +// Created by CFIF on 13.11.22. +// + +#ifndef UVEOS_ON_NATION_SERIALPORTP2P_H +#define UVEOS_ON_NATION_SERIALPORTP2P_H + +#include +#include +#include + +typedef struct { + osMessageQueueId_t firstToSecondQueue; + osMessageQueueId_t secondToFirstQueue; +} tSerialPortP2p; + +void SerialPortP2p_Init(tSerialPortP2p *env, uint16_t firstToSecondBufferLen, uint16_t secondToFirstBufferLen); + +tSerialPortIO SerialPortP2p_GetIoFirst(tSerialPortP2p *env); + +tSerialPortIO SerialPortP2p_GetIoSecond(tSerialPortP2p *env); + +#endif //UVEOS_ON_NATION_SERIALPORTP2P_H diff --git a/MODULES/SerialPort_P2P_CmsisRtos/Src/SerialPortP2p.c b/MODULES/SerialPort_P2P_CmsisRtos/Src/SerialPortP2p.c new file mode 100644 index 0000000..6faf648 --- /dev/null +++ b/MODULES/SerialPort_P2P_CmsisRtos/Src/SerialPortP2p.c @@ -0,0 +1,101 @@ +// +// Created by CFIF on 13.11.22. +// +#include "SerialPortP2p.h" + +void SerialPortP2p_Init(tSerialPortP2p *env, uint16_t firstToSecondBufferLen, uint16_t secondToFirstBufferLen) { + env->firstToSecondQueue = osMessageQueueNew(firstToSecondBufferLen, 1, NULL); + env->secondToFirstQueue = osMessageQueueNew(secondToFirstBufferLen, 1, NULL); +} + +static uint16_t vSerialPortReceiveQueue(uint8_t *data, uint16_t size, uint32_t timeout, osMessageQueueId_t queueId) { + uint16_t received = 0; + + uint32_t endMs = SystemGetMs() + timeout; + uint32_t leftMs; + + uint16_t granted = 0; + + if (!timeout) { + granted = osMessageQueueGetCount(queueId); + } + + while (size && (((timeout == SystemWaitForever) || (endMs > SystemGetMs())) || (received < granted))) { + leftMs = endMs - SystemGetMs(); + if (osMessageQueueGet(queueId, data, NULL, leftMs) == osOK) { + --size; + ++received; + ++data; + } else if (timeout == 0) { + return received; + } + } + + return received; +} + +static uint16_t vSerialPortReceiveFirst(tSerialPortP2p *env, uint8_t *data, uint16_t size, uint32_t timeout) { + return vSerialPortReceiveQueue(data, size, timeout, env->secondToFirstQueue); +} + +static uint16_t vSerialPortReceiveSecond(tSerialPortP2p *env, uint8_t *data, uint16_t size, uint32_t timeout) { + return vSerialPortReceiveQueue(data, size, timeout, env->firstToSecondQueue); +} + +static uint16_t vSerialPortTransmitQueue(uint8_t *data, uint16_t size, uint32_t timeout, osMessageQueueId_t queueId) { + uint16_t sent = 0; + + uint32_t endMs = SystemGetMs() + timeout; + uint32_t leftMs; + + uint16_t granted = 0; + + if (!timeout) { + granted = osMessageQueueGetSpace(queueId); + } + + while (size && (((timeout == SystemWaitForever) || (endMs > SystemGetMs())) || (sent < granted))) { + + if (timeout == SystemWaitForever) { + leftMs = SystemWaitForever; + } else { + leftMs = endMs - SystemGetMs(); + } + + if (osMessageQueuePut(queueId, data, 0x00, leftMs) == osOK) { + --size; + ++sent; + ++data; + } else if (timeout == 0) { + return sent; + } + } + return sent; +} + + +static uint16_t vSerialPortTransmitFirst(tSerialPortP2p *env, uint8_t *data, uint16_t size, uint32_t timeout) { + return vSerialPortTransmitQueue(data, size, timeout, env->firstToSecondQueue); +} + +static uint16_t vSerialPortTransmitSecond(tSerialPortP2p *env, uint8_t *data, uint16_t size, uint32_t timeout) { + return vSerialPortTransmitQueue(data, size, timeout, env->secondToFirstQueue); +} + +tSerialPortIO SerialPortP2p_GetIoFirst(tSerialPortP2p *env) { + tSerialPortIO io = { + .env = env, + .receive = (SerialPortIOTransaction) vSerialPortReceiveFirst, + .transmit = (SerialPortIOTransaction) vSerialPortTransmitFirst + }; + return io; +} + +tSerialPortIO SerialPortP2p_GetIoSecond(tSerialPortP2p *env) { + tSerialPortIO io = { + .env = env, + .receive = (SerialPortIOTransaction) vSerialPortReceiveSecond, + .transmit = (SerialPortIOTransaction) vSerialPortTransmitSecond + }; + return io; +} \ No newline at end of file diff --git a/MODULES/SerialPort_P2P_CmsisRtos/modular.json b/MODULES/SerialPort_P2P_CmsisRtos/modular.json new file mode 100644 index 0000000..f14c79e --- /dev/null +++ b/MODULES/SerialPort_P2P_CmsisRtos/modular.json @@ -0,0 +1,27 @@ +{ + "dep": [ + { + "type": "local", + + "dir": "./MODULES/CmsisRtosInterface" + }, + { + "type": "local", + + "dir": "./MODULES/SerialPortInterface" + }, + { + "type": "local", + + "dir": "./MODULES/SystemDelayInterface" + } + ], + "cmake": { + "inc_dirs": [ + "Inc/" + ], + "srcs": [ + "Src/**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/SerialPort_Virt_CmsisRtos/Inc/SerialPortVirt.h b/MODULES/SerialPort_Virt_CmsisRtos/Inc/SerialPortVirt.h new file mode 100644 index 0000000..cf40c00 --- /dev/null +++ b/MODULES/SerialPort_Virt_CmsisRtos/Inc/SerialPortVirt.h @@ -0,0 +1,21 @@ +// +// Created by CFIF on 13.11.22. +// + +#ifndef UVEOS_ON_NATION_SERIALPORTVIRT_H +#define UVEOS_ON_NATION_SERIALPORTVIRT_H + +#include +#include +#include + +typedef struct { + osMessageQueueId_t queue; +// osMutexId_t access; +} tSerialPortVirt; + +void SerialPortVirt_Init(tSerialPortVirt *env, uint16_t queueBufferLen); + +tSerialPortIO SerialPortVirt_GetIo(tSerialPortVirt *env); + +#endif //UVEOS_ON_NATION_SERIALPORTVIRT_H diff --git a/MODULES/SerialPort_Virt_CmsisRtos/Src/SerialPortVirt.c b/MODULES/SerialPort_Virt_CmsisRtos/Src/SerialPortVirt.c new file mode 100644 index 0000000..3e03e44 --- /dev/null +++ b/MODULES/SerialPort_Virt_CmsisRtos/Src/SerialPortVirt.c @@ -0,0 +1,113 @@ +// +// Created by CFIF on 13.11.22. +// +#include "SerialPortVirt.h" + +void SerialPortVirt_Init(tSerialPortVirt *env, uint16_t queueBufferLen) { + env->queue = osMessageQueueNew(queueBufferLen, 1, NULL); +// env->access = osMutexNew(NULL); +} + +static uint16_t vSerialPortReceiveQueue(uint8_t *data, uint16_t size, uint32_t timeout, osMessageQueueId_t queueId) { + uint16_t received = 0; + + uint32_t endMs = SystemGetMs() + timeout; + uint32_t leftMs = 0; + + uint16_t granted = 0; + + if (!timeout) { + granted = osMessageQueueGetCount(queueId); + } + + while (size && (((timeout == SystemWaitForever) || (endMs > SystemGetMs())) || (received < granted))) { + + if (timeout == SystemWaitForever) { + leftMs = SystemWaitForever; + } else { + leftMs = endMs - SystemGetMs(); + } + + if (osMessageQueueGet(queueId, data, NULL, leftMs) == osOK) { + --size; + ++received; + ++data; + } else if (timeout == 0) { + return received; + } + } + + return received; +} + +static uint16_t vSerialPortReceive(tSerialPortVirt *env, uint8_t *data, uint16_t size, uint32_t timeout) { + + uint16_t result; + + + result = vSerialPortReceiveQueue(data, size, timeout, env->queue); + + + return result; + +} + +static uint16_t vSerialPortTransmitQueue(uint8_t *data, uint16_t size, uint32_t timeout, osMessageQueueId_t queueId) { + uint16_t sent = 0; + + uint32_t endMs = SystemGetMs() + timeout; + uint32_t leftMs; + + uint16_t granted = 0; + + if (!timeout) { + granted = osMessageQueueGetSpace(queueId); + } + + while (size && (((timeout == SystemWaitForever) || (endMs > SystemGetMs())) || (sent < granted))) { + + if (timeout == SystemWaitForever) { + leftMs = SystemWaitForever; + } else { + leftMs = endMs - SystemGetMs(); + } + + if (osMessageQueuePut(queueId, data, 0x00, leftMs) == osOK) { + --size; + ++sent; + ++data; + } else if (timeout == 0) { + return sent; + } + } + return sent; +} + + +static uint16_t vSerialPortTransmit(tSerialPortVirt *env, uint8_t *data, uint16_t size, uint32_t timeout) { + + + +// if (osMutexAcquire(env->access, 1000) == osOK) { +// result = vSerialPortTransmitQueue(data, size, timeout, env->queue); +// osMutexRelease(env->access); +// } + + uint16_t sent = 0; + for (uint16_t i = 0; i < size; ++i) { + if (osMessageQueuePut(env->queue, &data[i], 0x00, 0) == osOK) { + ++sent; + } + } + + return sent; +} + +tSerialPortIO SerialPortVirt_GetIo(tSerialPortVirt *env) { + tSerialPortIO io = { + .env = env, + .receive = (SerialPortIOTransaction) vSerialPortReceive, + .transmit = (SerialPortIOTransaction) vSerialPortTransmit + }; + return io; +} diff --git a/MODULES/SerialPort_Virt_CmsisRtos/modular.json b/MODULES/SerialPort_Virt_CmsisRtos/modular.json new file mode 100644 index 0000000..f14c79e --- /dev/null +++ b/MODULES/SerialPort_Virt_CmsisRtos/modular.json @@ -0,0 +1,27 @@ +{ + "dep": [ + { + "type": "local", + + "dir": "./MODULES/CmsisRtosInterface" + }, + { + "type": "local", + + "dir": "./MODULES/SerialPortInterface" + }, + { + "type": "local", + + "dir": "./MODULES/SystemDelayInterface" + } + ], + "cmake": { + "inc_dirs": [ + "Inc/" + ], + "srcs": [ + "Src/**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/StorageInterface/Inc/StorageIO.h b/MODULES/StorageInterface/Inc/StorageIO.h new file mode 100644 index 0000000..a769d37 --- /dev/null +++ b/MODULES/StorageInterface/Inc/StorageIO.h @@ -0,0 +1,32 @@ +// +// Created by cfif on 07.10.22. +// + +#ifndef MODULE_STORAGEIO_H +#define MODULE_STORAGEIO_H + +#include "stdint.h" +#include "stddef.h" + +typedef enum { + STORAGE_OK = 0, + STORAGE_ERR_DATA = 1, + STORAGE_ERR_DEVICE = 2, +} eStorageStatus; + +typedef eStorageStatus (*StorageIOTransaction )(void *env, void *mem, size_t size); + +typedef struct { + void *env; + StorageIOTransaction load; + StorageIOTransaction dump; +} tStorageInterface; + +#define StorageDump(STORAGE, MEM, SIZE) (STORAGE)->dump((STORAGE)->env, MEM, SIZE) +#define StorageLoad(STORAGE, MEM, SIZE) (STORAGE)->load((STORAGE)->env, MEM, SIZE) + +#define StorageDumpStatic(STORAGE, MEM) (STORAGE)->dump((STORAGE)->env, &(MEM), sizeof(MEM)) +#define StorageLoadStatic(STORAGE, MEM) (STORAGE)->load((STORAGE)->env, &(MEM), sizeof(MEM)) + + +#endif //MODULE_STORAGEIO_H diff --git a/MODULES/StorageInterface/modular.json b/MODULES/StorageInterface/modular.json new file mode 100644 index 0000000..9bdd478 --- /dev/null +++ b/MODULES/StorageInterface/modular.json @@ -0,0 +1,7 @@ +{ + "cmake": { + "inc_dirs": [ + "Inc" + ] + } +} \ No newline at end of file diff --git a/MODULES/StorageOnFlash_Flagchip_FC7240/Inc/StorageOnFlashFlagchip.h b/MODULES/StorageOnFlash_Flagchip_FC7240/Inc/StorageOnFlashFlagchip.h new file mode 100644 index 0000000..562da13 --- /dev/null +++ b/MODULES/StorageOnFlash_Flagchip_FC7240/Inc/StorageOnFlashFlagchip.h @@ -0,0 +1,35 @@ +// +// Created by cfif on 07.10.22. +// + +#ifndef STORAGE_ON_FLASH_FLAGCHIP_H +#define STORAGE_ON_FLASH_FLAGCHIP_H + +#include "stddef.h" +#include "StorageIO.h" +#include "LoggerInterface.h" + +typedef enum { + STORAGE_TYPE_D_DATA, + STORAGE_TYPE_P_DATA +} eTypeStorageOnFlashFlagchip; + +typedef struct { + uint32_t mainFlashPageAddress; + uint32_t recoveryFlashPageAddress; + eTypeStorageOnFlashFlagchip TypeStorageOnFlashFlagchip; + tLoggerInterface *logger; +} tStorageOnFlashFlagchip; + +void vStorageOnFlashFlagchip_Init( + tStorageOnFlashFlagchip *env, + eTypeStorageOnFlashFlagchip TypeStorageOnFlashFlagchip, + uint32_t mainPage, + uint32_t recoveryPage +); + + +tStorageInterface xStorageOnFlashFlagchip_GetInterface(tStorageOnFlashFlagchip *env); + + +#endif //STORAGE_ON_FLASH_FLAGCHIP_H diff --git a/MODULES/StorageOnFlash_Flagchip_FC7240/Src/StorageOnFlashFlagchip.c b/MODULES/StorageOnFlash_Flagchip_FC7240/Src/StorageOnFlashFlagchip.c new file mode 100644 index 0000000..572dac1 --- /dev/null +++ b/MODULES/StorageOnFlash_Flagchip_FC7240/Src/StorageOnFlashFlagchip.c @@ -0,0 +1,226 @@ +// +// Created by cfif on 07.10.22. +// +#include "InternalFlashPage.h" +#include "StorageOnFlashFlagchip.h" +#include "crc32_m7.h" + +#define LOGGER env->logger +#define LOG_SIGN "Storage" + +static uint32_t xStorageOnFlashArtery_Crc(uint8_t *data, size_t len) { + + uint32_t crc = UdsCrc32Update_Hardware(0xFFFFFFFF, data, len, NULL, NULL, 0); + + return crc; + + /* + uint32_t crc = 0; + + uint8_t *end = data + len; + while (data < end) { + crc += *data; + ++data; + } + + return crc; + */ +} + +static uint32_t xStorageOnFlashArtery_CrcFlash(tStorageOnFlashFlagchip *env, uint8_t *addressOnFlash, size_t len) { + uint32_t crc = UdsCrc32Update_Hardware(0xFFFFFFFF, addressOnFlash, len, NULL, NULL, 0); + + return crc; + /* + uint32_t crc = 0; + + size_t left = len; + uint8_t *end = addressOnFlash + len; + + uint32_t word; + while (addressOnFlash < end) { + + if (env->TypeStorageOnFlashFlagchip == STORAGE_TYPE_D_DATA) { + word = D_iInternalFlashPage_ReadWord((uint32_t) addressOnFlash); + } else { + word = P_iInternalFlashPage_ReadWord((uint32_t) addressOnFlash); + } + + for (uint8_t sub_byte = 0; (sub_byte < 4) && (left); ++sub_byte) { + crc += ((uint8_t *) &word)[sub_byte]; + --left; + } + addressOnFlash += 4; + } + + return crc; + */ +} + +static eStorageStatus +xStorageOnFlashFlagchip_DumpOn( + tStorageOnFlashFlagchip *env, + uint32_t dataCrc, + uint32_t pageAddress, + void *data, + size_t size +) { + +// if (!bInternalFlashPage_Clear(pageAddress)) { +// return STORAGE_ERR_DEVICE; +// } +// +// size_t dataSizeOnFlash = sInternalFlashPage_Write(pageAddress, 0x0, env->data, env->size); + + size_t dataSizeOnFlash; + if (env->TypeStorageOnFlashFlagchip == STORAGE_TYPE_D_DATA) { + dataSizeOnFlash = D_bInternalFlashPage_DumpFromRam(pageAddress, data, size); + } else { + dataSizeOnFlash = P_bInternalFlashPage_DumpFromRam(pageAddress, data, size); + } + + if (dataSizeOnFlash < size) { + return STORAGE_ERR_DEVICE; + } + + uint64_t dataCrc64 = dataCrc; + + if (env->TypeStorageOnFlashFlagchip == STORAGE_TYPE_D_DATA) { + if (D_sInternalFlashPage_Write(pageAddress, dataSizeOnFlash, (uint8_t *) &dataCrc64, 8) != 8) { + return STORAGE_ERR_DEVICE; + } + } else { + if (P_sInternalFlashPage_Write(pageAddress, dataSizeOnFlash, (uint8_t *) &dataCrc64, 8) != 8) { + return STORAGE_ERR_DEVICE; + } + } + + + uint32_t flashCalcCrc = xStorageOnFlashArtery_CrcFlash(env, (uint8_t *) pageAddress, size); + + uint32_t flashReedCrc; + if (env->TypeStorageOnFlashFlagchip == STORAGE_TYPE_D_DATA) { + flashReedCrc = D_iInternalFlashPage_ReadWord(pageAddress + dataSizeOnFlash); + } else { + flashReedCrc = P_iInternalFlashPage_ReadWord(pageAddress + dataSizeOnFlash); + } + + if ((flashCalcCrc == flashReedCrc) && (flashCalcCrc == dataCrc)) { + return STORAGE_OK; + } else { + return STORAGE_ERR_DATA; + } + +} + +static uint8_t xStorageOnFlashFlagchip_Dump(tStorageOnFlashFlagchip *env, void *data, size_t size) { + + + size = size - 8; + + uint32_t crc = xStorageOnFlashArtery_Crc(data, size); + + if (xStorageOnFlashFlagchip_DumpOn(env, crc, env->recoveryFlashPageAddress, data, size) != STORAGE_OK) { + return STORAGE_ERR_DEVICE; + } + + if (xStorageOnFlashFlagchip_DumpOn(env, crc, env->mainFlashPageAddress, data, size) != STORAGE_OK) { + return STORAGE_ERR_DEVICE; + } + + return STORAGE_OK; +} + + +eStorageStatus xStorageOnFlashFlagchip_Load(tStorageOnFlashFlagchip *env, void *data, size_t size) { + + + size_t offset_crc = size - 8; + + uint32_t recoveryCrcCalc = xStorageOnFlashArtery_CrcFlash(env, (uint8_t *) env->recoveryFlashPageAddress, + offset_crc); + + uint32_t recoveryCrcReed; + if (env->TypeStorageOnFlashFlagchip == STORAGE_TYPE_D_DATA) { + recoveryCrcReed = D_iInternalFlashPage_ReadWord(env->recoveryFlashPageAddress + offset_crc); + } else { + recoveryCrcReed = P_iInternalFlashPage_ReadWord(env->recoveryFlashPageAddress + offset_crc); + } + + LoggerFormatInfo(LOGGER, LOG_SIGN, "Crc recovery page (calc): 0x%08X", recoveryCrcCalc) + LoggerFormatInfo(LOGGER, LOG_SIGN, "Crc recovery page (flash): 0x%08X", recoveryCrcReed) + + uint32_t mainCrcCalc = xStorageOnFlashArtery_CrcFlash(env, (uint8_t *) env->mainFlashPageAddress, offset_crc); + + uint32_t mainCrcReed; + if (env->TypeStorageOnFlashFlagchip == STORAGE_TYPE_D_DATA) { + mainCrcReed = D_iInternalFlashPage_ReadWord(env->mainFlashPageAddress + offset_crc); + } else { + mainCrcReed = P_iInternalFlashPage_ReadWord(env->mainFlashPageAddress + offset_crc); + } + + LoggerFormatInfo(LOGGER, LOG_SIGN, "Crc main page (calc): 0x%08X", mainCrcCalc) + LoggerFormatInfo(LOGGER, LOG_SIGN, "Crc main page (flash): 0x%08X", mainCrcReed) + + bool recoveryCrcOk = (recoveryCrcCalc == recoveryCrcReed); + bool mainCrcOk = (mainCrcReed == mainCrcCalc); + + if (recoveryCrcOk && mainCrcOk) { + if (recoveryCrcReed == mainCrcReed) { + if (env->TypeStorageOnFlashFlagchip == STORAGE_TYPE_D_DATA) { + D_sInternalFlashPage_Read(env->mainFlashPageAddress, 0x0, data, offset_crc); + } else { + P_sInternalFlashPage_Read(env->mainFlashPageAddress, 0x0, data, offset_crc); + } + + return STORAGE_OK; + } else { + LoggerInfoStatic(LOGGER, LOG_SIGN, "Data recovery main page (main page <- recovery) ") + if (env->TypeStorageOnFlashFlagchip == STORAGE_TYPE_D_DATA) { + D_sInternalFlashPage_Read(env->recoveryFlashPageAddress, 0x0, data, offset_crc); + } else { + P_sInternalFlashPage_Read(env->recoveryFlashPageAddress, 0x0, data, offset_crc); + } + + return xStorageOnFlashFlagchip_DumpOn(env, recoveryCrcCalc, env->mainFlashPageAddress, data, offset_crc); + } + } else if (recoveryCrcOk || mainCrcOk) { + if (recoveryCrcOk) { + LoggerInfoStatic(LOGGER, LOG_SIGN, "Data recovery main page (main page <- recovery)") + if (env->TypeStorageOnFlashFlagchip == STORAGE_TYPE_D_DATA) { + D_sInternalFlashPage_Read(env->recoveryFlashPageAddress, 0x0, data, offset_crc); + } else { + P_sInternalFlashPage_Read(env->recoveryFlashPageAddress, 0x0, data, offset_crc); + } + return xStorageOnFlashFlagchip_DumpOn(env, recoveryCrcCalc, env->mainFlashPageAddress, data, offset_crc); + } else { + LoggerInfoStatic(LOGGER, LOG_SIGN, "Data recovery recovery page (main page -> recovery)") + if (env->TypeStorageOnFlashFlagchip == STORAGE_TYPE_D_DATA) { + D_sInternalFlashPage_Read(env->mainFlashPageAddress, 0x0, data, offset_crc); + } else { + P_sInternalFlashPage_Read(env->mainFlashPageAddress, 0x0, data, offset_crc); + } + return xStorageOnFlashFlagchip_DumpOn(env, mainCrcCalc, env->recoveryFlashPageAddress, data, offset_crc); + } + } else { + return STORAGE_ERR_DATA; + } + +} + +void vStorageOnFlashFlagchip_Init( + tStorageOnFlashFlagchip *env, eTypeStorageOnFlashFlagchip TypeStorageOnFlashFlagchip, uint32_t mainPage, + uint32_t recoveryPage +) { + env->TypeStorageOnFlashFlagchip = TypeStorageOnFlashFlagchip; + env->mainFlashPageAddress = mainPage; + env->recoveryFlashPageAddress = recoveryPage; +} + +tStorageInterface xStorageOnFlashFlagchip_GetInterface(tStorageOnFlashFlagchip *env) { + return (tStorageInterface) { + .env = env, + .load = (StorageIOTransaction) xStorageOnFlashFlagchip_Load, + .dump = (StorageIOTransaction) xStorageOnFlashFlagchip_Dump + }; +} \ No newline at end of file diff --git a/MODULES/StorageOnFlash_Flagchip_FC7240/modular.json b/MODULES/StorageOnFlash_Flagchip_FC7240/modular.json new file mode 100644 index 0000000..89baf75 --- /dev/null +++ b/MODULES/StorageOnFlash_Flagchip_FC7240/modular.json @@ -0,0 +1,22 @@ +{ + "dep": [ + { + "type": "local", + + "dir": "./MODULES/StorageInterface" + }, + { + "type": "local", + + "dir": "./MODULES/InternalFlashPage_Flagchip_FC7240" + } + ], + "cmake": { + "inc_dirs": [ + "Inc" + ], + "srcs": [ + "Src/**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/SystemDelayInterface/Inc/SystemDelayInterface.h b/MODULES/SystemDelayInterface/Inc/SystemDelayInterface.h new file mode 100644 index 0000000..c52a096 --- /dev/null +++ b/MODULES/SystemDelayInterface/Inc/SystemDelayInterface.h @@ -0,0 +1,18 @@ +// +// Created by CFIF on 8/24/22. +// + +#ifndef MODULE_SYSTEMDELAYINTERFACE_H +#define MODULE_SYSTEMDELAYINTERFACE_H + +#include "stdint.h" + +extern const uint32_t SystemWaitForever; + +void SystemDelayMs(uint32_t ms); + +uint64_t SystemGetMs(); + +uint64_t SystemMsToTicks(uint64_t ms); + +#endif //MODULE_SYSTEMDELAYINTERFACE_H diff --git a/MODULES/SystemDelayInterface/modular.json b/MODULES/SystemDelayInterface/modular.json new file mode 100644 index 0000000..174bad2 --- /dev/null +++ b/MODULES/SystemDelayInterface/modular.json @@ -0,0 +1,7 @@ +{ + "cmake": { + "inc_dirs": [ + "Inc" + ] + } +} diff --git a/MODULES/SystemDelay_CMSIS_RTOS/Src/SystemDelayCmsisRtos.c b/MODULES/SystemDelay_CMSIS_RTOS/Src/SystemDelayCmsisRtos.c new file mode 100644 index 0000000..2235afd --- /dev/null +++ b/MODULES/SystemDelay_CMSIS_RTOS/Src/SystemDelayCmsisRtos.c @@ -0,0 +1,26 @@ +// +// Created by CFIF on 29.08.22. +// +#include +#include "SystemDelayInterface.h" +#include "systickcounter.h" + +const uint32_t SystemWaitForever = osWaitForever; + +void SystemYield() { + osThreadYield(); +} + +void SystemDelayMs(uint32_t ms) { + osDelay(SystemMsToTicks(ms)); +} + +uint64_t SystemMsToTicks(uint64_t ms) { + return (ms * osKernelGetTickFreq()) / 1000; +} + +uint64_t SystemGetMs() { +// return (osKernelGetTickCount() * osKernelGetTickFreq()) / 1000; +// return (__sys_tick_counter * osKernelGetTickFreq()) / 1000; + return __sys_tick_counter; +} \ No newline at end of file diff --git a/MODULES/SystemDelay_CMSIS_RTOS/modular.json b/MODULES/SystemDelay_CMSIS_RTOS/modular.json new file mode 100644 index 0000000..6d4a0d8 --- /dev/null +++ b/MODULES/SystemDelay_CMSIS_RTOS/modular.json @@ -0,0 +1,21 @@ +{ + "dep": [ + { + "type": "local", + + "dir": "./MODULES/CmsisRtosInterface" + }, + { + "type": "local", + + "dir": "./MODULES/SystemDelayInterface" + } + ], + "cmake": { + "inc_dirs": [ + ], + "srcs": [ + "Src/**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/SystemSyncInterface/inc/SystemMutexInterface.h b/MODULES/SystemSyncInterface/inc/SystemMutexInterface.h new file mode 100644 index 0000000..66f1b09 --- /dev/null +++ b/MODULES/SystemSyncInterface/inc/SystemMutexInterface.h @@ -0,0 +1,25 @@ +// +// Created by CFIF on 26.09.23. +// + +#ifndef MOTOTERMINAL_MAIN_ONAT435_MUTEXINTERFACE_H +#define MOTOTERMINAL_MAIN_ONAT435_MUTEXINTERFACE_H + +#include "stdbool.h" +#include "stdint.h" + +typedef bool ( *SystemMutex_Operation_acquire )(void *env, int32_t timeout); + +typedef bool ( *SystemMutex_Operation_release )(void *env); + +typedef struct { + void *env; + SystemMutex_Operation_acquire acquire; + SystemMutex_Operation_release release; +} tSystemMutexInterface; + +#define SystemMutex_acquire(ENV, TIMEOUT) (ENV)->acquire((ENV)->env,TIMEOUT) +#define SystemMutex_release(ENV) (ENV)->release((ENV)->env) + + +#endif //MOTOTERMINAL_MAIN_ONAT435_MUTEXINTERFACE_H diff --git a/MODULES/SystemSyncInterface/modular.json b/MODULES/SystemSyncInterface/modular.json new file mode 100644 index 0000000..ed66e77 --- /dev/null +++ b/MODULES/SystemSyncInterface/modular.json @@ -0,0 +1,7 @@ +{ + "cmake": { + "inc_dirs": [ + "inc" + ] + } +} diff --git a/MODULES/SystemSync_CMSIS_RTOS/inc/SystemMutexCmsis.h b/MODULES/SystemSync_CMSIS_RTOS/inc/SystemMutexCmsis.h new file mode 100644 index 0000000..4d13b6b --- /dev/null +++ b/MODULES/SystemSync_CMSIS_RTOS/inc/SystemMutexCmsis.h @@ -0,0 +1,17 @@ +// +// Created by CFIF on 26.09.23. +// + +#ifndef MOTOTERMINAL_MAIN_ONAT435_SYSTEMMUTEXCMSIS_H +#define MOTOTERMINAL_MAIN_ONAT435_SYSTEMMUTEXCMSIS_H + +#include "SystemMutexInterface.h" +#include "cmsis_os.h" + +typedef osMutexId_t SystemMutexCmsis; + +void SystemMutexCmsis_init(SystemMutexCmsis *env, const osMutexAttr_t *attr); + +tSystemMutexInterface SystemMutexCmsis_getInterface(SystemMutexCmsis *env); + +#endif //MOTOTERMINAL_MAIN_ONAT435_SYSTEMMUTEXCMSIS_H diff --git a/MODULES/SystemSync_CMSIS_RTOS/modular.json b/MODULES/SystemSync_CMSIS_RTOS/modular.json new file mode 100644 index 0000000..9211cf4 --- /dev/null +++ b/MODULES/SystemSync_CMSIS_RTOS/modular.json @@ -0,0 +1,22 @@ +{ + "dep": [ + { + "type": "local", + + "dir": "./MODULES/CmsisRtosInterface" + }, + { + "type": "local", + + "dir": "./MODULES/SystemSyncInterface" + } + ], + "cmake": { + "inc_dirs": [ + "./inc/" + ], + "srcs": [ + "./src/**.c" + ] + } +} \ No newline at end of file diff --git a/MODULES/SystemSync_CMSIS_RTOS/src/SystemMutexCmsis.c b/MODULES/SystemSync_CMSIS_RTOS/src/SystemMutexCmsis.c new file mode 100644 index 0000000..b009a82 --- /dev/null +++ b/MODULES/SystemSync_CMSIS_RTOS/src/SystemMutexCmsis.c @@ -0,0 +1,30 @@ +// +// Created by CFIF on 26.09.23. +// +#include +#include +#include "SystemMutexCmsis.h" + + +void SystemMutexCmsis_init(SystemMutexCmsis *env, const osMutexAttr_t *attr) { + *env = osMutexNew(attr); +} + +static bool SystemMutexCmsis_acquire(SystemMutexCmsis *env, int32_t timeout) { + return osMutexAcquire(*env, timeout) == osOK; +} + +static bool SystemMutexCmsis_release(SystemMutexCmsis *env, const osMutexAttr_t *attr) { + (void)(attr); + return osMutexRelease(*env) == osOK; +} + + +tSystemMutexInterface SystemMutexCmsis_getInterface(SystemMutexCmsis *env) { + return (tSystemMutexInterface) { + .env = env, + .acquire = (void *) SystemMutexCmsis_acquire, + .release = (void *) SystemMutexCmsis_release, + }; +} + diff --git a/MODULES/VarTabDumpObserver/VarTabDumpObserver.c b/MODULES/VarTabDumpObserver/VarTabDumpObserver.c new file mode 100644 index 0000000..d64d1b5 --- /dev/null +++ b/MODULES/VarTabDumpObserver/VarTabDumpObserver.c @@ -0,0 +1,255 @@ +// +// Created by cfif on 19.12.22. +// + +#include +#include "VarsTabDumpObserver.h" +#include "SystemDelayInterface.h" +#include "string.h" +#include "StorageOnFlashFlagchip.h" + + +#define LOGGER env->logger +#define LOG_SIGN "Storage" + +void VarsTabDumpObserver_Init( + tVarsTabDumpObserver *env, + tStorageInterface *storageCalibInterface, + tStorageInterface *storageParamInterface, + uint32_t delay, + void *dataCalib, + void *dataParam, + size_t sizeCalib, + size_t sizeParam, + uint8_t *trackableVarsTab, + uint32_t trackableGroup, + tLoggerInterface *logger +) { + env->logger = logger; + + env->interfaceCalib = storageCalibInterface; + env->interfaceParam = storageParamInterface; + + env->trackableVarsTab = trackableVarsTab; + env->trackableGroup = trackableGroup; + + env->dataCalib = dataCalib; + env->sizeCalib = sizeCalib; + + env->dataParam = dataParam; + env->sizeParam = sizeParam; + + env->delay = delay; + env->dumpAfter = 0; + env->access = osMutexNew(NULL); + env->accessDumper = osMutexNew(NULL); + + InitThreadAtrStatic(&env->thread.attr, "Data", env->thread.controlBlock, env->thread.stack, osPriorityNormal); + env->thread.id = 0; + +} + +bool VarsTabDumpObserverCalib_Load(tVarsTabDumpObserver *env) { + + if (osMutexAcquire(env->accessDumper, 1000) == osOK) { + eStorageStatus dumpStatus = StorageLoad(env->interfaceCalib, env->dataCalib, env->sizeCalib); + osMutexRelease(env->accessDumper); + + if (dumpStatus == STORAGE_ERR_DEVICE) { + LoggerInfoStatic(LOGGER, LOG_SIGN, "Calibration: ROM error") + env->health = false; + return false; + } else if (dumpStatus == STORAGE_OK) { + env->health = true; + LoggerInfoStatic(LOGGER, LOG_SIGN, "Calibrations: Data successfully loaded from ROM") + return true; + } + LoggerInfoStatic(LOGGER, LOG_SIGN, "Calibration: Data error when loading from ROM") + return false; + } else { + LoggerErrorStatic(LOGGER, LOG_SIGN, "Calibration: ROM read error") + LoggerErrorStatic(LOGGER, LOG_SIGN, "Calibrations: Parallel access error") + return false; + } + +} + +bool VarsTabDumpObserverParam_Load(tVarsTabDumpObserver *env) { + + if (osMutexAcquire(env->accessDumper, 1000) == osOK) { + eStorageStatus dumpStatus = StorageLoad(env->interfaceParam, env->dataParam, env->sizeParam); + osMutexRelease(env->accessDumper); + + if (dumpStatus == STORAGE_ERR_DEVICE) { + LoggerInfoStatic(LOGGER, LOG_SIGN, "Parameters: ROM error") + env->health = false; + return false; + } else if (dumpStatus == STORAGE_OK) { + env->health = true; + LoggerInfoStatic(LOGGER, LOG_SIGN, "Parameters: Data successfully loaded from ROM") + return true; + } + LoggerInfoStatic(LOGGER, LOG_SIGN, "Parameters: Data error while loading from ROM") + return false; + } else { + LoggerErrorStatic(LOGGER, LOG_SIGN, "Parameters: ROM read error.") + LoggerErrorStatic(LOGGER, LOG_SIGN, "Parameters: Concurrent access error") + return false; + } + +} + +bool VarsTabDumpObserverCalib_Dump(tVarsTabDumpObserver *env) { + LoggerInfoStatic(LOGGER, LOG_SIGN, "Calibrations: Attempting to write to ROM") + + tStorageOnFlashFlagchip *storageOnFlashChipsCheckClear = env->interfaceCalib->env; + + int isMainFlashPageAddressCheckClear = memcmp((uint8_t *) storageOnFlashChipsCheckClear->mainFlashPageAddress, + env->dataCalib, env->sizeCalib - 8); + + int isRecoveryFlashPageAddressCheckClear = memcmp( + (uint8_t *) storageOnFlashChipsCheckClear->recoveryFlashPageAddress, env->dataCalib, env->sizeCalib - 8); + + if ((isMainFlashPageAddressCheckClear == 0) && (isRecoveryFlashPageAddressCheckClear == 0)) { + LoggerInfoStatic(LOGGER, LOG_SIGN, "Calibrations: No need to write to ROM") + return true; + } + + if (osMutexAcquire(env->accessDumper, 1000) == osOK) { + + eStorageStatus result = StorageDump(env->interfaceCalib, env->dataCalib, env->sizeCalib); + + osMutexRelease(env->accessDumper); + + env->health = (result == STORAGE_OK); + + if (env->health) { + LoggerInfoStatic(LOGGER, LOG_SIGN, "Calibrations: Successfully written to ROM") + return true; + } else { + LoggerErrorStatic(LOGGER, LOG_SIGN, "Calibration: ROM write error") + if (result == STORAGE_ERR_DATA) { + LoggerErrorStatic(LOGGER, LOG_SIGN, "Calibration: Checksum error") + } else { + LoggerErrorStatic(LOGGER, LOG_SIGN, "Calibration: ROM error") + } + return false; + } + + } else { + LoggerErrorStatic(LOGGER, LOG_SIGN, "Calibration: ROM write error") + LoggerErrorStatic(LOGGER, LOG_SIGN, "Calibrations: Parallel access error") + return false; + } +} + + +bool VarsTabDumpObserverParam_Dump(tVarsTabDumpObserver *env) { + LoggerInfoStatic(LOGGER, LOG_SIGN, "Parameters: Attempting to write to ROM") + + tStorageOnFlashFlagchip *storageOnFlashChipsCheckClear = env->interfaceParam->env; + + int isMainFlashPageAddressCheckClear = memcmp((uint8_t *) storageOnFlashChipsCheckClear->mainFlashPageAddress, + env->dataParam, env->sizeParam - 8); + + int isRecoveryFlashPageAddressCheckClear = memcmp( + (uint8_t *) storageOnFlashChipsCheckClear->recoveryFlashPageAddress, env->dataParam, env->sizeParam - 8); + + if ((isMainFlashPageAddressCheckClear == 0) && (isRecoveryFlashPageAddressCheckClear == 0)) { + LoggerInfoStatic(LOGGER, LOG_SIGN, "Parameters: No need to write to ROM") + return true; + } + + if (osMutexAcquire(env->accessDumper, 1000) == osOK) { + + eStorageStatus result = StorageDump(env->interfaceParam, env->dataParam, env->sizeParam); + + osMutexRelease(env->accessDumper); + + env->health = (result == STORAGE_OK); + + if (env->health) { + LoggerInfoStatic(LOGGER, LOG_SIGN, "Parameters: Successfully written to ROM") + return true; + } else { + LoggerErrorStatic(LOGGER, LOG_SIGN, "Parameters: Error writing to ROM") + if (result == STORAGE_ERR_DATA) { + LoggerErrorStatic(LOGGER, LOG_SIGN, "Parameters: Checksum error") + } else { + LoggerErrorStatic(LOGGER, LOG_SIGN, "Parameters: ROM error") + } + return false; + } + + } else { + LoggerErrorStatic(LOGGER, LOG_SIGN, "Parameters: Error writing to ROM") + LoggerErrorStatic(LOGGER, LOG_SIGN, "Parameters: Concurrency error") + return false; + } +} + + +static bool VarsTabDumpObserver_IsNowDumpRequired(tVarsTabDumpObserver *env) { + return env->dumpAfter < SystemGetMs(); +} + +void VarsTabDumpObserver_RequireDump(tVarsTabDumpObserver *env) { + if (osMutexAcquire(env->access, 1000) == osOK) { + env->dumpAfter = SystemGetMs() + env->delay; + osMutexRelease(env->access); + } else { + LoggerErrorStatic(LOGGER, LOG_SIGN, "Access error VarsTabDumpObserver_RequireDump"); + } +} + +void DeviceStorageProcessing(tVarsTabDumpObserver *env) { + if (*env->trackableVarsTab) { + *env->trackableVarsTab = 0; + LoggerInfoStatic(LOGGER, LOG_SIGN, "Changes in parameters detected, writing to ROM is required") + VarsTabDumpObserver_RequireDump(env); + } + + if (env->dumpAfter && VarsTabDumpObserver_IsNowDumpRequired(env)) { + if (osMutexAcquire(env->access, 1000) == osOK) { + if (VarsTabDumpObserver_IsNowDumpRequired(env)) { + VarsTabDumpObserverParam_Dump(env); + env->dumpAfter = 0; + } + osMutexRelease(env->access); + } else { + LoggerErrorStatic(LOGGER, LOG_SIGN, "Access error DeviceStorageProcessing"); + } + } +} + +static _Noreturn void VarsTabDumpObserver_Thread(tVarsTabDumpObserver *env) { + for (;;) { + DeviceStorageProcessing(env); + SystemDelayMs(100); + } +} + +void VarsTabDumpObserver_StartThread(tVarsTabDumpObserver *env) { + ThreadBlock_Start(env->thread, env, VarsTabDumpObserver_Thread); +} + +void VarsTabDumpObserver_StopThread(tVarsTabDumpObserver *env) { + ThreadBlock_Stop(env->thread); +} + + +void VarsTabDumpObserver_Flush(tVarsTabDumpObserver *env) { + if (env->dumpAfter) { + LoggerInfoStatic(LOGGER, LOG_SIGN, "There are changes, we write them to ROM") + if (osMutexAcquire(env->access, 10000) == osOK) { + VarsTabDumpObserverParam_Dump(env); + env->dumpAfter = 0; + osMutexRelease(env->access); + } else { + LoggerErrorStatic(LOGGER, LOG_SIGN, "Access error VarsTabDumpObserver_Flush"); + } + } +} + + + diff --git a/MODULES/VarTabDumpObserver/VarsTabDumpObserver.h b/MODULES/VarTabDumpObserver/VarsTabDumpObserver.h new file mode 100644 index 0000000..402f7e3 --- /dev/null +++ b/MODULES/VarTabDumpObserver/VarsTabDumpObserver.h @@ -0,0 +1,65 @@ +// +// Created by CFIF on 19.12.22. +// + +#ifndef HVAC_VarsTabDumpOBSERVER_H +#define HVAC_VarsTabDumpOBSERVER_H + +#include +#include "LoggerInterface.h" + +typedef struct { + tLoggerInterface *logger; + tStorageInterface *interfaceCalib; + tStorageInterface *interfaceParam; + uint8_t *trackableVarsTab; + uint32_t trackableGroup; + void *dataCalib; + void *dataParam; + size_t sizeCalib; + size_t sizeParam; + + bool health; + + osMutexId_t access; + osMutexId_t accessDumper; + uint32_t dumpAfter; + uint32_t delay; + + struct { + osThreadId_t id; + uint32_t stack[384]; + StaticTask_t controlBlock; + osThreadAttr_t attr; + } thread; +} tVarsTabDumpObserver; + +void VarsTabDumpObserver_Init( + tVarsTabDumpObserver *env, + tStorageInterface *storageCalibInterface, + tStorageInterface *storageParamInterface, + uint32_t delay, + void *dataCalib, + void *dataParam, + size_t sizeCalib, + size_t sizeParam, + uint8_t *trackableVarsTab, + uint32_t trackableGroup, + tLoggerInterface *logger +); + +bool VarsTabDumpObserverCalib_Load(tVarsTabDumpObserver *env); +bool VarsTabDumpObserverParam_Load(tVarsTabDumpObserver *env); + +bool VarsTabDumpObserverCalib_Dump(tVarsTabDumpObserver *env); +bool VarsTabDumpObserverParam_Dump(tVarsTabDumpObserver *env); + +void VarsTabDumpObserver_RequireDump(tVarsTabDumpObserver *env); + +void VarsTabDumpObserver_StartThread(tVarsTabDumpObserver *env); + +void VarsTabDumpObserver_StopThread(tVarsTabDumpObserver *env); + +void VarsTabDumpObserver_Flush(tVarsTabDumpObserver *env); + +#endif //HVAC_VarsTabDumpOBSERVER_H diff --git a/MODULES/VarTabDumpObserver/modular.json b/MODULES/VarTabDumpObserver/modular.json new file mode 100644 index 0000000..0dd1901 --- /dev/null +++ b/MODULES/VarTabDumpObserver/modular.json @@ -0,0 +1,10 @@ +{ + "cmake": { + "inc_dirs": [ + "./" + ], + "srcs": [ + "./**.c" + ] + } +} \ No newline at end of file diff --git a/WORK/HVAC_CALIB.bin b/WORK/HVAC_CALIB.bin new file mode 100644 index 0000000..e64ee18 Binary files /dev/null and b/WORK/HVAC_CALIB.bin differ diff --git a/WORK/HVAC_M7.bin b/WORK/HVAC_M7.bin new file mode 100755 index 0000000..fb123f0 Binary files /dev/null and b/WORK/HVAC_M7.bin differ diff --git a/WORK/HVAC_MAIN.bin b/WORK/HVAC_MAIN.bin new file mode 100644 index 0000000..09d0ebe Binary files /dev/null and b/WORK/HVAC_MAIN.bin differ diff --git a/WORK/create.sh b/WORK/create.sh new file mode 100755 index 0000000..5c84d51 --- /dev/null +++ b/WORK/create.sh @@ -0,0 +1,79 @@ +#!/bin/bash +echo "=== Processing HVAC Firmware ===" + +# Разделение файла +./fc_bin_hvac --split 0xB0000 --output1 HVAC_MAIN.bin --output2 HVAC_CALIB.bin HVAC_M7.bin && \ +echo "✓ Split OK" || { echo "✗ Split failed"; exit 1; } + +# Запись CRC в MAIN файл +./fc_bin_hvac -w HVAC_MAIN.bin && \ +echo "✓ CRC MAIN written" || { echo "✗ CRC MAIN write failed"; exit 1; } + +# Проверка CRC MAIN файла +echo -e "\n--- Verifying CRC for MAIN ---" +./fc_bin_hvac -c HVAC_MAIN.bin +if [ $? -eq 0 ]; then + echo "✓ CRC MAIN verification PASSED" +else + echo "✗ CRC MAIN verification FAILED" + exit 1 +fi + +# Запись CRC в CALIB файл +./fc_bin_hvac -w HVAC_CALIB.bin && \ +echo "✓ CRC CALIB written" || { echo "✗ CRC CALIB write failed"; exit 1; } + +# Проверка CRC CALIB файла +echo -e "\n--- Verifying CRC for CALIB ---" +./fc_bin_hvac -c HVAC_CALIB.bin +if [ $? -eq 0 ]; then + echo "✓ CRC CALIB verification PASSED" +else + echo "✗ CRC CALIB verification FAILED" + exit 1 +fi + + + +# Запись CRC в BOOT файл +./fc_bin_hvac -w HVAC_BOOT_OTA_M7.bin && \ +echo "✓ CRC BOOT written" || { echo "✗ CRC BOOT write failed"; exit 1; } + +# Проверка CRC BOOT файла +echo -e "\n--- Verifying CRC for BOOT ---" +./fc_bin_hvac -c HVAC_BOOT_OTA_M7.bin +if [ $? -eq 0 ]; then + echo "✓ CRC BOOT verification PASSED" +else + echo "✗ CRC BOOT verification FAILED" + exit 1 +fi + + + + + + + +# Конвертация в HEX +echo -e "\n--- Converting to HEX ---" +objcopy -I binary -O ihex --change-addresses 0x01010000 HVAC_MAIN.bin HVAC_MAIN.hex && \ +echo "✓ HEX MAIN OK" || echo "✗ HEX MAIN failed" + +objcopy -I binary -O ihex --change-addresses 0x010C0000 HVAC_CALIB.bin HVAC_CALIB.hex && \ +echo "✓ HEX CALIB OK" || echo "✗ HEX CALIB failed" + +objcopy -I binary -O ihex --change-addresses 0x01000000 HVAC_BOOT_OTA_M7.bin HVAC_BOOT_OTA_M7.hex && \ +echo "✓ HEX BOOT OK" || echo "✗ HEX BOOT failed" + +echo -e "\n=== All operations completed ===" +ls -lh *.bin *.hex + +# Дополнительная финальная проверка всех CRC +echo -e "\n=== Final CRC Verification ===" +echo "MAIN file CRC:" +./fc_bin_hvac -s HVAC_MAIN.bin +echo -e "\nCALIB file CRC:" +./fc_bin_hvac -s HVAC_CALIB.bin +echo -e "\nBOOT file CRC:" +./fc_bin_hvac -s HVAC_BOOT_OTA_M7.bin \ No newline at end of file diff --git a/WORK/fc_bin_hvac b/WORK/fc_bin_hvac new file mode 100755 index 0000000..983d8b9 Binary files /dev/null and b/WORK/fc_bin_hvac differ diff --git a/modular.json b/modular.json new file mode 100644 index 0000000..126a2d2 --- /dev/null +++ b/modular.json @@ -0,0 +1,501 @@ +{ + "dep": [ + + { + "type": "local", + + "dir": "./MODULES/CmakeConfig_RandomBuildIdGenerator" + }, + + { + "type": "local", + "dir": "./MODULES/FreeRTOS" + }, + + { + "type": "local", + "dir": "./MODULES/FreeRTOSPortable_GCC_CM7" + }, + + { + "type": "local", + "dir": "./MODULES/CmsisRtosInterface" + }, + + { + "type": "local", + "dir": "./MODULES/FreeRTOSCmsis" + }, + + + + + + { + "type": "local", + + "dir": "./MODULES/CmakeConfig_GCC_CortexM7" + }, + + + + { + "type": "local", + + "dir": "./MODULES/FreeRTOSHeap4" + }, + { + "type": "local", + + "dir": "./MODULES/SystemDelay_CMSIS_RTOS" + }, + { + "type": "local", + + "dir": "./MODULES/SystemSync_CMSIS_RTOS" + }, + { + "type": "local", + + "dir": "./MODULES/SystemDelayInterface" + }, + { + "type": "local", + + "dir": "./MODULES/CmsisRtosThreadUtils" + }, + { + "type": "local", + + "dir": "./MODULES/PeripheralDriver_Flagchip_FC7240" + }, + + { + "type": "local", + + "dir": "./MODULES/Device_Flagchip_FC7240" + }, + + { + "type": "local", + + "dir": "./MODULES/HwA_Flagchip_FC7240" + }, + + { + "type": "local", + + "dir": "./MODULES/HVAC_M7_GpioPins" + }, + + { + "type": "local", + + "dir": "./MODULES/HVAC_M7_SerialPorts" + }, + + { + "type": "local", + + "dir": "./MODULES/SerialPort_Flagchip_FC7240" + }, + + { + "type": "local", + + "dir": "./MODULES/SerialPort_P2P_CmsisRtos" + }, + + { + "type": "local", + + "dir": "./MODULES/HVAC_M7_DebugTesting" + }, + + + { + "type": "local", + + "dir": "./MODULES/HVAC_M7_Indication" + }, + + + { + "type": "local", + + "dir": "./MODULES/BaseTypes" + }, + + { + "type": "local", + + "dir": "./MODULES/LoggerToSerialPort" + }, + + { + "type": "local", + + "dir": "./MODULES/HVAC_M7_PowerManagement" + }, + + { + "type": "local", + + "dir": "./MODULES/HVAC_M7_Command" + }, + + { + "type": "local", + + "dir": "./MODULES/HVAC_M7_Rtcs" + }, + + + { + "type": "local", + + "dir": "./MODULES/Rtc_Flagchip_FC7240" + }, + + { + "type": "local", + + "dir": "./MODULES/FirmwareMetadataSection" + }, + + { + "type": "local", + + "dir": "./MODULES/CanSerialPortFrame_Flagchip_FC7240" + }, + + { + "type": "local", + + "dir": "./MODULES/HVAC_M7_CanPorts" + }, + + { + "type": "local", + + "dir": "./MODULES/Adc_Flagchip_FC7240" + }, + + { + "type": "local", + + "dir": "./MODULES/HVAC_M7_Adcs" + }, + + { + "type": "local", + + "dir": "./MODULES/Pwm_Flagchip_FC7240" + }, + { + "type": "local", + + "dir": "./MODULES/PwmInterface" + }, + + { + "type": "local", + + "dir": "./MODULES/HVAC_M7_Pwms" + }, + + { + "type": "local", + + "dir": "./MODULES/Lin_Flagchip_FC7240" + }, + + { + "type": "local", + + "dir": "./MODULES/HVAC_M7_Lins" + }, + + { + "type": "local", + + "dir": "./MODULES/HVAC_M7_DataNonVolatile" + }, + + { + "type": "local", + + "dir": "./MODULES/HVAC_M7_DataRuntime" + }, + + + { + "type": "local", + + "dir": "./MODULES/HVAC_M7_DeviceStorage" + }, + + { + "type": "local", + + "dir": "./MODULES/StorageOnFlash_Flagchip_FC7240" + }, + + { + "type": "local", + + "dir": "./MODULES/InternalFlashPage_Flagchip_FC7240" + }, + + { + "type": "local", + + "dir": "./MODULES/VarTabDumpObserver" + }, + + { + "type": "local", + + "dir": "./MODULES/HVAC_M7_StorageOnFlash" + }, + + { + "type": "local", + + "dir": "./MODULES/SerialPortCan" + }, + + { + "type": "local", + + "dir": "./MODULES/CanSerialPortFrame_XCP" + }, + + + { + "type": "local", + + "dir": "./MODULES/HVAC_M7_CAN_MATRIX" + }, + + { + "type": "local", + + "dir": "./MODULES/HVAC_M7_CAN_SPAM" + }, + + { + "type": "local", + + "dir": "./MODULES/HVAC_M7_LIN_TASKS" + }, + + { + "type": "local", + + "dir": "./MODULES/HVAC_M7_ADC_TEMP" + }, + + + { + "type": "local", + + "dir": "./MODULES/HVAC_M7_StatusData" + }, + + { + "type": "local", + + "dir": "./MODULES/SerialPort_Virt_CmsisRtos" + }, + + { + "type": "local", + + "dir": "./MODULES/HVAC_M7_ADC_TASKS" + }, + + + { + "type": "local", + + "dir": "./MODULES/HVAC_M7_SMC" + }, + + { + "type": "local", + + "dir": "./MODULES/HVAC_M7_MODEL" + }, + + + { + "type": "local", + + "dir": "./MODULES/PwmCapture_Flagchip_FC7240" + }, + + { + "type": "local", + + "dir": "./MODULES/CanSerialPortFrame_TP" + }, + + { + "type": "local", + + "dir": "./MODULES/HVAC_M7_CAN_UDS" + }, + + + { + "type": "local", + + "dir": "./MODULES/HVAC_M7_CAN_DBG_MATRIX" + }, + + { + "type": "local", + + "dir": "./MODULES/HVAC_M7_CAN_DEBUG_SPAM" + }, + + { + "type": "local", + + "dir": "./MODULES/BootJump_Flagchip_FC7240" + }, + + + { + "type": "local", + + "dir": "./MODULES/HVAC_M7_CRC32" + }, + + { + "type": "local", + + "dir": "./MODULES/HVAC_M7_DOC" + }, + + { + "type": "local", + + "dir": "./MODULES/HVAC_M7_HardFault" + }, + + + + + + + + + { + "type": "local", + "dir": "./MODULES/SystemSyncInterface" + }, + + { + "type": "local", + "dir": "./MODULES/GpioPinInterface" + }, + + { + "type": "local", + "dir": "./MODULES/GpioPin_Flagchip_FC7240" + }, + + { + "type": "local", + "dir": "./MODULES/SerialPortInterface" + }, + + { + "type": "local", + "dir": "./MODULES/SerialPort_Flagchip_FC7240" + }, + + { + "type": "local", + "dir": "./MODULES/LoggerInterface" + }, + + { + "type": "local", + "dir": "./MODULES/SerialPort" + }, + + { + "type": "local", + "dir": "./MODULES/LoggerInterface" + }, + + { + "type": "local", + "dir": "./MODULES/RtcInterface" + }, + + { + "type": "local", + "dir": "./MODULES/AsciiStringAssemblingUtils" + }, + + { + "type": "local", + "dir": "./MODULES/SerialPortFrameInterface" + }, + + { + "type": "local", + "dir": "./MODULES/Rtc" + }, + + { + "type": "local", + "dir": "./MODULES/CliCmd" + }, + + { + "type": "local", + "dir": "./MODULES/CliCmd_RedirectTable" + }, + + { + "type": "local", + "dir": "./MODULES/AdcInterface" + }, + + { + "type": "local", + "dir": "./MODULES/StorageInterface" + }, + + { + "type": "local", + "dir": "./MODULES/LinInterface" + }, + + { + "type": "local", + "dir": "./MODULES/LinInterface" + }, + + { + "type": "local", + "dir": "./MODULES/AsciiStringParsingUtils" + }, + + { + "type": "local", + "dir": "./MODULES/Adc" + }, + + { + "type": "local", + "dir": "APP" + } + ] +} + diff --git a/modular.py b/modular.py new file mode 100644 index 0000000..816b44d --- /dev/null +++ b/modular.py @@ -0,0 +1,666 @@ +#!/usr/bin/python3 +import subprocess +import sys +import argparse +import os +import json +import platform +import re +import shutil +from datetime import datetime + + +def get_git_revision_hash(path=None) -> str: + if path: + # git -C + # Runs the command as if git was started in instead of the current working directory. + # return subprocess.check_output(['git', '-C', path, 'rev-parse', 'HEAD']).decode('ascii').strip() + stdout = subprocess.run(['git', '-C', path, 'rev-parse', 'HEAD'], + check=True, capture_output=True, text=True).stdout.strip() + return stdout + else: + # return subprocess.check_output(['git', 'rev-parse', 'HEAD']).decode('ascii').strip() + stdout = subprocess.run(['git', 'rev-parse', 'HEAD'], + check=True, capture_output=True, text=True).stdout.strip() + return stdout + + +class DependencyType: + local = 'local' + git = 'git' + + +class Module: + # raw - это прочитанный json в виде словаря + def __init__(self, raw=None): + self.cmake = {'inc': [], 'src': [], 'inc_dirs': [], 'srcs': [], 'libs': [], 'uis': []} + self.dep = [] # список из объектов Dependency + self.raw = raw + + if raw: + if 'cmake' in raw: + if 'inc_dirs' in raw['cmake']: + self.cmake['inc_dirs'] = raw['cmake']['inc_dirs'] + if 'srcs' in raw['cmake']: + self.cmake['srcs'] = raw['cmake']['srcs'] + if 'libs' in raw['cmake']: + self.cmake['libs'] = raw['cmake']['libs'] + if 'uis' in raw['cmake']: + self.cmake['uis'] = raw['cmake']['uis'] + if 'dep' in raw: + self.dep = [Dependency(rawDep) for rawDep in raw['dep']] + + def __str__(self): + return str(self.cmake) + + def __repr__(self): + return self.__str__() + + def __eq__(self, other): + if not isinstance(other, type(self)): + return False + return self.cmake == other.cmake and self.dep == other.dep + + +class Dependency: + # raw - это словарь + def __init__(self, raw): + if raw: + if raw['type'] == DependencyType.local: + self.type = DependencyType.local + self.dir = raw.get('dir', '') + self.os = raw.get('os', '') + elif raw['type'] == DependencyType.git: + self.type = DependencyType.git + self.provider = raw.get('provider', '') + self.dir = raw.get('dir', '') + self.repo = raw.get('repo', '') + self.commit = raw.get('commit', '') + self.os = raw.get('os', '') + self.project = raw.get('project', 'false') + else: + raise ValueError('Unknown dependency ' + str(raw['type'])) + + def __eq__(self, other): + if self.type != other.type: + return False + + if self.type == DependencyType.local: + return self.dir == other.dir + elif self.type == DependencyType.git: + return self.repo == other.repo + else: + raise ValueError('Unknown dependency' + str(self.type)) + + def __str__(self): + if self.type == DependencyType.local: + return 'local ' + str(self.dir) + elif self.type == DependencyType.git: + return 'git ' + str(self.repo) + else: + raise ValueError('Unknown dependency' + str(self.type)) + + +class ModularProject: + # получить домашнюю директорию и приклеить к ней путь к modular_builder/config.json + userConfigFile = os.path.join(os.path.expanduser('~'), '.modular_builder', 'config.json') + + def __init__(self): + self.clear() + self.initDir() + self.loadConfigs() + + def clear(self): + self.loadedModules = [] + self.rules = {} + + def initDir(self): + if not os.path.exists('MODULES'): + print('No MODULES folder, creating...') + os.mkdir('MODULES') + print('Done') + + def loadConfigs(self): + if os.path.exists(self.userConfigFile): + print('Has config file at ' + str(self.userConfigFile) + ', loading...') + self.loadConfig(self.userConfigFile) + print('Done') + else: + print('No config file at ' + str(self.userConfigFile)) + + # в config.json лежит примерно это: + # { + # "git_providers:" { + # "rospron_modules": "http"//git...blabla.../rosprom_modules" + # } + # } + def loadConfig(self, config_path): + config = json.load(open(config_path, encoding='utf-8')) + self.gitProviders = config['git_providers'] + + def loadJsonAtPath(self, path): # path - путь до modular.json + print('loading json', path) + try: + with open(path, encoding='utf-8') as f: + result = Module(json.load(f)) + return result + except json.JSONDecodeError: + print('Error while reading json file at path:', path, file=sys.stderr) + print('Try fixing JSON file and run modular.py again', file=sys.stderr) + raise json.JSONDecodeError + + def downloadableModulePath(self, dependency): + if dependency.type == DependencyType.git: + if dependency.project == 'true': + return dependency.repo + else: + return os.path.join('MODULES', dependency.repo) + raise ValueError('UnknownDependency') + + def isGitModuleCloned(self, dependency): + return os.path.exists(self.downloadableModulePath(dependency)) + + def isModuleSystemAppropriate(self, dependency): + if not dependency.os: # если ОС не указана для модуля, то грузим его всегда + return True + elif dependency.os.lower() == 'windows': + print('Module only for Windows') + return platform.system().lower() == 'windows' + elif dependency.os.lower() == 'linux': + print('Module only for Linux') + return platform.system().lower() == 'linux' + else: + print('Unknown OS:', dependency.os) + print('Dependency will be uploaded anyway') + return True + + def cloneGitDependency(self, dependency): + path = self.downloadableModulePath(dependency) + clone_cmd = 'git clone ' + str(self.gitProviders[dependency.provider]) + '/' + str(dependency.repo) + ' ' + str( + path) + print('Clone with', clone_cmd) + os.system(clone_cmd) # выполняет любые поддерживаемые команды в командной строке + + if dependency.commit: + checkout_cmd = f'git -C {path} checkout {dependency.commit}' + # git -C + # Runs the command as if git was started in instead of the current working directory. + print(f'Checkout with {checkout_cmd}') + os.system(checkout_cmd) # выполняет любые поддерживаемые команды в командной строке + + def loadDependency(self, dependency): + if self.checkDependencyCollision(dependency): + return [] + print('\nLoading module', dependency) + if dependency.type == DependencyType.local: + return self.loadDependencyFromLocal(dependency) + elif dependency.type == DependencyType.git: + return self.loadDependencyFromGit(dependency) + else: + raise ValueError('Unknown module') + + def loadDependencyFromLocal(self, dependency): + if self.isModuleSystemAppropriate(dependency): + return self.loadDependencyFromDir(dependency.dir) + + def loadDependencyFromGit(self, dependency): + if self.isModuleSystemAppropriate(dependency): + if not self.isGitModuleCloned(dependency): + self.cloneGitDependency(dependency) + return self.loadDependencyFromDir(self.downloadableModulePath(dependency)) + + def loadDependencyFromDir(self, modular_dir): + modular_json_path = os.path.join(modular_dir, 'modular.json') + + if not os.path.exists(modular_json_path): + print('Directory in not a module:', modular_dir) + return [] + + # module_relative - объект класса Module, внутри него в списке dep хранятся прочитанные из json объекты Dependency + module_relative = self.loadJsonAtPath(modular_json_path) + project_relative = Module() + + print('module_relative:', module_relative) + print(module_relative.cmake) + + result_inc_dirs = self.addRootToPaths(modular_dir, module_relative.cmake.get('inc_dirs', '')) + project_relative.cmake['inc_dirs'] = result_inc_dirs + result_srcs = self.addRootToPaths(modular_dir, module_relative.cmake.get('srcs', '')) + project_relative.cmake['srcs'] = result_srcs + result_libs = self.addRootToPaths(modular_dir, module_relative.cmake.get('libs', '')) + project_relative.cmake['libs'] = result_libs + result_uis = self.addRootToPaths(modular_dir, module_relative.cmake.get('uis', '')) + project_relative.cmake['uis'] = result_uis + + # После выполнения строки ниже в project_relative.dep окажется просто + # список Dependency, который и был в module_relative.dep. + # (Это список модулей, от которых текущий модуль зависит. Их надо будет докачать) + project_relative.dep = self.addRootToDeps(modular_dir, module_relative.dep) + + sub_modules = [] + for dependency in project_relative.dep: + loaded_dependencies = self.loadDependency(dependency) + if loaded_dependencies: + # sub_modules.extend(loaded_dependencies) + # чтобы не было повторений + for dep_loaded in loaded_dependencies: + if dep_loaded not in sub_modules: + sub_modules.append(dep_loaded) + else: + print('Nothing to download, continuing') + + sub_modules.append(project_relative) + print('sub_modules', sub_modules) + return sub_modules + + def addRootToPaths(self, root, paths): + if not paths: + return [] + result = [] + for pth in paths: + if os.path.isabs(pth): # если путь абсолютный + result.append(pth) + else: + if pth.startswith('./'): # если текущий путь начинается с текущей папки, то убери ее + pth = pth[2:] + result.append(os.path.join(root, pth)) + return result + + # эта функция возвращает просто список объектов Dependency + def addRootToDeps(self, root, deps): + result = [] + for dep in deps: + if dep.type == DependencyType.local: + if not os.path.isabs(dep.dir): + dep.dir = os.path.join(root, dep.dir) + result.append(dep) + return result + + def download(self): + # self.modules - это список из объектов Dependency + self.modules = self.loadDependency(Dependency({'type': 'local', 'dir': './'})) + + print('modules: ') + print(self.modules) + + def replace_slashes(self, path): + return path.replace('\\', '/') + + def genCmake(self): + cmakeText = '''function(add_sources FILE_LIST FILES_PATH) + file(GLOB_RECURSE ADD_FILES_LIST ${FILES_PATH}) + list(APPEND ${FILE_LIST} ${ADD_FILES_LIST}) + set(${FILE_LIST} ${${FILE_LIST}} PARENT_SCOPE) +endfunction()\n\n''' + + for module in self.modules: + for inc in module.cmake['inc_dirs']: + cmakeText += 'include_directories("' + str(inc) + '")\n' + cmakeText += '\n' + + for module in self.modules: + for src in module.cmake['srcs']: + cmakeText += 'add_sources(SOURCES "' + str(src) + '")\n' + cmakeText += '\n' + + for module in self.modules: + for lib in module.cmake['libs']: + cmakeText += 'add_sources(LIBRARIES "' + str(lib) + '")\n' + cmakeText += '\n' + + for module in self.modules: + for ui in module.cmake['uis']: + cmakeText += 'add_sources(UIS "' + str(ui) + '")\n' + cmakeText += '\n' + + # заменяем обратный слеш на прямой, так как винда склеивает своими слешами, но их не поинмает компилятор: + cmakeText = self.replace_slashes(cmakeText) + print(cmakeText) + with open('modular.cmake', 'w', encoding='utf-8') as file: + file.write(cmakeText) + + def genCmakeForLibrify(self): + other_path, project_name = os.path.split(os.getcwd()) + cmakeText = '''cmake_minimum_required(VERSION 3.17) +project(''' + project_name + ''') +set(CMAKE_C_STANDARD 11) + +function(add_sources FILE_LIST FILES_PATH) + file(GLOB ADD_FILES_LIST ${FILES_PATH}) + list(APPEND ${FILE_LIST} ${ADD_FILES_LIST}) + set(${FILE_LIST} ${${FILE_LIST}} PARENT_SCOPE) +endfunction()\n\n''' + + for module in self.modules: + for inc in module.cmake['inc_dirs']: + cmakeText += 'include_directories("' + str(inc) + '")\n' + cmakeText += '\n' + + module = self.modules[-1] # берем только главный (корневой) модуль + for src in module.cmake['srcs']: + cmakeText += 'add_sources(SOURCES "' + str(src) + '")\n' + cmakeText += '\n' + + for module in self.modules: + for lib in module.cmake['libs']: + cmakeText += 'add_sources(LIBRARIES "' + str(lib) + '")\n' + cmakeText += '\n' + + for module in self.modules: + for ui in module.cmake['uis']: + cmakeText += 'add_sources(UIS "' + str(ui) + '")\n' + cmakeText += '\n' + + cmakeText += 'add_library(' + project_name + ' ${SOURCES})\n' + + # заменяем обратный слеш на прямой, так как винда склеивает своими слешами, но их не поинмает компилятор: + cmakeText = self.replace_slashes(cmakeText) + print(cmakeText) + with open('modular.cmake', 'w', encoding='utf-8') as file: + file.write(cmakeText) + + def checkDependencyCollision(self, dependency): + """Возвращает True, если зависимость dependency уже есть среди загруженных модулей""" + # TODO проверка не работает, в self.loadedModules ничего не добавляется, коллизии происходят, ну и пофиг... + return any([loaded == dependency for loaded in self.loadedModules]) + + # def genEclipseXmlPart(self) - эта функция использоваться не будет + # def genExp32Cmake(self) - эта функция использоваться не будет + + def load_rules(self, config_path): + try: + rules = json.load(open(config_path, encoding='utf-8')) + except json.JSONDecodeError: + print('Error while reading json file at path:', config_path, file=sys.stderr) + print('Try fixing JSON file and run modular.py again', file=sys.stderr) + raise json.JSONDecodeError + if 'replacements' not in rules: + rules['replacements'] = {} + if 'filetypes' not in rules: + rules['filetypes'] = [".c", ".cpp", ".h"] # если типы файлов не указали, будем менять только в этих + if 'remove_comments' not in rules: + rules['remove_comments'] = False + if 'librify' not in rules: + rules['librify'] = [] + if 'ignore' not in rules: + rules['ignore'] = [] + + self.rules = rules + + def replacements_and_comments_deletion(self): + project_path = '.' + + def remove_comments_in_text(string): + pattern = r"(\".*?\"|\'.*?\')|(/\*.*?\*/|//[^\r\n]*$)" + # первая группа захватывает строки в кавычках (двойных или одинарных) + # вторая группа захватывает комментарии ( + regex = re.compile(pattern, re.MULTILINE | re.DOTALL) + + def _replacer(match): + # если вторая группа (захватывающая комменты) не None, + # значит, мы захватили не закавыченные (нормальные) комменты + if match.group(2) is not None: + return "" # возвращаем пустую строку для удаления коммента + else: # иначе возвращаем 1-ую группу + return match.group(1) # поймали "закавыченную" строку + + return regex.sub(_replacer, string) + + def remove_comments_in_file(filename): + with open(filename, 'r') as f: + content = f.read() + content_new = remove_comments_in_text(content) + with open(filename, 'w') as f: + f.write(content_new) + + def should_exclude_folder(project_path, dirpath, rules): + folder_fullpath = os.path.normpath(dirpath) + return any([folder_fullpath == os.path.normpath(os.path.join(project_path, ignore_path)) + for ignore_path in rules['ignore']]) + + def replace_occurrences_in_file(filename, rules): + with open(filename, 'r') as f: + content = f.read() + content_new = content + for (old_name, new_name) in rules['replacements'].items(): + content_new = re.sub(old_name, new_name, content_new) + with open(filename, 'w') as f: + f.write(content_new) + + for (dirpath, dirnames, filenames) in os.walk(project_path): + # print('*****', dirpath, dirnames, filenames) + if should_exclude_folder(project_path, dirpath, self.rules): + # если папка входит в игнорируемые, то пропускаем + print('Исключена папка:', dirpath) + continue + for file in filenames: + filename, file_extension = os.path.splitext(file) + if file_extension not in self.rules['filetypes']: + # если расширение не входит в список заданных, то пропускаем этот файт + continue + fullpath = os.path.join(dirpath, file) + print(fullpath) + if self.rules['remove_comments']: + remove_comments_in_file(fullpath) + replace_occurrences_in_file(fullpath, self.rules) + + def libraryfication(self): + initial_wd = os.getcwd() + """Собирает библиотеки из модулей в папках, указанных в self.rules["librify"] """ + if not os.path.exists('SHRINK'): + print('No SHRINK folder, creating...') + os.mkdir('SHRINK') + print('Done') + else: + print( + 'SHRINK folder already exists. Stopping. \n(If you want to generate libs, delete SHRINK folder first)') + return + + cmake_lists_text = '''include(../arch.cmake) + +function(add_sources FILE_LIST FILES_PATH) + file(GLOB_RECURSE ADD_FILES_LIST ${FILES_PATH}) + list(APPEND ${FILE_LIST} ${ADD_FILES_LIST}) +endfunction() + +include(modular.cmake) +''' + + for directory in self.rules["librify"]: + if not os.path.exists(directory): + print('Error! Directory from shrink.json does not exists:', directory) + raise FileNotFoundError + os.chdir(directory) # переходим в папку к этому модулю + + library_name = directory.split('/')[-1] + + config = json.load(open('modular.json', encoding='utf-8')) + for src in config['cmake']['srcs']: + cmake_lists_text += f'add_sources({library_name}_SOURCES "' + '../MODULES/' + library_name + '/' + src + '")\n' + + cmake_lists_text += 'add_library(' + library_name + ' ${' + library_name + '_SOURCES})' + os.chdir(initial_wd) # в конце не забываем вернуться в корневую папку проекта + + os.chdir('SHRINK') + with open('CMakeLists.txt', 'w', encoding='utf-8') as file: + file.write(cmake_lists_text) + + with open('modular.json', 'w') as new_modular: + modular_text = '''{ + "dep": [ + { + "type": "local", + "dir": "../" + } + ] +}''' + new_modular.write(modular_text) + result_run = subprocess.run(["modular.py", "-c"]) + os.mkdir('build') + os.chdir('build') + result_run = subprocess.run(["cmake", ".."]) + if result_run.returncode != 0: + print('cmake not successful. Stop') + raise RuntimeError('Previous cmake not successful. Stop') + result_run = subprocess.run(["make"]) + if result_run.returncode != 0: + print('make not successful. Stop') + raise RuntimeError('Previous make not successful. Stop') + # print('Result code of cmake:', result_run.returncode) + os.chdir('..') + os.chdir(initial_wd) + self.copy_all_libs_to_libs_folder() + + def copy_all_libs_to_libs_folder(self): + current_wd = os.path.abspath(os.getcwd()) + try: + if os.path.exists('libs'): + print('libs already exists') + else: + os.mkdir('libs') + dest_path = os.path.join(current_wd, 'libs') + os.chdir('SHRINK') + os.chdir('build') + + for (dirpath, dirnames, filenames) in os.walk('.'): + for file in filenames: + if file.endswith(".a"): + source_file_path = os.path.join(dirpath, file) + shutil.copy(source_file_path, dest_path) + + except FileNotFoundError as e: + print('Couldn\'t copy .a libs, error occurred!') + print(e) + os.chdir(current_wd) # возвращаемся в исходную папку + + def delete_sources_of_libraries(self): + current_wd = os.path.abspath(os.getcwd()) + for module_directory in self.rules["librify"]: + if not os.path.exists(module_directory): + print('Error! Directory from shrink.json does not exists:', module_directory) + raise FileNotFoundError + os.chdir(module_directory) + config = json.load(open('modular.json', encoding='utf-8')) + needed_dirs = config['cmake']['inc_dirs'] + all_dirs_files = [name for name in os.listdir(os.getcwd()) if + os.path.isdir(os.path.join(os.getcwd(), name))] + print('all files:', all_dirs_files) + for dir in all_dirs_files: + if dir not in needed_dirs: + print(f'remove dir {dir} in {os.path.join(current_wd, module_directory)}') + shutil.rmtree(dir) + os.chdir(current_wd) + + def delete_all_modular_json_files(self): + print('Starting to delete all modular.json...') + for (dirpath, dirnames, filenames) in os.walk('.'): + for file in filenames: + if str(file) == 'modular.json': + os.remove(os.path.join(dirpath, file)) + print('All modular.json files deleted from the project!') + + def shrink(self): + print('Start shrinking...') + self.load_rules('shrink.json') + self.replacements_and_comments_deletion() + self.libraryfication() + self.delete_sources_of_libraries() + self.delete_all_modular_json_files() + + print('Done shrinking') + + def create_release(self, tag=None): + """ + Сохраняет информацию о текущих версиях каждого из модулей в качестве релиза. + В результате в корне проекта создается файл с именем + :param tag: + :return: + """ + # without_duplicates = [] + # for module in self.modules: + # if module not in without_duplicates: + # without_duplicates.append(module) + # print(without_duplicates) + dependencies_without_duplicated = [] + for module in self.modules: + if module.dep: + for dep in module.dep: + if dep not in dependencies_without_duplicated: + dependencies_without_duplicated.append(dep) + # print(dependencies_without_duplicated) + + all_dependencies_for_project = {"dep": []} + for dep in dependencies_without_duplicated: + try: + path = os.path.join('MODULES', dep.repo) + commit_hash = get_git_revision_hash(path) + dep_json = { + "type": dep.type, + "provider": dep.provider, + "repo": dep.repo, + "commit": commit_hash + } + all_dependencies_for_project['dep'].append(dep_json) + except AttributeError as e: + pass # игнорим: 'Dependency' object has no attribute 'repo' (dep=local ./APP) + except Exception as e: + print(f'Случилось испключение: {e} (dep={dep})') + # print(all_dependencies_for_project) + + release_file_name = datetime.today().strftime('%d.%m.%Y_%H.%M') # + if tag: + release_file_name += '_' + tag + release_file_name += '_release.json' + with open(release_file_name, 'w', encoding='utf-8') as output_file: + json.dump(all_dependencies_for_project, output_file, ensure_ascii=False, indent=2) + print(f'Создан файл релиза: {release_file_name}') + + def checkout_release(self, json_name): + # with open(json_name, encoding='utf-8') as f: + # release_json = json.load(f) + print('Начинаем переход на указанные коммиты в релизе...') + module = self.loadJsonAtPath(json_name) + for dependency in module.dep: + if dependency.commit: + path = self.downloadableModulePath(dependency) + checkout_cmd = f'git -C {path} checkout {dependency.commit}' + # git -C + # Runs the command as if git was started in instead of the current working directory. + print(f'Checkout with {checkout_cmd}') + os.system(checkout_cmd) # выполняет любые поддерживаемые команды в командной строке + print(f'Вернули состояние проекта к релизной версии {json_name}') + + +parser = argparse.ArgumentParser() +parser.add_argument('-c', '--cmake', action='store_true', help='require generate cmake from modules') +parser.add_argument('-s', '--shrink', action='store_true', + help='Согласно правилам из shrink.json выполняет замены по RegEx и при "remove_comments": true удаляет все комментарии из кода') +parser.add_argument('-d', '--download', action='store_true', help='require download submodules') +parser.add_argument('wdir', help='path to working directory', type=str, default='./', nargs='?') +parser.add_argument('-r', '--release', action='store_true', + help='Отмечает текущее состояние проекта как релизное, создает соответствующий состоянию json') +parser.add_argument('--checkout', type=str, + help='Переходит в указанный релиз (выполняет checkout). Для релиза должен быть заранее создан релизный json') +argv = parser.parse_args() + +print('working directory', argv.wdir) + +os.chdir(argv.wdir) # изменить текущую рабочую директорию + +project = ModularProject() + +if argv.download or argv.cmake or argv.shrink: + project.download() +if argv.cmake: + project.genCmake() +if argv.shrink: + project.shrink() +if argv.release: + print('release') + project.download() + project.create_release() +if argv.checkout: + project.download() + project.checkout_release(argv.checkout) +# TODO: после checkout проекты будут в состоянии detached HEAH (оторванный указатель HEAD), +# и надо уметь какой-то командой возвращаться в исходную позицию (с учитыванием commit, указанного в самом проекте...) diff --git a/script.cfg b/script.cfg new file mode 100644 index 0000000..0d4e65e --- /dev/null +++ b/script.cfg @@ -0,0 +1,27 @@ +# +# This is an STM32F429 discovery board with a single STM32F429ZI chip. +# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/PF259090 +# + +source [find interface/atlink.cfg] + +#transport select hla_swd + +source [find target/flagchip/fc7240/fc7240f2m.cfg] + +#reset_config trst_only +#reset_config srst_only +#reset_config trst_and_srst +#reset_config srst_pulls_trst +#reset_config combined +#reset_config srst_gates_jtag +#reset_config trst_push_pull +#reset_config trst_push_pull + +reset_config none + +#reset_config [none|trst_only|srst_only|trst_and_srst] +#[srst_pulls_trst|trst_pulls_srst|combined|separate] +#[srst_gates_jtag|srst_nogate] [trst_push_pull|trst_open_drain] +#[srst_push_pull|srst_open_drain] +#[connect_deassert_srst|connect_assert_srst] \ No newline at end of file